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79e53945 | 1 | /* |
39507259 | 2 | * Copyright © 2006 Intel Corporation |
79e53945 JB |
3 | * |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, | |
20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE | |
21 | * SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | * | |
26 | */ | |
25e341cf | 27 | #include <linux/dmi.h> |
9f0e7ff4 | 28 | #include <drm/drm_dp_helper.h> |
760285e7 DH |
29 | #include <drm/drmP.h> |
30 | #include <drm/i915_drm.h> | |
79e53945 JB |
31 | #include "i915_drv.h" |
32 | #include "intel_bios.h" | |
33 | ||
9b9d172d | 34 | #define SLAVE_ADDR1 0x70 |
35 | #define SLAVE_ADDR2 0x72 | |
79e53945 | 36 | |
500a8cc4 ZW |
37 | static int panel_type; |
38 | ||
e8ef3b4c JN |
39 | static const void * |
40 | find_section(const void *_bdb, int section_id) | |
79e53945 | 41 | { |
e8ef3b4c JN |
42 | const struct bdb_header *bdb = _bdb; |
43 | const u8 *base = _bdb; | |
79e53945 JB |
44 | int index = 0; |
45 | u16 total, current_size; | |
46 | u8 current_id; | |
47 | ||
48 | /* skip to first section */ | |
49 | index += bdb->header_size; | |
50 | total = bdb->bdb_size; | |
51 | ||
52 | /* walk the sections looking for section_id */ | |
d1f13fd2 | 53 | while (index + 3 < total) { |
79e53945 JB |
54 | current_id = *(base + index); |
55 | index++; | |
d1f13fd2 | 56 | |
e8ef3b4c | 57 | current_size = *((const u16 *)(base + index)); |
79e53945 | 58 | index += 2; |
d1f13fd2 CW |
59 | |
60 | if (index + current_size > total) | |
61 | return NULL; | |
62 | ||
79e53945 JB |
63 | if (current_id == section_id) |
64 | return base + index; | |
d1f13fd2 | 65 | |
79e53945 JB |
66 | index += current_size; |
67 | } | |
68 | ||
69 | return NULL; | |
70 | } | |
71 | ||
db545019 | 72 | static u16 |
e8ef3b4c | 73 | get_blocksize(const void *p) |
db545019 DMEA |
74 | { |
75 | u16 *block_ptr, block_size; | |
76 | ||
77 | block_ptr = (u16 *)((char *)p - 2); | |
78 | block_size = *block_ptr; | |
79 | return block_size; | |
80 | } | |
81 | ||
79e53945 | 82 | static void |
88631706 | 83 | fill_detail_timing_data(struct drm_display_mode *panel_fixed_mode, |
99834ea4 | 84 | const struct lvds_dvo_timing *dvo_timing) |
88631706 ML |
85 | { |
86 | panel_fixed_mode->hdisplay = (dvo_timing->hactive_hi << 8) | | |
87 | dvo_timing->hactive_lo; | |
88 | panel_fixed_mode->hsync_start = panel_fixed_mode->hdisplay + | |
89 | ((dvo_timing->hsync_off_hi << 8) | dvo_timing->hsync_off_lo); | |
90 | panel_fixed_mode->hsync_end = panel_fixed_mode->hsync_start + | |
91 | dvo_timing->hsync_pulse_width; | |
92 | panel_fixed_mode->htotal = panel_fixed_mode->hdisplay + | |
93 | ((dvo_timing->hblank_hi << 8) | dvo_timing->hblank_lo); | |
94 | ||
95 | panel_fixed_mode->vdisplay = (dvo_timing->vactive_hi << 8) | | |
96 | dvo_timing->vactive_lo; | |
97 | panel_fixed_mode->vsync_start = panel_fixed_mode->vdisplay + | |
98 | dvo_timing->vsync_off; | |
99 | panel_fixed_mode->vsync_end = panel_fixed_mode->vsync_start + | |
100 | dvo_timing->vsync_pulse_width; | |
101 | panel_fixed_mode->vtotal = panel_fixed_mode->vdisplay + | |
102 | ((dvo_timing->vblank_hi << 8) | dvo_timing->vblank_lo); | |
103 | panel_fixed_mode->clock = dvo_timing->clock * 10; | |
104 | panel_fixed_mode->type = DRM_MODE_TYPE_PREFERRED; | |
105 | ||
9bc35499 AJ |
106 | if (dvo_timing->hsync_positive) |
107 | panel_fixed_mode->flags |= DRM_MODE_FLAG_PHSYNC; | |
108 | else | |
109 | panel_fixed_mode->flags |= DRM_MODE_FLAG_NHSYNC; | |
110 | ||
111 | if (dvo_timing->vsync_positive) | |
112 | panel_fixed_mode->flags |= DRM_MODE_FLAG_PVSYNC; | |
113 | else | |
114 | panel_fixed_mode->flags |= DRM_MODE_FLAG_NVSYNC; | |
115 | ||
88631706 ML |
116 | /* Some VBTs have bogus h/vtotal values */ |
117 | if (panel_fixed_mode->hsync_end > panel_fixed_mode->htotal) | |
118 | panel_fixed_mode->htotal = panel_fixed_mode->hsync_end + 1; | |
119 | if (panel_fixed_mode->vsync_end > panel_fixed_mode->vtotal) | |
120 | panel_fixed_mode->vtotal = panel_fixed_mode->vsync_end + 1; | |
121 | ||
122 | drm_mode_set_name(panel_fixed_mode); | |
123 | } | |
124 | ||
99834ea4 CW |
125 | static const struct lvds_dvo_timing * |
126 | get_lvds_dvo_timing(const struct bdb_lvds_lfp_data *lvds_lfp_data, | |
127 | const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs, | |
128 | int index) | |
129 | { | |
130 | /* | |
131 | * the size of fp_timing varies on the different platform. | |
132 | * So calculate the DVO timing relative offset in LVDS data | |
133 | * entry to get the DVO timing entry | |
134 | */ | |
135 | ||
136 | int lfp_data_size = | |
137 | lvds_lfp_data_ptrs->ptr[1].dvo_timing_offset - | |
138 | lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset; | |
139 | int dvo_timing_offset = | |
140 | lvds_lfp_data_ptrs->ptr[0].dvo_timing_offset - | |
141 | lvds_lfp_data_ptrs->ptr[0].fp_timing_offset; | |
142 | char *entry = (char *)lvds_lfp_data->data + lfp_data_size * index; | |
143 | ||
144 | return (struct lvds_dvo_timing *)(entry + dvo_timing_offset); | |
145 | } | |
146 | ||
b0354385 TI |
147 | /* get lvds_fp_timing entry |
148 | * this function may return NULL if the corresponding entry is invalid | |
149 | */ | |
150 | static const struct lvds_fp_timing * | |
151 | get_lvds_fp_timing(const struct bdb_header *bdb, | |
152 | const struct bdb_lvds_lfp_data *data, | |
153 | const struct bdb_lvds_lfp_data_ptrs *ptrs, | |
154 | int index) | |
155 | { | |
156 | size_t data_ofs = (const u8 *)data - (const u8 *)bdb; | |
157 | u16 data_size = ((const u16 *)data)[-1]; /* stored in header */ | |
158 | size_t ofs; | |
159 | ||
160 | if (index >= ARRAY_SIZE(ptrs->ptr)) | |
161 | return NULL; | |
162 | ofs = ptrs->ptr[index].fp_timing_offset; | |
163 | if (ofs < data_ofs || | |
164 | ofs + sizeof(struct lvds_fp_timing) > data_ofs + data_size) | |
165 | return NULL; | |
166 | return (const struct lvds_fp_timing *)((const u8 *)bdb + ofs); | |
167 | } | |
168 | ||
88631706 ML |
169 | /* Try to find integrated panel data */ |
170 | static void | |
171 | parse_lfp_panel_data(struct drm_i915_private *dev_priv, | |
dcb58a40 | 172 | const struct bdb_header *bdb) |
79e53945 | 173 | { |
99834ea4 CW |
174 | const struct bdb_lvds_options *lvds_options; |
175 | const struct bdb_lvds_lfp_data *lvds_lfp_data; | |
176 | const struct bdb_lvds_lfp_data_ptrs *lvds_lfp_data_ptrs; | |
177 | const struct lvds_dvo_timing *panel_dvo_timing; | |
b0354385 | 178 | const struct lvds_fp_timing *fp_timing; |
79e53945 | 179 | struct drm_display_mode *panel_fixed_mode; |
c329a4ec | 180 | int drrs_mode; |
79e53945 | 181 | |
79e53945 JB |
182 | lvds_options = find_section(bdb, BDB_LVDS_OPTIONS); |
183 | if (!lvds_options) | |
184 | return; | |
185 | ||
41aa3448 | 186 | dev_priv->vbt.lvds_dither = lvds_options->pixel_dither; |
79e53945 JB |
187 | if (lvds_options->panel_type == 0xff) |
188 | return; | |
6a04002b | 189 | |
500a8cc4 | 190 | panel_type = lvds_options->panel_type; |
79e53945 | 191 | |
83a7280e PB |
192 | drrs_mode = (lvds_options->dps_panel_type_bits |
193 | >> (panel_type * 2)) & MODE_MASK; | |
194 | /* | |
195 | * VBT has static DRRS = 0 and seamless DRRS = 2. | |
196 | * The below piece of code is required to adjust vbt.drrs_type | |
197 | * to match the enum drrs_support_type. | |
198 | */ | |
199 | switch (drrs_mode) { | |
200 | case 0: | |
201 | dev_priv->vbt.drrs_type = STATIC_DRRS_SUPPORT; | |
202 | DRM_DEBUG_KMS("DRRS supported mode is static\n"); | |
203 | break; | |
204 | case 2: | |
205 | dev_priv->vbt.drrs_type = SEAMLESS_DRRS_SUPPORT; | |
206 | DRM_DEBUG_KMS("DRRS supported mode is seamless\n"); | |
207 | break; | |
208 | default: | |
209 | dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED; | |
210 | DRM_DEBUG_KMS("DRRS not supported (VBT input)\n"); | |
211 | break; | |
212 | } | |
213 | ||
79e53945 JB |
214 | lvds_lfp_data = find_section(bdb, BDB_LVDS_LFP_DATA); |
215 | if (!lvds_lfp_data) | |
216 | return; | |
217 | ||
1b16de0b JB |
218 | lvds_lfp_data_ptrs = find_section(bdb, BDB_LVDS_LFP_DATA_PTRS); |
219 | if (!lvds_lfp_data_ptrs) | |
220 | return; | |
221 | ||
41aa3448 | 222 | dev_priv->vbt.lvds_vbt = 1; |
79e53945 | 223 | |
99834ea4 CW |
224 | panel_dvo_timing = get_lvds_dvo_timing(lvds_lfp_data, |
225 | lvds_lfp_data_ptrs, | |
226 | lvds_options->panel_type); | |
79e53945 | 227 | |
9a298b2a | 228 | panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); |
6edc3242 CW |
229 | if (!panel_fixed_mode) |
230 | return; | |
79e53945 | 231 | |
99834ea4 | 232 | fill_detail_timing_data(panel_fixed_mode, panel_dvo_timing); |
79e53945 | 233 | |
41aa3448 | 234 | dev_priv->vbt.lfp_lvds_vbt_mode = panel_fixed_mode; |
79e53945 | 235 | |
28c97730 | 236 | DRM_DEBUG_KMS("Found panel mode in BIOS VBT tables:\n"); |
88631706 | 237 | drm_mode_debug_printmodeline(panel_fixed_mode); |
37df9673 | 238 | |
b0354385 TI |
239 | fp_timing = get_lvds_fp_timing(bdb, lvds_lfp_data, |
240 | lvds_lfp_data_ptrs, | |
241 | lvds_options->panel_type); | |
242 | if (fp_timing) { | |
243 | /* check the resolution, just to be sure */ | |
244 | if (fp_timing->x_res == panel_fixed_mode->hdisplay && | |
245 | fp_timing->y_res == panel_fixed_mode->vdisplay) { | |
41aa3448 | 246 | dev_priv->vbt.bios_lvds_val = fp_timing->lvds_reg_val; |
b0354385 | 247 | DRM_DEBUG_KMS("VBT initial LVDS value %x\n", |
41aa3448 | 248 | dev_priv->vbt.bios_lvds_val); |
b0354385 TI |
249 | } |
250 | } | |
88631706 ML |
251 | } |
252 | ||
f00076d2 | 253 | static void |
dcb58a40 JN |
254 | parse_lfp_backlight(struct drm_i915_private *dev_priv, |
255 | const struct bdb_header *bdb) | |
f00076d2 JN |
256 | { |
257 | const struct bdb_lfp_backlight_data *backlight_data; | |
258 | const struct bdb_lfp_backlight_data_entry *entry; | |
259 | ||
260 | backlight_data = find_section(bdb, BDB_LVDS_BACKLIGHT); | |
261 | if (!backlight_data) | |
262 | return; | |
263 | ||
264 | if (backlight_data->entry_size != sizeof(backlight_data->data[0])) { | |
265 | DRM_DEBUG_KMS("Unsupported backlight data entry size %u\n", | |
266 | backlight_data->entry_size); | |
267 | return; | |
268 | } | |
269 | ||
270 | entry = &backlight_data->data[panel_type]; | |
271 | ||
39fbc9c8 JN |
272 | dev_priv->vbt.backlight.present = entry->type == BDB_BACKLIGHT_TYPE_PWM; |
273 | if (!dev_priv->vbt.backlight.present) { | |
274 | DRM_DEBUG_KMS("PWM backlight not present in VBT (type %u)\n", | |
275 | entry->type); | |
276 | return; | |
277 | } | |
278 | ||
f00076d2 JN |
279 | dev_priv->vbt.backlight.pwm_freq_hz = entry->pwm_freq_hz; |
280 | dev_priv->vbt.backlight.active_low_pwm = entry->active_low_pwm; | |
1de6068e | 281 | dev_priv->vbt.backlight.min_brightness = entry->min_brightness; |
f00076d2 JN |
282 | DRM_DEBUG_KMS("VBT backlight PWM modulation frequency %u Hz, " |
283 | "active %s, min brightness %u, level %u\n", | |
284 | dev_priv->vbt.backlight.pwm_freq_hz, | |
285 | dev_priv->vbt.backlight.active_low_pwm ? "low" : "high", | |
1de6068e | 286 | dev_priv->vbt.backlight.min_brightness, |
f00076d2 JN |
287 | backlight_data->level[panel_type]); |
288 | } | |
289 | ||
88631706 ML |
290 | /* Try to find sdvo panel data */ |
291 | static void | |
292 | parse_sdvo_panel_data(struct drm_i915_private *dev_priv, | |
dcb58a40 | 293 | const struct bdb_header *bdb) |
88631706 | 294 | { |
e8ef3b4c | 295 | const struct lvds_dvo_timing *dvo_timing; |
88631706 | 296 | struct drm_display_mode *panel_fixed_mode; |
5a1e5b6c | 297 | int index; |
79e53945 | 298 | |
d330a953 | 299 | index = i915.vbt_sdvo_panel_type; |
c10e408a MF |
300 | if (index == -2) { |
301 | DRM_DEBUG_KMS("Ignore SDVO panel mode from BIOS VBT tables.\n"); | |
302 | return; | |
303 | } | |
304 | ||
5a1e5b6c | 305 | if (index == -1) { |
e8ef3b4c | 306 | const struct bdb_sdvo_lvds_options *sdvo_lvds_options; |
5a1e5b6c CW |
307 | |
308 | sdvo_lvds_options = find_section(bdb, BDB_SDVO_LVDS_OPTIONS); | |
309 | if (!sdvo_lvds_options) | |
310 | return; | |
311 | ||
312 | index = sdvo_lvds_options->panel_type; | |
313 | } | |
88631706 ML |
314 | |
315 | dvo_timing = find_section(bdb, BDB_SDVO_PANEL_DTDS); | |
316 | if (!dvo_timing) | |
317 | return; | |
318 | ||
9a298b2a | 319 | panel_fixed_mode = kzalloc(sizeof(*panel_fixed_mode), GFP_KERNEL); |
88631706 ML |
320 | if (!panel_fixed_mode) |
321 | return; | |
322 | ||
5a1e5b6c | 323 | fill_detail_timing_data(panel_fixed_mode, dvo_timing + index); |
88631706 | 324 | |
41aa3448 | 325 | dev_priv->vbt.sdvo_lvds_vbt_mode = panel_fixed_mode; |
79e53945 | 326 | |
5a1e5b6c CW |
327 | DRM_DEBUG_KMS("Found SDVO panel mode in BIOS VBT tables:\n"); |
328 | drm_mode_debug_printmodeline(panel_fixed_mode); | |
79e53945 JB |
329 | } |
330 | ||
9a4114ff BF |
331 | static int intel_bios_ssc_frequency(struct drm_device *dev, |
332 | bool alternate) | |
333 | { | |
334 | switch (INTEL_INFO(dev)->gen) { | |
335 | case 2: | |
e91e941b | 336 | return alternate ? 66667 : 48000; |
9a4114ff BF |
337 | case 3: |
338 | case 4: | |
e91e941b | 339 | return alternate ? 100000 : 96000; |
9a4114ff | 340 | default: |
e91e941b | 341 | return alternate ? 100000 : 120000; |
9a4114ff BF |
342 | } |
343 | } | |
344 | ||
79e53945 JB |
345 | static void |
346 | parse_general_features(struct drm_i915_private *dev_priv, | |
dcb58a40 | 347 | const struct bdb_header *bdb) |
79e53945 | 348 | { |
bad720ff | 349 | struct drm_device *dev = dev_priv->dev; |
e8ef3b4c | 350 | const struct bdb_general_features *general; |
79e53945 | 351 | |
79e53945 JB |
352 | general = find_section(bdb, BDB_GENERAL_FEATURES); |
353 | if (general) { | |
41aa3448 RV |
354 | dev_priv->vbt.int_tv_support = general->int_tv_support; |
355 | dev_priv->vbt.int_crt_support = general->int_crt_support; | |
356 | dev_priv->vbt.lvds_use_ssc = general->enable_ssc; | |
357 | dev_priv->vbt.lvds_ssc_freq = | |
9a4114ff | 358 | intel_bios_ssc_frequency(dev, general->ssc_freq); |
41aa3448 RV |
359 | dev_priv->vbt.display_clock_mode = general->display_clock_mode; |
360 | dev_priv->vbt.fdi_rx_polarity_inverted = general->fdi_rx_polarity_inverted; | |
3f704fa2 | 361 | DRM_DEBUG_KMS("BDB_GENERAL_FEATURES int_tv_support %d int_crt_support %d lvds_use_ssc %d lvds_ssc_freq %d display_clock_mode %d fdi_rx_polarity_inverted %d\n", |
41aa3448 RV |
362 | dev_priv->vbt.int_tv_support, |
363 | dev_priv->vbt.int_crt_support, | |
364 | dev_priv->vbt.lvds_use_ssc, | |
365 | dev_priv->vbt.lvds_ssc_freq, | |
366 | dev_priv->vbt.display_clock_mode, | |
367 | dev_priv->vbt.fdi_rx_polarity_inverted); | |
79e53945 JB |
368 | } |
369 | } | |
370 | ||
db545019 DMEA |
371 | static void |
372 | parse_general_definitions(struct drm_i915_private *dev_priv, | |
dcb58a40 | 373 | const struct bdb_header *bdb) |
db545019 | 374 | { |
e8ef3b4c | 375 | const struct bdb_general_definitions *general; |
db545019 | 376 | |
db545019 DMEA |
377 | general = find_section(bdb, BDB_GENERAL_DEFINITIONS); |
378 | if (general) { | |
379 | u16 block_size = get_blocksize(general); | |
380 | if (block_size >= sizeof(*general)) { | |
381 | int bus_pin = general->crt_ddc_gmbus_pin; | |
28c97730 | 382 | DRM_DEBUG_KMS("crt_ddc_bus_pin: %d\n", bus_pin); |
88ac7939 | 383 | if (intel_gmbus_is_valid_pin(dev_priv, bus_pin)) |
41aa3448 | 384 | dev_priv->vbt.crt_ddc_pin = bus_pin; |
db545019 | 385 | } else { |
28c97730 | 386 | DRM_DEBUG_KMS("BDB_GD too small (%d). Invalid.\n", |
3bd7d909 | 387 | block_size); |
db545019 DMEA |
388 | } |
389 | } | |
390 | } | |
391 | ||
e8ef3b4c JN |
392 | static const union child_device_config * |
393 | child_device_ptr(const struct bdb_general_definitions *p_defs, int i) | |
90e4f159 | 394 | { |
e8ef3b4c | 395 | return (const void *) &p_defs->devices[i * p_defs->child_dev_size]; |
90e4f159 VS |
396 | } |
397 | ||
9b9d172d | 398 | static void |
399 | parse_sdvo_device_mapping(struct drm_i915_private *dev_priv, | |
dcb58a40 | 400 | const struct bdb_header *bdb) |
9b9d172d | 401 | { |
402 | struct sdvo_device_mapping *p_mapping; | |
e8ef3b4c JN |
403 | const struct bdb_general_definitions *p_defs; |
404 | const union child_device_config *p_child; | |
9b9d172d | 405 | int i, child_device_num, count; |
db545019 | 406 | u16 block_size; |
9b9d172d | 407 | |
408 | p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS); | |
409 | if (!p_defs) { | |
44834a67 | 410 | DRM_DEBUG_KMS("No general definition block is found, unable to construct sdvo mapping.\n"); |
9b9d172d | 411 | return; |
412 | } | |
413 | /* judge whether the size of child device meets the requirements. | |
414 | * If the child device size obtained from general definition block | |
415 | * is different with sizeof(struct child_device_config), skip the | |
416 | * parsing of sdvo device info | |
417 | */ | |
418 | if (p_defs->child_dev_size != sizeof(*p_child)) { | |
419 | /* different child dev size . Ignore it */ | |
28c97730 | 420 | DRM_DEBUG_KMS("different child size is found. Invalid.\n"); |
9b9d172d | 421 | return; |
422 | } | |
423 | /* get the block size of general definitions */ | |
db545019 | 424 | block_size = get_blocksize(p_defs); |
9b9d172d | 425 | /* get the number of child device */ |
426 | child_device_num = (block_size - sizeof(*p_defs)) / | |
90e4f159 | 427 | p_defs->child_dev_size; |
9b9d172d | 428 | count = 0; |
429 | for (i = 0; i < child_device_num; i++) { | |
90e4f159 | 430 | p_child = child_device_ptr(p_defs, i); |
768f69c9 | 431 | if (!p_child->old.device_type) { |
9b9d172d | 432 | /* skip the device block if device type is invalid */ |
433 | continue; | |
434 | } | |
768f69c9 PZ |
435 | if (p_child->old.slave_addr != SLAVE_ADDR1 && |
436 | p_child->old.slave_addr != SLAVE_ADDR2) { | |
9b9d172d | 437 | /* |
438 | * If the slave address is neither 0x70 nor 0x72, | |
439 | * it is not a SDVO device. Skip it. | |
440 | */ | |
441 | continue; | |
442 | } | |
768f69c9 PZ |
443 | if (p_child->old.dvo_port != DEVICE_PORT_DVOB && |
444 | p_child->old.dvo_port != DEVICE_PORT_DVOC) { | |
9b9d172d | 445 | /* skip the incorrect SDVO port */ |
0206e353 | 446 | DRM_DEBUG_KMS("Incorrect SDVO port. Skip it\n"); |
9b9d172d | 447 | continue; |
448 | } | |
28c97730 ZY |
449 | DRM_DEBUG_KMS("the SDVO device with slave addr %2x is found on" |
450 | " %s port\n", | |
768f69c9 PZ |
451 | p_child->old.slave_addr, |
452 | (p_child->old.dvo_port == DEVICE_PORT_DVOB) ? | |
9b9d172d | 453 | "SDVOB" : "SDVOC"); |
768f69c9 | 454 | p_mapping = &(dev_priv->sdvo_mappings[p_child->old.dvo_port - 1]); |
9b9d172d | 455 | if (!p_mapping->initialized) { |
768f69c9 PZ |
456 | p_mapping->dvo_port = p_child->old.dvo_port; |
457 | p_mapping->slave_addr = p_child->old.slave_addr; | |
458 | p_mapping->dvo_wiring = p_child->old.dvo_wiring; | |
459 | p_mapping->ddc_pin = p_child->old.ddc_pin; | |
460 | p_mapping->i2c_pin = p_child->old.i2c_pin; | |
9b9d172d | 461 | p_mapping->initialized = 1; |
46eb3036 | 462 | DRM_DEBUG_KMS("SDVO device: dvo=%x, addr=%x, wiring=%d, ddc_pin=%d, i2c_pin=%d\n", |
e957d772 CW |
463 | p_mapping->dvo_port, |
464 | p_mapping->slave_addr, | |
465 | p_mapping->dvo_wiring, | |
466 | p_mapping->ddc_pin, | |
46eb3036 | 467 | p_mapping->i2c_pin); |
9b9d172d | 468 | } else { |
28c97730 | 469 | DRM_DEBUG_KMS("Maybe one SDVO port is shared by " |
9b9d172d | 470 | "two SDVO device.\n"); |
471 | } | |
768f69c9 | 472 | if (p_child->old.slave2_addr) { |
9b9d172d | 473 | /* Maybe this is a SDVO device with multiple inputs */ |
474 | /* And the mapping info is not added */ | |
28c97730 ZY |
475 | DRM_DEBUG_KMS("there exists the slave2_addr. Maybe this" |
476 | " is a SDVO device with multiple inputs.\n"); | |
9b9d172d | 477 | } |
478 | count++; | |
479 | } | |
480 | ||
481 | if (!count) { | |
482 | /* No SDVO device info is found */ | |
28c97730 | 483 | DRM_DEBUG_KMS("No SDVO device info is found in VBT\n"); |
9b9d172d | 484 | } |
485 | return; | |
486 | } | |
32f9d658 ZW |
487 | |
488 | static void | |
489 | parse_driver_features(struct drm_i915_private *dev_priv, | |
dcb58a40 | 490 | const struct bdb_header *bdb) |
32f9d658 | 491 | { |
e8ef3b4c | 492 | const struct bdb_driver_features *driver; |
32f9d658 | 493 | |
32f9d658 | 494 | driver = find_section(bdb, BDB_DRIVER_FEATURES); |
652c393a JB |
495 | if (!driver) |
496 | return; | |
497 | ||
6fca55b1 | 498 | if (driver->lvds_config == BDB_DRIVER_FEATURE_EDP) |
41aa3448 | 499 | dev_priv->vbt.edp_support = 1; |
652c393a | 500 | |
5ceb0f9b | 501 | if (driver->dual_frequency) |
652c393a | 502 | dev_priv->render_reclock_avail = true; |
83a7280e PB |
503 | |
504 | DRM_DEBUG_KMS("DRRS State Enabled:%d\n", driver->drrs_enabled); | |
505 | /* | |
506 | * If DRRS is not supported, drrs_type has to be set to 0. | |
507 | * This is because, VBT is configured in such a way that | |
508 | * static DRRS is 0 and DRRS not supported is represented by | |
509 | * driver->drrs_enabled=false | |
510 | */ | |
511 | if (!driver->drrs_enabled) | |
512 | dev_priv->vbt.drrs_type = DRRS_NOT_SUPPORTED; | |
32f9d658 ZW |
513 | } |
514 | ||
500a8cc4 | 515 | static void |
dcb58a40 | 516 | parse_edp(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) |
500a8cc4 | 517 | { |
e8ef3b4c JN |
518 | const struct bdb_edp *edp; |
519 | const struct edp_power_seq *edp_pps; | |
520 | const struct edp_link_params *edp_link_params; | |
500a8cc4 ZW |
521 | |
522 | edp = find_section(bdb, BDB_EDP); | |
523 | if (!edp) { | |
6fca55b1 | 524 | if (dev_priv->vbt.edp_support) |
9a30a61f | 525 | DRM_DEBUG_KMS("No eDP BDB found but eDP panel supported.\n"); |
500a8cc4 ZW |
526 | return; |
527 | } | |
528 | ||
529 | switch ((edp->color_depth >> (panel_type * 2)) & 3) { | |
530 | case EDP_18BPP: | |
41aa3448 | 531 | dev_priv->vbt.edp_bpp = 18; |
500a8cc4 ZW |
532 | break; |
533 | case EDP_24BPP: | |
41aa3448 | 534 | dev_priv->vbt.edp_bpp = 24; |
500a8cc4 ZW |
535 | break; |
536 | case EDP_30BPP: | |
41aa3448 | 537 | dev_priv->vbt.edp_bpp = 30; |
500a8cc4 ZW |
538 | break; |
539 | } | |
5ceb0f9b | 540 | |
9f0e7ff4 JB |
541 | /* Get the eDP sequencing and link info */ |
542 | edp_pps = &edp->power_seqs[panel_type]; | |
543 | edp_link_params = &edp->link_params[panel_type]; | |
5ceb0f9b | 544 | |
41aa3448 | 545 | dev_priv->vbt.edp_pps = *edp_pps; |
5ceb0f9b | 546 | |
e13e2b2c JN |
547 | switch (edp_link_params->rate) { |
548 | case EDP_RATE_1_62: | |
549 | dev_priv->vbt.edp_rate = DP_LINK_BW_1_62; | |
550 | break; | |
551 | case EDP_RATE_2_7: | |
552 | dev_priv->vbt.edp_rate = DP_LINK_BW_2_7; | |
553 | break; | |
554 | default: | |
555 | DRM_DEBUG_KMS("VBT has unknown eDP link rate value %u\n", | |
556 | edp_link_params->rate); | |
557 | break; | |
558 | } | |
559 | ||
9f0e7ff4 | 560 | switch (edp_link_params->lanes) { |
e13e2b2c | 561 | case EDP_LANE_1: |
41aa3448 | 562 | dev_priv->vbt.edp_lanes = 1; |
9f0e7ff4 | 563 | break; |
e13e2b2c | 564 | case EDP_LANE_2: |
41aa3448 | 565 | dev_priv->vbt.edp_lanes = 2; |
9f0e7ff4 | 566 | break; |
e13e2b2c | 567 | case EDP_LANE_4: |
41aa3448 | 568 | dev_priv->vbt.edp_lanes = 4; |
9f0e7ff4 | 569 | break; |
e13e2b2c JN |
570 | default: |
571 | DRM_DEBUG_KMS("VBT has unknown eDP lane count value %u\n", | |
572 | edp_link_params->lanes); | |
573 | break; | |
9f0e7ff4 | 574 | } |
e13e2b2c | 575 | |
9f0e7ff4 | 576 | switch (edp_link_params->preemphasis) { |
e13e2b2c | 577 | case EDP_PREEMPHASIS_NONE: |
bd60018a | 578 | dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_0; |
9f0e7ff4 | 579 | break; |
e13e2b2c | 580 | case EDP_PREEMPHASIS_3_5dB: |
bd60018a | 581 | dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_1; |
9f0e7ff4 | 582 | break; |
e13e2b2c | 583 | case EDP_PREEMPHASIS_6dB: |
bd60018a | 584 | dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_2; |
9f0e7ff4 | 585 | break; |
e13e2b2c | 586 | case EDP_PREEMPHASIS_9_5dB: |
bd60018a | 587 | dev_priv->vbt.edp_preemphasis = DP_TRAIN_PRE_EMPH_LEVEL_3; |
9f0e7ff4 | 588 | break; |
e13e2b2c JN |
589 | default: |
590 | DRM_DEBUG_KMS("VBT has unknown eDP pre-emphasis value %u\n", | |
591 | edp_link_params->preemphasis); | |
592 | break; | |
9f0e7ff4 | 593 | } |
e13e2b2c | 594 | |
9f0e7ff4 | 595 | switch (edp_link_params->vswing) { |
e13e2b2c | 596 | case EDP_VSWING_0_4V: |
bd60018a | 597 | dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_0; |
9f0e7ff4 | 598 | break; |
e13e2b2c | 599 | case EDP_VSWING_0_6V: |
bd60018a | 600 | dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_1; |
9f0e7ff4 | 601 | break; |
e13e2b2c | 602 | case EDP_VSWING_0_8V: |
bd60018a | 603 | dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_2; |
9f0e7ff4 | 604 | break; |
e13e2b2c | 605 | case EDP_VSWING_1_2V: |
bd60018a | 606 | dev_priv->vbt.edp_vswing = DP_TRAIN_VOLTAGE_SWING_LEVEL_3; |
9f0e7ff4 | 607 | break; |
e13e2b2c JN |
608 | default: |
609 | DRM_DEBUG_KMS("VBT has unknown eDP voltage swing value %u\n", | |
610 | edp_link_params->vswing); | |
611 | break; | |
9f0e7ff4 | 612 | } |
9a57f5bb SJ |
613 | |
614 | if (bdb->version >= 173) { | |
615 | uint8_t vswing; | |
616 | ||
9e458034 SJ |
617 | /* Don't read from VBT if module parameter has valid value*/ |
618 | if (i915.edp_vswing) { | |
619 | dev_priv->edp_low_vswing = i915.edp_vswing == 1; | |
620 | } else { | |
621 | vswing = (edp->edp_vswing_preemph >> (panel_type * 4)) & 0xF; | |
622 | dev_priv->edp_low_vswing = vswing == 0; | |
623 | } | |
9a57f5bb | 624 | } |
500a8cc4 ZW |
625 | } |
626 | ||
bfd7ebda | 627 | static void |
dcb58a40 | 628 | parse_psr(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) |
bfd7ebda | 629 | { |
e8ef3b4c JN |
630 | const struct bdb_psr *psr; |
631 | const struct psr_table *psr_table; | |
bfd7ebda RV |
632 | |
633 | psr = find_section(bdb, BDB_PSR); | |
634 | if (!psr) { | |
635 | DRM_DEBUG_KMS("No PSR BDB found.\n"); | |
636 | return; | |
637 | } | |
638 | ||
639 | psr_table = &psr->psr_table[panel_type]; | |
640 | ||
641 | dev_priv->vbt.psr.full_link = psr_table->full_link; | |
642 | dev_priv->vbt.psr.require_aux_wakeup = psr_table->require_aux_to_wakeup; | |
643 | ||
644 | /* Allowed VBT values goes from 0 to 15 */ | |
645 | dev_priv->vbt.psr.idle_frames = psr_table->idle_frames < 0 ? 0 : | |
646 | psr_table->idle_frames > 15 ? 15 : psr_table->idle_frames; | |
647 | ||
648 | switch (psr_table->lines_to_wait) { | |
649 | case 0: | |
650 | dev_priv->vbt.psr.lines_to_wait = PSR_0_LINES_TO_WAIT; | |
651 | break; | |
652 | case 1: | |
653 | dev_priv->vbt.psr.lines_to_wait = PSR_1_LINE_TO_WAIT; | |
654 | break; | |
655 | case 2: | |
656 | dev_priv->vbt.psr.lines_to_wait = PSR_4_LINES_TO_WAIT; | |
657 | break; | |
658 | case 3: | |
659 | dev_priv->vbt.psr.lines_to_wait = PSR_8_LINES_TO_WAIT; | |
660 | break; | |
661 | default: | |
662 | DRM_DEBUG_KMS("VBT has unknown PSR lines to wait %u\n", | |
663 | psr_table->lines_to_wait); | |
664 | break; | |
665 | } | |
666 | ||
667 | dev_priv->vbt.psr.tp1_wakeup_time = psr_table->tp1_wakeup_time; | |
668 | dev_priv->vbt.psr.tp2_tp3_wakeup_time = psr_table->tp2_tp3_wakeup_time; | |
669 | } | |
670 | ||
d3b542fc SK |
671 | static u8 *goto_next_sequence(u8 *data, int *size) |
672 | { | |
673 | u16 len; | |
674 | int tmp = *size; | |
675 | ||
676 | if (--tmp < 0) | |
677 | return NULL; | |
678 | ||
679 | /* goto first element */ | |
680 | data++; | |
681 | while (1) { | |
682 | switch (*data) { | |
683 | case MIPI_SEQ_ELEM_SEND_PKT: | |
684 | /* | |
685 | * skip by this element payload size | |
686 | * skip elem id, command flag and data type | |
687 | */ | |
b0256cdc SK |
688 | tmp -= 5; |
689 | if (tmp < 0) | |
d3b542fc SK |
690 | return NULL; |
691 | ||
692 | data += 3; | |
693 | len = *((u16 *)data); | |
694 | ||
b0256cdc SK |
695 | tmp -= len; |
696 | if (tmp < 0) | |
d3b542fc SK |
697 | return NULL; |
698 | ||
699 | /* skip by len */ | |
700 | data = data + 2 + len; | |
701 | break; | |
702 | case MIPI_SEQ_ELEM_DELAY: | |
703 | /* skip by elem id, and delay is 4 bytes */ | |
b0256cdc SK |
704 | tmp -= 5; |
705 | if (tmp < 0) | |
d3b542fc SK |
706 | return NULL; |
707 | ||
708 | data += 5; | |
709 | break; | |
710 | case MIPI_SEQ_ELEM_GPIO: | |
b0256cdc SK |
711 | tmp -= 3; |
712 | if (tmp < 0) | |
d3b542fc SK |
713 | return NULL; |
714 | ||
715 | data += 3; | |
716 | break; | |
717 | default: | |
718 | DRM_ERROR("Unknown element\n"); | |
719 | return NULL; | |
720 | } | |
721 | ||
722 | /* end of sequence ? */ | |
723 | if (*data == 0) | |
724 | break; | |
725 | } | |
726 | ||
727 | /* goto next sequence or end of block byte */ | |
728 | if (--tmp < 0) | |
729 | return NULL; | |
730 | ||
731 | data++; | |
732 | ||
733 | /* update amount of data left for the sequence block to be parsed */ | |
734 | *size = tmp; | |
735 | return data; | |
736 | } | |
737 | ||
d17c5443 | 738 | static void |
dcb58a40 | 739 | parse_mipi(struct drm_i915_private *dev_priv, const struct bdb_header *bdb) |
d17c5443 | 740 | { |
e8ef3b4c JN |
741 | const struct bdb_mipi_config *start; |
742 | const struct bdb_mipi_sequence *sequence; | |
743 | const struct mipi_config *config; | |
744 | const struct mipi_pps_data *pps; | |
745 | u8 *data; | |
746 | const u8 *seq_data; | |
d3b542fc SK |
747 | int i, panel_id, seq_size; |
748 | u16 block_size; | |
749 | ||
3e6bd011 SK |
750 | /* parse MIPI blocks only if LFP type is MIPI */ |
751 | if (!dev_priv->vbt.has_mipi) | |
752 | return; | |
753 | ||
d3b542fc SK |
754 | /* Initialize this to undefined indicating no generic MIPI support */ |
755 | dev_priv->vbt.dsi.panel_id = MIPI_DSI_UNDEFINED_PANEL_ID; | |
756 | ||
757 | /* Block #40 is already parsed and panel_fixed_mode is | |
758 | * stored in dev_priv->lfp_lvds_vbt_mode | |
759 | * resuse this when needed | |
760 | */ | |
d17c5443 | 761 | |
d3b542fc SK |
762 | /* Parse #52 for panel index used from panel_type already |
763 | * parsed | |
764 | */ | |
765 | start = find_section(bdb, BDB_MIPI_CONFIG); | |
766 | if (!start) { | |
767 | DRM_DEBUG_KMS("No MIPI config BDB found"); | |
d17c5443 SK |
768 | return; |
769 | } | |
770 | ||
d3b542fc SK |
771 | DRM_DEBUG_DRIVER("Found MIPI Config block, panel index = %d\n", |
772 | panel_type); | |
773 | ||
774 | /* | |
775 | * get hold of the correct configuration block and pps data as per | |
776 | * the panel_type as index | |
777 | */ | |
778 | config = &start->config[panel_type]; | |
779 | pps = &start->pps[panel_type]; | |
780 | ||
781 | /* store as of now full data. Trim when we realise all is not needed */ | |
782 | dev_priv->vbt.dsi.config = kmemdup(config, sizeof(struct mipi_config), GFP_KERNEL); | |
783 | if (!dev_priv->vbt.dsi.config) | |
784 | return; | |
785 | ||
786 | dev_priv->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL); | |
787 | if (!dev_priv->vbt.dsi.pps) { | |
788 | kfree(dev_priv->vbt.dsi.config); | |
789 | return; | |
790 | } | |
791 | ||
792 | /* We have mandatory mipi config blocks. Initialize as generic panel */ | |
ea9a6baf | 793 | dev_priv->vbt.dsi.panel_id = MIPI_DSI_GENERIC_PANEL_ID; |
d3b542fc SK |
794 | |
795 | /* Check if we have sequence block as well */ | |
796 | sequence = find_section(bdb, BDB_MIPI_SEQUENCE); | |
797 | if (!sequence) { | |
798 | DRM_DEBUG_KMS("No MIPI Sequence found, parsing complete\n"); | |
799 | return; | |
800 | } | |
801 | ||
802 | DRM_DEBUG_DRIVER("Found MIPI sequence block\n"); | |
803 | ||
804 | block_size = get_blocksize(sequence); | |
805 | ||
806 | /* | |
807 | * parse the sequence block for individual sequences | |
808 | */ | |
809 | dev_priv->vbt.dsi.seq_version = sequence->version; | |
810 | ||
811 | seq_data = &sequence->data[0]; | |
812 | ||
813 | /* | |
814 | * sequence block is variable length and hence we need to parse and | |
815 | * get the sequence data for specific panel id | |
816 | */ | |
817 | for (i = 0; i < MAX_MIPI_CONFIGURATIONS; i++) { | |
818 | panel_id = *seq_data; | |
819 | seq_size = *((u16 *) (seq_data + 1)); | |
820 | if (panel_id == panel_type) | |
821 | break; | |
822 | ||
823 | /* skip the sequence including seq header of 3 bytes */ | |
824 | seq_data = seq_data + 3 + seq_size; | |
825 | if ((seq_data - &sequence->data[0]) > block_size) { | |
826 | DRM_ERROR("Sequence start is beyond sequence block size, corrupted sequence block\n"); | |
827 | return; | |
828 | } | |
829 | } | |
830 | ||
831 | if (i == MAX_MIPI_CONFIGURATIONS) { | |
832 | DRM_ERROR("Sequence block detected but no valid configuration\n"); | |
833 | return; | |
834 | } | |
835 | ||
836 | /* check if found sequence is completely within the sequence block | |
837 | * just being paranoid */ | |
838 | if (seq_size > block_size) { | |
839 | DRM_ERROR("Corrupted sequence/size, bailing out\n"); | |
840 | return; | |
841 | } | |
842 | ||
843 | /* skip the panel id(1 byte) and seq size(2 bytes) */ | |
844 | dev_priv->vbt.dsi.data = kmemdup(seq_data + 3, seq_size, GFP_KERNEL); | |
845 | if (!dev_priv->vbt.dsi.data) | |
846 | return; | |
847 | ||
848 | /* | |
849 | * loop into the sequence data and split into multiple sequneces | |
850 | * There are only 5 types of sequences as of now | |
851 | */ | |
852 | data = dev_priv->vbt.dsi.data; | |
853 | dev_priv->vbt.dsi.size = seq_size; | |
854 | ||
855 | /* two consecutive 0x00 indicate end of all sequences */ | |
856 | while (1) { | |
857 | int seq_id = *data; | |
858 | if (MIPI_SEQ_MAX > seq_id && seq_id > MIPI_SEQ_UNDEFINED) { | |
859 | dev_priv->vbt.dsi.sequence[seq_id] = data; | |
860 | DRM_DEBUG_DRIVER("Found mipi sequence - %d\n", seq_id); | |
861 | } else { | |
862 | DRM_ERROR("undefined sequence\n"); | |
863 | goto err; | |
864 | } | |
865 | ||
866 | /* partial parsing to skip elements */ | |
867 | data = goto_next_sequence(data, &seq_size); | |
868 | ||
869 | if (data == NULL) { | |
870 | DRM_ERROR("Sequence elements going beyond block itself. Sequence block parsing failed\n"); | |
871 | goto err; | |
872 | } | |
873 | ||
874 | if (*data == 0) | |
875 | break; /* end of sequence reached */ | |
876 | } | |
877 | ||
878 | DRM_DEBUG_DRIVER("MIPI related vbt parsing complete\n"); | |
879 | return; | |
880 | err: | |
881 | kfree(dev_priv->vbt.dsi.data); | |
882 | dev_priv->vbt.dsi.data = NULL; | |
883 | ||
884 | /* error during parsing so set all pointers to null | |
885 | * because of partial parsing */ | |
ed3b6679 | 886 | memset(dev_priv->vbt.dsi.sequence, 0, sizeof(dev_priv->vbt.dsi.sequence)); |
d17c5443 SK |
887 | } |
888 | ||
6acab15a | 889 | static void parse_ddi_port(struct drm_i915_private *dev_priv, enum port port, |
dcb58a40 | 890 | const struct bdb_header *bdb) |
6acab15a PZ |
891 | { |
892 | union child_device_config *it, *child = NULL; | |
893 | struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port]; | |
894 | uint8_t hdmi_level_shift; | |
895 | int i, j; | |
554d6af5 | 896 | bool is_dvi, is_hdmi, is_dp, is_edp, is_crt; |
6bf19e7c | 897 | uint8_t aux_channel; |
6acab15a PZ |
898 | /* Each DDI port can have more than one value on the "DVO Port" field, |
899 | * so look for all the possible values for each port and abort if more | |
900 | * than one is found. */ | |
901 | int dvo_ports[][2] = { | |
902 | {DVO_PORT_HDMIA, DVO_PORT_DPA}, | |
903 | {DVO_PORT_HDMIB, DVO_PORT_DPB}, | |
904 | {DVO_PORT_HDMIC, DVO_PORT_DPC}, | |
905 | {DVO_PORT_HDMID, DVO_PORT_DPD}, | |
906 | {DVO_PORT_CRT, -1 /* Port E can only be DVO_PORT_CRT */ }, | |
907 | }; | |
908 | ||
909 | /* Find the child device to use, abort if more than one found. */ | |
910 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { | |
911 | it = dev_priv->vbt.child_dev + i; | |
912 | ||
913 | for (j = 0; j < 2; j++) { | |
914 | if (dvo_ports[port][j] == -1) | |
915 | break; | |
916 | ||
917 | if (it->common.dvo_port == dvo_ports[port][j]) { | |
918 | if (child) { | |
919 | DRM_DEBUG_KMS("More than one child device for port %c in VBT.\n", | |
920 | port_name(port)); | |
921 | return; | |
922 | } | |
923 | child = it; | |
924 | } | |
925 | } | |
926 | } | |
927 | if (!child) | |
928 | return; | |
929 | ||
6bf19e7c PZ |
930 | aux_channel = child->raw[25]; |
931 | ||
78eb06c3 VS |
932 | is_dvi = child->common.device_type & DEVICE_TYPE_TMDS_DVI_SIGNALING; |
933 | is_dp = child->common.device_type & DEVICE_TYPE_DISPLAYPORT_OUTPUT; | |
934 | is_crt = child->common.device_type & DEVICE_TYPE_ANALOG_OUTPUT; | |
935 | is_hdmi = is_dvi && (child->common.device_type & DEVICE_TYPE_NOT_HDMI_OUTPUT) == 0; | |
936 | is_edp = is_dp && (child->common.device_type & DEVICE_TYPE_INTERNAL_CONNECTOR); | |
554d6af5 | 937 | |
311a2094 PZ |
938 | info->supports_dvi = is_dvi; |
939 | info->supports_hdmi = is_hdmi; | |
940 | info->supports_dp = is_dp; | |
941 | ||
554d6af5 PZ |
942 | DRM_DEBUG_KMS("Port %c VBT info: DP:%d HDMI:%d DVI:%d EDP:%d CRT:%d\n", |
943 | port_name(port), is_dp, is_hdmi, is_dvi, is_edp, is_crt); | |
944 | ||
945 | if (is_edp && is_dvi) | |
946 | DRM_DEBUG_KMS("Internal DP port %c is TMDS compatible\n", | |
947 | port_name(port)); | |
948 | if (is_crt && port != PORT_E) | |
949 | DRM_DEBUG_KMS("Port %c is analog\n", port_name(port)); | |
950 | if (is_crt && (is_dvi || is_dp)) | |
951 | DRM_DEBUG_KMS("Analog port %c is also DP or TMDS compatible\n", | |
952 | port_name(port)); | |
953 | if (is_dvi && (port == PORT_A || port == PORT_E)) | |
9b13494c | 954 | DRM_DEBUG_KMS("Port %c is TMDS compatible\n", port_name(port)); |
554d6af5 PZ |
955 | if (!is_dvi && !is_dp && !is_crt) |
956 | DRM_DEBUG_KMS("Port %c is not DP/TMDS/CRT compatible\n", | |
957 | port_name(port)); | |
958 | if (is_edp && (port == PORT_B || port == PORT_C || port == PORT_E)) | |
959 | DRM_DEBUG_KMS("Port %c is internal DP\n", port_name(port)); | |
6bf19e7c PZ |
960 | |
961 | if (is_dvi) { | |
962 | if (child->common.ddc_pin == 0x05 && port != PORT_B) | |
963 | DRM_DEBUG_KMS("Unexpected DDC pin for port B\n"); | |
964 | if (child->common.ddc_pin == 0x04 && port != PORT_C) | |
965 | DRM_DEBUG_KMS("Unexpected DDC pin for port C\n"); | |
966 | if (child->common.ddc_pin == 0x06 && port != PORT_D) | |
967 | DRM_DEBUG_KMS("Unexpected DDC pin for port D\n"); | |
968 | } | |
969 | ||
970 | if (is_dp) { | |
500ea70d RV |
971 | if (port == PORT_E) { |
972 | info->alternate_aux_channel = aux_channel; | |
973 | /* if DDIE share aux channel with other port, then | |
974 | * DP couldn't exist on the shared port. Otherwise | |
975 | * they share the same aux channel and system | |
976 | * couldn't communicate with them seperately. */ | |
977 | if (aux_channel == DP_AUX_A) | |
978 | dev_priv->vbt.ddi_port_info[PORT_A].supports_dp = 0; | |
979 | else if (aux_channel == DP_AUX_B) | |
980 | dev_priv->vbt.ddi_port_info[PORT_B].supports_dp = 0; | |
981 | else if (aux_channel == DP_AUX_C) | |
982 | dev_priv->vbt.ddi_port_info[PORT_C].supports_dp = 0; | |
983 | else if (aux_channel == DP_AUX_D) | |
984 | dev_priv->vbt.ddi_port_info[PORT_D].supports_dp = 0; | |
985 | } | |
986 | else if (aux_channel == DP_AUX_A && port != PORT_A) | |
6bf19e7c | 987 | DRM_DEBUG_KMS("Unexpected AUX channel for port A\n"); |
500ea70d | 988 | else if (aux_channel == DP_AUX_B && port != PORT_B) |
6bf19e7c | 989 | DRM_DEBUG_KMS("Unexpected AUX channel for port B\n"); |
500ea70d | 990 | else if (aux_channel == DP_AUX_C && port != PORT_C) |
6bf19e7c | 991 | DRM_DEBUG_KMS("Unexpected AUX channel for port C\n"); |
500ea70d | 992 | else if (aux_channel == DP_AUX_D && port != PORT_D) |
6bf19e7c PZ |
993 | DRM_DEBUG_KMS("Unexpected AUX channel for port D\n"); |
994 | } | |
995 | ||
6acab15a PZ |
996 | if (bdb->version >= 158) { |
997 | /* The VBT HDMI level shift values match the table we have. */ | |
998 | hdmi_level_shift = child->raw[7] & 0xF; | |
ce4dd49e DL |
999 | DRM_DEBUG_KMS("VBT HDMI level shift for port %c: %d\n", |
1000 | port_name(port), | |
1001 | hdmi_level_shift); | |
1002 | info->hdmi_level_shift = hdmi_level_shift; | |
6acab15a PZ |
1003 | } |
1004 | } | |
1005 | ||
1006 | static void parse_ddi_ports(struct drm_i915_private *dev_priv, | |
dcb58a40 | 1007 | const struct bdb_header *bdb) |
6acab15a PZ |
1008 | { |
1009 | struct drm_device *dev = dev_priv->dev; | |
1010 | enum port port; | |
1011 | ||
1012 | if (!HAS_DDI(dev)) | |
1013 | return; | |
1014 | ||
1015 | if (!dev_priv->vbt.child_dev_num) | |
1016 | return; | |
1017 | ||
1018 | if (bdb->version < 155) | |
1019 | return; | |
1020 | ||
1021 | for (port = PORT_A; port < I915_MAX_PORTS; port++) | |
1022 | parse_ddi_port(dev_priv, port, bdb); | |
1023 | } | |
1024 | ||
6363ee6f ZY |
1025 | static void |
1026 | parse_device_mapping(struct drm_i915_private *dev_priv, | |
dcb58a40 | 1027 | const struct bdb_header *bdb) |
6363ee6f | 1028 | { |
e8ef3b4c JN |
1029 | const struct bdb_general_definitions *p_defs; |
1030 | const union child_device_config *p_child; | |
1031 | union child_device_config *child_dev_ptr; | |
6363ee6f ZY |
1032 | int i, child_device_num, count; |
1033 | u16 block_size; | |
1034 | ||
1035 | p_defs = find_section(bdb, BDB_GENERAL_DEFINITIONS); | |
1036 | if (!p_defs) { | |
44834a67 | 1037 | DRM_DEBUG_KMS("No general definition block is found, no devices defined.\n"); |
6363ee6f ZY |
1038 | return; |
1039 | } | |
90e4f159 VS |
1040 | if (p_defs->child_dev_size < sizeof(*p_child)) { |
1041 | DRM_ERROR("General definiton block child device size is too small.\n"); | |
6363ee6f ZY |
1042 | return; |
1043 | } | |
1044 | /* get the block size of general definitions */ | |
1045 | block_size = get_blocksize(p_defs); | |
1046 | /* get the number of child device */ | |
1047 | child_device_num = (block_size - sizeof(*p_defs)) / | |
90e4f159 | 1048 | p_defs->child_dev_size; |
6363ee6f ZY |
1049 | count = 0; |
1050 | /* get the number of child device that is present */ | |
1051 | for (i = 0; i < child_device_num; i++) { | |
90e4f159 | 1052 | p_child = child_device_ptr(p_defs, i); |
768f69c9 | 1053 | if (!p_child->common.device_type) { |
6363ee6f ZY |
1054 | /* skip the device block if device type is invalid */ |
1055 | continue; | |
1056 | } | |
1057 | count++; | |
1058 | } | |
1059 | if (!count) { | |
0206e353 | 1060 | DRM_DEBUG_KMS("no child dev is parsed from VBT\n"); |
6363ee6f ZY |
1061 | return; |
1062 | } | |
41aa3448 RV |
1063 | dev_priv->vbt.child_dev = kcalloc(count, sizeof(*p_child), GFP_KERNEL); |
1064 | if (!dev_priv->vbt.child_dev) { | |
6363ee6f ZY |
1065 | DRM_DEBUG_KMS("No memory space for child device\n"); |
1066 | return; | |
1067 | } | |
1068 | ||
41aa3448 | 1069 | dev_priv->vbt.child_dev_num = count; |
6363ee6f ZY |
1070 | count = 0; |
1071 | for (i = 0; i < child_device_num; i++) { | |
90e4f159 | 1072 | p_child = child_device_ptr(p_defs, i); |
768f69c9 | 1073 | if (!p_child->common.device_type) { |
6363ee6f ZY |
1074 | /* skip the device block if device type is invalid */ |
1075 | continue; | |
1076 | } | |
3e6bd011 SK |
1077 | |
1078 | if (p_child->common.dvo_port >= DVO_PORT_MIPIA | |
1079 | && p_child->common.dvo_port <= DVO_PORT_MIPID | |
1080 | &&p_child->common.device_type & DEVICE_TYPE_MIPI_OUTPUT) { | |
1081 | DRM_DEBUG_KMS("Found MIPI as LFP\n"); | |
1082 | dev_priv->vbt.has_mipi = 1; | |
1083 | dev_priv->vbt.dsi.port = p_child->common.dvo_port; | |
1084 | } | |
1085 | ||
41aa3448 | 1086 | child_dev_ptr = dev_priv->vbt.child_dev + count; |
6363ee6f | 1087 | count++; |
e8ef3b4c | 1088 | memcpy(child_dev_ptr, p_child, sizeof(*p_child)); |
6363ee6f ZY |
1089 | } |
1090 | return; | |
1091 | } | |
44834a67 | 1092 | |
6a04002b SQ |
1093 | static void |
1094 | init_vbt_defaults(struct drm_i915_private *dev_priv) | |
1095 | { | |
9a4114ff | 1096 | struct drm_device *dev = dev_priv->dev; |
6acab15a | 1097 | enum port port; |
9a4114ff | 1098 | |
988c7015 | 1099 | dev_priv->vbt.crt_ddc_pin = GMBUS_PIN_VGADDC; |
6a04002b | 1100 | |
56c4b63a JN |
1101 | /* Default to having backlight */ |
1102 | dev_priv->vbt.backlight.present = true; | |
1103 | ||
6a04002b | 1104 | /* LFP panel data */ |
41aa3448 RV |
1105 | dev_priv->vbt.lvds_dither = 1; |
1106 | dev_priv->vbt.lvds_vbt = 0; | |
6a04002b SQ |
1107 | |
1108 | /* SDVO panel data */ | |
41aa3448 | 1109 | dev_priv->vbt.sdvo_lvds_vbt_mode = NULL; |
6a04002b SQ |
1110 | |
1111 | /* general features */ | |
41aa3448 RV |
1112 | dev_priv->vbt.int_tv_support = 1; |
1113 | dev_priv->vbt.int_crt_support = 1; | |
9a4114ff BF |
1114 | |
1115 | /* Default to using SSC */ | |
41aa3448 | 1116 | dev_priv->vbt.lvds_use_ssc = 1; |
f69e5156 DL |
1117 | /* |
1118 | * Core/SandyBridge/IvyBridge use alternative (120MHz) reference | |
1119 | * clock for LVDS. | |
1120 | */ | |
1121 | dev_priv->vbt.lvds_ssc_freq = intel_bios_ssc_frequency(dev, | |
1122 | !HAS_PCH_SPLIT(dev)); | |
e91e941b | 1123 | DRM_DEBUG_KMS("Set default to SSC at %d kHz\n", dev_priv->vbt.lvds_ssc_freq); |
6acab15a PZ |
1124 | |
1125 | for (port = PORT_A; port < I915_MAX_PORTS; port++) { | |
311a2094 PZ |
1126 | struct ddi_vbt_port_info *info = |
1127 | &dev_priv->vbt.ddi_port_info[port]; | |
1128 | ||
ce4dd49e | 1129 | info->hdmi_level_shift = HDMI_LEVEL_SHIFT_UNKNOWN; |
311a2094 PZ |
1130 | |
1131 | info->supports_dvi = (port != PORT_A && port != PORT_E); | |
1132 | info->supports_hdmi = info->supports_dvi; | |
1133 | info->supports_dp = (port != PORT_E); | |
6acab15a | 1134 | } |
6a04002b SQ |
1135 | } |
1136 | ||
bbe1c274 | 1137 | static int intel_no_opregion_vbt_callback(const struct dmi_system_id *id) |
25e341cf DV |
1138 | { |
1139 | DRM_DEBUG_KMS("Falling back to manually reading VBT from " | |
1140 | "VBIOS ROM for %s\n", | |
1141 | id->ident); | |
1142 | return 1; | |
1143 | } | |
1144 | ||
1145 | static const struct dmi_system_id intel_no_opregion_vbt[] = { | |
1146 | { | |
1147 | .callback = intel_no_opregion_vbt_callback, | |
1148 | .ident = "ThinkCentre A57", | |
1149 | .matches = { | |
1150 | DMI_MATCH(DMI_SYS_VENDOR, "LENOVO"), | |
1151 | DMI_MATCH(DMI_PRODUCT_NAME, "97027RG"), | |
1152 | }, | |
1153 | }, | |
1154 | { } | |
1155 | }; | |
1156 | ||
acbb4793 JN |
1157 | static const struct bdb_header *validate_vbt(const void __iomem *_base, |
1158 | size_t size, | |
1159 | const void __iomem *_vbt, | |
dcb58a40 | 1160 | const char *source) |
3dd4e846 | 1161 | { |
acbb4793 JN |
1162 | /* |
1163 | * This is the one place where we explicitly discard the address space | |
1164 | * (__iomem) of the BIOS/VBT. (And this will cause a sparse complaint.) | |
1165 | * From now on everything is based on 'base', and treated as regular | |
1166 | * memory. | |
1167 | */ | |
1168 | const void *base = (const void *) _base; | |
1169 | size_t offset = _vbt - _base; | |
1170 | const struct vbt_header *vbt = base + offset; | |
dcb58a40 | 1171 | const struct bdb_header *bdb; |
3dd4e846 | 1172 | |
3dd4e846 CW |
1173 | if (offset + sizeof(struct vbt_header) > size) { |
1174 | DRM_DEBUG_DRIVER("VBT header incomplete\n"); | |
1175 | return NULL; | |
1176 | } | |
1177 | ||
1178 | if (memcmp(vbt->signature, "$VBT", 4)) { | |
1179 | DRM_DEBUG_DRIVER("VBT invalid signature\n"); | |
1180 | return NULL; | |
1181 | } | |
1182 | ||
1183 | offset += vbt->bdb_offset; | |
1184 | if (offset + sizeof(struct bdb_header) > size) { | |
1185 | DRM_DEBUG_DRIVER("BDB header incomplete\n"); | |
1186 | return NULL; | |
1187 | } | |
1188 | ||
dcb58a40 | 1189 | bdb = base + offset; |
3dd4e846 CW |
1190 | if (offset + bdb->bdb_size > size) { |
1191 | DRM_DEBUG_DRIVER("BDB incomplete\n"); | |
1192 | return NULL; | |
1193 | } | |
1194 | ||
1195 | DRM_DEBUG_KMS("Using VBT from %s: %20s\n", | |
1196 | source, vbt->signature); | |
1197 | return bdb; | |
1198 | } | |
1199 | ||
acbb4793 | 1200 | static const struct bdb_header *find_vbt(void __iomem *bios, size_t size) |
b34a991a JN |
1201 | { |
1202 | const struct bdb_header *bdb = NULL; | |
1203 | size_t i; | |
1204 | ||
1205 | /* Scour memory looking for the VBT signature. */ | |
1206 | for (i = 0; i + 4 < size; i++) { | |
acbb4793 | 1207 | if (ioread32(bios + i) == *((const u32 *) "$VBT")) { |
b34a991a JN |
1208 | bdb = validate_vbt(bios, size, bios + i, "PCI ROM"); |
1209 | break; | |
1210 | } | |
1211 | } | |
1212 | ||
1213 | return bdb; | |
1214 | } | |
1215 | ||
79e53945 | 1216 | /** |
6d139a87 | 1217 | * intel_parse_bios - find VBT and initialize settings from the BIOS |
79e53945 JB |
1218 | * @dev: DRM device |
1219 | * | |
1220 | * Loads the Video BIOS and checks that the VBT exists. Sets scratch registers | |
1221 | * to appropriate values. | |
1222 | * | |
79e53945 JB |
1223 | * Returns 0 on success, nonzero on failure. |
1224 | */ | |
0317c6ce | 1225 | int |
6d139a87 | 1226 | intel_parse_bios(struct drm_device *dev) |
79e53945 JB |
1227 | { |
1228 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1229 | struct pci_dev *pdev = dev->pdev; | |
dcb58a40 | 1230 | const struct bdb_header *bdb = NULL; |
44834a67 CW |
1231 | u8 __iomem *bios = NULL; |
1232 | ||
ab5c608b BW |
1233 | if (HAS_PCH_NOP(dev)) |
1234 | return -ENODEV; | |
1235 | ||
6a04002b | 1236 | init_vbt_defaults(dev_priv); |
f899fc64 | 1237 | |
44834a67 | 1238 | /* XXX Should this validation be moved to intel_opregion.c? */ |
3dd4e846 | 1239 | if (!dmi_check_system(intel_no_opregion_vbt) && dev_priv->opregion.vbt) |
dcb58a40 JN |
1240 | bdb = validate_vbt(dev_priv->opregion.header, OPREGION_SIZE, |
1241 | dev_priv->opregion.vbt, "OpRegion"); | |
79e53945 | 1242 | |
44834a67 | 1243 | if (bdb == NULL) { |
b34a991a | 1244 | size_t size; |
79e53945 | 1245 | |
44834a67 CW |
1246 | bios = pci_map_rom(pdev, &size); |
1247 | if (!bios) | |
1248 | return -1; | |
1249 | ||
b34a991a | 1250 | bdb = find_vbt(bios, size); |
3dd4e846 | 1251 | if (!bdb) { |
44834a67 CW |
1252 | pci_unmap_rom(pdev, bios); |
1253 | return -1; | |
1254 | } | |
44834a67 | 1255 | } |
79e53945 JB |
1256 | |
1257 | /* Grab useful general definitions */ | |
1258 | parse_general_features(dev_priv, bdb); | |
db545019 | 1259 | parse_general_definitions(dev_priv, bdb); |
88631706 | 1260 | parse_lfp_panel_data(dev_priv, bdb); |
f00076d2 | 1261 | parse_lfp_backlight(dev_priv, bdb); |
88631706 | 1262 | parse_sdvo_panel_data(dev_priv, bdb); |
9b9d172d | 1263 | parse_sdvo_device_mapping(dev_priv, bdb); |
6363ee6f | 1264 | parse_device_mapping(dev_priv, bdb); |
32f9d658 | 1265 | parse_driver_features(dev_priv, bdb); |
500a8cc4 | 1266 | parse_edp(dev_priv, bdb); |
bfd7ebda | 1267 | parse_psr(dev_priv, bdb); |
d17c5443 | 1268 | parse_mipi(dev_priv, bdb); |
6acab15a | 1269 | parse_ddi_ports(dev_priv, bdb); |
32f9d658 | 1270 | |
44834a67 CW |
1271 | if (bios) |
1272 | pci_unmap_rom(pdev, bios); | |
79e53945 JB |
1273 | |
1274 | return 0; | |
1275 | } | |
6d139a87 BF |
1276 | |
1277 | /* Ensure that vital registers have been initialised, even if the BIOS | |
1278 | * is absent or just failing to do its job. | |
1279 | */ | |
1280 | void intel_setup_bios(struct drm_device *dev) | |
1281 | { | |
1282 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1283 | ||
1284 | /* Set the Panel Power On/Off timings if uninitialized. */ | |
42d42e7e DL |
1285 | if (!HAS_PCH_SPLIT(dev) && |
1286 | I915_READ(PP_ON_DELAYS) == 0 && I915_READ(PP_OFF_DELAYS) == 0) { | |
6d139a87 BF |
1287 | /* Set T2 to 40ms and T5 to 200ms */ |
1288 | I915_WRITE(PP_ON_DELAYS, 0x019007d0); | |
1289 | ||
1290 | /* Set T3 to 35ms and Tx to 200ms */ | |
1291 | I915_WRITE(PP_OFF_DELAYS, 0x015e07d0); | |
1292 | } | |
1293 | } |