Commit | Line | Data |
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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
8ca4013d | 27 | #include <linux/dmi.h> |
79e53945 | 28 | #include <linux/i2c.h> |
5a0e3ad6 | 29 | #include <linux/slab.h> |
760285e7 | 30 | #include <drm/drmP.h> |
c6f95f27 | 31 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
32 | #include <drm/drm_crtc.h> |
33 | #include <drm/drm_crtc_helper.h> | |
34 | #include <drm/drm_edid.h> | |
79e53945 | 35 | #include "intel_drv.h" |
760285e7 | 36 | #include <drm/i915_drm.h> |
79e53945 JB |
37 | #include "i915_drv.h" |
38 | ||
e7dbb2f2 KP |
39 | /* Here's the desired hotplug mode */ |
40 | #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 | \ | |
41 | ADPA_CRT_HOTPLUG_WARMUP_10MS | \ | |
42 | ADPA_CRT_HOTPLUG_SAMPLE_4S | \ | |
43 | ADPA_CRT_HOTPLUG_VOLTAGE_50 | \ | |
44 | ADPA_CRT_HOTPLUG_VOLREF_325MV | \ | |
45 | ADPA_CRT_HOTPLUG_ENABLE) | |
46 | ||
c9a1c4cd CW |
47 | struct intel_crt { |
48 | struct intel_encoder base; | |
637f44d2 AJ |
49 | /* DPMS state is stored in the connector, which we need in the |
50 | * encoder's enable/disable callbacks */ | |
51 | struct intel_connector *connector; | |
e7dbb2f2 | 52 | bool force_hotplug_required; |
540a8950 | 53 | u32 adpa_reg; |
c9a1c4cd CW |
54 | }; |
55 | ||
eebe6f0b | 56 | static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder) |
c9a1c4cd | 57 | { |
eebe6f0b | 58 | return container_of(encoder, struct intel_crt, base); |
c9a1c4cd CW |
59 | } |
60 | ||
eebe6f0b | 61 | static struct intel_crt *intel_attached_crt(struct drm_connector *connector) |
79e53945 | 62 | { |
eebe6f0b | 63 | return intel_encoder_to_crt(intel_attached_encoder(connector)); |
540a8950 DV |
64 | } |
65 | ||
e403fc94 DV |
66 | static bool intel_crt_get_hw_state(struct intel_encoder *encoder, |
67 | enum pipe *pipe) | |
79e53945 | 68 | { |
e403fc94 | 69 | struct drm_device *dev = encoder->base.dev; |
79e53945 | 70 | struct drm_i915_private *dev_priv = dev->dev_private; |
e403fc94 | 71 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
6d129bea | 72 | enum intel_display_power_domain power_domain; |
e403fc94 DV |
73 | u32 tmp; |
74 | ||
6d129bea | 75 | power_domain = intel_display_port_power_domain(encoder); |
f458ebbc | 76 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
6d129bea ID |
77 | return false; |
78 | ||
e403fc94 DV |
79 | tmp = I915_READ(crt->adpa_reg); |
80 | ||
81 | if (!(tmp & ADPA_DAC_ENABLE)) | |
82 | return false; | |
83 | ||
84 | if (HAS_PCH_CPT(dev)) | |
85 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
86 | else | |
87 | *pipe = PORT_TO_PIPE(tmp); | |
88 | ||
89 | return true; | |
90 | } | |
91 | ||
6801c18c | 92 | static unsigned int intel_crt_get_flags(struct intel_encoder *encoder) |
045ac3b5 JB |
93 | { |
94 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
95 | struct intel_crt *crt = intel_encoder_to_crt(encoder); | |
96 | u32 tmp, flags = 0; | |
97 | ||
98 | tmp = I915_READ(crt->adpa_reg); | |
99 | ||
100 | if (tmp & ADPA_HSYNC_ACTIVE_HIGH) | |
101 | flags |= DRM_MODE_FLAG_PHSYNC; | |
102 | else | |
103 | flags |= DRM_MODE_FLAG_NHSYNC; | |
104 | ||
105 | if (tmp & ADPA_VSYNC_ACTIVE_HIGH) | |
106 | flags |= DRM_MODE_FLAG_PVSYNC; | |
107 | else | |
108 | flags |= DRM_MODE_FLAG_NVSYNC; | |
109 | ||
6801c18c VS |
110 | return flags; |
111 | } | |
112 | ||
113 | static void intel_crt_get_config(struct intel_encoder *encoder, | |
5cec258b | 114 | struct intel_crtc_state *pipe_config) |
6801c18c VS |
115 | { |
116 | struct drm_device *dev = encoder->base.dev; | |
117 | int dotclock; | |
118 | ||
2d112de7 | 119 | pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); |
18442d08 VS |
120 | |
121 | dotclock = pipe_config->port_clock; | |
122 | ||
6801c18c | 123 | if (HAS_PCH_SPLIT(dev)) |
18442d08 VS |
124 | ironlake_check_encoder_dotclock(pipe_config, dotclock); |
125 | ||
2d112de7 | 126 | pipe_config->base.adjusted_mode.crtc_clock = dotclock; |
045ac3b5 JB |
127 | } |
128 | ||
6801c18c | 129 | static void hsw_crt_get_config(struct intel_encoder *encoder, |
5cec258b | 130 | struct intel_crtc_state *pipe_config) |
6801c18c VS |
131 | { |
132 | intel_ddi_get_config(encoder, pipe_config); | |
133 | ||
2d112de7 | 134 | pipe_config->base.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC | |
6801c18c VS |
135 | DRM_MODE_FLAG_NHSYNC | |
136 | DRM_MODE_FLAG_PVSYNC | | |
137 | DRM_MODE_FLAG_NVSYNC); | |
2d112de7 | 138 | pipe_config->base.adjusted_mode.flags |= intel_crt_get_flags(encoder); |
6801c18c VS |
139 | } |
140 | ||
082717ea DV |
141 | static void hsw_crt_pre_enable(struct intel_encoder *encoder) |
142 | { | |
143 | struct drm_device *dev = encoder->base.dev; | |
144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
145 | ||
146 | WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL already enabled\n"); | |
147 | I915_WRITE(SPLL_CTL, | |
148 | SPLL_PLL_ENABLE | SPLL_PLL_FREQ_1350MHz | SPLL_PLL_SSC); | |
149 | POSTING_READ(SPLL_CTL); | |
150 | udelay(20); | |
151 | } | |
152 | ||
b2cabb0e DV |
153 | /* Note: The caller is required to filter out dpms modes not supported by the |
154 | * platform. */ | |
155 | static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) | |
df0323c4 | 156 | { |
b2cabb0e | 157 | struct drm_device *dev = encoder->base.dev; |
df0323c4 | 158 | struct drm_i915_private *dev_priv = dev->dev_private; |
b2cabb0e | 159 | struct intel_crt *crt = intel_encoder_to_crt(encoder); |
894ed1ec | 160 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
6e3c9717 | 161 | struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode; |
894ed1ec DV |
162 | u32 adpa; |
163 | ||
164 | if (INTEL_INFO(dev)->gen >= 5) | |
165 | adpa = ADPA_HOTPLUG_BITS; | |
166 | else | |
167 | adpa = 0; | |
df0323c4 | 168 | |
894ed1ec DV |
169 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
170 | adpa |= ADPA_HSYNC_ACTIVE_HIGH; | |
171 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) | |
172 | adpa |= ADPA_VSYNC_ACTIVE_HIGH; | |
173 | ||
174 | /* For CPT allow 3 pipe config, for others just use A or B */ | |
175 | if (HAS_PCH_LPT(dev)) | |
176 | ; /* Those bits don't exist here */ | |
177 | else if (HAS_PCH_CPT(dev)) | |
178 | adpa |= PORT_TRANS_SEL_CPT(crtc->pipe); | |
179 | else if (crtc->pipe == 0) | |
180 | adpa |= ADPA_PIPE_A_SELECT; | |
181 | else | |
182 | adpa |= ADPA_PIPE_B_SELECT; | |
183 | ||
184 | if (!HAS_PCH_SPLIT(dev)) | |
185 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
79e53945 | 186 | |
0206e353 | 187 | switch (mode) { |
79e53945 | 188 | case DRM_MODE_DPMS_ON: |
894ed1ec | 189 | adpa |= ADPA_DAC_ENABLE; |
79e53945 JB |
190 | break; |
191 | case DRM_MODE_DPMS_STANDBY: | |
894ed1ec | 192 | adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE; |
79e53945 JB |
193 | break; |
194 | case DRM_MODE_DPMS_SUSPEND: | |
894ed1ec | 195 | adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE; |
79e53945 JB |
196 | break; |
197 | case DRM_MODE_DPMS_OFF: | |
894ed1ec | 198 | adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE; |
79e53945 JB |
199 | break; |
200 | } | |
201 | ||
894ed1ec | 202 | I915_WRITE(crt->adpa_reg, adpa); |
df0323c4 | 203 | } |
2c07245f | 204 | |
637f44d2 AJ |
205 | static void intel_disable_crt(struct intel_encoder *encoder) |
206 | { | |
207 | intel_crt_set_dpms(encoder, DRM_MODE_DPMS_OFF); | |
208 | } | |
209 | ||
abfdc1e3 DV |
210 | |
211 | static void hsw_crt_post_disable(struct intel_encoder *encoder) | |
212 | { | |
213 | struct drm_device *dev = encoder->base.dev; | |
214 | struct drm_i915_private *dev_priv = dev->dev_private; | |
215 | uint32_t val; | |
216 | ||
217 | DRM_DEBUG_KMS("Disabling SPLL\n"); | |
218 | val = I915_READ(SPLL_CTL); | |
219 | WARN_ON(!(val & SPLL_PLL_ENABLE)); | |
220 | I915_WRITE(SPLL_CTL, val & ~SPLL_PLL_ENABLE); | |
221 | POSTING_READ(SPLL_CTL); | |
222 | } | |
223 | ||
637f44d2 AJ |
224 | static void intel_enable_crt(struct intel_encoder *encoder) |
225 | { | |
226 | struct intel_crt *crt = intel_encoder_to_crt(encoder); | |
227 | ||
228 | intel_crt_set_dpms(encoder, crt->connector->base.dpms); | |
229 | } | |
230 | ||
6b1c087b | 231 | /* Special dpms function to support cloning between dvo/sdvo/crt. */ |
b2cabb0e | 232 | static void intel_crt_dpms(struct drm_connector *connector, int mode) |
df0323c4 | 233 | { |
b2cabb0e DV |
234 | struct drm_device *dev = connector->dev; |
235 | struct intel_encoder *encoder = intel_attached_encoder(connector); | |
236 | struct drm_crtc *crtc; | |
237 | int old_dpms; | |
79e53945 | 238 | |
b2cabb0e | 239 | /* PCH platforms and VLV only support on/off. */ |
4a8dece2 | 240 | if (INTEL_INFO(dev)->gen >= 5 && mode != DRM_MODE_DPMS_ON) |
bd9e8413 JB |
241 | mode = DRM_MODE_DPMS_OFF; |
242 | ||
b2cabb0e DV |
243 | if (mode == connector->dpms) |
244 | return; | |
245 | ||
246 | old_dpms = connector->dpms; | |
247 | connector->dpms = mode; | |
248 | ||
249 | /* Only need to change hw state when actually enabled */ | |
250 | crtc = encoder->base.crtc; | |
251 | if (!crtc) { | |
252 | encoder->connectors_active = false; | |
253 | return; | |
79e53945 JB |
254 | } |
255 | ||
b2cabb0e DV |
256 | /* We need the pipe to run for anything but OFF. */ |
257 | if (mode == DRM_MODE_DPMS_OFF) | |
258 | encoder->connectors_active = false; | |
259 | else | |
260 | encoder->connectors_active = true; | |
261 | ||
6b1c087b JN |
262 | /* We call connector dpms manually below in case pipe dpms doesn't |
263 | * change due to cloning. */ | |
b2cabb0e DV |
264 | if (mode < old_dpms) { |
265 | /* From off to on, enable the pipe first. */ | |
266 | intel_crtc_update_dpms(crtc); | |
267 | ||
268 | intel_crt_set_dpms(encoder, mode); | |
269 | } else { | |
270 | intel_crt_set_dpms(encoder, mode); | |
271 | ||
272 | intel_crtc_update_dpms(crtc); | |
273 | } | |
0a91ca29 | 274 | |
b980514c | 275 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
276 | } |
277 | ||
c19de8eb DL |
278 | static enum drm_mode_status |
279 | intel_crt_mode_valid(struct drm_connector *connector, | |
280 | struct drm_display_mode *mode) | |
79e53945 | 281 | { |
6bcdcd9e ZY |
282 | struct drm_device *dev = connector->dev; |
283 | ||
284 | int max_clock = 0; | |
79e53945 JB |
285 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) |
286 | return MODE_NO_DBLESCAN; | |
287 | ||
6bcdcd9e ZY |
288 | if (mode->clock < 25000) |
289 | return MODE_CLOCK_LOW; | |
290 | ||
a6c45cf0 | 291 | if (IS_GEN2(dev)) |
6bcdcd9e ZY |
292 | max_clock = 350000; |
293 | else | |
294 | max_clock = 400000; | |
295 | if (mode->clock > max_clock) | |
296 | return MODE_CLOCK_HIGH; | |
79e53945 | 297 | |
d4b1931c PZ |
298 | /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */ |
299 | if (HAS_PCH_LPT(dev) && | |
300 | (ironlake_get_lanes_required(mode->clock, 270000, 24) > 2)) | |
301 | return MODE_CLOCK_HIGH; | |
302 | ||
79e53945 JB |
303 | return MODE_OK; |
304 | } | |
305 | ||
5bfe2ac0 | 306 | static bool intel_crt_compute_config(struct intel_encoder *encoder, |
5cec258b | 307 | struct intel_crtc_state *pipe_config) |
79e53945 | 308 | { |
5bfe2ac0 DV |
309 | struct drm_device *dev = encoder->base.dev; |
310 | ||
311 | if (HAS_PCH_SPLIT(dev)) | |
312 | pipe_config->has_pch_encoder = true; | |
313 | ||
2a7aceec DV |
314 | /* LPT FDI RX only supports 8bpc. */ |
315 | if (HAS_PCH_LPT(dev)) | |
316 | pipe_config->pipe_bpp = 24; | |
317 | ||
8f7abfd8 | 318 | /* FDI must always be 2.7 GHz */ |
0e50338c DV |
319 | if (HAS_DDI(dev)) { |
320 | pipe_config->ddi_pll_sel = PORT_CLK_SEL_SPLL; | |
8f7abfd8 | 321 | pipe_config->port_clock = 135000 * 2; |
0e50338c | 322 | } |
8f7abfd8 | 323 | |
79e53945 JB |
324 | return true; |
325 | } | |
326 | ||
f2b115e6 | 327 | static bool intel_ironlake_crt_detect_hotplug(struct drm_connector *connector) |
2c07245f ZW |
328 | { |
329 | struct drm_device *dev = connector->dev; | |
e7dbb2f2 | 330 | struct intel_crt *crt = intel_attached_crt(connector); |
2c07245f | 331 | struct drm_i915_private *dev_priv = dev->dev_private; |
e7dbb2f2 | 332 | u32 adpa; |
2c07245f ZW |
333 | bool ret; |
334 | ||
e7dbb2f2 KP |
335 | /* The first time through, trigger an explicit detection cycle */ |
336 | if (crt->force_hotplug_required) { | |
337 | bool turn_off_dac = HAS_PCH_SPLIT(dev); | |
338 | u32 save_adpa; | |
67941da2 | 339 | |
e7dbb2f2 KP |
340 | crt->force_hotplug_required = 0; |
341 | ||
ca54b810 | 342 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
e7dbb2f2 KP |
343 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
344 | ||
345 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
346 | if (turn_off_dac) | |
347 | adpa &= ~ADPA_DAC_ENABLE; | |
348 | ||
ca54b810 | 349 | I915_WRITE(crt->adpa_reg, adpa); |
e7dbb2f2 | 350 | |
ca54b810 | 351 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
e7dbb2f2 KP |
352 | 1000)) |
353 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); | |
354 | ||
355 | if (turn_off_dac) { | |
ca54b810 VS |
356 | I915_WRITE(crt->adpa_reg, save_adpa); |
357 | POSTING_READ(crt->adpa_reg); | |
e7dbb2f2 | 358 | } |
a4a6b901 ZW |
359 | } |
360 | ||
2c07245f | 361 | /* Check the status to see if both blue and green are on now */ |
ca54b810 | 362 | adpa = I915_READ(crt->adpa_reg); |
e7dbb2f2 | 363 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
2c07245f ZW |
364 | ret = true; |
365 | else | |
366 | ret = false; | |
e7dbb2f2 | 367 | DRM_DEBUG_KMS("ironlake hotplug adpa=0x%x, result %d\n", adpa, ret); |
2c07245f | 368 | |
2c07245f | 369 | return ret; |
79e53945 JB |
370 | } |
371 | ||
7d2c24e8 JB |
372 | static bool valleyview_crt_detect_hotplug(struct drm_connector *connector) |
373 | { | |
374 | struct drm_device *dev = connector->dev; | |
ca54b810 | 375 | struct intel_crt *crt = intel_attached_crt(connector); |
7d2c24e8 JB |
376 | struct drm_i915_private *dev_priv = dev->dev_private; |
377 | u32 adpa; | |
378 | bool ret; | |
379 | u32 save_adpa; | |
380 | ||
ca54b810 | 381 | save_adpa = adpa = I915_READ(crt->adpa_reg); |
7d2c24e8 JB |
382 | DRM_DEBUG_KMS("trigger hotplug detect cycle: adpa=0x%x\n", adpa); |
383 | ||
384 | adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER; | |
385 | ||
ca54b810 | 386 | I915_WRITE(crt->adpa_reg, adpa); |
7d2c24e8 | 387 | |
ca54b810 | 388 | if (wait_for((I915_READ(crt->adpa_reg) & ADPA_CRT_HOTPLUG_FORCE_TRIGGER) == 0, |
7d2c24e8 JB |
389 | 1000)) { |
390 | DRM_DEBUG_KMS("timed out waiting for FORCE_TRIGGER"); | |
ca54b810 | 391 | I915_WRITE(crt->adpa_reg, save_adpa); |
7d2c24e8 JB |
392 | } |
393 | ||
394 | /* Check the status to see if both blue and green are on now */ | |
ca54b810 | 395 | adpa = I915_READ(crt->adpa_reg); |
7d2c24e8 JB |
396 | if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0) |
397 | ret = true; | |
398 | else | |
399 | ret = false; | |
400 | ||
401 | DRM_DEBUG_KMS("valleyview hotplug adpa=0x%x, result %d\n", adpa, ret); | |
402 | ||
7d2c24e8 JB |
403 | return ret; |
404 | } | |
405 | ||
79e53945 JB |
406 | /** |
407 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence. | |
408 | * | |
409 | * Not for i915G/i915GM | |
410 | * | |
411 | * \return true if CRT is connected. | |
412 | * \return false if CRT is disconnected. | |
413 | */ | |
414 | static bool intel_crt_detect_hotplug(struct drm_connector *connector) | |
415 | { | |
416 | struct drm_device *dev = connector->dev; | |
417 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7a772c49 AJ |
418 | u32 hotplug_en, orig, stat; |
419 | bool ret = false; | |
771cb081 | 420 | int i, tries = 0; |
2c07245f | 421 | |
bad720ff | 422 | if (HAS_PCH_SPLIT(dev)) |
f2b115e6 | 423 | return intel_ironlake_crt_detect_hotplug(connector); |
2c07245f | 424 | |
7d2c24e8 JB |
425 | if (IS_VALLEYVIEW(dev)) |
426 | return valleyview_crt_detect_hotplug(connector); | |
427 | ||
771cb081 ZY |
428 | /* |
429 | * On 4 series desktop, CRT detect sequence need to be done twice | |
430 | * to get a reliable result. | |
431 | */ | |
79e53945 | 432 | |
771cb081 ZY |
433 | if (IS_G4X(dev) && !IS_GM45(dev)) |
434 | tries = 2; | |
435 | else | |
436 | tries = 1; | |
7a772c49 | 437 | hotplug_en = orig = I915_READ(PORT_HOTPLUG_EN); |
771cb081 ZY |
438 | hotplug_en |= CRT_HOTPLUG_FORCE_DETECT; |
439 | ||
771cb081 | 440 | for (i = 0; i < tries ; i++) { |
771cb081 ZY |
441 | /* turn on the FORCE_DETECT */ |
442 | I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); | |
771cb081 | 443 | /* wait for FORCE_DETECT to go off */ |
913d8d11 CW |
444 | if (wait_for((I915_READ(PORT_HOTPLUG_EN) & |
445 | CRT_HOTPLUG_FORCE_DETECT) == 0, | |
481b6af3 | 446 | 1000)) |
79077319 | 447 | DRM_DEBUG_KMS("timed out waiting for FORCE_DETECT to go off"); |
771cb081 | 448 | } |
79e53945 | 449 | |
7a772c49 AJ |
450 | stat = I915_READ(PORT_HOTPLUG_STAT); |
451 | if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE) | |
452 | ret = true; | |
453 | ||
454 | /* clear the interrupt we just generated, if any */ | |
455 | I915_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS); | |
79e53945 | 456 | |
7a772c49 AJ |
457 | /* and put the bits back */ |
458 | I915_WRITE(PORT_HOTPLUG_EN, orig); | |
459 | ||
460 | return ret; | |
79e53945 JB |
461 | } |
462 | ||
f1a2f5b7 JN |
463 | static struct edid *intel_crt_get_edid(struct drm_connector *connector, |
464 | struct i2c_adapter *i2c) | |
465 | { | |
466 | struct edid *edid; | |
467 | ||
468 | edid = drm_get_edid(connector, i2c); | |
469 | ||
470 | if (!edid && !intel_gmbus_is_forced_bit(i2c)) { | |
471 | DRM_DEBUG_KMS("CRT GMBUS EDID read failed, retry using GPIO bit-banging\n"); | |
472 | intel_gmbus_force_bit(i2c, true); | |
473 | edid = drm_get_edid(connector, i2c); | |
474 | intel_gmbus_force_bit(i2c, false); | |
475 | } | |
476 | ||
477 | return edid; | |
478 | } | |
479 | ||
480 | /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */ | |
481 | static int intel_crt_ddc_get_modes(struct drm_connector *connector, | |
482 | struct i2c_adapter *adapter) | |
483 | { | |
484 | struct edid *edid; | |
ebda95a9 | 485 | int ret; |
f1a2f5b7 JN |
486 | |
487 | edid = intel_crt_get_edid(connector, adapter); | |
488 | if (!edid) | |
489 | return 0; | |
490 | ||
ebda95a9 JN |
491 | ret = intel_connector_update_modes(connector, edid); |
492 | kfree(edid); | |
493 | ||
494 | return ret; | |
f1a2f5b7 JN |
495 | } |
496 | ||
f5afcd3d | 497 | static bool intel_crt_detect_ddc(struct drm_connector *connector) |
79e53945 | 498 | { |
f5afcd3d | 499 | struct intel_crt *crt = intel_attached_crt(connector); |
c9a1c4cd | 500 | struct drm_i915_private *dev_priv = crt->base.base.dev->dev_private; |
a2bd1f54 DV |
501 | struct edid *edid; |
502 | struct i2c_adapter *i2c; | |
79e53945 | 503 | |
a2bd1f54 | 504 | BUG_ON(crt->base.type != INTEL_OUTPUT_ANALOG); |
79e53945 | 505 | |
41aa3448 | 506 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
f1a2f5b7 | 507 | edid = intel_crt_get_edid(connector, i2c); |
a2bd1f54 DV |
508 | |
509 | if (edid) { | |
510 | bool is_digital = edid->input & DRM_EDID_INPUT_DIGITAL; | |
f5afcd3d | 511 | |
f5afcd3d DM |
512 | /* |
513 | * This may be a DVI-I connector with a shared DDC | |
514 | * link between analog and digital outputs, so we | |
515 | * have to check the EDID input spec of the attached device. | |
516 | */ | |
f5afcd3d DM |
517 | if (!is_digital) { |
518 | DRM_DEBUG_KMS("CRT detected via DDC:0x50 [EDID]\n"); | |
519 | return true; | |
520 | } | |
a2bd1f54 DV |
521 | |
522 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [EDID reports a digital panel]\n"); | |
523 | } else { | |
524 | DRM_DEBUG_KMS("CRT not detected via DDC:0x50 [no valid EDID found]\n"); | |
6ec3d0c0 CW |
525 | } |
526 | ||
a2bd1f54 DV |
527 | kfree(edid); |
528 | ||
6ec3d0c0 | 529 | return false; |
79e53945 JB |
530 | } |
531 | ||
e4a5d54f | 532 | static enum drm_connector_status |
7173188d | 533 | intel_crt_load_detect(struct intel_crt *crt) |
e4a5d54f | 534 | { |
7173188d | 535 | struct drm_device *dev = crt->base.base.dev; |
e4a5d54f | 536 | struct drm_i915_private *dev_priv = dev->dev_private; |
7173188d | 537 | uint32_t pipe = to_intel_crtc(crt->base.base.crtc)->pipe; |
e4a5d54f ML |
538 | uint32_t save_bclrpat; |
539 | uint32_t save_vtotal; | |
540 | uint32_t vtotal, vactive; | |
541 | uint32_t vsample; | |
542 | uint32_t vblank, vblank_start, vblank_end; | |
543 | uint32_t dsl; | |
544 | uint32_t bclrpat_reg; | |
545 | uint32_t vtotal_reg; | |
546 | uint32_t vblank_reg; | |
547 | uint32_t vsync_reg; | |
548 | uint32_t pipeconf_reg; | |
549 | uint32_t pipe_dsl_reg; | |
550 | uint8_t st00; | |
551 | enum drm_connector_status status; | |
552 | ||
6ec3d0c0 CW |
553 | DRM_DEBUG_KMS("starting load-detect on CRT\n"); |
554 | ||
9db4a9c7 JB |
555 | bclrpat_reg = BCLRPAT(pipe); |
556 | vtotal_reg = VTOTAL(pipe); | |
557 | vblank_reg = VBLANK(pipe); | |
558 | vsync_reg = VSYNC(pipe); | |
559 | pipeconf_reg = PIPECONF(pipe); | |
560 | pipe_dsl_reg = PIPEDSL(pipe); | |
e4a5d54f ML |
561 | |
562 | save_bclrpat = I915_READ(bclrpat_reg); | |
563 | save_vtotal = I915_READ(vtotal_reg); | |
564 | vblank = I915_READ(vblank_reg); | |
565 | ||
566 | vtotal = ((save_vtotal >> 16) & 0xfff) + 1; | |
567 | vactive = (save_vtotal & 0x7ff) + 1; | |
568 | ||
569 | vblank_start = (vblank & 0xfff) + 1; | |
570 | vblank_end = ((vblank >> 16) & 0xfff) + 1; | |
571 | ||
572 | /* Set the border color to purple. */ | |
573 | I915_WRITE(bclrpat_reg, 0x500050); | |
574 | ||
a6c45cf0 | 575 | if (!IS_GEN2(dev)) { |
e4a5d54f ML |
576 | uint32_t pipeconf = I915_READ(pipeconf_reg); |
577 | I915_WRITE(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER); | |
19c55da1 | 578 | POSTING_READ(pipeconf_reg); |
e4a5d54f ML |
579 | /* Wait for next Vblank to substitue |
580 | * border color for Color info */ | |
9d0498a2 | 581 | intel_wait_for_vblank(dev, pipe); |
e4a5d54f ML |
582 | st00 = I915_READ8(VGA_MSR_WRITE); |
583 | status = ((st00 & (1 << 4)) != 0) ? | |
584 | connector_status_connected : | |
585 | connector_status_disconnected; | |
586 | ||
587 | I915_WRITE(pipeconf_reg, pipeconf); | |
588 | } else { | |
589 | bool restore_vblank = false; | |
590 | int count, detect; | |
591 | ||
592 | /* | |
593 | * If there isn't any border, add some. | |
594 | * Yes, this will flicker | |
595 | */ | |
596 | if (vblank_start <= vactive && vblank_end >= vtotal) { | |
597 | uint32_t vsync = I915_READ(vsync_reg); | |
598 | uint32_t vsync_start = (vsync & 0xffff) + 1; | |
599 | ||
600 | vblank_start = vsync_start; | |
601 | I915_WRITE(vblank_reg, | |
602 | (vblank_start - 1) | | |
603 | ((vblank_end - 1) << 16)); | |
604 | restore_vblank = true; | |
605 | } | |
606 | /* sample in the vertical border, selecting the larger one */ | |
607 | if (vblank_start - vactive >= vtotal - vblank_end) | |
608 | vsample = (vblank_start + vactive) >> 1; | |
609 | else | |
610 | vsample = (vtotal + vblank_end) >> 1; | |
611 | ||
612 | /* | |
613 | * Wait for the border to be displayed | |
614 | */ | |
615 | while (I915_READ(pipe_dsl_reg) >= vactive) | |
616 | ; | |
617 | while ((dsl = I915_READ(pipe_dsl_reg)) <= vsample) | |
618 | ; | |
619 | /* | |
620 | * Watch ST00 for an entire scanline | |
621 | */ | |
622 | detect = 0; | |
623 | count = 0; | |
624 | do { | |
625 | count++; | |
626 | /* Read the ST00 VGA status register */ | |
627 | st00 = I915_READ8(VGA_MSR_WRITE); | |
628 | if (st00 & (1 << 4)) | |
629 | detect++; | |
630 | } while ((I915_READ(pipe_dsl_reg) == dsl)); | |
631 | ||
632 | /* restore vblank if necessary */ | |
633 | if (restore_vblank) | |
634 | I915_WRITE(vblank_reg, vblank); | |
635 | /* | |
636 | * If more than 3/4 of the scanline detected a monitor, | |
637 | * then it is assumed to be present. This works even on i830, | |
638 | * where there isn't any way to force the border color across | |
639 | * the screen | |
640 | */ | |
641 | status = detect * 4 > count * 3 ? | |
642 | connector_status_connected : | |
643 | connector_status_disconnected; | |
644 | } | |
645 | ||
646 | /* Restore previous settings */ | |
647 | I915_WRITE(bclrpat_reg, save_bclrpat); | |
648 | ||
649 | return status; | |
650 | } | |
651 | ||
7b334fcb | 652 | static enum drm_connector_status |
930a9e28 | 653 | intel_crt_detect(struct drm_connector *connector, bool force) |
79e53945 JB |
654 | { |
655 | struct drm_device *dev = connector->dev; | |
c19a0df2 | 656 | struct drm_i915_private *dev_priv = dev->dev_private; |
c9a1c4cd | 657 | struct intel_crt *crt = intel_attached_crt(connector); |
671dedd2 ID |
658 | struct intel_encoder *intel_encoder = &crt->base; |
659 | enum intel_display_power_domain power_domain; | |
e4a5d54f | 660 | enum drm_connector_status status; |
e95c8438 | 661 | struct intel_load_detect_pipe tmp; |
51fd371b | 662 | struct drm_modeset_acquire_ctx ctx; |
79e53945 | 663 | |
164c8598 | 664 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] force=%d\n", |
c23cc417 | 665 | connector->base.id, connector->name, |
164c8598 CW |
666 | force); |
667 | ||
671dedd2 ID |
668 | power_domain = intel_display_port_power_domain(intel_encoder); |
669 | intel_display_power_get(dev_priv, power_domain); | |
670 | ||
a6c45cf0 | 671 | if (I915_HAS_HOTPLUG(dev)) { |
aaa37730 DV |
672 | /* We can not rely on the HPD pin always being correctly wired |
673 | * up, for example many KVM do not pass it through, and so | |
674 | * only trust an assertion that the monitor is connected. | |
675 | */ | |
6ec3d0c0 CW |
676 | if (intel_crt_detect_hotplug(connector)) { |
677 | DRM_DEBUG_KMS("CRT detected via hotplug\n"); | |
c19a0df2 PZ |
678 | status = connector_status_connected; |
679 | goto out; | |
aaa37730 | 680 | } else |
e7dbb2f2 | 681 | DRM_DEBUG_KMS("CRT not detected via hotplug\n"); |
79e53945 JB |
682 | } |
683 | ||
c19a0df2 PZ |
684 | if (intel_crt_detect_ddc(connector)) { |
685 | status = connector_status_connected; | |
686 | goto out; | |
687 | } | |
79e53945 | 688 | |
aaa37730 DV |
689 | /* Load detection is broken on HPD capable machines. Whoever wants a |
690 | * broken monitor (without edid) to work behind a broken kvm (that fails | |
691 | * to have the right resistors for HP detection) needs to fix this up. | |
692 | * For now just bail out. */ | |
c19a0df2 PZ |
693 | if (I915_HAS_HOTPLUG(dev)) { |
694 | status = connector_status_disconnected; | |
695 | goto out; | |
696 | } | |
aaa37730 | 697 | |
c19a0df2 PZ |
698 | if (!force) { |
699 | status = connector->status; | |
700 | goto out; | |
701 | } | |
7b334fcb | 702 | |
208bf9fd VS |
703 | drm_modeset_acquire_init(&ctx, 0); |
704 | ||
e4a5d54f | 705 | /* for pre-945g platforms use load detect */ |
51fd371b | 706 | if (intel_get_load_detect_pipe(connector, NULL, &tmp, &ctx)) { |
e95c8438 DV |
707 | if (intel_crt_detect_ddc(connector)) |
708 | status = connector_status_connected; | |
709 | else | |
710 | status = intel_crt_load_detect(crt); | |
208bf9fd | 711 | intel_release_load_detect_pipe(connector, &tmp); |
e95c8438 DV |
712 | } else |
713 | status = connector_status_unknown; | |
e4a5d54f | 714 | |
208bf9fd VS |
715 | drm_modeset_drop_locks(&ctx); |
716 | drm_modeset_acquire_fini(&ctx); | |
717 | ||
c19a0df2 | 718 | out: |
671dedd2 | 719 | intel_display_power_put(dev_priv, power_domain); |
e4a5d54f | 720 | return status; |
79e53945 JB |
721 | } |
722 | ||
723 | static void intel_crt_destroy(struct drm_connector *connector) | |
724 | { | |
79e53945 JB |
725 | drm_connector_cleanup(connector); |
726 | kfree(connector); | |
727 | } | |
728 | ||
729 | static int intel_crt_get_modes(struct drm_connector *connector) | |
730 | { | |
8e4d36b9 | 731 | struct drm_device *dev = connector->dev; |
f899fc64 | 732 | struct drm_i915_private *dev_priv = dev->dev_private; |
671dedd2 ID |
733 | struct intel_crt *crt = intel_attached_crt(connector); |
734 | struct intel_encoder *intel_encoder = &crt->base; | |
735 | enum intel_display_power_domain power_domain; | |
890f3359 | 736 | int ret; |
3bd7d909 | 737 | struct i2c_adapter *i2c; |
8e4d36b9 | 738 | |
671dedd2 ID |
739 | power_domain = intel_display_port_power_domain(intel_encoder); |
740 | intel_display_power_get(dev_priv, power_domain); | |
741 | ||
41aa3448 | 742 | i2c = intel_gmbus_get_adapter(dev_priv, dev_priv->vbt.crt_ddc_pin); |
f1a2f5b7 | 743 | ret = intel_crt_ddc_get_modes(connector, i2c); |
8e4d36b9 | 744 | if (ret || !IS_G4X(dev)) |
671dedd2 | 745 | goto out; |
8e4d36b9 | 746 | |
8e4d36b9 | 747 | /* Try to probe digital port for output in DVI-I -> VGA mode. */ |
3bd7d909 | 748 | i2c = intel_gmbus_get_adapter(dev_priv, GMBUS_PORT_DPB); |
671dedd2 ID |
749 | ret = intel_crt_ddc_get_modes(connector, i2c); |
750 | ||
751 | out: | |
752 | intel_display_power_put(dev_priv, power_domain); | |
753 | ||
754 | return ret; | |
79e53945 JB |
755 | } |
756 | ||
757 | static int intel_crt_set_property(struct drm_connector *connector, | |
758 | struct drm_property *property, | |
759 | uint64_t value) | |
760 | { | |
79e53945 JB |
761 | return 0; |
762 | } | |
763 | ||
f3269058 CW |
764 | static void intel_crt_reset(struct drm_connector *connector) |
765 | { | |
766 | struct drm_device *dev = connector->dev; | |
2e938892 | 767 | struct drm_i915_private *dev_priv = dev->dev_private; |
f3269058 CW |
768 | struct intel_crt *crt = intel_attached_crt(connector); |
769 | ||
10603caa | 770 | if (INTEL_INFO(dev)->gen >= 5) { |
2e938892 DV |
771 | u32 adpa; |
772 | ||
ca54b810 | 773 | adpa = I915_READ(crt->adpa_reg); |
2e938892 DV |
774 | adpa &= ~ADPA_CRT_HOTPLUG_MASK; |
775 | adpa |= ADPA_HOTPLUG_BITS; | |
ca54b810 VS |
776 | I915_WRITE(crt->adpa_reg, adpa); |
777 | POSTING_READ(crt->adpa_reg); | |
2e938892 | 778 | |
0039a4b3 | 779 | DRM_DEBUG_KMS("crt adpa set to 0x%x\n", adpa); |
f3269058 | 780 | crt->force_hotplug_required = 1; |
2e938892 DV |
781 | } |
782 | ||
f3269058 CW |
783 | } |
784 | ||
79e53945 JB |
785 | /* |
786 | * Routines for controlling stuff on the analog port | |
787 | */ | |
788 | ||
79e53945 | 789 | static const struct drm_connector_funcs intel_crt_connector_funcs = { |
f3269058 | 790 | .reset = intel_crt_reset, |
b2cabb0e | 791 | .dpms = intel_crt_dpms, |
79e53945 JB |
792 | .detect = intel_crt_detect, |
793 | .fill_modes = drm_helper_probe_single_connector_modes, | |
794 | .destroy = intel_crt_destroy, | |
795 | .set_property = intel_crt_set_property, | |
c6f95f27 | 796 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
2545e4a6 | 797 | .atomic_get_property = intel_connector_atomic_get_property, |
79e53945 JB |
798 | }; |
799 | ||
800 | static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = { | |
801 | .mode_valid = intel_crt_mode_valid, | |
802 | .get_modes = intel_crt_get_modes, | |
df0e9248 | 803 | .best_encoder = intel_best_encoder, |
79e53945 JB |
804 | }; |
805 | ||
79e53945 | 806 | static const struct drm_encoder_funcs intel_crt_enc_funcs = { |
ea5b213a | 807 | .destroy = intel_encoder_destroy, |
79e53945 JB |
808 | }; |
809 | ||
bbe1c274 | 810 | static int intel_no_crt_dmi_callback(const struct dmi_system_id *id) |
8ca4013d | 811 | { |
bc0daf48 | 812 | DRM_INFO("Skipping CRT initialization for %s\n", id->ident); |
8ca4013d DL |
813 | return 1; |
814 | } | |
815 | ||
816 | static const struct dmi_system_id intel_no_crt[] = { | |
817 | { | |
818 | .callback = intel_no_crt_dmi_callback, | |
819 | .ident = "ACER ZGB", | |
820 | .matches = { | |
821 | DMI_MATCH(DMI_SYS_VENDOR, "ACER"), | |
822 | DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"), | |
823 | }, | |
824 | }, | |
10b6ee4a GC |
825 | { |
826 | .callback = intel_no_crt_dmi_callback, | |
827 | .ident = "DELL XPS 8700", | |
828 | .matches = { | |
829 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
830 | DMI_MATCH(DMI_PRODUCT_NAME, "XPS 8700"), | |
831 | }, | |
832 | }, | |
8ca4013d DL |
833 | { } |
834 | }; | |
835 | ||
79e53945 JB |
836 | void intel_crt_init(struct drm_device *dev) |
837 | { | |
838 | struct drm_connector *connector; | |
c9a1c4cd | 839 | struct intel_crt *crt; |
454c1ca8 | 840 | struct intel_connector *intel_connector; |
db545019 | 841 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 842 | |
8ca4013d DL |
843 | /* Skip machines without VGA that falsely report hotplug events */ |
844 | if (dmi_check_system(intel_no_crt)) | |
845 | return; | |
846 | ||
c9a1c4cd CW |
847 | crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL); |
848 | if (!crt) | |
79e53945 JB |
849 | return; |
850 | ||
b14c5679 | 851 | intel_connector = kzalloc(sizeof(*intel_connector), GFP_KERNEL); |
454c1ca8 | 852 | if (!intel_connector) { |
c9a1c4cd | 853 | kfree(crt); |
454c1ca8 ZW |
854 | return; |
855 | } | |
856 | ||
857 | connector = &intel_connector->base; | |
637f44d2 | 858 | crt->connector = intel_connector; |
454c1ca8 | 859 | drm_connector_init(dev, &intel_connector->base, |
79e53945 JB |
860 | &intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA); |
861 | ||
c9a1c4cd | 862 | drm_encoder_init(dev, &crt->base.base, &intel_crt_enc_funcs, |
79e53945 JB |
863 | DRM_MODE_ENCODER_DAC); |
864 | ||
c9a1c4cd | 865 | intel_connector_attach_encoder(intel_connector, &crt->base); |
79e53945 | 866 | |
c9a1c4cd | 867 | crt->base.type = INTEL_OUTPUT_ANALOG; |
301ea74a | 868 | crt->base.cloneable = (1 << INTEL_OUTPUT_DVO) | (1 << INTEL_OUTPUT_HDMI); |
d63fa0dc | 869 | if (IS_I830(dev)) |
59c859d6 ED |
870 | crt->base.crtc_mask = (1 << 0); |
871 | else | |
0826874a | 872 | crt->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
59c859d6 | 873 | |
dbb02575 DV |
874 | if (IS_GEN2(dev)) |
875 | connector->interlace_allowed = 0; | |
876 | else | |
877 | connector->interlace_allowed = 1; | |
79e53945 JB |
878 | connector->doublescan_allowed = 0; |
879 | ||
df0323c4 | 880 | if (HAS_PCH_SPLIT(dev)) |
540a8950 DV |
881 | crt->adpa_reg = PCH_ADPA; |
882 | else if (IS_VALLEYVIEW(dev)) | |
883 | crt->adpa_reg = VLV_ADPA; | |
df0323c4 | 884 | else |
540a8950 DV |
885 | crt->adpa_reg = ADPA; |
886 | ||
5bfe2ac0 | 887 | crt->base.compute_config = intel_crt_compute_config; |
2124604b DV |
888 | crt->base.disable = intel_disable_crt; |
889 | crt->base.enable = intel_enable_crt; | |
1d843f9d EE |
890 | if (I915_HAS_HOTPLUG(dev)) |
891 | crt->base.hpd_pin = HPD_CRT; | |
a2985791 VS |
892 | if (HAS_DDI(dev)) { |
893 | crt->base.get_config = hsw_crt_get_config; | |
4eda01b2 | 894 | crt->base.get_hw_state = intel_ddi_get_hw_state; |
082717ea | 895 | crt->base.pre_enable = hsw_crt_pre_enable; |
abfdc1e3 | 896 | crt->base.post_disable = hsw_crt_post_disable; |
a2985791 VS |
897 | } else { |
898 | crt->base.get_config = intel_crt_get_config; | |
4eda01b2 | 899 | crt->base.get_hw_state = intel_crt_get_hw_state; |
a2985791 | 900 | } |
e403fc94 | 901 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
4932e2c3 | 902 | intel_connector->unregister = intel_connector_unregister; |
df0323c4 | 903 | |
79e53945 JB |
904 | drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs); |
905 | ||
34ea3d38 | 906 | drm_connector_register(connector); |
b01f2c3a | 907 | |
821450c6 EE |
908 | if (!I915_HAS_HOTPLUG(dev)) |
909 | intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT; | |
eb1f8e4f | 910 | |
e7dbb2f2 KP |
911 | /* |
912 | * Configure the automatic hotplug detection stuff | |
913 | */ | |
914 | crt->force_hotplug_required = 0; | |
e7dbb2f2 | 915 | |
68d18ad7 | 916 | /* |
3e68320e DL |
917 | * TODO: find a proper way to discover whether we need to set the the |
918 | * polarity and link reversal bits or not, instead of relying on the | |
919 | * BIOS. | |
68d18ad7 | 920 | */ |
3e68320e DL |
921 | if (HAS_PCH_LPT(dev)) { |
922 | u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT | | |
923 | FDI_RX_LINK_REVERSAL_OVERRIDE; | |
924 | ||
925 | dev_priv->fdi_rx_config = I915_READ(_FDI_RXA_CTL) & fdi_config; | |
926 | } | |
754970ee DV |
927 | |
928 | intel_crt_reset(connector); | |
79e53945 | 929 | } |