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Merge tag 'pm-extra-4.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael...
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
f8896f5d 34 u8 i_boost; /* SKL: I_boost; valid: 0x0, 0x1, 0x3, 0x7 */
10122051
JN		 35};
36
45244b87
ED		 37/* HDMI/DVI modes ignore everything but the last 2 items. So we share
38 * them for both DP and FDI transports, allowing those ports to
39 * automatically adapt to HDMI connections as well
40 */
10122051 41static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
f8896f5d
DW		 42 { 0x00FFFFFF, 0x0006000E, 0x0 },
43 { 0x00D75FFF, 0x0005000A, 0x0 },
44 { 0x00C30FFF, 0x00040006, 0x0 },
45 { 0x80AAAFFF, 0x000B0000, 0x0 },
46 { 0x00FFFFFF, 0x0005000A, 0x0 },
47 { 0x00D75FFF, 0x000C0004, 0x0 },
48 { 0x80C30FFF, 0x000B0000, 0x0 },
49 { 0x00FFFFFF, 0x00040006, 0x0 },
50 { 0x80D75FFF, 0x000B0000, 0x0 },
45244b87
ED		 51};
52
10122051 53static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
f8896f5d
DW		 54 { 0x00FFFFFF, 0x0007000E, 0x0 },
55 { 0x00D75FFF, 0x000F000A, 0x0 },
56 { 0x00C30FFF, 0x00060006, 0x0 },
57 { 0x00AAAFFF, 0x001E0000, 0x0 },
58 { 0x00FFFFFF, 0x000F000A, 0x0 },
59 { 0x00D75FFF, 0x00160004, 0x0 },
60 { 0x00C30FFF, 0x001E0000, 0x0 },
61 { 0x00FFFFFF, 0x00060006, 0x0 },
62 { 0x00D75FFF, 0x001E0000, 0x0 },
6acab15a
PZ		 63};
64
10122051
JN		 65static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
66 /* Idx NT mV d T mV d db */
f8896f5d
DW		 67 { 0x00FFFFFF, 0x0006000E, 0x0 },/* 0: 400 400 0 */
68 { 0x00E79FFF, 0x000E000C, 0x0 },/* 1: 400 500 2 */
69 { 0x00D75FFF, 0x0005000A, 0x0 },/* 2: 400 600 3.5 */
70 { 0x00FFFFFF, 0x0005000A, 0x0 },/* 3: 600 600 0 */
71 { 0x00E79FFF, 0x001D0007, 0x0 },/* 4: 600 750 2 */
72 { 0x00D75FFF, 0x000C0004, 0x0 },/* 5: 600 900 3.5 */
73 { 0x00FFFFFF, 0x00040006, 0x0 },/* 6: 800 800 0 */
74 { 0x80E79FFF, 0x00030002, 0x0 },/* 7: 800 1000 2 */
75 { 0x00FFFFFF, 0x00140005, 0x0 },/* 8: 850 850 0 */
76 { 0x00FFFFFF, 0x000C0004, 0x0 },/* 9: 900 900 0 */
77 { 0x00FFFFFF, 0x001C0003, 0x0 },/* 10: 950 950 0 */
78 { 0x80FFFFFF, 0x00030002, 0x0 },/* 11: 1000 1000 0 */
45244b87
ED		 79};
80
10122051 81static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
f8896f5d
DW		 82 { 0x00FFFFFF, 0x00000012, 0x0 },
83 { 0x00EBAFFF, 0x00020011, 0x0 },
84 { 0x00C71FFF, 0x0006000F, 0x0 },
85 { 0x00AAAFFF, 0x000E000A, 0x0 },
86 { 0x00FFFFFF, 0x00020011, 0x0 },
87 { 0x00DB6FFF, 0x0005000F, 0x0 },
88 { 0x00BEEFFF, 0x000A000C, 0x0 },
89 { 0x00FFFFFF, 0x0005000F, 0x0 },
90 { 0x00DB6FFF, 0x000A000C, 0x0 },
300644c7
PZ		 91};
92
10122051 93static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
f8896f5d
DW		 94 { 0x00FFFFFF, 0x0007000E, 0x0 },
95 { 0x00D75FFF, 0x000E000A, 0x0 },
96 { 0x00BEFFFF, 0x00140006, 0x0 },
97 { 0x80B2CFFF, 0x001B0002, 0x0 },
98 { 0x00FFFFFF, 0x000E000A, 0x0 },
99 { 0x00DB6FFF, 0x00160005, 0x0 },
100 { 0x80C71FFF, 0x001A0002, 0x0 },
101 { 0x00F7DFFF, 0x00180004, 0x0 },
102 { 0x80D75FFF, 0x001B0002, 0x0 },
e58623cb
AR		 103};
104
10122051 105static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
f8896f5d
DW		 106 { 0x00FFFFFF, 0x0001000E, 0x0 },
107 { 0x00D75FFF, 0x0004000A, 0x0 },
108 { 0x00C30FFF, 0x00070006, 0x0 },
109 { 0x00AAAFFF, 0x000C0000, 0x0 },
110 { 0x00FFFFFF, 0x0004000A, 0x0 },
111 { 0x00D75FFF, 0x00090004, 0x0 },
112 { 0x00C30FFF, 0x000C0000, 0x0 },
113 { 0x00FFFFFF, 0x00070006, 0x0 },
114 { 0x00D75FFF, 0x000C0000, 0x0 },
e58623cb
AR		 115};
116
10122051
JN		 117static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
118 /* Idx NT mV d T mV df db */
f8896f5d
DW		 119 { 0x00FFFFFF, 0x0007000E, 0x0 },/* 0: 400 400 0 */
120 { 0x00D75FFF, 0x000E000A, 0x0 },/* 1: 400 600 3.5 */
121 { 0x00BEFFFF, 0x00140006, 0x0 },/* 2: 400 800 6 */
122 { 0x00FFFFFF, 0x0009000D, 0x0 },/* 3: 450 450 0 */
123 { 0x00FFFFFF, 0x000E000A, 0x0 },/* 4: 600 600 0 */
124 { 0x00D7FFFF, 0x00140006, 0x0 },/* 5: 600 800 2.5 */
125 { 0x80CB2FFF, 0x001B0002, 0x0 },/* 6: 600 1000 4.5 */
126 { 0x00FFFFFF, 0x00140006, 0x0 },/* 7: 800 800 0 */
127 { 0x80E79FFF, 0x001B0002, 0x0 },/* 8: 800 1000 2 */
128 { 0x80FFFFFF, 0x001B0002, 0x0 },/* 9: 1000 1000 0 */
a26aa8ba
DL		 129};
130
5f8b2531 131/* Skylake H and S */
7f88e3af 132static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
f8896f5d
DW		 133 { 0x00002016, 0x000000A0, 0x0 },
134 { 0x00005012, 0x0000009B, 0x0 },
135 { 0x00007011, 0x00000088, 0x0 },
d7097cff 136 { 0x80009010, 0x000000C0, 0x1 },
f8896f5d
DW		 137 { 0x00002016, 0x0000009B, 0x0 },
138 { 0x00005012, 0x00000088, 0x0 },
d7097cff 139 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 140 { 0x00002016, 0x000000DF, 0x0 },
d7097cff 141 { 0x80005012, 0x000000C0, 0x1 },
7f88e3af
DL		 142};
143
f8896f5d
DW		 144/* Skylake U */
145static const struct ddi_buf_trans skl_u_ddi_translations_dp[] = {
5f8b2531 146 { 0x0000201B, 0x000000A2, 0x0 },
f8896f5d 147 { 0x00005012, 0x00000088, 0x0 },
63ebce1f 148 { 0x80007011, 0x000000CD, 0x0 },
d7097cff 149 { 0x80009010, 0x000000C0, 0x1 },
5f8b2531 150 { 0x0000201B, 0x0000009D, 0x0 },
d7097cff
RV		 151 { 0x80005012, 0x000000C0, 0x1 },
152 { 0x80007011, 0x000000C0, 0x1 },
f8896f5d 153 { 0x00002016, 0x00000088, 0x0 },
d7097cff 154 { 0x80005012, 0x000000C0, 0x1 },
f8896f5d
DW		 155};
156
5f8b2531
RV		 157/* Skylake Y */
158static const struct ddi_buf_trans skl_y_ddi_translations_dp[] = {
f8896f5d
DW		 159 { 0x00000018, 0x000000A2, 0x0 },
160 { 0x00005012, 0x00000088, 0x0 },
63ebce1f 161 { 0x80007011, 0x000000CD, 0x0 },
d7097cff 162 { 0x80009010, 0x000000C0, 0x3 },
f8896f5d 163 { 0x00000018, 0x0000009D, 0x0 },
d7097cff
RV		 164 { 0x80005012, 0x000000C0, 0x3 },
165 { 0x80007011, 0x000000C0, 0x3 },
f8896f5d 166 { 0x00000018, 0x00000088, 0x0 },
d7097cff 167 { 0x80005012, 0x000000C0, 0x3 },
f8896f5d
DW		 168};
169
170/*
5f8b2531 171 * Skylake H and S
f8896f5d
DW		 172 * eDP 1.4 low vswing translation parameters
173 */
7ad14a29 174static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
f8896f5d
DW		 175 { 0x00000018, 0x000000A8, 0x0 },
176 { 0x00004013, 0x000000A9, 0x0 },
177 { 0x00007011, 0x000000A2, 0x0 },
178 { 0x00009010, 0x0000009C, 0x0 },
179 { 0x00000018, 0x000000A9, 0x0 },
180 { 0x00006013, 0x000000A2, 0x0 },
181 { 0x00007011, 0x000000A6, 0x0 },
182 { 0x00000018, 0x000000AB, 0x0 },
183 { 0x00007013, 0x0000009F, 0x0 },
184 { 0x00000018, 0x000000DF, 0x0 },
185};
186
187/*
188 * Skylake U
189 * eDP 1.4 low vswing translation parameters
190 */
191static const struct ddi_buf_trans skl_u_ddi_translations_edp[] = {
192 { 0x00000018, 0x000000A8, 0x0 },
193 { 0x00004013, 0x000000A9, 0x0 },
194 { 0x00007011, 0x000000A2, 0x0 },
195 { 0x00009010, 0x0000009C, 0x0 },
196 { 0x00000018, 0x000000A9, 0x0 },
197 { 0x00006013, 0x000000A2, 0x0 },
198 { 0x00007011, 0x000000A6, 0x0 },
199 { 0x00002016, 0x000000AB, 0x0 },
200 { 0x00005013, 0x0000009F, 0x0 },
201 { 0x00000018, 0x000000DF, 0x0 },
7ad14a29
SJ		 202};
203
f8896f5d 204/*
5f8b2531 205 * Skylake Y
f8896f5d
DW		 206 * eDP 1.4 low vswing translation parameters
207 */
5f8b2531 208static const struct ddi_buf_trans skl_y_ddi_translations_edp[] = {
f8896f5d
DW		 209 { 0x00000018, 0x000000A8, 0x0 },
210 { 0x00004013, 0x000000AB, 0x0 },
211 { 0x00007011, 0x000000A4, 0x0 },
212 { 0x00009010, 0x000000DF, 0x0 },
213 { 0x00000018, 0x000000AA, 0x0 },
214 { 0x00006013, 0x000000A4, 0x0 },
215 { 0x00007011, 0x0000009D, 0x0 },
216 { 0x00000018, 0x000000A0, 0x0 },
217 { 0x00006012, 0x000000DF, 0x0 },
218 { 0x00000018, 0x0000008A, 0x0 },
219};
7ad14a29 220
5f8b2531 221/* Skylake U, H and S */
7f88e3af 222static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
f8896f5d
DW		 223 { 0x00000018, 0x000000AC, 0x0 },
224 { 0x00005012, 0x0000009D, 0x0 },
225 { 0x00007011, 0x00000088, 0x0 },
226 { 0x00000018, 0x000000A1, 0x0 },
227 { 0x00000018, 0x00000098, 0x0 },
228 { 0x00004013, 0x00000088, 0x0 },
2e78416e 229 { 0x80006012, 0x000000CD, 0x1 },
f8896f5d 230 { 0x00000018, 0x000000DF, 0x0 },
2e78416e
RV		 231 { 0x80003015, 0x000000CD, 0x1 }, /* Default */
232 { 0x80003015, 0x000000C0, 0x1 },
233 { 0x80000018, 0x000000C0, 0x1 },
f8896f5d
DW		 234};
235
5f8b2531
RV		 236/* Skylake Y */
237static const struct ddi_buf_trans skl_y_ddi_translations_hdmi[] = {
f8896f5d
DW		 238 { 0x00000018, 0x000000A1, 0x0 },
239 { 0x00005012, 0x000000DF, 0x0 },
2e78416e 240 { 0x80007011, 0x000000CB, 0x3 },
f8896f5d
DW		 241 { 0x00000018, 0x000000A4, 0x0 },
242 { 0x00000018, 0x0000009D, 0x0 },
243 { 0x00004013, 0x00000080, 0x0 },
2e78416e 244 { 0x80006013, 0x000000C0, 0x3 },
f8896f5d 245 { 0x00000018, 0x0000008A, 0x0 },
2e78416e
RV		 246 { 0x80003015, 0x000000C0, 0x3 }, /* Default */
247 { 0x80003015, 0x000000C0, 0x3 },
248 { 0x80000018, 0x000000C0, 0x3 },
7f88e3af
DL		 249};
250
96fb9f9b
VK		 251struct bxt_ddi_buf_trans {
252 u32 margin; /* swing value */
253 u32 scale; /* scale value */
254 u32 enable; /* scale enable */
255 u32 deemphasis;
256 bool default_index; /* true if the entry represents default value */
257};
258
96fb9f9b
VK		 259static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
260 /* Idx NT mV diff db */
fe4c63c8
ID		 261 { 52, 0x9A, 0, 128, true }, /* 0: 400 0 */
262 { 78, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
263 { 104, 0x9A, 0, 64, false }, /* 2: 400 6 */
264 { 154, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
265 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
266 { 116, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
267 { 154, 0x9A, 0, 64, false }, /* 6: 600 6 */
268 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
269 { 154, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
f8896f5d 270 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
96fb9f9b
VK		 271};
272
d9d7000d
SJ		 273static const struct bxt_ddi_buf_trans bxt_ddi_translations_edp[] = {
274 /* Idx NT mV diff db */
275 { 26, 0, 0, 128, false }, /* 0: 200 0 */
276 { 38, 0, 0, 112, false }, /* 1: 200 1.5 */
277 { 48, 0, 0, 96, false }, /* 2: 200 4 */
278 { 54, 0, 0, 69, false }, /* 3: 200 6 */
279 { 32, 0, 0, 128, false }, /* 4: 250 0 */
280 { 48, 0, 0, 104, false }, /* 5: 250 1.5 */
281 { 54, 0, 0, 85, false }, /* 6: 250 4 */
282 { 43, 0, 0, 128, false }, /* 7: 300 0 */
283 { 54, 0, 0, 101, false }, /* 8: 300 1.5 */
284 { 48, 0, 0, 128, false }, /* 9: 300 0 */
285};
286
96fb9f9b
VK		 287/* BSpec has 2 recommended values - entries 0 and 8.
288 * Using the entry with higher vswing.
289 */
290static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
291 /* Idx NT mV diff db */
fe4c63c8
ID		 292 { 52, 0x9A, 0, 128, false }, /* 0: 400 0 */
293 { 52, 0x9A, 0, 85, false }, /* 1: 400 3.5 */
294 { 52, 0x9A, 0, 64, false }, /* 2: 400 6 */
295 { 42, 0x9A, 0, 43, false }, /* 3: 400 9.5 */
296 { 77, 0x9A, 0, 128, false }, /* 4: 600 0 */
297 { 77, 0x9A, 0, 85, false }, /* 5: 600 3.5 */
298 { 77, 0x9A, 0, 64, false }, /* 6: 600 6 */
299 { 102, 0x9A, 0, 128, false }, /* 7: 800 0 */
300 { 102, 0x9A, 0, 85, false }, /* 8: 800 3.5 */
96fb9f9b
VK		 301 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
302};
303
78ab0bae
VS		 304static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
305 u32 level, enum port port, int type);
f8896f5d 306
a1e6ad66
ID		 307static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
308 struct intel_digital_port **dig_port,
309 enum port *port)
fc914639 310{
0bdee30e 311 struct drm_encoder *encoder = &intel_encoder->base;
fc914639 312
8cd21b7f
JN		 313 switch (intel_encoder->type) {
314 case INTEL_OUTPUT_DP_MST:
a1e6ad66
ID		 315 *dig_port = enc_to_mst(encoder)->primary;
316 *port = (*dig_port)->port;
8cd21b7f 317 break;
183aec16
CW		 318 default:
319 WARN(1, "Invalid DDI encoder type %d\n", intel_encoder->type);
320 /* fallthrough and treat as unknown */
cca0502b 321 case INTEL_OUTPUT_DP:
8cd21b7f
JN		 322 case INTEL_OUTPUT_EDP:
323 case INTEL_OUTPUT_HDMI:
324 case INTEL_OUTPUT_UNKNOWN:
a1e6ad66
ID		 325 *dig_port = enc_to_dig_port(encoder);
326 *port = (*dig_port)->port;
8cd21b7f
JN		 327 break;
328 case INTEL_OUTPUT_ANALOG:
a1e6ad66
ID		 329 *dig_port = NULL;
330 *port = PORT_E;
8cd21b7f 331 break;
fc914639
PZ		 332 }
333}
334
a1e6ad66
ID		 335enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
336{
337 struct intel_digital_port *dig_port;
338 enum port port;
339
340 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
341
342 return port;
343}
344
acee2998 345static const struct ddi_buf_trans *
78ab0bae 346skl_get_buf_trans_dp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 347{
78ab0bae 348 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 349 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_dp);
acee2998 350 return skl_y_ddi_translations_dp;
78ab0bae 351 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
f8896f5d 352 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_dp);
acee2998 353 return skl_u_ddi_translations_dp;
f8896f5d 354 } else {
f8896f5d 355 *n_entries = ARRAY_SIZE(skl_ddi_translations_dp);
acee2998 356 return skl_ddi_translations_dp;
f8896f5d 357 }
f8896f5d
DW		 358}
359
acee2998 360static const struct ddi_buf_trans *
78ab0bae 361skl_get_buf_trans_edp(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 362{
06411f08 363 if (dev_priv->vbt.edp.low_vswing) {
78ab0bae 364 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 365 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_edp);
acee2998 366 return skl_y_ddi_translations_edp;
78ab0bae 367 } else if (IS_SKL_ULT(dev_priv) || IS_KBL_ULT(dev_priv)) {
f8896f5d 368 *n_entries = ARRAY_SIZE(skl_u_ddi_translations_edp);
acee2998 369 return skl_u_ddi_translations_edp;
f8896f5d 370 } else {
f8896f5d 371 *n_entries = ARRAY_SIZE(skl_ddi_translations_edp);
acee2998 372 return skl_ddi_translations_edp;
f8896f5d
DW		 373 }
374 }
cd1101cb 375
78ab0bae 376 return skl_get_buf_trans_dp(dev_priv, n_entries);
f8896f5d
DW		 377}
378
379static const struct ddi_buf_trans *
78ab0bae 380skl_get_buf_trans_hdmi(struct drm_i915_private *dev_priv, int *n_entries)
f8896f5d 381{
78ab0bae 382 if (IS_SKL_ULX(dev_priv) || IS_KBL_ULX(dev_priv)) {
5f8b2531 383 *n_entries = ARRAY_SIZE(skl_y_ddi_translations_hdmi);
acee2998 384 return skl_y_ddi_translations_hdmi;
f8896f5d 385 } else {
f8896f5d 386 *n_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
acee2998 387 return skl_ddi_translations_hdmi;
f8896f5d 388 }
f8896f5d
DW		 389}
390
e58623cb
AR		 391/*
392 * Starting with Haswell, DDI port buffers must be programmed with correct
393 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 394 * but the HDMI/DVI fields are shared among those. So we program the DDI
395 * in either FDI or DP modes only, as HDMI connections will work with both
396 * of those
397 */
6a7e4f99 398void intel_prepare_ddi_buffer(struct intel_encoder *encoder)
45244b87 399{
6a7e4f99 400 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
75067dde 401 u32 iboost_bit = 0;
7ff44670 402 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
7ad14a29 403 size;
6a7e4f99
VS		 404 int hdmi_level;
405 enum port port;
10122051
JN		 406 const struct ddi_buf_trans *ddi_translations_fdi;
407 const struct ddi_buf_trans *ddi_translations_dp;
408 const struct ddi_buf_trans *ddi_translations_edp;
409 const struct ddi_buf_trans *ddi_translations_hdmi;
410 const struct ddi_buf_trans *ddi_translations;
e58623cb 411
6a7e4f99
VS		 412 port = intel_ddi_get_encoder_port(encoder);
413 hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
414
78ab0bae 415 if (IS_BROXTON(dev_priv)) {
6a7e4f99 416 if (encoder->type != INTEL_OUTPUT_HDMI)
96fb9f9b
VK		 417 return;
418
419 /* Vswing programming for HDMI */
78ab0bae 420 bxt_ddi_vswing_sequence(dev_priv, hdmi_level, port,
96fb9f9b
VK		 421 INTEL_OUTPUT_HDMI);
422 return;
6a7e4f99
VS		 423 }
424
425 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c30400fc 426 ddi_translations_fdi = NULL;
f8896f5d 427 ddi_translations_dp =
78ab0bae 428 skl_get_buf_trans_dp(dev_priv, &n_dp_entries);
f8896f5d 429 ddi_translations_edp =
78ab0bae 430 skl_get_buf_trans_edp(dev_priv, &n_edp_entries);
f8896f5d 431 ddi_translations_hdmi =
78ab0bae 432 skl_get_buf_trans_hdmi(dev_priv, &n_hdmi_entries);
f8896f5d 433 hdmi_default_entry = 8;
75067dde
AK		 434 /* If we're boosting the current, set bit 31 of trans1 */
435 if (dev_priv->vbt.ddi_port_info[port].hdmi_boost_level ||
436 dev_priv->vbt.ddi_port_info[port].dp_boost_level)
437 iboost_bit = 1<<31;
10afa0b6 438
ceccad59
VS		 439 if (WARN_ON(encoder->type == INTEL_OUTPUT_EDP &&
440 port != PORT_A && port != PORT_E &&
441 n_edp_entries > 9))
10afa0b6 442 n_edp_entries = 9;
78ab0bae 443 } else if (IS_BROADWELL(dev_priv)) {
e58623cb
AR		 444 ddi_translations_fdi = bdw_ddi_translations_fdi;
445 ddi_translations_dp = bdw_ddi_translations_dp;
00983519
MK		 446
447 if (dev_priv->vbt.edp.low_vswing) {
448 ddi_translations_edp = bdw_ddi_translations_edp;
449 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
450 } else {
451 ddi_translations_edp = bdw_ddi_translations_dp;
452 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
453 }
454
a26aa8ba 455 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
00983519 456
7ad14a29 457 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 458 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 459 hdmi_default_entry = 7;
78ab0bae 460 } else if (IS_HASWELL(dev_priv)) {
e58623cb
AR		 461 ddi_translations_fdi = hsw_ddi_translations_fdi;
462 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 463 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 464 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
7ad14a29 465 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
10122051 466 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
7ff44670 467 hdmi_default_entry = 6;
e58623cb
AR		 468 } else {
469 WARN(1, "ddi translation table missing\n");
300644c7 470 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 471 ddi_translations_fdi = bdw_ddi_translations_fdi;
472 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 473 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 474 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
475 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 476 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 477 hdmi_default_entry = 7;
e58623cb
AR		 478 }
479
6a7e4f99
VS		 480 switch (encoder->type) {
481 case INTEL_OUTPUT_EDP:
300644c7 482 ddi_translations = ddi_translations_edp;
7ad14a29 483 size = n_edp_entries;
300644c7 484 break;
cca0502b 485 case INTEL_OUTPUT_DP:
6a7e4f99 486 case INTEL_OUTPUT_HDMI:
300644c7 487 ddi_translations = ddi_translations_dp;
7ad14a29 488 size = n_dp_entries;
300644c7 489 break;
6a7e4f99
VS		 490 case INTEL_OUTPUT_ANALOG:
491 ddi_translations = ddi_translations_fdi;
7ad14a29 492 size = n_dp_entries;
300644c7
PZ		 493 break;
494 default:
495 BUG();
496 }
45244b87 497
9712e688
VS		 498 for (i = 0; i < size; i++) {
499 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
500 ddi_translations[i].trans1 | iboost_bit);
501 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
502 ddi_translations[i].trans2);
45244b87 503 }
ce4dd49e 504
6a7e4f99 505 if (encoder->type != INTEL_OUTPUT_HDMI)
ce3b7e9b
DL		 506 return;
507
ce4dd49e
DL		 508 /* Choose a good default if VBT is badly populated */
509 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
510 hdmi_level >= n_hdmi_entries)
7ff44670 511 hdmi_level = hdmi_default_entry;
ce4dd49e 512
6acab15a 513 /* Entry 9 is for HDMI: */
9712e688
VS		 514 I915_WRITE(DDI_BUF_TRANS_LO(port, i),
515 ddi_translations_hdmi[hdmi_level].trans1 | iboost_bit);
516 I915_WRITE(DDI_BUF_TRANS_HI(port, i),
517 ddi_translations_hdmi[hdmi_level].trans2);
45244b87
ED		 518}
519
248138b5
PZ		 520static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
521 enum port port)
522{
f0f59a00 523 i915_reg_t reg = DDI_BUF_CTL(port);
248138b5
PZ		 524 int i;
525
3449ca85 526 for (i = 0; i < 16; i++) {
248138b5
PZ		 527 udelay(1);
528 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
529 return;
530 }
531 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
532}
c82e4d26
ED		 533
534/* Starting with Haswell, different DDI ports can work in FDI mode for
535 * connection to the PCH-located connectors. For this, it is necessary to train
536 * both the DDI port and PCH receiver for the desired DDI buffer settings.
537 *
538 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
539 * please note that when FDI mode is active on DDI E, it shares 2 lines with
540 * DDI A (which is used for eDP)
541 */
542
543void hsw_fdi_link_train(struct drm_crtc *crtc)
544{
545 struct drm_device *dev = crtc->dev;
fac5e23e 546 struct drm_i915_private *dev_priv = to_i915(dev);
c82e4d26 547 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6a7e4f99 548 struct intel_encoder *encoder;
04945641 549 u32 temp, i, rx_ctl_val;
c82e4d26 550
6a7e4f99
VS		 551 for_each_encoder_on_crtc(dev, crtc, encoder) {
552 WARN_ON(encoder->type != INTEL_OUTPUT_ANALOG);
553 intel_prepare_ddi_buffer(encoder);
554 }
555
04945641
PZ		 556 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
557 * mode set "sequence for CRT port" document:
558 * - TP1 to TP2 time with the default value
559 * - FDI delay to 90h
8693a824
DL		 560 *
561 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641 562 */
eede3b53 563 I915_WRITE(FDI_RX_MISC(PIPE_A), FDI_RX_PWRDN_LANE1_VAL(2) |
04945641
PZ		 564 FDI_RX_PWRDN_LANE0_VAL(2) |
565 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
566
567 /* Enable the PCH Receiver FDI PLL */
3e68320e 568 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 569 FDI_RX_PLL_ENABLE |
6e3c9717 570 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
eede3b53
VS		 571 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
572 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 573 udelay(220);
574
575 /* Switch from Rawclk to PCDclk */
576 rx_ctl_val |= FDI_PCDCLK;
eede3b53 577 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
04945641
PZ		 578
579 /* Configure Port Clock Select */
6e3c9717
ACO		 580 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
581 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 582
583 /* Start the training iterating through available voltages and emphasis,
584 * testing each value twice. */
10122051 585 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 586 /* Configure DP_TP_CTL with auto-training */
587 I915_WRITE(DP_TP_CTL(PORT_E),
588 DP_TP_CTL_FDI_AUTOTRAIN |
589 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
590 DP_TP_CTL_LINK_TRAIN_PAT1 |
591 DP_TP_CTL_ENABLE);
592
876a8cdf
DL		 593 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
594 * DDI E does not support port reversal, the functionality is
595 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
596 * port reversal bit */
c82e4d26 597 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 598 DDI_BUF_CTL_ENABLE |
6e3c9717 599 ((intel_crtc->config->fdi_lanes - 1) << 1) |
c5fe6a06 600 DDI_BUF_TRANS_SELECT(i / 2));
04945641 601 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 602
603 udelay(600);
604
04945641 605 /* Program PCH FDI Receiver TU */
eede3b53 606 I915_WRITE(FDI_RX_TUSIZE1(PIPE_A), TU_SIZE(64));
04945641
PZ		 607
608 /* Enable PCH FDI Receiver with auto-training */
609 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
eede3b53
VS		 610 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
611 POSTING_READ(FDI_RX_CTL(PIPE_A));
04945641
PZ		 612
613 /* Wait for FDI receiver lane calibration */
614 udelay(30);
615
616 /* Unset FDI_RX_MISC pwrdn lanes */
eede3b53 617 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641 618 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
eede3b53
VS		 619 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
620 POSTING_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 621
622 /* Wait for FDI auto training time */
623 udelay(5);
c82e4d26
ED		 624
625 temp = I915_READ(DP_TP_STATUS(PORT_E));
626 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 627 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
a308ccb3
VS		 628 break;
629 }
c82e4d26 630
a308ccb3
VS		 631 /*
632 * Leave things enabled even if we failed to train FDI.
633 * Results in less fireworks from the state checker.
634 */
635 if (i == ARRAY_SIZE(hsw_ddi_translations_fdi) * 2 - 1) {
636 DRM_ERROR("FDI link training failed!\n");
637 break;
c82e4d26 638 }
04945641 639
5b421c57
VS		 640 rx_ctl_val &= ~FDI_RX_ENABLE;
641 I915_WRITE(FDI_RX_CTL(PIPE_A), rx_ctl_val);
642 POSTING_READ(FDI_RX_CTL(PIPE_A));
643
248138b5
PZ		 644 temp = I915_READ(DDI_BUF_CTL(PORT_E));
645 temp &= ~DDI_BUF_CTL_ENABLE;
646 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
647 POSTING_READ(DDI_BUF_CTL(PORT_E));
648
04945641 649 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 650 temp = I915_READ(DP_TP_CTL(PORT_E));
651 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
652 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
653 I915_WRITE(DP_TP_CTL(PORT_E), temp);
654 POSTING_READ(DP_TP_CTL(PORT_E));
655
656 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641 657
04945641 658 /* Reset FDI_RX_MISC pwrdn lanes */
eede3b53 659 temp = I915_READ(FDI_RX_MISC(PIPE_A));
04945641
PZ		 660 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
661 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53
VS		 662 I915_WRITE(FDI_RX_MISC(PIPE_A), temp);
663 POSTING_READ(FDI_RX_MISC(PIPE_A));
c82e4d26
ED		 664 }
665
a308ccb3
VS		 666 /* Enable normal pixel sending for FDI */
667 I915_WRITE(DP_TP_CTL(PORT_E),
668 DP_TP_CTL_FDI_AUTOTRAIN |
669 DP_TP_CTL_LINK_TRAIN_NORMAL |
670 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
671 DP_TP_CTL_ENABLE);
c82e4d26 672}
0e72a5b5 673
44905a27
DA		 674void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
675{
676 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
677 struct intel_digital_port *intel_dig_port =
678 enc_to_dig_port(&encoder->base);
679
680 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 681 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
901c2daf 682 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
44905a27
DA		 683}
684
8d9ddbcb
PZ		 685static struct intel_encoder *
686intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
687{
688 struct drm_device *dev = crtc->dev;
689 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
690 struct intel_encoder *intel_encoder, *ret = NULL;
691 int num_encoders = 0;
692
693 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
694 ret = intel_encoder;
695 num_encoders++;
696 }
697
698 if (num_encoders != 1)
84f44ce7
VS		 699 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
700 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 701
702 BUG_ON(ret == NULL);
703 return ret;
704}
705
bcddf610 706struct intel_encoder *
3165c074 707intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 708{
3165c074
ACO		 709 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
710 struct intel_encoder *ret = NULL;
711 struct drm_atomic_state *state;
da3ced29
ACO		 712 struct drm_connector *connector;
713 struct drm_connector_state *connector_state;
d0737e1d 714 int num_encoders = 0;
3165c074 715 int i;
d0737e1d 716
3165c074
ACO		 717 state = crtc_state->base.state;
718
da3ced29
ACO		 719 for_each_connector_in_state(state, connector, connector_state, i) {
720 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 721 continue;
722
da3ced29 723 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 724 num_encoders++;
d0737e1d
ACO		 725 }
726
727 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
728 pipe_name(crtc->pipe));
729
730 BUG_ON(ret == NULL);
731 return ret;
732}
733
1c0b85c5 734#define LC_FREQ 2700
1c0b85c5 735
f0f59a00
VS		 736static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
737 i915_reg_t reg)
11578553
JB		 738{
739 int refclk = LC_FREQ;
740 int n, p, r;
741 u32 wrpll;
742
743 wrpll = I915_READ(reg);
114fe488
DV		 744 switch (wrpll & WRPLL_PLL_REF_MASK) {
745 case WRPLL_PLL_SSC:
746 case WRPLL_PLL_NON_SSC:
11578553
JB		 747 /*
748 * We could calculate spread here, but our checking
749 * code only cares about 5% accuracy, and spread is a max of
750 * 0.5% downspread.
751 */
752 refclk = 135;
753 break;
114fe488 754 case WRPLL_PLL_LCPLL:
11578553
JB		 755 refclk = LC_FREQ;
756 break;
757 default:
758 WARN(1, "bad wrpll refclk\n");
759 return 0;
760 }
761
762 r = wrpll & WRPLL_DIVIDER_REF_MASK;
763 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
764 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
765
20f0ec16
JB		 766 /* Convert to KHz, p & r have a fixed point portion */
767 return (refclk * n * 100) / (p * r);
11578553
JB		 768}
769
540e732c
S		 770static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
771 uint32_t dpll)
772{
f0f59a00 773 i915_reg_t cfgcr1_reg, cfgcr2_reg;
540e732c
S		 774 uint32_t cfgcr1_val, cfgcr2_val;
775 uint32_t p0, p1, p2, dco_freq;
776
923c1241
VS		 777 cfgcr1_reg = DPLL_CFGCR1(dpll);
778 cfgcr2_reg = DPLL_CFGCR2(dpll);
540e732c
S		 779
780 cfgcr1_val = I915_READ(cfgcr1_reg);
781 cfgcr2_val = I915_READ(cfgcr2_reg);
782
783 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
784 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
785
786 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
787 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
788 else
789 p1 = 1;
790
791
792 switch (p0) {
793 case DPLL_CFGCR2_PDIV_1:
794 p0 = 1;
795 break;
796 case DPLL_CFGCR2_PDIV_2:
797 p0 = 2;
798 break;
799 case DPLL_CFGCR2_PDIV_3:
800 p0 = 3;
801 break;
802 case DPLL_CFGCR2_PDIV_7:
803 p0 = 7;
804 break;
805 }
806
807 switch (p2) {
808 case DPLL_CFGCR2_KDIV_5:
809 p2 = 5;
810 break;
811 case DPLL_CFGCR2_KDIV_2:
812 p2 = 2;
813 break;
814 case DPLL_CFGCR2_KDIV_3:
815 p2 = 3;
816 break;
817 case DPLL_CFGCR2_KDIV_1:
818 p2 = 1;
819 break;
820 }
821
822 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
823
824 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
825 1000) / 0x8000;
826
827 return dco_freq / (p0 * p1 * p2 * 5);
828}
829
398a017e
VS		 830static void ddi_dotclock_get(struct intel_crtc_state *pipe_config)
831{
832 int dotclock;
833
834 if (pipe_config->has_pch_encoder)
835 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
836 &pipe_config->fdi_m_n);
37a5650b 837 else if (intel_crtc_has_dp_encoder(pipe_config))
398a017e
VS		 838 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
839 &pipe_config->dp_m_n);
840 else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp == 36)
841 dotclock = pipe_config->port_clock * 2 / 3;
842 else
843 dotclock = pipe_config->port_clock;
844
845 if (pipe_config->pixel_multiplier)
846 dotclock /= pipe_config->pixel_multiplier;
847
848 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
849}
540e732c
S		 850
851static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 852 struct intel_crtc_state *pipe_config)
540e732c 853{
fac5e23e 854 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
540e732c
S		 855 int link_clock = 0;
856 uint32_t dpll_ctl1, dpll;
857
134ffa44 858 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 859
860 dpll_ctl1 = I915_READ(DPLL_CTRL1);
861
862 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
863 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
864 } else {
71cd8423
DL		 865 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
866 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 867
868 switch (link_clock) {
71cd8423 869 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 870 link_clock = 81000;
871 break;
71cd8423 872 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 873 link_clock = 108000;
874 break;
71cd8423 875 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 876 link_clock = 135000;
877 break;
71cd8423 878 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 879 link_clock = 162000;
880 break;
71cd8423 881 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 882 link_clock = 216000;
883 break;
71cd8423 884 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 885 link_clock = 270000;
886 break;
887 default:
888 WARN(1, "Unsupported link rate\n");
889 break;
890 }
891 link_clock *= 2;
892 }
893
894 pipe_config->port_clock = link_clock;
895
398a017e 896 ddi_dotclock_get(pipe_config);
540e732c
S		 897}
898
3d51278a 899static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 900 struct intel_crtc_state *pipe_config)
11578553 901{
fac5e23e 902 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
11578553
JB		 903 int link_clock = 0;
904 u32 val, pll;
905
26804afd 906 val = pipe_config->ddi_pll_sel;
11578553
JB		 907 switch (val & PORT_CLK_SEL_MASK) {
908 case PORT_CLK_SEL_LCPLL_810:
909 link_clock = 81000;
910 break;
911 case PORT_CLK_SEL_LCPLL_1350:
912 link_clock = 135000;
913 break;
914 case PORT_CLK_SEL_LCPLL_2700:
915 link_clock = 270000;
916 break;
917 case PORT_CLK_SEL_WRPLL1:
01403de3 918 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(0));
11578553
JB		 919 break;
920 case PORT_CLK_SEL_WRPLL2:
01403de3 921 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL(1));
11578553
JB		 922 break;
923 case PORT_CLK_SEL_SPLL:
924 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
925 if (pll == SPLL_PLL_FREQ_810MHz)
926 link_clock = 81000;
927 else if (pll == SPLL_PLL_FREQ_1350MHz)
928 link_clock = 135000;
929 else if (pll == SPLL_PLL_FREQ_2700MHz)
930 link_clock = 270000;
931 else {
932 WARN(1, "bad spll freq\n");
933 return;
934 }
935 break;
936 default:
937 WARN(1, "bad port clock sel\n");
938 return;
939 }
940
941 pipe_config->port_clock = link_clock * 2;
942
398a017e 943 ddi_dotclock_get(pipe_config);
11578553
JB		 944}
945
977bb38d
S		 946static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
947 enum intel_dpll_id dpll)
948{
aa610dcb
ID		 949 struct intel_shared_dpll *pll;
950 struct intel_dpll_hw_state *state;
9e2c8475 951 struct dpll clock;
aa610dcb
ID		 952
953 /* For DDI ports we always use a shared PLL. */
954 if (WARN_ON(dpll == DPLL_ID_PRIVATE))
955 return 0;
956
957 pll = &dev_priv->shared_dplls[dpll];
958 state = &pll->config.hw_state;
959
960 clock.m1 = 2;
961 clock.m2 = (state->pll0 & PORT_PLL_M2_MASK) << 22;
962 if (state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
963 clock.m2 |= state->pll2 & PORT_PLL_M2_FRAC_MASK;
964 clock.n = (state->pll1 & PORT_PLL_N_MASK) >> PORT_PLL_N_SHIFT;
965 clock.p1 = (state->ebb0 & PORT_PLL_P1_MASK) >> PORT_PLL_P1_SHIFT;
966 clock.p2 = (state->ebb0 & PORT_PLL_P2_MASK) >> PORT_PLL_P2_SHIFT;
967
968 return chv_calc_dpll_params(100000, &clock);
977bb38d
S		 969}
970
971static void bxt_ddi_clock_get(struct intel_encoder *encoder,
972 struct intel_crtc_state *pipe_config)
973{
fac5e23e 974 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
977bb38d
S		 975 enum port port = intel_ddi_get_encoder_port(encoder);
976 uint32_t dpll = port;
977
398a017e 978 pipe_config->port_clock = bxt_calc_pll_link(dev_priv, dpll);
977bb38d 979
398a017e 980 ddi_dotclock_get(pipe_config);
977bb38d
S		 981}
982
3d51278a 983void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 984 struct intel_crtc_state *pipe_config)
3d51278a 985{
22606a18
DL		 986 struct drm_device *dev = encoder->base.dev;
987
988 if (INTEL_INFO(dev)->gen <= 8)
989 hsw_ddi_clock_get(encoder, pipe_config);
ef11bdb3 990 else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
22606a18 991 skl_ddi_clock_get(encoder, pipe_config);
977bb38d
S		 992 else if (IS_BROXTON(dev))
993 bxt_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 994}
995
0220ab6e 996static bool
d664c0ce 997hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 998 struct intel_crtc_state *crtc_state,
96f3f1f9 999 struct intel_encoder *intel_encoder)
6441ab5f 1000{
daedf20a 1001 struct intel_shared_dpll *pll;
6441ab5f 1002
9d16da65
ACO		 1003 pll = intel_get_shared_dpll(intel_crtc, crtc_state,
1004 intel_encoder);
1005 if (!pll)
1006 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1007 pipe_name(intel_crtc->pipe));
1008
1009 return pll;
6441ab5f
PZ		 1010}
1011
82d35437
S		 1012static bool
1013skl_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1014 struct intel_crtc_state *crtc_state,
96f3f1f9 1015 struct intel_encoder *intel_encoder)
82d35437
S		 1016{
1017 struct intel_shared_dpll *pll;
82d35437 1018
daedf20a 1019 pll = intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
82d35437
S		 1020 if (pll == NULL) {
1021 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1022 pipe_name(intel_crtc->pipe));
1023 return false;
1024 }
1025
82d35437
S		 1026 return true;
1027}
0220ab6e 1028
d683f3bc
S		 1029static bool
1030bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1031 struct intel_crtc_state *crtc_state,
96f3f1f9 1032 struct intel_encoder *intel_encoder)
d683f3bc 1033{
34177c24 1034 return !!intel_get_shared_dpll(intel_crtc, crtc_state, intel_encoder);
d683f3bc
S		 1035}
1036
0220ab6e
DL		 1037/*
1038 * Tries to find a *shared* PLL for the CRTC and store it in
1039 * intel_crtc->ddi_pll_sel.
1040 *
1041 * For private DPLLs, compute_config() should do the selection for us. This
1042 * function should be folded into compute_config() eventually.
1043 */
190f68c5
ACO		 1044bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1045 struct intel_crtc_state *crtc_state)
0220ab6e 1046{
82d35437 1047 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d 1048 struct intel_encoder *intel_encoder =
3165c074 1049 intel_ddi_get_crtc_new_encoder(crtc_state);
0220ab6e 1050
ef11bdb3 1051 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
190f68c5 1052 return skl_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1053 intel_encoder);
d683f3bc
S		 1054 else if (IS_BROXTON(dev))
1055 return bxt_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1056 intel_encoder);
82d35437 1057 else
190f68c5 1058 return hsw_ddi_pll_select(intel_crtc, crtc_state,
96f3f1f9 1059 intel_encoder);
0220ab6e
DL		 1060}
1061
dae84799
PZ		 1062void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1063{
fac5e23e 1064 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
dae84799
PZ		 1065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1066 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6e3c9717 1067 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
dae84799
PZ		 1068 int type = intel_encoder->type;
1069 uint32_t temp;
1070
cca0502b 1071 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
4d1de975
JN		 1072 WARN_ON(transcoder_is_dsi(cpu_transcoder));
1073
c9809791 1074 temp = TRANS_MSA_SYNC_CLK;
6e3c9717 1075 switch (intel_crtc->config->pipe_bpp) {
dae84799 1076 case 18:
c9809791 1077 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1078 break;
1079 case 24:
c9809791 1080 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1081 break;
1082 case 30:
c9809791 1083 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1084 break;
1085 case 36:
c9809791 1086 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1087 break;
1088 default:
4e53c2e0 1089 BUG();
dae84799 1090 }
c9809791 1091 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1092 }
1093}
1094
0e32b39c
DA		 1095void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1096{
1097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1098 struct drm_device *dev = crtc->dev;
fac5e23e 1099 struct drm_i915_private *dev_priv = to_i915(dev);
6e3c9717 1100 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
0e32b39c
DA		 1101 uint32_t temp;
1102 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1103 if (state == true)
1104 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1105 else
1106 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1107 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1108}
1109
8228c251 1110void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1111{
1112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1113 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1114 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10 1115 struct drm_device *dev = crtc->dev;
fac5e23e 1116 struct drm_i915_private *dev_priv = to_i915(dev);
8d9ddbcb 1117 enum pipe pipe = intel_crtc->pipe;
6e3c9717 1118 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
174edf1f 1119 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1120 int type = intel_encoder->type;
8d9ddbcb
PZ		 1121 uint32_t temp;
1122
ad80a810
PZ		 1123 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1124 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1125 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1126
6e3c9717 1127 switch (intel_crtc->config->pipe_bpp) {
dfcef252 1128 case 18:
ad80a810 1129 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1130 break;
1131 case 24:
ad80a810 1132 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1133 break;
1134 case 30:
ad80a810 1135 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1136 break;
1137 case 36:
ad80a810 1138 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1139 break;
1140 default:
4e53c2e0 1141 BUG();
dfcef252 1142 }
72662e10 1143
6e3c9717 1144 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1145 temp |= TRANS_DDI_PVSYNC;
6e3c9717 1146 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1147 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1148
e6f0bfc4
PZ		 1149 if (cpu_transcoder == TRANSCODER_EDP) {
1150 switch (pipe) {
1151 case PIPE_A:
c7670b10
PZ		 1152 /* On Haswell, can only use the always-on power well for
1153 * eDP when not using the panel fitter, and when not
1154 * using motion blur mitigation (which we don't
1155 * support). */
fabf6e51 1156 if (IS_HASWELL(dev) &&
6e3c9717
ACO		 1157 (intel_crtc->config->pch_pfit.enabled ||
1158 intel_crtc->config->pch_pfit.force_thru))
d6dd9eb1
DV		 1159 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1160 else
1161 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1162 break;
1163 case PIPE_B:
1164 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1165 break;
1166 case PIPE_C:
1167 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1168 break;
1169 default:
1170 BUG();
1171 break;
1172 }
1173 }
1174
7739c33b 1175 if (type == INTEL_OUTPUT_HDMI) {
6e3c9717 1176 if (intel_crtc->config->has_hdmi_sink)
ad80a810 1177 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1178 else
ad80a810 1179 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1180
7739c33b 1181 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1182 temp |= TRANS_DDI_MODE_SELECT_FDI;
6e3c9717 1183 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
7739c33b 1184
cca0502b 1185 } else if (type == INTEL_OUTPUT_DP ||
7739c33b
PZ		 1186 type == INTEL_OUTPUT_EDP) {
1187 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1188
0e32b39c
DA		 1189 if (intel_dp->is_mst) {
1190 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1191 } else
1192 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1193
90a6b7b0 1194 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
0e32b39c
DA		 1195 } else if (type == INTEL_OUTPUT_DP_MST) {
1196 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1197
1198 if (intel_dp->is_mst) {
1199 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1200 } else
1201 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1202
90a6b7b0 1203 temp |= DDI_PORT_WIDTH(intel_crtc->config->lane_count);
8d9ddbcb 1204 } else {
84f44ce7
VS		 1205 WARN(1, "Invalid encoder type %d for pipe %c\n",
1206 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1207 }
1208
ad80a810 1209 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1210}
72662e10 1211
ad80a810
PZ		 1212void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1213 enum transcoder cpu_transcoder)
8d9ddbcb 1214{
f0f59a00 1215 i915_reg_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1216 uint32_t val = I915_READ(reg);
1217
0e32b39c 1218 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1219 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1220 I915_WRITE(reg, val);
72662e10
ED		 1221}
1222
bcbc889b
PZ		 1223bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1224{
1225 struct drm_device *dev = intel_connector->base.dev;
fac5e23e 1226 struct drm_i915_private *dev_priv = to_i915(dev);
bcbc889b
PZ		 1227 struct intel_encoder *intel_encoder = intel_connector->encoder;
1228 int type = intel_connector->base.connector_type;
1229 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1230 enum pipe pipe = 0;
1231 enum transcoder cpu_transcoder;
882244a3 1232 enum intel_display_power_domain power_domain;
bcbc889b 1233 uint32_t tmp;
e27daab4 1234 bool ret;
bcbc889b 1235
882244a3 1236 power_domain = intel_display_port_power_domain(intel_encoder);
e27daab4 1237 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
882244a3
PZ		 1238 return false;
1239
e27daab4
ID		 1240 if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) {
1241 ret = false;
1242 goto out;
1243 }
bcbc889b
PZ		 1244
1245 if (port == PORT_A)
1246 cpu_transcoder = TRANSCODER_EDP;
1247 else
1a240d4d 1248 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1249
1250 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1251
1252 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1253 case TRANS_DDI_MODE_SELECT_HDMI:
1254 case TRANS_DDI_MODE_SELECT_DVI:
e27daab4
ID		 1255 ret = type == DRM_MODE_CONNECTOR_HDMIA;
1256 break;
bcbc889b
PZ		 1257
1258 case TRANS_DDI_MODE_SELECT_DP_SST:
e27daab4
ID		 1259 ret = type == DRM_MODE_CONNECTOR_eDP ||
1260 type == DRM_MODE_CONNECTOR_DisplayPort;
1261 break;
1262
0e32b39c
DA		 1263 case TRANS_DDI_MODE_SELECT_DP_MST:
1264 /* if the transcoder is in MST state then
1265 * connector isn't connected */
e27daab4
ID		 1266 ret = false;
1267 break;
bcbc889b
PZ		 1268
1269 case TRANS_DDI_MODE_SELECT_FDI:
e27daab4
ID		 1270 ret = type == DRM_MODE_CONNECTOR_VGA;
1271 break;
bcbc889b
PZ		 1272
1273 default:
e27daab4
ID		 1274 ret = false;
1275 break;
bcbc889b 1276 }
e27daab4
ID		 1277
1278out:
1279 intel_display_power_put(dev_priv, power_domain);
1280
1281 return ret;
bcbc889b
PZ		 1282}
1283
85234cdc
DV		 1284bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1285 enum pipe *pipe)
1286{
1287 struct drm_device *dev = encoder->base.dev;
fac5e23e 1288 struct drm_i915_private *dev_priv = to_i915(dev);
fe43d3f5 1289 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 1290 enum intel_display_power_domain power_domain;
85234cdc
DV		 1291 u32 tmp;
1292 int i;
e27daab4 1293 bool ret;
85234cdc 1294
6d129bea 1295 power_domain = intel_display_port_power_domain(encoder);
e27daab4 1296 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
6d129bea
ID		 1297 return false;
1298
e27daab4
ID		 1299 ret = false;
1300
fe43d3f5 1301 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1302
1303 if (!(tmp & DDI_BUF_CTL_ENABLE))
e27daab4 1304 goto out;
85234cdc 1305
ad80a810
PZ		 1306 if (port == PORT_A) {
1307 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1308
ad80a810
PZ		 1309 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1310 case TRANS_DDI_EDP_INPUT_A_ON:
1311 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1312 *pipe = PIPE_A;
1313 break;
1314 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1315 *pipe = PIPE_B;
1316 break;
1317 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1318 *pipe = PIPE_C;
1319 break;
1320 }
1321
e27daab4 1322 ret = true;
ad80a810 1323
e27daab4
ID		 1324 goto out;
1325 }
0e32b39c 1326
e27daab4
ID		 1327 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1328 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1329
1330 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(port)) {
1331 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) ==
1332 TRANS_DDI_MODE_SELECT_DP_MST)
1333 goto out;
1334
1335 *pipe = i;
1336 ret = true;
1337
1338 goto out;
85234cdc
DV		 1339 }
1340 }
1341
84f44ce7 1342 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 1343
e27daab4 1344out:
e93da0a0
ID		 1345 if (ret && IS_BROXTON(dev_priv)) {
1346 tmp = I915_READ(BXT_PHY_CTL(port));
1347 if ((tmp & (BXT_PHY_LANE_POWERDOWN_ACK |
1348 BXT_PHY_LANE_ENABLED)) != BXT_PHY_LANE_ENABLED)
1349 DRM_ERROR("Port %c enabled but PHY powered down? "
1350 "(PHY_CTL %08x)\n", port_name(port), tmp);
1351 }
1352
e27daab4
ID		 1353 intel_display_power_put(dev_priv, power_domain);
1354
1355 return ret;
85234cdc
DV		 1356}
1357
fc914639
PZ		 1358void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1359{
1360 struct drm_crtc *crtc = &intel_crtc->base;
7d4aefd0 1361 struct drm_device *dev = crtc->dev;
fac5e23e 1362 struct drm_i915_private *dev_priv = to_i915(dev);
fc914639
PZ		 1363 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1364 enum port port = intel_ddi_get_encoder_port(intel_encoder);
6e3c9717 1365 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 1366
bb523fc0
PZ		 1367 if (cpu_transcoder != TRANSCODER_EDP)
1368 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1369 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1370}
1371
1372void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1373{
fac5e23e 1374 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
6e3c9717 1375 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 1376
bb523fc0
PZ		 1377 if (cpu_transcoder != TRANSCODER_EDP)
1378 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1379 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1380}
1381
78ab0bae
VS		 1382static void skl_ddi_set_iboost(struct drm_i915_private *dev_priv,
1383 u32 level, enum port port, int type)
f8896f5d 1384{
f8896f5d
DW		 1385 const struct ddi_buf_trans *ddi_translations;
1386 uint8_t iboost;
75067dde 1387 uint8_t dp_iboost, hdmi_iboost;
f8896f5d
DW		 1388 int n_entries;
1389 u32 reg;
1390
75067dde
AK		 1391 /* VBT may override standard boost values */
1392 dp_iboost = dev_priv->vbt.ddi_port_info[port].dp_boost_level;
1393 hdmi_iboost = dev_priv->vbt.ddi_port_info[port].hdmi_boost_level;
1394
cca0502b 1395 if (type == INTEL_OUTPUT_DP) {
75067dde
AK		 1396 if (dp_iboost) {
1397 iboost = dp_iboost;
1398 } else {
78ab0bae 1399 ddi_translations = skl_get_buf_trans_dp(dev_priv, &n_entries);
e4d4c05b 1400 iboost = ddi_translations[level].i_boost;
75067dde 1401 }
f8896f5d 1402 } else if (type == INTEL_OUTPUT_EDP) {
75067dde
AK		 1403 if (dp_iboost) {
1404 iboost = dp_iboost;
1405 } else {
78ab0bae 1406 ddi_translations = skl_get_buf_trans_edp(dev_priv, &n_entries);
10afa0b6
VS		 1407
1408 if (WARN_ON(port != PORT_A &&
1409 port != PORT_E && n_entries > 9))
1410 n_entries = 9;
1411
e4d4c05b 1412 iboost = ddi_translations[level].i_boost;
75067dde 1413 }
f8896f5d 1414 } else if (type == INTEL_OUTPUT_HDMI) {
75067dde
AK		 1415 if (hdmi_iboost) {
1416 iboost = hdmi_iboost;
1417 } else {
78ab0bae 1418 ddi_translations = skl_get_buf_trans_hdmi(dev_priv, &n_entries);
e4d4c05b 1419 iboost = ddi_translations[level].i_boost;
75067dde 1420 }
f8896f5d
DW		 1421 } else {
1422 return;
1423 }
1424
1425 /* Make sure that the requested I_boost is valid */
1426 if (iboost && iboost != 0x1 && iboost != 0x3 && iboost != 0x7) {
1427 DRM_ERROR("Invalid I_boost value %u\n", iboost);
1428 return;
1429 }
1430
1431 reg = I915_READ(DISPIO_CR_TX_BMU_CR0);
1432 reg &= ~BALANCE_LEG_MASK(port);
1433 reg &= ~(1 << (BALANCE_LEG_DISABLE_SHIFT + port));
1434
1435 if (iboost)
1436 reg |= iboost << BALANCE_LEG_SHIFT(port);
1437 else
1438 reg |= 1 << (BALANCE_LEG_DISABLE_SHIFT + port);
1439
1440 I915_WRITE(DISPIO_CR_TX_BMU_CR0, reg);
1441}
1442
78ab0bae
VS		 1443static void bxt_ddi_vswing_sequence(struct drm_i915_private *dev_priv,
1444 u32 level, enum port port, int type)
96fb9f9b 1445{
96fb9f9b
VK		 1446 const struct bxt_ddi_buf_trans *ddi_translations;
1447 u32 n_entries, i;
1448 uint32_t val;
1449
06411f08 1450 if (type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.low_vswing) {
d9d7000d
SJ		 1451 n_entries = ARRAY_SIZE(bxt_ddi_translations_edp);
1452 ddi_translations = bxt_ddi_translations_edp;
cca0502b 1453 } else if (type == INTEL_OUTPUT_DP
d9d7000d 1454 || type == INTEL_OUTPUT_EDP) {
96fb9f9b
VK		 1455 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1456 ddi_translations = bxt_ddi_translations_dp;
1457 } else if (type == INTEL_OUTPUT_HDMI) {
1458 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1459 ddi_translations = bxt_ddi_translations_hdmi;
1460 } else {
1461 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1462 type);
1463 return;
1464 }
1465
1466 /* Check if default value has to be used */
1467 if (level >= n_entries ||
1468 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1469 for (i = 0; i < n_entries; i++) {
1470 if (ddi_translations[i].default_index) {
1471 level = i;
1472 break;
1473 }
1474 }
1475 }
1476
1477 /*
1478 * While we write to the group register to program all lanes at once we
1479 * can read only lane registers and we pick lanes 0/1 for that.
1480 */
1481 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1482 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
1483 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1484
1485 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
1486 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
1487 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
1488 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
1489 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
1490
1491 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
9c58a049 1492 val &= ~SCALE_DCOMP_METHOD;
96fb9f9b 1493 if (ddi_translations[level].enable)
9c58a049
SJ		 1494 val |= SCALE_DCOMP_METHOD;
1495
1496 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
1497 DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
1498
96fb9f9b
VK		 1499 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
1500
1501 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
1502 val &= ~DE_EMPHASIS;
1503 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
1504 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
1505
1506 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1507 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
1508 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1509}
1510
f8896f5d
DW		 1511static uint32_t translate_signal_level(int signal_levels)
1512{
1513 uint32_t level;
1514
1515 switch (signal_levels) {
1516 default:
1517 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level: 0x%x\n",
1518 signal_levels);
1519 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1520 level = 0;
1521 break;
1522 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1523 level = 1;
1524 break;
1525 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1526 level = 2;
1527 break;
1528 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_3:
1529 level = 3;
1530 break;
1531
1532 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1533 level = 4;
1534 break;
1535 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1536 level = 5;
1537 break;
1538 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
1539 level = 6;
1540 break;
1541
1542 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1543 level = 7;
1544 break;
1545 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
1546 level = 8;
1547 break;
1548
1549 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
1550 level = 9;
1551 break;
1552 }
1553
1554 return level;
1555}
1556
1557uint32_t ddi_signal_levels(struct intel_dp *intel_dp)
1558{
1559 struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
78ab0bae 1560 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
f8896f5d
DW		 1561 struct intel_encoder *encoder = &dport->base;
1562 uint8_t train_set = intel_dp->train_set[0];
1563 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1564 DP_TRAIN_PRE_EMPHASIS_MASK);
1565 enum port port = dport->port;
1566 uint32_t level;
1567
1568 level = translate_signal_level(signal_levels);
1569
78ab0bae
VS		 1570 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
1571 skl_ddi_set_iboost(dev_priv, level, port, encoder->type);
1572 else if (IS_BROXTON(dev_priv))
1573 bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
f8896f5d
DW		 1574
1575 return DDI_BUF_TRANS_SELECT(level);
1576}
1577
e404ba8d
VS		 1578void intel_ddi_clk_select(struct intel_encoder *encoder,
1579 const struct intel_crtc_state *pipe_config)
6441ab5f 1580{
e404ba8d
VS		 1581 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1582 enum port port = intel_ddi_get_encoder_port(encoder);
6441ab5f 1583
e404ba8d
VS		 1584 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
1585 uint32_t dpll = pipe_config->ddi_pll_sel;
efa80add
S		 1586 uint32_t val;
1587
5416d871 1588 /* DDI -> PLL mapping */
efa80add
S		 1589 val = I915_READ(DPLL_CTRL2);
1590
1591 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1592 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1593 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1594 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1595
1596 I915_WRITE(DPLL_CTRL2, val);
5416d871 1597
e404ba8d
VS		 1598 } else if (INTEL_INFO(dev_priv)->gen < 9) {
1599 WARN_ON(pipe_config->ddi_pll_sel == PORT_CLK_SEL_NONE);
1600 I915_WRITE(PORT_CLK_SEL(port), pipe_config->ddi_pll_sel);
efa80add 1601 }
e404ba8d
VS		 1602}
1603
1604static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
1605{
1606 struct drm_encoder *encoder = &intel_encoder->base;
6a7e4f99 1607 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
e404ba8d
VS		 1608 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
1609 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1610 int type = intel_encoder->type;
6a7e4f99 1611
b2ccb822
VS		 1612 if (type == INTEL_OUTPUT_HDMI) {
1613 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1614
1615 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
1616 }
1617
6a7e4f99 1618 intel_prepare_ddi_buffer(intel_encoder);
e404ba8d
VS		 1619
1620 if (type == INTEL_OUTPUT_EDP) {
1621 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1622 intel_edp_panel_on(intel_dp);
1623 }
1624
1625 intel_ddi_clk_select(intel_encoder, crtc->config);
c19b0669 1626
cca0502b 1627 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
c19b0669 1628 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 1629
901c2daf
VS		 1630 intel_dp_set_link_params(intel_dp, crtc->config);
1631
44905a27 1632 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 1633
1634 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1635 intel_dp_start_link_train(intel_dp);
6a7e4f99 1636 if (port != PORT_A || INTEL_INFO(dev_priv)->gen >= 9)
3ab9c637 1637 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 1638 } else if (type == INTEL_OUTPUT_HDMI) {
1639 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1640
1641 intel_hdmi->set_infoframes(encoder,
6e3c9717
ACO		 1642 crtc->config->has_hdmi_sink,
1643 &crtc->config->base.adjusted_mode);
c19b0669 1644 }
6441ab5f
PZ		 1645}
1646
00c09d70 1647static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 1648{
1649 struct drm_encoder *encoder = &intel_encoder->base;
efa80add 1650 struct drm_device *dev = encoder->dev;
fac5e23e 1651 struct drm_i915_private *dev_priv = to_i915(dev);
6441ab5f 1652 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1653 int type = intel_encoder->type;
2886e93f 1654 uint32_t val;
a836bdf9 1655 bool wait = false;
2886e93f
PZ		 1656
1657 val = I915_READ(DDI_BUF_CTL(port));
1658 if (val & DDI_BUF_CTL_ENABLE) {
1659 val &= ~DDI_BUF_CTL_ENABLE;
1660 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 1661 wait = true;
2886e93f 1662 }
6441ab5f 1663
a836bdf9
PZ		 1664 val = I915_READ(DP_TP_CTL(port));
1665 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1666 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1667 I915_WRITE(DP_TP_CTL(port), val);
1668
1669 if (wait)
1670 intel_wait_ddi_buf_idle(dev_priv, port);
1671
cca0502b 1672 if (type == INTEL_OUTPUT_DP || type == INTEL_OUTPUT_EDP) {
82a4d9c0 1673 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 1674 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 1675 intel_edp_panel_vdd_on(intel_dp);
4be73780 1676 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 1677 }
1678
ef11bdb3 1679 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
efa80add
S		 1680 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1681 DPLL_CTRL2_DDI_CLK_OFF(port)));
1ab23380 1682 else if (INTEL_INFO(dev)->gen < 9)
efa80add 1683 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
b2ccb822
VS		 1684
1685 if (type == INTEL_OUTPUT_HDMI) {
1686 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1687
1688 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1689 }
6441ab5f
PZ		 1690}
1691
00c09d70 1692static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 1693{
6547fef8 1694 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1695 struct drm_crtc *crtc = encoder->crtc;
1696 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 1697 struct drm_device *dev = encoder->dev;
fac5e23e 1698 struct drm_i915_private *dev_priv = to_i915(dev);
6547fef8
PZ		 1699 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1700 int type = intel_encoder->type;
72662e10 1701
6547fef8 1702 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 1703 struct intel_digital_port *intel_dig_port =
1704 enc_to_dig_port(encoder);
1705
6547fef8
PZ		 1706 /* In HDMI/DVI mode, the port width, and swing/emphasis values
1707 * are ignored so nothing special needs to be done besides
1708 * enabling the port.
1709 */
876a8cdf 1710 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 1711 intel_dig_port->saved_port_bits |
1712 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 1713 } else if (type == INTEL_OUTPUT_EDP) {
1714 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1715
23f08d83 1716 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 1717 intel_dp_stop_link_train(intel_dp);
1718
4be73780 1719 intel_edp_backlight_on(intel_dp);
0bc12bcb 1720 intel_psr_enable(intel_dp);
c395578e 1721 intel_edp_drrs_enable(intel_dp);
6547fef8 1722 }
7b9f35a6 1723
6e3c9717 1724 if (intel_crtc->config->has_audio) {
d45a0bf5 1725 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 1726 intel_audio_codec_enable(intel_encoder);
7b9f35a6 1727 }
5ab432ef
DV		 1728}
1729
00c09d70 1730static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 1731{
d6c50ff8 1732 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1733 struct drm_crtc *crtc = encoder->crtc;
1734 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 1735 int type = intel_encoder->type;
7b9f35a6 1736 struct drm_device *dev = encoder->dev;
fac5e23e 1737 struct drm_i915_private *dev_priv = to_i915(dev);
d6c50ff8 1738
6e3c9717 1739 if (intel_crtc->config->has_audio) {
69bfe1a9 1740 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 1741 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
1742 }
2831d842 1743
d6c50ff8
PZ		 1744 if (type == INTEL_OUTPUT_EDP) {
1745 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1746
c395578e 1747 intel_edp_drrs_disable(intel_dp);
0bc12bcb 1748 intel_psr_disable(intel_dp);
4be73780 1749 intel_edp_backlight_off(intel_dp);
d6c50ff8 1750 }
72662e10 1751}
79f689aa 1752
9c8d0b8e
ID		 1753bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
1754 enum dpio_phy phy)
bd480061 1755{
e93da0a0
ID		 1756 enum port port;
1757
bd480061
ID		 1758 if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & GT_DISPLAY_POWER_ON(phy)))
1759 return false;
1760
1761 if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
1762 (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
1763 DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n",
1764 phy);
1765
1766 return false;
1767 }
1768
1769 if (phy == DPIO_PHY1 &&
1770 !(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE)) {
1771 DRM_DEBUG_DRIVER("DDI PHY 1 powered, but GRC isn't done\n");
1772
1773 return false;
1774 }
1775
1776 if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
1777 DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n",
1778 phy);
1779
1780 return false;
1781 }
1782
e93da0a0
ID		 1783 for_each_port_masked(port,
1784 phy == DPIO_PHY0 ? BIT(PORT_B) | BIT(PORT_C) :
1785 BIT(PORT_A)) {
1786 u32 tmp = I915_READ(BXT_PHY_CTL(port));
1787
1788 if (tmp & BXT_PHY_CMNLANE_POWERDOWN_ACK) {
1789 DRM_DEBUG_DRIVER("DDI PHY %d powered, but common lane "
1790 "for port %c powered down "
1791 "(PHY_CTL %08x)\n",
1792 phy, port_name(port), tmp);
1793
1794 return false;
1795 }
1796 }
1797
bd480061
ID		 1798 return true;
1799}
1800
324513c0 1801static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
adc7f04b
ID		 1802{
1803 u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
1804
1805 return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
1806}
1807
324513c0
ID		 1808static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
1809 enum dpio_phy phy)
01a01ef2 1810{
058fee93
CW		 1811 if (intel_wait_for_register(dev_priv,
1812 BXT_PORT_REF_DW3(phy),
1813 GRC_DONE, GRC_DONE,
1814 10))
01a01ef2
ID		 1815 DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
1816}
1817
9c8d0b8e 1818void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
5c6706e5 1819{
95a7a2ae 1820 u32 val;
5c6706e5 1821
9c8d0b8e 1822 if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
adc7f04b 1823 /* Still read out the GRC value for state verification */
67856d4d 1824 if (phy == DPIO_PHY0)
324513c0 1825 dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
bd480061 1826
9c8d0b8e 1827 if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
47baf2a5
ID		 1828 DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
1829 "won't reprogram it\n", phy);
1830
1831 return;
1832 }
bd480061 1833
47baf2a5
ID		 1834 DRM_DEBUG_DRIVER("DDI PHY %d enabled with invalid state, "
1835 "force reprogramming it\n", phy);
47baf2a5 1836 }
bd480061 1837
5c6706e5
VK		 1838 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
1839 val |= GT_DISPLAY_POWER_ON(phy);
1840 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
1841
b61e7996
VK		 1842 /*
1843 * The PHY registers start out inaccessible and respond to reads with
1844 * all 1s. Eventually they become accessible as they power up, then
1845 * the reserved bit will give the default 0. Poll on the reserved bit
1846 * becoming 0 to find when the PHY is accessible.
1847 * HW team confirmed that the time to reach phypowergood status is
1848 * anywhere between 50 us and 100us.
1849 */
1850 if (wait_for_us(((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
1851 (PHY_RESERVED | PHY_POWER_GOOD)) == PHY_POWER_GOOD), 100)) {
5c6706e5 1852 DRM_ERROR("timeout during PHY%d power on\n", phy);
b61e7996 1853 }
5c6706e5 1854
5c6706e5
VK		 1855 /* Program PLL Rcomp code offset */
1856 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
1857 val &= ~IREF0RC_OFFSET_MASK;
1858 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
1859 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
1860
1861 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
1862 val &= ~IREF1RC_OFFSET_MASK;
1863 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
1864 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
1865
1866 /* Program power gating */
1867 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
1868 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
1869 SUS_CLK_CONFIG;
1870 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
1871
1872 if (phy == DPIO_PHY0) {
1873 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
1874 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
1875 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
1876 }
1877
1878 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
1879 val &= ~OCL2_LDOFUSE_PWR_DIS;
1880 /*
1881 * On PHY1 disable power on the second channel, since no port is
1882 * connected there. On PHY0 both channels have a port, so leave it
1883 * enabled.
1884 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
1885 * power down the second channel on PHY0 as well.
28ca6931
ID		 1886 *
1887 * FIXME: Clarify programming of the following, the register is
1888 * read-only with bit 6 fixed at 0 at least in stepping A.
5c6706e5
VK		 1889 */
1890 if (phy == DPIO_PHY1)
1891 val |= OCL2_LDOFUSE_PWR_DIS;
1892 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
1893
1894 if (phy == DPIO_PHY0) {
1895 uint32_t grc_code;
1896 /*
1897 * PHY0 isn't connected to an RCOMP resistor so copy over
1898 * the corresponding calibrated value from PHY1, and disable
1899 * the automatic calibration on PHY0.
1900 */
324513c0 1901 val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, DPIO_PHY1);
5c6706e5
VK		 1902 grc_code = val << GRC_CODE_FAST_SHIFT |
1903 val << GRC_CODE_SLOW_SHIFT |
1904 val;
1905 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
1906
1907 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
1908 val |= GRC_DIS | GRC_RDY_OVRD;
1909 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
1910 }
1911
1912 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
1913 val |= COMMON_RESET_DIS;
1914 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
e4c49e0f
ID		 1915
1916 if (phy == DPIO_PHY1)
324513c0 1917 bxt_phy_wait_grc_done(dev_priv, DPIO_PHY1);
5c6706e5
VK		 1918}
1919
9c8d0b8e 1920void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
5c6706e5
VK		 1921{
1922 uint32_t val;
1923
1924 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
1925 val &= ~COMMON_RESET_DIS;
1926 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
d7d33fd8
ID		 1927
1928 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
1929 val &= ~GT_DISPLAY_POWER_ON(phy);
1930 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
5c6706e5
VK		 1931}
1932
adc7f04b
ID		 1933static bool __printf(6, 7)
1934__phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1935 i915_reg_t reg, u32 mask, u32 expected,
1936 const char *reg_fmt, ...)
1937{
1938 struct va_format vaf;
1939 va_list args;
1940 u32 val;
1941
1942 val = I915_READ(reg);
1943 if ((val & mask) == expected)
1944 return true;
1945
1946 va_start(args, reg_fmt);
1947 vaf.fmt = reg_fmt;
1948 vaf.va = &args;
1949
1950 DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: "
1951 "current %08x, expected %08x (mask %08x)\n",
1952 phy, &vaf, reg.reg, val, (val & ~mask) | expected,
1953 mask);
1954
1955 va_end(args);
1956
1957 return false;
1958}
1959
9c8d0b8e
ID		 1960bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
1961 enum dpio_phy phy)
adc7f04b 1962{
adc7f04b
ID		 1963 uint32_t mask;
1964 bool ok;
1965
1966#define _CHK(reg, mask, exp, fmt, ...) \
1967 __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \
1968 ## __VA_ARGS__)
1969
9c8d0b8e 1970 if (!bxt_ddi_phy_is_enabled(dev_priv, phy))
adc7f04b
ID		 1971 return false;
1972
1973 ok = true;
1974
adc7f04b
ID		 1975 /* PLL Rcomp code offset */
1976 ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
1977 IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
1978 "BXT_PORT_CL1CM_DW9(%d)", phy);
1979 ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
1980 IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
1981 "BXT_PORT_CL1CM_DW10(%d)", phy);
1982
1983 /* Power gating */
1984 mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
1985 ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
1986 "BXT_PORT_CL1CM_DW28(%d)", phy);
1987
1988 if (phy == DPIO_PHY0)
1989 ok &= _CHK(BXT_PORT_CL2CM_DW6_BC,
1990 DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
1991 "BXT_PORT_CL2CM_DW6_BC");
1992
1993 /*
1994 * TODO: Verify BXT_PORT_CL1CM_DW30 bit OCL2_LDOFUSE_PWR_DIS,
1995 * at least on stepping A this bit is read-only and fixed at 0.
1996 */
1997
1998 if (phy == DPIO_PHY0) {
1999 u32 grc_code = dev_priv->bxt_phy_grc;
2000
2001 grc_code = grc_code << GRC_CODE_FAST_SHIFT |
2002 grc_code << GRC_CODE_SLOW_SHIFT |
2003 grc_code;
2004 mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
2005 GRC_CODE_NOM_MASK;
2006 ok &= _CHK(BXT_PORT_REF_DW6(DPIO_PHY0), mask, grc_code,
2007 "BXT_PORT_REF_DW6(%d)", DPIO_PHY0);
2008
2009 mask = GRC_DIS | GRC_RDY_OVRD;
2010 ok &= _CHK(BXT_PORT_REF_DW8(DPIO_PHY0), mask, mask,
2011 "BXT_PORT_REF_DW8(%d)", DPIO_PHY0);
2012 }
2013
2014 return ok;
2015#undef _CHK
2016}
2017
95a7a2ae
ID		 2018static uint8_t
2019bxt_ddi_phy_calc_lane_lat_optim_mask(struct intel_encoder *encoder,
2020 struct intel_crtc_state *pipe_config)
2021{
2022 switch (pipe_config->lane_count) {
2023 case 1:
2024 return 0;
2025 case 2:
2026 return BIT(2) | BIT(0);
2027 case 4:
2028 return BIT(3) | BIT(2) | BIT(0);
2029 default:
2030 MISSING_CASE(pipe_config->lane_count);
2031
2032 return 0;
2033 }
2034}
2035
2036static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder)
2037{
2038 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2039 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2040 enum port port = dport->port;
2041 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2042 int lane;
2043
2044 for (lane = 0; lane < 4; lane++) {
2045 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2046
2047 /*
2048 * Note that on CHV this flag is called UPAR, but has
2049 * the same function.
2050 */
2051 val &= ~LATENCY_OPTIM;
2052 if (intel_crtc->config->lane_lat_optim_mask & BIT(lane))
2053 val |= LATENCY_OPTIM;
2054
2055 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2056 }
2057}
2058
2059static uint8_t
2060bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
2061{
2062 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2063 struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
2064 enum port port = dport->port;
2065 int lane;
2066 uint8_t mask;
2067
2068 mask = 0;
2069 for (lane = 0; lane < 4; lane++) {
2070 u32 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2071
2072 if (val & LATENCY_OPTIM)
2073 mask |= BIT(lane);
2074 }
2075
2076 return mask;
2077}
2078
ad64217b 2079void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
c19b0669 2080{
ad64217b
ACO		 2081 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2082 struct drm_i915_private *dev_priv =
2083 to_i915(intel_dig_port->base.base.dev);
174edf1f 2084 enum port port = intel_dig_port->port;
c19b0669 2085 uint32_t val;
f3e227df 2086 bool wait = false;
c19b0669
PZ		 2087
2088 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2089 val = I915_READ(DDI_BUF_CTL(port));
2090 if (val & DDI_BUF_CTL_ENABLE) {
2091 val &= ~DDI_BUF_CTL_ENABLE;
2092 I915_WRITE(DDI_BUF_CTL(port), val);
2093 wait = true;
2094 }
2095
2096 val = I915_READ(DP_TP_CTL(port));
2097 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2098 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2099 I915_WRITE(DP_TP_CTL(port), val);
2100 POSTING_READ(DP_TP_CTL(port));
2101
2102 if (wait)
2103 intel_wait_ddi_buf_idle(dev_priv, port);
2104 }
2105
0e32b39c 2106 val = DP_TP_CTL_ENABLE |
c19b0669 2107 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 2108 if (intel_dp->is_mst)
2109 val |= DP_TP_CTL_MODE_MST;
2110 else {
2111 val |= DP_TP_CTL_MODE_SST;
2112 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2113 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2114 }
c19b0669
PZ		 2115 I915_WRITE(DP_TP_CTL(port), val);
2116 POSTING_READ(DP_TP_CTL(port));
2117
2118 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2119 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2120 POSTING_READ(DDI_BUF_CTL(port));
2121
2122 udelay(600);
2123}
00c09d70 2124
1ad960f2
PZ		 2125void intel_ddi_fdi_disable(struct drm_crtc *crtc)
2126{
fac5e23e 2127 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
1ad960f2
PZ		 2128 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2129 uint32_t val;
2130
5b421c57
VS		 2131 /*
2132 * Bspec lists this as both step 13 (before DDI_BUF_CTL disable)
2133 * and step 18 (after clearing PORT_CLK_SEL). Based on a BUN,
2134 * step 13 is the correct place for it. Step 18 is where it was
2135 * originally before the BUN.
2136 */
eede3b53 2137 val = I915_READ(FDI_RX_CTL(PIPE_A));
1ad960f2 2138 val &= ~FDI_RX_ENABLE;
eede3b53 2139 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1ad960f2 2140
5b421c57
VS		 2141 intel_ddi_post_disable(intel_encoder);
2142
eede3b53 2143 val = I915_READ(FDI_RX_MISC(PIPE_A));
1ad960f2
PZ		 2144 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2145 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
eede3b53 2146 I915_WRITE(FDI_RX_MISC(PIPE_A), val);
1ad960f2 2147
eede3b53 2148 val = I915_READ(FDI_RX_CTL(PIPE_A));
1ad960f2 2149 val &= ~FDI_PCDCLK;
eede3b53 2150 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1ad960f2 2151
eede3b53 2152 val = I915_READ(FDI_RX_CTL(PIPE_A));
1ad960f2 2153 val &= ~FDI_RX_PLL_ENABLE;
eede3b53 2154 I915_WRITE(FDI_RX_CTL(PIPE_A), val);
1ad960f2
PZ		 2155}
2156
6801c18c 2157void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 2158 struct intel_crtc_state *pipe_config)
045ac3b5 2159{
fac5e23e 2160 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
045ac3b5 2161 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 2162 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 2163 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 2164 u32 temp, flags = 0;
2165
4d1de975
JN		 2166 /* XXX: DSI transcoder paranoia */
2167 if (WARN_ON(transcoder_is_dsi(cpu_transcoder)))
2168 return;
2169
045ac3b5
JB		 2170 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2171 if (temp & TRANS_DDI_PHSYNC)
2172 flags |= DRM_MODE_FLAG_PHSYNC;
2173 else
2174 flags |= DRM_MODE_FLAG_NHSYNC;
2175 if (temp & TRANS_DDI_PVSYNC)
2176 flags |= DRM_MODE_FLAG_PVSYNC;
2177 else
2178 flags |= DRM_MODE_FLAG_NVSYNC;
2179
2d112de7 2180 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 2181
2182 switch (temp & TRANS_DDI_BPC_MASK) {
2183 case TRANS_DDI_BPC_6:
2184 pipe_config->pipe_bpp = 18;
2185 break;
2186 case TRANS_DDI_BPC_8:
2187 pipe_config->pipe_bpp = 24;
2188 break;
2189 case TRANS_DDI_BPC_10:
2190 pipe_config->pipe_bpp = 30;
2191 break;
2192 case TRANS_DDI_BPC_12:
2193 pipe_config->pipe_bpp = 36;
2194 break;
2195 default:
2196 break;
2197 }
eb14cb74
VS		 2198
2199 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2200 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 2201 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 2202 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2203
cda0aaaf 2204 if (intel_hdmi->infoframe_enabled(&encoder->base, pipe_config))
bbd440fb 2205 pipe_config->has_infoframe = true;
d4d6279a 2206 /* fall through */
eb14cb74 2207 case TRANS_DDI_MODE_SELECT_DVI:
d4d6279a
ACO		 2208 pipe_config->lane_count = 4;
2209 break;
eb14cb74
VS		 2210 case TRANS_DDI_MODE_SELECT_FDI:
2211 break;
2212 case TRANS_DDI_MODE_SELECT_DP_SST:
2213 case TRANS_DDI_MODE_SELECT_DP_MST:
90a6b7b0
VS		 2214 pipe_config->lane_count =
2215 ((temp & DDI_PORT_WIDTH_MASK) >> DDI_PORT_WIDTH_SHIFT) + 1;
eb14cb74
VS		 2216 intel_dp_get_m_n(intel_crtc, pipe_config);
2217 break;
2218 default:
2219 break;
2220 }
10214420 2221
5a8f97ea
L		 2222 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
2223 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
2224 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
2225 pipe_config->has_audio = true;
2226 }
9ed109a7 2227
6aa23e65
JN		 2228 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp.bpp &&
2229 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
10214420
DV		 2230 /*
2231 * This is a big fat ugly hack.
2232 *
2233 * Some machines in UEFI boot mode provide us a VBT that has 18
2234 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2235 * unknown we fail to light up. Yet the same BIOS boots up with
2236 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2237 * max, not what it tells us to use.
2238 *
2239 * Note: This will still be broken if the eDP panel is not lit
2240 * up by the BIOS, and thus we can't get the mode at module
2241 * load.
2242 */
2243 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
6aa23e65
JN		 2244 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2245 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
10214420 2246 }
11578553 2247
22606a18 2248 intel_ddi_clock_get(encoder, pipe_config);
95a7a2ae
ID		 2249
2250 if (IS_BROXTON(dev_priv))
2251 pipe_config->lane_lat_optim_mask =
2252 bxt_ddi_phy_get_lane_lat_optim_mask(encoder);
045ac3b5
JB		 2253}
2254
5bfe2ac0 2255static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 2256 struct intel_crtc_state *pipe_config)
00c09d70 2257{
fac5e23e 2258 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
5bfe2ac0 2259 int type = encoder->type;
eccb140b 2260 int port = intel_ddi_get_encoder_port(encoder);
95a7a2ae 2261 int ret;
00c09d70 2262
5bfe2ac0 2263 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 2264
eccb140b
DV		 2265 if (port == PORT_A)
2266 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2267
00c09d70 2268 if (type == INTEL_OUTPUT_HDMI)
95a7a2ae 2269 ret = intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 2270 else
95a7a2ae
ID		 2271 ret = intel_dp_compute_config(encoder, pipe_config);
2272
2273 if (IS_BROXTON(dev_priv) && ret)
2274 pipe_config->lane_lat_optim_mask =
2275 bxt_ddi_phy_calc_lane_lat_optim_mask(encoder,
2276 pipe_config);
2277
2278 return ret;
2279
00c09d70
PZ		 2280}
2281
2282static const struct drm_encoder_funcs intel_ddi_funcs = {
bf93ba67
ID		 2283 .reset = intel_dp_encoder_reset,
2284 .destroy = intel_dp_encoder_destroy,
00c09d70
PZ		 2285};
2286
4a28ae58
PZ		 2287static struct intel_connector *
2288intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2289{
2290 struct intel_connector *connector;
2291 enum port port = intel_dig_port->port;
2292
9bdbd0b9 2293 connector = intel_connector_alloc();
4a28ae58
PZ		 2294 if (!connector)
2295 return NULL;
2296
2297 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2298 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2299 kfree(connector);
2300 return NULL;
2301 }
2302
2303 return connector;
2304}
2305
2306static struct intel_connector *
2307intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2308{
2309 struct intel_connector *connector;
2310 enum port port = intel_dig_port->port;
2311
9bdbd0b9 2312 connector = intel_connector_alloc();
4a28ae58
PZ		 2313 if (!connector)
2314 return NULL;
2315
2316 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2317 intel_hdmi_init_connector(intel_dig_port, connector);
2318
2319 return connector;
2320}
2321
00c09d70
PZ		 2322void intel_ddi_init(struct drm_device *dev, enum port port)
2323{
fac5e23e 2324 struct drm_i915_private *dev_priv = to_i915(dev);
00c09d70
PZ		 2325 struct intel_digital_port *intel_dig_port;
2326 struct intel_encoder *intel_encoder;
2327 struct drm_encoder *encoder;
311a2094 2328 bool init_hdmi, init_dp;
10e7bec3
VS		 2329 int max_lanes;
2330
2331 if (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES) {
2332 switch (port) {
2333 case PORT_A:
2334 max_lanes = 4;
2335 break;
2336 case PORT_E:
2337 max_lanes = 0;
2338 break;
2339 default:
2340 max_lanes = 4;
2341 break;
2342 }
2343 } else {
2344 switch (port) {
2345 case PORT_A:
2346 max_lanes = 2;
2347 break;
2348 case PORT_E:
2349 max_lanes = 2;
2350 break;
2351 default:
2352 max_lanes = 4;
2353 break;
2354 }
2355 }
311a2094
PZ		 2356
2357 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2358 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2359 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2360 if (!init_dp && !init_hdmi) {
500ea70d 2361 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, respect it\n",
311a2094 2362 port_name(port));
500ea70d 2363 return;
311a2094 2364 }
00c09d70 2365
b14c5679 2366 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 2367 if (!intel_dig_port)
2368 return;
2369
00c09d70
PZ		 2370 intel_encoder = &intel_dig_port->base;
2371 encoder = &intel_encoder->base;
2372
2373 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
580d8ed5 2374 DRM_MODE_ENCODER_TMDS, "DDI %c", port_name(port));
00c09d70 2375
5bfe2ac0 2376 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70 2377 intel_encoder->enable = intel_enable_ddi;
95a7a2ae
ID		 2378 if (IS_BROXTON(dev_priv))
2379 intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
00c09d70
PZ		 2380 intel_encoder->pre_enable = intel_ddi_pre_enable;
2381 intel_encoder->disable = intel_disable_ddi;
2382 intel_encoder->post_disable = intel_ddi_post_disable;
2383 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 2384 intel_encoder->get_config = intel_ddi_get_config;
bf93ba67 2385 intel_encoder->suspend = intel_dp_encoder_suspend;
00c09d70
PZ		 2386
2387 intel_dig_port->port = port;
bcf53de4
SM		 2388 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2389 (DDI_BUF_PORT_REVERSAL |
2390 DDI_A_4_LANES);
00c09d70 2391
6c566dc9
MR		 2392 /*
2393 * Bspec says that DDI_A_4_LANES is the only supported configuration
2394 * for Broxton. Yet some BIOS fail to set this bit on port A if eDP
2395 * wasn't lit up at boot. Force this bit on in our internal
2396 * configuration so that we use the proper lane count for our
2397 * calculations.
2398 */
2399 if (IS_BROXTON(dev) && port == PORT_A) {
2400 if (!(intel_dig_port->saved_port_bits & DDI_A_4_LANES)) {
2401 DRM_DEBUG_KMS("BXT BIOS forgot to set DDI_A_4_LANES for port A; fixing\n");
2402 intel_dig_port->saved_port_bits |= DDI_A_4_LANES;
ed8d60f4 2403 max_lanes = 4;
6c566dc9
MR		 2404 }
2405 }
2406
ed8d60f4
MR		 2407 intel_dig_port->max_lanes = max_lanes;
2408
00c09d70 2409 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 2410 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 2411 intel_encoder->cloneable = 0;
00c09d70 2412
f68d697e
CW		 2413 if (init_dp) {
2414 if (!intel_ddi_init_dp_connector(intel_dig_port))
2415 goto err;
13cf5504 2416
f68d697e 2417 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
cf1d5883
SJ		 2418 /*
2419 * On BXT A0/A1, sw needs to activate DDIA HPD logic and
2420 * interrupts to check the external panel connection.
2421 */
e87a005d 2422 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) && port == PORT_B)
cf1d5883
SJ		 2423 dev_priv->hotplug.irq_port[PORT_A] = intel_dig_port;
2424 else
2425 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 2426 }
21a8e6a4 2427
311a2094
PZ		 2428 /* In theory we don't need the encoder->type check, but leave it just in
2429 * case we have some really bad VBTs... */
f68d697e
CW		 2430 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2431 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2432 goto err;
21a8e6a4 2433 }
f68d697e
CW		 2434
2435 return;
2436
2437err:
2438 drm_encoder_cleanup(encoder);
2439 kfree(intel_dig_port);
00c09d70 2440}
Linux kernel - Deliverables
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