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45244b87 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "i915_drv.h" | |
29 | #include "intel_drv.h" | |
30 | ||
10122051 JN |
31 | struct ddi_buf_trans { |
32 | u32 trans1; /* balance leg enable, de-emph level */ | |
33 | u32 trans2; /* vref sel, vswing */ | |
34 | }; | |
35 | ||
45244b87 ED |
36 | /* HDMI/DVI modes ignore everything but the last 2 items. So we share |
37 | * them for both DP and FDI transports, allowing those ports to | |
38 | * automatically adapt to HDMI connections as well | |
39 | */ | |
10122051 JN |
40 | static const struct ddi_buf_trans hsw_ddi_translations_dp[] = { |
41 | { 0x00FFFFFF, 0x0006000E }, | |
42 | { 0x00D75FFF, 0x0005000A }, | |
43 | { 0x00C30FFF, 0x00040006 }, | |
44 | { 0x80AAAFFF, 0x000B0000 }, | |
45 | { 0x00FFFFFF, 0x0005000A }, | |
46 | { 0x00D75FFF, 0x000C0004 }, | |
47 | { 0x80C30FFF, 0x000B0000 }, | |
48 | { 0x00FFFFFF, 0x00040006 }, | |
49 | { 0x80D75FFF, 0x000B0000 }, | |
45244b87 ED |
50 | }; |
51 | ||
10122051 JN |
52 | static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = { |
53 | { 0x00FFFFFF, 0x0007000E }, | |
54 | { 0x00D75FFF, 0x000F000A }, | |
55 | { 0x00C30FFF, 0x00060006 }, | |
56 | { 0x00AAAFFF, 0x001E0000 }, | |
57 | { 0x00FFFFFF, 0x000F000A }, | |
58 | { 0x00D75FFF, 0x00160004 }, | |
59 | { 0x00C30FFF, 0x001E0000 }, | |
60 | { 0x00FFFFFF, 0x00060006 }, | |
61 | { 0x00D75FFF, 0x001E0000 }, | |
6acab15a PZ |
62 | }; |
63 | ||
10122051 JN |
64 | static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = { |
65 | /* Idx NT mV d T mV d db */ | |
66 | { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */ | |
67 | { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */ | |
68 | { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */ | |
69 | { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */ | |
70 | { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */ | |
71 | { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */ | |
72 | { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */ | |
73 | { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */ | |
74 | { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */ | |
75 | { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */ | |
76 | { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */ | |
77 | { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */ | |
45244b87 ED |
78 | }; |
79 | ||
10122051 JN |
80 | static const struct ddi_buf_trans bdw_ddi_translations_edp[] = { |
81 | { 0x00FFFFFF, 0x00000012 }, | |
82 | { 0x00EBAFFF, 0x00020011 }, | |
83 | { 0x00C71FFF, 0x0006000F }, | |
84 | { 0x00AAAFFF, 0x000E000A }, | |
85 | { 0x00FFFFFF, 0x00020011 }, | |
86 | { 0x00DB6FFF, 0x0005000F }, | |
87 | { 0x00BEEFFF, 0x000A000C }, | |
88 | { 0x00FFFFFF, 0x0005000F }, | |
89 | { 0x00DB6FFF, 0x000A000C }, | |
300644c7 PZ |
90 | }; |
91 | ||
10122051 JN |
92 | static const struct ddi_buf_trans bdw_ddi_translations_dp[] = { |
93 | { 0x00FFFFFF, 0x0007000E }, | |
94 | { 0x00D75FFF, 0x000E000A }, | |
95 | { 0x00BEFFFF, 0x00140006 }, | |
96 | { 0x80B2CFFF, 0x001B0002 }, | |
97 | { 0x00FFFFFF, 0x000E000A }, | |
17b523ba | 98 | { 0x00DB6FFF, 0x00160005 }, |
6805b2a7 | 99 | { 0x80C71FFF, 0x001A0002 }, |
10122051 JN |
100 | { 0x00F7DFFF, 0x00180004 }, |
101 | { 0x80D75FFF, 0x001B0002 }, | |
e58623cb AR |
102 | }; |
103 | ||
10122051 JN |
104 | static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = { |
105 | { 0x00FFFFFF, 0x0001000E }, | |
106 | { 0x00D75FFF, 0x0004000A }, | |
107 | { 0x00C30FFF, 0x00070006 }, | |
108 | { 0x00AAAFFF, 0x000C0000 }, | |
109 | { 0x00FFFFFF, 0x0004000A }, | |
110 | { 0x00D75FFF, 0x00090004 }, | |
111 | { 0x00C30FFF, 0x000C0000 }, | |
112 | { 0x00FFFFFF, 0x00070006 }, | |
113 | { 0x00D75FFF, 0x000C0000 }, | |
e58623cb AR |
114 | }; |
115 | ||
10122051 JN |
116 | static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = { |
117 | /* Idx NT mV d T mV df db */ | |
118 | { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */ | |
119 | { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */ | |
120 | { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */ | |
121 | { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */ | |
122 | { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */ | |
123 | { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */ | |
124 | { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */ | |
125 | { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */ | |
126 | { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */ | |
127 | { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */ | |
a26aa8ba DL |
128 | }; |
129 | ||
7f88e3af | 130 | static const struct ddi_buf_trans skl_ddi_translations_dp[] = { |
6c930688 DL |
131 | { 0x00000018, 0x000000a2 }, |
132 | { 0x00004014, 0x0000009B }, | |
7f88e3af | 133 | { 0x00006012, 0x00000088 }, |
6c930688 DL |
134 | { 0x00008010, 0x00000087 }, |
135 | { 0x00000018, 0x0000009B }, | |
7f88e3af | 136 | { 0x00004014, 0x00000088 }, |
6c930688 | 137 | { 0x00006012, 0x00000087 }, |
7f88e3af | 138 | { 0x00000018, 0x00000088 }, |
6c930688 | 139 | { 0x00004014, 0x00000087 }, |
7f88e3af DL |
140 | }; |
141 | ||
7ad14a29 SJ |
142 | /* eDP 1.4 low vswing translation parameters */ |
143 | static const struct ddi_buf_trans skl_ddi_translations_edp[] = { | |
144 | { 0x00000018, 0x000000a8 }, | |
145 | { 0x00002016, 0x000000ab }, | |
146 | { 0x00006012, 0x000000a2 }, | |
147 | { 0x00008010, 0x00000088 }, | |
148 | { 0x00000018, 0x000000ab }, | |
149 | { 0x00004014, 0x000000a2 }, | |
150 | { 0x00006012, 0x000000a6 }, | |
151 | { 0x00000018, 0x000000a2 }, | |
152 | { 0x00005013, 0x0000009c }, | |
153 | { 0x00000018, 0x00000088 }, | |
154 | }; | |
155 | ||
156 | ||
7f88e3af | 157 | static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = { |
b7192a56 SJ |
158 | { 0x00000018, 0x000000ac }, |
159 | { 0x00005012, 0x0000009d }, | |
160 | { 0x00007011, 0x00000088 }, | |
161 | { 0x00000018, 0x000000a1 }, | |
162 | { 0x00000018, 0x00000098 }, | |
163 | { 0x00004013, 0x00000088 }, | |
164 | { 0x00006012, 0x00000087 }, | |
165 | { 0x00000018, 0x000000df }, | |
166 | { 0x00003015, 0x00000087 }, | |
167 | { 0x00003015, 0x000000c7 }, | |
168 | { 0x00000018, 0x000000c7 }, | |
7f88e3af DL |
169 | }; |
170 | ||
96fb9f9b VK |
171 | struct bxt_ddi_buf_trans { |
172 | u32 margin; /* swing value */ | |
173 | u32 scale; /* scale value */ | |
174 | u32 enable; /* scale enable */ | |
175 | u32 deemphasis; | |
176 | bool default_index; /* true if the entry represents default value */ | |
177 | }; | |
178 | ||
179 | /* BSpec does not define separate vswing/pre-emphasis values for eDP. | |
180 | * Using DP values for eDP as well. | |
181 | */ | |
182 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = { | |
183 | /* Idx NT mV diff db */ | |
184 | { 52, 0, 0, 128, true }, /* 0: 400 0 */ | |
185 | { 78, 0, 0, 85, false }, /* 1: 400 3.5 */ | |
186 | { 104, 0, 0, 64, false }, /* 2: 400 6 */ | |
187 | { 154, 0, 0, 43, false }, /* 3: 400 9.5 */ | |
188 | { 77, 0, 0, 128, false }, /* 4: 600 0 */ | |
189 | { 116, 0, 0, 85, false }, /* 5: 600 3.5 */ | |
190 | { 154, 0, 0, 64, false }, /* 6: 600 6 */ | |
191 | { 102, 0, 0, 128, false }, /* 7: 800 0 */ | |
192 | { 154, 0, 0, 85, false }, /* 8: 800 3.5 */ | |
193 | { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */ | |
194 | }; | |
195 | ||
196 | /* BSpec has 2 recommended values - entries 0 and 8. | |
197 | * Using the entry with higher vswing. | |
198 | */ | |
199 | static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = { | |
200 | /* Idx NT mV diff db */ | |
201 | { 52, 0, 0, 128, false }, /* 0: 400 0 */ | |
202 | { 52, 0, 0, 85, false }, /* 1: 400 3.5 */ | |
203 | { 52, 0, 0, 64, false }, /* 2: 400 6 */ | |
204 | { 42, 0, 0, 43, false }, /* 3: 400 9.5 */ | |
205 | { 77, 0, 0, 128, false }, /* 4: 600 0 */ | |
206 | { 77, 0, 0, 85, false }, /* 5: 600 3.5 */ | |
207 | { 77, 0, 0, 64, false }, /* 6: 600 6 */ | |
208 | { 102, 0, 0, 128, false }, /* 7: 800 0 */ | |
209 | { 102, 0, 0, 85, false }, /* 8: 800 3.5 */ | |
210 | { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */ | |
211 | }; | |
212 | ||
a1e6ad66 ID |
213 | static void ddi_get_encoder_port(struct intel_encoder *intel_encoder, |
214 | struct intel_digital_port **dig_port, | |
215 | enum port *port) | |
fc914639 | 216 | { |
0bdee30e | 217 | struct drm_encoder *encoder = &intel_encoder->base; |
fc914639 PZ |
218 | int type = intel_encoder->type; |
219 | ||
0e32b39c | 220 | if (type == INTEL_OUTPUT_DP_MST) { |
a1e6ad66 ID |
221 | *dig_port = enc_to_mst(encoder)->primary; |
222 | *port = (*dig_port)->port; | |
0e32b39c | 223 | } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || |
00c09d70 | 224 | type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) { |
a1e6ad66 ID |
225 | *dig_port = enc_to_dig_port(encoder); |
226 | *port = (*dig_port)->port; | |
fc914639 | 227 | } else if (type == INTEL_OUTPUT_ANALOG) { |
a1e6ad66 ID |
228 | *dig_port = NULL; |
229 | *port = PORT_E; | |
fc914639 PZ |
230 | } else { |
231 | DRM_ERROR("Invalid DDI encoder type %d\n", type); | |
232 | BUG(); | |
233 | } | |
234 | } | |
235 | ||
a1e6ad66 ID |
236 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) |
237 | { | |
238 | struct intel_digital_port *dig_port; | |
239 | enum port port; | |
240 | ||
241 | ddi_get_encoder_port(intel_encoder, &dig_port, &port); | |
242 | ||
243 | return port; | |
244 | } | |
245 | ||
ce3b7e9b DL |
246 | static bool |
247 | intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port) | |
248 | { | |
249 | return intel_dig_port->hdmi.hdmi_reg; | |
250 | } | |
251 | ||
e58623cb AR |
252 | /* |
253 | * Starting with Haswell, DDI port buffers must be programmed with correct | |
254 | * values in advance. The buffer values are different for FDI and DP modes, | |
45244b87 ED |
255 | * but the HDMI/DVI fields are shared among those. So we program the DDI |
256 | * in either FDI or DP modes only, as HDMI connections will work with both | |
257 | * of those | |
258 | */ | |
faa0cdbe ID |
259 | static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port, |
260 | bool supports_hdmi) | |
45244b87 ED |
261 | { |
262 | struct drm_i915_private *dev_priv = dev->dev_private; | |
263 | u32 reg; | |
7ff44670 | 264 | int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry, |
7ad14a29 | 265 | size; |
6acab15a | 266 | int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; |
10122051 JN |
267 | const struct ddi_buf_trans *ddi_translations_fdi; |
268 | const struct ddi_buf_trans *ddi_translations_dp; | |
269 | const struct ddi_buf_trans *ddi_translations_edp; | |
270 | const struct ddi_buf_trans *ddi_translations_hdmi; | |
271 | const struct ddi_buf_trans *ddi_translations; | |
e58623cb | 272 | |
96fb9f9b | 273 | if (IS_BROXTON(dev)) { |
faa0cdbe | 274 | if (!supports_hdmi) |
96fb9f9b VK |
275 | return; |
276 | ||
277 | /* Vswing programming for HDMI */ | |
278 | bxt_ddi_vswing_sequence(dev, hdmi_level, port, | |
279 | INTEL_OUTPUT_HDMI); | |
280 | return; | |
281 | } else if (IS_SKYLAKE(dev)) { | |
7f88e3af DL |
282 | ddi_translations_fdi = NULL; |
283 | ddi_translations_dp = skl_ddi_translations_dp; | |
7ad14a29 | 284 | n_dp_entries = ARRAY_SIZE(skl_ddi_translations_dp); |
9e458034 | 285 | if (dev_priv->edp_low_vswing) { |
7ad14a29 SJ |
286 | ddi_translations_edp = skl_ddi_translations_edp; |
287 | n_edp_entries = ARRAY_SIZE(skl_ddi_translations_edp); | |
288 | } else { | |
289 | ddi_translations_edp = skl_ddi_translations_dp; | |
290 | n_edp_entries = ARRAY_SIZE(skl_ddi_translations_dp); | |
291 | } | |
292 | ||
7f88e3af DL |
293 | ddi_translations_hdmi = skl_ddi_translations_hdmi; |
294 | n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi); | |
b7192a56 | 295 | hdmi_default_entry = 7; |
7f88e3af | 296 | } else if (IS_BROADWELL(dev)) { |
e58623cb AR |
297 | ddi_translations_fdi = bdw_ddi_translations_fdi; |
298 | ddi_translations_dp = bdw_ddi_translations_dp; | |
300644c7 | 299 | ddi_translations_edp = bdw_ddi_translations_edp; |
a26aa8ba | 300 | ddi_translations_hdmi = bdw_ddi_translations_hdmi; |
7ad14a29 SJ |
301 | n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); |
302 | n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); | |
10122051 | 303 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); |
7ff44670 | 304 | hdmi_default_entry = 7; |
e58623cb AR |
305 | } else if (IS_HASWELL(dev)) { |
306 | ddi_translations_fdi = hsw_ddi_translations_fdi; | |
307 | ddi_translations_dp = hsw_ddi_translations_dp; | |
300644c7 | 308 | ddi_translations_edp = hsw_ddi_translations_dp; |
a26aa8ba | 309 | ddi_translations_hdmi = hsw_ddi_translations_hdmi; |
7ad14a29 | 310 | n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp); |
10122051 | 311 | n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi); |
7ff44670 | 312 | hdmi_default_entry = 6; |
e58623cb AR |
313 | } else { |
314 | WARN(1, "ddi translation table missing\n"); | |
300644c7 | 315 | ddi_translations_edp = bdw_ddi_translations_dp; |
e58623cb AR |
316 | ddi_translations_fdi = bdw_ddi_translations_fdi; |
317 | ddi_translations_dp = bdw_ddi_translations_dp; | |
a26aa8ba | 318 | ddi_translations_hdmi = bdw_ddi_translations_hdmi; |
7ad14a29 SJ |
319 | n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp); |
320 | n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp); | |
10122051 | 321 | n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi); |
7ff44670 | 322 | hdmi_default_entry = 7; |
e58623cb AR |
323 | } |
324 | ||
300644c7 PZ |
325 | switch (port) { |
326 | case PORT_A: | |
327 | ddi_translations = ddi_translations_edp; | |
7ad14a29 | 328 | size = n_edp_entries; |
300644c7 PZ |
329 | break; |
330 | case PORT_B: | |
331 | case PORT_C: | |
300644c7 | 332 | ddi_translations = ddi_translations_dp; |
7ad14a29 | 333 | size = n_dp_entries; |
300644c7 | 334 | break; |
77d8d009 | 335 | case PORT_D: |
7ad14a29 | 336 | if (intel_dp_is_edp(dev, PORT_D)) { |
77d8d009 | 337 | ddi_translations = ddi_translations_edp; |
7ad14a29 SJ |
338 | size = n_edp_entries; |
339 | } else { | |
77d8d009 | 340 | ddi_translations = ddi_translations_dp; |
7ad14a29 SJ |
341 | size = n_dp_entries; |
342 | } | |
77d8d009 | 343 | break; |
300644c7 | 344 | case PORT_E: |
7f88e3af DL |
345 | if (ddi_translations_fdi) |
346 | ddi_translations = ddi_translations_fdi; | |
347 | else | |
348 | ddi_translations = ddi_translations_dp; | |
7ad14a29 | 349 | size = n_dp_entries; |
300644c7 PZ |
350 | break; |
351 | default: | |
352 | BUG(); | |
353 | } | |
45244b87 | 354 | |
7ad14a29 | 355 | for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) { |
10122051 JN |
356 | I915_WRITE(reg, ddi_translations[i].trans1); |
357 | reg += 4; | |
358 | I915_WRITE(reg, ddi_translations[i].trans2); | |
45244b87 ED |
359 | reg += 4; |
360 | } | |
ce4dd49e | 361 | |
faa0cdbe | 362 | if (!supports_hdmi) |
ce3b7e9b DL |
363 | return; |
364 | ||
ce4dd49e DL |
365 | /* Choose a good default if VBT is badly populated */ |
366 | if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN || | |
367 | hdmi_level >= n_hdmi_entries) | |
7ff44670 | 368 | hdmi_level = hdmi_default_entry; |
ce4dd49e | 369 | |
6acab15a | 370 | /* Entry 9 is for HDMI: */ |
10122051 JN |
371 | I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1); |
372 | reg += 4; | |
373 | I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2); | |
374 | reg += 4; | |
45244b87 ED |
375 | } |
376 | ||
377 | /* Program DDI buffers translations for DP. By default, program ports A-D in DP | |
378 | * mode and port E for FDI. | |
379 | */ | |
380 | void intel_prepare_ddi(struct drm_device *dev) | |
381 | { | |
faa0cdbe | 382 | struct intel_encoder *intel_encoder; |
b403745c | 383 | bool visited[I915_MAX_PORTS] = { 0, }; |
45244b87 | 384 | |
0d536cb4 PZ |
385 | if (!HAS_DDI(dev)) |
386 | return; | |
45244b87 | 387 | |
faa0cdbe ID |
388 | for_each_intel_encoder(dev, intel_encoder) { |
389 | struct intel_digital_port *intel_dig_port; | |
390 | enum port port; | |
391 | bool supports_hdmi; | |
392 | ||
393 | ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port); | |
394 | ||
395 | if (visited[port]) | |
b403745c DL |
396 | continue; |
397 | ||
faa0cdbe ID |
398 | supports_hdmi = intel_dig_port && |
399 | intel_dig_port_supports_hdmi(intel_dig_port); | |
400 | ||
401 | intel_prepare_ddi_buffers(dev, port, supports_hdmi); | |
402 | visited[port] = true; | |
b403745c | 403 | } |
45244b87 | 404 | } |
c82e4d26 | 405 | |
248138b5 PZ |
406 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
407 | enum port port) | |
408 | { | |
409 | uint32_t reg = DDI_BUF_CTL(port); | |
410 | int i; | |
411 | ||
3449ca85 | 412 | for (i = 0; i < 16; i++) { |
248138b5 PZ |
413 | udelay(1); |
414 | if (I915_READ(reg) & DDI_BUF_IS_IDLE) | |
415 | return; | |
416 | } | |
417 | DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); | |
418 | } | |
c82e4d26 ED |
419 | |
420 | /* Starting with Haswell, different DDI ports can work in FDI mode for | |
421 | * connection to the PCH-located connectors. For this, it is necessary to train | |
422 | * both the DDI port and PCH receiver for the desired DDI buffer settings. | |
423 | * | |
424 | * The recommended port to work in FDI mode is DDI E, which we use here. Also, | |
425 | * please note that when FDI mode is active on DDI E, it shares 2 lines with | |
426 | * DDI A (which is used for eDP) | |
427 | */ | |
428 | ||
429 | void hsw_fdi_link_train(struct drm_crtc *crtc) | |
430 | { | |
431 | struct drm_device *dev = crtc->dev; | |
432 | struct drm_i915_private *dev_priv = dev->dev_private; | |
433 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
04945641 | 434 | u32 temp, i, rx_ctl_val; |
c82e4d26 | 435 | |
04945641 PZ |
436 | /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the |
437 | * mode set "sequence for CRT port" document: | |
438 | * - TP1 to TP2 time with the default value | |
439 | * - FDI delay to 90h | |
8693a824 DL |
440 | * |
441 | * WaFDIAutoLinkSetTimingOverrride:hsw | |
04945641 PZ |
442 | */ |
443 | I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) | | |
444 | FDI_RX_PWRDN_LANE0_VAL(2) | | |
445 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
446 | ||
447 | /* Enable the PCH Receiver FDI PLL */ | |
3e68320e | 448 | rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | |
33d29b14 | 449 | FDI_RX_PLL_ENABLE | |
6e3c9717 | 450 | FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes); |
04945641 PZ |
451 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); |
452 | POSTING_READ(_FDI_RXA_CTL); | |
453 | udelay(220); | |
454 | ||
455 | /* Switch from Rawclk to PCDclk */ | |
456 | rx_ctl_val |= FDI_PCDCLK; | |
457 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
458 | ||
459 | /* Configure Port Clock Select */ | |
6e3c9717 ACO |
460 | I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel); |
461 | WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL); | |
04945641 PZ |
462 | |
463 | /* Start the training iterating through available voltages and emphasis, | |
464 | * testing each value twice. */ | |
10122051 | 465 | for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) { |
c82e4d26 ED |
466 | /* Configure DP_TP_CTL with auto-training */ |
467 | I915_WRITE(DP_TP_CTL(PORT_E), | |
468 | DP_TP_CTL_FDI_AUTOTRAIN | | |
469 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
470 | DP_TP_CTL_LINK_TRAIN_PAT1 | | |
471 | DP_TP_CTL_ENABLE); | |
472 | ||
876a8cdf DL |
473 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. |
474 | * DDI E does not support port reversal, the functionality is | |
475 | * achieved on the PCH side in FDI_RX_CTL, so no need to set the | |
476 | * port reversal bit */ | |
c82e4d26 | 477 | I915_WRITE(DDI_BUF_CTL(PORT_E), |
04945641 | 478 | DDI_BUF_CTL_ENABLE | |
6e3c9717 | 479 | ((intel_crtc->config->fdi_lanes - 1) << 1) | |
c5fe6a06 | 480 | DDI_BUF_TRANS_SELECT(i / 2)); |
04945641 | 481 | POSTING_READ(DDI_BUF_CTL(PORT_E)); |
c82e4d26 ED |
482 | |
483 | udelay(600); | |
484 | ||
04945641 PZ |
485 | /* Program PCH FDI Receiver TU */ |
486 | I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64)); | |
487 | ||
488 | /* Enable PCH FDI Receiver with auto-training */ | |
489 | rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; | |
490 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
491 | POSTING_READ(_FDI_RXA_CTL); | |
492 | ||
493 | /* Wait for FDI receiver lane calibration */ | |
494 | udelay(30); | |
495 | ||
496 | /* Unset FDI_RX_MISC pwrdn lanes */ | |
497 | temp = I915_READ(_FDI_RXA_MISC); | |
498 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
499 | I915_WRITE(_FDI_RXA_MISC, temp); | |
500 | POSTING_READ(_FDI_RXA_MISC); | |
501 | ||
502 | /* Wait for FDI auto training time */ | |
503 | udelay(5); | |
c82e4d26 ED |
504 | |
505 | temp = I915_READ(DP_TP_STATUS(PORT_E)); | |
506 | if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { | |
04945641 | 507 | DRM_DEBUG_KMS("FDI link training done on step %d\n", i); |
c82e4d26 ED |
508 | |
509 | /* Enable normal pixel sending for FDI */ | |
510 | I915_WRITE(DP_TP_CTL(PORT_E), | |
04945641 PZ |
511 | DP_TP_CTL_FDI_AUTOTRAIN | |
512 | DP_TP_CTL_LINK_TRAIN_NORMAL | | |
513 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
514 | DP_TP_CTL_ENABLE); | |
c82e4d26 | 515 | |
04945641 | 516 | return; |
c82e4d26 | 517 | } |
04945641 | 518 | |
248138b5 PZ |
519 | temp = I915_READ(DDI_BUF_CTL(PORT_E)); |
520 | temp &= ~DDI_BUF_CTL_ENABLE; | |
521 | I915_WRITE(DDI_BUF_CTL(PORT_E), temp); | |
522 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
523 | ||
04945641 | 524 | /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ |
248138b5 PZ |
525 | temp = I915_READ(DP_TP_CTL(PORT_E)); |
526 | temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
527 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
528 | I915_WRITE(DP_TP_CTL(PORT_E), temp); | |
529 | POSTING_READ(DP_TP_CTL(PORT_E)); | |
530 | ||
531 | intel_wait_ddi_buf_idle(dev_priv, PORT_E); | |
04945641 PZ |
532 | |
533 | rx_ctl_val &= ~FDI_RX_ENABLE; | |
534 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
248138b5 | 535 | POSTING_READ(_FDI_RXA_CTL); |
04945641 PZ |
536 | |
537 | /* Reset FDI_RX_MISC pwrdn lanes */ | |
538 | temp = I915_READ(_FDI_RXA_MISC); | |
539 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
540 | temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
541 | I915_WRITE(_FDI_RXA_MISC, temp); | |
248138b5 | 542 | POSTING_READ(_FDI_RXA_MISC); |
c82e4d26 ED |
543 | } |
544 | ||
04945641 | 545 | DRM_ERROR("FDI link training failed!\n"); |
c82e4d26 | 546 | } |
0e72a5b5 | 547 | |
44905a27 DA |
548 | void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) |
549 | { | |
550 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
551 | struct intel_digital_port *intel_dig_port = | |
552 | enc_to_dig_port(&encoder->base); | |
553 | ||
554 | intel_dp->DP = intel_dig_port->saved_port_bits | | |
c5fe6a06 | 555 | DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0); |
44905a27 DA |
556 | intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); |
557 | ||
558 | } | |
559 | ||
8d9ddbcb PZ |
560 | static struct intel_encoder * |
561 | intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) | |
562 | { | |
563 | struct drm_device *dev = crtc->dev; | |
564 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
565 | struct intel_encoder *intel_encoder, *ret = NULL; | |
566 | int num_encoders = 0; | |
567 | ||
568 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { | |
569 | ret = intel_encoder; | |
570 | num_encoders++; | |
571 | } | |
572 | ||
573 | if (num_encoders != 1) | |
84f44ce7 VS |
574 | WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, |
575 | pipe_name(intel_crtc->pipe)); | |
8d9ddbcb PZ |
576 | |
577 | BUG_ON(ret == NULL); | |
578 | return ret; | |
579 | } | |
580 | ||
bcddf610 | 581 | struct intel_encoder * |
3165c074 | 582 | intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state) |
d0737e1d | 583 | { |
3165c074 ACO |
584 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
585 | struct intel_encoder *ret = NULL; | |
586 | struct drm_atomic_state *state; | |
da3ced29 ACO |
587 | struct drm_connector *connector; |
588 | struct drm_connector_state *connector_state; | |
d0737e1d | 589 | int num_encoders = 0; |
3165c074 | 590 | int i; |
d0737e1d | 591 | |
3165c074 ACO |
592 | state = crtc_state->base.state; |
593 | ||
da3ced29 ACO |
594 | for_each_connector_in_state(state, connector, connector_state, i) { |
595 | if (connector_state->crtc != crtc_state->base.crtc) | |
3165c074 ACO |
596 | continue; |
597 | ||
da3ced29 | 598 | ret = to_intel_encoder(connector_state->best_encoder); |
3165c074 | 599 | num_encoders++; |
d0737e1d ACO |
600 | } |
601 | ||
602 | WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders, | |
603 | pipe_name(crtc->pipe)); | |
604 | ||
605 | BUG_ON(ret == NULL); | |
606 | return ret; | |
607 | } | |
608 | ||
1c0b85c5 | 609 | #define LC_FREQ 2700 |
27893390 | 610 | #define LC_FREQ_2K U64_C(LC_FREQ * 2000) |
1c0b85c5 DL |
611 | |
612 | #define P_MIN 2 | |
613 | #define P_MAX 64 | |
614 | #define P_INC 2 | |
615 | ||
616 | /* Constraints for PLL good behavior */ | |
617 | #define REF_MIN 48 | |
618 | #define REF_MAX 400 | |
619 | #define VCO_MIN 2400 | |
620 | #define VCO_MAX 4800 | |
621 | ||
27893390 DL |
622 | #define abs_diff(a, b) ({ \ |
623 | typeof(a) __a = (a); \ | |
624 | typeof(b) __b = (b); \ | |
625 | (void) (&__a == &__b); \ | |
626 | __a > __b ? (__a - __b) : (__b - __a); }) | |
1c0b85c5 DL |
627 | |
628 | struct wrpll_rnp { | |
629 | unsigned p, n2, r2; | |
630 | }; | |
631 | ||
632 | static unsigned wrpll_get_budget_for_freq(int clock) | |
6441ab5f | 633 | { |
1c0b85c5 DL |
634 | unsigned budget; |
635 | ||
636 | switch (clock) { | |
637 | case 25175000: | |
638 | case 25200000: | |
639 | case 27000000: | |
640 | case 27027000: | |
641 | case 37762500: | |
642 | case 37800000: | |
643 | case 40500000: | |
644 | case 40541000: | |
645 | case 54000000: | |
646 | case 54054000: | |
647 | case 59341000: | |
648 | case 59400000: | |
649 | case 72000000: | |
650 | case 74176000: | |
651 | case 74250000: | |
652 | case 81000000: | |
653 | case 81081000: | |
654 | case 89012000: | |
655 | case 89100000: | |
656 | case 108000000: | |
657 | case 108108000: | |
658 | case 111264000: | |
659 | case 111375000: | |
660 | case 148352000: | |
661 | case 148500000: | |
662 | case 162000000: | |
663 | case 162162000: | |
664 | case 222525000: | |
665 | case 222750000: | |
666 | case 296703000: | |
667 | case 297000000: | |
668 | budget = 0; | |
669 | break; | |
670 | case 233500000: | |
671 | case 245250000: | |
672 | case 247750000: | |
673 | case 253250000: | |
674 | case 298000000: | |
675 | budget = 1500; | |
676 | break; | |
677 | case 169128000: | |
678 | case 169500000: | |
679 | case 179500000: | |
680 | case 202000000: | |
681 | budget = 2000; | |
682 | break; | |
683 | case 256250000: | |
684 | case 262500000: | |
685 | case 270000000: | |
686 | case 272500000: | |
687 | case 273750000: | |
688 | case 280750000: | |
689 | case 281250000: | |
690 | case 286000000: | |
691 | case 291750000: | |
692 | budget = 4000; | |
693 | break; | |
694 | case 267250000: | |
695 | case 268500000: | |
696 | budget = 5000; | |
697 | break; | |
698 | default: | |
699 | budget = 1000; | |
700 | break; | |
701 | } | |
6441ab5f | 702 | |
1c0b85c5 DL |
703 | return budget; |
704 | } | |
705 | ||
706 | static void wrpll_update_rnp(uint64_t freq2k, unsigned budget, | |
707 | unsigned r2, unsigned n2, unsigned p, | |
708 | struct wrpll_rnp *best) | |
709 | { | |
710 | uint64_t a, b, c, d, diff, diff_best; | |
6441ab5f | 711 | |
1c0b85c5 DL |
712 | /* No best (r,n,p) yet */ |
713 | if (best->p == 0) { | |
714 | best->p = p; | |
715 | best->n2 = n2; | |
716 | best->r2 = r2; | |
717 | return; | |
718 | } | |
6441ab5f | 719 | |
1c0b85c5 DL |
720 | /* |
721 | * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to | |
722 | * freq2k. | |
723 | * | |
724 | * delta = 1e6 * | |
725 | * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / | |
726 | * freq2k; | |
727 | * | |
728 | * and we would like delta <= budget. | |
729 | * | |
730 | * If the discrepancy is above the PPM-based budget, always prefer to | |
731 | * improve upon the previous solution. However, if you're within the | |
732 | * budget, try to maximize Ref * VCO, that is N / (P * R^2). | |
733 | */ | |
734 | a = freq2k * budget * p * r2; | |
735 | b = freq2k * budget * best->p * best->r2; | |
27893390 DL |
736 | diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2); |
737 | diff_best = abs_diff(freq2k * best->p * best->r2, | |
738 | LC_FREQ_2K * best->n2); | |
1c0b85c5 DL |
739 | c = 1000000 * diff; |
740 | d = 1000000 * diff_best; | |
741 | ||
742 | if (a < c && b < d) { | |
743 | /* If both are above the budget, pick the closer */ | |
744 | if (best->p * best->r2 * diff < p * r2 * diff_best) { | |
745 | best->p = p; | |
746 | best->n2 = n2; | |
747 | best->r2 = r2; | |
748 | } | |
749 | } else if (a >= c && b < d) { | |
750 | /* If A is below the threshold but B is above it? Update. */ | |
751 | best->p = p; | |
752 | best->n2 = n2; | |
753 | best->r2 = r2; | |
754 | } else if (a >= c && b >= d) { | |
755 | /* Both are below the limit, so pick the higher n2/(r2*r2) */ | |
756 | if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { | |
757 | best->p = p; | |
758 | best->n2 = n2; | |
759 | best->r2 = r2; | |
760 | } | |
761 | } | |
762 | /* Otherwise a < c && b >= d, do nothing */ | |
763 | } | |
764 | ||
11578553 JB |
765 | static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, |
766 | int reg) | |
767 | { | |
768 | int refclk = LC_FREQ; | |
769 | int n, p, r; | |
770 | u32 wrpll; | |
771 | ||
772 | wrpll = I915_READ(reg); | |
114fe488 DV |
773 | switch (wrpll & WRPLL_PLL_REF_MASK) { |
774 | case WRPLL_PLL_SSC: | |
775 | case WRPLL_PLL_NON_SSC: | |
11578553 JB |
776 | /* |
777 | * We could calculate spread here, but our checking | |
778 | * code only cares about 5% accuracy, and spread is a max of | |
779 | * 0.5% downspread. | |
780 | */ | |
781 | refclk = 135; | |
782 | break; | |
114fe488 | 783 | case WRPLL_PLL_LCPLL: |
11578553 JB |
784 | refclk = LC_FREQ; |
785 | break; | |
786 | default: | |
787 | WARN(1, "bad wrpll refclk\n"); | |
788 | return 0; | |
789 | } | |
790 | ||
791 | r = wrpll & WRPLL_DIVIDER_REF_MASK; | |
792 | p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; | |
793 | n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; | |
794 | ||
20f0ec16 JB |
795 | /* Convert to KHz, p & r have a fixed point portion */ |
796 | return (refclk * n * 100) / (p * r); | |
11578553 JB |
797 | } |
798 | ||
540e732c S |
799 | static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv, |
800 | uint32_t dpll) | |
801 | { | |
802 | uint32_t cfgcr1_reg, cfgcr2_reg; | |
803 | uint32_t cfgcr1_val, cfgcr2_val; | |
804 | uint32_t p0, p1, p2, dco_freq; | |
805 | ||
806 | cfgcr1_reg = GET_CFG_CR1_REG(dpll); | |
807 | cfgcr2_reg = GET_CFG_CR2_REG(dpll); | |
808 | ||
809 | cfgcr1_val = I915_READ(cfgcr1_reg); | |
810 | cfgcr2_val = I915_READ(cfgcr2_reg); | |
811 | ||
812 | p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK; | |
813 | p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK; | |
814 | ||
815 | if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1)) | |
816 | p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8; | |
817 | else | |
818 | p1 = 1; | |
819 | ||
820 | ||
821 | switch (p0) { | |
822 | case DPLL_CFGCR2_PDIV_1: | |
823 | p0 = 1; | |
824 | break; | |
825 | case DPLL_CFGCR2_PDIV_2: | |
826 | p0 = 2; | |
827 | break; | |
828 | case DPLL_CFGCR2_PDIV_3: | |
829 | p0 = 3; | |
830 | break; | |
831 | case DPLL_CFGCR2_PDIV_7: | |
832 | p0 = 7; | |
833 | break; | |
834 | } | |
835 | ||
836 | switch (p2) { | |
837 | case DPLL_CFGCR2_KDIV_5: | |
838 | p2 = 5; | |
839 | break; | |
840 | case DPLL_CFGCR2_KDIV_2: | |
841 | p2 = 2; | |
842 | break; | |
843 | case DPLL_CFGCR2_KDIV_3: | |
844 | p2 = 3; | |
845 | break; | |
846 | case DPLL_CFGCR2_KDIV_1: | |
847 | p2 = 1; | |
848 | break; | |
849 | } | |
850 | ||
851 | dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000; | |
852 | ||
853 | dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 * | |
854 | 1000) / 0x8000; | |
855 | ||
856 | return dco_freq / (p0 * p1 * p2 * 5); | |
857 | } | |
858 | ||
859 | ||
860 | static void skl_ddi_clock_get(struct intel_encoder *encoder, | |
5cec258b | 861 | struct intel_crtc_state *pipe_config) |
540e732c S |
862 | { |
863 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
540e732c S |
864 | int link_clock = 0; |
865 | uint32_t dpll_ctl1, dpll; | |
866 | ||
134ffa44 | 867 | dpll = pipe_config->ddi_pll_sel; |
540e732c S |
868 | |
869 | dpll_ctl1 = I915_READ(DPLL_CTRL1); | |
870 | ||
871 | if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) { | |
872 | link_clock = skl_calc_wrpll_link(dev_priv, dpll); | |
873 | } else { | |
71cd8423 DL |
874 | link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll); |
875 | link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll); | |
540e732c S |
876 | |
877 | switch (link_clock) { | |
71cd8423 | 878 | case DPLL_CTRL1_LINK_RATE_810: |
540e732c S |
879 | link_clock = 81000; |
880 | break; | |
71cd8423 | 881 | case DPLL_CTRL1_LINK_RATE_1080: |
a8f3ef61 SJ |
882 | link_clock = 108000; |
883 | break; | |
71cd8423 | 884 | case DPLL_CTRL1_LINK_RATE_1350: |
540e732c S |
885 | link_clock = 135000; |
886 | break; | |
71cd8423 | 887 | case DPLL_CTRL1_LINK_RATE_1620: |
a8f3ef61 SJ |
888 | link_clock = 162000; |
889 | break; | |
71cd8423 | 890 | case DPLL_CTRL1_LINK_RATE_2160: |
a8f3ef61 SJ |
891 | link_clock = 216000; |
892 | break; | |
71cd8423 | 893 | case DPLL_CTRL1_LINK_RATE_2700: |
540e732c S |
894 | link_clock = 270000; |
895 | break; | |
896 | default: | |
897 | WARN(1, "Unsupported link rate\n"); | |
898 | break; | |
899 | } | |
900 | link_clock *= 2; | |
901 | } | |
902 | ||
903 | pipe_config->port_clock = link_clock; | |
904 | ||
905 | if (pipe_config->has_dp_encoder) | |
2d112de7 | 906 | pipe_config->base.adjusted_mode.crtc_clock = |
540e732c S |
907 | intel_dotclock_calculate(pipe_config->port_clock, |
908 | &pipe_config->dp_m_n); | |
909 | else | |
2d112de7 | 910 | pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; |
540e732c S |
911 | } |
912 | ||
3d51278a | 913 | static void hsw_ddi_clock_get(struct intel_encoder *encoder, |
5cec258b | 914 | struct intel_crtc_state *pipe_config) |
11578553 JB |
915 | { |
916 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
11578553 JB |
917 | int link_clock = 0; |
918 | u32 val, pll; | |
919 | ||
26804afd | 920 | val = pipe_config->ddi_pll_sel; |
11578553 JB |
921 | switch (val & PORT_CLK_SEL_MASK) { |
922 | case PORT_CLK_SEL_LCPLL_810: | |
923 | link_clock = 81000; | |
924 | break; | |
925 | case PORT_CLK_SEL_LCPLL_1350: | |
926 | link_clock = 135000; | |
927 | break; | |
928 | case PORT_CLK_SEL_LCPLL_2700: | |
929 | link_clock = 270000; | |
930 | break; | |
931 | case PORT_CLK_SEL_WRPLL1: | |
932 | link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1); | |
933 | break; | |
934 | case PORT_CLK_SEL_WRPLL2: | |
935 | link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2); | |
936 | break; | |
937 | case PORT_CLK_SEL_SPLL: | |
938 | pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; | |
939 | if (pll == SPLL_PLL_FREQ_810MHz) | |
940 | link_clock = 81000; | |
941 | else if (pll == SPLL_PLL_FREQ_1350MHz) | |
942 | link_clock = 135000; | |
943 | else if (pll == SPLL_PLL_FREQ_2700MHz) | |
944 | link_clock = 270000; | |
945 | else { | |
946 | WARN(1, "bad spll freq\n"); | |
947 | return; | |
948 | } | |
949 | break; | |
950 | default: | |
951 | WARN(1, "bad port clock sel\n"); | |
952 | return; | |
953 | } | |
954 | ||
955 | pipe_config->port_clock = link_clock * 2; | |
956 | ||
957 | if (pipe_config->has_pch_encoder) | |
2d112de7 | 958 | pipe_config->base.adjusted_mode.crtc_clock = |
11578553 JB |
959 | intel_dotclock_calculate(pipe_config->port_clock, |
960 | &pipe_config->fdi_m_n); | |
961 | else if (pipe_config->has_dp_encoder) | |
2d112de7 | 962 | pipe_config->base.adjusted_mode.crtc_clock = |
11578553 JB |
963 | intel_dotclock_calculate(pipe_config->port_clock, |
964 | &pipe_config->dp_m_n); | |
965 | else | |
2d112de7 | 966 | pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; |
11578553 JB |
967 | } |
968 | ||
977bb38d S |
969 | static int bxt_calc_pll_link(struct drm_i915_private *dev_priv, |
970 | enum intel_dpll_id dpll) | |
971 | { | |
972 | /* FIXME formula not available in bspec */ | |
973 | return 0; | |
974 | } | |
975 | ||
976 | static void bxt_ddi_clock_get(struct intel_encoder *encoder, | |
977 | struct intel_crtc_state *pipe_config) | |
978 | { | |
979 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
980 | enum port port = intel_ddi_get_encoder_port(encoder); | |
981 | uint32_t dpll = port; | |
982 | ||
983 | pipe_config->port_clock = | |
984 | bxt_calc_pll_link(dev_priv, dpll); | |
985 | ||
986 | if (pipe_config->has_dp_encoder) | |
987 | pipe_config->base.adjusted_mode.crtc_clock = | |
988 | intel_dotclock_calculate(pipe_config->port_clock, | |
989 | &pipe_config->dp_m_n); | |
990 | else | |
991 | pipe_config->base.adjusted_mode.crtc_clock = | |
992 | pipe_config->port_clock; | |
993 | } | |
994 | ||
3d51278a | 995 | void intel_ddi_clock_get(struct intel_encoder *encoder, |
5cec258b | 996 | struct intel_crtc_state *pipe_config) |
3d51278a | 997 | { |
22606a18 DL |
998 | struct drm_device *dev = encoder->base.dev; |
999 | ||
1000 | if (INTEL_INFO(dev)->gen <= 8) | |
1001 | hsw_ddi_clock_get(encoder, pipe_config); | |
977bb38d | 1002 | else if (IS_SKYLAKE(dev)) |
22606a18 | 1003 | skl_ddi_clock_get(encoder, pipe_config); |
977bb38d S |
1004 | else if (IS_BROXTON(dev)) |
1005 | bxt_ddi_clock_get(encoder, pipe_config); | |
3d51278a DV |
1006 | } |
1007 | ||
1c0b85c5 | 1008 | static void |
d664c0ce DL |
1009 | hsw_ddi_calculate_wrpll(int clock /* in Hz */, |
1010 | unsigned *r2_out, unsigned *n2_out, unsigned *p_out) | |
1c0b85c5 DL |
1011 | { |
1012 | uint64_t freq2k; | |
1013 | unsigned p, n2, r2; | |
1014 | struct wrpll_rnp best = { 0, 0, 0 }; | |
1015 | unsigned budget; | |
1016 | ||
1017 | freq2k = clock / 100; | |
1018 | ||
1019 | budget = wrpll_get_budget_for_freq(clock); | |
1020 | ||
1021 | /* Special case handling for 540 pixel clock: bypass WR PLL entirely | |
1022 | * and directly pass the LC PLL to it. */ | |
1023 | if (freq2k == 5400000) { | |
1024 | *n2_out = 2; | |
1025 | *p_out = 1; | |
1026 | *r2_out = 2; | |
1027 | return; | |
1028 | } | |
1029 | ||
1030 | /* | |
1031 | * Ref = LC_FREQ / R, where Ref is the actual reference input seen by | |
1032 | * the WR PLL. | |
1033 | * | |
1034 | * We want R so that REF_MIN <= Ref <= REF_MAX. | |
1035 | * Injecting R2 = 2 * R gives: | |
1036 | * REF_MAX * r2 > LC_FREQ * 2 and | |
1037 | * REF_MIN * r2 < LC_FREQ * 2 | |
1038 | * | |
1039 | * Which means the desired boundaries for r2 are: | |
1040 | * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN | |
1041 | * | |
1042 | */ | |
1043 | for (r2 = LC_FREQ * 2 / REF_MAX + 1; | |
1044 | r2 <= LC_FREQ * 2 / REF_MIN; | |
1045 | r2++) { | |
1046 | ||
1047 | /* | |
1048 | * VCO = N * Ref, that is: VCO = N * LC_FREQ / R | |
1049 | * | |
1050 | * Once again we want VCO_MIN <= VCO <= VCO_MAX. | |
1051 | * Injecting R2 = 2 * R and N2 = 2 * N, we get: | |
1052 | * VCO_MAX * r2 > n2 * LC_FREQ and | |
1053 | * VCO_MIN * r2 < n2 * LC_FREQ) | |
1054 | * | |
1055 | * Which means the desired boundaries for n2 are: | |
1056 | * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ | |
1057 | */ | |
1058 | for (n2 = VCO_MIN * r2 / LC_FREQ + 1; | |
1059 | n2 <= VCO_MAX * r2 / LC_FREQ; | |
1060 | n2++) { | |
1061 | ||
1062 | for (p = P_MIN; p <= P_MAX; p += P_INC) | |
1063 | wrpll_update_rnp(freq2k, budget, | |
1064 | r2, n2, p, &best); | |
1065 | } | |
1066 | } | |
6441ab5f | 1067 | |
1c0b85c5 DL |
1068 | *n2_out = best.n2; |
1069 | *p_out = best.p; | |
1070 | *r2_out = best.r2; | |
6441ab5f PZ |
1071 | } |
1072 | ||
0220ab6e | 1073 | static bool |
d664c0ce | 1074 | hsw_ddi_pll_select(struct intel_crtc *intel_crtc, |
190f68c5 | 1075 | struct intel_crtc_state *crtc_state, |
d664c0ce DL |
1076 | struct intel_encoder *intel_encoder, |
1077 | int clock) | |
6441ab5f | 1078 | { |
d664c0ce | 1079 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { |
e0b01be4 | 1080 | struct intel_shared_dpll *pll; |
716c2e55 | 1081 | uint32_t val; |
1c0b85c5 | 1082 | unsigned p, n2, r2; |
6441ab5f | 1083 | |
d664c0ce | 1084 | hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); |
0694001b | 1085 | |
114fe488 | 1086 | val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | |
0694001b PZ |
1087 | WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | |
1088 | WRPLL_DIVIDER_POST(p); | |
1089 | ||
dd3cd74a ACO |
1090 | memset(&crtc_state->dpll_hw_state, 0, |
1091 | sizeof(crtc_state->dpll_hw_state)); | |
1092 | ||
190f68c5 | 1093 | crtc_state->dpll_hw_state.wrpll = val; |
6441ab5f | 1094 | |
190f68c5 | 1095 | pll = intel_get_shared_dpll(intel_crtc, crtc_state); |
716c2e55 DV |
1096 | if (pll == NULL) { |
1097 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
1098 | pipe_name(intel_crtc->pipe)); | |
1099 | return false; | |
0694001b | 1100 | } |
d452c5b6 | 1101 | |
190f68c5 | 1102 | crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id); |
6441ab5f PZ |
1103 | } |
1104 | ||
6441ab5f PZ |
1105 | return true; |
1106 | } | |
1107 | ||
82d35437 S |
1108 | struct skl_wrpll_params { |
1109 | uint32_t dco_fraction; | |
1110 | uint32_t dco_integer; | |
1111 | uint32_t qdiv_ratio; | |
1112 | uint32_t qdiv_mode; | |
1113 | uint32_t kdiv; | |
1114 | uint32_t pdiv; | |
1115 | uint32_t central_freq; | |
1116 | }; | |
1117 | ||
1118 | static void | |
1119 | skl_ddi_calculate_wrpll(int clock /* in Hz */, | |
1120 | struct skl_wrpll_params *wrpll_params) | |
1121 | { | |
1122 | uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */ | |
21318cce DL |
1123 | uint64_t dco_central_freq[3] = {8400000000ULL, |
1124 | 9000000000ULL, | |
1125 | 9600000000ULL}; | |
82d35437 S |
1126 | uint32_t min_dco_deviation = 400; |
1127 | uint32_t min_dco_index = 3; | |
1128 | uint32_t P0[4] = {1, 2, 3, 7}; | |
1129 | uint32_t P2[4] = {1, 2, 3, 5}; | |
1130 | bool found = false; | |
1131 | uint32_t candidate_p = 0; | |
1132 | uint32_t candidate_p0[3] = {0}, candidate_p1[3] = {0}; | |
1133 | uint32_t candidate_p2[3] = {0}; | |
1134 | uint32_t dco_central_freq_deviation[3]; | |
1135 | uint32_t i, P1, k, dco_count; | |
1136 | bool retry_with_odd = false; | |
1137 | uint64_t dco_freq; | |
1138 | ||
1139 | /* Determine P0, P1 or P2 */ | |
1140 | for (dco_count = 0; dco_count < 3; dco_count++) { | |
1141 | found = false; | |
1142 | candidate_p = | |
1143 | div64_u64(dco_central_freq[dco_count], afe_clock); | |
1144 | if (retry_with_odd == false) | |
1145 | candidate_p = (candidate_p % 2 == 0 ? | |
1146 | candidate_p : candidate_p + 1); | |
1147 | ||
1148 | for (P1 = 1; P1 < candidate_p; P1++) { | |
1149 | for (i = 0; i < 4; i++) { | |
1150 | if (!(P0[i] != 1 || P1 == 1)) | |
1151 | continue; | |
1152 | ||
1153 | for (k = 0; k < 4; k++) { | |
1154 | if (P1 != 1 && P2[k] != 2) | |
1155 | continue; | |
1156 | ||
1157 | if (candidate_p == P0[i] * P1 * P2[k]) { | |
1158 | /* Found possible P0, P1, P2 */ | |
1159 | found = true; | |
1160 | candidate_p0[dco_count] = P0[i]; | |
1161 | candidate_p1[dco_count] = P1; | |
1162 | candidate_p2[dco_count] = P2[k]; | |
1163 | goto found; | |
1164 | } | |
1165 | ||
1166 | } | |
1167 | } | |
1168 | } | |
1169 | ||
1170 | found: | |
1171 | if (found) { | |
1172 | dco_central_freq_deviation[dco_count] = | |
1173 | div64_u64(10000 * | |
1174 | abs_diff((candidate_p * afe_clock), | |
1175 | dco_central_freq[dco_count]), | |
1176 | dco_central_freq[dco_count]); | |
1177 | ||
1178 | if (dco_central_freq_deviation[dco_count] < | |
1179 | min_dco_deviation) { | |
1180 | min_dco_deviation = | |
1181 | dco_central_freq_deviation[dco_count]; | |
1182 | min_dco_index = dco_count; | |
1183 | } | |
1184 | } | |
1185 | ||
1186 | if (min_dco_index > 2 && dco_count == 2) { | |
1187 | retry_with_odd = true; | |
1188 | dco_count = 0; | |
1189 | } | |
1190 | } | |
1191 | ||
1192 | if (min_dco_index > 2) { | |
1193 | WARN(1, "No valid values found for the given pixel clock\n"); | |
1194 | } else { | |
ebf7ed1a | 1195 | wrpll_params->central_freq = dco_central_freq[min_dco_index]; |
82d35437 | 1196 | |
ebf7ed1a DL |
1197 | switch (dco_central_freq[min_dco_index]) { |
1198 | case 9600000000ULL: | |
82d35437 S |
1199 | wrpll_params->central_freq = 0; |
1200 | break; | |
ebf7ed1a | 1201 | case 9000000000ULL: |
82d35437 S |
1202 | wrpll_params->central_freq = 1; |
1203 | break; | |
ebf7ed1a | 1204 | case 8400000000ULL: |
82d35437 | 1205 | wrpll_params->central_freq = 3; |
ebf7ed1a | 1206 | } |
82d35437 | 1207 | |
ebf7ed1a DL |
1208 | switch (candidate_p0[min_dco_index]) { |
1209 | case 1: | |
82d35437 S |
1210 | wrpll_params->pdiv = 0; |
1211 | break; | |
ebf7ed1a | 1212 | case 2: |
82d35437 S |
1213 | wrpll_params->pdiv = 1; |
1214 | break; | |
ebf7ed1a | 1215 | case 3: |
82d35437 S |
1216 | wrpll_params->pdiv = 2; |
1217 | break; | |
ebf7ed1a | 1218 | case 7: |
82d35437 S |
1219 | wrpll_params->pdiv = 4; |
1220 | break; | |
ebf7ed1a | 1221 | default: |
82d35437 | 1222 | WARN(1, "Incorrect PDiv\n"); |
ebf7ed1a | 1223 | } |
82d35437 | 1224 | |
ebf7ed1a DL |
1225 | switch (candidate_p2[min_dco_index]) { |
1226 | case 5: | |
82d35437 S |
1227 | wrpll_params->kdiv = 0; |
1228 | break; | |
ebf7ed1a | 1229 | case 2: |
82d35437 S |
1230 | wrpll_params->kdiv = 1; |
1231 | break; | |
ebf7ed1a | 1232 | case 3: |
82d35437 S |
1233 | wrpll_params->kdiv = 2; |
1234 | break; | |
ebf7ed1a | 1235 | case 1: |
82d35437 S |
1236 | wrpll_params->kdiv = 3; |
1237 | break; | |
ebf7ed1a | 1238 | default: |
82d35437 | 1239 | WARN(1, "Incorrect KDiv\n"); |
ebf7ed1a | 1240 | } |
82d35437 | 1241 | |
ebf7ed1a DL |
1242 | wrpll_params->qdiv_ratio = candidate_p1[min_dco_index]; |
1243 | wrpll_params->qdiv_mode = | |
82d35437 S |
1244 | (wrpll_params->qdiv_ratio == 1) ? 0 : 1; |
1245 | ||
ebf7ed1a DL |
1246 | dco_freq = candidate_p0[min_dco_index] * |
1247 | candidate_p1[min_dco_index] * | |
1248 | candidate_p2[min_dco_index] * afe_clock; | |
82d35437 S |
1249 | |
1250 | /* | |
ebf7ed1a DL |
1251 | * Intermediate values are in Hz. |
1252 | * Divide by MHz to match bsepc | |
1253 | */ | |
1254 | wrpll_params->dco_integer = div_u64(dco_freq, (24 * MHz(1))); | |
1255 | wrpll_params->dco_fraction = | |
1256 | div_u64(((div_u64(dco_freq, 24) - | |
1257 | wrpll_params->dco_integer * MHz(1)) * 0x8000), MHz(1)); | |
82d35437 S |
1258 | |
1259 | } | |
1260 | } | |
1261 | ||
1262 | ||
1263 | static bool | |
1264 | skl_ddi_pll_select(struct intel_crtc *intel_crtc, | |
190f68c5 | 1265 | struct intel_crtc_state *crtc_state, |
82d35437 S |
1266 | struct intel_encoder *intel_encoder, |
1267 | int clock) | |
1268 | { | |
1269 | struct intel_shared_dpll *pll; | |
1270 | uint32_t ctrl1, cfgcr1, cfgcr2; | |
1271 | ||
1272 | /* | |
1273 | * See comment in intel_dpll_hw_state to understand why we always use 0 | |
1274 | * as the DPLL id in this function. | |
1275 | */ | |
1276 | ||
1277 | ctrl1 = DPLL_CTRL1_OVERRIDE(0); | |
1278 | ||
1279 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { | |
1280 | struct skl_wrpll_params wrpll_params = { 0, }; | |
1281 | ||
1282 | ctrl1 |= DPLL_CTRL1_HDMI_MODE(0); | |
1283 | ||
1284 | skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params); | |
1285 | ||
1286 | cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE | | |
1287 | DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) | | |
1288 | wrpll_params.dco_integer; | |
1289 | ||
1290 | cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) | | |
1291 | DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) | | |
1292 | DPLL_CFGCR2_KDIV(wrpll_params.kdiv) | | |
1293 | DPLL_CFGCR2_PDIV(wrpll_params.pdiv) | | |
1294 | wrpll_params.central_freq; | |
1295 | } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) { | |
1296 | struct drm_encoder *encoder = &intel_encoder->base; | |
1297 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1298 | ||
1299 | switch (intel_dp->link_bw) { | |
1300 | case DP_LINK_BW_1_62: | |
71cd8423 | 1301 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0); |
82d35437 S |
1302 | break; |
1303 | case DP_LINK_BW_2_7: | |
71cd8423 | 1304 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0); |
82d35437 S |
1305 | break; |
1306 | case DP_LINK_BW_5_4: | |
71cd8423 | 1307 | ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0); |
82d35437 S |
1308 | break; |
1309 | } | |
1310 | ||
1311 | cfgcr1 = cfgcr2 = 0; | |
1312 | } else /* eDP */ | |
1313 | return true; | |
1314 | ||
dd3cd74a ACO |
1315 | memset(&crtc_state->dpll_hw_state, 0, |
1316 | sizeof(crtc_state->dpll_hw_state)); | |
1317 | ||
190f68c5 ACO |
1318 | crtc_state->dpll_hw_state.ctrl1 = ctrl1; |
1319 | crtc_state->dpll_hw_state.cfgcr1 = cfgcr1; | |
1320 | crtc_state->dpll_hw_state.cfgcr2 = cfgcr2; | |
82d35437 | 1321 | |
190f68c5 | 1322 | pll = intel_get_shared_dpll(intel_crtc, crtc_state); |
82d35437 S |
1323 | if (pll == NULL) { |
1324 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
1325 | pipe_name(intel_crtc->pipe)); | |
1326 | return false; | |
1327 | } | |
1328 | ||
1329 | /* shared DPLL id 0 is DPLL 1 */ | |
190f68c5 | 1330 | crtc_state->ddi_pll_sel = pll->id + 1; |
82d35437 S |
1331 | |
1332 | return true; | |
1333 | } | |
0220ab6e | 1334 | |
d683f3bc S |
1335 | /* bxt clock parameters */ |
1336 | struct bxt_clk_div { | |
1337 | uint32_t p1; | |
1338 | uint32_t p2; | |
1339 | uint32_t m2_int; | |
1340 | uint32_t m2_frac; | |
1341 | bool m2_frac_en; | |
1342 | uint32_t n; | |
1343 | uint32_t prop_coef; | |
1344 | uint32_t int_coef; | |
1345 | uint32_t gain_ctl; | |
1346 | uint32_t targ_cnt; | |
1347 | uint32_t lanestagger; | |
1348 | }; | |
1349 | ||
1350 | /* pre-calculated values for DP linkrates */ | |
1351 | static struct bxt_clk_div bxt_dp_clk_val[7] = { | |
1352 | /* 162 */ {4, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd}, | |
1353 | /* 270 */ {4, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0xd}, | |
1354 | /* 540 */ {2, 1, 27, 0, 0, 1, 3, 8, 1, 9, 0x18}, | |
1355 | /* 216 */ {3, 2, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd}, | |
1356 | /* 243 */ {4, 1, 24, 1258291, 1, 1, 5, 11, 2, 9, 0xd}, | |
1357 | /* 324 */ {4, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0xd}, | |
1358 | /* 432 */ {3, 1, 32, 1677722, 1, 1, 5, 11, 2, 9, 0x18} | |
1359 | }; | |
1360 | ||
1361 | static bool | |
1362 | bxt_ddi_pll_select(struct intel_crtc *intel_crtc, | |
1363 | struct intel_crtc_state *crtc_state, | |
1364 | struct intel_encoder *intel_encoder, | |
1365 | int clock) | |
1366 | { | |
1367 | struct intel_shared_dpll *pll; | |
1368 | struct bxt_clk_div clk_div = {0}; | |
1369 | ||
1370 | if (intel_encoder->type == INTEL_OUTPUT_HDMI) { | |
1371 | intel_clock_t best_clock; | |
1372 | ||
1373 | /* Calculate HDMI div */ | |
1374 | /* | |
1375 | * FIXME: tie the following calculation into | |
1376 | * i9xx_crtc_compute_clock | |
1377 | */ | |
1378 | if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) { | |
1379 | DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n", | |
1380 | clock, pipe_name(intel_crtc->pipe)); | |
1381 | return false; | |
1382 | } | |
1383 | ||
1384 | clk_div.p1 = best_clock.p1; | |
1385 | clk_div.p2 = best_clock.p2; | |
1386 | WARN_ON(best_clock.m1 != 2); | |
1387 | clk_div.n = best_clock.n; | |
1388 | clk_div.m2_int = best_clock.m2 >> 22; | |
1389 | clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1); | |
1390 | clk_div.m2_frac_en = clk_div.m2_frac != 0; | |
1391 | ||
1392 | /* FIXME: set coef, gain, targcnt based on freq band */ | |
1393 | clk_div.prop_coef = 5; | |
1394 | clk_div.int_coef = 11; | |
1395 | clk_div.gain_ctl = 2; | |
1396 | clk_div.targ_cnt = 9; | |
1397 | if (clock > 270000) | |
1398 | clk_div.lanestagger = 0x18; | |
1399 | else if (clock > 135000) | |
1400 | clk_div.lanestagger = 0x0d; | |
1401 | else if (clock > 67000) | |
1402 | clk_div.lanestagger = 0x07; | |
1403 | else if (clock > 33000) | |
1404 | clk_div.lanestagger = 0x04; | |
1405 | else | |
1406 | clk_div.lanestagger = 0x02; | |
1407 | } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || | |
1408 | intel_encoder->type == INTEL_OUTPUT_EDP) { | |
1409 | struct drm_encoder *encoder = &intel_encoder->base; | |
1410 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1411 | ||
1412 | switch (intel_dp->link_bw) { | |
1413 | case DP_LINK_BW_1_62: | |
1414 | clk_div = bxt_dp_clk_val[0]; | |
1415 | break; | |
1416 | case DP_LINK_BW_2_7: | |
1417 | clk_div = bxt_dp_clk_val[1]; | |
1418 | break; | |
1419 | case DP_LINK_BW_5_4: | |
1420 | clk_div = bxt_dp_clk_val[2]; | |
1421 | break; | |
1422 | default: | |
1423 | clk_div = bxt_dp_clk_val[0]; | |
1424 | DRM_ERROR("Unknown link rate\n"); | |
1425 | } | |
1426 | } | |
1427 | ||
dd3cd74a ACO |
1428 | memset(&crtc_state->dpll_hw_state, 0, |
1429 | sizeof(crtc_state->dpll_hw_state)); | |
1430 | ||
d683f3bc S |
1431 | crtc_state->dpll_hw_state.ebb0 = |
1432 | PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2); | |
1433 | crtc_state->dpll_hw_state.pll0 = clk_div.m2_int; | |
1434 | crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n); | |
1435 | crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac; | |
1436 | ||
1437 | if (clk_div.m2_frac_en) | |
1438 | crtc_state->dpll_hw_state.pll3 = | |
1439 | PORT_PLL_M2_FRAC_ENABLE; | |
1440 | ||
1441 | crtc_state->dpll_hw_state.pll6 = | |
1442 | clk_div.prop_coef | PORT_PLL_INT_COEFF(clk_div.int_coef); | |
1443 | crtc_state->dpll_hw_state.pll6 |= | |
1444 | PORT_PLL_GAIN_CTL(clk_div.gain_ctl); | |
1445 | ||
1446 | crtc_state->dpll_hw_state.pll8 = clk_div.targ_cnt; | |
1447 | ||
1448 | crtc_state->dpll_hw_state.pcsdw12 = | |
1449 | LANESTAGGER_STRAP_OVRD | clk_div.lanestagger; | |
1450 | ||
1451 | pll = intel_get_shared_dpll(intel_crtc, crtc_state); | |
1452 | if (pll == NULL) { | |
1453 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
1454 | pipe_name(intel_crtc->pipe)); | |
1455 | return false; | |
1456 | } | |
1457 | ||
1458 | /* shared DPLL id 0 is DPLL A */ | |
1459 | crtc_state->ddi_pll_sel = pll->id; | |
1460 | ||
1461 | return true; | |
1462 | } | |
1463 | ||
0220ab6e DL |
1464 | /* |
1465 | * Tries to find a *shared* PLL for the CRTC and store it in | |
1466 | * intel_crtc->ddi_pll_sel. | |
1467 | * | |
1468 | * For private DPLLs, compute_config() should do the selection for us. This | |
1469 | * function should be folded into compute_config() eventually. | |
1470 | */ | |
190f68c5 ACO |
1471 | bool intel_ddi_pll_select(struct intel_crtc *intel_crtc, |
1472 | struct intel_crtc_state *crtc_state) | |
0220ab6e | 1473 | { |
82d35437 | 1474 | struct drm_device *dev = intel_crtc->base.dev; |
d0737e1d | 1475 | struct intel_encoder *intel_encoder = |
3165c074 | 1476 | intel_ddi_get_crtc_new_encoder(crtc_state); |
190f68c5 | 1477 | int clock = crtc_state->port_clock; |
0220ab6e | 1478 | |
82d35437 | 1479 | if (IS_SKYLAKE(dev)) |
190f68c5 ACO |
1480 | return skl_ddi_pll_select(intel_crtc, crtc_state, |
1481 | intel_encoder, clock); | |
d683f3bc S |
1482 | else if (IS_BROXTON(dev)) |
1483 | return bxt_ddi_pll_select(intel_crtc, crtc_state, | |
1484 | intel_encoder, clock); | |
82d35437 | 1485 | else |
190f68c5 ACO |
1486 | return hsw_ddi_pll_select(intel_crtc, crtc_state, |
1487 | intel_encoder, clock); | |
0220ab6e DL |
1488 | } |
1489 | ||
dae84799 PZ |
1490 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) |
1491 | { | |
1492 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1493 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1494 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
6e3c9717 | 1495 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
dae84799 PZ |
1496 | int type = intel_encoder->type; |
1497 | uint32_t temp; | |
1498 | ||
0e32b39c | 1499 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) { |
c9809791 | 1500 | temp = TRANS_MSA_SYNC_CLK; |
6e3c9717 | 1501 | switch (intel_crtc->config->pipe_bpp) { |
dae84799 | 1502 | case 18: |
c9809791 | 1503 | temp |= TRANS_MSA_6_BPC; |
dae84799 PZ |
1504 | break; |
1505 | case 24: | |
c9809791 | 1506 | temp |= TRANS_MSA_8_BPC; |
dae84799 PZ |
1507 | break; |
1508 | case 30: | |
c9809791 | 1509 | temp |= TRANS_MSA_10_BPC; |
dae84799 PZ |
1510 | break; |
1511 | case 36: | |
c9809791 | 1512 | temp |= TRANS_MSA_12_BPC; |
dae84799 PZ |
1513 | break; |
1514 | default: | |
4e53c2e0 | 1515 | BUG(); |
dae84799 | 1516 | } |
c9809791 | 1517 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
dae84799 PZ |
1518 | } |
1519 | } | |
1520 | ||
0e32b39c DA |
1521 | void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state) |
1522 | { | |
1523 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1524 | struct drm_device *dev = crtc->dev; | |
1525 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6e3c9717 | 1526 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
0e32b39c DA |
1527 | uint32_t temp; |
1528 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1529 | if (state == true) | |
1530 | temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC; | |
1531 | else | |
1532 | temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; | |
1533 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); | |
1534 | } | |
1535 | ||
8228c251 | 1536 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) |
8d9ddbcb PZ |
1537 | { |
1538 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1539 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
7739c33b | 1540 | struct drm_encoder *encoder = &intel_encoder->base; |
c7670b10 PZ |
1541 | struct drm_device *dev = crtc->dev; |
1542 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8d9ddbcb | 1543 | enum pipe pipe = intel_crtc->pipe; |
6e3c9717 | 1544 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
174edf1f | 1545 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
7739c33b | 1546 | int type = intel_encoder->type; |
8d9ddbcb PZ |
1547 | uint32_t temp; |
1548 | ||
ad80a810 PZ |
1549 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
1550 | temp = TRANS_DDI_FUNC_ENABLE; | |
174edf1f | 1551 | temp |= TRANS_DDI_SELECT_PORT(port); |
dfcef252 | 1552 | |
6e3c9717 | 1553 | switch (intel_crtc->config->pipe_bpp) { |
dfcef252 | 1554 | case 18: |
ad80a810 | 1555 | temp |= TRANS_DDI_BPC_6; |
dfcef252 PZ |
1556 | break; |
1557 | case 24: | |
ad80a810 | 1558 | temp |= TRANS_DDI_BPC_8; |
dfcef252 PZ |
1559 | break; |
1560 | case 30: | |
ad80a810 | 1561 | temp |= TRANS_DDI_BPC_10; |
dfcef252 PZ |
1562 | break; |
1563 | case 36: | |
ad80a810 | 1564 | temp |= TRANS_DDI_BPC_12; |
dfcef252 PZ |
1565 | break; |
1566 | default: | |
4e53c2e0 | 1567 | BUG(); |
dfcef252 | 1568 | } |
72662e10 | 1569 | |
6e3c9717 | 1570 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) |
ad80a810 | 1571 | temp |= TRANS_DDI_PVSYNC; |
6e3c9717 | 1572 | if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) |
ad80a810 | 1573 | temp |= TRANS_DDI_PHSYNC; |
f63eb7c4 | 1574 | |
e6f0bfc4 PZ |
1575 | if (cpu_transcoder == TRANSCODER_EDP) { |
1576 | switch (pipe) { | |
1577 | case PIPE_A: | |
c7670b10 PZ |
1578 | /* On Haswell, can only use the always-on power well for |
1579 | * eDP when not using the panel fitter, and when not | |
1580 | * using motion blur mitigation (which we don't | |
1581 | * support). */ | |
fabf6e51 | 1582 | if (IS_HASWELL(dev) && |
6e3c9717 ACO |
1583 | (intel_crtc->config->pch_pfit.enabled || |
1584 | intel_crtc->config->pch_pfit.force_thru)) | |
d6dd9eb1 DV |
1585 | temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; |
1586 | else | |
1587 | temp |= TRANS_DDI_EDP_INPUT_A_ON; | |
e6f0bfc4 PZ |
1588 | break; |
1589 | case PIPE_B: | |
1590 | temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; | |
1591 | break; | |
1592 | case PIPE_C: | |
1593 | temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; | |
1594 | break; | |
1595 | default: | |
1596 | BUG(); | |
1597 | break; | |
1598 | } | |
1599 | } | |
1600 | ||
7739c33b | 1601 | if (type == INTEL_OUTPUT_HDMI) { |
6e3c9717 | 1602 | if (intel_crtc->config->has_hdmi_sink) |
ad80a810 | 1603 | temp |= TRANS_DDI_MODE_SELECT_HDMI; |
8d9ddbcb | 1604 | else |
ad80a810 | 1605 | temp |= TRANS_DDI_MODE_SELECT_DVI; |
8d9ddbcb | 1606 | |
7739c33b | 1607 | } else if (type == INTEL_OUTPUT_ANALOG) { |
ad80a810 | 1608 | temp |= TRANS_DDI_MODE_SELECT_FDI; |
6e3c9717 | 1609 | temp |= (intel_crtc->config->fdi_lanes - 1) << 1; |
7739c33b PZ |
1610 | |
1611 | } else if (type == INTEL_OUTPUT_DISPLAYPORT || | |
1612 | type == INTEL_OUTPUT_EDP) { | |
1613 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1614 | ||
0e32b39c DA |
1615 | if (intel_dp->is_mst) { |
1616 | temp |= TRANS_DDI_MODE_SELECT_DP_MST; | |
1617 | } else | |
1618 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; | |
1619 | ||
1620 | temp |= DDI_PORT_WIDTH(intel_dp->lane_count); | |
1621 | } else if (type == INTEL_OUTPUT_DP_MST) { | |
1622 | struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp; | |
1623 | ||
1624 | if (intel_dp->is_mst) { | |
1625 | temp |= TRANS_DDI_MODE_SELECT_DP_MST; | |
1626 | } else | |
1627 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; | |
7739c33b | 1628 | |
17aa6be9 | 1629 | temp |= DDI_PORT_WIDTH(intel_dp->lane_count); |
8d9ddbcb | 1630 | } else { |
84f44ce7 VS |
1631 | WARN(1, "Invalid encoder type %d for pipe %c\n", |
1632 | intel_encoder->type, pipe_name(pipe)); | |
8d9ddbcb PZ |
1633 | } |
1634 | ||
ad80a810 | 1635 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
8d9ddbcb | 1636 | } |
72662e10 | 1637 | |
ad80a810 PZ |
1638 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
1639 | enum transcoder cpu_transcoder) | |
8d9ddbcb | 1640 | { |
ad80a810 | 1641 | uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
8d9ddbcb PZ |
1642 | uint32_t val = I915_READ(reg); |
1643 | ||
0e32b39c | 1644 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC); |
ad80a810 | 1645 | val |= TRANS_DDI_PORT_NONE; |
8d9ddbcb | 1646 | I915_WRITE(reg, val); |
72662e10 ED |
1647 | } |
1648 | ||
bcbc889b PZ |
1649 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) |
1650 | { | |
1651 | struct drm_device *dev = intel_connector->base.dev; | |
1652 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1653 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
1654 | int type = intel_connector->base.connector_type; | |
1655 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
1656 | enum pipe pipe = 0; | |
1657 | enum transcoder cpu_transcoder; | |
882244a3 | 1658 | enum intel_display_power_domain power_domain; |
bcbc889b PZ |
1659 | uint32_t tmp; |
1660 | ||
882244a3 | 1661 | power_domain = intel_display_port_power_domain(intel_encoder); |
f458ebbc | 1662 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
882244a3 PZ |
1663 | return false; |
1664 | ||
bcbc889b PZ |
1665 | if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) |
1666 | return false; | |
1667 | ||
1668 | if (port == PORT_A) | |
1669 | cpu_transcoder = TRANSCODER_EDP; | |
1670 | else | |
1a240d4d | 1671 | cpu_transcoder = (enum transcoder) pipe; |
bcbc889b PZ |
1672 | |
1673 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1674 | ||
1675 | switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { | |
1676 | case TRANS_DDI_MODE_SELECT_HDMI: | |
1677 | case TRANS_DDI_MODE_SELECT_DVI: | |
1678 | return (type == DRM_MODE_CONNECTOR_HDMIA); | |
1679 | ||
1680 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
1681 | if (type == DRM_MODE_CONNECTOR_eDP) | |
1682 | return true; | |
bcbc889b | 1683 | return (type == DRM_MODE_CONNECTOR_DisplayPort); |
0e32b39c DA |
1684 | case TRANS_DDI_MODE_SELECT_DP_MST: |
1685 | /* if the transcoder is in MST state then | |
1686 | * connector isn't connected */ | |
1687 | return false; | |
bcbc889b PZ |
1688 | |
1689 | case TRANS_DDI_MODE_SELECT_FDI: | |
1690 | return (type == DRM_MODE_CONNECTOR_VGA); | |
1691 | ||
1692 | default: | |
1693 | return false; | |
1694 | } | |
1695 | } | |
1696 | ||
85234cdc DV |
1697 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
1698 | enum pipe *pipe) | |
1699 | { | |
1700 | struct drm_device *dev = encoder->base.dev; | |
1701 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fe43d3f5 | 1702 | enum port port = intel_ddi_get_encoder_port(encoder); |
6d129bea | 1703 | enum intel_display_power_domain power_domain; |
85234cdc DV |
1704 | u32 tmp; |
1705 | int i; | |
1706 | ||
6d129bea | 1707 | power_domain = intel_display_port_power_domain(encoder); |
f458ebbc | 1708 | if (!intel_display_power_is_enabled(dev_priv, power_domain)) |
6d129bea ID |
1709 | return false; |
1710 | ||
fe43d3f5 | 1711 | tmp = I915_READ(DDI_BUF_CTL(port)); |
85234cdc DV |
1712 | |
1713 | if (!(tmp & DDI_BUF_CTL_ENABLE)) | |
1714 | return false; | |
1715 | ||
ad80a810 PZ |
1716 | if (port == PORT_A) { |
1717 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
85234cdc | 1718 | |
ad80a810 PZ |
1719 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
1720 | case TRANS_DDI_EDP_INPUT_A_ON: | |
1721 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
1722 | *pipe = PIPE_A; | |
1723 | break; | |
1724 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
1725 | *pipe = PIPE_B; | |
1726 | break; | |
1727 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
1728 | *pipe = PIPE_C; | |
1729 | break; | |
1730 | } | |
1731 | ||
1732 | return true; | |
1733 | } else { | |
1734 | for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { | |
1735 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); | |
1736 | ||
1737 | if ((tmp & TRANS_DDI_PORT_MASK) | |
1738 | == TRANS_DDI_SELECT_PORT(port)) { | |
0e32b39c DA |
1739 | if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST) |
1740 | return false; | |
1741 | ||
ad80a810 PZ |
1742 | *pipe = i; |
1743 | return true; | |
1744 | } | |
85234cdc DV |
1745 | } |
1746 | } | |
1747 | ||
84f44ce7 | 1748 | DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); |
85234cdc | 1749 | |
22f9fe50 | 1750 | return false; |
85234cdc DV |
1751 | } |
1752 | ||
fc914639 PZ |
1753 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) |
1754 | { | |
1755 | struct drm_crtc *crtc = &intel_crtc->base; | |
1756 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1757 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
1758 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
6e3c9717 | 1759 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
fc914639 | 1760 | |
bb523fc0 PZ |
1761 | if (cpu_transcoder != TRANSCODER_EDP) |
1762 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1763 | TRANS_CLK_SEL_PORT(port)); | |
fc914639 PZ |
1764 | } |
1765 | ||
1766 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) | |
1767 | { | |
1768 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; | |
6e3c9717 | 1769 | enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; |
fc914639 | 1770 | |
bb523fc0 PZ |
1771 | if (cpu_transcoder != TRANSCODER_EDP) |
1772 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1773 | TRANS_CLK_SEL_DISABLED); | |
fc914639 PZ |
1774 | } |
1775 | ||
96fb9f9b VK |
1776 | void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level, |
1777 | enum port port, int type) | |
1778 | { | |
1779 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1780 | const struct bxt_ddi_buf_trans *ddi_translations; | |
1781 | u32 n_entries, i; | |
1782 | uint32_t val; | |
1783 | ||
1784 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { | |
1785 | n_entries = ARRAY_SIZE(bxt_ddi_translations_dp); | |
1786 | ddi_translations = bxt_ddi_translations_dp; | |
1787 | } else if (type == INTEL_OUTPUT_HDMI) { | |
1788 | n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi); | |
1789 | ddi_translations = bxt_ddi_translations_hdmi; | |
1790 | } else { | |
1791 | DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n", | |
1792 | type); | |
1793 | return; | |
1794 | } | |
1795 | ||
1796 | /* Check if default value has to be used */ | |
1797 | if (level >= n_entries || | |
1798 | (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) { | |
1799 | for (i = 0; i < n_entries; i++) { | |
1800 | if (ddi_translations[i].default_index) { | |
1801 | level = i; | |
1802 | break; | |
1803 | } | |
1804 | } | |
1805 | } | |
1806 | ||
1807 | /* | |
1808 | * While we write to the group register to program all lanes at once we | |
1809 | * can read only lane registers and we pick lanes 0/1 for that. | |
1810 | */ | |
1811 | val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); | |
1812 | val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); | |
1813 | I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); | |
1814 | ||
1815 | val = I915_READ(BXT_PORT_TX_DW2_LN0(port)); | |
1816 | val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); | |
1817 | val |= ddi_translations[level].margin << MARGIN_000_SHIFT | | |
1818 | ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT; | |
1819 | I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val); | |
1820 | ||
1821 | val = I915_READ(BXT_PORT_TX_DW3_LN0(port)); | |
1822 | val &= ~UNIQE_TRANGE_EN_METHOD; | |
1823 | if (ddi_translations[level].enable) | |
1824 | val |= UNIQE_TRANGE_EN_METHOD; | |
1825 | I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val); | |
1826 | ||
1827 | val = I915_READ(BXT_PORT_TX_DW4_LN0(port)); | |
1828 | val &= ~DE_EMPHASIS; | |
1829 | val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT; | |
1830 | I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val); | |
1831 | ||
1832 | val = I915_READ(BXT_PORT_PCS_DW10_LN01(port)); | |
1833 | val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT; | |
1834 | I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val); | |
1835 | } | |
1836 | ||
00c09d70 | 1837 | static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) |
6441ab5f | 1838 | { |
c19b0669 | 1839 | struct drm_encoder *encoder = &intel_encoder->base; |
efa80add S |
1840 | struct drm_device *dev = encoder->dev; |
1841 | struct drm_i915_private *dev_priv = dev->dev_private; | |
30cf6db8 | 1842 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
6441ab5f | 1843 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
82a4d9c0 | 1844 | int type = intel_encoder->type; |
96fb9f9b | 1845 | int hdmi_level; |
6441ab5f | 1846 | |
82a4d9c0 PZ |
1847 | if (type == INTEL_OUTPUT_EDP) { |
1848 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
4be73780 | 1849 | intel_edp_panel_on(intel_dp); |
82a4d9c0 | 1850 | } |
6441ab5f | 1851 | |
efa80add | 1852 | if (IS_SKYLAKE(dev)) { |
6e3c9717 | 1853 | uint32_t dpll = crtc->config->ddi_pll_sel; |
efa80add S |
1854 | uint32_t val; |
1855 | ||
5416d871 DL |
1856 | /* |
1857 | * DPLL0 is used for eDP and is the only "private" DPLL (as | |
1858 | * opposed to shared) on SKL | |
1859 | */ | |
1860 | if (type == INTEL_OUTPUT_EDP) { | |
1861 | WARN_ON(dpll != SKL_DPLL0); | |
1862 | ||
1863 | val = I915_READ(DPLL_CTRL1); | |
1864 | ||
1865 | val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | | |
1866 | DPLL_CTRL1_SSC(dpll) | | |
71cd8423 | 1867 | DPLL_CTRL1_LINK_RATE_MASK(dpll)); |
6e3c9717 | 1868 | val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6); |
5416d871 DL |
1869 | |
1870 | I915_WRITE(DPLL_CTRL1, val); | |
1871 | POSTING_READ(DPLL_CTRL1); | |
1872 | } | |
1873 | ||
1874 | /* DDI -> PLL mapping */ | |
efa80add S |
1875 | val = I915_READ(DPLL_CTRL2); |
1876 | ||
1877 | val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) | | |
1878 | DPLL_CTRL2_DDI_CLK_SEL_MASK(port)); | |
1879 | val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) | | |
1880 | DPLL_CTRL2_DDI_SEL_OVERRIDE(port)); | |
1881 | ||
1882 | I915_WRITE(DPLL_CTRL2, val); | |
5416d871 | 1883 | |
1ab23380 | 1884 | } else if (INTEL_INFO(dev)->gen < 9) { |
6e3c9717 ACO |
1885 | WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE); |
1886 | I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel); | |
efa80add | 1887 | } |
c19b0669 | 1888 | |
82a4d9c0 | 1889 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
c19b0669 | 1890 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
30cf6db8 | 1891 | |
44905a27 | 1892 | intel_ddi_init_dp_buf_reg(intel_encoder); |
c19b0669 PZ |
1893 | |
1894 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
1895 | intel_dp_start_link_train(intel_dp); | |
1896 | intel_dp_complete_link_train(intel_dp); | |
23f08d83 | 1897 | if (port != PORT_A || INTEL_INFO(dev)->gen >= 9) |
3ab9c637 | 1898 | intel_dp_stop_link_train(intel_dp); |
30cf6db8 DV |
1899 | } else if (type == INTEL_OUTPUT_HDMI) { |
1900 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
1901 | ||
96fb9f9b VK |
1902 | if (IS_BROXTON(dev)) { |
1903 | hdmi_level = dev_priv->vbt. | |
1904 | ddi_port_info[port].hdmi_level_shift; | |
1905 | bxt_ddi_vswing_sequence(dev, hdmi_level, port, | |
1906 | INTEL_OUTPUT_HDMI); | |
1907 | } | |
30cf6db8 | 1908 | intel_hdmi->set_infoframes(encoder, |
6e3c9717 ACO |
1909 | crtc->config->has_hdmi_sink, |
1910 | &crtc->config->base.adjusted_mode); | |
c19b0669 | 1911 | } |
6441ab5f PZ |
1912 | } |
1913 | ||
00c09d70 | 1914 | static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) |
6441ab5f PZ |
1915 | { |
1916 | struct drm_encoder *encoder = &intel_encoder->base; | |
efa80add S |
1917 | struct drm_device *dev = encoder->dev; |
1918 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6441ab5f | 1919 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
82a4d9c0 | 1920 | int type = intel_encoder->type; |
2886e93f | 1921 | uint32_t val; |
a836bdf9 | 1922 | bool wait = false; |
2886e93f PZ |
1923 | |
1924 | val = I915_READ(DDI_BUF_CTL(port)); | |
1925 | if (val & DDI_BUF_CTL_ENABLE) { | |
1926 | val &= ~DDI_BUF_CTL_ENABLE; | |
1927 | I915_WRITE(DDI_BUF_CTL(port), val); | |
a836bdf9 | 1928 | wait = true; |
2886e93f | 1929 | } |
6441ab5f | 1930 | |
a836bdf9 PZ |
1931 | val = I915_READ(DP_TP_CTL(port)); |
1932 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1933 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1934 | I915_WRITE(DP_TP_CTL(port), val); | |
1935 | ||
1936 | if (wait) | |
1937 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1938 | ||
76bb80ed | 1939 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
82a4d9c0 | 1940 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
76bb80ed | 1941 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
24f3e092 | 1942 | intel_edp_panel_vdd_on(intel_dp); |
4be73780 | 1943 | intel_edp_panel_off(intel_dp); |
82a4d9c0 PZ |
1944 | } |
1945 | ||
efa80add S |
1946 | if (IS_SKYLAKE(dev)) |
1947 | I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) | | |
1948 | DPLL_CTRL2_DDI_CLK_OFF(port))); | |
1ab23380 | 1949 | else if (INTEL_INFO(dev)->gen < 9) |
efa80add | 1950 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); |
6441ab5f PZ |
1951 | } |
1952 | ||
00c09d70 | 1953 | static void intel_enable_ddi(struct intel_encoder *intel_encoder) |
72662e10 | 1954 | { |
6547fef8 | 1955 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1956 | struct drm_crtc *crtc = encoder->crtc; |
1957 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6547fef8 | 1958 | struct drm_device *dev = encoder->dev; |
72662e10 | 1959 | struct drm_i915_private *dev_priv = dev->dev_private; |
6547fef8 PZ |
1960 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
1961 | int type = intel_encoder->type; | |
72662e10 | 1962 | |
6547fef8 | 1963 | if (type == INTEL_OUTPUT_HDMI) { |
876a8cdf DL |
1964 | struct intel_digital_port *intel_dig_port = |
1965 | enc_to_dig_port(encoder); | |
1966 | ||
6547fef8 PZ |
1967 | /* In HDMI/DVI mode, the port width, and swing/emphasis values |
1968 | * are ignored so nothing special needs to be done besides | |
1969 | * enabling the port. | |
1970 | */ | |
876a8cdf | 1971 | I915_WRITE(DDI_BUF_CTL(port), |
bcf53de4 SM |
1972 | intel_dig_port->saved_port_bits | |
1973 | DDI_BUF_CTL_ENABLE); | |
d6c50ff8 PZ |
1974 | } else if (type == INTEL_OUTPUT_EDP) { |
1975 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1976 | ||
23f08d83 | 1977 | if (port == PORT_A && INTEL_INFO(dev)->gen < 9) |
3ab9c637 ID |
1978 | intel_dp_stop_link_train(intel_dp); |
1979 | ||
4be73780 | 1980 | intel_edp_backlight_on(intel_dp); |
0bc12bcb | 1981 | intel_psr_enable(intel_dp); |
c395578e | 1982 | intel_edp_drrs_enable(intel_dp); |
6547fef8 | 1983 | } |
7b9f35a6 | 1984 | |
6e3c9717 | 1985 | if (intel_crtc->config->has_audio) { |
d45a0bf5 | 1986 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); |
69bfe1a9 | 1987 | intel_audio_codec_enable(intel_encoder); |
7b9f35a6 | 1988 | } |
5ab432ef DV |
1989 | } |
1990 | ||
00c09d70 | 1991 | static void intel_disable_ddi(struct intel_encoder *intel_encoder) |
5ab432ef | 1992 | { |
d6c50ff8 | 1993 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1994 | struct drm_crtc *crtc = encoder->crtc; |
1995 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
d6c50ff8 | 1996 | int type = intel_encoder->type; |
7b9f35a6 WX |
1997 | struct drm_device *dev = encoder->dev; |
1998 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d6c50ff8 | 1999 | |
6e3c9717 | 2000 | if (intel_crtc->config->has_audio) { |
69bfe1a9 | 2001 | intel_audio_codec_disable(intel_encoder); |
d45a0bf5 PZ |
2002 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); |
2003 | } | |
2831d842 | 2004 | |
d6c50ff8 PZ |
2005 | if (type == INTEL_OUTPUT_EDP) { |
2006 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
2007 | ||
c395578e | 2008 | intel_edp_drrs_disable(intel_dp); |
0bc12bcb | 2009 | intel_psr_disable(intel_dp); |
4be73780 | 2010 | intel_edp_backlight_off(intel_dp); |
d6c50ff8 | 2011 | } |
72662e10 | 2012 | } |
79f689aa | 2013 | |
e0b01be4 DV |
2014 | static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv, |
2015 | struct intel_shared_dpll *pll) | |
2016 | { | |
3e369b76 | 2017 | I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll); |
e0b01be4 DV |
2018 | POSTING_READ(WRPLL_CTL(pll->id)); |
2019 | udelay(20); | |
2020 | } | |
2021 | ||
12030431 DV |
2022 | static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv, |
2023 | struct intel_shared_dpll *pll) | |
2024 | { | |
2025 | uint32_t val; | |
2026 | ||
2027 | val = I915_READ(WRPLL_CTL(pll->id)); | |
12030431 DV |
2028 | I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE); |
2029 | POSTING_READ(WRPLL_CTL(pll->id)); | |
2030 | } | |
2031 | ||
d452c5b6 DV |
2032 | static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, |
2033 | struct intel_shared_dpll *pll, | |
2034 | struct intel_dpll_hw_state *hw_state) | |
2035 | { | |
2036 | uint32_t val; | |
2037 | ||
f458ebbc | 2038 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
d452c5b6 DV |
2039 | return false; |
2040 | ||
2041 | val = I915_READ(WRPLL_CTL(pll->id)); | |
2042 | hw_state->wrpll = val; | |
2043 | ||
2044 | return val & WRPLL_PLL_ENABLE; | |
2045 | } | |
2046 | ||
ca1381b5 | 2047 | static const char * const hsw_ddi_pll_names[] = { |
9cd86933 DV |
2048 | "WRPLL 1", |
2049 | "WRPLL 2", | |
2050 | }; | |
2051 | ||
143b307c | 2052 | static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv) |
79f689aa | 2053 | { |
9cd86933 DV |
2054 | int i; |
2055 | ||
716c2e55 | 2056 | dev_priv->num_shared_dpll = 2; |
9cd86933 | 2057 | |
716c2e55 | 2058 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
9cd86933 DV |
2059 | dev_priv->shared_dplls[i].id = i; |
2060 | dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; | |
12030431 | 2061 | dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable; |
e0b01be4 | 2062 | dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable; |
d452c5b6 DV |
2063 | dev_priv->shared_dplls[i].get_hw_state = |
2064 | hsw_ddi_pll_get_hw_state; | |
9cd86933 | 2065 | } |
143b307c DL |
2066 | } |
2067 | ||
d1a2dc78 S |
2068 | static const char * const skl_ddi_pll_names[] = { |
2069 | "DPLL 1", | |
2070 | "DPLL 2", | |
2071 | "DPLL 3", | |
2072 | }; | |
2073 | ||
2074 | struct skl_dpll_regs { | |
2075 | u32 ctl, cfgcr1, cfgcr2; | |
2076 | }; | |
2077 | ||
2078 | /* this array is indexed by the *shared* pll id */ | |
2079 | static const struct skl_dpll_regs skl_dpll_regs[3] = { | |
2080 | { | |
2081 | /* DPLL 1 */ | |
2082 | .ctl = LCPLL2_CTL, | |
2083 | .cfgcr1 = DPLL1_CFGCR1, | |
2084 | .cfgcr2 = DPLL1_CFGCR2, | |
2085 | }, | |
2086 | { | |
2087 | /* DPLL 2 */ | |
2088 | .ctl = WRPLL_CTL1, | |
2089 | .cfgcr1 = DPLL2_CFGCR1, | |
2090 | .cfgcr2 = DPLL2_CFGCR2, | |
2091 | }, | |
2092 | { | |
2093 | /* DPLL 3 */ | |
2094 | .ctl = WRPLL_CTL2, | |
2095 | .cfgcr1 = DPLL3_CFGCR1, | |
2096 | .cfgcr2 = DPLL3_CFGCR2, | |
2097 | }, | |
2098 | }; | |
2099 | ||
2100 | static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv, | |
2101 | struct intel_shared_dpll *pll) | |
2102 | { | |
2103 | uint32_t val; | |
2104 | unsigned int dpll; | |
2105 | const struct skl_dpll_regs *regs = skl_dpll_regs; | |
2106 | ||
2107 | /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ | |
2108 | dpll = pll->id + 1; | |
2109 | ||
2110 | val = I915_READ(DPLL_CTRL1); | |
2111 | ||
2112 | val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) | | |
71cd8423 | 2113 | DPLL_CTRL1_LINK_RATE_MASK(dpll)); |
d1a2dc78 S |
2114 | val |= pll->config.hw_state.ctrl1 << (dpll * 6); |
2115 | ||
2116 | I915_WRITE(DPLL_CTRL1, val); | |
2117 | POSTING_READ(DPLL_CTRL1); | |
2118 | ||
2119 | I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1); | |
2120 | I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2); | |
2121 | POSTING_READ(regs[pll->id].cfgcr1); | |
2122 | POSTING_READ(regs[pll->id].cfgcr2); | |
2123 | ||
2124 | /* the enable bit is always bit 31 */ | |
2125 | I915_WRITE(regs[pll->id].ctl, | |
2126 | I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE); | |
2127 | ||
2128 | if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5)) | |
2129 | DRM_ERROR("DPLL %d not locked\n", dpll); | |
2130 | } | |
2131 | ||
2132 | static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv, | |
2133 | struct intel_shared_dpll *pll) | |
2134 | { | |
2135 | const struct skl_dpll_regs *regs = skl_dpll_regs; | |
2136 | ||
2137 | /* the enable bit is always bit 31 */ | |
2138 | I915_WRITE(regs[pll->id].ctl, | |
2139 | I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE); | |
2140 | POSTING_READ(regs[pll->id].ctl); | |
2141 | } | |
2142 | ||
2143 | static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, | |
2144 | struct intel_shared_dpll *pll, | |
2145 | struct intel_dpll_hw_state *hw_state) | |
2146 | { | |
2147 | uint32_t val; | |
2148 | unsigned int dpll; | |
2149 | const struct skl_dpll_regs *regs = skl_dpll_regs; | |
2150 | ||
2151 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) | |
2152 | return false; | |
2153 | ||
2154 | /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */ | |
2155 | dpll = pll->id + 1; | |
2156 | ||
2157 | val = I915_READ(regs[pll->id].ctl); | |
2158 | if (!(val & LCPLL_PLL_ENABLE)) | |
2159 | return false; | |
2160 | ||
2161 | val = I915_READ(DPLL_CTRL1); | |
2162 | hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f; | |
2163 | ||
2164 | /* avoid reading back stale values if HDMI mode is not enabled */ | |
2165 | if (val & DPLL_CTRL1_HDMI_MODE(dpll)) { | |
2166 | hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1); | |
2167 | hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2); | |
2168 | } | |
2169 | ||
2170 | return true; | |
2171 | } | |
2172 | ||
2173 | static void skl_shared_dplls_init(struct drm_i915_private *dev_priv) | |
2174 | { | |
2175 | int i; | |
2176 | ||
2177 | dev_priv->num_shared_dpll = 3; | |
2178 | ||
2179 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
2180 | dev_priv->shared_dplls[i].id = i; | |
2181 | dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i]; | |
2182 | dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable; | |
2183 | dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable; | |
2184 | dev_priv->shared_dplls[i].get_hw_state = | |
2185 | skl_ddi_pll_get_hw_state; | |
2186 | } | |
2187 | } | |
2188 | ||
5c6706e5 VK |
2189 | static void broxton_phy_init(struct drm_i915_private *dev_priv, |
2190 | enum dpio_phy phy) | |
2191 | { | |
2192 | enum port port; | |
2193 | uint32_t val; | |
2194 | ||
2195 | val = I915_READ(BXT_P_CR_GT_DISP_PWRON); | |
2196 | val |= GT_DISPLAY_POWER_ON(phy); | |
2197 | I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); | |
2198 | ||
2199 | /* Considering 10ms timeout until BSpec is updated */ | |
2200 | if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10)) | |
2201 | DRM_ERROR("timeout during PHY%d power on\n", phy); | |
2202 | ||
2203 | for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A); | |
2204 | port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) { | |
2205 | int lane; | |
2206 | ||
2207 | for (lane = 0; lane < 4; lane++) { | |
2208 | val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane)); | |
2209 | /* | |
2210 | * Note that on CHV this flag is called UPAR, but has | |
2211 | * the same function. | |
2212 | */ | |
2213 | val &= ~LATENCY_OPTIM; | |
2214 | if (lane != 1) | |
2215 | val |= LATENCY_OPTIM; | |
2216 | ||
2217 | I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val); | |
2218 | } | |
2219 | } | |
2220 | ||
2221 | /* Program PLL Rcomp code offset */ | |
2222 | val = I915_READ(BXT_PORT_CL1CM_DW9(phy)); | |
2223 | val &= ~IREF0RC_OFFSET_MASK; | |
2224 | val |= 0xE4 << IREF0RC_OFFSET_SHIFT; | |
2225 | I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val); | |
2226 | ||
2227 | val = I915_READ(BXT_PORT_CL1CM_DW10(phy)); | |
2228 | val &= ~IREF1RC_OFFSET_MASK; | |
2229 | val |= 0xE4 << IREF1RC_OFFSET_SHIFT; | |
2230 | I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val); | |
2231 | ||
2232 | /* Program power gating */ | |
2233 | val = I915_READ(BXT_PORT_CL1CM_DW28(phy)); | |
2234 | val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | | |
2235 | SUS_CLK_CONFIG; | |
2236 | I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val); | |
2237 | ||
2238 | if (phy == DPIO_PHY0) { | |
2239 | val = I915_READ(BXT_PORT_CL2CM_DW6_BC); | |
2240 | val |= DW6_OLDO_DYN_PWR_DOWN_EN; | |
2241 | I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val); | |
2242 | } | |
2243 | ||
2244 | val = I915_READ(BXT_PORT_CL1CM_DW30(phy)); | |
2245 | val &= ~OCL2_LDOFUSE_PWR_DIS; | |
2246 | /* | |
2247 | * On PHY1 disable power on the second channel, since no port is | |
2248 | * connected there. On PHY0 both channels have a port, so leave it | |
2249 | * enabled. | |
2250 | * TODO: port C is only connected on BXT-P, so on BXT0/1 we should | |
2251 | * power down the second channel on PHY0 as well. | |
2252 | */ | |
2253 | if (phy == DPIO_PHY1) | |
2254 | val |= OCL2_LDOFUSE_PWR_DIS; | |
2255 | I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val); | |
2256 | ||
2257 | if (phy == DPIO_PHY0) { | |
2258 | uint32_t grc_code; | |
2259 | /* | |
2260 | * PHY0 isn't connected to an RCOMP resistor so copy over | |
2261 | * the corresponding calibrated value from PHY1, and disable | |
2262 | * the automatic calibration on PHY0. | |
2263 | */ | |
2264 | if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE, | |
2265 | 10)) | |
2266 | DRM_ERROR("timeout waiting for PHY1 GRC\n"); | |
2267 | ||
2268 | val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1)); | |
2269 | val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT; | |
2270 | grc_code = val << GRC_CODE_FAST_SHIFT | | |
2271 | val << GRC_CODE_SLOW_SHIFT | | |
2272 | val; | |
2273 | I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code); | |
2274 | ||
2275 | val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0)); | |
2276 | val |= GRC_DIS | GRC_RDY_OVRD; | |
2277 | I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val); | |
2278 | } | |
2279 | ||
2280 | val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); | |
2281 | val |= COMMON_RESET_DIS; | |
2282 | I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); | |
2283 | } | |
2284 | ||
2285 | void broxton_ddi_phy_init(struct drm_device *dev) | |
2286 | { | |
2287 | /* Enable PHY1 first since it provides Rcomp for PHY0 */ | |
2288 | broxton_phy_init(dev->dev_private, DPIO_PHY1); | |
2289 | broxton_phy_init(dev->dev_private, DPIO_PHY0); | |
2290 | } | |
2291 | ||
2292 | static void broxton_phy_uninit(struct drm_i915_private *dev_priv, | |
2293 | enum dpio_phy phy) | |
2294 | { | |
2295 | uint32_t val; | |
2296 | ||
2297 | val = I915_READ(BXT_PHY_CTL_FAMILY(phy)); | |
2298 | val &= ~COMMON_RESET_DIS; | |
2299 | I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val); | |
2300 | } | |
2301 | ||
2302 | void broxton_ddi_phy_uninit(struct drm_device *dev) | |
2303 | { | |
2304 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2305 | ||
2306 | broxton_phy_uninit(dev_priv, DPIO_PHY1); | |
2307 | broxton_phy_uninit(dev_priv, DPIO_PHY0); | |
2308 | ||
2309 | /* FIXME: do this in broxton_phy_uninit per phy */ | |
2310 | I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0); | |
2311 | } | |
2312 | ||
dfb82408 S |
2313 | static const char * const bxt_ddi_pll_names[] = { |
2314 | "PORT PLL A", | |
2315 | "PORT PLL B", | |
2316 | "PORT PLL C", | |
2317 | }; | |
2318 | ||
2319 | static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv, | |
2320 | struct intel_shared_dpll *pll) | |
2321 | { | |
2322 | uint32_t temp; | |
2323 | enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ | |
2324 | ||
2325 | temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); | |
2326 | temp &= ~PORT_PLL_REF_SEL; | |
2327 | /* Non-SSC reference */ | |
2328 | I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); | |
2329 | ||
2330 | /* Disable 10 bit clock */ | |
2331 | temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); | |
2332 | temp &= ~PORT_PLL_10BIT_CLK_ENABLE; | |
2333 | I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); | |
2334 | ||
2335 | /* Write P1 & P2 */ | |
2336 | temp = I915_READ(BXT_PORT_PLL_EBB_0(port)); | |
2337 | temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK); | |
2338 | temp |= pll->config.hw_state.ebb0; | |
2339 | I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp); | |
2340 | ||
2341 | /* Write M2 integer */ | |
2342 | temp = I915_READ(BXT_PORT_PLL(port, 0)); | |
2343 | temp &= ~PORT_PLL_M2_MASK; | |
2344 | temp |= pll->config.hw_state.pll0; | |
2345 | I915_WRITE(BXT_PORT_PLL(port, 0), temp); | |
2346 | ||
2347 | /* Write N */ | |
2348 | temp = I915_READ(BXT_PORT_PLL(port, 1)); | |
2349 | temp &= ~PORT_PLL_N_MASK; | |
2350 | temp |= pll->config.hw_state.pll1; | |
2351 | I915_WRITE(BXT_PORT_PLL(port, 1), temp); | |
2352 | ||
2353 | /* Write M2 fraction */ | |
2354 | temp = I915_READ(BXT_PORT_PLL(port, 2)); | |
2355 | temp &= ~PORT_PLL_M2_FRAC_MASK; | |
2356 | temp |= pll->config.hw_state.pll2; | |
2357 | I915_WRITE(BXT_PORT_PLL(port, 2), temp); | |
2358 | ||
2359 | /* Write M2 fraction enable */ | |
2360 | temp = I915_READ(BXT_PORT_PLL(port, 3)); | |
2361 | temp &= ~PORT_PLL_M2_FRAC_ENABLE; | |
2362 | temp |= pll->config.hw_state.pll3; | |
2363 | I915_WRITE(BXT_PORT_PLL(port, 3), temp); | |
2364 | ||
2365 | /* Write coeff */ | |
2366 | temp = I915_READ(BXT_PORT_PLL(port, 6)); | |
2367 | temp &= ~PORT_PLL_PROP_COEFF_MASK; | |
2368 | temp &= ~PORT_PLL_INT_COEFF_MASK; | |
2369 | temp &= ~PORT_PLL_GAIN_CTL_MASK; | |
2370 | temp |= pll->config.hw_state.pll6; | |
2371 | I915_WRITE(BXT_PORT_PLL(port, 6), temp); | |
2372 | ||
2373 | /* Write calibration val */ | |
2374 | temp = I915_READ(BXT_PORT_PLL(port, 8)); | |
2375 | temp &= ~PORT_PLL_TARGET_CNT_MASK; | |
2376 | temp |= pll->config.hw_state.pll8; | |
2377 | I915_WRITE(BXT_PORT_PLL(port, 8), temp); | |
2378 | ||
2379 | /* | |
2380 | * FIXME: program PORT_PLL_9/i_lockthresh according to the latest | |
2381 | * specification update. | |
2382 | */ | |
2383 | ||
2384 | /* Recalibrate with new settings */ | |
2385 | temp = I915_READ(BXT_PORT_PLL_EBB_4(port)); | |
2386 | temp |= PORT_PLL_RECALIBRATE; | |
2387 | I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); | |
2388 | /* Enable 10 bit clock */ | |
2389 | temp |= PORT_PLL_10BIT_CLK_ENABLE; | |
2390 | I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp); | |
2391 | ||
2392 | /* Enable PLL */ | |
2393 | temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); | |
2394 | temp |= PORT_PLL_ENABLE; | |
2395 | I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); | |
2396 | POSTING_READ(BXT_PORT_PLL_ENABLE(port)); | |
2397 | ||
2398 | if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) & | |
2399 | PORT_PLL_LOCK), 200)) | |
2400 | DRM_ERROR("PLL %d not locked\n", port); | |
2401 | ||
2402 | /* | |
2403 | * While we write to the group register to program all lanes at once we | |
2404 | * can read only lane registers and we pick lanes 0/1 for that. | |
2405 | */ | |
2406 | temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); | |
2407 | temp &= ~LANE_STAGGER_MASK; | |
2408 | temp &= ~LANESTAGGER_STRAP_OVRD; | |
2409 | temp |= pll->config.hw_state.pcsdw12; | |
2410 | I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp); | |
2411 | } | |
2412 | ||
2413 | static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv, | |
2414 | struct intel_shared_dpll *pll) | |
2415 | { | |
2416 | enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ | |
2417 | uint32_t temp; | |
2418 | ||
2419 | temp = I915_READ(BXT_PORT_PLL_ENABLE(port)); | |
2420 | temp &= ~PORT_PLL_ENABLE; | |
2421 | I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp); | |
2422 | POSTING_READ(BXT_PORT_PLL_ENABLE(port)); | |
2423 | } | |
2424 | ||
2425 | static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, | |
2426 | struct intel_shared_dpll *pll, | |
2427 | struct intel_dpll_hw_state *hw_state) | |
2428 | { | |
2429 | enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */ | |
2430 | uint32_t val; | |
2431 | ||
2432 | if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS)) | |
2433 | return false; | |
2434 | ||
2435 | val = I915_READ(BXT_PORT_PLL_ENABLE(port)); | |
2436 | if (!(val & PORT_PLL_ENABLE)) | |
2437 | return false; | |
2438 | ||
2439 | hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port)); | |
2440 | hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0)); | |
2441 | hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1)); | |
2442 | hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2)); | |
2443 | hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3)); | |
2444 | hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6)); | |
2445 | hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8)); | |
2446 | /* | |
2447 | * While we write to the group register to program all lanes at once we | |
2448 | * can read only lane registers. We configure all lanes the same way, so | |
2449 | * here just read out lanes 0/1 and output a note if lanes 2/3 differ. | |
2450 | */ | |
2451 | hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port)); | |
2452 | if (I915_READ(BXT_PORT_PCS_DW12_LN23(port) != hw_state->pcsdw12)) | |
2453 | DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n", | |
2454 | hw_state->pcsdw12, | |
2455 | I915_READ(BXT_PORT_PCS_DW12_LN23(port))); | |
2456 | ||
2457 | return true; | |
2458 | } | |
2459 | ||
2460 | static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv) | |
2461 | { | |
2462 | int i; | |
2463 | ||
2464 | dev_priv->num_shared_dpll = 3; | |
2465 | ||
2466 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
2467 | dev_priv->shared_dplls[i].id = i; | |
2468 | dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i]; | |
2469 | dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable; | |
2470 | dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable; | |
2471 | dev_priv->shared_dplls[i].get_hw_state = | |
2472 | bxt_ddi_pll_get_hw_state; | |
2473 | } | |
2474 | } | |
2475 | ||
143b307c DL |
2476 | void intel_ddi_pll_init(struct drm_device *dev) |
2477 | { | |
2478 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2479 | uint32_t val = I915_READ(LCPLL_CTL); | |
2480 | ||
d1a2dc78 S |
2481 | if (IS_SKYLAKE(dev)) |
2482 | skl_shared_dplls_init(dev_priv); | |
dfb82408 S |
2483 | else if (IS_BROXTON(dev)) |
2484 | bxt_shared_dplls_init(dev_priv); | |
d1a2dc78 S |
2485 | else |
2486 | hsw_shared_dplls_init(dev_priv); | |
79f689aa | 2487 | |
b2b877ff | 2488 | DRM_DEBUG_KMS("CDCLK running at %dKHz\n", |
1652d19e | 2489 | dev_priv->display.get_display_clock_speed(dev)); |
79f689aa | 2490 | |
121643c2 S |
2491 | if (IS_SKYLAKE(dev)) { |
2492 | if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) | |
2493 | DRM_ERROR("LCPLL1 is disabled\n"); | |
f8437dd1 VK |
2494 | } else if (IS_BROXTON(dev)) { |
2495 | broxton_init_cdclk(dev); | |
5c6706e5 | 2496 | broxton_ddi_phy_init(dev); |
121643c2 S |
2497 | } else { |
2498 | /* | |
2499 | * The LCPLL register should be turned on by the BIOS. For now | |
2500 | * let's just check its state and print errors in case | |
2501 | * something is wrong. Don't even try to turn it on. | |
2502 | */ | |
2503 | ||
2504 | if (val & LCPLL_CD_SOURCE_FCLK) | |
2505 | DRM_ERROR("CDCLK source is not LCPLL\n"); | |
79f689aa | 2506 | |
121643c2 S |
2507 | if (val & LCPLL_PLL_DISABLE) |
2508 | DRM_ERROR("LCPLL is disabled\n"); | |
2509 | } | |
79f689aa | 2510 | } |
c19b0669 PZ |
2511 | |
2512 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) | |
2513 | { | |
174edf1f PZ |
2514 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
2515 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
c19b0669 | 2516 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
174edf1f | 2517 | enum port port = intel_dig_port->port; |
c19b0669 | 2518 | uint32_t val; |
f3e227df | 2519 | bool wait = false; |
c19b0669 PZ |
2520 | |
2521 | if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { | |
2522 | val = I915_READ(DDI_BUF_CTL(port)); | |
2523 | if (val & DDI_BUF_CTL_ENABLE) { | |
2524 | val &= ~DDI_BUF_CTL_ENABLE; | |
2525 | I915_WRITE(DDI_BUF_CTL(port), val); | |
2526 | wait = true; | |
2527 | } | |
2528 | ||
2529 | val = I915_READ(DP_TP_CTL(port)); | |
2530 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
2531 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
2532 | I915_WRITE(DP_TP_CTL(port), val); | |
2533 | POSTING_READ(DP_TP_CTL(port)); | |
2534 | ||
2535 | if (wait) | |
2536 | intel_wait_ddi_buf_idle(dev_priv, port); | |
2537 | } | |
2538 | ||
0e32b39c | 2539 | val = DP_TP_CTL_ENABLE | |
c19b0669 | 2540 | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; |
0e32b39c DA |
2541 | if (intel_dp->is_mst) |
2542 | val |= DP_TP_CTL_MODE_MST; | |
2543 | else { | |
2544 | val |= DP_TP_CTL_MODE_SST; | |
2545 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) | |
2546 | val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; | |
2547 | } | |
c19b0669 PZ |
2548 | I915_WRITE(DP_TP_CTL(port), val); |
2549 | POSTING_READ(DP_TP_CTL(port)); | |
2550 | ||
2551 | intel_dp->DP |= DDI_BUF_CTL_ENABLE; | |
2552 | I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); | |
2553 | POSTING_READ(DDI_BUF_CTL(port)); | |
2554 | ||
2555 | udelay(600); | |
2556 | } | |
00c09d70 | 2557 | |
1ad960f2 PZ |
2558 | void intel_ddi_fdi_disable(struct drm_crtc *crtc) |
2559 | { | |
2560 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
2561 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
2562 | uint32_t val; | |
2563 | ||
2564 | intel_ddi_post_disable(intel_encoder); | |
2565 | ||
2566 | val = I915_READ(_FDI_RXA_CTL); | |
2567 | val &= ~FDI_RX_ENABLE; | |
2568 | I915_WRITE(_FDI_RXA_CTL, val); | |
2569 | ||
2570 | val = I915_READ(_FDI_RXA_MISC); | |
2571 | val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
2572 | val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
2573 | I915_WRITE(_FDI_RXA_MISC, val); | |
2574 | ||
2575 | val = I915_READ(_FDI_RXA_CTL); | |
2576 | val &= ~FDI_PCDCLK; | |
2577 | I915_WRITE(_FDI_RXA_CTL, val); | |
2578 | ||
2579 | val = I915_READ(_FDI_RXA_CTL); | |
2580 | val &= ~FDI_RX_PLL_ENABLE; | |
2581 | I915_WRITE(_FDI_RXA_CTL, val); | |
2582 | } | |
2583 | ||
00c09d70 PZ |
2584 | static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder) |
2585 | { | |
0e32b39c DA |
2586 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(&intel_encoder->base); |
2587 | int type = intel_dig_port->base.type; | |
2588 | ||
2589 | if (type != INTEL_OUTPUT_DISPLAYPORT && | |
2590 | type != INTEL_OUTPUT_EDP && | |
2591 | type != INTEL_OUTPUT_UNKNOWN) { | |
2592 | return; | |
2593 | } | |
00c09d70 | 2594 | |
0e32b39c | 2595 | intel_dp_hot_plug(intel_encoder); |
00c09d70 PZ |
2596 | } |
2597 | ||
6801c18c | 2598 | void intel_ddi_get_config(struct intel_encoder *encoder, |
5cec258b | 2599 | struct intel_crtc_state *pipe_config) |
045ac3b5 JB |
2600 | { |
2601 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
2602 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
0cb09a97 | 2603 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; |
bbd440fb | 2604 | struct intel_hdmi *intel_hdmi; |
045ac3b5 JB |
2605 | u32 temp, flags = 0; |
2606 | ||
2607 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
2608 | if (temp & TRANS_DDI_PHSYNC) | |
2609 | flags |= DRM_MODE_FLAG_PHSYNC; | |
2610 | else | |
2611 | flags |= DRM_MODE_FLAG_NHSYNC; | |
2612 | if (temp & TRANS_DDI_PVSYNC) | |
2613 | flags |= DRM_MODE_FLAG_PVSYNC; | |
2614 | else | |
2615 | flags |= DRM_MODE_FLAG_NVSYNC; | |
2616 | ||
2d112de7 | 2617 | pipe_config->base.adjusted_mode.flags |= flags; |
42571aef VS |
2618 | |
2619 | switch (temp & TRANS_DDI_BPC_MASK) { | |
2620 | case TRANS_DDI_BPC_6: | |
2621 | pipe_config->pipe_bpp = 18; | |
2622 | break; | |
2623 | case TRANS_DDI_BPC_8: | |
2624 | pipe_config->pipe_bpp = 24; | |
2625 | break; | |
2626 | case TRANS_DDI_BPC_10: | |
2627 | pipe_config->pipe_bpp = 30; | |
2628 | break; | |
2629 | case TRANS_DDI_BPC_12: | |
2630 | pipe_config->pipe_bpp = 36; | |
2631 | break; | |
2632 | default: | |
2633 | break; | |
2634 | } | |
eb14cb74 VS |
2635 | |
2636 | switch (temp & TRANS_DDI_MODE_SELECT_MASK) { | |
2637 | case TRANS_DDI_MODE_SELECT_HDMI: | |
6897b4b5 | 2638 | pipe_config->has_hdmi_sink = true; |
bbd440fb DV |
2639 | intel_hdmi = enc_to_intel_hdmi(&encoder->base); |
2640 | ||
2641 | if (intel_hdmi->infoframe_enabled(&encoder->base)) | |
2642 | pipe_config->has_infoframe = true; | |
cbc572a9 | 2643 | break; |
eb14cb74 VS |
2644 | case TRANS_DDI_MODE_SELECT_DVI: |
2645 | case TRANS_DDI_MODE_SELECT_FDI: | |
2646 | break; | |
2647 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
2648 | case TRANS_DDI_MODE_SELECT_DP_MST: | |
2649 | pipe_config->has_dp_encoder = true; | |
2650 | intel_dp_get_m_n(intel_crtc, pipe_config); | |
2651 | break; | |
2652 | default: | |
2653 | break; | |
2654 | } | |
10214420 | 2655 | |
f458ebbc | 2656 | if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { |
a60551b1 | 2657 | temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
82910ac6 | 2658 | if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe)) |
a60551b1 PZ |
2659 | pipe_config->has_audio = true; |
2660 | } | |
9ed109a7 | 2661 | |
10214420 DV |
2662 | if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp && |
2663 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { | |
2664 | /* | |
2665 | * This is a big fat ugly hack. | |
2666 | * | |
2667 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
2668 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
2669 | * unknown we fail to light up. Yet the same BIOS boots up with | |
2670 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
2671 | * max, not what it tells us to use. | |
2672 | * | |
2673 | * Note: This will still be broken if the eDP panel is not lit | |
2674 | * up by the BIOS, and thus we can't get the mode at module | |
2675 | * load. | |
2676 | */ | |
2677 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
2678 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); | |
2679 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; | |
2680 | } | |
11578553 | 2681 | |
22606a18 | 2682 | intel_ddi_clock_get(encoder, pipe_config); |
045ac3b5 JB |
2683 | } |
2684 | ||
00c09d70 PZ |
2685 | static void intel_ddi_destroy(struct drm_encoder *encoder) |
2686 | { | |
2687 | /* HDMI has nothing special to destroy, so we can go with this. */ | |
2688 | intel_dp_encoder_destroy(encoder); | |
2689 | } | |
2690 | ||
5bfe2ac0 | 2691 | static bool intel_ddi_compute_config(struct intel_encoder *encoder, |
5cec258b | 2692 | struct intel_crtc_state *pipe_config) |
00c09d70 | 2693 | { |
5bfe2ac0 | 2694 | int type = encoder->type; |
eccb140b | 2695 | int port = intel_ddi_get_encoder_port(encoder); |
00c09d70 | 2696 | |
5bfe2ac0 | 2697 | WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); |
00c09d70 | 2698 | |
eccb140b DV |
2699 | if (port == PORT_A) |
2700 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
2701 | ||
00c09d70 | 2702 | if (type == INTEL_OUTPUT_HDMI) |
5bfe2ac0 | 2703 | return intel_hdmi_compute_config(encoder, pipe_config); |
00c09d70 | 2704 | else |
5bfe2ac0 | 2705 | return intel_dp_compute_config(encoder, pipe_config); |
00c09d70 PZ |
2706 | } |
2707 | ||
2708 | static const struct drm_encoder_funcs intel_ddi_funcs = { | |
2709 | .destroy = intel_ddi_destroy, | |
2710 | }; | |
2711 | ||
4a28ae58 PZ |
2712 | static struct intel_connector * |
2713 | intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) | |
2714 | { | |
2715 | struct intel_connector *connector; | |
2716 | enum port port = intel_dig_port->port; | |
2717 | ||
9bdbd0b9 | 2718 | connector = intel_connector_alloc(); |
4a28ae58 PZ |
2719 | if (!connector) |
2720 | return NULL; | |
2721 | ||
2722 | intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); | |
2723 | if (!intel_dp_init_connector(intel_dig_port, connector)) { | |
2724 | kfree(connector); | |
2725 | return NULL; | |
2726 | } | |
2727 | ||
2728 | return connector; | |
2729 | } | |
2730 | ||
2731 | static struct intel_connector * | |
2732 | intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) | |
2733 | { | |
2734 | struct intel_connector *connector; | |
2735 | enum port port = intel_dig_port->port; | |
2736 | ||
9bdbd0b9 | 2737 | connector = intel_connector_alloc(); |
4a28ae58 PZ |
2738 | if (!connector) |
2739 | return NULL; | |
2740 | ||
2741 | intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); | |
2742 | intel_hdmi_init_connector(intel_dig_port, connector); | |
2743 | ||
2744 | return connector; | |
2745 | } | |
2746 | ||
00c09d70 PZ |
2747 | void intel_ddi_init(struct drm_device *dev, enum port port) |
2748 | { | |
876a8cdf | 2749 | struct drm_i915_private *dev_priv = dev->dev_private; |
00c09d70 PZ |
2750 | struct intel_digital_port *intel_dig_port; |
2751 | struct intel_encoder *intel_encoder; | |
2752 | struct drm_encoder *encoder; | |
311a2094 PZ |
2753 | bool init_hdmi, init_dp; |
2754 | ||
2755 | init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || | |
2756 | dev_priv->vbt.ddi_port_info[port].supports_hdmi); | |
2757 | init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; | |
2758 | if (!init_dp && !init_hdmi) { | |
f68d697e | 2759 | DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n", |
311a2094 PZ |
2760 | port_name(port)); |
2761 | init_hdmi = true; | |
2762 | init_dp = true; | |
2763 | } | |
00c09d70 | 2764 | |
b14c5679 | 2765 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
00c09d70 PZ |
2766 | if (!intel_dig_port) |
2767 | return; | |
2768 | ||
00c09d70 PZ |
2769 | intel_encoder = &intel_dig_port->base; |
2770 | encoder = &intel_encoder->base; | |
2771 | ||
2772 | drm_encoder_init(dev, encoder, &intel_ddi_funcs, | |
2773 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 2774 | |
5bfe2ac0 | 2775 | intel_encoder->compute_config = intel_ddi_compute_config; |
00c09d70 PZ |
2776 | intel_encoder->enable = intel_enable_ddi; |
2777 | intel_encoder->pre_enable = intel_ddi_pre_enable; | |
2778 | intel_encoder->disable = intel_disable_ddi; | |
2779 | intel_encoder->post_disable = intel_ddi_post_disable; | |
2780 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; | |
045ac3b5 | 2781 | intel_encoder->get_config = intel_ddi_get_config; |
00c09d70 PZ |
2782 | |
2783 | intel_dig_port->port = port; | |
bcf53de4 SM |
2784 | intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & |
2785 | (DDI_BUF_PORT_REVERSAL | | |
2786 | DDI_A_4_LANES); | |
00c09d70 PZ |
2787 | |
2788 | intel_encoder->type = INTEL_OUTPUT_UNKNOWN; | |
f68d697e | 2789 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
bc079e8b | 2790 | intel_encoder->cloneable = 0; |
00c09d70 PZ |
2791 | intel_encoder->hot_plug = intel_ddi_hot_plug; |
2792 | ||
f68d697e CW |
2793 | if (init_dp) { |
2794 | if (!intel_ddi_init_dp_connector(intel_dig_port)) | |
2795 | goto err; | |
13cf5504 | 2796 | |
f68d697e CW |
2797 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
2798 | dev_priv->hpd_irq_port[port] = intel_dig_port; | |
2799 | } | |
21a8e6a4 | 2800 | |
311a2094 PZ |
2801 | /* In theory we don't need the encoder->type check, but leave it just in |
2802 | * case we have some really bad VBTs... */ | |
f68d697e CW |
2803 | if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) { |
2804 | if (!intel_ddi_init_hdmi_connector(intel_dig_port)) | |
2805 | goto err; | |
21a8e6a4 | 2806 | } |
f68d697e CW |
2807 | |
2808 | return; | |
2809 | ||
2810 | err: | |
2811 | drm_encoder_cleanup(encoder); | |
2812 | kfree(intel_dig_port); | |
00c09d70 | 2813 | } |