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drm/i915: Move WaBarrierPerformanceFixDisable:skl to skl code from chv code
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34};
35
45244b87
ED		 36/* HDMI/DVI modes ignore everything but the last 2 items. So we share
37 * them for both DP and FDI transports, allowing those ports to
38 * automatically adapt to HDMI connections as well
39 */
10122051
JN		 40static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
41 { 0x00FFFFFF, 0x0006000E },
42 { 0x00D75FFF, 0x0005000A },
43 { 0x00C30FFF, 0x00040006 },
44 { 0x80AAAFFF, 0x000B0000 },
45 { 0x00FFFFFF, 0x0005000A },
46 { 0x00D75FFF, 0x000C0004 },
47 { 0x80C30FFF, 0x000B0000 },
48 { 0x00FFFFFF, 0x00040006 },
49 { 0x80D75FFF, 0x000B0000 },
45244b87
ED		 50};
51
10122051
JN		 52static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
53 { 0x00FFFFFF, 0x0007000E },
54 { 0x00D75FFF, 0x000F000A },
55 { 0x00C30FFF, 0x00060006 },
56 { 0x00AAAFFF, 0x001E0000 },
57 { 0x00FFFFFF, 0x000F000A },
58 { 0x00D75FFF, 0x00160004 },
59 { 0x00C30FFF, 0x001E0000 },
60 { 0x00FFFFFF, 0x00060006 },
61 { 0x00D75FFF, 0x001E0000 },
6acab15a
PZ		 62};
63
10122051
JN		 64static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
65 /* Idx NT mV d T mV d db */
66 { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */
67 { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */
68 { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */
69 { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */
70 { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */
71 { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */
72 { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */
73 { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */
74 { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */
75 { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */
76 { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */
77 { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */
45244b87
ED		 78};
79
10122051
JN		 80static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
81 { 0x00FFFFFF, 0x00000012 },
82 { 0x00EBAFFF, 0x00020011 },
83 { 0x00C71FFF, 0x0006000F },
84 { 0x00AAAFFF, 0x000E000A },
85 { 0x00FFFFFF, 0x00020011 },
86 { 0x00DB6FFF, 0x0005000F },
87 { 0x00BEEFFF, 0x000A000C },
88 { 0x00FFFFFF, 0x0005000F },
89 { 0x00DB6FFF, 0x000A000C },
300644c7
PZ		 90};
91
10122051
JN		 92static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
93 { 0x00FFFFFF, 0x0007000E },
94 { 0x00D75FFF, 0x000E000A },
95 { 0x00BEFFFF, 0x00140006 },
96 { 0x80B2CFFF, 0x001B0002 },
97 { 0x00FFFFFF, 0x000E000A },
17b523ba 98 { 0x00DB6FFF, 0x00160005 },
6805b2a7 99 { 0x80C71FFF, 0x001A0002 },
10122051
JN		 100 { 0x00F7DFFF, 0x00180004 },
101 { 0x80D75FFF, 0x001B0002 },
e58623cb
AR		 102};
103
10122051
JN		 104static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
105 { 0x00FFFFFF, 0x0001000E },
106 { 0x00D75FFF, 0x0004000A },
107 { 0x00C30FFF, 0x00070006 },
108 { 0x00AAAFFF, 0x000C0000 },
109 { 0x00FFFFFF, 0x0004000A },
110 { 0x00D75FFF, 0x00090004 },
111 { 0x00C30FFF, 0x000C0000 },
112 { 0x00FFFFFF, 0x00070006 },
113 { 0x00D75FFF, 0x000C0000 },
e58623cb
AR		 114};
115
10122051
JN		 116static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
117 /* Idx NT mV d T mV df db */
118 { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */
119 { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */
120 { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */
121 { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */
122 { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */
123 { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */
124 { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */
125 { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */
126 { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */
127 { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */
a26aa8ba
DL		 128};
129
7f88e3af 130static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
6c930688
DL		 131 { 0x00000018, 0x000000a2 },
132 { 0x00004014, 0x0000009B },
7f88e3af 133 { 0x00006012, 0x00000088 },
6c930688
DL		 134 { 0x00008010, 0x00000087 },
135 { 0x00000018, 0x0000009B },
7f88e3af 136 { 0x00004014, 0x00000088 },
6c930688 137 { 0x00006012, 0x00000087 },
7f88e3af 138 { 0x00000018, 0x00000088 },
6c930688 139 { 0x00004014, 0x00000087 },
7f88e3af
DL		 140};
141
7ad14a29
SJ		 142/* eDP 1.4 low vswing translation parameters */
143static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
144 { 0x00000018, 0x000000a8 },
145 { 0x00002016, 0x000000ab },
146 { 0x00006012, 0x000000a2 },
147 { 0x00008010, 0x00000088 },
148 { 0x00000018, 0x000000ab },
149 { 0x00004014, 0x000000a2 },
150 { 0x00006012, 0x000000a6 },
151 { 0x00000018, 0x000000a2 },
152 { 0x00005013, 0x0000009c },
153 { 0x00000018, 0x00000088 },
154};
155
156
7f88e3af 157static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
b7192a56
SJ		 158 { 0x00000018, 0x000000ac },
159 { 0x00005012, 0x0000009d },
160 { 0x00007011, 0x00000088 },
161 { 0x00000018, 0x000000a1 },
162 { 0x00000018, 0x00000098 },
163 { 0x00004013, 0x00000088 },
164 { 0x00006012, 0x00000087 },
165 { 0x00000018, 0x000000df },
166 { 0x00003015, 0x00000087 },
167 { 0x00003015, 0x000000c7 },
168 { 0x00000018, 0x000000c7 },
7f88e3af
DL		 169};
170
96fb9f9b
VK		 171struct bxt_ddi_buf_trans {
172 u32 margin; /* swing value */
173 u32 scale; /* scale value */
174 u32 enable; /* scale enable */
175 u32 deemphasis;
176 bool default_index; /* true if the entry represents default value */
177};
178
179/* BSpec does not define separate vswing/pre-emphasis values for eDP.
180 * Using DP values for eDP as well.
181 */
182static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
183 /* Idx NT mV diff db */
184 { 52, 0, 0, 128, true }, /* 0: 400 0 */
185 { 78, 0, 0, 85, false }, /* 1: 400 3.5 */
186 { 104, 0, 0, 64, false }, /* 2: 400 6 */
187 { 154, 0, 0, 43, false }, /* 3: 400 9.5 */
188 { 77, 0, 0, 128, false }, /* 4: 600 0 */
189 { 116, 0, 0, 85, false }, /* 5: 600 3.5 */
190 { 154, 0, 0, 64, false }, /* 6: 600 6 */
191 { 102, 0, 0, 128, false }, /* 7: 800 0 */
192 { 154, 0, 0, 85, false }, /* 8: 800 3.5 */
193 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
194};
195
196/* BSpec has 2 recommended values - entries 0 and 8.
197 * Using the entry with higher vswing.
198 */
199static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
200 /* Idx NT mV diff db */
201 { 52, 0, 0, 128, false }, /* 0: 400 0 */
202 { 52, 0, 0, 85, false }, /* 1: 400 3.5 */
203 { 52, 0, 0, 64, false }, /* 2: 400 6 */
204 { 42, 0, 0, 43, false }, /* 3: 400 9.5 */
205 { 77, 0, 0, 128, false }, /* 4: 600 0 */
206 { 77, 0, 0, 85, false }, /* 5: 600 3.5 */
207 { 77, 0, 0, 64, false }, /* 6: 600 6 */
208 { 102, 0, 0, 128, false }, /* 7: 800 0 */
209 { 102, 0, 0, 85, false }, /* 8: 800 3.5 */
210 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
211};
212
a1e6ad66
ID		 213static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
214 struct intel_digital_port **dig_port,
215 enum port *port)
fc914639 216{
0bdee30e 217 struct drm_encoder *encoder = &intel_encoder->base;
fc914639
PZ		 218 int type = intel_encoder->type;
219
0e32b39c 220 if (type == INTEL_OUTPUT_DP_MST) {
a1e6ad66
ID		 221 *dig_port = enc_to_mst(encoder)->primary;
222 *port = (*dig_port)->port;
0e32b39c 223 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
00c09d70 224 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
a1e6ad66
ID		 225 *dig_port = enc_to_dig_port(encoder);
226 *port = (*dig_port)->port;
fc914639 227 } else if (type == INTEL_OUTPUT_ANALOG) {
a1e6ad66
ID		 228 *dig_port = NULL;
229 *port = PORT_E;
fc914639
PZ		 230 } else {
231 DRM_ERROR("Invalid DDI encoder type %d\n", type);
232 BUG();
233 }
234}
235
a1e6ad66
ID		 236enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
237{
238 struct intel_digital_port *dig_port;
239 enum port port;
240
241 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
242
243 return port;
244}
245
ce3b7e9b
DL		 246static bool
247intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
248{
249 return intel_dig_port->hdmi.hdmi_reg;
250}
251
e58623cb
AR		 252/*
253 * Starting with Haswell, DDI port buffers must be programmed with correct
254 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 255 * but the HDMI/DVI fields are shared among those. So we program the DDI
256 * in either FDI or DP modes only, as HDMI connections will work with both
257 * of those
258 */
faa0cdbe
ID		 259static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
260 bool supports_hdmi)
45244b87
ED		 261{
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 u32 reg;
7ff44670 264 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
7ad14a29 265 size;
6acab15a 266 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
10122051
JN		 267 const struct ddi_buf_trans *ddi_translations_fdi;
268 const struct ddi_buf_trans *ddi_translations_dp;
269 const struct ddi_buf_trans *ddi_translations_edp;
270 const struct ddi_buf_trans *ddi_translations_hdmi;
271 const struct ddi_buf_trans *ddi_translations;
e58623cb 272
96fb9f9b 273 if (IS_BROXTON(dev)) {
faa0cdbe 274 if (!supports_hdmi)
96fb9f9b
VK		 275 return;
276
277 /* Vswing programming for HDMI */
278 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
279 INTEL_OUTPUT_HDMI);
280 return;
281 } else if (IS_SKYLAKE(dev)) {
7f88e3af
DL		 282 ddi_translations_fdi = NULL;
283 ddi_translations_dp = skl_ddi_translations_dp;
7ad14a29 284 n_dp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
9e458034 285 if (dev_priv->edp_low_vswing) {
7ad14a29
SJ		 286 ddi_translations_edp = skl_ddi_translations_edp;
287 n_edp_entries = ARRAY_SIZE(skl_ddi_translations_edp);
288 } else {
289 ddi_translations_edp = skl_ddi_translations_dp;
290 n_edp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
291 }
292
7f88e3af
DL		 293 ddi_translations_hdmi = skl_ddi_translations_hdmi;
294 n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
b7192a56 295 hdmi_default_entry = 7;
7f88e3af 296 } else if (IS_BROADWELL(dev)) {
e58623cb
AR		 297 ddi_translations_fdi = bdw_ddi_translations_fdi;
298 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 299 ddi_translations_edp = bdw_ddi_translations_edp;
a26aa8ba 300 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 301 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
302 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 303 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 304 hdmi_default_entry = 7;
e58623cb
AR		 305 } else if (IS_HASWELL(dev)) {
306 ddi_translations_fdi = hsw_ddi_translations_fdi;
307 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 308 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 309 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
7ad14a29 310 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
10122051 311 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
7ff44670 312 hdmi_default_entry = 6;
e58623cb
AR		 313 } else {
314 WARN(1, "ddi translation table missing\n");
300644c7 315 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 316 ddi_translations_fdi = bdw_ddi_translations_fdi;
317 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 318 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 319 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
320 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 321 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 322 hdmi_default_entry = 7;
e58623cb
AR		 323 }
324
300644c7
PZ		 325 switch (port) {
326 case PORT_A:
327 ddi_translations = ddi_translations_edp;
7ad14a29 328 size = n_edp_entries;
300644c7
PZ		 329 break;
330 case PORT_B:
331 case PORT_C:
300644c7 332 ddi_translations = ddi_translations_dp;
7ad14a29 333 size = n_dp_entries;
300644c7 334 break;
77d8d009 335 case PORT_D:
7ad14a29 336 if (intel_dp_is_edp(dev, PORT_D)) {
77d8d009 337 ddi_translations = ddi_translations_edp;
7ad14a29
SJ		 338 size = n_edp_entries;
339 } else {
77d8d009 340 ddi_translations = ddi_translations_dp;
7ad14a29
SJ		 341 size = n_dp_entries;
342 }
77d8d009 343 break;
300644c7 344 case PORT_E:
7f88e3af
DL		 345 if (ddi_translations_fdi)
346 ddi_translations = ddi_translations_fdi;
347 else
348 ddi_translations = ddi_translations_dp;
7ad14a29 349 size = n_dp_entries;
300644c7
PZ		 350 break;
351 default:
352 BUG();
353 }
45244b87 354
7ad14a29 355 for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) {
10122051
JN		 356 I915_WRITE(reg, ddi_translations[i].trans1);
357 reg += 4;
358 I915_WRITE(reg, ddi_translations[i].trans2);
45244b87
ED		 359 reg += 4;
360 }
ce4dd49e 361
faa0cdbe 362 if (!supports_hdmi)
ce3b7e9b
DL		 363 return;
364
ce4dd49e
DL		 365 /* Choose a good default if VBT is badly populated */
366 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
367 hdmi_level >= n_hdmi_entries)
7ff44670 368 hdmi_level = hdmi_default_entry;
ce4dd49e 369
6acab15a 370 /* Entry 9 is for HDMI: */
10122051
JN		 371 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
372 reg += 4;
373 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
374 reg += 4;
45244b87
ED		 375}
376
377/* Program DDI buffers translations for DP. By default, program ports A-D in DP
378 * mode and port E for FDI.
379 */
380void intel_prepare_ddi(struct drm_device *dev)
381{
faa0cdbe 382 struct intel_encoder *intel_encoder;
b403745c 383 bool visited[I915_MAX_PORTS] = { 0, };
45244b87 384
0d536cb4
PZ		 385 if (!HAS_DDI(dev))
386 return;
45244b87 387
faa0cdbe
ID		 388 for_each_intel_encoder(dev, intel_encoder) {
389 struct intel_digital_port *intel_dig_port;
390 enum port port;
391 bool supports_hdmi;
392
393 ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
394
395 if (visited[port])
b403745c
DL		 396 continue;
397
faa0cdbe
ID		 398 supports_hdmi = intel_dig_port &&
399 intel_dig_port_supports_hdmi(intel_dig_port);
400
401 intel_prepare_ddi_buffers(dev, port, supports_hdmi);
402 visited[port] = true;
b403745c 403 }
45244b87 404}
c82e4d26 405
248138b5
PZ		 406static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
407 enum port port)
408{
409 uint32_t reg = DDI_BUF_CTL(port);
410 int i;
411
3449ca85 412 for (i = 0; i < 16; i++) {
248138b5
PZ		 413 udelay(1);
414 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
415 return;
416 }
417 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
418}
c82e4d26
ED		 419
420/* Starting with Haswell, different DDI ports can work in FDI mode for
421 * connection to the PCH-located connectors. For this, it is necessary to train
422 * both the DDI port and PCH receiver for the desired DDI buffer settings.
423 *
424 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
425 * please note that when FDI mode is active on DDI E, it shares 2 lines with
426 * DDI A (which is used for eDP)
427 */
428
429void hsw_fdi_link_train(struct drm_crtc *crtc)
430{
431 struct drm_device *dev = crtc->dev;
432 struct drm_i915_private *dev_priv = dev->dev_private;
433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 434 u32 temp, i, rx_ctl_val;
c82e4d26 435
04945641
PZ		 436 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
437 * mode set "sequence for CRT port" document:
438 * - TP1 to TP2 time with the default value
439 * - FDI delay to 90h
8693a824
DL		 440 *
441 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641
PZ		 442 */
443 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
444 FDI_RX_PWRDN_LANE0_VAL(2) |
445 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
446
447 /* Enable the PCH Receiver FDI PLL */
3e68320e 448 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 449 FDI_RX_PLL_ENABLE |
6e3c9717 450 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
04945641
PZ		 451 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
452 POSTING_READ(_FDI_RXA_CTL);
453 udelay(220);
454
455 /* Switch from Rawclk to PCDclk */
456 rx_ctl_val |= FDI_PCDCLK;
457 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
458
459 /* Configure Port Clock Select */
6e3c9717
ACO		 460 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
461 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 462
463 /* Start the training iterating through available voltages and emphasis,
464 * testing each value twice. */
10122051 465 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 466 /* Configure DP_TP_CTL with auto-training */
467 I915_WRITE(DP_TP_CTL(PORT_E),
468 DP_TP_CTL_FDI_AUTOTRAIN |
469 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
470 DP_TP_CTL_LINK_TRAIN_PAT1 |
471 DP_TP_CTL_ENABLE);
472
876a8cdf
DL		 473 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
474 * DDI E does not support port reversal, the functionality is
475 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
476 * port reversal bit */
c82e4d26 477 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 478 DDI_BUF_CTL_ENABLE |
6e3c9717 479 ((intel_crtc->config->fdi_lanes - 1) << 1) |
c5fe6a06 480 DDI_BUF_TRANS_SELECT(i / 2));
04945641 481 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 482
483 udelay(600);
484
04945641
PZ		 485 /* Program PCH FDI Receiver TU */
486 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
487
488 /* Enable PCH FDI Receiver with auto-training */
489 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
490 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
491 POSTING_READ(_FDI_RXA_CTL);
492
493 /* Wait for FDI receiver lane calibration */
494 udelay(30);
495
496 /* Unset FDI_RX_MISC pwrdn lanes */
497 temp = I915_READ(_FDI_RXA_MISC);
498 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
499 I915_WRITE(_FDI_RXA_MISC, temp);
500 POSTING_READ(_FDI_RXA_MISC);
501
502 /* Wait for FDI auto training time */
503 udelay(5);
c82e4d26
ED		 504
505 temp = I915_READ(DP_TP_STATUS(PORT_E));
506 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 507 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
c82e4d26
ED		 508
509 /* Enable normal pixel sending for FDI */
510 I915_WRITE(DP_TP_CTL(PORT_E),
04945641
PZ		 511 DP_TP_CTL_FDI_AUTOTRAIN |
512 DP_TP_CTL_LINK_TRAIN_NORMAL |
513 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
514 DP_TP_CTL_ENABLE);
c82e4d26 515
04945641 516 return;
c82e4d26 517 }
04945641 518
248138b5
PZ		 519 temp = I915_READ(DDI_BUF_CTL(PORT_E));
520 temp &= ~DDI_BUF_CTL_ENABLE;
521 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
522 POSTING_READ(DDI_BUF_CTL(PORT_E));
523
04945641 524 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 525 temp = I915_READ(DP_TP_CTL(PORT_E));
526 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
527 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
528 I915_WRITE(DP_TP_CTL(PORT_E), temp);
529 POSTING_READ(DP_TP_CTL(PORT_E));
530
531 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 532
533 rx_ctl_val &= ~FDI_RX_ENABLE;
534 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
248138b5 535 POSTING_READ(_FDI_RXA_CTL);
04945641
PZ		 536
537 /* Reset FDI_RX_MISC pwrdn lanes */
538 temp = I915_READ(_FDI_RXA_MISC);
539 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
540 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
541 I915_WRITE(_FDI_RXA_MISC, temp);
248138b5 542 POSTING_READ(_FDI_RXA_MISC);
c82e4d26
ED		 543 }
544
04945641 545 DRM_ERROR("FDI link training failed!\n");
c82e4d26 546}
0e72a5b5 547
44905a27
DA		 548void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
549{
550 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
551 struct intel_digital_port *intel_dig_port =
552 enc_to_dig_port(&encoder->base);
553
554 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 555 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
44905a27
DA		 556 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
557
558}
559
8d9ddbcb
PZ		 560static struct intel_encoder *
561intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
562{
563 struct drm_device *dev = crtc->dev;
564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
565 struct intel_encoder *intel_encoder, *ret = NULL;
566 int num_encoders = 0;
567
568 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
569 ret = intel_encoder;
570 num_encoders++;
571 }
572
573 if (num_encoders != 1)
84f44ce7
VS		 574 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
575 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 576
577 BUG_ON(ret == NULL);
578 return ret;
579}
580
bcddf610 581struct intel_encoder *
3165c074 582intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 583{
3165c074
ACO		 584 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
585 struct intel_encoder *ret = NULL;
586 struct drm_atomic_state *state;
da3ced29
ACO		 587 struct drm_connector *connector;
588 struct drm_connector_state *connector_state;
d0737e1d 589 int num_encoders = 0;
3165c074 590 int i;
d0737e1d 591
3165c074
ACO		 592 state = crtc_state->base.state;
593
da3ced29
ACO		 594 for_each_connector_in_state(state, connector, connector_state, i) {
595 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 596 continue;
597
da3ced29 598 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 599 num_encoders++;
d0737e1d
ACO		 600 }
601
602 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
603 pipe_name(crtc->pipe));
604
605 BUG_ON(ret == NULL);
606 return ret;
607}
608
1c0b85c5 609#define LC_FREQ 2700
27893390 610#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
1c0b85c5
DL		 611
612#define P_MIN 2
613#define P_MAX 64
614#define P_INC 2
615
616/* Constraints for PLL good behavior */
617#define REF_MIN 48
618#define REF_MAX 400
619#define VCO_MIN 2400
620#define VCO_MAX 4800
621
27893390
DL		 622#define abs_diff(a, b) ({ \
623 typeof(a) __a = (a); \
624 typeof(b) __b = (b); \
625 (void) (&__a == &__b); \
626 __a > __b ? (__a - __b) : (__b - __a); })
1c0b85c5 627
63582983 628struct hsw_wrpll_rnp {
1c0b85c5
DL		 629 unsigned p, n2, r2;
630};
631
63582983 632static unsigned hsw_wrpll_get_budget_for_freq(int clock)
6441ab5f 633{
1c0b85c5
DL		 634 unsigned budget;
635
636 switch (clock) {
637 case 25175000:
638 case 25200000:
639 case 27000000:
640 case 27027000:
641 case 37762500:
642 case 37800000:
643 case 40500000:
644 case 40541000:
645 case 54000000:
646 case 54054000:
647 case 59341000:
648 case 59400000:
649 case 72000000:
650 case 74176000:
651 case 74250000:
652 case 81000000:
653 case 81081000:
654 case 89012000:
655 case 89100000:
656 case 108000000:
657 case 108108000:
658 case 111264000:
659 case 111375000:
660 case 148352000:
661 case 148500000:
662 case 162000000:
663 case 162162000:
664 case 222525000:
665 case 222750000:
666 case 296703000:
667 case 297000000:
668 budget = 0;
669 break;
670 case 233500000:
671 case 245250000:
672 case 247750000:
673 case 253250000:
674 case 298000000:
675 budget = 1500;
676 break;
677 case 169128000:
678 case 169500000:
679 case 179500000:
680 case 202000000:
681 budget = 2000;
682 break;
683 case 256250000:
684 case 262500000:
685 case 270000000:
686 case 272500000:
687 case 273750000:
688 case 280750000:
689 case 281250000:
690 case 286000000:
691 case 291750000:
692 budget = 4000;
693 break;
694 case 267250000:
695 case 268500000:
696 budget = 5000;
697 break;
698 default:
699 budget = 1000;
700 break;
701 }
6441ab5f 702
1c0b85c5
DL		 703 return budget;
704}
705
63582983
DL		 706static void hsw_wrpll_update_rnp(uint64_t freq2k, unsigned budget,
707 unsigned r2, unsigned n2, unsigned p,
708 struct hsw_wrpll_rnp *best)
1c0b85c5
DL		 709{
710 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 711
1c0b85c5
DL		 712 /* No best (r,n,p) yet */
713 if (best->p == 0) {
714 best->p = p;
715 best->n2 = n2;
716 best->r2 = r2;
717 return;
718 }
6441ab5f 719
1c0b85c5
DL		 720 /*
721 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
722 * freq2k.
723 *
724 * delta = 1e6 *
725 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
726 * freq2k;
727 *
728 * and we would like delta <= budget.
729 *
730 * If the discrepancy is above the PPM-based budget, always prefer to
731 * improve upon the previous solution. However, if you're within the
732 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
733 */
734 a = freq2k * budget * p * r2;
735 b = freq2k * budget * best->p * best->r2;
27893390
DL		 736 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
737 diff_best = abs_diff(freq2k * best->p * best->r2,
738 LC_FREQ_2K * best->n2);
1c0b85c5
DL		 739 c = 1000000 * diff;
740 d = 1000000 * diff_best;
741
742 if (a < c && b < d) {
743 /* If both are above the budget, pick the closer */
744 if (best->p * best->r2 * diff < p * r2 * diff_best) {
745 best->p = p;
746 best->n2 = n2;
747 best->r2 = r2;
748 }
749 } else if (a >= c && b < d) {
750 /* If A is below the threshold but B is above it? Update. */
751 best->p = p;
752 best->n2 = n2;
753 best->r2 = r2;
754 } else if (a >= c && b >= d) {
755 /* Both are below the limit, so pick the higher n2/(r2*r2) */
756 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
757 best->p = p;
758 best->n2 = n2;
759 best->r2 = r2;
760 }
761 }
762 /* Otherwise a < c && b >= d, do nothing */
763}
764
63582983 765static int hsw_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, int reg)
11578553
JB		 766{
767 int refclk = LC_FREQ;
768 int n, p, r;
769 u32 wrpll;
770
771 wrpll = I915_READ(reg);
114fe488
DV		 772 switch (wrpll & WRPLL_PLL_REF_MASK) {
773 case WRPLL_PLL_SSC:
774 case WRPLL_PLL_NON_SSC:
11578553
JB		 775 /*
776 * We could calculate spread here, but our checking
777 * code only cares about 5% accuracy, and spread is a max of
778 * 0.5% downspread.
779 */
780 refclk = 135;
781 break;
114fe488 782 case WRPLL_PLL_LCPLL:
11578553
JB		 783 refclk = LC_FREQ;
784 break;
785 default:
786 WARN(1, "bad wrpll refclk\n");
787 return 0;
788 }
789
790 r = wrpll & WRPLL_DIVIDER_REF_MASK;
791 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
792 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
793
20f0ec16
JB		 794 /* Convert to KHz, p & r have a fixed point portion */
795 return (refclk * n * 100) / (p * r);
11578553
JB		 796}
797
540e732c
S		 798static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
799 uint32_t dpll)
800{
801 uint32_t cfgcr1_reg, cfgcr2_reg;
802 uint32_t cfgcr1_val, cfgcr2_val;
803 uint32_t p0, p1, p2, dco_freq;
804
805 cfgcr1_reg = GET_CFG_CR1_REG(dpll);
806 cfgcr2_reg = GET_CFG_CR2_REG(dpll);
807
808 cfgcr1_val = I915_READ(cfgcr1_reg);
809 cfgcr2_val = I915_READ(cfgcr2_reg);
810
811 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
812 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
813
814 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
815 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
816 else
817 p1 = 1;
818
819
820 switch (p0) {
821 case DPLL_CFGCR2_PDIV_1:
822 p0 = 1;
823 break;
824 case DPLL_CFGCR2_PDIV_2:
825 p0 = 2;
826 break;
827 case DPLL_CFGCR2_PDIV_3:
828 p0 = 3;
829 break;
830 case DPLL_CFGCR2_PDIV_7:
831 p0 = 7;
832 break;
833 }
834
835 switch (p2) {
836 case DPLL_CFGCR2_KDIV_5:
837 p2 = 5;
838 break;
839 case DPLL_CFGCR2_KDIV_2:
840 p2 = 2;
841 break;
842 case DPLL_CFGCR2_KDIV_3:
843 p2 = 3;
844 break;
845 case DPLL_CFGCR2_KDIV_1:
846 p2 = 1;
847 break;
848 }
849
850 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
851
852 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
853 1000) / 0x8000;
854
855 return dco_freq / (p0 * p1 * p2 * 5);
856}
857
858
859static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 860 struct intel_crtc_state *pipe_config)
540e732c
S		 861{
862 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
540e732c
S		 863 int link_clock = 0;
864 uint32_t dpll_ctl1, dpll;
865
134ffa44 866 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 867
868 dpll_ctl1 = I915_READ(DPLL_CTRL1);
869
870 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
871 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
872 } else {
71cd8423
DL		 873 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
874 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 875
876 switch (link_clock) {
71cd8423 877 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 878 link_clock = 81000;
879 break;
71cd8423 880 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 881 link_clock = 108000;
882 break;
71cd8423 883 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 884 link_clock = 135000;
885 break;
71cd8423 886 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 887 link_clock = 162000;
888 break;
71cd8423 889 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 890 link_clock = 216000;
891 break;
71cd8423 892 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 893 link_clock = 270000;
894 break;
895 default:
896 WARN(1, "Unsupported link rate\n");
897 break;
898 }
899 link_clock *= 2;
900 }
901
902 pipe_config->port_clock = link_clock;
903
904 if (pipe_config->has_dp_encoder)
2d112de7 905 pipe_config->base.adjusted_mode.crtc_clock =
540e732c
S		 906 intel_dotclock_calculate(pipe_config->port_clock,
907 &pipe_config->dp_m_n);
908 else
2d112de7 909 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
540e732c
S		 910}
911
3d51278a 912static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 913 struct intel_crtc_state *pipe_config)
11578553
JB		 914{
915 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
11578553
JB		 916 int link_clock = 0;
917 u32 val, pll;
918
26804afd 919 val = pipe_config->ddi_pll_sel;
11578553
JB		 920 switch (val & PORT_CLK_SEL_MASK) {
921 case PORT_CLK_SEL_LCPLL_810:
922 link_clock = 81000;
923 break;
924 case PORT_CLK_SEL_LCPLL_1350:
925 link_clock = 135000;
926 break;
927 case PORT_CLK_SEL_LCPLL_2700:
928 link_clock = 270000;
929 break;
930 case PORT_CLK_SEL_WRPLL1:
63582983 931 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
11578553
JB		 932 break;
933 case PORT_CLK_SEL_WRPLL2:
63582983 934 link_clock = hsw_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
11578553
JB		 935 break;
936 case PORT_CLK_SEL_SPLL:
937 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
938 if (pll == SPLL_PLL_FREQ_810MHz)
939 link_clock = 81000;
940 else if (pll == SPLL_PLL_FREQ_1350MHz)
941 link_clock = 135000;
942 else if (pll == SPLL_PLL_FREQ_2700MHz)
943 link_clock = 270000;
944 else {
945 WARN(1, "bad spll freq\n");
946 return;
947 }
948 break;
949 default:
950 WARN(1, "bad port clock sel\n");
951 return;
952 }
953
954 pipe_config->port_clock = link_clock * 2;
955
956 if (pipe_config->has_pch_encoder)
2d112de7 957 pipe_config->base.adjusted_mode.crtc_clock =
11578553
JB		 958 intel_dotclock_calculate(pipe_config->port_clock,
959 &pipe_config->fdi_m_n);
960 else if (pipe_config->has_dp_encoder)
2d112de7 961 pipe_config->base.adjusted_mode.crtc_clock =
11578553
JB		 962 intel_dotclock_calculate(pipe_config->port_clock,
963 &pipe_config->dp_m_n);
964 else
2d112de7 965 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
11578553
JB		 966}
967
977bb38d
S		 968static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
969 enum intel_dpll_id dpll)
970{
971 /* FIXME formula not available in bspec */
972 return 0;
973}
974
975static void bxt_ddi_clock_get(struct intel_encoder *encoder,
976 struct intel_crtc_state *pipe_config)
977{
978 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
979 enum port port = intel_ddi_get_encoder_port(encoder);
980 uint32_t dpll = port;
981
982 pipe_config->port_clock =
983 bxt_calc_pll_link(dev_priv, dpll);
984
985 if (pipe_config->has_dp_encoder)
986 pipe_config->base.adjusted_mode.crtc_clock =
987 intel_dotclock_calculate(pipe_config->port_clock,
988 &pipe_config->dp_m_n);
989 else
990 pipe_config->base.adjusted_mode.crtc_clock =
991 pipe_config->port_clock;
992}
993
3d51278a 994void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 995 struct intel_crtc_state *pipe_config)
3d51278a 996{
22606a18
DL		 997 struct drm_device *dev = encoder->base.dev;
998
999 if (INTEL_INFO(dev)->gen <= 8)
1000 hsw_ddi_clock_get(encoder, pipe_config);
977bb38d 1001 else if (IS_SKYLAKE(dev))
22606a18 1002 skl_ddi_clock_get(encoder, pipe_config);
977bb38d
S		 1003 else if (IS_BROXTON(dev))
1004 bxt_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1005}
1006
1c0b85c5 1007static void
d664c0ce
DL		 1008hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1009 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1c0b85c5
DL		 1010{
1011 uint64_t freq2k;
1012 unsigned p, n2, r2;
63582983 1013 struct hsw_wrpll_rnp best = { 0, 0, 0 };
1c0b85c5
DL		 1014 unsigned budget;
1015
1016 freq2k = clock / 100;
1017
63582983 1018 budget = hsw_wrpll_get_budget_for_freq(clock);
1c0b85c5
DL		 1019
1020 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1021 * and directly pass the LC PLL to it. */
1022 if (freq2k == 5400000) {
1023 *n2_out = 2;
1024 *p_out = 1;
1025 *r2_out = 2;
1026 return;
1027 }
1028
1029 /*
1030 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1031 * the WR PLL.
1032 *
1033 * We want R so that REF_MIN <= Ref <= REF_MAX.
1034 * Injecting R2 = 2 * R gives:
1035 * REF_MAX * r2 > LC_FREQ * 2 and
1036 * REF_MIN * r2 < LC_FREQ * 2
1037 *
1038 * Which means the desired boundaries for r2 are:
1039 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1040 *
1041 */
1042 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1043 r2 <= LC_FREQ * 2 / REF_MIN;
1044 r2++) {
1045
1046 /*
1047 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1048 *
1049 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1050 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1051 * VCO_MAX * r2 > n2 * LC_FREQ and
1052 * VCO_MIN * r2 < n2 * LC_FREQ)
1053 *
1054 * Which means the desired boundaries for n2 are:
1055 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1056 */
1057 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1058 n2 <= VCO_MAX * r2 / LC_FREQ;
1059 n2++) {
1060
1061 for (p = P_MIN; p <= P_MAX; p += P_INC)
63582983
DL		 1062 hsw_wrpll_update_rnp(freq2k, budget,
1063 r2, n2, p, &best);
1c0b85c5
DL		 1064 }
1065 }
6441ab5f 1066
1c0b85c5
DL		 1067 *n2_out = best.n2;
1068 *p_out = best.p;
1069 *r2_out = best.r2;
6441ab5f
PZ		 1070}
1071
0220ab6e 1072static bool
d664c0ce 1073hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1074 struct intel_crtc_state *crtc_state,
d664c0ce
DL		 1075 struct intel_encoder *intel_encoder,
1076 int clock)
6441ab5f 1077{
d664c0ce 1078 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
e0b01be4 1079 struct intel_shared_dpll *pll;
716c2e55 1080 uint32_t val;
1c0b85c5 1081 unsigned p, n2, r2;
6441ab5f 1082
d664c0ce 1083 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
0694001b 1084
114fe488 1085 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
0694001b
PZ		 1086 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1087 WRPLL_DIVIDER_POST(p);
1088
dd3cd74a
ACO		 1089 memset(&crtc_state->dpll_hw_state, 0,
1090 sizeof(crtc_state->dpll_hw_state));
1091
190f68c5 1092 crtc_state->dpll_hw_state.wrpll = val;
6441ab5f 1093
190f68c5 1094 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
716c2e55
DV		 1095 if (pll == NULL) {
1096 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1097 pipe_name(intel_crtc->pipe));
1098 return false;
0694001b 1099 }
d452c5b6 1100
190f68c5 1101 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
6441ab5f
PZ		 1102 }
1103
6441ab5f
PZ		 1104 return true;
1105}
1106
82d35437
S		 1107struct skl_wrpll_params {
1108 uint32_t dco_fraction;
1109 uint32_t dco_integer;
1110 uint32_t qdiv_ratio;
1111 uint32_t qdiv_mode;
1112 uint32_t kdiv;
1113 uint32_t pdiv;
1114 uint32_t central_freq;
1115};
1116
76516fbc
DL		 1117static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1118 uint64_t afe_clock,
1119 uint64_t central_freq,
1120 uint32_t p0, uint32_t p1, uint32_t p2)
1121{
1122 uint64_t dco_freq;
1123
76516fbc
DL		 1124 switch (central_freq) {
1125 case 9600000000ULL:
1126 params->central_freq = 0;
1127 break;
1128 case 9000000000ULL:
1129 params->central_freq = 1;
1130 break;
1131 case 8400000000ULL:
1132 params->central_freq = 3;
1133 }
1134
1135 switch (p0) {
1136 case 1:
1137 params->pdiv = 0;
1138 break;
1139 case 2:
1140 params->pdiv = 1;
1141 break;
1142 case 3:
1143 params->pdiv = 2;
1144 break;
1145 case 7:
1146 params->pdiv = 4;
1147 break;
1148 default:
1149 WARN(1, "Incorrect PDiv\n");
1150 }
1151
1152 switch (p2) {
1153 case 5:
1154 params->kdiv = 0;
1155 break;
1156 case 2:
1157 params->kdiv = 1;
1158 break;
1159 case 3:
1160 params->kdiv = 2;
1161 break;
1162 case 1:
1163 params->kdiv = 3;
1164 break;
1165 default:
1166 WARN(1, "Incorrect KDiv\n");
1167 }
1168
1169 params->qdiv_ratio = p1;
1170 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1171
1172 dco_freq = p0 * p1 * p2 * afe_clock;
1173
1174 /*
1175 * Intermediate values are in Hz.
1176 * Divide by MHz to match bsepc
1177 */
30a7862d 1178 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
76516fbc 1179 params->dco_fraction =
30a7862d
DL		 1180 div_u64((div_u64(dco_freq, 24) -
1181 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
76516fbc
DL		 1182}
1183
318bd821 1184static bool
82d35437
S		 1185skl_ddi_calculate_wrpll(int clock /* in Hz */,
1186 struct skl_wrpll_params *wrpll_params)
1187{
1188 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
21318cce
DL		 1189 uint64_t dco_central_freq[3] = {8400000000ULL,
1190 9000000000ULL,
1191 9600000000ULL};
82d35437
S		 1192 uint32_t min_dco_deviation = 400;
1193 uint32_t min_dco_index = 3;
1194 uint32_t P0[4] = {1, 2, 3, 7};
1195 uint32_t P2[4] = {1, 2, 3, 5};
1196 bool found = false;
1197 uint32_t candidate_p = 0;
1198 uint32_t candidate_p0[3] = {0}, candidate_p1[3] = {0};
1199 uint32_t candidate_p2[3] = {0};
1200 uint32_t dco_central_freq_deviation[3];
1201 uint32_t i, P1, k, dco_count;
1202 bool retry_with_odd = false;
82d35437
S		 1203
1204 /* Determine P0, P1 or P2 */
1205 for (dco_count = 0; dco_count < 3; dco_count++) {
1206 found = false;
1207 candidate_p =
1208 div64_u64(dco_central_freq[dco_count], afe_clock);
1209 if (retry_with_odd == false)
1210 candidate_p = (candidate_p % 2 == 0 ?
1211 candidate_p : candidate_p + 1);
1212
1213 for (P1 = 1; P1 < candidate_p; P1++) {
1214 for (i = 0; i < 4; i++) {
1215 if (!(P0[i] != 1 || P1 == 1))
1216 continue;
1217
1218 for (k = 0; k < 4; k++) {
1219 if (P1 != 1 && P2[k] != 2)
1220 continue;
1221
1222 if (candidate_p == P0[i] * P1 * P2[k]) {
1223 /* Found possible P0, P1, P2 */
1224 found = true;
1225 candidate_p0[dco_count] = P0[i];
1226 candidate_p1[dco_count] = P1;
1227 candidate_p2[dco_count] = P2[k];
1228 goto found;
1229 }
1230
1231 }
1232 }
1233 }
1234
1235found:
1236 if (found) {
1237 dco_central_freq_deviation[dco_count] =
1238 div64_u64(10000 *
64311571 1239 abs_diff(candidate_p * afe_clock,
82d35437
S		 1240 dco_central_freq[dco_count]),
1241 dco_central_freq[dco_count]);
1242
1243 if (dco_central_freq_deviation[dco_count] <
1244 min_dco_deviation) {
1245 min_dco_deviation =
1246 dco_central_freq_deviation[dco_count];
1247 min_dco_index = dco_count;
1248 }
1249 }
1250
1251 if (min_dco_index > 2 && dco_count == 2) {
6cf75178
DL		 1252 /* oh well, we tried... */
1253 if (retry_with_odd)
1254 break;
1255
82d35437
S		 1256 retry_with_odd = true;
1257 dco_count = 0;
1258 }
1259 }
1260
9c236753
DL		 1261 if (WARN(min_dco_index > 2,
1262 "No valid parameters found for pixel clock: %dHz\n", clock))
318bd821 1263 return false;
82d35437 1264
76516fbc
DL		 1265 skl_wrpll_params_populate(wrpll_params,
1266 afe_clock,
1267 dco_central_freq[min_dco_index],
1268 candidate_p0[min_dco_index],
1269 candidate_p1[min_dco_index],
1270 candidate_p2[min_dco_index]);
318bd821
DL		 1271
1272 return true;
82d35437
S		 1273}
1274
1275
1276static bool
1277skl_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1278 struct intel_crtc_state *crtc_state,
82d35437
S		 1279 struct intel_encoder *intel_encoder,
1280 int clock)
1281{
1282 struct intel_shared_dpll *pll;
1283 uint32_t ctrl1, cfgcr1, cfgcr2;
1284
1285 /*
1286 * See comment in intel_dpll_hw_state to understand why we always use 0
1287 * as the DPLL id in this function.
1288 */
1289
1290 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1291
1292 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1293 struct skl_wrpll_params wrpll_params = { 0, };
1294
1295 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1296
318bd821
DL		 1297 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1298 return false;
82d35437
S		 1299
1300 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1301 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1302 wrpll_params.dco_integer;
1303
1304 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1305 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1306 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1307 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1308 wrpll_params.central_freq;
1309 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1310 struct drm_encoder *encoder = &intel_encoder->base;
1311 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1312
1313 switch (intel_dp->link_bw) {
1314 case DP_LINK_BW_1_62:
71cd8423 1315 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
82d35437
S		 1316 break;
1317 case DP_LINK_BW_2_7:
71cd8423 1318 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
82d35437
S		 1319 break;
1320 case DP_LINK_BW_5_4:
71cd8423 1321 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
82d35437
S		 1322 break;
1323 }
1324
1325 cfgcr1 = cfgcr2 = 0;
1326 } else /* eDP */
1327 return true;
1328
dd3cd74a
ACO		 1329 memset(&crtc_state->dpll_hw_state, 0,
1330 sizeof(crtc_state->dpll_hw_state));
1331
190f68c5
ACO		 1332 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1333 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1334 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
82d35437 1335
190f68c5 1336 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
82d35437
S		 1337 if (pll == NULL) {
1338 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1339 pipe_name(intel_crtc->pipe));
1340 return false;
1341 }
1342
1343 /* shared DPLL id 0 is DPLL 1 */
190f68c5 1344 crtc_state->ddi_pll_sel = pll->id + 1;
82d35437
S		 1345
1346 return true;
1347}
0220ab6e 1348
d683f3bc
S		 1349/* bxt clock parameters */
1350struct bxt_clk_div {
1351 uint32_t p1;
1352 uint32_t p2;
1353 uint32_t m2_int;
1354 uint32_t m2_frac;
1355 bool m2_frac_en;
1356 uint32_t n;
d683f3bc
S		 1357};
1358
1359/* pre-calculated values for DP linkrates */
1360static struct bxt_clk_div bxt_dp_clk_val[7] = {
e0681e38
VK		 1361 /* 162 */ {4, 2, 32, 1677722, 1, 1},
1362 /* 270 */ {4, 1, 27, 0, 0, 1},
1363 /* 540 */ {2, 1, 27, 0, 0, 1},
1364 /* 216 */ {3, 2, 32, 1677722, 1, 1},
1365 /* 243 */ {4, 1, 24, 1258291, 1, 1},
1366 /* 324 */ {4, 1, 32, 1677722, 1, 1},
1367 /* 432 */ {3, 1, 32, 1677722, 1, 1}
d683f3bc
S		 1368};
1369
1370static bool
1371bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1372 struct intel_crtc_state *crtc_state,
1373 struct intel_encoder *intel_encoder,
1374 int clock)
1375{
1376 struct intel_shared_dpll *pll;
1377 struct bxt_clk_div clk_div = {0};
b6dc71f3
VK		 1378 int vco = 0;
1379 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
e0681e38 1380 uint32_t dcoampovr_en_h, dco_amp, lanestagger;
d683f3bc
S		 1381
1382 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1383 intel_clock_t best_clock;
1384
1385 /* Calculate HDMI div */
1386 /*
1387 * FIXME: tie the following calculation into
1388 * i9xx_crtc_compute_clock
1389 */
1390 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1391 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1392 clock, pipe_name(intel_crtc->pipe));
1393 return false;
1394 }
1395
1396 clk_div.p1 = best_clock.p1;
1397 clk_div.p2 = best_clock.p2;
1398 WARN_ON(best_clock.m1 != 2);
1399 clk_div.n = best_clock.n;
1400 clk_div.m2_int = best_clock.m2 >> 22;
1401 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1402 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1403
b6dc71f3 1404 vco = best_clock.vco;
d683f3bc
S		 1405 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1406 intel_encoder->type == INTEL_OUTPUT_EDP) {
1407 struct drm_encoder *encoder = &intel_encoder->base;
1408 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1409
1410 switch (intel_dp->link_bw) {
1411 case DP_LINK_BW_1_62:
1412 clk_div = bxt_dp_clk_val[0];
1413 break;
1414 case DP_LINK_BW_2_7:
1415 clk_div = bxt_dp_clk_val[1];
1416 break;
1417 case DP_LINK_BW_5_4:
1418 clk_div = bxt_dp_clk_val[2];
1419 break;
1420 default:
1421 clk_div = bxt_dp_clk_val[0];
1422 DRM_ERROR("Unknown link rate\n");
1423 }
b6dc71f3
VK		 1424 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1425 }
1426
1427 dco_amp = 15;
1428 dcoampovr_en_h = 0;
1429 if (vco >= 6200000 && vco <= 6480000) {
1430 prop_coef = 4;
1431 int_coef = 9;
1432 gain_ctl = 3;
1433 targ_cnt = 8;
1434 } else if ((vco > 5400000 && vco < 6200000) ||
1435 (vco >= 4800000 && vco < 5400000)) {
1436 prop_coef = 5;
1437 int_coef = 11;
1438 gain_ctl = 3;
1439 targ_cnt = 9;
1440 if (vco >= 4800000 && vco < 5400000)
1441 dcoampovr_en_h = 1;
1442 } else if (vco == 5400000) {
1443 prop_coef = 3;
1444 int_coef = 8;
1445 gain_ctl = 1;
1446 targ_cnt = 9;
1447 } else {
1448 DRM_ERROR("Invalid VCO\n");
1449 return false;
d683f3bc
S		 1450 }
1451
dd3cd74a
ACO		 1452 memset(&crtc_state->dpll_hw_state, 0,
1453 sizeof(crtc_state->dpll_hw_state));
1454
e0681e38
VK		 1455 if (clock > 270000)
1456 lanestagger = 0x18;
1457 else if (clock > 135000)
1458 lanestagger = 0x0d;
1459 else if (clock > 67000)
1460 lanestagger = 0x07;
1461 else if (clock > 33000)
1462 lanestagger = 0x04;
1463 else
1464 lanestagger = 0x02;
1465
d683f3bc
S		 1466 crtc_state->dpll_hw_state.ebb0 =
1467 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1468 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1469 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1470 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1471
1472 if (clk_div.m2_frac_en)
1473 crtc_state->dpll_hw_state.pll3 =
1474 PORT_PLL_M2_FRAC_ENABLE;
1475
1476 crtc_state->dpll_hw_state.pll6 =
b6dc71f3 1477 prop_coef | PORT_PLL_INT_COEFF(int_coef);
d683f3bc 1478 crtc_state->dpll_hw_state.pll6 |=
b6dc71f3
VK		 1479 PORT_PLL_GAIN_CTL(gain_ctl);
1480
1481 crtc_state->dpll_hw_state.pll8 = targ_cnt;
d683f3bc 1482
b6dc71f3
VK		 1483 if (dcoampovr_en_h)
1484 crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H;
1485
1486 crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp);
d683f3bc
S		 1487
1488 crtc_state->dpll_hw_state.pcsdw12 =
e0681e38 1489 LANESTAGGER_STRAP_OVRD | lanestagger;
d683f3bc
S		 1490
1491 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1492 if (pll == NULL) {
1493 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1494 pipe_name(intel_crtc->pipe));
1495 return false;
1496 }
1497
1498 /* shared DPLL id 0 is DPLL A */
1499 crtc_state->ddi_pll_sel = pll->id;
1500
1501 return true;
1502}
1503
0220ab6e
DL		 1504/*
1505 * Tries to find a *shared* PLL for the CRTC and store it in
1506 * intel_crtc->ddi_pll_sel.
1507 *
1508 * For private DPLLs, compute_config() should do the selection for us. This
1509 * function should be folded into compute_config() eventually.
1510 */
190f68c5
ACO		 1511bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1512 struct intel_crtc_state *crtc_state)
0220ab6e 1513{
82d35437 1514 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d 1515 struct intel_encoder *intel_encoder =
3165c074 1516 intel_ddi_get_crtc_new_encoder(crtc_state);
190f68c5 1517 int clock = crtc_state->port_clock;
0220ab6e 1518
82d35437 1519 if (IS_SKYLAKE(dev))
190f68c5
ACO		 1520 return skl_ddi_pll_select(intel_crtc, crtc_state,
1521 intel_encoder, clock);
d683f3bc
S		 1522 else if (IS_BROXTON(dev))
1523 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1524 intel_encoder, clock);
82d35437 1525 else
190f68c5
ACO		 1526 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1527 intel_encoder, clock);
0220ab6e
DL		 1528}
1529
dae84799
PZ		 1530void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1531{
1532 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1533 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1534 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6e3c9717 1535 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
dae84799
PZ		 1536 int type = intel_encoder->type;
1537 uint32_t temp;
1538
0e32b39c 1539 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
c9809791 1540 temp = TRANS_MSA_SYNC_CLK;
6e3c9717 1541 switch (intel_crtc->config->pipe_bpp) {
dae84799 1542 case 18:
c9809791 1543 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1544 break;
1545 case 24:
c9809791 1546 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1547 break;
1548 case 30:
c9809791 1549 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1550 break;
1551 case 36:
c9809791 1552 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1553 break;
1554 default:
4e53c2e0 1555 BUG();
dae84799 1556 }
c9809791 1557 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1558 }
1559}
1560
0e32b39c
DA		 1561void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1562{
1563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1564 struct drm_device *dev = crtc->dev;
1565 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1566 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
0e32b39c
DA		 1567 uint32_t temp;
1568 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1569 if (state == true)
1570 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1571 else
1572 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1573 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1574}
1575
8228c251 1576void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1577{
1578 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1579 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1580 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 1581 struct drm_device *dev = crtc->dev;
1582 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 1583 enum pipe pipe = intel_crtc->pipe;
6e3c9717 1584 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
174edf1f 1585 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1586 int type = intel_encoder->type;
8d9ddbcb
PZ		 1587 uint32_t temp;
1588
ad80a810
PZ		 1589 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1590 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1591 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1592
6e3c9717 1593 switch (intel_crtc->config->pipe_bpp) {
dfcef252 1594 case 18:
ad80a810 1595 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1596 break;
1597 case 24:
ad80a810 1598 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1599 break;
1600 case 30:
ad80a810 1601 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1602 break;
1603 case 36:
ad80a810 1604 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1605 break;
1606 default:
4e53c2e0 1607 BUG();
dfcef252 1608 }
72662e10 1609
6e3c9717 1610 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1611 temp |= TRANS_DDI_PVSYNC;
6e3c9717 1612 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1613 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1614
e6f0bfc4
PZ		 1615 if (cpu_transcoder == TRANSCODER_EDP) {
1616 switch (pipe) {
1617 case PIPE_A:
c7670b10
PZ		 1618 /* On Haswell, can only use the always-on power well for
1619 * eDP when not using the panel fitter, and when not
1620 * using motion blur mitigation (which we don't
1621 * support). */
fabf6e51 1622 if (IS_HASWELL(dev) &&
6e3c9717
ACO		 1623 (intel_crtc->config->pch_pfit.enabled ||
1624 intel_crtc->config->pch_pfit.force_thru))
d6dd9eb1
DV		 1625 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1626 else
1627 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1628 break;
1629 case PIPE_B:
1630 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1631 break;
1632 case PIPE_C:
1633 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1634 break;
1635 default:
1636 BUG();
1637 break;
1638 }
1639 }
1640
7739c33b 1641 if (type == INTEL_OUTPUT_HDMI) {
6e3c9717 1642 if (intel_crtc->config->has_hdmi_sink)
ad80a810 1643 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1644 else
ad80a810 1645 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1646
7739c33b 1647 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1648 temp |= TRANS_DDI_MODE_SELECT_FDI;
6e3c9717 1649 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
7739c33b
PZ		 1650
1651 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1652 type == INTEL_OUTPUT_EDP) {
1653 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1654
0e32b39c
DA		 1655 if (intel_dp->is_mst) {
1656 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1657 } else
1658 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1659
1660 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1661 } else if (type == INTEL_OUTPUT_DP_MST) {
1662 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1663
1664 if (intel_dp->is_mst) {
1665 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1666 } else
1667 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1668
17aa6be9 1669 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
8d9ddbcb 1670 } else {
84f44ce7
VS		 1671 WARN(1, "Invalid encoder type %d for pipe %c\n",
1672 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1673 }
1674
ad80a810 1675 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1676}
72662e10 1677
ad80a810
PZ		 1678void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1679 enum transcoder cpu_transcoder)
8d9ddbcb 1680{
ad80a810 1681 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1682 uint32_t val = I915_READ(reg);
1683
0e32b39c 1684 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1685 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1686 I915_WRITE(reg, val);
72662e10
ED		 1687}
1688
bcbc889b
PZ		 1689bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1690{
1691 struct drm_device *dev = intel_connector->base.dev;
1692 struct drm_i915_private *dev_priv = dev->dev_private;
1693 struct intel_encoder *intel_encoder = intel_connector->encoder;
1694 int type = intel_connector->base.connector_type;
1695 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1696 enum pipe pipe = 0;
1697 enum transcoder cpu_transcoder;
882244a3 1698 enum intel_display_power_domain power_domain;
bcbc889b
PZ		 1699 uint32_t tmp;
1700
882244a3 1701 power_domain = intel_display_port_power_domain(intel_encoder);
f458ebbc 1702 if (!intel_display_power_is_enabled(dev_priv, power_domain))
882244a3
PZ		 1703 return false;
1704
bcbc889b
PZ		 1705 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1706 return false;
1707
1708 if (port == PORT_A)
1709 cpu_transcoder = TRANSCODER_EDP;
1710 else
1a240d4d 1711 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1712
1713 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1714
1715 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1716 case TRANS_DDI_MODE_SELECT_HDMI:
1717 case TRANS_DDI_MODE_SELECT_DVI:
1718 return (type == DRM_MODE_CONNECTOR_HDMIA);
1719
1720 case TRANS_DDI_MODE_SELECT_DP_SST:
1721 if (type == DRM_MODE_CONNECTOR_eDP)
1722 return true;
bcbc889b 1723 return (type == DRM_MODE_CONNECTOR_DisplayPort);
0e32b39c
DA		 1724 case TRANS_DDI_MODE_SELECT_DP_MST:
1725 /* if the transcoder is in MST state then
1726 * connector isn't connected */
1727 return false;
bcbc889b
PZ		 1728
1729 case TRANS_DDI_MODE_SELECT_FDI:
1730 return (type == DRM_MODE_CONNECTOR_VGA);
1731
1732 default:
1733 return false;
1734 }
1735}
1736
85234cdc
DV		 1737bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1738 enum pipe *pipe)
1739{
1740 struct drm_device *dev = encoder->base.dev;
1741 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 1742 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 1743 enum intel_display_power_domain power_domain;
85234cdc
DV		 1744 u32 tmp;
1745 int i;
1746
6d129bea 1747 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1748 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1749 return false;
1750
fe43d3f5 1751 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1752
1753 if (!(tmp & DDI_BUF_CTL_ENABLE))
1754 return false;
1755
ad80a810
PZ		 1756 if (port == PORT_A) {
1757 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1758
ad80a810
PZ		 1759 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1760 case TRANS_DDI_EDP_INPUT_A_ON:
1761 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1762 *pipe = PIPE_A;
1763 break;
1764 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1765 *pipe = PIPE_B;
1766 break;
1767 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1768 *pipe = PIPE_C;
1769 break;
1770 }
1771
1772 return true;
1773 } else {
1774 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1775 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1776
1777 if ((tmp & TRANS_DDI_PORT_MASK)
1778 == TRANS_DDI_SELECT_PORT(port)) {
0e32b39c
DA		 1779 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1780 return false;
1781
ad80a810
PZ		 1782 *pipe = i;
1783 return true;
1784 }
85234cdc
DV		 1785 }
1786 }
1787
84f44ce7 1788 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 1789
22f9fe50 1790 return false;
85234cdc
DV		 1791}
1792
fc914639
PZ		 1793void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1794{
1795 struct drm_crtc *crtc = &intel_crtc->base;
1796 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1797 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1798 enum port port = intel_ddi_get_encoder_port(intel_encoder);
6e3c9717 1799 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 1800
bb523fc0
PZ		 1801 if (cpu_transcoder != TRANSCODER_EDP)
1802 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1803 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1804}
1805
1806void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1807{
1808 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
6e3c9717 1809 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 1810
bb523fc0
PZ		 1811 if (cpu_transcoder != TRANSCODER_EDP)
1812 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1813 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1814}
1815
96fb9f9b
VK		 1816void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
1817 enum port port, int type)
1818{
1819 struct drm_i915_private *dev_priv = dev->dev_private;
1820 const struct bxt_ddi_buf_trans *ddi_translations;
1821 u32 n_entries, i;
1822 uint32_t val;
1823
1824 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1825 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1826 ddi_translations = bxt_ddi_translations_dp;
1827 } else if (type == INTEL_OUTPUT_HDMI) {
1828 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1829 ddi_translations = bxt_ddi_translations_hdmi;
1830 } else {
1831 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1832 type);
1833 return;
1834 }
1835
1836 /* Check if default value has to be used */
1837 if (level >= n_entries ||
1838 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1839 for (i = 0; i < n_entries; i++) {
1840 if (ddi_translations[i].default_index) {
1841 level = i;
1842 break;
1843 }
1844 }
1845 }
1846
1847 /*
1848 * While we write to the group register to program all lanes at once we
1849 * can read only lane registers and we pick lanes 0/1 for that.
1850 */
1851 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1852 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
1853 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1854
1855 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
1856 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
1857 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
1858 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
1859 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
1860
1861 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
1862 val &= ~UNIQE_TRANGE_EN_METHOD;
1863 if (ddi_translations[level].enable)
1864 val |= UNIQE_TRANGE_EN_METHOD;
1865 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
1866
1867 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
1868 val &= ~DE_EMPHASIS;
1869 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
1870 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
1871
1872 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1873 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
1874 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1875}
1876
00c09d70 1877static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
6441ab5f 1878{
c19b0669 1879 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 1880 struct drm_device *dev = encoder->dev;
1881 struct drm_i915_private *dev_priv = dev->dev_private;
30cf6db8 1882 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
6441ab5f 1883 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1884 int type = intel_encoder->type;
96fb9f9b 1885 int hdmi_level;
6441ab5f 1886
82a4d9c0
PZ		 1887 if (type == INTEL_OUTPUT_EDP) {
1888 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4be73780 1889 intel_edp_panel_on(intel_dp);
82a4d9c0 1890 }
6441ab5f 1891
efa80add 1892 if (IS_SKYLAKE(dev)) {
6e3c9717 1893 uint32_t dpll = crtc->config->ddi_pll_sel;
efa80add
S		 1894 uint32_t val;
1895
5416d871
DL		 1896 /*
1897 * DPLL0 is used for eDP and is the only "private" DPLL (as
1898 * opposed to shared) on SKL
1899 */
1900 if (type == INTEL_OUTPUT_EDP) {
1901 WARN_ON(dpll != SKL_DPLL0);
1902
1903 val = I915_READ(DPLL_CTRL1);
1904
1905 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
1906 DPLL_CTRL1_SSC(dpll) |
71cd8423 1907 DPLL_CTRL1_LINK_RATE_MASK(dpll));
6e3c9717 1908 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
5416d871
DL		 1909
1910 I915_WRITE(DPLL_CTRL1, val);
1911 POSTING_READ(DPLL_CTRL1);
1912 }
1913
1914 /* DDI -> PLL mapping */
efa80add
S		 1915 val = I915_READ(DPLL_CTRL2);
1916
1917 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1918 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1919 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1920 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1921
1922 I915_WRITE(DPLL_CTRL2, val);
5416d871 1923
1ab23380 1924 } else if (INTEL_INFO(dev)->gen < 9) {
6e3c9717
ACO		 1925 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
1926 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
efa80add 1927 }
c19b0669 1928
82a4d9c0 1929 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669 1930 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 1931
44905a27 1932 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 1933
1934 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1935 intel_dp_start_link_train(intel_dp);
1936 intel_dp_complete_link_train(intel_dp);
23f08d83 1937 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
3ab9c637 1938 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 1939 } else if (type == INTEL_OUTPUT_HDMI) {
1940 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1941
96fb9f9b
VK		 1942 if (IS_BROXTON(dev)) {
1943 hdmi_level = dev_priv->vbt.
1944 ddi_port_info[port].hdmi_level_shift;
1945 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
1946 INTEL_OUTPUT_HDMI);
1947 }
30cf6db8 1948 intel_hdmi->set_infoframes(encoder,
6e3c9717
ACO		 1949 crtc->config->has_hdmi_sink,
1950 &crtc->config->base.adjusted_mode);
c19b0669 1951 }
6441ab5f
PZ		 1952}
1953
00c09d70 1954static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 1955{
1956 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 1957 struct drm_device *dev = encoder->dev;
1958 struct drm_i915_private *dev_priv = dev->dev_private;
6441ab5f 1959 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1960 int type = intel_encoder->type;
2886e93f 1961 uint32_t val;
a836bdf9 1962 bool wait = false;
2886e93f
PZ		 1963
1964 val = I915_READ(DDI_BUF_CTL(port));
1965 if (val & DDI_BUF_CTL_ENABLE) {
1966 val &= ~DDI_BUF_CTL_ENABLE;
1967 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 1968 wait = true;
2886e93f 1969 }
6441ab5f 1970
a836bdf9
PZ		 1971 val = I915_READ(DP_TP_CTL(port));
1972 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1973 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1974 I915_WRITE(DP_TP_CTL(port), val);
1975
1976 if (wait)
1977 intel_wait_ddi_buf_idle(dev_priv, port);
1978
76bb80ed 1979 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 1980 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 1981 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 1982 intel_edp_panel_vdd_on(intel_dp);
4be73780 1983 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 1984 }
1985
efa80add
S		 1986 if (IS_SKYLAKE(dev))
1987 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1988 DPLL_CTRL2_DDI_CLK_OFF(port)));
1ab23380 1989 else if (INTEL_INFO(dev)->gen < 9)
efa80add 1990 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
6441ab5f
PZ		 1991}
1992
00c09d70 1993static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 1994{
6547fef8 1995 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1996 struct drm_crtc *crtc = encoder->crtc;
1997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 1998 struct drm_device *dev = encoder->dev;
72662e10 1999 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 2000 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2001 int type = intel_encoder->type;
72662e10 2002
6547fef8 2003 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 2004 struct intel_digital_port *intel_dig_port =
2005 enc_to_dig_port(encoder);
2006
6547fef8
PZ		 2007 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2008 * are ignored so nothing special needs to be done besides
2009 * enabling the port.
2010 */
876a8cdf 2011 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 2012 intel_dig_port->saved_port_bits |
2013 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 2014 } else if (type == INTEL_OUTPUT_EDP) {
2015 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2016
23f08d83 2017 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 2018 intel_dp_stop_link_train(intel_dp);
2019
4be73780 2020 intel_edp_backlight_on(intel_dp);
0bc12bcb 2021 intel_psr_enable(intel_dp);
c395578e 2022 intel_edp_drrs_enable(intel_dp);
6547fef8 2023 }
7b9f35a6 2024
6e3c9717 2025 if (intel_crtc->config->has_audio) {
d45a0bf5 2026 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 2027 intel_audio_codec_enable(intel_encoder);
7b9f35a6 2028 }
5ab432ef
DV		 2029}
2030
00c09d70 2031static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 2032{
d6c50ff8 2033 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2034 struct drm_crtc *crtc = encoder->crtc;
2035 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 2036 int type = intel_encoder->type;
7b9f35a6
WX		 2037 struct drm_device *dev = encoder->dev;
2038 struct drm_i915_private *dev_priv = dev->dev_private;
d6c50ff8 2039
6e3c9717 2040 if (intel_crtc->config->has_audio) {
69bfe1a9 2041 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 2042 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2043 }
2831d842 2044
d6c50ff8
PZ		 2045 if (type == INTEL_OUTPUT_EDP) {
2046 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2047
c395578e 2048 intel_edp_drrs_disable(intel_dp);
0bc12bcb 2049 intel_psr_disable(intel_dp);
4be73780 2050 intel_edp_backlight_off(intel_dp);
d6c50ff8 2051 }
72662e10 2052}
79f689aa 2053
e0b01be4
DV		 2054static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
2055 struct intel_shared_dpll *pll)
2056{
3e369b76 2057 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
e0b01be4
DV		 2058 POSTING_READ(WRPLL_CTL(pll->id));
2059 udelay(20);
2060}
2061
12030431
DV		 2062static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
2063 struct intel_shared_dpll *pll)
2064{
2065 uint32_t val;
2066
2067 val = I915_READ(WRPLL_CTL(pll->id));
12030431
DV		 2068 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2069 POSTING_READ(WRPLL_CTL(pll->id));
2070}
2071
d452c5b6
DV		 2072static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2073 struct intel_shared_dpll *pll,
2074 struct intel_dpll_hw_state *hw_state)
2075{
2076 uint32_t val;
2077
f458ebbc 2078 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
d452c5b6
DV		 2079 return false;
2080
2081 val = I915_READ(WRPLL_CTL(pll->id));
2082 hw_state->wrpll = val;
2083
2084 return val & WRPLL_PLL_ENABLE;
2085}
2086
ca1381b5 2087static const char * const hsw_ddi_pll_names[] = {
9cd86933
DV		 2088 "WRPLL 1",
2089 "WRPLL 2",
2090};
2091
143b307c 2092static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
79f689aa 2093{
9cd86933
DV		 2094 int i;
2095
716c2e55 2096 dev_priv->num_shared_dpll = 2;
9cd86933 2097
716c2e55 2098 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9cd86933
DV		 2099 dev_priv->shared_dplls[i].id = i;
2100 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
12030431 2101 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
e0b01be4 2102 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
d452c5b6
DV		 2103 dev_priv->shared_dplls[i].get_hw_state =
2104 hsw_ddi_pll_get_hw_state;
9cd86933 2105 }
143b307c
DL		 2106}
2107
d1a2dc78
S		 2108static const char * const skl_ddi_pll_names[] = {
2109 "DPLL 1",
2110 "DPLL 2",
2111 "DPLL 3",
2112};
2113
2114struct skl_dpll_regs {
2115 u32 ctl, cfgcr1, cfgcr2;
2116};
2117
2118/* this array is indexed by the *shared* pll id */
2119static const struct skl_dpll_regs skl_dpll_regs[3] = {
2120 {
2121 /* DPLL 1 */
2122 .ctl = LCPLL2_CTL,
2123 .cfgcr1 = DPLL1_CFGCR1,
2124 .cfgcr2 = DPLL1_CFGCR2,
2125 },
2126 {
2127 /* DPLL 2 */
2128 .ctl = WRPLL_CTL1,
2129 .cfgcr1 = DPLL2_CFGCR1,
2130 .cfgcr2 = DPLL2_CFGCR2,
2131 },
2132 {
2133 /* DPLL 3 */
2134 .ctl = WRPLL_CTL2,
2135 .cfgcr1 = DPLL3_CFGCR1,
2136 .cfgcr2 = DPLL3_CFGCR2,
2137 },
2138};
2139
2140static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2141 struct intel_shared_dpll *pll)
2142{
2143 uint32_t val;
2144 unsigned int dpll;
2145 const struct skl_dpll_regs *regs = skl_dpll_regs;
2146
2147 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2148 dpll = pll->id + 1;
2149
2150 val = I915_READ(DPLL_CTRL1);
2151
2152 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
71cd8423 2153 DPLL_CTRL1_LINK_RATE_MASK(dpll));
d1a2dc78
S		 2154 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2155
2156 I915_WRITE(DPLL_CTRL1, val);
2157 POSTING_READ(DPLL_CTRL1);
2158
2159 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2160 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2161 POSTING_READ(regs[pll->id].cfgcr1);
2162 POSTING_READ(regs[pll->id].cfgcr2);
2163
2164 /* the enable bit is always bit 31 */
2165 I915_WRITE(regs[pll->id].ctl,
2166 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2167
2168 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2169 DRM_ERROR("DPLL %d not locked\n", dpll);
2170}
2171
2172static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2173 struct intel_shared_dpll *pll)
2174{
2175 const struct skl_dpll_regs *regs = skl_dpll_regs;
2176
2177 /* the enable bit is always bit 31 */
2178 I915_WRITE(regs[pll->id].ctl,
2179 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2180 POSTING_READ(regs[pll->id].ctl);
2181}
2182
2183static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2184 struct intel_shared_dpll *pll,
2185 struct intel_dpll_hw_state *hw_state)
2186{
2187 uint32_t val;
2188 unsigned int dpll;
2189 const struct skl_dpll_regs *regs = skl_dpll_regs;
2190
2191 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2192 return false;
2193
2194 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2195 dpll = pll->id + 1;
2196
2197 val = I915_READ(regs[pll->id].ctl);
2198 if (!(val & LCPLL_PLL_ENABLE))
2199 return false;
2200
2201 val = I915_READ(DPLL_CTRL1);
2202 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2203
2204 /* avoid reading back stale values if HDMI mode is not enabled */
2205 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2206 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2207 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2208 }
2209
2210 return true;
2211}
2212
2213static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2214{
2215 int i;
2216
2217 dev_priv->num_shared_dpll = 3;
2218
2219 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2220 dev_priv->shared_dplls[i].id = i;
2221 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2222 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2223 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2224 dev_priv->shared_dplls[i].get_hw_state =
2225 skl_ddi_pll_get_hw_state;
2226 }
2227}
2228
5c6706e5
VK		 2229static void broxton_phy_init(struct drm_i915_private *dev_priv,
2230 enum dpio_phy phy)
2231{
2232 enum port port;
2233 uint32_t val;
2234
2235 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2236 val |= GT_DISPLAY_POWER_ON(phy);
2237 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2238
2239 /* Considering 10ms timeout until BSpec is updated */
2240 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2241 DRM_ERROR("timeout during PHY%d power on\n", phy);
2242
2243 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2244 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2245 int lane;
2246
2247 for (lane = 0; lane < 4; lane++) {
2248 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2249 /*
2250 * Note that on CHV this flag is called UPAR, but has
2251 * the same function.
2252 */
2253 val &= ~LATENCY_OPTIM;
2254 if (lane != 1)
2255 val |= LATENCY_OPTIM;
2256
2257 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2258 }
2259 }
2260
2261 /* Program PLL Rcomp code offset */
2262 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2263 val &= ~IREF0RC_OFFSET_MASK;
2264 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2265 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2266
2267 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2268 val &= ~IREF1RC_OFFSET_MASK;
2269 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2270 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2271
2272 /* Program power gating */
2273 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2274 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2275 SUS_CLK_CONFIG;
2276 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2277
2278 if (phy == DPIO_PHY0) {
2279 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2280 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2281 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2282 }
2283
2284 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2285 val &= ~OCL2_LDOFUSE_PWR_DIS;
2286 /*
2287 * On PHY1 disable power on the second channel, since no port is
2288 * connected there. On PHY0 both channels have a port, so leave it
2289 * enabled.
2290 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2291 * power down the second channel on PHY0 as well.
2292 */
2293 if (phy == DPIO_PHY1)
2294 val |= OCL2_LDOFUSE_PWR_DIS;
2295 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2296
2297 if (phy == DPIO_PHY0) {
2298 uint32_t grc_code;
2299 /*
2300 * PHY0 isn't connected to an RCOMP resistor so copy over
2301 * the corresponding calibrated value from PHY1, and disable
2302 * the automatic calibration on PHY0.
2303 */
2304 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2305 10))
2306 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2307
2308 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2309 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2310 grc_code = val << GRC_CODE_FAST_SHIFT |
2311 val << GRC_CODE_SLOW_SHIFT |
2312 val;
2313 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2314
2315 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2316 val |= GRC_DIS | GRC_RDY_OVRD;
2317 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2318 }
2319
2320 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2321 val |= COMMON_RESET_DIS;
2322 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2323}
2324
2325void broxton_ddi_phy_init(struct drm_device *dev)
2326{
2327 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2328 broxton_phy_init(dev->dev_private, DPIO_PHY1);
2329 broxton_phy_init(dev->dev_private, DPIO_PHY0);
2330}
2331
2332static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2333 enum dpio_phy phy)
2334{
2335 uint32_t val;
2336
2337 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2338 val &= ~COMMON_RESET_DIS;
2339 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2340}
2341
2342void broxton_ddi_phy_uninit(struct drm_device *dev)
2343{
2344 struct drm_i915_private *dev_priv = dev->dev_private;
2345
2346 broxton_phy_uninit(dev_priv, DPIO_PHY1);
2347 broxton_phy_uninit(dev_priv, DPIO_PHY0);
2348
2349 /* FIXME: do this in broxton_phy_uninit per phy */
2350 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2351}
2352
dfb82408
S		 2353static const char * const bxt_ddi_pll_names[] = {
2354 "PORT PLL A",
2355 "PORT PLL B",
2356 "PORT PLL C",
2357};
2358
2359static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2360 struct intel_shared_dpll *pll)
2361{
2362 uint32_t temp;
2363 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2364
2365 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2366 temp &= ~PORT_PLL_REF_SEL;
2367 /* Non-SSC reference */
2368 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2369
2370 /* Disable 10 bit clock */
2371 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2372 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2373 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2374
2375 /* Write P1 & P2 */
2376 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2377 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2378 temp |= pll->config.hw_state.ebb0;
2379 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2380
2381 /* Write M2 integer */
2382 temp = I915_READ(BXT_PORT_PLL(port, 0));
2383 temp &= ~PORT_PLL_M2_MASK;
2384 temp |= pll->config.hw_state.pll0;
2385 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2386
2387 /* Write N */
2388 temp = I915_READ(BXT_PORT_PLL(port, 1));
2389 temp &= ~PORT_PLL_N_MASK;
2390 temp |= pll->config.hw_state.pll1;
2391 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2392
2393 /* Write M2 fraction */
2394 temp = I915_READ(BXT_PORT_PLL(port, 2));
2395 temp &= ~PORT_PLL_M2_FRAC_MASK;
2396 temp |= pll->config.hw_state.pll2;
2397 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2398
2399 /* Write M2 fraction enable */
2400 temp = I915_READ(BXT_PORT_PLL(port, 3));
2401 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2402 temp |= pll->config.hw_state.pll3;
2403 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2404
2405 /* Write coeff */
2406 temp = I915_READ(BXT_PORT_PLL(port, 6));
2407 temp &= ~PORT_PLL_PROP_COEFF_MASK;
2408 temp &= ~PORT_PLL_INT_COEFF_MASK;
2409 temp &= ~PORT_PLL_GAIN_CTL_MASK;
2410 temp |= pll->config.hw_state.pll6;
2411 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2412
2413 /* Write calibration val */
2414 temp = I915_READ(BXT_PORT_PLL(port, 8));
2415 temp &= ~PORT_PLL_TARGET_CNT_MASK;
2416 temp |= pll->config.hw_state.pll8;
2417 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2418
b6dc71f3
VK		 2419 temp = I915_READ(BXT_PORT_PLL(port, 9));
2420 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
2421 temp |= (5 << 1);
2422 I915_WRITE(BXT_PORT_PLL(port, 9), temp);
2423
2424 temp = I915_READ(BXT_PORT_PLL(port, 10));
2425 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2426 temp &= ~PORT_PLL_DCO_AMP_MASK;
2427 temp |= pll->config.hw_state.pll10;
2428 I915_WRITE(BXT_PORT_PLL(port, 10), temp);
dfb82408
S		 2429
2430 /* Recalibrate with new settings */
2431 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2432 temp |= PORT_PLL_RECALIBRATE;
2433 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2434 /* Enable 10 bit clock */
2435 temp |= PORT_PLL_10BIT_CLK_ENABLE;
2436 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2437
2438 /* Enable PLL */
2439 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2440 temp |= PORT_PLL_ENABLE;
2441 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2442 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2443
2444 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2445 PORT_PLL_LOCK), 200))
2446 DRM_ERROR("PLL %d not locked\n", port);
2447
2448 /*
2449 * While we write to the group register to program all lanes at once we
2450 * can read only lane registers and we pick lanes 0/1 for that.
2451 */
2452 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2453 temp &= ~LANE_STAGGER_MASK;
2454 temp &= ~LANESTAGGER_STRAP_OVRD;
2455 temp |= pll->config.hw_state.pcsdw12;
2456 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2457}
2458
2459static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2460 struct intel_shared_dpll *pll)
2461{
2462 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2463 uint32_t temp;
2464
2465 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2466 temp &= ~PORT_PLL_ENABLE;
2467 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2468 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2469}
2470
2471static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2472 struct intel_shared_dpll *pll,
2473 struct intel_dpll_hw_state *hw_state)
2474{
2475 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2476 uint32_t val;
2477
2478 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2479 return false;
2480
2481 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2482 if (!(val & PORT_PLL_ENABLE))
2483 return false;
2484
2485 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
2486 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
2487 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
2488 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
2489 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
2490 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
2491 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
b6dc71f3 2492 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
dfb82408
S		 2493 /*
2494 * While we write to the group register to program all lanes at once we
2495 * can read only lane registers. We configure all lanes the same way, so
2496 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2497 */
2498 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2499 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port) != hw_state->pcsdw12))
2500 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2501 hw_state->pcsdw12,
2502 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
2503
2504 return true;
2505}
2506
2507static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2508{
2509 int i;
2510
2511 dev_priv->num_shared_dpll = 3;
2512
2513 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2514 dev_priv->shared_dplls[i].id = i;
2515 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2516 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2517 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2518 dev_priv->shared_dplls[i].get_hw_state =
2519 bxt_ddi_pll_get_hw_state;
2520 }
2521}
2522
143b307c
DL		 2523void intel_ddi_pll_init(struct drm_device *dev)
2524{
2525 struct drm_i915_private *dev_priv = dev->dev_private;
2526 uint32_t val = I915_READ(LCPLL_CTL);
5d96d8af 2527 int cdclk_freq;
143b307c 2528
d1a2dc78
S		 2529 if (IS_SKYLAKE(dev))
2530 skl_shared_dplls_init(dev_priv);
dfb82408
S		 2531 else if (IS_BROXTON(dev))
2532 bxt_shared_dplls_init(dev_priv);
d1a2dc78
S		 2533 else
2534 hsw_shared_dplls_init(dev_priv);
79f689aa 2535
5d96d8af
DL		 2536 cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
2537 DRM_DEBUG_KMS("CDCLK running at %dKHz\n", cdclk_freq);
79f689aa 2538
121643c2 2539 if (IS_SKYLAKE(dev)) {
5d96d8af 2540 dev_priv->skl_boot_cdclk = cdclk_freq;
121643c2
S		 2541 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
2542 DRM_ERROR("LCPLL1 is disabled\n");
5d96d8af
DL		 2543 else
2544 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
f8437dd1
VK		 2545 } else if (IS_BROXTON(dev)) {
2546 broxton_init_cdclk(dev);
5c6706e5 2547 broxton_ddi_phy_init(dev);
121643c2
S		 2548 } else {
2549 /*
2550 * The LCPLL register should be turned on by the BIOS. For now
2551 * let's just check its state and print errors in case
2552 * something is wrong. Don't even try to turn it on.
2553 */
2554
2555 if (val & LCPLL_CD_SOURCE_FCLK)
2556 DRM_ERROR("CDCLK source is not LCPLL\n");
79f689aa 2557
121643c2
S		 2558 if (val & LCPLL_PLL_DISABLE)
2559 DRM_ERROR("LCPLL is disabled\n");
2560 }
79f689aa 2561}
c19b0669
PZ		 2562
2563void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
2564{
174edf1f
PZ		 2565 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2566 struct intel_dp *intel_dp = &intel_dig_port->dp;
c19b0669 2567 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
174edf1f 2568 enum port port = intel_dig_port->port;
c19b0669 2569 uint32_t val;
f3e227df 2570 bool wait = false;
c19b0669
PZ		 2571
2572 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2573 val = I915_READ(DDI_BUF_CTL(port));
2574 if (val & DDI_BUF_CTL_ENABLE) {
2575 val &= ~DDI_BUF_CTL_ENABLE;
2576 I915_WRITE(DDI_BUF_CTL(port), val);
2577 wait = true;
2578 }
2579
2580 val = I915_READ(DP_TP_CTL(port));
2581 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2582 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2583 I915_WRITE(DP_TP_CTL(port), val);
2584 POSTING_READ(DP_TP_CTL(port));
2585
2586 if (wait)
2587 intel_wait_ddi_buf_idle(dev_priv, port);
2588 }
2589
0e32b39c 2590 val = DP_TP_CTL_ENABLE |
c19b0669 2591 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 2592 if (intel_dp->is_mst)
2593 val |= DP_TP_CTL_MODE_MST;
2594 else {
2595 val |= DP_TP_CTL_MODE_SST;
2596 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2597 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2598 }
c19b0669
PZ		 2599 I915_WRITE(DP_TP_CTL(port), val);
2600 POSTING_READ(DP_TP_CTL(port));
2601
2602 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2603 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2604 POSTING_READ(DDI_BUF_CTL(port));
2605
2606 udelay(600);
2607}
00c09d70 2608
1ad960f2
PZ		 2609void intel_ddi_fdi_disable(struct drm_crtc *crtc)
2610{
2611 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2612 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2613 uint32_t val;
2614
2615 intel_ddi_post_disable(intel_encoder);
2616
2617 val = I915_READ(_FDI_RXA_CTL);
2618 val &= ~FDI_RX_ENABLE;
2619 I915_WRITE(_FDI_RXA_CTL, val);
2620
2621 val = I915_READ(_FDI_RXA_MISC);
2622 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2623 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2624 I915_WRITE(_FDI_RXA_MISC, val);
2625
2626 val = I915_READ(_FDI_RXA_CTL);
2627 val &= ~FDI_PCDCLK;
2628 I915_WRITE(_FDI_RXA_CTL, val);
2629
2630 val = I915_READ(_FDI_RXA_CTL);
2631 val &= ~FDI_RX_PLL_ENABLE;
2632 I915_WRITE(_FDI_RXA_CTL, val);
2633}
2634
6801c18c 2635void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 2636 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2637{
2638 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
2639 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 2640 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 2641 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 2642 u32 temp, flags = 0;
2643
2644 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2645 if (temp & TRANS_DDI_PHSYNC)
2646 flags |= DRM_MODE_FLAG_PHSYNC;
2647 else
2648 flags |= DRM_MODE_FLAG_NHSYNC;
2649 if (temp & TRANS_DDI_PVSYNC)
2650 flags |= DRM_MODE_FLAG_PVSYNC;
2651 else
2652 flags |= DRM_MODE_FLAG_NVSYNC;
2653
2d112de7 2654 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 2655
2656 switch (temp & TRANS_DDI_BPC_MASK) {
2657 case TRANS_DDI_BPC_6:
2658 pipe_config->pipe_bpp = 18;
2659 break;
2660 case TRANS_DDI_BPC_8:
2661 pipe_config->pipe_bpp = 24;
2662 break;
2663 case TRANS_DDI_BPC_10:
2664 pipe_config->pipe_bpp = 30;
2665 break;
2666 case TRANS_DDI_BPC_12:
2667 pipe_config->pipe_bpp = 36;
2668 break;
2669 default:
2670 break;
2671 }
eb14cb74
VS		 2672
2673 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2674 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 2675 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 2676 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2677
2678 if (intel_hdmi->infoframe_enabled(&encoder->base))
2679 pipe_config->has_infoframe = true;
cbc572a9 2680 break;
eb14cb74
VS		 2681 case TRANS_DDI_MODE_SELECT_DVI:
2682 case TRANS_DDI_MODE_SELECT_FDI:
2683 break;
2684 case TRANS_DDI_MODE_SELECT_DP_SST:
2685 case TRANS_DDI_MODE_SELECT_DP_MST:
2686 pipe_config->has_dp_encoder = true;
2687 intel_dp_get_m_n(intel_crtc, pipe_config);
2688 break;
2689 default:
2690 break;
2691 }
10214420 2692
f458ebbc 2693 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
a60551b1 2694 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
82910ac6 2695 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
a60551b1
PZ		 2696 pipe_config->has_audio = true;
2697 }
9ed109a7 2698
10214420
DV		 2699 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
2700 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2701 /*
2702 * This is a big fat ugly hack.
2703 *
2704 * Some machines in UEFI boot mode provide us a VBT that has 18
2705 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2706 * unknown we fail to light up. Yet the same BIOS boots up with
2707 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2708 * max, not what it tells us to use.
2709 *
2710 * Note: This will still be broken if the eDP panel is not lit
2711 * up by the BIOS, and thus we can't get the mode at module
2712 * load.
2713 */
2714 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2715 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2716 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2717 }
11578553 2718
22606a18 2719 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 2720}
2721
00c09d70
PZ		 2722static void intel_ddi_destroy(struct drm_encoder *encoder)
2723{
2724 /* HDMI has nothing special to destroy, so we can go with this. */
2725 intel_dp_encoder_destroy(encoder);
2726}
2727
5bfe2ac0 2728static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 2729 struct intel_crtc_state *pipe_config)
00c09d70 2730{
5bfe2ac0 2731 int type = encoder->type;
eccb140b 2732 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 2733
5bfe2ac0 2734 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 2735
eccb140b
DV		 2736 if (port == PORT_A)
2737 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2738
00c09d70 2739 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 2740 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 2741 else
5bfe2ac0 2742 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 2743}
2744
2745static const struct drm_encoder_funcs intel_ddi_funcs = {
2746 .destroy = intel_ddi_destroy,
2747};
2748
4a28ae58
PZ		 2749static struct intel_connector *
2750intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2751{
2752 struct intel_connector *connector;
2753 enum port port = intel_dig_port->port;
2754
9bdbd0b9 2755 connector = intel_connector_alloc();
4a28ae58
PZ		 2756 if (!connector)
2757 return NULL;
2758
2759 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2760 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2761 kfree(connector);
2762 return NULL;
2763 }
2764
2765 return connector;
2766}
2767
2768static struct intel_connector *
2769intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2770{
2771 struct intel_connector *connector;
2772 enum port port = intel_dig_port->port;
2773
9bdbd0b9 2774 connector = intel_connector_alloc();
4a28ae58
PZ		 2775 if (!connector)
2776 return NULL;
2777
2778 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2779 intel_hdmi_init_connector(intel_dig_port, connector);
2780
2781 return connector;
2782}
2783
00c09d70
PZ		 2784void intel_ddi_init(struct drm_device *dev, enum port port)
2785{
876a8cdf 2786 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 2787 struct intel_digital_port *intel_dig_port;
2788 struct intel_encoder *intel_encoder;
2789 struct drm_encoder *encoder;
311a2094
PZ		 2790 bool init_hdmi, init_dp;
2791
2792 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2793 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2794 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2795 if (!init_dp && !init_hdmi) {
f68d697e 2796 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
311a2094
PZ		 2797 port_name(port));
2798 init_hdmi = true;
2799 init_dp = true;
2800 }
00c09d70 2801
b14c5679 2802 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 2803 if (!intel_dig_port)
2804 return;
2805
00c09d70
PZ		 2806 intel_encoder = &intel_dig_port->base;
2807 encoder = &intel_encoder->base;
2808
2809 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
2810 DRM_MODE_ENCODER_TMDS);
00c09d70 2811
5bfe2ac0 2812 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 2813 intel_encoder->enable = intel_enable_ddi;
2814 intel_encoder->pre_enable = intel_ddi_pre_enable;
2815 intel_encoder->disable = intel_disable_ddi;
2816 intel_encoder->post_disable = intel_ddi_post_disable;
2817 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 2818 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 2819
2820 intel_dig_port->port = port;
bcf53de4
SM		 2821 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2822 (DDI_BUF_PORT_REVERSAL |
2823 DDI_A_4_LANES);
00c09d70
PZ		 2824
2825 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 2826 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 2827 intel_encoder->cloneable = 0;
00c09d70 2828
f68d697e
CW		 2829 if (init_dp) {
2830 if (!intel_ddi_init_dp_connector(intel_dig_port))
2831 goto err;
13cf5504 2832
f68d697e 2833 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5fcece80 2834 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 2835 }
21a8e6a4 2836
311a2094
PZ		 2837 /* In theory we don't need the encoder->type check, but leave it just in
2838 * case we have some really bad VBTs... */
f68d697e
CW		 2839 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2840 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2841 goto err;
21a8e6a4 2842 }
f68d697e
CW		 2843
2844 return;
2845
2846err:
2847 drm_encoder_cleanup(encoder);
2848 kfree(intel_dig_port);
00c09d70 2849}
Linux kernel - Deliverables
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