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drm/i915/skl: Remove unnecessary () used with abs_diff()
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_ddi.c
CommitLineData
45244b87
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
28#include "i915_drv.h"
29#include "intel_drv.h"
30
10122051
JN		 31struct ddi_buf_trans {
32 u32 trans1; /* balance leg enable, de-emph level */
33 u32 trans2; /* vref sel, vswing */
34};
35
45244b87
ED		 36/* HDMI/DVI modes ignore everything but the last 2 items. So we share
37 * them for both DP and FDI transports, allowing those ports to
38 * automatically adapt to HDMI connections as well
39 */
10122051
JN		 40static const struct ddi_buf_trans hsw_ddi_translations_dp[] = {
41 { 0x00FFFFFF, 0x0006000E },
42 { 0x00D75FFF, 0x0005000A },
43 { 0x00C30FFF, 0x00040006 },
44 { 0x80AAAFFF, 0x000B0000 },
45 { 0x00FFFFFF, 0x0005000A },
46 { 0x00D75FFF, 0x000C0004 },
47 { 0x80C30FFF, 0x000B0000 },
48 { 0x00FFFFFF, 0x00040006 },
49 { 0x80D75FFF, 0x000B0000 },
45244b87
ED		 50};
51
10122051
JN		 52static const struct ddi_buf_trans hsw_ddi_translations_fdi[] = {
53 { 0x00FFFFFF, 0x0007000E },
54 { 0x00D75FFF, 0x000F000A },
55 { 0x00C30FFF, 0x00060006 },
56 { 0x00AAAFFF, 0x001E0000 },
57 { 0x00FFFFFF, 0x000F000A },
58 { 0x00D75FFF, 0x00160004 },
59 { 0x00C30FFF, 0x001E0000 },
60 { 0x00FFFFFF, 0x00060006 },
61 { 0x00D75FFF, 0x001E0000 },
6acab15a
PZ		 62};
63
10122051
JN		 64static const struct ddi_buf_trans hsw_ddi_translations_hdmi[] = {
65 /* Idx NT mV d T mV d db */
66 { 0x00FFFFFF, 0x0006000E }, /* 0: 400 400 0 */
67 { 0x00E79FFF, 0x000E000C }, /* 1: 400 500 2 */
68 { 0x00D75FFF, 0x0005000A }, /* 2: 400 600 3.5 */
69 { 0x00FFFFFF, 0x0005000A }, /* 3: 600 600 0 */
70 { 0x00E79FFF, 0x001D0007 }, /* 4: 600 750 2 */
71 { 0x00D75FFF, 0x000C0004 }, /* 5: 600 900 3.5 */
72 { 0x00FFFFFF, 0x00040006 }, /* 6: 800 800 0 */
73 { 0x80E79FFF, 0x00030002 }, /* 7: 800 1000 2 */
74 { 0x00FFFFFF, 0x00140005 }, /* 8: 850 850 0 */
75 { 0x00FFFFFF, 0x000C0004 }, /* 9: 900 900 0 */
76 { 0x00FFFFFF, 0x001C0003 }, /* 10: 950 950 0 */
77 { 0x80FFFFFF, 0x00030002 }, /* 11: 1000 1000 0 */
45244b87
ED		 78};
79
10122051
JN		 80static const struct ddi_buf_trans bdw_ddi_translations_edp[] = {
81 { 0x00FFFFFF, 0x00000012 },
82 { 0x00EBAFFF, 0x00020011 },
83 { 0x00C71FFF, 0x0006000F },
84 { 0x00AAAFFF, 0x000E000A },
85 { 0x00FFFFFF, 0x00020011 },
86 { 0x00DB6FFF, 0x0005000F },
87 { 0x00BEEFFF, 0x000A000C },
88 { 0x00FFFFFF, 0x0005000F },
89 { 0x00DB6FFF, 0x000A000C },
300644c7
PZ		 90};
91
10122051
JN		 92static const struct ddi_buf_trans bdw_ddi_translations_dp[] = {
93 { 0x00FFFFFF, 0x0007000E },
94 { 0x00D75FFF, 0x000E000A },
95 { 0x00BEFFFF, 0x00140006 },
96 { 0x80B2CFFF, 0x001B0002 },
97 { 0x00FFFFFF, 0x000E000A },
17b523ba 98 { 0x00DB6FFF, 0x00160005 },
6805b2a7 99 { 0x80C71FFF, 0x001A0002 },
10122051
JN		 100 { 0x00F7DFFF, 0x00180004 },
101 { 0x80D75FFF, 0x001B0002 },
e58623cb
AR		 102};
103
10122051
JN		 104static const struct ddi_buf_trans bdw_ddi_translations_fdi[] = {
105 { 0x00FFFFFF, 0x0001000E },
106 { 0x00D75FFF, 0x0004000A },
107 { 0x00C30FFF, 0x00070006 },
108 { 0x00AAAFFF, 0x000C0000 },
109 { 0x00FFFFFF, 0x0004000A },
110 { 0x00D75FFF, 0x00090004 },
111 { 0x00C30FFF, 0x000C0000 },
112 { 0x00FFFFFF, 0x00070006 },
113 { 0x00D75FFF, 0x000C0000 },
e58623cb
AR		 114};
115
10122051
JN		 116static const struct ddi_buf_trans bdw_ddi_translations_hdmi[] = {
117 /* Idx NT mV d T mV df db */
118 { 0x00FFFFFF, 0x0007000E }, /* 0: 400 400 0 */
119 { 0x00D75FFF, 0x000E000A }, /* 1: 400 600 3.5 */
120 { 0x00BEFFFF, 0x00140006 }, /* 2: 400 800 6 */
121 { 0x00FFFFFF, 0x0009000D }, /* 3: 450 450 0 */
122 { 0x00FFFFFF, 0x000E000A }, /* 4: 600 600 0 */
123 { 0x00D7FFFF, 0x00140006 }, /* 5: 600 800 2.5 */
124 { 0x80CB2FFF, 0x001B0002 }, /* 6: 600 1000 4.5 */
125 { 0x00FFFFFF, 0x00140006 }, /* 7: 800 800 0 */
126 { 0x80E79FFF, 0x001B0002 }, /* 8: 800 1000 2 */
127 { 0x80FFFFFF, 0x001B0002 }, /* 9: 1000 1000 0 */
a26aa8ba
DL		 128};
129
7f88e3af 130static const struct ddi_buf_trans skl_ddi_translations_dp[] = {
6c930688
DL		 131 { 0x00000018, 0x000000a2 },
132 { 0x00004014, 0x0000009B },
7f88e3af 133 { 0x00006012, 0x00000088 },
6c930688
DL		 134 { 0x00008010, 0x00000087 },
135 { 0x00000018, 0x0000009B },
7f88e3af 136 { 0x00004014, 0x00000088 },
6c930688 137 { 0x00006012, 0x00000087 },
7f88e3af 138 { 0x00000018, 0x00000088 },
6c930688 139 { 0x00004014, 0x00000087 },
7f88e3af
DL		 140};
141
7ad14a29
SJ		 142/* eDP 1.4 low vswing translation parameters */
143static const struct ddi_buf_trans skl_ddi_translations_edp[] = {
144 { 0x00000018, 0x000000a8 },
145 { 0x00002016, 0x000000ab },
146 { 0x00006012, 0x000000a2 },
147 { 0x00008010, 0x00000088 },
148 { 0x00000018, 0x000000ab },
149 { 0x00004014, 0x000000a2 },
150 { 0x00006012, 0x000000a6 },
151 { 0x00000018, 0x000000a2 },
152 { 0x00005013, 0x0000009c },
153 { 0x00000018, 0x00000088 },
154};
155
156
7f88e3af 157static const struct ddi_buf_trans skl_ddi_translations_hdmi[] = {
b7192a56
SJ		 158 { 0x00000018, 0x000000ac },
159 { 0x00005012, 0x0000009d },
160 { 0x00007011, 0x00000088 },
161 { 0x00000018, 0x000000a1 },
162 { 0x00000018, 0x00000098 },
163 { 0x00004013, 0x00000088 },
164 { 0x00006012, 0x00000087 },
165 { 0x00000018, 0x000000df },
166 { 0x00003015, 0x00000087 },
167 { 0x00003015, 0x000000c7 },
168 { 0x00000018, 0x000000c7 },
7f88e3af
DL		 169};
170
96fb9f9b
VK		 171struct bxt_ddi_buf_trans {
172 u32 margin; /* swing value */
173 u32 scale; /* scale value */
174 u32 enable; /* scale enable */
175 u32 deemphasis;
176 bool default_index; /* true if the entry represents default value */
177};
178
179/* BSpec does not define separate vswing/pre-emphasis values for eDP.
180 * Using DP values for eDP as well.
181 */
182static const struct bxt_ddi_buf_trans bxt_ddi_translations_dp[] = {
183 /* Idx NT mV diff db */
184 { 52, 0, 0, 128, true }, /* 0: 400 0 */
185 { 78, 0, 0, 85, false }, /* 1: 400 3.5 */
186 { 104, 0, 0, 64, false }, /* 2: 400 6 */
187 { 154, 0, 0, 43, false }, /* 3: 400 9.5 */
188 { 77, 0, 0, 128, false }, /* 4: 600 0 */
189 { 116, 0, 0, 85, false }, /* 5: 600 3.5 */
190 { 154, 0, 0, 64, false }, /* 6: 600 6 */
191 { 102, 0, 0, 128, false }, /* 7: 800 0 */
192 { 154, 0, 0, 85, false }, /* 8: 800 3.5 */
193 { 154, 0x9A, 1, 128, false }, /* 9: 1200 0 */
194};
195
196/* BSpec has 2 recommended values - entries 0 and 8.
197 * Using the entry with higher vswing.
198 */
199static const struct bxt_ddi_buf_trans bxt_ddi_translations_hdmi[] = {
200 /* Idx NT mV diff db */
201 { 52, 0, 0, 128, false }, /* 0: 400 0 */
202 { 52, 0, 0, 85, false }, /* 1: 400 3.5 */
203 { 52, 0, 0, 64, false }, /* 2: 400 6 */
204 { 42, 0, 0, 43, false }, /* 3: 400 9.5 */
205 { 77, 0, 0, 128, false }, /* 4: 600 0 */
206 { 77, 0, 0, 85, false }, /* 5: 600 3.5 */
207 { 77, 0, 0, 64, false }, /* 6: 600 6 */
208 { 102, 0, 0, 128, false }, /* 7: 800 0 */
209 { 102, 0, 0, 85, false }, /* 8: 800 3.5 */
210 { 154, 0x9A, 1, 128, true }, /* 9: 1200 0 */
211};
212
a1e6ad66
ID		 213static void ddi_get_encoder_port(struct intel_encoder *intel_encoder,
214 struct intel_digital_port **dig_port,
215 enum port *port)
fc914639 216{
0bdee30e 217 struct drm_encoder *encoder = &intel_encoder->base;
fc914639
PZ		 218 int type = intel_encoder->type;
219
0e32b39c 220 if (type == INTEL_OUTPUT_DP_MST) {
a1e6ad66
ID		 221 *dig_port = enc_to_mst(encoder)->primary;
222 *port = (*dig_port)->port;
0e32b39c 223 } else if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP ||
00c09d70 224 type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) {
a1e6ad66
ID		 225 *dig_port = enc_to_dig_port(encoder);
226 *port = (*dig_port)->port;
fc914639 227 } else if (type == INTEL_OUTPUT_ANALOG) {
a1e6ad66
ID		 228 *dig_port = NULL;
229 *port = PORT_E;
fc914639
PZ		 230 } else {
231 DRM_ERROR("Invalid DDI encoder type %d\n", type);
232 BUG();
233 }
234}
235
a1e6ad66
ID		 236enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder)
237{
238 struct intel_digital_port *dig_port;
239 enum port port;
240
241 ddi_get_encoder_port(intel_encoder, &dig_port, &port);
242
243 return port;
244}
245
ce3b7e9b
DL		 246static bool
247intel_dig_port_supports_hdmi(const struct intel_digital_port *intel_dig_port)
248{
249 return intel_dig_port->hdmi.hdmi_reg;
250}
251
e58623cb
AR		 252/*
253 * Starting with Haswell, DDI port buffers must be programmed with correct
254 * values in advance. The buffer values are different for FDI and DP modes,
45244b87
ED		 255 * but the HDMI/DVI fields are shared among those. So we program the DDI
256 * in either FDI or DP modes only, as HDMI connections will work with both
257 * of those
258 */
faa0cdbe
ID		 259static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port,
260 bool supports_hdmi)
45244b87
ED		 261{
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 u32 reg;
7ff44670 264 int i, n_hdmi_entries, n_dp_entries, n_edp_entries, hdmi_default_entry,
7ad14a29 265 size;
6acab15a 266 int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift;
10122051
JN		 267 const struct ddi_buf_trans *ddi_translations_fdi;
268 const struct ddi_buf_trans *ddi_translations_dp;
269 const struct ddi_buf_trans *ddi_translations_edp;
270 const struct ddi_buf_trans *ddi_translations_hdmi;
271 const struct ddi_buf_trans *ddi_translations;
e58623cb 272
96fb9f9b 273 if (IS_BROXTON(dev)) {
faa0cdbe 274 if (!supports_hdmi)
96fb9f9b
VK		 275 return;
276
277 /* Vswing programming for HDMI */
278 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
279 INTEL_OUTPUT_HDMI);
280 return;
281 } else if (IS_SKYLAKE(dev)) {
7f88e3af
DL		 282 ddi_translations_fdi = NULL;
283 ddi_translations_dp = skl_ddi_translations_dp;
7ad14a29 284 n_dp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
9e458034 285 if (dev_priv->edp_low_vswing) {
7ad14a29
SJ		 286 ddi_translations_edp = skl_ddi_translations_edp;
287 n_edp_entries = ARRAY_SIZE(skl_ddi_translations_edp);
288 } else {
289 ddi_translations_edp = skl_ddi_translations_dp;
290 n_edp_entries = ARRAY_SIZE(skl_ddi_translations_dp);
291 }
292
7f88e3af
DL		 293 ddi_translations_hdmi = skl_ddi_translations_hdmi;
294 n_hdmi_entries = ARRAY_SIZE(skl_ddi_translations_hdmi);
b7192a56 295 hdmi_default_entry = 7;
7f88e3af 296 } else if (IS_BROADWELL(dev)) {
e58623cb
AR		 297 ddi_translations_fdi = bdw_ddi_translations_fdi;
298 ddi_translations_dp = bdw_ddi_translations_dp;
300644c7 299 ddi_translations_edp = bdw_ddi_translations_edp;
a26aa8ba 300 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 301 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
302 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 303 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 304 hdmi_default_entry = 7;
e58623cb
AR		 305 } else if (IS_HASWELL(dev)) {
306 ddi_translations_fdi = hsw_ddi_translations_fdi;
307 ddi_translations_dp = hsw_ddi_translations_dp;
300644c7 308 ddi_translations_edp = hsw_ddi_translations_dp;
a26aa8ba 309 ddi_translations_hdmi = hsw_ddi_translations_hdmi;
7ad14a29 310 n_dp_entries = n_edp_entries = ARRAY_SIZE(hsw_ddi_translations_dp);
10122051 311 n_hdmi_entries = ARRAY_SIZE(hsw_ddi_translations_hdmi);
7ff44670 312 hdmi_default_entry = 6;
e58623cb
AR		 313 } else {
314 WARN(1, "ddi translation table missing\n");
300644c7 315 ddi_translations_edp = bdw_ddi_translations_dp;
e58623cb
AR		 316 ddi_translations_fdi = bdw_ddi_translations_fdi;
317 ddi_translations_dp = bdw_ddi_translations_dp;
a26aa8ba 318 ddi_translations_hdmi = bdw_ddi_translations_hdmi;
7ad14a29
SJ		 319 n_edp_entries = ARRAY_SIZE(bdw_ddi_translations_edp);
320 n_dp_entries = ARRAY_SIZE(bdw_ddi_translations_dp);
10122051 321 n_hdmi_entries = ARRAY_SIZE(bdw_ddi_translations_hdmi);
7ff44670 322 hdmi_default_entry = 7;
e58623cb
AR		 323 }
324
300644c7
PZ		 325 switch (port) {
326 case PORT_A:
327 ddi_translations = ddi_translations_edp;
7ad14a29 328 size = n_edp_entries;
300644c7
PZ		 329 break;
330 case PORT_B:
331 case PORT_C:
300644c7 332 ddi_translations = ddi_translations_dp;
7ad14a29 333 size = n_dp_entries;
300644c7 334 break;
77d8d009 335 case PORT_D:
7ad14a29 336 if (intel_dp_is_edp(dev, PORT_D)) {
77d8d009 337 ddi_translations = ddi_translations_edp;
7ad14a29
SJ		 338 size = n_edp_entries;
339 } else {
77d8d009 340 ddi_translations = ddi_translations_dp;
7ad14a29
SJ		 341 size = n_dp_entries;
342 }
77d8d009 343 break;
300644c7 344 case PORT_E:
7f88e3af
DL		 345 if (ddi_translations_fdi)
346 ddi_translations = ddi_translations_fdi;
347 else
348 ddi_translations = ddi_translations_dp;
7ad14a29 349 size = n_dp_entries;
300644c7
PZ		 350 break;
351 default:
352 BUG();
353 }
45244b87 354
7ad14a29 355 for (i = 0, reg = DDI_BUF_TRANS(port); i < size; i++) {
10122051
JN		 356 I915_WRITE(reg, ddi_translations[i].trans1);
357 reg += 4;
358 I915_WRITE(reg, ddi_translations[i].trans2);
45244b87
ED		 359 reg += 4;
360 }
ce4dd49e 361
faa0cdbe 362 if (!supports_hdmi)
ce3b7e9b
DL		 363 return;
364
ce4dd49e
DL		 365 /* Choose a good default if VBT is badly populated */
366 if (hdmi_level == HDMI_LEVEL_SHIFT_UNKNOWN ||
367 hdmi_level >= n_hdmi_entries)
7ff44670 368 hdmi_level = hdmi_default_entry;
ce4dd49e 369
6acab15a 370 /* Entry 9 is for HDMI: */
10122051
JN		 371 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans1);
372 reg += 4;
373 I915_WRITE(reg, ddi_translations_hdmi[hdmi_level].trans2);
374 reg += 4;
45244b87
ED		 375}
376
377/* Program DDI buffers translations for DP. By default, program ports A-D in DP
378 * mode and port E for FDI.
379 */
380void intel_prepare_ddi(struct drm_device *dev)
381{
faa0cdbe 382 struct intel_encoder *intel_encoder;
b403745c 383 bool visited[I915_MAX_PORTS] = { 0, };
45244b87 384
0d536cb4
PZ		 385 if (!HAS_DDI(dev))
386 return;
45244b87 387
faa0cdbe
ID		 388 for_each_intel_encoder(dev, intel_encoder) {
389 struct intel_digital_port *intel_dig_port;
390 enum port port;
391 bool supports_hdmi;
392
393 ddi_get_encoder_port(intel_encoder, &intel_dig_port, &port);
394
395 if (visited[port])
b403745c
DL		 396 continue;
397
faa0cdbe
ID		 398 supports_hdmi = intel_dig_port &&
399 intel_dig_port_supports_hdmi(intel_dig_port);
400
401 intel_prepare_ddi_buffers(dev, port, supports_hdmi);
402 visited[port] = true;
b403745c 403 }
45244b87 404}
c82e4d26 405
248138b5
PZ		 406static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv,
407 enum port port)
408{
409 uint32_t reg = DDI_BUF_CTL(port);
410 int i;
411
3449ca85 412 for (i = 0; i < 16; i++) {
248138b5
PZ		 413 udelay(1);
414 if (I915_READ(reg) & DDI_BUF_IS_IDLE)
415 return;
416 }
417 DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port));
418}
c82e4d26
ED		 419
420/* Starting with Haswell, different DDI ports can work in FDI mode for
421 * connection to the PCH-located connectors. For this, it is necessary to train
422 * both the DDI port and PCH receiver for the desired DDI buffer settings.
423 *
424 * The recommended port to work in FDI mode is DDI E, which we use here. Also,
425 * please note that when FDI mode is active on DDI E, it shares 2 lines with
426 * DDI A (which is used for eDP)
427 */
428
429void hsw_fdi_link_train(struct drm_crtc *crtc)
430{
431 struct drm_device *dev = crtc->dev;
432 struct drm_i915_private *dev_priv = dev->dev_private;
433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
04945641 434 u32 temp, i, rx_ctl_val;
c82e4d26 435
04945641
PZ		 436 /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the
437 * mode set "sequence for CRT port" document:
438 * - TP1 to TP2 time with the default value
439 * - FDI delay to 90h
8693a824
DL		 440 *
441 * WaFDIAutoLinkSetTimingOverrride:hsw
04945641
PZ		 442 */
443 I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
444 FDI_RX_PWRDN_LANE0_VAL(2) |
445 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
446
447 /* Enable the PCH Receiver FDI PLL */
3e68320e 448 rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE |
33d29b14 449 FDI_RX_PLL_ENABLE |
6e3c9717 450 FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
04945641
PZ		 451 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
452 POSTING_READ(_FDI_RXA_CTL);
453 udelay(220);
454
455 /* Switch from Rawclk to PCDclk */
456 rx_ctl_val |= FDI_PCDCLK;
457 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
458
459 /* Configure Port Clock Select */
6e3c9717
ACO		 460 I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config->ddi_pll_sel);
461 WARN_ON(intel_crtc->config->ddi_pll_sel != PORT_CLK_SEL_SPLL);
04945641
PZ		 462
463 /* Start the training iterating through available voltages and emphasis,
464 * testing each value twice. */
10122051 465 for (i = 0; i < ARRAY_SIZE(hsw_ddi_translations_fdi) * 2; i++) {
c82e4d26
ED		 466 /* Configure DP_TP_CTL with auto-training */
467 I915_WRITE(DP_TP_CTL(PORT_E),
468 DP_TP_CTL_FDI_AUTOTRAIN |
469 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
470 DP_TP_CTL_LINK_TRAIN_PAT1 |
471 DP_TP_CTL_ENABLE);
472
876a8cdf
DL		 473 /* Configure and enable DDI_BUF_CTL for DDI E with next voltage.
474 * DDI E does not support port reversal, the functionality is
475 * achieved on the PCH side in FDI_RX_CTL, so no need to set the
476 * port reversal bit */
c82e4d26 477 I915_WRITE(DDI_BUF_CTL(PORT_E),
04945641 478 DDI_BUF_CTL_ENABLE |
6e3c9717 479 ((intel_crtc->config->fdi_lanes - 1) << 1) |
c5fe6a06 480 DDI_BUF_TRANS_SELECT(i / 2));
04945641 481 POSTING_READ(DDI_BUF_CTL(PORT_E));
c82e4d26
ED		 482
483 udelay(600);
484
04945641
PZ		 485 /* Program PCH FDI Receiver TU */
486 I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64));
487
488 /* Enable PCH FDI Receiver with auto-training */
489 rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO;
490 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
491 POSTING_READ(_FDI_RXA_CTL);
492
493 /* Wait for FDI receiver lane calibration */
494 udelay(30);
495
496 /* Unset FDI_RX_MISC pwrdn lanes */
497 temp = I915_READ(_FDI_RXA_MISC);
498 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
499 I915_WRITE(_FDI_RXA_MISC, temp);
500 POSTING_READ(_FDI_RXA_MISC);
501
502 /* Wait for FDI auto training time */
503 udelay(5);
c82e4d26
ED		 504
505 temp = I915_READ(DP_TP_STATUS(PORT_E));
506 if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) {
04945641 507 DRM_DEBUG_KMS("FDI link training done on step %d\n", i);
c82e4d26
ED		 508
509 /* Enable normal pixel sending for FDI */
510 I915_WRITE(DP_TP_CTL(PORT_E),
04945641
PZ		 511 DP_TP_CTL_FDI_AUTOTRAIN |
512 DP_TP_CTL_LINK_TRAIN_NORMAL |
513 DP_TP_CTL_ENHANCED_FRAME_ENABLE |
514 DP_TP_CTL_ENABLE);
c82e4d26 515
04945641 516 return;
c82e4d26 517 }
04945641 518
248138b5
PZ		 519 temp = I915_READ(DDI_BUF_CTL(PORT_E));
520 temp &= ~DDI_BUF_CTL_ENABLE;
521 I915_WRITE(DDI_BUF_CTL(PORT_E), temp);
522 POSTING_READ(DDI_BUF_CTL(PORT_E));
523
04945641 524 /* Disable DP_TP_CTL and FDI_RX_CTL and retry */
248138b5
PZ		 525 temp = I915_READ(DP_TP_CTL(PORT_E));
526 temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
527 temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
528 I915_WRITE(DP_TP_CTL(PORT_E), temp);
529 POSTING_READ(DP_TP_CTL(PORT_E));
530
531 intel_wait_ddi_buf_idle(dev_priv, PORT_E);
04945641
PZ		 532
533 rx_ctl_val &= ~FDI_RX_ENABLE;
534 I915_WRITE(_FDI_RXA_CTL, rx_ctl_val);
248138b5 535 POSTING_READ(_FDI_RXA_CTL);
04945641
PZ		 536
537 /* Reset FDI_RX_MISC pwrdn lanes */
538 temp = I915_READ(_FDI_RXA_MISC);
539 temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
540 temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
541 I915_WRITE(_FDI_RXA_MISC, temp);
248138b5 542 POSTING_READ(_FDI_RXA_MISC);
c82e4d26
ED		 543 }
544
04945641 545 DRM_ERROR("FDI link training failed!\n");
c82e4d26 546}
0e72a5b5 547
44905a27
DA		 548void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder)
549{
550 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
551 struct intel_digital_port *intel_dig_port =
552 enc_to_dig_port(&encoder->base);
553
554 intel_dp->DP = intel_dig_port->saved_port_bits |
c5fe6a06 555 DDI_BUF_CTL_ENABLE | DDI_BUF_TRANS_SELECT(0);
44905a27
DA		 556 intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count);
557
558}
559
8d9ddbcb
PZ		 560static struct intel_encoder *
561intel_ddi_get_crtc_encoder(struct drm_crtc *crtc)
562{
563 struct drm_device *dev = crtc->dev;
564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
565 struct intel_encoder *intel_encoder, *ret = NULL;
566 int num_encoders = 0;
567
568 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
569 ret = intel_encoder;
570 num_encoders++;
571 }
572
573 if (num_encoders != 1)
84f44ce7
VS		 574 WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders,
575 pipe_name(intel_crtc->pipe));
8d9ddbcb
PZ		 576
577 BUG_ON(ret == NULL);
578 return ret;
579}
580
bcddf610 581struct intel_encoder *
3165c074 582intel_ddi_get_crtc_new_encoder(struct intel_crtc_state *crtc_state)
d0737e1d 583{
3165c074
ACO		 584 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
585 struct intel_encoder *ret = NULL;
586 struct drm_atomic_state *state;
da3ced29
ACO		 587 struct drm_connector *connector;
588 struct drm_connector_state *connector_state;
d0737e1d 589 int num_encoders = 0;
3165c074 590 int i;
d0737e1d 591
3165c074
ACO		 592 state = crtc_state->base.state;
593
da3ced29
ACO		 594 for_each_connector_in_state(state, connector, connector_state, i) {
595 if (connector_state->crtc != crtc_state->base.crtc)
3165c074
ACO		 596 continue;
597
da3ced29 598 ret = to_intel_encoder(connector_state->best_encoder);
3165c074 599 num_encoders++;
d0737e1d
ACO		 600 }
601
602 WARN(num_encoders != 1, "%d encoders on crtc for pipe %c\n", num_encoders,
603 pipe_name(crtc->pipe));
604
605 BUG_ON(ret == NULL);
606 return ret;
607}
608
1c0b85c5 609#define LC_FREQ 2700
27893390 610#define LC_FREQ_2K U64_C(LC_FREQ * 2000)
1c0b85c5
DL		 611
612#define P_MIN 2
613#define P_MAX 64
614#define P_INC 2
615
616/* Constraints for PLL good behavior */
617#define REF_MIN 48
618#define REF_MAX 400
619#define VCO_MIN 2400
620#define VCO_MAX 4800
621
27893390
DL		 622#define abs_diff(a, b) ({ \
623 typeof(a) __a = (a); \
624 typeof(b) __b = (b); \
625 (void) (&__a == &__b); \
626 __a > __b ? (__a - __b) : (__b - __a); })
1c0b85c5
DL		 627
628struct wrpll_rnp {
629 unsigned p, n2, r2;
630};
631
632static unsigned wrpll_get_budget_for_freq(int clock)
6441ab5f 633{
1c0b85c5
DL		 634 unsigned budget;
635
636 switch (clock) {
637 case 25175000:
638 case 25200000:
639 case 27000000:
640 case 27027000:
641 case 37762500:
642 case 37800000:
643 case 40500000:
644 case 40541000:
645 case 54000000:
646 case 54054000:
647 case 59341000:
648 case 59400000:
649 case 72000000:
650 case 74176000:
651 case 74250000:
652 case 81000000:
653 case 81081000:
654 case 89012000:
655 case 89100000:
656 case 108000000:
657 case 108108000:
658 case 111264000:
659 case 111375000:
660 case 148352000:
661 case 148500000:
662 case 162000000:
663 case 162162000:
664 case 222525000:
665 case 222750000:
666 case 296703000:
667 case 297000000:
668 budget = 0;
669 break;
670 case 233500000:
671 case 245250000:
672 case 247750000:
673 case 253250000:
674 case 298000000:
675 budget = 1500;
676 break;
677 case 169128000:
678 case 169500000:
679 case 179500000:
680 case 202000000:
681 budget = 2000;
682 break;
683 case 256250000:
684 case 262500000:
685 case 270000000:
686 case 272500000:
687 case 273750000:
688 case 280750000:
689 case 281250000:
690 case 286000000:
691 case 291750000:
692 budget = 4000;
693 break;
694 case 267250000:
695 case 268500000:
696 budget = 5000;
697 break;
698 default:
699 budget = 1000;
700 break;
701 }
6441ab5f 702
1c0b85c5
DL		 703 return budget;
704}
705
706static void wrpll_update_rnp(uint64_t freq2k, unsigned budget,
707 unsigned r2, unsigned n2, unsigned p,
708 struct wrpll_rnp *best)
709{
710 uint64_t a, b, c, d, diff, diff_best;
6441ab5f 711
1c0b85c5
DL		 712 /* No best (r,n,p) yet */
713 if (best->p == 0) {
714 best->p = p;
715 best->n2 = n2;
716 best->r2 = r2;
717 return;
718 }
6441ab5f 719
1c0b85c5
DL		 720 /*
721 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
722 * freq2k.
723 *
724 * delta = 1e6 *
725 * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
726 * freq2k;
727 *
728 * and we would like delta <= budget.
729 *
730 * If the discrepancy is above the PPM-based budget, always prefer to
731 * improve upon the previous solution. However, if you're within the
732 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
733 */
734 a = freq2k * budget * p * r2;
735 b = freq2k * budget * best->p * best->r2;
27893390
DL		 736 diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
737 diff_best = abs_diff(freq2k * best->p * best->r2,
738 LC_FREQ_2K * best->n2);
1c0b85c5
DL		 739 c = 1000000 * diff;
740 d = 1000000 * diff_best;
741
742 if (a < c && b < d) {
743 /* If both are above the budget, pick the closer */
744 if (best->p * best->r2 * diff < p * r2 * diff_best) {
745 best->p = p;
746 best->n2 = n2;
747 best->r2 = r2;
748 }
749 } else if (a >= c && b < d) {
750 /* If A is below the threshold but B is above it? Update. */
751 best->p = p;
752 best->n2 = n2;
753 best->r2 = r2;
754 } else if (a >= c && b >= d) {
755 /* Both are below the limit, so pick the higher n2/(r2*r2) */
756 if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
757 best->p = p;
758 best->n2 = n2;
759 best->r2 = r2;
760 }
761 }
762 /* Otherwise a < c && b >= d, do nothing */
763}
764
11578553
JB		 765static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv,
766 int reg)
767{
768 int refclk = LC_FREQ;
769 int n, p, r;
770 u32 wrpll;
771
772 wrpll = I915_READ(reg);
114fe488
DV		 773 switch (wrpll & WRPLL_PLL_REF_MASK) {
774 case WRPLL_PLL_SSC:
775 case WRPLL_PLL_NON_SSC:
11578553
JB		 776 /*
777 * We could calculate spread here, but our checking
778 * code only cares about 5% accuracy, and spread is a max of
779 * 0.5% downspread.
780 */
781 refclk = 135;
782 break;
114fe488 783 case WRPLL_PLL_LCPLL:
11578553
JB		 784 refclk = LC_FREQ;
785 break;
786 default:
787 WARN(1, "bad wrpll refclk\n");
788 return 0;
789 }
790
791 r = wrpll & WRPLL_DIVIDER_REF_MASK;
792 p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
793 n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
794
20f0ec16
JB		 795 /* Convert to KHz, p & r have a fixed point portion */
796 return (refclk * n * 100) / (p * r);
11578553
JB		 797}
798
540e732c
S		 799static int skl_calc_wrpll_link(struct drm_i915_private *dev_priv,
800 uint32_t dpll)
801{
802 uint32_t cfgcr1_reg, cfgcr2_reg;
803 uint32_t cfgcr1_val, cfgcr2_val;
804 uint32_t p0, p1, p2, dco_freq;
805
806 cfgcr1_reg = GET_CFG_CR1_REG(dpll);
807 cfgcr2_reg = GET_CFG_CR2_REG(dpll);
808
809 cfgcr1_val = I915_READ(cfgcr1_reg);
810 cfgcr2_val = I915_READ(cfgcr2_reg);
811
812 p0 = cfgcr2_val & DPLL_CFGCR2_PDIV_MASK;
813 p2 = cfgcr2_val & DPLL_CFGCR2_KDIV_MASK;
814
815 if (cfgcr2_val & DPLL_CFGCR2_QDIV_MODE(1))
816 p1 = (cfgcr2_val & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
817 else
818 p1 = 1;
819
820
821 switch (p0) {
822 case DPLL_CFGCR2_PDIV_1:
823 p0 = 1;
824 break;
825 case DPLL_CFGCR2_PDIV_2:
826 p0 = 2;
827 break;
828 case DPLL_CFGCR2_PDIV_3:
829 p0 = 3;
830 break;
831 case DPLL_CFGCR2_PDIV_7:
832 p0 = 7;
833 break;
834 }
835
836 switch (p2) {
837 case DPLL_CFGCR2_KDIV_5:
838 p2 = 5;
839 break;
840 case DPLL_CFGCR2_KDIV_2:
841 p2 = 2;
842 break;
843 case DPLL_CFGCR2_KDIV_3:
844 p2 = 3;
845 break;
846 case DPLL_CFGCR2_KDIV_1:
847 p2 = 1;
848 break;
849 }
850
851 dco_freq = (cfgcr1_val & DPLL_CFGCR1_DCO_INTEGER_MASK) * 24 * 1000;
852
853 dco_freq += (((cfgcr1_val & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) * 24 *
854 1000) / 0x8000;
855
856 return dco_freq / (p0 * p1 * p2 * 5);
857}
858
859
860static void skl_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 861 struct intel_crtc_state *pipe_config)
540e732c
S		 862{
863 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
540e732c
S		 864 int link_clock = 0;
865 uint32_t dpll_ctl1, dpll;
866
134ffa44 867 dpll = pipe_config->ddi_pll_sel;
540e732c
S		 868
869 dpll_ctl1 = I915_READ(DPLL_CTRL1);
870
871 if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
872 link_clock = skl_calc_wrpll_link(dev_priv, dpll);
873 } else {
71cd8423
DL		 874 link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
875 link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
540e732c
S		 876
877 switch (link_clock) {
71cd8423 878 case DPLL_CTRL1_LINK_RATE_810:
540e732c
S		 879 link_clock = 81000;
880 break;
71cd8423 881 case DPLL_CTRL1_LINK_RATE_1080:
a8f3ef61
SJ		 882 link_clock = 108000;
883 break;
71cd8423 884 case DPLL_CTRL1_LINK_RATE_1350:
540e732c
S		 885 link_clock = 135000;
886 break;
71cd8423 887 case DPLL_CTRL1_LINK_RATE_1620:
a8f3ef61
SJ		 888 link_clock = 162000;
889 break;
71cd8423 890 case DPLL_CTRL1_LINK_RATE_2160:
a8f3ef61
SJ		 891 link_clock = 216000;
892 break;
71cd8423 893 case DPLL_CTRL1_LINK_RATE_2700:
540e732c
S		 894 link_clock = 270000;
895 break;
896 default:
897 WARN(1, "Unsupported link rate\n");
898 break;
899 }
900 link_clock *= 2;
901 }
902
903 pipe_config->port_clock = link_clock;
904
905 if (pipe_config->has_dp_encoder)
2d112de7 906 pipe_config->base.adjusted_mode.crtc_clock =
540e732c
S		 907 intel_dotclock_calculate(pipe_config->port_clock,
908 &pipe_config->dp_m_n);
909 else
2d112de7 910 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
540e732c
S		 911}
912
3d51278a 913static void hsw_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 914 struct intel_crtc_state *pipe_config)
11578553
JB		 915{
916 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
11578553
JB		 917 int link_clock = 0;
918 u32 val, pll;
919
26804afd 920 val = pipe_config->ddi_pll_sel;
11578553
JB		 921 switch (val & PORT_CLK_SEL_MASK) {
922 case PORT_CLK_SEL_LCPLL_810:
923 link_clock = 81000;
924 break;
925 case PORT_CLK_SEL_LCPLL_1350:
926 link_clock = 135000;
927 break;
928 case PORT_CLK_SEL_LCPLL_2700:
929 link_clock = 270000;
930 break;
931 case PORT_CLK_SEL_WRPLL1:
932 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1);
933 break;
934 case PORT_CLK_SEL_WRPLL2:
935 link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2);
936 break;
937 case PORT_CLK_SEL_SPLL:
938 pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK;
939 if (pll == SPLL_PLL_FREQ_810MHz)
940 link_clock = 81000;
941 else if (pll == SPLL_PLL_FREQ_1350MHz)
942 link_clock = 135000;
943 else if (pll == SPLL_PLL_FREQ_2700MHz)
944 link_clock = 270000;
945 else {
946 WARN(1, "bad spll freq\n");
947 return;
948 }
949 break;
950 default:
951 WARN(1, "bad port clock sel\n");
952 return;
953 }
954
955 pipe_config->port_clock = link_clock * 2;
956
957 if (pipe_config->has_pch_encoder)
2d112de7 958 pipe_config->base.adjusted_mode.crtc_clock =
11578553
JB		 959 intel_dotclock_calculate(pipe_config->port_clock,
960 &pipe_config->fdi_m_n);
961 else if (pipe_config->has_dp_encoder)
2d112de7 962 pipe_config->base.adjusted_mode.crtc_clock =
11578553
JB		 963 intel_dotclock_calculate(pipe_config->port_clock,
964 &pipe_config->dp_m_n);
965 else
2d112de7 966 pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
11578553
JB		 967}
968
977bb38d
S		 969static int bxt_calc_pll_link(struct drm_i915_private *dev_priv,
970 enum intel_dpll_id dpll)
971{
972 /* FIXME formula not available in bspec */
973 return 0;
974}
975
976static void bxt_ddi_clock_get(struct intel_encoder *encoder,
977 struct intel_crtc_state *pipe_config)
978{
979 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
980 enum port port = intel_ddi_get_encoder_port(encoder);
981 uint32_t dpll = port;
982
983 pipe_config->port_clock =
984 bxt_calc_pll_link(dev_priv, dpll);
985
986 if (pipe_config->has_dp_encoder)
987 pipe_config->base.adjusted_mode.crtc_clock =
988 intel_dotclock_calculate(pipe_config->port_clock,
989 &pipe_config->dp_m_n);
990 else
991 pipe_config->base.adjusted_mode.crtc_clock =
992 pipe_config->port_clock;
993}
994
3d51278a 995void intel_ddi_clock_get(struct intel_encoder *encoder,
5cec258b 996 struct intel_crtc_state *pipe_config)
3d51278a 997{
22606a18
DL		 998 struct drm_device *dev = encoder->base.dev;
999
1000 if (INTEL_INFO(dev)->gen <= 8)
1001 hsw_ddi_clock_get(encoder, pipe_config);
977bb38d 1002 else if (IS_SKYLAKE(dev))
22606a18 1003 skl_ddi_clock_get(encoder, pipe_config);
977bb38d
S		 1004 else if (IS_BROXTON(dev))
1005 bxt_ddi_clock_get(encoder, pipe_config);
3d51278a
DV		 1006}
1007
1c0b85c5 1008static void
d664c0ce
DL		 1009hsw_ddi_calculate_wrpll(int clock /* in Hz */,
1010 unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
1c0b85c5
DL		 1011{
1012 uint64_t freq2k;
1013 unsigned p, n2, r2;
1014 struct wrpll_rnp best = { 0, 0, 0 };
1015 unsigned budget;
1016
1017 freq2k = clock / 100;
1018
1019 budget = wrpll_get_budget_for_freq(clock);
1020
1021 /* Special case handling for 540 pixel clock: bypass WR PLL entirely
1022 * and directly pass the LC PLL to it. */
1023 if (freq2k == 5400000) {
1024 *n2_out = 2;
1025 *p_out = 1;
1026 *r2_out = 2;
1027 return;
1028 }
1029
1030 /*
1031 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
1032 * the WR PLL.
1033 *
1034 * We want R so that REF_MIN <= Ref <= REF_MAX.
1035 * Injecting R2 = 2 * R gives:
1036 * REF_MAX * r2 > LC_FREQ * 2 and
1037 * REF_MIN * r2 < LC_FREQ * 2
1038 *
1039 * Which means the desired boundaries for r2 are:
1040 * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
1041 *
1042 */
1043 for (r2 = LC_FREQ * 2 / REF_MAX + 1;
1044 r2 <= LC_FREQ * 2 / REF_MIN;
1045 r2++) {
1046
1047 /*
1048 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
1049 *
1050 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
1051 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
1052 * VCO_MAX * r2 > n2 * LC_FREQ and
1053 * VCO_MIN * r2 < n2 * LC_FREQ)
1054 *
1055 * Which means the desired boundaries for n2 are:
1056 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
1057 */
1058 for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
1059 n2 <= VCO_MAX * r2 / LC_FREQ;
1060 n2++) {
1061
1062 for (p = P_MIN; p <= P_MAX; p += P_INC)
1063 wrpll_update_rnp(freq2k, budget,
1064 r2, n2, p, &best);
1065 }
1066 }
6441ab5f 1067
1c0b85c5
DL		 1068 *n2_out = best.n2;
1069 *p_out = best.p;
1070 *r2_out = best.r2;
6441ab5f
PZ		 1071}
1072
0220ab6e 1073static bool
d664c0ce 1074hsw_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1075 struct intel_crtc_state *crtc_state,
d664c0ce
DL		 1076 struct intel_encoder *intel_encoder,
1077 int clock)
6441ab5f 1078{
d664c0ce 1079 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
e0b01be4 1080 struct intel_shared_dpll *pll;
716c2e55 1081 uint32_t val;
1c0b85c5 1082 unsigned p, n2, r2;
6441ab5f 1083
d664c0ce 1084 hsw_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p);
0694001b 1085
114fe488 1086 val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL |
0694001b
PZ		 1087 WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
1088 WRPLL_DIVIDER_POST(p);
1089
dd3cd74a
ACO		 1090 memset(&crtc_state->dpll_hw_state, 0,
1091 sizeof(crtc_state->dpll_hw_state));
1092
190f68c5 1093 crtc_state->dpll_hw_state.wrpll = val;
6441ab5f 1094
190f68c5 1095 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
716c2e55
DV		 1096 if (pll == NULL) {
1097 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1098 pipe_name(intel_crtc->pipe));
1099 return false;
0694001b 1100 }
d452c5b6 1101
190f68c5 1102 crtc_state->ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id);
6441ab5f
PZ		 1103 }
1104
6441ab5f
PZ		 1105 return true;
1106}
1107
82d35437
S		 1108struct skl_wrpll_params {
1109 uint32_t dco_fraction;
1110 uint32_t dco_integer;
1111 uint32_t qdiv_ratio;
1112 uint32_t qdiv_mode;
1113 uint32_t kdiv;
1114 uint32_t pdiv;
1115 uint32_t central_freq;
1116};
1117
76516fbc
DL		 1118static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1119 uint64_t afe_clock,
1120 uint64_t central_freq,
1121 uint32_t p0, uint32_t p1, uint32_t p2)
1122{
1123 uint64_t dco_freq;
1124
1125 params->central_freq = central_freq;
1126
1127 switch (central_freq) {
1128 case 9600000000ULL:
1129 params->central_freq = 0;
1130 break;
1131 case 9000000000ULL:
1132 params->central_freq = 1;
1133 break;
1134 case 8400000000ULL:
1135 params->central_freq = 3;
1136 }
1137
1138 switch (p0) {
1139 case 1:
1140 params->pdiv = 0;
1141 break;
1142 case 2:
1143 params->pdiv = 1;
1144 break;
1145 case 3:
1146 params->pdiv = 2;
1147 break;
1148 case 7:
1149 params->pdiv = 4;
1150 break;
1151 default:
1152 WARN(1, "Incorrect PDiv\n");
1153 }
1154
1155 switch (p2) {
1156 case 5:
1157 params->kdiv = 0;
1158 break;
1159 case 2:
1160 params->kdiv = 1;
1161 break;
1162 case 3:
1163 params->kdiv = 2;
1164 break;
1165 case 1:
1166 params->kdiv = 3;
1167 break;
1168 default:
1169 WARN(1, "Incorrect KDiv\n");
1170 }
1171
1172 params->qdiv_ratio = p1;
1173 params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1174
1175 dco_freq = p0 * p1 * p2 * afe_clock;
1176
1177 /*
1178 * Intermediate values are in Hz.
1179 * Divide by MHz to match bsepc
1180 */
30a7862d 1181 params->dco_integer = div_u64(dco_freq, 24 * MHz(1));
76516fbc 1182 params->dco_fraction =
30a7862d
DL		 1183 div_u64((div_u64(dco_freq, 24) -
1184 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
76516fbc
DL		 1185}
1186
318bd821 1187static bool
82d35437
S		 1188skl_ddi_calculate_wrpll(int clock /* in Hz */,
1189 struct skl_wrpll_params *wrpll_params)
1190{
1191 uint64_t afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
21318cce
DL		 1192 uint64_t dco_central_freq[3] = {8400000000ULL,
1193 9000000000ULL,
1194 9600000000ULL};
82d35437
S		 1195 uint32_t min_dco_deviation = 400;
1196 uint32_t min_dco_index = 3;
1197 uint32_t P0[4] = {1, 2, 3, 7};
1198 uint32_t P2[4] = {1, 2, 3, 5};
1199 bool found = false;
1200 uint32_t candidate_p = 0;
1201 uint32_t candidate_p0[3] = {0}, candidate_p1[3] = {0};
1202 uint32_t candidate_p2[3] = {0};
1203 uint32_t dco_central_freq_deviation[3];
1204 uint32_t i, P1, k, dco_count;
1205 bool retry_with_odd = false;
82d35437
S		 1206
1207 /* Determine P0, P1 or P2 */
1208 for (dco_count = 0; dco_count < 3; dco_count++) {
1209 found = false;
1210 candidate_p =
1211 div64_u64(dco_central_freq[dco_count], afe_clock);
1212 if (retry_with_odd == false)
1213 candidate_p = (candidate_p % 2 == 0 ?
1214 candidate_p : candidate_p + 1);
1215
1216 for (P1 = 1; P1 < candidate_p; P1++) {
1217 for (i = 0; i < 4; i++) {
1218 if (!(P0[i] != 1 || P1 == 1))
1219 continue;
1220
1221 for (k = 0; k < 4; k++) {
1222 if (P1 != 1 && P2[k] != 2)
1223 continue;
1224
1225 if (candidate_p == P0[i] * P1 * P2[k]) {
1226 /* Found possible P0, P1, P2 */
1227 found = true;
1228 candidate_p0[dco_count] = P0[i];
1229 candidate_p1[dco_count] = P1;
1230 candidate_p2[dco_count] = P2[k];
1231 goto found;
1232 }
1233
1234 }
1235 }
1236 }
1237
1238found:
1239 if (found) {
1240 dco_central_freq_deviation[dco_count] =
1241 div64_u64(10000 *
64311571 1242 abs_diff(candidate_p * afe_clock,
82d35437
S		 1243 dco_central_freq[dco_count]),
1244 dco_central_freq[dco_count]);
1245
1246 if (dco_central_freq_deviation[dco_count] <
1247 min_dco_deviation) {
1248 min_dco_deviation =
1249 dco_central_freq_deviation[dco_count];
1250 min_dco_index = dco_count;
1251 }
1252 }
1253
1254 if (min_dco_index > 2 && dco_count == 2) {
6cf75178
DL		 1255 /* oh well, we tried... */
1256 if (retry_with_odd)
1257 break;
1258
82d35437
S		 1259 retry_with_odd = true;
1260 dco_count = 0;
1261 }
1262 }
1263
9c236753
DL		 1264 if (WARN(min_dco_index > 2,
1265 "No valid parameters found for pixel clock: %dHz\n", clock))
318bd821 1266 return false;
82d35437 1267
76516fbc
DL		 1268 skl_wrpll_params_populate(wrpll_params,
1269 afe_clock,
1270 dco_central_freq[min_dco_index],
1271 candidate_p0[min_dco_index],
1272 candidate_p1[min_dco_index],
1273 candidate_p2[min_dco_index]);
318bd821
DL		 1274
1275 return true;
82d35437
S		 1276}
1277
1278
1279static bool
1280skl_ddi_pll_select(struct intel_crtc *intel_crtc,
190f68c5 1281 struct intel_crtc_state *crtc_state,
82d35437
S		 1282 struct intel_encoder *intel_encoder,
1283 int clock)
1284{
1285 struct intel_shared_dpll *pll;
1286 uint32_t ctrl1, cfgcr1, cfgcr2;
1287
1288 /*
1289 * See comment in intel_dpll_hw_state to understand why we always use 0
1290 * as the DPLL id in this function.
1291 */
1292
1293 ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1294
1295 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1296 struct skl_wrpll_params wrpll_params = { 0, };
1297
1298 ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1299
318bd821
DL		 1300 if (!skl_ddi_calculate_wrpll(clock * 1000, &wrpll_params))
1301 return false;
82d35437
S		 1302
1303 cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1304 DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1305 wrpll_params.dco_integer;
1306
1307 cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1308 DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1309 DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1310 DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1311 wrpll_params.central_freq;
1312 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT) {
1313 struct drm_encoder *encoder = &intel_encoder->base;
1314 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1315
1316 switch (intel_dp->link_bw) {
1317 case DP_LINK_BW_1_62:
71cd8423 1318 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
82d35437
S		 1319 break;
1320 case DP_LINK_BW_2_7:
71cd8423 1321 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
82d35437
S		 1322 break;
1323 case DP_LINK_BW_5_4:
71cd8423 1324 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
82d35437
S		 1325 break;
1326 }
1327
1328 cfgcr1 = cfgcr2 = 0;
1329 } else /* eDP */
1330 return true;
1331
dd3cd74a
ACO		 1332 memset(&crtc_state->dpll_hw_state, 0,
1333 sizeof(crtc_state->dpll_hw_state));
1334
190f68c5
ACO		 1335 crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1336 crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1337 crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
82d35437 1338
190f68c5 1339 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
82d35437
S		 1340 if (pll == NULL) {
1341 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1342 pipe_name(intel_crtc->pipe));
1343 return false;
1344 }
1345
1346 /* shared DPLL id 0 is DPLL 1 */
190f68c5 1347 crtc_state->ddi_pll_sel = pll->id + 1;
82d35437
S		 1348
1349 return true;
1350}
0220ab6e 1351
d683f3bc
S		 1352/* bxt clock parameters */
1353struct bxt_clk_div {
1354 uint32_t p1;
1355 uint32_t p2;
1356 uint32_t m2_int;
1357 uint32_t m2_frac;
1358 bool m2_frac_en;
1359 uint32_t n;
d683f3bc
S		 1360};
1361
1362/* pre-calculated values for DP linkrates */
1363static struct bxt_clk_div bxt_dp_clk_val[7] = {
e0681e38
VK		 1364 /* 162 */ {4, 2, 32, 1677722, 1, 1},
1365 /* 270 */ {4, 1, 27, 0, 0, 1},
1366 /* 540 */ {2, 1, 27, 0, 0, 1},
1367 /* 216 */ {3, 2, 32, 1677722, 1, 1},
1368 /* 243 */ {4, 1, 24, 1258291, 1, 1},
1369 /* 324 */ {4, 1, 32, 1677722, 1, 1},
1370 /* 432 */ {3, 1, 32, 1677722, 1, 1}
d683f3bc
S		 1371};
1372
1373static bool
1374bxt_ddi_pll_select(struct intel_crtc *intel_crtc,
1375 struct intel_crtc_state *crtc_state,
1376 struct intel_encoder *intel_encoder,
1377 int clock)
1378{
1379 struct intel_shared_dpll *pll;
1380 struct bxt_clk_div clk_div = {0};
b6dc71f3
VK		 1381 int vco = 0;
1382 uint32_t prop_coef, int_coef, gain_ctl, targ_cnt;
e0681e38 1383 uint32_t dcoampovr_en_h, dco_amp, lanestagger;
d683f3bc
S		 1384
1385 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
1386 intel_clock_t best_clock;
1387
1388 /* Calculate HDMI div */
1389 /*
1390 * FIXME: tie the following calculation into
1391 * i9xx_crtc_compute_clock
1392 */
1393 if (!bxt_find_best_dpll(crtc_state, clock, &best_clock)) {
1394 DRM_DEBUG_DRIVER("no PLL dividers found for clock %d pipe %c\n",
1395 clock, pipe_name(intel_crtc->pipe));
1396 return false;
1397 }
1398
1399 clk_div.p1 = best_clock.p1;
1400 clk_div.p2 = best_clock.p2;
1401 WARN_ON(best_clock.m1 != 2);
1402 clk_div.n = best_clock.n;
1403 clk_div.m2_int = best_clock.m2 >> 22;
1404 clk_div.m2_frac = best_clock.m2 & ((1 << 22) - 1);
1405 clk_div.m2_frac_en = clk_div.m2_frac != 0;
1406
b6dc71f3 1407 vco = best_clock.vco;
d683f3bc
S		 1408 } else if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
1409 intel_encoder->type == INTEL_OUTPUT_EDP) {
1410 struct drm_encoder *encoder = &intel_encoder->base;
1411 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1412
1413 switch (intel_dp->link_bw) {
1414 case DP_LINK_BW_1_62:
1415 clk_div = bxt_dp_clk_val[0];
1416 break;
1417 case DP_LINK_BW_2_7:
1418 clk_div = bxt_dp_clk_val[1];
1419 break;
1420 case DP_LINK_BW_5_4:
1421 clk_div = bxt_dp_clk_val[2];
1422 break;
1423 default:
1424 clk_div = bxt_dp_clk_val[0];
1425 DRM_ERROR("Unknown link rate\n");
1426 }
b6dc71f3
VK		 1427 vco = clock * 10 / 2 * clk_div.p1 * clk_div.p2;
1428 }
1429
1430 dco_amp = 15;
1431 dcoampovr_en_h = 0;
1432 if (vco >= 6200000 && vco <= 6480000) {
1433 prop_coef = 4;
1434 int_coef = 9;
1435 gain_ctl = 3;
1436 targ_cnt = 8;
1437 } else if ((vco > 5400000 && vco < 6200000) ||
1438 (vco >= 4800000 && vco < 5400000)) {
1439 prop_coef = 5;
1440 int_coef = 11;
1441 gain_ctl = 3;
1442 targ_cnt = 9;
1443 if (vco >= 4800000 && vco < 5400000)
1444 dcoampovr_en_h = 1;
1445 } else if (vco == 5400000) {
1446 prop_coef = 3;
1447 int_coef = 8;
1448 gain_ctl = 1;
1449 targ_cnt = 9;
1450 } else {
1451 DRM_ERROR("Invalid VCO\n");
1452 return false;
d683f3bc
S		 1453 }
1454
dd3cd74a
ACO		 1455 memset(&crtc_state->dpll_hw_state, 0,
1456 sizeof(crtc_state->dpll_hw_state));
1457
e0681e38
VK		 1458 if (clock > 270000)
1459 lanestagger = 0x18;
1460 else if (clock > 135000)
1461 lanestagger = 0x0d;
1462 else if (clock > 67000)
1463 lanestagger = 0x07;
1464 else if (clock > 33000)
1465 lanestagger = 0x04;
1466 else
1467 lanestagger = 0x02;
1468
d683f3bc
S		 1469 crtc_state->dpll_hw_state.ebb0 =
1470 PORT_PLL_P1(clk_div.p1) | PORT_PLL_P2(clk_div.p2);
1471 crtc_state->dpll_hw_state.pll0 = clk_div.m2_int;
1472 crtc_state->dpll_hw_state.pll1 = PORT_PLL_N(clk_div.n);
1473 crtc_state->dpll_hw_state.pll2 = clk_div.m2_frac;
1474
1475 if (clk_div.m2_frac_en)
1476 crtc_state->dpll_hw_state.pll3 =
1477 PORT_PLL_M2_FRAC_ENABLE;
1478
1479 crtc_state->dpll_hw_state.pll6 =
b6dc71f3 1480 prop_coef | PORT_PLL_INT_COEFF(int_coef);
d683f3bc 1481 crtc_state->dpll_hw_state.pll6 |=
b6dc71f3
VK		 1482 PORT_PLL_GAIN_CTL(gain_ctl);
1483
1484 crtc_state->dpll_hw_state.pll8 = targ_cnt;
d683f3bc 1485
b6dc71f3
VK		 1486 if (dcoampovr_en_h)
1487 crtc_state->dpll_hw_state.pll10 = PORT_PLL_DCO_AMP_OVR_EN_H;
1488
1489 crtc_state->dpll_hw_state.pll10 |= PORT_PLL_DCO_AMP(dco_amp);
d683f3bc
S		 1490
1491 crtc_state->dpll_hw_state.pcsdw12 =
e0681e38 1492 LANESTAGGER_STRAP_OVRD | lanestagger;
d683f3bc
S		 1493
1494 pll = intel_get_shared_dpll(intel_crtc, crtc_state);
1495 if (pll == NULL) {
1496 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
1497 pipe_name(intel_crtc->pipe));
1498 return false;
1499 }
1500
1501 /* shared DPLL id 0 is DPLL A */
1502 crtc_state->ddi_pll_sel = pll->id;
1503
1504 return true;
1505}
1506
0220ab6e
DL		 1507/*
1508 * Tries to find a *shared* PLL for the CRTC and store it in
1509 * intel_crtc->ddi_pll_sel.
1510 *
1511 * For private DPLLs, compute_config() should do the selection for us. This
1512 * function should be folded into compute_config() eventually.
1513 */
190f68c5
ACO		 1514bool intel_ddi_pll_select(struct intel_crtc *intel_crtc,
1515 struct intel_crtc_state *crtc_state)
0220ab6e 1516{
82d35437 1517 struct drm_device *dev = intel_crtc->base.dev;
d0737e1d 1518 struct intel_encoder *intel_encoder =
3165c074 1519 intel_ddi_get_crtc_new_encoder(crtc_state);
190f68c5 1520 int clock = crtc_state->port_clock;
0220ab6e 1521
82d35437 1522 if (IS_SKYLAKE(dev))
190f68c5
ACO		 1523 return skl_ddi_pll_select(intel_crtc, crtc_state,
1524 intel_encoder, clock);
d683f3bc
S		 1525 else if (IS_BROXTON(dev))
1526 return bxt_ddi_pll_select(intel_crtc, crtc_state,
1527 intel_encoder, clock);
82d35437 1528 else
190f68c5
ACO		 1529 return hsw_ddi_pll_select(intel_crtc, crtc_state,
1530 intel_encoder, clock);
0220ab6e
DL		 1531}
1532
dae84799
PZ		 1533void intel_ddi_set_pipe_settings(struct drm_crtc *crtc)
1534{
1535 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1536 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1537 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
6e3c9717 1538 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
dae84799
PZ		 1539 int type = intel_encoder->type;
1540 uint32_t temp;
1541
0e32b39c 1542 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || type == INTEL_OUTPUT_DP_MST) {
c9809791 1543 temp = TRANS_MSA_SYNC_CLK;
6e3c9717 1544 switch (intel_crtc->config->pipe_bpp) {
dae84799 1545 case 18:
c9809791 1546 temp |= TRANS_MSA_6_BPC;
dae84799
PZ		 1547 break;
1548 case 24:
c9809791 1549 temp |= TRANS_MSA_8_BPC;
dae84799
PZ		 1550 break;
1551 case 30:
c9809791 1552 temp |= TRANS_MSA_10_BPC;
dae84799
PZ		 1553 break;
1554 case 36:
c9809791 1555 temp |= TRANS_MSA_12_BPC;
dae84799
PZ		 1556 break;
1557 default:
4e53c2e0 1558 BUG();
dae84799 1559 }
c9809791 1560 I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp);
dae84799
PZ		 1561 }
1562}
1563
0e32b39c
DA		 1564void intel_ddi_set_vc_payload_alloc(struct drm_crtc *crtc, bool state)
1565{
1566 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1567 struct drm_device *dev = crtc->dev;
1568 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1569 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
0e32b39c
DA		 1570 uint32_t temp;
1571 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1572 if (state == true)
1573 temp |= TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1574 else
1575 temp &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC;
1576 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
1577}
1578
8228c251 1579void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc)
8d9ddbcb
PZ		 1580{
1581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1582 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
7739c33b 1583 struct drm_encoder *encoder = &intel_encoder->base;
c7670b10
PZ		 1584 struct drm_device *dev = crtc->dev;
1585 struct drm_i915_private *dev_priv = dev->dev_private;
8d9ddbcb 1586 enum pipe pipe = intel_crtc->pipe;
6e3c9717 1587 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
174edf1f 1588 enum port port = intel_ddi_get_encoder_port(intel_encoder);
7739c33b 1589 int type = intel_encoder->type;
8d9ddbcb
PZ		 1590 uint32_t temp;
1591
ad80a810
PZ		 1592 /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */
1593 temp = TRANS_DDI_FUNC_ENABLE;
174edf1f 1594 temp |= TRANS_DDI_SELECT_PORT(port);
dfcef252 1595
6e3c9717 1596 switch (intel_crtc->config->pipe_bpp) {
dfcef252 1597 case 18:
ad80a810 1598 temp |= TRANS_DDI_BPC_6;
dfcef252
PZ		 1599 break;
1600 case 24:
ad80a810 1601 temp |= TRANS_DDI_BPC_8;
dfcef252
PZ		 1602 break;
1603 case 30:
ad80a810 1604 temp |= TRANS_DDI_BPC_10;
dfcef252
PZ		 1605 break;
1606 case 36:
ad80a810 1607 temp |= TRANS_DDI_BPC_12;
dfcef252
PZ		 1608 break;
1609 default:
4e53c2e0 1610 BUG();
dfcef252 1611 }
72662e10 1612
6e3c9717 1613 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC)
ad80a810 1614 temp |= TRANS_DDI_PVSYNC;
6e3c9717 1615 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC)
ad80a810 1616 temp |= TRANS_DDI_PHSYNC;
f63eb7c4 1617
e6f0bfc4
PZ		 1618 if (cpu_transcoder == TRANSCODER_EDP) {
1619 switch (pipe) {
1620 case PIPE_A:
c7670b10
PZ		 1621 /* On Haswell, can only use the always-on power well for
1622 * eDP when not using the panel fitter, and when not
1623 * using motion blur mitigation (which we don't
1624 * support). */
fabf6e51 1625 if (IS_HASWELL(dev) &&
6e3c9717
ACO		 1626 (intel_crtc->config->pch_pfit.enabled ||
1627 intel_crtc->config->pch_pfit.force_thru))
d6dd9eb1
DV		 1628 temp |= TRANS_DDI_EDP_INPUT_A_ONOFF;
1629 else
1630 temp |= TRANS_DDI_EDP_INPUT_A_ON;
e6f0bfc4
PZ		 1631 break;
1632 case PIPE_B:
1633 temp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
1634 break;
1635 case PIPE_C:
1636 temp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
1637 break;
1638 default:
1639 BUG();
1640 break;
1641 }
1642 }
1643
7739c33b 1644 if (type == INTEL_OUTPUT_HDMI) {
6e3c9717 1645 if (intel_crtc->config->has_hdmi_sink)
ad80a810 1646 temp |= TRANS_DDI_MODE_SELECT_HDMI;
8d9ddbcb 1647 else
ad80a810 1648 temp |= TRANS_DDI_MODE_SELECT_DVI;
8d9ddbcb 1649
7739c33b 1650 } else if (type == INTEL_OUTPUT_ANALOG) {
ad80a810 1651 temp |= TRANS_DDI_MODE_SELECT_FDI;
6e3c9717 1652 temp |= (intel_crtc->config->fdi_lanes - 1) << 1;
7739c33b
PZ		 1653
1654 } else if (type == INTEL_OUTPUT_DISPLAYPORT ||
1655 type == INTEL_OUTPUT_EDP) {
1656 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1657
0e32b39c
DA		 1658 if (intel_dp->is_mst) {
1659 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1660 } else
1661 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
1662
1663 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
1664 } else if (type == INTEL_OUTPUT_DP_MST) {
1665 struct intel_dp *intel_dp = &enc_to_mst(encoder)->primary->dp;
1666
1667 if (intel_dp->is_mst) {
1668 temp |= TRANS_DDI_MODE_SELECT_DP_MST;
1669 } else
1670 temp |= TRANS_DDI_MODE_SELECT_DP_SST;
7739c33b 1671
17aa6be9 1672 temp |= DDI_PORT_WIDTH(intel_dp->lane_count);
8d9ddbcb 1673 } else {
84f44ce7
VS		 1674 WARN(1, "Invalid encoder type %d for pipe %c\n",
1675 intel_encoder->type, pipe_name(pipe));
8d9ddbcb
PZ		 1676 }
1677
ad80a810 1678 I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp);
8d9ddbcb 1679}
72662e10 1680
ad80a810
PZ		 1681void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv,
1682 enum transcoder cpu_transcoder)
8d9ddbcb 1683{
ad80a810 1684 uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
8d9ddbcb
PZ		 1685 uint32_t val = I915_READ(reg);
1686
0e32b39c 1687 val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK | TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
ad80a810 1688 val |= TRANS_DDI_PORT_NONE;
8d9ddbcb 1689 I915_WRITE(reg, val);
72662e10
ED		 1690}
1691
bcbc889b
PZ		 1692bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector)
1693{
1694 struct drm_device *dev = intel_connector->base.dev;
1695 struct drm_i915_private *dev_priv = dev->dev_private;
1696 struct intel_encoder *intel_encoder = intel_connector->encoder;
1697 int type = intel_connector->base.connector_type;
1698 enum port port = intel_ddi_get_encoder_port(intel_encoder);
1699 enum pipe pipe = 0;
1700 enum transcoder cpu_transcoder;
882244a3 1701 enum intel_display_power_domain power_domain;
bcbc889b
PZ		 1702 uint32_t tmp;
1703
882244a3 1704 power_domain = intel_display_port_power_domain(intel_encoder);
f458ebbc 1705 if (!intel_display_power_is_enabled(dev_priv, power_domain))
882244a3
PZ		 1706 return false;
1707
bcbc889b
PZ		 1708 if (!intel_encoder->get_hw_state(intel_encoder, &pipe))
1709 return false;
1710
1711 if (port == PORT_A)
1712 cpu_transcoder = TRANSCODER_EDP;
1713 else
1a240d4d 1714 cpu_transcoder = (enum transcoder) pipe;
bcbc889b
PZ		 1715
1716 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
1717
1718 switch (tmp & TRANS_DDI_MODE_SELECT_MASK) {
1719 case TRANS_DDI_MODE_SELECT_HDMI:
1720 case TRANS_DDI_MODE_SELECT_DVI:
1721 return (type == DRM_MODE_CONNECTOR_HDMIA);
1722
1723 case TRANS_DDI_MODE_SELECT_DP_SST:
1724 if (type == DRM_MODE_CONNECTOR_eDP)
1725 return true;
bcbc889b 1726 return (type == DRM_MODE_CONNECTOR_DisplayPort);
0e32b39c
DA		 1727 case TRANS_DDI_MODE_SELECT_DP_MST:
1728 /* if the transcoder is in MST state then
1729 * connector isn't connected */
1730 return false;
bcbc889b
PZ		 1731
1732 case TRANS_DDI_MODE_SELECT_FDI:
1733 return (type == DRM_MODE_CONNECTOR_VGA);
1734
1735 default:
1736 return false;
1737 }
1738}
1739
85234cdc
DV		 1740bool intel_ddi_get_hw_state(struct intel_encoder *encoder,
1741 enum pipe *pipe)
1742{
1743 struct drm_device *dev = encoder->base.dev;
1744 struct drm_i915_private *dev_priv = dev->dev_private;
fe43d3f5 1745 enum port port = intel_ddi_get_encoder_port(encoder);
6d129bea 1746 enum intel_display_power_domain power_domain;
85234cdc
DV		 1747 u32 tmp;
1748 int i;
1749
6d129bea 1750 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 1751 if (!intel_display_power_is_enabled(dev_priv, power_domain))
6d129bea
ID		 1752 return false;
1753
fe43d3f5 1754 tmp = I915_READ(DDI_BUF_CTL(port));
85234cdc
DV		 1755
1756 if (!(tmp & DDI_BUF_CTL_ENABLE))
1757 return false;
1758
ad80a810
PZ		 1759 if (port == PORT_A) {
1760 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
85234cdc 1761
ad80a810
PZ		 1762 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1763 case TRANS_DDI_EDP_INPUT_A_ON:
1764 case TRANS_DDI_EDP_INPUT_A_ONOFF:
1765 *pipe = PIPE_A;
1766 break;
1767 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1768 *pipe = PIPE_B;
1769 break;
1770 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1771 *pipe = PIPE_C;
1772 break;
1773 }
1774
1775 return true;
1776 } else {
1777 for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) {
1778 tmp = I915_READ(TRANS_DDI_FUNC_CTL(i));
1779
1780 if ((tmp & TRANS_DDI_PORT_MASK)
1781 == TRANS_DDI_SELECT_PORT(port)) {
0e32b39c
DA		 1782 if ((tmp & TRANS_DDI_MODE_SELECT_MASK) == TRANS_DDI_MODE_SELECT_DP_MST)
1783 return false;
1784
ad80a810
PZ		 1785 *pipe = i;
1786 return true;
1787 }
85234cdc
DV		 1788 }
1789 }
1790
84f44ce7 1791 DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port));
85234cdc 1792
22f9fe50 1793 return false;
85234cdc
DV		 1794}
1795
fc914639
PZ		 1796void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc)
1797{
1798 struct drm_crtc *crtc = &intel_crtc->base;
1799 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1800 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
1801 enum port port = intel_ddi_get_encoder_port(intel_encoder);
6e3c9717 1802 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 1803
bb523fc0
PZ		 1804 if (cpu_transcoder != TRANSCODER_EDP)
1805 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1806 TRANS_CLK_SEL_PORT(port));
fc914639
PZ		 1807}
1808
1809void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc)
1810{
1811 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
6e3c9717 1812 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
fc914639 1813
bb523fc0
PZ		 1814 if (cpu_transcoder != TRANSCODER_EDP)
1815 I915_WRITE(TRANS_CLK_SEL(cpu_transcoder),
1816 TRANS_CLK_SEL_DISABLED);
fc914639
PZ		 1817}
1818
96fb9f9b
VK		 1819void bxt_ddi_vswing_sequence(struct drm_device *dev, u32 level,
1820 enum port port, int type)
1821{
1822 struct drm_i915_private *dev_priv = dev->dev_private;
1823 const struct bxt_ddi_buf_trans *ddi_translations;
1824 u32 n_entries, i;
1825 uint32_t val;
1826
1827 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
1828 n_entries = ARRAY_SIZE(bxt_ddi_translations_dp);
1829 ddi_translations = bxt_ddi_translations_dp;
1830 } else if (type == INTEL_OUTPUT_HDMI) {
1831 n_entries = ARRAY_SIZE(bxt_ddi_translations_hdmi);
1832 ddi_translations = bxt_ddi_translations_hdmi;
1833 } else {
1834 DRM_DEBUG_KMS("Vswing programming not done for encoder %d\n",
1835 type);
1836 return;
1837 }
1838
1839 /* Check if default value has to be used */
1840 if (level >= n_entries ||
1841 (type == INTEL_OUTPUT_HDMI && level == HDMI_LEVEL_SHIFT_UNKNOWN)) {
1842 for (i = 0; i < n_entries; i++) {
1843 if (ddi_translations[i].default_index) {
1844 level = i;
1845 break;
1846 }
1847 }
1848 }
1849
1850 /*
1851 * While we write to the group register to program all lanes at once we
1852 * can read only lane registers and we pick lanes 0/1 for that.
1853 */
1854 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1855 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
1856 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1857
1858 val = I915_READ(BXT_PORT_TX_DW2_LN0(port));
1859 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
1860 val |= ddi_translations[level].margin << MARGIN_000_SHIFT |
1861 ddi_translations[level].scale << UNIQ_TRANS_SCALE_SHIFT;
1862 I915_WRITE(BXT_PORT_TX_DW2_GRP(port), val);
1863
1864 val = I915_READ(BXT_PORT_TX_DW3_LN0(port));
1865 val &= ~UNIQE_TRANGE_EN_METHOD;
1866 if (ddi_translations[level].enable)
1867 val |= UNIQE_TRANGE_EN_METHOD;
1868 I915_WRITE(BXT_PORT_TX_DW3_GRP(port), val);
1869
1870 val = I915_READ(BXT_PORT_TX_DW4_LN0(port));
1871 val &= ~DE_EMPHASIS;
1872 val |= ddi_translations[level].deemphasis << DEEMPH_SHIFT;
1873 I915_WRITE(BXT_PORT_TX_DW4_GRP(port), val);
1874
1875 val = I915_READ(BXT_PORT_PCS_DW10_LN01(port));
1876 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
1877 I915_WRITE(BXT_PORT_PCS_DW10_GRP(port), val);
1878}
1879
00c09d70 1880static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
6441ab5f 1881{
c19b0669 1882 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 1883 struct drm_device *dev = encoder->dev;
1884 struct drm_i915_private *dev_priv = dev->dev_private;
30cf6db8 1885 struct intel_crtc *crtc = to_intel_crtc(encoder->crtc);
6441ab5f 1886 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1887 int type = intel_encoder->type;
96fb9f9b 1888 int hdmi_level;
6441ab5f 1889
82a4d9c0
PZ		 1890 if (type == INTEL_OUTPUT_EDP) {
1891 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
4be73780 1892 intel_edp_panel_on(intel_dp);
82a4d9c0 1893 }
6441ab5f 1894
efa80add 1895 if (IS_SKYLAKE(dev)) {
6e3c9717 1896 uint32_t dpll = crtc->config->ddi_pll_sel;
efa80add
S		 1897 uint32_t val;
1898
5416d871
DL		 1899 /*
1900 * DPLL0 is used for eDP and is the only "private" DPLL (as
1901 * opposed to shared) on SKL
1902 */
1903 if (type == INTEL_OUTPUT_EDP) {
1904 WARN_ON(dpll != SKL_DPLL0);
1905
1906 val = I915_READ(DPLL_CTRL1);
1907
1908 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
1909 DPLL_CTRL1_SSC(dpll) |
71cd8423 1910 DPLL_CTRL1_LINK_RATE_MASK(dpll));
6e3c9717 1911 val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
5416d871
DL		 1912
1913 I915_WRITE(DPLL_CTRL1, val);
1914 POSTING_READ(DPLL_CTRL1);
1915 }
1916
1917 /* DDI -> PLL mapping */
efa80add
S		 1918 val = I915_READ(DPLL_CTRL2);
1919
1920 val &= ~(DPLL_CTRL2_DDI_CLK_OFF(port) |
1921 DPLL_CTRL2_DDI_CLK_SEL_MASK(port));
1922 val |= (DPLL_CTRL2_DDI_CLK_SEL(dpll, port) |
1923 DPLL_CTRL2_DDI_SEL_OVERRIDE(port));
1924
1925 I915_WRITE(DPLL_CTRL2, val);
5416d871 1926
1ab23380 1927 } else if (INTEL_INFO(dev)->gen < 9) {
6e3c9717
ACO		 1928 WARN_ON(crtc->config->ddi_pll_sel == PORT_CLK_SEL_NONE);
1929 I915_WRITE(PORT_CLK_SEL(port), crtc->config->ddi_pll_sel);
efa80add 1930 }
c19b0669 1931
82a4d9c0 1932 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
c19b0669 1933 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
30cf6db8 1934
44905a27 1935 intel_ddi_init_dp_buf_reg(intel_encoder);
c19b0669
PZ		 1936
1937 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1938 intel_dp_start_link_train(intel_dp);
1939 intel_dp_complete_link_train(intel_dp);
23f08d83 1940 if (port != PORT_A || INTEL_INFO(dev)->gen >= 9)
3ab9c637 1941 intel_dp_stop_link_train(intel_dp);
30cf6db8
DV		 1942 } else if (type == INTEL_OUTPUT_HDMI) {
1943 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
1944
96fb9f9b
VK		 1945 if (IS_BROXTON(dev)) {
1946 hdmi_level = dev_priv->vbt.
1947 ddi_port_info[port].hdmi_level_shift;
1948 bxt_ddi_vswing_sequence(dev, hdmi_level, port,
1949 INTEL_OUTPUT_HDMI);
1950 }
30cf6db8 1951 intel_hdmi->set_infoframes(encoder,
6e3c9717
ACO		 1952 crtc->config->has_hdmi_sink,
1953 &crtc->config->base.adjusted_mode);
c19b0669 1954 }
6441ab5f
PZ		 1955}
1956
00c09d70 1957static void intel_ddi_post_disable(struct intel_encoder *intel_encoder)
6441ab5f
PZ		 1958{
1959 struct drm_encoder *encoder = &intel_encoder->base;
efa80add
S		 1960 struct drm_device *dev = encoder->dev;
1961 struct drm_i915_private *dev_priv = dev->dev_private;
6441ab5f 1962 enum port port = intel_ddi_get_encoder_port(intel_encoder);
82a4d9c0 1963 int type = intel_encoder->type;
2886e93f 1964 uint32_t val;
a836bdf9 1965 bool wait = false;
2886e93f
PZ		 1966
1967 val = I915_READ(DDI_BUF_CTL(port));
1968 if (val & DDI_BUF_CTL_ENABLE) {
1969 val &= ~DDI_BUF_CTL_ENABLE;
1970 I915_WRITE(DDI_BUF_CTL(port), val);
a836bdf9 1971 wait = true;
2886e93f 1972 }
6441ab5f 1973
a836bdf9
PZ		 1974 val = I915_READ(DP_TP_CTL(port));
1975 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
1976 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
1977 I915_WRITE(DP_TP_CTL(port), val);
1978
1979 if (wait)
1980 intel_wait_ddi_buf_idle(dev_priv, port);
1981
76bb80ed 1982 if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) {
82a4d9c0 1983 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
76bb80ed 1984 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
24f3e092 1985 intel_edp_panel_vdd_on(intel_dp);
4be73780 1986 intel_edp_panel_off(intel_dp);
82a4d9c0
PZ		 1987 }
1988
efa80add
S		 1989 if (IS_SKYLAKE(dev))
1990 I915_WRITE(DPLL_CTRL2, (I915_READ(DPLL_CTRL2) |
1991 DPLL_CTRL2_DDI_CLK_OFF(port)));
1ab23380 1992 else if (INTEL_INFO(dev)->gen < 9)
efa80add 1993 I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE);
6441ab5f
PZ		 1994}
1995
00c09d70 1996static void intel_enable_ddi(struct intel_encoder *intel_encoder)
72662e10 1997{
6547fef8 1998 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 1999 struct drm_crtc *crtc = encoder->crtc;
2000 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6547fef8 2001 struct drm_device *dev = encoder->dev;
72662e10 2002 struct drm_i915_private *dev_priv = dev->dev_private;
6547fef8
PZ		 2003 enum port port = intel_ddi_get_encoder_port(intel_encoder);
2004 int type = intel_encoder->type;
72662e10 2005
6547fef8 2006 if (type == INTEL_OUTPUT_HDMI) {
876a8cdf
DL		 2007 struct intel_digital_port *intel_dig_port =
2008 enc_to_dig_port(encoder);
2009
6547fef8
PZ		 2010 /* In HDMI/DVI mode, the port width, and swing/emphasis values
2011 * are ignored so nothing special needs to be done besides
2012 * enabling the port.
2013 */
876a8cdf 2014 I915_WRITE(DDI_BUF_CTL(port),
bcf53de4
SM		 2015 intel_dig_port->saved_port_bits |
2016 DDI_BUF_CTL_ENABLE);
d6c50ff8
PZ		 2017 } else if (type == INTEL_OUTPUT_EDP) {
2018 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2019
23f08d83 2020 if (port == PORT_A && INTEL_INFO(dev)->gen < 9)
3ab9c637
ID		 2021 intel_dp_stop_link_train(intel_dp);
2022
4be73780 2023 intel_edp_backlight_on(intel_dp);
0bc12bcb 2024 intel_psr_enable(intel_dp);
c395578e 2025 intel_edp_drrs_enable(intel_dp);
6547fef8 2026 }
7b9f35a6 2027
6e3c9717 2028 if (intel_crtc->config->has_audio) {
d45a0bf5 2029 intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO);
69bfe1a9 2030 intel_audio_codec_enable(intel_encoder);
7b9f35a6 2031 }
5ab432ef
DV		 2032}
2033
00c09d70 2034static void intel_disable_ddi(struct intel_encoder *intel_encoder)
5ab432ef 2035{
d6c50ff8 2036 struct drm_encoder *encoder = &intel_encoder->base;
7b9f35a6
WX		 2037 struct drm_crtc *crtc = encoder->crtc;
2038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d6c50ff8 2039 int type = intel_encoder->type;
7b9f35a6
WX		 2040 struct drm_device *dev = encoder->dev;
2041 struct drm_i915_private *dev_priv = dev->dev_private;
d6c50ff8 2042
6e3c9717 2043 if (intel_crtc->config->has_audio) {
69bfe1a9 2044 intel_audio_codec_disable(intel_encoder);
d45a0bf5
PZ		 2045 intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO);
2046 }
2831d842 2047
d6c50ff8
PZ		 2048 if (type == INTEL_OUTPUT_EDP) {
2049 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2050
c395578e 2051 intel_edp_drrs_disable(intel_dp);
0bc12bcb 2052 intel_psr_disable(intel_dp);
4be73780 2053 intel_edp_backlight_off(intel_dp);
d6c50ff8 2054 }
72662e10 2055}
79f689aa 2056
e0b01be4
DV		 2057static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv,
2058 struct intel_shared_dpll *pll)
2059{
3e369b76 2060 I915_WRITE(WRPLL_CTL(pll->id), pll->config.hw_state.wrpll);
e0b01be4
DV		 2061 POSTING_READ(WRPLL_CTL(pll->id));
2062 udelay(20);
2063}
2064
12030431
DV		 2065static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv,
2066 struct intel_shared_dpll *pll)
2067{
2068 uint32_t val;
2069
2070 val = I915_READ(WRPLL_CTL(pll->id));
12030431
DV		 2071 I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE);
2072 POSTING_READ(WRPLL_CTL(pll->id));
2073}
2074
d452c5b6
DV		 2075static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2076 struct intel_shared_dpll *pll,
2077 struct intel_dpll_hw_state *hw_state)
2078{
2079 uint32_t val;
2080
f458ebbc 2081 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
d452c5b6
DV		 2082 return false;
2083
2084 val = I915_READ(WRPLL_CTL(pll->id));
2085 hw_state->wrpll = val;
2086
2087 return val & WRPLL_PLL_ENABLE;
2088}
2089
ca1381b5 2090static const char * const hsw_ddi_pll_names[] = {
9cd86933
DV		 2091 "WRPLL 1",
2092 "WRPLL 2",
2093};
2094
143b307c 2095static void hsw_shared_dplls_init(struct drm_i915_private *dev_priv)
79f689aa 2096{
9cd86933
DV		 2097 int i;
2098
716c2e55 2099 dev_priv->num_shared_dpll = 2;
9cd86933 2100
716c2e55 2101 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9cd86933
DV		 2102 dev_priv->shared_dplls[i].id = i;
2103 dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i];
12030431 2104 dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable;
e0b01be4 2105 dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable;
d452c5b6
DV		 2106 dev_priv->shared_dplls[i].get_hw_state =
2107 hsw_ddi_pll_get_hw_state;
9cd86933 2108 }
143b307c
DL		 2109}
2110
d1a2dc78
S		 2111static const char * const skl_ddi_pll_names[] = {
2112 "DPLL 1",
2113 "DPLL 2",
2114 "DPLL 3",
2115};
2116
2117struct skl_dpll_regs {
2118 u32 ctl, cfgcr1, cfgcr2;
2119};
2120
2121/* this array is indexed by the *shared* pll id */
2122static const struct skl_dpll_regs skl_dpll_regs[3] = {
2123 {
2124 /* DPLL 1 */
2125 .ctl = LCPLL2_CTL,
2126 .cfgcr1 = DPLL1_CFGCR1,
2127 .cfgcr2 = DPLL1_CFGCR2,
2128 },
2129 {
2130 /* DPLL 2 */
2131 .ctl = WRPLL_CTL1,
2132 .cfgcr1 = DPLL2_CFGCR1,
2133 .cfgcr2 = DPLL2_CFGCR2,
2134 },
2135 {
2136 /* DPLL 3 */
2137 .ctl = WRPLL_CTL2,
2138 .cfgcr1 = DPLL3_CFGCR1,
2139 .cfgcr2 = DPLL3_CFGCR2,
2140 },
2141};
2142
2143static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
2144 struct intel_shared_dpll *pll)
2145{
2146 uint32_t val;
2147 unsigned int dpll;
2148 const struct skl_dpll_regs *regs = skl_dpll_regs;
2149
2150 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2151 dpll = pll->id + 1;
2152
2153 val = I915_READ(DPLL_CTRL1);
2154
2155 val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
71cd8423 2156 DPLL_CTRL1_LINK_RATE_MASK(dpll));
d1a2dc78
S		 2157 val |= pll->config.hw_state.ctrl1 << (dpll * 6);
2158
2159 I915_WRITE(DPLL_CTRL1, val);
2160 POSTING_READ(DPLL_CTRL1);
2161
2162 I915_WRITE(regs[pll->id].cfgcr1, pll->config.hw_state.cfgcr1);
2163 I915_WRITE(regs[pll->id].cfgcr2, pll->config.hw_state.cfgcr2);
2164 POSTING_READ(regs[pll->id].cfgcr1);
2165 POSTING_READ(regs[pll->id].cfgcr2);
2166
2167 /* the enable bit is always bit 31 */
2168 I915_WRITE(regs[pll->id].ctl,
2169 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE);
2170
2171 if (wait_for(I915_READ(DPLL_STATUS) & DPLL_LOCK(dpll), 5))
2172 DRM_ERROR("DPLL %d not locked\n", dpll);
2173}
2174
2175static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
2176 struct intel_shared_dpll *pll)
2177{
2178 const struct skl_dpll_regs *regs = skl_dpll_regs;
2179
2180 /* the enable bit is always bit 31 */
2181 I915_WRITE(regs[pll->id].ctl,
2182 I915_READ(regs[pll->id].ctl) & ~LCPLL_PLL_ENABLE);
2183 POSTING_READ(regs[pll->id].ctl);
2184}
2185
2186static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2187 struct intel_shared_dpll *pll,
2188 struct intel_dpll_hw_state *hw_state)
2189{
2190 uint32_t val;
2191 unsigned int dpll;
2192 const struct skl_dpll_regs *regs = skl_dpll_regs;
2193
2194 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2195 return false;
2196
2197 /* DPLL0 is not part of the shared DPLLs, so pll->id is 0 for DPLL1 */
2198 dpll = pll->id + 1;
2199
2200 val = I915_READ(regs[pll->id].ctl);
2201 if (!(val & LCPLL_PLL_ENABLE))
2202 return false;
2203
2204 val = I915_READ(DPLL_CTRL1);
2205 hw_state->ctrl1 = (val >> (dpll * 6)) & 0x3f;
2206
2207 /* avoid reading back stale values if HDMI mode is not enabled */
2208 if (val & DPLL_CTRL1_HDMI_MODE(dpll)) {
2209 hw_state->cfgcr1 = I915_READ(regs[pll->id].cfgcr1);
2210 hw_state->cfgcr2 = I915_READ(regs[pll->id].cfgcr2);
2211 }
2212
2213 return true;
2214}
2215
2216static void skl_shared_dplls_init(struct drm_i915_private *dev_priv)
2217{
2218 int i;
2219
2220 dev_priv->num_shared_dpll = 3;
2221
2222 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2223 dev_priv->shared_dplls[i].id = i;
2224 dev_priv->shared_dplls[i].name = skl_ddi_pll_names[i];
2225 dev_priv->shared_dplls[i].disable = skl_ddi_pll_disable;
2226 dev_priv->shared_dplls[i].enable = skl_ddi_pll_enable;
2227 dev_priv->shared_dplls[i].get_hw_state =
2228 skl_ddi_pll_get_hw_state;
2229 }
2230}
2231
5c6706e5
VK		 2232static void broxton_phy_init(struct drm_i915_private *dev_priv,
2233 enum dpio_phy phy)
2234{
2235 enum port port;
2236 uint32_t val;
2237
2238 val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
2239 val |= GT_DISPLAY_POWER_ON(phy);
2240 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
2241
2242 /* Considering 10ms timeout until BSpec is updated */
2243 if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & PHY_POWER_GOOD, 10))
2244 DRM_ERROR("timeout during PHY%d power on\n", phy);
2245
2246 for (port = (phy == DPIO_PHY0 ? PORT_B : PORT_A);
2247 port <= (phy == DPIO_PHY0 ? PORT_C : PORT_A); port++) {
2248 int lane;
2249
2250 for (lane = 0; lane < 4; lane++) {
2251 val = I915_READ(BXT_PORT_TX_DW14_LN(port, lane));
2252 /*
2253 * Note that on CHV this flag is called UPAR, but has
2254 * the same function.
2255 */
2256 val &= ~LATENCY_OPTIM;
2257 if (lane != 1)
2258 val |= LATENCY_OPTIM;
2259
2260 I915_WRITE(BXT_PORT_TX_DW14_LN(port, lane), val);
2261 }
2262 }
2263
2264 /* Program PLL Rcomp code offset */
2265 val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
2266 val &= ~IREF0RC_OFFSET_MASK;
2267 val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
2268 I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
2269
2270 val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
2271 val &= ~IREF1RC_OFFSET_MASK;
2272 val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
2273 I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
2274
2275 /* Program power gating */
2276 val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
2277 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
2278 SUS_CLK_CONFIG;
2279 I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
2280
2281 if (phy == DPIO_PHY0) {
2282 val = I915_READ(BXT_PORT_CL2CM_DW6_BC);
2283 val |= DW6_OLDO_DYN_PWR_DOWN_EN;
2284 I915_WRITE(BXT_PORT_CL2CM_DW6_BC, val);
2285 }
2286
2287 val = I915_READ(BXT_PORT_CL1CM_DW30(phy));
2288 val &= ~OCL2_LDOFUSE_PWR_DIS;
2289 /*
2290 * On PHY1 disable power on the second channel, since no port is
2291 * connected there. On PHY0 both channels have a port, so leave it
2292 * enabled.
2293 * TODO: port C is only connected on BXT-P, so on BXT0/1 we should
2294 * power down the second channel on PHY0 as well.
2295 */
2296 if (phy == DPIO_PHY1)
2297 val |= OCL2_LDOFUSE_PWR_DIS;
2298 I915_WRITE(BXT_PORT_CL1CM_DW30(phy), val);
2299
2300 if (phy == DPIO_PHY0) {
2301 uint32_t grc_code;
2302 /*
2303 * PHY0 isn't connected to an RCOMP resistor so copy over
2304 * the corresponding calibrated value from PHY1, and disable
2305 * the automatic calibration on PHY0.
2306 */
2307 if (wait_for(I915_READ(BXT_PORT_REF_DW3(DPIO_PHY1)) & GRC_DONE,
2308 10))
2309 DRM_ERROR("timeout waiting for PHY1 GRC\n");
2310
2311 val = I915_READ(BXT_PORT_REF_DW6(DPIO_PHY1));
2312 val = (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
2313 grc_code = val << GRC_CODE_FAST_SHIFT |
2314 val << GRC_CODE_SLOW_SHIFT |
2315 val;
2316 I915_WRITE(BXT_PORT_REF_DW6(DPIO_PHY0), grc_code);
2317
2318 val = I915_READ(BXT_PORT_REF_DW8(DPIO_PHY0));
2319 val |= GRC_DIS | GRC_RDY_OVRD;
2320 I915_WRITE(BXT_PORT_REF_DW8(DPIO_PHY0), val);
2321 }
2322
2323 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2324 val |= COMMON_RESET_DIS;
2325 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2326}
2327
2328void broxton_ddi_phy_init(struct drm_device *dev)
2329{
2330 /* Enable PHY1 first since it provides Rcomp for PHY0 */
2331 broxton_phy_init(dev->dev_private, DPIO_PHY1);
2332 broxton_phy_init(dev->dev_private, DPIO_PHY0);
2333}
2334
2335static void broxton_phy_uninit(struct drm_i915_private *dev_priv,
2336 enum dpio_phy phy)
2337{
2338 uint32_t val;
2339
2340 val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
2341 val &= ~COMMON_RESET_DIS;
2342 I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
2343}
2344
2345void broxton_ddi_phy_uninit(struct drm_device *dev)
2346{
2347 struct drm_i915_private *dev_priv = dev->dev_private;
2348
2349 broxton_phy_uninit(dev_priv, DPIO_PHY1);
2350 broxton_phy_uninit(dev_priv, DPIO_PHY0);
2351
2352 /* FIXME: do this in broxton_phy_uninit per phy */
2353 I915_WRITE(BXT_P_CR_GT_DISP_PWRON, 0);
2354}
2355
dfb82408
S		 2356static const char * const bxt_ddi_pll_names[] = {
2357 "PORT PLL A",
2358 "PORT PLL B",
2359 "PORT PLL C",
2360};
2361
2362static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
2363 struct intel_shared_dpll *pll)
2364{
2365 uint32_t temp;
2366 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2367
2368 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2369 temp &= ~PORT_PLL_REF_SEL;
2370 /* Non-SSC reference */
2371 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2372
2373 /* Disable 10 bit clock */
2374 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2375 temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
2376 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2377
2378 /* Write P1 & P2 */
2379 temp = I915_READ(BXT_PORT_PLL_EBB_0(port));
2380 temp &= ~(PORT_PLL_P1_MASK | PORT_PLL_P2_MASK);
2381 temp |= pll->config.hw_state.ebb0;
2382 I915_WRITE(BXT_PORT_PLL_EBB_0(port), temp);
2383
2384 /* Write M2 integer */
2385 temp = I915_READ(BXT_PORT_PLL(port, 0));
2386 temp &= ~PORT_PLL_M2_MASK;
2387 temp |= pll->config.hw_state.pll0;
2388 I915_WRITE(BXT_PORT_PLL(port, 0), temp);
2389
2390 /* Write N */
2391 temp = I915_READ(BXT_PORT_PLL(port, 1));
2392 temp &= ~PORT_PLL_N_MASK;
2393 temp |= pll->config.hw_state.pll1;
2394 I915_WRITE(BXT_PORT_PLL(port, 1), temp);
2395
2396 /* Write M2 fraction */
2397 temp = I915_READ(BXT_PORT_PLL(port, 2));
2398 temp &= ~PORT_PLL_M2_FRAC_MASK;
2399 temp |= pll->config.hw_state.pll2;
2400 I915_WRITE(BXT_PORT_PLL(port, 2), temp);
2401
2402 /* Write M2 fraction enable */
2403 temp = I915_READ(BXT_PORT_PLL(port, 3));
2404 temp &= ~PORT_PLL_M2_FRAC_ENABLE;
2405 temp |= pll->config.hw_state.pll3;
2406 I915_WRITE(BXT_PORT_PLL(port, 3), temp);
2407
2408 /* Write coeff */
2409 temp = I915_READ(BXT_PORT_PLL(port, 6));
2410 temp &= ~PORT_PLL_PROP_COEFF_MASK;
2411 temp &= ~PORT_PLL_INT_COEFF_MASK;
2412 temp &= ~PORT_PLL_GAIN_CTL_MASK;
2413 temp |= pll->config.hw_state.pll6;
2414 I915_WRITE(BXT_PORT_PLL(port, 6), temp);
2415
2416 /* Write calibration val */
2417 temp = I915_READ(BXT_PORT_PLL(port, 8));
2418 temp &= ~PORT_PLL_TARGET_CNT_MASK;
2419 temp |= pll->config.hw_state.pll8;
2420 I915_WRITE(BXT_PORT_PLL(port, 8), temp);
2421
b6dc71f3
VK		 2422 temp = I915_READ(BXT_PORT_PLL(port, 9));
2423 temp &= ~PORT_PLL_LOCK_THRESHOLD_MASK;
2424 temp |= (5 << 1);
2425 I915_WRITE(BXT_PORT_PLL(port, 9), temp);
2426
2427 temp = I915_READ(BXT_PORT_PLL(port, 10));
2428 temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
2429 temp &= ~PORT_PLL_DCO_AMP_MASK;
2430 temp |= pll->config.hw_state.pll10;
2431 I915_WRITE(BXT_PORT_PLL(port, 10), temp);
dfb82408
S		 2432
2433 /* Recalibrate with new settings */
2434 temp = I915_READ(BXT_PORT_PLL_EBB_4(port));
2435 temp |= PORT_PLL_RECALIBRATE;
2436 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2437 /* Enable 10 bit clock */
2438 temp |= PORT_PLL_10BIT_CLK_ENABLE;
2439 I915_WRITE(BXT_PORT_PLL_EBB_4(port), temp);
2440
2441 /* Enable PLL */
2442 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2443 temp |= PORT_PLL_ENABLE;
2444 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2445 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2446
2447 if (wait_for_atomic_us((I915_READ(BXT_PORT_PLL_ENABLE(port)) &
2448 PORT_PLL_LOCK), 200))
2449 DRM_ERROR("PLL %d not locked\n", port);
2450
2451 /*
2452 * While we write to the group register to program all lanes at once we
2453 * can read only lane registers and we pick lanes 0/1 for that.
2454 */
2455 temp = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2456 temp &= ~LANE_STAGGER_MASK;
2457 temp &= ~LANESTAGGER_STRAP_OVRD;
2458 temp |= pll->config.hw_state.pcsdw12;
2459 I915_WRITE(BXT_PORT_PCS_DW12_GRP(port), temp);
2460}
2461
2462static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2463 struct intel_shared_dpll *pll)
2464{
2465 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2466 uint32_t temp;
2467
2468 temp = I915_READ(BXT_PORT_PLL_ENABLE(port));
2469 temp &= ~PORT_PLL_ENABLE;
2470 I915_WRITE(BXT_PORT_PLL_ENABLE(port), temp);
2471 POSTING_READ(BXT_PORT_PLL_ENABLE(port));
2472}
2473
2474static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2475 struct intel_shared_dpll *pll,
2476 struct intel_dpll_hw_state *hw_state)
2477{
2478 enum port port = (enum port)pll->id; /* 1:1 port->PLL mapping */
2479 uint32_t val;
2480
2481 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
2482 return false;
2483
2484 val = I915_READ(BXT_PORT_PLL_ENABLE(port));
2485 if (!(val & PORT_PLL_ENABLE))
2486 return false;
2487
2488 hw_state->ebb0 = I915_READ(BXT_PORT_PLL_EBB_0(port));
2489 hw_state->pll0 = I915_READ(BXT_PORT_PLL(port, 0));
2490 hw_state->pll1 = I915_READ(BXT_PORT_PLL(port, 1));
2491 hw_state->pll2 = I915_READ(BXT_PORT_PLL(port, 2));
2492 hw_state->pll3 = I915_READ(BXT_PORT_PLL(port, 3));
2493 hw_state->pll6 = I915_READ(BXT_PORT_PLL(port, 6));
2494 hw_state->pll8 = I915_READ(BXT_PORT_PLL(port, 8));
b6dc71f3 2495 hw_state->pll10 = I915_READ(BXT_PORT_PLL(port, 10));
dfb82408
S		 2496 /*
2497 * While we write to the group register to program all lanes at once we
2498 * can read only lane registers. We configure all lanes the same way, so
2499 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2500 */
2501 hw_state->pcsdw12 = I915_READ(BXT_PORT_PCS_DW12_LN01(port));
2502 if (I915_READ(BXT_PORT_PCS_DW12_LN23(port) != hw_state->pcsdw12))
2503 DRM_DEBUG_DRIVER("lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2504 hw_state->pcsdw12,
2505 I915_READ(BXT_PORT_PCS_DW12_LN23(port)));
2506
2507 return true;
2508}
2509
2510static void bxt_shared_dplls_init(struct drm_i915_private *dev_priv)
2511{
2512 int i;
2513
2514 dev_priv->num_shared_dpll = 3;
2515
2516 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
2517 dev_priv->shared_dplls[i].id = i;
2518 dev_priv->shared_dplls[i].name = bxt_ddi_pll_names[i];
2519 dev_priv->shared_dplls[i].disable = bxt_ddi_pll_disable;
2520 dev_priv->shared_dplls[i].enable = bxt_ddi_pll_enable;
2521 dev_priv->shared_dplls[i].get_hw_state =
2522 bxt_ddi_pll_get_hw_state;
2523 }
2524}
2525
143b307c
DL		 2526void intel_ddi_pll_init(struct drm_device *dev)
2527{
2528 struct drm_i915_private *dev_priv = dev->dev_private;
2529 uint32_t val = I915_READ(LCPLL_CTL);
5d96d8af 2530 int cdclk_freq;
143b307c 2531
d1a2dc78
S		 2532 if (IS_SKYLAKE(dev))
2533 skl_shared_dplls_init(dev_priv);
dfb82408
S		 2534 else if (IS_BROXTON(dev))
2535 bxt_shared_dplls_init(dev_priv);
d1a2dc78
S		 2536 else
2537 hsw_shared_dplls_init(dev_priv);
79f689aa 2538
5d96d8af
DL		 2539 cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
2540 DRM_DEBUG_KMS("CDCLK running at %dKHz\n", cdclk_freq);
79f689aa 2541
121643c2 2542 if (IS_SKYLAKE(dev)) {
5d96d8af 2543 dev_priv->skl_boot_cdclk = cdclk_freq;
121643c2
S		 2544 if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE))
2545 DRM_ERROR("LCPLL1 is disabled\n");
5d96d8af
DL		 2546 else
2547 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
f8437dd1
VK		 2548 } else if (IS_BROXTON(dev)) {
2549 broxton_init_cdclk(dev);
5c6706e5 2550 broxton_ddi_phy_init(dev);
121643c2
S		 2551 } else {
2552 /*
2553 * The LCPLL register should be turned on by the BIOS. For now
2554 * let's just check its state and print errors in case
2555 * something is wrong. Don't even try to turn it on.
2556 */
2557
2558 if (val & LCPLL_CD_SOURCE_FCLK)
2559 DRM_ERROR("CDCLK source is not LCPLL\n");
79f689aa 2560
121643c2
S		 2561 if (val & LCPLL_PLL_DISABLE)
2562 DRM_ERROR("LCPLL is disabled\n");
2563 }
79f689aa 2564}
c19b0669
PZ		 2565
2566void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder)
2567{
174edf1f
PZ		 2568 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2569 struct intel_dp *intel_dp = &intel_dig_port->dp;
c19b0669 2570 struct drm_i915_private *dev_priv = encoder->dev->dev_private;
174edf1f 2571 enum port port = intel_dig_port->port;
c19b0669 2572 uint32_t val;
f3e227df 2573 bool wait = false;
c19b0669
PZ		 2574
2575 if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) {
2576 val = I915_READ(DDI_BUF_CTL(port));
2577 if (val & DDI_BUF_CTL_ENABLE) {
2578 val &= ~DDI_BUF_CTL_ENABLE;
2579 I915_WRITE(DDI_BUF_CTL(port), val);
2580 wait = true;
2581 }
2582
2583 val = I915_READ(DP_TP_CTL(port));
2584 val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK);
2585 val |= DP_TP_CTL_LINK_TRAIN_PAT1;
2586 I915_WRITE(DP_TP_CTL(port), val);
2587 POSTING_READ(DP_TP_CTL(port));
2588
2589 if (wait)
2590 intel_wait_ddi_buf_idle(dev_priv, port);
2591 }
2592
0e32b39c 2593 val = DP_TP_CTL_ENABLE |
c19b0669 2594 DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE;
0e32b39c
DA		 2595 if (intel_dp->is_mst)
2596 val |= DP_TP_CTL_MODE_MST;
2597 else {
2598 val |= DP_TP_CTL_MODE_SST;
2599 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
2600 val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE;
2601 }
c19b0669
PZ		 2602 I915_WRITE(DP_TP_CTL(port), val);
2603 POSTING_READ(DP_TP_CTL(port));
2604
2605 intel_dp->DP |= DDI_BUF_CTL_ENABLE;
2606 I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP);
2607 POSTING_READ(DDI_BUF_CTL(port));
2608
2609 udelay(600);
2610}
00c09d70 2611
1ad960f2
PZ		 2612void intel_ddi_fdi_disable(struct drm_crtc *crtc)
2613{
2614 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
2615 struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc);
2616 uint32_t val;
2617
2618 intel_ddi_post_disable(intel_encoder);
2619
2620 val = I915_READ(_FDI_RXA_CTL);
2621 val &= ~FDI_RX_ENABLE;
2622 I915_WRITE(_FDI_RXA_CTL, val);
2623
2624 val = I915_READ(_FDI_RXA_MISC);
2625 val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK);
2626 val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2);
2627 I915_WRITE(_FDI_RXA_MISC, val);
2628
2629 val = I915_READ(_FDI_RXA_CTL);
2630 val &= ~FDI_PCDCLK;
2631 I915_WRITE(_FDI_RXA_CTL, val);
2632
2633 val = I915_READ(_FDI_RXA_CTL);
2634 val &= ~FDI_RX_PLL_ENABLE;
2635 I915_WRITE(_FDI_RXA_CTL, val);
2636}
2637
6801c18c 2638void intel_ddi_get_config(struct intel_encoder *encoder,
5cec258b 2639 struct intel_crtc_state *pipe_config)
045ac3b5
JB		 2640{
2641 struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
2642 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
0cb09a97 2643 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bbd440fb 2644 struct intel_hdmi *intel_hdmi;
045ac3b5
JB		 2645 u32 temp, flags = 0;
2646
2647 temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
2648 if (temp & TRANS_DDI_PHSYNC)
2649 flags |= DRM_MODE_FLAG_PHSYNC;
2650 else
2651 flags |= DRM_MODE_FLAG_NHSYNC;
2652 if (temp & TRANS_DDI_PVSYNC)
2653 flags |= DRM_MODE_FLAG_PVSYNC;
2654 else
2655 flags |= DRM_MODE_FLAG_NVSYNC;
2656
2d112de7 2657 pipe_config->base.adjusted_mode.flags |= flags;
42571aef
VS		 2658
2659 switch (temp & TRANS_DDI_BPC_MASK) {
2660 case TRANS_DDI_BPC_6:
2661 pipe_config->pipe_bpp = 18;
2662 break;
2663 case TRANS_DDI_BPC_8:
2664 pipe_config->pipe_bpp = 24;
2665 break;
2666 case TRANS_DDI_BPC_10:
2667 pipe_config->pipe_bpp = 30;
2668 break;
2669 case TRANS_DDI_BPC_12:
2670 pipe_config->pipe_bpp = 36;
2671 break;
2672 default:
2673 break;
2674 }
eb14cb74
VS		 2675
2676 switch (temp & TRANS_DDI_MODE_SELECT_MASK) {
2677 case TRANS_DDI_MODE_SELECT_HDMI:
6897b4b5 2678 pipe_config->has_hdmi_sink = true;
bbd440fb
DV		 2679 intel_hdmi = enc_to_intel_hdmi(&encoder->base);
2680
2681 if (intel_hdmi->infoframe_enabled(&encoder->base))
2682 pipe_config->has_infoframe = true;
cbc572a9 2683 break;
eb14cb74
VS		 2684 case TRANS_DDI_MODE_SELECT_DVI:
2685 case TRANS_DDI_MODE_SELECT_FDI:
2686 break;
2687 case TRANS_DDI_MODE_SELECT_DP_SST:
2688 case TRANS_DDI_MODE_SELECT_DP_MST:
2689 pipe_config->has_dp_encoder = true;
2690 intel_dp_get_m_n(intel_crtc, pipe_config);
2691 break;
2692 default:
2693 break;
2694 }
10214420 2695
f458ebbc 2696 if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_AUDIO)) {
a60551b1 2697 temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
82910ac6 2698 if (temp & AUDIO_OUTPUT_ENABLE(intel_crtc->pipe))
a60551b1
PZ		 2699 pipe_config->has_audio = true;
2700 }
9ed109a7 2701
10214420
DV		 2702 if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp &&
2703 pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2704 /*
2705 * This is a big fat ugly hack.
2706 *
2707 * Some machines in UEFI boot mode provide us a VBT that has 18
2708 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2709 * unknown we fail to light up. Yet the same BIOS boots up with
2710 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2711 * max, not what it tells us to use.
2712 *
2713 * Note: This will still be broken if the eDP panel is not lit
2714 * up by the BIOS, and thus we can't get the mode at module
2715 * load.
2716 */
2717 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2718 pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2719 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2720 }
11578553 2721
22606a18 2722 intel_ddi_clock_get(encoder, pipe_config);
045ac3b5
JB		 2723}
2724
00c09d70
PZ		 2725static void intel_ddi_destroy(struct drm_encoder *encoder)
2726{
2727 /* HDMI has nothing special to destroy, so we can go with this. */
2728 intel_dp_encoder_destroy(encoder);
2729}
2730
5bfe2ac0 2731static bool intel_ddi_compute_config(struct intel_encoder *encoder,
5cec258b 2732 struct intel_crtc_state *pipe_config)
00c09d70 2733{
5bfe2ac0 2734 int type = encoder->type;
eccb140b 2735 int port = intel_ddi_get_encoder_port(encoder);
00c09d70 2736
5bfe2ac0 2737 WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n");
00c09d70 2738
eccb140b
DV		 2739 if (port == PORT_A)
2740 pipe_config->cpu_transcoder = TRANSCODER_EDP;
2741
00c09d70 2742 if (type == INTEL_OUTPUT_HDMI)
5bfe2ac0 2743 return intel_hdmi_compute_config(encoder, pipe_config);
00c09d70 2744 else
5bfe2ac0 2745 return intel_dp_compute_config(encoder, pipe_config);
00c09d70
PZ		 2746}
2747
2748static const struct drm_encoder_funcs intel_ddi_funcs = {
2749 .destroy = intel_ddi_destroy,
2750};
2751
4a28ae58
PZ		 2752static struct intel_connector *
2753intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port)
2754{
2755 struct intel_connector *connector;
2756 enum port port = intel_dig_port->port;
2757
9bdbd0b9 2758 connector = intel_connector_alloc();
4a28ae58
PZ		 2759 if (!connector)
2760 return NULL;
2761
2762 intel_dig_port->dp.output_reg = DDI_BUF_CTL(port);
2763 if (!intel_dp_init_connector(intel_dig_port, connector)) {
2764 kfree(connector);
2765 return NULL;
2766 }
2767
2768 return connector;
2769}
2770
2771static struct intel_connector *
2772intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port)
2773{
2774 struct intel_connector *connector;
2775 enum port port = intel_dig_port->port;
2776
9bdbd0b9 2777 connector = intel_connector_alloc();
4a28ae58
PZ		 2778 if (!connector)
2779 return NULL;
2780
2781 intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port);
2782 intel_hdmi_init_connector(intel_dig_port, connector);
2783
2784 return connector;
2785}
2786
00c09d70
PZ		 2787void intel_ddi_init(struct drm_device *dev, enum port port)
2788{
876a8cdf 2789 struct drm_i915_private *dev_priv = dev->dev_private;
00c09d70
PZ		 2790 struct intel_digital_port *intel_dig_port;
2791 struct intel_encoder *intel_encoder;
2792 struct drm_encoder *encoder;
311a2094
PZ		 2793 bool init_hdmi, init_dp;
2794
2795 init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi ||
2796 dev_priv->vbt.ddi_port_info[port].supports_hdmi);
2797 init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp;
2798 if (!init_dp && !init_hdmi) {
f68d697e 2799 DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible, assuming it is\n",
311a2094
PZ		 2800 port_name(port));
2801 init_hdmi = true;
2802 init_dp = true;
2803 }
00c09d70 2804
b14c5679 2805 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
00c09d70
PZ		 2806 if (!intel_dig_port)
2807 return;
2808
00c09d70
PZ		 2809 intel_encoder = &intel_dig_port->base;
2810 encoder = &intel_encoder->base;
2811
2812 drm_encoder_init(dev, encoder, &intel_ddi_funcs,
2813 DRM_MODE_ENCODER_TMDS);
00c09d70 2814
5bfe2ac0 2815 intel_encoder->compute_config = intel_ddi_compute_config;
00c09d70
PZ		 2816 intel_encoder->enable = intel_enable_ddi;
2817 intel_encoder->pre_enable = intel_ddi_pre_enable;
2818 intel_encoder->disable = intel_disable_ddi;
2819 intel_encoder->post_disable = intel_ddi_post_disable;
2820 intel_encoder->get_hw_state = intel_ddi_get_hw_state;
045ac3b5 2821 intel_encoder->get_config = intel_ddi_get_config;
00c09d70
PZ		 2822
2823 intel_dig_port->port = port;
bcf53de4
SM		 2824 intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) &
2825 (DDI_BUF_PORT_REVERSAL |
2826 DDI_A_4_LANES);
00c09d70
PZ		 2827
2828 intel_encoder->type = INTEL_OUTPUT_UNKNOWN;
f68d697e 2829 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
bc079e8b 2830 intel_encoder->cloneable = 0;
00c09d70 2831
f68d697e
CW		 2832 if (init_dp) {
2833 if (!intel_ddi_init_dp_connector(intel_dig_port))
2834 goto err;
13cf5504 2835
f68d697e 2836 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
5fcece80 2837 dev_priv->hotplug.irq_port[port] = intel_dig_port;
f68d697e 2838 }
21a8e6a4 2839
311a2094
PZ		 2840 /* In theory we don't need the encoder->type check, but leave it just in
2841 * case we have some really bad VBTs... */
f68d697e
CW		 2842 if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) {
2843 if (!intel_ddi_init_hdmi_connector(intel_dig_port))
2844 goto err;
21a8e6a4 2845 }
f68d697e
CW		 2846
2847 return;
2848
2849err:
2850 drm_encoder_cleanup(encoder);
2851 kfree(intel_dig_port);
00c09d70 2852}
Linux kernel - Deliverables
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