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45244b87 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
28 | #include "i915_drv.h" | |
29 | #include "intel_drv.h" | |
30 | ||
31 | /* HDMI/DVI modes ignore everything but the last 2 items. So we share | |
32 | * them for both DP and FDI transports, allowing those ports to | |
33 | * automatically adapt to HDMI connections as well | |
34 | */ | |
35 | static const u32 hsw_ddi_translations_dp[] = { | |
36 | 0x00FFFFFF, 0x0006000E, /* DP parameters */ | |
37 | 0x00D75FFF, 0x0005000A, | |
38 | 0x00C30FFF, 0x00040006, | |
39 | 0x80AAAFFF, 0x000B0000, | |
40 | 0x00FFFFFF, 0x0005000A, | |
41 | 0x00D75FFF, 0x000C0004, | |
42 | 0x80C30FFF, 0x000B0000, | |
43 | 0x00FFFFFF, 0x00040006, | |
44 | 0x80D75FFF, 0x000B0000, | |
45244b87 ED |
45 | }; |
46 | ||
47 | static const u32 hsw_ddi_translations_fdi[] = { | |
48 | 0x00FFFFFF, 0x0007000E, /* FDI parameters */ | |
49 | 0x00D75FFF, 0x000F000A, | |
50 | 0x00C30FFF, 0x00060006, | |
51 | 0x00AAAFFF, 0x001E0000, | |
52 | 0x00FFFFFF, 0x000F000A, | |
53 | 0x00D75FFF, 0x00160004, | |
54 | 0x00C30FFF, 0x001E0000, | |
55 | 0x00FFFFFF, 0x00060006, | |
56 | 0x00D75FFF, 0x001E0000, | |
6acab15a PZ |
57 | }; |
58 | ||
59 | static const u32 hsw_ddi_translations_hdmi[] = { | |
60 | /* Idx NT mV diff T mV diff db */ | |
61 | 0x00FFFFFF, 0x0006000E, /* 0: 400 400 0 */ | |
62 | 0x00E79FFF, 0x000E000C, /* 1: 400 500 2 */ | |
63 | 0x00D75FFF, 0x0005000A, /* 2: 400 600 3.5 */ | |
64 | 0x00FFFFFF, 0x0005000A, /* 3: 600 600 0 */ | |
65 | 0x00E79FFF, 0x001D0007, /* 4: 600 750 2 */ | |
66 | 0x00D75FFF, 0x000C0004, /* 5: 600 900 3.5 */ | |
67 | 0x00FFFFFF, 0x00040006, /* 6: 800 800 0 */ | |
68 | 0x80E79FFF, 0x00030002, /* 7: 800 1000 2 */ | |
69 | 0x00FFFFFF, 0x00140005, /* 8: 850 850 0 */ | |
70 | 0x00FFFFFF, 0x000C0004, /* 9: 900 900 0 */ | |
71 | 0x00FFFFFF, 0x001C0003, /* 10: 950 950 0 */ | |
72 | 0x80FFFFFF, 0x00030002, /* 11: 1000 1000 0 */ | |
45244b87 ED |
73 | }; |
74 | ||
300644c7 | 75 | static const u32 bdw_ddi_translations_edp[] = { |
e1b22732 | 76 | 0x00FFFFFF, 0x00000012, /* eDP parameters */ |
300644c7 PZ |
77 | 0x00EBAFFF, 0x00020011, |
78 | 0x00C71FFF, 0x0006000F, | |
9576c27f | 79 | 0x00AAAFFF, 0x000E000A, |
300644c7 PZ |
80 | 0x00FFFFFF, 0x00020011, |
81 | 0x00DB6FFF, 0x0005000F, | |
82 | 0x00BEEFFF, 0x000A000C, | |
83 | 0x00FFFFFF, 0x0005000F, | |
84 | 0x00DB6FFF, 0x000A000C, | |
300644c7 PZ |
85 | 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/ |
86 | }; | |
87 | ||
e58623cb AR |
88 | static const u32 bdw_ddi_translations_dp[] = { |
89 | 0x00FFFFFF, 0x0007000E, /* DP parameters */ | |
90 | 0x00D75FFF, 0x000E000A, | |
91 | 0x00BEFFFF, 0x00140006, | |
9576c27f | 92 | 0x80B2CFFF, 0x001B0002, |
e58623cb AR |
93 | 0x00FFFFFF, 0x000E000A, |
94 | 0x00D75FFF, 0x00180004, | |
95 | 0x80CB2FFF, 0x001B0002, | |
96 | 0x00F7DFFF, 0x00180004, | |
97 | 0x80D75FFF, 0x001B0002, | |
e58623cb AR |
98 | 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/ |
99 | }; | |
100 | ||
101 | static const u32 bdw_ddi_translations_fdi[] = { | |
102 | 0x00FFFFFF, 0x0001000E, /* FDI parameters */ | |
103 | 0x00D75FFF, 0x0004000A, | |
104 | 0x00C30FFF, 0x00070006, | |
105 | 0x00AAAFFF, 0x000C0000, | |
106 | 0x00FFFFFF, 0x0004000A, | |
107 | 0x00D75FFF, 0x00090004, | |
108 | 0x00C30FFF, 0x000C0000, | |
109 | 0x00FFFFFF, 0x00070006, | |
110 | 0x00D75FFF, 0x000C0000, | |
111 | 0x00FFFFFF, 0x00140006 /* HDMI parameters 800mV 0dB*/ | |
112 | }; | |
113 | ||
20f4dbe4 | 114 | enum port intel_ddi_get_encoder_port(struct intel_encoder *intel_encoder) |
fc914639 | 115 | { |
0bdee30e | 116 | struct drm_encoder *encoder = &intel_encoder->base; |
fc914639 PZ |
117 | int type = intel_encoder->type; |
118 | ||
174edf1f | 119 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP || |
00c09d70 | 120 | type == INTEL_OUTPUT_HDMI || type == INTEL_OUTPUT_UNKNOWN) { |
174edf1f PZ |
121 | struct intel_digital_port *intel_dig_port = |
122 | enc_to_dig_port(encoder); | |
123 | return intel_dig_port->port; | |
0bdee30e | 124 | |
fc914639 PZ |
125 | } else if (type == INTEL_OUTPUT_ANALOG) { |
126 | return PORT_E; | |
0bdee30e | 127 | |
fc914639 PZ |
128 | } else { |
129 | DRM_ERROR("Invalid DDI encoder type %d\n", type); | |
130 | BUG(); | |
131 | } | |
132 | } | |
133 | ||
e58623cb AR |
134 | /* |
135 | * Starting with Haswell, DDI port buffers must be programmed with correct | |
136 | * values in advance. The buffer values are different for FDI and DP modes, | |
45244b87 ED |
137 | * but the HDMI/DVI fields are shared among those. So we program the DDI |
138 | * in either FDI or DP modes only, as HDMI connections will work with both | |
139 | * of those | |
140 | */ | |
ad8d270c | 141 | static void intel_prepare_ddi_buffers(struct drm_device *dev, enum port port) |
45244b87 ED |
142 | { |
143 | struct drm_i915_private *dev_priv = dev->dev_private; | |
144 | u32 reg; | |
145 | int i; | |
6acab15a | 146 | int hdmi_level = dev_priv->vbt.ddi_port_info[port].hdmi_level_shift; |
e58623cb AR |
147 | const u32 *ddi_translations_fdi; |
148 | const u32 *ddi_translations_dp; | |
300644c7 | 149 | const u32 *ddi_translations_edp; |
e58623cb AR |
150 | const u32 *ddi_translations; |
151 | ||
152 | if (IS_BROADWELL(dev)) { | |
153 | ddi_translations_fdi = bdw_ddi_translations_fdi; | |
154 | ddi_translations_dp = bdw_ddi_translations_dp; | |
300644c7 | 155 | ddi_translations_edp = bdw_ddi_translations_edp; |
e58623cb AR |
156 | } else if (IS_HASWELL(dev)) { |
157 | ddi_translations_fdi = hsw_ddi_translations_fdi; | |
158 | ddi_translations_dp = hsw_ddi_translations_dp; | |
300644c7 | 159 | ddi_translations_edp = hsw_ddi_translations_dp; |
e58623cb AR |
160 | } else { |
161 | WARN(1, "ddi translation table missing\n"); | |
300644c7 | 162 | ddi_translations_edp = bdw_ddi_translations_dp; |
e58623cb AR |
163 | ddi_translations_fdi = bdw_ddi_translations_fdi; |
164 | ddi_translations_dp = bdw_ddi_translations_dp; | |
165 | } | |
166 | ||
300644c7 PZ |
167 | switch (port) { |
168 | case PORT_A: | |
169 | ddi_translations = ddi_translations_edp; | |
170 | break; | |
171 | case PORT_B: | |
172 | case PORT_C: | |
300644c7 PZ |
173 | ddi_translations = ddi_translations_dp; |
174 | break; | |
77d8d009 | 175 | case PORT_D: |
5d8a7752 | 176 | if (intel_dp_is_edp(dev, PORT_D)) |
77d8d009 PZ |
177 | ddi_translations = ddi_translations_edp; |
178 | else | |
179 | ddi_translations = ddi_translations_dp; | |
180 | break; | |
300644c7 PZ |
181 | case PORT_E: |
182 | ddi_translations = ddi_translations_fdi; | |
183 | break; | |
184 | default: | |
185 | BUG(); | |
186 | } | |
45244b87 | 187 | |
f72d19f0 PZ |
188 | for (i = 0, reg = DDI_BUF_TRANS(port); |
189 | i < ARRAY_SIZE(hsw_ddi_translations_fdi); i++) { | |
45244b87 ED |
190 | I915_WRITE(reg, ddi_translations[i]); |
191 | reg += 4; | |
192 | } | |
6acab15a PZ |
193 | /* Entry 9 is for HDMI: */ |
194 | for (i = 0; i < 2; i++) { | |
195 | I915_WRITE(reg, hsw_ddi_translations_hdmi[hdmi_level * 2 + i]); | |
196 | reg += 4; | |
197 | } | |
45244b87 ED |
198 | } |
199 | ||
200 | /* Program DDI buffers translations for DP. By default, program ports A-D in DP | |
201 | * mode and port E for FDI. | |
202 | */ | |
203 | void intel_prepare_ddi(struct drm_device *dev) | |
204 | { | |
205 | int port; | |
206 | ||
0d536cb4 PZ |
207 | if (!HAS_DDI(dev)) |
208 | return; | |
45244b87 | 209 | |
ad8d270c PZ |
210 | for (port = PORT_A; port <= PORT_E; port++) |
211 | intel_prepare_ddi_buffers(dev, port); | |
45244b87 | 212 | } |
c82e4d26 ED |
213 | |
214 | static const long hsw_ddi_buf_ctl_values[] = { | |
215 | DDI_BUF_EMP_400MV_0DB_HSW, | |
216 | DDI_BUF_EMP_400MV_3_5DB_HSW, | |
217 | DDI_BUF_EMP_400MV_6DB_HSW, | |
218 | DDI_BUF_EMP_400MV_9_5DB_HSW, | |
219 | DDI_BUF_EMP_600MV_0DB_HSW, | |
220 | DDI_BUF_EMP_600MV_3_5DB_HSW, | |
221 | DDI_BUF_EMP_600MV_6DB_HSW, | |
222 | DDI_BUF_EMP_800MV_0DB_HSW, | |
223 | DDI_BUF_EMP_800MV_3_5DB_HSW | |
224 | }; | |
225 | ||
248138b5 PZ |
226 | static void intel_wait_ddi_buf_idle(struct drm_i915_private *dev_priv, |
227 | enum port port) | |
228 | { | |
229 | uint32_t reg = DDI_BUF_CTL(port); | |
230 | int i; | |
231 | ||
232 | for (i = 0; i < 8; i++) { | |
233 | udelay(1); | |
234 | if (I915_READ(reg) & DDI_BUF_IS_IDLE) | |
235 | return; | |
236 | } | |
237 | DRM_ERROR("Timeout waiting for DDI BUF %c idle bit\n", port_name(port)); | |
238 | } | |
c82e4d26 ED |
239 | |
240 | /* Starting with Haswell, different DDI ports can work in FDI mode for | |
241 | * connection to the PCH-located connectors. For this, it is necessary to train | |
242 | * both the DDI port and PCH receiver for the desired DDI buffer settings. | |
243 | * | |
244 | * The recommended port to work in FDI mode is DDI E, which we use here. Also, | |
245 | * please note that when FDI mode is active on DDI E, it shares 2 lines with | |
246 | * DDI A (which is used for eDP) | |
247 | */ | |
248 | ||
249 | void hsw_fdi_link_train(struct drm_crtc *crtc) | |
250 | { | |
251 | struct drm_device *dev = crtc->dev; | |
252 | struct drm_i915_private *dev_priv = dev->dev_private; | |
253 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
04945641 | 254 | u32 temp, i, rx_ctl_val; |
c82e4d26 | 255 | |
04945641 PZ |
256 | /* Set the FDI_RX_MISC pwrdn lanes and the 2 workarounds listed at the |
257 | * mode set "sequence for CRT port" document: | |
258 | * - TP1 to TP2 time with the default value | |
259 | * - FDI delay to 90h | |
8693a824 DL |
260 | * |
261 | * WaFDIAutoLinkSetTimingOverrride:hsw | |
04945641 PZ |
262 | */ |
263 | I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) | | |
264 | FDI_RX_PWRDN_LANE0_VAL(2) | | |
265 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
266 | ||
267 | /* Enable the PCH Receiver FDI PLL */ | |
3e68320e | 268 | rx_ctl_val = dev_priv->fdi_rx_config | FDI_RX_ENHANCE_FRAME_ENABLE | |
33d29b14 | 269 | FDI_RX_PLL_ENABLE | |
627eb5a3 | 270 | FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); |
04945641 PZ |
271 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); |
272 | POSTING_READ(_FDI_RXA_CTL); | |
273 | udelay(220); | |
274 | ||
275 | /* Switch from Rawclk to PCDclk */ | |
276 | rx_ctl_val |= FDI_PCDCLK; | |
277 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
278 | ||
279 | /* Configure Port Clock Select */ | |
de7cfc63 DV |
280 | I915_WRITE(PORT_CLK_SEL(PORT_E), intel_crtc->config.ddi_pll_sel); |
281 | WARN_ON(intel_crtc->config.ddi_pll_sel != PORT_CLK_SEL_SPLL); | |
04945641 PZ |
282 | |
283 | /* Start the training iterating through available voltages and emphasis, | |
284 | * testing each value twice. */ | |
285 | for (i = 0; i < ARRAY_SIZE(hsw_ddi_buf_ctl_values) * 2; i++) { | |
c82e4d26 ED |
286 | /* Configure DP_TP_CTL with auto-training */ |
287 | I915_WRITE(DP_TP_CTL(PORT_E), | |
288 | DP_TP_CTL_FDI_AUTOTRAIN | | |
289 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
290 | DP_TP_CTL_LINK_TRAIN_PAT1 | | |
291 | DP_TP_CTL_ENABLE); | |
292 | ||
876a8cdf DL |
293 | /* Configure and enable DDI_BUF_CTL for DDI E with next voltage. |
294 | * DDI E does not support port reversal, the functionality is | |
295 | * achieved on the PCH side in FDI_RX_CTL, so no need to set the | |
296 | * port reversal bit */ | |
c82e4d26 | 297 | I915_WRITE(DDI_BUF_CTL(PORT_E), |
04945641 | 298 | DDI_BUF_CTL_ENABLE | |
33d29b14 | 299 | ((intel_crtc->config.fdi_lanes - 1) << 1) | |
04945641 PZ |
300 | hsw_ddi_buf_ctl_values[i / 2]); |
301 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
c82e4d26 ED |
302 | |
303 | udelay(600); | |
304 | ||
04945641 PZ |
305 | /* Program PCH FDI Receiver TU */ |
306 | I915_WRITE(_FDI_RXA_TUSIZE1, TU_SIZE(64)); | |
307 | ||
308 | /* Enable PCH FDI Receiver with auto-training */ | |
309 | rx_ctl_val |= FDI_RX_ENABLE | FDI_LINK_TRAIN_AUTO; | |
310 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
311 | POSTING_READ(_FDI_RXA_CTL); | |
312 | ||
313 | /* Wait for FDI receiver lane calibration */ | |
314 | udelay(30); | |
315 | ||
316 | /* Unset FDI_RX_MISC pwrdn lanes */ | |
317 | temp = I915_READ(_FDI_RXA_MISC); | |
318 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
319 | I915_WRITE(_FDI_RXA_MISC, temp); | |
320 | POSTING_READ(_FDI_RXA_MISC); | |
321 | ||
322 | /* Wait for FDI auto training time */ | |
323 | udelay(5); | |
c82e4d26 ED |
324 | |
325 | temp = I915_READ(DP_TP_STATUS(PORT_E)); | |
326 | if (temp & DP_TP_STATUS_AUTOTRAIN_DONE) { | |
04945641 | 327 | DRM_DEBUG_KMS("FDI link training done on step %d\n", i); |
c82e4d26 ED |
328 | |
329 | /* Enable normal pixel sending for FDI */ | |
330 | I915_WRITE(DP_TP_CTL(PORT_E), | |
04945641 PZ |
331 | DP_TP_CTL_FDI_AUTOTRAIN | |
332 | DP_TP_CTL_LINK_TRAIN_NORMAL | | |
333 | DP_TP_CTL_ENHANCED_FRAME_ENABLE | | |
334 | DP_TP_CTL_ENABLE); | |
c82e4d26 | 335 | |
04945641 | 336 | return; |
c82e4d26 | 337 | } |
04945641 | 338 | |
248138b5 PZ |
339 | temp = I915_READ(DDI_BUF_CTL(PORT_E)); |
340 | temp &= ~DDI_BUF_CTL_ENABLE; | |
341 | I915_WRITE(DDI_BUF_CTL(PORT_E), temp); | |
342 | POSTING_READ(DDI_BUF_CTL(PORT_E)); | |
343 | ||
04945641 | 344 | /* Disable DP_TP_CTL and FDI_RX_CTL and retry */ |
248138b5 PZ |
345 | temp = I915_READ(DP_TP_CTL(PORT_E)); |
346 | temp &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
347 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
348 | I915_WRITE(DP_TP_CTL(PORT_E), temp); | |
349 | POSTING_READ(DP_TP_CTL(PORT_E)); | |
350 | ||
351 | intel_wait_ddi_buf_idle(dev_priv, PORT_E); | |
04945641 PZ |
352 | |
353 | rx_ctl_val &= ~FDI_RX_ENABLE; | |
354 | I915_WRITE(_FDI_RXA_CTL, rx_ctl_val); | |
248138b5 | 355 | POSTING_READ(_FDI_RXA_CTL); |
04945641 PZ |
356 | |
357 | /* Reset FDI_RX_MISC pwrdn lanes */ | |
358 | temp = I915_READ(_FDI_RXA_MISC); | |
359 | temp &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
360 | temp |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
361 | I915_WRITE(_FDI_RXA_MISC, temp); | |
248138b5 | 362 | POSTING_READ(_FDI_RXA_MISC); |
c82e4d26 ED |
363 | } |
364 | ||
04945641 | 365 | DRM_ERROR("FDI link training failed!\n"); |
c82e4d26 | 366 | } |
0e72a5b5 | 367 | |
44905a27 DA |
368 | void intel_ddi_init_dp_buf_reg(struct intel_encoder *encoder) |
369 | { | |
370 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); | |
371 | struct intel_digital_port *intel_dig_port = | |
372 | enc_to_dig_port(&encoder->base); | |
373 | ||
374 | intel_dp->DP = intel_dig_port->saved_port_bits | | |
375 | DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_0DB_HSW; | |
376 | intel_dp->DP |= DDI_PORT_WIDTH(intel_dp->lane_count); | |
377 | ||
378 | } | |
379 | ||
8d9ddbcb PZ |
380 | static struct intel_encoder * |
381 | intel_ddi_get_crtc_encoder(struct drm_crtc *crtc) | |
382 | { | |
383 | struct drm_device *dev = crtc->dev; | |
384 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
385 | struct intel_encoder *intel_encoder, *ret = NULL; | |
386 | int num_encoders = 0; | |
387 | ||
388 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { | |
389 | ret = intel_encoder; | |
390 | num_encoders++; | |
391 | } | |
392 | ||
393 | if (num_encoders != 1) | |
84f44ce7 VS |
394 | WARN(1, "%d encoders on crtc for pipe %c\n", num_encoders, |
395 | pipe_name(intel_crtc->pipe)); | |
8d9ddbcb PZ |
396 | |
397 | BUG_ON(ret == NULL); | |
398 | return ret; | |
399 | } | |
400 | ||
1c0b85c5 DL |
401 | #define LC_FREQ 2700 |
402 | #define LC_FREQ_2K (LC_FREQ * 2000) | |
403 | ||
404 | #define P_MIN 2 | |
405 | #define P_MAX 64 | |
406 | #define P_INC 2 | |
407 | ||
408 | /* Constraints for PLL good behavior */ | |
409 | #define REF_MIN 48 | |
410 | #define REF_MAX 400 | |
411 | #define VCO_MIN 2400 | |
412 | #define VCO_MAX 4800 | |
413 | ||
414 | #define ABS_DIFF(a, b) ((a > b) ? (a - b) : (b - a)) | |
415 | ||
416 | struct wrpll_rnp { | |
417 | unsigned p, n2, r2; | |
418 | }; | |
419 | ||
420 | static unsigned wrpll_get_budget_for_freq(int clock) | |
6441ab5f | 421 | { |
1c0b85c5 DL |
422 | unsigned budget; |
423 | ||
424 | switch (clock) { | |
425 | case 25175000: | |
426 | case 25200000: | |
427 | case 27000000: | |
428 | case 27027000: | |
429 | case 37762500: | |
430 | case 37800000: | |
431 | case 40500000: | |
432 | case 40541000: | |
433 | case 54000000: | |
434 | case 54054000: | |
435 | case 59341000: | |
436 | case 59400000: | |
437 | case 72000000: | |
438 | case 74176000: | |
439 | case 74250000: | |
440 | case 81000000: | |
441 | case 81081000: | |
442 | case 89012000: | |
443 | case 89100000: | |
444 | case 108000000: | |
445 | case 108108000: | |
446 | case 111264000: | |
447 | case 111375000: | |
448 | case 148352000: | |
449 | case 148500000: | |
450 | case 162000000: | |
451 | case 162162000: | |
452 | case 222525000: | |
453 | case 222750000: | |
454 | case 296703000: | |
455 | case 297000000: | |
456 | budget = 0; | |
457 | break; | |
458 | case 233500000: | |
459 | case 245250000: | |
460 | case 247750000: | |
461 | case 253250000: | |
462 | case 298000000: | |
463 | budget = 1500; | |
464 | break; | |
465 | case 169128000: | |
466 | case 169500000: | |
467 | case 179500000: | |
468 | case 202000000: | |
469 | budget = 2000; | |
470 | break; | |
471 | case 256250000: | |
472 | case 262500000: | |
473 | case 270000000: | |
474 | case 272500000: | |
475 | case 273750000: | |
476 | case 280750000: | |
477 | case 281250000: | |
478 | case 286000000: | |
479 | case 291750000: | |
480 | budget = 4000; | |
481 | break; | |
482 | case 267250000: | |
483 | case 268500000: | |
484 | budget = 5000; | |
485 | break; | |
486 | default: | |
487 | budget = 1000; | |
488 | break; | |
489 | } | |
6441ab5f | 490 | |
1c0b85c5 DL |
491 | return budget; |
492 | } | |
493 | ||
494 | static void wrpll_update_rnp(uint64_t freq2k, unsigned budget, | |
495 | unsigned r2, unsigned n2, unsigned p, | |
496 | struct wrpll_rnp *best) | |
497 | { | |
498 | uint64_t a, b, c, d, diff, diff_best; | |
6441ab5f | 499 | |
1c0b85c5 DL |
500 | /* No best (r,n,p) yet */ |
501 | if (best->p == 0) { | |
502 | best->p = p; | |
503 | best->n2 = n2; | |
504 | best->r2 = r2; | |
505 | return; | |
506 | } | |
6441ab5f | 507 | |
1c0b85c5 DL |
508 | /* |
509 | * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to | |
510 | * freq2k. | |
511 | * | |
512 | * delta = 1e6 * | |
513 | * abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) / | |
514 | * freq2k; | |
515 | * | |
516 | * and we would like delta <= budget. | |
517 | * | |
518 | * If the discrepancy is above the PPM-based budget, always prefer to | |
519 | * improve upon the previous solution. However, if you're within the | |
520 | * budget, try to maximize Ref * VCO, that is N / (P * R^2). | |
521 | */ | |
522 | a = freq2k * budget * p * r2; | |
523 | b = freq2k * budget * best->p * best->r2; | |
524 | diff = ABS_DIFF((freq2k * p * r2), (LC_FREQ_2K * n2)); | |
525 | diff_best = ABS_DIFF((freq2k * best->p * best->r2), | |
526 | (LC_FREQ_2K * best->n2)); | |
527 | c = 1000000 * diff; | |
528 | d = 1000000 * diff_best; | |
529 | ||
530 | if (a < c && b < d) { | |
531 | /* If both are above the budget, pick the closer */ | |
532 | if (best->p * best->r2 * diff < p * r2 * diff_best) { | |
533 | best->p = p; | |
534 | best->n2 = n2; | |
535 | best->r2 = r2; | |
536 | } | |
537 | } else if (a >= c && b < d) { | |
538 | /* If A is below the threshold but B is above it? Update. */ | |
539 | best->p = p; | |
540 | best->n2 = n2; | |
541 | best->r2 = r2; | |
542 | } else if (a >= c && b >= d) { | |
543 | /* Both are below the limit, so pick the higher n2/(r2*r2) */ | |
544 | if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) { | |
545 | best->p = p; | |
546 | best->n2 = n2; | |
547 | best->r2 = r2; | |
548 | } | |
549 | } | |
550 | /* Otherwise a < c && b >= d, do nothing */ | |
551 | } | |
552 | ||
11578553 JB |
553 | static int intel_ddi_calc_wrpll_link(struct drm_i915_private *dev_priv, |
554 | int reg) | |
555 | { | |
556 | int refclk = LC_FREQ; | |
557 | int n, p, r; | |
558 | u32 wrpll; | |
559 | ||
560 | wrpll = I915_READ(reg); | |
114fe488 DV |
561 | switch (wrpll & WRPLL_PLL_REF_MASK) { |
562 | case WRPLL_PLL_SSC: | |
563 | case WRPLL_PLL_NON_SSC: | |
11578553 JB |
564 | /* |
565 | * We could calculate spread here, but our checking | |
566 | * code only cares about 5% accuracy, and spread is a max of | |
567 | * 0.5% downspread. | |
568 | */ | |
569 | refclk = 135; | |
570 | break; | |
114fe488 | 571 | case WRPLL_PLL_LCPLL: |
11578553 JB |
572 | refclk = LC_FREQ; |
573 | break; | |
574 | default: | |
575 | WARN(1, "bad wrpll refclk\n"); | |
576 | return 0; | |
577 | } | |
578 | ||
579 | r = wrpll & WRPLL_DIVIDER_REF_MASK; | |
580 | p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT; | |
581 | n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT; | |
582 | ||
20f0ec16 JB |
583 | /* Convert to KHz, p & r have a fixed point portion */ |
584 | return (refclk * n * 100) / (p * r); | |
11578553 JB |
585 | } |
586 | ||
587 | static void intel_ddi_clock_get(struct intel_encoder *encoder, | |
588 | struct intel_crtc_config *pipe_config) | |
589 | { | |
590 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
11578553 JB |
591 | int link_clock = 0; |
592 | u32 val, pll; | |
593 | ||
26804afd | 594 | val = pipe_config->ddi_pll_sel; |
11578553 JB |
595 | switch (val & PORT_CLK_SEL_MASK) { |
596 | case PORT_CLK_SEL_LCPLL_810: | |
597 | link_clock = 81000; | |
598 | break; | |
599 | case PORT_CLK_SEL_LCPLL_1350: | |
600 | link_clock = 135000; | |
601 | break; | |
602 | case PORT_CLK_SEL_LCPLL_2700: | |
603 | link_clock = 270000; | |
604 | break; | |
605 | case PORT_CLK_SEL_WRPLL1: | |
606 | link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL1); | |
607 | break; | |
608 | case PORT_CLK_SEL_WRPLL2: | |
609 | link_clock = intel_ddi_calc_wrpll_link(dev_priv, WRPLL_CTL2); | |
610 | break; | |
611 | case PORT_CLK_SEL_SPLL: | |
612 | pll = I915_READ(SPLL_CTL) & SPLL_PLL_FREQ_MASK; | |
613 | if (pll == SPLL_PLL_FREQ_810MHz) | |
614 | link_clock = 81000; | |
615 | else if (pll == SPLL_PLL_FREQ_1350MHz) | |
616 | link_clock = 135000; | |
617 | else if (pll == SPLL_PLL_FREQ_2700MHz) | |
618 | link_clock = 270000; | |
619 | else { | |
620 | WARN(1, "bad spll freq\n"); | |
621 | return; | |
622 | } | |
623 | break; | |
624 | default: | |
625 | WARN(1, "bad port clock sel\n"); | |
626 | return; | |
627 | } | |
628 | ||
629 | pipe_config->port_clock = link_clock * 2; | |
630 | ||
631 | if (pipe_config->has_pch_encoder) | |
632 | pipe_config->adjusted_mode.crtc_clock = | |
633 | intel_dotclock_calculate(pipe_config->port_clock, | |
634 | &pipe_config->fdi_m_n); | |
635 | else if (pipe_config->has_dp_encoder) | |
636 | pipe_config->adjusted_mode.crtc_clock = | |
637 | intel_dotclock_calculate(pipe_config->port_clock, | |
638 | &pipe_config->dp_m_n); | |
639 | else | |
640 | pipe_config->adjusted_mode.crtc_clock = pipe_config->port_clock; | |
641 | } | |
642 | ||
1c0b85c5 DL |
643 | static void |
644 | intel_ddi_calculate_wrpll(int clock /* in Hz */, | |
645 | unsigned *r2_out, unsigned *n2_out, unsigned *p_out) | |
646 | { | |
647 | uint64_t freq2k; | |
648 | unsigned p, n2, r2; | |
649 | struct wrpll_rnp best = { 0, 0, 0 }; | |
650 | unsigned budget; | |
651 | ||
652 | freq2k = clock / 100; | |
653 | ||
654 | budget = wrpll_get_budget_for_freq(clock); | |
655 | ||
656 | /* Special case handling for 540 pixel clock: bypass WR PLL entirely | |
657 | * and directly pass the LC PLL to it. */ | |
658 | if (freq2k == 5400000) { | |
659 | *n2_out = 2; | |
660 | *p_out = 1; | |
661 | *r2_out = 2; | |
662 | return; | |
663 | } | |
664 | ||
665 | /* | |
666 | * Ref = LC_FREQ / R, where Ref is the actual reference input seen by | |
667 | * the WR PLL. | |
668 | * | |
669 | * We want R so that REF_MIN <= Ref <= REF_MAX. | |
670 | * Injecting R2 = 2 * R gives: | |
671 | * REF_MAX * r2 > LC_FREQ * 2 and | |
672 | * REF_MIN * r2 < LC_FREQ * 2 | |
673 | * | |
674 | * Which means the desired boundaries for r2 are: | |
675 | * LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN | |
676 | * | |
677 | */ | |
678 | for (r2 = LC_FREQ * 2 / REF_MAX + 1; | |
679 | r2 <= LC_FREQ * 2 / REF_MIN; | |
680 | r2++) { | |
681 | ||
682 | /* | |
683 | * VCO = N * Ref, that is: VCO = N * LC_FREQ / R | |
684 | * | |
685 | * Once again we want VCO_MIN <= VCO <= VCO_MAX. | |
686 | * Injecting R2 = 2 * R and N2 = 2 * N, we get: | |
687 | * VCO_MAX * r2 > n2 * LC_FREQ and | |
688 | * VCO_MIN * r2 < n2 * LC_FREQ) | |
689 | * | |
690 | * Which means the desired boundaries for n2 are: | |
691 | * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ | |
692 | */ | |
693 | for (n2 = VCO_MIN * r2 / LC_FREQ + 1; | |
694 | n2 <= VCO_MAX * r2 / LC_FREQ; | |
695 | n2++) { | |
696 | ||
697 | for (p = P_MIN; p <= P_MAX; p += P_INC) | |
698 | wrpll_update_rnp(freq2k, budget, | |
699 | r2, n2, p, &best); | |
700 | } | |
701 | } | |
6441ab5f | 702 | |
1c0b85c5 DL |
703 | *n2_out = best.n2; |
704 | *p_out = best.p; | |
705 | *r2_out = best.r2; | |
6441ab5f PZ |
706 | } |
707 | ||
566b734a PZ |
708 | /* |
709 | * Tries to find a PLL for the CRTC. If it finds, it increases the refcount and | |
710 | * stores it in intel_crtc->ddi_pll_sel, so other mode sets won't be able to | |
711 | * steal the selected PLL. You need to call intel_ddi_pll_enable to actually | |
712 | * enable the PLL. | |
713 | */ | |
714 | bool intel_ddi_pll_select(struct intel_crtc *intel_crtc) | |
6441ab5f | 715 | { |
566b734a | 716 | struct drm_crtc *crtc = &intel_crtc->base; |
6441ab5f | 717 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); |
6441ab5f | 718 | int type = intel_encoder->type; |
ff9a6750 | 719 | int clock = intel_crtc->config.port_clock; |
6441ab5f | 720 | |
df8ad70c | 721 | intel_put_shared_dpll(intel_crtc); |
6441ab5f | 722 | |
0e50338c | 723 | if (type == INTEL_OUTPUT_HDMI) { |
e0b01be4 | 724 | struct intel_shared_dpll *pll; |
716c2e55 | 725 | uint32_t val; |
1c0b85c5 | 726 | unsigned p, n2, r2; |
6441ab5f | 727 | |
0694001b PZ |
728 | intel_ddi_calculate_wrpll(clock * 1000, &r2, &n2, &p); |
729 | ||
114fe488 | 730 | val = WRPLL_PLL_ENABLE | WRPLL_PLL_LCPLL | |
0694001b PZ |
731 | WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) | |
732 | WRPLL_DIVIDER_POST(p); | |
733 | ||
716c2e55 | 734 | intel_crtc->config.dpll_hw_state.wrpll = val; |
6441ab5f | 735 | |
716c2e55 DV |
736 | pll = intel_get_shared_dpll(intel_crtc); |
737 | if (pll == NULL) { | |
738 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", | |
739 | pipe_name(intel_crtc->pipe)); | |
740 | return false; | |
0694001b | 741 | } |
d452c5b6 | 742 | |
716c2e55 | 743 | intel_crtc->config.ddi_pll_sel = PORT_CLK_SEL_WRPLL(pll->id); |
6441ab5f PZ |
744 | } |
745 | ||
6441ab5f PZ |
746 | return true; |
747 | } | |
748 | ||
dae84799 PZ |
749 | void intel_ddi_set_pipe_settings(struct drm_crtc *crtc) |
750 | { | |
751 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
752 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
753 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
3b117c8f | 754 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
dae84799 PZ |
755 | int type = intel_encoder->type; |
756 | uint32_t temp; | |
757 | ||
758 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { | |
759 | ||
c9809791 | 760 | temp = TRANS_MSA_SYNC_CLK; |
965e0c48 | 761 | switch (intel_crtc->config.pipe_bpp) { |
dae84799 | 762 | case 18: |
c9809791 | 763 | temp |= TRANS_MSA_6_BPC; |
dae84799 PZ |
764 | break; |
765 | case 24: | |
c9809791 | 766 | temp |= TRANS_MSA_8_BPC; |
dae84799 PZ |
767 | break; |
768 | case 30: | |
c9809791 | 769 | temp |= TRANS_MSA_10_BPC; |
dae84799 PZ |
770 | break; |
771 | case 36: | |
c9809791 | 772 | temp |= TRANS_MSA_12_BPC; |
dae84799 PZ |
773 | break; |
774 | default: | |
4e53c2e0 | 775 | BUG(); |
dae84799 | 776 | } |
c9809791 | 777 | I915_WRITE(TRANS_MSA_MISC(cpu_transcoder), temp); |
dae84799 PZ |
778 | } |
779 | } | |
780 | ||
8228c251 | 781 | void intel_ddi_enable_transcoder_func(struct drm_crtc *crtc) |
8d9ddbcb PZ |
782 | { |
783 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
784 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
7739c33b | 785 | struct drm_encoder *encoder = &intel_encoder->base; |
c7670b10 PZ |
786 | struct drm_device *dev = crtc->dev; |
787 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8d9ddbcb | 788 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 789 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
174edf1f | 790 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
7739c33b | 791 | int type = intel_encoder->type; |
8d9ddbcb PZ |
792 | uint32_t temp; |
793 | ||
ad80a810 PZ |
794 | /* Enable TRANS_DDI_FUNC_CTL for the pipe to work in HDMI mode */ |
795 | temp = TRANS_DDI_FUNC_ENABLE; | |
174edf1f | 796 | temp |= TRANS_DDI_SELECT_PORT(port); |
dfcef252 | 797 | |
965e0c48 | 798 | switch (intel_crtc->config.pipe_bpp) { |
dfcef252 | 799 | case 18: |
ad80a810 | 800 | temp |= TRANS_DDI_BPC_6; |
dfcef252 PZ |
801 | break; |
802 | case 24: | |
ad80a810 | 803 | temp |= TRANS_DDI_BPC_8; |
dfcef252 PZ |
804 | break; |
805 | case 30: | |
ad80a810 | 806 | temp |= TRANS_DDI_BPC_10; |
dfcef252 PZ |
807 | break; |
808 | case 36: | |
ad80a810 | 809 | temp |= TRANS_DDI_BPC_12; |
dfcef252 PZ |
810 | break; |
811 | default: | |
4e53c2e0 | 812 | BUG(); |
dfcef252 | 813 | } |
72662e10 | 814 | |
a666283e | 815 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PVSYNC) |
ad80a810 | 816 | temp |= TRANS_DDI_PVSYNC; |
a666283e | 817 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_PHSYNC) |
ad80a810 | 818 | temp |= TRANS_DDI_PHSYNC; |
f63eb7c4 | 819 | |
e6f0bfc4 PZ |
820 | if (cpu_transcoder == TRANSCODER_EDP) { |
821 | switch (pipe) { | |
822 | case PIPE_A: | |
c7670b10 PZ |
823 | /* On Haswell, can only use the always-on power well for |
824 | * eDP when not using the panel fitter, and when not | |
825 | * using motion blur mitigation (which we don't | |
826 | * support). */ | |
fabf6e51 DV |
827 | if (IS_HASWELL(dev) && |
828 | (intel_crtc->config.pch_pfit.enabled || | |
829 | intel_crtc->config.pch_pfit.force_thru)) | |
d6dd9eb1 DV |
830 | temp |= TRANS_DDI_EDP_INPUT_A_ONOFF; |
831 | else | |
832 | temp |= TRANS_DDI_EDP_INPUT_A_ON; | |
e6f0bfc4 PZ |
833 | break; |
834 | case PIPE_B: | |
835 | temp |= TRANS_DDI_EDP_INPUT_B_ONOFF; | |
836 | break; | |
837 | case PIPE_C: | |
838 | temp |= TRANS_DDI_EDP_INPUT_C_ONOFF; | |
839 | break; | |
840 | default: | |
841 | BUG(); | |
842 | break; | |
843 | } | |
844 | } | |
845 | ||
7739c33b | 846 | if (type == INTEL_OUTPUT_HDMI) { |
6897b4b5 | 847 | if (intel_crtc->config.has_hdmi_sink) |
ad80a810 | 848 | temp |= TRANS_DDI_MODE_SELECT_HDMI; |
8d9ddbcb | 849 | else |
ad80a810 | 850 | temp |= TRANS_DDI_MODE_SELECT_DVI; |
8d9ddbcb | 851 | |
7739c33b | 852 | } else if (type == INTEL_OUTPUT_ANALOG) { |
ad80a810 | 853 | temp |= TRANS_DDI_MODE_SELECT_FDI; |
33d29b14 | 854 | temp |= (intel_crtc->config.fdi_lanes - 1) << 1; |
7739c33b PZ |
855 | |
856 | } else if (type == INTEL_OUTPUT_DISPLAYPORT || | |
857 | type == INTEL_OUTPUT_EDP) { | |
858 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
859 | ||
ad80a810 | 860 | temp |= TRANS_DDI_MODE_SELECT_DP_SST; |
7739c33b | 861 | |
17aa6be9 | 862 | temp |= DDI_PORT_WIDTH(intel_dp->lane_count); |
8d9ddbcb | 863 | } else { |
84f44ce7 VS |
864 | WARN(1, "Invalid encoder type %d for pipe %c\n", |
865 | intel_encoder->type, pipe_name(pipe)); | |
8d9ddbcb PZ |
866 | } |
867 | ||
ad80a810 | 868 | I915_WRITE(TRANS_DDI_FUNC_CTL(cpu_transcoder), temp); |
8d9ddbcb | 869 | } |
72662e10 | 870 | |
ad80a810 PZ |
871 | void intel_ddi_disable_transcoder_func(struct drm_i915_private *dev_priv, |
872 | enum transcoder cpu_transcoder) | |
8d9ddbcb | 873 | { |
ad80a810 | 874 | uint32_t reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
8d9ddbcb PZ |
875 | uint32_t val = I915_READ(reg); |
876 | ||
ad80a810 PZ |
877 | val &= ~(TRANS_DDI_FUNC_ENABLE | TRANS_DDI_PORT_MASK); |
878 | val |= TRANS_DDI_PORT_NONE; | |
8d9ddbcb | 879 | I915_WRITE(reg, val); |
72662e10 ED |
880 | } |
881 | ||
bcbc889b PZ |
882 | bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector) |
883 | { | |
884 | struct drm_device *dev = intel_connector->base.dev; | |
885 | struct drm_i915_private *dev_priv = dev->dev_private; | |
886 | struct intel_encoder *intel_encoder = intel_connector->encoder; | |
887 | int type = intel_connector->base.connector_type; | |
888 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
889 | enum pipe pipe = 0; | |
890 | enum transcoder cpu_transcoder; | |
882244a3 | 891 | enum intel_display_power_domain power_domain; |
bcbc889b PZ |
892 | uint32_t tmp; |
893 | ||
882244a3 PZ |
894 | power_domain = intel_display_port_power_domain(intel_encoder); |
895 | if (!intel_display_power_enabled(dev_priv, power_domain)) | |
896 | return false; | |
897 | ||
bcbc889b PZ |
898 | if (!intel_encoder->get_hw_state(intel_encoder, &pipe)) |
899 | return false; | |
900 | ||
901 | if (port == PORT_A) | |
902 | cpu_transcoder = TRANSCODER_EDP; | |
903 | else | |
1a240d4d | 904 | cpu_transcoder = (enum transcoder) pipe; |
bcbc889b PZ |
905 | |
906 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
907 | ||
908 | switch (tmp & TRANS_DDI_MODE_SELECT_MASK) { | |
909 | case TRANS_DDI_MODE_SELECT_HDMI: | |
910 | case TRANS_DDI_MODE_SELECT_DVI: | |
911 | return (type == DRM_MODE_CONNECTOR_HDMIA); | |
912 | ||
913 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
914 | if (type == DRM_MODE_CONNECTOR_eDP) | |
915 | return true; | |
916 | case TRANS_DDI_MODE_SELECT_DP_MST: | |
917 | return (type == DRM_MODE_CONNECTOR_DisplayPort); | |
918 | ||
919 | case TRANS_DDI_MODE_SELECT_FDI: | |
920 | return (type == DRM_MODE_CONNECTOR_VGA); | |
921 | ||
922 | default: | |
923 | return false; | |
924 | } | |
925 | } | |
926 | ||
85234cdc DV |
927 | bool intel_ddi_get_hw_state(struct intel_encoder *encoder, |
928 | enum pipe *pipe) | |
929 | { | |
930 | struct drm_device *dev = encoder->base.dev; | |
931 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fe43d3f5 | 932 | enum port port = intel_ddi_get_encoder_port(encoder); |
6d129bea | 933 | enum intel_display_power_domain power_domain; |
85234cdc DV |
934 | u32 tmp; |
935 | int i; | |
936 | ||
6d129bea ID |
937 | power_domain = intel_display_port_power_domain(encoder); |
938 | if (!intel_display_power_enabled(dev_priv, power_domain)) | |
939 | return false; | |
940 | ||
fe43d3f5 | 941 | tmp = I915_READ(DDI_BUF_CTL(port)); |
85234cdc DV |
942 | |
943 | if (!(tmp & DDI_BUF_CTL_ENABLE)) | |
944 | return false; | |
945 | ||
ad80a810 PZ |
946 | if (port == PORT_A) { |
947 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); | |
85234cdc | 948 | |
ad80a810 PZ |
949 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { |
950 | case TRANS_DDI_EDP_INPUT_A_ON: | |
951 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
952 | *pipe = PIPE_A; | |
953 | break; | |
954 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
955 | *pipe = PIPE_B; | |
956 | break; | |
957 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
958 | *pipe = PIPE_C; | |
959 | break; | |
960 | } | |
961 | ||
962 | return true; | |
963 | } else { | |
964 | for (i = TRANSCODER_A; i <= TRANSCODER_C; i++) { | |
965 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(i)); | |
966 | ||
967 | if ((tmp & TRANS_DDI_PORT_MASK) | |
968 | == TRANS_DDI_SELECT_PORT(port)) { | |
969 | *pipe = i; | |
970 | return true; | |
971 | } | |
85234cdc DV |
972 | } |
973 | } | |
974 | ||
84f44ce7 | 975 | DRM_DEBUG_KMS("No pipe for ddi port %c found\n", port_name(port)); |
85234cdc | 976 | |
22f9fe50 | 977 | return false; |
85234cdc DV |
978 | } |
979 | ||
fc914639 PZ |
980 | void intel_ddi_enable_pipe_clock(struct intel_crtc *intel_crtc) |
981 | { | |
982 | struct drm_crtc *crtc = &intel_crtc->base; | |
983 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
984 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
985 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
3b117c8f | 986 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
fc914639 | 987 | |
bb523fc0 PZ |
988 | if (cpu_transcoder != TRANSCODER_EDP) |
989 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
990 | TRANS_CLK_SEL_PORT(port)); | |
fc914639 PZ |
991 | } |
992 | ||
993 | void intel_ddi_disable_pipe_clock(struct intel_crtc *intel_crtc) | |
994 | { | |
995 | struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private; | |
3b117c8f | 996 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
fc914639 | 997 | |
bb523fc0 PZ |
998 | if (cpu_transcoder != TRANSCODER_EDP) |
999 | I915_WRITE(TRANS_CLK_SEL(cpu_transcoder), | |
1000 | TRANS_CLK_SEL_DISABLED); | |
fc914639 PZ |
1001 | } |
1002 | ||
00c09d70 | 1003 | static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder) |
6441ab5f | 1004 | { |
c19b0669 | 1005 | struct drm_encoder *encoder = &intel_encoder->base; |
c19b0669 | 1006 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
30cf6db8 | 1007 | struct intel_crtc *crtc = to_intel_crtc(encoder->crtc); |
6441ab5f | 1008 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
82a4d9c0 | 1009 | int type = intel_encoder->type; |
6441ab5f | 1010 | |
30cf6db8 DV |
1011 | if (crtc->config.has_audio) { |
1012 | DRM_DEBUG_DRIVER("Audio on pipe %c on DDI\n", | |
1013 | pipe_name(crtc->pipe)); | |
1014 | ||
1015 | /* write eld */ | |
1016 | DRM_DEBUG_DRIVER("DDI audio: write eld information\n"); | |
1017 | intel_write_eld(encoder, &crtc->config.adjusted_mode); | |
1018 | } | |
1019 | ||
82a4d9c0 PZ |
1020 | if (type == INTEL_OUTPUT_EDP) { |
1021 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
4be73780 | 1022 | intel_edp_panel_on(intel_dp); |
82a4d9c0 | 1023 | } |
6441ab5f | 1024 | |
de7cfc63 DV |
1025 | WARN_ON(crtc->config.ddi_pll_sel == PORT_CLK_SEL_NONE); |
1026 | I915_WRITE(PORT_CLK_SEL(port), crtc->config.ddi_pll_sel); | |
c19b0669 | 1027 | |
82a4d9c0 | 1028 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
c19b0669 | 1029 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
30cf6db8 | 1030 | |
44905a27 | 1031 | intel_ddi_init_dp_buf_reg(intel_encoder); |
c19b0669 PZ |
1032 | |
1033 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); | |
1034 | intel_dp_start_link_train(intel_dp); | |
1035 | intel_dp_complete_link_train(intel_dp); | |
3ab9c637 ID |
1036 | if (port != PORT_A) |
1037 | intel_dp_stop_link_train(intel_dp); | |
30cf6db8 DV |
1038 | } else if (type == INTEL_OUTPUT_HDMI) { |
1039 | struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder); | |
1040 | ||
1041 | intel_hdmi->set_infoframes(encoder, | |
1042 | crtc->config.has_hdmi_sink, | |
1043 | &crtc->config.adjusted_mode); | |
c19b0669 | 1044 | } |
6441ab5f PZ |
1045 | } |
1046 | ||
00c09d70 | 1047 | static void intel_ddi_post_disable(struct intel_encoder *intel_encoder) |
6441ab5f PZ |
1048 | { |
1049 | struct drm_encoder *encoder = &intel_encoder->base; | |
1050 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; | |
1051 | enum port port = intel_ddi_get_encoder_port(intel_encoder); | |
82a4d9c0 | 1052 | int type = intel_encoder->type; |
2886e93f | 1053 | uint32_t val; |
a836bdf9 | 1054 | bool wait = false; |
2886e93f PZ |
1055 | |
1056 | val = I915_READ(DDI_BUF_CTL(port)); | |
1057 | if (val & DDI_BUF_CTL_ENABLE) { | |
1058 | val &= ~DDI_BUF_CTL_ENABLE; | |
1059 | I915_WRITE(DDI_BUF_CTL(port), val); | |
a836bdf9 | 1060 | wait = true; |
2886e93f | 1061 | } |
6441ab5f | 1062 | |
a836bdf9 PZ |
1063 | val = I915_READ(DP_TP_CTL(port)); |
1064 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1065 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1066 | I915_WRITE(DP_TP_CTL(port), val); | |
1067 | ||
1068 | if (wait) | |
1069 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1070 | ||
76bb80ed | 1071 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) { |
82a4d9c0 | 1072 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
76bb80ed | 1073 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); |
24f3e092 | 1074 | intel_edp_panel_vdd_on(intel_dp); |
4be73780 | 1075 | intel_edp_panel_off(intel_dp); |
82a4d9c0 PZ |
1076 | } |
1077 | ||
6441ab5f PZ |
1078 | I915_WRITE(PORT_CLK_SEL(port), PORT_CLK_SEL_NONE); |
1079 | } | |
1080 | ||
00c09d70 | 1081 | static void intel_enable_ddi(struct intel_encoder *intel_encoder) |
72662e10 | 1082 | { |
6547fef8 | 1083 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1084 | struct drm_crtc *crtc = encoder->crtc; |
1085 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1086 | int pipe = intel_crtc->pipe; | |
6547fef8 | 1087 | struct drm_device *dev = encoder->dev; |
72662e10 | 1088 | struct drm_i915_private *dev_priv = dev->dev_private; |
6547fef8 PZ |
1089 | enum port port = intel_ddi_get_encoder_port(intel_encoder); |
1090 | int type = intel_encoder->type; | |
7b9f35a6 | 1091 | uint32_t tmp; |
72662e10 | 1092 | |
6547fef8 | 1093 | if (type == INTEL_OUTPUT_HDMI) { |
876a8cdf DL |
1094 | struct intel_digital_port *intel_dig_port = |
1095 | enc_to_dig_port(encoder); | |
1096 | ||
6547fef8 PZ |
1097 | /* In HDMI/DVI mode, the port width, and swing/emphasis values |
1098 | * are ignored so nothing special needs to be done besides | |
1099 | * enabling the port. | |
1100 | */ | |
876a8cdf | 1101 | I915_WRITE(DDI_BUF_CTL(port), |
bcf53de4 SM |
1102 | intel_dig_port->saved_port_bits | |
1103 | DDI_BUF_CTL_ENABLE); | |
d6c50ff8 PZ |
1104 | } else if (type == INTEL_OUTPUT_EDP) { |
1105 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1106 | ||
3ab9c637 ID |
1107 | if (port == PORT_A) |
1108 | intel_dp_stop_link_train(intel_dp); | |
1109 | ||
4be73780 | 1110 | intel_edp_backlight_on(intel_dp); |
4906557e | 1111 | intel_edp_psr_enable(intel_dp); |
6547fef8 | 1112 | } |
7b9f35a6 | 1113 | |
9ed109a7 | 1114 | if (intel_crtc->config.has_audio) { |
d45a0bf5 | 1115 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); |
7b9f35a6 WX |
1116 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); |
1117 | tmp |= ((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << (pipe * 4)); | |
1118 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); | |
1119 | } | |
5ab432ef DV |
1120 | } |
1121 | ||
00c09d70 | 1122 | static void intel_disable_ddi(struct intel_encoder *intel_encoder) |
5ab432ef | 1123 | { |
d6c50ff8 | 1124 | struct drm_encoder *encoder = &intel_encoder->base; |
7b9f35a6 WX |
1125 | struct drm_crtc *crtc = encoder->crtc; |
1126 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
1127 | int pipe = intel_crtc->pipe; | |
d6c50ff8 | 1128 | int type = intel_encoder->type; |
7b9f35a6 WX |
1129 | struct drm_device *dev = encoder->dev; |
1130 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1131 | uint32_t tmp; | |
d6c50ff8 | 1132 | |
d45a0bf5 PZ |
1133 | /* We can't touch HSW_AUD_PIN_ELD_CP_VLD uncionditionally because this |
1134 | * register is part of the power well on Haswell. */ | |
1135 | if (intel_crtc->config.has_audio) { | |
1136 | tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
1137 | tmp &= ~((AUDIO_OUTPUT_ENABLE_A | AUDIO_ELD_VALID_A) << | |
1138 | (pipe * 4)); | |
1139 | I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); | |
1140 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); | |
1141 | } | |
2831d842 | 1142 | |
d6c50ff8 PZ |
1143 | if (type == INTEL_OUTPUT_EDP) { |
1144 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); | |
1145 | ||
4906557e | 1146 | intel_edp_psr_disable(intel_dp); |
4be73780 | 1147 | intel_edp_backlight_off(intel_dp); |
d6c50ff8 | 1148 | } |
72662e10 | 1149 | } |
79f689aa | 1150 | |
b8fc2f6a | 1151 | int intel_ddi_get_cdclk_freq(struct drm_i915_private *dev_priv) |
79f689aa | 1152 | { |
e39bf98a | 1153 | struct drm_device *dev = dev_priv->dev; |
a4006641 | 1154 | uint32_t lcpll = I915_READ(LCPLL_CTL); |
e39bf98a | 1155 | uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK; |
a4006641 | 1156 | |
e39bf98a | 1157 | if (lcpll & LCPLL_CD_SOURCE_FCLK) { |
a4006641 | 1158 | return 800000; |
e3589908 | 1159 | } else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) { |
b2b877ff | 1160 | return 450000; |
e39bf98a | 1161 | } else if (freq == LCPLL_CLK_FREQ_450) { |
b2b877ff | 1162 | return 450000; |
e39bf98a PZ |
1163 | } else if (IS_HASWELL(dev)) { |
1164 | if (IS_ULT(dev)) | |
1165 | return 337500; | |
1166 | else | |
1167 | return 540000; | |
1168 | } else { | |
1169 | if (freq == LCPLL_CLK_FREQ_54O_BDW) | |
1170 | return 540000; | |
1171 | else if (freq == LCPLL_CLK_FREQ_337_5_BDW) | |
1172 | return 337500; | |
1173 | else | |
1174 | return 675000; | |
1175 | } | |
79f689aa PZ |
1176 | } |
1177 | ||
e0b01be4 DV |
1178 | static void hsw_ddi_pll_enable(struct drm_i915_private *dev_priv, |
1179 | struct intel_shared_dpll *pll) | |
1180 | { | |
e0b01be4 DV |
1181 | I915_WRITE(WRPLL_CTL(pll->id), pll->hw_state.wrpll); |
1182 | POSTING_READ(WRPLL_CTL(pll->id)); | |
1183 | udelay(20); | |
1184 | } | |
1185 | ||
12030431 DV |
1186 | static void hsw_ddi_pll_disable(struct drm_i915_private *dev_priv, |
1187 | struct intel_shared_dpll *pll) | |
1188 | { | |
1189 | uint32_t val; | |
1190 | ||
1191 | val = I915_READ(WRPLL_CTL(pll->id)); | |
12030431 DV |
1192 | I915_WRITE(WRPLL_CTL(pll->id), val & ~WRPLL_PLL_ENABLE); |
1193 | POSTING_READ(WRPLL_CTL(pll->id)); | |
1194 | } | |
1195 | ||
d452c5b6 DV |
1196 | static bool hsw_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv, |
1197 | struct intel_shared_dpll *pll, | |
1198 | struct intel_dpll_hw_state *hw_state) | |
1199 | { | |
1200 | uint32_t val; | |
1201 | ||
1202 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS)) | |
1203 | return false; | |
1204 | ||
1205 | val = I915_READ(WRPLL_CTL(pll->id)); | |
1206 | hw_state->wrpll = val; | |
1207 | ||
1208 | return val & WRPLL_PLL_ENABLE; | |
1209 | } | |
1210 | ||
9cd86933 DV |
1211 | static char *hsw_ddi_pll_names[] = { |
1212 | "WRPLL 1", | |
1213 | "WRPLL 2", | |
1214 | }; | |
1215 | ||
79f689aa PZ |
1216 | void intel_ddi_pll_init(struct drm_device *dev) |
1217 | { | |
1218 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1219 | uint32_t val = I915_READ(LCPLL_CTL); | |
9cd86933 DV |
1220 | int i; |
1221 | ||
716c2e55 | 1222 | dev_priv->num_shared_dpll = 2; |
9cd86933 | 1223 | |
716c2e55 | 1224 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
9cd86933 DV |
1225 | dev_priv->shared_dplls[i].id = i; |
1226 | dev_priv->shared_dplls[i].name = hsw_ddi_pll_names[i]; | |
12030431 | 1227 | dev_priv->shared_dplls[i].disable = hsw_ddi_pll_disable; |
e0b01be4 | 1228 | dev_priv->shared_dplls[i].enable = hsw_ddi_pll_enable; |
d452c5b6 DV |
1229 | dev_priv->shared_dplls[i].get_hw_state = |
1230 | hsw_ddi_pll_get_hw_state; | |
9cd86933 | 1231 | } |
79f689aa PZ |
1232 | |
1233 | /* The LCPLL register should be turned on by the BIOS. For now let's | |
1234 | * just check its state and print errors in case something is wrong. | |
1235 | * Don't even try to turn it on. | |
1236 | */ | |
1237 | ||
b2b877ff | 1238 | DRM_DEBUG_KMS("CDCLK running at %dKHz\n", |
79f689aa PZ |
1239 | intel_ddi_get_cdclk_freq(dev_priv)); |
1240 | ||
1241 | if (val & LCPLL_CD_SOURCE_FCLK) | |
1242 | DRM_ERROR("CDCLK source is not LCPLL\n"); | |
1243 | ||
1244 | if (val & LCPLL_PLL_DISABLE) | |
1245 | DRM_ERROR("LCPLL is disabled\n"); | |
1246 | } | |
c19b0669 PZ |
1247 | |
1248 | void intel_ddi_prepare_link_retrain(struct drm_encoder *encoder) | |
1249 | { | |
174edf1f PZ |
1250 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
1251 | struct intel_dp *intel_dp = &intel_dig_port->dp; | |
c19b0669 | 1252 | struct drm_i915_private *dev_priv = encoder->dev->dev_private; |
174edf1f | 1253 | enum port port = intel_dig_port->port; |
c19b0669 | 1254 | uint32_t val; |
f3e227df | 1255 | bool wait = false; |
c19b0669 PZ |
1256 | |
1257 | if (I915_READ(DP_TP_CTL(port)) & DP_TP_CTL_ENABLE) { | |
1258 | val = I915_READ(DDI_BUF_CTL(port)); | |
1259 | if (val & DDI_BUF_CTL_ENABLE) { | |
1260 | val &= ~DDI_BUF_CTL_ENABLE; | |
1261 | I915_WRITE(DDI_BUF_CTL(port), val); | |
1262 | wait = true; | |
1263 | } | |
1264 | ||
1265 | val = I915_READ(DP_TP_CTL(port)); | |
1266 | val &= ~(DP_TP_CTL_ENABLE | DP_TP_CTL_LINK_TRAIN_MASK); | |
1267 | val |= DP_TP_CTL_LINK_TRAIN_PAT1; | |
1268 | I915_WRITE(DP_TP_CTL(port), val); | |
1269 | POSTING_READ(DP_TP_CTL(port)); | |
1270 | ||
1271 | if (wait) | |
1272 | intel_wait_ddi_buf_idle(dev_priv, port); | |
1273 | } | |
1274 | ||
1275 | val = DP_TP_CTL_ENABLE | DP_TP_CTL_MODE_SST | | |
1276 | DP_TP_CTL_LINK_TRAIN_PAT1 | DP_TP_CTL_SCRAMBLE_DISABLE; | |
6aba5b6c | 1277 | if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) |
c19b0669 PZ |
1278 | val |= DP_TP_CTL_ENHANCED_FRAME_ENABLE; |
1279 | I915_WRITE(DP_TP_CTL(port), val); | |
1280 | POSTING_READ(DP_TP_CTL(port)); | |
1281 | ||
1282 | intel_dp->DP |= DDI_BUF_CTL_ENABLE; | |
1283 | I915_WRITE(DDI_BUF_CTL(port), intel_dp->DP); | |
1284 | POSTING_READ(DDI_BUF_CTL(port)); | |
1285 | ||
1286 | udelay(600); | |
1287 | } | |
00c09d70 | 1288 | |
1ad960f2 PZ |
1289 | void intel_ddi_fdi_disable(struct drm_crtc *crtc) |
1290 | { | |
1291 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
1292 | struct intel_encoder *intel_encoder = intel_ddi_get_crtc_encoder(crtc); | |
1293 | uint32_t val; | |
1294 | ||
1295 | intel_ddi_post_disable(intel_encoder); | |
1296 | ||
1297 | val = I915_READ(_FDI_RXA_CTL); | |
1298 | val &= ~FDI_RX_ENABLE; | |
1299 | I915_WRITE(_FDI_RXA_CTL, val); | |
1300 | ||
1301 | val = I915_READ(_FDI_RXA_MISC); | |
1302 | val &= ~(FDI_RX_PWRDN_LANE1_MASK | FDI_RX_PWRDN_LANE0_MASK); | |
1303 | val |= FDI_RX_PWRDN_LANE1_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2); | |
1304 | I915_WRITE(_FDI_RXA_MISC, val); | |
1305 | ||
1306 | val = I915_READ(_FDI_RXA_CTL); | |
1307 | val &= ~FDI_PCDCLK; | |
1308 | I915_WRITE(_FDI_RXA_CTL, val); | |
1309 | ||
1310 | val = I915_READ(_FDI_RXA_CTL); | |
1311 | val &= ~FDI_RX_PLL_ENABLE; | |
1312 | I915_WRITE(_FDI_RXA_CTL, val); | |
1313 | } | |
1314 | ||
00c09d70 PZ |
1315 | static void intel_ddi_hot_plug(struct intel_encoder *intel_encoder) |
1316 | { | |
1317 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); | |
1318 | int type = intel_encoder->type; | |
1319 | ||
1320 | if (type == INTEL_OUTPUT_DISPLAYPORT || type == INTEL_OUTPUT_EDP) | |
1321 | intel_dp_check_link_status(intel_dp); | |
1322 | } | |
1323 | ||
6801c18c VS |
1324 | void intel_ddi_get_config(struct intel_encoder *encoder, |
1325 | struct intel_crtc_config *pipe_config) | |
045ac3b5 JB |
1326 | { |
1327 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; | |
1328 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
1329 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; | |
1330 | u32 temp, flags = 0; | |
1331 | ||
1332 | temp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); | |
1333 | if (temp & TRANS_DDI_PHSYNC) | |
1334 | flags |= DRM_MODE_FLAG_PHSYNC; | |
1335 | else | |
1336 | flags |= DRM_MODE_FLAG_NHSYNC; | |
1337 | if (temp & TRANS_DDI_PVSYNC) | |
1338 | flags |= DRM_MODE_FLAG_PVSYNC; | |
1339 | else | |
1340 | flags |= DRM_MODE_FLAG_NVSYNC; | |
1341 | ||
1342 | pipe_config->adjusted_mode.flags |= flags; | |
42571aef VS |
1343 | |
1344 | switch (temp & TRANS_DDI_BPC_MASK) { | |
1345 | case TRANS_DDI_BPC_6: | |
1346 | pipe_config->pipe_bpp = 18; | |
1347 | break; | |
1348 | case TRANS_DDI_BPC_8: | |
1349 | pipe_config->pipe_bpp = 24; | |
1350 | break; | |
1351 | case TRANS_DDI_BPC_10: | |
1352 | pipe_config->pipe_bpp = 30; | |
1353 | break; | |
1354 | case TRANS_DDI_BPC_12: | |
1355 | pipe_config->pipe_bpp = 36; | |
1356 | break; | |
1357 | default: | |
1358 | break; | |
1359 | } | |
eb14cb74 VS |
1360 | |
1361 | switch (temp & TRANS_DDI_MODE_SELECT_MASK) { | |
1362 | case TRANS_DDI_MODE_SELECT_HDMI: | |
6897b4b5 | 1363 | pipe_config->has_hdmi_sink = true; |
eb14cb74 VS |
1364 | case TRANS_DDI_MODE_SELECT_DVI: |
1365 | case TRANS_DDI_MODE_SELECT_FDI: | |
1366 | break; | |
1367 | case TRANS_DDI_MODE_SELECT_DP_SST: | |
1368 | case TRANS_DDI_MODE_SELECT_DP_MST: | |
1369 | pipe_config->has_dp_encoder = true; | |
1370 | intel_dp_get_m_n(intel_crtc, pipe_config); | |
1371 | break; | |
1372 | default: | |
1373 | break; | |
1374 | } | |
10214420 | 1375 | |
a60551b1 PZ |
1376 | if (intel_display_power_enabled(dev_priv, POWER_DOMAIN_AUDIO)) { |
1377 | temp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); | |
1378 | if (temp & (AUDIO_OUTPUT_ENABLE_A << (intel_crtc->pipe * 4))) | |
1379 | pipe_config->has_audio = true; | |
1380 | } | |
9ed109a7 | 1381 | |
10214420 DV |
1382 | if (encoder->type == INTEL_OUTPUT_EDP && dev_priv->vbt.edp_bpp && |
1383 | pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) { | |
1384 | /* | |
1385 | * This is a big fat ugly hack. | |
1386 | * | |
1387 | * Some machines in UEFI boot mode provide us a VBT that has 18 | |
1388 | * bpp and 1.62 GHz link bandwidth for eDP, which for reasons | |
1389 | * unknown we fail to light up. Yet the same BIOS boots up with | |
1390 | * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as | |
1391 | * max, not what it tells us to use. | |
1392 | * | |
1393 | * Note: This will still be broken if the eDP panel is not lit | |
1394 | * up by the BIOS, and thus we can't get the mode at module | |
1395 | * load. | |
1396 | */ | |
1397 | DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", | |
1398 | pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp); | |
1399 | dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp; | |
1400 | } | |
11578553 JB |
1401 | |
1402 | intel_ddi_clock_get(encoder, pipe_config); | |
045ac3b5 JB |
1403 | } |
1404 | ||
00c09d70 PZ |
1405 | static void intel_ddi_destroy(struct drm_encoder *encoder) |
1406 | { | |
1407 | /* HDMI has nothing special to destroy, so we can go with this. */ | |
1408 | intel_dp_encoder_destroy(encoder); | |
1409 | } | |
1410 | ||
5bfe2ac0 DV |
1411 | static bool intel_ddi_compute_config(struct intel_encoder *encoder, |
1412 | struct intel_crtc_config *pipe_config) | |
00c09d70 | 1413 | { |
5bfe2ac0 | 1414 | int type = encoder->type; |
eccb140b | 1415 | int port = intel_ddi_get_encoder_port(encoder); |
00c09d70 | 1416 | |
5bfe2ac0 | 1417 | WARN(type == INTEL_OUTPUT_UNKNOWN, "compute_config() on unknown output!\n"); |
00c09d70 | 1418 | |
eccb140b DV |
1419 | if (port == PORT_A) |
1420 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
1421 | ||
00c09d70 | 1422 | if (type == INTEL_OUTPUT_HDMI) |
5bfe2ac0 | 1423 | return intel_hdmi_compute_config(encoder, pipe_config); |
00c09d70 | 1424 | else |
5bfe2ac0 | 1425 | return intel_dp_compute_config(encoder, pipe_config); |
00c09d70 PZ |
1426 | } |
1427 | ||
1428 | static const struct drm_encoder_funcs intel_ddi_funcs = { | |
1429 | .destroy = intel_ddi_destroy, | |
1430 | }; | |
1431 | ||
4a28ae58 PZ |
1432 | static struct intel_connector * |
1433 | intel_ddi_init_dp_connector(struct intel_digital_port *intel_dig_port) | |
1434 | { | |
1435 | struct intel_connector *connector; | |
1436 | enum port port = intel_dig_port->port; | |
1437 | ||
1438 | connector = kzalloc(sizeof(*connector), GFP_KERNEL); | |
1439 | if (!connector) | |
1440 | return NULL; | |
1441 | ||
1442 | intel_dig_port->dp.output_reg = DDI_BUF_CTL(port); | |
1443 | if (!intel_dp_init_connector(intel_dig_port, connector)) { | |
1444 | kfree(connector); | |
1445 | return NULL; | |
1446 | } | |
1447 | ||
1448 | return connector; | |
1449 | } | |
1450 | ||
1451 | static struct intel_connector * | |
1452 | intel_ddi_init_hdmi_connector(struct intel_digital_port *intel_dig_port) | |
1453 | { | |
1454 | struct intel_connector *connector; | |
1455 | enum port port = intel_dig_port->port; | |
1456 | ||
1457 | connector = kzalloc(sizeof(*connector), GFP_KERNEL); | |
1458 | if (!connector) | |
1459 | return NULL; | |
1460 | ||
1461 | intel_dig_port->hdmi.hdmi_reg = DDI_BUF_CTL(port); | |
1462 | intel_hdmi_init_connector(intel_dig_port, connector); | |
1463 | ||
1464 | return connector; | |
1465 | } | |
1466 | ||
00c09d70 PZ |
1467 | void intel_ddi_init(struct drm_device *dev, enum port port) |
1468 | { | |
876a8cdf | 1469 | struct drm_i915_private *dev_priv = dev->dev_private; |
00c09d70 PZ |
1470 | struct intel_digital_port *intel_dig_port; |
1471 | struct intel_encoder *intel_encoder; | |
1472 | struct drm_encoder *encoder; | |
1473 | struct intel_connector *hdmi_connector = NULL; | |
1474 | struct intel_connector *dp_connector = NULL; | |
311a2094 PZ |
1475 | bool init_hdmi, init_dp; |
1476 | ||
1477 | init_hdmi = (dev_priv->vbt.ddi_port_info[port].supports_dvi || | |
1478 | dev_priv->vbt.ddi_port_info[port].supports_hdmi); | |
1479 | init_dp = dev_priv->vbt.ddi_port_info[port].supports_dp; | |
1480 | if (!init_dp && !init_hdmi) { | |
1481 | DRM_DEBUG_KMS("VBT says port %c is not DVI/HDMI/DP compatible\n", | |
1482 | port_name(port)); | |
1483 | init_hdmi = true; | |
1484 | init_dp = true; | |
1485 | } | |
00c09d70 | 1486 | |
b14c5679 | 1487 | intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); |
00c09d70 PZ |
1488 | if (!intel_dig_port) |
1489 | return; | |
1490 | ||
00c09d70 PZ |
1491 | intel_encoder = &intel_dig_port->base; |
1492 | encoder = &intel_encoder->base; | |
1493 | ||
1494 | drm_encoder_init(dev, encoder, &intel_ddi_funcs, | |
1495 | DRM_MODE_ENCODER_TMDS); | |
00c09d70 | 1496 | |
5bfe2ac0 | 1497 | intel_encoder->compute_config = intel_ddi_compute_config; |
00c09d70 PZ |
1498 | intel_encoder->enable = intel_enable_ddi; |
1499 | intel_encoder->pre_enable = intel_ddi_pre_enable; | |
1500 | intel_encoder->disable = intel_disable_ddi; | |
1501 | intel_encoder->post_disable = intel_ddi_post_disable; | |
1502 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; | |
045ac3b5 | 1503 | intel_encoder->get_config = intel_ddi_get_config; |
00c09d70 PZ |
1504 | |
1505 | intel_dig_port->port = port; | |
bcf53de4 SM |
1506 | intel_dig_port->saved_port_bits = I915_READ(DDI_BUF_CTL(port)) & |
1507 | (DDI_BUF_PORT_REVERSAL | | |
1508 | DDI_A_4_LANES); | |
00c09d70 PZ |
1509 | |
1510 | intel_encoder->type = INTEL_OUTPUT_UNKNOWN; | |
1511 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
bc079e8b | 1512 | intel_encoder->cloneable = 0; |
00c09d70 PZ |
1513 | intel_encoder->hot_plug = intel_ddi_hot_plug; |
1514 | ||
13cf5504 DA |
1515 | intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; |
1516 | dev_priv->hpd_irq_port[port] = intel_dig_port; | |
1517 | ||
4a28ae58 PZ |
1518 | if (init_dp) |
1519 | dp_connector = intel_ddi_init_dp_connector(intel_dig_port); | |
21a8e6a4 | 1520 | |
311a2094 PZ |
1521 | /* In theory we don't need the encoder->type check, but leave it just in |
1522 | * case we have some really bad VBTs... */ | |
4a28ae58 PZ |
1523 | if (intel_encoder->type != INTEL_OUTPUT_EDP && init_hdmi) |
1524 | hdmi_connector = intel_ddi_init_hdmi_connector(intel_dig_port); | |
21a8e6a4 | 1525 | |
4a28ae58 PZ |
1526 | if (!dp_connector && !hdmi_connector) { |
1527 | drm_encoder_cleanup(encoder); | |
1528 | kfree(intel_dig_port); | |
21a8e6a4 | 1529 | } |
00c09d70 | 1530 | } |