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drm/i915: Convert resume to atomic.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR		 75};
76
3d7d6510
MR		 77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
568c634a 89static int intel_set_mode(struct drm_atomic_state *state);
eb1bfe80
JB		 90static int intel_framebuffer_init(struct drm_device *dev,
91 struct intel_framebuffer *ifb,
92 struct drm_mode_fb_cmd2 *mode_cmd,
93 struct drm_i915_gem_object *obj);
5b18e57c
DV		 94static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
95static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 96static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 97 struct intel_link_m_n *m_n,
98 struct intel_link_m_n *m2_n2);
29407aab 99static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 100static void haswell_set_pipeconf(struct drm_crtc *crtc);
101static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 102static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 103 const struct intel_crtc_state *pipe_config);
d288f65f 104static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 105 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 106static void intel_begin_crtc_commit(struct drm_crtc *crtc);
107static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 108static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
109 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 110static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
111 int num_connectors);
043e9bda 112static void intel_modeset_setup_hw_state(struct drm_device *dev);
e7457a9a 113
0e32b39c
DA		 114static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
115{
116 if (!connector->mst_port)
117 return connector->encoder;
118 else
119 return &connector->mst_port->mst_encoders[pipe]->base;
120}
121
79e53945 122typedef struct {
0206e353 123 int min, max;
79e53945
JB		 124} intel_range_t;
125
126typedef struct {
0206e353
AJ		 127 int dot_limit;
128 int p2_slow, p2_fast;
79e53945
JB		 129} intel_p2_t;
130
d4906093
ML		 131typedef struct intel_limit intel_limit_t;
132struct intel_limit {
0206e353
AJ		 133 intel_range_t dot, vco, n, m, m1, m2, p, p1;
134 intel_p2_t p2;
d4906093 135};
79e53945 136
d2acd215
DV		 137int
138intel_pch_rawclk(struct drm_device *dev)
139{
140 struct drm_i915_private *dev_priv = dev->dev_private;
141
142 WARN_ON(!HAS_PCH_SPLIT(dev));
143
144 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
145}
146
021357ac
CW		 147static inline u32 /* units of 100MHz */
148intel_fdi_link_freq(struct drm_device *dev)
149{
8b99e68c
CW		 150 if (IS_GEN5(dev)) {
151 struct drm_i915_private *dev_priv = dev->dev_private;
152 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
153 } else
154 return 27;
021357ac
CW		 155}
156
5d536e28 157static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 158 .dot = { .min = 25000, .max = 350000 },
9c333719 159 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 160 .n = { .min = 2, .max = 16 },
0206e353
AJ		 161 .m = { .min = 96, .max = 140 },
162 .m1 = { .min = 18, .max = 26 },
163 .m2 = { .min = 6, .max = 16 },
164 .p = { .min = 4, .max = 128 },
165 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 166 .p2 = { .dot_limit = 165000,
167 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 168};
169
5d536e28
DV		 170static const intel_limit_t intel_limits_i8xx_dvo = {
171 .dot = { .min = 25000, .max = 350000 },
9c333719 172 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 173 .n = { .min = 2, .max = 16 },
5d536e28
DV		 174 .m = { .min = 96, .max = 140 },
175 .m1 = { .min = 18, .max = 26 },
176 .m2 = { .min = 6, .max = 16 },
177 .p = { .min = 4, .max = 128 },
178 .p1 = { .min = 2, .max = 33 },
179 .p2 = { .dot_limit = 165000,
180 .p2_slow = 4, .p2_fast = 4 },
181};
182
e4b36699 183static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 184 .dot = { .min = 25000, .max = 350000 },
9c333719 185 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 186 .n = { .min = 2, .max = 16 },
0206e353
AJ		 187 .m = { .min = 96, .max = 140 },
188 .m1 = { .min = 18, .max = 26 },
189 .m2 = { .min = 6, .max = 16 },
190 .p = { .min = 4, .max = 128 },
191 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 192 .p2 = { .dot_limit = 165000,
193 .p2_slow = 14, .p2_fast = 7 },
e4b36699 194};
273e27ca 195
e4b36699 196static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 197 .dot = { .min = 20000, .max = 400000 },
198 .vco = { .min = 1400000, .max = 2800000 },
199 .n = { .min = 1, .max = 6 },
200 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 201 .m1 = { .min = 8, .max = 18 },
202 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 203 .p = { .min = 5, .max = 80 },
204 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 205 .p2 = { .dot_limit = 200000,
206 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 207};
208
209static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 210 .dot = { .min = 20000, .max = 400000 },
211 .vco = { .min = 1400000, .max = 2800000 },
212 .n = { .min = 1, .max = 6 },
213 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 214 .m1 = { .min = 8, .max = 18 },
215 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 216 .p = { .min = 7, .max = 98 },
217 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 218 .p2 = { .dot_limit = 112000,
219 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 220};
221
273e27ca 222
e4b36699 223static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 224 .dot = { .min = 25000, .max = 270000 },
225 .vco = { .min = 1750000, .max = 3500000},
226 .n = { .min = 1, .max = 4 },
227 .m = { .min = 104, .max = 138 },
228 .m1 = { .min = 17, .max = 23 },
229 .m2 = { .min = 5, .max = 11 },
230 .p = { .min = 10, .max = 30 },
231 .p1 = { .min = 1, .max = 3},
232 .p2 = { .dot_limit = 270000,
233 .p2_slow = 10,
234 .p2_fast = 10
044c7c41 235 },
e4b36699
KP		 236};
237
238static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 239 .dot = { .min = 22000, .max = 400000 },
240 .vco = { .min = 1750000, .max = 3500000},
241 .n = { .min = 1, .max = 4 },
242 .m = { .min = 104, .max = 138 },
243 .m1 = { .min = 16, .max = 23 },
244 .m2 = { .min = 5, .max = 11 },
245 .p = { .min = 5, .max = 80 },
246 .p1 = { .min = 1, .max = 8},
247 .p2 = { .dot_limit = 165000,
248 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 249};
250
251static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 252 .dot = { .min = 20000, .max = 115000 },
253 .vco = { .min = 1750000, .max = 3500000 },
254 .n = { .min = 1, .max = 3 },
255 .m = { .min = 104, .max = 138 },
256 .m1 = { .min = 17, .max = 23 },
257 .m2 = { .min = 5, .max = 11 },
258 .p = { .min = 28, .max = 112 },
259 .p1 = { .min = 2, .max = 8 },
260 .p2 = { .dot_limit = 0,
261 .p2_slow = 14, .p2_fast = 14
044c7c41 262 },
e4b36699
KP		 263};
264
265static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 266 .dot = { .min = 80000, .max = 224000 },
267 .vco = { .min = 1750000, .max = 3500000 },
268 .n = { .min = 1, .max = 3 },
269 .m = { .min = 104, .max = 138 },
270 .m1 = { .min = 17, .max = 23 },
271 .m2 = { .min = 5, .max = 11 },
272 .p = { .min = 14, .max = 42 },
273 .p1 = { .min = 2, .max = 6 },
274 .p2 = { .dot_limit = 0,
275 .p2_slow = 7, .p2_fast = 7
044c7c41 276 },
e4b36699
KP		 277};
278
f2b115e6 279static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 280 .dot = { .min = 20000, .max = 400000},
281 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 282 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 283 .n = { .min = 3, .max = 6 },
284 .m = { .min = 2, .max = 256 },
273e27ca 285 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 286 .m1 = { .min = 0, .max = 0 },
287 .m2 = { .min = 0, .max = 254 },
288 .p = { .min = 5, .max = 80 },
289 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 290 .p2 = { .dot_limit = 200000,
291 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 292};
293
f2b115e6 294static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 295 .dot = { .min = 20000, .max = 400000 },
296 .vco = { .min = 1700000, .max = 3500000 },
297 .n = { .min = 3, .max = 6 },
298 .m = { .min = 2, .max = 256 },
299 .m1 = { .min = 0, .max = 0 },
300 .m2 = { .min = 0, .max = 254 },
301 .p = { .min = 7, .max = 112 },
302 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 303 .p2 = { .dot_limit = 112000,
304 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 305};
306
273e27ca
EA		 307/* Ironlake / Sandybridge
308 *
309 * We calculate clock using (register_value + 2) for N/M1/M2, so here
310 * the range value for them is (actual_value - 2).
311 */
b91ad0ec 312static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 313 .dot = { .min = 25000, .max = 350000 },
314 .vco = { .min = 1760000, .max = 3510000 },
315 .n = { .min = 1, .max = 5 },
316 .m = { .min = 79, .max = 127 },
317 .m1 = { .min = 12, .max = 22 },
318 .m2 = { .min = 5, .max = 9 },
319 .p = { .min = 5, .max = 80 },
320 .p1 = { .min = 1, .max = 8 },
321 .p2 = { .dot_limit = 225000,
322 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 323};
324
b91ad0ec 325static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 3 },
329 .m = { .min = 79, .max = 118 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
333 .p1 = { .min = 2, .max = 8 },
334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 336};
337
338static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 339 .dot = { .min = 25000, .max = 350000 },
340 .vco = { .min = 1760000, .max = 3510000 },
341 .n = { .min = 1, .max = 3 },
342 .m = { .min = 79, .max = 127 },
343 .m1 = { .min = 12, .max = 22 },
344 .m2 = { .min = 5, .max = 9 },
345 .p = { .min = 14, .max = 56 },
346 .p1 = { .min = 2, .max = 8 },
347 .p2 = { .dot_limit = 225000,
348 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 349};
350
273e27ca 351/* LVDS 100mhz refclk limits. */
b91ad0ec 352static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 353 .dot = { .min = 25000, .max = 350000 },
354 .vco = { .min = 1760000, .max = 3510000 },
355 .n = { .min = 1, .max = 2 },
356 .m = { .min = 79, .max = 126 },
357 .m1 = { .min = 12, .max = 22 },
358 .m2 = { .min = 5, .max = 9 },
359 .p = { .min = 28, .max = 112 },
0206e353 360 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 361 .p2 = { .dot_limit = 225000,
362 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 363};
364
365static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 366 .dot = { .min = 25000, .max = 350000 },
367 .vco = { .min = 1760000, .max = 3510000 },
368 .n = { .min = 1, .max = 3 },
369 .m = { .min = 79, .max = 126 },
370 .m1 = { .min = 12, .max = 22 },
371 .m2 = { .min = 5, .max = 9 },
372 .p = { .min = 14, .max = 42 },
0206e353 373 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 374 .p2 = { .dot_limit = 225000,
375 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 376};
377
dc730512 378static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 379 /*
380 * These are the data rate limits (measured in fast clocks)
381 * since those are the strictest limits we have. The fast
382 * clock and actual rate limits are more relaxed, so checking
383 * them would make no difference.
384 */
385 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 386 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 387 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 388 .m1 = { .min = 2, .max = 3 },
389 .m2 = { .min = 11, .max = 156 },
b99ab663 390 .p1 = { .min = 2, .max = 3 },
5fdc9c49 391 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 392};
393
ef9348c8
CML		 394static const intel_limit_t intel_limits_chv = {
395 /*
396 * These are the data rate limits (measured in fast clocks)
397 * since those are the strictest limits we have. The fast
398 * clock and actual rate limits are more relaxed, so checking
399 * them would make no difference.
400 */
401 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 402 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 403 .n = { .min = 1, .max = 1 },
404 .m1 = { .min = 2, .max = 2 },
405 .m2 = { .min = 24 << 22, .max = 175 << 22 },
406 .p1 = { .min = 2, .max = 4 },
407 .p2 = { .p2_slow = 1, .p2_fast = 14 },
408};
409
5ab7b0b7
ID		 410static const intel_limit_t intel_limits_bxt = {
411 /* FIXME: find real dot limits */
412 .dot = { .min = 0, .max = INT_MAX },
e6292556 413 .vco = { .min = 4800000, .max = 6700000 },
5ab7b0b7
ID		 414 .n = { .min = 1, .max = 1 },
415 .m1 = { .min = 2, .max = 2 },
416 /* FIXME: find real m2 limits */
417 .m2 = { .min = 2 << 22, .max = 255 << 22 },
418 .p1 = { .min = 2, .max = 4 },
419 .p2 = { .p2_slow = 1, .p2_fast = 20 },
420};
421
cdba954e
ACO		 422static bool
423needs_modeset(struct drm_crtc_state *state)
424{
425 return state->mode_changed || state->active_changed;
426}
427
e0638cdf
PZ		 428/**
429 * Returns whether any output on the specified pipe is of the specified type
430 */
4093561b 431bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 432{
409ee761 433 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 434 struct intel_encoder *encoder;
435
409ee761 436 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 437 if (encoder->type == type)
438 return true;
439
440 return false;
441}
442
d0737e1d
ACO		 443/**
444 * Returns whether any output on the specified pipe will have the specified
445 * type after a staged modeset is complete, i.e., the same as
446 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
447 * encoder->crtc.
448 */
a93e255f
ACO		 449static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
450 int type)
d0737e1d 451{
a93e255f 452 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 453 struct drm_connector *connector;
a93e255f 454 struct drm_connector_state *connector_state;
d0737e1d 455 struct intel_encoder *encoder;
a93e255f
ACO		 456 int i, num_connectors = 0;
457
da3ced29 458 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 459 if (connector_state->crtc != crtc_state->base.crtc)
460 continue;
461
462 num_connectors++;
d0737e1d 463
a93e255f
ACO		 464 encoder = to_intel_encoder(connector_state->best_encoder);
465 if (encoder->type == type)
d0737e1d 466 return true;
a93e255f
ACO		 467 }
468
469 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 470
471 return false;
472}
473
a93e255f
ACO		 474static const intel_limit_t *
475intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 476{
a93e255f 477 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 478 const intel_limit_t *limit;
b91ad0ec 479
a93e255f 480 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 481 if (intel_is_dual_link_lvds(dev)) {
1b894b59 482 if (refclk == 100000)
b91ad0ec
ZW		 483 limit = &intel_limits_ironlake_dual_lvds_100m;
484 else
485 limit = &intel_limits_ironlake_dual_lvds;
486 } else {
1b894b59 487 if (refclk == 100000)
b91ad0ec
ZW		 488 limit = &intel_limits_ironlake_single_lvds_100m;
489 else
490 limit = &intel_limits_ironlake_single_lvds;
491 }
c6bb3538 492 } else
b91ad0ec 493 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 494
495 return limit;
496}
497
a93e255f
ACO		 498static const intel_limit_t *
499intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 500{
a93e255f 501 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 502 const intel_limit_t *limit;
503
a93e255f 504 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 505 if (intel_is_dual_link_lvds(dev))
e4b36699 506 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 507 else
e4b36699 508 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 509 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
510 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 511 limit = &intel_limits_g4x_hdmi;
a93e255f 512 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 513 limit = &intel_limits_g4x_sdvo;
044c7c41 514 } else /* The option is for other outputs */
e4b36699 515 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 516
517 return limit;
518}
519
a93e255f
ACO		 520static const intel_limit_t *
521intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 522{
a93e255f 523 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 524 const intel_limit_t *limit;
525
5ab7b0b7
ID		 526 if (IS_BROXTON(dev))
527 limit = &intel_limits_bxt;
528 else if (HAS_PCH_SPLIT(dev))
a93e255f 529 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 530 else if (IS_G4X(dev)) {
a93e255f 531 limit = intel_g4x_limit(crtc_state);
f2b115e6 532 } else if (IS_PINEVIEW(dev)) {
a93e255f 533 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 534 limit = &intel_limits_pineview_lvds;
2177832f 535 else
f2b115e6 536 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 537 } else if (IS_CHERRYVIEW(dev)) {
538 limit = &intel_limits_chv;
a0c4da24 539 } else if (IS_VALLEYVIEW(dev)) {
dc730512 540 limit = &intel_limits_vlv;
a6c45cf0 541 } else if (!IS_GEN2(dev)) {
a93e255f 542 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 543 limit = &intel_limits_i9xx_lvds;
544 else
545 limit = &intel_limits_i9xx_sdvo;
79e53945 546 } else {
a93e255f 547 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 548 limit = &intel_limits_i8xx_lvds;
a93e255f 549 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 550 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 551 else
552 limit = &intel_limits_i8xx_dac;
79e53945
JB		 553 }
554 return limit;
555}
556
dccbea3b
ID		 557/*
558 * Platform specific helpers to calculate the port PLL loopback- (clock.m),
559 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast
560 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic.
561 * The helpers' return value is the rate of the clock that is fed to the
562 * display engine's pipe which can be the above fast dot clock rate or a
563 * divided-down version of it.
564 */
f2b115e6 565/* m1 is reserved as 0 in Pineview, n is a ring counter */
dccbea3b 566static int pnv_calc_dpll_params(int refclk, intel_clock_t *clock)
79e53945 567{
2177832f
SL		 568 clock->m = clock->m2 + 2;
569 clock->p = clock->p1 * clock->p2;
ed5ca77e 570 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 571 return 0;
fb03ac01
VS		 572 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
573 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 574
575 return clock->dot;
2177832f
SL		 576}
577
7429e9d4
DV		 578static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
579{
580 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
581}
582
dccbea3b 583static int i9xx_calc_dpll_params(int refclk, intel_clock_t *clock)
2177832f 584{
7429e9d4 585 clock->m = i9xx_dpll_compute_m(clock);
79e53945 586 clock->p = clock->p1 * clock->p2;
ed5ca77e 587 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
dccbea3b 588 return 0;
fb03ac01
VS		 589 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
590 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 591
592 return clock->dot;
79e53945
JB		 593}
594
dccbea3b 595static int vlv_calc_dpll_params(int refclk, intel_clock_t *clock)
589eca67
ID		 596{
597 clock->m = clock->m1 * clock->m2;
598 clock->p = clock->p1 * clock->p2;
599 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 600 return 0;
589eca67
ID		 601 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
602 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 603
604 return clock->dot / 5;
589eca67
ID		 605}
606
dccbea3b 607int chv_calc_dpll_params(int refclk, intel_clock_t *clock)
ef9348c8
CML		 608{
609 clock->m = clock->m1 * clock->m2;
610 clock->p = clock->p1 * clock->p2;
611 if (WARN_ON(clock->n == 0 || clock->p == 0))
dccbea3b 612 return 0;
ef9348c8
CML		 613 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
614 clock->n << 22);
615 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
dccbea3b
ID		 616
617 return clock->dot / 5;
ef9348c8
CML		 618}
619
7c04d1d9 620#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 621/**
622 * Returns whether the given set of divisors are valid for a given refclk with
623 * the given connectors.
624 */
625
1b894b59
CW		 626static bool intel_PLL_is_valid(struct drm_device *dev,
627 const intel_limit_t *limit,
628 const intel_clock_t *clock)
79e53945 629{
f01b7962
VS		 630 if (clock->n < limit->n.min || limit->n.max < clock->n)
631 INTELPllInvalid("n out of range\n");
79e53945 632 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 633 INTELPllInvalid("p1 out of range\n");
79e53945 634 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 635 INTELPllInvalid("m2 out of range\n");
79e53945 636 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 637 INTELPllInvalid("m1 out of range\n");
f01b7962 638
5ab7b0b7 639 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 640 if (clock->m1 <= clock->m2)
641 INTELPllInvalid("m1 <= m2\n");
642
5ab7b0b7 643 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 644 if (clock->p < limit->p.min || limit->p.max < clock->p)
645 INTELPllInvalid("p out of range\n");
646 if (clock->m < limit->m.min || limit->m.max < clock->m)
647 INTELPllInvalid("m out of range\n");
648 }
649
79e53945 650 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 651 INTELPllInvalid("vco out of range\n");
79e53945
JB		 652 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
653 * connector, etc., rather than just a single range.
654 */
655 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 656 INTELPllInvalid("dot out of range\n");
79e53945
JB		 657
658 return true;
659}
660
3b1429d9
VS		 661static int
662i9xx_select_p2_div(const intel_limit_t *limit,
663 const struct intel_crtc_state *crtc_state,
664 int target)
79e53945 665{
3b1429d9 666 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 667
a93e255f 668 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 669 /*
a210b028
DV		 670 * For LVDS just rely on its current settings for dual-channel.
671 * We haven't figured out how to reliably set up different
672 * single/dual channel state, if we even can.
79e53945 673 */
1974cad0 674 if (intel_is_dual_link_lvds(dev))
3b1429d9 675 return limit->p2.p2_fast;
79e53945 676 else
3b1429d9 677 return limit->p2.p2_slow;
79e53945
JB		 678 } else {
679 if (target < limit->p2.dot_limit)
3b1429d9 680 return limit->p2.p2_slow;
79e53945 681 else
3b1429d9 682 return limit->p2.p2_fast;
79e53945 683 }
3b1429d9
VS		 684}
685
686static bool
687i9xx_find_best_dpll(const intel_limit_t *limit,
688 struct intel_crtc_state *crtc_state,
689 int target, int refclk, intel_clock_t *match_clock,
690 intel_clock_t *best_clock)
691{
692 struct drm_device *dev = crtc_state->base.crtc->dev;
693 intel_clock_t clock;
694 int err = target;
79e53945 695
0206e353 696 memset(best_clock, 0, sizeof(*best_clock));
79e53945 697
3b1429d9
VS		 698 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
699
42158660
ZY		 700 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
701 clock.m1++) {
702 for (clock.m2 = limit->m2.min;
703 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 704 if (clock.m2 >= clock.m1)
42158660
ZY		 705 break;
706 for (clock.n = limit->n.min;
707 clock.n <= limit->n.max; clock.n++) {
708 for (clock.p1 = limit->p1.min;
709 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 710 int this_err;
711
dccbea3b 712 i9xx_calc_dpll_params(refclk, &clock);
ac58c3f0
DV		 713 if (!intel_PLL_is_valid(dev, limit,
714 &clock))
715 continue;
716 if (match_clock &&
717 clock.p != match_clock->p)
718 continue;
719
720 this_err = abs(clock.dot - target);
721 if (this_err < err) {
722 *best_clock = clock;
723 err = this_err;
724 }
725 }
726 }
727 }
728 }
729
730 return (err != target);
731}
732
733static bool
a93e255f
ACO		 734pnv_find_best_dpll(const intel_limit_t *limit,
735 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 736 int target, int refclk, intel_clock_t *match_clock,
737 intel_clock_t *best_clock)
79e53945 738{
3b1429d9 739 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945 740 intel_clock_t clock;
79e53945
JB		 741 int err = target;
742
0206e353 743 memset(best_clock, 0, sizeof(*best_clock));
79e53945 744
3b1429d9
VS		 745 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
746
42158660
ZY		 747 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
748 clock.m1++) {
749 for (clock.m2 = limit->m2.min;
750 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 751 for (clock.n = limit->n.min;
752 clock.n <= limit->n.max; clock.n++) {
753 for (clock.p1 = limit->p1.min;
754 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 755 int this_err;
756
dccbea3b 757 pnv_calc_dpll_params(refclk, &clock);
1b894b59
CW		 758 if (!intel_PLL_is_valid(dev, limit,
759 &clock))
79e53945 760 continue;
cec2f356
SP		 761 if (match_clock &&
762 clock.p != match_clock->p)
763 continue;
79e53945
JB		 764
765 this_err = abs(clock.dot - target);
766 if (this_err < err) {
767 *best_clock = clock;
768 err = this_err;
769 }
770 }
771 }
772 }
773 }
774
775 return (err != target);
776}
777
d4906093 778static bool
a93e255f
ACO		 779g4x_find_best_dpll(const intel_limit_t *limit,
780 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 781 int target, int refclk, intel_clock_t *match_clock,
782 intel_clock_t *best_clock)
d4906093 783{
3b1429d9 784 struct drm_device *dev = crtc_state->base.crtc->dev;
d4906093
ML		 785 intel_clock_t clock;
786 int max_n;
3b1429d9 787 bool found = false;
6ba770dc
AJ		 788 /* approximately equals target * 0.00585 */
789 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 790
791 memset(best_clock, 0, sizeof(*best_clock));
3b1429d9
VS		 792
793 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target);
794
d4906093 795 max_n = limit->n.max;
f77f13e2 796 /* based on hardware requirement, prefer smaller n to precision */
d4906093 797 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 798 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 799 for (clock.m1 = limit->m1.max;
800 clock.m1 >= limit->m1.min; clock.m1--) {
801 for (clock.m2 = limit->m2.max;
802 clock.m2 >= limit->m2.min; clock.m2--) {
803 for (clock.p1 = limit->p1.max;
804 clock.p1 >= limit->p1.min; clock.p1--) {
805 int this_err;
806
dccbea3b 807 i9xx_calc_dpll_params(refclk, &clock);
1b894b59
CW		 808 if (!intel_PLL_is_valid(dev, limit,
809 &clock))
d4906093 810 continue;
1b894b59
CW		 811
812 this_err = abs(clock.dot - target);
d4906093
ML		 813 if (this_err < err_most) {
814 *best_clock = clock;
815 err_most = this_err;
816 max_n = clock.n;
817 found = true;
818 }
819 }
820 }
821 }
822 }
2c07245f
ZW		 823 return found;
824}
825
d5dd62bd
ID		 826/*
827 * Check if the calculated PLL configuration is more optimal compared to the
828 * best configuration and error found so far. Return the calculated error.
829 */
830static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
831 const intel_clock_t *calculated_clock,
832 const intel_clock_t *best_clock,
833 unsigned int best_error_ppm,
834 unsigned int *error_ppm)
835{
9ca3ba01
ID		 836 /*
837 * For CHV ignore the error and consider only the P value.
838 * Prefer a bigger P value based on HW requirements.
839 */
840 if (IS_CHERRYVIEW(dev)) {
841 *error_ppm = 0;
842
843 return calculated_clock->p > best_clock->p;
844 }
845
24be4e46
ID		 846 if (WARN_ON_ONCE(!target_freq))
847 return false;
848
d5dd62bd
ID		 849 *error_ppm = div_u64(1000000ULL *
850 abs(target_freq - calculated_clock->dot),
851 target_freq);
852 /*
853 * Prefer a better P value over a better (smaller) error if the error
854 * is small. Ensure this preference for future configurations too by
855 * setting the error to 0.
856 */
857 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
858 *error_ppm = 0;
859
860 return true;
861 }
862
863 return *error_ppm + 10 < best_error_ppm;
864}
865
a0c4da24 866static bool
a93e255f
ACO		 867vlv_find_best_dpll(const intel_limit_t *limit,
868 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 869 int target, int refclk, intel_clock_t *match_clock,
870 intel_clock_t *best_clock)
a0c4da24 871{
a93e255f 872 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 873 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 874 intel_clock_t clock;
69e4f900 875 unsigned int bestppm = 1000000;
27e639bf
VS		 876 /* min update 19.2 MHz */
877 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 878 bool found = false;
a0c4da24 879
6b4bf1c4
VS		 880 target *= 5; /* fast clock */
881
882 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 883
884 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 885 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 886 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 887 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 888 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 889 clock.p = clock.p1 * clock.p2;
a0c4da24 890 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 891 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 892 unsigned int ppm;
69e4f900 893
6b4bf1c4
VS		 894 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
895 refclk * clock.m1);
896
dccbea3b 897 vlv_calc_dpll_params(refclk, &clock);
43b0ac53 898
f01b7962
VS		 899 if (!intel_PLL_is_valid(dev, limit,
900 &clock))
43b0ac53
VS		 901 continue;
902
d5dd62bd
ID		 903 if (!vlv_PLL_is_optimal(dev, target,
904 &clock,
905 best_clock,
906 bestppm, &ppm))
907 continue;
6b4bf1c4 908
d5dd62bd
ID		 909 *best_clock = clock;
910 bestppm = ppm;
911 found = true;
a0c4da24
JB		 912 }
913 }
914 }
915 }
a0c4da24 916
49e497ef 917 return found;
a0c4da24 918}
a4fc5ed6 919
ef9348c8 920static bool
a93e255f
ACO		 921chv_find_best_dpll(const intel_limit_t *limit,
922 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 923 int target, int refclk, intel_clock_t *match_clock,
924 intel_clock_t *best_clock)
925{
a93e255f 926 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 927 struct drm_device *dev = crtc->base.dev;
9ca3ba01 928 unsigned int best_error_ppm;
ef9348c8
CML		 929 intel_clock_t clock;
930 uint64_t m2;
931 int found = false;
932
933 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 934 best_error_ppm = 1000000;
ef9348c8
CML		 935
936 /*
937 * Based on hardware doc, the n always set to 1, and m1 always
938 * set to 2. If requires to support 200Mhz refclk, we need to
939 * revisit this because n may not 1 anymore.
940 */
941 clock.n = 1, clock.m1 = 2;
942 target *= 5; /* fast clock */
943
944 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
945 for (clock.p2 = limit->p2.p2_fast;
946 clock.p2 >= limit->p2.p2_slow;
947 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 948 unsigned int error_ppm;
ef9348c8
CML		 949
950 clock.p = clock.p1 * clock.p2;
951
952 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
953 clock.n) << 22, refclk * clock.m1);
954
955 if (m2 > INT_MAX/clock.m1)
956 continue;
957
958 clock.m2 = m2;
959
dccbea3b 960 chv_calc_dpll_params(refclk, &clock);
ef9348c8
CML		 961
962 if (!intel_PLL_is_valid(dev, limit, &clock))
963 continue;
964
9ca3ba01
ID		 965 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
966 best_error_ppm, &error_ppm))
967 continue;
968
969 *best_clock = clock;
970 best_error_ppm = error_ppm;
971 found = true;
ef9348c8
CML		 972 }
973 }
974
975 return found;
976}
977
5ab7b0b7
ID		 978bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
979 intel_clock_t *best_clock)
980{
981 int refclk = i9xx_get_refclk(crtc_state, 0);
982
983 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
984 target_clock, refclk, NULL, best_clock);
985}
986
20ddf665
VS		 987bool intel_crtc_active(struct drm_crtc *crtc)
988{
989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
990
991 /* Be paranoid as we can arrive here with only partial
992 * state retrieved from the hardware during setup.
993 *
241bfc38 994 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 995 * as Haswell has gained clock readout/fastboot support.
996 *
66e514c1 997 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 998 * properly reconstruct framebuffers.
c3d1f436
MR		 999 *
1000 * FIXME: The intel_crtc->active here should be switched to
1001 * crtc->state->active once we have proper CRTC states wired up
1002 * for atomic.
20ddf665 1003 */
c3d1f436 1004 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1005 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1006}
1007
a5c961d1
PZ		 1008enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1009 enum pipe pipe)
1010{
1011 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1013
6e3c9717 1014 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1015}
1016
fbf49ea2
VS		 1017static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1018{
1019 struct drm_i915_private *dev_priv = dev->dev_private;
1020 u32 reg = PIPEDSL(pipe);
1021 u32 line1, line2;
1022 u32 line_mask;
1023
1024 if (IS_GEN2(dev))
1025 line_mask = DSL_LINEMASK_GEN2;
1026 else
1027 line_mask = DSL_LINEMASK_GEN3;
1028
1029 line1 = I915_READ(reg) & line_mask;
6adfb1ef 1030 msleep(5);
fbf49ea2
VS		 1031 line2 = I915_READ(reg) & line_mask;
1032
1033 return line1 == line2;
1034}
1035
ab7ad7f6
KP		 1036/*
1037 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1038 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1039 *
1040 * After disabling a pipe, we can't wait for vblank in the usual way,
1041 * spinning on the vblank interrupt status bit, since we won't actually
1042 * see an interrupt when the pipe is disabled.
1043 *
ab7ad7f6
KP		 1044 * On Gen4 and above:
1045 * wait for the pipe register state bit to turn off
1046 *
1047 * Otherwise:
1048 * wait for the display line value to settle (it usually
1049 * ends up stopping at the start of the next frame).
58e10eb9 1050 *
9d0498a2 1051 */
575f7ab7 1052static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1053{
575f7ab7 1054 struct drm_device *dev = crtc->base.dev;
9d0498a2 1055 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1056 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1057 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1058
1059 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1060 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1061
1062 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1063 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1064 100))
284637d9 1065 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1066 } else {
ab7ad7f6 1067 /* Wait for the display line to settle */
fbf49ea2 1068 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1069 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1070 }
79e53945
JB		 1071}
1072
b0ea7d37
DL		 1073/*
1074 * ibx_digital_port_connected - is the specified port connected?
1075 * @dev_priv: i915 private structure
1076 * @port: the port to test
1077 *
1078 * Returns true if @port is connected, false otherwise.
1079 */
1080bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1081 struct intel_digital_port *port)
1082{
1083 u32 bit;
1084
c36346e3 1085 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1086 switch (port->port) {
c36346e3
DL		 1087 case PORT_B:
1088 bit = SDE_PORTB_HOTPLUG;
1089 break;
1090 case PORT_C:
1091 bit = SDE_PORTC_HOTPLUG;
1092 break;
1093 case PORT_D:
1094 bit = SDE_PORTD_HOTPLUG;
1095 break;
1096 default:
1097 return true;
1098 }
1099 } else {
eba905b2 1100 switch (port->port) {
c36346e3
DL		 1101 case PORT_B:
1102 bit = SDE_PORTB_HOTPLUG_CPT;
1103 break;
1104 case PORT_C:
1105 bit = SDE_PORTC_HOTPLUG_CPT;
1106 break;
1107 case PORT_D:
1108 bit = SDE_PORTD_HOTPLUG_CPT;
1109 break;
1110 default:
1111 return true;
1112 }
b0ea7d37
DL		 1113 }
1114
1115 return I915_READ(SDEISR) & bit;
1116}
1117
b24e7179
JB		 1118static const char *state_string(bool enabled)
1119{
1120 return enabled ? "on" : "off";
1121}
1122
1123/* Only for pre-ILK configs */
55607e8a
DV		 1124void assert_pll(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, bool state)
b24e7179
JB		 1126{
1127 int reg;
1128 u32 val;
1129 bool cur_state;
1130
1131 reg = DPLL(pipe);
1132 val = I915_READ(reg);
1133 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1134 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1135 "PLL state assertion failure (expected %s, current %s)\n",
1136 state_string(state), state_string(cur_state));
1137}
b24e7179 1138
23538ef1
JN		 1139/* XXX: the dsi pll is shared between MIPI DSI ports */
1140static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1141{
1142 u32 val;
1143 bool cur_state;
1144
a580516d 1145 mutex_lock(&dev_priv->sb_lock);
23538ef1 1146 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
a580516d 1147 mutex_unlock(&dev_priv->sb_lock);
23538ef1
JN		 1148
1149 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1150 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1151 "DSI PLL state assertion failure (expected %s, current %s)\n",
1152 state_string(state), state_string(cur_state));
1153}
1154#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1155#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1156
55607e8a 1157struct intel_shared_dpll *
e2b78267
DV		 1158intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1159{
1160 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1161
6e3c9717 1162 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1163 return NULL;
1164
6e3c9717 1165 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1166}
1167
040484af 1168/* For ILK+ */
55607e8a
DV		 1169void assert_shared_dpll(struct drm_i915_private *dev_priv,
1170 struct intel_shared_dpll *pll,
1171 bool state)
040484af 1172{
040484af 1173 bool cur_state;
5358901f 1174 struct intel_dpll_hw_state hw_state;
040484af 1175
92b27b08 1176 if (WARN (!pll,
46edb027 1177 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1178 return;
ee7b9f93 1179
5358901f 1180 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1181 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1182 "%s assertion failure (expected %s, current %s)\n",
1183 pll->name, state_string(state), state_string(cur_state));
040484af 1184}
040484af
JB		 1185
1186static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1187 enum pipe pipe, bool state)
1188{
1189 int reg;
1190 u32 val;
1191 bool cur_state;
ad80a810
PZ		 1192 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1193 pipe);
040484af 1194
affa9354
PZ		 1195 if (HAS_DDI(dev_priv->dev)) {
1196 /* DDI does not have a specific FDI_TX register */
ad80a810 1197 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1198 val = I915_READ(reg);
ad80a810 1199 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1200 } else {
1201 reg = FDI_TX_CTL(pipe);
1202 val = I915_READ(reg);
1203 cur_state = !!(val & FDI_TX_ENABLE);
1204 }
e2c719b7 1205 I915_STATE_WARN(cur_state != state,
040484af
JB		 1206 "FDI TX state assertion failure (expected %s, current %s)\n",
1207 state_string(state), state_string(cur_state));
1208}
1209#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1210#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1211
1212static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1213 enum pipe pipe, bool state)
1214{
1215 int reg;
1216 u32 val;
1217 bool cur_state;
1218
d63fa0dc
PZ		 1219 reg = FDI_RX_CTL(pipe);
1220 val = I915_READ(reg);
1221 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1222 I915_STATE_WARN(cur_state != state,
040484af
JB		 1223 "FDI RX state assertion failure (expected %s, current %s)\n",
1224 state_string(state), state_string(cur_state));
1225}
1226#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1227#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1228
1229static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1230 enum pipe pipe)
1231{
1232 int reg;
1233 u32 val;
1234
1235 /* ILK FDI PLL is always enabled */
3d13ef2e 1236 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1237 return;
1238
bf507ef7 1239 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1240 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1241 return;
1242
040484af
JB		 1243 reg = FDI_TX_CTL(pipe);
1244 val = I915_READ(reg);
e2c719b7 1245 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1246}
1247
55607e8a
DV		 1248void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1249 enum pipe pipe, bool state)
040484af
JB		 1250{
1251 int reg;
1252 u32 val;
55607e8a 1253 bool cur_state;
040484af
JB		 1254
1255 reg = FDI_RX_CTL(pipe);
1256 val = I915_READ(reg);
55607e8a 1257 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1258 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1259 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1260 state_string(state), state_string(cur_state));
040484af
JB		 1261}
1262
b680c37a
DV		 1263void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1264 enum pipe pipe)
ea0760cf 1265{
bedd4dba
JN		 1266 struct drm_device *dev = dev_priv->dev;
1267 int pp_reg;
ea0760cf
JB		 1268 u32 val;
1269 enum pipe panel_pipe = PIPE_A;
0de3b485 1270 bool locked = true;
ea0760cf 1271
bedd4dba
JN		 1272 if (WARN_ON(HAS_DDI(dev)))
1273 return;
1274
1275 if (HAS_PCH_SPLIT(dev)) {
1276 u32 port_sel;
1277
ea0760cf 1278 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1279 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1280
1281 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1282 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1283 panel_pipe = PIPE_B;
1284 /* XXX: else fix for eDP */
1285 } else if (IS_VALLEYVIEW(dev)) {
1286 /* presumably write lock depends on pipe, not port select */
1287 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1288 panel_pipe = pipe;
ea0760cf
JB		 1289 } else {
1290 pp_reg = PP_CONTROL;
bedd4dba
JN		 1291 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1292 panel_pipe = PIPE_B;
ea0760cf
JB		 1293 }
1294
1295 val = I915_READ(pp_reg);
1296 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1297 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1298 locked = false;
1299
e2c719b7 1300 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1301 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1302 pipe_name(pipe));
ea0760cf
JB		 1303}
1304
93ce0ba6
JN		 1305static void assert_cursor(struct drm_i915_private *dev_priv,
1306 enum pipe pipe, bool state)
1307{
1308 struct drm_device *dev = dev_priv->dev;
1309 bool cur_state;
1310
d9d82081 1311 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1312 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1313 else
5efb3e28 1314 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1315
e2c719b7 1316 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1317 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1318 pipe_name(pipe), state_string(state), state_string(cur_state));
1319}
1320#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1321#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1322
b840d907
JB		 1323void assert_pipe(struct drm_i915_private *dev_priv,
1324 enum pipe pipe, bool state)
b24e7179
JB		 1325{
1326 int reg;
1327 u32 val;
63d7bbe9 1328 bool cur_state;
702e7a56
PZ		 1329 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1330 pipe);
b24e7179 1331
b6b5d049
VS		 1332 /* if we need the pipe quirk it must be always on */
1333 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1334 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1335 state = true;
1336
f458ebbc 1337 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1338 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1339 cur_state = false;
1340 } else {
1341 reg = PIPECONF(cpu_transcoder);
1342 val = I915_READ(reg);
1343 cur_state = !!(val & PIPECONF_ENABLE);
1344 }
1345
e2c719b7 1346 I915_STATE_WARN(cur_state != state,
63d7bbe9 1347 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1348 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1349}
1350
931872fc
CW		 1351static void assert_plane(struct drm_i915_private *dev_priv,
1352 enum plane plane, bool state)
b24e7179
JB		 1353{
1354 int reg;
1355 u32 val;
931872fc 1356 bool cur_state;
b24e7179
JB		 1357
1358 reg = DSPCNTR(plane);
1359 val = I915_READ(reg);
931872fc 1360 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1361 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1362 "plane %c assertion failure (expected %s, current %s)\n",
1363 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1364}
1365
931872fc
CW		 1366#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1367#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1368
b24e7179
JB		 1369static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1370 enum pipe pipe)
1371{
653e1026 1372 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1373 int reg, i;
1374 u32 val;
1375 int cur_pipe;
1376
653e1026
VS		 1377 /* Primary planes are fixed to pipes on gen4+ */
1378 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1379 reg = DSPCNTR(pipe);
1380 val = I915_READ(reg);
e2c719b7 1381 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1382 "plane %c assertion failure, should be disabled but not\n",
1383 plane_name(pipe));
19ec1358 1384 return;
28c05794 1385 }
19ec1358 1386
b24e7179 1387 /* Need to check both planes against the pipe */
055e393f 1388 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1389 reg = DSPCNTR(i);
1390 val = I915_READ(reg);
1391 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1392 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1393 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1394 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1395 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1396 }
1397}
1398
19332d7a
JB		 1399static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1400 enum pipe pipe)
1401{
20674eef 1402 struct drm_device *dev = dev_priv->dev;
1fe47785 1403 int reg, sprite;
19332d7a
JB		 1404 u32 val;
1405
7feb8b88 1406 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1407 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1408 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1409 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1410 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1411 sprite, pipe_name(pipe));
1412 }
1413 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1414 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1415 reg = SPCNTR(pipe, sprite);
20674eef 1416 val = I915_READ(reg);
e2c719b7 1417 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1418 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1419 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1420 }
1421 } else if (INTEL_INFO(dev)->gen >= 7) {
1422 reg = SPRCTL(pipe);
19332d7a 1423 val = I915_READ(reg);
e2c719b7 1424 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1425 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1426 plane_name(pipe), pipe_name(pipe));
1427 } else if (INTEL_INFO(dev)->gen >= 5) {
1428 reg = DVSCNTR(pipe);
19332d7a 1429 val = I915_READ(reg);
e2c719b7 1430 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1431 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1432 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1433 }
1434}
1435
08c71e5e
VS		 1436static void assert_vblank_disabled(struct drm_crtc *crtc)
1437{
e2c719b7 1438 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1439 drm_crtc_vblank_put(crtc);
1440}
1441
89eff4be 1442static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1443{
1444 u32 val;
1445 bool enabled;
1446
e2c719b7 1447 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1448
92f2584a
JB		 1449 val = I915_READ(PCH_DREF_CONTROL);
1450 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1451 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1452 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1453}
1454
ab9412ba
DV		 1455static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1456 enum pipe pipe)
92f2584a
JB		 1457{
1458 int reg;
1459 u32 val;
1460 bool enabled;
1461
ab9412ba 1462 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1463 val = I915_READ(reg);
1464 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1465 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1466 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1467 pipe_name(pipe));
92f2584a
JB		 1468}
1469
4e634389
KP		 1470static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1471 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1472{
1473 if ((val & DP_PORT_EN) == 0)
1474 return false;
1475
1476 if (HAS_PCH_CPT(dev_priv->dev)) {
1477 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1478 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1479 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1480 return false;
44f37d1f
CML		 1481 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1482 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1483 return false;
f0575e92
KP		 1484 } else {
1485 if ((val & DP_PIPE_MASK) != (pipe << 30))
1486 return false;
1487 }
1488 return true;
1489}
1490
1519b995
KP		 1491static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1492 enum pipe pipe, u32 val)
1493{
dc0fa718 1494 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1495 return false;
1496
1497 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1498 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1499 return false;
44f37d1f
CML		 1500 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1501 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1502 return false;
1519b995 1503 } else {
dc0fa718 1504 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1505 return false;
1506 }
1507 return true;
1508}
1509
1510static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1511 enum pipe pipe, u32 val)
1512{
1513 if ((val & LVDS_PORT_EN) == 0)
1514 return false;
1515
1516 if (HAS_PCH_CPT(dev_priv->dev)) {
1517 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1518 return false;
1519 } else {
1520 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1521 return false;
1522 }
1523 return true;
1524}
1525
1526static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1527 enum pipe pipe, u32 val)
1528{
1529 if ((val & ADPA_DAC_ENABLE) == 0)
1530 return false;
1531 if (HAS_PCH_CPT(dev_priv->dev)) {
1532 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1533 return false;
1534 } else {
1535 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1536 return false;
1537 }
1538 return true;
1539}
1540
291906f1 1541static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1542 enum pipe pipe, int reg, u32 port_sel)
291906f1 1543{
47a05eca 1544 u32 val = I915_READ(reg);
e2c719b7 1545 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1546 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1547 reg, pipe_name(pipe));
de9a35ab 1548
e2c719b7 1549 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1550 && (val & DP_PIPEB_SELECT),
de9a35ab 1551 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1552}
1553
1554static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1555 enum pipe pipe, int reg)
1556{
47a05eca 1557 u32 val = I915_READ(reg);
e2c719b7 1558 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1559 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1560 reg, pipe_name(pipe));
de9a35ab 1561
e2c719b7 1562 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1563 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1564 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1565}
1566
1567static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1568 enum pipe pipe)
1569{
1570 int reg;
1571 u32 val;
291906f1 1572
f0575e92
KP		 1573 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1574 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1575 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1576
1577 reg = PCH_ADPA;
1578 val = I915_READ(reg);
e2c719b7 1579 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1580 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1581 pipe_name(pipe));
291906f1
JB		 1582
1583 reg = PCH_LVDS;
1584 val = I915_READ(reg);
e2c719b7 1585 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1586 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1587 pipe_name(pipe));
291906f1 1588
e2debe91
PZ		 1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1590 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1591 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1592}
1593
40e9cf64
JB		 1594static void intel_init_dpio(struct drm_device *dev)
1595{
1596 struct drm_i915_private *dev_priv = dev->dev_private;
1597
1598 if (!IS_VALLEYVIEW(dev))
1599 return;
1600
a09caddd
CML		 1601 /*
1602 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1603 * CHV x1 PHY (DP/HDMI D)
1604 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1605 */
1606 if (IS_CHERRYVIEW(dev)) {
1607 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1608 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1609 } else {
1610 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1611 }
5382f5f3
JB		 1612}
1613
d288f65f 1614static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1615 const struct intel_crtc_state *pipe_config)
87442f73 1616{
426115cf
DV		 1617 struct drm_device *dev = crtc->base.dev;
1618 struct drm_i915_private *dev_priv = dev->dev_private;
1619 int reg = DPLL(crtc->pipe);
d288f65f 1620 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1621
426115cf 1622 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1623
1624 /* No really, not for ILK+ */
1625 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1626
1627 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1628 if (IS_MOBILE(dev_priv->dev))
426115cf 1629 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1630
426115cf
DV		 1631 I915_WRITE(reg, dpll);
1632 POSTING_READ(reg);
1633 udelay(150);
1634
1635 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1636 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1637
d288f65f 1638 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1639 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1640
1641 /* We do this three times for luck */
426115cf 1642 I915_WRITE(reg, dpll);
87442f73
DV		 1643 POSTING_READ(reg);
1644 udelay(150); /* wait for warmup */
426115cf 1645 I915_WRITE(reg, dpll);
87442f73
DV		 1646 POSTING_READ(reg);
1647 udelay(150); /* wait for warmup */
426115cf 1648 I915_WRITE(reg, dpll);
87442f73
DV		 1649 POSTING_READ(reg);
1650 udelay(150); /* wait for warmup */
1651}
1652
d288f65f 1653static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1654 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1655{
1656 struct drm_device *dev = crtc->base.dev;
1657 struct drm_i915_private *dev_priv = dev->dev_private;
1658 int pipe = crtc->pipe;
1659 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1660 u32 tmp;
1661
1662 assert_pipe_disabled(dev_priv, crtc->pipe);
1663
1664 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1665
a580516d 1666 mutex_lock(&dev_priv->sb_lock);
9d556c99
CML		 1667
1668 /* Enable back the 10bit clock to display controller */
1669 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1670 tmp |= DPIO_DCLKP_EN;
1671 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1672
54433e91
VS		 1673 mutex_unlock(&dev_priv->sb_lock);
1674
9d556c99
CML		 1675 /*
1676 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1677 */
1678 udelay(1);
1679
1680 /* Enable PLL */
d288f65f 1681 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1682
1683 /* Check PLL is locked */
a11b0703 1684 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1685 DRM_ERROR("PLL %d failed to lock\n", pipe);
1686
a11b0703 1687 /* not sure when this should be written */
d288f65f 1688 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703 1689 POSTING_READ(DPLL_MD(pipe));
9d556c99
CML		 1690}
1691
1c4e0274
VS		 1692static int intel_num_dvo_pipes(struct drm_device *dev)
1693{
1694 struct intel_crtc *crtc;
1695 int count = 0;
1696
1697 for_each_intel_crtc(dev, crtc)
3538b9df 1698 count += crtc->base.state->active &&
409ee761 1699 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1700
1701 return count;
1702}
1703
66e3d5c0 1704static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1705{
66e3d5c0
DV		 1706 struct drm_device *dev = crtc->base.dev;
1707 struct drm_i915_private *dev_priv = dev->dev_private;
1708 int reg = DPLL(crtc->pipe);
6e3c9717 1709 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1710
66e3d5c0 1711 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1712
63d7bbe9 1713 /* No really, not for ILK+ */
3d13ef2e 1714 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1715
1716 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1717 if (IS_MOBILE(dev) && !IS_I830(dev))
1718 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1719
1c4e0274
VS		 1720 /* Enable DVO 2x clock on both PLLs if necessary */
1721 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1722 /*
1723 * It appears to be important that we don't enable this
1724 * for the current pipe before otherwise configuring the
1725 * PLL. No idea how this should be handled if multiple
1726 * DVO outputs are enabled simultaneosly.
1727 */
1728 dpll |= DPLL_DVO_2X_MODE;
1729 I915_WRITE(DPLL(!crtc->pipe),
1730 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1731 }
66e3d5c0
DV		 1732
1733 /* Wait for the clocks to stabilize. */
1734 POSTING_READ(reg);
1735 udelay(150);
1736
1737 if (INTEL_INFO(dev)->gen >= 4) {
1738 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1739 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1740 } else {
1741 /* The pixel multiplier can only be updated once the
1742 * DPLL is enabled and the clocks are stable.
1743 *
1744 * So write it again.
1745 */
1746 I915_WRITE(reg, dpll);
1747 }
63d7bbe9
JB		 1748
1749 /* We do this three times for luck */
66e3d5c0 1750 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1751 POSTING_READ(reg);
1752 udelay(150); /* wait for warmup */
66e3d5c0 1753 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1754 POSTING_READ(reg);
1755 udelay(150); /* wait for warmup */
66e3d5c0 1756 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1757 POSTING_READ(reg);
1758 udelay(150); /* wait for warmup */
1759}
1760
1761/**
50b44a44 1762 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1763 * @dev_priv: i915 private structure
1764 * @pipe: pipe PLL to disable
1765 *
1766 * Disable the PLL for @pipe, making sure the pipe is off first.
1767 *
1768 * Note! This is for pre-ILK only.
1769 */
1c4e0274 1770static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1771{
1c4e0274
VS		 1772 struct drm_device *dev = crtc->base.dev;
1773 struct drm_i915_private *dev_priv = dev->dev_private;
1774 enum pipe pipe = crtc->pipe;
1775
1776 /* Disable DVO 2x clock on both PLLs if necessary */
1777 if (IS_I830(dev) &&
409ee761 1778 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
3538b9df 1779 !intel_num_dvo_pipes(dev)) {
1c4e0274
VS		 1780 I915_WRITE(DPLL(PIPE_B),
1781 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1782 I915_WRITE(DPLL(PIPE_A),
1783 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1784 }
1785
b6b5d049
VS		 1786 /* Don't disable pipe or pipe PLLs if needed */
1787 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1788 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1789 return;
1790
1791 /* Make sure the pipe isn't still relying on us */
1792 assert_pipe_disabled(dev_priv, pipe);
1793
b8afb911 1794 I915_WRITE(DPLL(pipe), DPLL_VGA_MODE_DIS);
50b44a44 1795 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1796}
1797
f6071166
JB		 1798static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1799{
b8afb911 1800 u32 val;
f6071166
JB		 1801
1802 /* Make sure the pipe isn't still relying on us */
1803 assert_pipe_disabled(dev_priv, pipe);
1804
e5cbfbfb
ID		 1805 /*
1806 * Leave integrated clock source and reference clock enabled for pipe B.
1807 * The latter is needed for VGA hotplug / manual detection.
1808 */
b8afb911 1809 val = DPLL_VGA_MODE_DIS;
f6071166 1810 if (pipe == PIPE_B)
60bfe44f 1811 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REF_CLK_ENABLE_VLV;
f6071166
JB		 1812 I915_WRITE(DPLL(pipe), val);
1813 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1814
1815}
1816
1817static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1818{
d752048d 1819 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1820 u32 val;
1821
a11b0703
VS		 1822 /* Make sure the pipe isn't still relying on us */
1823 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1824
a11b0703 1825 /* Set PLL en = 0 */
60bfe44f
VS		 1826 val = DPLL_SSC_REF_CLK_CHV |
1827 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
a11b0703
VS		 1828 if (pipe != PIPE_A)
1829 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1830 I915_WRITE(DPLL(pipe), val);
1831 POSTING_READ(DPLL(pipe));
d752048d 1832
a580516d 1833 mutex_lock(&dev_priv->sb_lock);
d752048d
VS		 1834
1835 /* Disable 10bit clock to display controller */
1836 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1837 val &= ~DPIO_DCLKP_EN;
1838 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1839
61407f6d
VS		 1840 /* disable left/right clock distribution */
1841 if (pipe != PIPE_B) {
1842 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1843 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1844 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1845 } else {
1846 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1847 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1848 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1849 }
1850
a580516d 1851 mutex_unlock(&dev_priv->sb_lock);
f6071166
JB		 1852}
1853
e4607fcf 1854void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1855 struct intel_digital_port *dport,
1856 unsigned int expected_mask)
89b667f8
JB		 1857{
1858 u32 port_mask;
00fc31b7 1859 int dpll_reg;
89b667f8 1860
e4607fcf
CML		 1861 switch (dport->port) {
1862 case PORT_B:
89b667f8 1863 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1864 dpll_reg = DPLL(0);
e4607fcf
CML		 1865 break;
1866 case PORT_C:
89b667f8 1867 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1868 dpll_reg = DPLL(0);
9b6de0a1 1869 expected_mask <<= 4;
00fc31b7
CML		 1870 break;
1871 case PORT_D:
1872 port_mask = DPLL_PORTD_READY_MASK;
1873 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1874 break;
1875 default:
1876 BUG();
1877 }
89b667f8 1878
9b6de0a1
VS		 1879 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1880 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1881 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1882}
1883
b14b1055
DV		 1884static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1885{
1886 struct drm_device *dev = crtc->base.dev;
1887 struct drm_i915_private *dev_priv = dev->dev_private;
1888 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1889
be19f0ff
CW		 1890 if (WARN_ON(pll == NULL))
1891 return;
1892
3e369b76 1893 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1894 if (pll->active == 0) {
1895 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1896 WARN_ON(pll->on);
1897 assert_shared_dpll_disabled(dev_priv, pll);
1898
1899 pll->mode_set(dev_priv, pll);
1900 }
1901}
1902
92f2584a 1903/**
85b3894f 1904 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1905 * @dev_priv: i915 private structure
1906 * @pipe: pipe PLL to enable
1907 *
1908 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1909 * drives the transcoder clock.
1910 */
85b3894f 1911static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1912{
3d13ef2e
DL		 1913 struct drm_device *dev = crtc->base.dev;
1914 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1915 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1916
87a875bb 1917 if (WARN_ON(pll == NULL))
48da64a8
CW		 1918 return;
1919
3e369b76 1920 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1921 return;
ee7b9f93 1922
74dd6928 1923 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1924 pll->name, pll->active, pll->on,
e2b78267 1925 crtc->base.base.id);
92f2584a 1926
cdbd2316
DV		 1927 if (pll->active++) {
1928 WARN_ON(!pll->on);
e9d6944e 1929 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1930 return;
1931 }
f4a091c7 1932 WARN_ON(pll->on);
ee7b9f93 1933
bd2bb1b9
PZ		 1934 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1935
46edb027 1936 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1937 pll->enable(dev_priv, pll);
ee7b9f93 1938 pll->on = true;
92f2584a
JB		 1939}
1940
f6daaec2 1941static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1942{
3d13ef2e
DL		 1943 struct drm_device *dev = crtc->base.dev;
1944 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1945 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1946
92f2584a 1947 /* PCH only available on ILK+ */
3d13ef2e 1948 BUG_ON(INTEL_INFO(dev)->gen < 5);
eddfcbcd
ML		 1949 if (pll == NULL)
1950 return;
92f2584a 1951
eddfcbcd 1952 if (WARN_ON(!(pll->config.crtc_mask & (1 << drm_crtc_index(&crtc->base)))))
48da64a8 1953 return;
7a419866 1954
46edb027
DV		 1955 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1956 pll->name, pll->active, pll->on,
e2b78267 1957 crtc->base.base.id);
7a419866 1958
48da64a8 1959 if (WARN_ON(pll->active == 0)) {
e9d6944e 1960 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1961 return;
1962 }
1963
e9d6944e 1964 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1965 WARN_ON(!pll->on);
cdbd2316 1966 if (--pll->active)
7a419866 1967 return;
ee7b9f93 1968
46edb027 1969 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1970 pll->disable(dev_priv, pll);
ee7b9f93 1971 pll->on = false;
bd2bb1b9
PZ		 1972
1973 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1974}
1975
b8a4f404
PZ		 1976static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1977 enum pipe pipe)
040484af 1978{
23670b32 1979 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1980 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1981 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1982 uint32_t reg, val, pipeconf_val;
040484af
JB		 1983
1984 /* PCH only available on ILK+ */
55522f37 1985 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1986
1987 /* Make sure PCH DPLL is enabled */
e72f9fbf 1988 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1989 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1990
1991 /* FDI must be feeding us bits for PCH ports */
1992 assert_fdi_tx_enabled(dev_priv, pipe);
1993 assert_fdi_rx_enabled(dev_priv, pipe);
1994
23670b32
DV		 1995 if (HAS_PCH_CPT(dev)) {
1996 /* Workaround: Set the timing override bit before enabling the
1997 * pch transcoder. */
1998 reg = TRANS_CHICKEN2(pipe);
1999 val = I915_READ(reg);
2000 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
2001 I915_WRITE(reg, val);
59c859d6 2002 }
23670b32 2003
ab9412ba 2004 reg = PCH_TRANSCONF(pipe);
040484af 2005 val = I915_READ(reg);
5f7f726d 2006 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 2007
2008 if (HAS_PCH_IBX(dev_priv->dev)) {
2009 /*
c5de7c6f
VS		 2010 * Make the BPC in transcoder be consistent with
2011 * that in pipeconf reg. For HDMI we must use 8bpc
2012 * here for both 8bpc and 12bpc.
e9bcff5c 2013 */
dfd07d72 2014 val &= ~PIPECONF_BPC_MASK;
c5de7c6f
VS		 2015 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_HDMI))
2016 val |= PIPECONF_8BPC;
2017 else
2018 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2019 }
5f7f726d
PZ		 2020
2021 val &= ~TRANS_INTERLACE_MASK;
2022 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2023 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2024 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2025 val |= TRANS_LEGACY_INTERLACED_ILK;
2026 else
2027 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2028 else
2029 val |= TRANS_PROGRESSIVE;
2030
040484af
JB		 2031 I915_WRITE(reg, val | TRANS_ENABLE);
2032 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2033 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2034}
2035
8fb033d7 2036static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2037 enum transcoder cpu_transcoder)
040484af 2038{
8fb033d7 2039 u32 val, pipeconf_val;
8fb033d7
PZ		 2040
2041 /* PCH only available on ILK+ */
55522f37 2042 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2043
8fb033d7 2044 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2045 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2046 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2047
223a6fdf
PZ		 2048 /* Workaround: set timing override bit. */
2049 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2050 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2051 I915_WRITE(_TRANSA_CHICKEN2, val);
2052
25f3ef11 2053 val = TRANS_ENABLE;
937bb610 2054 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2055
9a76b1c6
PZ		 2056 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2057 PIPECONF_INTERLACED_ILK)
a35f2679 2058 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2059 else
2060 val |= TRANS_PROGRESSIVE;
2061
ab9412ba
DV		 2062 I915_WRITE(LPT_TRANSCONF, val);
2063 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2064 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2065}
2066
b8a4f404
PZ		 2067static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2068 enum pipe pipe)
040484af 2069{
23670b32
DV		 2070 struct drm_device *dev = dev_priv->dev;
2071 uint32_t reg, val;
040484af
JB		 2072
2073 /* FDI relies on the transcoder */
2074 assert_fdi_tx_disabled(dev_priv, pipe);
2075 assert_fdi_rx_disabled(dev_priv, pipe);
2076
291906f1
JB		 2077 /* Ports must be off as well */
2078 assert_pch_ports_disabled(dev_priv, pipe);
2079
ab9412ba 2080 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2081 val = I915_READ(reg);
2082 val &= ~TRANS_ENABLE;
2083 I915_WRITE(reg, val);
2084 /* wait for PCH transcoder off, transcoder state */
2085 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2086 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2087
2088 if (!HAS_PCH_IBX(dev)) {
2089 /* Workaround: Clear the timing override chicken bit again. */
2090 reg = TRANS_CHICKEN2(pipe);
2091 val = I915_READ(reg);
2092 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2093 I915_WRITE(reg, val);
2094 }
040484af
JB		 2095}
2096
ab4d966c 2097static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2098{
8fb033d7
PZ		 2099 u32 val;
2100
ab9412ba 2101 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2102 val &= ~TRANS_ENABLE;
ab9412ba 2103 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2104 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2105 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2106 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2107
2108 /* Workaround: clear timing override bit. */
2109 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2110 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2111 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2112}
2113
b24e7179 2114/**
309cfea8 2115 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2116 * @crtc: crtc responsible for the pipe
b24e7179 2117 *
0372264a 2118 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2119 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2120 */
e1fdc473 2121static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2122{
0372264a
PZ		 2123 struct drm_device *dev = crtc->base.dev;
2124 struct drm_i915_private *dev_priv = dev->dev_private;
2125 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2126 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2127 pipe);
1a240d4d 2128 enum pipe pch_transcoder;
b24e7179
JB		 2129 int reg;
2130 u32 val;
2131
9e2ee2dd
VS		 2132 DRM_DEBUG_KMS("enabling pipe %c\n", pipe_name(pipe));
2133
58c6eaa2 2134 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2135 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2136 assert_sprites_disabled(dev_priv, pipe);
2137
681e5811 2138 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2139 pch_transcoder = TRANSCODER_A;
2140 else
2141 pch_transcoder = pipe;
2142
b24e7179
JB		 2143 /*
2144 * A pipe without a PLL won't actually be able to drive bits from
2145 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2146 * need the check.
2147 */
50360403 2148 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2149 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2150 assert_dsi_pll_enabled(dev_priv);
2151 else
2152 assert_pll_enabled(dev_priv, pipe);
040484af 2153 else {
6e3c9717 2154 if (crtc->config->has_pch_encoder) {
040484af 2155 /* if driving the PCH, we need FDI enabled */
cc391bbb 2156 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2157 assert_fdi_tx_pll_enabled(dev_priv,
2158 (enum pipe) cpu_transcoder);
040484af
JB		 2159 }
2160 /* FIXME: assert CPU port conditions for SNB+ */
2161 }
b24e7179 2162
702e7a56 2163 reg = PIPECONF(cpu_transcoder);
b24e7179 2164 val = I915_READ(reg);
7ad25d48 2165 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2166 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2167 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2168 return;
7ad25d48 2169 }
00d70b15
CW		 2170
2171 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2172 POSTING_READ(reg);
b24e7179
JB		 2173}
2174
2175/**
309cfea8 2176 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2177 * @crtc: crtc whose pipes is to be disabled
b24e7179 2178 *
575f7ab7
VS		 2179 * Disable the pipe of @crtc, making sure that various hardware
2180 * specific requirements are met, if applicable, e.g. plane
2181 * disabled, panel fitter off, etc.
b24e7179
JB		 2182 *
2183 * Will wait until the pipe has shut down before returning.
2184 */
575f7ab7 2185static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2186{
575f7ab7 2187 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2188 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2189 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2190 int reg;
2191 u32 val;
2192
9e2ee2dd
VS		 2193 DRM_DEBUG_KMS("disabling pipe %c\n", pipe_name(pipe));
2194
b24e7179
JB		 2195 /*
2196 * Make sure planes won't keep trying to pump pixels to us,
2197 * or we might hang the display.
2198 */
2199 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2200 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2201 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2202
702e7a56 2203 reg = PIPECONF(cpu_transcoder);
b24e7179 2204 val = I915_READ(reg);
00d70b15
CW		 2205 if ((val & PIPECONF_ENABLE) == 0)
2206 return;
2207
67adc644
VS		 2208 /*
2209 * Double wide has implications for planes
2210 * so best keep it disabled when not needed.
2211 */
6e3c9717 2212 if (crtc->config->double_wide)
67adc644
VS		 2213 val &= ~PIPECONF_DOUBLE_WIDE;
2214
2215 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2216 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2217 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2218 val &= ~PIPECONF_ENABLE;
2219
2220 I915_WRITE(reg, val);
2221 if ((val & PIPECONF_ENABLE) == 0)
2222 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2223}
2224
693db184
CW		 2225static bool need_vtd_wa(struct drm_device *dev)
2226{
2227#ifdef CONFIG_INTEL_IOMMU
2228 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2229 return true;
2230#endif
2231 return false;
2232}
2233
50470bb0 2234unsigned int
6761dd31
TU		 2235intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2236 uint64_t fb_format_modifier)
a57ce0b2 2237{
6761dd31
TU		 2238 unsigned int tile_height;
2239 uint32_t pixel_bytes;
a57ce0b2 2240
b5d0e9bf
DL		 2241 switch (fb_format_modifier) {
2242 case DRM_FORMAT_MOD_NONE:
2243 tile_height = 1;
2244 break;
2245 case I915_FORMAT_MOD_X_TILED:
2246 tile_height = IS_GEN2(dev) ? 16 : 8;
2247 break;
2248 case I915_FORMAT_MOD_Y_TILED:
2249 tile_height = 32;
2250 break;
2251 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2252 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2253 switch (pixel_bytes) {
b5d0e9bf 2254 default:
6761dd31 2255 case 1:
b5d0e9bf
DL		 2256 tile_height = 64;
2257 break;
6761dd31
TU		 2258 case 2:
2259 case 4:
b5d0e9bf
DL		 2260 tile_height = 32;
2261 break;
6761dd31 2262 case 8:
b5d0e9bf
DL		 2263 tile_height = 16;
2264 break;
6761dd31 2265 case 16:
b5d0e9bf
DL		 2266 WARN_ONCE(1,
2267 "128-bit pixels are not supported for display!");
2268 tile_height = 16;
2269 break;
2270 }
2271 break;
2272 default:
2273 MISSING_CASE(fb_format_modifier);
2274 tile_height = 1;
2275 break;
2276 }
091df6cb 2277
6761dd31
TU		 2278 return tile_height;
2279}
2280
2281unsigned int
2282intel_fb_align_height(struct drm_device *dev, unsigned int height,
2283 uint32_t pixel_format, uint64_t fb_format_modifier)
2284{
2285 return ALIGN(height, intel_tile_height(dev, pixel_format,
2286 fb_format_modifier));
a57ce0b2
JB		 2287}
2288
f64b98cd
TU		 2289static int
2290intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2291 const struct drm_plane_state *plane_state)
2292{
50470bb0 2293 struct intel_rotation_info *info = &view->rotation_info;
84fe03f7 2294 unsigned int tile_height, tile_pitch;
50470bb0 2295
f64b98cd
TU		 2296 *view = i915_ggtt_view_normal;
2297
50470bb0
TU		 2298 if (!plane_state)
2299 return 0;
2300
121920fa 2301 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2302 return 0;
2303
9abc4648 2304 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2305
2306 info->height = fb->height;
2307 info->pixel_format = fb->pixel_format;
2308 info->pitch = fb->pitches[0];
2309 info->fb_modifier = fb->modifier[0];
2310
84fe03f7
TU		 2311 tile_height = intel_tile_height(fb->dev, fb->pixel_format,
2312 fb->modifier[0]);
2313 tile_pitch = PAGE_SIZE / tile_height;
2314 info->width_pages = DIV_ROUND_UP(fb->pitches[0], tile_pitch);
2315 info->height_pages = DIV_ROUND_UP(fb->height, tile_height);
2316 info->size = info->width_pages * info->height_pages * PAGE_SIZE;
2317
f64b98cd
TU		 2318 return 0;
2319}
2320
4e9a86b6
VS		 2321static unsigned int intel_linear_alignment(struct drm_i915_private *dev_priv)
2322{
2323 if (INTEL_INFO(dev_priv)->gen >= 9)
2324 return 256 * 1024;
985b8bb4
VS		 2325 else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
2326 IS_VALLEYVIEW(dev_priv))
4e9a86b6
VS		 2327 return 128 * 1024;
2328 else if (INTEL_INFO(dev_priv)->gen >= 4)
2329 return 4 * 1024;
2330 else
44c5905e 2331 return 0;
4e9a86b6
VS		 2332}
2333
127bd2ac 2334int
850c4cdc
TU		 2335intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2336 struct drm_framebuffer *fb,
82bc3b2d 2337 const struct drm_plane_state *plane_state,
91af127f
JH		 2338 struct intel_engine_cs *pipelined,
2339 struct drm_i915_gem_request **pipelined_request)
6b95a207 2340{
850c4cdc 2341 struct drm_device *dev = fb->dev;
ce453d81 2342 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2343 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2344 struct i915_ggtt_view view;
6b95a207
KH		 2345 u32 alignment;
2346 int ret;
2347
ebcdd39e
MR		 2348 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2349
7b911adc
TU		 2350 switch (fb->modifier[0]) {
2351 case DRM_FORMAT_MOD_NONE:
4e9a86b6 2352 alignment = intel_linear_alignment(dev_priv);
6b95a207 2353 break;
7b911adc 2354 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2355 if (INTEL_INFO(dev)->gen >= 9)
2356 alignment = 256 * 1024;
2357 else {
2358 /* pin() will align the object as required by fence */
2359 alignment = 0;
2360 }
6b95a207 2361 break;
7b911adc 2362 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2363 case I915_FORMAT_MOD_Yf_TILED:
2364 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2365 "Y tiling bo slipped through, driver bug!\n"))
2366 return -EINVAL;
2367 alignment = 1 * 1024 * 1024;
2368 break;
6b95a207 2369 default:
7b911adc
TU		 2370 MISSING_CASE(fb->modifier[0]);
2371 return -EINVAL;
6b95a207
KH		 2372 }
2373
f64b98cd
TU		 2374 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2375 if (ret)
2376 return ret;
2377
693db184
CW		 2378 /* Note that the w/a also requires 64 PTE of padding following the
2379 * bo. We currently fill all unused PTE with the shadow page and so
2380 * we should always have valid PTE following the scanout preventing
2381 * the VT-d warning.
2382 */
2383 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2384 alignment = 256 * 1024;
2385
d6dd6843
PZ		 2386 /*
2387 * Global gtt pte registers are special registers which actually forward
2388 * writes to a chunk of system memory. Which means that there is no risk
2389 * that the register values disappear as soon as we call
2390 * intel_runtime_pm_put(), so it is correct to wrap only the
2391 * pin/unpin/fence and not more.
2392 */
2393 intel_runtime_pm_get(dev_priv);
2394
ce453d81 2395 dev_priv->mm.interruptible = false;
e6617330 2396 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
91af127f 2397 pipelined_request, &view);
48b956c5 2398 if (ret)
ce453d81 2399 goto err_interruptible;
6b95a207
KH		 2400
2401 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2402 * fence, whereas 965+ only requires a fence if using
2403 * framebuffer compression. For simplicity, we always install
2404 * a fence as the cost is not that onerous.
2405 */
06d98131 2406 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2407 if (ret)
2408 goto err_unpin;
1690e1eb 2409
9a5a53b3 2410 i915_gem_object_pin_fence(obj);
6b95a207 2411
ce453d81 2412 dev_priv->mm.interruptible = true;
d6dd6843 2413 intel_runtime_pm_put(dev_priv);
6b95a207 2414 return 0;
48b956c5
CW		 2415
2416err_unpin:
f64b98cd 2417 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2418err_interruptible:
2419 dev_priv->mm.interruptible = true;
d6dd6843 2420 intel_runtime_pm_put(dev_priv);
48b956c5 2421 return ret;
6b95a207
KH		 2422}
2423
82bc3b2d
TU		 2424static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2425 const struct drm_plane_state *plane_state)
1690e1eb 2426{
82bc3b2d 2427 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2428 struct i915_ggtt_view view;
2429 int ret;
82bc3b2d 2430
ebcdd39e
MR		 2431 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2432
f64b98cd
TU		 2433 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2434 WARN_ONCE(ret, "Couldn't get view from plane state!");
2435
1690e1eb 2436 i915_gem_object_unpin_fence(obj);
f64b98cd 2437 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2438}
2439
c2c75131
DV		 2440/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2441 * is assumed to be a power-of-two. */
4e9a86b6
VS		 2442unsigned long intel_gen4_compute_page_offset(struct drm_i915_private *dev_priv,
2443 int *x, int *y,
bc752862
CW		 2444 unsigned int tiling_mode,
2445 unsigned int cpp,
2446 unsigned int pitch)
c2c75131 2447{
bc752862
CW		 2448 if (tiling_mode != I915_TILING_NONE) {
2449 unsigned int tile_rows, tiles;
c2c75131 2450
bc752862
CW		 2451 tile_rows = *y / 8;
2452 *y %= 8;
c2c75131 2453
bc752862
CW		 2454 tiles = *x / (512/cpp);
2455 *x %= 512/cpp;
2456
2457 return tile_rows * pitch * 8 + tiles * 4096;
2458 } else {
4e9a86b6 2459 unsigned int alignment = intel_linear_alignment(dev_priv) - 1;
bc752862
CW		 2460 unsigned int offset;
2461
2462 offset = *y * pitch + *x * cpp;
4e9a86b6
VS		 2463 *y = (offset & alignment) / pitch;
2464 *x = ((offset & alignment) - *y * pitch) / cpp;
2465 return offset & ~alignment;
bc752862 2466 }
c2c75131
DV		 2467}
2468
b35d63fa 2469static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2470{
2471 switch (format) {
2472 case DISPPLANE_8BPP:
2473 return DRM_FORMAT_C8;
2474 case DISPPLANE_BGRX555:
2475 return DRM_FORMAT_XRGB1555;
2476 case DISPPLANE_BGRX565:
2477 return DRM_FORMAT_RGB565;
2478 default:
2479 case DISPPLANE_BGRX888:
2480 return DRM_FORMAT_XRGB8888;
2481 case DISPPLANE_RGBX888:
2482 return DRM_FORMAT_XBGR8888;
2483 case DISPPLANE_BGRX101010:
2484 return DRM_FORMAT_XRGB2101010;
2485 case DISPPLANE_RGBX101010:
2486 return DRM_FORMAT_XBGR2101010;
2487 }
2488}
2489
bc8d7dff
DL		 2490static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2491{
2492 switch (format) {
2493 case PLANE_CTL_FORMAT_RGB_565:
2494 return DRM_FORMAT_RGB565;
2495 default:
2496 case PLANE_CTL_FORMAT_XRGB_8888:
2497 if (rgb_order) {
2498 if (alpha)
2499 return DRM_FORMAT_ABGR8888;
2500 else
2501 return DRM_FORMAT_XBGR8888;
2502 } else {
2503 if (alpha)
2504 return DRM_FORMAT_ARGB8888;
2505 else
2506 return DRM_FORMAT_XRGB8888;
2507 }
2508 case PLANE_CTL_FORMAT_XRGB_2101010:
2509 if (rgb_order)
2510 return DRM_FORMAT_XBGR2101010;
2511 else
2512 return DRM_FORMAT_XRGB2101010;
2513 }
2514}
2515
5724dbd1 2516static bool
f6936e29
DV		 2517intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2518 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2519{
2520 struct drm_device *dev = crtc->base.dev;
2521 struct drm_i915_gem_object *obj = NULL;
2522 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2523 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2524 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2525 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2526 PAGE_SIZE);
2527
2528 size_aligned -= base_aligned;
46f297fb 2529
ff2652ea
CW		 2530 if (plane_config->size == 0)
2531 return false;
2532
f37b5c2b
DV		 2533 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2534 base_aligned,
2535 base_aligned,
2536 size_aligned);
46f297fb 2537 if (!obj)
484b41dd 2538 return false;
46f297fb 2539
49af449b
DL		 2540 obj->tiling_mode = plane_config->tiling;
2541 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2542 obj->stride = fb->pitches[0];
46f297fb 2543
6bf129df
DL		 2544 mode_cmd.pixel_format = fb->pixel_format;
2545 mode_cmd.width = fb->width;
2546 mode_cmd.height = fb->height;
2547 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2548 mode_cmd.modifier[0] = fb->modifier[0];
2549 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2550
2551 mutex_lock(&dev->struct_mutex);
6bf129df 2552 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2553 &mode_cmd, obj)) {
46f297fb
JB		 2554 DRM_DEBUG_KMS("intel fb init failed\n");
2555 goto out_unref_obj;
2556 }
46f297fb 2557 mutex_unlock(&dev->struct_mutex);
484b41dd 2558
f6936e29 2559 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2560 return true;
46f297fb
JB		 2561
2562out_unref_obj:
2563 drm_gem_object_unreference(&obj->base);
2564 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2565 return false;
2566}
2567
afd65eb4
MR		 2568/* Update plane->state->fb to match plane->fb after driver-internal updates */
2569static void
2570update_state_fb(struct drm_plane *plane)
2571{
2572 if (plane->fb == plane->state->fb)
2573 return;
2574
2575 if (plane->state->fb)
2576 drm_framebuffer_unreference(plane->state->fb);
2577 plane->state->fb = plane->fb;
2578 if (plane->state->fb)
2579 drm_framebuffer_reference(plane->state->fb);
2580}
2581
5724dbd1 2582static void
f6936e29
DV		 2583intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2584 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2585{
2586 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2587 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2588 struct drm_crtc *c;
2589 struct intel_crtc *i;
2ff8fde1 2590 struct drm_i915_gem_object *obj;
88595ac9 2591 struct drm_plane *primary = intel_crtc->base.primary;
be5651f2 2592 struct drm_plane_state *plane_state = primary->state;
88595ac9 2593 struct drm_framebuffer *fb;
484b41dd 2594
2d14030b 2595 if (!plane_config->fb)
484b41dd
JB		 2596 return;
2597
f6936e29 2598 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2599 fb = &plane_config->fb->base;
2600 goto valid_fb;
f55548b5 2601 }
484b41dd 2602
2d14030b 2603 kfree(plane_config->fb);
484b41dd
JB		 2604
2605 /*
2606 * Failed to alloc the obj, check to see if we should share
2607 * an fb with another CRTC instead
2608 */
70e1e0ec 2609 for_each_crtc(dev, c) {
484b41dd
JB		 2610 i = to_intel_crtc(c);
2611
2612 if (c == &intel_crtc->base)
2613 continue;
2614
2ff8fde1
MR		 2615 if (!i->active)
2616 continue;
2617
88595ac9
DV		 2618 fb = c->primary->fb;
2619 if (!fb)
484b41dd
JB		 2620 continue;
2621
88595ac9 2622 obj = intel_fb_obj(fb);
2ff8fde1 2623 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2624 drm_framebuffer_reference(fb);
2625 goto valid_fb;
484b41dd
JB		 2626 }
2627 }
88595ac9
DV		 2628
2629 return;
2630
2631valid_fb:
be5651f2
ML		 2632 plane_state->src_x = plane_state->src_y = 0;
2633 plane_state->src_w = fb->width << 16;
2634 plane_state->src_h = fb->height << 16;
2635
2636 plane_state->crtc_x = plane_state->src_y = 0;
2637 plane_state->crtc_w = fb->width;
2638 plane_state->crtc_h = fb->height;
2639
88595ac9
DV		 2640 obj = intel_fb_obj(fb);
2641 if (obj->tiling_mode != I915_TILING_NONE)
2642 dev_priv->preserve_bios_swizzle = true;
2643
be5651f2
ML		 2644 drm_framebuffer_reference(fb);
2645 primary->fb = primary->state->fb = fb;
36750f28 2646 primary->crtc = primary->state->crtc = &intel_crtc->base;
36750f28 2647 intel_crtc->base.state->plane_mask |= (1 << drm_plane_index(primary));
a9ff8714 2648 obj->frontbuffer_bits |= to_intel_plane(primary)->frontbuffer_bit;
46f297fb
JB		 2649}
2650
29b9bde6
DV		 2651static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2652 struct drm_framebuffer *fb,
2653 int x, int y)
81255565
JB		 2654{
2655 struct drm_device *dev = crtc->dev;
2656 struct drm_i915_private *dev_priv = dev->dev_private;
2657 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2658 struct drm_plane *primary = crtc->primary;
2659 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2660 struct drm_i915_gem_object *obj;
81255565 2661 int plane = intel_crtc->plane;
e506a0c6 2662 unsigned long linear_offset;
81255565 2663 u32 dspcntr;
f45651ba 2664 u32 reg = DSPCNTR(plane);
48404c1e 2665 int pixel_size;
f45651ba 2666
b70709a6 2667 if (!visible || !fb) {
fdd508a6
VS		 2668 I915_WRITE(reg, 0);
2669 if (INTEL_INFO(dev)->gen >= 4)
2670 I915_WRITE(DSPSURF(plane), 0);
2671 else
2672 I915_WRITE(DSPADDR(plane), 0);
2673 POSTING_READ(reg);
2674 return;
2675 }
2676
c9ba6fad
VS		 2677 obj = intel_fb_obj(fb);
2678 if (WARN_ON(obj == NULL))
2679 return;
2680
2681 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2682
f45651ba
VS		 2683 dspcntr = DISPPLANE_GAMMA_ENABLE;
2684
fdd508a6 2685 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2686
2687 if (INTEL_INFO(dev)->gen < 4) {
2688 if (intel_crtc->pipe == PIPE_B)
2689 dspcntr |= DISPPLANE_SEL_PIPE_B;
2690
2691 /* pipesrc and dspsize control the size that is scaled from,
2692 * which should always be the user's requested size.
2693 */
2694 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2695 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2696 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2697 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2698 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2699 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2700 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2701 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2702 I915_WRITE(PRIMPOS(plane), 0);
2703 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2704 }
81255565 2705
57779d06
VS		 2706 switch (fb->pixel_format) {
2707 case DRM_FORMAT_C8:
81255565
JB		 2708 dspcntr |= DISPPLANE_8BPP;
2709 break;
57779d06 2710 case DRM_FORMAT_XRGB1555:
57779d06 2711 dspcntr |= DISPPLANE_BGRX555;
81255565 2712 break;
57779d06
VS		 2713 case DRM_FORMAT_RGB565:
2714 dspcntr |= DISPPLANE_BGRX565;
2715 break;
2716 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2717 dspcntr |= DISPPLANE_BGRX888;
2718 break;
2719 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2720 dspcntr |= DISPPLANE_RGBX888;
2721 break;
2722 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2723 dspcntr |= DISPPLANE_BGRX101010;
2724 break;
2725 case DRM_FORMAT_XBGR2101010:
57779d06 2726 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2727 break;
2728 default:
baba133a 2729 BUG();
81255565 2730 }
57779d06 2731
f45651ba
VS		 2732 if (INTEL_INFO(dev)->gen >= 4 &&
2733 obj->tiling_mode != I915_TILING_NONE)
2734 dspcntr |= DISPPLANE_TILED;
81255565 2735
de1aa629
VS		 2736 if (IS_G4X(dev))
2737 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2738
b9897127 2739 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2740
c2c75131
DV		 2741 if (INTEL_INFO(dev)->gen >= 4) {
2742 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2743 intel_gen4_compute_page_offset(dev_priv,
2744 &x, &y, obj->tiling_mode,
b9897127 2745 pixel_size,
bc752862 2746 fb->pitches[0]);
c2c75131
DV		 2747 linear_offset -= intel_crtc->dspaddr_offset;
2748 } else {
e506a0c6 2749 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2750 }
e506a0c6 2751
8e7d688b 2752 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2753 dspcntr |= DISPPLANE_ROTATE_180;
2754
6e3c9717
ACO		 2755 x += (intel_crtc->config->pipe_src_w - 1);
2756 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2757
2758 /* Finding the last pixel of the last line of the display
2759 data and adding to linear_offset*/
2760 linear_offset +=
6e3c9717
ACO		 2761 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2762 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2763 }
2764
2765 I915_WRITE(reg, dspcntr);
2766
01f2c773 2767 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2768 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2769 I915_WRITE(DSPSURF(plane),
2770 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2771 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2772 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2773 } else
f343c5f6 2774 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2775 POSTING_READ(reg);
17638cd6
JB		 2776}
2777
29b9bde6
DV		 2778static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2779 struct drm_framebuffer *fb,
2780 int x, int y)
17638cd6
JB		 2781{
2782 struct drm_device *dev = crtc->dev;
2783 struct drm_i915_private *dev_priv = dev->dev_private;
2784 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2785 struct drm_plane *primary = crtc->primary;
2786 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2787 struct drm_i915_gem_object *obj;
17638cd6 2788 int plane = intel_crtc->plane;
e506a0c6 2789 unsigned long linear_offset;
17638cd6 2790 u32 dspcntr;
f45651ba 2791 u32 reg = DSPCNTR(plane);
48404c1e 2792 int pixel_size;
f45651ba 2793
b70709a6 2794 if (!visible || !fb) {
fdd508a6
VS		 2795 I915_WRITE(reg, 0);
2796 I915_WRITE(DSPSURF(plane), 0);
2797 POSTING_READ(reg);
2798 return;
2799 }
2800
c9ba6fad
VS		 2801 obj = intel_fb_obj(fb);
2802 if (WARN_ON(obj == NULL))
2803 return;
2804
2805 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2806
f45651ba
VS		 2807 dspcntr = DISPPLANE_GAMMA_ENABLE;
2808
fdd508a6 2809 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2810
2811 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2812 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2813
57779d06
VS		 2814 switch (fb->pixel_format) {
2815 case DRM_FORMAT_C8:
17638cd6
JB		 2816 dspcntr |= DISPPLANE_8BPP;
2817 break;
57779d06
VS		 2818 case DRM_FORMAT_RGB565:
2819 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2820 break;
57779d06 2821 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2822 dspcntr |= DISPPLANE_BGRX888;
2823 break;
2824 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2825 dspcntr |= DISPPLANE_RGBX888;
2826 break;
2827 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2828 dspcntr |= DISPPLANE_BGRX101010;
2829 break;
2830 case DRM_FORMAT_XBGR2101010:
57779d06 2831 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2832 break;
2833 default:
baba133a 2834 BUG();
17638cd6
JB		 2835 }
2836
2837 if (obj->tiling_mode != I915_TILING_NONE)
2838 dspcntr |= DISPPLANE_TILED;
17638cd6 2839
f45651ba 2840 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2841 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2842
b9897127 2843 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2844 intel_crtc->dspaddr_offset =
4e9a86b6
VS		 2845 intel_gen4_compute_page_offset(dev_priv,
2846 &x, &y, obj->tiling_mode,
b9897127 2847 pixel_size,
bc752862 2848 fb->pitches[0]);
c2c75131 2849 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2850 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2851 dspcntr |= DISPPLANE_ROTATE_180;
2852
2853 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2854 x += (intel_crtc->config->pipe_src_w - 1);
2855 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2856
2857 /* Finding the last pixel of the last line of the display
2858 data and adding to linear_offset*/
2859 linear_offset +=
6e3c9717
ACO		 2860 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2861 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2862 }
2863 }
2864
2865 I915_WRITE(reg, dspcntr);
17638cd6 2866
01f2c773 2867 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2868 I915_WRITE(DSPSURF(plane),
2869 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2870 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2871 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2872 } else {
2873 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2874 I915_WRITE(DSPLINOFF(plane), linear_offset);
2875 }
17638cd6 2876 POSTING_READ(reg);
17638cd6
JB		 2877}
2878
b321803d
DL		 2879u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2880 uint32_t pixel_format)
2881{
2882 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2883
2884 /*
2885 * The stride is either expressed as a multiple of 64 bytes
2886 * chunks for linear buffers or in number of tiles for tiled
2887 * buffers.
2888 */
2889 switch (fb_modifier) {
2890 case DRM_FORMAT_MOD_NONE:
2891 return 64;
2892 case I915_FORMAT_MOD_X_TILED:
2893 if (INTEL_INFO(dev)->gen == 2)
2894 return 128;
2895 return 512;
2896 case I915_FORMAT_MOD_Y_TILED:
2897 /* No need to check for old gens and Y tiling since this is
2898 * about the display engine and those will be blocked before
2899 * we get here.
2900 */
2901 return 128;
2902 case I915_FORMAT_MOD_Yf_TILED:
2903 if (bits_per_pixel == 8)
2904 return 64;
2905 else
2906 return 128;
2907 default:
2908 MISSING_CASE(fb_modifier);
2909 return 64;
2910 }
2911}
2912
121920fa
TU		 2913unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2914 struct drm_i915_gem_object *obj)
2915{
9abc4648 2916 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2917
2918 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2919 view = &i915_ggtt_view_rotated;
121920fa
TU		 2920
2921 return i915_gem_obj_ggtt_offset_view(obj, view);
2922}
2923
e435d6e5
ML		 2924static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
2925{
2926 struct drm_device *dev = intel_crtc->base.dev;
2927 struct drm_i915_private *dev_priv = dev->dev_private;
2928
2929 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, id), 0);
2930 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, id), 0);
2931 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, id), 0);
2932 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2933 intel_crtc->base.base.id, intel_crtc->pipe, id);
2934}
2935
a1b2278e
CK		 2936/*
2937 * This function detaches (aka. unbinds) unused scalers in hardware
2938 */
0583236e 2939static void skl_detach_scalers(struct intel_crtc *intel_crtc)
a1b2278e 2940{
a1b2278e
CK		 2941 struct intel_crtc_scaler_state *scaler_state;
2942 int i;
2943
a1b2278e
CK		 2944 scaler_state = &intel_crtc->config->scaler_state;
2945
2946 /* loop through and disable scalers that aren't in use */
2947 for (i = 0; i < intel_crtc->num_scalers; i++) {
e435d6e5
ML		 2948 if (!scaler_state->scalers[i].in_use)
2949 skl_detach_scaler(intel_crtc, i);
a1b2278e
CK		 2950 }
2951}
2952
6156a456 2953u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2954{
6156a456 2955 switch (pixel_format) {
d161cf7a 2956 case DRM_FORMAT_C8:
c34ce3d1 2957 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2958 case DRM_FORMAT_RGB565:
c34ce3d1 2959 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2960 case DRM_FORMAT_XBGR8888:
c34ce3d1 2961 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2962 case DRM_FORMAT_XRGB8888:
c34ce3d1 2963 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2964 /*
2965 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2966 * to be already pre-multiplied. We need to add a knob (or a different
2967 * DRM_FORMAT) for user-space to configure that.
2968 */
f75fb42a 2969 case DRM_FORMAT_ABGR8888:
c34ce3d1 2970 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2971 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2972 case DRM_FORMAT_ARGB8888:
c34ce3d1 2973 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2974 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2975 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2976 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2977 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2978 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2979 case DRM_FORMAT_YUYV:
c34ce3d1 2980 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2981 case DRM_FORMAT_YVYU:
c34ce3d1 2982 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2983 case DRM_FORMAT_UYVY:
c34ce3d1 2984 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2985 case DRM_FORMAT_VYUY:
c34ce3d1 2986 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2987 default:
4249eeef 2988 MISSING_CASE(pixel_format);
70d21f0e 2989 }
8cfcba41 2990
c34ce3d1 2991 return 0;
6156a456 2992}
70d21f0e 2993
6156a456
CK		 2994u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2995{
6156a456 2996 switch (fb_modifier) {
30af77c4 2997 case DRM_FORMAT_MOD_NONE:
70d21f0e 2998 break;
30af77c4 2999 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 3000 return PLANE_CTL_TILED_X;
b321803d 3001 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 3002 return PLANE_CTL_TILED_Y;
b321803d 3003 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 3004 return PLANE_CTL_TILED_YF;
70d21f0e 3005 default:
6156a456 3006 MISSING_CASE(fb_modifier);
70d21f0e 3007 }
8cfcba41 3008
c34ce3d1 3009 return 0;
6156a456 3010}
70d21f0e 3011
6156a456
CK		 3012u32 skl_plane_ctl_rotation(unsigned int rotation)
3013{
3b7a5119 3014 switch (rotation) {
6156a456
CK		 3015 case BIT(DRM_ROTATE_0):
3016 break;
1e8df167
SJ		 3017 /*
3018 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3019 * while i915 HW rotation is clockwise, thats why this swapping.
3020 */
3b7a5119 3021 case BIT(DRM_ROTATE_90):
1e8df167 3022 return PLANE_CTL_ROTATE_270;
3b7a5119 3023 case BIT(DRM_ROTATE_180):
c34ce3d1 3024 return PLANE_CTL_ROTATE_180;
3b7a5119 3025 case BIT(DRM_ROTATE_270):
1e8df167 3026 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3027 default:
3028 MISSING_CASE(rotation);
3029 }
3030
c34ce3d1 3031 return 0;
6156a456
CK		 3032}
3033
3034static void skylake_update_primary_plane(struct drm_crtc *crtc,
3035 struct drm_framebuffer *fb,
3036 int x, int y)
3037{
3038 struct drm_device *dev = crtc->dev;
3039 struct drm_i915_private *dev_priv = dev->dev_private;
3040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3041 struct drm_plane *plane = crtc->primary;
3042 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3043 struct drm_i915_gem_object *obj;
3044 int pipe = intel_crtc->pipe;
3045 u32 plane_ctl, stride_div, stride;
3046 u32 tile_height, plane_offset, plane_size;
3047 unsigned int rotation;
3048 int x_offset, y_offset;
3049 unsigned long surf_addr;
6156a456
CK		 3050 struct intel_crtc_state *crtc_state = intel_crtc->config;
3051 struct intel_plane_state *plane_state;
3052 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3053 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3054 int scaler_id = -1;
3055
6156a456
CK		 3056 plane_state = to_intel_plane_state(plane->state);
3057
b70709a6 3058 if (!visible || !fb) {
6156a456
CK		 3059 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3060 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3061 POSTING_READ(PLANE_CTL(pipe, 0));
3062 return;
3b7a5119 3063 }
70d21f0e 3064
6156a456
CK		 3065 plane_ctl = PLANE_CTL_ENABLE |
3066 PLANE_CTL_PIPE_GAMMA_ENABLE |
3067 PLANE_CTL_PIPE_CSC_ENABLE;
3068
3069 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3070 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3071 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3072
3073 rotation = plane->state->rotation;
3074 plane_ctl |= skl_plane_ctl_rotation(rotation);
3075
b321803d
DL		 3076 obj = intel_fb_obj(fb);
3077 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3078 fb->pixel_format);
3b7a5119
SJ		 3079 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3080
6156a456
CK		 3081 /*
3082 * FIXME: intel_plane_state->src, dst aren't set when transitional
3083 * update_plane helpers are called from legacy paths.
3084 * Once full atomic crtc is available, below check can be avoided.
3085 */
3086 if (drm_rect_width(&plane_state->src)) {
3087 scaler_id = plane_state->scaler_id;
3088 src_x = plane_state->src.x1 >> 16;
3089 src_y = plane_state->src.y1 >> 16;
3090 src_w = drm_rect_width(&plane_state->src) >> 16;
3091 src_h = drm_rect_height(&plane_state->src) >> 16;
3092 dst_x = plane_state->dst.x1;
3093 dst_y = plane_state->dst.y1;
3094 dst_w = drm_rect_width(&plane_state->dst);
3095 dst_h = drm_rect_height(&plane_state->dst);
3096
3097 WARN_ON(x != src_x || y != src_y);
3098 } else {
3099 src_w = intel_crtc->config->pipe_src_w;
3100 src_h = intel_crtc->config->pipe_src_h;
3101 }
3102
3b7a5119
SJ		 3103 if (intel_rotation_90_or_270(rotation)) {
3104 /* stride = Surface height in tiles */
2614f17d 3105 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3106 fb->modifier[0]);
3107 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3108 x_offset = stride * tile_height - y - src_h;
3b7a5119 3109 y_offset = x;
6156a456 3110 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3111 } else {
3112 stride = fb->pitches[0] / stride_div;
3113 x_offset = x;
3114 y_offset = y;
6156a456 3115 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3116 }
3117 plane_offset = y_offset << 16 | x_offset;
b321803d 3118
70d21f0e 3119 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3120 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3121 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3122 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3123
3124 if (scaler_id >= 0) {
3125 uint32_t ps_ctrl = 0;
3126
3127 WARN_ON(!dst_w || !dst_h);
3128 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3129 crtc_state->scaler_state.scalers[scaler_id].mode;
3130 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3131 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3132 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3133 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3134 I915_WRITE(PLANE_POS(pipe, 0), 0);
3135 } else {
3136 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3137 }
3138
121920fa 3139 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3140
3141 POSTING_READ(PLANE_SURF(pipe, 0));
3142}
3143
17638cd6
JB		 3144/* Assume fb object is pinned & idle & fenced and just update base pointers */
3145static int
3146intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3147 int x, int y, enum mode_set_atomic state)
3148{
3149 struct drm_device *dev = crtc->dev;
3150 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3151
ff2a3117 3152 if (dev_priv->fbc.disable_fbc)
7733b49b 3153 dev_priv->fbc.disable_fbc(dev_priv);
81255565 3154
29b9bde6
DV		 3155 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3156
3157 return 0;
81255565
JB		 3158}
3159
7514747d 3160static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3161{
96a02917
VS		 3162 struct drm_crtc *crtc;
3163
70e1e0ec 3164 for_each_crtc(dev, crtc) {
96a02917
VS		 3165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3166 enum plane plane = intel_crtc->plane;
3167
3168 intel_prepare_page_flip(dev, plane);
3169 intel_finish_page_flip_plane(dev, plane);
3170 }
7514747d
VS		 3171}
3172
3173static void intel_update_primary_planes(struct drm_device *dev)
3174{
3175 struct drm_i915_private *dev_priv = dev->dev_private;
3176 struct drm_crtc *crtc;
96a02917 3177
70e1e0ec 3178 for_each_crtc(dev, crtc) {
96a02917
VS		 3179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3180
51fd371b 3181 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3182 /*
3183 * FIXME: Once we have proper support for primary planes (and
3184 * disabling them without disabling the entire crtc) allow again
66e514c1 3185 * a NULL crtc->primary->fb.
947fdaad 3186 */
f4510a27 3187 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3188 dev_priv->display.update_primary_plane(crtc,
66e514c1 3189 crtc->primary->fb,
262ca2b0
MR		 3190 crtc->x,
3191 crtc->y);
51fd371b 3192 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3193 }
3194}
3195
7514747d
VS		 3196void intel_prepare_reset(struct drm_device *dev)
3197{
3198 /* no reset support for gen2 */
3199 if (IS_GEN2(dev))
3200 return;
3201
3202 /* reset doesn't touch the display */
3203 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3204 return;
3205
3206 drm_modeset_lock_all(dev);
f98ce92f
VS		 3207 /*
3208 * Disabling the crtcs gracefully seems nicer. Also the
3209 * g33 docs say we should at least disable all the planes.
3210 */
6b72d486 3211 intel_display_suspend(dev);
7514747d
VS		 3212}
3213
3214void intel_finish_reset(struct drm_device *dev)
3215{
3216 struct drm_i915_private *dev_priv = to_i915(dev);
3217
3218 /*
3219 * Flips in the rings will be nuked by the reset,
3220 * so complete all pending flips so that user space
3221 * will get its events and not get stuck.
3222 */
3223 intel_complete_page_flips(dev);
3224
3225 /* no reset support for gen2 */
3226 if (IS_GEN2(dev))
3227 return;
3228
3229 /* reset doesn't touch the display */
3230 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3231 /*
3232 * Flips in the rings have been nuked by the reset,
3233 * so update the base address of all primary
3234 * planes to the the last fb to make sure we're
3235 * showing the correct fb after a reset.
3236 */
3237 intel_update_primary_planes(dev);
3238 return;
3239 }
3240
3241 /*
3242 * The display has been reset as well,
3243 * so need a full re-initialization.
3244 */
3245 intel_runtime_pm_disable_interrupts(dev_priv);
3246 intel_runtime_pm_enable_interrupts(dev_priv);
3247
3248 intel_modeset_init_hw(dev);
3249
3250 spin_lock_irq(&dev_priv->irq_lock);
3251 if (dev_priv->display.hpd_irq_setup)
3252 dev_priv->display.hpd_irq_setup(dev);
3253 spin_unlock_irq(&dev_priv->irq_lock);
3254
043e9bda 3255 intel_display_resume(dev);
7514747d
VS		 3256
3257 intel_hpd_init(dev_priv);
3258
3259 drm_modeset_unlock_all(dev);
3260}
3261
2e2f351d 3262static void
14667a4b
CW		 3263intel_finish_fb(struct drm_framebuffer *old_fb)
3264{
2ff8fde1 3265 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3266 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3267 bool was_interruptible = dev_priv->mm.interruptible;
3268 int ret;
3269
14667a4b
CW		 3270 /* Big Hammer, we also need to ensure that any pending
3271 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3272 * current scanout is retired before unpinning the old
2e2f351d
CW		 3273 * framebuffer. Note that we rely on userspace rendering
3274 * into the buffer attached to the pipe they are waiting
3275 * on. If not, userspace generates a GPU hang with IPEHR
3276 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3277 *
3278 * This should only fail upon a hung GPU, in which case we
3279 * can safely continue.
3280 */
3281 dev_priv->mm.interruptible = false;
2e2f351d 3282 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3283 dev_priv->mm.interruptible = was_interruptible;
3284
2e2f351d 3285 WARN_ON(ret);
14667a4b
CW		 3286}
3287
7d5e3799
CW		 3288static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3289{
3290 struct drm_device *dev = crtc->dev;
3291 struct drm_i915_private *dev_priv = dev->dev_private;
3292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3293 bool pending;
3294
3295 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3296 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3297 return false;
3298
5e2d7afc 3299 spin_lock_irq(&dev->event_lock);
7d5e3799 3300 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3301 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3302
3303 return pending;
3304}
3305
e30e8f75
GP		 3306static void intel_update_pipe_size(struct intel_crtc *crtc)
3307{
3308 struct drm_device *dev = crtc->base.dev;
3309 struct drm_i915_private *dev_priv = dev->dev_private;
3310 const struct drm_display_mode *adjusted_mode;
3311
3312 if (!i915.fastboot)
3313 return;
3314
3315 /*
3316 * Update pipe size and adjust fitter if needed: the reason for this is
3317 * that in compute_mode_changes we check the native mode (not the pfit
3318 * mode) to see if we can flip rather than do a full mode set. In the
3319 * fastboot case, we'll flip, but if we don't update the pipesrc and
3320 * pfit state, we'll end up with a big fb scanned out into the wrong
3321 * sized surface.
3322 *
3323 * To fix this properly, we need to hoist the checks up into
3324 * compute_mode_changes (or above), check the actual pfit state and
3325 * whether the platform allows pfit disable with pipe active, and only
3326 * then update the pipesrc and pfit state, even on the flip path.
3327 */
3328
6e3c9717 3329 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3330
3331 I915_WRITE(PIPESRC(crtc->pipe),
3332 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3333 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3334 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3335 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3336 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3337 I915_WRITE(PF_CTL(crtc->pipe), 0);
3338 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3339 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3340 }
6e3c9717
ACO		 3341 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3342 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3343}
3344
5e84e1a4
ZW		 3345static void intel_fdi_normal_train(struct drm_crtc *crtc)
3346{
3347 struct drm_device *dev = crtc->dev;
3348 struct drm_i915_private *dev_priv = dev->dev_private;
3349 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3350 int pipe = intel_crtc->pipe;
3351 u32 reg, temp;
3352
3353 /* enable normal train */
3354 reg = FDI_TX_CTL(pipe);
3355 temp = I915_READ(reg);
61e499bf 3356 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3357 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3358 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3359 } else {
3360 temp &= ~FDI_LINK_TRAIN_NONE;
3361 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3362 }
5e84e1a4
ZW		 3363 I915_WRITE(reg, temp);
3364
3365 reg = FDI_RX_CTL(pipe);
3366 temp = I915_READ(reg);
3367 if (HAS_PCH_CPT(dev)) {
3368 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3369 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3370 } else {
3371 temp &= ~FDI_LINK_TRAIN_NONE;
3372 temp |= FDI_LINK_TRAIN_NONE;
3373 }
3374 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3375
3376 /* wait one idle pattern time */
3377 POSTING_READ(reg);
3378 udelay(1000);
357555c0
JB		 3379
3380 /* IVB wants error correction enabled */
3381 if (IS_IVYBRIDGE(dev))
3382 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3383 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3384}
3385
8db9d77b
ZW		 3386/* The FDI link training functions for ILK/Ibexpeak. */
3387static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3388{
3389 struct drm_device *dev = crtc->dev;
3390 struct drm_i915_private *dev_priv = dev->dev_private;
3391 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3392 int pipe = intel_crtc->pipe;
5eddb70b 3393 u32 reg, temp, tries;
8db9d77b 3394
1c8562f6 3395 /* FDI needs bits from pipe first */
0fc932b8 3396 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3397
e1a44743
AJ		 3398 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3399 for train result */
5eddb70b
CW		 3400 reg = FDI_RX_IMR(pipe);
3401 temp = I915_READ(reg);
e1a44743
AJ		 3402 temp &= ~FDI_RX_SYMBOL_LOCK;
3403 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3404 I915_WRITE(reg, temp);
3405 I915_READ(reg);
e1a44743
AJ		 3406 udelay(150);
3407
8db9d77b 3408 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3409 reg = FDI_TX_CTL(pipe);
3410 temp = I915_READ(reg);
627eb5a3 3411 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3412 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3413 temp &= ~FDI_LINK_TRAIN_NONE;
3414 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3415 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3416
5eddb70b
CW		 3417 reg = FDI_RX_CTL(pipe);
3418 temp = I915_READ(reg);
8db9d77b
ZW		 3419 temp &= ~FDI_LINK_TRAIN_NONE;
3420 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3421 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3422
3423 POSTING_READ(reg);
8db9d77b
ZW		 3424 udelay(150);
3425
5b2adf89 3426 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3427 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3428 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3429 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3430
5eddb70b 3431 reg = FDI_RX_IIR(pipe);
e1a44743 3432 for (tries = 0; tries < 5; tries++) {
5eddb70b 3433 temp = I915_READ(reg);
8db9d77b
ZW		 3434 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3435
3436 if ((temp & FDI_RX_BIT_LOCK)) {
3437 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3438 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3439 break;
3440 }
8db9d77b 3441 }
e1a44743 3442 if (tries == 5)
5eddb70b 3443 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3444
3445 /* Train 2 */
5eddb70b
CW		 3446 reg = FDI_TX_CTL(pipe);
3447 temp = I915_READ(reg);
8db9d77b
ZW		 3448 temp &= ~FDI_LINK_TRAIN_NONE;
3449 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3450 I915_WRITE(reg, temp);
8db9d77b 3451
5eddb70b
CW		 3452 reg = FDI_RX_CTL(pipe);
3453 temp = I915_READ(reg);
8db9d77b
ZW		 3454 temp &= ~FDI_LINK_TRAIN_NONE;
3455 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3456 I915_WRITE(reg, temp);
8db9d77b 3457
5eddb70b
CW		 3458 POSTING_READ(reg);
3459 udelay(150);
8db9d77b 3460
5eddb70b 3461 reg = FDI_RX_IIR(pipe);
e1a44743 3462 for (tries = 0; tries < 5; tries++) {
5eddb70b 3463 temp = I915_READ(reg);
8db9d77b
ZW		 3464 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3465
3466 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3467 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3468 DRM_DEBUG_KMS("FDI train 2 done.\n");
3469 break;
3470 }
8db9d77b 3471 }
e1a44743 3472 if (tries == 5)
5eddb70b 3473 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3474
3475 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3476
8db9d77b
ZW		 3477}
3478
0206e353 3479static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3480 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3481 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3482 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3483 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3484};
3485
3486/* The FDI link training functions for SNB/Cougarpoint. */
3487static void gen6_fdi_link_train(struct drm_crtc *crtc)
3488{
3489 struct drm_device *dev = crtc->dev;
3490 struct drm_i915_private *dev_priv = dev->dev_private;
3491 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3492 int pipe = intel_crtc->pipe;
fa37d39e 3493 u32 reg, temp, i, retry;
8db9d77b 3494
e1a44743
AJ		 3495 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3496 for train result */
5eddb70b
CW		 3497 reg = FDI_RX_IMR(pipe);
3498 temp = I915_READ(reg);
e1a44743
AJ		 3499 temp &= ~FDI_RX_SYMBOL_LOCK;
3500 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3501 I915_WRITE(reg, temp);
3502
3503 POSTING_READ(reg);
e1a44743
AJ		 3504 udelay(150);
3505
8db9d77b 3506 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3507 reg = FDI_TX_CTL(pipe);
3508 temp = I915_READ(reg);
627eb5a3 3509 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3510 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3511 temp &= ~FDI_LINK_TRAIN_NONE;
3512 temp |= FDI_LINK_TRAIN_PATTERN_1;
3513 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3514 /* SNB-B */
3515 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3516 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3517
d74cf324
DV		 3518 I915_WRITE(FDI_RX_MISC(pipe),
3519 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3520
5eddb70b
CW		 3521 reg = FDI_RX_CTL(pipe);
3522 temp = I915_READ(reg);
8db9d77b
ZW		 3523 if (HAS_PCH_CPT(dev)) {
3524 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3525 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3526 } else {
3527 temp &= ~FDI_LINK_TRAIN_NONE;
3528 temp |= FDI_LINK_TRAIN_PATTERN_1;
3529 }
5eddb70b
CW		 3530 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3531
3532 POSTING_READ(reg);
8db9d77b
ZW		 3533 udelay(150);
3534
0206e353 3535 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3536 reg = FDI_TX_CTL(pipe);
3537 temp = I915_READ(reg);
8db9d77b
ZW		 3538 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3539 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3540 I915_WRITE(reg, temp);
3541
3542 POSTING_READ(reg);
8db9d77b
ZW		 3543 udelay(500);
3544
fa37d39e
SP		 3545 for (retry = 0; retry < 5; retry++) {
3546 reg = FDI_RX_IIR(pipe);
3547 temp = I915_READ(reg);
3548 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3549 if (temp & FDI_RX_BIT_LOCK) {
3550 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3551 DRM_DEBUG_KMS("FDI train 1 done.\n");
3552 break;
3553 }
3554 udelay(50);
8db9d77b 3555 }
fa37d39e
SP		 3556 if (retry < 5)
3557 break;
8db9d77b
ZW		 3558 }
3559 if (i == 4)
5eddb70b 3560 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3561
3562 /* Train 2 */
5eddb70b
CW		 3563 reg = FDI_TX_CTL(pipe);
3564 temp = I915_READ(reg);
8db9d77b
ZW		 3565 temp &= ~FDI_LINK_TRAIN_NONE;
3566 temp |= FDI_LINK_TRAIN_PATTERN_2;
3567 if (IS_GEN6(dev)) {
3568 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3569 /* SNB-B */
3570 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3571 }
5eddb70b 3572 I915_WRITE(reg, temp);
8db9d77b 3573
5eddb70b
CW		 3574 reg = FDI_RX_CTL(pipe);
3575 temp = I915_READ(reg);
8db9d77b
ZW		 3576 if (HAS_PCH_CPT(dev)) {
3577 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3578 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3579 } else {
3580 temp &= ~FDI_LINK_TRAIN_NONE;
3581 temp |= FDI_LINK_TRAIN_PATTERN_2;
3582 }
5eddb70b
CW		 3583 I915_WRITE(reg, temp);
3584
3585 POSTING_READ(reg);
8db9d77b
ZW		 3586 udelay(150);
3587
0206e353 3588 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3589 reg = FDI_TX_CTL(pipe);
3590 temp = I915_READ(reg);
8db9d77b
ZW		 3591 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3592 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3593 I915_WRITE(reg, temp);
3594
3595 POSTING_READ(reg);
8db9d77b
ZW		 3596 udelay(500);
3597
fa37d39e
SP		 3598 for (retry = 0; retry < 5; retry++) {
3599 reg = FDI_RX_IIR(pipe);
3600 temp = I915_READ(reg);
3601 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3602 if (temp & FDI_RX_SYMBOL_LOCK) {
3603 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3604 DRM_DEBUG_KMS("FDI train 2 done.\n");
3605 break;
3606 }
3607 udelay(50);
8db9d77b 3608 }
fa37d39e
SP		 3609 if (retry < 5)
3610 break;
8db9d77b
ZW		 3611 }
3612 if (i == 4)
5eddb70b 3613 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3614
3615 DRM_DEBUG_KMS("FDI train done.\n");
3616}
3617
357555c0
JB		 3618/* Manual link training for Ivy Bridge A0 parts */
3619static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3620{
3621 struct drm_device *dev = crtc->dev;
3622 struct drm_i915_private *dev_priv = dev->dev_private;
3623 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3624 int pipe = intel_crtc->pipe;
139ccd3f 3625 u32 reg, temp, i, j;
357555c0
JB		 3626
3627 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3628 for train result */
3629 reg = FDI_RX_IMR(pipe);
3630 temp = I915_READ(reg);
3631 temp &= ~FDI_RX_SYMBOL_LOCK;
3632 temp &= ~FDI_RX_BIT_LOCK;
3633 I915_WRITE(reg, temp);
3634
3635 POSTING_READ(reg);
3636 udelay(150);
3637
01a415fd
DV		 3638 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3639 I915_READ(FDI_RX_IIR(pipe)));
3640
139ccd3f
JB		 3641 /* Try each vswing and preemphasis setting twice before moving on */
3642 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3643 /* disable first in case we need to retry */
3644 reg = FDI_TX_CTL(pipe);
3645 temp = I915_READ(reg);
3646 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3647 temp &= ~FDI_TX_ENABLE;
3648 I915_WRITE(reg, temp);
357555c0 3649
139ccd3f
JB		 3650 reg = FDI_RX_CTL(pipe);
3651 temp = I915_READ(reg);
3652 temp &= ~FDI_LINK_TRAIN_AUTO;
3653 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3654 temp &= ~FDI_RX_ENABLE;
3655 I915_WRITE(reg, temp);
357555c0 3656
139ccd3f 3657 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3658 reg = FDI_TX_CTL(pipe);
3659 temp = I915_READ(reg);
139ccd3f 3660 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3661 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3662 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3663 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3664 temp |= snb_b_fdi_train_param[j/2];
3665 temp |= FDI_COMPOSITE_SYNC;
3666 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3667
139ccd3f
JB		 3668 I915_WRITE(FDI_RX_MISC(pipe),
3669 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3670
139ccd3f 3671 reg = FDI_RX_CTL(pipe);
357555c0 3672 temp = I915_READ(reg);
139ccd3f
JB		 3673 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3674 temp |= FDI_COMPOSITE_SYNC;
3675 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3676
139ccd3f
JB		 3677 POSTING_READ(reg);
3678 udelay(1); /* should be 0.5us */
357555c0 3679
139ccd3f
JB		 3680 for (i = 0; i < 4; i++) {
3681 reg = FDI_RX_IIR(pipe);
3682 temp = I915_READ(reg);
3683 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3684
139ccd3f
JB		 3685 if (temp & FDI_RX_BIT_LOCK ||
3686 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3687 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3688 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3689 i);
3690 break;
3691 }
3692 udelay(1); /* should be 0.5us */
3693 }
3694 if (i == 4) {
3695 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3696 continue;
3697 }
357555c0 3698
139ccd3f 3699 /* Train 2 */
357555c0
JB		 3700 reg = FDI_TX_CTL(pipe);
3701 temp = I915_READ(reg);
139ccd3f
JB		 3702 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3703 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3704 I915_WRITE(reg, temp);
3705
3706 reg = FDI_RX_CTL(pipe);
3707 temp = I915_READ(reg);
3708 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3709 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3710 I915_WRITE(reg, temp);
3711
3712 POSTING_READ(reg);
139ccd3f 3713 udelay(2); /* should be 1.5us */
357555c0 3714
139ccd3f
JB		 3715 for (i = 0; i < 4; i++) {
3716 reg = FDI_RX_IIR(pipe);
3717 temp = I915_READ(reg);
3718 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3719
139ccd3f
JB		 3720 if (temp & FDI_RX_SYMBOL_LOCK ||
3721 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3722 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3723 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3724 i);
3725 goto train_done;
3726 }
3727 udelay(2); /* should be 1.5us */
357555c0 3728 }
139ccd3f
JB		 3729 if (i == 4)
3730 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3731 }
357555c0 3732
139ccd3f 3733train_done:
357555c0
JB		 3734 DRM_DEBUG_KMS("FDI train done.\n");
3735}
3736
88cefb6c 3737static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3738{
88cefb6c 3739 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3740 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3741 int pipe = intel_crtc->pipe;
5eddb70b 3742 u32 reg, temp;
79e53945 3743
c64e311e 3744
c98e9dcf 3745 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3746 reg = FDI_RX_CTL(pipe);
3747 temp = I915_READ(reg);
627eb5a3 3748 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3749 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3750 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3751 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3752
3753 POSTING_READ(reg);
c98e9dcf
JB		 3754 udelay(200);
3755
3756 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3757 temp = I915_READ(reg);
3758 I915_WRITE(reg, temp | FDI_PCDCLK);
3759
3760 POSTING_READ(reg);
c98e9dcf
JB		 3761 udelay(200);
3762
20749730
PZ		 3763 /* Enable CPU FDI TX PLL, always on for Ironlake */
3764 reg = FDI_TX_CTL(pipe);
3765 temp = I915_READ(reg);
3766 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3767 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3768
20749730
PZ		 3769 POSTING_READ(reg);
3770 udelay(100);
6be4a607 3771 }
0e23b99d
JB		 3772}
3773
88cefb6c
DV		 3774static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3775{
3776 struct drm_device *dev = intel_crtc->base.dev;
3777 struct drm_i915_private *dev_priv = dev->dev_private;
3778 int pipe = intel_crtc->pipe;
3779 u32 reg, temp;
3780
3781 /* Switch from PCDclk to Rawclk */
3782 reg = FDI_RX_CTL(pipe);
3783 temp = I915_READ(reg);
3784 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3785
3786 /* Disable CPU FDI TX PLL */
3787 reg = FDI_TX_CTL(pipe);
3788 temp = I915_READ(reg);
3789 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3790
3791 POSTING_READ(reg);
3792 udelay(100);
3793
3794 reg = FDI_RX_CTL(pipe);
3795 temp = I915_READ(reg);
3796 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3797
3798 /* Wait for the clocks to turn off. */
3799 POSTING_READ(reg);
3800 udelay(100);
3801}
3802
0fc932b8
JB		 3803static void ironlake_fdi_disable(struct drm_crtc *crtc)
3804{
3805 struct drm_device *dev = crtc->dev;
3806 struct drm_i915_private *dev_priv = dev->dev_private;
3807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3808 int pipe = intel_crtc->pipe;
3809 u32 reg, temp;
3810
3811 /* disable CPU FDI tx and PCH FDI rx */
3812 reg = FDI_TX_CTL(pipe);
3813 temp = I915_READ(reg);
3814 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3815 POSTING_READ(reg);
3816
3817 reg = FDI_RX_CTL(pipe);
3818 temp = I915_READ(reg);
3819 temp &= ~(0x7 << 16);
dfd07d72 3820 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3821 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3822
3823 POSTING_READ(reg);
3824 udelay(100);
3825
3826 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3827 if (HAS_PCH_IBX(dev))
6f06ce18 3828 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3829
3830 /* still set train pattern 1 */
3831 reg = FDI_TX_CTL(pipe);
3832 temp = I915_READ(reg);
3833 temp &= ~FDI_LINK_TRAIN_NONE;
3834 temp |= FDI_LINK_TRAIN_PATTERN_1;
3835 I915_WRITE(reg, temp);
3836
3837 reg = FDI_RX_CTL(pipe);
3838 temp = I915_READ(reg);
3839 if (HAS_PCH_CPT(dev)) {
3840 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3841 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3842 } else {
3843 temp &= ~FDI_LINK_TRAIN_NONE;
3844 temp |= FDI_LINK_TRAIN_PATTERN_1;
3845 }
3846 /* BPC in FDI rx is consistent with that in PIPECONF */
3847 temp &= ~(0x07 << 16);
dfd07d72 3848 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3849 I915_WRITE(reg, temp);
3850
3851 POSTING_READ(reg);
3852 udelay(100);
3853}
3854
5dce5b93
CW		 3855bool intel_has_pending_fb_unpin(struct drm_device *dev)
3856{
3857 struct intel_crtc *crtc;
3858
3859 /* Note that we don't need to be called with mode_config.lock here
3860 * as our list of CRTC objects is static for the lifetime of the
3861 * device and so cannot disappear as we iterate. Similarly, we can
3862 * happily treat the predicates as racy, atomic checks as userspace
3863 * cannot claim and pin a new fb without at least acquring the
3864 * struct_mutex and so serialising with us.
3865 */
d3fcc808 3866 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3867 if (atomic_read(&crtc->unpin_work_count) == 0)
3868 continue;
3869
3870 if (crtc->unpin_work)
3871 intel_wait_for_vblank(dev, crtc->pipe);
3872
3873 return true;
3874 }
3875
3876 return false;
3877}
3878
d6bbafa1
CW		 3879static void page_flip_completed(struct intel_crtc *intel_crtc)
3880{
3881 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3882 struct intel_unpin_work *work = intel_crtc->unpin_work;
3883
3884 /* ensure that the unpin work is consistent wrt ->pending. */
3885 smp_rmb();
3886 intel_crtc->unpin_work = NULL;
3887
3888 if (work->event)
3889 drm_send_vblank_event(intel_crtc->base.dev,
3890 intel_crtc->pipe,
3891 work->event);
3892
3893 drm_crtc_vblank_put(&intel_crtc->base);
3894
3895 wake_up_all(&dev_priv->pending_flip_queue);
3896 queue_work(dev_priv->wq, &work->work);
3897
3898 trace_i915_flip_complete(intel_crtc->plane,
3899 work->pending_flip_obj);
3900}
3901
46a55d30 3902void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3903{
0f91128d 3904 struct drm_device *dev = crtc->dev;
5bb61643 3905 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3906
2c10d571 3907 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3908 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3909 !intel_crtc_has_pending_flip(crtc),
3910 60*HZ) == 0)) {
3911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3912
5e2d7afc 3913 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3914 if (intel_crtc->unpin_work) {
3915 WARN_ONCE(1, "Removing stuck page flip\n");
3916 page_flip_completed(intel_crtc);
3917 }
5e2d7afc 3918 spin_unlock_irq(&dev->event_lock);
9c787942 3919 }
5bb61643 3920
975d568a
CW		 3921 if (crtc->primary->fb) {
3922 mutex_lock(&dev->struct_mutex);
3923 intel_finish_fb(crtc->primary->fb);
3924 mutex_unlock(&dev->struct_mutex);
3925 }
e6c3a2a6
CW		 3926}
3927
e615efe4
ED		 3928/* Program iCLKIP clock to the desired frequency */
3929static void lpt_program_iclkip(struct drm_crtc *crtc)
3930{
3931 struct drm_device *dev = crtc->dev;
3932 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3933 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3934 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3935 u32 temp;
3936
a580516d 3937 mutex_lock(&dev_priv->sb_lock);
09153000 3938
e615efe4
ED		 3939 /* It is necessary to ungate the pixclk gate prior to programming
3940 * the divisors, and gate it back when it is done.
3941 */
3942 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3943
3944 /* Disable SSCCTL */
3945 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3946 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3947 SBI_SSCCTL_DISABLE,
3948 SBI_ICLK);
e615efe4
ED		 3949
3950 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3951 if (clock == 20000) {
e615efe4
ED		 3952 auxdiv = 1;
3953 divsel = 0x41;
3954 phaseinc = 0x20;
3955 } else {
3956 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3957 * but the adjusted_mode->crtc_clock in in KHz. To get the
3958 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3959 * convert the virtual clock precision to KHz here for higher
3960 * precision.
3961 */
3962 u32 iclk_virtual_root_freq = 172800 * 1000;
3963 u32 iclk_pi_range = 64;
3964 u32 desired_divisor, msb_divisor_value, pi_value;
3965
12d7ceed 3966 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3967 msb_divisor_value = desired_divisor / iclk_pi_range;
3968 pi_value = desired_divisor % iclk_pi_range;
3969
3970 auxdiv = 0;
3971 divsel = msb_divisor_value - 2;
3972 phaseinc = pi_value;
3973 }
3974
3975 /* This should not happen with any sane values */
3976 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3977 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3978 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3979 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3980
3981 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3982 clock,
e615efe4
ED		 3983 auxdiv,
3984 divsel,
3985 phasedir,
3986 phaseinc);
3987
3988 /* Program SSCDIVINTPHASE6 */
988d6ee8 3989 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3990 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3991 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3992 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3993 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3994 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3995 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3996 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3997
3998 /* Program SSCAUXDIV */
988d6ee8 3999 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 4000 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4001 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 4002 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 4003
4004 /* Enable modulator and associated divider */
988d6ee8 4005 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4006 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4007 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4008
4009 /* Wait for initialization time */
4010 udelay(24);
4011
4012 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000 4013
a580516d 4014 mutex_unlock(&dev_priv->sb_lock);
e615efe4
ED		 4015}
4016
275f01b2
DV		 4017static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4018 enum pipe pch_transcoder)
4019{
4020 struct drm_device *dev = crtc->base.dev;
4021 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4022 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4023
4024 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4025 I915_READ(HTOTAL(cpu_transcoder)));
4026 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4027 I915_READ(HBLANK(cpu_transcoder)));
4028 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4029 I915_READ(HSYNC(cpu_transcoder)));
4030
4031 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4032 I915_READ(VTOTAL(cpu_transcoder)));
4033 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4034 I915_READ(VBLANK(cpu_transcoder)));
4035 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4036 I915_READ(VSYNC(cpu_transcoder)));
4037 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4038 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4039}
4040
003632d9 4041static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4042{
4043 struct drm_i915_private *dev_priv = dev->dev_private;
4044 uint32_t temp;
4045
4046 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4047 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4048 return;
4049
4050 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4051 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4052
003632d9
ACO		 4053 temp &= ~FDI_BC_BIFURCATION_SELECT;
4054 if (enable)
4055 temp |= FDI_BC_BIFURCATION_SELECT;
4056
4057 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4058 I915_WRITE(SOUTH_CHICKEN1, temp);
4059 POSTING_READ(SOUTH_CHICKEN1);
4060}
4061
4062static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4063{
4064 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4065
4066 switch (intel_crtc->pipe) {
4067 case PIPE_A:
4068 break;
4069 case PIPE_B:
6e3c9717 4070 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4071 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4072 else
003632d9 4073 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4074
4075 break;
4076 case PIPE_C:
003632d9 4077 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4078
4079 break;
4080 default:
4081 BUG();
4082 }
4083}
4084
f67a559d
JB		 4085/*
4086 * Enable PCH resources required for PCH ports:
4087 * - PCH PLLs
4088 * - FDI training & RX/TX
4089 * - update transcoder timings
4090 * - DP transcoding bits
4091 * - transcoder
4092 */
4093static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4094{
4095 struct drm_device *dev = crtc->dev;
4096 struct drm_i915_private *dev_priv = dev->dev_private;
4097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4098 int pipe = intel_crtc->pipe;
ee7b9f93 4099 u32 reg, temp;
2c07245f 4100
ab9412ba 4101 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4102
1fbc0d78
DV		 4103 if (IS_IVYBRIDGE(dev))
4104 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4105
cd986abb
DV		 4106 /* Write the TU size bits before fdi link training, so that error
4107 * detection works. */
4108 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4109 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4110
c98e9dcf 4111 /* For PCH output, training FDI link */
674cf967 4112 dev_priv->display.fdi_link_train(crtc);
2c07245f 4113
3ad8a208
DV		 4114 /* We need to program the right clock selection before writing the pixel
4115 * mutliplier into the DPLL. */
303b81e0 4116 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4117 u32 sel;
4b645f14 4118
c98e9dcf 4119 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4120 temp |= TRANS_DPLL_ENABLE(pipe);
4121 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4122 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4123 temp |= sel;
4124 else
4125 temp &= ~sel;
c98e9dcf 4126 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4127 }
5eddb70b 4128
3ad8a208
DV		 4129 /* XXX: pch pll's can be enabled any time before we enable the PCH
4130 * transcoder, and we actually should do this to not upset any PCH
4131 * transcoder that already use the clock when we share it.
4132 *
4133 * Note that enable_shared_dpll tries to do the right thing, but
4134 * get_shared_dpll unconditionally resets the pll - we need that to have
4135 * the right LVDS enable sequence. */
85b3894f 4136 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4137
d9b6cb56
JB		 4138 /* set transcoder timing, panel must allow it */
4139 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4140 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4141
303b81e0 4142 intel_fdi_normal_train(crtc);
5e84e1a4 4143
c98e9dcf 4144 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4145 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4146 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4147 reg = TRANS_DP_CTL(pipe);
4148 temp = I915_READ(reg);
4149 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4150 TRANS_DP_SYNC_MASK |
4151 TRANS_DP_BPC_MASK);
e3ef4479 4152 temp |= TRANS_DP_OUTPUT_ENABLE;
9325c9f0 4153 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4154
4155 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4156 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4157 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4158 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4159
4160 switch (intel_trans_dp_port_sel(crtc)) {
4161 case PCH_DP_B:
5eddb70b 4162 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4163 break;
4164 case PCH_DP_C:
5eddb70b 4165 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4166 break;
4167 case PCH_DP_D:
5eddb70b 4168 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4169 break;
4170 default:
e95d41e1 4171 BUG();
32f9d658 4172 }
2c07245f 4173
5eddb70b 4174 I915_WRITE(reg, temp);
6be4a607 4175 }
b52eb4dc 4176
b8a4f404 4177 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4178}
4179
1507e5bd
PZ		 4180static void lpt_pch_enable(struct drm_crtc *crtc)
4181{
4182 struct drm_device *dev = crtc->dev;
4183 struct drm_i915_private *dev_priv = dev->dev_private;
4184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4185 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4186
ab9412ba 4187 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4188
8c52b5e8 4189 lpt_program_iclkip(crtc);
1507e5bd 4190
0540e488 4191 /* Set transcoder timing. */
275f01b2 4192 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4193
937bb610 4194 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4195}
4196
190f68c5
ACO		 4197struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4198 struct intel_crtc_state *crtc_state)
ee7b9f93 4199{
e2b78267 4200 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4201 struct intel_shared_dpll *pll;
de419ab6 4202 struct intel_shared_dpll_config *shared_dpll;
e2b78267 4203 enum intel_dpll_id i;
ee7b9f93 4204
de419ab6
ML		 4205 shared_dpll = intel_atomic_get_shared_dpll_state(crtc_state->base.state);
4206
98b6bd99
DV		 4207 if (HAS_PCH_IBX(dev_priv->dev)) {
4208 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4209 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4210 pll = &dev_priv->shared_dplls[i];
98b6bd99 4211
46edb027
DV		 4212 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4213 crtc->base.base.id, pll->name);
98b6bd99 4214
de419ab6 4215 WARN_ON(shared_dpll[i].crtc_mask);
f2a69f44 4216
98b6bd99
DV		 4217 goto found;
4218 }
4219
bcddf610
S		 4220 if (IS_BROXTON(dev_priv->dev)) {
4221 /* PLL is attached to port in bxt */
4222 struct intel_encoder *encoder;
4223 struct intel_digital_port *intel_dig_port;
4224
4225 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4226 if (WARN_ON(!encoder))
4227 return NULL;
4228
4229 intel_dig_port = enc_to_dig_port(&encoder->base);
4230 /* 1:1 mapping between ports and PLLs */
4231 i = (enum intel_dpll_id)intel_dig_port->port;
4232 pll = &dev_priv->shared_dplls[i];
4233 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4234 crtc->base.base.id, pll->name);
de419ab6 4235 WARN_ON(shared_dpll[i].crtc_mask);
bcddf610
S		 4236
4237 goto found;
4238 }
4239
e72f9fbf
DV		 4240 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4241 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4242
4243 /* Only want to check enabled timings first */
de419ab6 4244 if (shared_dpll[i].crtc_mask == 0)
ee7b9f93
JB		 4245 continue;
4246
190f68c5 4247 if (memcmp(&crtc_state->dpll_hw_state,
de419ab6
ML		 4248 &shared_dpll[i].hw_state,
4249 sizeof(crtc_state->dpll_hw_state)) == 0) {
8bd31e67 4250 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4251 crtc->base.base.id, pll->name,
de419ab6 4252 shared_dpll[i].crtc_mask,
8bd31e67 4253 pll->active);
ee7b9f93
JB		 4254 goto found;
4255 }
4256 }
4257
4258 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4259 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4260 pll = &dev_priv->shared_dplls[i];
de419ab6 4261 if (shared_dpll[i].crtc_mask == 0) {
46edb027
DV		 4262 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4263 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4264 goto found;
4265 }
4266 }
4267
4268 return NULL;
4269
4270found:
de419ab6
ML		 4271 if (shared_dpll[i].crtc_mask == 0)
4272 shared_dpll[i].hw_state =
4273 crtc_state->dpll_hw_state;
f2a69f44 4274
190f68c5 4275 crtc_state->shared_dpll = i;
46edb027
DV		 4276 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4277 pipe_name(crtc->pipe));
ee7b9f93 4278
de419ab6 4279 shared_dpll[i].crtc_mask |= 1 << crtc->pipe;
e04c7350 4280
ee7b9f93
JB		 4281 return pll;
4282}
4283
de419ab6 4284static void intel_shared_dpll_commit(struct drm_atomic_state *state)
8bd31e67 4285{
de419ab6
ML		 4286 struct drm_i915_private *dev_priv = to_i915(state->dev);
4287 struct intel_shared_dpll_config *shared_dpll;
8bd31e67
ACO		 4288 struct intel_shared_dpll *pll;
4289 enum intel_dpll_id i;
4290
de419ab6
ML		 4291 if (!to_intel_atomic_state(state)->dpll_set)
4292 return;
8bd31e67 4293
de419ab6 4294 shared_dpll = to_intel_atomic_state(state)->shared_dpll;
8bd31e67
ACO		 4295 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4296 pll = &dev_priv->shared_dplls[i];
de419ab6 4297 pll->config = shared_dpll[i];
8bd31e67
ACO		 4298 }
4299}
4300
a1520318 4301static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4302{
4303 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4304 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4305 u32 temp;
4306
4307 temp = I915_READ(dslreg);
4308 udelay(500);
4309 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4310 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4311 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4312 }
4313}
4314
86adf9d7
ML		 4315static int
4316skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
4317 unsigned scaler_user, int *scaler_id, unsigned int rotation,
4318 int src_w, int src_h, int dst_w, int dst_h)
a1b2278e 4319{
86adf9d7
ML		 4320 struct intel_crtc_scaler_state *scaler_state =
4321 &crtc_state->scaler_state;
4322 struct intel_crtc *intel_crtc =
4323 to_intel_crtc(crtc_state->base.crtc);
a1b2278e 4324 int need_scaling;
6156a456
CK		 4325
4326 need_scaling = intel_rotation_90_or_270(rotation) ?
4327 (src_h != dst_w || src_w != dst_h):
4328 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4329
4330 /*
4331 * if plane is being disabled or scaler is no more required or force detach
4332 * - free scaler binded to this plane/crtc
4333 * - in order to do this, update crtc->scaler_usage
4334 *
4335 * Here scaler state in crtc_state is set free so that
4336 * scaler can be assigned to other user. Actual register
4337 * update to free the scaler is done in plane/panel-fit programming.
4338 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4339 */
86adf9d7 4340 if (force_detach || !need_scaling) {
a1b2278e 4341 if (*scaler_id >= 0) {
86adf9d7 4342 scaler_state->scaler_users &= ~(1 << scaler_user);
a1b2278e
CK		 4343 scaler_state->scalers[*scaler_id].in_use = 0;
4344
86adf9d7
ML		 4345 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4346 "Staged freeing scaler id %d scaler_users = 0x%x\n",
4347 intel_crtc->pipe, scaler_user, *scaler_id,
a1b2278e
CK		 4348 scaler_state->scaler_users);
4349 *scaler_id = -1;
4350 }
4351 return 0;
4352 }
4353
4354 /* range checks */
4355 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4356 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4357
4358 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4359 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
86adf9d7 4360 DRM_DEBUG_KMS("scaler_user index %u.%u: src %ux%u dst %ux%u "
a1b2278e 4361 "size is out of scaler range\n",
86adf9d7 4362 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h);
a1b2278e
CK		 4363 return -EINVAL;
4364 }
4365
86adf9d7
ML		 4366 /* mark this plane as a scaler user in crtc_state */
4367 scaler_state->scaler_users |= (1 << scaler_user);
4368 DRM_DEBUG_KMS("scaler_user index %u.%u: "
4369 "staged scaling request for %ux%u->%ux%u scaler_users = 0x%x\n",
4370 intel_crtc->pipe, scaler_user, src_w, src_h, dst_w, dst_h,
4371 scaler_state->scaler_users);
4372
4373 return 0;
4374}
4375
4376/**
4377 * skl_update_scaler_crtc - Stages update to scaler state for a given crtc.
4378 *
4379 * @state: crtc's scaler state
86adf9d7
ML		 4380 *
4381 * Return
4382 * 0 - scaler_usage updated successfully
4383 * error - requested scaling cannot be supported or other error condition
4384 */
e435d6e5 4385int skl_update_scaler_crtc(struct intel_crtc_state *state)
86adf9d7
ML		 4386{
4387 struct intel_crtc *intel_crtc = to_intel_crtc(state->base.crtc);
4388 struct drm_display_mode *adjusted_mode =
4389 &state->base.adjusted_mode;
4390
4391 DRM_DEBUG_KMS("Updating scaler for [CRTC:%i] scaler_user index %u.%u\n",
4392 intel_crtc->base.base.id, intel_crtc->pipe, SKL_CRTC_INDEX);
4393
e435d6e5 4394 return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
86adf9d7
ML		 4395 &state->scaler_state.scaler_id, DRM_ROTATE_0,
4396 state->pipe_src_w, state->pipe_src_h,
8c6cda29 4397 adjusted_mode->hdisplay, adjusted_mode->vdisplay);
86adf9d7
ML		 4398}
4399
4400/**
4401 * skl_update_scaler_plane - Stages update to scaler state for a given plane.
4402 *
4403 * @state: crtc's scaler state
86adf9d7
ML		 4404 * @plane_state: atomic plane state to update
4405 *
4406 * Return
4407 * 0 - scaler_usage updated successfully
4408 * error - requested scaling cannot be supported or other error condition
4409 */
da20eabd
ML		 4410static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
4411 struct intel_plane_state *plane_state)
86adf9d7
ML		 4412{
4413
4414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
da20eabd
ML		 4415 struct intel_plane *intel_plane =
4416 to_intel_plane(plane_state->base.plane);
86adf9d7
ML		 4417 struct drm_framebuffer *fb = plane_state->base.fb;
4418 int ret;
4419
4420 bool force_detach = !fb || !plane_state->visible;
4421
4422 DRM_DEBUG_KMS("Updating scaler for [PLANE:%d] scaler_user index %u.%u\n",
4423 intel_plane->base.base.id, intel_crtc->pipe,
4424 drm_plane_index(&intel_plane->base));
4425
4426 ret = skl_update_scaler(crtc_state, force_detach,
4427 drm_plane_index(&intel_plane->base),
4428 &plane_state->scaler_id,
4429 plane_state->base.rotation,
4430 drm_rect_width(&plane_state->src) >> 16,
4431 drm_rect_height(&plane_state->src) >> 16,
4432 drm_rect_width(&plane_state->dst),
4433 drm_rect_height(&plane_state->dst));
4434
4435 if (ret || plane_state->scaler_id < 0)
4436 return ret;
4437
a1b2278e 4438 /* check colorkey */
818ed961 4439 if (plane_state->ckey.flags != I915_SET_COLORKEY_NONE) {
86adf9d7 4440 DRM_DEBUG_KMS("[PLANE:%d] scaling with color key not allowed",
818ed961 4441 intel_plane->base.base.id);
a1b2278e
CK		 4442 return -EINVAL;
4443 }
4444
4445 /* Check src format */
86adf9d7
ML		 4446 switch (fb->pixel_format) {
4447 case DRM_FORMAT_RGB565:
4448 case DRM_FORMAT_XBGR8888:
4449 case DRM_FORMAT_XRGB8888:
4450 case DRM_FORMAT_ABGR8888:
4451 case DRM_FORMAT_ARGB8888:
4452 case DRM_FORMAT_XRGB2101010:
4453 case DRM_FORMAT_XBGR2101010:
4454 case DRM_FORMAT_YUYV:
4455 case DRM_FORMAT_YVYU:
4456 case DRM_FORMAT_UYVY:
4457 case DRM_FORMAT_VYUY:
4458 break;
4459 default:
4460 DRM_DEBUG_KMS("[PLANE:%d] FB:%d unsupported scaling format 0x%x\n",
4461 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4462 return -EINVAL;
a1b2278e
CK		 4463 }
4464
a1b2278e
CK		 4465 return 0;
4466}
4467
e435d6e5
ML		 4468static void skylake_scaler_disable(struct intel_crtc *crtc)
4469{
4470 int i;
4471
4472 for (i = 0; i < crtc->num_scalers; i++)
4473 skl_detach_scaler(crtc, i);
4474}
4475
4476static void skylake_pfit_enable(struct intel_crtc *crtc)
bd2e244f
JB		 4477{
4478 struct drm_device *dev = crtc->base.dev;
4479 struct drm_i915_private *dev_priv = dev->dev_private;
4480 int pipe = crtc->pipe;
a1b2278e
CK		 4481 struct intel_crtc_scaler_state *scaler_state =
4482 &crtc->config->scaler_state;
4483
4484 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4485
6e3c9717 4486 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4487 int id;
4488
4489 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4490 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4491 return;
4492 }
4493
4494 id = scaler_state->scaler_id;
4495 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4496 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4497 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4498 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4499
4500 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4501 }
4502}
4503
b074cec8
JB		 4504static void ironlake_pfit_enable(struct intel_crtc *crtc)
4505{
4506 struct drm_device *dev = crtc->base.dev;
4507 struct drm_i915_private *dev_priv = dev->dev_private;
4508 int pipe = crtc->pipe;
4509
6e3c9717 4510 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4511 /* Force use of hard-coded filter coefficients
4512 * as some pre-programmed values are broken,
4513 * e.g. x201.
4514 */
4515 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4516 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4517 PF_PIPE_SEL_IVB(pipe));
4518 else
4519 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4520 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4521 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4522 }
4523}
4524
20bc8673 4525void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4526{
cea165c3
VS		 4527 struct drm_device *dev = crtc->base.dev;
4528 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4529
6e3c9717 4530 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4531 return;
4532
cea165c3
VS		 4533 /* We can only enable IPS after we enable a plane and wait for a vblank */
4534 intel_wait_for_vblank(dev, crtc->pipe);
4535
d77e4531 4536 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4537 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4538 mutex_lock(&dev_priv->rps.hw_lock);
4539 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4540 mutex_unlock(&dev_priv->rps.hw_lock);
4541 /* Quoting Art Runyan: "its not safe to expect any particular
4542 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4543 * mailbox." Moreover, the mailbox may return a bogus state,
4544 * so we need to just enable it and continue on.
2a114cc1
BW		 4545 */
4546 } else {
4547 I915_WRITE(IPS_CTL, IPS_ENABLE);
4548 /* The bit only becomes 1 in the next vblank, so this wait here
4549 * is essentially intel_wait_for_vblank. If we don't have this
4550 * and don't wait for vblanks until the end of crtc_enable, then
4551 * the HW state readout code will complain that the expected
4552 * IPS_CTL value is not the one we read. */
4553 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4554 DRM_ERROR("Timed out waiting for IPS enable\n");
4555 }
d77e4531
PZ		 4556}
4557
20bc8673 4558void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4559{
4560 struct drm_device *dev = crtc->base.dev;
4561 struct drm_i915_private *dev_priv = dev->dev_private;
4562
6e3c9717 4563 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4564 return;
4565
4566 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4567 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4568 mutex_lock(&dev_priv->rps.hw_lock);
4569 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4570 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4571 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4572 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4573 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4574 } else {
2a114cc1 4575 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4576 POSTING_READ(IPS_CTL);
4577 }
d77e4531
PZ		 4578
4579 /* We need to wait for a vblank before we can disable the plane. */
4580 intel_wait_for_vblank(dev, crtc->pipe);
4581}
4582
4583/** Loads the palette/gamma unit for the CRTC with the prepared values */
4584static void intel_crtc_load_lut(struct drm_crtc *crtc)
4585{
4586 struct drm_device *dev = crtc->dev;
4587 struct drm_i915_private *dev_priv = dev->dev_private;
4588 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4589 enum pipe pipe = intel_crtc->pipe;
4590 int palreg = PALETTE(pipe);
4591 int i;
4592 bool reenable_ips = false;
4593
4594 /* The clocks have to be on to load the palette. */
53d9f4e9 4595 if (!crtc->state->active)
d77e4531
PZ		 4596 return;
4597
50360403 4598 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4599 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4600 assert_dsi_pll_enabled(dev_priv);
4601 else
4602 assert_pll_enabled(dev_priv, pipe);
4603 }
4604
4605 /* use legacy palette for Ironlake */
7a1db49a 4606 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4607 palreg = LGC_PALETTE(pipe);
4608
4609 /* Workaround : Do not read or write the pipe palette/gamma data while
4610 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4611 */
6e3c9717 4612 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4613 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4614 GAMMA_MODE_MODE_SPLIT)) {
4615 hsw_disable_ips(intel_crtc);
4616 reenable_ips = true;
4617 }
4618
4619 for (i = 0; i < 256; i++) {
4620 I915_WRITE(palreg + 4 * i,
4621 (intel_crtc->lut_r[i] << 16) |
4622 (intel_crtc->lut_g[i] << 8) |
4623 intel_crtc->lut_b[i]);
4624 }
4625
4626 if (reenable_ips)
4627 hsw_enable_ips(intel_crtc);
4628}
4629
7cac945f 4630static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4631{
7cac945f 4632 if (intel_crtc->overlay) {
d3eedb1a
VS		 4633 struct drm_device *dev = intel_crtc->base.dev;
4634 struct drm_i915_private *dev_priv = dev->dev_private;
4635
4636 mutex_lock(&dev->struct_mutex);
4637 dev_priv->mm.interruptible = false;
4638 (void) intel_overlay_switch_off(intel_crtc->overlay);
4639 dev_priv->mm.interruptible = true;
4640 mutex_unlock(&dev->struct_mutex);
4641 }
4642
4643 /* Let userspace switch the overlay on again. In most cases userspace
4644 * has to recompute where to put it anyway.
4645 */
4646}
4647
87d4300a
ML		 4648/**
4649 * intel_post_enable_primary - Perform operations after enabling primary plane
4650 * @crtc: the CRTC whose primary plane was just enabled
4651 *
4652 * Performs potentially sleeping operations that must be done after the primary
4653 * plane is enabled, such as updating FBC and IPS. Note that this may be
4654 * called due to an explicit primary plane update, or due to an implicit
4655 * re-enable that is caused when a sprite plane is updated to no longer
4656 * completely hide the primary plane.
4657 */
4658static void
4659intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4660{
4661 struct drm_device *dev = crtc->dev;
87d4300a 4662 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4664 int pipe = intel_crtc->pipe;
a5c4d7bc 4665
87d4300a
ML		 4666 /*
4667 * BDW signals flip done immediately if the plane
4668 * is disabled, even if the plane enable is already
4669 * armed to occur at the next vblank :(
4670 */
4671 if (IS_BROADWELL(dev))
4672 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4673
87d4300a
ML		 4674 /*
4675 * FIXME IPS should be fine as long as one plane is
4676 * enabled, but in practice it seems to have problems
4677 * when going from primary only to sprite only and vice
4678 * versa.
4679 */
a5c4d7bc
VS		 4680 hsw_enable_ips(intel_crtc);
4681
f99d7069 4682 /*
87d4300a
ML		 4683 * Gen2 reports pipe underruns whenever all planes are disabled.
4684 * So don't enable underrun reporting before at least some planes
4685 * are enabled.
4686 * FIXME: Need to fix the logic to work when we turn off all planes
4687 * but leave the pipe running.
f99d7069 4688 */
87d4300a
ML		 4689 if (IS_GEN2(dev))
4690 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4691
4692 /* Underruns don't raise interrupts, so check manually. */
4693 if (HAS_GMCH_DISPLAY(dev))
4694 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4695}
4696
87d4300a
ML		 4697/**
4698 * intel_pre_disable_primary - Perform operations before disabling primary plane
4699 * @crtc: the CRTC whose primary plane is to be disabled
4700 *
4701 * Performs potentially sleeping operations that must be done before the
4702 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4703 * be called due to an explicit primary plane update, or due to an implicit
4704 * disable that is caused when a sprite plane completely hides the primary
4705 * plane.
4706 */
4707static void
4708intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4709{
4710 struct drm_device *dev = crtc->dev;
4711 struct drm_i915_private *dev_priv = dev->dev_private;
4712 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4713 int pipe = intel_crtc->pipe;
a5c4d7bc 4714
87d4300a
ML		 4715 /*
4716 * Gen2 reports pipe underruns whenever all planes are disabled.
4717 * So diasble underrun reporting before all the planes get disabled.
4718 * FIXME: Need to fix the logic to work when we turn off all planes
4719 * but leave the pipe running.
4720 */
4721 if (IS_GEN2(dev))
4722 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4723
87d4300a
ML		 4724 /*
4725 * Vblank time updates from the shadow to live plane control register
4726 * are blocked if the memory self-refresh mode is active at that
4727 * moment. So to make sure the plane gets truly disabled, disable
4728 * first the self-refresh mode. The self-refresh enable bit in turn
4729 * will be checked/applied by the HW only at the next frame start
4730 * event which is after the vblank start event, so we need to have a
4731 * wait-for-vblank between disabling the plane and the pipe.
4732 */
262cd2e1 4733 if (HAS_GMCH_DISPLAY(dev)) {
87d4300a 4734 intel_set_memory_cxsr(dev_priv, false);
262cd2e1
VS		 4735 dev_priv->wm.vlv.cxsr = false;
4736 intel_wait_for_vblank(dev, pipe);
4737 }
87d4300a 4738
87d4300a
ML		 4739 /*
4740 * FIXME IPS should be fine as long as one plane is
4741 * enabled, but in practice it seems to have problems
4742 * when going from primary only to sprite only and vice
4743 * versa.
4744 */
a5c4d7bc 4745 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4746}
4747
ac21b225
ML		 4748static void intel_post_plane_update(struct intel_crtc *crtc)
4749{
4750 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4751 struct drm_device *dev = crtc->base.dev;
7733b49b 4752 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4753 struct drm_plane *plane;
4754
4755 if (atomic->wait_vblank)
4756 intel_wait_for_vblank(dev, crtc->pipe);
4757
4758 intel_frontbuffer_flip(dev, atomic->fb_bits);
4759
852eb00d
VS		 4760 if (atomic->disable_cxsr)
4761 crtc->wm.cxsr_allowed = true;
4762
f015c551
VS		 4763 if (crtc->atomic.update_wm_post)
4764 intel_update_watermarks(&crtc->base);
4765
c80ac854 4766 if (atomic->update_fbc)
7733b49b 4767 intel_fbc_update(dev_priv);
ac21b225
ML		 4768
4769 if (atomic->post_enable_primary)
4770 intel_post_enable_primary(&crtc->base);
4771
4772 drm_for_each_plane_mask(plane, dev, atomic->update_sprite_watermarks)
4773 intel_update_sprite_watermarks(plane, &crtc->base,
4774 0, 0, 0, false, false);
4775
4776 memset(atomic, 0, sizeof(*atomic));
4777}
4778
4779static void intel_pre_plane_update(struct intel_crtc *crtc)
4780{
4781 struct drm_device *dev = crtc->base.dev;
eddfcbcd 4782 struct drm_i915_private *dev_priv = dev->dev_private;
ac21b225
ML		 4783 struct intel_crtc_atomic_commit *atomic = &crtc->atomic;
4784 struct drm_plane *p;
4785
4786 /* Track fb's for any planes being disabled */
ac21b225
ML		 4787 drm_for_each_plane_mask(p, dev, atomic->disabled_planes) {
4788 struct intel_plane *plane = to_intel_plane(p);
ac21b225
ML		 4789
4790 mutex_lock(&dev->struct_mutex);
a9ff8714
VS		 4791 i915_gem_track_fb(intel_fb_obj(plane->base.fb), NULL,
4792 plane->frontbuffer_bit);
ac21b225
ML		 4793 mutex_unlock(&dev->struct_mutex);
4794 }
4795
4796 if (atomic->wait_for_flips)
4797 intel_crtc_wait_for_pending_flips(&crtc->base);
4798
c80ac854 4799 if (atomic->disable_fbc)
25ad93fd 4800 intel_fbc_disable_crtc(crtc);
ac21b225 4801
066cf55b
RV		 4802 if (crtc->atomic.disable_ips)
4803 hsw_disable_ips(crtc);
4804
ac21b225
ML		 4805 if (atomic->pre_disable_primary)
4806 intel_pre_disable_primary(&crtc->base);
852eb00d
VS		 4807
4808 if (atomic->disable_cxsr) {
4809 crtc->wm.cxsr_allowed = false;
4810 intel_set_memory_cxsr(dev_priv, false);
4811 }
ac21b225
ML		 4812}
4813
d032ffa0 4814static void intel_crtc_disable_planes(struct drm_crtc *crtc, unsigned plane_mask)
87d4300a
ML		 4815{
4816 struct drm_device *dev = crtc->dev;
4817 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d032ffa0 4818 struct drm_plane *p;
87d4300a
ML		 4819 int pipe = intel_crtc->pipe;
4820
7cac945f 4821 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8 4822
d032ffa0
ML		 4823 drm_for_each_plane_mask(p, dev, plane_mask)
4824 to_intel_plane(p)->disable_plane(p, crtc);
f98551ae 4825
f99d7069
DV		 4826 /*
4827 * FIXME: Once we grow proper nuclear flip support out of this we need
4828 * to compute the mask of flip planes precisely. For the time being
4829 * consider this a flip to a NULL plane.
4830 */
4831 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4832}
4833
f67a559d
JB		 4834static void ironlake_crtc_enable(struct drm_crtc *crtc)
4835{
4836 struct drm_device *dev = crtc->dev;
4837 struct drm_i915_private *dev_priv = dev->dev_private;
4838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4839 struct intel_encoder *encoder;
f67a559d 4840 int pipe = intel_crtc->pipe;
f67a559d 4841
53d9f4e9 4842 if (WARN_ON(intel_crtc->active))
f67a559d
JB		 4843 return;
4844
6e3c9717 4845 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4846 intel_prepare_shared_dpll(intel_crtc);
4847
6e3c9717 4848 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4849 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4850
4851 intel_set_pipe_timings(intel_crtc);
4852
6e3c9717 4853 if (intel_crtc->config->has_pch_encoder) {
29407aab 4854 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4855 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4856 }
4857
4858 ironlake_set_pipeconf(crtc);
4859
f67a559d 4860 intel_crtc->active = true;
8664281b 4861
a72e4c9f
DV		 4862 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4863 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4864
f6736a1a 4865 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4866 if (encoder->pre_enable)
4867 encoder->pre_enable(encoder);
f67a559d 4868
6e3c9717 4869 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4870 /* Note: FDI PLL enabling _must_ be done before we enable the
4871 * cpu pipes, hence this is separate from all the other fdi/pch
4872 * enabling. */
88cefb6c 4873 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4874 } else {
4875 assert_fdi_tx_disabled(dev_priv, pipe);
4876 assert_fdi_rx_disabled(dev_priv, pipe);
4877 }
f67a559d 4878
b074cec8 4879 ironlake_pfit_enable(intel_crtc);
f67a559d 4880
9c54c0dd
JB		 4881 /*
4882 * On ILK+ LUT must be loaded before the pipe is running but with
4883 * clocks enabled
4884 */
4885 intel_crtc_load_lut(crtc);
4886
f37fcc2a 4887 intel_update_watermarks(crtc);
e1fdc473 4888 intel_enable_pipe(intel_crtc);
f67a559d 4889
6e3c9717 4890 if (intel_crtc->config->has_pch_encoder)
f67a559d 4891 ironlake_pch_enable(crtc);
c98e9dcf 4892
f9b61ff6
DV		 4893 assert_vblank_disabled(crtc);
4894 drm_crtc_vblank_on(crtc);
4895
fa5c73b1
DV		 4896 for_each_encoder_on_crtc(dev, crtc, encoder)
4897 encoder->enable(encoder);
61b77ddd
DV		 4898
4899 if (HAS_PCH_CPT(dev))
a1520318 4900 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4901}
4902
42db64ef
PZ		 4903/* IPS only exists on ULT machines and is tied to pipe A. */
4904static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4905{
f5adf94e 4906 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4907}
4908
4f771f10
PZ		 4909static void haswell_crtc_enable(struct drm_crtc *crtc)
4910{
4911 struct drm_device *dev = crtc->dev;
4912 struct drm_i915_private *dev_priv = dev->dev_private;
4913 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4914 struct intel_encoder *encoder;
99d736a2
ML		 4915 int pipe = intel_crtc->pipe, hsw_workaround_pipe;
4916 struct intel_crtc_state *pipe_config =
4917 to_intel_crtc_state(crtc->state);
4f771f10 4918
53d9f4e9 4919 if (WARN_ON(intel_crtc->active))
4f771f10
PZ		 4920 return;
4921
df8ad70c
DV		 4922 if (intel_crtc_to_shared_dpll(intel_crtc))
4923 intel_enable_shared_dpll(intel_crtc);
4924
6e3c9717 4925 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4926 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4927
4928 intel_set_pipe_timings(intel_crtc);
4929
6e3c9717
ACO		 4930 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4931 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4932 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4933 }
4934
6e3c9717 4935 if (intel_crtc->config->has_pch_encoder) {
229fca97 4936 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4937 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4938 }
4939
4940 haswell_set_pipeconf(crtc);
4941
4942 intel_set_pipe_csc(crtc);
4943
4f771f10 4944 intel_crtc->active = true;
8664281b 4945
a72e4c9f 4946 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4947 for_each_encoder_on_crtc(dev, crtc, encoder)
4948 if (encoder->pre_enable)
4949 encoder->pre_enable(encoder);
4950
6e3c9717 4951 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4952 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4953 true);
4fe9467d
ID		 4954 dev_priv->display.fdi_link_train(crtc);
4955 }
4956
1f544388 4957 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4958
ff6d9f55 4959 if (INTEL_INFO(dev)->gen == 9)
e435d6e5 4960 skylake_pfit_enable(intel_crtc);
ff6d9f55 4961 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 4962 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 4963 else
4964 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 4965
4966 /*
4967 * On ILK+ LUT must be loaded before the pipe is running but with
4968 * clocks enabled
4969 */
4970 intel_crtc_load_lut(crtc);
4971
1f544388 4972 intel_ddi_set_pipe_settings(crtc);
8228c251 4973 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4974
f37fcc2a 4975 intel_update_watermarks(crtc);
e1fdc473 4976 intel_enable_pipe(intel_crtc);
42db64ef 4977
6e3c9717 4978 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4979 lpt_pch_enable(crtc);
4f771f10 4980
6e3c9717 4981 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4982 intel_ddi_set_vc_payload_alloc(crtc, true);
4983
f9b61ff6
DV		 4984 assert_vblank_disabled(crtc);
4985 drm_crtc_vblank_on(crtc);
4986
8807e55b 4987 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4988 encoder->enable(encoder);
8807e55b
JN		 4989 intel_opregion_notify_encoder(encoder, true);
4990 }
4f771f10 4991
e4916946
PZ		 4992 /* If we change the relative order between pipe/planes enabling, we need
4993 * to change the workaround. */
99d736a2
ML		 4994 hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
4995 if (IS_HASWELL(dev) && hsw_workaround_pipe != INVALID_PIPE) {
4996 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4997 intel_wait_for_vblank(dev, hsw_workaround_pipe);
4998 }
4f771f10
PZ		 4999}
5000
3f8dce3a
DV		 5001static void ironlake_pfit_disable(struct intel_crtc *crtc)
5002{
5003 struct drm_device *dev = crtc->base.dev;
5004 struct drm_i915_private *dev_priv = dev->dev_private;
5005 int pipe = crtc->pipe;
5006
5007 /* To avoid upsetting the power well on haswell only disable the pfit if
5008 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 5009 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5010 I915_WRITE(PF_CTL(pipe), 0);
5011 I915_WRITE(PF_WIN_POS(pipe), 0);
5012 I915_WRITE(PF_WIN_SZ(pipe), 0);
5013 }
5014}
5015
6be4a607
JB		 5016static void ironlake_crtc_disable(struct drm_crtc *crtc)
5017{
5018 struct drm_device *dev = crtc->dev;
5019 struct drm_i915_private *dev_priv = dev->dev_private;
5020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5021 struct intel_encoder *encoder;
6be4a607 5022 int pipe = intel_crtc->pipe;
5eddb70b 5023 u32 reg, temp;
b52eb4dc 5024
ea9d758d
DV		 5025 for_each_encoder_on_crtc(dev, crtc, encoder)
5026 encoder->disable(encoder);
5027
f9b61ff6
DV		 5028 drm_crtc_vblank_off(crtc);
5029 assert_vblank_disabled(crtc);
5030
6e3c9717 5031 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5032 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5033
575f7ab7 5034 intel_disable_pipe(intel_crtc);
32f9d658 5035
3f8dce3a 5036 ironlake_pfit_disable(intel_crtc);
2c07245f 5037
5a74f70a
VS		 5038 if (intel_crtc->config->has_pch_encoder)
5039 ironlake_fdi_disable(crtc);
5040
bf49ec8c
DV		 5041 for_each_encoder_on_crtc(dev, crtc, encoder)
5042 if (encoder->post_disable)
5043 encoder->post_disable(encoder);
2c07245f 5044
6e3c9717 5045 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5046 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5047
d925c59a
DV		 5048 if (HAS_PCH_CPT(dev)) {
5049 /* disable TRANS_DP_CTL */
5050 reg = TRANS_DP_CTL(pipe);
5051 temp = I915_READ(reg);
5052 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5053 TRANS_DP_PORT_SEL_MASK);
5054 temp |= TRANS_DP_PORT_SEL_NONE;
5055 I915_WRITE(reg, temp);
5056
5057 /* disable DPLL_SEL */
5058 temp = I915_READ(PCH_DPLL_SEL);
11887397 5059 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5060 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5061 }
e3421a18 5062
d925c59a
DV		 5063 ironlake_fdi_pll_disable(intel_crtc);
5064 }
e4ca0612
PJ		 5065
5066 intel_crtc->active = false;
5067 intel_update_watermarks(crtc);
6be4a607 5068}
1b3c7a47 5069
4f771f10 5070static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5071{
4f771f10
PZ		 5072 struct drm_device *dev = crtc->dev;
5073 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5074 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5075 struct intel_encoder *encoder;
6e3c9717 5076 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5077
8807e55b
JN		 5078 for_each_encoder_on_crtc(dev, crtc, encoder) {
5079 intel_opregion_notify_encoder(encoder, false);
4f771f10 5080 encoder->disable(encoder);
8807e55b 5081 }
4f771f10 5082
f9b61ff6
DV		 5083 drm_crtc_vblank_off(crtc);
5084 assert_vblank_disabled(crtc);
5085
6e3c9717 5086 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5087 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5088 false);
575f7ab7 5089 intel_disable_pipe(intel_crtc);
4f771f10 5090
6e3c9717 5091 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5092 intel_ddi_set_vc_payload_alloc(crtc, false);
5093
ad80a810 5094 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5095
ff6d9f55 5096 if (INTEL_INFO(dev)->gen == 9)
e435d6e5 5097 skylake_scaler_disable(intel_crtc);
ff6d9f55 5098 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5099 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5100 else
5101 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5102
1f544388 5103 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5104
6e3c9717 5105 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5106 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5107 intel_ddi_fdi_disable(crtc);
83616634 5108 }
4f771f10 5109
97b040aa
ID		 5110 for_each_encoder_on_crtc(dev, crtc, encoder)
5111 if (encoder->post_disable)
5112 encoder->post_disable(encoder);
e4ca0612
PJ		 5113
5114 intel_crtc->active = false;
5115 intel_update_watermarks(crtc);
4f771f10
PZ		 5116}
5117
2dd24552
JB		 5118static void i9xx_pfit_enable(struct intel_crtc *crtc)
5119{
5120 struct drm_device *dev = crtc->base.dev;
5121 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5122 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5123
681a8504 5124 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5125 return;
5126
2dd24552 5127 /*
c0b03411
DV		 5128 * The panel fitter should only be adjusted whilst the pipe is disabled,
5129 * according to register description and PRM.
2dd24552 5130 */
c0b03411
DV		 5131 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5132 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5133
b074cec8
JB		 5134 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5135 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5136
5137 /* Border color in case we don't scale up to the full screen. Black by
5138 * default, change to something else for debugging. */
5139 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5140}
5141
d05410f9
DA		 5142static enum intel_display_power_domain port_to_power_domain(enum port port)
5143{
5144 switch (port) {
5145 case PORT_A:
5146 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5147 case PORT_B:
5148 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5149 case PORT_C:
5150 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5151 case PORT_D:
5152 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5153 default:
5154 WARN_ON_ONCE(1);
5155 return POWER_DOMAIN_PORT_OTHER;
5156 }
5157}
5158
77d22dca
ID		 5159#define for_each_power_domain(domain, mask) \
5160 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5161 if ((1 << (domain)) & (mask))
5162
319be8ae
ID		 5163enum intel_display_power_domain
5164intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5165{
5166 struct drm_device *dev = intel_encoder->base.dev;
5167 struct intel_digital_port *intel_dig_port;
5168
5169 switch (intel_encoder->type) {
5170 case INTEL_OUTPUT_UNKNOWN:
5171 /* Only DDI platforms should ever use this output type */
5172 WARN_ON_ONCE(!HAS_DDI(dev));
5173 case INTEL_OUTPUT_DISPLAYPORT:
5174 case INTEL_OUTPUT_HDMI:
5175 case INTEL_OUTPUT_EDP:
5176 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5177 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5178 case INTEL_OUTPUT_DP_MST:
5179 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5180 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5181 case INTEL_OUTPUT_ANALOG:
5182 return POWER_DOMAIN_PORT_CRT;
5183 case INTEL_OUTPUT_DSI:
5184 return POWER_DOMAIN_PORT_DSI;
5185 default:
5186 return POWER_DOMAIN_PORT_OTHER;
5187 }
5188}
5189
5190static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5191{
319be8ae
ID		 5192 struct drm_device *dev = crtc->dev;
5193 struct intel_encoder *intel_encoder;
5194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5195 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5196 unsigned long mask;
5197 enum transcoder transcoder;
5198
5199 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5200
5201 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5202 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5203 if (intel_crtc->config->pch_pfit.enabled ||
5204 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5205 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5206
319be8ae
ID		 5207 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5208 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5209
77d22dca
ID		 5210 return mask;
5211}
5212
679dacd4 5213static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5214{
679dacd4 5215 struct drm_device *dev = state->dev;
77d22dca
ID		 5216 struct drm_i915_private *dev_priv = dev->dev_private;
5217 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5218 struct intel_crtc *crtc;
5219
5220 /*
5221 * First get all needed power domains, then put all unneeded, to avoid
5222 * any unnecessary toggling of the power wells.
5223 */
d3fcc808 5224 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5225 enum intel_display_power_domain domain;
5226
83d65738 5227 if (!crtc->base.state->enable)
77d22dca
ID		 5228 continue;
5229
319be8ae 5230 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5231
5232 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5233 intel_display_power_get(dev_priv, domain);
5234 }
5235
27c329ed
ML		 5236 if (dev_priv->display.modeset_commit_cdclk) {
5237 unsigned int cdclk = to_intel_atomic_state(state)->cdclk;
5238
5239 if (cdclk != dev_priv->cdclk_freq &&
5240 !WARN_ON(!state->allow_modeset))
5241 dev_priv->display.modeset_commit_cdclk(state);
5242 }
50f6e502 5243
d3fcc808 5244 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5245 enum intel_display_power_domain domain;
5246
5247 for_each_power_domain(domain, crtc->enabled_power_domains)
5248 intel_display_power_put(dev_priv, domain);
5249
5250 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5251 }
5252
5253 intel_display_set_init_power(dev_priv, false);
5254}
5255
560a7ae4
DL		 5256static void intel_update_max_cdclk(struct drm_device *dev)
5257{
5258 struct drm_i915_private *dev_priv = dev->dev_private;
5259
5260 if (IS_SKYLAKE(dev)) {
5261 u32 limit = I915_READ(SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
5262
5263 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
5264 dev_priv->max_cdclk_freq = 675000;
5265 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
5266 dev_priv->max_cdclk_freq = 540000;
5267 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
5268 dev_priv->max_cdclk_freq = 450000;
5269 else
5270 dev_priv->max_cdclk_freq = 337500;
5271 } else if (IS_BROADWELL(dev)) {
5272 /*
5273 * FIXME with extra cooling we can allow
5274 * 540 MHz for ULX and 675 Mhz for ULT.
5275 * How can we know if extra cooling is
5276 * available? PCI ID, VTB, something else?
5277 */
5278 if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
5279 dev_priv->max_cdclk_freq = 450000;
5280 else if (IS_BDW_ULX(dev))
5281 dev_priv->max_cdclk_freq = 450000;
5282 else if (IS_BDW_ULT(dev))
5283 dev_priv->max_cdclk_freq = 540000;
5284 else
5285 dev_priv->max_cdclk_freq = 675000;
0904deaf
MK		 5286 } else if (IS_CHERRYVIEW(dev)) {
5287 dev_priv->max_cdclk_freq = 320000;
560a7ae4
DL		 5288 } else if (IS_VALLEYVIEW(dev)) {
5289 dev_priv->max_cdclk_freq = 400000;
5290 } else {
5291 /* otherwise assume cdclk is fixed */
5292 dev_priv->max_cdclk_freq = dev_priv->cdclk_freq;
5293 }
5294
5295 DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n",
5296 dev_priv->max_cdclk_freq);
5297}
5298
5299static void intel_update_cdclk(struct drm_device *dev)
5300{
5301 struct drm_i915_private *dev_priv = dev->dev_private;
5302
5303 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
5304 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
5305 dev_priv->cdclk_freq);
5306
5307 /*
5308 * Program the gmbus_freq based on the cdclk frequency.
5309 * BSpec erroneously claims we should aim for 4MHz, but
5310 * in fact 1MHz is the correct frequency.
5311 */
5312 if (IS_VALLEYVIEW(dev)) {
5313 /*
5314 * Program the gmbus_freq based on the cdclk frequency.
5315 * BSpec erroneously claims we should aim for 4MHz, but
5316 * in fact 1MHz is the correct frequency.
5317 */
5318 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
5319 }
5320
5321 if (dev_priv->max_cdclk_freq == 0)
5322 intel_update_max_cdclk(dev);
5323}
5324
70d0c574 5325static void broxton_set_cdclk(struct drm_device *dev, int frequency)
f8437dd1
VK		 5326{
5327 struct drm_i915_private *dev_priv = dev->dev_private;
5328 uint32_t divider;
5329 uint32_t ratio;
5330 uint32_t current_freq;
5331 int ret;
5332
5333 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5334 switch (frequency) {
5335 case 144000:
5336 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5337 ratio = BXT_DE_PLL_RATIO(60);
5338 break;
5339 case 288000:
5340 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5341 ratio = BXT_DE_PLL_RATIO(60);
5342 break;
5343 case 384000:
5344 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5345 ratio = BXT_DE_PLL_RATIO(60);
5346 break;
5347 case 576000:
5348 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5349 ratio = BXT_DE_PLL_RATIO(60);
5350 break;
5351 case 624000:
5352 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5353 ratio = BXT_DE_PLL_RATIO(65);
5354 break;
5355 case 19200:
5356 /*
5357 * Bypass frequency with DE PLL disabled. Init ratio, divider
5358 * to suppress GCC warning.
5359 */
5360 ratio = 0;
5361 divider = 0;
5362 break;
5363 default:
5364 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5365
5366 return;
5367 }
5368
5369 mutex_lock(&dev_priv->rps.hw_lock);
5370 /* Inform power controller of upcoming frequency change */
5371 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5372 0x80000000);
5373 mutex_unlock(&dev_priv->rps.hw_lock);
5374
5375 if (ret) {
5376 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5377 ret, frequency);
5378 return;
5379 }
5380
5381 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5382 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5383 current_freq = current_freq * 500 + 1000;
5384
5385 /*
5386 * DE PLL has to be disabled when
5387 * - setting to 19.2MHz (bypass, PLL isn't used)
5388 * - before setting to 624MHz (PLL needs toggling)
5389 * - before setting to any frequency from 624MHz (PLL needs toggling)
5390 */
5391 if (frequency == 19200 || frequency == 624000 ||
5392 current_freq == 624000) {
5393 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5394 /* Timeout 200us */
5395 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5396 1))
5397 DRM_ERROR("timout waiting for DE PLL unlock\n");
5398 }
5399
5400 if (frequency != 19200) {
5401 uint32_t val;
5402
5403 val = I915_READ(BXT_DE_PLL_CTL);
5404 val &= ~BXT_DE_PLL_RATIO_MASK;
5405 val |= ratio;
5406 I915_WRITE(BXT_DE_PLL_CTL, val);
5407
5408 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5409 /* Timeout 200us */
5410 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5411 DRM_ERROR("timeout waiting for DE PLL lock\n");
5412
5413 val = I915_READ(CDCLK_CTL);
5414 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5415 val |= divider;
5416 /*
5417 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5418 * enable otherwise.
5419 */
5420 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5421 if (frequency >= 500000)
5422 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5423
5424 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5425 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5426 val |= (frequency - 1000) / 500;
5427 I915_WRITE(CDCLK_CTL, val);
5428 }
5429
5430 mutex_lock(&dev_priv->rps.hw_lock);
5431 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5432 DIV_ROUND_UP(frequency, 25000));
5433 mutex_unlock(&dev_priv->rps.hw_lock);
5434
5435 if (ret) {
5436 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5437 ret, frequency);
5438 return;
5439 }
5440
a47871bd 5441 intel_update_cdclk(dev);
f8437dd1
VK		 5442}
5443
5444void broxton_init_cdclk(struct drm_device *dev)
5445{
5446 struct drm_i915_private *dev_priv = dev->dev_private;
5447 uint32_t val;
5448
5449 /*
5450 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5451 * or else the reset will hang because there is no PCH to respond.
5452 * Move the handshake programming to initialization sequence.
5453 * Previously was left up to BIOS.
5454 */
5455 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5456 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5457 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5458
5459 /* Enable PG1 for cdclk */
5460 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5461
5462 /* check if cd clock is enabled */
5463 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5464 DRM_DEBUG_KMS("Display already initialized\n");
5465 return;
5466 }
5467
5468 /*
5469 * FIXME:
5470 * - The initial CDCLK needs to be read from VBT.
5471 * Need to make this change after VBT has changes for BXT.
5472 * - check if setting the max (or any) cdclk freq is really necessary
5473 * here, it belongs to modeset time
5474 */
5475 broxton_set_cdclk(dev, 624000);
5476
5477 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5478 POSTING_READ(DBUF_CTL);
5479
f8437dd1
VK		 5480 udelay(10);
5481
5482 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5483 DRM_ERROR("DBuf power enable timeout!\n");
5484}
5485
5486void broxton_uninit_cdclk(struct drm_device *dev)
5487{
5488 struct drm_i915_private *dev_priv = dev->dev_private;
5489
5490 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5491 POSTING_READ(DBUF_CTL);
5492
f8437dd1
VK		 5493 udelay(10);
5494
5495 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5496 DRM_ERROR("DBuf power disable timeout!\n");
5497
5498 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5499 broxton_set_cdclk(dev, 19200);
5500
5501 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5502}
5503
5d96d8af
DL		 5504static const struct skl_cdclk_entry {
5505 unsigned int freq;
5506 unsigned int vco;
5507} skl_cdclk_frequencies[] = {
5508 { .freq = 308570, .vco = 8640 },
5509 { .freq = 337500, .vco = 8100 },
5510 { .freq = 432000, .vco = 8640 },
5511 { .freq = 450000, .vco = 8100 },
5512 { .freq = 540000, .vco = 8100 },
5513 { .freq = 617140, .vco = 8640 },
5514 { .freq = 675000, .vco = 8100 },
5515};
5516
5517static unsigned int skl_cdclk_decimal(unsigned int freq)
5518{
5519 return (freq - 1000) / 500;
5520}
5521
5522static unsigned int skl_cdclk_get_vco(unsigned int freq)
5523{
5524 unsigned int i;
5525
5526 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5527 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5528
5529 if (e->freq == freq)
5530 return e->vco;
5531 }
5532
5533 return 8100;
5534}
5535
5536static void
5537skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5538{
5539 unsigned int min_freq;
5540 u32 val;
5541
5542 /* select the minimum CDCLK before enabling DPLL 0 */
5543 val = I915_READ(CDCLK_CTL);
5544 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5545 val |= CDCLK_FREQ_337_308;
5546
5547 if (required_vco == 8640)
5548 min_freq = 308570;
5549 else
5550 min_freq = 337500;
5551
5552 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5553
5554 I915_WRITE(CDCLK_CTL, val);
5555 POSTING_READ(CDCLK_CTL);
5556
5557 /*
5558 * We always enable DPLL0 with the lowest link rate possible, but still
5559 * taking into account the VCO required to operate the eDP panel at the
5560 * desired frequency. The usual DP link rates operate with a VCO of
5561 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5562 * The modeset code is responsible for the selection of the exact link
5563 * rate later on, with the constraint of choosing a frequency that
5564 * works with required_vco.
5565 */
5566 val = I915_READ(DPLL_CTRL1);
5567
5568 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5569 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5570 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5571 if (required_vco == 8640)
5572 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5573 SKL_DPLL0);
5574 else
5575 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5576 SKL_DPLL0);
5577
5578 I915_WRITE(DPLL_CTRL1, val);
5579 POSTING_READ(DPLL_CTRL1);
5580
5581 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5582
5583 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5584 DRM_ERROR("DPLL0 not locked\n");
5585}
5586
5587static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5588{
5589 int ret;
5590 u32 val;
5591
5592 /* inform PCU we want to change CDCLK */
5593 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5594 mutex_lock(&dev_priv->rps.hw_lock);
5595 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5596 mutex_unlock(&dev_priv->rps.hw_lock);
5597
5598 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5599}
5600
5601static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5602{
5603 unsigned int i;
5604
5605 for (i = 0; i < 15; i++) {
5606 if (skl_cdclk_pcu_ready(dev_priv))
5607 return true;
5608 udelay(10);
5609 }
5610
5611 return false;
5612}
5613
5614static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5615{
560a7ae4 5616 struct drm_device *dev = dev_priv->dev;
5d96d8af
DL		 5617 u32 freq_select, pcu_ack;
5618
5619 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5620
5621 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5622 DRM_ERROR("failed to inform PCU about cdclk change\n");
5623 return;
5624 }
5625
5626 /* set CDCLK_CTL */
5627 switch(freq) {
5628 case 450000:
5629 case 432000:
5630 freq_select = CDCLK_FREQ_450_432;
5631 pcu_ack = 1;
5632 break;
5633 case 540000:
5634 freq_select = CDCLK_FREQ_540;
5635 pcu_ack = 2;
5636 break;
5637 case 308570:
5638 case 337500:
5639 default:
5640 freq_select = CDCLK_FREQ_337_308;
5641 pcu_ack = 0;
5642 break;
5643 case 617140:
5644 case 675000:
5645 freq_select = CDCLK_FREQ_675_617;
5646 pcu_ack = 3;
5647 break;
5648 }
5649
5650 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5651 POSTING_READ(CDCLK_CTL);
5652
5653 /* inform PCU of the change */
5654 mutex_lock(&dev_priv->rps.hw_lock);
5655 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5656 mutex_unlock(&dev_priv->rps.hw_lock);
560a7ae4
DL		 5657
5658 intel_update_cdclk(dev);
5d96d8af
DL		 5659}
5660
5661void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5662{
5663 /* disable DBUF power */
5664 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5665 POSTING_READ(DBUF_CTL);
5666
5667 udelay(10);
5668
5669 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5670 DRM_ERROR("DBuf power disable timeout\n");
5671
5672 /* disable DPLL0 */
5673 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5674 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5675 DRM_ERROR("Couldn't disable DPLL0\n");
5676
5677 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5678}
5679
5680void skl_init_cdclk(struct drm_i915_private *dev_priv)
5681{
5682 u32 val;
5683 unsigned int required_vco;
5684
5685 /* enable PCH reset handshake */
5686 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5687 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5688
5689 /* enable PG1 and Misc I/O */
5690 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5691
5692 /* DPLL0 already enabed !? */
5693 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5694 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5695 return;
5696 }
5697
5698 /* enable DPLL0 */
5699 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5700 skl_dpll0_enable(dev_priv, required_vco);
5701
5702 /* set CDCLK to the frequency the BIOS chose */
5703 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5704
5705 /* enable DBUF power */
5706 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5707 POSTING_READ(DBUF_CTL);
5708
5709 udelay(10);
5710
5711 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5712 DRM_ERROR("DBuf power enable timeout\n");
5713}
5714
dfcab17e 5715/* returns HPLL frequency in kHz */
f8bf63fd 5716static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5717{
586f49dc 5718 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5719
586f49dc 5720 /* Obtain SKU information */
a580516d 5721 mutex_lock(&dev_priv->sb_lock);
586f49dc
JB		 5722 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5723 CCK_FUSE_HPLL_FREQ_MASK;
a580516d 5724 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5725
dfcab17e 5726 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5727}
5728
5729/* Adjust CDclk dividers to allow high res or save power if possible */
5730static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5731{
5732 struct drm_i915_private *dev_priv = dev->dev_private;
5733 u32 val, cmd;
5734
164dfd28
VK		 5735 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5736 != dev_priv->cdclk_freq);
d60c4473 5737
dfcab17e 5738 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5739 cmd = 2;
dfcab17e 5740 else if (cdclk == 266667)
30a970c6
JB		 5741 cmd = 1;
5742 else
5743 cmd = 0;
5744
5745 mutex_lock(&dev_priv->rps.hw_lock);
5746 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5747 val &= ~DSPFREQGUAR_MASK;
5748 val |= (cmd << DSPFREQGUAR_SHIFT);
5749 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5750 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5751 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5752 50)) {
5753 DRM_ERROR("timed out waiting for CDclk change\n");
5754 }
5755 mutex_unlock(&dev_priv->rps.hw_lock);
5756
54433e91
VS		 5757 mutex_lock(&dev_priv->sb_lock);
5758
dfcab17e 5759 if (cdclk == 400000) {
6bcda4f0 5760 u32 divider;
30a970c6 5761
6bcda4f0 5762 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6 5763
30a970c6
JB		 5764 /* adjust cdclk divider */
5765 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5766 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5767 val |= divider;
5768 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5769
5770 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5771 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5772 50))
5773 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5774 }
5775
30a970c6
JB		 5776 /* adjust self-refresh exit latency value */
5777 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5778 val &= ~0x7f;
5779
5780 /*
5781 * For high bandwidth configs, we set a higher latency in the bunit
5782 * so that the core display fetch happens in time to avoid underruns.
5783 */
dfcab17e 5784 if (cdclk == 400000)
30a970c6
JB		 5785 val |= 4500 / 250; /* 4.5 usec */
5786 else
5787 val |= 3000 / 250; /* 3.0 usec */
5788 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
54433e91 5789
a580516d 5790 mutex_unlock(&dev_priv->sb_lock);
30a970c6 5791
b6283055 5792 intel_update_cdclk(dev);
30a970c6
JB		 5793}
5794
383c5a6a
VS		 5795static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5796{
5797 struct drm_i915_private *dev_priv = dev->dev_private;
5798 u32 val, cmd;
5799
164dfd28
VK		 5800 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5801 != dev_priv->cdclk_freq);
383c5a6a
VS		 5802
5803 switch (cdclk) {
383c5a6a
VS		 5804 case 333333:
5805 case 320000:
383c5a6a 5806 case 266667:
383c5a6a 5807 case 200000:
383c5a6a
VS		 5808 break;
5809 default:
5f77eeb0 5810 MISSING_CASE(cdclk);
383c5a6a
VS		 5811 return;
5812 }
5813
9d0d3fda
VS		 5814 /*
5815 * Specs are full of misinformation, but testing on actual
5816 * hardware has shown that we just need to write the desired
5817 * CCK divider into the Punit register.
5818 */
5819 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5820
383c5a6a
VS		 5821 mutex_lock(&dev_priv->rps.hw_lock);
5822 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5823 val &= ~DSPFREQGUAR_MASK_CHV;
5824 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5825 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5826 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5827 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5828 50)) {
5829 DRM_ERROR("timed out waiting for CDclk change\n");
5830 }
5831 mutex_unlock(&dev_priv->rps.hw_lock);
5832
b6283055 5833 intel_update_cdclk(dev);
383c5a6a
VS		 5834}
5835
30a970c6
JB		 5836static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5837 int max_pixclk)
5838{
6bcda4f0 5839 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5840 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5841
30a970c6
JB		 5842 /*
5843 * Really only a few cases to deal with, as only 4 CDclks are supported:
5844 * 200MHz
5845 * 267MHz
29dc7ef3 5846 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5847 * 400MHz (VLV only)
5848 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5849 * of the lower bin and adjust if needed.
e37c67a1
VS		 5850 *
5851 * We seem to get an unstable or solid color picture at 200MHz.
5852 * Not sure what's wrong. For now use 200MHz only when all pipes
5853 * are off.
30a970c6 5854 */
6cca3195
VS		 5855 if (!IS_CHERRYVIEW(dev_priv) &&
5856 max_pixclk > freq_320*limit/100)
dfcab17e 5857 return 400000;
6cca3195 5858 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5859 return freq_320;
e37c67a1 5860 else if (max_pixclk > 0)
dfcab17e 5861 return 266667;
e37c67a1
VS		 5862 else
5863 return 200000;
30a970c6
JB		 5864}
5865
f8437dd1
VK		 5866static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5867 int max_pixclk)
5868{
5869 /*
5870 * FIXME:
5871 * - remove the guardband, it's not needed on BXT
5872 * - set 19.2MHz bypass frequency if there are no active pipes
5873 */
5874 if (max_pixclk > 576000*9/10)
5875 return 624000;
5876 else if (max_pixclk > 384000*9/10)
5877 return 576000;
5878 else if (max_pixclk > 288000*9/10)
5879 return 384000;
5880 else if (max_pixclk > 144000*9/10)
5881 return 288000;
5882 else
5883 return 144000;
5884}
5885
a821fc46
ACO		 5886/* Compute the max pixel clock for new configuration. Uses atomic state if
5887 * that's non-NULL, look at current state otherwise. */
5888static int intel_mode_max_pixclk(struct drm_device *dev,
5889 struct drm_atomic_state *state)
30a970c6 5890{
30a970c6 5891 struct intel_crtc *intel_crtc;
304603f4 5892 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5893 int max_pixclk = 0;
5894
d3fcc808 5895 for_each_intel_crtc(dev, intel_crtc) {
27c329ed 5896 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
304603f4
ACO		 5897 if (IS_ERR(crtc_state))
5898 return PTR_ERR(crtc_state);
5899
5900 if (!crtc_state->base.enable)
5901 continue;
5902
5903 max_pixclk = max(max_pixclk,
5904 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5905 }
5906
5907 return max_pixclk;
5908}
5909
27c329ed 5910static int valleyview_modeset_calc_cdclk(struct drm_atomic_state *state)
30a970c6 5911{
27c329ed
ML		 5912 struct drm_device *dev = state->dev;
5913 struct drm_i915_private *dev_priv = dev->dev_private;
5914 int max_pixclk = intel_mode_max_pixclk(dev, state);
30a970c6 5915
304603f4
ACO		 5916 if (max_pixclk < 0)
5917 return max_pixclk;
30a970c6 5918
27c329ed
ML		 5919 to_intel_atomic_state(state)->cdclk =
5920 valleyview_calc_cdclk(dev_priv, max_pixclk);
0a9ab303 5921
27c329ed
ML		 5922 return 0;
5923}
304603f4 5924
27c329ed
ML		 5925static int broxton_modeset_calc_cdclk(struct drm_atomic_state *state)
5926{
5927 struct drm_device *dev = state->dev;
5928 struct drm_i915_private *dev_priv = dev->dev_private;
5929 int max_pixclk = intel_mode_max_pixclk(dev, state);
85a96e7a 5930
27c329ed
ML		 5931 if (max_pixclk < 0)
5932 return max_pixclk;
85a96e7a 5933
27c329ed
ML		 5934 to_intel_atomic_state(state)->cdclk =
5935 broxton_calc_cdclk(dev_priv, max_pixclk);
85a96e7a 5936
27c329ed 5937 return 0;
30a970c6
JB		 5938}
5939
1e69cd74
VS		 5940static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5941{
5942 unsigned int credits, default_credits;
5943
5944 if (IS_CHERRYVIEW(dev_priv))
5945 default_credits = PFI_CREDIT(12);
5946 else
5947 default_credits = PFI_CREDIT(8);
5948
164dfd28 5949 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5950 /* CHV suggested value is 31 or 63 */
5951 if (IS_CHERRYVIEW(dev_priv))
fcc0008f 5952 credits = PFI_CREDIT_63;
1e69cd74
VS		 5953 else
5954 credits = PFI_CREDIT(15);
5955 } else {
5956 credits = default_credits;
5957 }
5958
5959 /*
5960 * WA - write default credits before re-programming
5961 * FIXME: should we also set the resend bit here?
5962 */
5963 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5964 default_credits);
5965
5966 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5967 credits | PFI_CREDIT_RESEND);
5968
5969 /*
5970 * FIXME is this guaranteed to clear
5971 * immediately or should we poll for it?
5972 */
5973 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5974}
5975
27c329ed 5976static void valleyview_modeset_commit_cdclk(struct drm_atomic_state *old_state)
30a970c6 5977{
a821fc46 5978 struct drm_device *dev = old_state->dev;
27c329ed 5979 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
30a970c6 5980 struct drm_i915_private *dev_priv = dev->dev_private;
30a970c6 5981
27c329ed
ML		 5982 /*
5983 * FIXME: We can end up here with all power domains off, yet
5984 * with a CDCLK frequency other than the minimum. To account
5985 * for this take the PIPE-A power domain, which covers the HW
5986 * blocks needed for the following programming. This can be
5987 * removed once it's guaranteed that we get here either with
5988 * the minimum CDCLK set, or the required power domains
5989 * enabled.
5990 */
5991 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
738c05c0 5992
27c329ed
ML		 5993 if (IS_CHERRYVIEW(dev))
5994 cherryview_set_cdclk(dev, req_cdclk);
5995 else
5996 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5997
27c329ed 5998 vlv_program_pfi_credits(dev_priv);
1e69cd74 5999
27c329ed 6000 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
30a970c6
JB		 6001}
6002
89b667f8
JB		 6003static void valleyview_crtc_enable(struct drm_crtc *crtc)
6004{
6005 struct drm_device *dev = crtc->dev;
a72e4c9f 6006 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6008 struct intel_encoder *encoder;
6009 int pipe = intel_crtc->pipe;
23538ef1 6010 bool is_dsi;
89b667f8 6011
53d9f4e9 6012 if (WARN_ON(intel_crtc->active))
89b667f8
JB		 6013 return;
6014
409ee761 6015 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6016
1ae0d137
VS		 6017 if (!is_dsi) {
6018 if (IS_CHERRYVIEW(dev))
6e3c9717 6019 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6020 else
6e3c9717 6021 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6022 }
5b18e57c 6023
6e3c9717 6024 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6025 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6026
6027 intel_set_pipe_timings(intel_crtc);
6028
c14b0485
VS		 6029 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6030 struct drm_i915_private *dev_priv = dev->dev_private;
6031
6032 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6033 I915_WRITE(CHV_CANVAS(pipe), 0);
6034 }
6035
5b18e57c
DV		 6036 i9xx_set_pipeconf(intel_crtc);
6037
89b667f8 6038 intel_crtc->active = true;
89b667f8 6039
a72e4c9f 6040 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6041
89b667f8
JB		 6042 for_each_encoder_on_crtc(dev, crtc, encoder)
6043 if (encoder->pre_pll_enable)
6044 encoder->pre_pll_enable(encoder);
6045
9d556c99
CML		 6046 if (!is_dsi) {
6047 if (IS_CHERRYVIEW(dev))
6e3c9717 6048 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6049 else
6e3c9717 6050 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6051 }
89b667f8
JB		 6052
6053 for_each_encoder_on_crtc(dev, crtc, encoder)
6054 if (encoder->pre_enable)
6055 encoder->pre_enable(encoder);
6056
2dd24552
JB		 6057 i9xx_pfit_enable(intel_crtc);
6058
63cbb074
VS		 6059 intel_crtc_load_lut(crtc);
6060
e1fdc473 6061 intel_enable_pipe(intel_crtc);
be6a6f8e 6062
4b3a9526
VS		 6063 assert_vblank_disabled(crtc);
6064 drm_crtc_vblank_on(crtc);
6065
f9b61ff6
DV		 6066 for_each_encoder_on_crtc(dev, crtc, encoder)
6067 encoder->enable(encoder);
89b667f8
JB		 6068}
6069
f13c2ef3
DV		 6070static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6071{
6072 struct drm_device *dev = crtc->base.dev;
6073 struct drm_i915_private *dev_priv = dev->dev_private;
6074
6e3c9717
ACO		 6075 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6076 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6077}
6078
0b8765c6 6079static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6080{
6081 struct drm_device *dev = crtc->dev;
a72e4c9f 6082 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6083 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6084 struct intel_encoder *encoder;
79e53945 6085 int pipe = intel_crtc->pipe;
79e53945 6086
53d9f4e9 6087 if (WARN_ON(intel_crtc->active))
f7abfe8b
CW		 6088 return;
6089
f13c2ef3
DV		 6090 i9xx_set_pll_dividers(intel_crtc);
6091
6e3c9717 6092 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6093 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6094
6095 intel_set_pipe_timings(intel_crtc);
6096
5b18e57c
DV		 6097 i9xx_set_pipeconf(intel_crtc);
6098
f7abfe8b 6099 intel_crtc->active = true;
6b383a7f 6100
4a3436e8 6101 if (!IS_GEN2(dev))
a72e4c9f 6102 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6103
9d6d9f19
MK		 6104 for_each_encoder_on_crtc(dev, crtc, encoder)
6105 if (encoder->pre_enable)
6106 encoder->pre_enable(encoder);
6107
f6736a1a
DV		 6108 i9xx_enable_pll(intel_crtc);
6109
2dd24552
JB		 6110 i9xx_pfit_enable(intel_crtc);
6111
63cbb074
VS		 6112 intel_crtc_load_lut(crtc);
6113
f37fcc2a 6114 intel_update_watermarks(crtc);
e1fdc473 6115 intel_enable_pipe(intel_crtc);
be6a6f8e 6116
4b3a9526
VS		 6117 assert_vblank_disabled(crtc);
6118 drm_crtc_vblank_on(crtc);
6119
f9b61ff6
DV		 6120 for_each_encoder_on_crtc(dev, crtc, encoder)
6121 encoder->enable(encoder);
0b8765c6 6122}
79e53945 6123
87476d63
DV		 6124static void i9xx_pfit_disable(struct intel_crtc *crtc)
6125{
6126 struct drm_device *dev = crtc->base.dev;
6127 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6128
6e3c9717 6129 if (!crtc->config->gmch_pfit.control)
328d8e82 6130 return;
87476d63 6131
328d8e82 6132 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6133
328d8e82
DV		 6134 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6135 I915_READ(PFIT_CONTROL));
6136 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6137}
6138
0b8765c6
JB		 6139static void i9xx_crtc_disable(struct drm_crtc *crtc)
6140{
6141 struct drm_device *dev = crtc->dev;
6142 struct drm_i915_private *dev_priv = dev->dev_private;
6143 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6144 struct intel_encoder *encoder;
0b8765c6 6145 int pipe = intel_crtc->pipe;
ef9c3aee 6146
6304cd91
VS		 6147 /*
6148 * On gen2 planes are double buffered but the pipe isn't, so we must
6149 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6150 * We also need to wait on all gmch platforms because of the
6151 * self-refresh mode constraint explained above.
6304cd91 6152 */
564ed191 6153 intel_wait_for_vblank(dev, pipe);
6304cd91 6154
4b3a9526
VS		 6155 for_each_encoder_on_crtc(dev, crtc, encoder)
6156 encoder->disable(encoder);
6157
f9b61ff6
DV		 6158 drm_crtc_vblank_off(crtc);
6159 assert_vblank_disabled(crtc);
6160
575f7ab7 6161 intel_disable_pipe(intel_crtc);
24a1f16d 6162
87476d63 6163 i9xx_pfit_disable(intel_crtc);
24a1f16d 6164
89b667f8
JB		 6165 for_each_encoder_on_crtc(dev, crtc, encoder)
6166 if (encoder->post_disable)
6167 encoder->post_disable(encoder);
6168
409ee761 6169 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6170 if (IS_CHERRYVIEW(dev))
6171 chv_disable_pll(dev_priv, pipe);
6172 else if (IS_VALLEYVIEW(dev))
6173 vlv_disable_pll(dev_priv, pipe);
6174 else
1c4e0274 6175 i9xx_disable_pll(intel_crtc);
076ed3b2 6176 }
0b8765c6 6177
4a3436e8 6178 if (!IS_GEN2(dev))
a72e4c9f 6179 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
e4ca0612
PJ		 6180
6181 intel_crtc->active = false;
6182 intel_update_watermarks(crtc);
0b8765c6
JB		 6183}
6184
b17d48e2
ML		 6185static void intel_crtc_disable_noatomic(struct drm_crtc *crtc)
6186{
6187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6188 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
6189 enum intel_display_power_domain domain;
6190 unsigned long domains;
6191
6192 if (!intel_crtc->active)
6193 return;
6194
a539205a
ML		 6195 if (to_intel_plane_state(crtc->primary->state)->visible) {
6196 intel_crtc_wait_for_pending_flips(crtc);
6197 intel_pre_disable_primary(crtc);
6198 }
6199
d032ffa0 6200 intel_crtc_disable_planes(crtc, crtc->state->plane_mask);
b17d48e2
ML		 6201 dev_priv->display.crtc_disable(crtc);
6202
6203 domains = intel_crtc->enabled_power_domains;
6204 for_each_power_domain(domain, domains)
6205 intel_display_power_put(dev_priv, domain);
6206 intel_crtc->enabled_power_domains = 0;
6207}
6208
6b72d486
ML		 6209/*
6210 * turn all crtc's off, but do not adjust state
6211 * This has to be paired with a call to intel_modeset_setup_hw_state.
6212 */
9716c691 6213void intel_display_suspend(struct drm_device *dev)
ee7b9f93 6214{
6b72d486
ML		 6215 struct drm_crtc *crtc;
6216
b17d48e2
ML		 6217 for_each_crtc(dev, crtc)
6218 intel_crtc_disable_noatomic(crtc);
ee7b9f93
JB		 6219}
6220
b04c5bd6 6221/* Master function to enable/disable CRTC and corresponding power wells */
5da76e94 6222int intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 6223{
6224 struct drm_device *dev = crtc->dev;
5da76e94
ML		 6225 struct drm_mode_config *config = &dev->mode_config;
6226 struct drm_modeset_acquire_ctx *ctx = config->acquire_ctx;
0e572fe7 6227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5da76e94
ML		 6228 struct intel_crtc_state *pipe_config;
6229 struct drm_atomic_state *state;
6230 int ret;
976f8a20 6231
1b509259 6232 if (enable == intel_crtc->active)
5da76e94 6233 return 0;
0e572fe7 6234
1b509259 6235 if (enable && !crtc->state->enable)
5da76e94 6236 return 0;
1b509259 6237
5da76e94
ML		 6238 /* this function should be called with drm_modeset_lock_all for now */
6239 if (WARN_ON(!ctx))
6240 return -EIO;
6241 lockdep_assert_held(&ctx->ww_ctx);
1b509259 6242
5da76e94
ML		 6243 state = drm_atomic_state_alloc(dev);
6244 if (WARN_ON(!state))
6245 return -ENOMEM;
1b509259 6246
5da76e94
ML		 6247 state->acquire_ctx = ctx;
6248 state->allow_modeset = true;
6249
6250 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
6251 if (IS_ERR(pipe_config)) {
6252 ret = PTR_ERR(pipe_config);
6253 goto err;
0e572fe7 6254 }
5da76e94
ML		 6255 pipe_config->base.active = enable;
6256
6257 ret = intel_set_mode(state);
6258 if (!ret)
6259 return ret;
6260
6261err:
6262 DRM_ERROR("Updating crtc active failed with %i\n", ret);
6263 drm_atomic_state_free(state);
6264 return ret;
b04c5bd6
BF		 6265}
6266
6267/**
6268 * Sets the power management mode of the pipe and plane.
6269 */
6270void intel_crtc_update_dpms(struct drm_crtc *crtc)
6271{
6272 struct drm_device *dev = crtc->dev;
6273 struct intel_encoder *intel_encoder;
6274 bool enable = false;
6275
6276 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6277 enable |= intel_encoder->connectors_active;
6278
6279 intel_crtc_control(crtc, enable);
cdd59983
CW		 6280}
6281
ea5b213a 6282void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6283{
4ef69c7a 6284 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6285
ea5b213a
CW		 6286 drm_encoder_cleanup(encoder);
6287 kfree(intel_encoder);
7e7d76c3
JB		 6288}
6289
9237329d 6290/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6291 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6292 * state of the entire output pipe. */
9237329d 6293static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6294{
5ab432ef
DV		 6295 if (mode == DRM_MODE_DPMS_ON) {
6296 encoder->connectors_active = true;
6297
b2cabb0e 6298 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6299 } else {
6300 encoder->connectors_active = false;
6301
b2cabb0e 6302 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6303 }
79e53945
JB		 6304}
6305
0a91ca29
DV		 6306/* Cross check the actual hw state with our own modeset state tracking (and it's
6307 * internal consistency). */
b980514c 6308static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6309{
0a91ca29
DV		 6310 if (connector->get_hw_state(connector)) {
6311 struct intel_encoder *encoder = connector->encoder;
6312 struct drm_crtc *crtc;
6313 bool encoder_enabled;
6314 enum pipe pipe;
6315
6316 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6317 connector->base.base.id,
c23cc417 6318 connector->base.name);
0a91ca29 6319
0e32b39c
DA		 6320 /* there is no real hw state for MST connectors */
6321 if (connector->mst_port)
6322 return;
6323
e2c719b7 6324 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6325 "wrong connector dpms state\n");
e2c719b7 6326 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6327 "active connector not linked to encoder\n");
0a91ca29 6328
36cd7444 6329 if (encoder) {
e2c719b7 6330 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6331 "encoder->connectors_active not set\n");
6332
6333 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6334 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6335 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6336 return;
0a91ca29 6337
36cd7444 6338 crtc = encoder->base.crtc;
0a91ca29 6339
83d65738
MR		 6340 I915_STATE_WARN(!crtc->state->enable,
6341 "crtc not enabled\n");
e2c719b7
RC		 6342 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6343 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6344 "encoder active on the wrong pipe\n");
6345 }
0a91ca29 6346 }
79e53945
JB		 6347}
6348
08d9bc92
ACO		 6349int intel_connector_init(struct intel_connector *connector)
6350{
6351 struct drm_connector_state *connector_state;
6352
6353 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6354 if (!connector_state)
6355 return -ENOMEM;
6356
6357 connector->base.state = connector_state;
6358 return 0;
6359}
6360
6361struct intel_connector *intel_connector_alloc(void)
6362{
6363 struct intel_connector *connector;
6364
6365 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6366 if (!connector)
6367 return NULL;
6368
6369 if (intel_connector_init(connector) < 0) {
6370 kfree(connector);
6371 return NULL;
6372 }
6373
6374 return connector;
6375}
6376
5ab432ef
DV		 6377/* Even simpler default implementation, if there's really no special case to
6378 * consider. */
6379void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6380{
5ab432ef
DV		 6381 /* All the simple cases only support two dpms states. */
6382 if (mode != DRM_MODE_DPMS_ON)
6383 mode = DRM_MODE_DPMS_OFF;
d4270e57 6384
5ab432ef
DV		 6385 if (mode == connector->dpms)
6386 return;
6387
6388 connector->dpms = mode;
6389
6390 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6391 if (connector->encoder)
6392 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6393
b980514c 6394 intel_modeset_check_state(connector->dev);
79e53945
JB		 6395}
6396
f0947c37
DV		 6397/* Simple connector->get_hw_state implementation for encoders that support only
6398 * one connector and no cloning and hence the encoder state determines the state
6399 * of the connector. */
6400bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6401{
24929352 6402 enum pipe pipe = 0;
f0947c37 6403 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6404
f0947c37 6405 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6406}
6407
6d293983 6408static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6409{
6d293983
ACO		 6410 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6411 return crtc_state->fdi_lanes;
d272ddfa
VS		 6412
6413 return 0;
6414}
6415
6d293983 6416static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6417 struct intel_crtc_state *pipe_config)
1857e1da 6418{
6d293983
ACO		 6419 struct drm_atomic_state *state = pipe_config->base.state;
6420 struct intel_crtc *other_crtc;
6421 struct intel_crtc_state *other_crtc_state;
6422
1857e1da
DV		 6423 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6424 pipe_name(pipe), pipe_config->fdi_lanes);
6425 if (pipe_config->fdi_lanes > 4) {
6426 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6427 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6428 return -EINVAL;
1857e1da
DV		 6429 }
6430
bafb6553 6431 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6432 if (pipe_config->fdi_lanes > 2) {
6433 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6434 pipe_config->fdi_lanes);
6d293983 6435 return -EINVAL;
1857e1da 6436 } else {
6d293983 6437 return 0;
1857e1da
DV		 6438 }
6439 }
6440
6441 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6442 return 0;
1857e1da
DV		 6443
6444 /* Ivybridge 3 pipe is really complicated */
6445 switch (pipe) {
6446 case PIPE_A:
6d293983 6447 return 0;
1857e1da 6448 case PIPE_B:
6d293983
ACO		 6449 if (pipe_config->fdi_lanes <= 2)
6450 return 0;
6451
6452 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6453 other_crtc_state =
6454 intel_atomic_get_crtc_state(state, other_crtc);
6455 if (IS_ERR(other_crtc_state))
6456 return PTR_ERR(other_crtc_state);
6457
6458 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6459 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6460 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6461 return -EINVAL;
1857e1da 6462 }
6d293983 6463 return 0;
1857e1da 6464 case PIPE_C:
251cc67c
VS		 6465 if (pipe_config->fdi_lanes > 2) {
6466 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6467 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6468 return -EINVAL;
251cc67c 6469 }
6d293983
ACO		 6470
6471 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6472 other_crtc_state =
6473 intel_atomic_get_crtc_state(state, other_crtc);
6474 if (IS_ERR(other_crtc_state))
6475 return PTR_ERR(other_crtc_state);
6476
6477 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6478 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6479 return -EINVAL;
1857e1da 6480 }
6d293983 6481 return 0;
1857e1da
DV		 6482 default:
6483 BUG();
6484 }
6485}
6486
e29c22c0
DV		 6487#define RETRY 1
6488static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6489 struct intel_crtc_state *pipe_config)
877d48d5 6490{
1857e1da 6491 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6492 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6493 int lane, link_bw, fdi_dotclock, ret;
6494 bool needs_recompute = false;
877d48d5 6495
e29c22c0 6496retry:
877d48d5
DV		 6497 /* FDI is a binary signal running at ~2.7GHz, encoding
6498 * each output octet as 10 bits. The actual frequency
6499 * is stored as a divider into a 100MHz clock, and the
6500 * mode pixel clock is stored in units of 1KHz.
6501 * Hence the bw of each lane in terms of the mode signal
6502 * is:
6503 */
6504 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6505
241bfc38 6506 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6507
2bd89a07 6508 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6509 pipe_config->pipe_bpp);
6510
6511 pipe_config->fdi_lanes = lane;
6512
2bd89a07 6513 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6514 link_bw, &pipe_config->fdi_m_n);
1857e1da 6515
6d293983
ACO		 6516 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6517 intel_crtc->pipe, pipe_config);
6518 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6519 pipe_config->pipe_bpp -= 2*3;
6520 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6521 pipe_config->pipe_bpp);
6522 needs_recompute = true;
6523 pipe_config->bw_constrained = true;
6524
6525 goto retry;
6526 }
6527
6528 if (needs_recompute)
6529 return RETRY;
6530
6d293983 6531 return ret;
877d48d5
DV		 6532}
6533
8cfb3407
VS		 6534static bool pipe_config_supports_ips(struct drm_i915_private *dev_priv,
6535 struct intel_crtc_state *pipe_config)
6536{
6537 if (pipe_config->pipe_bpp > 24)
6538 return false;
6539
6540 /* HSW can handle pixel rate up to cdclk? */
6541 if (IS_HASWELL(dev_priv->dev))
6542 return true;
6543
6544 /*
b432e5cf
VS		 6545 * We compare against max which means we must take
6546 * the increased cdclk requirement into account when
6547 * calculating the new cdclk.
6548 *
6549 * Should measure whether using a lower cdclk w/o IPS
8cfb3407
VS		 6550 */
6551 return ilk_pipe_pixel_rate(pipe_config) <=
6552 dev_priv->max_cdclk_freq * 95 / 100;
6553}
6554
42db64ef 6555static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6556 struct intel_crtc_state *pipe_config)
42db64ef 6557{
8cfb3407
VS		 6558 struct drm_device *dev = crtc->base.dev;
6559 struct drm_i915_private *dev_priv = dev->dev_private;
6560
d330a953 6561 pipe_config->ips_enabled = i915.enable_ips &&
8cfb3407
VS		 6562 hsw_crtc_supports_ips(crtc) &&
6563 pipe_config_supports_ips(dev_priv, pipe_config);
42db64ef
PZ		 6564}
6565
a43f6e0f 6566static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6567 struct intel_crtc_state *pipe_config)
79e53945 6568{
a43f6e0f 6569 struct drm_device *dev = crtc->base.dev;
8bd31e67 6570 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6571 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 6572
ad3a4479 6573 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6574 if (INTEL_INFO(dev)->gen < 4) {
44913155 6575 int clock_limit = dev_priv->max_cdclk_freq;
cf532bb2
VS		 6576
6577 /*
6578 * Enable pixel doubling when the dot clock
6579 * is > 90% of the (display) core speed.
6580 *
b397c96b
VS		 6581 * GDG double wide on either pipe,
6582 * otherwise pipe A only.
cf532bb2 6583 */
b397c96b 6584 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6585 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6586 clock_limit *= 2;
cf532bb2 6587 pipe_config->double_wide = true;
ad3a4479
VS		 6588 }
6589
241bfc38 6590 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6591 return -EINVAL;
2c07245f 6592 }
89749350 6593
1d1d0e27
VS		 6594 /*
6595 * Pipe horizontal size must be even in:
6596 * - DVO ganged mode
6597 * - LVDS dual channel mode
6598 * - Double wide pipe
6599 */
a93e255f 6600 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6601 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6602 pipe_config->pipe_src_w &= ~1;
6603
8693a824
DL		 6604 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6605 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6606 */
6607 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6608 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6609 return -EINVAL;
44f46b42 6610
f5adf94e 6611 if (HAS_IPS(dev))
a43f6e0f
DV		 6612 hsw_compute_ips_config(crtc, pipe_config);
6613
877d48d5 6614 if (pipe_config->has_pch_encoder)
a43f6e0f 6615 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6616
cf5a15be 6617 return 0;
79e53945
JB		 6618}
6619
1652d19e
VS		 6620static int skylake_get_display_clock_speed(struct drm_device *dev)
6621{
6622 struct drm_i915_private *dev_priv = to_i915(dev);
6623 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6624 uint32_t cdctl = I915_READ(CDCLK_CTL);
6625 uint32_t linkrate;
6626
414355a7 6627 if (!(lcpll1 & LCPLL_PLL_ENABLE))
1652d19e 6628 return 24000; /* 24MHz is the cd freq with NSSC ref */
1652d19e
VS		 6629
6630 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6631 return 540000;
6632
6633 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6634 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6635
71cd8423
DL		 6636 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6637 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6638 /* vco 8640 */
6639 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6640 case CDCLK_FREQ_450_432:
6641 return 432000;
6642 case CDCLK_FREQ_337_308:
6643 return 308570;
6644 case CDCLK_FREQ_675_617:
6645 return 617140;
6646 default:
6647 WARN(1, "Unknown cd freq selection\n");
6648 }
6649 } else {
6650 /* vco 8100 */
6651 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6652 case CDCLK_FREQ_450_432:
6653 return 450000;
6654 case CDCLK_FREQ_337_308:
6655 return 337500;
6656 case CDCLK_FREQ_675_617:
6657 return 675000;
6658 default:
6659 WARN(1, "Unknown cd freq selection\n");
6660 }
6661 }
6662
6663 /* error case, do as if DPLL0 isn't enabled */
6664 return 24000;
6665}
6666
acd3f3d3
BP		 6667static int broxton_get_display_clock_speed(struct drm_device *dev)
6668{
6669 struct drm_i915_private *dev_priv = to_i915(dev);
6670 uint32_t cdctl = I915_READ(CDCLK_CTL);
6671 uint32_t pll_ratio = I915_READ(BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
6672 uint32_t pll_enab = I915_READ(BXT_DE_PLL_ENABLE);
6673 int cdclk;
6674
6675 if (!(pll_enab & BXT_DE_PLL_PLL_ENABLE))
6676 return 19200;
6677
6678 cdclk = 19200 * pll_ratio / 2;
6679
6680 switch (cdctl & BXT_CDCLK_CD2X_DIV_SEL_MASK) {
6681 case BXT_CDCLK_CD2X_DIV_SEL_1:
6682 return cdclk; /* 576MHz or 624MHz */
6683 case BXT_CDCLK_CD2X_DIV_SEL_1_5:
6684 return cdclk * 2 / 3; /* 384MHz */
6685 case BXT_CDCLK_CD2X_DIV_SEL_2:
6686 return cdclk / 2; /* 288MHz */
6687 case BXT_CDCLK_CD2X_DIV_SEL_4:
6688 return cdclk / 4; /* 144MHz */
6689 }
6690
6691 /* error case, do as if DE PLL isn't enabled */
6692 return 19200;
6693}
6694
1652d19e
VS		 6695static int broadwell_get_display_clock_speed(struct drm_device *dev)
6696{
6697 struct drm_i915_private *dev_priv = dev->dev_private;
6698 uint32_t lcpll = I915_READ(LCPLL_CTL);
6699 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6700
6701 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6702 return 800000;
6703 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6704 return 450000;
6705 else if (freq == LCPLL_CLK_FREQ_450)
6706 return 450000;
6707 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6708 return 540000;
6709 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6710 return 337500;
6711 else
6712 return 675000;
6713}
6714
6715static int haswell_get_display_clock_speed(struct drm_device *dev)
6716{
6717 struct drm_i915_private *dev_priv = dev->dev_private;
6718 uint32_t lcpll = I915_READ(LCPLL_CTL);
6719 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6720
6721 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6722 return 800000;
6723 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6724 return 450000;
6725 else if (freq == LCPLL_CLK_FREQ_450)
6726 return 450000;
6727 else if (IS_HSW_ULT(dev))
6728 return 337500;
6729 else
6730 return 540000;
79e53945
JB		 6731}
6732
25eb05fc
JB		 6733static int valleyview_get_display_clock_speed(struct drm_device *dev)
6734{
d197b7d3 6735 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6736 u32 val;
6737 int divider;
6738
6bcda4f0
VS		 6739 if (dev_priv->hpll_freq == 0)
6740 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6741
a580516d 6742 mutex_lock(&dev_priv->sb_lock);
d197b7d3 6743 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
a580516d 6744 mutex_unlock(&dev_priv->sb_lock);
d197b7d3
VS		 6745
6746 divider = val & DISPLAY_FREQUENCY_VALUES;
6747
7d007f40
VS		 6748 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6749 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6750 "cdclk change in progress\n");
6751
6bcda4f0 6752 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6753}
6754
b37a6434
VS		 6755static int ilk_get_display_clock_speed(struct drm_device *dev)
6756{
6757 return 450000;
6758}
6759
e70236a8
JB		 6760static int i945_get_display_clock_speed(struct drm_device *dev)
6761{
6762 return 400000;
6763}
79e53945 6764
e70236a8 6765static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6766{
e907f170 6767 return 333333;
e70236a8 6768}
79e53945 6769
e70236a8
JB		 6770static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6771{
6772 return 200000;
6773}
79e53945 6774
257a7ffc
DV		 6775static int pnv_get_display_clock_speed(struct drm_device *dev)
6776{
6777 u16 gcfgc = 0;
6778
6779 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6780
6781 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6782 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6783 return 266667;
257a7ffc 6784 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6785 return 333333;
257a7ffc 6786 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6787 return 444444;
257a7ffc
DV		 6788 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6789 return 200000;
6790 default:
6791 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6792 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6793 return 133333;
257a7ffc 6794 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6795 return 166667;
257a7ffc
DV		 6796 }
6797}
6798
e70236a8
JB		 6799static int i915gm_get_display_clock_speed(struct drm_device *dev)
6800{
6801 u16 gcfgc = 0;
79e53945 6802
e70236a8
JB		 6803 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6804
6805 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6806 return 133333;
e70236a8
JB		 6807 else {
6808 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6809 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6810 return 333333;
e70236a8
JB		 6811 default:
6812 case GC_DISPLAY_CLOCK_190_200_MHZ:
6813 return 190000;
79e53945 6814 }
e70236a8
JB		 6815 }
6816}
6817
6818static int i865_get_display_clock_speed(struct drm_device *dev)
6819{
e907f170 6820 return 266667;
e70236a8
JB		 6821}
6822
1b1d2716 6823static int i85x_get_display_clock_speed(struct drm_device *dev)
e70236a8
JB		 6824{
6825 u16 hpllcc = 0;
1b1d2716 6826
65cd2b3f
VS		 6827 /*
6828 * 852GM/852GMV only supports 133 MHz and the HPLLCC
6829 * encoding is different :(
6830 * FIXME is this the right way to detect 852GM/852GMV?
6831 */
6832 if (dev->pdev->revision == 0x1)
6833 return 133333;
6834
1b1d2716
VS		 6835 pci_bus_read_config_word(dev->pdev->bus,
6836 PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
6837
e70236a8
JB		 6838 /* Assume that the hardware is in the high speed state. This
6839 * should be the default.
6840 */
6841 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6842 case GC_CLOCK_133_200:
1b1d2716 6843 case GC_CLOCK_133_200_2:
e70236a8
JB		 6844 case GC_CLOCK_100_200:
6845 return 200000;
6846 case GC_CLOCK_166_250:
6847 return 250000;
6848 case GC_CLOCK_100_133:
e907f170 6849 return 133333;
1b1d2716
VS		 6850 case GC_CLOCK_133_266:
6851 case GC_CLOCK_133_266_2:
6852 case GC_CLOCK_166_266:
6853 return 266667;
e70236a8 6854 }
79e53945 6855
e70236a8
JB		 6856 /* Shouldn't happen */
6857 return 0;
6858}
79e53945 6859
e70236a8
JB		 6860static int i830_get_display_clock_speed(struct drm_device *dev)
6861{
e907f170 6862 return 133333;
79e53945
JB		 6863}
6864
34edce2f
VS		 6865static unsigned int intel_hpll_vco(struct drm_device *dev)
6866{
6867 struct drm_i915_private *dev_priv = dev->dev_private;
6868 static const unsigned int blb_vco[8] = {
6869 [0] = 3200000,
6870 [1] = 4000000,
6871 [2] = 5333333,
6872 [3] = 4800000,
6873 [4] = 6400000,
6874 };
6875 static const unsigned int pnv_vco[8] = {
6876 [0] = 3200000,
6877 [1] = 4000000,
6878 [2] = 5333333,
6879 [3] = 4800000,
6880 [4] = 2666667,
6881 };
6882 static const unsigned int cl_vco[8] = {
6883 [0] = 3200000,
6884 [1] = 4000000,
6885 [2] = 5333333,
6886 [3] = 6400000,
6887 [4] = 3333333,
6888 [5] = 3566667,
6889 [6] = 4266667,
6890 };
6891 static const unsigned int elk_vco[8] = {
6892 [0] = 3200000,
6893 [1] = 4000000,
6894 [2] = 5333333,
6895 [3] = 4800000,
6896 };
6897 static const unsigned int ctg_vco[8] = {
6898 [0] = 3200000,
6899 [1] = 4000000,
6900 [2] = 5333333,
6901 [3] = 6400000,
6902 [4] = 2666667,
6903 [5] = 4266667,
6904 };
6905 const unsigned int *vco_table;
6906 unsigned int vco;
6907 uint8_t tmp = 0;
6908
6909 /* FIXME other chipsets? */
6910 if (IS_GM45(dev))
6911 vco_table = ctg_vco;
6912 else if (IS_G4X(dev))
6913 vco_table = elk_vco;
6914 else if (IS_CRESTLINE(dev))
6915 vco_table = cl_vco;
6916 else if (IS_PINEVIEW(dev))
6917 vco_table = pnv_vco;
6918 else if (IS_G33(dev))
6919 vco_table = blb_vco;
6920 else
6921 return 0;
6922
6923 tmp = I915_READ(IS_MOBILE(dev) ? HPLLVCO_MOBILE : HPLLVCO);
6924
6925 vco = vco_table[tmp & 0x7];
6926 if (vco == 0)
6927 DRM_ERROR("Bad HPLL VCO (HPLLVCO=0x%02x)\n", tmp);
6928 else
6929 DRM_DEBUG_KMS("HPLL VCO %u kHz\n", vco);
6930
6931 return vco;
6932}
6933
6934static int gm45_get_display_clock_speed(struct drm_device *dev)
6935{
6936 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6937 uint16_t tmp = 0;
6938
6939 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6940
6941 cdclk_sel = (tmp >> 12) & 0x1;
6942
6943 switch (vco) {
6944 case 2666667:
6945 case 4000000:
6946 case 5333333:
6947 return cdclk_sel ? 333333 : 222222;
6948 case 3200000:
6949 return cdclk_sel ? 320000 : 228571;
6950 default:
6951 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n", vco, tmp);
6952 return 222222;
6953 }
6954}
6955
6956static int i965gm_get_display_clock_speed(struct drm_device *dev)
6957{
6958 static const uint8_t div_3200[] = { 16, 10, 8 };
6959 static const uint8_t div_4000[] = { 20, 12, 10 };
6960 static const uint8_t div_5333[] = { 24, 16, 14 };
6961 const uint8_t *div_table;
6962 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
6963 uint16_t tmp = 0;
6964
6965 pci_read_config_word(dev->pdev, GCFGC, &tmp);
6966
6967 cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
6968
6969 if (cdclk_sel >= ARRAY_SIZE(div_3200))
6970 goto fail;
6971
6972 switch (vco) {
6973 case 3200000:
6974 div_table = div_3200;
6975 break;
6976 case 4000000:
6977 div_table = div_4000;
6978 break;
6979 case 5333333:
6980 div_table = div_5333;
6981 break;
6982 default:
6983 goto fail;
6984 }
6985
6986 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
6987
caf4e252 6988fail:
34edce2f
VS		 6989 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n", vco, tmp);
6990 return 200000;
6991}
6992
6993static int g33_get_display_clock_speed(struct drm_device *dev)
6994{
6995 static const uint8_t div_3200[] = { 12, 10, 8, 7, 5, 16 };
6996 static const uint8_t div_4000[] = { 14, 12, 10, 8, 6, 20 };
6997 static const uint8_t div_4800[] = { 20, 14, 12, 10, 8, 24 };
6998 static const uint8_t div_5333[] = { 20, 16, 12, 12, 8, 28 };
6999 const uint8_t *div_table;
7000 unsigned int cdclk_sel, vco = intel_hpll_vco(dev);
7001 uint16_t tmp = 0;
7002
7003 pci_read_config_word(dev->pdev, GCFGC, &tmp);
7004
7005 cdclk_sel = (tmp >> 4) & 0x7;
7006
7007 if (cdclk_sel >= ARRAY_SIZE(div_3200))
7008 goto fail;
7009
7010 switch (vco) {
7011 case 3200000:
7012 div_table = div_3200;
7013 break;
7014 case 4000000:
7015 div_table = div_4000;
7016 break;
7017 case 4800000:
7018 div_table = div_4800;
7019 break;
7020 case 5333333:
7021 div_table = div_5333;
7022 break;
7023 default:
7024 goto fail;
7025 }
7026
7027 return DIV_ROUND_CLOSEST(vco, div_table[cdclk_sel]);
7028
caf4e252 7029fail:
34edce2f
VS		 7030 DRM_ERROR("Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n", vco, tmp);
7031 return 190476;
7032}
7033
2c07245f 7034static void
a65851af 7035intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 7036{
a65851af
VS		 7037 while (*num > DATA_LINK_M_N_MASK ||
7038 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 7039 *num >>= 1;
7040 *den >>= 1;
7041 }
7042}
7043
a65851af
VS		 7044static void compute_m_n(unsigned int m, unsigned int n,
7045 uint32_t *ret_m, uint32_t *ret_n)
7046{
7047 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
7048 *ret_m = div_u64((uint64_t) m * *ret_n, n);
7049 intel_reduce_m_n_ratio(ret_m, ret_n);
7050}
7051
e69d0bc1
DV		 7052void
7053intel_link_compute_m_n(int bits_per_pixel, int nlanes,
7054 int pixel_clock, int link_clock,
7055 struct intel_link_m_n *m_n)
2c07245f 7056{
e69d0bc1 7057 m_n->tu = 64;
a65851af
VS		 7058
7059 compute_m_n(bits_per_pixel * pixel_clock,
7060 link_clock * nlanes * 8,
7061 &m_n->gmch_m, &m_n->gmch_n);
7062
7063 compute_m_n(pixel_clock, link_clock,
7064 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 7065}
7066
a7615030
CW		 7067static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
7068{
d330a953
JN		 7069 if (i915.panel_use_ssc >= 0)
7070 return i915.panel_use_ssc != 0;
41aa3448 7071 return dev_priv->vbt.lvds_use_ssc
435793df 7072 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 7073}
7074
a93e255f
ACO		 7075static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
7076 int num_connectors)
c65d77d8 7077{
a93e255f 7078 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 7079 struct drm_i915_private *dev_priv = dev->dev_private;
7080 int refclk;
7081
a93e255f
ACO		 7082 WARN_ON(!crtc_state->base.state);
7083
5ab7b0b7 7084 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 7085 refclk = 100000;
a93e255f 7086 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 7087 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 7088 refclk = dev_priv->vbt.lvds_ssc_freq;
7089 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 7090 } else if (!IS_GEN2(dev)) {
7091 refclk = 96000;
7092 } else {
7093 refclk = 48000;
7094 }
7095
7096 return refclk;
7097}
7098
7429e9d4 7099static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 7100{
7df00d7a 7101 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 7102}
f47709a9 7103
7429e9d4
DV		 7104static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
7105{
7106 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 7107}
7108
f47709a9 7109static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 7110 struct intel_crtc_state *crtc_state,
a7516a05
JB		 7111 intel_clock_t *reduced_clock)
7112{
f47709a9 7113 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 7114 u32 fp, fp2 = 0;
7115
7116 if (IS_PINEVIEW(dev)) {
190f68c5 7117 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7118 if (reduced_clock)
7429e9d4 7119 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 7120 } else {
190f68c5 7121 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 7122 if (reduced_clock)
7429e9d4 7123 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 7124 }
7125
190f68c5 7126 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 7127
f47709a9 7128 crtc->lowfreq_avail = false;
a93e255f 7129 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 7130 reduced_clock) {
190f68c5 7131 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 7132 crtc->lowfreq_avail = true;
a7516a05 7133 } else {
190f68c5 7134 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 7135 }
7136}
7137
5e69f97f
CML		 7138static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
7139 pipe)
89b667f8
JB		 7140{
7141 u32 reg_val;
7142
7143 /*
7144 * PLLB opamp always calibrates to max value of 0x3f, force enable it
7145 * and set it to a reasonable value instead.
7146 */
ab3c759a 7147 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 7148 reg_val &= 0xffffff00;
7149 reg_val |= 0x00000030;
ab3c759a 7150 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7151
ab3c759a 7152 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7153 reg_val &= 0x8cffffff;
7154 reg_val = 0x8c000000;
ab3c759a 7155 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 7156
ab3c759a 7157 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 7158 reg_val &= 0xffffff00;
ab3c759a 7159 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 7160
ab3c759a 7161 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 7162 reg_val &= 0x00ffffff;
7163 reg_val |= 0xb0000000;
ab3c759a 7164 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 7165}
7166
b551842d
DV		 7167static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
7168 struct intel_link_m_n *m_n)
7169{
7170 struct drm_device *dev = crtc->base.dev;
7171 struct drm_i915_private *dev_priv = dev->dev_private;
7172 int pipe = crtc->pipe;
7173
e3b95f1e
DV		 7174 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7175 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7176 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7177 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7178}
7179
7180static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7181 struct intel_link_m_n *m_n,
7182 struct intel_link_m_n *m2_n2)
b551842d
DV		 7183{
7184 struct drm_device *dev = crtc->base.dev;
7185 struct drm_i915_private *dev_priv = dev->dev_private;
7186 int pipe = crtc->pipe;
6e3c9717 7187 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7188
7189 if (INTEL_INFO(dev)->gen >= 5) {
7190 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7191 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7192 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7193 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7194 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7195 * for gen < 8) and if DRRS is supported (to make sure the
7196 * registers are not unnecessarily accessed).
7197 */
44395bfe 7198 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7199 crtc->config->has_drrs) {
f769cd24
VK		 7200 I915_WRITE(PIPE_DATA_M2(transcoder),
7201 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7202 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7203 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7204 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7205 }
b551842d 7206 } else {
e3b95f1e
DV		 7207 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7208 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7209 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7210 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7211 }
7212}
7213
fe3cd48d 7214void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7215{
fe3cd48d
R		 7216 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7217
7218 if (m_n == M1_N1) {
7219 dp_m_n = &crtc->config->dp_m_n;
7220 dp_m2_n2 = &crtc->config->dp_m2_n2;
7221 } else if (m_n == M2_N2) {
7222
7223 /*
7224 * M2_N2 registers are not supported. Hence m2_n2 divider value
7225 * needs to be programmed into M1_N1.
7226 */
7227 dp_m_n = &crtc->config->dp_m2_n2;
7228 } else {
7229 DRM_ERROR("Unsupported divider value\n");
7230 return;
7231 }
7232
6e3c9717
ACO		 7233 if (crtc->config->has_pch_encoder)
7234 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7235 else
fe3cd48d 7236 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7237}
7238
251ac862
DV		 7239static void vlv_compute_dpll(struct intel_crtc *crtc,
7240 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7241{
7242 u32 dpll, dpll_md;
7243
7244 /*
7245 * Enable DPIO clock input. We should never disable the reference
7246 * clock for pipe B, since VGA hotplug / manual detection depends
7247 * on it.
7248 */
60bfe44f
VS		 7249 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REF_CLK_ENABLE_VLV |
7250 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_REF_CLK_VLV;
bdd4b6a6
DV		 7251 /* We should never disable this, set it here for state tracking */
7252 if (crtc->pipe == PIPE_B)
7253 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7254 dpll |= DPLL_VCO_ENABLE;
d288f65f 7255 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7256
d288f65f 7257 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7258 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7259 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7260}
7261
d288f65f 7262static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7263 const struct intel_crtc_state *pipe_config)
a0c4da24 7264{
f47709a9 7265 struct drm_device *dev = crtc->base.dev;
a0c4da24 7266 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7267 int pipe = crtc->pipe;
bdd4b6a6 7268 u32 mdiv;
a0c4da24 7269 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7270 u32 coreclk, reg_val;
a0c4da24 7271
a580516d 7272 mutex_lock(&dev_priv->sb_lock);
09153000 7273
d288f65f
VS		 7274 bestn = pipe_config->dpll.n;
7275 bestm1 = pipe_config->dpll.m1;
7276 bestm2 = pipe_config->dpll.m2;
7277 bestp1 = pipe_config->dpll.p1;
7278 bestp2 = pipe_config->dpll.p2;
a0c4da24 7279
89b667f8
JB		 7280 /* See eDP HDMI DPIO driver vbios notes doc */
7281
7282 /* PLL B needs special handling */
bdd4b6a6 7283 if (pipe == PIPE_B)
5e69f97f 7284 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7285
7286 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7287 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7288
7289 /* Disable target IRef on PLL */
ab3c759a 7290 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7291 reg_val &= 0x00ffffff;
ab3c759a 7292 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7293
7294 /* Disable fast lock */
ab3c759a 7295 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7296
7297 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7298 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7299 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7300 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7301 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7302
7303 /*
7304 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7305 * but we don't support that).
7306 * Note: don't use the DAC post divider as it seems unstable.
7307 */
7308 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7309 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7310
a0c4da24 7311 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7312 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7313
89b667f8 7314 /* Set HBR and RBR LPF coefficients */
d288f65f 7315 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7316 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7317 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7318 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7319 0x009f0003);
89b667f8 7320 else
ab3c759a 7321 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7322 0x00d0000f);
7323
681a8504 7324 if (pipe_config->has_dp_encoder) {
89b667f8 7325 /* Use SSC source */
bdd4b6a6 7326 if (pipe == PIPE_A)
ab3c759a 7327 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7328 0x0df40000);
7329 else
ab3c759a 7330 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7331 0x0df70000);
7332 } else { /* HDMI or VGA */
7333 /* Use bend source */
bdd4b6a6 7334 if (pipe == PIPE_A)
ab3c759a 7335 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7336 0x0df70000);
7337 else
ab3c759a 7338 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7339 0x0df40000);
7340 }
a0c4da24 7341
ab3c759a 7342 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7343 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7344 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7345 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7346 coreclk |= 0x01000000;
ab3c759a 7347 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7348
ab3c759a 7349 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
a580516d 7350 mutex_unlock(&dev_priv->sb_lock);
a0c4da24
JB		 7351}
7352
251ac862
DV		 7353static void chv_compute_dpll(struct intel_crtc *crtc,
7354 struct intel_crtc_state *pipe_config)
1ae0d137 7355{
60bfe44f
VS		 7356 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV |
7357 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
1ae0d137
VS		 7358 DPLL_VCO_ENABLE;
7359 if (crtc->pipe != PIPE_A)
d288f65f 7360 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7361
d288f65f
VS		 7362 pipe_config->dpll_hw_state.dpll_md =
7363 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7364}
7365
d288f65f 7366static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7367 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7368{
7369 struct drm_device *dev = crtc->base.dev;
7370 struct drm_i915_private *dev_priv = dev->dev_private;
7371 int pipe = crtc->pipe;
7372 int dpll_reg = DPLL(crtc->pipe);
7373 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7374 u32 loopfilter, tribuf_calcntr;
9d556c99 7375 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7376 u32 dpio_val;
9cbe40c1 7377 int vco;
9d556c99 7378
d288f65f
VS		 7379 bestn = pipe_config->dpll.n;
7380 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7381 bestm1 = pipe_config->dpll.m1;
7382 bestm2 = pipe_config->dpll.m2 >> 22;
7383 bestp1 = pipe_config->dpll.p1;
7384 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7385 vco = pipe_config->dpll.vco;
a945ce7e 7386 dpio_val = 0;
9cbe40c1 7387 loopfilter = 0;
9d556c99
CML		 7388
7389 /*
7390 * Enable Refclk and SSC
7391 */
a11b0703 7392 I915_WRITE(dpll_reg,
d288f65f 7393 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703 7394
a580516d 7395 mutex_lock(&dev_priv->sb_lock);
9d556c99 7396
9d556c99
CML		 7397 /* p1 and p2 divider */
7398 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7399 5 << DPIO_CHV_S1_DIV_SHIFT |
7400 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7401 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7402 1 << DPIO_CHV_K_DIV_SHIFT);
7403
7404 /* Feedback post-divider - m2 */
7405 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7406
7407 /* Feedback refclk divider - n and m1 */
7408 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7409 DPIO_CHV_M1_DIV_BY_2 |
7410 1 << DPIO_CHV_N_DIV_SHIFT);
7411
7412 /* M2 fraction division */
a945ce7e
VP		 7413 if (bestm2_frac)
7414 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7415
7416 /* M2 fraction division enable */
a945ce7e
VP		 7417 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7418 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7419 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7420 if (bestm2_frac)
7421 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7422 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7423
de3a0fde
VP		 7424 /* Program digital lock detect threshold */
7425 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7426 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7427 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7428 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7429 if (!bestm2_frac)
7430 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7431 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7432
9d556c99 7433 /* Loop filter */
9cbe40c1
VP		 7434 if (vco == 5400000) {
7435 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7436 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7437 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7438 tribuf_calcntr = 0x9;
7439 } else if (vco <= 6200000) {
7440 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7441 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7442 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7443 tribuf_calcntr = 0x9;
7444 } else if (vco <= 6480000) {
7445 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7446 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7447 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7448 tribuf_calcntr = 0x8;
7449 } else {
7450 /* Not supported. Apply the same limits as in the max case */
7451 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7452 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7453 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7454 tribuf_calcntr = 0;
7455 }
9d556c99
CML		 7456 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7457
968040b2 7458 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7459 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7460 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7461 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7462
9d556c99
CML		 7463 /* AFC Recal */
7464 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7465 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7466 DPIO_AFC_RECAL);
7467
a580516d 7468 mutex_unlock(&dev_priv->sb_lock);
9d556c99
CML		 7469}
7470
d288f65f
VS		 7471/**
7472 * vlv_force_pll_on - forcibly enable just the PLL
7473 * @dev_priv: i915 private structure
7474 * @pipe: pipe PLL to enable
7475 * @dpll: PLL configuration
7476 *
7477 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7478 * in cases where we need the PLL enabled even when @pipe is not going to
7479 * be enabled.
7480 */
7481void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7482 const struct dpll *dpll)
7483{
7484 struct intel_crtc *crtc =
7485 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7486 struct intel_crtc_state pipe_config = {
a93e255f 7487 .base.crtc = &crtc->base,
d288f65f
VS		 7488 .pixel_multiplier = 1,
7489 .dpll = *dpll,
7490 };
7491
7492 if (IS_CHERRYVIEW(dev)) {
251ac862 7493 chv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7494 chv_prepare_pll(crtc, &pipe_config);
7495 chv_enable_pll(crtc, &pipe_config);
7496 } else {
251ac862 7497 vlv_compute_dpll(crtc, &pipe_config);
d288f65f
VS		 7498 vlv_prepare_pll(crtc, &pipe_config);
7499 vlv_enable_pll(crtc, &pipe_config);
7500 }
7501}
7502
7503/**
7504 * vlv_force_pll_off - forcibly disable just the PLL
7505 * @dev_priv: i915 private structure
7506 * @pipe: pipe PLL to disable
7507 *
7508 * Disable the PLL for @pipe. To be used in cases where we need
7509 * the PLL enabled even when @pipe is not going to be enabled.
7510 */
7511void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7512{
7513 if (IS_CHERRYVIEW(dev))
7514 chv_disable_pll(to_i915(dev), pipe);
7515 else
7516 vlv_disable_pll(to_i915(dev), pipe);
7517}
7518
251ac862
DV		 7519static void i9xx_compute_dpll(struct intel_crtc *crtc,
7520 struct intel_crtc_state *crtc_state,
7521 intel_clock_t *reduced_clock,
7522 int num_connectors)
eb1cbe48 7523{
f47709a9 7524 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7525 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7526 u32 dpll;
7527 bool is_sdvo;
190f68c5 7528 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7529
190f68c5 7530 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7531
a93e255f
ACO		 7532 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7533 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7534
7535 dpll = DPLL_VGA_MODE_DIS;
7536
a93e255f 7537 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7538 dpll |= DPLLB_MODE_LVDS;
7539 else
7540 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7541
ef1b460d 7542 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7543 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7544 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7545 }
198a037f
DV		 7546
7547 if (is_sdvo)
4a33e48d 7548 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7549
190f68c5 7550 if (crtc_state->has_dp_encoder)
4a33e48d 7551 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7552
7553 /* compute bitmask from p1 value */
7554 if (IS_PINEVIEW(dev))
7555 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7556 else {
7557 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7558 if (IS_G4X(dev) && reduced_clock)
7559 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7560 }
7561 switch (clock->p2) {
7562 case 5:
7563 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7564 break;
7565 case 7:
7566 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7567 break;
7568 case 10:
7569 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7570 break;
7571 case 14:
7572 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7573 break;
7574 }
7575 if (INTEL_INFO(dev)->gen >= 4)
7576 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7577
190f68c5 7578 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7579 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7580 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7581 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7582 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7583 else
7584 dpll |= PLL_REF_INPUT_DREFCLK;
7585
7586 dpll |= DPLL_VCO_ENABLE;
190f68c5 7587 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7588
eb1cbe48 7589 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7590 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7591 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7592 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7593 }
7594}
7595
251ac862
DV		 7596static void i8xx_compute_dpll(struct intel_crtc *crtc,
7597 struct intel_crtc_state *crtc_state,
7598 intel_clock_t *reduced_clock,
7599 int num_connectors)
eb1cbe48 7600{
f47709a9 7601 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7602 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7603 u32 dpll;
190f68c5 7604 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7605
190f68c5 7606 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7607
eb1cbe48
DV		 7608 dpll = DPLL_VGA_MODE_DIS;
7609
a93e255f 7610 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7611 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7612 } else {
7613 if (clock->p1 == 2)
7614 dpll |= PLL_P1_DIVIDE_BY_TWO;
7615 else
7616 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7617 if (clock->p2 == 4)
7618 dpll |= PLL_P2_DIVIDE_BY_4;
7619 }
7620
a93e255f 7621 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7622 dpll |= DPLL_DVO_2X_MODE;
7623
a93e255f 7624 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7625 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7626 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7627 else
7628 dpll |= PLL_REF_INPUT_DREFCLK;
7629
7630 dpll |= DPLL_VCO_ENABLE;
190f68c5 7631 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7632}
7633
8a654f3b 7634static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7635{
7636 struct drm_device *dev = intel_crtc->base.dev;
7637 struct drm_i915_private *dev_priv = dev->dev_private;
7638 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7639 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7640 struct drm_display_mode *adjusted_mode =
6e3c9717 7641 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7642 uint32_t crtc_vtotal, crtc_vblank_end;
7643 int vsyncshift = 0;
4d8a62ea
DV		 7644
7645 /* We need to be careful not to changed the adjusted mode, for otherwise
7646 * the hw state checker will get angry at the mismatch. */
7647 crtc_vtotal = adjusted_mode->crtc_vtotal;
7648 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7649
609aeaca 7650 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7651 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7652 crtc_vtotal -= 1;
7653 crtc_vblank_end -= 1;
609aeaca 7654
409ee761 7655 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7656 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7657 else
7658 vsyncshift = adjusted_mode->crtc_hsync_start -
7659 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7660 if (vsyncshift < 0)
7661 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7662 }
7663
7664 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7665 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7666
fe2b8f9d 7667 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7668 (adjusted_mode->crtc_hdisplay - 1) |
7669 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7670 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7671 (adjusted_mode->crtc_hblank_start - 1) |
7672 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7673 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7674 (adjusted_mode->crtc_hsync_start - 1) |
7675 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7676
fe2b8f9d 7677 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7678 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7679 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7680 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7681 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7682 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7683 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7684 (adjusted_mode->crtc_vsync_start - 1) |
7685 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7686
b5e508d4
PZ		 7687 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7688 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7689 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7690 * bits. */
7691 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7692 (pipe == PIPE_B || pipe == PIPE_C))
7693 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7694
b0e77b9c
PZ		 7695 /* pipesrc controls the size that is scaled from, which should
7696 * always be the user's requested size.
7697 */
7698 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7699 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7700 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7701}
7702
1bd1bd80 7703static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7704 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7705{
7706 struct drm_device *dev = crtc->base.dev;
7707 struct drm_i915_private *dev_priv = dev->dev_private;
7708 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7709 uint32_t tmp;
7710
7711 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7712 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7713 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7714 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7715 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7716 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7717 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7718 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7719 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7720
7721 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7722 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7723 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7724 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7725 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7726 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7727 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7728 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7729 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7730
7731 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7732 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7733 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7734 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7735 }
7736
7737 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7738 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7739 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7740
2d112de7
ACO		 7741 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7742 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7743}
7744
f6a83288 7745void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7746 struct intel_crtc_state *pipe_config)
babea61d 7747{
2d112de7
ACO		 7748 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7749 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7750 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7751 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7752
2d112de7
ACO		 7753 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7754 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7755 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7756 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7757
2d112de7 7758 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7759
2d112de7
ACO		 7760 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7761 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7762}
7763
84b046f3
DV		 7764static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7765{
7766 struct drm_device *dev = intel_crtc->base.dev;
7767 struct drm_i915_private *dev_priv = dev->dev_private;
7768 uint32_t pipeconf;
7769
9f11a9e4 7770 pipeconf = 0;
84b046f3 7771
b6b5d049
VS		 7772 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7773 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7774 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7775
6e3c9717 7776 if (intel_crtc->config->double_wide)
cf532bb2 7777 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7778
ff9ce46e
DV		 7779 /* only g4x and later have fancy bpc/dither controls */
7780 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7781 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7782 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7783 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7784 PIPECONF_DITHER_TYPE_SP;
84b046f3 7785
6e3c9717 7786 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7787 case 18:
7788 pipeconf |= PIPECONF_6BPC;
7789 break;
7790 case 24:
7791 pipeconf |= PIPECONF_8BPC;
7792 break;
7793 case 30:
7794 pipeconf |= PIPECONF_10BPC;
7795 break;
7796 default:
7797 /* Case prevented by intel_choose_pipe_bpp_dither. */
7798 BUG();
84b046f3
DV		 7799 }
7800 }
7801
7802 if (HAS_PIPE_CXSR(dev)) {
7803 if (intel_crtc->lowfreq_avail) {
7804 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7805 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7806 } else {
7807 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7808 }
7809 }
7810
6e3c9717 7811 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7812 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7813 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7814 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7815 else
7816 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7817 } else
84b046f3
DV		 7818 pipeconf |= PIPECONF_PROGRESSIVE;
7819
6e3c9717 7820 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7821 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7822
84b046f3
DV		 7823 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7824 POSTING_READ(PIPECONF(intel_crtc->pipe));
7825}
7826
190f68c5
ACO		 7827static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7828 struct intel_crtc_state *crtc_state)
79e53945 7829{
c7653199 7830 struct drm_device *dev = crtc->base.dev;
79e53945 7831 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7832 int refclk, num_connectors = 0;
c329a4ec
DV		 7833 intel_clock_t clock;
7834 bool ok;
7835 bool is_dsi = false;
5eddb70b 7836 struct intel_encoder *encoder;
d4906093 7837 const intel_limit_t *limit;
55bb9992 7838 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7839 struct drm_connector *connector;
55bb9992
ACO		 7840 struct drm_connector_state *connector_state;
7841 int i;
79e53945 7842
dd3cd74a
ACO		 7843 memset(&crtc_state->dpll_hw_state, 0,
7844 sizeof(crtc_state->dpll_hw_state));
7845
da3ced29 7846 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7847 if (connector_state->crtc != &crtc->base)
7848 continue;
7849
7850 encoder = to_intel_encoder(connector_state->best_encoder);
7851
5eddb70b 7852 switch (encoder->type) {
e9fd1c02
JN		 7853 case INTEL_OUTPUT_DSI:
7854 is_dsi = true;
7855 break;
6847d71b
PZ		 7856 default:
7857 break;
79e53945 7858 }
43565a06 7859
c751ce4f 7860 num_connectors++;
79e53945
JB		 7861 }
7862
f2335330 7863 if (is_dsi)
5b18e57c 7864 return 0;
f2335330 7865
190f68c5 7866 if (!crtc_state->clock_set) {
a93e255f 7867 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7868
e9fd1c02
JN		 7869 /*
7870 * Returns a set of divisors for the desired target clock with
7871 * the given refclk, or FALSE. The returned values represent
7872 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7873 * 2) / p1 / p2.
7874 */
a93e255f
ACO		 7875 limit = intel_limit(crtc_state, refclk);
7876 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7877 crtc_state->port_clock,
e9fd1c02 7878 refclk, NULL, &clock);
f2335330 7879 if (!ok) {
e9fd1c02
JN		 7880 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7881 return -EINVAL;
7882 }
79e53945 7883
f2335330 7884 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7885 crtc_state->dpll.n = clock.n;
7886 crtc_state->dpll.m1 = clock.m1;
7887 crtc_state->dpll.m2 = clock.m2;
7888 crtc_state->dpll.p1 = clock.p1;
7889 crtc_state->dpll.p2 = clock.p2;
f47709a9 7890 }
7026d4ac 7891
e9fd1c02 7892 if (IS_GEN2(dev)) {
c329a4ec 7893 i8xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7894 num_connectors);
9d556c99 7895 } else if (IS_CHERRYVIEW(dev)) {
251ac862 7896 chv_compute_dpll(crtc, crtc_state);
e9fd1c02 7897 } else if (IS_VALLEYVIEW(dev)) {
251ac862 7898 vlv_compute_dpll(crtc, crtc_state);
e9fd1c02 7899 } else {
c329a4ec 7900 i9xx_compute_dpll(crtc, crtc_state, NULL,
251ac862 7901 num_connectors);
e9fd1c02 7902 }
79e53945 7903
c8f7a0db 7904 return 0;
f564048e
EA		 7905}
7906
2fa2fe9a 7907static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7908 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7909{
7910 struct drm_device *dev = crtc->base.dev;
7911 struct drm_i915_private *dev_priv = dev->dev_private;
7912 uint32_t tmp;
7913
dc9e7dec
VS		 7914 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7915 return;
7916
2fa2fe9a 7917 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7918 if (!(tmp & PFIT_ENABLE))
7919 return;
2fa2fe9a 7920
06922821 7921 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7922 if (INTEL_INFO(dev)->gen < 4) {
7923 if (crtc->pipe != PIPE_B)
7924 return;
2fa2fe9a
DV		 7925 } else {
7926 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7927 return;
7928 }
7929
06922821 7930 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7931 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7932 if (INTEL_INFO(dev)->gen < 5)
7933 pipe_config->gmch_pfit.lvds_border_bits =
7934 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7935}
7936
acbec814 7937static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7938 struct intel_crtc_state *pipe_config)
acbec814
JB		 7939{
7940 struct drm_device *dev = crtc->base.dev;
7941 struct drm_i915_private *dev_priv = dev->dev_private;
7942 int pipe = pipe_config->cpu_transcoder;
7943 intel_clock_t clock;
7944 u32 mdiv;
662c6ecb 7945 int refclk = 100000;
acbec814 7946
f573de5a
SK		 7947 /* In case of MIPI DPLL will not even be used */
7948 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7949 return;
7950
a580516d 7951 mutex_lock(&dev_priv->sb_lock);
ab3c759a 7952 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
a580516d 7953 mutex_unlock(&dev_priv->sb_lock);
acbec814
JB		 7954
7955 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7956 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7957 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7958 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7959 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7960
dccbea3b 7961 pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
acbec814
JB		 7962}
7963
5724dbd1
DL		 7964static void
7965i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7966 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7967{
7968 struct drm_device *dev = crtc->base.dev;
7969 struct drm_i915_private *dev_priv = dev->dev_private;
7970 u32 val, base, offset;
7971 int pipe = crtc->pipe, plane = crtc->plane;
7972 int fourcc, pixel_format;
6761dd31 7973 unsigned int aligned_height;
b113d5ee 7974 struct drm_framebuffer *fb;
1b842c89 7975 struct intel_framebuffer *intel_fb;
1ad292b5 7976
42a7b088
DL		 7977 val = I915_READ(DSPCNTR(plane));
7978 if (!(val & DISPLAY_PLANE_ENABLE))
7979 return;
7980
d9806c9f 7981 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7982 if (!intel_fb) {
1ad292b5
JB		 7983 DRM_DEBUG_KMS("failed to alloc fb\n");
7984 return;
7985 }
7986
1b842c89
DL		 7987 fb = &intel_fb->base;
7988
18c5247e
DV		 7989 if (INTEL_INFO(dev)->gen >= 4) {
7990 if (val & DISPPLANE_TILED) {
49af449b 7991 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7992 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7993 }
7994 }
1ad292b5
JB		 7995
7996 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7997 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7998 fb->pixel_format = fourcc;
7999 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 8000
8001 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 8002 if (plane_config->tiling)
1ad292b5
JB		 8003 offset = I915_READ(DSPTILEOFF(plane));
8004 else
8005 offset = I915_READ(DSPLINOFF(plane));
8006 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
8007 } else {
8008 base = I915_READ(DSPADDR(plane));
8009 }
8010 plane_config->base = base;
8011
8012 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8013 fb->width = ((val >> 16) & 0xfff) + 1;
8014 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 8015
8016 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8017 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 8018
b113d5ee 8019 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8020 fb->pixel_format,
8021 fb->modifier[0]);
1ad292b5 8022
f37b5c2b 8023 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 8024
2844a921
DL		 8025 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8026 pipe_name(pipe), plane, fb->width, fb->height,
8027 fb->bits_per_pixel, base, fb->pitches[0],
8028 plane_config->size);
1ad292b5 8029
2d14030b 8030 plane_config->fb = intel_fb;
1ad292b5
JB		 8031}
8032
70b23a98 8033static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 8034 struct intel_crtc_state *pipe_config)
70b23a98
VS		 8035{
8036 struct drm_device *dev = crtc->base.dev;
8037 struct drm_i915_private *dev_priv = dev->dev_private;
8038 int pipe = pipe_config->cpu_transcoder;
8039 enum dpio_channel port = vlv_pipe_to_channel(pipe);
8040 intel_clock_t clock;
8041 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
8042 int refclk = 100000;
8043
a580516d 8044 mutex_lock(&dev_priv->sb_lock);
70b23a98
VS		 8045 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
8046 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
8047 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
8048 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
a580516d 8049 mutex_unlock(&dev_priv->sb_lock);
70b23a98
VS		 8050
8051 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
8052 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
8053 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
8054 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
8055 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
8056
dccbea3b 8057 pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
70b23a98
VS		 8058}
8059
0e8ffe1b 8060static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8061 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8062{
8063 struct drm_device *dev = crtc->base.dev;
8064 struct drm_i915_private *dev_priv = dev->dev_private;
8065 uint32_t tmp;
8066
f458ebbc
DV		 8067 if (!intel_display_power_is_enabled(dev_priv,
8068 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 8069 return false;
8070
e143a21c 8071 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8072 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8073
0e8ffe1b
DV		 8074 tmp = I915_READ(PIPECONF(crtc->pipe));
8075 if (!(tmp & PIPECONF_ENABLE))
8076 return false;
8077
42571aef
VS		 8078 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
8079 switch (tmp & PIPECONF_BPC_MASK) {
8080 case PIPECONF_6BPC:
8081 pipe_config->pipe_bpp = 18;
8082 break;
8083 case PIPECONF_8BPC:
8084 pipe_config->pipe_bpp = 24;
8085 break;
8086 case PIPECONF_10BPC:
8087 pipe_config->pipe_bpp = 30;
8088 break;
8089 default:
8090 break;
8091 }
8092 }
8093
b5a9fa09
DV		 8094 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
8095 pipe_config->limited_color_range = true;
8096
282740f7
VS		 8097 if (INTEL_INFO(dev)->gen < 4)
8098 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
8099
1bd1bd80
DV		 8100 intel_get_pipe_timings(crtc, pipe_config);
8101
2fa2fe9a
DV		 8102 i9xx_get_pfit_config(crtc, pipe_config);
8103
6c49f241
DV		 8104 if (INTEL_INFO(dev)->gen >= 4) {
8105 tmp = I915_READ(DPLL_MD(crtc->pipe));
8106 pipe_config->pixel_multiplier =
8107 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
8108 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 8109 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 8110 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
8111 tmp = I915_READ(DPLL(crtc->pipe));
8112 pipe_config->pixel_multiplier =
8113 ((tmp & SDVO_MULTIPLIER_MASK)
8114 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
8115 } else {
8116 /* Note that on i915G/GM the pixel multiplier is in the sdvo
8117 * port and will be fixed up in the encoder->get_config
8118 * function. */
8119 pipe_config->pixel_multiplier = 1;
8120 }
8bcc2795
DV		 8121 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
8122 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 8123 /*
8124 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
8125 * on 830. Filter it out here so that we don't
8126 * report errors due to that.
8127 */
8128 if (IS_I830(dev))
8129 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
8130
8bcc2795
DV		 8131 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
8132 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 8133 } else {
8134 /* Mask out read-only status bits. */
8135 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
8136 DPLL_PORTC_READY_MASK |
8137 DPLL_PORTB_READY_MASK);
8bcc2795 8138 }
6c49f241 8139
70b23a98
VS		 8140 if (IS_CHERRYVIEW(dev))
8141 chv_crtc_clock_get(crtc, pipe_config);
8142 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 8143 vlv_crtc_clock_get(crtc, pipe_config);
8144 else
8145 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 8146
0e8ffe1b
DV		 8147 return true;
8148}
8149
dde86e2d 8150static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8151{
8152 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8153 struct intel_encoder *encoder;
74cfd7ac 8154 u32 val, final;
13d83a67 8155 bool has_lvds = false;
199e5d79 8156 bool has_cpu_edp = false;
199e5d79 8157 bool has_panel = false;
99eb6a01
KP		 8158 bool has_ck505 = false;
8159 bool can_ssc = false;
13d83a67
JB		 8160
8161 /* We need to take the global config into account */
b2784e15 8162 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8163 switch (encoder->type) {
8164 case INTEL_OUTPUT_LVDS:
8165 has_panel = true;
8166 has_lvds = true;
8167 break;
8168 case INTEL_OUTPUT_EDP:
8169 has_panel = true;
2de6905f 8170 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8171 has_cpu_edp = true;
8172 break;
6847d71b
PZ		 8173 default:
8174 break;
13d83a67
JB		 8175 }
8176 }
8177
99eb6a01 8178 if (HAS_PCH_IBX(dev)) {
41aa3448 8179 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8180 can_ssc = has_ck505;
8181 } else {
8182 has_ck505 = false;
8183 can_ssc = true;
8184 }
8185
2de6905f
ID		 8186 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8187 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8188
8189 /* Ironlake: try to setup display ref clock before DPLL
8190 * enabling. This is only under driver's control after
8191 * PCH B stepping, previous chipset stepping should be
8192 * ignoring this setting.
8193 */
74cfd7ac
CW		 8194 val = I915_READ(PCH_DREF_CONTROL);
8195
8196 /* As we must carefully and slowly disable/enable each source in turn,
8197 * compute the final state we want first and check if we need to
8198 * make any changes at all.
8199 */
8200 final = val;
8201 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8202 if (has_ck505)
8203 final |= DREF_NONSPREAD_CK505_ENABLE;
8204 else
8205 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8206
8207 final &= ~DREF_SSC_SOURCE_MASK;
8208 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8209 final &= ~DREF_SSC1_ENABLE;
8210
8211 if (has_panel) {
8212 final |= DREF_SSC_SOURCE_ENABLE;
8213
8214 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8215 final |= DREF_SSC1_ENABLE;
8216
8217 if (has_cpu_edp) {
8218 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8219 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8220 else
8221 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8222 } else
8223 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8224 } else {
8225 final |= DREF_SSC_SOURCE_DISABLE;
8226 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8227 }
8228
8229 if (final == val)
8230 return;
8231
13d83a67 8232 /* Always enable nonspread source */
74cfd7ac 8233 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8234
99eb6a01 8235 if (has_ck505)
74cfd7ac 8236 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8237 else
74cfd7ac 8238 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8239
199e5d79 8240 if (has_panel) {
74cfd7ac
CW		 8241 val &= ~DREF_SSC_SOURCE_MASK;
8242 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8243
199e5d79 8244 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8245 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8246 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8247 val |= DREF_SSC1_ENABLE;
e77166b5 8248 } else
74cfd7ac 8249 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8250
8251 /* Get SSC going before enabling the outputs */
74cfd7ac 8252 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8253 POSTING_READ(PCH_DREF_CONTROL);
8254 udelay(200);
8255
74cfd7ac 8256 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8257
8258 /* Enable CPU source on CPU attached eDP */
199e5d79 8259 if (has_cpu_edp) {
99eb6a01 8260 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8261 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8262 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8263 } else
74cfd7ac 8264 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8265 } else
74cfd7ac 8266 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8267
74cfd7ac 8268 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8269 POSTING_READ(PCH_DREF_CONTROL);
8270 udelay(200);
8271 } else {
8272 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8273
74cfd7ac 8274 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8275
8276 /* Turn off CPU output */
74cfd7ac 8277 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8278
74cfd7ac 8279 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8280 POSTING_READ(PCH_DREF_CONTROL);
8281 udelay(200);
8282
8283 /* Turn off the SSC source */
74cfd7ac
CW		 8284 val &= ~DREF_SSC_SOURCE_MASK;
8285 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8286
8287 /* Turn off SSC1 */
74cfd7ac 8288 val &= ~DREF_SSC1_ENABLE;
199e5d79 8289
74cfd7ac 8290 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8291 POSTING_READ(PCH_DREF_CONTROL);
8292 udelay(200);
8293 }
74cfd7ac
CW		 8294
8295 BUG_ON(val != final);
13d83a67
JB		 8296}
8297
f31f2d55 8298static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8299{
f31f2d55 8300 uint32_t tmp;
dde86e2d 8301
0ff066a9
PZ		 8302 tmp = I915_READ(SOUTH_CHICKEN2);
8303 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8304 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8305
0ff066a9
PZ		 8306 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8307 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8308 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8309
0ff066a9
PZ		 8310 tmp = I915_READ(SOUTH_CHICKEN2);
8311 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8312 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8313
0ff066a9
PZ		 8314 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8315 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8316 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8317}
8318
8319/* WaMPhyProgramming:hsw */
8320static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8321{
8322 uint32_t tmp;
dde86e2d
PZ		 8323
8324 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8325 tmp &= ~(0xFF << 24);
8326 tmp |= (0x12 << 24);
8327 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8328
dde86e2d
PZ		 8329 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8330 tmp |= (1 << 11);
8331 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8332
8333 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8334 tmp |= (1 << 11);
8335 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8336
dde86e2d
PZ		 8337 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8338 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8339 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8340
8341 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8342 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8343 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8344
0ff066a9
PZ		 8345 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8346 tmp &= ~(7 << 13);
8347 tmp |= (5 << 13);
8348 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8349
0ff066a9
PZ		 8350 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8351 tmp &= ~(7 << 13);
8352 tmp |= (5 << 13);
8353 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8354
8355 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8356 tmp &= ~0xFF;
8357 tmp |= 0x1C;
8358 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8359
8360 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8361 tmp &= ~0xFF;
8362 tmp |= 0x1C;
8363 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8364
8365 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8366 tmp &= ~(0xFF << 16);
8367 tmp |= (0x1C << 16);
8368 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8369
8370 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8371 tmp &= ~(0xFF << 16);
8372 tmp |= (0x1C << 16);
8373 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8374
0ff066a9
PZ		 8375 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8376 tmp |= (1 << 27);
8377 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8378
0ff066a9
PZ		 8379 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8380 tmp |= (1 << 27);
8381 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8382
0ff066a9
PZ		 8383 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8384 tmp &= ~(0xF << 28);
8385 tmp |= (4 << 28);
8386 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8387
0ff066a9
PZ		 8388 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8389 tmp &= ~(0xF << 28);
8390 tmp |= (4 << 28);
8391 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8392}
8393
2fa86a1f
PZ		 8394/* Implements 3 different sequences from BSpec chapter "Display iCLK
8395 * Programming" based on the parameters passed:
8396 * - Sequence to enable CLKOUT_DP
8397 * - Sequence to enable CLKOUT_DP without spread
8398 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8399 */
8400static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8401 bool with_fdi)
f31f2d55
PZ		 8402{
8403 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8404 uint32_t reg, tmp;
8405
8406 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8407 with_spread = true;
8408 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8409 with_fdi, "LP PCH doesn't have FDI\n"))
8410 with_fdi = false;
f31f2d55 8411
a580516d 8412 mutex_lock(&dev_priv->sb_lock);
f31f2d55
PZ		 8413
8414 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8415 tmp &= ~SBI_SSCCTL_DISABLE;
8416 tmp |= SBI_SSCCTL_PATHALT;
8417 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8418
8419 udelay(24);
8420
2fa86a1f
PZ		 8421 if (with_spread) {
8422 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8423 tmp &= ~SBI_SSCCTL_PATHALT;
8424 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8425
2fa86a1f
PZ		 8426 if (with_fdi) {
8427 lpt_reset_fdi_mphy(dev_priv);
8428 lpt_program_fdi_mphy(dev_priv);
8429 }
8430 }
dde86e2d 8431
2fa86a1f
PZ		 8432 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8433 SBI_GEN0 : SBI_DBUFF0;
8434 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8435 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8436 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246 8437
a580516d 8438 mutex_unlock(&dev_priv->sb_lock);
dde86e2d
PZ		 8439}
8440
47701c3b
PZ		 8441/* Sequence to disable CLKOUT_DP */
8442static void lpt_disable_clkout_dp(struct drm_device *dev)
8443{
8444 struct drm_i915_private *dev_priv = dev->dev_private;
8445 uint32_t reg, tmp;
8446
a580516d 8447 mutex_lock(&dev_priv->sb_lock);
47701c3b
PZ		 8448
8449 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8450 SBI_GEN0 : SBI_DBUFF0;
8451 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8452 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8453 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8454
8455 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8456 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8457 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8458 tmp |= SBI_SSCCTL_PATHALT;
8459 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8460 udelay(32);
8461 }
8462 tmp |= SBI_SSCCTL_DISABLE;
8463 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8464 }
8465
a580516d 8466 mutex_unlock(&dev_priv->sb_lock);
47701c3b
PZ		 8467}
8468
bf8fa3d3
PZ		 8469static void lpt_init_pch_refclk(struct drm_device *dev)
8470{
bf8fa3d3
PZ		 8471 struct intel_encoder *encoder;
8472 bool has_vga = false;
8473
b2784e15 8474 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8475 switch (encoder->type) {
8476 case INTEL_OUTPUT_ANALOG:
8477 has_vga = true;
8478 break;
6847d71b
PZ		 8479 default:
8480 break;
bf8fa3d3
PZ		 8481 }
8482 }
8483
47701c3b
PZ		 8484 if (has_vga)
8485 lpt_enable_clkout_dp(dev, true, true);
8486 else
8487 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8488}
8489
dde86e2d
PZ		 8490/*
8491 * Initialize reference clocks when the driver loads
8492 */
8493void intel_init_pch_refclk(struct drm_device *dev)
8494{
8495 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8496 ironlake_init_pch_refclk(dev);
8497 else if (HAS_PCH_LPT(dev))
8498 lpt_init_pch_refclk(dev);
8499}
8500
55bb9992 8501static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8502{
55bb9992 8503 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8504 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8505 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8506 struct drm_connector *connector;
55bb9992 8507 struct drm_connector_state *connector_state;
d9d444cb 8508 struct intel_encoder *encoder;
55bb9992 8509 int num_connectors = 0, i;
d9d444cb
JB		 8510 bool is_lvds = false;
8511
da3ced29 8512 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8513 if (connector_state->crtc != crtc_state->base.crtc)
8514 continue;
8515
8516 encoder = to_intel_encoder(connector_state->best_encoder);
8517
d9d444cb
JB		 8518 switch (encoder->type) {
8519 case INTEL_OUTPUT_LVDS:
8520 is_lvds = true;
8521 break;
6847d71b
PZ		 8522 default:
8523 break;
d9d444cb
JB		 8524 }
8525 num_connectors++;
8526 }
8527
8528 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8529 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8530 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8531 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8532 }
8533
8534 return 120000;
8535}
8536
6ff93609 8537static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8538{
c8203565 8539 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8540 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8541 int pipe = intel_crtc->pipe;
c8203565
PZ		 8542 uint32_t val;
8543
78114071 8544 val = 0;
c8203565 8545
6e3c9717 8546 switch (intel_crtc->config->pipe_bpp) {
c8203565 8547 case 18:
dfd07d72 8548 val |= PIPECONF_6BPC;
c8203565
PZ		 8549 break;
8550 case 24:
dfd07d72 8551 val |= PIPECONF_8BPC;
c8203565
PZ		 8552 break;
8553 case 30:
dfd07d72 8554 val |= PIPECONF_10BPC;
c8203565
PZ		 8555 break;
8556 case 36:
dfd07d72 8557 val |= PIPECONF_12BPC;
c8203565
PZ		 8558 break;
8559 default:
cc769b62
PZ		 8560 /* Case prevented by intel_choose_pipe_bpp_dither. */
8561 BUG();
c8203565
PZ		 8562 }
8563
6e3c9717 8564 if (intel_crtc->config->dither)
c8203565
PZ		 8565 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8566
6e3c9717 8567 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8568 val |= PIPECONF_INTERLACED_ILK;
8569 else
8570 val |= PIPECONF_PROGRESSIVE;
8571
6e3c9717 8572 if (intel_crtc->config->limited_color_range)
3685a8f3 8573 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8574
c8203565
PZ		 8575 I915_WRITE(PIPECONF(pipe), val);
8576 POSTING_READ(PIPECONF(pipe));
8577}
8578
86d3efce
VS		 8579/*
8580 * Set up the pipe CSC unit.
8581 *
8582 * Currently only full range RGB to limited range RGB conversion
8583 * is supported, but eventually this should handle various
8584 * RGB<->YCbCr scenarios as well.
8585 */
50f3b016 8586static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8587{
8588 struct drm_device *dev = crtc->dev;
8589 struct drm_i915_private *dev_priv = dev->dev_private;
8590 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8591 int pipe = intel_crtc->pipe;
8592 uint16_t coeff = 0x7800; /* 1.0 */
8593
8594 /*
8595 * TODO: Check what kind of values actually come out of the pipe
8596 * with these coeff/postoff values and adjust to get the best
8597 * accuracy. Perhaps we even need to take the bpc value into
8598 * consideration.
8599 */
8600
6e3c9717 8601 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8602 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8603
8604 /*
8605 * GY/GU and RY/RU should be the other way around according
8606 * to BSpec, but reality doesn't agree. Just set them up in
8607 * a way that results in the correct picture.
8608 */
8609 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8610 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8611
8612 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8613 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8614
8615 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8616 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8617
8618 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8619 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8620 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8621
8622 if (INTEL_INFO(dev)->gen > 6) {
8623 uint16_t postoff = 0;
8624
6e3c9717 8625 if (intel_crtc->config->limited_color_range)
32cf0cb0 8626 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8627
8628 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8629 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8630 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8631
8632 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8633 } else {
8634 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8635
6e3c9717 8636 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8637 mode |= CSC_BLACK_SCREEN_OFFSET;
8638
8639 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8640 }
8641}
8642
6ff93609 8643static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8644{
756f85cf
PZ		 8645 struct drm_device *dev = crtc->dev;
8646 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8648 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8649 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8650 uint32_t val;
8651
3eff4faa 8652 val = 0;
ee2b0b38 8653
6e3c9717 8654 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8655 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8656
6e3c9717 8657 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8658 val |= PIPECONF_INTERLACED_ILK;
8659 else
8660 val |= PIPECONF_PROGRESSIVE;
8661
702e7a56
PZ		 8662 I915_WRITE(PIPECONF(cpu_transcoder), val);
8663 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8664
8665 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8666 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8667
3cdf122c 8668 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8669 val = 0;
8670
6e3c9717 8671 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8672 case 18:
8673 val |= PIPEMISC_DITHER_6_BPC;
8674 break;
8675 case 24:
8676 val |= PIPEMISC_DITHER_8_BPC;
8677 break;
8678 case 30:
8679 val |= PIPEMISC_DITHER_10_BPC;
8680 break;
8681 case 36:
8682 val |= PIPEMISC_DITHER_12_BPC;
8683 break;
8684 default:
8685 /* Case prevented by pipe_config_set_bpp. */
8686 BUG();
8687 }
8688
6e3c9717 8689 if (intel_crtc->config->dither)
756f85cf
PZ		 8690 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8691
8692 I915_WRITE(PIPEMISC(pipe), val);
8693 }
ee2b0b38
PZ		 8694}
8695
6591c6e4 8696static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8697 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8698 intel_clock_t *clock,
8699 bool *has_reduced_clock,
8700 intel_clock_t *reduced_clock)
8701{
8702 struct drm_device *dev = crtc->dev;
8703 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8704 int refclk;
d4906093 8705 const intel_limit_t *limit;
c329a4ec 8706 bool ret;
79e53945 8707
55bb9992 8708 refclk = ironlake_get_refclk(crtc_state);
79e53945 8709
d4906093
ML		 8710 /*
8711 * Returns a set of divisors for the desired target clock with the given
8712 * refclk, or FALSE. The returned values represent the clock equation:
8713 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8714 */
a93e255f
ACO		 8715 limit = intel_limit(crtc_state, refclk);
8716 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8717 crtc_state->port_clock,
ee9300bb 8718 refclk, NULL, clock);
6591c6e4
PZ		 8719 if (!ret)
8720 return false;
cda4b7d3 8721
6591c6e4
PZ		 8722 return true;
8723}
8724
d4b1931c
PZ		 8725int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8726{
8727 /*
8728 * Account for spread spectrum to avoid
8729 * oversubscribing the link. Max center spread
8730 * is 2.5%; use 5% for safety's sake.
8731 */
8732 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8733 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8734}
8735
7429e9d4 8736static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8737{
7429e9d4 8738 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8739}
8740
de13a2e3 8741static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8742 struct intel_crtc_state *crtc_state,
7429e9d4 8743 u32 *fp,
9a7c7890 8744 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8745{
de13a2e3 8746 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8747 struct drm_device *dev = crtc->dev;
8748 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8749 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8750 struct drm_connector *connector;
55bb9992
ACO		 8751 struct drm_connector_state *connector_state;
8752 struct intel_encoder *encoder;
de13a2e3 8753 uint32_t dpll;
55bb9992 8754 int factor, num_connectors = 0, i;
09ede541 8755 bool is_lvds = false, is_sdvo = false;
79e53945 8756
da3ced29 8757 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8758 if (connector_state->crtc != crtc_state->base.crtc)
8759 continue;
8760
8761 encoder = to_intel_encoder(connector_state->best_encoder);
8762
8763 switch (encoder->type) {
79e53945
JB		 8764 case INTEL_OUTPUT_LVDS:
8765 is_lvds = true;
8766 break;
8767 case INTEL_OUTPUT_SDVO:
7d57382e 8768 case INTEL_OUTPUT_HDMI:
79e53945 8769 is_sdvo = true;
79e53945 8770 break;
6847d71b
PZ		 8771 default:
8772 break;
79e53945 8773 }
43565a06 8774
c751ce4f 8775 num_connectors++;
79e53945 8776 }
79e53945 8777
c1858123 8778 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8779 factor = 21;
8780 if (is_lvds) {
8781 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8782 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8783 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8784 factor = 25;
190f68c5 8785 } else if (crtc_state->sdvo_tv_clock)
8febb297 8786 factor = 20;
c1858123 8787
190f68c5 8788 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8789 *fp |= FP_CB_TUNE;
2c07245f 8790
9a7c7890
DV		 8791 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8792 *fp2 |= FP_CB_TUNE;
8793
5eddb70b 8794 dpll = 0;
2c07245f 8795
a07d6787
EA		 8796 if (is_lvds)
8797 dpll |= DPLLB_MODE_LVDS;
8798 else
8799 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8800
190f68c5 8801 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8802 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8803
8804 if (is_sdvo)
4a33e48d 8805 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8806 if (crtc_state->has_dp_encoder)
4a33e48d 8807 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8808
a07d6787 8809 /* compute bitmask from p1 value */
190f68c5 8810 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8811 /* also FPA1 */
190f68c5 8812 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8813
190f68c5 8814 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8815 case 5:
8816 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8817 break;
8818 case 7:
8819 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8820 break;
8821 case 10:
8822 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8823 break;
8824 case 14:
8825 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8826 break;
79e53945
JB		 8827 }
8828
b4c09f3b 8829 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8830 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8831 else
8832 dpll |= PLL_REF_INPUT_DREFCLK;
8833
959e16d6 8834 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8835}
8836
190f68c5
ACO		 8837static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8838 struct intel_crtc_state *crtc_state)
de13a2e3 8839{
c7653199 8840 struct drm_device *dev = crtc->base.dev;
de13a2e3 8841 intel_clock_t clock, reduced_clock;
cbbab5bd 8842 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8843 bool ok, has_reduced_clock = false;
8b47047b 8844 bool is_lvds = false;
e2b78267 8845 struct intel_shared_dpll *pll;
de13a2e3 8846
dd3cd74a
ACO		 8847 memset(&crtc_state->dpll_hw_state, 0,
8848 sizeof(crtc_state->dpll_hw_state));
8849
409ee761 8850 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8851
5dc5298b
PZ		 8852 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8853 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8854
190f68c5 8855 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8856 &has_reduced_clock, &reduced_clock);
190f68c5 8857 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8858 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8859 return -EINVAL;
79e53945 8860 }
f47709a9 8861 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8862 if (!crtc_state->clock_set) {
8863 crtc_state->dpll.n = clock.n;
8864 crtc_state->dpll.m1 = clock.m1;
8865 crtc_state->dpll.m2 = clock.m2;
8866 crtc_state->dpll.p1 = clock.p1;
8867 crtc_state->dpll.p2 = clock.p2;
f47709a9 8868 }
79e53945 8869
5dc5298b 8870 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8871 if (crtc_state->has_pch_encoder) {
8872 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8873 if (has_reduced_clock)
7429e9d4 8874 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8875
190f68c5 8876 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8877 &fp, &reduced_clock,
8878 has_reduced_clock ? &fp2 : NULL);
8879
190f68c5
ACO		 8880 crtc_state->dpll_hw_state.dpll = dpll;
8881 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8882 if (has_reduced_clock)
190f68c5 8883 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8884 else
190f68c5 8885 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8886
190f68c5 8887 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8888 if (pll == NULL) {
84f44ce7 8889 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8890 pipe_name(crtc->pipe));
4b645f14
JB		 8891 return -EINVAL;
8892 }
3fb37703 8893 }
79e53945 8894
ab585dea 8895 if (is_lvds && has_reduced_clock)
c7653199 8896 crtc->lowfreq_avail = true;
bcd644e0 8897 else
c7653199 8898 crtc->lowfreq_avail = false;
e2b78267 8899
c8f7a0db 8900 return 0;
79e53945
JB		 8901}
8902
eb14cb74
VS		 8903static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8904 struct intel_link_m_n *m_n)
8905{
8906 struct drm_device *dev = crtc->base.dev;
8907 struct drm_i915_private *dev_priv = dev->dev_private;
8908 enum pipe pipe = crtc->pipe;
8909
8910 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8911 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8912 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8913 & ~TU_SIZE_MASK;
8914 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8915 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8916 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8917}
8918
8919static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8920 enum transcoder transcoder,
b95af8be
VK		 8921 struct intel_link_m_n *m_n,
8922 struct intel_link_m_n *m2_n2)
72419203
DV		 8923{
8924 struct drm_device *dev = crtc->base.dev;
8925 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8926 enum pipe pipe = crtc->pipe;
72419203 8927
eb14cb74
VS		 8928 if (INTEL_INFO(dev)->gen >= 5) {
8929 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8930 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8931 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8932 & ~TU_SIZE_MASK;
8933 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8934 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8935 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8936 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8937 * gen < 8) and if DRRS is supported (to make sure the
8938 * registers are not unnecessarily read).
8939 */
8940 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8941 crtc->config->has_drrs) {
b95af8be
VK		 8942 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8943 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8944 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8945 & ~TU_SIZE_MASK;
8946 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8947 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8948 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8949 }
eb14cb74
VS		 8950 } else {
8951 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8952 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8953 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8954 & ~TU_SIZE_MASK;
8955 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8956 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8957 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8958 }
8959}
8960
8961void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8962 struct intel_crtc_state *pipe_config)
eb14cb74 8963{
681a8504 8964 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8965 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8966 else
8967 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8968 &pipe_config->dp_m_n,
8969 &pipe_config->dp_m2_n2);
eb14cb74 8970}
72419203 8971
eb14cb74 8972static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8973 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8974{
8975 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8976 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8977}
8978
bd2e244f 8979static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8980 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8981{
8982 struct drm_device *dev = crtc->base.dev;
8983 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8984 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8985 uint32_t ps_ctrl = 0;
8986 int id = -1;
8987 int i;
bd2e244f 8988
a1b2278e
CK		 8989 /* find scaler attached to this pipe */
8990 for (i = 0; i < crtc->num_scalers; i++) {
8991 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8992 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8993 id = i;
8994 pipe_config->pch_pfit.enabled = true;
8995 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8996 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8997 break;
8998 }
8999 }
bd2e244f 9000
a1b2278e
CK		 9001 scaler_state->scaler_id = id;
9002 if (id >= 0) {
9003 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
9004 } else {
9005 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 9006 }
9007}
9008
5724dbd1
DL		 9009static void
9010skylake_get_initial_plane_config(struct intel_crtc *crtc,
9011 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 9012{
9013 struct drm_device *dev = crtc->base.dev;
9014 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 9015 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 9016 int pipe = crtc->pipe;
9017 int fourcc, pixel_format;
6761dd31 9018 unsigned int aligned_height;
bc8d7dff 9019 struct drm_framebuffer *fb;
1b842c89 9020 struct intel_framebuffer *intel_fb;
bc8d7dff 9021
d9806c9f 9022 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9023 if (!intel_fb) {
bc8d7dff
DL		 9024 DRM_DEBUG_KMS("failed to alloc fb\n");
9025 return;
9026 }
9027
1b842c89
DL		 9028 fb = &intel_fb->base;
9029
bc8d7dff 9030 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 9031 if (!(val & PLANE_CTL_ENABLE))
9032 goto error;
9033
bc8d7dff
DL		 9034 pixel_format = val & PLANE_CTL_FORMAT_MASK;
9035 fourcc = skl_format_to_fourcc(pixel_format,
9036 val & PLANE_CTL_ORDER_RGBX,
9037 val & PLANE_CTL_ALPHA_MASK);
9038 fb->pixel_format = fourcc;
9039 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
9040
40f46283
DL		 9041 tiling = val & PLANE_CTL_TILED_MASK;
9042 switch (tiling) {
9043 case PLANE_CTL_TILED_LINEAR:
9044 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
9045 break;
9046 case PLANE_CTL_TILED_X:
9047 plane_config->tiling = I915_TILING_X;
9048 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9049 break;
9050 case PLANE_CTL_TILED_Y:
9051 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
9052 break;
9053 case PLANE_CTL_TILED_YF:
9054 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
9055 break;
9056 default:
9057 MISSING_CASE(tiling);
9058 goto error;
9059 }
9060
bc8d7dff
DL		 9061 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
9062 plane_config->base = base;
9063
9064 offset = I915_READ(PLANE_OFFSET(pipe, 0));
9065
9066 val = I915_READ(PLANE_SIZE(pipe, 0));
9067 fb->height = ((val >> 16) & 0xfff) + 1;
9068 fb->width = ((val >> 0) & 0x1fff) + 1;
9069
9070 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 9071 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
9072 fb->pixel_format);
bc8d7dff
DL		 9073 fb->pitches[0] = (val & 0x3ff) * stride_mult;
9074
9075 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9076 fb->pixel_format,
9077 fb->modifier[0]);
bc8d7dff 9078
f37b5c2b 9079 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 9080
9081 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9082 pipe_name(pipe), fb->width, fb->height,
9083 fb->bits_per_pixel, base, fb->pitches[0],
9084 plane_config->size);
9085
2d14030b 9086 plane_config->fb = intel_fb;
bc8d7dff
DL		 9087 return;
9088
9089error:
9090 kfree(fb);
9091}
9092
2fa2fe9a 9093static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 9094 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 9095{
9096 struct drm_device *dev = crtc->base.dev;
9097 struct drm_i915_private *dev_priv = dev->dev_private;
9098 uint32_t tmp;
9099
9100 tmp = I915_READ(PF_CTL(crtc->pipe));
9101
9102 if (tmp & PF_ENABLE) {
fd4daa9c 9103 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 9104 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
9105 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 9106
9107 /* We currently do not free assignements of panel fitters on
9108 * ivb/hsw (since we don't use the higher upscaling modes which
9109 * differentiates them) so just WARN about this case for now. */
9110 if (IS_GEN7(dev)) {
9111 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
9112 PF_PIPE_SEL_IVB(crtc->pipe));
9113 }
2fa2fe9a 9114 }
79e53945
JB		 9115}
9116
5724dbd1
DL		 9117static void
9118ironlake_get_initial_plane_config(struct intel_crtc *crtc,
9119 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 9120{
9121 struct drm_device *dev = crtc->base.dev;
9122 struct drm_i915_private *dev_priv = dev->dev_private;
9123 u32 val, base, offset;
aeee5a49 9124 int pipe = crtc->pipe;
4c6baa59 9125 int fourcc, pixel_format;
6761dd31 9126 unsigned int aligned_height;
b113d5ee 9127 struct drm_framebuffer *fb;
1b842c89 9128 struct intel_framebuffer *intel_fb;
4c6baa59 9129
42a7b088
DL		 9130 val = I915_READ(DSPCNTR(pipe));
9131 if (!(val & DISPLAY_PLANE_ENABLE))
9132 return;
9133
d9806c9f 9134 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9135 if (!intel_fb) {
4c6baa59
JB		 9136 DRM_DEBUG_KMS("failed to alloc fb\n");
9137 return;
9138 }
9139
1b842c89
DL		 9140 fb = &intel_fb->base;
9141
18c5247e
DV		 9142 if (INTEL_INFO(dev)->gen >= 4) {
9143 if (val & DISPPLANE_TILED) {
49af449b 9144 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9145 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9146 }
9147 }
4c6baa59
JB		 9148
9149 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9150 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9151 fb->pixel_format = fourcc;
9152 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9153
aeee5a49 9154 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9155 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9156 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9157 } else {
49af449b 9158 if (plane_config->tiling)
aeee5a49 9159 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9160 else
aeee5a49 9161 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9162 }
9163 plane_config->base = base;
9164
9165 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9166 fb->width = ((val >> 16) & 0xfff) + 1;
9167 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9168
9169 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9170 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9171
b113d5ee 9172 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9173 fb->pixel_format,
9174 fb->modifier[0]);
4c6baa59 9175
f37b5c2b 9176 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9177
2844a921
DL		 9178 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9179 pipe_name(pipe), fb->width, fb->height,
9180 fb->bits_per_pixel, base, fb->pitches[0],
9181 plane_config->size);
b113d5ee 9182
2d14030b 9183 plane_config->fb = intel_fb;
4c6baa59
JB		 9184}
9185
0e8ffe1b 9186static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9187 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9188{
9189 struct drm_device *dev = crtc->base.dev;
9190 struct drm_i915_private *dev_priv = dev->dev_private;
9191 uint32_t tmp;
9192
f458ebbc
DV		 9193 if (!intel_display_power_is_enabled(dev_priv,
9194 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9195 return false;
9196
e143a21c 9197 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9198 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9199
0e8ffe1b
DV		 9200 tmp = I915_READ(PIPECONF(crtc->pipe));
9201 if (!(tmp & PIPECONF_ENABLE))
9202 return false;
9203
42571aef
VS		 9204 switch (tmp & PIPECONF_BPC_MASK) {
9205 case PIPECONF_6BPC:
9206 pipe_config->pipe_bpp = 18;
9207 break;
9208 case PIPECONF_8BPC:
9209 pipe_config->pipe_bpp = 24;
9210 break;
9211 case PIPECONF_10BPC:
9212 pipe_config->pipe_bpp = 30;
9213 break;
9214 case PIPECONF_12BPC:
9215 pipe_config->pipe_bpp = 36;
9216 break;
9217 default:
9218 break;
9219 }
9220
b5a9fa09
DV		 9221 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9222 pipe_config->limited_color_range = true;
9223
ab9412ba 9224 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9225 struct intel_shared_dpll *pll;
9226
88adfff1
DV		 9227 pipe_config->has_pch_encoder = true;
9228
627eb5a3
DV		 9229 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9230 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9231 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9232
9233 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9234
c0d43d62 9235 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9236 pipe_config->shared_dpll =
9237 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9238 } else {
9239 tmp = I915_READ(PCH_DPLL_SEL);
9240 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9241 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9242 else
9243 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9244 }
66e985c0
DV		 9245
9246 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9247
9248 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9249 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9250
9251 tmp = pipe_config->dpll_hw_state.dpll;
9252 pipe_config->pixel_multiplier =
9253 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9254 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9255
9256 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9257 } else {
9258 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9259 }
9260
1bd1bd80
DV		 9261 intel_get_pipe_timings(crtc, pipe_config);
9262
2fa2fe9a
DV		 9263 ironlake_get_pfit_config(crtc, pipe_config);
9264
0e8ffe1b
DV		 9265 return true;
9266}
9267
be256dc7
PZ		 9268static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9269{
9270 struct drm_device *dev = dev_priv->dev;
be256dc7 9271 struct intel_crtc *crtc;
be256dc7 9272
d3fcc808 9273 for_each_intel_crtc(dev, crtc)
e2c719b7 9274 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9275 pipe_name(crtc->pipe));
9276
e2c719b7
RC		 9277 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9278 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9279 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9280 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9281 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9282 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9283 "CPU PWM1 enabled\n");
c5107b87 9284 if (IS_HASWELL(dev))
e2c719b7 9285 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9286 "CPU PWM2 enabled\n");
e2c719b7 9287 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9288 "PCH PWM1 enabled\n");
e2c719b7 9289 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9290 "Utility pin enabled\n");
e2c719b7 9291 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9292
9926ada1
PZ		 9293 /*
9294 * In theory we can still leave IRQs enabled, as long as only the HPD
9295 * interrupts remain enabled. We used to check for that, but since it's
9296 * gen-specific and since we only disable LCPLL after we fully disable
9297 * the interrupts, the check below should be enough.
9298 */
e2c719b7 9299 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9300}
9301
9ccd5aeb
PZ		 9302static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9303{
9304 struct drm_device *dev = dev_priv->dev;
9305
9306 if (IS_HASWELL(dev))
9307 return I915_READ(D_COMP_HSW);
9308 else
9309 return I915_READ(D_COMP_BDW);
9310}
9311
3c4c9b81
PZ		 9312static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9313{
9314 struct drm_device *dev = dev_priv->dev;
9315
9316 if (IS_HASWELL(dev)) {
9317 mutex_lock(&dev_priv->rps.hw_lock);
9318 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9319 val))
f475dadf 9320 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9321 mutex_unlock(&dev_priv->rps.hw_lock);
9322 } else {
9ccd5aeb
PZ		 9323 I915_WRITE(D_COMP_BDW, val);
9324 POSTING_READ(D_COMP_BDW);
3c4c9b81 9325 }
be256dc7
PZ		 9326}
9327
9328/*
9329 * This function implements pieces of two sequences from BSpec:
9330 * - Sequence for display software to disable LCPLL
9331 * - Sequence for display software to allow package C8+
9332 * The steps implemented here are just the steps that actually touch the LCPLL
9333 * register. Callers should take care of disabling all the display engine
9334 * functions, doing the mode unset, fixing interrupts, etc.
9335 */
6ff58d53
PZ		 9336static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9337 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9338{
9339 uint32_t val;
9340
9341 assert_can_disable_lcpll(dev_priv);
9342
9343 val = I915_READ(LCPLL_CTL);
9344
9345 if (switch_to_fclk) {
9346 val |= LCPLL_CD_SOURCE_FCLK;
9347 I915_WRITE(LCPLL_CTL, val);
9348
9349 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9350 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9351 DRM_ERROR("Switching to FCLK failed\n");
9352
9353 val = I915_READ(LCPLL_CTL);
9354 }
9355
9356 val |= LCPLL_PLL_DISABLE;
9357 I915_WRITE(LCPLL_CTL, val);
9358 POSTING_READ(LCPLL_CTL);
9359
9360 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9361 DRM_ERROR("LCPLL still locked\n");
9362
9ccd5aeb 9363 val = hsw_read_dcomp(dev_priv);
be256dc7 9364 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9365 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9366 ndelay(100);
9367
9ccd5aeb
PZ		 9368 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9369 1))
be256dc7
PZ		 9370 DRM_ERROR("D_COMP RCOMP still in progress\n");
9371
9372 if (allow_power_down) {
9373 val = I915_READ(LCPLL_CTL);
9374 val |= LCPLL_POWER_DOWN_ALLOW;
9375 I915_WRITE(LCPLL_CTL, val);
9376 POSTING_READ(LCPLL_CTL);
9377 }
9378}
9379
9380/*
9381 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9382 * source.
9383 */
6ff58d53 9384static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9385{
9386 uint32_t val;
9387
9388 val = I915_READ(LCPLL_CTL);
9389
9390 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9391 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9392 return;
9393
a8a8bd54
PZ		 9394 /*
9395 * Make sure we're not on PC8 state before disabling PC8, otherwise
9396 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9397 */
59bad947 9398 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9399
be256dc7
PZ		 9400 if (val & LCPLL_POWER_DOWN_ALLOW) {
9401 val &= ~LCPLL_POWER_DOWN_ALLOW;
9402 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9403 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9404 }
9405
9ccd5aeb 9406 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9407 val |= D_COMP_COMP_FORCE;
9408 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9409 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9410
9411 val = I915_READ(LCPLL_CTL);
9412 val &= ~LCPLL_PLL_DISABLE;
9413 I915_WRITE(LCPLL_CTL, val);
9414
9415 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9416 DRM_ERROR("LCPLL not locked yet\n");
9417
9418 if (val & LCPLL_CD_SOURCE_FCLK) {
9419 val = I915_READ(LCPLL_CTL);
9420 val &= ~LCPLL_CD_SOURCE_FCLK;
9421 I915_WRITE(LCPLL_CTL, val);
9422
9423 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9424 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9425 DRM_ERROR("Switching back to LCPLL failed\n");
9426 }
215733fa 9427
59bad947 9428 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
b6283055 9429 intel_update_cdclk(dev_priv->dev);
be256dc7
PZ		 9430}
9431
765dab67
PZ		 9432/*
9433 * Package states C8 and deeper are really deep PC states that can only be
9434 * reached when all the devices on the system allow it, so even if the graphics
9435 * device allows PC8+, it doesn't mean the system will actually get to these
9436 * states. Our driver only allows PC8+ when going into runtime PM.
9437 *
9438 * The requirements for PC8+ are that all the outputs are disabled, the power
9439 * well is disabled and most interrupts are disabled, and these are also
9440 * requirements for runtime PM. When these conditions are met, we manually do
9441 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9442 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9443 * hang the machine.
9444 *
9445 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9446 * the state of some registers, so when we come back from PC8+ we need to
9447 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9448 * need to take care of the registers kept by RC6. Notice that this happens even
9449 * if we don't put the device in PCI D3 state (which is what currently happens
9450 * because of the runtime PM support).
9451 *
9452 * For more, read "Display Sequences for Package C8" on the hardware
9453 * documentation.
9454 */
a14cb6fc 9455void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9456{
c67a470b
PZ		 9457 struct drm_device *dev = dev_priv->dev;
9458 uint32_t val;
9459
c67a470b
PZ		 9460 DRM_DEBUG_KMS("Enabling package C8+\n");
9461
c67a470b
PZ		 9462 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9463 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9464 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9465 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9466 }
9467
9468 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9469 hsw_disable_lcpll(dev_priv, true, true);
9470}
9471
a14cb6fc 9472void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9473{
9474 struct drm_device *dev = dev_priv->dev;
9475 uint32_t val;
9476
c67a470b
PZ		 9477 DRM_DEBUG_KMS("Disabling package C8+\n");
9478
9479 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9480 lpt_init_pch_refclk(dev);
9481
9482 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9483 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9484 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9485 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9486 }
9487
9488 intel_prepare_ddi(dev);
c67a470b
PZ		 9489}
9490
27c329ed 9491static void broxton_modeset_commit_cdclk(struct drm_atomic_state *old_state)
f8437dd1 9492{
a821fc46 9493 struct drm_device *dev = old_state->dev;
27c329ed 9494 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
f8437dd1 9495
27c329ed 9496 broxton_set_cdclk(dev, req_cdclk);
f8437dd1
VK		 9497}
9498
b432e5cf 9499/* compute the max rate for new configuration */
27c329ed 9500static int ilk_max_pixel_rate(struct drm_atomic_state *state)
b432e5cf 9501{
b432e5cf 9502 struct intel_crtc *intel_crtc;
27c329ed 9503 struct intel_crtc_state *crtc_state;
b432e5cf 9504 int max_pixel_rate = 0;
b432e5cf 9505
27c329ed
ML		 9506 for_each_intel_crtc(state->dev, intel_crtc) {
9507 int pixel_rate;
9508
9509 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9510 if (IS_ERR(crtc_state))
9511 return PTR_ERR(crtc_state);
9512
9513 if (!crtc_state->base.enable)
b432e5cf
VS		 9514 continue;
9515
27c329ed 9516 pixel_rate = ilk_pipe_pixel_rate(crtc_state);
b432e5cf
VS		 9517
9518 /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
27c329ed 9519 if (IS_BROADWELL(state->dev) && crtc_state->ips_enabled)
b432e5cf
VS		 9520 pixel_rate = DIV_ROUND_UP(pixel_rate * 100, 95);
9521
9522 max_pixel_rate = max(max_pixel_rate, pixel_rate);
9523 }
9524
9525 return max_pixel_rate;
9526}
9527
9528static void broadwell_set_cdclk(struct drm_device *dev, int cdclk)
9529{
9530 struct drm_i915_private *dev_priv = dev->dev_private;
9531 uint32_t val, data;
9532 int ret;
9533
9534 if (WARN((I915_READ(LCPLL_CTL) &
9535 (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
9536 LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
9537 LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
9538 LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
9539 "trying to change cdclk frequency with cdclk not enabled\n"))
9540 return;
9541
9542 mutex_lock(&dev_priv->rps.hw_lock);
9543 ret = sandybridge_pcode_write(dev_priv,
9544 BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
9545 mutex_unlock(&dev_priv->rps.hw_lock);
9546 if (ret) {
9547 DRM_ERROR("failed to inform pcode about cdclk change\n");
9548 return;
9549 }
9550
9551 val = I915_READ(LCPLL_CTL);
9552 val |= LCPLL_CD_SOURCE_FCLK;
9553 I915_WRITE(LCPLL_CTL, val);
9554
9555 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9556 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9557 DRM_ERROR("Switching to FCLK failed\n");
9558
9559 val = I915_READ(LCPLL_CTL);
9560 val &= ~LCPLL_CLK_FREQ_MASK;
9561
9562 switch (cdclk) {
9563 case 450000:
9564 val |= LCPLL_CLK_FREQ_450;
9565 data = 0;
9566 break;
9567 case 540000:
9568 val |= LCPLL_CLK_FREQ_54O_BDW;
9569 data = 1;
9570 break;
9571 case 337500:
9572 val |= LCPLL_CLK_FREQ_337_5_BDW;
9573 data = 2;
9574 break;
9575 case 675000:
9576 val |= LCPLL_CLK_FREQ_675_BDW;
9577 data = 3;
9578 break;
9579 default:
9580 WARN(1, "invalid cdclk frequency\n");
9581 return;
9582 }
9583
9584 I915_WRITE(LCPLL_CTL, val);
9585
9586 val = I915_READ(LCPLL_CTL);
9587 val &= ~LCPLL_CD_SOURCE_FCLK;
9588 I915_WRITE(LCPLL_CTL, val);
9589
9590 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9591 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9592 DRM_ERROR("Switching back to LCPLL failed\n");
9593
9594 mutex_lock(&dev_priv->rps.hw_lock);
9595 sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ, data);
9596 mutex_unlock(&dev_priv->rps.hw_lock);
9597
9598 intel_update_cdclk(dev);
9599
9600 WARN(cdclk != dev_priv->cdclk_freq,
9601 "cdclk requested %d kHz but got %d kHz\n",
9602 cdclk, dev_priv->cdclk_freq);
9603}
9604
27c329ed 9605static int broadwell_modeset_calc_cdclk(struct drm_atomic_state *state)
b432e5cf 9606{
27c329ed
ML		 9607 struct drm_i915_private *dev_priv = to_i915(state->dev);
9608 int max_pixclk = ilk_max_pixel_rate(state);
b432e5cf
VS		 9609 int cdclk;
9610
9611 /*
9612 * FIXME should also account for plane ratio
9613 * once 64bpp pixel formats are supported.
9614 */
27c329ed 9615 if (max_pixclk > 540000)
b432e5cf 9616 cdclk = 675000;
27c329ed 9617 else if (max_pixclk > 450000)
b432e5cf 9618 cdclk = 540000;
27c329ed 9619 else if (max_pixclk > 337500)
b432e5cf
VS		 9620 cdclk = 450000;
9621 else
9622 cdclk = 337500;
9623
9624 /*
9625 * FIXME move the cdclk caclulation to
9626 * compute_config() so we can fail gracegully.
9627 */
9628 if (cdclk > dev_priv->max_cdclk_freq) {
9629 DRM_ERROR("requested cdclk (%d kHz) exceeds max (%d kHz)\n",
9630 cdclk, dev_priv->max_cdclk_freq);
9631 cdclk = dev_priv->max_cdclk_freq;
9632 }
9633
27c329ed 9634 to_intel_atomic_state(state)->cdclk = cdclk;
b432e5cf
VS		 9635
9636 return 0;
9637}
9638
27c329ed 9639static void broadwell_modeset_commit_cdclk(struct drm_atomic_state *old_state)
b432e5cf 9640{
27c329ed
ML		 9641 struct drm_device *dev = old_state->dev;
9642 unsigned int req_cdclk = to_intel_atomic_state(old_state)->cdclk;
b432e5cf 9643
27c329ed 9644 broadwell_set_cdclk(dev, req_cdclk);
b432e5cf
VS		 9645}
9646
190f68c5
ACO		 9647static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9648 struct intel_crtc_state *crtc_state)
09b4ddf9 9649{
190f68c5 9650 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9651 return -EINVAL;
716c2e55 9652
c7653199 9653 crtc->lowfreq_avail = false;
644cef34 9654
c8f7a0db 9655 return 0;
79e53945
JB		 9656}
9657
3760b59c
S		 9658static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9659 enum port port,
9660 struct intel_crtc_state *pipe_config)
9661{
9662 switch (port) {
9663 case PORT_A:
9664 pipe_config->ddi_pll_sel = SKL_DPLL0;
9665 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9666 break;
9667 case PORT_B:
9668 pipe_config->ddi_pll_sel = SKL_DPLL1;
9669 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9670 break;
9671 case PORT_C:
9672 pipe_config->ddi_pll_sel = SKL_DPLL2;
9673 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9674 break;
9675 default:
9676 DRM_ERROR("Incorrect port type\n");
9677 }
9678}
9679
96b7dfb7
S		 9680static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9681 enum port port,
5cec258b 9682 struct intel_crtc_state *pipe_config)
96b7dfb7 9683{
3148ade7 9684 u32 temp, dpll_ctl1;
96b7dfb7
S		 9685
9686 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9687 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9688
9689 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9690 case SKL_DPLL0:
9691 /*
9692 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9693 * of the shared DPLL framework and thus needs to be read out
9694 * separately
9695 */
9696 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9697 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9698 break;
96b7dfb7
S		 9699 case SKL_DPLL1:
9700 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9701 break;
9702 case SKL_DPLL2:
9703 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9704 break;
9705 case SKL_DPLL3:
9706 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9707 break;
96b7dfb7
S		 9708 }
9709}
9710
7d2c8175
DL		 9711static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9712 enum port port,
5cec258b 9713 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9714{
9715 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9716
9717 switch (pipe_config->ddi_pll_sel) {
9718 case PORT_CLK_SEL_WRPLL1:
9719 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9720 break;
9721 case PORT_CLK_SEL_WRPLL2:
9722 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9723 break;
9724 }
9725}
9726
26804afd 9727static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9728 struct intel_crtc_state *pipe_config)
26804afd
DV		 9729{
9730 struct drm_device *dev = crtc->base.dev;
9731 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9732 struct intel_shared_dpll *pll;
26804afd
DV		 9733 enum port port;
9734 uint32_t tmp;
9735
9736 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9737
9738 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9739
96b7dfb7
S		 9740 if (IS_SKYLAKE(dev))
9741 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9742 else if (IS_BROXTON(dev))
9743 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9744 else
9745 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9746
d452c5b6
DV		 9747 if (pipe_config->shared_dpll >= 0) {
9748 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9749
9750 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9751 &pipe_config->dpll_hw_state));
9752 }
9753
26804afd
DV		 9754 /*
9755 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9756 * DDI E. So just check whether this pipe is wired to DDI E and whether
9757 * the PCH transcoder is on.
9758 */
ca370455
DL		 9759 if (INTEL_INFO(dev)->gen < 9 &&
9760 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9761 pipe_config->has_pch_encoder = true;
9762
9763 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9764 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9765 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9766
9767 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9768 }
9769}
9770
0e8ffe1b 9771static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9772 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9773{
9774 struct drm_device *dev = crtc->base.dev;
9775 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9776 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9777 uint32_t tmp;
9778
f458ebbc 9779 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9780 POWER_DOMAIN_PIPE(crtc->pipe)))
9781 return false;
9782
e143a21c 9783 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9784 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9785
eccb140b
DV		 9786 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9787 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9788 enum pipe trans_edp_pipe;
9789 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9790 default:
9791 WARN(1, "unknown pipe linked to edp transcoder\n");
9792 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9793 case TRANS_DDI_EDP_INPUT_A_ON:
9794 trans_edp_pipe = PIPE_A;
9795 break;
9796 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9797 trans_edp_pipe = PIPE_B;
9798 break;
9799 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9800 trans_edp_pipe = PIPE_C;
9801 break;
9802 }
9803
9804 if (trans_edp_pipe == crtc->pipe)
9805 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9806 }
9807
f458ebbc 9808 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9809 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9810 return false;
9811
eccb140b 9812 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9813 if (!(tmp & PIPECONF_ENABLE))
9814 return false;
9815
26804afd 9816 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9817
1bd1bd80
DV		 9818 intel_get_pipe_timings(crtc, pipe_config);
9819
a1b2278e
CK		 9820 if (INTEL_INFO(dev)->gen >= 9) {
9821 skl_init_scalers(dev, crtc, pipe_config);
9822 }
9823
2fa2fe9a 9824 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9825
9826 if (INTEL_INFO(dev)->gen >= 9) {
9827 pipe_config->scaler_state.scaler_id = -1;
9828 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9829 }
9830
bd2e244f 9831 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9832 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9833 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9834 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9835 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9836 else
9837 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9838 }
88adfff1 9839
e59150dc
JB		 9840 if (IS_HASWELL(dev))
9841 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9842 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9843
ebb69c95
CT		 9844 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9845 pipe_config->pixel_multiplier =
9846 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9847 } else {
9848 pipe_config->pixel_multiplier = 1;
9849 }
6c49f241 9850
0e8ffe1b
DV		 9851 return true;
9852}
9853
560b85bb
CW		 9854static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9855{
9856 struct drm_device *dev = crtc->dev;
9857 struct drm_i915_private *dev_priv = dev->dev_private;
9858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9859 uint32_t cntl = 0, size = 0;
560b85bb 9860
dc41c154 9861 if (base) {
3dd512fb
MR		 9862 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9863 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9864 unsigned int stride = roundup_pow_of_two(width) * 4;
9865
9866 switch (stride) {
9867 default:
9868 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9869 width, stride);
9870 stride = 256;
9871 /* fallthrough */
9872 case 256:
9873 case 512:
9874 case 1024:
9875 case 2048:
9876 break;
4b0e333e
CW		 9877 }
9878
dc41c154
VS		 9879 cntl |= CURSOR_ENABLE |
9880 CURSOR_GAMMA_ENABLE |
9881 CURSOR_FORMAT_ARGB |
9882 CURSOR_STRIDE(stride);
9883
9884 size = (height << 12) | width;
4b0e333e 9885 }
560b85bb 9886
dc41c154
VS		 9887 if (intel_crtc->cursor_cntl != 0 &&
9888 (intel_crtc->cursor_base != base ||
9889 intel_crtc->cursor_size != size ||
9890 intel_crtc->cursor_cntl != cntl)) {
9891 /* On these chipsets we can only modify the base/size/stride
9892 * whilst the cursor is disabled.
9893 */
9894 I915_WRITE(_CURACNTR, 0);
4b0e333e 9895 POSTING_READ(_CURACNTR);
dc41c154 9896 intel_crtc->cursor_cntl = 0;
4b0e333e 9897 }
560b85bb 9898
99d1f387 9899 if (intel_crtc->cursor_base != base) {
9db4a9c7 9900 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9901 intel_crtc->cursor_base = base;
9902 }
4726e0b0 9903
dc41c154
VS		 9904 if (intel_crtc->cursor_size != size) {
9905 I915_WRITE(CURSIZE, size);
9906 intel_crtc->cursor_size = size;
4b0e333e 9907 }
560b85bb 9908
4b0e333e 9909 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9910 I915_WRITE(_CURACNTR, cntl);
9911 POSTING_READ(_CURACNTR);
4b0e333e 9912 intel_crtc->cursor_cntl = cntl;
560b85bb 9913 }
560b85bb
CW		 9914}
9915
560b85bb 9916static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9917{
9918 struct drm_device *dev = crtc->dev;
9919 struct drm_i915_private *dev_priv = dev->dev_private;
9920 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9921 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9922 uint32_t cntl;
9923
9924 cntl = 0;
9925 if (base) {
9926 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9927 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9928 case 64:
9929 cntl |= CURSOR_MODE_64_ARGB_AX;
9930 break;
9931 case 128:
9932 cntl |= CURSOR_MODE_128_ARGB_AX;
9933 break;
9934 case 256:
9935 cntl |= CURSOR_MODE_256_ARGB_AX;
9936 break;
9937 default:
3dd512fb 9938 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9939 return;
65a21cd6 9940 }
4b0e333e 9941 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9942
9943 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9944 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9945 }
65a21cd6 9946
8e7d688b 9947 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9948 cntl |= CURSOR_ROTATE_180;
9949
4b0e333e
CW		 9950 if (intel_crtc->cursor_cntl != cntl) {
9951 I915_WRITE(CURCNTR(pipe), cntl);
9952 POSTING_READ(CURCNTR(pipe));
9953 intel_crtc->cursor_cntl = cntl;
65a21cd6 9954 }
4b0e333e 9955
65a21cd6 9956 /* and commit changes on next vblank */
5efb3e28
VS		 9957 I915_WRITE(CURBASE(pipe), base);
9958 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9959
9960 intel_crtc->cursor_base = base;
65a21cd6
JB		 9961}
9962
cda4b7d3 9963/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9964static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9965 bool on)
cda4b7d3
CW		 9966{
9967 struct drm_device *dev = crtc->dev;
9968 struct drm_i915_private *dev_priv = dev->dev_private;
9969 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9970 int pipe = intel_crtc->pipe;
3d7d6510
MR		 9971 int x = crtc->cursor_x;
9972 int y = crtc->cursor_y;
d6e4db15 9973 u32 base = 0, pos = 0;
cda4b7d3 9974
d6e4db15 9975 if (on)
cda4b7d3 9976 base = intel_crtc->cursor_addr;
cda4b7d3 9977
6e3c9717 9978 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9979 base = 0;
9980
6e3c9717 9981 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9982 base = 0;
9983
9984 if (x < 0) {
3dd512fb 9985 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 9986 base = 0;
9987
9988 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9989 x = -x;
9990 }
9991 pos |= x << CURSOR_X_SHIFT;
9992
9993 if (y < 0) {
3dd512fb 9994 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 9995 base = 0;
9996
9997 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9998 y = -y;
9999 }
10000 pos |= y << CURSOR_Y_SHIFT;
10001
4b0e333e 10002 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 10003 return;
10004
5efb3e28
VS		 10005 I915_WRITE(CURPOS(pipe), pos);
10006
4398ad45
VS		 10007 /* ILK+ do this automagically */
10008 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 10009 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 10010 base += (intel_crtc->base.cursor->state->crtc_h *
10011 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 10012 }
10013
8ac54669 10014 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 10015 i845_update_cursor(crtc, base);
10016 else
10017 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 10018}
10019
dc41c154
VS		 10020static bool cursor_size_ok(struct drm_device *dev,
10021 uint32_t width, uint32_t height)
10022{
10023 if (width == 0 || height == 0)
10024 return false;
10025
10026 /*
10027 * 845g/865g are special in that they are only limited by
10028 * the width of their cursors, the height is arbitrary up to
10029 * the precision of the register. Everything else requires
10030 * square cursors, limited to a few power-of-two sizes.
10031 */
10032 if (IS_845G(dev) || IS_I865G(dev)) {
10033 if ((width & 63) != 0)
10034 return false;
10035
10036 if (width > (IS_845G(dev) ? 64 : 512))
10037 return false;
10038
10039 if (height > 1023)
10040 return false;
10041 } else {
10042 switch (width | height) {
10043 case 256:
10044 case 128:
10045 if (IS_GEN2(dev))
10046 return false;
10047 case 64:
10048 break;
10049 default:
10050 return false;
10051 }
10052 }
10053
10054 return true;
10055}
10056
79e53945 10057static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 10058 u16 *blue, uint32_t start, uint32_t size)
79e53945 10059{
7203425a 10060 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 10061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 10062
7203425a 10063 for (i = start; i < end; i++) {
79e53945
JB		 10064 intel_crtc->lut_r[i] = red[i] >> 8;
10065 intel_crtc->lut_g[i] = green[i] >> 8;
10066 intel_crtc->lut_b[i] = blue[i] >> 8;
10067 }
10068
10069 intel_crtc_load_lut(crtc);
10070}
10071
79e53945
JB		 10072/* VESA 640x480x72Hz mode to set on the pipe */
10073static struct drm_display_mode load_detect_mode = {
10074 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
10075 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
10076};
10077
a8bb6818
DV		 10078struct drm_framebuffer *
10079__intel_framebuffer_create(struct drm_device *dev,
10080 struct drm_mode_fb_cmd2 *mode_cmd,
10081 struct drm_i915_gem_object *obj)
d2dff872
CW		 10082{
10083 struct intel_framebuffer *intel_fb;
10084 int ret;
10085
10086 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
10087 if (!intel_fb) {
6ccb81f2 10088 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 10089 return ERR_PTR(-ENOMEM);
10090 }
10091
10092 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 10093 if (ret)
10094 goto err;
d2dff872
CW		 10095
10096 return &intel_fb->base;
dd4916c5 10097err:
6ccb81f2 10098 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 10099 kfree(intel_fb);
10100
10101 return ERR_PTR(ret);
d2dff872
CW		 10102}
10103
b5ea642a 10104static struct drm_framebuffer *
a8bb6818
DV		 10105intel_framebuffer_create(struct drm_device *dev,
10106 struct drm_mode_fb_cmd2 *mode_cmd,
10107 struct drm_i915_gem_object *obj)
10108{
10109 struct drm_framebuffer *fb;
10110 int ret;
10111
10112 ret = i915_mutex_lock_interruptible(dev);
10113 if (ret)
10114 return ERR_PTR(ret);
10115 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
10116 mutex_unlock(&dev->struct_mutex);
10117
10118 return fb;
10119}
10120
d2dff872
CW		 10121static u32
10122intel_framebuffer_pitch_for_width(int width, int bpp)
10123{
10124 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
10125 return ALIGN(pitch, 64);
10126}
10127
10128static u32
10129intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
10130{
10131 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 10132 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 10133}
10134
10135static struct drm_framebuffer *
10136intel_framebuffer_create_for_mode(struct drm_device *dev,
10137 struct drm_display_mode *mode,
10138 int depth, int bpp)
10139{
10140 struct drm_i915_gem_object *obj;
0fed39bd 10141 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 10142
10143 obj = i915_gem_alloc_object(dev,
10144 intel_framebuffer_size_for_mode(mode, bpp));
10145 if (obj == NULL)
10146 return ERR_PTR(-ENOMEM);
10147
10148 mode_cmd.width = mode->hdisplay;
10149 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 10150 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
10151 bpp);
5ca0c34a 10152 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 10153
10154 return intel_framebuffer_create(dev, &mode_cmd, obj);
10155}
10156
10157static struct drm_framebuffer *
10158mode_fits_in_fbdev(struct drm_device *dev,
10159 struct drm_display_mode *mode)
10160{
4520f53a 10161#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 10162 struct drm_i915_private *dev_priv = dev->dev_private;
10163 struct drm_i915_gem_object *obj;
10164 struct drm_framebuffer *fb;
10165
4c0e5528 10166 if (!dev_priv->fbdev)
d2dff872
CW		 10167 return NULL;
10168
4c0e5528 10169 if (!dev_priv->fbdev->fb)
d2dff872
CW		 10170 return NULL;
10171
4c0e5528
DV		 10172 obj = dev_priv->fbdev->fb->obj;
10173 BUG_ON(!obj);
10174
8bcd4553 10175 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 10176 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
10177 fb->bits_per_pixel))
d2dff872
CW		 10178 return NULL;
10179
01f2c773 10180 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 10181 return NULL;
10182
10183 return fb;
4520f53a
DV		 10184#else
10185 return NULL;
10186#endif
d2dff872
CW		 10187}
10188
d3a40d1b
ACO		 10189static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
10190 struct drm_crtc *crtc,
10191 struct drm_display_mode *mode,
10192 struct drm_framebuffer *fb,
10193 int x, int y)
10194{
10195 struct drm_plane_state *plane_state;
10196 int hdisplay, vdisplay;
10197 int ret;
10198
10199 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
10200 if (IS_ERR(plane_state))
10201 return PTR_ERR(plane_state);
10202
10203 if (mode)
10204 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
10205 else
10206 hdisplay = vdisplay = 0;
10207
10208 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
10209 if (ret)
10210 return ret;
10211 drm_atomic_set_fb_for_plane(plane_state, fb);
10212 plane_state->crtc_x = 0;
10213 plane_state->crtc_y = 0;
10214 plane_state->crtc_w = hdisplay;
10215 plane_state->crtc_h = vdisplay;
10216 plane_state->src_x = x << 16;
10217 plane_state->src_y = y << 16;
10218 plane_state->src_w = hdisplay << 16;
10219 plane_state->src_h = vdisplay << 16;
10220
10221 return 0;
10222}
10223
d2434ab7 10224bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 10225 struct drm_display_mode *mode,
51fd371b
RC		 10226 struct intel_load_detect_pipe *old,
10227 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 10228{
10229 struct intel_crtc *intel_crtc;
d2434ab7
DV		 10230 struct intel_encoder *intel_encoder =
10231 intel_attached_encoder(connector);
79e53945 10232 struct drm_crtc *possible_crtc;
4ef69c7a 10233 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 10234 struct drm_crtc *crtc = NULL;
10235 struct drm_device *dev = encoder->dev;
94352cf9 10236 struct drm_framebuffer *fb;
51fd371b 10237 struct drm_mode_config *config = &dev->mode_config;
83a57153 10238 struct drm_atomic_state *state = NULL;
944b0c76 10239 struct drm_connector_state *connector_state;
4be07317 10240 struct intel_crtc_state *crtc_state;
51fd371b 10241 int ret, i = -1;
79e53945 10242
d2dff872 10243 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10244 connector->base.id, connector->name,
8e329a03 10245 encoder->base.id, encoder->name);
d2dff872 10246
51fd371b
RC		 10247retry:
10248 ret = drm_modeset_lock(&config->connection_mutex, ctx);
10249 if (ret)
10250 goto fail_unlock;
6e9f798d 10251
79e53945
JB		 10252 /*
10253 * Algorithm gets a little messy:
7a5e4805 10254 *
79e53945
JB		 10255 * - if the connector already has an assigned crtc, use it (but make
10256 * sure it's on first)
7a5e4805 10257 *
79e53945
JB		 10258 * - try to find the first unused crtc that can drive this connector,
10259 * and use that if we find one
79e53945
JB		 10260 */
10261
10262 /* See if we already have a CRTC for this connector */
10263 if (encoder->crtc) {
10264 crtc = encoder->crtc;
8261b191 10265
51fd371b 10266 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 10267 if (ret)
10268 goto fail_unlock;
10269 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 10270 if (ret)
10271 goto fail_unlock;
7b24056b 10272
24218aac 10273 old->dpms_mode = connector->dpms;
8261b191
CW		 10274 old->load_detect_temp = false;
10275
10276 /* Make sure the crtc and connector are running */
24218aac
DV		 10277 if (connector->dpms != DRM_MODE_DPMS_ON)
10278 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10279
7173188d 10280 return true;
79e53945
JB		 10281 }
10282
10283 /* Find an unused one (if possible) */
70e1e0ec 10284 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10285 i++;
10286 if (!(encoder->possible_crtcs & (1 << i)))
10287 continue;
83d65738 10288 if (possible_crtc->state->enable)
a459249c
VS		 10289 continue;
10290 /* This can occur when applying the pipe A quirk on resume. */
10291 if (to_intel_crtc(possible_crtc)->new_enabled)
10292 continue;
10293
10294 crtc = possible_crtc;
10295 break;
79e53945
JB		 10296 }
10297
10298 /*
10299 * If we didn't find an unused CRTC, don't use any.
10300 */
10301 if (!crtc) {
7173188d 10302 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 10303 goto fail_unlock;
79e53945
JB		 10304 }
10305
51fd371b
RC		 10306 ret = drm_modeset_lock(&crtc->mutex, ctx);
10307 if (ret)
4d02e2de
DV		 10308 goto fail_unlock;
10309 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10310 if (ret)
51fd371b 10311 goto fail_unlock;
fc303101
DV		 10312 intel_encoder->new_crtc = to_intel_crtc(crtc);
10313 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 10314
10315 intel_crtc = to_intel_crtc(crtc);
412b61d8 10316 intel_crtc->new_enabled = true;
24218aac 10317 old->dpms_mode = connector->dpms;
8261b191 10318 old->load_detect_temp = true;
d2dff872 10319 old->release_fb = NULL;
79e53945 10320
83a57153
ACO		 10321 state = drm_atomic_state_alloc(dev);
10322 if (!state)
10323 return false;
10324
10325 state->acquire_ctx = ctx;
10326
944b0c76
ACO		 10327 connector_state = drm_atomic_get_connector_state(state, connector);
10328 if (IS_ERR(connector_state)) {
10329 ret = PTR_ERR(connector_state);
10330 goto fail;
10331 }
10332
10333 connector_state->crtc = crtc;
10334 connector_state->best_encoder = &intel_encoder->base;
10335
4be07317
ACO		 10336 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10337 if (IS_ERR(crtc_state)) {
10338 ret = PTR_ERR(crtc_state);
10339 goto fail;
10340 }
10341
49d6fa21 10342 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10343
6492711d
CW		 10344 if (!mode)
10345 mode = &load_detect_mode;
79e53945 10346
d2dff872
CW		 10347 /* We need a framebuffer large enough to accommodate all accesses
10348 * that the plane may generate whilst we perform load detection.
10349 * We can not rely on the fbcon either being present (we get called
10350 * during its initialisation to detect all boot displays, or it may
10351 * not even exist) or that it is large enough to satisfy the
10352 * requested mode.
10353 */
94352cf9
DV		 10354 fb = mode_fits_in_fbdev(dev, mode);
10355 if (fb == NULL) {
d2dff872 10356 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10357 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10358 old->release_fb = fb;
d2dff872
CW		 10359 } else
10360 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10361 if (IS_ERR(fb)) {
d2dff872 10362 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10363 goto fail;
79e53945 10364 }
79e53945 10365
d3a40d1b
ACO		 10366 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10367 if (ret)
10368 goto fail;
10369
8c7b5ccb
ACO		 10370 drm_mode_copy(&crtc_state->base.mode, mode);
10371
568c634a 10372 if (intel_set_mode(state)) {
6492711d 10373 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10374 if (old->release_fb)
10375 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10376 goto fail;
79e53945 10377 }
9128b040 10378 crtc->primary->crtc = crtc;
7173188d 10379
79e53945 10380 /* let the connector get through one full cycle before testing */
9d0498a2 10381 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10382 return true;
412b61d8
VS		 10383
10384 fail:
83d65738 10385 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 10386fail_unlock:
e5d958ef
ACO		 10387 drm_atomic_state_free(state);
10388 state = NULL;
83a57153 10389
51fd371b
RC		 10390 if (ret == -EDEADLK) {
10391 drm_modeset_backoff(ctx);
10392 goto retry;
10393 }
10394
412b61d8 10395 return false;
79e53945
JB		 10396}
10397
d2434ab7 10398void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10399 struct intel_load_detect_pipe *old,
10400 struct drm_modeset_acquire_ctx *ctx)
79e53945 10401{
83a57153 10402 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10403 struct intel_encoder *intel_encoder =
10404 intel_attached_encoder(connector);
4ef69c7a 10405 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10406 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10408 struct drm_atomic_state *state;
944b0c76 10409 struct drm_connector_state *connector_state;
4be07317 10410 struct intel_crtc_state *crtc_state;
d3a40d1b 10411 int ret;
79e53945 10412
d2dff872 10413 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10414 connector->base.id, connector->name,
8e329a03 10415 encoder->base.id, encoder->name);
d2dff872 10416
8261b191 10417 if (old->load_detect_temp) {
83a57153 10418 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10419 if (!state)
10420 goto fail;
83a57153
ACO		 10421
10422 state->acquire_ctx = ctx;
10423
944b0c76
ACO		 10424 connector_state = drm_atomic_get_connector_state(state, connector);
10425 if (IS_ERR(connector_state))
10426 goto fail;
10427
4be07317
ACO		 10428 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10429 if (IS_ERR(crtc_state))
10430 goto fail;
10431
fc303101
DV		 10432 to_intel_connector(connector)->new_encoder = NULL;
10433 intel_encoder->new_crtc = NULL;
412b61d8 10434 intel_crtc->new_enabled = false;
944b0c76
ACO		 10435
10436 connector_state->best_encoder = NULL;
10437 connector_state->crtc = NULL;
10438
49d6fa21 10439 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10440
d3a40d1b
ACO		 10441 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10442 0, 0);
10443 if (ret)
10444 goto fail;
10445
568c634a 10446 ret = intel_set_mode(state);
2bfb4627
ACO		 10447 if (ret)
10448 goto fail;
d2dff872 10449
36206361
DV		 10450 if (old->release_fb) {
10451 drm_framebuffer_unregister_private(old->release_fb);
10452 drm_framebuffer_unreference(old->release_fb);
10453 }
d2dff872 10454
0622a53c 10455 return;
79e53945
JB		 10456 }
10457
c751ce4f 10458 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10459 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10460 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10461
10462 return;
10463fail:
10464 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10465 drm_atomic_state_free(state);
79e53945
JB		 10466}
10467
da4a1efa 10468static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10469 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10470{
10471 struct drm_i915_private *dev_priv = dev->dev_private;
10472 u32 dpll = pipe_config->dpll_hw_state.dpll;
10473
10474 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10475 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10476 else if (HAS_PCH_SPLIT(dev))
10477 return 120000;
10478 else if (!IS_GEN2(dev))
10479 return 96000;
10480 else
10481 return 48000;
10482}
10483
79e53945 10484/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10485static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10486 struct intel_crtc_state *pipe_config)
79e53945 10487{
f1f644dc 10488 struct drm_device *dev = crtc->base.dev;
79e53945 10489 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10490 int pipe = pipe_config->cpu_transcoder;
293623f7 10491 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10492 u32 fp;
10493 intel_clock_t clock;
dccbea3b 10494 int port_clock;
da4a1efa 10495 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10496
10497 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10498 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10499 else
293623f7 10500 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10501
10502 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10503 if (IS_PINEVIEW(dev)) {
10504 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10505 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10506 } else {
10507 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10508 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10509 }
10510
a6c45cf0 10511 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10512 if (IS_PINEVIEW(dev))
10513 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10514 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10515 else
10516 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10517 DPLL_FPA01_P1_POST_DIV_SHIFT);
10518
10519 switch (dpll & DPLL_MODE_MASK) {
10520 case DPLLB_MODE_DAC_SERIAL:
10521 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10522 5 : 10;
10523 break;
10524 case DPLLB_MODE_LVDS:
10525 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10526 7 : 14;
10527 break;
10528 default:
28c97730 10529 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10530 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10531 return;
79e53945
JB		 10532 }
10533
ac58c3f0 10534 if (IS_PINEVIEW(dev))
dccbea3b 10535 port_clock = pnv_calc_dpll_params(refclk, &clock);
ac58c3f0 10536 else
dccbea3b 10537 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945 10538 } else {
0fb58223 10539 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10540 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10541
10542 if (is_lvds) {
10543 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10544 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10545
10546 if (lvds & LVDS_CLKB_POWER_UP)
10547 clock.p2 = 7;
10548 else
10549 clock.p2 = 14;
79e53945
JB		 10550 } else {
10551 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10552 clock.p1 = 2;
10553 else {
10554 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10555 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10556 }
10557 if (dpll & PLL_P2_DIVIDE_BY_4)
10558 clock.p2 = 4;
10559 else
10560 clock.p2 = 2;
79e53945 10561 }
da4a1efa 10562
dccbea3b 10563 port_clock = i9xx_calc_dpll_params(refclk, &clock);
79e53945
JB		 10564 }
10565
18442d08
VS		 10566 /*
10567 * This value includes pixel_multiplier. We will use
241bfc38 10568 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10569 * encoder's get_config() function.
10570 */
dccbea3b 10571 pipe_config->port_clock = port_clock;
f1f644dc
JB		 10572}
10573
6878da05
VS		 10574int intel_dotclock_calculate(int link_freq,
10575 const struct intel_link_m_n *m_n)
f1f644dc 10576{
f1f644dc
JB		 10577 /*
10578 * The calculation for the data clock is:
1041a02f 10579 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10580 * But we want to avoid losing precison if possible, so:
1041a02f 10581 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10582 *
10583 * and the link clock is simpler:
1041a02f 10584 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10585 */
10586
6878da05
VS		 10587 if (!m_n->link_n)
10588 return 0;
f1f644dc 10589
6878da05
VS		 10590 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10591}
f1f644dc 10592
18442d08 10593static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10594 struct intel_crtc_state *pipe_config)
6878da05
VS		 10595{
10596 struct drm_device *dev = crtc->base.dev;
79e53945 10597
18442d08
VS		 10598 /* read out port_clock from the DPLL */
10599 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10600
f1f644dc 10601 /*
18442d08 10602 * This value does not include pixel_multiplier.
241bfc38 10603 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10604 * agree once we know their relationship in the encoder's
10605 * get_config() function.
79e53945 10606 */
2d112de7 10607 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10608 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10609 &pipe_config->fdi_m_n);
79e53945
JB		 10610}
10611
10612/** Returns the currently programmed mode of the given pipe. */
10613struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10614 struct drm_crtc *crtc)
10615{
548f245b 10616 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10617 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10618 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10619 struct drm_display_mode *mode;
5cec258b 10620 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10621 int htot = I915_READ(HTOTAL(cpu_transcoder));
10622 int hsync = I915_READ(HSYNC(cpu_transcoder));
10623 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10624 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10625 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10626
10627 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10628 if (!mode)
10629 return NULL;
10630
f1f644dc
JB		 10631 /*
10632 * Construct a pipe_config sufficient for getting the clock info
10633 * back out of crtc_clock_get.
10634 *
10635 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10636 * to use a real value here instead.
10637 */
293623f7 10638 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10639 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10640 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10641 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10642 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10643 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10644
773ae034 10645 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10646 mode->hdisplay = (htot & 0xffff) + 1;
10647 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10648 mode->hsync_start = (hsync & 0xffff) + 1;
10649 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10650 mode->vdisplay = (vtot & 0xffff) + 1;
10651 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10652 mode->vsync_start = (vsync & 0xffff) + 1;
10653 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10654
10655 drm_mode_set_name(mode);
79e53945
JB		 10656
10657 return mode;
10658}
10659
f047e395
CW		 10660void intel_mark_busy(struct drm_device *dev)
10661{
c67a470b
PZ		 10662 struct drm_i915_private *dev_priv = dev->dev_private;
10663
f62a0076
CW		 10664 if (dev_priv->mm.busy)
10665 return;
10666
43694d69 10667 intel_runtime_pm_get(dev_priv);
c67a470b 10668 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10669 if (INTEL_INFO(dev)->gen >= 6)
10670 gen6_rps_busy(dev_priv);
f62a0076 10671 dev_priv->mm.busy = true;
f047e395
CW		 10672}
10673
10674void intel_mark_idle(struct drm_device *dev)
652c393a 10675{
c67a470b 10676 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10677
f62a0076
CW		 10678 if (!dev_priv->mm.busy)
10679 return;
10680
10681 dev_priv->mm.busy = false;
10682
3d13ef2e 10683 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10684 gen6_rps_idle(dev->dev_private);
bb4cdd53 10685
43694d69 10686 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10687}
10688
79e53945
JB		 10689static void intel_crtc_destroy(struct drm_crtc *crtc)
10690{
10691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10692 struct drm_device *dev = crtc->dev;
10693 struct intel_unpin_work *work;
67e77c5a 10694
5e2d7afc 10695 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10696 work = intel_crtc->unpin_work;
10697 intel_crtc->unpin_work = NULL;
5e2d7afc 10698 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10699
10700 if (work) {
10701 cancel_work_sync(&work->work);
10702 kfree(work);
10703 }
79e53945
JB		 10704
10705 drm_crtc_cleanup(crtc);
67e77c5a 10706
79e53945
JB		 10707 kfree(intel_crtc);
10708}
10709
6b95a207
KH		 10710static void intel_unpin_work_fn(struct work_struct *__work)
10711{
10712 struct intel_unpin_work *work =
10713 container_of(__work, struct intel_unpin_work, work);
a9ff8714
VS		 10714 struct intel_crtc *crtc = to_intel_crtc(work->crtc);
10715 struct drm_device *dev = crtc->base.dev;
7733b49b 10716 struct drm_i915_private *dev_priv = dev->dev_private;
a9ff8714 10717 struct drm_plane *primary = crtc->base.primary;
6b95a207 10718
b4a98e57 10719 mutex_lock(&dev->struct_mutex);
a9ff8714 10720 intel_unpin_fb_obj(work->old_fb, primary->state);
05394f39 10721 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10722
7733b49b 10723 intel_fbc_update(dev_priv);
f06cc1b9
JH		 10724
10725 if (work->flip_queued_req)
146d84f0 10726 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10727 mutex_unlock(&dev->struct_mutex);
10728
a9ff8714 10729 intel_frontbuffer_flip_complete(dev, to_intel_plane(primary)->frontbuffer_bit);
89ed88ba 10730 drm_framebuffer_unreference(work->old_fb);
f99d7069 10731
a9ff8714
VS		 10732 BUG_ON(atomic_read(&crtc->unpin_work_count) == 0);
10733 atomic_dec(&crtc->unpin_work_count);
b4a98e57 10734
6b95a207
KH		 10735 kfree(work);
10736}
10737
1afe3e9d 10738static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10739 struct drm_crtc *crtc)
6b95a207 10740{
6b95a207
KH		 10741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10742 struct intel_unpin_work *work;
6b95a207
KH		 10743 unsigned long flags;
10744
10745 /* Ignore early vblank irqs */
10746 if (intel_crtc == NULL)
10747 return;
10748
f326038a
DV		 10749 /*
10750 * This is called both by irq handlers and the reset code (to complete
10751 * lost pageflips) so needs the full irqsave spinlocks.
10752 */
6b95a207
KH		 10753 spin_lock_irqsave(&dev->event_lock, flags);
10754 work = intel_crtc->unpin_work;
e7d841ca
CW		 10755
10756 /* Ensure we don't miss a work->pending update ... */
10757 smp_rmb();
10758
10759 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10760 spin_unlock_irqrestore(&dev->event_lock, flags);
10761 return;
10762 }
10763
d6bbafa1 10764 page_flip_completed(intel_crtc);
0af7e4df 10765
6b95a207 10766 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10767}
10768
1afe3e9d
JB		 10769void intel_finish_page_flip(struct drm_device *dev, int pipe)
10770{
fbee40df 10771 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10772 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10773
49b14a5c 10774 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10775}
10776
10777void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10778{
fbee40df 10779 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10780 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10781
49b14a5c 10782 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10783}
10784
75f7f3ec
VS		 10785/* Is 'a' after or equal to 'b'? */
10786static bool g4x_flip_count_after_eq(u32 a, u32 b)
10787{
10788 return !((a - b) & 0x80000000);
10789}
10790
10791static bool page_flip_finished(struct intel_crtc *crtc)
10792{
10793 struct drm_device *dev = crtc->base.dev;
10794 struct drm_i915_private *dev_priv = dev->dev_private;
10795
bdfa7542
VS		 10796 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10797 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10798 return true;
10799
75f7f3ec
VS		 10800 /*
10801 * The relevant registers doen't exist on pre-ctg.
10802 * As the flip done interrupt doesn't trigger for mmio
10803 * flips on gmch platforms, a flip count check isn't
10804 * really needed there. But since ctg has the registers,
10805 * include it in the check anyway.
10806 */
10807 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10808 return true;
10809
10810 /*
10811 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10812 * used the same base address. In that case the mmio flip might
10813 * have completed, but the CS hasn't even executed the flip yet.
10814 *
10815 * A flip count check isn't enough as the CS might have updated
10816 * the base address just after start of vblank, but before we
10817 * managed to process the interrupt. This means we'd complete the
10818 * CS flip too soon.
10819 *
10820 * Combining both checks should get us a good enough result. It may
10821 * still happen that the CS flip has been executed, but has not
10822 * yet actually completed. But in case the base address is the same
10823 * anyway, we don't really care.
10824 */
10825 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10826 crtc->unpin_work->gtt_offset &&
10827 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10828 crtc->unpin_work->flip_count);
10829}
10830
6b95a207
KH		 10831void intel_prepare_page_flip(struct drm_device *dev, int plane)
10832{
fbee40df 10833 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10834 struct intel_crtc *intel_crtc =
10835 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10836 unsigned long flags;
10837
f326038a
DV		 10838
10839 /*
10840 * This is called both by irq handlers and the reset code (to complete
10841 * lost pageflips) so needs the full irqsave spinlocks.
10842 *
10843 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10844 * generate a page-flip completion irq, i.e. every modeset
10845 * is also accompanied by a spurious intel_prepare_page_flip().
10846 */
6b95a207 10847 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10848 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10849 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10850 spin_unlock_irqrestore(&dev->event_lock, flags);
10851}
10852
eba905b2 10853static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10854{
10855 /* Ensure that the work item is consistent when activating it ... */
10856 smp_wmb();
10857 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10858 /* and that it is marked active as soon as the irq could fire. */
10859 smp_wmb();
10860}
10861
8c9f3aaf
JB		 10862static int intel_gen2_queue_flip(struct drm_device *dev,
10863 struct drm_crtc *crtc,
10864 struct drm_framebuffer *fb,
ed8d1975 10865 struct drm_i915_gem_object *obj,
6258fbe2 10866 struct drm_i915_gem_request *req,
ed8d1975 10867 uint32_t flags)
8c9f3aaf 10868{
6258fbe2 10869 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10871 u32 flip_mask;
10872 int ret;
10873
5fb9de1a 10874 ret = intel_ring_begin(req, 6);
8c9f3aaf 10875 if (ret)
4fa62c89 10876 return ret;
8c9f3aaf
JB		 10877
10878 /* Can't queue multiple flips, so wait for the previous
10879 * one to finish before executing the next.
10880 */
10881 if (intel_crtc->plane)
10882 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10883 else
10884 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10885 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10886 intel_ring_emit(ring, MI_NOOP);
10887 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10888 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10889 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10890 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10891 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10892
10893 intel_mark_page_flip_active(intel_crtc);
83d4092b 10894 return 0;
8c9f3aaf
JB		 10895}
10896
10897static int intel_gen3_queue_flip(struct drm_device *dev,
10898 struct drm_crtc *crtc,
10899 struct drm_framebuffer *fb,
ed8d1975 10900 struct drm_i915_gem_object *obj,
6258fbe2 10901 struct drm_i915_gem_request *req,
ed8d1975 10902 uint32_t flags)
8c9f3aaf 10903{
6258fbe2 10904 struct intel_engine_cs *ring = req->ring;
8c9f3aaf 10905 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10906 u32 flip_mask;
10907 int ret;
10908
5fb9de1a 10909 ret = intel_ring_begin(req, 6);
8c9f3aaf 10910 if (ret)
4fa62c89 10911 return ret;
8c9f3aaf
JB		 10912
10913 if (intel_crtc->plane)
10914 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10915 else
10916 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10917 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10918 intel_ring_emit(ring, MI_NOOP);
10919 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10920 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10921 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10922 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10923 intel_ring_emit(ring, MI_NOOP);
10924
e7d841ca 10925 intel_mark_page_flip_active(intel_crtc);
83d4092b 10926 return 0;
8c9f3aaf
JB		 10927}
10928
10929static int intel_gen4_queue_flip(struct drm_device *dev,
10930 struct drm_crtc *crtc,
10931 struct drm_framebuffer *fb,
ed8d1975 10932 struct drm_i915_gem_object *obj,
6258fbe2 10933 struct drm_i915_gem_request *req,
ed8d1975 10934 uint32_t flags)
8c9f3aaf 10935{
6258fbe2 10936 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10937 struct drm_i915_private *dev_priv = dev->dev_private;
10938 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10939 uint32_t pf, pipesrc;
10940 int ret;
10941
5fb9de1a 10942 ret = intel_ring_begin(req, 4);
8c9f3aaf 10943 if (ret)
4fa62c89 10944 return ret;
8c9f3aaf
JB		 10945
10946 /* i965+ uses the linear or tiled offsets from the
10947 * Display Registers (which do not change across a page-flip)
10948 * so we need only reprogram the base address.
10949 */
6d90c952
DV		 10950 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10951 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10952 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10953 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10954 obj->tiling_mode);
8c9f3aaf
JB		 10955
10956 /* XXX Enabling the panel-fitter across page-flip is so far
10957 * untested on non-native modes, so ignore it for now.
10958 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10959 */
10960 pf = 0;
10961 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10962 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10963
10964 intel_mark_page_flip_active(intel_crtc);
83d4092b 10965 return 0;
8c9f3aaf
JB		 10966}
10967
10968static int intel_gen6_queue_flip(struct drm_device *dev,
10969 struct drm_crtc *crtc,
10970 struct drm_framebuffer *fb,
ed8d1975 10971 struct drm_i915_gem_object *obj,
6258fbe2 10972 struct drm_i915_gem_request *req,
ed8d1975 10973 uint32_t flags)
8c9f3aaf 10974{
6258fbe2 10975 struct intel_engine_cs *ring = req->ring;
8c9f3aaf
JB		 10976 struct drm_i915_private *dev_priv = dev->dev_private;
10977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10978 uint32_t pf, pipesrc;
10979 int ret;
10980
5fb9de1a 10981 ret = intel_ring_begin(req, 4);
8c9f3aaf 10982 if (ret)
4fa62c89 10983 return ret;
8c9f3aaf 10984
6d90c952
DV		 10985 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10986 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10987 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10988 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10989
dc257cf1
DV		 10990 /* Contrary to the suggestions in the documentation,
10991 * "Enable Panel Fitter" does not seem to be required when page
10992 * flipping with a non-native mode, and worse causes a normal
10993 * modeset to fail.
10994 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10995 */
10996 pf = 0;
8c9f3aaf 10997 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10998 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10999
11000 intel_mark_page_flip_active(intel_crtc);
83d4092b 11001 return 0;
8c9f3aaf
JB		 11002}
11003
7c9017e5
JB		 11004static int intel_gen7_queue_flip(struct drm_device *dev,
11005 struct drm_crtc *crtc,
11006 struct drm_framebuffer *fb,
ed8d1975 11007 struct drm_i915_gem_object *obj,
6258fbe2 11008 struct drm_i915_gem_request *req,
ed8d1975 11009 uint32_t flags)
7c9017e5 11010{
6258fbe2 11011 struct intel_engine_cs *ring = req->ring;
7c9017e5 11012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 11013 uint32_t plane_bit = 0;
ffe74d75
CW		 11014 int len, ret;
11015
eba905b2 11016 switch (intel_crtc->plane) {
cb05d8de
DV		 11017 case PLANE_A:
11018 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
11019 break;
11020 case PLANE_B:
11021 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
11022 break;
11023 case PLANE_C:
11024 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
11025 break;
11026 default:
11027 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 11028 return -ENODEV;
cb05d8de
DV		 11029 }
11030
ffe74d75 11031 len = 4;
f476828a 11032 if (ring->id == RCS) {
ffe74d75 11033 len += 6;
f476828a
DL		 11034 /*
11035 * On Gen 8, SRM is now taking an extra dword to accommodate
11036 * 48bits addresses, and we need a NOOP for the batch size to
11037 * stay even.
11038 */
11039 if (IS_GEN8(dev))
11040 len += 2;
11041 }
ffe74d75 11042
f66fab8e
VS		 11043 /*
11044 * BSpec MI_DISPLAY_FLIP for IVB:
11045 * "The full packet must be contained within the same cache line."
11046 *
11047 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
11048 * cacheline, if we ever start emitting more commands before
11049 * the MI_DISPLAY_FLIP we may need to first emit everything else,
11050 * then do the cacheline alignment, and finally emit the
11051 * MI_DISPLAY_FLIP.
11052 */
bba09b12 11053 ret = intel_ring_cacheline_align(req);
f66fab8e 11054 if (ret)
4fa62c89 11055 return ret;
f66fab8e 11056
5fb9de1a 11057 ret = intel_ring_begin(req, len);
7c9017e5 11058 if (ret)
4fa62c89 11059 return ret;
7c9017e5 11060
ffe74d75
CW		 11061 /* Unmask the flip-done completion message. Note that the bspec says that
11062 * we should do this for both the BCS and RCS, and that we must not unmask
11063 * more than one flip event at any time (or ensure that one flip message
11064 * can be sent by waiting for flip-done prior to queueing new flips).
11065 * Experimentation says that BCS works despite DERRMR masking all
11066 * flip-done completion events and that unmasking all planes at once
11067 * for the RCS also doesn't appear to drop events. Setting the DERRMR
11068 * to zero does lead to lockups within MI_DISPLAY_FLIP.
11069 */
11070 if (ring->id == RCS) {
11071 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
11072 intel_ring_emit(ring, DERRMR);
11073 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
11074 DERRMR_PIPEB_PRI_FLIP_DONE |
11075 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 11076 if (IS_GEN8(dev))
11077 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
11078 MI_SRM_LRM_GLOBAL_GTT);
11079 else
11080 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
11081 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 11082 intel_ring_emit(ring, DERRMR);
11083 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 11084 if (IS_GEN8(dev)) {
11085 intel_ring_emit(ring, 0);
11086 intel_ring_emit(ring, MI_NOOP);
11087 }
ffe74d75
CW		 11088 }
11089
cb05d8de 11090 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 11091 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 11092 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 11093 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 11094
11095 intel_mark_page_flip_active(intel_crtc);
83d4092b 11096 return 0;
7c9017e5
JB		 11097}
11098
84c33a64
SG		 11099static bool use_mmio_flip(struct intel_engine_cs *ring,
11100 struct drm_i915_gem_object *obj)
11101{
11102 /*
11103 * This is not being used for older platforms, because
11104 * non-availability of flip done interrupt forces us to use
11105 * CS flips. Older platforms derive flip done using some clever
11106 * tricks involving the flip_pending status bits and vblank irqs.
11107 * So using MMIO flips there would disrupt this mechanism.
11108 */
11109
8e09bf83
CW		 11110 if (ring == NULL)
11111 return true;
11112
84c33a64
SG		 11113 if (INTEL_INFO(ring->dev)->gen < 5)
11114 return false;
11115
11116 if (i915.use_mmio_flip < 0)
11117 return false;
11118 else if (i915.use_mmio_flip > 0)
11119 return true;
14bf993e
OM		 11120 else if (i915.enable_execlists)
11121 return true;
84c33a64 11122 else
b4716185 11123 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 11124}
11125
ff944564
DL		 11126static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
11127{
11128 struct drm_device *dev = intel_crtc->base.dev;
11129 struct drm_i915_private *dev_priv = dev->dev_private;
11130 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 11131 const enum pipe pipe = intel_crtc->pipe;
11132 u32 ctl, stride;
11133
11134 ctl = I915_READ(PLANE_CTL(pipe, 0));
11135 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 11136 switch (fb->modifier[0]) {
11137 case DRM_FORMAT_MOD_NONE:
11138 break;
11139 case I915_FORMAT_MOD_X_TILED:
ff944564 11140 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 11141 break;
11142 case I915_FORMAT_MOD_Y_TILED:
11143 ctl |= PLANE_CTL_TILED_Y;
11144 break;
11145 case I915_FORMAT_MOD_Yf_TILED:
11146 ctl |= PLANE_CTL_TILED_YF;
11147 break;
11148 default:
11149 MISSING_CASE(fb->modifier[0]);
11150 }
ff944564
DL		 11151
11152 /*
11153 * The stride is either expressed as a multiple of 64 bytes chunks for
11154 * linear buffers or in number of tiles for tiled buffers.
11155 */
2ebef630
TU		 11156 stride = fb->pitches[0] /
11157 intel_fb_stride_alignment(dev, fb->modifier[0],
11158 fb->pixel_format);
ff944564
DL		 11159
11160 /*
11161 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
11162 * PLANE_SURF updates, the update is then guaranteed to be atomic.
11163 */
11164 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
11165 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
11166
11167 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
11168 POSTING_READ(PLANE_SURF(pipe, 0));
11169}
11170
11171static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 11172{
11173 struct drm_device *dev = intel_crtc->base.dev;
11174 struct drm_i915_private *dev_priv = dev->dev_private;
11175 struct intel_framebuffer *intel_fb =
11176 to_intel_framebuffer(intel_crtc->base.primary->fb);
11177 struct drm_i915_gem_object *obj = intel_fb->obj;
11178 u32 dspcntr;
11179 u32 reg;
11180
84c33a64
SG		 11181 reg = DSPCNTR(intel_crtc->plane);
11182 dspcntr = I915_READ(reg);
11183
c5d97472
DL		 11184 if (obj->tiling_mode != I915_TILING_NONE)
11185 dspcntr |= DISPPLANE_TILED;
11186 else
11187 dspcntr &= ~DISPPLANE_TILED;
11188
84c33a64
SG		 11189 I915_WRITE(reg, dspcntr);
11190
11191 I915_WRITE(DSPSURF(intel_crtc->plane),
11192 intel_crtc->unpin_work->gtt_offset);
11193 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 11194
ff944564
DL		 11195}
11196
11197/*
11198 * XXX: This is the temporary way to update the plane registers until we get
11199 * around to using the usual plane update functions for MMIO flips
11200 */
11201static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
11202{
11203 struct drm_device *dev = intel_crtc->base.dev;
11204 bool atomic_update;
11205 u32 start_vbl_count;
11206
11207 intel_mark_page_flip_active(intel_crtc);
11208
11209 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
11210
11211 if (INTEL_INFO(dev)->gen >= 9)
11212 skl_do_mmio_flip(intel_crtc);
11213 else
11214 /* use_mmio_flip() retricts MMIO flips to ilk+ */
11215 ilk_do_mmio_flip(intel_crtc);
11216
9362c7c5
ACO		 11217 if (atomic_update)
11218 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 11219}
11220
9362c7c5 11221static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 11222{
b2cfe0ab
CW		 11223 struct intel_mmio_flip *mmio_flip =
11224 container_of(work, struct intel_mmio_flip, work);
84c33a64 11225
eed29a5b
DV		 11226 if (mmio_flip->req)
11227 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 11228 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 11229 false, NULL,
11230 &mmio_flip->i915->rps.mmioflips));
84c33a64 11231
b2cfe0ab
CW		 11232 intel_do_mmio_flip(mmio_flip->crtc);
11233
eed29a5b 11234 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11235 kfree(mmio_flip);
84c33a64
SG		 11236}
11237
11238static int intel_queue_mmio_flip(struct drm_device *dev,
11239 struct drm_crtc *crtc,
11240 struct drm_framebuffer *fb,
11241 struct drm_i915_gem_object *obj,
11242 struct intel_engine_cs *ring,
11243 uint32_t flags)
11244{
b2cfe0ab
CW		 11245 struct intel_mmio_flip *mmio_flip;
11246
11247 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11248 if (mmio_flip == NULL)
11249 return -ENOMEM;
84c33a64 11250
bcafc4e3 11251 mmio_flip->i915 = to_i915(dev);
eed29a5b 11252 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11253 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11254
b2cfe0ab
CW		 11255 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11256 schedule_work(&mmio_flip->work);
84c33a64 11257
84c33a64
SG		 11258 return 0;
11259}
11260
8c9f3aaf
JB		 11261static int intel_default_queue_flip(struct drm_device *dev,
11262 struct drm_crtc *crtc,
11263 struct drm_framebuffer *fb,
ed8d1975 11264 struct drm_i915_gem_object *obj,
6258fbe2 11265 struct drm_i915_gem_request *req,
ed8d1975 11266 uint32_t flags)
8c9f3aaf
JB		 11267{
11268 return -ENODEV;
11269}
11270
d6bbafa1
CW		 11271static bool __intel_pageflip_stall_check(struct drm_device *dev,
11272 struct drm_crtc *crtc)
11273{
11274 struct drm_i915_private *dev_priv = dev->dev_private;
11275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11276 struct intel_unpin_work *work = intel_crtc->unpin_work;
11277 u32 addr;
11278
11279 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11280 return true;
11281
11282 if (!work->enable_stall_check)
11283 return false;
11284
11285 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11286 if (work->flip_queued_req &&
11287 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11288 return false;
11289
1e3feefd 11290 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11291 }
11292
1e3feefd 11293 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11294 return false;
11295
11296 /* Potential stall - if we see that the flip has happened,
11297 * assume a missed interrupt. */
11298 if (INTEL_INFO(dev)->gen >= 4)
11299 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11300 else
11301 addr = I915_READ(DSPADDR(intel_crtc->plane));
11302
11303 /* There is a potential issue here with a false positive after a flip
11304 * to the same address. We could address this by checking for a
11305 * non-incrementing frame counter.
11306 */
11307 return addr == work->gtt_offset;
11308}
11309
11310void intel_check_page_flip(struct drm_device *dev, int pipe)
11311{
11312 struct drm_i915_private *dev_priv = dev->dev_private;
11313 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11315 struct intel_unpin_work *work;
f326038a 11316
6c51d46f 11317 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11318
11319 if (crtc == NULL)
11320 return;
11321
f326038a 11322 spin_lock(&dev->event_lock);
6ad790c0
CW		 11323 work = intel_crtc->unpin_work;
11324 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11325 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11326 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11327 page_flip_completed(intel_crtc);
6ad790c0 11328 work = NULL;
d6bbafa1 11329 }
6ad790c0
CW		 11330 if (work != NULL &&
11331 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11332 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11333 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11334}
11335
6b95a207
KH		 11336static int intel_crtc_page_flip(struct drm_crtc *crtc,
11337 struct drm_framebuffer *fb,
ed8d1975
KP		 11338 struct drm_pending_vblank_event *event,
11339 uint32_t page_flip_flags)
6b95a207
KH		 11340{
11341 struct drm_device *dev = crtc->dev;
11342 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11343 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11344 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11346 struct drm_plane *primary = crtc->primary;
a071fa00 11347 enum pipe pipe = intel_crtc->pipe;
6b95a207 11348 struct intel_unpin_work *work;
a4872ba6 11349 struct intel_engine_cs *ring;
cf5d8a46 11350 bool mmio_flip;
91af127f 11351 struct drm_i915_gem_request *request = NULL;
52e68630 11352 int ret;
6b95a207 11353
2ff8fde1
MR		 11354 /*
11355 * drm_mode_page_flip_ioctl() should already catch this, but double
11356 * check to be safe. In the future we may enable pageflipping from
11357 * a disabled primary plane.
11358 */
11359 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11360 return -EBUSY;
11361
e6a595d2 11362 /* Can't change pixel format via MI display flips. */
f4510a27 11363 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11364 return -EINVAL;
11365
11366 /*
11367 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11368 * Note that pitch changes could also affect these register.
11369 */
11370 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11371 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11372 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11373 return -EINVAL;
11374
f900db47
CW		 11375 if (i915_terminally_wedged(&dev_priv->gpu_error))
11376 goto out_hang;
11377
b14c5679 11378 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11379 if (work == NULL)
11380 return -ENOMEM;
11381
6b95a207 11382 work->event = event;
b4a98e57 11383 work->crtc = crtc;
ab8d6675 11384 work->old_fb = old_fb;
6b95a207
KH		 11385 INIT_WORK(&work->work, intel_unpin_work_fn);
11386
87b6b101 11387 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11388 if (ret)
11389 goto free_work;
11390
6b95a207 11391 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11392 spin_lock_irq(&dev->event_lock);
6b95a207 11393 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11394 /* Before declaring the flip queue wedged, check if
11395 * the hardware completed the operation behind our backs.
11396 */
11397 if (__intel_pageflip_stall_check(dev, crtc)) {
11398 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11399 page_flip_completed(intel_crtc);
11400 } else {
11401 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11402 spin_unlock_irq(&dev->event_lock);
468f0b44 11403
d6bbafa1
CW		 11404 drm_crtc_vblank_put(crtc);
11405 kfree(work);
11406 return -EBUSY;
11407 }
6b95a207
KH		 11408 }
11409 intel_crtc->unpin_work = work;
5e2d7afc 11410 spin_unlock_irq(&dev->event_lock);
6b95a207 11411
b4a98e57
CW		 11412 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11413 flush_workqueue(dev_priv->wq);
11414
75dfca80 11415 /* Reference the objects for the scheduled work. */
ab8d6675 11416 drm_framebuffer_reference(work->old_fb);
05394f39 11417 drm_gem_object_reference(&obj->base);
6b95a207 11418
f4510a27 11419 crtc->primary->fb = fb;
afd65eb4 11420 update_state_fb(crtc->primary);
1ed1f968 11421
e1f99ce6 11422 work->pending_flip_obj = obj;
e1f99ce6 11423
89ed88ba
CW		 11424 ret = i915_mutex_lock_interruptible(dev);
11425 if (ret)
11426 goto cleanup;
11427
b4a98e57 11428 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11429 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11430
75f7f3ec 11431 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11432 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11433
4fa62c89
VS		 11434 if (IS_VALLEYVIEW(dev)) {
11435 ring = &dev_priv->ring[BCS];
ab8d6675 11436 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11437 /* vlv: DISPLAY_FLIP fails to change tiling */
11438 ring = NULL;
48bf5b2d 11439 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11440 ring = &dev_priv->ring[BCS];
4fa62c89 11441 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11442 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11443 if (ring == NULL || ring->id != RCS)
11444 ring = &dev_priv->ring[BCS];
11445 } else {
11446 ring = &dev_priv->ring[RCS];
11447 }
11448
cf5d8a46
CW		 11449 mmio_flip = use_mmio_flip(ring, obj);
11450
11451 /* When using CS flips, we want to emit semaphores between rings.
11452 * However, when using mmio flips we will create a task to do the
11453 * synchronisation, so all we want here is to pin the framebuffer
11454 * into the display plane and skip any waits.
11455 */
82bc3b2d 11456 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11457 crtc->primary->state,
91af127f 11458 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring, &request);
8c9f3aaf
JB		 11459 if (ret)
11460 goto cleanup_pending;
6b95a207 11461
121920fa
TU		 11462 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11463 + intel_crtc->dspaddr_offset;
4fa62c89 11464
cf5d8a46 11465 if (mmio_flip) {
84c33a64
SG		 11466 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11467 page_flip_flags);
d6bbafa1
CW		 11468 if (ret)
11469 goto cleanup_unpin;
11470
f06cc1b9
JH		 11471 i915_gem_request_assign(&work->flip_queued_req,
11472 obj->last_write_req);
d6bbafa1 11473 } else {
6258fbe2
JH		 11474 if (!request) {
11475 ret = i915_gem_request_alloc(ring, ring->default_context, &request);
11476 if (ret)
11477 goto cleanup_unpin;
11478 }
11479
11480 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, request,
d6bbafa1
CW		 11481 page_flip_flags);
11482 if (ret)
11483 goto cleanup_unpin;
11484
6258fbe2 11485 i915_gem_request_assign(&work->flip_queued_req, request);
d6bbafa1
CW		 11486 }
11487
91af127f 11488 if (request)
75289874 11489 i915_add_request_no_flush(request);
91af127f 11490
1e3feefd 11491 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11492 work->enable_stall_check = true;
4fa62c89 11493
ab8d6675 11494 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a9ff8714 11495 to_intel_plane(primary)->frontbuffer_bit);
c80ac854 11496 mutex_unlock(&dev->struct_mutex);
a071fa00 11497
7733b49b 11498 intel_fbc_disable(dev_priv);
a9ff8714
VS		 11499 intel_frontbuffer_flip_prepare(dev,
11500 to_intel_plane(primary)->frontbuffer_bit);
6b95a207 11501
e5510fac
JB		 11502 trace_i915_flip_request(intel_crtc->plane, obj);
11503
6b95a207 11504 return 0;
96b099fd 11505
4fa62c89 11506cleanup_unpin:
82bc3b2d 11507 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11508cleanup_pending:
91af127f
JH		 11509 if (request)
11510 i915_gem_request_cancel(request);
b4a98e57 11511 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11512 mutex_unlock(&dev->struct_mutex);
11513cleanup:
f4510a27 11514 crtc->primary->fb = old_fb;
afd65eb4 11515 update_state_fb(crtc->primary);
89ed88ba
CW		 11516
11517 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11518 drm_framebuffer_unreference(work->old_fb);
96b099fd 11519
5e2d7afc 11520 spin_lock_irq(&dev->event_lock);
96b099fd 11521 intel_crtc->unpin_work = NULL;
5e2d7afc 11522 spin_unlock_irq(&dev->event_lock);
96b099fd 11523
87b6b101 11524 drm_crtc_vblank_put(crtc);
7317c75e 11525free_work:
96b099fd
CW		 11526 kfree(work);
11527
f900db47 11528 if (ret == -EIO) {
02e0efb5
ML		 11529 struct drm_atomic_state *state;
11530 struct drm_plane_state *plane_state;
11531
f900db47 11532out_hang:
02e0efb5
ML		 11533 state = drm_atomic_state_alloc(dev);
11534 if (!state)
11535 return -ENOMEM;
11536 state->acquire_ctx = drm_modeset_legacy_acquire_ctx(crtc);
11537
11538retry:
11539 plane_state = drm_atomic_get_plane_state(state, primary);
11540 ret = PTR_ERR_OR_ZERO(plane_state);
11541 if (!ret) {
11542 drm_atomic_set_fb_for_plane(plane_state, fb);
11543
11544 ret = drm_atomic_set_crtc_for_plane(plane_state, crtc);
11545 if (!ret)
11546 ret = drm_atomic_commit(state);
11547 }
11548
11549 if (ret == -EDEADLK) {
11550 drm_modeset_backoff(state->acquire_ctx);
11551 drm_atomic_state_clear(state);
11552 goto retry;
11553 }
11554
11555 if (ret)
11556 drm_atomic_state_free(state);
11557
f0d3dad3 11558 if (ret == 0 && event) {
5e2d7afc 11559 spin_lock_irq(&dev->event_lock);
a071fa00 11560 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11561 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11562 }
f900db47 11563 }
96b099fd 11564 return ret;
6b95a207
KH		 11565}
11566
da20eabd
ML		 11567
11568/**
11569 * intel_wm_need_update - Check whether watermarks need updating
11570 * @plane: drm plane
11571 * @state: new plane state
11572 *
11573 * Check current plane state versus the new one to determine whether
11574 * watermarks need to be recalculated.
11575 *
11576 * Returns true or false.
11577 */
11578static bool intel_wm_need_update(struct drm_plane *plane,
11579 struct drm_plane_state *state)
11580{
11581 /* Update watermarks on tiling changes. */
11582 if (!plane->state->fb || !state->fb ||
11583 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
11584 plane->state->rotation != state->rotation)
11585 return true;
11586
11587 if (plane->state->crtc_w != state->crtc_w)
11588 return true;
11589
11590 return false;
11591}
11592
11593int intel_plane_atomic_calc_changes(struct drm_crtc_state *crtc_state,
11594 struct drm_plane_state *plane_state)
11595{
11596 struct drm_crtc *crtc = crtc_state->crtc;
11597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11598 struct drm_plane *plane = plane_state->plane;
11599 struct drm_device *dev = crtc->dev;
11600 struct drm_i915_private *dev_priv = dev->dev_private;
11601 struct intel_plane_state *old_plane_state =
11602 to_intel_plane_state(plane->state);
11603 int idx = intel_crtc->base.base.id, ret;
11604 int i = drm_plane_index(plane);
11605 bool mode_changed = needs_modeset(crtc_state);
11606 bool was_crtc_enabled = crtc->state->active;
11607 bool is_crtc_enabled = crtc_state->active;
11608
11609 bool turn_off, turn_on, visible, was_visible;
11610 struct drm_framebuffer *fb = plane_state->fb;
11611
11612 if (crtc_state && INTEL_INFO(dev)->gen >= 9 &&
11613 plane->type != DRM_PLANE_TYPE_CURSOR) {
11614 ret = skl_update_scaler_plane(
11615 to_intel_crtc_state(crtc_state),
11616 to_intel_plane_state(plane_state));
11617 if (ret)
11618 return ret;
11619 }
11620
11621 /*
11622 * Disabling a plane is always okay; we just need to update
11623 * fb tracking in a special way since cleanup_fb() won't
11624 * get called by the plane helpers.
11625 */
11626 if (old_plane_state->base.fb && !fb)
11627 intel_crtc->atomic.disabled_planes |= 1 << i;
11628
da20eabd
ML		 11629 was_visible = old_plane_state->visible;
11630 visible = to_intel_plane_state(plane_state)->visible;
11631
11632 if (!was_crtc_enabled && WARN_ON(was_visible))
11633 was_visible = false;
11634
11635 if (!is_crtc_enabled && WARN_ON(visible))
11636 visible = false;
11637
11638 if (!was_visible && !visible)
11639 return 0;
11640
11641 turn_off = was_visible && (!visible || mode_changed);
11642 turn_on = visible && (!was_visible || mode_changed);
11643
11644 DRM_DEBUG_ATOMIC("[CRTC:%i] has [PLANE:%i] with fb %i\n", idx,
11645 plane->base.id, fb ? fb->base.id : -1);
11646
11647 DRM_DEBUG_ATOMIC("[PLANE:%i] visible %i -> %i, off %i, on %i, ms %i\n",
11648 plane->base.id, was_visible, visible,
11649 turn_off, turn_on, mode_changed);
11650
852eb00d 11651 if (turn_on) {
f015c551 11652 intel_crtc->atomic.update_wm_pre = true;
852eb00d
VS		 11653 /* must disable cxsr around plane enable/disable */
11654 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11655 intel_crtc->atomic.disable_cxsr = true;
11656 /* to potentially re-enable cxsr */
11657 intel_crtc->atomic.wait_vblank = true;
11658 intel_crtc->atomic.update_wm_post = true;
11659 }
11660 } else if (turn_off) {
f015c551 11661 intel_crtc->atomic.update_wm_post = true;
852eb00d
VS		 11662 /* must disable cxsr around plane enable/disable */
11663 if (plane->type != DRM_PLANE_TYPE_CURSOR) {
11664 if (is_crtc_enabled)
11665 intel_crtc->atomic.wait_vblank = true;
11666 intel_crtc->atomic.disable_cxsr = true;
11667 }
11668 } else if (intel_wm_need_update(plane, plane_state)) {
f015c551 11669 intel_crtc->atomic.update_wm_pre = true;
852eb00d 11670 }
da20eabd 11671
a9ff8714
VS		 11672 if (visible)
11673 intel_crtc->atomic.fb_bits |=
11674 to_intel_plane(plane)->frontbuffer_bit;
11675
da20eabd
ML		 11676 switch (plane->type) {
11677 case DRM_PLANE_TYPE_PRIMARY:
da20eabd
ML		 11678 intel_crtc->atomic.wait_for_flips = true;
11679 intel_crtc->atomic.pre_disable_primary = turn_off;
11680 intel_crtc->atomic.post_enable_primary = turn_on;
11681
066cf55b
RV		 11682 if (turn_off) {
11683 /*
11684 * FIXME: Actually if we will still have any other
11685 * plane enabled on the pipe we could let IPS enabled
11686 * still, but for now lets consider that when we make
11687 * primary invisible by setting DSPCNTR to 0 on
11688 * update_primary_plane function IPS needs to be
11689 * disable.
11690 */
11691 intel_crtc->atomic.disable_ips = true;
11692
da20eabd 11693 intel_crtc->atomic.disable_fbc = true;
066cf55b 11694 }
da20eabd
ML		 11695
11696 /*
11697 * FBC does not work on some platforms for rotated
11698 * planes, so disable it when rotation is not 0 and
11699 * update it when rotation is set back to 0.
11700 *
11701 * FIXME: This is redundant with the fbc update done in
11702 * the primary plane enable function except that that
11703 * one is done too late. We eventually need to unify
11704 * this.
11705 */
11706
11707 if (visible &&
11708 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
11709 dev_priv->fbc.crtc == intel_crtc &&
11710 plane_state->rotation != BIT(DRM_ROTATE_0))
11711 intel_crtc->atomic.disable_fbc = true;
11712
11713 /*
11714 * BDW signals flip done immediately if the plane
11715 * is disabled, even if the plane enable is already
11716 * armed to occur at the next vblank :(
11717 */
11718 if (turn_on && IS_BROADWELL(dev))
11719 intel_crtc->atomic.wait_vblank = true;
11720
11721 intel_crtc->atomic.update_fbc |= visible || mode_changed;
11722 break;
11723 case DRM_PLANE_TYPE_CURSOR:
da20eabd
ML		 11724 break;
11725 case DRM_PLANE_TYPE_OVERLAY:
d032ffa0 11726 if (turn_off && !mode_changed) {
da20eabd
ML		 11727 intel_crtc->atomic.wait_vblank = true;
11728 intel_crtc->atomic.update_sprite_watermarks |=
11729 1 << i;
11730 }
da20eabd
ML		 11731 }
11732 return 0;
11733}
11734
6d3a1ce7
ML		 11735static bool encoders_cloneable(const struct intel_encoder *a,
11736 const struct intel_encoder *b)
11737{
11738 /* masks could be asymmetric, so check both ways */
11739 return a == b || (a->cloneable & (1 << b->type) &&
11740 b->cloneable & (1 << a->type));
11741}
11742
11743static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11744 struct intel_crtc *crtc,
11745 struct intel_encoder *encoder)
11746{
11747 struct intel_encoder *source_encoder;
11748 struct drm_connector *connector;
11749 struct drm_connector_state *connector_state;
11750 int i;
11751
11752 for_each_connector_in_state(state, connector, connector_state, i) {
11753 if (connector_state->crtc != &crtc->base)
11754 continue;
11755
11756 source_encoder =
11757 to_intel_encoder(connector_state->best_encoder);
11758 if (!encoders_cloneable(encoder, source_encoder))
11759 return false;
11760 }
11761
11762 return true;
11763}
11764
11765static bool check_encoder_cloning(struct drm_atomic_state *state,
11766 struct intel_crtc *crtc)
11767{
11768 struct intel_encoder *encoder;
11769 struct drm_connector *connector;
11770 struct drm_connector_state *connector_state;
11771 int i;
11772
11773 for_each_connector_in_state(state, connector, connector_state, i) {
11774 if (connector_state->crtc != &crtc->base)
11775 continue;
11776
11777 encoder = to_intel_encoder(connector_state->best_encoder);
11778 if (!check_single_encoder_cloning(state, crtc, encoder))
11779 return false;
11780 }
11781
11782 return true;
11783}
11784
11785static int intel_crtc_atomic_check(struct drm_crtc *crtc,
11786 struct drm_crtc_state *crtc_state)
11787{
cf5a15be 11788 struct drm_device *dev = crtc->dev;
ad421372 11789 struct drm_i915_private *dev_priv = dev->dev_private;
6d3a1ce7 11790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cf5a15be
ML		 11791 struct intel_crtc_state *pipe_config =
11792 to_intel_crtc_state(crtc_state);
6d3a1ce7 11793 struct drm_atomic_state *state = crtc_state->state;
ad421372 11794 int ret, idx = crtc->base.id;
6d3a1ce7
ML		 11795 bool mode_changed = needs_modeset(crtc_state);
11796
11797 if (mode_changed && !check_encoder_cloning(state, intel_crtc)) {
11798 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11799 return -EINVAL;
11800 }
11801
11802 I915_STATE_WARN(crtc->state->active != intel_crtc->active,
11803 "[CRTC:%i] mismatch between state->active(%i) and crtc->active(%i)\n",
11804 idx, crtc->state->active, intel_crtc->active);
11805
852eb00d
VS		 11806 if (mode_changed && !crtc_state->active)
11807 intel_crtc->atomic.update_wm_post = true;
eddfcbcd 11808
ad421372
ML		 11809 if (mode_changed && crtc_state->enable &&
11810 dev_priv->display.crtc_compute_clock &&
11811 !WARN_ON(pipe_config->shared_dpll != DPLL_ID_PRIVATE)) {
11812 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11813 pipe_config);
11814 if (ret)
11815 return ret;
11816 }
11817
e435d6e5
ML		 11818 ret = 0;
11819 if (INTEL_INFO(dev)->gen >= 9) {
11820 if (mode_changed)
11821 ret = skl_update_scaler_crtc(pipe_config);
11822
11823 if (!ret)
11824 ret = intel_atomic_setup_scalers(dev, intel_crtc,
11825 pipe_config);
11826 }
11827
11828 return ret;
6d3a1ce7
ML		 11829}
11830
65b38e0d 11831static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11832 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11833 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11834 .atomic_begin = intel_begin_crtc_commit,
11835 .atomic_flush = intel_finish_crtc_commit,
6d3a1ce7 11836 .atomic_check = intel_crtc_atomic_check,
f6e5b160
CW		 11837};
11838
9a935856
DV		 11839/**
11840 * intel_modeset_update_staged_output_state
11841 *
11842 * Updates the staged output configuration state, e.g. after we've read out the
11843 * current hw state.
11844 */
11845static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11846{
7668851f 11847 struct intel_crtc *crtc;
9a935856
DV		 11848 struct intel_encoder *encoder;
11849 struct intel_connector *connector;
f6e5b160 11850
3a3371ff 11851 for_each_intel_connector(dev, connector) {
9a935856
DV		 11852 connector->new_encoder =
11853 to_intel_encoder(connector->base.encoder);
11854 }
f6e5b160 11855
b2784e15 11856 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11857 encoder->new_crtc =
11858 to_intel_crtc(encoder->base.crtc);
11859 }
7668851f 11860
d3fcc808 11861 for_each_intel_crtc(dev, crtc) {
83d65738 11862 crtc->new_enabled = crtc->base.state->enable;
7668851f 11863 }
f6e5b160
CW		 11864}
11865
d29b2f9d
ACO		 11866/* Transitional helper to copy current connector/encoder state to
11867 * connector->state. This is needed so that code that is partially
11868 * converted to atomic does the right thing.
11869 */
11870static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11871{
11872 struct intel_connector *connector;
11873
11874 for_each_intel_connector(dev, connector) {
11875 if (connector->base.encoder) {
11876 connector->base.state->best_encoder =
11877 connector->base.encoder;
11878 connector->base.state->crtc =
11879 connector->base.encoder->crtc;
11880 } else {
11881 connector->base.state->best_encoder = NULL;
11882 connector->base.state->crtc = NULL;
11883 }
11884 }
11885}
11886
050f7aeb 11887static void
eba905b2 11888connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11889 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11890{
11891 int bpp = pipe_config->pipe_bpp;
11892
11893 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11894 connector->base.base.id,
c23cc417 11895 connector->base.name);
050f7aeb
DV		 11896
11897 /* Don't use an invalid EDID bpc value */
11898 if (connector->base.display_info.bpc &&
11899 connector->base.display_info.bpc * 3 < bpp) {
11900 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11901 bpp, connector->base.display_info.bpc*3);
11902 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11903 }
11904
11905 /* Clamp bpp to 8 on screens without EDID 1.4 */
11906 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11907 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11908 bpp);
11909 pipe_config->pipe_bpp = 24;
11910 }
11911}
11912
4e53c2e0 11913static int
050f7aeb 11914compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11915 struct intel_crtc_state *pipe_config)
4e53c2e0 11916{
050f7aeb 11917 struct drm_device *dev = crtc->base.dev;
1486017f 11918 struct drm_atomic_state *state;
da3ced29
ACO		 11919 struct drm_connector *connector;
11920 struct drm_connector_state *connector_state;
1486017f 11921 int bpp, i;
4e53c2e0 11922
d328c9d7 11923 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11924 bpp = 10*3;
d328c9d7
DV		 11925 else if (INTEL_INFO(dev)->gen >= 5)
11926 bpp = 12*3;
11927 else
11928 bpp = 8*3;
11929
4e53c2e0 11930
4e53c2e0
DV		 11931 pipe_config->pipe_bpp = bpp;
11932
1486017f
ACO		 11933 state = pipe_config->base.state;
11934
4e53c2e0 11935 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11936 for_each_connector_in_state(state, connector, connector_state, i) {
11937 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11938 continue;
11939
da3ced29
ACO		 11940 connected_sink_compute_bpp(to_intel_connector(connector),
11941 pipe_config);
4e53c2e0
DV		 11942 }
11943
11944 return bpp;
11945}
11946
644db711
DV		 11947static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11948{
11949 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11950 "type: 0x%x flags: 0x%x\n",
1342830c 11951 mode->crtc_clock,
644db711
DV		 11952 mode->crtc_hdisplay, mode->crtc_hsync_start,
11953 mode->crtc_hsync_end, mode->crtc_htotal,
11954 mode->crtc_vdisplay, mode->crtc_vsync_start,
11955 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11956}
11957
c0b03411 11958static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11959 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11960 const char *context)
11961{
6a60cd87
CK		 11962 struct drm_device *dev = crtc->base.dev;
11963 struct drm_plane *plane;
11964 struct intel_plane *intel_plane;
11965 struct intel_plane_state *state;
11966 struct drm_framebuffer *fb;
11967
11968 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11969 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11970
11971 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11972 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11973 pipe_config->pipe_bpp, pipe_config->dither);
11974 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11975 pipe_config->has_pch_encoder,
11976 pipe_config->fdi_lanes,
11977 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11978 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11979 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11980 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11981 pipe_config->has_dp_encoder,
11982 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11983 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11984 pipe_config->dp_m_n.tu);
b95af8be
VK		 11985
11986 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11987 pipe_config->has_dp_encoder,
11988 pipe_config->dp_m2_n2.gmch_m,
11989 pipe_config->dp_m2_n2.gmch_n,
11990 pipe_config->dp_m2_n2.link_m,
11991 pipe_config->dp_m2_n2.link_n,
11992 pipe_config->dp_m2_n2.tu);
11993
55072d19
DV		 11994 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11995 pipe_config->has_audio,
11996 pipe_config->has_infoframe);
11997
c0b03411 11998 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11999 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 12000 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 12001 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
12002 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 12003 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 12004 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
12005 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 12006 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
12007 crtc->num_scalers,
12008 pipe_config->scaler_state.scaler_users,
12009 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 12010 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
12011 pipe_config->gmch_pfit.control,
12012 pipe_config->gmch_pfit.pgm_ratios,
12013 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 12014 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 12015 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 12016 pipe_config->pch_pfit.size,
12017 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 12018 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 12019 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 12020
415ff0f6 12021 if (IS_BROXTON(dev)) {
05712c15 12022 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
415ff0f6 12023 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
c8453338 12024 "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
415ff0f6
TU		 12025 pipe_config->ddi_pll_sel,
12026 pipe_config->dpll_hw_state.ebb0,
05712c15 12027 pipe_config->dpll_hw_state.ebb4,
415ff0f6
TU		 12028 pipe_config->dpll_hw_state.pll0,
12029 pipe_config->dpll_hw_state.pll1,
12030 pipe_config->dpll_hw_state.pll2,
12031 pipe_config->dpll_hw_state.pll3,
12032 pipe_config->dpll_hw_state.pll6,
12033 pipe_config->dpll_hw_state.pll8,
05712c15 12034 pipe_config->dpll_hw_state.pll9,
c8453338 12035 pipe_config->dpll_hw_state.pll10,
415ff0f6
TU		 12036 pipe_config->dpll_hw_state.pcsdw12);
12037 } else if (IS_SKYLAKE(dev)) {
12038 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
12039 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
12040 pipe_config->ddi_pll_sel,
12041 pipe_config->dpll_hw_state.ctrl1,
12042 pipe_config->dpll_hw_state.cfgcr1,
12043 pipe_config->dpll_hw_state.cfgcr2);
12044 } else if (HAS_DDI(dev)) {
12045 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
12046 pipe_config->ddi_pll_sel,
12047 pipe_config->dpll_hw_state.wrpll);
12048 } else {
12049 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
12050 "fp0: 0x%x, fp1: 0x%x\n",
12051 pipe_config->dpll_hw_state.dpll,
12052 pipe_config->dpll_hw_state.dpll_md,
12053 pipe_config->dpll_hw_state.fp0,
12054 pipe_config->dpll_hw_state.fp1);
12055 }
12056
6a60cd87
CK		 12057 DRM_DEBUG_KMS("planes on this crtc\n");
12058 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
12059 intel_plane = to_intel_plane(plane);
12060 if (intel_plane->pipe != crtc->pipe)
12061 continue;
12062
12063 state = to_intel_plane_state(plane->state);
12064 fb = state->base.fb;
12065 if (!fb) {
12066 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
12067 "disabled, scaler_id = %d\n",
12068 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12069 plane->base.id, intel_plane->pipe,
12070 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
12071 drm_plane_index(plane), state->scaler_id);
12072 continue;
12073 }
12074
12075 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
12076 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
12077 plane->base.id, intel_plane->pipe,
12078 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
12079 drm_plane_index(plane));
12080 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
12081 fb->base.id, fb->width, fb->height, fb->pixel_format);
12082 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
12083 state->scaler_id,
12084 state->src.x1 >> 16, state->src.y1 >> 16,
12085 drm_rect_width(&state->src) >> 16,
12086 drm_rect_height(&state->src) >> 16,
12087 state->dst.x1, state->dst.y1,
12088 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
12089 }
c0b03411
DV		 12090}
12091
5448a00d 12092static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 12093{
5448a00d
ACO		 12094 struct drm_device *dev = state->dev;
12095 struct intel_encoder *encoder;
da3ced29 12096 struct drm_connector *connector;
5448a00d 12097 struct drm_connector_state *connector_state;
00f0b378 12098 unsigned int used_ports = 0;
5448a00d 12099 int i;
00f0b378
VS		 12100
12101 /*
12102 * Walk the connector list instead of the encoder
12103 * list to detect the problem on ddi platforms
12104 * where there's just one encoder per digital port.
12105 */
da3ced29 12106 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 12107 if (!connector_state->best_encoder)
00f0b378
VS		 12108 continue;
12109
5448a00d
ACO		 12110 encoder = to_intel_encoder(connector_state->best_encoder);
12111
12112 WARN_ON(!connector_state->crtc);
00f0b378
VS		 12113
12114 switch (encoder->type) {
12115 unsigned int port_mask;
12116 case INTEL_OUTPUT_UNKNOWN:
12117 if (WARN_ON(!HAS_DDI(dev)))
12118 break;
12119 case INTEL_OUTPUT_DISPLAYPORT:
12120 case INTEL_OUTPUT_HDMI:
12121 case INTEL_OUTPUT_EDP:
12122 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
12123
12124 /* the same port mustn't appear more than once */
12125 if (used_ports & port_mask)
12126 return false;
12127
12128 used_ports |= port_mask;
12129 default:
12130 break;
12131 }
12132 }
12133
12134 return true;
12135}
12136
83a57153
ACO		 12137static void
12138clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
12139{
12140 struct drm_crtc_state tmp_state;
663a3640 12141 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 12142 struct intel_dpll_hw_state dpll_hw_state;
12143 enum intel_dpll_id shared_dpll;
8504c74c 12144 uint32_t ddi_pll_sel;
83a57153 12145
7546a384
ACO		 12146 /* FIXME: before the switch to atomic started, a new pipe_config was
12147 * kzalloc'd. Code that depends on any field being zero should be
12148 * fixed, so that the crtc_state can be safely duplicated. For now,
12149 * only fields that are know to not cause problems are preserved. */
12150
83a57153 12151 tmp_state = crtc_state->base;
663a3640 12152 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 12153 shared_dpll = crtc_state->shared_dpll;
12154 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 12155 ddi_pll_sel = crtc_state->ddi_pll_sel;
4978cc93 12156
83a57153 12157 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 12158
83a57153 12159 crtc_state->base = tmp_state;
663a3640 12160 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 12161 crtc_state->shared_dpll = shared_dpll;
12162 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 12163 crtc_state->ddi_pll_sel = ddi_pll_sel;
83a57153
ACO		 12164}
12165
548ee15b 12166static int
b8cecdf5 12167intel_modeset_pipe_config(struct drm_crtc *crtc,
b359283a 12168 struct intel_crtc_state *pipe_config)
ee7b9f93 12169{
b359283a 12170 struct drm_atomic_state *state = pipe_config->base.state;
7758a113 12171 struct intel_encoder *encoder;
da3ced29 12172 struct drm_connector *connector;
0b901879 12173 struct drm_connector_state *connector_state;
d328c9d7 12174 int base_bpp, ret = -EINVAL;
0b901879 12175 int i;
e29c22c0 12176 bool retry = true;
ee7b9f93 12177
83a57153 12178 clear_intel_crtc_state(pipe_config);
7758a113 12179
e143a21c
DV		 12180 pipe_config->cpu_transcoder =
12181 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 12182
2960bc9c
ID		 12183 /*
12184 * Sanitize sync polarity flags based on requested ones. If neither
12185 * positive or negative polarity is requested, treat this as meaning
12186 * negative polarity.
12187 */
2d112de7 12188 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12189 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 12190 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 12191
2d112de7 12192 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 12193 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 12194 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 12195
050f7aeb
DV		 12196 /* Compute a starting value for pipe_config->pipe_bpp taking the source
12197 * plane pixel format and any sink constraints into account. Returns the
12198 * source plane bpp so that dithering can be selected on mismatches
12199 * after encoders and crtc also have had their say. */
d328c9d7
DV		 12200 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
12201 pipe_config);
12202 if (base_bpp < 0)
4e53c2e0
DV		 12203 goto fail;
12204
e41a56be
VS		 12205 /*
12206 * Determine the real pipe dimensions. Note that stereo modes can
12207 * increase the actual pipe size due to the frame doubling and
12208 * insertion of additional space for blanks between the frame. This
12209 * is stored in the crtc timings. We use the requested mode to do this
12210 * computation to clearly distinguish it from the adjusted mode, which
12211 * can be changed by the connectors in the below retry loop.
12212 */
2d112de7 12213 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 12214 &pipe_config->pipe_src_w,
12215 &pipe_config->pipe_src_h);
e41a56be 12216
e29c22c0 12217encoder_retry:
ef1b460d 12218 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 12219 pipe_config->port_clock = 0;
ef1b460d 12220 pipe_config->pixel_multiplier = 1;
ff9a6750 12221
135c81b8 12222 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 12223 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
12224 CRTC_STEREO_DOUBLE);
135c81b8 12225
7758a113
DV		 12226 /* Pass our mode to the connectors and the CRTC to give them a chance to
12227 * adjust it according to limitations or connector properties, and also
12228 * a chance to reject the mode entirely.
47f1c6c9 12229 */
da3ced29 12230 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 12231 if (connector_state->crtc != crtc)
7758a113 12232 continue;
7ae89233 12233
0b901879
ACO		 12234 encoder = to_intel_encoder(connector_state->best_encoder);
12235
efea6e8e
DV		 12236 if (!(encoder->compute_config(encoder, pipe_config))) {
12237 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 12238 goto fail;
12239 }
ee7b9f93 12240 }
47f1c6c9 12241
ff9a6750
DV		 12242 /* Set default port clock if not overwritten by the encoder. Needs to be
12243 * done afterwards in case the encoder adjusts the mode. */
12244 if (!pipe_config->port_clock)
2d112de7 12245 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 12246 * pipe_config->pixel_multiplier;
ff9a6750 12247
a43f6e0f 12248 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 12249 if (ret < 0) {
7758a113
DV		 12250 DRM_DEBUG_KMS("CRTC fixup failed\n");
12251 goto fail;
ee7b9f93 12252 }
e29c22c0
DV		 12253
12254 if (ret == RETRY) {
12255 if (WARN(!retry, "loop in pipe configuration computation\n")) {
12256 ret = -EINVAL;
12257 goto fail;
12258 }
12259
12260 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
12261 retry = false;
12262 goto encoder_retry;
12263 }
12264
d328c9d7 12265 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 12266 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 12267 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 12268
7758a113 12269fail:
548ee15b 12270 return ret;
ee7b9f93 12271}
47f1c6c9 12272
ea9d758d 12273static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 12274{
ea9d758d 12275 struct drm_encoder *encoder;
f6e5b160 12276 struct drm_device *dev = crtc->dev;
f6e5b160 12277
ea9d758d
DV		 12278 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
12279 if (encoder->crtc == crtc)
12280 return true;
12281
12282 return false;
12283}
12284
12285static void
0a9ab303 12286intel_modeset_update_state(struct drm_atomic_state *state)
ea9d758d 12287{
0a9ab303 12288 struct drm_device *dev = state->dev;
ea9d758d 12289 struct intel_encoder *intel_encoder;
0a9ab303
ACO		 12290 struct drm_crtc *crtc;
12291 struct drm_crtc_state *crtc_state;
ea9d758d 12292 struct drm_connector *connector;
8a75d157 12293 int i;
ea9d758d 12294
de419ab6 12295 intel_shared_dpll_commit(state);
ba41c0de 12296
b2784e15 12297 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 12298 if (!intel_encoder->base.crtc)
12299 continue;
12300
69024de8
ML		 12301 crtc = intel_encoder->base.crtc;
12302 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12303 if (!crtc_state || !needs_modeset(crtc->state))
12304 continue;
ea9d758d 12305
69024de8 12306 intel_encoder->connectors_active = false;
ea9d758d
DV		 12307 }
12308
3cb480bc 12309 drm_atomic_helper_update_legacy_modeset_state(state->dev, state);
f7217905 12310 intel_modeset_update_staged_output_state(state->dev);
ea9d758d 12311
7668851f 12312 /* Double check state. */
8a75d157 12313 for_each_crtc_in_state(state, crtc, crtc_state, i) {
0a9ab303 12314 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
3cb480bc
ML		 12315
12316 to_intel_crtc(crtc)->config = to_intel_crtc_state(crtc->state);
fc467a22
ML		 12317
12318 /* Update hwmode for vblank functions */
12319 if (crtc->state->active)
12320 crtc->hwmode = crtc->state->adjusted_mode;
12321 else
12322 crtc->hwmode.crtc_clock = 0;
ea9d758d
DV		 12323 }
12324
12325 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
12326 if (!connector->encoder || !connector->encoder->crtc)
12327 continue;
12328
69024de8
ML		 12329 crtc = connector->encoder->crtc;
12330 crtc_state = drm_atomic_get_existing_crtc_state(state, crtc);
12331 if (!crtc_state || !needs_modeset(crtc->state))
12332 continue;
ea9d758d 12333
53d9f4e9 12334 if (crtc->state->active) {
69024de8
ML		 12335 struct drm_property *dpms_property =
12336 dev->mode_config.dpms_property;
68d34720 12337
69024de8
ML		 12338 connector->dpms = DRM_MODE_DPMS_ON;
12339 drm_object_property_set_value(&connector->base, dpms_property, DRM_MODE_DPMS_ON);
ea9d758d 12340
69024de8
ML		 12341 intel_encoder = to_intel_encoder(connector->encoder);
12342 intel_encoder->connectors_active = true;
12343 } else
12344 connector->dpms = DRM_MODE_DPMS_OFF;
ea9d758d 12345 }
ea9d758d
DV		 12346}
12347
3bd26263 12348static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 12349{
3bd26263 12350 int diff;
f1f644dc
JB		 12351
12352 if (clock1 == clock2)
12353 return true;
12354
12355 if (!clock1 || !clock2)
12356 return false;
12357
12358 diff = abs(clock1 - clock2);
12359
12360 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
12361 return true;
12362
12363 return false;
12364}
12365
25c5b266
DV		 12366#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
12367 list_for_each_entry((intel_crtc), \
12368 &(dev)->mode_config.crtc_list, \
12369 base.head) \
0973f18f 12370 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 12371
cfb23ed6
ML		 12372
12373static bool
12374intel_compare_m_n(unsigned int m, unsigned int n,
12375 unsigned int m2, unsigned int n2,
12376 bool exact)
12377{
12378 if (m == m2 && n == n2)
12379 return true;
12380
12381 if (exact || !m || !n || !m2 || !n2)
12382 return false;
12383
12384 BUILD_BUG_ON(DATA_LINK_M_N_MASK > INT_MAX);
12385
12386 if (m > m2) {
12387 while (m > m2) {
12388 m2 <<= 1;
12389 n2 <<= 1;
12390 }
12391 } else if (m < m2) {
12392 while (m < m2) {
12393 m <<= 1;
12394 n <<= 1;
12395 }
12396 }
12397
12398 return m == m2 && n == n2;
12399}
12400
12401static bool
12402intel_compare_link_m_n(const struct intel_link_m_n *m_n,
12403 struct intel_link_m_n *m2_n2,
12404 bool adjust)
12405{
12406 if (m_n->tu == m2_n2->tu &&
12407 intel_compare_m_n(m_n->gmch_m, m_n->gmch_n,
12408 m2_n2->gmch_m, m2_n2->gmch_n, !adjust) &&
12409 intel_compare_m_n(m_n->link_m, m_n->link_n,
12410 m2_n2->link_m, m2_n2->link_n, !adjust)) {
12411 if (adjust)
12412 *m2_n2 = *m_n;
12413
12414 return true;
12415 }
12416
12417 return false;
12418}
12419
0e8ffe1b 12420static bool
2fa2fe9a 12421intel_pipe_config_compare(struct drm_device *dev,
5cec258b 12422 struct intel_crtc_state *current_config,
cfb23ed6
ML		 12423 struct intel_crtc_state *pipe_config,
12424 bool adjust)
0e8ffe1b 12425{
cfb23ed6
ML		 12426 bool ret = true;
12427
12428#define INTEL_ERR_OR_DBG_KMS(fmt, ...) \
12429 do { \
12430 if (!adjust) \
12431 DRM_ERROR(fmt, ##__VA_ARGS__); \
12432 else \
12433 DRM_DEBUG_KMS(fmt, ##__VA_ARGS__); \
12434 } while (0)
12435
66e985c0
DV		 12436#define PIPE_CONF_CHECK_X(name) \
12437 if (current_config->name != pipe_config->name) { \
cfb23ed6 12438 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
66e985c0
DV		 12439 "(expected 0x%08x, found 0x%08x)\n", \
12440 current_config->name, \
12441 pipe_config->name); \
cfb23ed6 12442 ret = false; \
66e985c0
DV		 12443 }
12444
08a24034
DV		 12445#define PIPE_CONF_CHECK_I(name) \
12446 if (current_config->name != pipe_config->name) { \
cfb23ed6 12447 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
08a24034
DV		 12448 "(expected %i, found %i)\n", \
12449 current_config->name, \
12450 pipe_config->name); \
cfb23ed6
ML		 12451 ret = false; \
12452 }
12453
12454#define PIPE_CONF_CHECK_M_N(name) \
12455 if (!intel_compare_link_m_n(&current_config->name, \
12456 &pipe_config->name,\
12457 adjust)) { \
12458 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12459 "(expected tu %i gmch %i/%i link %i/%i, " \
12460 "found tu %i, gmch %i/%i link %i/%i)\n", \
12461 current_config->name.tu, \
12462 current_config->name.gmch_m, \
12463 current_config->name.gmch_n, \
12464 current_config->name.link_m, \
12465 current_config->name.link_n, \
12466 pipe_config->name.tu, \
12467 pipe_config->name.gmch_m, \
12468 pipe_config->name.gmch_n, \
12469 pipe_config->name.link_m, \
12470 pipe_config->name.link_n); \
12471 ret = false; \
12472 }
12473
12474#define PIPE_CONF_CHECK_M_N_ALT(name, alt_name) \
12475 if (!intel_compare_link_m_n(&current_config->name, \
12476 &pipe_config->name, adjust) && \
12477 !intel_compare_link_m_n(&current_config->alt_name, \
12478 &pipe_config->name, adjust)) { \
12479 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
12480 "(expected tu %i gmch %i/%i link %i/%i, " \
12481 "or tu %i gmch %i/%i link %i/%i, " \
12482 "found tu %i, gmch %i/%i link %i/%i)\n", \
12483 current_config->name.tu, \
12484 current_config->name.gmch_m, \
12485 current_config->name.gmch_n, \
12486 current_config->name.link_m, \
12487 current_config->name.link_n, \
12488 current_config->alt_name.tu, \
12489 current_config->alt_name.gmch_m, \
12490 current_config->alt_name.gmch_n, \
12491 current_config->alt_name.link_m, \
12492 current_config->alt_name.link_n, \
12493 pipe_config->name.tu, \
12494 pipe_config->name.gmch_m, \
12495 pipe_config->name.gmch_n, \
12496 pipe_config->name.link_m, \
12497 pipe_config->name.link_n); \
12498 ret = false; \
88adfff1
DV		 12499 }
12500
b95af8be
VK		 12501/* This is required for BDW+ where there is only one set of registers for
12502 * switching between high and low RR.
12503 * This macro can be used whenever a comparison has to be made between one
12504 * hw state and multiple sw state variables.
12505 */
12506#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
12507 if ((current_config->name != pipe_config->name) && \
12508 (current_config->alt_name != pipe_config->name)) { \
cfb23ed6 12509 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
b95af8be
VK		 12510 "(expected %i or %i, found %i)\n", \
12511 current_config->name, \
12512 current_config->alt_name, \
12513 pipe_config->name); \
cfb23ed6 12514 ret = false; \
b95af8be
VK		 12515 }
12516
1bd1bd80
DV		 12517#define PIPE_CONF_CHECK_FLAGS(name, mask) \
12518 if ((current_config->name ^ pipe_config->name) & (mask)) { \
cfb23ed6 12519 INTEL_ERR_OR_DBG_KMS("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 12520 "(expected %i, found %i)\n", \
12521 current_config->name & (mask), \
12522 pipe_config->name & (mask)); \
cfb23ed6 12523 ret = false; \
1bd1bd80
DV		 12524 }
12525
5e550656
VS		 12526#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
12527 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
cfb23ed6 12528 INTEL_ERR_OR_DBG_KMS("mismatch in " #name " " \
5e550656
VS		 12529 "(expected %i, found %i)\n", \
12530 current_config->name, \
12531 pipe_config->name); \
cfb23ed6 12532 ret = false; \
5e550656
VS		 12533 }
12534
bb760063
DV		 12535#define PIPE_CONF_QUIRK(quirk) \
12536 ((current_config->quirks | pipe_config->quirks) & (quirk))
12537
eccb140b
DV		 12538 PIPE_CONF_CHECK_I(cpu_transcoder);
12539
08a24034
DV		 12540 PIPE_CONF_CHECK_I(has_pch_encoder);
12541 PIPE_CONF_CHECK_I(fdi_lanes);
cfb23ed6 12542 PIPE_CONF_CHECK_M_N(fdi_m_n);
08a24034 12543
eb14cb74 12544 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 12545
12546 if (INTEL_INFO(dev)->gen < 8) {
cfb23ed6
ML		 12547 PIPE_CONF_CHECK_M_N(dp_m_n);
12548
12549 PIPE_CONF_CHECK_I(has_drrs);
12550 if (current_config->has_drrs)
12551 PIPE_CONF_CHECK_M_N(dp_m2_n2);
12552 } else
12553 PIPE_CONF_CHECK_M_N_ALT(dp_m_n, dp_m2_n2);
eb14cb74 12554
2d112de7
ACO		 12555 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12556 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12557 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12558 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12559 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12560 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12561
2d112de7
ACO		 12562 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12563 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12564 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12565 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12566 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12567 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12568
c93f54cf 12569 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12570 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12571 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12572 IS_VALLEYVIEW(dev))
12573 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12574 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12575
9ed109a7
DV		 12576 PIPE_CONF_CHECK_I(has_audio);
12577
2d112de7 12578 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12579 DRM_MODE_FLAG_INTERLACE);
12580
bb760063 12581 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12582 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12583 DRM_MODE_FLAG_PHSYNC);
2d112de7 12584 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12585 DRM_MODE_FLAG_NHSYNC);
2d112de7 12586 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12587 DRM_MODE_FLAG_PVSYNC);
2d112de7 12588 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12589 DRM_MODE_FLAG_NVSYNC);
12590 }
045ac3b5 12591
37327abd
VS		 12592 PIPE_CONF_CHECK_I(pipe_src_w);
12593 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12594
9953599b
DV		 12595 /*
12596 * FIXME: BIOS likes to set up a cloned config with lvds+external
12597 * screen. Since we don't yet re-compute the pipe config when moving
12598 * just the lvds port away to another pipe the sw tracking won't match.
12599 *
12600 * Proper atomic modesets with recomputed global state will fix this.
12601 * Until then just don't check gmch state for inherited modes.
12602 */
12603 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12604 PIPE_CONF_CHECK_I(gmch_pfit.control);
12605 /* pfit ratios are autocomputed by the hw on gen4+ */
12606 if (INTEL_INFO(dev)->gen < 4)
12607 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12608 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12609 }
12610
fd4daa9c
CW		 12611 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12612 if (current_config->pch_pfit.enabled) {
12613 PIPE_CONF_CHECK_I(pch_pfit.pos);
12614 PIPE_CONF_CHECK_I(pch_pfit.size);
12615 }
2fa2fe9a 12616
a1b2278e
CK		 12617 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12618
e59150dc
JB		 12619 /* BDW+ don't expose a synchronous way to read the state */
12620 if (IS_HASWELL(dev))
12621 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12622
282740f7
VS		 12623 PIPE_CONF_CHECK_I(double_wide);
12624
26804afd
DV		 12625 PIPE_CONF_CHECK_X(ddi_pll_sel);
12626
c0d43d62 12627 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12628 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12629 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12630 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12631 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12632 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12633 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12634 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12635 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12636
42571aef
VS		 12637 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12638 PIPE_CONF_CHECK_I(pipe_bpp);
12639
2d112de7 12640 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12641 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12642
66e985c0 12643#undef PIPE_CONF_CHECK_X
08a24034 12644#undef PIPE_CONF_CHECK_I
b95af8be 12645#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12646#undef PIPE_CONF_CHECK_FLAGS
5e550656 12647#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12648#undef PIPE_CONF_QUIRK
cfb23ed6 12649#undef INTEL_ERR_OR_DBG_KMS
88adfff1 12650
cfb23ed6 12651 return ret;
0e8ffe1b
DV		 12652}
12653
08db6652
DL		 12654static void check_wm_state(struct drm_device *dev)
12655{
12656 struct drm_i915_private *dev_priv = dev->dev_private;
12657 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12658 struct intel_crtc *intel_crtc;
12659 int plane;
12660
12661 if (INTEL_INFO(dev)->gen < 9)
12662 return;
12663
12664 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12665 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12666
12667 for_each_intel_crtc(dev, intel_crtc) {
12668 struct skl_ddb_entry *hw_entry, *sw_entry;
12669 const enum pipe pipe = intel_crtc->pipe;
12670
12671 if (!intel_crtc->active)
12672 continue;
12673
12674 /* planes */
dd740780 12675 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12676 hw_entry = &hw_ddb.plane[pipe][plane];
12677 sw_entry = &sw_ddb->plane[pipe][plane];
12678
12679 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12680 continue;
12681
12682 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12683 "(expected (%u,%u), found (%u,%u))\n",
12684 pipe_name(pipe), plane + 1,
12685 sw_entry->start, sw_entry->end,
12686 hw_entry->start, hw_entry->end);
12687 }
12688
12689 /* cursor */
12690 hw_entry = &hw_ddb.cursor[pipe];
12691 sw_entry = &sw_ddb->cursor[pipe];
12692
12693 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12694 continue;
12695
12696 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12697 "(expected (%u,%u), found (%u,%u))\n",
12698 pipe_name(pipe),
12699 sw_entry->start, sw_entry->end,
12700 hw_entry->start, hw_entry->end);
12701 }
12702}
12703
91d1b4bd
DV		 12704static void
12705check_connector_state(struct drm_device *dev)
8af6cf88 12706{
8af6cf88
DV		 12707 struct intel_connector *connector;
12708
3a3371ff 12709 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12710 /* This also checks the encoder/connector hw state with the
12711 * ->get_hw_state callbacks. */
12712 intel_connector_check_state(connector);
12713
e2c719b7 12714 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 12715 "connector's staged encoder doesn't match current encoder\n");
12716 }
91d1b4bd
DV		 12717}
12718
12719static void
12720check_encoder_state(struct drm_device *dev)
12721{
12722 struct intel_encoder *encoder;
12723 struct intel_connector *connector;
8af6cf88 12724
b2784e15 12725 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12726 bool enabled = false;
12727 bool active = false;
12728 enum pipe pipe, tracked_pipe;
12729
12730 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12731 encoder->base.base.id,
8e329a03 12732 encoder->base.name);
8af6cf88 12733
e2c719b7 12734 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 12735 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 12736 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 12737 "encoder's active_connectors set, but no crtc\n");
12738
3a3371ff 12739 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12740 if (connector->base.encoder != &encoder->base)
12741 continue;
12742 enabled = true;
12743 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12744 active = true;
12745 }
0e32b39c
DA		 12746 /*
12747 * for MST connectors if we unplug the connector is gone
12748 * away but the encoder is still connected to a crtc
12749 * until a modeset happens in response to the hotplug.
12750 */
12751 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12752 continue;
12753
e2c719b7 12754 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12755 "encoder's enabled state mismatch "
12756 "(expected %i, found %i)\n",
12757 !!encoder->base.crtc, enabled);
e2c719b7 12758 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 12759 "active encoder with no crtc\n");
12760
e2c719b7 12761 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 12762 "encoder's computed active state doesn't match tracked active state "
12763 "(expected %i, found %i)\n", active, encoder->connectors_active);
12764
12765 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 12766 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 12767 "encoder's hw state doesn't match sw tracking "
12768 "(expected %i, found %i)\n",
12769 encoder->connectors_active, active);
12770
12771 if (!encoder->base.crtc)
12772 continue;
12773
12774 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 12775 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 12776 "active encoder's pipe doesn't match"
12777 "(expected %i, found %i)\n",
12778 tracked_pipe, pipe);
12779
12780 }
91d1b4bd
DV		 12781}
12782
12783static void
12784check_crtc_state(struct drm_device *dev)
12785{
fbee40df 12786 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12787 struct intel_crtc *crtc;
12788 struct intel_encoder *encoder;
5cec258b 12789 struct intel_crtc_state pipe_config;
8af6cf88 12790
d3fcc808 12791 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 12792 bool enabled = false;
12793 bool active = false;
12794
045ac3b5
JB		 12795 memset(&pipe_config, 0, sizeof(pipe_config));
12796
8af6cf88
DV		 12797 DRM_DEBUG_KMS("[CRTC:%d]\n",
12798 crtc->base.base.id);
12799
83d65738 12800 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 12801 "active crtc, but not enabled in sw tracking\n");
12802
b2784e15 12803 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12804 if (encoder->base.crtc != &crtc->base)
12805 continue;
12806 enabled = true;
12807 if (encoder->connectors_active)
12808 active = true;
12809 }
6c49f241 12810
e2c719b7 12811 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 12812 "crtc's computed active state doesn't match tracked active state "
12813 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12814 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12815 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 12816 "(expected %i, found %i)\n", enabled,
12817 crtc->base.state->enable);
8af6cf88 12818
0e8ffe1b
DV		 12819 active = dev_priv->display.get_pipe_config(crtc,
12820 &pipe_config);
d62cf62a 12821
b6b5d049
VS		 12822 /* hw state is inconsistent with the pipe quirk */
12823 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12824 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 12825 active = crtc->active;
12826
b2784e15 12827 for_each_intel_encoder(dev, encoder) {
3eaba51c 12828 enum pipe pipe;
6c49f241
DV		 12829 if (encoder->base.crtc != &crtc->base)
12830 continue;
1d37b689 12831 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 12832 encoder->get_config(encoder, &pipe_config);
12833 }
12834
e2c719b7 12835 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 12836 "crtc active state doesn't match with hw state "
12837 "(expected %i, found %i)\n", crtc->active, active);
12838
53d9f4e9
ML		 12839 I915_STATE_WARN(crtc->active != crtc->base.state->active,
12840 "transitional active state does not match atomic hw state "
12841 "(expected %i, found %i)\n", crtc->base.state->active, crtc->active);
12842
cfb23ed6
ML		 12843 if (!active)
12844 continue;
12845
12846 if (!intel_pipe_config_compare(dev, crtc->config,
12847 &pipe_config, false)) {
e2c719b7 12848 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 12849 intel_dump_pipe_config(crtc, &pipe_config,
12850 "[hw state]");
6e3c9717 12851 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12852 "[sw state]");
12853 }
8af6cf88
DV		 12854 }
12855}
12856
91d1b4bd
DV		 12857static void
12858check_shared_dpll_state(struct drm_device *dev)
12859{
fbee40df 12860 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12861 struct intel_crtc *crtc;
12862 struct intel_dpll_hw_state dpll_hw_state;
12863 int i;
5358901f
DV		 12864
12865 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12866 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12867 int enabled_crtcs = 0, active_crtcs = 0;
12868 bool active;
12869
12870 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12871
12872 DRM_DEBUG_KMS("%s\n", pll->name);
12873
12874 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12875
e2c719b7 12876 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12877 "more active pll users than references: %i vs %i\n",
3e369b76 12878 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12879 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12880 "pll in active use but not on in sw tracking\n");
e2c719b7 12881 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12882 "pll in on but not on in use in sw tracking\n");
e2c719b7 12883 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12884 "pll on state mismatch (expected %i, found %i)\n",
12885 pll->on, active);
12886
d3fcc808 12887 for_each_intel_crtc(dev, crtc) {
83d65738 12888 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12889 enabled_crtcs++;
12890 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12891 active_crtcs++;
12892 }
e2c719b7 12893 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12894 "pll active crtcs mismatch (expected %i, found %i)\n",
12895 pll->active, active_crtcs);
e2c719b7 12896 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12897 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12898 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12899
e2c719b7 12900 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12901 sizeof(dpll_hw_state)),
12902 "pll hw state mismatch\n");
5358901f 12903 }
8af6cf88
DV		 12904}
12905
91d1b4bd
DV		 12906void
12907intel_modeset_check_state(struct drm_device *dev)
12908{
08db6652 12909 check_wm_state(dev);
91d1b4bd
DV		 12910 check_connector_state(dev);
12911 check_encoder_state(dev);
12912 check_crtc_state(dev);
12913 check_shared_dpll_state(dev);
12914}
12915
5cec258b 12916void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12917 int dotclock)
12918{
12919 /*
12920 * FDI already provided one idea for the dotclock.
12921 * Yell if the encoder disagrees.
12922 */
2d112de7 12923 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12924 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12925 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12926}
12927
80715b2f
VS		 12928static void update_scanline_offset(struct intel_crtc *crtc)
12929{
12930 struct drm_device *dev = crtc->base.dev;
12931
12932 /*
12933 * The scanline counter increments at the leading edge of hsync.
12934 *
12935 * On most platforms it starts counting from vtotal-1 on the
12936 * first active line. That means the scanline counter value is
12937 * always one less than what we would expect. Ie. just after
12938 * start of vblank, which also occurs at start of hsync (on the
12939 * last active line), the scanline counter will read vblank_start-1.
12940 *
12941 * On gen2 the scanline counter starts counting from 1 instead
12942 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12943 * to keep the value positive), instead of adding one.
12944 *
12945 * On HSW+ the behaviour of the scanline counter depends on the output
12946 * type. For DP ports it behaves like most other platforms, but on HDMI
12947 * there's an extra 1 line difference. So we need to add two instead of
12948 * one to the value.
12949 */
12950 if (IS_GEN2(dev)) {
6e3c9717 12951 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12952 int vtotal;
12953
12954 vtotal = mode->crtc_vtotal;
12955 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12956 vtotal /= 2;
12957
12958 crtc->scanline_offset = vtotal - 1;
12959 } else if (HAS_DDI(dev) &&
409ee761 12960 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12961 crtc->scanline_offset = 2;
12962 } else
12963 crtc->scanline_offset = 1;
12964}
12965
ad421372 12966static void intel_modeset_clear_plls(struct drm_atomic_state *state)
ed6739ef 12967{
225da59b 12968 struct drm_device *dev = state->dev;
ed6739ef 12969 struct drm_i915_private *dev_priv = to_i915(dev);
ad421372 12970 struct intel_shared_dpll_config *shared_dpll = NULL;
ed6739ef 12971 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12972 struct intel_crtc_state *intel_crtc_state;
12973 struct drm_crtc *crtc;
12974 struct drm_crtc_state *crtc_state;
0a9ab303 12975 int i;
ed6739ef
ACO		 12976
12977 if (!dev_priv->display.crtc_compute_clock)
ad421372 12978 return;
ed6739ef 12979
0a9ab303 12980 for_each_crtc_in_state(state, crtc, crtc_state, i) {
ad421372
ML		 12981 int dpll;
12982
0a9ab303 12983 intel_crtc = to_intel_crtc(crtc);
4978cc93 12984 intel_crtc_state = to_intel_crtc_state(crtc_state);
ad421372 12985 dpll = intel_crtc_state->shared_dpll;
0a9ab303 12986
ad421372 12987 if (!needs_modeset(crtc_state) || dpll == DPLL_ID_PRIVATE)
225da59b
ACO		 12988 continue;
12989
ad421372 12990 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
0a9ab303 12991
ad421372
ML		 12992 if (!shared_dpll)
12993 shared_dpll = intel_atomic_get_shared_dpll_state(state);
ed6739ef 12994
ad421372
ML		 12995 shared_dpll[dpll].crtc_mask &= ~(1 << intel_crtc->pipe);
12996 }
ed6739ef
ACO		 12997}
12998
99d736a2
ML		 12999/*
13000 * This implements the workaround described in the "notes" section of the mode
13001 * set sequence documentation. When going from no pipes or single pipe to
13002 * multiple pipes, and planes are enabled after the pipe, we need to wait at
13003 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
13004 */
13005static int haswell_mode_set_planes_workaround(struct drm_atomic_state *state)
13006{
13007 struct drm_crtc_state *crtc_state;
13008 struct intel_crtc *intel_crtc;
13009 struct drm_crtc *crtc;
13010 struct intel_crtc_state *first_crtc_state = NULL;
13011 struct intel_crtc_state *other_crtc_state = NULL;
13012 enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
13013 int i;
13014
13015 /* look at all crtc's that are going to be enabled in during modeset */
13016 for_each_crtc_in_state(state, crtc, crtc_state, i) {
13017 intel_crtc = to_intel_crtc(crtc);
13018
13019 if (!crtc_state->active || !needs_modeset(crtc_state))
13020 continue;
13021
13022 if (first_crtc_state) {
13023 other_crtc_state = to_intel_crtc_state(crtc_state);
13024 break;
13025 } else {
13026 first_crtc_state = to_intel_crtc_state(crtc_state);
13027 first_pipe = intel_crtc->pipe;
13028 }
13029 }
13030
13031 /* No workaround needed? */
13032 if (!first_crtc_state)
13033 return 0;
13034
13035 /* w/a possibly needed, check how many crtc's are already enabled. */
13036 for_each_intel_crtc(state->dev, intel_crtc) {
13037 struct intel_crtc_state *pipe_config;
13038
13039 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
13040 if (IS_ERR(pipe_config))
13041 return PTR_ERR(pipe_config);
13042
13043 pipe_config->hsw_workaround_pipe = INVALID_PIPE;
13044
13045 if (!pipe_config->base.active ||
13046 needs_modeset(&pipe_config->base))
13047 continue;
13048
13049 /* 2 or more enabled crtcs means no need for w/a */
13050 if (enabled_pipe != INVALID_PIPE)
13051 return 0;
13052
13053 enabled_pipe = intel_crtc->pipe;
13054 }
13055
13056 if (enabled_pipe != INVALID_PIPE)
13057 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
13058 else if (other_crtc_state)
13059 other_crtc_state->hsw_workaround_pipe = first_pipe;
13060
13061 return 0;
13062}
13063
27c329ed
ML		 13064static int intel_modeset_all_pipes(struct drm_atomic_state *state)
13065{
13066 struct drm_crtc *crtc;
13067 struct drm_crtc_state *crtc_state;
13068 int ret = 0;
13069
13070 /* add all active pipes to the state */
13071 for_each_crtc(state->dev, crtc) {
13072 crtc_state = drm_atomic_get_crtc_state(state, crtc);
13073 if (IS_ERR(crtc_state))
13074 return PTR_ERR(crtc_state);
13075
13076 if (!crtc_state->active || needs_modeset(crtc_state))
13077 continue;
13078
13079 crtc_state->mode_changed = true;
13080
13081 ret = drm_atomic_add_affected_connectors(state, crtc);
13082 if (ret)
13083 break;
13084
13085 ret = drm_atomic_add_affected_planes(state, crtc);
13086 if (ret)
13087 break;
13088 }
13089
13090 return ret;
13091}
13092
13093
054518dd 13094/* Code that should eventually be part of atomic_check() */
c347a676 13095static int intel_modeset_checks(struct drm_atomic_state *state)
054518dd
ACO		 13096{
13097 struct drm_device *dev = state->dev;
27c329ed 13098 struct drm_i915_private *dev_priv = dev->dev_private;
054518dd
ACO		 13099 int ret;
13100
b359283a
ML		 13101 if (!check_digital_port_conflicts(state)) {
13102 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
13103 return -EINVAL;
13104 }
13105
054518dd
ACO		 13106 /*
13107 * See if the config requires any additional preparation, e.g.
13108 * to adjust global state with pipes off. We need to do this
13109 * here so we can get the modeset_pipe updated config for the new
13110 * mode set on this crtc. For other crtcs we need to use the
13111 * adjusted_mode bits in the crtc directly.
13112 */
27c329ed
ML		 13113 if (dev_priv->display.modeset_calc_cdclk) {
13114 unsigned int cdclk;
b432e5cf 13115
27c329ed
ML		 13116 ret = dev_priv->display.modeset_calc_cdclk(state);
13117
13118 cdclk = to_intel_atomic_state(state)->cdclk;
13119 if (!ret && cdclk != dev_priv->cdclk_freq)
13120 ret = intel_modeset_all_pipes(state);
13121
13122 if (ret < 0)
054518dd 13123 return ret;
27c329ed
ML		 13124 } else
13125 to_intel_atomic_state(state)->cdclk = dev_priv->cdclk_freq;
054518dd 13126
ad421372 13127 intel_modeset_clear_plls(state);
054518dd 13128
99d736a2 13129 if (IS_HASWELL(dev))
ad421372 13130 return haswell_mode_set_planes_workaround(state);
99d736a2 13131
ad421372 13132 return 0;
c347a676
ACO		 13133}
13134
13135static int
13136intel_modeset_compute_config(struct drm_atomic_state *state)
13137{
13138 struct drm_crtc *crtc;
13139 struct drm_crtc_state *crtc_state;
13140 int ret, i;
61333b60 13141 bool any_ms = false;
c347a676
ACO		 13142
13143 ret = drm_atomic_helper_check_modeset(state->dev, state);
054518dd
ACO		 13144 if (ret)
13145 return ret;
13146
c347a676 13147 for_each_crtc_in_state(state, crtc, crtc_state, i) {
cfb23ed6
ML		 13148 struct intel_crtc_state *pipe_config =
13149 to_intel_crtc_state(crtc_state);
5c1e3426 13150 bool modeset, recalc = false;
cfb23ed6 13151
61333b60
ML		 13152 if (!crtc_state->enable) {
13153 if (needs_modeset(crtc_state))
13154 any_ms = true;
c347a676 13155 continue;
61333b60 13156 }
c347a676 13157
cfb23ed6 13158 modeset = needs_modeset(crtc_state);
5c1e3426
ML		 13159 /* see comment in intel_modeset_readout_hw_state */
13160 if (!modeset && crtc_state->mode_blob != crtc->state->mode_blob &&
13161 pipe_config->quirks & PIPE_CONFIG_QUIRK_INHERITED_MODE)
13162 recalc = true;
cfb23ed6
ML		 13163
13164 if (!modeset && !recalc)
13165 continue;
13166
13167 if (recalc) {
b359283a
ML		 13168 ret = drm_atomic_add_affected_connectors(state, crtc);
13169 if (ret)
13170 return ret;
13171 }
13172
cfb23ed6 13173 ret = intel_modeset_pipe_config(crtc, pipe_config);
c347a676
ACO		 13174 if (ret)
13175 return ret;
13176
5c1e3426
ML		 13177 if (recalc && (!i915.fastboot ||
13178 !intel_pipe_config_compare(state->dev,
cfb23ed6 13179 to_intel_crtc_state(crtc->state),
5c1e3426 13180 pipe_config, true))) {
cfb23ed6
ML		 13181 modeset = crtc_state->mode_changed = true;
13182
13183 ret = drm_atomic_add_affected_planes(state, crtc);
13184 if (ret)
13185 return ret;
13186 }
61333b60 13187
cfb23ed6 13188 any_ms = modeset;
c347a676 13189 intel_dump_pipe_config(to_intel_crtc(crtc),
cfb23ed6
ML		 13190 pipe_config,
13191 modeset ? "[modeset]" : "[fastboot]");
c347a676
ACO		 13192 }
13193
61333b60
ML		 13194 if (any_ms) {
13195 ret = intel_modeset_checks(state);
13196
13197 if (ret)
13198 return ret;
27c329ed
ML		 13199 } else
13200 to_intel_atomic_state(state)->cdclk =
13201 to_i915(state->dev)->cdclk_freq;
c347a676
ACO		 13202
13203 return drm_atomic_helper_check_planes(state->dev, state);
054518dd
ACO		 13204}
13205
c72d969b 13206static int __intel_set_mode(struct drm_atomic_state *state)
a6778b3c 13207{
c72d969b 13208 struct drm_device *dev = state->dev;
fbee40df 13209 struct drm_i915_private *dev_priv = dev->dev_private;
0a9ab303
ACO		 13210 struct drm_crtc *crtc;
13211 struct drm_crtc_state *crtc_state;
c0c36b94 13212 int ret = 0;
0a9ab303 13213 int i;
61333b60 13214 bool any_ms = false;
a6778b3c 13215
d4afb8cc
ACO		 13216 ret = drm_atomic_helper_prepare_planes(dev, state);
13217 if (ret)
13218 return ret;
13219
1c5e19f8
ML		 13220 drm_atomic_helper_swap_state(dev, state);
13221
0a9ab303 13222 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13224
61333b60
ML		 13225 if (!needs_modeset(crtc->state))
13226 continue;
13227
13228 any_ms = true;
a539205a 13229 intel_pre_plane_update(intel_crtc);
460da916 13230
a539205a
ML		 13231 if (crtc_state->active) {
13232 intel_crtc_disable_planes(crtc, crtc_state->plane_mask);
13233 dev_priv->display.crtc_disable(crtc);
eddfcbcd
ML		 13234 intel_crtc->active = false;
13235 intel_disable_shared_dpll(intel_crtc);
a539205a 13236 }
b8cecdf5 13237 }
7758a113 13238
ea9d758d
DV		 13239 /* Only after disabling all output pipelines that will be changed can we
13240 * update the the output configuration. */
0a9ab303 13241 intel_modeset_update_state(state);
f6e5b160 13242
a821fc46
ACO		 13243 /* The state has been swaped above, so state actually contains the
13244 * old state now. */
61333b60
ML		 13245 if (any_ms)
13246 modeset_update_crtc_power_domains(state);
47fab737 13247
a6778b3c 13248 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 13249 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a539205a
ML		 13250 if (needs_modeset(crtc->state) && crtc->state->active) {
13251 update_scanline_offset(to_intel_crtc(crtc));
13252 dev_priv->display.crtc_enable(crtc);
13253 }
80715b2f 13254
a539205a 13255 drm_atomic_helper_commit_planes_on_crtc(crtc_state);
80715b2f 13256 }
a6778b3c 13257
a6778b3c 13258 /* FIXME: add subpixel order */
83a57153 13259
d4afb8cc
ACO		 13260 drm_atomic_helper_cleanup_planes(dev, state);
13261
2bfb4627
ACO		 13262 drm_atomic_state_free(state);
13263
9eb45f22 13264 return 0;
f6e5b160
CW		 13265}
13266
568c634a 13267static int intel_set_mode_checked(struct drm_atomic_state *state)
f30da187 13268{
568c634a 13269 struct drm_device *dev = state->dev;
f30da187
DV		 13270 int ret;
13271
568c634a 13272 ret = __intel_set_mode(state);
f30da187 13273 if (ret == 0)
568c634a 13274 intel_modeset_check_state(dev);
f30da187
DV		 13275
13276 return ret;
13277}
13278
568c634a 13279static int intel_set_mode(struct drm_atomic_state *state)
7f27126e 13280{
568c634a 13281 int ret;
83a57153 13282
568c634a 13283 ret = intel_modeset_compute_config(state);
83a57153 13284 if (ret)
568c634a 13285 return ret;
7f27126e 13286
568c634a 13287 return intel_set_mode_checked(state);
7f27126e
JB		 13288}
13289
c0c36b94
CW		 13290void intel_crtc_restore_mode(struct drm_crtc *crtc)
13291{
83a57153
ACO		 13292 struct drm_device *dev = crtc->dev;
13293 struct drm_atomic_state *state;
13294 struct intel_encoder *encoder;
13295 struct intel_connector *connector;
13296 struct drm_connector_state *connector_state;
4be07317 13297 struct intel_crtc_state *crtc_state;
2bfb4627 13298 int ret;
83a57153
ACO		 13299
13300 state = drm_atomic_state_alloc(dev);
13301 if (!state) {
13302 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
13303 crtc->base.id);
13304 return;
13305 }
13306
13307 state->acquire_ctx = dev->mode_config.acquire_ctx;
13308
13309 /* The force restore path in the HW readout code relies on the staged
13310 * config still keeping the user requested config while the actual
13311 * state has been overwritten by the configuration read from HW. We
13312 * need to copy the staged config to the atomic state, otherwise the
13313 * mode set will just reapply the state the HW is already in. */
13314 for_each_intel_encoder(dev, encoder) {
13315 if (&encoder->new_crtc->base != crtc)
13316 continue;
13317
13318 for_each_intel_connector(dev, connector) {
13319 if (connector->new_encoder != encoder)
13320 continue;
13321
13322 connector_state = drm_atomic_get_connector_state(state, &connector->base);
13323 if (IS_ERR(connector_state)) {
13324 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
13325 connector->base.base.id,
13326 connector->base.name,
13327 PTR_ERR(connector_state));
13328 continue;
13329 }
13330
13331 connector_state->crtc = crtc;
13332 connector_state->best_encoder = &encoder->base;
13333 }
13334 }
13335
4ed9fb37
ACO		 13336 crtc_state = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
13337 if (IS_ERR(crtc_state)) {
13338 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
13339 crtc->base.id, PTR_ERR(crtc_state));
13340 drm_atomic_state_free(state);
13341 return;
13342 }
4be07317 13343
4ed9fb37
ACO		 13344 crtc_state->base.active = crtc_state->base.enable =
13345 to_intel_crtc(crtc)->new_enabled;
8c7b5ccb 13346
4ed9fb37 13347 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
4be07317 13348
d3a40d1b
ACO		 13349 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
13350 crtc->primary->fb, crtc->x, crtc->y);
13351
568c634a 13352 ret = intel_set_mode(state);
2bfb4627
ACO		 13353 if (ret)
13354 drm_atomic_state_free(state);
c0c36b94
CW		 13355}
13356
25c5b266
DV		 13357#undef for_each_intel_crtc_masked
13358
b7885264
ACO		 13359static bool intel_connector_in_mode_set(struct intel_connector *connector,
13360 struct drm_mode_set *set)
13361{
13362 int ro;
13363
13364 for (ro = 0; ro < set->num_connectors; ro++)
13365 if (set->connectors[ro] == &connector->base)
13366 return true;
13367
13368 return false;
13369}
13370
2e431051 13371static int
9a935856
DV		 13372intel_modeset_stage_output_state(struct drm_device *dev,
13373 struct drm_mode_set *set,
944b0c76 13374 struct drm_atomic_state *state)
50f56119 13375{
9a935856 13376 struct intel_connector *connector;
d5432a9d 13377 struct drm_connector *drm_connector;
944b0c76 13378 struct drm_connector_state *connector_state;
d5432a9d
ACO		 13379 struct drm_crtc *crtc;
13380 struct drm_crtc_state *crtc_state;
13381 int i, ret;
50f56119 13382
9abdda74 13383 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 13384 * of connectors. For paranoia, double-check this. */
13385 WARN_ON(!set->fb && (set->num_connectors != 0));
13386 WARN_ON(set->fb && (set->num_connectors == 0));
13387
3a3371ff 13388 for_each_intel_connector(dev, connector) {
b7885264
ACO		 13389 bool in_mode_set = intel_connector_in_mode_set(connector, set);
13390
d5432a9d
ACO		 13391 if (!in_mode_set && connector->base.state->crtc != set->crtc)
13392 continue;
13393
13394 connector_state =
13395 drm_atomic_get_connector_state(state, &connector->base);
13396 if (IS_ERR(connector_state))
13397 return PTR_ERR(connector_state);
13398
b7885264
ACO		 13399 if (in_mode_set) {
13400 int pipe = to_intel_crtc(set->crtc)->pipe;
d5432a9d
ACO		 13401 connector_state->best_encoder =
13402 &intel_find_encoder(connector, pipe)->base;
50f56119
DV		 13403 }
13404
d5432a9d 13405 if (connector->base.state->crtc != set->crtc)
b7885264
ACO		 13406 continue;
13407
9a935856
DV		 13408 /* If we disable the crtc, disable all its connectors. Also, if
13409 * the connector is on the changing crtc but not on the new
13410 * connector list, disable it. */
b7885264 13411 if (!set->fb || !in_mode_set) {
d5432a9d 13412 connector_state->best_encoder = NULL;
9a935856
DV		 13413
13414 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
13415 connector->base.base.id,
c23cc417 13416 connector->base.name);
9a935856 13417 }
50f56119 13418 }
9a935856 13419 /* connector->new_encoder is now updated for all connectors. */
50f56119 13420
d5432a9d
ACO		 13421 for_each_connector_in_state(state, drm_connector, connector_state, i) {
13422 connector = to_intel_connector(drm_connector);
13423
13424 if (!connector_state->best_encoder) {
13425 ret = drm_atomic_set_crtc_for_connector(connector_state,
13426 NULL);
13427 if (ret)
13428 return ret;
7668851f 13429
50f56119 13430 continue;
d5432a9d 13431 }
50f56119 13432
d5432a9d
ACO		 13433 if (intel_connector_in_mode_set(connector, set)) {
13434 struct drm_crtc *crtc = connector->base.state->crtc;
13435
13436 /* If this connector was in a previous crtc, add it
13437 * to the state. We might need to disable it. */
13438 if (crtc) {
13439 crtc_state =
13440 drm_atomic_get_crtc_state(state, crtc);
13441 if (IS_ERR(crtc_state))
13442 return PTR_ERR(crtc_state);
13443 }
13444
13445 ret = drm_atomic_set_crtc_for_connector(connector_state,
13446 set->crtc);
13447 if (ret)
13448 return ret;
13449 }
50f56119
DV		 13450
13451 /* Make sure the new CRTC will work with the encoder */
d5432a9d
ACO		 13452 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
13453 connector_state->crtc)) {
5e2b584e 13454 return -EINVAL;
50f56119 13455 }
944b0c76 13456
9a935856
DV		 13457 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
13458 connector->base.base.id,
c23cc417 13459 connector->base.name,
d5432a9d 13460 connector_state->crtc->base.id);
944b0c76 13461
d5432a9d
ACO		 13462 if (connector_state->best_encoder != &connector->encoder->base)
13463 connector->encoder =
13464 to_intel_encoder(connector_state->best_encoder);
0e32b39c 13465 }
7668851f 13466
d5432a9d 13467 for_each_crtc_in_state(state, crtc, crtc_state, i) {
49d6fa21
ML		 13468 bool has_connectors;
13469
d5432a9d
ACO		 13470 ret = drm_atomic_add_affected_connectors(state, crtc);
13471 if (ret)
13472 return ret;
4be07317 13473
49d6fa21
ML		 13474 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
13475 if (has_connectors != crtc_state->enable)
13476 crtc_state->enable =
13477 crtc_state->active = has_connectors;
7668851f
VS		 13478 }
13479
8c7b5ccb
ACO		 13480 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
13481 set->fb, set->x, set->y);
13482 if (ret)
13483 return ret;
13484
13485 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
13486 if (IS_ERR(crtc_state))
13487 return PTR_ERR(crtc_state);
13488
ce52299c
MR		 13489 ret = drm_atomic_set_mode_for_crtc(crtc_state, set->mode);
13490 if (ret)
13491 return ret;
8c7b5ccb
ACO		 13492
13493 if (set->num_connectors)
13494 crtc_state->active = true;
13495
2e431051
DV		 13496 return 0;
13497}
13498
13499static int intel_crtc_set_config(struct drm_mode_set *set)
13500{
13501 struct drm_device *dev;
83a57153 13502 struct drm_atomic_state *state = NULL;
2e431051 13503 int ret;
2e431051 13504
8d3e375e
DV		 13505 BUG_ON(!set);
13506 BUG_ON(!set->crtc);
13507 BUG_ON(!set->crtc->helper_private);
2e431051 13508
7e53f3a4
DV		 13509 /* Enforce sane interface api - has been abused by the fb helper. */
13510 BUG_ON(!set->mode && set->fb);
13511 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 13512
2e431051
DV		 13513 if (set->fb) {
13514 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
13515 set->crtc->base.id, set->fb->base.id,
13516 (int)set->num_connectors, set->x, set->y);
13517 } else {
13518 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 13519 }
13520
13521 dev = set->crtc->dev;
13522
83a57153 13523 state = drm_atomic_state_alloc(dev);
7cbf41d6
ACO		 13524 if (!state)
13525 return -ENOMEM;
83a57153
ACO		 13526
13527 state->acquire_ctx = dev->mode_config.acquire_ctx;
13528
462a425a 13529 ret = intel_modeset_stage_output_state(dev, set, state);
2e431051 13530 if (ret)
7cbf41d6 13531 goto out;
2e431051 13532
568c634a
ACO		 13533 ret = intel_modeset_compute_config(state);
13534 if (ret)
7cbf41d6 13535 goto out;
50f52756 13536
1f9954d0
JB		 13537 intel_update_pipe_size(to_intel_crtc(set->crtc));
13538
568c634a 13539 ret = intel_set_mode_checked(state);
2d05eae1 13540 if (ret) {
bf67dfeb
DV		 13541 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
13542 set->crtc->base.id, ret);
2d05eae1 13543 }
50f56119 13544
7cbf41d6 13545out:
2bfb4627
ACO		 13546 if (ret)
13547 drm_atomic_state_free(state);
50f56119
DV		 13548 return ret;
13549}
f6e5b160
CW		 13550
13551static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 13552 .gamma_set = intel_crtc_gamma_set,
50f56119 13553 .set_config = intel_crtc_set_config,
f6e5b160
CW		 13554 .destroy = intel_crtc_destroy,
13555 .page_flip = intel_crtc_page_flip,
1356837e
MR		 13556 .atomic_duplicate_state = intel_crtc_duplicate_state,
13557 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13558};
13559
5358901f
DV		 13560static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13561 struct intel_shared_dpll *pll,
13562 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13563{
5358901f 13564 uint32_t val;
ee7b9f93 13565
f458ebbc 13566 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13567 return false;
13568
5358901f 13569 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13570 hw_state->dpll = val;
13571 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13572 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13573
13574 return val & DPLL_VCO_ENABLE;
13575}
13576
15bdd4cf
DV		 13577static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13578 struct intel_shared_dpll *pll)
13579{
3e369b76
ACO		 13580 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13581 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13582}
13583
e7b903d2
DV		 13584static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13585 struct intel_shared_dpll *pll)
13586{
e7b903d2 13587 /* PCH refclock must be enabled first */
89eff4be 13588 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13589
3e369b76 13590 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13591
13592 /* Wait for the clocks to stabilize. */
13593 POSTING_READ(PCH_DPLL(pll->id));
13594 udelay(150);
13595
13596 /* The pixel multiplier can only be updated once the
13597 * DPLL is enabled and the clocks are stable.
13598 *
13599 * So write it again.
13600 */
3e369b76 13601 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13602 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13603 udelay(200);
13604}
13605
13606static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13607 struct intel_shared_dpll *pll)
13608{
13609 struct drm_device *dev = dev_priv->dev;
13610 struct intel_crtc *crtc;
e7b903d2
DV		 13611
13612 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13613 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13614 if (intel_crtc_to_shared_dpll(crtc) == pll)
13615 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13616 }
13617
15bdd4cf
DV		 13618 I915_WRITE(PCH_DPLL(pll->id), 0);
13619 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13620 udelay(200);
13621}
13622
46edb027
DV		 13623static char *ibx_pch_dpll_names[] = {
13624 "PCH DPLL A",
13625 "PCH DPLL B",
13626};
13627
7c74ade1 13628static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13629{
e7b903d2 13630 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13631 int i;
13632
7c74ade1 13633 dev_priv->num_shared_dpll = 2;
ee7b9f93 13634
e72f9fbf 13635 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13636 dev_priv->shared_dplls[i].id = i;
13637 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13638 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13639 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13640 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13641 dev_priv->shared_dplls[i].get_hw_state =
13642 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13643 }
13644}
13645
7c74ade1
DV		 13646static void intel_shared_dpll_init(struct drm_device *dev)
13647{
e7b903d2 13648 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13649
b6283055
VS		 13650 intel_update_cdclk(dev);
13651
9cd86933
DV		 13652 if (HAS_DDI(dev))
13653 intel_ddi_pll_init(dev);
13654 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13655 ibx_pch_dpll_init(dev);
13656 else
13657 dev_priv->num_shared_dpll = 0;
13658
13659 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13660}
13661
6beb8c23
MR		 13662/**
13663 * intel_prepare_plane_fb - Prepare fb for usage on plane
13664 * @plane: drm plane to prepare for
13665 * @fb: framebuffer to prepare for presentation
13666 *
13667 * Prepares a framebuffer for usage on a display plane. Generally this
13668 * involves pinning the underlying object and updating the frontbuffer tracking
13669 * bits. Some older platforms need special physical address handling for
13670 * cursor planes.
13671 *
13672 * Returns 0 on success, negative error code on failure.
13673 */
13674int
13675intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13676 struct drm_framebuffer *fb,
13677 const struct drm_plane_state *new_state)
465c120c
MR		 13678{
13679 struct drm_device *dev = plane->dev;
6beb8c23 13680 struct intel_plane *intel_plane = to_intel_plane(plane);
6beb8c23
MR		 13681 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13682 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
6beb8c23 13683 int ret = 0;
465c120c 13684
ea2c67bb 13685 if (!obj)
465c120c
MR		 13686 return 0;
13687
6beb8c23 13688 mutex_lock(&dev->struct_mutex);
465c120c 13689
6beb8c23
MR		 13690 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13691 INTEL_INFO(dev)->cursor_needs_physical) {
13692 int align = IS_I830(dev) ? 16 * 1024 : 256;
13693 ret = i915_gem_object_attach_phys(obj, align);
13694 if (ret)
13695 DRM_DEBUG_KMS("failed to attach phys object\n");
13696 } else {
91af127f 13697 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL, NULL);
6beb8c23 13698 }
465c120c 13699
6beb8c23 13700 if (ret == 0)
a9ff8714 13701 i915_gem_track_fb(old_obj, obj, intel_plane->frontbuffer_bit);
fdd508a6 13702
4c34574f 13703 mutex_unlock(&dev->struct_mutex);
465c120c 13704
6beb8c23
MR		 13705 return ret;
13706}
13707
38f3ce3a
MR		 13708/**
13709 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13710 * @plane: drm plane to clean up for
13711 * @fb: old framebuffer that was on plane
13712 *
13713 * Cleans up a framebuffer that has just been removed from a plane.
13714 */
13715void
13716intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13717 struct drm_framebuffer *fb,
13718 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13719{
13720 struct drm_device *dev = plane->dev;
13721 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13722
13723 if (WARN_ON(!obj))
13724 return;
13725
13726 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13727 !INTEL_INFO(dev)->cursor_needs_physical) {
13728 mutex_lock(&dev->struct_mutex);
82bc3b2d 13729 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13730 mutex_unlock(&dev->struct_mutex);
13731 }
465c120c
MR		 13732}
13733
6156a456
CK		 13734int
13735skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13736{
13737 int max_scale;
13738 struct drm_device *dev;
13739 struct drm_i915_private *dev_priv;
13740 int crtc_clock, cdclk;
13741
13742 if (!intel_crtc || !crtc_state)
13743 return DRM_PLANE_HELPER_NO_SCALING;
13744
13745 dev = intel_crtc->base.dev;
13746 dev_priv = dev->dev_private;
13747 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
27c329ed 13748 cdclk = to_intel_atomic_state(crtc_state->base.state)->cdclk;
6156a456
CK		 13749
13750 if (!crtc_clock || !cdclk)
13751 return DRM_PLANE_HELPER_NO_SCALING;
13752
13753 /*
13754 * skl max scale is lower of:
13755 * close to 3 but not 3, -1 is for that purpose
13756 * or
13757 * cdclk/crtc_clock
13758 */
13759 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13760
13761 return max_scale;
13762}
13763
465c120c 13764static int
3c692a41 13765intel_check_primary_plane(struct drm_plane *plane,
061e4b8d 13766 struct intel_crtc_state *crtc_state,
3c692a41
GP		 13767 struct intel_plane_state *state)
13768{
2b875c22
MR		 13769 struct drm_crtc *crtc = state->base.crtc;
13770 struct drm_framebuffer *fb = state->base.fb;
6156a456 13771 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
061e4b8d
ML		 13772 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13773 bool can_position = false;
465c120c 13774
061e4b8d
ML		 13775 /* use scaler when colorkey is not required */
13776 if (INTEL_INFO(plane->dev)->gen >= 9 &&
818ed961 13777 state->ckey.flags == I915_SET_COLORKEY_NONE) {
061e4b8d
ML		 13778 min_scale = 1;
13779 max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
d8106366 13780 can_position = true;
6156a456 13781 }
d8106366 13782
061e4b8d
ML		 13783 return drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13784 &state->dst, &state->clip,
da20eabd
ML		 13785 min_scale, max_scale,
13786 can_position, true,
13787 &state->visible);
14af293f
GP		 13788}
13789
13790static void
13791intel_commit_primary_plane(struct drm_plane *plane,
13792 struct intel_plane_state *state)
13793{
2b875c22
MR		 13794 struct drm_crtc *crtc = state->base.crtc;
13795 struct drm_framebuffer *fb = state->base.fb;
13796 struct drm_device *dev = plane->dev;
14af293f 13797 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13798 struct intel_crtc *intel_crtc;
14af293f
GP		 13799 struct drm_rect *src = &state->src;
13800
ea2c67bb
MR		 13801 crtc = crtc ? crtc : plane->crtc;
13802 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13803
13804 plane->fb = fb;
9dc806fc
MR		 13805 crtc->x = src->x1 >> 16;
13806 crtc->y = src->y1 >> 16;
ccc759dc 13807
a539205a 13808 if (!crtc->state->active)
302d19ac 13809 return;
465c120c 13810
302d19ac
ML		 13811 if (state->visible)
13812 /* FIXME: kill this fastboot hack */
13813 intel_update_pipe_size(intel_crtc);
13814
13815 dev_priv->display.update_primary_plane(crtc, fb, crtc->x, crtc->y);
465c120c
MR		 13816}
13817
a8ad0d8e
ML		 13818static void
13819intel_disable_primary_plane(struct drm_plane *plane,
7fabf5ef 13820 struct drm_crtc *crtc)
a8ad0d8e
ML		 13821{
13822 struct drm_device *dev = plane->dev;
13823 struct drm_i915_private *dev_priv = dev->dev_private;
13824
a8ad0d8e
ML		 13825 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13826}
13827
32b7eeec 13828static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13829{
32b7eeec 13830 struct drm_device *dev = crtc->dev;
140fd38d 13831 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3c692a41 13833
a539205a
ML		 13834 if (!needs_modeset(crtc->state))
13835 intel_pre_plane_update(intel_crtc);
3c692a41 13836
f015c551 13837 if (intel_crtc->atomic.update_wm_pre)
32b7eeec 13838 intel_update_watermarks(crtc);
3c692a41 13839
32b7eeec 13840 intel_runtime_pm_get(dev_priv);
3c692a41 13841
c34c9ee4 13842 /* Perform vblank evasion around commit operation */
a539205a 13843 if (crtc->state->active)
c34c9ee4
MR		 13844 intel_crtc->atomic.evade =
13845 intel_pipe_update_start(intel_crtc,
13846 &intel_crtc->atomic.start_vbl_count);
0583236e
ML		 13847
13848 if (!needs_modeset(crtc->state) && INTEL_INFO(dev)->gen >= 9)
13849 skl_detach_scalers(intel_crtc);
32b7eeec
MR		 13850}
13851
13852static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13853{
13854 struct drm_device *dev = crtc->dev;
13855 struct drm_i915_private *dev_priv = dev->dev_private;
13856 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
32b7eeec 13857
c34c9ee4
MR		 13858 if (intel_crtc->atomic.evade)
13859 intel_pipe_update_end(intel_crtc,
13860 intel_crtc->atomic.start_vbl_count);
3c692a41 13861
140fd38d 13862 intel_runtime_pm_put(dev_priv);
3c692a41 13863
ac21b225 13864 intel_post_plane_update(intel_crtc);
3c692a41
GP		 13865}
13866
cf4c7c12 13867/**
4a3b8769
MR		 13868 * intel_plane_destroy - destroy a plane
13869 * @plane: plane to destroy
cf4c7c12 13870 *
4a3b8769
MR		 13871 * Common destruction function for all types of planes (primary, cursor,
13872 * sprite).
cf4c7c12 13873 */
4a3b8769 13874void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13875{
13876 struct intel_plane *intel_plane = to_intel_plane(plane);
13877 drm_plane_cleanup(plane);
13878 kfree(intel_plane);
13879}
13880
65a3fea0 13881const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13882 .update_plane = drm_atomic_helper_update_plane,
13883 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13884 .destroy = intel_plane_destroy,
c196e1d6 13885 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13886 .atomic_get_property = intel_plane_atomic_get_property,
13887 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13888 .atomic_duplicate_state = intel_plane_duplicate_state,
13889 .atomic_destroy_state = intel_plane_destroy_state,
13890
465c120c
MR		 13891};
13892
13893static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13894 int pipe)
13895{
13896 struct intel_plane *primary;
8e7d688b 13897 struct intel_plane_state *state;
465c120c
MR		 13898 const uint32_t *intel_primary_formats;
13899 int num_formats;
13900
13901 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13902 if (primary == NULL)
13903 return NULL;
13904
8e7d688b
MR		 13905 state = intel_create_plane_state(&primary->base);
13906 if (!state) {
ea2c67bb
MR		 13907 kfree(primary);
13908 return NULL;
13909 }
8e7d688b 13910 primary->base.state = &state->base;
ea2c67bb 13911
465c120c
MR		 13912 primary->can_scale = false;
13913 primary->max_downscale = 1;
6156a456
CK		 13914 if (INTEL_INFO(dev)->gen >= 9) {
13915 primary->can_scale = true;
af99ceda 13916 state->scaler_id = -1;
6156a456 13917 }
465c120c
MR		 13918 primary->pipe = pipe;
13919 primary->plane = pipe;
a9ff8714 13920 primary->frontbuffer_bit = INTEL_FRONTBUFFER_PRIMARY(pipe);
c59cb179
MR		 13921 primary->check_plane = intel_check_primary_plane;
13922 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13923 primary->disable_plane = intel_disable_primary_plane;
465c120c
MR		 13924 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13925 primary->plane = !pipe;
13926
6c0fd451
DL		 13927 if (INTEL_INFO(dev)->gen >= 9) {
13928 intel_primary_formats = skl_primary_formats;
13929 num_formats = ARRAY_SIZE(skl_primary_formats);
13930 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13931 intel_primary_formats = i965_primary_formats;
13932 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13933 } else {
13934 intel_primary_formats = i8xx_primary_formats;
13935 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13936 }
13937
13938 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13939 &intel_plane_funcs,
465c120c
MR		 13940 intel_primary_formats, num_formats,
13941 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13942
3b7a5119
SJ		 13943 if (INTEL_INFO(dev)->gen >= 4)
13944 intel_create_rotation_property(dev, primary);
48404c1e 13945
ea2c67bb
MR		 13946 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13947
465c120c
MR		 13948 return &primary->base;
13949}
13950
3b7a5119
SJ		 13951void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13952{
13953 if (!dev->mode_config.rotation_property) {
13954 unsigned long flags = BIT(DRM_ROTATE_0) |
13955 BIT(DRM_ROTATE_180);
13956
13957 if (INTEL_INFO(dev)->gen >= 9)
13958 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13959
13960 dev->mode_config.rotation_property =
13961 drm_mode_create_rotation_property(dev, flags);
13962 }
13963 if (dev->mode_config.rotation_property)
13964 drm_object_attach_property(&plane->base.base,
13965 dev->mode_config.rotation_property,
13966 plane->base.state->rotation);
13967}
13968
3d7d6510 13969static int
852e787c 13970intel_check_cursor_plane(struct drm_plane *plane,
061e4b8d 13971 struct intel_crtc_state *crtc_state,
852e787c 13972 struct intel_plane_state *state)
3d7d6510 13973{
061e4b8d 13974 struct drm_crtc *crtc = crtc_state->base.crtc;
2b875c22 13975 struct drm_framebuffer *fb = state->base.fb;
757f9a3e 13976 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
757f9a3e
GP		 13977 unsigned stride;
13978 int ret;
3d7d6510 13979
061e4b8d
ML		 13980 ret = drm_plane_helper_check_update(plane, crtc, fb, &state->src,
13981 &state->dst, &state->clip,
3d7d6510
MR		 13982 DRM_PLANE_HELPER_NO_SCALING,
13983 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13984 true, true, &state->visible);
757f9a3e
GP		 13985 if (ret)
13986 return ret;
13987
757f9a3e
GP		 13988 /* if we want to turn off the cursor ignore width and height */
13989 if (!obj)
da20eabd 13990 return 0;
757f9a3e 13991
757f9a3e 13992 /* Check for which cursor types we support */
061e4b8d 13993 if (!cursor_size_ok(plane->dev, state->base.crtc_w, state->base.crtc_h)) {
ea2c67bb
MR		 13994 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13995 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13996 return -EINVAL;
13997 }
13998
ea2c67bb
MR		 13999 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
14000 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 14001 DRM_DEBUG_KMS("buffer is too small\n");
14002 return -ENOMEM;
14003 }
14004
3a656b54 14005 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e 14006 DRM_DEBUG_KMS("cursor cannot be tiled\n");
da20eabd 14007 return -EINVAL;
32b7eeec
MR		 14008 }
14009
da20eabd 14010 return 0;
852e787c 14011}
3d7d6510 14012
a8ad0d8e
ML		 14013static void
14014intel_disable_cursor_plane(struct drm_plane *plane,
7fabf5ef 14015 struct drm_crtc *crtc)
a8ad0d8e 14016{
a8ad0d8e
ML		 14017 intel_crtc_update_cursor(crtc, false);
14018}
14019
f4a2cf29 14020static void
852e787c
GP		 14021intel_commit_cursor_plane(struct drm_plane *plane,
14022 struct intel_plane_state *state)
14023{
2b875c22 14024 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 14025 struct drm_device *dev = plane->dev;
14026 struct intel_crtc *intel_crtc;
2b875c22 14027 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 14028 uint32_t addr;
852e787c 14029
ea2c67bb
MR		 14030 crtc = crtc ? crtc : plane->crtc;
14031 intel_crtc = to_intel_crtc(crtc);
14032
2b875c22 14033 plane->fb = state->base.fb;
ea2c67bb
MR		 14034 crtc->cursor_x = state->base.crtc_x;
14035 crtc->cursor_y = state->base.crtc_y;
14036
a912f12f
GP		 14037 if (intel_crtc->cursor_bo == obj)
14038 goto update;
4ed91096 14039
f4a2cf29 14040 if (!obj)
a912f12f 14041 addr = 0;
f4a2cf29 14042 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 14043 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 14044 else
a912f12f 14045 addr = obj->phys_handle->busaddr;
852e787c 14046
a912f12f
GP		 14047 intel_crtc->cursor_addr = addr;
14048 intel_crtc->cursor_bo = obj;
852e787c 14049
302d19ac 14050update:
a539205a 14051 if (crtc->state->active)
a912f12f 14052 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 14053}
14054
3d7d6510
MR		 14055static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
14056 int pipe)
14057{
14058 struct intel_plane *cursor;
8e7d688b 14059 struct intel_plane_state *state;
3d7d6510
MR		 14060
14061 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
14062 if (cursor == NULL)
14063 return NULL;
14064
8e7d688b
MR		 14065 state = intel_create_plane_state(&cursor->base);
14066 if (!state) {
ea2c67bb
MR		 14067 kfree(cursor);
14068 return NULL;
14069 }
8e7d688b 14070 cursor->base.state = &state->base;
ea2c67bb 14071
3d7d6510
MR		 14072 cursor->can_scale = false;
14073 cursor->max_downscale = 1;
14074 cursor->pipe = pipe;
14075 cursor->plane = pipe;
a9ff8714 14076 cursor->frontbuffer_bit = INTEL_FRONTBUFFER_CURSOR(pipe);
c59cb179
MR		 14077 cursor->check_plane = intel_check_cursor_plane;
14078 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 14079 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 14080
14081 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 14082 &intel_plane_funcs,
3d7d6510
MR		 14083 intel_cursor_formats,
14084 ARRAY_SIZE(intel_cursor_formats),
14085 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 14086
14087 if (INTEL_INFO(dev)->gen >= 4) {
14088 if (!dev->mode_config.rotation_property)
14089 dev->mode_config.rotation_property =
14090 drm_mode_create_rotation_property(dev,
14091 BIT(DRM_ROTATE_0) |
14092 BIT(DRM_ROTATE_180));
14093 if (dev->mode_config.rotation_property)
14094 drm_object_attach_property(&cursor->base.base,
14095 dev->mode_config.rotation_property,
8e7d688b 14096 state->base.rotation);
4398ad45
VS		 14097 }
14098
af99ceda
CK		 14099 if (INTEL_INFO(dev)->gen >=9)
14100 state->scaler_id = -1;
14101
ea2c67bb
MR		 14102 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
14103
3d7d6510
MR		 14104 return &cursor->base;
14105}
14106
549e2bfb
CK		 14107static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
14108 struct intel_crtc_state *crtc_state)
14109{
14110 int i;
14111 struct intel_scaler *intel_scaler;
14112 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
14113
14114 for (i = 0; i < intel_crtc->num_scalers; i++) {
14115 intel_scaler = &scaler_state->scalers[i];
14116 intel_scaler->in_use = 0;
549e2bfb
CK		 14117 intel_scaler->mode = PS_SCALER_MODE_DYN;
14118 }
14119
14120 scaler_state->scaler_id = -1;
14121}
14122
b358d0a6 14123static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 14124{
fbee40df 14125 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 14126 struct intel_crtc *intel_crtc;
f5de6e07 14127 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 14128 struct drm_plane *primary = NULL;
14129 struct drm_plane *cursor = NULL;
465c120c 14130 int i, ret;
79e53945 14131
955382f3 14132 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 14133 if (intel_crtc == NULL)
14134 return;
14135
f5de6e07
ACO		 14136 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
14137 if (!crtc_state)
14138 goto fail;
550acefd
ACO		 14139 intel_crtc->config = crtc_state;
14140 intel_crtc->base.state = &crtc_state->base;
07878248 14141 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 14142
549e2bfb
CK		 14143 /* initialize shared scalers */
14144 if (INTEL_INFO(dev)->gen >= 9) {
14145 if (pipe == PIPE_C)
14146 intel_crtc->num_scalers = 1;
14147 else
14148 intel_crtc->num_scalers = SKL_NUM_SCALERS;
14149
14150 skl_init_scalers(dev, intel_crtc, crtc_state);
14151 }
14152
465c120c 14153 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 14154 if (!primary)
14155 goto fail;
14156
14157 cursor = intel_cursor_plane_create(dev, pipe);
14158 if (!cursor)
14159 goto fail;
14160
465c120c 14161 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 14162 cursor, &intel_crtc_funcs);
14163 if (ret)
14164 goto fail;
79e53945
JB		 14165
14166 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 14167 for (i = 0; i < 256; i++) {
14168 intel_crtc->lut_r[i] = i;
14169 intel_crtc->lut_g[i] = i;
14170 intel_crtc->lut_b[i] = i;
14171 }
14172
1f1c2e24
VS		 14173 /*
14174 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 14175 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 14176 */
80824003
JB		 14177 intel_crtc->pipe = pipe;
14178 intel_crtc->plane = pipe;
3a77c4c4 14179 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 14180 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 14181 intel_crtc->plane = !pipe;
80824003
JB		 14182 }
14183
4b0e333e
CW		 14184 intel_crtc->cursor_base = ~0;
14185 intel_crtc->cursor_cntl = ~0;
dc41c154 14186 intel_crtc->cursor_size = ~0;
8d7849db 14187
852eb00d
VS		 14188 intel_crtc->wm.cxsr_allowed = true;
14189
22fd0fab
JB		 14190 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
14191 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
14192 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
14193 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
14194
79e53945 14195 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 14196
14197 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 14198 return;
14199
14200fail:
14201 if (primary)
14202 drm_plane_cleanup(primary);
14203 if (cursor)
14204 drm_plane_cleanup(cursor);
f5de6e07 14205 kfree(crtc_state);
3d7d6510 14206 kfree(intel_crtc);
79e53945
JB		 14207}
14208
752aa88a
JB		 14209enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
14210{
14211 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 14212 struct drm_device *dev = connector->base.dev;
752aa88a 14213
51fd371b 14214 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 14215
d3babd3f 14216 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 14217 return INVALID_PIPE;
14218
14219 return to_intel_crtc(encoder->crtc)->pipe;
14220}
14221
08d7b3d1 14222int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 14223 struct drm_file *file)
08d7b3d1 14224{
08d7b3d1 14225 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 14226 struct drm_crtc *drmmode_crtc;
c05422d5 14227 struct intel_crtc *crtc;
08d7b3d1 14228
7707e653 14229 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 14230
7707e653 14231 if (!drmmode_crtc) {
08d7b3d1 14232 DRM_ERROR("no such CRTC id\n");
3f2c2057 14233 return -ENOENT;
08d7b3d1
CW		 14234 }
14235
7707e653 14236 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 14237 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 14238
c05422d5 14239 return 0;
08d7b3d1
CW		 14240}
14241
66a9278e 14242static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 14243{
66a9278e
DV		 14244 struct drm_device *dev = encoder->base.dev;
14245 struct intel_encoder *source_encoder;
79e53945 14246 int index_mask = 0;
79e53945
JB		 14247 int entry = 0;
14248
b2784e15 14249 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 14250 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 14251 index_mask |= (1 << entry);
14252
79e53945
JB		 14253 entry++;
14254 }
4ef69c7a 14255
79e53945
JB		 14256 return index_mask;
14257}
14258
4d302442
CW		 14259static bool has_edp_a(struct drm_device *dev)
14260{
14261 struct drm_i915_private *dev_priv = dev->dev_private;
14262
14263 if (!IS_MOBILE(dev))
14264 return false;
14265
14266 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
14267 return false;
14268
e3589908 14269 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 14270 return false;
14271
14272 return true;
14273}
14274
84b4e042
JB		 14275static bool intel_crt_present(struct drm_device *dev)
14276{
14277 struct drm_i915_private *dev_priv = dev->dev_private;
14278
884497ed
DL		 14279 if (INTEL_INFO(dev)->gen >= 9)
14280 return false;
14281
cf404ce4 14282 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 14283 return false;
14284
14285 if (IS_CHERRYVIEW(dev))
14286 return false;
14287
14288 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
14289 return false;
14290
14291 return true;
14292}
14293
79e53945
JB		 14294static void intel_setup_outputs(struct drm_device *dev)
14295{
725e30ad 14296 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 14297 struct intel_encoder *encoder;
cb0953d7 14298 bool dpd_is_edp = false;
79e53945 14299
c9093354 14300 intel_lvds_init(dev);
79e53945 14301
84b4e042 14302 if (intel_crt_present(dev))
79935fca 14303 intel_crt_init(dev);
cb0953d7 14304
c776eb2e
VK		 14305 if (IS_BROXTON(dev)) {
14306 /*
14307 * FIXME: Broxton doesn't support port detection via the
14308 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
14309 * detect the ports.
14310 */
14311 intel_ddi_init(dev, PORT_A);
14312 intel_ddi_init(dev, PORT_B);
14313 intel_ddi_init(dev, PORT_C);
14314 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 14315 int found;
14316
de31facd
JB		 14317 /*
14318 * Haswell uses DDI functions to detect digital outputs.
14319 * On SKL pre-D0 the strap isn't connected, so we assume
14320 * it's there.
14321 */
0e72a5b5 14322 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 14323 /* WaIgnoreDDIAStrap: skl */
14324 if (found ||
14325 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 14326 intel_ddi_init(dev, PORT_A);
14327
14328 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
14329 * register */
14330 found = I915_READ(SFUSE_STRAP);
14331
14332 if (found & SFUSE_STRAP_DDIB_DETECTED)
14333 intel_ddi_init(dev, PORT_B);
14334 if (found & SFUSE_STRAP_DDIC_DETECTED)
14335 intel_ddi_init(dev, PORT_C);
14336 if (found & SFUSE_STRAP_DDID_DETECTED)
14337 intel_ddi_init(dev, PORT_D);
14338 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 14339 int found;
5d8a7752 14340 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 14341
14342 if (has_edp_a(dev))
14343 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 14344
dc0fa718 14345 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 14346 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 14347 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 14348 if (!found)
e2debe91 14349 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 14350 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 14351 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 14352 }
14353
dc0fa718 14354 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 14355 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 14356
dc0fa718 14357 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 14358 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 14359
5eb08b69 14360 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 14361 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 14362
270b3042 14363 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 14364 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 14365 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 14366 /*
14367 * The DP_DETECTED bit is the latched state of the DDC
14368 * SDA pin at boot. However since eDP doesn't require DDC
14369 * (no way to plug in a DP->HDMI dongle) the DDC pins for
14370 * eDP ports may have been muxed to an alternate function.
14371 * Thus we can't rely on the DP_DETECTED bit alone to detect
14372 * eDP ports. Consult the VBT as well as DP_DETECTED to
14373 * detect eDP ports.
14374 */
d2182a66
VS		 14375 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
14376 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 14377 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
14378 PORT_B);
e17ac6db
VS		 14379 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
14380 intel_dp_is_edp(dev, PORT_B))
14381 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 14382
d2182a66
VS		 14383 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14384 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 14385 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14386 PORT_C);
e17ac6db
VS		 14387 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14388 intel_dp_is_edp(dev, PORT_C))
14389 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14390
9418c1f1 14391 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14392 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14393 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14394 PORT_D);
e17ac6db
VS		 14395 /* eDP not supported on port D, so don't check VBT */
14396 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14397 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14398 }
14399
3cfca973 14400 intel_dsi_init(dev);
09da55dc 14401 } else if (!IS_GEN2(dev) && !IS_PINEVIEW(dev)) {
27185ae1 14402 bool found = false;
7d57382e 14403
e2debe91 14404 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14405 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14406 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
3fec3d2f 14407 if (!found && IS_G4X(dev)) {
b01f2c3a 14408 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14409 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14410 }
27185ae1 14411
3fec3d2f 14412 if (!found && IS_G4X(dev))
ab9d7c30 14413 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14414 }
13520b05
KH		 14415
14416 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14417
e2debe91 14418 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14419 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14420 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14421 }
27185ae1 14422
e2debe91 14423 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14424
3fec3d2f 14425 if (IS_G4X(dev)) {
b01f2c3a 14426 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14427 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14428 }
3fec3d2f 14429 if (IS_G4X(dev))
ab9d7c30 14430 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14431 }
27185ae1 14432
3fec3d2f 14433 if (IS_G4X(dev) &&
e7281eab 14434 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14435 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14436 } else if (IS_GEN2(dev))
79e53945
JB		 14437 intel_dvo_init(dev);
14438
103a196f 14439 if (SUPPORTS_TV(dev))
79e53945
JB		 14440 intel_tv_init(dev);
14441
0bc12bcb 14442 intel_psr_init(dev);
7c8f8a70 14443
b2784e15 14444 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14445 encoder->base.possible_crtcs = encoder->crtc_mask;
14446 encoder->base.possible_clones =
66a9278e 14447 intel_encoder_clones(encoder);
79e53945 14448 }
47356eb6 14449
dde86e2d 14450 intel_init_pch_refclk(dev);
270b3042
DV		 14451
14452 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14453}
14454
14455static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14456{
60a5ca01 14457 struct drm_device *dev = fb->dev;
79e53945 14458 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14459
ef2d633e 14460 drm_framebuffer_cleanup(fb);
60a5ca01 14461 mutex_lock(&dev->struct_mutex);
ef2d633e 14462 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14463 drm_gem_object_unreference(&intel_fb->obj->base);
14464 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14465 kfree(intel_fb);
14466}
14467
14468static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14469 struct drm_file *file,
79e53945
JB		 14470 unsigned int *handle)
14471{
14472 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14473 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14474
05394f39 14475 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14476}
14477
86c98588
RV		 14478static int intel_user_framebuffer_dirty(struct drm_framebuffer *fb,
14479 struct drm_file *file,
14480 unsigned flags, unsigned color,
14481 struct drm_clip_rect *clips,
14482 unsigned num_clips)
14483{
14484 struct drm_device *dev = fb->dev;
14485 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
14486 struct drm_i915_gem_object *obj = intel_fb->obj;
14487
14488 mutex_lock(&dev->struct_mutex);
14489 intel_fb_obj_flush(obj, false, ORIGIN_GTT);
14490 mutex_unlock(&dev->struct_mutex);
14491
14492 return 0;
14493}
14494
79e53945
JB		 14495static const struct drm_framebuffer_funcs intel_fb_funcs = {
14496 .destroy = intel_user_framebuffer_destroy,
14497 .create_handle = intel_user_framebuffer_create_handle,
86c98588 14498 .dirty = intel_user_framebuffer_dirty,
79e53945
JB		 14499};
14500
b321803d
DL		 14501static
14502u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14503 uint32_t pixel_format)
14504{
14505 u32 gen = INTEL_INFO(dev)->gen;
14506
14507 if (gen >= 9) {
14508 /* "The stride in bytes must not exceed the of the size of 8K
14509 * pixels and 32K bytes."
14510 */
14511 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14512 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14513 return 32*1024;
14514 } else if (gen >= 4) {
14515 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14516 return 16*1024;
14517 else
14518 return 32*1024;
14519 } else if (gen >= 3) {
14520 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14521 return 8*1024;
14522 else
14523 return 16*1024;
14524 } else {
14525 /* XXX DSPC is limited to 4k tiled */
14526 return 8*1024;
14527 }
14528}
14529
b5ea642a
DV		 14530static int intel_framebuffer_init(struct drm_device *dev,
14531 struct intel_framebuffer *intel_fb,
14532 struct drm_mode_fb_cmd2 *mode_cmd,
14533 struct drm_i915_gem_object *obj)
79e53945 14534{
6761dd31 14535 unsigned int aligned_height;
79e53945 14536 int ret;
b321803d 14537 u32 pitch_limit, stride_alignment;
79e53945 14538
dd4916c5
DV		 14539 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14540
2a80eada
DV		 14541 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14542 /* Enforce that fb modifier and tiling mode match, but only for
14543 * X-tiled. This is needed for FBC. */
14544 if (!!(obj->tiling_mode == I915_TILING_X) !=
14545 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14546 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14547 return -EINVAL;
14548 }
14549 } else {
14550 if (obj->tiling_mode == I915_TILING_X)
14551 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14552 else if (obj->tiling_mode == I915_TILING_Y) {
14553 DRM_DEBUG("No Y tiling for legacy addfb\n");
14554 return -EINVAL;
14555 }
14556 }
14557
9a8f0a12
TU		 14558 /* Passed in modifier sanity checking. */
14559 switch (mode_cmd->modifier[0]) {
14560 case I915_FORMAT_MOD_Y_TILED:
14561 case I915_FORMAT_MOD_Yf_TILED:
14562 if (INTEL_INFO(dev)->gen < 9) {
14563 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14564 mode_cmd->modifier[0]);
14565 return -EINVAL;
14566 }
14567 case DRM_FORMAT_MOD_NONE:
14568 case I915_FORMAT_MOD_X_TILED:
14569 break;
14570 default:
c0f40428
JB		 14571 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14572 mode_cmd->modifier[0]);
57cd6508 14573 return -EINVAL;
c16ed4be 14574 }
57cd6508 14575
b321803d
DL		 14576 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14577 mode_cmd->pixel_format);
14578 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14579 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14580 mode_cmd->pitches[0], stride_alignment);
57cd6508 14581 return -EINVAL;
c16ed4be 14582 }
57cd6508 14583
b321803d
DL		 14584 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14585 mode_cmd->pixel_format);
a35cdaa0 14586 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14587 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14588 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14589 "tiled" : "linear",
a35cdaa0 14590 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14591 return -EINVAL;
c16ed4be 14592 }
5d7bd705 14593
2a80eada 14594 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14595 mode_cmd->pitches[0] != obj->stride) {
14596 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14597 mode_cmd->pitches[0], obj->stride);
5d7bd705 14598 return -EINVAL;
c16ed4be 14599 }
5d7bd705 14600
57779d06 14601 /* Reject formats not supported by any plane early. */
308e5bcb 14602 switch (mode_cmd->pixel_format) {
57779d06 14603 case DRM_FORMAT_C8:
04b3924d
VS		 14604 case DRM_FORMAT_RGB565:
14605 case DRM_FORMAT_XRGB8888:
14606 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14607 break;
14608 case DRM_FORMAT_XRGB1555:
c16ed4be 14609 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14610 DRM_DEBUG("unsupported pixel format: %s\n",
14611 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14612 return -EINVAL;
c16ed4be 14613 }
57779d06 14614 break;
57779d06 14615 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14616 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14617 DRM_DEBUG("unsupported pixel format: %s\n",
14618 drm_get_format_name(mode_cmd->pixel_format));
14619 return -EINVAL;
14620 }
14621 break;
14622 case DRM_FORMAT_XBGR8888:
04b3924d 14623 case DRM_FORMAT_XRGB2101010:
57779d06 14624 case DRM_FORMAT_XBGR2101010:
c16ed4be 14625 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14626 DRM_DEBUG("unsupported pixel format: %s\n",
14627 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14628 return -EINVAL;
c16ed4be 14629 }
b5626747 14630 break;
7531208b
DL		 14631 case DRM_FORMAT_ABGR2101010:
14632 if (!IS_VALLEYVIEW(dev)) {
14633 DRM_DEBUG("unsupported pixel format: %s\n",
14634 drm_get_format_name(mode_cmd->pixel_format));
14635 return -EINVAL;
14636 }
14637 break;
04b3924d
VS		 14638 case DRM_FORMAT_YUYV:
14639 case DRM_FORMAT_UYVY:
14640 case DRM_FORMAT_YVYU:
14641 case DRM_FORMAT_VYUY:
c16ed4be 14642 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14643 DRM_DEBUG("unsupported pixel format: %s\n",
14644 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14645 return -EINVAL;
c16ed4be 14646 }
57cd6508
CW		 14647 break;
14648 default:
4ee62c76
VS		 14649 DRM_DEBUG("unsupported pixel format: %s\n",
14650 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14651 return -EINVAL;
14652 }
14653
90f9a336
VS		 14654 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14655 if (mode_cmd->offsets[0] != 0)
14656 return -EINVAL;
14657
ec2c981e 14658 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14659 mode_cmd->pixel_format,
14660 mode_cmd->modifier[0]);
53155c0a
DV		 14661 /* FIXME drm helper for size checks (especially planar formats)? */
14662 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14663 return -EINVAL;
14664
c7d73f6a
DV		 14665 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14666 intel_fb->obj = obj;
80075d49 14667 intel_fb->obj->framebuffer_references++;
c7d73f6a 14668
79e53945
JB		 14669 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14670 if (ret) {
14671 DRM_ERROR("framebuffer init failed %d\n", ret);
14672 return ret;
14673 }
14674
79e53945
JB		 14675 return 0;
14676}
14677
79e53945
JB		 14678static struct drm_framebuffer *
14679intel_user_framebuffer_create(struct drm_device *dev,
14680 struct drm_file *filp,
308e5bcb 14681 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14682{
05394f39 14683 struct drm_i915_gem_object *obj;
79e53945 14684
308e5bcb
JB		 14685 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14686 mode_cmd->handles[0]));
c8725226 14687 if (&obj->base == NULL)
cce13ff7 14688 return ERR_PTR(-ENOENT);
79e53945 14689
d2dff872 14690 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14691}
14692
4520f53a 14693#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14694static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14695{
14696}
14697#endif
14698
79e53945 14699static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14700 .fb_create = intel_user_framebuffer_create,
0632fef6 14701 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14702 .atomic_check = intel_atomic_check,
14703 .atomic_commit = intel_atomic_commit,
de419ab6
ML		 14704 .atomic_state_alloc = intel_atomic_state_alloc,
14705 .atomic_state_clear = intel_atomic_state_clear,
79e53945
JB		 14706};
14707
e70236a8
JB		 14708/* Set up chip specific display functions */
14709static void intel_init_display(struct drm_device *dev)
14710{
14711 struct drm_i915_private *dev_priv = dev->dev_private;
14712
ee9300bb
DV		 14713 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14714 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14715 else if (IS_CHERRYVIEW(dev))
14716 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14717 else if (IS_VALLEYVIEW(dev))
14718 dev_priv->display.find_dpll = vlv_find_best_dpll;
14719 else if (IS_PINEVIEW(dev))
14720 dev_priv->display.find_dpll = pnv_find_best_dpll;
14721 else
14722 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14723
bc8d7dff
DL		 14724 if (INTEL_INFO(dev)->gen >= 9) {
14725 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14726 dev_priv->display.get_initial_plane_config =
14727 skylake_get_initial_plane_config;
bc8d7dff
DL		 14728 dev_priv->display.crtc_compute_clock =
14729 haswell_crtc_compute_clock;
14730 dev_priv->display.crtc_enable = haswell_crtc_enable;
14731 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14732 dev_priv->display.update_primary_plane =
14733 skylake_update_primary_plane;
14734 } else if (HAS_DDI(dev)) {
0e8ffe1b 14735 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14736 dev_priv->display.get_initial_plane_config =
14737 ironlake_get_initial_plane_config;
797d0259
ACO		 14738 dev_priv->display.crtc_compute_clock =
14739 haswell_crtc_compute_clock;
4f771f10
PZ		 14740 dev_priv->display.crtc_enable = haswell_crtc_enable;
14741 dev_priv->display.crtc_disable = haswell_crtc_disable;
bc8d7dff
DL		 14742 dev_priv->display.update_primary_plane =
14743 ironlake_update_primary_plane;
09b4ddf9 14744 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14745 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14746 dev_priv->display.get_initial_plane_config =
14747 ironlake_get_initial_plane_config;
3fb37703
ACO		 14748 dev_priv->display.crtc_compute_clock =
14749 ironlake_crtc_compute_clock;
76e5a89c
DV		 14750 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14751 dev_priv->display.crtc_disable = ironlake_crtc_disable;
262ca2b0
MR		 14752 dev_priv->display.update_primary_plane =
14753 ironlake_update_primary_plane;
89b667f8
JB		 14754 } else if (IS_VALLEYVIEW(dev)) {
14755 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14756 dev_priv->display.get_initial_plane_config =
14757 i9xx_get_initial_plane_config;
d6dfee7a 14758 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14759 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14760 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14761 dev_priv->display.update_primary_plane =
14762 i9xx_update_primary_plane;
f564048e 14763 } else {
0e8ffe1b 14764 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14765 dev_priv->display.get_initial_plane_config =
14766 i9xx_get_initial_plane_config;
d6dfee7a 14767 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14768 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14769 dev_priv->display.crtc_disable = i9xx_crtc_disable;
262ca2b0
MR		 14770 dev_priv->display.update_primary_plane =
14771 i9xx_update_primary_plane;
f564048e 14772 }
e70236a8 14773
e70236a8 14774 /* Returns the core display clock speed */
1652d19e
VS		 14775 if (IS_SKYLAKE(dev))
14776 dev_priv->display.get_display_clock_speed =
14777 skylake_get_display_clock_speed;
acd3f3d3
BP		 14778 else if (IS_BROXTON(dev))
14779 dev_priv->display.get_display_clock_speed =
14780 broxton_get_display_clock_speed;
1652d19e
VS		 14781 else if (IS_BROADWELL(dev))
14782 dev_priv->display.get_display_clock_speed =
14783 broadwell_get_display_clock_speed;
14784 else if (IS_HASWELL(dev))
14785 dev_priv->display.get_display_clock_speed =
14786 haswell_get_display_clock_speed;
14787 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14788 dev_priv->display.get_display_clock_speed =
14789 valleyview_get_display_clock_speed;
b37a6434
VS		 14790 else if (IS_GEN5(dev))
14791 dev_priv->display.get_display_clock_speed =
14792 ilk_get_display_clock_speed;
a7c66cd8 14793 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
34edce2f 14794 IS_GEN6(dev) || IS_IVYBRIDGE(dev))
e70236a8
JB		 14795 dev_priv->display.get_display_clock_speed =
14796 i945_get_display_clock_speed;
34edce2f
VS		 14797 else if (IS_GM45(dev))
14798 dev_priv->display.get_display_clock_speed =
14799 gm45_get_display_clock_speed;
14800 else if (IS_CRESTLINE(dev))
14801 dev_priv->display.get_display_clock_speed =
14802 i965gm_get_display_clock_speed;
14803 else if (IS_PINEVIEW(dev))
14804 dev_priv->display.get_display_clock_speed =
14805 pnv_get_display_clock_speed;
14806 else if (IS_G33(dev) || IS_G4X(dev))
14807 dev_priv->display.get_display_clock_speed =
14808 g33_get_display_clock_speed;
e70236a8
JB		 14809 else if (IS_I915G(dev))
14810 dev_priv->display.get_display_clock_speed =
14811 i915_get_display_clock_speed;
257a7ffc 14812 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14813 dev_priv->display.get_display_clock_speed =
14814 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14815 else if (IS_PINEVIEW(dev))
14816 dev_priv->display.get_display_clock_speed =
14817 pnv_get_display_clock_speed;
e70236a8
JB		 14818 else if (IS_I915GM(dev))
14819 dev_priv->display.get_display_clock_speed =
14820 i915gm_get_display_clock_speed;
14821 else if (IS_I865G(dev))
14822 dev_priv->display.get_display_clock_speed =
14823 i865_get_display_clock_speed;
f0f8a9ce 14824 else if (IS_I85X(dev))
e70236a8 14825 dev_priv->display.get_display_clock_speed =
1b1d2716 14826 i85x_get_display_clock_speed;
623e01e5
VS		 14827 else { /* 830 */
14828 WARN(!IS_I830(dev), "Unknown platform. Assuming 133 MHz CDCLK\n");
e70236a8
JB		 14829 dev_priv->display.get_display_clock_speed =
14830 i830_get_display_clock_speed;
623e01e5 14831 }
e70236a8 14832
7c10a2b5 14833 if (IS_GEN5(dev)) {
3bb11b53 14834 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14835 } else if (IS_GEN6(dev)) {
14836 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14837 } else if (IS_IVYBRIDGE(dev)) {
14838 /* FIXME: detect B0+ stepping and use auto training */
14839 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14840 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14841 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
27c329ed
ML		 14842 if (IS_BROADWELL(dev)) {
14843 dev_priv->display.modeset_commit_cdclk =
14844 broadwell_modeset_commit_cdclk;
14845 dev_priv->display.modeset_calc_cdclk =
14846 broadwell_modeset_calc_cdclk;
14847 }
30a970c6 14848 } else if (IS_VALLEYVIEW(dev)) {
27c329ed
ML		 14849 dev_priv->display.modeset_commit_cdclk =
14850 valleyview_modeset_commit_cdclk;
14851 dev_priv->display.modeset_calc_cdclk =
14852 valleyview_modeset_calc_cdclk;
f8437dd1 14853 } else if (IS_BROXTON(dev)) {
27c329ed
ML		 14854 dev_priv->display.modeset_commit_cdclk =
14855 broxton_modeset_commit_cdclk;
14856 dev_priv->display.modeset_calc_cdclk =
14857 broxton_modeset_calc_cdclk;
e70236a8 14858 }
8c9f3aaf 14859
8c9f3aaf
JB		 14860 switch (INTEL_INFO(dev)->gen) {
14861 case 2:
14862 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14863 break;
14864
14865 case 3:
14866 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14867 break;
14868
14869 case 4:
14870 case 5:
14871 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14872 break;
14873
14874 case 6:
14875 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14876 break;
7c9017e5 14877 case 7:
4e0bbc31 14878 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14879 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14880 break;
830c81db 14881 case 9:
ba343e02
TU		 14882 /* Drop through - unsupported since execlist only. */
14883 default:
14884 /* Default just returns -ENODEV to indicate unsupported */
14885 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14886 }
7bd688cd
JN		 14887
14888 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14889
14890 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14891}
14892
b690e96c
JB		 14893/*
14894 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14895 * resume, or other times. This quirk makes sure that's the case for
14896 * affected systems.
14897 */
0206e353 14898static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14899{
14900 struct drm_i915_private *dev_priv = dev->dev_private;
14901
14902 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14903 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14904}
14905
b6b5d049
VS		 14906static void quirk_pipeb_force(struct drm_device *dev)
14907{
14908 struct drm_i915_private *dev_priv = dev->dev_private;
14909
14910 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14911 DRM_INFO("applying pipe b force quirk\n");
14912}
14913
435793df
KP		 14914/*
14915 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14916 */
14917static void quirk_ssc_force_disable(struct drm_device *dev)
14918{
14919 struct drm_i915_private *dev_priv = dev->dev_private;
14920 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14921 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14922}
14923
4dca20ef 14924/*
5a15ab5b
CE		 14925 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14926 * brightness value
4dca20ef
CE		 14927 */
14928static void quirk_invert_brightness(struct drm_device *dev)
14929{
14930 struct drm_i915_private *dev_priv = dev->dev_private;
14931 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14932 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14933}
14934
9c72cc6f
SD		 14935/* Some VBT's incorrectly indicate no backlight is present */
14936static void quirk_backlight_present(struct drm_device *dev)
14937{
14938 struct drm_i915_private *dev_priv = dev->dev_private;
14939 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14940 DRM_INFO("applying backlight present quirk\n");
14941}
14942
b690e96c
JB		 14943struct intel_quirk {
14944 int device;
14945 int subsystem_vendor;
14946 int subsystem_device;
14947 void (*hook)(struct drm_device *dev);
14948};
14949
5f85f176
EE		 14950/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14951struct intel_dmi_quirk {
14952 void (*hook)(struct drm_device *dev);
14953 const struct dmi_system_id (*dmi_id_list)[];
14954};
14955
14956static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14957{
14958 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14959 return 1;
14960}
14961
14962static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14963 {
14964 .dmi_id_list = &(const struct dmi_system_id[]) {
14965 {
14966 .callback = intel_dmi_reverse_brightness,
14967 .ident = "NCR Corporation",
14968 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14969 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14970 },
14971 },
14972 { } /* terminating entry */
14973 },
14974 .hook = quirk_invert_brightness,
14975 },
14976};
14977
c43b5634 14978static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14979 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14980 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14981
b690e96c
JB		 14982 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14983 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14984
5f080c0f
VS		 14985 /* 830 needs to leave pipe A & dpll A up */
14986 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14987
b6b5d049
VS		 14988 /* 830 needs to leave pipe B & dpll B up */
14989 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14990
435793df
KP		 14991 /* Lenovo U160 cannot use SSC on LVDS */
14992 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14993
14994 /* Sony Vaio Y cannot use SSC on LVDS */
14995 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14996
be505f64
AH		 14997 /* Acer Aspire 5734Z must invert backlight brightness */
14998 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14999
15000 /* Acer/eMachines G725 */
15001 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
15002
15003 /* Acer/eMachines e725 */
15004 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
15005
15006 /* Acer/Packard Bell NCL20 */
15007 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
15008
15009 /* Acer Aspire 4736Z */
15010 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 15011
15012 /* Acer Aspire 5336 */
15013 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 15014
15015 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
15016 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 15017
dfb3d47b
SD		 15018 /* Acer C720 Chromebook (Core i3 4005U) */
15019 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
15020
b2a9601c 15021 /* Apple Macbook 2,1 (Core 2 T7400) */
15022 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
15023
d4967d8c
SD		 15024 /* Toshiba CB35 Chromebook (Celeron 2955U) */
15025 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 15026
15027 /* HP Chromebook 14 (Celeron 2955U) */
15028 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 15029
15030 /* Dell Chromebook 11 */
15031 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 15032};
15033
15034static void intel_init_quirks(struct drm_device *dev)
15035{
15036 struct pci_dev *d = dev->pdev;
15037 int i;
15038
15039 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
15040 struct intel_quirk *q = &intel_quirks[i];
15041
15042 if (d->device == q->device &&
15043 (d->subsystem_vendor == q->subsystem_vendor ||
15044 q->subsystem_vendor == PCI_ANY_ID) &&
15045 (d->subsystem_device == q->subsystem_device ||
15046 q->subsystem_device == PCI_ANY_ID))
15047 q->hook(dev);
15048 }
5f85f176
EE		 15049 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
15050 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
15051 intel_dmi_quirks[i].hook(dev);
15052 }
b690e96c
JB		 15053}
15054
9cce37f4
JB		 15055/* Disable the VGA plane that we never use */
15056static void i915_disable_vga(struct drm_device *dev)
15057{
15058 struct drm_i915_private *dev_priv = dev->dev_private;
15059 u8 sr1;
766aa1c4 15060 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 15061
2b37c616 15062 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 15063 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 15064 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 15065 sr1 = inb(VGA_SR_DATA);
15066 outb(sr1 | 1<<5, VGA_SR_DATA);
15067 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
15068 udelay(300);
15069
01f5a626 15070 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 15071 POSTING_READ(vga_reg);
15072}
15073
f817586c
DV		 15074void intel_modeset_init_hw(struct drm_device *dev)
15075{
b6283055 15076 intel_update_cdclk(dev);
a8f78b58 15077 intel_prepare_ddi(dev);
f817586c 15078 intel_init_clock_gating(dev);
8090c6b9 15079 intel_enable_gt_powersave(dev);
f817586c
DV		 15080}
15081
79e53945
JB		 15082void intel_modeset_init(struct drm_device *dev)
15083{
652c393a 15084 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 15085 int sprite, ret;
8cc87b75 15086 enum pipe pipe;
46f297fb 15087 struct intel_crtc *crtc;
79e53945
JB		 15088
15089 drm_mode_config_init(dev);
15090
15091 dev->mode_config.min_width = 0;
15092 dev->mode_config.min_height = 0;
15093
019d96cb
DA		 15094 dev->mode_config.preferred_depth = 24;
15095 dev->mode_config.prefer_shadow = 1;
15096
25bab385
TU		 15097 dev->mode_config.allow_fb_modifiers = true;
15098
e6ecefaa 15099 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 15100
b690e96c
JB		 15101 intel_init_quirks(dev);
15102
1fa61106
ED		 15103 intel_init_pm(dev);
15104
e3c74757
BW		 15105 if (INTEL_INFO(dev)->num_pipes == 0)
15106 return;
15107
e70236a8 15108 intel_init_display(dev);
7c10a2b5 15109 intel_init_audio(dev);
e70236a8 15110
a6c45cf0
CW		 15111 if (IS_GEN2(dev)) {
15112 dev->mode_config.max_width = 2048;
15113 dev->mode_config.max_height = 2048;
15114 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 15115 dev->mode_config.max_width = 4096;
15116 dev->mode_config.max_height = 4096;
79e53945 15117 } else {
a6c45cf0
CW		 15118 dev->mode_config.max_width = 8192;
15119 dev->mode_config.max_height = 8192;
79e53945 15120 }
068be561 15121
dc41c154
VS		 15122 if (IS_845G(dev) || IS_I865G(dev)) {
15123 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
15124 dev->mode_config.cursor_height = 1023;
15125 } else if (IS_GEN2(dev)) {
068be561
DL		 15126 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
15127 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
15128 } else {
15129 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
15130 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
15131 }
15132
5d4545ae 15133 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 15134
28c97730 15135 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 15136 INTEL_INFO(dev)->num_pipes,
15137 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 15138
055e393f 15139 for_each_pipe(dev_priv, pipe) {
8cc87b75 15140 intel_crtc_init(dev, pipe);
3bdcfc0c 15141 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 15142 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 15143 if (ret)
06da8da2 15144 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 15145 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 15146 }
79e53945
JB		 15147 }
15148
f42bb70d
JB		 15149 intel_init_dpio(dev);
15150
e72f9fbf 15151 intel_shared_dpll_init(dev);
ee7b9f93 15152
9cce37f4
JB		 15153 /* Just disable it once at startup */
15154 i915_disable_vga(dev);
79e53945 15155 intel_setup_outputs(dev);
11be49eb
CW		 15156
15157 /* Just in case the BIOS is doing something questionable. */
7733b49b 15158 intel_fbc_disable(dev_priv);
fa9fa083 15159
6e9f798d 15160 drm_modeset_lock_all(dev);
043e9bda 15161 intel_modeset_setup_hw_state(dev);
6e9f798d 15162 drm_modeset_unlock_all(dev);
46f297fb 15163
d3fcc808 15164 for_each_intel_crtc(dev, crtc) {
eeebeac5
ML		 15165 struct intel_initial_plane_config plane_config = {};
15166
46f297fb
JB		 15167 if (!crtc->active)
15168 continue;
15169
46f297fb 15170 /*
46f297fb
JB		 15171 * Note that reserving the BIOS fb up front prevents us
15172 * from stuffing other stolen allocations like the ring
15173 * on top. This prevents some ugliness at boot time, and
15174 * can even allow for smooth boot transitions if the BIOS
15175 * fb is large enough for the active pipe configuration.
15176 */
eeebeac5
ML		 15177 dev_priv->display.get_initial_plane_config(crtc,
15178 &plane_config);
15179
15180 /*
15181 * If the fb is shared between multiple heads, we'll
15182 * just get the first one.
15183 */
15184 intel_find_initial_plane_obj(crtc, &plane_config);
46f297fb 15185 }
2c7111db
CW		 15186}
15187
7fad798e
DV		 15188static void intel_enable_pipe_a(struct drm_device *dev)
15189{
15190 struct intel_connector *connector;
15191 struct drm_connector *crt = NULL;
15192 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 15193 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 15194
15195 /* We can't just switch on the pipe A, we need to set things up with a
15196 * proper mode and output configuration. As a gross hack, enable pipe A
15197 * by enabling the load detect pipe once. */
3a3371ff 15198 for_each_intel_connector(dev, connector) {
7fad798e
DV		 15199 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
15200 crt = &connector->base;
15201 break;
15202 }
15203 }
15204
15205 if (!crt)
15206 return;
15207
208bf9fd 15208 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 15209 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 15210}
15211
fa555837
DV		 15212static bool
15213intel_check_plane_mapping(struct intel_crtc *crtc)
15214{
7eb552ae
BW		 15215 struct drm_device *dev = crtc->base.dev;
15216 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 15217 u32 reg, val;
15218
7eb552ae 15219 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 15220 return true;
15221
15222 reg = DSPCNTR(!crtc->plane);
15223 val = I915_READ(reg);
15224
15225 if ((val & DISPLAY_PLANE_ENABLE) &&
15226 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
15227 return false;
15228
15229 return true;
15230}
15231
24929352
DV		 15232static void intel_sanitize_crtc(struct intel_crtc *crtc)
15233{
15234 struct drm_device *dev = crtc->base.dev;
15235 struct drm_i915_private *dev_priv = dev->dev_private;
b17d48e2 15236 struct intel_encoder *encoder;
fa555837 15237 u32 reg;
b17d48e2 15238 bool enable;
24929352 15239
24929352 15240 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 15241 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 15242 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
15243
d3eaf884 15244 /* restore vblank interrupts to correct state */
9625604c 15245 drm_crtc_vblank_reset(&crtc->base);
d297e103 15246 if (crtc->active) {
3a03dfb0 15247 drm_calc_timestamping_constants(&crtc->base, &crtc->base.hwmode);
d297e103 15248 update_scanline_offset(crtc);
9625604c
DV		 15249 drm_crtc_vblank_on(&crtc->base);
15250 }
d3eaf884 15251
24929352 15252 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 15253 * disable the crtc (and hence change the state) if it is wrong. Note
15254 * that gen4+ has a fixed plane -> pipe mapping. */
15255 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 15256 bool plane;
15257
24929352
DV		 15258 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
15259 crtc->base.base.id);
15260
15261 /* Pipe has the wrong plane attached and the plane is active.
15262 * Temporarily change the plane mapping and disable everything
15263 * ... */
15264 plane = crtc->plane;
b70709a6 15265 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 15266 crtc->plane = !plane;
b17d48e2 15267 intel_crtc_disable_noatomic(&crtc->base);
24929352 15268 crtc->plane = plane;
24929352 15269 }
24929352 15270
7fad798e
DV		 15271 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
15272 crtc->pipe == PIPE_A && !crtc->active) {
15273 /* BIOS forgot to enable pipe A, this mostly happens after
15274 * resume. Force-enable the pipe to fix this, the update_dpms
15275 * call below we restore the pipe to the right state, but leave
15276 * the required bits on. */
15277 intel_enable_pipe_a(dev);
15278 }
15279
24929352
DV		 15280 /* Adjust the state of the output pipe according to whether we
15281 * have active connectors/encoders. */
b17d48e2
ML		 15282 enable = false;
15283 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
15284 enable |= encoder->connectors_active;
24929352 15285
b17d48e2
ML		 15286 if (!enable)
15287 intel_crtc_disable_noatomic(&crtc->base);
24929352 15288
53d9f4e9 15289 if (crtc->active != crtc->base.state->active) {
24929352
DV		 15290
15291 /* This can happen either due to bugs in the get_hw_state
b17d48e2
ML		 15292 * functions or because of calls to intel_crtc_disable_noatomic,
15293 * or because the pipe is force-enabled due to the
24929352
DV		 15294 * pipe A quirk. */
15295 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
15296 crtc->base.base.id,
83d65738 15297 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 15298 crtc->active ? "enabled" : "disabled");
15299
4be40c98 15300 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, NULL) < 0);
49d6fa21 15301 crtc->base.state->active = crtc->active;
24929352
DV		 15302 crtc->base.enabled = crtc->active;
15303
15304 /* Because we only establish the connector -> encoder ->
15305 * crtc links if something is active, this means the
15306 * crtc is now deactivated. Break the links. connector
15307 * -> encoder links are only establish when things are
15308 * actually up, hence no need to break them. */
15309 WARN_ON(crtc->active);
15310
15311 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
15312 WARN_ON(encoder->connectors_active);
15313 encoder->base.crtc = NULL;
15314 }
15315 }
c5ab3bc0 15316
a3ed6aad 15317 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 15318 /*
15319 * We start out with underrun reporting disabled to avoid races.
15320 * For correct bookkeeping mark this on active crtcs.
15321 *
c5ab3bc0
DV		 15322 * Also on gmch platforms we dont have any hardware bits to
15323 * disable the underrun reporting. Which means we need to start
15324 * out with underrun reporting disabled also on inactive pipes,
15325 * since otherwise we'll complain about the garbage we read when
15326 * e.g. coming up after runtime pm.
15327 *
4cc31489
DV		 15328 * No protection against concurrent access is required - at
15329 * worst a fifo underrun happens which also sets this to false.
15330 */
15331 crtc->cpu_fifo_underrun_disabled = true;
15332 crtc->pch_fifo_underrun_disabled = true;
15333 }
24929352
DV		 15334}
15335
15336static void intel_sanitize_encoder(struct intel_encoder *encoder)
15337{
15338 struct intel_connector *connector;
15339 struct drm_device *dev = encoder->base.dev;
15340
15341 /* We need to check both for a crtc link (meaning that the
15342 * encoder is active and trying to read from a pipe) and the
15343 * pipe itself being active. */
15344 bool has_active_crtc = encoder->base.crtc &&
15345 to_intel_crtc(encoder->base.crtc)->active;
15346
15347 if (encoder->connectors_active && !has_active_crtc) {
15348 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
15349 encoder->base.base.id,
8e329a03 15350 encoder->base.name);
24929352
DV		 15351
15352 /* Connector is active, but has no active pipe. This is
15353 * fallout from our resume register restoring. Disable
15354 * the encoder manually again. */
15355 if (encoder->base.crtc) {
15356 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
15357 encoder->base.base.id,
8e329a03 15358 encoder->base.name);
24929352 15359 encoder->disable(encoder);
a62d1497
VS		 15360 if (encoder->post_disable)
15361 encoder->post_disable(encoder);
24929352 15362 }
7f1950fb
EE		 15363 encoder->base.crtc = NULL;
15364 encoder->connectors_active = false;
24929352
DV		 15365
15366 /* Inconsistent output/port/pipe state happens presumably due to
15367 * a bug in one of the get_hw_state functions. Or someplace else
15368 * in our code, like the register restore mess on resume. Clamp
15369 * things to off as a safer default. */
3a3371ff 15370 for_each_intel_connector(dev, connector) {
24929352
DV		 15371 if (connector->encoder != encoder)
15372 continue;
7f1950fb
EE		 15373 connector->base.dpms = DRM_MODE_DPMS_OFF;
15374 connector->base.encoder = NULL;
24929352
DV		 15375 }
15376 }
15377 /* Enabled encoders without active connectors will be fixed in
15378 * the crtc fixup. */
15379}
15380
04098753 15381void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 15382{
15383 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 15384 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 15385
04098753
ID		 15386 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
15387 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
15388 i915_disable_vga(dev);
15389 }
15390}
15391
15392void i915_redisable_vga(struct drm_device *dev)
15393{
15394 struct drm_i915_private *dev_priv = dev->dev_private;
15395
8dc8a27c
PZ		 15396 /* This function can be called both from intel_modeset_setup_hw_state or
15397 * at a very early point in our resume sequence, where the power well
15398 * structures are not yet restored. Since this function is at a very
15399 * paranoid "someone might have enabled VGA while we were not looking"
15400 * level, just check if the power well is enabled instead of trying to
15401 * follow the "don't touch the power well if we don't need it" policy
15402 * the rest of the driver uses. */
f458ebbc 15403 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 15404 return;
15405
04098753 15406 i915_redisable_vga_power_on(dev);
0fde901f
KM		 15407}
15408
98ec7739
VS		 15409static bool primary_get_hw_state(struct intel_crtc *crtc)
15410{
15411 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15412
d032ffa0
ML		 15413 return !!(I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE);
15414}
15415
15416static void readout_plane_state(struct intel_crtc *crtc,
15417 struct intel_crtc_state *crtc_state)
15418{
15419 struct intel_plane *p;
4cf0ebbd 15420 struct intel_plane_state *plane_state;
d032ffa0
ML		 15421 bool active = crtc_state->base.active;
15422
d032ffa0 15423 for_each_intel_plane(crtc->base.dev, p) {
d032ffa0
ML		 15424 if (crtc->pipe != p->pipe)
15425 continue;
15426
4cf0ebbd 15427 plane_state = to_intel_plane_state(p->base.state);
e435d6e5 15428
4cf0ebbd
ML		 15429 if (p->base.type == DRM_PLANE_TYPE_PRIMARY)
15430 plane_state->visible = primary_get_hw_state(crtc);
15431 else {
15432 if (active)
15433 p->disable_plane(&p->base, &crtc->base);
d032ffa0 15434
4cf0ebbd 15435 plane_state->visible = false;
d032ffa0
ML		 15436 }
15437 }
98ec7739
VS		 15438}
15439
30e984df 15440static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15441{
15442 struct drm_i915_private *dev_priv = dev->dev_private;
15443 enum pipe pipe;
24929352
DV		 15444 struct intel_crtc *crtc;
15445 struct intel_encoder *encoder;
15446 struct intel_connector *connector;
5358901f 15447 int i;
24929352 15448
d3fcc808 15449 for_each_intel_crtc(dev, crtc) {
b06f8b0d 15450 __drm_atomic_helper_crtc_destroy_state(&crtc->base, crtc->base.state);
6e3c9717 15451 memset(crtc->config, 0, sizeof(*crtc->config));
f7217905 15452 crtc->config->base.crtc = &crtc->base;
3b117c8f 15453
6e3c9717 15454 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 15455
0e8ffe1b 15456 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15457 crtc->config);
24929352 15458
49d6fa21 15459 crtc->base.state->active = crtc->active;
24929352 15460 crtc->base.enabled = crtc->active;
b70709a6 15461
5c1e3426
ML		 15462 memset(&crtc->base.mode, 0, sizeof(crtc->base.mode));
15463 if (crtc->base.state->active) {
15464 intel_mode_from_pipe_config(&crtc->base.mode, crtc->config);
15465 intel_mode_from_pipe_config(&crtc->base.state->adjusted_mode, crtc->config);
15466 WARN_ON(drm_atomic_set_mode_for_crtc(crtc->base.state, &crtc->base.mode));
15467
15468 /*
15469 * The initial mode needs to be set in order to keep
15470 * the atomic core happy. It wants a valid mode if the
15471 * crtc's enabled, so we do the above call.
15472 *
15473 * At this point some state updated by the connectors
15474 * in their ->detect() callback has not run yet, so
15475 * no recalculation can be done yet.
15476 *
15477 * Even if we could do a recalculation and modeset
15478 * right now it would cause a double modeset if
15479 * fbdev or userspace chooses a different initial mode.
15480 *
15481 * So to prevent the double modeset, fail the memcmp
15482 * test in drm_atomic_set_mode_for_crtc to get a new
15483 * mode blob, and compare if the mode blob changed
15484 * when the PIPE_CONFIG_QUIRK_INHERITED_MODE quirk is
15485 * set.
15486 *
15487 * If that happens, someone indicated they wanted a
15488 * mode change, which means it's safe to do a full
15489 * recalculation.
15490 */
15491 crtc->base.state->mode.private_flags = ~0;
15492 }
15493
15494 crtc->base.hwmode = crtc->config->base.adjusted_mode;
d032ffa0 15495 readout_plane_state(crtc, to_intel_crtc_state(crtc->base.state));
24929352
DV		 15496
15497 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15498 crtc->base.base.id,
15499 crtc->active ? "enabled" : "disabled");
15500 }
15501
5358901f
DV		 15502 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15503 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15504
3e369b76
ACO		 15505 pll->on = pll->get_hw_state(dev_priv, pll,
15506 &pll->config.hw_state);
5358901f 15507 pll->active = 0;
3e369b76 15508 pll->config.crtc_mask = 0;
d3fcc808 15509 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15510 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15511 pll->active++;
3e369b76 15512 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15513 }
5358901f 15514 }
5358901f 15515
1e6f2ddc 15516 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15517 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15518
3e369b76 15519 if (pll->config.crtc_mask)
bd2bb1b9 15520 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15521 }
15522
b2784e15 15523 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15524 pipe = 0;
15525
15526 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15527 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15528 encoder->base.crtc = &crtc->base;
6e3c9717 15529 encoder->get_config(encoder, crtc->config);
24929352
DV		 15530 } else {
15531 encoder->base.crtc = NULL;
15532 }
15533
15534 encoder->connectors_active = false;
6f2bcceb 15535 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15536 encoder->base.base.id,
8e329a03 15537 encoder->base.name,
24929352 15538 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15539 pipe_name(pipe));
24929352
DV		 15540 }
15541
3a3371ff 15542 for_each_intel_connector(dev, connector) {
24929352
DV		 15543 if (connector->get_hw_state(connector)) {
15544 connector->base.dpms = DRM_MODE_DPMS_ON;
15545 connector->encoder->connectors_active = true;
15546 connector->base.encoder = &connector->encoder->base;
15547 } else {
15548 connector->base.dpms = DRM_MODE_DPMS_OFF;
15549 connector->base.encoder = NULL;
15550 }
15551 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15552 connector->base.base.id,
c23cc417 15553 connector->base.name,
24929352
DV		 15554 connector->base.encoder ? "enabled" : "disabled");
15555 }
30e984df
DV		 15556}
15557
043e9bda
ML		 15558/* Scan out the current hw modeset state,
15559 * and sanitizes it to the current state
15560 */
15561static void
15562intel_modeset_setup_hw_state(struct drm_device *dev)
30e984df
DV		 15563{
15564 struct drm_i915_private *dev_priv = dev->dev_private;
15565 enum pipe pipe;
30e984df
DV		 15566 struct intel_crtc *crtc;
15567 struct intel_encoder *encoder;
35c95375 15568 int i;
30e984df
DV		 15569
15570 intel_modeset_readout_hw_state(dev);
24929352
DV		 15571
15572 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15573 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15574 intel_sanitize_encoder(encoder);
15575 }
15576
055e393f 15577 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15578 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15579 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15580 intel_dump_pipe_config(crtc, crtc->config,
15581 "[setup_hw_state]");
24929352 15582 }
9a935856 15583
d29b2f9d
ACO		 15584 intel_modeset_update_connector_atomic_state(dev);
15585
35c95375
DV		 15586 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15587 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15588
15589 if (!pll->on || pll->active)
15590 continue;
15591
15592 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15593
15594 pll->disable(dev_priv, pll);
15595 pll->on = false;
15596 }
15597
26e1fe4f 15598 if (IS_VALLEYVIEW(dev))
6eb1a681
VS		 15599 vlv_wm_get_hw_state(dev);
15600 else if (IS_GEN9(dev))
3078999f
PB		 15601 skl_wm_get_hw_state(dev);
15602 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 15603 ilk_wm_get_hw_state(dev);
15604
043e9bda
ML		 15605 intel_modeset_update_staged_output_state(dev);
15606}
7d0bc1ea 15607
043e9bda
ML		 15608void intel_display_resume(struct drm_device *dev)
15609{
15610 struct drm_atomic_state *state = drm_atomic_state_alloc(dev);
15611 struct intel_connector *conn;
15612 struct intel_plane *plane;
15613 struct drm_crtc *crtc;
15614 int ret;
f30da187 15615
043e9bda
ML		 15616 if (!state)
15617 return;
15618
15619 state->acquire_ctx = dev->mode_config.acquire_ctx;
15620
15621 /* preserve complete old state, including dpll */
15622 intel_atomic_get_shared_dpll_state(state);
15623
15624 for_each_crtc(dev, crtc) {
15625 struct drm_crtc_state *crtc_state =
15626 drm_atomic_get_crtc_state(state, crtc);
15627
15628 ret = PTR_ERR_OR_ZERO(crtc_state);
15629 if (ret)
15630 goto err;
15631
15632 /* force a restore */
15633 crtc_state->mode_changed = true;
45e2b5f6 15634 }
8af6cf88 15635
043e9bda
ML		 15636 for_each_intel_plane(dev, plane) {
15637 ret = PTR_ERR_OR_ZERO(drm_atomic_get_plane_state(state, &plane->base));
15638 if (ret)
15639 goto err;
15640 }
15641
15642 for_each_intel_connector(dev, conn) {
15643 ret = PTR_ERR_OR_ZERO(drm_atomic_get_connector_state(state, &conn->base));
15644 if (ret)
15645 goto err;
15646 }
15647
15648 intel_modeset_setup_hw_state(dev);
15649
15650 i915_redisable_vga(dev);
15651 ret = intel_set_mode(state);
15652 if (!ret)
15653 return;
15654
15655err:
15656 DRM_ERROR("Restoring old state failed with %i\n", ret);
15657 drm_atomic_state_free(state);
2c7111db
CW		 15658}
15659
15660void intel_modeset_gem_init(struct drm_device *dev)
15661{
92122789 15662 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15663 struct drm_crtc *c;
2ff8fde1 15664 struct drm_i915_gem_object *obj;
e0d6149b 15665 int ret;
484b41dd 15666
ae48434c
ID		 15667 mutex_lock(&dev->struct_mutex);
15668 intel_init_gt_powersave(dev);
15669 mutex_unlock(&dev->struct_mutex);
15670
92122789
JB		 15671 /*
15672 * There may be no VBT; and if the BIOS enabled SSC we can
15673 * just keep using it to avoid unnecessary flicker. Whereas if the
15674 * BIOS isn't using it, don't assume it will work even if the VBT
15675 * indicates as much.
15676 */
15677 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15678 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15679 DREF_SSC1_ENABLE);
15680
1833b134 15681 intel_modeset_init_hw(dev);
02e792fb
DV		 15682
15683 intel_setup_overlay(dev);
484b41dd
JB		 15684
15685 /*
15686 * Make sure any fbs we allocated at startup are properly
15687 * pinned & fenced. When we do the allocation it's too early
15688 * for this.
15689 */
70e1e0ec 15690 for_each_crtc(dev, c) {
2ff8fde1
MR		 15691 obj = intel_fb_obj(c->primary->fb);
15692 if (obj == NULL)
484b41dd
JB		 15693 continue;
15694
e0d6149b
TU		 15695 mutex_lock(&dev->struct_mutex);
15696 ret = intel_pin_and_fence_fb_obj(c->primary,
15697 c->primary->fb,
15698 c->primary->state,
91af127f 15699 NULL, NULL);
e0d6149b
TU		 15700 mutex_unlock(&dev->struct_mutex);
15701 if (ret) {
484b41dd
JB		 15702 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15703 to_intel_crtc(c)->pipe);
66e514c1
DA		 15704 drm_framebuffer_unreference(c->primary->fb);
15705 c->primary->fb = NULL;
36750f28 15706 c->primary->crtc = c->primary->state->crtc = NULL;
afd65eb4 15707 update_state_fb(c->primary);
36750f28 15708 c->state->plane_mask &= ~(1 << drm_plane_index(c->primary));
484b41dd
JB		 15709 }
15710 }
0962c3c9
VS		 15711
15712 intel_backlight_register(dev);
79e53945
JB		 15713}
15714
4932e2c3
ID		 15715void intel_connector_unregister(struct intel_connector *intel_connector)
15716{
15717 struct drm_connector *connector = &intel_connector->base;
15718
15719 intel_panel_destroy_backlight(connector);
34ea3d38 15720 drm_connector_unregister(connector);
4932e2c3
ID		 15721}
15722
79e53945
JB		 15723void intel_modeset_cleanup(struct drm_device *dev)
15724{
652c393a 15725 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15726 struct drm_connector *connector;
652c393a 15727
2eb5252e
ID		 15728 intel_disable_gt_powersave(dev);
15729
0962c3c9
VS		 15730 intel_backlight_unregister(dev);
15731
fd0c0642
DV		 15732 /*
15733 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15734 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15735 * experience fancy races otherwise.
15736 */
2aeb7d3a 15737 intel_irq_uninstall(dev_priv);
eb21b92b 15738
fd0c0642
DV		 15739 /*
15740 * Due to the hpd irq storm handling the hotplug work can re-arm the
15741 * poll handlers. Hence disable polling after hpd handling is shut down.
15742 */
f87ea761 15743 drm_kms_helper_poll_fini(dev);
fd0c0642 15744
723bfd70
JB		 15745 intel_unregister_dsm_handler();
15746
7733b49b 15747 intel_fbc_disable(dev_priv);
69341a5e 15748
1630fe75
CW		 15749 /* flush any delayed tasks or pending work */
15750 flush_scheduled_work();
15751
db31af1d
JN		 15752 /* destroy the backlight and sysfs files before encoders/connectors */
15753 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15754 struct intel_connector *intel_connector;
15755
15756 intel_connector = to_intel_connector(connector);
15757 intel_connector->unregister(intel_connector);
db31af1d 15758 }
d9255d57 15759
79e53945 15760 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15761
15762 intel_cleanup_overlay(dev);
ae48434c
ID		 15763
15764 mutex_lock(&dev->struct_mutex);
15765 intel_cleanup_gt_powersave(dev);
15766 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15767}
15768
f1c79df3
ZW		 15769/*
15770 * Return which encoder is currently attached for connector.
15771 */
df0e9248 15772struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15773{
df0e9248
CW		 15774 return &intel_attached_encoder(connector)->base;
15775}
f1c79df3 15776
df0e9248
CW		 15777void intel_connector_attach_encoder(struct intel_connector *connector,
15778 struct intel_encoder *encoder)
15779{
15780 connector->encoder = encoder;
15781 drm_mode_connector_attach_encoder(&connector->base,
15782 &encoder->base);
79e53945 15783}
28d52043
DA		 15784
15785/*
15786 * set vga decode state - true == enable VGA decode
15787 */
15788int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15789{
15790 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15791 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15792 u16 gmch_ctrl;
15793
75fa041d
CW		 15794 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15795 DRM_ERROR("failed to read control word\n");
15796 return -EIO;
15797 }
15798
c0cc8a55
CW		 15799 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15800 return 0;
15801
28d52043
DA		 15802 if (state)
15803 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15804 else
15805 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15806
15807 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15808 DRM_ERROR("failed to write control word\n");
15809 return -EIO;
15810 }
15811
28d52043
DA		 15812 return 0;
15813}
c4a1d9e4 15814
c4a1d9e4 15815struct intel_display_error_state {
ff57f1b0
PZ		 15816
15817 u32 power_well_driver;
15818
63b66e5b
CW		 15819 int num_transcoders;
15820
c4a1d9e4
CW		 15821 struct intel_cursor_error_state {
15822 u32 control;
15823 u32 position;
15824 u32 base;
15825 u32 size;
52331309 15826 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15827
15828 struct intel_pipe_error_state {
ddf9c536 15829 bool power_domain_on;
c4a1d9e4 15830 u32 source;
f301b1e1 15831 u32 stat;
52331309 15832 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15833
15834 struct intel_plane_error_state {
15835 u32 control;
15836 u32 stride;
15837 u32 size;
15838 u32 pos;
15839 u32 addr;
15840 u32 surface;
15841 u32 tile_offset;
52331309 15842 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15843
15844 struct intel_transcoder_error_state {
ddf9c536 15845 bool power_domain_on;
63b66e5b
CW		 15846 enum transcoder cpu_transcoder;
15847
15848 u32 conf;
15849
15850 u32 htotal;
15851 u32 hblank;
15852 u32 hsync;
15853 u32 vtotal;
15854 u32 vblank;
15855 u32 vsync;
15856 } transcoder[4];
c4a1d9e4
CW		 15857};
15858
15859struct intel_display_error_state *
15860intel_display_capture_error_state(struct drm_device *dev)
15861{
fbee40df 15862 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15863 struct intel_display_error_state *error;
63b66e5b
CW		 15864 int transcoders[] = {
15865 TRANSCODER_A,
15866 TRANSCODER_B,
15867 TRANSCODER_C,
15868 TRANSCODER_EDP,
15869 };
c4a1d9e4
CW		 15870 int i;
15871
63b66e5b
CW		 15872 if (INTEL_INFO(dev)->num_pipes == 0)
15873 return NULL;
15874
9d1cb914 15875 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15876 if (error == NULL)
15877 return NULL;
15878
190be112 15879 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15880 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15881
055e393f 15882 for_each_pipe(dev_priv, i) {
ddf9c536 15883 error->pipe[i].power_domain_on =
f458ebbc
DV		 15884 __intel_display_power_is_enabled(dev_priv,
15885 POWER_DOMAIN_PIPE(i));
ddf9c536 15886 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15887 continue;
15888
5efb3e28
VS		 15889 error->cursor[i].control = I915_READ(CURCNTR(i));
15890 error->cursor[i].position = I915_READ(CURPOS(i));
15891 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15892
15893 error->plane[i].control = I915_READ(DSPCNTR(i));
15894 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15895 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15896 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15897 error->plane[i].pos = I915_READ(DSPPOS(i));
15898 }
ca291363
PZ		 15899 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15900 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15901 if (INTEL_INFO(dev)->gen >= 4) {
15902 error->plane[i].surface = I915_READ(DSPSURF(i));
15903 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15904 }
15905
c4a1d9e4 15906 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15907
3abfce77 15908 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15909 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15910 }
15911
15912 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15913 if (HAS_DDI(dev_priv->dev))
15914 error->num_transcoders++; /* Account for eDP. */
15915
15916 for (i = 0; i < error->num_transcoders; i++) {
15917 enum transcoder cpu_transcoder = transcoders[i];
15918
ddf9c536 15919 error->transcoder[i].power_domain_on =
f458ebbc 15920 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15921 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15922 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15923 continue;
15924
63b66e5b
CW		 15925 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15926
15927 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15928 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15929 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15930 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15931 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15932 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15933 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15934 }
15935
15936 return error;
15937}
15938
edc3d884
MK		 15939#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15940
c4a1d9e4 15941void
edc3d884 15942intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15943 struct drm_device *dev,
15944 struct intel_display_error_state *error)
15945{
055e393f 15946 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15947 int i;
15948
63b66e5b
CW		 15949 if (!error)
15950 return;
15951
edc3d884 15952 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15953 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15954 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15955 error->power_well_driver);
055e393f 15956 for_each_pipe(dev_priv, i) {
edc3d884 15957 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15958 err_printf(m, " Power: %s\n",
15959 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15960 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15961 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15962
15963 err_printf(m, "Plane [%d]:\n", i);
15964 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15965 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15966 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15967 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15968 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15969 }
4b71a570 15970 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15971 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15972 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15973 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15974 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15975 }
15976
edc3d884
MK		 15977 err_printf(m, "Cursor [%d]:\n", i);
15978 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15979 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15980 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15981 }
63b66e5b
CW		 15982
15983 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15984 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15985 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15986 err_printf(m, " Power: %s\n",
15987 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15988 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15989 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15990 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15991 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15992 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15993 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15994 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15995 }
c4a1d9e4 15996}
e2fcdaa9
VS		 15997
15998void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15999{
16000 struct intel_crtc *crtc;
16001
16002 for_each_intel_crtc(dev, crtc) {
16003 struct intel_unpin_work *work;
e2fcdaa9 16004
5e2d7afc 16005 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 16006
16007 work = crtc->unpin_work;
16008
16009 if (work && work->event &&
16010 work->event->base.file_priv == file) {
16011 kfree(work->event);
16012 work->event = NULL;
16013 }
16014
5e2d7afc 16015 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 16016 }
16017}
Linux kernel - Deliverables
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