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drm/i915: refactor sink bpp clamping
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
f4808ab8
VS		 62 /**
63 * find_pll() - Find the best values for the PLL
64 * @limit: limits for the PLL
65 * @crtc: current CRTC
66 * @target: target frequency in kHz
67 * @refclk: reference clock frequency in kHz
68 * @match_clock: if provided, @best_clock P divider must
69 * match the P divider from @match_clock
70 * used for LVDS downclocking
71 * @best_clock: best PLL values found
72 *
73 * Returns true on success, false on failure.
74 */
75 bool (*find_pll)(const intel_limit_t *limit,
76 struct drm_crtc *crtc,
77 int target, int refclk,
78 intel_clock_t *match_clock,
79 intel_clock_t *best_clock);
d4906093 80};
79e53945 81
2377b741
JB		 82/* FDI */
83#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84
d2acd215
DV		 85int
86intel_pch_rawclk(struct drm_device *dev)
87{
88 struct drm_i915_private *dev_priv = dev->dev_private;
89
90 WARN_ON(!HAS_PCH_SPLIT(dev));
91
92 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
93}
94
d4906093
ML		 95static bool
96intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
d4906093
ML		 99static bool
100intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 101 int target, int refclk, intel_clock_t *match_clock,
102 intel_clock_t *best_clock);
79e53945 103
a0c4da24
JB		 104static bool
105intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
108
021357ac
CW		 109static inline u32 /* units of 100MHz */
110intel_fdi_link_freq(struct drm_device *dev)
111{
8b99e68c
CW		 112 if (IS_GEN5(dev)) {
113 struct drm_i915_private *dev_priv = dev->dev_private;
114 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
115 } else
116 return 27;
021357ac
CW		 117}
118
e4b36699 119static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 120 .dot = { .min = 25000, .max = 350000 },
121 .vco = { .min = 930000, .max = 1400000 },
122 .n = { .min = 3, .max = 16 },
123 .m = { .min = 96, .max = 140 },
124 .m1 = { .min = 18, .max = 26 },
125 .m2 = { .min = 6, .max = 16 },
126 .p = { .min = 4, .max = 128 },
127 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 128 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 2 },
d4906093 130 .find_pll = intel_find_best_PLL,
e4b36699
KP		 131};
132
133static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 134 .dot = { .min = 25000, .max = 350000 },
135 .vco = { .min = 930000, .max = 1400000 },
136 .n = { .min = 3, .max = 16 },
137 .m = { .min = 96, .max = 140 },
138 .m1 = { .min = 18, .max = 26 },
139 .m2 = { .min = 6, .max = 16 },
140 .p = { .min = 4, .max = 128 },
141 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 142 .p2 = { .dot_limit = 165000,
143 .p2_slow = 14, .p2_fast = 7 },
d4906093 144 .find_pll = intel_find_best_PLL,
e4b36699 145};
273e27ca 146
e4b36699 147static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 154 .p = { .min = 5, .max = 80 },
155 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 156 .p2 = { .dot_limit = 200000,
157 .p2_slow = 10, .p2_fast = 5 },
d4906093 158 .find_pll = intel_find_best_PLL,
e4b36699
KP		 159};
160
161static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 162 .dot = { .min = 20000, .max = 400000 },
163 .vco = { .min = 1400000, .max = 2800000 },
164 .n = { .min = 1, .max = 6 },
165 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 166 .m1 = { .min = 8, .max = 18 },
167 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 168 .p = { .min = 7, .max = 98 },
169 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 170 .p2 = { .dot_limit = 112000,
171 .p2_slow = 14, .p2_fast = 7 },
d4906093 172 .find_pll = intel_find_best_PLL,
e4b36699
KP		 173};
174
273e27ca 175
e4b36699 176static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 177 .dot = { .min = 25000, .max = 270000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 17, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 10, .max = 30 },
184 .p1 = { .min = 1, .max = 3},
185 .p2 = { .dot_limit = 270000,
186 .p2_slow = 10,
187 .p2_fast = 10
044c7c41 188 },
d4906093 189 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 190};
191
192static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 193 .dot = { .min = 22000, .max = 400000 },
194 .vco = { .min = 1750000, .max = 3500000},
195 .n = { .min = 1, .max = 4 },
196 .m = { .min = 104, .max = 138 },
197 .m1 = { .min = 16, .max = 23 },
198 .m2 = { .min = 5, .max = 11 },
199 .p = { .min = 5, .max = 80 },
200 .p1 = { .min = 1, .max = 8},
201 .p2 = { .dot_limit = 165000,
202 .p2_slow = 10, .p2_fast = 5 },
d4906093 203 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 204};
205
206static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 207 .dot = { .min = 20000, .max = 115000 },
208 .vco = { .min = 1750000, .max = 3500000 },
209 .n = { .min = 1, .max = 3 },
210 .m = { .min = 104, .max = 138 },
211 .m1 = { .min = 17, .max = 23 },
212 .m2 = { .min = 5, .max = 11 },
213 .p = { .min = 28, .max = 112 },
214 .p1 = { .min = 2, .max = 8 },
215 .p2 = { .dot_limit = 0,
216 .p2_slow = 14, .p2_fast = 14
044c7c41 217 },
d4906093 218 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 219};
220
221static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 222 .dot = { .min = 80000, .max = 224000 },
223 .vco = { .min = 1750000, .max = 3500000 },
224 .n = { .min = 1, .max = 3 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 14, .max = 42 },
229 .p1 = { .min = 2, .max = 6 },
230 .p2 = { .dot_limit = 0,
231 .p2_slow = 7, .p2_fast = 7
044c7c41 232 },
d4906093 233 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 234};
235
f2b115e6 236static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 237 .dot = { .min = 20000, .max = 400000},
238 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 239 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 240 .n = { .min = 3, .max = 6 },
241 .m = { .min = 2, .max = 256 },
273e27ca 242 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 243 .m1 = { .min = 0, .max = 0 },
244 .m2 = { .min = 0, .max = 254 },
245 .p = { .min = 5, .max = 80 },
246 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 247 .p2 = { .dot_limit = 200000,
248 .p2_slow = 10, .p2_fast = 5 },
6115707b 249 .find_pll = intel_find_best_PLL,
e4b36699
KP		 250};
251
f2b115e6 252static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 253 .dot = { .min = 20000, .max = 400000 },
254 .vco = { .min = 1700000, .max = 3500000 },
255 .n = { .min = 3, .max = 6 },
256 .m = { .min = 2, .max = 256 },
257 .m1 = { .min = 0, .max = 0 },
258 .m2 = { .min = 0, .max = 254 },
259 .p = { .min = 7, .max = 112 },
260 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 261 .p2 = { .dot_limit = 112000,
262 .p2_slow = 14, .p2_fast = 14 },
6115707b 263 .find_pll = intel_find_best_PLL,
e4b36699
KP		 264};
265
273e27ca
EA		 266/* Ironlake / Sandybridge
267 *
268 * We calculate clock using (register_value + 2) for N/M1/M2, so here
269 * the range value for them is (actual_value - 2).
270 */
b91ad0ec 271static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 272 .dot = { .min = 25000, .max = 350000 },
273 .vco = { .min = 1760000, .max = 3510000 },
274 .n = { .min = 1, .max = 5 },
275 .m = { .min = 79, .max = 127 },
276 .m1 = { .min = 12, .max = 22 },
277 .m2 = { .min = 5, .max = 9 },
278 .p = { .min = 5, .max = 80 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 225000,
281 .p2_slow = 10, .p2_fast = 5 },
4547668a 282 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 283};
284
b91ad0ec 285static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 286 .dot = { .min = 25000, .max = 350000 },
287 .vco = { .min = 1760000, .max = 3510000 },
288 .n = { .min = 1, .max = 3 },
289 .m = { .min = 79, .max = 118 },
290 .m1 = { .min = 12, .max = 22 },
291 .m2 = { .min = 5, .max = 9 },
292 .p = { .min = 28, .max = 112 },
293 .p1 = { .min = 2, .max = 8 },
294 .p2 = { .dot_limit = 225000,
295 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 296 .find_pll = intel_g4x_find_best_PLL,
297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 127 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 56 },
307 .p1 = { .min = 2, .max = 8 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 310 .find_pll = intel_g4x_find_best_PLL,
311};
312
273e27ca 313/* LVDS 100mhz refclk limits. */
b91ad0ec 314static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 2 },
318 .m = { .min = 79, .max = 126 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 28, .max = 112 },
0206e353 322 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 325 .find_pll = intel_g4x_find_best_PLL,
326};
327
328static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 126 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 14, .max = 42 },
0206e353 336 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 339 .find_pll = intel_g4x_find_best_PLL,
340};
341
a0c4da24
JB		 342static const intel_limit_t intel_limits_vlv_dac = {
343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
345 .n = { .min = 1, .max = 7 },
346 .m = { .min = 22, .max = 450 }, /* guess */
347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
75e53986 350 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
353 .find_pll = intel_vlv_find_best_pll,
354};
355
356static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 357 .dot = { .min = 25000, .max = 270000 },
358 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 359 .n = { .min = 1, .max = 7 },
360 .m = { .min = 60, .max = 300 }, /* guess */
361 .m1 = { .min = 2, .max = 3 },
362 .m2 = { .min = 11, .max = 156 },
363 .p = { .min = 10, .max = 30 },
364 .p1 = { .min = 2, .max = 3 },
365 .p2 = { .dot_limit = 270000,
366 .p2_slow = 2, .p2_fast = 20 },
367 .find_pll = intel_vlv_find_best_pll,
368};
369
370static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 371 .dot = { .min = 25000, .max = 270000 },
372 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 373 .n = { .min = 1, .max = 7 },
74a4dd2e 374 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 375 .m1 = { .min = 2, .max = 3 },
376 .m2 = { .min = 11, .max = 156 },
377 .p = { .min = 10, .max = 30 },
75e53986 378 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 379 .p2 = { .dot_limit = 270000,
380 .p2_slow = 2, .p2_fast = 20 },
381 .find_pll = intel_vlv_find_best_pll,
382};
383
1b894b59
CW		 384static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
385 int refclk)
2c07245f 386{
b91ad0ec 387 struct drm_device *dev = crtc->dev;
2c07245f 388 const intel_limit_t *limit;
b91ad0ec
ZW		 389
390 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 391 if (intel_is_dual_link_lvds(dev)) {
1b894b59 392 if (refclk == 100000)
b91ad0ec
ZW		 393 limit = &intel_limits_ironlake_dual_lvds_100m;
394 else
395 limit = &intel_limits_ironlake_dual_lvds;
396 } else {
1b894b59 397 if (refclk == 100000)
b91ad0ec
ZW		 398 limit = &intel_limits_ironlake_single_lvds_100m;
399 else
400 limit = &intel_limits_ironlake_single_lvds;
401 }
c6bb3538 402 } else
b91ad0ec 403 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 404
405 return limit;
406}
407
044c7c41
ML		 408static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
409{
410 struct drm_device *dev = crtc->dev;
044c7c41
ML		 411 const intel_limit_t *limit;
412
413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 414 if (intel_is_dual_link_lvds(dev))
e4b36699 415 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 416 else
e4b36699 417 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 418 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
419 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 420 limit = &intel_limits_g4x_hdmi;
044c7c41 421 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 422 limit = &intel_limits_g4x_sdvo;
044c7c41 423 } else /* The option is for other outputs */
e4b36699 424 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 425
426 return limit;
427}
428
1b894b59 429static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 430{
431 struct drm_device *dev = crtc->dev;
432 const intel_limit_t *limit;
433
bad720ff 434 if (HAS_PCH_SPLIT(dev))
1b894b59 435 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 436 else if (IS_G4X(dev)) {
044c7c41 437 limit = intel_g4x_limit(crtc);
f2b115e6 438 } else if (IS_PINEVIEW(dev)) {
2177832f 439 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 440 limit = &intel_limits_pineview_lvds;
2177832f 441 else
f2b115e6 442 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 443 } else if (IS_VALLEYVIEW(dev)) {
444 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
445 limit = &intel_limits_vlv_dac;
446 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
447 limit = &intel_limits_vlv_hdmi;
448 else
449 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 450 } else if (!IS_GEN2(dev)) {
451 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
452 limit = &intel_limits_i9xx_lvds;
453 else
454 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 455 } else {
456 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 457 limit = &intel_limits_i8xx_lvds;
79e53945 458 else
e4b36699 459 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 460 }
461 return limit;
462}
463
f2b115e6
AJ		 464/* m1 is reserved as 0 in Pineview, n is a ring counter */
465static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 466{
2177832f
SL		 467 clock->m = clock->m2 + 2;
468 clock->p = clock->p1 * clock->p2;
469 clock->vco = refclk * clock->m / clock->n;
470 clock->dot = clock->vco / clock->p;
471}
472
7429e9d4
DV		 473static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
474{
475 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
476}
477
2177832f
SL		 478static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
479{
f2b115e6
AJ		 480 if (IS_PINEVIEW(dev)) {
481 pineview_clock(refclk, clock);
2177832f
SL		 482 return;
483 }
7429e9d4 484 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 485 clock->p = clock->p1 * clock->p2;
486 clock->vco = refclk * clock->m / (clock->n + 2);
487 clock->dot = clock->vco / clock->p;
488}
489
79e53945
JB		 490/**
491 * Returns whether any output on the specified pipe is of the specified type
492 */
4ef69c7a 493bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 494{
4ef69c7a 495 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 496 struct intel_encoder *encoder;
497
6c2b7c12
DV		 498 for_each_encoder_on_crtc(dev, crtc, encoder)
499 if (encoder->type == type)
4ef69c7a
CW		 500 return true;
501
502 return false;
79e53945
JB		 503}
504
7c04d1d9 505#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 506/**
507 * Returns whether the given set of divisors are valid for a given refclk with
508 * the given connectors.
509 */
510
1b894b59
CW		 511static bool intel_PLL_is_valid(struct drm_device *dev,
512 const intel_limit_t *limit,
513 const intel_clock_t *clock)
79e53945 514{
79e53945 515 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 516 INTELPllInvalid("p1 out of range\n");
79e53945 517 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 518 INTELPllInvalid("p out of range\n");
79e53945 519 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 520 INTELPllInvalid("m2 out of range\n");
79e53945 521 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 522 INTELPllInvalid("m1 out of range\n");
f2b115e6 523 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 524 INTELPllInvalid("m1 <= m2\n");
79e53945 525 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 526 INTELPllInvalid("m out of range\n");
79e53945 527 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 528 INTELPllInvalid("n out of range\n");
79e53945 529 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 530 INTELPllInvalid("vco out of range\n");
79e53945
JB		 531 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
532 * connector, etc., rather than just a single range.
533 */
534 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 535 INTELPllInvalid("dot out of range\n");
79e53945
JB		 536
537 return true;
538}
539
d4906093
ML		 540static bool
541intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 542 int target, int refclk, intel_clock_t *match_clock,
543 intel_clock_t *best_clock)
d4906093 544
79e53945
JB		 545{
546 struct drm_device *dev = crtc->dev;
79e53945 547 intel_clock_t clock;
79e53945
JB		 548 int err = target;
549
a210b028 550 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 551 /*
a210b028
DV		 552 * For LVDS just rely on its current settings for dual-channel.
553 * We haven't figured out how to reliably set up different
554 * single/dual channel state, if we even can.
79e53945 555 */
1974cad0 556 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 557 clock.p2 = limit->p2.p2_fast;
558 else
559 clock.p2 = limit->p2.p2_slow;
560 } else {
561 if (target < limit->p2.dot_limit)
562 clock.p2 = limit->p2.p2_slow;
563 else
564 clock.p2 = limit->p2.p2_fast;
565 }
566
0206e353 567 memset(best_clock, 0, sizeof(*best_clock));
79e53945 568
42158660
ZY		 569 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
570 clock.m1++) {
571 for (clock.m2 = limit->m2.min;
572 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 573 /* m1 is always 0 in Pineview */
574 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 575 break;
576 for (clock.n = limit->n.min;
577 clock.n <= limit->n.max; clock.n++) {
578 for (clock.p1 = limit->p1.min;
579 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 580 int this_err;
581
2177832f 582 intel_clock(dev, refclk, &clock);
1b894b59
CW		 583 if (!intel_PLL_is_valid(dev, limit,
584 &clock))
79e53945 585 continue;
cec2f356
SP		 586 if (match_clock &&
587 clock.p != match_clock->p)
588 continue;
79e53945
JB		 589
590 this_err = abs(clock.dot - target);
591 if (this_err < err) {
592 *best_clock = clock;
593 err = this_err;
594 }
595 }
596 }
597 }
598 }
599
600 return (err != target);
601}
602
d4906093
ML		 603static bool
604intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 605 int target, int refclk, intel_clock_t *match_clock,
606 intel_clock_t *best_clock)
d4906093
ML		 607{
608 struct drm_device *dev = crtc->dev;
d4906093
ML		 609 intel_clock_t clock;
610 int max_n;
611 bool found;
6ba770dc
AJ		 612 /* approximately equals target * 0.00585 */
613 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 614 found = false;
615
616 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 617 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 618 clock.p2 = limit->p2.p2_fast;
619 else
620 clock.p2 = limit->p2.p2_slow;
621 } else {
622 if (target < limit->p2.dot_limit)
623 clock.p2 = limit->p2.p2_slow;
624 else
625 clock.p2 = limit->p2.p2_fast;
626 }
627
628 memset(best_clock, 0, sizeof(*best_clock));
629 max_n = limit->n.max;
f77f13e2 630 /* based on hardware requirement, prefer smaller n to precision */
d4906093 631 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 632 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 633 for (clock.m1 = limit->m1.max;
634 clock.m1 >= limit->m1.min; clock.m1--) {
635 for (clock.m2 = limit->m2.max;
636 clock.m2 >= limit->m2.min; clock.m2--) {
637 for (clock.p1 = limit->p1.max;
638 clock.p1 >= limit->p1.min; clock.p1--) {
639 int this_err;
640
2177832f 641 intel_clock(dev, refclk, &clock);
1b894b59
CW		 642 if (!intel_PLL_is_valid(dev, limit,
643 &clock))
d4906093 644 continue;
1b894b59
CW		 645
646 this_err = abs(clock.dot - target);
d4906093
ML		 647 if (this_err < err_most) {
648 *best_clock = clock;
649 err_most = this_err;
650 max_n = clock.n;
651 found = true;
652 }
653 }
654 }
655 }
656 }
2c07245f
ZW		 657 return found;
658}
659
a0c4da24
JB		 660static bool
661intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
662 int target, int refclk, intel_clock_t *match_clock,
663 intel_clock_t *best_clock)
664{
665 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
666 u32 m, n, fastclk;
667 u32 updrate, minupdate, fracbits, p;
668 unsigned long bestppm, ppm, absppm;
669 int dotclk, flag;
670
af447bd3 671 flag = 0;
a0c4da24
JB		 672 dotclk = target * 1000;
673 bestppm = 1000000;
674 ppm = absppm = 0;
675 fastclk = dotclk / (2*100);
676 updrate = 0;
677 minupdate = 19200;
678 fracbits = 1;
679 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
680 bestm1 = bestm2 = bestp1 = bestp2 = 0;
681
682 /* based on hardware requirement, prefer smaller n to precision */
683 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
684 updrate = refclk / n;
685 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
686 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
687 if (p2 > 10)
688 p2 = p2 - 1;
689 p = p1 * p2;
690 /* based on hardware requirement, prefer bigger m1,m2 values */
691 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
692 m2 = (((2*(fastclk * p * n / m1 )) +
693 refclk) / (2*refclk));
694 m = m1 * m2;
695 vco = updrate * m;
696 if (vco >= limit->vco.min && vco < limit->vco.max) {
697 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
698 absppm = (ppm > 0) ? ppm : (-ppm);
699 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
700 bestppm = 0;
701 flag = 1;
702 }
703 if (absppm < bestppm - 10) {
704 bestppm = absppm;
705 flag = 1;
706 }
707 if (flag) {
708 bestn = n;
709 bestm1 = m1;
710 bestm2 = m2;
711 bestp1 = p1;
712 bestp2 = p2;
713 flag = 0;
714 }
715 }
716 }
717 }
718 }
719 }
720 best_clock->n = bestn;
721 best_clock->m1 = bestm1;
722 best_clock->m2 = bestm2;
723 best_clock->p1 = bestp1;
724 best_clock->p2 = bestp2;
725
726 return true;
727}
a4fc5ed6 728
a5c961d1
PZ		 729enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
730 enum pipe pipe)
731{
732 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
734
3b117c8f 735 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 736}
737
a928d536
PZ		 738static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
739{
740 struct drm_i915_private *dev_priv = dev->dev_private;
741 u32 frame, frame_reg = PIPEFRAME(pipe);
742
743 frame = I915_READ(frame_reg);
744
745 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
746 DRM_DEBUG_KMS("vblank wait timed out\n");
747}
748
9d0498a2
JB		 749/**
750 * intel_wait_for_vblank - wait for vblank on a given pipe
751 * @dev: drm device
752 * @pipe: pipe to wait for
753 *
754 * Wait for vblank to occur on a given pipe. Needed for various bits of
755 * mode setting code.
756 */
757void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 758{
9d0498a2 759 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 760 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 761
a928d536
PZ		 762 if (INTEL_INFO(dev)->gen >= 5) {
763 ironlake_wait_for_vblank(dev, pipe);
764 return;
765 }
766
300387c0
CW		 767 /* Clear existing vblank status. Note this will clear any other
768 * sticky status fields as well.
769 *
770 * This races with i915_driver_irq_handler() with the result
771 * that either function could miss a vblank event. Here it is not
772 * fatal, as we will either wait upon the next vblank interrupt or
773 * timeout. Generally speaking intel_wait_for_vblank() is only
774 * called during modeset at which time the GPU should be idle and
775 * should *not* be performing page flips and thus not waiting on
776 * vblanks...
777 * Currently, the result of us stealing a vblank from the irq
778 * handler is that a single frame will be skipped during swapbuffers.
779 */
780 I915_WRITE(pipestat_reg,
781 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
782
9d0498a2 783 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 784 if (wait_for(I915_READ(pipestat_reg) &
785 PIPE_VBLANK_INTERRUPT_STATUS,
786 50))
9d0498a2
JB		 787 DRM_DEBUG_KMS("vblank wait timed out\n");
788}
789
ab7ad7f6
KP		 790/*
791 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 792 * @dev: drm device
793 * @pipe: pipe to wait for
794 *
795 * After disabling a pipe, we can't wait for vblank in the usual way,
796 * spinning on the vblank interrupt status bit, since we won't actually
797 * see an interrupt when the pipe is disabled.
798 *
ab7ad7f6
KP		 799 * On Gen4 and above:
800 * wait for the pipe register state bit to turn off
801 *
802 * Otherwise:
803 * wait for the display line value to settle (it usually
804 * ends up stopping at the start of the next frame).
58e10eb9 805 *
9d0498a2 806 */
58e10eb9 807void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 808{
809 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 810 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
811 pipe);
ab7ad7f6
KP		 812
813 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 814 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 815
816 /* Wait for the Pipe State to go off */
58e10eb9
CW		 817 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
818 100))
284637d9 819 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 820 } else {
837ba00f 821 u32 last_line, line_mask;
58e10eb9 822 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 823 unsigned long timeout = jiffies + msecs_to_jiffies(100);
824
837ba00f
PZ		 825 if (IS_GEN2(dev))
826 line_mask = DSL_LINEMASK_GEN2;
827 else
828 line_mask = DSL_LINEMASK_GEN3;
829
ab7ad7f6
KP		 830 /* Wait for the display line to settle */
831 do {
837ba00f 832 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 833 mdelay(5);
837ba00f 834 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 835 time_after(timeout, jiffies));
836 if (time_after(jiffies, timeout))
284637d9 837 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 838 }
79e53945
JB		 839}
840
b0ea7d37
DL		 841/*
842 * ibx_digital_port_connected - is the specified port connected?
843 * @dev_priv: i915 private structure
844 * @port: the port to test
845 *
846 * Returns true if @port is connected, false otherwise.
847 */
848bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
849 struct intel_digital_port *port)
850{
851 u32 bit;
852
c36346e3
DL		 853 if (HAS_PCH_IBX(dev_priv->dev)) {
854 switch(port->port) {
855 case PORT_B:
856 bit = SDE_PORTB_HOTPLUG;
857 break;
858 case PORT_C:
859 bit = SDE_PORTC_HOTPLUG;
860 break;
861 case PORT_D:
862 bit = SDE_PORTD_HOTPLUG;
863 break;
864 default:
865 return true;
866 }
867 } else {
868 switch(port->port) {
869 case PORT_B:
870 bit = SDE_PORTB_HOTPLUG_CPT;
871 break;
872 case PORT_C:
873 bit = SDE_PORTC_HOTPLUG_CPT;
874 break;
875 case PORT_D:
876 bit = SDE_PORTD_HOTPLUG_CPT;
877 break;
878 default:
879 return true;
880 }
b0ea7d37
DL		 881 }
882
883 return I915_READ(SDEISR) & bit;
884}
885
b24e7179
JB		 886static const char *state_string(bool enabled)
887{
888 return enabled ? "on" : "off";
889}
890
891/* Only for pre-ILK configs */
892static void assert_pll(struct drm_i915_private *dev_priv,
893 enum pipe pipe, bool state)
894{
895 int reg;
896 u32 val;
897 bool cur_state;
898
899 reg = DPLL(pipe);
900 val = I915_READ(reg);
901 cur_state = !!(val & DPLL_VCO_ENABLE);
902 WARN(cur_state != state,
903 "PLL state assertion failure (expected %s, current %s)\n",
904 state_string(state), state_string(cur_state));
905}
906#define assert_pll_enabled(d, p) assert_pll(d, p, true)
907#define assert_pll_disabled(d, p) assert_pll(d, p, false)
908
040484af
JB		 909/* For ILK+ */
910static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 911 struct intel_pch_pll *pll,
912 struct intel_crtc *crtc,
913 bool state)
040484af 914{
040484af
JB		 915 u32 val;
916 bool cur_state;
917
9d82aa17
ED		 918 if (HAS_PCH_LPT(dev_priv->dev)) {
919 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
920 return;
921 }
922
92b27b08
CW		 923 if (WARN (!pll,
924 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 925 return;
ee7b9f93 926
92b27b08
CW		 927 val = I915_READ(pll->pll_reg);
928 cur_state = !!(val & DPLL_VCO_ENABLE);
929 WARN(cur_state != state,
930 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
931 pll->pll_reg, state_string(state), state_string(cur_state), val);
932
933 /* Make sure the selected PLL is correctly attached to the transcoder */
934 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 935 u32 pch_dpll;
936
937 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 938 cur_state = pll->pll_reg == _PCH_DPLL_B;
939 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
4bb6f1f3
VS		 940 "PLL[%d] not attached to this transcoder %c: %08x\n",
941 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
92b27b08
CW		 942 cur_state = !!(val >> (4*crtc->pipe + 3));
943 WARN(cur_state != state,
4bb6f1f3 944 "PLL[%d] not %s on this transcoder %c: %08x\n",
92b27b08
CW		 945 pll->pll_reg == _PCH_DPLL_B,
946 state_string(state),
4bb6f1f3 947 pipe_name(crtc->pipe),
92b27b08
CW		 948 val);
949 }
d3ccbe86 950 }
040484af 951}
92b27b08
CW		 952#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
953#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 954
955static void assert_fdi_tx(struct drm_i915_private *dev_priv,
956 enum pipe pipe, bool state)
957{
958 int reg;
959 u32 val;
960 bool cur_state;
ad80a810
PZ		 961 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
962 pipe);
040484af 963
affa9354
PZ		 964 if (HAS_DDI(dev_priv->dev)) {
965 /* DDI does not have a specific FDI_TX register */
ad80a810 966 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 967 val = I915_READ(reg);
ad80a810 968 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 969 } else {
970 reg = FDI_TX_CTL(pipe);
971 val = I915_READ(reg);
972 cur_state = !!(val & FDI_TX_ENABLE);
973 }
040484af
JB		 974 WARN(cur_state != state,
975 "FDI TX state assertion failure (expected %s, current %s)\n",
976 state_string(state), state_string(cur_state));
977}
978#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
979#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
980
981static void assert_fdi_rx(struct drm_i915_private *dev_priv,
982 enum pipe pipe, bool state)
983{
984 int reg;
985 u32 val;
986 bool cur_state;
987
d63fa0dc
PZ		 988 reg = FDI_RX_CTL(pipe);
989 val = I915_READ(reg);
990 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 991 WARN(cur_state != state,
992 "FDI RX state assertion failure (expected %s, current %s)\n",
993 state_string(state), state_string(cur_state));
994}
995#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
996#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
997
998static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
999 enum pipe pipe)
1000{
1001 int reg;
1002 u32 val;
1003
1004 /* ILK FDI PLL is always enabled */
1005 if (dev_priv->info->gen == 5)
1006 return;
1007
bf507ef7 1008 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1009 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1010 return;
1011
040484af
JB		 1012 reg = FDI_TX_CTL(pipe);
1013 val = I915_READ(reg);
1014 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1015}
1016
1017static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1018 enum pipe pipe)
1019{
1020 int reg;
1021 u32 val;
1022
1023 reg = FDI_RX_CTL(pipe);
1024 val = I915_READ(reg);
1025 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1026}
1027
ea0760cf
JB		 1028static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1029 enum pipe pipe)
1030{
1031 int pp_reg, lvds_reg;
1032 u32 val;
1033 enum pipe panel_pipe = PIPE_A;
0de3b485 1034 bool locked = true;
ea0760cf
JB		 1035
1036 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1037 pp_reg = PCH_PP_CONTROL;
1038 lvds_reg = PCH_LVDS;
1039 } else {
1040 pp_reg = PP_CONTROL;
1041 lvds_reg = LVDS;
1042 }
1043
1044 val = I915_READ(pp_reg);
1045 if (!(val & PANEL_POWER_ON) ||
1046 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1047 locked = false;
1048
1049 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1050 panel_pipe = PIPE_B;
1051
1052 WARN(panel_pipe == pipe && locked,
1053 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1054 pipe_name(pipe));
ea0760cf
JB		 1055}
1056
b840d907
JB		 1057void assert_pipe(struct drm_i915_private *dev_priv,
1058 enum pipe pipe, bool state)
b24e7179
JB		 1059{
1060 int reg;
1061 u32 val;
63d7bbe9 1062 bool cur_state;
702e7a56
PZ		 1063 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1064 pipe);
b24e7179 1065
8e636784
DV		 1066 /* if we need the pipe A quirk it must be always on */
1067 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1068 state = true;
1069
b97186f0
PZ		 1070 if (!intel_display_power_enabled(dev_priv->dev,
1071 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1072 cur_state = false;
1073 } else {
1074 reg = PIPECONF(cpu_transcoder);
1075 val = I915_READ(reg);
1076 cur_state = !!(val & PIPECONF_ENABLE);
1077 }
1078
63d7bbe9
JB		 1079 WARN(cur_state != state,
1080 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1081 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1082}
1083
931872fc
CW		 1084static void assert_plane(struct drm_i915_private *dev_priv,
1085 enum plane plane, bool state)
b24e7179
JB		 1086{
1087 int reg;
1088 u32 val;
931872fc 1089 bool cur_state;
b24e7179
JB		 1090
1091 reg = DSPCNTR(plane);
1092 val = I915_READ(reg);
931872fc
CW		 1093 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1094 WARN(cur_state != state,
1095 "plane %c assertion failure (expected %s, current %s)\n",
1096 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1097}
1098
931872fc
CW		 1099#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1100#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1101
b24e7179
JB		 1102static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1103 enum pipe pipe)
1104{
1105 int reg, i;
1106 u32 val;
1107 int cur_pipe;
1108
19ec1358 1109 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1110 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1111 reg = DSPCNTR(pipe);
1112 val = I915_READ(reg);
1113 WARN((val & DISPLAY_PLANE_ENABLE),
1114 "plane %c assertion failure, should be disabled but not\n",
1115 plane_name(pipe));
19ec1358 1116 return;
28c05794 1117 }
19ec1358 1118
b24e7179
JB		 1119 /* Need to check both planes against the pipe */
1120 for (i = 0; i < 2; i++) {
1121 reg = DSPCNTR(i);
1122 val = I915_READ(reg);
1123 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1124 DISPPLANE_SEL_PIPE_SHIFT;
1125 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1126 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1127 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1128 }
1129}
1130
19332d7a
JB		 1131static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1132 enum pipe pipe)
1133{
1134 int reg, i;
1135 u32 val;
1136
1137 if (!IS_VALLEYVIEW(dev_priv->dev))
1138 return;
1139
1140 /* Need to check both planes against the pipe */
1141 for (i = 0; i < dev_priv->num_plane; i++) {
1142 reg = SPCNTR(pipe, i);
1143 val = I915_READ(reg);
1144 WARN((val & SP_ENABLE),
06da8da2
VS		 1145 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1146 sprite_name(pipe, i), pipe_name(pipe));
19332d7a
JB		 1147 }
1148}
1149
92f2584a
JB		 1150static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1151{
1152 u32 val;
1153 bool enabled;
1154
9d82aa17
ED		 1155 if (HAS_PCH_LPT(dev_priv->dev)) {
1156 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1157 return;
1158 }
1159
92f2584a
JB		 1160 val = I915_READ(PCH_DREF_CONTROL);
1161 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1162 DREF_SUPERSPREAD_SOURCE_MASK));
1163 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1164}
1165
ab9412ba
DV		 1166static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1167 enum pipe pipe)
92f2584a
JB		 1168{
1169 int reg;
1170 u32 val;
1171 bool enabled;
1172
ab9412ba 1173 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1174 val = I915_READ(reg);
1175 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1176 WARN(enabled,
1177 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1178 pipe_name(pipe));
92f2584a
JB		 1179}
1180
4e634389
KP		 1181static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1182 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1183{
1184 if ((val & DP_PORT_EN) == 0)
1185 return false;
1186
1187 if (HAS_PCH_CPT(dev_priv->dev)) {
1188 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1189 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1190 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1191 return false;
1192 } else {
1193 if ((val & DP_PIPE_MASK) != (pipe << 30))
1194 return false;
1195 }
1196 return true;
1197}
1198
1519b995
KP		 1199static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1200 enum pipe pipe, u32 val)
1201{
dc0fa718 1202 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1203 return false;
1204
1205 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1206 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1207 return false;
1208 } else {
dc0fa718 1209 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1210 return false;
1211 }
1212 return true;
1213}
1214
1215static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1216 enum pipe pipe, u32 val)
1217{
1218 if ((val & LVDS_PORT_EN) == 0)
1219 return false;
1220
1221 if (HAS_PCH_CPT(dev_priv->dev)) {
1222 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1223 return false;
1224 } else {
1225 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1226 return false;
1227 }
1228 return true;
1229}
1230
1231static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1232 enum pipe pipe, u32 val)
1233{
1234 if ((val & ADPA_DAC_ENABLE) == 0)
1235 return false;
1236 if (HAS_PCH_CPT(dev_priv->dev)) {
1237 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1238 return false;
1239 } else {
1240 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1241 return false;
1242 }
1243 return true;
1244}
1245
291906f1 1246static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1247 enum pipe pipe, int reg, u32 port_sel)
291906f1 1248{
47a05eca 1249 u32 val = I915_READ(reg);
4e634389 1250 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1251 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1252 reg, pipe_name(pipe));
de9a35ab 1253
75c5da27
DV		 1254 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1255 && (val & DP_PIPEB_SELECT),
de9a35ab 1256 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1257}
1258
1259static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1260 enum pipe pipe, int reg)
1261{
47a05eca 1262 u32 val = I915_READ(reg);
b70ad586 1263 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1264 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1265 reg, pipe_name(pipe));
de9a35ab 1266
dc0fa718 1267 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1268 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1269 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1270}
1271
1272static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1273 enum pipe pipe)
1274{
1275 int reg;
1276 u32 val;
291906f1 1277
f0575e92
KP		 1278 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1279 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1280 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1281
1282 reg = PCH_ADPA;
1283 val = I915_READ(reg);
b70ad586 1284 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1285 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1286 pipe_name(pipe));
291906f1
JB		 1287
1288 reg = PCH_LVDS;
1289 val = I915_READ(reg);
b70ad586 1290 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1291 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1292 pipe_name(pipe));
291906f1 1293
e2debe91
PZ		 1294 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1295 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1296 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1297}
1298
63d7bbe9
JB		 1299/**
1300 * intel_enable_pll - enable a PLL
1301 * @dev_priv: i915 private structure
1302 * @pipe: pipe PLL to enable
1303 *
1304 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1305 * make sure the PLL reg is writable first though, since the panel write
1306 * protect mechanism may be enabled.
1307 *
1308 * Note! This is for pre-ILK only.
7434a255
TR		 1309 *
1310 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1311 */
1312static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1313{
1314 int reg;
1315 u32 val;
1316
58c6eaa2
DV		 1317 assert_pipe_disabled(dev_priv, pipe);
1318
63d7bbe9 1319 /* No really, not for ILK+ */
a0c4da24 1320 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1321
1322 /* PLL is protected by panel, make sure we can write it */
1323 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1324 assert_panel_unlocked(dev_priv, pipe);
1325
1326 reg = DPLL(pipe);
1327 val = I915_READ(reg);
1328 val |= DPLL_VCO_ENABLE;
1329
1330 /* We do this three times for luck */
1331 I915_WRITE(reg, val);
1332 POSTING_READ(reg);
1333 udelay(150); /* wait for warmup */
1334 I915_WRITE(reg, val);
1335 POSTING_READ(reg);
1336 udelay(150); /* wait for warmup */
1337 I915_WRITE(reg, val);
1338 POSTING_READ(reg);
1339 udelay(150); /* wait for warmup */
1340}
1341
1342/**
1343 * intel_disable_pll - disable a PLL
1344 * @dev_priv: i915 private structure
1345 * @pipe: pipe PLL to disable
1346 *
1347 * Disable the PLL for @pipe, making sure the pipe is off first.
1348 *
1349 * Note! This is for pre-ILK only.
1350 */
1351static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1352{
1353 int reg;
1354 u32 val;
1355
1356 /* Don't disable pipe A or pipe A PLLs if needed */
1357 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1358 return;
1359
1360 /* Make sure the pipe isn't still relying on us */
1361 assert_pipe_disabled(dev_priv, pipe);
1362
1363 reg = DPLL(pipe);
1364 val = I915_READ(reg);
1365 val &= ~DPLL_VCO_ENABLE;
1366 I915_WRITE(reg, val);
1367 POSTING_READ(reg);
1368}
1369
89b667f8
JB		 1370void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1371{
1372 u32 port_mask;
1373
1374 if (!port)
1375 port_mask = DPLL_PORTB_READY_MASK;
1376 else
1377 port_mask = DPLL_PORTC_READY_MASK;
1378
1379 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1380 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1381 'B' + port, I915_READ(DPLL(0)));
1382}
1383
92f2584a 1384/**
b6b4e185 1385 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1386 * @dev_priv: i915 private structure
1387 * @pipe: pipe PLL to enable
1388 *
1389 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1390 * drives the transcoder clock.
1391 */
b6b4e185 1392static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1393{
ee7b9f93 1394 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1395 struct intel_pch_pll *pll;
92f2584a
JB		 1396 int reg;
1397 u32 val;
1398
48da64a8 1399 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1400 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1401 pll = intel_crtc->pch_pll;
1402 if (pll == NULL)
1403 return;
1404
1405 if (WARN_ON(pll->refcount == 0))
1406 return;
ee7b9f93
JB		 1407
1408 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1409 pll->pll_reg, pll->active, pll->on,
1410 intel_crtc->base.base.id);
92f2584a
JB		 1411
1412 /* PCH refclock must be enabled first */
1413 assert_pch_refclk_enabled(dev_priv);
1414
ee7b9f93 1415 if (pll->active++ && pll->on) {
92b27b08 1416 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1417 return;
1418 }
1419
1420 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1421
1422 reg = pll->pll_reg;
92f2584a
JB		 1423 val = I915_READ(reg);
1424 val |= DPLL_VCO_ENABLE;
1425 I915_WRITE(reg, val);
1426 POSTING_READ(reg);
1427 udelay(200);
ee7b9f93
JB		 1428
1429 pll->on = true;
92f2584a
JB		 1430}
1431
ee7b9f93 1432static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1433{
ee7b9f93
JB		 1434 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1435 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1436 int reg;
ee7b9f93 1437 u32 val;
4c609cb8 1438
92f2584a
JB		 1439 /* PCH only available on ILK+ */
1440 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1441 if (pll == NULL)
1442 return;
92f2584a 1443
48da64a8
CW		 1444 if (WARN_ON(pll->refcount == 0))
1445 return;
7a419866 1446
ee7b9f93
JB		 1447 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1448 pll->pll_reg, pll->active, pll->on,
1449 intel_crtc->base.base.id);
7a419866 1450
48da64a8 1451 if (WARN_ON(pll->active == 0)) {
92b27b08 1452 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1453 return;
1454 }
1455
ee7b9f93 1456 if (--pll->active) {
92b27b08 1457 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1458 return;
ee7b9f93
JB		 1459 }
1460
1461 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1462
1463 /* Make sure transcoder isn't still depending on us */
ab9412ba 1464 assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1465
ee7b9f93 1466 reg = pll->pll_reg;
92f2584a
JB		 1467 val = I915_READ(reg);
1468 val &= ~DPLL_VCO_ENABLE;
1469 I915_WRITE(reg, val);
1470 POSTING_READ(reg);
1471 udelay(200);
ee7b9f93
JB		 1472
1473 pll->on = false;
92f2584a
JB		 1474}
1475
b8a4f404
PZ		 1476static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1477 enum pipe pipe)
040484af 1478{
23670b32 1479 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1480 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1481 uint32_t reg, val, pipeconf_val;
040484af
JB		 1482
1483 /* PCH only available on ILK+ */
1484 BUG_ON(dev_priv->info->gen < 5);
1485
1486 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1487 assert_pch_pll_enabled(dev_priv,
1488 to_intel_crtc(crtc)->pch_pll,
1489 to_intel_crtc(crtc));
040484af
JB		 1490
1491 /* FDI must be feeding us bits for PCH ports */
1492 assert_fdi_tx_enabled(dev_priv, pipe);
1493 assert_fdi_rx_enabled(dev_priv, pipe);
1494
23670b32
DV		 1495 if (HAS_PCH_CPT(dev)) {
1496 /* Workaround: Set the timing override bit before enabling the
1497 * pch transcoder. */
1498 reg = TRANS_CHICKEN2(pipe);
1499 val = I915_READ(reg);
1500 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1501 I915_WRITE(reg, val);
59c859d6 1502 }
23670b32 1503
ab9412ba 1504 reg = PCH_TRANSCONF(pipe);
040484af 1505 val = I915_READ(reg);
5f7f726d 1506 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1507
1508 if (HAS_PCH_IBX(dev_priv->dev)) {
1509 /*
1510 * make the BPC in transcoder be consistent with
1511 * that in pipeconf reg.
1512 */
dfd07d72
DV		 1513 val &= ~PIPECONF_BPC_MASK;
1514 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1515 }
5f7f726d
PZ		 1516
1517 val &= ~TRANS_INTERLACE_MASK;
1518 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1519 if (HAS_PCH_IBX(dev_priv->dev) &&
1520 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1521 val |= TRANS_LEGACY_INTERLACED_ILK;
1522 else
1523 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1524 else
1525 val |= TRANS_PROGRESSIVE;
1526
040484af
JB		 1527 I915_WRITE(reg, val | TRANS_ENABLE);
1528 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1529 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1530}
1531
8fb033d7 1532static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1533 enum transcoder cpu_transcoder)
040484af 1534{
8fb033d7 1535 u32 val, pipeconf_val;
8fb033d7
PZ		 1536
1537 /* PCH only available on ILK+ */
1538 BUG_ON(dev_priv->info->gen < 5);
1539
8fb033d7 1540 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1541 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1542 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1543
223a6fdf
PZ		 1544 /* Workaround: set timing override bit. */
1545 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1546 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1547 I915_WRITE(_TRANSA_CHICKEN2, val);
1548
25f3ef11 1549 val = TRANS_ENABLE;
937bb610 1550 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1551
9a76b1c6
PZ		 1552 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1553 PIPECONF_INTERLACED_ILK)
a35f2679 1554 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1555 else
1556 val |= TRANS_PROGRESSIVE;
1557
ab9412ba
DV		 1558 I915_WRITE(LPT_TRANSCONF, val);
1559 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1560 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1561}
1562
b8a4f404
PZ		 1563static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1564 enum pipe pipe)
040484af 1565{
23670b32
DV		 1566 struct drm_device *dev = dev_priv->dev;
1567 uint32_t reg, val;
040484af
JB		 1568
1569 /* FDI relies on the transcoder */
1570 assert_fdi_tx_disabled(dev_priv, pipe);
1571 assert_fdi_rx_disabled(dev_priv, pipe);
1572
291906f1
JB		 1573 /* Ports must be off as well */
1574 assert_pch_ports_disabled(dev_priv, pipe);
1575
ab9412ba 1576 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1577 val = I915_READ(reg);
1578 val &= ~TRANS_ENABLE;
1579 I915_WRITE(reg, val);
1580 /* wait for PCH transcoder off, transcoder state */
1581 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1582 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1583
1584 if (!HAS_PCH_IBX(dev)) {
1585 /* Workaround: Clear the timing override chicken bit again. */
1586 reg = TRANS_CHICKEN2(pipe);
1587 val = I915_READ(reg);
1588 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1589 I915_WRITE(reg, val);
1590 }
040484af
JB		 1591}
1592
ab4d966c 1593static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1594{
8fb033d7
PZ		 1595 u32 val;
1596
ab9412ba 1597 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1598 val &= ~TRANS_ENABLE;
ab9412ba 1599 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1600 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1601 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1602 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1603
1604 /* Workaround: clear timing override bit. */
1605 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1606 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1607 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1608}
1609
b24e7179 1610/**
309cfea8 1611 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1612 * @dev_priv: i915 private structure
1613 * @pipe: pipe to enable
040484af 1614 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1615 *
1616 * Enable @pipe, making sure that various hardware specific requirements
1617 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1618 *
1619 * @pipe should be %PIPE_A or %PIPE_B.
1620 *
1621 * Will wait until the pipe is actually running (i.e. first vblank) before
1622 * returning.
1623 */
040484af
JB		 1624static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1625 bool pch_port)
b24e7179 1626{
702e7a56
PZ		 1627 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1628 pipe);
1a240d4d 1629 enum pipe pch_transcoder;
b24e7179
JB		 1630 int reg;
1631 u32 val;
1632
58c6eaa2
DV		 1633 assert_planes_disabled(dev_priv, pipe);
1634 assert_sprites_disabled(dev_priv, pipe);
1635
681e5811 1636 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1637 pch_transcoder = TRANSCODER_A;
1638 else
1639 pch_transcoder = pipe;
1640
b24e7179
JB		 1641 /*
1642 * A pipe without a PLL won't actually be able to drive bits from
1643 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1644 * need the check.
1645 */
1646 if (!HAS_PCH_SPLIT(dev_priv->dev))
1647 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1648 else {
1649 if (pch_port) {
1650 /* if driving the PCH, we need FDI enabled */
cc391bbb 1651 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1652 assert_fdi_tx_pll_enabled(dev_priv,
1653 (enum pipe) cpu_transcoder);
040484af
JB		 1654 }
1655 /* FIXME: assert CPU port conditions for SNB+ */
1656 }
b24e7179 1657
702e7a56 1658 reg = PIPECONF(cpu_transcoder);
b24e7179 1659 val = I915_READ(reg);
00d70b15
CW		 1660 if (val & PIPECONF_ENABLE)
1661 return;
1662
1663 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1664 intel_wait_for_vblank(dev_priv->dev, pipe);
1665}
1666
1667/**
309cfea8 1668 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1669 * @dev_priv: i915 private structure
1670 * @pipe: pipe to disable
1671 *
1672 * Disable @pipe, making sure that various hardware specific requirements
1673 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1674 *
1675 * @pipe should be %PIPE_A or %PIPE_B.
1676 *
1677 * Will wait until the pipe has shut down before returning.
1678 */
1679static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1680 enum pipe pipe)
1681{
702e7a56
PZ		 1682 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1683 pipe);
b24e7179
JB		 1684 int reg;
1685 u32 val;
1686
1687 /*
1688 * Make sure planes won't keep trying to pump pixels to us,
1689 * or we might hang the display.
1690 */
1691 assert_planes_disabled(dev_priv, pipe);
19332d7a 1692 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1693
1694 /* Don't disable pipe A or pipe A PLLs if needed */
1695 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1696 return;
1697
702e7a56 1698 reg = PIPECONF(cpu_transcoder);
b24e7179 1699 val = I915_READ(reg);
00d70b15
CW		 1700 if ((val & PIPECONF_ENABLE) == 0)
1701 return;
1702
1703 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1704 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1705}
1706
d74362c9
KP		 1707/*
1708 * Plane regs are double buffered, going from enabled->disabled needs a
1709 * trigger in order to latch. The display address reg provides this.
1710 */
6f1d69b0 1711void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1712 enum plane plane)
1713{
14f86147
DL		 1714 if (dev_priv->info->gen >= 4)
1715 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1716 else
1717 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1718}
1719
b24e7179
JB		 1720/**
1721 * intel_enable_plane - enable a display plane on a given pipe
1722 * @dev_priv: i915 private structure
1723 * @plane: plane to enable
1724 * @pipe: pipe being fed
1725 *
1726 * Enable @plane on @pipe, making sure that @pipe is running first.
1727 */
1728static void intel_enable_plane(struct drm_i915_private *dev_priv,
1729 enum plane plane, enum pipe pipe)
1730{
1731 int reg;
1732 u32 val;
1733
1734 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1735 assert_pipe_enabled(dev_priv, pipe);
1736
1737 reg = DSPCNTR(plane);
1738 val = I915_READ(reg);
00d70b15
CW		 1739 if (val & DISPLAY_PLANE_ENABLE)
1740 return;
1741
1742 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1743 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1744 intel_wait_for_vblank(dev_priv->dev, pipe);
1745}
1746
b24e7179
JB		 1747/**
1748 * intel_disable_plane - disable a display plane
1749 * @dev_priv: i915 private structure
1750 * @plane: plane to disable
1751 * @pipe: pipe consuming the data
1752 *
1753 * Disable @plane; should be an independent operation.
1754 */
1755static void intel_disable_plane(struct drm_i915_private *dev_priv,
1756 enum plane plane, enum pipe pipe)
1757{
1758 int reg;
1759 u32 val;
1760
1761 reg = DSPCNTR(plane);
1762 val = I915_READ(reg);
00d70b15
CW		 1763 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1764 return;
1765
1766 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1767 intel_flush_display_plane(dev_priv, plane);
1768 intel_wait_for_vblank(dev_priv->dev, pipe);
1769}
1770
693db184
CW		 1771static bool need_vtd_wa(struct drm_device *dev)
1772{
1773#ifdef CONFIG_INTEL_IOMMU
1774 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1775 return true;
1776#endif
1777 return false;
1778}
1779
127bd2ac 1780int
48b956c5 1781intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1782 struct drm_i915_gem_object *obj,
919926ae 1783 struct intel_ring_buffer *pipelined)
6b95a207 1784{
ce453d81 1785 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1786 u32 alignment;
1787 int ret;
1788
05394f39 1789 switch (obj->tiling_mode) {
6b95a207 1790 case I915_TILING_NONE:
534843da
CW		 1791 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1792 alignment = 128 * 1024;
a6c45cf0 1793 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1794 alignment = 4 * 1024;
1795 else
1796 alignment = 64 * 1024;
6b95a207
KH		 1797 break;
1798 case I915_TILING_X:
1799 /* pin() will align the object as required by fence */
1800 alignment = 0;
1801 break;
1802 case I915_TILING_Y:
8bb6e959
DV		 1803 /* Despite that we check this in framebuffer_init userspace can
1804 * screw us over and change the tiling after the fact. Only
1805 * pinned buffers can't change their tiling. */
1806 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1807 return -EINVAL;
1808 default:
1809 BUG();
1810 }
1811
693db184
CW		 1812 /* Note that the w/a also requires 64 PTE of padding following the
1813 * bo. We currently fill all unused PTE with the shadow page and so
1814 * we should always have valid PTE following the scanout preventing
1815 * the VT-d warning.
1816 */
1817 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1818 alignment = 256 * 1024;
1819
ce453d81 1820 dev_priv->mm.interruptible = false;
2da3b9b9 1821 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1822 if (ret)
ce453d81 1823 goto err_interruptible;
6b95a207
KH		 1824
1825 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1826 * fence, whereas 965+ only requires a fence if using
1827 * framebuffer compression. For simplicity, we always install
1828 * a fence as the cost is not that onerous.
1829 */
06d98131 1830 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1831 if (ret)
1832 goto err_unpin;
1690e1eb 1833
9a5a53b3 1834 i915_gem_object_pin_fence(obj);
6b95a207 1835
ce453d81 1836 dev_priv->mm.interruptible = true;
6b95a207 1837 return 0;
48b956c5
CW		 1838
1839err_unpin:
1840 i915_gem_object_unpin(obj);
ce453d81
CW		 1841err_interruptible:
1842 dev_priv->mm.interruptible = true;
48b956c5 1843 return ret;
6b95a207
KH		 1844}
1845
1690e1eb
CW		 1846void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1847{
1848 i915_gem_object_unpin_fence(obj);
1849 i915_gem_object_unpin(obj);
1850}
1851
c2c75131
DV		 1852/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1853 * is assumed to be a power-of-two. */
bc752862
CW		 1854unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1855 unsigned int tiling_mode,
1856 unsigned int cpp,
1857 unsigned int pitch)
c2c75131 1858{
bc752862
CW		 1859 if (tiling_mode != I915_TILING_NONE) {
1860 unsigned int tile_rows, tiles;
c2c75131 1861
bc752862
CW		 1862 tile_rows = *y / 8;
1863 *y %= 8;
c2c75131 1864
bc752862
CW		 1865 tiles = *x / (512/cpp);
1866 *x %= 512/cpp;
1867
1868 return tile_rows * pitch * 8 + tiles * 4096;
1869 } else {
1870 unsigned int offset;
1871
1872 offset = *y * pitch + *x * cpp;
1873 *y = 0;
1874 *x = (offset & 4095) / cpp;
1875 return offset & -4096;
1876 }
c2c75131
DV		 1877}
1878
17638cd6
JB		 1879static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1880 int x, int y)
81255565
JB		 1881{
1882 struct drm_device *dev = crtc->dev;
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1885 struct intel_framebuffer *intel_fb;
05394f39 1886 struct drm_i915_gem_object *obj;
81255565 1887 int plane = intel_crtc->plane;
e506a0c6 1888 unsigned long linear_offset;
81255565 1889 u32 dspcntr;
5eddb70b 1890 u32 reg;
81255565
JB		 1891
1892 switch (plane) {
1893 case 0:
1894 case 1:
1895 break;
1896 default:
84f44ce7 1897 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1898 return -EINVAL;
1899 }
1900
1901 intel_fb = to_intel_framebuffer(fb);
1902 obj = intel_fb->obj;
81255565 1903
5eddb70b
CW		 1904 reg = DSPCNTR(plane);
1905 dspcntr = I915_READ(reg);
81255565
JB		 1906 /* Mask out pixel format bits in case we change it */
1907 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1908 switch (fb->pixel_format) {
1909 case DRM_FORMAT_C8:
81255565
JB		 1910 dspcntr |= DISPPLANE_8BPP;
1911 break;
57779d06
VS		 1912 case DRM_FORMAT_XRGB1555:
1913 case DRM_FORMAT_ARGB1555:
1914 dspcntr |= DISPPLANE_BGRX555;
81255565 1915 break;
57779d06
VS		 1916 case DRM_FORMAT_RGB565:
1917 dspcntr |= DISPPLANE_BGRX565;
1918 break;
1919 case DRM_FORMAT_XRGB8888:
1920 case DRM_FORMAT_ARGB8888:
1921 dspcntr |= DISPPLANE_BGRX888;
1922 break;
1923 case DRM_FORMAT_XBGR8888:
1924 case DRM_FORMAT_ABGR8888:
1925 dspcntr |= DISPPLANE_RGBX888;
1926 break;
1927 case DRM_FORMAT_XRGB2101010:
1928 case DRM_FORMAT_ARGB2101010:
1929 dspcntr |= DISPPLANE_BGRX101010;
1930 break;
1931 case DRM_FORMAT_XBGR2101010:
1932 case DRM_FORMAT_ABGR2101010:
1933 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1934 break;
1935 default:
baba133a 1936 BUG();
81255565 1937 }
57779d06 1938
a6c45cf0 1939 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1940 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1941 dspcntr |= DISPPLANE_TILED;
1942 else
1943 dspcntr &= ~DISPPLANE_TILED;
1944 }
1945
5eddb70b 1946 I915_WRITE(reg, dspcntr);
81255565 1947
e506a0c6 1948 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1949
c2c75131
DV		 1950 if (INTEL_INFO(dev)->gen >= 4) {
1951 intel_crtc->dspaddr_offset =
bc752862
CW		 1952 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1953 fb->bits_per_pixel / 8,
1954 fb->pitches[0]);
c2c75131
DV		 1955 linear_offset -= intel_crtc->dspaddr_offset;
1956 } else {
e506a0c6 1957 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 1958 }
e506a0c6
DV		 1959
1960 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1961 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 1962 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1963 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 1964 I915_MODIFY_DISPBASE(DSPSURF(plane),
1965 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 1966 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 1967 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 1968 } else
e506a0c6 1969 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 1970 POSTING_READ(reg);
81255565 1971
17638cd6
JB		 1972 return 0;
1973}
1974
1975static int ironlake_update_plane(struct drm_crtc *crtc,
1976 struct drm_framebuffer *fb, int x, int y)
1977{
1978 struct drm_device *dev = crtc->dev;
1979 struct drm_i915_private *dev_priv = dev->dev_private;
1980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1981 struct intel_framebuffer *intel_fb;
1982 struct drm_i915_gem_object *obj;
1983 int plane = intel_crtc->plane;
e506a0c6 1984 unsigned long linear_offset;
17638cd6
JB		 1985 u32 dspcntr;
1986 u32 reg;
1987
1988 switch (plane) {
1989 case 0:
1990 case 1:
27f8227b 1991 case 2:
17638cd6
JB		 1992 break;
1993 default:
84f44ce7 1994 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 1995 return -EINVAL;
1996 }
1997
1998 intel_fb = to_intel_framebuffer(fb);
1999 obj = intel_fb->obj;
2000
2001 reg = DSPCNTR(plane);
2002 dspcntr = I915_READ(reg);
2003 /* Mask out pixel format bits in case we change it */
2004 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2005 switch (fb->pixel_format) {
2006 case DRM_FORMAT_C8:
17638cd6
JB		 2007 dspcntr |= DISPPLANE_8BPP;
2008 break;
57779d06
VS		 2009 case DRM_FORMAT_RGB565:
2010 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2011 break;
57779d06
VS		 2012 case DRM_FORMAT_XRGB8888:
2013 case DRM_FORMAT_ARGB8888:
2014 dspcntr |= DISPPLANE_BGRX888;
2015 break;
2016 case DRM_FORMAT_XBGR8888:
2017 case DRM_FORMAT_ABGR8888:
2018 dspcntr |= DISPPLANE_RGBX888;
2019 break;
2020 case DRM_FORMAT_XRGB2101010:
2021 case DRM_FORMAT_ARGB2101010:
2022 dspcntr |= DISPPLANE_BGRX101010;
2023 break;
2024 case DRM_FORMAT_XBGR2101010:
2025 case DRM_FORMAT_ABGR2101010:
2026 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2027 break;
2028 default:
baba133a 2029 BUG();
17638cd6
JB		 2030 }
2031
2032 if (obj->tiling_mode != I915_TILING_NONE)
2033 dspcntr |= DISPPLANE_TILED;
2034 else
2035 dspcntr &= ~DISPPLANE_TILED;
2036
2037 /* must disable */
2038 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2039
2040 I915_WRITE(reg, dspcntr);
2041
e506a0c6 2042 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2043 intel_crtc->dspaddr_offset =
bc752862
CW		 2044 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2045 fb->bits_per_pixel / 8,
2046 fb->pitches[0]);
c2c75131 2047 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2048
e506a0c6
DV		 2049 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2050 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2051 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2052 I915_MODIFY_DISPBASE(DSPSURF(plane),
2053 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2054 if (IS_HASWELL(dev)) {
2055 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2056 } else {
2057 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2058 I915_WRITE(DSPLINOFF(plane), linear_offset);
2059 }
17638cd6
JB		 2060 POSTING_READ(reg);
2061
2062 return 0;
2063}
2064
2065/* Assume fb object is pinned & idle & fenced and just update base pointers */
2066static int
2067intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2068 int x, int y, enum mode_set_atomic state)
2069{
2070 struct drm_device *dev = crtc->dev;
2071 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2072
6b8e6ed0
CW		 2073 if (dev_priv->display.disable_fbc)
2074 dev_priv->display.disable_fbc(dev);
3dec0095 2075 intel_increase_pllclock(crtc);
81255565 2076
6b8e6ed0 2077 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2078}
2079
96a02917
VS		 2080void intel_display_handle_reset(struct drm_device *dev)
2081{
2082 struct drm_i915_private *dev_priv = dev->dev_private;
2083 struct drm_crtc *crtc;
2084
2085 /*
2086 * Flips in the rings have been nuked by the reset,
2087 * so complete all pending flips so that user space
2088 * will get its events and not get stuck.
2089 *
2090 * Also update the base address of all primary
2091 * planes to the the last fb to make sure we're
2092 * showing the correct fb after a reset.
2093 *
2094 * Need to make two loops over the crtcs so that we
2095 * don't try to grab a crtc mutex before the
2096 * pending_flip_queue really got woken up.
2097 */
2098
2099 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2100 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2101 enum plane plane = intel_crtc->plane;
2102
2103 intel_prepare_page_flip(dev, plane);
2104 intel_finish_page_flip_plane(dev, plane);
2105 }
2106
2107 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2109
2110 mutex_lock(&crtc->mutex);
2111 if (intel_crtc->active)
2112 dev_priv->display.update_plane(crtc, crtc->fb,
2113 crtc->x, crtc->y);
2114 mutex_unlock(&crtc->mutex);
2115 }
2116}
2117
14667a4b
CW		 2118static int
2119intel_finish_fb(struct drm_framebuffer *old_fb)
2120{
2121 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2122 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2123 bool was_interruptible = dev_priv->mm.interruptible;
2124 int ret;
2125
14667a4b
CW		 2126 /* Big Hammer, we also need to ensure that any pending
2127 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2128 * current scanout is retired before unpinning the old
2129 * framebuffer.
2130 *
2131 * This should only fail upon a hung GPU, in which case we
2132 * can safely continue.
2133 */
2134 dev_priv->mm.interruptible = false;
2135 ret = i915_gem_object_finish_gpu(obj);
2136 dev_priv->mm.interruptible = was_interruptible;
2137
2138 return ret;
2139}
2140
198598d0
VS		 2141static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2142{
2143 struct drm_device *dev = crtc->dev;
2144 struct drm_i915_master_private *master_priv;
2145 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2146
2147 if (!dev->primary->master)
2148 return;
2149
2150 master_priv = dev->primary->master->driver_priv;
2151 if (!master_priv->sarea_priv)
2152 return;
2153
2154 switch (intel_crtc->pipe) {
2155 case 0:
2156 master_priv->sarea_priv->pipeA_x = x;
2157 master_priv->sarea_priv->pipeA_y = y;
2158 break;
2159 case 1:
2160 master_priv->sarea_priv->pipeB_x = x;
2161 master_priv->sarea_priv->pipeB_y = y;
2162 break;
2163 default:
2164 break;
2165 }
2166}
2167
5c3b82e2 2168static int
3c4fdcfb 2169intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2170 struct drm_framebuffer *fb)
79e53945
JB		 2171{
2172 struct drm_device *dev = crtc->dev;
6b8e6ed0 2173 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2174 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2175 struct drm_framebuffer *old_fb;
5c3b82e2 2176 int ret;
79e53945
JB		 2177
2178 /* no fb bound */
94352cf9 2179 if (!fb) {
a5071c2f 2180 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2181 return 0;
2182 }
2183
7eb552ae 2184 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2185 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2186 plane_name(intel_crtc->plane),
2187 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2188 return -EINVAL;
79e53945
JB		 2189 }
2190
5c3b82e2 2191 mutex_lock(&dev->struct_mutex);
265db958 2192 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2193 to_intel_framebuffer(fb)->obj,
919926ae 2194 NULL);
5c3b82e2
CW		 2195 if (ret != 0) {
2196 mutex_unlock(&dev->struct_mutex);
a5071c2f 2197 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2198 return ret;
2199 }
79e53945 2200
94352cf9 2201 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2202 if (ret) {
94352cf9 2203 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2204 mutex_unlock(&dev->struct_mutex);
a5071c2f 2205 DRM_ERROR("failed to update base address\n");
4e6cfefc 2206 return ret;
79e53945 2207 }
3c4fdcfb 2208
94352cf9
DV		 2209 old_fb = crtc->fb;
2210 crtc->fb = fb;
6c4c86f5
DV		 2211 crtc->x = x;
2212 crtc->y = y;
94352cf9 2213
b7f1de28 2214 if (old_fb) {
d7697eea
DV		 2215 if (intel_crtc->active && old_fb != fb)
2216 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2217 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2218 }
652c393a 2219
6b8e6ed0 2220 intel_update_fbc(dev);
5c3b82e2 2221 mutex_unlock(&dev->struct_mutex);
79e53945 2222
198598d0 2223 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2224
2225 return 0;
79e53945
JB		 2226}
2227
5e84e1a4
ZW		 2228static void intel_fdi_normal_train(struct drm_crtc *crtc)
2229{
2230 struct drm_device *dev = crtc->dev;
2231 struct drm_i915_private *dev_priv = dev->dev_private;
2232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2233 int pipe = intel_crtc->pipe;
2234 u32 reg, temp;
2235
2236 /* enable normal train */
2237 reg = FDI_TX_CTL(pipe);
2238 temp = I915_READ(reg);
61e499bf 2239 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2240 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2241 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2242 } else {
2243 temp &= ~FDI_LINK_TRAIN_NONE;
2244 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2245 }
5e84e1a4
ZW		 2246 I915_WRITE(reg, temp);
2247
2248 reg = FDI_RX_CTL(pipe);
2249 temp = I915_READ(reg);
2250 if (HAS_PCH_CPT(dev)) {
2251 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2252 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2253 } else {
2254 temp &= ~FDI_LINK_TRAIN_NONE;
2255 temp |= FDI_LINK_TRAIN_NONE;
2256 }
2257 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2258
2259 /* wait one idle pattern time */
2260 POSTING_READ(reg);
2261 udelay(1000);
357555c0
JB		 2262
2263 /* IVB wants error correction enabled */
2264 if (IS_IVYBRIDGE(dev))
2265 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2266 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2267}
2268
1e833f40
DV		 2269static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2270{
2271 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2272}
2273
01a415fd
DV		 2274static void ivb_modeset_global_resources(struct drm_device *dev)
2275{
2276 struct drm_i915_private *dev_priv = dev->dev_private;
2277 struct intel_crtc *pipe_B_crtc =
2278 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2279 struct intel_crtc *pipe_C_crtc =
2280 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2281 uint32_t temp;
2282
1e833f40
DV		 2283 /*
2284 * When everything is off disable fdi C so that we could enable fdi B
2285 * with all lanes. Note that we don't care about enabled pipes without
2286 * an enabled pch encoder.
2287 */
2288 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2289 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2290 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2291 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2292
2293 temp = I915_READ(SOUTH_CHICKEN1);
2294 temp &= ~FDI_BC_BIFURCATION_SELECT;
2295 DRM_DEBUG_KMS("disabling fdi C rx\n");
2296 I915_WRITE(SOUTH_CHICKEN1, temp);
2297 }
2298}
2299
8db9d77b
ZW		 2300/* The FDI link training functions for ILK/Ibexpeak. */
2301static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2302{
2303 struct drm_device *dev = crtc->dev;
2304 struct drm_i915_private *dev_priv = dev->dev_private;
2305 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2306 int pipe = intel_crtc->pipe;
0fc932b8 2307 int plane = intel_crtc->plane;
5eddb70b 2308 u32 reg, temp, tries;
8db9d77b 2309
0fc932b8
JB		 2310 /* FDI needs bits from pipe & plane first */
2311 assert_pipe_enabled(dev_priv, pipe);
2312 assert_plane_enabled(dev_priv, plane);
2313
e1a44743
AJ		 2314 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2315 for train result */
5eddb70b
CW		 2316 reg = FDI_RX_IMR(pipe);
2317 temp = I915_READ(reg);
e1a44743
AJ		 2318 temp &= ~FDI_RX_SYMBOL_LOCK;
2319 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2320 I915_WRITE(reg, temp);
2321 I915_READ(reg);
e1a44743
AJ		 2322 udelay(150);
2323
8db9d77b 2324 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2325 reg = FDI_TX_CTL(pipe);
2326 temp = I915_READ(reg);
627eb5a3
DV		 2327 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2328 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2329 temp &= ~FDI_LINK_TRAIN_NONE;
2330 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2331 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2332
5eddb70b
CW		 2333 reg = FDI_RX_CTL(pipe);
2334 temp = I915_READ(reg);
8db9d77b
ZW		 2335 temp &= ~FDI_LINK_TRAIN_NONE;
2336 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2337 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2338
2339 POSTING_READ(reg);
8db9d77b
ZW		 2340 udelay(150);
2341
5b2adf89 2342 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2343 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2344 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2345 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2346
5eddb70b 2347 reg = FDI_RX_IIR(pipe);
e1a44743 2348 for (tries = 0; tries < 5; tries++) {
5eddb70b 2349 temp = I915_READ(reg);
8db9d77b
ZW		 2350 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2351
2352 if ((temp & FDI_RX_BIT_LOCK)) {
2353 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2354 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2355 break;
2356 }
8db9d77b 2357 }
e1a44743 2358 if (tries == 5)
5eddb70b 2359 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2360
2361 /* Train 2 */
5eddb70b
CW		 2362 reg = FDI_TX_CTL(pipe);
2363 temp = I915_READ(reg);
8db9d77b
ZW		 2364 temp &= ~FDI_LINK_TRAIN_NONE;
2365 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2366 I915_WRITE(reg, temp);
8db9d77b 2367
5eddb70b
CW		 2368 reg = FDI_RX_CTL(pipe);
2369 temp = I915_READ(reg);
8db9d77b
ZW		 2370 temp &= ~FDI_LINK_TRAIN_NONE;
2371 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2372 I915_WRITE(reg, temp);
8db9d77b 2373
5eddb70b
CW		 2374 POSTING_READ(reg);
2375 udelay(150);
8db9d77b 2376
5eddb70b 2377 reg = FDI_RX_IIR(pipe);
e1a44743 2378 for (tries = 0; tries < 5; tries++) {
5eddb70b 2379 temp = I915_READ(reg);
8db9d77b
ZW		 2380 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2381
2382 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2383 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2384 DRM_DEBUG_KMS("FDI train 2 done.\n");
2385 break;
2386 }
8db9d77b 2387 }
e1a44743 2388 if (tries == 5)
5eddb70b 2389 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2390
2391 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2392
8db9d77b
ZW		 2393}
2394
0206e353 2395static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2396 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2397 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2398 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2399 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2400};
2401
2402/* The FDI link training functions for SNB/Cougarpoint. */
2403static void gen6_fdi_link_train(struct drm_crtc *crtc)
2404{
2405 struct drm_device *dev = crtc->dev;
2406 struct drm_i915_private *dev_priv = dev->dev_private;
2407 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2408 int pipe = intel_crtc->pipe;
fa37d39e 2409 u32 reg, temp, i, retry;
8db9d77b 2410
e1a44743
AJ		 2411 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2412 for train result */
5eddb70b
CW		 2413 reg = FDI_RX_IMR(pipe);
2414 temp = I915_READ(reg);
e1a44743
AJ		 2415 temp &= ~FDI_RX_SYMBOL_LOCK;
2416 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2417 I915_WRITE(reg, temp);
2418
2419 POSTING_READ(reg);
e1a44743
AJ		 2420 udelay(150);
2421
8db9d77b 2422 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2423 reg = FDI_TX_CTL(pipe);
2424 temp = I915_READ(reg);
627eb5a3
DV		 2425 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2426 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2427 temp &= ~FDI_LINK_TRAIN_NONE;
2428 temp |= FDI_LINK_TRAIN_PATTERN_1;
2429 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2430 /* SNB-B */
2431 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2432 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2433
d74cf324
DV		 2434 I915_WRITE(FDI_RX_MISC(pipe),
2435 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2436
5eddb70b
CW		 2437 reg = FDI_RX_CTL(pipe);
2438 temp = I915_READ(reg);
8db9d77b
ZW		 2439 if (HAS_PCH_CPT(dev)) {
2440 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2441 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2442 } else {
2443 temp &= ~FDI_LINK_TRAIN_NONE;
2444 temp |= FDI_LINK_TRAIN_PATTERN_1;
2445 }
5eddb70b
CW		 2446 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2447
2448 POSTING_READ(reg);
8db9d77b
ZW		 2449 udelay(150);
2450
0206e353 2451 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2452 reg = FDI_TX_CTL(pipe);
2453 temp = I915_READ(reg);
8db9d77b
ZW		 2454 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2455 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2456 I915_WRITE(reg, temp);
2457
2458 POSTING_READ(reg);
8db9d77b
ZW		 2459 udelay(500);
2460
fa37d39e
SP		 2461 for (retry = 0; retry < 5; retry++) {
2462 reg = FDI_RX_IIR(pipe);
2463 temp = I915_READ(reg);
2464 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2465 if (temp & FDI_RX_BIT_LOCK) {
2466 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2467 DRM_DEBUG_KMS("FDI train 1 done.\n");
2468 break;
2469 }
2470 udelay(50);
8db9d77b 2471 }
fa37d39e
SP		 2472 if (retry < 5)
2473 break;
8db9d77b
ZW		 2474 }
2475 if (i == 4)
5eddb70b 2476 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2477
2478 /* Train 2 */
5eddb70b
CW		 2479 reg = FDI_TX_CTL(pipe);
2480 temp = I915_READ(reg);
8db9d77b
ZW		 2481 temp &= ~FDI_LINK_TRAIN_NONE;
2482 temp |= FDI_LINK_TRAIN_PATTERN_2;
2483 if (IS_GEN6(dev)) {
2484 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2485 /* SNB-B */
2486 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2487 }
5eddb70b 2488 I915_WRITE(reg, temp);
8db9d77b 2489
5eddb70b
CW		 2490 reg = FDI_RX_CTL(pipe);
2491 temp = I915_READ(reg);
8db9d77b
ZW		 2492 if (HAS_PCH_CPT(dev)) {
2493 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2494 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2495 } else {
2496 temp &= ~FDI_LINK_TRAIN_NONE;
2497 temp |= FDI_LINK_TRAIN_PATTERN_2;
2498 }
5eddb70b
CW		 2499 I915_WRITE(reg, temp);
2500
2501 POSTING_READ(reg);
8db9d77b
ZW		 2502 udelay(150);
2503
0206e353 2504 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2505 reg = FDI_TX_CTL(pipe);
2506 temp = I915_READ(reg);
8db9d77b
ZW		 2507 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2508 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2509 I915_WRITE(reg, temp);
2510
2511 POSTING_READ(reg);
8db9d77b
ZW		 2512 udelay(500);
2513
fa37d39e
SP		 2514 for (retry = 0; retry < 5; retry++) {
2515 reg = FDI_RX_IIR(pipe);
2516 temp = I915_READ(reg);
2517 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2518 if (temp & FDI_RX_SYMBOL_LOCK) {
2519 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2520 DRM_DEBUG_KMS("FDI train 2 done.\n");
2521 break;
2522 }
2523 udelay(50);
8db9d77b 2524 }
fa37d39e
SP		 2525 if (retry < 5)
2526 break;
8db9d77b
ZW		 2527 }
2528 if (i == 4)
5eddb70b 2529 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2530
2531 DRM_DEBUG_KMS("FDI train done.\n");
2532}
2533
357555c0
JB		 2534/* Manual link training for Ivy Bridge A0 parts */
2535static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2536{
2537 struct drm_device *dev = crtc->dev;
2538 struct drm_i915_private *dev_priv = dev->dev_private;
2539 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2540 int pipe = intel_crtc->pipe;
2541 u32 reg, temp, i;
2542
2543 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2544 for train result */
2545 reg = FDI_RX_IMR(pipe);
2546 temp = I915_READ(reg);
2547 temp &= ~FDI_RX_SYMBOL_LOCK;
2548 temp &= ~FDI_RX_BIT_LOCK;
2549 I915_WRITE(reg, temp);
2550
2551 POSTING_READ(reg);
2552 udelay(150);
2553
01a415fd
DV		 2554 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2555 I915_READ(FDI_RX_IIR(pipe)));
2556
357555c0
JB		 2557 /* enable CPU FDI TX and PCH FDI RX */
2558 reg = FDI_TX_CTL(pipe);
2559 temp = I915_READ(reg);
627eb5a3
DV		 2560 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2561 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2562 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2563 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2564 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2565 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2566 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2567 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2568
d74cf324
DV		 2569 I915_WRITE(FDI_RX_MISC(pipe),
2570 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2571
357555c0
JB		 2572 reg = FDI_RX_CTL(pipe);
2573 temp = I915_READ(reg);
2574 temp &= ~FDI_LINK_TRAIN_AUTO;
2575 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2576 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2577 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2578 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2579
2580 POSTING_READ(reg);
2581 udelay(150);
2582
0206e353 2583 for (i = 0; i < 4; i++) {
357555c0
JB		 2584 reg = FDI_TX_CTL(pipe);
2585 temp = I915_READ(reg);
2586 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2587 temp |= snb_b_fdi_train_param[i];
2588 I915_WRITE(reg, temp);
2589
2590 POSTING_READ(reg);
2591 udelay(500);
2592
2593 reg = FDI_RX_IIR(pipe);
2594 temp = I915_READ(reg);
2595 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2596
2597 if (temp & FDI_RX_BIT_LOCK ||
2598 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2599 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2600 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2601 break;
2602 }
2603 }
2604 if (i == 4)
2605 DRM_ERROR("FDI train 1 fail!\n");
2606
2607 /* Train 2 */
2608 reg = FDI_TX_CTL(pipe);
2609 temp = I915_READ(reg);
2610 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2611 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2612 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2613 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2614 I915_WRITE(reg, temp);
2615
2616 reg = FDI_RX_CTL(pipe);
2617 temp = I915_READ(reg);
2618 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2619 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2620 I915_WRITE(reg, temp);
2621
2622 POSTING_READ(reg);
2623 udelay(150);
2624
0206e353 2625 for (i = 0; i < 4; i++) {
357555c0
JB		 2626 reg = FDI_TX_CTL(pipe);
2627 temp = I915_READ(reg);
2628 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2629 temp |= snb_b_fdi_train_param[i];
2630 I915_WRITE(reg, temp);
2631
2632 POSTING_READ(reg);
2633 udelay(500);
2634
2635 reg = FDI_RX_IIR(pipe);
2636 temp = I915_READ(reg);
2637 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2638
2639 if (temp & FDI_RX_SYMBOL_LOCK) {
2640 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2641 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2642 break;
2643 }
2644 }
2645 if (i == 4)
2646 DRM_ERROR("FDI train 2 fail!\n");
2647
2648 DRM_DEBUG_KMS("FDI train done.\n");
2649}
2650
88cefb6c 2651static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2652{
88cefb6c 2653 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2654 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2655 int pipe = intel_crtc->pipe;
5eddb70b 2656 u32 reg, temp;
79e53945 2657
c64e311e 2658
c98e9dcf 2659 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2660 reg = FDI_RX_CTL(pipe);
2661 temp = I915_READ(reg);
627eb5a3
DV		 2662 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2663 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2664 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2665 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2666
2667 POSTING_READ(reg);
c98e9dcf
JB		 2668 udelay(200);
2669
2670 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2671 temp = I915_READ(reg);
2672 I915_WRITE(reg, temp | FDI_PCDCLK);
2673
2674 POSTING_READ(reg);
c98e9dcf
JB		 2675 udelay(200);
2676
20749730
PZ		 2677 /* Enable CPU FDI TX PLL, always on for Ironlake */
2678 reg = FDI_TX_CTL(pipe);
2679 temp = I915_READ(reg);
2680 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2681 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2682
20749730
PZ		 2683 POSTING_READ(reg);
2684 udelay(100);
6be4a607 2685 }
0e23b99d
JB		 2686}
2687
88cefb6c
DV		 2688static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2689{
2690 struct drm_device *dev = intel_crtc->base.dev;
2691 struct drm_i915_private *dev_priv = dev->dev_private;
2692 int pipe = intel_crtc->pipe;
2693 u32 reg, temp;
2694
2695 /* Switch from PCDclk to Rawclk */
2696 reg = FDI_RX_CTL(pipe);
2697 temp = I915_READ(reg);
2698 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2699
2700 /* Disable CPU FDI TX PLL */
2701 reg = FDI_TX_CTL(pipe);
2702 temp = I915_READ(reg);
2703 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2704
2705 POSTING_READ(reg);
2706 udelay(100);
2707
2708 reg = FDI_RX_CTL(pipe);
2709 temp = I915_READ(reg);
2710 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2711
2712 /* Wait for the clocks to turn off. */
2713 POSTING_READ(reg);
2714 udelay(100);
2715}
2716
0fc932b8
JB		 2717static void ironlake_fdi_disable(struct drm_crtc *crtc)
2718{
2719 struct drm_device *dev = crtc->dev;
2720 struct drm_i915_private *dev_priv = dev->dev_private;
2721 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2722 int pipe = intel_crtc->pipe;
2723 u32 reg, temp;
2724
2725 /* disable CPU FDI tx and PCH FDI rx */
2726 reg = FDI_TX_CTL(pipe);
2727 temp = I915_READ(reg);
2728 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2729 POSTING_READ(reg);
2730
2731 reg = FDI_RX_CTL(pipe);
2732 temp = I915_READ(reg);
2733 temp &= ~(0x7 << 16);
dfd07d72 2734 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2735 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2736
2737 POSTING_READ(reg);
2738 udelay(100);
2739
2740 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2741 if (HAS_PCH_IBX(dev)) {
2742 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2743 }
0fc932b8
JB		 2744
2745 /* still set train pattern 1 */
2746 reg = FDI_TX_CTL(pipe);
2747 temp = I915_READ(reg);
2748 temp &= ~FDI_LINK_TRAIN_NONE;
2749 temp |= FDI_LINK_TRAIN_PATTERN_1;
2750 I915_WRITE(reg, temp);
2751
2752 reg = FDI_RX_CTL(pipe);
2753 temp = I915_READ(reg);
2754 if (HAS_PCH_CPT(dev)) {
2755 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2756 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2757 } else {
2758 temp &= ~FDI_LINK_TRAIN_NONE;
2759 temp |= FDI_LINK_TRAIN_PATTERN_1;
2760 }
2761 /* BPC in FDI rx is consistent with that in PIPECONF */
2762 temp &= ~(0x07 << 16);
dfd07d72 2763 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2764 I915_WRITE(reg, temp);
2765
2766 POSTING_READ(reg);
2767 udelay(100);
2768}
2769
5bb61643
CW		 2770static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2771{
2772 struct drm_device *dev = crtc->dev;
2773 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2775 unsigned long flags;
2776 bool pending;
2777
10d83730
VS		 2778 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2779 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2780 return false;
2781
2782 spin_lock_irqsave(&dev->event_lock, flags);
2783 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2784 spin_unlock_irqrestore(&dev->event_lock, flags);
2785
2786 return pending;
2787}
2788
e6c3a2a6
CW		 2789static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2790{
0f91128d 2791 struct drm_device *dev = crtc->dev;
5bb61643 2792 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2793
2794 if (crtc->fb == NULL)
2795 return;
2796
2c10d571
DV		 2797 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2798
5bb61643
CW		 2799 wait_event(dev_priv->pending_flip_queue,
2800 !intel_crtc_has_pending_flip(crtc));
2801
0f91128d
CW		 2802 mutex_lock(&dev->struct_mutex);
2803 intel_finish_fb(crtc->fb);
2804 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2805}
2806
e615efe4
ED		 2807/* Program iCLKIP clock to the desired frequency */
2808static void lpt_program_iclkip(struct drm_crtc *crtc)
2809{
2810 struct drm_device *dev = crtc->dev;
2811 struct drm_i915_private *dev_priv = dev->dev_private;
2812 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2813 u32 temp;
2814
09153000
DV		 2815 mutex_lock(&dev_priv->dpio_lock);
2816
e615efe4
ED		 2817 /* It is necessary to ungate the pixclk gate prior to programming
2818 * the divisors, and gate it back when it is done.
2819 */
2820 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2821
2822 /* Disable SSCCTL */
2823 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2824 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2825 SBI_SSCCTL_DISABLE,
2826 SBI_ICLK);
e615efe4
ED		 2827
2828 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2829 if (crtc->mode.clock == 20000) {
2830 auxdiv = 1;
2831 divsel = 0x41;
2832 phaseinc = 0x20;
2833 } else {
2834 /* The iCLK virtual clock root frequency is in MHz,
2835 * but the crtc->mode.clock in in KHz. To get the divisors,
2836 * it is necessary to divide one by another, so we
2837 * convert the virtual clock precision to KHz here for higher
2838 * precision.
2839 */
2840 u32 iclk_virtual_root_freq = 172800 * 1000;
2841 u32 iclk_pi_range = 64;
2842 u32 desired_divisor, msb_divisor_value, pi_value;
2843
2844 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2845 msb_divisor_value = desired_divisor / iclk_pi_range;
2846 pi_value = desired_divisor % iclk_pi_range;
2847
2848 auxdiv = 0;
2849 divsel = msb_divisor_value - 2;
2850 phaseinc = pi_value;
2851 }
2852
2853 /* This should not happen with any sane values */
2854 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2855 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2856 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2857 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2858
2859 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2860 crtc->mode.clock,
2861 auxdiv,
2862 divsel,
2863 phasedir,
2864 phaseinc);
2865
2866 /* Program SSCDIVINTPHASE6 */
988d6ee8 2867 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2868 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2869 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2870 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2871 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2872 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2873 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2874 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2875
2876 /* Program SSCAUXDIV */
988d6ee8 2877 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2878 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2879 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2880 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2881
2882 /* Enable modulator and associated divider */
988d6ee8 2883 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2884 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2885 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2886
2887 /* Wait for initialization time */
2888 udelay(24);
2889
2890 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2891
2892 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2893}
2894
275f01b2
DV		 2895static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2896 enum pipe pch_transcoder)
2897{
2898 struct drm_device *dev = crtc->base.dev;
2899 struct drm_i915_private *dev_priv = dev->dev_private;
2900 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2901
2902 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2903 I915_READ(HTOTAL(cpu_transcoder)));
2904 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2905 I915_READ(HBLANK(cpu_transcoder)));
2906 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2907 I915_READ(HSYNC(cpu_transcoder)));
2908
2909 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2910 I915_READ(VTOTAL(cpu_transcoder)));
2911 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2912 I915_READ(VBLANK(cpu_transcoder)));
2913 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2914 I915_READ(VSYNC(cpu_transcoder)));
2915 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2916 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2917}
2918
f67a559d
JB		 2919/*
2920 * Enable PCH resources required for PCH ports:
2921 * - PCH PLLs
2922 * - FDI training & RX/TX
2923 * - update transcoder timings
2924 * - DP transcoding bits
2925 * - transcoder
2926 */
2927static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2928{
2929 struct drm_device *dev = crtc->dev;
2930 struct drm_i915_private *dev_priv = dev->dev_private;
2931 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2932 int pipe = intel_crtc->pipe;
ee7b9f93 2933 u32 reg, temp;
2c07245f 2934
ab9412ba 2935 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2936
cd986abb
DV		 2937 /* Write the TU size bits before fdi link training, so that error
2938 * detection works. */
2939 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2940 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2941
c98e9dcf 2942 /* For PCH output, training FDI link */
674cf967 2943 dev_priv->display.fdi_link_train(crtc);
2c07245f 2944
572deb37
DV		 2945 /* XXX: pch pll's can be enabled any time before we enable the PCH
2946 * transcoder, and we actually should do this to not upset any PCH
2947 * transcoder that already use the clock when we share it.
2948 *
2949 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
2950 * unconditionally resets the pll - we need that to have the right LVDS
2951 * enable sequence. */
b6b4e185 2952 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 2953
303b81e0 2954 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2955 u32 sel;
4b645f14 2956
c98e9dcf 2957 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 2958 switch (pipe) {
2959 default:
2960 case 0:
2961 temp |= TRANSA_DPLL_ENABLE;
2962 sel = TRANSA_DPLLB_SEL;
2963 break;
2964 case 1:
2965 temp |= TRANSB_DPLL_ENABLE;
2966 sel = TRANSB_DPLLB_SEL;
2967 break;
2968 case 2:
2969 temp |= TRANSC_DPLL_ENABLE;
2970 sel = TRANSC_DPLLB_SEL;
2971 break;
d64311ab 2972 }
ee7b9f93
JB		 2973 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2974 temp |= sel;
2975 else
2976 temp &= ~sel;
c98e9dcf 2977 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2978 }
5eddb70b 2979
d9b6cb56
JB		 2980 /* set transcoder timing, panel must allow it */
2981 assert_panel_unlocked(dev_priv, pipe);
275f01b2 2982 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 2983
303b81e0 2984 intel_fdi_normal_train(crtc);
5e84e1a4 2985
c98e9dcf
JB		 2986 /* For PCH DP, enable TRANS_DP_CTL */
2987 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2988 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2989 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 2990 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 2991 reg = TRANS_DP_CTL(pipe);
2992 temp = I915_READ(reg);
2993 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2994 TRANS_DP_SYNC_MASK |
2995 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2996 temp |= (TRANS_DP_OUTPUT_ENABLE |
2997 TRANS_DP_ENH_FRAMING);
9325c9f0 2998 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2999
3000 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3001 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3002 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3003 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3004
3005 switch (intel_trans_dp_port_sel(crtc)) {
3006 case PCH_DP_B:
5eddb70b 3007 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3008 break;
3009 case PCH_DP_C:
5eddb70b 3010 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3011 break;
3012 case PCH_DP_D:
5eddb70b 3013 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3014 break;
3015 default:
e95d41e1 3016 BUG();
32f9d658 3017 }
2c07245f 3018
5eddb70b 3019 I915_WRITE(reg, temp);
6be4a607 3020 }
b52eb4dc 3021
b8a4f404 3022 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3023}
3024
1507e5bd
PZ		 3025static void lpt_pch_enable(struct drm_crtc *crtc)
3026{
3027 struct drm_device *dev = crtc->dev;
3028 struct drm_i915_private *dev_priv = dev->dev_private;
3029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3030 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3031
ab9412ba 3032 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3033
8c52b5e8 3034 lpt_program_iclkip(crtc);
1507e5bd 3035
0540e488 3036 /* Set transcoder timing. */
275f01b2 3037 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3038
937bb610 3039 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3040}
3041
ee7b9f93
JB		 3042static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3043{
3044 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3045
3046 if (pll == NULL)
3047 return;
3048
3049 if (pll->refcount == 0) {
3050 WARN(1, "bad PCH PLL refcount\n");
3051 return;
3052 }
3053
3054 --pll->refcount;
3055 intel_crtc->pch_pll = NULL;
3056}
3057
3058static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3059{
3060 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3061 struct intel_pch_pll *pll;
3062 int i;
3063
3064 pll = intel_crtc->pch_pll;
3065 if (pll) {
3066 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3067 intel_crtc->base.base.id, pll->pll_reg);
3068 goto prepare;
3069 }
3070
98b6bd99
DV		 3071 if (HAS_PCH_IBX(dev_priv->dev)) {
3072 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3073 i = intel_crtc->pipe;
3074 pll = &dev_priv->pch_plls[i];
3075
3076 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3077 intel_crtc->base.base.id, pll->pll_reg);
3078
3079 goto found;
3080 }
3081
ee7b9f93
JB		 3082 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3083 pll = &dev_priv->pch_plls[i];
3084
3085 /* Only want to check enabled timings first */
3086 if (pll->refcount == 0)
3087 continue;
3088
3089 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3090 fp == I915_READ(pll->fp0_reg)) {
3091 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3092 intel_crtc->base.base.id,
3093 pll->pll_reg, pll->refcount, pll->active);
3094
3095 goto found;
3096 }
3097 }
3098
3099 /* Ok no matching timings, maybe there's a free one? */
3100 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3101 pll = &dev_priv->pch_plls[i];
3102 if (pll->refcount == 0) {
3103 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3104 intel_crtc->base.base.id, pll->pll_reg);
3105 goto found;
3106 }
3107 }
3108
3109 return NULL;
3110
3111found:
3112 intel_crtc->pch_pll = pll;
3113 pll->refcount++;
84f44ce7 3114 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
ee7b9f93
JB		 3115prepare: /* separate function? */
3116 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3117
e04c7350
CW		 3118 /* Wait for the clocks to stabilize before rewriting the regs */
3119 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3120 POSTING_READ(pll->pll_reg);
3121 udelay(150);
e04c7350
CW		 3122
3123 I915_WRITE(pll->fp0_reg, fp);
3124 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3125 pll->on = false;
3126 return pll;
3127}
3128
a1520318 3129static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3130{
3131 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3132 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3133 u32 temp;
3134
3135 temp = I915_READ(dslreg);
3136 udelay(500);
3137 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3138 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3139 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3140 }
3141}
3142
b074cec8
JB		 3143static void ironlake_pfit_enable(struct intel_crtc *crtc)
3144{
3145 struct drm_device *dev = crtc->base.dev;
3146 struct drm_i915_private *dev_priv = dev->dev_private;
3147 int pipe = crtc->pipe;
3148
0ef37f3f 3149 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3150 /* Force use of hard-coded filter coefficients
3151 * as some pre-programmed values are broken,
3152 * e.g. x201.
3153 */
3154 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3155 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3156 PF_PIPE_SEL_IVB(pipe));
3157 else
3158 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3159 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3160 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3161 }
3162}
3163
f67a559d
JB		 3164static void ironlake_crtc_enable(struct drm_crtc *crtc)
3165{
3166 struct drm_device *dev = crtc->dev;
3167 struct drm_i915_private *dev_priv = dev->dev_private;
3168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3169 struct intel_encoder *encoder;
f67a559d
JB		 3170 int pipe = intel_crtc->pipe;
3171 int plane = intel_crtc->plane;
3172 u32 temp;
f67a559d 3173
08a48469
DV		 3174 WARN_ON(!crtc->enabled);
3175
f67a559d
JB		 3176 if (intel_crtc->active)
3177 return;
3178
3179 intel_crtc->active = true;
8664281b
PZ		 3180
3181 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3182 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3183
f67a559d
JB		 3184 intel_update_watermarks(dev);
3185
3186 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3187 temp = I915_READ(PCH_LVDS);
3188 if ((temp & LVDS_PORT_EN) == 0)
3189 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3190 }
3191
f67a559d 3192
5bfe2ac0 3193 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3194 /* Note: FDI PLL enabling _must_ be done before we enable the
3195 * cpu pipes, hence this is separate from all the other fdi/pch
3196 * enabling. */
88cefb6c 3197 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3198 } else {
3199 assert_fdi_tx_disabled(dev_priv, pipe);
3200 assert_fdi_rx_disabled(dev_priv, pipe);
3201 }
f67a559d 3202
bf49ec8c
DV		 3203 for_each_encoder_on_crtc(dev, crtc, encoder)
3204 if (encoder->pre_enable)
3205 encoder->pre_enable(encoder);
f67a559d
JB		 3206
3207 /* Enable panel fitting for LVDS */
b074cec8 3208 ironlake_pfit_enable(intel_crtc);
f67a559d 3209
9c54c0dd
JB		 3210 /*
3211 * On ILK+ LUT must be loaded before the pipe is running but with
3212 * clocks enabled
3213 */
3214 intel_crtc_load_lut(crtc);
3215
5bfe2ac0
DV		 3216 intel_enable_pipe(dev_priv, pipe,
3217 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3218 intel_enable_plane(dev_priv, plane, pipe);
3219
5bfe2ac0 3220 if (intel_crtc->config.has_pch_encoder)
f67a559d 3221 ironlake_pch_enable(crtc);
c98e9dcf 3222
d1ebd816 3223 mutex_lock(&dev->struct_mutex);
bed4a673 3224 intel_update_fbc(dev);
d1ebd816
BW		 3225 mutex_unlock(&dev->struct_mutex);
3226
6b383a7f 3227 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3228
fa5c73b1
DV		 3229 for_each_encoder_on_crtc(dev, crtc, encoder)
3230 encoder->enable(encoder);
61b77ddd
DV		 3231
3232 if (HAS_PCH_CPT(dev))
a1520318 3233 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3234
3235 /*
3236 * There seems to be a race in PCH platform hw (at least on some
3237 * outputs) where an enabled pipe still completes any pageflip right
3238 * away (as if the pipe is off) instead of waiting for vblank. As soon
3239 * as the first vblank happend, everything works as expected. Hence just
3240 * wait for one vblank before returning to avoid strange things
3241 * happening.
3242 */
3243 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3244}
3245
42db64ef
PZ		 3246/* IPS only exists on ULT machines and is tied to pipe A. */
3247static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3248{
3249 return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
3250}
3251
3252static void hsw_enable_ips(struct intel_crtc *crtc)
3253{
3254 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3255
3256 if (!crtc->config.ips_enabled)
3257 return;
3258
3259 /* We can only enable IPS after we enable a plane and wait for a vblank.
3260 * We guarantee that the plane is enabled by calling intel_enable_ips
3261 * only after intel_enable_plane. And intel_enable_plane already waits
3262 * for a vblank, so all we need to do here is to enable the IPS bit. */
3263 assert_plane_enabled(dev_priv, crtc->plane);
3264 I915_WRITE(IPS_CTL, IPS_ENABLE);
3265}
3266
3267static void hsw_disable_ips(struct intel_crtc *crtc)
3268{
3269 struct drm_device *dev = crtc->base.dev;
3270 struct drm_i915_private *dev_priv = dev->dev_private;
3271
3272 if (!crtc->config.ips_enabled)
3273 return;
3274
3275 assert_plane_enabled(dev_priv, crtc->plane);
3276 I915_WRITE(IPS_CTL, 0);
3277
3278 /* We need to wait for a vblank before we can disable the plane. */
3279 intel_wait_for_vblank(dev, crtc->pipe);
3280}
3281
4f771f10
PZ		 3282static void haswell_crtc_enable(struct drm_crtc *crtc)
3283{
3284 struct drm_device *dev = crtc->dev;
3285 struct drm_i915_private *dev_priv = dev->dev_private;
3286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3287 struct intel_encoder *encoder;
3288 int pipe = intel_crtc->pipe;
3289 int plane = intel_crtc->plane;
4f771f10
PZ		 3290
3291 WARN_ON(!crtc->enabled);
3292
3293 if (intel_crtc->active)
3294 return;
3295
3296 intel_crtc->active = true;
8664281b
PZ		 3297
3298 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3299 if (intel_crtc->config.has_pch_encoder)
3300 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3301
4f771f10
PZ		 3302 intel_update_watermarks(dev);
3303
5bfe2ac0 3304 if (intel_crtc->config.has_pch_encoder)
04945641 3305 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3306
3307 for_each_encoder_on_crtc(dev, crtc, encoder)
3308 if (encoder->pre_enable)
3309 encoder->pre_enable(encoder);
3310
1f544388 3311 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3312
1f544388 3313 /* Enable panel fitting for eDP */
b074cec8 3314 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3315
3316 /*
3317 * On ILK+ LUT must be loaded before the pipe is running but with
3318 * clocks enabled
3319 */
3320 intel_crtc_load_lut(crtc);
3321
1f544388 3322 intel_ddi_set_pipe_settings(crtc);
8228c251 3323 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3324
5bfe2ac0
DV		 3325 intel_enable_pipe(dev_priv, pipe,
3326 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3327 intel_enable_plane(dev_priv, plane, pipe);
3328
42db64ef
PZ		 3329 hsw_enable_ips(intel_crtc);
3330
5bfe2ac0 3331 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3332 lpt_pch_enable(crtc);
4f771f10
PZ		 3333
3334 mutex_lock(&dev->struct_mutex);
3335 intel_update_fbc(dev);
3336 mutex_unlock(&dev->struct_mutex);
3337
3338 intel_crtc_update_cursor(crtc, true);
3339
3340 for_each_encoder_on_crtc(dev, crtc, encoder)
3341 encoder->enable(encoder);
3342
4f771f10
PZ		 3343 /*
3344 * There seems to be a race in PCH platform hw (at least on some
3345 * outputs) where an enabled pipe still completes any pageflip right
3346 * away (as if the pipe is off) instead of waiting for vblank. As soon
3347 * as the first vblank happend, everything works as expected. Hence just
3348 * wait for one vblank before returning to avoid strange things
3349 * happening.
3350 */
3351 intel_wait_for_vblank(dev, intel_crtc->pipe);
3352}
3353
3f8dce3a
DV		 3354static void ironlake_pfit_disable(struct intel_crtc *crtc)
3355{
3356 struct drm_device *dev = crtc->base.dev;
3357 struct drm_i915_private *dev_priv = dev->dev_private;
3358 int pipe = crtc->pipe;
3359
3360 /* To avoid upsetting the power well on haswell only disable the pfit if
3361 * it's in use. The hw state code will make sure we get this right. */
3362 if (crtc->config.pch_pfit.size) {
3363 I915_WRITE(PF_CTL(pipe), 0);
3364 I915_WRITE(PF_WIN_POS(pipe), 0);
3365 I915_WRITE(PF_WIN_SZ(pipe), 0);
3366 }
3367}
3368
6be4a607
JB		 3369static void ironlake_crtc_disable(struct drm_crtc *crtc)
3370{
3371 struct drm_device *dev = crtc->dev;
3372 struct drm_i915_private *dev_priv = dev->dev_private;
3373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3374 struct intel_encoder *encoder;
6be4a607
JB		 3375 int pipe = intel_crtc->pipe;
3376 int plane = intel_crtc->plane;
5eddb70b 3377 u32 reg, temp;
b52eb4dc 3378
ef9c3aee 3379
f7abfe8b
CW		 3380 if (!intel_crtc->active)
3381 return;
3382
ea9d758d
DV		 3383 for_each_encoder_on_crtc(dev, crtc, encoder)
3384 encoder->disable(encoder);
3385
e6c3a2a6 3386 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3387 drm_vblank_off(dev, pipe);
6b383a7f 3388 intel_crtc_update_cursor(crtc, false);
5eddb70b 3389
b24e7179 3390 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3391
973d04f9
CW		 3392 if (dev_priv->cfb_plane == plane)
3393 intel_disable_fbc(dev);
2c07245f 3394
8664281b 3395 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
b24e7179 3396 intel_disable_pipe(dev_priv, pipe);
32f9d658 3397
3f8dce3a 3398 ironlake_pfit_disable(intel_crtc);
2c07245f 3399
bf49ec8c
DV		 3400 for_each_encoder_on_crtc(dev, crtc, encoder)
3401 if (encoder->post_disable)
3402 encoder->post_disable(encoder);
2c07245f 3403
0fc932b8 3404 ironlake_fdi_disable(crtc);
249c0e64 3405
b8a4f404 3406 ironlake_disable_pch_transcoder(dev_priv, pipe);
8664281b 3407 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3408
6be4a607
JB		 3409 if (HAS_PCH_CPT(dev)) {
3410 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3411 reg = TRANS_DP_CTL(pipe);
3412 temp = I915_READ(reg);
3413 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3414 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3415 I915_WRITE(reg, temp);
6be4a607
JB		 3416
3417 /* disable DPLL_SEL */
3418 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3419 switch (pipe) {
3420 case 0:
d64311ab 3421 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3422 break;
3423 case 1:
6be4a607 3424 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3425 break;
3426 case 2:
4b645f14 3427 /* C shares PLL A or B */
d64311ab 3428 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3429 break;
3430 default:
3431 BUG(); /* wtf */
3432 }
6be4a607 3433 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3434 }
e3421a18 3435
6be4a607 3436 /* disable PCH DPLL */
ee7b9f93 3437 intel_disable_pch_pll(intel_crtc);
8db9d77b 3438
88cefb6c 3439 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3440
f7abfe8b 3441 intel_crtc->active = false;
6b383a7f 3442 intel_update_watermarks(dev);
d1ebd816
BW		 3443
3444 mutex_lock(&dev->struct_mutex);
6b383a7f 3445 intel_update_fbc(dev);
d1ebd816 3446 mutex_unlock(&dev->struct_mutex);
6be4a607 3447}
1b3c7a47 3448
4f771f10 3449static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3450{
4f771f10
PZ		 3451 struct drm_device *dev = crtc->dev;
3452 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3453 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3454 struct intel_encoder *encoder;
3455 int pipe = intel_crtc->pipe;
3456 int plane = intel_crtc->plane;
3b117c8f 3457 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3458
4f771f10
PZ		 3459 if (!intel_crtc->active)
3460 return;
3461
3462 for_each_encoder_on_crtc(dev, crtc, encoder)
3463 encoder->disable(encoder);
3464
3465 intel_crtc_wait_for_pending_flips(crtc);
3466 drm_vblank_off(dev, pipe);
3467 intel_crtc_update_cursor(crtc, false);
3468
891348b2 3469 /* FBC must be disabled before disabling the plane on HSW. */
4f771f10
PZ		 3470 if (dev_priv->cfb_plane == plane)
3471 intel_disable_fbc(dev);
3472
42db64ef
PZ		 3473 hsw_disable_ips(intel_crtc);
3474
891348b2
RV		 3475 intel_disable_plane(dev_priv, plane, pipe);
3476
8664281b
PZ		 3477 if (intel_crtc->config.has_pch_encoder)
3478 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3479 intel_disable_pipe(dev_priv, pipe);
3480
ad80a810 3481 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3482
3f8dce3a 3483 ironlake_pfit_disable(intel_crtc);
4f771f10 3484
1f544388 3485 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3486
3487 for_each_encoder_on_crtc(dev, crtc, encoder)
3488 if (encoder->post_disable)
3489 encoder->post_disable(encoder);
3490
88adfff1 3491 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3492 lpt_disable_pch_transcoder(dev_priv);
8664281b 3493 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3494 intel_ddi_fdi_disable(crtc);
83616634 3495 }
4f771f10
PZ		 3496
3497 intel_crtc->active = false;
3498 intel_update_watermarks(dev);
3499
3500 mutex_lock(&dev->struct_mutex);
3501 intel_update_fbc(dev);
3502 mutex_unlock(&dev->struct_mutex);
3503}
3504
ee7b9f93
JB		 3505static void ironlake_crtc_off(struct drm_crtc *crtc)
3506{
3507 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3508 intel_put_pch_pll(intel_crtc);
3509}
3510
6441ab5f
PZ		 3511static void haswell_crtc_off(struct drm_crtc *crtc)
3512{
3513 intel_ddi_put_crtc_pll(crtc);
3514}
3515
02e792fb
DV		 3516static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3517{
02e792fb 3518 if (!enable && intel_crtc->overlay) {
23f09ce3 3519 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3520 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3521
23f09ce3 3522 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3523 dev_priv->mm.interruptible = false;
3524 (void) intel_overlay_switch_off(intel_crtc->overlay);
3525 dev_priv->mm.interruptible = true;
23f09ce3 3526 mutex_unlock(&dev->struct_mutex);
02e792fb 3527 }
02e792fb 3528
5dcdbcb0
CW		 3529 /* Let userspace switch the overlay on again. In most cases userspace
3530 * has to recompute where to put it anyway.
3531 */
02e792fb
DV		 3532}
3533
61bc95c1
EE		 3534/**
3535 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3536 * cursor plane briefly if not already running after enabling the display
3537 * plane.
3538 * This workaround avoids occasional blank screens when self refresh is
3539 * enabled.
3540 */
3541static void
3542g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3543{
3544 u32 cntl = I915_READ(CURCNTR(pipe));
3545
3546 if ((cntl & CURSOR_MODE) == 0) {
3547 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3548
3549 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3550 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3551 intel_wait_for_vblank(dev_priv->dev, pipe);
3552 I915_WRITE(CURCNTR(pipe), cntl);
3553 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3554 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3555 }
3556}
3557
2dd24552
JB		 3558static void i9xx_pfit_enable(struct intel_crtc *crtc)
3559{
3560 struct drm_device *dev = crtc->base.dev;
3561 struct drm_i915_private *dev_priv = dev->dev_private;
3562 struct intel_crtc_config *pipe_config = &crtc->config;
3563
328d8e82 3564 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3565 return;
3566
2dd24552 3567 /*
c0b03411
DV		 3568 * The panel fitter should only be adjusted whilst the pipe is disabled,
3569 * according to register description and PRM.
2dd24552 3570 */
c0b03411
DV		 3571 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3572 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3573
b074cec8
JB		 3574 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3575 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3576
3577 /* Border color in case we don't scale up to the full screen. Black by
3578 * default, change to something else for debugging. */
3579 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3580}
3581
89b667f8
JB		 3582static void valleyview_crtc_enable(struct drm_crtc *crtc)
3583{
3584 struct drm_device *dev = crtc->dev;
3585 struct drm_i915_private *dev_priv = dev->dev_private;
3586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3587 struct intel_encoder *encoder;
3588 int pipe = intel_crtc->pipe;
3589 int plane = intel_crtc->plane;
3590
3591 WARN_ON(!crtc->enabled);
3592
3593 if (intel_crtc->active)
3594 return;
3595
3596 intel_crtc->active = true;
3597 intel_update_watermarks(dev);
3598
3599 mutex_lock(&dev_priv->dpio_lock);
3600
3601 for_each_encoder_on_crtc(dev, crtc, encoder)
3602 if (encoder->pre_pll_enable)
3603 encoder->pre_pll_enable(encoder);
3604
3605 intel_enable_pll(dev_priv, pipe);
3606
3607 for_each_encoder_on_crtc(dev, crtc, encoder)
3608 if (encoder->pre_enable)
3609 encoder->pre_enable(encoder);
3610
3611 /* VLV wants encoder enabling _before_ the pipe is up. */
3612 for_each_encoder_on_crtc(dev, crtc, encoder)
3613 encoder->enable(encoder);
3614
2dd24552
JB		 3615 /* Enable panel fitting for eDP */
3616 i9xx_pfit_enable(intel_crtc);
3617
89b667f8
JB		 3618 intel_enable_pipe(dev_priv, pipe, false);
3619 intel_enable_plane(dev_priv, plane, pipe);
3620
3621 intel_crtc_load_lut(crtc);
3622 intel_update_fbc(dev);
3623
3624 /* Give the overlay scaler a chance to enable if it's on this pipe */
3625 intel_crtc_dpms_overlay(intel_crtc, true);
3626 intel_crtc_update_cursor(crtc, true);
3627
3628 mutex_unlock(&dev_priv->dpio_lock);
3629}
3630
0b8765c6 3631static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3632{
3633 struct drm_device *dev = crtc->dev;
79e53945
JB		 3634 struct drm_i915_private *dev_priv = dev->dev_private;
3635 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3636 struct intel_encoder *encoder;
79e53945 3637 int pipe = intel_crtc->pipe;
80824003 3638 int plane = intel_crtc->plane;
79e53945 3639
08a48469
DV		 3640 WARN_ON(!crtc->enabled);
3641
f7abfe8b
CW		 3642 if (intel_crtc->active)
3643 return;
3644
3645 intel_crtc->active = true;
6b383a7f
CW		 3646 intel_update_watermarks(dev);
3647
63d7bbe9 3648 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3649
3650 for_each_encoder_on_crtc(dev, crtc, encoder)
3651 if (encoder->pre_enable)
3652 encoder->pre_enable(encoder);
3653
2dd24552
JB		 3654 /* Enable panel fitting for LVDS */
3655 i9xx_pfit_enable(intel_crtc);
3656
040484af 3657 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3658 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3659 if (IS_G4X(dev))
3660 g4x_fixup_plane(dev_priv, pipe);
79e53945 3661
0b8765c6 3662 intel_crtc_load_lut(crtc);
bed4a673 3663 intel_update_fbc(dev);
79e53945 3664
0b8765c6
JB		 3665 /* Give the overlay scaler a chance to enable if it's on this pipe */
3666 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3667 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3668
fa5c73b1
DV		 3669 for_each_encoder_on_crtc(dev, crtc, encoder)
3670 encoder->enable(encoder);
0b8765c6 3671}
79e53945 3672
87476d63
DV		 3673static void i9xx_pfit_disable(struct intel_crtc *crtc)
3674{
3675 struct drm_device *dev = crtc->base.dev;
3676 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3677
328d8e82
DV		 3678 if (!crtc->config.gmch_pfit.control)
3679 return;
87476d63 3680
328d8e82 3681 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3682
328d8e82
DV		 3683 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3684 I915_READ(PFIT_CONTROL));
3685 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3686}
3687
0b8765c6
JB		 3688static void i9xx_crtc_disable(struct drm_crtc *crtc)
3689{
3690 struct drm_device *dev = crtc->dev;
3691 struct drm_i915_private *dev_priv = dev->dev_private;
3692 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3693 struct intel_encoder *encoder;
0b8765c6
JB		 3694 int pipe = intel_crtc->pipe;
3695 int plane = intel_crtc->plane;
ef9c3aee 3696
f7abfe8b
CW		 3697 if (!intel_crtc->active)
3698 return;
3699
ea9d758d
DV		 3700 for_each_encoder_on_crtc(dev, crtc, encoder)
3701 encoder->disable(encoder);
3702
0b8765c6 3703 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3704 intel_crtc_wait_for_pending_flips(crtc);
3705 drm_vblank_off(dev, pipe);
0b8765c6 3706 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3707 intel_crtc_update_cursor(crtc, false);
0b8765c6 3708
973d04f9
CW		 3709 if (dev_priv->cfb_plane == plane)
3710 intel_disable_fbc(dev);
79e53945 3711
b24e7179 3712 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3713 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3714
87476d63 3715 i9xx_pfit_disable(intel_crtc);
24a1f16d 3716
89b667f8
JB		 3717 for_each_encoder_on_crtc(dev, crtc, encoder)
3718 if (encoder->post_disable)
3719 encoder->post_disable(encoder);
3720
63d7bbe9 3721 intel_disable_pll(dev_priv, pipe);
0b8765c6 3722
f7abfe8b 3723 intel_crtc->active = false;
6b383a7f
CW		 3724 intel_update_fbc(dev);
3725 intel_update_watermarks(dev);
0b8765c6
JB		 3726}
3727
ee7b9f93
JB		 3728static void i9xx_crtc_off(struct drm_crtc *crtc)
3729{
3730}
3731
976f8a20
DV		 3732static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3733 bool enabled)
2c07245f
ZW		 3734{
3735 struct drm_device *dev = crtc->dev;
3736 struct drm_i915_master_private *master_priv;
3737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3738 int pipe = intel_crtc->pipe;
79e53945
JB		 3739
3740 if (!dev->primary->master)
3741 return;
3742
3743 master_priv = dev->primary->master->driver_priv;
3744 if (!master_priv->sarea_priv)
3745 return;
3746
79e53945
JB		 3747 switch (pipe) {
3748 case 0:
3749 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3750 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3751 break;
3752 case 1:
3753 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3754 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3755 break;
3756 default:
9db4a9c7 3757 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3758 break;
3759 }
79e53945
JB		 3760}
3761
976f8a20
DV		 3762/**
3763 * Sets the power management mode of the pipe and plane.
3764 */
3765void intel_crtc_update_dpms(struct drm_crtc *crtc)
3766{
3767 struct drm_device *dev = crtc->dev;
3768 struct drm_i915_private *dev_priv = dev->dev_private;
3769 struct intel_encoder *intel_encoder;
3770 bool enable = false;
3771
3772 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3773 enable |= intel_encoder->connectors_active;
3774
3775 if (enable)
3776 dev_priv->display.crtc_enable(crtc);
3777 else
3778 dev_priv->display.crtc_disable(crtc);
3779
3780 intel_crtc_update_sarea(crtc, enable);
3781}
3782
cdd59983
CW		 3783static void intel_crtc_disable(struct drm_crtc *crtc)
3784{
cdd59983 3785 struct drm_device *dev = crtc->dev;
976f8a20 3786 struct drm_connector *connector;
ee7b9f93 3787 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3788 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3789
976f8a20
DV		 3790 /* crtc should still be enabled when we disable it. */
3791 WARN_ON(!crtc->enabled);
3792
3793 dev_priv->display.crtc_disable(crtc);
c77bf565 3794 intel_crtc->eld_vld = false;
976f8a20 3795 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3796 dev_priv->display.off(crtc);
3797
931872fc
CW		 3798 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3799 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3800
3801 if (crtc->fb) {
3802 mutex_lock(&dev->struct_mutex);
1690e1eb 3803 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3804 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3805 crtc->fb = NULL;
3806 }
3807
3808 /* Update computed state. */
3809 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3810 if (!connector->encoder || !connector->encoder->crtc)
3811 continue;
3812
3813 if (connector->encoder->crtc != crtc)
3814 continue;
3815
3816 connector->dpms = DRM_MODE_DPMS_OFF;
3817 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3818 }
3819}
3820
a261b246 3821void intel_modeset_disable(struct drm_device *dev)
79e53945 3822{
a261b246
DV		 3823 struct drm_crtc *crtc;
3824
3825 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3826 if (crtc->enabled)
3827 intel_crtc_disable(crtc);
3828 }
79e53945
JB		 3829}
3830
ea5b213a 3831void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3832{
4ef69c7a 3833 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3834
ea5b213a
CW		 3835 drm_encoder_cleanup(encoder);
3836 kfree(intel_encoder);
7e7d76c3
JB		 3837}
3838
5ab432ef
DV		 3839/* Simple dpms helper for encodres with just one connector, no cloning and only
3840 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3841 * state of the entire output pipe. */
3842void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3843{
5ab432ef
DV		 3844 if (mode == DRM_MODE_DPMS_ON) {
3845 encoder->connectors_active = true;
3846
b2cabb0e 3847 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3848 } else {
3849 encoder->connectors_active = false;
3850
b2cabb0e 3851 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3852 }
79e53945
JB		 3853}
3854
0a91ca29
DV		 3855/* Cross check the actual hw state with our own modeset state tracking (and it's
3856 * internal consistency). */
b980514c 3857static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3858{
0a91ca29
DV		 3859 if (connector->get_hw_state(connector)) {
3860 struct intel_encoder *encoder = connector->encoder;
3861 struct drm_crtc *crtc;
3862 bool encoder_enabled;
3863 enum pipe pipe;
3864
3865 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3866 connector->base.base.id,
3867 drm_get_connector_name(&connector->base));
3868
3869 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3870 "wrong connector dpms state\n");
3871 WARN(connector->base.encoder != &encoder->base,
3872 "active connector not linked to encoder\n");
3873 WARN(!encoder->connectors_active,
3874 "encoder->connectors_active not set\n");
3875
3876 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3877 WARN(!encoder_enabled, "encoder not enabled\n");
3878 if (WARN_ON(!encoder->base.crtc))
3879 return;
3880
3881 crtc = encoder->base.crtc;
3882
3883 WARN(!crtc->enabled, "crtc not enabled\n");
3884 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3885 WARN(pipe != to_intel_crtc(crtc)->pipe,
3886 "encoder active on the wrong pipe\n");
3887 }
79e53945
JB		 3888}
3889
5ab432ef
DV		 3890/* Even simpler default implementation, if there's really no special case to
3891 * consider. */
3892void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3893{
5ab432ef 3894 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3895
5ab432ef
DV		 3896 /* All the simple cases only support two dpms states. */
3897 if (mode != DRM_MODE_DPMS_ON)
3898 mode = DRM_MODE_DPMS_OFF;
d4270e57 3899
5ab432ef
DV		 3900 if (mode == connector->dpms)
3901 return;
3902
3903 connector->dpms = mode;
3904
3905 /* Only need to change hw state when actually enabled */
3906 if (encoder->base.crtc)
3907 intel_encoder_dpms(encoder, mode);
3908 else
8af6cf88 3909 WARN_ON(encoder->connectors_active != false);
0a91ca29 3910
b980514c 3911 intel_modeset_check_state(connector->dev);
79e53945
JB		 3912}
3913
f0947c37
DV		 3914/* Simple connector->get_hw_state implementation for encoders that support only
3915 * one connector and no cloning and hence the encoder state determines the state
3916 * of the connector. */
3917bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3918{
24929352 3919 enum pipe pipe = 0;
f0947c37 3920 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3921
f0947c37 3922 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3923}
3924
1857e1da
DV		 3925static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3926 struct intel_crtc_config *pipe_config)
3927{
3928 struct drm_i915_private *dev_priv = dev->dev_private;
3929 struct intel_crtc *pipe_B_crtc =
3930 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3931
3932 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3933 pipe_name(pipe), pipe_config->fdi_lanes);
3934 if (pipe_config->fdi_lanes > 4) {
3935 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3936 pipe_name(pipe), pipe_config->fdi_lanes);
3937 return false;
3938 }
3939
3940 if (IS_HASWELL(dev)) {
3941 if (pipe_config->fdi_lanes > 2) {
3942 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3943 pipe_config->fdi_lanes);
3944 return false;
3945 } else {
3946 return true;
3947 }
3948 }
3949
3950 if (INTEL_INFO(dev)->num_pipes == 2)
3951 return true;
3952
3953 /* Ivybridge 3 pipe is really complicated */
3954 switch (pipe) {
3955 case PIPE_A:
3956 return true;
3957 case PIPE_B:
3958 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3959 pipe_config->fdi_lanes > 2) {
3960 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3961 pipe_name(pipe), pipe_config->fdi_lanes);
3962 return false;
3963 }
3964 return true;
3965 case PIPE_C:
1e833f40 3966 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 3967 pipe_B_crtc->config.fdi_lanes <= 2) {
3968 if (pipe_config->fdi_lanes > 2) {
3969 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3970 pipe_name(pipe), pipe_config->fdi_lanes);
3971 return false;
3972 }
3973 } else {
3974 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3975 return false;
3976 }
3977 return true;
3978 default:
3979 BUG();
3980 }
3981}
3982
e29c22c0
DV		 3983#define RETRY 1
3984static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3985 struct intel_crtc_config *pipe_config)
877d48d5 3986{
1857e1da 3987 struct drm_device *dev = intel_crtc->base.dev;
877d48d5
DV		 3988 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3989 int target_clock, lane, link_bw;
e29c22c0 3990 bool setup_ok, needs_recompute = false;
877d48d5 3991
e29c22c0 3992retry:
877d48d5
DV		 3993 /* FDI is a binary signal running at ~2.7GHz, encoding
3994 * each output octet as 10 bits. The actual frequency
3995 * is stored as a divider into a 100MHz clock, and the
3996 * mode pixel clock is stored in units of 1KHz.
3997 * Hence the bw of each lane in terms of the mode signal
3998 * is:
3999 */
4000 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4001
4002 if (pipe_config->pixel_target_clock)
4003 target_clock = pipe_config->pixel_target_clock;
4004 else
4005 target_clock = adjusted_mode->clock;
4006
4007 lane = ironlake_get_lanes_required(target_clock, link_bw,
4008 pipe_config->pipe_bpp);
4009
4010 pipe_config->fdi_lanes = lane;
4011
4012 if (pipe_config->pixel_multiplier > 1)
4013 link_bw *= pipe_config->pixel_multiplier;
4014 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock,
4015 link_bw, &pipe_config->fdi_m_n);
1857e1da 4016
e29c22c0
DV		 4017 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4018 intel_crtc->pipe, pipe_config);
4019 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4020 pipe_config->pipe_bpp -= 2*3;
4021 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4022 pipe_config->pipe_bpp);
4023 needs_recompute = true;
4024 pipe_config->bw_constrained = true;
4025
4026 goto retry;
4027 }
4028
4029 if (needs_recompute)
4030 return RETRY;
4031
4032 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4033}
4034
42db64ef
PZ		 4035static void hsw_compute_ips_config(struct intel_crtc *crtc,
4036 struct intel_crtc_config *pipe_config)
4037{
3c4ca58c
PZ		 4038 pipe_config->ips_enabled = i915_enable_ips &&
4039 hsw_crtc_supports_ips(crtc) &&
42db64ef
PZ		 4040 pipe_config->pipe_bpp == 24;
4041}
4042
e29c22c0
DV		 4043static int intel_crtc_compute_config(struct drm_crtc *crtc,
4044 struct intel_crtc_config *pipe_config)
79e53945 4045{
2c07245f 4046 struct drm_device *dev = crtc->dev;
b8cecdf5 4047 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
42db64ef 4048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
89749350 4049
bad720ff 4050 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4051 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4052 if (pipe_config->requested_mode.clock * 3
4053 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4054 return -EINVAL;
2c07245f 4055 }
89749350 4056
f9bef081
DV		 4057 /* All interlaced capable intel hw wants timings in frames. Note though
4058 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4059 * timings, so we need to be careful not to clobber these.*/
7ae89233 4060 if (!pipe_config->timings_set)
f9bef081 4061 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4062
8693a824
DL		 4063 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4064 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4065 */
4066 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4067 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4068 return -EINVAL;
44f46b42 4069
bd080ee5 4070 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4071 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4072 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4073 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4074 * for lvds. */
4075 pipe_config->pipe_bpp = 8*3;
4076 }
4077
42db64ef
PZ		 4078 if (IS_HASWELL(dev))
4079 hsw_compute_ips_config(intel_crtc, pipe_config);
4080
877d48d5 4081 if (pipe_config->has_pch_encoder)
42db64ef 4082 return ironlake_fdi_compute_config(intel_crtc, pipe_config);
877d48d5 4083
e29c22c0 4084 return 0;
79e53945
JB		 4085}
4086
25eb05fc
JB		 4087static int valleyview_get_display_clock_speed(struct drm_device *dev)
4088{
4089 return 400000; /* FIXME */
4090}
4091
e70236a8
JB		 4092static int i945_get_display_clock_speed(struct drm_device *dev)
4093{
4094 return 400000;
4095}
79e53945 4096
e70236a8 4097static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4098{
e70236a8
JB		 4099 return 333000;
4100}
79e53945 4101
e70236a8
JB		 4102static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4103{
4104 return 200000;
4105}
79e53945 4106
e70236a8
JB		 4107static int i915gm_get_display_clock_speed(struct drm_device *dev)
4108{
4109 u16 gcfgc = 0;
79e53945 4110
e70236a8
JB		 4111 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4112
4113 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4114 return 133000;
4115 else {
4116 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4117 case GC_DISPLAY_CLOCK_333_MHZ:
4118 return 333000;
4119 default:
4120 case GC_DISPLAY_CLOCK_190_200_MHZ:
4121 return 190000;
79e53945 4122 }
e70236a8
JB		 4123 }
4124}
4125
4126static int i865_get_display_clock_speed(struct drm_device *dev)
4127{
4128 return 266000;
4129}
4130
4131static int i855_get_display_clock_speed(struct drm_device *dev)
4132{
4133 u16 hpllcc = 0;
4134 /* Assume that the hardware is in the high speed state. This
4135 * should be the default.
4136 */
4137 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4138 case GC_CLOCK_133_200:
4139 case GC_CLOCK_100_200:
4140 return 200000;
4141 case GC_CLOCK_166_250:
4142 return 250000;
4143 case GC_CLOCK_100_133:
79e53945 4144 return 133000;
e70236a8 4145 }
79e53945 4146
e70236a8
JB		 4147 /* Shouldn't happen */
4148 return 0;
4149}
79e53945 4150
e70236a8
JB		 4151static int i830_get_display_clock_speed(struct drm_device *dev)
4152{
4153 return 133000;
79e53945
JB		 4154}
4155
2c07245f 4156static void
a65851af 4157intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4158{
a65851af
VS		 4159 while (*num > DATA_LINK_M_N_MASK ||
4160 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4161 *num >>= 1;
4162 *den >>= 1;
4163 }
4164}
4165
a65851af
VS		 4166static void compute_m_n(unsigned int m, unsigned int n,
4167 uint32_t *ret_m, uint32_t *ret_n)
4168{
4169 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4170 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4171 intel_reduce_m_n_ratio(ret_m, ret_n);
4172}
4173
e69d0bc1
DV		 4174void
4175intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4176 int pixel_clock, int link_clock,
4177 struct intel_link_m_n *m_n)
2c07245f 4178{
e69d0bc1 4179 m_n->tu = 64;
a65851af
VS		 4180
4181 compute_m_n(bits_per_pixel * pixel_clock,
4182 link_clock * nlanes * 8,
4183 &m_n->gmch_m, &m_n->gmch_n);
4184
4185 compute_m_n(pixel_clock, link_clock,
4186 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4187}
4188
a7615030
CW		 4189static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4190{
72bbe58c
KP		 4191 if (i915_panel_use_ssc >= 0)
4192 return i915_panel_use_ssc != 0;
41aa3448 4193 return dev_priv->vbt.lvds_use_ssc
435793df 4194 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4195}
4196
a0c4da24
JB		 4197static int vlv_get_refclk(struct drm_crtc *crtc)
4198{
4199 struct drm_device *dev = crtc->dev;
4200 struct drm_i915_private *dev_priv = dev->dev_private;
4201 int refclk = 27000; /* for DP & HDMI */
4202
4203 return 100000; /* only one validated so far */
4204
4205 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4206 refclk = 96000;
4207 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4208 if (intel_panel_use_ssc(dev_priv))
4209 refclk = 100000;
4210 else
4211 refclk = 96000;
4212 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4213 refclk = 100000;
4214 }
4215
4216 return refclk;
4217}
4218
c65d77d8
JB		 4219static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4220{
4221 struct drm_device *dev = crtc->dev;
4222 struct drm_i915_private *dev_priv = dev->dev_private;
4223 int refclk;
4224
a0c4da24
JB		 4225 if (IS_VALLEYVIEW(dev)) {
4226 refclk = vlv_get_refclk(crtc);
4227 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4228 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4229 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4230 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4231 refclk / 1000);
4232 } else if (!IS_GEN2(dev)) {
4233 refclk = 96000;
4234 } else {
4235 refclk = 48000;
4236 }
4237
4238 return refclk;
4239}
4240
7429e9d4
DV		 4241static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4242{
4243 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4244}
4245
4246static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4247{
4248 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4249}
4250
f47709a9 4251static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4252 intel_clock_t *reduced_clock)
4253{
f47709a9 4254 struct drm_device *dev = crtc->base.dev;
a7516a05 4255 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4256 int pipe = crtc->pipe;
a7516a05
JB		 4257 u32 fp, fp2 = 0;
4258
4259 if (IS_PINEVIEW(dev)) {
7429e9d4 4260 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4261 if (reduced_clock)
7429e9d4 4262 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4263 } else {
7429e9d4 4264 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4265 if (reduced_clock)
7429e9d4 4266 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4267 }
4268
4269 I915_WRITE(FP0(pipe), fp);
4270
f47709a9
DV		 4271 crtc->lowfreq_avail = false;
4272 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4273 reduced_clock && i915_powersave) {
4274 I915_WRITE(FP1(pipe), fp2);
f47709a9 4275 crtc->lowfreq_avail = true;
a7516a05
JB		 4276 } else {
4277 I915_WRITE(FP1(pipe), fp);
4278 }
4279}
4280
89b667f8
JB		 4281static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4282{
4283 u32 reg_val;
4284
4285 /*
4286 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4287 * and set it to a reasonable value instead.
4288 */
ae99258f 4289 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4290 reg_val &= 0xffffff00;
4291 reg_val |= 0x00000030;
ae99258f 4292 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4293
ae99258f 4294 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4295 reg_val &= 0x8cffffff;
4296 reg_val = 0x8c000000;
ae99258f 4297 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4298
ae99258f 4299 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4300 reg_val &= 0xffffff00;
ae99258f 4301 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4302
ae99258f 4303 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4304 reg_val &= 0x00ffffff;
4305 reg_val |= 0xb0000000;
ae99258f 4306 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4307}
4308
b551842d
DV		 4309static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4310 struct intel_link_m_n *m_n)
4311{
4312 struct drm_device *dev = crtc->base.dev;
4313 struct drm_i915_private *dev_priv = dev->dev_private;
4314 int pipe = crtc->pipe;
4315
e3b95f1e
DV		 4316 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4317 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4318 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4319 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4320}
4321
4322static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4323 struct intel_link_m_n *m_n)
4324{
4325 struct drm_device *dev = crtc->base.dev;
4326 struct drm_i915_private *dev_priv = dev->dev_private;
4327 int pipe = crtc->pipe;
4328 enum transcoder transcoder = crtc->config.cpu_transcoder;
4329
4330 if (INTEL_INFO(dev)->gen >= 5) {
4331 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4332 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4333 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4334 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4335 } else {
e3b95f1e
DV		 4336 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4337 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4338 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4339 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4340 }
4341}
4342
03afc4a2
DV		 4343static void intel_dp_set_m_n(struct intel_crtc *crtc)
4344{
4345 if (crtc->config.has_pch_encoder)
4346 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4347 else
4348 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4349}
4350
f47709a9 4351static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4352{
f47709a9 4353 struct drm_device *dev = crtc->base.dev;
a0c4da24 4354 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8
JB		 4355 struct drm_display_mode *adjusted_mode =
4356 &crtc->config.adjusted_mode;
4357 struct intel_encoder *encoder;
f47709a9 4358 int pipe = crtc->pipe;
89b667f8 4359 u32 dpll, mdiv;
a0c4da24 4360 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4361 bool is_hdmi;
198a037f 4362 u32 coreclk, reg_val, dpll_md;
a0c4da24 4363
09153000
DV		 4364 mutex_lock(&dev_priv->dpio_lock);
4365
89b667f8 4366 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4367
f47709a9
DV		 4368 bestn = crtc->config.dpll.n;
4369 bestm1 = crtc->config.dpll.m1;
4370 bestm2 = crtc->config.dpll.m2;
4371 bestp1 = crtc->config.dpll.p1;
4372 bestp2 = crtc->config.dpll.p2;
a0c4da24 4373
89b667f8
JB		 4374 /* See eDP HDMI DPIO driver vbios notes doc */
4375
4376 /* PLL B needs special handling */
4377 if (pipe)
4378 vlv_pllb_recal_opamp(dev_priv);
4379
4380 /* Set up Tx target for periodic Rcomp update */
ae99258f 4381 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4382
4383 /* Disable target IRef on PLL */
ae99258f 4384 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4385 reg_val &= 0x00ffffff;
ae99258f 4386 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4387
4388 /* Disable fast lock */
ae99258f 4389 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4390
4391 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4392 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4393 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4394 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4395 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4396
4397 /*
4398 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4399 * but we don't support that).
4400 * Note: don't use the DAC post divider as it seems unstable.
4401 */
4402 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4403 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4404
89b667f8 4405 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4406 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4407
89b667f8
JB		 4408 /* Set HBR and RBR LPF coefficients */
4409 if (adjusted_mode->clock == 162000 ||
4410 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
ae99258f 4411 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4412 0x005f0021);
4413 else
ae99258f 4414 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4415 0x00d0000f);
4416
4417 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4418 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4419 /* Use SSC source */
4420 if (!pipe)
ae99258f 4421 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4422 0x0df40000);
4423 else
ae99258f 4424 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4425 0x0df70000);
4426 } else { /* HDMI or VGA */
4427 /* Use bend source */
4428 if (!pipe)
ae99258f 4429 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4430 0x0df70000);
4431 else
ae99258f 4432 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4433 0x0df40000);
4434 }
a0c4da24 4435
ae99258f 4436 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4437 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4438 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4439 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4440 coreclk |= 0x01000000;
ae99258f 4441 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4442
ae99258f 4443 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4444
89b667f8
JB		 4445 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4446 if (encoder->pre_pll_enable)
4447 encoder->pre_pll_enable(encoder);
2a8f64ca 4448
89b667f8
JB		 4449 /* Enable DPIO clock input */
4450 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4451 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4452 if (pipe)
4453 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4454
89b667f8 4455 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4456 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4457 POSTING_READ(DPLL(pipe));
4458 udelay(150);
a0c4da24 4459
89b667f8
JB		 4460 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4461 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4462
198a037f
DV		 4463 dpll_md = 0;
4464 if (crtc->config.pixel_multiplier > 1) {
4465 dpll_md = (crtc->config.pixel_multiplier - 1)
4466 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
2a8f64ca 4467 }
198a037f
DV		 4468 I915_WRITE(DPLL_MD(pipe), dpll_md);
4469 POSTING_READ(DPLL_MD(pipe));
f47709a9 4470
89b667f8
JB		 4471 if (crtc->config.has_dp_encoder)
4472 intel_dp_set_m_n(crtc);
09153000
DV		 4473
4474 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4475}
4476
f47709a9
DV		 4477static void i9xx_update_pll(struct intel_crtc *crtc,
4478 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4479 int num_connectors)
4480{
f47709a9 4481 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4482 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4483 struct intel_encoder *encoder;
f47709a9 4484 int pipe = crtc->pipe;
eb1cbe48
DV		 4485 u32 dpll;
4486 bool is_sdvo;
f47709a9 4487 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4488
f47709a9 4489 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4490
f47709a9
DV		 4491 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4492 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4493
4494 dpll = DPLL_VGA_MODE_DIS;
4495
f47709a9 4496 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4497 dpll |= DPLLB_MODE_LVDS;
4498 else
4499 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4500
198a037f
DV		 4501 if ((crtc->config.pixel_multiplier > 1) &&
4502 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4503 dpll |= (crtc->config.pixel_multiplier - 1)
4504 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4505 }
198a037f
DV		 4506
4507 if (is_sdvo)
4508 dpll |= DPLL_DVO_HIGH_SPEED;
4509
f47709a9 4510 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4511 dpll |= DPLL_DVO_HIGH_SPEED;
4512
4513 /* compute bitmask from p1 value */
4514 if (IS_PINEVIEW(dev))
4515 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4516 else {
4517 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4518 if (IS_G4X(dev) && reduced_clock)
4519 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4520 }
4521 switch (clock->p2) {
4522 case 5:
4523 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4524 break;
4525 case 7:
4526 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4527 break;
4528 case 10:
4529 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4530 break;
4531 case 14:
4532 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4533 break;
4534 }
4535 if (INTEL_INFO(dev)->gen >= 4)
4536 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4537
09ede541 4538 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4539 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4540 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4541 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4542 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4543 else
4544 dpll |= PLL_REF_INPUT_DREFCLK;
4545
4546 dpll |= DPLL_VCO_ENABLE;
4547 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4548 POSTING_READ(DPLL(pipe));
4549 udelay(150);
4550
f47709a9 4551 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4552 if (encoder->pre_pll_enable)
4553 encoder->pre_pll_enable(encoder);
eb1cbe48 4554
f47709a9
DV		 4555 if (crtc->config.has_dp_encoder)
4556 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4557
4558 I915_WRITE(DPLL(pipe), dpll);
4559
4560 /* Wait for the clocks to stabilize. */
4561 POSTING_READ(DPLL(pipe));
4562 udelay(150);
4563
4564 if (INTEL_INFO(dev)->gen >= 4) {
198a037f
DV		 4565 u32 dpll_md = 0;
4566 if (crtc->config.pixel_multiplier > 1) {
4567 dpll_md = (crtc->config.pixel_multiplier - 1)
4568 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
eb1cbe48 4569 }
198a037f 4570 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4571 } else {
4572 /* The pixel multiplier can only be updated once the
4573 * DPLL is enabled and the clocks are stable.
4574 *
4575 * So write it again.
4576 */
4577 I915_WRITE(DPLL(pipe), dpll);
4578 }
4579}
4580
f47709a9 4581static void i8xx_update_pll(struct intel_crtc *crtc,
eb1cbe48 4582 struct drm_display_mode *adjusted_mode,
f47709a9 4583 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4584 int num_connectors)
4585{
f47709a9 4586 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4587 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4588 struct intel_encoder *encoder;
f47709a9 4589 int pipe = crtc->pipe;
eb1cbe48 4590 u32 dpll;
f47709a9 4591 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4592
f47709a9 4593 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4594
eb1cbe48
DV		 4595 dpll = DPLL_VGA_MODE_DIS;
4596
f47709a9 4597 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4598 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4599 } else {
4600 if (clock->p1 == 2)
4601 dpll |= PLL_P1_DIVIDE_BY_TWO;
4602 else
4603 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4604 if (clock->p2 == 4)
4605 dpll |= PLL_P2_DIVIDE_BY_4;
4606 }
4607
f47709a9 4608 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4609 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4610 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4611 else
4612 dpll |= PLL_REF_INPUT_DREFCLK;
4613
4614 dpll |= DPLL_VCO_ENABLE;
4615 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4616 POSTING_READ(DPLL(pipe));
4617 udelay(150);
4618
f47709a9 4619 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4620 if (encoder->pre_pll_enable)
4621 encoder->pre_pll_enable(encoder);
eb1cbe48 4622
5b5896e4
DV		 4623 I915_WRITE(DPLL(pipe), dpll);
4624
4625 /* Wait for the clocks to stabilize. */
4626 POSTING_READ(DPLL(pipe));
4627 udelay(150);
4628
eb1cbe48
DV		 4629 /* The pixel multiplier can only be updated once the
4630 * DPLL is enabled and the clocks are stable.
4631 *
4632 * So write it again.
4633 */
4634 I915_WRITE(DPLL(pipe), dpll);
4635}
4636
b0e77b9c
PZ		 4637static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4638 struct drm_display_mode *mode,
4639 struct drm_display_mode *adjusted_mode)
4640{
4641 struct drm_device *dev = intel_crtc->base.dev;
4642 struct drm_i915_private *dev_priv = dev->dev_private;
4643 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4644 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4d8a62ea
DV		 4645 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4646
4647 /* We need to be careful not to changed the adjusted mode, for otherwise
4648 * the hw state checker will get angry at the mismatch. */
4649 crtc_vtotal = adjusted_mode->crtc_vtotal;
4650 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4651
4652 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4653 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4654 crtc_vtotal -= 1;
4655 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4656 vsyncshift = adjusted_mode->crtc_hsync_start
4657 - adjusted_mode->crtc_htotal / 2;
4658 } else {
4659 vsyncshift = 0;
4660 }
4661
4662 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4663 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4664
fe2b8f9d 4665 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4666 (adjusted_mode->crtc_hdisplay - 1) |
4667 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4668 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4669 (adjusted_mode->crtc_hblank_start - 1) |
4670 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4671 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4672 (adjusted_mode->crtc_hsync_start - 1) |
4673 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4674
fe2b8f9d 4675 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4676 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4677 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4678 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4679 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4680 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4681 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4682 (adjusted_mode->crtc_vsync_start - 1) |
4683 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4684
b5e508d4
PZ		 4685 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4686 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4687 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4688 * bits. */
4689 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4690 (pipe == PIPE_B || pipe == PIPE_C))
4691 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4692
b0e77b9c
PZ		 4693 /* pipesrc controls the size that is scaled from, which should
4694 * always be the user's requested size.
4695 */
4696 I915_WRITE(PIPESRC(pipe),
4697 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4698}
4699
1bd1bd80
DV		 4700static void intel_get_pipe_timings(struct intel_crtc *crtc,
4701 struct intel_crtc_config *pipe_config)
4702{
4703 struct drm_device *dev = crtc->base.dev;
4704 struct drm_i915_private *dev_priv = dev->dev_private;
4705 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4706 uint32_t tmp;
4707
4708 tmp = I915_READ(HTOTAL(cpu_transcoder));
4709 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4710 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4711 tmp = I915_READ(HBLANK(cpu_transcoder));
4712 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4713 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4714 tmp = I915_READ(HSYNC(cpu_transcoder));
4715 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4716 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4717
4718 tmp = I915_READ(VTOTAL(cpu_transcoder));
4719 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4720 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4721 tmp = I915_READ(VBLANK(cpu_transcoder));
4722 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4723 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4724 tmp = I915_READ(VSYNC(cpu_transcoder));
4725 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4726 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4727
4728 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4729 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4730 pipe_config->adjusted_mode.crtc_vtotal += 1;
4731 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4732 }
4733
4734 tmp = I915_READ(PIPESRC(crtc->pipe));
4735 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4736 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4737}
4738
84b046f3
DV		 4739static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4740{
4741 struct drm_device *dev = intel_crtc->base.dev;
4742 struct drm_i915_private *dev_priv = dev->dev_private;
4743 uint32_t pipeconf;
4744
4745 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4746
4747 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4748 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4749 * core speed.
4750 *
4751 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4752 * pipe == 0 check?
4753 */
4754 if (intel_crtc->config.requested_mode.clock >
4755 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4756 pipeconf |= PIPECONF_DOUBLE_WIDE;
4757 else
4758 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4759 }
4760
ff9ce46e
DV		 4761 /* only g4x and later have fancy bpc/dither controls */
4762 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4763 pipeconf &= ~(PIPECONF_BPC_MASK |
4764 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4765
4766 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4767 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4768 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4769 PIPECONF_DITHER_TYPE_SP;
84b046f3 4770
ff9ce46e
DV		 4771 switch (intel_crtc->config.pipe_bpp) {
4772 case 18:
4773 pipeconf |= PIPECONF_6BPC;
4774 break;
4775 case 24:
4776 pipeconf |= PIPECONF_8BPC;
4777 break;
4778 case 30:
4779 pipeconf |= PIPECONF_10BPC;
4780 break;
4781 default:
4782 /* Case prevented by intel_choose_pipe_bpp_dither. */
4783 BUG();
84b046f3
DV		 4784 }
4785 }
4786
4787 if (HAS_PIPE_CXSR(dev)) {
4788 if (intel_crtc->lowfreq_avail) {
4789 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4790 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4791 } else {
4792 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4793 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4794 }
4795 }
4796
4797 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4798 if (!IS_GEN2(dev) &&
4799 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4800 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4801 else
4802 pipeconf |= PIPECONF_PROGRESSIVE;
4803
9c8e09b7
VS		 4804 if (IS_VALLEYVIEW(dev)) {
4805 if (intel_crtc->config.limited_color_range)
4806 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4807 else
4808 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4809 }
4810
84b046f3
DV		 4811 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4812 POSTING_READ(PIPECONF(intel_crtc->pipe));
4813}
4814
f564048e 4815static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4816 int x, int y,
94352cf9 4817 struct drm_framebuffer *fb)
79e53945
JB		 4818{
4819 struct drm_device *dev = crtc->dev;
4820 struct drm_i915_private *dev_priv = dev->dev_private;
4821 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4822 struct drm_display_mode *adjusted_mode =
4823 &intel_crtc->config.adjusted_mode;
4824 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4825 int pipe = intel_crtc->pipe;
80824003 4826 int plane = intel_crtc->plane;
c751ce4f 4827 int refclk, num_connectors = 0;
652c393a 4828 intel_clock_t clock, reduced_clock;
84b046f3 4829 u32 dspcntr;
a16af721
DV		 4830 bool ok, has_reduced_clock = false;
4831 bool is_lvds = false;
5eddb70b 4832 struct intel_encoder *encoder;
d4906093 4833 const intel_limit_t *limit;
5c3b82e2 4834 int ret;
79e53945 4835
6c2b7c12 4836 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4837 switch (encoder->type) {
79e53945
JB		 4838 case INTEL_OUTPUT_LVDS:
4839 is_lvds = true;
4840 break;
79e53945 4841 }
43565a06 4842
c751ce4f 4843 num_connectors++;
79e53945
JB		 4844 }
4845
c65d77d8 4846 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4847
d4906093
ML		 4848 /*
4849 * Returns a set of divisors for the desired target clock with the given
4850 * refclk, or FALSE. The returned values represent the clock equation:
4851 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4852 */
1b894b59 4853 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4854 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4855 &clock);
79e53945
JB		 4856 if (!ok) {
4857 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4858 return -EINVAL;
79e53945
JB		 4859 }
4860
cda4b7d3 4861 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4862 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4863
ddc9003c 4864 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4865 /*
4866 * Ensure we match the reduced clock's P to the target clock.
4867 * If the clocks don't match, we can't switch the display clock
4868 * by using the FP0/FP1. In such case we will disable the LVDS
4869 * downclock feature.
4870 */
ddc9003c 4871 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4872 dev_priv->lvds_downclock,
4873 refclk,
cec2f356 4874 &clock,
5eddb70b 4875 &reduced_clock);
7026d4ac 4876 }
f47709a9
DV		 4877 /* Compat-code for transition, will disappear. */
4878 if (!intel_crtc->config.clock_set) {
4879 intel_crtc->config.dpll.n = clock.n;
4880 intel_crtc->config.dpll.m1 = clock.m1;
4881 intel_crtc->config.dpll.m2 = clock.m2;
4882 intel_crtc->config.dpll.p1 = clock.p1;
4883 intel_crtc->config.dpll.p2 = clock.p2;
4884 }
7026d4ac 4885
eb1cbe48 4886 if (IS_GEN2(dev))
f47709a9 4887 i8xx_update_pll(intel_crtc, adjusted_mode,
2a8f64ca
VP		 4888 has_reduced_clock ? &reduced_clock : NULL,
4889 num_connectors);
a0c4da24 4890 else if (IS_VALLEYVIEW(dev))
f47709a9 4891 vlv_update_pll(intel_crtc);
79e53945 4892 else
f47709a9 4893 i9xx_update_pll(intel_crtc,
eb1cbe48 4894 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4895 num_connectors);
79e53945 4896
79e53945
JB		 4897 /* Set up the display plane register */
4898 dspcntr = DISPPLANE_GAMMA_ENABLE;
4899
da6ecc5d
JB		 4900 if (!IS_VALLEYVIEW(dev)) {
4901 if (pipe == 0)
4902 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4903 else
4904 dspcntr |= DISPPLANE_SEL_PIPE_B;
4905 }
79e53945 4906
b0e77b9c 4907 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4908
4909 /* pipesrc and dspsize control the size that is scaled from,
4910 * which should always be the user's requested size.
79e53945 4911 */
929c77fb
EA		 4912 I915_WRITE(DSPSIZE(plane),
4913 ((mode->vdisplay - 1) << 16) |
4914 (mode->hdisplay - 1));
4915 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4916
84b046f3
DV		 4917 i9xx_set_pipeconf(intel_crtc);
4918
f564048e
EA		 4919 I915_WRITE(DSPCNTR(plane), dspcntr);
4920 POSTING_READ(DSPCNTR(plane));
4921
94352cf9 4922 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4923
4924 intel_update_watermarks(dev);
4925
f564048e
EA		 4926 return ret;
4927}
4928
2fa2fe9a
DV		 4929static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4930 struct intel_crtc_config *pipe_config)
4931{
4932 struct drm_device *dev = crtc->base.dev;
4933 struct drm_i915_private *dev_priv = dev->dev_private;
4934 uint32_t tmp;
4935
4936 tmp = I915_READ(PFIT_CONTROL);
4937
4938 if (INTEL_INFO(dev)->gen < 4) {
4939 if (crtc->pipe != PIPE_B)
4940 return;
4941
4942 /* gen2/3 store dither state in pfit control, needs to match */
4943 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4944 } else {
4945 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4946 return;
4947 }
4948
4949 if (!(tmp & PFIT_ENABLE))
4950 return;
4951
4952 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4953 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4954 if (INTEL_INFO(dev)->gen < 5)
4955 pipe_config->gmch_pfit.lvds_border_bits =
4956 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4957}
4958
0e8ffe1b
DV		 4959static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4960 struct intel_crtc_config *pipe_config)
4961{
4962 struct drm_device *dev = crtc->base.dev;
4963 struct drm_i915_private *dev_priv = dev->dev_private;
4964 uint32_t tmp;
4965
eccb140b
DV		 4966 pipe_config->cpu_transcoder = crtc->pipe;
4967
0e8ffe1b
DV		 4968 tmp = I915_READ(PIPECONF(crtc->pipe));
4969 if (!(tmp & PIPECONF_ENABLE))
4970 return false;
4971
1bd1bd80
DV		 4972 intel_get_pipe_timings(crtc, pipe_config);
4973
2fa2fe9a
DV		 4974 i9xx_get_pfit_config(crtc, pipe_config);
4975
0e8ffe1b
DV		 4976 return true;
4977}
4978
dde86e2d 4979static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4980{
4981 struct drm_i915_private *dev_priv = dev->dev_private;
4982 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4983 struct intel_encoder *encoder;
74cfd7ac 4984 u32 val, final;
13d83a67 4985 bool has_lvds = false;
199e5d79 4986 bool has_cpu_edp = false;
199e5d79 4987 bool has_panel = false;
99eb6a01
KP		 4988 bool has_ck505 = false;
4989 bool can_ssc = false;
13d83a67
JB		 4990
4991 /* We need to take the global config into account */
199e5d79
KP		 4992 list_for_each_entry(encoder, &mode_config->encoder_list,
4993 base.head) {
4994 switch (encoder->type) {
4995 case INTEL_OUTPUT_LVDS:
4996 has_panel = true;
4997 has_lvds = true;
4998 break;
4999 case INTEL_OUTPUT_EDP:
5000 has_panel = true;
2de6905f 5001 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5002 has_cpu_edp = true;
5003 break;
13d83a67
JB		 5004 }
5005 }
5006
99eb6a01 5007 if (HAS_PCH_IBX(dev)) {
41aa3448 5008 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5009 can_ssc = has_ck505;
5010 } else {
5011 has_ck505 = false;
5012 can_ssc = true;
5013 }
5014
2de6905f
ID		 5015 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5016 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5017
5018 /* Ironlake: try to setup display ref clock before DPLL
5019 * enabling. This is only under driver's control after
5020 * PCH B stepping, previous chipset stepping should be
5021 * ignoring this setting.
5022 */
74cfd7ac
CW		 5023 val = I915_READ(PCH_DREF_CONTROL);
5024
5025 /* As we must carefully and slowly disable/enable each source in turn,
5026 * compute the final state we want first and check if we need to
5027 * make any changes at all.
5028 */
5029 final = val;
5030 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5031 if (has_ck505)
5032 final |= DREF_NONSPREAD_CK505_ENABLE;
5033 else
5034 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5035
5036 final &= ~DREF_SSC_SOURCE_MASK;
5037 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5038 final &= ~DREF_SSC1_ENABLE;
5039
5040 if (has_panel) {
5041 final |= DREF_SSC_SOURCE_ENABLE;
5042
5043 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5044 final |= DREF_SSC1_ENABLE;
5045
5046 if (has_cpu_edp) {
5047 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5048 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5049 else
5050 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5051 } else
5052 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5053 } else {
5054 final |= DREF_SSC_SOURCE_DISABLE;
5055 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5056 }
5057
5058 if (final == val)
5059 return;
5060
13d83a67 5061 /* Always enable nonspread source */
74cfd7ac 5062 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5063
99eb6a01 5064 if (has_ck505)
74cfd7ac 5065 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5066 else
74cfd7ac 5067 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5068
199e5d79 5069 if (has_panel) {
74cfd7ac
CW		 5070 val &= ~DREF_SSC_SOURCE_MASK;
5071 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5072
199e5d79 5073 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5074 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5075 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5076 val |= DREF_SSC1_ENABLE;
e77166b5 5077 } else
74cfd7ac 5078 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5079
5080 /* Get SSC going before enabling the outputs */
74cfd7ac 5081 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5082 POSTING_READ(PCH_DREF_CONTROL);
5083 udelay(200);
5084
74cfd7ac 5085 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5086
5087 /* Enable CPU source on CPU attached eDP */
199e5d79 5088 if (has_cpu_edp) {
99eb6a01 5089 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5090 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5091 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5092 }
13d83a67 5093 else
74cfd7ac 5094 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5095 } else
74cfd7ac 5096 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5097
74cfd7ac 5098 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5099 POSTING_READ(PCH_DREF_CONTROL);
5100 udelay(200);
5101 } else {
5102 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5103
74cfd7ac 5104 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5105
5106 /* Turn off CPU output */
74cfd7ac 5107 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5108
74cfd7ac 5109 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5110 POSTING_READ(PCH_DREF_CONTROL);
5111 udelay(200);
5112
5113 /* Turn off the SSC source */
74cfd7ac
CW		 5114 val &= ~DREF_SSC_SOURCE_MASK;
5115 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5116
5117 /* Turn off SSC1 */
74cfd7ac 5118 val &= ~DREF_SSC1_ENABLE;
199e5d79 5119
74cfd7ac 5120 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5121 POSTING_READ(PCH_DREF_CONTROL);
5122 udelay(200);
5123 }
74cfd7ac
CW		 5124
5125 BUG_ON(val != final);
13d83a67
JB		 5126}
5127
dde86e2d
PZ		 5128/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5129static void lpt_init_pch_refclk(struct drm_device *dev)
5130{
5131 struct drm_i915_private *dev_priv = dev->dev_private;
5132 struct drm_mode_config *mode_config = &dev->mode_config;
5133 struct intel_encoder *encoder;
5134 bool has_vga = false;
5135 bool is_sdv = false;
5136 u32 tmp;
5137
5138 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5139 switch (encoder->type) {
5140 case INTEL_OUTPUT_ANALOG:
5141 has_vga = true;
5142 break;
5143 }
5144 }
5145
5146 if (!has_vga)
5147 return;
5148
c00db246
DV		 5149 mutex_lock(&dev_priv->dpio_lock);
5150
dde86e2d
PZ		 5151 /* XXX: Rip out SDV support once Haswell ships for real. */
5152 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5153 is_sdv = true;
5154
5155 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5156 tmp &= ~SBI_SSCCTL_DISABLE;
5157 tmp |= SBI_SSCCTL_PATHALT;
5158 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5159
5160 udelay(24);
5161
5162 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5163 tmp &= ~SBI_SSCCTL_PATHALT;
5164 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5165
5166 if (!is_sdv) {
5167 tmp = I915_READ(SOUTH_CHICKEN2);
5168 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5169 I915_WRITE(SOUTH_CHICKEN2, tmp);
5170
5171 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5172 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5173 DRM_ERROR("FDI mPHY reset assert timeout\n");
5174
5175 tmp = I915_READ(SOUTH_CHICKEN2);
5176 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5177 I915_WRITE(SOUTH_CHICKEN2, tmp);
5178
5179 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5180 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5181 100))
5182 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5183 }
5184
5185 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5186 tmp &= ~(0xFF << 24);
5187 tmp |= (0x12 << 24);
5188 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5189
dde86e2d
PZ		 5190 if (is_sdv) {
5191 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5192 tmp |= 0x7FFF;
5193 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5194 }
5195
5196 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5197 tmp |= (1 << 11);
5198 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5199
5200 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5201 tmp |= (1 << 11);
5202 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5203
5204 if (is_sdv) {
5205 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5206 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5207 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5208
5209 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5210 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5211 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5212
5213 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5214 tmp |= (0x3F << 8);
5215 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5216
5217 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5218 tmp |= (0x3F << 8);
5219 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5220 }
5221
5222 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5223 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5224 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5225
5226 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5227 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5228 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5229
5230 if (!is_sdv) {
5231 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5232 tmp &= ~(7 << 13);
5233 tmp |= (5 << 13);
5234 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5235
5236 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5237 tmp &= ~(7 << 13);
5238 tmp |= (5 << 13);
5239 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5240 }
5241
5242 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5243 tmp &= ~0xFF;
5244 tmp |= 0x1C;
5245 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5246
5247 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5248 tmp &= ~0xFF;
5249 tmp |= 0x1C;
5250 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5251
5252 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5253 tmp &= ~(0xFF << 16);
5254 tmp |= (0x1C << 16);
5255 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5256
5257 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5258 tmp &= ~(0xFF << 16);
5259 tmp |= (0x1C << 16);
5260 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5261
5262 if (!is_sdv) {
5263 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5264 tmp |= (1 << 27);
5265 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5266
5267 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5268 tmp |= (1 << 27);
5269 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5270
5271 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5272 tmp &= ~(0xF << 28);
5273 tmp |= (4 << 28);
5274 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5275
5276 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5277 tmp &= ~(0xF << 28);
5278 tmp |= (4 << 28);
5279 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5280 }
5281
5282 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5283 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5284 tmp |= SBI_DBUFF0_ENABLE;
5285 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5286
5287 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5288}
5289
5290/*
5291 * Initialize reference clocks when the driver loads
5292 */
5293void intel_init_pch_refclk(struct drm_device *dev)
5294{
5295 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5296 ironlake_init_pch_refclk(dev);
5297 else if (HAS_PCH_LPT(dev))
5298 lpt_init_pch_refclk(dev);
5299}
5300
d9d444cb
JB		 5301static int ironlake_get_refclk(struct drm_crtc *crtc)
5302{
5303 struct drm_device *dev = crtc->dev;
5304 struct drm_i915_private *dev_priv = dev->dev_private;
5305 struct intel_encoder *encoder;
d9d444cb
JB		 5306 int num_connectors = 0;
5307 bool is_lvds = false;
5308
6c2b7c12 5309 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5310 switch (encoder->type) {
5311 case INTEL_OUTPUT_LVDS:
5312 is_lvds = true;
5313 break;
d9d444cb
JB		 5314 }
5315 num_connectors++;
5316 }
5317
5318 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5319 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5320 dev_priv->vbt.lvds_ssc_freq);
5321 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5322 }
5323
5324 return 120000;
5325}
5326
6ff93609 5327static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5328{
c8203565 5329 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5331 int pipe = intel_crtc->pipe;
c8203565
PZ		 5332 uint32_t val;
5333
5334 val = I915_READ(PIPECONF(pipe));
5335
dfd07d72 5336 val &= ~PIPECONF_BPC_MASK;
965e0c48 5337 switch (intel_crtc->config.pipe_bpp) {
c8203565 5338 case 18:
dfd07d72 5339 val |= PIPECONF_6BPC;
c8203565
PZ		 5340 break;
5341 case 24:
dfd07d72 5342 val |= PIPECONF_8BPC;
c8203565
PZ		 5343 break;
5344 case 30:
dfd07d72 5345 val |= PIPECONF_10BPC;
c8203565
PZ		 5346 break;
5347 case 36:
dfd07d72 5348 val |= PIPECONF_12BPC;
c8203565
PZ		 5349 break;
5350 default:
cc769b62
PZ		 5351 /* Case prevented by intel_choose_pipe_bpp_dither. */
5352 BUG();
c8203565
PZ		 5353 }
5354
5355 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5356 if (intel_crtc->config.dither)
c8203565
PZ		 5357 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5358
5359 val &= ~PIPECONF_INTERLACE_MASK;
6ff93609 5360 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5361 val |= PIPECONF_INTERLACED_ILK;
5362 else
5363 val |= PIPECONF_PROGRESSIVE;
5364
50f3b016 5365 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5366 val |= PIPECONF_COLOR_RANGE_SELECT;
5367 else
5368 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5369
c8203565
PZ		 5370 I915_WRITE(PIPECONF(pipe), val);
5371 POSTING_READ(PIPECONF(pipe));
5372}
5373
86d3efce
VS		 5374/*
5375 * Set up the pipe CSC unit.
5376 *
5377 * Currently only full range RGB to limited range RGB conversion
5378 * is supported, but eventually this should handle various
5379 * RGB<->YCbCr scenarios as well.
5380 */
50f3b016 5381static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5382{
5383 struct drm_device *dev = crtc->dev;
5384 struct drm_i915_private *dev_priv = dev->dev_private;
5385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5386 int pipe = intel_crtc->pipe;
5387 uint16_t coeff = 0x7800; /* 1.0 */
5388
5389 /*
5390 * TODO: Check what kind of values actually come out of the pipe
5391 * with these coeff/postoff values and adjust to get the best
5392 * accuracy. Perhaps we even need to take the bpc value into
5393 * consideration.
5394 */
5395
50f3b016 5396 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5397 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5398
5399 /*
5400 * GY/GU and RY/RU should be the other way around according
5401 * to BSpec, but reality doesn't agree. Just set them up in
5402 * a way that results in the correct picture.
5403 */
5404 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5405 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5406
5407 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5408 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5409
5410 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5411 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5412
5413 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5414 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5415 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5416
5417 if (INTEL_INFO(dev)->gen > 6) {
5418 uint16_t postoff = 0;
5419
50f3b016 5420 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5421 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5422
5423 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5424 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5425 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5426
5427 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5428 } else {
5429 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5430
50f3b016 5431 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5432 mode |= CSC_BLACK_SCREEN_OFFSET;
5433
5434 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5435 }
5436}
5437
6ff93609 5438static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5439{
5440 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5442 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5443 uint32_t val;
5444
702e7a56 5445 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5446
5447 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5448 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5449 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5450
5451 val &= ~PIPECONF_INTERLACE_MASK_HSW;
6ff93609 5452 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5453 val |= PIPECONF_INTERLACED_ILK;
5454 else
5455 val |= PIPECONF_PROGRESSIVE;
5456
702e7a56
PZ		 5457 I915_WRITE(PIPECONF(cpu_transcoder), val);
5458 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5459}
5460
6591c6e4
PZ		 5461static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5462 struct drm_display_mode *adjusted_mode,
5463 intel_clock_t *clock,
5464 bool *has_reduced_clock,
5465 intel_clock_t *reduced_clock)
5466{
5467 struct drm_device *dev = crtc->dev;
5468 struct drm_i915_private *dev_priv = dev->dev_private;
5469 struct intel_encoder *intel_encoder;
5470 int refclk;
d4906093 5471 const intel_limit_t *limit;
a16af721 5472 bool ret, is_lvds = false;
79e53945 5473
6591c6e4
PZ		 5474 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5475 switch (intel_encoder->type) {
79e53945
JB		 5476 case INTEL_OUTPUT_LVDS:
5477 is_lvds = true;
5478 break;
79e53945
JB		 5479 }
5480 }
5481
d9d444cb 5482 refclk = ironlake_get_refclk(crtc);
79e53945 5483
d4906093
ML		 5484 /*
5485 * Returns a set of divisors for the desired target clock with the given
5486 * refclk, or FALSE. The returned values represent the clock equation:
5487 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5488 */
1b894b59 5489 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5490 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5491 clock);
5492 if (!ret)
5493 return false;
cda4b7d3 5494
ddc9003c 5495 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5496 /*
5497 * Ensure we match the reduced clock's P to the target clock.
5498 * If the clocks don't match, we can't switch the display clock
5499 * by using the FP0/FP1. In such case we will disable the LVDS
5500 * downclock feature.
5501 */
6591c6e4
PZ		 5502 *has_reduced_clock = limit->find_pll(limit, crtc,
5503 dev_priv->lvds_downclock,
5504 refclk,
5505 clock,
5506 reduced_clock);
652c393a 5507 }
61e9653f 5508
6591c6e4
PZ		 5509 return true;
5510}
5511
01a415fd
DV		 5512static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5513{
5514 struct drm_i915_private *dev_priv = dev->dev_private;
5515 uint32_t temp;
5516
5517 temp = I915_READ(SOUTH_CHICKEN1);
5518 if (temp & FDI_BC_BIFURCATION_SELECT)
5519 return;
5520
5521 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5522 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5523
5524 temp |= FDI_BC_BIFURCATION_SELECT;
5525 DRM_DEBUG_KMS("enabling fdi C rx\n");
5526 I915_WRITE(SOUTH_CHICKEN1, temp);
5527 POSTING_READ(SOUTH_CHICKEN1);
5528}
5529
ebfd86fd
DV		 5530static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5531{
5532 struct drm_device *dev = intel_crtc->base.dev;
5533 struct drm_i915_private *dev_priv = dev->dev_private;
5534
5535 switch (intel_crtc->pipe) {
5536 case PIPE_A:
5537 break;
5538 case PIPE_B:
5539 if (intel_crtc->config.fdi_lanes > 2)
5540 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5541 else
5542 cpt_enable_fdi_bc_bifurcation(dev);
5543
5544 break;
5545 case PIPE_C:
01a415fd
DV		 5546 cpt_enable_fdi_bc_bifurcation(dev);
5547
ebfd86fd 5548 break;
01a415fd
DV		 5549 default:
5550 BUG();
5551 }
5552}
5553
d4b1931c
PZ		 5554int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5555{
5556 /*
5557 * Account for spread spectrum to avoid
5558 * oversubscribing the link. Max center spread
5559 * is 2.5%; use 5% for safety's sake.
5560 */
5561 u32 bps = target_clock * bpp * 21 / 20;
5562 return bps / (link_bw * 8) + 1;
5563}
5564
7429e9d4
DV		 5565static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5566{
5567 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5568}
5569
de13a2e3 5570static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5571 u32 *fp,
9a7c7890 5572 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5573{
de13a2e3 5574 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5575 struct drm_device *dev = crtc->dev;
5576 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5577 struct intel_encoder *intel_encoder;
5578 uint32_t dpll;
6cc5f341 5579 int factor, num_connectors = 0;
09ede541 5580 bool is_lvds = false, is_sdvo = false;
79e53945 5581
de13a2e3
PZ		 5582 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5583 switch (intel_encoder->type) {
79e53945
JB		 5584 case INTEL_OUTPUT_LVDS:
5585 is_lvds = true;
5586 break;
5587 case INTEL_OUTPUT_SDVO:
7d57382e 5588 case INTEL_OUTPUT_HDMI:
79e53945
JB		 5589 is_sdvo = true;
5590 break;
79e53945 5591 }
43565a06 5592
c751ce4f 5593 num_connectors++;
79e53945 5594 }
79e53945 5595
c1858123 5596 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5597 factor = 21;
5598 if (is_lvds) {
5599 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5600 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5601 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5602 factor = 25;
09ede541 5603 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5604 factor = 20;
c1858123 5605
7429e9d4 5606 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5607 *fp |= FP_CB_TUNE;
2c07245f 5608
9a7c7890
DV		 5609 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5610 *fp2 |= FP_CB_TUNE;
5611
5eddb70b 5612 dpll = 0;
2c07245f 5613
a07d6787
EA		 5614 if (is_lvds)
5615 dpll |= DPLLB_MODE_LVDS;
5616 else
5617 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f
DV		 5618
5619 if (intel_crtc->config.pixel_multiplier > 1) {
5620 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5621 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
a07d6787 5622 }
198a037f
DV		 5623
5624 if (is_sdvo)
5625 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5626 if (intel_crtc->config.has_dp_encoder)
a07d6787 5627 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5628
a07d6787 5629 /* compute bitmask from p1 value */
7429e9d4 5630 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5631 /* also FPA1 */
7429e9d4 5632 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5633
7429e9d4 5634 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5635 case 5:
5636 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5637 break;
5638 case 7:
5639 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5640 break;
5641 case 10:
5642 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5643 break;
5644 case 14:
5645 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5646 break;
79e53945
JB		 5647 }
5648
b4c09f3b 5649 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5650 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5651 else
5652 dpll |= PLL_REF_INPUT_DREFCLK;
5653
de13a2e3
PZ		 5654 return dpll;
5655}
5656
5657static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5658 int x, int y,
5659 struct drm_framebuffer *fb)
5660{
5661 struct drm_device *dev = crtc->dev;
5662 struct drm_i915_private *dev_priv = dev->dev_private;
5663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5664 struct drm_display_mode *adjusted_mode =
5665 &intel_crtc->config.adjusted_mode;
5666 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5667 int pipe = intel_crtc->pipe;
5668 int plane = intel_crtc->plane;
5669 int num_connectors = 0;
5670 intel_clock_t clock, reduced_clock;
cbbab5bd 5671 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5672 bool ok, has_reduced_clock = false;
8b47047b 5673 bool is_lvds = false;
de13a2e3 5674 struct intel_encoder *encoder;
de13a2e3 5675 int ret;
de13a2e3
PZ		 5676
5677 for_each_encoder_on_crtc(dev, crtc, encoder) {
5678 switch (encoder->type) {
5679 case INTEL_OUTPUT_LVDS:
5680 is_lvds = true;
5681 break;
de13a2e3
PZ		 5682 }
5683
5684 num_connectors++;
a07d6787 5685 }
79e53945 5686
5dc5298b
PZ		 5687 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5688 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5689
de13a2e3
PZ		 5690 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5691 &has_reduced_clock, &reduced_clock);
5692 if (!ok) {
5693 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5694 return -EINVAL;
79e53945 5695 }
f47709a9
DV		 5696 /* Compat-code for transition, will disappear. */
5697 if (!intel_crtc->config.clock_set) {
5698 intel_crtc->config.dpll.n = clock.n;
5699 intel_crtc->config.dpll.m1 = clock.m1;
5700 intel_crtc->config.dpll.m2 = clock.m2;
5701 intel_crtc->config.dpll.p1 = clock.p1;
5702 intel_crtc->config.dpll.p2 = clock.p2;
5703 }
79e53945 5704
de13a2e3
PZ		 5705 /* Ensure that the cursor is valid for the new mode before changing... */
5706 intel_crtc_update_cursor(crtc, true);
5707
5dc5298b 5708 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5709 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5710 struct intel_pch_pll *pll;
4b645f14 5711
7429e9d4 5712 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5713 if (has_reduced_clock)
7429e9d4 5714 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5715
7429e9d4 5716 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5717 &fp, &reduced_clock,
5718 has_reduced_clock ? &fp2 : NULL);
5719
ee7b9f93
JB		 5720 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5721 if (pll == NULL) {
84f44ce7
VS		 5722 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5723 pipe_name(pipe));
4b645f14
JB		 5724 return -EINVAL;
5725 }
ee7b9f93
JB		 5726 } else
5727 intel_put_pch_pll(intel_crtc);
79e53945 5728
03afc4a2
DV		 5729 if (intel_crtc->config.has_dp_encoder)
5730 intel_dp_set_m_n(intel_crtc);
79e53945 5731
dafd226c
DV		 5732 for_each_encoder_on_crtc(dev, crtc, encoder)
5733 if (encoder->pre_pll_enable)
5734 encoder->pre_pll_enable(encoder);
79e53945 5735
ee7b9f93
JB		 5736 if (intel_crtc->pch_pll) {
5737 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5738
32f9d658 5739 /* Wait for the clocks to stabilize. */
ee7b9f93 5740 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5741 udelay(150);
5742
8febb297
EA		 5743 /* The pixel multiplier can only be updated once the
5744 * DPLL is enabled and the clocks are stable.
5745 *
5746 * So write it again.
5747 */
ee7b9f93 5748 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5749 }
79e53945 5750
5eddb70b 5751 intel_crtc->lowfreq_avail = false;
ee7b9f93 5752 if (intel_crtc->pch_pll) {
4b645f14 5753 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5754 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5755 intel_crtc->lowfreq_avail = true;
4b645f14 5756 } else {
ee7b9f93 5757 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5758 }
5759 }
5760
b0e77b9c 5761 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5762
ca3a0ff8 5763 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5764 intel_cpu_transcoder_set_m_n(intel_crtc,
5765 &intel_crtc->config.fdi_m_n);
5766 }
2c07245f 5767
ebfd86fd
DV		 5768 if (IS_IVYBRIDGE(dev))
5769 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
2c07245f 5770
6ff93609 5771 ironlake_set_pipeconf(crtc);
79e53945 5772
a1f9e77e
PZ		 5773 /* Set up the display plane register */
5774 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5775 POSTING_READ(DSPCNTR(plane));
79e53945 5776
94352cf9 5777 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5778
5779 intel_update_watermarks(dev);
5780
1857e1da 5781 return ret;
79e53945
JB		 5782}
5783
72419203
DV		 5784static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5785 struct intel_crtc_config *pipe_config)
5786{
5787 struct drm_device *dev = crtc->base.dev;
5788 struct drm_i915_private *dev_priv = dev->dev_private;
5789 enum transcoder transcoder = pipe_config->cpu_transcoder;
5790
5791 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5792 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5793 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5794 & ~TU_SIZE_MASK;
5795 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5796 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5797 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5798}
5799
2fa2fe9a
DV		 5800static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5801 struct intel_crtc_config *pipe_config)
5802{
5803 struct drm_device *dev = crtc->base.dev;
5804 struct drm_i915_private *dev_priv = dev->dev_private;
5805 uint32_t tmp;
5806
5807 tmp = I915_READ(PF_CTL(crtc->pipe));
5808
5809 if (tmp & PF_ENABLE) {
5810 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5811 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5812 }
5813}
5814
0e8ffe1b
DV		 5815static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5816 struct intel_crtc_config *pipe_config)
5817{
5818 struct drm_device *dev = crtc->base.dev;
5819 struct drm_i915_private *dev_priv = dev->dev_private;
5820 uint32_t tmp;
5821
eccb140b
DV		 5822 pipe_config->cpu_transcoder = crtc->pipe;
5823
0e8ffe1b
DV		 5824 tmp = I915_READ(PIPECONF(crtc->pipe));
5825 if (!(tmp & PIPECONF_ENABLE))
5826 return false;
5827
ab9412ba 5828 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
88adfff1
DV		 5829 pipe_config->has_pch_encoder = true;
5830
627eb5a3
DV		 5831 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5832 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5833 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5834
5835 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5836 }
5837
1bd1bd80
DV		 5838 intel_get_pipe_timings(crtc, pipe_config);
5839
2fa2fe9a
DV		 5840 ironlake_get_pfit_config(crtc, pipe_config);
5841
0e8ffe1b
DV		 5842 return true;
5843}
5844
d6dd9eb1
DV		 5845static void haswell_modeset_global_resources(struct drm_device *dev)
5846{
d6dd9eb1
DV		 5847 bool enable = false;
5848 struct intel_crtc *crtc;
d6dd9eb1
DV		 5849
5850 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 5851 if (!crtc->base.enabled)
5852 continue;
d6dd9eb1 5853
e7a639c4
DV		 5854 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5855 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 5856 enable = true;
5857 }
5858
d6dd9eb1
DV		 5859 intel_set_power_well(dev, enable);
5860}
5861
09b4ddf9 5862static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5863 int x, int y,
5864 struct drm_framebuffer *fb)
5865{
5866 struct drm_device *dev = crtc->dev;
5867 struct drm_i915_private *dev_priv = dev->dev_private;
5868 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5869 struct drm_display_mode *adjusted_mode =
5870 &intel_crtc->config.adjusted_mode;
5871 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5872 int pipe = intel_crtc->pipe;
5873 int plane = intel_crtc->plane;
5874 int num_connectors = 0;
8b47047b 5875 bool is_cpu_edp = false;
09b4ddf9 5876 struct intel_encoder *encoder;
09b4ddf9 5877 int ret;
09b4ddf9
PZ		 5878
5879 for_each_encoder_on_crtc(dev, crtc, encoder) {
5880 switch (encoder->type) {
09b4ddf9 5881 case INTEL_OUTPUT_EDP:
d8e8b582 5882 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
09b4ddf9
PZ		 5883 is_cpu_edp = true;
5884 break;
5885 }
5886
5887 num_connectors++;
5888 }
5889
5dc5298b
PZ		 5890 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5891 num_connectors, pipe_name(pipe));
5892
6441ab5f
PZ		 5893 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5894 return -EINVAL;
5895
09b4ddf9
PZ		 5896 /* Ensure that the cursor is valid for the new mode before changing... */
5897 intel_crtc_update_cursor(crtc, true);
5898
03afc4a2
DV		 5899 if (intel_crtc->config.has_dp_encoder)
5900 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5901
5902 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5903
5904 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5905
ca3a0ff8 5906 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5907 intel_cpu_transcoder_set_m_n(intel_crtc,
5908 &intel_crtc->config.fdi_m_n);
5909 }
09b4ddf9 5910
6ff93609 5911 haswell_set_pipeconf(crtc);
09b4ddf9 5912
50f3b016 5913 intel_set_pipe_csc(crtc);
86d3efce 5914
09b4ddf9 5915 /* Set up the display plane register */
86d3efce 5916 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5917 POSTING_READ(DSPCNTR(plane));
5918
5919 ret = intel_pipe_set_base(crtc, x, y, fb);
5920
5921 intel_update_watermarks(dev);
5922
1f803ee5 5923 return ret;
79e53945
JB		 5924}
5925
0e8ffe1b
DV		 5926static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5927 struct intel_crtc_config *pipe_config)
5928{
5929 struct drm_device *dev = crtc->base.dev;
5930 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 5931 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 5932 uint32_t tmp;
5933
eccb140b
DV		 5934 pipe_config->cpu_transcoder = crtc->pipe;
5935 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5936 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5937 enum pipe trans_edp_pipe;
5938 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5939 default:
5940 WARN(1, "unknown pipe linked to edp transcoder\n");
5941 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5942 case TRANS_DDI_EDP_INPUT_A_ON:
5943 trans_edp_pipe = PIPE_A;
5944 break;
5945 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5946 trans_edp_pipe = PIPE_B;
5947 break;
5948 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5949 trans_edp_pipe = PIPE_C;
5950 break;
5951 }
5952
5953 if (trans_edp_pipe == crtc->pipe)
5954 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5955 }
5956
b97186f0 5957 if (!intel_display_power_enabled(dev,
eccb140b 5958 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 5959 return false;
5960
eccb140b 5961 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 5962 if (!(tmp & PIPECONF_ENABLE))
5963 return false;
5964
88adfff1 5965 /*
f196e6be 5966 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 5967 * DDI E. So just check whether this pipe is wired to DDI E and whether
5968 * the PCH transcoder is on.
5969 */
eccb140b 5970 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 5971 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 5972 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 5973 pipe_config->has_pch_encoder = true;
5974
627eb5a3
DV		 5975 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5976 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5977 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5978
5979 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5980 }
5981
1bd1bd80
DV		 5982 intel_get_pipe_timings(crtc, pipe_config);
5983
2fa2fe9a
DV		 5984 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5985 if (intel_display_power_enabled(dev, pfit_domain))
5986 ironlake_get_pfit_config(crtc, pipe_config);
5987
42db64ef
PZ		 5988 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
5989 (I915_READ(IPS_CTL) & IPS_ENABLE);
5990
0e8ffe1b
DV		 5991 return true;
5992}
5993
f564048e 5994static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5995 int x, int y,
94352cf9 5996 struct drm_framebuffer *fb)
f564048e
EA		 5997{
5998 struct drm_device *dev = crtc->dev;
5999 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6000 struct drm_encoder_helper_funcs *encoder_funcs;
6001 struct intel_encoder *encoder;
0b701d27 6002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6003 struct drm_display_mode *adjusted_mode =
6004 &intel_crtc->config.adjusted_mode;
6005 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6006 int pipe = intel_crtc->pipe;
f564048e
EA		 6007 int ret;
6008
0b701d27 6009 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6010
b8cecdf5
DV		 6011 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6012
79e53945 6013 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6014
9256aa19
DV		 6015 if (ret != 0)
6016 return ret;
6017
6018 for_each_encoder_on_crtc(dev, crtc, encoder) {
6019 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6020 encoder->base.base.id,
6021 drm_get_encoder_name(&encoder->base),
6022 mode->base.id, mode->name);
6cc5f341
DV		 6023 if (encoder->mode_set) {
6024 encoder->mode_set(encoder);
6025 } else {
6026 encoder_funcs = encoder->base.helper_private;
6027 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6028 }
9256aa19
DV		 6029 }
6030
6031 return 0;
79e53945
JB		 6032}
6033
3a9627f4
WF		 6034static bool intel_eld_uptodate(struct drm_connector *connector,
6035 int reg_eldv, uint32_t bits_eldv,
6036 int reg_elda, uint32_t bits_elda,
6037 int reg_edid)
6038{
6039 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6040 uint8_t *eld = connector->eld;
6041 uint32_t i;
6042
6043 i = I915_READ(reg_eldv);
6044 i &= bits_eldv;
6045
6046 if (!eld[0])
6047 return !i;
6048
6049 if (!i)
6050 return false;
6051
6052 i = I915_READ(reg_elda);
6053 i &= ~bits_elda;
6054 I915_WRITE(reg_elda, i);
6055
6056 for (i = 0; i < eld[2]; i++)
6057 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6058 return false;
6059
6060 return true;
6061}
6062
e0dac65e
WF		 6063static void g4x_write_eld(struct drm_connector *connector,
6064 struct drm_crtc *crtc)
6065{
6066 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6067 uint8_t *eld = connector->eld;
6068 uint32_t eldv;
6069 uint32_t len;
6070 uint32_t i;
6071
6072 i = I915_READ(G4X_AUD_VID_DID);
6073
6074 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6075 eldv = G4X_ELDV_DEVCL_DEVBLC;
6076 else
6077 eldv = G4X_ELDV_DEVCTG;
6078
3a9627f4
WF		 6079 if (intel_eld_uptodate(connector,
6080 G4X_AUD_CNTL_ST, eldv,
6081 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6082 G4X_HDMIW_HDMIEDID))
6083 return;
6084
e0dac65e
WF		 6085 i = I915_READ(G4X_AUD_CNTL_ST);
6086 i &= ~(eldv | G4X_ELD_ADDR);
6087 len = (i >> 9) & 0x1f; /* ELD buffer size */
6088 I915_WRITE(G4X_AUD_CNTL_ST, i);
6089
6090 if (!eld[0])
6091 return;
6092
6093 len = min_t(uint8_t, eld[2], len);
6094 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6095 for (i = 0; i < len; i++)
6096 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6097
6098 i = I915_READ(G4X_AUD_CNTL_ST);
6099 i |= eldv;
6100 I915_WRITE(G4X_AUD_CNTL_ST, i);
6101}
6102
83358c85
WX		 6103static void haswell_write_eld(struct drm_connector *connector,
6104 struct drm_crtc *crtc)
6105{
6106 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6107 uint8_t *eld = connector->eld;
6108 struct drm_device *dev = crtc->dev;
7b9f35a6 6109 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6110 uint32_t eldv;
6111 uint32_t i;
6112 int len;
6113 int pipe = to_intel_crtc(crtc)->pipe;
6114 int tmp;
6115
6116 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6117 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6118 int aud_config = HSW_AUD_CFG(pipe);
6119 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6120
6121
6122 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6123
6124 /* Audio output enable */
6125 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6126 tmp = I915_READ(aud_cntrl_st2);
6127 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6128 I915_WRITE(aud_cntrl_st2, tmp);
6129
6130 /* Wait for 1 vertical blank */
6131 intel_wait_for_vblank(dev, pipe);
6132
6133 /* Set ELD valid state */
6134 tmp = I915_READ(aud_cntrl_st2);
6135 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6136 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6137 I915_WRITE(aud_cntrl_st2, tmp);
6138 tmp = I915_READ(aud_cntrl_st2);
6139 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6140
6141 /* Enable HDMI mode */
6142 tmp = I915_READ(aud_config);
6143 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6144 /* clear N_programing_enable and N_value_index */
6145 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6146 I915_WRITE(aud_config, tmp);
6147
6148 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6149
6150 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6151 intel_crtc->eld_vld = true;
83358c85
WX		 6152
6153 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6154 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6155 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6156 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6157 } else
6158 I915_WRITE(aud_config, 0);
6159
6160 if (intel_eld_uptodate(connector,
6161 aud_cntrl_st2, eldv,
6162 aud_cntl_st, IBX_ELD_ADDRESS,
6163 hdmiw_hdmiedid))
6164 return;
6165
6166 i = I915_READ(aud_cntrl_st2);
6167 i &= ~eldv;
6168 I915_WRITE(aud_cntrl_st2, i);
6169
6170 if (!eld[0])
6171 return;
6172
6173 i = I915_READ(aud_cntl_st);
6174 i &= ~IBX_ELD_ADDRESS;
6175 I915_WRITE(aud_cntl_st, i);
6176 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6177 DRM_DEBUG_DRIVER("port num:%d\n", i);
6178
6179 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6180 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6181 for (i = 0; i < len; i++)
6182 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6183
6184 i = I915_READ(aud_cntrl_st2);
6185 i |= eldv;
6186 I915_WRITE(aud_cntrl_st2, i);
6187
6188}
6189
e0dac65e
WF		 6190static void ironlake_write_eld(struct drm_connector *connector,
6191 struct drm_crtc *crtc)
6192{
6193 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6194 uint8_t *eld = connector->eld;
6195 uint32_t eldv;
6196 uint32_t i;
6197 int len;
6198 int hdmiw_hdmiedid;
b6daa025 6199 int aud_config;
e0dac65e
WF		 6200 int aud_cntl_st;
6201 int aud_cntrl_st2;
9b138a83 6202 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6203
b3f33cbf 6204 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6205 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6206 aud_config = IBX_AUD_CFG(pipe);
6207 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6208 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6209 } else {
9b138a83
WX		 6210 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6211 aud_config = CPT_AUD_CFG(pipe);
6212 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6213 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6214 }
6215
9b138a83 6216 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6217
6218 i = I915_READ(aud_cntl_st);
9b138a83 6219 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6220 if (!i) {
6221 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6222 /* operate blindly on all ports */
1202b4c6
WF		 6223 eldv = IBX_ELD_VALIDB;
6224 eldv |= IBX_ELD_VALIDB << 4;
6225 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6226 } else {
2582a850 6227 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6228 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6229 }
6230
3a9627f4
WF		 6231 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6232 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6233 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6234 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6235 } else
6236 I915_WRITE(aud_config, 0);
e0dac65e 6237
3a9627f4
WF		 6238 if (intel_eld_uptodate(connector,
6239 aud_cntrl_st2, eldv,
6240 aud_cntl_st, IBX_ELD_ADDRESS,
6241 hdmiw_hdmiedid))
6242 return;
6243
e0dac65e
WF		 6244 i = I915_READ(aud_cntrl_st2);
6245 i &= ~eldv;
6246 I915_WRITE(aud_cntrl_st2, i);
6247
6248 if (!eld[0])
6249 return;
6250
e0dac65e 6251 i = I915_READ(aud_cntl_st);
1202b4c6 6252 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6253 I915_WRITE(aud_cntl_st, i);
6254
6255 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6256 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6257 for (i = 0; i < len; i++)
6258 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6259
6260 i = I915_READ(aud_cntrl_st2);
6261 i |= eldv;
6262 I915_WRITE(aud_cntrl_st2, i);
6263}
6264
6265void intel_write_eld(struct drm_encoder *encoder,
6266 struct drm_display_mode *mode)
6267{
6268 struct drm_crtc *crtc = encoder->crtc;
6269 struct drm_connector *connector;
6270 struct drm_device *dev = encoder->dev;
6271 struct drm_i915_private *dev_priv = dev->dev_private;
6272
6273 connector = drm_select_eld(encoder, mode);
6274 if (!connector)
6275 return;
6276
6277 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6278 connector->base.id,
6279 drm_get_connector_name(connector),
6280 connector->encoder->base.id,
6281 drm_get_encoder_name(connector->encoder));
6282
6283 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6284
6285 if (dev_priv->display.write_eld)
6286 dev_priv->display.write_eld(connector, crtc);
6287}
6288
79e53945
JB		 6289/** Loads the palette/gamma unit for the CRTC with the prepared values */
6290void intel_crtc_load_lut(struct drm_crtc *crtc)
6291{
6292 struct drm_device *dev = crtc->dev;
6293 struct drm_i915_private *dev_priv = dev->dev_private;
6294 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6295 enum pipe pipe = intel_crtc->pipe;
6296 int palreg = PALETTE(pipe);
79e53945 6297 int i;
42db64ef 6298 bool reenable_ips = false;
79e53945
JB		 6299
6300 /* The clocks have to be on to load the palette. */
aed3f09d 6301 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6302 return;
6303
f2b115e6 6304 /* use legacy palette for Ironlake */
bad720ff 6305 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6306 palreg = LGC_PALETTE(pipe);
6307
6308 /* Workaround : Do not read or write the pipe palette/gamma data while
6309 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6310 */
6311 if (intel_crtc->config.ips_enabled &&
6312 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6313 GAMMA_MODE_MODE_SPLIT)) {
6314 hsw_disable_ips(intel_crtc);
6315 reenable_ips = true;
6316 }
2c07245f 6317
79e53945
JB		 6318 for (i = 0; i < 256; i++) {
6319 I915_WRITE(palreg + 4 * i,
6320 (intel_crtc->lut_r[i] << 16) |
6321 (intel_crtc->lut_g[i] << 8) |
6322 intel_crtc->lut_b[i]);
6323 }
42db64ef
PZ		 6324
6325 if (reenable_ips)
6326 hsw_enable_ips(intel_crtc);
79e53945
JB		 6327}
6328
560b85bb
CW		 6329static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6330{
6331 struct drm_device *dev = crtc->dev;
6332 struct drm_i915_private *dev_priv = dev->dev_private;
6333 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6334 bool visible = base != 0;
6335 u32 cntl;
6336
6337 if (intel_crtc->cursor_visible == visible)
6338 return;
6339
9db4a9c7 6340 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6341 if (visible) {
6342 /* On these chipsets we can only modify the base whilst
6343 * the cursor is disabled.
6344 */
9db4a9c7 6345 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6346
6347 cntl &= ~(CURSOR_FORMAT_MASK);
6348 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6349 cntl |= CURSOR_ENABLE |
6350 CURSOR_GAMMA_ENABLE |
6351 CURSOR_FORMAT_ARGB;
6352 } else
6353 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6354 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6355
6356 intel_crtc->cursor_visible = visible;
6357}
6358
6359static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6360{
6361 struct drm_device *dev = crtc->dev;
6362 struct drm_i915_private *dev_priv = dev->dev_private;
6363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6364 int pipe = intel_crtc->pipe;
6365 bool visible = base != 0;
6366
6367 if (intel_crtc->cursor_visible != visible) {
548f245b 6368 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6369 if (base) {
6370 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6371 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6372 cntl |= pipe << 28; /* Connect to correct pipe */
6373 } else {
6374 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6375 cntl |= CURSOR_MODE_DISABLE;
6376 }
9db4a9c7 6377 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6378
6379 intel_crtc->cursor_visible = visible;
6380 }
6381 /* and commit changes on next vblank */
9db4a9c7 6382 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6383}
6384
65a21cd6
JB		 6385static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6386{
6387 struct drm_device *dev = crtc->dev;
6388 struct drm_i915_private *dev_priv = dev->dev_private;
6389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6390 int pipe = intel_crtc->pipe;
6391 bool visible = base != 0;
6392
6393 if (intel_crtc->cursor_visible != visible) {
6394 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6395 if (base) {
6396 cntl &= ~CURSOR_MODE;
6397 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6398 } else {
6399 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6400 cntl |= CURSOR_MODE_DISABLE;
6401 }
86d3efce
VS		 6402 if (IS_HASWELL(dev))
6403 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6404 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6405
6406 intel_crtc->cursor_visible = visible;
6407 }
6408 /* and commit changes on next vblank */
6409 I915_WRITE(CURBASE_IVB(pipe), base);
6410}
6411
cda4b7d3 6412/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6413static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6414 bool on)
cda4b7d3
CW		 6415{
6416 struct drm_device *dev = crtc->dev;
6417 struct drm_i915_private *dev_priv = dev->dev_private;
6418 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6419 int pipe = intel_crtc->pipe;
6420 int x = intel_crtc->cursor_x;
6421 int y = intel_crtc->cursor_y;
560b85bb 6422 u32 base, pos;
cda4b7d3
CW		 6423 bool visible;
6424
6425 pos = 0;
6426
6b383a7f 6427 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6428 base = intel_crtc->cursor_addr;
6429 if (x > (int) crtc->fb->width)
6430 base = 0;
6431
6432 if (y > (int) crtc->fb->height)
6433 base = 0;
6434 } else
6435 base = 0;
6436
6437 if (x < 0) {
6438 if (x + intel_crtc->cursor_width < 0)
6439 base = 0;
6440
6441 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6442 x = -x;
6443 }
6444 pos |= x << CURSOR_X_SHIFT;
6445
6446 if (y < 0) {
6447 if (y + intel_crtc->cursor_height < 0)
6448 base = 0;
6449
6450 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6451 y = -y;
6452 }
6453 pos |= y << CURSOR_Y_SHIFT;
6454
6455 visible = base != 0;
560b85bb 6456 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6457 return;
6458
0cd83aa9 6459 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6460 I915_WRITE(CURPOS_IVB(pipe), pos);
6461 ivb_update_cursor(crtc, base);
6462 } else {
6463 I915_WRITE(CURPOS(pipe), pos);
6464 if (IS_845G(dev) || IS_I865G(dev))
6465 i845_update_cursor(crtc, base);
6466 else
6467 i9xx_update_cursor(crtc, base);
6468 }
cda4b7d3
CW		 6469}
6470
79e53945 6471static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6472 struct drm_file *file,
79e53945
JB		 6473 uint32_t handle,
6474 uint32_t width, uint32_t height)
6475{
6476 struct drm_device *dev = crtc->dev;
6477 struct drm_i915_private *dev_priv = dev->dev_private;
6478 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6479 struct drm_i915_gem_object *obj;
cda4b7d3 6480 uint32_t addr;
3f8bc370 6481 int ret;
79e53945 6482
79e53945
JB		 6483 /* if we want to turn off the cursor ignore width and height */
6484 if (!handle) {
28c97730 6485 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6486 addr = 0;
05394f39 6487 obj = NULL;
5004417d 6488 mutex_lock(&dev->struct_mutex);
3f8bc370 6489 goto finish;
79e53945
JB		 6490 }
6491
6492 /* Currently we only support 64x64 cursors */
6493 if (width != 64 || height != 64) {
6494 DRM_ERROR("we currently only support 64x64 cursors\n");
6495 return -EINVAL;
6496 }
6497
05394f39 6498 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6499 if (&obj->base == NULL)
79e53945
JB		 6500 return -ENOENT;
6501
05394f39 6502 if (obj->base.size < width * height * 4) {
79e53945 6503 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6504 ret = -ENOMEM;
6505 goto fail;
79e53945
JB		 6506 }
6507
71acb5eb 6508 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6509 mutex_lock(&dev->struct_mutex);
b295d1b6 6510 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6511 unsigned alignment;
6512
d9e86c0e
CW		 6513 if (obj->tiling_mode) {
6514 DRM_ERROR("cursor cannot be tiled\n");
6515 ret = -EINVAL;
6516 goto fail_locked;
6517 }
6518
693db184
CW		 6519 /* Note that the w/a also requires 2 PTE of padding following
6520 * the bo. We currently fill all unused PTE with the shadow
6521 * page and so we should always have valid PTE following the
6522 * cursor preventing the VT-d warning.
6523 */
6524 alignment = 0;
6525 if (need_vtd_wa(dev))
6526 alignment = 64*1024;
6527
6528 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6529 if (ret) {
6530 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6531 goto fail_locked;
e7b526bb
CW		 6532 }
6533
d9e86c0e
CW		 6534 ret = i915_gem_object_put_fence(obj);
6535 if (ret) {
2da3b9b9 6536 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6537 goto fail_unpin;
6538 }
6539
05394f39 6540 addr = obj->gtt_offset;
71acb5eb 6541 } else {
6eeefaf3 6542 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6543 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6544 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6545 align);
71acb5eb
DA		 6546 if (ret) {
6547 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6548 goto fail_locked;
71acb5eb 6549 }
05394f39 6550 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6551 }
6552
a6c45cf0 6553 if (IS_GEN2(dev))
14b60391
JB		 6554 I915_WRITE(CURSIZE, (height << 12) | width);
6555
3f8bc370 6556 finish:
3f8bc370 6557 if (intel_crtc->cursor_bo) {
b295d1b6 6558 if (dev_priv->info->cursor_needs_physical) {
05394f39 6559 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6560 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6561 } else
6562 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6563 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6564 }
80824003 6565
7f9872e0 6566 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6567
6568 intel_crtc->cursor_addr = addr;
05394f39 6569 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6570 intel_crtc->cursor_width = width;
6571 intel_crtc->cursor_height = height;
6572
40ccc72b 6573 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6574
79e53945 6575 return 0;
e7b526bb 6576fail_unpin:
05394f39 6577 i915_gem_object_unpin(obj);
7f9872e0 6578fail_locked:
34b8686e 6579 mutex_unlock(&dev->struct_mutex);
bc9025bd 6580fail:
05394f39 6581 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6582 return ret;
79e53945
JB		 6583}
6584
6585static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6586{
79e53945 6587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6588
cda4b7d3
CW		 6589 intel_crtc->cursor_x = x;
6590 intel_crtc->cursor_y = y;
652c393a 6591
40ccc72b 6592 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6593
6594 return 0;
6595}
6596
6597/** Sets the color ramps on behalf of RandR */
6598void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6599 u16 blue, int regno)
6600{
6601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6602
6603 intel_crtc->lut_r[regno] = red >> 8;
6604 intel_crtc->lut_g[regno] = green >> 8;
6605 intel_crtc->lut_b[regno] = blue >> 8;
6606}
6607
b8c00ac5
DA		 6608void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6609 u16 *blue, int regno)
6610{
6611 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6612
6613 *red = intel_crtc->lut_r[regno] << 8;
6614 *green = intel_crtc->lut_g[regno] << 8;
6615 *blue = intel_crtc->lut_b[regno] << 8;
6616}
6617
79e53945 6618static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6619 u16 *blue, uint32_t start, uint32_t size)
79e53945 6620{
7203425a 6621 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6622 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6623
7203425a 6624 for (i = start; i < end; i++) {
79e53945
JB		 6625 intel_crtc->lut_r[i] = red[i] >> 8;
6626 intel_crtc->lut_g[i] = green[i] >> 8;
6627 intel_crtc->lut_b[i] = blue[i] >> 8;
6628 }
6629
6630 intel_crtc_load_lut(crtc);
6631}
6632
79e53945
JB		 6633/* VESA 640x480x72Hz mode to set on the pipe */
6634static struct drm_display_mode load_detect_mode = {
6635 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6636 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6637};
6638
d2dff872
CW		 6639static struct drm_framebuffer *
6640intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6641 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6642 struct drm_i915_gem_object *obj)
6643{
6644 struct intel_framebuffer *intel_fb;
6645 int ret;
6646
6647 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6648 if (!intel_fb) {
6649 drm_gem_object_unreference_unlocked(&obj->base);
6650 return ERR_PTR(-ENOMEM);
6651 }
6652
6653 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6654 if (ret) {
6655 drm_gem_object_unreference_unlocked(&obj->base);
6656 kfree(intel_fb);
6657 return ERR_PTR(ret);
6658 }
6659
6660 return &intel_fb->base;
6661}
6662
6663static u32
6664intel_framebuffer_pitch_for_width(int width, int bpp)
6665{
6666 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6667 return ALIGN(pitch, 64);
6668}
6669
6670static u32
6671intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6672{
6673 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6674 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6675}
6676
6677static struct drm_framebuffer *
6678intel_framebuffer_create_for_mode(struct drm_device *dev,
6679 struct drm_display_mode *mode,
6680 int depth, int bpp)
6681{
6682 struct drm_i915_gem_object *obj;
0fed39bd 6683 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6684
6685 obj = i915_gem_alloc_object(dev,
6686 intel_framebuffer_size_for_mode(mode, bpp));
6687 if (obj == NULL)
6688 return ERR_PTR(-ENOMEM);
6689
6690 mode_cmd.width = mode->hdisplay;
6691 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6692 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6693 bpp);
5ca0c34a 6694 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6695
6696 return intel_framebuffer_create(dev, &mode_cmd, obj);
6697}
6698
6699static struct drm_framebuffer *
6700mode_fits_in_fbdev(struct drm_device *dev,
6701 struct drm_display_mode *mode)
6702{
6703 struct drm_i915_private *dev_priv = dev->dev_private;
6704 struct drm_i915_gem_object *obj;
6705 struct drm_framebuffer *fb;
6706
6707 if (dev_priv->fbdev == NULL)
6708 return NULL;
6709
6710 obj = dev_priv->fbdev->ifb.obj;
6711 if (obj == NULL)
6712 return NULL;
6713
6714 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6715 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6716 fb->bits_per_pixel))
d2dff872
CW		 6717 return NULL;
6718
01f2c773 6719 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6720 return NULL;
6721
6722 return fb;
6723}
6724
d2434ab7 6725bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6726 struct drm_display_mode *mode,
8261b191 6727 struct intel_load_detect_pipe *old)
79e53945
JB		 6728{
6729 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6730 struct intel_encoder *intel_encoder =
6731 intel_attached_encoder(connector);
79e53945 6732 struct drm_crtc *possible_crtc;
4ef69c7a 6733 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6734 struct drm_crtc *crtc = NULL;
6735 struct drm_device *dev = encoder->dev;
94352cf9 6736 struct drm_framebuffer *fb;
79e53945
JB		 6737 int i = -1;
6738
d2dff872
CW		 6739 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6740 connector->base.id, drm_get_connector_name(connector),
6741 encoder->base.id, drm_get_encoder_name(encoder));
6742
79e53945
JB		 6743 /*
6744 * Algorithm gets a little messy:
7a5e4805 6745 *
79e53945
JB		 6746 * - if the connector already has an assigned crtc, use it (but make
6747 * sure it's on first)
7a5e4805 6748 *
79e53945
JB		 6749 * - try to find the first unused crtc that can drive this connector,
6750 * and use that if we find one
79e53945
JB		 6751 */
6752
6753 /* See if we already have a CRTC for this connector */
6754 if (encoder->crtc) {
6755 crtc = encoder->crtc;
8261b191 6756
7b24056b
DV		 6757 mutex_lock(&crtc->mutex);
6758
24218aac 6759 old->dpms_mode = connector->dpms;
8261b191
CW		 6760 old->load_detect_temp = false;
6761
6762 /* Make sure the crtc and connector are running */
24218aac
DV		 6763 if (connector->dpms != DRM_MODE_DPMS_ON)
6764 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6765
7173188d 6766 return true;
79e53945
JB		 6767 }
6768
6769 /* Find an unused one (if possible) */
6770 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6771 i++;
6772 if (!(encoder->possible_crtcs & (1 << i)))
6773 continue;
6774 if (!possible_crtc->enabled) {
6775 crtc = possible_crtc;
6776 break;
6777 }
79e53945
JB		 6778 }
6779
6780 /*
6781 * If we didn't find an unused CRTC, don't use any.
6782 */
6783 if (!crtc) {
7173188d
CW		 6784 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6785 return false;
79e53945
JB		 6786 }
6787
7b24056b 6788 mutex_lock(&crtc->mutex);
fc303101
DV		 6789 intel_encoder->new_crtc = to_intel_crtc(crtc);
6790 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6791
6792 intel_crtc = to_intel_crtc(crtc);
24218aac 6793 old->dpms_mode = connector->dpms;
8261b191 6794 old->load_detect_temp = true;
d2dff872 6795 old->release_fb = NULL;
79e53945 6796
6492711d
CW		 6797 if (!mode)
6798 mode = &load_detect_mode;
79e53945 6799
d2dff872
CW		 6800 /* We need a framebuffer large enough to accommodate all accesses
6801 * that the plane may generate whilst we perform load detection.
6802 * We can not rely on the fbcon either being present (we get called
6803 * during its initialisation to detect all boot displays, or it may
6804 * not even exist) or that it is large enough to satisfy the
6805 * requested mode.
6806 */
94352cf9
DV		 6807 fb = mode_fits_in_fbdev(dev, mode);
6808 if (fb == NULL) {
d2dff872 6809 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6810 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6811 old->release_fb = fb;
d2dff872
CW		 6812 } else
6813 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6814 if (IS_ERR(fb)) {
d2dff872 6815 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6816 mutex_unlock(&crtc->mutex);
0e8b3d3e 6817 return false;
79e53945 6818 }
79e53945 6819
c0c36b94 6820 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6821 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6822 if (old->release_fb)
6823 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6824 mutex_unlock(&crtc->mutex);
0e8b3d3e 6825 return false;
79e53945 6826 }
7173188d 6827
79e53945 6828 /* let the connector get through one full cycle before testing */
9d0498a2 6829 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6830 return true;
79e53945
JB		 6831}
6832
d2434ab7 6833void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6834 struct intel_load_detect_pipe *old)
79e53945 6835{
d2434ab7
DV		 6836 struct intel_encoder *intel_encoder =
6837 intel_attached_encoder(connector);
4ef69c7a 6838 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6839 struct drm_crtc *crtc = encoder->crtc;
79e53945 6840
d2dff872
CW		 6841 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6842 connector->base.id, drm_get_connector_name(connector),
6843 encoder->base.id, drm_get_encoder_name(encoder));
6844
8261b191 6845 if (old->load_detect_temp) {
fc303101
DV		 6846 to_intel_connector(connector)->new_encoder = NULL;
6847 intel_encoder->new_crtc = NULL;
6848 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6849
36206361
DV		 6850 if (old->release_fb) {
6851 drm_framebuffer_unregister_private(old->release_fb);
6852 drm_framebuffer_unreference(old->release_fb);
6853 }
d2dff872 6854
67c96400 6855 mutex_unlock(&crtc->mutex);
0622a53c 6856 return;
79e53945
JB		 6857 }
6858
c751ce4f 6859 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6860 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6861 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6862
6863 mutex_unlock(&crtc->mutex);
79e53945
JB		 6864}
6865
6866/* Returns the clock of the currently programmed mode of the given pipe. */
6867static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6868{
6869 struct drm_i915_private *dev_priv = dev->dev_private;
6870 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6871 int pipe = intel_crtc->pipe;
548f245b 6872 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6873 u32 fp;
6874 intel_clock_t clock;
6875
6876 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6877 fp = I915_READ(FP0(pipe));
79e53945 6878 else
39adb7a5 6879 fp = I915_READ(FP1(pipe));
79e53945
JB		 6880
6881 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6882 if (IS_PINEVIEW(dev)) {
6883 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6884 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6885 } else {
6886 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6887 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6888 }
6889
a6c45cf0 6890 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6891 if (IS_PINEVIEW(dev))
6892 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6893 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6894 else
6895 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6896 DPLL_FPA01_P1_POST_DIV_SHIFT);
6897
6898 switch (dpll & DPLL_MODE_MASK) {
6899 case DPLLB_MODE_DAC_SERIAL:
6900 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6901 5 : 10;
6902 break;
6903 case DPLLB_MODE_LVDS:
6904 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6905 7 : 14;
6906 break;
6907 default:
28c97730 6908 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6909 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6910 return 0;
6911 }
6912
6913 /* XXX: Handle the 100Mhz refclk */
2177832f 6914 intel_clock(dev, 96000, &clock);
79e53945
JB		 6915 } else {
6916 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6917
6918 if (is_lvds) {
6919 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6920 DPLL_FPA01_P1_POST_DIV_SHIFT);
6921 clock.p2 = 14;
6922
6923 if ((dpll & PLL_REF_INPUT_MASK) ==
6924 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6925 /* XXX: might not be 66MHz */
2177832f 6926 intel_clock(dev, 66000, &clock);
79e53945 6927 } else
2177832f 6928 intel_clock(dev, 48000, &clock);
79e53945
JB		 6929 } else {
6930 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6931 clock.p1 = 2;
6932 else {
6933 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6934 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6935 }
6936 if (dpll & PLL_P2_DIVIDE_BY_4)
6937 clock.p2 = 4;
6938 else
6939 clock.p2 = 2;
6940
2177832f 6941 intel_clock(dev, 48000, &clock);
79e53945
JB		 6942 }
6943 }
6944
6945 /* XXX: It would be nice to validate the clocks, but we can't reuse
6946 * i830PllIsValid() because it relies on the xf86_config connector
6947 * configuration being accurate, which it isn't necessarily.
6948 */
6949
6950 return clock.dot;
6951}
6952
6953/** Returns the currently programmed mode of the given pipe. */
6954struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6955 struct drm_crtc *crtc)
6956{
548f245b 6957 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6958 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 6959 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 6960 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6961 int htot = I915_READ(HTOTAL(cpu_transcoder));
6962 int hsync = I915_READ(HSYNC(cpu_transcoder));
6963 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6964 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6965
6966 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6967 if (!mode)
6968 return NULL;
6969
6970 mode->clock = intel_crtc_clock_get(dev, crtc);
6971 mode->hdisplay = (htot & 0xffff) + 1;
6972 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6973 mode->hsync_start = (hsync & 0xffff) + 1;
6974 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6975 mode->vdisplay = (vtot & 0xffff) + 1;
6976 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6977 mode->vsync_start = (vsync & 0xffff) + 1;
6978 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6979
6980 drm_mode_set_name(mode);
79e53945
JB		 6981
6982 return mode;
6983}
6984
3dec0095 6985static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6986{
6987 struct drm_device *dev = crtc->dev;
6988 drm_i915_private_t *dev_priv = dev->dev_private;
6989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6990 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6991 int dpll_reg = DPLL(pipe);
6992 int dpll;
652c393a 6993
bad720ff 6994 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6995 return;
6996
6997 if (!dev_priv->lvds_downclock_avail)
6998 return;
6999
dbdc6479 7000 dpll = I915_READ(dpll_reg);
652c393a 7001 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7002 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7003
8ac5a6d5 7004 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7005
7006 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7007 I915_WRITE(dpll_reg, dpll);
9d0498a2 7008 intel_wait_for_vblank(dev, pipe);
dbdc6479 7009
652c393a
JB		 7010 dpll = I915_READ(dpll_reg);
7011 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7012 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7013 }
652c393a
JB		 7014}
7015
7016static void intel_decrease_pllclock(struct drm_crtc *crtc)
7017{
7018 struct drm_device *dev = crtc->dev;
7019 drm_i915_private_t *dev_priv = dev->dev_private;
7020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7021
bad720ff 7022 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7023 return;
7024
7025 if (!dev_priv->lvds_downclock_avail)
7026 return;
7027
7028 /*
7029 * Since this is called by a timer, we should never get here in
7030 * the manual case.
7031 */
7032 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7033 int pipe = intel_crtc->pipe;
7034 int dpll_reg = DPLL(pipe);
7035 int dpll;
f6e5b160 7036
44d98a61 7037 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7038
8ac5a6d5 7039 assert_panel_unlocked(dev_priv, pipe);
652c393a 7040
dc257cf1 7041 dpll = I915_READ(dpll_reg);
652c393a
JB		 7042 dpll |= DISPLAY_RATE_SELECT_FPA1;
7043 I915_WRITE(dpll_reg, dpll);
9d0498a2 7044 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7045 dpll = I915_READ(dpll_reg);
7046 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7047 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7048 }
7049
7050}
7051
f047e395
CW		 7052void intel_mark_busy(struct drm_device *dev)
7053{
f047e395
CW		 7054 i915_update_gfx_val(dev->dev_private);
7055}
7056
7057void intel_mark_idle(struct drm_device *dev)
652c393a 7058{
652c393a 7059 struct drm_crtc *crtc;
652c393a
JB		 7060
7061 if (!i915_powersave)
7062 return;
7063
652c393a 7064 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7065 if (!crtc->fb)
7066 continue;
7067
725a5b54 7068 intel_decrease_pllclock(crtc);
652c393a 7069 }
652c393a
JB		 7070}
7071
725a5b54 7072void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 7073{
f047e395
CW		 7074 struct drm_device *dev = obj->base.dev;
7075 struct drm_crtc *crtc;
652c393a 7076
f047e395 7077 if (!i915_powersave)
acb87dfb
CW		 7078 return;
7079
652c393a
JB		 7080 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7081 if (!crtc->fb)
7082 continue;
7083
f047e395 7084 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 7085 intel_increase_pllclock(crtc);
652c393a
JB		 7086 }
7087}
7088
79e53945
JB		 7089static void intel_crtc_destroy(struct drm_crtc *crtc)
7090{
7091 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7092 struct drm_device *dev = crtc->dev;
7093 struct intel_unpin_work *work;
7094 unsigned long flags;
7095
7096 spin_lock_irqsave(&dev->event_lock, flags);
7097 work = intel_crtc->unpin_work;
7098 intel_crtc->unpin_work = NULL;
7099 spin_unlock_irqrestore(&dev->event_lock, flags);
7100
7101 if (work) {
7102 cancel_work_sync(&work->work);
7103 kfree(work);
7104 }
79e53945 7105
40ccc72b
MK		 7106 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7107
79e53945 7108 drm_crtc_cleanup(crtc);
67e77c5a 7109
79e53945
JB		 7110 kfree(intel_crtc);
7111}
7112
6b95a207
KH		 7113static void intel_unpin_work_fn(struct work_struct *__work)
7114{
7115 struct intel_unpin_work *work =
7116 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7117 struct drm_device *dev = work->crtc->dev;
6b95a207 7118
b4a98e57 7119 mutex_lock(&dev->struct_mutex);
1690e1eb 7120 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7121 drm_gem_object_unreference(&work->pending_flip_obj->base);
7122 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7123
b4a98e57
CW		 7124 intel_update_fbc(dev);
7125 mutex_unlock(&dev->struct_mutex);
7126
7127 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7128 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7129
6b95a207
KH		 7130 kfree(work);
7131}
7132
1afe3e9d 7133static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7134 struct drm_crtc *crtc)
6b95a207
KH		 7135{
7136 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7137 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7138 struct intel_unpin_work *work;
6b95a207
KH		 7139 unsigned long flags;
7140
7141 /* Ignore early vblank irqs */
7142 if (intel_crtc == NULL)
7143 return;
7144
7145 spin_lock_irqsave(&dev->event_lock, flags);
7146 work = intel_crtc->unpin_work;
e7d841ca
CW		 7147
7148 /* Ensure we don't miss a work->pending update ... */
7149 smp_rmb();
7150
7151 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7152 spin_unlock_irqrestore(&dev->event_lock, flags);
7153 return;
7154 }
7155
e7d841ca
CW		 7156 /* and that the unpin work is consistent wrt ->pending. */
7157 smp_rmb();
7158
6b95a207 7159 intel_crtc->unpin_work = NULL;
6b95a207 7160
45a066eb
RC		 7161 if (work->event)
7162 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7163
0af7e4df
MK		 7164 drm_vblank_put(dev, intel_crtc->pipe);
7165
6b95a207
KH		 7166 spin_unlock_irqrestore(&dev->event_lock, flags);
7167
2c10d571 7168 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7169
7170 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7171
7172 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7173}
7174
1afe3e9d
JB		 7175void intel_finish_page_flip(struct drm_device *dev, int pipe)
7176{
7177 drm_i915_private_t *dev_priv = dev->dev_private;
7178 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7179
49b14a5c 7180 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7181}
7182
7183void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7184{
7185 drm_i915_private_t *dev_priv = dev->dev_private;
7186 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7187
49b14a5c 7188 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7189}
7190
6b95a207
KH		 7191void intel_prepare_page_flip(struct drm_device *dev, int plane)
7192{
7193 drm_i915_private_t *dev_priv = dev->dev_private;
7194 struct intel_crtc *intel_crtc =
7195 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7196 unsigned long flags;
7197
e7d841ca
CW		 7198 /* NB: An MMIO update of the plane base pointer will also
7199 * generate a page-flip completion irq, i.e. every modeset
7200 * is also accompanied by a spurious intel_prepare_page_flip().
7201 */
6b95a207 7202 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7203 if (intel_crtc->unpin_work)
7204 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7205 spin_unlock_irqrestore(&dev->event_lock, flags);
7206}
7207
e7d841ca
CW		 7208inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7209{
7210 /* Ensure that the work item is consistent when activating it ... */
7211 smp_wmb();
7212 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7213 /* and that it is marked active as soon as the irq could fire. */
7214 smp_wmb();
7215}
7216
8c9f3aaf
JB		 7217static int intel_gen2_queue_flip(struct drm_device *dev,
7218 struct drm_crtc *crtc,
7219 struct drm_framebuffer *fb,
7220 struct drm_i915_gem_object *obj)
7221{
7222 struct drm_i915_private *dev_priv = dev->dev_private;
7223 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7224 u32 flip_mask;
6d90c952 7225 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7226 int ret;
7227
6d90c952 7228 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7229 if (ret)
83d4092b 7230 goto err;
8c9f3aaf 7231
6d90c952 7232 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7233 if (ret)
83d4092b 7234 goto err_unpin;
8c9f3aaf
JB		 7235
7236 /* Can't queue multiple flips, so wait for the previous
7237 * one to finish before executing the next.
7238 */
7239 if (intel_crtc->plane)
7240 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7241 else
7242 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7243 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7244 intel_ring_emit(ring, MI_NOOP);
7245 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7246 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7247 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7248 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7249 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7250
7251 intel_mark_page_flip_active(intel_crtc);
6d90c952 7252 intel_ring_advance(ring);
83d4092b
CW		 7253 return 0;
7254
7255err_unpin:
7256 intel_unpin_fb_obj(obj);
7257err:
8c9f3aaf
JB		 7258 return ret;
7259}
7260
7261static int intel_gen3_queue_flip(struct drm_device *dev,
7262 struct drm_crtc *crtc,
7263 struct drm_framebuffer *fb,
7264 struct drm_i915_gem_object *obj)
7265{
7266 struct drm_i915_private *dev_priv = dev->dev_private;
7267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7268 u32 flip_mask;
6d90c952 7269 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7270 int ret;
7271
6d90c952 7272 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7273 if (ret)
83d4092b 7274 goto err;
8c9f3aaf 7275
6d90c952 7276 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7277 if (ret)
83d4092b 7278 goto err_unpin;
8c9f3aaf
JB		 7279
7280 if (intel_crtc->plane)
7281 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7282 else
7283 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7284 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7285 intel_ring_emit(ring, MI_NOOP);
7286 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7287 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7288 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7289 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7290 intel_ring_emit(ring, MI_NOOP);
7291
e7d841ca 7292 intel_mark_page_flip_active(intel_crtc);
6d90c952 7293 intel_ring_advance(ring);
83d4092b
CW		 7294 return 0;
7295
7296err_unpin:
7297 intel_unpin_fb_obj(obj);
7298err:
8c9f3aaf
JB		 7299 return ret;
7300}
7301
7302static int intel_gen4_queue_flip(struct drm_device *dev,
7303 struct drm_crtc *crtc,
7304 struct drm_framebuffer *fb,
7305 struct drm_i915_gem_object *obj)
7306{
7307 struct drm_i915_private *dev_priv = dev->dev_private;
7308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7309 uint32_t pf, pipesrc;
6d90c952 7310 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7311 int ret;
7312
6d90c952 7313 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7314 if (ret)
83d4092b 7315 goto err;
8c9f3aaf 7316
6d90c952 7317 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7318 if (ret)
83d4092b 7319 goto err_unpin;
8c9f3aaf
JB		 7320
7321 /* i965+ uses the linear or tiled offsets from the
7322 * Display Registers (which do not change across a page-flip)
7323 * so we need only reprogram the base address.
7324 */
6d90c952
DV		 7325 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7326 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7327 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7328 intel_ring_emit(ring,
7329 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7330 obj->tiling_mode);
8c9f3aaf
JB		 7331
7332 /* XXX Enabling the panel-fitter across page-flip is so far
7333 * untested on non-native modes, so ignore it for now.
7334 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7335 */
7336 pf = 0;
7337 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7338 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7339
7340 intel_mark_page_flip_active(intel_crtc);
6d90c952 7341 intel_ring_advance(ring);
83d4092b
CW		 7342 return 0;
7343
7344err_unpin:
7345 intel_unpin_fb_obj(obj);
7346err:
8c9f3aaf
JB		 7347 return ret;
7348}
7349
7350static int intel_gen6_queue_flip(struct drm_device *dev,
7351 struct drm_crtc *crtc,
7352 struct drm_framebuffer *fb,
7353 struct drm_i915_gem_object *obj)
7354{
7355 struct drm_i915_private *dev_priv = dev->dev_private;
7356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7357 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7358 uint32_t pf, pipesrc;
7359 int ret;
7360
6d90c952 7361 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7362 if (ret)
83d4092b 7363 goto err;
8c9f3aaf 7364
6d90c952 7365 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7366 if (ret)
83d4092b 7367 goto err_unpin;
8c9f3aaf 7368
6d90c952
DV		 7369 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7370 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7371 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7372 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7373
dc257cf1
DV		 7374 /* Contrary to the suggestions in the documentation,
7375 * "Enable Panel Fitter" does not seem to be required when page
7376 * flipping with a non-native mode, and worse causes a normal
7377 * modeset to fail.
7378 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7379 */
7380 pf = 0;
8c9f3aaf 7381 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7382 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7383
7384 intel_mark_page_flip_active(intel_crtc);
6d90c952 7385 intel_ring_advance(ring);
83d4092b
CW		 7386 return 0;
7387
7388err_unpin:
7389 intel_unpin_fb_obj(obj);
7390err:
8c9f3aaf
JB		 7391 return ret;
7392}
7393
7c9017e5
JB		 7394/*
7395 * On gen7 we currently use the blit ring because (in early silicon at least)
7396 * the render ring doesn't give us interrpts for page flip completion, which
7397 * means clients will hang after the first flip is queued. Fortunately the
7398 * blit ring generates interrupts properly, so use it instead.
7399 */
7400static int intel_gen7_queue_flip(struct drm_device *dev,
7401 struct drm_crtc *crtc,
7402 struct drm_framebuffer *fb,
7403 struct drm_i915_gem_object *obj)
7404{
7405 struct drm_i915_private *dev_priv = dev->dev_private;
7406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7407 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7408 uint32_t plane_bit = 0;
7c9017e5
JB		 7409 int ret;
7410
7411 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7412 if (ret)
83d4092b 7413 goto err;
7c9017e5 7414
cb05d8de
DV		 7415 switch(intel_crtc->plane) {
7416 case PLANE_A:
7417 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7418 break;
7419 case PLANE_B:
7420 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7421 break;
7422 case PLANE_C:
7423 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7424 break;
7425 default:
7426 WARN_ONCE(1, "unknown plane in flip command\n");
7427 ret = -ENODEV;
ab3951eb 7428 goto err_unpin;
cb05d8de
DV		 7429 }
7430
7c9017e5
JB		 7431 ret = intel_ring_begin(ring, 4);
7432 if (ret)
83d4092b 7433 goto err_unpin;
7c9017e5 7434
cb05d8de 7435 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7436 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7437 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7438 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7439
7440 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7441 intel_ring_advance(ring);
83d4092b
CW		 7442 return 0;
7443
7444err_unpin:
7445 intel_unpin_fb_obj(obj);
7446err:
7c9017e5
JB		 7447 return ret;
7448}
7449
8c9f3aaf
JB		 7450static int intel_default_queue_flip(struct drm_device *dev,
7451 struct drm_crtc *crtc,
7452 struct drm_framebuffer *fb,
7453 struct drm_i915_gem_object *obj)
7454{
7455 return -ENODEV;
7456}
7457
6b95a207
KH		 7458static int intel_crtc_page_flip(struct drm_crtc *crtc,
7459 struct drm_framebuffer *fb,
7460 struct drm_pending_vblank_event *event)
7461{
7462 struct drm_device *dev = crtc->dev;
7463 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7464 struct drm_framebuffer *old_fb = crtc->fb;
7465 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7466 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7467 struct intel_unpin_work *work;
8c9f3aaf 7468 unsigned long flags;
52e68630 7469 int ret;
6b95a207 7470
e6a595d2
VS		 7471 /* Can't change pixel format via MI display flips. */
7472 if (fb->pixel_format != crtc->fb->pixel_format)
7473 return -EINVAL;
7474
7475 /*
7476 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7477 * Note that pitch changes could also affect these register.
7478 */
7479 if (INTEL_INFO(dev)->gen > 3 &&
7480 (fb->offsets[0] != crtc->fb->offsets[0] ||
7481 fb->pitches[0] != crtc->fb->pitches[0]))
7482 return -EINVAL;
7483
6b95a207
KH		 7484 work = kzalloc(sizeof *work, GFP_KERNEL);
7485 if (work == NULL)
7486 return -ENOMEM;
7487
6b95a207 7488 work->event = event;
b4a98e57 7489 work->crtc = crtc;
4a35f83b 7490 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7491 INIT_WORK(&work->work, intel_unpin_work_fn);
7492
7317c75e
JB		 7493 ret = drm_vblank_get(dev, intel_crtc->pipe);
7494 if (ret)
7495 goto free_work;
7496
6b95a207
KH		 7497 /* We borrow the event spin lock for protecting unpin_work */
7498 spin_lock_irqsave(&dev->event_lock, flags);
7499 if (intel_crtc->unpin_work) {
7500 spin_unlock_irqrestore(&dev->event_lock, flags);
7501 kfree(work);
7317c75e 7502 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7503
7504 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7505 return -EBUSY;
7506 }
7507 intel_crtc->unpin_work = work;
7508 spin_unlock_irqrestore(&dev->event_lock, flags);
7509
b4a98e57
CW		 7510 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7511 flush_workqueue(dev_priv->wq);
7512
79158103
CW		 7513 ret = i915_mutex_lock_interruptible(dev);
7514 if (ret)
7515 goto cleanup;
6b95a207 7516
75dfca80 7517 /* Reference the objects for the scheduled work. */
05394f39
CW		 7518 drm_gem_object_reference(&work->old_fb_obj->base);
7519 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7520
7521 crtc->fb = fb;
96b099fd 7522
e1f99ce6 7523 work->pending_flip_obj = obj;
e1f99ce6 7524
4e5359cd
SF		 7525 work->enable_stall_check = true;
7526
b4a98e57 7527 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7528 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7529
8c9f3aaf
JB		 7530 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7531 if (ret)
7532 goto cleanup_pending;
6b95a207 7533
7782de3b 7534 intel_disable_fbc(dev);
f047e395 7535 intel_mark_fb_busy(obj);
6b95a207
KH		 7536 mutex_unlock(&dev->struct_mutex);
7537
e5510fac
JB		 7538 trace_i915_flip_request(intel_crtc->plane, obj);
7539
6b95a207 7540 return 0;
96b099fd 7541
8c9f3aaf 7542cleanup_pending:
b4a98e57 7543 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7544 crtc->fb = old_fb;
05394f39
CW		 7545 drm_gem_object_unreference(&work->old_fb_obj->base);
7546 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7547 mutex_unlock(&dev->struct_mutex);
7548
79158103 7549cleanup:
96b099fd
CW		 7550 spin_lock_irqsave(&dev->event_lock, flags);
7551 intel_crtc->unpin_work = NULL;
7552 spin_unlock_irqrestore(&dev->event_lock, flags);
7553
7317c75e
JB		 7554 drm_vblank_put(dev, intel_crtc->pipe);
7555free_work:
96b099fd
CW		 7556 kfree(work);
7557
7558 return ret;
6b95a207
KH		 7559}
7560
f6e5b160 7561static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7562 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7563 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7564};
7565
6ed0f796 7566bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7567{
6ed0f796
DV		 7568 struct intel_encoder *other_encoder;
7569 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7570
6ed0f796
DV		 7571 if (WARN_ON(!crtc))
7572 return false;
7573
7574 list_for_each_entry(other_encoder,
7575 &crtc->dev->mode_config.encoder_list,
7576 base.head) {
7577
7578 if (&other_encoder->new_crtc->base != crtc ||
7579 encoder == other_encoder)
7580 continue;
7581 else
7582 return true;
f47166d2
CW		 7583 }
7584
6ed0f796
DV		 7585 return false;
7586}
47f1c6c9 7587
50f56119
DV		 7588static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7589 struct drm_crtc *crtc)
7590{
7591 struct drm_device *dev;
7592 struct drm_crtc *tmp;
7593 int crtc_mask = 1;
47f1c6c9 7594
50f56119 7595 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7596
50f56119 7597 dev = crtc->dev;
47f1c6c9 7598
50f56119
DV		 7599 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7600 if (tmp == crtc)
7601 break;
7602 crtc_mask <<= 1;
7603 }
47f1c6c9 7604
50f56119
DV		 7605 if (encoder->possible_crtcs & crtc_mask)
7606 return true;
7607 return false;
47f1c6c9 7608}
79e53945 7609
9a935856
DV		 7610/**
7611 * intel_modeset_update_staged_output_state
7612 *
7613 * Updates the staged output configuration state, e.g. after we've read out the
7614 * current hw state.
7615 */
7616static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7617{
9a935856
DV		 7618 struct intel_encoder *encoder;
7619 struct intel_connector *connector;
f6e5b160 7620
9a935856
DV		 7621 list_for_each_entry(connector, &dev->mode_config.connector_list,
7622 base.head) {
7623 connector->new_encoder =
7624 to_intel_encoder(connector->base.encoder);
7625 }
f6e5b160 7626
9a935856
DV		 7627 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7628 base.head) {
7629 encoder->new_crtc =
7630 to_intel_crtc(encoder->base.crtc);
7631 }
f6e5b160
CW		 7632}
7633
9a935856
DV		 7634/**
7635 * intel_modeset_commit_output_state
7636 *
7637 * This function copies the stage display pipe configuration to the real one.
7638 */
7639static void intel_modeset_commit_output_state(struct drm_device *dev)
7640{
7641 struct intel_encoder *encoder;
7642 struct intel_connector *connector;
f6e5b160 7643
9a935856
DV		 7644 list_for_each_entry(connector, &dev->mode_config.connector_list,
7645 base.head) {
7646 connector->base.encoder = &connector->new_encoder->base;
7647 }
f6e5b160 7648
9a935856
DV		 7649 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7650 base.head) {
7651 encoder->base.crtc = &encoder->new_crtc->base;
7652 }
7653}
7654
050f7aeb
DV		 7655static void
7656connected_sink_compute_bpp(struct intel_connector * connector,
7657 struct intel_crtc_config *pipe_config)
7658{
7659 int bpp = pipe_config->pipe_bpp;
7660
7661 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7662 connector->base.base.id,
7663 drm_get_connector_name(&connector->base));
7664
7665 /* Don't use an invalid EDID bpc value */
7666 if (connector->base.display_info.bpc &&
7667 connector->base.display_info.bpc * 3 < bpp) {
7668 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7669 bpp, connector->base.display_info.bpc*3);
7670 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7671 }
7672
7673 /* Clamp bpp to 8 on screens without EDID 1.4 */
7674 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7675 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7676 bpp);
7677 pipe_config->pipe_bpp = 24;
7678 }
7679}
7680
4e53c2e0 7681static int
050f7aeb
DV		 7682compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7683 struct drm_framebuffer *fb,
7684 struct intel_crtc_config *pipe_config)
4e53c2e0 7685{
050f7aeb
DV		 7686 struct drm_device *dev = crtc->base.dev;
7687 struct intel_connector *connector;
4e53c2e0
DV		 7688 int bpp;
7689
d42264b1
DV		 7690 switch (fb->pixel_format) {
7691 case DRM_FORMAT_C8:
4e53c2e0
DV		 7692 bpp = 8*3; /* since we go through a colormap */
7693 break;
d42264b1
DV		 7694 case DRM_FORMAT_XRGB1555:
7695 case DRM_FORMAT_ARGB1555:
7696 /* checked in intel_framebuffer_init already */
7697 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7698 return -EINVAL;
7699 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7700 bpp = 6*3; /* min is 18bpp */
7701 break;
d42264b1
DV		 7702 case DRM_FORMAT_XBGR8888:
7703 case DRM_FORMAT_ABGR8888:
7704 /* checked in intel_framebuffer_init already */
7705 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7706 return -EINVAL;
7707 case DRM_FORMAT_XRGB8888:
7708 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7709 bpp = 8*3;
7710 break;
d42264b1
DV		 7711 case DRM_FORMAT_XRGB2101010:
7712 case DRM_FORMAT_ARGB2101010:
7713 case DRM_FORMAT_XBGR2101010:
7714 case DRM_FORMAT_ABGR2101010:
7715 /* checked in intel_framebuffer_init already */
7716 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7717 return -EINVAL;
4e53c2e0
DV		 7718 bpp = 10*3;
7719 break;
baba133a 7720 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7721 default:
7722 DRM_DEBUG_KMS("unsupported depth\n");
7723 return -EINVAL;
7724 }
7725
4e53c2e0
DV		 7726 pipe_config->pipe_bpp = bpp;
7727
7728 /* Clamp display bpp to EDID value */
7729 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb
DV		 7730 base.head) {
7731 if (connector->base.encoder &&
7732 connector->base.encoder->crtc != crtc)
4e53c2e0
DV		 7733 continue;
7734
050f7aeb 7735 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 7736 }
7737
7738 return bpp;
7739}
7740
c0b03411
DV		 7741static void intel_dump_pipe_config(struct intel_crtc *crtc,
7742 struct intel_crtc_config *pipe_config,
7743 const char *context)
7744{
7745 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7746 context, pipe_name(crtc->pipe));
7747
7748 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7749 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7750 pipe_config->pipe_bpp, pipe_config->dither);
7751 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7752 pipe_config->has_pch_encoder,
7753 pipe_config->fdi_lanes,
7754 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7755 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7756 pipe_config->fdi_m_n.tu);
7757 DRM_DEBUG_KMS("requested mode:\n");
7758 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7759 DRM_DEBUG_KMS("adjusted mode:\n");
7760 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7761 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7762 pipe_config->gmch_pfit.control,
7763 pipe_config->gmch_pfit.pgm_ratios,
7764 pipe_config->gmch_pfit.lvds_border_bits);
7765 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7766 pipe_config->pch_pfit.pos,
7767 pipe_config->pch_pfit.size);
42db64ef 7768 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 7769}
7770
b8cecdf5
DV		 7771static struct intel_crtc_config *
7772intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7773 struct drm_framebuffer *fb,
b8cecdf5 7774 struct drm_display_mode *mode)
ee7b9f93 7775{
7758a113 7776 struct drm_device *dev = crtc->dev;
7758a113
DV		 7777 struct drm_encoder_helper_funcs *encoder_funcs;
7778 struct intel_encoder *encoder;
b8cecdf5 7779 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7780 int plane_bpp, ret = -EINVAL;
7781 bool retry = true;
ee7b9f93 7782
b8cecdf5
DV		 7783 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7784 if (!pipe_config)
7758a113
DV		 7785 return ERR_PTR(-ENOMEM);
7786
b8cecdf5
DV		 7787 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7788 drm_mode_copy(&pipe_config->requested_mode, mode);
eccb140b 7789 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
b8cecdf5 7790
050f7aeb
DV		 7791 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7792 * plane pixel format and any sink constraints into account. Returns the
7793 * source plane bpp so that dithering can be selected on mismatches
7794 * after encoders and crtc also have had their say. */
7795 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7796 fb, pipe_config);
4e53c2e0
DV		 7797 if (plane_bpp < 0)
7798 goto fail;
7799
e29c22c0 7800encoder_retry:
7758a113
DV		 7801 /* Pass our mode to the connectors and the CRTC to give them a chance to
7802 * adjust it according to limitations or connector properties, and also
7803 * a chance to reject the mode entirely.
47f1c6c9 7804 */
7758a113
DV		 7805 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7806 base.head) {
47f1c6c9 7807
7758a113
DV		 7808 if (&encoder->new_crtc->base != crtc)
7809 continue;
7ae89233
DV		 7810
7811 if (encoder->compute_config) {
7812 if (!(encoder->compute_config(encoder, pipe_config))) {
7813 DRM_DEBUG_KMS("Encoder config failure\n");
7814 goto fail;
7815 }
7816
7817 continue;
7818 }
7819
7758a113 7820 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7821 if (!(encoder_funcs->mode_fixup(&encoder->base,
7822 &pipe_config->requested_mode,
7823 &pipe_config->adjusted_mode))) {
7758a113
DV		 7824 DRM_DEBUG_KMS("Encoder fixup failed\n");
7825 goto fail;
7826 }
ee7b9f93 7827 }
47f1c6c9 7828
e29c22c0
DV		 7829 ret = intel_crtc_compute_config(crtc, pipe_config);
7830 if (ret < 0) {
7758a113
DV		 7831 DRM_DEBUG_KMS("CRTC fixup failed\n");
7832 goto fail;
ee7b9f93 7833 }
e29c22c0
DV		 7834
7835 if (ret == RETRY) {
7836 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7837 ret = -EINVAL;
7838 goto fail;
7839 }
7840
7841 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7842 retry = false;
7843 goto encoder_retry;
7844 }
7845
4e53c2e0
DV		 7846 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7847 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7848 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7849
b8cecdf5 7850 return pipe_config;
7758a113 7851fail:
b8cecdf5 7852 kfree(pipe_config);
e29c22c0 7853 return ERR_PTR(ret);
ee7b9f93 7854}
47f1c6c9 7855
e2e1ed41
DV		 7856/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7857 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7858static void
7859intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7860 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7861{
7862 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7863 struct drm_device *dev = crtc->dev;
7864 struct intel_encoder *encoder;
7865 struct intel_connector *connector;
7866 struct drm_crtc *tmp_crtc;
79e53945 7867
e2e1ed41 7868 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7869
e2e1ed41
DV		 7870 /* Check which crtcs have changed outputs connected to them, these need
7871 * to be part of the prepare_pipes mask. We don't (yet) support global
7872 * modeset across multiple crtcs, so modeset_pipes will only have one
7873 * bit set at most. */
7874 list_for_each_entry(connector, &dev->mode_config.connector_list,
7875 base.head) {
7876 if (connector->base.encoder == &connector->new_encoder->base)
7877 continue;
79e53945 7878
e2e1ed41
DV		 7879 if (connector->base.encoder) {
7880 tmp_crtc = connector->base.encoder->crtc;
7881
7882 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7883 }
7884
7885 if (connector->new_encoder)
7886 *prepare_pipes |=
7887 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7888 }
7889
e2e1ed41
DV		 7890 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7891 base.head) {
7892 if (encoder->base.crtc == &encoder->new_crtc->base)
7893 continue;
7894
7895 if (encoder->base.crtc) {
7896 tmp_crtc = encoder->base.crtc;
7897
7898 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7899 }
7900
7901 if (encoder->new_crtc)
7902 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7903 }
7904
e2e1ed41
DV		 7905 /* Check for any pipes that will be fully disabled ... */
7906 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7907 base.head) {
7908 bool used = false;
22fd0fab 7909
e2e1ed41
DV		 7910 /* Don't try to disable disabled crtcs. */
7911 if (!intel_crtc->base.enabled)
7912 continue;
7e7d76c3 7913
e2e1ed41
DV		 7914 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7915 base.head) {
7916 if (encoder->new_crtc == intel_crtc)
7917 used = true;
7918 }
7919
7920 if (!used)
7921 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7922 }
7923
e2e1ed41
DV		 7924
7925 /* set_mode is also used to update properties on life display pipes. */
7926 intel_crtc = to_intel_crtc(crtc);
7927 if (crtc->enabled)
7928 *prepare_pipes |= 1 << intel_crtc->pipe;
7929
b6c5164d
DV		 7930 /*
7931 * For simplicity do a full modeset on any pipe where the output routing
7932 * changed. We could be more clever, but that would require us to be
7933 * more careful with calling the relevant encoder->mode_set functions.
7934 */
e2e1ed41
DV		 7935 if (*prepare_pipes)
7936 *modeset_pipes = *prepare_pipes;
7937
7938 /* ... and mask these out. */
7939 *modeset_pipes &= ~(*disable_pipes);
7940 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7941
7942 /*
7943 * HACK: We don't (yet) fully support global modesets. intel_set_config
7944 * obies this rule, but the modeset restore mode of
7945 * intel_modeset_setup_hw_state does not.
7946 */
7947 *modeset_pipes &= 1 << intel_crtc->pipe;
7948 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 7949
7950 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7951 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 7952}
79e53945 7953
ea9d758d 7954static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7955{
ea9d758d 7956 struct drm_encoder *encoder;
f6e5b160 7957 struct drm_device *dev = crtc->dev;
f6e5b160 7958
ea9d758d
DV		 7959 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7960 if (encoder->crtc == crtc)
7961 return true;
7962
7963 return false;
7964}
7965
7966static void
7967intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7968{
7969 struct intel_encoder *intel_encoder;
7970 struct intel_crtc *intel_crtc;
7971 struct drm_connector *connector;
7972
7973 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7974 base.head) {
7975 if (!intel_encoder->base.crtc)
7976 continue;
7977
7978 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7979
7980 if (prepare_pipes & (1 << intel_crtc->pipe))
7981 intel_encoder->connectors_active = false;
7982 }
7983
7984 intel_modeset_commit_output_state(dev);
7985
7986 /* Update computed state. */
7987 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7988 base.head) {
7989 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7990 }
7991
7992 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7993 if (!connector->encoder || !connector->encoder->crtc)
7994 continue;
7995
7996 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7997
7998 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7999 struct drm_property *dpms_property =
8000 dev->mode_config.dpms_property;
8001
ea9d758d 8002 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8003 drm_object_property_set_value(&connector->base,
68d34720
DV		 8004 dpms_property,
8005 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8006
8007 intel_encoder = to_intel_encoder(connector->encoder);
8008 intel_encoder->connectors_active = true;
8009 }
8010 }
8011
8012}
8013
25c5b266
DV		 8014#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8015 list_for_each_entry((intel_crtc), \
8016 &(dev)->mode_config.crtc_list, \
8017 base.head) \
0973f18f 8018 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8019
0e8ffe1b 8020static bool
2fa2fe9a
DV		 8021intel_pipe_config_compare(struct drm_device *dev,
8022 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8023 struct intel_crtc_config *pipe_config)
8024{
08a24034
DV		 8025#define PIPE_CONF_CHECK_I(name) \
8026 if (current_config->name != pipe_config->name) { \
8027 DRM_ERROR("mismatch in " #name " " \
8028 "(expected %i, found %i)\n", \
8029 current_config->name, \
8030 pipe_config->name); \
8031 return false; \
88adfff1
DV		 8032 }
8033
1bd1bd80
DV		 8034#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8035 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8036 DRM_ERROR("mismatch in " #name " " \
8037 "(expected %i, found %i)\n", \
8038 current_config->name & (mask), \
8039 pipe_config->name & (mask)); \
8040 return false; \
8041 }
8042
eccb140b
DV		 8043 PIPE_CONF_CHECK_I(cpu_transcoder);
8044
08a24034
DV		 8045 PIPE_CONF_CHECK_I(has_pch_encoder);
8046 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8047 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8048 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8049 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8050 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8051 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8052
1bd1bd80
DV		 8053 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8054 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8055 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8056 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8057 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8058 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8059
8060 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8061 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8062 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8063 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8064 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8065 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8066
8067 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8068 DRM_MODE_FLAG_INTERLACE);
8069
045ac3b5
JB		 8070 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8071 DRM_MODE_FLAG_PHSYNC);
8072 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8073 DRM_MODE_FLAG_NHSYNC);
8074 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8075 DRM_MODE_FLAG_PVSYNC);
8076 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8077 DRM_MODE_FLAG_NVSYNC);
8078
1bd1bd80
DV		 8079 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8080 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8081
2fa2fe9a
DV		 8082 PIPE_CONF_CHECK_I(gmch_pfit.control);
8083 /* pfit ratios are autocomputed by the hw on gen4+ */
8084 if (INTEL_INFO(dev)->gen < 4)
8085 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8086 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8087 PIPE_CONF_CHECK_I(pch_pfit.pos);
8088 PIPE_CONF_CHECK_I(pch_pfit.size);
8089
42db64ef
PZ		 8090 PIPE_CONF_CHECK_I(ips_enabled);
8091
08a24034 8092#undef PIPE_CONF_CHECK_I
1bd1bd80 8093#undef PIPE_CONF_CHECK_FLAGS
627eb5a3 8094
0e8ffe1b
DV		 8095 return true;
8096}
8097
b980514c 8098void
8af6cf88
DV		 8099intel_modeset_check_state(struct drm_device *dev)
8100{
0e8ffe1b 8101 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 8102 struct intel_crtc *crtc;
8103 struct intel_encoder *encoder;
8104 struct intel_connector *connector;
0e8ffe1b 8105 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8106
8107 list_for_each_entry(connector, &dev->mode_config.connector_list,
8108 base.head) {
8109 /* This also checks the encoder/connector hw state with the
8110 * ->get_hw_state callbacks. */
8111 intel_connector_check_state(connector);
8112
8113 WARN(&connector->new_encoder->base != connector->base.encoder,
8114 "connector's staged encoder doesn't match current encoder\n");
8115 }
8116
8117 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8118 base.head) {
8119 bool enabled = false;
8120 bool active = false;
8121 enum pipe pipe, tracked_pipe;
8122
8123 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8124 encoder->base.base.id,
8125 drm_get_encoder_name(&encoder->base));
8126
8127 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8128 "encoder's stage crtc doesn't match current crtc\n");
8129 WARN(encoder->connectors_active && !encoder->base.crtc,
8130 "encoder's active_connectors set, but no crtc\n");
8131
8132 list_for_each_entry(connector, &dev->mode_config.connector_list,
8133 base.head) {
8134 if (connector->base.encoder != &encoder->base)
8135 continue;
8136 enabled = true;
8137 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8138 active = true;
8139 }
8140 WARN(!!encoder->base.crtc != enabled,
8141 "encoder's enabled state mismatch "
8142 "(expected %i, found %i)\n",
8143 !!encoder->base.crtc, enabled);
8144 WARN(active && !encoder->base.crtc,
8145 "active encoder with no crtc\n");
8146
8147 WARN(encoder->connectors_active != active,
8148 "encoder's computed active state doesn't match tracked active state "
8149 "(expected %i, found %i)\n", active, encoder->connectors_active);
8150
8151 active = encoder->get_hw_state(encoder, &pipe);
8152 WARN(active != encoder->connectors_active,
8153 "encoder's hw state doesn't match sw tracking "
8154 "(expected %i, found %i)\n",
8155 encoder->connectors_active, active);
8156
8157 if (!encoder->base.crtc)
8158 continue;
8159
8160 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8161 WARN(active && pipe != tracked_pipe,
8162 "active encoder's pipe doesn't match"
8163 "(expected %i, found %i)\n",
8164 tracked_pipe, pipe);
8165
8166 }
8167
8168 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8169 base.head) {
8170 bool enabled = false;
8171 bool active = false;
8172
045ac3b5
JB		 8173 memset(&pipe_config, 0, sizeof(pipe_config));
8174
8af6cf88
DV		 8175 DRM_DEBUG_KMS("[CRTC:%d]\n",
8176 crtc->base.base.id);
8177
8178 WARN(crtc->active && !crtc->base.enabled,
8179 "active crtc, but not enabled in sw tracking\n");
8180
8181 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8182 base.head) {
8183 if (encoder->base.crtc != &crtc->base)
8184 continue;
8185 enabled = true;
8186 if (encoder->connectors_active)
8187 active = true;
045ac3b5
JB		 8188 if (encoder->get_config)
8189 encoder->get_config(encoder, &pipe_config);
8af6cf88
DV		 8190 }
8191 WARN(active != crtc->active,
8192 "crtc's computed active state doesn't match tracked active state "
8193 "(expected %i, found %i)\n", active, crtc->active);
8194 WARN(enabled != crtc->base.enabled,
8195 "crtc's computed enabled state doesn't match tracked enabled state "
8196 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8197
0e8ffe1b
DV		 8198 active = dev_priv->display.get_pipe_config(crtc,
8199 &pipe_config);
8200 WARN(crtc->active != active,
8201 "crtc active state doesn't match with hw state "
8202 "(expected %i, found %i)\n", crtc->active, active);
8203
c0b03411
DV		 8204 if (active &&
8205 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8206 WARN(1, "pipe state doesn't match!\n");
8207 intel_dump_pipe_config(crtc, &pipe_config,
8208 "[hw state]");
8209 intel_dump_pipe_config(crtc, &crtc->config,
8210 "[sw state]");
8211 }
8af6cf88
DV		 8212 }
8213}
8214
f30da187
DV		 8215static int __intel_set_mode(struct drm_crtc *crtc,
8216 struct drm_display_mode *mode,
8217 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8218{
8219 struct drm_device *dev = crtc->dev;
dbf2b54e 8220 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8221 struct drm_display_mode *saved_mode, *saved_hwmode;
8222 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8223 struct intel_crtc *intel_crtc;
8224 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8225 int ret = 0;
a6778b3c 8226
3ac18232 8227 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8228 if (!saved_mode)
8229 return -ENOMEM;
3ac18232 8230 saved_hwmode = saved_mode + 1;
a6778b3c 8231
e2e1ed41 8232 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8233 &prepare_pipes, &disable_pipes);
8234
3ac18232
TG		 8235 *saved_hwmode = crtc->hwmode;
8236 *saved_mode = crtc->mode;
a6778b3c 8237
25c5b266
DV		 8238 /* Hack: Because we don't (yet) support global modeset on multiple
8239 * crtcs, we don't keep track of the new mode for more than one crtc.
8240 * Hence simply check whether any bit is set in modeset_pipes in all the
8241 * pieces of code that are not yet converted to deal with mutliple crtcs
8242 * changing their mode at the same time. */
25c5b266 8243 if (modeset_pipes) {
4e53c2e0 8244 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8245 if (IS_ERR(pipe_config)) {
8246 ret = PTR_ERR(pipe_config);
8247 pipe_config = NULL;
8248
3ac18232 8249 goto out;
25c5b266 8250 }
c0b03411
DV		 8251 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8252 "[modeset]");
25c5b266 8253 }
a6778b3c 8254
460da916
DV		 8255 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8256 intel_crtc_disable(&intel_crtc->base);
8257
ea9d758d
DV		 8258 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8259 if (intel_crtc->base.enabled)
8260 dev_priv->display.crtc_disable(&intel_crtc->base);
8261 }
a6778b3c 8262
6c4c86f5
DV		 8263 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8264 * to set it here already despite that we pass it down the callchain.
f6e5b160 8265 */
b8cecdf5 8266 if (modeset_pipes) {
25c5b266 8267 crtc->mode = *mode;
b8cecdf5
DV		 8268 /* mode_set/enable/disable functions rely on a correct pipe
8269 * config. */
8270 to_intel_crtc(crtc)->config = *pipe_config;
8271 }
7758a113 8272
ea9d758d
DV		 8273 /* Only after disabling all output pipelines that will be changed can we
8274 * update the the output configuration. */
8275 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8276
47fab737
DV		 8277 if (dev_priv->display.modeset_global_resources)
8278 dev_priv->display.modeset_global_resources(dev);
8279
a6778b3c
DV		 8280 /* Set up the DPLL and any encoders state that needs to adjust or depend
8281 * on the DPLL.
f6e5b160 8282 */
25c5b266 8283 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8284 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8285 x, y, fb);
8286 if (ret)
8287 goto done;
a6778b3c
DV		 8288 }
8289
8290 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8291 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8292 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8293
25c5b266
DV		 8294 if (modeset_pipes) {
8295 /* Store real post-adjustment hardware mode. */
b8cecdf5 8296 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8297
25c5b266
DV		 8298 /* Calculate and store various constants which
8299 * are later needed by vblank and swap-completion
8300 * timestamping. They are derived from true hwmode.
8301 */
8302 drm_calc_timestamping_constants(crtc);
8303 }
a6778b3c
DV		 8304
8305 /* FIXME: add subpixel order */
8306done:
c0c36b94 8307 if (ret && crtc->enabled) {
3ac18232
TG		 8308 crtc->hwmode = *saved_hwmode;
8309 crtc->mode = *saved_mode;
a6778b3c
DV		 8310 }
8311
3ac18232 8312out:
b8cecdf5 8313 kfree(pipe_config);
3ac18232 8314 kfree(saved_mode);
a6778b3c 8315 return ret;
f6e5b160
CW		 8316}
8317
f30da187
DV		 8318int intel_set_mode(struct drm_crtc *crtc,
8319 struct drm_display_mode *mode,
8320 int x, int y, struct drm_framebuffer *fb)
8321{
8322 int ret;
8323
8324 ret = __intel_set_mode(crtc, mode, x, y, fb);
8325
8326 if (ret == 0)
8327 intel_modeset_check_state(crtc->dev);
8328
8329 return ret;
8330}
8331
c0c36b94
CW		 8332void intel_crtc_restore_mode(struct drm_crtc *crtc)
8333{
8334 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8335}
8336
25c5b266
DV		 8337#undef for_each_intel_crtc_masked
8338
d9e55608
DV		 8339static void intel_set_config_free(struct intel_set_config *config)
8340{
8341 if (!config)
8342 return;
8343
1aa4b628
DV		 8344 kfree(config->save_connector_encoders);
8345 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8346 kfree(config);
8347}
8348
85f9eb71
DV		 8349static int intel_set_config_save_state(struct drm_device *dev,
8350 struct intel_set_config *config)
8351{
85f9eb71
DV		 8352 struct drm_encoder *encoder;
8353 struct drm_connector *connector;
8354 int count;
8355
1aa4b628
DV		 8356 config->save_encoder_crtcs =
8357 kcalloc(dev->mode_config.num_encoder,
8358 sizeof(struct drm_crtc *), GFP_KERNEL);
8359 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8360 return -ENOMEM;
8361
1aa4b628
DV		 8362 config->save_connector_encoders =
8363 kcalloc(dev->mode_config.num_connector,
8364 sizeof(struct drm_encoder *), GFP_KERNEL);
8365 if (!config->save_connector_encoders)
85f9eb71
DV		 8366 return -ENOMEM;
8367
8368 /* Copy data. Note that driver private data is not affected.
8369 * Should anything bad happen only the expected state is
8370 * restored, not the drivers personal bookkeeping.
8371 */
85f9eb71
DV		 8372 count = 0;
8373 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8374 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8375 }
8376
8377 count = 0;
8378 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8379 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8380 }
8381
8382 return 0;
8383}
8384
8385static void intel_set_config_restore_state(struct drm_device *dev,
8386 struct intel_set_config *config)
8387{
9a935856
DV		 8388 struct intel_encoder *encoder;
8389 struct intel_connector *connector;
85f9eb71
DV		 8390 int count;
8391
85f9eb71 8392 count = 0;
9a935856
DV		 8393 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8394 encoder->new_crtc =
8395 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8396 }
8397
8398 count = 0;
9a935856
DV		 8399 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8400 connector->new_encoder =
8401 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8402 }
8403}
8404
5e2b584e
DV		 8405static void
8406intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8407 struct intel_set_config *config)
8408{
8409
8410 /* We should be able to check here if the fb has the same properties
8411 * and then just flip_or_move it */
8412 if (set->crtc->fb != set->fb) {
8413 /* If we have no fb then treat it as a full mode set */
8414 if (set->crtc->fb == NULL) {
8415 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8416 config->mode_changed = true;
8417 } else if (set->fb == NULL) {
8418 config->mode_changed = true;
72f4901e
DV		 8419 } else if (set->fb->pixel_format !=
8420 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8421 config->mode_changed = true;
8422 } else
8423 config->fb_changed = true;
8424 }
8425
835c5873 8426 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8427 config->fb_changed = true;
8428
8429 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8430 DRM_DEBUG_KMS("modes are different, full mode set\n");
8431 drm_mode_debug_printmodeline(&set->crtc->mode);
8432 drm_mode_debug_printmodeline(set->mode);
8433 config->mode_changed = true;
8434 }
8435}
8436
2e431051 8437static int
9a935856
DV		 8438intel_modeset_stage_output_state(struct drm_device *dev,
8439 struct drm_mode_set *set,
8440 struct intel_set_config *config)
50f56119 8441{
85f9eb71 8442 struct drm_crtc *new_crtc;
9a935856
DV		 8443 struct intel_connector *connector;
8444 struct intel_encoder *encoder;
2e431051 8445 int count, ro;
50f56119 8446
9abdda74 8447 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8448 * of connectors. For paranoia, double-check this. */
8449 WARN_ON(!set->fb && (set->num_connectors != 0));
8450 WARN_ON(set->fb && (set->num_connectors == 0));
8451
50f56119 8452 count = 0;
9a935856
DV		 8453 list_for_each_entry(connector, &dev->mode_config.connector_list,
8454 base.head) {
8455 /* Otherwise traverse passed in connector list and get encoders
8456 * for them. */
50f56119 8457 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8458 if (set->connectors[ro] == &connector->base) {
8459 connector->new_encoder = connector->encoder;
50f56119
DV		 8460 break;
8461 }
8462 }
8463
9a935856
DV		 8464 /* If we disable the crtc, disable all its connectors. Also, if
8465 * the connector is on the changing crtc but not on the new
8466 * connector list, disable it. */
8467 if ((!set->fb || ro == set->num_connectors) &&
8468 connector->base.encoder &&
8469 connector->base.encoder->crtc == set->crtc) {
8470 connector->new_encoder = NULL;
8471
8472 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8473 connector->base.base.id,
8474 drm_get_connector_name(&connector->base));
8475 }
8476
8477
8478 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8479 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8480 config->mode_changed = true;
50f56119
DV		 8481 }
8482 }
9a935856 8483 /* connector->new_encoder is now updated for all connectors. */
50f56119 8484
9a935856 8485 /* Update crtc of enabled connectors. */
50f56119 8486 count = 0;
9a935856
DV		 8487 list_for_each_entry(connector, &dev->mode_config.connector_list,
8488 base.head) {
8489 if (!connector->new_encoder)
50f56119
DV		 8490 continue;
8491
9a935856 8492 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8493
8494 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8495 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8496 new_crtc = set->crtc;
8497 }
8498
8499 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8500 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8501 new_crtc)) {
5e2b584e 8502 return -EINVAL;
50f56119 8503 }
9a935856
DV		 8504 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8505
8506 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8507 connector->base.base.id,
8508 drm_get_connector_name(&connector->base),
8509 new_crtc->base.id);
8510 }
8511
8512 /* Check for any encoders that needs to be disabled. */
8513 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8514 base.head) {
8515 list_for_each_entry(connector,
8516 &dev->mode_config.connector_list,
8517 base.head) {
8518 if (connector->new_encoder == encoder) {
8519 WARN_ON(!connector->new_encoder->new_crtc);
8520
8521 goto next_encoder;
8522 }
8523 }
8524 encoder->new_crtc = NULL;
8525next_encoder:
8526 /* Only now check for crtc changes so we don't miss encoders
8527 * that will be disabled. */
8528 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8529 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8530 config->mode_changed = true;
50f56119
DV		 8531 }
8532 }
9a935856 8533 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8534
2e431051
DV		 8535 return 0;
8536}
8537
8538static int intel_crtc_set_config(struct drm_mode_set *set)
8539{
8540 struct drm_device *dev;
2e431051
DV		 8541 struct drm_mode_set save_set;
8542 struct intel_set_config *config;
8543 int ret;
2e431051 8544
8d3e375e
DV		 8545 BUG_ON(!set);
8546 BUG_ON(!set->crtc);
8547 BUG_ON(!set->crtc->helper_private);
2e431051 8548
7e53f3a4
DV		 8549 /* Enforce sane interface api - has been abused by the fb helper. */
8550 BUG_ON(!set->mode && set->fb);
8551 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8552
2e431051
DV		 8553 if (set->fb) {
8554 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8555 set->crtc->base.id, set->fb->base.id,
8556 (int)set->num_connectors, set->x, set->y);
8557 } else {
8558 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8559 }
8560
8561 dev = set->crtc->dev;
8562
8563 ret = -ENOMEM;
8564 config = kzalloc(sizeof(*config), GFP_KERNEL);
8565 if (!config)
8566 goto out_config;
8567
8568 ret = intel_set_config_save_state(dev, config);
8569 if (ret)
8570 goto out_config;
8571
8572 save_set.crtc = set->crtc;
8573 save_set.mode = &set->crtc->mode;
8574 save_set.x = set->crtc->x;
8575 save_set.y = set->crtc->y;
8576 save_set.fb = set->crtc->fb;
8577
8578 /* Compute whether we need a full modeset, only an fb base update or no
8579 * change at all. In the future we might also check whether only the
8580 * mode changed, e.g. for LVDS where we only change the panel fitter in
8581 * such cases. */
8582 intel_set_config_compute_mode_changes(set, config);
8583
9a935856 8584 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8585 if (ret)
8586 goto fail;
8587
5e2b584e 8588 if (config->mode_changed) {
c0c36b94
CW		 8589 ret = intel_set_mode(set->crtc, set->mode,
8590 set->x, set->y, set->fb);
8591 if (ret) {
8592 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8593 set->crtc->base.id, ret);
87f1faa6
DV		 8594 goto fail;
8595 }
5e2b584e 8596 } else if (config->fb_changed) {
4878cae2
VS		 8597 intel_crtc_wait_for_pending_flips(set->crtc);
8598
4f660f49 8599 ret = intel_pipe_set_base(set->crtc,
94352cf9 8600 set->x, set->y, set->fb);
50f56119
DV		 8601 }
8602
d9e55608
DV		 8603 intel_set_config_free(config);
8604
50f56119
DV		 8605 return 0;
8606
8607fail:
85f9eb71 8608 intel_set_config_restore_state(dev, config);
50f56119
DV		 8609
8610 /* Try to restore the config */
5e2b584e 8611 if (config->mode_changed &&
c0c36b94
CW		 8612 intel_set_mode(save_set.crtc, save_set.mode,
8613 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8614 DRM_ERROR("failed to restore config after modeset failure\n");
8615
d9e55608
DV		 8616out_config:
8617 intel_set_config_free(config);
50f56119
DV		 8618 return ret;
8619}
f6e5b160
CW		 8620
8621static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8622 .cursor_set = intel_crtc_cursor_set,
8623 .cursor_move = intel_crtc_cursor_move,
8624 .gamma_set = intel_crtc_gamma_set,
50f56119 8625 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8626 .destroy = intel_crtc_destroy,
8627 .page_flip = intel_crtc_page_flip,
8628};
8629
79f689aa
PZ		 8630static void intel_cpu_pll_init(struct drm_device *dev)
8631{
affa9354 8632 if (HAS_DDI(dev))
79f689aa
PZ		 8633 intel_ddi_pll_init(dev);
8634}
8635
ee7b9f93
JB		 8636static void intel_pch_pll_init(struct drm_device *dev)
8637{
8638 drm_i915_private_t *dev_priv = dev->dev_private;
8639 int i;
8640
8641 if (dev_priv->num_pch_pll == 0) {
8642 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8643 return;
8644 }
8645
8646 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8647 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8648 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8649 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8650 }
8651}
8652
b358d0a6 8653static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8654{
22fd0fab 8655 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8656 struct intel_crtc *intel_crtc;
8657 int i;
8658
8659 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8660 if (intel_crtc == NULL)
8661 return;
8662
8663 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8664
8665 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8666 for (i = 0; i < 256; i++) {
8667 intel_crtc->lut_r[i] = i;
8668 intel_crtc->lut_g[i] = i;
8669 intel_crtc->lut_b[i] = i;
8670 }
8671
80824003
JB		 8672 /* Swap pipes & planes for FBC on pre-965 */
8673 intel_crtc->pipe = pipe;
8674 intel_crtc->plane = pipe;
e2e767ab 8675 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8676 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8677 intel_crtc->plane = !pipe;
80824003
JB		 8678 }
8679
22fd0fab
JB		 8680 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8681 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8682 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8683 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8684
79e53945 8685 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8686}
8687
08d7b3d1 8688int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8689 struct drm_file *file)
08d7b3d1 8690{
08d7b3d1 8691 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8692 struct drm_mode_object *drmmode_obj;
8693 struct intel_crtc *crtc;
08d7b3d1 8694
1cff8f6b
DV		 8695 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8696 return -ENODEV;
08d7b3d1 8697
c05422d5
DV		 8698 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8699 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8700
c05422d5 8701 if (!drmmode_obj) {
08d7b3d1
CW		 8702 DRM_ERROR("no such CRTC id\n");
8703 return -EINVAL;
8704 }
8705
c05422d5
DV		 8706 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8707 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8708
c05422d5 8709 return 0;
08d7b3d1
CW		 8710}
8711
66a9278e 8712static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8713{
66a9278e
DV		 8714 struct drm_device *dev = encoder->base.dev;
8715 struct intel_encoder *source_encoder;
79e53945 8716 int index_mask = 0;
79e53945
JB		 8717 int entry = 0;
8718
66a9278e
DV		 8719 list_for_each_entry(source_encoder,
8720 &dev->mode_config.encoder_list, base.head) {
8721
8722 if (encoder == source_encoder)
79e53945 8723 index_mask |= (1 << entry);
66a9278e
DV		 8724
8725 /* Intel hw has only one MUX where enocoders could be cloned. */
8726 if (encoder->cloneable && source_encoder->cloneable)
8727 index_mask |= (1 << entry);
8728
79e53945
JB		 8729 entry++;
8730 }
4ef69c7a 8731
79e53945
JB		 8732 return index_mask;
8733}
8734
4d302442
CW		 8735static bool has_edp_a(struct drm_device *dev)
8736{
8737 struct drm_i915_private *dev_priv = dev->dev_private;
8738
8739 if (!IS_MOBILE(dev))
8740 return false;
8741
8742 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8743 return false;
8744
8745 if (IS_GEN5(dev) &&
8746 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8747 return false;
8748
8749 return true;
8750}
8751
79e53945
JB		 8752static void intel_setup_outputs(struct drm_device *dev)
8753{
725e30ad 8754 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8755 struct intel_encoder *encoder;
cb0953d7 8756 bool dpd_is_edp = false;
f3cfcba6 8757 bool has_lvds;
79e53945 8758
f3cfcba6 8759 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8760 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8761 /* disable the panel fitter on everything but LVDS */
8762 I915_WRITE(PFIT_CONTROL, 0);
8763 }
79e53945 8764
c40c0f5b 8765 if (!IS_ULT(dev))
79935fca 8766 intel_crt_init(dev);
cb0953d7 8767
affa9354 8768 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8769 int found;
8770
8771 /* Haswell uses DDI functions to detect digital outputs */
8772 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8773 /* DDI A only supports eDP */
8774 if (found)
8775 intel_ddi_init(dev, PORT_A);
8776
8777 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8778 * register */
8779 found = I915_READ(SFUSE_STRAP);
8780
8781 if (found & SFUSE_STRAP_DDIB_DETECTED)
8782 intel_ddi_init(dev, PORT_B);
8783 if (found & SFUSE_STRAP_DDIC_DETECTED)
8784 intel_ddi_init(dev, PORT_C);
8785 if (found & SFUSE_STRAP_DDID_DETECTED)
8786 intel_ddi_init(dev, PORT_D);
8787 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8788 int found;
270b3042
DV		 8789 dpd_is_edp = intel_dpd_is_edp(dev);
8790
8791 if (has_edp_a(dev))
8792 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8793
dc0fa718 8794 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8795 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8796 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8797 if (!found)
e2debe91 8798 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8799 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8800 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8801 }
8802
dc0fa718 8803 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8804 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8805
dc0fa718 8806 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8807 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8808
5eb08b69 8809 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8810 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8811
270b3042 8812 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8813 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8814 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8815 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8816 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8817 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8818
dc0fa718 8819 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8820 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8821 PORT_B);
67cfc203
VS		 8822 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8823 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8824 }
103a196f 8825 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8826 bool found = false;
7d57382e 8827
e2debe91 8828 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8829 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8830 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8831 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8832 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8833 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8834 }
27185ae1 8835
e7281eab 8836 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8837 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 8838 }
13520b05
KH		 8839
8840 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8841
e2debe91 8842 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8843 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8844 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8845 }
27185ae1 8846
e2debe91 8847 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8848
b01f2c3a
JB		 8849 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8850 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8851 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 8852 }
e7281eab 8853 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8854 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 8855 }
27185ae1 8856
b01f2c3a 8857 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 8858 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 8859 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 8860 } else if (IS_GEN2(dev))
79e53945
JB		 8861 intel_dvo_init(dev);
8862
103a196f 8863 if (SUPPORTS_TV(dev))
79e53945
JB		 8864 intel_tv_init(dev);
8865
4ef69c7a
CW		 8866 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8867 encoder->base.possible_crtcs = encoder->crtc_mask;
8868 encoder->base.possible_clones =
66a9278e 8869 intel_encoder_clones(encoder);
79e53945 8870 }
47356eb6 8871
dde86e2d 8872 intel_init_pch_refclk(dev);
270b3042
DV		 8873
8874 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8875}
8876
8877static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8878{
8879 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8880
8881 drm_framebuffer_cleanup(fb);
05394f39 8882 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8883
8884 kfree(intel_fb);
8885}
8886
8887static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8888 struct drm_file *file,
79e53945
JB		 8889 unsigned int *handle)
8890{
8891 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8892 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8893
05394f39 8894 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8895}
8896
8897static const struct drm_framebuffer_funcs intel_fb_funcs = {
8898 .destroy = intel_user_framebuffer_destroy,
8899 .create_handle = intel_user_framebuffer_create_handle,
8900};
8901
38651674
DA		 8902int intel_framebuffer_init(struct drm_device *dev,
8903 struct intel_framebuffer *intel_fb,
308e5bcb 8904 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8905 struct drm_i915_gem_object *obj)
79e53945 8906{
79e53945
JB		 8907 int ret;
8908
c16ed4be
CW		 8909 if (obj->tiling_mode == I915_TILING_Y) {
8910 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8911 return -EINVAL;
c16ed4be 8912 }
57cd6508 8913
c16ed4be
CW		 8914 if (mode_cmd->pitches[0] & 63) {
8915 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8916 mode_cmd->pitches[0]);
57cd6508 8917 return -EINVAL;
c16ed4be 8918 }
57cd6508 8919
5d7bd705 8920 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8921 if (mode_cmd->pitches[0] > 32768) {
8922 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8923 mode_cmd->pitches[0]);
5d7bd705 8924 return -EINVAL;
c16ed4be 8925 }
5d7bd705
VS		 8926
8927 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8928 mode_cmd->pitches[0] != obj->stride) {
8929 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8930 mode_cmd->pitches[0], obj->stride);
5d7bd705 8931 return -EINVAL;
c16ed4be 8932 }
5d7bd705 8933
57779d06 8934 /* Reject formats not supported by any plane early. */
308e5bcb 8935 switch (mode_cmd->pixel_format) {
57779d06 8936 case DRM_FORMAT_C8:
04b3924d
VS		 8937 case DRM_FORMAT_RGB565:
8938 case DRM_FORMAT_XRGB8888:
8939 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8940 break;
8941 case DRM_FORMAT_XRGB1555:
8942 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8943 if (INTEL_INFO(dev)->gen > 3) {
8944 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8945 return -EINVAL;
c16ed4be 8946 }
57779d06
VS		 8947 break;
8948 case DRM_FORMAT_XBGR8888:
8949 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8950 case DRM_FORMAT_XRGB2101010:
8951 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8952 case DRM_FORMAT_XBGR2101010:
8953 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8954 if (INTEL_INFO(dev)->gen < 4) {
8955 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8956 return -EINVAL;
c16ed4be 8957 }
b5626747 8958 break;
04b3924d
VS		 8959 case DRM_FORMAT_YUYV:
8960 case DRM_FORMAT_UYVY:
8961 case DRM_FORMAT_YVYU:
8962 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8963 if (INTEL_INFO(dev)->gen < 5) {
8964 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8965 return -EINVAL;
c16ed4be 8966 }
57cd6508
CW		 8967 break;
8968 default:
c16ed4be 8969 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8970 return -EINVAL;
8971 }
8972
90f9a336
VS		 8973 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8974 if (mode_cmd->offsets[0] != 0)
8975 return -EINVAL;
8976
c7d73f6a
DV		 8977 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8978 intel_fb->obj = obj;
8979
79e53945
JB		 8980 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8981 if (ret) {
8982 DRM_ERROR("framebuffer init failed %d\n", ret);
8983 return ret;
8984 }
8985
79e53945
JB		 8986 return 0;
8987}
8988
79e53945
JB		 8989static struct drm_framebuffer *
8990intel_user_framebuffer_create(struct drm_device *dev,
8991 struct drm_file *filp,
308e5bcb 8992 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8993{
05394f39 8994 struct drm_i915_gem_object *obj;
79e53945 8995
308e5bcb
JB		 8996 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8997 mode_cmd->handles[0]));
c8725226 8998 if (&obj->base == NULL)
cce13ff7 8999 return ERR_PTR(-ENOENT);
79e53945 9000
d2dff872 9001 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9002}
9003
79e53945 9004static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9005 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9006 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9007};
9008
e70236a8
JB		 9009/* Set up chip specific display functions */
9010static void intel_init_display(struct drm_device *dev)
9011{
9012 struct drm_i915_private *dev_priv = dev->dev_private;
9013
affa9354 9014 if (HAS_DDI(dev)) {
0e8ffe1b 9015 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9016 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9017 dev_priv->display.crtc_enable = haswell_crtc_enable;
9018 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9019 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9020 dev_priv->display.update_plane = ironlake_update_plane;
9021 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9022 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9023 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9024 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9025 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9026 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9027 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9028 } else if (IS_VALLEYVIEW(dev)) {
9029 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9030 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9031 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9032 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9033 dev_priv->display.off = i9xx_crtc_off;
9034 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9035 } else {
0e8ffe1b 9036 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9037 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9038 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9039 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9040 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9041 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9042 }
e70236a8 9043
e70236a8 9044 /* Returns the core display clock speed */
25eb05fc
JB		 9045 if (IS_VALLEYVIEW(dev))
9046 dev_priv->display.get_display_clock_speed =
9047 valleyview_get_display_clock_speed;
9048 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9049 dev_priv->display.get_display_clock_speed =
9050 i945_get_display_clock_speed;
9051 else if (IS_I915G(dev))
9052 dev_priv->display.get_display_clock_speed =
9053 i915_get_display_clock_speed;
f2b115e6 9054 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9055 dev_priv->display.get_display_clock_speed =
9056 i9xx_misc_get_display_clock_speed;
9057 else if (IS_I915GM(dev))
9058 dev_priv->display.get_display_clock_speed =
9059 i915gm_get_display_clock_speed;
9060 else if (IS_I865G(dev))
9061 dev_priv->display.get_display_clock_speed =
9062 i865_get_display_clock_speed;
f0f8a9ce 9063 else if (IS_I85X(dev))
e70236a8
JB		 9064 dev_priv->display.get_display_clock_speed =
9065 i855_get_display_clock_speed;
9066 else /* 852, 830 */
9067 dev_priv->display.get_display_clock_speed =
9068 i830_get_display_clock_speed;
9069
7f8a8569 9070 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9071 if (IS_GEN5(dev)) {
674cf967 9072 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9073 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9074 } else if (IS_GEN6(dev)) {
674cf967 9075 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9076 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9077 } else if (IS_IVYBRIDGE(dev)) {
9078 /* FIXME: detect B0+ stepping and use auto training */
9079 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9080 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9081 dev_priv->display.modeset_global_resources =
9082 ivb_modeset_global_resources;
c82e4d26
ED		 9083 } else if (IS_HASWELL(dev)) {
9084 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9085 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9086 dev_priv->display.modeset_global_resources =
9087 haswell_modeset_global_resources;
a0e63c22 9088 }
6067aaea 9089 } else if (IS_G4X(dev)) {
e0dac65e 9090 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9091 }
8c9f3aaf
JB		 9092
9093 /* Default just returns -ENODEV to indicate unsupported */
9094 dev_priv->display.queue_flip = intel_default_queue_flip;
9095
9096 switch (INTEL_INFO(dev)->gen) {
9097 case 2:
9098 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9099 break;
9100
9101 case 3:
9102 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9103 break;
9104
9105 case 4:
9106 case 5:
9107 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9108 break;
9109
9110 case 6:
9111 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9112 break;
7c9017e5
JB		 9113 case 7:
9114 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9115 break;
8c9f3aaf 9116 }
e70236a8
JB		 9117}
9118
b690e96c
JB		 9119/*
9120 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9121 * resume, or other times. This quirk makes sure that's the case for
9122 * affected systems.
9123 */
0206e353 9124static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9125{
9126 struct drm_i915_private *dev_priv = dev->dev_private;
9127
9128 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9129 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9130}
9131
435793df
KP		 9132/*
9133 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9134 */
9135static void quirk_ssc_force_disable(struct drm_device *dev)
9136{
9137 struct drm_i915_private *dev_priv = dev->dev_private;
9138 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9139 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9140}
9141
4dca20ef 9142/*
5a15ab5b
CE		 9143 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9144 * brightness value
4dca20ef
CE		 9145 */
9146static void quirk_invert_brightness(struct drm_device *dev)
9147{
9148 struct drm_i915_private *dev_priv = dev->dev_private;
9149 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9150 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9151}
9152
b690e96c
JB		 9153struct intel_quirk {
9154 int device;
9155 int subsystem_vendor;
9156 int subsystem_device;
9157 void (*hook)(struct drm_device *dev);
9158};
9159
5f85f176
EE		 9160/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9161struct intel_dmi_quirk {
9162 void (*hook)(struct drm_device *dev);
9163 const struct dmi_system_id (*dmi_id_list)[];
9164};
9165
9166static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9167{
9168 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9169 return 1;
9170}
9171
9172static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9173 {
9174 .dmi_id_list = &(const struct dmi_system_id[]) {
9175 {
9176 .callback = intel_dmi_reverse_brightness,
9177 .ident = "NCR Corporation",
9178 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9179 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9180 },
9181 },
9182 { } /* terminating entry */
9183 },
9184 .hook = quirk_invert_brightness,
9185 },
9186};
9187
c43b5634 9188static struct intel_quirk intel_quirks[] = {
b690e96c 9189 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9190 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9191
b690e96c
JB		 9192 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9193 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9194
b690e96c
JB		 9195 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9196 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9197
ccd0d36e 9198 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9199 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9200 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9201
9202 /* Lenovo U160 cannot use SSC on LVDS */
9203 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9204
9205 /* Sony Vaio Y cannot use SSC on LVDS */
9206 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9207
9208 /* Acer Aspire 5734Z must invert backlight brightness */
9209 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9210
9211 /* Acer/eMachines G725 */
9212 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9213
9214 /* Acer/eMachines e725 */
9215 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9216
9217 /* Acer/Packard Bell NCL20 */
9218 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9219
9220 /* Acer Aspire 4736Z */
9221 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9222};
9223
9224static void intel_init_quirks(struct drm_device *dev)
9225{
9226 struct pci_dev *d = dev->pdev;
9227 int i;
9228
9229 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9230 struct intel_quirk *q = &intel_quirks[i];
9231
9232 if (d->device == q->device &&
9233 (d->subsystem_vendor == q->subsystem_vendor ||
9234 q->subsystem_vendor == PCI_ANY_ID) &&
9235 (d->subsystem_device == q->subsystem_device ||
9236 q->subsystem_device == PCI_ANY_ID))
9237 q->hook(dev);
9238 }
5f85f176
EE		 9239 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9240 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9241 intel_dmi_quirks[i].hook(dev);
9242 }
b690e96c
JB		 9243}
9244
9cce37f4
JB		 9245/* Disable the VGA plane that we never use */
9246static void i915_disable_vga(struct drm_device *dev)
9247{
9248 struct drm_i915_private *dev_priv = dev->dev_private;
9249 u8 sr1;
766aa1c4 9250 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9251
9252 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9253 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9254 sr1 = inb(VGA_SR_DATA);
9255 outb(sr1 | 1<<5, VGA_SR_DATA);
9256 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9257 udelay(300);
9258
9259 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9260 POSTING_READ(vga_reg);
9261}
9262
f817586c
DV		 9263void intel_modeset_init_hw(struct drm_device *dev)
9264{
fa42e23c 9265 intel_init_power_well(dev);
0232e927 9266
a8f78b58
ED		 9267 intel_prepare_ddi(dev);
9268
f817586c
DV		 9269 intel_init_clock_gating(dev);
9270
79f5b2c7 9271 mutex_lock(&dev->struct_mutex);
8090c6b9 9272 intel_enable_gt_powersave(dev);
79f5b2c7 9273 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9274}
9275
7d708ee4
ID		 9276void intel_modeset_suspend_hw(struct drm_device *dev)
9277{
9278 intel_suspend_hw(dev);
9279}
9280
79e53945
JB		 9281void intel_modeset_init(struct drm_device *dev)
9282{
652c393a 9283 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9284 int i, j, ret;
79e53945
JB		 9285
9286 drm_mode_config_init(dev);
9287
9288 dev->mode_config.min_width = 0;
9289 dev->mode_config.min_height = 0;
9290
019d96cb
DA		 9291 dev->mode_config.preferred_depth = 24;
9292 dev->mode_config.prefer_shadow = 1;
9293
e6ecefaa 9294 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9295
b690e96c
JB		 9296 intel_init_quirks(dev);
9297
1fa61106
ED		 9298 intel_init_pm(dev);
9299
e3c74757
BW		 9300 if (INTEL_INFO(dev)->num_pipes == 0)
9301 return;
9302
e70236a8
JB		 9303 intel_init_display(dev);
9304
a6c45cf0
CW		 9305 if (IS_GEN2(dev)) {
9306 dev->mode_config.max_width = 2048;
9307 dev->mode_config.max_height = 2048;
9308 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9309 dev->mode_config.max_width = 4096;
9310 dev->mode_config.max_height = 4096;
79e53945 9311 } else {
a6c45cf0
CW		 9312 dev->mode_config.max_width = 8192;
9313 dev->mode_config.max_height = 8192;
79e53945 9314 }
5d4545ae 9315 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9316
28c97730 9317 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9318 INTEL_INFO(dev)->num_pipes,
9319 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9320
7eb552ae 9321 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9322 intel_crtc_init(dev, i);
7f1f3851
JB		 9323 for (j = 0; j < dev_priv->num_plane; j++) {
9324 ret = intel_plane_init(dev, i, j);
9325 if (ret)
06da8da2
VS		 9326 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9327 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9328 }
79e53945
JB		 9329 }
9330
79f689aa 9331 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9332 intel_pch_pll_init(dev);
9333
9cce37f4
JB		 9334 /* Just disable it once at startup */
9335 i915_disable_vga(dev);
79e53945 9336 intel_setup_outputs(dev);
11be49eb
CW		 9337
9338 /* Just in case the BIOS is doing something questionable. */
9339 intel_disable_fbc(dev);
2c7111db
CW		 9340}
9341
24929352
DV		 9342static void
9343intel_connector_break_all_links(struct intel_connector *connector)
9344{
9345 connector->base.dpms = DRM_MODE_DPMS_OFF;
9346 connector->base.encoder = NULL;
9347 connector->encoder->connectors_active = false;
9348 connector->encoder->base.crtc = NULL;
9349}
9350
7fad798e
DV		 9351static void intel_enable_pipe_a(struct drm_device *dev)
9352{
9353 struct intel_connector *connector;
9354 struct drm_connector *crt = NULL;
9355 struct intel_load_detect_pipe load_detect_temp;
9356
9357 /* We can't just switch on the pipe A, we need to set things up with a
9358 * proper mode and output configuration. As a gross hack, enable pipe A
9359 * by enabling the load detect pipe once. */
9360 list_for_each_entry(connector,
9361 &dev->mode_config.connector_list,
9362 base.head) {
9363 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9364 crt = &connector->base;
9365 break;
9366 }
9367 }
9368
9369 if (!crt)
9370 return;
9371
9372 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9373 intel_release_load_detect_pipe(crt, &load_detect_temp);
9374
652c393a 9375
7fad798e
DV		 9376}
9377
fa555837
DV		 9378static bool
9379intel_check_plane_mapping(struct intel_crtc *crtc)
9380{
7eb552ae
BW		 9381 struct drm_device *dev = crtc->base.dev;
9382 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9383 u32 reg, val;
9384
7eb552ae 9385 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9386 return true;
9387
9388 reg = DSPCNTR(!crtc->plane);
9389 val = I915_READ(reg);
9390
9391 if ((val & DISPLAY_PLANE_ENABLE) &&
9392 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9393 return false;
9394
9395 return true;
9396}
9397
24929352
DV		 9398static void intel_sanitize_crtc(struct intel_crtc *crtc)
9399{
9400 struct drm_device *dev = crtc->base.dev;
9401 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9402 u32 reg;
24929352 9403
24929352 9404 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9405 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9406 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9407
9408 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9409 * disable the crtc (and hence change the state) if it is wrong. Note
9410 * that gen4+ has a fixed plane -> pipe mapping. */
9411 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9412 struct intel_connector *connector;
9413 bool plane;
9414
24929352
DV		 9415 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9416 crtc->base.base.id);
9417
9418 /* Pipe has the wrong plane attached and the plane is active.
9419 * Temporarily change the plane mapping and disable everything
9420 * ... */
9421 plane = crtc->plane;
9422 crtc->plane = !plane;
9423 dev_priv->display.crtc_disable(&crtc->base);
9424 crtc->plane = plane;
9425
9426 /* ... and break all links. */
9427 list_for_each_entry(connector, &dev->mode_config.connector_list,
9428 base.head) {
9429 if (connector->encoder->base.crtc != &crtc->base)
9430 continue;
9431
9432 intel_connector_break_all_links(connector);
9433 }
9434
9435 WARN_ON(crtc->active);
9436 crtc->base.enabled = false;
9437 }
24929352 9438
7fad798e
DV		 9439 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9440 crtc->pipe == PIPE_A && !crtc->active) {
9441 /* BIOS forgot to enable pipe A, this mostly happens after
9442 * resume. Force-enable the pipe to fix this, the update_dpms
9443 * call below we restore the pipe to the right state, but leave
9444 * the required bits on. */
9445 intel_enable_pipe_a(dev);
9446 }
9447
24929352
DV		 9448 /* Adjust the state of the output pipe according to whether we
9449 * have active connectors/encoders. */
9450 intel_crtc_update_dpms(&crtc->base);
9451
9452 if (crtc->active != crtc->base.enabled) {
9453 struct intel_encoder *encoder;
9454
9455 /* This can happen either due to bugs in the get_hw_state
9456 * functions or because the pipe is force-enabled due to the
9457 * pipe A quirk. */
9458 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9459 crtc->base.base.id,
9460 crtc->base.enabled ? "enabled" : "disabled",
9461 crtc->active ? "enabled" : "disabled");
9462
9463 crtc->base.enabled = crtc->active;
9464
9465 /* Because we only establish the connector -> encoder ->
9466 * crtc links if something is active, this means the
9467 * crtc is now deactivated. Break the links. connector
9468 * -> encoder links are only establish when things are
9469 * actually up, hence no need to break them. */
9470 WARN_ON(crtc->active);
9471
9472 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9473 WARN_ON(encoder->connectors_active);
9474 encoder->base.crtc = NULL;
9475 }
9476 }
9477}
9478
9479static void intel_sanitize_encoder(struct intel_encoder *encoder)
9480{
9481 struct intel_connector *connector;
9482 struct drm_device *dev = encoder->base.dev;
9483
9484 /* We need to check both for a crtc link (meaning that the
9485 * encoder is active and trying to read from a pipe) and the
9486 * pipe itself being active. */
9487 bool has_active_crtc = encoder->base.crtc &&
9488 to_intel_crtc(encoder->base.crtc)->active;
9489
9490 if (encoder->connectors_active && !has_active_crtc) {
9491 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9492 encoder->base.base.id,
9493 drm_get_encoder_name(&encoder->base));
9494
9495 /* Connector is active, but has no active pipe. This is
9496 * fallout from our resume register restoring. Disable
9497 * the encoder manually again. */
9498 if (encoder->base.crtc) {
9499 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9500 encoder->base.base.id,
9501 drm_get_encoder_name(&encoder->base));
9502 encoder->disable(encoder);
9503 }
9504
9505 /* Inconsistent output/port/pipe state happens presumably due to
9506 * a bug in one of the get_hw_state functions. Or someplace else
9507 * in our code, like the register restore mess on resume. Clamp
9508 * things to off as a safer default. */
9509 list_for_each_entry(connector,
9510 &dev->mode_config.connector_list,
9511 base.head) {
9512 if (connector->encoder != encoder)
9513 continue;
9514
9515 intel_connector_break_all_links(connector);
9516 }
9517 }
9518 /* Enabled encoders without active connectors will be fixed in
9519 * the crtc fixup. */
9520}
9521
44cec740 9522void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9523{
9524 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9525 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9526
9527 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9528 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9529 i915_disable_vga(dev);
0fde901f
KM		 9530 }
9531}
9532
24929352
DV		 9533/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9534 * and i915 state tracking structures. */
45e2b5f6
DV		 9535void intel_modeset_setup_hw_state(struct drm_device *dev,
9536 bool force_restore)
24929352
DV		 9537{
9538 struct drm_i915_private *dev_priv = dev->dev_private;
9539 enum pipe pipe;
b5644d05 9540 struct drm_plane *plane;
24929352
DV		 9541 struct intel_crtc *crtc;
9542 struct intel_encoder *encoder;
9543 struct intel_connector *connector;
9544
0e8ffe1b
DV		 9545 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9546 base.head) {
88adfff1 9547 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 9548
0e8ffe1b
DV		 9549 crtc->active = dev_priv->display.get_pipe_config(crtc,
9550 &crtc->config);
24929352
DV		 9551
9552 crtc->base.enabled = crtc->active;
9553
9554 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9555 crtc->base.base.id,
9556 crtc->active ? "enabled" : "disabled");
9557 }
9558
affa9354 9559 if (HAS_DDI(dev))
6441ab5f
PZ		 9560 intel_ddi_setup_hw_pll_state(dev);
9561
24929352
DV		 9562 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9563 base.head) {
9564 pipe = 0;
9565
9566 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 9567 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9568 encoder->base.crtc = &crtc->base;
9569 if (encoder->get_config)
9570 encoder->get_config(encoder, &crtc->config);
24929352
DV		 9571 } else {
9572 encoder->base.crtc = NULL;
9573 }
9574
9575 encoder->connectors_active = false;
9576 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9577 encoder->base.base.id,
9578 drm_get_encoder_name(&encoder->base),
9579 encoder->base.crtc ? "enabled" : "disabled",
9580 pipe);
9581 }
9582
9583 list_for_each_entry(connector, &dev->mode_config.connector_list,
9584 base.head) {
9585 if (connector->get_hw_state(connector)) {
9586 connector->base.dpms = DRM_MODE_DPMS_ON;
9587 connector->encoder->connectors_active = true;
9588 connector->base.encoder = &connector->encoder->base;
9589 } else {
9590 connector->base.dpms = DRM_MODE_DPMS_OFF;
9591 connector->base.encoder = NULL;
9592 }
9593 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9594 connector->base.base.id,
9595 drm_get_connector_name(&connector->base),
9596 connector->base.encoder ? "enabled" : "disabled");
9597 }
9598
9599 /* HW state is read out, now we need to sanitize this mess. */
9600 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9601 base.head) {
9602 intel_sanitize_encoder(encoder);
9603 }
9604
9605 for_each_pipe(pipe) {
9606 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9607 intel_sanitize_crtc(crtc);
c0b03411 9608 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 9609 }
9a935856 9610
45e2b5f6 9611 if (force_restore) {
f30da187
DV		 9612 /*
9613 * We need to use raw interfaces for restoring state to avoid
9614 * checking (bogus) intermediate states.
9615 */
45e2b5f6 9616 for_each_pipe(pipe) {
b5644d05
JB		 9617 struct drm_crtc *crtc =
9618 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9619
9620 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9621 crtc->fb);
45e2b5f6 9622 }
b5644d05
JB		 9623 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9624 intel_plane_restore(plane);
0fde901f
KM		 9625
9626 i915_redisable_vga(dev);
45e2b5f6
DV		 9627 } else {
9628 intel_modeset_update_staged_output_state(dev);
9629 }
8af6cf88
DV		 9630
9631 intel_modeset_check_state(dev);
2e938892
DV		 9632
9633 drm_mode_config_reset(dev);
2c7111db
CW		 9634}
9635
9636void intel_modeset_gem_init(struct drm_device *dev)
9637{
1833b134 9638 intel_modeset_init_hw(dev);
02e792fb
DV		 9639
9640 intel_setup_overlay(dev);
24929352 9641
45e2b5f6 9642 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9643}
9644
9645void intel_modeset_cleanup(struct drm_device *dev)
9646{
652c393a
JB		 9647 struct drm_i915_private *dev_priv = dev->dev_private;
9648 struct drm_crtc *crtc;
9649 struct intel_crtc *intel_crtc;
9650
fd0c0642
DV		 9651 /*
9652 * Interrupts and polling as the first thing to avoid creating havoc.
9653 * Too much stuff here (turning of rps, connectors, ...) would
9654 * experience fancy races otherwise.
9655 */
9656 drm_irq_uninstall(dev);
9657 cancel_work_sync(&dev_priv->hotplug_work);
9658 /*
9659 * Due to the hpd irq storm handling the hotplug work can re-arm the
9660 * poll handlers. Hence disable polling after hpd handling is shut down.
9661 */
f87ea761 9662 drm_kms_helper_poll_fini(dev);
fd0c0642 9663
652c393a
JB		 9664 mutex_lock(&dev->struct_mutex);
9665
723bfd70
JB		 9666 intel_unregister_dsm_handler();
9667
652c393a
JB		 9668 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9669 /* Skip inactive CRTCs */
9670 if (!crtc->fb)
9671 continue;
9672
9673 intel_crtc = to_intel_crtc(crtc);
3dec0095 9674 intel_increase_pllclock(crtc);
652c393a
JB		 9675 }
9676
973d04f9 9677 intel_disable_fbc(dev);
e70236a8 9678
8090c6b9 9679 intel_disable_gt_powersave(dev);
0cdab21f 9680
930ebb46
DV		 9681 ironlake_teardown_rc6(dev);
9682
69341a5e
KH		 9683 mutex_unlock(&dev->struct_mutex);
9684
1630fe75
CW		 9685 /* flush any delayed tasks or pending work */
9686 flush_scheduled_work();
9687
dc652f90
JN		 9688 /* destroy backlight, if any, before the connectors */
9689 intel_panel_destroy_backlight(dev);
9690
79e53945 9691 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9692
9693 intel_cleanup_overlay(dev);
79e53945
JB		 9694}
9695
f1c79df3
ZW		 9696/*
9697 * Return which encoder is currently attached for connector.
9698 */
df0e9248 9699struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9700{
df0e9248
CW		 9701 return &intel_attached_encoder(connector)->base;
9702}
f1c79df3 9703
df0e9248
CW		 9704void intel_connector_attach_encoder(struct intel_connector *connector,
9705 struct intel_encoder *encoder)
9706{
9707 connector->encoder = encoder;
9708 drm_mode_connector_attach_encoder(&connector->base,
9709 &encoder->base);
79e53945 9710}
28d52043
DA		 9711
9712/*
9713 * set vga decode state - true == enable VGA decode
9714 */
9715int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9716{
9717 struct drm_i915_private *dev_priv = dev->dev_private;
9718 u16 gmch_ctrl;
9719
9720 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9721 if (state)
9722 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9723 else
9724 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9725 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9726 return 0;
9727}
c4a1d9e4
CW		 9728
9729#ifdef CONFIG_DEBUG_FS
9730#include <linux/seq_file.h>
9731
9732struct intel_display_error_state {
ff57f1b0
PZ		 9733
9734 u32 power_well_driver;
9735
c4a1d9e4
CW		 9736 struct intel_cursor_error_state {
9737 u32 control;
9738 u32 position;
9739 u32 base;
9740 u32 size;
52331309 9741 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9742
9743 struct intel_pipe_error_state {
ff57f1b0 9744 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9745 u32 conf;
9746 u32 source;
9747
9748 u32 htotal;
9749 u32 hblank;
9750 u32 hsync;
9751 u32 vtotal;
9752 u32 vblank;
9753 u32 vsync;
52331309 9754 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9755
9756 struct intel_plane_error_state {
9757 u32 control;
9758 u32 stride;
9759 u32 size;
9760 u32 pos;
9761 u32 addr;
9762 u32 surface;
9763 u32 tile_offset;
52331309 9764 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9765};
9766
9767struct intel_display_error_state *
9768intel_display_capture_error_state(struct drm_device *dev)
9769{
0206e353 9770 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9771 struct intel_display_error_state *error;
702e7a56 9772 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9773 int i;
9774
9775 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9776 if (error == NULL)
9777 return NULL;
9778
ff57f1b0
PZ		 9779 if (HAS_POWER_WELL(dev))
9780 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9781
52331309 9782 for_each_pipe(i) {
702e7a56 9783 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 9784 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 9785
a18c4c3d
PZ		 9786 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9787 error->cursor[i].control = I915_READ(CURCNTR(i));
9788 error->cursor[i].position = I915_READ(CURPOS(i));
9789 error->cursor[i].base = I915_READ(CURBASE(i));
9790 } else {
9791 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9792 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9793 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9794 }
c4a1d9e4
CW		 9795
9796 error->plane[i].control = I915_READ(DSPCNTR(i));
9797 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9798 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9799 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9800 error->plane[i].pos = I915_READ(DSPPOS(i));
9801 }
ca291363
PZ		 9802 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9803 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9804 if (INTEL_INFO(dev)->gen >= 4) {
9805 error->plane[i].surface = I915_READ(DSPSURF(i));
9806 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9807 }
9808
702e7a56 9809 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9810 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9811 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9812 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9813 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9814 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9815 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9816 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9817 }
9818
12d217c7
PZ		 9819 /* In the code above we read the registers without checking if the power
9820 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9821 * prevent the next I915_WRITE from detecting it and printing an error
9822 * message. */
9823 if (HAS_POWER_WELL(dev))
9824 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9825
c4a1d9e4
CW		 9826 return error;
9827}
9828
edc3d884
MK		 9829#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
9830
c4a1d9e4 9831void
edc3d884 9832intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 9833 struct drm_device *dev,
9834 struct intel_display_error_state *error)
9835{
9836 int i;
9837
edc3d884 9838 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 9839 if (HAS_POWER_WELL(dev))
edc3d884 9840 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 9841 error->power_well_driver);
52331309 9842 for_each_pipe(i) {
edc3d884
MK		 9843 err_printf(m, "Pipe [%d]:\n", i);
9844 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 9845 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 9846 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9847 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
9848 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9849 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9850 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9851 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9852 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9853 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9854
9855 err_printf(m, "Plane [%d]:\n", i);
9856 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
9857 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9858 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 9859 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
9860 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 9861 }
4b71a570 9862 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 9863 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 9864 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 9865 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
9866 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 9867 }
9868
edc3d884
MK		 9869 err_printf(m, "Cursor [%d]:\n", i);
9870 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9871 err_printf(m, " POS: %08x\n", error->cursor[i].position);
9872 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 9873 }
9874}
9875#endif
Linux kernel - Deliverables
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