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drm/i915: unreference default context on module unload
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
f4808ab8
VS		 62 /**
63 * find_pll() - Find the best values for the PLL
64 * @limit: limits for the PLL
65 * @crtc: current CRTC
66 * @target: target frequency in kHz
67 * @refclk: reference clock frequency in kHz
68 * @match_clock: if provided, @best_clock P divider must
69 * match the P divider from @match_clock
70 * used for LVDS downclocking
71 * @best_clock: best PLL values found
72 *
73 * Returns true on success, false on failure.
74 */
75 bool (*find_pll)(const intel_limit_t *limit,
76 struct drm_crtc *crtc,
77 int target, int refclk,
78 intel_clock_t *match_clock,
79 intel_clock_t *best_clock);
d4906093 80};
79e53945 81
2377b741
JB		 82/* FDI */
83#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84
d2acd215
DV		 85int
86intel_pch_rawclk(struct drm_device *dev)
87{
88 struct drm_i915_private *dev_priv = dev->dev_private;
89
90 WARN_ON(!HAS_PCH_SPLIT(dev));
91
92 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
93}
94
d4906093
ML		 95static bool
96intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
d4906093
ML		 99static bool
100intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 101 int target, int refclk, intel_clock_t *match_clock,
102 intel_clock_t *best_clock);
79e53945 103
a0c4da24
JB		 104static bool
105intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
108
021357ac
CW		 109static inline u32 /* units of 100MHz */
110intel_fdi_link_freq(struct drm_device *dev)
111{
8b99e68c
CW		 112 if (IS_GEN5(dev)) {
113 struct drm_i915_private *dev_priv = dev->dev_private;
114 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
115 } else
116 return 27;
021357ac
CW		 117}
118
e4b36699 119static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 120 .dot = { .min = 25000, .max = 350000 },
121 .vco = { .min = 930000, .max = 1400000 },
122 .n = { .min = 3, .max = 16 },
123 .m = { .min = 96, .max = 140 },
124 .m1 = { .min = 18, .max = 26 },
125 .m2 = { .min = 6, .max = 16 },
126 .p = { .min = 4, .max = 128 },
127 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 128 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 2 },
d4906093 130 .find_pll = intel_find_best_PLL,
e4b36699
KP		 131};
132
133static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 134 .dot = { .min = 25000, .max = 350000 },
135 .vco = { .min = 930000, .max = 1400000 },
136 .n = { .min = 3, .max = 16 },
137 .m = { .min = 96, .max = 140 },
138 .m1 = { .min = 18, .max = 26 },
139 .m2 = { .min = 6, .max = 16 },
140 .p = { .min = 4, .max = 128 },
141 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 142 .p2 = { .dot_limit = 165000,
143 .p2_slow = 14, .p2_fast = 7 },
d4906093 144 .find_pll = intel_find_best_PLL,
e4b36699 145};
273e27ca 146
e4b36699 147static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 154 .p = { .min = 5, .max = 80 },
155 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 156 .p2 = { .dot_limit = 200000,
157 .p2_slow = 10, .p2_fast = 5 },
d4906093 158 .find_pll = intel_find_best_PLL,
e4b36699
KP		 159};
160
161static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 162 .dot = { .min = 20000, .max = 400000 },
163 .vco = { .min = 1400000, .max = 2800000 },
164 .n = { .min = 1, .max = 6 },
165 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 166 .m1 = { .min = 8, .max = 18 },
167 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 168 .p = { .min = 7, .max = 98 },
169 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 170 .p2 = { .dot_limit = 112000,
171 .p2_slow = 14, .p2_fast = 7 },
d4906093 172 .find_pll = intel_find_best_PLL,
e4b36699
KP		 173};
174
273e27ca 175
e4b36699 176static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 177 .dot = { .min = 25000, .max = 270000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 17, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 10, .max = 30 },
184 .p1 = { .min = 1, .max = 3},
185 .p2 = { .dot_limit = 270000,
186 .p2_slow = 10,
187 .p2_fast = 10
044c7c41 188 },
d4906093 189 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 190};
191
192static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 193 .dot = { .min = 22000, .max = 400000 },
194 .vco = { .min = 1750000, .max = 3500000},
195 .n = { .min = 1, .max = 4 },
196 .m = { .min = 104, .max = 138 },
197 .m1 = { .min = 16, .max = 23 },
198 .m2 = { .min = 5, .max = 11 },
199 .p = { .min = 5, .max = 80 },
200 .p1 = { .min = 1, .max = 8},
201 .p2 = { .dot_limit = 165000,
202 .p2_slow = 10, .p2_fast = 5 },
d4906093 203 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 204};
205
206static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 207 .dot = { .min = 20000, .max = 115000 },
208 .vco = { .min = 1750000, .max = 3500000 },
209 .n = { .min = 1, .max = 3 },
210 .m = { .min = 104, .max = 138 },
211 .m1 = { .min = 17, .max = 23 },
212 .m2 = { .min = 5, .max = 11 },
213 .p = { .min = 28, .max = 112 },
214 .p1 = { .min = 2, .max = 8 },
215 .p2 = { .dot_limit = 0,
216 .p2_slow = 14, .p2_fast = 14
044c7c41 217 },
d4906093 218 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 219};
220
221static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 222 .dot = { .min = 80000, .max = 224000 },
223 .vco = { .min = 1750000, .max = 3500000 },
224 .n = { .min = 1, .max = 3 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 14, .max = 42 },
229 .p1 = { .min = 2, .max = 6 },
230 .p2 = { .dot_limit = 0,
231 .p2_slow = 7, .p2_fast = 7
044c7c41 232 },
d4906093 233 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 234};
235
f2b115e6 236static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 237 .dot = { .min = 20000, .max = 400000},
238 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 239 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 240 .n = { .min = 3, .max = 6 },
241 .m = { .min = 2, .max = 256 },
273e27ca 242 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 243 .m1 = { .min = 0, .max = 0 },
244 .m2 = { .min = 0, .max = 254 },
245 .p = { .min = 5, .max = 80 },
246 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 247 .p2 = { .dot_limit = 200000,
248 .p2_slow = 10, .p2_fast = 5 },
6115707b 249 .find_pll = intel_find_best_PLL,
e4b36699
KP		 250};
251
f2b115e6 252static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 253 .dot = { .min = 20000, .max = 400000 },
254 .vco = { .min = 1700000, .max = 3500000 },
255 .n = { .min = 3, .max = 6 },
256 .m = { .min = 2, .max = 256 },
257 .m1 = { .min = 0, .max = 0 },
258 .m2 = { .min = 0, .max = 254 },
259 .p = { .min = 7, .max = 112 },
260 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 261 .p2 = { .dot_limit = 112000,
262 .p2_slow = 14, .p2_fast = 14 },
6115707b 263 .find_pll = intel_find_best_PLL,
e4b36699
KP		 264};
265
273e27ca
EA		 266/* Ironlake / Sandybridge
267 *
268 * We calculate clock using (register_value + 2) for N/M1/M2, so here
269 * the range value for them is (actual_value - 2).
270 */
b91ad0ec 271static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 272 .dot = { .min = 25000, .max = 350000 },
273 .vco = { .min = 1760000, .max = 3510000 },
274 .n = { .min = 1, .max = 5 },
275 .m = { .min = 79, .max = 127 },
276 .m1 = { .min = 12, .max = 22 },
277 .m2 = { .min = 5, .max = 9 },
278 .p = { .min = 5, .max = 80 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 225000,
281 .p2_slow = 10, .p2_fast = 5 },
4547668a 282 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 283};
284
b91ad0ec 285static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 286 .dot = { .min = 25000, .max = 350000 },
287 .vco = { .min = 1760000, .max = 3510000 },
288 .n = { .min = 1, .max = 3 },
289 .m = { .min = 79, .max = 118 },
290 .m1 = { .min = 12, .max = 22 },
291 .m2 = { .min = 5, .max = 9 },
292 .p = { .min = 28, .max = 112 },
293 .p1 = { .min = 2, .max = 8 },
294 .p2 = { .dot_limit = 225000,
295 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 296 .find_pll = intel_g4x_find_best_PLL,
297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 127 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 56 },
307 .p1 = { .min = 2, .max = 8 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 310 .find_pll = intel_g4x_find_best_PLL,
311};
312
273e27ca 313/* LVDS 100mhz refclk limits. */
b91ad0ec 314static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 2 },
318 .m = { .min = 79, .max = 126 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 28, .max = 112 },
0206e353 322 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 325 .find_pll = intel_g4x_find_best_PLL,
326};
327
328static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 126 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 14, .max = 42 },
0206e353 336 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 339 .find_pll = intel_g4x_find_best_PLL,
340};
341
a0c4da24
JB		 342static const intel_limit_t intel_limits_vlv_dac = {
343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
345 .n = { .min = 1, .max = 7 },
346 .m = { .min = 22, .max = 450 }, /* guess */
347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
75e53986 350 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
353 .find_pll = intel_vlv_find_best_pll,
354};
355
356static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 357 .dot = { .min = 25000, .max = 270000 },
358 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 359 .n = { .min = 1, .max = 7 },
360 .m = { .min = 60, .max = 300 }, /* guess */
361 .m1 = { .min = 2, .max = 3 },
362 .m2 = { .min = 11, .max = 156 },
363 .p = { .min = 10, .max = 30 },
364 .p1 = { .min = 2, .max = 3 },
365 .p2 = { .dot_limit = 270000,
366 .p2_slow = 2, .p2_fast = 20 },
367 .find_pll = intel_vlv_find_best_pll,
368};
369
370static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 371 .dot = { .min = 25000, .max = 270000 },
372 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 373 .n = { .min = 1, .max = 7 },
74a4dd2e 374 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 375 .m1 = { .min = 2, .max = 3 },
376 .m2 = { .min = 11, .max = 156 },
377 .p = { .min = 10, .max = 30 },
75e53986 378 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 379 .p2 = { .dot_limit = 270000,
380 .p2_slow = 2, .p2_fast = 20 },
381 .find_pll = intel_vlv_find_best_pll,
382};
383
57f350b6
JB		 384u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
385{
09153000 386 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 387
57f350b6
JB		 388 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
389 DRM_ERROR("DPIO idle wait timed out\n");
09153000 390 return 0;
57f350b6
JB		 391 }
392
393 I915_WRITE(DPIO_REG, reg);
394 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
395 DPIO_BYTE);
396 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
397 DRM_ERROR("DPIO read wait timed out\n");
09153000 398 return 0;
57f350b6 399 }
57f350b6 400
09153000 401 return I915_READ(DPIO_DATA);
57f350b6
JB		 402}
403
e2fa6fba 404void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
a0c4da24 405{
09153000 406 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 407
a0c4da24
JB		 408 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
409 DRM_ERROR("DPIO idle wait timed out\n");
09153000 410 return;
a0c4da24
JB		 411 }
412
413 I915_WRITE(DPIO_DATA, val);
414 I915_WRITE(DPIO_REG, reg);
415 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
416 DPIO_BYTE);
417 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
418 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 419}
420
1b894b59
CW		 421static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
422 int refclk)
2c07245f 423{
b91ad0ec 424 struct drm_device *dev = crtc->dev;
2c07245f 425 const intel_limit_t *limit;
b91ad0ec
ZW		 426
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 428 if (intel_is_dual_link_lvds(dev)) {
1b894b59 429 if (refclk == 100000)
b91ad0ec
ZW		 430 limit = &intel_limits_ironlake_dual_lvds_100m;
431 else
432 limit = &intel_limits_ironlake_dual_lvds;
433 } else {
1b894b59 434 if (refclk == 100000)
b91ad0ec
ZW		 435 limit = &intel_limits_ironlake_single_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_single_lvds;
438 }
c6bb3538 439 } else
b91ad0ec 440 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 441
442 return limit;
443}
444
044c7c41
ML		 445static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
446{
447 struct drm_device *dev = crtc->dev;
044c7c41
ML		 448 const intel_limit_t *limit;
449
450 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 451 if (intel_is_dual_link_lvds(dev))
e4b36699 452 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 453 else
e4b36699 454 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 455 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
456 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 457 limit = &intel_limits_g4x_hdmi;
044c7c41 458 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 459 limit = &intel_limits_g4x_sdvo;
044c7c41 460 } else /* The option is for other outputs */
e4b36699 461 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 462
463 return limit;
464}
465
1b894b59 466static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 467{
468 struct drm_device *dev = crtc->dev;
469 const intel_limit_t *limit;
470
bad720ff 471 if (HAS_PCH_SPLIT(dev))
1b894b59 472 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 473 else if (IS_G4X(dev)) {
044c7c41 474 limit = intel_g4x_limit(crtc);
f2b115e6 475 } else if (IS_PINEVIEW(dev)) {
2177832f 476 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 477 limit = &intel_limits_pineview_lvds;
2177832f 478 else
f2b115e6 479 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 480 } else if (IS_VALLEYVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
482 limit = &intel_limits_vlv_dac;
483 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
484 limit = &intel_limits_vlv_hdmi;
485 else
486 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 487 } else if (!IS_GEN2(dev)) {
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
489 limit = &intel_limits_i9xx_lvds;
490 else
491 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 492 } else {
493 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 494 limit = &intel_limits_i8xx_lvds;
79e53945 495 else
e4b36699 496 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 497 }
498 return limit;
499}
500
f2b115e6
AJ		 501/* m1 is reserved as 0 in Pineview, n is a ring counter */
502static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 503{
2177832f
SL		 504 clock->m = clock->m2 + 2;
505 clock->p = clock->p1 * clock->p2;
506 clock->vco = refclk * clock->m / clock->n;
507 clock->dot = clock->vco / clock->p;
508}
509
7429e9d4
DV		 510static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
511{
512 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
513}
514
2177832f
SL		 515static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
516{
f2b115e6
AJ		 517 if (IS_PINEVIEW(dev)) {
518 pineview_clock(refclk, clock);
2177832f
SL		 519 return;
520 }
7429e9d4 521 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 522 clock->p = clock->p1 * clock->p2;
523 clock->vco = refclk * clock->m / (clock->n + 2);
524 clock->dot = clock->vco / clock->p;
525}
526
79e53945
JB		 527/**
528 * Returns whether any output on the specified pipe is of the specified type
529 */
4ef69c7a 530bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 531{
4ef69c7a 532 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 533 struct intel_encoder *encoder;
534
6c2b7c12
DV		 535 for_each_encoder_on_crtc(dev, crtc, encoder)
536 if (encoder->type == type)
4ef69c7a
CW		 537 return true;
538
539 return false;
79e53945
JB		 540}
541
7c04d1d9 542#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 543/**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
1b894b59
CW		 548static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
79e53945 551{
79e53945 552 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 553 INTELPllInvalid("p1 out of range\n");
79e53945 554 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 555 INTELPllInvalid("p out of range\n");
79e53945 556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 557 INTELPllInvalid("m2 out of range\n");
79e53945 558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 559 INTELPllInvalid("m1 out of range\n");
f2b115e6 560 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 561 INTELPllInvalid("m1 <= m2\n");
79e53945 562 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 563 INTELPllInvalid("m out of range\n");
79e53945 564 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 565 INTELPllInvalid("n out of range\n");
79e53945 566 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 567 INTELPllInvalid("vco out of range\n");
79e53945
JB		 568 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
569 * connector, etc., rather than just a single range.
570 */
571 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 572 INTELPllInvalid("dot out of range\n");
79e53945
JB		 573
574 return true;
575}
576
d4906093
ML		 577static bool
578intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 579 int target, int refclk, intel_clock_t *match_clock,
580 intel_clock_t *best_clock)
d4906093 581
79e53945
JB		 582{
583 struct drm_device *dev = crtc->dev;
79e53945 584 intel_clock_t clock;
79e53945
JB		 585 int err = target;
586
a210b028 587 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 588 /*
a210b028
DV		 589 * For LVDS just rely on its current settings for dual-channel.
590 * We haven't figured out how to reliably set up different
591 * single/dual channel state, if we even can.
79e53945 592 */
1974cad0 593 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 594 clock.p2 = limit->p2.p2_fast;
595 else
596 clock.p2 = limit->p2.p2_slow;
597 } else {
598 if (target < limit->p2.dot_limit)
599 clock.p2 = limit->p2.p2_slow;
600 else
601 clock.p2 = limit->p2.p2_fast;
602 }
603
0206e353 604 memset(best_clock, 0, sizeof(*best_clock));
79e53945 605
42158660
ZY		 606 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
607 clock.m1++) {
608 for (clock.m2 = limit->m2.min;
609 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 610 /* m1 is always 0 in Pineview */
611 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 612 break;
613 for (clock.n = limit->n.min;
614 clock.n <= limit->n.max; clock.n++) {
615 for (clock.p1 = limit->p1.min;
616 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 617 int this_err;
618
2177832f 619 intel_clock(dev, refclk, &clock);
1b894b59
CW		 620 if (!intel_PLL_is_valid(dev, limit,
621 &clock))
79e53945 622 continue;
cec2f356
SP		 623 if (match_clock &&
624 clock.p != match_clock->p)
625 continue;
79e53945
JB		 626
627 this_err = abs(clock.dot - target);
628 if (this_err < err) {
629 *best_clock = clock;
630 err = this_err;
631 }
632 }
633 }
634 }
635 }
636
637 return (err != target);
638}
639
d4906093
ML		 640static bool
641intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 642 int target, int refclk, intel_clock_t *match_clock,
643 intel_clock_t *best_clock)
d4906093
ML		 644{
645 struct drm_device *dev = crtc->dev;
d4906093
ML		 646 intel_clock_t clock;
647 int max_n;
648 bool found;
6ba770dc
AJ		 649 /* approximately equals target * 0.00585 */
650 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 651 found = false;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 654 int lvds_reg;
655
c619eed4 656 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 657 lvds_reg = PCH_LVDS;
658 else
659 lvds_reg = LVDS;
1974cad0 660 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 661 clock.p2 = limit->p2.p2_fast;
662 else
663 clock.p2 = limit->p2.p2_slow;
664 } else {
665 if (target < limit->p2.dot_limit)
666 clock.p2 = limit->p2.p2_slow;
667 else
668 clock.p2 = limit->p2.p2_fast;
669 }
670
671 memset(best_clock, 0, sizeof(*best_clock));
672 max_n = limit->n.max;
f77f13e2 673 /* based on hardware requirement, prefer smaller n to precision */
d4906093 674 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 675 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 676 for (clock.m1 = limit->m1.max;
677 clock.m1 >= limit->m1.min; clock.m1--) {
678 for (clock.m2 = limit->m2.max;
679 clock.m2 >= limit->m2.min; clock.m2--) {
680 for (clock.p1 = limit->p1.max;
681 clock.p1 >= limit->p1.min; clock.p1--) {
682 int this_err;
683
2177832f 684 intel_clock(dev, refclk, &clock);
1b894b59
CW		 685 if (!intel_PLL_is_valid(dev, limit,
686 &clock))
d4906093 687 continue;
1b894b59
CW		 688
689 this_err = abs(clock.dot - target);
d4906093
ML		 690 if (this_err < err_most) {
691 *best_clock = clock;
692 err_most = this_err;
693 max_n = clock.n;
694 found = true;
695 }
696 }
697 }
698 }
699 }
2c07245f
ZW		 700 return found;
701}
702
a0c4da24
JB		 703static bool
704intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
707{
708 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
709 u32 m, n, fastclk;
710 u32 updrate, minupdate, fracbits, p;
711 unsigned long bestppm, ppm, absppm;
712 int dotclk, flag;
713
af447bd3 714 flag = 0;
a0c4da24
JB		 715 dotclk = target * 1000;
716 bestppm = 1000000;
717 ppm = absppm = 0;
718 fastclk = dotclk / (2*100);
719 updrate = 0;
720 minupdate = 19200;
721 fracbits = 1;
722 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
723 bestm1 = bestm2 = bestp1 = bestp2 = 0;
724
725 /* based on hardware requirement, prefer smaller n to precision */
726 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
727 updrate = refclk / n;
728 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
729 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
730 if (p2 > 10)
731 p2 = p2 - 1;
732 p = p1 * p2;
733 /* based on hardware requirement, prefer bigger m1,m2 values */
734 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
735 m2 = (((2*(fastclk * p * n / m1 )) +
736 refclk) / (2*refclk));
737 m = m1 * m2;
738 vco = updrate * m;
739 if (vco >= limit->vco.min && vco < limit->vco.max) {
740 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
741 absppm = (ppm > 0) ? ppm : (-ppm);
742 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
743 bestppm = 0;
744 flag = 1;
745 }
746 if (absppm < bestppm - 10) {
747 bestppm = absppm;
748 flag = 1;
749 }
750 if (flag) {
751 bestn = n;
752 bestm1 = m1;
753 bestm2 = m2;
754 bestp1 = p1;
755 bestp2 = p2;
756 flag = 0;
757 }
758 }
759 }
760 }
761 }
762 }
763 best_clock->n = bestn;
764 best_clock->m1 = bestm1;
765 best_clock->m2 = bestm2;
766 best_clock->p1 = bestp1;
767 best_clock->p2 = bestp2;
768
769 return true;
770}
a4fc5ed6 771
a5c961d1
PZ		 772enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
773 enum pipe pipe)
774{
775 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
777
3b117c8f 778 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 779}
780
a928d536
PZ		 781static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
782{
783 struct drm_i915_private *dev_priv = dev->dev_private;
784 u32 frame, frame_reg = PIPEFRAME(pipe);
785
786 frame = I915_READ(frame_reg);
787
788 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
789 DRM_DEBUG_KMS("vblank wait timed out\n");
790}
791
9d0498a2
JB		 792/**
793 * intel_wait_for_vblank - wait for vblank on a given pipe
794 * @dev: drm device
795 * @pipe: pipe to wait for
796 *
797 * Wait for vblank to occur on a given pipe. Needed for various bits of
798 * mode setting code.
799 */
800void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 801{
9d0498a2 802 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 803 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 804
a928d536
PZ		 805 if (INTEL_INFO(dev)->gen >= 5) {
806 ironlake_wait_for_vblank(dev, pipe);
807 return;
808 }
809
300387c0
CW		 810 /* Clear existing vblank status. Note this will clear any other
811 * sticky status fields as well.
812 *
813 * This races with i915_driver_irq_handler() with the result
814 * that either function could miss a vblank event. Here it is not
815 * fatal, as we will either wait upon the next vblank interrupt or
816 * timeout. Generally speaking intel_wait_for_vblank() is only
817 * called during modeset at which time the GPU should be idle and
818 * should *not* be performing page flips and thus not waiting on
819 * vblanks...
820 * Currently, the result of us stealing a vblank from the irq
821 * handler is that a single frame will be skipped during swapbuffers.
822 */
823 I915_WRITE(pipestat_reg,
824 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
825
9d0498a2 826 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 827 if (wait_for(I915_READ(pipestat_reg) &
828 PIPE_VBLANK_INTERRUPT_STATUS,
829 50))
9d0498a2
JB		 830 DRM_DEBUG_KMS("vblank wait timed out\n");
831}
832
ab7ad7f6
KP		 833/*
834 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 835 * @dev: drm device
836 * @pipe: pipe to wait for
837 *
838 * After disabling a pipe, we can't wait for vblank in the usual way,
839 * spinning on the vblank interrupt status bit, since we won't actually
840 * see an interrupt when the pipe is disabled.
841 *
ab7ad7f6
KP		 842 * On Gen4 and above:
843 * wait for the pipe register state bit to turn off
844 *
845 * Otherwise:
846 * wait for the display line value to settle (it usually
847 * ends up stopping at the start of the next frame).
58e10eb9 848 *
9d0498a2 849 */
58e10eb9 850void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 851{
852 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 853 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
854 pipe);
ab7ad7f6
KP		 855
856 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 857 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 858
859 /* Wait for the Pipe State to go off */
58e10eb9
CW		 860 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
861 100))
284637d9 862 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 863 } else {
837ba00f 864 u32 last_line, line_mask;
58e10eb9 865 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 866 unsigned long timeout = jiffies + msecs_to_jiffies(100);
867
837ba00f
PZ		 868 if (IS_GEN2(dev))
869 line_mask = DSL_LINEMASK_GEN2;
870 else
871 line_mask = DSL_LINEMASK_GEN3;
872
ab7ad7f6
KP		 873 /* Wait for the display line to settle */
874 do {
837ba00f 875 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 876 mdelay(5);
837ba00f 877 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 878 time_after(timeout, jiffies));
879 if (time_after(jiffies, timeout))
284637d9 880 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 881 }
79e53945
JB		 882}
883
b0ea7d37
DL		 884/*
885 * ibx_digital_port_connected - is the specified port connected?
886 * @dev_priv: i915 private structure
887 * @port: the port to test
888 *
889 * Returns true if @port is connected, false otherwise.
890 */
891bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
892 struct intel_digital_port *port)
893{
894 u32 bit;
895
c36346e3
DL		 896 if (HAS_PCH_IBX(dev_priv->dev)) {
897 switch(port->port) {
898 case PORT_B:
899 bit = SDE_PORTB_HOTPLUG;
900 break;
901 case PORT_C:
902 bit = SDE_PORTC_HOTPLUG;
903 break;
904 case PORT_D:
905 bit = SDE_PORTD_HOTPLUG;
906 break;
907 default:
908 return true;
909 }
910 } else {
911 switch(port->port) {
912 case PORT_B:
913 bit = SDE_PORTB_HOTPLUG_CPT;
914 break;
915 case PORT_C:
916 bit = SDE_PORTC_HOTPLUG_CPT;
917 break;
918 case PORT_D:
919 bit = SDE_PORTD_HOTPLUG_CPT;
920 break;
921 default:
922 return true;
923 }
b0ea7d37
DL		 924 }
925
926 return I915_READ(SDEISR) & bit;
927}
928
b24e7179
JB		 929static const char *state_string(bool enabled)
930{
931 return enabled ? "on" : "off";
932}
933
934/* Only for pre-ILK configs */
935static void assert_pll(struct drm_i915_private *dev_priv,
936 enum pipe pipe, bool state)
937{
938 int reg;
939 u32 val;
940 bool cur_state;
941
942 reg = DPLL(pipe);
943 val = I915_READ(reg);
944 cur_state = !!(val & DPLL_VCO_ENABLE);
945 WARN(cur_state != state,
946 "PLL state assertion failure (expected %s, current %s)\n",
947 state_string(state), state_string(cur_state));
948}
949#define assert_pll_enabled(d, p) assert_pll(d, p, true)
950#define assert_pll_disabled(d, p) assert_pll(d, p, false)
951
040484af
JB		 952/* For ILK+ */
953static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 954 struct intel_pch_pll *pll,
955 struct intel_crtc *crtc,
956 bool state)
040484af 957{
040484af
JB		 958 u32 val;
959 bool cur_state;
960
9d82aa17
ED		 961 if (HAS_PCH_LPT(dev_priv->dev)) {
962 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
963 return;
964 }
965
92b27b08
CW		 966 if (WARN (!pll,
967 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 968 return;
ee7b9f93 969
92b27b08
CW		 970 val = I915_READ(pll->pll_reg);
971 cur_state = !!(val & DPLL_VCO_ENABLE);
972 WARN(cur_state != state,
973 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
974 pll->pll_reg, state_string(state), state_string(cur_state), val);
975
976 /* Make sure the selected PLL is correctly attached to the transcoder */
977 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 978 u32 pch_dpll;
979
980 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 981 cur_state = pll->pll_reg == _PCH_DPLL_B;
982 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
4bb6f1f3
VS		 983 "PLL[%d] not attached to this transcoder %c: %08x\n",
984 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
92b27b08
CW		 985 cur_state = !!(val >> (4*crtc->pipe + 3));
986 WARN(cur_state != state,
4bb6f1f3 987 "PLL[%d] not %s on this transcoder %c: %08x\n",
92b27b08
CW		 988 pll->pll_reg == _PCH_DPLL_B,
989 state_string(state),
4bb6f1f3 990 pipe_name(crtc->pipe),
92b27b08
CW		 991 val);
992 }
d3ccbe86 993 }
040484af 994}
92b27b08
CW		 995#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
996#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 997
998static void assert_fdi_tx(struct drm_i915_private *dev_priv,
999 enum pipe pipe, bool state)
1000{
1001 int reg;
1002 u32 val;
1003 bool cur_state;
ad80a810
PZ		 1004 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1005 pipe);
040484af 1006
affa9354
PZ		 1007 if (HAS_DDI(dev_priv->dev)) {
1008 /* DDI does not have a specific FDI_TX register */
ad80a810 1009 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1010 val = I915_READ(reg);
ad80a810 1011 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1012 } else {
1013 reg = FDI_TX_CTL(pipe);
1014 val = I915_READ(reg);
1015 cur_state = !!(val & FDI_TX_ENABLE);
1016 }
040484af
JB		 1017 WARN(cur_state != state,
1018 "FDI TX state assertion failure (expected %s, current %s)\n",
1019 state_string(state), state_string(cur_state));
1020}
1021#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1022#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1023
1024static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1025 enum pipe pipe, bool state)
1026{
1027 int reg;
1028 u32 val;
1029 bool cur_state;
1030
d63fa0dc
PZ		 1031 reg = FDI_RX_CTL(pipe);
1032 val = I915_READ(reg);
1033 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1034 WARN(cur_state != state,
1035 "FDI RX state assertion failure (expected %s, current %s)\n",
1036 state_string(state), state_string(cur_state));
1037}
1038#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1039#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1040
1041static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1042 enum pipe pipe)
1043{
1044 int reg;
1045 u32 val;
1046
1047 /* ILK FDI PLL is always enabled */
1048 if (dev_priv->info->gen == 5)
1049 return;
1050
bf507ef7 1051 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1052 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1053 return;
1054
040484af
JB		 1055 reg = FDI_TX_CTL(pipe);
1056 val = I915_READ(reg);
1057 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1058}
1059
1060static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1061 enum pipe pipe)
1062{
1063 int reg;
1064 u32 val;
1065
1066 reg = FDI_RX_CTL(pipe);
1067 val = I915_READ(reg);
1068 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1069}
1070
ea0760cf
JB		 1071static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1072 enum pipe pipe)
1073{
1074 int pp_reg, lvds_reg;
1075 u32 val;
1076 enum pipe panel_pipe = PIPE_A;
0de3b485 1077 bool locked = true;
ea0760cf
JB		 1078
1079 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1080 pp_reg = PCH_PP_CONTROL;
1081 lvds_reg = PCH_LVDS;
1082 } else {
1083 pp_reg = PP_CONTROL;
1084 lvds_reg = LVDS;
1085 }
1086
1087 val = I915_READ(pp_reg);
1088 if (!(val & PANEL_POWER_ON) ||
1089 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1090 locked = false;
1091
1092 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1093 panel_pipe = PIPE_B;
1094
1095 WARN(panel_pipe == pipe && locked,
1096 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1097 pipe_name(pipe));
ea0760cf
JB		 1098}
1099
b840d907
JB		 1100void assert_pipe(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
b24e7179
JB		 1102{
1103 int reg;
1104 u32 val;
63d7bbe9 1105 bool cur_state;
702e7a56
PZ		 1106 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1107 pipe);
b24e7179 1108
8e636784
DV		 1109 /* if we need the pipe A quirk it must be always on */
1110 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1111 state = true;
1112
15d199ea
PZ		 1113 if (!intel_using_power_well(dev_priv->dev) &&
1114 cpu_transcoder != TRANSCODER_EDP) {
69310161
PZ		 1115 cur_state = false;
1116 } else {
1117 reg = PIPECONF(cpu_transcoder);
1118 val = I915_READ(reg);
1119 cur_state = !!(val & PIPECONF_ENABLE);
1120 }
1121
63d7bbe9
JB		 1122 WARN(cur_state != state,
1123 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1124 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1125}
1126
931872fc
CW		 1127static void assert_plane(struct drm_i915_private *dev_priv,
1128 enum plane plane, bool state)
b24e7179
JB		 1129{
1130 int reg;
1131 u32 val;
931872fc 1132 bool cur_state;
b24e7179
JB		 1133
1134 reg = DSPCNTR(plane);
1135 val = I915_READ(reg);
931872fc
CW		 1136 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1137 WARN(cur_state != state,
1138 "plane %c assertion failure (expected %s, current %s)\n",
1139 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1140}
1141
931872fc
CW		 1142#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1143#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1144
b24e7179
JB		 1145static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1146 enum pipe pipe)
1147{
1148 int reg, i;
1149 u32 val;
1150 int cur_pipe;
1151
19ec1358 1152 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1153 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1154 reg = DSPCNTR(pipe);
1155 val = I915_READ(reg);
1156 WARN((val & DISPLAY_PLANE_ENABLE),
1157 "plane %c assertion failure, should be disabled but not\n",
1158 plane_name(pipe));
19ec1358 1159 return;
28c05794 1160 }
19ec1358 1161
b24e7179
JB		 1162 /* Need to check both planes against the pipe */
1163 for (i = 0; i < 2; i++) {
1164 reg = DSPCNTR(i);
1165 val = I915_READ(reg);
1166 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1167 DISPPLANE_SEL_PIPE_SHIFT;
1168 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1169 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1170 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1171 }
1172}
1173
19332d7a
JB		 1174static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1175 enum pipe pipe)
1176{
1177 int reg, i;
1178 u32 val;
1179
1180 if (!IS_VALLEYVIEW(dev_priv->dev))
1181 return;
1182
1183 /* Need to check both planes against the pipe */
1184 for (i = 0; i < dev_priv->num_plane; i++) {
1185 reg = SPCNTR(pipe, i);
1186 val = I915_READ(reg);
1187 WARN((val & SP_ENABLE),
06da8da2
VS		 1188 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1189 sprite_name(pipe, i), pipe_name(pipe));
19332d7a
JB		 1190 }
1191}
1192
92f2584a
JB		 1193static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1194{
1195 u32 val;
1196 bool enabled;
1197
9d82aa17
ED		 1198 if (HAS_PCH_LPT(dev_priv->dev)) {
1199 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1200 return;
1201 }
1202
92f2584a
JB		 1203 val = I915_READ(PCH_DREF_CONTROL);
1204 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1205 DREF_SUPERSPREAD_SOURCE_MASK));
1206 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1207}
1208
1209static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1210 enum pipe pipe)
1211{
1212 int reg;
1213 u32 val;
1214 bool enabled;
1215
1216 reg = TRANSCONF(pipe);
1217 val = I915_READ(reg);
1218 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1219 WARN(enabled,
1220 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1221 pipe_name(pipe));
92f2584a
JB		 1222}
1223
4e634389
KP		 1224static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1225 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1226{
1227 if ((val & DP_PORT_EN) == 0)
1228 return false;
1229
1230 if (HAS_PCH_CPT(dev_priv->dev)) {
1231 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1232 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1233 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1234 return false;
1235 } else {
1236 if ((val & DP_PIPE_MASK) != (pipe << 30))
1237 return false;
1238 }
1239 return true;
1240}
1241
1519b995
KP		 1242static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, u32 val)
1244{
dc0fa718 1245 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1246 return false;
1247
1248 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1249 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1250 return false;
1251 } else {
dc0fa718 1252 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1253 return false;
1254 }
1255 return true;
1256}
1257
1258static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1259 enum pipe pipe, u32 val)
1260{
1261 if ((val & LVDS_PORT_EN) == 0)
1262 return false;
1263
1264 if (HAS_PCH_CPT(dev_priv->dev)) {
1265 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1266 return false;
1267 } else {
1268 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1269 return false;
1270 }
1271 return true;
1272}
1273
1274static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1275 enum pipe pipe, u32 val)
1276{
1277 if ((val & ADPA_DAC_ENABLE) == 0)
1278 return false;
1279 if (HAS_PCH_CPT(dev_priv->dev)) {
1280 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1281 return false;
1282 } else {
1283 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1284 return false;
1285 }
1286 return true;
1287}
1288
291906f1 1289static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1290 enum pipe pipe, int reg, u32 port_sel)
291906f1 1291{
47a05eca 1292 u32 val = I915_READ(reg);
4e634389 1293 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1294 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1295 reg, pipe_name(pipe));
de9a35ab 1296
75c5da27
DV		 1297 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1298 && (val & DP_PIPEB_SELECT),
de9a35ab 1299 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1300}
1301
1302static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1303 enum pipe pipe, int reg)
1304{
47a05eca 1305 u32 val = I915_READ(reg);
b70ad586 1306 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1307 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1308 reg, pipe_name(pipe));
de9a35ab 1309
dc0fa718 1310 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1311 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1312 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1313}
1314
1315static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1316 enum pipe pipe)
1317{
1318 int reg;
1319 u32 val;
291906f1 1320
f0575e92
KP		 1321 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1322 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1323 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1324
1325 reg = PCH_ADPA;
1326 val = I915_READ(reg);
b70ad586 1327 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1328 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1329 pipe_name(pipe));
291906f1
JB		 1330
1331 reg = PCH_LVDS;
1332 val = I915_READ(reg);
b70ad586 1333 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1334 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1335 pipe_name(pipe));
291906f1 1336
e2debe91
PZ		 1337 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1338 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1339 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1340}
1341
63d7bbe9
JB		 1342/**
1343 * intel_enable_pll - enable a PLL
1344 * @dev_priv: i915 private structure
1345 * @pipe: pipe PLL to enable
1346 *
1347 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1348 * make sure the PLL reg is writable first though, since the panel write
1349 * protect mechanism may be enabled.
1350 *
1351 * Note! This is for pre-ILK only.
7434a255
TR		 1352 *
1353 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1354 */
1355static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1356{
1357 int reg;
1358 u32 val;
1359
58c6eaa2
DV		 1360 assert_pipe_disabled(dev_priv, pipe);
1361
63d7bbe9 1362 /* No really, not for ILK+ */
a0c4da24 1363 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1364
1365 /* PLL is protected by panel, make sure we can write it */
1366 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1367 assert_panel_unlocked(dev_priv, pipe);
1368
1369 reg = DPLL(pipe);
1370 val = I915_READ(reg);
1371 val |= DPLL_VCO_ENABLE;
1372
1373 /* We do this three times for luck */
1374 I915_WRITE(reg, val);
1375 POSTING_READ(reg);
1376 udelay(150); /* wait for warmup */
1377 I915_WRITE(reg, val);
1378 POSTING_READ(reg);
1379 udelay(150); /* wait for warmup */
1380 I915_WRITE(reg, val);
1381 POSTING_READ(reg);
1382 udelay(150); /* wait for warmup */
1383}
1384
1385/**
1386 * intel_disable_pll - disable a PLL
1387 * @dev_priv: i915 private structure
1388 * @pipe: pipe PLL to disable
1389 *
1390 * Disable the PLL for @pipe, making sure the pipe is off first.
1391 *
1392 * Note! This is for pre-ILK only.
1393 */
1394static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1395{
1396 int reg;
1397 u32 val;
1398
1399 /* Don't disable pipe A or pipe A PLLs if needed */
1400 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1401 return;
1402
1403 /* Make sure the pipe isn't still relying on us */
1404 assert_pipe_disabled(dev_priv, pipe);
1405
1406 reg = DPLL(pipe);
1407 val = I915_READ(reg);
1408 val &= ~DPLL_VCO_ENABLE;
1409 I915_WRITE(reg, val);
1410 POSTING_READ(reg);
1411}
1412
a416edef
ED		 1413/* SBI access */
1414static void
988d6ee8
PZ		 1415intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1416 enum intel_sbi_destination destination)
a416edef 1417{
988d6ee8 1418 u32 tmp;
a416edef 1419
09153000 1420 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1421
39fb50f6 1422 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1423 100)) {
1424 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1425 return;
a416edef
ED		 1426 }
1427
988d6ee8
PZ		 1428 I915_WRITE(SBI_ADDR, (reg << 16));
1429 I915_WRITE(SBI_DATA, value);
1430
1431 if (destination == SBI_ICLK)
1432 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1433 else
1434 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1435 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1436
39fb50f6 1437 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1438 100)) {
1439 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1440 return;
a416edef 1441 }
a416edef
ED		 1442}
1443
1444static u32
988d6ee8
PZ		 1445intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1446 enum intel_sbi_destination destination)
a416edef 1447{
39fb50f6 1448 u32 value = 0;
09153000 1449 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1450
39fb50f6 1451 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1452 100)) {
1453 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1454 return 0;
a416edef
ED		 1455 }
1456
988d6ee8
PZ		 1457 I915_WRITE(SBI_ADDR, (reg << 16));
1458
1459 if (destination == SBI_ICLK)
1460 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1461 else
1462 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1463 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1464
39fb50f6 1465 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1466 100)) {
1467 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1468 return 0;
a416edef
ED		 1469 }
1470
09153000 1471 return I915_READ(SBI_DATA);
a416edef
ED		 1472}
1473
89b667f8
JB		 1474void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1475{
1476 u32 port_mask;
1477
1478 if (!port)
1479 port_mask = DPLL_PORTB_READY_MASK;
1480 else
1481 port_mask = DPLL_PORTC_READY_MASK;
1482
1483 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1484 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1485 'B' + port, I915_READ(DPLL(0)));
1486}
1487
92f2584a 1488/**
b6b4e185 1489 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1490 * @dev_priv: i915 private structure
1491 * @pipe: pipe PLL to enable
1492 *
1493 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1494 * drives the transcoder clock.
1495 */
b6b4e185 1496static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1497{
ee7b9f93 1498 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1499 struct intel_pch_pll *pll;
92f2584a
JB		 1500 int reg;
1501 u32 val;
1502
48da64a8 1503 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1504 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1505 pll = intel_crtc->pch_pll;
1506 if (pll == NULL)
1507 return;
1508
1509 if (WARN_ON(pll->refcount == 0))
1510 return;
ee7b9f93
JB		 1511
1512 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1513 pll->pll_reg, pll->active, pll->on,
1514 intel_crtc->base.base.id);
92f2584a
JB		 1515
1516 /* PCH refclock must be enabled first */
1517 assert_pch_refclk_enabled(dev_priv);
1518
ee7b9f93 1519 if (pll->active++ && pll->on) {
92b27b08 1520 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1521 return;
1522 }
1523
1524 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1525
1526 reg = pll->pll_reg;
92f2584a
JB		 1527 val = I915_READ(reg);
1528 val |= DPLL_VCO_ENABLE;
1529 I915_WRITE(reg, val);
1530 POSTING_READ(reg);
1531 udelay(200);
ee7b9f93
JB		 1532
1533 pll->on = true;
92f2584a
JB		 1534}
1535
ee7b9f93 1536static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1537{
ee7b9f93
JB		 1538 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1539 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1540 int reg;
ee7b9f93 1541 u32 val;
4c609cb8 1542
92f2584a
JB		 1543 /* PCH only available on ILK+ */
1544 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1545 if (pll == NULL)
1546 return;
92f2584a 1547
48da64a8
CW		 1548 if (WARN_ON(pll->refcount == 0))
1549 return;
7a419866 1550
ee7b9f93
JB		 1551 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1552 pll->pll_reg, pll->active, pll->on,
1553 intel_crtc->base.base.id);
7a419866 1554
48da64a8 1555 if (WARN_ON(pll->active == 0)) {
92b27b08 1556 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1557 return;
1558 }
1559
ee7b9f93 1560 if (--pll->active) {
92b27b08 1561 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1562 return;
ee7b9f93
JB		 1563 }
1564
1565 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1566
1567 /* Make sure transcoder isn't still depending on us */
1568 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1569
ee7b9f93 1570 reg = pll->pll_reg;
92f2584a
JB		 1571 val = I915_READ(reg);
1572 val &= ~DPLL_VCO_ENABLE;
1573 I915_WRITE(reg, val);
1574 POSTING_READ(reg);
1575 udelay(200);
ee7b9f93
JB		 1576
1577 pll->on = false;
92f2584a
JB		 1578}
1579
b8a4f404
PZ		 1580static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1581 enum pipe pipe)
040484af 1582{
23670b32 1583 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1584 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1585 uint32_t reg, val, pipeconf_val;
040484af
JB		 1586
1587 /* PCH only available on ILK+ */
1588 BUG_ON(dev_priv->info->gen < 5);
1589
1590 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1591 assert_pch_pll_enabled(dev_priv,
1592 to_intel_crtc(crtc)->pch_pll,
1593 to_intel_crtc(crtc));
040484af
JB		 1594
1595 /* FDI must be feeding us bits for PCH ports */
1596 assert_fdi_tx_enabled(dev_priv, pipe);
1597 assert_fdi_rx_enabled(dev_priv, pipe);
1598
23670b32
DV		 1599 if (HAS_PCH_CPT(dev)) {
1600 /* Workaround: Set the timing override bit before enabling the
1601 * pch transcoder. */
1602 reg = TRANS_CHICKEN2(pipe);
1603 val = I915_READ(reg);
1604 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1605 I915_WRITE(reg, val);
59c859d6 1606 }
23670b32 1607
040484af
JB		 1608 reg = TRANSCONF(pipe);
1609 val = I915_READ(reg);
5f7f726d 1610 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1611
1612 if (HAS_PCH_IBX(dev_priv->dev)) {
1613 /*
1614 * make the BPC in transcoder be consistent with
1615 * that in pipeconf reg.
1616 */
dfd07d72
DV		 1617 val &= ~PIPECONF_BPC_MASK;
1618 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1619 }
5f7f726d
PZ		 1620
1621 val &= ~TRANS_INTERLACE_MASK;
1622 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1623 if (HAS_PCH_IBX(dev_priv->dev) &&
1624 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1625 val |= TRANS_LEGACY_INTERLACED_ILK;
1626 else
1627 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1628 else
1629 val |= TRANS_PROGRESSIVE;
1630
040484af
JB		 1631 I915_WRITE(reg, val | TRANS_ENABLE);
1632 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1633 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1634}
1635
8fb033d7 1636static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1637 enum transcoder cpu_transcoder)
040484af 1638{
8fb033d7 1639 u32 val, pipeconf_val;
8fb033d7
PZ		 1640
1641 /* PCH only available on ILK+ */
1642 BUG_ON(dev_priv->info->gen < 5);
1643
8fb033d7 1644 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1645 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1646 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1647
223a6fdf
PZ		 1648 /* Workaround: set timing override bit. */
1649 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1650 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1651 I915_WRITE(_TRANSA_CHICKEN2, val);
1652
25f3ef11 1653 val = TRANS_ENABLE;
937bb610 1654 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1655
9a76b1c6
PZ		 1656 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1657 PIPECONF_INTERLACED_ILK)
a35f2679 1658 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1659 else
1660 val |= TRANS_PROGRESSIVE;
1661
25f3ef11 1662 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1663 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1664 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1665}
1666
b8a4f404
PZ		 1667static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1668 enum pipe pipe)
040484af 1669{
23670b32
DV		 1670 struct drm_device *dev = dev_priv->dev;
1671 uint32_t reg, val;
040484af
JB		 1672
1673 /* FDI relies on the transcoder */
1674 assert_fdi_tx_disabled(dev_priv, pipe);
1675 assert_fdi_rx_disabled(dev_priv, pipe);
1676
291906f1
JB		 1677 /* Ports must be off as well */
1678 assert_pch_ports_disabled(dev_priv, pipe);
1679
040484af
JB		 1680 reg = TRANSCONF(pipe);
1681 val = I915_READ(reg);
1682 val &= ~TRANS_ENABLE;
1683 I915_WRITE(reg, val);
1684 /* wait for PCH transcoder off, transcoder state */
1685 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1686 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1687
1688 if (!HAS_PCH_IBX(dev)) {
1689 /* Workaround: Clear the timing override chicken bit again. */
1690 reg = TRANS_CHICKEN2(pipe);
1691 val = I915_READ(reg);
1692 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1693 I915_WRITE(reg, val);
1694 }
040484af
JB		 1695}
1696
ab4d966c 1697static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1698{
8fb033d7
PZ		 1699 u32 val;
1700
8a52fd9f 1701 val = I915_READ(_TRANSACONF);
8fb033d7 1702 val &= ~TRANS_ENABLE;
8a52fd9f 1703 I915_WRITE(_TRANSACONF, val);
8fb033d7 1704 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1705 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1706 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1707
1708 /* Workaround: clear timing override bit. */
1709 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1710 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1711 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1712}
1713
b24e7179 1714/**
309cfea8 1715 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1716 * @dev_priv: i915 private structure
1717 * @pipe: pipe to enable
040484af 1718 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1719 *
1720 * Enable @pipe, making sure that various hardware specific requirements
1721 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1722 *
1723 * @pipe should be %PIPE_A or %PIPE_B.
1724 *
1725 * Will wait until the pipe is actually running (i.e. first vblank) before
1726 * returning.
1727 */
040484af
JB		 1728static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1729 bool pch_port)
b24e7179 1730{
702e7a56
PZ		 1731 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1732 pipe);
1a240d4d 1733 enum pipe pch_transcoder;
b24e7179
JB		 1734 int reg;
1735 u32 val;
1736
58c6eaa2
DV		 1737 assert_planes_disabled(dev_priv, pipe);
1738 assert_sprites_disabled(dev_priv, pipe);
1739
681e5811 1740 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1741 pch_transcoder = TRANSCODER_A;
1742 else
1743 pch_transcoder = pipe;
1744
b24e7179
JB		 1745 /*
1746 * A pipe without a PLL won't actually be able to drive bits from
1747 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1748 * need the check.
1749 */
1750 if (!HAS_PCH_SPLIT(dev_priv->dev))
1751 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1752 else {
1753 if (pch_port) {
1754 /* if driving the PCH, we need FDI enabled */
cc391bbb 1755 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1756 assert_fdi_tx_pll_enabled(dev_priv,
1757 (enum pipe) cpu_transcoder);
040484af
JB		 1758 }
1759 /* FIXME: assert CPU port conditions for SNB+ */
1760 }
b24e7179 1761
702e7a56 1762 reg = PIPECONF(cpu_transcoder);
b24e7179 1763 val = I915_READ(reg);
00d70b15
CW		 1764 if (val & PIPECONF_ENABLE)
1765 return;
1766
1767 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1768 intel_wait_for_vblank(dev_priv->dev, pipe);
1769}
1770
1771/**
309cfea8 1772 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1773 * @dev_priv: i915 private structure
1774 * @pipe: pipe to disable
1775 *
1776 * Disable @pipe, making sure that various hardware specific requirements
1777 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1778 *
1779 * @pipe should be %PIPE_A or %PIPE_B.
1780 *
1781 * Will wait until the pipe has shut down before returning.
1782 */
1783static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1784 enum pipe pipe)
1785{
702e7a56
PZ		 1786 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1787 pipe);
b24e7179
JB		 1788 int reg;
1789 u32 val;
1790
1791 /*
1792 * Make sure planes won't keep trying to pump pixels to us,
1793 * or we might hang the display.
1794 */
1795 assert_planes_disabled(dev_priv, pipe);
19332d7a 1796 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1797
1798 /* Don't disable pipe A or pipe A PLLs if needed */
1799 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1800 return;
1801
702e7a56 1802 reg = PIPECONF(cpu_transcoder);
b24e7179 1803 val = I915_READ(reg);
00d70b15
CW		 1804 if ((val & PIPECONF_ENABLE) == 0)
1805 return;
1806
1807 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1808 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1809}
1810
d74362c9
KP		 1811/*
1812 * Plane regs are double buffered, going from enabled->disabled needs a
1813 * trigger in order to latch. The display address reg provides this.
1814 */
6f1d69b0 1815void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1816 enum plane plane)
1817{
14f86147
DL		 1818 if (dev_priv->info->gen >= 4)
1819 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1820 else
1821 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1822}
1823
b24e7179
JB		 1824/**
1825 * intel_enable_plane - enable a display plane on a given pipe
1826 * @dev_priv: i915 private structure
1827 * @plane: plane to enable
1828 * @pipe: pipe being fed
1829 *
1830 * Enable @plane on @pipe, making sure that @pipe is running first.
1831 */
1832static void intel_enable_plane(struct drm_i915_private *dev_priv,
1833 enum plane plane, enum pipe pipe)
1834{
1835 int reg;
1836 u32 val;
1837
1838 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1839 assert_pipe_enabled(dev_priv, pipe);
1840
1841 reg = DSPCNTR(plane);
1842 val = I915_READ(reg);
00d70b15
CW		 1843 if (val & DISPLAY_PLANE_ENABLE)
1844 return;
1845
1846 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1847 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1848 intel_wait_for_vblank(dev_priv->dev, pipe);
1849}
1850
b24e7179
JB		 1851/**
1852 * intel_disable_plane - disable a display plane
1853 * @dev_priv: i915 private structure
1854 * @plane: plane to disable
1855 * @pipe: pipe consuming the data
1856 *
1857 * Disable @plane; should be an independent operation.
1858 */
1859static void intel_disable_plane(struct drm_i915_private *dev_priv,
1860 enum plane plane, enum pipe pipe)
1861{
1862 int reg;
1863 u32 val;
1864
1865 reg = DSPCNTR(plane);
1866 val = I915_READ(reg);
00d70b15
CW		 1867 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1868 return;
1869
1870 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1871 intel_flush_display_plane(dev_priv, plane);
1872 intel_wait_for_vblank(dev_priv->dev, pipe);
1873}
1874
693db184
CW		 1875static bool need_vtd_wa(struct drm_device *dev)
1876{
1877#ifdef CONFIG_INTEL_IOMMU
1878 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1879 return true;
1880#endif
1881 return false;
1882}
1883
127bd2ac 1884int
48b956c5 1885intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1886 struct drm_i915_gem_object *obj,
919926ae 1887 struct intel_ring_buffer *pipelined)
6b95a207 1888{
ce453d81 1889 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1890 u32 alignment;
1891 int ret;
1892
05394f39 1893 switch (obj->tiling_mode) {
6b95a207 1894 case I915_TILING_NONE:
534843da
CW		 1895 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1896 alignment = 128 * 1024;
a6c45cf0 1897 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1898 alignment = 4 * 1024;
1899 else
1900 alignment = 64 * 1024;
6b95a207
KH		 1901 break;
1902 case I915_TILING_X:
1903 /* pin() will align the object as required by fence */
1904 alignment = 0;
1905 break;
1906 case I915_TILING_Y:
8bb6e959
DV		 1907 /* Despite that we check this in framebuffer_init userspace can
1908 * screw us over and change the tiling after the fact. Only
1909 * pinned buffers can't change their tiling. */
1910 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1911 return -EINVAL;
1912 default:
1913 BUG();
1914 }
1915
693db184
CW		 1916 /* Note that the w/a also requires 64 PTE of padding following the
1917 * bo. We currently fill all unused PTE with the shadow page and so
1918 * we should always have valid PTE following the scanout preventing
1919 * the VT-d warning.
1920 */
1921 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1922 alignment = 256 * 1024;
1923
ce453d81 1924 dev_priv->mm.interruptible = false;
2da3b9b9 1925 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1926 if (ret)
ce453d81 1927 goto err_interruptible;
6b95a207
KH		 1928
1929 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1930 * fence, whereas 965+ only requires a fence if using
1931 * framebuffer compression. For simplicity, we always install
1932 * a fence as the cost is not that onerous.
1933 */
06d98131 1934 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1935 if (ret)
1936 goto err_unpin;
1690e1eb 1937
9a5a53b3 1938 i915_gem_object_pin_fence(obj);
6b95a207 1939
ce453d81 1940 dev_priv->mm.interruptible = true;
6b95a207 1941 return 0;
48b956c5
CW		 1942
1943err_unpin:
1944 i915_gem_object_unpin(obj);
ce453d81
CW		 1945err_interruptible:
1946 dev_priv->mm.interruptible = true;
48b956c5 1947 return ret;
6b95a207
KH		 1948}
1949
1690e1eb
CW		 1950void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1951{
1952 i915_gem_object_unpin_fence(obj);
1953 i915_gem_object_unpin(obj);
1954}
1955
c2c75131
DV		 1956/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1957 * is assumed to be a power-of-two. */
bc752862
CW		 1958unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1959 unsigned int tiling_mode,
1960 unsigned int cpp,
1961 unsigned int pitch)
c2c75131 1962{
bc752862
CW		 1963 if (tiling_mode != I915_TILING_NONE) {
1964 unsigned int tile_rows, tiles;
c2c75131 1965
bc752862
CW		 1966 tile_rows = *y / 8;
1967 *y %= 8;
c2c75131 1968
bc752862
CW		 1969 tiles = *x / (512/cpp);
1970 *x %= 512/cpp;
1971
1972 return tile_rows * pitch * 8 + tiles * 4096;
1973 } else {
1974 unsigned int offset;
1975
1976 offset = *y * pitch + *x * cpp;
1977 *y = 0;
1978 *x = (offset & 4095) / cpp;
1979 return offset & -4096;
1980 }
c2c75131
DV		 1981}
1982
17638cd6
JB		 1983static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1984 int x, int y)
81255565
JB		 1985{
1986 struct drm_device *dev = crtc->dev;
1987 struct drm_i915_private *dev_priv = dev->dev_private;
1988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1989 struct intel_framebuffer *intel_fb;
05394f39 1990 struct drm_i915_gem_object *obj;
81255565 1991 int plane = intel_crtc->plane;
e506a0c6 1992 unsigned long linear_offset;
81255565 1993 u32 dspcntr;
5eddb70b 1994 u32 reg;
81255565
JB		 1995
1996 switch (plane) {
1997 case 0:
1998 case 1:
1999 break;
2000 default:
84f44ce7 2001 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 2002 return -EINVAL;
2003 }
2004
2005 intel_fb = to_intel_framebuffer(fb);
2006 obj = intel_fb->obj;
81255565 2007
5eddb70b
CW		 2008 reg = DSPCNTR(plane);
2009 dspcntr = I915_READ(reg);
81255565
JB		 2010 /* Mask out pixel format bits in case we change it */
2011 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2012 switch (fb->pixel_format) {
2013 case DRM_FORMAT_C8:
81255565
JB		 2014 dspcntr |= DISPPLANE_8BPP;
2015 break;
57779d06
VS		 2016 case DRM_FORMAT_XRGB1555:
2017 case DRM_FORMAT_ARGB1555:
2018 dspcntr |= DISPPLANE_BGRX555;
81255565 2019 break;
57779d06
VS		 2020 case DRM_FORMAT_RGB565:
2021 dspcntr |= DISPPLANE_BGRX565;
2022 break;
2023 case DRM_FORMAT_XRGB8888:
2024 case DRM_FORMAT_ARGB8888:
2025 dspcntr |= DISPPLANE_BGRX888;
2026 break;
2027 case DRM_FORMAT_XBGR8888:
2028 case DRM_FORMAT_ABGR8888:
2029 dspcntr |= DISPPLANE_RGBX888;
2030 break;
2031 case DRM_FORMAT_XRGB2101010:
2032 case DRM_FORMAT_ARGB2101010:
2033 dspcntr |= DISPPLANE_BGRX101010;
2034 break;
2035 case DRM_FORMAT_XBGR2101010:
2036 case DRM_FORMAT_ABGR2101010:
2037 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2038 break;
2039 default:
baba133a 2040 BUG();
81255565 2041 }
57779d06 2042
a6c45cf0 2043 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2044 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2045 dspcntr |= DISPPLANE_TILED;
2046 else
2047 dspcntr &= ~DISPPLANE_TILED;
2048 }
2049
5eddb70b 2050 I915_WRITE(reg, dspcntr);
81255565 2051
e506a0c6 2052 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2053
c2c75131
DV		 2054 if (INTEL_INFO(dev)->gen >= 4) {
2055 intel_crtc->dspaddr_offset =
bc752862
CW		 2056 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2057 fb->bits_per_pixel / 8,
2058 fb->pitches[0]);
c2c75131
DV		 2059 linear_offset -= intel_crtc->dspaddr_offset;
2060 } else {
e506a0c6 2061 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2062 }
e506a0c6
DV		 2063
2064 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2065 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2066 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2067 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2068 I915_MODIFY_DISPBASE(DSPSURF(plane),
2069 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2070 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2071 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2072 } else
e506a0c6 2073 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2074 POSTING_READ(reg);
81255565 2075
17638cd6
JB		 2076 return 0;
2077}
2078
2079static int ironlake_update_plane(struct drm_crtc *crtc,
2080 struct drm_framebuffer *fb, int x, int y)
2081{
2082 struct drm_device *dev = crtc->dev;
2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085 struct intel_framebuffer *intel_fb;
2086 struct drm_i915_gem_object *obj;
2087 int plane = intel_crtc->plane;
e506a0c6 2088 unsigned long linear_offset;
17638cd6
JB		 2089 u32 dspcntr;
2090 u32 reg;
2091
2092 switch (plane) {
2093 case 0:
2094 case 1:
27f8227b 2095 case 2:
17638cd6
JB		 2096 break;
2097 default:
84f44ce7 2098 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2099 return -EINVAL;
2100 }
2101
2102 intel_fb = to_intel_framebuffer(fb);
2103 obj = intel_fb->obj;
2104
2105 reg = DSPCNTR(plane);
2106 dspcntr = I915_READ(reg);
2107 /* Mask out pixel format bits in case we change it */
2108 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2109 switch (fb->pixel_format) {
2110 case DRM_FORMAT_C8:
17638cd6
JB		 2111 dspcntr |= DISPPLANE_8BPP;
2112 break;
57779d06
VS		 2113 case DRM_FORMAT_RGB565:
2114 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2115 break;
57779d06
VS		 2116 case DRM_FORMAT_XRGB8888:
2117 case DRM_FORMAT_ARGB8888:
2118 dspcntr |= DISPPLANE_BGRX888;
2119 break;
2120 case DRM_FORMAT_XBGR8888:
2121 case DRM_FORMAT_ABGR8888:
2122 dspcntr |= DISPPLANE_RGBX888;
2123 break;
2124 case DRM_FORMAT_XRGB2101010:
2125 case DRM_FORMAT_ARGB2101010:
2126 dspcntr |= DISPPLANE_BGRX101010;
2127 break;
2128 case DRM_FORMAT_XBGR2101010:
2129 case DRM_FORMAT_ABGR2101010:
2130 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2131 break;
2132 default:
baba133a 2133 BUG();
17638cd6
JB		 2134 }
2135
2136 if (obj->tiling_mode != I915_TILING_NONE)
2137 dspcntr |= DISPPLANE_TILED;
2138 else
2139 dspcntr &= ~DISPPLANE_TILED;
2140
2141 /* must disable */
2142 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2143
2144 I915_WRITE(reg, dspcntr);
2145
e506a0c6 2146 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2147 intel_crtc->dspaddr_offset =
bc752862
CW		 2148 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2149 fb->bits_per_pixel / 8,
2150 fb->pitches[0]);
c2c75131 2151 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2152
e506a0c6
DV		 2153 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2154 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2155 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2156 I915_MODIFY_DISPBASE(DSPSURF(plane),
2157 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2158 if (IS_HASWELL(dev)) {
2159 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2160 } else {
2161 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2162 I915_WRITE(DSPLINOFF(plane), linear_offset);
2163 }
17638cd6
JB		 2164 POSTING_READ(reg);
2165
2166 return 0;
2167}
2168
2169/* Assume fb object is pinned & idle & fenced and just update base pointers */
2170static int
2171intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2172 int x, int y, enum mode_set_atomic state)
2173{
2174 struct drm_device *dev = crtc->dev;
2175 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2176
6b8e6ed0
CW		 2177 if (dev_priv->display.disable_fbc)
2178 dev_priv->display.disable_fbc(dev);
3dec0095 2179 intel_increase_pllclock(crtc);
81255565 2180
6b8e6ed0 2181 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2182}
2183
96a02917
VS		 2184void intel_display_handle_reset(struct drm_device *dev)
2185{
2186 struct drm_i915_private *dev_priv = dev->dev_private;
2187 struct drm_crtc *crtc;
2188
2189 /*
2190 * Flips in the rings have been nuked by the reset,
2191 * so complete all pending flips so that user space
2192 * will get its events and not get stuck.
2193 *
2194 * Also update the base address of all primary
2195 * planes to the the last fb to make sure we're
2196 * showing the correct fb after a reset.
2197 *
2198 * Need to make two loops over the crtcs so that we
2199 * don't try to grab a crtc mutex before the
2200 * pending_flip_queue really got woken up.
2201 */
2202
2203 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2205 enum plane plane = intel_crtc->plane;
2206
2207 intel_prepare_page_flip(dev, plane);
2208 intel_finish_page_flip_plane(dev, plane);
2209 }
2210
2211 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2213
2214 mutex_lock(&crtc->mutex);
2215 if (intel_crtc->active)
2216 dev_priv->display.update_plane(crtc, crtc->fb,
2217 crtc->x, crtc->y);
2218 mutex_unlock(&crtc->mutex);
2219 }
2220}
2221
14667a4b
CW		 2222static int
2223intel_finish_fb(struct drm_framebuffer *old_fb)
2224{
2225 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2226 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2227 bool was_interruptible = dev_priv->mm.interruptible;
2228 int ret;
2229
14667a4b
CW		 2230 /* Big Hammer, we also need to ensure that any pending
2231 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2232 * current scanout is retired before unpinning the old
2233 * framebuffer.
2234 *
2235 * This should only fail upon a hung GPU, in which case we
2236 * can safely continue.
2237 */
2238 dev_priv->mm.interruptible = false;
2239 ret = i915_gem_object_finish_gpu(obj);
2240 dev_priv->mm.interruptible = was_interruptible;
2241
2242 return ret;
2243}
2244
198598d0
VS		 2245static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2246{
2247 struct drm_device *dev = crtc->dev;
2248 struct drm_i915_master_private *master_priv;
2249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2250
2251 if (!dev->primary->master)
2252 return;
2253
2254 master_priv = dev->primary->master->driver_priv;
2255 if (!master_priv->sarea_priv)
2256 return;
2257
2258 switch (intel_crtc->pipe) {
2259 case 0:
2260 master_priv->sarea_priv->pipeA_x = x;
2261 master_priv->sarea_priv->pipeA_y = y;
2262 break;
2263 case 1:
2264 master_priv->sarea_priv->pipeB_x = x;
2265 master_priv->sarea_priv->pipeB_y = y;
2266 break;
2267 default:
2268 break;
2269 }
2270}
2271
5c3b82e2 2272static int
3c4fdcfb 2273intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2274 struct drm_framebuffer *fb)
79e53945
JB		 2275{
2276 struct drm_device *dev = crtc->dev;
6b8e6ed0 2277 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2279 struct drm_framebuffer *old_fb;
5c3b82e2 2280 int ret;
79e53945
JB		 2281
2282 /* no fb bound */
94352cf9 2283 if (!fb) {
a5071c2f 2284 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2285 return 0;
2286 }
2287
7eb552ae 2288 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2289 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2290 plane_name(intel_crtc->plane),
2291 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2292 return -EINVAL;
79e53945
JB		 2293 }
2294
5c3b82e2 2295 mutex_lock(&dev->struct_mutex);
265db958 2296 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2297 to_intel_framebuffer(fb)->obj,
919926ae 2298 NULL);
5c3b82e2
CW		 2299 if (ret != 0) {
2300 mutex_unlock(&dev->struct_mutex);
a5071c2f 2301 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2302 return ret;
2303 }
79e53945 2304
94352cf9 2305 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2306 if (ret) {
94352cf9 2307 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2308 mutex_unlock(&dev->struct_mutex);
a5071c2f 2309 DRM_ERROR("failed to update base address\n");
4e6cfefc 2310 return ret;
79e53945 2311 }
3c4fdcfb 2312
94352cf9
DV		 2313 old_fb = crtc->fb;
2314 crtc->fb = fb;
6c4c86f5
DV		 2315 crtc->x = x;
2316 crtc->y = y;
94352cf9 2317
b7f1de28
CW		 2318 if (old_fb) {
2319 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2320 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2321 }
652c393a 2322
6b8e6ed0 2323 intel_update_fbc(dev);
5c3b82e2 2324 mutex_unlock(&dev->struct_mutex);
79e53945 2325
198598d0 2326 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2327
2328 return 0;
79e53945
JB		 2329}
2330
5e84e1a4
ZW		 2331static void intel_fdi_normal_train(struct drm_crtc *crtc)
2332{
2333 struct drm_device *dev = crtc->dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336 int pipe = intel_crtc->pipe;
2337 u32 reg, temp;
2338
2339 /* enable normal train */
2340 reg = FDI_TX_CTL(pipe);
2341 temp = I915_READ(reg);
61e499bf 2342 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2343 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2344 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2345 } else {
2346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2348 }
5e84e1a4
ZW		 2349 I915_WRITE(reg, temp);
2350
2351 reg = FDI_RX_CTL(pipe);
2352 temp = I915_READ(reg);
2353 if (HAS_PCH_CPT(dev)) {
2354 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2355 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2356 } else {
2357 temp &= ~FDI_LINK_TRAIN_NONE;
2358 temp |= FDI_LINK_TRAIN_NONE;
2359 }
2360 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2361
2362 /* wait one idle pattern time */
2363 POSTING_READ(reg);
2364 udelay(1000);
357555c0
JB		 2365
2366 /* IVB wants error correction enabled */
2367 if (IS_IVYBRIDGE(dev))
2368 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2369 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2370}
2371
1e833f40
DV		 2372static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2373{
2374 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2375}
2376
01a415fd
DV		 2377static void ivb_modeset_global_resources(struct drm_device *dev)
2378{
2379 struct drm_i915_private *dev_priv = dev->dev_private;
2380 struct intel_crtc *pipe_B_crtc =
2381 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2382 struct intel_crtc *pipe_C_crtc =
2383 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2384 uint32_t temp;
2385
1e833f40
DV		 2386 /*
2387 * When everything is off disable fdi C so that we could enable fdi B
2388 * with all lanes. Note that we don't care about enabled pipes without
2389 * an enabled pch encoder.
2390 */
2391 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2392 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2393 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2394 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2395
2396 temp = I915_READ(SOUTH_CHICKEN1);
2397 temp &= ~FDI_BC_BIFURCATION_SELECT;
2398 DRM_DEBUG_KMS("disabling fdi C rx\n");
2399 I915_WRITE(SOUTH_CHICKEN1, temp);
2400 }
2401}
2402
8db9d77b
ZW		 2403/* The FDI link training functions for ILK/Ibexpeak. */
2404static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2405{
2406 struct drm_device *dev = crtc->dev;
2407 struct drm_i915_private *dev_priv = dev->dev_private;
2408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409 int pipe = intel_crtc->pipe;
0fc932b8 2410 int plane = intel_crtc->plane;
5eddb70b 2411 u32 reg, temp, tries;
8db9d77b 2412
0fc932b8
JB		 2413 /* FDI needs bits from pipe & plane first */
2414 assert_pipe_enabled(dev_priv, pipe);
2415 assert_plane_enabled(dev_priv, plane);
2416
e1a44743
AJ		 2417 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2418 for train result */
5eddb70b
CW		 2419 reg = FDI_RX_IMR(pipe);
2420 temp = I915_READ(reg);
e1a44743
AJ		 2421 temp &= ~FDI_RX_SYMBOL_LOCK;
2422 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2423 I915_WRITE(reg, temp);
2424 I915_READ(reg);
e1a44743
AJ		 2425 udelay(150);
2426
8db9d77b 2427 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2428 reg = FDI_TX_CTL(pipe);
2429 temp = I915_READ(reg);
627eb5a3
DV		 2430 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2431 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2434 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2435
5eddb70b
CW		 2436 reg = FDI_RX_CTL(pipe);
2437 temp = I915_READ(reg);
8db9d77b
ZW		 2438 temp &= ~FDI_LINK_TRAIN_NONE;
2439 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2440 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2441
2442 POSTING_READ(reg);
8db9d77b
ZW		 2443 udelay(150);
2444
5b2adf89 2445 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2447 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2448 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2449
5eddb70b 2450 reg = FDI_RX_IIR(pipe);
e1a44743 2451 for (tries = 0; tries < 5; tries++) {
5eddb70b 2452 temp = I915_READ(reg);
8db9d77b
ZW		 2453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455 if ((temp & FDI_RX_BIT_LOCK)) {
2456 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2457 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2458 break;
2459 }
8db9d77b 2460 }
e1a44743 2461 if (tries == 5)
5eddb70b 2462 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2463
2464 /* Train 2 */
5eddb70b
CW		 2465 reg = FDI_TX_CTL(pipe);
2466 temp = I915_READ(reg);
8db9d77b
ZW		 2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2469 I915_WRITE(reg, temp);
8db9d77b 2470
5eddb70b
CW		 2471 reg = FDI_RX_CTL(pipe);
2472 temp = I915_READ(reg);
8db9d77b
ZW		 2473 temp &= ~FDI_LINK_TRAIN_NONE;
2474 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2475 I915_WRITE(reg, temp);
8db9d77b 2476
5eddb70b
CW		 2477 POSTING_READ(reg);
2478 udelay(150);
8db9d77b 2479
5eddb70b 2480 reg = FDI_RX_IIR(pipe);
e1a44743 2481 for (tries = 0; tries < 5; tries++) {
5eddb70b 2482 temp = I915_READ(reg);
8db9d77b
ZW		 2483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484
2485 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2486 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2487 DRM_DEBUG_KMS("FDI train 2 done.\n");
2488 break;
2489 }
8db9d77b 2490 }
e1a44743 2491 if (tries == 5)
5eddb70b 2492 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2493
2494 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2495
8db9d77b
ZW		 2496}
2497
0206e353 2498static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2499 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2500 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2501 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2502 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2503};
2504
2505/* The FDI link training functions for SNB/Cougarpoint. */
2506static void gen6_fdi_link_train(struct drm_crtc *crtc)
2507{
2508 struct drm_device *dev = crtc->dev;
2509 struct drm_i915_private *dev_priv = dev->dev_private;
2510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2511 int pipe = intel_crtc->pipe;
fa37d39e 2512 u32 reg, temp, i, retry;
8db9d77b 2513
e1a44743
AJ		 2514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2515 for train result */
5eddb70b
CW		 2516 reg = FDI_RX_IMR(pipe);
2517 temp = I915_READ(reg);
e1a44743
AJ		 2518 temp &= ~FDI_RX_SYMBOL_LOCK;
2519 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2520 I915_WRITE(reg, temp);
2521
2522 POSTING_READ(reg);
e1a44743
AJ		 2523 udelay(150);
2524
8db9d77b 2525 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2526 reg = FDI_TX_CTL(pipe);
2527 temp = I915_READ(reg);
627eb5a3
DV		 2528 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2529 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2530 temp &= ~FDI_LINK_TRAIN_NONE;
2531 temp |= FDI_LINK_TRAIN_PATTERN_1;
2532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2533 /* SNB-B */
2534 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2535 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2536
d74cf324
DV		 2537 I915_WRITE(FDI_RX_MISC(pipe),
2538 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2539
5eddb70b
CW		 2540 reg = FDI_RX_CTL(pipe);
2541 temp = I915_READ(reg);
8db9d77b
ZW		 2542 if (HAS_PCH_CPT(dev)) {
2543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2545 } else {
2546 temp &= ~FDI_LINK_TRAIN_NONE;
2547 temp |= FDI_LINK_TRAIN_PATTERN_1;
2548 }
5eddb70b
CW		 2549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2550
2551 POSTING_READ(reg);
8db9d77b
ZW		 2552 udelay(150);
2553
0206e353 2554 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2555 reg = FDI_TX_CTL(pipe);
2556 temp = I915_READ(reg);
8db9d77b
ZW		 2557 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2558 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2559 I915_WRITE(reg, temp);
2560
2561 POSTING_READ(reg);
8db9d77b
ZW		 2562 udelay(500);
2563
fa37d39e
SP		 2564 for (retry = 0; retry < 5; retry++) {
2565 reg = FDI_RX_IIR(pipe);
2566 temp = I915_READ(reg);
2567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2568 if (temp & FDI_RX_BIT_LOCK) {
2569 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2570 DRM_DEBUG_KMS("FDI train 1 done.\n");
2571 break;
2572 }
2573 udelay(50);
8db9d77b 2574 }
fa37d39e
SP		 2575 if (retry < 5)
2576 break;
8db9d77b
ZW		 2577 }
2578 if (i == 4)
5eddb70b 2579 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2580
2581 /* Train 2 */
5eddb70b
CW		 2582 reg = FDI_TX_CTL(pipe);
2583 temp = I915_READ(reg);
8db9d77b
ZW		 2584 temp &= ~FDI_LINK_TRAIN_NONE;
2585 temp |= FDI_LINK_TRAIN_PATTERN_2;
2586 if (IS_GEN6(dev)) {
2587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588 /* SNB-B */
2589 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2590 }
5eddb70b 2591 I915_WRITE(reg, temp);
8db9d77b 2592
5eddb70b
CW		 2593 reg = FDI_RX_CTL(pipe);
2594 temp = I915_READ(reg);
8db9d77b
ZW		 2595 if (HAS_PCH_CPT(dev)) {
2596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2598 } else {
2599 temp &= ~FDI_LINK_TRAIN_NONE;
2600 temp |= FDI_LINK_TRAIN_PATTERN_2;
2601 }
5eddb70b
CW		 2602 I915_WRITE(reg, temp);
2603
2604 POSTING_READ(reg);
8db9d77b
ZW		 2605 udelay(150);
2606
0206e353 2607 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2608 reg = FDI_TX_CTL(pipe);
2609 temp = I915_READ(reg);
8db9d77b
ZW		 2610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2612 I915_WRITE(reg, temp);
2613
2614 POSTING_READ(reg);
8db9d77b
ZW		 2615 udelay(500);
2616
fa37d39e
SP		 2617 for (retry = 0; retry < 5; retry++) {
2618 reg = FDI_RX_IIR(pipe);
2619 temp = I915_READ(reg);
2620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621 if (temp & FDI_RX_SYMBOL_LOCK) {
2622 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2623 DRM_DEBUG_KMS("FDI train 2 done.\n");
2624 break;
2625 }
2626 udelay(50);
8db9d77b 2627 }
fa37d39e
SP		 2628 if (retry < 5)
2629 break;
8db9d77b
ZW		 2630 }
2631 if (i == 4)
5eddb70b 2632 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2633
2634 DRM_DEBUG_KMS("FDI train done.\n");
2635}
2636
357555c0
JB		 2637/* Manual link training for Ivy Bridge A0 parts */
2638static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2639{
2640 struct drm_device *dev = crtc->dev;
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643 int pipe = intel_crtc->pipe;
2644 u32 reg, temp, i;
2645
2646 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2647 for train result */
2648 reg = FDI_RX_IMR(pipe);
2649 temp = I915_READ(reg);
2650 temp &= ~FDI_RX_SYMBOL_LOCK;
2651 temp &= ~FDI_RX_BIT_LOCK;
2652 I915_WRITE(reg, temp);
2653
2654 POSTING_READ(reg);
2655 udelay(150);
2656
01a415fd
DV		 2657 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2658 I915_READ(FDI_RX_IIR(pipe)));
2659
357555c0
JB		 2660 /* enable CPU FDI TX and PCH FDI RX */
2661 reg = FDI_TX_CTL(pipe);
2662 temp = I915_READ(reg);
627eb5a3
DV		 2663 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2664 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2665 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2666 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2667 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2668 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2669 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2670 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2671
d74cf324
DV		 2672 I915_WRITE(FDI_RX_MISC(pipe),
2673 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2674
357555c0
JB		 2675 reg = FDI_RX_CTL(pipe);
2676 temp = I915_READ(reg);
2677 temp &= ~FDI_LINK_TRAIN_AUTO;
2678 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2679 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2680 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2681 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2682
2683 POSTING_READ(reg);
2684 udelay(150);
2685
0206e353 2686 for (i = 0; i < 4; i++) {
357555c0
JB		 2687 reg = FDI_TX_CTL(pipe);
2688 temp = I915_READ(reg);
2689 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690 temp |= snb_b_fdi_train_param[i];
2691 I915_WRITE(reg, temp);
2692
2693 POSTING_READ(reg);
2694 udelay(500);
2695
2696 reg = FDI_RX_IIR(pipe);
2697 temp = I915_READ(reg);
2698 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2699
2700 if (temp & FDI_RX_BIT_LOCK ||
2701 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2702 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2703 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2704 break;
2705 }
2706 }
2707 if (i == 4)
2708 DRM_ERROR("FDI train 1 fail!\n");
2709
2710 /* Train 2 */
2711 reg = FDI_TX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2714 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2715 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2716 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2717 I915_WRITE(reg, temp);
2718
2719 reg = FDI_RX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2722 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2723 I915_WRITE(reg, temp);
2724
2725 POSTING_READ(reg);
2726 udelay(150);
2727
0206e353 2728 for (i = 0; i < 4; i++) {
357555c0
JB		 2729 reg = FDI_TX_CTL(pipe);
2730 temp = I915_READ(reg);
2731 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2732 temp |= snb_b_fdi_train_param[i];
2733 I915_WRITE(reg, temp);
2734
2735 POSTING_READ(reg);
2736 udelay(500);
2737
2738 reg = FDI_RX_IIR(pipe);
2739 temp = I915_READ(reg);
2740 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2741
2742 if (temp & FDI_RX_SYMBOL_LOCK) {
2743 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2744 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2745 break;
2746 }
2747 }
2748 if (i == 4)
2749 DRM_ERROR("FDI train 2 fail!\n");
2750
2751 DRM_DEBUG_KMS("FDI train done.\n");
2752}
2753
88cefb6c 2754static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2755{
88cefb6c 2756 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2757 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2758 int pipe = intel_crtc->pipe;
5eddb70b 2759 u32 reg, temp;
79e53945 2760
c64e311e 2761
c98e9dcf 2762 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2763 reg = FDI_RX_CTL(pipe);
2764 temp = I915_READ(reg);
627eb5a3
DV		 2765 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2766 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2767 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2768 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2769
2770 POSTING_READ(reg);
c98e9dcf
JB		 2771 udelay(200);
2772
2773 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2774 temp = I915_READ(reg);
2775 I915_WRITE(reg, temp | FDI_PCDCLK);
2776
2777 POSTING_READ(reg);
c98e9dcf
JB		 2778 udelay(200);
2779
20749730
PZ		 2780 /* Enable CPU FDI TX PLL, always on for Ironlake */
2781 reg = FDI_TX_CTL(pipe);
2782 temp = I915_READ(reg);
2783 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2784 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2785
20749730
PZ		 2786 POSTING_READ(reg);
2787 udelay(100);
6be4a607 2788 }
0e23b99d
JB		 2789}
2790
88cefb6c
DV		 2791static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2792{
2793 struct drm_device *dev = intel_crtc->base.dev;
2794 struct drm_i915_private *dev_priv = dev->dev_private;
2795 int pipe = intel_crtc->pipe;
2796 u32 reg, temp;
2797
2798 /* Switch from PCDclk to Rawclk */
2799 reg = FDI_RX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2802
2803 /* Disable CPU FDI TX PLL */
2804 reg = FDI_TX_CTL(pipe);
2805 temp = I915_READ(reg);
2806 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2807
2808 POSTING_READ(reg);
2809 udelay(100);
2810
2811 reg = FDI_RX_CTL(pipe);
2812 temp = I915_READ(reg);
2813 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2814
2815 /* Wait for the clocks to turn off. */
2816 POSTING_READ(reg);
2817 udelay(100);
2818}
2819
0fc932b8
JB		 2820static void ironlake_fdi_disable(struct drm_crtc *crtc)
2821{
2822 struct drm_device *dev = crtc->dev;
2823 struct drm_i915_private *dev_priv = dev->dev_private;
2824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2825 int pipe = intel_crtc->pipe;
2826 u32 reg, temp;
2827
2828 /* disable CPU FDI tx and PCH FDI rx */
2829 reg = FDI_TX_CTL(pipe);
2830 temp = I915_READ(reg);
2831 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2832 POSTING_READ(reg);
2833
2834 reg = FDI_RX_CTL(pipe);
2835 temp = I915_READ(reg);
2836 temp &= ~(0x7 << 16);
dfd07d72 2837 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2838 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2839
2840 POSTING_READ(reg);
2841 udelay(100);
2842
2843 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2844 if (HAS_PCH_IBX(dev)) {
2845 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2846 }
0fc932b8
JB		 2847
2848 /* still set train pattern 1 */
2849 reg = FDI_TX_CTL(pipe);
2850 temp = I915_READ(reg);
2851 temp &= ~FDI_LINK_TRAIN_NONE;
2852 temp |= FDI_LINK_TRAIN_PATTERN_1;
2853 I915_WRITE(reg, temp);
2854
2855 reg = FDI_RX_CTL(pipe);
2856 temp = I915_READ(reg);
2857 if (HAS_PCH_CPT(dev)) {
2858 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2859 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2860 } else {
2861 temp &= ~FDI_LINK_TRAIN_NONE;
2862 temp |= FDI_LINK_TRAIN_PATTERN_1;
2863 }
2864 /* BPC in FDI rx is consistent with that in PIPECONF */
2865 temp &= ~(0x07 << 16);
dfd07d72 2866 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2867 I915_WRITE(reg, temp);
2868
2869 POSTING_READ(reg);
2870 udelay(100);
2871}
2872
5bb61643
CW		 2873static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2874{
2875 struct drm_device *dev = crtc->dev;
2876 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2878 unsigned long flags;
2879 bool pending;
2880
10d83730
VS		 2881 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2882 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2883 return false;
2884
2885 spin_lock_irqsave(&dev->event_lock, flags);
2886 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2887 spin_unlock_irqrestore(&dev->event_lock, flags);
2888
2889 return pending;
2890}
2891
e6c3a2a6
CW		 2892static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2893{
0f91128d 2894 struct drm_device *dev = crtc->dev;
5bb61643 2895 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2896
2897 if (crtc->fb == NULL)
2898 return;
2899
2c10d571
DV		 2900 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2901
5bb61643
CW		 2902 wait_event(dev_priv->pending_flip_queue,
2903 !intel_crtc_has_pending_flip(crtc));
2904
0f91128d
CW		 2905 mutex_lock(&dev->struct_mutex);
2906 intel_finish_fb(crtc->fb);
2907 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2908}
2909
e615efe4
ED		 2910/* Program iCLKIP clock to the desired frequency */
2911static void lpt_program_iclkip(struct drm_crtc *crtc)
2912{
2913 struct drm_device *dev = crtc->dev;
2914 struct drm_i915_private *dev_priv = dev->dev_private;
2915 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2916 u32 temp;
2917
09153000
DV		 2918 mutex_lock(&dev_priv->dpio_lock);
2919
e615efe4
ED		 2920 /* It is necessary to ungate the pixclk gate prior to programming
2921 * the divisors, and gate it back when it is done.
2922 */
2923 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2924
2925 /* Disable SSCCTL */
2926 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2927 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2928 SBI_SSCCTL_DISABLE,
2929 SBI_ICLK);
e615efe4
ED		 2930
2931 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2932 if (crtc->mode.clock == 20000) {
2933 auxdiv = 1;
2934 divsel = 0x41;
2935 phaseinc = 0x20;
2936 } else {
2937 /* The iCLK virtual clock root frequency is in MHz,
2938 * but the crtc->mode.clock in in KHz. To get the divisors,
2939 * it is necessary to divide one by another, so we
2940 * convert the virtual clock precision to KHz here for higher
2941 * precision.
2942 */
2943 u32 iclk_virtual_root_freq = 172800 * 1000;
2944 u32 iclk_pi_range = 64;
2945 u32 desired_divisor, msb_divisor_value, pi_value;
2946
2947 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2948 msb_divisor_value = desired_divisor / iclk_pi_range;
2949 pi_value = desired_divisor % iclk_pi_range;
2950
2951 auxdiv = 0;
2952 divsel = msb_divisor_value - 2;
2953 phaseinc = pi_value;
2954 }
2955
2956 /* This should not happen with any sane values */
2957 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2958 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2959 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2960 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2961
2962 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2963 crtc->mode.clock,
2964 auxdiv,
2965 divsel,
2966 phasedir,
2967 phaseinc);
2968
2969 /* Program SSCDIVINTPHASE6 */
988d6ee8 2970 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2971 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2972 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2973 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2974 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2975 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2976 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2977 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2978
2979 /* Program SSCAUXDIV */
988d6ee8 2980 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2981 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2982 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2983 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2984
2985 /* Enable modulator and associated divider */
988d6ee8 2986 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2987 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2988 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2989
2990 /* Wait for initialization time */
2991 udelay(24);
2992
2993 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2994
2995 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2996}
2997
f67a559d
JB		 2998/*
2999 * Enable PCH resources required for PCH ports:
3000 * - PCH PLLs
3001 * - FDI training & RX/TX
3002 * - update transcoder timings
3003 * - DP transcoding bits
3004 * - transcoder
3005 */
3006static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3007{
3008 struct drm_device *dev = crtc->dev;
3009 struct drm_i915_private *dev_priv = dev->dev_private;
3010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3011 int pipe = intel_crtc->pipe;
ee7b9f93 3012 u32 reg, temp;
2c07245f 3013
e7e164db
CW		 3014 assert_transcoder_disabled(dev_priv, pipe);
3015
cd986abb
DV		 3016 /* Write the TU size bits before fdi link training, so that error
3017 * detection works. */
3018 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3019 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3020
c98e9dcf 3021 /* For PCH output, training FDI link */
674cf967 3022 dev_priv->display.fdi_link_train(crtc);
2c07245f 3023
572deb37
DV		 3024 /* XXX: pch pll's can be enabled any time before we enable the PCH
3025 * transcoder, and we actually should do this to not upset any PCH
3026 * transcoder that already use the clock when we share it.
3027 *
3028 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3029 * unconditionally resets the pll - we need that to have the right LVDS
3030 * enable sequence. */
b6b4e185 3031 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3032
303b81e0 3033 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3034 u32 sel;
4b645f14 3035
c98e9dcf 3036 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3037 switch (pipe) {
3038 default:
3039 case 0:
3040 temp |= TRANSA_DPLL_ENABLE;
3041 sel = TRANSA_DPLLB_SEL;
3042 break;
3043 case 1:
3044 temp |= TRANSB_DPLL_ENABLE;
3045 sel = TRANSB_DPLLB_SEL;
3046 break;
3047 case 2:
3048 temp |= TRANSC_DPLL_ENABLE;
3049 sel = TRANSC_DPLLB_SEL;
3050 break;
d64311ab 3051 }
ee7b9f93
JB		 3052 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3053 temp |= sel;
3054 else
3055 temp &= ~sel;
c98e9dcf 3056 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3057 }
5eddb70b 3058
d9b6cb56
JB		 3059 /* set transcoder timing, panel must allow it */
3060 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3061 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3062 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3063 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3064
5eddb70b
CW		 3065 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3066 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3067 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3068 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3069
303b81e0 3070 intel_fdi_normal_train(crtc);
5e84e1a4 3071
c98e9dcf
JB		 3072 /* For PCH DP, enable TRANS_DP_CTL */
3073 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3074 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3075 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3076 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3077 reg = TRANS_DP_CTL(pipe);
3078 temp = I915_READ(reg);
3079 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3080 TRANS_DP_SYNC_MASK |
3081 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3082 temp |= (TRANS_DP_OUTPUT_ENABLE |
3083 TRANS_DP_ENH_FRAMING);
9325c9f0 3084 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3085
3086 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3087 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3088 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3089 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3090
3091 switch (intel_trans_dp_port_sel(crtc)) {
3092 case PCH_DP_B:
5eddb70b 3093 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3094 break;
3095 case PCH_DP_C:
5eddb70b 3096 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3097 break;
3098 case PCH_DP_D:
5eddb70b 3099 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3100 break;
3101 default:
e95d41e1 3102 BUG();
32f9d658 3103 }
2c07245f 3104
5eddb70b 3105 I915_WRITE(reg, temp);
6be4a607 3106 }
b52eb4dc 3107
b8a4f404 3108 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3109}
3110
1507e5bd
PZ		 3111static void lpt_pch_enable(struct drm_crtc *crtc)
3112{
3113 struct drm_device *dev = crtc->dev;
3114 struct drm_i915_private *dev_priv = dev->dev_private;
3115 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3116 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3117
daed2dbb 3118 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3119
8c52b5e8 3120 lpt_program_iclkip(crtc);
1507e5bd 3121
0540e488 3122 /* Set transcoder timing. */
daed2dbb
PZ		 3123 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3124 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3125 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3126
daed2dbb
PZ		 3127 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3128 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3129 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3130 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3131
937bb610 3132 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3133}
3134
ee7b9f93
JB		 3135static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3136{
3137 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3138
3139 if (pll == NULL)
3140 return;
3141
3142 if (pll->refcount == 0) {
3143 WARN(1, "bad PCH PLL refcount\n");
3144 return;
3145 }
3146
3147 --pll->refcount;
3148 intel_crtc->pch_pll = NULL;
3149}
3150
3151static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3152{
3153 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3154 struct intel_pch_pll *pll;
3155 int i;
3156
3157 pll = intel_crtc->pch_pll;
3158 if (pll) {
3159 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3160 intel_crtc->base.base.id, pll->pll_reg);
3161 goto prepare;
3162 }
3163
98b6bd99
DV		 3164 if (HAS_PCH_IBX(dev_priv->dev)) {
3165 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3166 i = intel_crtc->pipe;
3167 pll = &dev_priv->pch_plls[i];
3168
3169 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3170 intel_crtc->base.base.id, pll->pll_reg);
3171
3172 goto found;
3173 }
3174
ee7b9f93
JB		 3175 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3176 pll = &dev_priv->pch_plls[i];
3177
3178 /* Only want to check enabled timings first */
3179 if (pll->refcount == 0)
3180 continue;
3181
3182 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3183 fp == I915_READ(pll->fp0_reg)) {
3184 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3185 intel_crtc->base.base.id,
3186 pll->pll_reg, pll->refcount, pll->active);
3187
3188 goto found;
3189 }
3190 }
3191
3192 /* Ok no matching timings, maybe there's a free one? */
3193 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3194 pll = &dev_priv->pch_plls[i];
3195 if (pll->refcount == 0) {
3196 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3197 intel_crtc->base.base.id, pll->pll_reg);
3198 goto found;
3199 }
3200 }
3201
3202 return NULL;
3203
3204found:
3205 intel_crtc->pch_pll = pll;
3206 pll->refcount++;
84f44ce7 3207 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
ee7b9f93
JB		 3208prepare: /* separate function? */
3209 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3210
e04c7350
CW		 3211 /* Wait for the clocks to stabilize before rewriting the regs */
3212 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3213 POSTING_READ(pll->pll_reg);
3214 udelay(150);
e04c7350
CW		 3215
3216 I915_WRITE(pll->fp0_reg, fp);
3217 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3218 pll->on = false;
3219 return pll;
3220}
3221
d4270e57
JB		 3222void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3223{
3224 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3225 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3226 u32 temp;
3227
3228 temp = I915_READ(dslreg);
3229 udelay(500);
3230 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3231 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3232 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3233 }
3234}
3235
b074cec8
JB		 3236static void ironlake_pfit_enable(struct intel_crtc *crtc)
3237{
3238 struct drm_device *dev = crtc->base.dev;
3239 struct drm_i915_private *dev_priv = dev->dev_private;
3240 int pipe = crtc->pipe;
3241
3242 if (crtc->config.pch_pfit.size &&
3243 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) {
3244 /* Force use of hard-coded filter coefficients
3245 * as some pre-programmed values are broken,
3246 * e.g. x201.
3247 */
3248 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3249 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3250 PF_PIPE_SEL_IVB(pipe));
3251 else
3252 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3253 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3254 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3255 }
3256}
3257
f67a559d
JB		 3258static void ironlake_crtc_enable(struct drm_crtc *crtc)
3259{
3260 struct drm_device *dev = crtc->dev;
3261 struct drm_i915_private *dev_priv = dev->dev_private;
3262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3263 struct intel_encoder *encoder;
f67a559d
JB		 3264 int pipe = intel_crtc->pipe;
3265 int plane = intel_crtc->plane;
3266 u32 temp;
f67a559d 3267
08a48469
DV		 3268 WARN_ON(!crtc->enabled);
3269
f67a559d
JB		 3270 if (intel_crtc->active)
3271 return;
3272
3273 intel_crtc->active = true;
8664281b
PZ		 3274
3275 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3276 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3277
f67a559d
JB		 3278 intel_update_watermarks(dev);
3279
3280 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3281 temp = I915_READ(PCH_LVDS);
3282 if ((temp & LVDS_PORT_EN) == 0)
3283 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3284 }
3285
f67a559d 3286
5bfe2ac0 3287 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3288 /* Note: FDI PLL enabling _must_ be done before we enable the
3289 * cpu pipes, hence this is separate from all the other fdi/pch
3290 * enabling. */
88cefb6c 3291 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3292 } else {
3293 assert_fdi_tx_disabled(dev_priv, pipe);
3294 assert_fdi_rx_disabled(dev_priv, pipe);
3295 }
f67a559d 3296
bf49ec8c
DV		 3297 for_each_encoder_on_crtc(dev, crtc, encoder)
3298 if (encoder->pre_enable)
3299 encoder->pre_enable(encoder);
f67a559d
JB		 3300
3301 /* Enable panel fitting for LVDS */
b074cec8 3302 ironlake_pfit_enable(intel_crtc);
f67a559d 3303
9c54c0dd
JB		 3304 /*
3305 * On ILK+ LUT must be loaded before the pipe is running but with
3306 * clocks enabled
3307 */
3308 intel_crtc_load_lut(crtc);
3309
5bfe2ac0
DV		 3310 intel_enable_pipe(dev_priv, pipe,
3311 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3312 intel_enable_plane(dev_priv, plane, pipe);
3313
5bfe2ac0 3314 if (intel_crtc->config.has_pch_encoder)
f67a559d 3315 ironlake_pch_enable(crtc);
c98e9dcf 3316
d1ebd816 3317 mutex_lock(&dev->struct_mutex);
bed4a673 3318 intel_update_fbc(dev);
d1ebd816
BW		 3319 mutex_unlock(&dev->struct_mutex);
3320
6b383a7f 3321 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3322
fa5c73b1
DV		 3323 for_each_encoder_on_crtc(dev, crtc, encoder)
3324 encoder->enable(encoder);
61b77ddd
DV		 3325
3326 if (HAS_PCH_CPT(dev))
3327 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3328
3329 /*
3330 * There seems to be a race in PCH platform hw (at least on some
3331 * outputs) where an enabled pipe still completes any pageflip right
3332 * away (as if the pipe is off) instead of waiting for vblank. As soon
3333 * as the first vblank happend, everything works as expected. Hence just
3334 * wait for one vblank before returning to avoid strange things
3335 * happening.
3336 */
3337 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3338}
3339
4f771f10
PZ		 3340static void haswell_crtc_enable(struct drm_crtc *crtc)
3341{
3342 struct drm_device *dev = crtc->dev;
3343 struct drm_i915_private *dev_priv = dev->dev_private;
3344 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3345 struct intel_encoder *encoder;
3346 int pipe = intel_crtc->pipe;
3347 int plane = intel_crtc->plane;
4f771f10
PZ		 3348
3349 WARN_ON(!crtc->enabled);
3350
3351 if (intel_crtc->active)
3352 return;
3353
3354 intel_crtc->active = true;
8664281b
PZ		 3355
3356 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3357 if (intel_crtc->config.has_pch_encoder)
3358 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3359
4f771f10
PZ		 3360 intel_update_watermarks(dev);
3361
5bfe2ac0 3362 if (intel_crtc->config.has_pch_encoder)
04945641 3363 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3364
3365 for_each_encoder_on_crtc(dev, crtc, encoder)
3366 if (encoder->pre_enable)
3367 encoder->pre_enable(encoder);
3368
1f544388 3369 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3370
1f544388 3371 /* Enable panel fitting for eDP */
b074cec8 3372 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3373
3374 /*
3375 * On ILK+ LUT must be loaded before the pipe is running but with
3376 * clocks enabled
3377 */
3378 intel_crtc_load_lut(crtc);
3379
1f544388 3380 intel_ddi_set_pipe_settings(crtc);
8228c251 3381 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3382
5bfe2ac0
DV		 3383 intel_enable_pipe(dev_priv, pipe,
3384 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3385 intel_enable_plane(dev_priv, plane, pipe);
3386
5bfe2ac0 3387 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3388 lpt_pch_enable(crtc);
4f771f10
PZ		 3389
3390 mutex_lock(&dev->struct_mutex);
3391 intel_update_fbc(dev);
3392 mutex_unlock(&dev->struct_mutex);
3393
3394 intel_crtc_update_cursor(crtc, true);
3395
3396 for_each_encoder_on_crtc(dev, crtc, encoder)
3397 encoder->enable(encoder);
3398
4f771f10
PZ		 3399 /*
3400 * There seems to be a race in PCH platform hw (at least on some
3401 * outputs) where an enabled pipe still completes any pageflip right
3402 * away (as if the pipe is off) instead of waiting for vblank. As soon
3403 * as the first vblank happend, everything works as expected. Hence just
3404 * wait for one vblank before returning to avoid strange things
3405 * happening.
3406 */
3407 intel_wait_for_vblank(dev, intel_crtc->pipe);
3408}
3409
6be4a607
JB		 3410static void ironlake_crtc_disable(struct drm_crtc *crtc)
3411{
3412 struct drm_device *dev = crtc->dev;
3413 struct drm_i915_private *dev_priv = dev->dev_private;
3414 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3415 struct intel_encoder *encoder;
6be4a607
JB		 3416 int pipe = intel_crtc->pipe;
3417 int plane = intel_crtc->plane;
5eddb70b 3418 u32 reg, temp;
b52eb4dc 3419
ef9c3aee 3420
f7abfe8b
CW		 3421 if (!intel_crtc->active)
3422 return;
3423
ea9d758d
DV		 3424 for_each_encoder_on_crtc(dev, crtc, encoder)
3425 encoder->disable(encoder);
3426
e6c3a2a6 3427 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3428 drm_vblank_off(dev, pipe);
6b383a7f 3429 intel_crtc_update_cursor(crtc, false);
5eddb70b 3430
b24e7179 3431 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3432
973d04f9
CW		 3433 if (dev_priv->cfb_plane == plane)
3434 intel_disable_fbc(dev);
2c07245f 3435
8664281b 3436 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
b24e7179 3437 intel_disable_pipe(dev_priv, pipe);
32f9d658 3438
6be4a607 3439 /* Disable PF */
9db4a9c7
JB		 3440 I915_WRITE(PF_CTL(pipe), 0);
3441 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3442
bf49ec8c
DV		 3443 for_each_encoder_on_crtc(dev, crtc, encoder)
3444 if (encoder->post_disable)
3445 encoder->post_disable(encoder);
2c07245f 3446
0fc932b8 3447 ironlake_fdi_disable(crtc);
249c0e64 3448
b8a4f404 3449 ironlake_disable_pch_transcoder(dev_priv, pipe);
8664281b 3450 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3451
6be4a607
JB		 3452 if (HAS_PCH_CPT(dev)) {
3453 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3454 reg = TRANS_DP_CTL(pipe);
3455 temp = I915_READ(reg);
3456 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3457 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3458 I915_WRITE(reg, temp);
6be4a607
JB		 3459
3460 /* disable DPLL_SEL */
3461 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3462 switch (pipe) {
3463 case 0:
d64311ab 3464 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3465 break;
3466 case 1:
6be4a607 3467 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3468 break;
3469 case 2:
4b645f14 3470 /* C shares PLL A or B */
d64311ab 3471 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3472 break;
3473 default:
3474 BUG(); /* wtf */
3475 }
6be4a607 3476 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3477 }
e3421a18 3478
6be4a607 3479 /* disable PCH DPLL */
ee7b9f93 3480 intel_disable_pch_pll(intel_crtc);
8db9d77b 3481
88cefb6c 3482 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3483
f7abfe8b 3484 intel_crtc->active = false;
6b383a7f 3485 intel_update_watermarks(dev);
d1ebd816
BW		 3486
3487 mutex_lock(&dev->struct_mutex);
6b383a7f 3488 intel_update_fbc(dev);
d1ebd816 3489 mutex_unlock(&dev->struct_mutex);
6be4a607 3490}
1b3c7a47 3491
4f771f10 3492static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3493{
4f771f10
PZ		 3494 struct drm_device *dev = crtc->dev;
3495 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3497 struct intel_encoder *encoder;
3498 int pipe = intel_crtc->pipe;
3499 int plane = intel_crtc->plane;
3b117c8f 3500 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3501
4f771f10
PZ		 3502 if (!intel_crtc->active)
3503 return;
3504
3505 for_each_encoder_on_crtc(dev, crtc, encoder)
3506 encoder->disable(encoder);
3507
3508 intel_crtc_wait_for_pending_flips(crtc);
3509 drm_vblank_off(dev, pipe);
3510 intel_crtc_update_cursor(crtc, false);
3511
3512 intel_disable_plane(dev_priv, plane, pipe);
3513
3514 if (dev_priv->cfb_plane == plane)
3515 intel_disable_fbc(dev);
3516
8664281b
PZ		 3517 if (intel_crtc->config.has_pch_encoder)
3518 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3519 intel_disable_pipe(dev_priv, pipe);
3520
ad80a810 3521 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3522
f7708f78
PZ		 3523 /* XXX: Once we have proper panel fitter state tracking implemented with
3524 * hardware state read/check support we should switch to only disable
3525 * the panel fitter when we know it's used. */
3526 if (intel_using_power_well(dev)) {
3527 I915_WRITE(PF_CTL(pipe), 0);
3528 I915_WRITE(PF_WIN_SZ(pipe), 0);
3529 }
4f771f10 3530
1f544388 3531 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3532
3533 for_each_encoder_on_crtc(dev, crtc, encoder)
3534 if (encoder->post_disable)
3535 encoder->post_disable(encoder);
3536
88adfff1 3537 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3538 lpt_disable_pch_transcoder(dev_priv);
8664281b 3539 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3540 intel_ddi_fdi_disable(crtc);
83616634 3541 }
4f771f10
PZ		 3542
3543 intel_crtc->active = false;
3544 intel_update_watermarks(dev);
3545
3546 mutex_lock(&dev->struct_mutex);
3547 intel_update_fbc(dev);
3548 mutex_unlock(&dev->struct_mutex);
3549}
3550
ee7b9f93
JB		 3551static void ironlake_crtc_off(struct drm_crtc *crtc)
3552{
3553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3554 intel_put_pch_pll(intel_crtc);
3555}
3556
6441ab5f
PZ		 3557static void haswell_crtc_off(struct drm_crtc *crtc)
3558{
a5c961d1
PZ		 3559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3560
3561 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3562 * start using it. */
3b117c8f 3563 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3564
6441ab5f
PZ		 3565 intel_ddi_put_crtc_pll(crtc);
3566}
3567
02e792fb
DV		 3568static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3569{
02e792fb 3570 if (!enable && intel_crtc->overlay) {
23f09ce3 3571 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3572 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3573
23f09ce3 3574 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3575 dev_priv->mm.interruptible = false;
3576 (void) intel_overlay_switch_off(intel_crtc->overlay);
3577 dev_priv->mm.interruptible = true;
23f09ce3 3578 mutex_unlock(&dev->struct_mutex);
02e792fb 3579 }
02e792fb 3580
5dcdbcb0
CW		 3581 /* Let userspace switch the overlay on again. In most cases userspace
3582 * has to recompute where to put it anyway.
3583 */
02e792fb
DV		 3584}
3585
61bc95c1
EE		 3586/**
3587 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3588 * cursor plane briefly if not already running after enabling the display
3589 * plane.
3590 * This workaround avoids occasional blank screens when self refresh is
3591 * enabled.
3592 */
3593static void
3594g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3595{
3596 u32 cntl = I915_READ(CURCNTR(pipe));
3597
3598 if ((cntl & CURSOR_MODE) == 0) {
3599 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3600
3601 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3602 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3603 intel_wait_for_vblank(dev_priv->dev, pipe);
3604 I915_WRITE(CURCNTR(pipe), cntl);
3605 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3606 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3607 }
3608}
3609
2dd24552
JB		 3610static void i9xx_pfit_enable(struct intel_crtc *crtc)
3611{
3612 struct drm_device *dev = crtc->base.dev;
3613 struct drm_i915_private *dev_priv = dev->dev_private;
3614 struct intel_crtc_config *pipe_config = &crtc->config;
3615
3616 if (!(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
3617 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)))
3618 return;
3619
3620 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3621 assert_pipe_disabled(dev_priv, crtc->pipe);
3622
3623 /*
3624 * Enable automatic panel scaling so that non-native modes
3625 * fill the screen. The panel fitter should only be
3626 * adjusted whilst the pipe is disabled, according to
3627 * register description and PRM.
3628 */
3629 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
b074cec8
JB		 3630 pipe_config->gmch_pfit.control,
3631 pipe_config->gmch_pfit.pgm_ratios);
2dd24552 3632
b074cec8
JB		 3633 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3634 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3635
3636 /* Border color in case we don't scale up to the full screen. Black by
3637 * default, change to something else for debugging. */
3638 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3639}
3640
89b667f8
JB		 3641static void valleyview_crtc_enable(struct drm_crtc *crtc)
3642{
3643 struct drm_device *dev = crtc->dev;
3644 struct drm_i915_private *dev_priv = dev->dev_private;
3645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3646 struct intel_encoder *encoder;
3647 int pipe = intel_crtc->pipe;
3648 int plane = intel_crtc->plane;
3649
3650 WARN_ON(!crtc->enabled);
3651
3652 if (intel_crtc->active)
3653 return;
3654
3655 intel_crtc->active = true;
3656 intel_update_watermarks(dev);
3657
3658 mutex_lock(&dev_priv->dpio_lock);
3659
3660 for_each_encoder_on_crtc(dev, crtc, encoder)
3661 if (encoder->pre_pll_enable)
3662 encoder->pre_pll_enable(encoder);
3663
3664 intel_enable_pll(dev_priv, pipe);
3665
3666 for_each_encoder_on_crtc(dev, crtc, encoder)
3667 if (encoder->pre_enable)
3668 encoder->pre_enable(encoder);
3669
3670 /* VLV wants encoder enabling _before_ the pipe is up. */
3671 for_each_encoder_on_crtc(dev, crtc, encoder)
3672 encoder->enable(encoder);
3673
2dd24552
JB		 3674 /* Enable panel fitting for eDP */
3675 i9xx_pfit_enable(intel_crtc);
3676
89b667f8
JB		 3677 intel_enable_pipe(dev_priv, pipe, false);
3678 intel_enable_plane(dev_priv, plane, pipe);
3679
3680 intel_crtc_load_lut(crtc);
3681 intel_update_fbc(dev);
3682
3683 /* Give the overlay scaler a chance to enable if it's on this pipe */
3684 intel_crtc_dpms_overlay(intel_crtc, true);
3685 intel_crtc_update_cursor(crtc, true);
3686
3687 mutex_unlock(&dev_priv->dpio_lock);
3688}
3689
0b8765c6 3690static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3691{
3692 struct drm_device *dev = crtc->dev;
79e53945
JB		 3693 struct drm_i915_private *dev_priv = dev->dev_private;
3694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3695 struct intel_encoder *encoder;
79e53945 3696 int pipe = intel_crtc->pipe;
80824003 3697 int plane = intel_crtc->plane;
79e53945 3698
08a48469
DV		 3699 WARN_ON(!crtc->enabled);
3700
f7abfe8b
CW		 3701 if (intel_crtc->active)
3702 return;
3703
3704 intel_crtc->active = true;
6b383a7f
CW		 3705 intel_update_watermarks(dev);
3706
63d7bbe9 3707 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3708
3709 for_each_encoder_on_crtc(dev, crtc, encoder)
3710 if (encoder->pre_enable)
3711 encoder->pre_enable(encoder);
3712
2dd24552
JB		 3713 /* Enable panel fitting for LVDS */
3714 i9xx_pfit_enable(intel_crtc);
3715
040484af 3716 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3717 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3718 if (IS_G4X(dev))
3719 g4x_fixup_plane(dev_priv, pipe);
79e53945 3720
0b8765c6 3721 intel_crtc_load_lut(crtc);
bed4a673 3722 intel_update_fbc(dev);
79e53945 3723
0b8765c6
JB		 3724 /* Give the overlay scaler a chance to enable if it's on this pipe */
3725 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3726 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3727
fa5c73b1
DV		 3728 for_each_encoder_on_crtc(dev, crtc, encoder)
3729 encoder->enable(encoder);
0b8765c6 3730}
79e53945 3731
87476d63
DV		 3732static void i9xx_pfit_disable(struct intel_crtc *crtc)
3733{
3734 struct drm_device *dev = crtc->base.dev;
3735 struct drm_i915_private *dev_priv = dev->dev_private;
3736 enum pipe pipe;
3737 uint32_t pctl = I915_READ(PFIT_CONTROL);
3738
3739 assert_pipe_disabled(dev_priv, crtc->pipe);
3740
3741 if (INTEL_INFO(dev)->gen >= 4)
3742 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3743 else
3744 pipe = PIPE_B;
3745
3746 if (pipe == crtc->pipe) {
3747 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3748 I915_WRITE(PFIT_CONTROL, 0);
3749 }
3750}
3751
0b8765c6
JB		 3752static void i9xx_crtc_disable(struct drm_crtc *crtc)
3753{
3754 struct drm_device *dev = crtc->dev;
3755 struct drm_i915_private *dev_priv = dev->dev_private;
3756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3757 struct intel_encoder *encoder;
0b8765c6
JB		 3758 int pipe = intel_crtc->pipe;
3759 int plane = intel_crtc->plane;
ef9c3aee 3760
f7abfe8b
CW		 3761 if (!intel_crtc->active)
3762 return;
3763
ea9d758d
DV		 3764 for_each_encoder_on_crtc(dev, crtc, encoder)
3765 encoder->disable(encoder);
3766
0b8765c6 3767 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3768 intel_crtc_wait_for_pending_flips(crtc);
3769 drm_vblank_off(dev, pipe);
0b8765c6 3770 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3771 intel_crtc_update_cursor(crtc, false);
0b8765c6 3772
973d04f9
CW		 3773 if (dev_priv->cfb_plane == plane)
3774 intel_disable_fbc(dev);
79e53945 3775
b24e7179 3776 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3777 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3778
87476d63 3779 i9xx_pfit_disable(intel_crtc);
24a1f16d 3780
89b667f8
JB		 3781 for_each_encoder_on_crtc(dev, crtc, encoder)
3782 if (encoder->post_disable)
3783 encoder->post_disable(encoder);
3784
63d7bbe9 3785 intel_disable_pll(dev_priv, pipe);
0b8765c6 3786
f7abfe8b 3787 intel_crtc->active = false;
6b383a7f
CW		 3788 intel_update_fbc(dev);
3789 intel_update_watermarks(dev);
0b8765c6
JB		 3790}
3791
ee7b9f93
JB		 3792static void i9xx_crtc_off(struct drm_crtc *crtc)
3793{
3794}
3795
976f8a20
DV		 3796static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3797 bool enabled)
2c07245f
ZW		 3798{
3799 struct drm_device *dev = crtc->dev;
3800 struct drm_i915_master_private *master_priv;
3801 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3802 int pipe = intel_crtc->pipe;
79e53945
JB		 3803
3804 if (!dev->primary->master)
3805 return;
3806
3807 master_priv = dev->primary->master->driver_priv;
3808 if (!master_priv->sarea_priv)
3809 return;
3810
79e53945
JB		 3811 switch (pipe) {
3812 case 0:
3813 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3814 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3815 break;
3816 case 1:
3817 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3818 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3819 break;
3820 default:
9db4a9c7 3821 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3822 break;
3823 }
79e53945
JB		 3824}
3825
976f8a20
DV		 3826/**
3827 * Sets the power management mode of the pipe and plane.
3828 */
3829void intel_crtc_update_dpms(struct drm_crtc *crtc)
3830{
3831 struct drm_device *dev = crtc->dev;
3832 struct drm_i915_private *dev_priv = dev->dev_private;
3833 struct intel_encoder *intel_encoder;
3834 bool enable = false;
3835
3836 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3837 enable |= intel_encoder->connectors_active;
3838
3839 if (enable)
3840 dev_priv->display.crtc_enable(crtc);
3841 else
3842 dev_priv->display.crtc_disable(crtc);
3843
3844 intel_crtc_update_sarea(crtc, enable);
3845}
3846
cdd59983
CW		 3847static void intel_crtc_disable(struct drm_crtc *crtc)
3848{
cdd59983 3849 struct drm_device *dev = crtc->dev;
976f8a20 3850 struct drm_connector *connector;
ee7b9f93 3851 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3852 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3853
976f8a20
DV		 3854 /* crtc should still be enabled when we disable it. */
3855 WARN_ON(!crtc->enabled);
3856
7b9f35a6 3857 intel_crtc->eld_vld = false;
976f8a20
DV		 3858 dev_priv->display.crtc_disable(crtc);
3859 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3860 dev_priv->display.off(crtc);
3861
931872fc
CW		 3862 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3863 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3864
3865 if (crtc->fb) {
3866 mutex_lock(&dev->struct_mutex);
1690e1eb 3867 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3868 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3869 crtc->fb = NULL;
3870 }
3871
3872 /* Update computed state. */
3873 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3874 if (!connector->encoder || !connector->encoder->crtc)
3875 continue;
3876
3877 if (connector->encoder->crtc != crtc)
3878 continue;
3879
3880 connector->dpms = DRM_MODE_DPMS_OFF;
3881 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3882 }
3883}
3884
a261b246 3885void intel_modeset_disable(struct drm_device *dev)
79e53945 3886{
a261b246
DV		 3887 struct drm_crtc *crtc;
3888
3889 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3890 if (crtc->enabled)
3891 intel_crtc_disable(crtc);
3892 }
79e53945
JB		 3893}
3894
ea5b213a 3895void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3896{
4ef69c7a 3897 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3898
ea5b213a
CW		 3899 drm_encoder_cleanup(encoder);
3900 kfree(intel_encoder);
7e7d76c3
JB		 3901}
3902
5ab432ef
DV		 3903/* Simple dpms helper for encodres with just one connector, no cloning and only
3904 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3905 * state of the entire output pipe. */
3906void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3907{
5ab432ef
DV		 3908 if (mode == DRM_MODE_DPMS_ON) {
3909 encoder->connectors_active = true;
3910
b2cabb0e 3911 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3912 } else {
3913 encoder->connectors_active = false;
3914
b2cabb0e 3915 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3916 }
79e53945
JB		 3917}
3918
0a91ca29
DV		 3919/* Cross check the actual hw state with our own modeset state tracking (and it's
3920 * internal consistency). */
b980514c 3921static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3922{
0a91ca29
DV		 3923 if (connector->get_hw_state(connector)) {
3924 struct intel_encoder *encoder = connector->encoder;
3925 struct drm_crtc *crtc;
3926 bool encoder_enabled;
3927 enum pipe pipe;
3928
3929 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3930 connector->base.base.id,
3931 drm_get_connector_name(&connector->base));
3932
3933 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3934 "wrong connector dpms state\n");
3935 WARN(connector->base.encoder != &encoder->base,
3936 "active connector not linked to encoder\n");
3937 WARN(!encoder->connectors_active,
3938 "encoder->connectors_active not set\n");
3939
3940 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3941 WARN(!encoder_enabled, "encoder not enabled\n");
3942 if (WARN_ON(!encoder->base.crtc))
3943 return;
3944
3945 crtc = encoder->base.crtc;
3946
3947 WARN(!crtc->enabled, "crtc not enabled\n");
3948 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3949 WARN(pipe != to_intel_crtc(crtc)->pipe,
3950 "encoder active on the wrong pipe\n");
3951 }
79e53945
JB		 3952}
3953
5ab432ef
DV		 3954/* Even simpler default implementation, if there's really no special case to
3955 * consider. */
3956void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3957{
5ab432ef 3958 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3959
5ab432ef
DV		 3960 /* All the simple cases only support two dpms states. */
3961 if (mode != DRM_MODE_DPMS_ON)
3962 mode = DRM_MODE_DPMS_OFF;
d4270e57 3963
5ab432ef
DV		 3964 if (mode == connector->dpms)
3965 return;
3966
3967 connector->dpms = mode;
3968
3969 /* Only need to change hw state when actually enabled */
3970 if (encoder->base.crtc)
3971 intel_encoder_dpms(encoder, mode);
3972 else
8af6cf88 3973 WARN_ON(encoder->connectors_active != false);
0a91ca29 3974
b980514c 3975 intel_modeset_check_state(connector->dev);
79e53945
JB		 3976}
3977
f0947c37
DV		 3978/* Simple connector->get_hw_state implementation for encoders that support only
3979 * one connector and no cloning and hence the encoder state determines the state
3980 * of the connector. */
3981bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3982{
24929352 3983 enum pipe pipe = 0;
f0947c37 3984 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3985
f0947c37 3986 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3987}
3988
1857e1da
DV		 3989static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3990 struct intel_crtc_config *pipe_config)
3991{
3992 struct drm_i915_private *dev_priv = dev->dev_private;
3993 struct intel_crtc *pipe_B_crtc =
3994 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3995
3996 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3997 pipe_name(pipe), pipe_config->fdi_lanes);
3998 if (pipe_config->fdi_lanes > 4) {
3999 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4000 pipe_name(pipe), pipe_config->fdi_lanes);
4001 return false;
4002 }
4003
4004 if (IS_HASWELL(dev)) {
4005 if (pipe_config->fdi_lanes > 2) {
4006 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4007 pipe_config->fdi_lanes);
4008 return false;
4009 } else {
4010 return true;
4011 }
4012 }
4013
4014 if (INTEL_INFO(dev)->num_pipes == 2)
4015 return true;
4016
4017 /* Ivybridge 3 pipe is really complicated */
4018 switch (pipe) {
4019 case PIPE_A:
4020 return true;
4021 case PIPE_B:
4022 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4023 pipe_config->fdi_lanes > 2) {
4024 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4025 pipe_name(pipe), pipe_config->fdi_lanes);
4026 return false;
4027 }
4028 return true;
4029 case PIPE_C:
1e833f40 4030 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4031 pipe_B_crtc->config.fdi_lanes <= 2) {
4032 if (pipe_config->fdi_lanes > 2) {
4033 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4034 pipe_name(pipe), pipe_config->fdi_lanes);
4035 return false;
4036 }
4037 } else {
4038 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4039 return false;
4040 }
4041 return true;
4042 default:
4043 BUG();
4044 }
4045}
4046
e29c22c0
DV		 4047#define RETRY 1
4048static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4049 struct intel_crtc_config *pipe_config)
877d48d5 4050{
1857e1da 4051 struct drm_device *dev = intel_crtc->base.dev;
877d48d5
DV		 4052 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
4053 int target_clock, lane, link_bw;
e29c22c0 4054 bool setup_ok, needs_recompute = false;
877d48d5 4055
e29c22c0 4056retry:
877d48d5
DV		 4057 /* FDI is a binary signal running at ~2.7GHz, encoding
4058 * each output octet as 10 bits. The actual frequency
4059 * is stored as a divider into a 100MHz clock, and the
4060 * mode pixel clock is stored in units of 1KHz.
4061 * Hence the bw of each lane in terms of the mode signal
4062 * is:
4063 */
4064 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4065
4066 if (pipe_config->pixel_target_clock)
4067 target_clock = pipe_config->pixel_target_clock;
4068 else
4069 target_clock = adjusted_mode->clock;
4070
4071 lane = ironlake_get_lanes_required(target_clock, link_bw,
4072 pipe_config->pipe_bpp);
4073
4074 pipe_config->fdi_lanes = lane;
4075
4076 if (pipe_config->pixel_multiplier > 1)
4077 link_bw *= pipe_config->pixel_multiplier;
4078 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock,
4079 link_bw, &pipe_config->fdi_m_n);
1857e1da 4080
e29c22c0
DV		 4081 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4082 intel_crtc->pipe, pipe_config);
4083 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4084 pipe_config->pipe_bpp -= 2*3;
4085 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4086 pipe_config->pipe_bpp);
4087 needs_recompute = true;
4088 pipe_config->bw_constrained = true;
4089
4090 goto retry;
4091 }
4092
4093 if (needs_recompute)
4094 return RETRY;
4095
4096 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4097}
4098
e29c22c0
DV		 4099static int intel_crtc_compute_config(struct drm_crtc *crtc,
4100 struct intel_crtc_config *pipe_config)
79e53945 4101{
2c07245f 4102 struct drm_device *dev = crtc->dev;
b8cecdf5 4103 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4104
bad720ff 4105 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4106 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4107 if (pipe_config->requested_mode.clock * 3
4108 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4109 return -EINVAL;
2c07245f 4110 }
89749350 4111
f9bef081
DV		 4112 /* All interlaced capable intel hw wants timings in frames. Note though
4113 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4114 * timings, so we need to be careful not to clobber these.*/
7ae89233 4115 if (!pipe_config->timings_set)
f9bef081 4116 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4117
44f46b42
CW		 4118 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
4119 * with a hsync front porch of 0.
4120 */
4121 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4122 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4123 return -EINVAL;
44f46b42 4124
bd080ee5 4125 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4126 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4127 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4128 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4129 * for lvds. */
4130 pipe_config->pipe_bpp = 8*3;
4131 }
4132
877d48d5 4133 if (pipe_config->has_pch_encoder)
1857e1da 4134 return ironlake_fdi_compute_config(to_intel_crtc(crtc), pipe_config);
877d48d5 4135
e29c22c0 4136 return 0;
79e53945
JB		 4137}
4138
25eb05fc
JB		 4139static int valleyview_get_display_clock_speed(struct drm_device *dev)
4140{
4141 return 400000; /* FIXME */
4142}
4143
e70236a8
JB		 4144static int i945_get_display_clock_speed(struct drm_device *dev)
4145{
4146 return 400000;
4147}
79e53945 4148
e70236a8 4149static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4150{
e70236a8
JB		 4151 return 333000;
4152}
79e53945 4153
e70236a8
JB		 4154static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4155{
4156 return 200000;
4157}
79e53945 4158
e70236a8
JB		 4159static int i915gm_get_display_clock_speed(struct drm_device *dev)
4160{
4161 u16 gcfgc = 0;
79e53945 4162
e70236a8
JB		 4163 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4164
4165 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4166 return 133000;
4167 else {
4168 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4169 case GC_DISPLAY_CLOCK_333_MHZ:
4170 return 333000;
4171 default:
4172 case GC_DISPLAY_CLOCK_190_200_MHZ:
4173 return 190000;
79e53945 4174 }
e70236a8
JB		 4175 }
4176}
4177
4178static int i865_get_display_clock_speed(struct drm_device *dev)
4179{
4180 return 266000;
4181}
4182
4183static int i855_get_display_clock_speed(struct drm_device *dev)
4184{
4185 u16 hpllcc = 0;
4186 /* Assume that the hardware is in the high speed state. This
4187 * should be the default.
4188 */
4189 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4190 case GC_CLOCK_133_200:
4191 case GC_CLOCK_100_200:
4192 return 200000;
4193 case GC_CLOCK_166_250:
4194 return 250000;
4195 case GC_CLOCK_100_133:
79e53945 4196 return 133000;
e70236a8 4197 }
79e53945 4198
e70236a8
JB		 4199 /* Shouldn't happen */
4200 return 0;
4201}
79e53945 4202
e70236a8
JB		 4203static int i830_get_display_clock_speed(struct drm_device *dev)
4204{
4205 return 133000;
79e53945
JB		 4206}
4207
2c07245f 4208static void
e69d0bc1 4209intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 4210{
4211 while (*num > 0xffffff || *den > 0xffffff) {
4212 *num >>= 1;
4213 *den >>= 1;
4214 }
4215}
4216
e69d0bc1
DV		 4217void
4218intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4219 int pixel_clock, int link_clock,
4220 struct intel_link_m_n *m_n)
2c07245f 4221{
e69d0bc1 4222 m_n->tu = 64;
22ed1113
CW		 4223 m_n->gmch_m = bits_per_pixel * pixel_clock;
4224 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4225 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4226 m_n->link_m = pixel_clock;
4227 m_n->link_n = link_clock;
e69d0bc1 4228 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4229}
4230
a7615030
CW		 4231static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4232{
72bbe58c
KP		 4233 if (i915_panel_use_ssc >= 0)
4234 return i915_panel_use_ssc != 0;
4235 return dev_priv->lvds_use_ssc
435793df 4236 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4237}
4238
a0c4da24
JB		 4239static int vlv_get_refclk(struct drm_crtc *crtc)
4240{
4241 struct drm_device *dev = crtc->dev;
4242 struct drm_i915_private *dev_priv = dev->dev_private;
4243 int refclk = 27000; /* for DP & HDMI */
4244
4245 return 100000; /* only one validated so far */
4246
4247 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4248 refclk = 96000;
4249 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4250 if (intel_panel_use_ssc(dev_priv))
4251 refclk = 100000;
4252 else
4253 refclk = 96000;
4254 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4255 refclk = 100000;
4256 }
4257
4258 return refclk;
4259}
4260
c65d77d8
JB		 4261static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4262{
4263 struct drm_device *dev = crtc->dev;
4264 struct drm_i915_private *dev_priv = dev->dev_private;
4265 int refclk;
4266
a0c4da24
JB		 4267 if (IS_VALLEYVIEW(dev)) {
4268 refclk = vlv_get_refclk(crtc);
4269 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4270 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4271 refclk = dev_priv->lvds_ssc_freq * 1000;
4272 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4273 refclk / 1000);
4274 } else if (!IS_GEN2(dev)) {
4275 refclk = 96000;
4276 } else {
4277 refclk = 48000;
4278 }
4279
4280 return refclk;
4281}
4282
f47709a9 4283static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
c65d77d8 4284{
f47709a9
DV		 4285 unsigned dotclock = crtc->config.adjusted_mode.clock;
4286 struct dpll *clock = &crtc->config.dpll;
4287
c65d77d8
JB		 4288 /* SDVO TV has fixed PLL values depend on its clock range,
4289 this mirrors vbios setting. */
f47709a9 4290 if (dotclock >= 100000 && dotclock < 140500) {
c65d77d8
JB		 4291 clock->p1 = 2;
4292 clock->p2 = 10;
4293 clock->n = 3;
4294 clock->m1 = 16;
4295 clock->m2 = 8;
f47709a9 4296 } else if (dotclock >= 140500 && dotclock <= 200000) {
c65d77d8
JB		 4297 clock->p1 = 1;
4298 clock->p2 = 10;
4299 clock->n = 6;
4300 clock->m1 = 12;
4301 clock->m2 = 8;
4302 }
f47709a9
DV		 4303
4304 crtc->config.clock_set = true;
c65d77d8
JB		 4305}
4306
7429e9d4
DV		 4307static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4308{
4309 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4310}
4311
4312static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4313{
4314 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4315}
4316
f47709a9 4317static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4318 intel_clock_t *reduced_clock)
4319{
f47709a9 4320 struct drm_device *dev = crtc->base.dev;
a7516a05 4321 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4322 int pipe = crtc->pipe;
a7516a05
JB		 4323 u32 fp, fp2 = 0;
4324
4325 if (IS_PINEVIEW(dev)) {
7429e9d4 4326 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4327 if (reduced_clock)
7429e9d4 4328 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4329 } else {
7429e9d4 4330 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4331 if (reduced_clock)
7429e9d4 4332 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4333 }
4334
4335 I915_WRITE(FP0(pipe), fp);
4336
f47709a9
DV		 4337 crtc->lowfreq_avail = false;
4338 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4339 reduced_clock && i915_powersave) {
4340 I915_WRITE(FP1(pipe), fp2);
f47709a9 4341 crtc->lowfreq_avail = true;
a7516a05
JB		 4342 } else {
4343 I915_WRITE(FP1(pipe), fp);
4344 }
4345}
4346
89b667f8
JB		 4347static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4348{
4349 u32 reg_val;
4350
4351 /*
4352 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4353 * and set it to a reasonable value instead.
4354 */
4355 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4356 reg_val &= 0xffffff00;
4357 reg_val |= 0x00000030;
4358 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4359
4360 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4361 reg_val &= 0x8cffffff;
4362 reg_val = 0x8c000000;
4363 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4364
4365 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4366 reg_val &= 0xffffff00;
4367 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4368
4369 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4370 reg_val &= 0x00ffffff;
4371 reg_val |= 0xb0000000;
4372 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4373}
4374
03afc4a2
DV		 4375static void intel_dp_set_m_n(struct intel_crtc *crtc)
4376{
4377 if (crtc->config.has_pch_encoder)
4378 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4379 else
4380 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4381}
4382
f47709a9 4383static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4384{
f47709a9 4385 struct drm_device *dev = crtc->base.dev;
a0c4da24 4386 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8
JB		 4387 struct drm_display_mode *adjusted_mode =
4388 &crtc->config.adjusted_mode;
4389 struct intel_encoder *encoder;
f47709a9 4390 int pipe = crtc->pipe;
89b667f8 4391 u32 dpll, mdiv;
a0c4da24 4392 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4393 bool is_hdmi;
198a037f 4394 u32 coreclk, reg_val, dpll_md;
a0c4da24 4395
09153000
DV		 4396 mutex_lock(&dev_priv->dpio_lock);
4397
89b667f8 4398 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4399
f47709a9
DV		 4400 bestn = crtc->config.dpll.n;
4401 bestm1 = crtc->config.dpll.m1;
4402 bestm2 = crtc->config.dpll.m2;
4403 bestp1 = crtc->config.dpll.p1;
4404 bestp2 = crtc->config.dpll.p2;
a0c4da24 4405
89b667f8
JB		 4406 /* See eDP HDMI DPIO driver vbios notes doc */
4407
4408 /* PLL B needs special handling */
4409 if (pipe)
4410 vlv_pllb_recal_opamp(dev_priv);
4411
4412 /* Set up Tx target for periodic Rcomp update */
4413 intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4414
4415 /* Disable target IRef on PLL */
4416 reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4417 reg_val &= 0x00ffffff;
4418 intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4419
4420 /* Disable fast lock */
4421 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4422
4423 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4424 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4425 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4426 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4427 mdiv |= (1 << DPIO_K_SHIFT);
89b667f8
JB		 4428 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI) ||
4429 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4430 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4431 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
a0c4da24
JB		 4432 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4433
89b667f8
JB		 4434 mdiv |= DPIO_ENABLE_CALIBRATION;
4435 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4436
89b667f8
JB		 4437 /* Set HBR and RBR LPF coefficients */
4438 if (adjusted_mode->clock == 162000 ||
4439 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4440 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4441 0x005f0021);
4442 else
4443 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4444 0x00d0000f);
4445
4446 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4447 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4448 /* Use SSC source */
4449 if (!pipe)
4450 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4451 0x0df40000);
4452 else
4453 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4454 0x0df70000);
4455 } else { /* HDMI or VGA */
4456 /* Use bend source */
4457 if (!pipe)
4458 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4459 0x0df70000);
4460 else
4461 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4462 0x0df40000);
4463 }
a0c4da24 4464
89b667f8
JB		 4465 coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4466 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4467 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4468 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4469 coreclk |= 0x01000000;
4470 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4471
89b667f8 4472 intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4473
89b667f8
JB		 4474 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4475 if (encoder->pre_pll_enable)
4476 encoder->pre_pll_enable(encoder);
2a8f64ca 4477
89b667f8
JB		 4478 /* Enable DPIO clock input */
4479 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4480 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4481 if (pipe)
4482 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4483
89b667f8 4484 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4485 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4486 POSTING_READ(DPLL(pipe));
4487 udelay(150);
a0c4da24 4488
89b667f8
JB		 4489 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4490 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4491
198a037f
DV		 4492 dpll_md = 0;
4493 if (crtc->config.pixel_multiplier > 1) {
4494 dpll_md = (crtc->config.pixel_multiplier - 1)
4495 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
2a8f64ca 4496 }
198a037f
DV		 4497 I915_WRITE(DPLL_MD(pipe), dpll_md);
4498 POSTING_READ(DPLL_MD(pipe));
f47709a9 4499
89b667f8
JB		 4500 if (crtc->config.has_dp_encoder)
4501 intel_dp_set_m_n(crtc);
09153000
DV		 4502
4503 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4504}
4505
f47709a9
DV		 4506static void i9xx_update_pll(struct intel_crtc *crtc,
4507 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4508 int num_connectors)
4509{
f47709a9 4510 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4511 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4512 struct intel_encoder *encoder;
f47709a9 4513 int pipe = crtc->pipe;
eb1cbe48
DV		 4514 u32 dpll;
4515 bool is_sdvo;
f47709a9 4516 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4517
f47709a9 4518 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4519
f47709a9
DV		 4520 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4521 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4522
4523 dpll = DPLL_VGA_MODE_DIS;
4524
f47709a9 4525 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4526 dpll |= DPLLB_MODE_LVDS;
4527 else
4528 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4529
198a037f
DV		 4530 if ((crtc->config.pixel_multiplier > 1) &&
4531 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4532 dpll |= (crtc->config.pixel_multiplier - 1)
4533 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4534 }
198a037f
DV		 4535
4536 if (is_sdvo)
4537 dpll |= DPLL_DVO_HIGH_SPEED;
4538
f47709a9 4539 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4540 dpll |= DPLL_DVO_HIGH_SPEED;
4541
4542 /* compute bitmask from p1 value */
4543 if (IS_PINEVIEW(dev))
4544 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4545 else {
4546 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4547 if (IS_G4X(dev) && reduced_clock)
4548 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4549 }
4550 switch (clock->p2) {
4551 case 5:
4552 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4553 break;
4554 case 7:
4555 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4556 break;
4557 case 10:
4558 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4559 break;
4560 case 14:
4561 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4562 break;
4563 }
4564 if (INTEL_INFO(dev)->gen >= 4)
4565 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4566
f47709a9 4567 if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48 4568 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4569 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48
DV		 4570 /* XXX: just matching BIOS for now */
4571 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4572 dpll |= 3;
f47709a9 4573 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4574 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4575 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4576 else
4577 dpll |= PLL_REF_INPUT_DREFCLK;
4578
4579 dpll |= DPLL_VCO_ENABLE;
4580 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4581 POSTING_READ(DPLL(pipe));
4582 udelay(150);
4583
f47709a9 4584 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4585 if (encoder->pre_pll_enable)
4586 encoder->pre_pll_enable(encoder);
eb1cbe48 4587
f47709a9
DV		 4588 if (crtc->config.has_dp_encoder)
4589 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4590
4591 I915_WRITE(DPLL(pipe), dpll);
4592
4593 /* Wait for the clocks to stabilize. */
4594 POSTING_READ(DPLL(pipe));
4595 udelay(150);
4596
4597 if (INTEL_INFO(dev)->gen >= 4) {
198a037f
DV		 4598 u32 dpll_md = 0;
4599 if (crtc->config.pixel_multiplier > 1) {
4600 dpll_md = (crtc->config.pixel_multiplier - 1)
4601 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
eb1cbe48 4602 }
198a037f 4603 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4604 } else {
4605 /* The pixel multiplier can only be updated once the
4606 * DPLL is enabled and the clocks are stable.
4607 *
4608 * So write it again.
4609 */
4610 I915_WRITE(DPLL(pipe), dpll);
4611 }
4612}
4613
f47709a9 4614static void i8xx_update_pll(struct intel_crtc *crtc,
eb1cbe48 4615 struct drm_display_mode *adjusted_mode,
f47709a9 4616 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4617 int num_connectors)
4618{
f47709a9 4619 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4620 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4621 struct intel_encoder *encoder;
f47709a9 4622 int pipe = crtc->pipe;
eb1cbe48 4623 u32 dpll;
f47709a9 4624 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4625
f47709a9 4626 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4627
eb1cbe48
DV		 4628 dpll = DPLL_VGA_MODE_DIS;
4629
f47709a9 4630 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4631 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4632 } else {
4633 if (clock->p1 == 2)
4634 dpll |= PLL_P1_DIVIDE_BY_TWO;
4635 else
4636 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4637 if (clock->p2 == 4)
4638 dpll |= PLL_P2_DIVIDE_BY_4;
4639 }
4640
f47709a9 4641 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4642 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4643 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4644 else
4645 dpll |= PLL_REF_INPUT_DREFCLK;
4646
4647 dpll |= DPLL_VCO_ENABLE;
4648 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4649 POSTING_READ(DPLL(pipe));
4650 udelay(150);
4651
f47709a9 4652 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4653 if (encoder->pre_pll_enable)
4654 encoder->pre_pll_enable(encoder);
eb1cbe48 4655
5b5896e4
DV		 4656 I915_WRITE(DPLL(pipe), dpll);
4657
4658 /* Wait for the clocks to stabilize. */
4659 POSTING_READ(DPLL(pipe));
4660 udelay(150);
4661
eb1cbe48
DV		 4662 /* The pixel multiplier can only be updated once the
4663 * DPLL is enabled and the clocks are stable.
4664 *
4665 * So write it again.
4666 */
4667 I915_WRITE(DPLL(pipe), dpll);
4668}
4669
b0e77b9c
PZ		 4670static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4671 struct drm_display_mode *mode,
4672 struct drm_display_mode *adjusted_mode)
4673{
4674 struct drm_device *dev = intel_crtc->base.dev;
4675 struct drm_i915_private *dev_priv = dev->dev_private;
4676 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4677 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
b0e77b9c
PZ		 4678 uint32_t vsyncshift;
4679
4680 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4681 /* the chip adds 2 halflines automatically */
4682 adjusted_mode->crtc_vtotal -= 1;
4683 adjusted_mode->crtc_vblank_end -= 1;
4684 vsyncshift = adjusted_mode->crtc_hsync_start
4685 - adjusted_mode->crtc_htotal / 2;
4686 } else {
4687 vsyncshift = 0;
4688 }
4689
4690 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4691 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4692
fe2b8f9d 4693 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4694 (adjusted_mode->crtc_hdisplay - 1) |
4695 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4696 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4697 (adjusted_mode->crtc_hblank_start - 1) |
4698 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4699 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4700 (adjusted_mode->crtc_hsync_start - 1) |
4701 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4702
fe2b8f9d 4703 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4704 (adjusted_mode->crtc_vdisplay - 1) |
4705 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4706 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4707 (adjusted_mode->crtc_vblank_start - 1) |
4708 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4709 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4710 (adjusted_mode->crtc_vsync_start - 1) |
4711 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4712
b5e508d4
PZ		 4713 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4714 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4715 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4716 * bits. */
4717 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4718 (pipe == PIPE_B || pipe == PIPE_C))
4719 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4720
b0e77b9c
PZ		 4721 /* pipesrc controls the size that is scaled from, which should
4722 * always be the user's requested size.
4723 */
4724 I915_WRITE(PIPESRC(pipe),
4725 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4726}
4727
1bd1bd80
DV		 4728static void intel_get_pipe_timings(struct intel_crtc *crtc,
4729 struct intel_crtc_config *pipe_config)
4730{
4731 struct drm_device *dev = crtc->base.dev;
4732 struct drm_i915_private *dev_priv = dev->dev_private;
4733 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4734 uint32_t tmp;
4735
4736 tmp = I915_READ(HTOTAL(cpu_transcoder));
4737 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4738 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4739 tmp = I915_READ(HBLANK(cpu_transcoder));
4740 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4741 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4742 tmp = I915_READ(HSYNC(cpu_transcoder));
4743 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4744 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4745
4746 tmp = I915_READ(VTOTAL(cpu_transcoder));
4747 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4748 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4749 tmp = I915_READ(VBLANK(cpu_transcoder));
4750 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4751 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4752 tmp = I915_READ(VSYNC(cpu_transcoder));
4753 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4754 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4755
4756 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4757 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4758 pipe_config->adjusted_mode.crtc_vtotal += 1;
4759 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4760 }
4761
4762 tmp = I915_READ(PIPESRC(crtc->pipe));
4763 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4764 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4765}
4766
84b046f3
DV		 4767static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4768{
4769 struct drm_device *dev = intel_crtc->base.dev;
4770 struct drm_i915_private *dev_priv = dev->dev_private;
4771 uint32_t pipeconf;
4772
4773 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4774
4775 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4776 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4777 * core speed.
4778 *
4779 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4780 * pipe == 0 check?
4781 */
4782 if (intel_crtc->config.requested_mode.clock >
4783 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4784 pipeconf |= PIPECONF_DOUBLE_WIDE;
4785 else
4786 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4787 }
4788
ff9ce46e
DV		 4789 /* only g4x and later have fancy bpc/dither controls */
4790 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4791 pipeconf &= ~(PIPECONF_BPC_MASK |
4792 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4793
4794 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4795 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4796 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4797 PIPECONF_DITHER_TYPE_SP;
84b046f3 4798
ff9ce46e
DV		 4799 switch (intel_crtc->config.pipe_bpp) {
4800 case 18:
4801 pipeconf |= PIPECONF_6BPC;
4802 break;
4803 case 24:
4804 pipeconf |= PIPECONF_8BPC;
4805 break;
4806 case 30:
4807 pipeconf |= PIPECONF_10BPC;
4808 break;
4809 default:
4810 /* Case prevented by intel_choose_pipe_bpp_dither. */
4811 BUG();
84b046f3
DV		 4812 }
4813 }
4814
4815 if (HAS_PIPE_CXSR(dev)) {
4816 if (intel_crtc->lowfreq_avail) {
4817 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4818 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4819 } else {
4820 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4821 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4822 }
4823 }
4824
4825 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4826 if (!IS_GEN2(dev) &&
4827 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4828 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4829 else
4830 pipeconf |= PIPECONF_PROGRESSIVE;
4831
9c8e09b7
VS		 4832 if (IS_VALLEYVIEW(dev)) {
4833 if (intel_crtc->config.limited_color_range)
4834 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4835 else
4836 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4837 }
4838
84b046f3
DV		 4839 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4840 POSTING_READ(PIPECONF(intel_crtc->pipe));
4841}
4842
f564048e 4843static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4844 int x, int y,
94352cf9 4845 struct drm_framebuffer *fb)
79e53945
JB		 4846{
4847 struct drm_device *dev = crtc->dev;
4848 struct drm_i915_private *dev_priv = dev->dev_private;
4849 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4850 struct drm_display_mode *adjusted_mode =
4851 &intel_crtc->config.adjusted_mode;
4852 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4853 int pipe = intel_crtc->pipe;
80824003 4854 int plane = intel_crtc->plane;
c751ce4f 4855 int refclk, num_connectors = 0;
652c393a 4856 intel_clock_t clock, reduced_clock;
84b046f3 4857 u32 dspcntr;
eb1cbe48 4858 bool ok, has_reduced_clock = false, is_sdvo = false;
8b47047b 4859 bool is_lvds = false, is_tv = false;
5eddb70b 4860 struct intel_encoder *encoder;
d4906093 4861 const intel_limit_t *limit;
5c3b82e2 4862 int ret;
79e53945 4863
6c2b7c12 4864 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4865 switch (encoder->type) {
79e53945
JB		 4866 case INTEL_OUTPUT_LVDS:
4867 is_lvds = true;
4868 break;
4869 case INTEL_OUTPUT_SDVO:
7d57382e 4870 case INTEL_OUTPUT_HDMI:
79e53945 4871 is_sdvo = true;
5eddb70b 4872 if (encoder->needs_tv_clock)
e2f0ba97 4873 is_tv = true;
79e53945 4874 break;
79e53945
JB		 4875 case INTEL_OUTPUT_TVOUT:
4876 is_tv = true;
4877 break;
79e53945 4878 }
43565a06 4879
c751ce4f 4880 num_connectors++;
79e53945
JB		 4881 }
4882
c65d77d8 4883 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4884
d4906093
ML		 4885 /*
4886 * Returns a set of divisors for the desired target clock with the given
4887 * refclk, or FALSE. The returned values represent the clock equation:
4888 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4889 */
1b894b59 4890 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4891 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4892 &clock);
79e53945
JB		 4893 if (!ok) {
4894 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4895 return -EINVAL;
79e53945
JB		 4896 }
4897
cda4b7d3 4898 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4899 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4900
ddc9003c 4901 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4902 /*
4903 * Ensure we match the reduced clock's P to the target clock.
4904 * If the clocks don't match, we can't switch the display clock
4905 * by using the FP0/FP1. In such case we will disable the LVDS
4906 * downclock feature.
4907 */
ddc9003c 4908 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4909 dev_priv->lvds_downclock,
4910 refclk,
cec2f356 4911 &clock,
5eddb70b 4912 &reduced_clock);
7026d4ac 4913 }
f47709a9
DV		 4914 /* Compat-code for transition, will disappear. */
4915 if (!intel_crtc->config.clock_set) {
4916 intel_crtc->config.dpll.n = clock.n;
4917 intel_crtc->config.dpll.m1 = clock.m1;
4918 intel_crtc->config.dpll.m2 = clock.m2;
4919 intel_crtc->config.dpll.p1 = clock.p1;
4920 intel_crtc->config.dpll.p2 = clock.p2;
4921 }
7026d4ac 4922
c65d77d8 4923 if (is_sdvo && is_tv)
f47709a9 4924 i9xx_adjust_sdvo_tv_clock(intel_crtc);
7026d4ac 4925
eb1cbe48 4926 if (IS_GEN2(dev))
f47709a9 4927 i8xx_update_pll(intel_crtc, adjusted_mode,
2a8f64ca
VP		 4928 has_reduced_clock ? &reduced_clock : NULL,
4929 num_connectors);
a0c4da24 4930 else if (IS_VALLEYVIEW(dev))
f47709a9 4931 vlv_update_pll(intel_crtc);
79e53945 4932 else
f47709a9 4933 i9xx_update_pll(intel_crtc,
eb1cbe48 4934 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4935 num_connectors);
79e53945 4936
79e53945
JB		 4937 /* Set up the display plane register */
4938 dspcntr = DISPPLANE_GAMMA_ENABLE;
4939
da6ecc5d
JB		 4940 if (!IS_VALLEYVIEW(dev)) {
4941 if (pipe == 0)
4942 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4943 else
4944 dspcntr |= DISPPLANE_SEL_PIPE_B;
4945 }
79e53945 4946
2582a850 4947 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 4948 drm_mode_debug_printmodeline(mode);
4949
b0e77b9c 4950 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4951
4952 /* pipesrc and dspsize control the size that is scaled from,
4953 * which should always be the user's requested size.
79e53945 4954 */
929c77fb
EA		 4955 I915_WRITE(DSPSIZE(plane),
4956 ((mode->vdisplay - 1) << 16) |
4957 (mode->hdisplay - 1));
4958 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4959
84b046f3
DV		 4960 i9xx_set_pipeconf(intel_crtc);
4961
f564048e
EA		 4962 I915_WRITE(DSPCNTR(plane), dspcntr);
4963 POSTING_READ(DSPCNTR(plane));
4964
94352cf9 4965 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4966
4967 intel_update_watermarks(dev);
4968
f564048e
EA		 4969 return ret;
4970}
4971
0e8ffe1b
DV		 4972static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4973 struct intel_crtc_config *pipe_config)
4974{
4975 struct drm_device *dev = crtc->base.dev;
4976 struct drm_i915_private *dev_priv = dev->dev_private;
4977 uint32_t tmp;
4978
4979 tmp = I915_READ(PIPECONF(crtc->pipe));
4980 if (!(tmp & PIPECONF_ENABLE))
4981 return false;
4982
1bd1bd80
DV		 4983 intel_get_pipe_timings(crtc, pipe_config);
4984
0e8ffe1b
DV		 4985 return true;
4986}
4987
dde86e2d 4988static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4989{
4990 struct drm_i915_private *dev_priv = dev->dev_private;
4991 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4992 struct intel_encoder *encoder;
74cfd7ac 4993 u32 val, final;
13d83a67 4994 bool has_lvds = false;
199e5d79
KP		 4995 bool has_cpu_edp = false;
4996 bool has_pch_edp = false;
4997 bool has_panel = false;
99eb6a01
KP		 4998 bool has_ck505 = false;
4999 bool can_ssc = false;
13d83a67
JB		 5000
5001 /* We need to take the global config into account */
199e5d79
KP		 5002 list_for_each_entry(encoder, &mode_config->encoder_list,
5003 base.head) {
5004 switch (encoder->type) {
5005 case INTEL_OUTPUT_LVDS:
5006 has_panel = true;
5007 has_lvds = true;
5008 break;
5009 case INTEL_OUTPUT_EDP:
5010 has_panel = true;
5011 if (intel_encoder_is_pch_edp(&encoder->base))
5012 has_pch_edp = true;
5013 else
5014 has_cpu_edp = true;
5015 break;
13d83a67
JB		 5016 }
5017 }
5018
99eb6a01
KP		 5019 if (HAS_PCH_IBX(dev)) {
5020 has_ck505 = dev_priv->display_clock_mode;
5021 can_ssc = has_ck505;
5022 } else {
5023 has_ck505 = false;
5024 can_ssc = true;
5025 }
5026
5027 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5028 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5029 has_ck505);
13d83a67
JB		 5030
5031 /* Ironlake: try to setup display ref clock before DPLL
5032 * enabling. This is only under driver's control after
5033 * PCH B stepping, previous chipset stepping should be
5034 * ignoring this setting.
5035 */
74cfd7ac
CW		 5036 val = I915_READ(PCH_DREF_CONTROL);
5037
5038 /* As we must carefully and slowly disable/enable each source in turn,
5039 * compute the final state we want first and check if we need to
5040 * make any changes at all.
5041 */
5042 final = val;
5043 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5044 if (has_ck505)
5045 final |= DREF_NONSPREAD_CK505_ENABLE;
5046 else
5047 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5048
5049 final &= ~DREF_SSC_SOURCE_MASK;
5050 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5051 final &= ~DREF_SSC1_ENABLE;
5052
5053 if (has_panel) {
5054 final |= DREF_SSC_SOURCE_ENABLE;
5055
5056 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5057 final |= DREF_SSC1_ENABLE;
5058
5059 if (has_cpu_edp) {
5060 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5061 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5062 else
5063 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5064 } else
5065 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5066 } else {
5067 final |= DREF_SSC_SOURCE_DISABLE;
5068 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5069 }
5070
5071 if (final == val)
5072 return;
5073
13d83a67 5074 /* Always enable nonspread source */
74cfd7ac 5075 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5076
99eb6a01 5077 if (has_ck505)
74cfd7ac 5078 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5079 else
74cfd7ac 5080 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5081
199e5d79 5082 if (has_panel) {
74cfd7ac
CW		 5083 val &= ~DREF_SSC_SOURCE_MASK;
5084 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5085
199e5d79 5086 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5087 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5088 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5089 val |= DREF_SSC1_ENABLE;
e77166b5 5090 } else
74cfd7ac 5091 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5092
5093 /* Get SSC going before enabling the outputs */
74cfd7ac 5094 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5095 POSTING_READ(PCH_DREF_CONTROL);
5096 udelay(200);
5097
74cfd7ac 5098 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5099
5100 /* Enable CPU source on CPU attached eDP */
199e5d79 5101 if (has_cpu_edp) {
99eb6a01 5102 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5103 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5104 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5105 }
13d83a67 5106 else
74cfd7ac 5107 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5108 } else
74cfd7ac 5109 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5110
74cfd7ac 5111 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5112 POSTING_READ(PCH_DREF_CONTROL);
5113 udelay(200);
5114 } else {
5115 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5116
74cfd7ac 5117 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5118
5119 /* Turn off CPU output */
74cfd7ac 5120 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5121
74cfd7ac 5122 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5123 POSTING_READ(PCH_DREF_CONTROL);
5124 udelay(200);
5125
5126 /* Turn off the SSC source */
74cfd7ac
CW		 5127 val &= ~DREF_SSC_SOURCE_MASK;
5128 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5129
5130 /* Turn off SSC1 */
74cfd7ac 5131 val &= ~DREF_SSC1_ENABLE;
199e5d79 5132
74cfd7ac 5133 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5134 POSTING_READ(PCH_DREF_CONTROL);
5135 udelay(200);
5136 }
74cfd7ac
CW		 5137
5138 BUG_ON(val != final);
13d83a67
JB		 5139}
5140
dde86e2d
PZ		 5141/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5142static void lpt_init_pch_refclk(struct drm_device *dev)
5143{
5144 struct drm_i915_private *dev_priv = dev->dev_private;
5145 struct drm_mode_config *mode_config = &dev->mode_config;
5146 struct intel_encoder *encoder;
5147 bool has_vga = false;
5148 bool is_sdv = false;
5149 u32 tmp;
5150
5151 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5152 switch (encoder->type) {
5153 case INTEL_OUTPUT_ANALOG:
5154 has_vga = true;
5155 break;
5156 }
5157 }
5158
5159 if (!has_vga)
5160 return;
5161
c00db246
DV		 5162 mutex_lock(&dev_priv->dpio_lock);
5163
dde86e2d
PZ		 5164 /* XXX: Rip out SDV support once Haswell ships for real. */
5165 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5166 is_sdv = true;
5167
5168 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5169 tmp &= ~SBI_SSCCTL_DISABLE;
5170 tmp |= SBI_SSCCTL_PATHALT;
5171 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5172
5173 udelay(24);
5174
5175 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5176 tmp &= ~SBI_SSCCTL_PATHALT;
5177 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5178
5179 if (!is_sdv) {
5180 tmp = I915_READ(SOUTH_CHICKEN2);
5181 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5182 I915_WRITE(SOUTH_CHICKEN2, tmp);
5183
5184 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5185 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5186 DRM_ERROR("FDI mPHY reset assert timeout\n");
5187
5188 tmp = I915_READ(SOUTH_CHICKEN2);
5189 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5190 I915_WRITE(SOUTH_CHICKEN2, tmp);
5191
5192 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5193 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5194 100))
5195 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5196 }
5197
5198 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5199 tmp &= ~(0xFF << 24);
5200 tmp |= (0x12 << 24);
5201 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5202
dde86e2d
PZ		 5203 if (is_sdv) {
5204 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5205 tmp |= 0x7FFF;
5206 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5207 }
5208
5209 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5210 tmp |= (1 << 11);
5211 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5212
5213 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5214 tmp |= (1 << 11);
5215 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5216
5217 if (is_sdv) {
5218 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5219 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5220 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5221
5222 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5223 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5224 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5225
5226 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5227 tmp |= (0x3F << 8);
5228 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5229
5230 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5231 tmp |= (0x3F << 8);
5232 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5233 }
5234
5235 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5236 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5237 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5238
5239 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5240 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5241 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5242
5243 if (!is_sdv) {
5244 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5245 tmp &= ~(7 << 13);
5246 tmp |= (5 << 13);
5247 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5248
5249 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5250 tmp &= ~(7 << 13);
5251 tmp |= (5 << 13);
5252 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5253 }
5254
5255 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5256 tmp &= ~0xFF;
5257 tmp |= 0x1C;
5258 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5259
5260 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5261 tmp &= ~0xFF;
5262 tmp |= 0x1C;
5263 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5264
5265 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5266 tmp &= ~(0xFF << 16);
5267 tmp |= (0x1C << 16);
5268 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5269
5270 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5271 tmp &= ~(0xFF << 16);
5272 tmp |= (0x1C << 16);
5273 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5274
5275 if (!is_sdv) {
5276 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5277 tmp |= (1 << 27);
5278 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5279
5280 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5281 tmp |= (1 << 27);
5282 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5283
5284 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5285 tmp &= ~(0xF << 28);
5286 tmp |= (4 << 28);
5287 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5288
5289 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5290 tmp &= ~(0xF << 28);
5291 tmp |= (4 << 28);
5292 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5293 }
5294
5295 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5296 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5297 tmp |= SBI_DBUFF0_ENABLE;
5298 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5299
5300 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5301}
5302
5303/*
5304 * Initialize reference clocks when the driver loads
5305 */
5306void intel_init_pch_refclk(struct drm_device *dev)
5307{
5308 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5309 ironlake_init_pch_refclk(dev);
5310 else if (HAS_PCH_LPT(dev))
5311 lpt_init_pch_refclk(dev);
5312}
5313
d9d444cb
JB		 5314static int ironlake_get_refclk(struct drm_crtc *crtc)
5315{
5316 struct drm_device *dev = crtc->dev;
5317 struct drm_i915_private *dev_priv = dev->dev_private;
5318 struct intel_encoder *encoder;
d9d444cb
JB		 5319 struct intel_encoder *edp_encoder = NULL;
5320 int num_connectors = 0;
5321 bool is_lvds = false;
5322
6c2b7c12 5323 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5324 switch (encoder->type) {
5325 case INTEL_OUTPUT_LVDS:
5326 is_lvds = true;
5327 break;
5328 case INTEL_OUTPUT_EDP:
5329 edp_encoder = encoder;
5330 break;
5331 }
5332 num_connectors++;
5333 }
5334
5335 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5336 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5337 dev_priv->lvds_ssc_freq);
5338 return dev_priv->lvds_ssc_freq * 1000;
5339 }
5340
5341 return 120000;
5342}
5343
6ff93609 5344static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5345{
c8203565 5346 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5348 int pipe = intel_crtc->pipe;
c8203565
PZ		 5349 uint32_t val;
5350
5351 val = I915_READ(PIPECONF(pipe));
5352
dfd07d72 5353 val &= ~PIPECONF_BPC_MASK;
965e0c48 5354 switch (intel_crtc->config.pipe_bpp) {
c8203565 5355 case 18:
dfd07d72 5356 val |= PIPECONF_6BPC;
c8203565
PZ		 5357 break;
5358 case 24:
dfd07d72 5359 val |= PIPECONF_8BPC;
c8203565
PZ		 5360 break;
5361 case 30:
dfd07d72 5362 val |= PIPECONF_10BPC;
c8203565
PZ		 5363 break;
5364 case 36:
dfd07d72 5365 val |= PIPECONF_12BPC;
c8203565
PZ		 5366 break;
5367 default:
cc769b62
PZ		 5368 /* Case prevented by intel_choose_pipe_bpp_dither. */
5369 BUG();
c8203565
PZ		 5370 }
5371
5372 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5373 if (intel_crtc->config.dither)
c8203565
PZ		 5374 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5375
5376 val &= ~PIPECONF_INTERLACE_MASK;
6ff93609 5377 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5378 val |= PIPECONF_INTERLACED_ILK;
5379 else
5380 val |= PIPECONF_PROGRESSIVE;
5381
50f3b016 5382 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5383 val |= PIPECONF_COLOR_RANGE_SELECT;
5384 else
5385 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5386
c8203565
PZ		 5387 I915_WRITE(PIPECONF(pipe), val);
5388 POSTING_READ(PIPECONF(pipe));
5389}
5390
86d3efce
VS		 5391/*
5392 * Set up the pipe CSC unit.
5393 *
5394 * Currently only full range RGB to limited range RGB conversion
5395 * is supported, but eventually this should handle various
5396 * RGB<->YCbCr scenarios as well.
5397 */
50f3b016 5398static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5399{
5400 struct drm_device *dev = crtc->dev;
5401 struct drm_i915_private *dev_priv = dev->dev_private;
5402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5403 int pipe = intel_crtc->pipe;
5404 uint16_t coeff = 0x7800; /* 1.0 */
5405
5406 /*
5407 * TODO: Check what kind of values actually come out of the pipe
5408 * with these coeff/postoff values and adjust to get the best
5409 * accuracy. Perhaps we even need to take the bpc value into
5410 * consideration.
5411 */
5412
50f3b016 5413 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5414 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5415
5416 /*
5417 * GY/GU and RY/RU should be the other way around according
5418 * to BSpec, but reality doesn't agree. Just set them up in
5419 * a way that results in the correct picture.
5420 */
5421 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5422 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5423
5424 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5425 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5426
5427 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5428 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5429
5430 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5431 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5432 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5433
5434 if (INTEL_INFO(dev)->gen > 6) {
5435 uint16_t postoff = 0;
5436
50f3b016 5437 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5438 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5439
5440 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5441 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5442 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5443
5444 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5445 } else {
5446 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5447
50f3b016 5448 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5449 mode |= CSC_BLACK_SCREEN_OFFSET;
5450
5451 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5452 }
5453}
5454
6ff93609 5455static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5456{
5457 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5458 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5459 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5460 uint32_t val;
5461
702e7a56 5462 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5463
5464 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5465 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5466 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5467
5468 val &= ~PIPECONF_INTERLACE_MASK_HSW;
6ff93609 5469 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5470 val |= PIPECONF_INTERLACED_ILK;
5471 else
5472 val |= PIPECONF_PROGRESSIVE;
5473
702e7a56
PZ		 5474 I915_WRITE(PIPECONF(cpu_transcoder), val);
5475 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5476}
5477
6591c6e4
PZ		 5478static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5479 struct drm_display_mode *adjusted_mode,
5480 intel_clock_t *clock,
5481 bool *has_reduced_clock,
5482 intel_clock_t *reduced_clock)
5483{
5484 struct drm_device *dev = crtc->dev;
5485 struct drm_i915_private *dev_priv = dev->dev_private;
5486 struct intel_encoder *intel_encoder;
5487 int refclk;
d4906093 5488 const intel_limit_t *limit;
6591c6e4 5489 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5490
6591c6e4
PZ		 5491 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5492 switch (intel_encoder->type) {
79e53945
JB		 5493 case INTEL_OUTPUT_LVDS:
5494 is_lvds = true;
5495 break;
5496 case INTEL_OUTPUT_SDVO:
7d57382e 5497 case INTEL_OUTPUT_HDMI:
79e53945 5498 is_sdvo = true;
6591c6e4 5499 if (intel_encoder->needs_tv_clock)
e2f0ba97 5500 is_tv = true;
79e53945 5501 break;
79e53945
JB		 5502 case INTEL_OUTPUT_TVOUT:
5503 is_tv = true;
5504 break;
79e53945
JB		 5505 }
5506 }
5507
d9d444cb 5508 refclk = ironlake_get_refclk(crtc);
79e53945 5509
d4906093
ML		 5510 /*
5511 * Returns a set of divisors for the desired target clock with the given
5512 * refclk, or FALSE. The returned values represent the clock equation:
5513 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5514 */
1b894b59 5515 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5516 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5517 clock);
5518 if (!ret)
5519 return false;
cda4b7d3 5520
ddc9003c 5521 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5522 /*
5523 * Ensure we match the reduced clock's P to the target clock.
5524 * If the clocks don't match, we can't switch the display clock
5525 * by using the FP0/FP1. In such case we will disable the LVDS
5526 * downclock feature.
5527 */
6591c6e4
PZ		 5528 *has_reduced_clock = limit->find_pll(limit, crtc,
5529 dev_priv->lvds_downclock,
5530 refclk,
5531 clock,
5532 reduced_clock);
652c393a 5533 }
61e9653f
DV		 5534
5535 if (is_sdvo && is_tv)
f47709a9 5536 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
6591c6e4
PZ		 5537
5538 return true;
5539}
5540
01a415fd
DV		 5541static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5542{
5543 struct drm_i915_private *dev_priv = dev->dev_private;
5544 uint32_t temp;
5545
5546 temp = I915_READ(SOUTH_CHICKEN1);
5547 if (temp & FDI_BC_BIFURCATION_SELECT)
5548 return;
5549
5550 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5551 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5552
5553 temp |= FDI_BC_BIFURCATION_SELECT;
5554 DRM_DEBUG_KMS("enabling fdi C rx\n");
5555 I915_WRITE(SOUTH_CHICKEN1, temp);
5556 POSTING_READ(SOUTH_CHICKEN1);
5557}
5558
ebfd86fd
DV		 5559static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5560{
5561 struct drm_device *dev = intel_crtc->base.dev;
5562 struct drm_i915_private *dev_priv = dev->dev_private;
5563
5564 switch (intel_crtc->pipe) {
5565 case PIPE_A:
5566 break;
5567 case PIPE_B:
5568 if (intel_crtc->config.fdi_lanes > 2)
5569 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5570 else
5571 cpt_enable_fdi_bc_bifurcation(dev);
5572
5573 break;
5574 case PIPE_C:
01a415fd
DV		 5575 cpt_enable_fdi_bc_bifurcation(dev);
5576
ebfd86fd 5577 break;
01a415fd
DV		 5578 default:
5579 BUG();
5580 }
5581}
5582
d4b1931c
PZ		 5583int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5584{
5585 /*
5586 * Account for spread spectrum to avoid
5587 * oversubscribing the link. Max center spread
5588 * is 2.5%; use 5% for safety's sake.
5589 */
5590 u32 bps = target_clock * bpp * 21 / 20;
5591 return bps / (link_bw * 8) + 1;
5592}
5593
6cf86a5e
DV		 5594void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5595 struct intel_link_m_n *m_n)
79e53945 5596{
6cf86a5e
DV		 5597 struct drm_device *dev = crtc->base.dev;
5598 struct drm_i915_private *dev_priv = dev->dev_private;
5599 int pipe = crtc->pipe;
5600
5601 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5602 I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5603 I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5604 I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5605}
5606
5607void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5608 struct intel_link_m_n *m_n)
5609{
5610 struct drm_device *dev = crtc->base.dev;
79e53945 5611 struct drm_i915_private *dev_priv = dev->dev_private;
6cf86a5e 5612 int pipe = crtc->pipe;
3b117c8f 5613 enum transcoder transcoder = crtc->config.cpu_transcoder;
6cf86a5e
DV		 5614
5615 if (INTEL_INFO(dev)->gen >= 5) {
5616 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5617 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5618 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5619 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5620 } else {
5621 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5622 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5623 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5624 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5625 }
5626}
5627
7429e9d4
DV		 5628static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5629{
5630 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5631}
5632
de13a2e3 5633static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5634 u32 *fp,
9a7c7890 5635 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5636{
de13a2e3 5637 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5638 struct drm_device *dev = crtc->dev;
5639 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5640 struct intel_encoder *intel_encoder;
5641 uint32_t dpll;
6cc5f341 5642 int factor, num_connectors = 0;
de13a2e3 5643 bool is_lvds = false, is_sdvo = false, is_tv = false;
79e53945 5644
de13a2e3
PZ		 5645 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5646 switch (intel_encoder->type) {
79e53945
JB		 5647 case INTEL_OUTPUT_LVDS:
5648 is_lvds = true;
5649 break;
5650 case INTEL_OUTPUT_SDVO:
7d57382e 5651 case INTEL_OUTPUT_HDMI:
79e53945 5652 is_sdvo = true;
de13a2e3 5653 if (intel_encoder->needs_tv_clock)
e2f0ba97 5654 is_tv = true;
79e53945 5655 break;
79e53945
JB		 5656 case INTEL_OUTPUT_TVOUT:
5657 is_tv = true;
5658 break;
79e53945 5659 }
43565a06 5660
c751ce4f 5661 num_connectors++;
79e53945 5662 }
79e53945 5663
c1858123 5664 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5665 factor = 21;
5666 if (is_lvds) {
5667 if ((intel_panel_use_ssc(dev_priv) &&
5668 dev_priv->lvds_ssc_freq == 100) ||
f0b44056 5669 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297
EA		 5670 factor = 25;
5671 } else if (is_sdvo && is_tv)
5672 factor = 20;
c1858123 5673
7429e9d4 5674 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5675 *fp |= FP_CB_TUNE;
2c07245f 5676
9a7c7890
DV		 5677 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5678 *fp2 |= FP_CB_TUNE;
5679
5eddb70b 5680 dpll = 0;
2c07245f 5681
a07d6787
EA		 5682 if (is_lvds)
5683 dpll |= DPLLB_MODE_LVDS;
5684 else
5685 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f
DV		 5686
5687 if (intel_crtc->config.pixel_multiplier > 1) {
5688 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5689 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
a07d6787 5690 }
198a037f
DV		 5691
5692 if (is_sdvo)
5693 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5694 if (intel_crtc->config.has_dp_encoder)
a07d6787 5695 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5696
a07d6787 5697 /* compute bitmask from p1 value */
7429e9d4 5698 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5699 /* also FPA1 */
7429e9d4 5700 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5701
7429e9d4 5702 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5703 case 5:
5704 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5705 break;
5706 case 7:
5707 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5708 break;
5709 case 10:
5710 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5711 break;
5712 case 14:
5713 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5714 break;
79e53945
JB		 5715 }
5716
43565a06
KH		 5717 if (is_sdvo && is_tv)
5718 dpll |= PLL_REF_INPUT_TVCLKINBC;
5719 else if (is_tv)
79e53945 5720 /* XXX: just matching BIOS for now */
43565a06 5721 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5722 dpll |= 3;
a7615030 5723 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5724 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5725 else
5726 dpll |= PLL_REF_INPUT_DREFCLK;
5727
de13a2e3
PZ		 5728 return dpll;
5729}
5730
5731static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5732 int x, int y,
5733 struct drm_framebuffer *fb)
5734{
5735 struct drm_device *dev = crtc->dev;
5736 struct drm_i915_private *dev_priv = dev->dev_private;
5737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5738 struct drm_display_mode *adjusted_mode =
5739 &intel_crtc->config.adjusted_mode;
5740 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5741 int pipe = intel_crtc->pipe;
5742 int plane = intel_crtc->plane;
5743 int num_connectors = 0;
5744 intel_clock_t clock, reduced_clock;
cbbab5bd 5745 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5746 bool ok, has_reduced_clock = false;
8b47047b 5747 bool is_lvds = false;
de13a2e3 5748 struct intel_encoder *encoder;
de13a2e3 5749 int ret;
de13a2e3
PZ		 5750
5751 for_each_encoder_on_crtc(dev, crtc, encoder) {
5752 switch (encoder->type) {
5753 case INTEL_OUTPUT_LVDS:
5754 is_lvds = true;
5755 break;
de13a2e3
PZ		 5756 }
5757
5758 num_connectors++;
a07d6787 5759 }
79e53945 5760
5dc5298b
PZ		 5761 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5762 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5763
3b117c8f 5764 intel_crtc->config.cpu_transcoder = pipe;
6cf86a5e 5765
de13a2e3
PZ		 5766 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5767 &has_reduced_clock, &reduced_clock);
5768 if (!ok) {
5769 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5770 return -EINVAL;
79e53945 5771 }
f47709a9
DV		 5772 /* Compat-code for transition, will disappear. */
5773 if (!intel_crtc->config.clock_set) {
5774 intel_crtc->config.dpll.n = clock.n;
5775 intel_crtc->config.dpll.m1 = clock.m1;
5776 intel_crtc->config.dpll.m2 = clock.m2;
5777 intel_crtc->config.dpll.p1 = clock.p1;
5778 intel_crtc->config.dpll.p2 = clock.p2;
5779 }
79e53945 5780
de13a2e3
PZ		 5781 /* Ensure that the cursor is valid for the new mode before changing... */
5782 intel_crtc_update_cursor(crtc, true);
5783
84f44ce7 5784 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 5785 drm_mode_debug_printmodeline(mode);
5786
5dc5298b 5787 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5788 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5789 struct intel_pch_pll *pll;
4b645f14 5790
7429e9d4 5791 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5792 if (has_reduced_clock)
7429e9d4 5793 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5794
7429e9d4 5795 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5796 &fp, &reduced_clock,
5797 has_reduced_clock ? &fp2 : NULL);
5798
ee7b9f93
JB		 5799 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5800 if (pll == NULL) {
84f44ce7
VS		 5801 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5802 pipe_name(pipe));
4b645f14
JB		 5803 return -EINVAL;
5804 }
ee7b9f93
JB		 5805 } else
5806 intel_put_pch_pll(intel_crtc);
79e53945 5807
03afc4a2
DV		 5808 if (intel_crtc->config.has_dp_encoder)
5809 intel_dp_set_m_n(intel_crtc);
79e53945 5810
dafd226c
DV		 5811 for_each_encoder_on_crtc(dev, crtc, encoder)
5812 if (encoder->pre_pll_enable)
5813 encoder->pre_pll_enable(encoder);
79e53945 5814
ee7b9f93
JB		 5815 if (intel_crtc->pch_pll) {
5816 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5817
32f9d658 5818 /* Wait for the clocks to stabilize. */
ee7b9f93 5819 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5820 udelay(150);
5821
8febb297
EA		 5822 /* The pixel multiplier can only be updated once the
5823 * DPLL is enabled and the clocks are stable.
5824 *
5825 * So write it again.
5826 */
ee7b9f93 5827 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5828 }
79e53945 5829
5eddb70b 5830 intel_crtc->lowfreq_avail = false;
ee7b9f93 5831 if (intel_crtc->pch_pll) {
4b645f14 5832 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5833 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5834 intel_crtc->lowfreq_avail = true;
4b645f14 5835 } else {
ee7b9f93 5836 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5837 }
5838 }
5839
b0e77b9c 5840 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5841
ca3a0ff8 5842 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5843 intel_cpu_transcoder_set_m_n(intel_crtc,
5844 &intel_crtc->config.fdi_m_n);
5845 }
2c07245f 5846
ebfd86fd
DV		 5847 if (IS_IVYBRIDGE(dev))
5848 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
2c07245f 5849
6ff93609 5850 ironlake_set_pipeconf(crtc);
79e53945 5851
a1f9e77e
PZ		 5852 /* Set up the display plane register */
5853 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5854 POSTING_READ(DSPCNTR(plane));
79e53945 5855
94352cf9 5856 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5857
5858 intel_update_watermarks(dev);
5859
1f8eeabf
ED		 5860 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5861
1857e1da 5862 return ret;
79e53945
JB		 5863}
5864
72419203
DV		 5865static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5866 struct intel_crtc_config *pipe_config)
5867{
5868 struct drm_device *dev = crtc->base.dev;
5869 struct drm_i915_private *dev_priv = dev->dev_private;
5870 enum transcoder transcoder = pipe_config->cpu_transcoder;
5871
5872 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5873 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5874 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5875 & ~TU_SIZE_MASK;
5876 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5877 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5878 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5879}
5880
0e8ffe1b
DV		 5881static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5882 struct intel_crtc_config *pipe_config)
5883{
5884 struct drm_device *dev = crtc->base.dev;
5885 struct drm_i915_private *dev_priv = dev->dev_private;
5886 uint32_t tmp;
5887
5888 tmp = I915_READ(PIPECONF(crtc->pipe));
5889 if (!(tmp & PIPECONF_ENABLE))
5890 return false;
5891
627eb5a3 5892 if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
88adfff1
DV		 5893 pipe_config->has_pch_encoder = true;
5894
627eb5a3
DV		 5895 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5896 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5897 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5898
5899 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5900 }
5901
1bd1bd80
DV		 5902 intel_get_pipe_timings(crtc, pipe_config);
5903
0e8ffe1b
DV		 5904 return true;
5905}
5906
d6dd9eb1
DV		 5907static void haswell_modeset_global_resources(struct drm_device *dev)
5908{
5909 struct drm_i915_private *dev_priv = dev->dev_private;
5910 bool enable = false;
5911 struct intel_crtc *crtc;
5912 struct intel_encoder *encoder;
5913
5914 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5915 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5916 enable = true;
5917 /* XXX: Should check for edp transcoder here, but thanks to init
5918 * sequence that's not yet available. Just in case desktop eDP
5919 * on PORT D is possible on haswell, too. */
b074cec8
JB		 5920 /* Even the eDP panel fitter is outside the always-on well. */
5921 if (I915_READ(PF_WIN_SZ(crtc->pipe)))
5922 enable = true;
d6dd9eb1
DV		 5923 }
5924
5925 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5926 base.head) {
5927 if (encoder->type != INTEL_OUTPUT_EDP &&
5928 encoder->connectors_active)
5929 enable = true;
5930 }
5931
d6dd9eb1
DV		 5932 intel_set_power_well(dev, enable);
5933}
5934
09b4ddf9 5935static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5936 int x, int y,
5937 struct drm_framebuffer *fb)
5938{
5939 struct drm_device *dev = crtc->dev;
5940 struct drm_i915_private *dev_priv = dev->dev_private;
5941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5942 struct drm_display_mode *adjusted_mode =
5943 &intel_crtc->config.adjusted_mode;
5944 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5945 int pipe = intel_crtc->pipe;
5946 int plane = intel_crtc->plane;
5947 int num_connectors = 0;
8b47047b 5948 bool is_cpu_edp = false;
09b4ddf9 5949 struct intel_encoder *encoder;
09b4ddf9 5950 int ret;
09b4ddf9
PZ		 5951
5952 for_each_encoder_on_crtc(dev, crtc, encoder) {
5953 switch (encoder->type) {
09b4ddf9 5954 case INTEL_OUTPUT_EDP:
09b4ddf9
PZ		 5955 if (!intel_encoder_is_pch_edp(&encoder->base))
5956 is_cpu_edp = true;
5957 break;
5958 }
5959
5960 num_connectors++;
5961 }
5962
bba2181c 5963 if (is_cpu_edp)
3b117c8f 5964 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
bba2181c 5965 else
3b117c8f 5966 intel_crtc->config.cpu_transcoder = pipe;
bba2181c 5967
5dc5298b
PZ		 5968 /* We are not sure yet this won't happen. */
5969 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5970 INTEL_PCH_TYPE(dev));
5971
5972 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5973 num_connectors, pipe_name(pipe));
5974
3b117c8f 5975 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
1ce42920
PZ		 5976 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5977
5978 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5979
6441ab5f
PZ		 5980 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5981 return -EINVAL;
5982
09b4ddf9
PZ		 5983 /* Ensure that the cursor is valid for the new mode before changing... */
5984 intel_crtc_update_cursor(crtc, true);
5985
84f44ce7 5986 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
09b4ddf9
PZ		 5987 drm_mode_debug_printmodeline(mode);
5988
03afc4a2
DV		 5989 if (intel_crtc->config.has_dp_encoder)
5990 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5991
5992 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5993
5994 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5995
ca3a0ff8 5996 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5997 intel_cpu_transcoder_set_m_n(intel_crtc,
5998 &intel_crtc->config.fdi_m_n);
5999 }
09b4ddf9 6000
6ff93609 6001 haswell_set_pipeconf(crtc);
09b4ddf9 6002
50f3b016 6003 intel_set_pipe_csc(crtc);
86d3efce 6004
09b4ddf9 6005 /* Set up the display plane register */
86d3efce 6006 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6007 POSTING_READ(DSPCNTR(plane));
6008
6009 ret = intel_pipe_set_base(crtc, x, y, fb);
6010
6011 intel_update_watermarks(dev);
6012
6013 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
6014
1f803ee5 6015 return ret;
79e53945
JB		 6016}
6017
0e8ffe1b
DV		 6018static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6019 struct intel_crtc_config *pipe_config)
6020{
6021 struct drm_device *dev = crtc->base.dev;
6022 struct drm_i915_private *dev_priv = dev->dev_private;
2bfce950 6023 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
0e8ffe1b
DV		 6024 uint32_t tmp;
6025
2bfce950
PZ		 6026 if (!intel_using_power_well(dev_priv->dev) &&
6027 cpu_transcoder != TRANSCODER_EDP)
6028 return false;
6029
6030 tmp = I915_READ(PIPECONF(cpu_transcoder));
0e8ffe1b
DV		 6031 if (!(tmp & PIPECONF_ENABLE))
6032 return false;
6033
88adfff1 6034 /*
f196e6be 6035 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6036 * DDI E. So just check whether this pipe is wired to DDI E and whether
6037 * the PCH transcoder is on.
6038 */
f196e6be 6039 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
88adfff1 6040 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
627eb5a3 6041 I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE) {
88adfff1
DV		 6042 pipe_config->has_pch_encoder = true;
6043
627eb5a3
DV		 6044 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6045 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6046 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6047
6048 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6049 }
6050
1bd1bd80
DV		 6051 intel_get_pipe_timings(crtc, pipe_config);
6052
0e8ffe1b
DV		 6053 return true;
6054}
6055
f564048e 6056static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6057 int x, int y,
94352cf9 6058 struct drm_framebuffer *fb)
f564048e
EA		 6059{
6060 struct drm_device *dev = crtc->dev;
6061 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6062 struct drm_encoder_helper_funcs *encoder_funcs;
6063 struct intel_encoder *encoder;
0b701d27 6064 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6065 struct drm_display_mode *adjusted_mode =
6066 &intel_crtc->config.adjusted_mode;
6067 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6068 int pipe = intel_crtc->pipe;
f564048e
EA		 6069 int ret;
6070
0b701d27 6071 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6072
b8cecdf5
DV		 6073 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6074
79e53945 6075 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6076
9256aa19
DV		 6077 if (ret != 0)
6078 return ret;
6079
6080 for_each_encoder_on_crtc(dev, crtc, encoder) {
6081 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6082 encoder->base.base.id,
6083 drm_get_encoder_name(&encoder->base),
6084 mode->base.id, mode->name);
6cc5f341
DV		 6085 if (encoder->mode_set) {
6086 encoder->mode_set(encoder);
6087 } else {
6088 encoder_funcs = encoder->base.helper_private;
6089 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6090 }
9256aa19
DV		 6091 }
6092
6093 return 0;
79e53945
JB		 6094}
6095
3a9627f4
WF		 6096static bool intel_eld_uptodate(struct drm_connector *connector,
6097 int reg_eldv, uint32_t bits_eldv,
6098 int reg_elda, uint32_t bits_elda,
6099 int reg_edid)
6100{
6101 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6102 uint8_t *eld = connector->eld;
6103 uint32_t i;
6104
6105 i = I915_READ(reg_eldv);
6106 i &= bits_eldv;
6107
6108 if (!eld[0])
6109 return !i;
6110
6111 if (!i)
6112 return false;
6113
6114 i = I915_READ(reg_elda);
6115 i &= ~bits_elda;
6116 I915_WRITE(reg_elda, i);
6117
6118 for (i = 0; i < eld[2]; i++)
6119 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6120 return false;
6121
6122 return true;
6123}
6124
e0dac65e
WF		 6125static void g4x_write_eld(struct drm_connector *connector,
6126 struct drm_crtc *crtc)
6127{
6128 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6129 uint8_t *eld = connector->eld;
6130 uint32_t eldv;
6131 uint32_t len;
6132 uint32_t i;
6133
6134 i = I915_READ(G4X_AUD_VID_DID);
6135
6136 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6137 eldv = G4X_ELDV_DEVCL_DEVBLC;
6138 else
6139 eldv = G4X_ELDV_DEVCTG;
6140
3a9627f4
WF		 6141 if (intel_eld_uptodate(connector,
6142 G4X_AUD_CNTL_ST, eldv,
6143 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6144 G4X_HDMIW_HDMIEDID))
6145 return;
6146
e0dac65e
WF		 6147 i = I915_READ(G4X_AUD_CNTL_ST);
6148 i &= ~(eldv | G4X_ELD_ADDR);
6149 len = (i >> 9) & 0x1f; /* ELD buffer size */
6150 I915_WRITE(G4X_AUD_CNTL_ST, i);
6151
6152 if (!eld[0])
6153 return;
6154
6155 len = min_t(uint8_t, eld[2], len);
6156 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6157 for (i = 0; i < len; i++)
6158 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6159
6160 i = I915_READ(G4X_AUD_CNTL_ST);
6161 i |= eldv;
6162 I915_WRITE(G4X_AUD_CNTL_ST, i);
6163}
6164
83358c85
WX		 6165static void haswell_write_eld(struct drm_connector *connector,
6166 struct drm_crtc *crtc)
6167{
6168 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6169 uint8_t *eld = connector->eld;
6170 struct drm_device *dev = crtc->dev;
7b9f35a6 6171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6172 uint32_t eldv;
6173 uint32_t i;
6174 int len;
6175 int pipe = to_intel_crtc(crtc)->pipe;
6176 int tmp;
6177
6178 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6179 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6180 int aud_config = HSW_AUD_CFG(pipe);
6181 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6182
6183
6184 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6185
6186 /* Audio output enable */
6187 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6188 tmp = I915_READ(aud_cntrl_st2);
6189 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6190 I915_WRITE(aud_cntrl_st2, tmp);
6191
6192 /* Wait for 1 vertical blank */
6193 intel_wait_for_vblank(dev, pipe);
6194
6195 /* Set ELD valid state */
6196 tmp = I915_READ(aud_cntrl_st2);
6197 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6198 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6199 I915_WRITE(aud_cntrl_st2, tmp);
6200 tmp = I915_READ(aud_cntrl_st2);
6201 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6202
6203 /* Enable HDMI mode */
6204 tmp = I915_READ(aud_config);
6205 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6206 /* clear N_programing_enable and N_value_index */
6207 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6208 I915_WRITE(aud_config, tmp);
6209
6210 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6211
6212 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6213 intel_crtc->eld_vld = true;
83358c85
WX		 6214
6215 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6216 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6217 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6218 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6219 } else
6220 I915_WRITE(aud_config, 0);
6221
6222 if (intel_eld_uptodate(connector,
6223 aud_cntrl_st2, eldv,
6224 aud_cntl_st, IBX_ELD_ADDRESS,
6225 hdmiw_hdmiedid))
6226 return;
6227
6228 i = I915_READ(aud_cntrl_st2);
6229 i &= ~eldv;
6230 I915_WRITE(aud_cntrl_st2, i);
6231
6232 if (!eld[0])
6233 return;
6234
6235 i = I915_READ(aud_cntl_st);
6236 i &= ~IBX_ELD_ADDRESS;
6237 I915_WRITE(aud_cntl_st, i);
6238 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6239 DRM_DEBUG_DRIVER("port num:%d\n", i);
6240
6241 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6242 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6243 for (i = 0; i < len; i++)
6244 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6245
6246 i = I915_READ(aud_cntrl_st2);
6247 i |= eldv;
6248 I915_WRITE(aud_cntrl_st2, i);
6249
6250}
6251
e0dac65e
WF		 6252static void ironlake_write_eld(struct drm_connector *connector,
6253 struct drm_crtc *crtc)
6254{
6255 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6256 uint8_t *eld = connector->eld;
6257 uint32_t eldv;
6258 uint32_t i;
6259 int len;
6260 int hdmiw_hdmiedid;
b6daa025 6261 int aud_config;
e0dac65e
WF		 6262 int aud_cntl_st;
6263 int aud_cntrl_st2;
9b138a83 6264 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6265
b3f33cbf 6266 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6267 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6268 aud_config = IBX_AUD_CFG(pipe);
6269 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6270 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6271 } else {
9b138a83
WX		 6272 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6273 aud_config = CPT_AUD_CFG(pipe);
6274 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6275 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6276 }
6277
9b138a83 6278 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6279
6280 i = I915_READ(aud_cntl_st);
9b138a83 6281 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6282 if (!i) {
6283 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6284 /* operate blindly on all ports */
1202b4c6
WF		 6285 eldv = IBX_ELD_VALIDB;
6286 eldv |= IBX_ELD_VALIDB << 4;
6287 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6288 } else {
2582a850 6289 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6290 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6291 }
6292
3a9627f4
WF		 6293 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6294 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6295 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6296 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6297 } else
6298 I915_WRITE(aud_config, 0);
e0dac65e 6299
3a9627f4
WF		 6300 if (intel_eld_uptodate(connector,
6301 aud_cntrl_st2, eldv,
6302 aud_cntl_st, IBX_ELD_ADDRESS,
6303 hdmiw_hdmiedid))
6304 return;
6305
e0dac65e
WF		 6306 i = I915_READ(aud_cntrl_st2);
6307 i &= ~eldv;
6308 I915_WRITE(aud_cntrl_st2, i);
6309
6310 if (!eld[0])
6311 return;
6312
e0dac65e 6313 i = I915_READ(aud_cntl_st);
1202b4c6 6314 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6315 I915_WRITE(aud_cntl_st, i);
6316
6317 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6318 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6319 for (i = 0; i < len; i++)
6320 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6321
6322 i = I915_READ(aud_cntrl_st2);
6323 i |= eldv;
6324 I915_WRITE(aud_cntrl_st2, i);
6325}
6326
6327void intel_write_eld(struct drm_encoder *encoder,
6328 struct drm_display_mode *mode)
6329{
6330 struct drm_crtc *crtc = encoder->crtc;
6331 struct drm_connector *connector;
6332 struct drm_device *dev = encoder->dev;
6333 struct drm_i915_private *dev_priv = dev->dev_private;
6334
6335 connector = drm_select_eld(encoder, mode);
6336 if (!connector)
6337 return;
6338
6339 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6340 connector->base.id,
6341 drm_get_connector_name(connector),
6342 connector->encoder->base.id,
6343 drm_get_encoder_name(connector->encoder));
6344
6345 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6346
6347 if (dev_priv->display.write_eld)
6348 dev_priv->display.write_eld(connector, crtc);
6349}
6350
79e53945
JB		 6351/** Loads the palette/gamma unit for the CRTC with the prepared values */
6352void intel_crtc_load_lut(struct drm_crtc *crtc)
6353{
6354 struct drm_device *dev = crtc->dev;
6355 struct drm_i915_private *dev_priv = dev->dev_private;
6356 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6357 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6358 int i;
6359
6360 /* The clocks have to be on to load the palette. */
aed3f09d 6361 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6362 return;
6363
f2b115e6 6364 /* use legacy palette for Ironlake */
bad720ff 6365 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6366 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6367
79e53945
JB		 6368 for (i = 0; i < 256; i++) {
6369 I915_WRITE(palreg + 4 * i,
6370 (intel_crtc->lut_r[i] << 16) |
6371 (intel_crtc->lut_g[i] << 8) |
6372 intel_crtc->lut_b[i]);
6373 }
6374}
6375
560b85bb
CW		 6376static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6377{
6378 struct drm_device *dev = crtc->dev;
6379 struct drm_i915_private *dev_priv = dev->dev_private;
6380 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6381 bool visible = base != 0;
6382 u32 cntl;
6383
6384 if (intel_crtc->cursor_visible == visible)
6385 return;
6386
9db4a9c7 6387 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6388 if (visible) {
6389 /* On these chipsets we can only modify the base whilst
6390 * the cursor is disabled.
6391 */
9db4a9c7 6392 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6393
6394 cntl &= ~(CURSOR_FORMAT_MASK);
6395 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6396 cntl |= CURSOR_ENABLE |
6397 CURSOR_GAMMA_ENABLE |
6398 CURSOR_FORMAT_ARGB;
6399 } else
6400 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6401 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6402
6403 intel_crtc->cursor_visible = visible;
6404}
6405
6406static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6407{
6408 struct drm_device *dev = crtc->dev;
6409 struct drm_i915_private *dev_priv = dev->dev_private;
6410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6411 int pipe = intel_crtc->pipe;
6412 bool visible = base != 0;
6413
6414 if (intel_crtc->cursor_visible != visible) {
548f245b 6415 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6416 if (base) {
6417 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6418 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6419 cntl |= pipe << 28; /* Connect to correct pipe */
6420 } else {
6421 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6422 cntl |= CURSOR_MODE_DISABLE;
6423 }
9db4a9c7 6424 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6425
6426 intel_crtc->cursor_visible = visible;
6427 }
6428 /* and commit changes on next vblank */
9db4a9c7 6429 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6430}
6431
65a21cd6
JB		 6432static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6433{
6434 struct drm_device *dev = crtc->dev;
6435 struct drm_i915_private *dev_priv = dev->dev_private;
6436 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6437 int pipe = intel_crtc->pipe;
6438 bool visible = base != 0;
6439
6440 if (intel_crtc->cursor_visible != visible) {
6441 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6442 if (base) {
6443 cntl &= ~CURSOR_MODE;
6444 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6445 } else {
6446 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6447 cntl |= CURSOR_MODE_DISABLE;
6448 }
86d3efce
VS		 6449 if (IS_HASWELL(dev))
6450 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6451 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6452
6453 intel_crtc->cursor_visible = visible;
6454 }
6455 /* and commit changes on next vblank */
6456 I915_WRITE(CURBASE_IVB(pipe), base);
6457}
6458
cda4b7d3 6459/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6460static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6461 bool on)
cda4b7d3
CW		 6462{
6463 struct drm_device *dev = crtc->dev;
6464 struct drm_i915_private *dev_priv = dev->dev_private;
6465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6466 int pipe = intel_crtc->pipe;
6467 int x = intel_crtc->cursor_x;
6468 int y = intel_crtc->cursor_y;
560b85bb 6469 u32 base, pos;
cda4b7d3
CW		 6470 bool visible;
6471
6472 pos = 0;
6473
6b383a7f 6474 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6475 base = intel_crtc->cursor_addr;
6476 if (x > (int) crtc->fb->width)
6477 base = 0;
6478
6479 if (y > (int) crtc->fb->height)
6480 base = 0;
6481 } else
6482 base = 0;
6483
6484 if (x < 0) {
6485 if (x + intel_crtc->cursor_width < 0)
6486 base = 0;
6487
6488 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6489 x = -x;
6490 }
6491 pos |= x << CURSOR_X_SHIFT;
6492
6493 if (y < 0) {
6494 if (y + intel_crtc->cursor_height < 0)
6495 base = 0;
6496
6497 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6498 y = -y;
6499 }
6500 pos |= y << CURSOR_Y_SHIFT;
6501
6502 visible = base != 0;
560b85bb 6503 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6504 return;
6505
0cd83aa9 6506 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6507 I915_WRITE(CURPOS_IVB(pipe), pos);
6508 ivb_update_cursor(crtc, base);
6509 } else {
6510 I915_WRITE(CURPOS(pipe), pos);
6511 if (IS_845G(dev) || IS_I865G(dev))
6512 i845_update_cursor(crtc, base);
6513 else
6514 i9xx_update_cursor(crtc, base);
6515 }
cda4b7d3
CW		 6516}
6517
79e53945 6518static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6519 struct drm_file *file,
79e53945
JB		 6520 uint32_t handle,
6521 uint32_t width, uint32_t height)
6522{
6523 struct drm_device *dev = crtc->dev;
6524 struct drm_i915_private *dev_priv = dev->dev_private;
6525 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6526 struct drm_i915_gem_object *obj;
cda4b7d3 6527 uint32_t addr;
3f8bc370 6528 int ret;
79e53945 6529
79e53945
JB		 6530 /* if we want to turn off the cursor ignore width and height */
6531 if (!handle) {
28c97730 6532 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6533 addr = 0;
05394f39 6534 obj = NULL;
5004417d 6535 mutex_lock(&dev->struct_mutex);
3f8bc370 6536 goto finish;
79e53945
JB		 6537 }
6538
6539 /* Currently we only support 64x64 cursors */
6540 if (width != 64 || height != 64) {
6541 DRM_ERROR("we currently only support 64x64 cursors\n");
6542 return -EINVAL;
6543 }
6544
05394f39 6545 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6546 if (&obj->base == NULL)
79e53945
JB		 6547 return -ENOENT;
6548
05394f39 6549 if (obj->base.size < width * height * 4) {
79e53945 6550 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6551 ret = -ENOMEM;
6552 goto fail;
79e53945
JB		 6553 }
6554
71acb5eb 6555 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6556 mutex_lock(&dev->struct_mutex);
b295d1b6 6557 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6558 unsigned alignment;
6559
d9e86c0e
CW		 6560 if (obj->tiling_mode) {
6561 DRM_ERROR("cursor cannot be tiled\n");
6562 ret = -EINVAL;
6563 goto fail_locked;
6564 }
6565
693db184
CW		 6566 /* Note that the w/a also requires 2 PTE of padding following
6567 * the bo. We currently fill all unused PTE with the shadow
6568 * page and so we should always have valid PTE following the
6569 * cursor preventing the VT-d warning.
6570 */
6571 alignment = 0;
6572 if (need_vtd_wa(dev))
6573 alignment = 64*1024;
6574
6575 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6576 if (ret) {
6577 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6578 goto fail_locked;
e7b526bb
CW		 6579 }
6580
d9e86c0e
CW		 6581 ret = i915_gem_object_put_fence(obj);
6582 if (ret) {
2da3b9b9 6583 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6584 goto fail_unpin;
6585 }
6586
05394f39 6587 addr = obj->gtt_offset;
71acb5eb 6588 } else {
6eeefaf3 6589 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6590 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6591 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6592 align);
71acb5eb
DA		 6593 if (ret) {
6594 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6595 goto fail_locked;
71acb5eb 6596 }
05394f39 6597 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6598 }
6599
a6c45cf0 6600 if (IS_GEN2(dev))
14b60391
JB		 6601 I915_WRITE(CURSIZE, (height << 12) | width);
6602
3f8bc370 6603 finish:
3f8bc370 6604 if (intel_crtc->cursor_bo) {
b295d1b6 6605 if (dev_priv->info->cursor_needs_physical) {
05394f39 6606 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6607 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6608 } else
6609 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6610 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6611 }
80824003 6612
7f9872e0 6613 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6614
6615 intel_crtc->cursor_addr = addr;
05394f39 6616 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6617 intel_crtc->cursor_width = width;
6618 intel_crtc->cursor_height = height;
6619
6b383a7f 6620 intel_crtc_update_cursor(crtc, true);
3f8bc370 6621
79e53945 6622 return 0;
e7b526bb 6623fail_unpin:
05394f39 6624 i915_gem_object_unpin(obj);
7f9872e0 6625fail_locked:
34b8686e 6626 mutex_unlock(&dev->struct_mutex);
bc9025bd 6627fail:
05394f39 6628 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6629 return ret;
79e53945
JB		 6630}
6631
6632static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6633{
79e53945 6634 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6635
cda4b7d3
CW		 6636 intel_crtc->cursor_x = x;
6637 intel_crtc->cursor_y = y;
652c393a 6638
6b383a7f 6639 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6640
6641 return 0;
6642}
6643
6644/** Sets the color ramps on behalf of RandR */
6645void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6646 u16 blue, int regno)
6647{
6648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6649
6650 intel_crtc->lut_r[regno] = red >> 8;
6651 intel_crtc->lut_g[regno] = green >> 8;
6652 intel_crtc->lut_b[regno] = blue >> 8;
6653}
6654
b8c00ac5
DA		 6655void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6656 u16 *blue, int regno)
6657{
6658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6659
6660 *red = intel_crtc->lut_r[regno] << 8;
6661 *green = intel_crtc->lut_g[regno] << 8;
6662 *blue = intel_crtc->lut_b[regno] << 8;
6663}
6664
79e53945 6665static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6666 u16 *blue, uint32_t start, uint32_t size)
79e53945 6667{
7203425a 6668 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6669 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6670
7203425a 6671 for (i = start; i < end; i++) {
79e53945
JB		 6672 intel_crtc->lut_r[i] = red[i] >> 8;
6673 intel_crtc->lut_g[i] = green[i] >> 8;
6674 intel_crtc->lut_b[i] = blue[i] >> 8;
6675 }
6676
6677 intel_crtc_load_lut(crtc);
6678}
6679
79e53945
JB		 6680/* VESA 640x480x72Hz mode to set on the pipe */
6681static struct drm_display_mode load_detect_mode = {
6682 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6683 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6684};
6685
d2dff872
CW		 6686static struct drm_framebuffer *
6687intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6688 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6689 struct drm_i915_gem_object *obj)
6690{
6691 struct intel_framebuffer *intel_fb;
6692 int ret;
6693
6694 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6695 if (!intel_fb) {
6696 drm_gem_object_unreference_unlocked(&obj->base);
6697 return ERR_PTR(-ENOMEM);
6698 }
6699
6700 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6701 if (ret) {
6702 drm_gem_object_unreference_unlocked(&obj->base);
6703 kfree(intel_fb);
6704 return ERR_PTR(ret);
6705 }
6706
6707 return &intel_fb->base;
6708}
6709
6710static u32
6711intel_framebuffer_pitch_for_width(int width, int bpp)
6712{
6713 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6714 return ALIGN(pitch, 64);
6715}
6716
6717static u32
6718intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6719{
6720 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6721 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6722}
6723
6724static struct drm_framebuffer *
6725intel_framebuffer_create_for_mode(struct drm_device *dev,
6726 struct drm_display_mode *mode,
6727 int depth, int bpp)
6728{
6729 struct drm_i915_gem_object *obj;
0fed39bd 6730 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6731
6732 obj = i915_gem_alloc_object(dev,
6733 intel_framebuffer_size_for_mode(mode, bpp));
6734 if (obj == NULL)
6735 return ERR_PTR(-ENOMEM);
6736
6737 mode_cmd.width = mode->hdisplay;
6738 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6739 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6740 bpp);
5ca0c34a 6741 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6742
6743 return intel_framebuffer_create(dev, &mode_cmd, obj);
6744}
6745
6746static struct drm_framebuffer *
6747mode_fits_in_fbdev(struct drm_device *dev,
6748 struct drm_display_mode *mode)
6749{
6750 struct drm_i915_private *dev_priv = dev->dev_private;
6751 struct drm_i915_gem_object *obj;
6752 struct drm_framebuffer *fb;
6753
6754 if (dev_priv->fbdev == NULL)
6755 return NULL;
6756
6757 obj = dev_priv->fbdev->ifb.obj;
6758 if (obj == NULL)
6759 return NULL;
6760
6761 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6762 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6763 fb->bits_per_pixel))
d2dff872
CW		 6764 return NULL;
6765
01f2c773 6766 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6767 return NULL;
6768
6769 return fb;
6770}
6771
d2434ab7 6772bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6773 struct drm_display_mode *mode,
8261b191 6774 struct intel_load_detect_pipe *old)
79e53945
JB		 6775{
6776 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6777 struct intel_encoder *intel_encoder =
6778 intel_attached_encoder(connector);
79e53945 6779 struct drm_crtc *possible_crtc;
4ef69c7a 6780 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6781 struct drm_crtc *crtc = NULL;
6782 struct drm_device *dev = encoder->dev;
94352cf9 6783 struct drm_framebuffer *fb;
79e53945
JB		 6784 int i = -1;
6785
d2dff872
CW		 6786 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6787 connector->base.id, drm_get_connector_name(connector),
6788 encoder->base.id, drm_get_encoder_name(encoder));
6789
79e53945
JB		 6790 /*
6791 * Algorithm gets a little messy:
7a5e4805 6792 *
79e53945
JB		 6793 * - if the connector already has an assigned crtc, use it (but make
6794 * sure it's on first)
7a5e4805 6795 *
79e53945
JB		 6796 * - try to find the first unused crtc that can drive this connector,
6797 * and use that if we find one
79e53945
JB		 6798 */
6799
6800 /* See if we already have a CRTC for this connector */
6801 if (encoder->crtc) {
6802 crtc = encoder->crtc;
8261b191 6803
7b24056b
DV		 6804 mutex_lock(&crtc->mutex);
6805
24218aac 6806 old->dpms_mode = connector->dpms;
8261b191
CW		 6807 old->load_detect_temp = false;
6808
6809 /* Make sure the crtc and connector are running */
24218aac
DV		 6810 if (connector->dpms != DRM_MODE_DPMS_ON)
6811 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6812
7173188d 6813 return true;
79e53945
JB		 6814 }
6815
6816 /* Find an unused one (if possible) */
6817 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6818 i++;
6819 if (!(encoder->possible_crtcs & (1 << i)))
6820 continue;
6821 if (!possible_crtc->enabled) {
6822 crtc = possible_crtc;
6823 break;
6824 }
79e53945
JB		 6825 }
6826
6827 /*
6828 * If we didn't find an unused CRTC, don't use any.
6829 */
6830 if (!crtc) {
7173188d
CW		 6831 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6832 return false;
79e53945
JB		 6833 }
6834
7b24056b 6835 mutex_lock(&crtc->mutex);
fc303101
DV		 6836 intel_encoder->new_crtc = to_intel_crtc(crtc);
6837 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6838
6839 intel_crtc = to_intel_crtc(crtc);
24218aac 6840 old->dpms_mode = connector->dpms;
8261b191 6841 old->load_detect_temp = true;
d2dff872 6842 old->release_fb = NULL;
79e53945 6843
6492711d
CW		 6844 if (!mode)
6845 mode = &load_detect_mode;
79e53945 6846
d2dff872
CW		 6847 /* We need a framebuffer large enough to accommodate all accesses
6848 * that the plane may generate whilst we perform load detection.
6849 * We can not rely on the fbcon either being present (we get called
6850 * during its initialisation to detect all boot displays, or it may
6851 * not even exist) or that it is large enough to satisfy the
6852 * requested mode.
6853 */
94352cf9
DV		 6854 fb = mode_fits_in_fbdev(dev, mode);
6855 if (fb == NULL) {
d2dff872 6856 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6857 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6858 old->release_fb = fb;
d2dff872
CW		 6859 } else
6860 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6861 if (IS_ERR(fb)) {
d2dff872 6862 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6863 mutex_unlock(&crtc->mutex);
0e8b3d3e 6864 return false;
79e53945 6865 }
79e53945 6866
c0c36b94 6867 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6868 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6869 if (old->release_fb)
6870 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6871 mutex_unlock(&crtc->mutex);
0e8b3d3e 6872 return false;
79e53945 6873 }
7173188d 6874
79e53945 6875 /* let the connector get through one full cycle before testing */
9d0498a2 6876 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6877 return true;
79e53945
JB		 6878}
6879
d2434ab7 6880void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6881 struct intel_load_detect_pipe *old)
79e53945 6882{
d2434ab7
DV		 6883 struct intel_encoder *intel_encoder =
6884 intel_attached_encoder(connector);
4ef69c7a 6885 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6886 struct drm_crtc *crtc = encoder->crtc;
79e53945 6887
d2dff872
CW		 6888 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6889 connector->base.id, drm_get_connector_name(connector),
6890 encoder->base.id, drm_get_encoder_name(encoder));
6891
8261b191 6892 if (old->load_detect_temp) {
fc303101
DV		 6893 to_intel_connector(connector)->new_encoder = NULL;
6894 intel_encoder->new_crtc = NULL;
6895 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6896
36206361
DV		 6897 if (old->release_fb) {
6898 drm_framebuffer_unregister_private(old->release_fb);
6899 drm_framebuffer_unreference(old->release_fb);
6900 }
d2dff872 6901
67c96400 6902 mutex_unlock(&crtc->mutex);
0622a53c 6903 return;
79e53945
JB		 6904 }
6905
c751ce4f 6906 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6907 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6908 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6909
6910 mutex_unlock(&crtc->mutex);
79e53945
JB		 6911}
6912
6913/* Returns the clock of the currently programmed mode of the given pipe. */
6914static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6915{
6916 struct drm_i915_private *dev_priv = dev->dev_private;
6917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6918 int pipe = intel_crtc->pipe;
548f245b 6919 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6920 u32 fp;
6921 intel_clock_t clock;
6922
6923 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6924 fp = I915_READ(FP0(pipe));
79e53945 6925 else
39adb7a5 6926 fp = I915_READ(FP1(pipe));
79e53945
JB		 6927
6928 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6929 if (IS_PINEVIEW(dev)) {
6930 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6931 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6932 } else {
6933 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6934 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6935 }
6936
a6c45cf0 6937 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6938 if (IS_PINEVIEW(dev))
6939 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6940 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6941 else
6942 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6943 DPLL_FPA01_P1_POST_DIV_SHIFT);
6944
6945 switch (dpll & DPLL_MODE_MASK) {
6946 case DPLLB_MODE_DAC_SERIAL:
6947 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6948 5 : 10;
6949 break;
6950 case DPLLB_MODE_LVDS:
6951 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6952 7 : 14;
6953 break;
6954 default:
28c97730 6955 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6956 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6957 return 0;
6958 }
6959
6960 /* XXX: Handle the 100Mhz refclk */
2177832f 6961 intel_clock(dev, 96000, &clock);
79e53945
JB		 6962 } else {
6963 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6964
6965 if (is_lvds) {
6966 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6967 DPLL_FPA01_P1_POST_DIV_SHIFT);
6968 clock.p2 = 14;
6969
6970 if ((dpll & PLL_REF_INPUT_MASK) ==
6971 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6972 /* XXX: might not be 66MHz */
2177832f 6973 intel_clock(dev, 66000, &clock);
79e53945 6974 } else
2177832f 6975 intel_clock(dev, 48000, &clock);
79e53945
JB		 6976 } else {
6977 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6978 clock.p1 = 2;
6979 else {
6980 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6981 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6982 }
6983 if (dpll & PLL_P2_DIVIDE_BY_4)
6984 clock.p2 = 4;
6985 else
6986 clock.p2 = 2;
6987
2177832f 6988 intel_clock(dev, 48000, &clock);
79e53945
JB		 6989 }
6990 }
6991
6992 /* XXX: It would be nice to validate the clocks, but we can't reuse
6993 * i830PllIsValid() because it relies on the xf86_config connector
6994 * configuration being accurate, which it isn't necessarily.
6995 */
6996
6997 return clock.dot;
6998}
6999
7000/** Returns the currently programmed mode of the given pipe. */
7001struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7002 struct drm_crtc *crtc)
7003{
548f245b 7004 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7006 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7007 struct drm_display_mode *mode;
fe2b8f9d
PZ		 7008 int htot = I915_READ(HTOTAL(cpu_transcoder));
7009 int hsync = I915_READ(HSYNC(cpu_transcoder));
7010 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7011 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 7012
7013 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7014 if (!mode)
7015 return NULL;
7016
7017 mode->clock = intel_crtc_clock_get(dev, crtc);
7018 mode->hdisplay = (htot & 0xffff) + 1;
7019 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7020 mode->hsync_start = (hsync & 0xffff) + 1;
7021 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7022 mode->vdisplay = (vtot & 0xffff) + 1;
7023 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7024 mode->vsync_start = (vsync & 0xffff) + 1;
7025 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7026
7027 drm_mode_set_name(mode);
79e53945
JB		 7028
7029 return mode;
7030}
7031
3dec0095 7032static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7033{
7034 struct drm_device *dev = crtc->dev;
7035 drm_i915_private_t *dev_priv = dev->dev_private;
7036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7037 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7038 int dpll_reg = DPLL(pipe);
7039 int dpll;
652c393a 7040
bad720ff 7041 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7042 return;
7043
7044 if (!dev_priv->lvds_downclock_avail)
7045 return;
7046
dbdc6479 7047 dpll = I915_READ(dpll_reg);
652c393a 7048 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7049 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7050
8ac5a6d5 7051 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7052
7053 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7054 I915_WRITE(dpll_reg, dpll);
9d0498a2 7055 intel_wait_for_vblank(dev, pipe);
dbdc6479 7056
652c393a
JB		 7057 dpll = I915_READ(dpll_reg);
7058 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7059 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7060 }
652c393a
JB		 7061}
7062
7063static void intel_decrease_pllclock(struct drm_crtc *crtc)
7064{
7065 struct drm_device *dev = crtc->dev;
7066 drm_i915_private_t *dev_priv = dev->dev_private;
7067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7068
bad720ff 7069 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7070 return;
7071
7072 if (!dev_priv->lvds_downclock_avail)
7073 return;
7074
7075 /*
7076 * Since this is called by a timer, we should never get here in
7077 * the manual case.
7078 */
7079 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7080 int pipe = intel_crtc->pipe;
7081 int dpll_reg = DPLL(pipe);
7082 int dpll;
f6e5b160 7083
44d98a61 7084 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7085
8ac5a6d5 7086 assert_panel_unlocked(dev_priv, pipe);
652c393a 7087
dc257cf1 7088 dpll = I915_READ(dpll_reg);
652c393a
JB		 7089 dpll |= DISPLAY_RATE_SELECT_FPA1;
7090 I915_WRITE(dpll_reg, dpll);
9d0498a2 7091 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7092 dpll = I915_READ(dpll_reg);
7093 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7094 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7095 }
7096
7097}
7098
f047e395
CW		 7099void intel_mark_busy(struct drm_device *dev)
7100{
f047e395
CW		 7101 i915_update_gfx_val(dev->dev_private);
7102}
7103
7104void intel_mark_idle(struct drm_device *dev)
652c393a 7105{
652c393a 7106 struct drm_crtc *crtc;
652c393a
JB		 7107
7108 if (!i915_powersave)
7109 return;
7110
652c393a 7111 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7112 if (!crtc->fb)
7113 continue;
7114
725a5b54 7115 intel_decrease_pllclock(crtc);
652c393a 7116 }
652c393a
JB		 7117}
7118
725a5b54 7119void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 7120{
f047e395
CW		 7121 struct drm_device *dev = obj->base.dev;
7122 struct drm_crtc *crtc;
652c393a 7123
f047e395 7124 if (!i915_powersave)
acb87dfb
CW		 7125 return;
7126
652c393a
JB		 7127 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7128 if (!crtc->fb)
7129 continue;
7130
f047e395 7131 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 7132 intel_increase_pllclock(crtc);
652c393a
JB		 7133 }
7134}
7135
79e53945
JB		 7136static void intel_crtc_destroy(struct drm_crtc *crtc)
7137{
7138 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7139 struct drm_device *dev = crtc->dev;
7140 struct intel_unpin_work *work;
7141 unsigned long flags;
7142
7143 spin_lock_irqsave(&dev->event_lock, flags);
7144 work = intel_crtc->unpin_work;
7145 intel_crtc->unpin_work = NULL;
7146 spin_unlock_irqrestore(&dev->event_lock, flags);
7147
7148 if (work) {
7149 cancel_work_sync(&work->work);
7150 kfree(work);
7151 }
79e53945
JB		 7152
7153 drm_crtc_cleanup(crtc);
67e77c5a 7154
79e53945
JB		 7155 kfree(intel_crtc);
7156}
7157
6b95a207
KH		 7158static void intel_unpin_work_fn(struct work_struct *__work)
7159{
7160 struct intel_unpin_work *work =
7161 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7162 struct drm_device *dev = work->crtc->dev;
6b95a207 7163
b4a98e57 7164 mutex_lock(&dev->struct_mutex);
1690e1eb 7165 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7166 drm_gem_object_unreference(&work->pending_flip_obj->base);
7167 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7168
b4a98e57
CW		 7169 intel_update_fbc(dev);
7170 mutex_unlock(&dev->struct_mutex);
7171
7172 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7173 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7174
6b95a207
KH		 7175 kfree(work);
7176}
7177
1afe3e9d 7178static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7179 struct drm_crtc *crtc)
6b95a207
KH		 7180{
7181 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7183 struct intel_unpin_work *work;
6b95a207
KH		 7184 unsigned long flags;
7185
7186 /* Ignore early vblank irqs */
7187 if (intel_crtc == NULL)
7188 return;
7189
7190 spin_lock_irqsave(&dev->event_lock, flags);
7191 work = intel_crtc->unpin_work;
e7d841ca
CW		 7192
7193 /* Ensure we don't miss a work->pending update ... */
7194 smp_rmb();
7195
7196 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7197 spin_unlock_irqrestore(&dev->event_lock, flags);
7198 return;
7199 }
7200
e7d841ca
CW		 7201 /* and that the unpin work is consistent wrt ->pending. */
7202 smp_rmb();
7203
6b95a207 7204 intel_crtc->unpin_work = NULL;
6b95a207 7205
45a066eb
RC		 7206 if (work->event)
7207 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7208
0af7e4df
MK		 7209 drm_vblank_put(dev, intel_crtc->pipe);
7210
6b95a207
KH		 7211 spin_unlock_irqrestore(&dev->event_lock, flags);
7212
2c10d571 7213 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7214
7215 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7216
7217 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7218}
7219
1afe3e9d
JB		 7220void intel_finish_page_flip(struct drm_device *dev, int pipe)
7221{
7222 drm_i915_private_t *dev_priv = dev->dev_private;
7223 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7224
49b14a5c 7225 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7226}
7227
7228void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7229{
7230 drm_i915_private_t *dev_priv = dev->dev_private;
7231 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7232
49b14a5c 7233 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7234}
7235
6b95a207
KH		 7236void intel_prepare_page_flip(struct drm_device *dev, int plane)
7237{
7238 drm_i915_private_t *dev_priv = dev->dev_private;
7239 struct intel_crtc *intel_crtc =
7240 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7241 unsigned long flags;
7242
e7d841ca
CW		 7243 /* NB: An MMIO update of the plane base pointer will also
7244 * generate a page-flip completion irq, i.e. every modeset
7245 * is also accompanied by a spurious intel_prepare_page_flip().
7246 */
6b95a207 7247 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7248 if (intel_crtc->unpin_work)
7249 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7250 spin_unlock_irqrestore(&dev->event_lock, flags);
7251}
7252
e7d841ca
CW		 7253inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7254{
7255 /* Ensure that the work item is consistent when activating it ... */
7256 smp_wmb();
7257 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7258 /* and that it is marked active as soon as the irq could fire. */
7259 smp_wmb();
7260}
7261
8c9f3aaf
JB		 7262static int intel_gen2_queue_flip(struct drm_device *dev,
7263 struct drm_crtc *crtc,
7264 struct drm_framebuffer *fb,
7265 struct drm_i915_gem_object *obj)
7266{
7267 struct drm_i915_private *dev_priv = dev->dev_private;
7268 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7269 u32 flip_mask;
6d90c952 7270 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7271 int ret;
7272
6d90c952 7273 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7274 if (ret)
83d4092b 7275 goto err;
8c9f3aaf 7276
6d90c952 7277 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7278 if (ret)
83d4092b 7279 goto err_unpin;
8c9f3aaf
JB		 7280
7281 /* Can't queue multiple flips, so wait for the previous
7282 * one to finish before executing the next.
7283 */
7284 if (intel_crtc->plane)
7285 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7286 else
7287 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7288 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7289 intel_ring_emit(ring, MI_NOOP);
7290 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7291 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7292 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7293 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7294 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7295
7296 intel_mark_page_flip_active(intel_crtc);
6d90c952 7297 intel_ring_advance(ring);
83d4092b
CW		 7298 return 0;
7299
7300err_unpin:
7301 intel_unpin_fb_obj(obj);
7302err:
8c9f3aaf
JB		 7303 return ret;
7304}
7305
7306static int intel_gen3_queue_flip(struct drm_device *dev,
7307 struct drm_crtc *crtc,
7308 struct drm_framebuffer *fb,
7309 struct drm_i915_gem_object *obj)
7310{
7311 struct drm_i915_private *dev_priv = dev->dev_private;
7312 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7313 u32 flip_mask;
6d90c952 7314 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7315 int ret;
7316
6d90c952 7317 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7318 if (ret)
83d4092b 7319 goto err;
8c9f3aaf 7320
6d90c952 7321 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7322 if (ret)
83d4092b 7323 goto err_unpin;
8c9f3aaf
JB		 7324
7325 if (intel_crtc->plane)
7326 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7327 else
7328 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7329 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7330 intel_ring_emit(ring, MI_NOOP);
7331 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7332 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7333 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7334 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7335 intel_ring_emit(ring, MI_NOOP);
7336
e7d841ca 7337 intel_mark_page_flip_active(intel_crtc);
6d90c952 7338 intel_ring_advance(ring);
83d4092b
CW		 7339 return 0;
7340
7341err_unpin:
7342 intel_unpin_fb_obj(obj);
7343err:
8c9f3aaf
JB		 7344 return ret;
7345}
7346
7347static int intel_gen4_queue_flip(struct drm_device *dev,
7348 struct drm_crtc *crtc,
7349 struct drm_framebuffer *fb,
7350 struct drm_i915_gem_object *obj)
7351{
7352 struct drm_i915_private *dev_priv = dev->dev_private;
7353 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7354 uint32_t pf, pipesrc;
6d90c952 7355 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7356 int ret;
7357
6d90c952 7358 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7359 if (ret)
83d4092b 7360 goto err;
8c9f3aaf 7361
6d90c952 7362 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7363 if (ret)
83d4092b 7364 goto err_unpin;
8c9f3aaf
JB		 7365
7366 /* i965+ uses the linear or tiled offsets from the
7367 * Display Registers (which do not change across a page-flip)
7368 * so we need only reprogram the base address.
7369 */
6d90c952
DV		 7370 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7371 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7372 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7373 intel_ring_emit(ring,
7374 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7375 obj->tiling_mode);
8c9f3aaf
JB		 7376
7377 /* XXX Enabling the panel-fitter across page-flip is so far
7378 * untested on non-native modes, so ignore it for now.
7379 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7380 */
7381 pf = 0;
7382 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7383 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7384
7385 intel_mark_page_flip_active(intel_crtc);
6d90c952 7386 intel_ring_advance(ring);
83d4092b
CW		 7387 return 0;
7388
7389err_unpin:
7390 intel_unpin_fb_obj(obj);
7391err:
8c9f3aaf
JB		 7392 return ret;
7393}
7394
7395static int intel_gen6_queue_flip(struct drm_device *dev,
7396 struct drm_crtc *crtc,
7397 struct drm_framebuffer *fb,
7398 struct drm_i915_gem_object *obj)
7399{
7400 struct drm_i915_private *dev_priv = dev->dev_private;
7401 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7402 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7403 uint32_t pf, pipesrc;
7404 int ret;
7405
6d90c952 7406 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7407 if (ret)
83d4092b 7408 goto err;
8c9f3aaf 7409
6d90c952 7410 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7411 if (ret)
83d4092b 7412 goto err_unpin;
8c9f3aaf 7413
6d90c952
DV		 7414 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7415 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7416 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7417 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7418
dc257cf1
DV		 7419 /* Contrary to the suggestions in the documentation,
7420 * "Enable Panel Fitter" does not seem to be required when page
7421 * flipping with a non-native mode, and worse causes a normal
7422 * modeset to fail.
7423 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7424 */
7425 pf = 0;
8c9f3aaf 7426 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7427 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7428
7429 intel_mark_page_flip_active(intel_crtc);
6d90c952 7430 intel_ring_advance(ring);
83d4092b
CW		 7431 return 0;
7432
7433err_unpin:
7434 intel_unpin_fb_obj(obj);
7435err:
8c9f3aaf
JB		 7436 return ret;
7437}
7438
7c9017e5
JB		 7439/*
7440 * On gen7 we currently use the blit ring because (in early silicon at least)
7441 * the render ring doesn't give us interrpts for page flip completion, which
7442 * means clients will hang after the first flip is queued. Fortunately the
7443 * blit ring generates interrupts properly, so use it instead.
7444 */
7445static int intel_gen7_queue_flip(struct drm_device *dev,
7446 struct drm_crtc *crtc,
7447 struct drm_framebuffer *fb,
7448 struct drm_i915_gem_object *obj)
7449{
7450 struct drm_i915_private *dev_priv = dev->dev_private;
7451 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7452 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7453 uint32_t plane_bit = 0;
7c9017e5
JB		 7454 int ret;
7455
7456 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7457 if (ret)
83d4092b 7458 goto err;
7c9017e5 7459
cb05d8de
DV		 7460 switch(intel_crtc->plane) {
7461 case PLANE_A:
7462 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7463 break;
7464 case PLANE_B:
7465 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7466 break;
7467 case PLANE_C:
7468 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7469 break;
7470 default:
7471 WARN_ONCE(1, "unknown plane in flip command\n");
7472 ret = -ENODEV;
ab3951eb 7473 goto err_unpin;
cb05d8de
DV		 7474 }
7475
7c9017e5
JB		 7476 ret = intel_ring_begin(ring, 4);
7477 if (ret)
83d4092b 7478 goto err_unpin;
7c9017e5 7479
cb05d8de 7480 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7481 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7482 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7483 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7484
7485 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7486 intel_ring_advance(ring);
83d4092b
CW		 7487 return 0;
7488
7489err_unpin:
7490 intel_unpin_fb_obj(obj);
7491err:
7c9017e5
JB		 7492 return ret;
7493}
7494
8c9f3aaf
JB		 7495static int intel_default_queue_flip(struct drm_device *dev,
7496 struct drm_crtc *crtc,
7497 struct drm_framebuffer *fb,
7498 struct drm_i915_gem_object *obj)
7499{
7500 return -ENODEV;
7501}
7502
6b95a207
KH		 7503static int intel_crtc_page_flip(struct drm_crtc *crtc,
7504 struct drm_framebuffer *fb,
7505 struct drm_pending_vblank_event *event)
7506{
7507 struct drm_device *dev = crtc->dev;
7508 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7509 struct drm_framebuffer *old_fb = crtc->fb;
7510 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7511 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7512 struct intel_unpin_work *work;
8c9f3aaf 7513 unsigned long flags;
52e68630 7514 int ret;
6b95a207 7515
e6a595d2
VS		 7516 /* Can't change pixel format via MI display flips. */
7517 if (fb->pixel_format != crtc->fb->pixel_format)
7518 return -EINVAL;
7519
7520 /*
7521 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7522 * Note that pitch changes could also affect these register.
7523 */
7524 if (INTEL_INFO(dev)->gen > 3 &&
7525 (fb->offsets[0] != crtc->fb->offsets[0] ||
7526 fb->pitches[0] != crtc->fb->pitches[0]))
7527 return -EINVAL;
7528
6b95a207
KH		 7529 work = kzalloc(sizeof *work, GFP_KERNEL);
7530 if (work == NULL)
7531 return -ENOMEM;
7532
6b95a207 7533 work->event = event;
b4a98e57 7534 work->crtc = crtc;
4a35f83b 7535 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7536 INIT_WORK(&work->work, intel_unpin_work_fn);
7537
7317c75e
JB		 7538 ret = drm_vblank_get(dev, intel_crtc->pipe);
7539 if (ret)
7540 goto free_work;
7541
6b95a207
KH		 7542 /* We borrow the event spin lock for protecting unpin_work */
7543 spin_lock_irqsave(&dev->event_lock, flags);
7544 if (intel_crtc->unpin_work) {
7545 spin_unlock_irqrestore(&dev->event_lock, flags);
7546 kfree(work);
7317c75e 7547 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7548
7549 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7550 return -EBUSY;
7551 }
7552 intel_crtc->unpin_work = work;
7553 spin_unlock_irqrestore(&dev->event_lock, flags);
7554
b4a98e57
CW		 7555 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7556 flush_workqueue(dev_priv->wq);
7557
79158103
CW		 7558 ret = i915_mutex_lock_interruptible(dev);
7559 if (ret)
7560 goto cleanup;
6b95a207 7561
75dfca80 7562 /* Reference the objects for the scheduled work. */
05394f39
CW		 7563 drm_gem_object_reference(&work->old_fb_obj->base);
7564 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7565
7566 crtc->fb = fb;
96b099fd 7567
e1f99ce6 7568 work->pending_flip_obj = obj;
e1f99ce6 7569
4e5359cd
SF		 7570 work->enable_stall_check = true;
7571
b4a98e57 7572 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7573 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7574
8c9f3aaf
JB		 7575 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7576 if (ret)
7577 goto cleanup_pending;
6b95a207 7578
7782de3b 7579 intel_disable_fbc(dev);
f047e395 7580 intel_mark_fb_busy(obj);
6b95a207
KH		 7581 mutex_unlock(&dev->struct_mutex);
7582
e5510fac
JB		 7583 trace_i915_flip_request(intel_crtc->plane, obj);
7584
6b95a207 7585 return 0;
96b099fd 7586
8c9f3aaf 7587cleanup_pending:
b4a98e57 7588 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7589 crtc->fb = old_fb;
05394f39
CW		 7590 drm_gem_object_unreference(&work->old_fb_obj->base);
7591 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7592 mutex_unlock(&dev->struct_mutex);
7593
79158103 7594cleanup:
96b099fd
CW		 7595 spin_lock_irqsave(&dev->event_lock, flags);
7596 intel_crtc->unpin_work = NULL;
7597 spin_unlock_irqrestore(&dev->event_lock, flags);
7598
7317c75e
JB		 7599 drm_vblank_put(dev, intel_crtc->pipe);
7600free_work:
96b099fd
CW		 7601 kfree(work);
7602
7603 return ret;
6b95a207
KH		 7604}
7605
f6e5b160 7606static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7607 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7608 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7609};
7610
6ed0f796 7611bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7612{
6ed0f796
DV		 7613 struct intel_encoder *other_encoder;
7614 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7615
6ed0f796
DV		 7616 if (WARN_ON(!crtc))
7617 return false;
7618
7619 list_for_each_entry(other_encoder,
7620 &crtc->dev->mode_config.encoder_list,
7621 base.head) {
7622
7623 if (&other_encoder->new_crtc->base != crtc ||
7624 encoder == other_encoder)
7625 continue;
7626 else
7627 return true;
f47166d2
CW		 7628 }
7629
6ed0f796
DV		 7630 return false;
7631}
47f1c6c9 7632
50f56119
DV		 7633static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7634 struct drm_crtc *crtc)
7635{
7636 struct drm_device *dev;
7637 struct drm_crtc *tmp;
7638 int crtc_mask = 1;
47f1c6c9 7639
50f56119 7640 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7641
50f56119 7642 dev = crtc->dev;
47f1c6c9 7643
50f56119
DV		 7644 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7645 if (tmp == crtc)
7646 break;
7647 crtc_mask <<= 1;
7648 }
47f1c6c9 7649
50f56119
DV		 7650 if (encoder->possible_crtcs & crtc_mask)
7651 return true;
7652 return false;
47f1c6c9 7653}
79e53945 7654
9a935856
DV		 7655/**
7656 * intel_modeset_update_staged_output_state
7657 *
7658 * Updates the staged output configuration state, e.g. after we've read out the
7659 * current hw state.
7660 */
7661static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7662{
9a935856
DV		 7663 struct intel_encoder *encoder;
7664 struct intel_connector *connector;
f6e5b160 7665
9a935856
DV		 7666 list_for_each_entry(connector, &dev->mode_config.connector_list,
7667 base.head) {
7668 connector->new_encoder =
7669 to_intel_encoder(connector->base.encoder);
7670 }
f6e5b160 7671
9a935856
DV		 7672 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7673 base.head) {
7674 encoder->new_crtc =
7675 to_intel_crtc(encoder->base.crtc);
7676 }
f6e5b160
CW		 7677}
7678
9a935856
DV		 7679/**
7680 * intel_modeset_commit_output_state
7681 *
7682 * This function copies the stage display pipe configuration to the real one.
7683 */
7684static void intel_modeset_commit_output_state(struct drm_device *dev)
7685{
7686 struct intel_encoder *encoder;
7687 struct intel_connector *connector;
f6e5b160 7688
9a935856
DV		 7689 list_for_each_entry(connector, &dev->mode_config.connector_list,
7690 base.head) {
7691 connector->base.encoder = &connector->new_encoder->base;
7692 }
f6e5b160 7693
9a935856
DV		 7694 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7695 base.head) {
7696 encoder->base.crtc = &encoder->new_crtc->base;
7697 }
7698}
7699
4e53c2e0
DV		 7700static int
7701pipe_config_set_bpp(struct drm_crtc *crtc,
7702 struct drm_framebuffer *fb,
7703 struct intel_crtc_config *pipe_config)
7704{
7705 struct drm_device *dev = crtc->dev;
7706 struct drm_connector *connector;
7707 int bpp;
7708
d42264b1
DV		 7709 switch (fb->pixel_format) {
7710 case DRM_FORMAT_C8:
4e53c2e0
DV		 7711 bpp = 8*3; /* since we go through a colormap */
7712 break;
d42264b1
DV		 7713 case DRM_FORMAT_XRGB1555:
7714 case DRM_FORMAT_ARGB1555:
7715 /* checked in intel_framebuffer_init already */
7716 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7717 return -EINVAL;
7718 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7719 bpp = 6*3; /* min is 18bpp */
7720 break;
d42264b1
DV		 7721 case DRM_FORMAT_XBGR8888:
7722 case DRM_FORMAT_ABGR8888:
7723 /* checked in intel_framebuffer_init already */
7724 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7725 return -EINVAL;
7726 case DRM_FORMAT_XRGB8888:
7727 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7728 bpp = 8*3;
7729 break;
d42264b1
DV		 7730 case DRM_FORMAT_XRGB2101010:
7731 case DRM_FORMAT_ARGB2101010:
7732 case DRM_FORMAT_XBGR2101010:
7733 case DRM_FORMAT_ABGR2101010:
7734 /* checked in intel_framebuffer_init already */
7735 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7736 return -EINVAL;
4e53c2e0
DV		 7737 bpp = 10*3;
7738 break;
baba133a 7739 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7740 default:
7741 DRM_DEBUG_KMS("unsupported depth\n");
7742 return -EINVAL;
7743 }
7744
4e53c2e0
DV		 7745 pipe_config->pipe_bpp = bpp;
7746
7747 /* Clamp display bpp to EDID value */
7748 list_for_each_entry(connector, &dev->mode_config.connector_list,
7749 head) {
7750 if (connector->encoder && connector->encoder->crtc != crtc)
7751 continue;
7752
7753 /* Don't use an invalid EDID bpc value */
7754 if (connector->display_info.bpc &&
7755 connector->display_info.bpc * 3 < bpp) {
7756 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7757 bpp, connector->display_info.bpc*3);
7758 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7759 }
996a2239
DV		 7760
7761 /* Clamp bpp to 8 on screens without EDID 1.4 */
7762 if (connector->display_info.bpc == 0 && bpp > 24) {
7763 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7764 bpp);
7765 pipe_config->pipe_bpp = 24;
7766 }
4e53c2e0
DV		 7767 }
7768
7769 return bpp;
7770}
7771
b8cecdf5
DV		 7772static struct intel_crtc_config *
7773intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7774 struct drm_framebuffer *fb,
b8cecdf5 7775 struct drm_display_mode *mode)
ee7b9f93 7776{
7758a113 7777 struct drm_device *dev = crtc->dev;
7758a113
DV		 7778 struct drm_encoder_helper_funcs *encoder_funcs;
7779 struct intel_encoder *encoder;
b8cecdf5 7780 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7781 int plane_bpp, ret = -EINVAL;
7782 bool retry = true;
ee7b9f93 7783
b8cecdf5
DV		 7784 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7785 if (!pipe_config)
7758a113
DV		 7786 return ERR_PTR(-ENOMEM);
7787
b8cecdf5
DV		 7788 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7789 drm_mode_copy(&pipe_config->requested_mode, mode);
7790
4e53c2e0
DV		 7791 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7792 if (plane_bpp < 0)
7793 goto fail;
7794
e29c22c0 7795encoder_retry:
7758a113
DV		 7796 /* Pass our mode to the connectors and the CRTC to give them a chance to
7797 * adjust it according to limitations or connector properties, and also
7798 * a chance to reject the mode entirely.
47f1c6c9 7799 */
7758a113
DV		 7800 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7801 base.head) {
47f1c6c9 7802
7758a113
DV		 7803 if (&encoder->new_crtc->base != crtc)
7804 continue;
7ae89233
DV		 7805
7806 if (encoder->compute_config) {
7807 if (!(encoder->compute_config(encoder, pipe_config))) {
7808 DRM_DEBUG_KMS("Encoder config failure\n");
7809 goto fail;
7810 }
7811
7812 continue;
7813 }
7814
7758a113 7815 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7816 if (!(encoder_funcs->mode_fixup(&encoder->base,
7817 &pipe_config->requested_mode,
7818 &pipe_config->adjusted_mode))) {
7758a113
DV		 7819 DRM_DEBUG_KMS("Encoder fixup failed\n");
7820 goto fail;
7821 }
ee7b9f93 7822 }
47f1c6c9 7823
e29c22c0
DV		 7824 ret = intel_crtc_compute_config(crtc, pipe_config);
7825 if (ret < 0) {
7758a113
DV		 7826 DRM_DEBUG_KMS("CRTC fixup failed\n");
7827 goto fail;
ee7b9f93 7828 }
e29c22c0
DV		 7829
7830 if (ret == RETRY) {
7831 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7832 ret = -EINVAL;
7833 goto fail;
7834 }
7835
7836 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7837 retry = false;
7838 goto encoder_retry;
7839 }
7840
7758a113 7841 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7842
4e53c2e0
DV		 7843 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7844 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7845 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7846
b8cecdf5 7847 return pipe_config;
7758a113 7848fail:
b8cecdf5 7849 kfree(pipe_config);
e29c22c0 7850 return ERR_PTR(ret);
ee7b9f93 7851}
47f1c6c9 7852
e2e1ed41
DV		 7853/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7854 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7855static void
7856intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7857 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7858{
7859 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7860 struct drm_device *dev = crtc->dev;
7861 struct intel_encoder *encoder;
7862 struct intel_connector *connector;
7863 struct drm_crtc *tmp_crtc;
79e53945 7864
e2e1ed41 7865 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7866
e2e1ed41
DV		 7867 /* Check which crtcs have changed outputs connected to them, these need
7868 * to be part of the prepare_pipes mask. We don't (yet) support global
7869 * modeset across multiple crtcs, so modeset_pipes will only have one
7870 * bit set at most. */
7871 list_for_each_entry(connector, &dev->mode_config.connector_list,
7872 base.head) {
7873 if (connector->base.encoder == &connector->new_encoder->base)
7874 continue;
79e53945 7875
e2e1ed41
DV		 7876 if (connector->base.encoder) {
7877 tmp_crtc = connector->base.encoder->crtc;
7878
7879 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7880 }
7881
7882 if (connector->new_encoder)
7883 *prepare_pipes |=
7884 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7885 }
7886
e2e1ed41
DV		 7887 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7888 base.head) {
7889 if (encoder->base.crtc == &encoder->new_crtc->base)
7890 continue;
7891
7892 if (encoder->base.crtc) {
7893 tmp_crtc = encoder->base.crtc;
7894
7895 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7896 }
7897
7898 if (encoder->new_crtc)
7899 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7900 }
7901
e2e1ed41
DV		 7902 /* Check for any pipes that will be fully disabled ... */
7903 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7904 base.head) {
7905 bool used = false;
22fd0fab 7906
e2e1ed41
DV		 7907 /* Don't try to disable disabled crtcs. */
7908 if (!intel_crtc->base.enabled)
7909 continue;
7e7d76c3 7910
e2e1ed41
DV		 7911 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7912 base.head) {
7913 if (encoder->new_crtc == intel_crtc)
7914 used = true;
7915 }
7916
7917 if (!used)
7918 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7919 }
7920
e2e1ed41
DV		 7921
7922 /* set_mode is also used to update properties on life display pipes. */
7923 intel_crtc = to_intel_crtc(crtc);
7924 if (crtc->enabled)
7925 *prepare_pipes |= 1 << intel_crtc->pipe;
7926
b6c5164d
DV		 7927 /*
7928 * For simplicity do a full modeset on any pipe where the output routing
7929 * changed. We could be more clever, but that would require us to be
7930 * more careful with calling the relevant encoder->mode_set functions.
7931 */
e2e1ed41
DV		 7932 if (*prepare_pipes)
7933 *modeset_pipes = *prepare_pipes;
7934
7935 /* ... and mask these out. */
7936 *modeset_pipes &= ~(*disable_pipes);
7937 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7938
7939 /*
7940 * HACK: We don't (yet) fully support global modesets. intel_set_config
7941 * obies this rule, but the modeset restore mode of
7942 * intel_modeset_setup_hw_state does not.
7943 */
7944 *modeset_pipes &= 1 << intel_crtc->pipe;
7945 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 7946
7947 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7948 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 7949}
79e53945 7950
ea9d758d 7951static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7952{
ea9d758d 7953 struct drm_encoder *encoder;
f6e5b160 7954 struct drm_device *dev = crtc->dev;
f6e5b160 7955
ea9d758d
DV		 7956 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7957 if (encoder->crtc == crtc)
7958 return true;
7959
7960 return false;
7961}
7962
7963static void
7964intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7965{
7966 struct intel_encoder *intel_encoder;
7967 struct intel_crtc *intel_crtc;
7968 struct drm_connector *connector;
7969
7970 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7971 base.head) {
7972 if (!intel_encoder->base.crtc)
7973 continue;
7974
7975 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7976
7977 if (prepare_pipes & (1 << intel_crtc->pipe))
7978 intel_encoder->connectors_active = false;
7979 }
7980
7981 intel_modeset_commit_output_state(dev);
7982
7983 /* Update computed state. */
7984 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7985 base.head) {
7986 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7987 }
7988
7989 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7990 if (!connector->encoder || !connector->encoder->crtc)
7991 continue;
7992
7993 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7994
7995 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7996 struct drm_property *dpms_property =
7997 dev->mode_config.dpms_property;
7998
ea9d758d 7999 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8000 drm_object_property_set_value(&connector->base,
68d34720
DV		 8001 dpms_property,
8002 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8003
8004 intel_encoder = to_intel_encoder(connector->encoder);
8005 intel_encoder->connectors_active = true;
8006 }
8007 }
8008
8009}
8010
25c5b266
DV		 8011#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8012 list_for_each_entry((intel_crtc), \
8013 &(dev)->mode_config.crtc_list, \
8014 base.head) \
0973f18f 8015 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8016
0e8ffe1b
DV		 8017static bool
8018intel_pipe_config_compare(struct intel_crtc_config *current_config,
8019 struct intel_crtc_config *pipe_config)
8020{
08a24034
DV		 8021#define PIPE_CONF_CHECK_I(name) \
8022 if (current_config->name != pipe_config->name) { \
8023 DRM_ERROR("mismatch in " #name " " \
8024 "(expected %i, found %i)\n", \
8025 current_config->name, \
8026 pipe_config->name); \
8027 return false; \
88adfff1
DV		 8028 }
8029
1bd1bd80
DV		 8030#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8031 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8032 DRM_ERROR("mismatch in " #name " " \
8033 "(expected %i, found %i)\n", \
8034 current_config->name & (mask), \
8035 pipe_config->name & (mask)); \
8036 return false; \
8037 }
8038
08a24034
DV		 8039 PIPE_CONF_CHECK_I(has_pch_encoder);
8040 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8041 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8042 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8043 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8044 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8045 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8046
1bd1bd80
DV		 8047 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8048 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8049 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8050 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8051 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8052 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8053
8054 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8055 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8056 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8057 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8058 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8059 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8060
8061 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8062 DRM_MODE_FLAG_INTERLACE);
8063
8064 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8065 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8066
08a24034 8067#undef PIPE_CONF_CHECK_I
1bd1bd80 8068#undef PIPE_CONF_CHECK_FLAGS
627eb5a3 8069
0e8ffe1b
DV		 8070 return true;
8071}
8072
b980514c 8073void
8af6cf88
DV		 8074intel_modeset_check_state(struct drm_device *dev)
8075{
0e8ffe1b 8076 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 8077 struct intel_crtc *crtc;
8078 struct intel_encoder *encoder;
8079 struct intel_connector *connector;
0e8ffe1b 8080 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8081
8082 list_for_each_entry(connector, &dev->mode_config.connector_list,
8083 base.head) {
8084 /* This also checks the encoder/connector hw state with the
8085 * ->get_hw_state callbacks. */
8086 intel_connector_check_state(connector);
8087
8088 WARN(&connector->new_encoder->base != connector->base.encoder,
8089 "connector's staged encoder doesn't match current encoder\n");
8090 }
8091
8092 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8093 base.head) {
8094 bool enabled = false;
8095 bool active = false;
8096 enum pipe pipe, tracked_pipe;
8097
8098 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8099 encoder->base.base.id,
8100 drm_get_encoder_name(&encoder->base));
8101
8102 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8103 "encoder's stage crtc doesn't match current crtc\n");
8104 WARN(encoder->connectors_active && !encoder->base.crtc,
8105 "encoder's active_connectors set, but no crtc\n");
8106
8107 list_for_each_entry(connector, &dev->mode_config.connector_list,
8108 base.head) {
8109 if (connector->base.encoder != &encoder->base)
8110 continue;
8111 enabled = true;
8112 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8113 active = true;
8114 }
8115 WARN(!!encoder->base.crtc != enabled,
8116 "encoder's enabled state mismatch "
8117 "(expected %i, found %i)\n",
8118 !!encoder->base.crtc, enabled);
8119 WARN(active && !encoder->base.crtc,
8120 "active encoder with no crtc\n");
8121
8122 WARN(encoder->connectors_active != active,
8123 "encoder's computed active state doesn't match tracked active state "
8124 "(expected %i, found %i)\n", active, encoder->connectors_active);
8125
8126 active = encoder->get_hw_state(encoder, &pipe);
8127 WARN(active != encoder->connectors_active,
8128 "encoder's hw state doesn't match sw tracking "
8129 "(expected %i, found %i)\n",
8130 encoder->connectors_active, active);
8131
8132 if (!encoder->base.crtc)
8133 continue;
8134
8135 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8136 WARN(active && pipe != tracked_pipe,
8137 "active encoder's pipe doesn't match"
8138 "(expected %i, found %i)\n",
8139 tracked_pipe, pipe);
8140
8141 }
8142
8143 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8144 base.head) {
8145 bool enabled = false;
8146 bool active = false;
8147
8148 DRM_DEBUG_KMS("[CRTC:%d]\n",
8149 crtc->base.base.id);
8150
8151 WARN(crtc->active && !crtc->base.enabled,
8152 "active crtc, but not enabled in sw tracking\n");
8153
8154 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8155 base.head) {
8156 if (encoder->base.crtc != &crtc->base)
8157 continue;
8158 enabled = true;
8159 if (encoder->connectors_active)
8160 active = true;
8161 }
8162 WARN(active != crtc->active,
8163 "crtc's computed active state doesn't match tracked active state "
8164 "(expected %i, found %i)\n", active, crtc->active);
8165 WARN(enabled != crtc->base.enabled,
8166 "crtc's computed enabled state doesn't match tracked enabled state "
8167 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8168
88adfff1 8169 memset(&pipe_config, 0, sizeof(pipe_config));
60c4ae10 8170 pipe_config.cpu_transcoder = crtc->config.cpu_transcoder;
0e8ffe1b
DV		 8171 active = dev_priv->display.get_pipe_config(crtc,
8172 &pipe_config);
8173 WARN(crtc->active != active,
8174 "crtc active state doesn't match with hw state "
8175 "(expected %i, found %i)\n", crtc->active, active);
8176
8177 WARN(active &&
8178 !intel_pipe_config_compare(&crtc->config, &pipe_config),
8179 "pipe state doesn't match!\n");
8af6cf88
DV		 8180 }
8181}
8182
f30da187
DV		 8183static int __intel_set_mode(struct drm_crtc *crtc,
8184 struct drm_display_mode *mode,
8185 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8186{
8187 struct drm_device *dev = crtc->dev;
dbf2b54e 8188 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8189 struct drm_display_mode *saved_mode, *saved_hwmode;
8190 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8191 struct intel_crtc *intel_crtc;
8192 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8193 int ret = 0;
a6778b3c 8194
3ac18232 8195 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8196 if (!saved_mode)
8197 return -ENOMEM;
3ac18232 8198 saved_hwmode = saved_mode + 1;
a6778b3c 8199
e2e1ed41 8200 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8201 &prepare_pipes, &disable_pipes);
8202
3ac18232
TG		 8203 *saved_hwmode = crtc->hwmode;
8204 *saved_mode = crtc->mode;
a6778b3c 8205
25c5b266
DV		 8206 /* Hack: Because we don't (yet) support global modeset on multiple
8207 * crtcs, we don't keep track of the new mode for more than one crtc.
8208 * Hence simply check whether any bit is set in modeset_pipes in all the
8209 * pieces of code that are not yet converted to deal with mutliple crtcs
8210 * changing their mode at the same time. */
25c5b266 8211 if (modeset_pipes) {
4e53c2e0 8212 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8213 if (IS_ERR(pipe_config)) {
8214 ret = PTR_ERR(pipe_config);
8215 pipe_config = NULL;
8216
3ac18232 8217 goto out;
25c5b266 8218 }
25c5b266 8219 }
a6778b3c 8220
460da916
DV		 8221 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8222 intel_crtc_disable(&intel_crtc->base);
8223
ea9d758d
DV		 8224 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8225 if (intel_crtc->base.enabled)
8226 dev_priv->display.crtc_disable(&intel_crtc->base);
8227 }
a6778b3c 8228
6c4c86f5
DV		 8229 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8230 * to set it here already despite that we pass it down the callchain.
f6e5b160 8231 */
b8cecdf5 8232 if (modeset_pipes) {
3b117c8f 8233 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
25c5b266 8234 crtc->mode = *mode;
b8cecdf5
DV		 8235 /* mode_set/enable/disable functions rely on a correct pipe
8236 * config. */
8237 to_intel_crtc(crtc)->config = *pipe_config;
3b117c8f 8238 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
b8cecdf5 8239 }
7758a113 8240
ea9d758d
DV		 8241 /* Only after disabling all output pipelines that will be changed can we
8242 * update the the output configuration. */
8243 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8244
47fab737
DV		 8245 if (dev_priv->display.modeset_global_resources)
8246 dev_priv->display.modeset_global_resources(dev);
8247
a6778b3c
DV		 8248 /* Set up the DPLL and any encoders state that needs to adjust or depend
8249 * on the DPLL.
f6e5b160 8250 */
25c5b266 8251 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8252 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8253 x, y, fb);
8254 if (ret)
8255 goto done;
a6778b3c
DV		 8256 }
8257
8258 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8259 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8260 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8261
25c5b266
DV		 8262 if (modeset_pipes) {
8263 /* Store real post-adjustment hardware mode. */
b8cecdf5 8264 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8265
25c5b266
DV		 8266 /* Calculate and store various constants which
8267 * are later needed by vblank and swap-completion
8268 * timestamping. They are derived from true hwmode.
8269 */
8270 drm_calc_timestamping_constants(crtc);
8271 }
a6778b3c
DV		 8272
8273 /* FIXME: add subpixel order */
8274done:
c0c36b94 8275 if (ret && crtc->enabled) {
3ac18232
TG		 8276 crtc->hwmode = *saved_hwmode;
8277 crtc->mode = *saved_mode;
a6778b3c
DV		 8278 }
8279
3ac18232 8280out:
b8cecdf5 8281 kfree(pipe_config);
3ac18232 8282 kfree(saved_mode);
a6778b3c 8283 return ret;
f6e5b160
CW		 8284}
8285
f30da187
DV		 8286int intel_set_mode(struct drm_crtc *crtc,
8287 struct drm_display_mode *mode,
8288 int x, int y, struct drm_framebuffer *fb)
8289{
8290 int ret;
8291
8292 ret = __intel_set_mode(crtc, mode, x, y, fb);
8293
8294 if (ret == 0)
8295 intel_modeset_check_state(crtc->dev);
8296
8297 return ret;
8298}
8299
c0c36b94
CW		 8300void intel_crtc_restore_mode(struct drm_crtc *crtc)
8301{
8302 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8303}
8304
25c5b266
DV		 8305#undef for_each_intel_crtc_masked
8306
d9e55608
DV		 8307static void intel_set_config_free(struct intel_set_config *config)
8308{
8309 if (!config)
8310 return;
8311
1aa4b628
DV		 8312 kfree(config->save_connector_encoders);
8313 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8314 kfree(config);
8315}
8316
85f9eb71
DV		 8317static int intel_set_config_save_state(struct drm_device *dev,
8318 struct intel_set_config *config)
8319{
85f9eb71
DV		 8320 struct drm_encoder *encoder;
8321 struct drm_connector *connector;
8322 int count;
8323
1aa4b628
DV		 8324 config->save_encoder_crtcs =
8325 kcalloc(dev->mode_config.num_encoder,
8326 sizeof(struct drm_crtc *), GFP_KERNEL);
8327 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8328 return -ENOMEM;
8329
1aa4b628
DV		 8330 config->save_connector_encoders =
8331 kcalloc(dev->mode_config.num_connector,
8332 sizeof(struct drm_encoder *), GFP_KERNEL);
8333 if (!config->save_connector_encoders)
85f9eb71
DV		 8334 return -ENOMEM;
8335
8336 /* Copy data. Note that driver private data is not affected.
8337 * Should anything bad happen only the expected state is
8338 * restored, not the drivers personal bookkeeping.
8339 */
85f9eb71
DV		 8340 count = 0;
8341 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8342 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8343 }
8344
8345 count = 0;
8346 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8347 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8348 }
8349
8350 return 0;
8351}
8352
8353static void intel_set_config_restore_state(struct drm_device *dev,
8354 struct intel_set_config *config)
8355{
9a935856
DV		 8356 struct intel_encoder *encoder;
8357 struct intel_connector *connector;
85f9eb71
DV		 8358 int count;
8359
85f9eb71 8360 count = 0;
9a935856
DV		 8361 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8362 encoder->new_crtc =
8363 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8364 }
8365
8366 count = 0;
9a935856
DV		 8367 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8368 connector->new_encoder =
8369 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8370 }
8371}
8372
5e2b584e
DV		 8373static void
8374intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8375 struct intel_set_config *config)
8376{
8377
8378 /* We should be able to check here if the fb has the same properties
8379 * and then just flip_or_move it */
8380 if (set->crtc->fb != set->fb) {
8381 /* If we have no fb then treat it as a full mode set */
8382 if (set->crtc->fb == NULL) {
8383 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8384 config->mode_changed = true;
8385 } else if (set->fb == NULL) {
8386 config->mode_changed = true;
72f4901e
DV		 8387 } else if (set->fb->pixel_format !=
8388 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8389 config->mode_changed = true;
8390 } else
8391 config->fb_changed = true;
8392 }
8393
835c5873 8394 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8395 config->fb_changed = true;
8396
8397 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8398 DRM_DEBUG_KMS("modes are different, full mode set\n");
8399 drm_mode_debug_printmodeline(&set->crtc->mode);
8400 drm_mode_debug_printmodeline(set->mode);
8401 config->mode_changed = true;
8402 }
8403}
8404
2e431051 8405static int
9a935856
DV		 8406intel_modeset_stage_output_state(struct drm_device *dev,
8407 struct drm_mode_set *set,
8408 struct intel_set_config *config)
50f56119 8409{
85f9eb71 8410 struct drm_crtc *new_crtc;
9a935856
DV		 8411 struct intel_connector *connector;
8412 struct intel_encoder *encoder;
2e431051 8413 int count, ro;
50f56119 8414
9abdda74 8415 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8416 * of connectors. For paranoia, double-check this. */
8417 WARN_ON(!set->fb && (set->num_connectors != 0));
8418 WARN_ON(set->fb && (set->num_connectors == 0));
8419
50f56119 8420 count = 0;
9a935856
DV		 8421 list_for_each_entry(connector, &dev->mode_config.connector_list,
8422 base.head) {
8423 /* Otherwise traverse passed in connector list and get encoders
8424 * for them. */
50f56119 8425 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8426 if (set->connectors[ro] == &connector->base) {
8427 connector->new_encoder = connector->encoder;
50f56119
DV		 8428 break;
8429 }
8430 }
8431
9a935856
DV		 8432 /* If we disable the crtc, disable all its connectors. Also, if
8433 * the connector is on the changing crtc but not on the new
8434 * connector list, disable it. */
8435 if ((!set->fb || ro == set->num_connectors) &&
8436 connector->base.encoder &&
8437 connector->base.encoder->crtc == set->crtc) {
8438 connector->new_encoder = NULL;
8439
8440 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8441 connector->base.base.id,
8442 drm_get_connector_name(&connector->base));
8443 }
8444
8445
8446 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8447 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8448 config->mode_changed = true;
50f56119
DV		 8449 }
8450 }
9a935856 8451 /* connector->new_encoder is now updated for all connectors. */
50f56119 8452
9a935856 8453 /* Update crtc of enabled connectors. */
50f56119 8454 count = 0;
9a935856
DV		 8455 list_for_each_entry(connector, &dev->mode_config.connector_list,
8456 base.head) {
8457 if (!connector->new_encoder)
50f56119
DV		 8458 continue;
8459
9a935856 8460 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8461
8462 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8463 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8464 new_crtc = set->crtc;
8465 }
8466
8467 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8468 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8469 new_crtc)) {
5e2b584e 8470 return -EINVAL;
50f56119 8471 }
9a935856
DV		 8472 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8473
8474 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8475 connector->base.base.id,
8476 drm_get_connector_name(&connector->base),
8477 new_crtc->base.id);
8478 }
8479
8480 /* Check for any encoders that needs to be disabled. */
8481 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8482 base.head) {
8483 list_for_each_entry(connector,
8484 &dev->mode_config.connector_list,
8485 base.head) {
8486 if (connector->new_encoder == encoder) {
8487 WARN_ON(!connector->new_encoder->new_crtc);
8488
8489 goto next_encoder;
8490 }
8491 }
8492 encoder->new_crtc = NULL;
8493next_encoder:
8494 /* Only now check for crtc changes so we don't miss encoders
8495 * that will be disabled. */
8496 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8497 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8498 config->mode_changed = true;
50f56119
DV		 8499 }
8500 }
9a935856 8501 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8502
2e431051
DV		 8503 return 0;
8504}
8505
8506static int intel_crtc_set_config(struct drm_mode_set *set)
8507{
8508 struct drm_device *dev;
2e431051
DV		 8509 struct drm_mode_set save_set;
8510 struct intel_set_config *config;
8511 int ret;
2e431051 8512
8d3e375e
DV		 8513 BUG_ON(!set);
8514 BUG_ON(!set->crtc);
8515 BUG_ON(!set->crtc->helper_private);
2e431051 8516
7e53f3a4
DV		 8517 /* Enforce sane interface api - has been abused by the fb helper. */
8518 BUG_ON(!set->mode && set->fb);
8519 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8520
2e431051
DV		 8521 if (set->fb) {
8522 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8523 set->crtc->base.id, set->fb->base.id,
8524 (int)set->num_connectors, set->x, set->y);
8525 } else {
8526 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8527 }
8528
8529 dev = set->crtc->dev;
8530
8531 ret = -ENOMEM;
8532 config = kzalloc(sizeof(*config), GFP_KERNEL);
8533 if (!config)
8534 goto out_config;
8535
8536 ret = intel_set_config_save_state(dev, config);
8537 if (ret)
8538 goto out_config;
8539
8540 save_set.crtc = set->crtc;
8541 save_set.mode = &set->crtc->mode;
8542 save_set.x = set->crtc->x;
8543 save_set.y = set->crtc->y;
8544 save_set.fb = set->crtc->fb;
8545
8546 /* Compute whether we need a full modeset, only an fb base update or no
8547 * change at all. In the future we might also check whether only the
8548 * mode changed, e.g. for LVDS where we only change the panel fitter in
8549 * such cases. */
8550 intel_set_config_compute_mode_changes(set, config);
8551
9a935856 8552 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8553 if (ret)
8554 goto fail;
8555
5e2b584e 8556 if (config->mode_changed) {
87f1faa6 8557 if (set->mode) {
50f56119
DV		 8558 DRM_DEBUG_KMS("attempting to set mode from"
8559 " userspace\n");
8560 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8561 }
8562
c0c36b94
CW		 8563 ret = intel_set_mode(set->crtc, set->mode,
8564 set->x, set->y, set->fb);
8565 if (ret) {
8566 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8567 set->crtc->base.id, ret);
87f1faa6
DV		 8568 goto fail;
8569 }
5e2b584e 8570 } else if (config->fb_changed) {
4878cae2
VS		 8571 intel_crtc_wait_for_pending_flips(set->crtc);
8572
4f660f49 8573 ret = intel_pipe_set_base(set->crtc,
94352cf9 8574 set->x, set->y, set->fb);
50f56119
DV		 8575 }
8576
d9e55608
DV		 8577 intel_set_config_free(config);
8578
50f56119
DV		 8579 return 0;
8580
8581fail:
85f9eb71 8582 intel_set_config_restore_state(dev, config);
50f56119
DV		 8583
8584 /* Try to restore the config */
5e2b584e 8585 if (config->mode_changed &&
c0c36b94
CW		 8586 intel_set_mode(save_set.crtc, save_set.mode,
8587 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8588 DRM_ERROR("failed to restore config after modeset failure\n");
8589
d9e55608
DV		 8590out_config:
8591 intel_set_config_free(config);
50f56119
DV		 8592 return ret;
8593}
f6e5b160
CW		 8594
8595static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8596 .cursor_set = intel_crtc_cursor_set,
8597 .cursor_move = intel_crtc_cursor_move,
8598 .gamma_set = intel_crtc_gamma_set,
50f56119 8599 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8600 .destroy = intel_crtc_destroy,
8601 .page_flip = intel_crtc_page_flip,
8602};
8603
79f689aa
PZ		 8604static void intel_cpu_pll_init(struct drm_device *dev)
8605{
affa9354 8606 if (HAS_DDI(dev))
79f689aa
PZ		 8607 intel_ddi_pll_init(dev);
8608}
8609
ee7b9f93
JB		 8610static void intel_pch_pll_init(struct drm_device *dev)
8611{
8612 drm_i915_private_t *dev_priv = dev->dev_private;
8613 int i;
8614
8615 if (dev_priv->num_pch_pll == 0) {
8616 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8617 return;
8618 }
8619
8620 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8621 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8622 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8623 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8624 }
8625}
8626
b358d0a6 8627static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8628{
22fd0fab 8629 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8630 struct intel_crtc *intel_crtc;
8631 int i;
8632
8633 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8634 if (intel_crtc == NULL)
8635 return;
8636
8637 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8638
8639 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8640 for (i = 0; i < 256; i++) {
8641 intel_crtc->lut_r[i] = i;
8642 intel_crtc->lut_g[i] = i;
8643 intel_crtc->lut_b[i] = i;
8644 }
8645
80824003
JB		 8646 /* Swap pipes & planes for FBC on pre-965 */
8647 intel_crtc->pipe = pipe;
8648 intel_crtc->plane = pipe;
3b117c8f 8649 intel_crtc->config.cpu_transcoder = pipe;
e2e767ab 8650 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8651 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8652 intel_crtc->plane = !pipe;
80824003
JB		 8653 }
8654
22fd0fab
JB		 8655 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8656 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8657 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8658 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8659
79e53945 8660 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8661}
8662
08d7b3d1 8663int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8664 struct drm_file *file)
08d7b3d1 8665{
08d7b3d1 8666 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8667 struct drm_mode_object *drmmode_obj;
8668 struct intel_crtc *crtc;
08d7b3d1 8669
1cff8f6b
DV		 8670 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8671 return -ENODEV;
08d7b3d1 8672
c05422d5
DV		 8673 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8674 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8675
c05422d5 8676 if (!drmmode_obj) {
08d7b3d1
CW		 8677 DRM_ERROR("no such CRTC id\n");
8678 return -EINVAL;
8679 }
8680
c05422d5
DV		 8681 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8682 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8683
c05422d5 8684 return 0;
08d7b3d1
CW		 8685}
8686
66a9278e 8687static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8688{
66a9278e
DV		 8689 struct drm_device *dev = encoder->base.dev;
8690 struct intel_encoder *source_encoder;
79e53945 8691 int index_mask = 0;
79e53945
JB		 8692 int entry = 0;
8693
66a9278e
DV		 8694 list_for_each_entry(source_encoder,
8695 &dev->mode_config.encoder_list, base.head) {
8696
8697 if (encoder == source_encoder)
79e53945 8698 index_mask |= (1 << entry);
66a9278e
DV		 8699
8700 /* Intel hw has only one MUX where enocoders could be cloned. */
8701 if (encoder->cloneable && source_encoder->cloneable)
8702 index_mask |= (1 << entry);
8703
79e53945
JB		 8704 entry++;
8705 }
4ef69c7a 8706
79e53945
JB		 8707 return index_mask;
8708}
8709
4d302442
CW		 8710static bool has_edp_a(struct drm_device *dev)
8711{
8712 struct drm_i915_private *dev_priv = dev->dev_private;
8713
8714 if (!IS_MOBILE(dev))
8715 return false;
8716
8717 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8718 return false;
8719
8720 if (IS_GEN5(dev) &&
8721 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8722 return false;
8723
8724 return true;
8725}
8726
79e53945
JB		 8727static void intel_setup_outputs(struct drm_device *dev)
8728{
725e30ad 8729 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8730 struct intel_encoder *encoder;
cb0953d7 8731 bool dpd_is_edp = false;
f3cfcba6 8732 bool has_lvds;
79e53945 8733
f3cfcba6 8734 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8735 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8736 /* disable the panel fitter on everything but LVDS */
8737 I915_WRITE(PFIT_CONTROL, 0);
8738 }
79e53945 8739
c40c0f5b 8740 if (!IS_ULT(dev))
79935fca 8741 intel_crt_init(dev);
cb0953d7 8742
affa9354 8743 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8744 int found;
8745
8746 /* Haswell uses DDI functions to detect digital outputs */
8747 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8748 /* DDI A only supports eDP */
8749 if (found)
8750 intel_ddi_init(dev, PORT_A);
8751
8752 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8753 * register */
8754 found = I915_READ(SFUSE_STRAP);
8755
8756 if (found & SFUSE_STRAP_DDIB_DETECTED)
8757 intel_ddi_init(dev, PORT_B);
8758 if (found & SFUSE_STRAP_DDIC_DETECTED)
8759 intel_ddi_init(dev, PORT_C);
8760 if (found & SFUSE_STRAP_DDID_DETECTED)
8761 intel_ddi_init(dev, PORT_D);
8762 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8763 int found;
270b3042
DV		 8764 dpd_is_edp = intel_dpd_is_edp(dev);
8765
8766 if (has_edp_a(dev))
8767 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8768
dc0fa718 8769 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8770 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8771 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8772 if (!found)
e2debe91 8773 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8774 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8775 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8776 }
8777
dc0fa718 8778 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8779 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8780
dc0fa718 8781 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8782 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8783
5eb08b69 8784 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8785 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8786
270b3042 8787 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8788 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8789 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8790 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8791 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8792 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8793
dc0fa718 8794 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8795 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8796 PORT_B);
67cfc203
VS		 8797 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8798 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8799 }
103a196f 8800 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8801 bool found = false;
7d57382e 8802
e2debe91 8803 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8804 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8805 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8806 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8807 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8808 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8809 }
27185ae1 8810
b01f2c3a
JB		 8811 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8812 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8813 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8814 }
725e30ad 8815 }
13520b05
KH		 8816
8817 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8818
e2debe91 8819 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8820 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8821 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8822 }
27185ae1 8823
e2debe91 8824 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8825
b01f2c3a
JB		 8826 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8827 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8828 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a
JB		 8829 }
8830 if (SUPPORTS_INTEGRATED_DP(dev)) {
8831 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8832 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8833 }
725e30ad 8834 }
27185ae1 8835
b01f2c3a
JB		 8836 if (SUPPORTS_INTEGRATED_DP(dev) &&
8837 (I915_READ(DP_D) & DP_DETECTED)) {
8838 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8839 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8840 }
bad720ff 8841 } else if (IS_GEN2(dev))
79e53945
JB		 8842 intel_dvo_init(dev);
8843
103a196f 8844 if (SUPPORTS_TV(dev))
79e53945
JB		 8845 intel_tv_init(dev);
8846
4ef69c7a
CW		 8847 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8848 encoder->base.possible_crtcs = encoder->crtc_mask;
8849 encoder->base.possible_clones =
66a9278e 8850 intel_encoder_clones(encoder);
79e53945 8851 }
47356eb6 8852
dde86e2d 8853 intel_init_pch_refclk(dev);
270b3042
DV		 8854
8855 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8856}
8857
8858static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8859{
8860 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8861
8862 drm_framebuffer_cleanup(fb);
05394f39 8863 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8864
8865 kfree(intel_fb);
8866}
8867
8868static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8869 struct drm_file *file,
79e53945
JB		 8870 unsigned int *handle)
8871{
8872 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8873 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8874
05394f39 8875 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8876}
8877
8878static const struct drm_framebuffer_funcs intel_fb_funcs = {
8879 .destroy = intel_user_framebuffer_destroy,
8880 .create_handle = intel_user_framebuffer_create_handle,
8881};
8882
38651674
DA		 8883int intel_framebuffer_init(struct drm_device *dev,
8884 struct intel_framebuffer *intel_fb,
308e5bcb 8885 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8886 struct drm_i915_gem_object *obj)
79e53945 8887{
79e53945
JB		 8888 int ret;
8889
c16ed4be
CW		 8890 if (obj->tiling_mode == I915_TILING_Y) {
8891 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8892 return -EINVAL;
c16ed4be 8893 }
57cd6508 8894
c16ed4be
CW		 8895 if (mode_cmd->pitches[0] & 63) {
8896 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8897 mode_cmd->pitches[0]);
57cd6508 8898 return -EINVAL;
c16ed4be 8899 }
57cd6508 8900
5d7bd705 8901 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8902 if (mode_cmd->pitches[0] > 32768) {
8903 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8904 mode_cmd->pitches[0]);
5d7bd705 8905 return -EINVAL;
c16ed4be 8906 }
5d7bd705
VS		 8907
8908 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8909 mode_cmd->pitches[0] != obj->stride) {
8910 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8911 mode_cmd->pitches[0], obj->stride);
5d7bd705 8912 return -EINVAL;
c16ed4be 8913 }
5d7bd705 8914
57779d06 8915 /* Reject formats not supported by any plane early. */
308e5bcb 8916 switch (mode_cmd->pixel_format) {
57779d06 8917 case DRM_FORMAT_C8:
04b3924d
VS		 8918 case DRM_FORMAT_RGB565:
8919 case DRM_FORMAT_XRGB8888:
8920 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8921 break;
8922 case DRM_FORMAT_XRGB1555:
8923 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8924 if (INTEL_INFO(dev)->gen > 3) {
8925 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8926 return -EINVAL;
c16ed4be 8927 }
57779d06
VS		 8928 break;
8929 case DRM_FORMAT_XBGR8888:
8930 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8931 case DRM_FORMAT_XRGB2101010:
8932 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8933 case DRM_FORMAT_XBGR2101010:
8934 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8935 if (INTEL_INFO(dev)->gen < 4) {
8936 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8937 return -EINVAL;
c16ed4be 8938 }
b5626747 8939 break;
04b3924d
VS		 8940 case DRM_FORMAT_YUYV:
8941 case DRM_FORMAT_UYVY:
8942 case DRM_FORMAT_YVYU:
8943 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8944 if (INTEL_INFO(dev)->gen < 5) {
8945 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8946 return -EINVAL;
c16ed4be 8947 }
57cd6508
CW		 8948 break;
8949 default:
c16ed4be 8950 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8951 return -EINVAL;
8952 }
8953
90f9a336
VS		 8954 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8955 if (mode_cmd->offsets[0] != 0)
8956 return -EINVAL;
8957
c7d73f6a
DV		 8958 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8959 intel_fb->obj = obj;
8960
79e53945
JB		 8961 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8962 if (ret) {
8963 DRM_ERROR("framebuffer init failed %d\n", ret);
8964 return ret;
8965 }
8966
79e53945
JB		 8967 return 0;
8968}
8969
79e53945
JB		 8970static struct drm_framebuffer *
8971intel_user_framebuffer_create(struct drm_device *dev,
8972 struct drm_file *filp,
308e5bcb 8973 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8974{
05394f39 8975 struct drm_i915_gem_object *obj;
79e53945 8976
308e5bcb
JB		 8977 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8978 mode_cmd->handles[0]));
c8725226 8979 if (&obj->base == NULL)
cce13ff7 8980 return ERR_PTR(-ENOENT);
79e53945 8981
d2dff872 8982 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8983}
8984
79e53945 8985static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8986 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8987 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8988};
8989
e70236a8
JB		 8990/* Set up chip specific display functions */
8991static void intel_init_display(struct drm_device *dev)
8992{
8993 struct drm_i915_private *dev_priv = dev->dev_private;
8994
affa9354 8995 if (HAS_DDI(dev)) {
0e8ffe1b 8996 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 8997 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8998 dev_priv->display.crtc_enable = haswell_crtc_enable;
8999 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9000 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9001 dev_priv->display.update_plane = ironlake_update_plane;
9002 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9003 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9004 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9005 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9006 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9007 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9008 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9009 } else if (IS_VALLEYVIEW(dev)) {
9010 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9011 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9012 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9013 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9014 dev_priv->display.off = i9xx_crtc_off;
9015 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9016 } else {
0e8ffe1b 9017 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9018 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9019 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9020 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9021 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9022 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9023 }
e70236a8 9024
e70236a8 9025 /* Returns the core display clock speed */
25eb05fc
JB		 9026 if (IS_VALLEYVIEW(dev))
9027 dev_priv->display.get_display_clock_speed =
9028 valleyview_get_display_clock_speed;
9029 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9030 dev_priv->display.get_display_clock_speed =
9031 i945_get_display_clock_speed;
9032 else if (IS_I915G(dev))
9033 dev_priv->display.get_display_clock_speed =
9034 i915_get_display_clock_speed;
f2b115e6 9035 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9036 dev_priv->display.get_display_clock_speed =
9037 i9xx_misc_get_display_clock_speed;
9038 else if (IS_I915GM(dev))
9039 dev_priv->display.get_display_clock_speed =
9040 i915gm_get_display_clock_speed;
9041 else if (IS_I865G(dev))
9042 dev_priv->display.get_display_clock_speed =
9043 i865_get_display_clock_speed;
f0f8a9ce 9044 else if (IS_I85X(dev))
e70236a8
JB		 9045 dev_priv->display.get_display_clock_speed =
9046 i855_get_display_clock_speed;
9047 else /* 852, 830 */
9048 dev_priv->display.get_display_clock_speed =
9049 i830_get_display_clock_speed;
9050
7f8a8569 9051 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9052 if (IS_GEN5(dev)) {
674cf967 9053 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9054 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9055 } else if (IS_GEN6(dev)) {
674cf967 9056 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9057 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9058 } else if (IS_IVYBRIDGE(dev)) {
9059 /* FIXME: detect B0+ stepping and use auto training */
9060 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9061 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9062 dev_priv->display.modeset_global_resources =
9063 ivb_modeset_global_resources;
c82e4d26
ED		 9064 } else if (IS_HASWELL(dev)) {
9065 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9066 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9067 dev_priv->display.modeset_global_resources =
9068 haswell_modeset_global_resources;
a0e63c22 9069 }
6067aaea 9070 } else if (IS_G4X(dev)) {
e0dac65e 9071 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9072 }
8c9f3aaf
JB		 9073
9074 /* Default just returns -ENODEV to indicate unsupported */
9075 dev_priv->display.queue_flip = intel_default_queue_flip;
9076
9077 switch (INTEL_INFO(dev)->gen) {
9078 case 2:
9079 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9080 break;
9081
9082 case 3:
9083 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9084 break;
9085
9086 case 4:
9087 case 5:
9088 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9089 break;
9090
9091 case 6:
9092 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9093 break;
7c9017e5
JB		 9094 case 7:
9095 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9096 break;
8c9f3aaf 9097 }
e70236a8
JB		 9098}
9099
b690e96c
JB		 9100/*
9101 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9102 * resume, or other times. This quirk makes sure that's the case for
9103 * affected systems.
9104 */
0206e353 9105static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9106{
9107 struct drm_i915_private *dev_priv = dev->dev_private;
9108
9109 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9110 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9111}
9112
435793df
KP		 9113/*
9114 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9115 */
9116static void quirk_ssc_force_disable(struct drm_device *dev)
9117{
9118 struct drm_i915_private *dev_priv = dev->dev_private;
9119 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9120 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9121}
9122
4dca20ef 9123/*
5a15ab5b
CE		 9124 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9125 * brightness value
4dca20ef
CE		 9126 */
9127static void quirk_invert_brightness(struct drm_device *dev)
9128{
9129 struct drm_i915_private *dev_priv = dev->dev_private;
9130 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9131 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9132}
9133
b690e96c
JB		 9134struct intel_quirk {
9135 int device;
9136 int subsystem_vendor;
9137 int subsystem_device;
9138 void (*hook)(struct drm_device *dev);
9139};
9140
5f85f176
EE		 9141/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9142struct intel_dmi_quirk {
9143 void (*hook)(struct drm_device *dev);
9144 const struct dmi_system_id (*dmi_id_list)[];
9145};
9146
9147static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9148{
9149 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9150 return 1;
9151}
9152
9153static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9154 {
9155 .dmi_id_list = &(const struct dmi_system_id[]) {
9156 {
9157 .callback = intel_dmi_reverse_brightness,
9158 .ident = "NCR Corporation",
9159 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9160 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9161 },
9162 },
9163 { } /* terminating entry */
9164 },
9165 .hook = quirk_invert_brightness,
9166 },
9167};
9168
c43b5634 9169static struct intel_quirk intel_quirks[] = {
b690e96c 9170 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9171 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9172
b690e96c
JB		 9173 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9174 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9175
b690e96c
JB		 9176 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9177 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9178
ccd0d36e 9179 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9180 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9181 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9182
9183 /* Lenovo U160 cannot use SSC on LVDS */
9184 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9185
9186 /* Sony Vaio Y cannot use SSC on LVDS */
9187 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9188
9189 /* Acer Aspire 5734Z must invert backlight brightness */
9190 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9191
9192 /* Acer/eMachines G725 */
9193 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9194
9195 /* Acer/eMachines e725 */
9196 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9197
9198 /* Acer/Packard Bell NCL20 */
9199 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9200
9201 /* Acer Aspire 4736Z */
9202 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9203};
9204
9205static void intel_init_quirks(struct drm_device *dev)
9206{
9207 struct pci_dev *d = dev->pdev;
9208 int i;
9209
9210 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9211 struct intel_quirk *q = &intel_quirks[i];
9212
9213 if (d->device == q->device &&
9214 (d->subsystem_vendor == q->subsystem_vendor ||
9215 q->subsystem_vendor == PCI_ANY_ID) &&
9216 (d->subsystem_device == q->subsystem_device ||
9217 q->subsystem_device == PCI_ANY_ID))
9218 q->hook(dev);
9219 }
5f85f176
EE		 9220 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9221 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9222 intel_dmi_quirks[i].hook(dev);
9223 }
b690e96c
JB		 9224}
9225
9cce37f4
JB		 9226/* Disable the VGA plane that we never use */
9227static void i915_disable_vga(struct drm_device *dev)
9228{
9229 struct drm_i915_private *dev_priv = dev->dev_private;
9230 u8 sr1;
766aa1c4 9231 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9232
9233 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9234 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9235 sr1 = inb(VGA_SR_DATA);
9236 outb(sr1 | 1<<5, VGA_SR_DATA);
9237 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9238 udelay(300);
9239
9240 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9241 POSTING_READ(vga_reg);
9242}
9243
f817586c
DV		 9244void intel_modeset_init_hw(struct drm_device *dev)
9245{
fa42e23c 9246 intel_init_power_well(dev);
0232e927 9247
a8f78b58
ED		 9248 intel_prepare_ddi(dev);
9249
f817586c
DV		 9250 intel_init_clock_gating(dev);
9251
79f5b2c7 9252 mutex_lock(&dev->struct_mutex);
8090c6b9 9253 intel_enable_gt_powersave(dev);
79f5b2c7 9254 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9255}
9256
79e53945
JB		 9257void intel_modeset_init(struct drm_device *dev)
9258{
652c393a 9259 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9260 int i, j, ret;
79e53945
JB		 9261
9262 drm_mode_config_init(dev);
9263
9264 dev->mode_config.min_width = 0;
9265 dev->mode_config.min_height = 0;
9266
019d96cb
DA		 9267 dev->mode_config.preferred_depth = 24;
9268 dev->mode_config.prefer_shadow = 1;
9269
e6ecefaa 9270 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9271
b690e96c
JB		 9272 intel_init_quirks(dev);
9273
1fa61106
ED		 9274 intel_init_pm(dev);
9275
e3c74757
BW		 9276 if (INTEL_INFO(dev)->num_pipes == 0)
9277 return;
9278
e70236a8
JB		 9279 intel_init_display(dev);
9280
a6c45cf0
CW		 9281 if (IS_GEN2(dev)) {
9282 dev->mode_config.max_width = 2048;
9283 dev->mode_config.max_height = 2048;
9284 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9285 dev->mode_config.max_width = 4096;
9286 dev->mode_config.max_height = 4096;
79e53945 9287 } else {
a6c45cf0
CW		 9288 dev->mode_config.max_width = 8192;
9289 dev->mode_config.max_height = 8192;
79e53945 9290 }
5d4545ae 9291 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9292
28c97730 9293 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9294 INTEL_INFO(dev)->num_pipes,
9295 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9296
7eb552ae 9297 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9298 intel_crtc_init(dev, i);
7f1f3851
JB		 9299 for (j = 0; j < dev_priv->num_plane; j++) {
9300 ret = intel_plane_init(dev, i, j);
9301 if (ret)
06da8da2
VS		 9302 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9303 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9304 }
79e53945
JB		 9305 }
9306
79f689aa 9307 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9308 intel_pch_pll_init(dev);
9309
9cce37f4
JB		 9310 /* Just disable it once at startup */
9311 i915_disable_vga(dev);
79e53945 9312 intel_setup_outputs(dev);
11be49eb
CW		 9313
9314 /* Just in case the BIOS is doing something questionable. */
9315 intel_disable_fbc(dev);
2c7111db
CW		 9316}
9317
24929352
DV		 9318static void
9319intel_connector_break_all_links(struct intel_connector *connector)
9320{
9321 connector->base.dpms = DRM_MODE_DPMS_OFF;
9322 connector->base.encoder = NULL;
9323 connector->encoder->connectors_active = false;
9324 connector->encoder->base.crtc = NULL;
9325}
9326
7fad798e
DV		 9327static void intel_enable_pipe_a(struct drm_device *dev)
9328{
9329 struct intel_connector *connector;
9330 struct drm_connector *crt = NULL;
9331 struct intel_load_detect_pipe load_detect_temp;
9332
9333 /* We can't just switch on the pipe A, we need to set things up with a
9334 * proper mode and output configuration. As a gross hack, enable pipe A
9335 * by enabling the load detect pipe once. */
9336 list_for_each_entry(connector,
9337 &dev->mode_config.connector_list,
9338 base.head) {
9339 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9340 crt = &connector->base;
9341 break;
9342 }
9343 }
9344
9345 if (!crt)
9346 return;
9347
9348 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9349 intel_release_load_detect_pipe(crt, &load_detect_temp);
9350
652c393a 9351
7fad798e
DV		 9352}
9353
fa555837
DV		 9354static bool
9355intel_check_plane_mapping(struct intel_crtc *crtc)
9356{
7eb552ae
BW		 9357 struct drm_device *dev = crtc->base.dev;
9358 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9359 u32 reg, val;
9360
7eb552ae 9361 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9362 return true;
9363
9364 reg = DSPCNTR(!crtc->plane);
9365 val = I915_READ(reg);
9366
9367 if ((val & DISPLAY_PLANE_ENABLE) &&
9368 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9369 return false;
9370
9371 return true;
9372}
9373
24929352
DV		 9374static void intel_sanitize_crtc(struct intel_crtc *crtc)
9375{
9376 struct drm_device *dev = crtc->base.dev;
9377 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9378 u32 reg;
24929352 9379
24929352 9380 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9381 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9382 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9383
9384 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9385 * disable the crtc (and hence change the state) if it is wrong. Note
9386 * that gen4+ has a fixed plane -> pipe mapping. */
9387 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9388 struct intel_connector *connector;
9389 bool plane;
9390
24929352
DV		 9391 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9392 crtc->base.base.id);
9393
9394 /* Pipe has the wrong plane attached and the plane is active.
9395 * Temporarily change the plane mapping and disable everything
9396 * ... */
9397 plane = crtc->plane;
9398 crtc->plane = !plane;
9399 dev_priv->display.crtc_disable(&crtc->base);
9400 crtc->plane = plane;
9401
9402 /* ... and break all links. */
9403 list_for_each_entry(connector, &dev->mode_config.connector_list,
9404 base.head) {
9405 if (connector->encoder->base.crtc != &crtc->base)
9406 continue;
9407
9408 intel_connector_break_all_links(connector);
9409 }
9410
9411 WARN_ON(crtc->active);
9412 crtc->base.enabled = false;
9413 }
24929352 9414
7fad798e
DV		 9415 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9416 crtc->pipe == PIPE_A && !crtc->active) {
9417 /* BIOS forgot to enable pipe A, this mostly happens after
9418 * resume. Force-enable the pipe to fix this, the update_dpms
9419 * call below we restore the pipe to the right state, but leave
9420 * the required bits on. */
9421 intel_enable_pipe_a(dev);
9422 }
9423
24929352
DV		 9424 /* Adjust the state of the output pipe according to whether we
9425 * have active connectors/encoders. */
9426 intel_crtc_update_dpms(&crtc->base);
9427
9428 if (crtc->active != crtc->base.enabled) {
9429 struct intel_encoder *encoder;
9430
9431 /* This can happen either due to bugs in the get_hw_state
9432 * functions or because the pipe is force-enabled due to the
9433 * pipe A quirk. */
9434 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9435 crtc->base.base.id,
9436 crtc->base.enabled ? "enabled" : "disabled",
9437 crtc->active ? "enabled" : "disabled");
9438
9439 crtc->base.enabled = crtc->active;
9440
9441 /* Because we only establish the connector -> encoder ->
9442 * crtc links if something is active, this means the
9443 * crtc is now deactivated. Break the links. connector
9444 * -> encoder links are only establish when things are
9445 * actually up, hence no need to break them. */
9446 WARN_ON(crtc->active);
9447
9448 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9449 WARN_ON(encoder->connectors_active);
9450 encoder->base.crtc = NULL;
9451 }
9452 }
9453}
9454
9455static void intel_sanitize_encoder(struct intel_encoder *encoder)
9456{
9457 struct intel_connector *connector;
9458 struct drm_device *dev = encoder->base.dev;
9459
9460 /* We need to check both for a crtc link (meaning that the
9461 * encoder is active and trying to read from a pipe) and the
9462 * pipe itself being active. */
9463 bool has_active_crtc = encoder->base.crtc &&
9464 to_intel_crtc(encoder->base.crtc)->active;
9465
9466 if (encoder->connectors_active && !has_active_crtc) {
9467 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9468 encoder->base.base.id,
9469 drm_get_encoder_name(&encoder->base));
9470
9471 /* Connector is active, but has no active pipe. This is
9472 * fallout from our resume register restoring. Disable
9473 * the encoder manually again. */
9474 if (encoder->base.crtc) {
9475 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9476 encoder->base.base.id,
9477 drm_get_encoder_name(&encoder->base));
9478 encoder->disable(encoder);
9479 }
9480
9481 /* Inconsistent output/port/pipe state happens presumably due to
9482 * a bug in one of the get_hw_state functions. Or someplace else
9483 * in our code, like the register restore mess on resume. Clamp
9484 * things to off as a safer default. */
9485 list_for_each_entry(connector,
9486 &dev->mode_config.connector_list,
9487 base.head) {
9488 if (connector->encoder != encoder)
9489 continue;
9490
9491 intel_connector_break_all_links(connector);
9492 }
9493 }
9494 /* Enabled encoders without active connectors will be fixed in
9495 * the crtc fixup. */
9496}
9497
44cec740 9498void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9499{
9500 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9501 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9502
9503 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9504 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9505 i915_disable_vga(dev);
0fde901f
KM		 9506 }
9507}
9508
24929352
DV		 9509/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9510 * and i915 state tracking structures. */
45e2b5f6
DV		 9511void intel_modeset_setup_hw_state(struct drm_device *dev,
9512 bool force_restore)
24929352
DV		 9513{
9514 struct drm_i915_private *dev_priv = dev->dev_private;
9515 enum pipe pipe;
9516 u32 tmp;
b5644d05 9517 struct drm_plane *plane;
24929352
DV		 9518 struct intel_crtc *crtc;
9519 struct intel_encoder *encoder;
9520 struct intel_connector *connector;
9521
affa9354 9522 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9523 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9524
9525 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9526 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9527 case TRANS_DDI_EDP_INPUT_A_ON:
9528 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9529 pipe = PIPE_A;
9530 break;
9531 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9532 pipe = PIPE_B;
9533 break;
9534 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9535 pipe = PIPE_C;
9536 break;
aaa148ec
DL		 9537 default:
9538 /* A bogus value has been programmed, disable
9539 * the transcoder */
9540 WARN(1, "Bogus eDP source %08x\n", tmp);
9541 intel_ddi_disable_transcoder_func(dev_priv,
9542 TRANSCODER_EDP);
9543 goto setup_pipes;
e28d54cb
PZ		 9544 }
9545
9546 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3b117c8f 9547 crtc->config.cpu_transcoder = TRANSCODER_EDP;
e28d54cb
PZ		 9548
9549 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9550 pipe_name(pipe));
9551 }
9552 }
9553
aaa148ec 9554setup_pipes:
0e8ffe1b
DV		 9555 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9556 base.head) {
3b117c8f 9557 enum transcoder tmp = crtc->config.cpu_transcoder;
88adfff1 9558 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f
DV		 9559 crtc->config.cpu_transcoder = tmp;
9560
0e8ffe1b
DV		 9561 crtc->active = dev_priv->display.get_pipe_config(crtc,
9562 &crtc->config);
24929352
DV		 9563
9564 crtc->base.enabled = crtc->active;
9565
9566 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9567 crtc->base.base.id,
9568 crtc->active ? "enabled" : "disabled");
9569 }
9570
affa9354 9571 if (HAS_DDI(dev))
6441ab5f
PZ		 9572 intel_ddi_setup_hw_pll_state(dev);
9573
24929352
DV		 9574 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9575 base.head) {
9576 pipe = 0;
9577
9578 if (encoder->get_hw_state(encoder, &pipe)) {
9579 encoder->base.crtc =
9580 dev_priv->pipe_to_crtc_mapping[pipe];
9581 } else {
9582 encoder->base.crtc = NULL;
9583 }
9584
9585 encoder->connectors_active = false;
9586 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9587 encoder->base.base.id,
9588 drm_get_encoder_name(&encoder->base),
9589 encoder->base.crtc ? "enabled" : "disabled",
9590 pipe);
9591 }
9592
9593 list_for_each_entry(connector, &dev->mode_config.connector_list,
9594 base.head) {
9595 if (connector->get_hw_state(connector)) {
9596 connector->base.dpms = DRM_MODE_DPMS_ON;
9597 connector->encoder->connectors_active = true;
9598 connector->base.encoder = &connector->encoder->base;
9599 } else {
9600 connector->base.dpms = DRM_MODE_DPMS_OFF;
9601 connector->base.encoder = NULL;
9602 }
9603 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9604 connector->base.base.id,
9605 drm_get_connector_name(&connector->base),
9606 connector->base.encoder ? "enabled" : "disabled");
9607 }
9608
9609 /* HW state is read out, now we need to sanitize this mess. */
9610 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9611 base.head) {
9612 intel_sanitize_encoder(encoder);
9613 }
9614
9615 for_each_pipe(pipe) {
9616 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9617 intel_sanitize_crtc(crtc);
9618 }
9a935856 9619
45e2b5f6 9620 if (force_restore) {
f30da187
DV		 9621 /*
9622 * We need to use raw interfaces for restoring state to avoid
9623 * checking (bogus) intermediate states.
9624 */
45e2b5f6 9625 for_each_pipe(pipe) {
b5644d05
JB		 9626 struct drm_crtc *crtc =
9627 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9628
9629 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9630 crtc->fb);
45e2b5f6 9631 }
b5644d05
JB		 9632 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9633 intel_plane_restore(plane);
0fde901f
KM		 9634
9635 i915_redisable_vga(dev);
45e2b5f6
DV		 9636 } else {
9637 intel_modeset_update_staged_output_state(dev);
9638 }
8af6cf88
DV		 9639
9640 intel_modeset_check_state(dev);
2e938892
DV		 9641
9642 drm_mode_config_reset(dev);
2c7111db
CW		 9643}
9644
9645void intel_modeset_gem_init(struct drm_device *dev)
9646{
1833b134 9647 intel_modeset_init_hw(dev);
02e792fb
DV		 9648
9649 intel_setup_overlay(dev);
24929352 9650
45e2b5f6 9651 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9652}
9653
9654void intel_modeset_cleanup(struct drm_device *dev)
9655{
652c393a
JB		 9656 struct drm_i915_private *dev_priv = dev->dev_private;
9657 struct drm_crtc *crtc;
9658 struct intel_crtc *intel_crtc;
9659
fd0c0642
DV		 9660 /*
9661 * Interrupts and polling as the first thing to avoid creating havoc.
9662 * Too much stuff here (turning of rps, connectors, ...) would
9663 * experience fancy races otherwise.
9664 */
9665 drm_irq_uninstall(dev);
9666 cancel_work_sync(&dev_priv->hotplug_work);
9667 /*
9668 * Due to the hpd irq storm handling the hotplug work can re-arm the
9669 * poll handlers. Hence disable polling after hpd handling is shut down.
9670 */
f87ea761 9671 drm_kms_helper_poll_fini(dev);
fd0c0642 9672
652c393a
JB		 9673 mutex_lock(&dev->struct_mutex);
9674
723bfd70
JB		 9675 intel_unregister_dsm_handler();
9676
652c393a
JB		 9677 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9678 /* Skip inactive CRTCs */
9679 if (!crtc->fb)
9680 continue;
9681
9682 intel_crtc = to_intel_crtc(crtc);
3dec0095 9683 intel_increase_pllclock(crtc);
652c393a
JB		 9684 }
9685
973d04f9 9686 intel_disable_fbc(dev);
e70236a8 9687
8090c6b9 9688 intel_disable_gt_powersave(dev);
0cdab21f 9689
930ebb46
DV		 9690 ironlake_teardown_rc6(dev);
9691
69341a5e
KH		 9692 mutex_unlock(&dev->struct_mutex);
9693
1630fe75
CW		 9694 /* flush any delayed tasks or pending work */
9695 flush_scheduled_work();
9696
dc652f90
JN		 9697 /* destroy backlight, if any, before the connectors */
9698 intel_panel_destroy_backlight(dev);
9699
79e53945 9700 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9701
9702 intel_cleanup_overlay(dev);
79e53945
JB		 9703}
9704
f1c79df3
ZW		 9705/*
9706 * Return which encoder is currently attached for connector.
9707 */
df0e9248 9708struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9709{
df0e9248
CW		 9710 return &intel_attached_encoder(connector)->base;
9711}
f1c79df3 9712
df0e9248
CW		 9713void intel_connector_attach_encoder(struct intel_connector *connector,
9714 struct intel_encoder *encoder)
9715{
9716 connector->encoder = encoder;
9717 drm_mode_connector_attach_encoder(&connector->base,
9718 &encoder->base);
79e53945 9719}
28d52043
DA		 9720
9721/*
9722 * set vga decode state - true == enable VGA decode
9723 */
9724int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9725{
9726 struct drm_i915_private *dev_priv = dev->dev_private;
9727 u16 gmch_ctrl;
9728
9729 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9730 if (state)
9731 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9732 else
9733 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9734 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9735 return 0;
9736}
c4a1d9e4
CW		 9737
9738#ifdef CONFIG_DEBUG_FS
9739#include <linux/seq_file.h>
9740
9741struct intel_display_error_state {
9742 struct intel_cursor_error_state {
9743 u32 control;
9744 u32 position;
9745 u32 base;
9746 u32 size;
52331309 9747 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9748
9749 struct intel_pipe_error_state {
9750 u32 conf;
9751 u32 source;
9752
9753 u32 htotal;
9754 u32 hblank;
9755 u32 hsync;
9756 u32 vtotal;
9757 u32 vblank;
9758 u32 vsync;
52331309 9759 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9760
9761 struct intel_plane_error_state {
9762 u32 control;
9763 u32 stride;
9764 u32 size;
9765 u32 pos;
9766 u32 addr;
9767 u32 surface;
9768 u32 tile_offset;
52331309 9769 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9770};
9771
9772struct intel_display_error_state *
9773intel_display_capture_error_state(struct drm_device *dev)
9774{
0206e353 9775 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9776 struct intel_display_error_state *error;
702e7a56 9777 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9778 int i;
9779
9780 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9781 if (error == NULL)
9782 return NULL;
9783
52331309 9784 for_each_pipe(i) {
702e7a56
PZ		 9785 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9786
a18c4c3d
PZ		 9787 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9788 error->cursor[i].control = I915_READ(CURCNTR(i));
9789 error->cursor[i].position = I915_READ(CURPOS(i));
9790 error->cursor[i].base = I915_READ(CURBASE(i));
9791 } else {
9792 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9793 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9794 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9795 }
c4a1d9e4
CW		 9796
9797 error->plane[i].control = I915_READ(DSPCNTR(i));
9798 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9799 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9800 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9801 error->plane[i].pos = I915_READ(DSPPOS(i));
9802 }
ca291363
PZ		 9803 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9804 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9805 if (INTEL_INFO(dev)->gen >= 4) {
9806 error->plane[i].surface = I915_READ(DSPSURF(i));
9807 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9808 }
9809
702e7a56 9810 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9811 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9812 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9813 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9814 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9815 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9816 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9817 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9818 }
9819
9820 return error;
9821}
9822
9823void
9824intel_display_print_error_state(struct seq_file *m,
9825 struct drm_device *dev,
9826 struct intel_display_error_state *error)
9827{
9828 int i;
9829
7eb552ae 9830 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
52331309 9831 for_each_pipe(i) {
c4a1d9e4
CW		 9832 seq_printf(m, "Pipe [%d]:\n", i);
9833 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9834 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9835 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9836 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9837 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9838 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9839 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9840 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9841
9842 seq_printf(m, "Plane [%d]:\n", i);
9843 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9844 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9845 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9846 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
80ca378b
PZ		 9847 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9848 }
4b71a570 9849 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
ca291363 9850 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4
CW		 9851 if (INTEL_INFO(dev)->gen >= 4) {
9852 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9853 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9854 }
9855
9856 seq_printf(m, "Cursor [%d]:\n", i);
9857 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9858 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9859 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9860 }
9861}
9862#endif
Linux kernel - Deliverables
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