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drm/i915: Use the disable callback for disabling planes.
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c
MR		 48/* Primary plane formats supported by all gen */
49#define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55/* Primary plane formats for gen <= 3 */
56static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60};
61
62/* Primary plane formats for gen >= 4 */
63static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71};
72
3d7d6510
MR		 73/* Cursor formats */
74static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76};
77
6b383a7f 78static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 79
f1f644dc 80static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 81 struct intel_crtc_state *pipe_config);
18442d08 82static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 83 struct intel_crtc_state *pipe_config);
f1f644dc 84
e7457a9a 85static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
83a57153
ACO		 86 int x, int y, struct drm_framebuffer *old_fb,
87 struct drm_atomic_state *state);
eb1bfe80
JB		 88static int intel_framebuffer_init(struct drm_device *dev,
89 struct intel_framebuffer *ifb,
90 struct drm_mode_fb_cmd2 *mode_cmd,
91 struct drm_i915_gem_object *obj);
5b18e57c
DV		 92static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
93static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 94static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 95 struct intel_link_m_n *m_n,
96 struct intel_link_m_n *m2_n2);
29407aab 97static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 98static void haswell_set_pipeconf(struct drm_crtc *crtc);
99static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 100static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 101 const struct intel_crtc_state *pipe_config);
d288f65f 102static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 103 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 104static void intel_begin_crtc_commit(struct drm_crtc *crtc);
105static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 106static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
107 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 108static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
109 int num_connectors);
e7457a9a 110
0e32b39c
DA		 111static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
112{
113 if (!connector->mst_port)
114 return connector->encoder;
115 else
116 return &connector->mst_port->mst_encoders[pipe]->base;
117}
118
79e53945 119typedef struct {
0206e353 120 int min, max;
79e53945
JB		 121} intel_range_t;
122
123typedef struct {
0206e353
AJ		 124 int dot_limit;
125 int p2_slow, p2_fast;
79e53945
JB		 126} intel_p2_t;
127
d4906093
ML		 128typedef struct intel_limit intel_limit_t;
129struct intel_limit {
0206e353
AJ		 130 intel_range_t dot, vco, n, m, m1, m2, p, p1;
131 intel_p2_t p2;
d4906093 132};
79e53945 133
d2acd215
DV		 134int
135intel_pch_rawclk(struct drm_device *dev)
136{
137 struct drm_i915_private *dev_priv = dev->dev_private;
138
139 WARN_ON(!HAS_PCH_SPLIT(dev));
140
141 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
142}
143
021357ac
CW		 144static inline u32 /* units of 100MHz */
145intel_fdi_link_freq(struct drm_device *dev)
146{
8b99e68c
CW		 147 if (IS_GEN5(dev)) {
148 struct drm_i915_private *dev_priv = dev->dev_private;
149 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
150 } else
151 return 27;
021357ac
CW		 152}
153
5d536e28 154static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 155 .dot = { .min = 25000, .max = 350000 },
9c333719 156 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 157 .n = { .min = 2, .max = 16 },
0206e353
AJ		 158 .m = { .min = 96, .max = 140 },
159 .m1 = { .min = 18, .max = 26 },
160 .m2 = { .min = 6, .max = 16 },
161 .p = { .min = 4, .max = 128 },
162 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 163 .p2 = { .dot_limit = 165000,
164 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 165};
166
5d536e28
DV		 167static const intel_limit_t intel_limits_i8xx_dvo = {
168 .dot = { .min = 25000, .max = 350000 },
9c333719 169 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 170 .n = { .min = 2, .max = 16 },
5d536e28
DV		 171 .m = { .min = 96, .max = 140 },
172 .m1 = { .min = 18, .max = 26 },
173 .m2 = { .min = 6, .max = 16 },
174 .p = { .min = 4, .max = 128 },
175 .p1 = { .min = 2, .max = 33 },
176 .p2 = { .dot_limit = 165000,
177 .p2_slow = 4, .p2_fast = 4 },
178};
179
e4b36699 180static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 181 .dot = { .min = 25000, .max = 350000 },
9c333719 182 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 183 .n = { .min = 2, .max = 16 },
0206e353
AJ		 184 .m = { .min = 96, .max = 140 },
185 .m1 = { .min = 18, .max = 26 },
186 .m2 = { .min = 6, .max = 16 },
187 .p = { .min = 4, .max = 128 },
188 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 189 .p2 = { .dot_limit = 165000,
190 .p2_slow = 14, .p2_fast = 7 },
e4b36699 191};
273e27ca 192
e4b36699 193static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 194 .dot = { .min = 20000, .max = 400000 },
195 .vco = { .min = 1400000, .max = 2800000 },
196 .n = { .min = 1, .max = 6 },
197 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 198 .m1 = { .min = 8, .max = 18 },
199 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 200 .p = { .min = 5, .max = 80 },
201 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 202 .p2 = { .dot_limit = 200000,
203 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 204};
205
206static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 207 .dot = { .min = 20000, .max = 400000 },
208 .vco = { .min = 1400000, .max = 2800000 },
209 .n = { .min = 1, .max = 6 },
210 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 211 .m1 = { .min = 8, .max = 18 },
212 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 213 .p = { .min = 7, .max = 98 },
214 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 215 .p2 = { .dot_limit = 112000,
216 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 217};
218
273e27ca 219
e4b36699 220static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 221 .dot = { .min = 25000, .max = 270000 },
222 .vco = { .min = 1750000, .max = 3500000},
223 .n = { .min = 1, .max = 4 },
224 .m = { .min = 104, .max = 138 },
225 .m1 = { .min = 17, .max = 23 },
226 .m2 = { .min = 5, .max = 11 },
227 .p = { .min = 10, .max = 30 },
228 .p1 = { .min = 1, .max = 3},
229 .p2 = { .dot_limit = 270000,
230 .p2_slow = 10,
231 .p2_fast = 10
044c7c41 232 },
e4b36699
KP		 233};
234
235static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 236 .dot = { .min = 22000, .max = 400000 },
237 .vco = { .min = 1750000, .max = 3500000},
238 .n = { .min = 1, .max = 4 },
239 .m = { .min = 104, .max = 138 },
240 .m1 = { .min = 16, .max = 23 },
241 .m2 = { .min = 5, .max = 11 },
242 .p = { .min = 5, .max = 80 },
243 .p1 = { .min = 1, .max = 8},
244 .p2 = { .dot_limit = 165000,
245 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 246};
247
248static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 249 .dot = { .min = 20000, .max = 115000 },
250 .vco = { .min = 1750000, .max = 3500000 },
251 .n = { .min = 1, .max = 3 },
252 .m = { .min = 104, .max = 138 },
253 .m1 = { .min = 17, .max = 23 },
254 .m2 = { .min = 5, .max = 11 },
255 .p = { .min = 28, .max = 112 },
256 .p1 = { .min = 2, .max = 8 },
257 .p2 = { .dot_limit = 0,
258 .p2_slow = 14, .p2_fast = 14
044c7c41 259 },
e4b36699
KP		 260};
261
262static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 263 .dot = { .min = 80000, .max = 224000 },
264 .vco = { .min = 1750000, .max = 3500000 },
265 .n = { .min = 1, .max = 3 },
266 .m = { .min = 104, .max = 138 },
267 .m1 = { .min = 17, .max = 23 },
268 .m2 = { .min = 5, .max = 11 },
269 .p = { .min = 14, .max = 42 },
270 .p1 = { .min = 2, .max = 6 },
271 .p2 = { .dot_limit = 0,
272 .p2_slow = 7, .p2_fast = 7
044c7c41 273 },
e4b36699
KP		 274};
275
f2b115e6 276static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 277 .dot = { .min = 20000, .max = 400000},
278 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 279 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 280 .n = { .min = 3, .max = 6 },
281 .m = { .min = 2, .max = 256 },
273e27ca 282 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 283 .m1 = { .min = 0, .max = 0 },
284 .m2 = { .min = 0, .max = 254 },
285 .p = { .min = 5, .max = 80 },
286 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 287 .p2 = { .dot_limit = 200000,
288 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 289};
290
f2b115e6 291static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 292 .dot = { .min = 20000, .max = 400000 },
293 .vco = { .min = 1700000, .max = 3500000 },
294 .n = { .min = 3, .max = 6 },
295 .m = { .min = 2, .max = 256 },
296 .m1 = { .min = 0, .max = 0 },
297 .m2 = { .min = 0, .max = 254 },
298 .p = { .min = 7, .max = 112 },
299 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 300 .p2 = { .dot_limit = 112000,
301 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 302};
303
273e27ca
EA		 304/* Ironlake / Sandybridge
305 *
306 * We calculate clock using (register_value + 2) for N/M1/M2, so here
307 * the range value for them is (actual_value - 2).
308 */
b91ad0ec 309static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 310 .dot = { .min = 25000, .max = 350000 },
311 .vco = { .min = 1760000, .max = 3510000 },
312 .n = { .min = 1, .max = 5 },
313 .m = { .min = 79, .max = 127 },
314 .m1 = { .min = 12, .max = 22 },
315 .m2 = { .min = 5, .max = 9 },
316 .p = { .min = 5, .max = 80 },
317 .p1 = { .min = 1, .max = 8 },
318 .p2 = { .dot_limit = 225000,
319 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 320};
321
b91ad0ec 322static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 323 .dot = { .min = 25000, .max = 350000 },
324 .vco = { .min = 1760000, .max = 3510000 },
325 .n = { .min = 1, .max = 3 },
326 .m = { .min = 79, .max = 118 },
327 .m1 = { .min = 12, .max = 22 },
328 .m2 = { .min = 5, .max = 9 },
329 .p = { .min = 28, .max = 112 },
330 .p1 = { .min = 2, .max = 8 },
331 .p2 = { .dot_limit = 225000,
332 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 333};
334
335static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 3 },
339 .m = { .min = 79, .max = 127 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 14, .max = 56 },
343 .p1 = { .min = 2, .max = 8 },
344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 346};
347
273e27ca 348/* LVDS 100mhz refclk limits. */
b91ad0ec 349static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000 },
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 79, .max = 126 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 28, .max = 112 },
0206e353 357 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 358 .p2 = { .dot_limit = 225000,
359 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 360};
361
362static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 363 .dot = { .min = 25000, .max = 350000 },
364 .vco = { .min = 1760000, .max = 3510000 },
365 .n = { .min = 1, .max = 3 },
366 .m = { .min = 79, .max = 126 },
367 .m1 = { .min = 12, .max = 22 },
368 .m2 = { .min = 5, .max = 9 },
369 .p = { .min = 14, .max = 42 },
0206e353 370 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 371 .p2 = { .dot_limit = 225000,
372 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 373};
374
dc730512 375static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 376 /*
377 * These are the data rate limits (measured in fast clocks)
378 * since those are the strictest limits we have. The fast
379 * clock and actual rate limits are more relaxed, so checking
380 * them would make no difference.
381 */
382 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 383 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 384 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 385 .m1 = { .min = 2, .max = 3 },
386 .m2 = { .min = 11, .max = 156 },
b99ab663 387 .p1 = { .min = 2, .max = 3 },
5fdc9c49 388 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 389};
390
ef9348c8
CML		 391static const intel_limit_t intel_limits_chv = {
392 /*
393 * These are the data rate limits (measured in fast clocks)
394 * since those are the strictest limits we have. The fast
395 * clock and actual rate limits are more relaxed, so checking
396 * them would make no difference.
397 */
398 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 399 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 400 .n = { .min = 1, .max = 1 },
401 .m1 = { .min = 2, .max = 2 },
402 .m2 = { .min = 24 << 22, .max = 175 << 22 },
403 .p1 = { .min = 2, .max = 4 },
404 .p2 = { .p2_slow = 1, .p2_fast = 14 },
405};
406
5ab7b0b7
ID		 407static const intel_limit_t intel_limits_bxt = {
408 /* FIXME: find real dot limits */
409 .dot = { .min = 0, .max = INT_MAX },
410 .vco = { .min = 4800000, .max = 6480000 },
411 .n = { .min = 1, .max = 1 },
412 .m1 = { .min = 2, .max = 2 },
413 /* FIXME: find real m2 limits */
414 .m2 = { .min = 2 << 22, .max = 255 << 22 },
415 .p1 = { .min = 2, .max = 4 },
416 .p2 = { .p2_slow = 1, .p2_fast = 20 },
417};
418
6b4bf1c4
VS		 419static void vlv_clock(int refclk, intel_clock_t *clock)
420{
421 clock->m = clock->m1 * clock->m2;
422 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 423 if (WARN_ON(clock->n == 0 || clock->p == 0))
424 return;
fb03ac01
VS		 425 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
426 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 427}
428
e0638cdf
PZ		 429/**
430 * Returns whether any output on the specified pipe is of the specified type
431 */
4093561b 432bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 433{
409ee761 434 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 435 struct intel_encoder *encoder;
436
409ee761 437 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 438 if (encoder->type == type)
439 return true;
440
441 return false;
442}
443
d0737e1d
ACO		 444/**
445 * Returns whether any output on the specified pipe will have the specified
446 * type after a staged modeset is complete, i.e., the same as
447 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
448 * encoder->crtc.
449 */
a93e255f
ACO		 450static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
451 int type)
d0737e1d 452{
a93e255f
ACO		 453 struct drm_atomic_state *state = crtc_state->base.state;
454 struct drm_connector_state *connector_state;
d0737e1d 455 struct intel_encoder *encoder;
a93e255f
ACO		 456 int i, num_connectors = 0;
457
458 for (i = 0; i < state->num_connector; i++) {
459 if (!state->connectors[i])
460 continue;
461
462 connector_state = state->connector_states[i];
463 if (connector_state->crtc != crtc_state->base.crtc)
464 continue;
465
466 num_connectors++;
d0737e1d 467
a93e255f
ACO		 468 encoder = to_intel_encoder(connector_state->best_encoder);
469 if (encoder->type == type)
d0737e1d 470 return true;
a93e255f
ACO		 471 }
472
473 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 474
475 return false;
476}
477
a93e255f
ACO		 478static const intel_limit_t *
479intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 480{
a93e255f 481 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 482 const intel_limit_t *limit;
b91ad0ec 483
a93e255f 484 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 485 if (intel_is_dual_link_lvds(dev)) {
1b894b59 486 if (refclk == 100000)
b91ad0ec
ZW		 487 limit = &intel_limits_ironlake_dual_lvds_100m;
488 else
489 limit = &intel_limits_ironlake_dual_lvds;
490 } else {
1b894b59 491 if (refclk == 100000)
b91ad0ec
ZW		 492 limit = &intel_limits_ironlake_single_lvds_100m;
493 else
494 limit = &intel_limits_ironlake_single_lvds;
495 }
c6bb3538 496 } else
b91ad0ec 497 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 498
499 return limit;
500}
501
a93e255f
ACO		 502static const intel_limit_t *
503intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 504{
a93e255f 505 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 506 const intel_limit_t *limit;
507
a93e255f 508 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 509 if (intel_is_dual_link_lvds(dev))
e4b36699 510 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 511 else
e4b36699 512 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 513 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
514 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 515 limit = &intel_limits_g4x_hdmi;
a93e255f 516 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 517 limit = &intel_limits_g4x_sdvo;
044c7c41 518 } else /* The option is for other outputs */
e4b36699 519 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 520
521 return limit;
522}
523
a93e255f
ACO		 524static const intel_limit_t *
525intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 526{
a93e255f 527 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 528 const intel_limit_t *limit;
529
5ab7b0b7
ID		 530 if (IS_BROXTON(dev))
531 limit = &intel_limits_bxt;
532 else if (HAS_PCH_SPLIT(dev))
a93e255f 533 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 534 else if (IS_G4X(dev)) {
a93e255f 535 limit = intel_g4x_limit(crtc_state);
f2b115e6 536 } else if (IS_PINEVIEW(dev)) {
a93e255f 537 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 538 limit = &intel_limits_pineview_lvds;
2177832f 539 else
f2b115e6 540 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 541 } else if (IS_CHERRYVIEW(dev)) {
542 limit = &intel_limits_chv;
a0c4da24 543 } else if (IS_VALLEYVIEW(dev)) {
dc730512 544 limit = &intel_limits_vlv;
a6c45cf0 545 } else if (!IS_GEN2(dev)) {
a93e255f 546 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 547 limit = &intel_limits_i9xx_lvds;
548 else
549 limit = &intel_limits_i9xx_sdvo;
79e53945 550 } else {
a93e255f 551 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 552 limit = &intel_limits_i8xx_lvds;
a93e255f 553 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 554 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 555 else
556 limit = &intel_limits_i8xx_dac;
79e53945
JB		 557 }
558 return limit;
559}
560
f2b115e6
AJ		 561/* m1 is reserved as 0 in Pineview, n is a ring counter */
562static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 563{
2177832f
SL		 564 clock->m = clock->m2 + 2;
565 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 566 if (WARN_ON(clock->n == 0 || clock->p == 0))
567 return;
fb03ac01
VS		 568 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
569 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 570}
571
7429e9d4
DV		 572static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
573{
574 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
575}
576
ac58c3f0 577static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 578{
7429e9d4 579 clock->m = i9xx_dpll_compute_m(clock);
79e53945 580 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 581 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
582 return;
fb03ac01
VS		 583 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
584 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 585}
586
ef9348c8
CML		 587static void chv_clock(int refclk, intel_clock_t *clock)
588{
589 clock->m = clock->m1 * clock->m2;
590 clock->p = clock->p1 * clock->p2;
591 if (WARN_ON(clock->n == 0 || clock->p == 0))
592 return;
593 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
594 clock->n << 22);
595 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
596}
597
7c04d1d9 598#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 599/**
600 * Returns whether the given set of divisors are valid for a given refclk with
601 * the given connectors.
602 */
603
1b894b59
CW		 604static bool intel_PLL_is_valid(struct drm_device *dev,
605 const intel_limit_t *limit,
606 const intel_clock_t *clock)
79e53945 607{
f01b7962
VS		 608 if (clock->n < limit->n.min || limit->n.max < clock->n)
609 INTELPllInvalid("n out of range\n");
79e53945 610 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 611 INTELPllInvalid("p1 out of range\n");
79e53945 612 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 613 INTELPllInvalid("m2 out of range\n");
79e53945 614 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 615 INTELPllInvalid("m1 out of range\n");
f01b7962 616
5ab7b0b7 617 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 618 if (clock->m1 <= clock->m2)
619 INTELPllInvalid("m1 <= m2\n");
620
5ab7b0b7 621 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 622 if (clock->p < limit->p.min || limit->p.max < clock->p)
623 INTELPllInvalid("p out of range\n");
624 if (clock->m < limit->m.min || limit->m.max < clock->m)
625 INTELPllInvalid("m out of range\n");
626 }
627
79e53945 628 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 629 INTELPllInvalid("vco out of range\n");
79e53945
JB		 630 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
631 * connector, etc., rather than just a single range.
632 */
633 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 634 INTELPllInvalid("dot out of range\n");
79e53945
JB		 635
636 return true;
637}
638
d4906093 639static bool
a93e255f
ACO		 640i9xx_find_best_dpll(const intel_limit_t *limit,
641 struct intel_crtc_state *crtc_state,
cec2f356
SP		 642 int target, int refclk, intel_clock_t *match_clock,
643 intel_clock_t *best_clock)
79e53945 644{
a93e255f 645 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 646 struct drm_device *dev = crtc->base.dev;
79e53945 647 intel_clock_t clock;
79e53945
JB		 648 int err = target;
649
a93e255f 650 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 651 /*
a210b028
DV		 652 * For LVDS just rely on its current settings for dual-channel.
653 * We haven't figured out how to reliably set up different
654 * single/dual channel state, if we even can.
79e53945 655 */
1974cad0 656 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 657 clock.p2 = limit->p2.p2_fast;
658 else
659 clock.p2 = limit->p2.p2_slow;
660 } else {
661 if (target < limit->p2.dot_limit)
662 clock.p2 = limit->p2.p2_slow;
663 else
664 clock.p2 = limit->p2.p2_fast;
665 }
666
0206e353 667 memset(best_clock, 0, sizeof(*best_clock));
79e53945 668
42158660
ZY		 669 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
670 clock.m1++) {
671 for (clock.m2 = limit->m2.min;
672 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 673 if (clock.m2 >= clock.m1)
42158660
ZY		 674 break;
675 for (clock.n = limit->n.min;
676 clock.n <= limit->n.max; clock.n++) {
677 for (clock.p1 = limit->p1.min;
678 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 679 int this_err;
680
ac58c3f0
DV		 681 i9xx_clock(refclk, &clock);
682 if (!intel_PLL_is_valid(dev, limit,
683 &clock))
684 continue;
685 if (match_clock &&
686 clock.p != match_clock->p)
687 continue;
688
689 this_err = abs(clock.dot - target);
690 if (this_err < err) {
691 *best_clock = clock;
692 err = this_err;
693 }
694 }
695 }
696 }
697 }
698
699 return (err != target);
700}
701
702static bool
a93e255f
ACO		 703pnv_find_best_dpll(const intel_limit_t *limit,
704 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
79e53945 707{
a93e255f 708 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 709 struct drm_device *dev = crtc->base.dev;
79e53945 710 intel_clock_t clock;
79e53945
JB		 711 int err = target;
712
a93e255f 713 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 714 /*
a210b028
DV		 715 * For LVDS just rely on its current settings for dual-channel.
716 * We haven't figured out how to reliably set up different
717 * single/dual channel state, if we even can.
79e53945 718 */
1974cad0 719 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 720 clock.p2 = limit->p2.p2_fast;
721 else
722 clock.p2 = limit->p2.p2_slow;
723 } else {
724 if (target < limit->p2.dot_limit)
725 clock.p2 = limit->p2.p2_slow;
726 else
727 clock.p2 = limit->p2.p2_fast;
728 }
729
0206e353 730 memset(best_clock, 0, sizeof(*best_clock));
79e53945 731
42158660
ZY		 732 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
733 clock.m1++) {
734 for (clock.m2 = limit->m2.min;
735 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 736 for (clock.n = limit->n.min;
737 clock.n <= limit->n.max; clock.n++) {
738 for (clock.p1 = limit->p1.min;
739 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 740 int this_err;
741
ac58c3f0 742 pineview_clock(refclk, &clock);
1b894b59
CW		 743 if (!intel_PLL_is_valid(dev, limit,
744 &clock))
79e53945 745 continue;
cec2f356
SP		 746 if (match_clock &&
747 clock.p != match_clock->p)
748 continue;
79e53945
JB		 749
750 this_err = abs(clock.dot - target);
751 if (this_err < err) {
752 *best_clock = clock;
753 err = this_err;
754 }
755 }
756 }
757 }
758 }
759
760 return (err != target);
761}
762
d4906093 763static bool
a93e255f
ACO		 764g4x_find_best_dpll(const intel_limit_t *limit,
765 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 766 int target, int refclk, intel_clock_t *match_clock,
767 intel_clock_t *best_clock)
d4906093 768{
a93e255f 769 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 770 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 771 intel_clock_t clock;
772 int max_n;
773 bool found;
6ba770dc
AJ		 774 /* approximately equals target * 0.00585 */
775 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 776 found = false;
777
a93e255f 778 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 779 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 780 clock.p2 = limit->p2.p2_fast;
781 else
782 clock.p2 = limit->p2.p2_slow;
783 } else {
784 if (target < limit->p2.dot_limit)
785 clock.p2 = limit->p2.p2_slow;
786 else
787 clock.p2 = limit->p2.p2_fast;
788 }
789
790 memset(best_clock, 0, sizeof(*best_clock));
791 max_n = limit->n.max;
f77f13e2 792 /* based on hardware requirement, prefer smaller n to precision */
d4906093 793 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 794 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 795 for (clock.m1 = limit->m1.max;
796 clock.m1 >= limit->m1.min; clock.m1--) {
797 for (clock.m2 = limit->m2.max;
798 clock.m2 >= limit->m2.min; clock.m2--) {
799 for (clock.p1 = limit->p1.max;
800 clock.p1 >= limit->p1.min; clock.p1--) {
801 int this_err;
802
ac58c3f0 803 i9xx_clock(refclk, &clock);
1b894b59
CW		 804 if (!intel_PLL_is_valid(dev, limit,
805 &clock))
d4906093 806 continue;
1b894b59
CW		 807
808 this_err = abs(clock.dot - target);
d4906093
ML		 809 if (this_err < err_most) {
810 *best_clock = clock;
811 err_most = this_err;
812 max_n = clock.n;
813 found = true;
814 }
815 }
816 }
817 }
818 }
2c07245f
ZW		 819 return found;
820}
821
d5dd62bd
ID		 822/*
823 * Check if the calculated PLL configuration is more optimal compared to the
824 * best configuration and error found so far. Return the calculated error.
825 */
826static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
827 const intel_clock_t *calculated_clock,
828 const intel_clock_t *best_clock,
829 unsigned int best_error_ppm,
830 unsigned int *error_ppm)
831{
9ca3ba01
ID		 832 /*
833 * For CHV ignore the error and consider only the P value.
834 * Prefer a bigger P value based on HW requirements.
835 */
836 if (IS_CHERRYVIEW(dev)) {
837 *error_ppm = 0;
838
839 return calculated_clock->p > best_clock->p;
840 }
841
24be4e46
ID		 842 if (WARN_ON_ONCE(!target_freq))
843 return false;
844
d5dd62bd
ID		 845 *error_ppm = div_u64(1000000ULL *
846 abs(target_freq - calculated_clock->dot),
847 target_freq);
848 /*
849 * Prefer a better P value over a better (smaller) error if the error
850 * is small. Ensure this preference for future configurations too by
851 * setting the error to 0.
852 */
853 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
854 *error_ppm = 0;
855
856 return true;
857 }
858
859 return *error_ppm + 10 < best_error_ppm;
860}
861
a0c4da24 862static bool
a93e255f
ACO		 863vlv_find_best_dpll(const intel_limit_t *limit,
864 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 865 int target, int refclk, intel_clock_t *match_clock,
866 intel_clock_t *best_clock)
a0c4da24 867{
a93e255f 868 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 869 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 870 intel_clock_t clock;
69e4f900 871 unsigned int bestppm = 1000000;
27e639bf
VS		 872 /* min update 19.2 MHz */
873 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 874 bool found = false;
a0c4da24 875
6b4bf1c4
VS		 876 target *= 5; /* fast clock */
877
878 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 879
880 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 881 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 882 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 883 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 884 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 885 clock.p = clock.p1 * clock.p2;
a0c4da24 886 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 887 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 888 unsigned int ppm;
69e4f900 889
6b4bf1c4
VS		 890 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
891 refclk * clock.m1);
892
893 vlv_clock(refclk, &clock);
43b0ac53 894
f01b7962
VS		 895 if (!intel_PLL_is_valid(dev, limit,
896 &clock))
43b0ac53
VS		 897 continue;
898
d5dd62bd
ID		 899 if (!vlv_PLL_is_optimal(dev, target,
900 &clock,
901 best_clock,
902 bestppm, &ppm))
903 continue;
6b4bf1c4 904
d5dd62bd
ID		 905 *best_clock = clock;
906 bestppm = ppm;
907 found = true;
a0c4da24
JB		 908 }
909 }
910 }
911 }
a0c4da24 912
49e497ef 913 return found;
a0c4da24 914}
a4fc5ed6 915
ef9348c8 916static bool
a93e255f
ACO		 917chv_find_best_dpll(const intel_limit_t *limit,
918 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 919 int target, int refclk, intel_clock_t *match_clock,
920 intel_clock_t *best_clock)
921{
a93e255f 922 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 923 struct drm_device *dev = crtc->base.dev;
9ca3ba01 924 unsigned int best_error_ppm;
ef9348c8
CML		 925 intel_clock_t clock;
926 uint64_t m2;
927 int found = false;
928
929 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 930 best_error_ppm = 1000000;
ef9348c8
CML		 931
932 /*
933 * Based on hardware doc, the n always set to 1, and m1 always
934 * set to 2. If requires to support 200Mhz refclk, we need to
935 * revisit this because n may not 1 anymore.
936 */
937 clock.n = 1, clock.m1 = 2;
938 target *= 5; /* fast clock */
939
940 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
941 for (clock.p2 = limit->p2.p2_fast;
942 clock.p2 >= limit->p2.p2_slow;
943 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 944 unsigned int error_ppm;
ef9348c8
CML		 945
946 clock.p = clock.p1 * clock.p2;
947
948 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
949 clock.n) << 22, refclk * clock.m1);
950
951 if (m2 > INT_MAX/clock.m1)
952 continue;
953
954 clock.m2 = m2;
955
956 chv_clock(refclk, &clock);
957
958 if (!intel_PLL_is_valid(dev, limit, &clock))
959 continue;
960
9ca3ba01
ID		 961 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
962 best_error_ppm, &error_ppm))
963 continue;
964
965 *best_clock = clock;
966 best_error_ppm = error_ppm;
967 found = true;
ef9348c8
CML		 968 }
969 }
970
971 return found;
972}
973
5ab7b0b7
ID		 974bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
975 intel_clock_t *best_clock)
976{
977 int refclk = i9xx_get_refclk(crtc_state, 0);
978
979 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
980 target_clock, refclk, NULL, best_clock);
981}
982
20ddf665
VS		 983bool intel_crtc_active(struct drm_crtc *crtc)
984{
985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
986
987 /* Be paranoid as we can arrive here with only partial
988 * state retrieved from the hardware during setup.
989 *
241bfc38 990 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 991 * as Haswell has gained clock readout/fastboot support.
992 *
66e514c1 993 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 994 * properly reconstruct framebuffers.
c3d1f436
MR		 995 *
996 * FIXME: The intel_crtc->active here should be switched to
997 * crtc->state->active once we have proper CRTC states wired up
998 * for atomic.
20ddf665 999 */
c3d1f436 1000 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1001 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1002}
1003
a5c961d1
PZ		 1004enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1005 enum pipe pipe)
1006{
1007 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1008 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1009
6e3c9717 1010 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1011}
1012
fbf49ea2
VS		 1013static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1014{
1015 struct drm_i915_private *dev_priv = dev->dev_private;
1016 u32 reg = PIPEDSL(pipe);
1017 u32 line1, line2;
1018 u32 line_mask;
1019
1020 if (IS_GEN2(dev))
1021 line_mask = DSL_LINEMASK_GEN2;
1022 else
1023 line_mask = DSL_LINEMASK_GEN3;
1024
1025 line1 = I915_READ(reg) & line_mask;
1026 mdelay(5);
1027 line2 = I915_READ(reg) & line_mask;
1028
1029 return line1 == line2;
1030}
1031
ab7ad7f6
KP		 1032/*
1033 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1034 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1035 *
1036 * After disabling a pipe, we can't wait for vblank in the usual way,
1037 * spinning on the vblank interrupt status bit, since we won't actually
1038 * see an interrupt when the pipe is disabled.
1039 *
ab7ad7f6
KP		 1040 * On Gen4 and above:
1041 * wait for the pipe register state bit to turn off
1042 *
1043 * Otherwise:
1044 * wait for the display line value to settle (it usually
1045 * ends up stopping at the start of the next frame).
58e10eb9 1046 *
9d0498a2 1047 */
575f7ab7 1048static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1049{
575f7ab7 1050 struct drm_device *dev = crtc->base.dev;
9d0498a2 1051 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1052 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1053 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1054
1055 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1056 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1057
1058 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1059 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1060 100))
284637d9 1061 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1062 } else {
ab7ad7f6 1063 /* Wait for the display line to settle */
fbf49ea2 1064 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1065 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1066 }
79e53945
JB		 1067}
1068
b0ea7d37
DL		 1069/*
1070 * ibx_digital_port_connected - is the specified port connected?
1071 * @dev_priv: i915 private structure
1072 * @port: the port to test
1073 *
1074 * Returns true if @port is connected, false otherwise.
1075 */
1076bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1077 struct intel_digital_port *port)
1078{
1079 u32 bit;
1080
c36346e3 1081 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1082 switch (port->port) {
c36346e3
DL		 1083 case PORT_B:
1084 bit = SDE_PORTB_HOTPLUG;
1085 break;
1086 case PORT_C:
1087 bit = SDE_PORTC_HOTPLUG;
1088 break;
1089 case PORT_D:
1090 bit = SDE_PORTD_HOTPLUG;
1091 break;
1092 default:
1093 return true;
1094 }
1095 } else {
eba905b2 1096 switch (port->port) {
c36346e3
DL		 1097 case PORT_B:
1098 bit = SDE_PORTB_HOTPLUG_CPT;
1099 break;
1100 case PORT_C:
1101 bit = SDE_PORTC_HOTPLUG_CPT;
1102 break;
1103 case PORT_D:
1104 bit = SDE_PORTD_HOTPLUG_CPT;
1105 break;
1106 default:
1107 return true;
1108 }
b0ea7d37
DL		 1109 }
1110
1111 return I915_READ(SDEISR) & bit;
1112}
1113
b24e7179
JB		 1114static const char *state_string(bool enabled)
1115{
1116 return enabled ? "on" : "off";
1117}
1118
1119/* Only for pre-ILK configs */
55607e8a
DV		 1120void assert_pll(struct drm_i915_private *dev_priv,
1121 enum pipe pipe, bool state)
b24e7179
JB		 1122{
1123 int reg;
1124 u32 val;
1125 bool cur_state;
1126
1127 reg = DPLL(pipe);
1128 val = I915_READ(reg);
1129 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1130 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1131 "PLL state assertion failure (expected %s, current %s)\n",
1132 state_string(state), state_string(cur_state));
1133}
b24e7179 1134
23538ef1
JN		 1135/* XXX: the dsi pll is shared between MIPI DSI ports */
1136static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1137{
1138 u32 val;
1139 bool cur_state;
1140
1141 mutex_lock(&dev_priv->dpio_lock);
1142 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1143 mutex_unlock(&dev_priv->dpio_lock);
1144
1145 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1146 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1147 "DSI PLL state assertion failure (expected %s, current %s)\n",
1148 state_string(state), state_string(cur_state));
1149}
1150#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1151#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1152
55607e8a 1153struct intel_shared_dpll *
e2b78267
DV		 1154intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1155{
1156 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1157
6e3c9717 1158 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1159 return NULL;
1160
6e3c9717 1161 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1162}
1163
040484af 1164/* For ILK+ */
55607e8a
DV		 1165void assert_shared_dpll(struct drm_i915_private *dev_priv,
1166 struct intel_shared_dpll *pll,
1167 bool state)
040484af 1168{
040484af 1169 bool cur_state;
5358901f 1170 struct intel_dpll_hw_state hw_state;
040484af 1171
92b27b08 1172 if (WARN (!pll,
46edb027 1173 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1174 return;
ee7b9f93 1175
5358901f 1176 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1177 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1178 "%s assertion failure (expected %s, current %s)\n",
1179 pll->name, state_string(state), state_string(cur_state));
040484af 1180}
040484af
JB		 1181
1182static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1183 enum pipe pipe, bool state)
1184{
1185 int reg;
1186 u32 val;
1187 bool cur_state;
ad80a810
PZ		 1188 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1189 pipe);
040484af 1190
affa9354
PZ		 1191 if (HAS_DDI(dev_priv->dev)) {
1192 /* DDI does not have a specific FDI_TX register */
ad80a810 1193 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1194 val = I915_READ(reg);
ad80a810 1195 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1196 } else {
1197 reg = FDI_TX_CTL(pipe);
1198 val = I915_READ(reg);
1199 cur_state = !!(val & FDI_TX_ENABLE);
1200 }
e2c719b7 1201 I915_STATE_WARN(cur_state != state,
040484af
JB		 1202 "FDI TX state assertion failure (expected %s, current %s)\n",
1203 state_string(state), state_string(cur_state));
1204}
1205#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1206#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1207
1208static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1209 enum pipe pipe, bool state)
1210{
1211 int reg;
1212 u32 val;
1213 bool cur_state;
1214
d63fa0dc
PZ		 1215 reg = FDI_RX_CTL(pipe);
1216 val = I915_READ(reg);
1217 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1218 I915_STATE_WARN(cur_state != state,
040484af
JB		 1219 "FDI RX state assertion failure (expected %s, current %s)\n",
1220 state_string(state), state_string(cur_state));
1221}
1222#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1223#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1224
1225static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1226 enum pipe pipe)
1227{
1228 int reg;
1229 u32 val;
1230
1231 /* ILK FDI PLL is always enabled */
3d13ef2e 1232 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1233 return;
1234
bf507ef7 1235 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1236 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1237 return;
1238
040484af
JB		 1239 reg = FDI_TX_CTL(pipe);
1240 val = I915_READ(reg);
e2c719b7 1241 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1242}
1243
55607e8a
DV		 1244void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1245 enum pipe pipe, bool state)
040484af
JB		 1246{
1247 int reg;
1248 u32 val;
55607e8a 1249 bool cur_state;
040484af
JB		 1250
1251 reg = FDI_RX_CTL(pipe);
1252 val = I915_READ(reg);
55607e8a 1253 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1254 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1255 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1256 state_string(state), state_string(cur_state));
040484af
JB		 1257}
1258
b680c37a
DV		 1259void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1260 enum pipe pipe)
ea0760cf 1261{
bedd4dba
JN		 1262 struct drm_device *dev = dev_priv->dev;
1263 int pp_reg;
ea0760cf
JB		 1264 u32 val;
1265 enum pipe panel_pipe = PIPE_A;
0de3b485 1266 bool locked = true;
ea0760cf 1267
bedd4dba
JN		 1268 if (WARN_ON(HAS_DDI(dev)))
1269 return;
1270
1271 if (HAS_PCH_SPLIT(dev)) {
1272 u32 port_sel;
1273
ea0760cf 1274 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1275 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1276
1277 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1278 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1279 panel_pipe = PIPE_B;
1280 /* XXX: else fix for eDP */
1281 } else if (IS_VALLEYVIEW(dev)) {
1282 /* presumably write lock depends on pipe, not port select */
1283 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1284 panel_pipe = pipe;
ea0760cf
JB		 1285 } else {
1286 pp_reg = PP_CONTROL;
bedd4dba
JN		 1287 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1288 panel_pipe = PIPE_B;
ea0760cf
JB		 1289 }
1290
1291 val = I915_READ(pp_reg);
1292 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1293 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1294 locked = false;
1295
e2c719b7 1296 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1297 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1298 pipe_name(pipe));
ea0760cf
JB		 1299}
1300
93ce0ba6
JN		 1301static void assert_cursor(struct drm_i915_private *dev_priv,
1302 enum pipe pipe, bool state)
1303{
1304 struct drm_device *dev = dev_priv->dev;
1305 bool cur_state;
1306
d9d82081 1307 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1308 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1309 else
5efb3e28 1310 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1311
e2c719b7 1312 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1313 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1314 pipe_name(pipe), state_string(state), state_string(cur_state));
1315}
1316#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1317#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1318
b840d907
JB		 1319void assert_pipe(struct drm_i915_private *dev_priv,
1320 enum pipe pipe, bool state)
b24e7179
JB		 1321{
1322 int reg;
1323 u32 val;
63d7bbe9 1324 bool cur_state;
702e7a56
PZ		 1325 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1326 pipe);
b24e7179 1327
b6b5d049
VS		 1328 /* if we need the pipe quirk it must be always on */
1329 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1330 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1331 state = true;
1332
f458ebbc 1333 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1334 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1335 cur_state = false;
1336 } else {
1337 reg = PIPECONF(cpu_transcoder);
1338 val = I915_READ(reg);
1339 cur_state = !!(val & PIPECONF_ENABLE);
1340 }
1341
e2c719b7 1342 I915_STATE_WARN(cur_state != state,
63d7bbe9 1343 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1344 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1345}
1346
931872fc
CW		 1347static void assert_plane(struct drm_i915_private *dev_priv,
1348 enum plane plane, bool state)
b24e7179
JB		 1349{
1350 int reg;
1351 u32 val;
931872fc 1352 bool cur_state;
b24e7179
JB		 1353
1354 reg = DSPCNTR(plane);
1355 val = I915_READ(reg);
931872fc 1356 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1357 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1358 "plane %c assertion failure (expected %s, current %s)\n",
1359 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1360}
1361
931872fc
CW		 1362#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1363#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1364
b24e7179
JB		 1365static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1366 enum pipe pipe)
1367{
653e1026 1368 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1369 int reg, i;
1370 u32 val;
1371 int cur_pipe;
1372
653e1026
VS		 1373 /* Primary planes are fixed to pipes on gen4+ */
1374 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1375 reg = DSPCNTR(pipe);
1376 val = I915_READ(reg);
e2c719b7 1377 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1378 "plane %c assertion failure, should be disabled but not\n",
1379 plane_name(pipe));
19ec1358 1380 return;
28c05794 1381 }
19ec1358 1382
b24e7179 1383 /* Need to check both planes against the pipe */
055e393f 1384 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1385 reg = DSPCNTR(i);
1386 val = I915_READ(reg);
1387 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1388 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1389 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1390 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1391 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1392 }
1393}
1394
19332d7a
JB		 1395static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe)
1397{
20674eef 1398 struct drm_device *dev = dev_priv->dev;
1fe47785 1399 int reg, sprite;
19332d7a
JB		 1400 u32 val;
1401
7feb8b88 1402 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1403 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1404 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1405 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1406 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1407 sprite, pipe_name(pipe));
1408 }
1409 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1410 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1411 reg = SPCNTR(pipe, sprite);
20674eef 1412 val = I915_READ(reg);
e2c719b7 1413 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1414 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1415 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1416 }
1417 } else if (INTEL_INFO(dev)->gen >= 7) {
1418 reg = SPRCTL(pipe);
19332d7a 1419 val = I915_READ(reg);
e2c719b7 1420 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1421 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1422 plane_name(pipe), pipe_name(pipe));
1423 } else if (INTEL_INFO(dev)->gen >= 5) {
1424 reg = DVSCNTR(pipe);
19332d7a 1425 val = I915_READ(reg);
e2c719b7 1426 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1427 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1428 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1429 }
1430}
1431
08c71e5e
VS		 1432static void assert_vblank_disabled(struct drm_crtc *crtc)
1433{
e2c719b7 1434 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1435 drm_crtc_vblank_put(crtc);
1436}
1437
89eff4be 1438static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1439{
1440 u32 val;
1441 bool enabled;
1442
e2c719b7 1443 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1444
92f2584a
JB		 1445 val = I915_READ(PCH_DREF_CONTROL);
1446 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1447 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1448 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1449}
1450
ab9412ba
DV		 1451static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1452 enum pipe pipe)
92f2584a
JB		 1453{
1454 int reg;
1455 u32 val;
1456 bool enabled;
1457
ab9412ba 1458 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1459 val = I915_READ(reg);
1460 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1461 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1462 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1463 pipe_name(pipe));
92f2584a
JB		 1464}
1465
4e634389
KP		 1466static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1467 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1468{
1469 if ((val & DP_PORT_EN) == 0)
1470 return false;
1471
1472 if (HAS_PCH_CPT(dev_priv->dev)) {
1473 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1474 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1475 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1476 return false;
44f37d1f
CML		 1477 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1478 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1479 return false;
f0575e92
KP		 1480 } else {
1481 if ((val & DP_PIPE_MASK) != (pipe << 30))
1482 return false;
1483 }
1484 return true;
1485}
1486
1519b995
KP		 1487static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1488 enum pipe pipe, u32 val)
1489{
dc0fa718 1490 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1491 return false;
1492
1493 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1494 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1495 return false;
44f37d1f
CML		 1496 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1497 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1498 return false;
1519b995 1499 } else {
dc0fa718 1500 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1501 return false;
1502 }
1503 return true;
1504}
1505
1506static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1507 enum pipe pipe, u32 val)
1508{
1509 if ((val & LVDS_PORT_EN) == 0)
1510 return false;
1511
1512 if (HAS_PCH_CPT(dev_priv->dev)) {
1513 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1514 return false;
1515 } else {
1516 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1517 return false;
1518 }
1519 return true;
1520}
1521
1522static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1523 enum pipe pipe, u32 val)
1524{
1525 if ((val & ADPA_DAC_ENABLE) == 0)
1526 return false;
1527 if (HAS_PCH_CPT(dev_priv->dev)) {
1528 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1529 return false;
1530 } else {
1531 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1532 return false;
1533 }
1534 return true;
1535}
1536
291906f1 1537static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1538 enum pipe pipe, int reg, u32 port_sel)
291906f1 1539{
47a05eca 1540 u32 val = I915_READ(reg);
e2c719b7 1541 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1542 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1543 reg, pipe_name(pipe));
de9a35ab 1544
e2c719b7 1545 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1546 && (val & DP_PIPEB_SELECT),
de9a35ab 1547 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1548}
1549
1550static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1551 enum pipe pipe, int reg)
1552{
47a05eca 1553 u32 val = I915_READ(reg);
e2c719b7 1554 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1555 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1556 reg, pipe_name(pipe));
de9a35ab 1557
e2c719b7 1558 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1559 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1560 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1561}
1562
1563static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1564 enum pipe pipe)
1565{
1566 int reg;
1567 u32 val;
291906f1 1568
f0575e92
KP		 1569 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1570 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1571 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1572
1573 reg = PCH_ADPA;
1574 val = I915_READ(reg);
e2c719b7 1575 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1576 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1577 pipe_name(pipe));
291906f1
JB		 1578
1579 reg = PCH_LVDS;
1580 val = I915_READ(reg);
e2c719b7 1581 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1582 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1583 pipe_name(pipe));
291906f1 1584
e2debe91
PZ		 1585 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1586 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1587 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1588}
1589
40e9cf64
JB		 1590static void intel_init_dpio(struct drm_device *dev)
1591{
1592 struct drm_i915_private *dev_priv = dev->dev_private;
1593
1594 if (!IS_VALLEYVIEW(dev))
1595 return;
1596
a09caddd
CML		 1597 /*
1598 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1599 * CHV x1 PHY (DP/HDMI D)
1600 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1601 */
1602 if (IS_CHERRYVIEW(dev)) {
1603 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1604 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1605 } else {
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1607 }
5382f5f3
JB		 1608}
1609
d288f65f 1610static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1611 const struct intel_crtc_state *pipe_config)
87442f73 1612{
426115cf
DV		 1613 struct drm_device *dev = crtc->base.dev;
1614 struct drm_i915_private *dev_priv = dev->dev_private;
1615 int reg = DPLL(crtc->pipe);
d288f65f 1616 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1617
426115cf 1618 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1619
1620 /* No really, not for ILK+ */
1621 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1622
1623 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1624 if (IS_MOBILE(dev_priv->dev))
426115cf 1625 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1626
426115cf
DV		 1627 I915_WRITE(reg, dpll);
1628 POSTING_READ(reg);
1629 udelay(150);
1630
1631 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1632 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1633
d288f65f 1634 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1635 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1636
1637 /* We do this three times for luck */
426115cf 1638 I915_WRITE(reg, dpll);
87442f73
DV		 1639 POSTING_READ(reg);
1640 udelay(150); /* wait for warmup */
426115cf 1641 I915_WRITE(reg, dpll);
87442f73
DV		 1642 POSTING_READ(reg);
1643 udelay(150); /* wait for warmup */
426115cf 1644 I915_WRITE(reg, dpll);
87442f73
DV		 1645 POSTING_READ(reg);
1646 udelay(150); /* wait for warmup */
1647}
1648
d288f65f 1649static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1650 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1651{
1652 struct drm_device *dev = crtc->base.dev;
1653 struct drm_i915_private *dev_priv = dev->dev_private;
1654 int pipe = crtc->pipe;
1655 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1656 u32 tmp;
1657
1658 assert_pipe_disabled(dev_priv, crtc->pipe);
1659
1660 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1661
1662 mutex_lock(&dev_priv->dpio_lock);
1663
1664 /* Enable back the 10bit clock to display controller */
1665 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1666 tmp |= DPIO_DCLKP_EN;
1667 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1668
1669 /*
1670 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1671 */
1672 udelay(1);
1673
1674 /* Enable PLL */
d288f65f 1675 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1676
1677 /* Check PLL is locked */
a11b0703 1678 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1679 DRM_ERROR("PLL %d failed to lock\n", pipe);
1680
a11b0703 1681 /* not sure when this should be written */
d288f65f 1682 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703
VS		 1683 POSTING_READ(DPLL_MD(pipe));
1684
9d556c99
CML		 1685 mutex_unlock(&dev_priv->dpio_lock);
1686}
1687
1c4e0274
VS		 1688static int intel_num_dvo_pipes(struct drm_device *dev)
1689{
1690 struct intel_crtc *crtc;
1691 int count = 0;
1692
1693 for_each_intel_crtc(dev, crtc)
1694 count += crtc->active &&
409ee761 1695 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1696
1697 return count;
1698}
1699
66e3d5c0 1700static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1701{
66e3d5c0
DV		 1702 struct drm_device *dev = crtc->base.dev;
1703 struct drm_i915_private *dev_priv = dev->dev_private;
1704 int reg = DPLL(crtc->pipe);
6e3c9717 1705 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1706
66e3d5c0 1707 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1708
63d7bbe9 1709 /* No really, not for ILK+ */
3d13ef2e 1710 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1711
1712 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1713 if (IS_MOBILE(dev) && !IS_I830(dev))
1714 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1715
1c4e0274
VS		 1716 /* Enable DVO 2x clock on both PLLs if necessary */
1717 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1718 /*
1719 * It appears to be important that we don't enable this
1720 * for the current pipe before otherwise configuring the
1721 * PLL. No idea how this should be handled if multiple
1722 * DVO outputs are enabled simultaneosly.
1723 */
1724 dpll |= DPLL_DVO_2X_MODE;
1725 I915_WRITE(DPLL(!crtc->pipe),
1726 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1727 }
66e3d5c0
DV		 1728
1729 /* Wait for the clocks to stabilize. */
1730 POSTING_READ(reg);
1731 udelay(150);
1732
1733 if (INTEL_INFO(dev)->gen >= 4) {
1734 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1735 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1736 } else {
1737 /* The pixel multiplier can only be updated once the
1738 * DPLL is enabled and the clocks are stable.
1739 *
1740 * So write it again.
1741 */
1742 I915_WRITE(reg, dpll);
1743 }
63d7bbe9
JB		 1744
1745 /* We do this three times for luck */
66e3d5c0 1746 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1747 POSTING_READ(reg);
1748 udelay(150); /* wait for warmup */
66e3d5c0 1749 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1750 POSTING_READ(reg);
1751 udelay(150); /* wait for warmup */
66e3d5c0 1752 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1753 POSTING_READ(reg);
1754 udelay(150); /* wait for warmup */
1755}
1756
1757/**
50b44a44 1758 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1759 * @dev_priv: i915 private structure
1760 * @pipe: pipe PLL to disable
1761 *
1762 * Disable the PLL for @pipe, making sure the pipe is off first.
1763 *
1764 * Note! This is for pre-ILK only.
1765 */
1c4e0274 1766static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1767{
1c4e0274
VS		 1768 struct drm_device *dev = crtc->base.dev;
1769 struct drm_i915_private *dev_priv = dev->dev_private;
1770 enum pipe pipe = crtc->pipe;
1771
1772 /* Disable DVO 2x clock on both PLLs if necessary */
1773 if (IS_I830(dev) &&
409ee761 1774 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1775 intel_num_dvo_pipes(dev) == 1) {
1776 I915_WRITE(DPLL(PIPE_B),
1777 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1778 I915_WRITE(DPLL(PIPE_A),
1779 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1780 }
1781
b6b5d049
VS		 1782 /* Don't disable pipe or pipe PLLs if needed */
1783 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1784 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1785 return;
1786
1787 /* Make sure the pipe isn't still relying on us */
1788 assert_pipe_disabled(dev_priv, pipe);
1789
50b44a44
DV		 1790 I915_WRITE(DPLL(pipe), 0);
1791 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1792}
1793
f6071166
JB		 1794static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1795{
1796 u32 val = 0;
1797
1798 /* Make sure the pipe isn't still relying on us */
1799 assert_pipe_disabled(dev_priv, pipe);
1800
e5cbfbfb
ID		 1801 /*
1802 * Leave integrated clock source and reference clock enabled for pipe B.
1803 * The latter is needed for VGA hotplug / manual detection.
1804 */
f6071166 1805 if (pipe == PIPE_B)
e5cbfbfb 1806 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1807 I915_WRITE(DPLL(pipe), val);
1808 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1809
1810}
1811
1812static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1813{
d752048d 1814 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1815 u32 val;
1816
a11b0703
VS		 1817 /* Make sure the pipe isn't still relying on us */
1818 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1819
a11b0703 1820 /* Set PLL en = 0 */
d17ec4ce 1821 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1822 if (pipe != PIPE_A)
1823 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1824 I915_WRITE(DPLL(pipe), val);
1825 POSTING_READ(DPLL(pipe));
d752048d
VS		 1826
1827 mutex_lock(&dev_priv->dpio_lock);
1828
1829 /* Disable 10bit clock to display controller */
1830 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1831 val &= ~DPIO_DCLKP_EN;
1832 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1833
61407f6d
VS		 1834 /* disable left/right clock distribution */
1835 if (pipe != PIPE_B) {
1836 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1837 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1838 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1839 } else {
1840 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1841 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1842 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1843 }
1844
d752048d 1845 mutex_unlock(&dev_priv->dpio_lock);
f6071166
JB		 1846}
1847
e4607fcf
CML		 1848void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1849 struct intel_digital_port *dport)
89b667f8
JB		 1850{
1851 u32 port_mask;
00fc31b7 1852 int dpll_reg;
89b667f8 1853
e4607fcf
CML		 1854 switch (dport->port) {
1855 case PORT_B:
89b667f8 1856 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1857 dpll_reg = DPLL(0);
e4607fcf
CML		 1858 break;
1859 case PORT_C:
89b667f8 1860 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7
CML		 1861 dpll_reg = DPLL(0);
1862 break;
1863 case PORT_D:
1864 port_mask = DPLL_PORTD_READY_MASK;
1865 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1866 break;
1867 default:
1868 BUG();
1869 }
89b667f8 1870
00fc31b7 1871 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
89b667f8 1872 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
00fc31b7 1873 port_name(dport->port), I915_READ(dpll_reg));
89b667f8
JB		 1874}
1875
b14b1055
DV		 1876static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1877{
1878 struct drm_device *dev = crtc->base.dev;
1879 struct drm_i915_private *dev_priv = dev->dev_private;
1880 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1881
be19f0ff
CW		 1882 if (WARN_ON(pll == NULL))
1883 return;
1884
3e369b76 1885 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1886 if (pll->active == 0) {
1887 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1888 WARN_ON(pll->on);
1889 assert_shared_dpll_disabled(dev_priv, pll);
1890
1891 pll->mode_set(dev_priv, pll);
1892 }
1893}
1894
92f2584a 1895/**
85b3894f 1896 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1897 * @dev_priv: i915 private structure
1898 * @pipe: pipe PLL to enable
1899 *
1900 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1901 * drives the transcoder clock.
1902 */
85b3894f 1903static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1904{
3d13ef2e
DL		 1905 struct drm_device *dev = crtc->base.dev;
1906 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1907 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1908
87a875bb 1909 if (WARN_ON(pll == NULL))
48da64a8
CW		 1910 return;
1911
3e369b76 1912 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1913 return;
ee7b9f93 1914
74dd6928 1915 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1916 pll->name, pll->active, pll->on,
e2b78267 1917 crtc->base.base.id);
92f2584a 1918
cdbd2316
DV		 1919 if (pll->active++) {
1920 WARN_ON(!pll->on);
e9d6944e 1921 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1922 return;
1923 }
f4a091c7 1924 WARN_ON(pll->on);
ee7b9f93 1925
bd2bb1b9
PZ		 1926 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1927
46edb027 1928 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1929 pll->enable(dev_priv, pll);
ee7b9f93 1930 pll->on = true;
92f2584a
JB		 1931}
1932
f6daaec2 1933static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1934{
3d13ef2e
DL		 1935 struct drm_device *dev = crtc->base.dev;
1936 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1937 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1938
92f2584a 1939 /* PCH only available on ILK+ */
3d13ef2e 1940 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1941 if (WARN_ON(pll == NULL))
ee7b9f93 1942 return;
92f2584a 1943
3e369b76 1944 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1945 return;
7a419866 1946
46edb027
DV		 1947 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1948 pll->name, pll->active, pll->on,
e2b78267 1949 crtc->base.base.id);
7a419866 1950
48da64a8 1951 if (WARN_ON(pll->active == 0)) {
e9d6944e 1952 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1953 return;
1954 }
1955
e9d6944e 1956 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1957 WARN_ON(!pll->on);
cdbd2316 1958 if (--pll->active)
7a419866 1959 return;
ee7b9f93 1960
46edb027 1961 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1962 pll->disable(dev_priv, pll);
ee7b9f93 1963 pll->on = false;
bd2bb1b9
PZ		 1964
1965 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1966}
1967
b8a4f404
PZ		 1968static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1969 enum pipe pipe)
040484af 1970{
23670b32 1971 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1972 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1974 uint32_t reg, val, pipeconf_val;
040484af
JB		 1975
1976 /* PCH only available on ILK+ */
55522f37 1977 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1978
1979 /* Make sure PCH DPLL is enabled */
e72f9fbf 1980 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1981 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1982
1983 /* FDI must be feeding us bits for PCH ports */
1984 assert_fdi_tx_enabled(dev_priv, pipe);
1985 assert_fdi_rx_enabled(dev_priv, pipe);
1986
23670b32
DV		 1987 if (HAS_PCH_CPT(dev)) {
1988 /* Workaround: Set the timing override bit before enabling the
1989 * pch transcoder. */
1990 reg = TRANS_CHICKEN2(pipe);
1991 val = I915_READ(reg);
1992 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1993 I915_WRITE(reg, val);
59c859d6 1994 }
23670b32 1995
ab9412ba 1996 reg = PCH_TRANSCONF(pipe);
040484af 1997 val = I915_READ(reg);
5f7f726d 1998 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1999
2000 if (HAS_PCH_IBX(dev_priv->dev)) {
2001 /*
2002 * make the BPC in transcoder be consistent with
2003 * that in pipeconf reg.
2004 */
dfd07d72
DV		 2005 val &= ~PIPECONF_BPC_MASK;
2006 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2007 }
5f7f726d
PZ		 2008
2009 val &= ~TRANS_INTERLACE_MASK;
2010 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2011 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2012 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2013 val |= TRANS_LEGACY_INTERLACED_ILK;
2014 else
2015 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2016 else
2017 val |= TRANS_PROGRESSIVE;
2018
040484af
JB		 2019 I915_WRITE(reg, val | TRANS_ENABLE);
2020 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2021 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2022}
2023
8fb033d7 2024static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2025 enum transcoder cpu_transcoder)
040484af 2026{
8fb033d7 2027 u32 val, pipeconf_val;
8fb033d7
PZ		 2028
2029 /* PCH only available on ILK+ */
55522f37 2030 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2031
8fb033d7 2032 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2033 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2034 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2035
223a6fdf
PZ		 2036 /* Workaround: set timing override bit. */
2037 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2038 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2039 I915_WRITE(_TRANSA_CHICKEN2, val);
2040
25f3ef11 2041 val = TRANS_ENABLE;
937bb610 2042 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2043
9a76b1c6
PZ		 2044 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2045 PIPECONF_INTERLACED_ILK)
a35f2679 2046 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2047 else
2048 val |= TRANS_PROGRESSIVE;
2049
ab9412ba
DV		 2050 I915_WRITE(LPT_TRANSCONF, val);
2051 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2052 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2053}
2054
b8a4f404
PZ		 2055static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2056 enum pipe pipe)
040484af 2057{
23670b32
DV		 2058 struct drm_device *dev = dev_priv->dev;
2059 uint32_t reg, val;
040484af
JB		 2060
2061 /* FDI relies on the transcoder */
2062 assert_fdi_tx_disabled(dev_priv, pipe);
2063 assert_fdi_rx_disabled(dev_priv, pipe);
2064
291906f1
JB		 2065 /* Ports must be off as well */
2066 assert_pch_ports_disabled(dev_priv, pipe);
2067
ab9412ba 2068 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2069 val = I915_READ(reg);
2070 val &= ~TRANS_ENABLE;
2071 I915_WRITE(reg, val);
2072 /* wait for PCH transcoder off, transcoder state */
2073 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2074 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2075
2076 if (!HAS_PCH_IBX(dev)) {
2077 /* Workaround: Clear the timing override chicken bit again. */
2078 reg = TRANS_CHICKEN2(pipe);
2079 val = I915_READ(reg);
2080 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2081 I915_WRITE(reg, val);
2082 }
040484af
JB		 2083}
2084
ab4d966c 2085static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2086{
8fb033d7
PZ		 2087 u32 val;
2088
ab9412ba 2089 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2090 val &= ~TRANS_ENABLE;
ab9412ba 2091 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2092 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2093 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2094 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2095
2096 /* Workaround: clear timing override bit. */
2097 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2098 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2099 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2100}
2101
b24e7179 2102/**
309cfea8 2103 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2104 * @crtc: crtc responsible for the pipe
b24e7179 2105 *
0372264a 2106 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2107 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2108 */
e1fdc473 2109static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2110{
0372264a
PZ		 2111 struct drm_device *dev = crtc->base.dev;
2112 struct drm_i915_private *dev_priv = dev->dev_private;
2113 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2114 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2115 pipe);
1a240d4d 2116 enum pipe pch_transcoder;
b24e7179
JB		 2117 int reg;
2118 u32 val;
2119
58c6eaa2 2120 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2121 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2122 assert_sprites_disabled(dev_priv, pipe);
2123
681e5811 2124 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2125 pch_transcoder = TRANSCODER_A;
2126 else
2127 pch_transcoder = pipe;
2128
b24e7179
JB		 2129 /*
2130 * A pipe without a PLL won't actually be able to drive bits from
2131 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2132 * need the check.
2133 */
50360403 2134 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2135 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2136 assert_dsi_pll_enabled(dev_priv);
2137 else
2138 assert_pll_enabled(dev_priv, pipe);
040484af 2139 else {
6e3c9717 2140 if (crtc->config->has_pch_encoder) {
040484af 2141 /* if driving the PCH, we need FDI enabled */
cc391bbb 2142 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2143 assert_fdi_tx_pll_enabled(dev_priv,
2144 (enum pipe) cpu_transcoder);
040484af
JB		 2145 }
2146 /* FIXME: assert CPU port conditions for SNB+ */
2147 }
b24e7179 2148
702e7a56 2149 reg = PIPECONF(cpu_transcoder);
b24e7179 2150 val = I915_READ(reg);
7ad25d48 2151 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2152 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2153 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2154 return;
7ad25d48 2155 }
00d70b15
CW		 2156
2157 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2158 POSTING_READ(reg);
b24e7179
JB		 2159}
2160
2161/**
309cfea8 2162 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2163 * @crtc: crtc whose pipes is to be disabled
b24e7179 2164 *
575f7ab7
VS		 2165 * Disable the pipe of @crtc, making sure that various hardware
2166 * specific requirements are met, if applicable, e.g. plane
2167 * disabled, panel fitter off, etc.
b24e7179
JB		 2168 *
2169 * Will wait until the pipe has shut down before returning.
2170 */
575f7ab7 2171static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2172{
575f7ab7 2173 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2174 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2175 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2176 int reg;
2177 u32 val;
2178
2179 /*
2180 * Make sure planes won't keep trying to pump pixels to us,
2181 * or we might hang the display.
2182 */
2183 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2184 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2185 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2186
702e7a56 2187 reg = PIPECONF(cpu_transcoder);
b24e7179 2188 val = I915_READ(reg);
00d70b15
CW		 2189 if ((val & PIPECONF_ENABLE) == 0)
2190 return;
2191
67adc644
VS		 2192 /*
2193 * Double wide has implications for planes
2194 * so best keep it disabled when not needed.
2195 */
6e3c9717 2196 if (crtc->config->double_wide)
67adc644
VS		 2197 val &= ~PIPECONF_DOUBLE_WIDE;
2198
2199 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2200 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2201 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2202 val &= ~PIPECONF_ENABLE;
2203
2204 I915_WRITE(reg, val);
2205 if ((val & PIPECONF_ENABLE) == 0)
2206 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2207}
2208
d74362c9
KP		 2209/*
2210 * Plane regs are double buffered, going from enabled->disabled needs a
2211 * trigger in order to latch. The display address reg provides this.
2212 */
1dba99f4
VS		 2213void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2214 enum plane plane)
d74362c9 2215{
3d13ef2e
DL		 2216 struct drm_device *dev = dev_priv->dev;
2217 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1dba99f4
VS		 2218
2219 I915_WRITE(reg, I915_READ(reg));
2220 POSTING_READ(reg);
d74362c9
KP		 2221}
2222
b24e7179 2223/**
262ca2b0 2224 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2225 * @plane: plane to be enabled
2226 * @crtc: crtc for the plane
b24e7179 2227 *
fdd508a6 2228 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2229 */
fdd508a6
VS		 2230static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2231 struct drm_crtc *crtc)
b24e7179 2232{
fdd508a6
VS		 2233 struct drm_device *dev = plane->dev;
2234 struct drm_i915_private *dev_priv = dev->dev_private;
2235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2236
2237 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2238 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b24e7179 2239
98ec7739
VS		 2240 if (intel_crtc->primary_enabled)
2241 return;
0037f71c 2242
4c445e0e 2243 intel_crtc->primary_enabled = true;
939c2fe8 2244
fdd508a6
VS		 2245 dev_priv->display.update_primary_plane(crtc, plane->fb,
2246 crtc->x, crtc->y);
33c3b0d1
VS		 2247
2248 /*
2249 * BDW signals flip done immediately if the plane
2250 * is disabled, even if the plane enable is already
2251 * armed to occur at the next vblank :(
2252 */
2253 if (IS_BROADWELL(dev))
2254 intel_wait_for_vblank(dev, intel_crtc->pipe);
b24e7179
JB		 2255}
2256
693db184
CW		 2257static bool need_vtd_wa(struct drm_device *dev)
2258{
2259#ifdef CONFIG_INTEL_IOMMU
2260 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2261 return true;
2262#endif
2263 return false;
2264}
2265
50470bb0 2266unsigned int
6761dd31
TU		 2267intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2268 uint64_t fb_format_modifier)
a57ce0b2 2269{
6761dd31
TU		 2270 unsigned int tile_height;
2271 uint32_t pixel_bytes;
a57ce0b2 2272
b5d0e9bf
DL		 2273 switch (fb_format_modifier) {
2274 case DRM_FORMAT_MOD_NONE:
2275 tile_height = 1;
2276 break;
2277 case I915_FORMAT_MOD_X_TILED:
2278 tile_height = IS_GEN2(dev) ? 16 : 8;
2279 break;
2280 case I915_FORMAT_MOD_Y_TILED:
2281 tile_height = 32;
2282 break;
2283 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2284 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2285 switch (pixel_bytes) {
b5d0e9bf 2286 default:
6761dd31 2287 case 1:
b5d0e9bf
DL		 2288 tile_height = 64;
2289 break;
6761dd31
TU		 2290 case 2:
2291 case 4:
b5d0e9bf
DL		 2292 tile_height = 32;
2293 break;
6761dd31 2294 case 8:
b5d0e9bf
DL		 2295 tile_height = 16;
2296 break;
6761dd31 2297 case 16:
b5d0e9bf
DL		 2298 WARN_ONCE(1,
2299 "128-bit pixels are not supported for display!");
2300 tile_height = 16;
2301 break;
2302 }
2303 break;
2304 default:
2305 MISSING_CASE(fb_format_modifier);
2306 tile_height = 1;
2307 break;
2308 }
091df6cb 2309
6761dd31
TU		 2310 return tile_height;
2311}
2312
2313unsigned int
2314intel_fb_align_height(struct drm_device *dev, unsigned int height,
2315 uint32_t pixel_format, uint64_t fb_format_modifier)
2316{
2317 return ALIGN(height, intel_tile_height(dev, pixel_format,
2318 fb_format_modifier));
a57ce0b2
JB		 2319}
2320
f64b98cd
TU		 2321static int
2322intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2323 const struct drm_plane_state *plane_state)
2324{
50470bb0 2325 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2326
f64b98cd
TU		 2327 *view = i915_ggtt_view_normal;
2328
50470bb0
TU		 2329 if (!plane_state)
2330 return 0;
2331
121920fa 2332 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2333 return 0;
2334
9abc4648 2335 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2336
2337 info->height = fb->height;
2338 info->pixel_format = fb->pixel_format;
2339 info->pitch = fb->pitches[0];
2340 info->fb_modifier = fb->modifier[0];
2341
f64b98cd
TU		 2342 return 0;
2343}
2344
127bd2ac 2345int
850c4cdc
TU		 2346intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2347 struct drm_framebuffer *fb,
82bc3b2d 2348 const struct drm_plane_state *plane_state,
a4872ba6 2349 struct intel_engine_cs *pipelined)
6b95a207 2350{
850c4cdc 2351 struct drm_device *dev = fb->dev;
ce453d81 2352 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2353 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2354 struct i915_ggtt_view view;
6b95a207
KH		 2355 u32 alignment;
2356 int ret;
2357
ebcdd39e
MR		 2358 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2359
7b911adc
TU		 2360 switch (fb->modifier[0]) {
2361 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2362 if (INTEL_INFO(dev)->gen >= 9)
2363 alignment = 256 * 1024;
2364 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2365 alignment = 128 * 1024;
a6c45cf0 2366 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2367 alignment = 4 * 1024;
2368 else
2369 alignment = 64 * 1024;
6b95a207 2370 break;
7b911adc 2371 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2372 if (INTEL_INFO(dev)->gen >= 9)
2373 alignment = 256 * 1024;
2374 else {
2375 /* pin() will align the object as required by fence */
2376 alignment = 0;
2377 }
6b95a207 2378 break;
7b911adc 2379 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2380 case I915_FORMAT_MOD_Yf_TILED:
2381 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2382 "Y tiling bo slipped through, driver bug!\n"))
2383 return -EINVAL;
2384 alignment = 1 * 1024 * 1024;
2385 break;
6b95a207 2386 default:
7b911adc
TU		 2387 MISSING_CASE(fb->modifier[0]);
2388 return -EINVAL;
6b95a207
KH		 2389 }
2390
f64b98cd
TU		 2391 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2392 if (ret)
2393 return ret;
2394
693db184
CW		 2395 /* Note that the w/a also requires 64 PTE of padding following the
2396 * bo. We currently fill all unused PTE with the shadow page and so
2397 * we should always have valid PTE following the scanout preventing
2398 * the VT-d warning.
2399 */
2400 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2401 alignment = 256 * 1024;
2402
d6dd6843
PZ		 2403 /*
2404 * Global gtt pte registers are special registers which actually forward
2405 * writes to a chunk of system memory. Which means that there is no risk
2406 * that the register values disappear as soon as we call
2407 * intel_runtime_pm_put(), so it is correct to wrap only the
2408 * pin/unpin/fence and not more.
2409 */
2410 intel_runtime_pm_get(dev_priv);
2411
ce453d81 2412 dev_priv->mm.interruptible = false;
e6617330 2413 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2414 &view);
48b956c5 2415 if (ret)
ce453d81 2416 goto err_interruptible;
6b95a207
KH		 2417
2418 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2419 * fence, whereas 965+ only requires a fence if using
2420 * framebuffer compression. For simplicity, we always install
2421 * a fence as the cost is not that onerous.
2422 */
06d98131 2423 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2424 if (ret)
2425 goto err_unpin;
1690e1eb 2426
9a5a53b3 2427 i915_gem_object_pin_fence(obj);
6b95a207 2428
ce453d81 2429 dev_priv->mm.interruptible = true;
d6dd6843 2430 intel_runtime_pm_put(dev_priv);
6b95a207 2431 return 0;
48b956c5
CW		 2432
2433err_unpin:
f64b98cd 2434 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2435err_interruptible:
2436 dev_priv->mm.interruptible = true;
d6dd6843 2437 intel_runtime_pm_put(dev_priv);
48b956c5 2438 return ret;
6b95a207
KH		 2439}
2440
82bc3b2d
TU		 2441static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2442 const struct drm_plane_state *plane_state)
1690e1eb 2443{
82bc3b2d 2444 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2445 struct i915_ggtt_view view;
2446 int ret;
82bc3b2d 2447
ebcdd39e
MR		 2448 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2449
f64b98cd
TU		 2450 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2451 WARN_ONCE(ret, "Couldn't get view from plane state!");
2452
1690e1eb 2453 i915_gem_object_unpin_fence(obj);
f64b98cd 2454 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2455}
2456
c2c75131
DV		 2457/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2458 * is assumed to be a power-of-two. */
bc752862
CW		 2459unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2460 unsigned int tiling_mode,
2461 unsigned int cpp,
2462 unsigned int pitch)
c2c75131 2463{
bc752862
CW		 2464 if (tiling_mode != I915_TILING_NONE) {
2465 unsigned int tile_rows, tiles;
c2c75131 2466
bc752862
CW		 2467 tile_rows = *y / 8;
2468 *y %= 8;
c2c75131 2469
bc752862
CW		 2470 tiles = *x / (512/cpp);
2471 *x %= 512/cpp;
2472
2473 return tile_rows * pitch * 8 + tiles * 4096;
2474 } else {
2475 unsigned int offset;
2476
2477 offset = *y * pitch + *x * cpp;
2478 *y = 0;
2479 *x = (offset & 4095) / cpp;
2480 return offset & -4096;
2481 }
c2c75131
DV		 2482}
2483
b35d63fa 2484static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2485{
2486 switch (format) {
2487 case DISPPLANE_8BPP:
2488 return DRM_FORMAT_C8;
2489 case DISPPLANE_BGRX555:
2490 return DRM_FORMAT_XRGB1555;
2491 case DISPPLANE_BGRX565:
2492 return DRM_FORMAT_RGB565;
2493 default:
2494 case DISPPLANE_BGRX888:
2495 return DRM_FORMAT_XRGB8888;
2496 case DISPPLANE_RGBX888:
2497 return DRM_FORMAT_XBGR8888;
2498 case DISPPLANE_BGRX101010:
2499 return DRM_FORMAT_XRGB2101010;
2500 case DISPPLANE_RGBX101010:
2501 return DRM_FORMAT_XBGR2101010;
2502 }
2503}
2504
bc8d7dff
DL		 2505static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2506{
2507 switch (format) {
2508 case PLANE_CTL_FORMAT_RGB_565:
2509 return DRM_FORMAT_RGB565;
2510 default:
2511 case PLANE_CTL_FORMAT_XRGB_8888:
2512 if (rgb_order) {
2513 if (alpha)
2514 return DRM_FORMAT_ABGR8888;
2515 else
2516 return DRM_FORMAT_XBGR8888;
2517 } else {
2518 if (alpha)
2519 return DRM_FORMAT_ARGB8888;
2520 else
2521 return DRM_FORMAT_XRGB8888;
2522 }
2523 case PLANE_CTL_FORMAT_XRGB_2101010:
2524 if (rgb_order)
2525 return DRM_FORMAT_XBGR2101010;
2526 else
2527 return DRM_FORMAT_XRGB2101010;
2528 }
2529}
2530
5724dbd1 2531static bool
f6936e29
DV		 2532intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2533 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2534{
2535 struct drm_device *dev = crtc->base.dev;
2536 struct drm_i915_gem_object *obj = NULL;
2537 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2538 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2539 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2540 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2541 PAGE_SIZE);
2542
2543 size_aligned -= base_aligned;
46f297fb 2544
ff2652ea
CW		 2545 if (plane_config->size == 0)
2546 return false;
2547
f37b5c2b
DV		 2548 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2549 base_aligned,
2550 base_aligned,
2551 size_aligned);
46f297fb 2552 if (!obj)
484b41dd 2553 return false;
46f297fb 2554
49af449b
DL		 2555 obj->tiling_mode = plane_config->tiling;
2556 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2557 obj->stride = fb->pitches[0];
46f297fb 2558
6bf129df
DL		 2559 mode_cmd.pixel_format = fb->pixel_format;
2560 mode_cmd.width = fb->width;
2561 mode_cmd.height = fb->height;
2562 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2563 mode_cmd.modifier[0] = fb->modifier[0];
2564 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2565
2566 mutex_lock(&dev->struct_mutex);
6bf129df 2567 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2568 &mode_cmd, obj)) {
46f297fb
JB		 2569 DRM_DEBUG_KMS("intel fb init failed\n");
2570 goto out_unref_obj;
2571 }
46f297fb 2572 mutex_unlock(&dev->struct_mutex);
484b41dd 2573
f6936e29 2574 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2575 return true;
46f297fb
JB		 2576
2577out_unref_obj:
2578 drm_gem_object_unreference(&obj->base);
2579 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2580 return false;
2581}
2582
afd65eb4
MR		 2583/* Update plane->state->fb to match plane->fb after driver-internal updates */
2584static void
2585update_state_fb(struct drm_plane *plane)
2586{
2587 if (plane->fb == plane->state->fb)
2588 return;
2589
2590 if (plane->state->fb)
2591 drm_framebuffer_unreference(plane->state->fb);
2592 plane->state->fb = plane->fb;
2593 if (plane->state->fb)
2594 drm_framebuffer_reference(plane->state->fb);
2595}
2596
5724dbd1 2597static void
f6936e29
DV		 2598intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2599 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2600{
2601 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2602 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2603 struct drm_crtc *c;
2604 struct intel_crtc *i;
2ff8fde1 2605 struct drm_i915_gem_object *obj;
88595ac9
DV		 2606 struct drm_plane *primary = intel_crtc->base.primary;
2607 struct drm_framebuffer *fb;
484b41dd 2608
2d14030b 2609 if (!plane_config->fb)
484b41dd
JB		 2610 return;
2611
f6936e29 2612 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2613 fb = &plane_config->fb->base;
2614 goto valid_fb;
f55548b5 2615 }
484b41dd 2616
2d14030b 2617 kfree(plane_config->fb);
484b41dd
JB		 2618
2619 /*
2620 * Failed to alloc the obj, check to see if we should share
2621 * an fb with another CRTC instead
2622 */
70e1e0ec 2623 for_each_crtc(dev, c) {
484b41dd
JB		 2624 i = to_intel_crtc(c);
2625
2626 if (c == &intel_crtc->base)
2627 continue;
2628
2ff8fde1
MR		 2629 if (!i->active)
2630 continue;
2631
88595ac9
DV		 2632 fb = c->primary->fb;
2633 if (!fb)
484b41dd
JB		 2634 continue;
2635
88595ac9 2636 obj = intel_fb_obj(fb);
2ff8fde1 2637 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2638 drm_framebuffer_reference(fb);
2639 goto valid_fb;
484b41dd
JB		 2640 }
2641 }
88595ac9
DV		 2642
2643 return;
2644
2645valid_fb:
2646 obj = intel_fb_obj(fb);
2647 if (obj->tiling_mode != I915_TILING_NONE)
2648 dev_priv->preserve_bios_swizzle = true;
2649
2650 primary->fb = fb;
2651 primary->state->crtc = &intel_crtc->base;
2652 primary->crtc = &intel_crtc->base;
2653 update_state_fb(primary);
2654 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2655}
2656
29b9bde6
DV		 2657static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2658 struct drm_framebuffer *fb,
2659 int x, int y)
81255565
JB		 2660{
2661 struct drm_device *dev = crtc->dev;
2662 struct drm_i915_private *dev_priv = dev->dev_private;
2663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c9ba6fad 2664 struct drm_i915_gem_object *obj;
81255565 2665 int plane = intel_crtc->plane;
e506a0c6 2666 unsigned long linear_offset;
81255565 2667 u32 dspcntr;
f45651ba 2668 u32 reg = DSPCNTR(plane);
48404c1e 2669 int pixel_size;
f45651ba 2670
a8ad0d8e 2671 if (!intel_crtc->primary_enabled || !fb) {
fdd508a6
VS		 2672 I915_WRITE(reg, 0);
2673 if (INTEL_INFO(dev)->gen >= 4)
2674 I915_WRITE(DSPSURF(plane), 0);
2675 else
2676 I915_WRITE(DSPADDR(plane), 0);
2677 POSTING_READ(reg);
2678 return;
2679 }
2680
c9ba6fad
VS		 2681 obj = intel_fb_obj(fb);
2682 if (WARN_ON(obj == NULL))
2683 return;
2684
2685 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2686
f45651ba
VS		 2687 dspcntr = DISPPLANE_GAMMA_ENABLE;
2688
fdd508a6 2689 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2690
2691 if (INTEL_INFO(dev)->gen < 4) {
2692 if (intel_crtc->pipe == PIPE_B)
2693 dspcntr |= DISPPLANE_SEL_PIPE_B;
2694
2695 /* pipesrc and dspsize control the size that is scaled from,
2696 * which should always be the user's requested size.
2697 */
2698 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2699 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2700 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2701 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2702 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2703 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2704 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2705 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2706 I915_WRITE(PRIMPOS(plane), 0);
2707 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2708 }
81255565 2709
57779d06
VS		 2710 switch (fb->pixel_format) {
2711 case DRM_FORMAT_C8:
81255565
JB		 2712 dspcntr |= DISPPLANE_8BPP;
2713 break;
57779d06
VS		 2714 case DRM_FORMAT_XRGB1555:
2715 case DRM_FORMAT_ARGB1555:
2716 dspcntr |= DISPPLANE_BGRX555;
81255565 2717 break;
57779d06
VS		 2718 case DRM_FORMAT_RGB565:
2719 dspcntr |= DISPPLANE_BGRX565;
2720 break;
2721 case DRM_FORMAT_XRGB8888:
2722 case DRM_FORMAT_ARGB8888:
2723 dspcntr |= DISPPLANE_BGRX888;
2724 break;
2725 case DRM_FORMAT_XBGR8888:
2726 case DRM_FORMAT_ABGR8888:
2727 dspcntr |= DISPPLANE_RGBX888;
2728 break;
2729 case DRM_FORMAT_XRGB2101010:
2730 case DRM_FORMAT_ARGB2101010:
2731 dspcntr |= DISPPLANE_BGRX101010;
2732 break;
2733 case DRM_FORMAT_XBGR2101010:
2734 case DRM_FORMAT_ABGR2101010:
2735 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2736 break;
2737 default:
baba133a 2738 BUG();
81255565 2739 }
57779d06 2740
f45651ba
VS		 2741 if (INTEL_INFO(dev)->gen >= 4 &&
2742 obj->tiling_mode != I915_TILING_NONE)
2743 dspcntr |= DISPPLANE_TILED;
81255565 2744
de1aa629
VS		 2745 if (IS_G4X(dev))
2746 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2747
b9897127 2748 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2749
c2c75131
DV		 2750 if (INTEL_INFO(dev)->gen >= 4) {
2751 intel_crtc->dspaddr_offset =
bc752862 2752 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2753 pixel_size,
bc752862 2754 fb->pitches[0]);
c2c75131
DV		 2755 linear_offset -= intel_crtc->dspaddr_offset;
2756 } else {
e506a0c6 2757 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2758 }
e506a0c6 2759
8e7d688b 2760 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2761 dspcntr |= DISPPLANE_ROTATE_180;
2762
6e3c9717
ACO		 2763 x += (intel_crtc->config->pipe_src_w - 1);
2764 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2765
2766 /* Finding the last pixel of the last line of the display
2767 data and adding to linear_offset*/
2768 linear_offset +=
6e3c9717
ACO		 2769 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2770 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2771 }
2772
2773 I915_WRITE(reg, dspcntr);
2774
01f2c773 2775 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2776 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2777 I915_WRITE(DSPSURF(plane),
2778 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2779 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2780 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2781 } else
f343c5f6 2782 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2783 POSTING_READ(reg);
17638cd6
JB		 2784}
2785
29b9bde6
DV		 2786static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2787 struct drm_framebuffer *fb,
2788 int x, int y)
17638cd6
JB		 2789{
2790 struct drm_device *dev = crtc->dev;
2791 struct drm_i915_private *dev_priv = dev->dev_private;
2792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c9ba6fad 2793 struct drm_i915_gem_object *obj;
17638cd6 2794 int plane = intel_crtc->plane;
e506a0c6 2795 unsigned long linear_offset;
17638cd6 2796 u32 dspcntr;
f45651ba 2797 u32 reg = DSPCNTR(plane);
48404c1e 2798 int pixel_size;
f45651ba 2799
a8ad0d8e 2800 if (!intel_crtc->primary_enabled || !fb) {
fdd508a6
VS		 2801 I915_WRITE(reg, 0);
2802 I915_WRITE(DSPSURF(plane), 0);
2803 POSTING_READ(reg);
2804 return;
2805 }
2806
c9ba6fad
VS		 2807 obj = intel_fb_obj(fb);
2808 if (WARN_ON(obj == NULL))
2809 return;
2810
2811 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2812
f45651ba
VS		 2813 dspcntr = DISPPLANE_GAMMA_ENABLE;
2814
fdd508a6 2815 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2816
2817 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2818 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2819
57779d06
VS		 2820 switch (fb->pixel_format) {
2821 case DRM_FORMAT_C8:
17638cd6
JB		 2822 dspcntr |= DISPPLANE_8BPP;
2823 break;
57779d06
VS		 2824 case DRM_FORMAT_RGB565:
2825 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2826 break;
57779d06
VS		 2827 case DRM_FORMAT_XRGB8888:
2828 case DRM_FORMAT_ARGB8888:
2829 dspcntr |= DISPPLANE_BGRX888;
2830 break;
2831 case DRM_FORMAT_XBGR8888:
2832 case DRM_FORMAT_ABGR8888:
2833 dspcntr |= DISPPLANE_RGBX888;
2834 break;
2835 case DRM_FORMAT_XRGB2101010:
2836 case DRM_FORMAT_ARGB2101010:
2837 dspcntr |= DISPPLANE_BGRX101010;
2838 break;
2839 case DRM_FORMAT_XBGR2101010:
2840 case DRM_FORMAT_ABGR2101010:
2841 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2842 break;
2843 default:
baba133a 2844 BUG();
17638cd6
JB		 2845 }
2846
2847 if (obj->tiling_mode != I915_TILING_NONE)
2848 dspcntr |= DISPPLANE_TILED;
17638cd6 2849
f45651ba 2850 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2851 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2852
b9897127 2853 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2854 intel_crtc->dspaddr_offset =
bc752862 2855 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2856 pixel_size,
bc752862 2857 fb->pitches[0]);
c2c75131 2858 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2859 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2860 dspcntr |= DISPPLANE_ROTATE_180;
2861
2862 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2863 x += (intel_crtc->config->pipe_src_w - 1);
2864 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2865
2866 /* Finding the last pixel of the last line of the display
2867 data and adding to linear_offset*/
2868 linear_offset +=
6e3c9717
ACO		 2869 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2870 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2871 }
2872 }
2873
2874 I915_WRITE(reg, dspcntr);
17638cd6 2875
01f2c773 2876 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2877 I915_WRITE(DSPSURF(plane),
2878 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2879 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2880 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2881 } else {
2882 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2883 I915_WRITE(DSPLINOFF(plane), linear_offset);
2884 }
17638cd6 2885 POSTING_READ(reg);
17638cd6
JB		 2886}
2887
b321803d
DL		 2888u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2889 uint32_t pixel_format)
2890{
2891 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2892
2893 /*
2894 * The stride is either expressed as a multiple of 64 bytes
2895 * chunks for linear buffers or in number of tiles for tiled
2896 * buffers.
2897 */
2898 switch (fb_modifier) {
2899 case DRM_FORMAT_MOD_NONE:
2900 return 64;
2901 case I915_FORMAT_MOD_X_TILED:
2902 if (INTEL_INFO(dev)->gen == 2)
2903 return 128;
2904 return 512;
2905 case I915_FORMAT_MOD_Y_TILED:
2906 /* No need to check for old gens and Y tiling since this is
2907 * about the display engine and those will be blocked before
2908 * we get here.
2909 */
2910 return 128;
2911 case I915_FORMAT_MOD_Yf_TILED:
2912 if (bits_per_pixel == 8)
2913 return 64;
2914 else
2915 return 128;
2916 default:
2917 MISSING_CASE(fb_modifier);
2918 return 64;
2919 }
2920}
2921
121920fa
TU		 2922unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2923 struct drm_i915_gem_object *obj)
2924{
9abc4648 2925 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2926
2927 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2928 view = &i915_ggtt_view_rotated;
121920fa
TU		 2929
2930 return i915_gem_obj_ggtt_offset_view(obj, view);
2931}
2932
a1b2278e
CK		 2933/*
2934 * This function detaches (aka. unbinds) unused scalers in hardware
2935 */
2936void skl_detach_scalers(struct intel_crtc *intel_crtc)
2937{
2938 struct drm_device *dev;
2939 struct drm_i915_private *dev_priv;
2940 struct intel_crtc_scaler_state *scaler_state;
2941 int i;
2942
2943 if (!intel_crtc || !intel_crtc->config)
2944 return;
2945
2946 dev = intel_crtc->base.dev;
2947 dev_priv = dev->dev_private;
2948 scaler_state = &intel_crtc->config->scaler_state;
2949
2950 /* loop through and disable scalers that aren't in use */
2951 for (i = 0; i < intel_crtc->num_scalers; i++) {
2952 if (!scaler_state->scalers[i].in_use) {
2953 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2954 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2955 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2956 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2957 intel_crtc->base.base.id, intel_crtc->pipe, i);
2958 }
2959 }
2960}
2961
6156a456 2962u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2963{
6156a456
CK		 2964 u32 plane_ctl_format = 0;
2965 switch (pixel_format) {
70d21f0e 2966 case DRM_FORMAT_RGB565:
6156a456 2967 plane_ctl_format = PLANE_CTL_FORMAT_RGB_565;
f75fb42a 2968 break;
70d21f0e 2969 case DRM_FORMAT_XBGR8888:
6156a456
CK		 2970 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
2971 break;
2972 case DRM_FORMAT_XRGB8888:
2973 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888;
70d21f0e 2974 break;
6156a456
CK		 2975 /*
2976 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2977 * to be already pre-multiplied. We need to add a knob (or a different
2978 * DRM_FORMAT) for user-space to configure that.
2979 */
f75fb42a 2980 case DRM_FORMAT_ABGR8888:
6156a456
CK		 2981 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
2982 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2983 break;
2984 case DRM_FORMAT_ARGB8888:
2985 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_8888 |
2986 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
f75fb42a 2987 break;
70d21f0e 2988 case DRM_FORMAT_XRGB2101010:
6156a456 2989 plane_ctl_format = PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e
DL		 2990 break;
2991 case DRM_FORMAT_XBGR2101010:
6156a456
CK		 2992 plane_ctl_format = PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
2993 break;
2994 case DRM_FORMAT_YUYV:
2995 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
2996 break;
2997 case DRM_FORMAT_YVYU:
2998 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
2999 break;
3000 case DRM_FORMAT_UYVY:
3001 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
3002 break;
3003 case DRM_FORMAT_VYUY:
3004 plane_ctl_format = PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e
DL		 3005 break;
3006 default:
3007 BUG();
3008 }
6156a456
CK		 3009 return plane_ctl_format;
3010}
70d21f0e 3011
6156a456
CK		 3012u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
3013{
3014 u32 plane_ctl_tiling = 0;
3015 switch (fb_modifier) {
30af77c4 3016 case DRM_FORMAT_MOD_NONE:
70d21f0e 3017 break;
30af77c4 3018 case I915_FORMAT_MOD_X_TILED:
6156a456 3019 plane_ctl_tiling = PLANE_CTL_TILED_X;
b321803d
DL		 3020 break;
3021 case I915_FORMAT_MOD_Y_TILED:
6156a456 3022 plane_ctl_tiling = PLANE_CTL_TILED_Y;
b321803d
DL		 3023 break;
3024 case I915_FORMAT_MOD_Yf_TILED:
6156a456 3025 plane_ctl_tiling = PLANE_CTL_TILED_YF;
70d21f0e
DL		 3026 break;
3027 default:
6156a456 3028 MISSING_CASE(fb_modifier);
70d21f0e 3029 }
6156a456
CK		 3030 return plane_ctl_tiling;
3031}
70d21f0e 3032
6156a456
CK		 3033u32 skl_plane_ctl_rotation(unsigned int rotation)
3034{
3035 u32 plane_ctl_rotation = 0;
3b7a5119 3036 switch (rotation) {
6156a456
CK		 3037 case BIT(DRM_ROTATE_0):
3038 break;
3b7a5119 3039 case BIT(DRM_ROTATE_90):
6156a456 3040 plane_ctl_rotation = PLANE_CTL_ROTATE_90;
3b7a5119 3041 break;
3b7a5119 3042 case BIT(DRM_ROTATE_180):
6156a456 3043 plane_ctl_rotation = PLANE_CTL_ROTATE_180;
3b7a5119 3044 break;
3b7a5119 3045 case BIT(DRM_ROTATE_270):
6156a456 3046 plane_ctl_rotation = PLANE_CTL_ROTATE_270;
3b7a5119 3047 break;
6156a456
CK		 3048 default:
3049 MISSING_CASE(rotation);
3050 }
3051
3052 return plane_ctl_rotation;
3053}
3054
3055static void skylake_update_primary_plane(struct drm_crtc *crtc,
3056 struct drm_framebuffer *fb,
3057 int x, int y)
3058{
3059 struct drm_device *dev = crtc->dev;
3060 struct drm_i915_private *dev_priv = dev->dev_private;
3061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3062 struct drm_i915_gem_object *obj;
3063 int pipe = intel_crtc->pipe;
3064 u32 plane_ctl, stride_div, stride;
3065 u32 tile_height, plane_offset, plane_size;
3066 unsigned int rotation;
3067 int x_offset, y_offset;
3068 unsigned long surf_addr;
3069 struct drm_plane *plane;
3070 struct intel_crtc_state *crtc_state = intel_crtc->config;
3071 struct intel_plane_state *plane_state;
3072 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3073 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3074 int scaler_id = -1;
3075
3076 plane = crtc->primary;
3077 plane_state = to_intel_plane_state(plane->state);
3078
a8ad0d8e 3079 if (!intel_crtc->primary_enabled || !fb) {
6156a456
CK		 3080 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3081 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3082 POSTING_READ(PLANE_CTL(pipe, 0));
3083 return;
3b7a5119 3084 }
70d21f0e 3085
6156a456
CK		 3086 plane_ctl = PLANE_CTL_ENABLE |
3087 PLANE_CTL_PIPE_GAMMA_ENABLE |
3088 PLANE_CTL_PIPE_CSC_ENABLE;
3089
3090 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3091 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3092 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3093
3094 rotation = plane->state->rotation;
3095 plane_ctl |= skl_plane_ctl_rotation(rotation);
3096
b321803d
DL		 3097 obj = intel_fb_obj(fb);
3098 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3099 fb->pixel_format);
3b7a5119
SJ		 3100 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3101
6156a456
CK		 3102 /*
3103 * FIXME: intel_plane_state->src, dst aren't set when transitional
3104 * update_plane helpers are called from legacy paths.
3105 * Once full atomic crtc is available, below check can be avoided.
3106 */
3107 if (drm_rect_width(&plane_state->src)) {
3108 scaler_id = plane_state->scaler_id;
3109 src_x = plane_state->src.x1 >> 16;
3110 src_y = plane_state->src.y1 >> 16;
3111 src_w = drm_rect_width(&plane_state->src) >> 16;
3112 src_h = drm_rect_height(&plane_state->src) >> 16;
3113 dst_x = plane_state->dst.x1;
3114 dst_y = plane_state->dst.y1;
3115 dst_w = drm_rect_width(&plane_state->dst);
3116 dst_h = drm_rect_height(&plane_state->dst);
3117
3118 WARN_ON(x != src_x || y != src_y);
3119 } else {
3120 src_w = intel_crtc->config->pipe_src_w;
3121 src_h = intel_crtc->config->pipe_src_h;
3122 }
3123
3b7a5119
SJ		 3124 if (intel_rotation_90_or_270(rotation)) {
3125 /* stride = Surface height in tiles */
3126 tile_height = intel_tile_height(dev, fb->bits_per_pixel,
3127 fb->modifier[0]);
3128 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3129 x_offset = stride * tile_height - y - src_h;
3b7a5119 3130 y_offset = x;
6156a456 3131 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3132 } else {
3133 stride = fb->pitches[0] / stride_div;
3134 x_offset = x;
3135 y_offset = y;
6156a456 3136 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3137 }
3138 plane_offset = y_offset << 16 | x_offset;
b321803d 3139
70d21f0e 3140 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3141 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3142 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3143 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3144
3145 if (scaler_id >= 0) {
3146 uint32_t ps_ctrl = 0;
3147
3148 WARN_ON(!dst_w || !dst_h);
3149 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3150 crtc_state->scaler_state.scalers[scaler_id].mode;
3151 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3152 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3153 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3154 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3155 I915_WRITE(PLANE_POS(pipe, 0), 0);
3156 } else {
3157 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3158 }
3159
121920fa 3160 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3161
3162 POSTING_READ(PLANE_SURF(pipe, 0));
3163}
3164
17638cd6
JB		 3165/* Assume fb object is pinned & idle & fenced and just update base pointers */
3166static int
3167intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3168 int x, int y, enum mode_set_atomic state)
3169{
3170 struct drm_device *dev = crtc->dev;
3171 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3172
6b8e6ed0
CW		 3173 if (dev_priv->display.disable_fbc)
3174 dev_priv->display.disable_fbc(dev);
81255565 3175
29b9bde6
DV		 3176 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3177
3178 return 0;
81255565
JB		 3179}
3180
7514747d 3181static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3182{
96a02917
VS		 3183 struct drm_crtc *crtc;
3184
70e1e0ec 3185 for_each_crtc(dev, crtc) {
96a02917
VS		 3186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3187 enum plane plane = intel_crtc->plane;
3188
3189 intel_prepare_page_flip(dev, plane);
3190 intel_finish_page_flip_plane(dev, plane);
3191 }
7514747d
VS		 3192}
3193
3194static void intel_update_primary_planes(struct drm_device *dev)
3195{
3196 struct drm_i915_private *dev_priv = dev->dev_private;
3197 struct drm_crtc *crtc;
96a02917 3198
70e1e0ec 3199 for_each_crtc(dev, crtc) {
96a02917
VS		 3200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3201
51fd371b 3202 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3203 /*
3204 * FIXME: Once we have proper support for primary planes (and
3205 * disabling them without disabling the entire crtc) allow again
66e514c1 3206 * a NULL crtc->primary->fb.
947fdaad 3207 */
f4510a27 3208 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3209 dev_priv->display.update_primary_plane(crtc,
66e514c1 3210 crtc->primary->fb,
262ca2b0
MR		 3211 crtc->x,
3212 crtc->y);
51fd371b 3213 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3214 }
3215}
3216
7514747d
VS		 3217void intel_prepare_reset(struct drm_device *dev)
3218{
f98ce92f
VS		 3219 struct drm_i915_private *dev_priv = to_i915(dev);
3220 struct intel_crtc *crtc;
3221
7514747d
VS		 3222 /* no reset support for gen2 */
3223 if (IS_GEN2(dev))
3224 return;
3225
3226 /* reset doesn't touch the display */
3227 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3228 return;
3229
3230 drm_modeset_lock_all(dev);
f98ce92f
VS		 3231
3232 /*
3233 * Disabling the crtcs gracefully seems nicer. Also the
3234 * g33 docs say we should at least disable all the planes.
3235 */
3236 for_each_intel_crtc(dev, crtc) {
3237 if (crtc->active)
3238 dev_priv->display.crtc_disable(&crtc->base);
3239 }
7514747d
VS		 3240}
3241
3242void intel_finish_reset(struct drm_device *dev)
3243{
3244 struct drm_i915_private *dev_priv = to_i915(dev);
3245
3246 /*
3247 * Flips in the rings will be nuked by the reset,
3248 * so complete all pending flips so that user space
3249 * will get its events and not get stuck.
3250 */
3251 intel_complete_page_flips(dev);
3252
3253 /* no reset support for gen2 */
3254 if (IS_GEN2(dev))
3255 return;
3256
3257 /* reset doesn't touch the display */
3258 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3259 /*
3260 * Flips in the rings have been nuked by the reset,
3261 * so update the base address of all primary
3262 * planes to the the last fb to make sure we're
3263 * showing the correct fb after a reset.
3264 */
3265 intel_update_primary_planes(dev);
3266 return;
3267 }
3268
3269 /*
3270 * The display has been reset as well,
3271 * so need a full re-initialization.
3272 */
3273 intel_runtime_pm_disable_interrupts(dev_priv);
3274 intel_runtime_pm_enable_interrupts(dev_priv);
3275
3276 intel_modeset_init_hw(dev);
3277
3278 spin_lock_irq(&dev_priv->irq_lock);
3279 if (dev_priv->display.hpd_irq_setup)
3280 dev_priv->display.hpd_irq_setup(dev);
3281 spin_unlock_irq(&dev_priv->irq_lock);
3282
3283 intel_modeset_setup_hw_state(dev, true);
3284
3285 intel_hpd_init(dev_priv);
3286
3287 drm_modeset_unlock_all(dev);
3288}
3289
14667a4b
CW		 3290static int
3291intel_finish_fb(struct drm_framebuffer *old_fb)
3292{
2ff8fde1 3293 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
14667a4b
CW		 3294 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3295 bool was_interruptible = dev_priv->mm.interruptible;
3296 int ret;
3297
14667a4b
CW		 3298 /* Big Hammer, we also need to ensure that any pending
3299 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3300 * current scanout is retired before unpinning the old
3301 * framebuffer.
3302 *
3303 * This should only fail upon a hung GPU, in which case we
3304 * can safely continue.
3305 */
3306 dev_priv->mm.interruptible = false;
3307 ret = i915_gem_object_finish_gpu(obj);
3308 dev_priv->mm.interruptible = was_interruptible;
3309
3310 return ret;
3311}
3312
7d5e3799
CW		 3313static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3314{
3315 struct drm_device *dev = crtc->dev;
3316 struct drm_i915_private *dev_priv = dev->dev_private;
3317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3318 bool pending;
3319
3320 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3321 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3322 return false;
3323
5e2d7afc 3324 spin_lock_irq(&dev->event_lock);
7d5e3799 3325 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3326 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3327
3328 return pending;
3329}
3330
e30e8f75
GP		 3331static void intel_update_pipe_size(struct intel_crtc *crtc)
3332{
3333 struct drm_device *dev = crtc->base.dev;
3334 struct drm_i915_private *dev_priv = dev->dev_private;
3335 const struct drm_display_mode *adjusted_mode;
3336
3337 if (!i915.fastboot)
3338 return;
3339
3340 /*
3341 * Update pipe size and adjust fitter if needed: the reason for this is
3342 * that in compute_mode_changes we check the native mode (not the pfit
3343 * mode) to see if we can flip rather than do a full mode set. In the
3344 * fastboot case, we'll flip, but if we don't update the pipesrc and
3345 * pfit state, we'll end up with a big fb scanned out into the wrong
3346 * sized surface.
3347 *
3348 * To fix this properly, we need to hoist the checks up into
3349 * compute_mode_changes (or above), check the actual pfit state and
3350 * whether the platform allows pfit disable with pipe active, and only
3351 * then update the pipesrc and pfit state, even on the flip path.
3352 */
3353
6e3c9717 3354 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3355
3356 I915_WRITE(PIPESRC(crtc->pipe),
3357 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3358 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3359 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3360 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3361 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3362 I915_WRITE(PF_CTL(crtc->pipe), 0);
3363 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3364 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3365 }
6e3c9717
ACO		 3366 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3367 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3368}
3369
5e84e1a4
ZW		 3370static void intel_fdi_normal_train(struct drm_crtc *crtc)
3371{
3372 struct drm_device *dev = crtc->dev;
3373 struct drm_i915_private *dev_priv = dev->dev_private;
3374 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3375 int pipe = intel_crtc->pipe;
3376 u32 reg, temp;
3377
3378 /* enable normal train */
3379 reg = FDI_TX_CTL(pipe);
3380 temp = I915_READ(reg);
61e499bf 3381 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3382 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3383 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3384 } else {
3385 temp &= ~FDI_LINK_TRAIN_NONE;
3386 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3387 }
5e84e1a4
ZW		 3388 I915_WRITE(reg, temp);
3389
3390 reg = FDI_RX_CTL(pipe);
3391 temp = I915_READ(reg);
3392 if (HAS_PCH_CPT(dev)) {
3393 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3394 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3395 } else {
3396 temp &= ~FDI_LINK_TRAIN_NONE;
3397 temp |= FDI_LINK_TRAIN_NONE;
3398 }
3399 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3400
3401 /* wait one idle pattern time */
3402 POSTING_READ(reg);
3403 udelay(1000);
357555c0
JB		 3404
3405 /* IVB wants error correction enabled */
3406 if (IS_IVYBRIDGE(dev))
3407 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3408 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3409}
3410
8db9d77b
ZW		 3411/* The FDI link training functions for ILK/Ibexpeak. */
3412static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3413{
3414 struct drm_device *dev = crtc->dev;
3415 struct drm_i915_private *dev_priv = dev->dev_private;
3416 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3417 int pipe = intel_crtc->pipe;
5eddb70b 3418 u32 reg, temp, tries;
8db9d77b 3419
1c8562f6 3420 /* FDI needs bits from pipe first */
0fc932b8 3421 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3422
e1a44743
AJ		 3423 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3424 for train result */
5eddb70b
CW		 3425 reg = FDI_RX_IMR(pipe);
3426 temp = I915_READ(reg);
e1a44743
AJ		 3427 temp &= ~FDI_RX_SYMBOL_LOCK;
3428 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3429 I915_WRITE(reg, temp);
3430 I915_READ(reg);
e1a44743
AJ		 3431 udelay(150);
3432
8db9d77b 3433 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3434 reg = FDI_TX_CTL(pipe);
3435 temp = I915_READ(reg);
627eb5a3 3436 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3437 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3438 temp &= ~FDI_LINK_TRAIN_NONE;
3439 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3440 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3441
5eddb70b
CW		 3442 reg = FDI_RX_CTL(pipe);
3443 temp = I915_READ(reg);
8db9d77b
ZW		 3444 temp &= ~FDI_LINK_TRAIN_NONE;
3445 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3446 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3447
3448 POSTING_READ(reg);
8db9d77b
ZW		 3449 udelay(150);
3450
5b2adf89 3451 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3452 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3453 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3454 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3455
5eddb70b 3456 reg = FDI_RX_IIR(pipe);
e1a44743 3457 for (tries = 0; tries < 5; tries++) {
5eddb70b 3458 temp = I915_READ(reg);
8db9d77b
ZW		 3459 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3460
3461 if ((temp & FDI_RX_BIT_LOCK)) {
3462 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3463 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3464 break;
3465 }
8db9d77b 3466 }
e1a44743 3467 if (tries == 5)
5eddb70b 3468 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3469
3470 /* Train 2 */
5eddb70b
CW		 3471 reg = FDI_TX_CTL(pipe);
3472 temp = I915_READ(reg);
8db9d77b
ZW		 3473 temp &= ~FDI_LINK_TRAIN_NONE;
3474 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3475 I915_WRITE(reg, temp);
8db9d77b 3476
5eddb70b
CW		 3477 reg = FDI_RX_CTL(pipe);
3478 temp = I915_READ(reg);
8db9d77b
ZW		 3479 temp &= ~FDI_LINK_TRAIN_NONE;
3480 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3481 I915_WRITE(reg, temp);
8db9d77b 3482
5eddb70b
CW		 3483 POSTING_READ(reg);
3484 udelay(150);
8db9d77b 3485
5eddb70b 3486 reg = FDI_RX_IIR(pipe);
e1a44743 3487 for (tries = 0; tries < 5; tries++) {
5eddb70b 3488 temp = I915_READ(reg);
8db9d77b
ZW		 3489 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3490
3491 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3492 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3493 DRM_DEBUG_KMS("FDI train 2 done.\n");
3494 break;
3495 }
8db9d77b 3496 }
e1a44743 3497 if (tries == 5)
5eddb70b 3498 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3499
3500 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3501
8db9d77b
ZW		 3502}
3503
0206e353 3504static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3505 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3506 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3507 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3508 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3509};
3510
3511/* The FDI link training functions for SNB/Cougarpoint. */
3512static void gen6_fdi_link_train(struct drm_crtc *crtc)
3513{
3514 struct drm_device *dev = crtc->dev;
3515 struct drm_i915_private *dev_priv = dev->dev_private;
3516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3517 int pipe = intel_crtc->pipe;
fa37d39e 3518 u32 reg, temp, i, retry;
8db9d77b 3519
e1a44743
AJ		 3520 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3521 for train result */
5eddb70b
CW		 3522 reg = FDI_RX_IMR(pipe);
3523 temp = I915_READ(reg);
e1a44743
AJ		 3524 temp &= ~FDI_RX_SYMBOL_LOCK;
3525 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3526 I915_WRITE(reg, temp);
3527
3528 POSTING_READ(reg);
e1a44743
AJ		 3529 udelay(150);
3530
8db9d77b 3531 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3532 reg = FDI_TX_CTL(pipe);
3533 temp = I915_READ(reg);
627eb5a3 3534 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3535 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3536 temp &= ~FDI_LINK_TRAIN_NONE;
3537 temp |= FDI_LINK_TRAIN_PATTERN_1;
3538 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3539 /* SNB-B */
3540 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3541 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3542
d74cf324
DV		 3543 I915_WRITE(FDI_RX_MISC(pipe),
3544 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3545
5eddb70b
CW		 3546 reg = FDI_RX_CTL(pipe);
3547 temp = I915_READ(reg);
8db9d77b
ZW		 3548 if (HAS_PCH_CPT(dev)) {
3549 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3550 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3551 } else {
3552 temp &= ~FDI_LINK_TRAIN_NONE;
3553 temp |= FDI_LINK_TRAIN_PATTERN_1;
3554 }
5eddb70b
CW		 3555 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3556
3557 POSTING_READ(reg);
8db9d77b
ZW		 3558 udelay(150);
3559
0206e353 3560 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3561 reg = FDI_TX_CTL(pipe);
3562 temp = I915_READ(reg);
8db9d77b
ZW		 3563 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3564 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3565 I915_WRITE(reg, temp);
3566
3567 POSTING_READ(reg);
8db9d77b
ZW		 3568 udelay(500);
3569
fa37d39e
SP		 3570 for (retry = 0; retry < 5; retry++) {
3571 reg = FDI_RX_IIR(pipe);
3572 temp = I915_READ(reg);
3573 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3574 if (temp & FDI_RX_BIT_LOCK) {
3575 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3576 DRM_DEBUG_KMS("FDI train 1 done.\n");
3577 break;
3578 }
3579 udelay(50);
8db9d77b 3580 }
fa37d39e
SP		 3581 if (retry < 5)
3582 break;
8db9d77b
ZW		 3583 }
3584 if (i == 4)
5eddb70b 3585 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3586
3587 /* Train 2 */
5eddb70b
CW		 3588 reg = FDI_TX_CTL(pipe);
3589 temp = I915_READ(reg);
8db9d77b
ZW		 3590 temp &= ~FDI_LINK_TRAIN_NONE;
3591 temp |= FDI_LINK_TRAIN_PATTERN_2;
3592 if (IS_GEN6(dev)) {
3593 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3594 /* SNB-B */
3595 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3596 }
5eddb70b 3597 I915_WRITE(reg, temp);
8db9d77b 3598
5eddb70b
CW		 3599 reg = FDI_RX_CTL(pipe);
3600 temp = I915_READ(reg);
8db9d77b
ZW		 3601 if (HAS_PCH_CPT(dev)) {
3602 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3603 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3604 } else {
3605 temp &= ~FDI_LINK_TRAIN_NONE;
3606 temp |= FDI_LINK_TRAIN_PATTERN_2;
3607 }
5eddb70b
CW		 3608 I915_WRITE(reg, temp);
3609
3610 POSTING_READ(reg);
8db9d77b
ZW		 3611 udelay(150);
3612
0206e353 3613 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3614 reg = FDI_TX_CTL(pipe);
3615 temp = I915_READ(reg);
8db9d77b
ZW		 3616 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3617 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3618 I915_WRITE(reg, temp);
3619
3620 POSTING_READ(reg);
8db9d77b
ZW		 3621 udelay(500);
3622
fa37d39e
SP		 3623 for (retry = 0; retry < 5; retry++) {
3624 reg = FDI_RX_IIR(pipe);
3625 temp = I915_READ(reg);
3626 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3627 if (temp & FDI_RX_SYMBOL_LOCK) {
3628 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3629 DRM_DEBUG_KMS("FDI train 2 done.\n");
3630 break;
3631 }
3632 udelay(50);
8db9d77b 3633 }
fa37d39e
SP		 3634 if (retry < 5)
3635 break;
8db9d77b
ZW		 3636 }
3637 if (i == 4)
5eddb70b 3638 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3639
3640 DRM_DEBUG_KMS("FDI train done.\n");
3641}
3642
357555c0
JB		 3643/* Manual link training for Ivy Bridge A0 parts */
3644static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3645{
3646 struct drm_device *dev = crtc->dev;
3647 struct drm_i915_private *dev_priv = dev->dev_private;
3648 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3649 int pipe = intel_crtc->pipe;
139ccd3f 3650 u32 reg, temp, i, j;
357555c0
JB		 3651
3652 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3653 for train result */
3654 reg = FDI_RX_IMR(pipe);
3655 temp = I915_READ(reg);
3656 temp &= ~FDI_RX_SYMBOL_LOCK;
3657 temp &= ~FDI_RX_BIT_LOCK;
3658 I915_WRITE(reg, temp);
3659
3660 POSTING_READ(reg);
3661 udelay(150);
3662
01a415fd
DV		 3663 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3664 I915_READ(FDI_RX_IIR(pipe)));
3665
139ccd3f
JB		 3666 /* Try each vswing and preemphasis setting twice before moving on */
3667 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3668 /* disable first in case we need to retry */
3669 reg = FDI_TX_CTL(pipe);
3670 temp = I915_READ(reg);
3671 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3672 temp &= ~FDI_TX_ENABLE;
3673 I915_WRITE(reg, temp);
357555c0 3674
139ccd3f
JB		 3675 reg = FDI_RX_CTL(pipe);
3676 temp = I915_READ(reg);
3677 temp &= ~FDI_LINK_TRAIN_AUTO;
3678 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3679 temp &= ~FDI_RX_ENABLE;
3680 I915_WRITE(reg, temp);
357555c0 3681
139ccd3f 3682 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3683 reg = FDI_TX_CTL(pipe);
3684 temp = I915_READ(reg);
139ccd3f 3685 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3686 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3687 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3688 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3689 temp |= snb_b_fdi_train_param[j/2];
3690 temp |= FDI_COMPOSITE_SYNC;
3691 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3692
139ccd3f
JB		 3693 I915_WRITE(FDI_RX_MISC(pipe),
3694 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3695
139ccd3f 3696 reg = FDI_RX_CTL(pipe);
357555c0 3697 temp = I915_READ(reg);
139ccd3f
JB		 3698 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3699 temp |= FDI_COMPOSITE_SYNC;
3700 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3701
139ccd3f
JB		 3702 POSTING_READ(reg);
3703 udelay(1); /* should be 0.5us */
357555c0 3704
139ccd3f
JB		 3705 for (i = 0; i < 4; i++) {
3706 reg = FDI_RX_IIR(pipe);
3707 temp = I915_READ(reg);
3708 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3709
139ccd3f
JB		 3710 if (temp & FDI_RX_BIT_LOCK ||
3711 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3712 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3713 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3714 i);
3715 break;
3716 }
3717 udelay(1); /* should be 0.5us */
3718 }
3719 if (i == 4) {
3720 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3721 continue;
3722 }
357555c0 3723
139ccd3f 3724 /* Train 2 */
357555c0
JB		 3725 reg = FDI_TX_CTL(pipe);
3726 temp = I915_READ(reg);
139ccd3f
JB		 3727 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3728 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3729 I915_WRITE(reg, temp);
3730
3731 reg = FDI_RX_CTL(pipe);
3732 temp = I915_READ(reg);
3733 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3734 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3735 I915_WRITE(reg, temp);
3736
3737 POSTING_READ(reg);
139ccd3f 3738 udelay(2); /* should be 1.5us */
357555c0 3739
139ccd3f
JB		 3740 for (i = 0; i < 4; i++) {
3741 reg = FDI_RX_IIR(pipe);
3742 temp = I915_READ(reg);
3743 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3744
139ccd3f
JB		 3745 if (temp & FDI_RX_SYMBOL_LOCK ||
3746 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3747 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3748 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3749 i);
3750 goto train_done;
3751 }
3752 udelay(2); /* should be 1.5us */
357555c0 3753 }
139ccd3f
JB		 3754 if (i == 4)
3755 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3756 }
357555c0 3757
139ccd3f 3758train_done:
357555c0
JB		 3759 DRM_DEBUG_KMS("FDI train done.\n");
3760}
3761
88cefb6c 3762static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3763{
88cefb6c 3764 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3765 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3766 int pipe = intel_crtc->pipe;
5eddb70b 3767 u32 reg, temp;
79e53945 3768
c64e311e 3769
c98e9dcf 3770 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3771 reg = FDI_RX_CTL(pipe);
3772 temp = I915_READ(reg);
627eb5a3 3773 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3774 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3775 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3776 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3777
3778 POSTING_READ(reg);
c98e9dcf
JB		 3779 udelay(200);
3780
3781 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3782 temp = I915_READ(reg);
3783 I915_WRITE(reg, temp | FDI_PCDCLK);
3784
3785 POSTING_READ(reg);
c98e9dcf
JB		 3786 udelay(200);
3787
20749730
PZ		 3788 /* Enable CPU FDI TX PLL, always on for Ironlake */
3789 reg = FDI_TX_CTL(pipe);
3790 temp = I915_READ(reg);
3791 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3792 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3793
20749730
PZ		 3794 POSTING_READ(reg);
3795 udelay(100);
6be4a607 3796 }
0e23b99d
JB		 3797}
3798
88cefb6c
DV		 3799static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3800{
3801 struct drm_device *dev = intel_crtc->base.dev;
3802 struct drm_i915_private *dev_priv = dev->dev_private;
3803 int pipe = intel_crtc->pipe;
3804 u32 reg, temp;
3805
3806 /* Switch from PCDclk to Rawclk */
3807 reg = FDI_RX_CTL(pipe);
3808 temp = I915_READ(reg);
3809 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3810
3811 /* Disable CPU FDI TX PLL */
3812 reg = FDI_TX_CTL(pipe);
3813 temp = I915_READ(reg);
3814 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3815
3816 POSTING_READ(reg);
3817 udelay(100);
3818
3819 reg = FDI_RX_CTL(pipe);
3820 temp = I915_READ(reg);
3821 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3822
3823 /* Wait for the clocks to turn off. */
3824 POSTING_READ(reg);
3825 udelay(100);
3826}
3827
0fc932b8
JB		 3828static void ironlake_fdi_disable(struct drm_crtc *crtc)
3829{
3830 struct drm_device *dev = crtc->dev;
3831 struct drm_i915_private *dev_priv = dev->dev_private;
3832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3833 int pipe = intel_crtc->pipe;
3834 u32 reg, temp;
3835
3836 /* disable CPU FDI tx and PCH FDI rx */
3837 reg = FDI_TX_CTL(pipe);
3838 temp = I915_READ(reg);
3839 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3840 POSTING_READ(reg);
3841
3842 reg = FDI_RX_CTL(pipe);
3843 temp = I915_READ(reg);
3844 temp &= ~(0x7 << 16);
dfd07d72 3845 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3846 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3847
3848 POSTING_READ(reg);
3849 udelay(100);
3850
3851 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3852 if (HAS_PCH_IBX(dev))
6f06ce18 3853 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3854
3855 /* still set train pattern 1 */
3856 reg = FDI_TX_CTL(pipe);
3857 temp = I915_READ(reg);
3858 temp &= ~FDI_LINK_TRAIN_NONE;
3859 temp |= FDI_LINK_TRAIN_PATTERN_1;
3860 I915_WRITE(reg, temp);
3861
3862 reg = FDI_RX_CTL(pipe);
3863 temp = I915_READ(reg);
3864 if (HAS_PCH_CPT(dev)) {
3865 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3866 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3867 } else {
3868 temp &= ~FDI_LINK_TRAIN_NONE;
3869 temp |= FDI_LINK_TRAIN_PATTERN_1;
3870 }
3871 /* BPC in FDI rx is consistent with that in PIPECONF */
3872 temp &= ~(0x07 << 16);
dfd07d72 3873 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3874 I915_WRITE(reg, temp);
3875
3876 POSTING_READ(reg);
3877 udelay(100);
3878}
3879
5dce5b93
CW		 3880bool intel_has_pending_fb_unpin(struct drm_device *dev)
3881{
3882 struct intel_crtc *crtc;
3883
3884 /* Note that we don't need to be called with mode_config.lock here
3885 * as our list of CRTC objects is static for the lifetime of the
3886 * device and so cannot disappear as we iterate. Similarly, we can
3887 * happily treat the predicates as racy, atomic checks as userspace
3888 * cannot claim and pin a new fb without at least acquring the
3889 * struct_mutex and so serialising with us.
3890 */
d3fcc808 3891 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3892 if (atomic_read(&crtc->unpin_work_count) == 0)
3893 continue;
3894
3895 if (crtc->unpin_work)
3896 intel_wait_for_vblank(dev, crtc->pipe);
3897
3898 return true;
3899 }
3900
3901 return false;
3902}
3903
d6bbafa1
CW		 3904static void page_flip_completed(struct intel_crtc *intel_crtc)
3905{
3906 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3907 struct intel_unpin_work *work = intel_crtc->unpin_work;
3908
3909 /* ensure that the unpin work is consistent wrt ->pending. */
3910 smp_rmb();
3911 intel_crtc->unpin_work = NULL;
3912
3913 if (work->event)
3914 drm_send_vblank_event(intel_crtc->base.dev,
3915 intel_crtc->pipe,
3916 work->event);
3917
3918 drm_crtc_vblank_put(&intel_crtc->base);
3919
3920 wake_up_all(&dev_priv->pending_flip_queue);
3921 queue_work(dev_priv->wq, &work->work);
3922
3923 trace_i915_flip_complete(intel_crtc->plane,
3924 work->pending_flip_obj);
3925}
3926
46a55d30 3927void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3928{
0f91128d 3929 struct drm_device *dev = crtc->dev;
5bb61643 3930 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3931
2c10d571 3932 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3933 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3934 !intel_crtc_has_pending_flip(crtc),
3935 60*HZ) == 0)) {
3936 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3937
5e2d7afc 3938 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3939 if (intel_crtc->unpin_work) {
3940 WARN_ONCE(1, "Removing stuck page flip\n");
3941 page_flip_completed(intel_crtc);
3942 }
5e2d7afc 3943 spin_unlock_irq(&dev->event_lock);
9c787942 3944 }
5bb61643 3945
975d568a
CW		 3946 if (crtc->primary->fb) {
3947 mutex_lock(&dev->struct_mutex);
3948 intel_finish_fb(crtc->primary->fb);
3949 mutex_unlock(&dev->struct_mutex);
3950 }
e6c3a2a6
CW		 3951}
3952
e615efe4
ED		 3953/* Program iCLKIP clock to the desired frequency */
3954static void lpt_program_iclkip(struct drm_crtc *crtc)
3955{
3956 struct drm_device *dev = crtc->dev;
3957 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3958 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3959 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3960 u32 temp;
3961
09153000
DV		 3962 mutex_lock(&dev_priv->dpio_lock);
3963
e615efe4
ED		 3964 /* It is necessary to ungate the pixclk gate prior to programming
3965 * the divisors, and gate it back when it is done.
3966 */
3967 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3968
3969 /* Disable SSCCTL */
3970 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3971 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3972 SBI_SSCCTL_DISABLE,
3973 SBI_ICLK);
e615efe4
ED		 3974
3975 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3976 if (clock == 20000) {
e615efe4
ED		 3977 auxdiv = 1;
3978 divsel = 0x41;
3979 phaseinc = 0x20;
3980 } else {
3981 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3982 * but the adjusted_mode->crtc_clock in in KHz. To get the
3983 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3984 * convert the virtual clock precision to KHz here for higher
3985 * precision.
3986 */
3987 u32 iclk_virtual_root_freq = 172800 * 1000;
3988 u32 iclk_pi_range = 64;
3989 u32 desired_divisor, msb_divisor_value, pi_value;
3990
12d7ceed 3991 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3992 msb_divisor_value = desired_divisor / iclk_pi_range;
3993 pi_value = desired_divisor % iclk_pi_range;
3994
3995 auxdiv = 0;
3996 divsel = msb_divisor_value - 2;
3997 phaseinc = pi_value;
3998 }
3999
4000 /* This should not happen with any sane values */
4001 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
4002 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
4003 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
4004 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4005
4006 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 4007 clock,
e615efe4
ED		 4008 auxdiv,
4009 divsel,
4010 phasedir,
4011 phaseinc);
4012
4013 /* Program SSCDIVINTPHASE6 */
988d6ee8 4014 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 4015 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4016 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4017 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4018 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4019 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4020 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 4021 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 4022
4023 /* Program SSCAUXDIV */
988d6ee8 4024 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 4025 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4026 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 4027 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 4028
4029 /* Enable modulator and associated divider */
988d6ee8 4030 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4031 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4032 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4033
4034 /* Wait for initialization time */
4035 udelay(24);
4036
4037 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 4038
4039 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 4040}
4041
275f01b2
DV		 4042static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4043 enum pipe pch_transcoder)
4044{
4045 struct drm_device *dev = crtc->base.dev;
4046 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4047 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4048
4049 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4050 I915_READ(HTOTAL(cpu_transcoder)));
4051 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4052 I915_READ(HBLANK(cpu_transcoder)));
4053 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4054 I915_READ(HSYNC(cpu_transcoder)));
4055
4056 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4057 I915_READ(VTOTAL(cpu_transcoder)));
4058 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4059 I915_READ(VBLANK(cpu_transcoder)));
4060 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4061 I915_READ(VSYNC(cpu_transcoder)));
4062 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4063 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4064}
4065
003632d9 4066static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4067{
4068 struct drm_i915_private *dev_priv = dev->dev_private;
4069 uint32_t temp;
4070
4071 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4072 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4073 return;
4074
4075 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4076 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4077
003632d9
ACO		 4078 temp &= ~FDI_BC_BIFURCATION_SELECT;
4079 if (enable)
4080 temp |= FDI_BC_BIFURCATION_SELECT;
4081
4082 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4083 I915_WRITE(SOUTH_CHICKEN1, temp);
4084 POSTING_READ(SOUTH_CHICKEN1);
4085}
4086
4087static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4088{
4089 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4090
4091 switch (intel_crtc->pipe) {
4092 case PIPE_A:
4093 break;
4094 case PIPE_B:
6e3c9717 4095 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4096 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4097 else
003632d9 4098 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4099
4100 break;
4101 case PIPE_C:
003632d9 4102 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4103
4104 break;
4105 default:
4106 BUG();
4107 }
4108}
4109
f67a559d
JB		 4110/*
4111 * Enable PCH resources required for PCH ports:
4112 * - PCH PLLs
4113 * - FDI training & RX/TX
4114 * - update transcoder timings
4115 * - DP transcoding bits
4116 * - transcoder
4117 */
4118static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4119{
4120 struct drm_device *dev = crtc->dev;
4121 struct drm_i915_private *dev_priv = dev->dev_private;
4122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4123 int pipe = intel_crtc->pipe;
ee7b9f93 4124 u32 reg, temp;
2c07245f 4125
ab9412ba 4126 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4127
1fbc0d78
DV		 4128 if (IS_IVYBRIDGE(dev))
4129 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4130
cd986abb
DV		 4131 /* Write the TU size bits before fdi link training, so that error
4132 * detection works. */
4133 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4134 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4135
c98e9dcf 4136 /* For PCH output, training FDI link */
674cf967 4137 dev_priv->display.fdi_link_train(crtc);
2c07245f 4138
3ad8a208
DV		 4139 /* We need to program the right clock selection before writing the pixel
4140 * mutliplier into the DPLL. */
303b81e0 4141 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4142 u32 sel;
4b645f14 4143
c98e9dcf 4144 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4145 temp |= TRANS_DPLL_ENABLE(pipe);
4146 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4147 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4148 temp |= sel;
4149 else
4150 temp &= ~sel;
c98e9dcf 4151 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4152 }
5eddb70b 4153
3ad8a208
DV		 4154 /* XXX: pch pll's can be enabled any time before we enable the PCH
4155 * transcoder, and we actually should do this to not upset any PCH
4156 * transcoder that already use the clock when we share it.
4157 *
4158 * Note that enable_shared_dpll tries to do the right thing, but
4159 * get_shared_dpll unconditionally resets the pll - we need that to have
4160 * the right LVDS enable sequence. */
85b3894f 4161 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4162
d9b6cb56
JB		 4163 /* set transcoder timing, panel must allow it */
4164 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4165 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4166
303b81e0 4167 intel_fdi_normal_train(crtc);
5e84e1a4 4168
c98e9dcf 4169 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4170 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4171 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4172 reg = TRANS_DP_CTL(pipe);
4173 temp = I915_READ(reg);
4174 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4175 TRANS_DP_SYNC_MASK |
4176 TRANS_DP_BPC_MASK);
5eddb70b
CW		 4177 temp |= (TRANS_DP_OUTPUT_ENABLE |
4178 TRANS_DP_ENH_FRAMING);
9325c9f0 4179 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4180
4181 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4182 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4183 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4184 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4185
4186 switch (intel_trans_dp_port_sel(crtc)) {
4187 case PCH_DP_B:
5eddb70b 4188 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4189 break;
4190 case PCH_DP_C:
5eddb70b 4191 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4192 break;
4193 case PCH_DP_D:
5eddb70b 4194 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4195 break;
4196 default:
e95d41e1 4197 BUG();
32f9d658 4198 }
2c07245f 4199
5eddb70b 4200 I915_WRITE(reg, temp);
6be4a607 4201 }
b52eb4dc 4202
b8a4f404 4203 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4204}
4205
1507e5bd
PZ		 4206static void lpt_pch_enable(struct drm_crtc *crtc)
4207{
4208 struct drm_device *dev = crtc->dev;
4209 struct drm_i915_private *dev_priv = dev->dev_private;
4210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4211 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4212
ab9412ba 4213 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4214
8c52b5e8 4215 lpt_program_iclkip(crtc);
1507e5bd 4216
0540e488 4217 /* Set transcoder timing. */
275f01b2 4218 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4219
937bb610 4220 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4221}
4222
716c2e55 4223void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 4224{
e2b78267 4225 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 4226
4227 if (pll == NULL)
4228 return;
4229
3e369b76 4230 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
1e6f2ddc 4231 WARN(1, "bad %s crtc mask\n", pll->name);
ee7b9f93
JB		 4232 return;
4233 }
4234
3e369b76
ACO		 4235 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4236 if (pll->config.crtc_mask == 0) {
f4a091c7
DV		 4237 WARN_ON(pll->on);
4238 WARN_ON(pll->active);
4239 }
4240
6e3c9717 4241 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 4242}
4243
190f68c5
ACO		 4244struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4245 struct intel_crtc_state *crtc_state)
ee7b9f93 4246{
e2b78267 4247 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4248 struct intel_shared_dpll *pll;
e2b78267 4249 enum intel_dpll_id i;
ee7b9f93 4250
98b6bd99
DV		 4251 if (HAS_PCH_IBX(dev_priv->dev)) {
4252 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4253 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4254 pll = &dev_priv->shared_dplls[i];
98b6bd99 4255
46edb027
DV		 4256 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4257 crtc->base.base.id, pll->name);
98b6bd99 4258
8bd31e67 4259 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4260
98b6bd99
DV		 4261 goto found;
4262 }
4263
bcddf610
S		 4264 if (IS_BROXTON(dev_priv->dev)) {
4265 /* PLL is attached to port in bxt */
4266 struct intel_encoder *encoder;
4267 struct intel_digital_port *intel_dig_port;
4268
4269 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4270 if (WARN_ON(!encoder))
4271 return NULL;
4272
4273 intel_dig_port = enc_to_dig_port(&encoder->base);
4274 /* 1:1 mapping between ports and PLLs */
4275 i = (enum intel_dpll_id)intel_dig_port->port;
4276 pll = &dev_priv->shared_dplls[i];
4277 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4278 crtc->base.base.id, pll->name);
4279 WARN_ON(pll->new_config->crtc_mask);
4280
4281 goto found;
4282 }
4283
e72f9fbf
DV		 4284 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4285 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4286
4287 /* Only want to check enabled timings first */
8bd31e67 4288 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4289 continue;
4290
190f68c5 4291 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4292 &pll->new_config->hw_state,
4293 sizeof(pll->new_config->hw_state)) == 0) {
4294 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4295 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4296 pll->new_config->crtc_mask,
4297 pll->active);
ee7b9f93
JB		 4298 goto found;
4299 }
4300 }
4301
4302 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4303 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4304 pll = &dev_priv->shared_dplls[i];
8bd31e67 4305 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4306 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4307 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4308 goto found;
4309 }
4310 }
4311
4312 return NULL;
4313
4314found:
8bd31e67 4315 if (pll->new_config->crtc_mask == 0)
190f68c5 4316 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4317
190f68c5 4318 crtc_state->shared_dpll = i;
46edb027
DV		 4319 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4320 pipe_name(crtc->pipe));
ee7b9f93 4321
8bd31e67 4322 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4323
ee7b9f93
JB		 4324 return pll;
4325}
4326
8bd31e67
ACO		 4327/**
4328 * intel_shared_dpll_start_config - start a new PLL staged config
4329 * @dev_priv: DRM device
4330 * @clear_pipes: mask of pipes that will have their PLLs freed
4331 *
4332 * Starts a new PLL staged config, copying the current config but
4333 * releasing the references of pipes specified in clear_pipes.
4334 */
4335static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4336 unsigned clear_pipes)
4337{
4338 struct intel_shared_dpll *pll;
4339 enum intel_dpll_id i;
4340
4341 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4342 pll = &dev_priv->shared_dplls[i];
4343
4344 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4345 GFP_KERNEL);
4346 if (!pll->new_config)
4347 goto cleanup;
4348
4349 pll->new_config->crtc_mask &= ~clear_pipes;
4350 }
4351
4352 return 0;
4353
4354cleanup:
4355 while (--i >= 0) {
4356 pll = &dev_priv->shared_dplls[i];
f354d733 4357 kfree(pll->new_config);
8bd31e67
ACO		 4358 pll->new_config = NULL;
4359 }
4360
4361 return -ENOMEM;
4362}
4363
4364static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4365{
4366 struct intel_shared_dpll *pll;
4367 enum intel_dpll_id i;
4368
4369 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4370 pll = &dev_priv->shared_dplls[i];
4371
4372 WARN_ON(pll->new_config == &pll->config);
4373
4374 pll->config = *pll->new_config;
4375 kfree(pll->new_config);
4376 pll->new_config = NULL;
4377 }
4378}
4379
4380static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4381{
4382 struct intel_shared_dpll *pll;
4383 enum intel_dpll_id i;
4384
4385 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4386 pll = &dev_priv->shared_dplls[i];
4387
4388 WARN_ON(pll->new_config == &pll->config);
4389
4390 kfree(pll->new_config);
4391 pll->new_config = NULL;
4392 }
4393}
4394
a1520318 4395static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4396{
4397 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4398 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4399 u32 temp;
4400
4401 temp = I915_READ(dslreg);
4402 udelay(500);
4403 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4404 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4405 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4406 }
4407}
4408
a1b2278e
CK		 4409/**
4410 * skl_update_scaler_users - Stages update to crtc's scaler state
4411 * @intel_crtc: crtc
4412 * @crtc_state: crtc_state
4413 * @plane: plane (NULL indicates crtc is requesting update)
4414 * @plane_state: plane's state
4415 * @force_detach: request unconditional detachment of scaler
4416 *
4417 * This function updates scaler state for requested plane or crtc.
4418 * To request scaler usage update for a plane, caller shall pass plane pointer.
4419 * To request scaler usage update for crtc, caller shall pass plane pointer
4420 * as NULL.
4421 *
4422 * Return
4423 * 0 - scaler_usage updated successfully
4424 * error - requested scaling cannot be supported or other error condition
4425 */
4426int
4427skl_update_scaler_users(
4428 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4429 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4430 int force_detach)
4431{
4432 int need_scaling;
4433 int idx;
4434 int src_w, src_h, dst_w, dst_h;
4435 int *scaler_id;
4436 struct drm_framebuffer *fb;
4437 struct intel_crtc_scaler_state *scaler_state;
6156a456 4438 unsigned int rotation;
a1b2278e
CK		 4439
4440 if (!intel_crtc || !crtc_state)
4441 return 0;
4442
4443 scaler_state = &crtc_state->scaler_state;
4444
4445 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4446 fb = intel_plane ? plane_state->base.fb : NULL;
4447
4448 if (intel_plane) {
4449 src_w = drm_rect_width(&plane_state->src) >> 16;
4450 src_h = drm_rect_height(&plane_state->src) >> 16;
4451 dst_w = drm_rect_width(&plane_state->dst);
4452 dst_h = drm_rect_height(&plane_state->dst);
4453 scaler_id = &plane_state->scaler_id;
6156a456 4454 rotation = plane_state->base.rotation;
a1b2278e
CK		 4455 } else {
4456 struct drm_display_mode *adjusted_mode =
4457 &crtc_state->base.adjusted_mode;
4458 src_w = crtc_state->pipe_src_w;
4459 src_h = crtc_state->pipe_src_h;
4460 dst_w = adjusted_mode->hdisplay;
4461 dst_h = adjusted_mode->vdisplay;
4462 scaler_id = &scaler_state->scaler_id;
6156a456 4463 rotation = DRM_ROTATE_0;
a1b2278e 4464 }
6156a456
CK		 4465
4466 need_scaling = intel_rotation_90_or_270(rotation) ?
4467 (src_h != dst_w || src_w != dst_h):
4468 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4469
4470 /*
4471 * if plane is being disabled or scaler is no more required or force detach
4472 * - free scaler binded to this plane/crtc
4473 * - in order to do this, update crtc->scaler_usage
4474 *
4475 * Here scaler state in crtc_state is set free so that
4476 * scaler can be assigned to other user. Actual register
4477 * update to free the scaler is done in plane/panel-fit programming.
4478 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4479 */
4480 if (force_detach || !need_scaling || (intel_plane &&
4481 (!fb || !plane_state->visible))) {
4482 if (*scaler_id >= 0) {
4483 scaler_state->scaler_users &= ~(1 << idx);
4484 scaler_state->scalers[*scaler_id].in_use = 0;
4485
4486 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4487 "crtc_state = %p scaler_users = 0x%x\n",
4488 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4489 intel_plane ? intel_plane->base.base.id :
4490 intel_crtc->base.base.id, crtc_state,
4491 scaler_state->scaler_users);
4492 *scaler_id = -1;
4493 }
4494 return 0;
4495 }
4496
4497 /* range checks */
4498 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4499 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4500
4501 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4502 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4503 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4504 "size is out of scaler range\n",
4505 intel_plane ? "PLANE" : "CRTC",
4506 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4507 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4508 return -EINVAL;
4509 }
4510
4511 /* check colorkey */
4512 if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) {
4513 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4514 intel_plane->base.base.id);
4515 return -EINVAL;
4516 }
4517
4518 /* Check src format */
4519 if (intel_plane) {
4520 switch (fb->pixel_format) {
4521 case DRM_FORMAT_RGB565:
4522 case DRM_FORMAT_XBGR8888:
4523 case DRM_FORMAT_XRGB8888:
4524 case DRM_FORMAT_ABGR8888:
4525 case DRM_FORMAT_ARGB8888:
4526 case DRM_FORMAT_XRGB2101010:
4527 case DRM_FORMAT_ARGB2101010:
4528 case DRM_FORMAT_XBGR2101010:
4529 case DRM_FORMAT_ABGR2101010:
4530 case DRM_FORMAT_YUYV:
4531 case DRM_FORMAT_YVYU:
4532 case DRM_FORMAT_UYVY:
4533 case DRM_FORMAT_VYUY:
4534 break;
4535 default:
4536 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4537 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4538 return -EINVAL;
4539 }
4540 }
4541
4542 /* mark this plane as a scaler user in crtc_state */
4543 scaler_state->scaler_users |= (1 << idx);
4544 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4545 "crtc_state = %p scaler_users = 0x%x\n",
4546 intel_plane ? "PLANE" : "CRTC",
4547 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4548 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4549 return 0;
4550}
4551
4552static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4553{
4554 struct drm_device *dev = crtc->base.dev;
4555 struct drm_i915_private *dev_priv = dev->dev_private;
4556 int pipe = crtc->pipe;
a1b2278e
CK		 4557 struct intel_crtc_scaler_state *scaler_state =
4558 &crtc->config->scaler_state;
4559
4560 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4561
4562 /* To update pfit, first update scaler state */
4563 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4564 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4565 skl_detach_scalers(crtc);
4566 if (!enable)
4567 return;
bd2e244f 4568
6e3c9717 4569 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4570 int id;
4571
4572 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4573 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4574 return;
4575 }
4576
4577 id = scaler_state->scaler_id;
4578 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4579 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4580 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4581 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4582
4583 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4584 }
4585}
4586
b074cec8
JB		 4587static void ironlake_pfit_enable(struct intel_crtc *crtc)
4588{
4589 struct drm_device *dev = crtc->base.dev;
4590 struct drm_i915_private *dev_priv = dev->dev_private;
4591 int pipe = crtc->pipe;
4592
6e3c9717 4593 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4594 /* Force use of hard-coded filter coefficients
4595 * as some pre-programmed values are broken,
4596 * e.g. x201.
4597 */
4598 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4599 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4600 PF_PIPE_SEL_IVB(pipe));
4601 else
4602 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4603 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4604 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4605 }
4606}
4607
4a3b8769 4608static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4609{
4610 struct drm_device *dev = crtc->dev;
4611 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4612 struct drm_plane *plane;
bb53d4ae
VS		 4613 struct intel_plane *intel_plane;
4614
af2b653b
MR		 4615 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4616 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4617 if (intel_plane->pipe == pipe)
4618 intel_plane_restore(&intel_plane->base);
af2b653b 4619 }
bb53d4ae
VS		 4620}
4621
20bc8673 4622void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4623{
cea165c3
VS		 4624 struct drm_device *dev = crtc->base.dev;
4625 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4626
6e3c9717 4627 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4628 return;
4629
cea165c3
VS		 4630 /* We can only enable IPS after we enable a plane and wait for a vblank */
4631 intel_wait_for_vblank(dev, crtc->pipe);
4632
d77e4531 4633 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4634 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4635 mutex_lock(&dev_priv->rps.hw_lock);
4636 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4637 mutex_unlock(&dev_priv->rps.hw_lock);
4638 /* Quoting Art Runyan: "its not safe to expect any particular
4639 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4640 * mailbox." Moreover, the mailbox may return a bogus state,
4641 * so we need to just enable it and continue on.
2a114cc1
BW		 4642 */
4643 } else {
4644 I915_WRITE(IPS_CTL, IPS_ENABLE);
4645 /* The bit only becomes 1 in the next vblank, so this wait here
4646 * is essentially intel_wait_for_vblank. If we don't have this
4647 * and don't wait for vblanks until the end of crtc_enable, then
4648 * the HW state readout code will complain that the expected
4649 * IPS_CTL value is not the one we read. */
4650 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4651 DRM_ERROR("Timed out waiting for IPS enable\n");
4652 }
d77e4531
PZ		 4653}
4654
20bc8673 4655void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4656{
4657 struct drm_device *dev = crtc->base.dev;
4658 struct drm_i915_private *dev_priv = dev->dev_private;
4659
6e3c9717 4660 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4661 return;
4662
4663 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4664 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4665 mutex_lock(&dev_priv->rps.hw_lock);
4666 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4667 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4668 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4669 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4670 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4671 } else {
2a114cc1 4672 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4673 POSTING_READ(IPS_CTL);
4674 }
d77e4531
PZ		 4675
4676 /* We need to wait for a vblank before we can disable the plane. */
4677 intel_wait_for_vblank(dev, crtc->pipe);
4678}
4679
4680/** Loads the palette/gamma unit for the CRTC with the prepared values */
4681static void intel_crtc_load_lut(struct drm_crtc *crtc)
4682{
4683 struct drm_device *dev = crtc->dev;
4684 struct drm_i915_private *dev_priv = dev->dev_private;
4685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4686 enum pipe pipe = intel_crtc->pipe;
4687 int palreg = PALETTE(pipe);
4688 int i;
4689 bool reenable_ips = false;
4690
4691 /* The clocks have to be on to load the palette. */
83d65738 4692 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4693 return;
4694
50360403 4695 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4696 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4697 assert_dsi_pll_enabled(dev_priv);
4698 else
4699 assert_pll_enabled(dev_priv, pipe);
4700 }
4701
4702 /* use legacy palette for Ironlake */
7a1db49a 4703 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4704 palreg = LGC_PALETTE(pipe);
4705
4706 /* Workaround : Do not read or write the pipe palette/gamma data while
4707 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4708 */
6e3c9717 4709 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4710 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4711 GAMMA_MODE_MODE_SPLIT)) {
4712 hsw_disable_ips(intel_crtc);
4713 reenable_ips = true;
4714 }
4715
4716 for (i = 0; i < 256; i++) {
4717 I915_WRITE(palreg + 4 * i,
4718 (intel_crtc->lut_r[i] << 16) |
4719 (intel_crtc->lut_g[i] << 8) |
4720 intel_crtc->lut_b[i]);
4721 }
4722
4723 if (reenable_ips)
4724 hsw_enable_ips(intel_crtc);
4725}
4726
d3eedb1a
VS		 4727static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4728{
4729 if (!enable && intel_crtc->overlay) {
4730 struct drm_device *dev = intel_crtc->base.dev;
4731 struct drm_i915_private *dev_priv = dev->dev_private;
4732
4733 mutex_lock(&dev->struct_mutex);
4734 dev_priv->mm.interruptible = false;
4735 (void) intel_overlay_switch_off(intel_crtc->overlay);
4736 dev_priv->mm.interruptible = true;
4737 mutex_unlock(&dev->struct_mutex);
4738 }
4739
4740 /* Let userspace switch the overlay on again. In most cases userspace
4741 * has to recompute where to put it anyway.
4742 */
4743}
4744
d3eedb1a 4745static void intel_crtc_enable_planes(struct drm_crtc *crtc)
a5c4d7bc
VS		 4746{
4747 struct drm_device *dev = crtc->dev;
a5c4d7bc
VS		 4748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4749 int pipe = intel_crtc->pipe;
a5c4d7bc 4750
fdd508a6 4751 intel_enable_primary_hw_plane(crtc->primary, crtc);
4a3b8769 4752 intel_enable_sprite_planes(crtc);
a5c4d7bc 4753 intel_crtc_update_cursor(crtc, true);
d3eedb1a 4754 intel_crtc_dpms_overlay(intel_crtc, true);
a5c4d7bc
VS		 4755
4756 hsw_enable_ips(intel_crtc);
4757
4758 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4759 intel_fbc_update(dev);
a5c4d7bc 4760 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4761
4762 /*
4763 * FIXME: Once we grow proper nuclear flip support out of this we need
4764 * to compute the mask of flip planes precisely. For the time being
4765 * consider this a flip from a NULL plane.
4766 */
4767 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4768}
4769
d3eedb1a 4770static void intel_crtc_disable_planes(struct drm_crtc *crtc)
a5c4d7bc
VS		 4771{
4772 struct drm_device *dev = crtc->dev;
4773 struct drm_i915_private *dev_priv = dev->dev_private;
4774 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
27321ae8 4775 struct intel_plane *intel_plane;
a5c4d7bc 4776 int pipe = intel_crtc->pipe;
a5c4d7bc
VS		 4777
4778 intel_crtc_wait_for_pending_flips(crtc);
a5c4d7bc 4779
e35fef21 4780 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4781 intel_fbc_disable(dev);
a5c4d7bc
VS		 4782
4783 hsw_disable_ips(intel_crtc);
4784
d3eedb1a 4785 intel_crtc_dpms_overlay(intel_crtc, false);
27321ae8
ML		 4786 intel_crtc->primary_enabled = false;
4787 for_each_intel_plane(dev, intel_plane) {
4788 if (intel_plane->pipe == pipe) {
4789 struct drm_crtc *from = intel_plane->base.crtc;
4790
4791 intel_plane->disable_plane(&intel_plane->base,
4792 from ?: crtc, true);
4793 }
4794 }
f98551ae 4795
f99d7069
DV		 4796 /*
4797 * FIXME: Once we grow proper nuclear flip support out of this we need
4798 * to compute the mask of flip planes precisely. For the time being
4799 * consider this a flip to a NULL plane.
4800 */
4801 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4802}
4803
f67a559d
JB		 4804static void ironlake_crtc_enable(struct drm_crtc *crtc)
4805{
4806 struct drm_device *dev = crtc->dev;
4807 struct drm_i915_private *dev_priv = dev->dev_private;
4808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4809 struct intel_encoder *encoder;
f67a559d 4810 int pipe = intel_crtc->pipe;
f67a559d 4811
83d65738 4812 WARN_ON(!crtc->state->enable);
08a48469 4813
f67a559d
JB		 4814 if (intel_crtc->active)
4815 return;
4816
6e3c9717 4817 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4818 intel_prepare_shared_dpll(intel_crtc);
4819
6e3c9717 4820 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4821 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4822
4823 intel_set_pipe_timings(intel_crtc);
4824
6e3c9717 4825 if (intel_crtc->config->has_pch_encoder) {
29407aab 4826 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4827 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4828 }
4829
4830 ironlake_set_pipeconf(crtc);
4831
f67a559d 4832 intel_crtc->active = true;
8664281b 4833
a72e4c9f
DV		 4834 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4835 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4836
f6736a1a 4837 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4838 if (encoder->pre_enable)
4839 encoder->pre_enable(encoder);
f67a559d 4840
6e3c9717 4841 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4842 /* Note: FDI PLL enabling _must_ be done before we enable the
4843 * cpu pipes, hence this is separate from all the other fdi/pch
4844 * enabling. */
88cefb6c 4845 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4846 } else {
4847 assert_fdi_tx_disabled(dev_priv, pipe);
4848 assert_fdi_rx_disabled(dev_priv, pipe);
4849 }
f67a559d 4850
b074cec8 4851 ironlake_pfit_enable(intel_crtc);
f67a559d 4852
9c54c0dd
JB		 4853 /*
4854 * On ILK+ LUT must be loaded before the pipe is running but with
4855 * clocks enabled
4856 */
4857 intel_crtc_load_lut(crtc);
4858
f37fcc2a 4859 intel_update_watermarks(crtc);
e1fdc473 4860 intel_enable_pipe(intel_crtc);
f67a559d 4861
6e3c9717 4862 if (intel_crtc->config->has_pch_encoder)
f67a559d 4863 ironlake_pch_enable(crtc);
c98e9dcf 4864
f9b61ff6
DV		 4865 assert_vblank_disabled(crtc);
4866 drm_crtc_vblank_on(crtc);
4867
fa5c73b1
DV		 4868 for_each_encoder_on_crtc(dev, crtc, encoder)
4869 encoder->enable(encoder);
61b77ddd
DV		 4870
4871 if (HAS_PCH_CPT(dev))
a1520318 4872 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100 4873
d3eedb1a 4874 intel_crtc_enable_planes(crtc);
6be4a607
JB		 4875}
4876
42db64ef
PZ		 4877/* IPS only exists on ULT machines and is tied to pipe A. */
4878static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4879{
f5adf94e 4880 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4881}
4882
e4916946
PZ		 4883/*
4884 * This implements the workaround described in the "notes" section of the mode
4885 * set sequence documentation. When going from no pipes or single pipe to
4886 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4887 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4888 */
4889static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4890{
4891 struct drm_device *dev = crtc->base.dev;
4892 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4893
4894 /* We want to get the other_active_crtc only if there's only 1 other
4895 * active crtc. */
d3fcc808 4896 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4897 if (!crtc_it->active || crtc_it == crtc)
4898 continue;
4899
4900 if (other_active_crtc)
4901 return;
4902
4903 other_active_crtc = crtc_it;
4904 }
4905 if (!other_active_crtc)
4906 return;
4907
4908 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4909 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4910}
4911
4f771f10
PZ		 4912static void haswell_crtc_enable(struct drm_crtc *crtc)
4913{
4914 struct drm_device *dev = crtc->dev;
4915 struct drm_i915_private *dev_priv = dev->dev_private;
4916 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4917 struct intel_encoder *encoder;
4918 int pipe = intel_crtc->pipe;
4f771f10 4919
83d65738 4920 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 4921
4922 if (intel_crtc->active)
4923 return;
4924
df8ad70c
DV		 4925 if (intel_crtc_to_shared_dpll(intel_crtc))
4926 intel_enable_shared_dpll(intel_crtc);
4927
6e3c9717 4928 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4929 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4930
4931 intel_set_pipe_timings(intel_crtc);
4932
6e3c9717
ACO		 4933 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4934 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4935 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4936 }
4937
6e3c9717 4938 if (intel_crtc->config->has_pch_encoder) {
229fca97 4939 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4940 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4941 }
4942
4943 haswell_set_pipeconf(crtc);
4944
4945 intel_set_pipe_csc(crtc);
4946
4f771f10 4947 intel_crtc->active = true;
8664281b 4948
a72e4c9f 4949 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4950 for_each_encoder_on_crtc(dev, crtc, encoder)
4951 if (encoder->pre_enable)
4952 encoder->pre_enable(encoder);
4953
6e3c9717 4954 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4955 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4956 true);
4fe9467d
ID		 4957 dev_priv->display.fdi_link_train(crtc);
4958 }
4959
1f544388 4960 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4961
ff6d9f55 4962 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 4963 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 4964 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 4965 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 4966 else
4967 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 4968
4969 /*
4970 * On ILK+ LUT must be loaded before the pipe is running but with
4971 * clocks enabled
4972 */
4973 intel_crtc_load_lut(crtc);
4974
1f544388 4975 intel_ddi_set_pipe_settings(crtc);
8228c251 4976 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4977
f37fcc2a 4978 intel_update_watermarks(crtc);
e1fdc473 4979 intel_enable_pipe(intel_crtc);
42db64ef 4980
6e3c9717 4981 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4982 lpt_pch_enable(crtc);
4f771f10 4983
6e3c9717 4984 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4985 intel_ddi_set_vc_payload_alloc(crtc, true);
4986
f9b61ff6
DV		 4987 assert_vblank_disabled(crtc);
4988 drm_crtc_vblank_on(crtc);
4989
8807e55b 4990 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4991 encoder->enable(encoder);
8807e55b
JN		 4992 intel_opregion_notify_encoder(encoder, true);
4993 }
4f771f10 4994
e4916946
PZ		 4995 /* If we change the relative order between pipe/planes enabling, we need
4996 * to change the workaround. */
4997 haswell_mode_set_planes_workaround(intel_crtc);
d3eedb1a 4998 intel_crtc_enable_planes(crtc);
4f771f10
PZ		 4999}
5000
3f8dce3a
DV		 5001static void ironlake_pfit_disable(struct intel_crtc *crtc)
5002{
5003 struct drm_device *dev = crtc->base.dev;
5004 struct drm_i915_private *dev_priv = dev->dev_private;
5005 int pipe = crtc->pipe;
5006
5007 /* To avoid upsetting the power well on haswell only disable the pfit if
5008 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 5009 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5010 I915_WRITE(PF_CTL(pipe), 0);
5011 I915_WRITE(PF_WIN_POS(pipe), 0);
5012 I915_WRITE(PF_WIN_SZ(pipe), 0);
5013 }
5014}
5015
6be4a607
JB		 5016static void ironlake_crtc_disable(struct drm_crtc *crtc)
5017{
5018 struct drm_device *dev = crtc->dev;
5019 struct drm_i915_private *dev_priv = dev->dev_private;
5020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5021 struct intel_encoder *encoder;
6be4a607 5022 int pipe = intel_crtc->pipe;
5eddb70b 5023 u32 reg, temp;
b52eb4dc 5024
f7abfe8b
CW		 5025 if (!intel_crtc->active)
5026 return;
5027
d3eedb1a 5028 intel_crtc_disable_planes(crtc);
a5c4d7bc 5029
ea9d758d
DV		 5030 for_each_encoder_on_crtc(dev, crtc, encoder)
5031 encoder->disable(encoder);
5032
f9b61ff6
DV		 5033 drm_crtc_vblank_off(crtc);
5034 assert_vblank_disabled(crtc);
5035
6e3c9717 5036 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5037 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5038
575f7ab7 5039 intel_disable_pipe(intel_crtc);
32f9d658 5040
3f8dce3a 5041 ironlake_pfit_disable(intel_crtc);
2c07245f 5042
bf49ec8c
DV		 5043 for_each_encoder_on_crtc(dev, crtc, encoder)
5044 if (encoder->post_disable)
5045 encoder->post_disable(encoder);
2c07245f 5046
6e3c9717 5047 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5048 ironlake_fdi_disable(crtc);
913d8d11 5049
d925c59a 5050 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5051
d925c59a
DV		 5052 if (HAS_PCH_CPT(dev)) {
5053 /* disable TRANS_DP_CTL */
5054 reg = TRANS_DP_CTL(pipe);
5055 temp = I915_READ(reg);
5056 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5057 TRANS_DP_PORT_SEL_MASK);
5058 temp |= TRANS_DP_PORT_SEL_NONE;
5059 I915_WRITE(reg, temp);
5060
5061 /* disable DPLL_SEL */
5062 temp = I915_READ(PCH_DPLL_SEL);
11887397 5063 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5064 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5065 }
e3421a18 5066
d925c59a 5067 /* disable PCH DPLL */
e72f9fbf 5068 intel_disable_shared_dpll(intel_crtc);
8db9d77b 5069
d925c59a
DV		 5070 ironlake_fdi_pll_disable(intel_crtc);
5071 }
6b383a7f 5072
f7abfe8b 5073 intel_crtc->active = false;
46ba614c 5074 intel_update_watermarks(crtc);
d1ebd816
BW		 5075
5076 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5077 intel_fbc_update(dev);
d1ebd816 5078 mutex_unlock(&dev->struct_mutex);
6be4a607 5079}
1b3c7a47 5080
4f771f10 5081static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5082{
4f771f10
PZ		 5083 struct drm_device *dev = crtc->dev;
5084 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5085 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5086 struct intel_encoder *encoder;
6e3c9717 5087 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5088
4f771f10
PZ		 5089 if (!intel_crtc->active)
5090 return;
5091
d3eedb1a 5092 intel_crtc_disable_planes(crtc);
dda9a66a 5093
8807e55b
JN		 5094 for_each_encoder_on_crtc(dev, crtc, encoder) {
5095 intel_opregion_notify_encoder(encoder, false);
4f771f10 5096 encoder->disable(encoder);
8807e55b 5097 }
4f771f10 5098
f9b61ff6
DV		 5099 drm_crtc_vblank_off(crtc);
5100 assert_vblank_disabled(crtc);
5101
6e3c9717 5102 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5103 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5104 false);
575f7ab7 5105 intel_disable_pipe(intel_crtc);
4f771f10 5106
6e3c9717 5107 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5108 intel_ddi_set_vc_payload_alloc(crtc, false);
5109
ad80a810 5110 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5111
ff6d9f55 5112 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5113 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5114 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5115 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5116 else
5117 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5118
1f544388 5119 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5120
6e3c9717 5121 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5122 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5123 intel_ddi_fdi_disable(crtc);
83616634 5124 }
4f771f10 5125
97b040aa
ID		 5126 for_each_encoder_on_crtc(dev, crtc, encoder)
5127 if (encoder->post_disable)
5128 encoder->post_disable(encoder);
5129
4f771f10 5130 intel_crtc->active = false;
46ba614c 5131 intel_update_watermarks(crtc);
4f771f10
PZ		 5132
5133 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5134 intel_fbc_update(dev);
4f771f10 5135 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 5136
5137 if (intel_crtc_to_shared_dpll(intel_crtc))
5138 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 5139}
5140
ee7b9f93
JB		 5141static void ironlake_crtc_off(struct drm_crtc *crtc)
5142{
5143 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 5144 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 5145}
5146
6441ab5f 5147
2dd24552
JB		 5148static void i9xx_pfit_enable(struct intel_crtc *crtc)
5149{
5150 struct drm_device *dev = crtc->base.dev;
5151 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5152 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5153
681a8504 5154 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5155 return;
5156
2dd24552 5157 /*
c0b03411
DV		 5158 * The panel fitter should only be adjusted whilst the pipe is disabled,
5159 * according to register description and PRM.
2dd24552 5160 */
c0b03411
DV		 5161 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5162 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5163
b074cec8
JB		 5164 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5165 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5166
5167 /* Border color in case we don't scale up to the full screen. Black by
5168 * default, change to something else for debugging. */
5169 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5170}
5171
d05410f9
DA		 5172static enum intel_display_power_domain port_to_power_domain(enum port port)
5173{
5174 switch (port) {
5175 case PORT_A:
5176 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5177 case PORT_B:
5178 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5179 case PORT_C:
5180 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5181 case PORT_D:
5182 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5183 default:
5184 WARN_ON_ONCE(1);
5185 return POWER_DOMAIN_PORT_OTHER;
5186 }
5187}
5188
77d22dca
ID		 5189#define for_each_power_domain(domain, mask) \
5190 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5191 if ((1 << (domain)) & (mask))
5192
319be8ae
ID		 5193enum intel_display_power_domain
5194intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5195{
5196 struct drm_device *dev = intel_encoder->base.dev;
5197 struct intel_digital_port *intel_dig_port;
5198
5199 switch (intel_encoder->type) {
5200 case INTEL_OUTPUT_UNKNOWN:
5201 /* Only DDI platforms should ever use this output type */
5202 WARN_ON_ONCE(!HAS_DDI(dev));
5203 case INTEL_OUTPUT_DISPLAYPORT:
5204 case INTEL_OUTPUT_HDMI:
5205 case INTEL_OUTPUT_EDP:
5206 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5207 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5208 case INTEL_OUTPUT_DP_MST:
5209 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5210 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5211 case INTEL_OUTPUT_ANALOG:
5212 return POWER_DOMAIN_PORT_CRT;
5213 case INTEL_OUTPUT_DSI:
5214 return POWER_DOMAIN_PORT_DSI;
5215 default:
5216 return POWER_DOMAIN_PORT_OTHER;
5217 }
5218}
5219
5220static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5221{
319be8ae
ID		 5222 struct drm_device *dev = crtc->dev;
5223 struct intel_encoder *intel_encoder;
5224 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5225 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5226 unsigned long mask;
5227 enum transcoder transcoder;
5228
5229 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5230
5231 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5232 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5233 if (intel_crtc->config->pch_pfit.enabled ||
5234 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5235 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5236
319be8ae
ID		 5237 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5238 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5239
77d22dca
ID		 5240 return mask;
5241}
5242
679dacd4 5243static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5244{
679dacd4 5245 struct drm_device *dev = state->dev;
77d22dca
ID		 5246 struct drm_i915_private *dev_priv = dev->dev_private;
5247 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5248 struct intel_crtc *crtc;
5249
5250 /*
5251 * First get all needed power domains, then put all unneeded, to avoid
5252 * any unnecessary toggling of the power wells.
5253 */
d3fcc808 5254 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5255 enum intel_display_power_domain domain;
5256
83d65738 5257 if (!crtc->base.state->enable)
77d22dca
ID		 5258 continue;
5259
319be8ae 5260 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5261
5262 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5263 intel_display_power_get(dev_priv, domain);
5264 }
5265
50f6e502 5266 if (dev_priv->display.modeset_global_resources)
679dacd4 5267 dev_priv->display.modeset_global_resources(state);
50f6e502 5268
d3fcc808 5269 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5270 enum intel_display_power_domain domain;
5271
5272 for_each_power_domain(domain, crtc->enabled_power_domains)
5273 intel_display_power_put(dev_priv, domain);
5274
5275 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5276 }
5277
5278 intel_display_set_init_power(dev_priv, false);
5279}
5280
f8437dd1
VK		 5281void broxton_set_cdclk(struct drm_device *dev, int frequency)
5282{
5283 struct drm_i915_private *dev_priv = dev->dev_private;
5284 uint32_t divider;
5285 uint32_t ratio;
5286 uint32_t current_freq;
5287 int ret;
5288
5289 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5290 switch (frequency) {
5291 case 144000:
5292 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5293 ratio = BXT_DE_PLL_RATIO(60);
5294 break;
5295 case 288000:
5296 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5297 ratio = BXT_DE_PLL_RATIO(60);
5298 break;
5299 case 384000:
5300 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5301 ratio = BXT_DE_PLL_RATIO(60);
5302 break;
5303 case 576000:
5304 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5305 ratio = BXT_DE_PLL_RATIO(60);
5306 break;
5307 case 624000:
5308 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5309 ratio = BXT_DE_PLL_RATIO(65);
5310 break;
5311 case 19200:
5312 /*
5313 * Bypass frequency with DE PLL disabled. Init ratio, divider
5314 * to suppress GCC warning.
5315 */
5316 ratio = 0;
5317 divider = 0;
5318 break;
5319 default:
5320 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5321
5322 return;
5323 }
5324
5325 mutex_lock(&dev_priv->rps.hw_lock);
5326 /* Inform power controller of upcoming frequency change */
5327 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5328 0x80000000);
5329 mutex_unlock(&dev_priv->rps.hw_lock);
5330
5331 if (ret) {
5332 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5333 ret, frequency);
5334 return;
5335 }
5336
5337 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5338 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5339 current_freq = current_freq * 500 + 1000;
5340
5341 /*
5342 * DE PLL has to be disabled when
5343 * - setting to 19.2MHz (bypass, PLL isn't used)
5344 * - before setting to 624MHz (PLL needs toggling)
5345 * - before setting to any frequency from 624MHz (PLL needs toggling)
5346 */
5347 if (frequency == 19200 || frequency == 624000 ||
5348 current_freq == 624000) {
5349 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5350 /* Timeout 200us */
5351 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5352 1))
5353 DRM_ERROR("timout waiting for DE PLL unlock\n");
5354 }
5355
5356 if (frequency != 19200) {
5357 uint32_t val;
5358
5359 val = I915_READ(BXT_DE_PLL_CTL);
5360 val &= ~BXT_DE_PLL_RATIO_MASK;
5361 val |= ratio;
5362 I915_WRITE(BXT_DE_PLL_CTL, val);
5363
5364 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5365 /* Timeout 200us */
5366 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5367 DRM_ERROR("timeout waiting for DE PLL lock\n");
5368
5369 val = I915_READ(CDCLK_CTL);
5370 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5371 val |= divider;
5372 /*
5373 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5374 * enable otherwise.
5375 */
5376 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5377 if (frequency >= 500000)
5378 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5379
5380 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5381 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5382 val |= (frequency - 1000) / 500;
5383 I915_WRITE(CDCLK_CTL, val);
5384 }
5385
5386 mutex_lock(&dev_priv->rps.hw_lock);
5387 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5388 DIV_ROUND_UP(frequency, 25000));
5389 mutex_unlock(&dev_priv->rps.hw_lock);
5390
5391 if (ret) {
5392 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5393 ret, frequency);
5394 return;
5395 }
5396
5397 dev_priv->cdclk_freq = frequency;
5398}
5399
5400void broxton_init_cdclk(struct drm_device *dev)
5401{
5402 struct drm_i915_private *dev_priv = dev->dev_private;
5403 uint32_t val;
5404
5405 /*
5406 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5407 * or else the reset will hang because there is no PCH to respond.
5408 * Move the handshake programming to initialization sequence.
5409 * Previously was left up to BIOS.
5410 */
5411 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5412 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5413 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5414
5415 /* Enable PG1 for cdclk */
5416 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5417
5418 /* check if cd clock is enabled */
5419 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5420 DRM_DEBUG_KMS("Display already initialized\n");
5421 return;
5422 }
5423
5424 /*
5425 * FIXME:
5426 * - The initial CDCLK needs to be read from VBT.
5427 * Need to make this change after VBT has changes for BXT.
5428 * - check if setting the max (or any) cdclk freq is really necessary
5429 * here, it belongs to modeset time
5430 */
5431 broxton_set_cdclk(dev, 624000);
5432
5433 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5434 POSTING_READ(DBUF_CTL);
5435
f8437dd1
VK		 5436 udelay(10);
5437
5438 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5439 DRM_ERROR("DBuf power enable timeout!\n");
5440}
5441
5442void broxton_uninit_cdclk(struct drm_device *dev)
5443{
5444 struct drm_i915_private *dev_priv = dev->dev_private;
5445
5446 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5447 POSTING_READ(DBUF_CTL);
5448
f8437dd1
VK		 5449 udelay(10);
5450
5451 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5452 DRM_ERROR("DBuf power disable timeout!\n");
5453
5454 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5455 broxton_set_cdclk(dev, 19200);
5456
5457 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5458}
5459
dfcab17e 5460/* returns HPLL frequency in kHz */
f8bf63fd 5461static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5462{
586f49dc 5463 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5464
586f49dc
JB		 5465 /* Obtain SKU information */
5466 mutex_lock(&dev_priv->dpio_lock);
5467 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5468 CCK_FUSE_HPLL_FREQ_MASK;
5469 mutex_unlock(&dev_priv->dpio_lock);
30a970c6 5470
dfcab17e 5471 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5472}
5473
f8bf63fd
VS		 5474static void vlv_update_cdclk(struct drm_device *dev)
5475{
5476 struct drm_i915_private *dev_priv = dev->dev_private;
5477
164dfd28 5478 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
43dc52c3 5479 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
164dfd28 5480 dev_priv->cdclk_freq);
f8bf63fd
VS		 5481
5482 /*
5483 * Program the gmbus_freq based on the cdclk frequency.
5484 * BSpec erroneously claims we should aim for 4MHz, but
5485 * in fact 1MHz is the correct frequency.
5486 */
164dfd28 5487 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
f8bf63fd
VS		 5488}
5489
30a970c6
JB		 5490/* Adjust CDclk dividers to allow high res or save power if possible */
5491static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5492{
5493 struct drm_i915_private *dev_priv = dev->dev_private;
5494 u32 val, cmd;
5495
164dfd28
VK		 5496 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5497 != dev_priv->cdclk_freq);
d60c4473 5498
dfcab17e 5499 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5500 cmd = 2;
dfcab17e 5501 else if (cdclk == 266667)
30a970c6
JB		 5502 cmd = 1;
5503 else
5504 cmd = 0;
5505
5506 mutex_lock(&dev_priv->rps.hw_lock);
5507 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5508 val &= ~DSPFREQGUAR_MASK;
5509 val |= (cmd << DSPFREQGUAR_SHIFT);
5510 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5511 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5512 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5513 50)) {
5514 DRM_ERROR("timed out waiting for CDclk change\n");
5515 }
5516 mutex_unlock(&dev_priv->rps.hw_lock);
5517
dfcab17e 5518 if (cdclk == 400000) {
6bcda4f0 5519 u32 divider;
30a970c6 5520
6bcda4f0 5521 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6
JB		 5522
5523 mutex_lock(&dev_priv->dpio_lock);
5524 /* adjust cdclk divider */
5525 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5526 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5527 val |= divider;
5528 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5529
5530 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5531 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5532 50))
5533 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5534 mutex_unlock(&dev_priv->dpio_lock);
5535 }
5536
5537 mutex_lock(&dev_priv->dpio_lock);
5538 /* adjust self-refresh exit latency value */
5539 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5540 val &= ~0x7f;
5541
5542 /*
5543 * For high bandwidth configs, we set a higher latency in the bunit
5544 * so that the core display fetch happens in time to avoid underruns.
5545 */
dfcab17e 5546 if (cdclk == 400000)
30a970c6
JB		 5547 val |= 4500 / 250; /* 4.5 usec */
5548 else
5549 val |= 3000 / 250; /* 3.0 usec */
5550 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5551 mutex_unlock(&dev_priv->dpio_lock);
5552
f8bf63fd 5553 vlv_update_cdclk(dev);
30a970c6
JB		 5554}
5555
383c5a6a
VS		 5556static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5557{
5558 struct drm_i915_private *dev_priv = dev->dev_private;
5559 u32 val, cmd;
5560
164dfd28
VK		 5561 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5562 != dev_priv->cdclk_freq);
383c5a6a
VS		 5563
5564 switch (cdclk) {
383c5a6a
VS		 5565 case 333333:
5566 case 320000:
383c5a6a 5567 case 266667:
383c5a6a 5568 case 200000:
383c5a6a
VS		 5569 break;
5570 default:
5f77eeb0 5571 MISSING_CASE(cdclk);
383c5a6a
VS		 5572 return;
5573 }
5574
9d0d3fda
VS		 5575 /*
5576 * Specs are full of misinformation, but testing on actual
5577 * hardware has shown that we just need to write the desired
5578 * CCK divider into the Punit register.
5579 */
5580 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5581
383c5a6a
VS		 5582 mutex_lock(&dev_priv->rps.hw_lock);
5583 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5584 val &= ~DSPFREQGUAR_MASK_CHV;
5585 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5586 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5587 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5588 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5589 50)) {
5590 DRM_ERROR("timed out waiting for CDclk change\n");
5591 }
5592 mutex_unlock(&dev_priv->rps.hw_lock);
5593
5594 vlv_update_cdclk(dev);
5595}
5596
30a970c6
JB		 5597static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5598 int max_pixclk)
5599{
6bcda4f0 5600 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5601 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5602
30a970c6
JB		 5603 /*
5604 * Really only a few cases to deal with, as only 4 CDclks are supported:
5605 * 200MHz
5606 * 267MHz
29dc7ef3 5607 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5608 * 400MHz (VLV only)
5609 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5610 * of the lower bin and adjust if needed.
e37c67a1
VS		 5611 *
5612 * We seem to get an unstable or solid color picture at 200MHz.
5613 * Not sure what's wrong. For now use 200MHz only when all pipes
5614 * are off.
30a970c6 5615 */
6cca3195
VS		 5616 if (!IS_CHERRYVIEW(dev_priv) &&
5617 max_pixclk > freq_320*limit/100)
dfcab17e 5618 return 400000;
6cca3195 5619 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5620 return freq_320;
e37c67a1 5621 else if (max_pixclk > 0)
dfcab17e 5622 return 266667;
e37c67a1
VS		 5623 else
5624 return 200000;
30a970c6
JB		 5625}
5626
f8437dd1
VK		 5627static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5628 int max_pixclk)
5629{
5630 /*
5631 * FIXME:
5632 * - remove the guardband, it's not needed on BXT
5633 * - set 19.2MHz bypass frequency if there are no active pipes
5634 */
5635 if (max_pixclk > 576000*9/10)
5636 return 624000;
5637 else if (max_pixclk > 384000*9/10)
5638 return 576000;
5639 else if (max_pixclk > 288000*9/10)
5640 return 384000;
5641 else if (max_pixclk > 144000*9/10)
5642 return 288000;
5643 else
5644 return 144000;
5645}
5646
2f2d7aa1 5647/* compute the max pixel clock for new configuration */
304603f4 5648static int intel_mode_max_pixclk(struct drm_atomic_state *state)
30a970c6 5649{
304603f4 5650 struct drm_device *dev = state->dev;
30a970c6 5651 struct intel_crtc *intel_crtc;
304603f4 5652 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5653 int max_pixclk = 0;
5654
d3fcc808 5655 for_each_intel_crtc(dev, intel_crtc) {
304603f4
ACO		 5656 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
5657 if (IS_ERR(crtc_state))
5658 return PTR_ERR(crtc_state);
5659
5660 if (!crtc_state->base.enable)
5661 continue;
5662
5663 max_pixclk = max(max_pixclk,
5664 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5665 }
5666
5667 return max_pixclk;
5668}
5669
304603f4 5670static int valleyview_modeset_global_pipes(struct drm_atomic_state *state,
2f2d7aa1 5671 unsigned *prepare_pipes)
30a970c6 5672{
304603f4 5673 struct drm_i915_private *dev_priv = to_i915(state->dev);
30a970c6 5674 struct intel_crtc *intel_crtc;
304603f4 5675 int max_pixclk = intel_mode_max_pixclk(state);
f8437dd1 5676 int cdclk;
30a970c6 5677
304603f4
ACO		 5678 if (max_pixclk < 0)
5679 return max_pixclk;
30a970c6 5680
f8437dd1
VK		 5681 if (IS_VALLEYVIEW(dev_priv))
5682 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5683 else
5684 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5685
5686 if (cdclk == dev_priv->cdclk_freq)
304603f4 5687 return 0;
30a970c6 5688
2f2d7aa1 5689 /* disable/enable all currently active pipes while we change cdclk */
304603f4 5690 for_each_intel_crtc(state->dev, intel_crtc)
83d65738 5691 if (intel_crtc->base.state->enable)
30a970c6 5692 *prepare_pipes |= (1 << intel_crtc->pipe);
304603f4
ACO		 5693
5694 return 0;
30a970c6
JB		 5695}
5696
1e69cd74
VS		 5697static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5698{
5699 unsigned int credits, default_credits;
5700
5701 if (IS_CHERRYVIEW(dev_priv))
5702 default_credits = PFI_CREDIT(12);
5703 else
5704 default_credits = PFI_CREDIT(8);
5705
164dfd28 5706 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5707 /* CHV suggested value is 31 or 63 */
5708 if (IS_CHERRYVIEW(dev_priv))
5709 credits = PFI_CREDIT_31;
5710 else
5711 credits = PFI_CREDIT(15);
5712 } else {
5713 credits = default_credits;
5714 }
5715
5716 /*
5717 * WA - write default credits before re-programming
5718 * FIXME: should we also set the resend bit here?
5719 */
5720 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5721 default_credits);
5722
5723 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5724 credits | PFI_CREDIT_RESEND);
5725
5726 /*
5727 * FIXME is this guaranteed to clear
5728 * immediately or should we poll for it?
5729 */
5730 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5731}
5732
679dacd4 5733static void valleyview_modeset_global_resources(struct drm_atomic_state *state)
30a970c6 5734{
679dacd4 5735 struct drm_device *dev = state->dev;
30a970c6 5736 struct drm_i915_private *dev_priv = dev->dev_private;
304603f4
ACO		 5737 int max_pixclk = intel_mode_max_pixclk(state);
5738 int req_cdclk;
5739
5740 /* The only reason this can fail is if we fail to add the crtc_state
5741 * to the atomic state. But that can't happen since the call to
5742 * intel_mode_max_pixclk() in valleyview_modeset_global_pipes() (which
5743 * can't have failed otherwise the mode set would be aborted) added all
5744 * the states already. */
5745 if (WARN_ON(max_pixclk < 0))
5746 return;
30a970c6 5747
304603f4 5748 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
30a970c6 5749
164dfd28 5750 if (req_cdclk != dev_priv->cdclk_freq) {
738c05c0
ID		 5751 /*
5752 * FIXME: We can end up here with all power domains off, yet
5753 * with a CDCLK frequency other than the minimum. To account
5754 * for this take the PIPE-A power domain, which covers the HW
5755 * blocks needed for the following programming. This can be
5756 * removed once it's guaranteed that we get here either with
5757 * the minimum CDCLK set, or the required power domains
5758 * enabled.
5759 */
5760 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5761
383c5a6a
VS		 5762 if (IS_CHERRYVIEW(dev))
5763 cherryview_set_cdclk(dev, req_cdclk);
5764 else
5765 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5766
1e69cd74
VS		 5767 vlv_program_pfi_credits(dev_priv);
5768
738c05c0 5769 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 5770 }
30a970c6
JB		 5771}
5772
89b667f8
JB		 5773static void valleyview_crtc_enable(struct drm_crtc *crtc)
5774{
5775 struct drm_device *dev = crtc->dev;
a72e4c9f 5776 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 5777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5778 struct intel_encoder *encoder;
5779 int pipe = intel_crtc->pipe;
23538ef1 5780 bool is_dsi;
89b667f8 5781
83d65738 5782 WARN_ON(!crtc->state->enable);
89b667f8
JB		 5783
5784 if (intel_crtc->active)
5785 return;
5786
409ee761 5787 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 5788
1ae0d137
VS		 5789 if (!is_dsi) {
5790 if (IS_CHERRYVIEW(dev))
6e3c9717 5791 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5792 else
6e3c9717 5793 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5794 }
5b18e57c 5795
6e3c9717 5796 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5797 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5798
5799 intel_set_pipe_timings(intel_crtc);
5800
c14b0485
VS		 5801 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5802 struct drm_i915_private *dev_priv = dev->dev_private;
5803
5804 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5805 I915_WRITE(CHV_CANVAS(pipe), 0);
5806 }
5807
5b18e57c
DV		 5808 i9xx_set_pipeconf(intel_crtc);
5809
89b667f8 5810 intel_crtc->active = true;
89b667f8 5811
a72e4c9f 5812 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5813
89b667f8
JB		 5814 for_each_encoder_on_crtc(dev, crtc, encoder)
5815 if (encoder->pre_pll_enable)
5816 encoder->pre_pll_enable(encoder);
5817
9d556c99
CML		 5818 if (!is_dsi) {
5819 if (IS_CHERRYVIEW(dev))
6e3c9717 5820 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5821 else
6e3c9717 5822 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5823 }
89b667f8
JB		 5824
5825 for_each_encoder_on_crtc(dev, crtc, encoder)
5826 if (encoder->pre_enable)
5827 encoder->pre_enable(encoder);
5828
2dd24552
JB		 5829 i9xx_pfit_enable(intel_crtc);
5830
63cbb074
VS		 5831 intel_crtc_load_lut(crtc);
5832
f37fcc2a 5833 intel_update_watermarks(crtc);
e1fdc473 5834 intel_enable_pipe(intel_crtc);
be6a6f8e 5835
4b3a9526
VS		 5836 assert_vblank_disabled(crtc);
5837 drm_crtc_vblank_on(crtc);
5838
f9b61ff6
DV		 5839 for_each_encoder_on_crtc(dev, crtc, encoder)
5840 encoder->enable(encoder);
5841
9ab0460b 5842 intel_crtc_enable_planes(crtc);
d40d9187 5843
56b80e1f 5844 /* Underruns don't raise interrupts, so check manually. */
a72e4c9f 5845 i9xx_check_fifo_underruns(dev_priv);
89b667f8
JB		 5846}
5847
f13c2ef3
DV		 5848static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5849{
5850 struct drm_device *dev = crtc->base.dev;
5851 struct drm_i915_private *dev_priv = dev->dev_private;
5852
6e3c9717
ACO		 5853 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5854 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 5855}
5856
0b8765c6 5857static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 5858{
5859 struct drm_device *dev = crtc->dev;
a72e4c9f 5860 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 5861 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5862 struct intel_encoder *encoder;
79e53945 5863 int pipe = intel_crtc->pipe;
79e53945 5864
83d65738 5865 WARN_ON(!crtc->state->enable);
08a48469 5866
f7abfe8b
CW		 5867 if (intel_crtc->active)
5868 return;
5869
f13c2ef3
DV		 5870 i9xx_set_pll_dividers(intel_crtc);
5871
6e3c9717 5872 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5873 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5874
5875 intel_set_pipe_timings(intel_crtc);
5876
5b18e57c
DV		 5877 i9xx_set_pipeconf(intel_crtc);
5878
f7abfe8b 5879 intel_crtc->active = true;
6b383a7f 5880
4a3436e8 5881 if (!IS_GEN2(dev))
a72e4c9f 5882 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5883
9d6d9f19
MK		 5884 for_each_encoder_on_crtc(dev, crtc, encoder)
5885 if (encoder->pre_enable)
5886 encoder->pre_enable(encoder);
5887
f6736a1a
DV		 5888 i9xx_enable_pll(intel_crtc);
5889
2dd24552
JB		 5890 i9xx_pfit_enable(intel_crtc);
5891
63cbb074
VS		 5892 intel_crtc_load_lut(crtc);
5893
f37fcc2a 5894 intel_update_watermarks(crtc);
e1fdc473 5895 intel_enable_pipe(intel_crtc);
be6a6f8e 5896
4b3a9526
VS		 5897 assert_vblank_disabled(crtc);
5898 drm_crtc_vblank_on(crtc);
5899
f9b61ff6
DV		 5900 for_each_encoder_on_crtc(dev, crtc, encoder)
5901 encoder->enable(encoder);
5902
9ab0460b 5903 intel_crtc_enable_planes(crtc);
d40d9187 5904
4a3436e8
VS		 5905 /*
5906 * Gen2 reports pipe underruns whenever all planes are disabled.
5907 * So don't enable underrun reporting before at least some planes
5908 * are enabled.
5909 * FIXME: Need to fix the logic to work when we turn off all planes
5910 * but leave the pipe running.
5911 */
5912 if (IS_GEN2(dev))
a72e4c9f 5913 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5914
56b80e1f 5915 /* Underruns don't raise interrupts, so check manually. */
a72e4c9f 5916 i9xx_check_fifo_underruns(dev_priv);
0b8765c6 5917}
79e53945 5918
87476d63
DV		 5919static void i9xx_pfit_disable(struct intel_crtc *crtc)
5920{
5921 struct drm_device *dev = crtc->base.dev;
5922 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 5923
6e3c9717 5924 if (!crtc->config->gmch_pfit.control)
328d8e82 5925 return;
87476d63 5926
328d8e82 5927 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 5928
328d8e82
DV		 5929 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5930 I915_READ(PFIT_CONTROL));
5931 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 5932}
5933
0b8765c6
JB		 5934static void i9xx_crtc_disable(struct drm_crtc *crtc)
5935{
5936 struct drm_device *dev = crtc->dev;
5937 struct drm_i915_private *dev_priv = dev->dev_private;
5938 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5939 struct intel_encoder *encoder;
0b8765c6 5940 int pipe = intel_crtc->pipe;
ef9c3aee 5941
f7abfe8b
CW		 5942 if (!intel_crtc->active)
5943 return;
5944
4a3436e8
VS		 5945 /*
5946 * Gen2 reports pipe underruns whenever all planes are disabled.
5947 * So diasble underrun reporting before all the planes get disabled.
5948 * FIXME: Need to fix the logic to work when we turn off all planes
5949 * but leave the pipe running.
5950 */
5951 if (IS_GEN2(dev))
a72e4c9f 5952 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 5953
564ed191
ID		 5954 /*
5955 * Vblank time updates from the shadow to live plane control register
5956 * are blocked if the memory self-refresh mode is active at that
5957 * moment. So to make sure the plane gets truly disabled, disable
5958 * first the self-refresh mode. The self-refresh enable bit in turn
5959 * will be checked/applied by the HW only at the next frame start
5960 * event which is after the vblank start event, so we need to have a
5961 * wait-for-vblank between disabling the plane and the pipe.
5962 */
5963 intel_set_memory_cxsr(dev_priv, false);
9ab0460b
VS		 5964 intel_crtc_disable_planes(crtc);
5965
6304cd91
VS		 5966 /*
5967 * On gen2 planes are double buffered but the pipe isn't, so we must
5968 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 5969 * We also need to wait on all gmch platforms because of the
5970 * self-refresh mode constraint explained above.
6304cd91 5971 */
564ed191 5972 intel_wait_for_vblank(dev, pipe);
6304cd91 5973
4b3a9526
VS		 5974 for_each_encoder_on_crtc(dev, crtc, encoder)
5975 encoder->disable(encoder);
5976
f9b61ff6
DV		 5977 drm_crtc_vblank_off(crtc);
5978 assert_vblank_disabled(crtc);
5979
575f7ab7 5980 intel_disable_pipe(intel_crtc);
24a1f16d 5981
87476d63 5982 i9xx_pfit_disable(intel_crtc);
24a1f16d 5983
89b667f8
JB		 5984 for_each_encoder_on_crtc(dev, crtc, encoder)
5985 if (encoder->post_disable)
5986 encoder->post_disable(encoder);
5987
409ee761 5988 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 5989 if (IS_CHERRYVIEW(dev))
5990 chv_disable_pll(dev_priv, pipe);
5991 else if (IS_VALLEYVIEW(dev))
5992 vlv_disable_pll(dev_priv, pipe);
5993 else
1c4e0274 5994 i9xx_disable_pll(intel_crtc);
076ed3b2 5995 }
0b8765c6 5996
4a3436e8 5997 if (!IS_GEN2(dev))
a72e4c9f 5998 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 5999
f7abfe8b 6000 intel_crtc->active = false;
46ba614c 6001 intel_update_watermarks(crtc);
f37fcc2a 6002
efa9624e 6003 mutex_lock(&dev->struct_mutex);
7ff0ebcc 6004 intel_fbc_update(dev);
efa9624e 6005 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 6006}
6007
ee7b9f93
JB		 6008static void i9xx_crtc_off(struct drm_crtc *crtc)
6009{
6010}
6011
b04c5bd6
BF		 6012/* Master function to enable/disable CRTC and corresponding power wells */
6013void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 6014{
6015 struct drm_device *dev = crtc->dev;
6016 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 6017 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 6018 enum intel_display_power_domain domain;
6019 unsigned long domains;
976f8a20 6020
0e572fe7
DV		 6021 if (enable) {
6022 if (!intel_crtc->active) {
e1e9fb84
DV		 6023 domains = get_crtc_power_domains(crtc);
6024 for_each_power_domain(domain, domains)
6025 intel_display_power_get(dev_priv, domain);
6026 intel_crtc->enabled_power_domains = domains;
0e572fe7
DV		 6027
6028 dev_priv->display.crtc_enable(crtc);
6029 }
6030 } else {
6031 if (intel_crtc->active) {
6032 dev_priv->display.crtc_disable(crtc);
6033
e1e9fb84
DV		 6034 domains = intel_crtc->enabled_power_domains;
6035 for_each_power_domain(domain, domains)
6036 intel_display_power_put(dev_priv, domain);
6037 intel_crtc->enabled_power_domains = 0;
0e572fe7
DV		 6038 }
6039 }
b04c5bd6
BF		 6040}
6041
6042/**
6043 * Sets the power management mode of the pipe and plane.
6044 */
6045void intel_crtc_update_dpms(struct drm_crtc *crtc)
6046{
6047 struct drm_device *dev = crtc->dev;
6048 struct intel_encoder *intel_encoder;
6049 bool enable = false;
6050
6051 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6052 enable |= intel_encoder->connectors_active;
6053
6054 intel_crtc_control(crtc, enable);
976f8a20
DV		 6055}
6056
cdd59983
CW		 6057static void intel_crtc_disable(struct drm_crtc *crtc)
6058{
cdd59983 6059 struct drm_device *dev = crtc->dev;
976f8a20 6060 struct drm_connector *connector;
ee7b9f93 6061 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 6062
976f8a20 6063 /* crtc should still be enabled when we disable it. */
83d65738 6064 WARN_ON(!crtc->state->enable);
976f8a20
DV		 6065
6066 dev_priv->display.crtc_disable(crtc);
ee7b9f93
JB		 6067 dev_priv->display.off(crtc);
6068
70a101f8 6069 drm_plane_helper_disable(crtc->primary);
976f8a20
DV		 6070
6071 /* Update computed state. */
6072 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6073 if (!connector->encoder || !connector->encoder->crtc)
6074 continue;
6075
6076 if (connector->encoder->crtc != crtc)
6077 continue;
6078
6079 connector->dpms = DRM_MODE_DPMS_OFF;
6080 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 6081 }
6082}
6083
ea5b213a 6084void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6085{
4ef69c7a 6086 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6087
ea5b213a
CW		 6088 drm_encoder_cleanup(encoder);
6089 kfree(intel_encoder);
7e7d76c3
JB		 6090}
6091
9237329d 6092/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6093 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6094 * state of the entire output pipe. */
9237329d 6095static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6096{
5ab432ef
DV		 6097 if (mode == DRM_MODE_DPMS_ON) {
6098 encoder->connectors_active = true;
6099
b2cabb0e 6100 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6101 } else {
6102 encoder->connectors_active = false;
6103
b2cabb0e 6104 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6105 }
79e53945
JB		 6106}
6107
0a91ca29
DV		 6108/* Cross check the actual hw state with our own modeset state tracking (and it's
6109 * internal consistency). */
b980514c 6110static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6111{
0a91ca29
DV		 6112 if (connector->get_hw_state(connector)) {
6113 struct intel_encoder *encoder = connector->encoder;
6114 struct drm_crtc *crtc;
6115 bool encoder_enabled;
6116 enum pipe pipe;
6117
6118 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6119 connector->base.base.id,
c23cc417 6120 connector->base.name);
0a91ca29 6121
0e32b39c
DA		 6122 /* there is no real hw state for MST connectors */
6123 if (connector->mst_port)
6124 return;
6125
e2c719b7 6126 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6127 "wrong connector dpms state\n");
e2c719b7 6128 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6129 "active connector not linked to encoder\n");
0a91ca29 6130
36cd7444 6131 if (encoder) {
e2c719b7 6132 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6133 "encoder->connectors_active not set\n");
6134
6135 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6136 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6137 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6138 return;
0a91ca29 6139
36cd7444 6140 crtc = encoder->base.crtc;
0a91ca29 6141
83d65738
MR		 6142 I915_STATE_WARN(!crtc->state->enable,
6143 "crtc not enabled\n");
e2c719b7
RC		 6144 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6145 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6146 "encoder active on the wrong pipe\n");
6147 }
0a91ca29 6148 }
79e53945
JB		 6149}
6150
08d9bc92
ACO		 6151int intel_connector_init(struct intel_connector *connector)
6152{
6153 struct drm_connector_state *connector_state;
6154
6155 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6156 if (!connector_state)
6157 return -ENOMEM;
6158
6159 connector->base.state = connector_state;
6160 return 0;
6161}
6162
6163struct intel_connector *intel_connector_alloc(void)
6164{
6165 struct intel_connector *connector;
6166
6167 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6168 if (!connector)
6169 return NULL;
6170
6171 if (intel_connector_init(connector) < 0) {
6172 kfree(connector);
6173 return NULL;
6174 }
6175
6176 return connector;
6177}
6178
5ab432ef
DV		 6179/* Even simpler default implementation, if there's really no special case to
6180 * consider. */
6181void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6182{
5ab432ef
DV		 6183 /* All the simple cases only support two dpms states. */
6184 if (mode != DRM_MODE_DPMS_ON)
6185 mode = DRM_MODE_DPMS_OFF;
d4270e57 6186
5ab432ef
DV		 6187 if (mode == connector->dpms)
6188 return;
6189
6190 connector->dpms = mode;
6191
6192 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6193 if (connector->encoder)
6194 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6195
b980514c 6196 intel_modeset_check_state(connector->dev);
79e53945
JB		 6197}
6198
f0947c37
DV		 6199/* Simple connector->get_hw_state implementation for encoders that support only
6200 * one connector and no cloning and hence the encoder state determines the state
6201 * of the connector. */
6202bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6203{
24929352 6204 enum pipe pipe = 0;
f0947c37 6205 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6206
f0947c37 6207 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6208}
6209
6d293983 6210static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6211{
6d293983
ACO		 6212 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6213 return crtc_state->fdi_lanes;
d272ddfa
VS		 6214
6215 return 0;
6216}
6217
6d293983 6218static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6219 struct intel_crtc_state *pipe_config)
1857e1da 6220{
6d293983
ACO		 6221 struct drm_atomic_state *state = pipe_config->base.state;
6222 struct intel_crtc *other_crtc;
6223 struct intel_crtc_state *other_crtc_state;
6224
1857e1da
DV		 6225 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6226 pipe_name(pipe), pipe_config->fdi_lanes);
6227 if (pipe_config->fdi_lanes > 4) {
6228 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6229 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6230 return -EINVAL;
1857e1da
DV		 6231 }
6232
bafb6553 6233 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6234 if (pipe_config->fdi_lanes > 2) {
6235 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6236 pipe_config->fdi_lanes);
6d293983 6237 return -EINVAL;
1857e1da 6238 } else {
6d293983 6239 return 0;
1857e1da
DV		 6240 }
6241 }
6242
6243 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6244 return 0;
1857e1da
DV		 6245
6246 /* Ivybridge 3 pipe is really complicated */
6247 switch (pipe) {
6248 case PIPE_A:
6d293983 6249 return 0;
1857e1da 6250 case PIPE_B:
6d293983
ACO		 6251 if (pipe_config->fdi_lanes <= 2)
6252 return 0;
6253
6254 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6255 other_crtc_state =
6256 intel_atomic_get_crtc_state(state, other_crtc);
6257 if (IS_ERR(other_crtc_state))
6258 return PTR_ERR(other_crtc_state);
6259
6260 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6261 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6262 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6263 return -EINVAL;
1857e1da 6264 }
6d293983 6265 return 0;
1857e1da 6266 case PIPE_C:
251cc67c
VS		 6267 if (pipe_config->fdi_lanes > 2) {
6268 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6269 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6270 return -EINVAL;
251cc67c 6271 }
6d293983
ACO		 6272
6273 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6274 other_crtc_state =
6275 intel_atomic_get_crtc_state(state, other_crtc);
6276 if (IS_ERR(other_crtc_state))
6277 return PTR_ERR(other_crtc_state);
6278
6279 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6280 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6281 return -EINVAL;
1857e1da 6282 }
6d293983 6283 return 0;
1857e1da
DV		 6284 default:
6285 BUG();
6286 }
6287}
6288
e29c22c0
DV		 6289#define RETRY 1
6290static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6291 struct intel_crtc_state *pipe_config)
877d48d5 6292{
1857e1da 6293 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6294 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6295 int lane, link_bw, fdi_dotclock, ret;
6296 bool needs_recompute = false;
877d48d5 6297
e29c22c0 6298retry:
877d48d5
DV		 6299 /* FDI is a binary signal running at ~2.7GHz, encoding
6300 * each output octet as 10 bits. The actual frequency
6301 * is stored as a divider into a 100MHz clock, and the
6302 * mode pixel clock is stored in units of 1KHz.
6303 * Hence the bw of each lane in terms of the mode signal
6304 * is:
6305 */
6306 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6307
241bfc38 6308 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6309
2bd89a07 6310 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6311 pipe_config->pipe_bpp);
6312
6313 pipe_config->fdi_lanes = lane;
6314
2bd89a07 6315 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6316 link_bw, &pipe_config->fdi_m_n);
1857e1da 6317
6d293983
ACO		 6318 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6319 intel_crtc->pipe, pipe_config);
6320 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6321 pipe_config->pipe_bpp -= 2*3;
6322 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6323 pipe_config->pipe_bpp);
6324 needs_recompute = true;
6325 pipe_config->bw_constrained = true;
6326
6327 goto retry;
6328 }
6329
6330 if (needs_recompute)
6331 return RETRY;
6332
6d293983 6333 return ret;
877d48d5
DV		 6334}
6335
42db64ef 6336static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6337 struct intel_crtc_state *pipe_config)
42db64ef 6338{
d330a953 6339 pipe_config->ips_enabled = i915.enable_ips &&
3c4ca58c 6340 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 6341 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 6342}
6343
a43f6e0f 6344static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6345 struct intel_crtc_state *pipe_config)
79e53945 6346{
a43f6e0f 6347 struct drm_device *dev = crtc->base.dev;
8bd31e67 6348 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6349 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
d03c93d4 6350 int ret;
89749350 6351
ad3a4479 6352 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6353 if (INTEL_INFO(dev)->gen < 4) {
cf532bb2
VS		 6354 int clock_limit =
6355 dev_priv->display.get_display_clock_speed(dev);
6356
6357 /*
6358 * Enable pixel doubling when the dot clock
6359 * is > 90% of the (display) core speed.
6360 *
b397c96b
VS		 6361 * GDG double wide on either pipe,
6362 * otherwise pipe A only.
cf532bb2 6363 */
b397c96b 6364 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6365 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6366 clock_limit *= 2;
cf532bb2 6367 pipe_config->double_wide = true;
ad3a4479
VS		 6368 }
6369
241bfc38 6370 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6371 return -EINVAL;
2c07245f 6372 }
89749350 6373
1d1d0e27
VS		 6374 /*
6375 * Pipe horizontal size must be even in:
6376 * - DVO ganged mode
6377 * - LVDS dual channel mode
6378 * - Double wide pipe
6379 */
a93e255f 6380 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6381 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6382 pipe_config->pipe_src_w &= ~1;
6383
8693a824
DL		 6384 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6385 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6386 */
6387 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6388 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6389 return -EINVAL;
44f46b42 6390
f5adf94e 6391 if (HAS_IPS(dev))
a43f6e0f
DV		 6392 hsw_compute_ips_config(crtc, pipe_config);
6393
877d48d5 6394 if (pipe_config->has_pch_encoder)
a43f6e0f 6395 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6396
d03c93d4
CK		 6397 /* FIXME: remove below call once atomic mode set is place and all crtc
6398 * related checks called from atomic_crtc_check function */
6399 ret = 0;
6400 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6401 crtc, pipe_config->base.state);
6402 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6403
6404 return ret;
79e53945
JB		 6405}
6406
1652d19e
VS		 6407static int skylake_get_display_clock_speed(struct drm_device *dev)
6408{
6409 struct drm_i915_private *dev_priv = to_i915(dev);
6410 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6411 uint32_t cdctl = I915_READ(CDCLK_CTL);
6412 uint32_t linkrate;
6413
6414 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6415 WARN(1, "LCPLL1 not enabled\n");
6416 return 24000; /* 24MHz is the cd freq with NSSC ref */
6417 }
6418
6419 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6420 return 540000;
6421
6422 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6423 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6424
71cd8423
DL		 6425 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6426 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6427 /* vco 8640 */
6428 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6429 case CDCLK_FREQ_450_432:
6430 return 432000;
6431 case CDCLK_FREQ_337_308:
6432 return 308570;
6433 case CDCLK_FREQ_675_617:
6434 return 617140;
6435 default:
6436 WARN(1, "Unknown cd freq selection\n");
6437 }
6438 } else {
6439 /* vco 8100 */
6440 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6441 case CDCLK_FREQ_450_432:
6442 return 450000;
6443 case CDCLK_FREQ_337_308:
6444 return 337500;
6445 case CDCLK_FREQ_675_617:
6446 return 675000;
6447 default:
6448 WARN(1, "Unknown cd freq selection\n");
6449 }
6450 }
6451
6452 /* error case, do as if DPLL0 isn't enabled */
6453 return 24000;
6454}
6455
6456static int broadwell_get_display_clock_speed(struct drm_device *dev)
6457{
6458 struct drm_i915_private *dev_priv = dev->dev_private;
6459 uint32_t lcpll = I915_READ(LCPLL_CTL);
6460 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6461
6462 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6463 return 800000;
6464 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6465 return 450000;
6466 else if (freq == LCPLL_CLK_FREQ_450)
6467 return 450000;
6468 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6469 return 540000;
6470 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6471 return 337500;
6472 else
6473 return 675000;
6474}
6475
6476static int haswell_get_display_clock_speed(struct drm_device *dev)
6477{
6478 struct drm_i915_private *dev_priv = dev->dev_private;
6479 uint32_t lcpll = I915_READ(LCPLL_CTL);
6480 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6481
6482 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6483 return 800000;
6484 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6485 return 450000;
6486 else if (freq == LCPLL_CLK_FREQ_450)
6487 return 450000;
6488 else if (IS_HSW_ULT(dev))
6489 return 337500;
6490 else
6491 return 540000;
79e53945
JB		 6492}
6493
25eb05fc
JB		 6494static int valleyview_get_display_clock_speed(struct drm_device *dev)
6495{
d197b7d3 6496 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6497 u32 val;
6498 int divider;
6499
6bcda4f0
VS		 6500 if (dev_priv->hpll_freq == 0)
6501 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6502
d197b7d3
VS		 6503 mutex_lock(&dev_priv->dpio_lock);
6504 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6505 mutex_unlock(&dev_priv->dpio_lock);
6506
6507 divider = val & DISPLAY_FREQUENCY_VALUES;
6508
7d007f40
VS		 6509 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6510 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6511 "cdclk change in progress\n");
6512
6bcda4f0 6513 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6514}
6515
b37a6434
VS		 6516static int ilk_get_display_clock_speed(struct drm_device *dev)
6517{
6518 return 450000;
6519}
6520
e70236a8
JB		 6521static int i945_get_display_clock_speed(struct drm_device *dev)
6522{
6523 return 400000;
6524}
79e53945 6525
e70236a8 6526static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6527{
e907f170 6528 return 333333;
e70236a8 6529}
79e53945 6530
e70236a8
JB		 6531static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6532{
6533 return 200000;
6534}
79e53945 6535
257a7ffc
DV		 6536static int pnv_get_display_clock_speed(struct drm_device *dev)
6537{
6538 u16 gcfgc = 0;
6539
6540 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6541
6542 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6543 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6544 return 266667;
257a7ffc 6545 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6546 return 333333;
257a7ffc 6547 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6548 return 444444;
257a7ffc
DV		 6549 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6550 return 200000;
6551 default:
6552 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6553 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6554 return 133333;
257a7ffc 6555 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6556 return 166667;
257a7ffc
DV		 6557 }
6558}
6559
e70236a8
JB		 6560static int i915gm_get_display_clock_speed(struct drm_device *dev)
6561{
6562 u16 gcfgc = 0;
79e53945 6563
e70236a8
JB		 6564 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6565
6566 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6567 return 133333;
e70236a8
JB		 6568 else {
6569 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6570 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6571 return 333333;
e70236a8
JB		 6572 default:
6573 case GC_DISPLAY_CLOCK_190_200_MHZ:
6574 return 190000;
79e53945 6575 }
e70236a8
JB		 6576 }
6577}
6578
6579static int i865_get_display_clock_speed(struct drm_device *dev)
6580{
e907f170 6581 return 266667;
e70236a8
JB		 6582}
6583
6584static int i855_get_display_clock_speed(struct drm_device *dev)
6585{
6586 u16 hpllcc = 0;
6587 /* Assume that the hardware is in the high speed state. This
6588 * should be the default.
6589 */
6590 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6591 case GC_CLOCK_133_200:
6592 case GC_CLOCK_100_200:
6593 return 200000;
6594 case GC_CLOCK_166_250:
6595 return 250000;
6596 case GC_CLOCK_100_133:
e907f170 6597 return 133333;
e70236a8 6598 }
79e53945 6599
e70236a8
JB		 6600 /* Shouldn't happen */
6601 return 0;
6602}
79e53945 6603
e70236a8
JB		 6604static int i830_get_display_clock_speed(struct drm_device *dev)
6605{
e907f170 6606 return 133333;
79e53945
JB		 6607}
6608
2c07245f 6609static void
a65851af 6610intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6611{
a65851af
VS		 6612 while (*num > DATA_LINK_M_N_MASK ||
6613 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 6614 *num >>= 1;
6615 *den >>= 1;
6616 }
6617}
6618
a65851af
VS		 6619static void compute_m_n(unsigned int m, unsigned int n,
6620 uint32_t *ret_m, uint32_t *ret_n)
6621{
6622 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6623 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6624 intel_reduce_m_n_ratio(ret_m, ret_n);
6625}
6626
e69d0bc1
DV		 6627void
6628intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6629 int pixel_clock, int link_clock,
6630 struct intel_link_m_n *m_n)
2c07245f 6631{
e69d0bc1 6632 m_n->tu = 64;
a65851af
VS		 6633
6634 compute_m_n(bits_per_pixel * pixel_clock,
6635 link_clock * nlanes * 8,
6636 &m_n->gmch_m, &m_n->gmch_n);
6637
6638 compute_m_n(pixel_clock, link_clock,
6639 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 6640}
6641
a7615030
CW		 6642static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6643{
d330a953
JN		 6644 if (i915.panel_use_ssc >= 0)
6645 return i915.panel_use_ssc != 0;
41aa3448 6646 return dev_priv->vbt.lvds_use_ssc
435793df 6647 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 6648}
6649
a93e255f
ACO		 6650static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6651 int num_connectors)
c65d77d8 6652{
a93e255f 6653 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 6654 struct drm_i915_private *dev_priv = dev->dev_private;
6655 int refclk;
6656
a93e255f
ACO		 6657 WARN_ON(!crtc_state->base.state);
6658
5ab7b0b7 6659 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 6660 refclk = 100000;
a93e255f 6661 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 6662 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 6663 refclk = dev_priv->vbt.lvds_ssc_freq;
6664 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 6665 } else if (!IS_GEN2(dev)) {
6666 refclk = 96000;
6667 } else {
6668 refclk = 48000;
6669 }
6670
6671 return refclk;
6672}
6673
7429e9d4 6674static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 6675{
7df00d7a 6676 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 6677}
f47709a9 6678
7429e9d4
DV		 6679static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6680{
6681 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 6682}
6683
f47709a9 6684static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 6685 struct intel_crtc_state *crtc_state,
a7516a05
JB		 6686 intel_clock_t *reduced_clock)
6687{
f47709a9 6688 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 6689 u32 fp, fp2 = 0;
6690
6691 if (IS_PINEVIEW(dev)) {
190f68c5 6692 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6693 if (reduced_clock)
7429e9d4 6694 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 6695 } else {
190f68c5 6696 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6697 if (reduced_clock)
7429e9d4 6698 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 6699 }
6700
190f68c5 6701 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 6702
f47709a9 6703 crtc->lowfreq_avail = false;
a93e255f 6704 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 6705 reduced_clock) {
190f68c5 6706 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 6707 crtc->lowfreq_avail = true;
a7516a05 6708 } else {
190f68c5 6709 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 6710 }
6711}
6712
5e69f97f
CML		 6713static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6714 pipe)
89b667f8
JB		 6715{
6716 u32 reg_val;
6717
6718 /*
6719 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6720 * and set it to a reasonable value instead.
6721 */
ab3c759a 6722 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 6723 reg_val &= 0xffffff00;
6724 reg_val |= 0x00000030;
ab3c759a 6725 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6726
ab3c759a 6727 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6728 reg_val &= 0x8cffffff;
6729 reg_val = 0x8c000000;
ab3c759a 6730 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 6731
ab3c759a 6732 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 6733 reg_val &= 0xffffff00;
ab3c759a 6734 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6735
ab3c759a 6736 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6737 reg_val &= 0x00ffffff;
6738 reg_val |= 0xb0000000;
ab3c759a 6739 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 6740}
6741
b551842d
DV		 6742static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6743 struct intel_link_m_n *m_n)
6744{
6745 struct drm_device *dev = crtc->base.dev;
6746 struct drm_i915_private *dev_priv = dev->dev_private;
6747 int pipe = crtc->pipe;
6748
e3b95f1e
DV		 6749 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6750 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6751 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6752 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 6753}
6754
6755static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 6756 struct intel_link_m_n *m_n,
6757 struct intel_link_m_n *m2_n2)
b551842d
DV		 6758{
6759 struct drm_device *dev = crtc->base.dev;
6760 struct drm_i915_private *dev_priv = dev->dev_private;
6761 int pipe = crtc->pipe;
6e3c9717 6762 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 6763
6764 if (INTEL_INFO(dev)->gen >= 5) {
6765 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6766 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6767 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6768 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 6769 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6770 * for gen < 8) and if DRRS is supported (to make sure the
6771 * registers are not unnecessarily accessed).
6772 */
44395bfe 6773 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 6774 crtc->config->has_drrs) {
f769cd24
VK		 6775 I915_WRITE(PIPE_DATA_M2(transcoder),
6776 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6777 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6778 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6779 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6780 }
b551842d 6781 } else {
e3b95f1e
DV		 6782 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6783 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6784 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6785 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 6786 }
6787}
6788
fe3cd48d 6789void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 6790{
fe3cd48d
R		 6791 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6792
6793 if (m_n == M1_N1) {
6794 dp_m_n = &crtc->config->dp_m_n;
6795 dp_m2_n2 = &crtc->config->dp_m2_n2;
6796 } else if (m_n == M2_N2) {
6797
6798 /*
6799 * M2_N2 registers are not supported. Hence m2_n2 divider value
6800 * needs to be programmed into M1_N1.
6801 */
6802 dp_m_n = &crtc->config->dp_m2_n2;
6803 } else {
6804 DRM_ERROR("Unsupported divider value\n");
6805 return;
6806 }
6807
6e3c9717
ACO		 6808 if (crtc->config->has_pch_encoder)
6809 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 6810 else
fe3cd48d 6811 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 6812}
6813
d288f65f 6814static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 6815 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 6816{
6817 u32 dpll, dpll_md;
6818
6819 /*
6820 * Enable DPIO clock input. We should never disable the reference
6821 * clock for pipe B, since VGA hotplug / manual detection depends
6822 * on it.
6823 */
6824 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6825 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6826 /* We should never disable this, set it here for state tracking */
6827 if (crtc->pipe == PIPE_B)
6828 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6829 dpll |= DPLL_VCO_ENABLE;
d288f65f 6830 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 6831
d288f65f 6832 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 6833 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 6834 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 6835}
6836
d288f65f 6837static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6838 const struct intel_crtc_state *pipe_config)
a0c4da24 6839{
f47709a9 6840 struct drm_device *dev = crtc->base.dev;
a0c4da24 6841 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 6842 int pipe = crtc->pipe;
bdd4b6a6 6843 u32 mdiv;
a0c4da24 6844 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 6845 u32 coreclk, reg_val;
a0c4da24 6846
09153000
DV		 6847 mutex_lock(&dev_priv->dpio_lock);
6848
d288f65f
VS		 6849 bestn = pipe_config->dpll.n;
6850 bestm1 = pipe_config->dpll.m1;
6851 bestm2 = pipe_config->dpll.m2;
6852 bestp1 = pipe_config->dpll.p1;
6853 bestp2 = pipe_config->dpll.p2;
a0c4da24 6854
89b667f8
JB		 6855 /* See eDP HDMI DPIO driver vbios notes doc */
6856
6857 /* PLL B needs special handling */
bdd4b6a6 6858 if (pipe == PIPE_B)
5e69f97f 6859 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 6860
6861 /* Set up Tx target for periodic Rcomp update */
ab3c759a 6862 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 6863
6864 /* Disable target IRef on PLL */
ab3c759a 6865 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 6866 reg_val &= 0x00ffffff;
ab3c759a 6867 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 6868
6869 /* Disable fast lock */
ab3c759a 6870 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 6871
6872 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 6873 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6874 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6875 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 6876 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 6877
6878 /*
6879 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6880 * but we don't support that).
6881 * Note: don't use the DAC post divider as it seems unstable.
6882 */
6883 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 6884 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6885
a0c4da24 6886 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 6887 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6888
89b667f8 6889 /* Set HBR and RBR LPF coefficients */
d288f65f 6890 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 6891 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6892 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 6893 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 6894 0x009f0003);
89b667f8 6895 else
ab3c759a 6896 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 6897 0x00d0000f);
6898
681a8504 6899 if (pipe_config->has_dp_encoder) {
89b667f8 6900 /* Use SSC source */
bdd4b6a6 6901 if (pipe == PIPE_A)
ab3c759a 6902 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6903 0x0df40000);
6904 else
ab3c759a 6905 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6906 0x0df70000);
6907 } else { /* HDMI or VGA */
6908 /* Use bend source */
bdd4b6a6 6909 if (pipe == PIPE_A)
ab3c759a 6910 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6911 0x0df70000);
6912 else
ab3c759a 6913 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6914 0x0df40000);
6915 }
a0c4da24 6916
ab3c759a 6917 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 6918 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 6919 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6920 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 6921 coreclk |= 0x01000000;
ab3c759a 6922 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 6923
ab3c759a 6924 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
09153000 6925 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 6926}
6927
d288f65f 6928static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 6929 struct intel_crtc_state *pipe_config)
1ae0d137 6930{
d288f65f 6931 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 6932 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6933 DPLL_VCO_ENABLE;
6934 if (crtc->pipe != PIPE_A)
d288f65f 6935 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 6936
d288f65f
VS		 6937 pipe_config->dpll_hw_state.dpll_md =
6938 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 6939}
6940
d288f65f 6941static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6942 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 6943{
6944 struct drm_device *dev = crtc->base.dev;
6945 struct drm_i915_private *dev_priv = dev->dev_private;
6946 int pipe = crtc->pipe;
6947 int dpll_reg = DPLL(crtc->pipe);
6948 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 6949 u32 loopfilter, tribuf_calcntr;
9d556c99 6950 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 6951 u32 dpio_val;
9cbe40c1 6952 int vco;
9d556c99 6953
d288f65f
VS		 6954 bestn = pipe_config->dpll.n;
6955 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6956 bestm1 = pipe_config->dpll.m1;
6957 bestm2 = pipe_config->dpll.m2 >> 22;
6958 bestp1 = pipe_config->dpll.p1;
6959 bestp2 = pipe_config->dpll.p2;
9cbe40c1 6960 vco = pipe_config->dpll.vco;
a945ce7e 6961 dpio_val = 0;
9cbe40c1 6962 loopfilter = 0;
9d556c99
CML		 6963
6964 /*
6965 * Enable Refclk and SSC
6966 */
a11b0703 6967 I915_WRITE(dpll_reg,
d288f65f 6968 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703
VS		 6969
6970 mutex_lock(&dev_priv->dpio_lock);
9d556c99 6971
9d556c99
CML		 6972 /* p1 and p2 divider */
6973 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6974 5 << DPIO_CHV_S1_DIV_SHIFT |
6975 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6976 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6977 1 << DPIO_CHV_K_DIV_SHIFT);
6978
6979 /* Feedback post-divider - m2 */
6980 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6981
6982 /* Feedback refclk divider - n and m1 */
6983 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6984 DPIO_CHV_M1_DIV_BY_2 |
6985 1 << DPIO_CHV_N_DIV_SHIFT);
6986
6987 /* M2 fraction division */
a945ce7e
VP		 6988 if (bestm2_frac)
6989 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 6990
6991 /* M2 fraction division enable */
a945ce7e
VP		 6992 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6993 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6994 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6995 if (bestm2_frac)
6996 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6997 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 6998
de3a0fde
VP		 6999 /* Program digital lock detect threshold */
7000 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7001 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7002 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7003 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7004 if (!bestm2_frac)
7005 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7006 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7007
9d556c99 7008 /* Loop filter */
9cbe40c1
VP		 7009 if (vco == 5400000) {
7010 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7011 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7012 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7013 tribuf_calcntr = 0x9;
7014 } else if (vco <= 6200000) {
7015 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7016 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7017 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7018 tribuf_calcntr = 0x9;
7019 } else if (vco <= 6480000) {
7020 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7021 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7022 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7023 tribuf_calcntr = 0x8;
7024 } else {
7025 /* Not supported. Apply the same limits as in the max case */
7026 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7027 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7028 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7029 tribuf_calcntr = 0;
7030 }
9d556c99
CML		 7031 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7032
968040b2 7033 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7034 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7035 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7036 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7037
9d556c99
CML		 7038 /* AFC Recal */
7039 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7040 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7041 DPIO_AFC_RECAL);
7042
7043 mutex_unlock(&dev_priv->dpio_lock);
7044}
7045
d288f65f
VS		 7046/**
7047 * vlv_force_pll_on - forcibly enable just the PLL
7048 * @dev_priv: i915 private structure
7049 * @pipe: pipe PLL to enable
7050 * @dpll: PLL configuration
7051 *
7052 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7053 * in cases where we need the PLL enabled even when @pipe is not going to
7054 * be enabled.
7055 */
7056void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7057 const struct dpll *dpll)
7058{
7059 struct intel_crtc *crtc =
7060 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7061 struct intel_crtc_state pipe_config = {
a93e255f 7062 .base.crtc = &crtc->base,
d288f65f
VS		 7063 .pixel_multiplier = 1,
7064 .dpll = *dpll,
7065 };
7066
7067 if (IS_CHERRYVIEW(dev)) {
7068 chv_update_pll(crtc, &pipe_config);
7069 chv_prepare_pll(crtc, &pipe_config);
7070 chv_enable_pll(crtc, &pipe_config);
7071 } else {
7072 vlv_update_pll(crtc, &pipe_config);
7073 vlv_prepare_pll(crtc, &pipe_config);
7074 vlv_enable_pll(crtc, &pipe_config);
7075 }
7076}
7077
7078/**
7079 * vlv_force_pll_off - forcibly disable just the PLL
7080 * @dev_priv: i915 private structure
7081 * @pipe: pipe PLL to disable
7082 *
7083 * Disable the PLL for @pipe. To be used in cases where we need
7084 * the PLL enabled even when @pipe is not going to be enabled.
7085 */
7086void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7087{
7088 if (IS_CHERRYVIEW(dev))
7089 chv_disable_pll(to_i915(dev), pipe);
7090 else
7091 vlv_disable_pll(to_i915(dev), pipe);
7092}
7093
f47709a9 7094static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 7095 struct intel_crtc_state *crtc_state,
f47709a9 7096 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7097 int num_connectors)
7098{
f47709a9 7099 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7100 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7101 u32 dpll;
7102 bool is_sdvo;
190f68c5 7103 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7104
190f68c5 7105 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7106
a93e255f
ACO		 7107 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7108 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7109
7110 dpll = DPLL_VGA_MODE_DIS;
7111
a93e255f 7112 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7113 dpll |= DPLLB_MODE_LVDS;
7114 else
7115 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7116
ef1b460d 7117 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7118 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7119 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7120 }
198a037f
DV		 7121
7122 if (is_sdvo)
4a33e48d 7123 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7124
190f68c5 7125 if (crtc_state->has_dp_encoder)
4a33e48d 7126 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7127
7128 /* compute bitmask from p1 value */
7129 if (IS_PINEVIEW(dev))
7130 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7131 else {
7132 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7133 if (IS_G4X(dev) && reduced_clock)
7134 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7135 }
7136 switch (clock->p2) {
7137 case 5:
7138 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7139 break;
7140 case 7:
7141 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7142 break;
7143 case 10:
7144 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7145 break;
7146 case 14:
7147 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7148 break;
7149 }
7150 if (INTEL_INFO(dev)->gen >= 4)
7151 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7152
190f68c5 7153 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7154 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7155 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7156 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7157 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7158 else
7159 dpll |= PLL_REF_INPUT_DREFCLK;
7160
7161 dpll |= DPLL_VCO_ENABLE;
190f68c5 7162 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7163
eb1cbe48 7164 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7165 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7166 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7167 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7168 }
7169}
7170
f47709a9 7171static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 7172 struct intel_crtc_state *crtc_state,
f47709a9 7173 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7174 int num_connectors)
7175{
f47709a9 7176 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7177 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7178 u32 dpll;
190f68c5 7179 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7180
190f68c5 7181 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7182
eb1cbe48
DV		 7183 dpll = DPLL_VGA_MODE_DIS;
7184
a93e255f 7185 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7186 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7187 } else {
7188 if (clock->p1 == 2)
7189 dpll |= PLL_P1_DIVIDE_BY_TWO;
7190 else
7191 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7192 if (clock->p2 == 4)
7193 dpll |= PLL_P2_DIVIDE_BY_4;
7194 }
7195
a93e255f 7196 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7197 dpll |= DPLL_DVO_2X_MODE;
7198
a93e255f 7199 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7200 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7201 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7202 else
7203 dpll |= PLL_REF_INPUT_DREFCLK;
7204
7205 dpll |= DPLL_VCO_ENABLE;
190f68c5 7206 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7207}
7208
8a654f3b 7209static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7210{
7211 struct drm_device *dev = intel_crtc->base.dev;
7212 struct drm_i915_private *dev_priv = dev->dev_private;
7213 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7214 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7215 struct drm_display_mode *adjusted_mode =
6e3c9717 7216 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7217 uint32_t crtc_vtotal, crtc_vblank_end;
7218 int vsyncshift = 0;
4d8a62ea
DV		 7219
7220 /* We need to be careful not to changed the adjusted mode, for otherwise
7221 * the hw state checker will get angry at the mismatch. */
7222 crtc_vtotal = adjusted_mode->crtc_vtotal;
7223 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7224
609aeaca 7225 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7226 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7227 crtc_vtotal -= 1;
7228 crtc_vblank_end -= 1;
609aeaca 7229
409ee761 7230 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7231 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7232 else
7233 vsyncshift = adjusted_mode->crtc_hsync_start -
7234 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7235 if (vsyncshift < 0)
7236 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7237 }
7238
7239 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7240 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7241
fe2b8f9d 7242 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7243 (adjusted_mode->crtc_hdisplay - 1) |
7244 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7245 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7246 (adjusted_mode->crtc_hblank_start - 1) |
7247 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7248 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7249 (adjusted_mode->crtc_hsync_start - 1) |
7250 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7251
fe2b8f9d 7252 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7253 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7254 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7255 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7256 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7257 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7258 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7259 (adjusted_mode->crtc_vsync_start - 1) |
7260 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7261
b5e508d4
PZ		 7262 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7263 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7264 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7265 * bits. */
7266 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7267 (pipe == PIPE_B || pipe == PIPE_C))
7268 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7269
b0e77b9c
PZ		 7270 /* pipesrc controls the size that is scaled from, which should
7271 * always be the user's requested size.
7272 */
7273 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7274 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7275 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7276}
7277
1bd1bd80 7278static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7279 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7280{
7281 struct drm_device *dev = crtc->base.dev;
7282 struct drm_i915_private *dev_priv = dev->dev_private;
7283 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7284 uint32_t tmp;
7285
7286 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7287 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7288 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7289 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7290 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7291 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7292 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7293 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7294 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7295
7296 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7297 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7298 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7299 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7300 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7301 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7302 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7303 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7304 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7305
7306 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7307 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7308 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7309 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7310 }
7311
7312 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7313 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7314 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7315
2d112de7
ACO		 7316 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7317 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7318}
7319
f6a83288 7320void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7321 struct intel_crtc_state *pipe_config)
babea61d 7322{
2d112de7
ACO		 7323 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7324 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7325 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7326 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7327
2d112de7
ACO		 7328 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7329 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7330 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7331 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7332
2d112de7 7333 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7334
2d112de7
ACO		 7335 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7336 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7337}
7338
84b046f3
DV		 7339static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7340{
7341 struct drm_device *dev = intel_crtc->base.dev;
7342 struct drm_i915_private *dev_priv = dev->dev_private;
7343 uint32_t pipeconf;
7344
9f11a9e4 7345 pipeconf = 0;
84b046f3 7346
b6b5d049
VS		 7347 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7348 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7349 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7350
6e3c9717 7351 if (intel_crtc->config->double_wide)
cf532bb2 7352 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7353
ff9ce46e
DV		 7354 /* only g4x and later have fancy bpc/dither controls */
7355 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7356 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7357 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7358 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7359 PIPECONF_DITHER_TYPE_SP;
84b046f3 7360
6e3c9717 7361 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7362 case 18:
7363 pipeconf |= PIPECONF_6BPC;
7364 break;
7365 case 24:
7366 pipeconf |= PIPECONF_8BPC;
7367 break;
7368 case 30:
7369 pipeconf |= PIPECONF_10BPC;
7370 break;
7371 default:
7372 /* Case prevented by intel_choose_pipe_bpp_dither. */
7373 BUG();
84b046f3
DV		 7374 }
7375 }
7376
7377 if (HAS_PIPE_CXSR(dev)) {
7378 if (intel_crtc->lowfreq_avail) {
7379 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7380 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7381 } else {
7382 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7383 }
7384 }
7385
6e3c9717 7386 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7387 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7388 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7389 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7390 else
7391 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7392 } else
84b046f3
DV		 7393 pipeconf |= PIPECONF_PROGRESSIVE;
7394
6e3c9717 7395 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7396 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7397
84b046f3
DV		 7398 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7399 POSTING_READ(PIPECONF(intel_crtc->pipe));
7400}
7401
190f68c5
ACO		 7402static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7403 struct intel_crtc_state *crtc_state)
79e53945 7404{
c7653199 7405 struct drm_device *dev = crtc->base.dev;
79e53945 7406 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7407 int refclk, num_connectors = 0;
652c393a 7408 intel_clock_t clock, reduced_clock;
a16af721 7409 bool ok, has_reduced_clock = false;
e9fd1c02 7410 bool is_lvds = false, is_dsi = false;
5eddb70b 7411 struct intel_encoder *encoder;
d4906093 7412 const intel_limit_t *limit;
55bb9992
ACO		 7413 struct drm_atomic_state *state = crtc_state->base.state;
7414 struct drm_connector_state *connector_state;
7415 int i;
79e53945 7416
55bb9992
ACO		 7417 for (i = 0; i < state->num_connector; i++) {
7418 if (!state->connectors[i])
d0737e1d
ACO		 7419 continue;
7420
55bb9992
ACO		 7421 connector_state = state->connector_states[i];
7422 if (connector_state->crtc != &crtc->base)
7423 continue;
7424
7425 encoder = to_intel_encoder(connector_state->best_encoder);
7426
5eddb70b 7427 switch (encoder->type) {
79e53945
JB		 7428 case INTEL_OUTPUT_LVDS:
7429 is_lvds = true;
7430 break;
e9fd1c02
JN		 7431 case INTEL_OUTPUT_DSI:
7432 is_dsi = true;
7433 break;
6847d71b
PZ		 7434 default:
7435 break;
79e53945 7436 }
43565a06 7437
c751ce4f 7438 num_connectors++;
79e53945
JB		 7439 }
7440
f2335330 7441 if (is_dsi)
5b18e57c 7442 return 0;
f2335330 7443
190f68c5 7444 if (!crtc_state->clock_set) {
a93e255f 7445 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7446
e9fd1c02
JN		 7447 /*
7448 * Returns a set of divisors for the desired target clock with
7449 * the given refclk, or FALSE. The returned values represent
7450 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7451 * 2) / p1 / p2.
7452 */
a93e255f
ACO		 7453 limit = intel_limit(crtc_state, refclk);
7454 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7455 crtc_state->port_clock,
e9fd1c02 7456 refclk, NULL, &clock);
f2335330 7457 if (!ok) {
e9fd1c02
JN		 7458 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7459 return -EINVAL;
7460 }
79e53945 7461
f2335330
JN		 7462 if (is_lvds && dev_priv->lvds_downclock_avail) {
7463 /*
7464 * Ensure we match the reduced clock's P to the target
7465 * clock. If the clocks don't match, we can't switch
7466 * the display clock by using the FP0/FP1. In such case
7467 * we will disable the LVDS downclock feature.
7468 */
7469 has_reduced_clock =
a93e255f 7470 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 7471 dev_priv->lvds_downclock,
7472 refclk, &clock,
7473 &reduced_clock);
7474 }
7475 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7476 crtc_state->dpll.n = clock.n;
7477 crtc_state->dpll.m1 = clock.m1;
7478 crtc_state->dpll.m2 = clock.m2;
7479 crtc_state->dpll.p1 = clock.p1;
7480 crtc_state->dpll.p2 = clock.p2;
f47709a9 7481 }
7026d4ac 7482
e9fd1c02 7483 if (IS_GEN2(dev)) {
190f68c5 7484 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 7485 has_reduced_clock ? &reduced_clock : NULL,
7486 num_connectors);
9d556c99 7487 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 7488 chv_update_pll(crtc, crtc_state);
e9fd1c02 7489 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 7490 vlv_update_pll(crtc, crtc_state);
e9fd1c02 7491 } else {
190f68c5 7492 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 7493 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 7494 num_connectors);
e9fd1c02 7495 }
79e53945 7496
c8f7a0db 7497 return 0;
f564048e
EA		 7498}
7499
2fa2fe9a 7500static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7501 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7502{
7503 struct drm_device *dev = crtc->base.dev;
7504 struct drm_i915_private *dev_priv = dev->dev_private;
7505 uint32_t tmp;
7506
dc9e7dec
VS		 7507 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7508 return;
7509
2fa2fe9a 7510 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7511 if (!(tmp & PFIT_ENABLE))
7512 return;
2fa2fe9a 7513
06922821 7514 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7515 if (INTEL_INFO(dev)->gen < 4) {
7516 if (crtc->pipe != PIPE_B)
7517 return;
2fa2fe9a
DV		 7518 } else {
7519 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7520 return;
7521 }
7522
06922821 7523 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7524 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7525 if (INTEL_INFO(dev)->gen < 5)
7526 pipe_config->gmch_pfit.lvds_border_bits =
7527 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7528}
7529
acbec814 7530static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7531 struct intel_crtc_state *pipe_config)
acbec814
JB		 7532{
7533 struct drm_device *dev = crtc->base.dev;
7534 struct drm_i915_private *dev_priv = dev->dev_private;
7535 int pipe = pipe_config->cpu_transcoder;
7536 intel_clock_t clock;
7537 u32 mdiv;
662c6ecb 7538 int refclk = 100000;
acbec814 7539
f573de5a
SK		 7540 /* In case of MIPI DPLL will not even be used */
7541 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7542 return;
7543
acbec814 7544 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 7545 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
acbec814
JB		 7546 mutex_unlock(&dev_priv->dpio_lock);
7547
7548 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7549 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7550 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7551 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7552 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7553
f646628b 7554 vlv_clock(refclk, &clock);
acbec814 7555
f646628b
VS		 7556 /* clock.dot is the fast clock */
7557 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 7558}
7559
5724dbd1
DL		 7560static void
7561i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7562 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7563{
7564 struct drm_device *dev = crtc->base.dev;
7565 struct drm_i915_private *dev_priv = dev->dev_private;
7566 u32 val, base, offset;
7567 int pipe = crtc->pipe, plane = crtc->plane;
7568 int fourcc, pixel_format;
6761dd31 7569 unsigned int aligned_height;
b113d5ee 7570 struct drm_framebuffer *fb;
1b842c89 7571 struct intel_framebuffer *intel_fb;
1ad292b5 7572
42a7b088
DL		 7573 val = I915_READ(DSPCNTR(plane));
7574 if (!(val & DISPLAY_PLANE_ENABLE))
7575 return;
7576
d9806c9f 7577 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7578 if (!intel_fb) {
1ad292b5
JB		 7579 DRM_DEBUG_KMS("failed to alloc fb\n");
7580 return;
7581 }
7582
1b842c89
DL		 7583 fb = &intel_fb->base;
7584
18c5247e
DV		 7585 if (INTEL_INFO(dev)->gen >= 4) {
7586 if (val & DISPPLANE_TILED) {
49af449b 7587 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7588 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7589 }
7590 }
1ad292b5
JB		 7591
7592 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7593 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7594 fb->pixel_format = fourcc;
7595 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7596
7597 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7598 if (plane_config->tiling)
1ad292b5
JB		 7599 offset = I915_READ(DSPTILEOFF(plane));
7600 else
7601 offset = I915_READ(DSPLINOFF(plane));
7602 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7603 } else {
7604 base = I915_READ(DSPADDR(plane));
7605 }
7606 plane_config->base = base;
7607
7608 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7609 fb->width = ((val >> 16) & 0xfff) + 1;
7610 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7611
7612 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7613 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7614
b113d5ee 7615 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7616 fb->pixel_format,
7617 fb->modifier[0]);
1ad292b5 7618
f37b5c2b 7619 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7620
2844a921
DL		 7621 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7622 pipe_name(pipe), plane, fb->width, fb->height,
7623 fb->bits_per_pixel, base, fb->pitches[0],
7624 plane_config->size);
1ad292b5 7625
2d14030b 7626 plane_config->fb = intel_fb;
1ad292b5
JB		 7627}
7628
70b23a98 7629static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7630 struct intel_crtc_state *pipe_config)
70b23a98
VS		 7631{
7632 struct drm_device *dev = crtc->base.dev;
7633 struct drm_i915_private *dev_priv = dev->dev_private;
7634 int pipe = pipe_config->cpu_transcoder;
7635 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7636 intel_clock_t clock;
7637 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7638 int refclk = 100000;
7639
7640 mutex_lock(&dev_priv->dpio_lock);
7641 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7642 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7643 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7644 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7645 mutex_unlock(&dev_priv->dpio_lock);
7646
7647 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7648 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7649 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7650 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7651 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7652
7653 chv_clock(refclk, &clock);
7654
7655 /* clock.dot is the fast clock */
7656 pipe_config->port_clock = clock.dot / 5;
7657}
7658
0e8ffe1b 7659static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 7660 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 7661{
7662 struct drm_device *dev = crtc->base.dev;
7663 struct drm_i915_private *dev_priv = dev->dev_private;
7664 uint32_t tmp;
7665
f458ebbc
DV		 7666 if (!intel_display_power_is_enabled(dev_priv,
7667 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 7668 return false;
7669
e143a21c 7670 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 7671 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 7672
0e8ffe1b
DV		 7673 tmp = I915_READ(PIPECONF(crtc->pipe));
7674 if (!(tmp & PIPECONF_ENABLE))
7675 return false;
7676
42571aef
VS		 7677 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7678 switch (tmp & PIPECONF_BPC_MASK) {
7679 case PIPECONF_6BPC:
7680 pipe_config->pipe_bpp = 18;
7681 break;
7682 case PIPECONF_8BPC:
7683 pipe_config->pipe_bpp = 24;
7684 break;
7685 case PIPECONF_10BPC:
7686 pipe_config->pipe_bpp = 30;
7687 break;
7688 default:
7689 break;
7690 }
7691 }
7692
b5a9fa09
DV		 7693 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7694 pipe_config->limited_color_range = true;
7695
282740f7
VS		 7696 if (INTEL_INFO(dev)->gen < 4)
7697 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7698
1bd1bd80
DV		 7699 intel_get_pipe_timings(crtc, pipe_config);
7700
2fa2fe9a
DV		 7701 i9xx_get_pfit_config(crtc, pipe_config);
7702
6c49f241
DV		 7703 if (INTEL_INFO(dev)->gen >= 4) {
7704 tmp = I915_READ(DPLL_MD(crtc->pipe));
7705 pipe_config->pixel_multiplier =
7706 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7707 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 7708 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 7709 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7710 tmp = I915_READ(DPLL(crtc->pipe));
7711 pipe_config->pixel_multiplier =
7712 ((tmp & SDVO_MULTIPLIER_MASK)
7713 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7714 } else {
7715 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7716 * port and will be fixed up in the encoder->get_config
7717 * function. */
7718 pipe_config->pixel_multiplier = 1;
7719 }
8bcc2795
DV		 7720 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7721 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 7722 /*
7723 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7724 * on 830. Filter it out here so that we don't
7725 * report errors due to that.
7726 */
7727 if (IS_I830(dev))
7728 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7729
8bcc2795
DV		 7730 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7731 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 7732 } else {
7733 /* Mask out read-only status bits. */
7734 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7735 DPLL_PORTC_READY_MASK |
7736 DPLL_PORTB_READY_MASK);
8bcc2795 7737 }
6c49f241 7738
70b23a98
VS		 7739 if (IS_CHERRYVIEW(dev))
7740 chv_crtc_clock_get(crtc, pipe_config);
7741 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 7742 vlv_crtc_clock_get(crtc, pipe_config);
7743 else
7744 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 7745
0e8ffe1b
DV		 7746 return true;
7747}
7748
dde86e2d 7749static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 7750{
7751 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 7752 struct intel_encoder *encoder;
74cfd7ac 7753 u32 val, final;
13d83a67 7754 bool has_lvds = false;
199e5d79 7755 bool has_cpu_edp = false;
199e5d79 7756 bool has_panel = false;
99eb6a01
KP		 7757 bool has_ck505 = false;
7758 bool can_ssc = false;
13d83a67
JB		 7759
7760 /* We need to take the global config into account */
b2784e15 7761 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 7762 switch (encoder->type) {
7763 case INTEL_OUTPUT_LVDS:
7764 has_panel = true;
7765 has_lvds = true;
7766 break;
7767 case INTEL_OUTPUT_EDP:
7768 has_panel = true;
2de6905f 7769 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 7770 has_cpu_edp = true;
7771 break;
6847d71b
PZ		 7772 default:
7773 break;
13d83a67
JB		 7774 }
7775 }
7776
99eb6a01 7777 if (HAS_PCH_IBX(dev)) {
41aa3448 7778 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 7779 can_ssc = has_ck505;
7780 } else {
7781 has_ck505 = false;
7782 can_ssc = true;
7783 }
7784
2de6905f
ID		 7785 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7786 has_panel, has_lvds, has_ck505);
13d83a67
JB		 7787
7788 /* Ironlake: try to setup display ref clock before DPLL
7789 * enabling. This is only under driver's control after
7790 * PCH B stepping, previous chipset stepping should be
7791 * ignoring this setting.
7792 */
74cfd7ac
CW		 7793 val = I915_READ(PCH_DREF_CONTROL);
7794
7795 /* As we must carefully and slowly disable/enable each source in turn,
7796 * compute the final state we want first and check if we need to
7797 * make any changes at all.
7798 */
7799 final = val;
7800 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7801 if (has_ck505)
7802 final |= DREF_NONSPREAD_CK505_ENABLE;
7803 else
7804 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7805
7806 final &= ~DREF_SSC_SOURCE_MASK;
7807 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7808 final &= ~DREF_SSC1_ENABLE;
7809
7810 if (has_panel) {
7811 final |= DREF_SSC_SOURCE_ENABLE;
7812
7813 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7814 final |= DREF_SSC1_ENABLE;
7815
7816 if (has_cpu_edp) {
7817 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7818 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7819 else
7820 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7821 } else
7822 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7823 } else {
7824 final |= DREF_SSC_SOURCE_DISABLE;
7825 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7826 }
7827
7828 if (final == val)
7829 return;
7830
13d83a67 7831 /* Always enable nonspread source */
74cfd7ac 7832 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 7833
99eb6a01 7834 if (has_ck505)
74cfd7ac 7835 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 7836 else
74cfd7ac 7837 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 7838
199e5d79 7839 if (has_panel) {
74cfd7ac
CW		 7840 val &= ~DREF_SSC_SOURCE_MASK;
7841 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 7842
199e5d79 7843 /* SSC must be turned on before enabling the CPU output */
99eb6a01 7844 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7845 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 7846 val |= DREF_SSC1_ENABLE;
e77166b5 7847 } else
74cfd7ac 7848 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 7849
7850 /* Get SSC going before enabling the outputs */
74cfd7ac 7851 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7852 POSTING_READ(PCH_DREF_CONTROL);
7853 udelay(200);
7854
74cfd7ac 7855 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 7856
7857 /* Enable CPU source on CPU attached eDP */
199e5d79 7858 if (has_cpu_edp) {
99eb6a01 7859 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7860 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 7861 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 7862 } else
74cfd7ac 7863 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 7864 } else
74cfd7ac 7865 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7866
74cfd7ac 7867 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7868 POSTING_READ(PCH_DREF_CONTROL);
7869 udelay(200);
7870 } else {
7871 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7872
74cfd7ac 7873 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 7874
7875 /* Turn off CPU output */
74cfd7ac 7876 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7877
74cfd7ac 7878 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7879 POSTING_READ(PCH_DREF_CONTROL);
7880 udelay(200);
7881
7882 /* Turn off the SSC source */
74cfd7ac
CW		 7883 val &= ~DREF_SSC_SOURCE_MASK;
7884 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 7885
7886 /* Turn off SSC1 */
74cfd7ac 7887 val &= ~DREF_SSC1_ENABLE;
199e5d79 7888
74cfd7ac 7889 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 7890 POSTING_READ(PCH_DREF_CONTROL);
7891 udelay(200);
7892 }
74cfd7ac
CW		 7893
7894 BUG_ON(val != final);
13d83a67
JB		 7895}
7896
f31f2d55 7897static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 7898{
f31f2d55 7899 uint32_t tmp;
dde86e2d 7900
0ff066a9
PZ		 7901 tmp = I915_READ(SOUTH_CHICKEN2);
7902 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7903 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7904
0ff066a9
PZ		 7905 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7906 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7907 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 7908
0ff066a9
PZ		 7909 tmp = I915_READ(SOUTH_CHICKEN2);
7910 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7911 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7912
0ff066a9
PZ		 7913 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7914 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7915 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 7916}
7917
7918/* WaMPhyProgramming:hsw */
7919static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7920{
7921 uint32_t tmp;
dde86e2d
PZ		 7922
7923 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7924 tmp &= ~(0xFF << 24);
7925 tmp |= (0x12 << 24);
7926 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7927
dde86e2d
PZ		 7928 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7929 tmp |= (1 << 11);
7930 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7931
7932 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7933 tmp |= (1 << 11);
7934 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7935
dde86e2d
PZ		 7936 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7937 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7938 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7939
7940 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7941 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7942 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7943
0ff066a9
PZ		 7944 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7945 tmp &= ~(7 << 13);
7946 tmp |= (5 << 13);
7947 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 7948
0ff066a9
PZ		 7949 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7950 tmp &= ~(7 << 13);
7951 tmp |= (5 << 13);
7952 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 7953
7954 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7955 tmp &= ~0xFF;
7956 tmp |= 0x1C;
7957 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7958
7959 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7960 tmp &= ~0xFF;
7961 tmp |= 0x1C;
7962 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7963
7964 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7965 tmp &= ~(0xFF << 16);
7966 tmp |= (0x1C << 16);
7967 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7968
7969 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7970 tmp &= ~(0xFF << 16);
7971 tmp |= (0x1C << 16);
7972 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7973
0ff066a9
PZ		 7974 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7975 tmp |= (1 << 27);
7976 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 7977
0ff066a9
PZ		 7978 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7979 tmp |= (1 << 27);
7980 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 7981
0ff066a9
PZ		 7982 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7983 tmp &= ~(0xF << 28);
7984 tmp |= (4 << 28);
7985 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 7986
0ff066a9
PZ		 7987 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7988 tmp &= ~(0xF << 28);
7989 tmp |= (4 << 28);
7990 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 7991}
7992
2fa86a1f
PZ		 7993/* Implements 3 different sequences from BSpec chapter "Display iCLK
7994 * Programming" based on the parameters passed:
7995 * - Sequence to enable CLKOUT_DP
7996 * - Sequence to enable CLKOUT_DP without spread
7997 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7998 */
7999static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8000 bool with_fdi)
f31f2d55
PZ		 8001{
8002 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8003 uint32_t reg, tmp;
8004
8005 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8006 with_spread = true;
8007 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8008 with_fdi, "LP PCH doesn't have FDI\n"))
8009 with_fdi = false;
f31f2d55
PZ		 8010
8011 mutex_lock(&dev_priv->dpio_lock);
8012
8013 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8014 tmp &= ~SBI_SSCCTL_DISABLE;
8015 tmp |= SBI_SSCCTL_PATHALT;
8016 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8017
8018 udelay(24);
8019
2fa86a1f
PZ		 8020 if (with_spread) {
8021 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8022 tmp &= ~SBI_SSCCTL_PATHALT;
8023 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8024
2fa86a1f
PZ		 8025 if (with_fdi) {
8026 lpt_reset_fdi_mphy(dev_priv);
8027 lpt_program_fdi_mphy(dev_priv);
8028 }
8029 }
dde86e2d 8030
2fa86a1f
PZ		 8031 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8032 SBI_GEN0 : SBI_DBUFF0;
8033 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8034 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8035 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 8036
8037 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 8038}
8039
47701c3b
PZ		 8040/* Sequence to disable CLKOUT_DP */
8041static void lpt_disable_clkout_dp(struct drm_device *dev)
8042{
8043 struct drm_i915_private *dev_priv = dev->dev_private;
8044 uint32_t reg, tmp;
8045
8046 mutex_lock(&dev_priv->dpio_lock);
8047
8048 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8049 SBI_GEN0 : SBI_DBUFF0;
8050 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8051 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8052 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8053
8054 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8055 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8056 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8057 tmp |= SBI_SSCCTL_PATHALT;
8058 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8059 udelay(32);
8060 }
8061 tmp |= SBI_SSCCTL_DISABLE;
8062 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8063 }
8064
8065 mutex_unlock(&dev_priv->dpio_lock);
8066}
8067
bf8fa3d3
PZ		 8068static void lpt_init_pch_refclk(struct drm_device *dev)
8069{
bf8fa3d3
PZ		 8070 struct intel_encoder *encoder;
8071 bool has_vga = false;
8072
b2784e15 8073 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8074 switch (encoder->type) {
8075 case INTEL_OUTPUT_ANALOG:
8076 has_vga = true;
8077 break;
6847d71b
PZ		 8078 default:
8079 break;
bf8fa3d3
PZ		 8080 }
8081 }
8082
47701c3b
PZ		 8083 if (has_vga)
8084 lpt_enable_clkout_dp(dev, true, true);
8085 else
8086 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8087}
8088
dde86e2d
PZ		 8089/*
8090 * Initialize reference clocks when the driver loads
8091 */
8092void intel_init_pch_refclk(struct drm_device *dev)
8093{
8094 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8095 ironlake_init_pch_refclk(dev);
8096 else if (HAS_PCH_LPT(dev))
8097 lpt_init_pch_refclk(dev);
8098}
8099
55bb9992 8100static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8101{
55bb9992 8102 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8103 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992
ACO		 8104 struct drm_atomic_state *state = crtc_state->base.state;
8105 struct drm_connector_state *connector_state;
d9d444cb 8106 struct intel_encoder *encoder;
55bb9992 8107 int num_connectors = 0, i;
d9d444cb
JB		 8108 bool is_lvds = false;
8109
55bb9992
ACO		 8110 for (i = 0; i < state->num_connector; i++) {
8111 if (!state->connectors[i])
d0737e1d
ACO		 8112 continue;
8113
55bb9992
ACO		 8114 connector_state = state->connector_states[i];
8115 if (connector_state->crtc != crtc_state->base.crtc)
8116 continue;
8117
8118 encoder = to_intel_encoder(connector_state->best_encoder);
8119
d9d444cb
JB		 8120 switch (encoder->type) {
8121 case INTEL_OUTPUT_LVDS:
8122 is_lvds = true;
8123 break;
6847d71b
PZ		 8124 default:
8125 break;
d9d444cb
JB		 8126 }
8127 num_connectors++;
8128 }
8129
8130 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8131 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8132 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8133 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8134 }
8135
8136 return 120000;
8137}
8138
6ff93609 8139static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8140{
c8203565 8141 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8143 int pipe = intel_crtc->pipe;
c8203565
PZ		 8144 uint32_t val;
8145
78114071 8146 val = 0;
c8203565 8147
6e3c9717 8148 switch (intel_crtc->config->pipe_bpp) {
c8203565 8149 case 18:
dfd07d72 8150 val |= PIPECONF_6BPC;
c8203565
PZ		 8151 break;
8152 case 24:
dfd07d72 8153 val |= PIPECONF_8BPC;
c8203565
PZ		 8154 break;
8155 case 30:
dfd07d72 8156 val |= PIPECONF_10BPC;
c8203565
PZ		 8157 break;
8158 case 36:
dfd07d72 8159 val |= PIPECONF_12BPC;
c8203565
PZ		 8160 break;
8161 default:
cc769b62
PZ		 8162 /* Case prevented by intel_choose_pipe_bpp_dither. */
8163 BUG();
c8203565
PZ		 8164 }
8165
6e3c9717 8166 if (intel_crtc->config->dither)
c8203565
PZ		 8167 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8168
6e3c9717 8169 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8170 val |= PIPECONF_INTERLACED_ILK;
8171 else
8172 val |= PIPECONF_PROGRESSIVE;
8173
6e3c9717 8174 if (intel_crtc->config->limited_color_range)
3685a8f3 8175 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8176
c8203565
PZ		 8177 I915_WRITE(PIPECONF(pipe), val);
8178 POSTING_READ(PIPECONF(pipe));
8179}
8180
86d3efce
VS		 8181/*
8182 * Set up the pipe CSC unit.
8183 *
8184 * Currently only full range RGB to limited range RGB conversion
8185 * is supported, but eventually this should handle various
8186 * RGB<->YCbCr scenarios as well.
8187 */
50f3b016 8188static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8189{
8190 struct drm_device *dev = crtc->dev;
8191 struct drm_i915_private *dev_priv = dev->dev_private;
8192 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8193 int pipe = intel_crtc->pipe;
8194 uint16_t coeff = 0x7800; /* 1.0 */
8195
8196 /*
8197 * TODO: Check what kind of values actually come out of the pipe
8198 * with these coeff/postoff values and adjust to get the best
8199 * accuracy. Perhaps we even need to take the bpc value into
8200 * consideration.
8201 */
8202
6e3c9717 8203 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8204 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8205
8206 /*
8207 * GY/GU and RY/RU should be the other way around according
8208 * to BSpec, but reality doesn't agree. Just set them up in
8209 * a way that results in the correct picture.
8210 */
8211 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8212 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8213
8214 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8215 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8216
8217 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8218 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8219
8220 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8221 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8222 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8223
8224 if (INTEL_INFO(dev)->gen > 6) {
8225 uint16_t postoff = 0;
8226
6e3c9717 8227 if (intel_crtc->config->limited_color_range)
32cf0cb0 8228 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8229
8230 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8231 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8232 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8233
8234 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8235 } else {
8236 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8237
6e3c9717 8238 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8239 mode |= CSC_BLACK_SCREEN_OFFSET;
8240
8241 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8242 }
8243}
8244
6ff93609 8245static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8246{
756f85cf
PZ		 8247 struct drm_device *dev = crtc->dev;
8248 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8250 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8251 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8252 uint32_t val;
8253
3eff4faa 8254 val = 0;
ee2b0b38 8255
6e3c9717 8256 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8257 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8258
6e3c9717 8259 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8260 val |= PIPECONF_INTERLACED_ILK;
8261 else
8262 val |= PIPECONF_PROGRESSIVE;
8263
702e7a56
PZ		 8264 I915_WRITE(PIPECONF(cpu_transcoder), val);
8265 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8266
8267 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8268 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8269
3cdf122c 8270 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8271 val = 0;
8272
6e3c9717 8273 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8274 case 18:
8275 val |= PIPEMISC_DITHER_6_BPC;
8276 break;
8277 case 24:
8278 val |= PIPEMISC_DITHER_8_BPC;
8279 break;
8280 case 30:
8281 val |= PIPEMISC_DITHER_10_BPC;
8282 break;
8283 case 36:
8284 val |= PIPEMISC_DITHER_12_BPC;
8285 break;
8286 default:
8287 /* Case prevented by pipe_config_set_bpp. */
8288 BUG();
8289 }
8290
6e3c9717 8291 if (intel_crtc->config->dither)
756f85cf
PZ		 8292 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8293
8294 I915_WRITE(PIPEMISC(pipe), val);
8295 }
ee2b0b38
PZ		 8296}
8297
6591c6e4 8298static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8299 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8300 intel_clock_t *clock,
8301 bool *has_reduced_clock,
8302 intel_clock_t *reduced_clock)
8303{
8304 struct drm_device *dev = crtc->dev;
8305 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8306 int refclk;
d4906093 8307 const intel_limit_t *limit;
a16af721 8308 bool ret, is_lvds = false;
79e53945 8309
a93e255f 8310 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 8311
55bb9992 8312 refclk = ironlake_get_refclk(crtc_state);
79e53945 8313
d4906093
ML		 8314 /*
8315 * Returns a set of divisors for the desired target clock with the given
8316 * refclk, or FALSE. The returned values represent the clock equation:
8317 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8318 */
a93e255f
ACO		 8319 limit = intel_limit(crtc_state, refclk);
8320 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8321 crtc_state->port_clock,
ee9300bb 8322 refclk, NULL, clock);
6591c6e4
PZ		 8323 if (!ret)
8324 return false;
cda4b7d3 8325
ddc9003c 8326 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 8327 /*
8328 * Ensure we match the reduced clock's P to the target clock.
8329 * If the clocks don't match, we can't switch the display clock
8330 * by using the FP0/FP1. In such case we will disable the LVDS
8331 * downclock feature.
8332 */
ee9300bb 8333 *has_reduced_clock =
a93e255f 8334 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV		 8335 dev_priv->lvds_downclock,
8336 refclk, clock,
8337 reduced_clock);
652c393a 8338 }
61e9653f 8339
6591c6e4
PZ		 8340 return true;
8341}
8342
d4b1931c
PZ		 8343int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8344{
8345 /*
8346 * Account for spread spectrum to avoid
8347 * oversubscribing the link. Max center spread
8348 * is 2.5%; use 5% for safety's sake.
8349 */
8350 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8351 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8352}
8353
7429e9d4 8354static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8355{
7429e9d4 8356 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8357}
8358
de13a2e3 8359static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8360 struct intel_crtc_state *crtc_state,
7429e9d4 8361 u32 *fp,
9a7c7890 8362 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8363{
de13a2e3 8364 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8365 struct drm_device *dev = crtc->dev;
8366 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992
ACO		 8367 struct drm_atomic_state *state = crtc_state->base.state;
8368 struct drm_connector_state *connector_state;
8369 struct intel_encoder *encoder;
de13a2e3 8370 uint32_t dpll;
55bb9992 8371 int factor, num_connectors = 0, i;
09ede541 8372 bool is_lvds = false, is_sdvo = false;
79e53945 8373
55bb9992
ACO		 8374 for (i = 0; i < state->num_connector; i++) {
8375 if (!state->connectors[i])
d0737e1d
ACO		 8376 continue;
8377
55bb9992
ACO		 8378 connector_state = state->connector_states[i];
8379 if (connector_state->crtc != crtc_state->base.crtc)
8380 continue;
8381
8382 encoder = to_intel_encoder(connector_state->best_encoder);
8383
8384 switch (encoder->type) {
79e53945
JB		 8385 case INTEL_OUTPUT_LVDS:
8386 is_lvds = true;
8387 break;
8388 case INTEL_OUTPUT_SDVO:
7d57382e 8389 case INTEL_OUTPUT_HDMI:
79e53945 8390 is_sdvo = true;
79e53945 8391 break;
6847d71b
PZ		 8392 default:
8393 break;
79e53945 8394 }
43565a06 8395
c751ce4f 8396 num_connectors++;
79e53945 8397 }
79e53945 8398
c1858123 8399 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8400 factor = 21;
8401 if (is_lvds) {
8402 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8403 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8404 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8405 factor = 25;
190f68c5 8406 } else if (crtc_state->sdvo_tv_clock)
8febb297 8407 factor = 20;
c1858123 8408
190f68c5 8409 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8410 *fp |= FP_CB_TUNE;
2c07245f 8411
9a7c7890
DV		 8412 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8413 *fp2 |= FP_CB_TUNE;
8414
5eddb70b 8415 dpll = 0;
2c07245f 8416
a07d6787
EA		 8417 if (is_lvds)
8418 dpll |= DPLLB_MODE_LVDS;
8419 else
8420 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8421
190f68c5 8422 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8423 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8424
8425 if (is_sdvo)
4a33e48d 8426 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8427 if (crtc_state->has_dp_encoder)
4a33e48d 8428 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8429
a07d6787 8430 /* compute bitmask from p1 value */
190f68c5 8431 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8432 /* also FPA1 */
190f68c5 8433 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8434
190f68c5 8435 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8436 case 5:
8437 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8438 break;
8439 case 7:
8440 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8441 break;
8442 case 10:
8443 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8444 break;
8445 case 14:
8446 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8447 break;
79e53945
JB		 8448 }
8449
b4c09f3b 8450 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8451 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8452 else
8453 dpll |= PLL_REF_INPUT_DREFCLK;
8454
959e16d6 8455 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8456}
8457
190f68c5
ACO		 8458static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8459 struct intel_crtc_state *crtc_state)
de13a2e3 8460{
c7653199 8461 struct drm_device *dev = crtc->base.dev;
de13a2e3 8462 intel_clock_t clock, reduced_clock;
cbbab5bd 8463 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8464 bool ok, has_reduced_clock = false;
8b47047b 8465 bool is_lvds = false;
e2b78267 8466 struct intel_shared_dpll *pll;
de13a2e3 8467
409ee761 8468 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8469
5dc5298b
PZ		 8470 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8471 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8472
190f68c5 8473 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8474 &has_reduced_clock, &reduced_clock);
190f68c5 8475 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8476 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8477 return -EINVAL;
79e53945 8478 }
f47709a9 8479 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8480 if (!crtc_state->clock_set) {
8481 crtc_state->dpll.n = clock.n;
8482 crtc_state->dpll.m1 = clock.m1;
8483 crtc_state->dpll.m2 = clock.m2;
8484 crtc_state->dpll.p1 = clock.p1;
8485 crtc_state->dpll.p2 = clock.p2;
f47709a9 8486 }
79e53945 8487
5dc5298b 8488 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8489 if (crtc_state->has_pch_encoder) {
8490 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8491 if (has_reduced_clock)
7429e9d4 8492 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8493
190f68c5 8494 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8495 &fp, &reduced_clock,
8496 has_reduced_clock ? &fp2 : NULL);
8497
190f68c5
ACO		 8498 crtc_state->dpll_hw_state.dpll = dpll;
8499 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8500 if (has_reduced_clock)
190f68c5 8501 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8502 else
190f68c5 8503 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8504
190f68c5 8505 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8506 if (pll == NULL) {
84f44ce7 8507 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8508 pipe_name(crtc->pipe));
4b645f14
JB		 8509 return -EINVAL;
8510 }
3fb37703 8511 }
79e53945 8512
ab585dea 8513 if (is_lvds && has_reduced_clock)
c7653199 8514 crtc->lowfreq_avail = true;
bcd644e0 8515 else
c7653199 8516 crtc->lowfreq_avail = false;
e2b78267 8517
c8f7a0db 8518 return 0;
79e53945
JB		 8519}
8520
eb14cb74
VS		 8521static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8522 struct intel_link_m_n *m_n)
8523{
8524 struct drm_device *dev = crtc->base.dev;
8525 struct drm_i915_private *dev_priv = dev->dev_private;
8526 enum pipe pipe = crtc->pipe;
8527
8528 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8529 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8530 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8531 & ~TU_SIZE_MASK;
8532 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8533 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8534 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8535}
8536
8537static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8538 enum transcoder transcoder,
b95af8be
VK		 8539 struct intel_link_m_n *m_n,
8540 struct intel_link_m_n *m2_n2)
72419203
DV		 8541{
8542 struct drm_device *dev = crtc->base.dev;
8543 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8544 enum pipe pipe = crtc->pipe;
72419203 8545
eb14cb74
VS		 8546 if (INTEL_INFO(dev)->gen >= 5) {
8547 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8548 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8549 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8550 & ~TU_SIZE_MASK;
8551 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8552 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8553 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8554 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8555 * gen < 8) and if DRRS is supported (to make sure the
8556 * registers are not unnecessarily read).
8557 */
8558 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8559 crtc->config->has_drrs) {
b95af8be
VK		 8560 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8561 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8562 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8563 & ~TU_SIZE_MASK;
8564 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8565 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8566 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8567 }
eb14cb74
VS		 8568 } else {
8569 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8570 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8571 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8572 & ~TU_SIZE_MASK;
8573 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8574 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8575 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8576 }
8577}
8578
8579void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8580 struct intel_crtc_state *pipe_config)
eb14cb74 8581{
681a8504 8582 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8583 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8584 else
8585 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8586 &pipe_config->dp_m_n,
8587 &pipe_config->dp_m2_n2);
eb14cb74 8588}
72419203 8589
eb14cb74 8590static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8591 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8592{
8593 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8594 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8595}
8596
bd2e244f 8597static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8598 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8599{
8600 struct drm_device *dev = crtc->base.dev;
8601 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8602 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8603 uint32_t ps_ctrl = 0;
8604 int id = -1;
8605 int i;
bd2e244f 8606
a1b2278e
CK		 8607 /* find scaler attached to this pipe */
8608 for (i = 0; i < crtc->num_scalers; i++) {
8609 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8610 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8611 id = i;
8612 pipe_config->pch_pfit.enabled = true;
8613 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8614 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8615 break;
8616 }
8617 }
bd2e244f 8618
a1b2278e
CK		 8619 scaler_state->scaler_id = id;
8620 if (id >= 0) {
8621 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8622 } else {
8623 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8624 }
8625}
8626
5724dbd1
DL		 8627static void
8628skylake_get_initial_plane_config(struct intel_crtc *crtc,
8629 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8630{
8631 struct drm_device *dev = crtc->base.dev;
8632 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8633 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8634 int pipe = crtc->pipe;
8635 int fourcc, pixel_format;
6761dd31 8636 unsigned int aligned_height;
bc8d7dff 8637 struct drm_framebuffer *fb;
1b842c89 8638 struct intel_framebuffer *intel_fb;
bc8d7dff 8639
d9806c9f 8640 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8641 if (!intel_fb) {
bc8d7dff
DL		 8642 DRM_DEBUG_KMS("failed to alloc fb\n");
8643 return;
8644 }
8645
1b842c89
DL		 8646 fb = &intel_fb->base;
8647
bc8d7dff 8648 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 8649 if (!(val & PLANE_CTL_ENABLE))
8650 goto error;
8651
bc8d7dff
DL		 8652 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8653 fourcc = skl_format_to_fourcc(pixel_format,
8654 val & PLANE_CTL_ORDER_RGBX,
8655 val & PLANE_CTL_ALPHA_MASK);
8656 fb->pixel_format = fourcc;
8657 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8658
40f46283
DL		 8659 tiling = val & PLANE_CTL_TILED_MASK;
8660 switch (tiling) {
8661 case PLANE_CTL_TILED_LINEAR:
8662 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8663 break;
8664 case PLANE_CTL_TILED_X:
8665 plane_config->tiling = I915_TILING_X;
8666 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8667 break;
8668 case PLANE_CTL_TILED_Y:
8669 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8670 break;
8671 case PLANE_CTL_TILED_YF:
8672 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8673 break;
8674 default:
8675 MISSING_CASE(tiling);
8676 goto error;
8677 }
8678
bc8d7dff
DL		 8679 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8680 plane_config->base = base;
8681
8682 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8683
8684 val = I915_READ(PLANE_SIZE(pipe, 0));
8685 fb->height = ((val >> 16) & 0xfff) + 1;
8686 fb->width = ((val >> 0) & 0x1fff) + 1;
8687
8688 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 8689 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8690 fb->pixel_format);
bc8d7dff
DL		 8691 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8692
8693 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8694 fb->pixel_format,
8695 fb->modifier[0]);
bc8d7dff 8696
f37b5c2b 8697 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 8698
8699 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8700 pipe_name(pipe), fb->width, fb->height,
8701 fb->bits_per_pixel, base, fb->pitches[0],
8702 plane_config->size);
8703
2d14030b 8704 plane_config->fb = intel_fb;
bc8d7dff
DL		 8705 return;
8706
8707error:
8708 kfree(fb);
8709}
8710
2fa2fe9a 8711static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8712 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 8713{
8714 struct drm_device *dev = crtc->base.dev;
8715 struct drm_i915_private *dev_priv = dev->dev_private;
8716 uint32_t tmp;
8717
8718 tmp = I915_READ(PF_CTL(crtc->pipe));
8719
8720 if (tmp & PF_ENABLE) {
fd4daa9c 8721 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 8722 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8723 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 8724
8725 /* We currently do not free assignements of panel fitters on
8726 * ivb/hsw (since we don't use the higher upscaling modes which
8727 * differentiates them) so just WARN about this case for now. */
8728 if (IS_GEN7(dev)) {
8729 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8730 PF_PIPE_SEL_IVB(crtc->pipe));
8731 }
2fa2fe9a 8732 }
79e53945
JB		 8733}
8734
5724dbd1
DL		 8735static void
8736ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8737 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 8738{
8739 struct drm_device *dev = crtc->base.dev;
8740 struct drm_i915_private *dev_priv = dev->dev_private;
8741 u32 val, base, offset;
aeee5a49 8742 int pipe = crtc->pipe;
4c6baa59 8743 int fourcc, pixel_format;
6761dd31 8744 unsigned int aligned_height;
b113d5ee 8745 struct drm_framebuffer *fb;
1b842c89 8746 struct intel_framebuffer *intel_fb;
4c6baa59 8747
42a7b088
DL		 8748 val = I915_READ(DSPCNTR(pipe));
8749 if (!(val & DISPLAY_PLANE_ENABLE))
8750 return;
8751
d9806c9f 8752 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8753 if (!intel_fb) {
4c6baa59
JB		 8754 DRM_DEBUG_KMS("failed to alloc fb\n");
8755 return;
8756 }
8757
1b842c89
DL		 8758 fb = &intel_fb->base;
8759
18c5247e
DV		 8760 if (INTEL_INFO(dev)->gen >= 4) {
8761 if (val & DISPPLANE_TILED) {
49af449b 8762 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8763 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8764 }
8765 }
4c6baa59
JB		 8766
8767 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8768 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8769 fb->pixel_format = fourcc;
8770 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 8771
aeee5a49 8772 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 8773 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 8774 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 8775 } else {
49af449b 8776 if (plane_config->tiling)
aeee5a49 8777 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 8778 else
aeee5a49 8779 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 8780 }
8781 plane_config->base = base;
8782
8783 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8784 fb->width = ((val >> 16) & 0xfff) + 1;
8785 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 8786
8787 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8788 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 8789
b113d5ee 8790 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8791 fb->pixel_format,
8792 fb->modifier[0]);
4c6baa59 8793
f37b5c2b 8794 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 8795
2844a921
DL		 8796 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8797 pipe_name(pipe), fb->width, fb->height,
8798 fb->bits_per_pixel, base, fb->pitches[0],
8799 plane_config->size);
b113d5ee 8800
2d14030b 8801 plane_config->fb = intel_fb;
4c6baa59
JB		 8802}
8803
0e8ffe1b 8804static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8805 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8806{
8807 struct drm_device *dev = crtc->base.dev;
8808 struct drm_i915_private *dev_priv = dev->dev_private;
8809 uint32_t tmp;
8810
f458ebbc
DV		 8811 if (!intel_display_power_is_enabled(dev_priv,
8812 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 8813 return false;
8814
e143a21c 8815 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8816 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8817
0e8ffe1b
DV		 8818 tmp = I915_READ(PIPECONF(crtc->pipe));
8819 if (!(tmp & PIPECONF_ENABLE))
8820 return false;
8821
42571aef
VS		 8822 switch (tmp & PIPECONF_BPC_MASK) {
8823 case PIPECONF_6BPC:
8824 pipe_config->pipe_bpp = 18;
8825 break;
8826 case PIPECONF_8BPC:
8827 pipe_config->pipe_bpp = 24;
8828 break;
8829 case PIPECONF_10BPC:
8830 pipe_config->pipe_bpp = 30;
8831 break;
8832 case PIPECONF_12BPC:
8833 pipe_config->pipe_bpp = 36;
8834 break;
8835 default:
8836 break;
8837 }
8838
b5a9fa09
DV		 8839 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8840 pipe_config->limited_color_range = true;
8841
ab9412ba 8842 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 8843 struct intel_shared_dpll *pll;
8844
88adfff1
DV		 8845 pipe_config->has_pch_encoder = true;
8846
627eb5a3
DV		 8847 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8848 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8849 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 8850
8851 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 8852
c0d43d62 8853 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 8854 pipe_config->shared_dpll =
8855 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 8856 } else {
8857 tmp = I915_READ(PCH_DPLL_SEL);
8858 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8859 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8860 else
8861 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8862 }
66e985c0
DV		 8863
8864 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8865
8866 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8867 &pipe_config->dpll_hw_state));
c93f54cf
DV		 8868
8869 tmp = pipe_config->dpll_hw_state.dpll;
8870 pipe_config->pixel_multiplier =
8871 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8872 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 8873
8874 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 8875 } else {
8876 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 8877 }
8878
1bd1bd80
DV		 8879 intel_get_pipe_timings(crtc, pipe_config);
8880
2fa2fe9a
DV		 8881 ironlake_get_pfit_config(crtc, pipe_config);
8882
0e8ffe1b
DV		 8883 return true;
8884}
8885
be256dc7
PZ		 8886static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8887{
8888 struct drm_device *dev = dev_priv->dev;
be256dc7 8889 struct intel_crtc *crtc;
be256dc7 8890
d3fcc808 8891 for_each_intel_crtc(dev, crtc)
e2c719b7 8892 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 8893 pipe_name(crtc->pipe));
8894
e2c719b7
RC		 8895 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8896 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8897 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8898 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8899 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8900 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 8901 "CPU PWM1 enabled\n");
c5107b87 8902 if (IS_HASWELL(dev))
e2c719b7 8903 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 8904 "CPU PWM2 enabled\n");
e2c719b7 8905 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 8906 "PCH PWM1 enabled\n");
e2c719b7 8907 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 8908 "Utility pin enabled\n");
e2c719b7 8909 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 8910
9926ada1
PZ		 8911 /*
8912 * In theory we can still leave IRQs enabled, as long as only the HPD
8913 * interrupts remain enabled. We used to check for that, but since it's
8914 * gen-specific and since we only disable LCPLL after we fully disable
8915 * the interrupts, the check below should be enough.
8916 */
e2c719b7 8917 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 8918}
8919
9ccd5aeb
PZ		 8920static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8921{
8922 struct drm_device *dev = dev_priv->dev;
8923
8924 if (IS_HASWELL(dev))
8925 return I915_READ(D_COMP_HSW);
8926 else
8927 return I915_READ(D_COMP_BDW);
8928}
8929
3c4c9b81
PZ		 8930static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8931{
8932 struct drm_device *dev = dev_priv->dev;
8933
8934 if (IS_HASWELL(dev)) {
8935 mutex_lock(&dev_priv->rps.hw_lock);
8936 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8937 val))
f475dadf 8938 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 8939 mutex_unlock(&dev_priv->rps.hw_lock);
8940 } else {
9ccd5aeb
PZ		 8941 I915_WRITE(D_COMP_BDW, val);
8942 POSTING_READ(D_COMP_BDW);
3c4c9b81 8943 }
be256dc7
PZ		 8944}
8945
8946/*
8947 * This function implements pieces of two sequences from BSpec:
8948 * - Sequence for display software to disable LCPLL
8949 * - Sequence for display software to allow package C8+
8950 * The steps implemented here are just the steps that actually touch the LCPLL
8951 * register. Callers should take care of disabling all the display engine
8952 * functions, doing the mode unset, fixing interrupts, etc.
8953 */
6ff58d53
PZ		 8954static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8955 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 8956{
8957 uint32_t val;
8958
8959 assert_can_disable_lcpll(dev_priv);
8960
8961 val = I915_READ(LCPLL_CTL);
8962
8963 if (switch_to_fclk) {
8964 val |= LCPLL_CD_SOURCE_FCLK;
8965 I915_WRITE(LCPLL_CTL, val);
8966
8967 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8968 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8969 DRM_ERROR("Switching to FCLK failed\n");
8970
8971 val = I915_READ(LCPLL_CTL);
8972 }
8973
8974 val |= LCPLL_PLL_DISABLE;
8975 I915_WRITE(LCPLL_CTL, val);
8976 POSTING_READ(LCPLL_CTL);
8977
8978 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8979 DRM_ERROR("LCPLL still locked\n");
8980
9ccd5aeb 8981 val = hsw_read_dcomp(dev_priv);
be256dc7 8982 val |= D_COMP_COMP_DISABLE;
3c4c9b81 8983 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 8984 ndelay(100);
8985
9ccd5aeb
PZ		 8986 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8987 1))
be256dc7
PZ		 8988 DRM_ERROR("D_COMP RCOMP still in progress\n");
8989
8990 if (allow_power_down) {
8991 val = I915_READ(LCPLL_CTL);
8992 val |= LCPLL_POWER_DOWN_ALLOW;
8993 I915_WRITE(LCPLL_CTL, val);
8994 POSTING_READ(LCPLL_CTL);
8995 }
8996}
8997
8998/*
8999 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9000 * source.
9001 */
6ff58d53 9002static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9003{
9004 uint32_t val;
9005
9006 val = I915_READ(LCPLL_CTL);
9007
9008 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9009 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9010 return;
9011
a8a8bd54
PZ		 9012 /*
9013 * Make sure we're not on PC8 state before disabling PC8, otherwise
9014 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9015 */
59bad947 9016 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9017
be256dc7
PZ		 9018 if (val & LCPLL_POWER_DOWN_ALLOW) {
9019 val &= ~LCPLL_POWER_DOWN_ALLOW;
9020 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9021 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9022 }
9023
9ccd5aeb 9024 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9025 val |= D_COMP_COMP_FORCE;
9026 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9027 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9028
9029 val = I915_READ(LCPLL_CTL);
9030 val &= ~LCPLL_PLL_DISABLE;
9031 I915_WRITE(LCPLL_CTL, val);
9032
9033 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9034 DRM_ERROR("LCPLL not locked yet\n");
9035
9036 if (val & LCPLL_CD_SOURCE_FCLK) {
9037 val = I915_READ(LCPLL_CTL);
9038 val &= ~LCPLL_CD_SOURCE_FCLK;
9039 I915_WRITE(LCPLL_CTL, val);
9040
9041 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9042 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9043 DRM_ERROR("Switching back to LCPLL failed\n");
9044 }
215733fa 9045
59bad947 9046 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
be256dc7
PZ		 9047}
9048
765dab67
PZ		 9049/*
9050 * Package states C8 and deeper are really deep PC states that can only be
9051 * reached when all the devices on the system allow it, so even if the graphics
9052 * device allows PC8+, it doesn't mean the system will actually get to these
9053 * states. Our driver only allows PC8+ when going into runtime PM.
9054 *
9055 * The requirements for PC8+ are that all the outputs are disabled, the power
9056 * well is disabled and most interrupts are disabled, and these are also
9057 * requirements for runtime PM. When these conditions are met, we manually do
9058 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9059 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9060 * hang the machine.
9061 *
9062 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9063 * the state of some registers, so when we come back from PC8+ we need to
9064 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9065 * need to take care of the registers kept by RC6. Notice that this happens even
9066 * if we don't put the device in PCI D3 state (which is what currently happens
9067 * because of the runtime PM support).
9068 *
9069 * For more, read "Display Sequences for Package C8" on the hardware
9070 * documentation.
9071 */
a14cb6fc 9072void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9073{
c67a470b
PZ		 9074 struct drm_device *dev = dev_priv->dev;
9075 uint32_t val;
9076
c67a470b
PZ		 9077 DRM_DEBUG_KMS("Enabling package C8+\n");
9078
c67a470b
PZ		 9079 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9080 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9081 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9082 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9083 }
9084
9085 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9086 hsw_disable_lcpll(dev_priv, true, true);
9087}
9088
a14cb6fc 9089void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9090{
9091 struct drm_device *dev = dev_priv->dev;
9092 uint32_t val;
9093
c67a470b
PZ		 9094 DRM_DEBUG_KMS("Disabling package C8+\n");
9095
9096 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9097 lpt_init_pch_refclk(dev);
9098
9099 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9100 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9101 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9102 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9103 }
9104
9105 intel_prepare_ddi(dev);
c67a470b
PZ		 9106}
9107
f8437dd1
VK		 9108static void broxton_modeset_global_resources(struct drm_atomic_state *state)
9109{
9110 struct drm_device *dev = state->dev;
9111 struct drm_i915_private *dev_priv = dev->dev_private;
9112 int max_pixclk = intel_mode_max_pixclk(state);
9113 int req_cdclk;
9114
9115 /* see the comment in valleyview_modeset_global_resources */
9116 if (WARN_ON(max_pixclk < 0))
9117 return;
9118
9119 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9120
9121 if (req_cdclk != dev_priv->cdclk_freq)
9122 broxton_set_cdclk(dev, req_cdclk);
9123}
9124
190f68c5
ACO		 9125static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9126 struct intel_crtc_state *crtc_state)
09b4ddf9 9127{
190f68c5 9128 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9129 return -EINVAL;
716c2e55 9130
c7653199 9131 crtc->lowfreq_avail = false;
644cef34 9132
c8f7a0db 9133 return 0;
79e53945
JB		 9134}
9135
3760b59c
S		 9136static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9137 enum port port,
9138 struct intel_crtc_state *pipe_config)
9139{
9140 switch (port) {
9141 case PORT_A:
9142 pipe_config->ddi_pll_sel = SKL_DPLL0;
9143 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9144 break;
9145 case PORT_B:
9146 pipe_config->ddi_pll_sel = SKL_DPLL1;
9147 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9148 break;
9149 case PORT_C:
9150 pipe_config->ddi_pll_sel = SKL_DPLL2;
9151 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9152 break;
9153 default:
9154 DRM_ERROR("Incorrect port type\n");
9155 }
9156}
9157
96b7dfb7
S		 9158static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9159 enum port port,
5cec258b 9160 struct intel_crtc_state *pipe_config)
96b7dfb7 9161{
3148ade7 9162 u32 temp, dpll_ctl1;
96b7dfb7
S		 9163
9164 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9165 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9166
9167 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9168 case SKL_DPLL0:
9169 /*
9170 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9171 * of the shared DPLL framework and thus needs to be read out
9172 * separately
9173 */
9174 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9175 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9176 break;
96b7dfb7
S		 9177 case SKL_DPLL1:
9178 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9179 break;
9180 case SKL_DPLL2:
9181 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9182 break;
9183 case SKL_DPLL3:
9184 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9185 break;
96b7dfb7
S		 9186 }
9187}
9188
7d2c8175
DL		 9189static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9190 enum port port,
5cec258b 9191 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9192{
9193 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9194
9195 switch (pipe_config->ddi_pll_sel) {
9196 case PORT_CLK_SEL_WRPLL1:
9197 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9198 break;
9199 case PORT_CLK_SEL_WRPLL2:
9200 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9201 break;
9202 }
9203}
9204
26804afd 9205static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9206 struct intel_crtc_state *pipe_config)
26804afd
DV		 9207{
9208 struct drm_device *dev = crtc->base.dev;
9209 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9210 struct intel_shared_dpll *pll;
26804afd
DV		 9211 enum port port;
9212 uint32_t tmp;
9213
9214 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9215
9216 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9217
96b7dfb7
S		 9218 if (IS_SKYLAKE(dev))
9219 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9220 else if (IS_BROXTON(dev))
9221 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9222 else
9223 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9224
d452c5b6
DV		 9225 if (pipe_config->shared_dpll >= 0) {
9226 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9227
9228 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9229 &pipe_config->dpll_hw_state));
9230 }
9231
26804afd
DV		 9232 /*
9233 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9234 * DDI E. So just check whether this pipe is wired to DDI E and whether
9235 * the PCH transcoder is on.
9236 */
ca370455
DL		 9237 if (INTEL_INFO(dev)->gen < 9 &&
9238 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9239 pipe_config->has_pch_encoder = true;
9240
9241 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9242 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9243 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9244
9245 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9246 }
9247}
9248
0e8ffe1b 9249static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9250 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9251{
9252 struct drm_device *dev = crtc->base.dev;
9253 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9254 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9255 uint32_t tmp;
9256
f458ebbc 9257 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9258 POWER_DOMAIN_PIPE(crtc->pipe)))
9259 return false;
9260
e143a21c 9261 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9262 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9263
eccb140b
DV		 9264 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9265 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9266 enum pipe trans_edp_pipe;
9267 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9268 default:
9269 WARN(1, "unknown pipe linked to edp transcoder\n");
9270 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9271 case TRANS_DDI_EDP_INPUT_A_ON:
9272 trans_edp_pipe = PIPE_A;
9273 break;
9274 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9275 trans_edp_pipe = PIPE_B;
9276 break;
9277 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9278 trans_edp_pipe = PIPE_C;
9279 break;
9280 }
9281
9282 if (trans_edp_pipe == crtc->pipe)
9283 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9284 }
9285
f458ebbc 9286 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9287 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9288 return false;
9289
eccb140b 9290 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9291 if (!(tmp & PIPECONF_ENABLE))
9292 return false;
9293
26804afd 9294 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9295
1bd1bd80
DV		 9296 intel_get_pipe_timings(crtc, pipe_config);
9297
a1b2278e
CK		 9298 if (INTEL_INFO(dev)->gen >= 9) {
9299 skl_init_scalers(dev, crtc, pipe_config);
9300 }
9301
2fa2fe9a 9302 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
bd2e244f 9303 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9304 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9305 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9306 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9307 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9308 else
9309 MISSING_CASE(INTEL_INFO(dev)->gen);
9310
a1b2278e
CK		 9311 } else {
9312 pipe_config->scaler_state.scaler_id = -1;
9313 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f 9314 }
88adfff1 9315
e59150dc
JB		 9316 if (IS_HASWELL(dev))
9317 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9318 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9319
ebb69c95
CT		 9320 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9321 pipe_config->pixel_multiplier =
9322 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9323 } else {
9324 pipe_config->pixel_multiplier = 1;
9325 }
6c49f241 9326
0e8ffe1b
DV		 9327 return true;
9328}
9329
560b85bb
CW		 9330static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9331{
9332 struct drm_device *dev = crtc->dev;
9333 struct drm_i915_private *dev_priv = dev->dev_private;
9334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9335 uint32_t cntl = 0, size = 0;
560b85bb 9336
dc41c154 9337 if (base) {
3dd512fb
MR		 9338 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9339 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9340 unsigned int stride = roundup_pow_of_two(width) * 4;
9341
9342 switch (stride) {
9343 default:
9344 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9345 width, stride);
9346 stride = 256;
9347 /* fallthrough */
9348 case 256:
9349 case 512:
9350 case 1024:
9351 case 2048:
9352 break;
4b0e333e
CW		 9353 }
9354
dc41c154
VS		 9355 cntl |= CURSOR_ENABLE |
9356 CURSOR_GAMMA_ENABLE |
9357 CURSOR_FORMAT_ARGB |
9358 CURSOR_STRIDE(stride);
9359
9360 size = (height << 12) | width;
4b0e333e 9361 }
560b85bb 9362
dc41c154
VS		 9363 if (intel_crtc->cursor_cntl != 0 &&
9364 (intel_crtc->cursor_base != base ||
9365 intel_crtc->cursor_size != size ||
9366 intel_crtc->cursor_cntl != cntl)) {
9367 /* On these chipsets we can only modify the base/size/stride
9368 * whilst the cursor is disabled.
9369 */
9370 I915_WRITE(_CURACNTR, 0);
4b0e333e 9371 POSTING_READ(_CURACNTR);
dc41c154 9372 intel_crtc->cursor_cntl = 0;
4b0e333e 9373 }
560b85bb 9374
99d1f387 9375 if (intel_crtc->cursor_base != base) {
9db4a9c7 9376 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9377 intel_crtc->cursor_base = base;
9378 }
4726e0b0 9379
dc41c154
VS		 9380 if (intel_crtc->cursor_size != size) {
9381 I915_WRITE(CURSIZE, size);
9382 intel_crtc->cursor_size = size;
4b0e333e 9383 }
560b85bb 9384
4b0e333e 9385 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9386 I915_WRITE(_CURACNTR, cntl);
9387 POSTING_READ(_CURACNTR);
4b0e333e 9388 intel_crtc->cursor_cntl = cntl;
560b85bb 9389 }
560b85bb
CW		 9390}
9391
560b85bb 9392static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9393{
9394 struct drm_device *dev = crtc->dev;
9395 struct drm_i915_private *dev_priv = dev->dev_private;
9396 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9397 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9398 uint32_t cntl;
9399
9400 cntl = 0;
9401 if (base) {
9402 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9403 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9404 case 64:
9405 cntl |= CURSOR_MODE_64_ARGB_AX;
9406 break;
9407 case 128:
9408 cntl |= CURSOR_MODE_128_ARGB_AX;
9409 break;
9410 case 256:
9411 cntl |= CURSOR_MODE_256_ARGB_AX;
9412 break;
9413 default:
3dd512fb 9414 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9415 return;
65a21cd6 9416 }
4b0e333e 9417 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9418
9419 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9420 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9421 }
65a21cd6 9422
8e7d688b 9423 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9424 cntl |= CURSOR_ROTATE_180;
9425
4b0e333e
CW		 9426 if (intel_crtc->cursor_cntl != cntl) {
9427 I915_WRITE(CURCNTR(pipe), cntl);
9428 POSTING_READ(CURCNTR(pipe));
9429 intel_crtc->cursor_cntl = cntl;
65a21cd6 9430 }
4b0e333e 9431
65a21cd6 9432 /* and commit changes on next vblank */
5efb3e28
VS		 9433 I915_WRITE(CURBASE(pipe), base);
9434 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9435
9436 intel_crtc->cursor_base = base;
65a21cd6
JB		 9437}
9438
cda4b7d3 9439/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9440static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9441 bool on)
cda4b7d3
CW		 9442{
9443 struct drm_device *dev = crtc->dev;
9444 struct drm_i915_private *dev_priv = dev->dev_private;
9445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9446 int pipe = intel_crtc->pipe;
3d7d6510
MR		 9447 int x = crtc->cursor_x;
9448 int y = crtc->cursor_y;
d6e4db15 9449 u32 base = 0, pos = 0;
cda4b7d3 9450
d6e4db15 9451 if (on)
cda4b7d3 9452 base = intel_crtc->cursor_addr;
cda4b7d3 9453
6e3c9717 9454 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9455 base = 0;
9456
6e3c9717 9457 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9458 base = 0;
9459
9460 if (x < 0) {
3dd512fb 9461 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 9462 base = 0;
9463
9464 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9465 x = -x;
9466 }
9467 pos |= x << CURSOR_X_SHIFT;
9468
9469 if (y < 0) {
3dd512fb 9470 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 9471 base = 0;
9472
9473 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9474 y = -y;
9475 }
9476 pos |= y << CURSOR_Y_SHIFT;
9477
4b0e333e 9478 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9479 return;
9480
5efb3e28
VS		 9481 I915_WRITE(CURPOS(pipe), pos);
9482
4398ad45
VS		 9483 /* ILK+ do this automagically */
9484 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9485 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 9486 base += (intel_crtc->base.cursor->state->crtc_h *
9487 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 9488 }
9489
8ac54669 9490 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9491 i845_update_cursor(crtc, base);
9492 else
9493 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9494}
9495
dc41c154
VS		 9496static bool cursor_size_ok(struct drm_device *dev,
9497 uint32_t width, uint32_t height)
9498{
9499 if (width == 0 || height == 0)
9500 return false;
9501
9502 /*
9503 * 845g/865g are special in that they are only limited by
9504 * the width of their cursors, the height is arbitrary up to
9505 * the precision of the register. Everything else requires
9506 * square cursors, limited to a few power-of-two sizes.
9507 */
9508 if (IS_845G(dev) || IS_I865G(dev)) {
9509 if ((width & 63) != 0)
9510 return false;
9511
9512 if (width > (IS_845G(dev) ? 64 : 512))
9513 return false;
9514
9515 if (height > 1023)
9516 return false;
9517 } else {
9518 switch (width | height) {
9519 case 256:
9520 case 128:
9521 if (IS_GEN2(dev))
9522 return false;
9523 case 64:
9524 break;
9525 default:
9526 return false;
9527 }
9528 }
9529
9530 return true;
9531}
9532
79e53945 9533static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 9534 u16 *blue, uint32_t start, uint32_t size)
79e53945 9535{
7203425a 9536 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 9537 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 9538
7203425a 9539 for (i = start; i < end; i++) {
79e53945
JB		 9540 intel_crtc->lut_r[i] = red[i] >> 8;
9541 intel_crtc->lut_g[i] = green[i] >> 8;
9542 intel_crtc->lut_b[i] = blue[i] >> 8;
9543 }
9544
9545 intel_crtc_load_lut(crtc);
9546}
9547
79e53945
JB		 9548/* VESA 640x480x72Hz mode to set on the pipe */
9549static struct drm_display_mode load_detect_mode = {
9550 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9551 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9552};
9553
a8bb6818
DV		 9554struct drm_framebuffer *
9555__intel_framebuffer_create(struct drm_device *dev,
9556 struct drm_mode_fb_cmd2 *mode_cmd,
9557 struct drm_i915_gem_object *obj)
d2dff872
CW		 9558{
9559 struct intel_framebuffer *intel_fb;
9560 int ret;
9561
9562 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9563 if (!intel_fb) {
6ccb81f2 9564 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 9565 return ERR_PTR(-ENOMEM);
9566 }
9567
9568 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 9569 if (ret)
9570 goto err;
d2dff872
CW		 9571
9572 return &intel_fb->base;
dd4916c5 9573err:
6ccb81f2 9574 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 9575 kfree(intel_fb);
9576
9577 return ERR_PTR(ret);
d2dff872
CW		 9578}
9579
b5ea642a 9580static struct drm_framebuffer *
a8bb6818
DV		 9581intel_framebuffer_create(struct drm_device *dev,
9582 struct drm_mode_fb_cmd2 *mode_cmd,
9583 struct drm_i915_gem_object *obj)
9584{
9585 struct drm_framebuffer *fb;
9586 int ret;
9587
9588 ret = i915_mutex_lock_interruptible(dev);
9589 if (ret)
9590 return ERR_PTR(ret);
9591 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9592 mutex_unlock(&dev->struct_mutex);
9593
9594 return fb;
9595}
9596
d2dff872
CW		 9597static u32
9598intel_framebuffer_pitch_for_width(int width, int bpp)
9599{
9600 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9601 return ALIGN(pitch, 64);
9602}
9603
9604static u32
9605intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9606{
9607 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 9608 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 9609}
9610
9611static struct drm_framebuffer *
9612intel_framebuffer_create_for_mode(struct drm_device *dev,
9613 struct drm_display_mode *mode,
9614 int depth, int bpp)
9615{
9616 struct drm_i915_gem_object *obj;
0fed39bd 9617 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 9618
9619 obj = i915_gem_alloc_object(dev,
9620 intel_framebuffer_size_for_mode(mode, bpp));
9621 if (obj == NULL)
9622 return ERR_PTR(-ENOMEM);
9623
9624 mode_cmd.width = mode->hdisplay;
9625 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 9626 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9627 bpp);
5ca0c34a 9628 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 9629
9630 return intel_framebuffer_create(dev, &mode_cmd, obj);
9631}
9632
9633static struct drm_framebuffer *
9634mode_fits_in_fbdev(struct drm_device *dev,
9635 struct drm_display_mode *mode)
9636{
4520f53a 9637#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 9638 struct drm_i915_private *dev_priv = dev->dev_private;
9639 struct drm_i915_gem_object *obj;
9640 struct drm_framebuffer *fb;
9641
4c0e5528 9642 if (!dev_priv->fbdev)
d2dff872
CW		 9643 return NULL;
9644
4c0e5528 9645 if (!dev_priv->fbdev->fb)
d2dff872
CW		 9646 return NULL;
9647
4c0e5528
DV		 9648 obj = dev_priv->fbdev->fb->obj;
9649 BUG_ON(!obj);
9650
8bcd4553 9651 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 9652 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9653 fb->bits_per_pixel))
d2dff872
CW		 9654 return NULL;
9655
01f2c773 9656 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 9657 return NULL;
9658
9659 return fb;
4520f53a
DV		 9660#else
9661 return NULL;
9662#endif
d2dff872
CW		 9663}
9664
d2434ab7 9665bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 9666 struct drm_display_mode *mode,
51fd371b
RC		 9667 struct intel_load_detect_pipe *old,
9668 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 9669{
9670 struct intel_crtc *intel_crtc;
d2434ab7
DV		 9671 struct intel_encoder *intel_encoder =
9672 intel_attached_encoder(connector);
79e53945 9673 struct drm_crtc *possible_crtc;
4ef69c7a 9674 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 9675 struct drm_crtc *crtc = NULL;
9676 struct drm_device *dev = encoder->dev;
94352cf9 9677 struct drm_framebuffer *fb;
51fd371b 9678 struct drm_mode_config *config = &dev->mode_config;
83a57153 9679 struct drm_atomic_state *state = NULL;
944b0c76 9680 struct drm_connector_state *connector_state;
51fd371b 9681 int ret, i = -1;
79e53945 9682
d2dff872 9683 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9684 connector->base.id, connector->name,
8e329a03 9685 encoder->base.id, encoder->name);
d2dff872 9686
51fd371b
RC		 9687retry:
9688 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9689 if (ret)
9690 goto fail_unlock;
6e9f798d 9691
79e53945
JB		 9692 /*
9693 * Algorithm gets a little messy:
7a5e4805 9694 *
79e53945
JB		 9695 * - if the connector already has an assigned crtc, use it (but make
9696 * sure it's on first)
7a5e4805 9697 *
79e53945
JB		 9698 * - try to find the first unused crtc that can drive this connector,
9699 * and use that if we find one
79e53945
JB		 9700 */
9701
9702 /* See if we already have a CRTC for this connector */
9703 if (encoder->crtc) {
9704 crtc = encoder->crtc;
8261b191 9705
51fd371b 9706 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 9707 if (ret)
9708 goto fail_unlock;
9709 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 9710 if (ret)
9711 goto fail_unlock;
7b24056b 9712
24218aac 9713 old->dpms_mode = connector->dpms;
8261b191
CW		 9714 old->load_detect_temp = false;
9715
9716 /* Make sure the crtc and connector are running */
24218aac
DV		 9717 if (connector->dpms != DRM_MODE_DPMS_ON)
9718 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 9719
7173188d 9720 return true;
79e53945
JB		 9721 }
9722
9723 /* Find an unused one (if possible) */
70e1e0ec 9724 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 9725 i++;
9726 if (!(encoder->possible_crtcs & (1 << i)))
9727 continue;
83d65738 9728 if (possible_crtc->state->enable)
a459249c
VS		 9729 continue;
9730 /* This can occur when applying the pipe A quirk on resume. */
9731 if (to_intel_crtc(possible_crtc)->new_enabled)
9732 continue;
9733
9734 crtc = possible_crtc;
9735 break;
79e53945
JB		 9736 }
9737
9738 /*
9739 * If we didn't find an unused CRTC, don't use any.
9740 */
9741 if (!crtc) {
7173188d 9742 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 9743 goto fail_unlock;
79e53945
JB		 9744 }
9745
51fd371b
RC		 9746 ret = drm_modeset_lock(&crtc->mutex, ctx);
9747 if (ret)
4d02e2de
DV		 9748 goto fail_unlock;
9749 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9750 if (ret)
51fd371b 9751 goto fail_unlock;
fc303101
DV		 9752 intel_encoder->new_crtc = to_intel_crtc(crtc);
9753 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 9754
9755 intel_crtc = to_intel_crtc(crtc);
412b61d8 9756 intel_crtc->new_enabled = true;
24218aac 9757 old->dpms_mode = connector->dpms;
8261b191 9758 old->load_detect_temp = true;
d2dff872 9759 old->release_fb = NULL;
79e53945 9760
83a57153
ACO		 9761 state = drm_atomic_state_alloc(dev);
9762 if (!state)
9763 return false;
9764
9765 state->acquire_ctx = ctx;
9766
944b0c76
ACO		 9767 connector_state = drm_atomic_get_connector_state(state, connector);
9768 if (IS_ERR(connector_state)) {
9769 ret = PTR_ERR(connector_state);
9770 goto fail;
9771 }
9772
9773 connector_state->crtc = crtc;
9774 connector_state->best_encoder = &intel_encoder->base;
9775
6492711d
CW		 9776 if (!mode)
9777 mode = &load_detect_mode;
79e53945 9778
d2dff872
CW		 9779 /* We need a framebuffer large enough to accommodate all accesses
9780 * that the plane may generate whilst we perform load detection.
9781 * We can not rely on the fbcon either being present (we get called
9782 * during its initialisation to detect all boot displays, or it may
9783 * not even exist) or that it is large enough to satisfy the
9784 * requested mode.
9785 */
94352cf9
DV		 9786 fb = mode_fits_in_fbdev(dev, mode);
9787 if (fb == NULL) {
d2dff872 9788 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 9789 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9790 old->release_fb = fb;
d2dff872
CW		 9791 } else
9792 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 9793 if (IS_ERR(fb)) {
d2dff872 9794 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 9795 goto fail;
79e53945 9796 }
79e53945 9797
83a57153 9798 if (intel_set_mode(crtc, mode, 0, 0, fb, state)) {
6492711d 9799 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 9800 if (old->release_fb)
9801 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 9802 goto fail;
79e53945 9803 }
9128b040 9804 crtc->primary->crtc = crtc;
7173188d 9805
79e53945 9806 /* let the connector get through one full cycle before testing */
9d0498a2 9807 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 9808 return true;
412b61d8
VS		 9809
9810 fail:
83d65738 9811 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 9812fail_unlock:
83a57153
ACO		 9813 if (state) {
9814 drm_atomic_state_free(state);
9815 state = NULL;
9816 }
9817
51fd371b
RC		 9818 if (ret == -EDEADLK) {
9819 drm_modeset_backoff(ctx);
9820 goto retry;
9821 }
9822
412b61d8 9823 return false;
79e53945
JB		 9824}
9825
d2434ab7 9826void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 9827 struct intel_load_detect_pipe *old,
9828 struct drm_modeset_acquire_ctx *ctx)
79e53945 9829{
83a57153 9830 struct drm_device *dev = connector->dev;
d2434ab7
DV		 9831 struct intel_encoder *intel_encoder =
9832 intel_attached_encoder(connector);
4ef69c7a 9833 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 9834 struct drm_crtc *crtc = encoder->crtc;
412b61d8 9835 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 9836 struct drm_atomic_state *state;
944b0c76 9837 struct drm_connector_state *connector_state;
79e53945 9838
d2dff872 9839 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9840 connector->base.id, connector->name,
8e329a03 9841 encoder->base.id, encoder->name);
d2dff872 9842
8261b191 9843 if (old->load_detect_temp) {
83a57153 9844 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 9845 if (!state)
9846 goto fail;
83a57153
ACO		 9847
9848 state->acquire_ctx = ctx;
9849
944b0c76
ACO		 9850 connector_state = drm_atomic_get_connector_state(state, connector);
9851 if (IS_ERR(connector_state))
9852 goto fail;
9853
fc303101
DV		 9854 to_intel_connector(connector)->new_encoder = NULL;
9855 intel_encoder->new_crtc = NULL;
412b61d8 9856 intel_crtc->new_enabled = false;
944b0c76
ACO		 9857
9858 connector_state->best_encoder = NULL;
9859 connector_state->crtc = NULL;
9860
83a57153
ACO		 9861 intel_set_mode(crtc, NULL, 0, 0, NULL, state);
9862
9863 drm_atomic_state_free(state);
d2dff872 9864
36206361
DV		 9865 if (old->release_fb) {
9866 drm_framebuffer_unregister_private(old->release_fb);
9867 drm_framebuffer_unreference(old->release_fb);
9868 }
d2dff872 9869
0622a53c 9870 return;
79e53945
JB		 9871 }
9872
c751ce4f 9873 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 9874 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9875 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 9876
9877 return;
9878fail:
9879 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9880 drm_atomic_state_free(state);
79e53945
JB		 9881}
9882
da4a1efa 9883static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 9884 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 9885{
9886 struct drm_i915_private *dev_priv = dev->dev_private;
9887 u32 dpll = pipe_config->dpll_hw_state.dpll;
9888
9889 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 9890 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 9891 else if (HAS_PCH_SPLIT(dev))
9892 return 120000;
9893 else if (!IS_GEN2(dev))
9894 return 96000;
9895 else
9896 return 48000;
9897}
9898
79e53945 9899/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 9900static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 9901 struct intel_crtc_state *pipe_config)
79e53945 9902{
f1f644dc 9903 struct drm_device *dev = crtc->base.dev;
79e53945 9904 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 9905 int pipe = pipe_config->cpu_transcoder;
293623f7 9906 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 9907 u32 fp;
9908 intel_clock_t clock;
da4a1efa 9909 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 9910
9911 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 9912 fp = pipe_config->dpll_hw_state.fp0;
79e53945 9913 else
293623f7 9914 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 9915
9916 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 9917 if (IS_PINEVIEW(dev)) {
9918 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9919 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 9920 } else {
9921 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9922 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9923 }
9924
a6c45cf0 9925 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 9926 if (IS_PINEVIEW(dev))
9927 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9928 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 9929 else
9930 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 9931 DPLL_FPA01_P1_POST_DIV_SHIFT);
9932
9933 switch (dpll & DPLL_MODE_MASK) {
9934 case DPLLB_MODE_DAC_SERIAL:
9935 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9936 5 : 10;
9937 break;
9938 case DPLLB_MODE_LVDS:
9939 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9940 7 : 14;
9941 break;
9942 default:
28c97730 9943 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 9944 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 9945 return;
79e53945
JB		 9946 }
9947
ac58c3f0 9948 if (IS_PINEVIEW(dev))
da4a1efa 9949 pineview_clock(refclk, &clock);
ac58c3f0 9950 else
da4a1efa 9951 i9xx_clock(refclk, &clock);
79e53945 9952 } else {
0fb58223 9953 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 9954 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 9955
9956 if (is_lvds) {
9957 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9958 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 9959
9960 if (lvds & LVDS_CLKB_POWER_UP)
9961 clock.p2 = 7;
9962 else
9963 clock.p2 = 14;
79e53945
JB		 9964 } else {
9965 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9966 clock.p1 = 2;
9967 else {
9968 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9969 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9970 }
9971 if (dpll & PLL_P2_DIVIDE_BY_4)
9972 clock.p2 = 4;
9973 else
9974 clock.p2 = 2;
79e53945 9975 }
da4a1efa
VS		 9976
9977 i9xx_clock(refclk, &clock);
79e53945
JB		 9978 }
9979
18442d08
VS		 9980 /*
9981 * This value includes pixel_multiplier. We will use
241bfc38 9982 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 9983 * encoder's get_config() function.
9984 */
9985 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 9986}
9987
6878da05
VS		 9988int intel_dotclock_calculate(int link_freq,
9989 const struct intel_link_m_n *m_n)
f1f644dc 9990{
f1f644dc
JB		 9991 /*
9992 * The calculation for the data clock is:
1041a02f 9993 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 9994 * But we want to avoid losing precison if possible, so:
1041a02f 9995 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 9996 *
9997 * and the link clock is simpler:
1041a02f 9998 * link_clock = (m * link_clock) / n
f1f644dc
JB		 9999 */
10000
6878da05
VS		 10001 if (!m_n->link_n)
10002 return 0;
f1f644dc 10003
6878da05
VS		 10004 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10005}
f1f644dc 10006
18442d08 10007static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10008 struct intel_crtc_state *pipe_config)
6878da05
VS		 10009{
10010 struct drm_device *dev = crtc->base.dev;
79e53945 10011
18442d08
VS		 10012 /* read out port_clock from the DPLL */
10013 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10014
f1f644dc 10015 /*
18442d08 10016 * This value does not include pixel_multiplier.
241bfc38 10017 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10018 * agree once we know their relationship in the encoder's
10019 * get_config() function.
79e53945 10020 */
2d112de7 10021 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10022 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10023 &pipe_config->fdi_m_n);
79e53945
JB		 10024}
10025
10026/** Returns the currently programmed mode of the given pipe. */
10027struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10028 struct drm_crtc *crtc)
10029{
548f245b 10030 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10031 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10032 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10033 struct drm_display_mode *mode;
5cec258b 10034 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10035 int htot = I915_READ(HTOTAL(cpu_transcoder));
10036 int hsync = I915_READ(HSYNC(cpu_transcoder));
10037 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10038 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10039 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10040
10041 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10042 if (!mode)
10043 return NULL;
10044
f1f644dc
JB		 10045 /*
10046 * Construct a pipe_config sufficient for getting the clock info
10047 * back out of crtc_clock_get.
10048 *
10049 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10050 * to use a real value here instead.
10051 */
293623f7 10052 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10053 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10054 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10055 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10056 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10057 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10058
773ae034 10059 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10060 mode->hdisplay = (htot & 0xffff) + 1;
10061 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10062 mode->hsync_start = (hsync & 0xffff) + 1;
10063 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10064 mode->vdisplay = (vtot & 0xffff) + 1;
10065 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10066 mode->vsync_start = (vsync & 0xffff) + 1;
10067 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10068
10069 drm_mode_set_name(mode);
79e53945
JB		 10070
10071 return mode;
10072}
10073
652c393a
JB		 10074static void intel_decrease_pllclock(struct drm_crtc *crtc)
10075{
10076 struct drm_device *dev = crtc->dev;
fbee40df 10077 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10078 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 10079
baff296c 10080 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 10081 return;
10082
10083 if (!dev_priv->lvds_downclock_avail)
10084 return;
10085
10086 /*
10087 * Since this is called by a timer, we should never get here in
10088 * the manual case.
10089 */
10090 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 10091 int pipe = intel_crtc->pipe;
10092 int dpll_reg = DPLL(pipe);
10093 int dpll;
f6e5b160 10094
44d98a61 10095 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 10096
8ac5a6d5 10097 assert_panel_unlocked(dev_priv, pipe);
652c393a 10098
dc257cf1 10099 dpll = I915_READ(dpll_reg);
652c393a
JB		 10100 dpll |= DISPLAY_RATE_SELECT_FPA1;
10101 I915_WRITE(dpll_reg, dpll);
9d0498a2 10102 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 10103 dpll = I915_READ(dpll_reg);
10104 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 10105 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 10106 }
10107
10108}
10109
f047e395
CW		 10110void intel_mark_busy(struct drm_device *dev)
10111{
c67a470b
PZ		 10112 struct drm_i915_private *dev_priv = dev->dev_private;
10113
f62a0076
CW		 10114 if (dev_priv->mm.busy)
10115 return;
10116
43694d69 10117 intel_runtime_pm_get(dev_priv);
c67a470b 10118 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10119 if (INTEL_INFO(dev)->gen >= 6)
10120 gen6_rps_busy(dev_priv);
f62a0076 10121 dev_priv->mm.busy = true;
f047e395
CW		 10122}
10123
10124void intel_mark_idle(struct drm_device *dev)
652c393a 10125{
c67a470b 10126 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10127 struct drm_crtc *crtc;
652c393a 10128
f62a0076
CW		 10129 if (!dev_priv->mm.busy)
10130 return;
10131
10132 dev_priv->mm.busy = false;
10133
70e1e0ec 10134 for_each_crtc(dev, crtc) {
f4510a27 10135 if (!crtc->primary->fb)
652c393a
JB		 10136 continue;
10137
725a5b54 10138 intel_decrease_pllclock(crtc);
652c393a 10139 }
b29c19b6 10140
3d13ef2e 10141 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10142 gen6_rps_idle(dev->dev_private);
bb4cdd53 10143
43694d69 10144 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10145}
10146
f5de6e07
ACO		 10147static void intel_crtc_set_state(struct intel_crtc *crtc,
10148 struct intel_crtc_state *crtc_state)
10149{
10150 kfree(crtc->config);
10151 crtc->config = crtc_state;
16f3f658 10152 crtc->base.state = &crtc_state->base;
f5de6e07
ACO		 10153}
10154
79e53945
JB		 10155static void intel_crtc_destroy(struct drm_crtc *crtc)
10156{
10157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10158 struct drm_device *dev = crtc->dev;
10159 struct intel_unpin_work *work;
67e77c5a 10160
5e2d7afc 10161 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10162 work = intel_crtc->unpin_work;
10163 intel_crtc->unpin_work = NULL;
5e2d7afc 10164 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10165
10166 if (work) {
10167 cancel_work_sync(&work->work);
10168 kfree(work);
10169 }
79e53945 10170
f5de6e07 10171 intel_crtc_set_state(intel_crtc, NULL);
79e53945 10172 drm_crtc_cleanup(crtc);
67e77c5a 10173
79e53945
JB		 10174 kfree(intel_crtc);
10175}
10176
6b95a207
KH		 10177static void intel_unpin_work_fn(struct work_struct *__work)
10178{
10179 struct intel_unpin_work *work =
10180 container_of(__work, struct intel_unpin_work, work);
b4a98e57 10181 struct drm_device *dev = work->crtc->dev;
f99d7069 10182 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 10183
b4a98e57 10184 mutex_lock(&dev->struct_mutex);
82bc3b2d 10185 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 10186 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10187
7ff0ebcc 10188 intel_fbc_update(dev);
f06cc1b9
JH		 10189
10190 if (work->flip_queued_req)
146d84f0 10191 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10192 mutex_unlock(&dev->struct_mutex);
10193
f99d7069 10194 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 10195 drm_framebuffer_unreference(work->old_fb);
f99d7069 10196
b4a98e57
CW		 10197 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10198 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10199
6b95a207
KH		 10200 kfree(work);
10201}
10202
1afe3e9d 10203static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10204 struct drm_crtc *crtc)
6b95a207 10205{
6b95a207
KH		 10206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10207 struct intel_unpin_work *work;
6b95a207
KH		 10208 unsigned long flags;
10209
10210 /* Ignore early vblank irqs */
10211 if (intel_crtc == NULL)
10212 return;
10213
f326038a
DV		 10214 /*
10215 * This is called both by irq handlers and the reset code (to complete
10216 * lost pageflips) so needs the full irqsave spinlocks.
10217 */
6b95a207
KH		 10218 spin_lock_irqsave(&dev->event_lock, flags);
10219 work = intel_crtc->unpin_work;
e7d841ca
CW		 10220
10221 /* Ensure we don't miss a work->pending update ... */
10222 smp_rmb();
10223
10224 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10225 spin_unlock_irqrestore(&dev->event_lock, flags);
10226 return;
10227 }
10228
d6bbafa1 10229 page_flip_completed(intel_crtc);
0af7e4df 10230
6b95a207 10231 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10232}
10233
1afe3e9d
JB		 10234void intel_finish_page_flip(struct drm_device *dev, int pipe)
10235{
fbee40df 10236 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10237 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10238
49b14a5c 10239 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10240}
10241
10242void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10243{
fbee40df 10244 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10245 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10246
49b14a5c 10247 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10248}
10249
75f7f3ec
VS		 10250/* Is 'a' after or equal to 'b'? */
10251static bool g4x_flip_count_after_eq(u32 a, u32 b)
10252{
10253 return !((a - b) & 0x80000000);
10254}
10255
10256static bool page_flip_finished(struct intel_crtc *crtc)
10257{
10258 struct drm_device *dev = crtc->base.dev;
10259 struct drm_i915_private *dev_priv = dev->dev_private;
10260
bdfa7542
VS		 10261 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10262 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10263 return true;
10264
75f7f3ec
VS		 10265 /*
10266 * The relevant registers doen't exist on pre-ctg.
10267 * As the flip done interrupt doesn't trigger for mmio
10268 * flips on gmch platforms, a flip count check isn't
10269 * really needed there. But since ctg has the registers,
10270 * include it in the check anyway.
10271 */
10272 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10273 return true;
10274
10275 /*
10276 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10277 * used the same base address. In that case the mmio flip might
10278 * have completed, but the CS hasn't even executed the flip yet.
10279 *
10280 * A flip count check isn't enough as the CS might have updated
10281 * the base address just after start of vblank, but before we
10282 * managed to process the interrupt. This means we'd complete the
10283 * CS flip too soon.
10284 *
10285 * Combining both checks should get us a good enough result. It may
10286 * still happen that the CS flip has been executed, but has not
10287 * yet actually completed. But in case the base address is the same
10288 * anyway, we don't really care.
10289 */
10290 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10291 crtc->unpin_work->gtt_offset &&
10292 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10293 crtc->unpin_work->flip_count);
10294}
10295
6b95a207
KH		 10296void intel_prepare_page_flip(struct drm_device *dev, int plane)
10297{
fbee40df 10298 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10299 struct intel_crtc *intel_crtc =
10300 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10301 unsigned long flags;
10302
f326038a
DV		 10303
10304 /*
10305 * This is called both by irq handlers and the reset code (to complete
10306 * lost pageflips) so needs the full irqsave spinlocks.
10307 *
10308 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10309 * generate a page-flip completion irq, i.e. every modeset
10310 * is also accompanied by a spurious intel_prepare_page_flip().
10311 */
6b95a207 10312 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10313 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10314 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10315 spin_unlock_irqrestore(&dev->event_lock, flags);
10316}
10317
eba905b2 10318static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10319{
10320 /* Ensure that the work item is consistent when activating it ... */
10321 smp_wmb();
10322 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10323 /* and that it is marked active as soon as the irq could fire. */
10324 smp_wmb();
10325}
10326
8c9f3aaf
JB		 10327static int intel_gen2_queue_flip(struct drm_device *dev,
10328 struct drm_crtc *crtc,
10329 struct drm_framebuffer *fb,
ed8d1975 10330 struct drm_i915_gem_object *obj,
a4872ba6 10331 struct intel_engine_cs *ring,
ed8d1975 10332 uint32_t flags)
8c9f3aaf 10333{
8c9f3aaf 10334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10335 u32 flip_mask;
10336 int ret;
10337
6d90c952 10338 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10339 if (ret)
4fa62c89 10340 return ret;
8c9f3aaf
JB		 10341
10342 /* Can't queue multiple flips, so wait for the previous
10343 * one to finish before executing the next.
10344 */
10345 if (intel_crtc->plane)
10346 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10347 else
10348 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10349 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10350 intel_ring_emit(ring, MI_NOOP);
10351 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10352 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10353 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10354 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10355 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10356
10357 intel_mark_page_flip_active(intel_crtc);
09246732 10358 __intel_ring_advance(ring);
83d4092b 10359 return 0;
8c9f3aaf
JB		 10360}
10361
10362static int intel_gen3_queue_flip(struct drm_device *dev,
10363 struct drm_crtc *crtc,
10364 struct drm_framebuffer *fb,
ed8d1975 10365 struct drm_i915_gem_object *obj,
a4872ba6 10366 struct intel_engine_cs *ring,
ed8d1975 10367 uint32_t flags)
8c9f3aaf 10368{
8c9f3aaf 10369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10370 u32 flip_mask;
10371 int ret;
10372
6d90c952 10373 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10374 if (ret)
4fa62c89 10375 return ret;
8c9f3aaf
JB		 10376
10377 if (intel_crtc->plane)
10378 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10379 else
10380 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10381 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10382 intel_ring_emit(ring, MI_NOOP);
10383 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10384 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10385 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10386 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10387 intel_ring_emit(ring, MI_NOOP);
10388
e7d841ca 10389 intel_mark_page_flip_active(intel_crtc);
09246732 10390 __intel_ring_advance(ring);
83d4092b 10391 return 0;
8c9f3aaf
JB		 10392}
10393
10394static int intel_gen4_queue_flip(struct drm_device *dev,
10395 struct drm_crtc *crtc,
10396 struct drm_framebuffer *fb,
ed8d1975 10397 struct drm_i915_gem_object *obj,
a4872ba6 10398 struct intel_engine_cs *ring,
ed8d1975 10399 uint32_t flags)
8c9f3aaf
JB		 10400{
10401 struct drm_i915_private *dev_priv = dev->dev_private;
10402 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10403 uint32_t pf, pipesrc;
10404 int ret;
10405
6d90c952 10406 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10407 if (ret)
4fa62c89 10408 return ret;
8c9f3aaf
JB		 10409
10410 /* i965+ uses the linear or tiled offsets from the
10411 * Display Registers (which do not change across a page-flip)
10412 * so we need only reprogram the base address.
10413 */
6d90c952
DV		 10414 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10415 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10416 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10417 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10418 obj->tiling_mode);
8c9f3aaf
JB		 10419
10420 /* XXX Enabling the panel-fitter across page-flip is so far
10421 * untested on non-native modes, so ignore it for now.
10422 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10423 */
10424 pf = 0;
10425 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10426 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10427
10428 intel_mark_page_flip_active(intel_crtc);
09246732 10429 __intel_ring_advance(ring);
83d4092b 10430 return 0;
8c9f3aaf
JB		 10431}
10432
10433static int intel_gen6_queue_flip(struct drm_device *dev,
10434 struct drm_crtc *crtc,
10435 struct drm_framebuffer *fb,
ed8d1975 10436 struct drm_i915_gem_object *obj,
a4872ba6 10437 struct intel_engine_cs *ring,
ed8d1975 10438 uint32_t flags)
8c9f3aaf
JB		 10439{
10440 struct drm_i915_private *dev_priv = dev->dev_private;
10441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10442 uint32_t pf, pipesrc;
10443 int ret;
10444
6d90c952 10445 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10446 if (ret)
4fa62c89 10447 return ret;
8c9f3aaf 10448
6d90c952
DV		 10449 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10450 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10451 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10452 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10453
dc257cf1
DV		 10454 /* Contrary to the suggestions in the documentation,
10455 * "Enable Panel Fitter" does not seem to be required when page
10456 * flipping with a non-native mode, and worse causes a normal
10457 * modeset to fail.
10458 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10459 */
10460 pf = 0;
8c9f3aaf 10461 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10462 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10463
10464 intel_mark_page_flip_active(intel_crtc);
09246732 10465 __intel_ring_advance(ring);
83d4092b 10466 return 0;
8c9f3aaf
JB		 10467}
10468
7c9017e5
JB		 10469static int intel_gen7_queue_flip(struct drm_device *dev,
10470 struct drm_crtc *crtc,
10471 struct drm_framebuffer *fb,
ed8d1975 10472 struct drm_i915_gem_object *obj,
a4872ba6 10473 struct intel_engine_cs *ring,
ed8d1975 10474 uint32_t flags)
7c9017e5 10475{
7c9017e5 10476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10477 uint32_t plane_bit = 0;
ffe74d75
CW		 10478 int len, ret;
10479
eba905b2 10480 switch (intel_crtc->plane) {
cb05d8de
DV		 10481 case PLANE_A:
10482 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10483 break;
10484 case PLANE_B:
10485 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10486 break;
10487 case PLANE_C:
10488 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10489 break;
10490 default:
10491 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10492 return -ENODEV;
cb05d8de
DV		 10493 }
10494
ffe74d75 10495 len = 4;
f476828a 10496 if (ring->id == RCS) {
ffe74d75 10497 len += 6;
f476828a
DL		 10498 /*
10499 * On Gen 8, SRM is now taking an extra dword to accommodate
10500 * 48bits addresses, and we need a NOOP for the batch size to
10501 * stay even.
10502 */
10503 if (IS_GEN8(dev))
10504 len += 2;
10505 }
ffe74d75 10506
f66fab8e
VS		 10507 /*
10508 * BSpec MI_DISPLAY_FLIP for IVB:
10509 * "The full packet must be contained within the same cache line."
10510 *
10511 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10512 * cacheline, if we ever start emitting more commands before
10513 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10514 * then do the cacheline alignment, and finally emit the
10515 * MI_DISPLAY_FLIP.
10516 */
10517 ret = intel_ring_cacheline_align(ring);
10518 if (ret)
4fa62c89 10519 return ret;
f66fab8e 10520
ffe74d75 10521 ret = intel_ring_begin(ring, len);
7c9017e5 10522 if (ret)
4fa62c89 10523 return ret;
7c9017e5 10524
ffe74d75
CW		 10525 /* Unmask the flip-done completion message. Note that the bspec says that
10526 * we should do this for both the BCS and RCS, and that we must not unmask
10527 * more than one flip event at any time (or ensure that one flip message
10528 * can be sent by waiting for flip-done prior to queueing new flips).
10529 * Experimentation says that BCS works despite DERRMR masking all
10530 * flip-done completion events and that unmasking all planes at once
10531 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10532 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10533 */
10534 if (ring->id == RCS) {
10535 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10536 intel_ring_emit(ring, DERRMR);
10537 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10538 DERRMR_PIPEB_PRI_FLIP_DONE |
10539 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 10540 if (IS_GEN8(dev))
10541 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10542 MI_SRM_LRM_GLOBAL_GTT);
10543 else
10544 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10545 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 10546 intel_ring_emit(ring, DERRMR);
10547 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 10548 if (IS_GEN8(dev)) {
10549 intel_ring_emit(ring, 0);
10550 intel_ring_emit(ring, MI_NOOP);
10551 }
ffe74d75
CW		 10552 }
10553
cb05d8de 10554 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 10555 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 10556 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 10557 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 10558
10559 intel_mark_page_flip_active(intel_crtc);
09246732 10560 __intel_ring_advance(ring);
83d4092b 10561 return 0;
7c9017e5
JB		 10562}
10563
84c33a64
SG		 10564static bool use_mmio_flip(struct intel_engine_cs *ring,
10565 struct drm_i915_gem_object *obj)
10566{
10567 /*
10568 * This is not being used for older platforms, because
10569 * non-availability of flip done interrupt forces us to use
10570 * CS flips. Older platforms derive flip done using some clever
10571 * tricks involving the flip_pending status bits and vblank irqs.
10572 * So using MMIO flips there would disrupt this mechanism.
10573 */
10574
8e09bf83
CW		 10575 if (ring == NULL)
10576 return true;
10577
84c33a64
SG		 10578 if (INTEL_INFO(ring->dev)->gen < 5)
10579 return false;
10580
10581 if (i915.use_mmio_flip < 0)
10582 return false;
10583 else if (i915.use_mmio_flip > 0)
10584 return true;
14bf993e
OM		 10585 else if (i915.enable_execlists)
10586 return true;
84c33a64 10587 else
41c52415 10588 return ring != i915_gem_request_get_ring(obj->last_read_req);
84c33a64
SG		 10589}
10590
ff944564
DL		 10591static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10592{
10593 struct drm_device *dev = intel_crtc->base.dev;
10594 struct drm_i915_private *dev_priv = dev->dev_private;
10595 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 10596 const enum pipe pipe = intel_crtc->pipe;
10597 u32 ctl, stride;
10598
10599 ctl = I915_READ(PLANE_CTL(pipe, 0));
10600 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 10601 switch (fb->modifier[0]) {
10602 case DRM_FORMAT_MOD_NONE:
10603 break;
10604 case I915_FORMAT_MOD_X_TILED:
ff944564 10605 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 10606 break;
10607 case I915_FORMAT_MOD_Y_TILED:
10608 ctl |= PLANE_CTL_TILED_Y;
10609 break;
10610 case I915_FORMAT_MOD_Yf_TILED:
10611 ctl |= PLANE_CTL_TILED_YF;
10612 break;
10613 default:
10614 MISSING_CASE(fb->modifier[0]);
10615 }
ff944564
DL		 10616
10617 /*
10618 * The stride is either expressed as a multiple of 64 bytes chunks for
10619 * linear buffers or in number of tiles for tiled buffers.
10620 */
2ebef630
TU		 10621 stride = fb->pitches[0] /
10622 intel_fb_stride_alignment(dev, fb->modifier[0],
10623 fb->pixel_format);
ff944564
DL		 10624
10625 /*
10626 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10627 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10628 */
10629 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10630 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10631
10632 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10633 POSTING_READ(PLANE_SURF(pipe, 0));
10634}
10635
10636static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 10637{
10638 struct drm_device *dev = intel_crtc->base.dev;
10639 struct drm_i915_private *dev_priv = dev->dev_private;
10640 struct intel_framebuffer *intel_fb =
10641 to_intel_framebuffer(intel_crtc->base.primary->fb);
10642 struct drm_i915_gem_object *obj = intel_fb->obj;
10643 u32 dspcntr;
10644 u32 reg;
10645
84c33a64
SG		 10646 reg = DSPCNTR(intel_crtc->plane);
10647 dspcntr = I915_READ(reg);
10648
c5d97472
DL		 10649 if (obj->tiling_mode != I915_TILING_NONE)
10650 dspcntr |= DISPPLANE_TILED;
10651 else
10652 dspcntr &= ~DISPPLANE_TILED;
10653
84c33a64
SG		 10654 I915_WRITE(reg, dspcntr);
10655
10656 I915_WRITE(DSPSURF(intel_crtc->plane),
10657 intel_crtc->unpin_work->gtt_offset);
10658 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 10659
ff944564
DL		 10660}
10661
10662/*
10663 * XXX: This is the temporary way to update the plane registers until we get
10664 * around to using the usual plane update functions for MMIO flips
10665 */
10666static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10667{
10668 struct drm_device *dev = intel_crtc->base.dev;
10669 bool atomic_update;
10670 u32 start_vbl_count;
10671
10672 intel_mark_page_flip_active(intel_crtc);
10673
10674 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10675
10676 if (INTEL_INFO(dev)->gen >= 9)
10677 skl_do_mmio_flip(intel_crtc);
10678 else
10679 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10680 ilk_do_mmio_flip(intel_crtc);
10681
9362c7c5
ACO		 10682 if (atomic_update)
10683 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 10684}
10685
9362c7c5 10686static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 10687{
cc8c4cc2 10688 struct intel_crtc *crtc =
9362c7c5 10689 container_of(work, struct intel_crtc, mmio_flip.work);
cc8c4cc2 10690 struct intel_mmio_flip *mmio_flip;
84c33a64 10691
cc8c4cc2
JH		 10692 mmio_flip = &crtc->mmio_flip;
10693 if (mmio_flip->req)
9c654818
JH		 10694 WARN_ON(__i915_wait_request(mmio_flip->req,
10695 crtc->reset_counter,
10696 false, NULL, NULL) != 0);
84c33a64 10697
cc8c4cc2
JH		 10698 intel_do_mmio_flip(crtc);
10699 if (mmio_flip->req) {
10700 mutex_lock(&crtc->base.dev->struct_mutex);
146d84f0 10701 i915_gem_request_assign(&mmio_flip->req, NULL);
cc8c4cc2
JH		 10702 mutex_unlock(&crtc->base.dev->struct_mutex);
10703 }
84c33a64
SG		 10704}
10705
10706static int intel_queue_mmio_flip(struct drm_device *dev,
10707 struct drm_crtc *crtc,
10708 struct drm_framebuffer *fb,
10709 struct drm_i915_gem_object *obj,
10710 struct intel_engine_cs *ring,
10711 uint32_t flags)
10712{
84c33a64 10713 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
84c33a64 10714
cc8c4cc2
JH		 10715 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
10716 obj->last_write_req);
536f5b5e
ACO		 10717
10718 schedule_work(&intel_crtc->mmio_flip.work);
84c33a64 10719
84c33a64
SG		 10720 return 0;
10721}
10722
8c9f3aaf
JB		 10723static int intel_default_queue_flip(struct drm_device *dev,
10724 struct drm_crtc *crtc,
10725 struct drm_framebuffer *fb,
ed8d1975 10726 struct drm_i915_gem_object *obj,
a4872ba6 10727 struct intel_engine_cs *ring,
ed8d1975 10728 uint32_t flags)
8c9f3aaf
JB		 10729{
10730 return -ENODEV;
10731}
10732
d6bbafa1
CW		 10733static bool __intel_pageflip_stall_check(struct drm_device *dev,
10734 struct drm_crtc *crtc)
10735{
10736 struct drm_i915_private *dev_priv = dev->dev_private;
10737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10738 struct intel_unpin_work *work = intel_crtc->unpin_work;
10739 u32 addr;
10740
10741 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10742 return true;
10743
10744 if (!work->enable_stall_check)
10745 return false;
10746
10747 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 10748 if (work->flip_queued_req &&
10749 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 10750 return false;
10751
1e3feefd 10752 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 10753 }
10754
1e3feefd 10755 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 10756 return false;
10757
10758 /* Potential stall - if we see that the flip has happened,
10759 * assume a missed interrupt. */
10760 if (INTEL_INFO(dev)->gen >= 4)
10761 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10762 else
10763 addr = I915_READ(DSPADDR(intel_crtc->plane));
10764
10765 /* There is a potential issue here with a false positive after a flip
10766 * to the same address. We could address this by checking for a
10767 * non-incrementing frame counter.
10768 */
10769 return addr == work->gtt_offset;
10770}
10771
10772void intel_check_page_flip(struct drm_device *dev, int pipe)
10773{
10774 struct drm_i915_private *dev_priv = dev->dev_private;
10775 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 10777 struct intel_unpin_work *work;
f326038a 10778
6c51d46f 10779 WARN_ON(!in_interrupt());
d6bbafa1
CW		 10780
10781 if (crtc == NULL)
10782 return;
10783
f326038a 10784 spin_lock(&dev->event_lock);
6ad790c0
CW		 10785 work = intel_crtc->unpin_work;
10786 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 10787 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 10788 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 10789 page_flip_completed(intel_crtc);
6ad790c0 10790 work = NULL;
d6bbafa1 10791 }
6ad790c0
CW		 10792 if (work != NULL &&
10793 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
10794 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 10795 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 10796}
10797
6b95a207
KH		 10798static int intel_crtc_page_flip(struct drm_crtc *crtc,
10799 struct drm_framebuffer *fb,
ed8d1975
KP		 10800 struct drm_pending_vblank_event *event,
10801 uint32_t page_flip_flags)
6b95a207
KH		 10802{
10803 struct drm_device *dev = crtc->dev;
10804 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 10805 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 10806 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 10807 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 10808 struct drm_plane *primary = crtc->primary;
a071fa00 10809 enum pipe pipe = intel_crtc->pipe;
6b95a207 10810 struct intel_unpin_work *work;
a4872ba6 10811 struct intel_engine_cs *ring;
cf5d8a46 10812 bool mmio_flip;
52e68630 10813 int ret;
6b95a207 10814
2ff8fde1
MR		 10815 /*
10816 * drm_mode_page_flip_ioctl() should already catch this, but double
10817 * check to be safe. In the future we may enable pageflipping from
10818 * a disabled primary plane.
10819 */
10820 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10821 return -EBUSY;
10822
e6a595d2 10823 /* Can't change pixel format via MI display flips. */
f4510a27 10824 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 10825 return -EINVAL;
10826
10827 /*
10828 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10829 * Note that pitch changes could also affect these register.
10830 */
10831 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 10832 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10833 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 10834 return -EINVAL;
10835
f900db47
CW		 10836 if (i915_terminally_wedged(&dev_priv->gpu_error))
10837 goto out_hang;
10838
b14c5679 10839 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 10840 if (work == NULL)
10841 return -ENOMEM;
10842
6b95a207 10843 work->event = event;
b4a98e57 10844 work->crtc = crtc;
ab8d6675 10845 work->old_fb = old_fb;
6b95a207
KH		 10846 INIT_WORK(&work->work, intel_unpin_work_fn);
10847
87b6b101 10848 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 10849 if (ret)
10850 goto free_work;
10851
6b95a207 10852 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 10853 spin_lock_irq(&dev->event_lock);
6b95a207 10854 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 10855 /* Before declaring the flip queue wedged, check if
10856 * the hardware completed the operation behind our backs.
10857 */
10858 if (__intel_pageflip_stall_check(dev, crtc)) {
10859 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10860 page_flip_completed(intel_crtc);
10861 } else {
10862 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 10863 spin_unlock_irq(&dev->event_lock);
468f0b44 10864
d6bbafa1
CW		 10865 drm_crtc_vblank_put(crtc);
10866 kfree(work);
10867 return -EBUSY;
10868 }
6b95a207
KH		 10869 }
10870 intel_crtc->unpin_work = work;
5e2d7afc 10871 spin_unlock_irq(&dev->event_lock);
6b95a207 10872
b4a98e57
CW		 10873 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10874 flush_workqueue(dev_priv->wq);
10875
75dfca80 10876 /* Reference the objects for the scheduled work. */
ab8d6675 10877 drm_framebuffer_reference(work->old_fb);
05394f39 10878 drm_gem_object_reference(&obj->base);
6b95a207 10879
f4510a27 10880 crtc->primary->fb = fb;
afd65eb4 10881 update_state_fb(crtc->primary);
1ed1f968 10882
e1f99ce6 10883 work->pending_flip_obj = obj;
e1f99ce6 10884
89ed88ba
CW		 10885 ret = i915_mutex_lock_interruptible(dev);
10886 if (ret)
10887 goto cleanup;
10888
b4a98e57 10889 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 10890 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 10891
75f7f3ec 10892 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 10893 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 10894
4fa62c89
VS		 10895 if (IS_VALLEYVIEW(dev)) {
10896 ring = &dev_priv->ring[BCS];
ab8d6675 10897 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 10898 /* vlv: DISPLAY_FLIP fails to change tiling */
10899 ring = NULL;
48bf5b2d 10900 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 10901 ring = &dev_priv->ring[BCS];
4fa62c89 10902 } else if (INTEL_INFO(dev)->gen >= 7) {
41c52415 10903 ring = i915_gem_request_get_ring(obj->last_read_req);
4fa62c89
VS		 10904 if (ring == NULL || ring->id != RCS)
10905 ring = &dev_priv->ring[BCS];
10906 } else {
10907 ring = &dev_priv->ring[RCS];
10908 }
10909
cf5d8a46
CW		 10910 mmio_flip = use_mmio_flip(ring, obj);
10911
10912 /* When using CS flips, we want to emit semaphores between rings.
10913 * However, when using mmio flips we will create a task to do the
10914 * synchronisation, so all we want here is to pin the framebuffer
10915 * into the display plane and skip any waits.
10916 */
82bc3b2d 10917 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46
CW		 10918 crtc->primary->state,
10919 mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring);
8c9f3aaf
JB		 10920 if (ret)
10921 goto cleanup_pending;
6b95a207 10922
121920fa
TU		 10923 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
10924 + intel_crtc->dspaddr_offset;
4fa62c89 10925
cf5d8a46 10926 if (mmio_flip) {
84c33a64
SG		 10927 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10928 page_flip_flags);
d6bbafa1
CW		 10929 if (ret)
10930 goto cleanup_unpin;
10931
f06cc1b9
JH		 10932 i915_gem_request_assign(&work->flip_queued_req,
10933 obj->last_write_req);
d6bbafa1 10934 } else {
84c33a64 10935 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 10936 page_flip_flags);
10937 if (ret)
10938 goto cleanup_unpin;
10939
f06cc1b9
JH		 10940 i915_gem_request_assign(&work->flip_queued_req,
10941 intel_ring_get_request(ring));
d6bbafa1
CW		 10942 }
10943
1e3feefd 10944 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 10945 work->enable_stall_check = true;
4fa62c89 10946
ab8d6675 10947 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 10948 INTEL_FRONTBUFFER_PRIMARY(pipe));
10949
7ff0ebcc 10950 intel_fbc_disable(dev);
f99d7069 10951 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 10952 mutex_unlock(&dev->struct_mutex);
10953
e5510fac
JB		 10954 trace_i915_flip_request(intel_crtc->plane, obj);
10955
6b95a207 10956 return 0;
96b099fd 10957
4fa62c89 10958cleanup_unpin:
82bc3b2d 10959 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 10960cleanup_pending:
b4a98e57 10961 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 10962 mutex_unlock(&dev->struct_mutex);
10963cleanup:
f4510a27 10964 crtc->primary->fb = old_fb;
afd65eb4 10965 update_state_fb(crtc->primary);
89ed88ba
CW		 10966
10967 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 10968 drm_framebuffer_unreference(work->old_fb);
96b099fd 10969
5e2d7afc 10970 spin_lock_irq(&dev->event_lock);
96b099fd 10971 intel_crtc->unpin_work = NULL;
5e2d7afc 10972 spin_unlock_irq(&dev->event_lock);
96b099fd 10973
87b6b101 10974 drm_crtc_vblank_put(crtc);
7317c75e 10975free_work:
96b099fd
CW		 10976 kfree(work);
10977
f900db47
CW		 10978 if (ret == -EIO) {
10979out_hang:
53a366b9 10980 ret = intel_plane_restore(primary);
f0d3dad3 10981 if (ret == 0 && event) {
5e2d7afc 10982 spin_lock_irq(&dev->event_lock);
a071fa00 10983 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 10984 spin_unlock_irq(&dev->event_lock);
f0d3dad3 10985 }
f900db47 10986 }
96b099fd 10987 return ret;
6b95a207
KH		 10988}
10989
65b38e0d 10990static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 10991 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10992 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 10993 .atomic_begin = intel_begin_crtc_commit,
10994 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 10995};
10996
9a935856
DV		 10997/**
10998 * intel_modeset_update_staged_output_state
10999 *
11000 * Updates the staged output configuration state, e.g. after we've read out the
11001 * current hw state.
11002 */
11003static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11004{
7668851f 11005 struct intel_crtc *crtc;
9a935856
DV		 11006 struct intel_encoder *encoder;
11007 struct intel_connector *connector;
f6e5b160 11008
3a3371ff 11009 for_each_intel_connector(dev, connector) {
9a935856
DV		 11010 connector->new_encoder =
11011 to_intel_encoder(connector->base.encoder);
11012 }
f6e5b160 11013
b2784e15 11014 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11015 encoder->new_crtc =
11016 to_intel_crtc(encoder->base.crtc);
11017 }
7668851f 11018
d3fcc808 11019 for_each_intel_crtc(dev, crtc) {
83d65738 11020 crtc->new_enabled = crtc->base.state->enable;
7668851f 11021 }
f6e5b160
CW		 11022}
11023
d29b2f9d
ACO		 11024/* Transitional helper to copy current connector/encoder state to
11025 * connector->state. This is needed so that code that is partially
11026 * converted to atomic does the right thing.
11027 */
11028static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11029{
11030 struct intel_connector *connector;
11031
11032 for_each_intel_connector(dev, connector) {
11033 if (connector->base.encoder) {
11034 connector->base.state->best_encoder =
11035 connector->base.encoder;
11036 connector->base.state->crtc =
11037 connector->base.encoder->crtc;
11038 } else {
11039 connector->base.state->best_encoder = NULL;
11040 connector->base.state->crtc = NULL;
11041 }
11042 }
11043}
11044
9a935856
DV		 11045/**
11046 * intel_modeset_commit_output_state
11047 *
11048 * This function copies the stage display pipe configuration to the real one.
11049 */
11050static void intel_modeset_commit_output_state(struct drm_device *dev)
11051{
7668851f 11052 struct intel_crtc *crtc;
9a935856
DV		 11053 struct intel_encoder *encoder;
11054 struct intel_connector *connector;
f6e5b160 11055
3a3371ff 11056 for_each_intel_connector(dev, connector) {
9a935856
DV		 11057 connector->base.encoder = &connector->new_encoder->base;
11058 }
f6e5b160 11059
b2784e15 11060 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11061 encoder->base.crtc = &encoder->new_crtc->base;
11062 }
7668851f 11063
d3fcc808 11064 for_each_intel_crtc(dev, crtc) {
83d65738 11065 crtc->base.state->enable = crtc->new_enabled;
7668851f
VS		 11066 crtc->base.enabled = crtc->new_enabled;
11067 }
d29b2f9d
ACO		 11068
11069 intel_modeset_update_connector_atomic_state(dev);
9a935856
DV		 11070}
11071
050f7aeb 11072static void
eba905b2 11073connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11074 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11075{
11076 int bpp = pipe_config->pipe_bpp;
11077
11078 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11079 connector->base.base.id,
c23cc417 11080 connector->base.name);
050f7aeb
DV		 11081
11082 /* Don't use an invalid EDID bpc value */
11083 if (connector->base.display_info.bpc &&
11084 connector->base.display_info.bpc * 3 < bpp) {
11085 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11086 bpp, connector->base.display_info.bpc*3);
11087 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11088 }
11089
11090 /* Clamp bpp to 8 on screens without EDID 1.4 */
11091 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11092 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11093 bpp);
11094 pipe_config->pipe_bpp = 24;
11095 }
11096}
11097
4e53c2e0 11098static int
050f7aeb 11099compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11100 struct intel_crtc_state *pipe_config)
4e53c2e0 11101{
050f7aeb 11102 struct drm_device *dev = crtc->base.dev;
1486017f 11103 struct drm_atomic_state *state;
050f7aeb 11104 struct intel_connector *connector;
1486017f 11105 int bpp, i;
4e53c2e0 11106
d328c9d7 11107 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11108 bpp = 10*3;
d328c9d7
DV		 11109 else if (INTEL_INFO(dev)->gen >= 5)
11110 bpp = 12*3;
11111 else
11112 bpp = 8*3;
11113
4e53c2e0 11114
4e53c2e0
DV		 11115 pipe_config->pipe_bpp = bpp;
11116
1486017f
ACO		 11117 state = pipe_config->base.state;
11118
4e53c2e0 11119 /* Clamp display bpp to EDID value */
1486017f
ACO		 11120 for (i = 0; i < state->num_connector; i++) {
11121 if (!state->connectors[i])
11122 continue;
11123
11124 connector = to_intel_connector(state->connectors[i]);
11125 if (state->connector_states[i]->crtc != &crtc->base)
4e53c2e0
DV		 11126 continue;
11127
050f7aeb 11128 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 11129 }
11130
11131 return bpp;
11132}
11133
644db711
DV		 11134static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11135{
11136 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11137 "type: 0x%x flags: 0x%x\n",
1342830c 11138 mode->crtc_clock,
644db711
DV		 11139 mode->crtc_hdisplay, mode->crtc_hsync_start,
11140 mode->crtc_hsync_end, mode->crtc_htotal,
11141 mode->crtc_vdisplay, mode->crtc_vsync_start,
11142 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11143}
11144
c0b03411 11145static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11146 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11147 const char *context)
11148{
6a60cd87
CK		 11149 struct drm_device *dev = crtc->base.dev;
11150 struct drm_plane *plane;
11151 struct intel_plane *intel_plane;
11152 struct intel_plane_state *state;
11153 struct drm_framebuffer *fb;
11154
11155 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11156 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11157
11158 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11159 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11160 pipe_config->pipe_bpp, pipe_config->dither);
11161 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11162 pipe_config->has_pch_encoder,
11163 pipe_config->fdi_lanes,
11164 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11165 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11166 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11167 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11168 pipe_config->has_dp_encoder,
11169 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11170 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11171 pipe_config->dp_m_n.tu);
b95af8be
VK		 11172
11173 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11174 pipe_config->has_dp_encoder,
11175 pipe_config->dp_m2_n2.gmch_m,
11176 pipe_config->dp_m2_n2.gmch_n,
11177 pipe_config->dp_m2_n2.link_m,
11178 pipe_config->dp_m2_n2.link_n,
11179 pipe_config->dp_m2_n2.tu);
11180
55072d19
DV		 11181 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11182 pipe_config->has_audio,
11183 pipe_config->has_infoframe);
11184
c0b03411 11185 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11186 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11187 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11188 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11189 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11190 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11191 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11192 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
6a60cd87
CK		 11193 DRM_DEBUG_KMS("num_scalers: %d\n", crtc->num_scalers);
11194 DRM_DEBUG_KMS("scaler_users: 0x%x\n", pipe_config->scaler_state.scaler_users);
11195 DRM_DEBUG_KMS("scaler id: %d\n", pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11196 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11197 pipe_config->gmch_pfit.control,
11198 pipe_config->gmch_pfit.pgm_ratios,
11199 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11200 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11201 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11202 pipe_config->pch_pfit.size,
11203 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11204 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11205 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87
CK		 11206
11207 DRM_DEBUG_KMS("planes on this crtc\n");
11208 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11209 intel_plane = to_intel_plane(plane);
11210 if (intel_plane->pipe != crtc->pipe)
11211 continue;
11212
11213 state = to_intel_plane_state(plane->state);
11214 fb = state->base.fb;
11215 if (!fb) {
11216 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11217 "disabled, scaler_id = %d\n",
11218 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11219 plane->base.id, intel_plane->pipe,
11220 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11221 drm_plane_index(plane), state->scaler_id);
11222 continue;
11223 }
11224
11225 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11226 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11227 plane->base.id, intel_plane->pipe,
11228 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11229 drm_plane_index(plane));
11230 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11231 fb->base.id, fb->width, fb->height, fb->pixel_format);
11232 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11233 state->scaler_id,
11234 state->src.x1 >> 16, state->src.y1 >> 16,
11235 drm_rect_width(&state->src) >> 16,
11236 drm_rect_height(&state->src) >> 16,
11237 state->dst.x1, state->dst.y1,
11238 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11239 }
c0b03411
DV		 11240}
11241
bc079e8b
VS		 11242static bool encoders_cloneable(const struct intel_encoder *a,
11243 const struct intel_encoder *b)
accfc0c5 11244{
bc079e8b
VS		 11245 /* masks could be asymmetric, so check both ways */
11246 return a == b || (a->cloneable & (1 << b->type) &&
11247 b->cloneable & (1 << a->type));
11248}
11249
98a221da
ACO		 11250static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11251 struct intel_crtc *crtc,
bc079e8b
VS		 11252 struct intel_encoder *encoder)
11253{
bc079e8b 11254 struct intel_encoder *source_encoder;
98a221da
ACO		 11255 struct drm_connector_state *connector_state;
11256 int i;
bc079e8b 11257
98a221da
ACO		 11258 for (i = 0; i < state->num_connector; i++) {
11259 if (!state->connectors[i])
11260 continue;
bc079e8b 11261
98a221da
ACO		 11262 connector_state = state->connector_states[i];
11263 if (connector_state->crtc != &crtc->base)
bc079e8b
VS		 11264 continue;
11265
98a221da
ACO		 11266 source_encoder =
11267 to_intel_encoder(connector_state->best_encoder);
bc079e8b
VS		 11268 if (!encoders_cloneable(encoder, source_encoder))
11269 return false;
11270 }
11271
11272 return true;
11273}
11274
98a221da
ACO		 11275static bool check_encoder_cloning(struct drm_atomic_state *state,
11276 struct intel_crtc *crtc)
bc079e8b 11277{
accfc0c5 11278 struct intel_encoder *encoder;
98a221da
ACO		 11279 struct drm_connector_state *connector_state;
11280 int i;
accfc0c5 11281
98a221da
ACO		 11282 for (i = 0; i < state->num_connector; i++) {
11283 if (!state->connectors[i])
accfc0c5
DV		 11284 continue;
11285
98a221da
ACO		 11286 connector_state = state->connector_states[i];
11287 if (connector_state->crtc != &crtc->base)
11288 continue;
11289
11290 encoder = to_intel_encoder(connector_state->best_encoder);
11291 if (!check_single_encoder_cloning(state, crtc, encoder))
bc079e8b 11292 return false;
accfc0c5
DV		 11293 }
11294
bc079e8b 11295 return true;
accfc0c5
DV		 11296}
11297
5448a00d 11298static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 11299{
5448a00d
ACO		 11300 struct drm_device *dev = state->dev;
11301 struct intel_encoder *encoder;
11302 struct drm_connector_state *connector_state;
00f0b378 11303 unsigned int used_ports = 0;
5448a00d 11304 int i;
00f0b378
VS		 11305
11306 /*
11307 * Walk the connector list instead of the encoder
11308 * list to detect the problem on ddi platforms
11309 * where there's just one encoder per digital port.
11310 */
5448a00d
ACO		 11311 for (i = 0; i < state->num_connector; i++) {
11312 if (!state->connectors[i])
11313 continue;
00f0b378 11314
5448a00d
ACO		 11315 connector_state = state->connector_states[i];
11316 if (!connector_state->best_encoder)
00f0b378
VS		 11317 continue;
11318
5448a00d
ACO		 11319 encoder = to_intel_encoder(connector_state->best_encoder);
11320
11321 WARN_ON(!connector_state->crtc);
00f0b378
VS		 11322
11323 switch (encoder->type) {
11324 unsigned int port_mask;
11325 case INTEL_OUTPUT_UNKNOWN:
11326 if (WARN_ON(!HAS_DDI(dev)))
11327 break;
11328 case INTEL_OUTPUT_DISPLAYPORT:
11329 case INTEL_OUTPUT_HDMI:
11330 case INTEL_OUTPUT_EDP:
11331 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11332
11333 /* the same port mustn't appear more than once */
11334 if (used_ports & port_mask)
11335 return false;
11336
11337 used_ports |= port_mask;
11338 default:
11339 break;
11340 }
11341 }
11342
11343 return true;
11344}
11345
83a57153
ACO		 11346static void
11347clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11348{
11349 struct drm_crtc_state tmp_state;
663a3640 11350 struct intel_crtc_scaler_state scaler_state;
83a57153 11351
663a3640 11352 /* Clear only the intel specific part of the crtc state excluding scalers */
83a57153 11353 tmp_state = crtc_state->base;
663a3640 11354 scaler_state = crtc_state->scaler_state;
83a57153
ACO		 11355 memset(crtc_state, 0, sizeof *crtc_state);
11356 crtc_state->base = tmp_state;
663a3640 11357 crtc_state->scaler_state = scaler_state;
83a57153
ACO		 11358}
11359
5cec258b 11360static struct intel_crtc_state *
b8cecdf5 11361intel_modeset_pipe_config(struct drm_crtc *crtc,
83a57153
ACO		 11362 struct drm_display_mode *mode,
11363 struct drm_atomic_state *state)
ee7b9f93 11364{
7758a113 11365 struct intel_encoder *encoder;
0b901879
ACO		 11366 struct intel_connector *connector;
11367 struct drm_connector_state *connector_state;
5cec258b 11368 struct intel_crtc_state *pipe_config;
d328c9d7 11369 int base_bpp, ret = -EINVAL;
0b901879 11370 int i;
e29c22c0 11371 bool retry = true;
ee7b9f93 11372
98a221da 11373 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
accfc0c5
DV		 11374 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
11375 return ERR_PTR(-EINVAL);
11376 }
11377
5448a00d 11378 if (!check_digital_port_conflicts(state)) {
00f0b378
VS		 11379 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
11380 return ERR_PTR(-EINVAL);
11381 }
11382
83a57153
ACO		 11383 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
11384 if (IS_ERR(pipe_config))
11385 return pipe_config;
11386
11387 clear_intel_crtc_state(pipe_config);
7758a113 11388
07878248 11389 pipe_config->base.crtc = crtc;
2d112de7
ACO		 11390 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
11391 drm_mode_copy(&pipe_config->base.mode, mode);
37327abd 11392
e143a21c
DV		 11393 pipe_config->cpu_transcoder =
11394 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 11395 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 11396
2960bc9c
ID		 11397 /*
11398 * Sanitize sync polarity flags based on requested ones. If neither
11399 * positive or negative polarity is requested, treat this as meaning
11400 * negative polarity.
11401 */
2d112de7 11402 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11403 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 11404 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 11405
2d112de7 11406 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11407 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 11408 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 11409
050f7aeb
DV		 11410 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11411 * plane pixel format and any sink constraints into account. Returns the
11412 * source plane bpp so that dithering can be selected on mismatches
11413 * after encoders and crtc also have had their say. */
d328c9d7
DV		 11414 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11415 pipe_config);
11416 if (base_bpp < 0)
4e53c2e0
DV		 11417 goto fail;
11418
e41a56be
VS		 11419 /*
11420 * Determine the real pipe dimensions. Note that stereo modes can
11421 * increase the actual pipe size due to the frame doubling and
11422 * insertion of additional space for blanks between the frame. This
11423 * is stored in the crtc timings. We use the requested mode to do this
11424 * computation to clearly distinguish it from the adjusted mode, which
11425 * can be changed by the connectors in the below retry loop.
11426 */
2d112de7 11427 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 11428 &pipe_config->pipe_src_w,
11429 &pipe_config->pipe_src_h);
e41a56be 11430
e29c22c0 11431encoder_retry:
ef1b460d 11432 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 11433 pipe_config->port_clock = 0;
ef1b460d 11434 pipe_config->pixel_multiplier = 1;
ff9a6750 11435
135c81b8 11436 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 11437 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11438 CRTC_STEREO_DOUBLE);
135c81b8 11439
7758a113
DV		 11440 /* Pass our mode to the connectors and the CRTC to give them a chance to
11441 * adjust it according to limitations or connector properties, and also
11442 * a chance to reject the mode entirely.
47f1c6c9 11443 */
0b901879
ACO		 11444 for (i = 0; i < state->num_connector; i++) {
11445 connector = to_intel_connector(state->connectors[i]);
11446 if (!connector)
11447 continue;
47f1c6c9 11448
0b901879
ACO		 11449 connector_state = state->connector_states[i];
11450 if (connector_state->crtc != crtc)
7758a113 11451 continue;
7ae89233 11452
0b901879
ACO		 11453 encoder = to_intel_encoder(connector_state->best_encoder);
11454
efea6e8e
DV		 11455 if (!(encoder->compute_config(encoder, pipe_config))) {
11456 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 11457 goto fail;
11458 }
ee7b9f93 11459 }
47f1c6c9 11460
ff9a6750
DV		 11461 /* Set default port clock if not overwritten by the encoder. Needs to be
11462 * done afterwards in case the encoder adjusts the mode. */
11463 if (!pipe_config->port_clock)
2d112de7 11464 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 11465 * pipe_config->pixel_multiplier;
ff9a6750 11466
a43f6e0f 11467 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 11468 if (ret < 0) {
7758a113
DV		 11469 DRM_DEBUG_KMS("CRTC fixup failed\n");
11470 goto fail;
ee7b9f93 11471 }
e29c22c0
DV		 11472
11473 if (ret == RETRY) {
11474 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11475 ret = -EINVAL;
11476 goto fail;
11477 }
11478
11479 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11480 retry = false;
11481 goto encoder_retry;
11482 }
11483
d328c9d7 11484 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 11485 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 11486 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 11487
b8cecdf5 11488 return pipe_config;
7758a113 11489fail:
e29c22c0 11490 return ERR_PTR(ret);
ee7b9f93 11491}
47f1c6c9 11492
e2e1ed41
DV		 11493/* Computes which crtcs are affected and sets the relevant bits in the mask. For
11494 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
11495static void
11496intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
11497 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 11498{
11499 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 11500 struct drm_device *dev = crtc->dev;
11501 struct intel_encoder *encoder;
11502 struct intel_connector *connector;
11503 struct drm_crtc *tmp_crtc;
79e53945 11504
e2e1ed41 11505 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 11506
e2e1ed41
DV		 11507 /* Check which crtcs have changed outputs connected to them, these need
11508 * to be part of the prepare_pipes mask. We don't (yet) support global
11509 * modeset across multiple crtcs, so modeset_pipes will only have one
11510 * bit set at most. */
3a3371ff 11511 for_each_intel_connector(dev, connector) {
e2e1ed41
DV		 11512 if (connector->base.encoder == &connector->new_encoder->base)
11513 continue;
79e53945 11514
e2e1ed41
DV		 11515 if (connector->base.encoder) {
11516 tmp_crtc = connector->base.encoder->crtc;
11517
11518 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
11519 }
11520
11521 if (connector->new_encoder)
11522 *prepare_pipes |=
11523 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 11524 }
11525
b2784e15 11526 for_each_intel_encoder(dev, encoder) {
e2e1ed41
DV		 11527 if (encoder->base.crtc == &encoder->new_crtc->base)
11528 continue;
11529
11530 if (encoder->base.crtc) {
11531 tmp_crtc = encoder->base.crtc;
11532
11533 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
11534 }
11535
11536 if (encoder->new_crtc)
11537 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 11538 }
11539
7668851f 11540 /* Check for pipes that will be enabled/disabled ... */
d3fcc808 11541 for_each_intel_crtc(dev, intel_crtc) {
83d65738 11542 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
e2e1ed41 11543 continue;
7e7d76c3 11544
7668851f 11545 if (!intel_crtc->new_enabled)
e2e1ed41 11546 *disable_pipes |= 1 << intel_crtc->pipe;
7668851f
VS		 11547 else
11548 *prepare_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 11549 }
11550
e2e1ed41
DV		 11551
11552 /* set_mode is also used to update properties on life display pipes. */
11553 intel_crtc = to_intel_crtc(crtc);
7668851f 11554 if (intel_crtc->new_enabled)
e2e1ed41
DV		 11555 *prepare_pipes |= 1 << intel_crtc->pipe;
11556
b6c5164d
DV		 11557 /*
11558 * For simplicity do a full modeset on any pipe where the output routing
11559 * changed. We could be more clever, but that would require us to be
11560 * more careful with calling the relevant encoder->mode_set functions.
11561 */
e2e1ed41
DV		 11562 if (*prepare_pipes)
11563 *modeset_pipes = *prepare_pipes;
11564
11565 /* ... and mask these out. */
11566 *modeset_pipes &= ~(*disable_pipes);
11567 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 11568
11569 /*
11570 * HACK: We don't (yet) fully support global modesets. intel_set_config
11571 * obies this rule, but the modeset restore mode of
11572 * intel_modeset_setup_hw_state does not.
11573 */
11574 *modeset_pipes &= 1 << intel_crtc->pipe;
11575 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 11576
11577 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
11578 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 11579}
79e53945 11580
ea9d758d 11581static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 11582{
ea9d758d 11583 struct drm_encoder *encoder;
f6e5b160 11584 struct drm_device *dev = crtc->dev;
f6e5b160 11585
ea9d758d
DV		 11586 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11587 if (encoder->crtc == crtc)
11588 return true;
11589
11590 return false;
11591}
11592
11593static void
11594intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
11595{
ba41c0de 11596 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d
DV		 11597 struct intel_encoder *intel_encoder;
11598 struct intel_crtc *intel_crtc;
11599 struct drm_connector *connector;
11600
ba41c0de
DV		 11601 intel_shared_dpll_commit(dev_priv);
11602
b2784e15 11603 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 11604 if (!intel_encoder->base.crtc)
11605 continue;
11606
11607 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
11608
11609 if (prepare_pipes & (1 << intel_crtc->pipe))
11610 intel_encoder->connectors_active = false;
11611 }
11612
11613 intel_modeset_commit_output_state(dev);
11614
7668851f 11615 /* Double check state. */
d3fcc808 11616 for_each_intel_crtc(dev, intel_crtc) {
83d65738 11617 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
ea9d758d
DV		 11618 }
11619
11620 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11621 if (!connector->encoder || !connector->encoder->crtc)
11622 continue;
11623
11624 intel_crtc = to_intel_crtc(connector->encoder->crtc);
11625
11626 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 11627 struct drm_property *dpms_property =
11628 dev->mode_config.dpms_property;
11629
ea9d758d 11630 connector->dpms = DRM_MODE_DPMS_ON;
662595df 11631 drm_object_property_set_value(&connector->base,
68d34720
DV		 11632 dpms_property,
11633 DRM_MODE_DPMS_ON);
ea9d758d
DV		 11634
11635 intel_encoder = to_intel_encoder(connector->encoder);
11636 intel_encoder->connectors_active = true;
11637 }
11638 }
11639
11640}
11641
3bd26263 11642static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 11643{
3bd26263 11644 int diff;
f1f644dc
JB		 11645
11646 if (clock1 == clock2)
11647 return true;
11648
11649 if (!clock1 || !clock2)
11650 return false;
11651
11652 diff = abs(clock1 - clock2);
11653
11654 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11655 return true;
11656
11657 return false;
11658}
11659
25c5b266
DV		 11660#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11661 list_for_each_entry((intel_crtc), \
11662 &(dev)->mode_config.crtc_list, \
11663 base.head) \
0973f18f 11664 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 11665
0e8ffe1b 11666static bool
2fa2fe9a 11667intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 11668 struct intel_crtc_state *current_config,
11669 struct intel_crtc_state *pipe_config)
0e8ffe1b 11670{
66e985c0
DV		 11671#define PIPE_CONF_CHECK_X(name) \
11672 if (current_config->name != pipe_config->name) { \
11673 DRM_ERROR("mismatch in " #name " " \
11674 "(expected 0x%08x, found 0x%08x)\n", \
11675 current_config->name, \
11676 pipe_config->name); \
11677 return false; \
11678 }
11679
08a24034
DV		 11680#define PIPE_CONF_CHECK_I(name) \
11681 if (current_config->name != pipe_config->name) { \
11682 DRM_ERROR("mismatch in " #name " " \
11683 "(expected %i, found %i)\n", \
11684 current_config->name, \
11685 pipe_config->name); \
11686 return false; \
88adfff1
DV		 11687 }
11688
b95af8be
VK		 11689/* This is required for BDW+ where there is only one set of registers for
11690 * switching between high and low RR.
11691 * This macro can be used whenever a comparison has to be made between one
11692 * hw state and multiple sw state variables.
11693 */
11694#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11695 if ((current_config->name != pipe_config->name) && \
11696 (current_config->alt_name != pipe_config->name)) { \
11697 DRM_ERROR("mismatch in " #name " " \
11698 "(expected %i or %i, found %i)\n", \
11699 current_config->name, \
11700 current_config->alt_name, \
11701 pipe_config->name); \
11702 return false; \
11703 }
11704
1bd1bd80
DV		 11705#define PIPE_CONF_CHECK_FLAGS(name, mask) \
11706 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 11707 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 11708 "(expected %i, found %i)\n", \
11709 current_config->name & (mask), \
11710 pipe_config->name & (mask)); \
11711 return false; \
11712 }
11713
5e550656
VS		 11714#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11715 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11716 DRM_ERROR("mismatch in " #name " " \
11717 "(expected %i, found %i)\n", \
11718 current_config->name, \
11719 pipe_config->name); \
11720 return false; \
11721 }
11722
bb760063
DV		 11723#define PIPE_CONF_QUIRK(quirk) \
11724 ((current_config->quirks | pipe_config->quirks) & (quirk))
11725
eccb140b
DV		 11726 PIPE_CONF_CHECK_I(cpu_transcoder);
11727
08a24034
DV		 11728 PIPE_CONF_CHECK_I(has_pch_encoder);
11729 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 11730 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
11731 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
11732 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
11733 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
11734 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 11735
eb14cb74 11736 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 11737
11738 if (INTEL_INFO(dev)->gen < 8) {
11739 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
11740 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
11741 PIPE_CONF_CHECK_I(dp_m_n.link_m);
11742 PIPE_CONF_CHECK_I(dp_m_n.link_n);
11743 PIPE_CONF_CHECK_I(dp_m_n.tu);
11744
11745 if (current_config->has_drrs) {
11746 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
11747 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
11748 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
11749 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
11750 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
11751 }
11752 } else {
11753 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
11754 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
11755 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
11756 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
11757 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11758 }
eb14cb74 11759
2d112de7
ACO		 11760 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11761 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11762 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11763 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11764 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11765 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 11766
2d112de7
ACO		 11767 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11768 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11769 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11770 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11771 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11772 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 11773
c93f54cf 11774 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 11775 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 11776 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11777 IS_VALLEYVIEW(dev))
11778 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 11779 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 11780
9ed109a7
DV		 11781 PIPE_CONF_CHECK_I(has_audio);
11782
2d112de7 11783 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 11784 DRM_MODE_FLAG_INTERLACE);
11785
bb760063 11786 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 11787 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11788 DRM_MODE_FLAG_PHSYNC);
2d112de7 11789 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11790 DRM_MODE_FLAG_NHSYNC);
2d112de7 11791 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11792 DRM_MODE_FLAG_PVSYNC);
2d112de7 11793 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 11794 DRM_MODE_FLAG_NVSYNC);
11795 }
045ac3b5 11796
37327abd
VS		 11797 PIPE_CONF_CHECK_I(pipe_src_w);
11798 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 11799
9953599b
DV		 11800 /*
11801 * FIXME: BIOS likes to set up a cloned config with lvds+external
11802 * screen. Since we don't yet re-compute the pipe config when moving
11803 * just the lvds port away to another pipe the sw tracking won't match.
11804 *
11805 * Proper atomic modesets with recomputed global state will fix this.
11806 * Until then just don't check gmch state for inherited modes.
11807 */
11808 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11809 PIPE_CONF_CHECK_I(gmch_pfit.control);
11810 /* pfit ratios are autocomputed by the hw on gen4+ */
11811 if (INTEL_INFO(dev)->gen < 4)
11812 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11813 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11814 }
11815
fd4daa9c
CW		 11816 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11817 if (current_config->pch_pfit.enabled) {
11818 PIPE_CONF_CHECK_I(pch_pfit.pos);
11819 PIPE_CONF_CHECK_I(pch_pfit.size);
11820 }
2fa2fe9a 11821
a1b2278e
CK		 11822 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11823
e59150dc
JB		 11824 /* BDW+ don't expose a synchronous way to read the state */
11825 if (IS_HASWELL(dev))
11826 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 11827
282740f7
VS		 11828 PIPE_CONF_CHECK_I(double_wide);
11829
26804afd
DV		 11830 PIPE_CONF_CHECK_X(ddi_pll_sel);
11831
c0d43d62 11832 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 11833 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 11834 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 11835 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11836 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 11837 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 11838 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11839 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11840 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 11841
42571aef
VS		 11842 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11843 PIPE_CONF_CHECK_I(pipe_bpp);
11844
2d112de7 11845 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 11846 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 11847
66e985c0 11848#undef PIPE_CONF_CHECK_X
08a24034 11849#undef PIPE_CONF_CHECK_I
b95af8be 11850#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 11851#undef PIPE_CONF_CHECK_FLAGS
5e550656 11852#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 11853#undef PIPE_CONF_QUIRK
88adfff1 11854
0e8ffe1b
DV		 11855 return true;
11856}
11857
08db6652
DL		 11858static void check_wm_state(struct drm_device *dev)
11859{
11860 struct drm_i915_private *dev_priv = dev->dev_private;
11861 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11862 struct intel_crtc *intel_crtc;
11863 int plane;
11864
11865 if (INTEL_INFO(dev)->gen < 9)
11866 return;
11867
11868 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11869 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11870
11871 for_each_intel_crtc(dev, intel_crtc) {
11872 struct skl_ddb_entry *hw_entry, *sw_entry;
11873 const enum pipe pipe = intel_crtc->pipe;
11874
11875 if (!intel_crtc->active)
11876 continue;
11877
11878 /* planes */
dd740780 11879 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 11880 hw_entry = &hw_ddb.plane[pipe][plane];
11881 sw_entry = &sw_ddb->plane[pipe][plane];
11882
11883 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11884 continue;
11885
11886 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11887 "(expected (%u,%u), found (%u,%u))\n",
11888 pipe_name(pipe), plane + 1,
11889 sw_entry->start, sw_entry->end,
11890 hw_entry->start, hw_entry->end);
11891 }
11892
11893 /* cursor */
11894 hw_entry = &hw_ddb.cursor[pipe];
11895 sw_entry = &sw_ddb->cursor[pipe];
11896
11897 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11898 continue;
11899
11900 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11901 "(expected (%u,%u), found (%u,%u))\n",
11902 pipe_name(pipe),
11903 sw_entry->start, sw_entry->end,
11904 hw_entry->start, hw_entry->end);
11905 }
11906}
11907
91d1b4bd
DV		 11908static void
11909check_connector_state(struct drm_device *dev)
8af6cf88 11910{
8af6cf88
DV		 11911 struct intel_connector *connector;
11912
3a3371ff 11913 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11914 /* This also checks the encoder/connector hw state with the
11915 * ->get_hw_state callbacks. */
11916 intel_connector_check_state(connector);
11917
e2c719b7 11918 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 11919 "connector's staged encoder doesn't match current encoder\n");
11920 }
91d1b4bd
DV		 11921}
11922
11923static void
11924check_encoder_state(struct drm_device *dev)
11925{
11926 struct intel_encoder *encoder;
11927 struct intel_connector *connector;
8af6cf88 11928
b2784e15 11929 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 11930 bool enabled = false;
11931 bool active = false;
11932 enum pipe pipe, tracked_pipe;
11933
11934 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11935 encoder->base.base.id,
8e329a03 11936 encoder->base.name);
8af6cf88 11937
e2c719b7 11938 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 11939 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 11940 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 11941 "encoder's active_connectors set, but no crtc\n");
11942
3a3371ff 11943 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11944 if (connector->base.encoder != &encoder->base)
11945 continue;
11946 enabled = true;
11947 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11948 active = true;
11949 }
0e32b39c
DA		 11950 /*
11951 * for MST connectors if we unplug the connector is gone
11952 * away but the encoder is still connected to a crtc
11953 * until a modeset happens in response to the hotplug.
11954 */
11955 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11956 continue;
11957
e2c719b7 11958 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 11959 "encoder's enabled state mismatch "
11960 "(expected %i, found %i)\n",
11961 !!encoder->base.crtc, enabled);
e2c719b7 11962 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 11963 "active encoder with no crtc\n");
11964
e2c719b7 11965 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 11966 "encoder's computed active state doesn't match tracked active state "
11967 "(expected %i, found %i)\n", active, encoder->connectors_active);
11968
11969 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 11970 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 11971 "encoder's hw state doesn't match sw tracking "
11972 "(expected %i, found %i)\n",
11973 encoder->connectors_active, active);
11974
11975 if (!encoder->base.crtc)
11976 continue;
11977
11978 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 11979 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 11980 "active encoder's pipe doesn't match"
11981 "(expected %i, found %i)\n",
11982 tracked_pipe, pipe);
11983
11984 }
91d1b4bd
DV		 11985}
11986
11987static void
11988check_crtc_state(struct drm_device *dev)
11989{
fbee40df 11990 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 11991 struct intel_crtc *crtc;
11992 struct intel_encoder *encoder;
5cec258b 11993 struct intel_crtc_state pipe_config;
8af6cf88 11994
d3fcc808 11995 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 11996 bool enabled = false;
11997 bool active = false;
11998
045ac3b5
JB		 11999 memset(&pipe_config, 0, sizeof(pipe_config));
12000
8af6cf88
DV		 12001 DRM_DEBUG_KMS("[CRTC:%d]\n",
12002 crtc->base.base.id);
12003
83d65738 12004 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 12005 "active crtc, but not enabled in sw tracking\n");
12006
b2784e15 12007 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12008 if (encoder->base.crtc != &crtc->base)
12009 continue;
12010 enabled = true;
12011 if (encoder->connectors_active)
12012 active = true;
12013 }
6c49f241 12014
e2c719b7 12015 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 12016 "crtc's computed active state doesn't match tracked active state "
12017 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12018 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12019 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 12020 "(expected %i, found %i)\n", enabled,
12021 crtc->base.state->enable);
8af6cf88 12022
0e8ffe1b
DV		 12023 active = dev_priv->display.get_pipe_config(crtc,
12024 &pipe_config);
d62cf62a 12025
b6b5d049
VS		 12026 /* hw state is inconsistent with the pipe quirk */
12027 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12028 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 12029 active = crtc->active;
12030
b2784e15 12031 for_each_intel_encoder(dev, encoder) {
3eaba51c 12032 enum pipe pipe;
6c49f241
DV		 12033 if (encoder->base.crtc != &crtc->base)
12034 continue;
1d37b689 12035 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 12036 encoder->get_config(encoder, &pipe_config);
12037 }
12038
e2c719b7 12039 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 12040 "crtc active state doesn't match with hw state "
12041 "(expected %i, found %i)\n", crtc->active, active);
12042
c0b03411 12043 if (active &&
6e3c9717 12044 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 12045 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 12046 intel_dump_pipe_config(crtc, &pipe_config,
12047 "[hw state]");
6e3c9717 12048 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12049 "[sw state]");
12050 }
8af6cf88
DV		 12051 }
12052}
12053
91d1b4bd
DV		 12054static void
12055check_shared_dpll_state(struct drm_device *dev)
12056{
fbee40df 12057 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12058 struct intel_crtc *crtc;
12059 struct intel_dpll_hw_state dpll_hw_state;
12060 int i;
5358901f
DV		 12061
12062 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12063 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12064 int enabled_crtcs = 0, active_crtcs = 0;
12065 bool active;
12066
12067 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12068
12069 DRM_DEBUG_KMS("%s\n", pll->name);
12070
12071 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12072
e2c719b7 12073 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12074 "more active pll users than references: %i vs %i\n",
3e369b76 12075 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12076 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12077 "pll in active use but not on in sw tracking\n");
e2c719b7 12078 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12079 "pll in on but not on in use in sw tracking\n");
e2c719b7 12080 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12081 "pll on state mismatch (expected %i, found %i)\n",
12082 pll->on, active);
12083
d3fcc808 12084 for_each_intel_crtc(dev, crtc) {
83d65738 12085 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12086 enabled_crtcs++;
12087 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12088 active_crtcs++;
12089 }
e2c719b7 12090 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12091 "pll active crtcs mismatch (expected %i, found %i)\n",
12092 pll->active, active_crtcs);
e2c719b7 12093 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12094 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12095 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12096
e2c719b7 12097 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12098 sizeof(dpll_hw_state)),
12099 "pll hw state mismatch\n");
5358901f 12100 }
8af6cf88
DV		 12101}
12102
91d1b4bd
DV		 12103void
12104intel_modeset_check_state(struct drm_device *dev)
12105{
08db6652 12106 check_wm_state(dev);
91d1b4bd
DV		 12107 check_connector_state(dev);
12108 check_encoder_state(dev);
12109 check_crtc_state(dev);
12110 check_shared_dpll_state(dev);
12111}
12112
5cec258b 12113void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12114 int dotclock)
12115{
12116 /*
12117 * FDI already provided one idea for the dotclock.
12118 * Yell if the encoder disagrees.
12119 */
2d112de7 12120 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12121 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12122 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12123}
12124
80715b2f
VS		 12125static void update_scanline_offset(struct intel_crtc *crtc)
12126{
12127 struct drm_device *dev = crtc->base.dev;
12128
12129 /*
12130 * The scanline counter increments at the leading edge of hsync.
12131 *
12132 * On most platforms it starts counting from vtotal-1 on the
12133 * first active line. That means the scanline counter value is
12134 * always one less than what we would expect. Ie. just after
12135 * start of vblank, which also occurs at start of hsync (on the
12136 * last active line), the scanline counter will read vblank_start-1.
12137 *
12138 * On gen2 the scanline counter starts counting from 1 instead
12139 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12140 * to keep the value positive), instead of adding one.
12141 *
12142 * On HSW+ the behaviour of the scanline counter depends on the output
12143 * type. For DP ports it behaves like most other platforms, but on HDMI
12144 * there's an extra 1 line difference. So we need to add two instead of
12145 * one to the value.
12146 */
12147 if (IS_GEN2(dev)) {
6e3c9717 12148 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12149 int vtotal;
12150
12151 vtotal = mode->crtc_vtotal;
12152 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12153 vtotal /= 2;
12154
12155 crtc->scanline_offset = vtotal - 1;
12156 } else if (HAS_DDI(dev) &&
409ee761 12157 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12158 crtc->scanline_offset = 2;
12159 } else
12160 crtc->scanline_offset = 1;
12161}
12162
5cec258b 12163static struct intel_crtc_state *
7f27126e
JB		 12164intel_modeset_compute_config(struct drm_crtc *crtc,
12165 struct drm_display_mode *mode,
83a57153 12166 struct drm_atomic_state *state,
7f27126e
JB		 12167 unsigned *modeset_pipes,
12168 unsigned *prepare_pipes,
12169 unsigned *disable_pipes)
12170{
db7542dd 12171 struct drm_device *dev = crtc->dev;
5cec258b 12172 struct intel_crtc_state *pipe_config = NULL;
db7542dd 12173 struct intel_crtc *intel_crtc;
0b901879
ACO		 12174 int ret = 0;
12175
12176 ret = drm_atomic_add_affected_connectors(state, crtc);
12177 if (ret)
12178 return ERR_PTR(ret);
7f27126e
JB		 12179
12180 intel_modeset_affected_pipes(crtc, modeset_pipes,
12181 prepare_pipes, disable_pipes);
12182
db7542dd
ACO		 12183 for_each_intel_crtc_masked(dev, *disable_pipes, intel_crtc) {
12184 pipe_config = intel_atomic_get_crtc_state(state, intel_crtc);
12185 if (IS_ERR(pipe_config))
12186 return pipe_config;
12187
12188 pipe_config->base.enable = false;
12189 }
7f27126e
JB		 12190
12191 /*
12192 * Note this needs changes when we start tracking multiple modes
12193 * and crtcs. At that point we'll need to compute the whole config
12194 * (i.e. one pipe_config for each crtc) rather than just the one
12195 * for this crtc.
12196 */
db7542dd
ACO		 12197 for_each_intel_crtc_masked(dev, *modeset_pipes, intel_crtc) {
12198 /* FIXME: For now we still expect modeset_pipes has at most
12199 * one bit set. */
12200 if (WARN_ON(&intel_crtc->base != crtc))
12201 continue;
83a57153 12202
8805aa71 12203 pipe_config = intel_modeset_pipe_config(crtc, mode, state);
db7542dd
ACO		 12204 if (IS_ERR(pipe_config))
12205 return pipe_config;
7f27126e 12206
304603f4
ACO		 12207 pipe_config->base.enable = true;
12208
db7542dd
ACO		 12209 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
12210 "[modeset]");
12211 }
12212
12213 return intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));;
7f27126e
JB		 12214}
12215
225da59b 12216static int __intel_set_mode_setup_plls(struct drm_atomic_state *state,
ed6739ef
ACO		 12217 unsigned modeset_pipes,
12218 unsigned disable_pipes)
12219{
225da59b 12220 struct drm_device *dev = state->dev;
ed6739ef
ACO		 12221 struct drm_i915_private *dev_priv = to_i915(dev);
12222 unsigned clear_pipes = modeset_pipes | disable_pipes;
12223 struct intel_crtc *intel_crtc;
12224 int ret = 0;
12225
12226 if (!dev_priv->display.crtc_compute_clock)
12227 return 0;
12228
12229 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12230 if (ret)
12231 goto done;
12232
12233 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
225da59b
ACO		 12234 struct intel_crtc_state *crtc_state =
12235 intel_atomic_get_crtc_state(state, intel_crtc);
12236
12237 /* Modeset pipes should have a new state by now */
12238 if (WARN_ON(IS_ERR(crtc_state)))
12239 continue;
12240
ed6739ef 12241 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
225da59b 12242 crtc_state);
ed6739ef
ACO		 12243 if (ret) {
12244 intel_shared_dpll_abort_config(dev_priv);
12245 goto done;
12246 }
12247 }
12248
12249done:
12250 return ret;
12251}
12252
f30da187
DV		 12253static int __intel_set_mode(struct drm_crtc *crtc,
12254 struct drm_display_mode *mode,
7f27126e 12255 int x, int y, struct drm_framebuffer *fb,
5cec258b 12256 struct intel_crtc_state *pipe_config,
7f27126e
JB		 12257 unsigned modeset_pipes,
12258 unsigned prepare_pipes,
12259 unsigned disable_pipes)
a6778b3c
DV		 12260{
12261 struct drm_device *dev = crtc->dev;
fbee40df 12262 struct drm_i915_private *dev_priv = dev->dev_private;
4b4b9238 12263 struct drm_display_mode *saved_mode;
304603f4 12264 struct drm_atomic_state *state = pipe_config->base.state;
83a57153 12265 struct intel_crtc_state *crtc_state_copy = NULL;
25c5b266 12266 struct intel_crtc *intel_crtc;
c0c36b94 12267 int ret = 0;
a6778b3c 12268
4b4b9238 12269 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 12270 if (!saved_mode)
12271 return -ENOMEM;
a6778b3c 12272
83a57153
ACO		 12273 crtc_state_copy = kmalloc(sizeof(*crtc_state_copy), GFP_KERNEL);
12274 if (!crtc_state_copy) {
12275 ret = -ENOMEM;
12276 goto done;
12277 }
12278
3ac18232 12279 *saved_mode = crtc->mode;
a6778b3c 12280
30a970c6
JB		 12281 /*
12282 * See if the config requires any additional preparation, e.g.
12283 * to adjust global state with pipes off. We need to do this
12284 * here so we can get the modeset_pipe updated config for the new
12285 * mode set on this crtc. For other crtcs we need to use the
12286 * adjusted_mode bits in the crtc directly.
12287 */
f8437dd1 12288 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
304603f4
ACO		 12289 ret = valleyview_modeset_global_pipes(state, &prepare_pipes);
12290 if (ret)
12291 goto done;
30a970c6 12292
c164f833
VS		 12293 /* may have added more to prepare_pipes than we should */
12294 prepare_pipes &= ~disable_pipes;
12295 }
12296
225da59b 12297 ret = __intel_set_mode_setup_plls(state, modeset_pipes, disable_pipes);
ed6739ef
ACO		 12298 if (ret)
12299 goto done;
8bd31e67 12300
460da916
DV		 12301 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
12302 intel_crtc_disable(&intel_crtc->base);
12303
ea9d758d 12304 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
83d65738 12305 if (intel_crtc->base.state->enable)
ea9d758d
DV		 12306 dev_priv->display.crtc_disable(&intel_crtc->base);
12307 }
a6778b3c 12308
6c4c86f5
DV		 12309 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12310 * to set it here already despite that we pass it down the callchain.
7f27126e
JB		 12311 *
12312 * Note we'll need to fix this up when we start tracking multiple
12313 * pipes; here we assume a single modeset_pipe and only track the
12314 * single crtc and mode.
f6e5b160 12315 */
b8cecdf5 12316 if (modeset_pipes) {
25c5b266 12317 crtc->mode = *mode;
b8cecdf5
DV		 12318 /* mode_set/enable/disable functions rely on a correct pipe
12319 * config. */
f5de6e07 12320 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
c326c0a9
VS		 12321
12322 /*
12323 * Calculate and store various constants which
12324 * are later needed by vblank and swap-completion
12325 * timestamping. They are derived from true hwmode.
12326 */
12327 drm_calc_timestamping_constants(crtc,
2d112de7 12328 &pipe_config->base.adjusted_mode);
b8cecdf5 12329 }
7758a113 12330
ea9d758d
DV		 12331 /* Only after disabling all output pipelines that will be changed can we
12332 * update the the output configuration. */
12333 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 12334
304603f4 12335 modeset_update_crtc_power_domains(state);
47fab737 12336
25c5b266 12337 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
455a6808
GP		 12338 struct drm_plane *primary = intel_crtc->base.primary;
12339 int vdisplay, hdisplay;
4c10794f 12340
455a6808 12341 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
70a101f8
MR		 12342 ret = drm_plane_helper_update(primary, &intel_crtc->base,
12343 fb, 0, 0,
12344 hdisplay, vdisplay,
12345 x << 16, y << 16,
12346 hdisplay << 16, vdisplay << 16);
a6778b3c
DV		 12347 }
12348
12349 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
80715b2f
VS		 12350 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
12351 update_scanline_offset(intel_crtc);
12352
25c5b266 12353 dev_priv->display.crtc_enable(&intel_crtc->base);
80715b2f 12354 }
a6778b3c 12355
a6778b3c
DV		 12356 /* FIXME: add subpixel order */
12357done:
83d65738 12358 if (ret && crtc->state->enable)
3ac18232 12359 crtc->mode = *saved_mode;
a6778b3c 12360
83a57153
ACO		 12361 if (ret == 0 && pipe_config) {
12362 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12363
12364 /* The pipe_config will be freed with the atomic state, so
12365 * make a copy. */
12366 memcpy(crtc_state_copy, intel_crtc->config,
12367 sizeof *crtc_state_copy);
12368 intel_crtc->config = crtc_state_copy;
12369 intel_crtc->base.state = &crtc_state_copy->base;
83a57153
ACO		 12370 } else {
12371 kfree(crtc_state_copy);
12372 }
12373
3ac18232 12374 kfree(saved_mode);
a6778b3c 12375 return ret;
f6e5b160
CW		 12376}
12377
7f27126e
JB		 12378static int intel_set_mode_pipes(struct drm_crtc *crtc,
12379 struct drm_display_mode *mode,
12380 int x, int y, struct drm_framebuffer *fb,
5cec258b 12381 struct intel_crtc_state *pipe_config,
7f27126e
JB		 12382 unsigned modeset_pipes,
12383 unsigned prepare_pipes,
12384 unsigned disable_pipes)
f30da187
DV		 12385{
12386 int ret;
12387
7f27126e
JB		 12388 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
12389 prepare_pipes, disable_pipes);
f30da187
DV		 12390
12391 if (ret == 0)
12392 intel_modeset_check_state(crtc->dev);
12393
12394 return ret;
12395}
12396
7f27126e
JB		 12397static int intel_set_mode(struct drm_crtc *crtc,
12398 struct drm_display_mode *mode,
83a57153
ACO		 12399 int x, int y, struct drm_framebuffer *fb,
12400 struct drm_atomic_state *state)
7f27126e 12401{
5cec258b 12402 struct intel_crtc_state *pipe_config;
7f27126e 12403 unsigned modeset_pipes, prepare_pipes, disable_pipes;
83a57153 12404 int ret = 0;
7f27126e 12405
8805aa71 12406 pipe_config = intel_modeset_compute_config(crtc, mode, state,
7f27126e
JB		 12407 &modeset_pipes,
12408 &prepare_pipes,
12409 &disable_pipes);
12410
83a57153
ACO		 12411 if (IS_ERR(pipe_config)) {
12412 ret = PTR_ERR(pipe_config);
12413 goto out;
12414 }
12415
12416 ret = intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
12417 modeset_pipes, prepare_pipes,
12418 disable_pipes);
12419 if (ret)
12420 goto out;
7f27126e 12421
83a57153
ACO		 12422out:
12423 return ret;
7f27126e
JB		 12424}
12425
c0c36b94
CW		 12426void intel_crtc_restore_mode(struct drm_crtc *crtc)
12427{
83a57153
ACO		 12428 struct drm_device *dev = crtc->dev;
12429 struct drm_atomic_state *state;
12430 struct intel_encoder *encoder;
12431 struct intel_connector *connector;
12432 struct drm_connector_state *connector_state;
12433
12434 state = drm_atomic_state_alloc(dev);
12435 if (!state) {
12436 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12437 crtc->base.id);
12438 return;
12439 }
12440
12441 state->acquire_ctx = dev->mode_config.acquire_ctx;
12442
12443 /* The force restore path in the HW readout code relies on the staged
12444 * config still keeping the user requested config while the actual
12445 * state has been overwritten by the configuration read from HW. We
12446 * need to copy the staged config to the atomic state, otherwise the
12447 * mode set will just reapply the state the HW is already in. */
12448 for_each_intel_encoder(dev, encoder) {
12449 if (&encoder->new_crtc->base != crtc)
12450 continue;
12451
12452 for_each_intel_connector(dev, connector) {
12453 if (connector->new_encoder != encoder)
12454 continue;
12455
12456 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12457 if (IS_ERR(connector_state)) {
12458 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12459 connector->base.base.id,
12460 connector->base.name,
12461 PTR_ERR(connector_state));
12462 continue;
12463 }
12464
12465 connector_state->crtc = crtc;
12466 connector_state->best_encoder = &encoder->base;
12467 }
12468 }
12469
12470 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb,
12471 state);
12472
12473 drm_atomic_state_free(state);
c0c36b94
CW		 12474}
12475
25c5b266
DV		 12476#undef for_each_intel_crtc_masked
12477
d9e55608
DV		 12478static void intel_set_config_free(struct intel_set_config *config)
12479{
12480 if (!config)
12481 return;
12482
1aa4b628
DV		 12483 kfree(config->save_connector_encoders);
12484 kfree(config->save_encoder_crtcs);
7668851f 12485 kfree(config->save_crtc_enabled);
d9e55608
DV		 12486 kfree(config);
12487}
12488
85f9eb71
DV		 12489static int intel_set_config_save_state(struct drm_device *dev,
12490 struct intel_set_config *config)
12491{
7668851f 12492 struct drm_crtc *crtc;
85f9eb71
DV		 12493 struct drm_encoder *encoder;
12494 struct drm_connector *connector;
12495 int count;
12496
7668851f
VS		 12497 config->save_crtc_enabled =
12498 kcalloc(dev->mode_config.num_crtc,
12499 sizeof(bool), GFP_KERNEL);
12500 if (!config->save_crtc_enabled)
12501 return -ENOMEM;
12502
1aa4b628
DV		 12503 config->save_encoder_crtcs =
12504 kcalloc(dev->mode_config.num_encoder,
12505 sizeof(struct drm_crtc *), GFP_KERNEL);
12506 if (!config->save_encoder_crtcs)
85f9eb71
DV		 12507 return -ENOMEM;
12508
1aa4b628
DV		 12509 config->save_connector_encoders =
12510 kcalloc(dev->mode_config.num_connector,
12511 sizeof(struct drm_encoder *), GFP_KERNEL);
12512 if (!config->save_connector_encoders)
85f9eb71
DV		 12513 return -ENOMEM;
12514
12515 /* Copy data. Note that driver private data is not affected.
12516 * Should anything bad happen only the expected state is
12517 * restored, not the drivers personal bookkeeping.
12518 */
7668851f 12519 count = 0;
70e1e0ec 12520 for_each_crtc(dev, crtc) {
83d65738 12521 config->save_crtc_enabled[count++] = crtc->state->enable;
7668851f
VS		 12522 }
12523
85f9eb71
DV		 12524 count = 0;
12525 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 12526 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 12527 }
12528
12529 count = 0;
12530 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 12531 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 12532 }
12533
12534 return 0;
12535}
12536
12537static void intel_set_config_restore_state(struct drm_device *dev,
12538 struct intel_set_config *config)
12539{
7668851f 12540 struct intel_crtc *crtc;
9a935856
DV		 12541 struct intel_encoder *encoder;
12542 struct intel_connector *connector;
85f9eb71
DV		 12543 int count;
12544
7668851f 12545 count = 0;
d3fcc808 12546 for_each_intel_crtc(dev, crtc) {
7668851f
VS		 12547 crtc->new_enabled = config->save_crtc_enabled[count++];
12548 }
12549
85f9eb71 12550 count = 0;
b2784e15 12551 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 12552 encoder->new_crtc =
12553 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 12554 }
12555
12556 count = 0;
3a3371ff 12557 for_each_intel_connector(dev, connector) {
9a935856
DV		 12558 connector->new_encoder =
12559 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 12560 }
12561}
12562
e3de42b6 12563static bool
2e57f47d 12564is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 12565{
12566 int i;
12567
2e57f47d
CW		 12568 if (set->num_connectors == 0)
12569 return false;
12570
12571 if (WARN_ON(set->connectors == NULL))
12572 return false;
12573
12574 for (i = 0; i < set->num_connectors; i++)
12575 if (set->connectors[i]->encoder &&
12576 set->connectors[i]->encoder->crtc == set->crtc &&
12577 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 12578 return true;
12579
12580 return false;
12581}
12582
5e2b584e
DV		 12583static void
12584intel_set_config_compute_mode_changes(struct drm_mode_set *set,
12585 struct intel_set_config *config)
12586{
12587
12588 /* We should be able to check here if the fb has the same properties
12589 * and then just flip_or_move it */
2e57f47d
CW		 12590 if (is_crtc_connector_off(set)) {
12591 config->mode_changed = true;
f4510a27 12592 } else if (set->crtc->primary->fb != set->fb) {
3b150f08
MR		 12593 /*
12594 * If we have no fb, we can only flip as long as the crtc is
12595 * active, otherwise we need a full mode set. The crtc may
12596 * be active if we've only disabled the primary plane, or
12597 * in fastboot situations.
12598 */
f4510a27 12599 if (set->crtc->primary->fb == NULL) {
319d9827
JB		 12600 struct intel_crtc *intel_crtc =
12601 to_intel_crtc(set->crtc);
12602
3b150f08 12603 if (intel_crtc->active) {
319d9827
JB		 12604 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
12605 config->fb_changed = true;
12606 } else {
12607 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
12608 config->mode_changed = true;
12609 }
5e2b584e
DV		 12610 } else if (set->fb == NULL) {
12611 config->mode_changed = true;
72f4901e 12612 } else if (set->fb->pixel_format !=
f4510a27 12613 set->crtc->primary->fb->pixel_format) {
5e2b584e 12614 config->mode_changed = true;
e3de42b6 12615 } else {
5e2b584e 12616 config->fb_changed = true;
e3de42b6 12617 }
5e2b584e
DV		 12618 }
12619
835c5873 12620 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 12621 config->fb_changed = true;
12622
12623 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
12624 DRM_DEBUG_KMS("modes are different, full mode set\n");
12625 drm_mode_debug_printmodeline(&set->crtc->mode);
12626 drm_mode_debug_printmodeline(set->mode);
12627 config->mode_changed = true;
12628 }
a1d95703
CW		 12629
12630 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
12631 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 12632}
12633
2e431051 12634static int
9a935856
DV		 12635intel_modeset_stage_output_state(struct drm_device *dev,
12636 struct drm_mode_set *set,
944b0c76
ACO		 12637 struct intel_set_config *config,
12638 struct drm_atomic_state *state)
50f56119 12639{
9a935856 12640 struct intel_connector *connector;
944b0c76 12641 struct drm_connector_state *connector_state;
9a935856 12642 struct intel_encoder *encoder;
7668851f 12643 struct intel_crtc *crtc;
f3f08572 12644 int ro;
50f56119 12645
9abdda74 12646 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 12647 * of connectors. For paranoia, double-check this. */
12648 WARN_ON(!set->fb && (set->num_connectors != 0));
12649 WARN_ON(set->fb && (set->num_connectors == 0));
12650
3a3371ff 12651 for_each_intel_connector(dev, connector) {
9a935856
DV		 12652 /* Otherwise traverse passed in connector list and get encoders
12653 * for them. */
50f56119 12654 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 12655 if (set->connectors[ro] == &connector->base) {
0e32b39c 12656 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
50f56119
DV		 12657 break;
12658 }
12659 }
12660
9a935856
DV		 12661 /* If we disable the crtc, disable all its connectors. Also, if
12662 * the connector is on the changing crtc but not on the new
12663 * connector list, disable it. */
12664 if ((!set->fb || ro == set->num_connectors) &&
12665 connector->base.encoder &&
12666 connector->base.encoder->crtc == set->crtc) {
12667 connector->new_encoder = NULL;
12668
12669 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12670 connector->base.base.id,
c23cc417 12671 connector->base.name);
9a935856
DV		 12672 }
12673
12674
12675 if (&connector->new_encoder->base != connector->base.encoder) {
10634189
ACO		 12676 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
12677 connector->base.base.id,
12678 connector->base.name);
5e2b584e 12679 config->mode_changed = true;
50f56119
DV		 12680 }
12681 }
9a935856 12682 /* connector->new_encoder is now updated for all connectors. */
50f56119 12683
9a935856 12684 /* Update crtc of enabled connectors. */
3a3371ff 12685 for_each_intel_connector(dev, connector) {
7668851f
VS		 12686 struct drm_crtc *new_crtc;
12687
9a935856 12688 if (!connector->new_encoder)
50f56119
DV		 12689 continue;
12690
9a935856 12691 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 12692
12693 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 12694 if (set->connectors[ro] == &connector->base)
50f56119
DV		 12695 new_crtc = set->crtc;
12696 }
12697
12698 /* Make sure the new CRTC will work with the encoder */
14509916
TR		 12699 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
12700 new_crtc)) {
5e2b584e 12701 return -EINVAL;
50f56119 12702 }
0e32b39c 12703 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
9a935856 12704
944b0c76
ACO		 12705 connector_state =
12706 drm_atomic_get_connector_state(state, &connector->base);
12707 if (IS_ERR(connector_state))
12708 return PTR_ERR(connector_state);
12709
12710 connector_state->crtc = new_crtc;
12711 connector_state->best_encoder = &connector->new_encoder->base;
12712
9a935856
DV		 12713 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12714 connector->base.base.id,
c23cc417 12715 connector->base.name,
9a935856
DV		 12716 new_crtc->base.id);
12717 }
12718
12719 /* Check for any encoders that needs to be disabled. */
b2784e15 12720 for_each_intel_encoder(dev, encoder) {
5a65f358 12721 int num_connectors = 0;
3a3371ff 12722 for_each_intel_connector(dev, connector) {
9a935856
DV		 12723 if (connector->new_encoder == encoder) {
12724 WARN_ON(!connector->new_encoder->new_crtc);
5a65f358 12725 num_connectors++;
9a935856
DV		 12726 }
12727 }
5a65f358
PZ		 12728
12729 if (num_connectors == 0)
12730 encoder->new_crtc = NULL;
12731 else if (num_connectors > 1)
12732 return -EINVAL;
12733
9a935856
DV		 12734 /* Only now check for crtc changes so we don't miss encoders
12735 * that will be disabled. */
12736 if (&encoder->new_crtc->base != encoder->base.crtc) {
10634189
ACO		 12737 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
12738 encoder->base.base.id,
12739 encoder->base.name);
5e2b584e 12740 config->mode_changed = true;
50f56119
DV		 12741 }
12742 }
9a935856 12743 /* Now we've also updated encoder->new_crtc for all encoders. */
3a3371ff 12744 for_each_intel_connector(dev, connector) {
944b0c76
ACO		 12745 connector_state =
12746 drm_atomic_get_connector_state(state, &connector->base);
9d918c15
ACO		 12747 if (IS_ERR(connector_state))
12748 return PTR_ERR(connector_state);
944b0c76
ACO		 12749
12750 if (connector->new_encoder) {
0e32b39c
DA		 12751 if (connector->new_encoder != connector->encoder)
12752 connector->encoder = connector->new_encoder;
944b0c76
ACO		 12753 } else {
12754 connector_state->crtc = NULL;
f61cccf3 12755 connector_state->best_encoder = NULL;
944b0c76 12756 }
0e32b39c 12757 }
d3fcc808 12758 for_each_intel_crtc(dev, crtc) {
7668851f
VS		 12759 crtc->new_enabled = false;
12760
b2784e15 12761 for_each_intel_encoder(dev, encoder) {
7668851f
VS		 12762 if (encoder->new_crtc == crtc) {
12763 crtc->new_enabled = true;
12764 break;
12765 }
12766 }
12767
83d65738 12768 if (crtc->new_enabled != crtc->base.state->enable) {
10634189
ACO		 12769 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
12770 crtc->base.base.id,
7668851f
VS		 12771 crtc->new_enabled ? "en" : "dis");
12772 config->mode_changed = true;
12773 }
12774 }
12775
2e431051
DV		 12776 return 0;
12777}
12778
7d00a1f5
VS		 12779static void disable_crtc_nofb(struct intel_crtc *crtc)
12780{
12781 struct drm_device *dev = crtc->base.dev;
12782 struct intel_encoder *encoder;
12783 struct intel_connector *connector;
12784
12785 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
12786 pipe_name(crtc->pipe));
12787
3a3371ff 12788 for_each_intel_connector(dev, connector) {
7d00a1f5
VS		 12789 if (connector->new_encoder &&
12790 connector->new_encoder->new_crtc == crtc)
12791 connector->new_encoder = NULL;
12792 }
12793
b2784e15 12794 for_each_intel_encoder(dev, encoder) {
7d00a1f5
VS		 12795 if (encoder->new_crtc == crtc)
12796 encoder->new_crtc = NULL;
12797 }
12798
12799 crtc->new_enabled = false;
12800}
12801
2e431051
DV		 12802static int intel_crtc_set_config(struct drm_mode_set *set)
12803{
12804 struct drm_device *dev;
2e431051 12805 struct drm_mode_set save_set;
83a57153 12806 struct drm_atomic_state *state = NULL;
2e431051 12807 struct intel_set_config *config;
5cec258b 12808 struct intel_crtc_state *pipe_config;
50f52756 12809 unsigned modeset_pipes, prepare_pipes, disable_pipes;
2e431051 12810 int ret;
2e431051 12811
8d3e375e
DV		 12812 BUG_ON(!set);
12813 BUG_ON(!set->crtc);
12814 BUG_ON(!set->crtc->helper_private);
2e431051 12815
7e53f3a4
DV		 12816 /* Enforce sane interface api - has been abused by the fb helper. */
12817 BUG_ON(!set->mode && set->fb);
12818 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 12819
2e431051
DV		 12820 if (set->fb) {
12821 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12822 set->crtc->base.id, set->fb->base.id,
12823 (int)set->num_connectors, set->x, set->y);
12824 } else {
12825 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 12826 }
12827
12828 dev = set->crtc->dev;
12829
12830 ret = -ENOMEM;
12831 config = kzalloc(sizeof(*config), GFP_KERNEL);
12832 if (!config)
12833 goto out_config;
12834
12835 ret = intel_set_config_save_state(dev, config);
12836 if (ret)
12837 goto out_config;
12838
12839 save_set.crtc = set->crtc;
12840 save_set.mode = &set->crtc->mode;
12841 save_set.x = set->crtc->x;
12842 save_set.y = set->crtc->y;
f4510a27 12843 save_set.fb = set->crtc->primary->fb;
2e431051
DV		 12844
12845 /* Compute whether we need a full modeset, only an fb base update or no
12846 * change at all. In the future we might also check whether only the
12847 * mode changed, e.g. for LVDS where we only change the panel fitter in
12848 * such cases. */
12849 intel_set_config_compute_mode_changes(set, config);
12850
83a57153
ACO		 12851 state = drm_atomic_state_alloc(dev);
12852 if (!state) {
12853 ret = -ENOMEM;
12854 goto out_config;
12855 }
12856
12857 state->acquire_ctx = dev->mode_config.acquire_ctx;
12858
944b0c76 12859 ret = intel_modeset_stage_output_state(dev, set, config, state);
2e431051
DV		 12860 if (ret)
12861 goto fail;
12862
50f52756 12863 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
8805aa71 12864 state,
50f52756
JB		 12865 &modeset_pipes,
12866 &prepare_pipes,
12867 &disable_pipes);
20664591 12868 if (IS_ERR(pipe_config)) {
6ac0483b 12869 ret = PTR_ERR(pipe_config);
50f52756 12870 goto fail;
20664591 12871 } else if (pipe_config) {
b9950a13 12872 if (pipe_config->has_audio !=
6e3c9717 12873 to_intel_crtc(set->crtc)->config->has_audio)
20664591
JB		 12874 config->mode_changed = true;
12875
af15d2ce
JB		 12876 /*
12877 * Note we have an issue here with infoframes: current code
12878 * only updates them on the full mode set path per hw
12879 * requirements. So here we should be checking for any
12880 * required changes and forcing a mode set.
12881 */
20664591 12882 }
50f52756 12883
1f9954d0
JB		 12884 intel_update_pipe_size(to_intel_crtc(set->crtc));
12885
5e2b584e 12886 if (config->mode_changed) {
50f52756
JB		 12887 ret = intel_set_mode_pipes(set->crtc, set->mode,
12888 set->x, set->y, set->fb, pipe_config,
12889 modeset_pipes, prepare_pipes,
12890 disable_pipes);
5e2b584e 12891 } else if (config->fb_changed) {
3b150f08 12892 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
455a6808
GP		 12893 struct drm_plane *primary = set->crtc->primary;
12894 int vdisplay, hdisplay;
3b150f08 12895
455a6808 12896 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
70a101f8
MR		 12897 ret = drm_plane_helper_update(primary, set->crtc, set->fb,
12898 0, 0, hdisplay, vdisplay,
12899 set->x << 16, set->y << 16,
12900 hdisplay << 16, vdisplay << 16);
3b150f08
MR		 12901
12902 /*
12903 * We need to make sure the primary plane is re-enabled if it
12904 * has previously been turned off.
12905 */
12906 if (!intel_crtc->primary_enabled && ret == 0) {
12907 WARN_ON(!intel_crtc->active);
fdd508a6 12908 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
3b150f08
MR		 12909 }
12910
7ca51a3a
JB		 12911 /*
12912 * In the fastboot case this may be our only check of the
12913 * state after boot. It would be better to only do it on
12914 * the first update, but we don't have a nice way of doing that
12915 * (and really, set_config isn't used much for high freq page
12916 * flipping, so increasing its cost here shouldn't be a big
12917 * deal).
12918 */
d330a953 12919 if (i915.fastboot && ret == 0)
7ca51a3a 12920 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 12921 }
12922
2d05eae1 12923 if (ret) {
bf67dfeb
DV		 12924 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12925 set->crtc->base.id, ret);
50f56119 12926fail:
2d05eae1 12927 intel_set_config_restore_state(dev, config);
50f56119 12928
83a57153
ACO		 12929 drm_atomic_state_clear(state);
12930
7d00a1f5
VS		 12931 /*
12932 * HACK: if the pipe was on, but we didn't have a framebuffer,
12933 * force the pipe off to avoid oopsing in the modeset code
12934 * due to fb==NULL. This should only happen during boot since
12935 * we don't yet reconstruct the FB from the hardware state.
12936 */
12937 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
12938 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
12939
2d05eae1
CW		 12940 /* Try to restore the config */
12941 if (config->mode_changed &&
12942 intel_set_mode(save_set.crtc, save_set.mode,
83a57153
ACO		 12943 save_set.x, save_set.y, save_set.fb,
12944 state))
2d05eae1
CW		 12945 DRM_ERROR("failed to restore config after modeset failure\n");
12946 }
50f56119 12947
d9e55608 12948out_config:
83a57153
ACO		 12949 if (state)
12950 drm_atomic_state_free(state);
12951
d9e55608 12952 intel_set_config_free(config);
50f56119
DV		 12953 return ret;
12954}
f6e5b160
CW		 12955
12956static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 12957 .gamma_set = intel_crtc_gamma_set,
50f56119 12958 .set_config = intel_crtc_set_config,
f6e5b160
CW		 12959 .destroy = intel_crtc_destroy,
12960 .page_flip = intel_crtc_page_flip,
1356837e
MR		 12961 .atomic_duplicate_state = intel_crtc_duplicate_state,
12962 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 12963};
12964
5358901f
DV		 12965static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12966 struct intel_shared_dpll *pll,
12967 struct intel_dpll_hw_state *hw_state)
ee7b9f93 12968{
5358901f 12969 uint32_t val;
ee7b9f93 12970
f458ebbc 12971 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 12972 return false;
12973
5358901f 12974 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 12975 hw_state->dpll = val;
12976 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12977 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 12978
12979 return val & DPLL_VCO_ENABLE;
12980}
12981
15bdd4cf
DV		 12982static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12983 struct intel_shared_dpll *pll)
12984{
3e369b76
ACO		 12985 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12986 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 12987}
12988
e7b903d2
DV		 12989static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12990 struct intel_shared_dpll *pll)
12991{
e7b903d2 12992 /* PCH refclock must be enabled first */
89eff4be 12993 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 12994
3e369b76 12995 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 12996
12997 /* Wait for the clocks to stabilize. */
12998 POSTING_READ(PCH_DPLL(pll->id));
12999 udelay(150);
13000
13001 /* The pixel multiplier can only be updated once the
13002 * DPLL is enabled and the clocks are stable.
13003 *
13004 * So write it again.
13005 */
3e369b76 13006 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13007 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13008 udelay(200);
13009}
13010
13011static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13012 struct intel_shared_dpll *pll)
13013{
13014 struct drm_device *dev = dev_priv->dev;
13015 struct intel_crtc *crtc;
e7b903d2
DV		 13016
13017 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13018 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13019 if (intel_crtc_to_shared_dpll(crtc) == pll)
13020 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13021 }
13022
15bdd4cf
DV		 13023 I915_WRITE(PCH_DPLL(pll->id), 0);
13024 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13025 udelay(200);
13026}
13027
46edb027
DV		 13028static char *ibx_pch_dpll_names[] = {
13029 "PCH DPLL A",
13030 "PCH DPLL B",
13031};
13032
7c74ade1 13033static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13034{
e7b903d2 13035 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13036 int i;
13037
7c74ade1 13038 dev_priv->num_shared_dpll = 2;
ee7b9f93 13039
e72f9fbf 13040 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13041 dev_priv->shared_dplls[i].id = i;
13042 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13043 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13044 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13045 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13046 dev_priv->shared_dplls[i].get_hw_state =
13047 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13048 }
13049}
13050
7c74ade1
DV		 13051static void intel_shared_dpll_init(struct drm_device *dev)
13052{
e7b903d2 13053 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13054
9cd86933
DV		 13055 if (HAS_DDI(dev))
13056 intel_ddi_pll_init(dev);
13057 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13058 ibx_pch_dpll_init(dev);
13059 else
13060 dev_priv->num_shared_dpll = 0;
13061
13062 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13063}
13064
1fc0a8f7
TU		 13065/**
13066 * intel_wm_need_update - Check whether watermarks need updating
13067 * @plane: drm plane
13068 * @state: new plane state
13069 *
13070 * Check current plane state versus the new one to determine whether
13071 * watermarks need to be recalculated.
13072 *
13073 * Returns true or false.
13074 */
13075bool intel_wm_need_update(struct drm_plane *plane,
13076 struct drm_plane_state *state)
13077{
13078 /* Update watermarks on tiling changes. */
13079 if (!plane->state->fb || !state->fb ||
13080 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13081 plane->state->rotation != state->rotation)
13082 return true;
13083
13084 return false;
13085}
13086
6beb8c23
MR		 13087/**
13088 * intel_prepare_plane_fb - Prepare fb for usage on plane
13089 * @plane: drm plane to prepare for
13090 * @fb: framebuffer to prepare for presentation
13091 *
13092 * Prepares a framebuffer for usage on a display plane. Generally this
13093 * involves pinning the underlying object and updating the frontbuffer tracking
13094 * bits. Some older platforms need special physical address handling for
13095 * cursor planes.
13096 *
13097 * Returns 0 on success, negative error code on failure.
13098 */
13099int
13100intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13101 struct drm_framebuffer *fb,
13102 const struct drm_plane_state *new_state)
465c120c
MR		 13103{
13104 struct drm_device *dev = plane->dev;
6beb8c23
MR		 13105 struct intel_plane *intel_plane = to_intel_plane(plane);
13106 enum pipe pipe = intel_plane->pipe;
13107 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13108 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13109 unsigned frontbuffer_bits = 0;
13110 int ret = 0;
465c120c 13111
ea2c67bb 13112 if (!obj)
465c120c
MR		 13113 return 0;
13114
6beb8c23
MR		 13115 switch (plane->type) {
13116 case DRM_PLANE_TYPE_PRIMARY:
13117 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13118 break;
13119 case DRM_PLANE_TYPE_CURSOR:
13120 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13121 break;
13122 case DRM_PLANE_TYPE_OVERLAY:
13123 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13124 break;
13125 }
465c120c 13126
6beb8c23 13127 mutex_lock(&dev->struct_mutex);
465c120c 13128
6beb8c23
MR		 13129 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13130 INTEL_INFO(dev)->cursor_needs_physical) {
13131 int align = IS_I830(dev) ? 16 * 1024 : 256;
13132 ret = i915_gem_object_attach_phys(obj, align);
13133 if (ret)
13134 DRM_DEBUG_KMS("failed to attach phys object\n");
13135 } else {
82bc3b2d 13136 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 13137 }
465c120c 13138
6beb8c23
MR		 13139 if (ret == 0)
13140 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 13141
4c34574f 13142 mutex_unlock(&dev->struct_mutex);
465c120c 13143
6beb8c23
MR		 13144 return ret;
13145}
13146
38f3ce3a
MR		 13147/**
13148 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13149 * @plane: drm plane to clean up for
13150 * @fb: old framebuffer that was on plane
13151 *
13152 * Cleans up a framebuffer that has just been removed from a plane.
13153 */
13154void
13155intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13156 struct drm_framebuffer *fb,
13157 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13158{
13159 struct drm_device *dev = plane->dev;
13160 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13161
13162 if (WARN_ON(!obj))
13163 return;
13164
13165 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13166 !INTEL_INFO(dev)->cursor_needs_physical) {
13167 mutex_lock(&dev->struct_mutex);
82bc3b2d 13168 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13169 mutex_unlock(&dev->struct_mutex);
13170 }
465c120c
MR		 13171}
13172
6156a456
CK		 13173int
13174skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13175{
13176 int max_scale;
13177 struct drm_device *dev;
13178 struct drm_i915_private *dev_priv;
13179 int crtc_clock, cdclk;
13180
13181 if (!intel_crtc || !crtc_state)
13182 return DRM_PLANE_HELPER_NO_SCALING;
13183
13184 dev = intel_crtc->base.dev;
13185 dev_priv = dev->dev_private;
13186 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13187 cdclk = dev_priv->display.get_display_clock_speed(dev);
13188
13189 if (!crtc_clock || !cdclk)
13190 return DRM_PLANE_HELPER_NO_SCALING;
13191
13192 /*
13193 * skl max scale is lower of:
13194 * close to 3 but not 3, -1 is for that purpose
13195 * or
13196 * cdclk/crtc_clock
13197 */
13198 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13199
13200 return max_scale;
13201}
13202
465c120c 13203static int
3c692a41
GP		 13204intel_check_primary_plane(struct drm_plane *plane,
13205 struct intel_plane_state *state)
13206{
32b7eeec
MR		 13207 struct drm_device *dev = plane->dev;
13208 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 13209 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13210 struct intel_crtc *intel_crtc;
6156a456 13211 struct intel_crtc_state *crtc_state;
2b875c22 13212 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 13213 struct drm_rect *dest = &state->dst;
13214 struct drm_rect *src = &state->src;
13215 const struct drm_rect *clip = &state->clip;
d8106366 13216 bool can_position = false;
6156a456
CK		 13217 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13218 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
465c120c
MR		 13219 int ret;
13220
ea2c67bb
MR		 13221 crtc = crtc ? crtc : plane->crtc;
13222 intel_crtc = to_intel_crtc(crtc);
6156a456
CK		 13223 crtc_state = state->base.state ?
13224 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
ea2c67bb 13225
6156a456
CK		 13226 if (INTEL_INFO(dev)->gen >= 9) {
13227 min_scale = 1;
13228 max_scale = skl_max_scale(intel_crtc, crtc_state);
d8106366 13229 can_position = true;
6156a456 13230 }
d8106366 13231
c59cb179
MR		 13232 ret = drm_plane_helper_check_update(plane, crtc, fb,
13233 src, dest, clip,
6156a456
CK		 13234 min_scale,
13235 max_scale,
d8106366
SJ		 13236 can_position, true,
13237 &state->visible);
c59cb179
MR		 13238 if (ret)
13239 return ret;
465c120c 13240
32b7eeec
MR		 13241 if (intel_crtc->active) {
13242 intel_crtc->atomic.wait_for_flips = true;
13243
13244 /*
13245 * FBC does not work on some platforms for rotated
13246 * planes, so disable it when rotation is not 0 and
13247 * update it when rotation is set back to 0.
13248 *
13249 * FIXME: This is redundant with the fbc update done in
13250 * the primary plane enable function except that that
13251 * one is done too late. We eventually need to unify
13252 * this.
13253 */
13254 if (intel_crtc->primary_enabled &&
13255 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 13256 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 13257 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 13258 intel_crtc->atomic.disable_fbc = true;
13259 }
13260
13261 if (state->visible) {
13262 /*
13263 * BDW signals flip done immediately if the plane
13264 * is disabled, even if the plane enable is already
13265 * armed to occur at the next vblank :(
13266 */
13267 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
13268 intel_crtc->atomic.wait_vblank = true;
13269 }
13270
13271 intel_crtc->atomic.fb_bits |=
13272 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13273
13274 intel_crtc->atomic.update_fbc = true;
0fda6568 13275
1fc0a8f7 13276 if (intel_wm_need_update(plane, &state->base))
0fda6568 13277 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 13278 }
13279
6156a456
CK		 13280 if (INTEL_INFO(dev)->gen >= 9) {
13281 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13282 to_intel_plane(plane), state, 0);
13283 if (ret)
13284 return ret;
13285 }
13286
14af293f
GP		 13287 return 0;
13288}
13289
13290static void
13291intel_commit_primary_plane(struct drm_plane *plane,
13292 struct intel_plane_state *state)
13293{
2b875c22
MR		 13294 struct drm_crtc *crtc = state->base.crtc;
13295 struct drm_framebuffer *fb = state->base.fb;
13296 struct drm_device *dev = plane->dev;
14af293f 13297 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13298 struct intel_crtc *intel_crtc;
14af293f
GP		 13299 struct drm_rect *src = &state->src;
13300
ea2c67bb
MR		 13301 crtc = crtc ? crtc : plane->crtc;
13302 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13303
13304 plane->fb = fb;
9dc806fc
MR		 13305 crtc->x = src->x1 >> 16;
13306 crtc->y = src->y1 >> 16;
ccc759dc 13307
ccc759dc 13308 if (intel_crtc->active) {
27321ae8
ML		 13309 intel_crtc->primary_enabled = state->visible;
13310
13311 if (state->visible)
ccc759dc
GP		 13312 /* FIXME: kill this fastboot hack */
13313 intel_update_pipe_size(intel_crtc);
465c120c 13314
27321ae8
ML		 13315 dev_priv->display.update_primary_plane(crtc, plane->fb,
13316 crtc->x, crtc->y);
ccc759dc 13317 }
465c120c
MR		 13318}
13319
a8ad0d8e
ML		 13320static void
13321intel_disable_primary_plane(struct drm_plane *plane,
13322 struct drm_crtc *crtc,
13323 bool force)
13324{
13325 struct drm_device *dev = plane->dev;
13326 struct drm_i915_private *dev_priv = dev->dev_private;
13327
13328 if (!force)
13329 to_intel_crtc(crtc)->primary_enabled = false;
13330
13331 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13332}
13333
32b7eeec 13334static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13335{
32b7eeec 13336 struct drm_device *dev = crtc->dev;
140fd38d 13337 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13338 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 13339 struct intel_plane *intel_plane;
13340 struct drm_plane *p;
13341 unsigned fb_bits = 0;
13342
13343 /* Track fb's for any planes being disabled */
13344 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13345 intel_plane = to_intel_plane(p);
13346
13347 if (intel_crtc->atomic.disabled_planes &
13348 (1 << drm_plane_index(p))) {
13349 switch (p->type) {
13350 case DRM_PLANE_TYPE_PRIMARY:
13351 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13352 break;
13353 case DRM_PLANE_TYPE_CURSOR:
13354 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13355 break;
13356 case DRM_PLANE_TYPE_OVERLAY:
13357 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13358 break;
13359 }
3c692a41 13360
ea2c67bb
MR		 13361 mutex_lock(&dev->struct_mutex);
13362 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13363 mutex_unlock(&dev->struct_mutex);
13364 }
13365 }
3c692a41 13366
32b7eeec
MR		 13367 if (intel_crtc->atomic.wait_for_flips)
13368 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 13369
32b7eeec
MR		 13370 if (intel_crtc->atomic.disable_fbc)
13371 intel_fbc_disable(dev);
3c692a41 13372
32b7eeec
MR		 13373 if (intel_crtc->atomic.pre_disable_primary)
13374 intel_pre_disable_primary(crtc);
3c692a41 13375
32b7eeec
MR		 13376 if (intel_crtc->atomic.update_wm)
13377 intel_update_watermarks(crtc);
3c692a41 13378
32b7eeec 13379 intel_runtime_pm_get(dev_priv);
3c692a41 13380
c34c9ee4
MR		 13381 /* Perform vblank evasion around commit operation */
13382 if (intel_crtc->active)
13383 intel_crtc->atomic.evade =
13384 intel_pipe_update_start(intel_crtc,
13385 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 13386}
13387
13388static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13389{
13390 struct drm_device *dev = crtc->dev;
13391 struct drm_i915_private *dev_priv = dev->dev_private;
13392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13393 struct drm_plane *p;
13394
c34c9ee4
MR		 13395 if (intel_crtc->atomic.evade)
13396 intel_pipe_update_end(intel_crtc,
13397 intel_crtc->atomic.start_vbl_count);
3c692a41 13398
140fd38d 13399 intel_runtime_pm_put(dev_priv);
3c692a41 13400
32b7eeec
MR		 13401 if (intel_crtc->atomic.wait_vblank)
13402 intel_wait_for_vblank(dev, intel_crtc->pipe);
13403
13404 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13405
13406 if (intel_crtc->atomic.update_fbc) {
ccc759dc 13407 mutex_lock(&dev->struct_mutex);
7ff0ebcc 13408 intel_fbc_update(dev);
ccc759dc 13409 mutex_unlock(&dev->struct_mutex);
38f3ce3a 13410 }
3c692a41 13411
32b7eeec
MR		 13412 if (intel_crtc->atomic.post_enable_primary)
13413 intel_post_enable_primary(crtc);
3c692a41 13414
32b7eeec
MR		 13415 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13416 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13417 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13418 false, false);
13419
13420 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 13421}
13422
cf4c7c12 13423/**
4a3b8769
MR		 13424 * intel_plane_destroy - destroy a plane
13425 * @plane: plane to destroy
cf4c7c12 13426 *
4a3b8769
MR		 13427 * Common destruction function for all types of planes (primary, cursor,
13428 * sprite).
cf4c7c12 13429 */
4a3b8769 13430void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13431{
13432 struct intel_plane *intel_plane = to_intel_plane(plane);
13433 drm_plane_cleanup(plane);
13434 kfree(intel_plane);
13435}
13436
65a3fea0 13437const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13438 .update_plane = drm_atomic_helper_update_plane,
13439 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13440 .destroy = intel_plane_destroy,
c196e1d6 13441 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13442 .atomic_get_property = intel_plane_atomic_get_property,
13443 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13444 .atomic_duplicate_state = intel_plane_duplicate_state,
13445 .atomic_destroy_state = intel_plane_destroy_state,
13446
465c120c
MR		 13447};
13448
13449static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13450 int pipe)
13451{
13452 struct intel_plane *primary;
8e7d688b 13453 struct intel_plane_state *state;
465c120c
MR		 13454 const uint32_t *intel_primary_formats;
13455 int num_formats;
13456
13457 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13458 if (primary == NULL)
13459 return NULL;
13460
8e7d688b
MR		 13461 state = intel_create_plane_state(&primary->base);
13462 if (!state) {
ea2c67bb
MR		 13463 kfree(primary);
13464 return NULL;
13465 }
8e7d688b 13466 primary->base.state = &state->base;
ea2c67bb 13467
465c120c
MR		 13468 primary->can_scale = false;
13469 primary->max_downscale = 1;
6156a456
CK		 13470 if (INTEL_INFO(dev)->gen >= 9) {
13471 primary->can_scale = true;
13472 }
549e2bfb 13473 state->scaler_id = -1;
465c120c
MR		 13474 primary->pipe = pipe;
13475 primary->plane = pipe;
c59cb179
MR		 13476 primary->check_plane = intel_check_primary_plane;
13477 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13478 primary->disable_plane = intel_disable_primary_plane;
08e221fb 13479 primary->ckey.flags = I915_SET_COLORKEY_NONE;
465c120c
MR		 13480 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13481 primary->plane = !pipe;
13482
13483 if (INTEL_INFO(dev)->gen <= 3) {
13484 intel_primary_formats = intel_primary_formats_gen2;
13485 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
13486 } else {
13487 intel_primary_formats = intel_primary_formats_gen4;
13488 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
13489 }
13490
13491 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13492 &intel_plane_funcs,
465c120c
MR		 13493 intel_primary_formats, num_formats,
13494 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13495
3b7a5119
SJ		 13496 if (INTEL_INFO(dev)->gen >= 4)
13497 intel_create_rotation_property(dev, primary);
48404c1e 13498
ea2c67bb
MR		 13499 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13500
465c120c
MR		 13501 return &primary->base;
13502}
13503
3b7a5119
SJ		 13504void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13505{
13506 if (!dev->mode_config.rotation_property) {
13507 unsigned long flags = BIT(DRM_ROTATE_0) |
13508 BIT(DRM_ROTATE_180);
13509
13510 if (INTEL_INFO(dev)->gen >= 9)
13511 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13512
13513 dev->mode_config.rotation_property =
13514 drm_mode_create_rotation_property(dev, flags);
13515 }
13516 if (dev->mode_config.rotation_property)
13517 drm_object_attach_property(&plane->base.base,
13518 dev->mode_config.rotation_property,
13519 plane->base.state->rotation);
13520}
13521
3d7d6510 13522static int
852e787c
GP		 13523intel_check_cursor_plane(struct drm_plane *plane,
13524 struct intel_plane_state *state)
3d7d6510 13525{
2b875c22 13526 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13527 struct drm_device *dev = plane->dev;
2b875c22 13528 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 13529 struct drm_rect *dest = &state->dst;
13530 struct drm_rect *src = &state->src;
13531 const struct drm_rect *clip = &state->clip;
757f9a3e 13532 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 13533 struct intel_crtc *intel_crtc;
757f9a3e
GP		 13534 unsigned stride;
13535 int ret;
3d7d6510 13536
ea2c67bb
MR		 13537 crtc = crtc ? crtc : plane->crtc;
13538 intel_crtc = to_intel_crtc(crtc);
13539
757f9a3e 13540 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 13541 src, dest, clip,
3d7d6510
MR		 13542 DRM_PLANE_HELPER_NO_SCALING,
13543 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13544 true, true, &state->visible);
757f9a3e
GP		 13545 if (ret)
13546 return ret;
13547
13548
13549 /* if we want to turn off the cursor ignore width and height */
13550 if (!obj)
32b7eeec 13551 goto finish;
757f9a3e 13552
757f9a3e 13553 /* Check for which cursor types we support */
ea2c67bb
MR		 13554 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13555 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13556 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13557 return -EINVAL;
13558 }
13559
ea2c67bb
MR		 13560 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13561 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13562 DRM_DEBUG_KMS("buffer is too small\n");
13563 return -ENOMEM;
13564 }
13565
3a656b54 13566 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 13567 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13568 ret = -EINVAL;
13569 }
757f9a3e 13570
32b7eeec
MR		 13571finish:
13572 if (intel_crtc->active) {
3749f463 13573 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 13574 intel_crtc->atomic.update_wm = true;
13575
13576 intel_crtc->atomic.fb_bits |=
13577 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13578 }
13579
757f9a3e 13580 return ret;
852e787c 13581}
3d7d6510 13582
a8ad0d8e
ML		 13583static void
13584intel_disable_cursor_plane(struct drm_plane *plane,
13585 struct drm_crtc *crtc,
13586 bool force)
13587{
13588 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13589
13590 if (!force) {
13591 plane->fb = NULL;
13592 intel_crtc->cursor_bo = NULL;
13593 intel_crtc->cursor_addr = 0;
13594 }
13595
13596 intel_crtc_update_cursor(crtc, false);
13597}
13598
f4a2cf29 13599static void
852e787c
GP		 13600intel_commit_cursor_plane(struct drm_plane *plane,
13601 struct intel_plane_state *state)
13602{
2b875c22 13603 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13604 struct drm_device *dev = plane->dev;
13605 struct intel_crtc *intel_crtc;
2b875c22 13606 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13607 uint32_t addr;
852e787c 13608
ea2c67bb
MR		 13609 crtc = crtc ? crtc : plane->crtc;
13610 intel_crtc = to_intel_crtc(crtc);
13611
2b875c22 13612 plane->fb = state->base.fb;
ea2c67bb
MR		 13613 crtc->cursor_x = state->base.crtc_x;
13614 crtc->cursor_y = state->base.crtc_y;
13615
a912f12f
GP		 13616 if (intel_crtc->cursor_bo == obj)
13617 goto update;
4ed91096 13618
f4a2cf29 13619 if (!obj)
a912f12f 13620 addr = 0;
f4a2cf29 13621 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13622 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13623 else
a912f12f 13624 addr = obj->phys_handle->busaddr;
852e787c 13625
a912f12f
GP		 13626 intel_crtc->cursor_addr = addr;
13627 intel_crtc->cursor_bo = obj;
13628update:
852e787c 13629
32b7eeec 13630 if (intel_crtc->active)
a912f12f 13631 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13632}
13633
3d7d6510
MR		 13634static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13635 int pipe)
13636{
13637 struct intel_plane *cursor;
8e7d688b 13638 struct intel_plane_state *state;
3d7d6510
MR		 13639
13640 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13641 if (cursor == NULL)
13642 return NULL;
13643
8e7d688b
MR		 13644 state = intel_create_plane_state(&cursor->base);
13645 if (!state) {
ea2c67bb
MR		 13646 kfree(cursor);
13647 return NULL;
13648 }
8e7d688b 13649 cursor->base.state = &state->base;
ea2c67bb 13650
3d7d6510
MR		 13651 cursor->can_scale = false;
13652 cursor->max_downscale = 1;
13653 cursor->pipe = pipe;
13654 cursor->plane = pipe;
549e2bfb 13655 state->scaler_id = -1;
c59cb179
MR		 13656 cursor->check_plane = intel_check_cursor_plane;
13657 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13658 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13659
13660 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13661 &intel_plane_funcs,
3d7d6510
MR		 13662 intel_cursor_formats,
13663 ARRAY_SIZE(intel_cursor_formats),
13664 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13665
13666 if (INTEL_INFO(dev)->gen >= 4) {
13667 if (!dev->mode_config.rotation_property)
13668 dev->mode_config.rotation_property =
13669 drm_mode_create_rotation_property(dev,
13670 BIT(DRM_ROTATE_0) |
13671 BIT(DRM_ROTATE_180));
13672 if (dev->mode_config.rotation_property)
13673 drm_object_attach_property(&cursor->base.base,
13674 dev->mode_config.rotation_property,
8e7d688b 13675 state->base.rotation);
4398ad45
VS		 13676 }
13677
ea2c67bb
MR		 13678 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13679
3d7d6510
MR		 13680 return &cursor->base;
13681}
13682
549e2bfb
CK		 13683static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13684 struct intel_crtc_state *crtc_state)
13685{
13686 int i;
13687 struct intel_scaler *intel_scaler;
13688 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13689
13690 for (i = 0; i < intel_crtc->num_scalers; i++) {
13691 intel_scaler = &scaler_state->scalers[i];
13692 intel_scaler->in_use = 0;
13693 intel_scaler->id = i;
13694
13695 intel_scaler->mode = PS_SCALER_MODE_DYN;
13696 }
13697
13698 scaler_state->scaler_id = -1;
13699}
13700
b358d0a6 13701static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13702{
fbee40df 13703 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13704 struct intel_crtc *intel_crtc;
f5de6e07 13705 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13706 struct drm_plane *primary = NULL;
13707 struct drm_plane *cursor = NULL;
465c120c 13708 int i, ret;
79e53945 13709
955382f3 13710 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13711 if (intel_crtc == NULL)
13712 return;
13713
f5de6e07
ACO		 13714 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13715 if (!crtc_state)
13716 goto fail;
13717 intel_crtc_set_state(intel_crtc, crtc_state);
07878248 13718 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13719
549e2bfb
CK		 13720 /* initialize shared scalers */
13721 if (INTEL_INFO(dev)->gen >= 9) {
13722 if (pipe == PIPE_C)
13723 intel_crtc->num_scalers = 1;
13724 else
13725 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13726
13727 skl_init_scalers(dev, intel_crtc, crtc_state);
13728 }
13729
465c120c 13730 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13731 if (!primary)
13732 goto fail;
13733
13734 cursor = intel_cursor_plane_create(dev, pipe);
13735 if (!cursor)
13736 goto fail;
13737
465c120c 13738 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13739 cursor, &intel_crtc_funcs);
13740 if (ret)
13741 goto fail;
79e53945
JB		 13742
13743 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13744 for (i = 0; i < 256; i++) {
13745 intel_crtc->lut_r[i] = i;
13746 intel_crtc->lut_g[i] = i;
13747 intel_crtc->lut_b[i] = i;
13748 }
13749
1f1c2e24
VS		 13750 /*
13751 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13752 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13753 */
80824003
JB		 13754 intel_crtc->pipe = pipe;
13755 intel_crtc->plane = pipe;
3a77c4c4 13756 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13757 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13758 intel_crtc->plane = !pipe;
80824003
JB		 13759 }
13760
4b0e333e
CW		 13761 intel_crtc->cursor_base = ~0;
13762 intel_crtc->cursor_cntl = ~0;
dc41c154 13763 intel_crtc->cursor_size = ~0;
8d7849db 13764
22fd0fab
JB		 13765 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13766 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13767 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13768 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13769
9362c7c5
ACO		 13770 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
13771
79e53945 13772 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 13773
13774 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13775 return;
13776
13777fail:
13778 if (primary)
13779 drm_plane_cleanup(primary);
13780 if (cursor)
13781 drm_plane_cleanup(cursor);
f5de6e07 13782 kfree(crtc_state);
3d7d6510 13783 kfree(intel_crtc);
79e53945
JB		 13784}
13785
752aa88a
JB		 13786enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13787{
13788 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13789 struct drm_device *dev = connector->base.dev;
752aa88a 13790
51fd371b 13791 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13792
d3babd3f 13793 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 13794 return INVALID_PIPE;
13795
13796 return to_intel_crtc(encoder->crtc)->pipe;
13797}
13798
08d7b3d1 13799int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13800 struct drm_file *file)
08d7b3d1 13801{
08d7b3d1 13802 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13803 struct drm_crtc *drmmode_crtc;
c05422d5 13804 struct intel_crtc *crtc;
08d7b3d1 13805
7707e653 13806 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13807
7707e653 13808 if (!drmmode_crtc) {
08d7b3d1 13809 DRM_ERROR("no such CRTC id\n");
3f2c2057 13810 return -ENOENT;
08d7b3d1
CW		 13811 }
13812
7707e653 13813 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13814 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13815
c05422d5 13816 return 0;
08d7b3d1
CW		 13817}
13818
66a9278e 13819static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13820{
66a9278e
DV		 13821 struct drm_device *dev = encoder->base.dev;
13822 struct intel_encoder *source_encoder;
79e53945 13823 int index_mask = 0;
79e53945
JB		 13824 int entry = 0;
13825
b2784e15 13826 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13827 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 13828 index_mask |= (1 << entry);
13829
79e53945
JB		 13830 entry++;
13831 }
4ef69c7a 13832
79e53945
JB		 13833 return index_mask;
13834}
13835
4d302442
CW		 13836static bool has_edp_a(struct drm_device *dev)
13837{
13838 struct drm_i915_private *dev_priv = dev->dev_private;
13839
13840 if (!IS_MOBILE(dev))
13841 return false;
13842
13843 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13844 return false;
13845
e3589908 13846 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 13847 return false;
13848
13849 return true;
13850}
13851
84b4e042
JB		 13852static bool intel_crt_present(struct drm_device *dev)
13853{
13854 struct drm_i915_private *dev_priv = dev->dev_private;
13855
884497ed
DL		 13856 if (INTEL_INFO(dev)->gen >= 9)
13857 return false;
13858
cf404ce4 13859 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 13860 return false;
13861
13862 if (IS_CHERRYVIEW(dev))
13863 return false;
13864
13865 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13866 return false;
13867
13868 return true;
13869}
13870
79e53945
JB		 13871static void intel_setup_outputs(struct drm_device *dev)
13872{
725e30ad 13873 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13874 struct intel_encoder *encoder;
cb0953d7 13875 bool dpd_is_edp = false;
79e53945 13876
c9093354 13877 intel_lvds_init(dev);
79e53945 13878
84b4e042 13879 if (intel_crt_present(dev))
79935fca 13880 intel_crt_init(dev);
cb0953d7 13881
c776eb2e
VK		 13882 if (IS_BROXTON(dev)) {
13883 /*
13884 * FIXME: Broxton doesn't support port detection via the
13885 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13886 * detect the ports.
13887 */
13888 intel_ddi_init(dev, PORT_A);
13889 intel_ddi_init(dev, PORT_B);
13890 intel_ddi_init(dev, PORT_C);
13891 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 13892 int found;
13893
de31facd
JB		 13894 /*
13895 * Haswell uses DDI functions to detect digital outputs.
13896 * On SKL pre-D0 the strap isn't connected, so we assume
13897 * it's there.
13898 */
0e72a5b5 13899 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 13900 /* WaIgnoreDDIAStrap: skl */
13901 if (found ||
13902 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 13903 intel_ddi_init(dev, PORT_A);
13904
13905 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13906 * register */
13907 found = I915_READ(SFUSE_STRAP);
13908
13909 if (found & SFUSE_STRAP_DDIB_DETECTED)
13910 intel_ddi_init(dev, PORT_B);
13911 if (found & SFUSE_STRAP_DDIC_DETECTED)
13912 intel_ddi_init(dev, PORT_C);
13913 if (found & SFUSE_STRAP_DDID_DETECTED)
13914 intel_ddi_init(dev, PORT_D);
13915 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 13916 int found;
5d8a7752 13917 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 13918
13919 if (has_edp_a(dev))
13920 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 13921
dc0fa718 13922 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 13923 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 13924 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 13925 if (!found)
e2debe91 13926 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 13927 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 13928 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 13929 }
13930
dc0fa718 13931 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 13932 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 13933
dc0fa718 13934 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 13935 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 13936
5eb08b69 13937 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 13938 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 13939
270b3042 13940 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 13941 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 13942 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 13943 /*
13944 * The DP_DETECTED bit is the latched state of the DDC
13945 * SDA pin at boot. However since eDP doesn't require DDC
13946 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13947 * eDP ports may have been muxed to an alternate function.
13948 * Thus we can't rely on the DP_DETECTED bit alone to detect
13949 * eDP ports. Consult the VBT as well as DP_DETECTED to
13950 * detect eDP ports.
13951 */
d2182a66
VS		 13952 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13953 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 13954 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13955 PORT_B);
e17ac6db
VS		 13956 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13957 intel_dp_is_edp(dev, PORT_B))
13958 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 13959
d2182a66
VS		 13960 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13961 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 13962 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13963 PORT_C);
e17ac6db
VS		 13964 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13965 intel_dp_is_edp(dev, PORT_C))
13966 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 13967
9418c1f1 13968 if (IS_CHERRYVIEW(dev)) {
e17ac6db 13969 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 13970 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13971 PORT_D);
e17ac6db
VS		 13972 /* eDP not supported on port D, so don't check VBT */
13973 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13974 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 13975 }
13976
3cfca973 13977 intel_dsi_init(dev);
103a196f 13978 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 13979 bool found = false;
7d57382e 13980
e2debe91 13981 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13982 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 13983 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 13984 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13985 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 13986 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 13987 }
27185ae1 13988
e7281eab 13989 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 13990 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 13991 }
13520b05
KH		 13992
13993 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 13994
e2debe91 13995 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13996 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 13997 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 13998 }
27185ae1 13999
e2debe91 14000 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14001
b01f2c3a
JB		 14002 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14003 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14004 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14005 }
e7281eab 14006 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14007 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14008 }
27185ae1 14009
b01f2c3a 14010 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 14011 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14012 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14013 } else if (IS_GEN2(dev))
79e53945
JB		 14014 intel_dvo_init(dev);
14015
103a196f 14016 if (SUPPORTS_TV(dev))
79e53945
JB		 14017 intel_tv_init(dev);
14018
0bc12bcb 14019 intel_psr_init(dev);
7c8f8a70 14020
b2784e15 14021 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14022 encoder->base.possible_crtcs = encoder->crtc_mask;
14023 encoder->base.possible_clones =
66a9278e 14024 intel_encoder_clones(encoder);
79e53945 14025 }
47356eb6 14026
dde86e2d 14027 intel_init_pch_refclk(dev);
270b3042
DV		 14028
14029 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14030}
14031
14032static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14033{
60a5ca01 14034 struct drm_device *dev = fb->dev;
79e53945 14035 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14036
ef2d633e 14037 drm_framebuffer_cleanup(fb);
60a5ca01 14038 mutex_lock(&dev->struct_mutex);
ef2d633e 14039 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14040 drm_gem_object_unreference(&intel_fb->obj->base);
14041 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14042 kfree(intel_fb);
14043}
14044
14045static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14046 struct drm_file *file,
79e53945
JB		 14047 unsigned int *handle)
14048{
14049 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14050 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14051
05394f39 14052 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14053}
14054
14055static const struct drm_framebuffer_funcs intel_fb_funcs = {
14056 .destroy = intel_user_framebuffer_destroy,
14057 .create_handle = intel_user_framebuffer_create_handle,
14058};
14059
b321803d
DL		 14060static
14061u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14062 uint32_t pixel_format)
14063{
14064 u32 gen = INTEL_INFO(dev)->gen;
14065
14066 if (gen >= 9) {
14067 /* "The stride in bytes must not exceed the of the size of 8K
14068 * pixels and 32K bytes."
14069 */
14070 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14071 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14072 return 32*1024;
14073 } else if (gen >= 4) {
14074 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14075 return 16*1024;
14076 else
14077 return 32*1024;
14078 } else if (gen >= 3) {
14079 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14080 return 8*1024;
14081 else
14082 return 16*1024;
14083 } else {
14084 /* XXX DSPC is limited to 4k tiled */
14085 return 8*1024;
14086 }
14087}
14088
b5ea642a
DV		 14089static int intel_framebuffer_init(struct drm_device *dev,
14090 struct intel_framebuffer *intel_fb,
14091 struct drm_mode_fb_cmd2 *mode_cmd,
14092 struct drm_i915_gem_object *obj)
79e53945 14093{
6761dd31 14094 unsigned int aligned_height;
79e53945 14095 int ret;
b321803d 14096 u32 pitch_limit, stride_alignment;
79e53945 14097
dd4916c5
DV		 14098 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14099
2a80eada
DV		 14100 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14101 /* Enforce that fb modifier and tiling mode match, but only for
14102 * X-tiled. This is needed for FBC. */
14103 if (!!(obj->tiling_mode == I915_TILING_X) !=
14104 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14105 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14106 return -EINVAL;
14107 }
14108 } else {
14109 if (obj->tiling_mode == I915_TILING_X)
14110 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14111 else if (obj->tiling_mode == I915_TILING_Y) {
14112 DRM_DEBUG("No Y tiling for legacy addfb\n");
14113 return -EINVAL;
14114 }
14115 }
14116
9a8f0a12
TU		 14117 /* Passed in modifier sanity checking. */
14118 switch (mode_cmd->modifier[0]) {
14119 case I915_FORMAT_MOD_Y_TILED:
14120 case I915_FORMAT_MOD_Yf_TILED:
14121 if (INTEL_INFO(dev)->gen < 9) {
14122 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14123 mode_cmd->modifier[0]);
14124 return -EINVAL;
14125 }
14126 case DRM_FORMAT_MOD_NONE:
14127 case I915_FORMAT_MOD_X_TILED:
14128 break;
14129 default:
c0f40428
JB		 14130 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14131 mode_cmd->modifier[0]);
57cd6508 14132 return -EINVAL;
c16ed4be 14133 }
57cd6508 14134
b321803d
DL		 14135 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14136 mode_cmd->pixel_format);
14137 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14138 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14139 mode_cmd->pitches[0], stride_alignment);
57cd6508 14140 return -EINVAL;
c16ed4be 14141 }
57cd6508 14142
b321803d
DL		 14143 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14144 mode_cmd->pixel_format);
a35cdaa0 14145 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14146 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14147 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14148 "tiled" : "linear",
a35cdaa0 14149 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14150 return -EINVAL;
c16ed4be 14151 }
5d7bd705 14152
2a80eada 14153 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14154 mode_cmd->pitches[0] != obj->stride) {
14155 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14156 mode_cmd->pitches[0], obj->stride);
5d7bd705 14157 return -EINVAL;
c16ed4be 14158 }
5d7bd705 14159
57779d06 14160 /* Reject formats not supported by any plane early. */
308e5bcb 14161 switch (mode_cmd->pixel_format) {
57779d06 14162 case DRM_FORMAT_C8:
04b3924d
VS		 14163 case DRM_FORMAT_RGB565:
14164 case DRM_FORMAT_XRGB8888:
14165 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14166 break;
14167 case DRM_FORMAT_XRGB1555:
14168 case DRM_FORMAT_ARGB1555:
c16ed4be 14169 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14170 DRM_DEBUG("unsupported pixel format: %s\n",
14171 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14172 return -EINVAL;
c16ed4be 14173 }
57779d06
VS		 14174 break;
14175 case DRM_FORMAT_XBGR8888:
14176 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 14177 case DRM_FORMAT_XRGB2101010:
14178 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 14179 case DRM_FORMAT_XBGR2101010:
14180 case DRM_FORMAT_ABGR2101010:
c16ed4be 14181 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14182 DRM_DEBUG("unsupported pixel format: %s\n",
14183 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14184 return -EINVAL;
c16ed4be 14185 }
b5626747 14186 break;
04b3924d
VS		 14187 case DRM_FORMAT_YUYV:
14188 case DRM_FORMAT_UYVY:
14189 case DRM_FORMAT_YVYU:
14190 case DRM_FORMAT_VYUY:
c16ed4be 14191 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14192 DRM_DEBUG("unsupported pixel format: %s\n",
14193 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14194 return -EINVAL;
c16ed4be 14195 }
57cd6508
CW		 14196 break;
14197 default:
4ee62c76
VS		 14198 DRM_DEBUG("unsupported pixel format: %s\n",
14199 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14200 return -EINVAL;
14201 }
14202
90f9a336
VS		 14203 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14204 if (mode_cmd->offsets[0] != 0)
14205 return -EINVAL;
14206
ec2c981e 14207 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14208 mode_cmd->pixel_format,
14209 mode_cmd->modifier[0]);
53155c0a
DV		 14210 /* FIXME drm helper for size checks (especially planar formats)? */
14211 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14212 return -EINVAL;
14213
c7d73f6a
DV		 14214 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14215 intel_fb->obj = obj;
80075d49 14216 intel_fb->obj->framebuffer_references++;
c7d73f6a 14217
79e53945
JB		 14218 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14219 if (ret) {
14220 DRM_ERROR("framebuffer init failed %d\n", ret);
14221 return ret;
14222 }
14223
79e53945
JB		 14224 return 0;
14225}
14226
79e53945
JB		 14227static struct drm_framebuffer *
14228intel_user_framebuffer_create(struct drm_device *dev,
14229 struct drm_file *filp,
308e5bcb 14230 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14231{
05394f39 14232 struct drm_i915_gem_object *obj;
79e53945 14233
308e5bcb
JB		 14234 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14235 mode_cmd->handles[0]));
c8725226 14236 if (&obj->base == NULL)
cce13ff7 14237 return ERR_PTR(-ENOENT);
79e53945 14238
d2dff872 14239 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14240}
14241
4520f53a 14242#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14243static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14244{
14245}
14246#endif
14247
79e53945 14248static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14249 .fb_create = intel_user_framebuffer_create,
0632fef6 14250 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14251 .atomic_check = intel_atomic_check,
14252 .atomic_commit = intel_atomic_commit,
79e53945
JB		 14253};
14254
e70236a8
JB		 14255/* Set up chip specific display functions */
14256static void intel_init_display(struct drm_device *dev)
14257{
14258 struct drm_i915_private *dev_priv = dev->dev_private;
14259
ee9300bb
DV		 14260 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14261 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14262 else if (IS_CHERRYVIEW(dev))
14263 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14264 else if (IS_VALLEYVIEW(dev))
14265 dev_priv->display.find_dpll = vlv_find_best_dpll;
14266 else if (IS_PINEVIEW(dev))
14267 dev_priv->display.find_dpll = pnv_find_best_dpll;
14268 else
14269 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14270
bc8d7dff
DL		 14271 if (INTEL_INFO(dev)->gen >= 9) {
14272 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14273 dev_priv->display.get_initial_plane_config =
14274 skylake_get_initial_plane_config;
bc8d7dff
DL		 14275 dev_priv->display.crtc_compute_clock =
14276 haswell_crtc_compute_clock;
14277 dev_priv->display.crtc_enable = haswell_crtc_enable;
14278 dev_priv->display.crtc_disable = haswell_crtc_disable;
14279 dev_priv->display.off = ironlake_crtc_off;
14280 dev_priv->display.update_primary_plane =
14281 skylake_update_primary_plane;
14282 } else if (HAS_DDI(dev)) {
0e8ffe1b 14283 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14284 dev_priv->display.get_initial_plane_config =
14285 ironlake_get_initial_plane_config;
797d0259
ACO		 14286 dev_priv->display.crtc_compute_clock =
14287 haswell_crtc_compute_clock;
4f771f10
PZ		 14288 dev_priv->display.crtc_enable = haswell_crtc_enable;
14289 dev_priv->display.crtc_disable = haswell_crtc_disable;
df8ad70c 14290 dev_priv->display.off = ironlake_crtc_off;
bc8d7dff
DL		 14291 dev_priv->display.update_primary_plane =
14292 ironlake_update_primary_plane;
09b4ddf9 14293 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14294 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14295 dev_priv->display.get_initial_plane_config =
14296 ironlake_get_initial_plane_config;
3fb37703
ACO		 14297 dev_priv->display.crtc_compute_clock =
14298 ironlake_crtc_compute_clock;
76e5a89c
DV		 14299 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14300 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 14301 dev_priv->display.off = ironlake_crtc_off;
262ca2b0
MR		 14302 dev_priv->display.update_primary_plane =
14303 ironlake_update_primary_plane;
89b667f8
JB		 14304 } else if (IS_VALLEYVIEW(dev)) {
14305 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14306 dev_priv->display.get_initial_plane_config =
14307 i9xx_get_initial_plane_config;
d6dfee7a 14308 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14309 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14310 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14311 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14312 dev_priv->display.update_primary_plane =
14313 i9xx_update_primary_plane;
f564048e 14314 } else {
0e8ffe1b 14315 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14316 dev_priv->display.get_initial_plane_config =
14317 i9xx_get_initial_plane_config;
d6dfee7a 14318 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14319 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14320 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 14321 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14322 dev_priv->display.update_primary_plane =
14323 i9xx_update_primary_plane;
f564048e 14324 }
e70236a8 14325
e70236a8 14326 /* Returns the core display clock speed */
1652d19e
VS		 14327 if (IS_SKYLAKE(dev))
14328 dev_priv->display.get_display_clock_speed =
14329 skylake_get_display_clock_speed;
14330 else if (IS_BROADWELL(dev))
14331 dev_priv->display.get_display_clock_speed =
14332 broadwell_get_display_clock_speed;
14333 else if (IS_HASWELL(dev))
14334 dev_priv->display.get_display_clock_speed =
14335 haswell_get_display_clock_speed;
14336 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14337 dev_priv->display.get_display_clock_speed =
14338 valleyview_get_display_clock_speed;
b37a6434
VS		 14339 else if (IS_GEN5(dev))
14340 dev_priv->display.get_display_clock_speed =
14341 ilk_get_display_clock_speed;
a7c66cd8
VS		 14342 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14343 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 14344 dev_priv->display.get_display_clock_speed =
14345 i945_get_display_clock_speed;
14346 else if (IS_I915G(dev))
14347 dev_priv->display.get_display_clock_speed =
14348 i915_get_display_clock_speed;
257a7ffc 14349 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14350 dev_priv->display.get_display_clock_speed =
14351 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14352 else if (IS_PINEVIEW(dev))
14353 dev_priv->display.get_display_clock_speed =
14354 pnv_get_display_clock_speed;
e70236a8
JB		 14355 else if (IS_I915GM(dev))
14356 dev_priv->display.get_display_clock_speed =
14357 i915gm_get_display_clock_speed;
14358 else if (IS_I865G(dev))
14359 dev_priv->display.get_display_clock_speed =
14360 i865_get_display_clock_speed;
f0f8a9ce 14361 else if (IS_I85X(dev))
e70236a8
JB		 14362 dev_priv->display.get_display_clock_speed =
14363 i855_get_display_clock_speed;
14364 else /* 852, 830 */
14365 dev_priv->display.get_display_clock_speed =
14366 i830_get_display_clock_speed;
14367
7c10a2b5 14368 if (IS_GEN5(dev)) {
3bb11b53 14369 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14370 } else if (IS_GEN6(dev)) {
14371 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14372 } else if (IS_IVYBRIDGE(dev)) {
14373 /* FIXME: detect B0+ stepping and use auto training */
14374 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14375 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14376 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
30a970c6
JB		 14377 } else if (IS_VALLEYVIEW(dev)) {
14378 dev_priv->display.modeset_global_resources =
14379 valleyview_modeset_global_resources;
f8437dd1
VK		 14380 } else if (IS_BROXTON(dev)) {
14381 dev_priv->display.modeset_global_resources =
14382 broxton_modeset_global_resources;
e70236a8 14383 }
8c9f3aaf 14384
8c9f3aaf
JB		 14385 switch (INTEL_INFO(dev)->gen) {
14386 case 2:
14387 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14388 break;
14389
14390 case 3:
14391 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14392 break;
14393
14394 case 4:
14395 case 5:
14396 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14397 break;
14398
14399 case 6:
14400 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14401 break;
7c9017e5 14402 case 7:
4e0bbc31 14403 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14404 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14405 break;
830c81db 14406 case 9:
ba343e02
TU		 14407 /* Drop through - unsupported since execlist only. */
14408 default:
14409 /* Default just returns -ENODEV to indicate unsupported */
14410 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14411 }
7bd688cd
JN		 14412
14413 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14414
14415 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14416}
14417
b690e96c
JB		 14418/*
14419 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14420 * resume, or other times. This quirk makes sure that's the case for
14421 * affected systems.
14422 */
0206e353 14423static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14424{
14425 struct drm_i915_private *dev_priv = dev->dev_private;
14426
14427 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14428 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14429}
14430
b6b5d049
VS		 14431static void quirk_pipeb_force(struct drm_device *dev)
14432{
14433 struct drm_i915_private *dev_priv = dev->dev_private;
14434
14435 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14436 DRM_INFO("applying pipe b force quirk\n");
14437}
14438
435793df
KP		 14439/*
14440 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14441 */
14442static void quirk_ssc_force_disable(struct drm_device *dev)
14443{
14444 struct drm_i915_private *dev_priv = dev->dev_private;
14445 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14446 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14447}
14448
4dca20ef 14449/*
5a15ab5b
CE		 14450 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14451 * brightness value
4dca20ef
CE		 14452 */
14453static void quirk_invert_brightness(struct drm_device *dev)
14454{
14455 struct drm_i915_private *dev_priv = dev->dev_private;
14456 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14457 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14458}
14459
9c72cc6f
SD		 14460/* Some VBT's incorrectly indicate no backlight is present */
14461static void quirk_backlight_present(struct drm_device *dev)
14462{
14463 struct drm_i915_private *dev_priv = dev->dev_private;
14464 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14465 DRM_INFO("applying backlight present quirk\n");
14466}
14467
b690e96c
JB		 14468struct intel_quirk {
14469 int device;
14470 int subsystem_vendor;
14471 int subsystem_device;
14472 void (*hook)(struct drm_device *dev);
14473};
14474
5f85f176
EE		 14475/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14476struct intel_dmi_quirk {
14477 void (*hook)(struct drm_device *dev);
14478 const struct dmi_system_id (*dmi_id_list)[];
14479};
14480
14481static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14482{
14483 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14484 return 1;
14485}
14486
14487static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14488 {
14489 .dmi_id_list = &(const struct dmi_system_id[]) {
14490 {
14491 .callback = intel_dmi_reverse_brightness,
14492 .ident = "NCR Corporation",
14493 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14494 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14495 },
14496 },
14497 { } /* terminating entry */
14498 },
14499 .hook = quirk_invert_brightness,
14500 },
14501};
14502
c43b5634 14503static struct intel_quirk intel_quirks[] = {
b690e96c 14504 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 14505 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 14506
b690e96c
JB		 14507 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14508 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14509
b690e96c
JB		 14510 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14511 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14512
5f080c0f
VS		 14513 /* 830 needs to leave pipe A & dpll A up */
14514 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14515
b6b5d049
VS		 14516 /* 830 needs to leave pipe B & dpll B up */
14517 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14518
435793df
KP		 14519 /* Lenovo U160 cannot use SSC on LVDS */
14520 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14521
14522 /* Sony Vaio Y cannot use SSC on LVDS */
14523 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14524
be505f64
AH		 14525 /* Acer Aspire 5734Z must invert backlight brightness */
14526 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14527
14528 /* Acer/eMachines G725 */
14529 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14530
14531 /* Acer/eMachines e725 */
14532 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14533
14534 /* Acer/Packard Bell NCL20 */
14535 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14536
14537 /* Acer Aspire 4736Z */
14538 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14539
14540 /* Acer Aspire 5336 */
14541 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14542
14543 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14544 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14545
dfb3d47b
SD		 14546 /* Acer C720 Chromebook (Core i3 4005U) */
14547 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14548
b2a9601c 14549 /* Apple Macbook 2,1 (Core 2 T7400) */
14550 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14551
d4967d8c
SD		 14552 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14553 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14554
14555 /* HP Chromebook 14 (Celeron 2955U) */
14556 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14557
14558 /* Dell Chromebook 11 */
14559 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14560};
14561
14562static void intel_init_quirks(struct drm_device *dev)
14563{
14564 struct pci_dev *d = dev->pdev;
14565 int i;
14566
14567 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14568 struct intel_quirk *q = &intel_quirks[i];
14569
14570 if (d->device == q->device &&
14571 (d->subsystem_vendor == q->subsystem_vendor ||
14572 q->subsystem_vendor == PCI_ANY_ID) &&
14573 (d->subsystem_device == q->subsystem_device ||
14574 q->subsystem_device == PCI_ANY_ID))
14575 q->hook(dev);
14576 }
5f85f176
EE		 14577 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14578 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14579 intel_dmi_quirks[i].hook(dev);
14580 }
b690e96c
JB		 14581}
14582
9cce37f4
JB		 14583/* Disable the VGA plane that we never use */
14584static void i915_disable_vga(struct drm_device *dev)
14585{
14586 struct drm_i915_private *dev_priv = dev->dev_private;
14587 u8 sr1;
766aa1c4 14588 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14589
2b37c616 14590 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14591 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14592 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14593 sr1 = inb(VGA_SR_DATA);
14594 outb(sr1 | 1<<5, VGA_SR_DATA);
14595 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14596 udelay(300);
14597
01f5a626 14598 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14599 POSTING_READ(vga_reg);
14600}
14601
f817586c
DV		 14602void intel_modeset_init_hw(struct drm_device *dev)
14603{
a8f78b58
ED		 14604 intel_prepare_ddi(dev);
14605
f8bf63fd
VS		 14606 if (IS_VALLEYVIEW(dev))
14607 vlv_update_cdclk(dev);
14608
f817586c
DV		 14609 intel_init_clock_gating(dev);
14610
8090c6b9 14611 intel_enable_gt_powersave(dev);
f817586c
DV		 14612}
14613
79e53945
JB		 14614void intel_modeset_init(struct drm_device *dev)
14615{
652c393a 14616 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14617 int sprite, ret;
8cc87b75 14618 enum pipe pipe;
46f297fb 14619 struct intel_crtc *crtc;
79e53945
JB		 14620
14621 drm_mode_config_init(dev);
14622
14623 dev->mode_config.min_width = 0;
14624 dev->mode_config.min_height = 0;
14625
019d96cb
DA		 14626 dev->mode_config.preferred_depth = 24;
14627 dev->mode_config.prefer_shadow = 1;
14628
25bab385
TU		 14629 dev->mode_config.allow_fb_modifiers = true;
14630
e6ecefaa 14631 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14632
b690e96c
JB		 14633 intel_init_quirks(dev);
14634
1fa61106
ED		 14635 intel_init_pm(dev);
14636
e3c74757
BW		 14637 if (INTEL_INFO(dev)->num_pipes == 0)
14638 return;
14639
e70236a8 14640 intel_init_display(dev);
7c10a2b5 14641 intel_init_audio(dev);
e70236a8 14642
a6c45cf0
CW		 14643 if (IS_GEN2(dev)) {
14644 dev->mode_config.max_width = 2048;
14645 dev->mode_config.max_height = 2048;
14646 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14647 dev->mode_config.max_width = 4096;
14648 dev->mode_config.max_height = 4096;
79e53945 14649 } else {
a6c45cf0
CW		 14650 dev->mode_config.max_width = 8192;
14651 dev->mode_config.max_height = 8192;
79e53945 14652 }
068be561 14653
dc41c154
VS		 14654 if (IS_845G(dev) || IS_I865G(dev)) {
14655 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14656 dev->mode_config.cursor_height = 1023;
14657 } else if (IS_GEN2(dev)) {
068be561
DL		 14658 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14659 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14660 } else {
14661 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14662 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14663 }
14664
5d4545ae 14665 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14666
28c97730 14667 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14668 INTEL_INFO(dev)->num_pipes,
14669 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14670
055e393f 14671 for_each_pipe(dev_priv, pipe) {
8cc87b75 14672 intel_crtc_init(dev, pipe);
3bdcfc0c 14673 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14674 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14675 if (ret)
06da8da2 14676 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14677 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14678 }
79e53945
JB		 14679 }
14680
f42bb70d
JB		 14681 intel_init_dpio(dev);
14682
e72f9fbf 14683 intel_shared_dpll_init(dev);
ee7b9f93 14684
9cce37f4
JB		 14685 /* Just disable it once at startup */
14686 i915_disable_vga(dev);
79e53945 14687 intel_setup_outputs(dev);
11be49eb
CW		 14688
14689 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 14690 intel_fbc_disable(dev);
fa9fa083 14691
6e9f798d 14692 drm_modeset_lock_all(dev);
fa9fa083 14693 intel_modeset_setup_hw_state(dev, false);
6e9f798d 14694 drm_modeset_unlock_all(dev);
46f297fb 14695
d3fcc808 14696 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 14697 if (!crtc->active)
14698 continue;
14699
46f297fb 14700 /*
46f297fb
JB		 14701 * Note that reserving the BIOS fb up front prevents us
14702 * from stuffing other stolen allocations like the ring
14703 * on top. This prevents some ugliness at boot time, and
14704 * can even allow for smooth boot transitions if the BIOS
14705 * fb is large enough for the active pipe configuration.
14706 */
5724dbd1
DL		 14707 if (dev_priv->display.get_initial_plane_config) {
14708 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 14709 &crtc->plane_config);
14710 /*
14711 * If the fb is shared between multiple heads, we'll
14712 * just get the first one.
14713 */
f6936e29 14714 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 14715 }
46f297fb 14716 }
2c7111db
CW		 14717}
14718
7fad798e
DV		 14719static void intel_enable_pipe_a(struct drm_device *dev)
14720{
14721 struct intel_connector *connector;
14722 struct drm_connector *crt = NULL;
14723 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14724 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14725
14726 /* We can't just switch on the pipe A, we need to set things up with a
14727 * proper mode and output configuration. As a gross hack, enable pipe A
14728 * by enabling the load detect pipe once. */
3a3371ff 14729 for_each_intel_connector(dev, connector) {
7fad798e
DV		 14730 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14731 crt = &connector->base;
14732 break;
14733 }
14734 }
14735
14736 if (!crt)
14737 return;
14738
208bf9fd 14739 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14740 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 14741}
14742
fa555837
DV		 14743static bool
14744intel_check_plane_mapping(struct intel_crtc *crtc)
14745{
7eb552ae
BW		 14746 struct drm_device *dev = crtc->base.dev;
14747 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 14748 u32 reg, val;
14749
7eb552ae 14750 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 14751 return true;
14752
14753 reg = DSPCNTR(!crtc->plane);
14754 val = I915_READ(reg);
14755
14756 if ((val & DISPLAY_PLANE_ENABLE) &&
14757 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14758 return false;
14759
14760 return true;
14761}
14762
24929352
DV		 14763static void intel_sanitize_crtc(struct intel_crtc *crtc)
14764{
14765 struct drm_device *dev = crtc->base.dev;
14766 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 14767 u32 reg;
24929352 14768
24929352 14769 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 14770 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 14771 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14772
d3eaf884 14773 /* restore vblank interrupts to correct state */
9625604c 14774 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 14775 if (crtc->active) {
14776 update_scanline_offset(crtc);
9625604c
DV		 14777 drm_crtc_vblank_on(&crtc->base);
14778 }
d3eaf884 14779
24929352 14780 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 14781 * disable the crtc (and hence change the state) if it is wrong. Note
14782 * that gen4+ has a fixed plane -> pipe mapping. */
14783 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 14784 struct intel_connector *connector;
14785 bool plane;
14786
24929352
DV		 14787 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14788 crtc->base.base.id);
14789
14790 /* Pipe has the wrong plane attached and the plane is active.
14791 * Temporarily change the plane mapping and disable everything
14792 * ... */
14793 plane = crtc->plane;
14794 crtc->plane = !plane;
9c8958bc 14795 crtc->primary_enabled = true;
24929352
DV		 14796 dev_priv->display.crtc_disable(&crtc->base);
14797 crtc->plane = plane;
14798
14799 /* ... and break all links. */
3a3371ff 14800 for_each_intel_connector(dev, connector) {
24929352
DV		 14801 if (connector->encoder->base.crtc != &crtc->base)
14802 continue;
14803
7f1950fb
EE		 14804 connector->base.dpms = DRM_MODE_DPMS_OFF;
14805 connector->base.encoder = NULL;
24929352 14806 }
7f1950fb
EE		 14807 /* multiple connectors may have the same encoder:
14808 * handle them and break crtc link separately */
3a3371ff 14809 for_each_intel_connector(dev, connector)
7f1950fb
EE		 14810 if (connector->encoder->base.crtc == &crtc->base) {
14811 connector->encoder->base.crtc = NULL;
14812 connector->encoder->connectors_active = false;
14813 }
24929352
DV		 14814
14815 WARN_ON(crtc->active);
83d65738 14816 crtc->base.state->enable = false;
24929352
DV		 14817 crtc->base.enabled = false;
14818 }
24929352 14819
7fad798e
DV		 14820 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14821 crtc->pipe == PIPE_A && !crtc->active) {
14822 /* BIOS forgot to enable pipe A, this mostly happens after
14823 * resume. Force-enable the pipe to fix this, the update_dpms
14824 * call below we restore the pipe to the right state, but leave
14825 * the required bits on. */
14826 intel_enable_pipe_a(dev);
14827 }
14828
24929352
DV		 14829 /* Adjust the state of the output pipe according to whether we
14830 * have active connectors/encoders. */
14831 intel_crtc_update_dpms(&crtc->base);
14832
83d65738 14833 if (crtc->active != crtc->base.state->enable) {
24929352
DV		 14834 struct intel_encoder *encoder;
14835
14836 /* This can happen either due to bugs in the get_hw_state
14837 * functions or because the pipe is force-enabled due to the
14838 * pipe A quirk. */
14839 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14840 crtc->base.base.id,
83d65738 14841 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 14842 crtc->active ? "enabled" : "disabled");
14843
83d65738 14844 crtc->base.state->enable = crtc->active;
24929352
DV		 14845 crtc->base.enabled = crtc->active;
14846
14847 /* Because we only establish the connector -> encoder ->
14848 * crtc links if something is active, this means the
14849 * crtc is now deactivated. Break the links. connector
14850 * -> encoder links are only establish when things are
14851 * actually up, hence no need to break them. */
14852 WARN_ON(crtc->active);
14853
14854 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14855 WARN_ON(encoder->connectors_active);
14856 encoder->base.crtc = NULL;
14857 }
14858 }
c5ab3bc0 14859
a3ed6aad 14860 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 14861 /*
14862 * We start out with underrun reporting disabled to avoid races.
14863 * For correct bookkeeping mark this on active crtcs.
14864 *
c5ab3bc0
DV		 14865 * Also on gmch platforms we dont have any hardware bits to
14866 * disable the underrun reporting. Which means we need to start
14867 * out with underrun reporting disabled also on inactive pipes,
14868 * since otherwise we'll complain about the garbage we read when
14869 * e.g. coming up after runtime pm.
14870 *
4cc31489
DV		 14871 * No protection against concurrent access is required - at
14872 * worst a fifo underrun happens which also sets this to false.
14873 */
14874 crtc->cpu_fifo_underrun_disabled = true;
14875 crtc->pch_fifo_underrun_disabled = true;
14876 }
24929352
DV		 14877}
14878
14879static void intel_sanitize_encoder(struct intel_encoder *encoder)
14880{
14881 struct intel_connector *connector;
14882 struct drm_device *dev = encoder->base.dev;
14883
14884 /* We need to check both for a crtc link (meaning that the
14885 * encoder is active and trying to read from a pipe) and the
14886 * pipe itself being active. */
14887 bool has_active_crtc = encoder->base.crtc &&
14888 to_intel_crtc(encoder->base.crtc)->active;
14889
14890 if (encoder->connectors_active && !has_active_crtc) {
14891 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14892 encoder->base.base.id,
8e329a03 14893 encoder->base.name);
24929352
DV		 14894
14895 /* Connector is active, but has no active pipe. This is
14896 * fallout from our resume register restoring. Disable
14897 * the encoder manually again. */
14898 if (encoder->base.crtc) {
14899 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14900 encoder->base.base.id,
8e329a03 14901 encoder->base.name);
24929352 14902 encoder->disable(encoder);
a62d1497
VS		 14903 if (encoder->post_disable)
14904 encoder->post_disable(encoder);
24929352 14905 }
7f1950fb
EE		 14906 encoder->base.crtc = NULL;
14907 encoder->connectors_active = false;
24929352
DV		 14908
14909 /* Inconsistent output/port/pipe state happens presumably due to
14910 * a bug in one of the get_hw_state functions. Or someplace else
14911 * in our code, like the register restore mess on resume. Clamp
14912 * things to off as a safer default. */
3a3371ff 14913 for_each_intel_connector(dev, connector) {
24929352
DV		 14914 if (connector->encoder != encoder)
14915 continue;
7f1950fb
EE		 14916 connector->base.dpms = DRM_MODE_DPMS_OFF;
14917 connector->base.encoder = NULL;
24929352
DV		 14918 }
14919 }
14920 /* Enabled encoders without active connectors will be fixed in
14921 * the crtc fixup. */
14922}
14923
04098753 14924void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 14925{
14926 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 14927 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 14928
04098753
ID		 14929 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14930 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14931 i915_disable_vga(dev);
14932 }
14933}
14934
14935void i915_redisable_vga(struct drm_device *dev)
14936{
14937 struct drm_i915_private *dev_priv = dev->dev_private;
14938
8dc8a27c
PZ		 14939 /* This function can be called both from intel_modeset_setup_hw_state or
14940 * at a very early point in our resume sequence, where the power well
14941 * structures are not yet restored. Since this function is at a very
14942 * paranoid "someone might have enabled VGA while we were not looking"
14943 * level, just check if the power well is enabled instead of trying to
14944 * follow the "don't touch the power well if we don't need it" policy
14945 * the rest of the driver uses. */
f458ebbc 14946 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 14947 return;
14948
04098753 14949 i915_redisable_vga_power_on(dev);
0fde901f
KM		 14950}
14951
98ec7739
VS		 14952static bool primary_get_hw_state(struct intel_crtc *crtc)
14953{
14954 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14955
14956 if (!crtc->active)
14957 return false;
14958
14959 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14960}
14961
30e984df 14962static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 14963{
14964 struct drm_i915_private *dev_priv = dev->dev_private;
14965 enum pipe pipe;
24929352
DV		 14966 struct intel_crtc *crtc;
14967 struct intel_encoder *encoder;
14968 struct intel_connector *connector;
5358901f 14969 int i;
24929352 14970
d3fcc808 14971 for_each_intel_crtc(dev, crtc) {
6e3c9717 14972 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 14973
6e3c9717 14974 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 14975
0e8ffe1b 14976 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 14977 crtc->config);
24929352 14978
83d65738 14979 crtc->base.state->enable = crtc->active;
24929352 14980 crtc->base.enabled = crtc->active;
98ec7739 14981 crtc->primary_enabled = primary_get_hw_state(crtc);
24929352
DV		 14982
14983 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14984 crtc->base.base.id,
14985 crtc->active ? "enabled" : "disabled");
14986 }
14987
5358901f
DV		 14988 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14989 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14990
3e369b76
ACO		 14991 pll->on = pll->get_hw_state(dev_priv, pll,
14992 &pll->config.hw_state);
5358901f 14993 pll->active = 0;
3e369b76 14994 pll->config.crtc_mask = 0;
d3fcc808 14995 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 14996 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 14997 pll->active++;
3e369b76 14998 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 14999 }
5358901f 15000 }
5358901f 15001
1e6f2ddc 15002 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15003 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15004
3e369b76 15005 if (pll->config.crtc_mask)
bd2bb1b9 15006 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15007 }
15008
b2784e15 15009 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15010 pipe = 0;
15011
15012 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15013 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15014 encoder->base.crtc = &crtc->base;
6e3c9717 15015 encoder->get_config(encoder, crtc->config);
24929352
DV		 15016 } else {
15017 encoder->base.crtc = NULL;
15018 }
15019
15020 encoder->connectors_active = false;
6f2bcceb 15021 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15022 encoder->base.base.id,
8e329a03 15023 encoder->base.name,
24929352 15024 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15025 pipe_name(pipe));
24929352
DV		 15026 }
15027
3a3371ff 15028 for_each_intel_connector(dev, connector) {
24929352
DV		 15029 if (connector->get_hw_state(connector)) {
15030 connector->base.dpms = DRM_MODE_DPMS_ON;
15031 connector->encoder->connectors_active = true;
15032 connector->base.encoder = &connector->encoder->base;
15033 } else {
15034 connector->base.dpms = DRM_MODE_DPMS_OFF;
15035 connector->base.encoder = NULL;
15036 }
15037 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15038 connector->base.base.id,
c23cc417 15039 connector->base.name,
24929352
DV		 15040 connector->base.encoder ? "enabled" : "disabled");
15041 }
30e984df
DV		 15042}
15043
15044/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15045 * and i915 state tracking structures. */
15046void intel_modeset_setup_hw_state(struct drm_device *dev,
15047 bool force_restore)
15048{
15049 struct drm_i915_private *dev_priv = dev->dev_private;
15050 enum pipe pipe;
30e984df
DV		 15051 struct intel_crtc *crtc;
15052 struct intel_encoder *encoder;
35c95375 15053 int i;
30e984df
DV		 15054
15055 intel_modeset_readout_hw_state(dev);
24929352 15056
babea61d
JB		 15057 /*
15058 * Now that we have the config, copy it to each CRTC struct
15059 * Note that this could go away if we move to using crtc_config
15060 * checking everywhere.
15061 */
d3fcc808 15062 for_each_intel_crtc(dev, crtc) {
d330a953 15063 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 15064 intel_mode_from_pipe_config(&crtc->base.mode,
15065 crtc->config);
babea61d
JB		 15066 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15067 crtc->base.base.id);
15068 drm_mode_debug_printmodeline(&crtc->base.mode);
15069 }
15070 }
15071
24929352 15072 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15073 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15074 intel_sanitize_encoder(encoder);
15075 }
15076
055e393f 15077 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15078 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15079 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15080 intel_dump_pipe_config(crtc, crtc->config,
15081 "[setup_hw_state]");
24929352 15082 }
9a935856 15083
d29b2f9d
ACO		 15084 intel_modeset_update_connector_atomic_state(dev);
15085
35c95375
DV		 15086 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15087 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15088
15089 if (!pll->on || pll->active)
15090 continue;
15091
15092 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15093
15094 pll->disable(dev_priv, pll);
15095 pll->on = false;
15096 }
15097
3078999f
PB		 15098 if (IS_GEN9(dev))
15099 skl_wm_get_hw_state(dev);
15100 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 15101 ilk_wm_get_hw_state(dev);
15102
45e2b5f6 15103 if (force_restore) {
7d0bc1ea
VS		 15104 i915_redisable_vga(dev);
15105
f30da187
DV		 15106 /*
15107 * We need to use raw interfaces for restoring state to avoid
15108 * checking (bogus) intermediate states.
15109 */
055e393f 15110 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 15111 struct drm_crtc *crtc =
15112 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 15113
83a57153 15114 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 15115 }
15116 } else {
15117 intel_modeset_update_staged_output_state(dev);
15118 }
8af6cf88
DV		 15119
15120 intel_modeset_check_state(dev);
2c7111db
CW		 15121}
15122
15123void intel_modeset_gem_init(struct drm_device *dev)
15124{
92122789 15125 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15126 struct drm_crtc *c;
2ff8fde1 15127 struct drm_i915_gem_object *obj;
e0d6149b 15128 int ret;
484b41dd 15129
ae48434c
ID		 15130 mutex_lock(&dev->struct_mutex);
15131 intel_init_gt_powersave(dev);
15132 mutex_unlock(&dev->struct_mutex);
15133
92122789
JB		 15134 /*
15135 * There may be no VBT; and if the BIOS enabled SSC we can
15136 * just keep using it to avoid unnecessary flicker. Whereas if the
15137 * BIOS isn't using it, don't assume it will work even if the VBT
15138 * indicates as much.
15139 */
15140 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15141 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15142 DREF_SSC1_ENABLE);
15143
1833b134 15144 intel_modeset_init_hw(dev);
02e792fb
DV		 15145
15146 intel_setup_overlay(dev);
484b41dd
JB		 15147
15148 /*
15149 * Make sure any fbs we allocated at startup are properly
15150 * pinned & fenced. When we do the allocation it's too early
15151 * for this.
15152 */
70e1e0ec 15153 for_each_crtc(dev, c) {
2ff8fde1
MR		 15154 obj = intel_fb_obj(c->primary->fb);
15155 if (obj == NULL)
484b41dd
JB		 15156 continue;
15157
e0d6149b
TU		 15158 mutex_lock(&dev->struct_mutex);
15159 ret = intel_pin_and_fence_fb_obj(c->primary,
15160 c->primary->fb,
15161 c->primary->state,
15162 NULL);
15163 mutex_unlock(&dev->struct_mutex);
15164 if (ret) {
484b41dd
JB		 15165 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15166 to_intel_crtc(c)->pipe);
66e514c1
DA		 15167 drm_framebuffer_unreference(c->primary->fb);
15168 c->primary->fb = NULL;
afd65eb4 15169 update_state_fb(c->primary);
484b41dd
JB		 15170 }
15171 }
0962c3c9
VS		 15172
15173 intel_backlight_register(dev);
79e53945
JB		 15174}
15175
4932e2c3
ID		 15176void intel_connector_unregister(struct intel_connector *intel_connector)
15177{
15178 struct drm_connector *connector = &intel_connector->base;
15179
15180 intel_panel_destroy_backlight(connector);
34ea3d38 15181 drm_connector_unregister(connector);
4932e2c3
ID		 15182}
15183
79e53945
JB		 15184void intel_modeset_cleanup(struct drm_device *dev)
15185{
652c393a 15186 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15187 struct drm_connector *connector;
652c393a 15188
2eb5252e
ID		 15189 intel_disable_gt_powersave(dev);
15190
0962c3c9
VS		 15191 intel_backlight_unregister(dev);
15192
fd0c0642
DV		 15193 /*
15194 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15195 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15196 * experience fancy races otherwise.
15197 */
2aeb7d3a 15198 intel_irq_uninstall(dev_priv);
eb21b92b 15199
fd0c0642
DV		 15200 /*
15201 * Due to the hpd irq storm handling the hotplug work can re-arm the
15202 * poll handlers. Hence disable polling after hpd handling is shut down.
15203 */
f87ea761 15204 drm_kms_helper_poll_fini(dev);
fd0c0642 15205
652c393a
JB		 15206 mutex_lock(&dev->struct_mutex);
15207
723bfd70
JB		 15208 intel_unregister_dsm_handler();
15209
7ff0ebcc 15210 intel_fbc_disable(dev);
e70236a8 15211
69341a5e
KH		 15212 mutex_unlock(&dev->struct_mutex);
15213
1630fe75
CW		 15214 /* flush any delayed tasks or pending work */
15215 flush_scheduled_work();
15216
db31af1d
JN		 15217 /* destroy the backlight and sysfs files before encoders/connectors */
15218 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15219 struct intel_connector *intel_connector;
15220
15221 intel_connector = to_intel_connector(connector);
15222 intel_connector->unregister(intel_connector);
db31af1d 15223 }
d9255d57 15224
79e53945 15225 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15226
15227 intel_cleanup_overlay(dev);
ae48434c
ID		 15228
15229 mutex_lock(&dev->struct_mutex);
15230 intel_cleanup_gt_powersave(dev);
15231 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15232}
15233
f1c79df3
ZW		 15234/*
15235 * Return which encoder is currently attached for connector.
15236 */
df0e9248 15237struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15238{
df0e9248
CW		 15239 return &intel_attached_encoder(connector)->base;
15240}
f1c79df3 15241
df0e9248
CW		 15242void intel_connector_attach_encoder(struct intel_connector *connector,
15243 struct intel_encoder *encoder)
15244{
15245 connector->encoder = encoder;
15246 drm_mode_connector_attach_encoder(&connector->base,
15247 &encoder->base);
79e53945 15248}
28d52043
DA		 15249
15250/*
15251 * set vga decode state - true == enable VGA decode
15252 */
15253int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15254{
15255 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15256 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15257 u16 gmch_ctrl;
15258
75fa041d
CW		 15259 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15260 DRM_ERROR("failed to read control word\n");
15261 return -EIO;
15262 }
15263
c0cc8a55
CW		 15264 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15265 return 0;
15266
28d52043
DA		 15267 if (state)
15268 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15269 else
15270 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15271
15272 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15273 DRM_ERROR("failed to write control word\n");
15274 return -EIO;
15275 }
15276
28d52043
DA		 15277 return 0;
15278}
c4a1d9e4 15279
c4a1d9e4 15280struct intel_display_error_state {
ff57f1b0
PZ		 15281
15282 u32 power_well_driver;
15283
63b66e5b
CW		 15284 int num_transcoders;
15285
c4a1d9e4
CW		 15286 struct intel_cursor_error_state {
15287 u32 control;
15288 u32 position;
15289 u32 base;
15290 u32 size;
52331309 15291 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15292
15293 struct intel_pipe_error_state {
ddf9c536 15294 bool power_domain_on;
c4a1d9e4 15295 u32 source;
f301b1e1 15296 u32 stat;
52331309 15297 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15298
15299 struct intel_plane_error_state {
15300 u32 control;
15301 u32 stride;
15302 u32 size;
15303 u32 pos;
15304 u32 addr;
15305 u32 surface;
15306 u32 tile_offset;
52331309 15307 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15308
15309 struct intel_transcoder_error_state {
ddf9c536 15310 bool power_domain_on;
63b66e5b
CW		 15311 enum transcoder cpu_transcoder;
15312
15313 u32 conf;
15314
15315 u32 htotal;
15316 u32 hblank;
15317 u32 hsync;
15318 u32 vtotal;
15319 u32 vblank;
15320 u32 vsync;
15321 } transcoder[4];
c4a1d9e4
CW		 15322};
15323
15324struct intel_display_error_state *
15325intel_display_capture_error_state(struct drm_device *dev)
15326{
fbee40df 15327 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15328 struct intel_display_error_state *error;
63b66e5b
CW		 15329 int transcoders[] = {
15330 TRANSCODER_A,
15331 TRANSCODER_B,
15332 TRANSCODER_C,
15333 TRANSCODER_EDP,
15334 };
c4a1d9e4
CW		 15335 int i;
15336
63b66e5b
CW		 15337 if (INTEL_INFO(dev)->num_pipes == 0)
15338 return NULL;
15339
9d1cb914 15340 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15341 if (error == NULL)
15342 return NULL;
15343
190be112 15344 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15345 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15346
055e393f 15347 for_each_pipe(dev_priv, i) {
ddf9c536 15348 error->pipe[i].power_domain_on =
f458ebbc
DV		 15349 __intel_display_power_is_enabled(dev_priv,
15350 POWER_DOMAIN_PIPE(i));
ddf9c536 15351 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15352 continue;
15353
5efb3e28
VS		 15354 error->cursor[i].control = I915_READ(CURCNTR(i));
15355 error->cursor[i].position = I915_READ(CURPOS(i));
15356 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15357
15358 error->plane[i].control = I915_READ(DSPCNTR(i));
15359 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15360 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15361 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15362 error->plane[i].pos = I915_READ(DSPPOS(i));
15363 }
ca291363
PZ		 15364 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15365 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15366 if (INTEL_INFO(dev)->gen >= 4) {
15367 error->plane[i].surface = I915_READ(DSPSURF(i));
15368 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15369 }
15370
c4a1d9e4 15371 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15372
3abfce77 15373 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15374 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15375 }
15376
15377 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15378 if (HAS_DDI(dev_priv->dev))
15379 error->num_transcoders++; /* Account for eDP. */
15380
15381 for (i = 0; i < error->num_transcoders; i++) {
15382 enum transcoder cpu_transcoder = transcoders[i];
15383
ddf9c536 15384 error->transcoder[i].power_domain_on =
f458ebbc 15385 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15386 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15387 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15388 continue;
15389
63b66e5b
CW		 15390 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15391
15392 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15393 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15394 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15395 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15396 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15397 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15398 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15399 }
15400
15401 return error;
15402}
15403
edc3d884
MK		 15404#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15405
c4a1d9e4 15406void
edc3d884 15407intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15408 struct drm_device *dev,
15409 struct intel_display_error_state *error)
15410{
055e393f 15411 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15412 int i;
15413
63b66e5b
CW		 15414 if (!error)
15415 return;
15416
edc3d884 15417 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15418 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15419 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15420 error->power_well_driver);
055e393f 15421 for_each_pipe(dev_priv, i) {
edc3d884 15422 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15423 err_printf(m, " Power: %s\n",
15424 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15425 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15426 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15427
15428 err_printf(m, "Plane [%d]:\n", i);
15429 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15430 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15431 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15432 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15433 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15434 }
4b71a570 15435 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15436 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15437 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15438 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15439 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15440 }
15441
edc3d884
MK		 15442 err_printf(m, "Cursor [%d]:\n", i);
15443 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15444 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15445 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15446 }
63b66e5b
CW		 15447
15448 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15449 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15450 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15451 err_printf(m, " Power: %s\n",
15452 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15453 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15454 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15455 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15456 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15457 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15458 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15459 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15460 }
c4a1d9e4 15461}
e2fcdaa9
VS		 15462
15463void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15464{
15465 struct intel_crtc *crtc;
15466
15467 for_each_intel_crtc(dev, crtc) {
15468 struct intel_unpin_work *work;
e2fcdaa9 15469
5e2d7afc 15470 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15471
15472 work = crtc->unpin_work;
15473
15474 if (work && work->event &&
15475 work->event->base.file_priv == file) {
15476 kfree(work->event);
15477 work->event = NULL;
15478 }
15479
5e2d7afc 15480 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15481 }
15482}
Linux kernel - Deliverables
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