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drm/i915: move intel_crtc->fdi_lanes to pipe_config
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
f4808ab8
VS		 62 /**
63 * find_pll() - Find the best values for the PLL
64 * @limit: limits for the PLL
65 * @crtc: current CRTC
66 * @target: target frequency in kHz
67 * @refclk: reference clock frequency in kHz
68 * @match_clock: if provided, @best_clock P divider must
69 * match the P divider from @match_clock
70 * used for LVDS downclocking
71 * @best_clock: best PLL values found
72 *
73 * Returns true on success, false on failure.
74 */
75 bool (*find_pll)(const intel_limit_t *limit,
76 struct drm_crtc *crtc,
77 int target, int refclk,
78 intel_clock_t *match_clock,
79 intel_clock_t *best_clock);
d4906093 80};
79e53945 81
2377b741
JB		 82/* FDI */
83#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
84
d2acd215
DV		 85int
86intel_pch_rawclk(struct drm_device *dev)
87{
88 struct drm_i915_private *dev_priv = dev->dev_private;
89
90 WARN_ON(!HAS_PCH_SPLIT(dev));
91
92 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
93}
94
d4906093
ML		 95static bool
96intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
d4906093
ML		 99static bool
100intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 101 int target, int refclk, intel_clock_t *match_clock,
102 intel_clock_t *best_clock);
79e53945 103
a0c4da24
JB		 104static bool
105intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
108
021357ac
CW		 109static inline u32 /* units of 100MHz */
110intel_fdi_link_freq(struct drm_device *dev)
111{
8b99e68c
CW		 112 if (IS_GEN5(dev)) {
113 struct drm_i915_private *dev_priv = dev->dev_private;
114 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
115 } else
116 return 27;
021357ac
CW		 117}
118
e4b36699 119static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 120 .dot = { .min = 25000, .max = 350000 },
121 .vco = { .min = 930000, .max = 1400000 },
122 .n = { .min = 3, .max = 16 },
123 .m = { .min = 96, .max = 140 },
124 .m1 = { .min = 18, .max = 26 },
125 .m2 = { .min = 6, .max = 16 },
126 .p = { .min = 4, .max = 128 },
127 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 128 .p2 = { .dot_limit = 165000,
129 .p2_slow = 4, .p2_fast = 2 },
d4906093 130 .find_pll = intel_find_best_PLL,
e4b36699
KP		 131};
132
133static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 134 .dot = { .min = 25000, .max = 350000 },
135 .vco = { .min = 930000, .max = 1400000 },
136 .n = { .min = 3, .max = 16 },
137 .m = { .min = 96, .max = 140 },
138 .m1 = { .min = 18, .max = 26 },
139 .m2 = { .min = 6, .max = 16 },
140 .p = { .min = 4, .max = 128 },
141 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 142 .p2 = { .dot_limit = 165000,
143 .p2_slow = 14, .p2_fast = 7 },
d4906093 144 .find_pll = intel_find_best_PLL,
e4b36699 145};
273e27ca 146
e4b36699 147static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 148 .dot = { .min = 20000, .max = 400000 },
149 .vco = { .min = 1400000, .max = 2800000 },
150 .n = { .min = 1, .max = 6 },
151 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 152 .m1 = { .min = 8, .max = 18 },
153 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 154 .p = { .min = 5, .max = 80 },
155 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 156 .p2 = { .dot_limit = 200000,
157 .p2_slow = 10, .p2_fast = 5 },
d4906093 158 .find_pll = intel_find_best_PLL,
e4b36699
KP		 159};
160
161static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 162 .dot = { .min = 20000, .max = 400000 },
163 .vco = { .min = 1400000, .max = 2800000 },
164 .n = { .min = 1, .max = 6 },
165 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 166 .m1 = { .min = 8, .max = 18 },
167 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 168 .p = { .min = 7, .max = 98 },
169 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 170 .p2 = { .dot_limit = 112000,
171 .p2_slow = 14, .p2_fast = 7 },
d4906093 172 .find_pll = intel_find_best_PLL,
e4b36699
KP		 173};
174
273e27ca 175
e4b36699 176static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 177 .dot = { .min = 25000, .max = 270000 },
178 .vco = { .min = 1750000, .max = 3500000},
179 .n = { .min = 1, .max = 4 },
180 .m = { .min = 104, .max = 138 },
181 .m1 = { .min = 17, .max = 23 },
182 .m2 = { .min = 5, .max = 11 },
183 .p = { .min = 10, .max = 30 },
184 .p1 = { .min = 1, .max = 3},
185 .p2 = { .dot_limit = 270000,
186 .p2_slow = 10,
187 .p2_fast = 10
044c7c41 188 },
d4906093 189 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 190};
191
192static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 193 .dot = { .min = 22000, .max = 400000 },
194 .vco = { .min = 1750000, .max = 3500000},
195 .n = { .min = 1, .max = 4 },
196 .m = { .min = 104, .max = 138 },
197 .m1 = { .min = 16, .max = 23 },
198 .m2 = { .min = 5, .max = 11 },
199 .p = { .min = 5, .max = 80 },
200 .p1 = { .min = 1, .max = 8},
201 .p2 = { .dot_limit = 165000,
202 .p2_slow = 10, .p2_fast = 5 },
d4906093 203 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 204};
205
206static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 207 .dot = { .min = 20000, .max = 115000 },
208 .vco = { .min = 1750000, .max = 3500000 },
209 .n = { .min = 1, .max = 3 },
210 .m = { .min = 104, .max = 138 },
211 .m1 = { .min = 17, .max = 23 },
212 .m2 = { .min = 5, .max = 11 },
213 .p = { .min = 28, .max = 112 },
214 .p1 = { .min = 2, .max = 8 },
215 .p2 = { .dot_limit = 0,
216 .p2_slow = 14, .p2_fast = 14
044c7c41 217 },
d4906093 218 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 219};
220
221static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 222 .dot = { .min = 80000, .max = 224000 },
223 .vco = { .min = 1750000, .max = 3500000 },
224 .n = { .min = 1, .max = 3 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 14, .max = 42 },
229 .p1 = { .min = 2, .max = 6 },
230 .p2 = { .dot_limit = 0,
231 .p2_slow = 7, .p2_fast = 7
044c7c41 232 },
d4906093 233 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 234};
235
f2b115e6 236static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 237 .dot = { .min = 20000, .max = 400000},
238 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 239 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 240 .n = { .min = 3, .max = 6 },
241 .m = { .min = 2, .max = 256 },
273e27ca 242 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 243 .m1 = { .min = 0, .max = 0 },
244 .m2 = { .min = 0, .max = 254 },
245 .p = { .min = 5, .max = 80 },
246 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 247 .p2 = { .dot_limit = 200000,
248 .p2_slow = 10, .p2_fast = 5 },
6115707b 249 .find_pll = intel_find_best_PLL,
e4b36699
KP		 250};
251
f2b115e6 252static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 253 .dot = { .min = 20000, .max = 400000 },
254 .vco = { .min = 1700000, .max = 3500000 },
255 .n = { .min = 3, .max = 6 },
256 .m = { .min = 2, .max = 256 },
257 .m1 = { .min = 0, .max = 0 },
258 .m2 = { .min = 0, .max = 254 },
259 .p = { .min = 7, .max = 112 },
260 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 261 .p2 = { .dot_limit = 112000,
262 .p2_slow = 14, .p2_fast = 14 },
6115707b 263 .find_pll = intel_find_best_PLL,
e4b36699
KP		 264};
265
273e27ca
EA		 266/* Ironlake / Sandybridge
267 *
268 * We calculate clock using (register_value + 2) for N/M1/M2, so here
269 * the range value for them is (actual_value - 2).
270 */
b91ad0ec 271static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 272 .dot = { .min = 25000, .max = 350000 },
273 .vco = { .min = 1760000, .max = 3510000 },
274 .n = { .min = 1, .max = 5 },
275 .m = { .min = 79, .max = 127 },
276 .m1 = { .min = 12, .max = 22 },
277 .m2 = { .min = 5, .max = 9 },
278 .p = { .min = 5, .max = 80 },
279 .p1 = { .min = 1, .max = 8 },
280 .p2 = { .dot_limit = 225000,
281 .p2_slow = 10, .p2_fast = 5 },
4547668a 282 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 283};
284
b91ad0ec 285static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 286 .dot = { .min = 25000, .max = 350000 },
287 .vco = { .min = 1760000, .max = 3510000 },
288 .n = { .min = 1, .max = 3 },
289 .m = { .min = 79, .max = 118 },
290 .m1 = { .min = 12, .max = 22 },
291 .m2 = { .min = 5, .max = 9 },
292 .p = { .min = 28, .max = 112 },
293 .p1 = { .min = 2, .max = 8 },
294 .p2 = { .dot_limit = 225000,
295 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 296 .find_pll = intel_g4x_find_best_PLL,
297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 127 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 56 },
307 .p1 = { .min = 2, .max = 8 },
308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 310 .find_pll = intel_g4x_find_best_PLL,
311};
312
273e27ca 313/* LVDS 100mhz refclk limits. */
b91ad0ec 314static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 2 },
318 .m = { .min = 79, .max = 126 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 28, .max = 112 },
0206e353 322 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 325 .find_pll = intel_g4x_find_best_PLL,
326};
327
328static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 329 .dot = { .min = 25000, .max = 350000 },
330 .vco = { .min = 1760000, .max = 3510000 },
331 .n = { .min = 1, .max = 3 },
332 .m = { .min = 79, .max = 126 },
333 .m1 = { .min = 12, .max = 22 },
334 .m2 = { .min = 5, .max = 9 },
335 .p = { .min = 14, .max = 42 },
0206e353 336 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 337 .p2 = { .dot_limit = 225000,
338 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 339 .find_pll = intel_g4x_find_best_PLL,
340};
341
a0c4da24
JB		 342static const intel_limit_t intel_limits_vlv_dac = {
343 .dot = { .min = 25000, .max = 270000 },
344 .vco = { .min = 4000000, .max = 6000000 },
345 .n = { .min = 1, .max = 7 },
346 .m = { .min = 22, .max = 450 }, /* guess */
347 .m1 = { .min = 2, .max = 3 },
348 .m2 = { .min = 11, .max = 156 },
349 .p = { .min = 10, .max = 30 },
75e53986 350 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 351 .p2 = { .dot_limit = 270000,
352 .p2_slow = 2, .p2_fast = 20 },
353 .find_pll = intel_vlv_find_best_pll,
354};
355
356static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 357 .dot = { .min = 25000, .max = 270000 },
358 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 359 .n = { .min = 1, .max = 7 },
360 .m = { .min = 60, .max = 300 }, /* guess */
361 .m1 = { .min = 2, .max = 3 },
362 .m2 = { .min = 11, .max = 156 },
363 .p = { .min = 10, .max = 30 },
364 .p1 = { .min = 2, .max = 3 },
365 .p2 = { .dot_limit = 270000,
366 .p2_slow = 2, .p2_fast = 20 },
367 .find_pll = intel_vlv_find_best_pll,
368};
369
370static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 371 .dot = { .min = 25000, .max = 270000 },
372 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 373 .n = { .min = 1, .max = 7 },
74a4dd2e 374 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 375 .m1 = { .min = 2, .max = 3 },
376 .m2 = { .min = 11, .max = 156 },
377 .p = { .min = 10, .max = 30 },
75e53986 378 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 379 .p2 = { .dot_limit = 270000,
380 .p2_slow = 2, .p2_fast = 20 },
381 .find_pll = intel_vlv_find_best_pll,
382};
383
57f350b6
JB		 384u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
385{
09153000 386 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 387
57f350b6
JB		 388 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
389 DRM_ERROR("DPIO idle wait timed out\n");
09153000 390 return 0;
57f350b6
JB		 391 }
392
393 I915_WRITE(DPIO_REG, reg);
394 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
395 DPIO_BYTE);
396 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
397 DRM_ERROR("DPIO read wait timed out\n");
09153000 398 return 0;
57f350b6 399 }
57f350b6 400
09153000 401 return I915_READ(DPIO_DATA);
57f350b6
JB		 402}
403
e2fa6fba 404void intel_dpio_write(struct drm_i915_private *dev_priv, int reg, u32 val)
a0c4da24 405{
09153000 406 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 407
a0c4da24
JB		 408 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
409 DRM_ERROR("DPIO idle wait timed out\n");
09153000 410 return;
a0c4da24
JB		 411 }
412
413 I915_WRITE(DPIO_DATA, val);
414 I915_WRITE(DPIO_REG, reg);
415 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
416 DPIO_BYTE);
417 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
418 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 419}
420
1b894b59
CW		 421static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
422 int refclk)
2c07245f 423{
b91ad0ec 424 struct drm_device *dev = crtc->dev;
2c07245f 425 const intel_limit_t *limit;
b91ad0ec
ZW		 426
427 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 428 if (intel_is_dual_link_lvds(dev)) {
1b894b59 429 if (refclk == 100000)
b91ad0ec
ZW		 430 limit = &intel_limits_ironlake_dual_lvds_100m;
431 else
432 limit = &intel_limits_ironlake_dual_lvds;
433 } else {
1b894b59 434 if (refclk == 100000)
b91ad0ec
ZW		 435 limit = &intel_limits_ironlake_single_lvds_100m;
436 else
437 limit = &intel_limits_ironlake_single_lvds;
438 }
c6bb3538 439 } else
b91ad0ec 440 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 441
442 return limit;
443}
444
044c7c41
ML		 445static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
446{
447 struct drm_device *dev = crtc->dev;
044c7c41
ML		 448 const intel_limit_t *limit;
449
450 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 451 if (intel_is_dual_link_lvds(dev))
e4b36699 452 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 453 else
e4b36699 454 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 455 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
456 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 457 limit = &intel_limits_g4x_hdmi;
044c7c41 458 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 459 limit = &intel_limits_g4x_sdvo;
044c7c41 460 } else /* The option is for other outputs */
e4b36699 461 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 462
463 return limit;
464}
465
1b894b59 466static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 467{
468 struct drm_device *dev = crtc->dev;
469 const intel_limit_t *limit;
470
bad720ff 471 if (HAS_PCH_SPLIT(dev))
1b894b59 472 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 473 else if (IS_G4X(dev)) {
044c7c41 474 limit = intel_g4x_limit(crtc);
f2b115e6 475 } else if (IS_PINEVIEW(dev)) {
2177832f 476 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 477 limit = &intel_limits_pineview_lvds;
2177832f 478 else
f2b115e6 479 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 480 } else if (IS_VALLEYVIEW(dev)) {
481 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
482 limit = &intel_limits_vlv_dac;
483 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
484 limit = &intel_limits_vlv_hdmi;
485 else
486 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 487 } else if (!IS_GEN2(dev)) {
488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
489 limit = &intel_limits_i9xx_lvds;
490 else
491 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 492 } else {
493 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 494 limit = &intel_limits_i8xx_lvds;
79e53945 495 else
e4b36699 496 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 497 }
498 return limit;
499}
500
f2b115e6
AJ		 501/* m1 is reserved as 0 in Pineview, n is a ring counter */
502static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 503{
2177832f
SL		 504 clock->m = clock->m2 + 2;
505 clock->p = clock->p1 * clock->p2;
506 clock->vco = refclk * clock->m / clock->n;
507 clock->dot = clock->vco / clock->p;
508}
509
7429e9d4
DV		 510static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
511{
512 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
513}
514
2177832f
SL		 515static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
516{
f2b115e6
AJ		 517 if (IS_PINEVIEW(dev)) {
518 pineview_clock(refclk, clock);
2177832f
SL		 519 return;
520 }
7429e9d4 521 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 522 clock->p = clock->p1 * clock->p2;
523 clock->vco = refclk * clock->m / (clock->n + 2);
524 clock->dot = clock->vco / clock->p;
525}
526
79e53945
JB		 527/**
528 * Returns whether any output on the specified pipe is of the specified type
529 */
4ef69c7a 530bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 531{
4ef69c7a 532 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 533 struct intel_encoder *encoder;
534
6c2b7c12
DV		 535 for_each_encoder_on_crtc(dev, crtc, encoder)
536 if (encoder->type == type)
4ef69c7a
CW		 537 return true;
538
539 return false;
79e53945
JB		 540}
541
7c04d1d9 542#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 543/**
544 * Returns whether the given set of divisors are valid for a given refclk with
545 * the given connectors.
546 */
547
1b894b59
CW		 548static bool intel_PLL_is_valid(struct drm_device *dev,
549 const intel_limit_t *limit,
550 const intel_clock_t *clock)
79e53945 551{
79e53945 552 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 553 INTELPllInvalid("p1 out of range\n");
79e53945 554 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 555 INTELPllInvalid("p out of range\n");
79e53945 556 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 557 INTELPllInvalid("m2 out of range\n");
79e53945 558 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 559 INTELPllInvalid("m1 out of range\n");
f2b115e6 560 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 561 INTELPllInvalid("m1 <= m2\n");
79e53945 562 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 563 INTELPllInvalid("m out of range\n");
79e53945 564 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 565 INTELPllInvalid("n out of range\n");
79e53945 566 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 567 INTELPllInvalid("vco out of range\n");
79e53945
JB		 568 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
569 * connector, etc., rather than just a single range.
570 */
571 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 572 INTELPllInvalid("dot out of range\n");
79e53945
JB		 573
574 return true;
575}
576
d4906093
ML		 577static bool
578intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 579 int target, int refclk, intel_clock_t *match_clock,
580 intel_clock_t *best_clock)
d4906093 581
79e53945
JB		 582{
583 struct drm_device *dev = crtc->dev;
79e53945 584 intel_clock_t clock;
79e53945
JB		 585 int err = target;
586
a210b028 587 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 588 /*
a210b028
DV		 589 * For LVDS just rely on its current settings for dual-channel.
590 * We haven't figured out how to reliably set up different
591 * single/dual channel state, if we even can.
79e53945 592 */
1974cad0 593 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 594 clock.p2 = limit->p2.p2_fast;
595 else
596 clock.p2 = limit->p2.p2_slow;
597 } else {
598 if (target < limit->p2.dot_limit)
599 clock.p2 = limit->p2.p2_slow;
600 else
601 clock.p2 = limit->p2.p2_fast;
602 }
603
0206e353 604 memset(best_clock, 0, sizeof(*best_clock));
79e53945 605
42158660
ZY		 606 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
607 clock.m1++) {
608 for (clock.m2 = limit->m2.min;
609 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 610 /* m1 is always 0 in Pineview */
611 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 612 break;
613 for (clock.n = limit->n.min;
614 clock.n <= limit->n.max; clock.n++) {
615 for (clock.p1 = limit->p1.min;
616 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 617 int this_err;
618
2177832f 619 intel_clock(dev, refclk, &clock);
1b894b59
CW		 620 if (!intel_PLL_is_valid(dev, limit,
621 &clock))
79e53945 622 continue;
cec2f356
SP		 623 if (match_clock &&
624 clock.p != match_clock->p)
625 continue;
79e53945
JB		 626
627 this_err = abs(clock.dot - target);
628 if (this_err < err) {
629 *best_clock = clock;
630 err = this_err;
631 }
632 }
633 }
634 }
635 }
636
637 return (err != target);
638}
639
d4906093
ML		 640static bool
641intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 642 int target, int refclk, intel_clock_t *match_clock,
643 intel_clock_t *best_clock)
d4906093
ML		 644{
645 struct drm_device *dev = crtc->dev;
d4906093
ML		 646 intel_clock_t clock;
647 int max_n;
648 bool found;
6ba770dc
AJ		 649 /* approximately equals target * 0.00585 */
650 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 651 found = false;
652
653 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 654 int lvds_reg;
655
c619eed4 656 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 657 lvds_reg = PCH_LVDS;
658 else
659 lvds_reg = LVDS;
1974cad0 660 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 661 clock.p2 = limit->p2.p2_fast;
662 else
663 clock.p2 = limit->p2.p2_slow;
664 } else {
665 if (target < limit->p2.dot_limit)
666 clock.p2 = limit->p2.p2_slow;
667 else
668 clock.p2 = limit->p2.p2_fast;
669 }
670
671 memset(best_clock, 0, sizeof(*best_clock));
672 max_n = limit->n.max;
f77f13e2 673 /* based on hardware requirement, prefer smaller n to precision */
d4906093 674 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 675 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 676 for (clock.m1 = limit->m1.max;
677 clock.m1 >= limit->m1.min; clock.m1--) {
678 for (clock.m2 = limit->m2.max;
679 clock.m2 >= limit->m2.min; clock.m2--) {
680 for (clock.p1 = limit->p1.max;
681 clock.p1 >= limit->p1.min; clock.p1--) {
682 int this_err;
683
2177832f 684 intel_clock(dev, refclk, &clock);
1b894b59
CW		 685 if (!intel_PLL_is_valid(dev, limit,
686 &clock))
d4906093 687 continue;
1b894b59
CW		 688
689 this_err = abs(clock.dot - target);
d4906093
ML		 690 if (this_err < err_most) {
691 *best_clock = clock;
692 err_most = this_err;
693 max_n = clock.n;
694 found = true;
695 }
696 }
697 }
698 }
699 }
2c07245f
ZW		 700 return found;
701}
702
a0c4da24
JB		 703static bool
704intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
705 int target, int refclk, intel_clock_t *match_clock,
706 intel_clock_t *best_clock)
707{
708 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
709 u32 m, n, fastclk;
710 u32 updrate, minupdate, fracbits, p;
711 unsigned long bestppm, ppm, absppm;
712 int dotclk, flag;
713
af447bd3 714 flag = 0;
a0c4da24
JB		 715 dotclk = target * 1000;
716 bestppm = 1000000;
717 ppm = absppm = 0;
718 fastclk = dotclk / (2*100);
719 updrate = 0;
720 minupdate = 19200;
721 fracbits = 1;
722 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
723 bestm1 = bestm2 = bestp1 = bestp2 = 0;
724
725 /* based on hardware requirement, prefer smaller n to precision */
726 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
727 updrate = refclk / n;
728 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
729 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
730 if (p2 > 10)
731 p2 = p2 - 1;
732 p = p1 * p2;
733 /* based on hardware requirement, prefer bigger m1,m2 values */
734 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
735 m2 = (((2*(fastclk * p * n / m1 )) +
736 refclk) / (2*refclk));
737 m = m1 * m2;
738 vco = updrate * m;
739 if (vco >= limit->vco.min && vco < limit->vco.max) {
740 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
741 absppm = (ppm > 0) ? ppm : (-ppm);
742 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
743 bestppm = 0;
744 flag = 1;
745 }
746 if (absppm < bestppm - 10) {
747 bestppm = absppm;
748 flag = 1;
749 }
750 if (flag) {
751 bestn = n;
752 bestm1 = m1;
753 bestm2 = m2;
754 bestp1 = p1;
755 bestp2 = p2;
756 flag = 0;
757 }
758 }
759 }
760 }
761 }
762 }
763 best_clock->n = bestn;
764 best_clock->m1 = bestm1;
765 best_clock->m2 = bestm2;
766 best_clock->p1 = bestp1;
767 best_clock->p2 = bestp2;
768
769 return true;
770}
a4fc5ed6 771
a5c961d1
PZ		 772enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
773 enum pipe pipe)
774{
775 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
777
3b117c8f 778 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 779}
780
a928d536
PZ		 781static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
782{
783 struct drm_i915_private *dev_priv = dev->dev_private;
784 u32 frame, frame_reg = PIPEFRAME(pipe);
785
786 frame = I915_READ(frame_reg);
787
788 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
789 DRM_DEBUG_KMS("vblank wait timed out\n");
790}
791
9d0498a2
JB		 792/**
793 * intel_wait_for_vblank - wait for vblank on a given pipe
794 * @dev: drm device
795 * @pipe: pipe to wait for
796 *
797 * Wait for vblank to occur on a given pipe. Needed for various bits of
798 * mode setting code.
799 */
800void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 801{
9d0498a2 802 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 803 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 804
a928d536
PZ		 805 if (INTEL_INFO(dev)->gen >= 5) {
806 ironlake_wait_for_vblank(dev, pipe);
807 return;
808 }
809
300387c0
CW		 810 /* Clear existing vblank status. Note this will clear any other
811 * sticky status fields as well.
812 *
813 * This races with i915_driver_irq_handler() with the result
814 * that either function could miss a vblank event. Here it is not
815 * fatal, as we will either wait upon the next vblank interrupt or
816 * timeout. Generally speaking intel_wait_for_vblank() is only
817 * called during modeset at which time the GPU should be idle and
818 * should *not* be performing page flips and thus not waiting on
819 * vblanks...
820 * Currently, the result of us stealing a vblank from the irq
821 * handler is that a single frame will be skipped during swapbuffers.
822 */
823 I915_WRITE(pipestat_reg,
824 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
825
9d0498a2 826 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 827 if (wait_for(I915_READ(pipestat_reg) &
828 PIPE_VBLANK_INTERRUPT_STATUS,
829 50))
9d0498a2
JB		 830 DRM_DEBUG_KMS("vblank wait timed out\n");
831}
832
ab7ad7f6
KP		 833/*
834 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 835 * @dev: drm device
836 * @pipe: pipe to wait for
837 *
838 * After disabling a pipe, we can't wait for vblank in the usual way,
839 * spinning on the vblank interrupt status bit, since we won't actually
840 * see an interrupt when the pipe is disabled.
841 *
ab7ad7f6
KP		 842 * On Gen4 and above:
843 * wait for the pipe register state bit to turn off
844 *
845 * Otherwise:
846 * wait for the display line value to settle (it usually
847 * ends up stopping at the start of the next frame).
58e10eb9 848 *
9d0498a2 849 */
58e10eb9 850void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 851{
852 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 853 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
854 pipe);
ab7ad7f6
KP		 855
856 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 857 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 858
859 /* Wait for the Pipe State to go off */
58e10eb9
CW		 860 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
861 100))
284637d9 862 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 863 } else {
837ba00f 864 u32 last_line, line_mask;
58e10eb9 865 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 866 unsigned long timeout = jiffies + msecs_to_jiffies(100);
867
837ba00f
PZ		 868 if (IS_GEN2(dev))
869 line_mask = DSL_LINEMASK_GEN2;
870 else
871 line_mask = DSL_LINEMASK_GEN3;
872
ab7ad7f6
KP		 873 /* Wait for the display line to settle */
874 do {
837ba00f 875 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 876 mdelay(5);
837ba00f 877 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 878 time_after(timeout, jiffies));
879 if (time_after(jiffies, timeout))
284637d9 880 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 881 }
79e53945
JB		 882}
883
b0ea7d37
DL		 884/*
885 * ibx_digital_port_connected - is the specified port connected?
886 * @dev_priv: i915 private structure
887 * @port: the port to test
888 *
889 * Returns true if @port is connected, false otherwise.
890 */
891bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
892 struct intel_digital_port *port)
893{
894 u32 bit;
895
c36346e3
DL		 896 if (HAS_PCH_IBX(dev_priv->dev)) {
897 switch(port->port) {
898 case PORT_B:
899 bit = SDE_PORTB_HOTPLUG;
900 break;
901 case PORT_C:
902 bit = SDE_PORTC_HOTPLUG;
903 break;
904 case PORT_D:
905 bit = SDE_PORTD_HOTPLUG;
906 break;
907 default:
908 return true;
909 }
910 } else {
911 switch(port->port) {
912 case PORT_B:
913 bit = SDE_PORTB_HOTPLUG_CPT;
914 break;
915 case PORT_C:
916 bit = SDE_PORTC_HOTPLUG_CPT;
917 break;
918 case PORT_D:
919 bit = SDE_PORTD_HOTPLUG_CPT;
920 break;
921 default:
922 return true;
923 }
b0ea7d37
DL		 924 }
925
926 return I915_READ(SDEISR) & bit;
927}
928
b24e7179
JB		 929static const char *state_string(bool enabled)
930{
931 return enabled ? "on" : "off";
932}
933
934/* Only for pre-ILK configs */
935static void assert_pll(struct drm_i915_private *dev_priv,
936 enum pipe pipe, bool state)
937{
938 int reg;
939 u32 val;
940 bool cur_state;
941
942 reg = DPLL(pipe);
943 val = I915_READ(reg);
944 cur_state = !!(val & DPLL_VCO_ENABLE);
945 WARN(cur_state != state,
946 "PLL state assertion failure (expected %s, current %s)\n",
947 state_string(state), state_string(cur_state));
948}
949#define assert_pll_enabled(d, p) assert_pll(d, p, true)
950#define assert_pll_disabled(d, p) assert_pll(d, p, false)
951
040484af
JB		 952/* For ILK+ */
953static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 954 struct intel_pch_pll *pll,
955 struct intel_crtc *crtc,
956 bool state)
040484af 957{
040484af
JB		 958 u32 val;
959 bool cur_state;
960
9d82aa17
ED		 961 if (HAS_PCH_LPT(dev_priv->dev)) {
962 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
963 return;
964 }
965
92b27b08
CW		 966 if (WARN (!pll,
967 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 968 return;
ee7b9f93 969
92b27b08
CW		 970 val = I915_READ(pll->pll_reg);
971 cur_state = !!(val & DPLL_VCO_ENABLE);
972 WARN(cur_state != state,
973 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
974 pll->pll_reg, state_string(state), state_string(cur_state), val);
975
976 /* Make sure the selected PLL is correctly attached to the transcoder */
977 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 978 u32 pch_dpll;
979
980 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 981 cur_state = pll->pll_reg == _PCH_DPLL_B;
982 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
4bb6f1f3
VS		 983 "PLL[%d] not attached to this transcoder %c: %08x\n",
984 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
92b27b08
CW		 985 cur_state = !!(val >> (4*crtc->pipe + 3));
986 WARN(cur_state != state,
4bb6f1f3 987 "PLL[%d] not %s on this transcoder %c: %08x\n",
92b27b08
CW		 988 pll->pll_reg == _PCH_DPLL_B,
989 state_string(state),
4bb6f1f3 990 pipe_name(crtc->pipe),
92b27b08
CW		 991 val);
992 }
d3ccbe86 993 }
040484af 994}
92b27b08
CW		 995#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
996#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 997
998static void assert_fdi_tx(struct drm_i915_private *dev_priv,
999 enum pipe pipe, bool state)
1000{
1001 int reg;
1002 u32 val;
1003 bool cur_state;
ad80a810
PZ		 1004 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1005 pipe);
040484af 1006
affa9354
PZ		 1007 if (HAS_DDI(dev_priv->dev)) {
1008 /* DDI does not have a specific FDI_TX register */
ad80a810 1009 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1010 val = I915_READ(reg);
ad80a810 1011 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1012 } else {
1013 reg = FDI_TX_CTL(pipe);
1014 val = I915_READ(reg);
1015 cur_state = !!(val & FDI_TX_ENABLE);
1016 }
040484af
JB		 1017 WARN(cur_state != state,
1018 "FDI TX state assertion failure (expected %s, current %s)\n",
1019 state_string(state), state_string(cur_state));
1020}
1021#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1022#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1023
1024static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1025 enum pipe pipe, bool state)
1026{
1027 int reg;
1028 u32 val;
1029 bool cur_state;
1030
d63fa0dc
PZ		 1031 reg = FDI_RX_CTL(pipe);
1032 val = I915_READ(reg);
1033 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1034 WARN(cur_state != state,
1035 "FDI RX state assertion failure (expected %s, current %s)\n",
1036 state_string(state), state_string(cur_state));
1037}
1038#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1039#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1040
1041static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1042 enum pipe pipe)
1043{
1044 int reg;
1045 u32 val;
1046
1047 /* ILK FDI PLL is always enabled */
1048 if (dev_priv->info->gen == 5)
1049 return;
1050
bf507ef7 1051 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1052 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1053 return;
1054
040484af
JB		 1055 reg = FDI_TX_CTL(pipe);
1056 val = I915_READ(reg);
1057 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1058}
1059
1060static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1061 enum pipe pipe)
1062{
1063 int reg;
1064 u32 val;
1065
1066 reg = FDI_RX_CTL(pipe);
1067 val = I915_READ(reg);
1068 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1069}
1070
ea0760cf
JB		 1071static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1072 enum pipe pipe)
1073{
1074 int pp_reg, lvds_reg;
1075 u32 val;
1076 enum pipe panel_pipe = PIPE_A;
0de3b485 1077 bool locked = true;
ea0760cf
JB		 1078
1079 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1080 pp_reg = PCH_PP_CONTROL;
1081 lvds_reg = PCH_LVDS;
1082 } else {
1083 pp_reg = PP_CONTROL;
1084 lvds_reg = LVDS;
1085 }
1086
1087 val = I915_READ(pp_reg);
1088 if (!(val & PANEL_POWER_ON) ||
1089 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1090 locked = false;
1091
1092 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1093 panel_pipe = PIPE_B;
1094
1095 WARN(panel_pipe == pipe && locked,
1096 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1097 pipe_name(pipe));
ea0760cf
JB		 1098}
1099
b840d907
JB		 1100void assert_pipe(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
b24e7179
JB		 1102{
1103 int reg;
1104 u32 val;
63d7bbe9 1105 bool cur_state;
702e7a56
PZ		 1106 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1107 pipe);
b24e7179 1108
8e636784
DV		 1109 /* if we need the pipe A quirk it must be always on */
1110 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1111 state = true;
1112
15d199ea
PZ		 1113 if (!intel_using_power_well(dev_priv->dev) &&
1114 cpu_transcoder != TRANSCODER_EDP) {
69310161
PZ		 1115 cur_state = false;
1116 } else {
1117 reg = PIPECONF(cpu_transcoder);
1118 val = I915_READ(reg);
1119 cur_state = !!(val & PIPECONF_ENABLE);
1120 }
1121
63d7bbe9
JB		 1122 WARN(cur_state != state,
1123 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1124 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1125}
1126
931872fc
CW		 1127static void assert_plane(struct drm_i915_private *dev_priv,
1128 enum plane plane, bool state)
b24e7179
JB		 1129{
1130 int reg;
1131 u32 val;
931872fc 1132 bool cur_state;
b24e7179
JB		 1133
1134 reg = DSPCNTR(plane);
1135 val = I915_READ(reg);
931872fc
CW		 1136 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1137 WARN(cur_state != state,
1138 "plane %c assertion failure (expected %s, current %s)\n",
1139 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1140}
1141
931872fc
CW		 1142#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1143#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1144
b24e7179
JB		 1145static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1146 enum pipe pipe)
1147{
1148 int reg, i;
1149 u32 val;
1150 int cur_pipe;
1151
19ec1358 1152 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1153 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1154 reg = DSPCNTR(pipe);
1155 val = I915_READ(reg);
1156 WARN((val & DISPLAY_PLANE_ENABLE),
1157 "plane %c assertion failure, should be disabled but not\n",
1158 plane_name(pipe));
19ec1358 1159 return;
28c05794 1160 }
19ec1358 1161
b24e7179
JB		 1162 /* Need to check both planes against the pipe */
1163 for (i = 0; i < 2; i++) {
1164 reg = DSPCNTR(i);
1165 val = I915_READ(reg);
1166 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1167 DISPPLANE_SEL_PIPE_SHIFT;
1168 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1169 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1170 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1171 }
1172}
1173
19332d7a
JB		 1174static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1175 enum pipe pipe)
1176{
1177 int reg, i;
1178 u32 val;
1179
1180 if (!IS_VALLEYVIEW(dev_priv->dev))
1181 return;
1182
1183 /* Need to check both planes against the pipe */
1184 for (i = 0; i < dev_priv->num_plane; i++) {
1185 reg = SPCNTR(pipe, i);
1186 val = I915_READ(reg);
1187 WARN((val & SP_ENABLE),
06da8da2
VS		 1188 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1189 sprite_name(pipe, i), pipe_name(pipe));
19332d7a
JB		 1190 }
1191}
1192
92f2584a
JB		 1193static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1194{
1195 u32 val;
1196 bool enabled;
1197
9d82aa17
ED		 1198 if (HAS_PCH_LPT(dev_priv->dev)) {
1199 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1200 return;
1201 }
1202
92f2584a
JB		 1203 val = I915_READ(PCH_DREF_CONTROL);
1204 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1205 DREF_SUPERSPREAD_SOURCE_MASK));
1206 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1207}
1208
1209static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1210 enum pipe pipe)
1211{
1212 int reg;
1213 u32 val;
1214 bool enabled;
1215
1216 reg = TRANSCONF(pipe);
1217 val = I915_READ(reg);
1218 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1219 WARN(enabled,
1220 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1221 pipe_name(pipe));
92f2584a
JB		 1222}
1223
4e634389
KP		 1224static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1225 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1226{
1227 if ((val & DP_PORT_EN) == 0)
1228 return false;
1229
1230 if (HAS_PCH_CPT(dev_priv->dev)) {
1231 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1232 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1233 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1234 return false;
1235 } else {
1236 if ((val & DP_PIPE_MASK) != (pipe << 30))
1237 return false;
1238 }
1239 return true;
1240}
1241
1519b995
KP		 1242static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, u32 val)
1244{
dc0fa718 1245 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1246 return false;
1247
1248 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1249 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1250 return false;
1251 } else {
dc0fa718 1252 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1253 return false;
1254 }
1255 return true;
1256}
1257
1258static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1259 enum pipe pipe, u32 val)
1260{
1261 if ((val & LVDS_PORT_EN) == 0)
1262 return false;
1263
1264 if (HAS_PCH_CPT(dev_priv->dev)) {
1265 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1266 return false;
1267 } else {
1268 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1269 return false;
1270 }
1271 return true;
1272}
1273
1274static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1275 enum pipe pipe, u32 val)
1276{
1277 if ((val & ADPA_DAC_ENABLE) == 0)
1278 return false;
1279 if (HAS_PCH_CPT(dev_priv->dev)) {
1280 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1281 return false;
1282 } else {
1283 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1284 return false;
1285 }
1286 return true;
1287}
1288
291906f1 1289static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1290 enum pipe pipe, int reg, u32 port_sel)
291906f1 1291{
47a05eca 1292 u32 val = I915_READ(reg);
4e634389 1293 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1294 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1295 reg, pipe_name(pipe));
de9a35ab 1296
75c5da27
DV		 1297 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1298 && (val & DP_PIPEB_SELECT),
de9a35ab 1299 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1300}
1301
1302static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1303 enum pipe pipe, int reg)
1304{
47a05eca 1305 u32 val = I915_READ(reg);
b70ad586 1306 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1307 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1308 reg, pipe_name(pipe));
de9a35ab 1309
dc0fa718 1310 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1311 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1312 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1313}
1314
1315static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1316 enum pipe pipe)
1317{
1318 int reg;
1319 u32 val;
291906f1 1320
f0575e92
KP		 1321 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1322 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1323 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1324
1325 reg = PCH_ADPA;
1326 val = I915_READ(reg);
b70ad586 1327 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1328 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1329 pipe_name(pipe));
291906f1
JB		 1330
1331 reg = PCH_LVDS;
1332 val = I915_READ(reg);
b70ad586 1333 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1334 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1335 pipe_name(pipe));
291906f1 1336
e2debe91
PZ		 1337 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1338 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1339 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1340}
1341
63d7bbe9
JB		 1342/**
1343 * intel_enable_pll - enable a PLL
1344 * @dev_priv: i915 private structure
1345 * @pipe: pipe PLL to enable
1346 *
1347 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1348 * make sure the PLL reg is writable first though, since the panel write
1349 * protect mechanism may be enabled.
1350 *
1351 * Note! This is for pre-ILK only.
7434a255
TR		 1352 *
1353 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1354 */
1355static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1356{
1357 int reg;
1358 u32 val;
1359
58c6eaa2
DV		 1360 assert_pipe_disabled(dev_priv, pipe);
1361
63d7bbe9 1362 /* No really, not for ILK+ */
a0c4da24 1363 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1364
1365 /* PLL is protected by panel, make sure we can write it */
1366 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1367 assert_panel_unlocked(dev_priv, pipe);
1368
1369 reg = DPLL(pipe);
1370 val = I915_READ(reg);
1371 val |= DPLL_VCO_ENABLE;
1372
1373 /* We do this three times for luck */
1374 I915_WRITE(reg, val);
1375 POSTING_READ(reg);
1376 udelay(150); /* wait for warmup */
1377 I915_WRITE(reg, val);
1378 POSTING_READ(reg);
1379 udelay(150); /* wait for warmup */
1380 I915_WRITE(reg, val);
1381 POSTING_READ(reg);
1382 udelay(150); /* wait for warmup */
1383}
1384
1385/**
1386 * intel_disable_pll - disable a PLL
1387 * @dev_priv: i915 private structure
1388 * @pipe: pipe PLL to disable
1389 *
1390 * Disable the PLL for @pipe, making sure the pipe is off first.
1391 *
1392 * Note! This is for pre-ILK only.
1393 */
1394static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1395{
1396 int reg;
1397 u32 val;
1398
1399 /* Don't disable pipe A or pipe A PLLs if needed */
1400 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1401 return;
1402
1403 /* Make sure the pipe isn't still relying on us */
1404 assert_pipe_disabled(dev_priv, pipe);
1405
1406 reg = DPLL(pipe);
1407 val = I915_READ(reg);
1408 val &= ~DPLL_VCO_ENABLE;
1409 I915_WRITE(reg, val);
1410 POSTING_READ(reg);
1411}
1412
a416edef
ED		 1413/* SBI access */
1414static void
988d6ee8
PZ		 1415intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1416 enum intel_sbi_destination destination)
a416edef 1417{
988d6ee8 1418 u32 tmp;
a416edef 1419
09153000 1420 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1421
39fb50f6 1422 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1423 100)) {
1424 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1425 return;
a416edef
ED		 1426 }
1427
988d6ee8
PZ		 1428 I915_WRITE(SBI_ADDR, (reg << 16));
1429 I915_WRITE(SBI_DATA, value);
1430
1431 if (destination == SBI_ICLK)
1432 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1433 else
1434 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1435 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1436
39fb50f6 1437 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1438 100)) {
1439 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1440 return;
a416edef 1441 }
a416edef
ED		 1442}
1443
1444static u32
988d6ee8
PZ		 1445intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1446 enum intel_sbi_destination destination)
a416edef 1447{
39fb50f6 1448 u32 value = 0;
09153000 1449 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1450
39fb50f6 1451 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1452 100)) {
1453 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1454 return 0;
a416edef
ED		 1455 }
1456
988d6ee8
PZ		 1457 I915_WRITE(SBI_ADDR, (reg << 16));
1458
1459 if (destination == SBI_ICLK)
1460 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1461 else
1462 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1463 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1464
39fb50f6 1465 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1466 100)) {
1467 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1468 return 0;
a416edef
ED		 1469 }
1470
09153000 1471 return I915_READ(SBI_DATA);
a416edef
ED		 1472}
1473
89b667f8
JB		 1474void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1475{
1476 u32 port_mask;
1477
1478 if (!port)
1479 port_mask = DPLL_PORTB_READY_MASK;
1480 else
1481 port_mask = DPLL_PORTC_READY_MASK;
1482
1483 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1484 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1485 'B' + port, I915_READ(DPLL(0)));
1486}
1487
92f2584a 1488/**
b6b4e185 1489 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1490 * @dev_priv: i915 private structure
1491 * @pipe: pipe PLL to enable
1492 *
1493 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1494 * drives the transcoder clock.
1495 */
b6b4e185 1496static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1497{
ee7b9f93 1498 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1499 struct intel_pch_pll *pll;
92f2584a
JB		 1500 int reg;
1501 u32 val;
1502
48da64a8 1503 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1504 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1505 pll = intel_crtc->pch_pll;
1506 if (pll == NULL)
1507 return;
1508
1509 if (WARN_ON(pll->refcount == 0))
1510 return;
ee7b9f93
JB		 1511
1512 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1513 pll->pll_reg, pll->active, pll->on,
1514 intel_crtc->base.base.id);
92f2584a
JB		 1515
1516 /* PCH refclock must be enabled first */
1517 assert_pch_refclk_enabled(dev_priv);
1518
ee7b9f93 1519 if (pll->active++ && pll->on) {
92b27b08 1520 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1521 return;
1522 }
1523
1524 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1525
1526 reg = pll->pll_reg;
92f2584a
JB		 1527 val = I915_READ(reg);
1528 val |= DPLL_VCO_ENABLE;
1529 I915_WRITE(reg, val);
1530 POSTING_READ(reg);
1531 udelay(200);
ee7b9f93
JB		 1532
1533 pll->on = true;
92f2584a
JB		 1534}
1535
ee7b9f93 1536static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1537{
ee7b9f93
JB		 1538 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1539 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1540 int reg;
ee7b9f93 1541 u32 val;
4c609cb8 1542
92f2584a
JB		 1543 /* PCH only available on ILK+ */
1544 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1545 if (pll == NULL)
1546 return;
92f2584a 1547
48da64a8
CW		 1548 if (WARN_ON(pll->refcount == 0))
1549 return;
7a419866 1550
ee7b9f93
JB		 1551 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1552 pll->pll_reg, pll->active, pll->on,
1553 intel_crtc->base.base.id);
7a419866 1554
48da64a8 1555 if (WARN_ON(pll->active == 0)) {
92b27b08 1556 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1557 return;
1558 }
1559
ee7b9f93 1560 if (--pll->active) {
92b27b08 1561 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1562 return;
ee7b9f93
JB		 1563 }
1564
1565 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1566
1567 /* Make sure transcoder isn't still depending on us */
1568 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1569
ee7b9f93 1570 reg = pll->pll_reg;
92f2584a
JB		 1571 val = I915_READ(reg);
1572 val &= ~DPLL_VCO_ENABLE;
1573 I915_WRITE(reg, val);
1574 POSTING_READ(reg);
1575 udelay(200);
ee7b9f93
JB		 1576
1577 pll->on = false;
92f2584a
JB		 1578}
1579
b8a4f404
PZ		 1580static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1581 enum pipe pipe)
040484af 1582{
23670b32 1583 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1584 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1585 uint32_t reg, val, pipeconf_val;
040484af
JB		 1586
1587 /* PCH only available on ILK+ */
1588 BUG_ON(dev_priv->info->gen < 5);
1589
1590 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1591 assert_pch_pll_enabled(dev_priv,
1592 to_intel_crtc(crtc)->pch_pll,
1593 to_intel_crtc(crtc));
040484af
JB		 1594
1595 /* FDI must be feeding us bits for PCH ports */
1596 assert_fdi_tx_enabled(dev_priv, pipe);
1597 assert_fdi_rx_enabled(dev_priv, pipe);
1598
23670b32
DV		 1599 if (HAS_PCH_CPT(dev)) {
1600 /* Workaround: Set the timing override bit before enabling the
1601 * pch transcoder. */
1602 reg = TRANS_CHICKEN2(pipe);
1603 val = I915_READ(reg);
1604 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1605 I915_WRITE(reg, val);
59c859d6 1606 }
23670b32 1607
040484af
JB		 1608 reg = TRANSCONF(pipe);
1609 val = I915_READ(reg);
5f7f726d 1610 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1611
1612 if (HAS_PCH_IBX(dev_priv->dev)) {
1613 /*
1614 * make the BPC in transcoder be consistent with
1615 * that in pipeconf reg.
1616 */
dfd07d72
DV		 1617 val &= ~PIPECONF_BPC_MASK;
1618 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1619 }
5f7f726d
PZ		 1620
1621 val &= ~TRANS_INTERLACE_MASK;
1622 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1623 if (HAS_PCH_IBX(dev_priv->dev) &&
1624 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1625 val |= TRANS_LEGACY_INTERLACED_ILK;
1626 else
1627 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1628 else
1629 val |= TRANS_PROGRESSIVE;
1630
040484af
JB		 1631 I915_WRITE(reg, val | TRANS_ENABLE);
1632 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1633 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1634}
1635
8fb033d7 1636static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1637 enum transcoder cpu_transcoder)
040484af 1638{
8fb033d7 1639 u32 val, pipeconf_val;
8fb033d7
PZ		 1640
1641 /* PCH only available on ILK+ */
1642 BUG_ON(dev_priv->info->gen < 5);
1643
8fb033d7 1644 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1645 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1646 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1647
223a6fdf
PZ		 1648 /* Workaround: set timing override bit. */
1649 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1650 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1651 I915_WRITE(_TRANSA_CHICKEN2, val);
1652
25f3ef11 1653 val = TRANS_ENABLE;
937bb610 1654 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1655
9a76b1c6
PZ		 1656 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1657 PIPECONF_INTERLACED_ILK)
a35f2679 1658 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1659 else
1660 val |= TRANS_PROGRESSIVE;
1661
25f3ef11 1662 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1663 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1664 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1665}
1666
b8a4f404
PZ		 1667static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1668 enum pipe pipe)
040484af 1669{
23670b32
DV		 1670 struct drm_device *dev = dev_priv->dev;
1671 uint32_t reg, val;
040484af
JB		 1672
1673 /* FDI relies on the transcoder */
1674 assert_fdi_tx_disabled(dev_priv, pipe);
1675 assert_fdi_rx_disabled(dev_priv, pipe);
1676
291906f1
JB		 1677 /* Ports must be off as well */
1678 assert_pch_ports_disabled(dev_priv, pipe);
1679
040484af
JB		 1680 reg = TRANSCONF(pipe);
1681 val = I915_READ(reg);
1682 val &= ~TRANS_ENABLE;
1683 I915_WRITE(reg, val);
1684 /* wait for PCH transcoder off, transcoder state */
1685 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1686 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1687
1688 if (!HAS_PCH_IBX(dev)) {
1689 /* Workaround: Clear the timing override chicken bit again. */
1690 reg = TRANS_CHICKEN2(pipe);
1691 val = I915_READ(reg);
1692 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1693 I915_WRITE(reg, val);
1694 }
040484af
JB		 1695}
1696
ab4d966c 1697static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1698{
8fb033d7
PZ		 1699 u32 val;
1700
8a52fd9f 1701 val = I915_READ(_TRANSACONF);
8fb033d7 1702 val &= ~TRANS_ENABLE;
8a52fd9f 1703 I915_WRITE(_TRANSACONF, val);
8fb033d7 1704 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1705 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1706 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1707
1708 /* Workaround: clear timing override bit. */
1709 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1710 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1711 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1712}
1713
b24e7179 1714/**
309cfea8 1715 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1716 * @dev_priv: i915 private structure
1717 * @pipe: pipe to enable
040484af 1718 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1719 *
1720 * Enable @pipe, making sure that various hardware specific requirements
1721 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1722 *
1723 * @pipe should be %PIPE_A or %PIPE_B.
1724 *
1725 * Will wait until the pipe is actually running (i.e. first vblank) before
1726 * returning.
1727 */
040484af
JB		 1728static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1729 bool pch_port)
b24e7179 1730{
702e7a56
PZ		 1731 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1732 pipe);
1a240d4d 1733 enum pipe pch_transcoder;
b24e7179
JB		 1734 int reg;
1735 u32 val;
1736
58c6eaa2
DV		 1737 assert_planes_disabled(dev_priv, pipe);
1738 assert_sprites_disabled(dev_priv, pipe);
1739
681e5811 1740 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1741 pch_transcoder = TRANSCODER_A;
1742 else
1743 pch_transcoder = pipe;
1744
b24e7179
JB		 1745 /*
1746 * A pipe without a PLL won't actually be able to drive bits from
1747 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1748 * need the check.
1749 */
1750 if (!HAS_PCH_SPLIT(dev_priv->dev))
1751 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1752 else {
1753 if (pch_port) {
1754 /* if driving the PCH, we need FDI enabled */
cc391bbb 1755 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1756 assert_fdi_tx_pll_enabled(dev_priv,
1757 (enum pipe) cpu_transcoder);
040484af
JB		 1758 }
1759 /* FIXME: assert CPU port conditions for SNB+ */
1760 }
b24e7179 1761
702e7a56 1762 reg = PIPECONF(cpu_transcoder);
b24e7179 1763 val = I915_READ(reg);
00d70b15
CW		 1764 if (val & PIPECONF_ENABLE)
1765 return;
1766
1767 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1768 intel_wait_for_vblank(dev_priv->dev, pipe);
1769}
1770
1771/**
309cfea8 1772 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1773 * @dev_priv: i915 private structure
1774 * @pipe: pipe to disable
1775 *
1776 * Disable @pipe, making sure that various hardware specific requirements
1777 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1778 *
1779 * @pipe should be %PIPE_A or %PIPE_B.
1780 *
1781 * Will wait until the pipe has shut down before returning.
1782 */
1783static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1784 enum pipe pipe)
1785{
702e7a56
PZ		 1786 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1787 pipe);
b24e7179
JB		 1788 int reg;
1789 u32 val;
1790
1791 /*
1792 * Make sure planes won't keep trying to pump pixels to us,
1793 * or we might hang the display.
1794 */
1795 assert_planes_disabled(dev_priv, pipe);
19332d7a 1796 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1797
1798 /* Don't disable pipe A or pipe A PLLs if needed */
1799 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1800 return;
1801
702e7a56 1802 reg = PIPECONF(cpu_transcoder);
b24e7179 1803 val = I915_READ(reg);
00d70b15
CW		 1804 if ((val & PIPECONF_ENABLE) == 0)
1805 return;
1806
1807 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1808 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1809}
1810
d74362c9
KP		 1811/*
1812 * Plane regs are double buffered, going from enabled->disabled needs a
1813 * trigger in order to latch. The display address reg provides this.
1814 */
6f1d69b0 1815void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1816 enum plane plane)
1817{
14f86147
DL		 1818 if (dev_priv->info->gen >= 4)
1819 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1820 else
1821 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1822}
1823
b24e7179
JB		 1824/**
1825 * intel_enable_plane - enable a display plane on a given pipe
1826 * @dev_priv: i915 private structure
1827 * @plane: plane to enable
1828 * @pipe: pipe being fed
1829 *
1830 * Enable @plane on @pipe, making sure that @pipe is running first.
1831 */
1832static void intel_enable_plane(struct drm_i915_private *dev_priv,
1833 enum plane plane, enum pipe pipe)
1834{
1835 int reg;
1836 u32 val;
1837
1838 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1839 assert_pipe_enabled(dev_priv, pipe);
1840
1841 reg = DSPCNTR(plane);
1842 val = I915_READ(reg);
00d70b15
CW		 1843 if (val & DISPLAY_PLANE_ENABLE)
1844 return;
1845
1846 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1847 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1848 intel_wait_for_vblank(dev_priv->dev, pipe);
1849}
1850
b24e7179
JB		 1851/**
1852 * intel_disable_plane - disable a display plane
1853 * @dev_priv: i915 private structure
1854 * @plane: plane to disable
1855 * @pipe: pipe consuming the data
1856 *
1857 * Disable @plane; should be an independent operation.
1858 */
1859static void intel_disable_plane(struct drm_i915_private *dev_priv,
1860 enum plane plane, enum pipe pipe)
1861{
1862 int reg;
1863 u32 val;
1864
1865 reg = DSPCNTR(plane);
1866 val = I915_READ(reg);
00d70b15
CW		 1867 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1868 return;
1869
1870 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1871 intel_flush_display_plane(dev_priv, plane);
1872 intel_wait_for_vblank(dev_priv->dev, pipe);
1873}
1874
693db184
CW		 1875static bool need_vtd_wa(struct drm_device *dev)
1876{
1877#ifdef CONFIG_INTEL_IOMMU
1878 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1879 return true;
1880#endif
1881 return false;
1882}
1883
127bd2ac 1884int
48b956c5 1885intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1886 struct drm_i915_gem_object *obj,
919926ae 1887 struct intel_ring_buffer *pipelined)
6b95a207 1888{
ce453d81 1889 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1890 u32 alignment;
1891 int ret;
1892
05394f39 1893 switch (obj->tiling_mode) {
6b95a207 1894 case I915_TILING_NONE:
534843da
CW		 1895 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1896 alignment = 128 * 1024;
a6c45cf0 1897 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1898 alignment = 4 * 1024;
1899 else
1900 alignment = 64 * 1024;
6b95a207
KH		 1901 break;
1902 case I915_TILING_X:
1903 /* pin() will align the object as required by fence */
1904 alignment = 0;
1905 break;
1906 case I915_TILING_Y:
8bb6e959
DV		 1907 /* Despite that we check this in framebuffer_init userspace can
1908 * screw us over and change the tiling after the fact. Only
1909 * pinned buffers can't change their tiling. */
1910 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1911 return -EINVAL;
1912 default:
1913 BUG();
1914 }
1915
693db184
CW		 1916 /* Note that the w/a also requires 64 PTE of padding following the
1917 * bo. We currently fill all unused PTE with the shadow page and so
1918 * we should always have valid PTE following the scanout preventing
1919 * the VT-d warning.
1920 */
1921 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1922 alignment = 256 * 1024;
1923
ce453d81 1924 dev_priv->mm.interruptible = false;
2da3b9b9 1925 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1926 if (ret)
ce453d81 1927 goto err_interruptible;
6b95a207
KH		 1928
1929 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1930 * fence, whereas 965+ only requires a fence if using
1931 * framebuffer compression. For simplicity, we always install
1932 * a fence as the cost is not that onerous.
1933 */
06d98131 1934 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1935 if (ret)
1936 goto err_unpin;
1690e1eb 1937
9a5a53b3 1938 i915_gem_object_pin_fence(obj);
6b95a207 1939
ce453d81 1940 dev_priv->mm.interruptible = true;
6b95a207 1941 return 0;
48b956c5
CW		 1942
1943err_unpin:
1944 i915_gem_object_unpin(obj);
ce453d81
CW		 1945err_interruptible:
1946 dev_priv->mm.interruptible = true;
48b956c5 1947 return ret;
6b95a207
KH		 1948}
1949
1690e1eb
CW		 1950void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1951{
1952 i915_gem_object_unpin_fence(obj);
1953 i915_gem_object_unpin(obj);
1954}
1955
c2c75131
DV		 1956/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1957 * is assumed to be a power-of-two. */
bc752862
CW		 1958unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1959 unsigned int tiling_mode,
1960 unsigned int cpp,
1961 unsigned int pitch)
c2c75131 1962{
bc752862
CW		 1963 if (tiling_mode != I915_TILING_NONE) {
1964 unsigned int tile_rows, tiles;
c2c75131 1965
bc752862
CW		 1966 tile_rows = *y / 8;
1967 *y %= 8;
c2c75131 1968
bc752862
CW		 1969 tiles = *x / (512/cpp);
1970 *x %= 512/cpp;
1971
1972 return tile_rows * pitch * 8 + tiles * 4096;
1973 } else {
1974 unsigned int offset;
1975
1976 offset = *y * pitch + *x * cpp;
1977 *y = 0;
1978 *x = (offset & 4095) / cpp;
1979 return offset & -4096;
1980 }
c2c75131
DV		 1981}
1982
17638cd6
JB		 1983static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1984 int x, int y)
81255565
JB		 1985{
1986 struct drm_device *dev = crtc->dev;
1987 struct drm_i915_private *dev_priv = dev->dev_private;
1988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1989 struct intel_framebuffer *intel_fb;
05394f39 1990 struct drm_i915_gem_object *obj;
81255565 1991 int plane = intel_crtc->plane;
e506a0c6 1992 unsigned long linear_offset;
81255565 1993 u32 dspcntr;
5eddb70b 1994 u32 reg;
81255565
JB		 1995
1996 switch (plane) {
1997 case 0:
1998 case 1:
1999 break;
2000 default:
84f44ce7 2001 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 2002 return -EINVAL;
2003 }
2004
2005 intel_fb = to_intel_framebuffer(fb);
2006 obj = intel_fb->obj;
81255565 2007
5eddb70b
CW		 2008 reg = DSPCNTR(plane);
2009 dspcntr = I915_READ(reg);
81255565
JB		 2010 /* Mask out pixel format bits in case we change it */
2011 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2012 switch (fb->pixel_format) {
2013 case DRM_FORMAT_C8:
81255565
JB		 2014 dspcntr |= DISPPLANE_8BPP;
2015 break;
57779d06
VS		 2016 case DRM_FORMAT_XRGB1555:
2017 case DRM_FORMAT_ARGB1555:
2018 dspcntr |= DISPPLANE_BGRX555;
81255565 2019 break;
57779d06
VS		 2020 case DRM_FORMAT_RGB565:
2021 dspcntr |= DISPPLANE_BGRX565;
2022 break;
2023 case DRM_FORMAT_XRGB8888:
2024 case DRM_FORMAT_ARGB8888:
2025 dspcntr |= DISPPLANE_BGRX888;
2026 break;
2027 case DRM_FORMAT_XBGR8888:
2028 case DRM_FORMAT_ABGR8888:
2029 dspcntr |= DISPPLANE_RGBX888;
2030 break;
2031 case DRM_FORMAT_XRGB2101010:
2032 case DRM_FORMAT_ARGB2101010:
2033 dspcntr |= DISPPLANE_BGRX101010;
2034 break;
2035 case DRM_FORMAT_XBGR2101010:
2036 case DRM_FORMAT_ABGR2101010:
2037 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2038 break;
2039 default:
baba133a 2040 BUG();
81255565 2041 }
57779d06 2042
a6c45cf0 2043 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2044 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2045 dspcntr |= DISPPLANE_TILED;
2046 else
2047 dspcntr &= ~DISPPLANE_TILED;
2048 }
2049
5eddb70b 2050 I915_WRITE(reg, dspcntr);
81255565 2051
e506a0c6 2052 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2053
c2c75131
DV		 2054 if (INTEL_INFO(dev)->gen >= 4) {
2055 intel_crtc->dspaddr_offset =
bc752862
CW		 2056 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2057 fb->bits_per_pixel / 8,
2058 fb->pitches[0]);
c2c75131
DV		 2059 linear_offset -= intel_crtc->dspaddr_offset;
2060 } else {
e506a0c6 2061 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2062 }
e506a0c6
DV		 2063
2064 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2065 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2066 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2067 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2068 I915_MODIFY_DISPBASE(DSPSURF(plane),
2069 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2070 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2071 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2072 } else
e506a0c6 2073 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2074 POSTING_READ(reg);
81255565 2075
17638cd6
JB		 2076 return 0;
2077}
2078
2079static int ironlake_update_plane(struct drm_crtc *crtc,
2080 struct drm_framebuffer *fb, int x, int y)
2081{
2082 struct drm_device *dev = crtc->dev;
2083 struct drm_i915_private *dev_priv = dev->dev_private;
2084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2085 struct intel_framebuffer *intel_fb;
2086 struct drm_i915_gem_object *obj;
2087 int plane = intel_crtc->plane;
e506a0c6 2088 unsigned long linear_offset;
17638cd6
JB		 2089 u32 dspcntr;
2090 u32 reg;
2091
2092 switch (plane) {
2093 case 0:
2094 case 1:
27f8227b 2095 case 2:
17638cd6
JB		 2096 break;
2097 default:
84f44ce7 2098 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2099 return -EINVAL;
2100 }
2101
2102 intel_fb = to_intel_framebuffer(fb);
2103 obj = intel_fb->obj;
2104
2105 reg = DSPCNTR(plane);
2106 dspcntr = I915_READ(reg);
2107 /* Mask out pixel format bits in case we change it */
2108 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2109 switch (fb->pixel_format) {
2110 case DRM_FORMAT_C8:
17638cd6
JB		 2111 dspcntr |= DISPPLANE_8BPP;
2112 break;
57779d06
VS		 2113 case DRM_FORMAT_RGB565:
2114 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2115 break;
57779d06
VS		 2116 case DRM_FORMAT_XRGB8888:
2117 case DRM_FORMAT_ARGB8888:
2118 dspcntr |= DISPPLANE_BGRX888;
2119 break;
2120 case DRM_FORMAT_XBGR8888:
2121 case DRM_FORMAT_ABGR8888:
2122 dspcntr |= DISPPLANE_RGBX888;
2123 break;
2124 case DRM_FORMAT_XRGB2101010:
2125 case DRM_FORMAT_ARGB2101010:
2126 dspcntr |= DISPPLANE_BGRX101010;
2127 break;
2128 case DRM_FORMAT_XBGR2101010:
2129 case DRM_FORMAT_ABGR2101010:
2130 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2131 break;
2132 default:
baba133a 2133 BUG();
17638cd6
JB		 2134 }
2135
2136 if (obj->tiling_mode != I915_TILING_NONE)
2137 dspcntr |= DISPPLANE_TILED;
2138 else
2139 dspcntr &= ~DISPPLANE_TILED;
2140
2141 /* must disable */
2142 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2143
2144 I915_WRITE(reg, dspcntr);
2145
e506a0c6 2146 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2147 intel_crtc->dspaddr_offset =
bc752862
CW		 2148 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2149 fb->bits_per_pixel / 8,
2150 fb->pitches[0]);
c2c75131 2151 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2152
e506a0c6
DV		 2153 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2154 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2155 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2156 I915_MODIFY_DISPBASE(DSPSURF(plane),
2157 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2158 if (IS_HASWELL(dev)) {
2159 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2160 } else {
2161 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2162 I915_WRITE(DSPLINOFF(plane), linear_offset);
2163 }
17638cd6
JB		 2164 POSTING_READ(reg);
2165
2166 return 0;
2167}
2168
2169/* Assume fb object is pinned & idle & fenced and just update base pointers */
2170static int
2171intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2172 int x, int y, enum mode_set_atomic state)
2173{
2174 struct drm_device *dev = crtc->dev;
2175 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2176
6b8e6ed0
CW		 2177 if (dev_priv->display.disable_fbc)
2178 dev_priv->display.disable_fbc(dev);
3dec0095 2179 intel_increase_pllclock(crtc);
81255565 2180
6b8e6ed0 2181 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2182}
2183
96a02917
VS		 2184void intel_display_handle_reset(struct drm_device *dev)
2185{
2186 struct drm_i915_private *dev_priv = dev->dev_private;
2187 struct drm_crtc *crtc;
2188
2189 /*
2190 * Flips in the rings have been nuked by the reset,
2191 * so complete all pending flips so that user space
2192 * will get its events and not get stuck.
2193 *
2194 * Also update the base address of all primary
2195 * planes to the the last fb to make sure we're
2196 * showing the correct fb after a reset.
2197 *
2198 * Need to make two loops over the crtcs so that we
2199 * don't try to grab a crtc mutex before the
2200 * pending_flip_queue really got woken up.
2201 */
2202
2203 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2205 enum plane plane = intel_crtc->plane;
2206
2207 intel_prepare_page_flip(dev, plane);
2208 intel_finish_page_flip_plane(dev, plane);
2209 }
2210
2211 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2212 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2213
2214 mutex_lock(&crtc->mutex);
2215 if (intel_crtc->active)
2216 dev_priv->display.update_plane(crtc, crtc->fb,
2217 crtc->x, crtc->y);
2218 mutex_unlock(&crtc->mutex);
2219 }
2220}
2221
14667a4b
CW		 2222static int
2223intel_finish_fb(struct drm_framebuffer *old_fb)
2224{
2225 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2226 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2227 bool was_interruptible = dev_priv->mm.interruptible;
2228 int ret;
2229
14667a4b
CW		 2230 /* Big Hammer, we also need to ensure that any pending
2231 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2232 * current scanout is retired before unpinning the old
2233 * framebuffer.
2234 *
2235 * This should only fail upon a hung GPU, in which case we
2236 * can safely continue.
2237 */
2238 dev_priv->mm.interruptible = false;
2239 ret = i915_gem_object_finish_gpu(obj);
2240 dev_priv->mm.interruptible = was_interruptible;
2241
2242 return ret;
2243}
2244
198598d0
VS		 2245static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2246{
2247 struct drm_device *dev = crtc->dev;
2248 struct drm_i915_master_private *master_priv;
2249 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2250
2251 if (!dev->primary->master)
2252 return;
2253
2254 master_priv = dev->primary->master->driver_priv;
2255 if (!master_priv->sarea_priv)
2256 return;
2257
2258 switch (intel_crtc->pipe) {
2259 case 0:
2260 master_priv->sarea_priv->pipeA_x = x;
2261 master_priv->sarea_priv->pipeA_y = y;
2262 break;
2263 case 1:
2264 master_priv->sarea_priv->pipeB_x = x;
2265 master_priv->sarea_priv->pipeB_y = y;
2266 break;
2267 default:
2268 break;
2269 }
2270}
2271
5c3b82e2 2272static int
3c4fdcfb 2273intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2274 struct drm_framebuffer *fb)
79e53945
JB		 2275{
2276 struct drm_device *dev = crtc->dev;
6b8e6ed0 2277 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2279 struct drm_framebuffer *old_fb;
5c3b82e2 2280 int ret;
79e53945
JB		 2281
2282 /* no fb bound */
94352cf9 2283 if (!fb) {
a5071c2f 2284 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2285 return 0;
2286 }
2287
7eb552ae 2288 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2289 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2290 plane_name(intel_crtc->plane),
2291 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2292 return -EINVAL;
79e53945
JB		 2293 }
2294
5c3b82e2 2295 mutex_lock(&dev->struct_mutex);
265db958 2296 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2297 to_intel_framebuffer(fb)->obj,
919926ae 2298 NULL);
5c3b82e2
CW		 2299 if (ret != 0) {
2300 mutex_unlock(&dev->struct_mutex);
a5071c2f 2301 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2302 return ret;
2303 }
79e53945 2304
94352cf9 2305 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2306 if (ret) {
94352cf9 2307 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2308 mutex_unlock(&dev->struct_mutex);
a5071c2f 2309 DRM_ERROR("failed to update base address\n");
4e6cfefc 2310 return ret;
79e53945 2311 }
3c4fdcfb 2312
94352cf9
DV		 2313 old_fb = crtc->fb;
2314 crtc->fb = fb;
6c4c86f5
DV		 2315 crtc->x = x;
2316 crtc->y = y;
94352cf9 2317
b7f1de28
CW		 2318 if (old_fb) {
2319 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2320 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2321 }
652c393a 2322
6b8e6ed0 2323 intel_update_fbc(dev);
5c3b82e2 2324 mutex_unlock(&dev->struct_mutex);
79e53945 2325
198598d0 2326 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2327
2328 return 0;
79e53945
JB		 2329}
2330
5e84e1a4
ZW		 2331static void intel_fdi_normal_train(struct drm_crtc *crtc)
2332{
2333 struct drm_device *dev = crtc->dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336 int pipe = intel_crtc->pipe;
2337 u32 reg, temp;
2338
2339 /* enable normal train */
2340 reg = FDI_TX_CTL(pipe);
2341 temp = I915_READ(reg);
61e499bf 2342 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2343 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2344 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2345 } else {
2346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2348 }
5e84e1a4
ZW		 2349 I915_WRITE(reg, temp);
2350
2351 reg = FDI_RX_CTL(pipe);
2352 temp = I915_READ(reg);
2353 if (HAS_PCH_CPT(dev)) {
2354 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2355 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2356 } else {
2357 temp &= ~FDI_LINK_TRAIN_NONE;
2358 temp |= FDI_LINK_TRAIN_NONE;
2359 }
2360 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2361
2362 /* wait one idle pattern time */
2363 POSTING_READ(reg);
2364 udelay(1000);
357555c0
JB		 2365
2366 /* IVB wants error correction enabled */
2367 if (IS_IVYBRIDGE(dev))
2368 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2369 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2370}
2371
01a415fd
DV		 2372static void ivb_modeset_global_resources(struct drm_device *dev)
2373{
2374 struct drm_i915_private *dev_priv = dev->dev_private;
2375 struct intel_crtc *pipe_B_crtc =
2376 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2377 struct intel_crtc *pipe_C_crtc =
2378 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2379 uint32_t temp;
2380
2381 /* When everything is off disable fdi C so that we could enable fdi B
2382 * with all lanes. XXX: This misses the case where a pipe is not using
2383 * any pch resources and so doesn't need any fdi lanes. */
2384 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2385 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2386 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2387
2388 temp = I915_READ(SOUTH_CHICKEN1);
2389 temp &= ~FDI_BC_BIFURCATION_SELECT;
2390 DRM_DEBUG_KMS("disabling fdi C rx\n");
2391 I915_WRITE(SOUTH_CHICKEN1, temp);
2392 }
2393}
2394
8db9d77b
ZW		 2395/* The FDI link training functions for ILK/Ibexpeak. */
2396static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2397{
2398 struct drm_device *dev = crtc->dev;
2399 struct drm_i915_private *dev_priv = dev->dev_private;
2400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2401 int pipe = intel_crtc->pipe;
0fc932b8 2402 int plane = intel_crtc->plane;
5eddb70b 2403 u32 reg, temp, tries;
8db9d77b 2404
0fc932b8
JB		 2405 /* FDI needs bits from pipe & plane first */
2406 assert_pipe_enabled(dev_priv, pipe);
2407 assert_plane_enabled(dev_priv, plane);
2408
e1a44743
AJ		 2409 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2410 for train result */
5eddb70b
CW		 2411 reg = FDI_RX_IMR(pipe);
2412 temp = I915_READ(reg);
e1a44743
AJ		 2413 temp &= ~FDI_RX_SYMBOL_LOCK;
2414 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2415 I915_WRITE(reg, temp);
2416 I915_READ(reg);
e1a44743
AJ		 2417 udelay(150);
2418
8db9d77b 2419 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2420 reg = FDI_TX_CTL(pipe);
2421 temp = I915_READ(reg);
77ffb597 2422 temp &= ~(7 << 19);
33d29b14 2423 temp |= (intel_crtc->config.fdi_lanes - 1) << 19;
8db9d77b
ZW		 2424 temp &= ~FDI_LINK_TRAIN_NONE;
2425 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2426 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2427
5eddb70b
CW		 2428 reg = FDI_RX_CTL(pipe);
2429 temp = I915_READ(reg);
8db9d77b
ZW		 2430 temp &= ~FDI_LINK_TRAIN_NONE;
2431 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2432 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2433
2434 POSTING_READ(reg);
8db9d77b
ZW		 2435 udelay(150);
2436
5b2adf89 2437 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2438 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2439 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2440 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2441
5eddb70b 2442 reg = FDI_RX_IIR(pipe);
e1a44743 2443 for (tries = 0; tries < 5; tries++) {
5eddb70b 2444 temp = I915_READ(reg);
8db9d77b
ZW		 2445 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2446
2447 if ((temp & FDI_RX_BIT_LOCK)) {
2448 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2449 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2450 break;
2451 }
8db9d77b 2452 }
e1a44743 2453 if (tries == 5)
5eddb70b 2454 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2455
2456 /* Train 2 */
5eddb70b
CW		 2457 reg = FDI_TX_CTL(pipe);
2458 temp = I915_READ(reg);
8db9d77b
ZW		 2459 temp &= ~FDI_LINK_TRAIN_NONE;
2460 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2461 I915_WRITE(reg, temp);
8db9d77b 2462
5eddb70b
CW		 2463 reg = FDI_RX_CTL(pipe);
2464 temp = I915_READ(reg);
8db9d77b
ZW		 2465 temp &= ~FDI_LINK_TRAIN_NONE;
2466 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2467 I915_WRITE(reg, temp);
8db9d77b 2468
5eddb70b
CW		 2469 POSTING_READ(reg);
2470 udelay(150);
8db9d77b 2471
5eddb70b 2472 reg = FDI_RX_IIR(pipe);
e1a44743 2473 for (tries = 0; tries < 5; tries++) {
5eddb70b 2474 temp = I915_READ(reg);
8db9d77b
ZW		 2475 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2476
2477 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2478 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2479 DRM_DEBUG_KMS("FDI train 2 done.\n");
2480 break;
2481 }
8db9d77b 2482 }
e1a44743 2483 if (tries == 5)
5eddb70b 2484 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2485
2486 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2487
8db9d77b
ZW		 2488}
2489
0206e353 2490static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2491 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2492 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2493 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2494 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2495};
2496
2497/* The FDI link training functions for SNB/Cougarpoint. */
2498static void gen6_fdi_link_train(struct drm_crtc *crtc)
2499{
2500 struct drm_device *dev = crtc->dev;
2501 struct drm_i915_private *dev_priv = dev->dev_private;
2502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2503 int pipe = intel_crtc->pipe;
fa37d39e 2504 u32 reg, temp, i, retry;
8db9d77b 2505
e1a44743
AJ		 2506 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2507 for train result */
5eddb70b
CW		 2508 reg = FDI_RX_IMR(pipe);
2509 temp = I915_READ(reg);
e1a44743
AJ		 2510 temp &= ~FDI_RX_SYMBOL_LOCK;
2511 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2512 I915_WRITE(reg, temp);
2513
2514 POSTING_READ(reg);
e1a44743
AJ		 2515 udelay(150);
2516
8db9d77b 2517 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2518 reg = FDI_TX_CTL(pipe);
2519 temp = I915_READ(reg);
77ffb597 2520 temp &= ~(7 << 19);
33d29b14 2521 temp |= (intel_crtc->config.fdi_lanes - 1) << 19;
8db9d77b
ZW		 2522 temp &= ~FDI_LINK_TRAIN_NONE;
2523 temp |= FDI_LINK_TRAIN_PATTERN_1;
2524 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2525 /* SNB-B */
2526 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2527 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2528
d74cf324
DV		 2529 I915_WRITE(FDI_RX_MISC(pipe),
2530 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2531
5eddb70b
CW		 2532 reg = FDI_RX_CTL(pipe);
2533 temp = I915_READ(reg);
8db9d77b
ZW		 2534 if (HAS_PCH_CPT(dev)) {
2535 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2536 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2537 } else {
2538 temp &= ~FDI_LINK_TRAIN_NONE;
2539 temp |= FDI_LINK_TRAIN_PATTERN_1;
2540 }
5eddb70b
CW		 2541 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2542
2543 POSTING_READ(reg);
8db9d77b
ZW		 2544 udelay(150);
2545
0206e353 2546 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2547 reg = FDI_TX_CTL(pipe);
2548 temp = I915_READ(reg);
8db9d77b
ZW		 2549 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2550 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2551 I915_WRITE(reg, temp);
2552
2553 POSTING_READ(reg);
8db9d77b
ZW		 2554 udelay(500);
2555
fa37d39e
SP		 2556 for (retry = 0; retry < 5; retry++) {
2557 reg = FDI_RX_IIR(pipe);
2558 temp = I915_READ(reg);
2559 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2560 if (temp & FDI_RX_BIT_LOCK) {
2561 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2562 DRM_DEBUG_KMS("FDI train 1 done.\n");
2563 break;
2564 }
2565 udelay(50);
8db9d77b 2566 }
fa37d39e
SP		 2567 if (retry < 5)
2568 break;
8db9d77b
ZW		 2569 }
2570 if (i == 4)
5eddb70b 2571 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2572
2573 /* Train 2 */
5eddb70b
CW		 2574 reg = FDI_TX_CTL(pipe);
2575 temp = I915_READ(reg);
8db9d77b
ZW		 2576 temp &= ~FDI_LINK_TRAIN_NONE;
2577 temp |= FDI_LINK_TRAIN_PATTERN_2;
2578 if (IS_GEN6(dev)) {
2579 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2580 /* SNB-B */
2581 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2582 }
5eddb70b 2583 I915_WRITE(reg, temp);
8db9d77b 2584
5eddb70b
CW		 2585 reg = FDI_RX_CTL(pipe);
2586 temp = I915_READ(reg);
8db9d77b
ZW		 2587 if (HAS_PCH_CPT(dev)) {
2588 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2589 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2590 } else {
2591 temp &= ~FDI_LINK_TRAIN_NONE;
2592 temp |= FDI_LINK_TRAIN_PATTERN_2;
2593 }
5eddb70b
CW		 2594 I915_WRITE(reg, temp);
2595
2596 POSTING_READ(reg);
8db9d77b
ZW		 2597 udelay(150);
2598
0206e353 2599 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2600 reg = FDI_TX_CTL(pipe);
2601 temp = I915_READ(reg);
8db9d77b
ZW		 2602 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2603 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2604 I915_WRITE(reg, temp);
2605
2606 POSTING_READ(reg);
8db9d77b
ZW		 2607 udelay(500);
2608
fa37d39e
SP		 2609 for (retry = 0; retry < 5; retry++) {
2610 reg = FDI_RX_IIR(pipe);
2611 temp = I915_READ(reg);
2612 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2613 if (temp & FDI_RX_SYMBOL_LOCK) {
2614 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2615 DRM_DEBUG_KMS("FDI train 2 done.\n");
2616 break;
2617 }
2618 udelay(50);
8db9d77b 2619 }
fa37d39e
SP		 2620 if (retry < 5)
2621 break;
8db9d77b
ZW		 2622 }
2623 if (i == 4)
5eddb70b 2624 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2625
2626 DRM_DEBUG_KMS("FDI train done.\n");
2627}
2628
357555c0
JB		 2629/* Manual link training for Ivy Bridge A0 parts */
2630static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2631{
2632 struct drm_device *dev = crtc->dev;
2633 struct drm_i915_private *dev_priv = dev->dev_private;
2634 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2635 int pipe = intel_crtc->pipe;
2636 u32 reg, temp, i;
2637
2638 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2639 for train result */
2640 reg = FDI_RX_IMR(pipe);
2641 temp = I915_READ(reg);
2642 temp &= ~FDI_RX_SYMBOL_LOCK;
2643 temp &= ~FDI_RX_BIT_LOCK;
2644 I915_WRITE(reg, temp);
2645
2646 POSTING_READ(reg);
2647 udelay(150);
2648
01a415fd
DV		 2649 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2650 I915_READ(FDI_RX_IIR(pipe)));
2651
357555c0
JB		 2652 /* enable CPU FDI TX and PCH FDI RX */
2653 reg = FDI_TX_CTL(pipe);
2654 temp = I915_READ(reg);
2655 temp &= ~(7 << 19);
33d29b14 2656 temp |= (intel_crtc->config.fdi_lanes - 1) << 19;
357555c0
JB		 2657 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2658 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2659 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2660 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2661 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2662 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2663
d74cf324
DV		 2664 I915_WRITE(FDI_RX_MISC(pipe),
2665 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2666
357555c0
JB		 2667 reg = FDI_RX_CTL(pipe);
2668 temp = I915_READ(reg);
2669 temp &= ~FDI_LINK_TRAIN_AUTO;
2670 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2671 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2672 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2673 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2674
2675 POSTING_READ(reg);
2676 udelay(150);
2677
0206e353 2678 for (i = 0; i < 4; i++) {
357555c0
JB		 2679 reg = FDI_TX_CTL(pipe);
2680 temp = I915_READ(reg);
2681 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2682 temp |= snb_b_fdi_train_param[i];
2683 I915_WRITE(reg, temp);
2684
2685 POSTING_READ(reg);
2686 udelay(500);
2687
2688 reg = FDI_RX_IIR(pipe);
2689 temp = I915_READ(reg);
2690 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2691
2692 if (temp & FDI_RX_BIT_LOCK ||
2693 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2694 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2695 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2696 break;
2697 }
2698 }
2699 if (i == 4)
2700 DRM_ERROR("FDI train 1 fail!\n");
2701
2702 /* Train 2 */
2703 reg = FDI_TX_CTL(pipe);
2704 temp = I915_READ(reg);
2705 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2706 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2707 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2708 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2709 I915_WRITE(reg, temp);
2710
2711 reg = FDI_RX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2714 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2715 I915_WRITE(reg, temp);
2716
2717 POSTING_READ(reg);
2718 udelay(150);
2719
0206e353 2720 for (i = 0; i < 4; i++) {
357555c0
JB		 2721 reg = FDI_TX_CTL(pipe);
2722 temp = I915_READ(reg);
2723 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2724 temp |= snb_b_fdi_train_param[i];
2725 I915_WRITE(reg, temp);
2726
2727 POSTING_READ(reg);
2728 udelay(500);
2729
2730 reg = FDI_RX_IIR(pipe);
2731 temp = I915_READ(reg);
2732 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2733
2734 if (temp & FDI_RX_SYMBOL_LOCK) {
2735 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2736 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2737 break;
2738 }
2739 }
2740 if (i == 4)
2741 DRM_ERROR("FDI train 2 fail!\n");
2742
2743 DRM_DEBUG_KMS("FDI train done.\n");
2744}
2745
88cefb6c 2746static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2747{
88cefb6c 2748 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2749 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2750 int pipe = intel_crtc->pipe;
5eddb70b 2751 u32 reg, temp;
79e53945 2752
c64e311e 2753
c98e9dcf 2754 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2755 reg = FDI_RX_CTL(pipe);
2756 temp = I915_READ(reg);
2757 temp &= ~((0x7 << 19) | (0x7 << 16));
33d29b14 2758 temp |= (intel_crtc->config.fdi_lanes - 1) << 19;
dfd07d72 2759 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2760 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2761
2762 POSTING_READ(reg);
c98e9dcf
JB		 2763 udelay(200);
2764
2765 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2766 temp = I915_READ(reg);
2767 I915_WRITE(reg, temp | FDI_PCDCLK);
2768
2769 POSTING_READ(reg);
c98e9dcf
JB		 2770 udelay(200);
2771
20749730
PZ		 2772 /* Enable CPU FDI TX PLL, always on for Ironlake */
2773 reg = FDI_TX_CTL(pipe);
2774 temp = I915_READ(reg);
2775 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2776 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2777
20749730
PZ		 2778 POSTING_READ(reg);
2779 udelay(100);
6be4a607 2780 }
0e23b99d
JB		 2781}
2782
88cefb6c
DV		 2783static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2784{
2785 struct drm_device *dev = intel_crtc->base.dev;
2786 struct drm_i915_private *dev_priv = dev->dev_private;
2787 int pipe = intel_crtc->pipe;
2788 u32 reg, temp;
2789
2790 /* Switch from PCDclk to Rawclk */
2791 reg = FDI_RX_CTL(pipe);
2792 temp = I915_READ(reg);
2793 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2794
2795 /* Disable CPU FDI TX PLL */
2796 reg = FDI_TX_CTL(pipe);
2797 temp = I915_READ(reg);
2798 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2799
2800 POSTING_READ(reg);
2801 udelay(100);
2802
2803 reg = FDI_RX_CTL(pipe);
2804 temp = I915_READ(reg);
2805 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2806
2807 /* Wait for the clocks to turn off. */
2808 POSTING_READ(reg);
2809 udelay(100);
2810}
2811
0fc932b8
JB		 2812static void ironlake_fdi_disable(struct drm_crtc *crtc)
2813{
2814 struct drm_device *dev = crtc->dev;
2815 struct drm_i915_private *dev_priv = dev->dev_private;
2816 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2817 int pipe = intel_crtc->pipe;
2818 u32 reg, temp;
2819
2820 /* disable CPU FDI tx and PCH FDI rx */
2821 reg = FDI_TX_CTL(pipe);
2822 temp = I915_READ(reg);
2823 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2824 POSTING_READ(reg);
2825
2826 reg = FDI_RX_CTL(pipe);
2827 temp = I915_READ(reg);
2828 temp &= ~(0x7 << 16);
dfd07d72 2829 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2830 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2831
2832 POSTING_READ(reg);
2833 udelay(100);
2834
2835 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2836 if (HAS_PCH_IBX(dev)) {
2837 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2838 }
0fc932b8
JB		 2839
2840 /* still set train pattern 1 */
2841 reg = FDI_TX_CTL(pipe);
2842 temp = I915_READ(reg);
2843 temp &= ~FDI_LINK_TRAIN_NONE;
2844 temp |= FDI_LINK_TRAIN_PATTERN_1;
2845 I915_WRITE(reg, temp);
2846
2847 reg = FDI_RX_CTL(pipe);
2848 temp = I915_READ(reg);
2849 if (HAS_PCH_CPT(dev)) {
2850 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2851 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2852 } else {
2853 temp &= ~FDI_LINK_TRAIN_NONE;
2854 temp |= FDI_LINK_TRAIN_PATTERN_1;
2855 }
2856 /* BPC in FDI rx is consistent with that in PIPECONF */
2857 temp &= ~(0x07 << 16);
dfd07d72 2858 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2859 I915_WRITE(reg, temp);
2860
2861 POSTING_READ(reg);
2862 udelay(100);
2863}
2864
5bb61643
CW		 2865static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2866{
2867 struct drm_device *dev = crtc->dev;
2868 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2869 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2870 unsigned long flags;
2871 bool pending;
2872
10d83730
VS		 2873 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2874 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2875 return false;
2876
2877 spin_lock_irqsave(&dev->event_lock, flags);
2878 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2879 spin_unlock_irqrestore(&dev->event_lock, flags);
2880
2881 return pending;
2882}
2883
e6c3a2a6
CW		 2884static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2885{
0f91128d 2886 struct drm_device *dev = crtc->dev;
5bb61643 2887 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2888
2889 if (crtc->fb == NULL)
2890 return;
2891
2c10d571
DV		 2892 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2893
5bb61643
CW		 2894 wait_event(dev_priv->pending_flip_queue,
2895 !intel_crtc_has_pending_flip(crtc));
2896
0f91128d
CW		 2897 mutex_lock(&dev->struct_mutex);
2898 intel_finish_fb(crtc->fb);
2899 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2900}
2901
e615efe4
ED		 2902/* Program iCLKIP clock to the desired frequency */
2903static void lpt_program_iclkip(struct drm_crtc *crtc)
2904{
2905 struct drm_device *dev = crtc->dev;
2906 struct drm_i915_private *dev_priv = dev->dev_private;
2907 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2908 u32 temp;
2909
09153000
DV		 2910 mutex_lock(&dev_priv->dpio_lock);
2911
e615efe4
ED		 2912 /* It is necessary to ungate the pixclk gate prior to programming
2913 * the divisors, and gate it back when it is done.
2914 */
2915 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2916
2917 /* Disable SSCCTL */
2918 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2919 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2920 SBI_SSCCTL_DISABLE,
2921 SBI_ICLK);
e615efe4
ED		 2922
2923 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2924 if (crtc->mode.clock == 20000) {
2925 auxdiv = 1;
2926 divsel = 0x41;
2927 phaseinc = 0x20;
2928 } else {
2929 /* The iCLK virtual clock root frequency is in MHz,
2930 * but the crtc->mode.clock in in KHz. To get the divisors,
2931 * it is necessary to divide one by another, so we
2932 * convert the virtual clock precision to KHz here for higher
2933 * precision.
2934 */
2935 u32 iclk_virtual_root_freq = 172800 * 1000;
2936 u32 iclk_pi_range = 64;
2937 u32 desired_divisor, msb_divisor_value, pi_value;
2938
2939 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2940 msb_divisor_value = desired_divisor / iclk_pi_range;
2941 pi_value = desired_divisor % iclk_pi_range;
2942
2943 auxdiv = 0;
2944 divsel = msb_divisor_value - 2;
2945 phaseinc = pi_value;
2946 }
2947
2948 /* This should not happen with any sane values */
2949 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2950 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2951 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2952 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2953
2954 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2955 crtc->mode.clock,
2956 auxdiv,
2957 divsel,
2958 phasedir,
2959 phaseinc);
2960
2961 /* Program SSCDIVINTPHASE6 */
988d6ee8 2962 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2963 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2964 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2965 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2966 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2967 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2968 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2969 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2970
2971 /* Program SSCAUXDIV */
988d6ee8 2972 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2973 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2974 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2975 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2976
2977 /* Enable modulator and associated divider */
988d6ee8 2978 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2979 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2980 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2981
2982 /* Wait for initialization time */
2983 udelay(24);
2984
2985 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2986
2987 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2988}
2989
f67a559d
JB		 2990/*
2991 * Enable PCH resources required for PCH ports:
2992 * - PCH PLLs
2993 * - FDI training & RX/TX
2994 * - update transcoder timings
2995 * - DP transcoding bits
2996 * - transcoder
2997 */
2998static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2999{
3000 struct drm_device *dev = crtc->dev;
3001 struct drm_i915_private *dev_priv = dev->dev_private;
3002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3003 int pipe = intel_crtc->pipe;
ee7b9f93 3004 u32 reg, temp;
2c07245f 3005
e7e164db
CW		 3006 assert_transcoder_disabled(dev_priv, pipe);
3007
cd986abb
DV		 3008 /* Write the TU size bits before fdi link training, so that error
3009 * detection works. */
3010 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3011 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3012
c98e9dcf 3013 /* For PCH output, training FDI link */
674cf967 3014 dev_priv->display.fdi_link_train(crtc);
2c07245f 3015
572deb37
DV		 3016 /* XXX: pch pll's can be enabled any time before we enable the PCH
3017 * transcoder, and we actually should do this to not upset any PCH
3018 * transcoder that already use the clock when we share it.
3019 *
3020 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3021 * unconditionally resets the pll - we need that to have the right LVDS
3022 * enable sequence. */
b6b4e185 3023 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3024
303b81e0 3025 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3026 u32 sel;
4b645f14 3027
c98e9dcf 3028 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3029 switch (pipe) {
3030 default:
3031 case 0:
3032 temp |= TRANSA_DPLL_ENABLE;
3033 sel = TRANSA_DPLLB_SEL;
3034 break;
3035 case 1:
3036 temp |= TRANSB_DPLL_ENABLE;
3037 sel = TRANSB_DPLLB_SEL;
3038 break;
3039 case 2:
3040 temp |= TRANSC_DPLL_ENABLE;
3041 sel = TRANSC_DPLLB_SEL;
3042 break;
d64311ab 3043 }
ee7b9f93
JB		 3044 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3045 temp |= sel;
3046 else
3047 temp &= ~sel;
c98e9dcf 3048 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3049 }
5eddb70b 3050
d9b6cb56
JB		 3051 /* set transcoder timing, panel must allow it */
3052 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3053 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3054 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3055 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3056
5eddb70b
CW		 3057 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3058 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3059 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3060 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3061
303b81e0 3062 intel_fdi_normal_train(crtc);
5e84e1a4 3063
c98e9dcf
JB		 3064 /* For PCH DP, enable TRANS_DP_CTL */
3065 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3066 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3067 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3068 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3069 reg = TRANS_DP_CTL(pipe);
3070 temp = I915_READ(reg);
3071 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3072 TRANS_DP_SYNC_MASK |
3073 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3074 temp |= (TRANS_DP_OUTPUT_ENABLE |
3075 TRANS_DP_ENH_FRAMING);
9325c9f0 3076 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3077
3078 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3079 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3080 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3081 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3082
3083 switch (intel_trans_dp_port_sel(crtc)) {
3084 case PCH_DP_B:
5eddb70b 3085 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3086 break;
3087 case PCH_DP_C:
5eddb70b 3088 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3089 break;
3090 case PCH_DP_D:
5eddb70b 3091 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3092 break;
3093 default:
e95d41e1 3094 BUG();
32f9d658 3095 }
2c07245f 3096
5eddb70b 3097 I915_WRITE(reg, temp);
6be4a607 3098 }
b52eb4dc 3099
b8a4f404 3100 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3101}
3102
1507e5bd
PZ		 3103static void lpt_pch_enable(struct drm_crtc *crtc)
3104{
3105 struct drm_device *dev = crtc->dev;
3106 struct drm_i915_private *dev_priv = dev->dev_private;
3107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3108 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3109
daed2dbb 3110 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3111
8c52b5e8 3112 lpt_program_iclkip(crtc);
1507e5bd 3113
0540e488 3114 /* Set transcoder timing. */
daed2dbb
PZ		 3115 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3116 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3117 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3118
daed2dbb
PZ		 3119 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3120 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3121 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3122 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3123
937bb610 3124 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3125}
3126
ee7b9f93
JB		 3127static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3128{
3129 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3130
3131 if (pll == NULL)
3132 return;
3133
3134 if (pll->refcount == 0) {
3135 WARN(1, "bad PCH PLL refcount\n");
3136 return;
3137 }
3138
3139 --pll->refcount;
3140 intel_crtc->pch_pll = NULL;
3141}
3142
3143static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3144{
3145 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3146 struct intel_pch_pll *pll;
3147 int i;
3148
3149 pll = intel_crtc->pch_pll;
3150 if (pll) {
3151 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3152 intel_crtc->base.base.id, pll->pll_reg);
3153 goto prepare;
3154 }
3155
98b6bd99
DV		 3156 if (HAS_PCH_IBX(dev_priv->dev)) {
3157 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3158 i = intel_crtc->pipe;
3159 pll = &dev_priv->pch_plls[i];
3160
3161 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3162 intel_crtc->base.base.id, pll->pll_reg);
3163
3164 goto found;
3165 }
3166
ee7b9f93
JB		 3167 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3168 pll = &dev_priv->pch_plls[i];
3169
3170 /* Only want to check enabled timings first */
3171 if (pll->refcount == 0)
3172 continue;
3173
3174 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3175 fp == I915_READ(pll->fp0_reg)) {
3176 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3177 intel_crtc->base.base.id,
3178 pll->pll_reg, pll->refcount, pll->active);
3179
3180 goto found;
3181 }
3182 }
3183
3184 /* Ok no matching timings, maybe there's a free one? */
3185 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3186 pll = &dev_priv->pch_plls[i];
3187 if (pll->refcount == 0) {
3188 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3189 intel_crtc->base.base.id, pll->pll_reg);
3190 goto found;
3191 }
3192 }
3193
3194 return NULL;
3195
3196found:
3197 intel_crtc->pch_pll = pll;
3198 pll->refcount++;
84f44ce7 3199 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
ee7b9f93
JB		 3200prepare: /* separate function? */
3201 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3202
e04c7350
CW		 3203 /* Wait for the clocks to stabilize before rewriting the regs */
3204 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3205 POSTING_READ(pll->pll_reg);
3206 udelay(150);
e04c7350
CW		 3207
3208 I915_WRITE(pll->fp0_reg, fp);
3209 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3210 pll->on = false;
3211 return pll;
3212}
3213
d4270e57
JB		 3214void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3215{
3216 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3217 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3218 u32 temp;
3219
3220 temp = I915_READ(dslreg);
3221 udelay(500);
3222 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3223 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3224 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3225 }
3226}
3227
b074cec8
JB		 3228static void ironlake_pfit_enable(struct intel_crtc *crtc)
3229{
3230 struct drm_device *dev = crtc->base.dev;
3231 struct drm_i915_private *dev_priv = dev->dev_private;
3232 int pipe = crtc->pipe;
3233
3234 if (crtc->config.pch_pfit.size &&
3235 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) {
3236 /* Force use of hard-coded filter coefficients
3237 * as some pre-programmed values are broken,
3238 * e.g. x201.
3239 */
3240 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3241 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3242 PF_PIPE_SEL_IVB(pipe));
3243 else
3244 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3245 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3246 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3247 }
3248}
3249
f67a559d
JB		 3250static void ironlake_crtc_enable(struct drm_crtc *crtc)
3251{
3252 struct drm_device *dev = crtc->dev;
3253 struct drm_i915_private *dev_priv = dev->dev_private;
3254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3255 struct intel_encoder *encoder;
f67a559d
JB		 3256 int pipe = intel_crtc->pipe;
3257 int plane = intel_crtc->plane;
3258 u32 temp;
f67a559d 3259
08a48469
DV		 3260 WARN_ON(!crtc->enabled);
3261
f67a559d
JB		 3262 if (intel_crtc->active)
3263 return;
3264
3265 intel_crtc->active = true;
8664281b
PZ		 3266
3267 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3268 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3269
f67a559d
JB		 3270 intel_update_watermarks(dev);
3271
3272 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3273 temp = I915_READ(PCH_LVDS);
3274 if ((temp & LVDS_PORT_EN) == 0)
3275 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3276 }
3277
f67a559d 3278
5bfe2ac0 3279 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3280 /* Note: FDI PLL enabling _must_ be done before we enable the
3281 * cpu pipes, hence this is separate from all the other fdi/pch
3282 * enabling. */
88cefb6c 3283 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3284 } else {
3285 assert_fdi_tx_disabled(dev_priv, pipe);
3286 assert_fdi_rx_disabled(dev_priv, pipe);
3287 }
f67a559d 3288
bf49ec8c
DV		 3289 for_each_encoder_on_crtc(dev, crtc, encoder)
3290 if (encoder->pre_enable)
3291 encoder->pre_enable(encoder);
f67a559d
JB		 3292
3293 /* Enable panel fitting for LVDS */
b074cec8 3294 ironlake_pfit_enable(intel_crtc);
f67a559d 3295
9c54c0dd
JB		 3296 /*
3297 * On ILK+ LUT must be loaded before the pipe is running but with
3298 * clocks enabled
3299 */
3300 intel_crtc_load_lut(crtc);
3301
5bfe2ac0
DV		 3302 intel_enable_pipe(dev_priv, pipe,
3303 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3304 intel_enable_plane(dev_priv, plane, pipe);
3305
5bfe2ac0 3306 if (intel_crtc->config.has_pch_encoder)
f67a559d 3307 ironlake_pch_enable(crtc);
c98e9dcf 3308
d1ebd816 3309 mutex_lock(&dev->struct_mutex);
bed4a673 3310 intel_update_fbc(dev);
d1ebd816
BW		 3311 mutex_unlock(&dev->struct_mutex);
3312
6b383a7f 3313 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3314
fa5c73b1
DV		 3315 for_each_encoder_on_crtc(dev, crtc, encoder)
3316 encoder->enable(encoder);
61b77ddd
DV		 3317
3318 if (HAS_PCH_CPT(dev))
3319 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3320
3321 /*
3322 * There seems to be a race in PCH platform hw (at least on some
3323 * outputs) where an enabled pipe still completes any pageflip right
3324 * away (as if the pipe is off) instead of waiting for vblank. As soon
3325 * as the first vblank happend, everything works as expected. Hence just
3326 * wait for one vblank before returning to avoid strange things
3327 * happening.
3328 */
3329 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3330}
3331
4f771f10
PZ		 3332static void haswell_crtc_enable(struct drm_crtc *crtc)
3333{
3334 struct drm_device *dev = crtc->dev;
3335 struct drm_i915_private *dev_priv = dev->dev_private;
3336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3337 struct intel_encoder *encoder;
3338 int pipe = intel_crtc->pipe;
3339 int plane = intel_crtc->plane;
4f771f10
PZ		 3340
3341 WARN_ON(!crtc->enabled);
3342
3343 if (intel_crtc->active)
3344 return;
3345
3346 intel_crtc->active = true;
8664281b
PZ		 3347
3348 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3349 if (intel_crtc->config.has_pch_encoder)
3350 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3351
4f771f10
PZ		 3352 intel_update_watermarks(dev);
3353
5bfe2ac0 3354 if (intel_crtc->config.has_pch_encoder)
04945641 3355 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3356
3357 for_each_encoder_on_crtc(dev, crtc, encoder)
3358 if (encoder->pre_enable)
3359 encoder->pre_enable(encoder);
3360
1f544388 3361 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3362
1f544388 3363 /* Enable panel fitting for eDP */
b074cec8 3364 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3365
3366 /*
3367 * On ILK+ LUT must be loaded before the pipe is running but with
3368 * clocks enabled
3369 */
3370 intel_crtc_load_lut(crtc);
3371
1f544388 3372 intel_ddi_set_pipe_settings(crtc);
8228c251 3373 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3374
5bfe2ac0
DV		 3375 intel_enable_pipe(dev_priv, pipe,
3376 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3377 intel_enable_plane(dev_priv, plane, pipe);
3378
5bfe2ac0 3379 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3380 lpt_pch_enable(crtc);
4f771f10
PZ		 3381
3382 mutex_lock(&dev->struct_mutex);
3383 intel_update_fbc(dev);
3384 mutex_unlock(&dev->struct_mutex);
3385
3386 intel_crtc_update_cursor(crtc, true);
3387
3388 for_each_encoder_on_crtc(dev, crtc, encoder)
3389 encoder->enable(encoder);
3390
4f771f10
PZ		 3391 /*
3392 * There seems to be a race in PCH platform hw (at least on some
3393 * outputs) where an enabled pipe still completes any pageflip right
3394 * away (as if the pipe is off) instead of waiting for vblank. As soon
3395 * as the first vblank happend, everything works as expected. Hence just
3396 * wait for one vblank before returning to avoid strange things
3397 * happening.
3398 */
3399 intel_wait_for_vblank(dev, intel_crtc->pipe);
3400}
3401
6be4a607
JB		 3402static void ironlake_crtc_disable(struct drm_crtc *crtc)
3403{
3404 struct drm_device *dev = crtc->dev;
3405 struct drm_i915_private *dev_priv = dev->dev_private;
3406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3407 struct intel_encoder *encoder;
6be4a607
JB		 3408 int pipe = intel_crtc->pipe;
3409 int plane = intel_crtc->plane;
5eddb70b 3410 u32 reg, temp;
b52eb4dc 3411
ef9c3aee 3412
f7abfe8b
CW		 3413 if (!intel_crtc->active)
3414 return;
3415
ea9d758d
DV		 3416 for_each_encoder_on_crtc(dev, crtc, encoder)
3417 encoder->disable(encoder);
3418
e6c3a2a6 3419 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3420 drm_vblank_off(dev, pipe);
6b383a7f 3421 intel_crtc_update_cursor(crtc, false);
5eddb70b 3422
b24e7179 3423 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3424
973d04f9
CW		 3425 if (dev_priv->cfb_plane == plane)
3426 intel_disable_fbc(dev);
2c07245f 3427
8664281b 3428 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
b24e7179 3429 intel_disable_pipe(dev_priv, pipe);
32f9d658 3430
6be4a607 3431 /* Disable PF */
9db4a9c7
JB		 3432 I915_WRITE(PF_CTL(pipe), 0);
3433 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3434
bf49ec8c
DV		 3435 for_each_encoder_on_crtc(dev, crtc, encoder)
3436 if (encoder->post_disable)
3437 encoder->post_disable(encoder);
2c07245f 3438
0fc932b8 3439 ironlake_fdi_disable(crtc);
249c0e64 3440
b8a4f404 3441 ironlake_disable_pch_transcoder(dev_priv, pipe);
8664281b 3442 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3443
6be4a607
JB		 3444 if (HAS_PCH_CPT(dev)) {
3445 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3446 reg = TRANS_DP_CTL(pipe);
3447 temp = I915_READ(reg);
3448 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3449 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3450 I915_WRITE(reg, temp);
6be4a607
JB		 3451
3452 /* disable DPLL_SEL */
3453 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3454 switch (pipe) {
3455 case 0:
d64311ab 3456 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3457 break;
3458 case 1:
6be4a607 3459 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3460 break;
3461 case 2:
4b645f14 3462 /* C shares PLL A or B */
d64311ab 3463 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3464 break;
3465 default:
3466 BUG(); /* wtf */
3467 }
6be4a607 3468 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3469 }
e3421a18 3470
6be4a607 3471 /* disable PCH DPLL */
ee7b9f93 3472 intel_disable_pch_pll(intel_crtc);
8db9d77b 3473
88cefb6c 3474 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3475
f7abfe8b 3476 intel_crtc->active = false;
6b383a7f 3477 intel_update_watermarks(dev);
d1ebd816
BW		 3478
3479 mutex_lock(&dev->struct_mutex);
6b383a7f 3480 intel_update_fbc(dev);
d1ebd816 3481 mutex_unlock(&dev->struct_mutex);
6be4a607 3482}
1b3c7a47 3483
4f771f10 3484static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3485{
4f771f10
PZ		 3486 struct drm_device *dev = crtc->dev;
3487 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3489 struct intel_encoder *encoder;
3490 int pipe = intel_crtc->pipe;
3491 int plane = intel_crtc->plane;
3b117c8f 3492 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3493
4f771f10
PZ		 3494 if (!intel_crtc->active)
3495 return;
3496
3497 for_each_encoder_on_crtc(dev, crtc, encoder)
3498 encoder->disable(encoder);
3499
3500 intel_crtc_wait_for_pending_flips(crtc);
3501 drm_vblank_off(dev, pipe);
3502 intel_crtc_update_cursor(crtc, false);
3503
3504 intel_disable_plane(dev_priv, plane, pipe);
3505
3506 if (dev_priv->cfb_plane == plane)
3507 intel_disable_fbc(dev);
3508
8664281b
PZ		 3509 if (intel_crtc->config.has_pch_encoder)
3510 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3511 intel_disable_pipe(dev_priv, pipe);
3512
ad80a810 3513 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3514
f7708f78
PZ		 3515 /* XXX: Once we have proper panel fitter state tracking implemented with
3516 * hardware state read/check support we should switch to only disable
3517 * the panel fitter when we know it's used. */
3518 if (intel_using_power_well(dev)) {
3519 I915_WRITE(PF_CTL(pipe), 0);
3520 I915_WRITE(PF_WIN_SZ(pipe), 0);
3521 }
4f771f10 3522
1f544388 3523 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3524
3525 for_each_encoder_on_crtc(dev, crtc, encoder)
3526 if (encoder->post_disable)
3527 encoder->post_disable(encoder);
3528
88adfff1 3529 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3530 lpt_disable_pch_transcoder(dev_priv);
8664281b 3531 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3532 intel_ddi_fdi_disable(crtc);
83616634 3533 }
4f771f10
PZ		 3534
3535 intel_crtc->active = false;
3536 intel_update_watermarks(dev);
3537
3538 mutex_lock(&dev->struct_mutex);
3539 intel_update_fbc(dev);
3540 mutex_unlock(&dev->struct_mutex);
3541}
3542
ee7b9f93
JB		 3543static void ironlake_crtc_off(struct drm_crtc *crtc)
3544{
3545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3546 intel_put_pch_pll(intel_crtc);
3547}
3548
6441ab5f
PZ		 3549static void haswell_crtc_off(struct drm_crtc *crtc)
3550{
a5c961d1
PZ		 3551 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3552
3553 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3554 * start using it. */
3b117c8f 3555 intel_crtc->config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3556
6441ab5f
PZ		 3557 intel_ddi_put_crtc_pll(crtc);
3558}
3559
02e792fb
DV		 3560static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3561{
02e792fb 3562 if (!enable && intel_crtc->overlay) {
23f09ce3 3563 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3564 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3565
23f09ce3 3566 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3567 dev_priv->mm.interruptible = false;
3568 (void) intel_overlay_switch_off(intel_crtc->overlay);
3569 dev_priv->mm.interruptible = true;
23f09ce3 3570 mutex_unlock(&dev->struct_mutex);
02e792fb 3571 }
02e792fb 3572
5dcdbcb0
CW		 3573 /* Let userspace switch the overlay on again. In most cases userspace
3574 * has to recompute where to put it anyway.
3575 */
02e792fb
DV		 3576}
3577
61bc95c1
EE		 3578/**
3579 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3580 * cursor plane briefly if not already running after enabling the display
3581 * plane.
3582 * This workaround avoids occasional blank screens when self refresh is
3583 * enabled.
3584 */
3585static void
3586g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3587{
3588 u32 cntl = I915_READ(CURCNTR(pipe));
3589
3590 if ((cntl & CURSOR_MODE) == 0) {
3591 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3592
3593 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3594 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3595 intel_wait_for_vblank(dev_priv->dev, pipe);
3596 I915_WRITE(CURCNTR(pipe), cntl);
3597 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3598 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3599 }
3600}
3601
2dd24552
JB		 3602static void i9xx_pfit_enable(struct intel_crtc *crtc)
3603{
3604 struct drm_device *dev = crtc->base.dev;
3605 struct drm_i915_private *dev_priv = dev->dev_private;
3606 struct intel_crtc_config *pipe_config = &crtc->config;
3607
3608 if (!(intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
3609 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)))
3610 return;
3611
3612 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3613 assert_pipe_disabled(dev_priv, crtc->pipe);
3614
3615 /*
3616 * Enable automatic panel scaling so that non-native modes
3617 * fill the screen. The panel fitter should only be
3618 * adjusted whilst the pipe is disabled, according to
3619 * register description and PRM.
3620 */
3621 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
b074cec8
JB		 3622 pipe_config->gmch_pfit.control,
3623 pipe_config->gmch_pfit.pgm_ratios);
2dd24552 3624
b074cec8
JB		 3625 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3626 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
2dd24552
JB		 3627}
3628
89b667f8
JB		 3629static void valleyview_crtc_enable(struct drm_crtc *crtc)
3630{
3631 struct drm_device *dev = crtc->dev;
3632 struct drm_i915_private *dev_priv = dev->dev_private;
3633 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3634 struct intel_encoder *encoder;
3635 int pipe = intel_crtc->pipe;
3636 int plane = intel_crtc->plane;
3637
3638 WARN_ON(!crtc->enabled);
3639
3640 if (intel_crtc->active)
3641 return;
3642
3643 intel_crtc->active = true;
3644 intel_update_watermarks(dev);
3645
3646 mutex_lock(&dev_priv->dpio_lock);
3647
3648 for_each_encoder_on_crtc(dev, crtc, encoder)
3649 if (encoder->pre_pll_enable)
3650 encoder->pre_pll_enable(encoder);
3651
3652 intel_enable_pll(dev_priv, pipe);
3653
3654 for_each_encoder_on_crtc(dev, crtc, encoder)
3655 if (encoder->pre_enable)
3656 encoder->pre_enable(encoder);
3657
3658 /* VLV wants encoder enabling _before_ the pipe is up. */
3659 for_each_encoder_on_crtc(dev, crtc, encoder)
3660 encoder->enable(encoder);
3661
2dd24552
JB		 3662 /* Enable panel fitting for eDP */
3663 i9xx_pfit_enable(intel_crtc);
3664
89b667f8
JB		 3665 intel_enable_pipe(dev_priv, pipe, false);
3666 intel_enable_plane(dev_priv, plane, pipe);
3667
3668 intel_crtc_load_lut(crtc);
3669 intel_update_fbc(dev);
3670
3671 /* Give the overlay scaler a chance to enable if it's on this pipe */
3672 intel_crtc_dpms_overlay(intel_crtc, true);
3673 intel_crtc_update_cursor(crtc, true);
3674
3675 mutex_unlock(&dev_priv->dpio_lock);
3676}
3677
0b8765c6 3678static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3679{
3680 struct drm_device *dev = crtc->dev;
79e53945
JB		 3681 struct drm_i915_private *dev_priv = dev->dev_private;
3682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3683 struct intel_encoder *encoder;
79e53945 3684 int pipe = intel_crtc->pipe;
80824003 3685 int plane = intel_crtc->plane;
79e53945 3686
08a48469
DV		 3687 WARN_ON(!crtc->enabled);
3688
f7abfe8b
CW		 3689 if (intel_crtc->active)
3690 return;
3691
3692 intel_crtc->active = true;
6b383a7f
CW		 3693 intel_update_watermarks(dev);
3694
63d7bbe9 3695 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3696
3697 for_each_encoder_on_crtc(dev, crtc, encoder)
3698 if (encoder->pre_enable)
3699 encoder->pre_enable(encoder);
3700
2dd24552
JB		 3701 /* Enable panel fitting for LVDS */
3702 i9xx_pfit_enable(intel_crtc);
3703
040484af 3704 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3705 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3706 if (IS_G4X(dev))
3707 g4x_fixup_plane(dev_priv, pipe);
79e53945 3708
0b8765c6 3709 intel_crtc_load_lut(crtc);
bed4a673 3710 intel_update_fbc(dev);
79e53945 3711
0b8765c6
JB		 3712 /* Give the overlay scaler a chance to enable if it's on this pipe */
3713 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3714 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3715
fa5c73b1
DV		 3716 for_each_encoder_on_crtc(dev, crtc, encoder)
3717 encoder->enable(encoder);
0b8765c6 3718}
79e53945 3719
87476d63
DV		 3720static void i9xx_pfit_disable(struct intel_crtc *crtc)
3721{
3722 struct drm_device *dev = crtc->base.dev;
3723 struct drm_i915_private *dev_priv = dev->dev_private;
3724 enum pipe pipe;
3725 uint32_t pctl = I915_READ(PFIT_CONTROL);
3726
3727 assert_pipe_disabled(dev_priv, crtc->pipe);
3728
3729 if (INTEL_INFO(dev)->gen >= 4)
3730 pipe = (pctl & PFIT_PIPE_MASK) >> PFIT_PIPE_SHIFT;
3731 else
3732 pipe = PIPE_B;
3733
3734 if (pipe == crtc->pipe) {
3735 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", pctl);
3736 I915_WRITE(PFIT_CONTROL, 0);
3737 }
3738}
3739
0b8765c6
JB		 3740static void i9xx_crtc_disable(struct drm_crtc *crtc)
3741{
3742 struct drm_device *dev = crtc->dev;
3743 struct drm_i915_private *dev_priv = dev->dev_private;
3744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3745 struct intel_encoder *encoder;
0b8765c6
JB		 3746 int pipe = intel_crtc->pipe;
3747 int plane = intel_crtc->plane;
ef9c3aee 3748
f7abfe8b
CW		 3749 if (!intel_crtc->active)
3750 return;
3751
ea9d758d
DV		 3752 for_each_encoder_on_crtc(dev, crtc, encoder)
3753 encoder->disable(encoder);
3754
0b8765c6 3755 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3756 intel_crtc_wait_for_pending_flips(crtc);
3757 drm_vblank_off(dev, pipe);
0b8765c6 3758 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3759 intel_crtc_update_cursor(crtc, false);
0b8765c6 3760
973d04f9
CW		 3761 if (dev_priv->cfb_plane == plane)
3762 intel_disable_fbc(dev);
79e53945 3763
b24e7179 3764 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3765 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3766
87476d63 3767 i9xx_pfit_disable(intel_crtc);
24a1f16d 3768
89b667f8
JB		 3769 for_each_encoder_on_crtc(dev, crtc, encoder)
3770 if (encoder->post_disable)
3771 encoder->post_disable(encoder);
3772
63d7bbe9 3773 intel_disable_pll(dev_priv, pipe);
0b8765c6 3774
f7abfe8b 3775 intel_crtc->active = false;
6b383a7f
CW		 3776 intel_update_fbc(dev);
3777 intel_update_watermarks(dev);
0b8765c6
JB		 3778}
3779
ee7b9f93
JB		 3780static void i9xx_crtc_off(struct drm_crtc *crtc)
3781{
3782}
3783
976f8a20
DV		 3784static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3785 bool enabled)
2c07245f
ZW		 3786{
3787 struct drm_device *dev = crtc->dev;
3788 struct drm_i915_master_private *master_priv;
3789 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3790 int pipe = intel_crtc->pipe;
79e53945
JB		 3791
3792 if (!dev->primary->master)
3793 return;
3794
3795 master_priv = dev->primary->master->driver_priv;
3796 if (!master_priv->sarea_priv)
3797 return;
3798
79e53945
JB		 3799 switch (pipe) {
3800 case 0:
3801 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3802 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3803 break;
3804 case 1:
3805 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3806 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3807 break;
3808 default:
9db4a9c7 3809 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3810 break;
3811 }
79e53945
JB		 3812}
3813
976f8a20
DV		 3814/**
3815 * Sets the power management mode of the pipe and plane.
3816 */
3817void intel_crtc_update_dpms(struct drm_crtc *crtc)
3818{
3819 struct drm_device *dev = crtc->dev;
3820 struct drm_i915_private *dev_priv = dev->dev_private;
3821 struct intel_encoder *intel_encoder;
3822 bool enable = false;
3823
3824 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3825 enable |= intel_encoder->connectors_active;
3826
3827 if (enable)
3828 dev_priv->display.crtc_enable(crtc);
3829 else
3830 dev_priv->display.crtc_disable(crtc);
3831
3832 intel_crtc_update_sarea(crtc, enable);
3833}
3834
cdd59983
CW		 3835static void intel_crtc_disable(struct drm_crtc *crtc)
3836{
cdd59983 3837 struct drm_device *dev = crtc->dev;
976f8a20 3838 struct drm_connector *connector;
ee7b9f93 3839 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3840 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3841
976f8a20
DV		 3842 /* crtc should still be enabled when we disable it. */
3843 WARN_ON(!crtc->enabled);
3844
7b9f35a6 3845 intel_crtc->eld_vld = false;
976f8a20
DV		 3846 dev_priv->display.crtc_disable(crtc);
3847 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3848 dev_priv->display.off(crtc);
3849
931872fc
CW		 3850 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3851 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3852
3853 if (crtc->fb) {
3854 mutex_lock(&dev->struct_mutex);
1690e1eb 3855 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3856 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3857 crtc->fb = NULL;
3858 }
3859
3860 /* Update computed state. */
3861 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3862 if (!connector->encoder || !connector->encoder->crtc)
3863 continue;
3864
3865 if (connector->encoder->crtc != crtc)
3866 continue;
3867
3868 connector->dpms = DRM_MODE_DPMS_OFF;
3869 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3870 }
3871}
3872
a261b246 3873void intel_modeset_disable(struct drm_device *dev)
79e53945 3874{
a261b246
DV		 3875 struct drm_crtc *crtc;
3876
3877 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3878 if (crtc->enabled)
3879 intel_crtc_disable(crtc);
3880 }
79e53945
JB		 3881}
3882
ea5b213a 3883void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3884{
4ef69c7a 3885 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3886
ea5b213a
CW		 3887 drm_encoder_cleanup(encoder);
3888 kfree(intel_encoder);
7e7d76c3
JB		 3889}
3890
5ab432ef
DV		 3891/* Simple dpms helper for encodres with just one connector, no cloning and only
3892 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3893 * state of the entire output pipe. */
3894void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3895{
5ab432ef
DV		 3896 if (mode == DRM_MODE_DPMS_ON) {
3897 encoder->connectors_active = true;
3898
b2cabb0e 3899 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3900 } else {
3901 encoder->connectors_active = false;
3902
b2cabb0e 3903 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3904 }
79e53945
JB		 3905}
3906
0a91ca29
DV		 3907/* Cross check the actual hw state with our own modeset state tracking (and it's
3908 * internal consistency). */
b980514c 3909static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3910{
0a91ca29
DV		 3911 if (connector->get_hw_state(connector)) {
3912 struct intel_encoder *encoder = connector->encoder;
3913 struct drm_crtc *crtc;
3914 bool encoder_enabled;
3915 enum pipe pipe;
3916
3917 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3918 connector->base.base.id,
3919 drm_get_connector_name(&connector->base));
3920
3921 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3922 "wrong connector dpms state\n");
3923 WARN(connector->base.encoder != &encoder->base,
3924 "active connector not linked to encoder\n");
3925 WARN(!encoder->connectors_active,
3926 "encoder->connectors_active not set\n");
3927
3928 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3929 WARN(!encoder_enabled, "encoder not enabled\n");
3930 if (WARN_ON(!encoder->base.crtc))
3931 return;
3932
3933 crtc = encoder->base.crtc;
3934
3935 WARN(!crtc->enabled, "crtc not enabled\n");
3936 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3937 WARN(pipe != to_intel_crtc(crtc)->pipe,
3938 "encoder active on the wrong pipe\n");
3939 }
79e53945
JB		 3940}
3941
5ab432ef
DV		 3942/* Even simpler default implementation, if there's really no special case to
3943 * consider. */
3944void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3945{
5ab432ef 3946 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3947
5ab432ef
DV		 3948 /* All the simple cases only support two dpms states. */
3949 if (mode != DRM_MODE_DPMS_ON)
3950 mode = DRM_MODE_DPMS_OFF;
d4270e57 3951
5ab432ef
DV		 3952 if (mode == connector->dpms)
3953 return;
3954
3955 connector->dpms = mode;
3956
3957 /* Only need to change hw state when actually enabled */
3958 if (encoder->base.crtc)
3959 intel_encoder_dpms(encoder, mode);
3960 else
8af6cf88 3961 WARN_ON(encoder->connectors_active != false);
0a91ca29 3962
b980514c 3963 intel_modeset_check_state(connector->dev);
79e53945
JB		 3964}
3965
f0947c37
DV		 3966/* Simple connector->get_hw_state implementation for encoders that support only
3967 * one connector and no cloning and hence the encoder state determines the state
3968 * of the connector. */
3969bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3970{
24929352 3971 enum pipe pipe = 0;
f0947c37 3972 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3973
f0947c37 3974 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3975}
3976
b8cecdf5
DV		 3977static bool intel_crtc_compute_config(struct drm_crtc *crtc,
3978 struct intel_crtc_config *pipe_config)
79e53945 3979{
2c07245f 3980 struct drm_device *dev = crtc->dev;
b8cecdf5 3981 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 3982
bad720ff 3983 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3984 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 3985 if (pipe_config->requested_mode.clock * 3
3986 > IRONLAKE_FDI_FREQ * 4)
2377b741 3987 return false;
2c07245f 3988 }
89749350 3989
f9bef081
DV		 3990 /* All interlaced capable intel hw wants timings in frames. Note though
3991 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3992 * timings, so we need to be careful not to clobber these.*/
7ae89233 3993 if (!pipe_config->timings_set)
f9bef081 3994 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3995
44f46b42
CW		 3996 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3997 * with a hsync front porch of 0.
3998 */
3999 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4000 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
4001 return false;
4002
bd080ee5 4003 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4004 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4005 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4006 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4007 * for lvds. */
4008 pipe_config->pipe_bpp = 8*3;
4009 }
4010
79e53945
JB		 4011 return true;
4012}
4013
25eb05fc
JB		 4014static int valleyview_get_display_clock_speed(struct drm_device *dev)
4015{
4016 return 400000; /* FIXME */
4017}
4018
e70236a8
JB		 4019static int i945_get_display_clock_speed(struct drm_device *dev)
4020{
4021 return 400000;
4022}
79e53945 4023
e70236a8 4024static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4025{
e70236a8
JB		 4026 return 333000;
4027}
79e53945 4028
e70236a8
JB		 4029static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4030{
4031 return 200000;
4032}
79e53945 4033
e70236a8
JB		 4034static int i915gm_get_display_clock_speed(struct drm_device *dev)
4035{
4036 u16 gcfgc = 0;
79e53945 4037
e70236a8
JB		 4038 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4039
4040 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4041 return 133000;
4042 else {
4043 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4044 case GC_DISPLAY_CLOCK_333_MHZ:
4045 return 333000;
4046 default:
4047 case GC_DISPLAY_CLOCK_190_200_MHZ:
4048 return 190000;
79e53945 4049 }
e70236a8
JB		 4050 }
4051}
4052
4053static int i865_get_display_clock_speed(struct drm_device *dev)
4054{
4055 return 266000;
4056}
4057
4058static int i855_get_display_clock_speed(struct drm_device *dev)
4059{
4060 u16 hpllcc = 0;
4061 /* Assume that the hardware is in the high speed state. This
4062 * should be the default.
4063 */
4064 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4065 case GC_CLOCK_133_200:
4066 case GC_CLOCK_100_200:
4067 return 200000;
4068 case GC_CLOCK_166_250:
4069 return 250000;
4070 case GC_CLOCK_100_133:
79e53945 4071 return 133000;
e70236a8 4072 }
79e53945 4073
e70236a8
JB		 4074 /* Shouldn't happen */
4075 return 0;
4076}
79e53945 4077
e70236a8
JB		 4078static int i830_get_display_clock_speed(struct drm_device *dev)
4079{
4080 return 133000;
79e53945
JB		 4081}
4082
2c07245f 4083static void
e69d0bc1 4084intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 4085{
4086 while (*num > 0xffffff || *den > 0xffffff) {
4087 *num >>= 1;
4088 *den >>= 1;
4089 }
4090}
4091
e69d0bc1
DV		 4092void
4093intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4094 int pixel_clock, int link_clock,
4095 struct intel_link_m_n *m_n)
2c07245f 4096{
e69d0bc1 4097 m_n->tu = 64;
22ed1113
CW		 4098 m_n->gmch_m = bits_per_pixel * pixel_clock;
4099 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 4100 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 4101 m_n->link_m = pixel_clock;
4102 m_n->link_n = link_clock;
e69d0bc1 4103 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4104}
4105
a7615030
CW		 4106static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4107{
72bbe58c
KP		 4108 if (i915_panel_use_ssc >= 0)
4109 return i915_panel_use_ssc != 0;
4110 return dev_priv->lvds_use_ssc
435793df 4111 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4112}
4113
a0c4da24
JB		 4114static int vlv_get_refclk(struct drm_crtc *crtc)
4115{
4116 struct drm_device *dev = crtc->dev;
4117 struct drm_i915_private *dev_priv = dev->dev_private;
4118 int refclk = 27000; /* for DP & HDMI */
4119
4120 return 100000; /* only one validated so far */
4121
4122 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4123 refclk = 96000;
4124 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4125 if (intel_panel_use_ssc(dev_priv))
4126 refclk = 100000;
4127 else
4128 refclk = 96000;
4129 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4130 refclk = 100000;
4131 }
4132
4133 return refclk;
4134}
4135
c65d77d8
JB		 4136static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4137{
4138 struct drm_device *dev = crtc->dev;
4139 struct drm_i915_private *dev_priv = dev->dev_private;
4140 int refclk;
4141
a0c4da24
JB		 4142 if (IS_VALLEYVIEW(dev)) {
4143 refclk = vlv_get_refclk(crtc);
4144 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4145 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4146 refclk = dev_priv->lvds_ssc_freq * 1000;
4147 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4148 refclk / 1000);
4149 } else if (!IS_GEN2(dev)) {
4150 refclk = 96000;
4151 } else {
4152 refclk = 48000;
4153 }
4154
4155 return refclk;
4156}
4157
f47709a9 4158static void i9xx_adjust_sdvo_tv_clock(struct intel_crtc *crtc)
c65d77d8 4159{
f47709a9
DV		 4160 unsigned dotclock = crtc->config.adjusted_mode.clock;
4161 struct dpll *clock = &crtc->config.dpll;
4162
c65d77d8
JB		 4163 /* SDVO TV has fixed PLL values depend on its clock range,
4164 this mirrors vbios setting. */
f47709a9 4165 if (dotclock >= 100000 && dotclock < 140500) {
c65d77d8
JB		 4166 clock->p1 = 2;
4167 clock->p2 = 10;
4168 clock->n = 3;
4169 clock->m1 = 16;
4170 clock->m2 = 8;
f47709a9 4171 } else if (dotclock >= 140500 && dotclock <= 200000) {
c65d77d8
JB		 4172 clock->p1 = 1;
4173 clock->p2 = 10;
4174 clock->n = 6;
4175 clock->m1 = 12;
4176 clock->m2 = 8;
4177 }
f47709a9
DV		 4178
4179 crtc->config.clock_set = true;
c65d77d8
JB		 4180}
4181
7429e9d4
DV		 4182static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4183{
4184 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4185}
4186
4187static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4188{
4189 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4190}
4191
f47709a9 4192static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4193 intel_clock_t *reduced_clock)
4194{
f47709a9 4195 struct drm_device *dev = crtc->base.dev;
a7516a05 4196 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4197 int pipe = crtc->pipe;
a7516a05
JB		 4198 u32 fp, fp2 = 0;
4199
4200 if (IS_PINEVIEW(dev)) {
7429e9d4 4201 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4202 if (reduced_clock)
7429e9d4 4203 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4204 } else {
7429e9d4 4205 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4206 if (reduced_clock)
7429e9d4 4207 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4208 }
4209
4210 I915_WRITE(FP0(pipe), fp);
4211
f47709a9
DV		 4212 crtc->lowfreq_avail = false;
4213 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4214 reduced_clock && i915_powersave) {
4215 I915_WRITE(FP1(pipe), fp2);
f47709a9 4216 crtc->lowfreq_avail = true;
a7516a05
JB		 4217 } else {
4218 I915_WRITE(FP1(pipe), fp);
4219 }
4220}
4221
89b667f8
JB		 4222static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4223{
4224 u32 reg_val;
4225
4226 /*
4227 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4228 * and set it to a reasonable value instead.
4229 */
4230 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4231 reg_val &= 0xffffff00;
4232 reg_val |= 0x00000030;
4233 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4234
4235 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4236 reg_val &= 0x8cffffff;
4237 reg_val = 0x8c000000;
4238 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4239
4240 reg_val = intel_dpio_read(dev_priv, DPIO_IREF(1));
4241 reg_val &= 0xffffff00;
4242 intel_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
4243
4244 reg_val = intel_dpio_read(dev_priv, DPIO_CALIBRATION);
4245 reg_val &= 0x00ffffff;
4246 reg_val |= 0xb0000000;
4247 intel_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
4248}
4249
03afc4a2
DV		 4250static void intel_dp_set_m_n(struct intel_crtc *crtc)
4251{
4252 if (crtc->config.has_pch_encoder)
4253 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4254 else
4255 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4256}
4257
f47709a9 4258static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4259{
f47709a9 4260 struct drm_device *dev = crtc->base.dev;
a0c4da24 4261 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8
JB		 4262 struct drm_display_mode *adjusted_mode =
4263 &crtc->config.adjusted_mode;
4264 struct intel_encoder *encoder;
f47709a9 4265 int pipe = crtc->pipe;
89b667f8 4266 u32 dpll, mdiv;
a0c4da24 4267 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4268 bool is_hdmi;
198a037f 4269 u32 coreclk, reg_val, dpll_md;
a0c4da24 4270
09153000
DV		 4271 mutex_lock(&dev_priv->dpio_lock);
4272
89b667f8 4273 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4274
f47709a9
DV		 4275 bestn = crtc->config.dpll.n;
4276 bestm1 = crtc->config.dpll.m1;
4277 bestm2 = crtc->config.dpll.m2;
4278 bestp1 = crtc->config.dpll.p1;
4279 bestp2 = crtc->config.dpll.p2;
a0c4da24 4280
89b667f8
JB		 4281 /* See eDP HDMI DPIO driver vbios notes doc */
4282
4283 /* PLL B needs special handling */
4284 if (pipe)
4285 vlv_pllb_recal_opamp(dev_priv);
4286
4287 /* Set up Tx target for periodic Rcomp update */
4288 intel_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
4289
4290 /* Disable target IRef on PLL */
4291 reg_val = intel_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
4292 reg_val &= 0x00ffffff;
4293 intel_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
4294
4295 /* Disable fast lock */
4296 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
4297
4298 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4299 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4300 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4301 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4302 mdiv |= (1 << DPIO_K_SHIFT);
89b667f8
JB		 4303 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI) ||
4304 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4305 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4306 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
a0c4da24
JB		 4307 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4308
89b667f8
JB		 4309 mdiv |= DPIO_ENABLE_CALIBRATION;
4310 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4311
89b667f8
JB		 4312 /* Set HBR and RBR LPF coefficients */
4313 if (adjusted_mode->clock == 162000 ||
4314 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4315 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4316 0x005f0021);
4317 else
4318 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
4319 0x00d0000f);
4320
4321 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4322 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4323 /* Use SSC source */
4324 if (!pipe)
4325 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4326 0x0df40000);
4327 else
4328 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4329 0x0df70000);
4330 } else { /* HDMI or VGA */
4331 /* Use bend source */
4332 if (!pipe)
4333 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4334 0x0df70000);
4335 else
4336 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe),
4337 0x0df40000);
4338 }
a0c4da24 4339
89b667f8
JB		 4340 coreclk = intel_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
4341 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4342 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4343 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4344 coreclk |= 0x01000000;
4345 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4346
89b667f8 4347 intel_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4348
89b667f8
JB		 4349 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4350 if (encoder->pre_pll_enable)
4351 encoder->pre_pll_enable(encoder);
2a8f64ca 4352
89b667f8
JB		 4353 /* Enable DPIO clock input */
4354 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4355 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4356 if (pipe)
4357 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4358
89b667f8 4359 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4360 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4361 POSTING_READ(DPLL(pipe));
4362 udelay(150);
a0c4da24 4363
89b667f8
JB		 4364 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4365 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4366
198a037f
DV		 4367 dpll_md = 0;
4368 if (crtc->config.pixel_multiplier > 1) {
4369 dpll_md = (crtc->config.pixel_multiplier - 1)
4370 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
2a8f64ca 4371 }
198a037f
DV		 4372 I915_WRITE(DPLL_MD(pipe), dpll_md);
4373 POSTING_READ(DPLL_MD(pipe));
f47709a9 4374
89b667f8
JB		 4375 if (crtc->config.has_dp_encoder)
4376 intel_dp_set_m_n(crtc);
09153000
DV		 4377
4378 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4379}
4380
f47709a9
DV		 4381static void i9xx_update_pll(struct intel_crtc *crtc,
4382 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4383 int num_connectors)
4384{
f47709a9 4385 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4386 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4387 struct intel_encoder *encoder;
f47709a9 4388 int pipe = crtc->pipe;
eb1cbe48
DV		 4389 u32 dpll;
4390 bool is_sdvo;
f47709a9 4391 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4392
f47709a9 4393 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4394
f47709a9
DV		 4395 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4396 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4397
4398 dpll = DPLL_VGA_MODE_DIS;
4399
f47709a9 4400 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4401 dpll |= DPLLB_MODE_LVDS;
4402 else
4403 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4404
198a037f
DV		 4405 if ((crtc->config.pixel_multiplier > 1) &&
4406 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4407 dpll |= (crtc->config.pixel_multiplier - 1)
4408 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4409 }
198a037f
DV		 4410
4411 if (is_sdvo)
4412 dpll |= DPLL_DVO_HIGH_SPEED;
4413
f47709a9 4414 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4415 dpll |= DPLL_DVO_HIGH_SPEED;
4416
4417 /* compute bitmask from p1 value */
4418 if (IS_PINEVIEW(dev))
4419 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4420 else {
4421 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4422 if (IS_G4X(dev) && reduced_clock)
4423 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4424 }
4425 switch (clock->p2) {
4426 case 5:
4427 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4428 break;
4429 case 7:
4430 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4431 break;
4432 case 10:
4433 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4434 break;
4435 case 14:
4436 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4437 break;
4438 }
4439 if (INTEL_INFO(dev)->gen >= 4)
4440 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4441
f47709a9 4442 if (is_sdvo && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48 4443 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4444 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_TVOUT))
eb1cbe48
DV		 4445 /* XXX: just matching BIOS for now */
4446 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4447 dpll |= 3;
f47709a9 4448 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4449 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4450 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4451 else
4452 dpll |= PLL_REF_INPUT_DREFCLK;
4453
4454 dpll |= DPLL_VCO_ENABLE;
4455 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4456 POSTING_READ(DPLL(pipe));
4457 udelay(150);
4458
f47709a9 4459 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4460 if (encoder->pre_pll_enable)
4461 encoder->pre_pll_enable(encoder);
eb1cbe48 4462
f47709a9
DV		 4463 if (crtc->config.has_dp_encoder)
4464 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4465
4466 I915_WRITE(DPLL(pipe), dpll);
4467
4468 /* Wait for the clocks to stabilize. */
4469 POSTING_READ(DPLL(pipe));
4470 udelay(150);
4471
4472 if (INTEL_INFO(dev)->gen >= 4) {
198a037f
DV		 4473 u32 dpll_md = 0;
4474 if (crtc->config.pixel_multiplier > 1) {
4475 dpll_md = (crtc->config.pixel_multiplier - 1)
4476 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
eb1cbe48 4477 }
198a037f 4478 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4479 } else {
4480 /* The pixel multiplier can only be updated once the
4481 * DPLL is enabled and the clocks are stable.
4482 *
4483 * So write it again.
4484 */
4485 I915_WRITE(DPLL(pipe), dpll);
4486 }
4487}
4488
f47709a9 4489static void i8xx_update_pll(struct intel_crtc *crtc,
eb1cbe48 4490 struct drm_display_mode *adjusted_mode,
f47709a9 4491 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4492 int num_connectors)
4493{
f47709a9 4494 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4495 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4496 struct intel_encoder *encoder;
f47709a9 4497 int pipe = crtc->pipe;
eb1cbe48 4498 u32 dpll;
f47709a9 4499 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4500
f47709a9 4501 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4502
eb1cbe48
DV		 4503 dpll = DPLL_VGA_MODE_DIS;
4504
f47709a9 4505 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4506 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4507 } else {
4508 if (clock->p1 == 2)
4509 dpll |= PLL_P1_DIVIDE_BY_TWO;
4510 else
4511 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4512 if (clock->p2 == 4)
4513 dpll |= PLL_P2_DIVIDE_BY_4;
4514 }
4515
f47709a9 4516 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4517 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4518 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4519 else
4520 dpll |= PLL_REF_INPUT_DREFCLK;
4521
4522 dpll |= DPLL_VCO_ENABLE;
4523 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4524 POSTING_READ(DPLL(pipe));
4525 udelay(150);
4526
f47709a9 4527 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4528 if (encoder->pre_pll_enable)
4529 encoder->pre_pll_enable(encoder);
eb1cbe48 4530
5b5896e4
DV		 4531 I915_WRITE(DPLL(pipe), dpll);
4532
4533 /* Wait for the clocks to stabilize. */
4534 POSTING_READ(DPLL(pipe));
4535 udelay(150);
4536
eb1cbe48
DV		 4537 /* The pixel multiplier can only be updated once the
4538 * DPLL is enabled and the clocks are stable.
4539 *
4540 * So write it again.
4541 */
4542 I915_WRITE(DPLL(pipe), dpll);
4543}
4544
b0e77b9c
PZ		 4545static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4546 struct drm_display_mode *mode,
4547 struct drm_display_mode *adjusted_mode)
4548{
4549 struct drm_device *dev = intel_crtc->base.dev;
4550 struct drm_i915_private *dev_priv = dev->dev_private;
4551 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4552 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
b0e77b9c
PZ		 4553 uint32_t vsyncshift;
4554
4555 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4556 /* the chip adds 2 halflines automatically */
4557 adjusted_mode->crtc_vtotal -= 1;
4558 adjusted_mode->crtc_vblank_end -= 1;
4559 vsyncshift = adjusted_mode->crtc_hsync_start
4560 - adjusted_mode->crtc_htotal / 2;
4561 } else {
4562 vsyncshift = 0;
4563 }
4564
4565 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4566 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4567
fe2b8f9d 4568 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4569 (adjusted_mode->crtc_hdisplay - 1) |
4570 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4571 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4572 (adjusted_mode->crtc_hblank_start - 1) |
4573 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4574 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4575 (adjusted_mode->crtc_hsync_start - 1) |
4576 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4577
fe2b8f9d 4578 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4579 (adjusted_mode->crtc_vdisplay - 1) |
4580 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4581 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4582 (adjusted_mode->crtc_vblank_start - 1) |
4583 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4584 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4585 (adjusted_mode->crtc_vsync_start - 1) |
4586 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4587
b5e508d4
PZ		 4588 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4589 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4590 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4591 * bits. */
4592 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4593 (pipe == PIPE_B || pipe == PIPE_C))
4594 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4595
b0e77b9c
PZ		 4596 /* pipesrc controls the size that is scaled from, which should
4597 * always be the user's requested size.
4598 */
4599 I915_WRITE(PIPESRC(pipe),
4600 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4601}
4602
84b046f3
DV		 4603static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4604{
4605 struct drm_device *dev = intel_crtc->base.dev;
4606 struct drm_i915_private *dev_priv = dev->dev_private;
4607 uint32_t pipeconf;
4608
4609 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4610
4611 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4612 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4613 * core speed.
4614 *
4615 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4616 * pipe == 0 check?
4617 */
4618 if (intel_crtc->config.requested_mode.clock >
4619 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4620 pipeconf |= PIPECONF_DOUBLE_WIDE;
4621 else
4622 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4623 }
4624
ff9ce46e
DV		 4625 /* only g4x and later have fancy bpc/dither controls */
4626 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4627 pipeconf &= ~(PIPECONF_BPC_MASK |
4628 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4629
4630 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4631 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4632 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4633 PIPECONF_DITHER_TYPE_SP;
84b046f3 4634
ff9ce46e
DV		 4635 switch (intel_crtc->config.pipe_bpp) {
4636 case 18:
4637 pipeconf |= PIPECONF_6BPC;
4638 break;
4639 case 24:
4640 pipeconf |= PIPECONF_8BPC;
4641 break;
4642 case 30:
4643 pipeconf |= PIPECONF_10BPC;
4644 break;
4645 default:
4646 /* Case prevented by intel_choose_pipe_bpp_dither. */
4647 BUG();
84b046f3
DV		 4648 }
4649 }
4650
4651 if (HAS_PIPE_CXSR(dev)) {
4652 if (intel_crtc->lowfreq_avail) {
4653 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4654 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4655 } else {
4656 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4657 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4658 }
4659 }
4660
4661 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4662 if (!IS_GEN2(dev) &&
4663 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4664 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4665 else
4666 pipeconf |= PIPECONF_PROGRESSIVE;
4667
9c8e09b7
VS		 4668 if (IS_VALLEYVIEW(dev)) {
4669 if (intel_crtc->config.limited_color_range)
4670 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4671 else
4672 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4673 }
4674
84b046f3
DV		 4675 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4676 POSTING_READ(PIPECONF(intel_crtc->pipe));
4677}
4678
f564048e 4679static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4680 int x, int y,
94352cf9 4681 struct drm_framebuffer *fb)
79e53945
JB		 4682{
4683 struct drm_device *dev = crtc->dev;
4684 struct drm_i915_private *dev_priv = dev->dev_private;
4685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4686 struct drm_display_mode *adjusted_mode =
4687 &intel_crtc->config.adjusted_mode;
4688 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4689 int pipe = intel_crtc->pipe;
80824003 4690 int plane = intel_crtc->plane;
c751ce4f 4691 int refclk, num_connectors = 0;
652c393a 4692 intel_clock_t clock, reduced_clock;
84b046f3 4693 u32 dspcntr;
eb1cbe48 4694 bool ok, has_reduced_clock = false, is_sdvo = false;
8b47047b 4695 bool is_lvds = false, is_tv = false;
5eddb70b 4696 struct intel_encoder *encoder;
d4906093 4697 const intel_limit_t *limit;
5c3b82e2 4698 int ret;
79e53945 4699
6c2b7c12 4700 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4701 switch (encoder->type) {
79e53945
JB		 4702 case INTEL_OUTPUT_LVDS:
4703 is_lvds = true;
4704 break;
4705 case INTEL_OUTPUT_SDVO:
7d57382e 4706 case INTEL_OUTPUT_HDMI:
79e53945 4707 is_sdvo = true;
5eddb70b 4708 if (encoder->needs_tv_clock)
e2f0ba97 4709 is_tv = true;
79e53945 4710 break;
79e53945
JB		 4711 case INTEL_OUTPUT_TVOUT:
4712 is_tv = true;
4713 break;
79e53945 4714 }
43565a06 4715
c751ce4f 4716 num_connectors++;
79e53945
JB		 4717 }
4718
c65d77d8 4719 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4720
d4906093
ML		 4721 /*
4722 * Returns a set of divisors for the desired target clock with the given
4723 * refclk, or FALSE. The returned values represent the clock equation:
4724 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4725 */
1b894b59 4726 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4727 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4728 &clock);
79e53945
JB		 4729 if (!ok) {
4730 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4731 return -EINVAL;
79e53945
JB		 4732 }
4733
cda4b7d3 4734 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4735 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4736
ddc9003c 4737 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4738 /*
4739 * Ensure we match the reduced clock's P to the target clock.
4740 * If the clocks don't match, we can't switch the display clock
4741 * by using the FP0/FP1. In such case we will disable the LVDS
4742 * downclock feature.
4743 */
ddc9003c 4744 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4745 dev_priv->lvds_downclock,
4746 refclk,
cec2f356 4747 &clock,
5eddb70b 4748 &reduced_clock);
7026d4ac 4749 }
f47709a9
DV		 4750 /* Compat-code for transition, will disappear. */
4751 if (!intel_crtc->config.clock_set) {
4752 intel_crtc->config.dpll.n = clock.n;
4753 intel_crtc->config.dpll.m1 = clock.m1;
4754 intel_crtc->config.dpll.m2 = clock.m2;
4755 intel_crtc->config.dpll.p1 = clock.p1;
4756 intel_crtc->config.dpll.p2 = clock.p2;
4757 }
7026d4ac 4758
c65d77d8 4759 if (is_sdvo && is_tv)
f47709a9 4760 i9xx_adjust_sdvo_tv_clock(intel_crtc);
7026d4ac 4761
eb1cbe48 4762 if (IS_GEN2(dev))
f47709a9 4763 i8xx_update_pll(intel_crtc, adjusted_mode,
2a8f64ca
VP		 4764 has_reduced_clock ? &reduced_clock : NULL,
4765 num_connectors);
a0c4da24 4766 else if (IS_VALLEYVIEW(dev))
f47709a9 4767 vlv_update_pll(intel_crtc);
79e53945 4768 else
f47709a9 4769 i9xx_update_pll(intel_crtc,
eb1cbe48 4770 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4771 num_connectors);
79e53945 4772
79e53945
JB		 4773 /* Set up the display plane register */
4774 dspcntr = DISPPLANE_GAMMA_ENABLE;
4775
da6ecc5d
JB		 4776 if (!IS_VALLEYVIEW(dev)) {
4777 if (pipe == 0)
4778 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4779 else
4780 dspcntr |= DISPPLANE_SEL_PIPE_B;
4781 }
79e53945 4782
2582a850 4783 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 4784 drm_mode_debug_printmodeline(mode);
4785
b0e77b9c 4786 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4787
4788 /* pipesrc and dspsize control the size that is scaled from,
4789 * which should always be the user's requested size.
79e53945 4790 */
929c77fb
EA		 4791 I915_WRITE(DSPSIZE(plane),
4792 ((mode->vdisplay - 1) << 16) |
4793 (mode->hdisplay - 1));
4794 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4795
84b046f3
DV		 4796 i9xx_set_pipeconf(intel_crtc);
4797
f564048e
EA		 4798 I915_WRITE(DSPCNTR(plane), dspcntr);
4799 POSTING_READ(DSPCNTR(plane));
4800
94352cf9 4801 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4802
4803 intel_update_watermarks(dev);
4804
f564048e
EA		 4805 return ret;
4806}
4807
0e8ffe1b
DV		 4808static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4809 struct intel_crtc_config *pipe_config)
4810{
4811 struct drm_device *dev = crtc->base.dev;
4812 struct drm_i915_private *dev_priv = dev->dev_private;
4813 uint32_t tmp;
4814
4815 tmp = I915_READ(PIPECONF(crtc->pipe));
4816 if (!(tmp & PIPECONF_ENABLE))
4817 return false;
4818
4819 return true;
4820}
4821
dde86e2d 4822static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4823{
4824 struct drm_i915_private *dev_priv = dev->dev_private;
4825 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4826 struct intel_encoder *encoder;
74cfd7ac 4827 u32 val, final;
13d83a67 4828 bool has_lvds = false;
199e5d79
KP		 4829 bool has_cpu_edp = false;
4830 bool has_pch_edp = false;
4831 bool has_panel = false;
99eb6a01
KP		 4832 bool has_ck505 = false;
4833 bool can_ssc = false;
13d83a67
JB		 4834
4835 /* We need to take the global config into account */
199e5d79
KP		 4836 list_for_each_entry(encoder, &mode_config->encoder_list,
4837 base.head) {
4838 switch (encoder->type) {
4839 case INTEL_OUTPUT_LVDS:
4840 has_panel = true;
4841 has_lvds = true;
4842 break;
4843 case INTEL_OUTPUT_EDP:
4844 has_panel = true;
4845 if (intel_encoder_is_pch_edp(&encoder->base))
4846 has_pch_edp = true;
4847 else
4848 has_cpu_edp = true;
4849 break;
13d83a67
JB		 4850 }
4851 }
4852
99eb6a01
KP		 4853 if (HAS_PCH_IBX(dev)) {
4854 has_ck505 = dev_priv->display_clock_mode;
4855 can_ssc = has_ck505;
4856 } else {
4857 has_ck505 = false;
4858 can_ssc = true;
4859 }
4860
4861 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4862 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4863 has_ck505);
13d83a67
JB		 4864
4865 /* Ironlake: try to setup display ref clock before DPLL
4866 * enabling. This is only under driver's control after
4867 * PCH B stepping, previous chipset stepping should be
4868 * ignoring this setting.
4869 */
74cfd7ac
CW		 4870 val = I915_READ(PCH_DREF_CONTROL);
4871
4872 /* As we must carefully and slowly disable/enable each source in turn,
4873 * compute the final state we want first and check if we need to
4874 * make any changes at all.
4875 */
4876 final = val;
4877 final &= ~DREF_NONSPREAD_SOURCE_MASK;
4878 if (has_ck505)
4879 final |= DREF_NONSPREAD_CK505_ENABLE;
4880 else
4881 final |= DREF_NONSPREAD_SOURCE_ENABLE;
4882
4883 final &= ~DREF_SSC_SOURCE_MASK;
4884 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4885 final &= ~DREF_SSC1_ENABLE;
4886
4887 if (has_panel) {
4888 final |= DREF_SSC_SOURCE_ENABLE;
4889
4890 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4891 final |= DREF_SSC1_ENABLE;
4892
4893 if (has_cpu_edp) {
4894 if (intel_panel_use_ssc(dev_priv) && can_ssc)
4895 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4896 else
4897 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4898 } else
4899 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4900 } else {
4901 final |= DREF_SSC_SOURCE_DISABLE;
4902 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4903 }
4904
4905 if (final == val)
4906 return;
4907
13d83a67 4908 /* Always enable nonspread source */
74cfd7ac 4909 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4910
99eb6a01 4911 if (has_ck505)
74cfd7ac 4912 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 4913 else
74cfd7ac 4914 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4915
199e5d79 4916 if (has_panel) {
74cfd7ac
CW		 4917 val &= ~DREF_SSC_SOURCE_MASK;
4918 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4919
199e5d79 4920 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4921 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4922 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 4923 val |= DREF_SSC1_ENABLE;
e77166b5 4924 } else
74cfd7ac 4925 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4926
4927 /* Get SSC going before enabling the outputs */
74cfd7ac 4928 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4929 POSTING_READ(PCH_DREF_CONTROL);
4930 udelay(200);
4931
74cfd7ac 4932 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 4933
4934 /* Enable CPU source on CPU attached eDP */
199e5d79 4935 if (has_cpu_edp) {
99eb6a01 4936 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4937 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 4938 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4939 }
13d83a67 4940 else
74cfd7ac 4941 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 4942 } else
74cfd7ac 4943 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 4944
74cfd7ac 4945 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4946 POSTING_READ(PCH_DREF_CONTROL);
4947 udelay(200);
4948 } else {
4949 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4950
74cfd7ac 4951 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 4952
4953 /* Turn off CPU output */
74cfd7ac 4954 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 4955
74cfd7ac 4956 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 4957 POSTING_READ(PCH_DREF_CONTROL);
4958 udelay(200);
4959
4960 /* Turn off the SSC source */
74cfd7ac
CW		 4961 val &= ~DREF_SSC_SOURCE_MASK;
4962 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 4963
4964 /* Turn off SSC1 */
74cfd7ac 4965 val &= ~DREF_SSC1_ENABLE;
199e5d79 4966
74cfd7ac 4967 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 4968 POSTING_READ(PCH_DREF_CONTROL);
4969 udelay(200);
4970 }
74cfd7ac
CW		 4971
4972 BUG_ON(val != final);
13d83a67
JB		 4973}
4974
dde86e2d
PZ		 4975/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4976static void lpt_init_pch_refclk(struct drm_device *dev)
4977{
4978 struct drm_i915_private *dev_priv = dev->dev_private;
4979 struct drm_mode_config *mode_config = &dev->mode_config;
4980 struct intel_encoder *encoder;
4981 bool has_vga = false;
4982 bool is_sdv = false;
4983 u32 tmp;
4984
4985 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4986 switch (encoder->type) {
4987 case INTEL_OUTPUT_ANALOG:
4988 has_vga = true;
4989 break;
4990 }
4991 }
4992
4993 if (!has_vga)
4994 return;
4995
c00db246
DV		 4996 mutex_lock(&dev_priv->dpio_lock);
4997
dde86e2d
PZ		 4998 /* XXX: Rip out SDV support once Haswell ships for real. */
4999 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5000 is_sdv = true;
5001
5002 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5003 tmp &= ~SBI_SSCCTL_DISABLE;
5004 tmp |= SBI_SSCCTL_PATHALT;
5005 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5006
5007 udelay(24);
5008
5009 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5010 tmp &= ~SBI_SSCCTL_PATHALT;
5011 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5012
5013 if (!is_sdv) {
5014 tmp = I915_READ(SOUTH_CHICKEN2);
5015 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5016 I915_WRITE(SOUTH_CHICKEN2, tmp);
5017
5018 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5019 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5020 DRM_ERROR("FDI mPHY reset assert timeout\n");
5021
5022 tmp = I915_READ(SOUTH_CHICKEN2);
5023 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5024 I915_WRITE(SOUTH_CHICKEN2, tmp);
5025
5026 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5027 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5028 100))
5029 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5030 }
5031
5032 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5033 tmp &= ~(0xFF << 24);
5034 tmp |= (0x12 << 24);
5035 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5036
dde86e2d
PZ		 5037 if (is_sdv) {
5038 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5039 tmp |= 0x7FFF;
5040 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5041 }
5042
5043 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5044 tmp |= (1 << 11);
5045 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5046
5047 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5048 tmp |= (1 << 11);
5049 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5050
5051 if (is_sdv) {
5052 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5053 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5054 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5055
5056 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5057 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5058 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5059
5060 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5061 tmp |= (0x3F << 8);
5062 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5063
5064 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5065 tmp |= (0x3F << 8);
5066 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5067 }
5068
5069 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5070 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5071 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5072
5073 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5074 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5075 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5076
5077 if (!is_sdv) {
5078 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5079 tmp &= ~(7 << 13);
5080 tmp |= (5 << 13);
5081 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5082
5083 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5084 tmp &= ~(7 << 13);
5085 tmp |= (5 << 13);
5086 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5087 }
5088
5089 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5090 tmp &= ~0xFF;
5091 tmp |= 0x1C;
5092 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5093
5094 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5095 tmp &= ~0xFF;
5096 tmp |= 0x1C;
5097 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5098
5099 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5100 tmp &= ~(0xFF << 16);
5101 tmp |= (0x1C << 16);
5102 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5103
5104 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5105 tmp &= ~(0xFF << 16);
5106 tmp |= (0x1C << 16);
5107 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5108
5109 if (!is_sdv) {
5110 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5111 tmp |= (1 << 27);
5112 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5113
5114 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5115 tmp |= (1 << 27);
5116 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5117
5118 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5119 tmp &= ~(0xF << 28);
5120 tmp |= (4 << 28);
5121 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5122
5123 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5124 tmp &= ~(0xF << 28);
5125 tmp |= (4 << 28);
5126 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5127 }
5128
5129 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5130 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5131 tmp |= SBI_DBUFF0_ENABLE;
5132 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5133
5134 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5135}
5136
5137/*
5138 * Initialize reference clocks when the driver loads
5139 */
5140void intel_init_pch_refclk(struct drm_device *dev)
5141{
5142 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5143 ironlake_init_pch_refclk(dev);
5144 else if (HAS_PCH_LPT(dev))
5145 lpt_init_pch_refclk(dev);
5146}
5147
d9d444cb
JB		 5148static int ironlake_get_refclk(struct drm_crtc *crtc)
5149{
5150 struct drm_device *dev = crtc->dev;
5151 struct drm_i915_private *dev_priv = dev->dev_private;
5152 struct intel_encoder *encoder;
d9d444cb
JB		 5153 struct intel_encoder *edp_encoder = NULL;
5154 int num_connectors = 0;
5155 bool is_lvds = false;
5156
6c2b7c12 5157 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5158 switch (encoder->type) {
5159 case INTEL_OUTPUT_LVDS:
5160 is_lvds = true;
5161 break;
5162 case INTEL_OUTPUT_EDP:
5163 edp_encoder = encoder;
5164 break;
5165 }
5166 num_connectors++;
5167 }
5168
5169 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5170 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5171 dev_priv->lvds_ssc_freq);
5172 return dev_priv->lvds_ssc_freq * 1000;
5173 }
5174
5175 return 120000;
5176}
5177
6ff93609 5178static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5179{
c8203565 5180 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5182 int pipe = intel_crtc->pipe;
c8203565
PZ		 5183 uint32_t val;
5184
5185 val = I915_READ(PIPECONF(pipe));
5186
dfd07d72 5187 val &= ~PIPECONF_BPC_MASK;
965e0c48 5188 switch (intel_crtc->config.pipe_bpp) {
c8203565 5189 case 18:
dfd07d72 5190 val |= PIPECONF_6BPC;
c8203565
PZ		 5191 break;
5192 case 24:
dfd07d72 5193 val |= PIPECONF_8BPC;
c8203565
PZ		 5194 break;
5195 case 30:
dfd07d72 5196 val |= PIPECONF_10BPC;
c8203565
PZ		 5197 break;
5198 case 36:
dfd07d72 5199 val |= PIPECONF_12BPC;
c8203565
PZ		 5200 break;
5201 default:
cc769b62
PZ		 5202 /* Case prevented by intel_choose_pipe_bpp_dither. */
5203 BUG();
c8203565
PZ		 5204 }
5205
5206 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5207 if (intel_crtc->config.dither)
c8203565
PZ		 5208 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5209
5210 val &= ~PIPECONF_INTERLACE_MASK;
6ff93609 5211 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5212 val |= PIPECONF_INTERLACED_ILK;
5213 else
5214 val |= PIPECONF_PROGRESSIVE;
5215
50f3b016 5216 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5217 val |= PIPECONF_COLOR_RANGE_SELECT;
5218 else
5219 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5220
c8203565
PZ		 5221 I915_WRITE(PIPECONF(pipe), val);
5222 POSTING_READ(PIPECONF(pipe));
5223}
5224
86d3efce
VS		 5225/*
5226 * Set up the pipe CSC unit.
5227 *
5228 * Currently only full range RGB to limited range RGB conversion
5229 * is supported, but eventually this should handle various
5230 * RGB<->YCbCr scenarios as well.
5231 */
50f3b016 5232static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5233{
5234 struct drm_device *dev = crtc->dev;
5235 struct drm_i915_private *dev_priv = dev->dev_private;
5236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5237 int pipe = intel_crtc->pipe;
5238 uint16_t coeff = 0x7800; /* 1.0 */
5239
5240 /*
5241 * TODO: Check what kind of values actually come out of the pipe
5242 * with these coeff/postoff values and adjust to get the best
5243 * accuracy. Perhaps we even need to take the bpc value into
5244 * consideration.
5245 */
5246
50f3b016 5247 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5248 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5249
5250 /*
5251 * GY/GU and RY/RU should be the other way around according
5252 * to BSpec, but reality doesn't agree. Just set them up in
5253 * a way that results in the correct picture.
5254 */
5255 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5256 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5257
5258 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5259 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5260
5261 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5262 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5263
5264 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5265 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5266 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5267
5268 if (INTEL_INFO(dev)->gen > 6) {
5269 uint16_t postoff = 0;
5270
50f3b016 5271 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5272 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5273
5274 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5275 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5276 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5277
5278 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5279 } else {
5280 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5281
50f3b016 5282 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5283 mode |= CSC_BLACK_SCREEN_OFFSET;
5284
5285 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5286 }
5287}
5288
6ff93609 5289static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5290{
5291 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5292 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5293 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5294 uint32_t val;
5295
702e7a56 5296 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5297
5298 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5299 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5300 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5301
5302 val &= ~PIPECONF_INTERLACE_MASK_HSW;
6ff93609 5303 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5304 val |= PIPECONF_INTERLACED_ILK;
5305 else
5306 val |= PIPECONF_PROGRESSIVE;
5307
702e7a56
PZ		 5308 I915_WRITE(PIPECONF(cpu_transcoder), val);
5309 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5310}
5311
6591c6e4
PZ		 5312static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5313 struct drm_display_mode *adjusted_mode,
5314 intel_clock_t *clock,
5315 bool *has_reduced_clock,
5316 intel_clock_t *reduced_clock)
5317{
5318 struct drm_device *dev = crtc->dev;
5319 struct drm_i915_private *dev_priv = dev->dev_private;
5320 struct intel_encoder *intel_encoder;
5321 int refclk;
d4906093 5322 const intel_limit_t *limit;
6591c6e4 5323 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5324
6591c6e4
PZ		 5325 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5326 switch (intel_encoder->type) {
79e53945
JB		 5327 case INTEL_OUTPUT_LVDS:
5328 is_lvds = true;
5329 break;
5330 case INTEL_OUTPUT_SDVO:
7d57382e 5331 case INTEL_OUTPUT_HDMI:
79e53945 5332 is_sdvo = true;
6591c6e4 5333 if (intel_encoder->needs_tv_clock)
e2f0ba97 5334 is_tv = true;
79e53945 5335 break;
79e53945
JB		 5336 case INTEL_OUTPUT_TVOUT:
5337 is_tv = true;
5338 break;
79e53945
JB		 5339 }
5340 }
5341
d9d444cb 5342 refclk = ironlake_get_refclk(crtc);
79e53945 5343
d4906093
ML		 5344 /*
5345 * Returns a set of divisors for the desired target clock with the given
5346 * refclk, or FALSE. The returned values represent the clock equation:
5347 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5348 */
1b894b59 5349 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5350 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5351 clock);
5352 if (!ret)
5353 return false;
cda4b7d3 5354
ddc9003c 5355 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5356 /*
5357 * Ensure we match the reduced clock's P to the target clock.
5358 * If the clocks don't match, we can't switch the display clock
5359 * by using the FP0/FP1. In such case we will disable the LVDS
5360 * downclock feature.
5361 */
6591c6e4
PZ		 5362 *has_reduced_clock = limit->find_pll(limit, crtc,
5363 dev_priv->lvds_downclock,
5364 refclk,
5365 clock,
5366 reduced_clock);
652c393a 5367 }
61e9653f
DV		 5368
5369 if (is_sdvo && is_tv)
f47709a9 5370 i9xx_adjust_sdvo_tv_clock(to_intel_crtc(crtc));
6591c6e4
PZ		 5371
5372 return true;
5373}
5374
01a415fd
DV		 5375static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5376{
5377 struct drm_i915_private *dev_priv = dev->dev_private;
5378 uint32_t temp;
5379
5380 temp = I915_READ(SOUTH_CHICKEN1);
5381 if (temp & FDI_BC_BIFURCATION_SELECT)
5382 return;
5383
5384 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5385 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5386
5387 temp |= FDI_BC_BIFURCATION_SELECT;
5388 DRM_DEBUG_KMS("enabling fdi C rx\n");
5389 I915_WRITE(SOUTH_CHICKEN1, temp);
5390 POSTING_READ(SOUTH_CHICKEN1);
5391}
5392
5393static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5394{
5395 struct drm_device *dev = intel_crtc->base.dev;
5396 struct drm_i915_private *dev_priv = dev->dev_private;
5397 struct intel_crtc *pipe_B_crtc =
5398 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5399
84f44ce7 5400 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
33d29b14
DV		 5401 pipe_name(intel_crtc->pipe), intel_crtc->config.fdi_lanes);
5402 if (intel_crtc->config.fdi_lanes > 4) {
84f44ce7 5403 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
33d29b14 5404 pipe_name(intel_crtc->pipe), intel_crtc->config.fdi_lanes);
01a415fd 5405 /* Clamp lanes to avoid programming the hw with bogus values. */
33d29b14 5406 intel_crtc->config.fdi_lanes = 4;
01a415fd
DV		 5407
5408 return false;
5409 }
5410
7eb552ae 5411 if (INTEL_INFO(dev)->num_pipes == 2)
01a415fd
DV		 5412 return true;
5413
5414 switch (intel_crtc->pipe) {
5415 case PIPE_A:
5416 return true;
5417 case PIPE_B:
5418 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
33d29b14 5419 intel_crtc->config.fdi_lanes > 2) {
84f44ce7 5420 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
33d29b14 5421 pipe_name(intel_crtc->pipe), intel_crtc->config.fdi_lanes);
01a415fd 5422 /* Clamp lanes to avoid programming the hw with bogus values. */
33d29b14 5423 intel_crtc->config.fdi_lanes = 2;
01a415fd
DV		 5424
5425 return false;
5426 }
5427
33d29b14 5428 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5429 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5430 else
5431 cpt_enable_fdi_bc_bifurcation(dev);
5432
5433 return true;
5434 case PIPE_C:
33d29b14
DV		 5435 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->config.fdi_lanes <= 2) {
5436 if (intel_crtc->config.fdi_lanes > 2) {
84f44ce7 5437 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
33d29b14 5438 pipe_name(intel_crtc->pipe), intel_crtc->config.fdi_lanes);
01a415fd 5439 /* Clamp lanes to avoid programming the hw with bogus values. */
33d29b14 5440 intel_crtc->config.fdi_lanes = 2;
01a415fd
DV		 5441
5442 return false;
5443 }
5444 } else {
5445 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5446 return false;
5447 }
5448
5449 cpt_enable_fdi_bc_bifurcation(dev);
5450
5451 return true;
5452 default:
5453 BUG();
5454 }
5455}
5456
d4b1931c
PZ		 5457int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5458{
5459 /*
5460 * Account for spread spectrum to avoid
5461 * oversubscribing the link. Max center spread
5462 * is 2.5%; use 5% for safety's sake.
5463 */
5464 u32 bps = target_clock * bpp * 21 / 20;
5465 return bps / (link_bw * 8) + 1;
5466}
5467
6cf86a5e
DV		 5468void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
5469 struct intel_link_m_n *m_n)
79e53945 5470{
6cf86a5e
DV		 5471 struct drm_device *dev = crtc->base.dev;
5472 struct drm_i915_private *dev_priv = dev->dev_private;
5473 int pipe = crtc->pipe;
5474
5475 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5476 I915_WRITE(TRANSDATA_N1(pipe), m_n->gmch_n);
5477 I915_WRITE(TRANSDPLINK_M1(pipe), m_n->link_m);
5478 I915_WRITE(TRANSDPLINK_N1(pipe), m_n->link_n);
5479}
5480
5481void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
5482 struct intel_link_m_n *m_n)
5483{
5484 struct drm_device *dev = crtc->base.dev;
79e53945 5485 struct drm_i915_private *dev_priv = dev->dev_private;
6cf86a5e 5486 int pipe = crtc->pipe;
3b117c8f 5487 enum transcoder transcoder = crtc->config.cpu_transcoder;
6cf86a5e
DV		 5488
5489 if (INTEL_INFO(dev)->gen >= 5) {
5490 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
5491 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
5492 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
5493 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
5494 } else {
5495 I915_WRITE(PIPE_GMCH_DATA_M(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
5496 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n->gmch_n);
5497 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n->link_m);
5498 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n->link_n);
5499 }
5500}
5501
5502static void ironlake_fdi_set_m_n(struct drm_crtc *crtc)
5503{
5504 struct drm_device *dev = crtc->dev;
79e53945 5505 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6cc5f341
DV		 5506 struct drm_display_mode *adjusted_mode =
5507 &intel_crtc->config.adjusted_mode;
e69d0bc1 5508 struct intel_link_m_n m_n = {0};
6cc5f341 5509 int target_clock, lane, link_bw;
61e9653f 5510
6cf86a5e
DV		 5511 /* FDI is a binary signal running at ~2.7GHz, encoding
5512 * each output octet as 10 bits. The actual frequency
5513 * is stored as a divider into a 100MHz clock, and the
5514 * mode pixel clock is stored in units of 1KHz.
5515 * Hence the bw of each lane in terms of the mode signal
5516 * is:
5517 */
5518 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
58a27471 5519
df92b1e6
DV		 5520 if (intel_crtc->config.pixel_target_clock)
5521 target_clock = intel_crtc->config.pixel_target_clock;
94bf2ced
DV		 5522 else
5523 target_clock = adjusted_mode->clock;
5524
6cf86a5e
DV		 5525 lane = ironlake_get_lanes_required(target_clock, link_bw,
5526 intel_crtc->config.pipe_bpp);
2c07245f 5527
33d29b14 5528 intel_crtc->config.fdi_lanes = lane;
8febb297 5529
6cc5f341
DV		 5530 if (intel_crtc->config.pixel_multiplier > 1)
5531 link_bw *= intel_crtc->config.pixel_multiplier;
965e0c48
DV		 5532 intel_link_compute_m_n(intel_crtc->config.pipe_bpp, lane, target_clock,
5533 link_bw, &m_n);
8febb297 5534
6cf86a5e 5535 intel_cpu_transcoder_set_m_n(intel_crtc, &m_n);
f48d8f23
PZ		 5536}
5537
7429e9d4
DV		 5538static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5539{
5540 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5541}
5542
de13a2e3 5543static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5544 u32 *fp,
9a7c7890 5545 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5546{
de13a2e3 5547 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5548 struct drm_device *dev = crtc->dev;
5549 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5550 struct intel_encoder *intel_encoder;
5551 uint32_t dpll;
6cc5f341 5552 int factor, num_connectors = 0;
de13a2e3 5553 bool is_lvds = false, is_sdvo = false, is_tv = false;
79e53945 5554
de13a2e3
PZ		 5555 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5556 switch (intel_encoder->type) {
79e53945
JB		 5557 case INTEL_OUTPUT_LVDS:
5558 is_lvds = true;
5559 break;
5560 case INTEL_OUTPUT_SDVO:
7d57382e 5561 case INTEL_OUTPUT_HDMI:
79e53945 5562 is_sdvo = true;
de13a2e3 5563 if (intel_encoder->needs_tv_clock)
e2f0ba97 5564 is_tv = true;
79e53945 5565 break;
79e53945
JB		 5566 case INTEL_OUTPUT_TVOUT:
5567 is_tv = true;
5568 break;
79e53945 5569 }
43565a06 5570
c751ce4f 5571 num_connectors++;
79e53945 5572 }
79e53945 5573
c1858123 5574 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5575 factor = 21;
5576 if (is_lvds) {
5577 if ((intel_panel_use_ssc(dev_priv) &&
5578 dev_priv->lvds_ssc_freq == 100) ||
f0b44056 5579 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297
EA		 5580 factor = 25;
5581 } else if (is_sdvo && is_tv)
5582 factor = 20;
c1858123 5583
7429e9d4 5584 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5585 *fp |= FP_CB_TUNE;
2c07245f 5586
9a7c7890
DV		 5587 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5588 *fp2 |= FP_CB_TUNE;
5589
5eddb70b 5590 dpll = 0;
2c07245f 5591
a07d6787
EA		 5592 if (is_lvds)
5593 dpll |= DPLLB_MODE_LVDS;
5594 else
5595 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f
DV		 5596
5597 if (intel_crtc->config.pixel_multiplier > 1) {
5598 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5599 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
a07d6787 5600 }
198a037f
DV		 5601
5602 if (is_sdvo)
5603 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5604 if (intel_crtc->config.has_dp_encoder)
a07d6787 5605 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5606
a07d6787 5607 /* compute bitmask from p1 value */
7429e9d4 5608 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5609 /* also FPA1 */
7429e9d4 5610 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5611
7429e9d4 5612 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5613 case 5:
5614 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5615 break;
5616 case 7:
5617 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5618 break;
5619 case 10:
5620 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5621 break;
5622 case 14:
5623 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5624 break;
79e53945
JB		 5625 }
5626
43565a06
KH		 5627 if (is_sdvo && is_tv)
5628 dpll |= PLL_REF_INPUT_TVCLKINBC;
5629 else if (is_tv)
79e53945 5630 /* XXX: just matching BIOS for now */
43565a06 5631 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5632 dpll |= 3;
a7615030 5633 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5634 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5635 else
5636 dpll |= PLL_REF_INPUT_DREFCLK;
5637
de13a2e3
PZ		 5638 return dpll;
5639}
5640
5641static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5642 int x, int y,
5643 struct drm_framebuffer *fb)
5644{
5645 struct drm_device *dev = crtc->dev;
5646 struct drm_i915_private *dev_priv = dev->dev_private;
5647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5648 struct drm_display_mode *adjusted_mode =
5649 &intel_crtc->config.adjusted_mode;
5650 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5651 int pipe = intel_crtc->pipe;
5652 int plane = intel_crtc->plane;
5653 int num_connectors = 0;
5654 intel_clock_t clock, reduced_clock;
cbbab5bd 5655 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5656 bool ok, has_reduced_clock = false;
8b47047b 5657 bool is_lvds = false;
de13a2e3 5658 struct intel_encoder *encoder;
de13a2e3 5659 int ret;
d8b32247 5660 bool fdi_config_ok;
de13a2e3
PZ		 5661
5662 for_each_encoder_on_crtc(dev, crtc, encoder) {
5663 switch (encoder->type) {
5664 case INTEL_OUTPUT_LVDS:
5665 is_lvds = true;
5666 break;
de13a2e3
PZ		 5667 }
5668
5669 num_connectors++;
a07d6787 5670 }
79e53945 5671
5dc5298b
PZ		 5672 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5673 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5674
3b117c8f 5675 intel_crtc->config.cpu_transcoder = pipe;
6cf86a5e 5676
de13a2e3
PZ		 5677 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5678 &has_reduced_clock, &reduced_clock);
5679 if (!ok) {
5680 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5681 return -EINVAL;
79e53945 5682 }
f47709a9
DV		 5683 /* Compat-code for transition, will disappear. */
5684 if (!intel_crtc->config.clock_set) {
5685 intel_crtc->config.dpll.n = clock.n;
5686 intel_crtc->config.dpll.m1 = clock.m1;
5687 intel_crtc->config.dpll.m2 = clock.m2;
5688 intel_crtc->config.dpll.p1 = clock.p1;
5689 intel_crtc->config.dpll.p2 = clock.p2;
5690 }
79e53945 5691
de13a2e3
PZ		 5692 /* Ensure that the cursor is valid for the new mode before changing... */
5693 intel_crtc_update_cursor(crtc, true);
5694
84f44ce7 5695 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
79e53945
JB		 5696 drm_mode_debug_printmodeline(mode);
5697
5dc5298b 5698 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5699 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5700 struct intel_pch_pll *pll;
4b645f14 5701
7429e9d4 5702 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5703 if (has_reduced_clock)
7429e9d4 5704 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5705
7429e9d4 5706 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5707 &fp, &reduced_clock,
5708 has_reduced_clock ? &fp2 : NULL);
5709
ee7b9f93
JB		 5710 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5711 if (pll == NULL) {
84f44ce7
VS		 5712 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5713 pipe_name(pipe));
4b645f14
JB		 5714 return -EINVAL;
5715 }
ee7b9f93
JB		 5716 } else
5717 intel_put_pch_pll(intel_crtc);
79e53945 5718
03afc4a2
DV		 5719 if (intel_crtc->config.has_dp_encoder)
5720 intel_dp_set_m_n(intel_crtc);
79e53945 5721
dafd226c
DV		 5722 for_each_encoder_on_crtc(dev, crtc, encoder)
5723 if (encoder->pre_pll_enable)
5724 encoder->pre_pll_enable(encoder);
79e53945 5725
ee7b9f93
JB		 5726 if (intel_crtc->pch_pll) {
5727 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5728
32f9d658 5729 /* Wait for the clocks to stabilize. */
ee7b9f93 5730 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5731 udelay(150);
5732
8febb297
EA		 5733 /* The pixel multiplier can only be updated once the
5734 * DPLL is enabled and the clocks are stable.
5735 *
5736 * So write it again.
5737 */
ee7b9f93 5738 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5739 }
79e53945 5740
5eddb70b 5741 intel_crtc->lowfreq_avail = false;
ee7b9f93 5742 if (intel_crtc->pch_pll) {
4b645f14 5743 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5744 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5745 intel_crtc->lowfreq_avail = true;
4b645f14 5746 } else {
ee7b9f93 5747 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5748 }
5749 }
5750
b0e77b9c 5751 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5752
01a415fd
DV		 5753 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5754 * ironlake_check_fdi_lanes. */
33d29b14 5755 intel_crtc->config.fdi_lanes = 0;
6cf86a5e
DV		 5756 if (intel_crtc->config.has_pch_encoder)
5757 ironlake_fdi_set_m_n(crtc);
2c07245f 5758
01a415fd 5759 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5760
6ff93609 5761 ironlake_set_pipeconf(crtc);
79e53945 5762
a1f9e77e
PZ		 5763 /* Set up the display plane register */
5764 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5765 POSTING_READ(DSPCNTR(plane));
79e53945 5766
94352cf9 5767 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5768
5769 intel_update_watermarks(dev);
5770
1f8eeabf
ED		 5771 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5772
01a415fd 5773 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5774}
5775
0e8ffe1b
DV		 5776static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5777 struct intel_crtc_config *pipe_config)
5778{
5779 struct drm_device *dev = crtc->base.dev;
5780 struct drm_i915_private *dev_priv = dev->dev_private;
5781 uint32_t tmp;
5782
5783 tmp = I915_READ(PIPECONF(crtc->pipe));
5784 if (!(tmp & PIPECONF_ENABLE))
5785 return false;
5786
88adfff1
DV		 5787 if (I915_READ(TRANSCONF(crtc->pipe)) & TRANS_ENABLE)
5788 pipe_config->has_pch_encoder = true;
5789
0e8ffe1b
DV		 5790 return true;
5791}
5792
d6dd9eb1
DV		 5793static void haswell_modeset_global_resources(struct drm_device *dev)
5794{
5795 struct drm_i915_private *dev_priv = dev->dev_private;
5796 bool enable = false;
5797 struct intel_crtc *crtc;
5798 struct intel_encoder *encoder;
5799
5800 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5801 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5802 enable = true;
5803 /* XXX: Should check for edp transcoder here, but thanks to init
5804 * sequence that's not yet available. Just in case desktop eDP
5805 * on PORT D is possible on haswell, too. */
b074cec8
JB		 5806 /* Even the eDP panel fitter is outside the always-on well. */
5807 if (I915_READ(PF_WIN_SZ(crtc->pipe)))
5808 enable = true;
d6dd9eb1
DV		 5809 }
5810
5811 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5812 base.head) {
5813 if (encoder->type != INTEL_OUTPUT_EDP &&
5814 encoder->connectors_active)
5815 enable = true;
5816 }
5817
d6dd9eb1
DV		 5818 intel_set_power_well(dev, enable);
5819}
5820
09b4ddf9 5821static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5822 int x, int y,
5823 struct drm_framebuffer *fb)
5824{
5825 struct drm_device *dev = crtc->dev;
5826 struct drm_i915_private *dev_priv = dev->dev_private;
5827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5828 struct drm_display_mode *adjusted_mode =
5829 &intel_crtc->config.adjusted_mode;
5830 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5831 int pipe = intel_crtc->pipe;
5832 int plane = intel_crtc->plane;
5833 int num_connectors = 0;
8b47047b 5834 bool is_cpu_edp = false;
09b4ddf9 5835 struct intel_encoder *encoder;
09b4ddf9 5836 int ret;
09b4ddf9
PZ		 5837
5838 for_each_encoder_on_crtc(dev, crtc, encoder) {
5839 switch (encoder->type) {
09b4ddf9 5840 case INTEL_OUTPUT_EDP:
09b4ddf9
PZ		 5841 if (!intel_encoder_is_pch_edp(&encoder->base))
5842 is_cpu_edp = true;
5843 break;
5844 }
5845
5846 num_connectors++;
5847 }
5848
bba2181c 5849 if (is_cpu_edp)
3b117c8f 5850 intel_crtc->config.cpu_transcoder = TRANSCODER_EDP;
bba2181c 5851 else
3b117c8f 5852 intel_crtc->config.cpu_transcoder = pipe;
bba2181c 5853
5dc5298b
PZ		 5854 /* We are not sure yet this won't happen. */
5855 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5856 INTEL_PCH_TYPE(dev));
5857
5858 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5859 num_connectors, pipe_name(pipe));
5860
3b117c8f 5861 WARN_ON(I915_READ(PIPECONF(intel_crtc->config.cpu_transcoder)) &
1ce42920
PZ		 5862 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5863
5864 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5865
6441ab5f
PZ		 5866 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5867 return -EINVAL;
5868
09b4ddf9
PZ		 5869 /* Ensure that the cursor is valid for the new mode before changing... */
5870 intel_crtc_update_cursor(crtc, true);
5871
84f44ce7 5872 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe_name(pipe));
09b4ddf9
PZ		 5873 drm_mode_debug_printmodeline(mode);
5874
03afc4a2
DV		 5875 if (intel_crtc->config.has_dp_encoder)
5876 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5877
5878 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5879
5880 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5881
6cf86a5e
DV		 5882 if (intel_crtc->config.has_pch_encoder)
5883 ironlake_fdi_set_m_n(crtc);
09b4ddf9 5884
6ff93609 5885 haswell_set_pipeconf(crtc);
09b4ddf9 5886
50f3b016 5887 intel_set_pipe_csc(crtc);
86d3efce 5888
09b4ddf9 5889 /* Set up the display plane register */
86d3efce 5890 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5891 POSTING_READ(DSPCNTR(plane));
5892
5893 ret = intel_pipe_set_base(crtc, x, y, fb);
5894
5895 intel_update_watermarks(dev);
5896
5897 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5898
1f803ee5 5899 return ret;
79e53945
JB		 5900}
5901
0e8ffe1b
DV		 5902static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5903 struct intel_crtc_config *pipe_config)
5904{
5905 struct drm_device *dev = crtc->base.dev;
5906 struct drm_i915_private *dev_priv = dev->dev_private;
2bfce950 5907 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
0e8ffe1b
DV		 5908 uint32_t tmp;
5909
2bfce950
PZ		 5910 if (!intel_using_power_well(dev_priv->dev) &&
5911 cpu_transcoder != TRANSCODER_EDP)
5912 return false;
5913
5914 tmp = I915_READ(PIPECONF(cpu_transcoder));
0e8ffe1b
DV		 5915 if (!(tmp & PIPECONF_ENABLE))
5916 return false;
5917
88adfff1 5918 /*
f196e6be 5919 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 5920 * DDI E. So just check whether this pipe is wired to DDI E and whether
5921 * the PCH transcoder is on.
5922 */
f196e6be 5923 tmp = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder));
88adfff1
DV		 5924 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
5925 I915_READ(TRANSCONF(PIPE_A)) & TRANS_ENABLE)
5926 pipe_config->has_pch_encoder = true;
5927
0e8ffe1b
DV		 5928 return true;
5929}
5930
f564048e 5931static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5932 int x, int y,
94352cf9 5933 struct drm_framebuffer *fb)
f564048e
EA		 5934{
5935 struct drm_device *dev = crtc->dev;
5936 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5937 struct drm_encoder_helper_funcs *encoder_funcs;
5938 struct intel_encoder *encoder;
0b701d27 5939 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5940 struct drm_display_mode *adjusted_mode =
5941 &intel_crtc->config.adjusted_mode;
5942 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 5943 int pipe = intel_crtc->pipe;
f564048e
EA		 5944 int ret;
5945
0b701d27 5946 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5947
b8cecdf5
DV		 5948 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
5949
79e53945 5950 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5951
9256aa19
DV		 5952 if (ret != 0)
5953 return ret;
5954
5955 for_each_encoder_on_crtc(dev, crtc, encoder) {
5956 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5957 encoder->base.base.id,
5958 drm_get_encoder_name(&encoder->base),
5959 mode->base.id, mode->name);
6cc5f341
DV		 5960 if (encoder->mode_set) {
5961 encoder->mode_set(encoder);
5962 } else {
5963 encoder_funcs = encoder->base.helper_private;
5964 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5965 }
9256aa19
DV		 5966 }
5967
5968 return 0;
79e53945
JB		 5969}
5970
3a9627f4
WF		 5971static bool intel_eld_uptodate(struct drm_connector *connector,
5972 int reg_eldv, uint32_t bits_eldv,
5973 int reg_elda, uint32_t bits_elda,
5974 int reg_edid)
5975{
5976 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5977 uint8_t *eld = connector->eld;
5978 uint32_t i;
5979
5980 i = I915_READ(reg_eldv);
5981 i &= bits_eldv;
5982
5983 if (!eld[0])
5984 return !i;
5985
5986 if (!i)
5987 return false;
5988
5989 i = I915_READ(reg_elda);
5990 i &= ~bits_elda;
5991 I915_WRITE(reg_elda, i);
5992
5993 for (i = 0; i < eld[2]; i++)
5994 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5995 return false;
5996
5997 return true;
5998}
5999
e0dac65e
WF		 6000static void g4x_write_eld(struct drm_connector *connector,
6001 struct drm_crtc *crtc)
6002{
6003 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6004 uint8_t *eld = connector->eld;
6005 uint32_t eldv;
6006 uint32_t len;
6007 uint32_t i;
6008
6009 i = I915_READ(G4X_AUD_VID_DID);
6010
6011 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6012 eldv = G4X_ELDV_DEVCL_DEVBLC;
6013 else
6014 eldv = G4X_ELDV_DEVCTG;
6015
3a9627f4
WF		 6016 if (intel_eld_uptodate(connector,
6017 G4X_AUD_CNTL_ST, eldv,
6018 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6019 G4X_HDMIW_HDMIEDID))
6020 return;
6021
e0dac65e
WF		 6022 i = I915_READ(G4X_AUD_CNTL_ST);
6023 i &= ~(eldv | G4X_ELD_ADDR);
6024 len = (i >> 9) & 0x1f; /* ELD buffer size */
6025 I915_WRITE(G4X_AUD_CNTL_ST, i);
6026
6027 if (!eld[0])
6028 return;
6029
6030 len = min_t(uint8_t, eld[2], len);
6031 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6032 for (i = 0; i < len; i++)
6033 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6034
6035 i = I915_READ(G4X_AUD_CNTL_ST);
6036 i |= eldv;
6037 I915_WRITE(G4X_AUD_CNTL_ST, i);
6038}
6039
83358c85
WX		 6040static void haswell_write_eld(struct drm_connector *connector,
6041 struct drm_crtc *crtc)
6042{
6043 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6044 uint8_t *eld = connector->eld;
6045 struct drm_device *dev = crtc->dev;
7b9f35a6 6046 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6047 uint32_t eldv;
6048 uint32_t i;
6049 int len;
6050 int pipe = to_intel_crtc(crtc)->pipe;
6051 int tmp;
6052
6053 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6054 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6055 int aud_config = HSW_AUD_CFG(pipe);
6056 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6057
6058
6059 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6060
6061 /* Audio output enable */
6062 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6063 tmp = I915_READ(aud_cntrl_st2);
6064 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6065 I915_WRITE(aud_cntrl_st2, tmp);
6066
6067 /* Wait for 1 vertical blank */
6068 intel_wait_for_vblank(dev, pipe);
6069
6070 /* Set ELD valid state */
6071 tmp = I915_READ(aud_cntrl_st2);
6072 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6073 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6074 I915_WRITE(aud_cntrl_st2, tmp);
6075 tmp = I915_READ(aud_cntrl_st2);
6076 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6077
6078 /* Enable HDMI mode */
6079 tmp = I915_READ(aud_config);
6080 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6081 /* clear N_programing_enable and N_value_index */
6082 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6083 I915_WRITE(aud_config, tmp);
6084
6085 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6086
6087 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6088 intel_crtc->eld_vld = true;
83358c85
WX		 6089
6090 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6091 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6092 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6093 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6094 } else
6095 I915_WRITE(aud_config, 0);
6096
6097 if (intel_eld_uptodate(connector,
6098 aud_cntrl_st2, eldv,
6099 aud_cntl_st, IBX_ELD_ADDRESS,
6100 hdmiw_hdmiedid))
6101 return;
6102
6103 i = I915_READ(aud_cntrl_st2);
6104 i &= ~eldv;
6105 I915_WRITE(aud_cntrl_st2, i);
6106
6107 if (!eld[0])
6108 return;
6109
6110 i = I915_READ(aud_cntl_st);
6111 i &= ~IBX_ELD_ADDRESS;
6112 I915_WRITE(aud_cntl_st, i);
6113 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6114 DRM_DEBUG_DRIVER("port num:%d\n", i);
6115
6116 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6117 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6118 for (i = 0; i < len; i++)
6119 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6120
6121 i = I915_READ(aud_cntrl_st2);
6122 i |= eldv;
6123 I915_WRITE(aud_cntrl_st2, i);
6124
6125}
6126
e0dac65e
WF		 6127static void ironlake_write_eld(struct drm_connector *connector,
6128 struct drm_crtc *crtc)
6129{
6130 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6131 uint8_t *eld = connector->eld;
6132 uint32_t eldv;
6133 uint32_t i;
6134 int len;
6135 int hdmiw_hdmiedid;
b6daa025 6136 int aud_config;
e0dac65e
WF		 6137 int aud_cntl_st;
6138 int aud_cntrl_st2;
9b138a83 6139 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6140
b3f33cbf 6141 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6142 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6143 aud_config = IBX_AUD_CFG(pipe);
6144 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6145 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6146 } else {
9b138a83
WX		 6147 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6148 aud_config = CPT_AUD_CFG(pipe);
6149 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6150 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6151 }
6152
9b138a83 6153 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6154
6155 i = I915_READ(aud_cntl_st);
9b138a83 6156 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6157 if (!i) {
6158 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6159 /* operate blindly on all ports */
1202b4c6
WF		 6160 eldv = IBX_ELD_VALIDB;
6161 eldv |= IBX_ELD_VALIDB << 4;
6162 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6163 } else {
2582a850 6164 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6165 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6166 }
6167
3a9627f4
WF		 6168 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6169 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6170 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6171 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6172 } else
6173 I915_WRITE(aud_config, 0);
e0dac65e 6174
3a9627f4
WF		 6175 if (intel_eld_uptodate(connector,
6176 aud_cntrl_st2, eldv,
6177 aud_cntl_st, IBX_ELD_ADDRESS,
6178 hdmiw_hdmiedid))
6179 return;
6180
e0dac65e
WF		 6181 i = I915_READ(aud_cntrl_st2);
6182 i &= ~eldv;
6183 I915_WRITE(aud_cntrl_st2, i);
6184
6185 if (!eld[0])
6186 return;
6187
e0dac65e 6188 i = I915_READ(aud_cntl_st);
1202b4c6 6189 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6190 I915_WRITE(aud_cntl_st, i);
6191
6192 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6193 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6194 for (i = 0; i < len; i++)
6195 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6196
6197 i = I915_READ(aud_cntrl_st2);
6198 i |= eldv;
6199 I915_WRITE(aud_cntrl_st2, i);
6200}
6201
6202void intel_write_eld(struct drm_encoder *encoder,
6203 struct drm_display_mode *mode)
6204{
6205 struct drm_crtc *crtc = encoder->crtc;
6206 struct drm_connector *connector;
6207 struct drm_device *dev = encoder->dev;
6208 struct drm_i915_private *dev_priv = dev->dev_private;
6209
6210 connector = drm_select_eld(encoder, mode);
6211 if (!connector)
6212 return;
6213
6214 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6215 connector->base.id,
6216 drm_get_connector_name(connector),
6217 connector->encoder->base.id,
6218 drm_get_encoder_name(connector->encoder));
6219
6220 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6221
6222 if (dev_priv->display.write_eld)
6223 dev_priv->display.write_eld(connector, crtc);
6224}
6225
79e53945
JB		 6226/** Loads the palette/gamma unit for the CRTC with the prepared values */
6227void intel_crtc_load_lut(struct drm_crtc *crtc)
6228{
6229 struct drm_device *dev = crtc->dev;
6230 struct drm_i915_private *dev_priv = dev->dev_private;
6231 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6232 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6233 int i;
6234
6235 /* The clocks have to be on to load the palette. */
aed3f09d 6236 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6237 return;
6238
f2b115e6 6239 /* use legacy palette for Ironlake */
bad720ff 6240 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6241 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6242
79e53945
JB		 6243 for (i = 0; i < 256; i++) {
6244 I915_WRITE(palreg + 4 * i,
6245 (intel_crtc->lut_r[i] << 16) |
6246 (intel_crtc->lut_g[i] << 8) |
6247 intel_crtc->lut_b[i]);
6248 }
6249}
6250
560b85bb
CW		 6251static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6252{
6253 struct drm_device *dev = crtc->dev;
6254 struct drm_i915_private *dev_priv = dev->dev_private;
6255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6256 bool visible = base != 0;
6257 u32 cntl;
6258
6259 if (intel_crtc->cursor_visible == visible)
6260 return;
6261
9db4a9c7 6262 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6263 if (visible) {
6264 /* On these chipsets we can only modify the base whilst
6265 * the cursor is disabled.
6266 */
9db4a9c7 6267 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6268
6269 cntl &= ~(CURSOR_FORMAT_MASK);
6270 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6271 cntl |= CURSOR_ENABLE |
6272 CURSOR_GAMMA_ENABLE |
6273 CURSOR_FORMAT_ARGB;
6274 } else
6275 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6276 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6277
6278 intel_crtc->cursor_visible = visible;
6279}
6280
6281static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6282{
6283 struct drm_device *dev = crtc->dev;
6284 struct drm_i915_private *dev_priv = dev->dev_private;
6285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6286 int pipe = intel_crtc->pipe;
6287 bool visible = base != 0;
6288
6289 if (intel_crtc->cursor_visible != visible) {
548f245b 6290 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6291 if (base) {
6292 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6293 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6294 cntl |= pipe << 28; /* Connect to correct pipe */
6295 } else {
6296 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6297 cntl |= CURSOR_MODE_DISABLE;
6298 }
9db4a9c7 6299 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6300
6301 intel_crtc->cursor_visible = visible;
6302 }
6303 /* and commit changes on next vblank */
9db4a9c7 6304 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6305}
6306
65a21cd6
JB		 6307static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6308{
6309 struct drm_device *dev = crtc->dev;
6310 struct drm_i915_private *dev_priv = dev->dev_private;
6311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6312 int pipe = intel_crtc->pipe;
6313 bool visible = base != 0;
6314
6315 if (intel_crtc->cursor_visible != visible) {
6316 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6317 if (base) {
6318 cntl &= ~CURSOR_MODE;
6319 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6320 } else {
6321 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6322 cntl |= CURSOR_MODE_DISABLE;
6323 }
86d3efce
VS		 6324 if (IS_HASWELL(dev))
6325 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6326 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6327
6328 intel_crtc->cursor_visible = visible;
6329 }
6330 /* and commit changes on next vblank */
6331 I915_WRITE(CURBASE_IVB(pipe), base);
6332}
6333
cda4b7d3 6334/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6335static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6336 bool on)
cda4b7d3
CW		 6337{
6338 struct drm_device *dev = crtc->dev;
6339 struct drm_i915_private *dev_priv = dev->dev_private;
6340 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6341 int pipe = intel_crtc->pipe;
6342 int x = intel_crtc->cursor_x;
6343 int y = intel_crtc->cursor_y;
560b85bb 6344 u32 base, pos;
cda4b7d3
CW		 6345 bool visible;
6346
6347 pos = 0;
6348
6b383a7f 6349 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6350 base = intel_crtc->cursor_addr;
6351 if (x > (int) crtc->fb->width)
6352 base = 0;
6353
6354 if (y > (int) crtc->fb->height)
6355 base = 0;
6356 } else
6357 base = 0;
6358
6359 if (x < 0) {
6360 if (x + intel_crtc->cursor_width < 0)
6361 base = 0;
6362
6363 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6364 x = -x;
6365 }
6366 pos |= x << CURSOR_X_SHIFT;
6367
6368 if (y < 0) {
6369 if (y + intel_crtc->cursor_height < 0)
6370 base = 0;
6371
6372 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6373 y = -y;
6374 }
6375 pos |= y << CURSOR_Y_SHIFT;
6376
6377 visible = base != 0;
560b85bb 6378 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6379 return;
6380
0cd83aa9 6381 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6382 I915_WRITE(CURPOS_IVB(pipe), pos);
6383 ivb_update_cursor(crtc, base);
6384 } else {
6385 I915_WRITE(CURPOS(pipe), pos);
6386 if (IS_845G(dev) || IS_I865G(dev))
6387 i845_update_cursor(crtc, base);
6388 else
6389 i9xx_update_cursor(crtc, base);
6390 }
cda4b7d3
CW		 6391}
6392
79e53945 6393static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6394 struct drm_file *file,
79e53945
JB		 6395 uint32_t handle,
6396 uint32_t width, uint32_t height)
6397{
6398 struct drm_device *dev = crtc->dev;
6399 struct drm_i915_private *dev_priv = dev->dev_private;
6400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6401 struct drm_i915_gem_object *obj;
cda4b7d3 6402 uint32_t addr;
3f8bc370 6403 int ret;
79e53945 6404
79e53945
JB		 6405 /* if we want to turn off the cursor ignore width and height */
6406 if (!handle) {
28c97730 6407 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6408 addr = 0;
05394f39 6409 obj = NULL;
5004417d 6410 mutex_lock(&dev->struct_mutex);
3f8bc370 6411 goto finish;
79e53945
JB		 6412 }
6413
6414 /* Currently we only support 64x64 cursors */
6415 if (width != 64 || height != 64) {
6416 DRM_ERROR("we currently only support 64x64 cursors\n");
6417 return -EINVAL;
6418 }
6419
05394f39 6420 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6421 if (&obj->base == NULL)
79e53945
JB		 6422 return -ENOENT;
6423
05394f39 6424 if (obj->base.size < width * height * 4) {
79e53945 6425 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6426 ret = -ENOMEM;
6427 goto fail;
79e53945
JB		 6428 }
6429
71acb5eb 6430 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6431 mutex_lock(&dev->struct_mutex);
b295d1b6 6432 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6433 unsigned alignment;
6434
d9e86c0e
CW		 6435 if (obj->tiling_mode) {
6436 DRM_ERROR("cursor cannot be tiled\n");
6437 ret = -EINVAL;
6438 goto fail_locked;
6439 }
6440
693db184
CW		 6441 /* Note that the w/a also requires 2 PTE of padding following
6442 * the bo. We currently fill all unused PTE with the shadow
6443 * page and so we should always have valid PTE following the
6444 * cursor preventing the VT-d warning.
6445 */
6446 alignment = 0;
6447 if (need_vtd_wa(dev))
6448 alignment = 64*1024;
6449
6450 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6451 if (ret) {
6452 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6453 goto fail_locked;
e7b526bb
CW		 6454 }
6455
d9e86c0e
CW		 6456 ret = i915_gem_object_put_fence(obj);
6457 if (ret) {
2da3b9b9 6458 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6459 goto fail_unpin;
6460 }
6461
05394f39 6462 addr = obj->gtt_offset;
71acb5eb 6463 } else {
6eeefaf3 6464 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6465 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6466 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6467 align);
71acb5eb
DA		 6468 if (ret) {
6469 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6470 goto fail_locked;
71acb5eb 6471 }
05394f39 6472 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6473 }
6474
a6c45cf0 6475 if (IS_GEN2(dev))
14b60391
JB		 6476 I915_WRITE(CURSIZE, (height << 12) | width);
6477
3f8bc370 6478 finish:
3f8bc370 6479 if (intel_crtc->cursor_bo) {
b295d1b6 6480 if (dev_priv->info->cursor_needs_physical) {
05394f39 6481 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6482 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6483 } else
6484 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6485 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6486 }
80824003 6487
7f9872e0 6488 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6489
6490 intel_crtc->cursor_addr = addr;
05394f39 6491 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6492 intel_crtc->cursor_width = width;
6493 intel_crtc->cursor_height = height;
6494
6b383a7f 6495 intel_crtc_update_cursor(crtc, true);
3f8bc370 6496
79e53945 6497 return 0;
e7b526bb 6498fail_unpin:
05394f39 6499 i915_gem_object_unpin(obj);
7f9872e0 6500fail_locked:
34b8686e 6501 mutex_unlock(&dev->struct_mutex);
bc9025bd 6502fail:
05394f39 6503 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6504 return ret;
79e53945
JB		 6505}
6506
6507static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6508{
79e53945 6509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6510
cda4b7d3
CW		 6511 intel_crtc->cursor_x = x;
6512 intel_crtc->cursor_y = y;
652c393a 6513
6b383a7f 6514 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6515
6516 return 0;
6517}
6518
6519/** Sets the color ramps on behalf of RandR */
6520void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6521 u16 blue, int regno)
6522{
6523 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6524
6525 intel_crtc->lut_r[regno] = red >> 8;
6526 intel_crtc->lut_g[regno] = green >> 8;
6527 intel_crtc->lut_b[regno] = blue >> 8;
6528}
6529
b8c00ac5
DA		 6530void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6531 u16 *blue, int regno)
6532{
6533 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6534
6535 *red = intel_crtc->lut_r[regno] << 8;
6536 *green = intel_crtc->lut_g[regno] << 8;
6537 *blue = intel_crtc->lut_b[regno] << 8;
6538}
6539
79e53945 6540static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6541 u16 *blue, uint32_t start, uint32_t size)
79e53945 6542{
7203425a 6543 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6545
7203425a 6546 for (i = start; i < end; i++) {
79e53945
JB		 6547 intel_crtc->lut_r[i] = red[i] >> 8;
6548 intel_crtc->lut_g[i] = green[i] >> 8;
6549 intel_crtc->lut_b[i] = blue[i] >> 8;
6550 }
6551
6552 intel_crtc_load_lut(crtc);
6553}
6554
79e53945
JB		 6555/* VESA 640x480x72Hz mode to set on the pipe */
6556static struct drm_display_mode load_detect_mode = {
6557 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6558 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6559};
6560
d2dff872
CW		 6561static struct drm_framebuffer *
6562intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6563 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6564 struct drm_i915_gem_object *obj)
6565{
6566 struct intel_framebuffer *intel_fb;
6567 int ret;
6568
6569 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6570 if (!intel_fb) {
6571 drm_gem_object_unreference_unlocked(&obj->base);
6572 return ERR_PTR(-ENOMEM);
6573 }
6574
6575 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6576 if (ret) {
6577 drm_gem_object_unreference_unlocked(&obj->base);
6578 kfree(intel_fb);
6579 return ERR_PTR(ret);
6580 }
6581
6582 return &intel_fb->base;
6583}
6584
6585static u32
6586intel_framebuffer_pitch_for_width(int width, int bpp)
6587{
6588 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6589 return ALIGN(pitch, 64);
6590}
6591
6592static u32
6593intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6594{
6595 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6596 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6597}
6598
6599static struct drm_framebuffer *
6600intel_framebuffer_create_for_mode(struct drm_device *dev,
6601 struct drm_display_mode *mode,
6602 int depth, int bpp)
6603{
6604 struct drm_i915_gem_object *obj;
0fed39bd 6605 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6606
6607 obj = i915_gem_alloc_object(dev,
6608 intel_framebuffer_size_for_mode(mode, bpp));
6609 if (obj == NULL)
6610 return ERR_PTR(-ENOMEM);
6611
6612 mode_cmd.width = mode->hdisplay;
6613 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6614 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6615 bpp);
5ca0c34a 6616 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6617
6618 return intel_framebuffer_create(dev, &mode_cmd, obj);
6619}
6620
6621static struct drm_framebuffer *
6622mode_fits_in_fbdev(struct drm_device *dev,
6623 struct drm_display_mode *mode)
6624{
6625 struct drm_i915_private *dev_priv = dev->dev_private;
6626 struct drm_i915_gem_object *obj;
6627 struct drm_framebuffer *fb;
6628
6629 if (dev_priv->fbdev == NULL)
6630 return NULL;
6631
6632 obj = dev_priv->fbdev->ifb.obj;
6633 if (obj == NULL)
6634 return NULL;
6635
6636 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6637 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6638 fb->bits_per_pixel))
d2dff872
CW		 6639 return NULL;
6640
01f2c773 6641 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6642 return NULL;
6643
6644 return fb;
6645}
6646
d2434ab7 6647bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6648 struct drm_display_mode *mode,
8261b191 6649 struct intel_load_detect_pipe *old)
79e53945
JB		 6650{
6651 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6652 struct intel_encoder *intel_encoder =
6653 intel_attached_encoder(connector);
79e53945 6654 struct drm_crtc *possible_crtc;
4ef69c7a 6655 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6656 struct drm_crtc *crtc = NULL;
6657 struct drm_device *dev = encoder->dev;
94352cf9 6658 struct drm_framebuffer *fb;
79e53945
JB		 6659 int i = -1;
6660
d2dff872
CW		 6661 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6662 connector->base.id, drm_get_connector_name(connector),
6663 encoder->base.id, drm_get_encoder_name(encoder));
6664
79e53945
JB		 6665 /*
6666 * Algorithm gets a little messy:
7a5e4805 6667 *
79e53945
JB		 6668 * - if the connector already has an assigned crtc, use it (but make
6669 * sure it's on first)
7a5e4805 6670 *
79e53945
JB		 6671 * - try to find the first unused crtc that can drive this connector,
6672 * and use that if we find one
79e53945
JB		 6673 */
6674
6675 /* See if we already have a CRTC for this connector */
6676 if (encoder->crtc) {
6677 crtc = encoder->crtc;
8261b191 6678
7b24056b
DV		 6679 mutex_lock(&crtc->mutex);
6680
24218aac 6681 old->dpms_mode = connector->dpms;
8261b191
CW		 6682 old->load_detect_temp = false;
6683
6684 /* Make sure the crtc and connector are running */
24218aac
DV		 6685 if (connector->dpms != DRM_MODE_DPMS_ON)
6686 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6687
7173188d 6688 return true;
79e53945
JB		 6689 }
6690
6691 /* Find an unused one (if possible) */
6692 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6693 i++;
6694 if (!(encoder->possible_crtcs & (1 << i)))
6695 continue;
6696 if (!possible_crtc->enabled) {
6697 crtc = possible_crtc;
6698 break;
6699 }
79e53945
JB		 6700 }
6701
6702 /*
6703 * If we didn't find an unused CRTC, don't use any.
6704 */
6705 if (!crtc) {
7173188d
CW		 6706 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6707 return false;
79e53945
JB		 6708 }
6709
7b24056b 6710 mutex_lock(&crtc->mutex);
fc303101
DV		 6711 intel_encoder->new_crtc = to_intel_crtc(crtc);
6712 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6713
6714 intel_crtc = to_intel_crtc(crtc);
24218aac 6715 old->dpms_mode = connector->dpms;
8261b191 6716 old->load_detect_temp = true;
d2dff872 6717 old->release_fb = NULL;
79e53945 6718
6492711d
CW		 6719 if (!mode)
6720 mode = &load_detect_mode;
79e53945 6721
d2dff872
CW		 6722 /* We need a framebuffer large enough to accommodate all accesses
6723 * that the plane may generate whilst we perform load detection.
6724 * We can not rely on the fbcon either being present (we get called
6725 * during its initialisation to detect all boot displays, or it may
6726 * not even exist) or that it is large enough to satisfy the
6727 * requested mode.
6728 */
94352cf9
DV		 6729 fb = mode_fits_in_fbdev(dev, mode);
6730 if (fb == NULL) {
d2dff872 6731 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6732 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6733 old->release_fb = fb;
d2dff872
CW		 6734 } else
6735 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6736 if (IS_ERR(fb)) {
d2dff872 6737 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6738 mutex_unlock(&crtc->mutex);
0e8b3d3e 6739 return false;
79e53945 6740 }
79e53945 6741
c0c36b94 6742 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6743 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6744 if (old->release_fb)
6745 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6746 mutex_unlock(&crtc->mutex);
0e8b3d3e 6747 return false;
79e53945 6748 }
7173188d 6749
79e53945 6750 /* let the connector get through one full cycle before testing */
9d0498a2 6751 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6752 return true;
79e53945
JB		 6753}
6754
d2434ab7 6755void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6756 struct intel_load_detect_pipe *old)
79e53945 6757{
d2434ab7
DV		 6758 struct intel_encoder *intel_encoder =
6759 intel_attached_encoder(connector);
4ef69c7a 6760 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6761 struct drm_crtc *crtc = encoder->crtc;
79e53945 6762
d2dff872
CW		 6763 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6764 connector->base.id, drm_get_connector_name(connector),
6765 encoder->base.id, drm_get_encoder_name(encoder));
6766
8261b191 6767 if (old->load_detect_temp) {
fc303101
DV		 6768 to_intel_connector(connector)->new_encoder = NULL;
6769 intel_encoder->new_crtc = NULL;
6770 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6771
36206361
DV		 6772 if (old->release_fb) {
6773 drm_framebuffer_unregister_private(old->release_fb);
6774 drm_framebuffer_unreference(old->release_fb);
6775 }
d2dff872 6776
67c96400 6777 mutex_unlock(&crtc->mutex);
0622a53c 6778 return;
79e53945
JB		 6779 }
6780
c751ce4f 6781 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6782 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6783 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6784
6785 mutex_unlock(&crtc->mutex);
79e53945
JB		 6786}
6787
6788/* Returns the clock of the currently programmed mode of the given pipe. */
6789static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6790{
6791 struct drm_i915_private *dev_priv = dev->dev_private;
6792 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6793 int pipe = intel_crtc->pipe;
548f245b 6794 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6795 u32 fp;
6796 intel_clock_t clock;
6797
6798 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6799 fp = I915_READ(FP0(pipe));
79e53945 6800 else
39adb7a5 6801 fp = I915_READ(FP1(pipe));
79e53945
JB		 6802
6803 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6804 if (IS_PINEVIEW(dev)) {
6805 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6806 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6807 } else {
6808 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6809 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6810 }
6811
a6c45cf0 6812 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6813 if (IS_PINEVIEW(dev))
6814 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6815 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6816 else
6817 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6818 DPLL_FPA01_P1_POST_DIV_SHIFT);
6819
6820 switch (dpll & DPLL_MODE_MASK) {
6821 case DPLLB_MODE_DAC_SERIAL:
6822 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6823 5 : 10;
6824 break;
6825 case DPLLB_MODE_LVDS:
6826 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6827 7 : 14;
6828 break;
6829 default:
28c97730 6830 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6831 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6832 return 0;
6833 }
6834
6835 /* XXX: Handle the 100Mhz refclk */
2177832f 6836 intel_clock(dev, 96000, &clock);
79e53945
JB		 6837 } else {
6838 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6839
6840 if (is_lvds) {
6841 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6842 DPLL_FPA01_P1_POST_DIV_SHIFT);
6843 clock.p2 = 14;
6844
6845 if ((dpll & PLL_REF_INPUT_MASK) ==
6846 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6847 /* XXX: might not be 66MHz */
2177832f 6848 intel_clock(dev, 66000, &clock);
79e53945 6849 } else
2177832f 6850 intel_clock(dev, 48000, &clock);
79e53945
JB		 6851 } else {
6852 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6853 clock.p1 = 2;
6854 else {
6855 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6856 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6857 }
6858 if (dpll & PLL_P2_DIVIDE_BY_4)
6859 clock.p2 = 4;
6860 else
6861 clock.p2 = 2;
6862
2177832f 6863 intel_clock(dev, 48000, &clock);
79e53945
JB		 6864 }
6865 }
6866
6867 /* XXX: It would be nice to validate the clocks, but we can't reuse
6868 * i830PllIsValid() because it relies on the xf86_config connector
6869 * configuration being accurate, which it isn't necessarily.
6870 */
6871
6872 return clock.dot;
6873}
6874
6875/** Returns the currently programmed mode of the given pipe. */
6876struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6877 struct drm_crtc *crtc)
6878{
548f245b 6879 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 6881 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 6882 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6883 int htot = I915_READ(HTOTAL(cpu_transcoder));
6884 int hsync = I915_READ(HSYNC(cpu_transcoder));
6885 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6886 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6887
6888 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6889 if (!mode)
6890 return NULL;
6891
6892 mode->clock = intel_crtc_clock_get(dev, crtc);
6893 mode->hdisplay = (htot & 0xffff) + 1;
6894 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6895 mode->hsync_start = (hsync & 0xffff) + 1;
6896 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6897 mode->vdisplay = (vtot & 0xffff) + 1;
6898 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6899 mode->vsync_start = (vsync & 0xffff) + 1;
6900 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6901
6902 drm_mode_set_name(mode);
79e53945
JB		 6903
6904 return mode;
6905}
6906
3dec0095 6907static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6908{
6909 struct drm_device *dev = crtc->dev;
6910 drm_i915_private_t *dev_priv = dev->dev_private;
6911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6912 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6913 int dpll_reg = DPLL(pipe);
6914 int dpll;
652c393a 6915
bad720ff 6916 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6917 return;
6918
6919 if (!dev_priv->lvds_downclock_avail)
6920 return;
6921
dbdc6479 6922 dpll = I915_READ(dpll_reg);
652c393a 6923 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6924 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6925
8ac5a6d5 6926 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6927
6928 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6929 I915_WRITE(dpll_reg, dpll);
9d0498a2 6930 intel_wait_for_vblank(dev, pipe);
dbdc6479 6931
652c393a
JB		 6932 dpll = I915_READ(dpll_reg);
6933 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6934 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6935 }
652c393a
JB		 6936}
6937
6938static void intel_decrease_pllclock(struct drm_crtc *crtc)
6939{
6940 struct drm_device *dev = crtc->dev;
6941 drm_i915_private_t *dev_priv = dev->dev_private;
6942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6943
bad720ff 6944 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6945 return;
6946
6947 if (!dev_priv->lvds_downclock_avail)
6948 return;
6949
6950 /*
6951 * Since this is called by a timer, we should never get here in
6952 * the manual case.
6953 */
6954 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6955 int pipe = intel_crtc->pipe;
6956 int dpll_reg = DPLL(pipe);
6957 int dpll;
f6e5b160 6958
44d98a61 6959 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6960
8ac5a6d5 6961 assert_panel_unlocked(dev_priv, pipe);
652c393a 6962
dc257cf1 6963 dpll = I915_READ(dpll_reg);
652c393a
JB		 6964 dpll |= DISPLAY_RATE_SELECT_FPA1;
6965 I915_WRITE(dpll_reg, dpll);
9d0498a2 6966 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6967 dpll = I915_READ(dpll_reg);
6968 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6969 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6970 }
6971
6972}
6973
f047e395
CW		 6974void intel_mark_busy(struct drm_device *dev)
6975{
f047e395
CW		 6976 i915_update_gfx_val(dev->dev_private);
6977}
6978
6979void intel_mark_idle(struct drm_device *dev)
652c393a 6980{
652c393a 6981 struct drm_crtc *crtc;
652c393a
JB		 6982
6983 if (!i915_powersave)
6984 return;
6985
652c393a 6986 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6987 if (!crtc->fb)
6988 continue;
6989
725a5b54 6990 intel_decrease_pllclock(crtc);
652c393a 6991 }
652c393a
JB		 6992}
6993
725a5b54 6994void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 6995{
f047e395
CW		 6996 struct drm_device *dev = obj->base.dev;
6997 struct drm_crtc *crtc;
652c393a 6998
f047e395 6999 if (!i915_powersave)
acb87dfb
CW		 7000 return;
7001
652c393a
JB		 7002 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7003 if (!crtc->fb)
7004 continue;
7005
f047e395 7006 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 7007 intel_increase_pllclock(crtc);
652c393a
JB		 7008 }
7009}
7010
79e53945
JB		 7011static void intel_crtc_destroy(struct drm_crtc *crtc)
7012{
7013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7014 struct drm_device *dev = crtc->dev;
7015 struct intel_unpin_work *work;
7016 unsigned long flags;
7017
7018 spin_lock_irqsave(&dev->event_lock, flags);
7019 work = intel_crtc->unpin_work;
7020 intel_crtc->unpin_work = NULL;
7021 spin_unlock_irqrestore(&dev->event_lock, flags);
7022
7023 if (work) {
7024 cancel_work_sync(&work->work);
7025 kfree(work);
7026 }
79e53945
JB		 7027
7028 drm_crtc_cleanup(crtc);
67e77c5a 7029
79e53945
JB		 7030 kfree(intel_crtc);
7031}
7032
6b95a207
KH		 7033static void intel_unpin_work_fn(struct work_struct *__work)
7034{
7035 struct intel_unpin_work *work =
7036 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7037 struct drm_device *dev = work->crtc->dev;
6b95a207 7038
b4a98e57 7039 mutex_lock(&dev->struct_mutex);
1690e1eb 7040 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7041 drm_gem_object_unreference(&work->pending_flip_obj->base);
7042 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7043
b4a98e57
CW		 7044 intel_update_fbc(dev);
7045 mutex_unlock(&dev->struct_mutex);
7046
7047 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7048 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7049
6b95a207
KH		 7050 kfree(work);
7051}
7052
1afe3e9d 7053static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7054 struct drm_crtc *crtc)
6b95a207
KH		 7055{
7056 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7057 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7058 struct intel_unpin_work *work;
6b95a207
KH		 7059 unsigned long flags;
7060
7061 /* Ignore early vblank irqs */
7062 if (intel_crtc == NULL)
7063 return;
7064
7065 spin_lock_irqsave(&dev->event_lock, flags);
7066 work = intel_crtc->unpin_work;
e7d841ca
CW		 7067
7068 /* Ensure we don't miss a work->pending update ... */
7069 smp_rmb();
7070
7071 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7072 spin_unlock_irqrestore(&dev->event_lock, flags);
7073 return;
7074 }
7075
e7d841ca
CW		 7076 /* and that the unpin work is consistent wrt ->pending. */
7077 smp_rmb();
7078
6b95a207 7079 intel_crtc->unpin_work = NULL;
6b95a207 7080
45a066eb
RC		 7081 if (work->event)
7082 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7083
0af7e4df
MK		 7084 drm_vblank_put(dev, intel_crtc->pipe);
7085
6b95a207
KH		 7086 spin_unlock_irqrestore(&dev->event_lock, flags);
7087
2c10d571 7088 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7089
7090 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7091
7092 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7093}
7094
1afe3e9d
JB		 7095void intel_finish_page_flip(struct drm_device *dev, int pipe)
7096{
7097 drm_i915_private_t *dev_priv = dev->dev_private;
7098 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7099
49b14a5c 7100 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7101}
7102
7103void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7104{
7105 drm_i915_private_t *dev_priv = dev->dev_private;
7106 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7107
49b14a5c 7108 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7109}
7110
6b95a207
KH		 7111void intel_prepare_page_flip(struct drm_device *dev, int plane)
7112{
7113 drm_i915_private_t *dev_priv = dev->dev_private;
7114 struct intel_crtc *intel_crtc =
7115 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7116 unsigned long flags;
7117
e7d841ca
CW		 7118 /* NB: An MMIO update of the plane base pointer will also
7119 * generate a page-flip completion irq, i.e. every modeset
7120 * is also accompanied by a spurious intel_prepare_page_flip().
7121 */
6b95a207 7122 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7123 if (intel_crtc->unpin_work)
7124 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7125 spin_unlock_irqrestore(&dev->event_lock, flags);
7126}
7127
e7d841ca
CW		 7128inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7129{
7130 /* Ensure that the work item is consistent when activating it ... */
7131 smp_wmb();
7132 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7133 /* and that it is marked active as soon as the irq could fire. */
7134 smp_wmb();
7135}
7136
8c9f3aaf
JB		 7137static int intel_gen2_queue_flip(struct drm_device *dev,
7138 struct drm_crtc *crtc,
7139 struct drm_framebuffer *fb,
7140 struct drm_i915_gem_object *obj)
7141{
7142 struct drm_i915_private *dev_priv = dev->dev_private;
7143 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7144 u32 flip_mask;
6d90c952 7145 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7146 int ret;
7147
6d90c952 7148 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7149 if (ret)
83d4092b 7150 goto err;
8c9f3aaf 7151
6d90c952 7152 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7153 if (ret)
83d4092b 7154 goto err_unpin;
8c9f3aaf
JB		 7155
7156 /* Can't queue multiple flips, so wait for the previous
7157 * one to finish before executing the next.
7158 */
7159 if (intel_crtc->plane)
7160 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7161 else
7162 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7163 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7164 intel_ring_emit(ring, MI_NOOP);
7165 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7166 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7167 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7168 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7169 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7170
7171 intel_mark_page_flip_active(intel_crtc);
6d90c952 7172 intel_ring_advance(ring);
83d4092b
CW		 7173 return 0;
7174
7175err_unpin:
7176 intel_unpin_fb_obj(obj);
7177err:
8c9f3aaf
JB		 7178 return ret;
7179}
7180
7181static int intel_gen3_queue_flip(struct drm_device *dev,
7182 struct drm_crtc *crtc,
7183 struct drm_framebuffer *fb,
7184 struct drm_i915_gem_object *obj)
7185{
7186 struct drm_i915_private *dev_priv = dev->dev_private;
7187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7188 u32 flip_mask;
6d90c952 7189 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7190 int ret;
7191
6d90c952 7192 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7193 if (ret)
83d4092b 7194 goto err;
8c9f3aaf 7195
6d90c952 7196 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7197 if (ret)
83d4092b 7198 goto err_unpin;
8c9f3aaf
JB		 7199
7200 if (intel_crtc->plane)
7201 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7202 else
7203 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7204 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7205 intel_ring_emit(ring, MI_NOOP);
7206 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7207 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7208 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7209 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7210 intel_ring_emit(ring, MI_NOOP);
7211
e7d841ca 7212 intel_mark_page_flip_active(intel_crtc);
6d90c952 7213 intel_ring_advance(ring);
83d4092b
CW		 7214 return 0;
7215
7216err_unpin:
7217 intel_unpin_fb_obj(obj);
7218err:
8c9f3aaf
JB		 7219 return ret;
7220}
7221
7222static int intel_gen4_queue_flip(struct drm_device *dev,
7223 struct drm_crtc *crtc,
7224 struct drm_framebuffer *fb,
7225 struct drm_i915_gem_object *obj)
7226{
7227 struct drm_i915_private *dev_priv = dev->dev_private;
7228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7229 uint32_t pf, pipesrc;
6d90c952 7230 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7231 int ret;
7232
6d90c952 7233 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7234 if (ret)
83d4092b 7235 goto err;
8c9f3aaf 7236
6d90c952 7237 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7238 if (ret)
83d4092b 7239 goto err_unpin;
8c9f3aaf
JB		 7240
7241 /* i965+ uses the linear or tiled offsets from the
7242 * Display Registers (which do not change across a page-flip)
7243 * so we need only reprogram the base address.
7244 */
6d90c952
DV		 7245 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7246 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7247 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7248 intel_ring_emit(ring,
7249 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7250 obj->tiling_mode);
8c9f3aaf
JB		 7251
7252 /* XXX Enabling the panel-fitter across page-flip is so far
7253 * untested on non-native modes, so ignore it for now.
7254 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7255 */
7256 pf = 0;
7257 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7258 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7259
7260 intel_mark_page_flip_active(intel_crtc);
6d90c952 7261 intel_ring_advance(ring);
83d4092b
CW		 7262 return 0;
7263
7264err_unpin:
7265 intel_unpin_fb_obj(obj);
7266err:
8c9f3aaf
JB		 7267 return ret;
7268}
7269
7270static int intel_gen6_queue_flip(struct drm_device *dev,
7271 struct drm_crtc *crtc,
7272 struct drm_framebuffer *fb,
7273 struct drm_i915_gem_object *obj)
7274{
7275 struct drm_i915_private *dev_priv = dev->dev_private;
7276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7277 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7278 uint32_t pf, pipesrc;
7279 int ret;
7280
6d90c952 7281 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7282 if (ret)
83d4092b 7283 goto err;
8c9f3aaf 7284
6d90c952 7285 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7286 if (ret)
83d4092b 7287 goto err_unpin;
8c9f3aaf 7288
6d90c952
DV		 7289 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7290 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7291 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7292 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7293
dc257cf1
DV		 7294 /* Contrary to the suggestions in the documentation,
7295 * "Enable Panel Fitter" does not seem to be required when page
7296 * flipping with a non-native mode, and worse causes a normal
7297 * modeset to fail.
7298 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7299 */
7300 pf = 0;
8c9f3aaf 7301 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7302 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7303
7304 intel_mark_page_flip_active(intel_crtc);
6d90c952 7305 intel_ring_advance(ring);
83d4092b
CW		 7306 return 0;
7307
7308err_unpin:
7309 intel_unpin_fb_obj(obj);
7310err:
8c9f3aaf
JB		 7311 return ret;
7312}
7313
7c9017e5
JB		 7314/*
7315 * On gen7 we currently use the blit ring because (in early silicon at least)
7316 * the render ring doesn't give us interrpts for page flip completion, which
7317 * means clients will hang after the first flip is queued. Fortunately the
7318 * blit ring generates interrupts properly, so use it instead.
7319 */
7320static int intel_gen7_queue_flip(struct drm_device *dev,
7321 struct drm_crtc *crtc,
7322 struct drm_framebuffer *fb,
7323 struct drm_i915_gem_object *obj)
7324{
7325 struct drm_i915_private *dev_priv = dev->dev_private;
7326 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7327 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7328 uint32_t plane_bit = 0;
7c9017e5
JB		 7329 int ret;
7330
7331 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7332 if (ret)
83d4092b 7333 goto err;
7c9017e5 7334
cb05d8de
DV		 7335 switch(intel_crtc->plane) {
7336 case PLANE_A:
7337 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7338 break;
7339 case PLANE_B:
7340 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7341 break;
7342 case PLANE_C:
7343 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7344 break;
7345 default:
7346 WARN_ONCE(1, "unknown plane in flip command\n");
7347 ret = -ENODEV;
ab3951eb 7348 goto err_unpin;
cb05d8de
DV		 7349 }
7350
7c9017e5
JB		 7351 ret = intel_ring_begin(ring, 4);
7352 if (ret)
83d4092b 7353 goto err_unpin;
7c9017e5 7354
cb05d8de 7355 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7356 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7357 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7358 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7359
7360 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7361 intel_ring_advance(ring);
83d4092b
CW		 7362 return 0;
7363
7364err_unpin:
7365 intel_unpin_fb_obj(obj);
7366err:
7c9017e5
JB		 7367 return ret;
7368}
7369
8c9f3aaf
JB		 7370static int intel_default_queue_flip(struct drm_device *dev,
7371 struct drm_crtc *crtc,
7372 struct drm_framebuffer *fb,
7373 struct drm_i915_gem_object *obj)
7374{
7375 return -ENODEV;
7376}
7377
6b95a207
KH		 7378static int intel_crtc_page_flip(struct drm_crtc *crtc,
7379 struct drm_framebuffer *fb,
7380 struct drm_pending_vblank_event *event)
7381{
7382 struct drm_device *dev = crtc->dev;
7383 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7384 struct drm_framebuffer *old_fb = crtc->fb;
7385 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7386 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7387 struct intel_unpin_work *work;
8c9f3aaf 7388 unsigned long flags;
52e68630 7389 int ret;
6b95a207 7390
e6a595d2
VS		 7391 /* Can't change pixel format via MI display flips. */
7392 if (fb->pixel_format != crtc->fb->pixel_format)
7393 return -EINVAL;
7394
7395 /*
7396 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7397 * Note that pitch changes could also affect these register.
7398 */
7399 if (INTEL_INFO(dev)->gen > 3 &&
7400 (fb->offsets[0] != crtc->fb->offsets[0] ||
7401 fb->pitches[0] != crtc->fb->pitches[0]))
7402 return -EINVAL;
7403
6b95a207
KH		 7404 work = kzalloc(sizeof *work, GFP_KERNEL);
7405 if (work == NULL)
7406 return -ENOMEM;
7407
6b95a207 7408 work->event = event;
b4a98e57 7409 work->crtc = crtc;
4a35f83b 7410 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7411 INIT_WORK(&work->work, intel_unpin_work_fn);
7412
7317c75e
JB		 7413 ret = drm_vblank_get(dev, intel_crtc->pipe);
7414 if (ret)
7415 goto free_work;
7416
6b95a207
KH		 7417 /* We borrow the event spin lock for protecting unpin_work */
7418 spin_lock_irqsave(&dev->event_lock, flags);
7419 if (intel_crtc->unpin_work) {
7420 spin_unlock_irqrestore(&dev->event_lock, flags);
7421 kfree(work);
7317c75e 7422 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7423
7424 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7425 return -EBUSY;
7426 }
7427 intel_crtc->unpin_work = work;
7428 spin_unlock_irqrestore(&dev->event_lock, flags);
7429
b4a98e57
CW		 7430 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7431 flush_workqueue(dev_priv->wq);
7432
79158103
CW		 7433 ret = i915_mutex_lock_interruptible(dev);
7434 if (ret)
7435 goto cleanup;
6b95a207 7436
75dfca80 7437 /* Reference the objects for the scheduled work. */
05394f39
CW		 7438 drm_gem_object_reference(&work->old_fb_obj->base);
7439 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7440
7441 crtc->fb = fb;
96b099fd 7442
e1f99ce6 7443 work->pending_flip_obj = obj;
e1f99ce6 7444
4e5359cd
SF		 7445 work->enable_stall_check = true;
7446
b4a98e57 7447 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7448 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7449
8c9f3aaf
JB		 7450 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7451 if (ret)
7452 goto cleanup_pending;
6b95a207 7453
7782de3b 7454 intel_disable_fbc(dev);
f047e395 7455 intel_mark_fb_busy(obj);
6b95a207
KH		 7456 mutex_unlock(&dev->struct_mutex);
7457
e5510fac
JB		 7458 trace_i915_flip_request(intel_crtc->plane, obj);
7459
6b95a207 7460 return 0;
96b099fd 7461
8c9f3aaf 7462cleanup_pending:
b4a98e57 7463 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7464 crtc->fb = old_fb;
05394f39
CW		 7465 drm_gem_object_unreference(&work->old_fb_obj->base);
7466 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7467 mutex_unlock(&dev->struct_mutex);
7468
79158103 7469cleanup:
96b099fd
CW		 7470 spin_lock_irqsave(&dev->event_lock, flags);
7471 intel_crtc->unpin_work = NULL;
7472 spin_unlock_irqrestore(&dev->event_lock, flags);
7473
7317c75e
JB		 7474 drm_vblank_put(dev, intel_crtc->pipe);
7475free_work:
96b099fd
CW		 7476 kfree(work);
7477
7478 return ret;
6b95a207
KH		 7479}
7480
f6e5b160 7481static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7482 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7483 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7484};
7485
6ed0f796 7486bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7487{
6ed0f796
DV		 7488 struct intel_encoder *other_encoder;
7489 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7490
6ed0f796
DV		 7491 if (WARN_ON(!crtc))
7492 return false;
7493
7494 list_for_each_entry(other_encoder,
7495 &crtc->dev->mode_config.encoder_list,
7496 base.head) {
7497
7498 if (&other_encoder->new_crtc->base != crtc ||
7499 encoder == other_encoder)
7500 continue;
7501 else
7502 return true;
f47166d2
CW		 7503 }
7504
6ed0f796
DV		 7505 return false;
7506}
47f1c6c9 7507
50f56119
DV		 7508static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7509 struct drm_crtc *crtc)
7510{
7511 struct drm_device *dev;
7512 struct drm_crtc *tmp;
7513 int crtc_mask = 1;
47f1c6c9 7514
50f56119 7515 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7516
50f56119 7517 dev = crtc->dev;
47f1c6c9 7518
50f56119
DV		 7519 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7520 if (tmp == crtc)
7521 break;
7522 crtc_mask <<= 1;
7523 }
47f1c6c9 7524
50f56119
DV		 7525 if (encoder->possible_crtcs & crtc_mask)
7526 return true;
7527 return false;
47f1c6c9 7528}
79e53945 7529
9a935856
DV		 7530/**
7531 * intel_modeset_update_staged_output_state
7532 *
7533 * Updates the staged output configuration state, e.g. after we've read out the
7534 * current hw state.
7535 */
7536static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7537{
9a935856
DV		 7538 struct intel_encoder *encoder;
7539 struct intel_connector *connector;
f6e5b160 7540
9a935856
DV		 7541 list_for_each_entry(connector, &dev->mode_config.connector_list,
7542 base.head) {
7543 connector->new_encoder =
7544 to_intel_encoder(connector->base.encoder);
7545 }
f6e5b160 7546
9a935856
DV		 7547 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7548 base.head) {
7549 encoder->new_crtc =
7550 to_intel_crtc(encoder->base.crtc);
7551 }
f6e5b160
CW		 7552}
7553
9a935856
DV		 7554/**
7555 * intel_modeset_commit_output_state
7556 *
7557 * This function copies the stage display pipe configuration to the real one.
7558 */
7559static void intel_modeset_commit_output_state(struct drm_device *dev)
7560{
7561 struct intel_encoder *encoder;
7562 struct intel_connector *connector;
f6e5b160 7563
9a935856
DV		 7564 list_for_each_entry(connector, &dev->mode_config.connector_list,
7565 base.head) {
7566 connector->base.encoder = &connector->new_encoder->base;
7567 }
f6e5b160 7568
9a935856
DV		 7569 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7570 base.head) {
7571 encoder->base.crtc = &encoder->new_crtc->base;
7572 }
7573}
7574
4e53c2e0
DV		 7575static int
7576pipe_config_set_bpp(struct drm_crtc *crtc,
7577 struct drm_framebuffer *fb,
7578 struct intel_crtc_config *pipe_config)
7579{
7580 struct drm_device *dev = crtc->dev;
7581 struct drm_connector *connector;
7582 int bpp;
7583
d42264b1
DV		 7584 switch (fb->pixel_format) {
7585 case DRM_FORMAT_C8:
4e53c2e0
DV		 7586 bpp = 8*3; /* since we go through a colormap */
7587 break;
d42264b1
DV		 7588 case DRM_FORMAT_XRGB1555:
7589 case DRM_FORMAT_ARGB1555:
7590 /* checked in intel_framebuffer_init already */
7591 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7592 return -EINVAL;
7593 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7594 bpp = 6*3; /* min is 18bpp */
7595 break;
d42264b1
DV		 7596 case DRM_FORMAT_XBGR8888:
7597 case DRM_FORMAT_ABGR8888:
7598 /* checked in intel_framebuffer_init already */
7599 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7600 return -EINVAL;
7601 case DRM_FORMAT_XRGB8888:
7602 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7603 bpp = 8*3;
7604 break;
d42264b1
DV		 7605 case DRM_FORMAT_XRGB2101010:
7606 case DRM_FORMAT_ARGB2101010:
7607 case DRM_FORMAT_XBGR2101010:
7608 case DRM_FORMAT_ABGR2101010:
7609 /* checked in intel_framebuffer_init already */
7610 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7611 return -EINVAL;
4e53c2e0
DV		 7612 bpp = 10*3;
7613 break;
baba133a 7614 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7615 default:
7616 DRM_DEBUG_KMS("unsupported depth\n");
7617 return -EINVAL;
7618 }
7619
4e53c2e0
DV		 7620 pipe_config->pipe_bpp = bpp;
7621
7622 /* Clamp display bpp to EDID value */
7623 list_for_each_entry(connector, &dev->mode_config.connector_list,
7624 head) {
7625 if (connector->encoder && connector->encoder->crtc != crtc)
7626 continue;
7627
7628 /* Don't use an invalid EDID bpc value */
7629 if (connector->display_info.bpc &&
7630 connector->display_info.bpc * 3 < bpp) {
7631 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7632 bpp, connector->display_info.bpc*3);
7633 pipe_config->pipe_bpp = connector->display_info.bpc*3;
7634 }
996a2239
DV		 7635
7636 /* Clamp bpp to 8 on screens without EDID 1.4 */
7637 if (connector->display_info.bpc == 0 && bpp > 24) {
7638 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7639 bpp);
7640 pipe_config->pipe_bpp = 24;
7641 }
4e53c2e0
DV		 7642 }
7643
7644 return bpp;
7645}
7646
b8cecdf5
DV		 7647static struct intel_crtc_config *
7648intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7649 struct drm_framebuffer *fb,
b8cecdf5 7650 struct drm_display_mode *mode)
ee7b9f93 7651{
7758a113 7652 struct drm_device *dev = crtc->dev;
7758a113
DV		 7653 struct drm_encoder_helper_funcs *encoder_funcs;
7654 struct intel_encoder *encoder;
b8cecdf5 7655 struct intel_crtc_config *pipe_config;
4e53c2e0 7656 int plane_bpp;
ee7b9f93 7657
b8cecdf5
DV		 7658 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7659 if (!pipe_config)
7758a113
DV		 7660 return ERR_PTR(-ENOMEM);
7661
b8cecdf5
DV		 7662 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7663 drm_mode_copy(&pipe_config->requested_mode, mode);
7664
4e53c2e0
DV		 7665 plane_bpp = pipe_config_set_bpp(crtc, fb, pipe_config);
7666 if (plane_bpp < 0)
7667 goto fail;
7668
7758a113
DV		 7669 /* Pass our mode to the connectors and the CRTC to give them a chance to
7670 * adjust it according to limitations or connector properties, and also
7671 * a chance to reject the mode entirely.
47f1c6c9 7672 */
7758a113
DV		 7673 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7674 base.head) {
47f1c6c9 7675
7758a113
DV		 7676 if (&encoder->new_crtc->base != crtc)
7677 continue;
7ae89233
DV		 7678
7679 if (encoder->compute_config) {
7680 if (!(encoder->compute_config(encoder, pipe_config))) {
7681 DRM_DEBUG_KMS("Encoder config failure\n");
7682 goto fail;
7683 }
7684
7685 continue;
7686 }
7687
7758a113 7688 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7689 if (!(encoder_funcs->mode_fixup(&encoder->base,
7690 &pipe_config->requested_mode,
7691 &pipe_config->adjusted_mode))) {
7758a113
DV		 7692 DRM_DEBUG_KMS("Encoder fixup failed\n");
7693 goto fail;
7694 }
ee7b9f93 7695 }
47f1c6c9 7696
b8cecdf5 7697 if (!(intel_crtc_compute_config(crtc, pipe_config))) {
7758a113
DV		 7698 DRM_DEBUG_KMS("CRTC fixup failed\n");
7699 goto fail;
ee7b9f93 7700 }
7758a113 7701 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7702
4e53c2e0
DV		 7703 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7704 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7705 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7706
b8cecdf5 7707 return pipe_config;
7758a113 7708fail:
b8cecdf5 7709 kfree(pipe_config);
7758a113 7710 return ERR_PTR(-EINVAL);
ee7b9f93 7711}
47f1c6c9 7712
e2e1ed41
DV		 7713/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7714 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7715static void
7716intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7717 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7718{
7719 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7720 struct drm_device *dev = crtc->dev;
7721 struct intel_encoder *encoder;
7722 struct intel_connector *connector;
7723 struct drm_crtc *tmp_crtc;
79e53945 7724
e2e1ed41 7725 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7726
e2e1ed41
DV		 7727 /* Check which crtcs have changed outputs connected to them, these need
7728 * to be part of the prepare_pipes mask. We don't (yet) support global
7729 * modeset across multiple crtcs, so modeset_pipes will only have one
7730 * bit set at most. */
7731 list_for_each_entry(connector, &dev->mode_config.connector_list,
7732 base.head) {
7733 if (connector->base.encoder == &connector->new_encoder->base)
7734 continue;
79e53945 7735
e2e1ed41
DV		 7736 if (connector->base.encoder) {
7737 tmp_crtc = connector->base.encoder->crtc;
7738
7739 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7740 }
7741
7742 if (connector->new_encoder)
7743 *prepare_pipes |=
7744 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7745 }
7746
e2e1ed41
DV		 7747 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7748 base.head) {
7749 if (encoder->base.crtc == &encoder->new_crtc->base)
7750 continue;
7751
7752 if (encoder->base.crtc) {
7753 tmp_crtc = encoder->base.crtc;
7754
7755 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7756 }
7757
7758 if (encoder->new_crtc)
7759 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7760 }
7761
e2e1ed41
DV		 7762 /* Check for any pipes that will be fully disabled ... */
7763 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7764 base.head) {
7765 bool used = false;
22fd0fab 7766
e2e1ed41
DV		 7767 /* Don't try to disable disabled crtcs. */
7768 if (!intel_crtc->base.enabled)
7769 continue;
7e7d76c3 7770
e2e1ed41
DV		 7771 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7772 base.head) {
7773 if (encoder->new_crtc == intel_crtc)
7774 used = true;
7775 }
7776
7777 if (!used)
7778 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7779 }
7780
e2e1ed41
DV		 7781
7782 /* set_mode is also used to update properties on life display pipes. */
7783 intel_crtc = to_intel_crtc(crtc);
7784 if (crtc->enabled)
7785 *prepare_pipes |= 1 << intel_crtc->pipe;
7786
b6c5164d
DV		 7787 /*
7788 * For simplicity do a full modeset on any pipe where the output routing
7789 * changed. We could be more clever, but that would require us to be
7790 * more careful with calling the relevant encoder->mode_set functions.
7791 */
e2e1ed41
DV		 7792 if (*prepare_pipes)
7793 *modeset_pipes = *prepare_pipes;
7794
7795 /* ... and mask these out. */
7796 *modeset_pipes &= ~(*disable_pipes);
7797 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7798
7799 /*
7800 * HACK: We don't (yet) fully support global modesets. intel_set_config
7801 * obies this rule, but the modeset restore mode of
7802 * intel_modeset_setup_hw_state does not.
7803 */
7804 *modeset_pipes &= 1 << intel_crtc->pipe;
7805 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 7806
7807 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7808 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 7809}
79e53945 7810
ea9d758d 7811static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7812{
ea9d758d 7813 struct drm_encoder *encoder;
f6e5b160 7814 struct drm_device *dev = crtc->dev;
f6e5b160 7815
ea9d758d
DV		 7816 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7817 if (encoder->crtc == crtc)
7818 return true;
7819
7820 return false;
7821}
7822
7823static void
7824intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7825{
7826 struct intel_encoder *intel_encoder;
7827 struct intel_crtc *intel_crtc;
7828 struct drm_connector *connector;
7829
7830 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7831 base.head) {
7832 if (!intel_encoder->base.crtc)
7833 continue;
7834
7835 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7836
7837 if (prepare_pipes & (1 << intel_crtc->pipe))
7838 intel_encoder->connectors_active = false;
7839 }
7840
7841 intel_modeset_commit_output_state(dev);
7842
7843 /* Update computed state. */
7844 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7845 base.head) {
7846 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7847 }
7848
7849 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7850 if (!connector->encoder || !connector->encoder->crtc)
7851 continue;
7852
7853 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7854
7855 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7856 struct drm_property *dpms_property =
7857 dev->mode_config.dpms_property;
7858
ea9d758d 7859 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7860 drm_object_property_set_value(&connector->base,
68d34720
DV		 7861 dpms_property,
7862 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7863
7864 intel_encoder = to_intel_encoder(connector->encoder);
7865 intel_encoder->connectors_active = true;
7866 }
7867 }
7868
7869}
7870
25c5b266
DV		 7871#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7872 list_for_each_entry((intel_crtc), \
7873 &(dev)->mode_config.crtc_list, \
7874 base.head) \
7875 if (mask & (1 <<(intel_crtc)->pipe)) \
7876
0e8ffe1b
DV		 7877static bool
7878intel_pipe_config_compare(struct intel_crtc_config *current_config,
7879 struct intel_crtc_config *pipe_config)
7880{
88adfff1
DV		 7881 if (current_config->has_pch_encoder != pipe_config->has_pch_encoder) {
7882 DRM_ERROR("mismatch in has_pch_encoder "
7883 "(expected %i, found %i)\n",
7884 current_config->has_pch_encoder,
7885 pipe_config->has_pch_encoder);
7886 return false;
7887 }
7888
0e8ffe1b
DV		 7889 return true;
7890}
7891
b980514c 7892void
8af6cf88
DV		 7893intel_modeset_check_state(struct drm_device *dev)
7894{
0e8ffe1b 7895 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 7896 struct intel_crtc *crtc;
7897 struct intel_encoder *encoder;
7898 struct intel_connector *connector;
0e8ffe1b 7899 struct intel_crtc_config pipe_config;
8af6cf88
DV		 7900
7901 list_for_each_entry(connector, &dev->mode_config.connector_list,
7902 base.head) {
7903 /* This also checks the encoder/connector hw state with the
7904 * ->get_hw_state callbacks. */
7905 intel_connector_check_state(connector);
7906
7907 WARN(&connector->new_encoder->base != connector->base.encoder,
7908 "connector's staged encoder doesn't match current encoder\n");
7909 }
7910
7911 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7912 base.head) {
7913 bool enabled = false;
7914 bool active = false;
7915 enum pipe pipe, tracked_pipe;
7916
7917 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7918 encoder->base.base.id,
7919 drm_get_encoder_name(&encoder->base));
7920
7921 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7922 "encoder's stage crtc doesn't match current crtc\n");
7923 WARN(encoder->connectors_active && !encoder->base.crtc,
7924 "encoder's active_connectors set, but no crtc\n");
7925
7926 list_for_each_entry(connector, &dev->mode_config.connector_list,
7927 base.head) {
7928 if (connector->base.encoder != &encoder->base)
7929 continue;
7930 enabled = true;
7931 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7932 active = true;
7933 }
7934 WARN(!!encoder->base.crtc != enabled,
7935 "encoder's enabled state mismatch "
7936 "(expected %i, found %i)\n",
7937 !!encoder->base.crtc, enabled);
7938 WARN(active && !encoder->base.crtc,
7939 "active encoder with no crtc\n");
7940
7941 WARN(encoder->connectors_active != active,
7942 "encoder's computed active state doesn't match tracked active state "
7943 "(expected %i, found %i)\n", active, encoder->connectors_active);
7944
7945 active = encoder->get_hw_state(encoder, &pipe);
7946 WARN(active != encoder->connectors_active,
7947 "encoder's hw state doesn't match sw tracking "
7948 "(expected %i, found %i)\n",
7949 encoder->connectors_active, active);
7950
7951 if (!encoder->base.crtc)
7952 continue;
7953
7954 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7955 WARN(active && pipe != tracked_pipe,
7956 "active encoder's pipe doesn't match"
7957 "(expected %i, found %i)\n",
7958 tracked_pipe, pipe);
7959
7960 }
7961
7962 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7963 base.head) {
7964 bool enabled = false;
7965 bool active = false;
7966
7967 DRM_DEBUG_KMS("[CRTC:%d]\n",
7968 crtc->base.base.id);
7969
7970 WARN(crtc->active && !crtc->base.enabled,
7971 "active crtc, but not enabled in sw tracking\n");
7972
7973 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7974 base.head) {
7975 if (encoder->base.crtc != &crtc->base)
7976 continue;
7977 enabled = true;
7978 if (encoder->connectors_active)
7979 active = true;
7980 }
7981 WARN(active != crtc->active,
7982 "crtc's computed active state doesn't match tracked active state "
7983 "(expected %i, found %i)\n", active, crtc->active);
7984 WARN(enabled != crtc->base.enabled,
7985 "crtc's computed enabled state doesn't match tracked enabled state "
7986 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7987
88adfff1 7988 memset(&pipe_config, 0, sizeof(pipe_config));
60c4ae10 7989 pipe_config.cpu_transcoder = crtc->config.cpu_transcoder;
0e8ffe1b
DV		 7990 active = dev_priv->display.get_pipe_config(crtc,
7991 &pipe_config);
7992 WARN(crtc->active != active,
7993 "crtc active state doesn't match with hw state "
7994 "(expected %i, found %i)\n", crtc->active, active);
7995
7996 WARN(active &&
7997 !intel_pipe_config_compare(&crtc->config, &pipe_config),
7998 "pipe state doesn't match!\n");
8af6cf88
DV		 7999 }
8000}
8001
f30da187
DV		 8002static int __intel_set_mode(struct drm_crtc *crtc,
8003 struct drm_display_mode *mode,
8004 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8005{
8006 struct drm_device *dev = crtc->dev;
dbf2b54e 8007 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8008 struct drm_display_mode *saved_mode, *saved_hwmode;
8009 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8010 struct intel_crtc *intel_crtc;
8011 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8012 int ret = 0;
a6778b3c 8013
3ac18232 8014 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8015 if (!saved_mode)
8016 return -ENOMEM;
3ac18232 8017 saved_hwmode = saved_mode + 1;
a6778b3c 8018
e2e1ed41 8019 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8020 &prepare_pipes, &disable_pipes);
8021
3ac18232
TG		 8022 *saved_hwmode = crtc->hwmode;
8023 *saved_mode = crtc->mode;
a6778b3c 8024
25c5b266
DV		 8025 /* Hack: Because we don't (yet) support global modeset on multiple
8026 * crtcs, we don't keep track of the new mode for more than one crtc.
8027 * Hence simply check whether any bit is set in modeset_pipes in all the
8028 * pieces of code that are not yet converted to deal with mutliple crtcs
8029 * changing their mode at the same time. */
25c5b266 8030 if (modeset_pipes) {
4e53c2e0 8031 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8032 if (IS_ERR(pipe_config)) {
8033 ret = PTR_ERR(pipe_config);
8034 pipe_config = NULL;
8035
3ac18232 8036 goto out;
25c5b266 8037 }
25c5b266 8038 }
a6778b3c 8039
460da916
DV		 8040 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8041 intel_crtc_disable(&intel_crtc->base);
8042
ea9d758d
DV		 8043 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8044 if (intel_crtc->base.enabled)
8045 dev_priv->display.crtc_disable(&intel_crtc->base);
8046 }
a6778b3c 8047
6c4c86f5
DV		 8048 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8049 * to set it here already despite that we pass it down the callchain.
f6e5b160 8050 */
b8cecdf5 8051 if (modeset_pipes) {
3b117c8f 8052 enum transcoder tmp = to_intel_crtc(crtc)->config.cpu_transcoder;
25c5b266 8053 crtc->mode = *mode;
b8cecdf5
DV		 8054 /* mode_set/enable/disable functions rely on a correct pipe
8055 * config. */
8056 to_intel_crtc(crtc)->config = *pipe_config;
3b117c8f 8057 to_intel_crtc(crtc)->config.cpu_transcoder = tmp;
b8cecdf5 8058 }
7758a113 8059
ea9d758d
DV		 8060 /* Only after disabling all output pipelines that will be changed can we
8061 * update the the output configuration. */
8062 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8063
47fab737
DV		 8064 if (dev_priv->display.modeset_global_resources)
8065 dev_priv->display.modeset_global_resources(dev);
8066
a6778b3c
DV		 8067 /* Set up the DPLL and any encoders state that needs to adjust or depend
8068 * on the DPLL.
f6e5b160 8069 */
25c5b266 8070 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8071 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8072 x, y, fb);
8073 if (ret)
8074 goto done;
a6778b3c
DV		 8075 }
8076
8077 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8078 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8079 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8080
25c5b266
DV		 8081 if (modeset_pipes) {
8082 /* Store real post-adjustment hardware mode. */
b8cecdf5 8083 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8084
25c5b266
DV		 8085 /* Calculate and store various constants which
8086 * are later needed by vblank and swap-completion
8087 * timestamping. They are derived from true hwmode.
8088 */
8089 drm_calc_timestamping_constants(crtc);
8090 }
a6778b3c
DV		 8091
8092 /* FIXME: add subpixel order */
8093done:
c0c36b94 8094 if (ret && crtc->enabled) {
3ac18232
TG		 8095 crtc->hwmode = *saved_hwmode;
8096 crtc->mode = *saved_mode;
a6778b3c
DV		 8097 }
8098
3ac18232 8099out:
b8cecdf5 8100 kfree(pipe_config);
3ac18232 8101 kfree(saved_mode);
a6778b3c 8102 return ret;
f6e5b160
CW		 8103}
8104
f30da187
DV		 8105int intel_set_mode(struct drm_crtc *crtc,
8106 struct drm_display_mode *mode,
8107 int x, int y, struct drm_framebuffer *fb)
8108{
8109 int ret;
8110
8111 ret = __intel_set_mode(crtc, mode, x, y, fb);
8112
8113 if (ret == 0)
8114 intel_modeset_check_state(crtc->dev);
8115
8116 return ret;
8117}
8118
c0c36b94
CW		 8119void intel_crtc_restore_mode(struct drm_crtc *crtc)
8120{
8121 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8122}
8123
25c5b266
DV		 8124#undef for_each_intel_crtc_masked
8125
d9e55608
DV		 8126static void intel_set_config_free(struct intel_set_config *config)
8127{
8128 if (!config)
8129 return;
8130
1aa4b628
DV		 8131 kfree(config->save_connector_encoders);
8132 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8133 kfree(config);
8134}
8135
85f9eb71
DV		 8136static int intel_set_config_save_state(struct drm_device *dev,
8137 struct intel_set_config *config)
8138{
85f9eb71
DV		 8139 struct drm_encoder *encoder;
8140 struct drm_connector *connector;
8141 int count;
8142
1aa4b628
DV		 8143 config->save_encoder_crtcs =
8144 kcalloc(dev->mode_config.num_encoder,
8145 sizeof(struct drm_crtc *), GFP_KERNEL);
8146 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8147 return -ENOMEM;
8148
1aa4b628
DV		 8149 config->save_connector_encoders =
8150 kcalloc(dev->mode_config.num_connector,
8151 sizeof(struct drm_encoder *), GFP_KERNEL);
8152 if (!config->save_connector_encoders)
85f9eb71
DV		 8153 return -ENOMEM;
8154
8155 /* Copy data. Note that driver private data is not affected.
8156 * Should anything bad happen only the expected state is
8157 * restored, not the drivers personal bookkeeping.
8158 */
85f9eb71
DV		 8159 count = 0;
8160 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8161 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8162 }
8163
8164 count = 0;
8165 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8166 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8167 }
8168
8169 return 0;
8170}
8171
8172static void intel_set_config_restore_state(struct drm_device *dev,
8173 struct intel_set_config *config)
8174{
9a935856
DV		 8175 struct intel_encoder *encoder;
8176 struct intel_connector *connector;
85f9eb71
DV		 8177 int count;
8178
85f9eb71 8179 count = 0;
9a935856
DV		 8180 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8181 encoder->new_crtc =
8182 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8183 }
8184
8185 count = 0;
9a935856
DV		 8186 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8187 connector->new_encoder =
8188 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8189 }
8190}
8191
5e2b584e
DV		 8192static void
8193intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8194 struct intel_set_config *config)
8195{
8196
8197 /* We should be able to check here if the fb has the same properties
8198 * and then just flip_or_move it */
8199 if (set->crtc->fb != set->fb) {
8200 /* If we have no fb then treat it as a full mode set */
8201 if (set->crtc->fb == NULL) {
8202 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8203 config->mode_changed = true;
8204 } else if (set->fb == NULL) {
8205 config->mode_changed = true;
72f4901e
DV		 8206 } else if (set->fb->pixel_format !=
8207 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8208 config->mode_changed = true;
8209 } else
8210 config->fb_changed = true;
8211 }
8212
835c5873 8213 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8214 config->fb_changed = true;
8215
8216 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8217 DRM_DEBUG_KMS("modes are different, full mode set\n");
8218 drm_mode_debug_printmodeline(&set->crtc->mode);
8219 drm_mode_debug_printmodeline(set->mode);
8220 config->mode_changed = true;
8221 }
8222}
8223
2e431051 8224static int
9a935856
DV		 8225intel_modeset_stage_output_state(struct drm_device *dev,
8226 struct drm_mode_set *set,
8227 struct intel_set_config *config)
50f56119 8228{
85f9eb71 8229 struct drm_crtc *new_crtc;
9a935856
DV		 8230 struct intel_connector *connector;
8231 struct intel_encoder *encoder;
2e431051 8232 int count, ro;
50f56119 8233
9abdda74 8234 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8235 * of connectors. For paranoia, double-check this. */
8236 WARN_ON(!set->fb && (set->num_connectors != 0));
8237 WARN_ON(set->fb && (set->num_connectors == 0));
8238
50f56119 8239 count = 0;
9a935856
DV		 8240 list_for_each_entry(connector, &dev->mode_config.connector_list,
8241 base.head) {
8242 /* Otherwise traverse passed in connector list and get encoders
8243 * for them. */
50f56119 8244 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8245 if (set->connectors[ro] == &connector->base) {
8246 connector->new_encoder = connector->encoder;
50f56119
DV		 8247 break;
8248 }
8249 }
8250
9a935856
DV		 8251 /* If we disable the crtc, disable all its connectors. Also, if
8252 * the connector is on the changing crtc but not on the new
8253 * connector list, disable it. */
8254 if ((!set->fb || ro == set->num_connectors) &&
8255 connector->base.encoder &&
8256 connector->base.encoder->crtc == set->crtc) {
8257 connector->new_encoder = NULL;
8258
8259 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8260 connector->base.base.id,
8261 drm_get_connector_name(&connector->base));
8262 }
8263
8264
8265 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8266 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8267 config->mode_changed = true;
50f56119
DV		 8268 }
8269 }
9a935856 8270 /* connector->new_encoder is now updated for all connectors. */
50f56119 8271
9a935856 8272 /* Update crtc of enabled connectors. */
50f56119 8273 count = 0;
9a935856
DV		 8274 list_for_each_entry(connector, &dev->mode_config.connector_list,
8275 base.head) {
8276 if (!connector->new_encoder)
50f56119
DV		 8277 continue;
8278
9a935856 8279 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8280
8281 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8282 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8283 new_crtc = set->crtc;
8284 }
8285
8286 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8287 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8288 new_crtc)) {
5e2b584e 8289 return -EINVAL;
50f56119 8290 }
9a935856
DV		 8291 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8292
8293 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8294 connector->base.base.id,
8295 drm_get_connector_name(&connector->base),
8296 new_crtc->base.id);
8297 }
8298
8299 /* Check for any encoders that needs to be disabled. */
8300 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8301 base.head) {
8302 list_for_each_entry(connector,
8303 &dev->mode_config.connector_list,
8304 base.head) {
8305 if (connector->new_encoder == encoder) {
8306 WARN_ON(!connector->new_encoder->new_crtc);
8307
8308 goto next_encoder;
8309 }
8310 }
8311 encoder->new_crtc = NULL;
8312next_encoder:
8313 /* Only now check for crtc changes so we don't miss encoders
8314 * that will be disabled. */
8315 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8316 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8317 config->mode_changed = true;
50f56119
DV		 8318 }
8319 }
9a935856 8320 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8321
2e431051
DV		 8322 return 0;
8323}
8324
8325static int intel_crtc_set_config(struct drm_mode_set *set)
8326{
8327 struct drm_device *dev;
2e431051
DV		 8328 struct drm_mode_set save_set;
8329 struct intel_set_config *config;
8330 int ret;
2e431051 8331
8d3e375e
DV		 8332 BUG_ON(!set);
8333 BUG_ON(!set->crtc);
8334 BUG_ON(!set->crtc->helper_private);
2e431051 8335
7e53f3a4
DV		 8336 /* Enforce sane interface api - has been abused by the fb helper. */
8337 BUG_ON(!set->mode && set->fb);
8338 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8339
2e431051
DV		 8340 if (set->fb) {
8341 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8342 set->crtc->base.id, set->fb->base.id,
8343 (int)set->num_connectors, set->x, set->y);
8344 } else {
8345 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8346 }
8347
8348 dev = set->crtc->dev;
8349
8350 ret = -ENOMEM;
8351 config = kzalloc(sizeof(*config), GFP_KERNEL);
8352 if (!config)
8353 goto out_config;
8354
8355 ret = intel_set_config_save_state(dev, config);
8356 if (ret)
8357 goto out_config;
8358
8359 save_set.crtc = set->crtc;
8360 save_set.mode = &set->crtc->mode;
8361 save_set.x = set->crtc->x;
8362 save_set.y = set->crtc->y;
8363 save_set.fb = set->crtc->fb;
8364
8365 /* Compute whether we need a full modeset, only an fb base update or no
8366 * change at all. In the future we might also check whether only the
8367 * mode changed, e.g. for LVDS where we only change the panel fitter in
8368 * such cases. */
8369 intel_set_config_compute_mode_changes(set, config);
8370
9a935856 8371 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8372 if (ret)
8373 goto fail;
8374
5e2b584e 8375 if (config->mode_changed) {
87f1faa6 8376 if (set->mode) {
50f56119
DV		 8377 DRM_DEBUG_KMS("attempting to set mode from"
8378 " userspace\n");
8379 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8380 }
8381
c0c36b94
CW		 8382 ret = intel_set_mode(set->crtc, set->mode,
8383 set->x, set->y, set->fb);
8384 if (ret) {
8385 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8386 set->crtc->base.id, ret);
87f1faa6
DV		 8387 goto fail;
8388 }
5e2b584e 8389 } else if (config->fb_changed) {
4878cae2
VS		 8390 intel_crtc_wait_for_pending_flips(set->crtc);
8391
4f660f49 8392 ret = intel_pipe_set_base(set->crtc,
94352cf9 8393 set->x, set->y, set->fb);
50f56119
DV		 8394 }
8395
d9e55608
DV		 8396 intel_set_config_free(config);
8397
50f56119
DV		 8398 return 0;
8399
8400fail:
85f9eb71 8401 intel_set_config_restore_state(dev, config);
50f56119
DV		 8402
8403 /* Try to restore the config */
5e2b584e 8404 if (config->mode_changed &&
c0c36b94
CW		 8405 intel_set_mode(save_set.crtc, save_set.mode,
8406 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8407 DRM_ERROR("failed to restore config after modeset failure\n");
8408
d9e55608
DV		 8409out_config:
8410 intel_set_config_free(config);
50f56119
DV		 8411 return ret;
8412}
f6e5b160
CW		 8413
8414static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8415 .cursor_set = intel_crtc_cursor_set,
8416 .cursor_move = intel_crtc_cursor_move,
8417 .gamma_set = intel_crtc_gamma_set,
50f56119 8418 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8419 .destroy = intel_crtc_destroy,
8420 .page_flip = intel_crtc_page_flip,
8421};
8422
79f689aa
PZ		 8423static void intel_cpu_pll_init(struct drm_device *dev)
8424{
affa9354 8425 if (HAS_DDI(dev))
79f689aa
PZ		 8426 intel_ddi_pll_init(dev);
8427}
8428
ee7b9f93
JB		 8429static void intel_pch_pll_init(struct drm_device *dev)
8430{
8431 drm_i915_private_t *dev_priv = dev->dev_private;
8432 int i;
8433
8434 if (dev_priv->num_pch_pll == 0) {
8435 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8436 return;
8437 }
8438
8439 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8440 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8441 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8442 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8443 }
8444}
8445
b358d0a6 8446static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8447{
22fd0fab 8448 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8449 struct intel_crtc *intel_crtc;
8450 int i;
8451
8452 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8453 if (intel_crtc == NULL)
8454 return;
8455
8456 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8457
8458 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8459 for (i = 0; i < 256; i++) {
8460 intel_crtc->lut_r[i] = i;
8461 intel_crtc->lut_g[i] = i;
8462 intel_crtc->lut_b[i] = i;
8463 }
8464
80824003
JB		 8465 /* Swap pipes & planes for FBC on pre-965 */
8466 intel_crtc->pipe = pipe;
8467 intel_crtc->plane = pipe;
3b117c8f 8468 intel_crtc->config.cpu_transcoder = pipe;
e2e767ab 8469 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8470 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8471 intel_crtc->plane = !pipe;
80824003
JB		 8472 }
8473
22fd0fab
JB		 8474 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8475 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8476 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8477 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8478
79e53945 8479 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8480}
8481
08d7b3d1 8482int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8483 struct drm_file *file)
08d7b3d1 8484{
08d7b3d1 8485 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8486 struct drm_mode_object *drmmode_obj;
8487 struct intel_crtc *crtc;
08d7b3d1 8488
1cff8f6b
DV		 8489 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8490 return -ENODEV;
08d7b3d1 8491
c05422d5
DV		 8492 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8493 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8494
c05422d5 8495 if (!drmmode_obj) {
08d7b3d1
CW		 8496 DRM_ERROR("no such CRTC id\n");
8497 return -EINVAL;
8498 }
8499
c05422d5
DV		 8500 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8501 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8502
c05422d5 8503 return 0;
08d7b3d1
CW		 8504}
8505
66a9278e 8506static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8507{
66a9278e
DV		 8508 struct drm_device *dev = encoder->base.dev;
8509 struct intel_encoder *source_encoder;
79e53945 8510 int index_mask = 0;
79e53945
JB		 8511 int entry = 0;
8512
66a9278e
DV		 8513 list_for_each_entry(source_encoder,
8514 &dev->mode_config.encoder_list, base.head) {
8515
8516 if (encoder == source_encoder)
79e53945 8517 index_mask |= (1 << entry);
66a9278e
DV		 8518
8519 /* Intel hw has only one MUX where enocoders could be cloned. */
8520 if (encoder->cloneable && source_encoder->cloneable)
8521 index_mask |= (1 << entry);
8522
79e53945
JB		 8523 entry++;
8524 }
4ef69c7a 8525
79e53945
JB		 8526 return index_mask;
8527}
8528
4d302442
CW		 8529static bool has_edp_a(struct drm_device *dev)
8530{
8531 struct drm_i915_private *dev_priv = dev->dev_private;
8532
8533 if (!IS_MOBILE(dev))
8534 return false;
8535
8536 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8537 return false;
8538
8539 if (IS_GEN5(dev) &&
8540 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8541 return false;
8542
8543 return true;
8544}
8545
79e53945
JB		 8546static void intel_setup_outputs(struct drm_device *dev)
8547{
725e30ad 8548 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8549 struct intel_encoder *encoder;
cb0953d7 8550 bool dpd_is_edp = false;
f3cfcba6 8551 bool has_lvds;
79e53945 8552
f3cfcba6 8553 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8554 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8555 /* disable the panel fitter on everything but LVDS */
8556 I915_WRITE(PFIT_CONTROL, 0);
8557 }
79e53945 8558
c40c0f5b 8559 if (!IS_ULT(dev))
79935fca 8560 intel_crt_init(dev);
cb0953d7 8561
affa9354 8562 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8563 int found;
8564
8565 /* Haswell uses DDI functions to detect digital outputs */
8566 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8567 /* DDI A only supports eDP */
8568 if (found)
8569 intel_ddi_init(dev, PORT_A);
8570
8571 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8572 * register */
8573 found = I915_READ(SFUSE_STRAP);
8574
8575 if (found & SFUSE_STRAP_DDIB_DETECTED)
8576 intel_ddi_init(dev, PORT_B);
8577 if (found & SFUSE_STRAP_DDIC_DETECTED)
8578 intel_ddi_init(dev, PORT_C);
8579 if (found & SFUSE_STRAP_DDID_DETECTED)
8580 intel_ddi_init(dev, PORT_D);
8581 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8582 int found;
270b3042
DV		 8583 dpd_is_edp = intel_dpd_is_edp(dev);
8584
8585 if (has_edp_a(dev))
8586 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8587
dc0fa718 8588 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8589 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8590 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8591 if (!found)
e2debe91 8592 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8593 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8594 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8595 }
8596
dc0fa718 8597 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8598 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8599
dc0fa718 8600 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8601 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8602
5eb08b69 8603 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8604 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8605
270b3042 8606 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8607 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8608 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8609 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8610 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8611 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8612
dc0fa718 8613 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8614 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8615 PORT_B);
67cfc203
VS		 8616 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8617 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8618 }
103a196f 8619 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8620 bool found = false;
7d57382e 8621
e2debe91 8622 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8623 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8624 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8625 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8626 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8627 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8628 }
27185ae1 8629
b01f2c3a
JB		 8630 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8631 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8632 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8633 }
725e30ad 8634 }
13520b05
KH		 8635
8636 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8637
e2debe91 8638 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8639 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8640 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8641 }
27185ae1 8642
e2debe91 8643 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8644
b01f2c3a
JB		 8645 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8646 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8647 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a
JB		 8648 }
8649 if (SUPPORTS_INTEGRATED_DP(dev)) {
8650 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8651 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8652 }
725e30ad 8653 }
27185ae1 8654
b01f2c3a
JB		 8655 if (SUPPORTS_INTEGRATED_DP(dev) &&
8656 (I915_READ(DP_D) & DP_DETECTED)) {
8657 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8658 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8659 }
bad720ff 8660 } else if (IS_GEN2(dev))
79e53945
JB		 8661 intel_dvo_init(dev);
8662
103a196f 8663 if (SUPPORTS_TV(dev))
79e53945
JB		 8664 intel_tv_init(dev);
8665
4ef69c7a
CW		 8666 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8667 encoder->base.possible_crtcs = encoder->crtc_mask;
8668 encoder->base.possible_clones =
66a9278e 8669 intel_encoder_clones(encoder);
79e53945 8670 }
47356eb6 8671
dde86e2d 8672 intel_init_pch_refclk(dev);
270b3042
DV		 8673
8674 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8675}
8676
8677static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8678{
8679 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8680
8681 drm_framebuffer_cleanup(fb);
05394f39 8682 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8683
8684 kfree(intel_fb);
8685}
8686
8687static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8688 struct drm_file *file,
79e53945
JB		 8689 unsigned int *handle)
8690{
8691 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8692 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8693
05394f39 8694 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8695}
8696
8697static const struct drm_framebuffer_funcs intel_fb_funcs = {
8698 .destroy = intel_user_framebuffer_destroy,
8699 .create_handle = intel_user_framebuffer_create_handle,
8700};
8701
38651674
DA		 8702int intel_framebuffer_init(struct drm_device *dev,
8703 struct intel_framebuffer *intel_fb,
308e5bcb 8704 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8705 struct drm_i915_gem_object *obj)
79e53945 8706{
79e53945
JB		 8707 int ret;
8708
c16ed4be
CW		 8709 if (obj->tiling_mode == I915_TILING_Y) {
8710 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8711 return -EINVAL;
c16ed4be 8712 }
57cd6508 8713
c16ed4be
CW		 8714 if (mode_cmd->pitches[0] & 63) {
8715 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8716 mode_cmd->pitches[0]);
57cd6508 8717 return -EINVAL;
c16ed4be 8718 }
57cd6508 8719
5d7bd705 8720 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8721 if (mode_cmd->pitches[0] > 32768) {
8722 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8723 mode_cmd->pitches[0]);
5d7bd705 8724 return -EINVAL;
c16ed4be 8725 }
5d7bd705
VS		 8726
8727 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8728 mode_cmd->pitches[0] != obj->stride) {
8729 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8730 mode_cmd->pitches[0], obj->stride);
5d7bd705 8731 return -EINVAL;
c16ed4be 8732 }
5d7bd705 8733
57779d06 8734 /* Reject formats not supported by any plane early. */
308e5bcb 8735 switch (mode_cmd->pixel_format) {
57779d06 8736 case DRM_FORMAT_C8:
04b3924d
VS		 8737 case DRM_FORMAT_RGB565:
8738 case DRM_FORMAT_XRGB8888:
8739 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8740 break;
8741 case DRM_FORMAT_XRGB1555:
8742 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8743 if (INTEL_INFO(dev)->gen > 3) {
8744 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8745 return -EINVAL;
c16ed4be 8746 }
57779d06
VS		 8747 break;
8748 case DRM_FORMAT_XBGR8888:
8749 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8750 case DRM_FORMAT_XRGB2101010:
8751 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8752 case DRM_FORMAT_XBGR2101010:
8753 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8754 if (INTEL_INFO(dev)->gen < 4) {
8755 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8756 return -EINVAL;
c16ed4be 8757 }
b5626747 8758 break;
04b3924d
VS		 8759 case DRM_FORMAT_YUYV:
8760 case DRM_FORMAT_UYVY:
8761 case DRM_FORMAT_YVYU:
8762 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8763 if (INTEL_INFO(dev)->gen < 5) {
8764 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8765 return -EINVAL;
c16ed4be 8766 }
57cd6508
CW		 8767 break;
8768 default:
c16ed4be 8769 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8770 return -EINVAL;
8771 }
8772
90f9a336
VS		 8773 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8774 if (mode_cmd->offsets[0] != 0)
8775 return -EINVAL;
8776
c7d73f6a
DV		 8777 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8778 intel_fb->obj = obj;
8779
79e53945
JB		 8780 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8781 if (ret) {
8782 DRM_ERROR("framebuffer init failed %d\n", ret);
8783 return ret;
8784 }
8785
79e53945
JB		 8786 return 0;
8787}
8788
79e53945
JB		 8789static struct drm_framebuffer *
8790intel_user_framebuffer_create(struct drm_device *dev,
8791 struct drm_file *filp,
308e5bcb 8792 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8793{
05394f39 8794 struct drm_i915_gem_object *obj;
79e53945 8795
308e5bcb
JB		 8796 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8797 mode_cmd->handles[0]));
c8725226 8798 if (&obj->base == NULL)
cce13ff7 8799 return ERR_PTR(-ENOENT);
79e53945 8800
d2dff872 8801 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8802}
8803
79e53945 8804static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8805 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8806 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8807};
8808
e70236a8
JB		 8809/* Set up chip specific display functions */
8810static void intel_init_display(struct drm_device *dev)
8811{
8812 struct drm_i915_private *dev_priv = dev->dev_private;
8813
affa9354 8814 if (HAS_DDI(dev)) {
0e8ffe1b 8815 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 8816 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8817 dev_priv->display.crtc_enable = haswell_crtc_enable;
8818 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8819 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8820 dev_priv->display.update_plane = ironlake_update_plane;
8821 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 8822 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 8823 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8824 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8825 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8826 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8827 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 8828 } else if (IS_VALLEYVIEW(dev)) {
8829 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
8830 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8831 dev_priv->display.crtc_enable = valleyview_crtc_enable;
8832 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8833 dev_priv->display.off = i9xx_crtc_off;
8834 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8835 } else {
0e8ffe1b 8836 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 8837 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8838 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8839 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8840 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8841 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8842 }
e70236a8 8843
e70236a8 8844 /* Returns the core display clock speed */
25eb05fc
JB		 8845 if (IS_VALLEYVIEW(dev))
8846 dev_priv->display.get_display_clock_speed =
8847 valleyview_get_display_clock_speed;
8848 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8849 dev_priv->display.get_display_clock_speed =
8850 i945_get_display_clock_speed;
8851 else if (IS_I915G(dev))
8852 dev_priv->display.get_display_clock_speed =
8853 i915_get_display_clock_speed;
f2b115e6 8854 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8855 dev_priv->display.get_display_clock_speed =
8856 i9xx_misc_get_display_clock_speed;
8857 else if (IS_I915GM(dev))
8858 dev_priv->display.get_display_clock_speed =
8859 i915gm_get_display_clock_speed;
8860 else if (IS_I865G(dev))
8861 dev_priv->display.get_display_clock_speed =
8862 i865_get_display_clock_speed;
f0f8a9ce 8863 else if (IS_I85X(dev))
e70236a8
JB		 8864 dev_priv->display.get_display_clock_speed =
8865 i855_get_display_clock_speed;
8866 else /* 852, 830 */
8867 dev_priv->display.get_display_clock_speed =
8868 i830_get_display_clock_speed;
8869
7f8a8569 8870 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8871 if (IS_GEN5(dev)) {
674cf967 8872 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8873 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8874 } else if (IS_GEN6(dev)) {
674cf967 8875 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8876 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8877 } else if (IS_IVYBRIDGE(dev)) {
8878 /* FIXME: detect B0+ stepping and use auto training */
8879 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8880 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8881 dev_priv->display.modeset_global_resources =
8882 ivb_modeset_global_resources;
c82e4d26
ED		 8883 } else if (IS_HASWELL(dev)) {
8884 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8885 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8886 dev_priv->display.modeset_global_resources =
8887 haswell_modeset_global_resources;
a0e63c22 8888 }
6067aaea 8889 } else if (IS_G4X(dev)) {
e0dac65e 8890 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8891 }
8c9f3aaf
JB		 8892
8893 /* Default just returns -ENODEV to indicate unsupported */
8894 dev_priv->display.queue_flip = intel_default_queue_flip;
8895
8896 switch (INTEL_INFO(dev)->gen) {
8897 case 2:
8898 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8899 break;
8900
8901 case 3:
8902 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8903 break;
8904
8905 case 4:
8906 case 5:
8907 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8908 break;
8909
8910 case 6:
8911 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8912 break;
7c9017e5
JB		 8913 case 7:
8914 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8915 break;
8c9f3aaf 8916 }
e70236a8
JB		 8917}
8918
b690e96c
JB		 8919/*
8920 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8921 * resume, or other times. This quirk makes sure that's the case for
8922 * affected systems.
8923 */
0206e353 8924static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8925{
8926 struct drm_i915_private *dev_priv = dev->dev_private;
8927
8928 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8929 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8930}
8931
435793df
KP		 8932/*
8933 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8934 */
8935static void quirk_ssc_force_disable(struct drm_device *dev)
8936{
8937 struct drm_i915_private *dev_priv = dev->dev_private;
8938 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8939 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8940}
8941
4dca20ef 8942/*
5a15ab5b
CE		 8943 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8944 * brightness value
4dca20ef
CE		 8945 */
8946static void quirk_invert_brightness(struct drm_device *dev)
8947{
8948 struct drm_i915_private *dev_priv = dev->dev_private;
8949 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8950 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8951}
8952
b690e96c
JB		 8953struct intel_quirk {
8954 int device;
8955 int subsystem_vendor;
8956 int subsystem_device;
8957 void (*hook)(struct drm_device *dev);
8958};
8959
5f85f176
EE		 8960/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8961struct intel_dmi_quirk {
8962 void (*hook)(struct drm_device *dev);
8963 const struct dmi_system_id (*dmi_id_list)[];
8964};
8965
8966static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8967{
8968 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8969 return 1;
8970}
8971
8972static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8973 {
8974 .dmi_id_list = &(const struct dmi_system_id[]) {
8975 {
8976 .callback = intel_dmi_reverse_brightness,
8977 .ident = "NCR Corporation",
8978 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8979 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8980 },
8981 },
8982 { } /* terminating entry */
8983 },
8984 .hook = quirk_invert_brightness,
8985 },
8986};
8987
c43b5634 8988static struct intel_quirk intel_quirks[] = {
b690e96c 8989 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8990 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8991
b690e96c
JB		 8992 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8993 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8994
b690e96c
JB		 8995 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8996 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8997
ccd0d36e 8998 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8999 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9000 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9001
9002 /* Lenovo U160 cannot use SSC on LVDS */
9003 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9004
9005 /* Sony Vaio Y cannot use SSC on LVDS */
9006 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9007
9008 /* Acer Aspire 5734Z must invert backlight brightness */
9009 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9010
9011 /* Acer/eMachines G725 */
9012 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9013
9014 /* Acer/eMachines e725 */
9015 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9016
9017 /* Acer/Packard Bell NCL20 */
9018 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9019
9020 /* Acer Aspire 4736Z */
9021 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9022};
9023
9024static void intel_init_quirks(struct drm_device *dev)
9025{
9026 struct pci_dev *d = dev->pdev;
9027 int i;
9028
9029 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9030 struct intel_quirk *q = &intel_quirks[i];
9031
9032 if (d->device == q->device &&
9033 (d->subsystem_vendor == q->subsystem_vendor ||
9034 q->subsystem_vendor == PCI_ANY_ID) &&
9035 (d->subsystem_device == q->subsystem_device ||
9036 q->subsystem_device == PCI_ANY_ID))
9037 q->hook(dev);
9038 }
5f85f176
EE		 9039 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9040 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9041 intel_dmi_quirks[i].hook(dev);
9042 }
b690e96c
JB		 9043}
9044
9cce37f4
JB		 9045/* Disable the VGA plane that we never use */
9046static void i915_disable_vga(struct drm_device *dev)
9047{
9048 struct drm_i915_private *dev_priv = dev->dev_private;
9049 u8 sr1;
766aa1c4 9050 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9051
9052 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9053 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9054 sr1 = inb(VGA_SR_DATA);
9055 outb(sr1 | 1<<5, VGA_SR_DATA);
9056 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9057 udelay(300);
9058
9059 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9060 POSTING_READ(vga_reg);
9061}
9062
f817586c
DV		 9063void intel_modeset_init_hw(struct drm_device *dev)
9064{
fa42e23c 9065 intel_init_power_well(dev);
0232e927 9066
a8f78b58
ED		 9067 intel_prepare_ddi(dev);
9068
f817586c
DV		 9069 intel_init_clock_gating(dev);
9070
79f5b2c7 9071 mutex_lock(&dev->struct_mutex);
8090c6b9 9072 intel_enable_gt_powersave(dev);
79f5b2c7 9073 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9074}
9075
79e53945
JB		 9076void intel_modeset_init(struct drm_device *dev)
9077{
652c393a 9078 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9079 int i, j, ret;
79e53945
JB		 9080
9081 drm_mode_config_init(dev);
9082
9083 dev->mode_config.min_width = 0;
9084 dev->mode_config.min_height = 0;
9085
019d96cb
DA		 9086 dev->mode_config.preferred_depth = 24;
9087 dev->mode_config.prefer_shadow = 1;
9088
e6ecefaa 9089 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9090
b690e96c
JB		 9091 intel_init_quirks(dev);
9092
1fa61106
ED		 9093 intel_init_pm(dev);
9094
e3c74757
BW		 9095 if (INTEL_INFO(dev)->num_pipes == 0)
9096 return;
9097
e70236a8
JB		 9098 intel_init_display(dev);
9099
a6c45cf0
CW		 9100 if (IS_GEN2(dev)) {
9101 dev->mode_config.max_width = 2048;
9102 dev->mode_config.max_height = 2048;
9103 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9104 dev->mode_config.max_width = 4096;
9105 dev->mode_config.max_height = 4096;
79e53945 9106 } else {
a6c45cf0
CW		 9107 dev->mode_config.max_width = 8192;
9108 dev->mode_config.max_height = 8192;
79e53945 9109 }
5d4545ae 9110 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9111
28c97730 9112 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9113 INTEL_INFO(dev)->num_pipes,
9114 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9115
7eb552ae 9116 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9117 intel_crtc_init(dev, i);
7f1f3851
JB		 9118 for (j = 0; j < dev_priv->num_plane; j++) {
9119 ret = intel_plane_init(dev, i, j);
9120 if (ret)
06da8da2
VS		 9121 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9122 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9123 }
79e53945
JB		 9124 }
9125
79f689aa 9126 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9127 intel_pch_pll_init(dev);
9128
9cce37f4
JB		 9129 /* Just disable it once at startup */
9130 i915_disable_vga(dev);
79e53945 9131 intel_setup_outputs(dev);
11be49eb
CW		 9132
9133 /* Just in case the BIOS is doing something questionable. */
9134 intel_disable_fbc(dev);
2c7111db
CW		 9135}
9136
24929352
DV		 9137static void
9138intel_connector_break_all_links(struct intel_connector *connector)
9139{
9140 connector->base.dpms = DRM_MODE_DPMS_OFF;
9141 connector->base.encoder = NULL;
9142 connector->encoder->connectors_active = false;
9143 connector->encoder->base.crtc = NULL;
9144}
9145
7fad798e
DV		 9146static void intel_enable_pipe_a(struct drm_device *dev)
9147{
9148 struct intel_connector *connector;
9149 struct drm_connector *crt = NULL;
9150 struct intel_load_detect_pipe load_detect_temp;
9151
9152 /* We can't just switch on the pipe A, we need to set things up with a
9153 * proper mode and output configuration. As a gross hack, enable pipe A
9154 * by enabling the load detect pipe once. */
9155 list_for_each_entry(connector,
9156 &dev->mode_config.connector_list,
9157 base.head) {
9158 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9159 crt = &connector->base;
9160 break;
9161 }
9162 }
9163
9164 if (!crt)
9165 return;
9166
9167 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9168 intel_release_load_detect_pipe(crt, &load_detect_temp);
9169
652c393a 9170
7fad798e
DV		 9171}
9172
fa555837
DV		 9173static bool
9174intel_check_plane_mapping(struct intel_crtc *crtc)
9175{
7eb552ae
BW		 9176 struct drm_device *dev = crtc->base.dev;
9177 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9178 u32 reg, val;
9179
7eb552ae 9180 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9181 return true;
9182
9183 reg = DSPCNTR(!crtc->plane);
9184 val = I915_READ(reg);
9185
9186 if ((val & DISPLAY_PLANE_ENABLE) &&
9187 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9188 return false;
9189
9190 return true;
9191}
9192
24929352
DV		 9193static void intel_sanitize_crtc(struct intel_crtc *crtc)
9194{
9195 struct drm_device *dev = crtc->base.dev;
9196 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9197 u32 reg;
24929352 9198
24929352 9199 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9200 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9201 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9202
9203 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9204 * disable the crtc (and hence change the state) if it is wrong. Note
9205 * that gen4+ has a fixed plane -> pipe mapping. */
9206 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9207 struct intel_connector *connector;
9208 bool plane;
9209
24929352
DV		 9210 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9211 crtc->base.base.id);
9212
9213 /* Pipe has the wrong plane attached and the plane is active.
9214 * Temporarily change the plane mapping and disable everything
9215 * ... */
9216 plane = crtc->plane;
9217 crtc->plane = !plane;
9218 dev_priv->display.crtc_disable(&crtc->base);
9219 crtc->plane = plane;
9220
9221 /* ... and break all links. */
9222 list_for_each_entry(connector, &dev->mode_config.connector_list,
9223 base.head) {
9224 if (connector->encoder->base.crtc != &crtc->base)
9225 continue;
9226
9227 intel_connector_break_all_links(connector);
9228 }
9229
9230 WARN_ON(crtc->active);
9231 crtc->base.enabled = false;
9232 }
24929352 9233
7fad798e
DV		 9234 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9235 crtc->pipe == PIPE_A && !crtc->active) {
9236 /* BIOS forgot to enable pipe A, this mostly happens after
9237 * resume. Force-enable the pipe to fix this, the update_dpms
9238 * call below we restore the pipe to the right state, but leave
9239 * the required bits on. */
9240 intel_enable_pipe_a(dev);
9241 }
9242
24929352
DV		 9243 /* Adjust the state of the output pipe according to whether we
9244 * have active connectors/encoders. */
9245 intel_crtc_update_dpms(&crtc->base);
9246
9247 if (crtc->active != crtc->base.enabled) {
9248 struct intel_encoder *encoder;
9249
9250 /* This can happen either due to bugs in the get_hw_state
9251 * functions or because the pipe is force-enabled due to the
9252 * pipe A quirk. */
9253 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9254 crtc->base.base.id,
9255 crtc->base.enabled ? "enabled" : "disabled",
9256 crtc->active ? "enabled" : "disabled");
9257
9258 crtc->base.enabled = crtc->active;
9259
9260 /* Because we only establish the connector -> encoder ->
9261 * crtc links if something is active, this means the
9262 * crtc is now deactivated. Break the links. connector
9263 * -> encoder links are only establish when things are
9264 * actually up, hence no need to break them. */
9265 WARN_ON(crtc->active);
9266
9267 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9268 WARN_ON(encoder->connectors_active);
9269 encoder->base.crtc = NULL;
9270 }
9271 }
9272}
9273
9274static void intel_sanitize_encoder(struct intel_encoder *encoder)
9275{
9276 struct intel_connector *connector;
9277 struct drm_device *dev = encoder->base.dev;
9278
9279 /* We need to check both for a crtc link (meaning that the
9280 * encoder is active and trying to read from a pipe) and the
9281 * pipe itself being active. */
9282 bool has_active_crtc = encoder->base.crtc &&
9283 to_intel_crtc(encoder->base.crtc)->active;
9284
9285 if (encoder->connectors_active && !has_active_crtc) {
9286 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9287 encoder->base.base.id,
9288 drm_get_encoder_name(&encoder->base));
9289
9290 /* Connector is active, but has no active pipe. This is
9291 * fallout from our resume register restoring. Disable
9292 * the encoder manually again. */
9293 if (encoder->base.crtc) {
9294 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9295 encoder->base.base.id,
9296 drm_get_encoder_name(&encoder->base));
9297 encoder->disable(encoder);
9298 }
9299
9300 /* Inconsistent output/port/pipe state happens presumably due to
9301 * a bug in one of the get_hw_state functions. Or someplace else
9302 * in our code, like the register restore mess on resume. Clamp
9303 * things to off as a safer default. */
9304 list_for_each_entry(connector,
9305 &dev->mode_config.connector_list,
9306 base.head) {
9307 if (connector->encoder != encoder)
9308 continue;
9309
9310 intel_connector_break_all_links(connector);
9311 }
9312 }
9313 /* Enabled encoders without active connectors will be fixed in
9314 * the crtc fixup. */
9315}
9316
44cec740 9317void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9318{
9319 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9320 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9321
9322 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9323 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9324 i915_disable_vga(dev);
0fde901f
KM		 9325 }
9326}
9327
24929352
DV		 9328/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9329 * and i915 state tracking structures. */
45e2b5f6
DV		 9330void intel_modeset_setup_hw_state(struct drm_device *dev,
9331 bool force_restore)
24929352
DV		 9332{
9333 struct drm_i915_private *dev_priv = dev->dev_private;
9334 enum pipe pipe;
9335 u32 tmp;
b5644d05 9336 struct drm_plane *plane;
24929352
DV		 9337 struct intel_crtc *crtc;
9338 struct intel_encoder *encoder;
9339 struct intel_connector *connector;
9340
affa9354 9341 if (HAS_DDI(dev)) {
e28d54cb
PZ		 9342 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9343
9344 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9345 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9346 case TRANS_DDI_EDP_INPUT_A_ON:
9347 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9348 pipe = PIPE_A;
9349 break;
9350 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9351 pipe = PIPE_B;
9352 break;
9353 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9354 pipe = PIPE_C;
9355 break;
aaa148ec
DL		 9356 default:
9357 /* A bogus value has been programmed, disable
9358 * the transcoder */
9359 WARN(1, "Bogus eDP source %08x\n", tmp);
9360 intel_ddi_disable_transcoder_func(dev_priv,
9361 TRANSCODER_EDP);
9362 goto setup_pipes;
e28d54cb
PZ		 9363 }
9364
9365 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
3b117c8f 9366 crtc->config.cpu_transcoder = TRANSCODER_EDP;
e28d54cb
PZ		 9367
9368 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9369 pipe_name(pipe));
9370 }
9371 }
9372
aaa148ec 9373setup_pipes:
0e8ffe1b
DV		 9374 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9375 base.head) {
3b117c8f 9376 enum transcoder tmp = crtc->config.cpu_transcoder;
88adfff1 9377 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f
DV		 9378 crtc->config.cpu_transcoder = tmp;
9379
0e8ffe1b
DV		 9380 crtc->active = dev_priv->display.get_pipe_config(crtc,
9381 &crtc->config);
24929352
DV		 9382
9383 crtc->base.enabled = crtc->active;
9384
9385 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9386 crtc->base.base.id,
9387 crtc->active ? "enabled" : "disabled");
9388 }
9389
affa9354 9390 if (HAS_DDI(dev))
6441ab5f
PZ		 9391 intel_ddi_setup_hw_pll_state(dev);
9392
24929352
DV		 9393 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9394 base.head) {
9395 pipe = 0;
9396
9397 if (encoder->get_hw_state(encoder, &pipe)) {
9398 encoder->base.crtc =
9399 dev_priv->pipe_to_crtc_mapping[pipe];
9400 } else {
9401 encoder->base.crtc = NULL;
9402 }
9403
9404 encoder->connectors_active = false;
9405 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9406 encoder->base.base.id,
9407 drm_get_encoder_name(&encoder->base),
9408 encoder->base.crtc ? "enabled" : "disabled",
9409 pipe);
9410 }
9411
9412 list_for_each_entry(connector, &dev->mode_config.connector_list,
9413 base.head) {
9414 if (connector->get_hw_state(connector)) {
9415 connector->base.dpms = DRM_MODE_DPMS_ON;
9416 connector->encoder->connectors_active = true;
9417 connector->base.encoder = &connector->encoder->base;
9418 } else {
9419 connector->base.dpms = DRM_MODE_DPMS_OFF;
9420 connector->base.encoder = NULL;
9421 }
9422 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9423 connector->base.base.id,
9424 drm_get_connector_name(&connector->base),
9425 connector->base.encoder ? "enabled" : "disabled");
9426 }
9427
9428 /* HW state is read out, now we need to sanitize this mess. */
9429 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9430 base.head) {
9431 intel_sanitize_encoder(encoder);
9432 }
9433
9434 for_each_pipe(pipe) {
9435 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9436 intel_sanitize_crtc(crtc);
9437 }
9a935856 9438
45e2b5f6 9439 if (force_restore) {
f30da187
DV		 9440 /*
9441 * We need to use raw interfaces for restoring state to avoid
9442 * checking (bogus) intermediate states.
9443 */
45e2b5f6 9444 for_each_pipe(pipe) {
b5644d05
JB		 9445 struct drm_crtc *crtc =
9446 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9447
9448 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9449 crtc->fb);
45e2b5f6 9450 }
b5644d05
JB		 9451 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9452 intel_plane_restore(plane);
0fde901f
KM		 9453
9454 i915_redisable_vga(dev);
45e2b5f6
DV		 9455 } else {
9456 intel_modeset_update_staged_output_state(dev);
9457 }
8af6cf88
DV		 9458
9459 intel_modeset_check_state(dev);
2e938892
DV		 9460
9461 drm_mode_config_reset(dev);
2c7111db
CW		 9462}
9463
9464void intel_modeset_gem_init(struct drm_device *dev)
9465{
1833b134 9466 intel_modeset_init_hw(dev);
02e792fb
DV		 9467
9468 intel_setup_overlay(dev);
24929352 9469
45e2b5f6 9470 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9471}
9472
9473void intel_modeset_cleanup(struct drm_device *dev)
9474{
652c393a
JB		 9475 struct drm_i915_private *dev_priv = dev->dev_private;
9476 struct drm_crtc *crtc;
9477 struct intel_crtc *intel_crtc;
9478
fd0c0642
DV		 9479 /*
9480 * Interrupts and polling as the first thing to avoid creating havoc.
9481 * Too much stuff here (turning of rps, connectors, ...) would
9482 * experience fancy races otherwise.
9483 */
9484 drm_irq_uninstall(dev);
9485 cancel_work_sync(&dev_priv->hotplug_work);
9486 /*
9487 * Due to the hpd irq storm handling the hotplug work can re-arm the
9488 * poll handlers. Hence disable polling after hpd handling is shut down.
9489 */
f87ea761 9490 drm_kms_helper_poll_fini(dev);
fd0c0642 9491
652c393a
JB		 9492 mutex_lock(&dev->struct_mutex);
9493
723bfd70
JB		 9494 intel_unregister_dsm_handler();
9495
652c393a
JB		 9496 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9497 /* Skip inactive CRTCs */
9498 if (!crtc->fb)
9499 continue;
9500
9501 intel_crtc = to_intel_crtc(crtc);
3dec0095 9502 intel_increase_pllclock(crtc);
652c393a
JB		 9503 }
9504
973d04f9 9505 intel_disable_fbc(dev);
e70236a8 9506
8090c6b9 9507 intel_disable_gt_powersave(dev);
0cdab21f 9508
930ebb46
DV		 9509 ironlake_teardown_rc6(dev);
9510
69341a5e
KH		 9511 mutex_unlock(&dev->struct_mutex);
9512
1630fe75
CW		 9513 /* flush any delayed tasks or pending work */
9514 flush_scheduled_work();
9515
dc652f90
JN		 9516 /* destroy backlight, if any, before the connectors */
9517 intel_panel_destroy_backlight(dev);
9518
79e53945 9519 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9520
9521 intel_cleanup_overlay(dev);
79e53945
JB		 9522}
9523
f1c79df3
ZW		 9524/*
9525 * Return which encoder is currently attached for connector.
9526 */
df0e9248 9527struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9528{
df0e9248
CW		 9529 return &intel_attached_encoder(connector)->base;
9530}
f1c79df3 9531
df0e9248
CW		 9532void intel_connector_attach_encoder(struct intel_connector *connector,
9533 struct intel_encoder *encoder)
9534{
9535 connector->encoder = encoder;
9536 drm_mode_connector_attach_encoder(&connector->base,
9537 &encoder->base);
79e53945 9538}
28d52043
DA		 9539
9540/*
9541 * set vga decode state - true == enable VGA decode
9542 */
9543int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9544{
9545 struct drm_i915_private *dev_priv = dev->dev_private;
9546 u16 gmch_ctrl;
9547
9548 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9549 if (state)
9550 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9551 else
9552 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9553 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9554 return 0;
9555}
c4a1d9e4
CW		 9556
9557#ifdef CONFIG_DEBUG_FS
9558#include <linux/seq_file.h>
9559
9560struct intel_display_error_state {
9561 struct intel_cursor_error_state {
9562 u32 control;
9563 u32 position;
9564 u32 base;
9565 u32 size;
52331309 9566 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9567
9568 struct intel_pipe_error_state {
9569 u32 conf;
9570 u32 source;
9571
9572 u32 htotal;
9573 u32 hblank;
9574 u32 hsync;
9575 u32 vtotal;
9576 u32 vblank;
9577 u32 vsync;
52331309 9578 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9579
9580 struct intel_plane_error_state {
9581 u32 control;
9582 u32 stride;
9583 u32 size;
9584 u32 pos;
9585 u32 addr;
9586 u32 surface;
9587 u32 tile_offset;
52331309 9588 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9589};
9590
9591struct intel_display_error_state *
9592intel_display_capture_error_state(struct drm_device *dev)
9593{
0206e353 9594 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9595 struct intel_display_error_state *error;
702e7a56 9596 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9597 int i;
9598
9599 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9600 if (error == NULL)
9601 return NULL;
9602
52331309 9603 for_each_pipe(i) {
702e7a56
PZ		 9604 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9605
a18c4c3d
PZ		 9606 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9607 error->cursor[i].control = I915_READ(CURCNTR(i));
9608 error->cursor[i].position = I915_READ(CURPOS(i));
9609 error->cursor[i].base = I915_READ(CURBASE(i));
9610 } else {
9611 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9612 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9613 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9614 }
c4a1d9e4
CW		 9615
9616 error->plane[i].control = I915_READ(DSPCNTR(i));
9617 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9618 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9619 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9620 error->plane[i].pos = I915_READ(DSPPOS(i));
9621 }
ca291363
PZ		 9622 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9623 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9624 if (INTEL_INFO(dev)->gen >= 4) {
9625 error->plane[i].surface = I915_READ(DSPSURF(i));
9626 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9627 }
9628
702e7a56 9629 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9630 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9631 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9632 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9633 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9634 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9635 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9636 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9637 }
9638
9639 return error;
9640}
9641
9642void
9643intel_display_print_error_state(struct seq_file *m,
9644 struct drm_device *dev,
9645 struct intel_display_error_state *error)
9646{
9647 int i;
9648
7eb552ae 9649 seq_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
52331309 9650 for_each_pipe(i) {
c4a1d9e4
CW		 9651 seq_printf(m, "Pipe [%d]:\n", i);
9652 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9653 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9654 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9655 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9656 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9657 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9658 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9659 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9660
9661 seq_printf(m, "Plane [%d]:\n", i);
9662 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9663 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9664 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9665 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
80ca378b
PZ		 9666 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9667 }
4b71a570 9668 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
ca291363 9669 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4
CW		 9670 if (INTEL_INFO(dev)->gen >= 4) {
9671 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9672 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9673 }
9674
9675 seq_printf(m, "Cursor [%d]:\n", i);
9676 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9677 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9678 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9679 }
9680}
9681#endif
Linux kernel - Deliverables
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