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drm/i915: pass mode to ELD write vfuncs
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
3dec0095 44static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 45static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 46
f1f644dc
JB		 47static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
18442d08
VS		 49static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
f1f644dc 51
e7457a9a
DL		 52static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54
55
79e53945 56typedef struct {
0206e353 57 int min, max;
79e53945
JB		 58} intel_range_t;
59
60typedef struct {
0206e353
AJ		 61 int dot_limit;
62 int p2_slow, p2_fast;
79e53945
JB		 63} intel_p2_t;
64
d4906093
ML		 65typedef struct intel_limit intel_limit_t;
66struct intel_limit {
0206e353
AJ		 67 intel_range_t dot, vco, n, m, m1, m2, p, p1;
68 intel_p2_t p2;
d4906093 69};
79e53945 70
d2acd215
DV		 71int
72intel_pch_rawclk(struct drm_device *dev)
73{
74 struct drm_i915_private *dev_priv = dev->dev_private;
75
76 WARN_ON(!HAS_PCH_SPLIT(dev));
77
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
79}
80
021357ac
CW		 81static inline u32 /* units of 100MHz */
82intel_fdi_link_freq(struct drm_device *dev)
83{
8b99e68c
CW		 84 if (IS_GEN5(dev)) {
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
87 } else
88 return 27;
021357ac
CW		 89}
90
5d536e28 91static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 92 .dot = { .min = 25000, .max = 350000 },
93 .vco = { .min = 930000, .max = 1400000 },
94 .n = { .min = 3, .max = 16 },
95 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 102};
103
5d536e28
DV		 104static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
106 .vco = { .min = 930000, .max = 1400000 },
107 .n = { .min = 3, .max = 16 },
108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
115};
116
e4b36699 117static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 118 .dot = { .min = 25000, .max = 350000 },
119 .vco = { .min = 930000, .max = 1400000 },
120 .n = { .min = 3, .max = 16 },
121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
e4b36699 128};
273e27ca 129
e4b36699 130static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 141};
142
143static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 154};
155
273e27ca 156
e4b36699 157static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
167 .p2_slow = 10,
168 .p2_fast = 10
044c7c41 169 },
e4b36699
KP		 170};
171
172static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 183};
184
185static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
044c7c41 196 },
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
044c7c41 210 },
e4b36699
KP		 211};
212
f2b115e6 213static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 216 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
273e27ca 219 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 226};
227
f2b115e6 228static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 239};
240
273e27ca
EA		 241/* Ironlake / Sandybridge
242 *
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
245 */
b91ad0ec 246static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 257};
258
b91ad0ec 259static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 270};
271
272static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 283};
284
273e27ca 285/* LVDS 100mhz refclk limits. */
b91ad0ec 286static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
0206e353 294 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
0206e353 307 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 310};
311
dc730512 312static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 313 /*
314 * These are the data rate limits (measured in fast clocks)
315 * since those are the strictest limits we have. The fast
316 * clock and actual rate limits are more relaxed, so checking
317 * them would make no difference.
318 */
319 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 320 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 321 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 322 .m1 = { .min = 2, .max = 3 },
323 .m2 = { .min = 11, .max = 156 },
b99ab663 324 .p1 = { .min = 2, .max = 3 },
5fdc9c49 325 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 326};
327
6b4bf1c4
VS		 328static void vlv_clock(int refclk, intel_clock_t *clock)
329{
330 clock->m = clock->m1 * clock->m2;
331 clock->p = clock->p1 * clock->p2;
fb03ac01
VS		 332 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
333 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 334}
335
e0638cdf
PZ		 336/**
337 * Returns whether any output on the specified pipe is of the specified type
338 */
339static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
340{
341 struct drm_device *dev = crtc->dev;
342 struct intel_encoder *encoder;
343
344 for_each_encoder_on_crtc(dev, crtc, encoder)
345 if (encoder->type == type)
346 return true;
347
348 return false;
349}
350
1b894b59
CW		 351static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
352 int refclk)
2c07245f 353{
b91ad0ec 354 struct drm_device *dev = crtc->dev;
2c07245f 355 const intel_limit_t *limit;
b91ad0ec
ZW		 356
357 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 358 if (intel_is_dual_link_lvds(dev)) {
1b894b59 359 if (refclk == 100000)
b91ad0ec
ZW		 360 limit = &intel_limits_ironlake_dual_lvds_100m;
361 else
362 limit = &intel_limits_ironlake_dual_lvds;
363 } else {
1b894b59 364 if (refclk == 100000)
b91ad0ec
ZW		 365 limit = &intel_limits_ironlake_single_lvds_100m;
366 else
367 limit = &intel_limits_ironlake_single_lvds;
368 }
c6bb3538 369 } else
b91ad0ec 370 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 371
372 return limit;
373}
374
044c7c41
ML		 375static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
376{
377 struct drm_device *dev = crtc->dev;
044c7c41
ML		 378 const intel_limit_t *limit;
379
380 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 381 if (intel_is_dual_link_lvds(dev))
e4b36699 382 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 383 else
e4b36699 384 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 385 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
386 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 387 limit = &intel_limits_g4x_hdmi;
044c7c41 388 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 389 limit = &intel_limits_g4x_sdvo;
044c7c41 390 } else /* The option is for other outputs */
e4b36699 391 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 392
393 return limit;
394}
395
1b894b59 396static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 397{
398 struct drm_device *dev = crtc->dev;
399 const intel_limit_t *limit;
400
bad720ff 401 if (HAS_PCH_SPLIT(dev))
1b894b59 402 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 403 else if (IS_G4X(dev)) {
044c7c41 404 limit = intel_g4x_limit(crtc);
f2b115e6 405 } else if (IS_PINEVIEW(dev)) {
2177832f 406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 407 limit = &intel_limits_pineview_lvds;
2177832f 408 else
f2b115e6 409 limit = &intel_limits_pineview_sdvo;
a0c4da24 410 } else if (IS_VALLEYVIEW(dev)) {
dc730512 411 limit = &intel_limits_vlv;
a6c45cf0
CW		 412 } else if (!IS_GEN2(dev)) {
413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
414 limit = &intel_limits_i9xx_lvds;
415 else
416 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 417 } else {
418 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 419 limit = &intel_limits_i8xx_lvds;
5d536e28 420 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 421 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 422 else
423 limit = &intel_limits_i8xx_dac;
79e53945
JB		 424 }
425 return limit;
426}
427
f2b115e6
AJ		 428/* m1 is reserved as 0 in Pineview, n is a ring counter */
429static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 430{
2177832f
SL		 431 clock->m = clock->m2 + 2;
432 clock->p = clock->p1 * clock->p2;
fb03ac01
VS		 433 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
434 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 435}
436
7429e9d4
DV		 437static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
438{
439 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
440}
441
ac58c3f0 442static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 443{
7429e9d4 444 clock->m = i9xx_dpll_compute_m(clock);
79e53945 445 clock->p = clock->p1 * clock->p2;
fb03ac01
VS		 446 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
447 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 448}
449
7c04d1d9 450#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 451/**
452 * Returns whether the given set of divisors are valid for a given refclk with
453 * the given connectors.
454 */
455
1b894b59
CW		 456static bool intel_PLL_is_valid(struct drm_device *dev,
457 const intel_limit_t *limit,
458 const intel_clock_t *clock)
79e53945 459{
f01b7962
VS		 460 if (clock->n < limit->n.min || limit->n.max < clock->n)
461 INTELPllInvalid("n out of range\n");
79e53945 462 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 463 INTELPllInvalid("p1 out of range\n");
79e53945 464 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 465 INTELPllInvalid("m2 out of range\n");
79e53945 466 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 467 INTELPllInvalid("m1 out of range\n");
f01b7962
VS		 468
469 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
470 if (clock->m1 <= clock->m2)
471 INTELPllInvalid("m1 <= m2\n");
472
473 if (!IS_VALLEYVIEW(dev)) {
474 if (clock->p < limit->p.min || limit->p.max < clock->p)
475 INTELPllInvalid("p out of range\n");
476 if (clock->m < limit->m.min || limit->m.max < clock->m)
477 INTELPllInvalid("m out of range\n");
478 }
479
79e53945 480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 481 INTELPllInvalid("vco out of range\n");
79e53945
JB		 482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
484 */
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 486 INTELPllInvalid("dot out of range\n");
79e53945
JB		 487
488 return true;
489}
490
d4906093 491static bool
ee9300bb 492i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
79e53945
JB		 495{
496 struct drm_device *dev = crtc->dev;
79e53945 497 intel_clock_t clock;
79e53945
JB		 498 int err = target;
499
a210b028 500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 501 /*
a210b028
DV		 502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
79e53945 505 */
1974cad0 506 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 507 clock.p2 = limit->p2.p2_fast;
508 else
509 clock.p2 = limit->p2.p2_slow;
510 } else {
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
513 else
514 clock.p2 = limit->p2.p2_fast;
515 }
516
0206e353 517 memset(best_clock, 0, sizeof(*best_clock));
79e53945 518
42158660
ZY		 519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
520 clock.m1++) {
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 523 if (clock.m2 >= clock.m1)
42158660
ZY		 524 break;
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 529 int this_err;
530
ac58c3f0
DV		 531 i9xx_clock(refclk, &clock);
532 if (!intel_PLL_is_valid(dev, limit,
533 &clock))
534 continue;
535 if (match_clock &&
536 clock.p != match_clock->p)
537 continue;
538
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
541 *best_clock = clock;
542 err = this_err;
543 }
544 }
545 }
546 }
547 }
548
549 return (err != target);
550}
551
552static bool
ee9300bb
DV		 553pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
79e53945
JB		 556{
557 struct drm_device *dev = crtc->dev;
79e53945 558 intel_clock_t clock;
79e53945
JB		 559 int err = target;
560
a210b028 561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 562 /*
a210b028
DV		 563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
79e53945 566 */
1974cad0 567 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 568 clock.p2 = limit->p2.p2_fast;
569 else
570 clock.p2 = limit->p2.p2_slow;
571 } else {
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
574 else
575 clock.p2 = limit->p2.p2_fast;
576 }
577
0206e353 578 memset(best_clock, 0, sizeof(*best_clock));
79e53945 579
42158660
ZY		 580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
581 clock.m1++) {
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 588 int this_err;
589
ac58c3f0 590 pineview_clock(refclk, &clock);
1b894b59
CW		 591 if (!intel_PLL_is_valid(dev, limit,
592 &clock))
79e53945 593 continue;
cec2f356
SP		 594 if (match_clock &&
595 clock.p != match_clock->p)
596 continue;
79e53945
JB		 597
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
600 *best_clock = clock;
601 err = this_err;
602 }
603 }
604 }
605 }
606 }
607
608 return (err != target);
609}
610
d4906093 611static bool
ee9300bb
DV		 612g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
d4906093
ML		 615{
616 struct drm_device *dev = crtc->dev;
d4906093
ML		 617 intel_clock_t clock;
618 int max_n;
619 bool found;
6ba770dc
AJ		 620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 622 found = false;
623
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 625 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 626 clock.p2 = limit->p2.p2_fast;
627 else
628 clock.p2 = limit->p2.p2_slow;
629 } else {
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
632 else
633 clock.p2 = limit->p2.p2_fast;
634 }
635
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
f77f13e2 638 /* based on hardware requirement, prefer smaller n to precision */
d4906093 639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 640 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
647 int this_err;
648
ac58c3f0 649 i9xx_clock(refclk, &clock);
1b894b59
CW		 650 if (!intel_PLL_is_valid(dev, limit,
651 &clock))
d4906093 652 continue;
1b894b59
CW		 653
654 this_err = abs(clock.dot - target);
d4906093
ML		 655 if (this_err < err_most) {
656 *best_clock = clock;
657 err_most = this_err;
658 max_n = clock.n;
659 found = true;
660 }
661 }
662 }
663 }
664 }
2c07245f
ZW		 665 return found;
666}
667
a0c4da24 668static bool
ee9300bb
DV		 669vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
a0c4da24 672{
f01b7962 673 struct drm_device *dev = crtc->dev;
6b4bf1c4 674 intel_clock_t clock;
69e4f900 675 unsigned int bestppm = 1000000;
27e639bf
VS		 676 /* min update 19.2 MHz */
677 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 678 bool found = false;
a0c4da24 679
6b4bf1c4
VS		 680 target *= 5; /* fast clock */
681
682 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 683
684 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 685 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 686 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 687 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 688 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 689 clock.p = clock.p1 * clock.p2;
a0c4da24 690 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
69e4f900
VS		 692 unsigned int ppm, diff;
693
6b4bf1c4
VS		 694 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
695 refclk * clock.m1);
696
697 vlv_clock(refclk, &clock);
43b0ac53 698
f01b7962
VS		 699 if (!intel_PLL_is_valid(dev, limit,
700 &clock))
43b0ac53
VS		 701 continue;
702
6b4bf1c4
VS		 703 diff = abs(clock.dot - target);
704 ppm = div_u64(1000000ULL * diff, target);
705
706 if (ppm < 100 && clock.p > best_clock->p) {
43b0ac53 707 bestppm = 0;
6b4bf1c4 708 *best_clock = clock;
49e497ef 709 found = true;
43b0ac53 710 }
6b4bf1c4 711
c686122c 712 if (bestppm >= 10 && ppm < bestppm - 10) {
69e4f900 713 bestppm = ppm;
6b4bf1c4 714 *best_clock = clock;
49e497ef 715 found = true;
a0c4da24
JB		 716 }
717 }
718 }
719 }
720 }
a0c4da24 721
49e497ef 722 return found;
a0c4da24 723}
a4fc5ed6 724
20ddf665
VS		 725bool intel_crtc_active(struct drm_crtc *crtc)
726{
727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
728
729 /* Be paranoid as we can arrive here with only partial
730 * state retrieved from the hardware during setup.
731 *
241bfc38 732 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 733 * as Haswell has gained clock readout/fastboot support.
734 *
735 * We can ditch the crtc->fb check as soon as we can
736 * properly reconstruct framebuffers.
737 */
738 return intel_crtc->active && crtc->fb &&
241bfc38 739 intel_crtc->config.adjusted_mode.crtc_clock;
20ddf665
VS		 740}
741
a5c961d1
PZ		 742enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
743 enum pipe pipe)
744{
745 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
747
3b117c8f 748 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 749}
750
a928d536
PZ		 751static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
752{
753 struct drm_i915_private *dev_priv = dev->dev_private;
754 u32 frame, frame_reg = PIPEFRAME(pipe);
755
756 frame = I915_READ(frame_reg);
757
758 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
759 DRM_DEBUG_KMS("vblank wait timed out\n");
760}
761
9d0498a2
JB		 762/**
763 * intel_wait_for_vblank - wait for vblank on a given pipe
764 * @dev: drm device
765 * @pipe: pipe to wait for
766 *
767 * Wait for vblank to occur on a given pipe. Needed for various bits of
768 * mode setting code.
769 */
770void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 771{
9d0498a2 772 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 773 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 774
a928d536
PZ		 775 if (INTEL_INFO(dev)->gen >= 5) {
776 ironlake_wait_for_vblank(dev, pipe);
777 return;
778 }
779
300387c0
CW		 780 /* Clear existing vblank status. Note this will clear any other
781 * sticky status fields as well.
782 *
783 * This races with i915_driver_irq_handler() with the result
784 * that either function could miss a vblank event. Here it is not
785 * fatal, as we will either wait upon the next vblank interrupt or
786 * timeout. Generally speaking intel_wait_for_vblank() is only
787 * called during modeset at which time the GPU should be idle and
788 * should *not* be performing page flips and thus not waiting on
789 * vblanks...
790 * Currently, the result of us stealing a vblank from the irq
791 * handler is that a single frame will be skipped during swapbuffers.
792 */
793 I915_WRITE(pipestat_reg,
794 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
795
9d0498a2 796 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 797 if (wait_for(I915_READ(pipestat_reg) &
798 PIPE_VBLANK_INTERRUPT_STATUS,
799 50))
9d0498a2
JB		 800 DRM_DEBUG_KMS("vblank wait timed out\n");
801}
802
fbf49ea2
VS		 803static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
804{
805 struct drm_i915_private *dev_priv = dev->dev_private;
806 u32 reg = PIPEDSL(pipe);
807 u32 line1, line2;
808 u32 line_mask;
809
810 if (IS_GEN2(dev))
811 line_mask = DSL_LINEMASK_GEN2;
812 else
813 line_mask = DSL_LINEMASK_GEN3;
814
815 line1 = I915_READ(reg) & line_mask;
816 mdelay(5);
817 line2 = I915_READ(reg) & line_mask;
818
819 return line1 == line2;
820}
821
ab7ad7f6
KP		 822/*
823 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 824 * @dev: drm device
825 * @pipe: pipe to wait for
826 *
827 * After disabling a pipe, we can't wait for vblank in the usual way,
828 * spinning on the vblank interrupt status bit, since we won't actually
829 * see an interrupt when the pipe is disabled.
830 *
ab7ad7f6
KP		 831 * On Gen4 and above:
832 * wait for the pipe register state bit to turn off
833 *
834 * Otherwise:
835 * wait for the display line value to settle (it usually
836 * ends up stopping at the start of the next frame).
58e10eb9 837 *
9d0498a2 838 */
58e10eb9 839void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 840{
841 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 842 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
843 pipe);
ab7ad7f6
KP		 844
845 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 846 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 847
848 /* Wait for the Pipe State to go off */
58e10eb9
CW		 849 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
850 100))
284637d9 851 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 852 } else {
ab7ad7f6 853 /* Wait for the display line to settle */
fbf49ea2 854 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 855 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 856 }
79e53945
JB		 857}
858
b0ea7d37
DL		 859/*
860 * ibx_digital_port_connected - is the specified port connected?
861 * @dev_priv: i915 private structure
862 * @port: the port to test
863 *
864 * Returns true if @port is connected, false otherwise.
865 */
866bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
867 struct intel_digital_port *port)
868{
869 u32 bit;
870
c36346e3
DL		 871 if (HAS_PCH_IBX(dev_priv->dev)) {
872 switch(port->port) {
873 case PORT_B:
874 bit = SDE_PORTB_HOTPLUG;
875 break;
876 case PORT_C:
877 bit = SDE_PORTC_HOTPLUG;
878 break;
879 case PORT_D:
880 bit = SDE_PORTD_HOTPLUG;
881 break;
882 default:
883 return true;
884 }
885 } else {
886 switch(port->port) {
887 case PORT_B:
888 bit = SDE_PORTB_HOTPLUG_CPT;
889 break;
890 case PORT_C:
891 bit = SDE_PORTC_HOTPLUG_CPT;
892 break;
893 case PORT_D:
894 bit = SDE_PORTD_HOTPLUG_CPT;
895 break;
896 default:
897 return true;
898 }
b0ea7d37
DL		 899 }
900
901 return I915_READ(SDEISR) & bit;
902}
903
b24e7179
JB		 904static const char *state_string(bool enabled)
905{
906 return enabled ? "on" : "off";
907}
908
909/* Only for pre-ILK configs */
55607e8a
DV		 910void assert_pll(struct drm_i915_private *dev_priv,
911 enum pipe pipe, bool state)
b24e7179
JB		 912{
913 int reg;
914 u32 val;
915 bool cur_state;
916
917 reg = DPLL(pipe);
918 val = I915_READ(reg);
919 cur_state = !!(val & DPLL_VCO_ENABLE);
920 WARN(cur_state != state,
921 "PLL state assertion failure (expected %s, current %s)\n",
922 state_string(state), state_string(cur_state));
923}
b24e7179 924
23538ef1
JN		 925/* XXX: the dsi pll is shared between MIPI DSI ports */
926static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
927{
928 u32 val;
929 bool cur_state;
930
931 mutex_lock(&dev_priv->dpio_lock);
932 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
933 mutex_unlock(&dev_priv->dpio_lock);
934
935 cur_state = val & DSI_PLL_VCO_EN;
936 WARN(cur_state != state,
937 "DSI PLL state assertion failure (expected %s, current %s)\n",
938 state_string(state), state_string(cur_state));
939}
940#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
941#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
942
55607e8a 943struct intel_shared_dpll *
e2b78267
DV		 944intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
945{
946 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
947
a43f6e0f 948 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 949 return NULL;
950
a43f6e0f 951 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 952}
953
040484af 954/* For ILK+ */
55607e8a
DV		 955void assert_shared_dpll(struct drm_i915_private *dev_priv,
956 struct intel_shared_dpll *pll,
957 bool state)
040484af 958{
040484af 959 bool cur_state;
5358901f 960 struct intel_dpll_hw_state hw_state;
040484af 961
9d82aa17
ED		 962 if (HAS_PCH_LPT(dev_priv->dev)) {
963 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
964 return;
965 }
966
92b27b08 967 if (WARN (!pll,
46edb027 968 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 969 return;
ee7b9f93 970
5358901f 971 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 972 WARN(cur_state != state,
5358901f
DV		 973 "%s assertion failure (expected %s, current %s)\n",
974 pll->name, state_string(state), state_string(cur_state));
040484af 975}
040484af
JB		 976
977static void assert_fdi_tx(struct drm_i915_private *dev_priv,
978 enum pipe pipe, bool state)
979{
980 int reg;
981 u32 val;
982 bool cur_state;
ad80a810
PZ		 983 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
984 pipe);
040484af 985
affa9354
PZ		 986 if (HAS_DDI(dev_priv->dev)) {
987 /* DDI does not have a specific FDI_TX register */
ad80a810 988 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 989 val = I915_READ(reg);
ad80a810 990 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 991 } else {
992 reg = FDI_TX_CTL(pipe);
993 val = I915_READ(reg);
994 cur_state = !!(val & FDI_TX_ENABLE);
995 }
040484af
JB		 996 WARN(cur_state != state,
997 "FDI TX state assertion failure (expected %s, current %s)\n",
998 state_string(state), state_string(cur_state));
999}
1000#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1001#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1002
1003static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1004 enum pipe pipe, bool state)
1005{
1006 int reg;
1007 u32 val;
1008 bool cur_state;
1009
d63fa0dc
PZ		 1010 reg = FDI_RX_CTL(pipe);
1011 val = I915_READ(reg);
1012 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1013 WARN(cur_state != state,
1014 "FDI RX state assertion failure (expected %s, current %s)\n",
1015 state_string(state), state_string(cur_state));
1016}
1017#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1018#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1019
1020static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1021 enum pipe pipe)
1022{
1023 int reg;
1024 u32 val;
1025
1026 /* ILK FDI PLL is always enabled */
1027 if (dev_priv->info->gen == 5)
1028 return;
1029
bf507ef7 1030 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1031 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1032 return;
1033
040484af
JB		 1034 reg = FDI_TX_CTL(pipe);
1035 val = I915_READ(reg);
1036 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1037}
1038
55607e8a
DV		 1039void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1040 enum pipe pipe, bool state)
040484af
JB		 1041{
1042 int reg;
1043 u32 val;
55607e8a 1044 bool cur_state;
040484af
JB		 1045
1046 reg = FDI_RX_CTL(pipe);
1047 val = I915_READ(reg);
55607e8a
DV		 1048 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1049 WARN(cur_state != state,
1050 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1051 state_string(state), state_string(cur_state));
040484af
JB		 1052}
1053
ea0760cf
JB		 1054static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1055 enum pipe pipe)
1056{
1057 int pp_reg, lvds_reg;
1058 u32 val;
1059 enum pipe panel_pipe = PIPE_A;
0de3b485 1060 bool locked = true;
ea0760cf
JB		 1061
1062 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1063 pp_reg = PCH_PP_CONTROL;
1064 lvds_reg = PCH_LVDS;
1065 } else {
1066 pp_reg = PP_CONTROL;
1067 lvds_reg = LVDS;
1068 }
1069
1070 val = I915_READ(pp_reg);
1071 if (!(val & PANEL_POWER_ON) ||
1072 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1073 locked = false;
1074
1075 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1076 panel_pipe = PIPE_B;
1077
1078 WARN(panel_pipe == pipe && locked,
1079 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1080 pipe_name(pipe));
ea0760cf
JB		 1081}
1082
93ce0ba6
JN		 1083static void assert_cursor(struct drm_i915_private *dev_priv,
1084 enum pipe pipe, bool state)
1085{
1086 struct drm_device *dev = dev_priv->dev;
1087 bool cur_state;
1088
1089 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1090 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1091 else if (IS_845G(dev) || IS_I865G(dev))
1092 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1093 else
1094 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1095
1096 WARN(cur_state != state,
1097 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1098 pipe_name(pipe), state_string(state), state_string(cur_state));
1099}
1100#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1101#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1102
b840d907
JB		 1103void assert_pipe(struct drm_i915_private *dev_priv,
1104 enum pipe pipe, bool state)
b24e7179
JB		 1105{
1106 int reg;
1107 u32 val;
63d7bbe9 1108 bool cur_state;
702e7a56
PZ		 1109 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1110 pipe);
b24e7179 1111
8e636784
DV		 1112 /* if we need the pipe A quirk it must be always on */
1113 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1114 state = true;
1115
b97186f0
PZ		 1116 if (!intel_display_power_enabled(dev_priv->dev,
1117 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1118 cur_state = false;
1119 } else {
1120 reg = PIPECONF(cpu_transcoder);
1121 val = I915_READ(reg);
1122 cur_state = !!(val & PIPECONF_ENABLE);
1123 }
1124
63d7bbe9
JB		 1125 WARN(cur_state != state,
1126 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1127 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1128}
1129
931872fc
CW		 1130static void assert_plane(struct drm_i915_private *dev_priv,
1131 enum plane plane, bool state)
b24e7179
JB		 1132{
1133 int reg;
1134 u32 val;
931872fc 1135 bool cur_state;
b24e7179
JB		 1136
1137 reg = DSPCNTR(plane);
1138 val = I915_READ(reg);
931872fc
CW		 1139 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1140 WARN(cur_state != state,
1141 "plane %c assertion failure (expected %s, current %s)\n",
1142 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1143}
1144
931872fc
CW		 1145#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1146#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1147
b24e7179
JB		 1148static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1149 enum pipe pipe)
1150{
653e1026 1151 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1152 int reg, i;
1153 u32 val;
1154 int cur_pipe;
1155
653e1026
VS		 1156 /* Primary planes are fixed to pipes on gen4+ */
1157 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1158 reg = DSPCNTR(pipe);
1159 val = I915_READ(reg);
1160 WARN((val & DISPLAY_PLANE_ENABLE),
1161 "plane %c assertion failure, should be disabled but not\n",
1162 plane_name(pipe));
19ec1358 1163 return;
28c05794 1164 }
19ec1358 1165
b24e7179 1166 /* Need to check both planes against the pipe */
08e2a7de 1167 for_each_pipe(i) {
b24e7179
JB		 1168 reg = DSPCNTR(i);
1169 val = I915_READ(reg);
1170 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1171 DISPPLANE_SEL_PIPE_SHIFT;
1172 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1173 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1174 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1175 }
1176}
1177
19332d7a
JB		 1178static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1179 enum pipe pipe)
1180{
20674eef 1181 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1182 int reg, i;
1183 u32 val;
1184
20674eef
VS		 1185 if (IS_VALLEYVIEW(dev)) {
1186 for (i = 0; i < dev_priv->num_plane; i++) {
1187 reg = SPCNTR(pipe, i);
1188 val = I915_READ(reg);
1189 WARN((val & SP_ENABLE),
1190 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1191 sprite_name(pipe, i), pipe_name(pipe));
1192 }
1193 } else if (INTEL_INFO(dev)->gen >= 7) {
1194 reg = SPRCTL(pipe);
19332d7a 1195 val = I915_READ(reg);
20674eef 1196 WARN((val & SPRITE_ENABLE),
06da8da2 1197 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1198 plane_name(pipe), pipe_name(pipe));
1199 } else if (INTEL_INFO(dev)->gen >= 5) {
1200 reg = DVSCNTR(pipe);
19332d7a 1201 val = I915_READ(reg);
20674eef 1202 WARN((val & DVS_ENABLE),
06da8da2 1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1204 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1205 }
1206}
1207
92f2584a
JB		 1208static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1209{
1210 u32 val;
1211 bool enabled;
1212
9d82aa17
ED		 1213 if (HAS_PCH_LPT(dev_priv->dev)) {
1214 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1215 return;
1216 }
1217
92f2584a
JB		 1218 val = I915_READ(PCH_DREF_CONTROL);
1219 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1220 DREF_SUPERSPREAD_SOURCE_MASK));
1221 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1222}
1223
ab9412ba
DV		 1224static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1225 enum pipe pipe)
92f2584a
JB		 1226{
1227 int reg;
1228 u32 val;
1229 bool enabled;
1230
ab9412ba 1231 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1232 val = I915_READ(reg);
1233 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1234 WARN(enabled,
1235 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1236 pipe_name(pipe));
92f2584a
JB		 1237}
1238
4e634389
KP		 1239static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1240 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1241{
1242 if ((val & DP_PORT_EN) == 0)
1243 return false;
1244
1245 if (HAS_PCH_CPT(dev_priv->dev)) {
1246 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1247 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1248 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1249 return false;
1250 } else {
1251 if ((val & DP_PIPE_MASK) != (pipe << 30))
1252 return false;
1253 }
1254 return true;
1255}
1256
1519b995
KP		 1257static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1258 enum pipe pipe, u32 val)
1259{
dc0fa718 1260 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1261 return false;
1262
1263 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1264 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1265 return false;
1266 } else {
dc0fa718 1267 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1268 return false;
1269 }
1270 return true;
1271}
1272
1273static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1274 enum pipe pipe, u32 val)
1275{
1276 if ((val & LVDS_PORT_EN) == 0)
1277 return false;
1278
1279 if (HAS_PCH_CPT(dev_priv->dev)) {
1280 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1281 return false;
1282 } else {
1283 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1284 return false;
1285 }
1286 return true;
1287}
1288
1289static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1290 enum pipe pipe, u32 val)
1291{
1292 if ((val & ADPA_DAC_ENABLE) == 0)
1293 return false;
1294 if (HAS_PCH_CPT(dev_priv->dev)) {
1295 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1296 return false;
1297 } else {
1298 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1299 return false;
1300 }
1301 return true;
1302}
1303
291906f1 1304static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1305 enum pipe pipe, int reg, u32 port_sel)
291906f1 1306{
47a05eca 1307 u32 val = I915_READ(reg);
4e634389 1308 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1309 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1310 reg, pipe_name(pipe));
de9a35ab 1311
75c5da27
DV		 1312 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1313 && (val & DP_PIPEB_SELECT),
de9a35ab 1314 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1315}
1316
1317static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1318 enum pipe pipe, int reg)
1319{
47a05eca 1320 u32 val = I915_READ(reg);
b70ad586 1321 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1322 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1323 reg, pipe_name(pipe));
de9a35ab 1324
dc0fa718 1325 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1326 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1327 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1328}
1329
1330static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1331 enum pipe pipe)
1332{
1333 int reg;
1334 u32 val;
291906f1 1335
f0575e92
KP		 1336 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1337 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1338 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1339
1340 reg = PCH_ADPA;
1341 val = I915_READ(reg);
b70ad586 1342 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1343 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1344 pipe_name(pipe));
291906f1
JB		 1345
1346 reg = PCH_LVDS;
1347 val = I915_READ(reg);
b70ad586 1348 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1349 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1350 pipe_name(pipe));
291906f1 1351
e2debe91
PZ		 1352 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1353 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1354 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1355}
1356
40e9cf64
JB		 1357static void intel_init_dpio(struct drm_device *dev)
1358{
1359 struct drm_i915_private *dev_priv = dev->dev_private;
1360
1361 if (!IS_VALLEYVIEW(dev))
1362 return;
1363
1364 /*
1365 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1366 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1367 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1368 * b. The other bits such as sfr settings / modesel may all be set
1369 * to 0.
1370 *
1371 * This should only be done on init and resume from S3 with both
1372 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1373 */
1374 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1375}
1376
426115cf 1377static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1378{
426115cf
DV		 1379 struct drm_device *dev = crtc->base.dev;
1380 struct drm_i915_private *dev_priv = dev->dev_private;
1381 int reg = DPLL(crtc->pipe);
1382 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1383
426115cf 1384 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1385
1386 /* No really, not for ILK+ */
1387 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1388
1389 /* PLL is protected by panel, make sure we can write it */
1390 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1391 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1392
426115cf
DV		 1393 I915_WRITE(reg, dpll);
1394 POSTING_READ(reg);
1395 udelay(150);
1396
1397 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1398 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1399
1400 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1401 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1402
1403 /* We do this three times for luck */
426115cf 1404 I915_WRITE(reg, dpll);
87442f73
DV		 1405 POSTING_READ(reg);
1406 udelay(150); /* wait for warmup */
426115cf 1407 I915_WRITE(reg, dpll);
87442f73
DV		 1408 POSTING_READ(reg);
1409 udelay(150); /* wait for warmup */
426115cf 1410 I915_WRITE(reg, dpll);
87442f73
DV		 1411 POSTING_READ(reg);
1412 udelay(150); /* wait for warmup */
1413}
1414
66e3d5c0 1415static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1416{
66e3d5c0
DV		 1417 struct drm_device *dev = crtc->base.dev;
1418 struct drm_i915_private *dev_priv = dev->dev_private;
1419 int reg = DPLL(crtc->pipe);
1420 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1421
66e3d5c0 1422 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1423
63d7bbe9 1424 /* No really, not for ILK+ */
87442f73 1425 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1426
1427 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1428 if (IS_MOBILE(dev) && !IS_I830(dev))
1429 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1430
66e3d5c0
DV		 1431 I915_WRITE(reg, dpll);
1432
1433 /* Wait for the clocks to stabilize. */
1434 POSTING_READ(reg);
1435 udelay(150);
1436
1437 if (INTEL_INFO(dev)->gen >= 4) {
1438 I915_WRITE(DPLL_MD(crtc->pipe),
1439 crtc->config.dpll_hw_state.dpll_md);
1440 } else {
1441 /* The pixel multiplier can only be updated once the
1442 * DPLL is enabled and the clocks are stable.
1443 *
1444 * So write it again.
1445 */
1446 I915_WRITE(reg, dpll);
1447 }
63d7bbe9
JB		 1448
1449 /* We do this three times for luck */
66e3d5c0 1450 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1451 POSTING_READ(reg);
1452 udelay(150); /* wait for warmup */
66e3d5c0 1453 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1454 POSTING_READ(reg);
1455 udelay(150); /* wait for warmup */
66e3d5c0 1456 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1457 POSTING_READ(reg);
1458 udelay(150); /* wait for warmup */
1459}
1460
1461/**
50b44a44 1462 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1463 * @dev_priv: i915 private structure
1464 * @pipe: pipe PLL to disable
1465 *
1466 * Disable the PLL for @pipe, making sure the pipe is off first.
1467 *
1468 * Note! This is for pre-ILK only.
1469 */
50b44a44 1470static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1471{
63d7bbe9
JB		 1472 /* Don't disable pipe A or pipe A PLLs if needed */
1473 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1474 return;
1475
1476 /* Make sure the pipe isn't still relying on us */
1477 assert_pipe_disabled(dev_priv, pipe);
1478
50b44a44
DV		 1479 I915_WRITE(DPLL(pipe), 0);
1480 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1481}
1482
f6071166
JB		 1483static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1484{
1485 u32 val = 0;
1486
1487 /* Make sure the pipe isn't still relying on us */
1488 assert_pipe_disabled(dev_priv, pipe);
1489
1490 /* Leave integrated clock source enabled */
1491 if (pipe == PIPE_B)
1492 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1493 I915_WRITE(DPLL(pipe), val);
1494 POSTING_READ(DPLL(pipe));
1495}
1496
89b667f8
JB		 1497void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1498{
1499 u32 port_mask;
1500
1501 if (!port)
1502 port_mask = DPLL_PORTB_READY_MASK;
1503 else
1504 port_mask = DPLL_PORTC_READY_MASK;
1505
1506 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1507 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1508 'B' + port, I915_READ(DPLL(0)));
1509}
1510
92f2584a 1511/**
e72f9fbf 1512 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1513 * @dev_priv: i915 private structure
1514 * @pipe: pipe PLL to enable
1515 *
1516 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1517 * drives the transcoder clock.
1518 */
e2b78267 1519static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1520{
e2b78267
DV		 1521 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1522 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1523
48da64a8 1524 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1525 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1526 if (WARN_ON(pll == NULL))
48da64a8
CW		 1527 return;
1528
1529 if (WARN_ON(pll->refcount == 0))
1530 return;
ee7b9f93 1531
46edb027
DV		 1532 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1533 pll->name, pll->active, pll->on,
e2b78267 1534 crtc->base.base.id);
92f2584a 1535
cdbd2316
DV		 1536 if (pll->active++) {
1537 WARN_ON(!pll->on);
e9d6944e 1538 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1539 return;
1540 }
f4a091c7 1541 WARN_ON(pll->on);
ee7b9f93 1542
46edb027 1543 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1544 pll->enable(dev_priv, pll);
ee7b9f93 1545 pll->on = true;
92f2584a
JB		 1546}
1547
e2b78267 1548static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1549{
e2b78267
DV		 1550 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1551 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1552
92f2584a
JB		 1553 /* PCH only available on ILK+ */
1554 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1555 if (WARN_ON(pll == NULL))
ee7b9f93 1556 return;
92f2584a 1557
48da64a8
CW		 1558 if (WARN_ON(pll->refcount == 0))
1559 return;
7a419866 1560
46edb027
DV		 1561 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1562 pll->name, pll->active, pll->on,
e2b78267 1563 crtc->base.base.id);
7a419866 1564
48da64a8 1565 if (WARN_ON(pll->active == 0)) {
e9d6944e 1566 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1567 return;
1568 }
1569
e9d6944e 1570 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1571 WARN_ON(!pll->on);
cdbd2316 1572 if (--pll->active)
7a419866 1573 return;
ee7b9f93 1574
46edb027 1575 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1576 pll->disable(dev_priv, pll);
ee7b9f93 1577 pll->on = false;
92f2584a
JB		 1578}
1579
b8a4f404
PZ		 1580static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1581 enum pipe pipe)
040484af 1582{
23670b32 1583 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1584 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1586 uint32_t reg, val, pipeconf_val;
040484af
JB		 1587
1588 /* PCH only available on ILK+ */
1589 BUG_ON(dev_priv->info->gen < 5);
1590
1591 /* Make sure PCH DPLL is enabled */
e72f9fbf 1592 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1593 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1594
1595 /* FDI must be feeding us bits for PCH ports */
1596 assert_fdi_tx_enabled(dev_priv, pipe);
1597 assert_fdi_rx_enabled(dev_priv, pipe);
1598
23670b32
DV		 1599 if (HAS_PCH_CPT(dev)) {
1600 /* Workaround: Set the timing override bit before enabling the
1601 * pch transcoder. */
1602 reg = TRANS_CHICKEN2(pipe);
1603 val = I915_READ(reg);
1604 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1605 I915_WRITE(reg, val);
59c859d6 1606 }
23670b32 1607
ab9412ba 1608 reg = PCH_TRANSCONF(pipe);
040484af 1609 val = I915_READ(reg);
5f7f726d 1610 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1611
1612 if (HAS_PCH_IBX(dev_priv->dev)) {
1613 /*
1614 * make the BPC in transcoder be consistent with
1615 * that in pipeconf reg.
1616 */
dfd07d72
DV		 1617 val &= ~PIPECONF_BPC_MASK;
1618 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1619 }
5f7f726d
PZ		 1620
1621 val &= ~TRANS_INTERLACE_MASK;
1622 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1623 if (HAS_PCH_IBX(dev_priv->dev) &&
1624 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1625 val |= TRANS_LEGACY_INTERLACED_ILK;
1626 else
1627 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1628 else
1629 val |= TRANS_PROGRESSIVE;
1630
040484af
JB		 1631 I915_WRITE(reg, val | TRANS_ENABLE);
1632 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1633 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1634}
1635
8fb033d7 1636static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1637 enum transcoder cpu_transcoder)
040484af 1638{
8fb033d7 1639 u32 val, pipeconf_val;
8fb033d7
PZ		 1640
1641 /* PCH only available on ILK+ */
1642 BUG_ON(dev_priv->info->gen < 5);
1643
8fb033d7 1644 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1645 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1646 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1647
223a6fdf
PZ		 1648 /* Workaround: set timing override bit. */
1649 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1650 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1651 I915_WRITE(_TRANSA_CHICKEN2, val);
1652
25f3ef11 1653 val = TRANS_ENABLE;
937bb610 1654 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1655
9a76b1c6
PZ		 1656 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1657 PIPECONF_INTERLACED_ILK)
a35f2679 1658 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1659 else
1660 val |= TRANS_PROGRESSIVE;
1661
ab9412ba
DV		 1662 I915_WRITE(LPT_TRANSCONF, val);
1663 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1664 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1665}
1666
b8a4f404
PZ		 1667static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1668 enum pipe pipe)
040484af 1669{
23670b32
DV		 1670 struct drm_device *dev = dev_priv->dev;
1671 uint32_t reg, val;
040484af
JB		 1672
1673 /* FDI relies on the transcoder */
1674 assert_fdi_tx_disabled(dev_priv, pipe);
1675 assert_fdi_rx_disabled(dev_priv, pipe);
1676
291906f1
JB		 1677 /* Ports must be off as well */
1678 assert_pch_ports_disabled(dev_priv, pipe);
1679
ab9412ba 1680 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1681 val = I915_READ(reg);
1682 val &= ~TRANS_ENABLE;
1683 I915_WRITE(reg, val);
1684 /* wait for PCH transcoder off, transcoder state */
1685 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1686 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1687
1688 if (!HAS_PCH_IBX(dev)) {
1689 /* Workaround: Clear the timing override chicken bit again. */
1690 reg = TRANS_CHICKEN2(pipe);
1691 val = I915_READ(reg);
1692 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1693 I915_WRITE(reg, val);
1694 }
040484af
JB		 1695}
1696
ab4d966c 1697static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1698{
8fb033d7
PZ		 1699 u32 val;
1700
ab9412ba 1701 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1702 val &= ~TRANS_ENABLE;
ab9412ba 1703 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1704 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1705 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1706 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1707
1708 /* Workaround: clear timing override bit. */
1709 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1710 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1711 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1712}
1713
b24e7179 1714/**
309cfea8 1715 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1716 * @dev_priv: i915 private structure
1717 * @pipe: pipe to enable
040484af 1718 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1719 *
1720 * Enable @pipe, making sure that various hardware specific requirements
1721 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1722 *
1723 * @pipe should be %PIPE_A or %PIPE_B.
1724 *
1725 * Will wait until the pipe is actually running (i.e. first vblank) before
1726 * returning.
1727 */
040484af 1728static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1729 bool pch_port, bool dsi)
b24e7179 1730{
702e7a56
PZ		 1731 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1732 pipe);
1a240d4d 1733 enum pipe pch_transcoder;
b24e7179
JB		 1734 int reg;
1735 u32 val;
1736
58c6eaa2 1737 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1738 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 1739 assert_sprites_disabled(dev_priv, pipe);
1740
681e5811 1741 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1742 pch_transcoder = TRANSCODER_A;
1743 else
1744 pch_transcoder = pipe;
1745
b24e7179
JB		 1746 /*
1747 * A pipe without a PLL won't actually be able to drive bits from
1748 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1749 * need the check.
1750 */
1751 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1752 if (dsi)
1753 assert_dsi_pll_enabled(dev_priv);
1754 else
1755 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1756 else {
1757 if (pch_port) {
1758 /* if driving the PCH, we need FDI enabled */
cc391bbb 1759 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1760 assert_fdi_tx_pll_enabled(dev_priv,
1761 (enum pipe) cpu_transcoder);
040484af
JB		 1762 }
1763 /* FIXME: assert CPU port conditions for SNB+ */
1764 }
b24e7179 1765
702e7a56 1766 reg = PIPECONF(cpu_transcoder);
b24e7179 1767 val = I915_READ(reg);
00d70b15
CW		 1768 if (val & PIPECONF_ENABLE)
1769 return;
1770
1771 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1772 intel_wait_for_vblank(dev_priv->dev, pipe);
1773}
1774
1775/**
309cfea8 1776 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1777 * @dev_priv: i915 private structure
1778 * @pipe: pipe to disable
1779 *
1780 * Disable @pipe, making sure that various hardware specific requirements
1781 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1782 *
1783 * @pipe should be %PIPE_A or %PIPE_B.
1784 *
1785 * Will wait until the pipe has shut down before returning.
1786 */
1787static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1788 enum pipe pipe)
1789{
702e7a56
PZ		 1790 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1791 pipe);
b24e7179
JB		 1792 int reg;
1793 u32 val;
1794
1795 /*
1796 * Make sure planes won't keep trying to pump pixels to us,
1797 * or we might hang the display.
1798 */
1799 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1800 assert_cursor_disabled(dev_priv, pipe);
19332d7a 1801 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1802
1803 /* Don't disable pipe A or pipe A PLLs if needed */
1804 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1805 return;
1806
702e7a56 1807 reg = PIPECONF(cpu_transcoder);
b24e7179 1808 val = I915_READ(reg);
00d70b15
CW		 1809 if ((val & PIPECONF_ENABLE) == 0)
1810 return;
1811
1812 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1813 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1814}
1815
d74362c9
KP		 1816/*
1817 * Plane regs are double buffered, going from enabled->disabled needs a
1818 * trigger in order to latch. The display address reg provides this.
1819 */
1dba99f4
VS		 1820void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
1821 enum plane plane)
d74362c9 1822{
1dba99f4
VS		 1823 u32 reg = dev_priv->info->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1824
1825 I915_WRITE(reg, I915_READ(reg));
1826 POSTING_READ(reg);
d74362c9
KP		 1827}
1828
b24e7179 1829/**
d1de00ef 1830 * intel_enable_primary_plane - enable the primary plane on a given pipe
b24e7179
JB		 1831 * @dev_priv: i915 private structure
1832 * @plane: plane to enable
1833 * @pipe: pipe being fed
1834 *
1835 * Enable @plane on @pipe, making sure that @pipe is running first.
1836 */
d1de00ef
VS		 1837static void intel_enable_primary_plane(struct drm_i915_private *dev_priv,
1838 enum plane plane, enum pipe pipe)
b24e7179 1839{
939c2fe8
VS		 1840 struct intel_crtc *intel_crtc =
1841 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
b24e7179
JB		 1842 int reg;
1843 u32 val;
1844
1845 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1846 assert_pipe_enabled(dev_priv, pipe);
1847
4c445e0e 1848 WARN(intel_crtc->primary_enabled, "Primary plane already enabled\n");
0037f71c 1849
4c445e0e 1850 intel_crtc->primary_enabled = true;
939c2fe8 1851
b24e7179
JB		 1852 reg = DSPCNTR(plane);
1853 val = I915_READ(reg);
00d70b15
CW		 1854 if (val & DISPLAY_PLANE_ENABLE)
1855 return;
1856
1857 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1dba99f4 1858 intel_flush_primary_plane(dev_priv, plane);
b24e7179
JB		 1859 intel_wait_for_vblank(dev_priv->dev, pipe);
1860}
1861
b24e7179 1862/**
d1de00ef 1863 * intel_disable_primary_plane - disable the primary plane
b24e7179
JB		 1864 * @dev_priv: i915 private structure
1865 * @plane: plane to disable
1866 * @pipe: pipe consuming the data
1867 *
1868 * Disable @plane; should be an independent operation.
1869 */
d1de00ef
VS		 1870static void intel_disable_primary_plane(struct drm_i915_private *dev_priv,
1871 enum plane plane, enum pipe pipe)
b24e7179 1872{
939c2fe8
VS		 1873 struct intel_crtc *intel_crtc =
1874 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
b24e7179
JB		 1875 int reg;
1876 u32 val;
1877
4c445e0e 1878 WARN(!intel_crtc->primary_enabled, "Primary plane already disabled\n");
0037f71c 1879
4c445e0e 1880 intel_crtc->primary_enabled = false;
939c2fe8 1881
b24e7179
JB		 1882 reg = DSPCNTR(plane);
1883 val = I915_READ(reg);
00d70b15
CW		 1884 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1885 return;
1886
1887 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1dba99f4 1888 intel_flush_primary_plane(dev_priv, plane);
b24e7179
JB		 1889 intel_wait_for_vblank(dev_priv->dev, pipe);
1890}
1891
693db184
CW		 1892static bool need_vtd_wa(struct drm_device *dev)
1893{
1894#ifdef CONFIG_INTEL_IOMMU
1895 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1896 return true;
1897#endif
1898 return false;
1899}
1900
127bd2ac 1901int
48b956c5 1902intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1903 struct drm_i915_gem_object *obj,
919926ae 1904 struct intel_ring_buffer *pipelined)
6b95a207 1905{
ce453d81 1906 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1907 u32 alignment;
1908 int ret;
1909
05394f39 1910 switch (obj->tiling_mode) {
6b95a207 1911 case I915_TILING_NONE:
534843da
CW		 1912 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1913 alignment = 128 * 1024;
a6c45cf0 1914 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1915 alignment = 4 * 1024;
1916 else
1917 alignment = 64 * 1024;
6b95a207
KH		 1918 break;
1919 case I915_TILING_X:
1920 /* pin() will align the object as required by fence */
1921 alignment = 0;
1922 break;
1923 case I915_TILING_Y:
80075d49 1924 WARN(1, "Y tiled bo slipped through, driver bug!\n");
6b95a207
KH		 1925 return -EINVAL;
1926 default:
1927 BUG();
1928 }
1929
693db184
CW		 1930 /* Note that the w/a also requires 64 PTE of padding following the
1931 * bo. We currently fill all unused PTE with the shadow page and so
1932 * we should always have valid PTE following the scanout preventing
1933 * the VT-d warning.
1934 */
1935 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1936 alignment = 256 * 1024;
1937
ce453d81 1938 dev_priv->mm.interruptible = false;
2da3b9b9 1939 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1940 if (ret)
ce453d81 1941 goto err_interruptible;
6b95a207
KH		 1942
1943 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1944 * fence, whereas 965+ only requires a fence if using
1945 * framebuffer compression. For simplicity, we always install
1946 * a fence as the cost is not that onerous.
1947 */
06d98131 1948 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1949 if (ret)
1950 goto err_unpin;
1690e1eb 1951
9a5a53b3 1952 i915_gem_object_pin_fence(obj);
6b95a207 1953
ce453d81 1954 dev_priv->mm.interruptible = true;
6b95a207 1955 return 0;
48b956c5
CW		 1956
1957err_unpin:
cc98b413 1958 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1959err_interruptible:
1960 dev_priv->mm.interruptible = true;
48b956c5 1961 return ret;
6b95a207
KH		 1962}
1963
1690e1eb
CW		 1964void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1965{
1966 i915_gem_object_unpin_fence(obj);
cc98b413 1967 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1968}
1969
c2c75131
DV		 1970/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1971 * is assumed to be a power-of-two. */
bc752862
CW		 1972unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1973 unsigned int tiling_mode,
1974 unsigned int cpp,
1975 unsigned int pitch)
c2c75131 1976{
bc752862
CW		 1977 if (tiling_mode != I915_TILING_NONE) {
1978 unsigned int tile_rows, tiles;
c2c75131 1979
bc752862
CW		 1980 tile_rows = *y / 8;
1981 *y %= 8;
c2c75131 1982
bc752862
CW		 1983 tiles = *x / (512/cpp);
1984 *x %= 512/cpp;
1985
1986 return tile_rows * pitch * 8 + tiles * 4096;
1987 } else {
1988 unsigned int offset;
1989
1990 offset = *y * pitch + *x * cpp;
1991 *y = 0;
1992 *x = (offset & 4095) / cpp;
1993 return offset & -4096;
1994 }
c2c75131
DV		 1995}
1996
17638cd6
JB		 1997static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1998 int x, int y)
81255565
JB		 1999{
2000 struct drm_device *dev = crtc->dev;
2001 struct drm_i915_private *dev_priv = dev->dev_private;
2002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2003 struct intel_framebuffer *intel_fb;
05394f39 2004 struct drm_i915_gem_object *obj;
81255565 2005 int plane = intel_crtc->plane;
e506a0c6 2006 unsigned long linear_offset;
81255565 2007 u32 dspcntr;
5eddb70b 2008 u32 reg;
81255565
JB		 2009
2010 switch (plane) {
2011 case 0:
2012 case 1:
2013 break;
2014 default:
84f44ce7 2015 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 2016 return -EINVAL;
2017 }
2018
2019 intel_fb = to_intel_framebuffer(fb);
2020 obj = intel_fb->obj;
81255565 2021
5eddb70b
CW		 2022 reg = DSPCNTR(plane);
2023 dspcntr = I915_READ(reg);
81255565
JB		 2024 /* Mask out pixel format bits in case we change it */
2025 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2026 switch (fb->pixel_format) {
2027 case DRM_FORMAT_C8:
81255565
JB		 2028 dspcntr |= DISPPLANE_8BPP;
2029 break;
57779d06
VS		 2030 case DRM_FORMAT_XRGB1555:
2031 case DRM_FORMAT_ARGB1555:
2032 dspcntr |= DISPPLANE_BGRX555;
81255565 2033 break;
57779d06
VS		 2034 case DRM_FORMAT_RGB565:
2035 dspcntr |= DISPPLANE_BGRX565;
2036 break;
2037 case DRM_FORMAT_XRGB8888:
2038 case DRM_FORMAT_ARGB8888:
2039 dspcntr |= DISPPLANE_BGRX888;
2040 break;
2041 case DRM_FORMAT_XBGR8888:
2042 case DRM_FORMAT_ABGR8888:
2043 dspcntr |= DISPPLANE_RGBX888;
2044 break;
2045 case DRM_FORMAT_XRGB2101010:
2046 case DRM_FORMAT_ARGB2101010:
2047 dspcntr |= DISPPLANE_BGRX101010;
2048 break;
2049 case DRM_FORMAT_XBGR2101010:
2050 case DRM_FORMAT_ABGR2101010:
2051 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2052 break;
2053 default:
baba133a 2054 BUG();
81255565 2055 }
57779d06 2056
a6c45cf0 2057 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2058 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2059 dspcntr |= DISPPLANE_TILED;
2060 else
2061 dspcntr &= ~DISPPLANE_TILED;
2062 }
2063
de1aa629
VS		 2064 if (IS_G4X(dev))
2065 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2066
5eddb70b 2067 I915_WRITE(reg, dspcntr);
81255565 2068
e506a0c6 2069 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2070
c2c75131
DV		 2071 if (INTEL_INFO(dev)->gen >= 4) {
2072 intel_crtc->dspaddr_offset =
bc752862
CW		 2073 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2074 fb->bits_per_pixel / 8,
2075 fb->pitches[0]);
c2c75131
DV		 2076 linear_offset -= intel_crtc->dspaddr_offset;
2077 } else {
e506a0c6 2078 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2079 }
e506a0c6 2080
f343c5f6
BW		 2081 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2082 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2083 fb->pitches[0]);
01f2c773 2084 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2085 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2086 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2087 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2088 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2089 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2090 } else
f343c5f6 2091 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2092 POSTING_READ(reg);
81255565 2093
17638cd6
JB		 2094 return 0;
2095}
2096
2097static int ironlake_update_plane(struct drm_crtc *crtc,
2098 struct drm_framebuffer *fb, int x, int y)
2099{
2100 struct drm_device *dev = crtc->dev;
2101 struct drm_i915_private *dev_priv = dev->dev_private;
2102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2103 struct intel_framebuffer *intel_fb;
2104 struct drm_i915_gem_object *obj;
2105 int plane = intel_crtc->plane;
e506a0c6 2106 unsigned long linear_offset;
17638cd6
JB		 2107 u32 dspcntr;
2108 u32 reg;
2109
2110 switch (plane) {
2111 case 0:
2112 case 1:
27f8227b 2113 case 2:
17638cd6
JB		 2114 break;
2115 default:
84f44ce7 2116 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2117 return -EINVAL;
2118 }
2119
2120 intel_fb = to_intel_framebuffer(fb);
2121 obj = intel_fb->obj;
2122
2123 reg = DSPCNTR(plane);
2124 dspcntr = I915_READ(reg);
2125 /* Mask out pixel format bits in case we change it */
2126 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2127 switch (fb->pixel_format) {
2128 case DRM_FORMAT_C8:
17638cd6
JB		 2129 dspcntr |= DISPPLANE_8BPP;
2130 break;
57779d06
VS		 2131 case DRM_FORMAT_RGB565:
2132 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2133 break;
57779d06
VS		 2134 case DRM_FORMAT_XRGB8888:
2135 case DRM_FORMAT_ARGB8888:
2136 dspcntr |= DISPPLANE_BGRX888;
2137 break;
2138 case DRM_FORMAT_XBGR8888:
2139 case DRM_FORMAT_ABGR8888:
2140 dspcntr |= DISPPLANE_RGBX888;
2141 break;
2142 case DRM_FORMAT_XRGB2101010:
2143 case DRM_FORMAT_ARGB2101010:
2144 dspcntr |= DISPPLANE_BGRX101010;
2145 break;
2146 case DRM_FORMAT_XBGR2101010:
2147 case DRM_FORMAT_ABGR2101010:
2148 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2149 break;
2150 default:
baba133a 2151 BUG();
17638cd6
JB		 2152 }
2153
2154 if (obj->tiling_mode != I915_TILING_NONE)
2155 dspcntr |= DISPPLANE_TILED;
2156 else
2157 dspcntr &= ~DISPPLANE_TILED;
2158
1f5d76db
PZ		 2159 if (IS_HASWELL(dev))
2160 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2161 else
2162 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2163
2164 I915_WRITE(reg, dspcntr);
2165
e506a0c6 2166 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2167 intel_crtc->dspaddr_offset =
bc752862
CW		 2168 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2169 fb->bits_per_pixel / 8,
2170 fb->pitches[0]);
c2c75131 2171 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2172
f343c5f6
BW		 2173 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2174 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2175 fb->pitches[0]);
01f2c773 2176 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2177 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2178 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2179 if (IS_HASWELL(dev)) {
2180 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2181 } else {
2182 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2183 I915_WRITE(DSPLINOFF(plane), linear_offset);
2184 }
17638cd6
JB		 2185 POSTING_READ(reg);
2186
2187 return 0;
2188}
2189
2190/* Assume fb object is pinned & idle & fenced and just update base pointers */
2191static int
2192intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2193 int x, int y, enum mode_set_atomic state)
2194{
2195 struct drm_device *dev = crtc->dev;
2196 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2197
6b8e6ed0
CW		 2198 if (dev_priv->display.disable_fbc)
2199 dev_priv->display.disable_fbc(dev);
3dec0095 2200 intel_increase_pllclock(crtc);
81255565 2201
6b8e6ed0 2202 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2203}
2204
96a02917
VS		 2205void intel_display_handle_reset(struct drm_device *dev)
2206{
2207 struct drm_i915_private *dev_priv = dev->dev_private;
2208 struct drm_crtc *crtc;
2209
2210 /*
2211 * Flips in the rings have been nuked by the reset,
2212 * so complete all pending flips so that user space
2213 * will get its events and not get stuck.
2214 *
2215 * Also update the base address of all primary
2216 * planes to the the last fb to make sure we're
2217 * showing the correct fb after a reset.
2218 *
2219 * Need to make two loops over the crtcs so that we
2220 * don't try to grab a crtc mutex before the
2221 * pending_flip_queue really got woken up.
2222 */
2223
2224 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2226 enum plane plane = intel_crtc->plane;
2227
2228 intel_prepare_page_flip(dev, plane);
2229 intel_finish_page_flip_plane(dev, plane);
2230 }
2231
2232 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2234
2235 mutex_lock(&crtc->mutex);
2236 if (intel_crtc->active)
2237 dev_priv->display.update_plane(crtc, crtc->fb,
2238 crtc->x, crtc->y);
2239 mutex_unlock(&crtc->mutex);
2240 }
2241}
2242
14667a4b
CW		 2243static int
2244intel_finish_fb(struct drm_framebuffer *old_fb)
2245{
2246 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2247 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2248 bool was_interruptible = dev_priv->mm.interruptible;
2249 int ret;
2250
14667a4b
CW		 2251 /* Big Hammer, we also need to ensure that any pending
2252 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2253 * current scanout is retired before unpinning the old
2254 * framebuffer.
2255 *
2256 * This should only fail upon a hung GPU, in which case we
2257 * can safely continue.
2258 */
2259 dev_priv->mm.interruptible = false;
2260 ret = i915_gem_object_finish_gpu(obj);
2261 dev_priv->mm.interruptible = was_interruptible;
2262
2263 return ret;
2264}
2265
198598d0
VS		 2266static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2267{
2268 struct drm_device *dev = crtc->dev;
2269 struct drm_i915_master_private *master_priv;
2270 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2271
2272 if (!dev->primary->master)
2273 return;
2274
2275 master_priv = dev->primary->master->driver_priv;
2276 if (!master_priv->sarea_priv)
2277 return;
2278
2279 switch (intel_crtc->pipe) {
2280 case 0:
2281 master_priv->sarea_priv->pipeA_x = x;
2282 master_priv->sarea_priv->pipeA_y = y;
2283 break;
2284 case 1:
2285 master_priv->sarea_priv->pipeB_x = x;
2286 master_priv->sarea_priv->pipeB_y = y;
2287 break;
2288 default:
2289 break;
2290 }
2291}
2292
5c3b82e2 2293static int
3c4fdcfb 2294intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2295 struct drm_framebuffer *fb)
79e53945
JB		 2296{
2297 struct drm_device *dev = crtc->dev;
6b8e6ed0 2298 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2299 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2300 struct drm_framebuffer *old_fb;
5c3b82e2 2301 int ret;
79e53945
JB		 2302
2303 /* no fb bound */
94352cf9 2304 if (!fb) {
a5071c2f 2305 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2306 return 0;
2307 }
2308
7eb552ae 2309 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2310 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2311 plane_name(intel_crtc->plane),
2312 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2313 return -EINVAL;
79e53945
JB		 2314 }
2315
5c3b82e2 2316 mutex_lock(&dev->struct_mutex);
265db958 2317 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2318 to_intel_framebuffer(fb)->obj,
919926ae 2319 NULL);
5c3b82e2
CW		 2320 if (ret != 0) {
2321 mutex_unlock(&dev->struct_mutex);
a5071c2f 2322 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2323 return ret;
2324 }
79e53945 2325
bb2043de
DL		 2326 /*
2327 * Update pipe size and adjust fitter if needed: the reason for this is
2328 * that in compute_mode_changes we check the native mode (not the pfit
2329 * mode) to see if we can flip rather than do a full mode set. In the
2330 * fastboot case, we'll flip, but if we don't update the pipesrc and
2331 * pfit state, we'll end up with a big fb scanned out into the wrong
2332 * sized surface.
2333 *
2334 * To fix this properly, we need to hoist the checks up into
2335 * compute_mode_changes (or above), check the actual pfit state and
2336 * whether the platform allows pfit disable with pipe active, and only
2337 * then update the pipesrc and pfit state, even on the flip path.
2338 */
4d6a3e63 2339 if (i915_fastboot) {
d7bf63f2
DL		 2340 const struct drm_display_mode *adjusted_mode =
2341 &intel_crtc->config.adjusted_mode;
2342
4d6a3e63 2343 I915_WRITE(PIPESRC(intel_crtc->pipe),
d7bf63f2
DL		 2344 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2345 (adjusted_mode->crtc_vdisplay - 1));
fd4daa9c 2346 if (!intel_crtc->config.pch_pfit.enabled &&
4d6a3e63
JB		 2347 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2348 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2349 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2350 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2351 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2352 }
2353 }
2354
94352cf9 2355 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2356 if (ret) {
94352cf9 2357 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2358 mutex_unlock(&dev->struct_mutex);
a5071c2f 2359 DRM_ERROR("failed to update base address\n");
4e6cfefc 2360 return ret;
79e53945 2361 }
3c4fdcfb 2362
94352cf9
DV		 2363 old_fb = crtc->fb;
2364 crtc->fb = fb;
6c4c86f5
DV		 2365 crtc->x = x;
2366 crtc->y = y;
94352cf9 2367
b7f1de28 2368 if (old_fb) {
d7697eea
DV		 2369 if (intel_crtc->active && old_fb != fb)
2370 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2371 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2372 }
652c393a 2373
6b8e6ed0 2374 intel_update_fbc(dev);
4906557e 2375 intel_edp_psr_update(dev);
5c3b82e2 2376 mutex_unlock(&dev->struct_mutex);
79e53945 2377
198598d0 2378 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2379
2380 return 0;
79e53945
JB		 2381}
2382
5e84e1a4
ZW		 2383static void intel_fdi_normal_train(struct drm_crtc *crtc)
2384{
2385 struct drm_device *dev = crtc->dev;
2386 struct drm_i915_private *dev_priv = dev->dev_private;
2387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2388 int pipe = intel_crtc->pipe;
2389 u32 reg, temp;
2390
2391 /* enable normal train */
2392 reg = FDI_TX_CTL(pipe);
2393 temp = I915_READ(reg);
61e499bf 2394 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2395 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2396 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2397 } else {
2398 temp &= ~FDI_LINK_TRAIN_NONE;
2399 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2400 }
5e84e1a4
ZW		 2401 I915_WRITE(reg, temp);
2402
2403 reg = FDI_RX_CTL(pipe);
2404 temp = I915_READ(reg);
2405 if (HAS_PCH_CPT(dev)) {
2406 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2407 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2408 } else {
2409 temp &= ~FDI_LINK_TRAIN_NONE;
2410 temp |= FDI_LINK_TRAIN_NONE;
2411 }
2412 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2413
2414 /* wait one idle pattern time */
2415 POSTING_READ(reg);
2416 udelay(1000);
357555c0
JB		 2417
2418 /* IVB wants error correction enabled */
2419 if (IS_IVYBRIDGE(dev))
2420 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2421 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2422}
2423
1e833f40
DV		 2424static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2425{
2426 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2427}
2428
01a415fd
DV		 2429static void ivb_modeset_global_resources(struct drm_device *dev)
2430{
2431 struct drm_i915_private *dev_priv = dev->dev_private;
2432 struct intel_crtc *pipe_B_crtc =
2433 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2434 struct intel_crtc *pipe_C_crtc =
2435 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2436 uint32_t temp;
2437
1e833f40
DV		 2438 /*
2439 * When everything is off disable fdi C so that we could enable fdi B
2440 * with all lanes. Note that we don't care about enabled pipes without
2441 * an enabled pch encoder.
2442 */
2443 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2444 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2445 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2446 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2447
2448 temp = I915_READ(SOUTH_CHICKEN1);
2449 temp &= ~FDI_BC_BIFURCATION_SELECT;
2450 DRM_DEBUG_KMS("disabling fdi C rx\n");
2451 I915_WRITE(SOUTH_CHICKEN1, temp);
2452 }
2453}
2454
8db9d77b
ZW		 2455/* The FDI link training functions for ILK/Ibexpeak. */
2456static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2457{
2458 struct drm_device *dev = crtc->dev;
2459 struct drm_i915_private *dev_priv = dev->dev_private;
2460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2461 int pipe = intel_crtc->pipe;
0fc932b8 2462 int plane = intel_crtc->plane;
5eddb70b 2463 u32 reg, temp, tries;
8db9d77b 2464
0fc932b8
JB		 2465 /* FDI needs bits from pipe & plane first */
2466 assert_pipe_enabled(dev_priv, pipe);
2467 assert_plane_enabled(dev_priv, plane);
2468
e1a44743
AJ		 2469 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2470 for train result */
5eddb70b
CW		 2471 reg = FDI_RX_IMR(pipe);
2472 temp = I915_READ(reg);
e1a44743
AJ		 2473 temp &= ~FDI_RX_SYMBOL_LOCK;
2474 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2475 I915_WRITE(reg, temp);
2476 I915_READ(reg);
e1a44743
AJ		 2477 udelay(150);
2478
8db9d77b 2479 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2480 reg = FDI_TX_CTL(pipe);
2481 temp = I915_READ(reg);
627eb5a3
DV		 2482 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2483 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2484 temp &= ~FDI_LINK_TRAIN_NONE;
2485 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2486 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2487
5eddb70b
CW		 2488 reg = FDI_RX_CTL(pipe);
2489 temp = I915_READ(reg);
8db9d77b
ZW		 2490 temp &= ~FDI_LINK_TRAIN_NONE;
2491 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2492 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2493
2494 POSTING_READ(reg);
8db9d77b
ZW		 2495 udelay(150);
2496
5b2adf89 2497 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2498 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2499 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2500 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2501
5eddb70b 2502 reg = FDI_RX_IIR(pipe);
e1a44743 2503 for (tries = 0; tries < 5; tries++) {
5eddb70b 2504 temp = I915_READ(reg);
8db9d77b
ZW		 2505 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2506
2507 if ((temp & FDI_RX_BIT_LOCK)) {
2508 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2509 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2510 break;
2511 }
8db9d77b 2512 }
e1a44743 2513 if (tries == 5)
5eddb70b 2514 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2515
2516 /* Train 2 */
5eddb70b
CW		 2517 reg = FDI_TX_CTL(pipe);
2518 temp = I915_READ(reg);
8db9d77b
ZW		 2519 temp &= ~FDI_LINK_TRAIN_NONE;
2520 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2521 I915_WRITE(reg, temp);
8db9d77b 2522
5eddb70b
CW		 2523 reg = FDI_RX_CTL(pipe);
2524 temp = I915_READ(reg);
8db9d77b
ZW		 2525 temp &= ~FDI_LINK_TRAIN_NONE;
2526 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2527 I915_WRITE(reg, temp);
8db9d77b 2528
5eddb70b
CW		 2529 POSTING_READ(reg);
2530 udelay(150);
8db9d77b 2531
5eddb70b 2532 reg = FDI_RX_IIR(pipe);
e1a44743 2533 for (tries = 0; tries < 5; tries++) {
5eddb70b 2534 temp = I915_READ(reg);
8db9d77b
ZW		 2535 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2536
2537 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2538 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2539 DRM_DEBUG_KMS("FDI train 2 done.\n");
2540 break;
2541 }
8db9d77b 2542 }
e1a44743 2543 if (tries == 5)
5eddb70b 2544 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2545
2546 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2547
8db9d77b
ZW		 2548}
2549
0206e353 2550static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2551 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2552 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2553 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2554 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2555};
2556
2557/* The FDI link training functions for SNB/Cougarpoint. */
2558static void gen6_fdi_link_train(struct drm_crtc *crtc)
2559{
2560 struct drm_device *dev = crtc->dev;
2561 struct drm_i915_private *dev_priv = dev->dev_private;
2562 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2563 int pipe = intel_crtc->pipe;
fa37d39e 2564 u32 reg, temp, i, retry;
8db9d77b 2565
e1a44743
AJ		 2566 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2567 for train result */
5eddb70b
CW		 2568 reg = FDI_RX_IMR(pipe);
2569 temp = I915_READ(reg);
e1a44743
AJ		 2570 temp &= ~FDI_RX_SYMBOL_LOCK;
2571 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2572 I915_WRITE(reg, temp);
2573
2574 POSTING_READ(reg);
e1a44743
AJ		 2575 udelay(150);
2576
8db9d77b 2577 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2578 reg = FDI_TX_CTL(pipe);
2579 temp = I915_READ(reg);
627eb5a3
DV		 2580 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2581 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2582 temp &= ~FDI_LINK_TRAIN_NONE;
2583 temp |= FDI_LINK_TRAIN_PATTERN_1;
2584 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2585 /* SNB-B */
2586 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2587 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2588
d74cf324
DV		 2589 I915_WRITE(FDI_RX_MISC(pipe),
2590 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2591
5eddb70b
CW		 2592 reg = FDI_RX_CTL(pipe);
2593 temp = I915_READ(reg);
8db9d77b
ZW		 2594 if (HAS_PCH_CPT(dev)) {
2595 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2596 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2597 } else {
2598 temp &= ~FDI_LINK_TRAIN_NONE;
2599 temp |= FDI_LINK_TRAIN_PATTERN_1;
2600 }
5eddb70b
CW		 2601 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2602
2603 POSTING_READ(reg);
8db9d77b
ZW		 2604 udelay(150);
2605
0206e353 2606 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2607 reg = FDI_TX_CTL(pipe);
2608 temp = I915_READ(reg);
8db9d77b
ZW		 2609 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2610 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2611 I915_WRITE(reg, temp);
2612
2613 POSTING_READ(reg);
8db9d77b
ZW		 2614 udelay(500);
2615
fa37d39e
SP		 2616 for (retry = 0; retry < 5; retry++) {
2617 reg = FDI_RX_IIR(pipe);
2618 temp = I915_READ(reg);
2619 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2620 if (temp & FDI_RX_BIT_LOCK) {
2621 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2622 DRM_DEBUG_KMS("FDI train 1 done.\n");
2623 break;
2624 }
2625 udelay(50);
8db9d77b 2626 }
fa37d39e
SP		 2627 if (retry < 5)
2628 break;
8db9d77b
ZW		 2629 }
2630 if (i == 4)
5eddb70b 2631 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2632
2633 /* Train 2 */
5eddb70b
CW		 2634 reg = FDI_TX_CTL(pipe);
2635 temp = I915_READ(reg);
8db9d77b
ZW		 2636 temp &= ~FDI_LINK_TRAIN_NONE;
2637 temp |= FDI_LINK_TRAIN_PATTERN_2;
2638 if (IS_GEN6(dev)) {
2639 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2640 /* SNB-B */
2641 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2642 }
5eddb70b 2643 I915_WRITE(reg, temp);
8db9d77b 2644
5eddb70b
CW		 2645 reg = FDI_RX_CTL(pipe);
2646 temp = I915_READ(reg);
8db9d77b
ZW		 2647 if (HAS_PCH_CPT(dev)) {
2648 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2649 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2650 } else {
2651 temp &= ~FDI_LINK_TRAIN_NONE;
2652 temp |= FDI_LINK_TRAIN_PATTERN_2;
2653 }
5eddb70b
CW		 2654 I915_WRITE(reg, temp);
2655
2656 POSTING_READ(reg);
8db9d77b
ZW		 2657 udelay(150);
2658
0206e353 2659 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2660 reg = FDI_TX_CTL(pipe);
2661 temp = I915_READ(reg);
8db9d77b
ZW		 2662 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2663 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2664 I915_WRITE(reg, temp);
2665
2666 POSTING_READ(reg);
8db9d77b
ZW		 2667 udelay(500);
2668
fa37d39e
SP		 2669 for (retry = 0; retry < 5; retry++) {
2670 reg = FDI_RX_IIR(pipe);
2671 temp = I915_READ(reg);
2672 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2673 if (temp & FDI_RX_SYMBOL_LOCK) {
2674 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2675 DRM_DEBUG_KMS("FDI train 2 done.\n");
2676 break;
2677 }
2678 udelay(50);
8db9d77b 2679 }
fa37d39e
SP		 2680 if (retry < 5)
2681 break;
8db9d77b
ZW		 2682 }
2683 if (i == 4)
5eddb70b 2684 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2685
2686 DRM_DEBUG_KMS("FDI train done.\n");
2687}
2688
357555c0
JB		 2689/* Manual link training for Ivy Bridge A0 parts */
2690static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2691{
2692 struct drm_device *dev = crtc->dev;
2693 struct drm_i915_private *dev_priv = dev->dev_private;
2694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2695 int pipe = intel_crtc->pipe;
139ccd3f 2696 u32 reg, temp, i, j;
357555c0
JB		 2697
2698 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2699 for train result */
2700 reg = FDI_RX_IMR(pipe);
2701 temp = I915_READ(reg);
2702 temp &= ~FDI_RX_SYMBOL_LOCK;
2703 temp &= ~FDI_RX_BIT_LOCK;
2704 I915_WRITE(reg, temp);
2705
2706 POSTING_READ(reg);
2707 udelay(150);
2708
01a415fd
DV		 2709 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2710 I915_READ(FDI_RX_IIR(pipe)));
2711
139ccd3f
JB		 2712 /* Try each vswing and preemphasis setting twice before moving on */
2713 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2714 /* disable first in case we need to retry */
2715 reg = FDI_TX_CTL(pipe);
2716 temp = I915_READ(reg);
2717 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2718 temp &= ~FDI_TX_ENABLE;
2719 I915_WRITE(reg, temp);
357555c0 2720
139ccd3f
JB		 2721 reg = FDI_RX_CTL(pipe);
2722 temp = I915_READ(reg);
2723 temp &= ~FDI_LINK_TRAIN_AUTO;
2724 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2725 temp &= ~FDI_RX_ENABLE;
2726 I915_WRITE(reg, temp);
357555c0 2727
139ccd3f 2728 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2729 reg = FDI_TX_CTL(pipe);
2730 temp = I915_READ(reg);
139ccd3f
JB		 2731 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2732 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2733 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2734 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2735 temp |= snb_b_fdi_train_param[j/2];
2736 temp |= FDI_COMPOSITE_SYNC;
2737 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2738
139ccd3f
JB		 2739 I915_WRITE(FDI_RX_MISC(pipe),
2740 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2741
139ccd3f 2742 reg = FDI_RX_CTL(pipe);
357555c0 2743 temp = I915_READ(reg);
139ccd3f
JB		 2744 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2745 temp |= FDI_COMPOSITE_SYNC;
2746 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2747
139ccd3f
JB		 2748 POSTING_READ(reg);
2749 udelay(1); /* should be 0.5us */
357555c0 2750
139ccd3f
JB		 2751 for (i = 0; i < 4; i++) {
2752 reg = FDI_RX_IIR(pipe);
2753 temp = I915_READ(reg);
2754 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2755
139ccd3f
JB		 2756 if (temp & FDI_RX_BIT_LOCK ||
2757 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2758 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2759 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2760 i);
2761 break;
2762 }
2763 udelay(1); /* should be 0.5us */
2764 }
2765 if (i == 4) {
2766 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2767 continue;
2768 }
357555c0 2769
139ccd3f 2770 /* Train 2 */
357555c0
JB		 2771 reg = FDI_TX_CTL(pipe);
2772 temp = I915_READ(reg);
139ccd3f
JB		 2773 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2774 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2775 I915_WRITE(reg, temp);
2776
2777 reg = FDI_RX_CTL(pipe);
2778 temp = I915_READ(reg);
2779 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2780 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2781 I915_WRITE(reg, temp);
2782
2783 POSTING_READ(reg);
139ccd3f 2784 udelay(2); /* should be 1.5us */
357555c0 2785
139ccd3f
JB		 2786 for (i = 0; i < 4; i++) {
2787 reg = FDI_RX_IIR(pipe);
2788 temp = I915_READ(reg);
2789 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2790
139ccd3f
JB		 2791 if (temp & FDI_RX_SYMBOL_LOCK ||
2792 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2793 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2794 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2795 i);
2796 goto train_done;
2797 }
2798 udelay(2); /* should be 1.5us */
357555c0 2799 }
139ccd3f
JB		 2800 if (i == 4)
2801 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2802 }
357555c0 2803
139ccd3f 2804train_done:
357555c0
JB		 2805 DRM_DEBUG_KMS("FDI train done.\n");
2806}
2807
88cefb6c 2808static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2809{
88cefb6c 2810 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2811 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2812 int pipe = intel_crtc->pipe;
5eddb70b 2813 u32 reg, temp;
79e53945 2814
c64e311e 2815
c98e9dcf 2816 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2817 reg = FDI_RX_CTL(pipe);
2818 temp = I915_READ(reg);
627eb5a3
DV		 2819 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2820 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2821 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2822 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2823
2824 POSTING_READ(reg);
c98e9dcf
JB		 2825 udelay(200);
2826
2827 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2828 temp = I915_READ(reg);
2829 I915_WRITE(reg, temp | FDI_PCDCLK);
2830
2831 POSTING_READ(reg);
c98e9dcf
JB		 2832 udelay(200);
2833
20749730
PZ		 2834 /* Enable CPU FDI TX PLL, always on for Ironlake */
2835 reg = FDI_TX_CTL(pipe);
2836 temp = I915_READ(reg);
2837 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2838 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2839
20749730
PZ		 2840 POSTING_READ(reg);
2841 udelay(100);
6be4a607 2842 }
0e23b99d
JB		 2843}
2844
88cefb6c
DV		 2845static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2846{
2847 struct drm_device *dev = intel_crtc->base.dev;
2848 struct drm_i915_private *dev_priv = dev->dev_private;
2849 int pipe = intel_crtc->pipe;
2850 u32 reg, temp;
2851
2852 /* Switch from PCDclk to Rawclk */
2853 reg = FDI_RX_CTL(pipe);
2854 temp = I915_READ(reg);
2855 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2856
2857 /* Disable CPU FDI TX PLL */
2858 reg = FDI_TX_CTL(pipe);
2859 temp = I915_READ(reg);
2860 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2861
2862 POSTING_READ(reg);
2863 udelay(100);
2864
2865 reg = FDI_RX_CTL(pipe);
2866 temp = I915_READ(reg);
2867 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2868
2869 /* Wait for the clocks to turn off. */
2870 POSTING_READ(reg);
2871 udelay(100);
2872}
2873
0fc932b8
JB		 2874static void ironlake_fdi_disable(struct drm_crtc *crtc)
2875{
2876 struct drm_device *dev = crtc->dev;
2877 struct drm_i915_private *dev_priv = dev->dev_private;
2878 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2879 int pipe = intel_crtc->pipe;
2880 u32 reg, temp;
2881
2882 /* disable CPU FDI tx and PCH FDI rx */
2883 reg = FDI_TX_CTL(pipe);
2884 temp = I915_READ(reg);
2885 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2886 POSTING_READ(reg);
2887
2888 reg = FDI_RX_CTL(pipe);
2889 temp = I915_READ(reg);
2890 temp &= ~(0x7 << 16);
dfd07d72 2891 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2892 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2893
2894 POSTING_READ(reg);
2895 udelay(100);
2896
2897 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2898 if (HAS_PCH_IBX(dev)) {
2899 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2900 }
0fc932b8
JB		 2901
2902 /* still set train pattern 1 */
2903 reg = FDI_TX_CTL(pipe);
2904 temp = I915_READ(reg);
2905 temp &= ~FDI_LINK_TRAIN_NONE;
2906 temp |= FDI_LINK_TRAIN_PATTERN_1;
2907 I915_WRITE(reg, temp);
2908
2909 reg = FDI_RX_CTL(pipe);
2910 temp = I915_READ(reg);
2911 if (HAS_PCH_CPT(dev)) {
2912 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2913 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2914 } else {
2915 temp &= ~FDI_LINK_TRAIN_NONE;
2916 temp |= FDI_LINK_TRAIN_PATTERN_1;
2917 }
2918 /* BPC in FDI rx is consistent with that in PIPECONF */
2919 temp &= ~(0x07 << 16);
dfd07d72 2920 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2921 I915_WRITE(reg, temp);
2922
2923 POSTING_READ(reg);
2924 udelay(100);
2925}
2926
5bb61643
CW		 2927static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2928{
2929 struct drm_device *dev = crtc->dev;
2930 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2931 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2932 unsigned long flags;
2933 bool pending;
2934
10d83730
VS		 2935 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2936 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2937 return false;
2938
2939 spin_lock_irqsave(&dev->event_lock, flags);
2940 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2941 spin_unlock_irqrestore(&dev->event_lock, flags);
2942
2943 return pending;
2944}
2945
e6c3a2a6
CW		 2946static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2947{
0f91128d 2948 struct drm_device *dev = crtc->dev;
5bb61643 2949 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2950
2951 if (crtc->fb == NULL)
2952 return;
2953
2c10d571
DV		 2954 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2955
5bb61643
CW		 2956 wait_event(dev_priv->pending_flip_queue,
2957 !intel_crtc_has_pending_flip(crtc));
2958
0f91128d
CW		 2959 mutex_lock(&dev->struct_mutex);
2960 intel_finish_fb(crtc->fb);
2961 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2962}
2963
e615efe4
ED		 2964/* Program iCLKIP clock to the desired frequency */
2965static void lpt_program_iclkip(struct drm_crtc *crtc)
2966{
2967 struct drm_device *dev = crtc->dev;
2968 struct drm_i915_private *dev_priv = dev->dev_private;
241bfc38 2969 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
e615efe4
ED		 2970 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2971 u32 temp;
2972
09153000
DV		 2973 mutex_lock(&dev_priv->dpio_lock);
2974
e615efe4
ED		 2975 /* It is necessary to ungate the pixclk gate prior to programming
2976 * the divisors, and gate it back when it is done.
2977 */
2978 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2979
2980 /* Disable SSCCTL */
2981 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2982 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2983 SBI_SSCCTL_DISABLE,
2984 SBI_ICLK);
e615efe4
ED		 2985
2986 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 2987 if (clock == 20000) {
e615efe4
ED		 2988 auxdiv = 1;
2989 divsel = 0x41;
2990 phaseinc = 0x20;
2991 } else {
2992 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 2993 * but the adjusted_mode->crtc_clock in in KHz. To get the
2994 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 2995 * convert the virtual clock precision to KHz here for higher
2996 * precision.
2997 */
2998 u32 iclk_virtual_root_freq = 172800 * 1000;
2999 u32 iclk_pi_range = 64;
3000 u32 desired_divisor, msb_divisor_value, pi_value;
3001
12d7ceed 3002 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3003 msb_divisor_value = desired_divisor / iclk_pi_range;
3004 pi_value = desired_divisor % iclk_pi_range;
3005
3006 auxdiv = 0;
3007 divsel = msb_divisor_value - 2;
3008 phaseinc = pi_value;
3009 }
3010
3011 /* This should not happen with any sane values */
3012 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3013 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3014 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3015 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3016
3017 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3018 clock,
e615efe4
ED		 3019 auxdiv,
3020 divsel,
3021 phasedir,
3022 phaseinc);
3023
3024 /* Program SSCDIVINTPHASE6 */
988d6ee8 3025 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3026 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3027 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3028 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3029 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3030 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3031 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3032 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3033
3034 /* Program SSCAUXDIV */
988d6ee8 3035 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3036 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3037 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3038 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3039
3040 /* Enable modulator and associated divider */
988d6ee8 3041 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3042 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3043 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3044
3045 /* Wait for initialization time */
3046 udelay(24);
3047
3048 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3049
3050 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3051}
3052
275f01b2
DV		 3053static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3054 enum pipe pch_transcoder)
3055{
3056 struct drm_device *dev = crtc->base.dev;
3057 struct drm_i915_private *dev_priv = dev->dev_private;
3058 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3059
3060 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3061 I915_READ(HTOTAL(cpu_transcoder)));
3062 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3063 I915_READ(HBLANK(cpu_transcoder)));
3064 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3065 I915_READ(HSYNC(cpu_transcoder)));
3066
3067 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3068 I915_READ(VTOTAL(cpu_transcoder)));
3069 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3070 I915_READ(VBLANK(cpu_transcoder)));
3071 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3072 I915_READ(VSYNC(cpu_transcoder)));
3073 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3074 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3075}
3076
f67a559d
JB		 3077/*
3078 * Enable PCH resources required for PCH ports:
3079 * - PCH PLLs
3080 * - FDI training & RX/TX
3081 * - update transcoder timings
3082 * - DP transcoding bits
3083 * - transcoder
3084 */
3085static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3086{
3087 struct drm_device *dev = crtc->dev;
3088 struct drm_i915_private *dev_priv = dev->dev_private;
3089 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3090 int pipe = intel_crtc->pipe;
ee7b9f93 3091 u32 reg, temp;
2c07245f 3092
ab9412ba 3093 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3094
cd986abb
DV		 3095 /* Write the TU size bits before fdi link training, so that error
3096 * detection works. */
3097 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3098 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3099
c98e9dcf 3100 /* For PCH output, training FDI link */
674cf967 3101 dev_priv->display.fdi_link_train(crtc);
2c07245f 3102
3ad8a208
DV		 3103 /* We need to program the right clock selection before writing the pixel
3104 * mutliplier into the DPLL. */
303b81e0 3105 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3106 u32 sel;
4b645f14 3107
c98e9dcf 3108 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3109 temp |= TRANS_DPLL_ENABLE(pipe);
3110 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3111 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3112 temp |= sel;
3113 else
3114 temp &= ~sel;
c98e9dcf 3115 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3116 }
5eddb70b 3117
3ad8a208
DV		 3118 /* XXX: pch pll's can be enabled any time before we enable the PCH
3119 * transcoder, and we actually should do this to not upset any PCH
3120 * transcoder that already use the clock when we share it.
3121 *
3122 * Note that enable_shared_dpll tries to do the right thing, but
3123 * get_shared_dpll unconditionally resets the pll - we need that to have
3124 * the right LVDS enable sequence. */
3125 ironlake_enable_shared_dpll(intel_crtc);
3126
d9b6cb56
JB		 3127 /* set transcoder timing, panel must allow it */
3128 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3129 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3130
303b81e0 3131 intel_fdi_normal_train(crtc);
5e84e1a4 3132
c98e9dcf
JB		 3133 /* For PCH DP, enable TRANS_DP_CTL */
3134 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3135 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3136 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3137 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3138 reg = TRANS_DP_CTL(pipe);
3139 temp = I915_READ(reg);
3140 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3141 TRANS_DP_SYNC_MASK |
3142 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3143 temp |= (TRANS_DP_OUTPUT_ENABLE |
3144 TRANS_DP_ENH_FRAMING);
9325c9f0 3145 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3146
3147 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3148 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3149 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3150 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3151
3152 switch (intel_trans_dp_port_sel(crtc)) {
3153 case PCH_DP_B:
5eddb70b 3154 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3155 break;
3156 case PCH_DP_C:
5eddb70b 3157 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3158 break;
3159 case PCH_DP_D:
5eddb70b 3160 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3161 break;
3162 default:
e95d41e1 3163 BUG();
32f9d658 3164 }
2c07245f 3165
5eddb70b 3166 I915_WRITE(reg, temp);
6be4a607 3167 }
b52eb4dc 3168
b8a4f404 3169 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3170}
3171
1507e5bd
PZ		 3172static void lpt_pch_enable(struct drm_crtc *crtc)
3173{
3174 struct drm_device *dev = crtc->dev;
3175 struct drm_i915_private *dev_priv = dev->dev_private;
3176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3177 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3178
ab9412ba 3179 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3180
8c52b5e8 3181 lpt_program_iclkip(crtc);
1507e5bd 3182
0540e488 3183 /* Set transcoder timing. */
275f01b2 3184 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3185
937bb610 3186 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3187}
3188
e2b78267 3189static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3190{
e2b78267 3191 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3192
3193 if (pll == NULL)
3194 return;
3195
3196 if (pll->refcount == 0) {
46edb027 3197 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3198 return;
3199 }
3200
f4a091c7
DV		 3201 if (--pll->refcount == 0) {
3202 WARN_ON(pll->on);
3203 WARN_ON(pll->active);
3204 }
3205
a43f6e0f 3206 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3207}
3208
b89a1d39 3209static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3210{
e2b78267
DV		 3211 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3212 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3213 enum intel_dpll_id i;
ee7b9f93 3214
ee7b9f93 3215 if (pll) {
46edb027
DV		 3216 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3217 crtc->base.base.id, pll->name);
e2b78267 3218 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3219 }
3220
98b6bd99
DV		 3221 if (HAS_PCH_IBX(dev_priv->dev)) {
3222 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3223 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3224 pll = &dev_priv->shared_dplls[i];
98b6bd99 3225
46edb027
DV		 3226 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3227 crtc->base.base.id, pll->name);
98b6bd99
DV		 3228
3229 goto found;
3230 }
3231
e72f9fbf
DV		 3232 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3233 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3234
3235 /* Only want to check enabled timings first */
3236 if (pll->refcount == 0)
3237 continue;
3238
b89a1d39
DV		 3239 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3240 sizeof(pll->hw_state)) == 0) {
46edb027 3241 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3242 crtc->base.base.id,
46edb027 3243 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3244
3245 goto found;
3246 }
3247 }
3248
3249 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3250 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3251 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3252 if (pll->refcount == 0) {
46edb027
DV		 3253 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3254 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3255 goto found;
3256 }
3257 }
3258
3259 return NULL;
3260
3261found:
a43f6e0f 3262 crtc->config.shared_dpll = i;
46edb027
DV		 3263 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3264 pipe_name(crtc->pipe));
ee7b9f93 3265
cdbd2316 3266 if (pll->active == 0) {
66e985c0
DV		 3267 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3268 sizeof(pll->hw_state));
3269
46edb027 3270 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3271 WARN_ON(pll->on);
e9d6944e 3272 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3273
15bdd4cf 3274 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3275 }
3276 pll->refcount++;
e04c7350 3277
ee7b9f93
JB		 3278 return pll;
3279}
3280
a1520318 3281static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3282{
3283 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3284 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3285 u32 temp;
3286
3287 temp = I915_READ(dslreg);
3288 udelay(500);
3289 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3290 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3291 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3292 }
3293}
3294
b074cec8
JB		 3295static void ironlake_pfit_enable(struct intel_crtc *crtc)
3296{
3297 struct drm_device *dev = crtc->base.dev;
3298 struct drm_i915_private *dev_priv = dev->dev_private;
3299 int pipe = crtc->pipe;
3300
fd4daa9c 3301 if (crtc->config.pch_pfit.enabled) {
b074cec8
JB		 3302 /* Force use of hard-coded filter coefficients
3303 * as some pre-programmed values are broken,
3304 * e.g. x201.
3305 */
3306 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3307 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3308 PF_PIPE_SEL_IVB(pipe));
3309 else
3310 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3311 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3312 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3313 }
3314}
3315
bb53d4ae
VS		 3316static void intel_enable_planes(struct drm_crtc *crtc)
3317{
3318 struct drm_device *dev = crtc->dev;
3319 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3320 struct intel_plane *intel_plane;
3321
3322 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3323 if (intel_plane->pipe == pipe)
3324 intel_plane_restore(&intel_plane->base);
3325}
3326
3327static void intel_disable_planes(struct drm_crtc *crtc)
3328{
3329 struct drm_device *dev = crtc->dev;
3330 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3331 struct intel_plane *intel_plane;
3332
3333 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3334 if (intel_plane->pipe == pipe)
3335 intel_plane_disable(&intel_plane->base);
3336}
3337
20bc8673 3338void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 3339{
3340 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3341
3342 if (!crtc->config.ips_enabled)
3343 return;
3344
3345 /* We can only enable IPS after we enable a plane and wait for a vblank.
3346 * We guarantee that the plane is enabled by calling intel_enable_ips
3347 * only after intel_enable_plane. And intel_enable_plane already waits
3348 * for a vblank, so all we need to do here is to enable the IPS bit. */
3349 assert_plane_enabled(dev_priv, crtc->plane);
3350 I915_WRITE(IPS_CTL, IPS_ENABLE);
5ade2c2f
PZ		 3351
3352 /* The bit only becomes 1 in the next vblank, so this wait here is
3353 * essentially intel_wait_for_vblank. If we don't have this and don't
3354 * wait for vblanks until the end of crtc_enable, then the HW state
3355 * readout code will complain that the expected IPS_CTL value is not the
3356 * one we read. */
3357 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
3358 DRM_ERROR("Timed out waiting for IPS enable\n");
d77e4531
PZ		 3359}
3360
20bc8673 3361void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 3362{
3363 struct drm_device *dev = crtc->base.dev;
3364 struct drm_i915_private *dev_priv = dev->dev_private;
3365
3366 if (!crtc->config.ips_enabled)
3367 return;
3368
3369 assert_plane_enabled(dev_priv, crtc->plane);
3370 I915_WRITE(IPS_CTL, 0);
3371 POSTING_READ(IPS_CTL);
3372
3373 /* We need to wait for a vblank before we can disable the plane. */
3374 intel_wait_for_vblank(dev, crtc->pipe);
3375}
3376
3377/** Loads the palette/gamma unit for the CRTC with the prepared values */
3378static void intel_crtc_load_lut(struct drm_crtc *crtc)
3379{
3380 struct drm_device *dev = crtc->dev;
3381 struct drm_i915_private *dev_priv = dev->dev_private;
3382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3383 enum pipe pipe = intel_crtc->pipe;
3384 int palreg = PALETTE(pipe);
3385 int i;
3386 bool reenable_ips = false;
3387
3388 /* The clocks have to be on to load the palette. */
3389 if (!crtc->enabled || !intel_crtc->active)
3390 return;
3391
3392 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3393 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3394 assert_dsi_pll_enabled(dev_priv);
3395 else
3396 assert_pll_enabled(dev_priv, pipe);
3397 }
3398
3399 /* use legacy palette for Ironlake */
3400 if (HAS_PCH_SPLIT(dev))
3401 palreg = LGC_PALETTE(pipe);
3402
3403 /* Workaround : Do not read or write the pipe palette/gamma data while
3404 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3405 */
3406 if (intel_crtc->config.ips_enabled &&
3407 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3408 GAMMA_MODE_MODE_SPLIT)) {
3409 hsw_disable_ips(intel_crtc);
3410 reenable_ips = true;
3411 }
3412
3413 for (i = 0; i < 256; i++) {
3414 I915_WRITE(palreg + 4 * i,
3415 (intel_crtc->lut_r[i] << 16) |
3416 (intel_crtc->lut_g[i] << 8) |
3417 intel_crtc->lut_b[i]);
3418 }
3419
3420 if (reenable_ips)
3421 hsw_enable_ips(intel_crtc);
3422}
3423
f67a559d
JB		 3424static void ironlake_crtc_enable(struct drm_crtc *crtc)
3425{
3426 struct drm_device *dev = crtc->dev;
3427 struct drm_i915_private *dev_priv = dev->dev_private;
3428 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3429 struct intel_encoder *encoder;
f67a559d
JB		 3430 int pipe = intel_crtc->pipe;
3431 int plane = intel_crtc->plane;
f67a559d 3432
08a48469
DV		 3433 WARN_ON(!crtc->enabled);
3434
f67a559d
JB		 3435 if (intel_crtc->active)
3436 return;
3437
3438 intel_crtc->active = true;
8664281b
PZ		 3439
3440 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3441 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3442
f6736a1a 3443 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3444 if (encoder->pre_enable)
3445 encoder->pre_enable(encoder);
f67a559d 3446
5bfe2ac0 3447 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3448 /* Note: FDI PLL enabling _must_ be done before we enable the
3449 * cpu pipes, hence this is separate from all the other fdi/pch
3450 * enabling. */
88cefb6c 3451 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3452 } else {
3453 assert_fdi_tx_disabled(dev_priv, pipe);
3454 assert_fdi_rx_disabled(dev_priv, pipe);
3455 }
f67a559d 3456
b074cec8 3457 ironlake_pfit_enable(intel_crtc);
f67a559d 3458
9c54c0dd
JB		 3459 /*
3460 * On ILK+ LUT must be loaded before the pipe is running but with
3461 * clocks enabled
3462 */
3463 intel_crtc_load_lut(crtc);
3464
f37fcc2a 3465 intel_update_watermarks(crtc);
5bfe2ac0 3466 intel_enable_pipe(dev_priv, pipe,
23538ef1 3467 intel_crtc->config.has_pch_encoder, false);
d1de00ef 3468 intel_enable_primary_plane(dev_priv, plane, pipe);
bb53d4ae 3469 intel_enable_planes(crtc);
5c38d48c 3470 intel_crtc_update_cursor(crtc, true);
f67a559d 3471
5bfe2ac0 3472 if (intel_crtc->config.has_pch_encoder)
f67a559d 3473 ironlake_pch_enable(crtc);
c98e9dcf 3474
d1ebd816 3475 mutex_lock(&dev->struct_mutex);
bed4a673 3476 intel_update_fbc(dev);
d1ebd816
BW		 3477 mutex_unlock(&dev->struct_mutex);
3478
fa5c73b1
DV		 3479 for_each_encoder_on_crtc(dev, crtc, encoder)
3480 encoder->enable(encoder);
61b77ddd
DV		 3481
3482 if (HAS_PCH_CPT(dev))
a1520318 3483 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3484
3485 /*
3486 * There seems to be a race in PCH platform hw (at least on some
3487 * outputs) where an enabled pipe still completes any pageflip right
3488 * away (as if the pipe is off) instead of waiting for vblank. As soon
3489 * as the first vblank happend, everything works as expected. Hence just
3490 * wait for one vblank before returning to avoid strange things
3491 * happening.
3492 */
3493 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3494}
3495
42db64ef
PZ		 3496/* IPS only exists on ULT machines and is tied to pipe A. */
3497static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3498{
f5adf94e 3499 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3500}
3501
dda9a66a
VS		 3502static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3503{
3504 struct drm_device *dev = crtc->dev;
3505 struct drm_i915_private *dev_priv = dev->dev_private;
3506 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3507 int pipe = intel_crtc->pipe;
3508 int plane = intel_crtc->plane;
3509
d1de00ef 3510 intel_enable_primary_plane(dev_priv, plane, pipe);
dda9a66a
VS		 3511 intel_enable_planes(crtc);
3512 intel_crtc_update_cursor(crtc, true);
3513
3514 hsw_enable_ips(intel_crtc);
3515
3516 mutex_lock(&dev->struct_mutex);
3517 intel_update_fbc(dev);
3518 mutex_unlock(&dev->struct_mutex);
3519}
3520
3521static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3522{
3523 struct drm_device *dev = crtc->dev;
3524 struct drm_i915_private *dev_priv = dev->dev_private;
3525 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3526 int pipe = intel_crtc->pipe;
3527 int plane = intel_crtc->plane;
3528
3529 intel_crtc_wait_for_pending_flips(crtc);
3530 drm_vblank_off(dev, pipe);
3531
3532 /* FBC must be disabled before disabling the plane on HSW. */
3533 if (dev_priv->fbc.plane == plane)
3534 intel_disable_fbc(dev);
3535
3536 hsw_disable_ips(intel_crtc);
3537
3538 intel_crtc_update_cursor(crtc, false);
3539 intel_disable_planes(crtc);
d1de00ef 3540 intel_disable_primary_plane(dev_priv, plane, pipe);
dda9a66a
VS		 3541}
3542
e4916946
PZ		 3543/*
3544 * This implements the workaround described in the "notes" section of the mode
3545 * set sequence documentation. When going from no pipes or single pipe to
3546 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3547 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3548 */
3549static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3550{
3551 struct drm_device *dev = crtc->base.dev;
3552 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3553
3554 /* We want to get the other_active_crtc only if there's only 1 other
3555 * active crtc. */
3556 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3557 if (!crtc_it->active || crtc_it == crtc)
3558 continue;
3559
3560 if (other_active_crtc)
3561 return;
3562
3563 other_active_crtc = crtc_it;
3564 }
3565 if (!other_active_crtc)
3566 return;
3567
3568 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3569 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3570}
3571
4f771f10
PZ		 3572static void haswell_crtc_enable(struct drm_crtc *crtc)
3573{
3574 struct drm_device *dev = crtc->dev;
3575 struct drm_i915_private *dev_priv = dev->dev_private;
3576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3577 struct intel_encoder *encoder;
3578 int pipe = intel_crtc->pipe;
4f771f10
PZ		 3579
3580 WARN_ON(!crtc->enabled);
3581
3582 if (intel_crtc->active)
3583 return;
3584
3585 intel_crtc->active = true;
8664281b
PZ		 3586
3587 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3588 if (intel_crtc->config.has_pch_encoder)
3589 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3590
5bfe2ac0 3591 if (intel_crtc->config.has_pch_encoder)
04945641 3592 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3593
3594 for_each_encoder_on_crtc(dev, crtc, encoder)
3595 if (encoder->pre_enable)
3596 encoder->pre_enable(encoder);
3597
1f544388 3598 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3599
b074cec8 3600 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3601
3602 /*
3603 * On ILK+ LUT must be loaded before the pipe is running but with
3604 * clocks enabled
3605 */
3606 intel_crtc_load_lut(crtc);
3607
1f544388 3608 intel_ddi_set_pipe_settings(crtc);
8228c251 3609 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3610
f37fcc2a 3611 intel_update_watermarks(crtc);
5bfe2ac0 3612 intel_enable_pipe(dev_priv, pipe,
23538ef1 3613 intel_crtc->config.has_pch_encoder, false);
42db64ef 3614
5bfe2ac0 3615 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3616 lpt_pch_enable(crtc);
4f771f10 3617
8807e55b 3618 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3619 encoder->enable(encoder);
8807e55b
JN		 3620 intel_opregion_notify_encoder(encoder, true);
3621 }
4f771f10 3622
e4916946
PZ		 3623 /* If we change the relative order between pipe/planes enabling, we need
3624 * to change the workaround. */
3625 haswell_mode_set_planes_workaround(intel_crtc);
dda9a66a
VS		 3626 haswell_crtc_enable_planes(crtc);
3627
4f771f10
PZ		 3628 /*
3629 * There seems to be a race in PCH platform hw (at least on some
3630 * outputs) where an enabled pipe still completes any pageflip right
3631 * away (as if the pipe is off) instead of waiting for vblank. As soon
3632 * as the first vblank happend, everything works as expected. Hence just
3633 * wait for one vblank before returning to avoid strange things
3634 * happening.
3635 */
3636 intel_wait_for_vblank(dev, intel_crtc->pipe);
3637}
3638
3f8dce3a
DV		 3639static void ironlake_pfit_disable(struct intel_crtc *crtc)
3640{
3641 struct drm_device *dev = crtc->base.dev;
3642 struct drm_i915_private *dev_priv = dev->dev_private;
3643 int pipe = crtc->pipe;
3644
3645 /* To avoid upsetting the power well on haswell only disable the pfit if
3646 * it's in use. The hw state code will make sure we get this right. */
fd4daa9c 3647 if (crtc->config.pch_pfit.enabled) {
3f8dce3a
DV		 3648 I915_WRITE(PF_CTL(pipe), 0);
3649 I915_WRITE(PF_WIN_POS(pipe), 0);
3650 I915_WRITE(PF_WIN_SZ(pipe), 0);
3651 }
3652}
3653
6be4a607
JB		 3654static void ironlake_crtc_disable(struct drm_crtc *crtc)
3655{
3656 struct drm_device *dev = crtc->dev;
3657 struct drm_i915_private *dev_priv = dev->dev_private;
3658 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3659 struct intel_encoder *encoder;
6be4a607
JB		 3660 int pipe = intel_crtc->pipe;
3661 int plane = intel_crtc->plane;
5eddb70b 3662 u32 reg, temp;
b52eb4dc 3663
ef9c3aee 3664
f7abfe8b
CW		 3665 if (!intel_crtc->active)
3666 return;
3667
ea9d758d
DV		 3668 for_each_encoder_on_crtc(dev, crtc, encoder)
3669 encoder->disable(encoder);
3670
e6c3a2a6 3671 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3672 drm_vblank_off(dev, pipe);
913d8d11 3673
5c3fe8b0 3674 if (dev_priv->fbc.plane == plane)
973d04f9 3675 intel_disable_fbc(dev);
2c07245f 3676
0d5b8c61 3677 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3678 intel_disable_planes(crtc);
d1de00ef 3679 intel_disable_primary_plane(dev_priv, plane, pipe);
0d5b8c61 3680
d925c59a
DV		 3681 if (intel_crtc->config.has_pch_encoder)
3682 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3683
b24e7179 3684 intel_disable_pipe(dev_priv, pipe);
32f9d658 3685
3f8dce3a 3686 ironlake_pfit_disable(intel_crtc);
2c07245f 3687
bf49ec8c
DV		 3688 for_each_encoder_on_crtc(dev, crtc, encoder)
3689 if (encoder->post_disable)
3690 encoder->post_disable(encoder);
2c07245f 3691
d925c59a
DV		 3692 if (intel_crtc->config.has_pch_encoder) {
3693 ironlake_fdi_disable(crtc);
913d8d11 3694
d925c59a
DV		 3695 ironlake_disable_pch_transcoder(dev_priv, pipe);
3696 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3697
d925c59a
DV		 3698 if (HAS_PCH_CPT(dev)) {
3699 /* disable TRANS_DP_CTL */
3700 reg = TRANS_DP_CTL(pipe);
3701 temp = I915_READ(reg);
3702 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3703 TRANS_DP_PORT_SEL_MASK);
3704 temp |= TRANS_DP_PORT_SEL_NONE;
3705 I915_WRITE(reg, temp);
3706
3707 /* disable DPLL_SEL */
3708 temp = I915_READ(PCH_DPLL_SEL);
11887397 3709 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3710 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3711 }
e3421a18 3712
d925c59a 3713 /* disable PCH DPLL */
e72f9fbf 3714 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3715
d925c59a
DV		 3716 ironlake_fdi_pll_disable(intel_crtc);
3717 }
6b383a7f 3718
f7abfe8b 3719 intel_crtc->active = false;
46ba614c 3720 intel_update_watermarks(crtc);
d1ebd816
BW		 3721
3722 mutex_lock(&dev->struct_mutex);
6b383a7f 3723 intel_update_fbc(dev);
d1ebd816 3724 mutex_unlock(&dev->struct_mutex);
6be4a607 3725}
1b3c7a47 3726
4f771f10 3727static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3728{
4f771f10
PZ		 3729 struct drm_device *dev = crtc->dev;
3730 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3731 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3732 struct intel_encoder *encoder;
3733 int pipe = intel_crtc->pipe;
3b117c8f 3734 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3735
4f771f10
PZ		 3736 if (!intel_crtc->active)
3737 return;
3738
dda9a66a
VS		 3739 haswell_crtc_disable_planes(crtc);
3740
8807e55b
JN		 3741 for_each_encoder_on_crtc(dev, crtc, encoder) {
3742 intel_opregion_notify_encoder(encoder, false);
4f771f10 3743 encoder->disable(encoder);
8807e55b 3744 }
4f771f10 3745
8664281b
PZ		 3746 if (intel_crtc->config.has_pch_encoder)
3747 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3748 intel_disable_pipe(dev_priv, pipe);
3749
ad80a810 3750 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3751
3f8dce3a 3752 ironlake_pfit_disable(intel_crtc);
4f771f10 3753
1f544388 3754 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3755
3756 for_each_encoder_on_crtc(dev, crtc, encoder)
3757 if (encoder->post_disable)
3758 encoder->post_disable(encoder);
3759
88adfff1 3760 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3761 lpt_disable_pch_transcoder(dev_priv);
8664281b 3762 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3763 intel_ddi_fdi_disable(crtc);
83616634 3764 }
4f771f10
PZ		 3765
3766 intel_crtc->active = false;
46ba614c 3767 intel_update_watermarks(crtc);
4f771f10
PZ		 3768
3769 mutex_lock(&dev->struct_mutex);
3770 intel_update_fbc(dev);
3771 mutex_unlock(&dev->struct_mutex);
3772}
3773
ee7b9f93
JB		 3774static void ironlake_crtc_off(struct drm_crtc *crtc)
3775{
3776 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3777 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3778}
3779
6441ab5f
PZ		 3780static void haswell_crtc_off(struct drm_crtc *crtc)
3781{
3782 intel_ddi_put_crtc_pll(crtc);
3783}
3784
02e792fb
DV		 3785static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3786{
02e792fb 3787 if (!enable && intel_crtc->overlay) {
23f09ce3 3788 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3789 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3790
23f09ce3 3791 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3792 dev_priv->mm.interruptible = false;
3793 (void) intel_overlay_switch_off(intel_crtc->overlay);
3794 dev_priv->mm.interruptible = true;
23f09ce3 3795 mutex_unlock(&dev->struct_mutex);
02e792fb 3796 }
02e792fb 3797
5dcdbcb0
CW		 3798 /* Let userspace switch the overlay on again. In most cases userspace
3799 * has to recompute where to put it anyway.
3800 */
02e792fb
DV		 3801}
3802
61bc95c1
EE		 3803/**
3804 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3805 * cursor plane briefly if not already running after enabling the display
3806 * plane.
3807 * This workaround avoids occasional blank screens when self refresh is
3808 * enabled.
3809 */
3810static void
3811g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3812{
3813 u32 cntl = I915_READ(CURCNTR(pipe));
3814
3815 if ((cntl & CURSOR_MODE) == 0) {
3816 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3817
3818 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3819 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3820 intel_wait_for_vblank(dev_priv->dev, pipe);
3821 I915_WRITE(CURCNTR(pipe), cntl);
3822 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3823 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3824 }
3825}
3826
2dd24552
JB		 3827static void i9xx_pfit_enable(struct intel_crtc *crtc)
3828{
3829 struct drm_device *dev = crtc->base.dev;
3830 struct drm_i915_private *dev_priv = dev->dev_private;
3831 struct intel_crtc_config *pipe_config = &crtc->config;
3832
328d8e82 3833 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3834 return;
3835
2dd24552 3836 /*
c0b03411
DV		 3837 * The panel fitter should only be adjusted whilst the pipe is disabled,
3838 * according to register description and PRM.
2dd24552 3839 */
c0b03411
DV		 3840 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3841 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3842
b074cec8
JB		 3843 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3844 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3845
3846 /* Border color in case we don't scale up to the full screen. Black by
3847 * default, change to something else for debugging. */
3848 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3849}
3850
89b667f8
JB		 3851static void valleyview_crtc_enable(struct drm_crtc *crtc)
3852{
3853 struct drm_device *dev = crtc->dev;
3854 struct drm_i915_private *dev_priv = dev->dev_private;
3855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3856 struct intel_encoder *encoder;
3857 int pipe = intel_crtc->pipe;
3858 int plane = intel_crtc->plane;
23538ef1 3859 bool is_dsi;
89b667f8
JB		 3860
3861 WARN_ON(!crtc->enabled);
3862
3863 if (intel_crtc->active)
3864 return;
3865
3866 intel_crtc->active = true;
89b667f8 3867
89b667f8
JB		 3868 for_each_encoder_on_crtc(dev, crtc, encoder)
3869 if (encoder->pre_pll_enable)
3870 encoder->pre_pll_enable(encoder);
3871
23538ef1
JN		 3872 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3873
e9fd1c02
JN		 3874 if (!is_dsi)
3875 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3876
3877 for_each_encoder_on_crtc(dev, crtc, encoder)
3878 if (encoder->pre_enable)
3879 encoder->pre_enable(encoder);
3880
2dd24552
JB		 3881 i9xx_pfit_enable(intel_crtc);
3882
63cbb074
VS		 3883 intel_crtc_load_lut(crtc);
3884
f37fcc2a 3885 intel_update_watermarks(crtc);
23538ef1 3886 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
d1de00ef 3887 intel_enable_primary_plane(dev_priv, plane, pipe);
bb53d4ae 3888 intel_enable_planes(crtc);
5c38d48c 3889 intel_crtc_update_cursor(crtc, true);
89b667f8 3890
89b667f8 3891 intel_update_fbc(dev);
5004945f
JN		 3892
3893 for_each_encoder_on_crtc(dev, crtc, encoder)
3894 encoder->enable(encoder);
89b667f8
JB		 3895}
3896
0b8765c6 3897static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3898{
3899 struct drm_device *dev = crtc->dev;
79e53945
JB		 3900 struct drm_i915_private *dev_priv = dev->dev_private;
3901 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3902 struct intel_encoder *encoder;
79e53945 3903 int pipe = intel_crtc->pipe;
80824003 3904 int plane = intel_crtc->plane;
79e53945 3905
08a48469
DV		 3906 WARN_ON(!crtc->enabled);
3907
f7abfe8b
CW		 3908 if (intel_crtc->active)
3909 return;
3910
3911 intel_crtc->active = true;
6b383a7f 3912
9d6d9f19
MK		 3913 for_each_encoder_on_crtc(dev, crtc, encoder)
3914 if (encoder->pre_enable)
3915 encoder->pre_enable(encoder);
3916
f6736a1a
DV		 3917 i9xx_enable_pll(intel_crtc);
3918
2dd24552
JB		 3919 i9xx_pfit_enable(intel_crtc);
3920
63cbb074
VS		 3921 intel_crtc_load_lut(crtc);
3922
f37fcc2a 3923 intel_update_watermarks(crtc);
23538ef1 3924 intel_enable_pipe(dev_priv, pipe, false, false);
d1de00ef 3925 intel_enable_primary_plane(dev_priv, plane, pipe);
bb53d4ae 3926 intel_enable_planes(crtc);
22e407d7 3927 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3928 if (IS_G4X(dev))
3929 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3930 intel_crtc_update_cursor(crtc, true);
79e53945 3931
0b8765c6
JB		 3932 /* Give the overlay scaler a chance to enable if it's on this pipe */
3933 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3934
f440eb13 3935 intel_update_fbc(dev);
ef9c3aee 3936
fa5c73b1
DV		 3937 for_each_encoder_on_crtc(dev, crtc, encoder)
3938 encoder->enable(encoder);
0b8765c6 3939}
79e53945 3940
87476d63
DV		 3941static void i9xx_pfit_disable(struct intel_crtc *crtc)
3942{
3943 struct drm_device *dev = crtc->base.dev;
3944 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3945
328d8e82
DV		 3946 if (!crtc->config.gmch_pfit.control)
3947 return;
87476d63 3948
328d8e82 3949 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3950
328d8e82
DV		 3951 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3952 I915_READ(PFIT_CONTROL));
3953 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3954}
3955
0b8765c6
JB		 3956static void i9xx_crtc_disable(struct drm_crtc *crtc)
3957{
3958 struct drm_device *dev = crtc->dev;
3959 struct drm_i915_private *dev_priv = dev->dev_private;
3960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3961 struct intel_encoder *encoder;
0b8765c6
JB		 3962 int pipe = intel_crtc->pipe;
3963 int plane = intel_crtc->plane;
ef9c3aee 3964
f7abfe8b
CW		 3965 if (!intel_crtc->active)
3966 return;
3967
ea9d758d
DV		 3968 for_each_encoder_on_crtc(dev, crtc, encoder)
3969 encoder->disable(encoder);
3970
0b8765c6 3971 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3972 intel_crtc_wait_for_pending_flips(crtc);
3973 drm_vblank_off(dev, pipe);
0b8765c6 3974
5c3fe8b0 3975 if (dev_priv->fbc.plane == plane)
973d04f9 3976 intel_disable_fbc(dev);
79e53945 3977
0d5b8c61
VS		 3978 intel_crtc_dpms_overlay(intel_crtc, false);
3979 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3980 intel_disable_planes(crtc);
d1de00ef 3981 intel_disable_primary_plane(dev_priv, plane, pipe);
0d5b8c61 3982
b24e7179 3983 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3984
87476d63 3985 i9xx_pfit_disable(intel_crtc);
24a1f16d 3986
89b667f8
JB		 3987 for_each_encoder_on_crtc(dev, crtc, encoder)
3988 if (encoder->post_disable)
3989 encoder->post_disable(encoder);
3990
f6071166
JB		 3991 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3992 vlv_disable_pll(dev_priv, pipe);
3993 else if (!IS_VALLEYVIEW(dev))
e9fd1c02 3994 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3995
f7abfe8b 3996 intel_crtc->active = false;
46ba614c 3997 intel_update_watermarks(crtc);
f37fcc2a 3998
6b383a7f 3999 intel_update_fbc(dev);
0b8765c6
JB		 4000}
4001
ee7b9f93
JB		 4002static void i9xx_crtc_off(struct drm_crtc *crtc)
4003{
4004}
4005
976f8a20
DV		 4006static void intel_crtc_update_sarea(struct drm_crtc *crtc,
4007 bool enabled)
2c07245f
ZW		 4008{
4009 struct drm_device *dev = crtc->dev;
4010 struct drm_i915_master_private *master_priv;
4011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4012 int pipe = intel_crtc->pipe;
79e53945
JB		 4013
4014 if (!dev->primary->master)
4015 return;
4016
4017 master_priv = dev->primary->master->driver_priv;
4018 if (!master_priv->sarea_priv)
4019 return;
4020
79e53945
JB		 4021 switch (pipe) {
4022 case 0:
4023 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4024 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4025 break;
4026 case 1:
4027 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4028 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4029 break;
4030 default:
9db4a9c7 4031 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 4032 break;
4033 }
79e53945
JB		 4034}
4035
976f8a20
DV		 4036/**
4037 * Sets the power management mode of the pipe and plane.
4038 */
4039void intel_crtc_update_dpms(struct drm_crtc *crtc)
4040{
4041 struct drm_device *dev = crtc->dev;
4042 struct drm_i915_private *dev_priv = dev->dev_private;
4043 struct intel_encoder *intel_encoder;
4044 bool enable = false;
4045
4046 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4047 enable |= intel_encoder->connectors_active;
4048
4049 if (enable)
4050 dev_priv->display.crtc_enable(crtc);
4051 else
4052 dev_priv->display.crtc_disable(crtc);
4053
4054 intel_crtc_update_sarea(crtc, enable);
4055}
4056
cdd59983
CW		 4057static void intel_crtc_disable(struct drm_crtc *crtc)
4058{
cdd59983 4059 struct drm_device *dev = crtc->dev;
976f8a20 4060 struct drm_connector *connector;
ee7b9f93 4061 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 4062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 4063
976f8a20
DV		 4064 /* crtc should still be enabled when we disable it. */
4065 WARN_ON(!crtc->enabled);
4066
4067 dev_priv->display.crtc_disable(crtc);
c77bf565 4068 intel_crtc->eld_vld = false;
976f8a20 4069 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 4070 dev_priv->display.off(crtc);
4071
931872fc 4072 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
93ce0ba6 4073 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
931872fc 4074 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 4075
4076 if (crtc->fb) {
4077 mutex_lock(&dev->struct_mutex);
1690e1eb 4078 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 4079 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 4080 crtc->fb = NULL;
4081 }
4082
4083 /* Update computed state. */
4084 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4085 if (!connector->encoder || !connector->encoder->crtc)
4086 continue;
4087
4088 if (connector->encoder->crtc != crtc)
4089 continue;
4090
4091 connector->dpms = DRM_MODE_DPMS_OFF;
4092 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 4093 }
4094}
4095
ea5b213a 4096void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 4097{
4ef69c7a 4098 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 4099
ea5b213a
CW		 4100 drm_encoder_cleanup(encoder);
4101 kfree(intel_encoder);
7e7d76c3
JB		 4102}
4103
9237329d 4104/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 4105 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4106 * state of the entire output pipe. */
9237329d 4107static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 4108{
5ab432ef
DV		 4109 if (mode == DRM_MODE_DPMS_ON) {
4110 encoder->connectors_active = true;
4111
b2cabb0e 4112 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 4113 } else {
4114 encoder->connectors_active = false;
4115
b2cabb0e 4116 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 4117 }
79e53945
JB		 4118}
4119
0a91ca29
DV		 4120/* Cross check the actual hw state with our own modeset state tracking (and it's
4121 * internal consistency). */
b980514c 4122static void intel_connector_check_state(struct intel_connector *connector)
79e53945 4123{
0a91ca29
DV		 4124 if (connector->get_hw_state(connector)) {
4125 struct intel_encoder *encoder = connector->encoder;
4126 struct drm_crtc *crtc;
4127 bool encoder_enabled;
4128 enum pipe pipe;
4129
4130 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4131 connector->base.base.id,
4132 drm_get_connector_name(&connector->base));
4133
4134 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4135 "wrong connector dpms state\n");
4136 WARN(connector->base.encoder != &encoder->base,
4137 "active connector not linked to encoder\n");
4138 WARN(!encoder->connectors_active,
4139 "encoder->connectors_active not set\n");
4140
4141 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4142 WARN(!encoder_enabled, "encoder not enabled\n");
4143 if (WARN_ON(!encoder->base.crtc))
4144 return;
4145
4146 crtc = encoder->base.crtc;
4147
4148 WARN(!crtc->enabled, "crtc not enabled\n");
4149 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4150 WARN(pipe != to_intel_crtc(crtc)->pipe,
4151 "encoder active on the wrong pipe\n");
4152 }
79e53945
JB		 4153}
4154
5ab432ef
DV		 4155/* Even simpler default implementation, if there's really no special case to
4156 * consider. */
4157void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 4158{
5ab432ef 4159 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 4160
5ab432ef
DV		 4161 /* All the simple cases only support two dpms states. */
4162 if (mode != DRM_MODE_DPMS_ON)
4163 mode = DRM_MODE_DPMS_OFF;
d4270e57 4164
5ab432ef
DV		 4165 if (mode == connector->dpms)
4166 return;
4167
4168 connector->dpms = mode;
4169
4170 /* Only need to change hw state when actually enabled */
4171 if (encoder->base.crtc)
4172 intel_encoder_dpms(encoder, mode);
4173 else
8af6cf88 4174 WARN_ON(encoder->connectors_active != false);
0a91ca29 4175
b980514c 4176 intel_modeset_check_state(connector->dev);
79e53945
JB		 4177}
4178
f0947c37
DV		 4179/* Simple connector->get_hw_state implementation for encoders that support only
4180 * one connector and no cloning and hence the encoder state determines the state
4181 * of the connector. */
4182bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4183{
24929352 4184 enum pipe pipe = 0;
f0947c37 4185 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4186
f0947c37 4187 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4188}
4189
1857e1da
DV		 4190static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4191 struct intel_crtc_config *pipe_config)
4192{
4193 struct drm_i915_private *dev_priv = dev->dev_private;
4194 struct intel_crtc *pipe_B_crtc =
4195 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4196
4197 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4198 pipe_name(pipe), pipe_config->fdi_lanes);
4199 if (pipe_config->fdi_lanes > 4) {
4200 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4201 pipe_name(pipe), pipe_config->fdi_lanes);
4202 return false;
4203 }
4204
4205 if (IS_HASWELL(dev)) {
4206 if (pipe_config->fdi_lanes > 2) {
4207 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4208 pipe_config->fdi_lanes);
4209 return false;
4210 } else {
4211 return true;
4212 }
4213 }
4214
4215 if (INTEL_INFO(dev)->num_pipes == 2)
4216 return true;
4217
4218 /* Ivybridge 3 pipe is really complicated */
4219 switch (pipe) {
4220 case PIPE_A:
4221 return true;
4222 case PIPE_B:
4223 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4224 pipe_config->fdi_lanes > 2) {
4225 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4226 pipe_name(pipe), pipe_config->fdi_lanes);
4227 return false;
4228 }
4229 return true;
4230 case PIPE_C:
1e833f40 4231 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4232 pipe_B_crtc->config.fdi_lanes <= 2) {
4233 if (pipe_config->fdi_lanes > 2) {
4234 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4235 pipe_name(pipe), pipe_config->fdi_lanes);
4236 return false;
4237 }
4238 } else {
4239 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4240 return false;
4241 }
4242 return true;
4243 default:
4244 BUG();
4245 }
4246}
4247
e29c22c0
DV		 4248#define RETRY 1
4249static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4250 struct intel_crtc_config *pipe_config)
877d48d5 4251{
1857e1da 4252 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4253 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4254 int lane, link_bw, fdi_dotclock;
e29c22c0 4255 bool setup_ok, needs_recompute = false;
877d48d5 4256
e29c22c0 4257retry:
877d48d5
DV		 4258 /* FDI is a binary signal running at ~2.7GHz, encoding
4259 * each output octet as 10 bits. The actual frequency
4260 * is stored as a divider into a 100MHz clock, and the
4261 * mode pixel clock is stored in units of 1KHz.
4262 * Hence the bw of each lane in terms of the mode signal
4263 * is:
4264 */
4265 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4266
241bfc38 4267 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 4268
2bd89a07 4269 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4270 pipe_config->pipe_bpp);
4271
4272 pipe_config->fdi_lanes = lane;
4273
2bd89a07 4274 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4275 link_bw, &pipe_config->fdi_m_n);
1857e1da 4276
e29c22c0
DV		 4277 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4278 intel_crtc->pipe, pipe_config);
4279 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4280 pipe_config->pipe_bpp -= 2*3;
4281 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4282 pipe_config->pipe_bpp);
4283 needs_recompute = true;
4284 pipe_config->bw_constrained = true;
4285
4286 goto retry;
4287 }
4288
4289 if (needs_recompute)
4290 return RETRY;
4291
4292 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4293}
4294
42db64ef
PZ		 4295static void hsw_compute_ips_config(struct intel_crtc *crtc,
4296 struct intel_crtc_config *pipe_config)
4297{
3c4ca58c
PZ		 4298 pipe_config->ips_enabled = i915_enable_ips &&
4299 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4300 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4301}
4302
a43f6e0f 4303static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4304 struct intel_crtc_config *pipe_config)
79e53945 4305{
a43f6e0f 4306 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4307 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4308
ad3a4479 4309 /* FIXME should check pixel clock limits on all platforms */
cf532bb2
VS		 4310 if (INTEL_INFO(dev)->gen < 4) {
4311 struct drm_i915_private *dev_priv = dev->dev_private;
4312 int clock_limit =
4313 dev_priv->display.get_display_clock_speed(dev);
4314
4315 /*
4316 * Enable pixel doubling when the dot clock
4317 * is > 90% of the (display) core speed.
4318 *
b397c96b
VS		 4319 * GDG double wide on either pipe,
4320 * otherwise pipe A only.
cf532bb2 4321 */
b397c96b 4322 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 4323 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 4324 clock_limit *= 2;
cf532bb2 4325 pipe_config->double_wide = true;
ad3a4479
VS		 4326 }
4327
241bfc38 4328 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 4329 return -EINVAL;
2c07245f 4330 }
89749350 4331
1d1d0e27
VS		 4332 /*
4333 * Pipe horizontal size must be even in:
4334 * - DVO ganged mode
4335 * - LVDS dual channel mode
4336 * - Double wide pipe
4337 */
4338 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4339 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4340 pipe_config->pipe_src_w &= ~1;
4341
8693a824
DL		 4342 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4343 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4344 */
4345 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4346 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4347 return -EINVAL;
44f46b42 4348
bd080ee5 4349 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4350 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4351 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4352 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4353 * for lvds. */
4354 pipe_config->pipe_bpp = 8*3;
4355 }
4356
f5adf94e 4357 if (HAS_IPS(dev))
a43f6e0f
DV		 4358 hsw_compute_ips_config(crtc, pipe_config);
4359
4360 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4361 * clock survives for now. */
4362 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4363 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4364
877d48d5 4365 if (pipe_config->has_pch_encoder)
a43f6e0f 4366 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4367
e29c22c0 4368 return 0;
79e53945
JB		 4369}
4370
25eb05fc
JB		 4371static int valleyview_get_display_clock_speed(struct drm_device *dev)
4372{
4373 return 400000; /* FIXME */
4374}
4375
e70236a8
JB		 4376static int i945_get_display_clock_speed(struct drm_device *dev)
4377{
4378 return 400000;
4379}
79e53945 4380
e70236a8 4381static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4382{
e70236a8
JB		 4383 return 333000;
4384}
79e53945 4385
e70236a8
JB		 4386static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4387{
4388 return 200000;
4389}
79e53945 4390
257a7ffc
DV		 4391static int pnv_get_display_clock_speed(struct drm_device *dev)
4392{
4393 u16 gcfgc = 0;
4394
4395 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4396
4397 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4398 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4399 return 267000;
4400 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4401 return 333000;
4402 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4403 return 444000;
4404 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4405 return 200000;
4406 default:
4407 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4408 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4409 return 133000;
4410 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4411 return 167000;
4412 }
4413}
4414
e70236a8
JB		 4415static int i915gm_get_display_clock_speed(struct drm_device *dev)
4416{
4417 u16 gcfgc = 0;
79e53945 4418
e70236a8
JB		 4419 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4420
4421 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4422 return 133000;
4423 else {
4424 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4425 case GC_DISPLAY_CLOCK_333_MHZ:
4426 return 333000;
4427 default:
4428 case GC_DISPLAY_CLOCK_190_200_MHZ:
4429 return 190000;
79e53945 4430 }
e70236a8
JB		 4431 }
4432}
4433
4434static int i865_get_display_clock_speed(struct drm_device *dev)
4435{
4436 return 266000;
4437}
4438
4439static int i855_get_display_clock_speed(struct drm_device *dev)
4440{
4441 u16 hpllcc = 0;
4442 /* Assume that the hardware is in the high speed state. This
4443 * should be the default.
4444 */
4445 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4446 case GC_CLOCK_133_200:
4447 case GC_CLOCK_100_200:
4448 return 200000;
4449 case GC_CLOCK_166_250:
4450 return 250000;
4451 case GC_CLOCK_100_133:
79e53945 4452 return 133000;
e70236a8 4453 }
79e53945 4454
e70236a8
JB		 4455 /* Shouldn't happen */
4456 return 0;
4457}
79e53945 4458
e70236a8
JB		 4459static int i830_get_display_clock_speed(struct drm_device *dev)
4460{
4461 return 133000;
79e53945
JB		 4462}
4463
2c07245f 4464static void
a65851af 4465intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4466{
a65851af
VS		 4467 while (*num > DATA_LINK_M_N_MASK ||
4468 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4469 *num >>= 1;
4470 *den >>= 1;
4471 }
4472}
4473
a65851af
VS		 4474static void compute_m_n(unsigned int m, unsigned int n,
4475 uint32_t *ret_m, uint32_t *ret_n)
4476{
4477 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4478 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4479 intel_reduce_m_n_ratio(ret_m, ret_n);
4480}
4481
e69d0bc1
DV		 4482void
4483intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4484 int pixel_clock, int link_clock,
4485 struct intel_link_m_n *m_n)
2c07245f 4486{
e69d0bc1 4487 m_n->tu = 64;
a65851af
VS		 4488
4489 compute_m_n(bits_per_pixel * pixel_clock,
4490 link_clock * nlanes * 8,
4491 &m_n->gmch_m, &m_n->gmch_n);
4492
4493 compute_m_n(pixel_clock, link_clock,
4494 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4495}
4496
a7615030
CW		 4497static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4498{
72bbe58c
KP		 4499 if (i915_panel_use_ssc >= 0)
4500 return i915_panel_use_ssc != 0;
41aa3448 4501 return dev_priv->vbt.lvds_use_ssc
435793df 4502 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4503}
4504
c65d77d8
JB		 4505static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4506{
4507 struct drm_device *dev = crtc->dev;
4508 struct drm_i915_private *dev_priv = dev->dev_private;
4509 int refclk;
4510
a0c4da24 4511 if (IS_VALLEYVIEW(dev)) {
9a0ea498 4512 refclk = 100000;
a0c4da24 4513 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4514 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4515 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4516 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4517 refclk / 1000);
4518 } else if (!IS_GEN2(dev)) {
4519 refclk = 96000;
4520 } else {
4521 refclk = 48000;
4522 }
4523
4524 return refclk;
4525}
4526
7429e9d4 4527static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4528{
7df00d7a 4529 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4530}
f47709a9 4531
7429e9d4
DV		 4532static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4533{
4534 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4535}
4536
f47709a9 4537static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4538 intel_clock_t *reduced_clock)
4539{
f47709a9 4540 struct drm_device *dev = crtc->base.dev;
a7516a05 4541 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4542 int pipe = crtc->pipe;
a7516a05
JB		 4543 u32 fp, fp2 = 0;
4544
4545 if (IS_PINEVIEW(dev)) {
7429e9d4 4546 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4547 if (reduced_clock)
7429e9d4 4548 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4549 } else {
7429e9d4 4550 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4551 if (reduced_clock)
7429e9d4 4552 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4553 }
4554
4555 I915_WRITE(FP0(pipe), fp);
8bcc2795 4556 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4557
f47709a9
DV		 4558 crtc->lowfreq_avail = false;
4559 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4560 reduced_clock && i915_powersave) {
4561 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4562 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4563 crtc->lowfreq_avail = true;
a7516a05
JB		 4564 } else {
4565 I915_WRITE(FP1(pipe), fp);
8bcc2795 4566 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4567 }
4568}
4569
5e69f97f
CML		 4570static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4571 pipe)
89b667f8
JB		 4572{
4573 u32 reg_val;
4574
4575 /*
4576 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4577 * and set it to a reasonable value instead.
4578 */
5e69f97f 4579 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8
JB		 4580 reg_val &= 0xffffff00;
4581 reg_val |= 0x00000030;
5e69f97f 4582 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4583
5e69f97f 4584 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4585 reg_val &= 0x8cffffff;
4586 reg_val = 0x8c000000;
5e69f97f 4587 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8 4588
5e69f97f 4589 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8 4590 reg_val &= 0xffffff00;
5e69f97f 4591 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4592
5e69f97f 4593 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4594 reg_val &= 0x00ffffff;
4595 reg_val |= 0xb0000000;
5e69f97f 4596 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4597}
4598
b551842d
DV		 4599static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4600 struct intel_link_m_n *m_n)
4601{
4602 struct drm_device *dev = crtc->base.dev;
4603 struct drm_i915_private *dev_priv = dev->dev_private;
4604 int pipe = crtc->pipe;
4605
e3b95f1e
DV		 4606 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4607 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4608 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4609 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4610}
4611
4612static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4613 struct intel_link_m_n *m_n)
4614{
4615 struct drm_device *dev = crtc->base.dev;
4616 struct drm_i915_private *dev_priv = dev->dev_private;
4617 int pipe = crtc->pipe;
4618 enum transcoder transcoder = crtc->config.cpu_transcoder;
4619
4620 if (INTEL_INFO(dev)->gen >= 5) {
4621 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4622 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4623 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4624 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4625 } else {
e3b95f1e
DV		 4626 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4627 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4628 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4629 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4630 }
4631}
4632
03afc4a2
DV		 4633static void intel_dp_set_m_n(struct intel_crtc *crtc)
4634{
4635 if (crtc->config.has_pch_encoder)
4636 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4637 else
4638 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4639}
4640
f47709a9 4641static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4642{
f47709a9 4643 struct drm_device *dev = crtc->base.dev;
a0c4da24 4644 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4645 int pipe = crtc->pipe;
89b667f8 4646 u32 dpll, mdiv;
a0c4da24 4647 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4648 u32 coreclk, reg_val, dpll_md;
a0c4da24 4649
09153000
DV		 4650 mutex_lock(&dev_priv->dpio_lock);
4651
f47709a9
DV		 4652 bestn = crtc->config.dpll.n;
4653 bestm1 = crtc->config.dpll.m1;
4654 bestm2 = crtc->config.dpll.m2;
4655 bestp1 = crtc->config.dpll.p1;
4656 bestp2 = crtc->config.dpll.p2;
a0c4da24 4657
89b667f8
JB		 4658 /* See eDP HDMI DPIO driver vbios notes doc */
4659
4660 /* PLL B needs special handling */
4661 if (pipe)
5e69f97f 4662 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 4663
4664 /* Set up Tx target for periodic Rcomp update */
5e69f97f 4665 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4666
4667 /* Disable target IRef on PLL */
5e69f97f 4668 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
89b667f8 4669 reg_val &= 0x00ffffff;
5e69f97f 4670 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4671
4672 /* Disable fast lock */
5e69f97f 4673 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4674
4675 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4676 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4677 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4678 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4679 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4680
4681 /*
4682 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4683 * but we don't support that).
4684 * Note: don't use the DAC post divider as it seems unstable.
4685 */
4686 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5e69f97f 4687 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4688
a0c4da24 4689 mdiv |= DPIO_ENABLE_CALIBRATION;
5e69f97f 4690 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4691
89b667f8 4692 /* Set HBR and RBR LPF coefficients */
ff9a6750 4693 if (crtc->config.port_clock == 162000 ||
99750bd4 4694 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4695 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5e69f97f 4696 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
885b0120 4697 0x009f0003);
89b667f8 4698 else
5e69f97f 4699 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4700 0x00d0000f);
4701
4702 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4703 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4704 /* Use SSC source */
4705 if (!pipe)
5e69f97f 4706 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4707 0x0df40000);
4708 else
5e69f97f 4709 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4710 0x0df70000);
4711 } else { /* HDMI or VGA */
4712 /* Use bend source */
4713 if (!pipe)
5e69f97f 4714 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4715 0x0df70000);
4716 else
5e69f97f 4717 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4718 0x0df40000);
4719 }
a0c4da24 4720
5e69f97f 4721 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4722 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4723 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4724 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4725 coreclk |= 0x01000000;
5e69f97f 4726 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4727
5e69f97f 4728 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4729
89b667f8
JB		 4730 /* Enable DPIO clock input */
4731 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4732 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
f6071166
JB		 4733 /* We should never disable this, set it here for state tracking */
4734 if (pipe == PIPE_B)
89b667f8 4735 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24 4736 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4737 crtc->config.dpll_hw_state.dpll = dpll;
4738
ef1b460d
DV		 4739 dpll_md = (crtc->config.pixel_multiplier - 1)
4740 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4741 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4742
89b667f8
JB		 4743 if (crtc->config.has_dp_encoder)
4744 intel_dp_set_m_n(crtc);
09153000
DV		 4745
4746 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4747}
4748
f47709a9
DV		 4749static void i9xx_update_pll(struct intel_crtc *crtc,
4750 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4751 int num_connectors)
4752{
f47709a9 4753 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4754 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4755 u32 dpll;
4756 bool is_sdvo;
f47709a9 4757 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4758
f47709a9 4759 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4760
f47709a9
DV		 4761 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4762 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4763
4764 dpll = DPLL_VGA_MODE_DIS;
4765
f47709a9 4766 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4767 dpll |= DPLLB_MODE_LVDS;
4768 else
4769 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4770
ef1b460d 4771 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4772 dpll |= (crtc->config.pixel_multiplier - 1)
4773 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4774 }
198a037f
DV		 4775
4776 if (is_sdvo)
4a33e48d 4777 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4778
f47709a9 4779 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4780 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4781
4782 /* compute bitmask from p1 value */
4783 if (IS_PINEVIEW(dev))
4784 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4785 else {
4786 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4787 if (IS_G4X(dev) && reduced_clock)
4788 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4789 }
4790 switch (clock->p2) {
4791 case 5:
4792 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4793 break;
4794 case 7:
4795 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4796 break;
4797 case 10:
4798 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4799 break;
4800 case 14:
4801 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4802 break;
4803 }
4804 if (INTEL_INFO(dev)->gen >= 4)
4805 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4806
09ede541 4807 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4808 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4809 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4810 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4811 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4812 else
4813 dpll |= PLL_REF_INPUT_DREFCLK;
4814
4815 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4816 crtc->config.dpll_hw_state.dpll = dpll;
4817
eb1cbe48 4818 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4819 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4820 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4821 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4822 }
66e3d5c0
DV		 4823
4824 if (crtc->config.has_dp_encoder)
4825 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4826}
4827
f47709a9 4828static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4829 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4830 int num_connectors)
4831{
f47709a9 4832 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4833 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4834 u32 dpll;
f47709a9 4835 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4836
f47709a9 4837 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4838
eb1cbe48
DV		 4839 dpll = DPLL_VGA_MODE_DIS;
4840
f47709a9 4841 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4842 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4843 } else {
4844 if (clock->p1 == 2)
4845 dpll |= PLL_P1_DIVIDE_BY_TWO;
4846 else
4847 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4848 if (clock->p2 == 4)
4849 dpll |= PLL_P2_DIVIDE_BY_4;
4850 }
4851
4a33e48d
DV		 4852 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4853 dpll |= DPLL_DVO_2X_MODE;
4854
f47709a9 4855 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4856 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4857 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4858 else
4859 dpll |= PLL_REF_INPUT_DREFCLK;
4860
4861 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4862 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4863}
4864
8a654f3b 4865static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4866{
4867 struct drm_device *dev = intel_crtc->base.dev;
4868 struct drm_i915_private *dev_priv = dev->dev_private;
4869 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4870 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4871 struct drm_display_mode *adjusted_mode =
4872 &intel_crtc->config.adjusted_mode;
4d8a62ea
DV		 4873 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4874
4875 /* We need to be careful not to changed the adjusted mode, for otherwise
4876 * the hw state checker will get angry at the mismatch. */
4877 crtc_vtotal = adjusted_mode->crtc_vtotal;
4878 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4879
4880 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4881 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4882 crtc_vtotal -= 1;
4883 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4884 vsyncshift = adjusted_mode->crtc_hsync_start
4885 - adjusted_mode->crtc_htotal / 2;
4886 } else {
4887 vsyncshift = 0;
4888 }
4889
4890 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4891 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4892
fe2b8f9d 4893 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4894 (adjusted_mode->crtc_hdisplay - 1) |
4895 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4896 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4897 (adjusted_mode->crtc_hblank_start - 1) |
4898 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4899 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4900 (adjusted_mode->crtc_hsync_start - 1) |
4901 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4902
fe2b8f9d 4903 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4904 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4905 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4906 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4907 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4908 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4909 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4910 (adjusted_mode->crtc_vsync_start - 1) |
4911 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4912
b5e508d4
PZ		 4913 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4914 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4915 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4916 * bits. */
4917 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4918 (pipe == PIPE_B || pipe == PIPE_C))
4919 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4920
b0e77b9c
PZ		 4921 /* pipesrc controls the size that is scaled from, which should
4922 * always be the user's requested size.
4923 */
4924 I915_WRITE(PIPESRC(pipe),
37327abd
VS		 4925 ((intel_crtc->config.pipe_src_w - 1) << 16) |
4926 (intel_crtc->config.pipe_src_h - 1));
b0e77b9c
PZ		 4927}
4928
1bd1bd80
DV		 4929static void intel_get_pipe_timings(struct intel_crtc *crtc,
4930 struct intel_crtc_config *pipe_config)
4931{
4932 struct drm_device *dev = crtc->base.dev;
4933 struct drm_i915_private *dev_priv = dev->dev_private;
4934 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4935 uint32_t tmp;
4936
4937 tmp = I915_READ(HTOTAL(cpu_transcoder));
4938 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4939 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4940 tmp = I915_READ(HBLANK(cpu_transcoder));
4941 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4942 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4943 tmp = I915_READ(HSYNC(cpu_transcoder));
4944 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4945 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4946
4947 tmp = I915_READ(VTOTAL(cpu_transcoder));
4948 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4949 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4950 tmp = I915_READ(VBLANK(cpu_transcoder));
4951 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4952 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4953 tmp = I915_READ(VSYNC(cpu_transcoder));
4954 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4955 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4956
4957 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4958 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4959 pipe_config->adjusted_mode.crtc_vtotal += 1;
4960 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4961 }
4962
4963 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 4964 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4965 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4966
4967 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4968 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 4969}
4970
babea61d
JB		 4971static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4972 struct intel_crtc_config *pipe_config)
4973{
4974 struct drm_crtc *crtc = &intel_crtc->base;
4975
4976 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4977 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4978 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4979 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4980
4981 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4982 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4983 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4984 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4985
4986 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4987
241bfc38 4988 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
babea61d
JB		 4989 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4990}
4991
84b046f3
DV		 4992static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4993{
4994 struct drm_device *dev = intel_crtc->base.dev;
4995 struct drm_i915_private *dev_priv = dev->dev_private;
4996 uint32_t pipeconf;
4997
9f11a9e4 4998 pipeconf = 0;
84b046f3 4999
67c72a12
DV		 5000 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
5001 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
5002 pipeconf |= PIPECONF_ENABLE;
5003
cf532bb2
VS		 5004 if (intel_crtc->config.double_wide)
5005 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 5006
ff9ce46e
DV		 5007 /* only g4x and later have fancy bpc/dither controls */
5008 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 5009 /* Bspec claims that we can't use dithering for 30bpp pipes. */
5010 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5011 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 5012 PIPECONF_DITHER_TYPE_SP;
84b046f3 5013
ff9ce46e
DV		 5014 switch (intel_crtc->config.pipe_bpp) {
5015 case 18:
5016 pipeconf |= PIPECONF_6BPC;
5017 break;
5018 case 24:
5019 pipeconf |= PIPECONF_8BPC;
5020 break;
5021 case 30:
5022 pipeconf |= PIPECONF_10BPC;
5023 break;
5024 default:
5025 /* Case prevented by intel_choose_pipe_bpp_dither. */
5026 BUG();
84b046f3
DV		 5027 }
5028 }
5029
5030 if (HAS_PIPE_CXSR(dev)) {
5031 if (intel_crtc->lowfreq_avail) {
5032 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5033 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5034 } else {
5035 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 5036 }
5037 }
5038
84b046f3
DV		 5039 if (!IS_GEN2(dev) &&
5040 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5041 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5042 else
5043 pipeconf |= PIPECONF_PROGRESSIVE;
5044
9f11a9e4
DV		 5045 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5046 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 5047
84b046f3
DV		 5048 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5049 POSTING_READ(PIPECONF(intel_crtc->pipe));
5050}
5051
f564048e 5052static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5053 int x, int y,
94352cf9 5054 struct drm_framebuffer *fb)
79e53945
JB		 5055{
5056 struct drm_device *dev = crtc->dev;
5057 struct drm_i915_private *dev_priv = dev->dev_private;
5058 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5059 int pipe = intel_crtc->pipe;
80824003 5060 int plane = intel_crtc->plane;
c751ce4f 5061 int refclk, num_connectors = 0;
652c393a 5062 intel_clock_t clock, reduced_clock;
84b046f3 5063 u32 dspcntr;
a16af721 5064 bool ok, has_reduced_clock = false;
e9fd1c02 5065 bool is_lvds = false, is_dsi = false;
5eddb70b 5066 struct intel_encoder *encoder;
d4906093 5067 const intel_limit_t *limit;
5c3b82e2 5068 int ret;
79e53945 5069
6c2b7c12 5070 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 5071 switch (encoder->type) {
79e53945
JB		 5072 case INTEL_OUTPUT_LVDS:
5073 is_lvds = true;
5074 break;
e9fd1c02
JN		 5075 case INTEL_OUTPUT_DSI:
5076 is_dsi = true;
5077 break;
79e53945 5078 }
43565a06 5079
c751ce4f 5080 num_connectors++;
79e53945
JB		 5081 }
5082
f2335330
JN		 5083 if (is_dsi)
5084 goto skip_dpll;
5085
5086 if (!intel_crtc->config.clock_set) {
5087 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 5088
e9fd1c02
JN		 5089 /*
5090 * Returns a set of divisors for the desired target clock with
5091 * the given refclk, or FALSE. The returned values represent
5092 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5093 * 2) / p1 / p2.
5094 */
5095 limit = intel_limit(crtc, refclk);
5096 ok = dev_priv->display.find_dpll(limit, crtc,
5097 intel_crtc->config.port_clock,
5098 refclk, NULL, &clock);
f2335330 5099 if (!ok) {
e9fd1c02
JN		 5100 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5101 return -EINVAL;
5102 }
79e53945 5103
f2335330
JN		 5104 if (is_lvds && dev_priv->lvds_downclock_avail) {
5105 /*
5106 * Ensure we match the reduced clock's P to the target
5107 * clock. If the clocks don't match, we can't switch
5108 * the display clock by using the FP0/FP1. In such case
5109 * we will disable the LVDS downclock feature.
5110 */
5111 has_reduced_clock =
5112 dev_priv->display.find_dpll(limit, crtc,
5113 dev_priv->lvds_downclock,
5114 refclk, &clock,
5115 &reduced_clock);
5116 }
5117 /* Compat-code for transition, will disappear. */
f47709a9
DV		 5118 intel_crtc->config.dpll.n = clock.n;
5119 intel_crtc->config.dpll.m1 = clock.m1;
5120 intel_crtc->config.dpll.m2 = clock.m2;
5121 intel_crtc->config.dpll.p1 = clock.p1;
5122 intel_crtc->config.dpll.p2 = clock.p2;
5123 }
7026d4ac 5124
e9fd1c02 5125 if (IS_GEN2(dev)) {
8a654f3b 5126 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 5127 has_reduced_clock ? &reduced_clock : NULL,
5128 num_connectors);
e9fd1c02 5129 } else if (IS_VALLEYVIEW(dev)) {
f2335330 5130 vlv_update_pll(intel_crtc);
e9fd1c02 5131 } else {
f47709a9 5132 i9xx_update_pll(intel_crtc,
eb1cbe48 5133 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 5134 num_connectors);
e9fd1c02 5135 }
79e53945 5136
f2335330 5137skip_dpll:
79e53945
JB		 5138 /* Set up the display plane register */
5139 dspcntr = DISPPLANE_GAMMA_ENABLE;
5140
da6ecc5d
JB		 5141 if (!IS_VALLEYVIEW(dev)) {
5142 if (pipe == 0)
5143 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5144 else
5145 dspcntr |= DISPPLANE_SEL_PIPE_B;
5146 }
79e53945 5147
8a654f3b 5148 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 5149
5150 /* pipesrc and dspsize control the size that is scaled from,
5151 * which should always be the user's requested size.
79e53945 5152 */
929c77fb 5153 I915_WRITE(DSPSIZE(plane),
37327abd
VS		 5154 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5155 (intel_crtc->config.pipe_src_w - 1));
929c77fb 5156 I915_WRITE(DSPPOS(plane), 0);
2c07245f 5157
84b046f3
DV		 5158 i9xx_set_pipeconf(intel_crtc);
5159
f564048e
EA		 5160 I915_WRITE(DSPCNTR(plane), dspcntr);
5161 POSTING_READ(DSPCNTR(plane));
5162
94352cf9 5163 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e 5164
f564048e
EA		 5165 return ret;
5166}
5167
2fa2fe9a
DV		 5168static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5169 struct intel_crtc_config *pipe_config)
5170{
5171 struct drm_device *dev = crtc->base.dev;
5172 struct drm_i915_private *dev_priv = dev->dev_private;
5173 uint32_t tmp;
5174
5175 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 5176 if (!(tmp & PFIT_ENABLE))
5177 return;
2fa2fe9a 5178
06922821 5179 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 5180 if (INTEL_INFO(dev)->gen < 4) {
5181 if (crtc->pipe != PIPE_B)
5182 return;
2fa2fe9a
DV		 5183 } else {
5184 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5185 return;
5186 }
5187
06922821 5188 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 5189 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5190 if (INTEL_INFO(dev)->gen < 5)
5191 pipe_config->gmch_pfit.lvds_border_bits =
5192 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5193}
5194
acbec814
JB		 5195static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5196 struct intel_crtc_config *pipe_config)
5197{
5198 struct drm_device *dev = crtc->base.dev;
5199 struct drm_i915_private *dev_priv = dev->dev_private;
5200 int pipe = pipe_config->cpu_transcoder;
5201 intel_clock_t clock;
5202 u32 mdiv;
662c6ecb 5203 int refclk = 100000;
acbec814
JB		 5204
5205 mutex_lock(&dev_priv->dpio_lock);
5206 mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5207 mutex_unlock(&dev_priv->dpio_lock);
5208
5209 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5210 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5211 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5212 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5213 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5214
f646628b 5215 vlv_clock(refclk, &clock);
acbec814 5216
f646628b
VS		 5217 /* clock.dot is the fast clock */
5218 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 5219}
5220
0e8ffe1b
DV		 5221static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5222 struct intel_crtc_config *pipe_config)
5223{
5224 struct drm_device *dev = crtc->base.dev;
5225 struct drm_i915_private *dev_priv = dev->dev_private;
5226 uint32_t tmp;
5227
e143a21c 5228 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5229 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5230
0e8ffe1b
DV		 5231 tmp = I915_READ(PIPECONF(crtc->pipe));
5232 if (!(tmp & PIPECONF_ENABLE))
5233 return false;
5234
42571aef
VS		 5235 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5236 switch (tmp & PIPECONF_BPC_MASK) {
5237 case PIPECONF_6BPC:
5238 pipe_config->pipe_bpp = 18;
5239 break;
5240 case PIPECONF_8BPC:
5241 pipe_config->pipe_bpp = 24;
5242 break;
5243 case PIPECONF_10BPC:
5244 pipe_config->pipe_bpp = 30;
5245 break;
5246 default:
5247 break;
5248 }
5249 }
5250
282740f7
VS		 5251 if (INTEL_INFO(dev)->gen < 4)
5252 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5253
1bd1bd80
DV		 5254 intel_get_pipe_timings(crtc, pipe_config);
5255
2fa2fe9a
DV		 5256 i9xx_get_pfit_config(crtc, pipe_config);
5257
6c49f241
DV		 5258 if (INTEL_INFO(dev)->gen >= 4) {
5259 tmp = I915_READ(DPLL_MD(crtc->pipe));
5260 pipe_config->pixel_multiplier =
5261 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5262 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5263 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5264 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5265 tmp = I915_READ(DPLL(crtc->pipe));
5266 pipe_config->pixel_multiplier =
5267 ((tmp & SDVO_MULTIPLIER_MASK)
5268 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5269 } else {
5270 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5271 * port and will be fixed up in the encoder->get_config
5272 * function. */
5273 pipe_config->pixel_multiplier = 1;
5274 }
8bcc2795
DV		 5275 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5276 if (!IS_VALLEYVIEW(dev)) {
5277 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5278 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5279 } else {
5280 /* Mask out read-only status bits. */
5281 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5282 DPLL_PORTC_READY_MASK |
5283 DPLL_PORTB_READY_MASK);
8bcc2795 5284 }
6c49f241 5285
acbec814
JB		 5286 if (IS_VALLEYVIEW(dev))
5287 vlv_crtc_clock_get(crtc, pipe_config);
5288 else
5289 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 5290
0e8ffe1b
DV		 5291 return true;
5292}
5293
dde86e2d 5294static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5295{
5296 struct drm_i915_private *dev_priv = dev->dev_private;
5297 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5298 struct intel_encoder *encoder;
74cfd7ac 5299 u32 val, final;
13d83a67 5300 bool has_lvds = false;
199e5d79 5301 bool has_cpu_edp = false;
199e5d79 5302 bool has_panel = false;
99eb6a01
KP		 5303 bool has_ck505 = false;
5304 bool can_ssc = false;
13d83a67
JB		 5305
5306 /* We need to take the global config into account */
199e5d79
KP		 5307 list_for_each_entry(encoder, &mode_config->encoder_list,
5308 base.head) {
5309 switch (encoder->type) {
5310 case INTEL_OUTPUT_LVDS:
5311 has_panel = true;
5312 has_lvds = true;
5313 break;
5314 case INTEL_OUTPUT_EDP:
5315 has_panel = true;
2de6905f 5316 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5317 has_cpu_edp = true;
5318 break;
13d83a67
JB		 5319 }
5320 }
5321
99eb6a01 5322 if (HAS_PCH_IBX(dev)) {
41aa3448 5323 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5324 can_ssc = has_ck505;
5325 } else {
5326 has_ck505 = false;
5327 can_ssc = true;
5328 }
5329
2de6905f
ID		 5330 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5331 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5332
5333 /* Ironlake: try to setup display ref clock before DPLL
5334 * enabling. This is only under driver's control after
5335 * PCH B stepping, previous chipset stepping should be
5336 * ignoring this setting.
5337 */
74cfd7ac
CW		 5338 val = I915_READ(PCH_DREF_CONTROL);
5339
5340 /* As we must carefully and slowly disable/enable each source in turn,
5341 * compute the final state we want first and check if we need to
5342 * make any changes at all.
5343 */
5344 final = val;
5345 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5346 if (has_ck505)
5347 final |= DREF_NONSPREAD_CK505_ENABLE;
5348 else
5349 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5350
5351 final &= ~DREF_SSC_SOURCE_MASK;
5352 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5353 final &= ~DREF_SSC1_ENABLE;
5354
5355 if (has_panel) {
5356 final |= DREF_SSC_SOURCE_ENABLE;
5357
5358 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5359 final |= DREF_SSC1_ENABLE;
5360
5361 if (has_cpu_edp) {
5362 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5363 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5364 else
5365 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5366 } else
5367 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5368 } else {
5369 final |= DREF_SSC_SOURCE_DISABLE;
5370 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5371 }
5372
5373 if (final == val)
5374 return;
5375
13d83a67 5376 /* Always enable nonspread source */
74cfd7ac 5377 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5378
99eb6a01 5379 if (has_ck505)
74cfd7ac 5380 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5381 else
74cfd7ac 5382 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5383
199e5d79 5384 if (has_panel) {
74cfd7ac
CW		 5385 val &= ~DREF_SSC_SOURCE_MASK;
5386 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5387
199e5d79 5388 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5389 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5390 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5391 val |= DREF_SSC1_ENABLE;
e77166b5 5392 } else
74cfd7ac 5393 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5394
5395 /* Get SSC going before enabling the outputs */
74cfd7ac 5396 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5397 POSTING_READ(PCH_DREF_CONTROL);
5398 udelay(200);
5399
74cfd7ac 5400 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5401
5402 /* Enable CPU source on CPU attached eDP */
199e5d79 5403 if (has_cpu_edp) {
99eb6a01 5404 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5405 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5406 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5407 }
13d83a67 5408 else
74cfd7ac 5409 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5410 } else
74cfd7ac 5411 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5412
74cfd7ac 5413 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5414 POSTING_READ(PCH_DREF_CONTROL);
5415 udelay(200);
5416 } else {
5417 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5418
74cfd7ac 5419 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5420
5421 /* Turn off CPU output */
74cfd7ac 5422 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5423
74cfd7ac 5424 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5425 POSTING_READ(PCH_DREF_CONTROL);
5426 udelay(200);
5427
5428 /* Turn off the SSC source */
74cfd7ac
CW		 5429 val &= ~DREF_SSC_SOURCE_MASK;
5430 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5431
5432 /* Turn off SSC1 */
74cfd7ac 5433 val &= ~DREF_SSC1_ENABLE;
199e5d79 5434
74cfd7ac 5435 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5436 POSTING_READ(PCH_DREF_CONTROL);
5437 udelay(200);
5438 }
74cfd7ac
CW		 5439
5440 BUG_ON(val != final);
13d83a67
JB		 5441}
5442
f31f2d55 5443static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5444{
f31f2d55 5445 uint32_t tmp;
dde86e2d 5446
0ff066a9
PZ		 5447 tmp = I915_READ(SOUTH_CHICKEN2);
5448 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5449 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5450
0ff066a9
PZ		 5451 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5452 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5453 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5454
0ff066a9
PZ		 5455 tmp = I915_READ(SOUTH_CHICKEN2);
5456 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5457 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5458
0ff066a9
PZ		 5459 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5460 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5461 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5462}
5463
5464/* WaMPhyProgramming:hsw */
5465static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5466{
5467 uint32_t tmp;
dde86e2d
PZ		 5468
5469 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5470 tmp &= ~(0xFF << 24);
5471 tmp |= (0x12 << 24);
5472 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5473
dde86e2d
PZ		 5474 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5475 tmp |= (1 << 11);
5476 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5477
5478 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5479 tmp |= (1 << 11);
5480 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5481
dde86e2d
PZ		 5482 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5483 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5484 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5485
5486 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5487 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5488 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5489
0ff066a9
PZ		 5490 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5491 tmp &= ~(7 << 13);
5492 tmp |= (5 << 13);
5493 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5494
0ff066a9
PZ		 5495 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5496 tmp &= ~(7 << 13);
5497 tmp |= (5 << 13);
5498 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5499
5500 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5501 tmp &= ~0xFF;
5502 tmp |= 0x1C;
5503 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5504
5505 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5506 tmp &= ~0xFF;
5507 tmp |= 0x1C;
5508 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5509
5510 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5511 tmp &= ~(0xFF << 16);
5512 tmp |= (0x1C << 16);
5513 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5514
5515 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5516 tmp &= ~(0xFF << 16);
5517 tmp |= (0x1C << 16);
5518 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5519
0ff066a9
PZ		 5520 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5521 tmp |= (1 << 27);
5522 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5523
0ff066a9
PZ		 5524 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5525 tmp |= (1 << 27);
5526 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5527
0ff066a9
PZ		 5528 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5529 tmp &= ~(0xF << 28);
5530 tmp |= (4 << 28);
5531 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5532
0ff066a9
PZ		 5533 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5534 tmp &= ~(0xF << 28);
5535 tmp |= (4 << 28);
5536 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5537}
5538
2fa86a1f
PZ		 5539/* Implements 3 different sequences from BSpec chapter "Display iCLK
5540 * Programming" based on the parameters passed:
5541 * - Sequence to enable CLKOUT_DP
5542 * - Sequence to enable CLKOUT_DP without spread
5543 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5544 */
5545static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5546 bool with_fdi)
f31f2d55
PZ		 5547{
5548 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5549 uint32_t reg, tmp;
5550
5551 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5552 with_spread = true;
5553 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5554 with_fdi, "LP PCH doesn't have FDI\n"))
5555 with_fdi = false;
f31f2d55
PZ		 5556
5557 mutex_lock(&dev_priv->dpio_lock);
5558
5559 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5560 tmp &= ~SBI_SSCCTL_DISABLE;
5561 tmp |= SBI_SSCCTL_PATHALT;
5562 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5563
5564 udelay(24);
5565
2fa86a1f
PZ		 5566 if (with_spread) {
5567 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5568 tmp &= ~SBI_SSCCTL_PATHALT;
5569 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5570
2fa86a1f
PZ		 5571 if (with_fdi) {
5572 lpt_reset_fdi_mphy(dev_priv);
5573 lpt_program_fdi_mphy(dev_priv);
5574 }
5575 }
dde86e2d 5576
2fa86a1f
PZ		 5577 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5578 SBI_GEN0 : SBI_DBUFF0;
5579 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5580 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5581 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5582
5583 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5584}
5585
47701c3b
PZ		 5586/* Sequence to disable CLKOUT_DP */
5587static void lpt_disable_clkout_dp(struct drm_device *dev)
5588{
5589 struct drm_i915_private *dev_priv = dev->dev_private;
5590 uint32_t reg, tmp;
5591
5592 mutex_lock(&dev_priv->dpio_lock);
5593
5594 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5595 SBI_GEN0 : SBI_DBUFF0;
5596 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5597 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5598 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5599
5600 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5601 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5602 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5603 tmp |= SBI_SSCCTL_PATHALT;
5604 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5605 udelay(32);
5606 }
5607 tmp |= SBI_SSCCTL_DISABLE;
5608 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5609 }
5610
5611 mutex_unlock(&dev_priv->dpio_lock);
5612}
5613
bf8fa3d3
PZ		 5614static void lpt_init_pch_refclk(struct drm_device *dev)
5615{
5616 struct drm_mode_config *mode_config = &dev->mode_config;
5617 struct intel_encoder *encoder;
5618 bool has_vga = false;
5619
5620 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5621 switch (encoder->type) {
5622 case INTEL_OUTPUT_ANALOG:
5623 has_vga = true;
5624 break;
5625 }
5626 }
5627
47701c3b
PZ		 5628 if (has_vga)
5629 lpt_enable_clkout_dp(dev, true, true);
5630 else
5631 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5632}
5633
dde86e2d
PZ		 5634/*
5635 * Initialize reference clocks when the driver loads
5636 */
5637void intel_init_pch_refclk(struct drm_device *dev)
5638{
5639 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5640 ironlake_init_pch_refclk(dev);
5641 else if (HAS_PCH_LPT(dev))
5642 lpt_init_pch_refclk(dev);
5643}
5644
d9d444cb
JB		 5645static int ironlake_get_refclk(struct drm_crtc *crtc)
5646{
5647 struct drm_device *dev = crtc->dev;
5648 struct drm_i915_private *dev_priv = dev->dev_private;
5649 struct intel_encoder *encoder;
d9d444cb
JB		 5650 int num_connectors = 0;
5651 bool is_lvds = false;
5652
6c2b7c12 5653 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5654 switch (encoder->type) {
5655 case INTEL_OUTPUT_LVDS:
5656 is_lvds = true;
5657 break;
d9d444cb
JB		 5658 }
5659 num_connectors++;
5660 }
5661
5662 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5663 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5664 dev_priv->vbt.lvds_ssc_freq);
5665 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5666 }
5667
5668 return 120000;
5669}
5670
6ff93609 5671static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5672{
c8203565 5673 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5675 int pipe = intel_crtc->pipe;
c8203565
PZ		 5676 uint32_t val;
5677
78114071 5678 val = 0;
c8203565 5679
965e0c48 5680 switch (intel_crtc->config.pipe_bpp) {
c8203565 5681 case 18:
dfd07d72 5682 val |= PIPECONF_6BPC;
c8203565
PZ		 5683 break;
5684 case 24:
dfd07d72 5685 val |= PIPECONF_8BPC;
c8203565
PZ		 5686 break;
5687 case 30:
dfd07d72 5688 val |= PIPECONF_10BPC;
c8203565
PZ		 5689 break;
5690 case 36:
dfd07d72 5691 val |= PIPECONF_12BPC;
c8203565
PZ		 5692 break;
5693 default:
cc769b62
PZ		 5694 /* Case prevented by intel_choose_pipe_bpp_dither. */
5695 BUG();
c8203565
PZ		 5696 }
5697
d8b32247 5698 if (intel_crtc->config.dither)
c8203565
PZ		 5699 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5700
6ff93609 5701 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5702 val |= PIPECONF_INTERLACED_ILK;
5703 else
5704 val |= PIPECONF_PROGRESSIVE;
5705
50f3b016 5706 if (intel_crtc->config.limited_color_range)
3685a8f3 5707 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5708
c8203565
PZ		 5709 I915_WRITE(PIPECONF(pipe), val);
5710 POSTING_READ(PIPECONF(pipe));
5711}
5712
86d3efce
VS		 5713/*
5714 * Set up the pipe CSC unit.
5715 *
5716 * Currently only full range RGB to limited range RGB conversion
5717 * is supported, but eventually this should handle various
5718 * RGB<->YCbCr scenarios as well.
5719 */
50f3b016 5720static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5721{
5722 struct drm_device *dev = crtc->dev;
5723 struct drm_i915_private *dev_priv = dev->dev_private;
5724 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5725 int pipe = intel_crtc->pipe;
5726 uint16_t coeff = 0x7800; /* 1.0 */
5727
5728 /*
5729 * TODO: Check what kind of values actually come out of the pipe
5730 * with these coeff/postoff values and adjust to get the best
5731 * accuracy. Perhaps we even need to take the bpc value into
5732 * consideration.
5733 */
5734
50f3b016 5735 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5736 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5737
5738 /*
5739 * GY/GU and RY/RU should be the other way around according
5740 * to BSpec, but reality doesn't agree. Just set them up in
5741 * a way that results in the correct picture.
5742 */
5743 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5744 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5745
5746 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5747 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5748
5749 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5750 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5751
5752 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5753 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5754 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5755
5756 if (INTEL_INFO(dev)->gen > 6) {
5757 uint16_t postoff = 0;
5758
50f3b016 5759 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5760 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5761
5762 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5763 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5764 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5765
5766 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5767 } else {
5768 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5769
50f3b016 5770 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5771 mode |= CSC_BLACK_SCREEN_OFFSET;
5772
5773 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5774 }
5775}
5776
6ff93609 5777static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5778{
5779 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5781 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5782 uint32_t val;
5783
3eff4faa 5784 val = 0;
ee2b0b38 5785
d8b32247 5786 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5787 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5788
6ff93609 5789 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5790 val |= PIPECONF_INTERLACED_ILK;
5791 else
5792 val |= PIPECONF_PROGRESSIVE;
5793
702e7a56
PZ		 5794 I915_WRITE(PIPECONF(cpu_transcoder), val);
5795 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5796
5797 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5798 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5799}
5800
6591c6e4 5801static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5802 intel_clock_t *clock,
5803 bool *has_reduced_clock,
5804 intel_clock_t *reduced_clock)
5805{
5806 struct drm_device *dev = crtc->dev;
5807 struct drm_i915_private *dev_priv = dev->dev_private;
5808 struct intel_encoder *intel_encoder;
5809 int refclk;
d4906093 5810 const intel_limit_t *limit;
a16af721 5811 bool ret, is_lvds = false;
79e53945 5812
6591c6e4
PZ		 5813 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5814 switch (intel_encoder->type) {
79e53945
JB		 5815 case INTEL_OUTPUT_LVDS:
5816 is_lvds = true;
5817 break;
79e53945
JB		 5818 }
5819 }
5820
d9d444cb 5821 refclk = ironlake_get_refclk(crtc);
79e53945 5822
d4906093
ML		 5823 /*
5824 * Returns a set of divisors for the desired target clock with the given
5825 * refclk, or FALSE. The returned values represent the clock equation:
5826 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5827 */
1b894b59 5828 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5829 ret = dev_priv->display.find_dpll(limit, crtc,
5830 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5831 refclk, NULL, clock);
6591c6e4
PZ		 5832 if (!ret)
5833 return false;
cda4b7d3 5834
ddc9003c 5835 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5836 /*
5837 * Ensure we match the reduced clock's P to the target clock.
5838 * If the clocks don't match, we can't switch the display clock
5839 * by using the FP0/FP1. In such case we will disable the LVDS
5840 * downclock feature.
5841 */
ee9300bb
DV		 5842 *has_reduced_clock =
5843 dev_priv->display.find_dpll(limit, crtc,
5844 dev_priv->lvds_downclock,
5845 refclk, clock,
5846 reduced_clock);
652c393a 5847 }
61e9653f 5848
6591c6e4
PZ		 5849 return true;
5850}
5851
01a415fd
DV		 5852static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5853{
5854 struct drm_i915_private *dev_priv = dev->dev_private;
5855 uint32_t temp;
5856
5857 temp = I915_READ(SOUTH_CHICKEN1);
5858 if (temp & FDI_BC_BIFURCATION_SELECT)
5859 return;
5860
5861 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5862 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5863
5864 temp |= FDI_BC_BIFURCATION_SELECT;
5865 DRM_DEBUG_KMS("enabling fdi C rx\n");
5866 I915_WRITE(SOUTH_CHICKEN1, temp);
5867 POSTING_READ(SOUTH_CHICKEN1);
5868}
5869
ebfd86fd 5870static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5871{
5872 struct drm_device *dev = intel_crtc->base.dev;
5873 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5874
5875 switch (intel_crtc->pipe) {
5876 case PIPE_A:
ebfd86fd 5877 break;
01a415fd 5878 case PIPE_B:
ebfd86fd 5879 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5880 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5881 else
5882 cpt_enable_fdi_bc_bifurcation(dev);
5883
ebfd86fd 5884 break;
01a415fd 5885 case PIPE_C:
01a415fd
DV		 5886 cpt_enable_fdi_bc_bifurcation(dev);
5887
ebfd86fd 5888 break;
01a415fd
DV		 5889 default:
5890 BUG();
5891 }
5892}
5893
d4b1931c
PZ		 5894int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5895{
5896 /*
5897 * Account for spread spectrum to avoid
5898 * oversubscribing the link. Max center spread
5899 * is 2.5%; use 5% for safety's sake.
5900 */
5901 u32 bps = target_clock * bpp * 21 / 20;
5902 return bps / (link_bw * 8) + 1;
5903}
5904
7429e9d4 5905static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5906{
7429e9d4 5907 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5908}
5909
de13a2e3 5910static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5911 u32 *fp,
9a7c7890 5912 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5913{
de13a2e3 5914 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5915 struct drm_device *dev = crtc->dev;
5916 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5917 struct intel_encoder *intel_encoder;
5918 uint32_t dpll;
6cc5f341 5919 int factor, num_connectors = 0;
09ede541 5920 bool is_lvds = false, is_sdvo = false;
79e53945 5921
de13a2e3
PZ		 5922 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5923 switch (intel_encoder->type) {
79e53945
JB		 5924 case INTEL_OUTPUT_LVDS:
5925 is_lvds = true;
5926 break;
5927 case INTEL_OUTPUT_SDVO:
7d57382e 5928 case INTEL_OUTPUT_HDMI:
79e53945 5929 is_sdvo = true;
79e53945 5930 break;
79e53945 5931 }
43565a06 5932
c751ce4f 5933 num_connectors++;
79e53945 5934 }
79e53945 5935
c1858123 5936 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5937 factor = 21;
5938 if (is_lvds) {
5939 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5940 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5941 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5942 factor = 25;
09ede541 5943 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5944 factor = 20;
c1858123 5945
7429e9d4 5946 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5947 *fp |= FP_CB_TUNE;
2c07245f 5948
9a7c7890
DV		 5949 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5950 *fp2 |= FP_CB_TUNE;
5951
5eddb70b 5952 dpll = 0;
2c07245f 5953
a07d6787
EA		 5954 if (is_lvds)
5955 dpll |= DPLLB_MODE_LVDS;
5956 else
5957 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5958
ef1b460d
DV		 5959 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5960 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5961
5962 if (is_sdvo)
4a33e48d 5963 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5964 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5965 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5966
a07d6787 5967 /* compute bitmask from p1 value */
7429e9d4 5968 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5969 /* also FPA1 */
7429e9d4 5970 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5971
7429e9d4 5972 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5973 case 5:
5974 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5975 break;
5976 case 7:
5977 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5978 break;
5979 case 10:
5980 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5981 break;
5982 case 14:
5983 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5984 break;
79e53945
JB		 5985 }
5986
b4c09f3b 5987 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5988 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5989 else
5990 dpll |= PLL_REF_INPUT_DREFCLK;
5991
959e16d6 5992 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5993}
5994
5995static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5996 int x, int y,
5997 struct drm_framebuffer *fb)
5998{
5999 struct drm_device *dev = crtc->dev;
6000 struct drm_i915_private *dev_priv = dev->dev_private;
6001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6002 int pipe = intel_crtc->pipe;
6003 int plane = intel_crtc->plane;
6004 int num_connectors = 0;
6005 intel_clock_t clock, reduced_clock;
cbbab5bd 6006 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 6007 bool ok, has_reduced_clock = false;
8b47047b 6008 bool is_lvds = false;
de13a2e3 6009 struct intel_encoder *encoder;
e2b78267 6010 struct intel_shared_dpll *pll;
de13a2e3 6011 int ret;
de13a2e3
PZ		 6012
6013 for_each_encoder_on_crtc(dev, crtc, encoder) {
6014 switch (encoder->type) {
6015 case INTEL_OUTPUT_LVDS:
6016 is_lvds = true;
6017 break;
de13a2e3
PZ		 6018 }
6019
6020 num_connectors++;
a07d6787 6021 }
79e53945 6022
5dc5298b
PZ		 6023 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6024 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 6025
ff9a6750 6026 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 6027 &has_reduced_clock, &reduced_clock);
ee9300bb 6028 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 6029 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6030 return -EINVAL;
79e53945 6031 }
f47709a9
DV		 6032 /* Compat-code for transition, will disappear. */
6033 if (!intel_crtc->config.clock_set) {
6034 intel_crtc->config.dpll.n = clock.n;
6035 intel_crtc->config.dpll.m1 = clock.m1;
6036 intel_crtc->config.dpll.m2 = clock.m2;
6037 intel_crtc->config.dpll.p1 = clock.p1;
6038 intel_crtc->config.dpll.p2 = clock.p2;
6039 }
79e53945 6040
5dc5298b 6041 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 6042 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 6043 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 6044 if (has_reduced_clock)
7429e9d4 6045 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 6046
7429e9d4 6047 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 6048 &fp, &reduced_clock,
6049 has_reduced_clock ? &fp2 : NULL);
6050
959e16d6 6051 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 6052 intel_crtc->config.dpll_hw_state.fp0 = fp;
6053 if (has_reduced_clock)
6054 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6055 else
6056 intel_crtc->config.dpll_hw_state.fp1 = fp;
6057
b89a1d39 6058 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 6059 if (pll == NULL) {
84f44ce7
VS		 6060 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6061 pipe_name(pipe));
4b645f14
JB		 6062 return -EINVAL;
6063 }
ee7b9f93 6064 } else
e72f9fbf 6065 intel_put_shared_dpll(intel_crtc);
79e53945 6066
03afc4a2
DV		 6067 if (intel_crtc->config.has_dp_encoder)
6068 intel_dp_set_m_n(intel_crtc);
79e53945 6069
bcd644e0
DV		 6070 if (is_lvds && has_reduced_clock && i915_powersave)
6071 intel_crtc->lowfreq_avail = true;
6072 else
6073 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 6074
6075 if (intel_crtc->config.has_pch_encoder) {
6076 pll = intel_crtc_to_shared_dpll(intel_crtc);
6077
652c393a
JB		 6078 }
6079
8a654f3b 6080 intel_set_pipe_timings(intel_crtc);
5eddb70b 6081
ca3a0ff8 6082 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6083 intel_cpu_transcoder_set_m_n(intel_crtc,
6084 &intel_crtc->config.fdi_m_n);
6085 }
2c07245f 6086
ebfd86fd
DV		 6087 if (IS_IVYBRIDGE(dev))
6088 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 6089
6ff93609 6090 ironlake_set_pipeconf(crtc);
79e53945 6091
a1f9e77e
PZ		 6092 /* Set up the display plane register */
6093 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 6094 POSTING_READ(DSPCNTR(plane));
79e53945 6095
94352cf9 6096 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd 6097
1857e1da 6098 return ret;
79e53945
JB		 6099}
6100
eb14cb74
VS		 6101static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6102 struct intel_link_m_n *m_n)
6103{
6104 struct drm_device *dev = crtc->base.dev;
6105 struct drm_i915_private *dev_priv = dev->dev_private;
6106 enum pipe pipe = crtc->pipe;
6107
6108 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6109 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6110 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6111 & ~TU_SIZE_MASK;
6112 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6113 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6114 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6115}
6116
6117static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6118 enum transcoder transcoder,
6119 struct intel_link_m_n *m_n)
72419203
DV		 6120{
6121 struct drm_device *dev = crtc->base.dev;
6122 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 6123 enum pipe pipe = crtc->pipe;
72419203 6124
eb14cb74
VS		 6125 if (INTEL_INFO(dev)->gen >= 5) {
6126 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6127 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6128 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6129 & ~TU_SIZE_MASK;
6130 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6131 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6132 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6133 } else {
6134 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6135 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6136 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6137 & ~TU_SIZE_MASK;
6138 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6139 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6140 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6141 }
6142}
6143
6144void intel_dp_get_m_n(struct intel_crtc *crtc,
6145 struct intel_crtc_config *pipe_config)
6146{
6147 if (crtc->config.has_pch_encoder)
6148 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6149 else
6150 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6151 &pipe_config->dp_m_n);
6152}
72419203 6153
eb14cb74
VS		 6154static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6155 struct intel_crtc_config *pipe_config)
6156{
6157 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6158 &pipe_config->fdi_m_n);
72419203
DV		 6159}
6160
2fa2fe9a
DV		 6161static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6162 struct intel_crtc_config *pipe_config)
6163{
6164 struct drm_device *dev = crtc->base.dev;
6165 struct drm_i915_private *dev_priv = dev->dev_private;
6166 uint32_t tmp;
6167
6168 tmp = I915_READ(PF_CTL(crtc->pipe));
6169
6170 if (tmp & PF_ENABLE) {
fd4daa9c 6171 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 6172 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6173 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 6174
6175 /* We currently do not free assignements of panel fitters on
6176 * ivb/hsw (since we don't use the higher upscaling modes which
6177 * differentiates them) so just WARN about this case for now. */
6178 if (IS_GEN7(dev)) {
6179 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6180 PF_PIPE_SEL_IVB(crtc->pipe));
6181 }
2fa2fe9a 6182 }
79e53945
JB		 6183}
6184
0e8ffe1b
DV		 6185static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6186 struct intel_crtc_config *pipe_config)
6187{
6188 struct drm_device *dev = crtc->base.dev;
6189 struct drm_i915_private *dev_priv = dev->dev_private;
6190 uint32_t tmp;
6191
e143a21c 6192 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 6193 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 6194
0e8ffe1b
DV		 6195 tmp = I915_READ(PIPECONF(crtc->pipe));
6196 if (!(tmp & PIPECONF_ENABLE))
6197 return false;
6198
42571aef
VS		 6199 switch (tmp & PIPECONF_BPC_MASK) {
6200 case PIPECONF_6BPC:
6201 pipe_config->pipe_bpp = 18;
6202 break;
6203 case PIPECONF_8BPC:
6204 pipe_config->pipe_bpp = 24;
6205 break;
6206 case PIPECONF_10BPC:
6207 pipe_config->pipe_bpp = 30;
6208 break;
6209 case PIPECONF_12BPC:
6210 pipe_config->pipe_bpp = 36;
6211 break;
6212 default:
6213 break;
6214 }
6215
ab9412ba 6216 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 6217 struct intel_shared_dpll *pll;
6218
88adfff1
DV		 6219 pipe_config->has_pch_encoder = true;
6220
627eb5a3
DV		 6221 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6222 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6223 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6224
6225 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 6226
c0d43d62 6227 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 6228 pipe_config->shared_dpll =
6229 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 6230 } else {
6231 tmp = I915_READ(PCH_DPLL_SEL);
6232 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6233 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6234 else
6235 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6236 }
66e985c0
DV		 6237
6238 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6239
6240 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6241 &pipe_config->dpll_hw_state));
c93f54cf
DV		 6242
6243 tmp = pipe_config->dpll_hw_state.dpll;
6244 pipe_config->pixel_multiplier =
6245 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6246 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 6247
6248 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 6249 } else {
6250 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 6251 }
6252
1bd1bd80
DV		 6253 intel_get_pipe_timings(crtc, pipe_config);
6254
2fa2fe9a
DV		 6255 ironlake_get_pfit_config(crtc, pipe_config);
6256
0e8ffe1b
DV		 6257 return true;
6258}
6259
be256dc7
PZ		 6260static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6261{
6262 struct drm_device *dev = dev_priv->dev;
6263 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6264 struct intel_crtc *crtc;
6265 unsigned long irqflags;
bd633a7c 6266 uint32_t val;
be256dc7
PZ		 6267
6268 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6269 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6270 pipe_name(crtc->pipe));
6271
6272 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6273 WARN(plls->spll_refcount, "SPLL enabled\n");
6274 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6275 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6276 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6277 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6278 "CPU PWM1 enabled\n");
6279 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6280 "CPU PWM2 enabled\n");
6281 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6282 "PCH PWM1 enabled\n");
6283 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6284 "Utility pin enabled\n");
6285 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6286
6287 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6288 val = I915_READ(DEIMR);
6289 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6290 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6291 val = I915_READ(SDEIMR);
bd633a7c 6292 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 6293 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6294 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6295}
6296
6297/*
6298 * This function implements pieces of two sequences from BSpec:
6299 * - Sequence for display software to disable LCPLL
6300 * - Sequence for display software to allow package C8+
6301 * The steps implemented here are just the steps that actually touch the LCPLL
6302 * register. Callers should take care of disabling all the display engine
6303 * functions, doing the mode unset, fixing interrupts, etc.
6304 */
6ff58d53
PZ		 6305static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6306 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 6307{
6308 uint32_t val;
6309
6310 assert_can_disable_lcpll(dev_priv);
6311
6312 val = I915_READ(LCPLL_CTL);
6313
6314 if (switch_to_fclk) {
6315 val |= LCPLL_CD_SOURCE_FCLK;
6316 I915_WRITE(LCPLL_CTL, val);
6317
6318 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6319 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6320 DRM_ERROR("Switching to FCLK failed\n");
6321
6322 val = I915_READ(LCPLL_CTL);
6323 }
6324
6325 val |= LCPLL_PLL_DISABLE;
6326 I915_WRITE(LCPLL_CTL, val);
6327 POSTING_READ(LCPLL_CTL);
6328
6329 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6330 DRM_ERROR("LCPLL still locked\n");
6331
6332 val = I915_READ(D_COMP);
6333 val |= D_COMP_COMP_DISABLE;
515b2392
PZ		 6334 mutex_lock(&dev_priv->rps.hw_lock);
6335 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6336 DRM_ERROR("Failed to disable D_COMP\n");
6337 mutex_unlock(&dev_priv->rps.hw_lock);
be256dc7
PZ		 6338 POSTING_READ(D_COMP);
6339 ndelay(100);
6340
6341 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6342 DRM_ERROR("D_COMP RCOMP still in progress\n");
6343
6344 if (allow_power_down) {
6345 val = I915_READ(LCPLL_CTL);
6346 val |= LCPLL_POWER_DOWN_ALLOW;
6347 I915_WRITE(LCPLL_CTL, val);
6348 POSTING_READ(LCPLL_CTL);
6349 }
6350}
6351
6352/*
6353 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6354 * source.
6355 */
6ff58d53 6356static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 6357{
6358 uint32_t val;
6359
6360 val = I915_READ(LCPLL_CTL);
6361
6362 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6363 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6364 return;
6365
215733fa
PZ		 6366 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6367 * we'll hang the machine! */
6368 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6369
be256dc7
PZ		 6370 if (val & LCPLL_POWER_DOWN_ALLOW) {
6371 val &= ~LCPLL_POWER_DOWN_ALLOW;
6372 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6373 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6374 }
6375
6376 val = I915_READ(D_COMP);
6377 val |= D_COMP_COMP_FORCE;
6378 val &= ~D_COMP_COMP_DISABLE;
515b2392
PZ		 6379 mutex_lock(&dev_priv->rps.hw_lock);
6380 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6381 DRM_ERROR("Failed to enable D_COMP\n");
6382 mutex_unlock(&dev_priv->rps.hw_lock);
35d8f2eb 6383 POSTING_READ(D_COMP);
be256dc7
PZ		 6384
6385 val = I915_READ(LCPLL_CTL);
6386 val &= ~LCPLL_PLL_DISABLE;
6387 I915_WRITE(LCPLL_CTL, val);
6388
6389 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6390 DRM_ERROR("LCPLL not locked yet\n");
6391
6392 if (val & LCPLL_CD_SOURCE_FCLK) {
6393 val = I915_READ(LCPLL_CTL);
6394 val &= ~LCPLL_CD_SOURCE_FCLK;
6395 I915_WRITE(LCPLL_CTL, val);
6396
6397 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6398 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6399 DRM_ERROR("Switching back to LCPLL failed\n");
6400 }
215733fa
PZ		 6401
6402 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6403}
6404
c67a470b
PZ		 6405void hsw_enable_pc8_work(struct work_struct *__work)
6406{
6407 struct drm_i915_private *dev_priv =
6408 container_of(to_delayed_work(__work), struct drm_i915_private,
6409 pc8.enable_work);
6410 struct drm_device *dev = dev_priv->dev;
6411 uint32_t val;
6412
6413 if (dev_priv->pc8.enabled)
6414 return;
6415
6416 DRM_DEBUG_KMS("Enabling package C8+\n");
6417
6418 dev_priv->pc8.enabled = true;
6419
6420 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6421 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6422 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6423 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6424 }
6425
6426 lpt_disable_clkout_dp(dev);
6427 hsw_pc8_disable_interrupts(dev);
6428 hsw_disable_lcpll(dev_priv, true, true);
6429}
6430
6431static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6432{
6433 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6434 WARN(dev_priv->pc8.disable_count < 1,
6435 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6436
6437 dev_priv->pc8.disable_count--;
6438 if (dev_priv->pc8.disable_count != 0)
6439 return;
6440
6441 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6442 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6443}
6444
6445static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6446{
6447 struct drm_device *dev = dev_priv->dev;
6448 uint32_t val;
6449
6450 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6451 WARN(dev_priv->pc8.disable_count < 0,
6452 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6453
6454 dev_priv->pc8.disable_count++;
6455 if (dev_priv->pc8.disable_count != 1)
6456 return;
6457
6458 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6459 if (!dev_priv->pc8.enabled)
6460 return;
6461
6462 DRM_DEBUG_KMS("Disabling package C8+\n");
6463
6464 hsw_restore_lcpll(dev_priv);
6465 hsw_pc8_restore_interrupts(dev);
6466 lpt_init_pch_refclk(dev);
6467
6468 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6469 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6470 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6471 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6472 }
6473
6474 intel_prepare_ddi(dev);
6475 i915_gem_init_swizzling(dev);
6476 mutex_lock(&dev_priv->rps.hw_lock);
6477 gen6_update_ring_freq(dev);
6478 mutex_unlock(&dev_priv->rps.hw_lock);
6479 dev_priv->pc8.enabled = false;
6480}
6481
6482void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6483{
6484 mutex_lock(&dev_priv->pc8.lock);
6485 __hsw_enable_package_c8(dev_priv);
6486 mutex_unlock(&dev_priv->pc8.lock);
6487}
6488
6489void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6490{
6491 mutex_lock(&dev_priv->pc8.lock);
6492 __hsw_disable_package_c8(dev_priv);
6493 mutex_unlock(&dev_priv->pc8.lock);
6494}
6495
6496static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6497{
6498 struct drm_device *dev = dev_priv->dev;
6499 struct intel_crtc *crtc;
6500 uint32_t val;
6501
6502 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6503 if (crtc->base.enabled)
6504 return false;
6505
6506 /* This case is still possible since we have the i915.disable_power_well
6507 * parameter and also the KVMr or something else might be requesting the
6508 * power well. */
6509 val = I915_READ(HSW_PWR_WELL_DRIVER);
6510 if (val != 0) {
6511 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6512 return false;
6513 }
6514
6515 return true;
6516}
6517
6518/* Since we're called from modeset_global_resources there's no way to
6519 * symmetrically increase and decrease the refcount, so we use
6520 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6521 * or not.
6522 */
6523static void hsw_update_package_c8(struct drm_device *dev)
6524{
6525 struct drm_i915_private *dev_priv = dev->dev_private;
6526 bool allow;
6527
6528 if (!i915_enable_pc8)
6529 return;
6530
6531 mutex_lock(&dev_priv->pc8.lock);
6532
6533 allow = hsw_can_enable_package_c8(dev_priv);
6534
6535 if (allow == dev_priv->pc8.requirements_met)
6536 goto done;
6537
6538 dev_priv->pc8.requirements_met = allow;
6539
6540 if (allow)
6541 __hsw_enable_package_c8(dev_priv);
6542 else
6543 __hsw_disable_package_c8(dev_priv);
6544
6545done:
6546 mutex_unlock(&dev_priv->pc8.lock);
6547}
6548
6549static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6550{
6551 if (!dev_priv->pc8.gpu_idle) {
6552 dev_priv->pc8.gpu_idle = true;
6553 hsw_enable_package_c8(dev_priv);
6554 }
6555}
6556
6557static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6558{
6559 if (dev_priv->pc8.gpu_idle) {
6560 dev_priv->pc8.gpu_idle = false;
6561 hsw_disable_package_c8(dev_priv);
6562 }
be256dc7
PZ		 6563}
6564
d6dd9eb1
DV		 6565static void haswell_modeset_global_resources(struct drm_device *dev)
6566{
d6dd9eb1
DV		 6567 bool enable = false;
6568 struct intel_crtc *crtc;
d6dd9eb1
DV		 6569
6570 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6571 if (!crtc->base.enabled)
6572 continue;
d6dd9eb1 6573
fd4daa9c 6574 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
e7a639c4 6575 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6576 enable = true;
6577 }
6578
d6dd9eb1 6579 intel_set_power_well(dev, enable);
c67a470b
PZ		 6580
6581 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6582}
6583
09b4ddf9 6584static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6585 int x, int y,
6586 struct drm_framebuffer *fb)
6587{
6588 struct drm_device *dev = crtc->dev;
6589 struct drm_i915_private *dev_priv = dev->dev_private;
6590 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6591 int plane = intel_crtc->plane;
09b4ddf9 6592 int ret;
09b4ddf9 6593
ff9a6750 6594 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6595 return -EINVAL;
6596
03afc4a2
DV		 6597 if (intel_crtc->config.has_dp_encoder)
6598 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6599
6600 intel_crtc->lowfreq_avail = false;
09b4ddf9 6601
8a654f3b 6602 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6603
ca3a0ff8 6604 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6605 intel_cpu_transcoder_set_m_n(intel_crtc,
6606 &intel_crtc->config.fdi_m_n);
6607 }
09b4ddf9 6608
6ff93609 6609 haswell_set_pipeconf(crtc);
09b4ddf9 6610
50f3b016 6611 intel_set_pipe_csc(crtc);
86d3efce 6612
09b4ddf9 6613 /* Set up the display plane register */
86d3efce 6614 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6615 POSTING_READ(DSPCNTR(plane));
6616
6617 ret = intel_pipe_set_base(crtc, x, y, fb);
6618
1f803ee5 6619 return ret;
79e53945
JB		 6620}
6621
0e8ffe1b
DV		 6622static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6623 struct intel_crtc_config *pipe_config)
6624{
6625 struct drm_device *dev = crtc->base.dev;
6626 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6627 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6628 uint32_t tmp;
6629
e143a21c 6630 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6631 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6632
eccb140b
DV		 6633 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6634 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6635 enum pipe trans_edp_pipe;
6636 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6637 default:
6638 WARN(1, "unknown pipe linked to edp transcoder\n");
6639 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6640 case TRANS_DDI_EDP_INPUT_A_ON:
6641 trans_edp_pipe = PIPE_A;
6642 break;
6643 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6644 trans_edp_pipe = PIPE_B;
6645 break;
6646 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6647 trans_edp_pipe = PIPE_C;
6648 break;
6649 }
6650
6651 if (trans_edp_pipe == crtc->pipe)
6652 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6653 }
6654
b97186f0 6655 if (!intel_display_power_enabled(dev,
eccb140b 6656 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6657 return false;
6658
eccb140b 6659 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6660 if (!(tmp & PIPECONF_ENABLE))
6661 return false;
6662
88adfff1 6663 /*
f196e6be 6664 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6665 * DDI E. So just check whether this pipe is wired to DDI E and whether
6666 * the PCH transcoder is on.
6667 */
eccb140b 6668 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6669 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6670 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6671 pipe_config->has_pch_encoder = true;
6672
627eb5a3
DV		 6673 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6674 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6675 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6676
6677 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6678 }
6679
1bd1bd80
DV		 6680 intel_get_pipe_timings(crtc, pipe_config);
6681
2fa2fe9a
DV		 6682 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6683 if (intel_display_power_enabled(dev, pfit_domain))
6684 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6685
42db64ef
PZ		 6686 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6687 (I915_READ(IPS_CTL) & IPS_ENABLE);
6688
6c49f241
DV		 6689 pipe_config->pixel_multiplier = 1;
6690
0e8ffe1b
DV		 6691 return true;
6692}
6693
f564048e 6694static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6695 int x, int y,
94352cf9 6696 struct drm_framebuffer *fb)
f564048e
EA		 6697{
6698 struct drm_device *dev = crtc->dev;
6699 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6700 struct intel_encoder *encoder;
0b701d27 6701 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6702 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6703 int pipe = intel_crtc->pipe;
f564048e
EA		 6704 int ret;
6705
0b701d27 6706 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6707
b8cecdf5
DV		 6708 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6709
79e53945 6710 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6711
9256aa19
DV		 6712 if (ret != 0)
6713 return ret;
6714
6715 for_each_encoder_on_crtc(dev, crtc, encoder) {
6716 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6717 encoder->base.base.id,
6718 drm_get_encoder_name(&encoder->base),
6719 mode->base.id, mode->name);
36f2d1f1 6720 encoder->mode_set(encoder);
9256aa19
DV		 6721 }
6722
6723 return 0;
79e53945
JB		 6724}
6725
3a9627f4
WF		 6726static bool intel_eld_uptodate(struct drm_connector *connector,
6727 int reg_eldv, uint32_t bits_eldv,
6728 int reg_elda, uint32_t bits_elda,
6729 int reg_edid)
6730{
6731 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6732 uint8_t *eld = connector->eld;
6733 uint32_t i;
6734
6735 i = I915_READ(reg_eldv);
6736 i &= bits_eldv;
6737
6738 if (!eld[0])
6739 return !i;
6740
6741 if (!i)
6742 return false;
6743
6744 i = I915_READ(reg_elda);
6745 i &= ~bits_elda;
6746 I915_WRITE(reg_elda, i);
6747
6748 for (i = 0; i < eld[2]; i++)
6749 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6750 return false;
6751
6752 return true;
6753}
6754
e0dac65e 6755static void g4x_write_eld(struct drm_connector *connector,
34427052
JN		 6756 struct drm_crtc *crtc,
6757 struct drm_display_mode *mode)
e0dac65e
WF		 6758{
6759 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6760 uint8_t *eld = connector->eld;
6761 uint32_t eldv;
6762 uint32_t len;
6763 uint32_t i;
6764
6765 i = I915_READ(G4X_AUD_VID_DID);
6766
6767 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6768 eldv = G4X_ELDV_DEVCL_DEVBLC;
6769 else
6770 eldv = G4X_ELDV_DEVCTG;
6771
3a9627f4
WF		 6772 if (intel_eld_uptodate(connector,
6773 G4X_AUD_CNTL_ST, eldv,
6774 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6775 G4X_HDMIW_HDMIEDID))
6776 return;
6777
e0dac65e
WF		 6778 i = I915_READ(G4X_AUD_CNTL_ST);
6779 i &= ~(eldv | G4X_ELD_ADDR);
6780 len = (i >> 9) & 0x1f; /* ELD buffer size */
6781 I915_WRITE(G4X_AUD_CNTL_ST, i);
6782
6783 if (!eld[0])
6784 return;
6785
6786 len = min_t(uint8_t, eld[2], len);
6787 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6788 for (i = 0; i < len; i++)
6789 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6790
6791 i = I915_READ(G4X_AUD_CNTL_ST);
6792 i |= eldv;
6793 I915_WRITE(G4X_AUD_CNTL_ST, i);
6794}
6795
83358c85 6796static void haswell_write_eld(struct drm_connector *connector,
34427052
JN		 6797 struct drm_crtc *crtc,
6798 struct drm_display_mode *mode)
83358c85
WX		 6799{
6800 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6801 uint8_t *eld = connector->eld;
6802 struct drm_device *dev = crtc->dev;
7b9f35a6 6803 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6804 uint32_t eldv;
6805 uint32_t i;
6806 int len;
6807 int pipe = to_intel_crtc(crtc)->pipe;
6808 int tmp;
6809
6810 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6811 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6812 int aud_config = HSW_AUD_CFG(pipe);
6813 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6814
6815
6816 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6817
6818 /* Audio output enable */
6819 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6820 tmp = I915_READ(aud_cntrl_st2);
6821 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6822 I915_WRITE(aud_cntrl_st2, tmp);
6823
6824 /* Wait for 1 vertical blank */
6825 intel_wait_for_vblank(dev, pipe);
6826
6827 /* Set ELD valid state */
6828 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6829 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
83358c85
WX		 6830 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6831 I915_WRITE(aud_cntrl_st2, tmp);
6832 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6833 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
83358c85
WX		 6834
6835 /* Enable HDMI mode */
6836 tmp = I915_READ(aud_config);
7e7cb34f 6837 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
83358c85
WX		 6838 /* clear N_programing_enable and N_value_index */
6839 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6840 I915_WRITE(aud_config, tmp);
6841
6842 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6843
6844 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6845 intel_crtc->eld_vld = true;
83358c85
WX		 6846
6847 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6848 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6849 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6850 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6851 } else
6852 I915_WRITE(aud_config, 0);
6853
6854 if (intel_eld_uptodate(connector,
6855 aud_cntrl_st2, eldv,
6856 aud_cntl_st, IBX_ELD_ADDRESS,
6857 hdmiw_hdmiedid))
6858 return;
6859
6860 i = I915_READ(aud_cntrl_st2);
6861 i &= ~eldv;
6862 I915_WRITE(aud_cntrl_st2, i);
6863
6864 if (!eld[0])
6865 return;
6866
6867 i = I915_READ(aud_cntl_st);
6868 i &= ~IBX_ELD_ADDRESS;
6869 I915_WRITE(aud_cntl_st, i);
6870 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6871 DRM_DEBUG_DRIVER("port num:%d\n", i);
6872
6873 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6874 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6875 for (i = 0; i < len; i++)
6876 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6877
6878 i = I915_READ(aud_cntrl_st2);
6879 i |= eldv;
6880 I915_WRITE(aud_cntrl_st2, i);
6881
6882}
6883
e0dac65e 6884static void ironlake_write_eld(struct drm_connector *connector,
34427052
JN		 6885 struct drm_crtc *crtc,
6886 struct drm_display_mode *mode)
e0dac65e
WF		 6887{
6888 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6889 uint8_t *eld = connector->eld;
6890 uint32_t eldv;
6891 uint32_t i;
6892 int len;
6893 int hdmiw_hdmiedid;
b6daa025 6894 int aud_config;
e0dac65e
WF		 6895 int aud_cntl_st;
6896 int aud_cntrl_st2;
9b138a83 6897 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6898
b3f33cbf 6899 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6900 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6901 aud_config = IBX_AUD_CFG(pipe);
6902 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6903 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6904 } else {
9b138a83
WX		 6905 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6906 aud_config = CPT_AUD_CFG(pipe);
6907 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6908 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6909 }
6910
9b138a83 6911 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6912
6913 i = I915_READ(aud_cntl_st);
9b138a83 6914 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6915 if (!i) {
6916 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6917 /* operate blindly on all ports */
1202b4c6
WF		 6918 eldv = IBX_ELD_VALIDB;
6919 eldv |= IBX_ELD_VALIDB << 4;
6920 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6921 } else {
2582a850 6922 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6923 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6924 }
6925
3a9627f4
WF		 6926 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6927 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6928 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6929 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6930 } else
6931 I915_WRITE(aud_config, 0);
e0dac65e 6932
3a9627f4
WF		 6933 if (intel_eld_uptodate(connector,
6934 aud_cntrl_st2, eldv,
6935 aud_cntl_st, IBX_ELD_ADDRESS,
6936 hdmiw_hdmiedid))
6937 return;
6938
e0dac65e
WF		 6939 i = I915_READ(aud_cntrl_st2);
6940 i &= ~eldv;
6941 I915_WRITE(aud_cntrl_st2, i);
6942
6943 if (!eld[0])
6944 return;
6945
e0dac65e 6946 i = I915_READ(aud_cntl_st);
1202b4c6 6947 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6948 I915_WRITE(aud_cntl_st, i);
6949
6950 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6951 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6952 for (i = 0; i < len; i++)
6953 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6954
6955 i = I915_READ(aud_cntrl_st2);
6956 i |= eldv;
6957 I915_WRITE(aud_cntrl_st2, i);
6958}
6959
6960void intel_write_eld(struct drm_encoder *encoder,
6961 struct drm_display_mode *mode)
6962{
6963 struct drm_crtc *crtc = encoder->crtc;
6964 struct drm_connector *connector;
6965 struct drm_device *dev = encoder->dev;
6966 struct drm_i915_private *dev_priv = dev->dev_private;
6967
6968 connector = drm_select_eld(encoder, mode);
6969 if (!connector)
6970 return;
6971
6972 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6973 connector->base.id,
6974 drm_get_connector_name(connector),
6975 connector->encoder->base.id,
6976 drm_get_encoder_name(connector->encoder));
6977
6978 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6979
6980 if (dev_priv->display.write_eld)
34427052 6981 dev_priv->display.write_eld(connector, crtc, mode);
e0dac65e
WF		 6982}
6983
560b85bb
CW		 6984static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6985{
6986 struct drm_device *dev = crtc->dev;
6987 struct drm_i915_private *dev_priv = dev->dev_private;
6988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6989 bool visible = base != 0;
6990 u32 cntl;
6991
6992 if (intel_crtc->cursor_visible == visible)
6993 return;
6994
9db4a9c7 6995 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6996 if (visible) {
6997 /* On these chipsets we can only modify the base whilst
6998 * the cursor is disabled.
6999 */
9db4a9c7 7000 I915_WRITE(_CURABASE, base);
560b85bb
CW		 7001
7002 cntl &= ~(CURSOR_FORMAT_MASK);
7003 /* XXX width must be 64, stride 256 => 0x00 << 28 */
7004 cntl |= CURSOR_ENABLE |
7005 CURSOR_GAMMA_ENABLE |
7006 CURSOR_FORMAT_ARGB;
7007 } else
7008 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 7009 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 7010
7011 intel_crtc->cursor_visible = visible;
7012}
7013
7014static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7015{
7016 struct drm_device *dev = crtc->dev;
7017 struct drm_i915_private *dev_priv = dev->dev_private;
7018 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7019 int pipe = intel_crtc->pipe;
7020 bool visible = base != 0;
7021
7022 if (intel_crtc->cursor_visible != visible) {
548f245b 7023 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 7024 if (base) {
7025 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7026 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7027 cntl |= pipe << 28; /* Connect to correct pipe */
7028 } else {
7029 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7030 cntl |= CURSOR_MODE_DISABLE;
7031 }
9db4a9c7 7032 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 7033
7034 intel_crtc->cursor_visible = visible;
7035 }
7036 /* and commit changes on next vblank */
9db4a9c7 7037 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 7038}
7039
65a21cd6
JB		 7040static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7041{
7042 struct drm_device *dev = crtc->dev;
7043 struct drm_i915_private *dev_priv = dev->dev_private;
7044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7045 int pipe = intel_crtc->pipe;
7046 bool visible = base != 0;
7047
7048 if (intel_crtc->cursor_visible != visible) {
7049 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7050 if (base) {
7051 cntl &= ~CURSOR_MODE;
7052 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7053 } else {
7054 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7055 cntl |= CURSOR_MODE_DISABLE;
7056 }
1f5d76db 7057 if (IS_HASWELL(dev)) {
86d3efce 7058 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 7059 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7060 }
65a21cd6
JB		 7061 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7062
7063 intel_crtc->cursor_visible = visible;
7064 }
7065 /* and commit changes on next vblank */
7066 I915_WRITE(CURBASE_IVB(pipe), base);
7067}
7068
cda4b7d3 7069/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 7070static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7071 bool on)
cda4b7d3
CW		 7072{
7073 struct drm_device *dev = crtc->dev;
7074 struct drm_i915_private *dev_priv = dev->dev_private;
7075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7076 int pipe = intel_crtc->pipe;
7077 int x = intel_crtc->cursor_x;
7078 int y = intel_crtc->cursor_y;
d6e4db15 7079 u32 base = 0, pos = 0;
cda4b7d3
CW		 7080 bool visible;
7081
d6e4db15 7082 if (on)
cda4b7d3 7083 base = intel_crtc->cursor_addr;
cda4b7d3 7084
d6e4db15
VS		 7085 if (x >= intel_crtc->config.pipe_src_w)
7086 base = 0;
7087
7088 if (y >= intel_crtc->config.pipe_src_h)
cda4b7d3
CW		 7089 base = 0;
7090
7091 if (x < 0) {
efc9064e 7092 if (x + intel_crtc->cursor_width <= 0)
cda4b7d3
CW		 7093 base = 0;
7094
7095 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7096 x = -x;
7097 }
7098 pos |= x << CURSOR_X_SHIFT;
7099
7100 if (y < 0) {
efc9064e 7101 if (y + intel_crtc->cursor_height <= 0)
cda4b7d3
CW		 7102 base = 0;
7103
7104 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7105 y = -y;
7106 }
7107 pos |= y << CURSOR_Y_SHIFT;
7108
7109 visible = base != 0;
560b85bb 7110 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 7111 return;
7112
0cd83aa9 7113 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 7114 I915_WRITE(CURPOS_IVB(pipe), pos);
7115 ivb_update_cursor(crtc, base);
7116 } else {
7117 I915_WRITE(CURPOS(pipe), pos);
7118 if (IS_845G(dev) || IS_I865G(dev))
7119 i845_update_cursor(crtc, base);
7120 else
7121 i9xx_update_cursor(crtc, base);
7122 }
cda4b7d3
CW		 7123}
7124
79e53945 7125static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 7126 struct drm_file *file,
79e53945
JB		 7127 uint32_t handle,
7128 uint32_t width, uint32_t height)
7129{
7130 struct drm_device *dev = crtc->dev;
7131 struct drm_i915_private *dev_priv = dev->dev_private;
7132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 7133 struct drm_i915_gem_object *obj;
cda4b7d3 7134 uint32_t addr;
3f8bc370 7135 int ret;
79e53945 7136
79e53945
JB		 7137 /* if we want to turn off the cursor ignore width and height */
7138 if (!handle) {
28c97730 7139 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 7140 addr = 0;
05394f39 7141 obj = NULL;
5004417d 7142 mutex_lock(&dev->struct_mutex);
3f8bc370 7143 goto finish;
79e53945
JB		 7144 }
7145
7146 /* Currently we only support 64x64 cursors */
7147 if (width != 64 || height != 64) {
7148 DRM_ERROR("we currently only support 64x64 cursors\n");
7149 return -EINVAL;
7150 }
7151
05394f39 7152 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 7153 if (&obj->base == NULL)
79e53945
JB		 7154 return -ENOENT;
7155
05394f39 7156 if (obj->base.size < width * height * 4) {
79e53945 7157 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 7158 ret = -ENOMEM;
7159 goto fail;
79e53945
JB		 7160 }
7161
71acb5eb 7162 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 7163 mutex_lock(&dev->struct_mutex);
b295d1b6 7164 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 7165 unsigned alignment;
7166
d9e86c0e
CW		 7167 if (obj->tiling_mode) {
7168 DRM_ERROR("cursor cannot be tiled\n");
7169 ret = -EINVAL;
7170 goto fail_locked;
7171 }
7172
693db184
CW		 7173 /* Note that the w/a also requires 2 PTE of padding following
7174 * the bo. We currently fill all unused PTE with the shadow
7175 * page and so we should always have valid PTE following the
7176 * cursor preventing the VT-d warning.
7177 */
7178 alignment = 0;
7179 if (need_vtd_wa(dev))
7180 alignment = 64*1024;
7181
7182 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 7183 if (ret) {
7184 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 7185 goto fail_locked;
e7b526bb
CW		 7186 }
7187
d9e86c0e
CW		 7188 ret = i915_gem_object_put_fence(obj);
7189 if (ret) {
2da3b9b9 7190 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 7191 goto fail_unpin;
7192 }
7193
f343c5f6 7194 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 7195 } else {
6eeefaf3 7196 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 7197 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 7198 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7199 align);
71acb5eb
DA		 7200 if (ret) {
7201 DRM_ERROR("failed to attach phys object\n");
7f9872e0 7202 goto fail_locked;
71acb5eb 7203 }
05394f39 7204 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 7205 }
7206
a6c45cf0 7207 if (IS_GEN2(dev))
14b60391
JB		 7208 I915_WRITE(CURSIZE, (height << 12) | width);
7209
3f8bc370 7210 finish:
3f8bc370 7211 if (intel_crtc->cursor_bo) {
b295d1b6 7212 if (dev_priv->info->cursor_needs_physical) {
05394f39 7213 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 7214 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7215 } else
cc98b413 7216 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 7217 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 7218 }
80824003 7219
7f9872e0 7220 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 7221
7222 intel_crtc->cursor_addr = addr;
05394f39 7223 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 7224 intel_crtc->cursor_width = width;
7225 intel_crtc->cursor_height = height;
7226
f2f5f771
VS		 7227 if (intel_crtc->active)
7228 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 7229
79e53945 7230 return 0;
e7b526bb 7231fail_unpin:
cc98b413 7232 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 7233fail_locked:
34b8686e 7234 mutex_unlock(&dev->struct_mutex);
bc9025bd 7235fail:
05394f39 7236 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 7237 return ret;
79e53945
JB		 7238}
7239
7240static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7241{
79e53945 7242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7243
cda4b7d3
CW		 7244 intel_crtc->cursor_x = x;
7245 intel_crtc->cursor_y = y;
652c393a 7246
f2f5f771
VS		 7247 if (intel_crtc->active)
7248 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 7249
7250 return 0;
b8c00ac5
DA		 7251}
7252
79e53945 7253static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7254 u16 *blue, uint32_t start, uint32_t size)
79e53945 7255{
7203425a 7256 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7257 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7258
7203425a 7259 for (i = start; i < end; i++) {
79e53945
JB		 7260 intel_crtc->lut_r[i] = red[i] >> 8;
7261 intel_crtc->lut_g[i] = green[i] >> 8;
7262 intel_crtc->lut_b[i] = blue[i] >> 8;
7263 }
7264
7265 intel_crtc_load_lut(crtc);
7266}
7267
79e53945
JB		 7268/* VESA 640x480x72Hz mode to set on the pipe */
7269static struct drm_display_mode load_detect_mode = {
7270 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7271 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7272};
7273
d2dff872
CW		 7274static struct drm_framebuffer *
7275intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7276 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7277 struct drm_i915_gem_object *obj)
7278{
7279 struct intel_framebuffer *intel_fb;
7280 int ret;
7281
7282 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7283 if (!intel_fb) {
7284 drm_gem_object_unreference_unlocked(&obj->base);
7285 return ERR_PTR(-ENOMEM);
7286 }
7287
dd4916c5
DV		 7288 ret = i915_mutex_lock_interruptible(dev);
7289 if (ret)
7290 goto err;
7291
d2dff872 7292 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 7293 mutex_unlock(&dev->struct_mutex);
7294 if (ret)
7295 goto err;
d2dff872
CW		 7296
7297 return &intel_fb->base;
dd4916c5
DV		 7298err:
7299 drm_gem_object_unreference_unlocked(&obj->base);
7300 kfree(intel_fb);
7301
7302 return ERR_PTR(ret);
d2dff872
CW		 7303}
7304
7305static u32
7306intel_framebuffer_pitch_for_width(int width, int bpp)
7307{
7308 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7309 return ALIGN(pitch, 64);
7310}
7311
7312static u32
7313intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7314{
7315 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7316 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7317}
7318
7319static struct drm_framebuffer *
7320intel_framebuffer_create_for_mode(struct drm_device *dev,
7321 struct drm_display_mode *mode,
7322 int depth, int bpp)
7323{
7324 struct drm_i915_gem_object *obj;
0fed39bd 7325 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7326
7327 obj = i915_gem_alloc_object(dev,
7328 intel_framebuffer_size_for_mode(mode, bpp));
7329 if (obj == NULL)
7330 return ERR_PTR(-ENOMEM);
7331
7332 mode_cmd.width = mode->hdisplay;
7333 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7334 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7335 bpp);
5ca0c34a 7336 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7337
7338 return intel_framebuffer_create(dev, &mode_cmd, obj);
7339}
7340
7341static struct drm_framebuffer *
7342mode_fits_in_fbdev(struct drm_device *dev,
7343 struct drm_display_mode *mode)
7344{
4520f53a 7345#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 7346 struct drm_i915_private *dev_priv = dev->dev_private;
7347 struct drm_i915_gem_object *obj;
7348 struct drm_framebuffer *fb;
7349
7350 if (dev_priv->fbdev == NULL)
7351 return NULL;
7352
7353 obj = dev_priv->fbdev->ifb.obj;
7354 if (obj == NULL)
7355 return NULL;
7356
7357 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7358 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7359 fb->bits_per_pixel))
d2dff872
CW		 7360 return NULL;
7361
01f2c773 7362 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7363 return NULL;
7364
7365 return fb;
4520f53a
DV		 7366#else
7367 return NULL;
7368#endif
d2dff872
CW		 7369}
7370
d2434ab7 7371bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7372 struct drm_display_mode *mode,
8261b191 7373 struct intel_load_detect_pipe *old)
79e53945
JB		 7374{
7375 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7376 struct intel_encoder *intel_encoder =
7377 intel_attached_encoder(connector);
79e53945 7378 struct drm_crtc *possible_crtc;
4ef69c7a 7379 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7380 struct drm_crtc *crtc = NULL;
7381 struct drm_device *dev = encoder->dev;
94352cf9 7382 struct drm_framebuffer *fb;
79e53945
JB		 7383 int i = -1;
7384
d2dff872
CW		 7385 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7386 connector->base.id, drm_get_connector_name(connector),
7387 encoder->base.id, drm_get_encoder_name(encoder));
7388
79e53945
JB		 7389 /*
7390 * Algorithm gets a little messy:
7a5e4805 7391 *
79e53945
JB		 7392 * - if the connector already has an assigned crtc, use it (but make
7393 * sure it's on first)
7a5e4805 7394 *
79e53945
JB		 7395 * - try to find the first unused crtc that can drive this connector,
7396 * and use that if we find one
79e53945
JB		 7397 */
7398
7399 /* See if we already have a CRTC for this connector */
7400 if (encoder->crtc) {
7401 crtc = encoder->crtc;
8261b191 7402
7b24056b
DV		 7403 mutex_lock(&crtc->mutex);
7404
24218aac 7405 old->dpms_mode = connector->dpms;
8261b191
CW		 7406 old->load_detect_temp = false;
7407
7408 /* Make sure the crtc and connector are running */
24218aac
DV		 7409 if (connector->dpms != DRM_MODE_DPMS_ON)
7410 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7411
7173188d 7412 return true;
79e53945
JB		 7413 }
7414
7415 /* Find an unused one (if possible) */
7416 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7417 i++;
7418 if (!(encoder->possible_crtcs & (1 << i)))
7419 continue;
7420 if (!possible_crtc->enabled) {
7421 crtc = possible_crtc;
7422 break;
7423 }
79e53945
JB		 7424 }
7425
7426 /*
7427 * If we didn't find an unused CRTC, don't use any.
7428 */
7429 if (!crtc) {
7173188d
CW		 7430 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7431 return false;
79e53945
JB		 7432 }
7433
7b24056b 7434 mutex_lock(&crtc->mutex);
fc303101
DV		 7435 intel_encoder->new_crtc = to_intel_crtc(crtc);
7436 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7437
7438 intel_crtc = to_intel_crtc(crtc);
24218aac 7439 old->dpms_mode = connector->dpms;
8261b191 7440 old->load_detect_temp = true;
d2dff872 7441 old->release_fb = NULL;
79e53945 7442
6492711d
CW		 7443 if (!mode)
7444 mode = &load_detect_mode;
79e53945 7445
d2dff872
CW		 7446 /* We need a framebuffer large enough to accommodate all accesses
7447 * that the plane may generate whilst we perform load detection.
7448 * We can not rely on the fbcon either being present (we get called
7449 * during its initialisation to detect all boot displays, or it may
7450 * not even exist) or that it is large enough to satisfy the
7451 * requested mode.
7452 */
94352cf9
DV		 7453 fb = mode_fits_in_fbdev(dev, mode);
7454 if (fb == NULL) {
d2dff872 7455 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7456 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7457 old->release_fb = fb;
d2dff872
CW		 7458 } else
7459 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7460 if (IS_ERR(fb)) {
d2dff872 7461 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7462 mutex_unlock(&crtc->mutex);
0e8b3d3e 7463 return false;
79e53945 7464 }
79e53945 7465
c0c36b94 7466 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7467 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7468 if (old->release_fb)
7469 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7470 mutex_unlock(&crtc->mutex);
0e8b3d3e 7471 return false;
79e53945 7472 }
7173188d 7473
79e53945 7474 /* let the connector get through one full cycle before testing */
9d0498a2 7475 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7476 return true;
79e53945
JB		 7477}
7478
d2434ab7 7479void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7480 struct intel_load_detect_pipe *old)
79e53945 7481{
d2434ab7
DV		 7482 struct intel_encoder *intel_encoder =
7483 intel_attached_encoder(connector);
4ef69c7a 7484 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7485 struct drm_crtc *crtc = encoder->crtc;
79e53945 7486
d2dff872
CW		 7487 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7488 connector->base.id, drm_get_connector_name(connector),
7489 encoder->base.id, drm_get_encoder_name(encoder));
7490
8261b191 7491 if (old->load_detect_temp) {
fc303101
DV		 7492 to_intel_connector(connector)->new_encoder = NULL;
7493 intel_encoder->new_crtc = NULL;
7494 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7495
36206361
DV		 7496 if (old->release_fb) {
7497 drm_framebuffer_unregister_private(old->release_fb);
7498 drm_framebuffer_unreference(old->release_fb);
7499 }
d2dff872 7500
67c96400 7501 mutex_unlock(&crtc->mutex);
0622a53c 7502 return;
79e53945
JB		 7503 }
7504
c751ce4f 7505 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7506 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7507 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7508
7509 mutex_unlock(&crtc->mutex);
79e53945
JB		 7510}
7511
da4a1efa
VS		 7512static int i9xx_pll_refclk(struct drm_device *dev,
7513 const struct intel_crtc_config *pipe_config)
7514{
7515 struct drm_i915_private *dev_priv = dev->dev_private;
7516 u32 dpll = pipe_config->dpll_hw_state.dpll;
7517
7518 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7519 return dev_priv->vbt.lvds_ssc_freq * 1000;
7520 else if (HAS_PCH_SPLIT(dev))
7521 return 120000;
7522 else if (!IS_GEN2(dev))
7523 return 96000;
7524 else
7525 return 48000;
7526}
7527
79e53945 7528/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7529static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7530 struct intel_crtc_config *pipe_config)
79e53945 7531{
f1f644dc 7532 struct drm_device *dev = crtc->base.dev;
79e53945 7533 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7534 int pipe = pipe_config->cpu_transcoder;
293623f7 7535 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 7536 u32 fp;
7537 intel_clock_t clock;
da4a1efa 7538 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 7539
7540 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 7541 fp = pipe_config->dpll_hw_state.fp0;
79e53945 7542 else
293623f7 7543 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 7544
7545 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7546 if (IS_PINEVIEW(dev)) {
7547 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7548 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7549 } else {
7550 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7551 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7552 }
7553
a6c45cf0 7554 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7555 if (IS_PINEVIEW(dev))
7556 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7557 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7558 else
7559 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7560 DPLL_FPA01_P1_POST_DIV_SHIFT);
7561
7562 switch (dpll & DPLL_MODE_MASK) {
7563 case DPLLB_MODE_DAC_SERIAL:
7564 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7565 5 : 10;
7566 break;
7567 case DPLLB_MODE_LVDS:
7568 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7569 7 : 14;
7570 break;
7571 default:
28c97730 7572 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7573 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 7574 return;
79e53945
JB		 7575 }
7576
ac58c3f0 7577 if (IS_PINEVIEW(dev))
da4a1efa 7578 pineview_clock(refclk, &clock);
ac58c3f0 7579 else
da4a1efa 7580 i9xx_clock(refclk, &clock);
79e53945
JB		 7581 } else {
7582 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7583
7584 if (is_lvds) {
7585 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7586 DPLL_FPA01_P1_POST_DIV_SHIFT);
7587 clock.p2 = 14;
79e53945
JB		 7588 } else {
7589 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7590 clock.p1 = 2;
7591 else {
7592 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7593 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7594 }
7595 if (dpll & PLL_P2_DIVIDE_BY_4)
7596 clock.p2 = 4;
7597 else
7598 clock.p2 = 2;
79e53945 7599 }
da4a1efa
VS		 7600
7601 i9xx_clock(refclk, &clock);
79e53945
JB		 7602 }
7603
18442d08
VS		 7604 /*
7605 * This value includes pixel_multiplier. We will use
241bfc38 7606 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 7607 * encoder's get_config() function.
7608 */
7609 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 7610}
7611
6878da05
VS		 7612int intel_dotclock_calculate(int link_freq,
7613 const struct intel_link_m_n *m_n)
f1f644dc 7614{
f1f644dc
JB		 7615 /*
7616 * The calculation for the data clock is:
1041a02f 7617 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 7618 * But we want to avoid losing precison if possible, so:
1041a02f 7619 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 7620 *
7621 * and the link clock is simpler:
1041a02f 7622 * link_clock = (m * link_clock) / n
f1f644dc
JB		 7623 */
7624
6878da05
VS		 7625 if (!m_n->link_n)
7626 return 0;
f1f644dc 7627
6878da05
VS		 7628 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7629}
f1f644dc 7630
18442d08
VS		 7631static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7632 struct intel_crtc_config *pipe_config)
6878da05
VS		 7633{
7634 struct drm_device *dev = crtc->base.dev;
79e53945 7635
18442d08
VS		 7636 /* read out port_clock from the DPLL */
7637 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 7638
f1f644dc 7639 /*
18442d08 7640 * This value does not include pixel_multiplier.
241bfc38 7641 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 7642 * agree once we know their relationship in the encoder's
7643 * get_config() function.
79e53945 7644 */
241bfc38 7645 pipe_config->adjusted_mode.crtc_clock =
18442d08
VS		 7646 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7647 &pipe_config->fdi_m_n);
79e53945
JB		 7648}
7649
7650/** Returns the currently programmed mode of the given pipe. */
7651struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7652 struct drm_crtc *crtc)
7653{
548f245b 7654 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7656 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7657 struct drm_display_mode *mode;
f1f644dc 7658 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7659 int htot = I915_READ(HTOTAL(cpu_transcoder));
7660 int hsync = I915_READ(HSYNC(cpu_transcoder));
7661 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7662 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 7663 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 7664
7665 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7666 if (!mode)
7667 return NULL;
7668
f1f644dc
JB		 7669 /*
7670 * Construct a pipe_config sufficient for getting the clock info
7671 * back out of crtc_clock_get.
7672 *
7673 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7674 * to use a real value here instead.
7675 */
293623f7 7676 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 7677 pipe_config.pixel_multiplier = 1;
293623f7
VS		 7678 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7679 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7680 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 7681 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7682
773ae034 7683 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 7684 mode->hdisplay = (htot & 0xffff) + 1;
7685 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7686 mode->hsync_start = (hsync & 0xffff) + 1;
7687 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7688 mode->vdisplay = (vtot & 0xffff) + 1;
7689 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7690 mode->vsync_start = (vsync & 0xffff) + 1;
7691 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7692
7693 drm_mode_set_name(mode);
79e53945
JB		 7694
7695 return mode;
7696}
7697
3dec0095 7698static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7699{
7700 struct drm_device *dev = crtc->dev;
7701 drm_i915_private_t *dev_priv = dev->dev_private;
7702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7703 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7704 int dpll_reg = DPLL(pipe);
7705 int dpll;
652c393a 7706
bad720ff 7707 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7708 return;
7709
7710 if (!dev_priv->lvds_downclock_avail)
7711 return;
7712
dbdc6479 7713 dpll = I915_READ(dpll_reg);
652c393a 7714 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7715 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7716
8ac5a6d5 7717 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7718
7719 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7720 I915_WRITE(dpll_reg, dpll);
9d0498a2 7721 intel_wait_for_vblank(dev, pipe);
dbdc6479 7722
652c393a
JB		 7723 dpll = I915_READ(dpll_reg);
7724 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7725 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7726 }
652c393a
JB		 7727}
7728
7729static void intel_decrease_pllclock(struct drm_crtc *crtc)
7730{
7731 struct drm_device *dev = crtc->dev;
7732 drm_i915_private_t *dev_priv = dev->dev_private;
7733 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7734
bad720ff 7735 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7736 return;
7737
7738 if (!dev_priv->lvds_downclock_avail)
7739 return;
7740
7741 /*
7742 * Since this is called by a timer, we should never get here in
7743 * the manual case.
7744 */
7745 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7746 int pipe = intel_crtc->pipe;
7747 int dpll_reg = DPLL(pipe);
7748 int dpll;
f6e5b160 7749
44d98a61 7750 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7751
8ac5a6d5 7752 assert_panel_unlocked(dev_priv, pipe);
652c393a 7753
dc257cf1 7754 dpll = I915_READ(dpll_reg);
652c393a
JB		 7755 dpll |= DISPLAY_RATE_SELECT_FPA1;
7756 I915_WRITE(dpll_reg, dpll);
9d0498a2 7757 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7758 dpll = I915_READ(dpll_reg);
7759 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7760 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7761 }
7762
7763}
7764
f047e395
CW		 7765void intel_mark_busy(struct drm_device *dev)
7766{
c67a470b
PZ		 7767 struct drm_i915_private *dev_priv = dev->dev_private;
7768
7769 hsw_package_c8_gpu_busy(dev_priv);
7770 i915_update_gfx_val(dev_priv);
f047e395
CW		 7771}
7772
7773void intel_mark_idle(struct drm_device *dev)
652c393a 7774{
c67a470b 7775 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7776 struct drm_crtc *crtc;
652c393a 7777
c67a470b
PZ		 7778 hsw_package_c8_gpu_idle(dev_priv);
7779
652c393a
JB		 7780 if (!i915_powersave)
7781 return;
7782
652c393a 7783 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7784 if (!crtc->fb)
7785 continue;
7786
725a5b54 7787 intel_decrease_pllclock(crtc);
652c393a 7788 }
b29c19b6
CW		 7789
7790 if (dev_priv->info->gen >= 6)
7791 gen6_rps_idle(dev->dev_private);
652c393a
JB		 7792}
7793
c65355bb
CW		 7794void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7795 struct intel_ring_buffer *ring)
652c393a 7796{
f047e395
CW		 7797 struct drm_device *dev = obj->base.dev;
7798 struct drm_crtc *crtc;
652c393a 7799
f047e395 7800 if (!i915_powersave)
acb87dfb
CW		 7801 return;
7802
652c393a
JB		 7803 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7804 if (!crtc->fb)
7805 continue;
7806
c65355bb
CW		 7807 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7808 continue;
7809
7810 intel_increase_pllclock(crtc);
7811 if (ring && intel_fbc_enabled(dev))
7812 ring->fbc_dirty = true;
652c393a
JB		 7813 }
7814}
7815
79e53945
JB		 7816static void intel_crtc_destroy(struct drm_crtc *crtc)
7817{
7818 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7819 struct drm_device *dev = crtc->dev;
7820 struct intel_unpin_work *work;
7821 unsigned long flags;
7822
7823 spin_lock_irqsave(&dev->event_lock, flags);
7824 work = intel_crtc->unpin_work;
7825 intel_crtc->unpin_work = NULL;
7826 spin_unlock_irqrestore(&dev->event_lock, flags);
7827
7828 if (work) {
7829 cancel_work_sync(&work->work);
7830 kfree(work);
7831 }
79e53945 7832
40ccc72b
MK		 7833 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7834
79e53945 7835 drm_crtc_cleanup(crtc);
67e77c5a 7836
79e53945
JB		 7837 kfree(intel_crtc);
7838}
7839
6b95a207
KH		 7840static void intel_unpin_work_fn(struct work_struct *__work)
7841{
7842 struct intel_unpin_work *work =
7843 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7844 struct drm_device *dev = work->crtc->dev;
6b95a207 7845
b4a98e57 7846 mutex_lock(&dev->struct_mutex);
1690e1eb 7847 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7848 drm_gem_object_unreference(&work->pending_flip_obj->base);
7849 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7850
b4a98e57
CW		 7851 intel_update_fbc(dev);
7852 mutex_unlock(&dev->struct_mutex);
7853
7854 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7855 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7856
6b95a207
KH		 7857 kfree(work);
7858}
7859
1afe3e9d 7860static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7861 struct drm_crtc *crtc)
6b95a207
KH		 7862{
7863 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7864 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7865 struct intel_unpin_work *work;
6b95a207
KH		 7866 unsigned long flags;
7867
7868 /* Ignore early vblank irqs */
7869 if (intel_crtc == NULL)
7870 return;
7871
7872 spin_lock_irqsave(&dev->event_lock, flags);
7873 work = intel_crtc->unpin_work;
e7d841ca
CW		 7874
7875 /* Ensure we don't miss a work->pending update ... */
7876 smp_rmb();
7877
7878 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7879 spin_unlock_irqrestore(&dev->event_lock, flags);
7880 return;
7881 }
7882
e7d841ca
CW		 7883 /* and that the unpin work is consistent wrt ->pending. */
7884 smp_rmb();
7885
6b95a207 7886 intel_crtc->unpin_work = NULL;
6b95a207 7887
45a066eb
RC		 7888 if (work->event)
7889 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7890
0af7e4df
MK		 7891 drm_vblank_put(dev, intel_crtc->pipe);
7892
6b95a207
KH		 7893 spin_unlock_irqrestore(&dev->event_lock, flags);
7894
2c10d571 7895 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7896
7897 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7898
7899 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7900}
7901
1afe3e9d
JB		 7902void intel_finish_page_flip(struct drm_device *dev, int pipe)
7903{
7904 drm_i915_private_t *dev_priv = dev->dev_private;
7905 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7906
49b14a5c 7907 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7908}
7909
7910void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7911{
7912 drm_i915_private_t *dev_priv = dev->dev_private;
7913 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7914
49b14a5c 7915 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7916}
7917
6b95a207
KH		 7918void intel_prepare_page_flip(struct drm_device *dev, int plane)
7919{
7920 drm_i915_private_t *dev_priv = dev->dev_private;
7921 struct intel_crtc *intel_crtc =
7922 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7923 unsigned long flags;
7924
e7d841ca
CW		 7925 /* NB: An MMIO update of the plane base pointer will also
7926 * generate a page-flip completion irq, i.e. every modeset
7927 * is also accompanied by a spurious intel_prepare_page_flip().
7928 */
6b95a207 7929 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7930 if (intel_crtc->unpin_work)
7931 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7932 spin_unlock_irqrestore(&dev->event_lock, flags);
7933}
7934
e7d841ca
CW		 7935inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7936{
7937 /* Ensure that the work item is consistent when activating it ... */
7938 smp_wmb();
7939 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7940 /* and that it is marked active as soon as the irq could fire. */
7941 smp_wmb();
7942}
7943
8c9f3aaf
JB		 7944static int intel_gen2_queue_flip(struct drm_device *dev,
7945 struct drm_crtc *crtc,
7946 struct drm_framebuffer *fb,
ed8d1975
KP		 7947 struct drm_i915_gem_object *obj,
7948 uint32_t flags)
8c9f3aaf
JB		 7949{
7950 struct drm_i915_private *dev_priv = dev->dev_private;
7951 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7952 u32 flip_mask;
6d90c952 7953 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7954 int ret;
7955
6d90c952 7956 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7957 if (ret)
83d4092b 7958 goto err;
8c9f3aaf 7959
6d90c952 7960 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7961 if (ret)
83d4092b 7962 goto err_unpin;
8c9f3aaf
JB		 7963
7964 /* Can't queue multiple flips, so wait for the previous
7965 * one to finish before executing the next.
7966 */
7967 if (intel_crtc->plane)
7968 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7969 else
7970 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7971 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7972 intel_ring_emit(ring, MI_NOOP);
7973 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7974 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7975 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7976 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7977 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7978
7979 intel_mark_page_flip_active(intel_crtc);
09246732 7980 __intel_ring_advance(ring);
83d4092b
CW		 7981 return 0;
7982
7983err_unpin:
7984 intel_unpin_fb_obj(obj);
7985err:
8c9f3aaf
JB		 7986 return ret;
7987}
7988
7989static int intel_gen3_queue_flip(struct drm_device *dev,
7990 struct drm_crtc *crtc,
7991 struct drm_framebuffer *fb,
ed8d1975
KP		 7992 struct drm_i915_gem_object *obj,
7993 uint32_t flags)
8c9f3aaf
JB		 7994{
7995 struct drm_i915_private *dev_priv = dev->dev_private;
7996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7997 u32 flip_mask;
6d90c952 7998 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7999 int ret;
8000
6d90c952 8001 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8002 if (ret)
83d4092b 8003 goto err;
8c9f3aaf 8004
6d90c952 8005 ret = intel_ring_begin(ring, 6);
8c9f3aaf 8006 if (ret)
83d4092b 8007 goto err_unpin;
8c9f3aaf
JB		 8008
8009 if (intel_crtc->plane)
8010 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
8011 else
8012 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 8013 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
8014 intel_ring_emit(ring, MI_NOOP);
8015 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
8016 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8017 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 8018 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 8019 intel_ring_emit(ring, MI_NOOP);
8020
e7d841ca 8021 intel_mark_page_flip_active(intel_crtc);
09246732 8022 __intel_ring_advance(ring);
83d4092b
CW		 8023 return 0;
8024
8025err_unpin:
8026 intel_unpin_fb_obj(obj);
8027err:
8c9f3aaf
JB		 8028 return ret;
8029}
8030
8031static int intel_gen4_queue_flip(struct drm_device *dev,
8032 struct drm_crtc *crtc,
8033 struct drm_framebuffer *fb,
ed8d1975
KP		 8034 struct drm_i915_gem_object *obj,
8035 uint32_t flags)
8c9f3aaf
JB		 8036{
8037 struct drm_i915_private *dev_priv = dev->dev_private;
8038 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8039 uint32_t pf, pipesrc;
6d90c952 8040 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8041 int ret;
8042
6d90c952 8043 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8044 if (ret)
83d4092b 8045 goto err;
8c9f3aaf 8046
6d90c952 8047 ret = intel_ring_begin(ring, 4);
8c9f3aaf 8048 if (ret)
83d4092b 8049 goto err_unpin;
8c9f3aaf
JB		 8050
8051 /* i965+ uses the linear or tiled offsets from the
8052 * Display Registers (which do not change across a page-flip)
8053 * so we need only reprogram the base address.
8054 */
6d90c952
DV		 8055 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8056 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8057 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 8058 intel_ring_emit(ring,
f343c5f6 8059 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 8060 obj->tiling_mode);
8c9f3aaf
JB		 8061
8062 /* XXX Enabling the panel-fitter across page-flip is so far
8063 * untested on non-native modes, so ignore it for now.
8064 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8065 */
8066 pf = 0;
8067 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 8068 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 8069
8070 intel_mark_page_flip_active(intel_crtc);
09246732 8071 __intel_ring_advance(ring);
83d4092b
CW		 8072 return 0;
8073
8074err_unpin:
8075 intel_unpin_fb_obj(obj);
8076err:
8c9f3aaf
JB		 8077 return ret;
8078}
8079
8080static int intel_gen6_queue_flip(struct drm_device *dev,
8081 struct drm_crtc *crtc,
8082 struct drm_framebuffer *fb,
ed8d1975
KP		 8083 struct drm_i915_gem_object *obj,
8084 uint32_t flags)
8c9f3aaf
JB		 8085{
8086 struct drm_i915_private *dev_priv = dev->dev_private;
8087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 8088 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8089 uint32_t pf, pipesrc;
8090 int ret;
8091
6d90c952 8092 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8093 if (ret)
83d4092b 8094 goto err;
8c9f3aaf 8095
6d90c952 8096 ret = intel_ring_begin(ring, 4);
8c9f3aaf 8097 if (ret)
83d4092b 8098 goto err_unpin;
8c9f3aaf 8099
6d90c952
DV		 8100 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8101 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8102 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 8103 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 8104
dc257cf1
DV		 8105 /* Contrary to the suggestions in the documentation,
8106 * "Enable Panel Fitter" does not seem to be required when page
8107 * flipping with a non-native mode, and worse causes a normal
8108 * modeset to fail.
8109 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8110 */
8111 pf = 0;
8c9f3aaf 8112 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 8113 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 8114
8115 intel_mark_page_flip_active(intel_crtc);
09246732 8116 __intel_ring_advance(ring);
83d4092b
CW		 8117 return 0;
8118
8119err_unpin:
8120 intel_unpin_fb_obj(obj);
8121err:
8c9f3aaf
JB		 8122 return ret;
8123}
8124
7c9017e5
JB		 8125static int intel_gen7_queue_flip(struct drm_device *dev,
8126 struct drm_crtc *crtc,
8127 struct drm_framebuffer *fb,
ed8d1975
KP		 8128 struct drm_i915_gem_object *obj,
8129 uint32_t flags)
7c9017e5
JB		 8130{
8131 struct drm_i915_private *dev_priv = dev->dev_private;
8132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 8133 struct intel_ring_buffer *ring;
cb05d8de 8134 uint32_t plane_bit = 0;
ffe74d75
CW		 8135 int len, ret;
8136
8137 ring = obj->ring;
1c5fd085 8138 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
ffe74d75 8139 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 8140
8141 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8142 if (ret)
83d4092b 8143 goto err;
7c9017e5 8144
cb05d8de
DV		 8145 switch(intel_crtc->plane) {
8146 case PLANE_A:
8147 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8148 break;
8149 case PLANE_B:
8150 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8151 break;
8152 case PLANE_C:
8153 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8154 break;
8155 default:
8156 WARN_ONCE(1, "unknown plane in flip command\n");
8157 ret = -ENODEV;
ab3951eb 8158 goto err_unpin;
cb05d8de
DV		 8159 }
8160
ffe74d75
CW		 8161 len = 4;
8162 if (ring->id == RCS)
8163 len += 6;
8164
8165 ret = intel_ring_begin(ring, len);
7c9017e5 8166 if (ret)
83d4092b 8167 goto err_unpin;
7c9017e5 8168
ffe74d75
CW		 8169 /* Unmask the flip-done completion message. Note that the bspec says that
8170 * we should do this for both the BCS and RCS, and that we must not unmask
8171 * more than one flip event at any time (or ensure that one flip message
8172 * can be sent by waiting for flip-done prior to queueing new flips).
8173 * Experimentation says that BCS works despite DERRMR masking all
8174 * flip-done completion events and that unmasking all planes at once
8175 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8176 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8177 */
8178 if (ring->id == RCS) {
8179 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8180 intel_ring_emit(ring, DERRMR);
8181 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8182 DERRMR_PIPEB_PRI_FLIP_DONE |
8183 DERRMR_PIPEC_PRI_FLIP_DONE));
8184 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8185 intel_ring_emit(ring, DERRMR);
8186 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8187 }
8188
cb05d8de 8189 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 8190 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 8191 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 8192 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 8193
8194 intel_mark_page_flip_active(intel_crtc);
09246732 8195 __intel_ring_advance(ring);
83d4092b
CW		 8196 return 0;
8197
8198err_unpin:
8199 intel_unpin_fb_obj(obj);
8200err:
7c9017e5
JB		 8201 return ret;
8202}
8203
8c9f3aaf
JB		 8204static int intel_default_queue_flip(struct drm_device *dev,
8205 struct drm_crtc *crtc,
8206 struct drm_framebuffer *fb,
ed8d1975
KP		 8207 struct drm_i915_gem_object *obj,
8208 uint32_t flags)
8c9f3aaf
JB		 8209{
8210 return -ENODEV;
8211}
8212
6b95a207
KH		 8213static int intel_crtc_page_flip(struct drm_crtc *crtc,
8214 struct drm_framebuffer *fb,
ed8d1975
KP		 8215 struct drm_pending_vblank_event *event,
8216 uint32_t page_flip_flags)
6b95a207
KH		 8217{
8218 struct drm_device *dev = crtc->dev;
8219 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 8220 struct drm_framebuffer *old_fb = crtc->fb;
8221 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 8222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8223 struct intel_unpin_work *work;
8c9f3aaf 8224 unsigned long flags;
52e68630 8225 int ret;
6b95a207 8226
e6a595d2
VS		 8227 /* Can't change pixel format via MI display flips. */
8228 if (fb->pixel_format != crtc->fb->pixel_format)
8229 return -EINVAL;
8230
8231 /*
8232 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8233 * Note that pitch changes could also affect these register.
8234 */
8235 if (INTEL_INFO(dev)->gen > 3 &&
8236 (fb->offsets[0] != crtc->fb->offsets[0] ||
8237 fb->pitches[0] != crtc->fb->pitches[0]))
8238 return -EINVAL;
8239
b14c5679 8240 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 8241 if (work == NULL)
8242 return -ENOMEM;
8243
6b95a207 8244 work->event = event;
b4a98e57 8245 work->crtc = crtc;
4a35f83b 8246 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 8247 INIT_WORK(&work->work, intel_unpin_work_fn);
8248
7317c75e
JB		 8249 ret = drm_vblank_get(dev, intel_crtc->pipe);
8250 if (ret)
8251 goto free_work;
8252
6b95a207
KH		 8253 /* We borrow the event spin lock for protecting unpin_work */
8254 spin_lock_irqsave(&dev->event_lock, flags);
8255 if (intel_crtc->unpin_work) {
8256 spin_unlock_irqrestore(&dev->event_lock, flags);
8257 kfree(work);
7317c75e 8258 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 8259
8260 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 8261 return -EBUSY;
8262 }
8263 intel_crtc->unpin_work = work;
8264 spin_unlock_irqrestore(&dev->event_lock, flags);
8265
b4a98e57
CW		 8266 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8267 flush_workqueue(dev_priv->wq);
8268
79158103
CW		 8269 ret = i915_mutex_lock_interruptible(dev);
8270 if (ret)
8271 goto cleanup;
6b95a207 8272
75dfca80 8273 /* Reference the objects for the scheduled work. */
05394f39
CW		 8274 drm_gem_object_reference(&work->old_fb_obj->base);
8275 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8276
8277 crtc->fb = fb;
96b099fd 8278
e1f99ce6 8279 work->pending_flip_obj = obj;
e1f99ce6 8280
4e5359cd
SF		 8281 work->enable_stall_check = true;
8282
b4a98e57 8283 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8284 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8285
ed8d1975 8286 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8287 if (ret)
8288 goto cleanup_pending;
6b95a207 8289
7782de3b 8290 intel_disable_fbc(dev);
c65355bb 8291 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8292 mutex_unlock(&dev->struct_mutex);
8293
e5510fac
JB		 8294 trace_i915_flip_request(intel_crtc->plane, obj);
8295
6b95a207 8296 return 0;
96b099fd 8297
8c9f3aaf 8298cleanup_pending:
b4a98e57 8299 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8300 crtc->fb = old_fb;
05394f39
CW		 8301 drm_gem_object_unreference(&work->old_fb_obj->base);
8302 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8303 mutex_unlock(&dev->struct_mutex);
8304
79158103 8305cleanup:
96b099fd
CW		 8306 spin_lock_irqsave(&dev->event_lock, flags);
8307 intel_crtc->unpin_work = NULL;
8308 spin_unlock_irqrestore(&dev->event_lock, flags);
8309
7317c75e
JB		 8310 drm_vblank_put(dev, intel_crtc->pipe);
8311free_work:
96b099fd
CW		 8312 kfree(work);
8313
8314 return ret;
6b95a207
KH		 8315}
8316
f6e5b160 8317static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8318 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8319 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8320};
8321
50f56119
DV		 8322static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8323 struct drm_crtc *crtc)
8324{
8325 struct drm_device *dev;
8326 struct drm_crtc *tmp;
8327 int crtc_mask = 1;
47f1c6c9 8328
50f56119 8329 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8330
50f56119 8331 dev = crtc->dev;
47f1c6c9 8332
50f56119
DV		 8333 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8334 if (tmp == crtc)
8335 break;
8336 crtc_mask <<= 1;
8337 }
47f1c6c9 8338
50f56119
DV		 8339 if (encoder->possible_crtcs & crtc_mask)
8340 return true;
8341 return false;
47f1c6c9 8342}
79e53945 8343
9a935856
DV		 8344/**
8345 * intel_modeset_update_staged_output_state
8346 *
8347 * Updates the staged output configuration state, e.g. after we've read out the
8348 * current hw state.
8349 */
8350static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8351{
9a935856
DV		 8352 struct intel_encoder *encoder;
8353 struct intel_connector *connector;
f6e5b160 8354
9a935856
DV		 8355 list_for_each_entry(connector, &dev->mode_config.connector_list,
8356 base.head) {
8357 connector->new_encoder =
8358 to_intel_encoder(connector->base.encoder);
8359 }
f6e5b160 8360
9a935856
DV		 8361 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8362 base.head) {
8363 encoder->new_crtc =
8364 to_intel_crtc(encoder->base.crtc);
8365 }
f6e5b160
CW		 8366}
8367
9a935856
DV		 8368/**
8369 * intel_modeset_commit_output_state
8370 *
8371 * This function copies the stage display pipe configuration to the real one.
8372 */
8373static void intel_modeset_commit_output_state(struct drm_device *dev)
8374{
8375 struct intel_encoder *encoder;
8376 struct intel_connector *connector;
f6e5b160 8377
9a935856
DV		 8378 list_for_each_entry(connector, &dev->mode_config.connector_list,
8379 base.head) {
8380 connector->base.encoder = &connector->new_encoder->base;
8381 }
f6e5b160 8382
9a935856
DV		 8383 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8384 base.head) {
8385 encoder->base.crtc = &encoder->new_crtc->base;
8386 }
8387}
8388
050f7aeb
DV		 8389static void
8390connected_sink_compute_bpp(struct intel_connector * connector,
8391 struct intel_crtc_config *pipe_config)
8392{
8393 int bpp = pipe_config->pipe_bpp;
8394
8395 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8396 connector->base.base.id,
8397 drm_get_connector_name(&connector->base));
8398
8399 /* Don't use an invalid EDID bpc value */
8400 if (connector->base.display_info.bpc &&
8401 connector->base.display_info.bpc * 3 < bpp) {
8402 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8403 bpp, connector->base.display_info.bpc*3);
8404 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8405 }
8406
8407 /* Clamp bpp to 8 on screens without EDID 1.4 */
8408 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8409 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8410 bpp);
8411 pipe_config->pipe_bpp = 24;
8412 }
8413}
8414
4e53c2e0 8415static int
050f7aeb
DV		 8416compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8417 struct drm_framebuffer *fb,
8418 struct intel_crtc_config *pipe_config)
4e53c2e0 8419{
050f7aeb
DV		 8420 struct drm_device *dev = crtc->base.dev;
8421 struct intel_connector *connector;
4e53c2e0
DV		 8422 int bpp;
8423
d42264b1
DV		 8424 switch (fb->pixel_format) {
8425 case DRM_FORMAT_C8:
4e53c2e0
DV		 8426 bpp = 8*3; /* since we go through a colormap */
8427 break;
d42264b1
DV		 8428 case DRM_FORMAT_XRGB1555:
8429 case DRM_FORMAT_ARGB1555:
8430 /* checked in intel_framebuffer_init already */
8431 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8432 return -EINVAL;
8433 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8434 bpp = 6*3; /* min is 18bpp */
8435 break;
d42264b1
DV		 8436 case DRM_FORMAT_XBGR8888:
8437 case DRM_FORMAT_ABGR8888:
8438 /* checked in intel_framebuffer_init already */
8439 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8440 return -EINVAL;
8441 case DRM_FORMAT_XRGB8888:
8442 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8443 bpp = 8*3;
8444 break;
d42264b1
DV		 8445 case DRM_FORMAT_XRGB2101010:
8446 case DRM_FORMAT_ARGB2101010:
8447 case DRM_FORMAT_XBGR2101010:
8448 case DRM_FORMAT_ABGR2101010:
8449 /* checked in intel_framebuffer_init already */
8450 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8451 return -EINVAL;
4e53c2e0
DV		 8452 bpp = 10*3;
8453 break;
baba133a 8454 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8455 default:
8456 DRM_DEBUG_KMS("unsupported depth\n");
8457 return -EINVAL;
8458 }
8459
4e53c2e0
DV		 8460 pipe_config->pipe_bpp = bpp;
8461
8462 /* Clamp display bpp to EDID value */
8463 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8464 base.head) {
1b829e05
DV		 8465 if (!connector->new_encoder ||
8466 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8467 continue;
8468
050f7aeb 8469 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8470 }
8471
8472 return bpp;
8473}
8474
644db711
DV		 8475static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8476{
8477 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8478 "type: 0x%x flags: 0x%x\n",
1342830c 8479 mode->crtc_clock,
644db711
DV		 8480 mode->crtc_hdisplay, mode->crtc_hsync_start,
8481 mode->crtc_hsync_end, mode->crtc_htotal,
8482 mode->crtc_vdisplay, mode->crtc_vsync_start,
8483 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8484}
8485
c0b03411
DV		 8486static void intel_dump_pipe_config(struct intel_crtc *crtc,
8487 struct intel_crtc_config *pipe_config,
8488 const char *context)
8489{
8490 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8491 context, pipe_name(crtc->pipe));
8492
8493 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8494 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8495 pipe_config->pipe_bpp, pipe_config->dither);
8496 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8497 pipe_config->has_pch_encoder,
8498 pipe_config->fdi_lanes,
8499 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8500 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8501 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 8502 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8503 pipe_config->has_dp_encoder,
8504 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8505 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8506 pipe_config->dp_m_n.tu);
c0b03411
DV		 8507 DRM_DEBUG_KMS("requested mode:\n");
8508 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8509 DRM_DEBUG_KMS("adjusted mode:\n");
8510 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
644db711 8511 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
d71b8d4a 8512 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 8513 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8514 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 8515 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8516 pipe_config->gmch_pfit.control,
8517 pipe_config->gmch_pfit.pgm_ratios,
8518 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 8519 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 8520 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 8521 pipe_config->pch_pfit.size,
8522 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 8523 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 8524 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
c0b03411
DV		 8525}
8526
accfc0c5
DV		 8527static bool check_encoder_cloning(struct drm_crtc *crtc)
8528{
8529 int num_encoders = 0;
8530 bool uncloneable_encoders = false;
8531 struct intel_encoder *encoder;
8532
8533 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8534 base.head) {
8535 if (&encoder->new_crtc->base != crtc)
8536 continue;
8537
8538 num_encoders++;
8539 if (!encoder->cloneable)
8540 uncloneable_encoders = true;
8541 }
8542
8543 return !(num_encoders > 1 && uncloneable_encoders);
8544}
8545
b8cecdf5
DV		 8546static struct intel_crtc_config *
8547intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8548 struct drm_framebuffer *fb,
b8cecdf5 8549 struct drm_display_mode *mode)
ee7b9f93 8550{
7758a113 8551 struct drm_device *dev = crtc->dev;
7758a113 8552 struct intel_encoder *encoder;
b8cecdf5 8553 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8554 int plane_bpp, ret = -EINVAL;
8555 bool retry = true;
ee7b9f93 8556
accfc0c5
DV		 8557 if (!check_encoder_cloning(crtc)) {
8558 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8559 return ERR_PTR(-EINVAL);
8560 }
8561
b8cecdf5
DV		 8562 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8563 if (!pipe_config)
7758a113
DV		 8564 return ERR_PTR(-ENOMEM);
8565
b8cecdf5
DV		 8566 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8567 drm_mode_copy(&pipe_config->requested_mode, mode);
37327abd 8568
e143a21c
DV		 8569 pipe_config->cpu_transcoder =
8570 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8571 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8572
2960bc9c
ID		 8573 /*
8574 * Sanitize sync polarity flags based on requested ones. If neither
8575 * positive or negative polarity is requested, treat this as meaning
8576 * negative polarity.
8577 */
8578 if (!(pipe_config->adjusted_mode.flags &
8579 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8580 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8581
8582 if (!(pipe_config->adjusted_mode.flags &
8583 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8584 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8585
050f7aeb
DV		 8586 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8587 * plane pixel format and any sink constraints into account. Returns the
8588 * source plane bpp so that dithering can be selected on mismatches
8589 * after encoders and crtc also have had their say. */
8590 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8591 fb, pipe_config);
4e53c2e0
DV		 8592 if (plane_bpp < 0)
8593 goto fail;
8594
e41a56be
VS		 8595 /*
8596 * Determine the real pipe dimensions. Note that stereo modes can
8597 * increase the actual pipe size due to the frame doubling and
8598 * insertion of additional space for blanks between the frame. This
8599 * is stored in the crtc timings. We use the requested mode to do this
8600 * computation to clearly distinguish it from the adjusted mode, which
8601 * can be changed by the connectors in the below retry loop.
8602 */
8603 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8604 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8605 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8606
e29c22c0 8607encoder_retry:
ef1b460d 8608 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8609 pipe_config->port_clock = 0;
ef1b460d 8610 pipe_config->pixel_multiplier = 1;
ff9a6750 8611
135c81b8 8612 /* Fill in default crtc timings, allow encoders to overwrite them. */
6ce70f5e 8613 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
135c81b8 8614
7758a113
DV		 8615 /* Pass our mode to the connectors and the CRTC to give them a chance to
8616 * adjust it according to limitations or connector properties, and also
8617 * a chance to reject the mode entirely.
47f1c6c9 8618 */
7758a113
DV		 8619 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8620 base.head) {
47f1c6c9 8621
7758a113
DV		 8622 if (&encoder->new_crtc->base != crtc)
8623 continue;
7ae89233 8624
efea6e8e
DV		 8625 if (!(encoder->compute_config(encoder, pipe_config))) {
8626 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8627 goto fail;
8628 }
ee7b9f93 8629 }
47f1c6c9 8630
ff9a6750
DV		 8631 /* Set default port clock if not overwritten by the encoder. Needs to be
8632 * done afterwards in case the encoder adjusts the mode. */
8633 if (!pipe_config->port_clock)
241bfc38
DL		 8634 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8635 * pipe_config->pixel_multiplier;
ff9a6750 8636
a43f6e0f 8637 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8638 if (ret < 0) {
7758a113
DV		 8639 DRM_DEBUG_KMS("CRTC fixup failed\n");
8640 goto fail;
ee7b9f93 8641 }
e29c22c0
DV		 8642
8643 if (ret == RETRY) {
8644 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8645 ret = -EINVAL;
8646 goto fail;
8647 }
8648
8649 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8650 retry = false;
8651 goto encoder_retry;
8652 }
8653
4e53c2e0
DV		 8654 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8655 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8656 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8657
b8cecdf5 8658 return pipe_config;
7758a113 8659fail:
b8cecdf5 8660 kfree(pipe_config);
e29c22c0 8661 return ERR_PTR(ret);
ee7b9f93 8662}
47f1c6c9 8663
e2e1ed41
DV		 8664/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8665 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8666static void
8667intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8668 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8669{
8670 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8671 struct drm_device *dev = crtc->dev;
8672 struct intel_encoder *encoder;
8673 struct intel_connector *connector;
8674 struct drm_crtc *tmp_crtc;
79e53945 8675
e2e1ed41 8676 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8677
e2e1ed41
DV		 8678 /* Check which crtcs have changed outputs connected to them, these need
8679 * to be part of the prepare_pipes mask. We don't (yet) support global
8680 * modeset across multiple crtcs, so modeset_pipes will only have one
8681 * bit set at most. */
8682 list_for_each_entry(connector, &dev->mode_config.connector_list,
8683 base.head) {
8684 if (connector->base.encoder == &connector->new_encoder->base)
8685 continue;
79e53945 8686
e2e1ed41
DV		 8687 if (connector->base.encoder) {
8688 tmp_crtc = connector->base.encoder->crtc;
8689
8690 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8691 }
8692
8693 if (connector->new_encoder)
8694 *prepare_pipes |=
8695 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8696 }
8697
e2e1ed41
DV		 8698 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8699 base.head) {
8700 if (encoder->base.crtc == &encoder->new_crtc->base)
8701 continue;
8702
8703 if (encoder->base.crtc) {
8704 tmp_crtc = encoder->base.crtc;
8705
8706 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8707 }
8708
8709 if (encoder->new_crtc)
8710 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8711 }
8712
e2e1ed41
DV		 8713 /* Check for any pipes that will be fully disabled ... */
8714 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8715 base.head) {
8716 bool used = false;
22fd0fab 8717
e2e1ed41
DV		 8718 /* Don't try to disable disabled crtcs. */
8719 if (!intel_crtc->base.enabled)
8720 continue;
7e7d76c3 8721
e2e1ed41
DV		 8722 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8723 base.head) {
8724 if (encoder->new_crtc == intel_crtc)
8725 used = true;
8726 }
8727
8728 if (!used)
8729 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8730 }
8731
e2e1ed41
DV		 8732
8733 /* set_mode is also used to update properties on life display pipes. */
8734 intel_crtc = to_intel_crtc(crtc);
8735 if (crtc->enabled)
8736 *prepare_pipes |= 1 << intel_crtc->pipe;
8737
b6c5164d
DV		 8738 /*
8739 * For simplicity do a full modeset on any pipe where the output routing
8740 * changed. We could be more clever, but that would require us to be
8741 * more careful with calling the relevant encoder->mode_set functions.
8742 */
e2e1ed41
DV		 8743 if (*prepare_pipes)
8744 *modeset_pipes = *prepare_pipes;
8745
8746 /* ... and mask these out. */
8747 *modeset_pipes &= ~(*disable_pipes);
8748 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8749
8750 /*
8751 * HACK: We don't (yet) fully support global modesets. intel_set_config
8752 * obies this rule, but the modeset restore mode of
8753 * intel_modeset_setup_hw_state does not.
8754 */
8755 *modeset_pipes &= 1 << intel_crtc->pipe;
8756 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8757
8758 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8759 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8760}
79e53945 8761
ea9d758d 8762static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8763{
ea9d758d 8764 struct drm_encoder *encoder;
f6e5b160 8765 struct drm_device *dev = crtc->dev;
f6e5b160 8766
ea9d758d
DV		 8767 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8768 if (encoder->crtc == crtc)
8769 return true;
8770
8771 return false;
8772}
8773
8774static void
8775intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8776{
8777 struct intel_encoder *intel_encoder;
8778 struct intel_crtc *intel_crtc;
8779 struct drm_connector *connector;
8780
8781 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8782 base.head) {
8783 if (!intel_encoder->base.crtc)
8784 continue;
8785
8786 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8787
8788 if (prepare_pipes & (1 << intel_crtc->pipe))
8789 intel_encoder->connectors_active = false;
8790 }
8791
8792 intel_modeset_commit_output_state(dev);
8793
8794 /* Update computed state. */
8795 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8796 base.head) {
8797 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8798 }
8799
8800 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8801 if (!connector->encoder || !connector->encoder->crtc)
8802 continue;
8803
8804 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8805
8806 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8807 struct drm_property *dpms_property =
8808 dev->mode_config.dpms_property;
8809
ea9d758d 8810 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8811 drm_object_property_set_value(&connector->base,
68d34720
DV		 8812 dpms_property,
8813 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8814
8815 intel_encoder = to_intel_encoder(connector->encoder);
8816 intel_encoder->connectors_active = true;
8817 }
8818 }
8819
8820}
8821
3bd26263 8822static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 8823{
3bd26263 8824 int diff;
f1f644dc
JB		 8825
8826 if (clock1 == clock2)
8827 return true;
8828
8829 if (!clock1 || !clock2)
8830 return false;
8831
8832 diff = abs(clock1 - clock2);
8833
8834 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8835 return true;
8836
8837 return false;
8838}
8839
25c5b266
DV		 8840#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8841 list_for_each_entry((intel_crtc), \
8842 &(dev)->mode_config.crtc_list, \
8843 base.head) \
0973f18f 8844 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8845
0e8ffe1b 8846static bool
2fa2fe9a
DV		 8847intel_pipe_config_compare(struct drm_device *dev,
8848 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8849 struct intel_crtc_config *pipe_config)
8850{
66e985c0
DV		 8851#define PIPE_CONF_CHECK_X(name) \
8852 if (current_config->name != pipe_config->name) { \
8853 DRM_ERROR("mismatch in " #name " " \
8854 "(expected 0x%08x, found 0x%08x)\n", \
8855 current_config->name, \
8856 pipe_config->name); \
8857 return false; \
8858 }
8859
08a24034
DV		 8860#define PIPE_CONF_CHECK_I(name) \
8861 if (current_config->name != pipe_config->name) { \
8862 DRM_ERROR("mismatch in " #name " " \
8863 "(expected %i, found %i)\n", \
8864 current_config->name, \
8865 pipe_config->name); \
8866 return false; \
88adfff1
DV		 8867 }
8868
1bd1bd80
DV		 8869#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8870 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8871 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8872 "(expected %i, found %i)\n", \
8873 current_config->name & (mask), \
8874 pipe_config->name & (mask)); \
8875 return false; \
8876 }
8877
5e550656
VS		 8878#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8879 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8880 DRM_ERROR("mismatch in " #name " " \
8881 "(expected %i, found %i)\n", \
8882 current_config->name, \
8883 pipe_config->name); \
8884 return false; \
8885 }
8886
bb760063
DV		 8887#define PIPE_CONF_QUIRK(quirk) \
8888 ((current_config->quirks | pipe_config->quirks) & (quirk))
8889
eccb140b
DV		 8890 PIPE_CONF_CHECK_I(cpu_transcoder);
8891
08a24034
DV		 8892 PIPE_CONF_CHECK_I(has_pch_encoder);
8893 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8894 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8895 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8896 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8897 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8898 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8899
eb14cb74
VS		 8900 PIPE_CONF_CHECK_I(has_dp_encoder);
8901 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8902 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8903 PIPE_CONF_CHECK_I(dp_m_n.link_m);
8904 PIPE_CONF_CHECK_I(dp_m_n.link_n);
8905 PIPE_CONF_CHECK_I(dp_m_n.tu);
8906
1bd1bd80
DV		 8907 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8908 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8909 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8910 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8911 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8912 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8913
8914 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8915 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8916 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8917 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8918 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8919 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8920
c93f54cf 8921 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8922
1bd1bd80
DV		 8923 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8924 DRM_MODE_FLAG_INTERLACE);
8925
bb760063
DV		 8926 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8927 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8928 DRM_MODE_FLAG_PHSYNC);
8929 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8930 DRM_MODE_FLAG_NHSYNC);
8931 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8932 DRM_MODE_FLAG_PVSYNC);
8933 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8934 DRM_MODE_FLAG_NVSYNC);
8935 }
045ac3b5 8936
37327abd
VS		 8937 PIPE_CONF_CHECK_I(pipe_src_w);
8938 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 8939
2fa2fe9a
DV		 8940 PIPE_CONF_CHECK_I(gmch_pfit.control);
8941 /* pfit ratios are autocomputed by the hw on gen4+ */
8942 if (INTEL_INFO(dev)->gen < 4)
8943 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8944 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
fd4daa9c
CW		 8945 PIPE_CONF_CHECK_I(pch_pfit.enabled);
8946 if (current_config->pch_pfit.enabled) {
8947 PIPE_CONF_CHECK_I(pch_pfit.pos);
8948 PIPE_CONF_CHECK_I(pch_pfit.size);
8949 }
2fa2fe9a 8950
42db64ef
PZ		 8951 PIPE_CONF_CHECK_I(ips_enabled);
8952
282740f7
VS		 8953 PIPE_CONF_CHECK_I(double_wide);
8954
c0d43d62 8955 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8956 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8957 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8958 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8959 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8960
42571aef
VS		 8961 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8962 PIPE_CONF_CHECK_I(pipe_bpp);
8963
d71b8d4a 8964 if (!IS_HASWELL(dev)) {
241bfc38 8965 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
d71b8d4a
VS		 8966 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8967 }
5e550656 8968
66e985c0 8969#undef PIPE_CONF_CHECK_X
08a24034 8970#undef PIPE_CONF_CHECK_I
1bd1bd80 8971#undef PIPE_CONF_CHECK_FLAGS
5e550656 8972#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 8973#undef PIPE_CONF_QUIRK
88adfff1 8974
0e8ffe1b
DV		 8975 return true;
8976}
8977
91d1b4bd
DV		 8978static void
8979check_connector_state(struct drm_device *dev)
8af6cf88 8980{
8af6cf88
DV		 8981 struct intel_connector *connector;
8982
8983 list_for_each_entry(connector, &dev->mode_config.connector_list,
8984 base.head) {
8985 /* This also checks the encoder/connector hw state with the
8986 * ->get_hw_state callbacks. */
8987 intel_connector_check_state(connector);
8988
8989 WARN(&connector->new_encoder->base != connector->base.encoder,
8990 "connector's staged encoder doesn't match current encoder\n");
8991 }
91d1b4bd
DV		 8992}
8993
8994static void
8995check_encoder_state(struct drm_device *dev)
8996{
8997 struct intel_encoder *encoder;
8998 struct intel_connector *connector;
8af6cf88
DV		 8999
9000 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9001 base.head) {
9002 bool enabled = false;
9003 bool active = false;
9004 enum pipe pipe, tracked_pipe;
9005
9006 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
9007 encoder->base.base.id,
9008 drm_get_encoder_name(&encoder->base));
9009
9010 WARN(&encoder->new_crtc->base != encoder->base.crtc,
9011 "encoder's stage crtc doesn't match current crtc\n");
9012 WARN(encoder->connectors_active && !encoder->base.crtc,
9013 "encoder's active_connectors set, but no crtc\n");
9014
9015 list_for_each_entry(connector, &dev->mode_config.connector_list,
9016 base.head) {
9017 if (connector->base.encoder != &encoder->base)
9018 continue;
9019 enabled = true;
9020 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
9021 active = true;
9022 }
9023 WARN(!!encoder->base.crtc != enabled,
9024 "encoder's enabled state mismatch "
9025 "(expected %i, found %i)\n",
9026 !!encoder->base.crtc, enabled);
9027 WARN(active && !encoder->base.crtc,
9028 "active encoder with no crtc\n");
9029
9030 WARN(encoder->connectors_active != active,
9031 "encoder's computed active state doesn't match tracked active state "
9032 "(expected %i, found %i)\n", active, encoder->connectors_active);
9033
9034 active = encoder->get_hw_state(encoder, &pipe);
9035 WARN(active != encoder->connectors_active,
9036 "encoder's hw state doesn't match sw tracking "
9037 "(expected %i, found %i)\n",
9038 encoder->connectors_active, active);
9039
9040 if (!encoder->base.crtc)
9041 continue;
9042
9043 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9044 WARN(active && pipe != tracked_pipe,
9045 "active encoder's pipe doesn't match"
9046 "(expected %i, found %i)\n",
9047 tracked_pipe, pipe);
9048
9049 }
91d1b4bd
DV		 9050}
9051
9052static void
9053check_crtc_state(struct drm_device *dev)
9054{
9055 drm_i915_private_t *dev_priv = dev->dev_private;
9056 struct intel_crtc *crtc;
9057 struct intel_encoder *encoder;
9058 struct intel_crtc_config pipe_config;
8af6cf88
DV		 9059
9060 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9061 base.head) {
9062 bool enabled = false;
9063 bool active = false;
9064
045ac3b5
JB		 9065 memset(&pipe_config, 0, sizeof(pipe_config));
9066
8af6cf88
DV		 9067 DRM_DEBUG_KMS("[CRTC:%d]\n",
9068 crtc->base.base.id);
9069
9070 WARN(crtc->active && !crtc->base.enabled,
9071 "active crtc, but not enabled in sw tracking\n");
9072
9073 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9074 base.head) {
9075 if (encoder->base.crtc != &crtc->base)
9076 continue;
9077 enabled = true;
9078 if (encoder->connectors_active)
9079 active = true;
9080 }
6c49f241 9081
8af6cf88
DV		 9082 WARN(active != crtc->active,
9083 "crtc's computed active state doesn't match tracked active state "
9084 "(expected %i, found %i)\n", active, crtc->active);
9085 WARN(enabled != crtc->base.enabled,
9086 "crtc's computed enabled state doesn't match tracked enabled state "
9087 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9088
0e8ffe1b
DV		 9089 active = dev_priv->display.get_pipe_config(crtc,
9090 &pipe_config);
d62cf62a
DV		 9091
9092 /* hw state is inconsistent with the pipe A quirk */
9093 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9094 active = crtc->active;
9095
6c49f241
DV		 9096 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9097 base.head) {
3eaba51c 9098 enum pipe pipe;
6c49f241
DV		 9099 if (encoder->base.crtc != &crtc->base)
9100 continue;
3eaba51c
VS		 9101 if (encoder->get_config &&
9102 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 9103 encoder->get_config(encoder, &pipe_config);
9104 }
9105
0e8ffe1b
DV		 9106 WARN(crtc->active != active,
9107 "crtc active state doesn't match with hw state "
9108 "(expected %i, found %i)\n", crtc->active, active);
9109
c0b03411
DV		 9110 if (active &&
9111 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9112 WARN(1, "pipe state doesn't match!\n");
9113 intel_dump_pipe_config(crtc, &pipe_config,
9114 "[hw state]");
9115 intel_dump_pipe_config(crtc, &crtc->config,
9116 "[sw state]");
9117 }
8af6cf88
DV		 9118 }
9119}
9120
91d1b4bd
DV		 9121static void
9122check_shared_dpll_state(struct drm_device *dev)
9123{
9124 drm_i915_private_t *dev_priv = dev->dev_private;
9125 struct intel_crtc *crtc;
9126 struct intel_dpll_hw_state dpll_hw_state;
9127 int i;
5358901f
DV		 9128
9129 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9130 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9131 int enabled_crtcs = 0, active_crtcs = 0;
9132 bool active;
9133
9134 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9135
9136 DRM_DEBUG_KMS("%s\n", pll->name);
9137
9138 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9139
9140 WARN(pll->active > pll->refcount,
9141 "more active pll users than references: %i vs %i\n",
9142 pll->active, pll->refcount);
9143 WARN(pll->active && !pll->on,
9144 "pll in active use but not on in sw tracking\n");
35c95375
DV		 9145 WARN(pll->on && !pll->active,
9146 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 9147 WARN(pll->on != active,
9148 "pll on state mismatch (expected %i, found %i)\n",
9149 pll->on, active);
9150
9151 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9152 base.head) {
9153 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9154 enabled_crtcs++;
9155 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9156 active_crtcs++;
9157 }
9158 WARN(pll->active != active_crtcs,
9159 "pll active crtcs mismatch (expected %i, found %i)\n",
9160 pll->active, active_crtcs);
9161 WARN(pll->refcount != enabled_crtcs,
9162 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9163 pll->refcount, enabled_crtcs);
66e985c0
DV		 9164
9165 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9166 sizeof(dpll_hw_state)),
9167 "pll hw state mismatch\n");
5358901f 9168 }
8af6cf88
DV		 9169}
9170
91d1b4bd
DV		 9171void
9172intel_modeset_check_state(struct drm_device *dev)
9173{
9174 check_connector_state(dev);
9175 check_encoder_state(dev);
9176 check_crtc_state(dev);
9177 check_shared_dpll_state(dev);
9178}
9179
18442d08
VS		 9180void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9181 int dotclock)
9182{
9183 /*
9184 * FDI already provided one idea for the dotclock.
9185 * Yell if the encoder disagrees.
9186 */
241bfc38 9187 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
18442d08 9188 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
241bfc38 9189 pipe_config->adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 9190}
9191
f30da187
DV		 9192static int __intel_set_mode(struct drm_crtc *crtc,
9193 struct drm_display_mode *mode,
9194 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 9195{
9196 struct drm_device *dev = crtc->dev;
dbf2b54e 9197 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 9198 struct drm_display_mode *saved_mode, *saved_hwmode;
9199 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 9200 struct intel_crtc *intel_crtc;
9201 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 9202 int ret = 0;
a6778b3c 9203
a1e22653 9204 saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 9205 if (!saved_mode)
9206 return -ENOMEM;
3ac18232 9207 saved_hwmode = saved_mode + 1;
a6778b3c 9208
e2e1ed41 9209 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 9210 &prepare_pipes, &disable_pipes);
9211
3ac18232
TG		 9212 *saved_hwmode = crtc->hwmode;
9213 *saved_mode = crtc->mode;
a6778b3c 9214
25c5b266
DV		 9215 /* Hack: Because we don't (yet) support global modeset on multiple
9216 * crtcs, we don't keep track of the new mode for more than one crtc.
9217 * Hence simply check whether any bit is set in modeset_pipes in all the
9218 * pieces of code that are not yet converted to deal with mutliple crtcs
9219 * changing their mode at the same time. */
25c5b266 9220 if (modeset_pipes) {
4e53c2e0 9221 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 9222 if (IS_ERR(pipe_config)) {
9223 ret = PTR_ERR(pipe_config);
9224 pipe_config = NULL;
9225
3ac18232 9226 goto out;
25c5b266 9227 }
c0b03411
DV		 9228 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9229 "[modeset]");
25c5b266 9230 }
a6778b3c 9231
460da916
DV		 9232 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9233 intel_crtc_disable(&intel_crtc->base);
9234
ea9d758d
DV		 9235 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9236 if (intel_crtc->base.enabled)
9237 dev_priv->display.crtc_disable(&intel_crtc->base);
9238 }
a6778b3c 9239
6c4c86f5
DV		 9240 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9241 * to set it here already despite that we pass it down the callchain.
f6e5b160 9242 */
b8cecdf5 9243 if (modeset_pipes) {
25c5b266 9244 crtc->mode = *mode;
b8cecdf5
DV		 9245 /* mode_set/enable/disable functions rely on a correct pipe
9246 * config. */
9247 to_intel_crtc(crtc)->config = *pipe_config;
9248 }
7758a113 9249
ea9d758d
DV		 9250 /* Only after disabling all output pipelines that will be changed can we
9251 * update the the output configuration. */
9252 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 9253
47fab737
DV		 9254 if (dev_priv->display.modeset_global_resources)
9255 dev_priv->display.modeset_global_resources(dev);
9256
a6778b3c
DV		 9257 /* Set up the DPLL and any encoders state that needs to adjust or depend
9258 * on the DPLL.
f6e5b160 9259 */
25c5b266 9260 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 9261 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 9262 x, y, fb);
9263 if (ret)
9264 goto done;
a6778b3c
DV		 9265 }
9266
9267 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 9268 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9269 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 9270
25c5b266
DV		 9271 if (modeset_pipes) {
9272 /* Store real post-adjustment hardware mode. */
b8cecdf5 9273 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 9274
25c5b266
DV		 9275 /* Calculate and store various constants which
9276 * are later needed by vblank and swap-completion
9277 * timestamping. They are derived from true hwmode.
9278 */
9279 drm_calc_timestamping_constants(crtc);
9280 }
a6778b3c
DV		 9281
9282 /* FIXME: add subpixel order */
9283done:
c0c36b94 9284 if (ret && crtc->enabled) {
3ac18232
TG		 9285 crtc->hwmode = *saved_hwmode;
9286 crtc->mode = *saved_mode;
a6778b3c
DV		 9287 }
9288
3ac18232 9289out:
b8cecdf5 9290 kfree(pipe_config);
3ac18232 9291 kfree(saved_mode);
a6778b3c 9292 return ret;
f6e5b160
CW		 9293}
9294
e7457a9a
DL		 9295static int intel_set_mode(struct drm_crtc *crtc,
9296 struct drm_display_mode *mode,
9297 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 9298{
9299 int ret;
9300
9301 ret = __intel_set_mode(crtc, mode, x, y, fb);
9302
9303 if (ret == 0)
9304 intel_modeset_check_state(crtc->dev);
9305
9306 return ret;
9307}
9308
c0c36b94
CW		 9309void intel_crtc_restore_mode(struct drm_crtc *crtc)
9310{
9311 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9312}
9313
25c5b266
DV		 9314#undef for_each_intel_crtc_masked
9315
d9e55608
DV		 9316static void intel_set_config_free(struct intel_set_config *config)
9317{
9318 if (!config)
9319 return;
9320
1aa4b628
DV		 9321 kfree(config->save_connector_encoders);
9322 kfree(config->save_encoder_crtcs);
d9e55608
DV		 9323 kfree(config);
9324}
9325
85f9eb71
DV		 9326static int intel_set_config_save_state(struct drm_device *dev,
9327 struct intel_set_config *config)
9328{
85f9eb71
DV		 9329 struct drm_encoder *encoder;
9330 struct drm_connector *connector;
9331 int count;
9332
1aa4b628
DV		 9333 config->save_encoder_crtcs =
9334 kcalloc(dev->mode_config.num_encoder,
9335 sizeof(struct drm_crtc *), GFP_KERNEL);
9336 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9337 return -ENOMEM;
9338
1aa4b628
DV		 9339 config->save_connector_encoders =
9340 kcalloc(dev->mode_config.num_connector,
9341 sizeof(struct drm_encoder *), GFP_KERNEL);
9342 if (!config->save_connector_encoders)
85f9eb71
DV		 9343 return -ENOMEM;
9344
9345 /* Copy data. Note that driver private data is not affected.
9346 * Should anything bad happen only the expected state is
9347 * restored, not the drivers personal bookkeeping.
9348 */
85f9eb71
DV		 9349 count = 0;
9350 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9351 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9352 }
9353
9354 count = 0;
9355 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9356 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9357 }
9358
9359 return 0;
9360}
9361
9362static void intel_set_config_restore_state(struct drm_device *dev,
9363 struct intel_set_config *config)
9364{
9a935856
DV		 9365 struct intel_encoder *encoder;
9366 struct intel_connector *connector;
85f9eb71
DV		 9367 int count;
9368
85f9eb71 9369 count = 0;
9a935856
DV		 9370 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9371 encoder->new_crtc =
9372 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9373 }
9374
9375 count = 0;
9a935856
DV		 9376 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9377 connector->new_encoder =
9378 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9379 }
9380}
9381
e3de42b6 9382static bool
2e57f47d 9383is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9384{
9385 int i;
9386
2e57f47d
CW		 9387 if (set->num_connectors == 0)
9388 return false;
9389
9390 if (WARN_ON(set->connectors == NULL))
9391 return false;
9392
9393 for (i = 0; i < set->num_connectors; i++)
9394 if (set->connectors[i]->encoder &&
9395 set->connectors[i]->encoder->crtc == set->crtc &&
9396 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9397 return true;
9398
9399 return false;
9400}
9401
5e2b584e
DV		 9402static void
9403intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9404 struct intel_set_config *config)
9405{
9406
9407 /* We should be able to check here if the fb has the same properties
9408 * and then just flip_or_move it */
2e57f47d
CW		 9409 if (is_crtc_connector_off(set)) {
9410 config->mode_changed = true;
e3de42b6 9411 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9412 /* If we have no fb then treat it as a full mode set */
9413 if (set->crtc->fb == NULL) {
319d9827
JB		 9414 struct intel_crtc *intel_crtc =
9415 to_intel_crtc(set->crtc);
9416
9417 if (intel_crtc->active && i915_fastboot) {
9418 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9419 config->fb_changed = true;
9420 } else {
9421 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9422 config->mode_changed = true;
9423 }
5e2b584e
DV		 9424 } else if (set->fb == NULL) {
9425 config->mode_changed = true;
72f4901e
DV		 9426 } else if (set->fb->pixel_format !=
9427 set->crtc->fb->pixel_format) {
5e2b584e 9428 config->mode_changed = true;
e3de42b6 9429 } else {
5e2b584e 9430 config->fb_changed = true;
e3de42b6 9431 }
5e2b584e
DV		 9432 }
9433
835c5873 9434 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9435 config->fb_changed = true;
9436
9437 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9438 DRM_DEBUG_KMS("modes are different, full mode set\n");
9439 drm_mode_debug_printmodeline(&set->crtc->mode);
9440 drm_mode_debug_printmodeline(set->mode);
9441 config->mode_changed = true;
9442 }
a1d95703
CW		 9443
9444 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9445 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9446}
9447
2e431051 9448static int
9a935856
DV		 9449intel_modeset_stage_output_state(struct drm_device *dev,
9450 struct drm_mode_set *set,
9451 struct intel_set_config *config)
50f56119 9452{
85f9eb71 9453 struct drm_crtc *new_crtc;
9a935856
DV		 9454 struct intel_connector *connector;
9455 struct intel_encoder *encoder;
f3f08572 9456 int ro;
50f56119 9457
9abdda74 9458 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9459 * of connectors. For paranoia, double-check this. */
9460 WARN_ON(!set->fb && (set->num_connectors != 0));
9461 WARN_ON(set->fb && (set->num_connectors == 0));
9462
9a935856
DV		 9463 list_for_each_entry(connector, &dev->mode_config.connector_list,
9464 base.head) {
9465 /* Otherwise traverse passed in connector list and get encoders
9466 * for them. */
50f56119 9467 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9468 if (set->connectors[ro] == &connector->base) {
9469 connector->new_encoder = connector->encoder;
50f56119
DV		 9470 break;
9471 }
9472 }
9473
9a935856
DV		 9474 /* If we disable the crtc, disable all its connectors. Also, if
9475 * the connector is on the changing crtc but not on the new
9476 * connector list, disable it. */
9477 if ((!set->fb || ro == set->num_connectors) &&
9478 connector->base.encoder &&
9479 connector->base.encoder->crtc == set->crtc) {
9480 connector->new_encoder = NULL;
9481
9482 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9483 connector->base.base.id,
9484 drm_get_connector_name(&connector->base));
9485 }
9486
9487
9488 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9489 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9490 config->mode_changed = true;
50f56119
DV		 9491 }
9492 }
9a935856 9493 /* connector->new_encoder is now updated for all connectors. */
50f56119 9494
9a935856 9495 /* Update crtc of enabled connectors. */
9a935856
DV		 9496 list_for_each_entry(connector, &dev->mode_config.connector_list,
9497 base.head) {
9498 if (!connector->new_encoder)
50f56119
DV		 9499 continue;
9500
9a935856 9501 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9502
9503 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9504 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9505 new_crtc = set->crtc;
9506 }
9507
9508 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9509 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9510 new_crtc)) {
5e2b584e 9511 return -EINVAL;
50f56119 9512 }
9a935856
DV		 9513 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9514
9515 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9516 connector->base.base.id,
9517 drm_get_connector_name(&connector->base),
9518 new_crtc->base.id);
9519 }
9520
9521 /* Check for any encoders that needs to be disabled. */
9522 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9523 base.head) {
9524 list_for_each_entry(connector,
9525 &dev->mode_config.connector_list,
9526 base.head) {
9527 if (connector->new_encoder == encoder) {
9528 WARN_ON(!connector->new_encoder->new_crtc);
9529
9530 goto next_encoder;
9531 }
9532 }
9533 encoder->new_crtc = NULL;
9534next_encoder:
9535 /* Only now check for crtc changes so we don't miss encoders
9536 * that will be disabled. */
9537 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9538 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9539 config->mode_changed = true;
50f56119
DV		 9540 }
9541 }
9a935856 9542 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9543
2e431051
DV		 9544 return 0;
9545}
9546
9547static int intel_crtc_set_config(struct drm_mode_set *set)
9548{
9549 struct drm_device *dev;
2e431051
DV		 9550 struct drm_mode_set save_set;
9551 struct intel_set_config *config;
9552 int ret;
2e431051 9553
8d3e375e
DV		 9554 BUG_ON(!set);
9555 BUG_ON(!set->crtc);
9556 BUG_ON(!set->crtc->helper_private);
2e431051 9557
7e53f3a4
DV		 9558 /* Enforce sane interface api - has been abused by the fb helper. */
9559 BUG_ON(!set->mode && set->fb);
9560 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9561
2e431051
DV		 9562 if (set->fb) {
9563 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9564 set->crtc->base.id, set->fb->base.id,
9565 (int)set->num_connectors, set->x, set->y);
9566 } else {
9567 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9568 }
9569
9570 dev = set->crtc->dev;
9571
9572 ret = -ENOMEM;
9573 config = kzalloc(sizeof(*config), GFP_KERNEL);
9574 if (!config)
9575 goto out_config;
9576
9577 ret = intel_set_config_save_state(dev, config);
9578 if (ret)
9579 goto out_config;
9580
9581 save_set.crtc = set->crtc;
9582 save_set.mode = &set->crtc->mode;
9583 save_set.x = set->crtc->x;
9584 save_set.y = set->crtc->y;
9585 save_set.fb = set->crtc->fb;
9586
9587 /* Compute whether we need a full modeset, only an fb base update or no
9588 * change at all. In the future we might also check whether only the
9589 * mode changed, e.g. for LVDS where we only change the panel fitter in
9590 * such cases. */
9591 intel_set_config_compute_mode_changes(set, config);
9592
9a935856 9593 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9594 if (ret)
9595 goto fail;
9596
5e2b584e 9597 if (config->mode_changed) {
c0c36b94
CW		 9598 ret = intel_set_mode(set->crtc, set->mode,
9599 set->x, set->y, set->fb);
5e2b584e 9600 } else if (config->fb_changed) {
4878cae2
VS		 9601 intel_crtc_wait_for_pending_flips(set->crtc);
9602
4f660f49 9603 ret = intel_pipe_set_base(set->crtc,
94352cf9 9604 set->x, set->y, set->fb);
50f56119
DV		 9605 }
9606
2d05eae1 9607 if (ret) {
bf67dfeb
DV		 9608 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9609 set->crtc->base.id, ret);
50f56119 9610fail:
2d05eae1 9611 intel_set_config_restore_state(dev, config);
50f56119 9612
2d05eae1
CW		 9613 /* Try to restore the config */
9614 if (config->mode_changed &&
9615 intel_set_mode(save_set.crtc, save_set.mode,
9616 save_set.x, save_set.y, save_set.fb))
9617 DRM_ERROR("failed to restore config after modeset failure\n");
9618 }
50f56119 9619
d9e55608
DV		 9620out_config:
9621 intel_set_config_free(config);
50f56119
DV		 9622 return ret;
9623}
f6e5b160
CW		 9624
9625static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9626 .cursor_set = intel_crtc_cursor_set,
9627 .cursor_move = intel_crtc_cursor_move,
9628 .gamma_set = intel_crtc_gamma_set,
50f56119 9629 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9630 .destroy = intel_crtc_destroy,
9631 .page_flip = intel_crtc_page_flip,
9632};
9633
79f689aa
PZ		 9634static void intel_cpu_pll_init(struct drm_device *dev)
9635{
affa9354 9636 if (HAS_DDI(dev))
79f689aa
PZ		 9637 intel_ddi_pll_init(dev);
9638}
9639
5358901f
DV		 9640static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9641 struct intel_shared_dpll *pll,
9642 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9643{
5358901f 9644 uint32_t val;
ee7b9f93 9645
5358901f 9646 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9647 hw_state->dpll = val;
9648 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9649 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9650
9651 return val & DPLL_VCO_ENABLE;
9652}
9653
15bdd4cf
DV		 9654static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9655 struct intel_shared_dpll *pll)
9656{
9657 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9658 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9659}
9660
e7b903d2
DV		 9661static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9662 struct intel_shared_dpll *pll)
9663{
e7b903d2
DV		 9664 /* PCH refclock must be enabled first */
9665 assert_pch_refclk_enabled(dev_priv);
9666
15bdd4cf
DV		 9667 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9668
9669 /* Wait for the clocks to stabilize. */
9670 POSTING_READ(PCH_DPLL(pll->id));
9671 udelay(150);
9672
9673 /* The pixel multiplier can only be updated once the
9674 * DPLL is enabled and the clocks are stable.
9675 *
9676 * So write it again.
9677 */
9678 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9679 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9680 udelay(200);
9681}
9682
9683static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9684 struct intel_shared_dpll *pll)
9685{
9686 struct drm_device *dev = dev_priv->dev;
9687 struct intel_crtc *crtc;
e7b903d2
DV		 9688
9689 /* Make sure no transcoder isn't still depending on us. */
9690 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9691 if (intel_crtc_to_shared_dpll(crtc) == pll)
9692 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9693 }
9694
15bdd4cf
DV		 9695 I915_WRITE(PCH_DPLL(pll->id), 0);
9696 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9697 udelay(200);
9698}
9699
46edb027
DV		 9700static char *ibx_pch_dpll_names[] = {
9701 "PCH DPLL A",
9702 "PCH DPLL B",
9703};
9704
7c74ade1 9705static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9706{
e7b903d2 9707 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9708 int i;
9709
7c74ade1 9710 dev_priv->num_shared_dpll = 2;
ee7b9f93 9711
e72f9fbf 9712 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9713 dev_priv->shared_dplls[i].id = i;
9714 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9715 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9716 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9717 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9718 dev_priv->shared_dplls[i].get_hw_state =
9719 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9720 }
9721}
9722
7c74ade1
DV		 9723static void intel_shared_dpll_init(struct drm_device *dev)
9724{
e7b903d2 9725 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9726
9727 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9728 ibx_pch_dpll_init(dev);
9729 else
9730 dev_priv->num_shared_dpll = 0;
9731
9732 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9733 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9734 dev_priv->num_shared_dpll);
9735}
9736
b358d0a6 9737static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9738{
22fd0fab 9739 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9740 struct intel_crtc *intel_crtc;
9741 int i;
9742
955382f3 9743 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 9744 if (intel_crtc == NULL)
9745 return;
9746
9747 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9748
9749 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9750 for (i = 0; i < 256; i++) {
9751 intel_crtc->lut_r[i] = i;
9752 intel_crtc->lut_g[i] = i;
9753 intel_crtc->lut_b[i] = i;
9754 }
9755
80824003
JB		 9756 /* Swap pipes & planes for FBC on pre-965 */
9757 intel_crtc->pipe = pipe;
9758 intel_crtc->plane = pipe;
e2e767ab 9759 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9760 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9761 intel_crtc->plane = !pipe;
80824003
JB		 9762 }
9763
22fd0fab
JB		 9764 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9765 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9766 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9767 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9768
79e53945 9769 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9770}
9771
08d7b3d1 9772int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9773 struct drm_file *file)
08d7b3d1 9774{
08d7b3d1 9775 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9776 struct drm_mode_object *drmmode_obj;
9777 struct intel_crtc *crtc;
08d7b3d1 9778
1cff8f6b
DV		 9779 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9780 return -ENODEV;
08d7b3d1 9781
c05422d5
DV		 9782 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9783 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9784
c05422d5 9785 if (!drmmode_obj) {
08d7b3d1
CW		 9786 DRM_ERROR("no such CRTC id\n");
9787 return -EINVAL;
9788 }
9789
c05422d5
DV		 9790 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9791 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9792
c05422d5 9793 return 0;
08d7b3d1
CW		 9794}
9795
66a9278e 9796static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9797{
66a9278e
DV		 9798 struct drm_device *dev = encoder->base.dev;
9799 struct intel_encoder *source_encoder;
79e53945 9800 int index_mask = 0;
79e53945
JB		 9801 int entry = 0;
9802
66a9278e
DV		 9803 list_for_each_entry(source_encoder,
9804 &dev->mode_config.encoder_list, base.head) {
9805
9806 if (encoder == source_encoder)
79e53945 9807 index_mask |= (1 << entry);
66a9278e
DV		 9808
9809 /* Intel hw has only one MUX where enocoders could be cloned. */
9810 if (encoder->cloneable && source_encoder->cloneable)
9811 index_mask |= (1 << entry);
9812
79e53945
JB		 9813 entry++;
9814 }
4ef69c7a 9815
79e53945
JB		 9816 return index_mask;
9817}
9818
4d302442
CW		 9819static bool has_edp_a(struct drm_device *dev)
9820{
9821 struct drm_i915_private *dev_priv = dev->dev_private;
9822
9823 if (!IS_MOBILE(dev))
9824 return false;
9825
9826 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9827 return false;
9828
9829 if (IS_GEN5(dev) &&
9830 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9831 return false;
9832
9833 return true;
9834}
9835
79e53945
JB		 9836static void intel_setup_outputs(struct drm_device *dev)
9837{
725e30ad 9838 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9839 struct intel_encoder *encoder;
cb0953d7 9840 bool dpd_is_edp = false;
79e53945 9841
c9093354 9842 intel_lvds_init(dev);
79e53945 9843
c40c0f5b 9844 if (!IS_ULT(dev))
79935fca 9845 intel_crt_init(dev);
cb0953d7 9846
affa9354 9847 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9848 int found;
9849
9850 /* Haswell uses DDI functions to detect digital outputs */
9851 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9852 /* DDI A only supports eDP */
9853 if (found)
9854 intel_ddi_init(dev, PORT_A);
9855
9856 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9857 * register */
9858 found = I915_READ(SFUSE_STRAP);
9859
9860 if (found & SFUSE_STRAP_DDIB_DETECTED)
9861 intel_ddi_init(dev, PORT_B);
9862 if (found & SFUSE_STRAP_DDIC_DETECTED)
9863 intel_ddi_init(dev, PORT_C);
9864 if (found & SFUSE_STRAP_DDID_DETECTED)
9865 intel_ddi_init(dev, PORT_D);
9866 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9867 int found;
270b3042
DV		 9868 dpd_is_edp = intel_dpd_is_edp(dev);
9869
9870 if (has_edp_a(dev))
9871 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9872
dc0fa718 9873 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9874 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9875 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9876 if (!found)
e2debe91 9877 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9878 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9879 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9880 }
9881
dc0fa718 9882 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9883 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9884
dc0fa718 9885 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9886 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9887
5eb08b69 9888 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9889 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9890
270b3042 9891 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9892 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9893 } else if (IS_VALLEYVIEW(dev)) {
585a94b8
AB		 9894 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
9895 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9896 PORT_B);
9897 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9898 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
9899 }
9900
6f6005a5
JB		 9901 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9902 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9903 PORT_C);
9904 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9905 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9906 PORT_C);
9907 }
19c03924 9908
3cfca973 9909 intel_dsi_init(dev);
103a196f 9910 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9911 bool found = false;
7d57382e 9912
e2debe91 9913 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9914 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9915 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9916 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9917 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9918 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9919 }
27185ae1 9920
e7281eab 9921 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9922 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9923 }
13520b05
KH		 9924
9925 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9926
e2debe91 9927 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9928 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9929 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9930 }
27185ae1 9931
e2debe91 9932 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9933
b01f2c3a
JB		 9934 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9935 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9936 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9937 }
e7281eab 9938 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9939 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9940 }
27185ae1 9941
b01f2c3a 9942 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9943 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9944 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9945 } else if (IS_GEN2(dev))
79e53945
JB		 9946 intel_dvo_init(dev);
9947
103a196f 9948 if (SUPPORTS_TV(dev))
79e53945
JB		 9949 intel_tv_init(dev);
9950
4ef69c7a
CW		 9951 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9952 encoder->base.possible_crtcs = encoder->crtc_mask;
9953 encoder->base.possible_clones =
66a9278e 9954 intel_encoder_clones(encoder);
79e53945 9955 }
47356eb6 9956
dde86e2d 9957 intel_init_pch_refclk(dev);
270b3042
DV		 9958
9959 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9960}
9961
ddfe1567
CW		 9962void intel_framebuffer_fini(struct intel_framebuffer *fb)
9963{
9964 drm_framebuffer_cleanup(&fb->base);
80075d49 9965 WARN_ON(!fb->obj->framebuffer_references--);
ddfe1567
CW		 9966 drm_gem_object_unreference_unlocked(&fb->obj->base);
9967}
9968
79e53945
JB		 9969static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9970{
9971 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9972
ddfe1567 9973 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9974 kfree(intel_fb);
9975}
9976
9977static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9978 struct drm_file *file,
79e53945
JB		 9979 unsigned int *handle)
9980{
9981 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9982 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9983
05394f39 9984 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9985}
9986
9987static const struct drm_framebuffer_funcs intel_fb_funcs = {
9988 .destroy = intel_user_framebuffer_destroy,
9989 .create_handle = intel_user_framebuffer_create_handle,
9990};
9991
38651674
DA		 9992int intel_framebuffer_init(struct drm_device *dev,
9993 struct intel_framebuffer *intel_fb,
308e5bcb 9994 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9995 struct drm_i915_gem_object *obj)
79e53945 9996{
53155c0a 9997 int aligned_height, tile_height;
a35cdaa0 9998 int pitch_limit;
79e53945
JB		 9999 int ret;
10000
dd4916c5
DV		 10001 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
10002
c16ed4be
CW		 10003 if (obj->tiling_mode == I915_TILING_Y) {
10004 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 10005 return -EINVAL;
c16ed4be 10006 }
57cd6508 10007
c16ed4be
CW		 10008 if (mode_cmd->pitches[0] & 63) {
10009 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
10010 mode_cmd->pitches[0]);
57cd6508 10011 return -EINVAL;
c16ed4be 10012 }
57cd6508 10013
a35cdaa0
CW		 10014 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
10015 pitch_limit = 32*1024;
10016 } else if (INTEL_INFO(dev)->gen >= 4) {
10017 if (obj->tiling_mode)
10018 pitch_limit = 16*1024;
10019 else
10020 pitch_limit = 32*1024;
10021 } else if (INTEL_INFO(dev)->gen >= 3) {
10022 if (obj->tiling_mode)
10023 pitch_limit = 8*1024;
10024 else
10025 pitch_limit = 16*1024;
10026 } else
10027 /* XXX DSPC is limited to 4k tiled */
10028 pitch_limit = 8*1024;
10029
10030 if (mode_cmd->pitches[0] > pitch_limit) {
10031 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10032 obj->tiling_mode ? "tiled" : "linear",
10033 mode_cmd->pitches[0], pitch_limit);
5d7bd705 10034 return -EINVAL;
c16ed4be 10035 }
5d7bd705
VS		 10036
10037 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 10038 mode_cmd->pitches[0] != obj->stride) {
10039 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10040 mode_cmd->pitches[0], obj->stride);
5d7bd705 10041 return -EINVAL;
c16ed4be 10042 }
5d7bd705 10043
57779d06 10044 /* Reject formats not supported by any plane early. */
308e5bcb 10045 switch (mode_cmd->pixel_format) {
57779d06 10046 case DRM_FORMAT_C8:
04b3924d
VS		 10047 case DRM_FORMAT_RGB565:
10048 case DRM_FORMAT_XRGB8888:
10049 case DRM_FORMAT_ARGB8888:
57779d06
VS		 10050 break;
10051 case DRM_FORMAT_XRGB1555:
10052 case DRM_FORMAT_ARGB1555:
c16ed4be 10053 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 10054 DRM_DEBUG("unsupported pixel format: %s\n",
10055 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10056 return -EINVAL;
c16ed4be 10057 }
57779d06
VS		 10058 break;
10059 case DRM_FORMAT_XBGR8888:
10060 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 10061 case DRM_FORMAT_XRGB2101010:
10062 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 10063 case DRM_FORMAT_XBGR2101010:
10064 case DRM_FORMAT_ABGR2101010:
c16ed4be 10065 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 10066 DRM_DEBUG("unsupported pixel format: %s\n",
10067 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10068 return -EINVAL;
c16ed4be 10069 }
b5626747 10070 break;
04b3924d
VS		 10071 case DRM_FORMAT_YUYV:
10072 case DRM_FORMAT_UYVY:
10073 case DRM_FORMAT_YVYU:
10074 case DRM_FORMAT_VYUY:
c16ed4be 10075 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 10076 DRM_DEBUG("unsupported pixel format: %s\n",
10077 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10078 return -EINVAL;
c16ed4be 10079 }
57cd6508
CW		 10080 break;
10081 default:
4ee62c76
VS		 10082 DRM_DEBUG("unsupported pixel format: %s\n",
10083 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 10084 return -EINVAL;
10085 }
10086
90f9a336
VS		 10087 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10088 if (mode_cmd->offsets[0] != 0)
10089 return -EINVAL;
10090
53155c0a
DV		 10091 tile_height = IS_GEN2(dev) ? 16 : 8;
10092 aligned_height = ALIGN(mode_cmd->height,
10093 obj->tiling_mode ? tile_height : 1);
10094 /* FIXME drm helper for size checks (especially planar formats)? */
10095 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
10096 return -EINVAL;
10097
c7d73f6a
DV		 10098 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10099 intel_fb->obj = obj;
80075d49 10100 intel_fb->obj->framebuffer_references++;
c7d73f6a 10101
79e53945
JB		 10102 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10103 if (ret) {
10104 DRM_ERROR("framebuffer init failed %d\n", ret);
10105 return ret;
10106 }
10107
79e53945
JB		 10108 return 0;
10109}
10110
79e53945
JB		 10111static struct drm_framebuffer *
10112intel_user_framebuffer_create(struct drm_device *dev,
10113 struct drm_file *filp,
308e5bcb 10114 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 10115{
05394f39 10116 struct drm_i915_gem_object *obj;
79e53945 10117
308e5bcb
JB		 10118 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10119 mode_cmd->handles[0]));
c8725226 10120 if (&obj->base == NULL)
cce13ff7 10121 return ERR_PTR(-ENOENT);
79e53945 10122
d2dff872 10123 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 10124}
10125
4520f53a 10126#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 10127static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 10128{
10129}
10130#endif
10131
79e53945 10132static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 10133 .fb_create = intel_user_framebuffer_create,
0632fef6 10134 .output_poll_changed = intel_fbdev_output_poll_changed,
79e53945
JB		 10135};
10136
e70236a8
JB		 10137/* Set up chip specific display functions */
10138static void intel_init_display(struct drm_device *dev)
10139{
10140 struct drm_i915_private *dev_priv = dev->dev_private;
10141
ee9300bb
DV		 10142 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10143 dev_priv->display.find_dpll = g4x_find_best_dpll;
10144 else if (IS_VALLEYVIEW(dev))
10145 dev_priv->display.find_dpll = vlv_find_best_dpll;
10146 else if (IS_PINEVIEW(dev))
10147 dev_priv->display.find_dpll = pnv_find_best_dpll;
10148 else
10149 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10150
affa9354 10151 if (HAS_DDI(dev)) {
0e8ffe1b 10152 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 10153 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 10154 dev_priv->display.crtc_enable = haswell_crtc_enable;
10155 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 10156 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 10157 dev_priv->display.update_plane = ironlake_update_plane;
10158 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 10159 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 10160 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 10161 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10162 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 10163 dev_priv->display.off = ironlake_crtc_off;
17638cd6 10164 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 10165 } else if (IS_VALLEYVIEW(dev)) {
10166 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10167 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10168 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10169 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10170 dev_priv->display.off = i9xx_crtc_off;
10171 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10172 } else {
0e8ffe1b 10173 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 10174 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 10175 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10176 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 10177 dev_priv->display.off = i9xx_crtc_off;
17638cd6 10178 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10179 }
e70236a8 10180
e70236a8 10181 /* Returns the core display clock speed */
25eb05fc
JB		 10182 if (IS_VALLEYVIEW(dev))
10183 dev_priv->display.get_display_clock_speed =
10184 valleyview_get_display_clock_speed;
10185 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 10186 dev_priv->display.get_display_clock_speed =
10187 i945_get_display_clock_speed;
10188 else if (IS_I915G(dev))
10189 dev_priv->display.get_display_clock_speed =
10190 i915_get_display_clock_speed;
257a7ffc 10191 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 10192 dev_priv->display.get_display_clock_speed =
10193 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 10194 else if (IS_PINEVIEW(dev))
10195 dev_priv->display.get_display_clock_speed =
10196 pnv_get_display_clock_speed;
e70236a8
JB		 10197 else if (IS_I915GM(dev))
10198 dev_priv->display.get_display_clock_speed =
10199 i915gm_get_display_clock_speed;
10200 else if (IS_I865G(dev))
10201 dev_priv->display.get_display_clock_speed =
10202 i865_get_display_clock_speed;
f0f8a9ce 10203 else if (IS_I85X(dev))
e70236a8
JB		 10204 dev_priv->display.get_display_clock_speed =
10205 i855_get_display_clock_speed;
10206 else /* 852, 830 */
10207 dev_priv->display.get_display_clock_speed =
10208 i830_get_display_clock_speed;
10209
7f8a8569 10210 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 10211 if (IS_GEN5(dev)) {
674cf967 10212 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 10213 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 10214 } else if (IS_GEN6(dev)) {
674cf967 10215 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 10216 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 10217 } else if (IS_IVYBRIDGE(dev)) {
10218 /* FIXME: detect B0+ stepping and use auto training */
10219 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 10220 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 10221 dev_priv->display.modeset_global_resources =
10222 ivb_modeset_global_resources;
c82e4d26
ED		 10223 } else if (IS_HASWELL(dev)) {
10224 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 10225 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 10226 dev_priv->display.modeset_global_resources =
10227 haswell_modeset_global_resources;
a0e63c22 10228 }
6067aaea 10229 } else if (IS_G4X(dev)) {
e0dac65e 10230 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 10231 }
8c9f3aaf
JB		 10232
10233 /* Default just returns -ENODEV to indicate unsupported */
10234 dev_priv->display.queue_flip = intel_default_queue_flip;
10235
10236 switch (INTEL_INFO(dev)->gen) {
10237 case 2:
10238 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10239 break;
10240
10241 case 3:
10242 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10243 break;
10244
10245 case 4:
10246 case 5:
10247 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10248 break;
10249
10250 case 6:
10251 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10252 break;
7c9017e5
JB		 10253 case 7:
10254 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10255 break;
8c9f3aaf 10256 }
e70236a8
JB		 10257}
10258
b690e96c
JB		 10259/*
10260 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10261 * resume, or other times. This quirk makes sure that's the case for
10262 * affected systems.
10263 */
0206e353 10264static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 10265{
10266 struct drm_i915_private *dev_priv = dev->dev_private;
10267
10268 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 10269 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 10270}
10271
435793df
KP		 10272/*
10273 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10274 */
10275static void quirk_ssc_force_disable(struct drm_device *dev)
10276{
10277 struct drm_i915_private *dev_priv = dev->dev_private;
10278 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 10279 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 10280}
10281
4dca20ef 10282/*
5a15ab5b
CE		 10283 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10284 * brightness value
4dca20ef
CE		 10285 */
10286static void quirk_invert_brightness(struct drm_device *dev)
10287{
10288 struct drm_i915_private *dev_priv = dev->dev_private;
10289 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 10290 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 10291}
10292
e85843be
KM		 10293/*
10294 * Some machines (Dell XPS13) suffer broken backlight controls if
10295 * BLM_PCH_PWM_ENABLE is set.
10296 */
10297static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10298{
10299 struct drm_i915_private *dev_priv = dev->dev_private;
10300 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10301 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10302}
10303
b690e96c
JB		 10304struct intel_quirk {
10305 int device;
10306 int subsystem_vendor;
10307 int subsystem_device;
10308 void (*hook)(struct drm_device *dev);
10309};
10310
5f85f176
EE		 10311/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10312struct intel_dmi_quirk {
10313 void (*hook)(struct drm_device *dev);
10314 const struct dmi_system_id (*dmi_id_list)[];
10315};
10316
10317static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10318{
10319 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10320 return 1;
10321}
10322
10323static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10324 {
10325 .dmi_id_list = &(const struct dmi_system_id[]) {
10326 {
10327 .callback = intel_dmi_reverse_brightness,
10328 .ident = "NCR Corporation",
10329 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10330 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10331 },
10332 },
10333 { } /* terminating entry */
10334 },
10335 .hook = quirk_invert_brightness,
10336 },
10337};
10338
c43b5634 10339static struct intel_quirk intel_quirks[] = {
b690e96c 10340 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10341 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10342
b690e96c
JB		 10343 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10344 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10345
b690e96c
JB		 10346 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10347 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10348
a4945f95 10349 /* 830 needs to leave pipe A & dpll A up */
dcdaed6e 10350 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10351
10352 /* Lenovo U160 cannot use SSC on LVDS */
10353 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10354
10355 /* Sony Vaio Y cannot use SSC on LVDS */
10356 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 10357
ee1452d7
JN		 10358 /*
10359 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10360 * seem to use inverted backlight PWM.
10361 */
10362 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
e85843be
KM		 10363
10364 /* Dell XPS13 HD Sandy Bridge */
10365 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10366 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10367 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10368};
10369
10370static void intel_init_quirks(struct drm_device *dev)
10371{
10372 struct pci_dev *d = dev->pdev;
10373 int i;
10374
10375 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10376 struct intel_quirk *q = &intel_quirks[i];
10377
10378 if (d->device == q->device &&
10379 (d->subsystem_vendor == q->subsystem_vendor ||
10380 q->subsystem_vendor == PCI_ANY_ID) &&
10381 (d->subsystem_device == q->subsystem_device ||
10382 q->subsystem_device == PCI_ANY_ID))
10383 q->hook(dev);
10384 }
5f85f176
EE		 10385 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10386 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10387 intel_dmi_quirks[i].hook(dev);
10388 }
b690e96c
JB		 10389}
10390
9cce37f4
JB		 10391/* Disable the VGA plane that we never use */
10392static void i915_disable_vga(struct drm_device *dev)
10393{
10394 struct drm_i915_private *dev_priv = dev->dev_private;
10395 u8 sr1;
766aa1c4 10396 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10397
10398 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10399 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10400 sr1 = inb(VGA_SR_DATA);
10401 outb(sr1 | 1<<5, VGA_SR_DATA);
10402 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10403 udelay(300);
10404
10405 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10406 POSTING_READ(vga_reg);
10407}
10408
6e1b4fda 10409static void i915_enable_vga_mem(struct drm_device *dev)
81b5c7bc
AW		 10410{
10411 /* Enable VGA memory on Intel HD */
10412 if (HAS_PCH_SPLIT(dev)) {
10413 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10414 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10415 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10416 VGA_RSRC_LEGACY_MEM |
10417 VGA_RSRC_NORMAL_IO |
10418 VGA_RSRC_NORMAL_MEM);
10419 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10420 }
10421}
10422
6e1b4fda
VS		 10423void i915_disable_vga_mem(struct drm_device *dev)
10424{
10425 /* Disable VGA memory on Intel HD */
10426 if (HAS_PCH_SPLIT(dev)) {
10427 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10428 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10429 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10430 VGA_RSRC_NORMAL_IO |
10431 VGA_RSRC_NORMAL_MEM);
10432 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10433 }
10434}
10435
f817586c
DV		 10436void intel_modeset_init_hw(struct drm_device *dev)
10437{
f6071166
JB		 10438 struct drm_i915_private *dev_priv = dev->dev_private;
10439
a8f78b58
ED		 10440 intel_prepare_ddi(dev);
10441
f817586c
DV		 10442 intel_init_clock_gating(dev);
10443
f6071166
JB		 10444 /* Enable the CRI clock source so we can get at the display */
10445 if (IS_VALLEYVIEW(dev))
10446 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10447 DPLL_INTEGRATED_CRI_CLK_VLV);
10448
40e9cf64
JB		 10449 intel_init_dpio(dev);
10450
79f5b2c7 10451 mutex_lock(&dev->struct_mutex);
8090c6b9 10452 intel_enable_gt_powersave(dev);
79f5b2c7 10453 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10454}
10455
7d708ee4
ID		 10456void intel_modeset_suspend_hw(struct drm_device *dev)
10457{
10458 intel_suspend_hw(dev);
10459}
10460
79e53945
JB		 10461void intel_modeset_init(struct drm_device *dev)
10462{
652c393a 10463 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10464 int i, j, ret;
79e53945
JB		 10465
10466 drm_mode_config_init(dev);
10467
10468 dev->mode_config.min_width = 0;
10469 dev->mode_config.min_height = 0;
10470
019d96cb
DA		 10471 dev->mode_config.preferred_depth = 24;
10472 dev->mode_config.prefer_shadow = 1;
10473
e6ecefaa 10474 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10475
b690e96c
JB		 10476 intel_init_quirks(dev);
10477
1fa61106
ED		 10478 intel_init_pm(dev);
10479
e3c74757
BW		 10480 if (INTEL_INFO(dev)->num_pipes == 0)
10481 return;
10482
e70236a8
JB		 10483 intel_init_display(dev);
10484
a6c45cf0
CW		 10485 if (IS_GEN2(dev)) {
10486 dev->mode_config.max_width = 2048;
10487 dev->mode_config.max_height = 2048;
10488 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10489 dev->mode_config.max_width = 4096;
10490 dev->mode_config.max_height = 4096;
79e53945 10491 } else {
a6c45cf0
CW		 10492 dev->mode_config.max_width = 8192;
10493 dev->mode_config.max_height = 8192;
79e53945 10494 }
5d4545ae 10495 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10496
28c97730 10497 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10498 INTEL_INFO(dev)->num_pipes,
10499 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10500
08e2a7de 10501 for_each_pipe(i) {
79e53945 10502 intel_crtc_init(dev, i);
7f1f3851
JB		 10503 for (j = 0; j < dev_priv->num_plane; j++) {
10504 ret = intel_plane_init(dev, i, j);
10505 if (ret)
06da8da2
VS		 10506 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10507 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10508 }
79e53945
JB		 10509 }
10510
79f689aa 10511 intel_cpu_pll_init(dev);
e72f9fbf 10512 intel_shared_dpll_init(dev);
ee7b9f93 10513
9cce37f4
JB		 10514 /* Just disable it once at startup */
10515 i915_disable_vga(dev);
79e53945 10516 intel_setup_outputs(dev);
11be49eb
CW		 10517
10518 /* Just in case the BIOS is doing something questionable. */
10519 intel_disable_fbc(dev);
2c7111db
CW		 10520}
10521
24929352
DV		 10522static void
10523intel_connector_break_all_links(struct intel_connector *connector)
10524{
10525 connector->base.dpms = DRM_MODE_DPMS_OFF;
10526 connector->base.encoder = NULL;
10527 connector->encoder->connectors_active = false;
10528 connector->encoder->base.crtc = NULL;
10529}
10530
7fad798e
DV		 10531static void intel_enable_pipe_a(struct drm_device *dev)
10532{
10533 struct intel_connector *connector;
10534 struct drm_connector *crt = NULL;
10535 struct intel_load_detect_pipe load_detect_temp;
10536
10537 /* We can't just switch on the pipe A, we need to set things up with a
10538 * proper mode and output configuration. As a gross hack, enable pipe A
10539 * by enabling the load detect pipe once. */
10540 list_for_each_entry(connector,
10541 &dev->mode_config.connector_list,
10542 base.head) {
10543 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10544 crt = &connector->base;
10545 break;
10546 }
10547 }
10548
10549 if (!crt)
10550 return;
10551
10552 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10553 intel_release_load_detect_pipe(crt, &load_detect_temp);
10554
652c393a 10555
7fad798e
DV		 10556}
10557
fa555837
DV		 10558static bool
10559intel_check_plane_mapping(struct intel_crtc *crtc)
10560{
7eb552ae
BW		 10561 struct drm_device *dev = crtc->base.dev;
10562 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10563 u32 reg, val;
10564
7eb552ae 10565 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10566 return true;
10567
10568 reg = DSPCNTR(!crtc->plane);
10569 val = I915_READ(reg);
10570
10571 if ((val & DISPLAY_PLANE_ENABLE) &&
10572 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10573 return false;
10574
10575 return true;
10576}
10577
24929352
DV		 10578static void intel_sanitize_crtc(struct intel_crtc *crtc)
10579{
10580 struct drm_device *dev = crtc->base.dev;
10581 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10582 u32 reg;
24929352 10583
24929352 10584 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10585 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10586 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10587
10588 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10589 * disable the crtc (and hence change the state) if it is wrong. Note
10590 * that gen4+ has a fixed plane -> pipe mapping. */
10591 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10592 struct intel_connector *connector;
10593 bool plane;
10594
24929352
DV		 10595 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10596 crtc->base.base.id);
10597
10598 /* Pipe has the wrong plane attached and the plane is active.
10599 * Temporarily change the plane mapping and disable everything
10600 * ... */
10601 plane = crtc->plane;
10602 crtc->plane = !plane;
10603 dev_priv->display.crtc_disable(&crtc->base);
10604 crtc->plane = plane;
10605
10606 /* ... and break all links. */
10607 list_for_each_entry(connector, &dev->mode_config.connector_list,
10608 base.head) {
10609 if (connector->encoder->base.crtc != &crtc->base)
10610 continue;
10611
10612 intel_connector_break_all_links(connector);
10613 }
10614
10615 WARN_ON(crtc->active);
10616 crtc->base.enabled = false;
10617 }
24929352 10618
7fad798e
DV		 10619 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10620 crtc->pipe == PIPE_A && !crtc->active) {
10621 /* BIOS forgot to enable pipe A, this mostly happens after
10622 * resume. Force-enable the pipe to fix this, the update_dpms
10623 * call below we restore the pipe to the right state, but leave
10624 * the required bits on. */
10625 intel_enable_pipe_a(dev);
10626 }
10627
24929352
DV		 10628 /* Adjust the state of the output pipe according to whether we
10629 * have active connectors/encoders. */
10630 intel_crtc_update_dpms(&crtc->base);
10631
10632 if (crtc->active != crtc->base.enabled) {
10633 struct intel_encoder *encoder;
10634
10635 /* This can happen either due to bugs in the get_hw_state
10636 * functions or because the pipe is force-enabled due to the
10637 * pipe A quirk. */
10638 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10639 crtc->base.base.id,
10640 crtc->base.enabled ? "enabled" : "disabled",
10641 crtc->active ? "enabled" : "disabled");
10642
10643 crtc->base.enabled = crtc->active;
10644
10645 /* Because we only establish the connector -> encoder ->
10646 * crtc links if something is active, this means the
10647 * crtc is now deactivated. Break the links. connector
10648 * -> encoder links are only establish when things are
10649 * actually up, hence no need to break them. */
10650 WARN_ON(crtc->active);
10651
10652 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10653 WARN_ON(encoder->connectors_active);
10654 encoder->base.crtc = NULL;
10655 }
10656 }
10657}
10658
10659static void intel_sanitize_encoder(struct intel_encoder *encoder)
10660{
10661 struct intel_connector *connector;
10662 struct drm_device *dev = encoder->base.dev;
10663
10664 /* We need to check both for a crtc link (meaning that the
10665 * encoder is active and trying to read from a pipe) and the
10666 * pipe itself being active. */
10667 bool has_active_crtc = encoder->base.crtc &&
10668 to_intel_crtc(encoder->base.crtc)->active;
10669
10670 if (encoder->connectors_active && !has_active_crtc) {
10671 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10672 encoder->base.base.id,
10673 drm_get_encoder_name(&encoder->base));
10674
10675 /* Connector is active, but has no active pipe. This is
10676 * fallout from our resume register restoring. Disable
10677 * the encoder manually again. */
10678 if (encoder->base.crtc) {
10679 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10680 encoder->base.base.id,
10681 drm_get_encoder_name(&encoder->base));
10682 encoder->disable(encoder);
10683 }
10684
10685 /* Inconsistent output/port/pipe state happens presumably due to
10686 * a bug in one of the get_hw_state functions. Or someplace else
10687 * in our code, like the register restore mess on resume. Clamp
10688 * things to off as a safer default. */
10689 list_for_each_entry(connector,
10690 &dev->mode_config.connector_list,
10691 base.head) {
10692 if (connector->encoder != encoder)
10693 continue;
10694
10695 intel_connector_break_all_links(connector);
10696 }
10697 }
10698 /* Enabled encoders without active connectors will be fixed in
10699 * the crtc fixup. */
10700}
10701
44cec740 10702void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10703{
10704 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10705 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10706
8dc8a27c
PZ		 10707 /* This function can be called both from intel_modeset_setup_hw_state or
10708 * at a very early point in our resume sequence, where the power well
10709 * structures are not yet restored. Since this function is at a very
10710 * paranoid "someone might have enabled VGA while we were not looking"
10711 * level, just check if the power well is enabled instead of trying to
10712 * follow the "don't touch the power well if we don't need it" policy
10713 * the rest of the driver uses. */
10714 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10715 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10716 return;
10717
e1553faa 10718 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
0fde901f 10719 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10720 i915_disable_vga(dev);
6e1b4fda 10721 i915_disable_vga_mem(dev);
0fde901f
KM		 10722 }
10723}
10724
30e984df 10725static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10726{
10727 struct drm_i915_private *dev_priv = dev->dev_private;
10728 enum pipe pipe;
24929352
DV		 10729 struct intel_crtc *crtc;
10730 struct intel_encoder *encoder;
10731 struct intel_connector *connector;
5358901f 10732 int i;
24929352 10733
0e8ffe1b
DV		 10734 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10735 base.head) {
88adfff1 10736 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10737
0e8ffe1b
DV		 10738 crtc->active = dev_priv->display.get_pipe_config(crtc,
10739 &crtc->config);
24929352
DV		 10740
10741 crtc->base.enabled = crtc->active;
4c445e0e 10742 crtc->primary_enabled = crtc->active;
24929352
DV		 10743
10744 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10745 crtc->base.base.id,
10746 crtc->active ? "enabled" : "disabled");
10747 }
10748
5358901f 10749 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10750 if (HAS_DDI(dev))
6441ab5f
PZ		 10751 intel_ddi_setup_hw_pll_state(dev);
10752
5358901f
DV		 10753 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10754 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10755
10756 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10757 pll->active = 0;
10758 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10759 base.head) {
10760 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10761 pll->active++;
10762 }
10763 pll->refcount = pll->active;
10764
35c95375
DV		 10765 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10766 pll->name, pll->refcount, pll->on);
5358901f
DV		 10767 }
10768
24929352
DV		 10769 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10770 base.head) {
10771 pipe = 0;
10772
10773 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10774 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10775 encoder->base.crtc = &crtc->base;
510d5f2f 10776 if (encoder->get_config)
045ac3b5 10777 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10778 } else {
10779 encoder->base.crtc = NULL;
10780 }
10781
10782 encoder->connectors_active = false;
6f2bcceb 10783 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352
DV		 10784 encoder->base.base.id,
10785 drm_get_encoder_name(&encoder->base),
10786 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 10787 pipe_name(pipe));
24929352
DV		 10788 }
10789
10790 list_for_each_entry(connector, &dev->mode_config.connector_list,
10791 base.head) {
10792 if (connector->get_hw_state(connector)) {
10793 connector->base.dpms = DRM_MODE_DPMS_ON;
10794 connector->encoder->connectors_active = true;
10795 connector->base.encoder = &connector->encoder->base;
10796 } else {
10797 connector->base.dpms = DRM_MODE_DPMS_OFF;
10798 connector->base.encoder = NULL;
10799 }
10800 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10801 connector->base.base.id,
10802 drm_get_connector_name(&connector->base),
10803 connector->base.encoder ? "enabled" : "disabled");
10804 }
30e984df
DV		 10805}
10806
10807/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10808 * and i915 state tracking structures. */
10809void intel_modeset_setup_hw_state(struct drm_device *dev,
10810 bool force_restore)
10811{
10812 struct drm_i915_private *dev_priv = dev->dev_private;
10813 enum pipe pipe;
30e984df
DV		 10814 struct intel_crtc *crtc;
10815 struct intel_encoder *encoder;
35c95375 10816 int i;
30e984df
DV		 10817
10818 intel_modeset_readout_hw_state(dev);
24929352 10819
babea61d
JB		 10820 /*
10821 * Now that we have the config, copy it to each CRTC struct
10822 * Note that this could go away if we move to using crtc_config
10823 * checking everywhere.
10824 */
10825 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10826 base.head) {
10827 if (crtc->active && i915_fastboot) {
10828 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10829
10830 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10831 crtc->base.base.id);
10832 drm_mode_debug_printmodeline(&crtc->base.mode);
10833 }
10834 }
10835
24929352
DV		 10836 /* HW state is read out, now we need to sanitize this mess. */
10837 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10838 base.head) {
10839 intel_sanitize_encoder(encoder);
10840 }
10841
10842 for_each_pipe(pipe) {
10843 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10844 intel_sanitize_crtc(crtc);
c0b03411 10845 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10846 }
9a935856 10847
35c95375
DV		 10848 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10849 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10850
10851 if (!pll->on || pll->active)
10852 continue;
10853
10854 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10855
10856 pll->disable(dev_priv, pll);
10857 pll->on = false;
10858 }
10859
243e6a44
VS		 10860 if (IS_HASWELL(dev))
10861 ilk_wm_get_hw_state(dev);
10862
45e2b5f6 10863 if (force_restore) {
7d0bc1ea
VS		 10864 i915_redisable_vga(dev);
10865
f30da187
DV		 10866 /*
10867 * We need to use raw interfaces for restoring state to avoid
10868 * checking (bogus) intermediate states.
10869 */
45e2b5f6 10870 for_each_pipe(pipe) {
b5644d05
JB		 10871 struct drm_crtc *crtc =
10872 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10873
10874 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10875 crtc->fb);
45e2b5f6
DV		 10876 }
10877 } else {
10878 intel_modeset_update_staged_output_state(dev);
10879 }
8af6cf88
DV		 10880
10881 intel_modeset_check_state(dev);
2e938892
DV		 10882
10883 drm_mode_config_reset(dev);
2c7111db
CW		 10884}
10885
10886void intel_modeset_gem_init(struct drm_device *dev)
10887{
1833b134 10888 intel_modeset_init_hw(dev);
02e792fb
DV		 10889
10890 intel_setup_overlay(dev);
24929352 10891
45e2b5f6 10892 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10893}
10894
10895void intel_modeset_cleanup(struct drm_device *dev)
10896{
652c393a
JB		 10897 struct drm_i915_private *dev_priv = dev->dev_private;
10898 struct drm_crtc *crtc;
d9255d57 10899 struct drm_connector *connector;
652c393a 10900
fd0c0642
DV		 10901 /*
10902 * Interrupts and polling as the first thing to avoid creating havoc.
10903 * Too much stuff here (turning of rps, connectors, ...) would
10904 * experience fancy races otherwise.
10905 */
10906 drm_irq_uninstall(dev);
10907 cancel_work_sync(&dev_priv->hotplug_work);
10908 /*
10909 * Due to the hpd irq storm handling the hotplug work can re-arm the
10910 * poll handlers. Hence disable polling after hpd handling is shut down.
10911 */
f87ea761 10912 drm_kms_helper_poll_fini(dev);
fd0c0642 10913
652c393a
JB		 10914 mutex_lock(&dev->struct_mutex);
10915
723bfd70
JB		 10916 intel_unregister_dsm_handler();
10917
652c393a
JB		 10918 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10919 /* Skip inactive CRTCs */
10920 if (!crtc->fb)
10921 continue;
10922
3dec0095 10923 intel_increase_pllclock(crtc);
652c393a
JB		 10924 }
10925
973d04f9 10926 intel_disable_fbc(dev);
e70236a8 10927
6e1b4fda 10928 i915_enable_vga_mem(dev);
81b5c7bc 10929
8090c6b9 10930 intel_disable_gt_powersave(dev);
0cdab21f 10931
930ebb46
DV		 10932 ironlake_teardown_rc6(dev);
10933
69341a5e
KH		 10934 mutex_unlock(&dev->struct_mutex);
10935
1630fe75
CW		 10936 /* flush any delayed tasks or pending work */
10937 flush_scheduled_work();
10938
dc652f90
JN		 10939 /* destroy backlight, if any, before the connectors */
10940 intel_panel_destroy_backlight(dev);
10941
d9255d57
PZ		 10942 /* destroy the sysfs files before encoders/connectors */
10943 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
10944 drm_sysfs_connector_remove(connector);
10945
79e53945 10946 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10947
10948 intel_cleanup_overlay(dev);
79e53945
JB		 10949}
10950
f1c79df3
ZW		 10951/*
10952 * Return which encoder is currently attached for connector.
10953 */
df0e9248 10954struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10955{
df0e9248
CW		 10956 return &intel_attached_encoder(connector)->base;
10957}
f1c79df3 10958
df0e9248
CW		 10959void intel_connector_attach_encoder(struct intel_connector *connector,
10960 struct intel_encoder *encoder)
10961{
10962 connector->encoder = encoder;
10963 drm_mode_connector_attach_encoder(&connector->base,
10964 &encoder->base);
79e53945 10965}
28d52043
DA		 10966
10967/*
10968 * set vga decode state - true == enable VGA decode
10969 */
10970int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10971{
10972 struct drm_i915_private *dev_priv = dev->dev_private;
10973 u16 gmch_ctrl;
10974
10975 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10976 if (state)
10977 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10978 else
10979 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10980 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10981 return 0;
10982}
c4a1d9e4 10983
c4a1d9e4 10984struct intel_display_error_state {
ff57f1b0
PZ		 10985
10986 u32 power_well_driver;
10987
63b66e5b
CW		 10988 int num_transcoders;
10989
c4a1d9e4
CW		 10990 struct intel_cursor_error_state {
10991 u32 control;
10992 u32 position;
10993 u32 base;
10994 u32 size;
52331309 10995 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10996
10997 struct intel_pipe_error_state {
c4a1d9e4 10998 u32 source;
52331309 10999 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 11000
11001 struct intel_plane_error_state {
11002 u32 control;
11003 u32 stride;
11004 u32 size;
11005 u32 pos;
11006 u32 addr;
11007 u32 surface;
11008 u32 tile_offset;
52331309 11009 } plane[I915_MAX_PIPES];
63b66e5b
CW		 11010
11011 struct intel_transcoder_error_state {
11012 enum transcoder cpu_transcoder;
11013
11014 u32 conf;
11015
11016 u32 htotal;
11017 u32 hblank;
11018 u32 hsync;
11019 u32 vtotal;
11020 u32 vblank;
11021 u32 vsync;
11022 } transcoder[4];
c4a1d9e4
CW		 11023};
11024
11025struct intel_display_error_state *
11026intel_display_capture_error_state(struct drm_device *dev)
11027{
0206e353 11028 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 11029 struct intel_display_error_state *error;
63b66e5b
CW		 11030 int transcoders[] = {
11031 TRANSCODER_A,
11032 TRANSCODER_B,
11033 TRANSCODER_C,
11034 TRANSCODER_EDP,
11035 };
c4a1d9e4
CW		 11036 int i;
11037
63b66e5b
CW		 11038 if (INTEL_INFO(dev)->num_pipes == 0)
11039 return NULL;
11040
c4a1d9e4
CW		 11041 error = kmalloc(sizeof(*error), GFP_ATOMIC);
11042 if (error == NULL)
11043 return NULL;
11044
ff57f1b0
PZ		 11045 if (HAS_POWER_WELL(dev))
11046 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11047
52331309 11048 for_each_pipe(i) {
a18c4c3d
PZ		 11049 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11050 error->cursor[i].control = I915_READ(CURCNTR(i));
11051 error->cursor[i].position = I915_READ(CURPOS(i));
11052 error->cursor[i].base = I915_READ(CURBASE(i));
11053 } else {
11054 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11055 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11056 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11057 }
c4a1d9e4
CW		 11058
11059 error->plane[i].control = I915_READ(DSPCNTR(i));
11060 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 11061 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 11062 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 11063 error->plane[i].pos = I915_READ(DSPPOS(i));
11064 }
ca291363
PZ		 11065 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11066 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 11067 if (INTEL_INFO(dev)->gen >= 4) {
11068 error->plane[i].surface = I915_READ(DSPSURF(i));
11069 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11070 }
11071
c4a1d9e4 11072 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 11073 }
11074
11075 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11076 if (HAS_DDI(dev_priv->dev))
11077 error->num_transcoders++; /* Account for eDP. */
11078
11079 for (i = 0; i < error->num_transcoders; i++) {
11080 enum transcoder cpu_transcoder = transcoders[i];
11081
11082 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11083
11084 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11085 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11086 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11087 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11088 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11089 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11090 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 11091 }
11092
12d217c7
PZ		 11093 /* In the code above we read the registers without checking if the power
11094 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
11095 * prevent the next I915_WRITE from detecting it and printing an error
11096 * message. */
907b28c5 11097 intel_uncore_clear_errors(dev);
12d217c7 11098
c4a1d9e4
CW		 11099 return error;
11100}
11101
edc3d884
MK		 11102#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11103
c4a1d9e4 11104void
edc3d884 11105intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 11106 struct drm_device *dev,
11107 struct intel_display_error_state *error)
11108{
11109 int i;
11110
63b66e5b
CW		 11111 if (!error)
11112 return;
11113
edc3d884 11114 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 11115 if (HAS_POWER_WELL(dev))
edc3d884 11116 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 11117 error->power_well_driver);
52331309 11118 for_each_pipe(i) {
edc3d884 11119 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 11120 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 11121
11122 err_printf(m, "Plane [%d]:\n", i);
11123 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
11124 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 11125 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 11126 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
11127 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 11128 }
4b71a570 11129 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 11130 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 11131 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 11132 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
11133 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 11134 }
11135
edc3d884
MK		 11136 err_printf(m, "Cursor [%d]:\n", i);
11137 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
11138 err_printf(m, " POS: %08x\n", error->cursor[i].position);
11139 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 11140 }
63b66e5b
CW		 11141
11142 for (i = 0; i < error->num_transcoders; i++) {
11143 err_printf(m, " CPU transcoder: %c\n",
11144 transcoder_name(error->transcoder[i].cpu_transcoder));
11145 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
11146 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
11147 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
11148 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
11149 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
11150 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
11151 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
11152 }
c4a1d9e4 11153}
Linux kernel - Deliverables
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