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drm/i915/dp: promote clock recovery failures to DRM_ERROR
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
3dec0095 44static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 45static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 46
f1f644dc
JB		 47static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
18442d08
VS		 49static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
f1f644dc 51
e7457a9a
DL		 52static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54
55
79e53945 56typedef struct {
0206e353 57 int min, max;
79e53945
JB		 58} intel_range_t;
59
60typedef struct {
0206e353
AJ		 61 int dot_limit;
62 int p2_slow, p2_fast;
79e53945
JB		 63} intel_p2_t;
64
d4906093
ML		 65typedef struct intel_limit intel_limit_t;
66struct intel_limit {
0206e353
AJ		 67 intel_range_t dot, vco, n, m, m1, m2, p, p1;
68 intel_p2_t p2;
d4906093 69};
79e53945 70
d2acd215
DV		 71int
72intel_pch_rawclk(struct drm_device *dev)
73{
74 struct drm_i915_private *dev_priv = dev->dev_private;
75
76 WARN_ON(!HAS_PCH_SPLIT(dev));
77
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
79}
80
021357ac
CW		 81static inline u32 /* units of 100MHz */
82intel_fdi_link_freq(struct drm_device *dev)
83{
8b99e68c
CW		 84 if (IS_GEN5(dev)) {
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
87 } else
88 return 27;
021357ac
CW		 89}
90
5d536e28 91static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 92 .dot = { .min = 25000, .max = 350000 },
93 .vco = { .min = 930000, .max = 1400000 },
94 .n = { .min = 3, .max = 16 },
95 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 102};
103
5d536e28
DV		 104static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
106 .vco = { .min = 930000, .max = 1400000 },
107 .n = { .min = 3, .max = 16 },
108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
115};
116
e4b36699 117static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 118 .dot = { .min = 25000, .max = 350000 },
119 .vco = { .min = 930000, .max = 1400000 },
120 .n = { .min = 3, .max = 16 },
121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
e4b36699 128};
273e27ca 129
e4b36699 130static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 141};
142
143static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 154};
155
273e27ca 156
e4b36699 157static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
167 .p2_slow = 10,
168 .p2_fast = 10
044c7c41 169 },
e4b36699
KP		 170};
171
172static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 183};
184
185static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
044c7c41 196 },
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
044c7c41 210 },
e4b36699
KP		 211};
212
f2b115e6 213static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 216 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
273e27ca 219 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 226};
227
f2b115e6 228static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 239};
240
273e27ca
EA		 241/* Ironlake / Sandybridge
242 *
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
245 */
b91ad0ec 246static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 257};
258
b91ad0ec 259static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 270};
271
272static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 283};
284
273e27ca 285/* LVDS 100mhz refclk limits. */
b91ad0ec 286static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
0206e353 294 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
0206e353 307 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 310};
311
dc730512 312static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 313 /*
314 * These are the data rate limits (measured in fast clocks)
315 * since those are the strictest limits we have. The fast
316 * clock and actual rate limits are more relaxed, so checking
317 * them would make no difference.
318 */
319 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 320 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 321 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 322 .m1 = { .min = 2, .max = 3 },
323 .m2 = { .min = 11, .max = 156 },
b99ab663 324 .p1 = { .min = 2, .max = 3 },
5fdc9c49 325 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 326};
327
6b4bf1c4
VS		 328static void vlv_clock(int refclk, intel_clock_t *clock)
329{
330 clock->m = clock->m1 * clock->m2;
331 clock->p = clock->p1 * clock->p2;
332 clock->vco = refclk * clock->m / clock->n;
333 clock->dot = clock->vco / clock->p;
334}
335
e0638cdf
PZ		 336/**
337 * Returns whether any output on the specified pipe is of the specified type
338 */
339static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
340{
341 struct drm_device *dev = crtc->dev;
342 struct intel_encoder *encoder;
343
344 for_each_encoder_on_crtc(dev, crtc, encoder)
345 if (encoder->type == type)
346 return true;
347
348 return false;
349}
350
1b894b59
CW		 351static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
352 int refclk)
2c07245f 353{
b91ad0ec 354 struct drm_device *dev = crtc->dev;
2c07245f 355 const intel_limit_t *limit;
b91ad0ec
ZW		 356
357 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 358 if (intel_is_dual_link_lvds(dev)) {
1b894b59 359 if (refclk == 100000)
b91ad0ec
ZW		 360 limit = &intel_limits_ironlake_dual_lvds_100m;
361 else
362 limit = &intel_limits_ironlake_dual_lvds;
363 } else {
1b894b59 364 if (refclk == 100000)
b91ad0ec
ZW		 365 limit = &intel_limits_ironlake_single_lvds_100m;
366 else
367 limit = &intel_limits_ironlake_single_lvds;
368 }
c6bb3538 369 } else
b91ad0ec 370 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 371
372 return limit;
373}
374
044c7c41
ML		 375static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
376{
377 struct drm_device *dev = crtc->dev;
044c7c41
ML		 378 const intel_limit_t *limit;
379
380 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 381 if (intel_is_dual_link_lvds(dev))
e4b36699 382 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 383 else
e4b36699 384 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 385 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
386 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 387 limit = &intel_limits_g4x_hdmi;
044c7c41 388 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 389 limit = &intel_limits_g4x_sdvo;
044c7c41 390 } else /* The option is for other outputs */
e4b36699 391 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 392
393 return limit;
394}
395
1b894b59 396static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 397{
398 struct drm_device *dev = crtc->dev;
399 const intel_limit_t *limit;
400
bad720ff 401 if (HAS_PCH_SPLIT(dev))
1b894b59 402 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 403 else if (IS_G4X(dev)) {
044c7c41 404 limit = intel_g4x_limit(crtc);
f2b115e6 405 } else if (IS_PINEVIEW(dev)) {
2177832f 406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 407 limit = &intel_limits_pineview_lvds;
2177832f 408 else
f2b115e6 409 limit = &intel_limits_pineview_sdvo;
a0c4da24 410 } else if (IS_VALLEYVIEW(dev)) {
dc730512 411 limit = &intel_limits_vlv;
a6c45cf0
CW		 412 } else if (!IS_GEN2(dev)) {
413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
414 limit = &intel_limits_i9xx_lvds;
415 else
416 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 417 } else {
418 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 419 limit = &intel_limits_i8xx_lvds;
5d536e28 420 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 421 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 422 else
423 limit = &intel_limits_i8xx_dac;
79e53945
JB		 424 }
425 return limit;
426}
427
f2b115e6
AJ		 428/* m1 is reserved as 0 in Pineview, n is a ring counter */
429static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 430{
2177832f
SL		 431 clock->m = clock->m2 + 2;
432 clock->p = clock->p1 * clock->p2;
433 clock->vco = refclk * clock->m / clock->n;
434 clock->dot = clock->vco / clock->p;
435}
436
7429e9d4
DV		 437static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
438{
439 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
440}
441
ac58c3f0 442static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 443{
7429e9d4 444 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 445 clock->p = clock->p1 * clock->p2;
446 clock->vco = refclk * clock->m / (clock->n + 2);
447 clock->dot = clock->vco / clock->p;
448}
449
7c04d1d9 450#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 451/**
452 * Returns whether the given set of divisors are valid for a given refclk with
453 * the given connectors.
454 */
455
1b894b59
CW		 456static bool intel_PLL_is_valid(struct drm_device *dev,
457 const intel_limit_t *limit,
458 const intel_clock_t *clock)
79e53945 459{
f01b7962
VS		 460 if (clock->n < limit->n.min || limit->n.max < clock->n)
461 INTELPllInvalid("n out of range\n");
79e53945 462 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 463 INTELPllInvalid("p1 out of range\n");
79e53945 464 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 465 INTELPllInvalid("m2 out of range\n");
79e53945 466 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 467 INTELPllInvalid("m1 out of range\n");
f01b7962
VS		 468
469 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
470 if (clock->m1 <= clock->m2)
471 INTELPllInvalid("m1 <= m2\n");
472
473 if (!IS_VALLEYVIEW(dev)) {
474 if (clock->p < limit->p.min || limit->p.max < clock->p)
475 INTELPllInvalid("p out of range\n");
476 if (clock->m < limit->m.min || limit->m.max < clock->m)
477 INTELPllInvalid("m out of range\n");
478 }
479
79e53945 480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 481 INTELPllInvalid("vco out of range\n");
79e53945
JB		 482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
484 */
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 486 INTELPllInvalid("dot out of range\n");
79e53945
JB		 487
488 return true;
489}
490
d4906093 491static bool
ee9300bb 492i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
79e53945
JB		 495{
496 struct drm_device *dev = crtc->dev;
79e53945 497 intel_clock_t clock;
79e53945
JB		 498 int err = target;
499
a210b028 500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 501 /*
a210b028
DV		 502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
79e53945 505 */
1974cad0 506 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 507 clock.p2 = limit->p2.p2_fast;
508 else
509 clock.p2 = limit->p2.p2_slow;
510 } else {
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
513 else
514 clock.p2 = limit->p2.p2_fast;
515 }
516
0206e353 517 memset(best_clock, 0, sizeof(*best_clock));
79e53945 518
42158660
ZY		 519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
520 clock.m1++) {
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 523 if (clock.m2 >= clock.m1)
42158660
ZY		 524 break;
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 529 int this_err;
530
ac58c3f0
DV		 531 i9xx_clock(refclk, &clock);
532 if (!intel_PLL_is_valid(dev, limit,
533 &clock))
534 continue;
535 if (match_clock &&
536 clock.p != match_clock->p)
537 continue;
538
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
541 *best_clock = clock;
542 err = this_err;
543 }
544 }
545 }
546 }
547 }
548
549 return (err != target);
550}
551
552static bool
ee9300bb
DV		 553pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
79e53945
JB		 556{
557 struct drm_device *dev = crtc->dev;
79e53945 558 intel_clock_t clock;
79e53945
JB		 559 int err = target;
560
a210b028 561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 562 /*
a210b028
DV		 563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
79e53945 566 */
1974cad0 567 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 568 clock.p2 = limit->p2.p2_fast;
569 else
570 clock.p2 = limit->p2.p2_slow;
571 } else {
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
574 else
575 clock.p2 = limit->p2.p2_fast;
576 }
577
0206e353 578 memset(best_clock, 0, sizeof(*best_clock));
79e53945 579
42158660
ZY		 580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
581 clock.m1++) {
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 588 int this_err;
589
ac58c3f0 590 pineview_clock(refclk, &clock);
1b894b59
CW		 591 if (!intel_PLL_is_valid(dev, limit,
592 &clock))
79e53945 593 continue;
cec2f356
SP		 594 if (match_clock &&
595 clock.p != match_clock->p)
596 continue;
79e53945
JB		 597
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
600 *best_clock = clock;
601 err = this_err;
602 }
603 }
604 }
605 }
606 }
607
608 return (err != target);
609}
610
d4906093 611static bool
ee9300bb
DV		 612g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
d4906093
ML		 615{
616 struct drm_device *dev = crtc->dev;
d4906093
ML		 617 intel_clock_t clock;
618 int max_n;
619 bool found;
6ba770dc
AJ		 620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 622 found = false;
623
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 625 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 626 clock.p2 = limit->p2.p2_fast;
627 else
628 clock.p2 = limit->p2.p2_slow;
629 } else {
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
632 else
633 clock.p2 = limit->p2.p2_fast;
634 }
635
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
f77f13e2 638 /* based on hardware requirement, prefer smaller n to precision */
d4906093 639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 640 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
647 int this_err;
648
ac58c3f0 649 i9xx_clock(refclk, &clock);
1b894b59
CW		 650 if (!intel_PLL_is_valid(dev, limit,
651 &clock))
d4906093 652 continue;
1b894b59
CW		 653
654 this_err = abs(clock.dot - target);
d4906093
ML		 655 if (this_err < err_most) {
656 *best_clock = clock;
657 err_most = this_err;
658 max_n = clock.n;
659 found = true;
660 }
661 }
662 }
663 }
664 }
2c07245f
ZW		 665 return found;
666}
667
a0c4da24 668static bool
ee9300bb
DV		 669vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
a0c4da24 672{
f01b7962 673 struct drm_device *dev = crtc->dev;
6b4bf1c4 674 intel_clock_t clock;
69e4f900 675 unsigned int bestppm = 1000000;
27e639bf
VS		 676 /* min update 19.2 MHz */
677 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 678 bool found = false;
a0c4da24 679
6b4bf1c4
VS		 680 target *= 5; /* fast clock */
681
682 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 683
684 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 685 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 686 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 687 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 688 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 689 clock.p = clock.p1 * clock.p2;
a0c4da24 690 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
69e4f900
VS		 692 unsigned int ppm, diff;
693
6b4bf1c4
VS		 694 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
695 refclk * clock.m1);
696
697 vlv_clock(refclk, &clock);
43b0ac53 698
f01b7962
VS		 699 if (!intel_PLL_is_valid(dev, limit,
700 &clock))
43b0ac53
VS		 701 continue;
702
6b4bf1c4
VS		 703 diff = abs(clock.dot - target);
704 ppm = div_u64(1000000ULL * diff, target);
705
706 if (ppm < 100 && clock.p > best_clock->p) {
43b0ac53 707 bestppm = 0;
6b4bf1c4 708 *best_clock = clock;
49e497ef 709 found = true;
43b0ac53 710 }
6b4bf1c4 711
c686122c 712 if (bestppm >= 10 && ppm < bestppm - 10) {
69e4f900 713 bestppm = ppm;
6b4bf1c4 714 *best_clock = clock;
49e497ef 715 found = true;
a0c4da24
JB		 716 }
717 }
718 }
719 }
720 }
a0c4da24 721
49e497ef 722 return found;
a0c4da24 723}
a4fc5ed6 724
20ddf665
VS		 725bool intel_crtc_active(struct drm_crtc *crtc)
726{
727 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
728
729 /* Be paranoid as we can arrive here with only partial
730 * state retrieved from the hardware during setup.
731 *
241bfc38 732 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 733 * as Haswell has gained clock readout/fastboot support.
734 *
735 * We can ditch the crtc->fb check as soon as we can
736 * properly reconstruct framebuffers.
737 */
738 return intel_crtc->active && crtc->fb &&
241bfc38 739 intel_crtc->config.adjusted_mode.crtc_clock;
20ddf665
VS		 740}
741
a5c961d1
PZ		 742enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
743 enum pipe pipe)
744{
745 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
747
3b117c8f 748 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 749}
750
a928d536
PZ		 751static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
752{
753 struct drm_i915_private *dev_priv = dev->dev_private;
754 u32 frame, frame_reg = PIPEFRAME(pipe);
755
756 frame = I915_READ(frame_reg);
757
758 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
759 DRM_DEBUG_KMS("vblank wait timed out\n");
760}
761
9d0498a2
JB		 762/**
763 * intel_wait_for_vblank - wait for vblank on a given pipe
764 * @dev: drm device
765 * @pipe: pipe to wait for
766 *
767 * Wait for vblank to occur on a given pipe. Needed for various bits of
768 * mode setting code.
769 */
770void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 771{
9d0498a2 772 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 773 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 774
a928d536
PZ		 775 if (INTEL_INFO(dev)->gen >= 5) {
776 ironlake_wait_for_vblank(dev, pipe);
777 return;
778 }
779
300387c0
CW		 780 /* Clear existing vblank status. Note this will clear any other
781 * sticky status fields as well.
782 *
783 * This races with i915_driver_irq_handler() with the result
784 * that either function could miss a vblank event. Here it is not
785 * fatal, as we will either wait upon the next vblank interrupt or
786 * timeout. Generally speaking intel_wait_for_vblank() is only
787 * called during modeset at which time the GPU should be idle and
788 * should *not* be performing page flips and thus not waiting on
789 * vblanks...
790 * Currently, the result of us stealing a vblank from the irq
791 * handler is that a single frame will be skipped during swapbuffers.
792 */
793 I915_WRITE(pipestat_reg,
794 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
795
9d0498a2 796 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 797 if (wait_for(I915_READ(pipestat_reg) &
798 PIPE_VBLANK_INTERRUPT_STATUS,
799 50))
9d0498a2
JB		 800 DRM_DEBUG_KMS("vblank wait timed out\n");
801}
802
ab7ad7f6
KP		 803/*
804 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 805 * @dev: drm device
806 * @pipe: pipe to wait for
807 *
808 * After disabling a pipe, we can't wait for vblank in the usual way,
809 * spinning on the vblank interrupt status bit, since we won't actually
810 * see an interrupt when the pipe is disabled.
811 *
ab7ad7f6
KP		 812 * On Gen4 and above:
813 * wait for the pipe register state bit to turn off
814 *
815 * Otherwise:
816 * wait for the display line value to settle (it usually
817 * ends up stopping at the start of the next frame).
58e10eb9 818 *
9d0498a2 819 */
58e10eb9 820void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 821{
822 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 823 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
824 pipe);
ab7ad7f6
KP		 825
826 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 827 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 828
829 /* Wait for the Pipe State to go off */
58e10eb9
CW		 830 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
831 100))
284637d9 832 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 833 } else {
837ba00f 834 u32 last_line, line_mask;
58e10eb9 835 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 836 unsigned long timeout = jiffies + msecs_to_jiffies(100);
837
837ba00f
PZ		 838 if (IS_GEN2(dev))
839 line_mask = DSL_LINEMASK_GEN2;
840 else
841 line_mask = DSL_LINEMASK_GEN3;
842
ab7ad7f6
KP		 843 /* Wait for the display line to settle */
844 do {
837ba00f 845 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 846 mdelay(5);
837ba00f 847 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 848 time_after(timeout, jiffies));
849 if (time_after(jiffies, timeout))
284637d9 850 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 851 }
79e53945
JB		 852}
853
b0ea7d37
DL		 854/*
855 * ibx_digital_port_connected - is the specified port connected?
856 * @dev_priv: i915 private structure
857 * @port: the port to test
858 *
859 * Returns true if @port is connected, false otherwise.
860 */
861bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
862 struct intel_digital_port *port)
863{
864 u32 bit;
865
c36346e3
DL		 866 if (HAS_PCH_IBX(dev_priv->dev)) {
867 switch(port->port) {
868 case PORT_B:
869 bit = SDE_PORTB_HOTPLUG;
870 break;
871 case PORT_C:
872 bit = SDE_PORTC_HOTPLUG;
873 break;
874 case PORT_D:
875 bit = SDE_PORTD_HOTPLUG;
876 break;
877 default:
878 return true;
879 }
880 } else {
881 switch(port->port) {
882 case PORT_B:
883 bit = SDE_PORTB_HOTPLUG_CPT;
884 break;
885 case PORT_C:
886 bit = SDE_PORTC_HOTPLUG_CPT;
887 break;
888 case PORT_D:
889 bit = SDE_PORTD_HOTPLUG_CPT;
890 break;
891 default:
892 return true;
893 }
b0ea7d37
DL		 894 }
895
896 return I915_READ(SDEISR) & bit;
897}
898
b24e7179
JB		 899static const char *state_string(bool enabled)
900{
901 return enabled ? "on" : "off";
902}
903
904/* Only for pre-ILK configs */
55607e8a
DV		 905void assert_pll(struct drm_i915_private *dev_priv,
906 enum pipe pipe, bool state)
b24e7179
JB		 907{
908 int reg;
909 u32 val;
910 bool cur_state;
911
912 reg = DPLL(pipe);
913 val = I915_READ(reg);
914 cur_state = !!(val & DPLL_VCO_ENABLE);
915 WARN(cur_state != state,
916 "PLL state assertion failure (expected %s, current %s)\n",
917 state_string(state), state_string(cur_state));
918}
b24e7179 919
23538ef1
JN		 920/* XXX: the dsi pll is shared between MIPI DSI ports */
921static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
922{
923 u32 val;
924 bool cur_state;
925
926 mutex_lock(&dev_priv->dpio_lock);
927 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
928 mutex_unlock(&dev_priv->dpio_lock);
929
930 cur_state = val & DSI_PLL_VCO_EN;
931 WARN(cur_state != state,
932 "DSI PLL state assertion failure (expected %s, current %s)\n",
933 state_string(state), state_string(cur_state));
934}
935#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
936#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
937
55607e8a 938struct intel_shared_dpll *
e2b78267
DV		 939intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
940{
941 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
942
a43f6e0f 943 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 944 return NULL;
945
a43f6e0f 946 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 947}
948
040484af 949/* For ILK+ */
55607e8a
DV		 950void assert_shared_dpll(struct drm_i915_private *dev_priv,
951 struct intel_shared_dpll *pll,
952 bool state)
040484af 953{
040484af 954 bool cur_state;
5358901f 955 struct intel_dpll_hw_state hw_state;
040484af 956
9d82aa17
ED		 957 if (HAS_PCH_LPT(dev_priv->dev)) {
958 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
959 return;
960 }
961
92b27b08 962 if (WARN (!pll,
46edb027 963 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 964 return;
ee7b9f93 965
5358901f 966 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 967 WARN(cur_state != state,
5358901f
DV		 968 "%s assertion failure (expected %s, current %s)\n",
969 pll->name, state_string(state), state_string(cur_state));
040484af 970}
040484af
JB		 971
972static void assert_fdi_tx(struct drm_i915_private *dev_priv,
973 enum pipe pipe, bool state)
974{
975 int reg;
976 u32 val;
977 bool cur_state;
ad80a810
PZ		 978 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
979 pipe);
040484af 980
affa9354
PZ		 981 if (HAS_DDI(dev_priv->dev)) {
982 /* DDI does not have a specific FDI_TX register */
ad80a810 983 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 984 val = I915_READ(reg);
ad80a810 985 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 986 } else {
987 reg = FDI_TX_CTL(pipe);
988 val = I915_READ(reg);
989 cur_state = !!(val & FDI_TX_ENABLE);
990 }
040484af
JB		 991 WARN(cur_state != state,
992 "FDI TX state assertion failure (expected %s, current %s)\n",
993 state_string(state), state_string(cur_state));
994}
995#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
996#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
997
998static void assert_fdi_rx(struct drm_i915_private *dev_priv,
999 enum pipe pipe, bool state)
1000{
1001 int reg;
1002 u32 val;
1003 bool cur_state;
1004
d63fa0dc
PZ		 1005 reg = FDI_RX_CTL(pipe);
1006 val = I915_READ(reg);
1007 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1008 WARN(cur_state != state,
1009 "FDI RX state assertion failure (expected %s, current %s)\n",
1010 state_string(state), state_string(cur_state));
1011}
1012#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1013#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1014
1015static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1016 enum pipe pipe)
1017{
1018 int reg;
1019 u32 val;
1020
1021 /* ILK FDI PLL is always enabled */
1022 if (dev_priv->info->gen == 5)
1023 return;
1024
bf507ef7 1025 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1026 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1027 return;
1028
040484af
JB		 1029 reg = FDI_TX_CTL(pipe);
1030 val = I915_READ(reg);
1031 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1032}
1033
55607e8a
DV		 1034void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1035 enum pipe pipe, bool state)
040484af
JB		 1036{
1037 int reg;
1038 u32 val;
55607e8a 1039 bool cur_state;
040484af
JB		 1040
1041 reg = FDI_RX_CTL(pipe);
1042 val = I915_READ(reg);
55607e8a
DV		 1043 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1044 WARN(cur_state != state,
1045 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1046 state_string(state), state_string(cur_state));
040484af
JB		 1047}
1048
ea0760cf
JB		 1049static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1050 enum pipe pipe)
1051{
1052 int pp_reg, lvds_reg;
1053 u32 val;
1054 enum pipe panel_pipe = PIPE_A;
0de3b485 1055 bool locked = true;
ea0760cf
JB		 1056
1057 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1058 pp_reg = PCH_PP_CONTROL;
1059 lvds_reg = PCH_LVDS;
1060 } else {
1061 pp_reg = PP_CONTROL;
1062 lvds_reg = LVDS;
1063 }
1064
1065 val = I915_READ(pp_reg);
1066 if (!(val & PANEL_POWER_ON) ||
1067 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1068 locked = false;
1069
1070 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1071 panel_pipe = PIPE_B;
1072
1073 WARN(panel_pipe == pipe && locked,
1074 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1075 pipe_name(pipe));
ea0760cf
JB		 1076}
1077
93ce0ba6
JN		 1078static void assert_cursor(struct drm_i915_private *dev_priv,
1079 enum pipe pipe, bool state)
1080{
1081 struct drm_device *dev = dev_priv->dev;
1082 bool cur_state;
1083
1084 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1085 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1086 else if (IS_845G(dev) || IS_I865G(dev))
1087 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1088 else
1089 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1090
1091 WARN(cur_state != state,
1092 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1093 pipe_name(pipe), state_string(state), state_string(cur_state));
1094}
1095#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1096#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1097
b840d907
JB		 1098void assert_pipe(struct drm_i915_private *dev_priv,
1099 enum pipe pipe, bool state)
b24e7179
JB		 1100{
1101 int reg;
1102 u32 val;
63d7bbe9 1103 bool cur_state;
702e7a56
PZ		 1104 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1105 pipe);
b24e7179 1106
8e636784
DV		 1107 /* if we need the pipe A quirk it must be always on */
1108 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1109 state = true;
1110
b97186f0
PZ		 1111 if (!intel_display_power_enabled(dev_priv->dev,
1112 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1113 cur_state = false;
1114 } else {
1115 reg = PIPECONF(cpu_transcoder);
1116 val = I915_READ(reg);
1117 cur_state = !!(val & PIPECONF_ENABLE);
1118 }
1119
63d7bbe9
JB		 1120 WARN(cur_state != state,
1121 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1122 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1123}
1124
931872fc
CW		 1125static void assert_plane(struct drm_i915_private *dev_priv,
1126 enum plane plane, bool state)
b24e7179
JB		 1127{
1128 int reg;
1129 u32 val;
931872fc 1130 bool cur_state;
b24e7179
JB		 1131
1132 reg = DSPCNTR(plane);
1133 val = I915_READ(reg);
931872fc
CW		 1134 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1135 WARN(cur_state != state,
1136 "plane %c assertion failure (expected %s, current %s)\n",
1137 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1138}
1139
931872fc
CW		 1140#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1141#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1142
b24e7179
JB		 1143static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1144 enum pipe pipe)
1145{
653e1026 1146 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1147 int reg, i;
1148 u32 val;
1149 int cur_pipe;
1150
653e1026
VS		 1151 /* Primary planes are fixed to pipes on gen4+ */
1152 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1153 reg = DSPCNTR(pipe);
1154 val = I915_READ(reg);
1155 WARN((val & DISPLAY_PLANE_ENABLE),
1156 "plane %c assertion failure, should be disabled but not\n",
1157 plane_name(pipe));
19ec1358 1158 return;
28c05794 1159 }
19ec1358 1160
b24e7179 1161 /* Need to check both planes against the pipe */
08e2a7de 1162 for_each_pipe(i) {
b24e7179
JB		 1163 reg = DSPCNTR(i);
1164 val = I915_READ(reg);
1165 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1166 DISPPLANE_SEL_PIPE_SHIFT;
1167 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1168 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1169 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1170 }
1171}
1172
19332d7a
JB		 1173static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1174 enum pipe pipe)
1175{
20674eef 1176 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1177 int reg, i;
1178 u32 val;
1179
20674eef
VS		 1180 if (IS_VALLEYVIEW(dev)) {
1181 for (i = 0; i < dev_priv->num_plane; i++) {
1182 reg = SPCNTR(pipe, i);
1183 val = I915_READ(reg);
1184 WARN((val & SP_ENABLE),
1185 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1186 sprite_name(pipe, i), pipe_name(pipe));
1187 }
1188 } else if (INTEL_INFO(dev)->gen >= 7) {
1189 reg = SPRCTL(pipe);
19332d7a 1190 val = I915_READ(reg);
20674eef 1191 WARN((val & SPRITE_ENABLE),
06da8da2 1192 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1193 plane_name(pipe), pipe_name(pipe));
1194 } else if (INTEL_INFO(dev)->gen >= 5) {
1195 reg = DVSCNTR(pipe);
19332d7a 1196 val = I915_READ(reg);
20674eef 1197 WARN((val & DVS_ENABLE),
06da8da2 1198 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1199 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1200 }
1201}
1202
92f2584a
JB		 1203static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1204{
1205 u32 val;
1206 bool enabled;
1207
9d82aa17
ED		 1208 if (HAS_PCH_LPT(dev_priv->dev)) {
1209 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1210 return;
1211 }
1212
92f2584a
JB		 1213 val = I915_READ(PCH_DREF_CONTROL);
1214 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1215 DREF_SUPERSPREAD_SOURCE_MASK));
1216 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1217}
1218
ab9412ba
DV		 1219static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1220 enum pipe pipe)
92f2584a
JB		 1221{
1222 int reg;
1223 u32 val;
1224 bool enabled;
1225
ab9412ba 1226 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1227 val = I915_READ(reg);
1228 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1229 WARN(enabled,
1230 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1231 pipe_name(pipe));
92f2584a
JB		 1232}
1233
4e634389
KP		 1234static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1235 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1236{
1237 if ((val & DP_PORT_EN) == 0)
1238 return false;
1239
1240 if (HAS_PCH_CPT(dev_priv->dev)) {
1241 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1242 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1243 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1244 return false;
1245 } else {
1246 if ((val & DP_PIPE_MASK) != (pipe << 30))
1247 return false;
1248 }
1249 return true;
1250}
1251
1519b995
KP		 1252static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1253 enum pipe pipe, u32 val)
1254{
dc0fa718 1255 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1256 return false;
1257
1258 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1259 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1260 return false;
1261 } else {
dc0fa718 1262 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1263 return false;
1264 }
1265 return true;
1266}
1267
1268static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1269 enum pipe pipe, u32 val)
1270{
1271 if ((val & LVDS_PORT_EN) == 0)
1272 return false;
1273
1274 if (HAS_PCH_CPT(dev_priv->dev)) {
1275 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1276 return false;
1277 } else {
1278 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1279 return false;
1280 }
1281 return true;
1282}
1283
1284static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1285 enum pipe pipe, u32 val)
1286{
1287 if ((val & ADPA_DAC_ENABLE) == 0)
1288 return false;
1289 if (HAS_PCH_CPT(dev_priv->dev)) {
1290 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1291 return false;
1292 } else {
1293 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1294 return false;
1295 }
1296 return true;
1297}
1298
291906f1 1299static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1300 enum pipe pipe, int reg, u32 port_sel)
291906f1 1301{
47a05eca 1302 u32 val = I915_READ(reg);
4e634389 1303 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1304 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1305 reg, pipe_name(pipe));
de9a35ab 1306
75c5da27
DV		 1307 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1308 && (val & DP_PIPEB_SELECT),
de9a35ab 1309 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1310}
1311
1312static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1313 enum pipe pipe, int reg)
1314{
47a05eca 1315 u32 val = I915_READ(reg);
b70ad586 1316 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1317 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1318 reg, pipe_name(pipe));
de9a35ab 1319
dc0fa718 1320 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1321 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1322 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1323}
1324
1325static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1326 enum pipe pipe)
1327{
1328 int reg;
1329 u32 val;
291906f1 1330
f0575e92
KP		 1331 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1332 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1333 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1334
1335 reg = PCH_ADPA;
1336 val = I915_READ(reg);
b70ad586 1337 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1338 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1339 pipe_name(pipe));
291906f1
JB		 1340
1341 reg = PCH_LVDS;
1342 val = I915_READ(reg);
b70ad586 1343 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1344 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1345 pipe_name(pipe));
291906f1 1346
e2debe91
PZ		 1347 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1348 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1349 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1350}
1351
40e9cf64
JB		 1352static void intel_init_dpio(struct drm_device *dev)
1353{
1354 struct drm_i915_private *dev_priv = dev->dev_private;
1355
1356 if (!IS_VALLEYVIEW(dev))
1357 return;
1358
1359 /*
1360 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1361 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1362 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1363 * b. The other bits such as sfr settings / modesel may all be set
1364 * to 0.
1365 *
1366 * This should only be done on init and resume from S3 with both
1367 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1368 */
1369 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1370}
1371
426115cf 1372static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1373{
426115cf
DV		 1374 struct drm_device *dev = crtc->base.dev;
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376 int reg = DPLL(crtc->pipe);
1377 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1378
426115cf 1379 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1380
1381 /* No really, not for ILK+ */
1382 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1383
1384 /* PLL is protected by panel, make sure we can write it */
1385 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1386 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1387
426115cf
DV		 1388 I915_WRITE(reg, dpll);
1389 POSTING_READ(reg);
1390 udelay(150);
1391
1392 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1393 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1394
1395 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1396 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1397
1398 /* We do this three times for luck */
426115cf 1399 I915_WRITE(reg, dpll);
87442f73
DV		 1400 POSTING_READ(reg);
1401 udelay(150); /* wait for warmup */
426115cf 1402 I915_WRITE(reg, dpll);
87442f73
DV		 1403 POSTING_READ(reg);
1404 udelay(150); /* wait for warmup */
426115cf 1405 I915_WRITE(reg, dpll);
87442f73
DV		 1406 POSTING_READ(reg);
1407 udelay(150); /* wait for warmup */
1408}
1409
66e3d5c0 1410static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1411{
66e3d5c0
DV		 1412 struct drm_device *dev = crtc->base.dev;
1413 struct drm_i915_private *dev_priv = dev->dev_private;
1414 int reg = DPLL(crtc->pipe);
1415 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1416
66e3d5c0 1417 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1418
63d7bbe9 1419 /* No really, not for ILK+ */
87442f73 1420 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1421
1422 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1423 if (IS_MOBILE(dev) && !IS_I830(dev))
1424 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1425
66e3d5c0
DV		 1426 I915_WRITE(reg, dpll);
1427
1428 /* Wait for the clocks to stabilize. */
1429 POSTING_READ(reg);
1430 udelay(150);
1431
1432 if (INTEL_INFO(dev)->gen >= 4) {
1433 I915_WRITE(DPLL_MD(crtc->pipe),
1434 crtc->config.dpll_hw_state.dpll_md);
1435 } else {
1436 /* The pixel multiplier can only be updated once the
1437 * DPLL is enabled and the clocks are stable.
1438 *
1439 * So write it again.
1440 */
1441 I915_WRITE(reg, dpll);
1442 }
63d7bbe9
JB		 1443
1444 /* We do this three times for luck */
66e3d5c0 1445 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1446 POSTING_READ(reg);
1447 udelay(150); /* wait for warmup */
66e3d5c0 1448 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1449 POSTING_READ(reg);
1450 udelay(150); /* wait for warmup */
66e3d5c0 1451 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1452 POSTING_READ(reg);
1453 udelay(150); /* wait for warmup */
1454}
1455
1456/**
50b44a44 1457 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1458 * @dev_priv: i915 private structure
1459 * @pipe: pipe PLL to disable
1460 *
1461 * Disable the PLL for @pipe, making sure the pipe is off first.
1462 *
1463 * Note! This is for pre-ILK only.
1464 */
50b44a44 1465static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1466{
63d7bbe9
JB		 1467 /* Don't disable pipe A or pipe A PLLs if needed */
1468 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1469 return;
1470
1471 /* Make sure the pipe isn't still relying on us */
1472 assert_pipe_disabled(dev_priv, pipe);
1473
50b44a44
DV		 1474 I915_WRITE(DPLL(pipe), 0);
1475 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1476}
1477
f6071166
JB		 1478static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1479{
1480 u32 val = 0;
1481
1482 /* Make sure the pipe isn't still relying on us */
1483 assert_pipe_disabled(dev_priv, pipe);
1484
1485 /* Leave integrated clock source enabled */
1486 if (pipe == PIPE_B)
1487 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1488 I915_WRITE(DPLL(pipe), val);
1489 POSTING_READ(DPLL(pipe));
1490}
1491
89b667f8
JB		 1492void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1493{
1494 u32 port_mask;
1495
1496 if (!port)
1497 port_mask = DPLL_PORTB_READY_MASK;
1498 else
1499 port_mask = DPLL_PORTC_READY_MASK;
1500
1501 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1502 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1503 'B' + port, I915_READ(DPLL(0)));
1504}
1505
92f2584a 1506/**
e72f9fbf 1507 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1508 * @dev_priv: i915 private structure
1509 * @pipe: pipe PLL to enable
1510 *
1511 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1512 * drives the transcoder clock.
1513 */
e2b78267 1514static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1515{
e2b78267
DV		 1516 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1517 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1518
48da64a8 1519 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1520 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1521 if (WARN_ON(pll == NULL))
48da64a8
CW		 1522 return;
1523
1524 if (WARN_ON(pll->refcount == 0))
1525 return;
ee7b9f93 1526
46edb027
DV		 1527 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1528 pll->name, pll->active, pll->on,
e2b78267 1529 crtc->base.base.id);
92f2584a 1530
cdbd2316
DV		 1531 if (pll->active++) {
1532 WARN_ON(!pll->on);
e9d6944e 1533 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1534 return;
1535 }
f4a091c7 1536 WARN_ON(pll->on);
ee7b9f93 1537
46edb027 1538 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1539 pll->enable(dev_priv, pll);
ee7b9f93 1540 pll->on = true;
92f2584a
JB		 1541}
1542
e2b78267 1543static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1544{
e2b78267
DV		 1545 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1546 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1547
92f2584a
JB		 1548 /* PCH only available on ILK+ */
1549 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1550 if (WARN_ON(pll == NULL))
ee7b9f93 1551 return;
92f2584a 1552
48da64a8
CW		 1553 if (WARN_ON(pll->refcount == 0))
1554 return;
7a419866 1555
46edb027
DV		 1556 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1557 pll->name, pll->active, pll->on,
e2b78267 1558 crtc->base.base.id);
7a419866 1559
48da64a8 1560 if (WARN_ON(pll->active == 0)) {
e9d6944e 1561 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1562 return;
1563 }
1564
e9d6944e 1565 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1566 WARN_ON(!pll->on);
cdbd2316 1567 if (--pll->active)
7a419866 1568 return;
ee7b9f93 1569
46edb027 1570 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1571 pll->disable(dev_priv, pll);
ee7b9f93 1572 pll->on = false;
92f2584a
JB		 1573}
1574
b8a4f404
PZ		 1575static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1576 enum pipe pipe)
040484af 1577{
23670b32 1578 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1579 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1581 uint32_t reg, val, pipeconf_val;
040484af
JB		 1582
1583 /* PCH only available on ILK+ */
1584 BUG_ON(dev_priv->info->gen < 5);
1585
1586 /* Make sure PCH DPLL is enabled */
e72f9fbf 1587 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1588 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1589
1590 /* FDI must be feeding us bits for PCH ports */
1591 assert_fdi_tx_enabled(dev_priv, pipe);
1592 assert_fdi_rx_enabled(dev_priv, pipe);
1593
23670b32
DV		 1594 if (HAS_PCH_CPT(dev)) {
1595 /* Workaround: Set the timing override bit before enabling the
1596 * pch transcoder. */
1597 reg = TRANS_CHICKEN2(pipe);
1598 val = I915_READ(reg);
1599 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1600 I915_WRITE(reg, val);
59c859d6 1601 }
23670b32 1602
ab9412ba 1603 reg = PCH_TRANSCONF(pipe);
040484af 1604 val = I915_READ(reg);
5f7f726d 1605 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1606
1607 if (HAS_PCH_IBX(dev_priv->dev)) {
1608 /*
1609 * make the BPC in transcoder be consistent with
1610 * that in pipeconf reg.
1611 */
dfd07d72
DV		 1612 val &= ~PIPECONF_BPC_MASK;
1613 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1614 }
5f7f726d
PZ		 1615
1616 val &= ~TRANS_INTERLACE_MASK;
1617 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1618 if (HAS_PCH_IBX(dev_priv->dev) &&
1619 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1620 val |= TRANS_LEGACY_INTERLACED_ILK;
1621 else
1622 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1623 else
1624 val |= TRANS_PROGRESSIVE;
1625
040484af
JB		 1626 I915_WRITE(reg, val | TRANS_ENABLE);
1627 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1628 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1629}
1630
8fb033d7 1631static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1632 enum transcoder cpu_transcoder)
040484af 1633{
8fb033d7 1634 u32 val, pipeconf_val;
8fb033d7
PZ		 1635
1636 /* PCH only available on ILK+ */
1637 BUG_ON(dev_priv->info->gen < 5);
1638
8fb033d7 1639 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1640 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1641 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1642
223a6fdf
PZ		 1643 /* Workaround: set timing override bit. */
1644 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1645 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1646 I915_WRITE(_TRANSA_CHICKEN2, val);
1647
25f3ef11 1648 val = TRANS_ENABLE;
937bb610 1649 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1650
9a76b1c6
PZ		 1651 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1652 PIPECONF_INTERLACED_ILK)
a35f2679 1653 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1654 else
1655 val |= TRANS_PROGRESSIVE;
1656
ab9412ba
DV		 1657 I915_WRITE(LPT_TRANSCONF, val);
1658 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1659 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1660}
1661
b8a4f404
PZ		 1662static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1663 enum pipe pipe)
040484af 1664{
23670b32
DV		 1665 struct drm_device *dev = dev_priv->dev;
1666 uint32_t reg, val;
040484af
JB		 1667
1668 /* FDI relies on the transcoder */
1669 assert_fdi_tx_disabled(dev_priv, pipe);
1670 assert_fdi_rx_disabled(dev_priv, pipe);
1671
291906f1
JB		 1672 /* Ports must be off as well */
1673 assert_pch_ports_disabled(dev_priv, pipe);
1674
ab9412ba 1675 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1676 val = I915_READ(reg);
1677 val &= ~TRANS_ENABLE;
1678 I915_WRITE(reg, val);
1679 /* wait for PCH transcoder off, transcoder state */
1680 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1681 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1682
1683 if (!HAS_PCH_IBX(dev)) {
1684 /* Workaround: Clear the timing override chicken bit again. */
1685 reg = TRANS_CHICKEN2(pipe);
1686 val = I915_READ(reg);
1687 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1688 I915_WRITE(reg, val);
1689 }
040484af
JB		 1690}
1691
ab4d966c 1692static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1693{
8fb033d7
PZ		 1694 u32 val;
1695
ab9412ba 1696 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1697 val &= ~TRANS_ENABLE;
ab9412ba 1698 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1699 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1700 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1701 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1702
1703 /* Workaround: clear timing override bit. */
1704 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1705 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1706 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1707}
1708
b24e7179 1709/**
309cfea8 1710 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1711 * @dev_priv: i915 private structure
1712 * @pipe: pipe to enable
040484af 1713 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1714 *
1715 * Enable @pipe, making sure that various hardware specific requirements
1716 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1717 *
1718 * @pipe should be %PIPE_A or %PIPE_B.
1719 *
1720 * Will wait until the pipe is actually running (i.e. first vblank) before
1721 * returning.
1722 */
040484af 1723static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1724 bool pch_port, bool dsi)
b24e7179 1725{
702e7a56
PZ		 1726 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1727 pipe);
1a240d4d 1728 enum pipe pch_transcoder;
b24e7179
JB		 1729 int reg;
1730 u32 val;
1731
58c6eaa2 1732 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1733 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 1734 assert_sprites_disabled(dev_priv, pipe);
1735
681e5811 1736 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1737 pch_transcoder = TRANSCODER_A;
1738 else
1739 pch_transcoder = pipe;
1740
b24e7179
JB		 1741 /*
1742 * A pipe without a PLL won't actually be able to drive bits from
1743 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1744 * need the check.
1745 */
1746 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1747 if (dsi)
1748 assert_dsi_pll_enabled(dev_priv);
1749 else
1750 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1751 else {
1752 if (pch_port) {
1753 /* if driving the PCH, we need FDI enabled */
cc391bbb 1754 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1755 assert_fdi_tx_pll_enabled(dev_priv,
1756 (enum pipe) cpu_transcoder);
040484af
JB		 1757 }
1758 /* FIXME: assert CPU port conditions for SNB+ */
1759 }
b24e7179 1760
702e7a56 1761 reg = PIPECONF(cpu_transcoder);
b24e7179 1762 val = I915_READ(reg);
00d70b15
CW		 1763 if (val & PIPECONF_ENABLE)
1764 return;
1765
1766 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1767 intel_wait_for_vblank(dev_priv->dev, pipe);
1768}
1769
1770/**
309cfea8 1771 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1772 * @dev_priv: i915 private structure
1773 * @pipe: pipe to disable
1774 *
1775 * Disable @pipe, making sure that various hardware specific requirements
1776 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1777 *
1778 * @pipe should be %PIPE_A or %PIPE_B.
1779 *
1780 * Will wait until the pipe has shut down before returning.
1781 */
1782static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1783 enum pipe pipe)
1784{
702e7a56
PZ		 1785 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1786 pipe);
b24e7179
JB		 1787 int reg;
1788 u32 val;
1789
1790 /*
1791 * Make sure planes won't keep trying to pump pixels to us,
1792 * or we might hang the display.
1793 */
1794 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1795 assert_cursor_disabled(dev_priv, pipe);
19332d7a 1796 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1797
1798 /* Don't disable pipe A or pipe A PLLs if needed */
1799 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1800 return;
1801
702e7a56 1802 reg = PIPECONF(cpu_transcoder);
b24e7179 1803 val = I915_READ(reg);
00d70b15
CW		 1804 if ((val & PIPECONF_ENABLE) == 0)
1805 return;
1806
1807 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1808 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1809}
1810
d74362c9
KP		 1811/*
1812 * Plane regs are double buffered, going from enabled->disabled needs a
1813 * trigger in order to latch. The display address reg provides this.
1814 */
6f1d69b0 1815void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1816 enum plane plane)
1817{
14f86147
DL		 1818 if (dev_priv->info->gen >= 4)
1819 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1820 else
1821 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1822}
1823
b24e7179
JB		 1824/**
1825 * intel_enable_plane - enable a display plane on a given pipe
1826 * @dev_priv: i915 private structure
1827 * @plane: plane to enable
1828 * @pipe: pipe being fed
1829 *
1830 * Enable @plane on @pipe, making sure that @pipe is running first.
1831 */
1832static void intel_enable_plane(struct drm_i915_private *dev_priv,
1833 enum plane plane, enum pipe pipe)
1834{
1835 int reg;
1836 u32 val;
1837
1838 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1839 assert_pipe_enabled(dev_priv, pipe);
1840
1841 reg = DSPCNTR(plane);
1842 val = I915_READ(reg);
00d70b15
CW		 1843 if (val & DISPLAY_PLANE_ENABLE)
1844 return;
1845
1846 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1847 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1848 intel_wait_for_vblank(dev_priv->dev, pipe);
1849}
1850
b24e7179
JB		 1851/**
1852 * intel_disable_plane - disable a display plane
1853 * @dev_priv: i915 private structure
1854 * @plane: plane to disable
1855 * @pipe: pipe consuming the data
1856 *
1857 * Disable @plane; should be an independent operation.
1858 */
1859static void intel_disable_plane(struct drm_i915_private *dev_priv,
1860 enum plane plane, enum pipe pipe)
1861{
1862 int reg;
1863 u32 val;
1864
1865 reg = DSPCNTR(plane);
1866 val = I915_READ(reg);
00d70b15
CW		 1867 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1868 return;
1869
1870 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1871 intel_flush_display_plane(dev_priv, plane);
1872 intel_wait_for_vblank(dev_priv->dev, pipe);
1873}
1874
693db184
CW		 1875static bool need_vtd_wa(struct drm_device *dev)
1876{
1877#ifdef CONFIG_INTEL_IOMMU
1878 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1879 return true;
1880#endif
1881 return false;
1882}
1883
127bd2ac 1884int
48b956c5 1885intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1886 struct drm_i915_gem_object *obj,
919926ae 1887 struct intel_ring_buffer *pipelined)
6b95a207 1888{
ce453d81 1889 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1890 u32 alignment;
1891 int ret;
1892
05394f39 1893 switch (obj->tiling_mode) {
6b95a207 1894 case I915_TILING_NONE:
534843da
CW		 1895 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1896 alignment = 128 * 1024;
a6c45cf0 1897 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1898 alignment = 4 * 1024;
1899 else
1900 alignment = 64 * 1024;
6b95a207
KH		 1901 break;
1902 case I915_TILING_X:
1903 /* pin() will align the object as required by fence */
1904 alignment = 0;
1905 break;
1906 case I915_TILING_Y:
8bb6e959
DV		 1907 /* Despite that we check this in framebuffer_init userspace can
1908 * screw us over and change the tiling after the fact. Only
1909 * pinned buffers can't change their tiling. */
1910 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1911 return -EINVAL;
1912 default:
1913 BUG();
1914 }
1915
693db184
CW		 1916 /* Note that the w/a also requires 64 PTE of padding following the
1917 * bo. We currently fill all unused PTE with the shadow page and so
1918 * we should always have valid PTE following the scanout preventing
1919 * the VT-d warning.
1920 */
1921 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1922 alignment = 256 * 1024;
1923
ce453d81 1924 dev_priv->mm.interruptible = false;
2da3b9b9 1925 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1926 if (ret)
ce453d81 1927 goto err_interruptible;
6b95a207
KH		 1928
1929 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1930 * fence, whereas 965+ only requires a fence if using
1931 * framebuffer compression. For simplicity, we always install
1932 * a fence as the cost is not that onerous.
1933 */
06d98131 1934 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1935 if (ret)
1936 goto err_unpin;
1690e1eb 1937
9a5a53b3 1938 i915_gem_object_pin_fence(obj);
6b95a207 1939
ce453d81 1940 dev_priv->mm.interruptible = true;
6b95a207 1941 return 0;
48b956c5
CW		 1942
1943err_unpin:
cc98b413 1944 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1945err_interruptible:
1946 dev_priv->mm.interruptible = true;
48b956c5 1947 return ret;
6b95a207
KH		 1948}
1949
1690e1eb
CW		 1950void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1951{
1952 i915_gem_object_unpin_fence(obj);
cc98b413 1953 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1954}
1955
c2c75131
DV		 1956/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1957 * is assumed to be a power-of-two. */
bc752862
CW		 1958unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1959 unsigned int tiling_mode,
1960 unsigned int cpp,
1961 unsigned int pitch)
c2c75131 1962{
bc752862
CW		 1963 if (tiling_mode != I915_TILING_NONE) {
1964 unsigned int tile_rows, tiles;
c2c75131 1965
bc752862
CW		 1966 tile_rows = *y / 8;
1967 *y %= 8;
c2c75131 1968
bc752862
CW		 1969 tiles = *x / (512/cpp);
1970 *x %= 512/cpp;
1971
1972 return tile_rows * pitch * 8 + tiles * 4096;
1973 } else {
1974 unsigned int offset;
1975
1976 offset = *y * pitch + *x * cpp;
1977 *y = 0;
1978 *x = (offset & 4095) / cpp;
1979 return offset & -4096;
1980 }
c2c75131
DV		 1981}
1982
17638cd6
JB		 1983static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1984 int x, int y)
81255565
JB		 1985{
1986 struct drm_device *dev = crtc->dev;
1987 struct drm_i915_private *dev_priv = dev->dev_private;
1988 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1989 struct intel_framebuffer *intel_fb;
05394f39 1990 struct drm_i915_gem_object *obj;
81255565 1991 int plane = intel_crtc->plane;
e506a0c6 1992 unsigned long linear_offset;
81255565 1993 u32 dspcntr;
5eddb70b 1994 u32 reg;
81255565
JB		 1995
1996 switch (plane) {
1997 case 0:
1998 case 1:
1999 break;
2000 default:
84f44ce7 2001 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 2002 return -EINVAL;
2003 }
2004
2005 intel_fb = to_intel_framebuffer(fb);
2006 obj = intel_fb->obj;
81255565 2007
5eddb70b
CW		 2008 reg = DSPCNTR(plane);
2009 dspcntr = I915_READ(reg);
81255565
JB		 2010 /* Mask out pixel format bits in case we change it */
2011 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2012 switch (fb->pixel_format) {
2013 case DRM_FORMAT_C8:
81255565
JB		 2014 dspcntr |= DISPPLANE_8BPP;
2015 break;
57779d06
VS		 2016 case DRM_FORMAT_XRGB1555:
2017 case DRM_FORMAT_ARGB1555:
2018 dspcntr |= DISPPLANE_BGRX555;
81255565 2019 break;
57779d06
VS		 2020 case DRM_FORMAT_RGB565:
2021 dspcntr |= DISPPLANE_BGRX565;
2022 break;
2023 case DRM_FORMAT_XRGB8888:
2024 case DRM_FORMAT_ARGB8888:
2025 dspcntr |= DISPPLANE_BGRX888;
2026 break;
2027 case DRM_FORMAT_XBGR8888:
2028 case DRM_FORMAT_ABGR8888:
2029 dspcntr |= DISPPLANE_RGBX888;
2030 break;
2031 case DRM_FORMAT_XRGB2101010:
2032 case DRM_FORMAT_ARGB2101010:
2033 dspcntr |= DISPPLANE_BGRX101010;
2034 break;
2035 case DRM_FORMAT_XBGR2101010:
2036 case DRM_FORMAT_ABGR2101010:
2037 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2038 break;
2039 default:
baba133a 2040 BUG();
81255565 2041 }
57779d06 2042
a6c45cf0 2043 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2044 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2045 dspcntr |= DISPPLANE_TILED;
2046 else
2047 dspcntr &= ~DISPPLANE_TILED;
2048 }
2049
de1aa629
VS		 2050 if (IS_G4X(dev))
2051 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2052
5eddb70b 2053 I915_WRITE(reg, dspcntr);
81255565 2054
e506a0c6 2055 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2056
c2c75131
DV		 2057 if (INTEL_INFO(dev)->gen >= 4) {
2058 intel_crtc->dspaddr_offset =
bc752862
CW		 2059 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2060 fb->bits_per_pixel / 8,
2061 fb->pitches[0]);
c2c75131
DV		 2062 linear_offset -= intel_crtc->dspaddr_offset;
2063 } else {
e506a0c6 2064 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2065 }
e506a0c6 2066
f343c5f6
BW		 2067 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2068 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2069 fb->pitches[0]);
01f2c773 2070 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2071 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2072 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2073 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2074 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2075 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2076 } else
f343c5f6 2077 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2078 POSTING_READ(reg);
81255565 2079
17638cd6
JB		 2080 return 0;
2081}
2082
2083static int ironlake_update_plane(struct drm_crtc *crtc,
2084 struct drm_framebuffer *fb, int x, int y)
2085{
2086 struct drm_device *dev = crtc->dev;
2087 struct drm_i915_private *dev_priv = dev->dev_private;
2088 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2089 struct intel_framebuffer *intel_fb;
2090 struct drm_i915_gem_object *obj;
2091 int plane = intel_crtc->plane;
e506a0c6 2092 unsigned long linear_offset;
17638cd6
JB		 2093 u32 dspcntr;
2094 u32 reg;
2095
2096 switch (plane) {
2097 case 0:
2098 case 1:
27f8227b 2099 case 2:
17638cd6
JB		 2100 break;
2101 default:
84f44ce7 2102 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2103 return -EINVAL;
2104 }
2105
2106 intel_fb = to_intel_framebuffer(fb);
2107 obj = intel_fb->obj;
2108
2109 reg = DSPCNTR(plane);
2110 dspcntr = I915_READ(reg);
2111 /* Mask out pixel format bits in case we change it */
2112 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2113 switch (fb->pixel_format) {
2114 case DRM_FORMAT_C8:
17638cd6
JB		 2115 dspcntr |= DISPPLANE_8BPP;
2116 break;
57779d06
VS		 2117 case DRM_FORMAT_RGB565:
2118 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2119 break;
57779d06
VS		 2120 case DRM_FORMAT_XRGB8888:
2121 case DRM_FORMAT_ARGB8888:
2122 dspcntr |= DISPPLANE_BGRX888;
2123 break;
2124 case DRM_FORMAT_XBGR8888:
2125 case DRM_FORMAT_ABGR8888:
2126 dspcntr |= DISPPLANE_RGBX888;
2127 break;
2128 case DRM_FORMAT_XRGB2101010:
2129 case DRM_FORMAT_ARGB2101010:
2130 dspcntr |= DISPPLANE_BGRX101010;
2131 break;
2132 case DRM_FORMAT_XBGR2101010:
2133 case DRM_FORMAT_ABGR2101010:
2134 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2135 break;
2136 default:
baba133a 2137 BUG();
17638cd6
JB		 2138 }
2139
2140 if (obj->tiling_mode != I915_TILING_NONE)
2141 dspcntr |= DISPPLANE_TILED;
2142 else
2143 dspcntr &= ~DISPPLANE_TILED;
2144
1f5d76db
PZ		 2145 if (IS_HASWELL(dev))
2146 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2147 else
2148 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2149
2150 I915_WRITE(reg, dspcntr);
2151
e506a0c6 2152 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2153 intel_crtc->dspaddr_offset =
bc752862
CW		 2154 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2155 fb->bits_per_pixel / 8,
2156 fb->pitches[0]);
c2c75131 2157 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2158
f343c5f6
BW		 2159 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2160 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2161 fb->pitches[0]);
01f2c773 2162 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2163 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2164 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2165 if (IS_HASWELL(dev)) {
2166 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2167 } else {
2168 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2169 I915_WRITE(DSPLINOFF(plane), linear_offset);
2170 }
17638cd6
JB		 2171 POSTING_READ(reg);
2172
2173 return 0;
2174}
2175
2176/* Assume fb object is pinned & idle & fenced and just update base pointers */
2177static int
2178intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2179 int x, int y, enum mode_set_atomic state)
2180{
2181 struct drm_device *dev = crtc->dev;
2182 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2183
6b8e6ed0
CW		 2184 if (dev_priv->display.disable_fbc)
2185 dev_priv->display.disable_fbc(dev);
3dec0095 2186 intel_increase_pllclock(crtc);
81255565 2187
6b8e6ed0 2188 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2189}
2190
96a02917
VS		 2191void intel_display_handle_reset(struct drm_device *dev)
2192{
2193 struct drm_i915_private *dev_priv = dev->dev_private;
2194 struct drm_crtc *crtc;
2195
2196 /*
2197 * Flips in the rings have been nuked by the reset,
2198 * so complete all pending flips so that user space
2199 * will get its events and not get stuck.
2200 *
2201 * Also update the base address of all primary
2202 * planes to the the last fb to make sure we're
2203 * showing the correct fb after a reset.
2204 *
2205 * Need to make two loops over the crtcs so that we
2206 * don't try to grab a crtc mutex before the
2207 * pending_flip_queue really got woken up.
2208 */
2209
2210 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2211 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2212 enum plane plane = intel_crtc->plane;
2213
2214 intel_prepare_page_flip(dev, plane);
2215 intel_finish_page_flip_plane(dev, plane);
2216 }
2217
2218 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2219 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2220
2221 mutex_lock(&crtc->mutex);
2222 if (intel_crtc->active)
2223 dev_priv->display.update_plane(crtc, crtc->fb,
2224 crtc->x, crtc->y);
2225 mutex_unlock(&crtc->mutex);
2226 }
2227}
2228
14667a4b
CW		 2229static int
2230intel_finish_fb(struct drm_framebuffer *old_fb)
2231{
2232 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2233 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2234 bool was_interruptible = dev_priv->mm.interruptible;
2235 int ret;
2236
14667a4b
CW		 2237 /* Big Hammer, we also need to ensure that any pending
2238 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2239 * current scanout is retired before unpinning the old
2240 * framebuffer.
2241 *
2242 * This should only fail upon a hung GPU, in which case we
2243 * can safely continue.
2244 */
2245 dev_priv->mm.interruptible = false;
2246 ret = i915_gem_object_finish_gpu(obj);
2247 dev_priv->mm.interruptible = was_interruptible;
2248
2249 return ret;
2250}
2251
198598d0
VS		 2252static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2253{
2254 struct drm_device *dev = crtc->dev;
2255 struct drm_i915_master_private *master_priv;
2256 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2257
2258 if (!dev->primary->master)
2259 return;
2260
2261 master_priv = dev->primary->master->driver_priv;
2262 if (!master_priv->sarea_priv)
2263 return;
2264
2265 switch (intel_crtc->pipe) {
2266 case 0:
2267 master_priv->sarea_priv->pipeA_x = x;
2268 master_priv->sarea_priv->pipeA_y = y;
2269 break;
2270 case 1:
2271 master_priv->sarea_priv->pipeB_x = x;
2272 master_priv->sarea_priv->pipeB_y = y;
2273 break;
2274 default:
2275 break;
2276 }
2277}
2278
5c3b82e2 2279static int
3c4fdcfb 2280intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2281 struct drm_framebuffer *fb)
79e53945
JB		 2282{
2283 struct drm_device *dev = crtc->dev;
6b8e6ed0 2284 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2286 struct drm_framebuffer *old_fb;
5c3b82e2 2287 int ret;
79e53945
JB		 2288
2289 /* no fb bound */
94352cf9 2290 if (!fb) {
a5071c2f 2291 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2292 return 0;
2293 }
2294
7eb552ae 2295 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2296 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2297 plane_name(intel_crtc->plane),
2298 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2299 return -EINVAL;
79e53945
JB		 2300 }
2301
5c3b82e2 2302 mutex_lock(&dev->struct_mutex);
265db958 2303 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2304 to_intel_framebuffer(fb)->obj,
919926ae 2305 NULL);
5c3b82e2
CW		 2306 if (ret != 0) {
2307 mutex_unlock(&dev->struct_mutex);
a5071c2f 2308 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2309 return ret;
2310 }
79e53945 2311
bb2043de
DL		 2312 /*
2313 * Update pipe size and adjust fitter if needed: the reason for this is
2314 * that in compute_mode_changes we check the native mode (not the pfit
2315 * mode) to see if we can flip rather than do a full mode set. In the
2316 * fastboot case, we'll flip, but if we don't update the pipesrc and
2317 * pfit state, we'll end up with a big fb scanned out into the wrong
2318 * sized surface.
2319 *
2320 * To fix this properly, we need to hoist the checks up into
2321 * compute_mode_changes (or above), check the actual pfit state and
2322 * whether the platform allows pfit disable with pipe active, and only
2323 * then update the pipesrc and pfit state, even on the flip path.
2324 */
4d6a3e63 2325 if (i915_fastboot) {
d7bf63f2
DL		 2326 const struct drm_display_mode *adjusted_mode =
2327 &intel_crtc->config.adjusted_mode;
2328
4d6a3e63 2329 I915_WRITE(PIPESRC(intel_crtc->pipe),
d7bf63f2
DL		 2330 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2331 (adjusted_mode->crtc_vdisplay - 1));
fd4daa9c 2332 if (!intel_crtc->config.pch_pfit.enabled &&
4d6a3e63
JB		 2333 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2334 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2335 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2336 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2337 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2338 }
2339 }
2340
94352cf9 2341 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2342 if (ret) {
94352cf9 2343 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2344 mutex_unlock(&dev->struct_mutex);
a5071c2f 2345 DRM_ERROR("failed to update base address\n");
4e6cfefc 2346 return ret;
79e53945 2347 }
3c4fdcfb 2348
94352cf9
DV		 2349 old_fb = crtc->fb;
2350 crtc->fb = fb;
6c4c86f5
DV		 2351 crtc->x = x;
2352 crtc->y = y;
94352cf9 2353
b7f1de28 2354 if (old_fb) {
d7697eea
DV		 2355 if (intel_crtc->active && old_fb != fb)
2356 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2357 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2358 }
652c393a 2359
6b8e6ed0 2360 intel_update_fbc(dev);
4906557e 2361 intel_edp_psr_update(dev);
5c3b82e2 2362 mutex_unlock(&dev->struct_mutex);
79e53945 2363
198598d0 2364 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2365
2366 return 0;
79e53945
JB		 2367}
2368
5e84e1a4
ZW		 2369static void intel_fdi_normal_train(struct drm_crtc *crtc)
2370{
2371 struct drm_device *dev = crtc->dev;
2372 struct drm_i915_private *dev_priv = dev->dev_private;
2373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2374 int pipe = intel_crtc->pipe;
2375 u32 reg, temp;
2376
2377 /* enable normal train */
2378 reg = FDI_TX_CTL(pipe);
2379 temp = I915_READ(reg);
61e499bf 2380 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2381 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2382 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2383 } else {
2384 temp &= ~FDI_LINK_TRAIN_NONE;
2385 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2386 }
5e84e1a4
ZW		 2387 I915_WRITE(reg, temp);
2388
2389 reg = FDI_RX_CTL(pipe);
2390 temp = I915_READ(reg);
2391 if (HAS_PCH_CPT(dev)) {
2392 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2393 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2394 } else {
2395 temp &= ~FDI_LINK_TRAIN_NONE;
2396 temp |= FDI_LINK_TRAIN_NONE;
2397 }
2398 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2399
2400 /* wait one idle pattern time */
2401 POSTING_READ(reg);
2402 udelay(1000);
357555c0
JB		 2403
2404 /* IVB wants error correction enabled */
2405 if (IS_IVYBRIDGE(dev))
2406 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2407 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2408}
2409
1e833f40
DV		 2410static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2411{
2412 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2413}
2414
01a415fd
DV		 2415static void ivb_modeset_global_resources(struct drm_device *dev)
2416{
2417 struct drm_i915_private *dev_priv = dev->dev_private;
2418 struct intel_crtc *pipe_B_crtc =
2419 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2420 struct intel_crtc *pipe_C_crtc =
2421 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2422 uint32_t temp;
2423
1e833f40
DV		 2424 /*
2425 * When everything is off disable fdi C so that we could enable fdi B
2426 * with all lanes. Note that we don't care about enabled pipes without
2427 * an enabled pch encoder.
2428 */
2429 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2430 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2431 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2432 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2433
2434 temp = I915_READ(SOUTH_CHICKEN1);
2435 temp &= ~FDI_BC_BIFURCATION_SELECT;
2436 DRM_DEBUG_KMS("disabling fdi C rx\n");
2437 I915_WRITE(SOUTH_CHICKEN1, temp);
2438 }
2439}
2440
8db9d77b
ZW		 2441/* The FDI link training functions for ILK/Ibexpeak. */
2442static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2443{
2444 struct drm_device *dev = crtc->dev;
2445 struct drm_i915_private *dev_priv = dev->dev_private;
2446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2447 int pipe = intel_crtc->pipe;
0fc932b8 2448 int plane = intel_crtc->plane;
5eddb70b 2449 u32 reg, temp, tries;
8db9d77b 2450
0fc932b8
JB		 2451 /* FDI needs bits from pipe & plane first */
2452 assert_pipe_enabled(dev_priv, pipe);
2453 assert_plane_enabled(dev_priv, plane);
2454
e1a44743
AJ		 2455 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2456 for train result */
5eddb70b
CW		 2457 reg = FDI_RX_IMR(pipe);
2458 temp = I915_READ(reg);
e1a44743
AJ		 2459 temp &= ~FDI_RX_SYMBOL_LOCK;
2460 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2461 I915_WRITE(reg, temp);
2462 I915_READ(reg);
e1a44743
AJ		 2463 udelay(150);
2464
8db9d77b 2465 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2466 reg = FDI_TX_CTL(pipe);
2467 temp = I915_READ(reg);
627eb5a3
DV		 2468 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2469 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2470 temp &= ~FDI_LINK_TRAIN_NONE;
2471 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2472 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2473
5eddb70b
CW		 2474 reg = FDI_RX_CTL(pipe);
2475 temp = I915_READ(reg);
8db9d77b
ZW		 2476 temp &= ~FDI_LINK_TRAIN_NONE;
2477 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2478 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2479
2480 POSTING_READ(reg);
8db9d77b
ZW		 2481 udelay(150);
2482
5b2adf89 2483 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2484 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2485 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2486 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2487
5eddb70b 2488 reg = FDI_RX_IIR(pipe);
e1a44743 2489 for (tries = 0; tries < 5; tries++) {
5eddb70b 2490 temp = I915_READ(reg);
8db9d77b
ZW		 2491 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2492
2493 if ((temp & FDI_RX_BIT_LOCK)) {
2494 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2495 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2496 break;
2497 }
8db9d77b 2498 }
e1a44743 2499 if (tries == 5)
5eddb70b 2500 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2501
2502 /* Train 2 */
5eddb70b
CW		 2503 reg = FDI_TX_CTL(pipe);
2504 temp = I915_READ(reg);
8db9d77b
ZW		 2505 temp &= ~FDI_LINK_TRAIN_NONE;
2506 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2507 I915_WRITE(reg, temp);
8db9d77b 2508
5eddb70b
CW		 2509 reg = FDI_RX_CTL(pipe);
2510 temp = I915_READ(reg);
8db9d77b
ZW		 2511 temp &= ~FDI_LINK_TRAIN_NONE;
2512 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2513 I915_WRITE(reg, temp);
8db9d77b 2514
5eddb70b
CW		 2515 POSTING_READ(reg);
2516 udelay(150);
8db9d77b 2517
5eddb70b 2518 reg = FDI_RX_IIR(pipe);
e1a44743 2519 for (tries = 0; tries < 5; tries++) {
5eddb70b 2520 temp = I915_READ(reg);
8db9d77b
ZW		 2521 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2522
2523 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2524 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2525 DRM_DEBUG_KMS("FDI train 2 done.\n");
2526 break;
2527 }
8db9d77b 2528 }
e1a44743 2529 if (tries == 5)
5eddb70b 2530 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2531
2532 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2533
8db9d77b
ZW		 2534}
2535
0206e353 2536static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2537 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2538 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2539 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2540 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2541};
2542
2543/* The FDI link training functions for SNB/Cougarpoint. */
2544static void gen6_fdi_link_train(struct drm_crtc *crtc)
2545{
2546 struct drm_device *dev = crtc->dev;
2547 struct drm_i915_private *dev_priv = dev->dev_private;
2548 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2549 int pipe = intel_crtc->pipe;
fa37d39e 2550 u32 reg, temp, i, retry;
8db9d77b 2551
e1a44743
AJ		 2552 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2553 for train result */
5eddb70b
CW		 2554 reg = FDI_RX_IMR(pipe);
2555 temp = I915_READ(reg);
e1a44743
AJ		 2556 temp &= ~FDI_RX_SYMBOL_LOCK;
2557 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2558 I915_WRITE(reg, temp);
2559
2560 POSTING_READ(reg);
e1a44743
AJ		 2561 udelay(150);
2562
8db9d77b 2563 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2564 reg = FDI_TX_CTL(pipe);
2565 temp = I915_READ(reg);
627eb5a3
DV		 2566 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2567 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2568 temp &= ~FDI_LINK_TRAIN_NONE;
2569 temp |= FDI_LINK_TRAIN_PATTERN_1;
2570 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2571 /* SNB-B */
2572 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2573 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2574
d74cf324
DV		 2575 I915_WRITE(FDI_RX_MISC(pipe),
2576 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2577
5eddb70b
CW		 2578 reg = FDI_RX_CTL(pipe);
2579 temp = I915_READ(reg);
8db9d77b
ZW		 2580 if (HAS_PCH_CPT(dev)) {
2581 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2582 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2583 } else {
2584 temp &= ~FDI_LINK_TRAIN_NONE;
2585 temp |= FDI_LINK_TRAIN_PATTERN_1;
2586 }
5eddb70b
CW		 2587 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2588
2589 POSTING_READ(reg);
8db9d77b
ZW		 2590 udelay(150);
2591
0206e353 2592 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2593 reg = FDI_TX_CTL(pipe);
2594 temp = I915_READ(reg);
8db9d77b
ZW		 2595 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2596 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2597 I915_WRITE(reg, temp);
2598
2599 POSTING_READ(reg);
8db9d77b
ZW		 2600 udelay(500);
2601
fa37d39e
SP		 2602 for (retry = 0; retry < 5; retry++) {
2603 reg = FDI_RX_IIR(pipe);
2604 temp = I915_READ(reg);
2605 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2606 if (temp & FDI_RX_BIT_LOCK) {
2607 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2608 DRM_DEBUG_KMS("FDI train 1 done.\n");
2609 break;
2610 }
2611 udelay(50);
8db9d77b 2612 }
fa37d39e
SP		 2613 if (retry < 5)
2614 break;
8db9d77b
ZW		 2615 }
2616 if (i == 4)
5eddb70b 2617 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2618
2619 /* Train 2 */
5eddb70b
CW		 2620 reg = FDI_TX_CTL(pipe);
2621 temp = I915_READ(reg);
8db9d77b
ZW		 2622 temp &= ~FDI_LINK_TRAIN_NONE;
2623 temp |= FDI_LINK_TRAIN_PATTERN_2;
2624 if (IS_GEN6(dev)) {
2625 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2626 /* SNB-B */
2627 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2628 }
5eddb70b 2629 I915_WRITE(reg, temp);
8db9d77b 2630
5eddb70b
CW		 2631 reg = FDI_RX_CTL(pipe);
2632 temp = I915_READ(reg);
8db9d77b
ZW		 2633 if (HAS_PCH_CPT(dev)) {
2634 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2635 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2636 } else {
2637 temp &= ~FDI_LINK_TRAIN_NONE;
2638 temp |= FDI_LINK_TRAIN_PATTERN_2;
2639 }
5eddb70b
CW		 2640 I915_WRITE(reg, temp);
2641
2642 POSTING_READ(reg);
8db9d77b
ZW		 2643 udelay(150);
2644
0206e353 2645 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2646 reg = FDI_TX_CTL(pipe);
2647 temp = I915_READ(reg);
8db9d77b
ZW		 2648 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2649 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2650 I915_WRITE(reg, temp);
2651
2652 POSTING_READ(reg);
8db9d77b
ZW		 2653 udelay(500);
2654
fa37d39e
SP		 2655 for (retry = 0; retry < 5; retry++) {
2656 reg = FDI_RX_IIR(pipe);
2657 temp = I915_READ(reg);
2658 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2659 if (temp & FDI_RX_SYMBOL_LOCK) {
2660 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2661 DRM_DEBUG_KMS("FDI train 2 done.\n");
2662 break;
2663 }
2664 udelay(50);
8db9d77b 2665 }
fa37d39e
SP		 2666 if (retry < 5)
2667 break;
8db9d77b
ZW		 2668 }
2669 if (i == 4)
5eddb70b 2670 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2671
2672 DRM_DEBUG_KMS("FDI train done.\n");
2673}
2674
357555c0
JB		 2675/* Manual link training for Ivy Bridge A0 parts */
2676static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2677{
2678 struct drm_device *dev = crtc->dev;
2679 struct drm_i915_private *dev_priv = dev->dev_private;
2680 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2681 int pipe = intel_crtc->pipe;
139ccd3f 2682 u32 reg, temp, i, j;
357555c0
JB		 2683
2684 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2685 for train result */
2686 reg = FDI_RX_IMR(pipe);
2687 temp = I915_READ(reg);
2688 temp &= ~FDI_RX_SYMBOL_LOCK;
2689 temp &= ~FDI_RX_BIT_LOCK;
2690 I915_WRITE(reg, temp);
2691
2692 POSTING_READ(reg);
2693 udelay(150);
2694
01a415fd
DV		 2695 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2696 I915_READ(FDI_RX_IIR(pipe)));
2697
139ccd3f
JB		 2698 /* Try each vswing and preemphasis setting twice before moving on */
2699 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2700 /* disable first in case we need to retry */
2701 reg = FDI_TX_CTL(pipe);
2702 temp = I915_READ(reg);
2703 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2704 temp &= ~FDI_TX_ENABLE;
2705 I915_WRITE(reg, temp);
357555c0 2706
139ccd3f
JB		 2707 reg = FDI_RX_CTL(pipe);
2708 temp = I915_READ(reg);
2709 temp &= ~FDI_LINK_TRAIN_AUTO;
2710 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2711 temp &= ~FDI_RX_ENABLE;
2712 I915_WRITE(reg, temp);
357555c0 2713
139ccd3f 2714 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2715 reg = FDI_TX_CTL(pipe);
2716 temp = I915_READ(reg);
139ccd3f
JB		 2717 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2718 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2719 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2720 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2721 temp |= snb_b_fdi_train_param[j/2];
2722 temp |= FDI_COMPOSITE_SYNC;
2723 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2724
139ccd3f
JB		 2725 I915_WRITE(FDI_RX_MISC(pipe),
2726 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2727
139ccd3f 2728 reg = FDI_RX_CTL(pipe);
357555c0 2729 temp = I915_READ(reg);
139ccd3f
JB		 2730 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2731 temp |= FDI_COMPOSITE_SYNC;
2732 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2733
139ccd3f
JB		 2734 POSTING_READ(reg);
2735 udelay(1); /* should be 0.5us */
357555c0 2736
139ccd3f
JB		 2737 for (i = 0; i < 4; i++) {
2738 reg = FDI_RX_IIR(pipe);
2739 temp = I915_READ(reg);
2740 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2741
139ccd3f
JB		 2742 if (temp & FDI_RX_BIT_LOCK ||
2743 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2744 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2745 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2746 i);
2747 break;
2748 }
2749 udelay(1); /* should be 0.5us */
2750 }
2751 if (i == 4) {
2752 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2753 continue;
2754 }
357555c0 2755
139ccd3f 2756 /* Train 2 */
357555c0
JB		 2757 reg = FDI_TX_CTL(pipe);
2758 temp = I915_READ(reg);
139ccd3f
JB		 2759 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2760 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2761 I915_WRITE(reg, temp);
2762
2763 reg = FDI_RX_CTL(pipe);
2764 temp = I915_READ(reg);
2765 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2766 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2767 I915_WRITE(reg, temp);
2768
2769 POSTING_READ(reg);
139ccd3f 2770 udelay(2); /* should be 1.5us */
357555c0 2771
139ccd3f
JB		 2772 for (i = 0; i < 4; i++) {
2773 reg = FDI_RX_IIR(pipe);
2774 temp = I915_READ(reg);
2775 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2776
139ccd3f
JB		 2777 if (temp & FDI_RX_SYMBOL_LOCK ||
2778 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2779 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2780 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2781 i);
2782 goto train_done;
2783 }
2784 udelay(2); /* should be 1.5us */
357555c0 2785 }
139ccd3f
JB		 2786 if (i == 4)
2787 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2788 }
357555c0 2789
139ccd3f 2790train_done:
357555c0
JB		 2791 DRM_DEBUG_KMS("FDI train done.\n");
2792}
2793
88cefb6c 2794static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2795{
88cefb6c 2796 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2797 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2798 int pipe = intel_crtc->pipe;
5eddb70b 2799 u32 reg, temp;
79e53945 2800
c64e311e 2801
c98e9dcf 2802 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2803 reg = FDI_RX_CTL(pipe);
2804 temp = I915_READ(reg);
627eb5a3
DV		 2805 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2806 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2807 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2808 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2809
2810 POSTING_READ(reg);
c98e9dcf
JB		 2811 udelay(200);
2812
2813 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2814 temp = I915_READ(reg);
2815 I915_WRITE(reg, temp | FDI_PCDCLK);
2816
2817 POSTING_READ(reg);
c98e9dcf
JB		 2818 udelay(200);
2819
20749730
PZ		 2820 /* Enable CPU FDI TX PLL, always on for Ironlake */
2821 reg = FDI_TX_CTL(pipe);
2822 temp = I915_READ(reg);
2823 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2824 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2825
20749730
PZ		 2826 POSTING_READ(reg);
2827 udelay(100);
6be4a607 2828 }
0e23b99d
JB		 2829}
2830
88cefb6c
DV		 2831static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2832{
2833 struct drm_device *dev = intel_crtc->base.dev;
2834 struct drm_i915_private *dev_priv = dev->dev_private;
2835 int pipe = intel_crtc->pipe;
2836 u32 reg, temp;
2837
2838 /* Switch from PCDclk to Rawclk */
2839 reg = FDI_RX_CTL(pipe);
2840 temp = I915_READ(reg);
2841 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2842
2843 /* Disable CPU FDI TX PLL */
2844 reg = FDI_TX_CTL(pipe);
2845 temp = I915_READ(reg);
2846 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2847
2848 POSTING_READ(reg);
2849 udelay(100);
2850
2851 reg = FDI_RX_CTL(pipe);
2852 temp = I915_READ(reg);
2853 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2854
2855 /* Wait for the clocks to turn off. */
2856 POSTING_READ(reg);
2857 udelay(100);
2858}
2859
0fc932b8
JB		 2860static void ironlake_fdi_disable(struct drm_crtc *crtc)
2861{
2862 struct drm_device *dev = crtc->dev;
2863 struct drm_i915_private *dev_priv = dev->dev_private;
2864 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2865 int pipe = intel_crtc->pipe;
2866 u32 reg, temp;
2867
2868 /* disable CPU FDI tx and PCH FDI rx */
2869 reg = FDI_TX_CTL(pipe);
2870 temp = I915_READ(reg);
2871 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2872 POSTING_READ(reg);
2873
2874 reg = FDI_RX_CTL(pipe);
2875 temp = I915_READ(reg);
2876 temp &= ~(0x7 << 16);
dfd07d72 2877 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2878 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2879
2880 POSTING_READ(reg);
2881 udelay(100);
2882
2883 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2884 if (HAS_PCH_IBX(dev)) {
2885 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2886 }
0fc932b8
JB		 2887
2888 /* still set train pattern 1 */
2889 reg = FDI_TX_CTL(pipe);
2890 temp = I915_READ(reg);
2891 temp &= ~FDI_LINK_TRAIN_NONE;
2892 temp |= FDI_LINK_TRAIN_PATTERN_1;
2893 I915_WRITE(reg, temp);
2894
2895 reg = FDI_RX_CTL(pipe);
2896 temp = I915_READ(reg);
2897 if (HAS_PCH_CPT(dev)) {
2898 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2899 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2900 } else {
2901 temp &= ~FDI_LINK_TRAIN_NONE;
2902 temp |= FDI_LINK_TRAIN_PATTERN_1;
2903 }
2904 /* BPC in FDI rx is consistent with that in PIPECONF */
2905 temp &= ~(0x07 << 16);
dfd07d72 2906 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2907 I915_WRITE(reg, temp);
2908
2909 POSTING_READ(reg);
2910 udelay(100);
2911}
2912
5bb61643
CW		 2913static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2914{
2915 struct drm_device *dev = crtc->dev;
2916 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2918 unsigned long flags;
2919 bool pending;
2920
10d83730
VS		 2921 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2922 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2923 return false;
2924
2925 spin_lock_irqsave(&dev->event_lock, flags);
2926 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2927 spin_unlock_irqrestore(&dev->event_lock, flags);
2928
2929 return pending;
2930}
2931
e6c3a2a6
CW		 2932static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2933{
0f91128d 2934 struct drm_device *dev = crtc->dev;
5bb61643 2935 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2936
2937 if (crtc->fb == NULL)
2938 return;
2939
2c10d571
DV		 2940 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2941
5bb61643
CW		 2942 wait_event(dev_priv->pending_flip_queue,
2943 !intel_crtc_has_pending_flip(crtc));
2944
0f91128d
CW		 2945 mutex_lock(&dev->struct_mutex);
2946 intel_finish_fb(crtc->fb);
2947 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2948}
2949
e615efe4
ED		 2950/* Program iCLKIP clock to the desired frequency */
2951static void lpt_program_iclkip(struct drm_crtc *crtc)
2952{
2953 struct drm_device *dev = crtc->dev;
2954 struct drm_i915_private *dev_priv = dev->dev_private;
241bfc38 2955 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
e615efe4
ED		 2956 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2957 u32 temp;
2958
09153000
DV		 2959 mutex_lock(&dev_priv->dpio_lock);
2960
e615efe4
ED		 2961 /* It is necessary to ungate the pixclk gate prior to programming
2962 * the divisors, and gate it back when it is done.
2963 */
2964 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2965
2966 /* Disable SSCCTL */
2967 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2968 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2969 SBI_SSCCTL_DISABLE,
2970 SBI_ICLK);
e615efe4
ED		 2971
2972 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 2973 if (clock == 20000) {
e615efe4
ED		 2974 auxdiv = 1;
2975 divsel = 0x41;
2976 phaseinc = 0x20;
2977 } else {
2978 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 2979 * but the adjusted_mode->crtc_clock in in KHz. To get the
2980 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 2981 * convert the virtual clock precision to KHz here for higher
2982 * precision.
2983 */
2984 u32 iclk_virtual_root_freq = 172800 * 1000;
2985 u32 iclk_pi_range = 64;
2986 u32 desired_divisor, msb_divisor_value, pi_value;
2987
12d7ceed 2988 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 2989 msb_divisor_value = desired_divisor / iclk_pi_range;
2990 pi_value = desired_divisor % iclk_pi_range;
2991
2992 auxdiv = 0;
2993 divsel = msb_divisor_value - 2;
2994 phaseinc = pi_value;
2995 }
2996
2997 /* This should not happen with any sane values */
2998 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2999 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3000 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3001 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3002
3003 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3004 clock,
e615efe4
ED		 3005 auxdiv,
3006 divsel,
3007 phasedir,
3008 phaseinc);
3009
3010 /* Program SSCDIVINTPHASE6 */
988d6ee8 3011 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3012 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3013 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3014 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3015 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3016 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3017 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3018 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3019
3020 /* Program SSCAUXDIV */
988d6ee8 3021 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3022 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3023 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3024 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3025
3026 /* Enable modulator and associated divider */
988d6ee8 3027 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3028 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3029 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3030
3031 /* Wait for initialization time */
3032 udelay(24);
3033
3034 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3035
3036 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3037}
3038
275f01b2
DV		 3039static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3040 enum pipe pch_transcoder)
3041{
3042 struct drm_device *dev = crtc->base.dev;
3043 struct drm_i915_private *dev_priv = dev->dev_private;
3044 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3045
3046 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3047 I915_READ(HTOTAL(cpu_transcoder)));
3048 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3049 I915_READ(HBLANK(cpu_transcoder)));
3050 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3051 I915_READ(HSYNC(cpu_transcoder)));
3052
3053 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3054 I915_READ(VTOTAL(cpu_transcoder)));
3055 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3056 I915_READ(VBLANK(cpu_transcoder)));
3057 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3058 I915_READ(VSYNC(cpu_transcoder)));
3059 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3060 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3061}
3062
f67a559d
JB		 3063/*
3064 * Enable PCH resources required for PCH ports:
3065 * - PCH PLLs
3066 * - FDI training & RX/TX
3067 * - update transcoder timings
3068 * - DP transcoding bits
3069 * - transcoder
3070 */
3071static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3072{
3073 struct drm_device *dev = crtc->dev;
3074 struct drm_i915_private *dev_priv = dev->dev_private;
3075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3076 int pipe = intel_crtc->pipe;
ee7b9f93 3077 u32 reg, temp;
2c07245f 3078
ab9412ba 3079 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3080
cd986abb
DV		 3081 /* Write the TU size bits before fdi link training, so that error
3082 * detection works. */
3083 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3084 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3085
c98e9dcf 3086 /* For PCH output, training FDI link */
674cf967 3087 dev_priv->display.fdi_link_train(crtc);
2c07245f 3088
3ad8a208
DV		 3089 /* We need to program the right clock selection before writing the pixel
3090 * mutliplier into the DPLL. */
303b81e0 3091 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3092 u32 sel;
4b645f14 3093
c98e9dcf 3094 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3095 temp |= TRANS_DPLL_ENABLE(pipe);
3096 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3097 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3098 temp |= sel;
3099 else
3100 temp &= ~sel;
c98e9dcf 3101 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3102 }
5eddb70b 3103
3ad8a208
DV		 3104 /* XXX: pch pll's can be enabled any time before we enable the PCH
3105 * transcoder, and we actually should do this to not upset any PCH
3106 * transcoder that already use the clock when we share it.
3107 *
3108 * Note that enable_shared_dpll tries to do the right thing, but
3109 * get_shared_dpll unconditionally resets the pll - we need that to have
3110 * the right LVDS enable sequence. */
3111 ironlake_enable_shared_dpll(intel_crtc);
3112
d9b6cb56
JB		 3113 /* set transcoder timing, panel must allow it */
3114 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3115 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3116
303b81e0 3117 intel_fdi_normal_train(crtc);
5e84e1a4 3118
c98e9dcf
JB		 3119 /* For PCH DP, enable TRANS_DP_CTL */
3120 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3121 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3122 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3123 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3124 reg = TRANS_DP_CTL(pipe);
3125 temp = I915_READ(reg);
3126 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3127 TRANS_DP_SYNC_MASK |
3128 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3129 temp |= (TRANS_DP_OUTPUT_ENABLE |
3130 TRANS_DP_ENH_FRAMING);
9325c9f0 3131 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3132
3133 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3134 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3135 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3136 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3137
3138 switch (intel_trans_dp_port_sel(crtc)) {
3139 case PCH_DP_B:
5eddb70b 3140 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3141 break;
3142 case PCH_DP_C:
5eddb70b 3143 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3144 break;
3145 case PCH_DP_D:
5eddb70b 3146 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3147 break;
3148 default:
e95d41e1 3149 BUG();
32f9d658 3150 }
2c07245f 3151
5eddb70b 3152 I915_WRITE(reg, temp);
6be4a607 3153 }
b52eb4dc 3154
b8a4f404 3155 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3156}
3157
1507e5bd
PZ		 3158static void lpt_pch_enable(struct drm_crtc *crtc)
3159{
3160 struct drm_device *dev = crtc->dev;
3161 struct drm_i915_private *dev_priv = dev->dev_private;
3162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3163 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3164
ab9412ba 3165 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3166
8c52b5e8 3167 lpt_program_iclkip(crtc);
1507e5bd 3168
0540e488 3169 /* Set transcoder timing. */
275f01b2 3170 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3171
937bb610 3172 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3173}
3174
e2b78267 3175static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3176{
e2b78267 3177 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3178
3179 if (pll == NULL)
3180 return;
3181
3182 if (pll->refcount == 0) {
46edb027 3183 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3184 return;
3185 }
3186
f4a091c7
DV		 3187 if (--pll->refcount == 0) {
3188 WARN_ON(pll->on);
3189 WARN_ON(pll->active);
3190 }
3191
a43f6e0f 3192 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3193}
3194
b89a1d39 3195static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3196{
e2b78267
DV		 3197 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3198 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3199 enum intel_dpll_id i;
ee7b9f93 3200
ee7b9f93 3201 if (pll) {
46edb027
DV		 3202 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3203 crtc->base.base.id, pll->name);
e2b78267 3204 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3205 }
3206
98b6bd99
DV		 3207 if (HAS_PCH_IBX(dev_priv->dev)) {
3208 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3209 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3210 pll = &dev_priv->shared_dplls[i];
98b6bd99 3211
46edb027
DV		 3212 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3213 crtc->base.base.id, pll->name);
98b6bd99
DV		 3214
3215 goto found;
3216 }
3217
e72f9fbf
DV		 3218 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3219 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3220
3221 /* Only want to check enabled timings first */
3222 if (pll->refcount == 0)
3223 continue;
3224
b89a1d39
DV		 3225 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3226 sizeof(pll->hw_state)) == 0) {
46edb027 3227 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3228 crtc->base.base.id,
46edb027 3229 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3230
3231 goto found;
3232 }
3233 }
3234
3235 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3236 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3237 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3238 if (pll->refcount == 0) {
46edb027
DV		 3239 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3240 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3241 goto found;
3242 }
3243 }
3244
3245 return NULL;
3246
3247found:
a43f6e0f 3248 crtc->config.shared_dpll = i;
46edb027
DV		 3249 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3250 pipe_name(crtc->pipe));
ee7b9f93 3251
cdbd2316 3252 if (pll->active == 0) {
66e985c0
DV		 3253 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3254 sizeof(pll->hw_state));
3255
46edb027 3256 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3257 WARN_ON(pll->on);
e9d6944e 3258 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3259
15bdd4cf 3260 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3261 }
3262 pll->refcount++;
e04c7350 3263
ee7b9f93
JB		 3264 return pll;
3265}
3266
a1520318 3267static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3268{
3269 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3270 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3271 u32 temp;
3272
3273 temp = I915_READ(dslreg);
3274 udelay(500);
3275 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3276 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3277 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3278 }
3279}
3280
b074cec8
JB		 3281static void ironlake_pfit_enable(struct intel_crtc *crtc)
3282{
3283 struct drm_device *dev = crtc->base.dev;
3284 struct drm_i915_private *dev_priv = dev->dev_private;
3285 int pipe = crtc->pipe;
3286
fd4daa9c 3287 if (crtc->config.pch_pfit.enabled) {
b074cec8
JB		 3288 /* Force use of hard-coded filter coefficients
3289 * as some pre-programmed values are broken,
3290 * e.g. x201.
3291 */
3292 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3293 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3294 PF_PIPE_SEL_IVB(pipe));
3295 else
3296 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3297 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3298 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3299 }
3300}
3301
bb53d4ae
VS		 3302static void intel_enable_planes(struct drm_crtc *crtc)
3303{
3304 struct drm_device *dev = crtc->dev;
3305 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3306 struct intel_plane *intel_plane;
3307
3308 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3309 if (intel_plane->pipe == pipe)
3310 intel_plane_restore(&intel_plane->base);
3311}
3312
3313static void intel_disable_planes(struct drm_crtc *crtc)
3314{
3315 struct drm_device *dev = crtc->dev;
3316 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3317 struct intel_plane *intel_plane;
3318
3319 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3320 if (intel_plane->pipe == pipe)
3321 intel_plane_disable(&intel_plane->base);
3322}
3323
d77e4531
PZ		 3324static void hsw_enable_ips(struct intel_crtc *crtc)
3325{
3326 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3327
3328 if (!crtc->config.ips_enabled)
3329 return;
3330
3331 /* We can only enable IPS after we enable a plane and wait for a vblank.
3332 * We guarantee that the plane is enabled by calling intel_enable_ips
3333 * only after intel_enable_plane. And intel_enable_plane already waits
3334 * for a vblank, so all we need to do here is to enable the IPS bit. */
3335 assert_plane_enabled(dev_priv, crtc->plane);
3336 I915_WRITE(IPS_CTL, IPS_ENABLE);
3337}
3338
3339static void hsw_disable_ips(struct intel_crtc *crtc)
3340{
3341 struct drm_device *dev = crtc->base.dev;
3342 struct drm_i915_private *dev_priv = dev->dev_private;
3343
3344 if (!crtc->config.ips_enabled)
3345 return;
3346
3347 assert_plane_enabled(dev_priv, crtc->plane);
3348 I915_WRITE(IPS_CTL, 0);
3349 POSTING_READ(IPS_CTL);
3350
3351 /* We need to wait for a vblank before we can disable the plane. */
3352 intel_wait_for_vblank(dev, crtc->pipe);
3353}
3354
3355/** Loads the palette/gamma unit for the CRTC with the prepared values */
3356static void intel_crtc_load_lut(struct drm_crtc *crtc)
3357{
3358 struct drm_device *dev = crtc->dev;
3359 struct drm_i915_private *dev_priv = dev->dev_private;
3360 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3361 enum pipe pipe = intel_crtc->pipe;
3362 int palreg = PALETTE(pipe);
3363 int i;
3364 bool reenable_ips = false;
3365
3366 /* The clocks have to be on to load the palette. */
3367 if (!crtc->enabled || !intel_crtc->active)
3368 return;
3369
3370 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3371 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3372 assert_dsi_pll_enabled(dev_priv);
3373 else
3374 assert_pll_enabled(dev_priv, pipe);
3375 }
3376
3377 /* use legacy palette for Ironlake */
3378 if (HAS_PCH_SPLIT(dev))
3379 palreg = LGC_PALETTE(pipe);
3380
3381 /* Workaround : Do not read or write the pipe palette/gamma data while
3382 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3383 */
3384 if (intel_crtc->config.ips_enabled &&
3385 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3386 GAMMA_MODE_MODE_SPLIT)) {
3387 hsw_disable_ips(intel_crtc);
3388 reenable_ips = true;
3389 }
3390
3391 for (i = 0; i < 256; i++) {
3392 I915_WRITE(palreg + 4 * i,
3393 (intel_crtc->lut_r[i] << 16) |
3394 (intel_crtc->lut_g[i] << 8) |
3395 intel_crtc->lut_b[i]);
3396 }
3397
3398 if (reenable_ips)
3399 hsw_enable_ips(intel_crtc);
3400}
3401
f67a559d
JB		 3402static void ironlake_crtc_enable(struct drm_crtc *crtc)
3403{
3404 struct drm_device *dev = crtc->dev;
3405 struct drm_i915_private *dev_priv = dev->dev_private;
3406 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3407 struct intel_encoder *encoder;
f67a559d
JB		 3408 int pipe = intel_crtc->pipe;
3409 int plane = intel_crtc->plane;
f67a559d 3410
08a48469
DV		 3411 WARN_ON(!crtc->enabled);
3412
f67a559d
JB		 3413 if (intel_crtc->active)
3414 return;
3415
3416 intel_crtc->active = true;
8664281b
PZ		 3417
3418 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3419 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3420
f6736a1a 3421 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3422 if (encoder->pre_enable)
3423 encoder->pre_enable(encoder);
f67a559d 3424
5bfe2ac0 3425 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3426 /* Note: FDI PLL enabling _must_ be done before we enable the
3427 * cpu pipes, hence this is separate from all the other fdi/pch
3428 * enabling. */
88cefb6c 3429 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3430 } else {
3431 assert_fdi_tx_disabled(dev_priv, pipe);
3432 assert_fdi_rx_disabled(dev_priv, pipe);
3433 }
f67a559d 3434
b074cec8 3435 ironlake_pfit_enable(intel_crtc);
f67a559d 3436
9c54c0dd
JB		 3437 /*
3438 * On ILK+ LUT must be loaded before the pipe is running but with
3439 * clocks enabled
3440 */
3441 intel_crtc_load_lut(crtc);
3442
f37fcc2a 3443 intel_update_watermarks(crtc);
5bfe2ac0 3444 intel_enable_pipe(dev_priv, pipe,
23538ef1 3445 intel_crtc->config.has_pch_encoder, false);
f67a559d 3446 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3447 intel_enable_planes(crtc);
5c38d48c 3448 intel_crtc_update_cursor(crtc, true);
f67a559d 3449
5bfe2ac0 3450 if (intel_crtc->config.has_pch_encoder)
f67a559d 3451 ironlake_pch_enable(crtc);
c98e9dcf 3452
d1ebd816 3453 mutex_lock(&dev->struct_mutex);
bed4a673 3454 intel_update_fbc(dev);
d1ebd816
BW		 3455 mutex_unlock(&dev->struct_mutex);
3456
fa5c73b1
DV		 3457 for_each_encoder_on_crtc(dev, crtc, encoder)
3458 encoder->enable(encoder);
61b77ddd
DV		 3459
3460 if (HAS_PCH_CPT(dev))
a1520318 3461 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3462
3463 /*
3464 * There seems to be a race in PCH platform hw (at least on some
3465 * outputs) where an enabled pipe still completes any pageflip right
3466 * away (as if the pipe is off) instead of waiting for vblank. As soon
3467 * as the first vblank happend, everything works as expected. Hence just
3468 * wait for one vblank before returning to avoid strange things
3469 * happening.
3470 */
3471 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3472}
3473
42db64ef
PZ		 3474/* IPS only exists on ULT machines and is tied to pipe A. */
3475static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3476{
f5adf94e 3477 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3478}
3479
dda9a66a
VS		 3480static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3481{
3482 struct drm_device *dev = crtc->dev;
3483 struct drm_i915_private *dev_priv = dev->dev_private;
3484 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3485 int pipe = intel_crtc->pipe;
3486 int plane = intel_crtc->plane;
3487
3488 intel_enable_plane(dev_priv, plane, pipe);
3489 intel_enable_planes(crtc);
3490 intel_crtc_update_cursor(crtc, true);
3491
3492 hsw_enable_ips(intel_crtc);
3493
3494 mutex_lock(&dev->struct_mutex);
3495 intel_update_fbc(dev);
3496 mutex_unlock(&dev->struct_mutex);
3497}
3498
3499static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3500{
3501 struct drm_device *dev = crtc->dev;
3502 struct drm_i915_private *dev_priv = dev->dev_private;
3503 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3504 int pipe = intel_crtc->pipe;
3505 int plane = intel_crtc->plane;
3506
3507 intel_crtc_wait_for_pending_flips(crtc);
3508 drm_vblank_off(dev, pipe);
3509
3510 /* FBC must be disabled before disabling the plane on HSW. */
3511 if (dev_priv->fbc.plane == plane)
3512 intel_disable_fbc(dev);
3513
3514 hsw_disable_ips(intel_crtc);
3515
3516 intel_crtc_update_cursor(crtc, false);
3517 intel_disable_planes(crtc);
3518 intel_disable_plane(dev_priv, plane, pipe);
3519}
3520
e4916946
PZ		 3521/*
3522 * This implements the workaround described in the "notes" section of the mode
3523 * set sequence documentation. When going from no pipes or single pipe to
3524 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3525 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3526 */
3527static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3528{
3529 struct drm_device *dev = crtc->base.dev;
3530 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3531
3532 /* We want to get the other_active_crtc only if there's only 1 other
3533 * active crtc. */
3534 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3535 if (!crtc_it->active || crtc_it == crtc)
3536 continue;
3537
3538 if (other_active_crtc)
3539 return;
3540
3541 other_active_crtc = crtc_it;
3542 }
3543 if (!other_active_crtc)
3544 return;
3545
3546 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3547 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3548}
3549
4f771f10
PZ		 3550static void haswell_crtc_enable(struct drm_crtc *crtc)
3551{
3552 struct drm_device *dev = crtc->dev;
3553 struct drm_i915_private *dev_priv = dev->dev_private;
3554 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3555 struct intel_encoder *encoder;
3556 int pipe = intel_crtc->pipe;
4f771f10
PZ		 3557
3558 WARN_ON(!crtc->enabled);
3559
3560 if (intel_crtc->active)
3561 return;
3562
3563 intel_crtc->active = true;
8664281b
PZ		 3564
3565 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3566 if (intel_crtc->config.has_pch_encoder)
3567 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3568
5bfe2ac0 3569 if (intel_crtc->config.has_pch_encoder)
04945641 3570 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3571
3572 for_each_encoder_on_crtc(dev, crtc, encoder)
3573 if (encoder->pre_enable)
3574 encoder->pre_enable(encoder);
3575
1f544388 3576 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3577
b074cec8 3578 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3579
3580 /*
3581 * On ILK+ LUT must be loaded before the pipe is running but with
3582 * clocks enabled
3583 */
3584 intel_crtc_load_lut(crtc);
3585
1f544388 3586 intel_ddi_set_pipe_settings(crtc);
8228c251 3587 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3588
f37fcc2a 3589 intel_update_watermarks(crtc);
5bfe2ac0 3590 intel_enable_pipe(dev_priv, pipe,
23538ef1 3591 intel_crtc->config.has_pch_encoder, false);
42db64ef 3592
5bfe2ac0 3593 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3594 lpt_pch_enable(crtc);
4f771f10 3595
8807e55b 3596 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3597 encoder->enable(encoder);
8807e55b
JN		 3598 intel_opregion_notify_encoder(encoder, true);
3599 }
4f771f10 3600
e4916946
PZ		 3601 /* If we change the relative order between pipe/planes enabling, we need
3602 * to change the workaround. */
3603 haswell_mode_set_planes_workaround(intel_crtc);
dda9a66a
VS		 3604 haswell_crtc_enable_planes(crtc);
3605
4f771f10
PZ		 3606 /*
3607 * There seems to be a race in PCH platform hw (at least on some
3608 * outputs) where an enabled pipe still completes any pageflip right
3609 * away (as if the pipe is off) instead of waiting for vblank. As soon
3610 * as the first vblank happend, everything works as expected. Hence just
3611 * wait for one vblank before returning to avoid strange things
3612 * happening.
3613 */
3614 intel_wait_for_vblank(dev, intel_crtc->pipe);
3615}
3616
3f8dce3a
DV		 3617static void ironlake_pfit_disable(struct intel_crtc *crtc)
3618{
3619 struct drm_device *dev = crtc->base.dev;
3620 struct drm_i915_private *dev_priv = dev->dev_private;
3621 int pipe = crtc->pipe;
3622
3623 /* To avoid upsetting the power well on haswell only disable the pfit if
3624 * it's in use. The hw state code will make sure we get this right. */
fd4daa9c 3625 if (crtc->config.pch_pfit.enabled) {
3f8dce3a
DV		 3626 I915_WRITE(PF_CTL(pipe), 0);
3627 I915_WRITE(PF_WIN_POS(pipe), 0);
3628 I915_WRITE(PF_WIN_SZ(pipe), 0);
3629 }
3630}
3631
6be4a607
JB		 3632static void ironlake_crtc_disable(struct drm_crtc *crtc)
3633{
3634 struct drm_device *dev = crtc->dev;
3635 struct drm_i915_private *dev_priv = dev->dev_private;
3636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3637 struct intel_encoder *encoder;
6be4a607
JB		 3638 int pipe = intel_crtc->pipe;
3639 int plane = intel_crtc->plane;
5eddb70b 3640 u32 reg, temp;
b52eb4dc 3641
ef9c3aee 3642
f7abfe8b
CW		 3643 if (!intel_crtc->active)
3644 return;
3645
ea9d758d
DV		 3646 for_each_encoder_on_crtc(dev, crtc, encoder)
3647 encoder->disable(encoder);
3648
e6c3a2a6 3649 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3650 drm_vblank_off(dev, pipe);
913d8d11 3651
5c3fe8b0 3652 if (dev_priv->fbc.plane == plane)
973d04f9 3653 intel_disable_fbc(dev);
2c07245f 3654
0d5b8c61 3655 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3656 intel_disable_planes(crtc);
0d5b8c61
VS		 3657 intel_disable_plane(dev_priv, plane, pipe);
3658
d925c59a
DV		 3659 if (intel_crtc->config.has_pch_encoder)
3660 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3661
b24e7179 3662 intel_disable_pipe(dev_priv, pipe);
32f9d658 3663
3f8dce3a 3664 ironlake_pfit_disable(intel_crtc);
2c07245f 3665
bf49ec8c
DV		 3666 for_each_encoder_on_crtc(dev, crtc, encoder)
3667 if (encoder->post_disable)
3668 encoder->post_disable(encoder);
2c07245f 3669
d925c59a
DV		 3670 if (intel_crtc->config.has_pch_encoder) {
3671 ironlake_fdi_disable(crtc);
913d8d11 3672
d925c59a
DV		 3673 ironlake_disable_pch_transcoder(dev_priv, pipe);
3674 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3675
d925c59a
DV		 3676 if (HAS_PCH_CPT(dev)) {
3677 /* disable TRANS_DP_CTL */
3678 reg = TRANS_DP_CTL(pipe);
3679 temp = I915_READ(reg);
3680 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3681 TRANS_DP_PORT_SEL_MASK);
3682 temp |= TRANS_DP_PORT_SEL_NONE;
3683 I915_WRITE(reg, temp);
3684
3685 /* disable DPLL_SEL */
3686 temp = I915_READ(PCH_DPLL_SEL);
11887397 3687 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3688 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3689 }
e3421a18 3690
d925c59a 3691 /* disable PCH DPLL */
e72f9fbf 3692 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3693
d925c59a
DV		 3694 ironlake_fdi_pll_disable(intel_crtc);
3695 }
6b383a7f 3696
f7abfe8b 3697 intel_crtc->active = false;
46ba614c 3698 intel_update_watermarks(crtc);
d1ebd816
BW		 3699
3700 mutex_lock(&dev->struct_mutex);
6b383a7f 3701 intel_update_fbc(dev);
d1ebd816 3702 mutex_unlock(&dev->struct_mutex);
6be4a607 3703}
1b3c7a47 3704
4f771f10 3705static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3706{
4f771f10
PZ		 3707 struct drm_device *dev = crtc->dev;
3708 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3709 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3710 struct intel_encoder *encoder;
3711 int pipe = intel_crtc->pipe;
3b117c8f 3712 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3713
4f771f10
PZ		 3714 if (!intel_crtc->active)
3715 return;
3716
dda9a66a
VS		 3717 haswell_crtc_disable_planes(crtc);
3718
8807e55b
JN		 3719 for_each_encoder_on_crtc(dev, crtc, encoder) {
3720 intel_opregion_notify_encoder(encoder, false);
4f771f10 3721 encoder->disable(encoder);
8807e55b 3722 }
4f771f10 3723
8664281b
PZ		 3724 if (intel_crtc->config.has_pch_encoder)
3725 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3726 intel_disable_pipe(dev_priv, pipe);
3727
ad80a810 3728 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3729
3f8dce3a 3730 ironlake_pfit_disable(intel_crtc);
4f771f10 3731
1f544388 3732 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3733
3734 for_each_encoder_on_crtc(dev, crtc, encoder)
3735 if (encoder->post_disable)
3736 encoder->post_disable(encoder);
3737
88adfff1 3738 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3739 lpt_disable_pch_transcoder(dev_priv);
8664281b 3740 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3741 intel_ddi_fdi_disable(crtc);
83616634 3742 }
4f771f10
PZ		 3743
3744 intel_crtc->active = false;
46ba614c 3745 intel_update_watermarks(crtc);
4f771f10
PZ		 3746
3747 mutex_lock(&dev->struct_mutex);
3748 intel_update_fbc(dev);
3749 mutex_unlock(&dev->struct_mutex);
3750}
3751
ee7b9f93
JB		 3752static void ironlake_crtc_off(struct drm_crtc *crtc)
3753{
3754 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3755 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3756}
3757
6441ab5f
PZ		 3758static void haswell_crtc_off(struct drm_crtc *crtc)
3759{
3760 intel_ddi_put_crtc_pll(crtc);
3761}
3762
02e792fb
DV		 3763static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3764{
02e792fb 3765 if (!enable && intel_crtc->overlay) {
23f09ce3 3766 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3767 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3768
23f09ce3 3769 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3770 dev_priv->mm.interruptible = false;
3771 (void) intel_overlay_switch_off(intel_crtc->overlay);
3772 dev_priv->mm.interruptible = true;
23f09ce3 3773 mutex_unlock(&dev->struct_mutex);
02e792fb 3774 }
02e792fb 3775
5dcdbcb0
CW		 3776 /* Let userspace switch the overlay on again. In most cases userspace
3777 * has to recompute where to put it anyway.
3778 */
02e792fb
DV		 3779}
3780
61bc95c1
EE		 3781/**
3782 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3783 * cursor plane briefly if not already running after enabling the display
3784 * plane.
3785 * This workaround avoids occasional blank screens when self refresh is
3786 * enabled.
3787 */
3788static void
3789g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3790{
3791 u32 cntl = I915_READ(CURCNTR(pipe));
3792
3793 if ((cntl & CURSOR_MODE) == 0) {
3794 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3795
3796 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3797 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3798 intel_wait_for_vblank(dev_priv->dev, pipe);
3799 I915_WRITE(CURCNTR(pipe), cntl);
3800 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3801 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3802 }
3803}
3804
2dd24552
JB		 3805static void i9xx_pfit_enable(struct intel_crtc *crtc)
3806{
3807 struct drm_device *dev = crtc->base.dev;
3808 struct drm_i915_private *dev_priv = dev->dev_private;
3809 struct intel_crtc_config *pipe_config = &crtc->config;
3810
328d8e82 3811 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3812 return;
3813
2dd24552 3814 /*
c0b03411
DV		 3815 * The panel fitter should only be adjusted whilst the pipe is disabled,
3816 * according to register description and PRM.
2dd24552 3817 */
c0b03411
DV		 3818 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3819 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3820
b074cec8
JB		 3821 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3822 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3823
3824 /* Border color in case we don't scale up to the full screen. Black by
3825 * default, change to something else for debugging. */
3826 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3827}
3828
89b667f8
JB		 3829static void valleyview_crtc_enable(struct drm_crtc *crtc)
3830{
3831 struct drm_device *dev = crtc->dev;
3832 struct drm_i915_private *dev_priv = dev->dev_private;
3833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3834 struct intel_encoder *encoder;
3835 int pipe = intel_crtc->pipe;
3836 int plane = intel_crtc->plane;
23538ef1 3837 bool is_dsi;
89b667f8
JB		 3838
3839 WARN_ON(!crtc->enabled);
3840
3841 if (intel_crtc->active)
3842 return;
3843
3844 intel_crtc->active = true;
89b667f8 3845
89b667f8
JB		 3846 for_each_encoder_on_crtc(dev, crtc, encoder)
3847 if (encoder->pre_pll_enable)
3848 encoder->pre_pll_enable(encoder);
3849
23538ef1
JN		 3850 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3851
e9fd1c02
JN		 3852 if (!is_dsi)
3853 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3854
3855 for_each_encoder_on_crtc(dev, crtc, encoder)
3856 if (encoder->pre_enable)
3857 encoder->pre_enable(encoder);
3858
2dd24552
JB		 3859 i9xx_pfit_enable(intel_crtc);
3860
63cbb074
VS		 3861 intel_crtc_load_lut(crtc);
3862
f37fcc2a 3863 intel_update_watermarks(crtc);
23538ef1 3864 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
89b667f8 3865 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3866 intel_enable_planes(crtc);
5c38d48c 3867 intel_crtc_update_cursor(crtc, true);
89b667f8 3868
89b667f8 3869 intel_update_fbc(dev);
5004945f
JN		 3870
3871 for_each_encoder_on_crtc(dev, crtc, encoder)
3872 encoder->enable(encoder);
89b667f8
JB		 3873}
3874
0b8765c6 3875static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3876{
3877 struct drm_device *dev = crtc->dev;
79e53945
JB		 3878 struct drm_i915_private *dev_priv = dev->dev_private;
3879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3880 struct intel_encoder *encoder;
79e53945 3881 int pipe = intel_crtc->pipe;
80824003 3882 int plane = intel_crtc->plane;
79e53945 3883
08a48469
DV		 3884 WARN_ON(!crtc->enabled);
3885
f7abfe8b
CW		 3886 if (intel_crtc->active)
3887 return;
3888
3889 intel_crtc->active = true;
6b383a7f 3890
9d6d9f19
MK		 3891 for_each_encoder_on_crtc(dev, crtc, encoder)
3892 if (encoder->pre_enable)
3893 encoder->pre_enable(encoder);
3894
f6736a1a
DV		 3895 i9xx_enable_pll(intel_crtc);
3896
2dd24552
JB		 3897 i9xx_pfit_enable(intel_crtc);
3898
63cbb074
VS		 3899 intel_crtc_load_lut(crtc);
3900
f37fcc2a 3901 intel_update_watermarks(crtc);
23538ef1 3902 intel_enable_pipe(dev_priv, pipe, false, false);
b24e7179 3903 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3904 intel_enable_planes(crtc);
22e407d7 3905 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3906 if (IS_G4X(dev))
3907 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3908 intel_crtc_update_cursor(crtc, true);
79e53945 3909
0b8765c6
JB		 3910 /* Give the overlay scaler a chance to enable if it's on this pipe */
3911 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3912
f440eb13 3913 intel_update_fbc(dev);
ef9c3aee 3914
fa5c73b1
DV		 3915 for_each_encoder_on_crtc(dev, crtc, encoder)
3916 encoder->enable(encoder);
0b8765c6 3917}
79e53945 3918
87476d63
DV		 3919static void i9xx_pfit_disable(struct intel_crtc *crtc)
3920{
3921 struct drm_device *dev = crtc->base.dev;
3922 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3923
328d8e82
DV		 3924 if (!crtc->config.gmch_pfit.control)
3925 return;
87476d63 3926
328d8e82 3927 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3928
328d8e82
DV		 3929 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3930 I915_READ(PFIT_CONTROL));
3931 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3932}
3933
0b8765c6
JB		 3934static void i9xx_crtc_disable(struct drm_crtc *crtc)
3935{
3936 struct drm_device *dev = crtc->dev;
3937 struct drm_i915_private *dev_priv = dev->dev_private;
3938 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3939 struct intel_encoder *encoder;
0b8765c6
JB		 3940 int pipe = intel_crtc->pipe;
3941 int plane = intel_crtc->plane;
ef9c3aee 3942
f7abfe8b
CW		 3943 if (!intel_crtc->active)
3944 return;
3945
ea9d758d
DV		 3946 for_each_encoder_on_crtc(dev, crtc, encoder)
3947 encoder->disable(encoder);
3948
0b8765c6 3949 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3950 intel_crtc_wait_for_pending_flips(crtc);
3951 drm_vblank_off(dev, pipe);
0b8765c6 3952
5c3fe8b0 3953 if (dev_priv->fbc.plane == plane)
973d04f9 3954 intel_disable_fbc(dev);
79e53945 3955
0d5b8c61
VS		 3956 intel_crtc_dpms_overlay(intel_crtc, false);
3957 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3958 intel_disable_planes(crtc);
b24e7179 3959 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3960
b24e7179 3961 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3962
87476d63 3963 i9xx_pfit_disable(intel_crtc);
24a1f16d 3964
89b667f8
JB		 3965 for_each_encoder_on_crtc(dev, crtc, encoder)
3966 if (encoder->post_disable)
3967 encoder->post_disable(encoder);
3968
f6071166
JB		 3969 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3970 vlv_disable_pll(dev_priv, pipe);
3971 else if (!IS_VALLEYVIEW(dev))
e9fd1c02 3972 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3973
f7abfe8b 3974 intel_crtc->active = false;
46ba614c 3975 intel_update_watermarks(crtc);
f37fcc2a 3976
6b383a7f 3977 intel_update_fbc(dev);
0b8765c6
JB		 3978}
3979
ee7b9f93
JB		 3980static void i9xx_crtc_off(struct drm_crtc *crtc)
3981{
3982}
3983
976f8a20
DV		 3984static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3985 bool enabled)
2c07245f
ZW		 3986{
3987 struct drm_device *dev = crtc->dev;
3988 struct drm_i915_master_private *master_priv;
3989 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3990 int pipe = intel_crtc->pipe;
79e53945
JB		 3991
3992 if (!dev->primary->master)
3993 return;
3994
3995 master_priv = dev->primary->master->driver_priv;
3996 if (!master_priv->sarea_priv)
3997 return;
3998
79e53945
JB		 3999 switch (pipe) {
4000 case 0:
4001 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4002 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4003 break;
4004 case 1:
4005 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4006 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4007 break;
4008 default:
9db4a9c7 4009 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 4010 break;
4011 }
79e53945
JB		 4012}
4013
976f8a20
DV		 4014/**
4015 * Sets the power management mode of the pipe and plane.
4016 */
4017void intel_crtc_update_dpms(struct drm_crtc *crtc)
4018{
4019 struct drm_device *dev = crtc->dev;
4020 struct drm_i915_private *dev_priv = dev->dev_private;
4021 struct intel_encoder *intel_encoder;
4022 bool enable = false;
4023
4024 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4025 enable |= intel_encoder->connectors_active;
4026
4027 if (enable)
4028 dev_priv->display.crtc_enable(crtc);
4029 else
4030 dev_priv->display.crtc_disable(crtc);
4031
4032 intel_crtc_update_sarea(crtc, enable);
4033}
4034
cdd59983
CW		 4035static void intel_crtc_disable(struct drm_crtc *crtc)
4036{
cdd59983 4037 struct drm_device *dev = crtc->dev;
976f8a20 4038 struct drm_connector *connector;
ee7b9f93 4039 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 4040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 4041
976f8a20
DV		 4042 /* crtc should still be enabled when we disable it. */
4043 WARN_ON(!crtc->enabled);
4044
4045 dev_priv->display.crtc_disable(crtc);
c77bf565 4046 intel_crtc->eld_vld = false;
976f8a20 4047 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 4048 dev_priv->display.off(crtc);
4049
931872fc 4050 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
93ce0ba6 4051 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
931872fc 4052 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 4053
4054 if (crtc->fb) {
4055 mutex_lock(&dev->struct_mutex);
1690e1eb 4056 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 4057 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 4058 crtc->fb = NULL;
4059 }
4060
4061 /* Update computed state. */
4062 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4063 if (!connector->encoder || !connector->encoder->crtc)
4064 continue;
4065
4066 if (connector->encoder->crtc != crtc)
4067 continue;
4068
4069 connector->dpms = DRM_MODE_DPMS_OFF;
4070 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 4071 }
4072}
4073
ea5b213a 4074void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 4075{
4ef69c7a 4076 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 4077
ea5b213a
CW		 4078 drm_encoder_cleanup(encoder);
4079 kfree(intel_encoder);
7e7d76c3
JB		 4080}
4081
9237329d 4082/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 4083 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4084 * state of the entire output pipe. */
9237329d 4085static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 4086{
5ab432ef
DV		 4087 if (mode == DRM_MODE_DPMS_ON) {
4088 encoder->connectors_active = true;
4089
b2cabb0e 4090 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 4091 } else {
4092 encoder->connectors_active = false;
4093
b2cabb0e 4094 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 4095 }
79e53945
JB		 4096}
4097
0a91ca29
DV		 4098/* Cross check the actual hw state with our own modeset state tracking (and it's
4099 * internal consistency). */
b980514c 4100static void intel_connector_check_state(struct intel_connector *connector)
79e53945 4101{
0a91ca29
DV		 4102 if (connector->get_hw_state(connector)) {
4103 struct intel_encoder *encoder = connector->encoder;
4104 struct drm_crtc *crtc;
4105 bool encoder_enabled;
4106 enum pipe pipe;
4107
4108 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4109 connector->base.base.id,
4110 drm_get_connector_name(&connector->base));
4111
4112 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4113 "wrong connector dpms state\n");
4114 WARN(connector->base.encoder != &encoder->base,
4115 "active connector not linked to encoder\n");
4116 WARN(!encoder->connectors_active,
4117 "encoder->connectors_active not set\n");
4118
4119 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4120 WARN(!encoder_enabled, "encoder not enabled\n");
4121 if (WARN_ON(!encoder->base.crtc))
4122 return;
4123
4124 crtc = encoder->base.crtc;
4125
4126 WARN(!crtc->enabled, "crtc not enabled\n");
4127 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4128 WARN(pipe != to_intel_crtc(crtc)->pipe,
4129 "encoder active on the wrong pipe\n");
4130 }
79e53945
JB		 4131}
4132
5ab432ef
DV		 4133/* Even simpler default implementation, if there's really no special case to
4134 * consider. */
4135void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 4136{
5ab432ef 4137 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 4138
5ab432ef
DV		 4139 /* All the simple cases only support two dpms states. */
4140 if (mode != DRM_MODE_DPMS_ON)
4141 mode = DRM_MODE_DPMS_OFF;
d4270e57 4142
5ab432ef
DV		 4143 if (mode == connector->dpms)
4144 return;
4145
4146 connector->dpms = mode;
4147
4148 /* Only need to change hw state when actually enabled */
4149 if (encoder->base.crtc)
4150 intel_encoder_dpms(encoder, mode);
4151 else
8af6cf88 4152 WARN_ON(encoder->connectors_active != false);
0a91ca29 4153
b980514c 4154 intel_modeset_check_state(connector->dev);
79e53945
JB		 4155}
4156
f0947c37
DV		 4157/* Simple connector->get_hw_state implementation for encoders that support only
4158 * one connector and no cloning and hence the encoder state determines the state
4159 * of the connector. */
4160bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4161{
24929352 4162 enum pipe pipe = 0;
f0947c37 4163 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4164
f0947c37 4165 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4166}
4167
1857e1da
DV		 4168static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4169 struct intel_crtc_config *pipe_config)
4170{
4171 struct drm_i915_private *dev_priv = dev->dev_private;
4172 struct intel_crtc *pipe_B_crtc =
4173 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4174
4175 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4176 pipe_name(pipe), pipe_config->fdi_lanes);
4177 if (pipe_config->fdi_lanes > 4) {
4178 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4179 pipe_name(pipe), pipe_config->fdi_lanes);
4180 return false;
4181 }
4182
4183 if (IS_HASWELL(dev)) {
4184 if (pipe_config->fdi_lanes > 2) {
4185 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4186 pipe_config->fdi_lanes);
4187 return false;
4188 } else {
4189 return true;
4190 }
4191 }
4192
4193 if (INTEL_INFO(dev)->num_pipes == 2)
4194 return true;
4195
4196 /* Ivybridge 3 pipe is really complicated */
4197 switch (pipe) {
4198 case PIPE_A:
4199 return true;
4200 case PIPE_B:
4201 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4202 pipe_config->fdi_lanes > 2) {
4203 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4204 pipe_name(pipe), pipe_config->fdi_lanes);
4205 return false;
4206 }
4207 return true;
4208 case PIPE_C:
1e833f40 4209 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4210 pipe_B_crtc->config.fdi_lanes <= 2) {
4211 if (pipe_config->fdi_lanes > 2) {
4212 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4213 pipe_name(pipe), pipe_config->fdi_lanes);
4214 return false;
4215 }
4216 } else {
4217 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4218 return false;
4219 }
4220 return true;
4221 default:
4222 BUG();
4223 }
4224}
4225
e29c22c0
DV		 4226#define RETRY 1
4227static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4228 struct intel_crtc_config *pipe_config)
877d48d5 4229{
1857e1da 4230 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4231 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4232 int lane, link_bw, fdi_dotclock;
e29c22c0 4233 bool setup_ok, needs_recompute = false;
877d48d5 4234
e29c22c0 4235retry:
877d48d5
DV		 4236 /* FDI is a binary signal running at ~2.7GHz, encoding
4237 * each output octet as 10 bits. The actual frequency
4238 * is stored as a divider into a 100MHz clock, and the
4239 * mode pixel clock is stored in units of 1KHz.
4240 * Hence the bw of each lane in terms of the mode signal
4241 * is:
4242 */
4243 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4244
241bfc38 4245 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 4246
2bd89a07 4247 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4248 pipe_config->pipe_bpp);
4249
4250 pipe_config->fdi_lanes = lane;
4251
2bd89a07 4252 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4253 link_bw, &pipe_config->fdi_m_n);
1857e1da 4254
e29c22c0
DV		 4255 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4256 intel_crtc->pipe, pipe_config);
4257 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4258 pipe_config->pipe_bpp -= 2*3;
4259 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4260 pipe_config->pipe_bpp);
4261 needs_recompute = true;
4262 pipe_config->bw_constrained = true;
4263
4264 goto retry;
4265 }
4266
4267 if (needs_recompute)
4268 return RETRY;
4269
4270 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4271}
4272
42db64ef
PZ		 4273static void hsw_compute_ips_config(struct intel_crtc *crtc,
4274 struct intel_crtc_config *pipe_config)
4275{
3c4ca58c
PZ		 4276 pipe_config->ips_enabled = i915_enable_ips &&
4277 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4278 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4279}
4280
a43f6e0f 4281static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4282 struct intel_crtc_config *pipe_config)
79e53945 4283{
a43f6e0f 4284 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4285 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4286
ad3a4479 4287 /* FIXME should check pixel clock limits on all platforms */
cf532bb2
VS		 4288 if (INTEL_INFO(dev)->gen < 4) {
4289 struct drm_i915_private *dev_priv = dev->dev_private;
4290 int clock_limit =
4291 dev_priv->display.get_display_clock_speed(dev);
4292
4293 /*
4294 * Enable pixel doubling when the dot clock
4295 * is > 90% of the (display) core speed.
4296 *
b397c96b
VS		 4297 * GDG double wide on either pipe,
4298 * otherwise pipe A only.
cf532bb2 4299 */
b397c96b 4300 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 4301 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 4302 clock_limit *= 2;
cf532bb2 4303 pipe_config->double_wide = true;
ad3a4479
VS		 4304 }
4305
241bfc38 4306 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 4307 return -EINVAL;
2c07245f 4308 }
89749350 4309
1d1d0e27
VS		 4310 /*
4311 * Pipe horizontal size must be even in:
4312 * - DVO ganged mode
4313 * - LVDS dual channel mode
4314 * - Double wide pipe
4315 */
4316 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4317 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4318 pipe_config->pipe_src_w &= ~1;
4319
8693a824
DL		 4320 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4321 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4322 */
4323 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4324 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4325 return -EINVAL;
44f46b42 4326
bd080ee5 4327 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4328 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4329 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4330 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4331 * for lvds. */
4332 pipe_config->pipe_bpp = 8*3;
4333 }
4334
f5adf94e 4335 if (HAS_IPS(dev))
a43f6e0f
DV		 4336 hsw_compute_ips_config(crtc, pipe_config);
4337
4338 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4339 * clock survives for now. */
4340 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4341 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4342
877d48d5 4343 if (pipe_config->has_pch_encoder)
a43f6e0f 4344 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4345
e29c22c0 4346 return 0;
79e53945
JB		 4347}
4348
25eb05fc
JB		 4349static int valleyview_get_display_clock_speed(struct drm_device *dev)
4350{
4351 return 400000; /* FIXME */
4352}
4353
e70236a8
JB		 4354static int i945_get_display_clock_speed(struct drm_device *dev)
4355{
4356 return 400000;
4357}
79e53945 4358
e70236a8 4359static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4360{
e70236a8
JB		 4361 return 333000;
4362}
79e53945 4363
e70236a8
JB		 4364static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4365{
4366 return 200000;
4367}
79e53945 4368
257a7ffc
DV		 4369static int pnv_get_display_clock_speed(struct drm_device *dev)
4370{
4371 u16 gcfgc = 0;
4372
4373 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4374
4375 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4376 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4377 return 267000;
4378 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4379 return 333000;
4380 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4381 return 444000;
4382 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4383 return 200000;
4384 default:
4385 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4386 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4387 return 133000;
4388 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4389 return 167000;
4390 }
4391}
4392
e70236a8
JB		 4393static int i915gm_get_display_clock_speed(struct drm_device *dev)
4394{
4395 u16 gcfgc = 0;
79e53945 4396
e70236a8
JB		 4397 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4398
4399 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4400 return 133000;
4401 else {
4402 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4403 case GC_DISPLAY_CLOCK_333_MHZ:
4404 return 333000;
4405 default:
4406 case GC_DISPLAY_CLOCK_190_200_MHZ:
4407 return 190000;
79e53945 4408 }
e70236a8
JB		 4409 }
4410}
4411
4412static int i865_get_display_clock_speed(struct drm_device *dev)
4413{
4414 return 266000;
4415}
4416
4417static int i855_get_display_clock_speed(struct drm_device *dev)
4418{
4419 u16 hpllcc = 0;
4420 /* Assume that the hardware is in the high speed state. This
4421 * should be the default.
4422 */
4423 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4424 case GC_CLOCK_133_200:
4425 case GC_CLOCK_100_200:
4426 return 200000;
4427 case GC_CLOCK_166_250:
4428 return 250000;
4429 case GC_CLOCK_100_133:
79e53945 4430 return 133000;
e70236a8 4431 }
79e53945 4432
e70236a8
JB		 4433 /* Shouldn't happen */
4434 return 0;
4435}
79e53945 4436
e70236a8
JB		 4437static int i830_get_display_clock_speed(struct drm_device *dev)
4438{
4439 return 133000;
79e53945
JB		 4440}
4441
2c07245f 4442static void
a65851af 4443intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4444{
a65851af
VS		 4445 while (*num > DATA_LINK_M_N_MASK ||
4446 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4447 *num >>= 1;
4448 *den >>= 1;
4449 }
4450}
4451
a65851af
VS		 4452static void compute_m_n(unsigned int m, unsigned int n,
4453 uint32_t *ret_m, uint32_t *ret_n)
4454{
4455 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4456 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4457 intel_reduce_m_n_ratio(ret_m, ret_n);
4458}
4459
e69d0bc1
DV		 4460void
4461intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4462 int pixel_clock, int link_clock,
4463 struct intel_link_m_n *m_n)
2c07245f 4464{
e69d0bc1 4465 m_n->tu = 64;
a65851af
VS		 4466
4467 compute_m_n(bits_per_pixel * pixel_clock,
4468 link_clock * nlanes * 8,
4469 &m_n->gmch_m, &m_n->gmch_n);
4470
4471 compute_m_n(pixel_clock, link_clock,
4472 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4473}
4474
a7615030
CW		 4475static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4476{
72bbe58c
KP		 4477 if (i915_panel_use_ssc >= 0)
4478 return i915_panel_use_ssc != 0;
41aa3448 4479 return dev_priv->vbt.lvds_use_ssc
435793df 4480 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4481}
4482
c65d77d8
JB		 4483static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4484{
4485 struct drm_device *dev = crtc->dev;
4486 struct drm_i915_private *dev_priv = dev->dev_private;
4487 int refclk;
4488
a0c4da24 4489 if (IS_VALLEYVIEW(dev)) {
9a0ea498 4490 refclk = 100000;
a0c4da24 4491 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4492 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4493 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4494 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4495 refclk / 1000);
4496 } else if (!IS_GEN2(dev)) {
4497 refclk = 96000;
4498 } else {
4499 refclk = 48000;
4500 }
4501
4502 return refclk;
4503}
4504
7429e9d4 4505static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4506{
7df00d7a 4507 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4508}
f47709a9 4509
7429e9d4
DV		 4510static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4511{
4512 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4513}
4514
f47709a9 4515static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4516 intel_clock_t *reduced_clock)
4517{
f47709a9 4518 struct drm_device *dev = crtc->base.dev;
a7516a05 4519 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4520 int pipe = crtc->pipe;
a7516a05
JB		 4521 u32 fp, fp2 = 0;
4522
4523 if (IS_PINEVIEW(dev)) {
7429e9d4 4524 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4525 if (reduced_clock)
7429e9d4 4526 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4527 } else {
7429e9d4 4528 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4529 if (reduced_clock)
7429e9d4 4530 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4531 }
4532
4533 I915_WRITE(FP0(pipe), fp);
8bcc2795 4534 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4535
f47709a9
DV		 4536 crtc->lowfreq_avail = false;
4537 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4538 reduced_clock && i915_powersave) {
4539 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4540 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4541 crtc->lowfreq_avail = true;
a7516a05
JB		 4542 } else {
4543 I915_WRITE(FP1(pipe), fp);
8bcc2795 4544 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4545 }
4546}
4547
5e69f97f
CML		 4548static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4549 pipe)
89b667f8
JB		 4550{
4551 u32 reg_val;
4552
4553 /*
4554 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4555 * and set it to a reasonable value instead.
4556 */
5e69f97f 4557 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8
JB		 4558 reg_val &= 0xffffff00;
4559 reg_val |= 0x00000030;
5e69f97f 4560 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4561
5e69f97f 4562 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4563 reg_val &= 0x8cffffff;
4564 reg_val = 0x8c000000;
5e69f97f 4565 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8 4566
5e69f97f 4567 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8 4568 reg_val &= 0xffffff00;
5e69f97f 4569 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4570
5e69f97f 4571 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4572 reg_val &= 0x00ffffff;
4573 reg_val |= 0xb0000000;
5e69f97f 4574 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4575}
4576
b551842d
DV		 4577static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4578 struct intel_link_m_n *m_n)
4579{
4580 struct drm_device *dev = crtc->base.dev;
4581 struct drm_i915_private *dev_priv = dev->dev_private;
4582 int pipe = crtc->pipe;
4583
e3b95f1e
DV		 4584 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4585 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4586 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4587 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4588}
4589
4590static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4591 struct intel_link_m_n *m_n)
4592{
4593 struct drm_device *dev = crtc->base.dev;
4594 struct drm_i915_private *dev_priv = dev->dev_private;
4595 int pipe = crtc->pipe;
4596 enum transcoder transcoder = crtc->config.cpu_transcoder;
4597
4598 if (INTEL_INFO(dev)->gen >= 5) {
4599 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4600 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4601 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4602 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4603 } else {
e3b95f1e
DV		 4604 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4605 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4606 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4607 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4608 }
4609}
4610
03afc4a2
DV		 4611static void intel_dp_set_m_n(struct intel_crtc *crtc)
4612{
4613 if (crtc->config.has_pch_encoder)
4614 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4615 else
4616 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4617}
4618
f47709a9 4619static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4620{
f47709a9 4621 struct drm_device *dev = crtc->base.dev;
a0c4da24 4622 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4623 int pipe = crtc->pipe;
89b667f8 4624 u32 dpll, mdiv;
a0c4da24 4625 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4626 u32 coreclk, reg_val, dpll_md;
a0c4da24 4627
09153000
DV		 4628 mutex_lock(&dev_priv->dpio_lock);
4629
f47709a9
DV		 4630 bestn = crtc->config.dpll.n;
4631 bestm1 = crtc->config.dpll.m1;
4632 bestm2 = crtc->config.dpll.m2;
4633 bestp1 = crtc->config.dpll.p1;
4634 bestp2 = crtc->config.dpll.p2;
a0c4da24 4635
89b667f8
JB		 4636 /* See eDP HDMI DPIO driver vbios notes doc */
4637
4638 /* PLL B needs special handling */
4639 if (pipe)
5e69f97f 4640 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 4641
4642 /* Set up Tx target for periodic Rcomp update */
5e69f97f 4643 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4644
4645 /* Disable target IRef on PLL */
5e69f97f 4646 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
89b667f8 4647 reg_val &= 0x00ffffff;
5e69f97f 4648 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4649
4650 /* Disable fast lock */
5e69f97f 4651 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4652
4653 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4654 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4655 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4656 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4657 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4658
4659 /*
4660 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4661 * but we don't support that).
4662 * Note: don't use the DAC post divider as it seems unstable.
4663 */
4664 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5e69f97f 4665 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4666
a0c4da24 4667 mdiv |= DPIO_ENABLE_CALIBRATION;
5e69f97f 4668 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4669
89b667f8 4670 /* Set HBR and RBR LPF coefficients */
ff9a6750 4671 if (crtc->config.port_clock == 162000 ||
99750bd4 4672 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4673 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5e69f97f 4674 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
885b0120 4675 0x009f0003);
89b667f8 4676 else
5e69f97f 4677 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4678 0x00d0000f);
4679
4680 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4681 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4682 /* Use SSC source */
4683 if (!pipe)
5e69f97f 4684 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4685 0x0df40000);
4686 else
5e69f97f 4687 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4688 0x0df70000);
4689 } else { /* HDMI or VGA */
4690 /* Use bend source */
4691 if (!pipe)
5e69f97f 4692 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4693 0x0df70000);
4694 else
5e69f97f 4695 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4696 0x0df40000);
4697 }
a0c4da24 4698
5e69f97f 4699 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4700 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4701 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4702 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4703 coreclk |= 0x01000000;
5e69f97f 4704 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4705
5e69f97f 4706 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4707
89b667f8
JB		 4708 /* Enable DPIO clock input */
4709 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4710 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
f6071166
JB		 4711 /* We should never disable this, set it here for state tracking */
4712 if (pipe == PIPE_B)
89b667f8 4713 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24 4714 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4715 crtc->config.dpll_hw_state.dpll = dpll;
4716
ef1b460d
DV		 4717 dpll_md = (crtc->config.pixel_multiplier - 1)
4718 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4719 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4720
89b667f8
JB		 4721 if (crtc->config.has_dp_encoder)
4722 intel_dp_set_m_n(crtc);
09153000
DV		 4723
4724 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4725}
4726
f47709a9
DV		 4727static void i9xx_update_pll(struct intel_crtc *crtc,
4728 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4729 int num_connectors)
4730{
f47709a9 4731 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4732 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4733 u32 dpll;
4734 bool is_sdvo;
f47709a9 4735 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4736
f47709a9 4737 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4738
f47709a9
DV		 4739 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4740 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4741
4742 dpll = DPLL_VGA_MODE_DIS;
4743
f47709a9 4744 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4745 dpll |= DPLLB_MODE_LVDS;
4746 else
4747 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4748
ef1b460d 4749 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4750 dpll |= (crtc->config.pixel_multiplier - 1)
4751 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4752 }
198a037f
DV		 4753
4754 if (is_sdvo)
4a33e48d 4755 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4756
f47709a9 4757 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4758 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4759
4760 /* compute bitmask from p1 value */
4761 if (IS_PINEVIEW(dev))
4762 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4763 else {
4764 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4765 if (IS_G4X(dev) && reduced_clock)
4766 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4767 }
4768 switch (clock->p2) {
4769 case 5:
4770 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4771 break;
4772 case 7:
4773 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4774 break;
4775 case 10:
4776 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4777 break;
4778 case 14:
4779 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4780 break;
4781 }
4782 if (INTEL_INFO(dev)->gen >= 4)
4783 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4784
09ede541 4785 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4786 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4787 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4788 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4789 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4790 else
4791 dpll |= PLL_REF_INPUT_DREFCLK;
4792
4793 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4794 crtc->config.dpll_hw_state.dpll = dpll;
4795
eb1cbe48 4796 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4797 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4798 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4799 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4800 }
66e3d5c0
DV		 4801
4802 if (crtc->config.has_dp_encoder)
4803 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4804}
4805
f47709a9 4806static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4807 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4808 int num_connectors)
4809{
f47709a9 4810 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4811 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4812 u32 dpll;
f47709a9 4813 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4814
f47709a9 4815 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4816
eb1cbe48
DV		 4817 dpll = DPLL_VGA_MODE_DIS;
4818
f47709a9 4819 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4820 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4821 } else {
4822 if (clock->p1 == 2)
4823 dpll |= PLL_P1_DIVIDE_BY_TWO;
4824 else
4825 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4826 if (clock->p2 == 4)
4827 dpll |= PLL_P2_DIVIDE_BY_4;
4828 }
4829
4a33e48d
DV		 4830 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4831 dpll |= DPLL_DVO_2X_MODE;
4832
f47709a9 4833 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4834 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4835 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4836 else
4837 dpll |= PLL_REF_INPUT_DREFCLK;
4838
4839 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4840 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4841}
4842
8a654f3b 4843static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4844{
4845 struct drm_device *dev = intel_crtc->base.dev;
4846 struct drm_i915_private *dev_priv = dev->dev_private;
4847 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4848 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4849 struct drm_display_mode *adjusted_mode =
4850 &intel_crtc->config.adjusted_mode;
4d8a62ea
DV		 4851 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4852
4853 /* We need to be careful not to changed the adjusted mode, for otherwise
4854 * the hw state checker will get angry at the mismatch. */
4855 crtc_vtotal = adjusted_mode->crtc_vtotal;
4856 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4857
4858 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4859 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4860 crtc_vtotal -= 1;
4861 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4862 vsyncshift = adjusted_mode->crtc_hsync_start
4863 - adjusted_mode->crtc_htotal / 2;
4864 } else {
4865 vsyncshift = 0;
4866 }
4867
4868 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4869 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4870
fe2b8f9d 4871 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4872 (adjusted_mode->crtc_hdisplay - 1) |
4873 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4874 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4875 (adjusted_mode->crtc_hblank_start - 1) |
4876 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4877 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4878 (adjusted_mode->crtc_hsync_start - 1) |
4879 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4880
fe2b8f9d 4881 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4882 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4883 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4884 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4885 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4886 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4887 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4888 (adjusted_mode->crtc_vsync_start - 1) |
4889 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4890
b5e508d4
PZ		 4891 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4892 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4893 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4894 * bits. */
4895 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4896 (pipe == PIPE_B || pipe == PIPE_C))
4897 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4898
b0e77b9c
PZ		 4899 /* pipesrc controls the size that is scaled from, which should
4900 * always be the user's requested size.
4901 */
4902 I915_WRITE(PIPESRC(pipe),
37327abd
VS		 4903 ((intel_crtc->config.pipe_src_w - 1) << 16) |
4904 (intel_crtc->config.pipe_src_h - 1));
b0e77b9c
PZ		 4905}
4906
1bd1bd80
DV		 4907static void intel_get_pipe_timings(struct intel_crtc *crtc,
4908 struct intel_crtc_config *pipe_config)
4909{
4910 struct drm_device *dev = crtc->base.dev;
4911 struct drm_i915_private *dev_priv = dev->dev_private;
4912 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4913 uint32_t tmp;
4914
4915 tmp = I915_READ(HTOTAL(cpu_transcoder));
4916 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4917 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4918 tmp = I915_READ(HBLANK(cpu_transcoder));
4919 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4920 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4921 tmp = I915_READ(HSYNC(cpu_transcoder));
4922 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4923 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4924
4925 tmp = I915_READ(VTOTAL(cpu_transcoder));
4926 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4927 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4928 tmp = I915_READ(VBLANK(cpu_transcoder));
4929 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4930 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4931 tmp = I915_READ(VSYNC(cpu_transcoder));
4932 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4933 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4934
4935 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4936 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4937 pipe_config->adjusted_mode.crtc_vtotal += 1;
4938 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4939 }
4940
4941 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 4942 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4943 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4944
4945 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4946 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 4947}
4948
babea61d
JB		 4949static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4950 struct intel_crtc_config *pipe_config)
4951{
4952 struct drm_crtc *crtc = &intel_crtc->base;
4953
4954 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4955 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4956 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4957 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4958
4959 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4960 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4961 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4962 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4963
4964 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4965
241bfc38 4966 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
babea61d
JB		 4967 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4968}
4969
84b046f3
DV		 4970static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4971{
4972 struct drm_device *dev = intel_crtc->base.dev;
4973 struct drm_i915_private *dev_priv = dev->dev_private;
4974 uint32_t pipeconf;
4975
9f11a9e4 4976 pipeconf = 0;
84b046f3 4977
67c72a12
DV		 4978 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
4979 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
4980 pipeconf |= PIPECONF_ENABLE;
4981
cf532bb2
VS		 4982 if (intel_crtc->config.double_wide)
4983 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 4984
ff9ce46e
DV		 4985 /* only g4x and later have fancy bpc/dither controls */
4986 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4987 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4988 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4989 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4990 PIPECONF_DITHER_TYPE_SP;
84b046f3 4991
ff9ce46e
DV		 4992 switch (intel_crtc->config.pipe_bpp) {
4993 case 18:
4994 pipeconf |= PIPECONF_6BPC;
4995 break;
4996 case 24:
4997 pipeconf |= PIPECONF_8BPC;
4998 break;
4999 case 30:
5000 pipeconf |= PIPECONF_10BPC;
5001 break;
5002 default:
5003 /* Case prevented by intel_choose_pipe_bpp_dither. */
5004 BUG();
84b046f3
DV		 5005 }
5006 }
5007
5008 if (HAS_PIPE_CXSR(dev)) {
5009 if (intel_crtc->lowfreq_avail) {
5010 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5011 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5012 } else {
5013 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 5014 }
5015 }
5016
84b046f3
DV		 5017 if (!IS_GEN2(dev) &&
5018 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5019 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5020 else
5021 pipeconf |= PIPECONF_PROGRESSIVE;
5022
9f11a9e4
DV		 5023 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5024 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 5025
84b046f3
DV		 5026 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5027 POSTING_READ(PIPECONF(intel_crtc->pipe));
5028}
5029
f564048e 5030static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5031 int x, int y,
94352cf9 5032 struct drm_framebuffer *fb)
79e53945
JB		 5033{
5034 struct drm_device *dev = crtc->dev;
5035 struct drm_i915_private *dev_priv = dev->dev_private;
5036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5037 int pipe = intel_crtc->pipe;
80824003 5038 int plane = intel_crtc->plane;
c751ce4f 5039 int refclk, num_connectors = 0;
652c393a 5040 intel_clock_t clock, reduced_clock;
84b046f3 5041 u32 dspcntr;
a16af721 5042 bool ok, has_reduced_clock = false;
e9fd1c02 5043 bool is_lvds = false, is_dsi = false;
5eddb70b 5044 struct intel_encoder *encoder;
d4906093 5045 const intel_limit_t *limit;
5c3b82e2 5046 int ret;
79e53945 5047
6c2b7c12 5048 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 5049 switch (encoder->type) {
79e53945
JB		 5050 case INTEL_OUTPUT_LVDS:
5051 is_lvds = true;
5052 break;
e9fd1c02
JN		 5053 case INTEL_OUTPUT_DSI:
5054 is_dsi = true;
5055 break;
79e53945 5056 }
43565a06 5057
c751ce4f 5058 num_connectors++;
79e53945
JB		 5059 }
5060
f2335330
JN		 5061 if (is_dsi)
5062 goto skip_dpll;
5063
5064 if (!intel_crtc->config.clock_set) {
5065 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 5066
e9fd1c02
JN		 5067 /*
5068 * Returns a set of divisors for the desired target clock with
5069 * the given refclk, or FALSE. The returned values represent
5070 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5071 * 2) / p1 / p2.
5072 */
5073 limit = intel_limit(crtc, refclk);
5074 ok = dev_priv->display.find_dpll(limit, crtc,
5075 intel_crtc->config.port_clock,
5076 refclk, NULL, &clock);
f2335330 5077 if (!ok) {
e9fd1c02
JN		 5078 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5079 return -EINVAL;
5080 }
79e53945 5081
f2335330
JN		 5082 if (is_lvds && dev_priv->lvds_downclock_avail) {
5083 /*
5084 * Ensure we match the reduced clock's P to the target
5085 * clock. If the clocks don't match, we can't switch
5086 * the display clock by using the FP0/FP1. In such case
5087 * we will disable the LVDS downclock feature.
5088 */
5089 has_reduced_clock =
5090 dev_priv->display.find_dpll(limit, crtc,
5091 dev_priv->lvds_downclock,
5092 refclk, &clock,
5093 &reduced_clock);
5094 }
5095 /* Compat-code for transition, will disappear. */
f47709a9
DV		 5096 intel_crtc->config.dpll.n = clock.n;
5097 intel_crtc->config.dpll.m1 = clock.m1;
5098 intel_crtc->config.dpll.m2 = clock.m2;
5099 intel_crtc->config.dpll.p1 = clock.p1;
5100 intel_crtc->config.dpll.p2 = clock.p2;
5101 }
7026d4ac 5102
e9fd1c02 5103 if (IS_GEN2(dev)) {
8a654f3b 5104 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 5105 has_reduced_clock ? &reduced_clock : NULL,
5106 num_connectors);
e9fd1c02 5107 } else if (IS_VALLEYVIEW(dev)) {
f2335330 5108 vlv_update_pll(intel_crtc);
e9fd1c02 5109 } else {
f47709a9 5110 i9xx_update_pll(intel_crtc,
eb1cbe48 5111 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 5112 num_connectors);
e9fd1c02 5113 }
79e53945 5114
f2335330 5115skip_dpll:
79e53945
JB		 5116 /* Set up the display plane register */
5117 dspcntr = DISPPLANE_GAMMA_ENABLE;
5118
da6ecc5d
JB		 5119 if (!IS_VALLEYVIEW(dev)) {
5120 if (pipe == 0)
5121 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5122 else
5123 dspcntr |= DISPPLANE_SEL_PIPE_B;
5124 }
79e53945 5125
8a654f3b 5126 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 5127
5128 /* pipesrc and dspsize control the size that is scaled from,
5129 * which should always be the user's requested size.
79e53945 5130 */
929c77fb 5131 I915_WRITE(DSPSIZE(plane),
37327abd
VS		 5132 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5133 (intel_crtc->config.pipe_src_w - 1));
929c77fb 5134 I915_WRITE(DSPPOS(plane), 0);
2c07245f 5135
84b046f3
DV		 5136 i9xx_set_pipeconf(intel_crtc);
5137
f564048e
EA		 5138 I915_WRITE(DSPCNTR(plane), dspcntr);
5139 POSTING_READ(DSPCNTR(plane));
5140
94352cf9 5141 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e 5142
f564048e
EA		 5143 return ret;
5144}
5145
2fa2fe9a
DV		 5146static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5147 struct intel_crtc_config *pipe_config)
5148{
5149 struct drm_device *dev = crtc->base.dev;
5150 struct drm_i915_private *dev_priv = dev->dev_private;
5151 uint32_t tmp;
5152
5153 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 5154 if (!(tmp & PFIT_ENABLE))
5155 return;
2fa2fe9a 5156
06922821 5157 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 5158 if (INTEL_INFO(dev)->gen < 4) {
5159 if (crtc->pipe != PIPE_B)
5160 return;
2fa2fe9a
DV		 5161 } else {
5162 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5163 return;
5164 }
5165
06922821 5166 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 5167 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5168 if (INTEL_INFO(dev)->gen < 5)
5169 pipe_config->gmch_pfit.lvds_border_bits =
5170 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5171}
5172
acbec814
JB		 5173static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5174 struct intel_crtc_config *pipe_config)
5175{
5176 struct drm_device *dev = crtc->base.dev;
5177 struct drm_i915_private *dev_priv = dev->dev_private;
5178 int pipe = pipe_config->cpu_transcoder;
5179 intel_clock_t clock;
5180 u32 mdiv;
662c6ecb 5181 int refclk = 100000;
acbec814
JB		 5182
5183 mutex_lock(&dev_priv->dpio_lock);
5184 mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5185 mutex_unlock(&dev_priv->dpio_lock);
5186
5187 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5188 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5189 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5190 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5191 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5192
662c6ecb
CW		 5193 clock.vco = refclk * clock.m1 * clock.m2 / clock.n;
5194 clock.dot = 2 * clock.vco / (clock.p1 * clock.p2);
acbec814
JB		 5195
5196 pipe_config->port_clock = clock.dot / 10;
5197}
5198
0e8ffe1b
DV		 5199static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5200 struct intel_crtc_config *pipe_config)
5201{
5202 struct drm_device *dev = crtc->base.dev;
5203 struct drm_i915_private *dev_priv = dev->dev_private;
5204 uint32_t tmp;
5205
e143a21c 5206 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5207 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5208
0e8ffe1b
DV		 5209 tmp = I915_READ(PIPECONF(crtc->pipe));
5210 if (!(tmp & PIPECONF_ENABLE))
5211 return false;
5212
42571aef
VS		 5213 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5214 switch (tmp & PIPECONF_BPC_MASK) {
5215 case PIPECONF_6BPC:
5216 pipe_config->pipe_bpp = 18;
5217 break;
5218 case PIPECONF_8BPC:
5219 pipe_config->pipe_bpp = 24;
5220 break;
5221 case PIPECONF_10BPC:
5222 pipe_config->pipe_bpp = 30;
5223 break;
5224 default:
5225 break;
5226 }
5227 }
5228
282740f7
VS		 5229 if (INTEL_INFO(dev)->gen < 4)
5230 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5231
1bd1bd80
DV		 5232 intel_get_pipe_timings(crtc, pipe_config);
5233
2fa2fe9a
DV		 5234 i9xx_get_pfit_config(crtc, pipe_config);
5235
6c49f241
DV		 5236 if (INTEL_INFO(dev)->gen >= 4) {
5237 tmp = I915_READ(DPLL_MD(crtc->pipe));
5238 pipe_config->pixel_multiplier =
5239 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5240 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5241 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5242 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5243 tmp = I915_READ(DPLL(crtc->pipe));
5244 pipe_config->pixel_multiplier =
5245 ((tmp & SDVO_MULTIPLIER_MASK)
5246 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5247 } else {
5248 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5249 * port and will be fixed up in the encoder->get_config
5250 * function. */
5251 pipe_config->pixel_multiplier = 1;
5252 }
8bcc2795
DV		 5253 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5254 if (!IS_VALLEYVIEW(dev)) {
5255 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5256 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5257 } else {
5258 /* Mask out read-only status bits. */
5259 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5260 DPLL_PORTC_READY_MASK |
5261 DPLL_PORTB_READY_MASK);
8bcc2795 5262 }
6c49f241 5263
acbec814
JB		 5264 if (IS_VALLEYVIEW(dev))
5265 vlv_crtc_clock_get(crtc, pipe_config);
5266 else
5267 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 5268
0e8ffe1b
DV		 5269 return true;
5270}
5271
dde86e2d 5272static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5273{
5274 struct drm_i915_private *dev_priv = dev->dev_private;
5275 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5276 struct intel_encoder *encoder;
74cfd7ac 5277 u32 val, final;
13d83a67 5278 bool has_lvds = false;
199e5d79 5279 bool has_cpu_edp = false;
199e5d79 5280 bool has_panel = false;
99eb6a01
KP		 5281 bool has_ck505 = false;
5282 bool can_ssc = false;
13d83a67
JB		 5283
5284 /* We need to take the global config into account */
199e5d79
KP		 5285 list_for_each_entry(encoder, &mode_config->encoder_list,
5286 base.head) {
5287 switch (encoder->type) {
5288 case INTEL_OUTPUT_LVDS:
5289 has_panel = true;
5290 has_lvds = true;
5291 break;
5292 case INTEL_OUTPUT_EDP:
5293 has_panel = true;
2de6905f 5294 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5295 has_cpu_edp = true;
5296 break;
13d83a67
JB		 5297 }
5298 }
5299
99eb6a01 5300 if (HAS_PCH_IBX(dev)) {
41aa3448 5301 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5302 can_ssc = has_ck505;
5303 } else {
5304 has_ck505 = false;
5305 can_ssc = true;
5306 }
5307
2de6905f
ID		 5308 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5309 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5310
5311 /* Ironlake: try to setup display ref clock before DPLL
5312 * enabling. This is only under driver's control after
5313 * PCH B stepping, previous chipset stepping should be
5314 * ignoring this setting.
5315 */
74cfd7ac
CW		 5316 val = I915_READ(PCH_DREF_CONTROL);
5317
5318 /* As we must carefully and slowly disable/enable each source in turn,
5319 * compute the final state we want first and check if we need to
5320 * make any changes at all.
5321 */
5322 final = val;
5323 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5324 if (has_ck505)
5325 final |= DREF_NONSPREAD_CK505_ENABLE;
5326 else
5327 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5328
5329 final &= ~DREF_SSC_SOURCE_MASK;
5330 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5331 final &= ~DREF_SSC1_ENABLE;
5332
5333 if (has_panel) {
5334 final |= DREF_SSC_SOURCE_ENABLE;
5335
5336 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5337 final |= DREF_SSC1_ENABLE;
5338
5339 if (has_cpu_edp) {
5340 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5341 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5342 else
5343 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5344 } else
5345 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5346 } else {
5347 final |= DREF_SSC_SOURCE_DISABLE;
5348 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5349 }
5350
5351 if (final == val)
5352 return;
5353
13d83a67 5354 /* Always enable nonspread source */
74cfd7ac 5355 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5356
99eb6a01 5357 if (has_ck505)
74cfd7ac 5358 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5359 else
74cfd7ac 5360 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5361
199e5d79 5362 if (has_panel) {
74cfd7ac
CW		 5363 val &= ~DREF_SSC_SOURCE_MASK;
5364 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5365
199e5d79 5366 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5367 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5368 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5369 val |= DREF_SSC1_ENABLE;
e77166b5 5370 } else
74cfd7ac 5371 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5372
5373 /* Get SSC going before enabling the outputs */
74cfd7ac 5374 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5375 POSTING_READ(PCH_DREF_CONTROL);
5376 udelay(200);
5377
74cfd7ac 5378 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5379
5380 /* Enable CPU source on CPU attached eDP */
199e5d79 5381 if (has_cpu_edp) {
99eb6a01 5382 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5383 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5384 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5385 }
13d83a67 5386 else
74cfd7ac 5387 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5388 } else
74cfd7ac 5389 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5390
74cfd7ac 5391 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5392 POSTING_READ(PCH_DREF_CONTROL);
5393 udelay(200);
5394 } else {
5395 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5396
74cfd7ac 5397 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5398
5399 /* Turn off CPU output */
74cfd7ac 5400 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5401
74cfd7ac 5402 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5403 POSTING_READ(PCH_DREF_CONTROL);
5404 udelay(200);
5405
5406 /* Turn off the SSC source */
74cfd7ac
CW		 5407 val &= ~DREF_SSC_SOURCE_MASK;
5408 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5409
5410 /* Turn off SSC1 */
74cfd7ac 5411 val &= ~DREF_SSC1_ENABLE;
199e5d79 5412
74cfd7ac 5413 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5414 POSTING_READ(PCH_DREF_CONTROL);
5415 udelay(200);
5416 }
74cfd7ac
CW		 5417
5418 BUG_ON(val != final);
13d83a67
JB		 5419}
5420
f31f2d55 5421static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5422{
f31f2d55 5423 uint32_t tmp;
dde86e2d 5424
0ff066a9
PZ		 5425 tmp = I915_READ(SOUTH_CHICKEN2);
5426 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5427 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5428
0ff066a9
PZ		 5429 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5430 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5431 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5432
0ff066a9
PZ		 5433 tmp = I915_READ(SOUTH_CHICKEN2);
5434 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5435 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5436
0ff066a9
PZ		 5437 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5438 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5439 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5440}
5441
5442/* WaMPhyProgramming:hsw */
5443static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5444{
5445 uint32_t tmp;
dde86e2d
PZ		 5446
5447 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5448 tmp &= ~(0xFF << 24);
5449 tmp |= (0x12 << 24);
5450 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5451
dde86e2d
PZ		 5452 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5453 tmp |= (1 << 11);
5454 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5455
5456 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5457 tmp |= (1 << 11);
5458 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5459
dde86e2d
PZ		 5460 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5461 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5462 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5463
5464 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5465 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5466 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5467
0ff066a9
PZ		 5468 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5469 tmp &= ~(7 << 13);
5470 tmp |= (5 << 13);
5471 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5472
0ff066a9
PZ		 5473 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5474 tmp &= ~(7 << 13);
5475 tmp |= (5 << 13);
5476 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5477
5478 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5479 tmp &= ~0xFF;
5480 tmp |= 0x1C;
5481 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5482
5483 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5484 tmp &= ~0xFF;
5485 tmp |= 0x1C;
5486 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5487
5488 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5489 tmp &= ~(0xFF << 16);
5490 tmp |= (0x1C << 16);
5491 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5492
5493 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5494 tmp &= ~(0xFF << 16);
5495 tmp |= (0x1C << 16);
5496 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5497
0ff066a9
PZ		 5498 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5499 tmp |= (1 << 27);
5500 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5501
0ff066a9
PZ		 5502 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5503 tmp |= (1 << 27);
5504 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5505
0ff066a9
PZ		 5506 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5507 tmp &= ~(0xF << 28);
5508 tmp |= (4 << 28);
5509 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5510
0ff066a9
PZ		 5511 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5512 tmp &= ~(0xF << 28);
5513 tmp |= (4 << 28);
5514 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5515}
5516
2fa86a1f
PZ		 5517/* Implements 3 different sequences from BSpec chapter "Display iCLK
5518 * Programming" based on the parameters passed:
5519 * - Sequence to enable CLKOUT_DP
5520 * - Sequence to enable CLKOUT_DP without spread
5521 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5522 */
5523static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5524 bool with_fdi)
f31f2d55
PZ		 5525{
5526 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5527 uint32_t reg, tmp;
5528
5529 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5530 with_spread = true;
5531 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5532 with_fdi, "LP PCH doesn't have FDI\n"))
5533 with_fdi = false;
f31f2d55
PZ		 5534
5535 mutex_lock(&dev_priv->dpio_lock);
5536
5537 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5538 tmp &= ~SBI_SSCCTL_DISABLE;
5539 tmp |= SBI_SSCCTL_PATHALT;
5540 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5541
5542 udelay(24);
5543
2fa86a1f
PZ		 5544 if (with_spread) {
5545 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5546 tmp &= ~SBI_SSCCTL_PATHALT;
5547 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5548
2fa86a1f
PZ		 5549 if (with_fdi) {
5550 lpt_reset_fdi_mphy(dev_priv);
5551 lpt_program_fdi_mphy(dev_priv);
5552 }
5553 }
dde86e2d 5554
2fa86a1f
PZ		 5555 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5556 SBI_GEN0 : SBI_DBUFF0;
5557 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5558 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5559 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5560
5561 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5562}
5563
47701c3b
PZ		 5564/* Sequence to disable CLKOUT_DP */
5565static void lpt_disable_clkout_dp(struct drm_device *dev)
5566{
5567 struct drm_i915_private *dev_priv = dev->dev_private;
5568 uint32_t reg, tmp;
5569
5570 mutex_lock(&dev_priv->dpio_lock);
5571
5572 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5573 SBI_GEN0 : SBI_DBUFF0;
5574 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5575 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5576 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5577
5578 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5579 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5580 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5581 tmp |= SBI_SSCCTL_PATHALT;
5582 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5583 udelay(32);
5584 }
5585 tmp |= SBI_SSCCTL_DISABLE;
5586 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5587 }
5588
5589 mutex_unlock(&dev_priv->dpio_lock);
5590}
5591
bf8fa3d3
PZ		 5592static void lpt_init_pch_refclk(struct drm_device *dev)
5593{
5594 struct drm_mode_config *mode_config = &dev->mode_config;
5595 struct intel_encoder *encoder;
5596 bool has_vga = false;
5597
5598 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5599 switch (encoder->type) {
5600 case INTEL_OUTPUT_ANALOG:
5601 has_vga = true;
5602 break;
5603 }
5604 }
5605
47701c3b
PZ		 5606 if (has_vga)
5607 lpt_enable_clkout_dp(dev, true, true);
5608 else
5609 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5610}
5611
dde86e2d
PZ		 5612/*
5613 * Initialize reference clocks when the driver loads
5614 */
5615void intel_init_pch_refclk(struct drm_device *dev)
5616{
5617 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5618 ironlake_init_pch_refclk(dev);
5619 else if (HAS_PCH_LPT(dev))
5620 lpt_init_pch_refclk(dev);
5621}
5622
d9d444cb
JB		 5623static int ironlake_get_refclk(struct drm_crtc *crtc)
5624{
5625 struct drm_device *dev = crtc->dev;
5626 struct drm_i915_private *dev_priv = dev->dev_private;
5627 struct intel_encoder *encoder;
d9d444cb
JB		 5628 int num_connectors = 0;
5629 bool is_lvds = false;
5630
6c2b7c12 5631 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5632 switch (encoder->type) {
5633 case INTEL_OUTPUT_LVDS:
5634 is_lvds = true;
5635 break;
d9d444cb
JB		 5636 }
5637 num_connectors++;
5638 }
5639
5640 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5641 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5642 dev_priv->vbt.lvds_ssc_freq);
5643 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5644 }
5645
5646 return 120000;
5647}
5648
6ff93609 5649static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5650{
c8203565 5651 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5652 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5653 int pipe = intel_crtc->pipe;
c8203565
PZ		 5654 uint32_t val;
5655
78114071 5656 val = 0;
c8203565 5657
965e0c48 5658 switch (intel_crtc->config.pipe_bpp) {
c8203565 5659 case 18:
dfd07d72 5660 val |= PIPECONF_6BPC;
c8203565
PZ		 5661 break;
5662 case 24:
dfd07d72 5663 val |= PIPECONF_8BPC;
c8203565
PZ		 5664 break;
5665 case 30:
dfd07d72 5666 val |= PIPECONF_10BPC;
c8203565
PZ		 5667 break;
5668 case 36:
dfd07d72 5669 val |= PIPECONF_12BPC;
c8203565
PZ		 5670 break;
5671 default:
cc769b62
PZ		 5672 /* Case prevented by intel_choose_pipe_bpp_dither. */
5673 BUG();
c8203565
PZ		 5674 }
5675
d8b32247 5676 if (intel_crtc->config.dither)
c8203565
PZ		 5677 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5678
6ff93609 5679 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5680 val |= PIPECONF_INTERLACED_ILK;
5681 else
5682 val |= PIPECONF_PROGRESSIVE;
5683
50f3b016 5684 if (intel_crtc->config.limited_color_range)
3685a8f3 5685 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5686
c8203565
PZ		 5687 I915_WRITE(PIPECONF(pipe), val);
5688 POSTING_READ(PIPECONF(pipe));
5689}
5690
86d3efce
VS		 5691/*
5692 * Set up the pipe CSC unit.
5693 *
5694 * Currently only full range RGB to limited range RGB conversion
5695 * is supported, but eventually this should handle various
5696 * RGB<->YCbCr scenarios as well.
5697 */
50f3b016 5698static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5699{
5700 struct drm_device *dev = crtc->dev;
5701 struct drm_i915_private *dev_priv = dev->dev_private;
5702 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5703 int pipe = intel_crtc->pipe;
5704 uint16_t coeff = 0x7800; /* 1.0 */
5705
5706 /*
5707 * TODO: Check what kind of values actually come out of the pipe
5708 * with these coeff/postoff values and adjust to get the best
5709 * accuracy. Perhaps we even need to take the bpc value into
5710 * consideration.
5711 */
5712
50f3b016 5713 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5714 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5715
5716 /*
5717 * GY/GU and RY/RU should be the other way around according
5718 * to BSpec, but reality doesn't agree. Just set them up in
5719 * a way that results in the correct picture.
5720 */
5721 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5722 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5723
5724 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5725 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5726
5727 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5728 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5729
5730 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5731 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5732 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5733
5734 if (INTEL_INFO(dev)->gen > 6) {
5735 uint16_t postoff = 0;
5736
50f3b016 5737 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5738 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5739
5740 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5741 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5742 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5743
5744 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5745 } else {
5746 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5747
50f3b016 5748 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5749 mode |= CSC_BLACK_SCREEN_OFFSET;
5750
5751 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5752 }
5753}
5754
6ff93609 5755static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5756{
5757 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5758 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5759 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5760 uint32_t val;
5761
3eff4faa 5762 val = 0;
ee2b0b38 5763
d8b32247 5764 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5765 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5766
6ff93609 5767 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5768 val |= PIPECONF_INTERLACED_ILK;
5769 else
5770 val |= PIPECONF_PROGRESSIVE;
5771
702e7a56
PZ		 5772 I915_WRITE(PIPECONF(cpu_transcoder), val);
5773 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5774
5775 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5776 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5777}
5778
6591c6e4 5779static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5780 intel_clock_t *clock,
5781 bool *has_reduced_clock,
5782 intel_clock_t *reduced_clock)
5783{
5784 struct drm_device *dev = crtc->dev;
5785 struct drm_i915_private *dev_priv = dev->dev_private;
5786 struct intel_encoder *intel_encoder;
5787 int refclk;
d4906093 5788 const intel_limit_t *limit;
a16af721 5789 bool ret, is_lvds = false;
79e53945 5790
6591c6e4
PZ		 5791 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5792 switch (intel_encoder->type) {
79e53945
JB		 5793 case INTEL_OUTPUT_LVDS:
5794 is_lvds = true;
5795 break;
79e53945
JB		 5796 }
5797 }
5798
d9d444cb 5799 refclk = ironlake_get_refclk(crtc);
79e53945 5800
d4906093
ML		 5801 /*
5802 * Returns a set of divisors for the desired target clock with the given
5803 * refclk, or FALSE. The returned values represent the clock equation:
5804 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5805 */
1b894b59 5806 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5807 ret = dev_priv->display.find_dpll(limit, crtc,
5808 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5809 refclk, NULL, clock);
6591c6e4
PZ		 5810 if (!ret)
5811 return false;
cda4b7d3 5812
ddc9003c 5813 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5814 /*
5815 * Ensure we match the reduced clock's P to the target clock.
5816 * If the clocks don't match, we can't switch the display clock
5817 * by using the FP0/FP1. In such case we will disable the LVDS
5818 * downclock feature.
5819 */
ee9300bb
DV		 5820 *has_reduced_clock =
5821 dev_priv->display.find_dpll(limit, crtc,
5822 dev_priv->lvds_downclock,
5823 refclk, clock,
5824 reduced_clock);
652c393a 5825 }
61e9653f 5826
6591c6e4
PZ		 5827 return true;
5828}
5829
01a415fd
DV		 5830static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5831{
5832 struct drm_i915_private *dev_priv = dev->dev_private;
5833 uint32_t temp;
5834
5835 temp = I915_READ(SOUTH_CHICKEN1);
5836 if (temp & FDI_BC_BIFURCATION_SELECT)
5837 return;
5838
5839 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5840 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5841
5842 temp |= FDI_BC_BIFURCATION_SELECT;
5843 DRM_DEBUG_KMS("enabling fdi C rx\n");
5844 I915_WRITE(SOUTH_CHICKEN1, temp);
5845 POSTING_READ(SOUTH_CHICKEN1);
5846}
5847
ebfd86fd 5848static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5849{
5850 struct drm_device *dev = intel_crtc->base.dev;
5851 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5852
5853 switch (intel_crtc->pipe) {
5854 case PIPE_A:
ebfd86fd 5855 break;
01a415fd 5856 case PIPE_B:
ebfd86fd 5857 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5858 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5859 else
5860 cpt_enable_fdi_bc_bifurcation(dev);
5861
ebfd86fd 5862 break;
01a415fd 5863 case PIPE_C:
01a415fd
DV		 5864 cpt_enable_fdi_bc_bifurcation(dev);
5865
ebfd86fd 5866 break;
01a415fd
DV		 5867 default:
5868 BUG();
5869 }
5870}
5871
d4b1931c
PZ		 5872int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5873{
5874 /*
5875 * Account for spread spectrum to avoid
5876 * oversubscribing the link. Max center spread
5877 * is 2.5%; use 5% for safety's sake.
5878 */
5879 u32 bps = target_clock * bpp * 21 / 20;
5880 return bps / (link_bw * 8) + 1;
5881}
5882
7429e9d4 5883static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5884{
7429e9d4 5885 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5886}
5887
de13a2e3 5888static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5889 u32 *fp,
9a7c7890 5890 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5891{
de13a2e3 5892 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5893 struct drm_device *dev = crtc->dev;
5894 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5895 struct intel_encoder *intel_encoder;
5896 uint32_t dpll;
6cc5f341 5897 int factor, num_connectors = 0;
09ede541 5898 bool is_lvds = false, is_sdvo = false;
79e53945 5899
de13a2e3
PZ		 5900 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5901 switch (intel_encoder->type) {
79e53945
JB		 5902 case INTEL_OUTPUT_LVDS:
5903 is_lvds = true;
5904 break;
5905 case INTEL_OUTPUT_SDVO:
7d57382e 5906 case INTEL_OUTPUT_HDMI:
79e53945 5907 is_sdvo = true;
79e53945 5908 break;
79e53945 5909 }
43565a06 5910
c751ce4f 5911 num_connectors++;
79e53945 5912 }
79e53945 5913
c1858123 5914 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5915 factor = 21;
5916 if (is_lvds) {
5917 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5918 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5919 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5920 factor = 25;
09ede541 5921 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5922 factor = 20;
c1858123 5923
7429e9d4 5924 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5925 *fp |= FP_CB_TUNE;
2c07245f 5926
9a7c7890
DV		 5927 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5928 *fp2 |= FP_CB_TUNE;
5929
5eddb70b 5930 dpll = 0;
2c07245f 5931
a07d6787
EA		 5932 if (is_lvds)
5933 dpll |= DPLLB_MODE_LVDS;
5934 else
5935 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5936
ef1b460d
DV		 5937 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5938 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5939
5940 if (is_sdvo)
4a33e48d 5941 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5942 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5943 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5944
a07d6787 5945 /* compute bitmask from p1 value */
7429e9d4 5946 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5947 /* also FPA1 */
7429e9d4 5948 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5949
7429e9d4 5950 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5951 case 5:
5952 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5953 break;
5954 case 7:
5955 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5956 break;
5957 case 10:
5958 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5959 break;
5960 case 14:
5961 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5962 break;
79e53945
JB		 5963 }
5964
b4c09f3b 5965 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5966 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5967 else
5968 dpll |= PLL_REF_INPUT_DREFCLK;
5969
959e16d6 5970 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5971}
5972
5973static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5974 int x, int y,
5975 struct drm_framebuffer *fb)
5976{
5977 struct drm_device *dev = crtc->dev;
5978 struct drm_i915_private *dev_priv = dev->dev_private;
5979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5980 int pipe = intel_crtc->pipe;
5981 int plane = intel_crtc->plane;
5982 int num_connectors = 0;
5983 intel_clock_t clock, reduced_clock;
cbbab5bd 5984 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5985 bool ok, has_reduced_clock = false;
8b47047b 5986 bool is_lvds = false;
de13a2e3 5987 struct intel_encoder *encoder;
e2b78267 5988 struct intel_shared_dpll *pll;
de13a2e3 5989 int ret;
de13a2e3
PZ		 5990
5991 for_each_encoder_on_crtc(dev, crtc, encoder) {
5992 switch (encoder->type) {
5993 case INTEL_OUTPUT_LVDS:
5994 is_lvds = true;
5995 break;
de13a2e3
PZ		 5996 }
5997
5998 num_connectors++;
a07d6787 5999 }
79e53945 6000
5dc5298b
PZ		 6001 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6002 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 6003
ff9a6750 6004 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 6005 &has_reduced_clock, &reduced_clock);
ee9300bb 6006 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 6007 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6008 return -EINVAL;
79e53945 6009 }
f47709a9
DV		 6010 /* Compat-code for transition, will disappear. */
6011 if (!intel_crtc->config.clock_set) {
6012 intel_crtc->config.dpll.n = clock.n;
6013 intel_crtc->config.dpll.m1 = clock.m1;
6014 intel_crtc->config.dpll.m2 = clock.m2;
6015 intel_crtc->config.dpll.p1 = clock.p1;
6016 intel_crtc->config.dpll.p2 = clock.p2;
6017 }
79e53945 6018
5dc5298b 6019 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 6020 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 6021 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 6022 if (has_reduced_clock)
7429e9d4 6023 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 6024
7429e9d4 6025 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 6026 &fp, &reduced_clock,
6027 has_reduced_clock ? &fp2 : NULL);
6028
959e16d6 6029 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 6030 intel_crtc->config.dpll_hw_state.fp0 = fp;
6031 if (has_reduced_clock)
6032 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6033 else
6034 intel_crtc->config.dpll_hw_state.fp1 = fp;
6035
b89a1d39 6036 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 6037 if (pll == NULL) {
84f44ce7
VS		 6038 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6039 pipe_name(pipe));
4b645f14
JB		 6040 return -EINVAL;
6041 }
ee7b9f93 6042 } else
e72f9fbf 6043 intel_put_shared_dpll(intel_crtc);
79e53945 6044
03afc4a2
DV		 6045 if (intel_crtc->config.has_dp_encoder)
6046 intel_dp_set_m_n(intel_crtc);
79e53945 6047
bcd644e0
DV		 6048 if (is_lvds && has_reduced_clock && i915_powersave)
6049 intel_crtc->lowfreq_avail = true;
6050 else
6051 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 6052
6053 if (intel_crtc->config.has_pch_encoder) {
6054 pll = intel_crtc_to_shared_dpll(intel_crtc);
6055
652c393a
JB		 6056 }
6057
8a654f3b 6058 intel_set_pipe_timings(intel_crtc);
5eddb70b 6059
ca3a0ff8 6060 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6061 intel_cpu_transcoder_set_m_n(intel_crtc,
6062 &intel_crtc->config.fdi_m_n);
6063 }
2c07245f 6064
ebfd86fd
DV		 6065 if (IS_IVYBRIDGE(dev))
6066 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 6067
6ff93609 6068 ironlake_set_pipeconf(crtc);
79e53945 6069
a1f9e77e
PZ		 6070 /* Set up the display plane register */
6071 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 6072 POSTING_READ(DSPCNTR(plane));
79e53945 6073
94352cf9 6074 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd 6075
1857e1da 6076 return ret;
79e53945
JB		 6077}
6078
eb14cb74
VS		 6079static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6080 struct intel_link_m_n *m_n)
6081{
6082 struct drm_device *dev = crtc->base.dev;
6083 struct drm_i915_private *dev_priv = dev->dev_private;
6084 enum pipe pipe = crtc->pipe;
6085
6086 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6087 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6088 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6089 & ~TU_SIZE_MASK;
6090 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6091 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6092 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6093}
6094
6095static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6096 enum transcoder transcoder,
6097 struct intel_link_m_n *m_n)
72419203
DV		 6098{
6099 struct drm_device *dev = crtc->base.dev;
6100 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 6101 enum pipe pipe = crtc->pipe;
72419203 6102
eb14cb74
VS		 6103 if (INTEL_INFO(dev)->gen >= 5) {
6104 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6105 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6106 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6107 & ~TU_SIZE_MASK;
6108 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6109 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6110 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6111 } else {
6112 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6113 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6114 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6115 & ~TU_SIZE_MASK;
6116 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6117 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6118 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6119 }
6120}
6121
6122void intel_dp_get_m_n(struct intel_crtc *crtc,
6123 struct intel_crtc_config *pipe_config)
6124{
6125 if (crtc->config.has_pch_encoder)
6126 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6127 else
6128 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6129 &pipe_config->dp_m_n);
6130}
72419203 6131
eb14cb74
VS		 6132static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6133 struct intel_crtc_config *pipe_config)
6134{
6135 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6136 &pipe_config->fdi_m_n);
72419203
DV		 6137}
6138
2fa2fe9a
DV		 6139static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6140 struct intel_crtc_config *pipe_config)
6141{
6142 struct drm_device *dev = crtc->base.dev;
6143 struct drm_i915_private *dev_priv = dev->dev_private;
6144 uint32_t tmp;
6145
6146 tmp = I915_READ(PF_CTL(crtc->pipe));
6147
6148 if (tmp & PF_ENABLE) {
fd4daa9c 6149 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 6150 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6151 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 6152
6153 /* We currently do not free assignements of panel fitters on
6154 * ivb/hsw (since we don't use the higher upscaling modes which
6155 * differentiates them) so just WARN about this case for now. */
6156 if (IS_GEN7(dev)) {
6157 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6158 PF_PIPE_SEL_IVB(crtc->pipe));
6159 }
2fa2fe9a 6160 }
79e53945
JB		 6161}
6162
0e8ffe1b
DV		 6163static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6164 struct intel_crtc_config *pipe_config)
6165{
6166 struct drm_device *dev = crtc->base.dev;
6167 struct drm_i915_private *dev_priv = dev->dev_private;
6168 uint32_t tmp;
6169
e143a21c 6170 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 6171 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 6172
0e8ffe1b
DV		 6173 tmp = I915_READ(PIPECONF(crtc->pipe));
6174 if (!(tmp & PIPECONF_ENABLE))
6175 return false;
6176
42571aef
VS		 6177 switch (tmp & PIPECONF_BPC_MASK) {
6178 case PIPECONF_6BPC:
6179 pipe_config->pipe_bpp = 18;
6180 break;
6181 case PIPECONF_8BPC:
6182 pipe_config->pipe_bpp = 24;
6183 break;
6184 case PIPECONF_10BPC:
6185 pipe_config->pipe_bpp = 30;
6186 break;
6187 case PIPECONF_12BPC:
6188 pipe_config->pipe_bpp = 36;
6189 break;
6190 default:
6191 break;
6192 }
6193
ab9412ba 6194 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 6195 struct intel_shared_dpll *pll;
6196
88adfff1
DV		 6197 pipe_config->has_pch_encoder = true;
6198
627eb5a3
DV		 6199 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6200 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6201 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6202
6203 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 6204
c0d43d62 6205 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 6206 pipe_config->shared_dpll =
6207 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 6208 } else {
6209 tmp = I915_READ(PCH_DPLL_SEL);
6210 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6211 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6212 else
6213 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6214 }
66e985c0
DV		 6215
6216 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6217
6218 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6219 &pipe_config->dpll_hw_state));
c93f54cf
DV		 6220
6221 tmp = pipe_config->dpll_hw_state.dpll;
6222 pipe_config->pixel_multiplier =
6223 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6224 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 6225
6226 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 6227 } else {
6228 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 6229 }
6230
1bd1bd80
DV		 6231 intel_get_pipe_timings(crtc, pipe_config);
6232
2fa2fe9a
DV		 6233 ironlake_get_pfit_config(crtc, pipe_config);
6234
0e8ffe1b
DV		 6235 return true;
6236}
6237
be256dc7
PZ		 6238static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6239{
6240 struct drm_device *dev = dev_priv->dev;
6241 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6242 struct intel_crtc *crtc;
6243 unsigned long irqflags;
bd633a7c 6244 uint32_t val;
be256dc7
PZ		 6245
6246 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6247 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6248 pipe_name(crtc->pipe));
6249
6250 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6251 WARN(plls->spll_refcount, "SPLL enabled\n");
6252 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6253 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6254 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6255 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6256 "CPU PWM1 enabled\n");
6257 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6258 "CPU PWM2 enabled\n");
6259 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6260 "PCH PWM1 enabled\n");
6261 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6262 "Utility pin enabled\n");
6263 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6264
6265 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6266 val = I915_READ(DEIMR);
6267 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6268 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6269 val = I915_READ(SDEIMR);
bd633a7c 6270 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 6271 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6272 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6273}
6274
6275/*
6276 * This function implements pieces of two sequences from BSpec:
6277 * - Sequence for display software to disable LCPLL
6278 * - Sequence for display software to allow package C8+
6279 * The steps implemented here are just the steps that actually touch the LCPLL
6280 * register. Callers should take care of disabling all the display engine
6281 * functions, doing the mode unset, fixing interrupts, etc.
6282 */
6ff58d53
PZ		 6283static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6284 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 6285{
6286 uint32_t val;
6287
6288 assert_can_disable_lcpll(dev_priv);
6289
6290 val = I915_READ(LCPLL_CTL);
6291
6292 if (switch_to_fclk) {
6293 val |= LCPLL_CD_SOURCE_FCLK;
6294 I915_WRITE(LCPLL_CTL, val);
6295
6296 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6297 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6298 DRM_ERROR("Switching to FCLK failed\n");
6299
6300 val = I915_READ(LCPLL_CTL);
6301 }
6302
6303 val |= LCPLL_PLL_DISABLE;
6304 I915_WRITE(LCPLL_CTL, val);
6305 POSTING_READ(LCPLL_CTL);
6306
6307 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6308 DRM_ERROR("LCPLL still locked\n");
6309
6310 val = I915_READ(D_COMP);
6311 val |= D_COMP_COMP_DISABLE;
515b2392
PZ		 6312 mutex_lock(&dev_priv->rps.hw_lock);
6313 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6314 DRM_ERROR("Failed to disable D_COMP\n");
6315 mutex_unlock(&dev_priv->rps.hw_lock);
be256dc7
PZ		 6316 POSTING_READ(D_COMP);
6317 ndelay(100);
6318
6319 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6320 DRM_ERROR("D_COMP RCOMP still in progress\n");
6321
6322 if (allow_power_down) {
6323 val = I915_READ(LCPLL_CTL);
6324 val |= LCPLL_POWER_DOWN_ALLOW;
6325 I915_WRITE(LCPLL_CTL, val);
6326 POSTING_READ(LCPLL_CTL);
6327 }
6328}
6329
6330/*
6331 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6332 * source.
6333 */
6ff58d53 6334static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 6335{
6336 uint32_t val;
6337
6338 val = I915_READ(LCPLL_CTL);
6339
6340 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6341 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6342 return;
6343
215733fa
PZ		 6344 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6345 * we'll hang the machine! */
6346 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6347
be256dc7
PZ		 6348 if (val & LCPLL_POWER_DOWN_ALLOW) {
6349 val &= ~LCPLL_POWER_DOWN_ALLOW;
6350 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6351 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6352 }
6353
6354 val = I915_READ(D_COMP);
6355 val |= D_COMP_COMP_FORCE;
6356 val &= ~D_COMP_COMP_DISABLE;
515b2392
PZ		 6357 mutex_lock(&dev_priv->rps.hw_lock);
6358 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6359 DRM_ERROR("Failed to enable D_COMP\n");
6360 mutex_unlock(&dev_priv->rps.hw_lock);
35d8f2eb 6361 POSTING_READ(D_COMP);
be256dc7
PZ		 6362
6363 val = I915_READ(LCPLL_CTL);
6364 val &= ~LCPLL_PLL_DISABLE;
6365 I915_WRITE(LCPLL_CTL, val);
6366
6367 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6368 DRM_ERROR("LCPLL not locked yet\n");
6369
6370 if (val & LCPLL_CD_SOURCE_FCLK) {
6371 val = I915_READ(LCPLL_CTL);
6372 val &= ~LCPLL_CD_SOURCE_FCLK;
6373 I915_WRITE(LCPLL_CTL, val);
6374
6375 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6376 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6377 DRM_ERROR("Switching back to LCPLL failed\n");
6378 }
215733fa
PZ		 6379
6380 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6381}
6382
c67a470b
PZ		 6383void hsw_enable_pc8_work(struct work_struct *__work)
6384{
6385 struct drm_i915_private *dev_priv =
6386 container_of(to_delayed_work(__work), struct drm_i915_private,
6387 pc8.enable_work);
6388 struct drm_device *dev = dev_priv->dev;
6389 uint32_t val;
6390
6391 if (dev_priv->pc8.enabled)
6392 return;
6393
6394 DRM_DEBUG_KMS("Enabling package C8+\n");
6395
6396 dev_priv->pc8.enabled = true;
6397
6398 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6399 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6400 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6401 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6402 }
6403
6404 lpt_disable_clkout_dp(dev);
6405 hsw_pc8_disable_interrupts(dev);
6406 hsw_disable_lcpll(dev_priv, true, true);
6407}
6408
6409static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6410{
6411 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6412 WARN(dev_priv->pc8.disable_count < 1,
6413 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6414
6415 dev_priv->pc8.disable_count--;
6416 if (dev_priv->pc8.disable_count != 0)
6417 return;
6418
6419 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6420 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6421}
6422
6423static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6424{
6425 struct drm_device *dev = dev_priv->dev;
6426 uint32_t val;
6427
6428 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6429 WARN(dev_priv->pc8.disable_count < 0,
6430 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6431
6432 dev_priv->pc8.disable_count++;
6433 if (dev_priv->pc8.disable_count != 1)
6434 return;
6435
6436 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6437 if (!dev_priv->pc8.enabled)
6438 return;
6439
6440 DRM_DEBUG_KMS("Disabling package C8+\n");
6441
6442 hsw_restore_lcpll(dev_priv);
6443 hsw_pc8_restore_interrupts(dev);
6444 lpt_init_pch_refclk(dev);
6445
6446 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6447 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6448 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6449 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6450 }
6451
6452 intel_prepare_ddi(dev);
6453 i915_gem_init_swizzling(dev);
6454 mutex_lock(&dev_priv->rps.hw_lock);
6455 gen6_update_ring_freq(dev);
6456 mutex_unlock(&dev_priv->rps.hw_lock);
6457 dev_priv->pc8.enabled = false;
6458}
6459
6460void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6461{
6462 mutex_lock(&dev_priv->pc8.lock);
6463 __hsw_enable_package_c8(dev_priv);
6464 mutex_unlock(&dev_priv->pc8.lock);
6465}
6466
6467void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6468{
6469 mutex_lock(&dev_priv->pc8.lock);
6470 __hsw_disable_package_c8(dev_priv);
6471 mutex_unlock(&dev_priv->pc8.lock);
6472}
6473
6474static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6475{
6476 struct drm_device *dev = dev_priv->dev;
6477 struct intel_crtc *crtc;
6478 uint32_t val;
6479
6480 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6481 if (crtc->base.enabled)
6482 return false;
6483
6484 /* This case is still possible since we have the i915.disable_power_well
6485 * parameter and also the KVMr or something else might be requesting the
6486 * power well. */
6487 val = I915_READ(HSW_PWR_WELL_DRIVER);
6488 if (val != 0) {
6489 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6490 return false;
6491 }
6492
6493 return true;
6494}
6495
6496/* Since we're called from modeset_global_resources there's no way to
6497 * symmetrically increase and decrease the refcount, so we use
6498 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6499 * or not.
6500 */
6501static void hsw_update_package_c8(struct drm_device *dev)
6502{
6503 struct drm_i915_private *dev_priv = dev->dev_private;
6504 bool allow;
6505
6506 if (!i915_enable_pc8)
6507 return;
6508
6509 mutex_lock(&dev_priv->pc8.lock);
6510
6511 allow = hsw_can_enable_package_c8(dev_priv);
6512
6513 if (allow == dev_priv->pc8.requirements_met)
6514 goto done;
6515
6516 dev_priv->pc8.requirements_met = allow;
6517
6518 if (allow)
6519 __hsw_enable_package_c8(dev_priv);
6520 else
6521 __hsw_disable_package_c8(dev_priv);
6522
6523done:
6524 mutex_unlock(&dev_priv->pc8.lock);
6525}
6526
6527static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6528{
6529 if (!dev_priv->pc8.gpu_idle) {
6530 dev_priv->pc8.gpu_idle = true;
6531 hsw_enable_package_c8(dev_priv);
6532 }
6533}
6534
6535static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6536{
6537 if (dev_priv->pc8.gpu_idle) {
6538 dev_priv->pc8.gpu_idle = false;
6539 hsw_disable_package_c8(dev_priv);
6540 }
be256dc7
PZ		 6541}
6542
d6dd9eb1
DV		 6543static void haswell_modeset_global_resources(struct drm_device *dev)
6544{
d6dd9eb1
DV		 6545 bool enable = false;
6546 struct intel_crtc *crtc;
d6dd9eb1
DV		 6547
6548 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6549 if (!crtc->base.enabled)
6550 continue;
d6dd9eb1 6551
fd4daa9c 6552 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
e7a639c4 6553 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6554 enable = true;
6555 }
6556
d6dd9eb1 6557 intel_set_power_well(dev, enable);
c67a470b
PZ		 6558
6559 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6560}
6561
09b4ddf9 6562static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6563 int x, int y,
6564 struct drm_framebuffer *fb)
6565{
6566 struct drm_device *dev = crtc->dev;
6567 struct drm_i915_private *dev_priv = dev->dev_private;
6568 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6569 int plane = intel_crtc->plane;
09b4ddf9 6570 int ret;
09b4ddf9 6571
ff9a6750 6572 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6573 return -EINVAL;
6574
03afc4a2
DV		 6575 if (intel_crtc->config.has_dp_encoder)
6576 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6577
6578 intel_crtc->lowfreq_avail = false;
09b4ddf9 6579
8a654f3b 6580 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6581
ca3a0ff8 6582 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6583 intel_cpu_transcoder_set_m_n(intel_crtc,
6584 &intel_crtc->config.fdi_m_n);
6585 }
09b4ddf9 6586
6ff93609 6587 haswell_set_pipeconf(crtc);
09b4ddf9 6588
50f3b016 6589 intel_set_pipe_csc(crtc);
86d3efce 6590
09b4ddf9 6591 /* Set up the display plane register */
86d3efce 6592 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6593 POSTING_READ(DSPCNTR(plane));
6594
6595 ret = intel_pipe_set_base(crtc, x, y, fb);
6596
1f803ee5 6597 return ret;
79e53945
JB		 6598}
6599
0e8ffe1b
DV		 6600static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6601 struct intel_crtc_config *pipe_config)
6602{
6603 struct drm_device *dev = crtc->base.dev;
6604 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6605 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6606 uint32_t tmp;
6607
e143a21c 6608 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6609 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6610
eccb140b
DV		 6611 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6612 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6613 enum pipe trans_edp_pipe;
6614 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6615 default:
6616 WARN(1, "unknown pipe linked to edp transcoder\n");
6617 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6618 case TRANS_DDI_EDP_INPUT_A_ON:
6619 trans_edp_pipe = PIPE_A;
6620 break;
6621 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6622 trans_edp_pipe = PIPE_B;
6623 break;
6624 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6625 trans_edp_pipe = PIPE_C;
6626 break;
6627 }
6628
6629 if (trans_edp_pipe == crtc->pipe)
6630 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6631 }
6632
b97186f0 6633 if (!intel_display_power_enabled(dev,
eccb140b 6634 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6635 return false;
6636
eccb140b 6637 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6638 if (!(tmp & PIPECONF_ENABLE))
6639 return false;
6640
88adfff1 6641 /*
f196e6be 6642 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6643 * DDI E. So just check whether this pipe is wired to DDI E and whether
6644 * the PCH transcoder is on.
6645 */
eccb140b 6646 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6647 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6648 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6649 pipe_config->has_pch_encoder = true;
6650
627eb5a3
DV		 6651 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6652 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6653 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6654
6655 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6656 }
6657
1bd1bd80
DV		 6658 intel_get_pipe_timings(crtc, pipe_config);
6659
2fa2fe9a
DV		 6660 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6661 if (intel_display_power_enabled(dev, pfit_domain))
6662 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6663
42db64ef
PZ		 6664 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6665 (I915_READ(IPS_CTL) & IPS_ENABLE);
6666
6c49f241
DV		 6667 pipe_config->pixel_multiplier = 1;
6668
0e8ffe1b
DV		 6669 return true;
6670}
6671
f564048e 6672static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6673 int x, int y,
94352cf9 6674 struct drm_framebuffer *fb)
f564048e
EA		 6675{
6676 struct drm_device *dev = crtc->dev;
6677 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6678 struct intel_encoder *encoder;
0b701d27 6679 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6680 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6681 int pipe = intel_crtc->pipe;
f564048e
EA		 6682 int ret;
6683
0b701d27 6684 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6685
b8cecdf5
DV		 6686 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6687
79e53945 6688 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6689
9256aa19
DV		 6690 if (ret != 0)
6691 return ret;
6692
6693 for_each_encoder_on_crtc(dev, crtc, encoder) {
6694 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6695 encoder->base.base.id,
6696 drm_get_encoder_name(&encoder->base),
6697 mode->base.id, mode->name);
36f2d1f1 6698 encoder->mode_set(encoder);
9256aa19
DV		 6699 }
6700
6701 return 0;
79e53945
JB		 6702}
6703
3a9627f4
WF		 6704static bool intel_eld_uptodate(struct drm_connector *connector,
6705 int reg_eldv, uint32_t bits_eldv,
6706 int reg_elda, uint32_t bits_elda,
6707 int reg_edid)
6708{
6709 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6710 uint8_t *eld = connector->eld;
6711 uint32_t i;
6712
6713 i = I915_READ(reg_eldv);
6714 i &= bits_eldv;
6715
6716 if (!eld[0])
6717 return !i;
6718
6719 if (!i)
6720 return false;
6721
6722 i = I915_READ(reg_elda);
6723 i &= ~bits_elda;
6724 I915_WRITE(reg_elda, i);
6725
6726 for (i = 0; i < eld[2]; i++)
6727 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6728 return false;
6729
6730 return true;
6731}
6732
e0dac65e
WF		 6733static void g4x_write_eld(struct drm_connector *connector,
6734 struct drm_crtc *crtc)
6735{
6736 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6737 uint8_t *eld = connector->eld;
6738 uint32_t eldv;
6739 uint32_t len;
6740 uint32_t i;
6741
6742 i = I915_READ(G4X_AUD_VID_DID);
6743
6744 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6745 eldv = G4X_ELDV_DEVCL_DEVBLC;
6746 else
6747 eldv = G4X_ELDV_DEVCTG;
6748
3a9627f4
WF		 6749 if (intel_eld_uptodate(connector,
6750 G4X_AUD_CNTL_ST, eldv,
6751 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6752 G4X_HDMIW_HDMIEDID))
6753 return;
6754
e0dac65e
WF		 6755 i = I915_READ(G4X_AUD_CNTL_ST);
6756 i &= ~(eldv | G4X_ELD_ADDR);
6757 len = (i >> 9) & 0x1f; /* ELD buffer size */
6758 I915_WRITE(G4X_AUD_CNTL_ST, i);
6759
6760 if (!eld[0])
6761 return;
6762
6763 len = min_t(uint8_t, eld[2], len);
6764 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6765 for (i = 0; i < len; i++)
6766 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6767
6768 i = I915_READ(G4X_AUD_CNTL_ST);
6769 i |= eldv;
6770 I915_WRITE(G4X_AUD_CNTL_ST, i);
6771}
6772
83358c85
WX		 6773static void haswell_write_eld(struct drm_connector *connector,
6774 struct drm_crtc *crtc)
6775{
6776 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6777 uint8_t *eld = connector->eld;
6778 struct drm_device *dev = crtc->dev;
7b9f35a6 6779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6780 uint32_t eldv;
6781 uint32_t i;
6782 int len;
6783 int pipe = to_intel_crtc(crtc)->pipe;
6784 int tmp;
6785
6786 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6787 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6788 int aud_config = HSW_AUD_CFG(pipe);
6789 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6790
6791
6792 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6793
6794 /* Audio output enable */
6795 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6796 tmp = I915_READ(aud_cntrl_st2);
6797 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6798 I915_WRITE(aud_cntrl_st2, tmp);
6799
6800 /* Wait for 1 vertical blank */
6801 intel_wait_for_vblank(dev, pipe);
6802
6803 /* Set ELD valid state */
6804 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6805 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
83358c85
WX		 6806 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6807 I915_WRITE(aud_cntrl_st2, tmp);
6808 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6809 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
83358c85
WX		 6810
6811 /* Enable HDMI mode */
6812 tmp = I915_READ(aud_config);
7e7cb34f 6813 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
83358c85
WX		 6814 /* clear N_programing_enable and N_value_index */
6815 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6816 I915_WRITE(aud_config, tmp);
6817
6818 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6819
6820 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6821 intel_crtc->eld_vld = true;
83358c85
WX		 6822
6823 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6824 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6825 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6826 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6827 } else
6828 I915_WRITE(aud_config, 0);
6829
6830 if (intel_eld_uptodate(connector,
6831 aud_cntrl_st2, eldv,
6832 aud_cntl_st, IBX_ELD_ADDRESS,
6833 hdmiw_hdmiedid))
6834 return;
6835
6836 i = I915_READ(aud_cntrl_st2);
6837 i &= ~eldv;
6838 I915_WRITE(aud_cntrl_st2, i);
6839
6840 if (!eld[0])
6841 return;
6842
6843 i = I915_READ(aud_cntl_st);
6844 i &= ~IBX_ELD_ADDRESS;
6845 I915_WRITE(aud_cntl_st, i);
6846 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6847 DRM_DEBUG_DRIVER("port num:%d\n", i);
6848
6849 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6850 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6851 for (i = 0; i < len; i++)
6852 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6853
6854 i = I915_READ(aud_cntrl_st2);
6855 i |= eldv;
6856 I915_WRITE(aud_cntrl_st2, i);
6857
6858}
6859
e0dac65e
WF		 6860static void ironlake_write_eld(struct drm_connector *connector,
6861 struct drm_crtc *crtc)
6862{
6863 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6864 uint8_t *eld = connector->eld;
6865 uint32_t eldv;
6866 uint32_t i;
6867 int len;
6868 int hdmiw_hdmiedid;
b6daa025 6869 int aud_config;
e0dac65e
WF		 6870 int aud_cntl_st;
6871 int aud_cntrl_st2;
9b138a83 6872 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6873
b3f33cbf 6874 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6875 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6876 aud_config = IBX_AUD_CFG(pipe);
6877 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6878 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6879 } else {
9b138a83
WX		 6880 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6881 aud_config = CPT_AUD_CFG(pipe);
6882 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6883 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6884 }
6885
9b138a83 6886 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6887
6888 i = I915_READ(aud_cntl_st);
9b138a83 6889 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6890 if (!i) {
6891 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6892 /* operate blindly on all ports */
1202b4c6
WF		 6893 eldv = IBX_ELD_VALIDB;
6894 eldv |= IBX_ELD_VALIDB << 4;
6895 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6896 } else {
2582a850 6897 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6898 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6899 }
6900
3a9627f4
WF		 6901 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6902 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6903 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6904 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6905 } else
6906 I915_WRITE(aud_config, 0);
e0dac65e 6907
3a9627f4
WF		 6908 if (intel_eld_uptodate(connector,
6909 aud_cntrl_st2, eldv,
6910 aud_cntl_st, IBX_ELD_ADDRESS,
6911 hdmiw_hdmiedid))
6912 return;
6913
e0dac65e
WF		 6914 i = I915_READ(aud_cntrl_st2);
6915 i &= ~eldv;
6916 I915_WRITE(aud_cntrl_st2, i);
6917
6918 if (!eld[0])
6919 return;
6920
e0dac65e 6921 i = I915_READ(aud_cntl_st);
1202b4c6 6922 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6923 I915_WRITE(aud_cntl_st, i);
6924
6925 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6926 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6927 for (i = 0; i < len; i++)
6928 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6929
6930 i = I915_READ(aud_cntrl_st2);
6931 i |= eldv;
6932 I915_WRITE(aud_cntrl_st2, i);
6933}
6934
6935void intel_write_eld(struct drm_encoder *encoder,
6936 struct drm_display_mode *mode)
6937{
6938 struct drm_crtc *crtc = encoder->crtc;
6939 struct drm_connector *connector;
6940 struct drm_device *dev = encoder->dev;
6941 struct drm_i915_private *dev_priv = dev->dev_private;
6942
6943 connector = drm_select_eld(encoder, mode);
6944 if (!connector)
6945 return;
6946
6947 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6948 connector->base.id,
6949 drm_get_connector_name(connector),
6950 connector->encoder->base.id,
6951 drm_get_encoder_name(connector->encoder));
6952
6953 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6954
6955 if (dev_priv->display.write_eld)
6956 dev_priv->display.write_eld(connector, crtc);
6957}
6958
560b85bb
CW		 6959static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6960{
6961 struct drm_device *dev = crtc->dev;
6962 struct drm_i915_private *dev_priv = dev->dev_private;
6963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6964 bool visible = base != 0;
6965 u32 cntl;
6966
6967 if (intel_crtc->cursor_visible == visible)
6968 return;
6969
9db4a9c7 6970 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6971 if (visible) {
6972 /* On these chipsets we can only modify the base whilst
6973 * the cursor is disabled.
6974 */
9db4a9c7 6975 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6976
6977 cntl &= ~(CURSOR_FORMAT_MASK);
6978 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6979 cntl |= CURSOR_ENABLE |
6980 CURSOR_GAMMA_ENABLE |
6981 CURSOR_FORMAT_ARGB;
6982 } else
6983 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6984 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6985
6986 intel_crtc->cursor_visible = visible;
6987}
6988
6989static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6990{
6991 struct drm_device *dev = crtc->dev;
6992 struct drm_i915_private *dev_priv = dev->dev_private;
6993 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6994 int pipe = intel_crtc->pipe;
6995 bool visible = base != 0;
6996
6997 if (intel_crtc->cursor_visible != visible) {
548f245b 6998 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6999 if (base) {
7000 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7001 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7002 cntl |= pipe << 28; /* Connect to correct pipe */
7003 } else {
7004 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7005 cntl |= CURSOR_MODE_DISABLE;
7006 }
9db4a9c7 7007 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 7008
7009 intel_crtc->cursor_visible = visible;
7010 }
7011 /* and commit changes on next vblank */
9db4a9c7 7012 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 7013}
7014
65a21cd6
JB		 7015static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7016{
7017 struct drm_device *dev = crtc->dev;
7018 struct drm_i915_private *dev_priv = dev->dev_private;
7019 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7020 int pipe = intel_crtc->pipe;
7021 bool visible = base != 0;
7022
7023 if (intel_crtc->cursor_visible != visible) {
7024 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7025 if (base) {
7026 cntl &= ~CURSOR_MODE;
7027 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7028 } else {
7029 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7030 cntl |= CURSOR_MODE_DISABLE;
7031 }
1f5d76db 7032 if (IS_HASWELL(dev)) {
86d3efce 7033 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 7034 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7035 }
65a21cd6
JB		 7036 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7037
7038 intel_crtc->cursor_visible = visible;
7039 }
7040 /* and commit changes on next vblank */
7041 I915_WRITE(CURBASE_IVB(pipe), base);
7042}
7043
cda4b7d3 7044/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 7045static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7046 bool on)
cda4b7d3
CW		 7047{
7048 struct drm_device *dev = crtc->dev;
7049 struct drm_i915_private *dev_priv = dev->dev_private;
7050 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7051 int pipe = intel_crtc->pipe;
7052 int x = intel_crtc->cursor_x;
7053 int y = intel_crtc->cursor_y;
d6e4db15 7054 u32 base = 0, pos = 0;
cda4b7d3
CW		 7055 bool visible;
7056
d6e4db15 7057 if (on)
cda4b7d3 7058 base = intel_crtc->cursor_addr;
cda4b7d3 7059
d6e4db15
VS		 7060 if (x >= intel_crtc->config.pipe_src_w)
7061 base = 0;
7062
7063 if (y >= intel_crtc->config.pipe_src_h)
cda4b7d3
CW		 7064 base = 0;
7065
7066 if (x < 0) {
efc9064e 7067 if (x + intel_crtc->cursor_width <= 0)
cda4b7d3
CW		 7068 base = 0;
7069
7070 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7071 x = -x;
7072 }
7073 pos |= x << CURSOR_X_SHIFT;
7074
7075 if (y < 0) {
efc9064e 7076 if (y + intel_crtc->cursor_height <= 0)
cda4b7d3
CW		 7077 base = 0;
7078
7079 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7080 y = -y;
7081 }
7082 pos |= y << CURSOR_Y_SHIFT;
7083
7084 visible = base != 0;
560b85bb 7085 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 7086 return;
7087
0cd83aa9 7088 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 7089 I915_WRITE(CURPOS_IVB(pipe), pos);
7090 ivb_update_cursor(crtc, base);
7091 } else {
7092 I915_WRITE(CURPOS(pipe), pos);
7093 if (IS_845G(dev) || IS_I865G(dev))
7094 i845_update_cursor(crtc, base);
7095 else
7096 i9xx_update_cursor(crtc, base);
7097 }
cda4b7d3
CW		 7098}
7099
79e53945 7100static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 7101 struct drm_file *file,
79e53945
JB		 7102 uint32_t handle,
7103 uint32_t width, uint32_t height)
7104{
7105 struct drm_device *dev = crtc->dev;
7106 struct drm_i915_private *dev_priv = dev->dev_private;
7107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 7108 struct drm_i915_gem_object *obj;
cda4b7d3 7109 uint32_t addr;
3f8bc370 7110 int ret;
79e53945 7111
79e53945
JB		 7112 /* if we want to turn off the cursor ignore width and height */
7113 if (!handle) {
28c97730 7114 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 7115 addr = 0;
05394f39 7116 obj = NULL;
5004417d 7117 mutex_lock(&dev->struct_mutex);
3f8bc370 7118 goto finish;
79e53945
JB		 7119 }
7120
7121 /* Currently we only support 64x64 cursors */
7122 if (width != 64 || height != 64) {
7123 DRM_ERROR("we currently only support 64x64 cursors\n");
7124 return -EINVAL;
7125 }
7126
05394f39 7127 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 7128 if (&obj->base == NULL)
79e53945
JB		 7129 return -ENOENT;
7130
05394f39 7131 if (obj->base.size < width * height * 4) {
79e53945 7132 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 7133 ret = -ENOMEM;
7134 goto fail;
79e53945
JB		 7135 }
7136
71acb5eb 7137 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 7138 mutex_lock(&dev->struct_mutex);
b295d1b6 7139 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 7140 unsigned alignment;
7141
d9e86c0e
CW		 7142 if (obj->tiling_mode) {
7143 DRM_ERROR("cursor cannot be tiled\n");
7144 ret = -EINVAL;
7145 goto fail_locked;
7146 }
7147
693db184
CW		 7148 /* Note that the w/a also requires 2 PTE of padding following
7149 * the bo. We currently fill all unused PTE with the shadow
7150 * page and so we should always have valid PTE following the
7151 * cursor preventing the VT-d warning.
7152 */
7153 alignment = 0;
7154 if (need_vtd_wa(dev))
7155 alignment = 64*1024;
7156
7157 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 7158 if (ret) {
7159 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 7160 goto fail_locked;
e7b526bb
CW		 7161 }
7162
d9e86c0e
CW		 7163 ret = i915_gem_object_put_fence(obj);
7164 if (ret) {
2da3b9b9 7165 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 7166 goto fail_unpin;
7167 }
7168
f343c5f6 7169 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 7170 } else {
6eeefaf3 7171 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 7172 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 7173 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7174 align);
71acb5eb
DA		 7175 if (ret) {
7176 DRM_ERROR("failed to attach phys object\n");
7f9872e0 7177 goto fail_locked;
71acb5eb 7178 }
05394f39 7179 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 7180 }
7181
a6c45cf0 7182 if (IS_GEN2(dev))
14b60391
JB		 7183 I915_WRITE(CURSIZE, (height << 12) | width);
7184
3f8bc370 7185 finish:
3f8bc370 7186 if (intel_crtc->cursor_bo) {
b295d1b6 7187 if (dev_priv->info->cursor_needs_physical) {
05394f39 7188 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 7189 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7190 } else
cc98b413 7191 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 7192 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 7193 }
80824003 7194
7f9872e0 7195 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 7196
7197 intel_crtc->cursor_addr = addr;
05394f39 7198 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 7199 intel_crtc->cursor_width = width;
7200 intel_crtc->cursor_height = height;
7201
f2f5f771
VS		 7202 if (intel_crtc->active)
7203 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 7204
79e53945 7205 return 0;
e7b526bb 7206fail_unpin:
cc98b413 7207 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 7208fail_locked:
34b8686e 7209 mutex_unlock(&dev->struct_mutex);
bc9025bd 7210fail:
05394f39 7211 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 7212 return ret;
79e53945
JB		 7213}
7214
7215static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7216{
79e53945 7217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7218
cda4b7d3
CW		 7219 intel_crtc->cursor_x = x;
7220 intel_crtc->cursor_y = y;
652c393a 7221
f2f5f771
VS		 7222 if (intel_crtc->active)
7223 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 7224
7225 return 0;
b8c00ac5
DA		 7226}
7227
79e53945 7228static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7229 u16 *blue, uint32_t start, uint32_t size)
79e53945 7230{
7203425a 7231 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7233
7203425a 7234 for (i = start; i < end; i++) {
79e53945
JB		 7235 intel_crtc->lut_r[i] = red[i] >> 8;
7236 intel_crtc->lut_g[i] = green[i] >> 8;
7237 intel_crtc->lut_b[i] = blue[i] >> 8;
7238 }
7239
7240 intel_crtc_load_lut(crtc);
7241}
7242
79e53945
JB		 7243/* VESA 640x480x72Hz mode to set on the pipe */
7244static struct drm_display_mode load_detect_mode = {
7245 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7246 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7247};
7248
d2dff872
CW		 7249static struct drm_framebuffer *
7250intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7251 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7252 struct drm_i915_gem_object *obj)
7253{
7254 struct intel_framebuffer *intel_fb;
7255 int ret;
7256
7257 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7258 if (!intel_fb) {
7259 drm_gem_object_unreference_unlocked(&obj->base);
7260 return ERR_PTR(-ENOMEM);
7261 }
7262
7263 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7264 if (ret) {
7265 drm_gem_object_unreference_unlocked(&obj->base);
7266 kfree(intel_fb);
7267 return ERR_PTR(ret);
7268 }
7269
7270 return &intel_fb->base;
7271}
7272
7273static u32
7274intel_framebuffer_pitch_for_width(int width, int bpp)
7275{
7276 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7277 return ALIGN(pitch, 64);
7278}
7279
7280static u32
7281intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7282{
7283 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7284 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7285}
7286
7287static struct drm_framebuffer *
7288intel_framebuffer_create_for_mode(struct drm_device *dev,
7289 struct drm_display_mode *mode,
7290 int depth, int bpp)
7291{
7292 struct drm_i915_gem_object *obj;
0fed39bd 7293 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7294
7295 obj = i915_gem_alloc_object(dev,
7296 intel_framebuffer_size_for_mode(mode, bpp));
7297 if (obj == NULL)
7298 return ERR_PTR(-ENOMEM);
7299
7300 mode_cmd.width = mode->hdisplay;
7301 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7302 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7303 bpp);
5ca0c34a 7304 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7305
7306 return intel_framebuffer_create(dev, &mode_cmd, obj);
7307}
7308
7309static struct drm_framebuffer *
7310mode_fits_in_fbdev(struct drm_device *dev,
7311 struct drm_display_mode *mode)
7312{
7313 struct drm_i915_private *dev_priv = dev->dev_private;
7314 struct drm_i915_gem_object *obj;
7315 struct drm_framebuffer *fb;
7316
7317 if (dev_priv->fbdev == NULL)
7318 return NULL;
7319
7320 obj = dev_priv->fbdev->ifb.obj;
7321 if (obj == NULL)
7322 return NULL;
7323
7324 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7325 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7326 fb->bits_per_pixel))
d2dff872
CW		 7327 return NULL;
7328
01f2c773 7329 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7330 return NULL;
7331
7332 return fb;
7333}
7334
d2434ab7 7335bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7336 struct drm_display_mode *mode,
8261b191 7337 struct intel_load_detect_pipe *old)
79e53945
JB		 7338{
7339 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7340 struct intel_encoder *intel_encoder =
7341 intel_attached_encoder(connector);
79e53945 7342 struct drm_crtc *possible_crtc;
4ef69c7a 7343 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7344 struct drm_crtc *crtc = NULL;
7345 struct drm_device *dev = encoder->dev;
94352cf9 7346 struct drm_framebuffer *fb;
79e53945
JB		 7347 int i = -1;
7348
d2dff872
CW		 7349 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7350 connector->base.id, drm_get_connector_name(connector),
7351 encoder->base.id, drm_get_encoder_name(encoder));
7352
79e53945
JB		 7353 /*
7354 * Algorithm gets a little messy:
7a5e4805 7355 *
79e53945
JB		 7356 * - if the connector already has an assigned crtc, use it (but make
7357 * sure it's on first)
7a5e4805 7358 *
79e53945
JB		 7359 * - try to find the first unused crtc that can drive this connector,
7360 * and use that if we find one
79e53945
JB		 7361 */
7362
7363 /* See if we already have a CRTC for this connector */
7364 if (encoder->crtc) {
7365 crtc = encoder->crtc;
8261b191 7366
7b24056b
DV		 7367 mutex_lock(&crtc->mutex);
7368
24218aac 7369 old->dpms_mode = connector->dpms;
8261b191
CW		 7370 old->load_detect_temp = false;
7371
7372 /* Make sure the crtc and connector are running */
24218aac
DV		 7373 if (connector->dpms != DRM_MODE_DPMS_ON)
7374 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7375
7173188d 7376 return true;
79e53945
JB		 7377 }
7378
7379 /* Find an unused one (if possible) */
7380 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7381 i++;
7382 if (!(encoder->possible_crtcs & (1 << i)))
7383 continue;
7384 if (!possible_crtc->enabled) {
7385 crtc = possible_crtc;
7386 break;
7387 }
79e53945
JB		 7388 }
7389
7390 /*
7391 * If we didn't find an unused CRTC, don't use any.
7392 */
7393 if (!crtc) {
7173188d
CW		 7394 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7395 return false;
79e53945
JB		 7396 }
7397
7b24056b 7398 mutex_lock(&crtc->mutex);
fc303101
DV		 7399 intel_encoder->new_crtc = to_intel_crtc(crtc);
7400 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7401
7402 intel_crtc = to_intel_crtc(crtc);
24218aac 7403 old->dpms_mode = connector->dpms;
8261b191 7404 old->load_detect_temp = true;
d2dff872 7405 old->release_fb = NULL;
79e53945 7406
6492711d
CW		 7407 if (!mode)
7408 mode = &load_detect_mode;
79e53945 7409
d2dff872
CW		 7410 /* We need a framebuffer large enough to accommodate all accesses
7411 * that the plane may generate whilst we perform load detection.
7412 * We can not rely on the fbcon either being present (we get called
7413 * during its initialisation to detect all boot displays, or it may
7414 * not even exist) or that it is large enough to satisfy the
7415 * requested mode.
7416 */
94352cf9
DV		 7417 fb = mode_fits_in_fbdev(dev, mode);
7418 if (fb == NULL) {
d2dff872 7419 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7420 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7421 old->release_fb = fb;
d2dff872
CW		 7422 } else
7423 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7424 if (IS_ERR(fb)) {
d2dff872 7425 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7426 mutex_unlock(&crtc->mutex);
0e8b3d3e 7427 return false;
79e53945 7428 }
79e53945 7429
c0c36b94 7430 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7431 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7432 if (old->release_fb)
7433 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7434 mutex_unlock(&crtc->mutex);
0e8b3d3e 7435 return false;
79e53945 7436 }
7173188d 7437
79e53945 7438 /* let the connector get through one full cycle before testing */
9d0498a2 7439 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7440 return true;
79e53945
JB		 7441}
7442
d2434ab7 7443void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7444 struct intel_load_detect_pipe *old)
79e53945 7445{
d2434ab7
DV		 7446 struct intel_encoder *intel_encoder =
7447 intel_attached_encoder(connector);
4ef69c7a 7448 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7449 struct drm_crtc *crtc = encoder->crtc;
79e53945 7450
d2dff872
CW		 7451 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7452 connector->base.id, drm_get_connector_name(connector),
7453 encoder->base.id, drm_get_encoder_name(encoder));
7454
8261b191 7455 if (old->load_detect_temp) {
fc303101
DV		 7456 to_intel_connector(connector)->new_encoder = NULL;
7457 intel_encoder->new_crtc = NULL;
7458 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7459
36206361
DV		 7460 if (old->release_fb) {
7461 drm_framebuffer_unregister_private(old->release_fb);
7462 drm_framebuffer_unreference(old->release_fb);
7463 }
d2dff872 7464
67c96400 7465 mutex_unlock(&crtc->mutex);
0622a53c 7466 return;
79e53945
JB		 7467 }
7468
c751ce4f 7469 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7470 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7471 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7472
7473 mutex_unlock(&crtc->mutex);
79e53945
JB		 7474}
7475
da4a1efa
VS		 7476static int i9xx_pll_refclk(struct drm_device *dev,
7477 const struct intel_crtc_config *pipe_config)
7478{
7479 struct drm_i915_private *dev_priv = dev->dev_private;
7480 u32 dpll = pipe_config->dpll_hw_state.dpll;
7481
7482 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7483 return dev_priv->vbt.lvds_ssc_freq * 1000;
7484 else if (HAS_PCH_SPLIT(dev))
7485 return 120000;
7486 else if (!IS_GEN2(dev))
7487 return 96000;
7488 else
7489 return 48000;
7490}
7491
79e53945 7492/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7493static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7494 struct intel_crtc_config *pipe_config)
79e53945 7495{
f1f644dc 7496 struct drm_device *dev = crtc->base.dev;
79e53945 7497 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7498 int pipe = pipe_config->cpu_transcoder;
293623f7 7499 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 7500 u32 fp;
7501 intel_clock_t clock;
da4a1efa 7502 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 7503
7504 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 7505 fp = pipe_config->dpll_hw_state.fp0;
79e53945 7506 else
293623f7 7507 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 7508
7509 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7510 if (IS_PINEVIEW(dev)) {
7511 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7512 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7513 } else {
7514 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7515 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7516 }
7517
a6c45cf0 7518 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7519 if (IS_PINEVIEW(dev))
7520 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7521 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7522 else
7523 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7524 DPLL_FPA01_P1_POST_DIV_SHIFT);
7525
7526 switch (dpll & DPLL_MODE_MASK) {
7527 case DPLLB_MODE_DAC_SERIAL:
7528 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7529 5 : 10;
7530 break;
7531 case DPLLB_MODE_LVDS:
7532 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7533 7 : 14;
7534 break;
7535 default:
28c97730 7536 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7537 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 7538 return;
79e53945
JB		 7539 }
7540
ac58c3f0 7541 if (IS_PINEVIEW(dev))
da4a1efa 7542 pineview_clock(refclk, &clock);
ac58c3f0 7543 else
da4a1efa 7544 i9xx_clock(refclk, &clock);
79e53945
JB		 7545 } else {
7546 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7547
7548 if (is_lvds) {
7549 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7550 DPLL_FPA01_P1_POST_DIV_SHIFT);
7551 clock.p2 = 14;
79e53945
JB		 7552 } else {
7553 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7554 clock.p1 = 2;
7555 else {
7556 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7557 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7558 }
7559 if (dpll & PLL_P2_DIVIDE_BY_4)
7560 clock.p2 = 4;
7561 else
7562 clock.p2 = 2;
79e53945 7563 }
da4a1efa
VS		 7564
7565 i9xx_clock(refclk, &clock);
79e53945
JB		 7566 }
7567
18442d08
VS		 7568 /*
7569 * This value includes pixel_multiplier. We will use
241bfc38 7570 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 7571 * encoder's get_config() function.
7572 */
7573 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 7574}
7575
6878da05
VS		 7576int intel_dotclock_calculate(int link_freq,
7577 const struct intel_link_m_n *m_n)
f1f644dc 7578{
f1f644dc
JB		 7579 /*
7580 * The calculation for the data clock is:
1041a02f 7581 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 7582 * But we want to avoid losing precison if possible, so:
1041a02f 7583 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 7584 *
7585 * and the link clock is simpler:
1041a02f 7586 * link_clock = (m * link_clock) / n
f1f644dc
JB		 7587 */
7588
6878da05
VS		 7589 if (!m_n->link_n)
7590 return 0;
f1f644dc 7591
6878da05
VS		 7592 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7593}
f1f644dc 7594
18442d08
VS		 7595static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7596 struct intel_crtc_config *pipe_config)
6878da05
VS		 7597{
7598 struct drm_device *dev = crtc->base.dev;
79e53945 7599
18442d08
VS		 7600 /* read out port_clock from the DPLL */
7601 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 7602
f1f644dc 7603 /*
18442d08 7604 * This value does not include pixel_multiplier.
241bfc38 7605 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 7606 * agree once we know their relationship in the encoder's
7607 * get_config() function.
79e53945 7608 */
241bfc38 7609 pipe_config->adjusted_mode.crtc_clock =
18442d08
VS		 7610 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7611 &pipe_config->fdi_m_n);
79e53945
JB		 7612}
7613
7614/** Returns the currently programmed mode of the given pipe. */
7615struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7616 struct drm_crtc *crtc)
7617{
548f245b 7618 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7619 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7620 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7621 struct drm_display_mode *mode;
f1f644dc 7622 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7623 int htot = I915_READ(HTOTAL(cpu_transcoder));
7624 int hsync = I915_READ(HSYNC(cpu_transcoder));
7625 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7626 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 7627 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 7628
7629 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7630 if (!mode)
7631 return NULL;
7632
f1f644dc
JB		 7633 /*
7634 * Construct a pipe_config sufficient for getting the clock info
7635 * back out of crtc_clock_get.
7636 *
7637 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7638 * to use a real value here instead.
7639 */
293623f7 7640 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 7641 pipe_config.pixel_multiplier = 1;
293623f7
VS		 7642 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7643 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7644 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 7645 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7646
773ae034 7647 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 7648 mode->hdisplay = (htot & 0xffff) + 1;
7649 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7650 mode->hsync_start = (hsync & 0xffff) + 1;
7651 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7652 mode->vdisplay = (vtot & 0xffff) + 1;
7653 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7654 mode->vsync_start = (vsync & 0xffff) + 1;
7655 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7656
7657 drm_mode_set_name(mode);
79e53945
JB		 7658
7659 return mode;
7660}
7661
3dec0095 7662static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7663{
7664 struct drm_device *dev = crtc->dev;
7665 drm_i915_private_t *dev_priv = dev->dev_private;
7666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7667 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7668 int dpll_reg = DPLL(pipe);
7669 int dpll;
652c393a 7670
bad720ff 7671 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7672 return;
7673
7674 if (!dev_priv->lvds_downclock_avail)
7675 return;
7676
dbdc6479 7677 dpll = I915_READ(dpll_reg);
652c393a 7678 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7679 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7680
8ac5a6d5 7681 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7682
7683 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7684 I915_WRITE(dpll_reg, dpll);
9d0498a2 7685 intel_wait_for_vblank(dev, pipe);
dbdc6479 7686
652c393a
JB		 7687 dpll = I915_READ(dpll_reg);
7688 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7689 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7690 }
652c393a
JB		 7691}
7692
7693static void intel_decrease_pllclock(struct drm_crtc *crtc)
7694{
7695 struct drm_device *dev = crtc->dev;
7696 drm_i915_private_t *dev_priv = dev->dev_private;
7697 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7698
bad720ff 7699 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7700 return;
7701
7702 if (!dev_priv->lvds_downclock_avail)
7703 return;
7704
7705 /*
7706 * Since this is called by a timer, we should never get here in
7707 * the manual case.
7708 */
7709 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7710 int pipe = intel_crtc->pipe;
7711 int dpll_reg = DPLL(pipe);
7712 int dpll;
f6e5b160 7713
44d98a61 7714 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7715
8ac5a6d5 7716 assert_panel_unlocked(dev_priv, pipe);
652c393a 7717
dc257cf1 7718 dpll = I915_READ(dpll_reg);
652c393a
JB		 7719 dpll |= DISPLAY_RATE_SELECT_FPA1;
7720 I915_WRITE(dpll_reg, dpll);
9d0498a2 7721 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7722 dpll = I915_READ(dpll_reg);
7723 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7724 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7725 }
7726
7727}
7728
f047e395
CW		 7729void intel_mark_busy(struct drm_device *dev)
7730{
c67a470b
PZ		 7731 struct drm_i915_private *dev_priv = dev->dev_private;
7732
7733 hsw_package_c8_gpu_busy(dev_priv);
7734 i915_update_gfx_val(dev_priv);
f047e395
CW		 7735}
7736
7737void intel_mark_idle(struct drm_device *dev)
652c393a 7738{
c67a470b 7739 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7740 struct drm_crtc *crtc;
652c393a 7741
c67a470b
PZ		 7742 hsw_package_c8_gpu_idle(dev_priv);
7743
652c393a
JB		 7744 if (!i915_powersave)
7745 return;
7746
652c393a 7747 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7748 if (!crtc->fb)
7749 continue;
7750
725a5b54 7751 intel_decrease_pllclock(crtc);
652c393a 7752 }
b29c19b6
CW		 7753
7754 if (dev_priv->info->gen >= 6)
7755 gen6_rps_idle(dev->dev_private);
652c393a
JB		 7756}
7757
c65355bb
CW		 7758void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7759 struct intel_ring_buffer *ring)
652c393a 7760{
f047e395
CW		 7761 struct drm_device *dev = obj->base.dev;
7762 struct drm_crtc *crtc;
652c393a 7763
f047e395 7764 if (!i915_powersave)
acb87dfb
CW		 7765 return;
7766
652c393a
JB		 7767 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7768 if (!crtc->fb)
7769 continue;
7770
c65355bb
CW		 7771 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7772 continue;
7773
7774 intel_increase_pllclock(crtc);
7775 if (ring && intel_fbc_enabled(dev))
7776 ring->fbc_dirty = true;
652c393a
JB		 7777 }
7778}
7779
79e53945
JB		 7780static void intel_crtc_destroy(struct drm_crtc *crtc)
7781{
7782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7783 struct drm_device *dev = crtc->dev;
7784 struct intel_unpin_work *work;
7785 unsigned long flags;
7786
7787 spin_lock_irqsave(&dev->event_lock, flags);
7788 work = intel_crtc->unpin_work;
7789 intel_crtc->unpin_work = NULL;
7790 spin_unlock_irqrestore(&dev->event_lock, flags);
7791
7792 if (work) {
7793 cancel_work_sync(&work->work);
7794 kfree(work);
7795 }
79e53945 7796
40ccc72b
MK		 7797 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7798
79e53945 7799 drm_crtc_cleanup(crtc);
67e77c5a 7800
79e53945
JB		 7801 kfree(intel_crtc);
7802}
7803
6b95a207
KH		 7804static void intel_unpin_work_fn(struct work_struct *__work)
7805{
7806 struct intel_unpin_work *work =
7807 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7808 struct drm_device *dev = work->crtc->dev;
6b95a207 7809
b4a98e57 7810 mutex_lock(&dev->struct_mutex);
1690e1eb 7811 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7812 drm_gem_object_unreference(&work->pending_flip_obj->base);
7813 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7814
b4a98e57
CW		 7815 intel_update_fbc(dev);
7816 mutex_unlock(&dev->struct_mutex);
7817
7818 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7819 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7820
6b95a207
KH		 7821 kfree(work);
7822}
7823
1afe3e9d 7824static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7825 struct drm_crtc *crtc)
6b95a207
KH		 7826{
7827 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7829 struct intel_unpin_work *work;
6b95a207
KH		 7830 unsigned long flags;
7831
7832 /* Ignore early vblank irqs */
7833 if (intel_crtc == NULL)
7834 return;
7835
7836 spin_lock_irqsave(&dev->event_lock, flags);
7837 work = intel_crtc->unpin_work;
e7d841ca
CW		 7838
7839 /* Ensure we don't miss a work->pending update ... */
7840 smp_rmb();
7841
7842 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7843 spin_unlock_irqrestore(&dev->event_lock, flags);
7844 return;
7845 }
7846
e7d841ca
CW		 7847 /* and that the unpin work is consistent wrt ->pending. */
7848 smp_rmb();
7849
6b95a207 7850 intel_crtc->unpin_work = NULL;
6b95a207 7851
45a066eb
RC		 7852 if (work->event)
7853 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7854
0af7e4df
MK		 7855 drm_vblank_put(dev, intel_crtc->pipe);
7856
6b95a207
KH		 7857 spin_unlock_irqrestore(&dev->event_lock, flags);
7858
2c10d571 7859 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7860
7861 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7862
7863 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7864}
7865
1afe3e9d
JB		 7866void intel_finish_page_flip(struct drm_device *dev, int pipe)
7867{
7868 drm_i915_private_t *dev_priv = dev->dev_private;
7869 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7870
49b14a5c 7871 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7872}
7873
7874void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7875{
7876 drm_i915_private_t *dev_priv = dev->dev_private;
7877 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7878
49b14a5c 7879 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7880}
7881
6b95a207
KH		 7882void intel_prepare_page_flip(struct drm_device *dev, int plane)
7883{
7884 drm_i915_private_t *dev_priv = dev->dev_private;
7885 struct intel_crtc *intel_crtc =
7886 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7887 unsigned long flags;
7888
e7d841ca
CW		 7889 /* NB: An MMIO update of the plane base pointer will also
7890 * generate a page-flip completion irq, i.e. every modeset
7891 * is also accompanied by a spurious intel_prepare_page_flip().
7892 */
6b95a207 7893 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7894 if (intel_crtc->unpin_work)
7895 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7896 spin_unlock_irqrestore(&dev->event_lock, flags);
7897}
7898
e7d841ca
CW		 7899inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7900{
7901 /* Ensure that the work item is consistent when activating it ... */
7902 smp_wmb();
7903 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7904 /* and that it is marked active as soon as the irq could fire. */
7905 smp_wmb();
7906}
7907
8c9f3aaf
JB		 7908static int intel_gen2_queue_flip(struct drm_device *dev,
7909 struct drm_crtc *crtc,
7910 struct drm_framebuffer *fb,
ed8d1975
KP		 7911 struct drm_i915_gem_object *obj,
7912 uint32_t flags)
8c9f3aaf
JB		 7913{
7914 struct drm_i915_private *dev_priv = dev->dev_private;
7915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7916 u32 flip_mask;
6d90c952 7917 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7918 int ret;
7919
6d90c952 7920 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7921 if (ret)
83d4092b 7922 goto err;
8c9f3aaf 7923
6d90c952 7924 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7925 if (ret)
83d4092b 7926 goto err_unpin;
8c9f3aaf
JB		 7927
7928 /* Can't queue multiple flips, so wait for the previous
7929 * one to finish before executing the next.
7930 */
7931 if (intel_crtc->plane)
7932 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7933 else
7934 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7935 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7936 intel_ring_emit(ring, MI_NOOP);
7937 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7938 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7939 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7940 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7941 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7942
7943 intel_mark_page_flip_active(intel_crtc);
09246732 7944 __intel_ring_advance(ring);
83d4092b
CW		 7945 return 0;
7946
7947err_unpin:
7948 intel_unpin_fb_obj(obj);
7949err:
8c9f3aaf
JB		 7950 return ret;
7951}
7952
7953static int intel_gen3_queue_flip(struct drm_device *dev,
7954 struct drm_crtc *crtc,
7955 struct drm_framebuffer *fb,
ed8d1975
KP		 7956 struct drm_i915_gem_object *obj,
7957 uint32_t flags)
8c9f3aaf
JB		 7958{
7959 struct drm_i915_private *dev_priv = dev->dev_private;
7960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7961 u32 flip_mask;
6d90c952 7962 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7963 int ret;
7964
6d90c952 7965 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7966 if (ret)
83d4092b 7967 goto err;
8c9f3aaf 7968
6d90c952 7969 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7970 if (ret)
83d4092b 7971 goto err_unpin;
8c9f3aaf
JB		 7972
7973 if (intel_crtc->plane)
7974 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7975 else
7976 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7977 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7978 intel_ring_emit(ring, MI_NOOP);
7979 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7980 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7981 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7982 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7983 intel_ring_emit(ring, MI_NOOP);
7984
e7d841ca 7985 intel_mark_page_flip_active(intel_crtc);
09246732 7986 __intel_ring_advance(ring);
83d4092b
CW		 7987 return 0;
7988
7989err_unpin:
7990 intel_unpin_fb_obj(obj);
7991err:
8c9f3aaf
JB		 7992 return ret;
7993}
7994
7995static int intel_gen4_queue_flip(struct drm_device *dev,
7996 struct drm_crtc *crtc,
7997 struct drm_framebuffer *fb,
ed8d1975
KP		 7998 struct drm_i915_gem_object *obj,
7999 uint32_t flags)
8c9f3aaf
JB		 8000{
8001 struct drm_i915_private *dev_priv = dev->dev_private;
8002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8003 uint32_t pf, pipesrc;
6d90c952 8004 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8005 int ret;
8006
6d90c952 8007 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8008 if (ret)
83d4092b 8009 goto err;
8c9f3aaf 8010
6d90c952 8011 ret = intel_ring_begin(ring, 4);
8c9f3aaf 8012 if (ret)
83d4092b 8013 goto err_unpin;
8c9f3aaf
JB		 8014
8015 /* i965+ uses the linear or tiled offsets from the
8016 * Display Registers (which do not change across a page-flip)
8017 * so we need only reprogram the base address.
8018 */
6d90c952
DV		 8019 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8020 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8021 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 8022 intel_ring_emit(ring,
f343c5f6 8023 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 8024 obj->tiling_mode);
8c9f3aaf
JB		 8025
8026 /* XXX Enabling the panel-fitter across page-flip is so far
8027 * untested on non-native modes, so ignore it for now.
8028 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8029 */
8030 pf = 0;
8031 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 8032 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 8033
8034 intel_mark_page_flip_active(intel_crtc);
09246732 8035 __intel_ring_advance(ring);
83d4092b
CW		 8036 return 0;
8037
8038err_unpin:
8039 intel_unpin_fb_obj(obj);
8040err:
8c9f3aaf
JB		 8041 return ret;
8042}
8043
8044static int intel_gen6_queue_flip(struct drm_device *dev,
8045 struct drm_crtc *crtc,
8046 struct drm_framebuffer *fb,
ed8d1975
KP		 8047 struct drm_i915_gem_object *obj,
8048 uint32_t flags)
8c9f3aaf
JB		 8049{
8050 struct drm_i915_private *dev_priv = dev->dev_private;
8051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 8052 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8053 uint32_t pf, pipesrc;
8054 int ret;
8055
6d90c952 8056 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8057 if (ret)
83d4092b 8058 goto err;
8c9f3aaf 8059
6d90c952 8060 ret = intel_ring_begin(ring, 4);
8c9f3aaf 8061 if (ret)
83d4092b 8062 goto err_unpin;
8c9f3aaf 8063
6d90c952
DV		 8064 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8065 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8066 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 8067 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 8068
dc257cf1
DV		 8069 /* Contrary to the suggestions in the documentation,
8070 * "Enable Panel Fitter" does not seem to be required when page
8071 * flipping with a non-native mode, and worse causes a normal
8072 * modeset to fail.
8073 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8074 */
8075 pf = 0;
8c9f3aaf 8076 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 8077 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 8078
8079 intel_mark_page_flip_active(intel_crtc);
09246732 8080 __intel_ring_advance(ring);
83d4092b
CW		 8081 return 0;
8082
8083err_unpin:
8084 intel_unpin_fb_obj(obj);
8085err:
8c9f3aaf
JB		 8086 return ret;
8087}
8088
7c9017e5
JB		 8089static int intel_gen7_queue_flip(struct drm_device *dev,
8090 struct drm_crtc *crtc,
8091 struct drm_framebuffer *fb,
ed8d1975
KP		 8092 struct drm_i915_gem_object *obj,
8093 uint32_t flags)
7c9017e5
JB		 8094{
8095 struct drm_i915_private *dev_priv = dev->dev_private;
8096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 8097 struct intel_ring_buffer *ring;
cb05d8de 8098 uint32_t plane_bit = 0;
ffe74d75
CW		 8099 int len, ret;
8100
8101 ring = obj->ring;
1c5fd085 8102 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
ffe74d75 8103 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 8104
8105 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8106 if (ret)
83d4092b 8107 goto err;
7c9017e5 8108
cb05d8de
DV		 8109 switch(intel_crtc->plane) {
8110 case PLANE_A:
8111 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8112 break;
8113 case PLANE_B:
8114 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8115 break;
8116 case PLANE_C:
8117 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8118 break;
8119 default:
8120 WARN_ONCE(1, "unknown plane in flip command\n");
8121 ret = -ENODEV;
ab3951eb 8122 goto err_unpin;
cb05d8de
DV		 8123 }
8124
ffe74d75
CW		 8125 len = 4;
8126 if (ring->id == RCS)
8127 len += 6;
8128
8129 ret = intel_ring_begin(ring, len);
7c9017e5 8130 if (ret)
83d4092b 8131 goto err_unpin;
7c9017e5 8132
ffe74d75
CW		 8133 /* Unmask the flip-done completion message. Note that the bspec says that
8134 * we should do this for both the BCS and RCS, and that we must not unmask
8135 * more than one flip event at any time (or ensure that one flip message
8136 * can be sent by waiting for flip-done prior to queueing new flips).
8137 * Experimentation says that BCS works despite DERRMR masking all
8138 * flip-done completion events and that unmasking all planes at once
8139 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8140 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8141 */
8142 if (ring->id == RCS) {
8143 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8144 intel_ring_emit(ring, DERRMR);
8145 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8146 DERRMR_PIPEB_PRI_FLIP_DONE |
8147 DERRMR_PIPEC_PRI_FLIP_DONE));
8148 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8149 intel_ring_emit(ring, DERRMR);
8150 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8151 }
8152
cb05d8de 8153 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 8154 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 8155 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 8156 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 8157
8158 intel_mark_page_flip_active(intel_crtc);
09246732 8159 __intel_ring_advance(ring);
83d4092b
CW		 8160 return 0;
8161
8162err_unpin:
8163 intel_unpin_fb_obj(obj);
8164err:
7c9017e5
JB		 8165 return ret;
8166}
8167
8c9f3aaf
JB		 8168static int intel_default_queue_flip(struct drm_device *dev,
8169 struct drm_crtc *crtc,
8170 struct drm_framebuffer *fb,
ed8d1975
KP		 8171 struct drm_i915_gem_object *obj,
8172 uint32_t flags)
8c9f3aaf
JB		 8173{
8174 return -ENODEV;
8175}
8176
6b95a207
KH		 8177static int intel_crtc_page_flip(struct drm_crtc *crtc,
8178 struct drm_framebuffer *fb,
ed8d1975
KP		 8179 struct drm_pending_vblank_event *event,
8180 uint32_t page_flip_flags)
6b95a207
KH		 8181{
8182 struct drm_device *dev = crtc->dev;
8183 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 8184 struct drm_framebuffer *old_fb = crtc->fb;
8185 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 8186 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8187 struct intel_unpin_work *work;
8c9f3aaf 8188 unsigned long flags;
52e68630 8189 int ret;
6b95a207 8190
e6a595d2
VS		 8191 /* Can't change pixel format via MI display flips. */
8192 if (fb->pixel_format != crtc->fb->pixel_format)
8193 return -EINVAL;
8194
8195 /*
8196 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8197 * Note that pitch changes could also affect these register.
8198 */
8199 if (INTEL_INFO(dev)->gen > 3 &&
8200 (fb->offsets[0] != crtc->fb->offsets[0] ||
8201 fb->pitches[0] != crtc->fb->pitches[0]))
8202 return -EINVAL;
8203
b14c5679 8204 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 8205 if (work == NULL)
8206 return -ENOMEM;
8207
6b95a207 8208 work->event = event;
b4a98e57 8209 work->crtc = crtc;
4a35f83b 8210 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 8211 INIT_WORK(&work->work, intel_unpin_work_fn);
8212
7317c75e
JB		 8213 ret = drm_vblank_get(dev, intel_crtc->pipe);
8214 if (ret)
8215 goto free_work;
8216
6b95a207
KH		 8217 /* We borrow the event spin lock for protecting unpin_work */
8218 spin_lock_irqsave(&dev->event_lock, flags);
8219 if (intel_crtc->unpin_work) {
8220 spin_unlock_irqrestore(&dev->event_lock, flags);
8221 kfree(work);
7317c75e 8222 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 8223
8224 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 8225 return -EBUSY;
8226 }
8227 intel_crtc->unpin_work = work;
8228 spin_unlock_irqrestore(&dev->event_lock, flags);
8229
b4a98e57
CW		 8230 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8231 flush_workqueue(dev_priv->wq);
8232
79158103
CW		 8233 ret = i915_mutex_lock_interruptible(dev);
8234 if (ret)
8235 goto cleanup;
6b95a207 8236
75dfca80 8237 /* Reference the objects for the scheduled work. */
05394f39
CW		 8238 drm_gem_object_reference(&work->old_fb_obj->base);
8239 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8240
8241 crtc->fb = fb;
96b099fd 8242
e1f99ce6 8243 work->pending_flip_obj = obj;
e1f99ce6 8244
4e5359cd
SF		 8245 work->enable_stall_check = true;
8246
b4a98e57 8247 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8248 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8249
ed8d1975 8250 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8251 if (ret)
8252 goto cleanup_pending;
6b95a207 8253
7782de3b 8254 intel_disable_fbc(dev);
c65355bb 8255 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8256 mutex_unlock(&dev->struct_mutex);
8257
e5510fac
JB		 8258 trace_i915_flip_request(intel_crtc->plane, obj);
8259
6b95a207 8260 return 0;
96b099fd 8261
8c9f3aaf 8262cleanup_pending:
b4a98e57 8263 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8264 crtc->fb = old_fb;
05394f39
CW		 8265 drm_gem_object_unreference(&work->old_fb_obj->base);
8266 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8267 mutex_unlock(&dev->struct_mutex);
8268
79158103 8269cleanup:
96b099fd
CW		 8270 spin_lock_irqsave(&dev->event_lock, flags);
8271 intel_crtc->unpin_work = NULL;
8272 spin_unlock_irqrestore(&dev->event_lock, flags);
8273
7317c75e
JB		 8274 drm_vblank_put(dev, intel_crtc->pipe);
8275free_work:
96b099fd
CW		 8276 kfree(work);
8277
8278 return ret;
6b95a207
KH		 8279}
8280
f6e5b160 8281static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8282 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8283 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8284};
8285
50f56119
DV		 8286static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8287 struct drm_crtc *crtc)
8288{
8289 struct drm_device *dev;
8290 struct drm_crtc *tmp;
8291 int crtc_mask = 1;
47f1c6c9 8292
50f56119 8293 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8294
50f56119 8295 dev = crtc->dev;
47f1c6c9 8296
50f56119
DV		 8297 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8298 if (tmp == crtc)
8299 break;
8300 crtc_mask <<= 1;
8301 }
47f1c6c9 8302
50f56119
DV		 8303 if (encoder->possible_crtcs & crtc_mask)
8304 return true;
8305 return false;
47f1c6c9 8306}
79e53945 8307
9a935856
DV		 8308/**
8309 * intel_modeset_update_staged_output_state
8310 *
8311 * Updates the staged output configuration state, e.g. after we've read out the
8312 * current hw state.
8313 */
8314static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8315{
9a935856
DV		 8316 struct intel_encoder *encoder;
8317 struct intel_connector *connector;
f6e5b160 8318
9a935856
DV		 8319 list_for_each_entry(connector, &dev->mode_config.connector_list,
8320 base.head) {
8321 connector->new_encoder =
8322 to_intel_encoder(connector->base.encoder);
8323 }
f6e5b160 8324
9a935856
DV		 8325 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8326 base.head) {
8327 encoder->new_crtc =
8328 to_intel_crtc(encoder->base.crtc);
8329 }
f6e5b160
CW		 8330}
8331
9a935856
DV		 8332/**
8333 * intel_modeset_commit_output_state
8334 *
8335 * This function copies the stage display pipe configuration to the real one.
8336 */
8337static void intel_modeset_commit_output_state(struct drm_device *dev)
8338{
8339 struct intel_encoder *encoder;
8340 struct intel_connector *connector;
f6e5b160 8341
9a935856
DV		 8342 list_for_each_entry(connector, &dev->mode_config.connector_list,
8343 base.head) {
8344 connector->base.encoder = &connector->new_encoder->base;
8345 }
f6e5b160 8346
9a935856
DV		 8347 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8348 base.head) {
8349 encoder->base.crtc = &encoder->new_crtc->base;
8350 }
8351}
8352
050f7aeb
DV		 8353static void
8354connected_sink_compute_bpp(struct intel_connector * connector,
8355 struct intel_crtc_config *pipe_config)
8356{
8357 int bpp = pipe_config->pipe_bpp;
8358
8359 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8360 connector->base.base.id,
8361 drm_get_connector_name(&connector->base));
8362
8363 /* Don't use an invalid EDID bpc value */
8364 if (connector->base.display_info.bpc &&
8365 connector->base.display_info.bpc * 3 < bpp) {
8366 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8367 bpp, connector->base.display_info.bpc*3);
8368 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8369 }
8370
8371 /* Clamp bpp to 8 on screens without EDID 1.4 */
8372 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8373 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8374 bpp);
8375 pipe_config->pipe_bpp = 24;
8376 }
8377}
8378
4e53c2e0 8379static int
050f7aeb
DV		 8380compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8381 struct drm_framebuffer *fb,
8382 struct intel_crtc_config *pipe_config)
4e53c2e0 8383{
050f7aeb
DV		 8384 struct drm_device *dev = crtc->base.dev;
8385 struct intel_connector *connector;
4e53c2e0
DV		 8386 int bpp;
8387
d42264b1
DV		 8388 switch (fb->pixel_format) {
8389 case DRM_FORMAT_C8:
4e53c2e0
DV		 8390 bpp = 8*3; /* since we go through a colormap */
8391 break;
d42264b1
DV		 8392 case DRM_FORMAT_XRGB1555:
8393 case DRM_FORMAT_ARGB1555:
8394 /* checked in intel_framebuffer_init already */
8395 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8396 return -EINVAL;
8397 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8398 bpp = 6*3; /* min is 18bpp */
8399 break;
d42264b1
DV		 8400 case DRM_FORMAT_XBGR8888:
8401 case DRM_FORMAT_ABGR8888:
8402 /* checked in intel_framebuffer_init already */
8403 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8404 return -EINVAL;
8405 case DRM_FORMAT_XRGB8888:
8406 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8407 bpp = 8*3;
8408 break;
d42264b1
DV		 8409 case DRM_FORMAT_XRGB2101010:
8410 case DRM_FORMAT_ARGB2101010:
8411 case DRM_FORMAT_XBGR2101010:
8412 case DRM_FORMAT_ABGR2101010:
8413 /* checked in intel_framebuffer_init already */
8414 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8415 return -EINVAL;
4e53c2e0
DV		 8416 bpp = 10*3;
8417 break;
baba133a 8418 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8419 default:
8420 DRM_DEBUG_KMS("unsupported depth\n");
8421 return -EINVAL;
8422 }
8423
4e53c2e0
DV		 8424 pipe_config->pipe_bpp = bpp;
8425
8426 /* Clamp display bpp to EDID value */
8427 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8428 base.head) {
1b829e05
DV		 8429 if (!connector->new_encoder ||
8430 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8431 continue;
8432
050f7aeb 8433 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8434 }
8435
8436 return bpp;
8437}
8438
644db711
DV		 8439static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8440{
8441 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8442 "type: 0x%x flags: 0x%x\n",
1342830c 8443 mode->crtc_clock,
644db711
DV		 8444 mode->crtc_hdisplay, mode->crtc_hsync_start,
8445 mode->crtc_hsync_end, mode->crtc_htotal,
8446 mode->crtc_vdisplay, mode->crtc_vsync_start,
8447 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8448}
8449
c0b03411
DV		 8450static void intel_dump_pipe_config(struct intel_crtc *crtc,
8451 struct intel_crtc_config *pipe_config,
8452 const char *context)
8453{
8454 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8455 context, pipe_name(crtc->pipe));
8456
8457 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8458 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8459 pipe_config->pipe_bpp, pipe_config->dither);
8460 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8461 pipe_config->has_pch_encoder,
8462 pipe_config->fdi_lanes,
8463 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8464 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8465 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 8466 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8467 pipe_config->has_dp_encoder,
8468 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8469 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8470 pipe_config->dp_m_n.tu);
c0b03411
DV		 8471 DRM_DEBUG_KMS("requested mode:\n");
8472 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8473 DRM_DEBUG_KMS("adjusted mode:\n");
8474 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
644db711 8475 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
d71b8d4a 8476 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 8477 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8478 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 8479 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8480 pipe_config->gmch_pfit.control,
8481 pipe_config->gmch_pfit.pgm_ratios,
8482 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 8483 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 8484 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 8485 pipe_config->pch_pfit.size,
8486 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 8487 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 8488 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
c0b03411
DV		 8489}
8490
accfc0c5
DV		 8491static bool check_encoder_cloning(struct drm_crtc *crtc)
8492{
8493 int num_encoders = 0;
8494 bool uncloneable_encoders = false;
8495 struct intel_encoder *encoder;
8496
8497 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8498 base.head) {
8499 if (&encoder->new_crtc->base != crtc)
8500 continue;
8501
8502 num_encoders++;
8503 if (!encoder->cloneable)
8504 uncloneable_encoders = true;
8505 }
8506
8507 return !(num_encoders > 1 && uncloneable_encoders);
8508}
8509
b8cecdf5
DV		 8510static struct intel_crtc_config *
8511intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8512 struct drm_framebuffer *fb,
b8cecdf5 8513 struct drm_display_mode *mode)
ee7b9f93 8514{
7758a113 8515 struct drm_device *dev = crtc->dev;
7758a113 8516 struct intel_encoder *encoder;
b8cecdf5 8517 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8518 int plane_bpp, ret = -EINVAL;
8519 bool retry = true;
ee7b9f93 8520
accfc0c5
DV		 8521 if (!check_encoder_cloning(crtc)) {
8522 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8523 return ERR_PTR(-EINVAL);
8524 }
8525
b8cecdf5
DV		 8526 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8527 if (!pipe_config)
7758a113
DV		 8528 return ERR_PTR(-ENOMEM);
8529
b8cecdf5
DV		 8530 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8531 drm_mode_copy(&pipe_config->requested_mode, mode);
37327abd 8532
e143a21c
DV		 8533 pipe_config->cpu_transcoder =
8534 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8535 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8536
2960bc9c
ID		 8537 /*
8538 * Sanitize sync polarity flags based on requested ones. If neither
8539 * positive or negative polarity is requested, treat this as meaning
8540 * negative polarity.
8541 */
8542 if (!(pipe_config->adjusted_mode.flags &
8543 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8544 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8545
8546 if (!(pipe_config->adjusted_mode.flags &
8547 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8548 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8549
050f7aeb
DV		 8550 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8551 * plane pixel format and any sink constraints into account. Returns the
8552 * source plane bpp so that dithering can be selected on mismatches
8553 * after encoders and crtc also have had their say. */
8554 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8555 fb, pipe_config);
4e53c2e0
DV		 8556 if (plane_bpp < 0)
8557 goto fail;
8558
e41a56be
VS		 8559 /*
8560 * Determine the real pipe dimensions. Note that stereo modes can
8561 * increase the actual pipe size due to the frame doubling and
8562 * insertion of additional space for blanks between the frame. This
8563 * is stored in the crtc timings. We use the requested mode to do this
8564 * computation to clearly distinguish it from the adjusted mode, which
8565 * can be changed by the connectors in the below retry loop.
8566 */
8567 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8568 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8569 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8570
e29c22c0 8571encoder_retry:
ef1b460d 8572 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8573 pipe_config->port_clock = 0;
ef1b460d 8574 pipe_config->pixel_multiplier = 1;
ff9a6750 8575
135c81b8 8576 /* Fill in default crtc timings, allow encoders to overwrite them. */
6ce70f5e 8577 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
135c81b8 8578
7758a113
DV		 8579 /* Pass our mode to the connectors and the CRTC to give them a chance to
8580 * adjust it according to limitations or connector properties, and also
8581 * a chance to reject the mode entirely.
47f1c6c9 8582 */
7758a113
DV		 8583 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8584 base.head) {
47f1c6c9 8585
7758a113
DV		 8586 if (&encoder->new_crtc->base != crtc)
8587 continue;
7ae89233 8588
efea6e8e
DV		 8589 if (!(encoder->compute_config(encoder, pipe_config))) {
8590 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8591 goto fail;
8592 }
ee7b9f93 8593 }
47f1c6c9 8594
ff9a6750
DV		 8595 /* Set default port clock if not overwritten by the encoder. Needs to be
8596 * done afterwards in case the encoder adjusts the mode. */
8597 if (!pipe_config->port_clock)
241bfc38
DL		 8598 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8599 * pipe_config->pixel_multiplier;
ff9a6750 8600
a43f6e0f 8601 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8602 if (ret < 0) {
7758a113
DV		 8603 DRM_DEBUG_KMS("CRTC fixup failed\n");
8604 goto fail;
ee7b9f93 8605 }
e29c22c0
DV		 8606
8607 if (ret == RETRY) {
8608 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8609 ret = -EINVAL;
8610 goto fail;
8611 }
8612
8613 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8614 retry = false;
8615 goto encoder_retry;
8616 }
8617
4e53c2e0
DV		 8618 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8619 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8620 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8621
b8cecdf5 8622 return pipe_config;
7758a113 8623fail:
b8cecdf5 8624 kfree(pipe_config);
e29c22c0 8625 return ERR_PTR(ret);
ee7b9f93 8626}
47f1c6c9 8627
e2e1ed41
DV		 8628/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8629 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8630static void
8631intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8632 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8633{
8634 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8635 struct drm_device *dev = crtc->dev;
8636 struct intel_encoder *encoder;
8637 struct intel_connector *connector;
8638 struct drm_crtc *tmp_crtc;
79e53945 8639
e2e1ed41 8640 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8641
e2e1ed41
DV		 8642 /* Check which crtcs have changed outputs connected to them, these need
8643 * to be part of the prepare_pipes mask. We don't (yet) support global
8644 * modeset across multiple crtcs, so modeset_pipes will only have one
8645 * bit set at most. */
8646 list_for_each_entry(connector, &dev->mode_config.connector_list,
8647 base.head) {
8648 if (connector->base.encoder == &connector->new_encoder->base)
8649 continue;
79e53945 8650
e2e1ed41
DV		 8651 if (connector->base.encoder) {
8652 tmp_crtc = connector->base.encoder->crtc;
8653
8654 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8655 }
8656
8657 if (connector->new_encoder)
8658 *prepare_pipes |=
8659 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8660 }
8661
e2e1ed41
DV		 8662 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8663 base.head) {
8664 if (encoder->base.crtc == &encoder->new_crtc->base)
8665 continue;
8666
8667 if (encoder->base.crtc) {
8668 tmp_crtc = encoder->base.crtc;
8669
8670 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8671 }
8672
8673 if (encoder->new_crtc)
8674 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8675 }
8676
e2e1ed41
DV		 8677 /* Check for any pipes that will be fully disabled ... */
8678 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8679 base.head) {
8680 bool used = false;
22fd0fab 8681
e2e1ed41
DV		 8682 /* Don't try to disable disabled crtcs. */
8683 if (!intel_crtc->base.enabled)
8684 continue;
7e7d76c3 8685
e2e1ed41
DV		 8686 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8687 base.head) {
8688 if (encoder->new_crtc == intel_crtc)
8689 used = true;
8690 }
8691
8692 if (!used)
8693 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8694 }
8695
e2e1ed41
DV		 8696
8697 /* set_mode is also used to update properties on life display pipes. */
8698 intel_crtc = to_intel_crtc(crtc);
8699 if (crtc->enabled)
8700 *prepare_pipes |= 1 << intel_crtc->pipe;
8701
b6c5164d
DV		 8702 /*
8703 * For simplicity do a full modeset on any pipe where the output routing
8704 * changed. We could be more clever, but that would require us to be
8705 * more careful with calling the relevant encoder->mode_set functions.
8706 */
e2e1ed41
DV		 8707 if (*prepare_pipes)
8708 *modeset_pipes = *prepare_pipes;
8709
8710 /* ... and mask these out. */
8711 *modeset_pipes &= ~(*disable_pipes);
8712 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8713
8714 /*
8715 * HACK: We don't (yet) fully support global modesets. intel_set_config
8716 * obies this rule, but the modeset restore mode of
8717 * intel_modeset_setup_hw_state does not.
8718 */
8719 *modeset_pipes &= 1 << intel_crtc->pipe;
8720 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8721
8722 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8723 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8724}
79e53945 8725
ea9d758d 8726static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8727{
ea9d758d 8728 struct drm_encoder *encoder;
f6e5b160 8729 struct drm_device *dev = crtc->dev;
f6e5b160 8730
ea9d758d
DV		 8731 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8732 if (encoder->crtc == crtc)
8733 return true;
8734
8735 return false;
8736}
8737
8738static void
8739intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8740{
8741 struct intel_encoder *intel_encoder;
8742 struct intel_crtc *intel_crtc;
8743 struct drm_connector *connector;
8744
8745 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8746 base.head) {
8747 if (!intel_encoder->base.crtc)
8748 continue;
8749
8750 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8751
8752 if (prepare_pipes & (1 << intel_crtc->pipe))
8753 intel_encoder->connectors_active = false;
8754 }
8755
8756 intel_modeset_commit_output_state(dev);
8757
8758 /* Update computed state. */
8759 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8760 base.head) {
8761 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8762 }
8763
8764 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8765 if (!connector->encoder || !connector->encoder->crtc)
8766 continue;
8767
8768 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8769
8770 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8771 struct drm_property *dpms_property =
8772 dev->mode_config.dpms_property;
8773
ea9d758d 8774 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8775 drm_object_property_set_value(&connector->base,
68d34720
DV		 8776 dpms_property,
8777 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8778
8779 intel_encoder = to_intel_encoder(connector->encoder);
8780 intel_encoder->connectors_active = true;
8781 }
8782 }
8783
8784}
8785
3bd26263 8786static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 8787{
3bd26263 8788 int diff;
f1f644dc
JB		 8789
8790 if (clock1 == clock2)
8791 return true;
8792
8793 if (!clock1 || !clock2)
8794 return false;
8795
8796 diff = abs(clock1 - clock2);
8797
8798 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8799 return true;
8800
8801 return false;
8802}
8803
25c5b266
DV		 8804#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8805 list_for_each_entry((intel_crtc), \
8806 &(dev)->mode_config.crtc_list, \
8807 base.head) \
0973f18f 8808 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8809
0e8ffe1b 8810static bool
2fa2fe9a
DV		 8811intel_pipe_config_compare(struct drm_device *dev,
8812 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8813 struct intel_crtc_config *pipe_config)
8814{
66e985c0
DV		 8815#define PIPE_CONF_CHECK_X(name) \
8816 if (current_config->name != pipe_config->name) { \
8817 DRM_ERROR("mismatch in " #name " " \
8818 "(expected 0x%08x, found 0x%08x)\n", \
8819 current_config->name, \
8820 pipe_config->name); \
8821 return false; \
8822 }
8823
08a24034
DV		 8824#define PIPE_CONF_CHECK_I(name) \
8825 if (current_config->name != pipe_config->name) { \
8826 DRM_ERROR("mismatch in " #name " " \
8827 "(expected %i, found %i)\n", \
8828 current_config->name, \
8829 pipe_config->name); \
8830 return false; \
88adfff1
DV		 8831 }
8832
1bd1bd80
DV		 8833#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8834 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8835 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8836 "(expected %i, found %i)\n", \
8837 current_config->name & (mask), \
8838 pipe_config->name & (mask)); \
8839 return false; \
8840 }
8841
5e550656
VS		 8842#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8843 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8844 DRM_ERROR("mismatch in " #name " " \
8845 "(expected %i, found %i)\n", \
8846 current_config->name, \
8847 pipe_config->name); \
8848 return false; \
8849 }
8850
bb760063
DV		 8851#define PIPE_CONF_QUIRK(quirk) \
8852 ((current_config->quirks | pipe_config->quirks) & (quirk))
8853
eccb140b
DV		 8854 PIPE_CONF_CHECK_I(cpu_transcoder);
8855
08a24034
DV		 8856 PIPE_CONF_CHECK_I(has_pch_encoder);
8857 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8858 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8859 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8860 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8861 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8862 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8863
eb14cb74
VS		 8864 PIPE_CONF_CHECK_I(has_dp_encoder);
8865 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8866 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8867 PIPE_CONF_CHECK_I(dp_m_n.link_m);
8868 PIPE_CONF_CHECK_I(dp_m_n.link_n);
8869 PIPE_CONF_CHECK_I(dp_m_n.tu);
8870
1bd1bd80
DV		 8871 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8872 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8873 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8874 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8875 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8876 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8877
8878 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8879 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8880 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8881 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8882 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8883 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8884
c93f54cf 8885 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8886
1bd1bd80
DV		 8887 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8888 DRM_MODE_FLAG_INTERLACE);
8889
bb760063
DV		 8890 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8891 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8892 DRM_MODE_FLAG_PHSYNC);
8893 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8894 DRM_MODE_FLAG_NHSYNC);
8895 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8896 DRM_MODE_FLAG_PVSYNC);
8897 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8898 DRM_MODE_FLAG_NVSYNC);
8899 }
045ac3b5 8900
37327abd
VS		 8901 PIPE_CONF_CHECK_I(pipe_src_w);
8902 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 8903
2fa2fe9a
DV		 8904 PIPE_CONF_CHECK_I(gmch_pfit.control);
8905 /* pfit ratios are autocomputed by the hw on gen4+ */
8906 if (INTEL_INFO(dev)->gen < 4)
8907 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8908 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
fd4daa9c
CW		 8909 PIPE_CONF_CHECK_I(pch_pfit.enabled);
8910 if (current_config->pch_pfit.enabled) {
8911 PIPE_CONF_CHECK_I(pch_pfit.pos);
8912 PIPE_CONF_CHECK_I(pch_pfit.size);
8913 }
2fa2fe9a 8914
42db64ef
PZ		 8915 PIPE_CONF_CHECK_I(ips_enabled);
8916
282740f7
VS		 8917 PIPE_CONF_CHECK_I(double_wide);
8918
c0d43d62 8919 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8920 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8921 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8922 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8923 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8924
42571aef
VS		 8925 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8926 PIPE_CONF_CHECK_I(pipe_bpp);
8927
d71b8d4a 8928 if (!IS_HASWELL(dev)) {
241bfc38 8929 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
d71b8d4a
VS		 8930 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8931 }
5e550656 8932
66e985c0 8933#undef PIPE_CONF_CHECK_X
08a24034 8934#undef PIPE_CONF_CHECK_I
1bd1bd80 8935#undef PIPE_CONF_CHECK_FLAGS
5e550656 8936#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 8937#undef PIPE_CONF_QUIRK
88adfff1 8938
0e8ffe1b
DV		 8939 return true;
8940}
8941
91d1b4bd
DV		 8942static void
8943check_connector_state(struct drm_device *dev)
8af6cf88 8944{
8af6cf88
DV		 8945 struct intel_connector *connector;
8946
8947 list_for_each_entry(connector, &dev->mode_config.connector_list,
8948 base.head) {
8949 /* This also checks the encoder/connector hw state with the
8950 * ->get_hw_state callbacks. */
8951 intel_connector_check_state(connector);
8952
8953 WARN(&connector->new_encoder->base != connector->base.encoder,
8954 "connector's staged encoder doesn't match current encoder\n");
8955 }
91d1b4bd
DV		 8956}
8957
8958static void
8959check_encoder_state(struct drm_device *dev)
8960{
8961 struct intel_encoder *encoder;
8962 struct intel_connector *connector;
8af6cf88
DV		 8963
8964 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8965 base.head) {
8966 bool enabled = false;
8967 bool active = false;
8968 enum pipe pipe, tracked_pipe;
8969
8970 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8971 encoder->base.base.id,
8972 drm_get_encoder_name(&encoder->base));
8973
8974 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8975 "encoder's stage crtc doesn't match current crtc\n");
8976 WARN(encoder->connectors_active && !encoder->base.crtc,
8977 "encoder's active_connectors set, but no crtc\n");
8978
8979 list_for_each_entry(connector, &dev->mode_config.connector_list,
8980 base.head) {
8981 if (connector->base.encoder != &encoder->base)
8982 continue;
8983 enabled = true;
8984 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8985 active = true;
8986 }
8987 WARN(!!encoder->base.crtc != enabled,
8988 "encoder's enabled state mismatch "
8989 "(expected %i, found %i)\n",
8990 !!encoder->base.crtc, enabled);
8991 WARN(active && !encoder->base.crtc,
8992 "active encoder with no crtc\n");
8993
8994 WARN(encoder->connectors_active != active,
8995 "encoder's computed active state doesn't match tracked active state "
8996 "(expected %i, found %i)\n", active, encoder->connectors_active);
8997
8998 active = encoder->get_hw_state(encoder, &pipe);
8999 WARN(active != encoder->connectors_active,
9000 "encoder's hw state doesn't match sw tracking "
9001 "(expected %i, found %i)\n",
9002 encoder->connectors_active, active);
9003
9004 if (!encoder->base.crtc)
9005 continue;
9006
9007 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9008 WARN(active && pipe != tracked_pipe,
9009 "active encoder's pipe doesn't match"
9010 "(expected %i, found %i)\n",
9011 tracked_pipe, pipe);
9012
9013 }
91d1b4bd
DV		 9014}
9015
9016static void
9017check_crtc_state(struct drm_device *dev)
9018{
9019 drm_i915_private_t *dev_priv = dev->dev_private;
9020 struct intel_crtc *crtc;
9021 struct intel_encoder *encoder;
9022 struct intel_crtc_config pipe_config;
8af6cf88
DV		 9023
9024 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9025 base.head) {
9026 bool enabled = false;
9027 bool active = false;
9028
045ac3b5
JB		 9029 memset(&pipe_config, 0, sizeof(pipe_config));
9030
8af6cf88
DV		 9031 DRM_DEBUG_KMS("[CRTC:%d]\n",
9032 crtc->base.base.id);
9033
9034 WARN(crtc->active && !crtc->base.enabled,
9035 "active crtc, but not enabled in sw tracking\n");
9036
9037 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9038 base.head) {
9039 if (encoder->base.crtc != &crtc->base)
9040 continue;
9041 enabled = true;
9042 if (encoder->connectors_active)
9043 active = true;
9044 }
6c49f241 9045
8af6cf88
DV		 9046 WARN(active != crtc->active,
9047 "crtc's computed active state doesn't match tracked active state "
9048 "(expected %i, found %i)\n", active, crtc->active);
9049 WARN(enabled != crtc->base.enabled,
9050 "crtc's computed enabled state doesn't match tracked enabled state "
9051 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9052
0e8ffe1b
DV		 9053 active = dev_priv->display.get_pipe_config(crtc,
9054 &pipe_config);
d62cf62a
DV		 9055
9056 /* hw state is inconsistent with the pipe A quirk */
9057 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9058 active = crtc->active;
9059
6c49f241
DV		 9060 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9061 base.head) {
3eaba51c 9062 enum pipe pipe;
6c49f241
DV		 9063 if (encoder->base.crtc != &crtc->base)
9064 continue;
3eaba51c
VS		 9065 if (encoder->get_config &&
9066 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 9067 encoder->get_config(encoder, &pipe_config);
9068 }
9069
0e8ffe1b
DV		 9070 WARN(crtc->active != active,
9071 "crtc active state doesn't match with hw state "
9072 "(expected %i, found %i)\n", crtc->active, active);
9073
c0b03411
DV		 9074 if (active &&
9075 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9076 WARN(1, "pipe state doesn't match!\n");
9077 intel_dump_pipe_config(crtc, &pipe_config,
9078 "[hw state]");
9079 intel_dump_pipe_config(crtc, &crtc->config,
9080 "[sw state]");
9081 }
8af6cf88
DV		 9082 }
9083}
9084
91d1b4bd
DV		 9085static void
9086check_shared_dpll_state(struct drm_device *dev)
9087{
9088 drm_i915_private_t *dev_priv = dev->dev_private;
9089 struct intel_crtc *crtc;
9090 struct intel_dpll_hw_state dpll_hw_state;
9091 int i;
5358901f
DV		 9092
9093 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9094 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9095 int enabled_crtcs = 0, active_crtcs = 0;
9096 bool active;
9097
9098 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9099
9100 DRM_DEBUG_KMS("%s\n", pll->name);
9101
9102 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9103
9104 WARN(pll->active > pll->refcount,
9105 "more active pll users than references: %i vs %i\n",
9106 pll->active, pll->refcount);
9107 WARN(pll->active && !pll->on,
9108 "pll in active use but not on in sw tracking\n");
35c95375
DV		 9109 WARN(pll->on && !pll->active,
9110 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 9111 WARN(pll->on != active,
9112 "pll on state mismatch (expected %i, found %i)\n",
9113 pll->on, active);
9114
9115 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9116 base.head) {
9117 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9118 enabled_crtcs++;
9119 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9120 active_crtcs++;
9121 }
9122 WARN(pll->active != active_crtcs,
9123 "pll active crtcs mismatch (expected %i, found %i)\n",
9124 pll->active, active_crtcs);
9125 WARN(pll->refcount != enabled_crtcs,
9126 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9127 pll->refcount, enabled_crtcs);
66e985c0
DV		 9128
9129 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9130 sizeof(dpll_hw_state)),
9131 "pll hw state mismatch\n");
5358901f 9132 }
8af6cf88
DV		 9133}
9134
91d1b4bd
DV		 9135void
9136intel_modeset_check_state(struct drm_device *dev)
9137{
9138 check_connector_state(dev);
9139 check_encoder_state(dev);
9140 check_crtc_state(dev);
9141 check_shared_dpll_state(dev);
9142}
9143
18442d08
VS		 9144void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9145 int dotclock)
9146{
9147 /*
9148 * FDI already provided one idea for the dotclock.
9149 * Yell if the encoder disagrees.
9150 */
241bfc38 9151 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
18442d08 9152 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
241bfc38 9153 pipe_config->adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 9154}
9155
f30da187
DV		 9156static int __intel_set_mode(struct drm_crtc *crtc,
9157 struct drm_display_mode *mode,
9158 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 9159{
9160 struct drm_device *dev = crtc->dev;
dbf2b54e 9161 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 9162 struct drm_display_mode *saved_mode, *saved_hwmode;
9163 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 9164 struct intel_crtc *intel_crtc;
9165 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 9166 int ret = 0;
a6778b3c 9167
a1e22653 9168 saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 9169 if (!saved_mode)
9170 return -ENOMEM;
3ac18232 9171 saved_hwmode = saved_mode + 1;
a6778b3c 9172
e2e1ed41 9173 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 9174 &prepare_pipes, &disable_pipes);
9175
3ac18232
TG		 9176 *saved_hwmode = crtc->hwmode;
9177 *saved_mode = crtc->mode;
a6778b3c 9178
25c5b266
DV		 9179 /* Hack: Because we don't (yet) support global modeset on multiple
9180 * crtcs, we don't keep track of the new mode for more than one crtc.
9181 * Hence simply check whether any bit is set in modeset_pipes in all the
9182 * pieces of code that are not yet converted to deal with mutliple crtcs
9183 * changing their mode at the same time. */
25c5b266 9184 if (modeset_pipes) {
4e53c2e0 9185 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 9186 if (IS_ERR(pipe_config)) {
9187 ret = PTR_ERR(pipe_config);
9188 pipe_config = NULL;
9189
3ac18232 9190 goto out;
25c5b266 9191 }
c0b03411
DV		 9192 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9193 "[modeset]");
25c5b266 9194 }
a6778b3c 9195
460da916
DV		 9196 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9197 intel_crtc_disable(&intel_crtc->base);
9198
ea9d758d
DV		 9199 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9200 if (intel_crtc->base.enabled)
9201 dev_priv->display.crtc_disable(&intel_crtc->base);
9202 }
a6778b3c 9203
6c4c86f5
DV		 9204 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9205 * to set it here already despite that we pass it down the callchain.
f6e5b160 9206 */
b8cecdf5 9207 if (modeset_pipes) {
25c5b266 9208 crtc->mode = *mode;
b8cecdf5
DV		 9209 /* mode_set/enable/disable functions rely on a correct pipe
9210 * config. */
9211 to_intel_crtc(crtc)->config = *pipe_config;
9212 }
7758a113 9213
ea9d758d
DV		 9214 /* Only after disabling all output pipelines that will be changed can we
9215 * update the the output configuration. */
9216 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 9217
47fab737
DV		 9218 if (dev_priv->display.modeset_global_resources)
9219 dev_priv->display.modeset_global_resources(dev);
9220
a6778b3c
DV		 9221 /* Set up the DPLL and any encoders state that needs to adjust or depend
9222 * on the DPLL.
f6e5b160 9223 */
25c5b266 9224 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 9225 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 9226 x, y, fb);
9227 if (ret)
9228 goto done;
a6778b3c
DV		 9229 }
9230
9231 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 9232 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9233 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 9234
25c5b266
DV		 9235 if (modeset_pipes) {
9236 /* Store real post-adjustment hardware mode. */
b8cecdf5 9237 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 9238
25c5b266
DV		 9239 /* Calculate and store various constants which
9240 * are later needed by vblank and swap-completion
9241 * timestamping. They are derived from true hwmode.
9242 */
9243 drm_calc_timestamping_constants(crtc);
9244 }
a6778b3c
DV		 9245
9246 /* FIXME: add subpixel order */
9247done:
c0c36b94 9248 if (ret && crtc->enabled) {
3ac18232
TG		 9249 crtc->hwmode = *saved_hwmode;
9250 crtc->mode = *saved_mode;
a6778b3c
DV		 9251 }
9252
3ac18232 9253out:
b8cecdf5 9254 kfree(pipe_config);
3ac18232 9255 kfree(saved_mode);
a6778b3c 9256 return ret;
f6e5b160
CW		 9257}
9258
e7457a9a
DL		 9259static int intel_set_mode(struct drm_crtc *crtc,
9260 struct drm_display_mode *mode,
9261 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 9262{
9263 int ret;
9264
9265 ret = __intel_set_mode(crtc, mode, x, y, fb);
9266
9267 if (ret == 0)
9268 intel_modeset_check_state(crtc->dev);
9269
9270 return ret;
9271}
9272
c0c36b94
CW		 9273void intel_crtc_restore_mode(struct drm_crtc *crtc)
9274{
9275 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9276}
9277
25c5b266
DV		 9278#undef for_each_intel_crtc_masked
9279
d9e55608
DV		 9280static void intel_set_config_free(struct intel_set_config *config)
9281{
9282 if (!config)
9283 return;
9284
1aa4b628
DV		 9285 kfree(config->save_connector_encoders);
9286 kfree(config->save_encoder_crtcs);
d9e55608
DV		 9287 kfree(config);
9288}
9289
85f9eb71
DV		 9290static int intel_set_config_save_state(struct drm_device *dev,
9291 struct intel_set_config *config)
9292{
85f9eb71
DV		 9293 struct drm_encoder *encoder;
9294 struct drm_connector *connector;
9295 int count;
9296
1aa4b628
DV		 9297 config->save_encoder_crtcs =
9298 kcalloc(dev->mode_config.num_encoder,
9299 sizeof(struct drm_crtc *), GFP_KERNEL);
9300 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9301 return -ENOMEM;
9302
1aa4b628
DV		 9303 config->save_connector_encoders =
9304 kcalloc(dev->mode_config.num_connector,
9305 sizeof(struct drm_encoder *), GFP_KERNEL);
9306 if (!config->save_connector_encoders)
85f9eb71
DV		 9307 return -ENOMEM;
9308
9309 /* Copy data. Note that driver private data is not affected.
9310 * Should anything bad happen only the expected state is
9311 * restored, not the drivers personal bookkeeping.
9312 */
85f9eb71
DV		 9313 count = 0;
9314 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9315 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9316 }
9317
9318 count = 0;
9319 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9320 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9321 }
9322
9323 return 0;
9324}
9325
9326static void intel_set_config_restore_state(struct drm_device *dev,
9327 struct intel_set_config *config)
9328{
9a935856
DV		 9329 struct intel_encoder *encoder;
9330 struct intel_connector *connector;
85f9eb71
DV		 9331 int count;
9332
85f9eb71 9333 count = 0;
9a935856
DV		 9334 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9335 encoder->new_crtc =
9336 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9337 }
9338
9339 count = 0;
9a935856
DV		 9340 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9341 connector->new_encoder =
9342 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9343 }
9344}
9345
e3de42b6 9346static bool
2e57f47d 9347is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9348{
9349 int i;
9350
2e57f47d
CW		 9351 if (set->num_connectors == 0)
9352 return false;
9353
9354 if (WARN_ON(set->connectors == NULL))
9355 return false;
9356
9357 for (i = 0; i < set->num_connectors; i++)
9358 if (set->connectors[i]->encoder &&
9359 set->connectors[i]->encoder->crtc == set->crtc &&
9360 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9361 return true;
9362
9363 return false;
9364}
9365
5e2b584e
DV		 9366static void
9367intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9368 struct intel_set_config *config)
9369{
9370
9371 /* We should be able to check here if the fb has the same properties
9372 * and then just flip_or_move it */
2e57f47d
CW		 9373 if (is_crtc_connector_off(set)) {
9374 config->mode_changed = true;
e3de42b6 9375 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9376 /* If we have no fb then treat it as a full mode set */
9377 if (set->crtc->fb == NULL) {
319d9827
JB		 9378 struct intel_crtc *intel_crtc =
9379 to_intel_crtc(set->crtc);
9380
9381 if (intel_crtc->active && i915_fastboot) {
9382 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9383 config->fb_changed = true;
9384 } else {
9385 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9386 config->mode_changed = true;
9387 }
5e2b584e
DV		 9388 } else if (set->fb == NULL) {
9389 config->mode_changed = true;
72f4901e
DV		 9390 } else if (set->fb->pixel_format !=
9391 set->crtc->fb->pixel_format) {
5e2b584e 9392 config->mode_changed = true;
e3de42b6 9393 } else {
5e2b584e 9394 config->fb_changed = true;
e3de42b6 9395 }
5e2b584e
DV		 9396 }
9397
835c5873 9398 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9399 config->fb_changed = true;
9400
9401 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9402 DRM_DEBUG_KMS("modes are different, full mode set\n");
9403 drm_mode_debug_printmodeline(&set->crtc->mode);
9404 drm_mode_debug_printmodeline(set->mode);
9405 config->mode_changed = true;
9406 }
a1d95703
CW		 9407
9408 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9409 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9410}
9411
2e431051 9412static int
9a935856
DV		 9413intel_modeset_stage_output_state(struct drm_device *dev,
9414 struct drm_mode_set *set,
9415 struct intel_set_config *config)
50f56119 9416{
85f9eb71 9417 struct drm_crtc *new_crtc;
9a935856
DV		 9418 struct intel_connector *connector;
9419 struct intel_encoder *encoder;
f3f08572 9420 int ro;
50f56119 9421
9abdda74 9422 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9423 * of connectors. For paranoia, double-check this. */
9424 WARN_ON(!set->fb && (set->num_connectors != 0));
9425 WARN_ON(set->fb && (set->num_connectors == 0));
9426
9a935856
DV		 9427 list_for_each_entry(connector, &dev->mode_config.connector_list,
9428 base.head) {
9429 /* Otherwise traverse passed in connector list and get encoders
9430 * for them. */
50f56119 9431 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9432 if (set->connectors[ro] == &connector->base) {
9433 connector->new_encoder = connector->encoder;
50f56119
DV		 9434 break;
9435 }
9436 }
9437
9a935856
DV		 9438 /* If we disable the crtc, disable all its connectors. Also, if
9439 * the connector is on the changing crtc but not on the new
9440 * connector list, disable it. */
9441 if ((!set->fb || ro == set->num_connectors) &&
9442 connector->base.encoder &&
9443 connector->base.encoder->crtc == set->crtc) {
9444 connector->new_encoder = NULL;
9445
9446 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9447 connector->base.base.id,
9448 drm_get_connector_name(&connector->base));
9449 }
9450
9451
9452 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9453 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9454 config->mode_changed = true;
50f56119
DV		 9455 }
9456 }
9a935856 9457 /* connector->new_encoder is now updated for all connectors. */
50f56119 9458
9a935856 9459 /* Update crtc of enabled connectors. */
9a935856
DV		 9460 list_for_each_entry(connector, &dev->mode_config.connector_list,
9461 base.head) {
9462 if (!connector->new_encoder)
50f56119
DV		 9463 continue;
9464
9a935856 9465 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9466
9467 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9468 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9469 new_crtc = set->crtc;
9470 }
9471
9472 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9473 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9474 new_crtc)) {
5e2b584e 9475 return -EINVAL;
50f56119 9476 }
9a935856
DV		 9477 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9478
9479 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9480 connector->base.base.id,
9481 drm_get_connector_name(&connector->base),
9482 new_crtc->base.id);
9483 }
9484
9485 /* Check for any encoders that needs to be disabled. */
9486 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9487 base.head) {
9488 list_for_each_entry(connector,
9489 &dev->mode_config.connector_list,
9490 base.head) {
9491 if (connector->new_encoder == encoder) {
9492 WARN_ON(!connector->new_encoder->new_crtc);
9493
9494 goto next_encoder;
9495 }
9496 }
9497 encoder->new_crtc = NULL;
9498next_encoder:
9499 /* Only now check for crtc changes so we don't miss encoders
9500 * that will be disabled. */
9501 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9502 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9503 config->mode_changed = true;
50f56119
DV		 9504 }
9505 }
9a935856 9506 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9507
2e431051
DV		 9508 return 0;
9509}
9510
9511static int intel_crtc_set_config(struct drm_mode_set *set)
9512{
9513 struct drm_device *dev;
2e431051
DV		 9514 struct drm_mode_set save_set;
9515 struct intel_set_config *config;
9516 int ret;
2e431051 9517
8d3e375e
DV		 9518 BUG_ON(!set);
9519 BUG_ON(!set->crtc);
9520 BUG_ON(!set->crtc->helper_private);
2e431051 9521
7e53f3a4
DV		 9522 /* Enforce sane interface api - has been abused by the fb helper. */
9523 BUG_ON(!set->mode && set->fb);
9524 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9525
2e431051
DV		 9526 if (set->fb) {
9527 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9528 set->crtc->base.id, set->fb->base.id,
9529 (int)set->num_connectors, set->x, set->y);
9530 } else {
9531 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9532 }
9533
9534 dev = set->crtc->dev;
9535
9536 ret = -ENOMEM;
9537 config = kzalloc(sizeof(*config), GFP_KERNEL);
9538 if (!config)
9539 goto out_config;
9540
9541 ret = intel_set_config_save_state(dev, config);
9542 if (ret)
9543 goto out_config;
9544
9545 save_set.crtc = set->crtc;
9546 save_set.mode = &set->crtc->mode;
9547 save_set.x = set->crtc->x;
9548 save_set.y = set->crtc->y;
9549 save_set.fb = set->crtc->fb;
9550
9551 /* Compute whether we need a full modeset, only an fb base update or no
9552 * change at all. In the future we might also check whether only the
9553 * mode changed, e.g. for LVDS where we only change the panel fitter in
9554 * such cases. */
9555 intel_set_config_compute_mode_changes(set, config);
9556
9a935856 9557 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9558 if (ret)
9559 goto fail;
9560
5e2b584e 9561 if (config->mode_changed) {
c0c36b94
CW		 9562 ret = intel_set_mode(set->crtc, set->mode,
9563 set->x, set->y, set->fb);
5e2b584e 9564 } else if (config->fb_changed) {
4878cae2
VS		 9565 intel_crtc_wait_for_pending_flips(set->crtc);
9566
4f660f49 9567 ret = intel_pipe_set_base(set->crtc,
94352cf9 9568 set->x, set->y, set->fb);
50f56119
DV		 9569 }
9570
2d05eae1 9571 if (ret) {
bf67dfeb
DV		 9572 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9573 set->crtc->base.id, ret);
50f56119 9574fail:
2d05eae1 9575 intel_set_config_restore_state(dev, config);
50f56119 9576
2d05eae1
CW		 9577 /* Try to restore the config */
9578 if (config->mode_changed &&
9579 intel_set_mode(save_set.crtc, save_set.mode,
9580 save_set.x, save_set.y, save_set.fb))
9581 DRM_ERROR("failed to restore config after modeset failure\n");
9582 }
50f56119 9583
d9e55608
DV		 9584out_config:
9585 intel_set_config_free(config);
50f56119
DV		 9586 return ret;
9587}
f6e5b160
CW		 9588
9589static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9590 .cursor_set = intel_crtc_cursor_set,
9591 .cursor_move = intel_crtc_cursor_move,
9592 .gamma_set = intel_crtc_gamma_set,
50f56119 9593 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9594 .destroy = intel_crtc_destroy,
9595 .page_flip = intel_crtc_page_flip,
9596};
9597
79f689aa
PZ		 9598static void intel_cpu_pll_init(struct drm_device *dev)
9599{
affa9354 9600 if (HAS_DDI(dev))
79f689aa
PZ		 9601 intel_ddi_pll_init(dev);
9602}
9603
5358901f
DV		 9604static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9605 struct intel_shared_dpll *pll,
9606 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9607{
5358901f 9608 uint32_t val;
ee7b9f93 9609
5358901f 9610 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9611 hw_state->dpll = val;
9612 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9613 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9614
9615 return val & DPLL_VCO_ENABLE;
9616}
9617
15bdd4cf
DV		 9618static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9619 struct intel_shared_dpll *pll)
9620{
9621 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9622 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9623}
9624
e7b903d2
DV		 9625static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9626 struct intel_shared_dpll *pll)
9627{
e7b903d2
DV		 9628 /* PCH refclock must be enabled first */
9629 assert_pch_refclk_enabled(dev_priv);
9630
15bdd4cf
DV		 9631 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9632
9633 /* Wait for the clocks to stabilize. */
9634 POSTING_READ(PCH_DPLL(pll->id));
9635 udelay(150);
9636
9637 /* The pixel multiplier can only be updated once the
9638 * DPLL is enabled and the clocks are stable.
9639 *
9640 * So write it again.
9641 */
9642 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9643 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9644 udelay(200);
9645}
9646
9647static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9648 struct intel_shared_dpll *pll)
9649{
9650 struct drm_device *dev = dev_priv->dev;
9651 struct intel_crtc *crtc;
e7b903d2
DV		 9652
9653 /* Make sure no transcoder isn't still depending on us. */
9654 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9655 if (intel_crtc_to_shared_dpll(crtc) == pll)
9656 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9657 }
9658
15bdd4cf
DV		 9659 I915_WRITE(PCH_DPLL(pll->id), 0);
9660 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9661 udelay(200);
9662}
9663
46edb027
DV		 9664static char *ibx_pch_dpll_names[] = {
9665 "PCH DPLL A",
9666 "PCH DPLL B",
9667};
9668
7c74ade1 9669static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9670{
e7b903d2 9671 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9672 int i;
9673
7c74ade1 9674 dev_priv->num_shared_dpll = 2;
ee7b9f93 9675
e72f9fbf 9676 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9677 dev_priv->shared_dplls[i].id = i;
9678 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9679 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9680 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9681 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9682 dev_priv->shared_dplls[i].get_hw_state =
9683 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9684 }
9685}
9686
7c74ade1
DV		 9687static void intel_shared_dpll_init(struct drm_device *dev)
9688{
e7b903d2 9689 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9690
9691 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9692 ibx_pch_dpll_init(dev);
9693 else
9694 dev_priv->num_shared_dpll = 0;
9695
9696 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9697 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9698 dev_priv->num_shared_dpll);
9699}
9700
b358d0a6 9701static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9702{
22fd0fab 9703 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9704 struct intel_crtc *intel_crtc;
9705 int i;
9706
955382f3 9707 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 9708 if (intel_crtc == NULL)
9709 return;
9710
9711 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9712
9713 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9714 for (i = 0; i < 256; i++) {
9715 intel_crtc->lut_r[i] = i;
9716 intel_crtc->lut_g[i] = i;
9717 intel_crtc->lut_b[i] = i;
9718 }
9719
80824003
JB		 9720 /* Swap pipes & planes for FBC on pre-965 */
9721 intel_crtc->pipe = pipe;
9722 intel_crtc->plane = pipe;
e2e767ab 9723 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9724 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9725 intel_crtc->plane = !pipe;
80824003
JB		 9726 }
9727
22fd0fab
JB		 9728 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9729 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9730 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9731 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9732
79e53945 9733 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9734}
9735
08d7b3d1 9736int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9737 struct drm_file *file)
08d7b3d1 9738{
08d7b3d1 9739 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9740 struct drm_mode_object *drmmode_obj;
9741 struct intel_crtc *crtc;
08d7b3d1 9742
1cff8f6b
DV		 9743 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9744 return -ENODEV;
08d7b3d1 9745
c05422d5
DV		 9746 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9747 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9748
c05422d5 9749 if (!drmmode_obj) {
08d7b3d1
CW		 9750 DRM_ERROR("no such CRTC id\n");
9751 return -EINVAL;
9752 }
9753
c05422d5
DV		 9754 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9755 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9756
c05422d5 9757 return 0;
08d7b3d1
CW		 9758}
9759
66a9278e 9760static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9761{
66a9278e
DV		 9762 struct drm_device *dev = encoder->base.dev;
9763 struct intel_encoder *source_encoder;
79e53945 9764 int index_mask = 0;
79e53945
JB		 9765 int entry = 0;
9766
66a9278e
DV		 9767 list_for_each_entry(source_encoder,
9768 &dev->mode_config.encoder_list, base.head) {
9769
9770 if (encoder == source_encoder)
79e53945 9771 index_mask |= (1 << entry);
66a9278e
DV		 9772
9773 /* Intel hw has only one MUX where enocoders could be cloned. */
9774 if (encoder->cloneable && source_encoder->cloneable)
9775 index_mask |= (1 << entry);
9776
79e53945
JB		 9777 entry++;
9778 }
4ef69c7a 9779
79e53945
JB		 9780 return index_mask;
9781}
9782
4d302442
CW		 9783static bool has_edp_a(struct drm_device *dev)
9784{
9785 struct drm_i915_private *dev_priv = dev->dev_private;
9786
9787 if (!IS_MOBILE(dev))
9788 return false;
9789
9790 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9791 return false;
9792
9793 if (IS_GEN5(dev) &&
9794 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9795 return false;
9796
9797 return true;
9798}
9799
79e53945
JB		 9800static void intel_setup_outputs(struct drm_device *dev)
9801{
725e30ad 9802 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9803 struct intel_encoder *encoder;
cb0953d7 9804 bool dpd_is_edp = false;
79e53945 9805
c9093354 9806 intel_lvds_init(dev);
79e53945 9807
c40c0f5b 9808 if (!IS_ULT(dev))
79935fca 9809 intel_crt_init(dev);
cb0953d7 9810
affa9354 9811 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9812 int found;
9813
9814 /* Haswell uses DDI functions to detect digital outputs */
9815 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9816 /* DDI A only supports eDP */
9817 if (found)
9818 intel_ddi_init(dev, PORT_A);
9819
9820 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9821 * register */
9822 found = I915_READ(SFUSE_STRAP);
9823
9824 if (found & SFUSE_STRAP_DDIB_DETECTED)
9825 intel_ddi_init(dev, PORT_B);
9826 if (found & SFUSE_STRAP_DDIC_DETECTED)
9827 intel_ddi_init(dev, PORT_C);
9828 if (found & SFUSE_STRAP_DDID_DETECTED)
9829 intel_ddi_init(dev, PORT_D);
9830 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9831 int found;
270b3042
DV		 9832 dpd_is_edp = intel_dpd_is_edp(dev);
9833
9834 if (has_edp_a(dev))
9835 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9836
dc0fa718 9837 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9838 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9839 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9840 if (!found)
e2debe91 9841 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9842 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9843 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9844 }
9845
dc0fa718 9846 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9847 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9848
dc0fa718 9849 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9850 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9851
5eb08b69 9852 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9853 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9854
270b3042 9855 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9856 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9857 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9858 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB		 9859 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9860 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9861 PORT_C);
9862 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9863 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9864 PORT_C);
9865 }
19c03924 9866
dc0fa718 9867 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9868 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9869 PORT_B);
67cfc203
VS		 9870 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9871 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9872 }
3cfca973
JN		 9873
9874 intel_dsi_init(dev);
103a196f 9875 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9876 bool found = false;
7d57382e 9877
e2debe91 9878 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9879 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9880 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9881 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9882 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9883 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9884 }
27185ae1 9885
e7281eab 9886 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9887 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9888 }
13520b05
KH		 9889
9890 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9891
e2debe91 9892 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9893 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9894 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9895 }
27185ae1 9896
e2debe91 9897 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9898
b01f2c3a
JB		 9899 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9900 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9901 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9902 }
e7281eab 9903 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9904 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9905 }
27185ae1 9906
b01f2c3a 9907 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9908 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9909 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9910 } else if (IS_GEN2(dev))
79e53945
JB		 9911 intel_dvo_init(dev);
9912
103a196f 9913 if (SUPPORTS_TV(dev))
79e53945
JB		 9914 intel_tv_init(dev);
9915
4ef69c7a
CW		 9916 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9917 encoder->base.possible_crtcs = encoder->crtc_mask;
9918 encoder->base.possible_clones =
66a9278e 9919 intel_encoder_clones(encoder);
79e53945 9920 }
47356eb6 9921
dde86e2d 9922 intel_init_pch_refclk(dev);
270b3042
DV		 9923
9924 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9925}
9926
ddfe1567
CW		 9927void intel_framebuffer_fini(struct intel_framebuffer *fb)
9928{
9929 drm_framebuffer_cleanup(&fb->base);
9930 drm_gem_object_unreference_unlocked(&fb->obj->base);
9931}
9932
79e53945
JB		 9933static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9934{
9935 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9936
ddfe1567 9937 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9938 kfree(intel_fb);
9939}
9940
9941static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9942 struct drm_file *file,
79e53945
JB		 9943 unsigned int *handle)
9944{
9945 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9946 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9947
05394f39 9948 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9949}
9950
9951static const struct drm_framebuffer_funcs intel_fb_funcs = {
9952 .destroy = intel_user_framebuffer_destroy,
9953 .create_handle = intel_user_framebuffer_create_handle,
9954};
9955
38651674
DA		 9956int intel_framebuffer_init(struct drm_device *dev,
9957 struct intel_framebuffer *intel_fb,
308e5bcb 9958 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9959 struct drm_i915_gem_object *obj)
79e53945 9960{
a35cdaa0 9961 int pitch_limit;
79e53945
JB		 9962 int ret;
9963
c16ed4be
CW		 9964 if (obj->tiling_mode == I915_TILING_Y) {
9965 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9966 return -EINVAL;
c16ed4be 9967 }
57cd6508 9968
c16ed4be
CW		 9969 if (mode_cmd->pitches[0] & 63) {
9970 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9971 mode_cmd->pitches[0]);
57cd6508 9972 return -EINVAL;
c16ed4be 9973 }
57cd6508 9974
a35cdaa0
CW		 9975 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9976 pitch_limit = 32*1024;
9977 } else if (INTEL_INFO(dev)->gen >= 4) {
9978 if (obj->tiling_mode)
9979 pitch_limit = 16*1024;
9980 else
9981 pitch_limit = 32*1024;
9982 } else if (INTEL_INFO(dev)->gen >= 3) {
9983 if (obj->tiling_mode)
9984 pitch_limit = 8*1024;
9985 else
9986 pitch_limit = 16*1024;
9987 } else
9988 /* XXX DSPC is limited to 4k tiled */
9989 pitch_limit = 8*1024;
9990
9991 if (mode_cmd->pitches[0] > pitch_limit) {
9992 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9993 obj->tiling_mode ? "tiled" : "linear",
9994 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9995 return -EINVAL;
c16ed4be 9996 }
5d7bd705
VS		 9997
9998 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9999 mode_cmd->pitches[0] != obj->stride) {
10000 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10001 mode_cmd->pitches[0], obj->stride);
5d7bd705 10002 return -EINVAL;
c16ed4be 10003 }
5d7bd705 10004
57779d06 10005 /* Reject formats not supported by any plane early. */
308e5bcb 10006 switch (mode_cmd->pixel_format) {
57779d06 10007 case DRM_FORMAT_C8:
04b3924d
VS		 10008 case DRM_FORMAT_RGB565:
10009 case DRM_FORMAT_XRGB8888:
10010 case DRM_FORMAT_ARGB8888:
57779d06
VS		 10011 break;
10012 case DRM_FORMAT_XRGB1555:
10013 case DRM_FORMAT_ARGB1555:
c16ed4be 10014 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 10015 DRM_DEBUG("unsupported pixel format: %s\n",
10016 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10017 return -EINVAL;
c16ed4be 10018 }
57779d06
VS		 10019 break;
10020 case DRM_FORMAT_XBGR8888:
10021 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 10022 case DRM_FORMAT_XRGB2101010:
10023 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 10024 case DRM_FORMAT_XBGR2101010:
10025 case DRM_FORMAT_ABGR2101010:
c16ed4be 10026 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 10027 DRM_DEBUG("unsupported pixel format: %s\n",
10028 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10029 return -EINVAL;
c16ed4be 10030 }
b5626747 10031 break;
04b3924d
VS		 10032 case DRM_FORMAT_YUYV:
10033 case DRM_FORMAT_UYVY:
10034 case DRM_FORMAT_YVYU:
10035 case DRM_FORMAT_VYUY:
c16ed4be 10036 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 10037 DRM_DEBUG("unsupported pixel format: %s\n",
10038 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10039 return -EINVAL;
c16ed4be 10040 }
57cd6508
CW		 10041 break;
10042 default:
4ee62c76
VS		 10043 DRM_DEBUG("unsupported pixel format: %s\n",
10044 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 10045 return -EINVAL;
10046 }
10047
90f9a336
VS		 10048 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10049 if (mode_cmd->offsets[0] != 0)
10050 return -EINVAL;
10051
c7d73f6a
DV		 10052 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10053 intel_fb->obj = obj;
10054
79e53945
JB		 10055 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10056 if (ret) {
10057 DRM_ERROR("framebuffer init failed %d\n", ret);
10058 return ret;
10059 }
10060
79e53945
JB		 10061 return 0;
10062}
10063
79e53945
JB		 10064static struct drm_framebuffer *
10065intel_user_framebuffer_create(struct drm_device *dev,
10066 struct drm_file *filp,
308e5bcb 10067 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 10068{
05394f39 10069 struct drm_i915_gem_object *obj;
79e53945 10070
308e5bcb
JB		 10071 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10072 mode_cmd->handles[0]));
c8725226 10073 if (&obj->base == NULL)
cce13ff7 10074 return ERR_PTR(-ENOENT);
79e53945 10075
d2dff872 10076 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 10077}
10078
79e53945 10079static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 10080 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 10081 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 10082};
10083
e70236a8
JB		 10084/* Set up chip specific display functions */
10085static void intel_init_display(struct drm_device *dev)
10086{
10087 struct drm_i915_private *dev_priv = dev->dev_private;
10088
ee9300bb
DV		 10089 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10090 dev_priv->display.find_dpll = g4x_find_best_dpll;
10091 else if (IS_VALLEYVIEW(dev))
10092 dev_priv->display.find_dpll = vlv_find_best_dpll;
10093 else if (IS_PINEVIEW(dev))
10094 dev_priv->display.find_dpll = pnv_find_best_dpll;
10095 else
10096 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10097
affa9354 10098 if (HAS_DDI(dev)) {
0e8ffe1b 10099 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 10100 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 10101 dev_priv->display.crtc_enable = haswell_crtc_enable;
10102 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 10103 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 10104 dev_priv->display.update_plane = ironlake_update_plane;
10105 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 10106 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 10107 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 10108 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10109 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 10110 dev_priv->display.off = ironlake_crtc_off;
17638cd6 10111 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 10112 } else if (IS_VALLEYVIEW(dev)) {
10113 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10114 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10115 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10116 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10117 dev_priv->display.off = i9xx_crtc_off;
10118 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10119 } else {
0e8ffe1b 10120 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 10121 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 10122 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10123 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 10124 dev_priv->display.off = i9xx_crtc_off;
17638cd6 10125 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10126 }
e70236a8 10127
e70236a8 10128 /* Returns the core display clock speed */
25eb05fc
JB		 10129 if (IS_VALLEYVIEW(dev))
10130 dev_priv->display.get_display_clock_speed =
10131 valleyview_get_display_clock_speed;
10132 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 10133 dev_priv->display.get_display_clock_speed =
10134 i945_get_display_clock_speed;
10135 else if (IS_I915G(dev))
10136 dev_priv->display.get_display_clock_speed =
10137 i915_get_display_clock_speed;
257a7ffc 10138 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 10139 dev_priv->display.get_display_clock_speed =
10140 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 10141 else if (IS_PINEVIEW(dev))
10142 dev_priv->display.get_display_clock_speed =
10143 pnv_get_display_clock_speed;
e70236a8
JB		 10144 else if (IS_I915GM(dev))
10145 dev_priv->display.get_display_clock_speed =
10146 i915gm_get_display_clock_speed;
10147 else if (IS_I865G(dev))
10148 dev_priv->display.get_display_clock_speed =
10149 i865_get_display_clock_speed;
f0f8a9ce 10150 else if (IS_I85X(dev))
e70236a8
JB		 10151 dev_priv->display.get_display_clock_speed =
10152 i855_get_display_clock_speed;
10153 else /* 852, 830 */
10154 dev_priv->display.get_display_clock_speed =
10155 i830_get_display_clock_speed;
10156
7f8a8569 10157 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 10158 if (IS_GEN5(dev)) {
674cf967 10159 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 10160 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 10161 } else if (IS_GEN6(dev)) {
674cf967 10162 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 10163 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 10164 } else if (IS_IVYBRIDGE(dev)) {
10165 /* FIXME: detect B0+ stepping and use auto training */
10166 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 10167 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 10168 dev_priv->display.modeset_global_resources =
10169 ivb_modeset_global_resources;
c82e4d26
ED		 10170 } else if (IS_HASWELL(dev)) {
10171 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 10172 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 10173 dev_priv->display.modeset_global_resources =
10174 haswell_modeset_global_resources;
a0e63c22 10175 }
6067aaea 10176 } else if (IS_G4X(dev)) {
e0dac65e 10177 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 10178 }
8c9f3aaf
JB		 10179
10180 /* Default just returns -ENODEV to indicate unsupported */
10181 dev_priv->display.queue_flip = intel_default_queue_flip;
10182
10183 switch (INTEL_INFO(dev)->gen) {
10184 case 2:
10185 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10186 break;
10187
10188 case 3:
10189 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10190 break;
10191
10192 case 4:
10193 case 5:
10194 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10195 break;
10196
10197 case 6:
10198 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10199 break;
7c9017e5
JB		 10200 case 7:
10201 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10202 break;
8c9f3aaf 10203 }
e70236a8
JB		 10204}
10205
b690e96c
JB		 10206/*
10207 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10208 * resume, or other times. This quirk makes sure that's the case for
10209 * affected systems.
10210 */
0206e353 10211static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 10212{
10213 struct drm_i915_private *dev_priv = dev->dev_private;
10214
10215 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 10216 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 10217}
10218
435793df
KP		 10219/*
10220 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10221 */
10222static void quirk_ssc_force_disable(struct drm_device *dev)
10223{
10224 struct drm_i915_private *dev_priv = dev->dev_private;
10225 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 10226 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 10227}
10228
4dca20ef 10229/*
5a15ab5b
CE		 10230 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10231 * brightness value
4dca20ef
CE		 10232 */
10233static void quirk_invert_brightness(struct drm_device *dev)
10234{
10235 struct drm_i915_private *dev_priv = dev->dev_private;
10236 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 10237 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 10238}
10239
e85843be
KM		 10240/*
10241 * Some machines (Dell XPS13) suffer broken backlight controls if
10242 * BLM_PCH_PWM_ENABLE is set.
10243 */
10244static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10245{
10246 struct drm_i915_private *dev_priv = dev->dev_private;
10247 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10248 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10249}
10250
b690e96c
JB		 10251struct intel_quirk {
10252 int device;
10253 int subsystem_vendor;
10254 int subsystem_device;
10255 void (*hook)(struct drm_device *dev);
10256};
10257
5f85f176
EE		 10258/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10259struct intel_dmi_quirk {
10260 void (*hook)(struct drm_device *dev);
10261 const struct dmi_system_id (*dmi_id_list)[];
10262};
10263
10264static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10265{
10266 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10267 return 1;
10268}
10269
10270static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10271 {
10272 .dmi_id_list = &(const struct dmi_system_id[]) {
10273 {
10274 .callback = intel_dmi_reverse_brightness,
10275 .ident = "NCR Corporation",
10276 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10277 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10278 },
10279 },
10280 { } /* terminating entry */
10281 },
10282 .hook = quirk_invert_brightness,
10283 },
10284};
10285
c43b5634 10286static struct intel_quirk intel_quirks[] = {
b690e96c 10287 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10288 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10289
b690e96c
JB		 10290 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10291 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10292
b690e96c
JB		 10293 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10294 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10295
ccd0d36e 10296 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 10297 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 10298 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10299
10300 /* Lenovo U160 cannot use SSC on LVDS */
10301 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10302
10303 /* Sony Vaio Y cannot use SSC on LVDS */
10304 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 10305
ee1452d7
JN		 10306 /*
10307 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10308 * seem to use inverted backlight PWM.
10309 */
10310 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
e85843be
KM		 10311
10312 /* Dell XPS13 HD Sandy Bridge */
10313 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10314 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10315 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10316};
10317
10318static void intel_init_quirks(struct drm_device *dev)
10319{
10320 struct pci_dev *d = dev->pdev;
10321 int i;
10322
10323 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10324 struct intel_quirk *q = &intel_quirks[i];
10325
10326 if (d->device == q->device &&
10327 (d->subsystem_vendor == q->subsystem_vendor ||
10328 q->subsystem_vendor == PCI_ANY_ID) &&
10329 (d->subsystem_device == q->subsystem_device ||
10330 q->subsystem_device == PCI_ANY_ID))
10331 q->hook(dev);
10332 }
5f85f176
EE		 10333 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10334 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10335 intel_dmi_quirks[i].hook(dev);
10336 }
b690e96c
JB		 10337}
10338
9cce37f4
JB		 10339/* Disable the VGA plane that we never use */
10340static void i915_disable_vga(struct drm_device *dev)
10341{
10342 struct drm_i915_private *dev_priv = dev->dev_private;
10343 u8 sr1;
766aa1c4 10344 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10345
10346 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10347 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10348 sr1 = inb(VGA_SR_DATA);
10349 outb(sr1 | 1<<5, VGA_SR_DATA);
10350 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10351 udelay(300);
10352
10353 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10354 POSTING_READ(vga_reg);
10355}
10356
6e1b4fda 10357static void i915_enable_vga_mem(struct drm_device *dev)
81b5c7bc
AW		 10358{
10359 /* Enable VGA memory on Intel HD */
10360 if (HAS_PCH_SPLIT(dev)) {
10361 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10362 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10363 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10364 VGA_RSRC_LEGACY_MEM |
10365 VGA_RSRC_NORMAL_IO |
10366 VGA_RSRC_NORMAL_MEM);
10367 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10368 }
10369}
10370
6e1b4fda
VS		 10371void i915_disable_vga_mem(struct drm_device *dev)
10372{
10373 /* Disable VGA memory on Intel HD */
10374 if (HAS_PCH_SPLIT(dev)) {
10375 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10376 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10377 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10378 VGA_RSRC_NORMAL_IO |
10379 VGA_RSRC_NORMAL_MEM);
10380 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10381 }
10382}
10383
f817586c
DV		 10384void intel_modeset_init_hw(struct drm_device *dev)
10385{
f6071166
JB		 10386 struct drm_i915_private *dev_priv = dev->dev_private;
10387
a8f78b58
ED		 10388 intel_prepare_ddi(dev);
10389
f817586c
DV		 10390 intel_init_clock_gating(dev);
10391
f6071166
JB		 10392 /* Enable the CRI clock source so we can get at the display */
10393 if (IS_VALLEYVIEW(dev))
10394 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10395 DPLL_INTEGRATED_CRI_CLK_VLV);
10396
40e9cf64
JB		 10397 intel_init_dpio(dev);
10398
79f5b2c7 10399 mutex_lock(&dev->struct_mutex);
8090c6b9 10400 intel_enable_gt_powersave(dev);
79f5b2c7 10401 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10402}
10403
7d708ee4
ID		 10404void intel_modeset_suspend_hw(struct drm_device *dev)
10405{
10406 intel_suspend_hw(dev);
10407}
10408
79e53945
JB		 10409void intel_modeset_init(struct drm_device *dev)
10410{
652c393a 10411 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10412 int i, j, ret;
79e53945
JB		 10413
10414 drm_mode_config_init(dev);
10415
10416 dev->mode_config.min_width = 0;
10417 dev->mode_config.min_height = 0;
10418
019d96cb
DA		 10419 dev->mode_config.preferred_depth = 24;
10420 dev->mode_config.prefer_shadow = 1;
10421
e6ecefaa 10422 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10423
b690e96c
JB		 10424 intel_init_quirks(dev);
10425
1fa61106
ED		 10426 intel_init_pm(dev);
10427
e3c74757
BW		 10428 if (INTEL_INFO(dev)->num_pipes == 0)
10429 return;
10430
e70236a8
JB		 10431 intel_init_display(dev);
10432
a6c45cf0
CW		 10433 if (IS_GEN2(dev)) {
10434 dev->mode_config.max_width = 2048;
10435 dev->mode_config.max_height = 2048;
10436 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10437 dev->mode_config.max_width = 4096;
10438 dev->mode_config.max_height = 4096;
79e53945 10439 } else {
a6c45cf0
CW		 10440 dev->mode_config.max_width = 8192;
10441 dev->mode_config.max_height = 8192;
79e53945 10442 }
5d4545ae 10443 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10444
28c97730 10445 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10446 INTEL_INFO(dev)->num_pipes,
10447 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10448
08e2a7de 10449 for_each_pipe(i) {
79e53945 10450 intel_crtc_init(dev, i);
7f1f3851
JB		 10451 for (j = 0; j < dev_priv->num_plane; j++) {
10452 ret = intel_plane_init(dev, i, j);
10453 if (ret)
06da8da2
VS		 10454 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10455 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10456 }
79e53945
JB		 10457 }
10458
79f689aa 10459 intel_cpu_pll_init(dev);
e72f9fbf 10460 intel_shared_dpll_init(dev);
ee7b9f93 10461
9cce37f4
JB		 10462 /* Just disable it once at startup */
10463 i915_disable_vga(dev);
79e53945 10464 intel_setup_outputs(dev);
11be49eb
CW		 10465
10466 /* Just in case the BIOS is doing something questionable. */
10467 intel_disable_fbc(dev);
2c7111db
CW		 10468}
10469
24929352
DV		 10470static void
10471intel_connector_break_all_links(struct intel_connector *connector)
10472{
10473 connector->base.dpms = DRM_MODE_DPMS_OFF;
10474 connector->base.encoder = NULL;
10475 connector->encoder->connectors_active = false;
10476 connector->encoder->base.crtc = NULL;
10477}
10478
7fad798e
DV		 10479static void intel_enable_pipe_a(struct drm_device *dev)
10480{
10481 struct intel_connector *connector;
10482 struct drm_connector *crt = NULL;
10483 struct intel_load_detect_pipe load_detect_temp;
10484
10485 /* We can't just switch on the pipe A, we need to set things up with a
10486 * proper mode and output configuration. As a gross hack, enable pipe A
10487 * by enabling the load detect pipe once. */
10488 list_for_each_entry(connector,
10489 &dev->mode_config.connector_list,
10490 base.head) {
10491 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10492 crt = &connector->base;
10493 break;
10494 }
10495 }
10496
10497 if (!crt)
10498 return;
10499
10500 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10501 intel_release_load_detect_pipe(crt, &load_detect_temp);
10502
652c393a 10503
7fad798e
DV		 10504}
10505
fa555837
DV		 10506static bool
10507intel_check_plane_mapping(struct intel_crtc *crtc)
10508{
7eb552ae
BW		 10509 struct drm_device *dev = crtc->base.dev;
10510 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10511 u32 reg, val;
10512
7eb552ae 10513 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10514 return true;
10515
10516 reg = DSPCNTR(!crtc->plane);
10517 val = I915_READ(reg);
10518
10519 if ((val & DISPLAY_PLANE_ENABLE) &&
10520 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10521 return false;
10522
10523 return true;
10524}
10525
24929352
DV		 10526static void intel_sanitize_crtc(struct intel_crtc *crtc)
10527{
10528 struct drm_device *dev = crtc->base.dev;
10529 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10530 u32 reg;
24929352 10531
24929352 10532 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10533 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10534 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10535
10536 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10537 * disable the crtc (and hence change the state) if it is wrong. Note
10538 * that gen4+ has a fixed plane -> pipe mapping. */
10539 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10540 struct intel_connector *connector;
10541 bool plane;
10542
24929352
DV		 10543 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10544 crtc->base.base.id);
10545
10546 /* Pipe has the wrong plane attached and the plane is active.
10547 * Temporarily change the plane mapping and disable everything
10548 * ... */
10549 plane = crtc->plane;
10550 crtc->plane = !plane;
10551 dev_priv->display.crtc_disable(&crtc->base);
10552 crtc->plane = plane;
10553
10554 /* ... and break all links. */
10555 list_for_each_entry(connector, &dev->mode_config.connector_list,
10556 base.head) {
10557 if (connector->encoder->base.crtc != &crtc->base)
10558 continue;
10559
10560 intel_connector_break_all_links(connector);
10561 }
10562
10563 WARN_ON(crtc->active);
10564 crtc->base.enabled = false;
10565 }
24929352 10566
7fad798e
DV		 10567 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10568 crtc->pipe == PIPE_A && !crtc->active) {
10569 /* BIOS forgot to enable pipe A, this mostly happens after
10570 * resume. Force-enable the pipe to fix this, the update_dpms
10571 * call below we restore the pipe to the right state, but leave
10572 * the required bits on. */
10573 intel_enable_pipe_a(dev);
10574 }
10575
24929352
DV		 10576 /* Adjust the state of the output pipe according to whether we
10577 * have active connectors/encoders. */
10578 intel_crtc_update_dpms(&crtc->base);
10579
10580 if (crtc->active != crtc->base.enabled) {
10581 struct intel_encoder *encoder;
10582
10583 /* This can happen either due to bugs in the get_hw_state
10584 * functions or because the pipe is force-enabled due to the
10585 * pipe A quirk. */
10586 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10587 crtc->base.base.id,
10588 crtc->base.enabled ? "enabled" : "disabled",
10589 crtc->active ? "enabled" : "disabled");
10590
10591 crtc->base.enabled = crtc->active;
10592
10593 /* Because we only establish the connector -> encoder ->
10594 * crtc links if something is active, this means the
10595 * crtc is now deactivated. Break the links. connector
10596 * -> encoder links are only establish when things are
10597 * actually up, hence no need to break them. */
10598 WARN_ON(crtc->active);
10599
10600 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10601 WARN_ON(encoder->connectors_active);
10602 encoder->base.crtc = NULL;
10603 }
10604 }
10605}
10606
10607static void intel_sanitize_encoder(struct intel_encoder *encoder)
10608{
10609 struct intel_connector *connector;
10610 struct drm_device *dev = encoder->base.dev;
10611
10612 /* We need to check both for a crtc link (meaning that the
10613 * encoder is active and trying to read from a pipe) and the
10614 * pipe itself being active. */
10615 bool has_active_crtc = encoder->base.crtc &&
10616 to_intel_crtc(encoder->base.crtc)->active;
10617
10618 if (encoder->connectors_active && !has_active_crtc) {
10619 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10620 encoder->base.base.id,
10621 drm_get_encoder_name(&encoder->base));
10622
10623 /* Connector is active, but has no active pipe. This is
10624 * fallout from our resume register restoring. Disable
10625 * the encoder manually again. */
10626 if (encoder->base.crtc) {
10627 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10628 encoder->base.base.id,
10629 drm_get_encoder_name(&encoder->base));
10630 encoder->disable(encoder);
10631 }
10632
10633 /* Inconsistent output/port/pipe state happens presumably due to
10634 * a bug in one of the get_hw_state functions. Or someplace else
10635 * in our code, like the register restore mess on resume. Clamp
10636 * things to off as a safer default. */
10637 list_for_each_entry(connector,
10638 &dev->mode_config.connector_list,
10639 base.head) {
10640 if (connector->encoder != encoder)
10641 continue;
10642
10643 intel_connector_break_all_links(connector);
10644 }
10645 }
10646 /* Enabled encoders without active connectors will be fixed in
10647 * the crtc fixup. */
10648}
10649
44cec740 10650void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10651{
10652 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10653 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10654
8dc8a27c
PZ		 10655 /* This function can be called both from intel_modeset_setup_hw_state or
10656 * at a very early point in our resume sequence, where the power well
10657 * structures are not yet restored. Since this function is at a very
10658 * paranoid "someone might have enabled VGA while we were not looking"
10659 * level, just check if the power well is enabled instead of trying to
10660 * follow the "don't touch the power well if we don't need it" policy
10661 * the rest of the driver uses. */
10662 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10663 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10664 return;
10665
e1553faa 10666 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
0fde901f 10667 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10668 i915_disable_vga(dev);
6e1b4fda 10669 i915_disable_vga_mem(dev);
0fde901f
KM		 10670 }
10671}
10672
30e984df 10673static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10674{
10675 struct drm_i915_private *dev_priv = dev->dev_private;
10676 enum pipe pipe;
24929352
DV		 10677 struct intel_crtc *crtc;
10678 struct intel_encoder *encoder;
10679 struct intel_connector *connector;
5358901f 10680 int i;
24929352 10681
0e8ffe1b
DV		 10682 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10683 base.head) {
88adfff1 10684 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10685
0e8ffe1b
DV		 10686 crtc->active = dev_priv->display.get_pipe_config(crtc,
10687 &crtc->config);
24929352
DV		 10688
10689 crtc->base.enabled = crtc->active;
10690
10691 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10692 crtc->base.base.id,
10693 crtc->active ? "enabled" : "disabled");
10694 }
10695
5358901f 10696 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10697 if (HAS_DDI(dev))
6441ab5f
PZ		 10698 intel_ddi_setup_hw_pll_state(dev);
10699
5358901f
DV		 10700 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10701 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10702
10703 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10704 pll->active = 0;
10705 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10706 base.head) {
10707 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10708 pll->active++;
10709 }
10710 pll->refcount = pll->active;
10711
35c95375
DV		 10712 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10713 pll->name, pll->refcount, pll->on);
5358901f
DV		 10714 }
10715
24929352
DV		 10716 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10717 base.head) {
10718 pipe = 0;
10719
10720 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10721 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10722 encoder->base.crtc = &crtc->base;
510d5f2f 10723 if (encoder->get_config)
045ac3b5 10724 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10725 } else {
10726 encoder->base.crtc = NULL;
10727 }
10728
10729 encoder->connectors_active = false;
10730 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10731 encoder->base.base.id,
10732 drm_get_encoder_name(&encoder->base),
10733 encoder->base.crtc ? "enabled" : "disabled",
10734 pipe);
10735 }
10736
10737 list_for_each_entry(connector, &dev->mode_config.connector_list,
10738 base.head) {
10739 if (connector->get_hw_state(connector)) {
10740 connector->base.dpms = DRM_MODE_DPMS_ON;
10741 connector->encoder->connectors_active = true;
10742 connector->base.encoder = &connector->encoder->base;
10743 } else {
10744 connector->base.dpms = DRM_MODE_DPMS_OFF;
10745 connector->base.encoder = NULL;
10746 }
10747 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10748 connector->base.base.id,
10749 drm_get_connector_name(&connector->base),
10750 connector->base.encoder ? "enabled" : "disabled");
10751 }
30e984df
DV		 10752}
10753
10754/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10755 * and i915 state tracking structures. */
10756void intel_modeset_setup_hw_state(struct drm_device *dev,
10757 bool force_restore)
10758{
10759 struct drm_i915_private *dev_priv = dev->dev_private;
10760 enum pipe pipe;
30e984df
DV		 10761 struct intel_crtc *crtc;
10762 struct intel_encoder *encoder;
35c95375 10763 int i;
30e984df
DV		 10764
10765 intel_modeset_readout_hw_state(dev);
24929352 10766
babea61d
JB		 10767 /*
10768 * Now that we have the config, copy it to each CRTC struct
10769 * Note that this could go away if we move to using crtc_config
10770 * checking everywhere.
10771 */
10772 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10773 base.head) {
10774 if (crtc->active && i915_fastboot) {
10775 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10776
10777 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10778 crtc->base.base.id);
10779 drm_mode_debug_printmodeline(&crtc->base.mode);
10780 }
10781 }
10782
24929352
DV		 10783 /* HW state is read out, now we need to sanitize this mess. */
10784 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10785 base.head) {
10786 intel_sanitize_encoder(encoder);
10787 }
10788
10789 for_each_pipe(pipe) {
10790 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10791 intel_sanitize_crtc(crtc);
c0b03411 10792 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10793 }
9a935856 10794
35c95375
DV		 10795 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10796 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10797
10798 if (!pll->on || pll->active)
10799 continue;
10800
10801 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10802
10803 pll->disable(dev_priv, pll);
10804 pll->on = false;
10805 }
10806
45e2b5f6 10807 if (force_restore) {
7d0bc1ea
VS		 10808 i915_redisable_vga(dev);
10809
f30da187
DV		 10810 /*
10811 * We need to use raw interfaces for restoring state to avoid
10812 * checking (bogus) intermediate states.
10813 */
45e2b5f6 10814 for_each_pipe(pipe) {
b5644d05
JB		 10815 struct drm_crtc *crtc =
10816 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10817
10818 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10819 crtc->fb);
45e2b5f6
DV		 10820 }
10821 } else {
10822 intel_modeset_update_staged_output_state(dev);
10823 }
8af6cf88
DV		 10824
10825 intel_modeset_check_state(dev);
2e938892
DV		 10826
10827 drm_mode_config_reset(dev);
2c7111db
CW		 10828}
10829
10830void intel_modeset_gem_init(struct drm_device *dev)
10831{
1833b134 10832 intel_modeset_init_hw(dev);
02e792fb
DV		 10833
10834 intel_setup_overlay(dev);
24929352 10835
45e2b5f6 10836 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10837}
10838
10839void intel_modeset_cleanup(struct drm_device *dev)
10840{
652c393a
JB		 10841 struct drm_i915_private *dev_priv = dev->dev_private;
10842 struct drm_crtc *crtc;
d9255d57 10843 struct drm_connector *connector;
652c393a 10844
fd0c0642
DV		 10845 /*
10846 * Interrupts and polling as the first thing to avoid creating havoc.
10847 * Too much stuff here (turning of rps, connectors, ...) would
10848 * experience fancy races otherwise.
10849 */
10850 drm_irq_uninstall(dev);
10851 cancel_work_sync(&dev_priv->hotplug_work);
10852 /*
10853 * Due to the hpd irq storm handling the hotplug work can re-arm the
10854 * poll handlers. Hence disable polling after hpd handling is shut down.
10855 */
f87ea761 10856 drm_kms_helper_poll_fini(dev);
fd0c0642 10857
652c393a
JB		 10858 mutex_lock(&dev->struct_mutex);
10859
723bfd70
JB		 10860 intel_unregister_dsm_handler();
10861
652c393a
JB		 10862 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10863 /* Skip inactive CRTCs */
10864 if (!crtc->fb)
10865 continue;
10866
3dec0095 10867 intel_increase_pllclock(crtc);
652c393a
JB		 10868 }
10869
973d04f9 10870 intel_disable_fbc(dev);
e70236a8 10871
6e1b4fda 10872 i915_enable_vga_mem(dev);
81b5c7bc 10873
8090c6b9 10874 intel_disable_gt_powersave(dev);
0cdab21f 10875
930ebb46
DV		 10876 ironlake_teardown_rc6(dev);
10877
69341a5e
KH		 10878 mutex_unlock(&dev->struct_mutex);
10879
1630fe75
CW		 10880 /* flush any delayed tasks or pending work */
10881 flush_scheduled_work();
10882
dc652f90
JN		 10883 /* destroy backlight, if any, before the connectors */
10884 intel_panel_destroy_backlight(dev);
10885
d9255d57
PZ		 10886 /* destroy the sysfs files before encoders/connectors */
10887 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
10888 drm_sysfs_connector_remove(connector);
10889
79e53945 10890 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10891
10892 intel_cleanup_overlay(dev);
79e53945
JB		 10893}
10894
f1c79df3
ZW		 10895/*
10896 * Return which encoder is currently attached for connector.
10897 */
df0e9248 10898struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10899{
df0e9248
CW		 10900 return &intel_attached_encoder(connector)->base;
10901}
f1c79df3 10902
df0e9248
CW		 10903void intel_connector_attach_encoder(struct intel_connector *connector,
10904 struct intel_encoder *encoder)
10905{
10906 connector->encoder = encoder;
10907 drm_mode_connector_attach_encoder(&connector->base,
10908 &encoder->base);
79e53945 10909}
28d52043
DA		 10910
10911/*
10912 * set vga decode state - true == enable VGA decode
10913 */
10914int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10915{
10916 struct drm_i915_private *dev_priv = dev->dev_private;
10917 u16 gmch_ctrl;
10918
10919 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10920 if (state)
10921 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10922 else
10923 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10924 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10925 return 0;
10926}
c4a1d9e4 10927
c4a1d9e4 10928struct intel_display_error_state {
ff57f1b0
PZ		 10929
10930 u32 power_well_driver;
10931
63b66e5b
CW		 10932 int num_transcoders;
10933
c4a1d9e4
CW		 10934 struct intel_cursor_error_state {
10935 u32 control;
10936 u32 position;
10937 u32 base;
10938 u32 size;
52331309 10939 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10940
10941 struct intel_pipe_error_state {
c4a1d9e4 10942 u32 source;
52331309 10943 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10944
10945 struct intel_plane_error_state {
10946 u32 control;
10947 u32 stride;
10948 u32 size;
10949 u32 pos;
10950 u32 addr;
10951 u32 surface;
10952 u32 tile_offset;
52331309 10953 } plane[I915_MAX_PIPES];
63b66e5b
CW		 10954
10955 struct intel_transcoder_error_state {
10956 enum transcoder cpu_transcoder;
10957
10958 u32 conf;
10959
10960 u32 htotal;
10961 u32 hblank;
10962 u32 hsync;
10963 u32 vtotal;
10964 u32 vblank;
10965 u32 vsync;
10966 } transcoder[4];
c4a1d9e4
CW		 10967};
10968
10969struct intel_display_error_state *
10970intel_display_capture_error_state(struct drm_device *dev)
10971{
0206e353 10972 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10973 struct intel_display_error_state *error;
63b66e5b
CW		 10974 int transcoders[] = {
10975 TRANSCODER_A,
10976 TRANSCODER_B,
10977 TRANSCODER_C,
10978 TRANSCODER_EDP,
10979 };
c4a1d9e4
CW		 10980 int i;
10981
63b66e5b
CW		 10982 if (INTEL_INFO(dev)->num_pipes == 0)
10983 return NULL;
10984
c4a1d9e4
CW		 10985 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10986 if (error == NULL)
10987 return NULL;
10988
ff57f1b0
PZ		 10989 if (HAS_POWER_WELL(dev))
10990 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10991
52331309 10992 for_each_pipe(i) {
a18c4c3d
PZ		 10993 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10994 error->cursor[i].control = I915_READ(CURCNTR(i));
10995 error->cursor[i].position = I915_READ(CURPOS(i));
10996 error->cursor[i].base = I915_READ(CURBASE(i));
10997 } else {
10998 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10999 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11000 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11001 }
c4a1d9e4
CW		 11002
11003 error->plane[i].control = I915_READ(DSPCNTR(i));
11004 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 11005 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 11006 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 11007 error->plane[i].pos = I915_READ(DSPPOS(i));
11008 }
ca291363
PZ		 11009 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11010 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 11011 if (INTEL_INFO(dev)->gen >= 4) {
11012 error->plane[i].surface = I915_READ(DSPSURF(i));
11013 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11014 }
11015
c4a1d9e4 11016 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 11017 }
11018
11019 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11020 if (HAS_DDI(dev_priv->dev))
11021 error->num_transcoders++; /* Account for eDP. */
11022
11023 for (i = 0; i < error->num_transcoders; i++) {
11024 enum transcoder cpu_transcoder = transcoders[i];
11025
11026 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11027
11028 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11029 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11030 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11031 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11032 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11033 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11034 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 11035 }
11036
12d217c7
PZ		 11037 /* In the code above we read the registers without checking if the power
11038 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
11039 * prevent the next I915_WRITE from detecting it and printing an error
11040 * message. */
907b28c5 11041 intel_uncore_clear_errors(dev);
12d217c7 11042
c4a1d9e4
CW		 11043 return error;
11044}
11045
edc3d884
MK		 11046#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11047
c4a1d9e4 11048void
edc3d884 11049intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 11050 struct drm_device *dev,
11051 struct intel_display_error_state *error)
11052{
11053 int i;
11054
63b66e5b
CW		 11055 if (!error)
11056 return;
11057
edc3d884 11058 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 11059 if (HAS_POWER_WELL(dev))
edc3d884 11060 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 11061 error->power_well_driver);
52331309 11062 for_each_pipe(i) {
edc3d884 11063 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 11064 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 11065
11066 err_printf(m, "Plane [%d]:\n", i);
11067 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
11068 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 11069 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 11070 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
11071 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 11072 }
4b71a570 11073 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 11074 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 11075 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 11076 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
11077 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 11078 }
11079
edc3d884
MK		 11080 err_printf(m, "Cursor [%d]:\n", i);
11081 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
11082 err_printf(m, " POS: %08x\n", error->cursor[i].position);
11083 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 11084 }
63b66e5b
CW		 11085
11086 for (i = 0; i < error->num_transcoders; i++) {
11087 err_printf(m, " CPU transcoder: %c\n",
11088 transcoder_name(error->transcoder[i].cpu_transcoder));
11089 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
11090 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
11091 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
11092 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
11093 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
11094 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
11095 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
11096 }
c4a1d9e4 11097}
Linux kernel - Deliverables
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