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drm/i915: Dump some DPLL fields in pipe config debug
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c
MR		 48/* Primary plane formats supported by all gen */
49#define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55/* Primary plane formats for gen <= 3 */
568db4f2 56static const uint32_t i8xx_primary_formats[] = {
465c120c
MR		 57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60};
61
62/* Primary plane formats for gen >= 4 */
568db4f2 63static const uint32_t i965_primary_formats[] = {
465c120c
MR		 64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71};
72
3d7d6510
MR		 73/* Cursor formats */
74static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76};
77
6b383a7f 78static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 79
f1f644dc 80static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 81 struct intel_crtc_state *pipe_config);
18442d08 82static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 83 struct intel_crtc_state *pipe_config);
f1f644dc 84
8c7b5ccb 85static int intel_set_mode(struct drm_crtc *crtc,
83a57153 86 struct drm_atomic_state *state);
eb1bfe80
JB		 87static int intel_framebuffer_init(struct drm_device *dev,
88 struct intel_framebuffer *ifb,
89 struct drm_mode_fb_cmd2 *mode_cmd,
90 struct drm_i915_gem_object *obj);
5b18e57c
DV		 91static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
92static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 93static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 94 struct intel_link_m_n *m_n,
95 struct intel_link_m_n *m2_n2);
29407aab 96static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 97static void haswell_set_pipeconf(struct drm_crtc *crtc);
98static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 99static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 100 const struct intel_crtc_state *pipe_config);
d288f65f 101static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 102 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 103static void intel_begin_crtc_commit(struct drm_crtc *crtc);
104static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 105static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
106 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 107static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
108 int num_connectors);
ce22dba9
ML		 109static void intel_crtc_enable_planes(struct drm_crtc *crtc);
110static void intel_crtc_disable_planes(struct drm_crtc *crtc);
e7457a9a 111
0e32b39c
DA		 112static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
113{
114 if (!connector->mst_port)
115 return connector->encoder;
116 else
117 return &connector->mst_port->mst_encoders[pipe]->base;
118}
119
79e53945 120typedef struct {
0206e353 121 int min, max;
79e53945
JB		 122} intel_range_t;
123
124typedef struct {
0206e353
AJ		 125 int dot_limit;
126 int p2_slow, p2_fast;
79e53945
JB		 127} intel_p2_t;
128
d4906093
ML		 129typedef struct intel_limit intel_limit_t;
130struct intel_limit {
0206e353
AJ		 131 intel_range_t dot, vco, n, m, m1, m2, p, p1;
132 intel_p2_t p2;
d4906093 133};
79e53945 134
d2acd215
DV		 135int
136intel_pch_rawclk(struct drm_device *dev)
137{
138 struct drm_i915_private *dev_priv = dev->dev_private;
139
140 WARN_ON(!HAS_PCH_SPLIT(dev));
141
142 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
143}
144
021357ac
CW		 145static inline u32 /* units of 100MHz */
146intel_fdi_link_freq(struct drm_device *dev)
147{
8b99e68c
CW		 148 if (IS_GEN5(dev)) {
149 struct drm_i915_private *dev_priv = dev->dev_private;
150 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
151 } else
152 return 27;
021357ac
CW		 153}
154
5d536e28 155static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 156 .dot = { .min = 25000, .max = 350000 },
9c333719 157 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 158 .n = { .min = 2, .max = 16 },
0206e353
AJ		 159 .m = { .min = 96, .max = 140 },
160 .m1 = { .min = 18, .max = 26 },
161 .m2 = { .min = 6, .max = 16 },
162 .p = { .min = 4, .max = 128 },
163 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 166};
167
5d536e28
DV		 168static const intel_limit_t intel_limits_i8xx_dvo = {
169 .dot = { .min = 25000, .max = 350000 },
9c333719 170 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 171 .n = { .min = 2, .max = 16 },
5d536e28
DV		 172 .m = { .min = 96, .max = 140 },
173 .m1 = { .min = 18, .max = 26 },
174 .m2 = { .min = 6, .max = 16 },
175 .p = { .min = 4, .max = 128 },
176 .p1 = { .min = 2, .max = 33 },
177 .p2 = { .dot_limit = 165000,
178 .p2_slow = 4, .p2_fast = 4 },
179};
180
e4b36699 181static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 182 .dot = { .min = 25000, .max = 350000 },
9c333719 183 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 184 .n = { .min = 2, .max = 16 },
0206e353
AJ		 185 .m = { .min = 96, .max = 140 },
186 .m1 = { .min = 18, .max = 26 },
187 .m2 = { .min = 6, .max = 16 },
188 .p = { .min = 4, .max = 128 },
189 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 190 .p2 = { .dot_limit = 165000,
191 .p2_slow = 14, .p2_fast = 7 },
e4b36699 192};
273e27ca 193
e4b36699 194static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 195 .dot = { .min = 20000, .max = 400000 },
196 .vco = { .min = 1400000, .max = 2800000 },
197 .n = { .min = 1, .max = 6 },
198 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 199 .m1 = { .min = 8, .max = 18 },
200 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 201 .p = { .min = 5, .max = 80 },
202 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 203 .p2 = { .dot_limit = 200000,
204 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 205};
206
207static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 208 .dot = { .min = 20000, .max = 400000 },
209 .vco = { .min = 1400000, .max = 2800000 },
210 .n = { .min = 1, .max = 6 },
211 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 212 .m1 = { .min = 8, .max = 18 },
213 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 214 .p = { .min = 7, .max = 98 },
215 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 216 .p2 = { .dot_limit = 112000,
217 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 218};
219
273e27ca 220
e4b36699 221static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 222 .dot = { .min = 25000, .max = 270000 },
223 .vco = { .min = 1750000, .max = 3500000},
224 .n = { .min = 1, .max = 4 },
225 .m = { .min = 104, .max = 138 },
226 .m1 = { .min = 17, .max = 23 },
227 .m2 = { .min = 5, .max = 11 },
228 .p = { .min = 10, .max = 30 },
229 .p1 = { .min = 1, .max = 3},
230 .p2 = { .dot_limit = 270000,
231 .p2_slow = 10,
232 .p2_fast = 10
044c7c41 233 },
e4b36699
KP		 234};
235
236static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 237 .dot = { .min = 22000, .max = 400000 },
238 .vco = { .min = 1750000, .max = 3500000},
239 .n = { .min = 1, .max = 4 },
240 .m = { .min = 104, .max = 138 },
241 .m1 = { .min = 16, .max = 23 },
242 .m2 = { .min = 5, .max = 11 },
243 .p = { .min = 5, .max = 80 },
244 .p1 = { .min = 1, .max = 8},
245 .p2 = { .dot_limit = 165000,
246 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 247};
248
249static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 250 .dot = { .min = 20000, .max = 115000 },
251 .vco = { .min = 1750000, .max = 3500000 },
252 .n = { .min = 1, .max = 3 },
253 .m = { .min = 104, .max = 138 },
254 .m1 = { .min = 17, .max = 23 },
255 .m2 = { .min = 5, .max = 11 },
256 .p = { .min = 28, .max = 112 },
257 .p1 = { .min = 2, .max = 8 },
258 .p2 = { .dot_limit = 0,
259 .p2_slow = 14, .p2_fast = 14
044c7c41 260 },
e4b36699
KP		 261};
262
263static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 264 .dot = { .min = 80000, .max = 224000 },
265 .vco = { .min = 1750000, .max = 3500000 },
266 .n = { .min = 1, .max = 3 },
267 .m = { .min = 104, .max = 138 },
268 .m1 = { .min = 17, .max = 23 },
269 .m2 = { .min = 5, .max = 11 },
270 .p = { .min = 14, .max = 42 },
271 .p1 = { .min = 2, .max = 6 },
272 .p2 = { .dot_limit = 0,
273 .p2_slow = 7, .p2_fast = 7
044c7c41 274 },
e4b36699
KP		 275};
276
f2b115e6 277static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 278 .dot = { .min = 20000, .max = 400000},
279 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 280 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 281 .n = { .min = 3, .max = 6 },
282 .m = { .min = 2, .max = 256 },
273e27ca 283 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 284 .m1 = { .min = 0, .max = 0 },
285 .m2 = { .min = 0, .max = 254 },
286 .p = { .min = 5, .max = 80 },
287 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 288 .p2 = { .dot_limit = 200000,
289 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 290};
291
f2b115e6 292static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 293 .dot = { .min = 20000, .max = 400000 },
294 .vco = { .min = 1700000, .max = 3500000 },
295 .n = { .min = 3, .max = 6 },
296 .m = { .min = 2, .max = 256 },
297 .m1 = { .min = 0, .max = 0 },
298 .m2 = { .min = 0, .max = 254 },
299 .p = { .min = 7, .max = 112 },
300 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 301 .p2 = { .dot_limit = 112000,
302 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 303};
304
273e27ca
EA		 305/* Ironlake / Sandybridge
306 *
307 * We calculate clock using (register_value + 2) for N/M1/M2, so here
308 * the range value for them is (actual_value - 2).
309 */
b91ad0ec 310static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 5 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 5, .max = 80 },
318 .p1 = { .min = 1, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 321};
322
b91ad0ec 323static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 324 .dot = { .min = 25000, .max = 350000 },
325 .vco = { .min = 1760000, .max = 3510000 },
326 .n = { .min = 1, .max = 3 },
327 .m = { .min = 79, .max = 118 },
328 .m1 = { .min = 12, .max = 22 },
329 .m2 = { .min = 5, .max = 9 },
330 .p = { .min = 28, .max = 112 },
331 .p1 = { .min = 2, .max = 8 },
332 .p2 = { .dot_limit = 225000,
333 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 334};
335
336static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 337 .dot = { .min = 25000, .max = 350000 },
338 .vco = { .min = 1760000, .max = 3510000 },
339 .n = { .min = 1, .max = 3 },
340 .m = { .min = 79, .max = 127 },
341 .m1 = { .min = 12, .max = 22 },
342 .m2 = { .min = 5, .max = 9 },
343 .p = { .min = 14, .max = 56 },
344 .p1 = { .min = 2, .max = 8 },
345 .p2 = { .dot_limit = 225000,
346 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 347};
348
273e27ca 349/* LVDS 100mhz refclk limits. */
b91ad0ec 350static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 351 .dot = { .min = 25000, .max = 350000 },
352 .vco = { .min = 1760000, .max = 3510000 },
353 .n = { .min = 1, .max = 2 },
354 .m = { .min = 79, .max = 126 },
355 .m1 = { .min = 12, .max = 22 },
356 .m2 = { .min = 5, .max = 9 },
357 .p = { .min = 28, .max = 112 },
0206e353 358 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 359 .p2 = { .dot_limit = 225000,
360 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 361};
362
363static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 364 .dot = { .min = 25000, .max = 350000 },
365 .vco = { .min = 1760000, .max = 3510000 },
366 .n = { .min = 1, .max = 3 },
367 .m = { .min = 79, .max = 126 },
368 .m1 = { .min = 12, .max = 22 },
369 .m2 = { .min = 5, .max = 9 },
370 .p = { .min = 14, .max = 42 },
0206e353 371 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 372 .p2 = { .dot_limit = 225000,
373 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 374};
375
dc730512 376static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 377 /*
378 * These are the data rate limits (measured in fast clocks)
379 * since those are the strictest limits we have. The fast
380 * clock and actual rate limits are more relaxed, so checking
381 * them would make no difference.
382 */
383 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 384 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 385 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
b99ab663 388 .p1 = { .min = 2, .max = 3 },
5fdc9c49 389 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 390};
391
ef9348c8
CML		 392static const intel_limit_t intel_limits_chv = {
393 /*
394 * These are the data rate limits (measured in fast clocks)
395 * since those are the strictest limits we have. The fast
396 * clock and actual rate limits are more relaxed, so checking
397 * them would make no difference.
398 */
399 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 400 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 401 .n = { .min = 1, .max = 1 },
402 .m1 = { .min = 2, .max = 2 },
403 .m2 = { .min = 24 << 22, .max = 175 << 22 },
404 .p1 = { .min = 2, .max = 4 },
405 .p2 = { .p2_slow = 1, .p2_fast = 14 },
406};
407
5ab7b0b7
ID		 408static const intel_limit_t intel_limits_bxt = {
409 /* FIXME: find real dot limits */
410 .dot = { .min = 0, .max = INT_MAX },
411 .vco = { .min = 4800000, .max = 6480000 },
412 .n = { .min = 1, .max = 1 },
413 .m1 = { .min = 2, .max = 2 },
414 /* FIXME: find real m2 limits */
415 .m2 = { .min = 2 << 22, .max = 255 << 22 },
416 .p1 = { .min = 2, .max = 4 },
417 .p2 = { .p2_slow = 1, .p2_fast = 20 },
418};
419
6b4bf1c4
VS		 420static void vlv_clock(int refclk, intel_clock_t *clock)
421{
422 clock->m = clock->m1 * clock->m2;
423 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 424 if (WARN_ON(clock->n == 0 || clock->p == 0))
425 return;
fb03ac01
VS		 426 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
427 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 428}
429
e0638cdf
PZ		 430/**
431 * Returns whether any output on the specified pipe is of the specified type
432 */
4093561b 433bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 434{
409ee761 435 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 436 struct intel_encoder *encoder;
437
409ee761 438 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 439 if (encoder->type == type)
440 return true;
441
442 return false;
443}
444
d0737e1d
ACO		 445/**
446 * Returns whether any output on the specified pipe will have the specified
447 * type after a staged modeset is complete, i.e., the same as
448 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
449 * encoder->crtc.
450 */
a93e255f
ACO		 451static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
452 int type)
d0737e1d 453{
a93e255f 454 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 455 struct drm_connector *connector;
a93e255f 456 struct drm_connector_state *connector_state;
d0737e1d 457 struct intel_encoder *encoder;
a93e255f
ACO		 458 int i, num_connectors = 0;
459
da3ced29 460 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 461 if (connector_state->crtc != crtc_state->base.crtc)
462 continue;
463
464 num_connectors++;
d0737e1d 465
a93e255f
ACO		 466 encoder = to_intel_encoder(connector_state->best_encoder);
467 if (encoder->type == type)
d0737e1d 468 return true;
a93e255f
ACO		 469 }
470
471 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 472
473 return false;
474}
475
a93e255f
ACO		 476static const intel_limit_t *
477intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 478{
a93e255f 479 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 480 const intel_limit_t *limit;
b91ad0ec 481
a93e255f 482 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 483 if (intel_is_dual_link_lvds(dev)) {
1b894b59 484 if (refclk == 100000)
b91ad0ec
ZW		 485 limit = &intel_limits_ironlake_dual_lvds_100m;
486 else
487 limit = &intel_limits_ironlake_dual_lvds;
488 } else {
1b894b59 489 if (refclk == 100000)
b91ad0ec
ZW		 490 limit = &intel_limits_ironlake_single_lvds_100m;
491 else
492 limit = &intel_limits_ironlake_single_lvds;
493 }
c6bb3538 494 } else
b91ad0ec 495 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 496
497 return limit;
498}
499
a93e255f
ACO		 500static const intel_limit_t *
501intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 502{
a93e255f 503 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 504 const intel_limit_t *limit;
505
a93e255f 506 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 507 if (intel_is_dual_link_lvds(dev))
e4b36699 508 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 509 else
e4b36699 510 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 511 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
512 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 513 limit = &intel_limits_g4x_hdmi;
a93e255f 514 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 515 limit = &intel_limits_g4x_sdvo;
044c7c41 516 } else /* The option is for other outputs */
e4b36699 517 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 518
519 return limit;
520}
521
a93e255f
ACO		 522static const intel_limit_t *
523intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 524{
a93e255f 525 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 526 const intel_limit_t *limit;
527
5ab7b0b7
ID		 528 if (IS_BROXTON(dev))
529 limit = &intel_limits_bxt;
530 else if (HAS_PCH_SPLIT(dev))
a93e255f 531 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 532 else if (IS_G4X(dev)) {
a93e255f 533 limit = intel_g4x_limit(crtc_state);
f2b115e6 534 } else if (IS_PINEVIEW(dev)) {
a93e255f 535 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 536 limit = &intel_limits_pineview_lvds;
2177832f 537 else
f2b115e6 538 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 539 } else if (IS_CHERRYVIEW(dev)) {
540 limit = &intel_limits_chv;
a0c4da24 541 } else if (IS_VALLEYVIEW(dev)) {
dc730512 542 limit = &intel_limits_vlv;
a6c45cf0 543 } else if (!IS_GEN2(dev)) {
a93e255f 544 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 545 limit = &intel_limits_i9xx_lvds;
546 else
547 limit = &intel_limits_i9xx_sdvo;
79e53945 548 } else {
a93e255f 549 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 550 limit = &intel_limits_i8xx_lvds;
a93e255f 551 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 552 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 553 else
554 limit = &intel_limits_i8xx_dac;
79e53945
JB		 555 }
556 return limit;
557}
558
f2b115e6
AJ		 559/* m1 is reserved as 0 in Pineview, n is a ring counter */
560static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 561{
2177832f
SL		 562 clock->m = clock->m2 + 2;
563 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 564 if (WARN_ON(clock->n == 0 || clock->p == 0))
565 return;
fb03ac01
VS		 566 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
567 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 568}
569
7429e9d4
DV		 570static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
571{
572 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
573}
574
ac58c3f0 575static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 576{
7429e9d4 577 clock->m = i9xx_dpll_compute_m(clock);
79e53945 578 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 579 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
580 return;
fb03ac01
VS		 581 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
582 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 583}
584
ef9348c8
CML		 585static void chv_clock(int refclk, intel_clock_t *clock)
586{
587 clock->m = clock->m1 * clock->m2;
588 clock->p = clock->p1 * clock->p2;
589 if (WARN_ON(clock->n == 0 || clock->p == 0))
590 return;
591 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
592 clock->n << 22);
593 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
594}
595
7c04d1d9 596#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 597/**
598 * Returns whether the given set of divisors are valid for a given refclk with
599 * the given connectors.
600 */
601
1b894b59
CW		 602static bool intel_PLL_is_valid(struct drm_device *dev,
603 const intel_limit_t *limit,
604 const intel_clock_t *clock)
79e53945 605{
f01b7962
VS		 606 if (clock->n < limit->n.min || limit->n.max < clock->n)
607 INTELPllInvalid("n out of range\n");
79e53945 608 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 609 INTELPllInvalid("p1 out of range\n");
79e53945 610 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 611 INTELPllInvalid("m2 out of range\n");
79e53945 612 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 613 INTELPllInvalid("m1 out of range\n");
f01b7962 614
5ab7b0b7 615 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 616 if (clock->m1 <= clock->m2)
617 INTELPllInvalid("m1 <= m2\n");
618
5ab7b0b7 619 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 620 if (clock->p < limit->p.min || limit->p.max < clock->p)
621 INTELPllInvalid("p out of range\n");
622 if (clock->m < limit->m.min || limit->m.max < clock->m)
623 INTELPllInvalid("m out of range\n");
624 }
625
79e53945 626 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 627 INTELPllInvalid("vco out of range\n");
79e53945
JB		 628 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
629 * connector, etc., rather than just a single range.
630 */
631 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 632 INTELPllInvalid("dot out of range\n");
79e53945
JB		 633
634 return true;
635}
636
d4906093 637static bool
a93e255f
ACO		 638i9xx_find_best_dpll(const intel_limit_t *limit,
639 struct intel_crtc_state *crtc_state,
cec2f356
SP		 640 int target, int refclk, intel_clock_t *match_clock,
641 intel_clock_t *best_clock)
79e53945 642{
a93e255f 643 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 644 struct drm_device *dev = crtc->base.dev;
79e53945 645 intel_clock_t clock;
79e53945
JB		 646 int err = target;
647
a93e255f 648 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 649 /*
a210b028
DV		 650 * For LVDS just rely on its current settings for dual-channel.
651 * We haven't figured out how to reliably set up different
652 * single/dual channel state, if we even can.
79e53945 653 */
1974cad0 654 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 655 clock.p2 = limit->p2.p2_fast;
656 else
657 clock.p2 = limit->p2.p2_slow;
658 } else {
659 if (target < limit->p2.dot_limit)
660 clock.p2 = limit->p2.p2_slow;
661 else
662 clock.p2 = limit->p2.p2_fast;
663 }
664
0206e353 665 memset(best_clock, 0, sizeof(*best_clock));
79e53945 666
42158660
ZY		 667 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
668 clock.m1++) {
669 for (clock.m2 = limit->m2.min;
670 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 671 if (clock.m2 >= clock.m1)
42158660
ZY		 672 break;
673 for (clock.n = limit->n.min;
674 clock.n <= limit->n.max; clock.n++) {
675 for (clock.p1 = limit->p1.min;
676 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 677 int this_err;
678
ac58c3f0
DV		 679 i9xx_clock(refclk, &clock);
680 if (!intel_PLL_is_valid(dev, limit,
681 &clock))
682 continue;
683 if (match_clock &&
684 clock.p != match_clock->p)
685 continue;
686
687 this_err = abs(clock.dot - target);
688 if (this_err < err) {
689 *best_clock = clock;
690 err = this_err;
691 }
692 }
693 }
694 }
695 }
696
697 return (err != target);
698}
699
700static bool
a93e255f
ACO		 701pnv_find_best_dpll(const intel_limit_t *limit,
702 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 703 int target, int refclk, intel_clock_t *match_clock,
704 intel_clock_t *best_clock)
79e53945 705{
a93e255f 706 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 707 struct drm_device *dev = crtc->base.dev;
79e53945 708 intel_clock_t clock;
79e53945
JB		 709 int err = target;
710
a93e255f 711 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 712 /*
a210b028
DV		 713 * For LVDS just rely on its current settings for dual-channel.
714 * We haven't figured out how to reliably set up different
715 * single/dual channel state, if we even can.
79e53945 716 */
1974cad0 717 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 718 clock.p2 = limit->p2.p2_fast;
719 else
720 clock.p2 = limit->p2.p2_slow;
721 } else {
722 if (target < limit->p2.dot_limit)
723 clock.p2 = limit->p2.p2_slow;
724 else
725 clock.p2 = limit->p2.p2_fast;
726 }
727
0206e353 728 memset(best_clock, 0, sizeof(*best_clock));
79e53945 729
42158660
ZY		 730 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
731 clock.m1++) {
732 for (clock.m2 = limit->m2.min;
733 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 734 for (clock.n = limit->n.min;
735 clock.n <= limit->n.max; clock.n++) {
736 for (clock.p1 = limit->p1.min;
737 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 738 int this_err;
739
ac58c3f0 740 pineview_clock(refclk, &clock);
1b894b59
CW		 741 if (!intel_PLL_is_valid(dev, limit,
742 &clock))
79e53945 743 continue;
cec2f356
SP		 744 if (match_clock &&
745 clock.p != match_clock->p)
746 continue;
79e53945
JB		 747
748 this_err = abs(clock.dot - target);
749 if (this_err < err) {
750 *best_clock = clock;
751 err = this_err;
752 }
753 }
754 }
755 }
756 }
757
758 return (err != target);
759}
760
d4906093 761static bool
a93e255f
ACO		 762g4x_find_best_dpll(const intel_limit_t *limit,
763 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 764 int target, int refclk, intel_clock_t *match_clock,
765 intel_clock_t *best_clock)
d4906093 766{
a93e255f 767 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 768 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 769 intel_clock_t clock;
770 int max_n;
771 bool found;
6ba770dc
AJ		 772 /* approximately equals target * 0.00585 */
773 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 774 found = false;
775
a93e255f 776 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 777 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 778 clock.p2 = limit->p2.p2_fast;
779 else
780 clock.p2 = limit->p2.p2_slow;
781 } else {
782 if (target < limit->p2.dot_limit)
783 clock.p2 = limit->p2.p2_slow;
784 else
785 clock.p2 = limit->p2.p2_fast;
786 }
787
788 memset(best_clock, 0, sizeof(*best_clock));
789 max_n = limit->n.max;
f77f13e2 790 /* based on hardware requirement, prefer smaller n to precision */
d4906093 791 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 792 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 793 for (clock.m1 = limit->m1.max;
794 clock.m1 >= limit->m1.min; clock.m1--) {
795 for (clock.m2 = limit->m2.max;
796 clock.m2 >= limit->m2.min; clock.m2--) {
797 for (clock.p1 = limit->p1.max;
798 clock.p1 >= limit->p1.min; clock.p1--) {
799 int this_err;
800
ac58c3f0 801 i9xx_clock(refclk, &clock);
1b894b59
CW		 802 if (!intel_PLL_is_valid(dev, limit,
803 &clock))
d4906093 804 continue;
1b894b59
CW		 805
806 this_err = abs(clock.dot - target);
d4906093
ML		 807 if (this_err < err_most) {
808 *best_clock = clock;
809 err_most = this_err;
810 max_n = clock.n;
811 found = true;
812 }
813 }
814 }
815 }
816 }
2c07245f
ZW		 817 return found;
818}
819
d5dd62bd
ID		 820/*
821 * Check if the calculated PLL configuration is more optimal compared to the
822 * best configuration and error found so far. Return the calculated error.
823 */
824static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
825 const intel_clock_t *calculated_clock,
826 const intel_clock_t *best_clock,
827 unsigned int best_error_ppm,
828 unsigned int *error_ppm)
829{
9ca3ba01
ID		 830 /*
831 * For CHV ignore the error and consider only the P value.
832 * Prefer a bigger P value based on HW requirements.
833 */
834 if (IS_CHERRYVIEW(dev)) {
835 *error_ppm = 0;
836
837 return calculated_clock->p > best_clock->p;
838 }
839
24be4e46
ID		 840 if (WARN_ON_ONCE(!target_freq))
841 return false;
842
d5dd62bd
ID		 843 *error_ppm = div_u64(1000000ULL *
844 abs(target_freq - calculated_clock->dot),
845 target_freq);
846 /*
847 * Prefer a better P value over a better (smaller) error if the error
848 * is small. Ensure this preference for future configurations too by
849 * setting the error to 0.
850 */
851 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
852 *error_ppm = 0;
853
854 return true;
855 }
856
857 return *error_ppm + 10 < best_error_ppm;
858}
859
a0c4da24 860static bool
a93e255f
ACO		 861vlv_find_best_dpll(const intel_limit_t *limit,
862 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
a0c4da24 865{
a93e255f 866 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 867 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 868 intel_clock_t clock;
69e4f900 869 unsigned int bestppm = 1000000;
27e639bf
VS		 870 /* min update 19.2 MHz */
871 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 872 bool found = false;
a0c4da24 873
6b4bf1c4
VS		 874 target *= 5; /* fast clock */
875
876 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 877
878 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 879 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 880 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 881 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 882 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 883 clock.p = clock.p1 * clock.p2;
a0c4da24 884 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 885 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 886 unsigned int ppm;
69e4f900 887
6b4bf1c4
VS		 888 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
889 refclk * clock.m1);
890
891 vlv_clock(refclk, &clock);
43b0ac53 892
f01b7962
VS		 893 if (!intel_PLL_is_valid(dev, limit,
894 &clock))
43b0ac53
VS		 895 continue;
896
d5dd62bd
ID		 897 if (!vlv_PLL_is_optimal(dev, target,
898 &clock,
899 best_clock,
900 bestppm, &ppm))
901 continue;
6b4bf1c4 902
d5dd62bd
ID		 903 *best_clock = clock;
904 bestppm = ppm;
905 found = true;
a0c4da24
JB		 906 }
907 }
908 }
909 }
a0c4da24 910
49e497ef 911 return found;
a0c4da24 912}
a4fc5ed6 913
ef9348c8 914static bool
a93e255f
ACO		 915chv_find_best_dpll(const intel_limit_t *limit,
916 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 917 int target, int refclk, intel_clock_t *match_clock,
918 intel_clock_t *best_clock)
919{
a93e255f 920 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 921 struct drm_device *dev = crtc->base.dev;
9ca3ba01 922 unsigned int best_error_ppm;
ef9348c8
CML		 923 intel_clock_t clock;
924 uint64_t m2;
925 int found = false;
926
927 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 928 best_error_ppm = 1000000;
ef9348c8
CML		 929
930 /*
931 * Based on hardware doc, the n always set to 1, and m1 always
932 * set to 2. If requires to support 200Mhz refclk, we need to
933 * revisit this because n may not 1 anymore.
934 */
935 clock.n = 1, clock.m1 = 2;
936 target *= 5; /* fast clock */
937
938 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
939 for (clock.p2 = limit->p2.p2_fast;
940 clock.p2 >= limit->p2.p2_slow;
941 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 942 unsigned int error_ppm;
ef9348c8
CML		 943
944 clock.p = clock.p1 * clock.p2;
945
946 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
947 clock.n) << 22, refclk * clock.m1);
948
949 if (m2 > INT_MAX/clock.m1)
950 continue;
951
952 clock.m2 = m2;
953
954 chv_clock(refclk, &clock);
955
956 if (!intel_PLL_is_valid(dev, limit, &clock))
957 continue;
958
9ca3ba01
ID		 959 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
960 best_error_ppm, &error_ppm))
961 continue;
962
963 *best_clock = clock;
964 best_error_ppm = error_ppm;
965 found = true;
ef9348c8
CML		 966 }
967 }
968
969 return found;
970}
971
5ab7b0b7
ID		 972bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
973 intel_clock_t *best_clock)
974{
975 int refclk = i9xx_get_refclk(crtc_state, 0);
976
977 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
978 target_clock, refclk, NULL, best_clock);
979}
980
20ddf665
VS		 981bool intel_crtc_active(struct drm_crtc *crtc)
982{
983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
984
985 /* Be paranoid as we can arrive here with only partial
986 * state retrieved from the hardware during setup.
987 *
241bfc38 988 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 989 * as Haswell has gained clock readout/fastboot support.
990 *
66e514c1 991 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 992 * properly reconstruct framebuffers.
c3d1f436
MR		 993 *
994 * FIXME: The intel_crtc->active here should be switched to
995 * crtc->state->active once we have proper CRTC states wired up
996 * for atomic.
20ddf665 997 */
c3d1f436 998 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 999 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1000}
1001
a5c961d1
PZ		 1002enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1003 enum pipe pipe)
1004{
1005 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1006 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1007
6e3c9717 1008 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1009}
1010
fbf49ea2
VS		 1011static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1012{
1013 struct drm_i915_private *dev_priv = dev->dev_private;
1014 u32 reg = PIPEDSL(pipe);
1015 u32 line1, line2;
1016 u32 line_mask;
1017
1018 if (IS_GEN2(dev))
1019 line_mask = DSL_LINEMASK_GEN2;
1020 else
1021 line_mask = DSL_LINEMASK_GEN3;
1022
1023 line1 = I915_READ(reg) & line_mask;
1024 mdelay(5);
1025 line2 = I915_READ(reg) & line_mask;
1026
1027 return line1 == line2;
1028}
1029
ab7ad7f6
KP		 1030/*
1031 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1032 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1033 *
1034 * After disabling a pipe, we can't wait for vblank in the usual way,
1035 * spinning on the vblank interrupt status bit, since we won't actually
1036 * see an interrupt when the pipe is disabled.
1037 *
ab7ad7f6
KP		 1038 * On Gen4 and above:
1039 * wait for the pipe register state bit to turn off
1040 *
1041 * Otherwise:
1042 * wait for the display line value to settle (it usually
1043 * ends up stopping at the start of the next frame).
58e10eb9 1044 *
9d0498a2 1045 */
575f7ab7 1046static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1047{
575f7ab7 1048 struct drm_device *dev = crtc->base.dev;
9d0498a2 1049 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1050 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1051 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1052
1053 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1054 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1055
1056 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1057 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1058 100))
284637d9 1059 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1060 } else {
ab7ad7f6 1061 /* Wait for the display line to settle */
fbf49ea2 1062 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1063 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1064 }
79e53945
JB		 1065}
1066
b0ea7d37
DL		 1067/*
1068 * ibx_digital_port_connected - is the specified port connected?
1069 * @dev_priv: i915 private structure
1070 * @port: the port to test
1071 *
1072 * Returns true if @port is connected, false otherwise.
1073 */
1074bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1075 struct intel_digital_port *port)
1076{
1077 u32 bit;
1078
c36346e3 1079 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1080 switch (port->port) {
c36346e3
DL		 1081 case PORT_B:
1082 bit = SDE_PORTB_HOTPLUG;
1083 break;
1084 case PORT_C:
1085 bit = SDE_PORTC_HOTPLUG;
1086 break;
1087 case PORT_D:
1088 bit = SDE_PORTD_HOTPLUG;
1089 break;
1090 default:
1091 return true;
1092 }
1093 } else {
eba905b2 1094 switch (port->port) {
c36346e3
DL		 1095 case PORT_B:
1096 bit = SDE_PORTB_HOTPLUG_CPT;
1097 break;
1098 case PORT_C:
1099 bit = SDE_PORTC_HOTPLUG_CPT;
1100 break;
1101 case PORT_D:
1102 bit = SDE_PORTD_HOTPLUG_CPT;
1103 break;
1104 default:
1105 return true;
1106 }
b0ea7d37
DL		 1107 }
1108
1109 return I915_READ(SDEISR) & bit;
1110}
1111
b24e7179
JB		 1112static const char *state_string(bool enabled)
1113{
1114 return enabled ? "on" : "off";
1115}
1116
1117/* Only for pre-ILK configs */
55607e8a
DV		 1118void assert_pll(struct drm_i915_private *dev_priv,
1119 enum pipe pipe, bool state)
b24e7179
JB		 1120{
1121 int reg;
1122 u32 val;
1123 bool cur_state;
1124
1125 reg = DPLL(pipe);
1126 val = I915_READ(reg);
1127 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1128 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1129 "PLL state assertion failure (expected %s, current %s)\n",
1130 state_string(state), state_string(cur_state));
1131}
b24e7179 1132
23538ef1
JN		 1133/* XXX: the dsi pll is shared between MIPI DSI ports */
1134static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1135{
1136 u32 val;
1137 bool cur_state;
1138
1139 mutex_lock(&dev_priv->dpio_lock);
1140 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1141 mutex_unlock(&dev_priv->dpio_lock);
1142
1143 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1144 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1145 "DSI PLL state assertion failure (expected %s, current %s)\n",
1146 state_string(state), state_string(cur_state));
1147}
1148#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1149#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1150
55607e8a 1151struct intel_shared_dpll *
e2b78267
DV		 1152intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1153{
1154 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1155
6e3c9717 1156 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1157 return NULL;
1158
6e3c9717 1159 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1160}
1161
040484af 1162/* For ILK+ */
55607e8a
DV		 1163void assert_shared_dpll(struct drm_i915_private *dev_priv,
1164 struct intel_shared_dpll *pll,
1165 bool state)
040484af 1166{
040484af 1167 bool cur_state;
5358901f 1168 struct intel_dpll_hw_state hw_state;
040484af 1169
92b27b08 1170 if (WARN (!pll,
46edb027 1171 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1172 return;
ee7b9f93 1173
5358901f 1174 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1175 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1176 "%s assertion failure (expected %s, current %s)\n",
1177 pll->name, state_string(state), state_string(cur_state));
040484af 1178}
040484af
JB		 1179
1180static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1181 enum pipe pipe, bool state)
1182{
1183 int reg;
1184 u32 val;
1185 bool cur_state;
ad80a810
PZ		 1186 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1187 pipe);
040484af 1188
affa9354
PZ		 1189 if (HAS_DDI(dev_priv->dev)) {
1190 /* DDI does not have a specific FDI_TX register */
ad80a810 1191 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1192 val = I915_READ(reg);
ad80a810 1193 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1194 } else {
1195 reg = FDI_TX_CTL(pipe);
1196 val = I915_READ(reg);
1197 cur_state = !!(val & FDI_TX_ENABLE);
1198 }
e2c719b7 1199 I915_STATE_WARN(cur_state != state,
040484af
JB		 1200 "FDI TX state assertion failure (expected %s, current %s)\n",
1201 state_string(state), state_string(cur_state));
1202}
1203#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1204#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1205
1206static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1207 enum pipe pipe, bool state)
1208{
1209 int reg;
1210 u32 val;
1211 bool cur_state;
1212
d63fa0dc
PZ		 1213 reg = FDI_RX_CTL(pipe);
1214 val = I915_READ(reg);
1215 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1216 I915_STATE_WARN(cur_state != state,
040484af
JB		 1217 "FDI RX state assertion failure (expected %s, current %s)\n",
1218 state_string(state), state_string(cur_state));
1219}
1220#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1221#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1222
1223static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1224 enum pipe pipe)
1225{
1226 int reg;
1227 u32 val;
1228
1229 /* ILK FDI PLL is always enabled */
3d13ef2e 1230 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1231 return;
1232
bf507ef7 1233 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1234 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1235 return;
1236
040484af
JB		 1237 reg = FDI_TX_CTL(pipe);
1238 val = I915_READ(reg);
e2c719b7 1239 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1240}
1241
55607e8a
DV		 1242void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1243 enum pipe pipe, bool state)
040484af
JB		 1244{
1245 int reg;
1246 u32 val;
55607e8a 1247 bool cur_state;
040484af
JB		 1248
1249 reg = FDI_RX_CTL(pipe);
1250 val = I915_READ(reg);
55607e8a 1251 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1252 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1253 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1254 state_string(state), state_string(cur_state));
040484af
JB		 1255}
1256
b680c37a
DV		 1257void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1258 enum pipe pipe)
ea0760cf 1259{
bedd4dba
JN		 1260 struct drm_device *dev = dev_priv->dev;
1261 int pp_reg;
ea0760cf
JB		 1262 u32 val;
1263 enum pipe panel_pipe = PIPE_A;
0de3b485 1264 bool locked = true;
ea0760cf 1265
bedd4dba
JN		 1266 if (WARN_ON(HAS_DDI(dev)))
1267 return;
1268
1269 if (HAS_PCH_SPLIT(dev)) {
1270 u32 port_sel;
1271
ea0760cf 1272 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1273 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1274
1275 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1276 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1277 panel_pipe = PIPE_B;
1278 /* XXX: else fix for eDP */
1279 } else if (IS_VALLEYVIEW(dev)) {
1280 /* presumably write lock depends on pipe, not port select */
1281 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1282 panel_pipe = pipe;
ea0760cf
JB		 1283 } else {
1284 pp_reg = PP_CONTROL;
bedd4dba
JN		 1285 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1286 panel_pipe = PIPE_B;
ea0760cf
JB		 1287 }
1288
1289 val = I915_READ(pp_reg);
1290 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1291 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1292 locked = false;
1293
e2c719b7 1294 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1295 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1296 pipe_name(pipe));
ea0760cf
JB		 1297}
1298
93ce0ba6
JN		 1299static void assert_cursor(struct drm_i915_private *dev_priv,
1300 enum pipe pipe, bool state)
1301{
1302 struct drm_device *dev = dev_priv->dev;
1303 bool cur_state;
1304
d9d82081 1305 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1306 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1307 else
5efb3e28 1308 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1309
e2c719b7 1310 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1311 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1312 pipe_name(pipe), state_string(state), state_string(cur_state));
1313}
1314#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1315#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1316
b840d907
JB		 1317void assert_pipe(struct drm_i915_private *dev_priv,
1318 enum pipe pipe, bool state)
b24e7179
JB		 1319{
1320 int reg;
1321 u32 val;
63d7bbe9 1322 bool cur_state;
702e7a56
PZ		 1323 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1324 pipe);
b24e7179 1325
b6b5d049
VS		 1326 /* if we need the pipe quirk it must be always on */
1327 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1328 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1329 state = true;
1330
f458ebbc 1331 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1332 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1333 cur_state = false;
1334 } else {
1335 reg = PIPECONF(cpu_transcoder);
1336 val = I915_READ(reg);
1337 cur_state = !!(val & PIPECONF_ENABLE);
1338 }
1339
e2c719b7 1340 I915_STATE_WARN(cur_state != state,
63d7bbe9 1341 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1342 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1343}
1344
931872fc
CW		 1345static void assert_plane(struct drm_i915_private *dev_priv,
1346 enum plane plane, bool state)
b24e7179
JB		 1347{
1348 int reg;
1349 u32 val;
931872fc 1350 bool cur_state;
b24e7179
JB		 1351
1352 reg = DSPCNTR(plane);
1353 val = I915_READ(reg);
931872fc 1354 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1355 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1356 "plane %c assertion failure (expected %s, current %s)\n",
1357 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1358}
1359
931872fc
CW		 1360#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1361#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1362
b24e7179
JB		 1363static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1364 enum pipe pipe)
1365{
653e1026 1366 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1367 int reg, i;
1368 u32 val;
1369 int cur_pipe;
1370
653e1026
VS		 1371 /* Primary planes are fixed to pipes on gen4+ */
1372 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1373 reg = DSPCNTR(pipe);
1374 val = I915_READ(reg);
e2c719b7 1375 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1376 "plane %c assertion failure, should be disabled but not\n",
1377 plane_name(pipe));
19ec1358 1378 return;
28c05794 1379 }
19ec1358 1380
b24e7179 1381 /* Need to check both planes against the pipe */
055e393f 1382 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1383 reg = DSPCNTR(i);
1384 val = I915_READ(reg);
1385 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1386 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1387 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1388 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1389 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1390 }
1391}
1392
19332d7a
JB		 1393static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1394 enum pipe pipe)
1395{
20674eef 1396 struct drm_device *dev = dev_priv->dev;
1fe47785 1397 int reg, sprite;
19332d7a
JB		 1398 u32 val;
1399
7feb8b88 1400 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1401 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1402 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1403 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1404 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1405 sprite, pipe_name(pipe));
1406 }
1407 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1408 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1409 reg = SPCNTR(pipe, sprite);
20674eef 1410 val = I915_READ(reg);
e2c719b7 1411 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1412 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1413 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1414 }
1415 } else if (INTEL_INFO(dev)->gen >= 7) {
1416 reg = SPRCTL(pipe);
19332d7a 1417 val = I915_READ(reg);
e2c719b7 1418 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1419 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1420 plane_name(pipe), pipe_name(pipe));
1421 } else if (INTEL_INFO(dev)->gen >= 5) {
1422 reg = DVSCNTR(pipe);
19332d7a 1423 val = I915_READ(reg);
e2c719b7 1424 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1425 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1426 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1427 }
1428}
1429
08c71e5e
VS		 1430static void assert_vblank_disabled(struct drm_crtc *crtc)
1431{
e2c719b7 1432 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1433 drm_crtc_vblank_put(crtc);
1434}
1435
89eff4be 1436static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1437{
1438 u32 val;
1439 bool enabled;
1440
e2c719b7 1441 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1442
92f2584a
JB		 1443 val = I915_READ(PCH_DREF_CONTROL);
1444 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1445 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1446 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1447}
1448
ab9412ba
DV		 1449static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1450 enum pipe pipe)
92f2584a
JB		 1451{
1452 int reg;
1453 u32 val;
1454 bool enabled;
1455
ab9412ba 1456 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1457 val = I915_READ(reg);
1458 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1459 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1460 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1461 pipe_name(pipe));
92f2584a
JB		 1462}
1463
4e634389
KP		 1464static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1465 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1466{
1467 if ((val & DP_PORT_EN) == 0)
1468 return false;
1469
1470 if (HAS_PCH_CPT(dev_priv->dev)) {
1471 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1472 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1473 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1474 return false;
44f37d1f
CML		 1475 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1476 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1477 return false;
f0575e92
KP		 1478 } else {
1479 if ((val & DP_PIPE_MASK) != (pipe << 30))
1480 return false;
1481 }
1482 return true;
1483}
1484
1519b995
KP		 1485static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1486 enum pipe pipe, u32 val)
1487{
dc0fa718 1488 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1489 return false;
1490
1491 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1492 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1493 return false;
44f37d1f
CML		 1494 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1495 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1496 return false;
1519b995 1497 } else {
dc0fa718 1498 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1499 return false;
1500 }
1501 return true;
1502}
1503
1504static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1505 enum pipe pipe, u32 val)
1506{
1507 if ((val & LVDS_PORT_EN) == 0)
1508 return false;
1509
1510 if (HAS_PCH_CPT(dev_priv->dev)) {
1511 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1512 return false;
1513 } else {
1514 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1515 return false;
1516 }
1517 return true;
1518}
1519
1520static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1521 enum pipe pipe, u32 val)
1522{
1523 if ((val & ADPA_DAC_ENABLE) == 0)
1524 return false;
1525 if (HAS_PCH_CPT(dev_priv->dev)) {
1526 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1527 return false;
1528 } else {
1529 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1530 return false;
1531 }
1532 return true;
1533}
1534
291906f1 1535static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1536 enum pipe pipe, int reg, u32 port_sel)
291906f1 1537{
47a05eca 1538 u32 val = I915_READ(reg);
e2c719b7 1539 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1540 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1541 reg, pipe_name(pipe));
de9a35ab 1542
e2c719b7 1543 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1544 && (val & DP_PIPEB_SELECT),
de9a35ab 1545 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1546}
1547
1548static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1549 enum pipe pipe, int reg)
1550{
47a05eca 1551 u32 val = I915_READ(reg);
e2c719b7 1552 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1553 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1554 reg, pipe_name(pipe));
de9a35ab 1555
e2c719b7 1556 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1557 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1558 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1559}
1560
1561static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1562 enum pipe pipe)
1563{
1564 int reg;
1565 u32 val;
291906f1 1566
f0575e92
KP		 1567 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1568 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1569 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1570
1571 reg = PCH_ADPA;
1572 val = I915_READ(reg);
e2c719b7 1573 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1574 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1575 pipe_name(pipe));
291906f1
JB		 1576
1577 reg = PCH_LVDS;
1578 val = I915_READ(reg);
e2c719b7 1579 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1580 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1581 pipe_name(pipe));
291906f1 1582
e2debe91
PZ		 1583 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1584 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1585 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1586}
1587
40e9cf64
JB		 1588static void intel_init_dpio(struct drm_device *dev)
1589{
1590 struct drm_i915_private *dev_priv = dev->dev_private;
1591
1592 if (!IS_VALLEYVIEW(dev))
1593 return;
1594
a09caddd
CML		 1595 /*
1596 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1597 * CHV x1 PHY (DP/HDMI D)
1598 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1599 */
1600 if (IS_CHERRYVIEW(dev)) {
1601 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1602 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1603 } else {
1604 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1605 }
5382f5f3
JB		 1606}
1607
d288f65f 1608static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1609 const struct intel_crtc_state *pipe_config)
87442f73 1610{
426115cf
DV		 1611 struct drm_device *dev = crtc->base.dev;
1612 struct drm_i915_private *dev_priv = dev->dev_private;
1613 int reg = DPLL(crtc->pipe);
d288f65f 1614 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1615
426115cf 1616 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1617
1618 /* No really, not for ILK+ */
1619 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1620
1621 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1622 if (IS_MOBILE(dev_priv->dev))
426115cf 1623 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1624
426115cf
DV		 1625 I915_WRITE(reg, dpll);
1626 POSTING_READ(reg);
1627 udelay(150);
1628
1629 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1630 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1631
d288f65f 1632 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1633 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1634
1635 /* We do this three times for luck */
426115cf 1636 I915_WRITE(reg, dpll);
87442f73
DV		 1637 POSTING_READ(reg);
1638 udelay(150); /* wait for warmup */
426115cf 1639 I915_WRITE(reg, dpll);
87442f73
DV		 1640 POSTING_READ(reg);
1641 udelay(150); /* wait for warmup */
426115cf 1642 I915_WRITE(reg, dpll);
87442f73
DV		 1643 POSTING_READ(reg);
1644 udelay(150); /* wait for warmup */
1645}
1646
d288f65f 1647static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1648 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1649{
1650 struct drm_device *dev = crtc->base.dev;
1651 struct drm_i915_private *dev_priv = dev->dev_private;
1652 int pipe = crtc->pipe;
1653 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1654 u32 tmp;
1655
1656 assert_pipe_disabled(dev_priv, crtc->pipe);
1657
1658 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1659
1660 mutex_lock(&dev_priv->dpio_lock);
1661
1662 /* Enable back the 10bit clock to display controller */
1663 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1664 tmp |= DPIO_DCLKP_EN;
1665 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1666
1667 /*
1668 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1669 */
1670 udelay(1);
1671
1672 /* Enable PLL */
d288f65f 1673 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1674
1675 /* Check PLL is locked */
a11b0703 1676 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1677 DRM_ERROR("PLL %d failed to lock\n", pipe);
1678
a11b0703 1679 /* not sure when this should be written */
d288f65f 1680 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703
VS		 1681 POSTING_READ(DPLL_MD(pipe));
1682
9d556c99
CML		 1683 mutex_unlock(&dev_priv->dpio_lock);
1684}
1685
1c4e0274
VS		 1686static int intel_num_dvo_pipes(struct drm_device *dev)
1687{
1688 struct intel_crtc *crtc;
1689 int count = 0;
1690
1691 for_each_intel_crtc(dev, crtc)
1692 count += crtc->active &&
409ee761 1693 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1694
1695 return count;
1696}
1697
66e3d5c0 1698static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1699{
66e3d5c0
DV		 1700 struct drm_device *dev = crtc->base.dev;
1701 struct drm_i915_private *dev_priv = dev->dev_private;
1702 int reg = DPLL(crtc->pipe);
6e3c9717 1703 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1704
66e3d5c0 1705 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1706
63d7bbe9 1707 /* No really, not for ILK+ */
3d13ef2e 1708 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1709
1710 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1711 if (IS_MOBILE(dev) && !IS_I830(dev))
1712 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1713
1c4e0274
VS		 1714 /* Enable DVO 2x clock on both PLLs if necessary */
1715 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1716 /*
1717 * It appears to be important that we don't enable this
1718 * for the current pipe before otherwise configuring the
1719 * PLL. No idea how this should be handled if multiple
1720 * DVO outputs are enabled simultaneosly.
1721 */
1722 dpll |= DPLL_DVO_2X_MODE;
1723 I915_WRITE(DPLL(!crtc->pipe),
1724 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1725 }
66e3d5c0
DV		 1726
1727 /* Wait for the clocks to stabilize. */
1728 POSTING_READ(reg);
1729 udelay(150);
1730
1731 if (INTEL_INFO(dev)->gen >= 4) {
1732 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1733 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1734 } else {
1735 /* The pixel multiplier can only be updated once the
1736 * DPLL is enabled and the clocks are stable.
1737 *
1738 * So write it again.
1739 */
1740 I915_WRITE(reg, dpll);
1741 }
63d7bbe9
JB		 1742
1743 /* We do this three times for luck */
66e3d5c0 1744 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1745 POSTING_READ(reg);
1746 udelay(150); /* wait for warmup */
66e3d5c0 1747 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1748 POSTING_READ(reg);
1749 udelay(150); /* wait for warmup */
66e3d5c0 1750 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1751 POSTING_READ(reg);
1752 udelay(150); /* wait for warmup */
1753}
1754
1755/**
50b44a44 1756 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1757 * @dev_priv: i915 private structure
1758 * @pipe: pipe PLL to disable
1759 *
1760 * Disable the PLL for @pipe, making sure the pipe is off first.
1761 *
1762 * Note! This is for pre-ILK only.
1763 */
1c4e0274 1764static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1765{
1c4e0274
VS		 1766 struct drm_device *dev = crtc->base.dev;
1767 struct drm_i915_private *dev_priv = dev->dev_private;
1768 enum pipe pipe = crtc->pipe;
1769
1770 /* Disable DVO 2x clock on both PLLs if necessary */
1771 if (IS_I830(dev) &&
409ee761 1772 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1773 intel_num_dvo_pipes(dev) == 1) {
1774 I915_WRITE(DPLL(PIPE_B),
1775 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1776 I915_WRITE(DPLL(PIPE_A),
1777 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1778 }
1779
b6b5d049
VS		 1780 /* Don't disable pipe or pipe PLLs if needed */
1781 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1782 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1783 return;
1784
1785 /* Make sure the pipe isn't still relying on us */
1786 assert_pipe_disabled(dev_priv, pipe);
1787
50b44a44
DV		 1788 I915_WRITE(DPLL(pipe), 0);
1789 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1790}
1791
f6071166
JB		 1792static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1793{
1794 u32 val = 0;
1795
1796 /* Make sure the pipe isn't still relying on us */
1797 assert_pipe_disabled(dev_priv, pipe);
1798
e5cbfbfb
ID		 1799 /*
1800 * Leave integrated clock source and reference clock enabled for pipe B.
1801 * The latter is needed for VGA hotplug / manual detection.
1802 */
f6071166 1803 if (pipe == PIPE_B)
e5cbfbfb 1804 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1805 I915_WRITE(DPLL(pipe), val);
1806 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1807
1808}
1809
1810static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1811{
d752048d 1812 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1813 u32 val;
1814
a11b0703
VS		 1815 /* Make sure the pipe isn't still relying on us */
1816 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1817
a11b0703 1818 /* Set PLL en = 0 */
d17ec4ce 1819 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1820 if (pipe != PIPE_A)
1821 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1822 I915_WRITE(DPLL(pipe), val);
1823 POSTING_READ(DPLL(pipe));
d752048d
VS		 1824
1825 mutex_lock(&dev_priv->dpio_lock);
1826
1827 /* Disable 10bit clock to display controller */
1828 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1829 val &= ~DPIO_DCLKP_EN;
1830 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1831
61407f6d
VS		 1832 /* disable left/right clock distribution */
1833 if (pipe != PIPE_B) {
1834 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1835 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1836 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1837 } else {
1838 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1839 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1840 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1841 }
1842
d752048d 1843 mutex_unlock(&dev_priv->dpio_lock);
f6071166
JB		 1844}
1845
e4607fcf 1846void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1847 struct intel_digital_port *dport,
1848 unsigned int expected_mask)
89b667f8
JB		 1849{
1850 u32 port_mask;
00fc31b7 1851 int dpll_reg;
89b667f8 1852
e4607fcf
CML		 1853 switch (dport->port) {
1854 case PORT_B:
89b667f8 1855 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1856 dpll_reg = DPLL(0);
e4607fcf
CML		 1857 break;
1858 case PORT_C:
89b667f8 1859 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1860 dpll_reg = DPLL(0);
9b6de0a1 1861 expected_mask <<= 4;
00fc31b7
CML		 1862 break;
1863 case PORT_D:
1864 port_mask = DPLL_PORTD_READY_MASK;
1865 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1866 break;
1867 default:
1868 BUG();
1869 }
89b667f8 1870
9b6de0a1
VS		 1871 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1872 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1873 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1874}
1875
b14b1055
DV		 1876static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1877{
1878 struct drm_device *dev = crtc->base.dev;
1879 struct drm_i915_private *dev_priv = dev->dev_private;
1880 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1881
be19f0ff
CW		 1882 if (WARN_ON(pll == NULL))
1883 return;
1884
3e369b76 1885 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1886 if (pll->active == 0) {
1887 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1888 WARN_ON(pll->on);
1889 assert_shared_dpll_disabled(dev_priv, pll);
1890
1891 pll->mode_set(dev_priv, pll);
1892 }
1893}
1894
92f2584a 1895/**
85b3894f 1896 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1897 * @dev_priv: i915 private structure
1898 * @pipe: pipe PLL to enable
1899 *
1900 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1901 * drives the transcoder clock.
1902 */
85b3894f 1903static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1904{
3d13ef2e
DL		 1905 struct drm_device *dev = crtc->base.dev;
1906 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1907 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1908
87a875bb 1909 if (WARN_ON(pll == NULL))
48da64a8
CW		 1910 return;
1911
3e369b76 1912 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1913 return;
ee7b9f93 1914
74dd6928 1915 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1916 pll->name, pll->active, pll->on,
e2b78267 1917 crtc->base.base.id);
92f2584a 1918
cdbd2316
DV		 1919 if (pll->active++) {
1920 WARN_ON(!pll->on);
e9d6944e 1921 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1922 return;
1923 }
f4a091c7 1924 WARN_ON(pll->on);
ee7b9f93 1925
bd2bb1b9
PZ		 1926 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1927
46edb027 1928 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1929 pll->enable(dev_priv, pll);
ee7b9f93 1930 pll->on = true;
92f2584a
JB		 1931}
1932
f6daaec2 1933static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1934{
3d13ef2e
DL		 1935 struct drm_device *dev = crtc->base.dev;
1936 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1937 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1938
92f2584a 1939 /* PCH only available on ILK+ */
3d13ef2e 1940 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1941 if (WARN_ON(pll == NULL))
ee7b9f93 1942 return;
92f2584a 1943
3e369b76 1944 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1945 return;
7a419866 1946
46edb027
DV		 1947 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1948 pll->name, pll->active, pll->on,
e2b78267 1949 crtc->base.base.id);
7a419866 1950
48da64a8 1951 if (WARN_ON(pll->active == 0)) {
e9d6944e 1952 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1953 return;
1954 }
1955
e9d6944e 1956 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1957 WARN_ON(!pll->on);
cdbd2316 1958 if (--pll->active)
7a419866 1959 return;
ee7b9f93 1960
46edb027 1961 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1962 pll->disable(dev_priv, pll);
ee7b9f93 1963 pll->on = false;
bd2bb1b9
PZ		 1964
1965 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1966}
1967
b8a4f404
PZ		 1968static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1969 enum pipe pipe)
040484af 1970{
23670b32 1971 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1972 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1973 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1974 uint32_t reg, val, pipeconf_val;
040484af
JB		 1975
1976 /* PCH only available on ILK+ */
55522f37 1977 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1978
1979 /* Make sure PCH DPLL is enabled */
e72f9fbf 1980 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1981 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1982
1983 /* FDI must be feeding us bits for PCH ports */
1984 assert_fdi_tx_enabled(dev_priv, pipe);
1985 assert_fdi_rx_enabled(dev_priv, pipe);
1986
23670b32
DV		 1987 if (HAS_PCH_CPT(dev)) {
1988 /* Workaround: Set the timing override bit before enabling the
1989 * pch transcoder. */
1990 reg = TRANS_CHICKEN2(pipe);
1991 val = I915_READ(reg);
1992 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1993 I915_WRITE(reg, val);
59c859d6 1994 }
23670b32 1995
ab9412ba 1996 reg = PCH_TRANSCONF(pipe);
040484af 1997 val = I915_READ(reg);
5f7f726d 1998 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1999
2000 if (HAS_PCH_IBX(dev_priv->dev)) {
2001 /*
2002 * make the BPC in transcoder be consistent with
2003 * that in pipeconf reg.
2004 */
dfd07d72
DV		 2005 val &= ~PIPECONF_BPC_MASK;
2006 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2007 }
5f7f726d
PZ		 2008
2009 val &= ~TRANS_INTERLACE_MASK;
2010 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2011 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2012 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2013 val |= TRANS_LEGACY_INTERLACED_ILK;
2014 else
2015 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2016 else
2017 val |= TRANS_PROGRESSIVE;
2018
040484af
JB		 2019 I915_WRITE(reg, val | TRANS_ENABLE);
2020 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2021 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2022}
2023
8fb033d7 2024static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2025 enum transcoder cpu_transcoder)
040484af 2026{
8fb033d7 2027 u32 val, pipeconf_val;
8fb033d7
PZ		 2028
2029 /* PCH only available on ILK+ */
55522f37 2030 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2031
8fb033d7 2032 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2033 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2034 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2035
223a6fdf
PZ		 2036 /* Workaround: set timing override bit. */
2037 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2038 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2039 I915_WRITE(_TRANSA_CHICKEN2, val);
2040
25f3ef11 2041 val = TRANS_ENABLE;
937bb610 2042 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2043
9a76b1c6
PZ		 2044 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2045 PIPECONF_INTERLACED_ILK)
a35f2679 2046 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2047 else
2048 val |= TRANS_PROGRESSIVE;
2049
ab9412ba
DV		 2050 I915_WRITE(LPT_TRANSCONF, val);
2051 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2052 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2053}
2054
b8a4f404
PZ		 2055static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2056 enum pipe pipe)
040484af 2057{
23670b32
DV		 2058 struct drm_device *dev = dev_priv->dev;
2059 uint32_t reg, val;
040484af
JB		 2060
2061 /* FDI relies on the transcoder */
2062 assert_fdi_tx_disabled(dev_priv, pipe);
2063 assert_fdi_rx_disabled(dev_priv, pipe);
2064
291906f1
JB		 2065 /* Ports must be off as well */
2066 assert_pch_ports_disabled(dev_priv, pipe);
2067
ab9412ba 2068 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2069 val = I915_READ(reg);
2070 val &= ~TRANS_ENABLE;
2071 I915_WRITE(reg, val);
2072 /* wait for PCH transcoder off, transcoder state */
2073 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2074 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2075
2076 if (!HAS_PCH_IBX(dev)) {
2077 /* Workaround: Clear the timing override chicken bit again. */
2078 reg = TRANS_CHICKEN2(pipe);
2079 val = I915_READ(reg);
2080 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2081 I915_WRITE(reg, val);
2082 }
040484af
JB		 2083}
2084
ab4d966c 2085static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2086{
8fb033d7
PZ		 2087 u32 val;
2088
ab9412ba 2089 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2090 val &= ~TRANS_ENABLE;
ab9412ba 2091 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2092 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2093 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2094 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2095
2096 /* Workaround: clear timing override bit. */
2097 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2098 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2099 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2100}
2101
b24e7179 2102/**
309cfea8 2103 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2104 * @crtc: crtc responsible for the pipe
b24e7179 2105 *
0372264a 2106 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2107 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2108 */
e1fdc473 2109static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2110{
0372264a
PZ		 2111 struct drm_device *dev = crtc->base.dev;
2112 struct drm_i915_private *dev_priv = dev->dev_private;
2113 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2114 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2115 pipe);
1a240d4d 2116 enum pipe pch_transcoder;
b24e7179
JB		 2117 int reg;
2118 u32 val;
2119
58c6eaa2 2120 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2121 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2122 assert_sprites_disabled(dev_priv, pipe);
2123
681e5811 2124 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2125 pch_transcoder = TRANSCODER_A;
2126 else
2127 pch_transcoder = pipe;
2128
b24e7179
JB		 2129 /*
2130 * A pipe without a PLL won't actually be able to drive bits from
2131 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2132 * need the check.
2133 */
50360403 2134 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2135 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2136 assert_dsi_pll_enabled(dev_priv);
2137 else
2138 assert_pll_enabled(dev_priv, pipe);
040484af 2139 else {
6e3c9717 2140 if (crtc->config->has_pch_encoder) {
040484af 2141 /* if driving the PCH, we need FDI enabled */
cc391bbb 2142 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2143 assert_fdi_tx_pll_enabled(dev_priv,
2144 (enum pipe) cpu_transcoder);
040484af
JB		 2145 }
2146 /* FIXME: assert CPU port conditions for SNB+ */
2147 }
b24e7179 2148
702e7a56 2149 reg = PIPECONF(cpu_transcoder);
b24e7179 2150 val = I915_READ(reg);
7ad25d48 2151 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2152 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2153 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2154 return;
7ad25d48 2155 }
00d70b15
CW		 2156
2157 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2158 POSTING_READ(reg);
b24e7179
JB		 2159}
2160
2161/**
309cfea8 2162 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2163 * @crtc: crtc whose pipes is to be disabled
b24e7179 2164 *
575f7ab7
VS		 2165 * Disable the pipe of @crtc, making sure that various hardware
2166 * specific requirements are met, if applicable, e.g. plane
2167 * disabled, panel fitter off, etc.
b24e7179
JB		 2168 *
2169 * Will wait until the pipe has shut down before returning.
2170 */
575f7ab7 2171static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2172{
575f7ab7 2173 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2174 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2175 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2176 int reg;
2177 u32 val;
2178
2179 /*
2180 * Make sure planes won't keep trying to pump pixels to us,
2181 * or we might hang the display.
2182 */
2183 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2184 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2185 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2186
702e7a56 2187 reg = PIPECONF(cpu_transcoder);
b24e7179 2188 val = I915_READ(reg);
00d70b15
CW		 2189 if ((val & PIPECONF_ENABLE) == 0)
2190 return;
2191
67adc644
VS		 2192 /*
2193 * Double wide has implications for planes
2194 * so best keep it disabled when not needed.
2195 */
6e3c9717 2196 if (crtc->config->double_wide)
67adc644
VS		 2197 val &= ~PIPECONF_DOUBLE_WIDE;
2198
2199 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2200 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2201 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2202 val &= ~PIPECONF_ENABLE;
2203
2204 I915_WRITE(reg, val);
2205 if ((val & PIPECONF_ENABLE) == 0)
2206 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2207}
2208
d74362c9
KP		 2209/*
2210 * Plane regs are double buffered, going from enabled->disabled needs a
2211 * trigger in order to latch. The display address reg provides this.
2212 */
1dba99f4
VS		 2213void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2214 enum plane plane)
d74362c9 2215{
3d13ef2e
DL		 2216 struct drm_device *dev = dev_priv->dev;
2217 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1dba99f4
VS		 2218
2219 I915_WRITE(reg, I915_READ(reg));
2220 POSTING_READ(reg);
d74362c9
KP		 2221}
2222
b24e7179 2223/**
262ca2b0 2224 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2225 * @plane: plane to be enabled
2226 * @crtc: crtc for the plane
b24e7179 2227 *
fdd508a6 2228 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2229 */
fdd508a6
VS		 2230static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2231 struct drm_crtc *crtc)
b24e7179 2232{
fdd508a6
VS		 2233 struct drm_device *dev = plane->dev;
2234 struct drm_i915_private *dev_priv = dev->dev_private;
2235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2236
2237 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2238 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b70709a6 2239 to_intel_plane_state(plane->state)->visible = true;
939c2fe8 2240
fdd508a6
VS		 2241 dev_priv->display.update_primary_plane(crtc, plane->fb,
2242 crtc->x, crtc->y);
b24e7179
JB		 2243}
2244
693db184
CW		 2245static bool need_vtd_wa(struct drm_device *dev)
2246{
2247#ifdef CONFIG_INTEL_IOMMU
2248 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2249 return true;
2250#endif
2251 return false;
2252}
2253
50470bb0 2254unsigned int
6761dd31
TU		 2255intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2256 uint64_t fb_format_modifier)
a57ce0b2 2257{
6761dd31
TU		 2258 unsigned int tile_height;
2259 uint32_t pixel_bytes;
a57ce0b2 2260
b5d0e9bf
DL		 2261 switch (fb_format_modifier) {
2262 case DRM_FORMAT_MOD_NONE:
2263 tile_height = 1;
2264 break;
2265 case I915_FORMAT_MOD_X_TILED:
2266 tile_height = IS_GEN2(dev) ? 16 : 8;
2267 break;
2268 case I915_FORMAT_MOD_Y_TILED:
2269 tile_height = 32;
2270 break;
2271 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2272 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2273 switch (pixel_bytes) {
b5d0e9bf 2274 default:
6761dd31 2275 case 1:
b5d0e9bf
DL		 2276 tile_height = 64;
2277 break;
6761dd31
TU		 2278 case 2:
2279 case 4:
b5d0e9bf
DL		 2280 tile_height = 32;
2281 break;
6761dd31 2282 case 8:
b5d0e9bf
DL		 2283 tile_height = 16;
2284 break;
6761dd31 2285 case 16:
b5d0e9bf
DL		 2286 WARN_ONCE(1,
2287 "128-bit pixels are not supported for display!");
2288 tile_height = 16;
2289 break;
2290 }
2291 break;
2292 default:
2293 MISSING_CASE(fb_format_modifier);
2294 tile_height = 1;
2295 break;
2296 }
091df6cb 2297
6761dd31
TU		 2298 return tile_height;
2299}
2300
2301unsigned int
2302intel_fb_align_height(struct drm_device *dev, unsigned int height,
2303 uint32_t pixel_format, uint64_t fb_format_modifier)
2304{
2305 return ALIGN(height, intel_tile_height(dev, pixel_format,
2306 fb_format_modifier));
a57ce0b2
JB		 2307}
2308
f64b98cd
TU		 2309static int
2310intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2311 const struct drm_plane_state *plane_state)
2312{
50470bb0 2313 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2314
f64b98cd
TU		 2315 *view = i915_ggtt_view_normal;
2316
50470bb0
TU		 2317 if (!plane_state)
2318 return 0;
2319
121920fa 2320 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2321 return 0;
2322
9abc4648 2323 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2324
2325 info->height = fb->height;
2326 info->pixel_format = fb->pixel_format;
2327 info->pitch = fb->pitches[0];
2328 info->fb_modifier = fb->modifier[0];
2329
f64b98cd
TU		 2330 return 0;
2331}
2332
127bd2ac 2333int
850c4cdc
TU		 2334intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2335 struct drm_framebuffer *fb,
82bc3b2d 2336 const struct drm_plane_state *plane_state,
a4872ba6 2337 struct intel_engine_cs *pipelined)
6b95a207 2338{
850c4cdc 2339 struct drm_device *dev = fb->dev;
ce453d81 2340 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2341 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2342 struct i915_ggtt_view view;
6b95a207
KH		 2343 u32 alignment;
2344 int ret;
2345
ebcdd39e
MR		 2346 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2347
7b911adc
TU		 2348 switch (fb->modifier[0]) {
2349 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2350 if (INTEL_INFO(dev)->gen >= 9)
2351 alignment = 256 * 1024;
2352 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2353 alignment = 128 * 1024;
a6c45cf0 2354 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2355 alignment = 4 * 1024;
2356 else
2357 alignment = 64 * 1024;
6b95a207 2358 break;
7b911adc 2359 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2360 if (INTEL_INFO(dev)->gen >= 9)
2361 alignment = 256 * 1024;
2362 else {
2363 /* pin() will align the object as required by fence */
2364 alignment = 0;
2365 }
6b95a207 2366 break;
7b911adc 2367 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2368 case I915_FORMAT_MOD_Yf_TILED:
2369 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2370 "Y tiling bo slipped through, driver bug!\n"))
2371 return -EINVAL;
2372 alignment = 1 * 1024 * 1024;
2373 break;
6b95a207 2374 default:
7b911adc
TU		 2375 MISSING_CASE(fb->modifier[0]);
2376 return -EINVAL;
6b95a207
KH		 2377 }
2378
f64b98cd
TU		 2379 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2380 if (ret)
2381 return ret;
2382
693db184
CW		 2383 /* Note that the w/a also requires 64 PTE of padding following the
2384 * bo. We currently fill all unused PTE with the shadow page and so
2385 * we should always have valid PTE following the scanout preventing
2386 * the VT-d warning.
2387 */
2388 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2389 alignment = 256 * 1024;
2390
d6dd6843
PZ		 2391 /*
2392 * Global gtt pte registers are special registers which actually forward
2393 * writes to a chunk of system memory. Which means that there is no risk
2394 * that the register values disappear as soon as we call
2395 * intel_runtime_pm_put(), so it is correct to wrap only the
2396 * pin/unpin/fence and not more.
2397 */
2398 intel_runtime_pm_get(dev_priv);
2399
ce453d81 2400 dev_priv->mm.interruptible = false;
e6617330 2401 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2402 &view);
48b956c5 2403 if (ret)
ce453d81 2404 goto err_interruptible;
6b95a207
KH		 2405
2406 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2407 * fence, whereas 965+ only requires a fence if using
2408 * framebuffer compression. For simplicity, we always install
2409 * a fence as the cost is not that onerous.
2410 */
06d98131 2411 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2412 if (ret)
2413 goto err_unpin;
1690e1eb 2414
9a5a53b3 2415 i915_gem_object_pin_fence(obj);
6b95a207 2416
ce453d81 2417 dev_priv->mm.interruptible = true;
d6dd6843 2418 intel_runtime_pm_put(dev_priv);
6b95a207 2419 return 0;
48b956c5
CW		 2420
2421err_unpin:
f64b98cd 2422 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2423err_interruptible:
2424 dev_priv->mm.interruptible = true;
d6dd6843 2425 intel_runtime_pm_put(dev_priv);
48b956c5 2426 return ret;
6b95a207
KH		 2427}
2428
82bc3b2d
TU		 2429static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2430 const struct drm_plane_state *plane_state)
1690e1eb 2431{
82bc3b2d 2432 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2433 struct i915_ggtt_view view;
2434 int ret;
82bc3b2d 2435
ebcdd39e
MR		 2436 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2437
f64b98cd
TU		 2438 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2439 WARN_ONCE(ret, "Couldn't get view from plane state!");
2440
1690e1eb 2441 i915_gem_object_unpin_fence(obj);
f64b98cd 2442 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2443}
2444
c2c75131
DV		 2445/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2446 * is assumed to be a power-of-two. */
bc752862
CW		 2447unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2448 unsigned int tiling_mode,
2449 unsigned int cpp,
2450 unsigned int pitch)
c2c75131 2451{
bc752862
CW		 2452 if (tiling_mode != I915_TILING_NONE) {
2453 unsigned int tile_rows, tiles;
c2c75131 2454
bc752862
CW		 2455 tile_rows = *y / 8;
2456 *y %= 8;
c2c75131 2457
bc752862
CW		 2458 tiles = *x / (512/cpp);
2459 *x %= 512/cpp;
2460
2461 return tile_rows * pitch * 8 + tiles * 4096;
2462 } else {
2463 unsigned int offset;
2464
2465 offset = *y * pitch + *x * cpp;
2466 *y = 0;
2467 *x = (offset & 4095) / cpp;
2468 return offset & -4096;
2469 }
c2c75131
DV		 2470}
2471
b35d63fa 2472static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2473{
2474 switch (format) {
2475 case DISPPLANE_8BPP:
2476 return DRM_FORMAT_C8;
2477 case DISPPLANE_BGRX555:
2478 return DRM_FORMAT_XRGB1555;
2479 case DISPPLANE_BGRX565:
2480 return DRM_FORMAT_RGB565;
2481 default:
2482 case DISPPLANE_BGRX888:
2483 return DRM_FORMAT_XRGB8888;
2484 case DISPPLANE_RGBX888:
2485 return DRM_FORMAT_XBGR8888;
2486 case DISPPLANE_BGRX101010:
2487 return DRM_FORMAT_XRGB2101010;
2488 case DISPPLANE_RGBX101010:
2489 return DRM_FORMAT_XBGR2101010;
2490 }
2491}
2492
bc8d7dff
DL		 2493static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2494{
2495 switch (format) {
2496 case PLANE_CTL_FORMAT_RGB_565:
2497 return DRM_FORMAT_RGB565;
2498 default:
2499 case PLANE_CTL_FORMAT_XRGB_8888:
2500 if (rgb_order) {
2501 if (alpha)
2502 return DRM_FORMAT_ABGR8888;
2503 else
2504 return DRM_FORMAT_XBGR8888;
2505 } else {
2506 if (alpha)
2507 return DRM_FORMAT_ARGB8888;
2508 else
2509 return DRM_FORMAT_XRGB8888;
2510 }
2511 case PLANE_CTL_FORMAT_XRGB_2101010:
2512 if (rgb_order)
2513 return DRM_FORMAT_XBGR2101010;
2514 else
2515 return DRM_FORMAT_XRGB2101010;
2516 }
2517}
2518
5724dbd1 2519static bool
f6936e29
DV		 2520intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2521 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2522{
2523 struct drm_device *dev = crtc->base.dev;
2524 struct drm_i915_gem_object *obj = NULL;
2525 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2526 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2527 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2528 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2529 PAGE_SIZE);
2530
2531 size_aligned -= base_aligned;
46f297fb 2532
ff2652ea
CW		 2533 if (plane_config->size == 0)
2534 return false;
2535
f37b5c2b
DV		 2536 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2537 base_aligned,
2538 base_aligned,
2539 size_aligned);
46f297fb 2540 if (!obj)
484b41dd 2541 return false;
46f297fb 2542
49af449b
DL		 2543 obj->tiling_mode = plane_config->tiling;
2544 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2545 obj->stride = fb->pitches[0];
46f297fb 2546
6bf129df
DL		 2547 mode_cmd.pixel_format = fb->pixel_format;
2548 mode_cmd.width = fb->width;
2549 mode_cmd.height = fb->height;
2550 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2551 mode_cmd.modifier[0] = fb->modifier[0];
2552 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2553
2554 mutex_lock(&dev->struct_mutex);
6bf129df 2555 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2556 &mode_cmd, obj)) {
46f297fb
JB		 2557 DRM_DEBUG_KMS("intel fb init failed\n");
2558 goto out_unref_obj;
2559 }
46f297fb 2560 mutex_unlock(&dev->struct_mutex);
484b41dd 2561
f6936e29 2562 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2563 return true;
46f297fb
JB		 2564
2565out_unref_obj:
2566 drm_gem_object_unreference(&obj->base);
2567 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2568 return false;
2569}
2570
afd65eb4
MR		 2571/* Update plane->state->fb to match plane->fb after driver-internal updates */
2572static void
2573update_state_fb(struct drm_plane *plane)
2574{
2575 if (plane->fb == plane->state->fb)
2576 return;
2577
2578 if (plane->state->fb)
2579 drm_framebuffer_unreference(plane->state->fb);
2580 plane->state->fb = plane->fb;
2581 if (plane->state->fb)
2582 drm_framebuffer_reference(plane->state->fb);
2583}
2584
5724dbd1 2585static void
f6936e29
DV		 2586intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2587 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2588{
2589 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2590 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2591 struct drm_crtc *c;
2592 struct intel_crtc *i;
2ff8fde1 2593 struct drm_i915_gem_object *obj;
88595ac9
DV		 2594 struct drm_plane *primary = intel_crtc->base.primary;
2595 struct drm_framebuffer *fb;
484b41dd 2596
2d14030b 2597 if (!plane_config->fb)
484b41dd
JB		 2598 return;
2599
f6936e29 2600 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2601 fb = &plane_config->fb->base;
2602 goto valid_fb;
f55548b5 2603 }
484b41dd 2604
2d14030b 2605 kfree(plane_config->fb);
484b41dd
JB		 2606
2607 /*
2608 * Failed to alloc the obj, check to see if we should share
2609 * an fb with another CRTC instead
2610 */
70e1e0ec 2611 for_each_crtc(dev, c) {
484b41dd
JB		 2612 i = to_intel_crtc(c);
2613
2614 if (c == &intel_crtc->base)
2615 continue;
2616
2ff8fde1
MR		 2617 if (!i->active)
2618 continue;
2619
88595ac9
DV		 2620 fb = c->primary->fb;
2621 if (!fb)
484b41dd
JB		 2622 continue;
2623
88595ac9 2624 obj = intel_fb_obj(fb);
2ff8fde1 2625 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2626 drm_framebuffer_reference(fb);
2627 goto valid_fb;
484b41dd
JB		 2628 }
2629 }
88595ac9
DV		 2630
2631 return;
2632
2633valid_fb:
2634 obj = intel_fb_obj(fb);
2635 if (obj->tiling_mode != I915_TILING_NONE)
2636 dev_priv->preserve_bios_swizzle = true;
2637
2638 primary->fb = fb;
2639 primary->state->crtc = &intel_crtc->base;
2640 primary->crtc = &intel_crtc->base;
2641 update_state_fb(primary);
2642 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2643}
2644
29b9bde6
DV		 2645static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2646 struct drm_framebuffer *fb,
2647 int x, int y)
81255565
JB		 2648{
2649 struct drm_device *dev = crtc->dev;
2650 struct drm_i915_private *dev_priv = dev->dev_private;
2651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2652 struct drm_plane *primary = crtc->primary;
2653 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2654 struct drm_i915_gem_object *obj;
81255565 2655 int plane = intel_crtc->plane;
e506a0c6 2656 unsigned long linear_offset;
81255565 2657 u32 dspcntr;
f45651ba 2658 u32 reg = DSPCNTR(plane);
48404c1e 2659 int pixel_size;
f45651ba 2660
b70709a6 2661 if (!visible || !fb) {
fdd508a6
VS		 2662 I915_WRITE(reg, 0);
2663 if (INTEL_INFO(dev)->gen >= 4)
2664 I915_WRITE(DSPSURF(plane), 0);
2665 else
2666 I915_WRITE(DSPADDR(plane), 0);
2667 POSTING_READ(reg);
2668 return;
2669 }
2670
c9ba6fad
VS		 2671 obj = intel_fb_obj(fb);
2672 if (WARN_ON(obj == NULL))
2673 return;
2674
2675 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2676
f45651ba
VS		 2677 dspcntr = DISPPLANE_GAMMA_ENABLE;
2678
fdd508a6 2679 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2680
2681 if (INTEL_INFO(dev)->gen < 4) {
2682 if (intel_crtc->pipe == PIPE_B)
2683 dspcntr |= DISPPLANE_SEL_PIPE_B;
2684
2685 /* pipesrc and dspsize control the size that is scaled from,
2686 * which should always be the user's requested size.
2687 */
2688 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2689 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2690 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2691 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2692 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2693 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2694 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2695 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2696 I915_WRITE(PRIMPOS(plane), 0);
2697 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2698 }
81255565 2699
57779d06
VS		 2700 switch (fb->pixel_format) {
2701 case DRM_FORMAT_C8:
81255565
JB		 2702 dspcntr |= DISPPLANE_8BPP;
2703 break;
57779d06
VS		 2704 case DRM_FORMAT_XRGB1555:
2705 case DRM_FORMAT_ARGB1555:
2706 dspcntr |= DISPPLANE_BGRX555;
81255565 2707 break;
57779d06
VS		 2708 case DRM_FORMAT_RGB565:
2709 dspcntr |= DISPPLANE_BGRX565;
2710 break;
2711 case DRM_FORMAT_XRGB8888:
2712 case DRM_FORMAT_ARGB8888:
2713 dspcntr |= DISPPLANE_BGRX888;
2714 break;
2715 case DRM_FORMAT_XBGR8888:
2716 case DRM_FORMAT_ABGR8888:
2717 dspcntr |= DISPPLANE_RGBX888;
2718 break;
2719 case DRM_FORMAT_XRGB2101010:
2720 case DRM_FORMAT_ARGB2101010:
2721 dspcntr |= DISPPLANE_BGRX101010;
2722 break;
2723 case DRM_FORMAT_XBGR2101010:
2724 case DRM_FORMAT_ABGR2101010:
2725 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2726 break;
2727 default:
baba133a 2728 BUG();
81255565 2729 }
57779d06 2730
f45651ba
VS		 2731 if (INTEL_INFO(dev)->gen >= 4 &&
2732 obj->tiling_mode != I915_TILING_NONE)
2733 dspcntr |= DISPPLANE_TILED;
81255565 2734
de1aa629
VS		 2735 if (IS_G4X(dev))
2736 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2737
b9897127 2738 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2739
c2c75131
DV		 2740 if (INTEL_INFO(dev)->gen >= 4) {
2741 intel_crtc->dspaddr_offset =
bc752862 2742 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2743 pixel_size,
bc752862 2744 fb->pitches[0]);
c2c75131
DV		 2745 linear_offset -= intel_crtc->dspaddr_offset;
2746 } else {
e506a0c6 2747 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2748 }
e506a0c6 2749
8e7d688b 2750 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2751 dspcntr |= DISPPLANE_ROTATE_180;
2752
6e3c9717
ACO		 2753 x += (intel_crtc->config->pipe_src_w - 1);
2754 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2755
2756 /* Finding the last pixel of the last line of the display
2757 data and adding to linear_offset*/
2758 linear_offset +=
6e3c9717
ACO		 2759 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2760 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2761 }
2762
2763 I915_WRITE(reg, dspcntr);
2764
01f2c773 2765 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2766 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2767 I915_WRITE(DSPSURF(plane),
2768 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2769 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2770 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2771 } else
f343c5f6 2772 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2773 POSTING_READ(reg);
17638cd6
JB		 2774}
2775
29b9bde6
DV		 2776static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2777 struct drm_framebuffer *fb,
2778 int x, int y)
17638cd6
JB		 2779{
2780 struct drm_device *dev = crtc->dev;
2781 struct drm_i915_private *dev_priv = dev->dev_private;
2782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2783 struct drm_plane *primary = crtc->primary;
2784 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2785 struct drm_i915_gem_object *obj;
17638cd6 2786 int plane = intel_crtc->plane;
e506a0c6 2787 unsigned long linear_offset;
17638cd6 2788 u32 dspcntr;
f45651ba 2789 u32 reg = DSPCNTR(plane);
48404c1e 2790 int pixel_size;
f45651ba 2791
b70709a6 2792 if (!visible || !fb) {
fdd508a6
VS		 2793 I915_WRITE(reg, 0);
2794 I915_WRITE(DSPSURF(plane), 0);
2795 POSTING_READ(reg);
2796 return;
2797 }
2798
c9ba6fad
VS		 2799 obj = intel_fb_obj(fb);
2800 if (WARN_ON(obj == NULL))
2801 return;
2802
2803 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2804
f45651ba
VS		 2805 dspcntr = DISPPLANE_GAMMA_ENABLE;
2806
fdd508a6 2807 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2808
2809 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2810 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2811
57779d06
VS		 2812 switch (fb->pixel_format) {
2813 case DRM_FORMAT_C8:
17638cd6
JB		 2814 dspcntr |= DISPPLANE_8BPP;
2815 break;
57779d06
VS		 2816 case DRM_FORMAT_RGB565:
2817 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2818 break;
57779d06
VS		 2819 case DRM_FORMAT_XRGB8888:
2820 case DRM_FORMAT_ARGB8888:
2821 dspcntr |= DISPPLANE_BGRX888;
2822 break;
2823 case DRM_FORMAT_XBGR8888:
2824 case DRM_FORMAT_ABGR8888:
2825 dspcntr |= DISPPLANE_RGBX888;
2826 break;
2827 case DRM_FORMAT_XRGB2101010:
2828 case DRM_FORMAT_ARGB2101010:
2829 dspcntr |= DISPPLANE_BGRX101010;
2830 break;
2831 case DRM_FORMAT_XBGR2101010:
2832 case DRM_FORMAT_ABGR2101010:
2833 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2834 break;
2835 default:
baba133a 2836 BUG();
17638cd6
JB		 2837 }
2838
2839 if (obj->tiling_mode != I915_TILING_NONE)
2840 dspcntr |= DISPPLANE_TILED;
17638cd6 2841
f45651ba 2842 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2843 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2844
b9897127 2845 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2846 intel_crtc->dspaddr_offset =
bc752862 2847 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2848 pixel_size,
bc752862 2849 fb->pitches[0]);
c2c75131 2850 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2851 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2852 dspcntr |= DISPPLANE_ROTATE_180;
2853
2854 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2855 x += (intel_crtc->config->pipe_src_w - 1);
2856 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2857
2858 /* Finding the last pixel of the last line of the display
2859 data and adding to linear_offset*/
2860 linear_offset +=
6e3c9717
ACO		 2861 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2862 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2863 }
2864 }
2865
2866 I915_WRITE(reg, dspcntr);
17638cd6 2867
01f2c773 2868 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2869 I915_WRITE(DSPSURF(plane),
2870 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2871 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2872 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2873 } else {
2874 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2875 I915_WRITE(DSPLINOFF(plane), linear_offset);
2876 }
17638cd6 2877 POSTING_READ(reg);
17638cd6
JB		 2878}
2879
b321803d
DL		 2880u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2881 uint32_t pixel_format)
2882{
2883 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2884
2885 /*
2886 * The stride is either expressed as a multiple of 64 bytes
2887 * chunks for linear buffers or in number of tiles for tiled
2888 * buffers.
2889 */
2890 switch (fb_modifier) {
2891 case DRM_FORMAT_MOD_NONE:
2892 return 64;
2893 case I915_FORMAT_MOD_X_TILED:
2894 if (INTEL_INFO(dev)->gen == 2)
2895 return 128;
2896 return 512;
2897 case I915_FORMAT_MOD_Y_TILED:
2898 /* No need to check for old gens and Y tiling since this is
2899 * about the display engine and those will be blocked before
2900 * we get here.
2901 */
2902 return 128;
2903 case I915_FORMAT_MOD_Yf_TILED:
2904 if (bits_per_pixel == 8)
2905 return 64;
2906 else
2907 return 128;
2908 default:
2909 MISSING_CASE(fb_modifier);
2910 return 64;
2911 }
2912}
2913
121920fa
TU		 2914unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2915 struct drm_i915_gem_object *obj)
2916{
9abc4648 2917 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2918
2919 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2920 view = &i915_ggtt_view_rotated;
121920fa
TU		 2921
2922 return i915_gem_obj_ggtt_offset_view(obj, view);
2923}
2924
a1b2278e
CK		 2925/*
2926 * This function detaches (aka. unbinds) unused scalers in hardware
2927 */
2928void skl_detach_scalers(struct intel_crtc *intel_crtc)
2929{
2930 struct drm_device *dev;
2931 struct drm_i915_private *dev_priv;
2932 struct intel_crtc_scaler_state *scaler_state;
2933 int i;
2934
2935 if (!intel_crtc || !intel_crtc->config)
2936 return;
2937
2938 dev = intel_crtc->base.dev;
2939 dev_priv = dev->dev_private;
2940 scaler_state = &intel_crtc->config->scaler_state;
2941
2942 /* loop through and disable scalers that aren't in use */
2943 for (i = 0; i < intel_crtc->num_scalers; i++) {
2944 if (!scaler_state->scalers[i].in_use) {
2945 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2946 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2947 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2948 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2949 intel_crtc->base.base.id, intel_crtc->pipe, i);
2950 }
2951 }
2952}
2953
6156a456 2954u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2955{
6156a456 2956 switch (pixel_format) {
d161cf7a 2957 case DRM_FORMAT_C8:
c34ce3d1 2958 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2959 case DRM_FORMAT_RGB565:
c34ce3d1 2960 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2961 case DRM_FORMAT_XBGR8888:
c34ce3d1 2962 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2963 case DRM_FORMAT_XRGB8888:
c34ce3d1 2964 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2965 /*
2966 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2967 * to be already pre-multiplied. We need to add a knob (or a different
2968 * DRM_FORMAT) for user-space to configure that.
2969 */
f75fb42a 2970 case DRM_FORMAT_ABGR8888:
c34ce3d1 2971 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2972 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2973 case DRM_FORMAT_ARGB8888:
c34ce3d1 2974 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2975 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2976 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2977 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2978 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2979 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2980 case DRM_FORMAT_YUYV:
c34ce3d1 2981 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2982 case DRM_FORMAT_YVYU:
c34ce3d1 2983 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2984 case DRM_FORMAT_UYVY:
c34ce3d1 2985 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2986 case DRM_FORMAT_VYUY:
c34ce3d1 2987 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2988 default:
4249eeef 2989 MISSING_CASE(pixel_format);
70d21f0e 2990 }
8cfcba41 2991
c34ce3d1 2992 return 0;
6156a456 2993}
70d21f0e 2994
6156a456
CK		 2995u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2996{
6156a456 2997 switch (fb_modifier) {
30af77c4 2998 case DRM_FORMAT_MOD_NONE:
70d21f0e 2999 break;
30af77c4 3000 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 3001 return PLANE_CTL_TILED_X;
b321803d 3002 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 3003 return PLANE_CTL_TILED_Y;
b321803d 3004 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 3005 return PLANE_CTL_TILED_YF;
70d21f0e 3006 default:
6156a456 3007 MISSING_CASE(fb_modifier);
70d21f0e 3008 }
8cfcba41 3009
c34ce3d1 3010 return 0;
6156a456 3011}
70d21f0e 3012
6156a456
CK		 3013u32 skl_plane_ctl_rotation(unsigned int rotation)
3014{
3b7a5119 3015 switch (rotation) {
6156a456
CK		 3016 case BIT(DRM_ROTATE_0):
3017 break;
3b7a5119 3018 case BIT(DRM_ROTATE_90):
c34ce3d1 3019 return PLANE_CTL_ROTATE_90;
3b7a5119 3020 case BIT(DRM_ROTATE_180):
c34ce3d1 3021 return PLANE_CTL_ROTATE_180;
3b7a5119 3022 case BIT(DRM_ROTATE_270):
c34ce3d1 3023 return PLANE_CTL_ROTATE_270;
6156a456
CK		 3024 default:
3025 MISSING_CASE(rotation);
3026 }
3027
c34ce3d1 3028 return 0;
6156a456
CK		 3029}
3030
3031static void skylake_update_primary_plane(struct drm_crtc *crtc,
3032 struct drm_framebuffer *fb,
3033 int x, int y)
3034{
3035 struct drm_device *dev = crtc->dev;
3036 struct drm_i915_private *dev_priv = dev->dev_private;
3037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3038 struct drm_plane *plane = crtc->primary;
3039 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3040 struct drm_i915_gem_object *obj;
3041 int pipe = intel_crtc->pipe;
3042 u32 plane_ctl, stride_div, stride;
3043 u32 tile_height, plane_offset, plane_size;
3044 unsigned int rotation;
3045 int x_offset, y_offset;
3046 unsigned long surf_addr;
6156a456
CK		 3047 struct intel_crtc_state *crtc_state = intel_crtc->config;
3048 struct intel_plane_state *plane_state;
3049 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3050 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3051 int scaler_id = -1;
3052
6156a456
CK		 3053 plane_state = to_intel_plane_state(plane->state);
3054
b70709a6 3055 if (!visible || !fb) {
6156a456
CK		 3056 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3057 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3058 POSTING_READ(PLANE_CTL(pipe, 0));
3059 return;
3b7a5119 3060 }
70d21f0e 3061
6156a456
CK		 3062 plane_ctl = PLANE_CTL_ENABLE |
3063 PLANE_CTL_PIPE_GAMMA_ENABLE |
3064 PLANE_CTL_PIPE_CSC_ENABLE;
3065
3066 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3067 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3068 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3069
3070 rotation = plane->state->rotation;
3071 plane_ctl |= skl_plane_ctl_rotation(rotation);
3072
b321803d
DL		 3073 obj = intel_fb_obj(fb);
3074 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3075 fb->pixel_format);
3b7a5119
SJ		 3076 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3077
6156a456
CK		 3078 /*
3079 * FIXME: intel_plane_state->src, dst aren't set when transitional
3080 * update_plane helpers are called from legacy paths.
3081 * Once full atomic crtc is available, below check can be avoided.
3082 */
3083 if (drm_rect_width(&plane_state->src)) {
3084 scaler_id = plane_state->scaler_id;
3085 src_x = plane_state->src.x1 >> 16;
3086 src_y = plane_state->src.y1 >> 16;
3087 src_w = drm_rect_width(&plane_state->src) >> 16;
3088 src_h = drm_rect_height(&plane_state->src) >> 16;
3089 dst_x = plane_state->dst.x1;
3090 dst_y = plane_state->dst.y1;
3091 dst_w = drm_rect_width(&plane_state->dst);
3092 dst_h = drm_rect_height(&plane_state->dst);
3093
3094 WARN_ON(x != src_x || y != src_y);
3095 } else {
3096 src_w = intel_crtc->config->pipe_src_w;
3097 src_h = intel_crtc->config->pipe_src_h;
3098 }
3099
3b7a5119
SJ		 3100 if (intel_rotation_90_or_270(rotation)) {
3101 /* stride = Surface height in tiles */
2614f17d 3102 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3103 fb->modifier[0]);
3104 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3105 x_offset = stride * tile_height - y - src_h;
3b7a5119 3106 y_offset = x;
6156a456 3107 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3108 } else {
3109 stride = fb->pitches[0] / stride_div;
3110 x_offset = x;
3111 y_offset = y;
6156a456 3112 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3113 }
3114 plane_offset = y_offset << 16 | x_offset;
b321803d 3115
70d21f0e 3116 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3117 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3118 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3119 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3120
3121 if (scaler_id >= 0) {
3122 uint32_t ps_ctrl = 0;
3123
3124 WARN_ON(!dst_w || !dst_h);
3125 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3126 crtc_state->scaler_state.scalers[scaler_id].mode;
3127 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3128 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3129 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3130 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3131 I915_WRITE(PLANE_POS(pipe, 0), 0);
3132 } else {
3133 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3134 }
3135
121920fa 3136 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3137
3138 POSTING_READ(PLANE_SURF(pipe, 0));
3139}
3140
17638cd6
JB		 3141/* Assume fb object is pinned & idle & fenced and just update base pointers */
3142static int
3143intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3144 int x, int y, enum mode_set_atomic state)
3145{
3146 struct drm_device *dev = crtc->dev;
3147 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3148
6b8e6ed0
CW		 3149 if (dev_priv->display.disable_fbc)
3150 dev_priv->display.disable_fbc(dev);
81255565 3151
29b9bde6
DV		 3152 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3153
3154 return 0;
81255565
JB		 3155}
3156
7514747d 3157static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3158{
96a02917
VS		 3159 struct drm_crtc *crtc;
3160
70e1e0ec 3161 for_each_crtc(dev, crtc) {
96a02917
VS		 3162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3163 enum plane plane = intel_crtc->plane;
3164
3165 intel_prepare_page_flip(dev, plane);
3166 intel_finish_page_flip_plane(dev, plane);
3167 }
7514747d
VS		 3168}
3169
3170static void intel_update_primary_planes(struct drm_device *dev)
3171{
3172 struct drm_i915_private *dev_priv = dev->dev_private;
3173 struct drm_crtc *crtc;
96a02917 3174
70e1e0ec 3175 for_each_crtc(dev, crtc) {
96a02917
VS		 3176 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3177
51fd371b 3178 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3179 /*
3180 * FIXME: Once we have proper support for primary planes (and
3181 * disabling them without disabling the entire crtc) allow again
66e514c1 3182 * a NULL crtc->primary->fb.
947fdaad 3183 */
f4510a27 3184 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3185 dev_priv->display.update_primary_plane(crtc,
66e514c1 3186 crtc->primary->fb,
262ca2b0
MR		 3187 crtc->x,
3188 crtc->y);
51fd371b 3189 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3190 }
3191}
3192
ce22dba9
ML		 3193void intel_crtc_reset(struct intel_crtc *crtc)
3194{
3195 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3196
3197 if (!crtc->active)
3198 return;
3199
3200 intel_crtc_disable_planes(&crtc->base);
3201 dev_priv->display.crtc_disable(&crtc->base);
3202 dev_priv->display.crtc_enable(&crtc->base);
3203 intel_crtc_enable_planes(&crtc->base);
3204}
3205
7514747d
VS		 3206void intel_prepare_reset(struct drm_device *dev)
3207{
f98ce92f
VS		 3208 struct drm_i915_private *dev_priv = to_i915(dev);
3209 struct intel_crtc *crtc;
3210
7514747d
VS		 3211 /* no reset support for gen2 */
3212 if (IS_GEN2(dev))
3213 return;
3214
3215 /* reset doesn't touch the display */
3216 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3217 return;
3218
3219 drm_modeset_lock_all(dev);
f98ce92f
VS		 3220
3221 /*
3222 * Disabling the crtcs gracefully seems nicer. Also the
3223 * g33 docs say we should at least disable all the planes.
3224 */
3225 for_each_intel_crtc(dev, crtc) {
ce22dba9
ML		 3226 if (!crtc->active)
3227 continue;
3228
3229 intel_crtc_disable_planes(&crtc->base);
3230 dev_priv->display.crtc_disable(&crtc->base);
f98ce92f 3231 }
7514747d
VS		 3232}
3233
3234void intel_finish_reset(struct drm_device *dev)
3235{
3236 struct drm_i915_private *dev_priv = to_i915(dev);
3237
3238 /*
3239 * Flips in the rings will be nuked by the reset,
3240 * so complete all pending flips so that user space
3241 * will get its events and not get stuck.
3242 */
3243 intel_complete_page_flips(dev);
3244
3245 /* no reset support for gen2 */
3246 if (IS_GEN2(dev))
3247 return;
3248
3249 /* reset doesn't touch the display */
3250 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3251 /*
3252 * Flips in the rings have been nuked by the reset,
3253 * so update the base address of all primary
3254 * planes to the the last fb to make sure we're
3255 * showing the correct fb after a reset.
3256 */
3257 intel_update_primary_planes(dev);
3258 return;
3259 }
3260
3261 /*
3262 * The display has been reset as well,
3263 * so need a full re-initialization.
3264 */
3265 intel_runtime_pm_disable_interrupts(dev_priv);
3266 intel_runtime_pm_enable_interrupts(dev_priv);
3267
3268 intel_modeset_init_hw(dev);
3269
3270 spin_lock_irq(&dev_priv->irq_lock);
3271 if (dev_priv->display.hpd_irq_setup)
3272 dev_priv->display.hpd_irq_setup(dev);
3273 spin_unlock_irq(&dev_priv->irq_lock);
3274
3275 intel_modeset_setup_hw_state(dev, true);
3276
3277 intel_hpd_init(dev_priv);
3278
3279 drm_modeset_unlock_all(dev);
3280}
3281
2e2f351d 3282static void
14667a4b
CW		 3283intel_finish_fb(struct drm_framebuffer *old_fb)
3284{
2ff8fde1 3285 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3286 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3287 bool was_interruptible = dev_priv->mm.interruptible;
3288 int ret;
3289
14667a4b
CW		 3290 /* Big Hammer, we also need to ensure that any pending
3291 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3292 * current scanout is retired before unpinning the old
2e2f351d
CW		 3293 * framebuffer. Note that we rely on userspace rendering
3294 * into the buffer attached to the pipe they are waiting
3295 * on. If not, userspace generates a GPU hang with IPEHR
3296 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3297 *
3298 * This should only fail upon a hung GPU, in which case we
3299 * can safely continue.
3300 */
3301 dev_priv->mm.interruptible = false;
2e2f351d 3302 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3303 dev_priv->mm.interruptible = was_interruptible;
3304
2e2f351d 3305 WARN_ON(ret);
14667a4b
CW		 3306}
3307
7d5e3799
CW		 3308static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3309{
3310 struct drm_device *dev = crtc->dev;
3311 struct drm_i915_private *dev_priv = dev->dev_private;
3312 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3313 bool pending;
3314
3315 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3316 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3317 return false;
3318
5e2d7afc 3319 spin_lock_irq(&dev->event_lock);
7d5e3799 3320 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3321 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3322
3323 return pending;
3324}
3325
e30e8f75
GP		 3326static void intel_update_pipe_size(struct intel_crtc *crtc)
3327{
3328 struct drm_device *dev = crtc->base.dev;
3329 struct drm_i915_private *dev_priv = dev->dev_private;
3330 const struct drm_display_mode *adjusted_mode;
3331
3332 if (!i915.fastboot)
3333 return;
3334
3335 /*
3336 * Update pipe size and adjust fitter if needed: the reason for this is
3337 * that in compute_mode_changes we check the native mode (not the pfit
3338 * mode) to see if we can flip rather than do a full mode set. In the
3339 * fastboot case, we'll flip, but if we don't update the pipesrc and
3340 * pfit state, we'll end up with a big fb scanned out into the wrong
3341 * sized surface.
3342 *
3343 * To fix this properly, we need to hoist the checks up into
3344 * compute_mode_changes (or above), check the actual pfit state and
3345 * whether the platform allows pfit disable with pipe active, and only
3346 * then update the pipesrc and pfit state, even on the flip path.
3347 */
3348
6e3c9717 3349 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3350
3351 I915_WRITE(PIPESRC(crtc->pipe),
3352 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3353 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3354 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3355 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3356 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3357 I915_WRITE(PF_CTL(crtc->pipe), 0);
3358 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3359 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3360 }
6e3c9717
ACO		 3361 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3362 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3363}
3364
5e84e1a4
ZW		 3365static void intel_fdi_normal_train(struct drm_crtc *crtc)
3366{
3367 struct drm_device *dev = crtc->dev;
3368 struct drm_i915_private *dev_priv = dev->dev_private;
3369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3370 int pipe = intel_crtc->pipe;
3371 u32 reg, temp;
3372
3373 /* enable normal train */
3374 reg = FDI_TX_CTL(pipe);
3375 temp = I915_READ(reg);
61e499bf 3376 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3377 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3378 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3379 } else {
3380 temp &= ~FDI_LINK_TRAIN_NONE;
3381 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3382 }
5e84e1a4
ZW		 3383 I915_WRITE(reg, temp);
3384
3385 reg = FDI_RX_CTL(pipe);
3386 temp = I915_READ(reg);
3387 if (HAS_PCH_CPT(dev)) {
3388 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3389 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3390 } else {
3391 temp &= ~FDI_LINK_TRAIN_NONE;
3392 temp |= FDI_LINK_TRAIN_NONE;
3393 }
3394 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3395
3396 /* wait one idle pattern time */
3397 POSTING_READ(reg);
3398 udelay(1000);
357555c0
JB		 3399
3400 /* IVB wants error correction enabled */
3401 if (IS_IVYBRIDGE(dev))
3402 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3403 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3404}
3405
8db9d77b
ZW		 3406/* The FDI link training functions for ILK/Ibexpeak. */
3407static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3408{
3409 struct drm_device *dev = crtc->dev;
3410 struct drm_i915_private *dev_priv = dev->dev_private;
3411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3412 int pipe = intel_crtc->pipe;
5eddb70b 3413 u32 reg, temp, tries;
8db9d77b 3414
1c8562f6 3415 /* FDI needs bits from pipe first */
0fc932b8 3416 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3417
e1a44743
AJ		 3418 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3419 for train result */
5eddb70b
CW		 3420 reg = FDI_RX_IMR(pipe);
3421 temp = I915_READ(reg);
e1a44743
AJ		 3422 temp &= ~FDI_RX_SYMBOL_LOCK;
3423 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3424 I915_WRITE(reg, temp);
3425 I915_READ(reg);
e1a44743
AJ		 3426 udelay(150);
3427
8db9d77b 3428 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3429 reg = FDI_TX_CTL(pipe);
3430 temp = I915_READ(reg);
627eb5a3 3431 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3432 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3433 temp &= ~FDI_LINK_TRAIN_NONE;
3434 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3435 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3436
5eddb70b
CW		 3437 reg = FDI_RX_CTL(pipe);
3438 temp = I915_READ(reg);
8db9d77b
ZW		 3439 temp &= ~FDI_LINK_TRAIN_NONE;
3440 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3441 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3442
3443 POSTING_READ(reg);
8db9d77b
ZW		 3444 udelay(150);
3445
5b2adf89 3446 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3447 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3448 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3449 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3450
5eddb70b 3451 reg = FDI_RX_IIR(pipe);
e1a44743 3452 for (tries = 0; tries < 5; tries++) {
5eddb70b 3453 temp = I915_READ(reg);
8db9d77b
ZW		 3454 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3455
3456 if ((temp & FDI_RX_BIT_LOCK)) {
3457 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3458 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3459 break;
3460 }
8db9d77b 3461 }
e1a44743 3462 if (tries == 5)
5eddb70b 3463 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3464
3465 /* Train 2 */
5eddb70b
CW		 3466 reg = FDI_TX_CTL(pipe);
3467 temp = I915_READ(reg);
8db9d77b
ZW		 3468 temp &= ~FDI_LINK_TRAIN_NONE;
3469 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3470 I915_WRITE(reg, temp);
8db9d77b 3471
5eddb70b
CW		 3472 reg = FDI_RX_CTL(pipe);
3473 temp = I915_READ(reg);
8db9d77b
ZW		 3474 temp &= ~FDI_LINK_TRAIN_NONE;
3475 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3476 I915_WRITE(reg, temp);
8db9d77b 3477
5eddb70b
CW		 3478 POSTING_READ(reg);
3479 udelay(150);
8db9d77b 3480
5eddb70b 3481 reg = FDI_RX_IIR(pipe);
e1a44743 3482 for (tries = 0; tries < 5; tries++) {
5eddb70b 3483 temp = I915_READ(reg);
8db9d77b
ZW		 3484 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3485
3486 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3487 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3488 DRM_DEBUG_KMS("FDI train 2 done.\n");
3489 break;
3490 }
8db9d77b 3491 }
e1a44743 3492 if (tries == 5)
5eddb70b 3493 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3494
3495 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3496
8db9d77b
ZW		 3497}
3498
0206e353 3499static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3500 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3501 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3502 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3503 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3504};
3505
3506/* The FDI link training functions for SNB/Cougarpoint. */
3507static void gen6_fdi_link_train(struct drm_crtc *crtc)
3508{
3509 struct drm_device *dev = crtc->dev;
3510 struct drm_i915_private *dev_priv = dev->dev_private;
3511 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3512 int pipe = intel_crtc->pipe;
fa37d39e 3513 u32 reg, temp, i, retry;
8db9d77b 3514
e1a44743
AJ		 3515 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3516 for train result */
5eddb70b
CW		 3517 reg = FDI_RX_IMR(pipe);
3518 temp = I915_READ(reg);
e1a44743
AJ		 3519 temp &= ~FDI_RX_SYMBOL_LOCK;
3520 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3521 I915_WRITE(reg, temp);
3522
3523 POSTING_READ(reg);
e1a44743
AJ		 3524 udelay(150);
3525
8db9d77b 3526 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3527 reg = FDI_TX_CTL(pipe);
3528 temp = I915_READ(reg);
627eb5a3 3529 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3530 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3531 temp &= ~FDI_LINK_TRAIN_NONE;
3532 temp |= FDI_LINK_TRAIN_PATTERN_1;
3533 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3534 /* SNB-B */
3535 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3536 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3537
d74cf324
DV		 3538 I915_WRITE(FDI_RX_MISC(pipe),
3539 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3540
5eddb70b
CW		 3541 reg = FDI_RX_CTL(pipe);
3542 temp = I915_READ(reg);
8db9d77b
ZW		 3543 if (HAS_PCH_CPT(dev)) {
3544 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3545 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3546 } else {
3547 temp &= ~FDI_LINK_TRAIN_NONE;
3548 temp |= FDI_LINK_TRAIN_PATTERN_1;
3549 }
5eddb70b
CW		 3550 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3551
3552 POSTING_READ(reg);
8db9d77b
ZW		 3553 udelay(150);
3554
0206e353 3555 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3556 reg = FDI_TX_CTL(pipe);
3557 temp = I915_READ(reg);
8db9d77b
ZW		 3558 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3559 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3560 I915_WRITE(reg, temp);
3561
3562 POSTING_READ(reg);
8db9d77b
ZW		 3563 udelay(500);
3564
fa37d39e
SP		 3565 for (retry = 0; retry < 5; retry++) {
3566 reg = FDI_RX_IIR(pipe);
3567 temp = I915_READ(reg);
3568 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3569 if (temp & FDI_RX_BIT_LOCK) {
3570 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3571 DRM_DEBUG_KMS("FDI train 1 done.\n");
3572 break;
3573 }
3574 udelay(50);
8db9d77b 3575 }
fa37d39e
SP		 3576 if (retry < 5)
3577 break;
8db9d77b
ZW		 3578 }
3579 if (i == 4)
5eddb70b 3580 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3581
3582 /* Train 2 */
5eddb70b
CW		 3583 reg = FDI_TX_CTL(pipe);
3584 temp = I915_READ(reg);
8db9d77b
ZW		 3585 temp &= ~FDI_LINK_TRAIN_NONE;
3586 temp |= FDI_LINK_TRAIN_PATTERN_2;
3587 if (IS_GEN6(dev)) {
3588 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3589 /* SNB-B */
3590 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3591 }
5eddb70b 3592 I915_WRITE(reg, temp);
8db9d77b 3593
5eddb70b
CW		 3594 reg = FDI_RX_CTL(pipe);
3595 temp = I915_READ(reg);
8db9d77b
ZW		 3596 if (HAS_PCH_CPT(dev)) {
3597 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3598 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3599 } else {
3600 temp &= ~FDI_LINK_TRAIN_NONE;
3601 temp |= FDI_LINK_TRAIN_PATTERN_2;
3602 }
5eddb70b
CW		 3603 I915_WRITE(reg, temp);
3604
3605 POSTING_READ(reg);
8db9d77b
ZW		 3606 udelay(150);
3607
0206e353 3608 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3609 reg = FDI_TX_CTL(pipe);
3610 temp = I915_READ(reg);
8db9d77b
ZW		 3611 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3612 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3613 I915_WRITE(reg, temp);
3614
3615 POSTING_READ(reg);
8db9d77b
ZW		 3616 udelay(500);
3617
fa37d39e
SP		 3618 for (retry = 0; retry < 5; retry++) {
3619 reg = FDI_RX_IIR(pipe);
3620 temp = I915_READ(reg);
3621 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3622 if (temp & FDI_RX_SYMBOL_LOCK) {
3623 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3624 DRM_DEBUG_KMS("FDI train 2 done.\n");
3625 break;
3626 }
3627 udelay(50);
8db9d77b 3628 }
fa37d39e
SP		 3629 if (retry < 5)
3630 break;
8db9d77b
ZW		 3631 }
3632 if (i == 4)
5eddb70b 3633 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3634
3635 DRM_DEBUG_KMS("FDI train done.\n");
3636}
3637
357555c0
JB		 3638/* Manual link training for Ivy Bridge A0 parts */
3639static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3640{
3641 struct drm_device *dev = crtc->dev;
3642 struct drm_i915_private *dev_priv = dev->dev_private;
3643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3644 int pipe = intel_crtc->pipe;
139ccd3f 3645 u32 reg, temp, i, j;
357555c0
JB		 3646
3647 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3648 for train result */
3649 reg = FDI_RX_IMR(pipe);
3650 temp = I915_READ(reg);
3651 temp &= ~FDI_RX_SYMBOL_LOCK;
3652 temp &= ~FDI_RX_BIT_LOCK;
3653 I915_WRITE(reg, temp);
3654
3655 POSTING_READ(reg);
3656 udelay(150);
3657
01a415fd
DV		 3658 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3659 I915_READ(FDI_RX_IIR(pipe)));
3660
139ccd3f
JB		 3661 /* Try each vswing and preemphasis setting twice before moving on */
3662 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3663 /* disable first in case we need to retry */
3664 reg = FDI_TX_CTL(pipe);
3665 temp = I915_READ(reg);
3666 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3667 temp &= ~FDI_TX_ENABLE;
3668 I915_WRITE(reg, temp);
357555c0 3669
139ccd3f
JB		 3670 reg = FDI_RX_CTL(pipe);
3671 temp = I915_READ(reg);
3672 temp &= ~FDI_LINK_TRAIN_AUTO;
3673 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3674 temp &= ~FDI_RX_ENABLE;
3675 I915_WRITE(reg, temp);
357555c0 3676
139ccd3f 3677 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3678 reg = FDI_TX_CTL(pipe);
3679 temp = I915_READ(reg);
139ccd3f 3680 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3681 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3682 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3683 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3684 temp |= snb_b_fdi_train_param[j/2];
3685 temp |= FDI_COMPOSITE_SYNC;
3686 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3687
139ccd3f
JB		 3688 I915_WRITE(FDI_RX_MISC(pipe),
3689 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3690
139ccd3f 3691 reg = FDI_RX_CTL(pipe);
357555c0 3692 temp = I915_READ(reg);
139ccd3f
JB		 3693 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3694 temp |= FDI_COMPOSITE_SYNC;
3695 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3696
139ccd3f
JB		 3697 POSTING_READ(reg);
3698 udelay(1); /* should be 0.5us */
357555c0 3699
139ccd3f
JB		 3700 for (i = 0; i < 4; i++) {
3701 reg = FDI_RX_IIR(pipe);
3702 temp = I915_READ(reg);
3703 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3704
139ccd3f
JB		 3705 if (temp & FDI_RX_BIT_LOCK ||
3706 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3707 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3708 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3709 i);
3710 break;
3711 }
3712 udelay(1); /* should be 0.5us */
3713 }
3714 if (i == 4) {
3715 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3716 continue;
3717 }
357555c0 3718
139ccd3f 3719 /* Train 2 */
357555c0
JB		 3720 reg = FDI_TX_CTL(pipe);
3721 temp = I915_READ(reg);
139ccd3f
JB		 3722 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3723 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3724 I915_WRITE(reg, temp);
3725
3726 reg = FDI_RX_CTL(pipe);
3727 temp = I915_READ(reg);
3728 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3729 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3730 I915_WRITE(reg, temp);
3731
3732 POSTING_READ(reg);
139ccd3f 3733 udelay(2); /* should be 1.5us */
357555c0 3734
139ccd3f
JB		 3735 for (i = 0; i < 4; i++) {
3736 reg = FDI_RX_IIR(pipe);
3737 temp = I915_READ(reg);
3738 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3739
139ccd3f
JB		 3740 if (temp & FDI_RX_SYMBOL_LOCK ||
3741 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3742 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3743 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3744 i);
3745 goto train_done;
3746 }
3747 udelay(2); /* should be 1.5us */
357555c0 3748 }
139ccd3f
JB		 3749 if (i == 4)
3750 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3751 }
357555c0 3752
139ccd3f 3753train_done:
357555c0
JB		 3754 DRM_DEBUG_KMS("FDI train done.\n");
3755}
3756
88cefb6c 3757static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3758{
88cefb6c 3759 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3760 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3761 int pipe = intel_crtc->pipe;
5eddb70b 3762 u32 reg, temp;
79e53945 3763
c64e311e 3764
c98e9dcf 3765 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3766 reg = FDI_RX_CTL(pipe);
3767 temp = I915_READ(reg);
627eb5a3 3768 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3769 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3770 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3771 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3772
3773 POSTING_READ(reg);
c98e9dcf
JB		 3774 udelay(200);
3775
3776 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3777 temp = I915_READ(reg);
3778 I915_WRITE(reg, temp | FDI_PCDCLK);
3779
3780 POSTING_READ(reg);
c98e9dcf
JB		 3781 udelay(200);
3782
20749730
PZ		 3783 /* Enable CPU FDI TX PLL, always on for Ironlake */
3784 reg = FDI_TX_CTL(pipe);
3785 temp = I915_READ(reg);
3786 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3787 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3788
20749730
PZ		 3789 POSTING_READ(reg);
3790 udelay(100);
6be4a607 3791 }
0e23b99d
JB		 3792}
3793
88cefb6c
DV		 3794static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3795{
3796 struct drm_device *dev = intel_crtc->base.dev;
3797 struct drm_i915_private *dev_priv = dev->dev_private;
3798 int pipe = intel_crtc->pipe;
3799 u32 reg, temp;
3800
3801 /* Switch from PCDclk to Rawclk */
3802 reg = FDI_RX_CTL(pipe);
3803 temp = I915_READ(reg);
3804 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3805
3806 /* Disable CPU FDI TX PLL */
3807 reg = FDI_TX_CTL(pipe);
3808 temp = I915_READ(reg);
3809 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3810
3811 POSTING_READ(reg);
3812 udelay(100);
3813
3814 reg = FDI_RX_CTL(pipe);
3815 temp = I915_READ(reg);
3816 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3817
3818 /* Wait for the clocks to turn off. */
3819 POSTING_READ(reg);
3820 udelay(100);
3821}
3822
0fc932b8
JB		 3823static void ironlake_fdi_disable(struct drm_crtc *crtc)
3824{
3825 struct drm_device *dev = crtc->dev;
3826 struct drm_i915_private *dev_priv = dev->dev_private;
3827 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3828 int pipe = intel_crtc->pipe;
3829 u32 reg, temp;
3830
3831 /* disable CPU FDI tx and PCH FDI rx */
3832 reg = FDI_TX_CTL(pipe);
3833 temp = I915_READ(reg);
3834 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3835 POSTING_READ(reg);
3836
3837 reg = FDI_RX_CTL(pipe);
3838 temp = I915_READ(reg);
3839 temp &= ~(0x7 << 16);
dfd07d72 3840 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3841 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3842
3843 POSTING_READ(reg);
3844 udelay(100);
3845
3846 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3847 if (HAS_PCH_IBX(dev))
6f06ce18 3848 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3849
3850 /* still set train pattern 1 */
3851 reg = FDI_TX_CTL(pipe);
3852 temp = I915_READ(reg);
3853 temp &= ~FDI_LINK_TRAIN_NONE;
3854 temp |= FDI_LINK_TRAIN_PATTERN_1;
3855 I915_WRITE(reg, temp);
3856
3857 reg = FDI_RX_CTL(pipe);
3858 temp = I915_READ(reg);
3859 if (HAS_PCH_CPT(dev)) {
3860 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3861 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3862 } else {
3863 temp &= ~FDI_LINK_TRAIN_NONE;
3864 temp |= FDI_LINK_TRAIN_PATTERN_1;
3865 }
3866 /* BPC in FDI rx is consistent with that in PIPECONF */
3867 temp &= ~(0x07 << 16);
dfd07d72 3868 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3869 I915_WRITE(reg, temp);
3870
3871 POSTING_READ(reg);
3872 udelay(100);
3873}
3874
5dce5b93
CW		 3875bool intel_has_pending_fb_unpin(struct drm_device *dev)
3876{
3877 struct intel_crtc *crtc;
3878
3879 /* Note that we don't need to be called with mode_config.lock here
3880 * as our list of CRTC objects is static for the lifetime of the
3881 * device and so cannot disappear as we iterate. Similarly, we can
3882 * happily treat the predicates as racy, atomic checks as userspace
3883 * cannot claim and pin a new fb without at least acquring the
3884 * struct_mutex and so serialising with us.
3885 */
d3fcc808 3886 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3887 if (atomic_read(&crtc->unpin_work_count) == 0)
3888 continue;
3889
3890 if (crtc->unpin_work)
3891 intel_wait_for_vblank(dev, crtc->pipe);
3892
3893 return true;
3894 }
3895
3896 return false;
3897}
3898
d6bbafa1
CW		 3899static void page_flip_completed(struct intel_crtc *intel_crtc)
3900{
3901 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3902 struct intel_unpin_work *work = intel_crtc->unpin_work;
3903
3904 /* ensure that the unpin work is consistent wrt ->pending. */
3905 smp_rmb();
3906 intel_crtc->unpin_work = NULL;
3907
3908 if (work->event)
3909 drm_send_vblank_event(intel_crtc->base.dev,
3910 intel_crtc->pipe,
3911 work->event);
3912
3913 drm_crtc_vblank_put(&intel_crtc->base);
3914
3915 wake_up_all(&dev_priv->pending_flip_queue);
3916 queue_work(dev_priv->wq, &work->work);
3917
3918 trace_i915_flip_complete(intel_crtc->plane,
3919 work->pending_flip_obj);
3920}
3921
46a55d30 3922void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3923{
0f91128d 3924 struct drm_device *dev = crtc->dev;
5bb61643 3925 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3926
2c10d571 3927 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3928 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3929 !intel_crtc_has_pending_flip(crtc),
3930 60*HZ) == 0)) {
3931 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3932
5e2d7afc 3933 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3934 if (intel_crtc->unpin_work) {
3935 WARN_ONCE(1, "Removing stuck page flip\n");
3936 page_flip_completed(intel_crtc);
3937 }
5e2d7afc 3938 spin_unlock_irq(&dev->event_lock);
9c787942 3939 }
5bb61643 3940
975d568a
CW		 3941 if (crtc->primary->fb) {
3942 mutex_lock(&dev->struct_mutex);
3943 intel_finish_fb(crtc->primary->fb);
3944 mutex_unlock(&dev->struct_mutex);
3945 }
e6c3a2a6
CW		 3946}
3947
e615efe4
ED		 3948/* Program iCLKIP clock to the desired frequency */
3949static void lpt_program_iclkip(struct drm_crtc *crtc)
3950{
3951 struct drm_device *dev = crtc->dev;
3952 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3953 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3954 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3955 u32 temp;
3956
09153000
DV		 3957 mutex_lock(&dev_priv->dpio_lock);
3958
e615efe4
ED		 3959 /* It is necessary to ungate the pixclk gate prior to programming
3960 * the divisors, and gate it back when it is done.
3961 */
3962 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3963
3964 /* Disable SSCCTL */
3965 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3966 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3967 SBI_SSCCTL_DISABLE,
3968 SBI_ICLK);
e615efe4
ED		 3969
3970 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3971 if (clock == 20000) {
e615efe4
ED		 3972 auxdiv = 1;
3973 divsel = 0x41;
3974 phaseinc = 0x20;
3975 } else {
3976 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3977 * but the adjusted_mode->crtc_clock in in KHz. To get the
3978 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3979 * convert the virtual clock precision to KHz here for higher
3980 * precision.
3981 */
3982 u32 iclk_virtual_root_freq = 172800 * 1000;
3983 u32 iclk_pi_range = 64;
3984 u32 desired_divisor, msb_divisor_value, pi_value;
3985
12d7ceed 3986 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3987 msb_divisor_value = desired_divisor / iclk_pi_range;
3988 pi_value = desired_divisor % iclk_pi_range;
3989
3990 auxdiv = 0;
3991 divsel = msb_divisor_value - 2;
3992 phaseinc = pi_value;
3993 }
3994
3995 /* This should not happen with any sane values */
3996 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3997 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3998 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3999 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
4000
4001 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 4002 clock,
e615efe4
ED		 4003 auxdiv,
4004 divsel,
4005 phasedir,
4006 phaseinc);
4007
4008 /* Program SSCDIVINTPHASE6 */
988d6ee8 4009 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 4010 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4011 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4012 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4013 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4014 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4015 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 4016 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 4017
4018 /* Program SSCAUXDIV */
988d6ee8 4019 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 4020 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4021 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 4022 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 4023
4024 /* Enable modulator and associated divider */
988d6ee8 4025 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4026 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4027 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4028
4029 /* Wait for initialization time */
4030 udelay(24);
4031
4032 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 4033
4034 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 4035}
4036
275f01b2
DV		 4037static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4038 enum pipe pch_transcoder)
4039{
4040 struct drm_device *dev = crtc->base.dev;
4041 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4042 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4043
4044 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4045 I915_READ(HTOTAL(cpu_transcoder)));
4046 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4047 I915_READ(HBLANK(cpu_transcoder)));
4048 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4049 I915_READ(HSYNC(cpu_transcoder)));
4050
4051 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4052 I915_READ(VTOTAL(cpu_transcoder)));
4053 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4054 I915_READ(VBLANK(cpu_transcoder)));
4055 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4056 I915_READ(VSYNC(cpu_transcoder)));
4057 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4058 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4059}
4060
003632d9 4061static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4062{
4063 struct drm_i915_private *dev_priv = dev->dev_private;
4064 uint32_t temp;
4065
4066 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4067 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4068 return;
4069
4070 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4071 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4072
003632d9
ACO		 4073 temp &= ~FDI_BC_BIFURCATION_SELECT;
4074 if (enable)
4075 temp |= FDI_BC_BIFURCATION_SELECT;
4076
4077 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4078 I915_WRITE(SOUTH_CHICKEN1, temp);
4079 POSTING_READ(SOUTH_CHICKEN1);
4080}
4081
4082static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4083{
4084 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4085
4086 switch (intel_crtc->pipe) {
4087 case PIPE_A:
4088 break;
4089 case PIPE_B:
6e3c9717 4090 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4091 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4092 else
003632d9 4093 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4094
4095 break;
4096 case PIPE_C:
003632d9 4097 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4098
4099 break;
4100 default:
4101 BUG();
4102 }
4103}
4104
f67a559d
JB		 4105/*
4106 * Enable PCH resources required for PCH ports:
4107 * - PCH PLLs
4108 * - FDI training & RX/TX
4109 * - update transcoder timings
4110 * - DP transcoding bits
4111 * - transcoder
4112 */
4113static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4114{
4115 struct drm_device *dev = crtc->dev;
4116 struct drm_i915_private *dev_priv = dev->dev_private;
4117 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4118 int pipe = intel_crtc->pipe;
ee7b9f93 4119 u32 reg, temp;
2c07245f 4120
ab9412ba 4121 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4122
1fbc0d78
DV		 4123 if (IS_IVYBRIDGE(dev))
4124 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4125
cd986abb
DV		 4126 /* Write the TU size bits before fdi link training, so that error
4127 * detection works. */
4128 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4129 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4130
c98e9dcf 4131 /* For PCH output, training FDI link */
674cf967 4132 dev_priv->display.fdi_link_train(crtc);
2c07245f 4133
3ad8a208
DV		 4134 /* We need to program the right clock selection before writing the pixel
4135 * mutliplier into the DPLL. */
303b81e0 4136 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4137 u32 sel;
4b645f14 4138
c98e9dcf 4139 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4140 temp |= TRANS_DPLL_ENABLE(pipe);
4141 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4142 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4143 temp |= sel;
4144 else
4145 temp &= ~sel;
c98e9dcf 4146 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4147 }
5eddb70b 4148
3ad8a208
DV		 4149 /* XXX: pch pll's can be enabled any time before we enable the PCH
4150 * transcoder, and we actually should do this to not upset any PCH
4151 * transcoder that already use the clock when we share it.
4152 *
4153 * Note that enable_shared_dpll tries to do the right thing, but
4154 * get_shared_dpll unconditionally resets the pll - we need that to have
4155 * the right LVDS enable sequence. */
85b3894f 4156 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4157
d9b6cb56
JB		 4158 /* set transcoder timing, panel must allow it */
4159 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4160 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4161
303b81e0 4162 intel_fdi_normal_train(crtc);
5e84e1a4 4163
c98e9dcf 4164 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4165 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4166 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4167 reg = TRANS_DP_CTL(pipe);
4168 temp = I915_READ(reg);
4169 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4170 TRANS_DP_SYNC_MASK |
4171 TRANS_DP_BPC_MASK);
5eddb70b
CW		 4172 temp |= (TRANS_DP_OUTPUT_ENABLE |
4173 TRANS_DP_ENH_FRAMING);
9325c9f0 4174 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4175
4176 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4177 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4178 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4179 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4180
4181 switch (intel_trans_dp_port_sel(crtc)) {
4182 case PCH_DP_B:
5eddb70b 4183 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4184 break;
4185 case PCH_DP_C:
5eddb70b 4186 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4187 break;
4188 case PCH_DP_D:
5eddb70b 4189 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4190 break;
4191 default:
e95d41e1 4192 BUG();
32f9d658 4193 }
2c07245f 4194
5eddb70b 4195 I915_WRITE(reg, temp);
6be4a607 4196 }
b52eb4dc 4197
b8a4f404 4198 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4199}
4200
1507e5bd
PZ		 4201static void lpt_pch_enable(struct drm_crtc *crtc)
4202{
4203 struct drm_device *dev = crtc->dev;
4204 struct drm_i915_private *dev_priv = dev->dev_private;
4205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4206 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4207
ab9412ba 4208 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4209
8c52b5e8 4210 lpt_program_iclkip(crtc);
1507e5bd 4211
0540e488 4212 /* Set transcoder timing. */
275f01b2 4213 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4214
937bb610 4215 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4216}
4217
716c2e55 4218void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 4219{
e2b78267 4220 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 4221
4222 if (pll == NULL)
4223 return;
4224
3e369b76 4225 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
1e6f2ddc 4226 WARN(1, "bad %s crtc mask\n", pll->name);
ee7b9f93
JB		 4227 return;
4228 }
4229
3e369b76
ACO		 4230 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4231 if (pll->config.crtc_mask == 0) {
f4a091c7
DV		 4232 WARN_ON(pll->on);
4233 WARN_ON(pll->active);
4234 }
4235
6e3c9717 4236 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 4237}
4238
190f68c5
ACO		 4239struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4240 struct intel_crtc_state *crtc_state)
ee7b9f93 4241{
e2b78267 4242 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4243 struct intel_shared_dpll *pll;
e2b78267 4244 enum intel_dpll_id i;
ee7b9f93 4245
98b6bd99
DV		 4246 if (HAS_PCH_IBX(dev_priv->dev)) {
4247 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4248 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4249 pll = &dev_priv->shared_dplls[i];
98b6bd99 4250
46edb027
DV		 4251 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4252 crtc->base.base.id, pll->name);
98b6bd99 4253
8bd31e67 4254 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4255
98b6bd99
DV		 4256 goto found;
4257 }
4258
bcddf610
S		 4259 if (IS_BROXTON(dev_priv->dev)) {
4260 /* PLL is attached to port in bxt */
4261 struct intel_encoder *encoder;
4262 struct intel_digital_port *intel_dig_port;
4263
4264 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4265 if (WARN_ON(!encoder))
4266 return NULL;
4267
4268 intel_dig_port = enc_to_dig_port(&encoder->base);
4269 /* 1:1 mapping between ports and PLLs */
4270 i = (enum intel_dpll_id)intel_dig_port->port;
4271 pll = &dev_priv->shared_dplls[i];
4272 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4273 crtc->base.base.id, pll->name);
4274 WARN_ON(pll->new_config->crtc_mask);
4275
4276 goto found;
4277 }
4278
e72f9fbf
DV		 4279 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4280 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4281
4282 /* Only want to check enabled timings first */
8bd31e67 4283 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4284 continue;
4285
190f68c5 4286 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4287 &pll->new_config->hw_state,
4288 sizeof(pll->new_config->hw_state)) == 0) {
4289 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4290 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4291 pll->new_config->crtc_mask,
4292 pll->active);
ee7b9f93
JB		 4293 goto found;
4294 }
4295 }
4296
4297 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4298 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4299 pll = &dev_priv->shared_dplls[i];
8bd31e67 4300 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4301 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4302 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4303 goto found;
4304 }
4305 }
4306
4307 return NULL;
4308
4309found:
8bd31e67 4310 if (pll->new_config->crtc_mask == 0)
190f68c5 4311 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4312
190f68c5 4313 crtc_state->shared_dpll = i;
46edb027
DV		 4314 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4315 pipe_name(crtc->pipe));
ee7b9f93 4316
8bd31e67 4317 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4318
ee7b9f93
JB		 4319 return pll;
4320}
4321
8bd31e67
ACO		 4322/**
4323 * intel_shared_dpll_start_config - start a new PLL staged config
4324 * @dev_priv: DRM device
4325 * @clear_pipes: mask of pipes that will have their PLLs freed
4326 *
4327 * Starts a new PLL staged config, copying the current config but
4328 * releasing the references of pipes specified in clear_pipes.
4329 */
4330static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4331 unsigned clear_pipes)
4332{
4333 struct intel_shared_dpll *pll;
4334 enum intel_dpll_id i;
4335
4336 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4337 pll = &dev_priv->shared_dplls[i];
4338
4339 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4340 GFP_KERNEL);
4341 if (!pll->new_config)
4342 goto cleanup;
4343
4344 pll->new_config->crtc_mask &= ~clear_pipes;
4345 }
4346
4347 return 0;
4348
4349cleanup:
4350 while (--i >= 0) {
4351 pll = &dev_priv->shared_dplls[i];
f354d733 4352 kfree(pll->new_config);
8bd31e67
ACO		 4353 pll->new_config = NULL;
4354 }
4355
4356 return -ENOMEM;
4357}
4358
4359static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4360{
4361 struct intel_shared_dpll *pll;
4362 enum intel_dpll_id i;
4363
4364 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4365 pll = &dev_priv->shared_dplls[i];
4366
4367 WARN_ON(pll->new_config == &pll->config);
4368
4369 pll->config = *pll->new_config;
4370 kfree(pll->new_config);
4371 pll->new_config = NULL;
4372 }
4373}
4374
4375static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4376{
4377 struct intel_shared_dpll *pll;
4378 enum intel_dpll_id i;
4379
4380 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4381 pll = &dev_priv->shared_dplls[i];
4382
4383 WARN_ON(pll->new_config == &pll->config);
4384
4385 kfree(pll->new_config);
4386 pll->new_config = NULL;
4387 }
4388}
4389
a1520318 4390static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4391{
4392 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4393 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4394 u32 temp;
4395
4396 temp = I915_READ(dslreg);
4397 udelay(500);
4398 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4399 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4400 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4401 }
4402}
4403
a1b2278e
CK		 4404/**
4405 * skl_update_scaler_users - Stages update to crtc's scaler state
4406 * @intel_crtc: crtc
4407 * @crtc_state: crtc_state
4408 * @plane: plane (NULL indicates crtc is requesting update)
4409 * @plane_state: plane's state
4410 * @force_detach: request unconditional detachment of scaler
4411 *
4412 * This function updates scaler state for requested plane or crtc.
4413 * To request scaler usage update for a plane, caller shall pass plane pointer.
4414 * To request scaler usage update for crtc, caller shall pass plane pointer
4415 * as NULL.
4416 *
4417 * Return
4418 * 0 - scaler_usage updated successfully
4419 * error - requested scaling cannot be supported or other error condition
4420 */
4421int
4422skl_update_scaler_users(
4423 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4424 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4425 int force_detach)
4426{
4427 int need_scaling;
4428 int idx;
4429 int src_w, src_h, dst_w, dst_h;
4430 int *scaler_id;
4431 struct drm_framebuffer *fb;
4432 struct intel_crtc_scaler_state *scaler_state;
6156a456 4433 unsigned int rotation;
a1b2278e
CK		 4434
4435 if (!intel_crtc || !crtc_state)
4436 return 0;
4437
4438 scaler_state = &crtc_state->scaler_state;
4439
4440 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4441 fb = intel_plane ? plane_state->base.fb : NULL;
4442
4443 if (intel_plane) {
4444 src_w = drm_rect_width(&plane_state->src) >> 16;
4445 src_h = drm_rect_height(&plane_state->src) >> 16;
4446 dst_w = drm_rect_width(&plane_state->dst);
4447 dst_h = drm_rect_height(&plane_state->dst);
4448 scaler_id = &plane_state->scaler_id;
6156a456 4449 rotation = plane_state->base.rotation;
a1b2278e
CK		 4450 } else {
4451 struct drm_display_mode *adjusted_mode =
4452 &crtc_state->base.adjusted_mode;
4453 src_w = crtc_state->pipe_src_w;
4454 src_h = crtc_state->pipe_src_h;
4455 dst_w = adjusted_mode->hdisplay;
4456 dst_h = adjusted_mode->vdisplay;
4457 scaler_id = &scaler_state->scaler_id;
6156a456 4458 rotation = DRM_ROTATE_0;
a1b2278e 4459 }
6156a456
CK		 4460
4461 need_scaling = intel_rotation_90_or_270(rotation) ?
4462 (src_h != dst_w || src_w != dst_h):
4463 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4464
4465 /*
4466 * if plane is being disabled or scaler is no more required or force detach
4467 * - free scaler binded to this plane/crtc
4468 * - in order to do this, update crtc->scaler_usage
4469 *
4470 * Here scaler state in crtc_state is set free so that
4471 * scaler can be assigned to other user. Actual register
4472 * update to free the scaler is done in plane/panel-fit programming.
4473 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4474 */
4475 if (force_detach || !need_scaling || (intel_plane &&
4476 (!fb || !plane_state->visible))) {
4477 if (*scaler_id >= 0) {
4478 scaler_state->scaler_users &= ~(1 << idx);
4479 scaler_state->scalers[*scaler_id].in_use = 0;
4480
4481 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4482 "crtc_state = %p scaler_users = 0x%x\n",
4483 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4484 intel_plane ? intel_plane->base.base.id :
4485 intel_crtc->base.base.id, crtc_state,
4486 scaler_state->scaler_users);
4487 *scaler_id = -1;
4488 }
4489 return 0;
4490 }
4491
4492 /* range checks */
4493 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4494 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4495
4496 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4497 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4498 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4499 "size is out of scaler range\n",
4500 intel_plane ? "PLANE" : "CRTC",
4501 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4502 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4503 return -EINVAL;
4504 }
4505
4506 /* check colorkey */
4507 if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) {
4508 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4509 intel_plane->base.base.id);
4510 return -EINVAL;
4511 }
4512
4513 /* Check src format */
4514 if (intel_plane) {
4515 switch (fb->pixel_format) {
4516 case DRM_FORMAT_RGB565:
4517 case DRM_FORMAT_XBGR8888:
4518 case DRM_FORMAT_XRGB8888:
4519 case DRM_FORMAT_ABGR8888:
4520 case DRM_FORMAT_ARGB8888:
4521 case DRM_FORMAT_XRGB2101010:
4522 case DRM_FORMAT_ARGB2101010:
4523 case DRM_FORMAT_XBGR2101010:
4524 case DRM_FORMAT_ABGR2101010:
4525 case DRM_FORMAT_YUYV:
4526 case DRM_FORMAT_YVYU:
4527 case DRM_FORMAT_UYVY:
4528 case DRM_FORMAT_VYUY:
4529 break;
4530 default:
4531 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4532 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4533 return -EINVAL;
4534 }
4535 }
4536
4537 /* mark this plane as a scaler user in crtc_state */
4538 scaler_state->scaler_users |= (1 << idx);
4539 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4540 "crtc_state = %p scaler_users = 0x%x\n",
4541 intel_plane ? "PLANE" : "CRTC",
4542 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4543 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4544 return 0;
4545}
4546
4547static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4548{
4549 struct drm_device *dev = crtc->base.dev;
4550 struct drm_i915_private *dev_priv = dev->dev_private;
4551 int pipe = crtc->pipe;
a1b2278e
CK		 4552 struct intel_crtc_scaler_state *scaler_state =
4553 &crtc->config->scaler_state;
4554
4555 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4556
4557 /* To update pfit, first update scaler state */
4558 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4559 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4560 skl_detach_scalers(crtc);
4561 if (!enable)
4562 return;
bd2e244f 4563
6e3c9717 4564 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4565 int id;
4566
4567 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4568 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4569 return;
4570 }
4571
4572 id = scaler_state->scaler_id;
4573 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4574 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4575 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4576 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4577
4578 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4579 }
4580}
4581
b074cec8
JB		 4582static void ironlake_pfit_enable(struct intel_crtc *crtc)
4583{
4584 struct drm_device *dev = crtc->base.dev;
4585 struct drm_i915_private *dev_priv = dev->dev_private;
4586 int pipe = crtc->pipe;
4587
6e3c9717 4588 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4589 /* Force use of hard-coded filter coefficients
4590 * as some pre-programmed values are broken,
4591 * e.g. x201.
4592 */
4593 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4594 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4595 PF_PIPE_SEL_IVB(pipe));
4596 else
4597 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4598 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4599 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4600 }
4601}
4602
4a3b8769 4603static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4604{
4605 struct drm_device *dev = crtc->dev;
4606 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4607 struct drm_plane *plane;
bb53d4ae
VS		 4608 struct intel_plane *intel_plane;
4609
af2b653b
MR		 4610 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4611 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4612 if (intel_plane->pipe == pipe)
4613 intel_plane_restore(&intel_plane->base);
af2b653b 4614 }
bb53d4ae
VS		 4615}
4616
20bc8673 4617void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4618{
cea165c3
VS		 4619 struct drm_device *dev = crtc->base.dev;
4620 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4621
6e3c9717 4622 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4623 return;
4624
cea165c3
VS		 4625 /* We can only enable IPS after we enable a plane and wait for a vblank */
4626 intel_wait_for_vblank(dev, crtc->pipe);
4627
d77e4531 4628 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4629 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4630 mutex_lock(&dev_priv->rps.hw_lock);
4631 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4632 mutex_unlock(&dev_priv->rps.hw_lock);
4633 /* Quoting Art Runyan: "its not safe to expect any particular
4634 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4635 * mailbox." Moreover, the mailbox may return a bogus state,
4636 * so we need to just enable it and continue on.
2a114cc1
BW		 4637 */
4638 } else {
4639 I915_WRITE(IPS_CTL, IPS_ENABLE);
4640 /* The bit only becomes 1 in the next vblank, so this wait here
4641 * is essentially intel_wait_for_vblank. If we don't have this
4642 * and don't wait for vblanks until the end of crtc_enable, then
4643 * the HW state readout code will complain that the expected
4644 * IPS_CTL value is not the one we read. */
4645 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4646 DRM_ERROR("Timed out waiting for IPS enable\n");
4647 }
d77e4531
PZ		 4648}
4649
20bc8673 4650void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4651{
4652 struct drm_device *dev = crtc->base.dev;
4653 struct drm_i915_private *dev_priv = dev->dev_private;
4654
6e3c9717 4655 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4656 return;
4657
4658 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4659 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4660 mutex_lock(&dev_priv->rps.hw_lock);
4661 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4662 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4663 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4664 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4665 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4666 } else {
2a114cc1 4667 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4668 POSTING_READ(IPS_CTL);
4669 }
d77e4531
PZ		 4670
4671 /* We need to wait for a vblank before we can disable the plane. */
4672 intel_wait_for_vblank(dev, crtc->pipe);
4673}
4674
4675/** Loads the palette/gamma unit for the CRTC with the prepared values */
4676static void intel_crtc_load_lut(struct drm_crtc *crtc)
4677{
4678 struct drm_device *dev = crtc->dev;
4679 struct drm_i915_private *dev_priv = dev->dev_private;
4680 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4681 enum pipe pipe = intel_crtc->pipe;
4682 int palreg = PALETTE(pipe);
4683 int i;
4684 bool reenable_ips = false;
4685
4686 /* The clocks have to be on to load the palette. */
83d65738 4687 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4688 return;
4689
50360403 4690 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4691 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4692 assert_dsi_pll_enabled(dev_priv);
4693 else
4694 assert_pll_enabled(dev_priv, pipe);
4695 }
4696
4697 /* use legacy palette for Ironlake */
7a1db49a 4698 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4699 palreg = LGC_PALETTE(pipe);
4700
4701 /* Workaround : Do not read or write the pipe palette/gamma data while
4702 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4703 */
6e3c9717 4704 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4705 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4706 GAMMA_MODE_MODE_SPLIT)) {
4707 hsw_disable_ips(intel_crtc);
4708 reenable_ips = true;
4709 }
4710
4711 for (i = 0; i < 256; i++) {
4712 I915_WRITE(palreg + 4 * i,
4713 (intel_crtc->lut_r[i] << 16) |
4714 (intel_crtc->lut_g[i] << 8) |
4715 intel_crtc->lut_b[i]);
4716 }
4717
4718 if (reenable_ips)
4719 hsw_enable_ips(intel_crtc);
4720}
4721
7cac945f 4722static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4723{
7cac945f 4724 if (intel_crtc->overlay) {
d3eedb1a
VS		 4725 struct drm_device *dev = intel_crtc->base.dev;
4726 struct drm_i915_private *dev_priv = dev->dev_private;
4727
4728 mutex_lock(&dev->struct_mutex);
4729 dev_priv->mm.interruptible = false;
4730 (void) intel_overlay_switch_off(intel_crtc->overlay);
4731 dev_priv->mm.interruptible = true;
4732 mutex_unlock(&dev->struct_mutex);
4733 }
4734
4735 /* Let userspace switch the overlay on again. In most cases userspace
4736 * has to recompute where to put it anyway.
4737 */
4738}
4739
87d4300a
ML		 4740/**
4741 * intel_post_enable_primary - Perform operations after enabling primary plane
4742 * @crtc: the CRTC whose primary plane was just enabled
4743 *
4744 * Performs potentially sleeping operations that must be done after the primary
4745 * plane is enabled, such as updating FBC and IPS. Note that this may be
4746 * called due to an explicit primary plane update, or due to an implicit
4747 * re-enable that is caused when a sprite plane is updated to no longer
4748 * completely hide the primary plane.
4749 */
4750static void
4751intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4752{
4753 struct drm_device *dev = crtc->dev;
87d4300a 4754 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4755 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4756 int pipe = intel_crtc->pipe;
a5c4d7bc 4757
87d4300a
ML		 4758 /*
4759 * BDW signals flip done immediately if the plane
4760 * is disabled, even if the plane enable is already
4761 * armed to occur at the next vblank :(
4762 */
4763 if (IS_BROADWELL(dev))
4764 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4765
87d4300a
ML		 4766 /*
4767 * FIXME IPS should be fine as long as one plane is
4768 * enabled, but in practice it seems to have problems
4769 * when going from primary only to sprite only and vice
4770 * versa.
4771 */
a5c4d7bc
VS		 4772 hsw_enable_ips(intel_crtc);
4773
4774 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4775 intel_fbc_update(dev);
a5c4d7bc 4776 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4777
4778 /*
87d4300a
ML		 4779 * Gen2 reports pipe underruns whenever all planes are disabled.
4780 * So don't enable underrun reporting before at least some planes
4781 * are enabled.
4782 * FIXME: Need to fix the logic to work when we turn off all planes
4783 * but leave the pipe running.
f99d7069 4784 */
87d4300a
ML		 4785 if (IS_GEN2(dev))
4786 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4787
4788 /* Underruns don't raise interrupts, so check manually. */
4789 if (HAS_GMCH_DISPLAY(dev))
4790 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4791}
4792
87d4300a
ML		 4793/**
4794 * intel_pre_disable_primary - Perform operations before disabling primary plane
4795 * @crtc: the CRTC whose primary plane is to be disabled
4796 *
4797 * Performs potentially sleeping operations that must be done before the
4798 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4799 * be called due to an explicit primary plane update, or due to an implicit
4800 * disable that is caused when a sprite plane completely hides the primary
4801 * plane.
4802 */
4803static void
4804intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4805{
4806 struct drm_device *dev = crtc->dev;
4807 struct drm_i915_private *dev_priv = dev->dev_private;
4808 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4809 int pipe = intel_crtc->pipe;
a5c4d7bc 4810
87d4300a
ML		 4811 /*
4812 * Gen2 reports pipe underruns whenever all planes are disabled.
4813 * So diasble underrun reporting before all the planes get disabled.
4814 * FIXME: Need to fix the logic to work when we turn off all planes
4815 * but leave the pipe running.
4816 */
4817 if (IS_GEN2(dev))
4818 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4819
87d4300a
ML		 4820 /*
4821 * Vblank time updates from the shadow to live plane control register
4822 * are blocked if the memory self-refresh mode is active at that
4823 * moment. So to make sure the plane gets truly disabled, disable
4824 * first the self-refresh mode. The self-refresh enable bit in turn
4825 * will be checked/applied by the HW only at the next frame start
4826 * event which is after the vblank start event, so we need to have a
4827 * wait-for-vblank between disabling the plane and the pipe.
4828 */
4829 if (HAS_GMCH_DISPLAY(dev))
4830 intel_set_memory_cxsr(dev_priv, false);
4831
4832 mutex_lock(&dev->struct_mutex);
e35fef21 4833 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4834 intel_fbc_disable(dev);
87d4300a 4835 mutex_unlock(&dev->struct_mutex);
a5c4d7bc 4836
87d4300a
ML		 4837 /*
4838 * FIXME IPS should be fine as long as one plane is
4839 * enabled, but in practice it seems to have problems
4840 * when going from primary only to sprite only and vice
4841 * versa.
4842 */
a5c4d7bc 4843 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4844}
4845
4846static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4847{
87d4300a
ML		 4848 intel_enable_primary_hw_plane(crtc->primary, crtc);
4849 intel_enable_sprite_planes(crtc);
4850 intel_crtc_update_cursor(crtc, true);
87d4300a
ML		 4851
4852 intel_post_enable_primary(crtc);
4853}
4854
4855static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4856{
4857 struct drm_device *dev = crtc->dev;
4858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4859 struct intel_plane *intel_plane;
4860 int pipe = intel_crtc->pipe;
4861
4862 intel_crtc_wait_for_pending_flips(crtc);
4863
4864 intel_pre_disable_primary(crtc);
a5c4d7bc 4865
7cac945f 4866 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8
ML		 4867 for_each_intel_plane(dev, intel_plane) {
4868 if (intel_plane->pipe == pipe) {
4869 struct drm_crtc *from = intel_plane->base.crtc;
4870
4871 intel_plane->disable_plane(&intel_plane->base,
4872 from ?: crtc, true);
4873 }
4874 }
f98551ae 4875
f99d7069
DV		 4876 /*
4877 * FIXME: Once we grow proper nuclear flip support out of this we need
4878 * to compute the mask of flip planes precisely. For the time being
4879 * consider this a flip to a NULL plane.
4880 */
4881 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4882}
4883
f67a559d
JB		 4884static void ironlake_crtc_enable(struct drm_crtc *crtc)
4885{
4886 struct drm_device *dev = crtc->dev;
4887 struct drm_i915_private *dev_priv = dev->dev_private;
4888 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4889 struct intel_encoder *encoder;
f67a559d 4890 int pipe = intel_crtc->pipe;
f67a559d 4891
83d65738 4892 WARN_ON(!crtc->state->enable);
08a48469 4893
f67a559d
JB		 4894 if (intel_crtc->active)
4895 return;
4896
6e3c9717 4897 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4898 intel_prepare_shared_dpll(intel_crtc);
4899
6e3c9717 4900 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4901 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4902
4903 intel_set_pipe_timings(intel_crtc);
4904
6e3c9717 4905 if (intel_crtc->config->has_pch_encoder) {
29407aab 4906 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4907 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4908 }
4909
4910 ironlake_set_pipeconf(crtc);
4911
f67a559d 4912 intel_crtc->active = true;
8664281b 4913
a72e4c9f
DV		 4914 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4915 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4916
f6736a1a 4917 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4918 if (encoder->pre_enable)
4919 encoder->pre_enable(encoder);
f67a559d 4920
6e3c9717 4921 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4922 /* Note: FDI PLL enabling _must_ be done before we enable the
4923 * cpu pipes, hence this is separate from all the other fdi/pch
4924 * enabling. */
88cefb6c 4925 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4926 } else {
4927 assert_fdi_tx_disabled(dev_priv, pipe);
4928 assert_fdi_rx_disabled(dev_priv, pipe);
4929 }
f67a559d 4930
b074cec8 4931 ironlake_pfit_enable(intel_crtc);
f67a559d 4932
9c54c0dd
JB		 4933 /*
4934 * On ILK+ LUT must be loaded before the pipe is running but with
4935 * clocks enabled
4936 */
4937 intel_crtc_load_lut(crtc);
4938
f37fcc2a 4939 intel_update_watermarks(crtc);
e1fdc473 4940 intel_enable_pipe(intel_crtc);
f67a559d 4941
6e3c9717 4942 if (intel_crtc->config->has_pch_encoder)
f67a559d 4943 ironlake_pch_enable(crtc);
c98e9dcf 4944
f9b61ff6
DV		 4945 assert_vblank_disabled(crtc);
4946 drm_crtc_vblank_on(crtc);
4947
fa5c73b1
DV		 4948 for_each_encoder_on_crtc(dev, crtc, encoder)
4949 encoder->enable(encoder);
61b77ddd
DV		 4950
4951 if (HAS_PCH_CPT(dev))
a1520318 4952 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4953}
4954
42db64ef
PZ		 4955/* IPS only exists on ULT machines and is tied to pipe A. */
4956static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4957{
f5adf94e 4958 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4959}
4960
e4916946
PZ		 4961/*
4962 * This implements the workaround described in the "notes" section of the mode
4963 * set sequence documentation. When going from no pipes or single pipe to
4964 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4965 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4966 */
4967static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4968{
4969 struct drm_device *dev = crtc->base.dev;
4970 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4971
4972 /* We want to get the other_active_crtc only if there's only 1 other
4973 * active crtc. */
d3fcc808 4974 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4975 if (!crtc_it->active || crtc_it == crtc)
4976 continue;
4977
4978 if (other_active_crtc)
4979 return;
4980
4981 other_active_crtc = crtc_it;
4982 }
4983 if (!other_active_crtc)
4984 return;
4985
4986 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4987 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4988}
4989
4f771f10
PZ		 4990static void haswell_crtc_enable(struct drm_crtc *crtc)
4991{
4992 struct drm_device *dev = crtc->dev;
4993 struct drm_i915_private *dev_priv = dev->dev_private;
4994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4995 struct intel_encoder *encoder;
4996 int pipe = intel_crtc->pipe;
4f771f10 4997
83d65738 4998 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 4999
5000 if (intel_crtc->active)
5001 return;
5002
df8ad70c
DV		 5003 if (intel_crtc_to_shared_dpll(intel_crtc))
5004 intel_enable_shared_dpll(intel_crtc);
5005
6e3c9717 5006 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5007 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 5008
5009 intel_set_pipe_timings(intel_crtc);
5010
6e3c9717
ACO		 5011 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5012 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5013 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 5014 }
5015
6e3c9717 5016 if (intel_crtc->config->has_pch_encoder) {
229fca97 5017 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 5018 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 5019 }
5020
5021 haswell_set_pipeconf(crtc);
5022
5023 intel_set_pipe_csc(crtc);
5024
4f771f10 5025 intel_crtc->active = true;
8664281b 5026
a72e4c9f 5027 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 5028 for_each_encoder_on_crtc(dev, crtc, encoder)
5029 if (encoder->pre_enable)
5030 encoder->pre_enable(encoder);
5031
6e3c9717 5032 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 5033 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5034 true);
4fe9467d
ID		 5035 dev_priv->display.fdi_link_train(crtc);
5036 }
5037
1f544388 5038 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 5039
ff6d9f55 5040 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5041 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 5042 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5043 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 5044 else
5045 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 5046
5047 /*
5048 * On ILK+ LUT must be loaded before the pipe is running but with
5049 * clocks enabled
5050 */
5051 intel_crtc_load_lut(crtc);
5052
1f544388 5053 intel_ddi_set_pipe_settings(crtc);
8228c251 5054 intel_ddi_enable_transcoder_func(crtc);
4f771f10 5055
f37fcc2a 5056 intel_update_watermarks(crtc);
e1fdc473 5057 intel_enable_pipe(intel_crtc);
42db64ef 5058
6e3c9717 5059 if (intel_crtc->config->has_pch_encoder)
1507e5bd 5060 lpt_pch_enable(crtc);
4f771f10 5061
6e3c9717 5062 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 5063 intel_ddi_set_vc_payload_alloc(crtc, true);
5064
f9b61ff6
DV		 5065 assert_vblank_disabled(crtc);
5066 drm_crtc_vblank_on(crtc);
5067
8807e55b 5068 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 5069 encoder->enable(encoder);
8807e55b
JN		 5070 intel_opregion_notify_encoder(encoder, true);
5071 }
4f771f10 5072
e4916946
PZ		 5073 /* If we change the relative order between pipe/planes enabling, we need
5074 * to change the workaround. */
5075 haswell_mode_set_planes_workaround(intel_crtc);
4f771f10
PZ		 5076}
5077
3f8dce3a
DV		 5078static void ironlake_pfit_disable(struct intel_crtc *crtc)
5079{
5080 struct drm_device *dev = crtc->base.dev;
5081 struct drm_i915_private *dev_priv = dev->dev_private;
5082 int pipe = crtc->pipe;
5083
5084 /* To avoid upsetting the power well on haswell only disable the pfit if
5085 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 5086 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5087 I915_WRITE(PF_CTL(pipe), 0);
5088 I915_WRITE(PF_WIN_POS(pipe), 0);
5089 I915_WRITE(PF_WIN_SZ(pipe), 0);
5090 }
5091}
5092
6be4a607
JB		 5093static void ironlake_crtc_disable(struct drm_crtc *crtc)
5094{
5095 struct drm_device *dev = crtc->dev;
5096 struct drm_i915_private *dev_priv = dev->dev_private;
5097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5098 struct intel_encoder *encoder;
6be4a607 5099 int pipe = intel_crtc->pipe;
5eddb70b 5100 u32 reg, temp;
b52eb4dc 5101
f7abfe8b
CW		 5102 if (!intel_crtc->active)
5103 return;
5104
ea9d758d
DV		 5105 for_each_encoder_on_crtc(dev, crtc, encoder)
5106 encoder->disable(encoder);
5107
f9b61ff6
DV		 5108 drm_crtc_vblank_off(crtc);
5109 assert_vblank_disabled(crtc);
5110
6e3c9717 5111 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5112 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5113
575f7ab7 5114 intel_disable_pipe(intel_crtc);
32f9d658 5115
3f8dce3a 5116 ironlake_pfit_disable(intel_crtc);
2c07245f 5117
bf49ec8c
DV		 5118 for_each_encoder_on_crtc(dev, crtc, encoder)
5119 if (encoder->post_disable)
5120 encoder->post_disable(encoder);
2c07245f 5121
6e3c9717 5122 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5123 ironlake_fdi_disable(crtc);
913d8d11 5124
d925c59a 5125 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5126
d925c59a
DV		 5127 if (HAS_PCH_CPT(dev)) {
5128 /* disable TRANS_DP_CTL */
5129 reg = TRANS_DP_CTL(pipe);
5130 temp = I915_READ(reg);
5131 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5132 TRANS_DP_PORT_SEL_MASK);
5133 temp |= TRANS_DP_PORT_SEL_NONE;
5134 I915_WRITE(reg, temp);
5135
5136 /* disable DPLL_SEL */
5137 temp = I915_READ(PCH_DPLL_SEL);
11887397 5138 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5139 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5140 }
e3421a18 5141
d925c59a 5142 /* disable PCH DPLL */
e72f9fbf 5143 intel_disable_shared_dpll(intel_crtc);
8db9d77b 5144
d925c59a
DV		 5145 ironlake_fdi_pll_disable(intel_crtc);
5146 }
6b383a7f 5147
f7abfe8b 5148 intel_crtc->active = false;
46ba614c 5149 intel_update_watermarks(crtc);
d1ebd816
BW		 5150
5151 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5152 intel_fbc_update(dev);
d1ebd816 5153 mutex_unlock(&dev->struct_mutex);
6be4a607 5154}
1b3c7a47 5155
4f771f10 5156static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5157{
4f771f10
PZ		 5158 struct drm_device *dev = crtc->dev;
5159 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5160 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5161 struct intel_encoder *encoder;
6e3c9717 5162 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5163
4f771f10
PZ		 5164 if (!intel_crtc->active)
5165 return;
5166
8807e55b
JN		 5167 for_each_encoder_on_crtc(dev, crtc, encoder) {
5168 intel_opregion_notify_encoder(encoder, false);
4f771f10 5169 encoder->disable(encoder);
8807e55b 5170 }
4f771f10 5171
f9b61ff6
DV		 5172 drm_crtc_vblank_off(crtc);
5173 assert_vblank_disabled(crtc);
5174
6e3c9717 5175 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5176 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5177 false);
575f7ab7 5178 intel_disable_pipe(intel_crtc);
4f771f10 5179
6e3c9717 5180 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5181 intel_ddi_set_vc_payload_alloc(crtc, false);
5182
ad80a810 5183 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5184
ff6d9f55 5185 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5186 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5187 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5188 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5189 else
5190 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5191
1f544388 5192 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5193
6e3c9717 5194 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5195 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5196 intel_ddi_fdi_disable(crtc);
83616634 5197 }
4f771f10 5198
97b040aa
ID		 5199 for_each_encoder_on_crtc(dev, crtc, encoder)
5200 if (encoder->post_disable)
5201 encoder->post_disable(encoder);
5202
4f771f10 5203 intel_crtc->active = false;
46ba614c 5204 intel_update_watermarks(crtc);
4f771f10
PZ		 5205
5206 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5207 intel_fbc_update(dev);
4f771f10 5208 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 5209
5210 if (intel_crtc_to_shared_dpll(intel_crtc))
5211 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 5212}
5213
ee7b9f93
JB		 5214static void ironlake_crtc_off(struct drm_crtc *crtc)
5215{
5216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 5217 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 5218}
5219
6441ab5f 5220
2dd24552
JB		 5221static void i9xx_pfit_enable(struct intel_crtc *crtc)
5222{
5223 struct drm_device *dev = crtc->base.dev;
5224 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5225 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5226
681a8504 5227 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5228 return;
5229
2dd24552 5230 /*
c0b03411
DV		 5231 * The panel fitter should only be adjusted whilst the pipe is disabled,
5232 * according to register description and PRM.
2dd24552 5233 */
c0b03411
DV		 5234 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5235 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5236
b074cec8
JB		 5237 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5238 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5239
5240 /* Border color in case we don't scale up to the full screen. Black by
5241 * default, change to something else for debugging. */
5242 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5243}
5244
d05410f9
DA		 5245static enum intel_display_power_domain port_to_power_domain(enum port port)
5246{
5247 switch (port) {
5248 case PORT_A:
5249 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5250 case PORT_B:
5251 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5252 case PORT_C:
5253 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5254 case PORT_D:
5255 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5256 default:
5257 WARN_ON_ONCE(1);
5258 return POWER_DOMAIN_PORT_OTHER;
5259 }
5260}
5261
77d22dca
ID		 5262#define for_each_power_domain(domain, mask) \
5263 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5264 if ((1 << (domain)) & (mask))
5265
319be8ae
ID		 5266enum intel_display_power_domain
5267intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5268{
5269 struct drm_device *dev = intel_encoder->base.dev;
5270 struct intel_digital_port *intel_dig_port;
5271
5272 switch (intel_encoder->type) {
5273 case INTEL_OUTPUT_UNKNOWN:
5274 /* Only DDI platforms should ever use this output type */
5275 WARN_ON_ONCE(!HAS_DDI(dev));
5276 case INTEL_OUTPUT_DISPLAYPORT:
5277 case INTEL_OUTPUT_HDMI:
5278 case INTEL_OUTPUT_EDP:
5279 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5280 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5281 case INTEL_OUTPUT_DP_MST:
5282 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5283 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5284 case INTEL_OUTPUT_ANALOG:
5285 return POWER_DOMAIN_PORT_CRT;
5286 case INTEL_OUTPUT_DSI:
5287 return POWER_DOMAIN_PORT_DSI;
5288 default:
5289 return POWER_DOMAIN_PORT_OTHER;
5290 }
5291}
5292
5293static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5294{
319be8ae
ID		 5295 struct drm_device *dev = crtc->dev;
5296 struct intel_encoder *intel_encoder;
5297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5298 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5299 unsigned long mask;
5300 enum transcoder transcoder;
5301
5302 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5303
5304 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5305 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5306 if (intel_crtc->config->pch_pfit.enabled ||
5307 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5308 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5309
319be8ae
ID		 5310 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5311 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5312
77d22dca
ID		 5313 return mask;
5314}
5315
679dacd4 5316static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5317{
679dacd4 5318 struct drm_device *dev = state->dev;
77d22dca
ID		 5319 struct drm_i915_private *dev_priv = dev->dev_private;
5320 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5321 struct intel_crtc *crtc;
5322
5323 /*
5324 * First get all needed power domains, then put all unneeded, to avoid
5325 * any unnecessary toggling of the power wells.
5326 */
d3fcc808 5327 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5328 enum intel_display_power_domain domain;
5329
83d65738 5330 if (!crtc->base.state->enable)
77d22dca
ID		 5331 continue;
5332
319be8ae 5333 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5334
5335 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5336 intel_display_power_get(dev_priv, domain);
5337 }
5338
50f6e502 5339 if (dev_priv->display.modeset_global_resources)
679dacd4 5340 dev_priv->display.modeset_global_resources(state);
50f6e502 5341
d3fcc808 5342 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5343 enum intel_display_power_domain domain;
5344
5345 for_each_power_domain(domain, crtc->enabled_power_domains)
5346 intel_display_power_put(dev_priv, domain);
5347
5348 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5349 }
5350
5351 intel_display_set_init_power(dev_priv, false);
5352}
5353
f8437dd1
VK		 5354void broxton_set_cdclk(struct drm_device *dev, int frequency)
5355{
5356 struct drm_i915_private *dev_priv = dev->dev_private;
5357 uint32_t divider;
5358 uint32_t ratio;
5359 uint32_t current_freq;
5360 int ret;
5361
5362 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5363 switch (frequency) {
5364 case 144000:
5365 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5366 ratio = BXT_DE_PLL_RATIO(60);
5367 break;
5368 case 288000:
5369 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5370 ratio = BXT_DE_PLL_RATIO(60);
5371 break;
5372 case 384000:
5373 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5374 ratio = BXT_DE_PLL_RATIO(60);
5375 break;
5376 case 576000:
5377 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5378 ratio = BXT_DE_PLL_RATIO(60);
5379 break;
5380 case 624000:
5381 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5382 ratio = BXT_DE_PLL_RATIO(65);
5383 break;
5384 case 19200:
5385 /*
5386 * Bypass frequency with DE PLL disabled. Init ratio, divider
5387 * to suppress GCC warning.
5388 */
5389 ratio = 0;
5390 divider = 0;
5391 break;
5392 default:
5393 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5394
5395 return;
5396 }
5397
5398 mutex_lock(&dev_priv->rps.hw_lock);
5399 /* Inform power controller of upcoming frequency change */
5400 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5401 0x80000000);
5402 mutex_unlock(&dev_priv->rps.hw_lock);
5403
5404 if (ret) {
5405 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5406 ret, frequency);
5407 return;
5408 }
5409
5410 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5411 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5412 current_freq = current_freq * 500 + 1000;
5413
5414 /*
5415 * DE PLL has to be disabled when
5416 * - setting to 19.2MHz (bypass, PLL isn't used)
5417 * - before setting to 624MHz (PLL needs toggling)
5418 * - before setting to any frequency from 624MHz (PLL needs toggling)
5419 */
5420 if (frequency == 19200 || frequency == 624000 ||
5421 current_freq == 624000) {
5422 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5423 /* Timeout 200us */
5424 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5425 1))
5426 DRM_ERROR("timout waiting for DE PLL unlock\n");
5427 }
5428
5429 if (frequency != 19200) {
5430 uint32_t val;
5431
5432 val = I915_READ(BXT_DE_PLL_CTL);
5433 val &= ~BXT_DE_PLL_RATIO_MASK;
5434 val |= ratio;
5435 I915_WRITE(BXT_DE_PLL_CTL, val);
5436
5437 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5438 /* Timeout 200us */
5439 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5440 DRM_ERROR("timeout waiting for DE PLL lock\n");
5441
5442 val = I915_READ(CDCLK_CTL);
5443 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5444 val |= divider;
5445 /*
5446 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5447 * enable otherwise.
5448 */
5449 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5450 if (frequency >= 500000)
5451 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5452
5453 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5454 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5455 val |= (frequency - 1000) / 500;
5456 I915_WRITE(CDCLK_CTL, val);
5457 }
5458
5459 mutex_lock(&dev_priv->rps.hw_lock);
5460 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5461 DIV_ROUND_UP(frequency, 25000));
5462 mutex_unlock(&dev_priv->rps.hw_lock);
5463
5464 if (ret) {
5465 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5466 ret, frequency);
5467 return;
5468 }
5469
5470 dev_priv->cdclk_freq = frequency;
5471}
5472
5473void broxton_init_cdclk(struct drm_device *dev)
5474{
5475 struct drm_i915_private *dev_priv = dev->dev_private;
5476 uint32_t val;
5477
5478 /*
5479 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5480 * or else the reset will hang because there is no PCH to respond.
5481 * Move the handshake programming to initialization sequence.
5482 * Previously was left up to BIOS.
5483 */
5484 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5485 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5486 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5487
5488 /* Enable PG1 for cdclk */
5489 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5490
5491 /* check if cd clock is enabled */
5492 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5493 DRM_DEBUG_KMS("Display already initialized\n");
5494 return;
5495 }
5496
5497 /*
5498 * FIXME:
5499 * - The initial CDCLK needs to be read from VBT.
5500 * Need to make this change after VBT has changes for BXT.
5501 * - check if setting the max (or any) cdclk freq is really necessary
5502 * here, it belongs to modeset time
5503 */
5504 broxton_set_cdclk(dev, 624000);
5505
5506 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5507 POSTING_READ(DBUF_CTL);
5508
f8437dd1
VK		 5509 udelay(10);
5510
5511 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5512 DRM_ERROR("DBuf power enable timeout!\n");
5513}
5514
5515void broxton_uninit_cdclk(struct drm_device *dev)
5516{
5517 struct drm_i915_private *dev_priv = dev->dev_private;
5518
5519 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5520 POSTING_READ(DBUF_CTL);
5521
f8437dd1
VK		 5522 udelay(10);
5523
5524 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5525 DRM_ERROR("DBuf power disable timeout!\n");
5526
5527 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5528 broxton_set_cdclk(dev, 19200);
5529
5530 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5531}
5532
dfcab17e 5533/* returns HPLL frequency in kHz */
f8bf63fd 5534static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5535{
586f49dc 5536 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5537
586f49dc
JB		 5538 /* Obtain SKU information */
5539 mutex_lock(&dev_priv->dpio_lock);
5540 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5541 CCK_FUSE_HPLL_FREQ_MASK;
5542 mutex_unlock(&dev_priv->dpio_lock);
30a970c6 5543
dfcab17e 5544 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5545}
5546
f8bf63fd
VS		 5547static void vlv_update_cdclk(struct drm_device *dev)
5548{
5549 struct drm_i915_private *dev_priv = dev->dev_private;
5550
164dfd28 5551 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
43dc52c3 5552 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
164dfd28 5553 dev_priv->cdclk_freq);
f8bf63fd
VS		 5554
5555 /*
5556 * Program the gmbus_freq based on the cdclk frequency.
5557 * BSpec erroneously claims we should aim for 4MHz, but
5558 * in fact 1MHz is the correct frequency.
5559 */
164dfd28 5560 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
f8bf63fd
VS		 5561}
5562
30a970c6
JB		 5563/* Adjust CDclk dividers to allow high res or save power if possible */
5564static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5565{
5566 struct drm_i915_private *dev_priv = dev->dev_private;
5567 u32 val, cmd;
5568
164dfd28
VK		 5569 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5570 != dev_priv->cdclk_freq);
d60c4473 5571
dfcab17e 5572 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5573 cmd = 2;
dfcab17e 5574 else if (cdclk == 266667)
30a970c6
JB		 5575 cmd = 1;
5576 else
5577 cmd = 0;
5578
5579 mutex_lock(&dev_priv->rps.hw_lock);
5580 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5581 val &= ~DSPFREQGUAR_MASK;
5582 val |= (cmd << DSPFREQGUAR_SHIFT);
5583 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5584 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5585 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5586 50)) {
5587 DRM_ERROR("timed out waiting for CDclk change\n");
5588 }
5589 mutex_unlock(&dev_priv->rps.hw_lock);
5590
dfcab17e 5591 if (cdclk == 400000) {
6bcda4f0 5592 u32 divider;
30a970c6 5593
6bcda4f0 5594 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6
JB		 5595
5596 mutex_lock(&dev_priv->dpio_lock);
5597 /* adjust cdclk divider */
5598 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5599 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5600 val |= divider;
5601 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5602
5603 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5604 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5605 50))
5606 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5607 mutex_unlock(&dev_priv->dpio_lock);
5608 }
5609
5610 mutex_lock(&dev_priv->dpio_lock);
5611 /* adjust self-refresh exit latency value */
5612 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5613 val &= ~0x7f;
5614
5615 /*
5616 * For high bandwidth configs, we set a higher latency in the bunit
5617 * so that the core display fetch happens in time to avoid underruns.
5618 */
dfcab17e 5619 if (cdclk == 400000)
30a970c6
JB		 5620 val |= 4500 / 250; /* 4.5 usec */
5621 else
5622 val |= 3000 / 250; /* 3.0 usec */
5623 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5624 mutex_unlock(&dev_priv->dpio_lock);
5625
f8bf63fd 5626 vlv_update_cdclk(dev);
30a970c6
JB		 5627}
5628
383c5a6a
VS		 5629static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5630{
5631 struct drm_i915_private *dev_priv = dev->dev_private;
5632 u32 val, cmd;
5633
164dfd28
VK		 5634 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5635 != dev_priv->cdclk_freq);
383c5a6a
VS		 5636
5637 switch (cdclk) {
383c5a6a
VS		 5638 case 333333:
5639 case 320000:
383c5a6a 5640 case 266667:
383c5a6a 5641 case 200000:
383c5a6a
VS		 5642 break;
5643 default:
5f77eeb0 5644 MISSING_CASE(cdclk);
383c5a6a
VS		 5645 return;
5646 }
5647
9d0d3fda
VS		 5648 /*
5649 * Specs are full of misinformation, but testing on actual
5650 * hardware has shown that we just need to write the desired
5651 * CCK divider into the Punit register.
5652 */
5653 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5654
383c5a6a
VS		 5655 mutex_lock(&dev_priv->rps.hw_lock);
5656 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5657 val &= ~DSPFREQGUAR_MASK_CHV;
5658 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5659 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5660 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5661 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5662 50)) {
5663 DRM_ERROR("timed out waiting for CDclk change\n");
5664 }
5665 mutex_unlock(&dev_priv->rps.hw_lock);
5666
5667 vlv_update_cdclk(dev);
5668}
5669
30a970c6
JB		 5670static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5671 int max_pixclk)
5672{
6bcda4f0 5673 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5674 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5675
30a970c6
JB		 5676 /*
5677 * Really only a few cases to deal with, as only 4 CDclks are supported:
5678 * 200MHz
5679 * 267MHz
29dc7ef3 5680 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5681 * 400MHz (VLV only)
5682 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5683 * of the lower bin and adjust if needed.
e37c67a1
VS		 5684 *
5685 * We seem to get an unstable or solid color picture at 200MHz.
5686 * Not sure what's wrong. For now use 200MHz only when all pipes
5687 * are off.
30a970c6 5688 */
6cca3195
VS		 5689 if (!IS_CHERRYVIEW(dev_priv) &&
5690 max_pixclk > freq_320*limit/100)
dfcab17e 5691 return 400000;
6cca3195 5692 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5693 return freq_320;
e37c67a1 5694 else if (max_pixclk > 0)
dfcab17e 5695 return 266667;
e37c67a1
VS		 5696 else
5697 return 200000;
30a970c6
JB		 5698}
5699
f8437dd1
VK		 5700static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5701 int max_pixclk)
5702{
5703 /*
5704 * FIXME:
5705 * - remove the guardband, it's not needed on BXT
5706 * - set 19.2MHz bypass frequency if there are no active pipes
5707 */
5708 if (max_pixclk > 576000*9/10)
5709 return 624000;
5710 else if (max_pixclk > 384000*9/10)
5711 return 576000;
5712 else if (max_pixclk > 288000*9/10)
5713 return 384000;
5714 else if (max_pixclk > 144000*9/10)
5715 return 288000;
5716 else
5717 return 144000;
5718}
5719
a821fc46
ACO		 5720/* Compute the max pixel clock for new configuration. Uses atomic state if
5721 * that's non-NULL, look at current state otherwise. */
5722static int intel_mode_max_pixclk(struct drm_device *dev,
5723 struct drm_atomic_state *state)
30a970c6 5724{
30a970c6 5725 struct intel_crtc *intel_crtc;
304603f4 5726 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5727 int max_pixclk = 0;
5728
d3fcc808 5729 for_each_intel_crtc(dev, intel_crtc) {
a821fc46
ACO		 5730 if (state)
5731 crtc_state =
5732 intel_atomic_get_crtc_state(state, intel_crtc);
5733 else
5734 crtc_state = intel_crtc->config;
304603f4
ACO		 5735 if (IS_ERR(crtc_state))
5736 return PTR_ERR(crtc_state);
5737
5738 if (!crtc_state->base.enable)
5739 continue;
5740
5741 max_pixclk = max(max_pixclk,
5742 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5743 }
5744
5745 return max_pixclk;
5746}
5747
0a9ab303 5748static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
30a970c6 5749{
304603f4 5750 struct drm_i915_private *dev_priv = to_i915(state->dev);
0a9ab303
ACO		 5751 struct drm_crtc *crtc;
5752 struct drm_crtc_state *crtc_state;
a821fc46 5753 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
0a9ab303 5754 int cdclk, i;
30a970c6 5755
304603f4
ACO		 5756 if (max_pixclk < 0)
5757 return max_pixclk;
30a970c6 5758
f8437dd1
VK		 5759 if (IS_VALLEYVIEW(dev_priv))
5760 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5761 else
5762 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5763
5764 if (cdclk == dev_priv->cdclk_freq)
304603f4 5765 return 0;
30a970c6 5766
0a9ab303
ACO		 5767 /* add all active pipes to the state */
5768 for_each_crtc(state->dev, crtc) {
5769 if (!crtc->state->enable)
5770 continue;
5771
5772 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5773 if (IS_ERR(crtc_state))
5774 return PTR_ERR(crtc_state);
5775 }
5776
2f2d7aa1 5777 /* disable/enable all currently active pipes while we change cdclk */
0a9ab303
ACO		 5778 for_each_crtc_in_state(state, crtc, crtc_state, i)
5779 if (crtc_state->enable)
5780 crtc_state->mode_changed = true;
304603f4
ACO		 5781
5782 return 0;
30a970c6
JB		 5783}
5784
1e69cd74
VS		 5785static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5786{
5787 unsigned int credits, default_credits;
5788
5789 if (IS_CHERRYVIEW(dev_priv))
5790 default_credits = PFI_CREDIT(12);
5791 else
5792 default_credits = PFI_CREDIT(8);
5793
164dfd28 5794 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 5795 /* CHV suggested value is 31 or 63 */
5796 if (IS_CHERRYVIEW(dev_priv))
5797 credits = PFI_CREDIT_31;
5798 else
5799 credits = PFI_CREDIT(15);
5800 } else {
5801 credits = default_credits;
5802 }
5803
5804 /*
5805 * WA - write default credits before re-programming
5806 * FIXME: should we also set the resend bit here?
5807 */
5808 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5809 default_credits);
5810
5811 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5812 credits | PFI_CREDIT_RESEND);
5813
5814 /*
5815 * FIXME is this guaranteed to clear
5816 * immediately or should we poll for it?
5817 */
5818 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5819}
5820
a821fc46 5821static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
30a970c6 5822{
a821fc46 5823 struct drm_device *dev = old_state->dev;
30a970c6 5824 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 5825 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
304603f4
ACO		 5826 int req_cdclk;
5827
a821fc46
ACO		 5828 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
5829 * never fail. */
304603f4
ACO		 5830 if (WARN_ON(max_pixclk < 0))
5831 return;
30a970c6 5832
304603f4 5833 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
30a970c6 5834
164dfd28 5835 if (req_cdclk != dev_priv->cdclk_freq) {
738c05c0
ID		 5836 /*
5837 * FIXME: We can end up here with all power domains off, yet
5838 * with a CDCLK frequency other than the minimum. To account
5839 * for this take the PIPE-A power domain, which covers the HW
5840 * blocks needed for the following programming. This can be
5841 * removed once it's guaranteed that we get here either with
5842 * the minimum CDCLK set, or the required power domains
5843 * enabled.
5844 */
5845 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5846
383c5a6a
VS		 5847 if (IS_CHERRYVIEW(dev))
5848 cherryview_set_cdclk(dev, req_cdclk);
5849 else
5850 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5851
1e69cd74
VS		 5852 vlv_program_pfi_credits(dev_priv);
5853
738c05c0 5854 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 5855 }
30a970c6
JB		 5856}
5857
89b667f8
JB		 5858static void valleyview_crtc_enable(struct drm_crtc *crtc)
5859{
5860 struct drm_device *dev = crtc->dev;
a72e4c9f 5861 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 5862 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5863 struct intel_encoder *encoder;
5864 int pipe = intel_crtc->pipe;
23538ef1 5865 bool is_dsi;
89b667f8 5866
83d65738 5867 WARN_ON(!crtc->state->enable);
89b667f8
JB		 5868
5869 if (intel_crtc->active)
5870 return;
5871
409ee761 5872 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 5873
1ae0d137
VS		 5874 if (!is_dsi) {
5875 if (IS_CHERRYVIEW(dev))
6e3c9717 5876 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5877 else
6e3c9717 5878 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5879 }
5b18e57c 5880
6e3c9717 5881 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5882 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5883
5884 intel_set_pipe_timings(intel_crtc);
5885
c14b0485
VS		 5886 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5887 struct drm_i915_private *dev_priv = dev->dev_private;
5888
5889 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5890 I915_WRITE(CHV_CANVAS(pipe), 0);
5891 }
5892
5b18e57c
DV		 5893 i9xx_set_pipeconf(intel_crtc);
5894
89b667f8 5895 intel_crtc->active = true;
89b667f8 5896
a72e4c9f 5897 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5898
89b667f8
JB		 5899 for_each_encoder_on_crtc(dev, crtc, encoder)
5900 if (encoder->pre_pll_enable)
5901 encoder->pre_pll_enable(encoder);
5902
9d556c99
CML		 5903 if (!is_dsi) {
5904 if (IS_CHERRYVIEW(dev))
6e3c9717 5905 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5906 else
6e3c9717 5907 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5908 }
89b667f8
JB		 5909
5910 for_each_encoder_on_crtc(dev, crtc, encoder)
5911 if (encoder->pre_enable)
5912 encoder->pre_enable(encoder);
5913
2dd24552
JB		 5914 i9xx_pfit_enable(intel_crtc);
5915
63cbb074
VS		 5916 intel_crtc_load_lut(crtc);
5917
f37fcc2a 5918 intel_update_watermarks(crtc);
e1fdc473 5919 intel_enable_pipe(intel_crtc);
be6a6f8e 5920
4b3a9526
VS		 5921 assert_vblank_disabled(crtc);
5922 drm_crtc_vblank_on(crtc);
5923
f9b61ff6
DV		 5924 for_each_encoder_on_crtc(dev, crtc, encoder)
5925 encoder->enable(encoder);
89b667f8
JB		 5926}
5927
f13c2ef3
DV		 5928static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5929{
5930 struct drm_device *dev = crtc->base.dev;
5931 struct drm_i915_private *dev_priv = dev->dev_private;
5932
6e3c9717
ACO		 5933 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5934 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 5935}
5936
0b8765c6 5937static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 5938{
5939 struct drm_device *dev = crtc->dev;
a72e4c9f 5940 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 5941 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5942 struct intel_encoder *encoder;
79e53945 5943 int pipe = intel_crtc->pipe;
79e53945 5944
83d65738 5945 WARN_ON(!crtc->state->enable);
08a48469 5946
f7abfe8b
CW		 5947 if (intel_crtc->active)
5948 return;
5949
f13c2ef3
DV		 5950 i9xx_set_pll_dividers(intel_crtc);
5951
6e3c9717 5952 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5953 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5954
5955 intel_set_pipe_timings(intel_crtc);
5956
5b18e57c
DV		 5957 i9xx_set_pipeconf(intel_crtc);
5958
f7abfe8b 5959 intel_crtc->active = true;
6b383a7f 5960
4a3436e8 5961 if (!IS_GEN2(dev))
a72e4c9f 5962 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5963
9d6d9f19
MK		 5964 for_each_encoder_on_crtc(dev, crtc, encoder)
5965 if (encoder->pre_enable)
5966 encoder->pre_enable(encoder);
5967
f6736a1a
DV		 5968 i9xx_enable_pll(intel_crtc);
5969
2dd24552
JB		 5970 i9xx_pfit_enable(intel_crtc);
5971
63cbb074
VS		 5972 intel_crtc_load_lut(crtc);
5973
f37fcc2a 5974 intel_update_watermarks(crtc);
e1fdc473 5975 intel_enable_pipe(intel_crtc);
be6a6f8e 5976
4b3a9526
VS		 5977 assert_vblank_disabled(crtc);
5978 drm_crtc_vblank_on(crtc);
5979
f9b61ff6
DV		 5980 for_each_encoder_on_crtc(dev, crtc, encoder)
5981 encoder->enable(encoder);
0b8765c6 5982}
79e53945 5983
87476d63
DV		 5984static void i9xx_pfit_disable(struct intel_crtc *crtc)
5985{
5986 struct drm_device *dev = crtc->base.dev;
5987 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 5988
6e3c9717 5989 if (!crtc->config->gmch_pfit.control)
328d8e82 5990 return;
87476d63 5991
328d8e82 5992 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 5993
328d8e82
DV		 5994 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5995 I915_READ(PFIT_CONTROL));
5996 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 5997}
5998
0b8765c6
JB		 5999static void i9xx_crtc_disable(struct drm_crtc *crtc)
6000{
6001 struct drm_device *dev = crtc->dev;
6002 struct drm_i915_private *dev_priv = dev->dev_private;
6003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6004 struct intel_encoder *encoder;
0b8765c6 6005 int pipe = intel_crtc->pipe;
ef9c3aee 6006
f7abfe8b
CW		 6007 if (!intel_crtc->active)
6008 return;
6009
6304cd91
VS		 6010 /*
6011 * On gen2 planes are double buffered but the pipe isn't, so we must
6012 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6013 * We also need to wait on all gmch platforms because of the
6014 * self-refresh mode constraint explained above.
6304cd91 6015 */
564ed191 6016 intel_wait_for_vblank(dev, pipe);
6304cd91 6017
4b3a9526
VS		 6018 for_each_encoder_on_crtc(dev, crtc, encoder)
6019 encoder->disable(encoder);
6020
f9b61ff6
DV		 6021 drm_crtc_vblank_off(crtc);
6022 assert_vblank_disabled(crtc);
6023
575f7ab7 6024 intel_disable_pipe(intel_crtc);
24a1f16d 6025
87476d63 6026 i9xx_pfit_disable(intel_crtc);
24a1f16d 6027
89b667f8
JB		 6028 for_each_encoder_on_crtc(dev, crtc, encoder)
6029 if (encoder->post_disable)
6030 encoder->post_disable(encoder);
6031
409ee761 6032 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6033 if (IS_CHERRYVIEW(dev))
6034 chv_disable_pll(dev_priv, pipe);
6035 else if (IS_VALLEYVIEW(dev))
6036 vlv_disable_pll(dev_priv, pipe);
6037 else
1c4e0274 6038 i9xx_disable_pll(intel_crtc);
076ed3b2 6039 }
0b8765c6 6040
4a3436e8 6041 if (!IS_GEN2(dev))
a72e4c9f 6042 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 6043
f7abfe8b 6044 intel_crtc->active = false;
46ba614c 6045 intel_update_watermarks(crtc);
f37fcc2a 6046
efa9624e 6047 mutex_lock(&dev->struct_mutex);
7ff0ebcc 6048 intel_fbc_update(dev);
efa9624e 6049 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 6050}
6051
ee7b9f93
JB		 6052static void i9xx_crtc_off(struct drm_crtc *crtc)
6053{
6054}
6055
b04c5bd6
BF		 6056/* Master function to enable/disable CRTC and corresponding power wells */
6057void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 6058{
6059 struct drm_device *dev = crtc->dev;
6060 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 6061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 6062 enum intel_display_power_domain domain;
6063 unsigned long domains;
976f8a20 6064
0e572fe7
DV		 6065 if (enable) {
6066 if (!intel_crtc->active) {
e1e9fb84
DV		 6067 domains = get_crtc_power_domains(crtc);
6068 for_each_power_domain(domain, domains)
6069 intel_display_power_get(dev_priv, domain);
6070 intel_crtc->enabled_power_domains = domains;
0e572fe7
DV		 6071
6072 dev_priv->display.crtc_enable(crtc);
ce22dba9 6073 intel_crtc_enable_planes(crtc);
0e572fe7
DV		 6074 }
6075 } else {
6076 if (intel_crtc->active) {
ce22dba9 6077 intel_crtc_disable_planes(crtc);
0e572fe7
DV		 6078 dev_priv->display.crtc_disable(crtc);
6079
e1e9fb84
DV		 6080 domains = intel_crtc->enabled_power_domains;
6081 for_each_power_domain(domain, domains)
6082 intel_display_power_put(dev_priv, domain);
6083 intel_crtc->enabled_power_domains = 0;
0e572fe7
DV		 6084 }
6085 }
b04c5bd6
BF		 6086}
6087
6088/**
6089 * Sets the power management mode of the pipe and plane.
6090 */
6091void intel_crtc_update_dpms(struct drm_crtc *crtc)
6092{
6093 struct drm_device *dev = crtc->dev;
6094 struct intel_encoder *intel_encoder;
6095 bool enable = false;
6096
6097 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6098 enable |= intel_encoder->connectors_active;
6099
6100 intel_crtc_control(crtc, enable);
0f63cca2
ACO		 6101
6102 crtc->state->active = enable;
976f8a20
DV		 6103}
6104
cdd59983
CW		 6105static void intel_crtc_disable(struct drm_crtc *crtc)
6106{
cdd59983 6107 struct drm_device *dev = crtc->dev;
976f8a20 6108 struct drm_connector *connector;
ee7b9f93 6109 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 6110
976f8a20 6111 /* crtc should still be enabled when we disable it. */
83d65738 6112 WARN_ON(!crtc->state->enable);
976f8a20 6113
ce22dba9 6114 intel_crtc_disable_planes(crtc);
976f8a20 6115 dev_priv->display.crtc_disable(crtc);
ee7b9f93
JB		 6116 dev_priv->display.off(crtc);
6117
70a101f8 6118 drm_plane_helper_disable(crtc->primary);
976f8a20
DV		 6119
6120 /* Update computed state. */
6121 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6122 if (!connector->encoder || !connector->encoder->crtc)
6123 continue;
6124
6125 if (connector->encoder->crtc != crtc)
6126 continue;
6127
6128 connector->dpms = DRM_MODE_DPMS_OFF;
6129 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 6130 }
6131}
6132
ea5b213a 6133void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6134{
4ef69c7a 6135 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6136
ea5b213a
CW		 6137 drm_encoder_cleanup(encoder);
6138 kfree(intel_encoder);
7e7d76c3
JB		 6139}
6140
9237329d 6141/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6142 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6143 * state of the entire output pipe. */
9237329d 6144static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6145{
5ab432ef
DV		 6146 if (mode == DRM_MODE_DPMS_ON) {
6147 encoder->connectors_active = true;
6148
b2cabb0e 6149 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6150 } else {
6151 encoder->connectors_active = false;
6152
b2cabb0e 6153 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6154 }
79e53945
JB		 6155}
6156
0a91ca29
DV		 6157/* Cross check the actual hw state with our own modeset state tracking (and it's
6158 * internal consistency). */
b980514c 6159static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6160{
0a91ca29
DV		 6161 if (connector->get_hw_state(connector)) {
6162 struct intel_encoder *encoder = connector->encoder;
6163 struct drm_crtc *crtc;
6164 bool encoder_enabled;
6165 enum pipe pipe;
6166
6167 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6168 connector->base.base.id,
c23cc417 6169 connector->base.name);
0a91ca29 6170
0e32b39c
DA		 6171 /* there is no real hw state for MST connectors */
6172 if (connector->mst_port)
6173 return;
6174
e2c719b7 6175 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6176 "wrong connector dpms state\n");
e2c719b7 6177 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6178 "active connector not linked to encoder\n");
0a91ca29 6179
36cd7444 6180 if (encoder) {
e2c719b7 6181 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6182 "encoder->connectors_active not set\n");
6183
6184 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6185 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6186 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6187 return;
0a91ca29 6188
36cd7444 6189 crtc = encoder->base.crtc;
0a91ca29 6190
83d65738
MR		 6191 I915_STATE_WARN(!crtc->state->enable,
6192 "crtc not enabled\n");
e2c719b7
RC		 6193 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6194 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6195 "encoder active on the wrong pipe\n");
6196 }
0a91ca29 6197 }
79e53945
JB		 6198}
6199
08d9bc92
ACO		 6200int intel_connector_init(struct intel_connector *connector)
6201{
6202 struct drm_connector_state *connector_state;
6203
6204 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6205 if (!connector_state)
6206 return -ENOMEM;
6207
6208 connector->base.state = connector_state;
6209 return 0;
6210}
6211
6212struct intel_connector *intel_connector_alloc(void)
6213{
6214 struct intel_connector *connector;
6215
6216 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6217 if (!connector)
6218 return NULL;
6219
6220 if (intel_connector_init(connector) < 0) {
6221 kfree(connector);
6222 return NULL;
6223 }
6224
6225 return connector;
6226}
6227
5ab432ef
DV		 6228/* Even simpler default implementation, if there's really no special case to
6229 * consider. */
6230void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6231{
5ab432ef
DV		 6232 /* All the simple cases only support two dpms states. */
6233 if (mode != DRM_MODE_DPMS_ON)
6234 mode = DRM_MODE_DPMS_OFF;
d4270e57 6235
5ab432ef
DV		 6236 if (mode == connector->dpms)
6237 return;
6238
6239 connector->dpms = mode;
6240
6241 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6242 if (connector->encoder)
6243 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6244
b980514c 6245 intel_modeset_check_state(connector->dev);
79e53945
JB		 6246}
6247
f0947c37
DV		 6248/* Simple connector->get_hw_state implementation for encoders that support only
6249 * one connector and no cloning and hence the encoder state determines the state
6250 * of the connector. */
6251bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6252{
24929352 6253 enum pipe pipe = 0;
f0947c37 6254 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6255
f0947c37 6256 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6257}
6258
6d293983 6259static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6260{
6d293983
ACO		 6261 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6262 return crtc_state->fdi_lanes;
d272ddfa
VS		 6263
6264 return 0;
6265}
6266
6d293983 6267static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6268 struct intel_crtc_state *pipe_config)
1857e1da 6269{
6d293983
ACO		 6270 struct drm_atomic_state *state = pipe_config->base.state;
6271 struct intel_crtc *other_crtc;
6272 struct intel_crtc_state *other_crtc_state;
6273
1857e1da
DV		 6274 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6275 pipe_name(pipe), pipe_config->fdi_lanes);
6276 if (pipe_config->fdi_lanes > 4) {
6277 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6278 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6279 return -EINVAL;
1857e1da
DV		 6280 }
6281
bafb6553 6282 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6283 if (pipe_config->fdi_lanes > 2) {
6284 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6285 pipe_config->fdi_lanes);
6d293983 6286 return -EINVAL;
1857e1da 6287 } else {
6d293983 6288 return 0;
1857e1da
DV		 6289 }
6290 }
6291
6292 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6293 return 0;
1857e1da
DV		 6294
6295 /* Ivybridge 3 pipe is really complicated */
6296 switch (pipe) {
6297 case PIPE_A:
6d293983 6298 return 0;
1857e1da 6299 case PIPE_B:
6d293983
ACO		 6300 if (pipe_config->fdi_lanes <= 2)
6301 return 0;
6302
6303 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6304 other_crtc_state =
6305 intel_atomic_get_crtc_state(state, other_crtc);
6306 if (IS_ERR(other_crtc_state))
6307 return PTR_ERR(other_crtc_state);
6308
6309 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6310 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6311 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6312 return -EINVAL;
1857e1da 6313 }
6d293983 6314 return 0;
1857e1da 6315 case PIPE_C:
251cc67c
VS		 6316 if (pipe_config->fdi_lanes > 2) {
6317 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6318 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6319 return -EINVAL;
251cc67c 6320 }
6d293983
ACO		 6321
6322 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6323 other_crtc_state =
6324 intel_atomic_get_crtc_state(state, other_crtc);
6325 if (IS_ERR(other_crtc_state))
6326 return PTR_ERR(other_crtc_state);
6327
6328 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6329 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6330 return -EINVAL;
1857e1da 6331 }
6d293983 6332 return 0;
1857e1da
DV		 6333 default:
6334 BUG();
6335 }
6336}
6337
e29c22c0
DV		 6338#define RETRY 1
6339static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6340 struct intel_crtc_state *pipe_config)
877d48d5 6341{
1857e1da 6342 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6343 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6344 int lane, link_bw, fdi_dotclock, ret;
6345 bool needs_recompute = false;
877d48d5 6346
e29c22c0 6347retry:
877d48d5
DV		 6348 /* FDI is a binary signal running at ~2.7GHz, encoding
6349 * each output octet as 10 bits. The actual frequency
6350 * is stored as a divider into a 100MHz clock, and the
6351 * mode pixel clock is stored in units of 1KHz.
6352 * Hence the bw of each lane in terms of the mode signal
6353 * is:
6354 */
6355 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6356
241bfc38 6357 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6358
2bd89a07 6359 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6360 pipe_config->pipe_bpp);
6361
6362 pipe_config->fdi_lanes = lane;
6363
2bd89a07 6364 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6365 link_bw, &pipe_config->fdi_m_n);
1857e1da 6366
6d293983
ACO		 6367 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6368 intel_crtc->pipe, pipe_config);
6369 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6370 pipe_config->pipe_bpp -= 2*3;
6371 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6372 pipe_config->pipe_bpp);
6373 needs_recompute = true;
6374 pipe_config->bw_constrained = true;
6375
6376 goto retry;
6377 }
6378
6379 if (needs_recompute)
6380 return RETRY;
6381
6d293983 6382 return ret;
877d48d5
DV		 6383}
6384
42db64ef 6385static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6386 struct intel_crtc_state *pipe_config)
42db64ef 6387{
d330a953 6388 pipe_config->ips_enabled = i915.enable_ips &&
3c4ca58c 6389 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 6390 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 6391}
6392
a43f6e0f 6393static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6394 struct intel_crtc_state *pipe_config)
79e53945 6395{
a43f6e0f 6396 struct drm_device *dev = crtc->base.dev;
8bd31e67 6397 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6398 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
d03c93d4 6399 int ret;
89749350 6400
ad3a4479 6401 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6402 if (INTEL_INFO(dev)->gen < 4) {
cf532bb2
VS		 6403 int clock_limit =
6404 dev_priv->display.get_display_clock_speed(dev);
6405
6406 /*
6407 * Enable pixel doubling when the dot clock
6408 * is > 90% of the (display) core speed.
6409 *
b397c96b
VS		 6410 * GDG double wide on either pipe,
6411 * otherwise pipe A only.
cf532bb2 6412 */
b397c96b 6413 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6414 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6415 clock_limit *= 2;
cf532bb2 6416 pipe_config->double_wide = true;
ad3a4479
VS		 6417 }
6418
241bfc38 6419 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6420 return -EINVAL;
2c07245f 6421 }
89749350 6422
1d1d0e27
VS		 6423 /*
6424 * Pipe horizontal size must be even in:
6425 * - DVO ganged mode
6426 * - LVDS dual channel mode
6427 * - Double wide pipe
6428 */
a93e255f 6429 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6430 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6431 pipe_config->pipe_src_w &= ~1;
6432
8693a824
DL		 6433 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6434 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6435 */
6436 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6437 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6438 return -EINVAL;
44f46b42 6439
f5adf94e 6440 if (HAS_IPS(dev))
a43f6e0f
DV		 6441 hsw_compute_ips_config(crtc, pipe_config);
6442
877d48d5 6443 if (pipe_config->has_pch_encoder)
a43f6e0f 6444 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6445
d03c93d4
CK		 6446 /* FIXME: remove below call once atomic mode set is place and all crtc
6447 * related checks called from atomic_crtc_check function */
6448 ret = 0;
6449 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6450 crtc, pipe_config->base.state);
6451 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6452
6453 return ret;
79e53945
JB		 6454}
6455
1652d19e
VS		 6456static int skylake_get_display_clock_speed(struct drm_device *dev)
6457{
6458 struct drm_i915_private *dev_priv = to_i915(dev);
6459 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6460 uint32_t cdctl = I915_READ(CDCLK_CTL);
6461 uint32_t linkrate;
6462
6463 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6464 WARN(1, "LCPLL1 not enabled\n");
6465 return 24000; /* 24MHz is the cd freq with NSSC ref */
6466 }
6467
6468 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6469 return 540000;
6470
6471 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6472 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6473
71cd8423
DL		 6474 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6475 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6476 /* vco 8640 */
6477 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6478 case CDCLK_FREQ_450_432:
6479 return 432000;
6480 case CDCLK_FREQ_337_308:
6481 return 308570;
6482 case CDCLK_FREQ_675_617:
6483 return 617140;
6484 default:
6485 WARN(1, "Unknown cd freq selection\n");
6486 }
6487 } else {
6488 /* vco 8100 */
6489 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6490 case CDCLK_FREQ_450_432:
6491 return 450000;
6492 case CDCLK_FREQ_337_308:
6493 return 337500;
6494 case CDCLK_FREQ_675_617:
6495 return 675000;
6496 default:
6497 WARN(1, "Unknown cd freq selection\n");
6498 }
6499 }
6500
6501 /* error case, do as if DPLL0 isn't enabled */
6502 return 24000;
6503}
6504
6505static int broadwell_get_display_clock_speed(struct drm_device *dev)
6506{
6507 struct drm_i915_private *dev_priv = dev->dev_private;
6508 uint32_t lcpll = I915_READ(LCPLL_CTL);
6509 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6510
6511 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6512 return 800000;
6513 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6514 return 450000;
6515 else if (freq == LCPLL_CLK_FREQ_450)
6516 return 450000;
6517 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6518 return 540000;
6519 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6520 return 337500;
6521 else
6522 return 675000;
6523}
6524
6525static int haswell_get_display_clock_speed(struct drm_device *dev)
6526{
6527 struct drm_i915_private *dev_priv = dev->dev_private;
6528 uint32_t lcpll = I915_READ(LCPLL_CTL);
6529 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6530
6531 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6532 return 800000;
6533 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6534 return 450000;
6535 else if (freq == LCPLL_CLK_FREQ_450)
6536 return 450000;
6537 else if (IS_HSW_ULT(dev))
6538 return 337500;
6539 else
6540 return 540000;
79e53945
JB		 6541}
6542
25eb05fc
JB		 6543static int valleyview_get_display_clock_speed(struct drm_device *dev)
6544{
d197b7d3 6545 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6546 u32 val;
6547 int divider;
6548
6bcda4f0
VS		 6549 if (dev_priv->hpll_freq == 0)
6550 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6551
d197b7d3
VS		 6552 mutex_lock(&dev_priv->dpio_lock);
6553 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6554 mutex_unlock(&dev_priv->dpio_lock);
6555
6556 divider = val & DISPLAY_FREQUENCY_VALUES;
6557
7d007f40
VS		 6558 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6559 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6560 "cdclk change in progress\n");
6561
6bcda4f0 6562 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6563}
6564
b37a6434
VS		 6565static int ilk_get_display_clock_speed(struct drm_device *dev)
6566{
6567 return 450000;
6568}
6569
e70236a8
JB		 6570static int i945_get_display_clock_speed(struct drm_device *dev)
6571{
6572 return 400000;
6573}
79e53945 6574
e70236a8 6575static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6576{
e907f170 6577 return 333333;
e70236a8 6578}
79e53945 6579
e70236a8
JB		 6580static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6581{
6582 return 200000;
6583}
79e53945 6584
257a7ffc
DV		 6585static int pnv_get_display_clock_speed(struct drm_device *dev)
6586{
6587 u16 gcfgc = 0;
6588
6589 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6590
6591 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6592 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6593 return 266667;
257a7ffc 6594 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6595 return 333333;
257a7ffc 6596 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6597 return 444444;
257a7ffc
DV		 6598 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6599 return 200000;
6600 default:
6601 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6602 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6603 return 133333;
257a7ffc 6604 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6605 return 166667;
257a7ffc
DV		 6606 }
6607}
6608
e70236a8
JB		 6609static int i915gm_get_display_clock_speed(struct drm_device *dev)
6610{
6611 u16 gcfgc = 0;
79e53945 6612
e70236a8
JB		 6613 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6614
6615 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6616 return 133333;
e70236a8
JB		 6617 else {
6618 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6619 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6620 return 333333;
e70236a8
JB		 6621 default:
6622 case GC_DISPLAY_CLOCK_190_200_MHZ:
6623 return 190000;
79e53945 6624 }
e70236a8
JB		 6625 }
6626}
6627
6628static int i865_get_display_clock_speed(struct drm_device *dev)
6629{
e907f170 6630 return 266667;
e70236a8
JB		 6631}
6632
6633static int i855_get_display_clock_speed(struct drm_device *dev)
6634{
6635 u16 hpllcc = 0;
6636 /* Assume that the hardware is in the high speed state. This
6637 * should be the default.
6638 */
6639 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6640 case GC_CLOCK_133_200:
6641 case GC_CLOCK_100_200:
6642 return 200000;
6643 case GC_CLOCK_166_250:
6644 return 250000;
6645 case GC_CLOCK_100_133:
e907f170 6646 return 133333;
e70236a8 6647 }
79e53945 6648
e70236a8
JB		 6649 /* Shouldn't happen */
6650 return 0;
6651}
79e53945 6652
e70236a8
JB		 6653static int i830_get_display_clock_speed(struct drm_device *dev)
6654{
e907f170 6655 return 133333;
79e53945
JB		 6656}
6657
2c07245f 6658static void
a65851af 6659intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6660{
a65851af
VS		 6661 while (*num > DATA_LINK_M_N_MASK ||
6662 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 6663 *num >>= 1;
6664 *den >>= 1;
6665 }
6666}
6667
a65851af
VS		 6668static void compute_m_n(unsigned int m, unsigned int n,
6669 uint32_t *ret_m, uint32_t *ret_n)
6670{
6671 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6672 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6673 intel_reduce_m_n_ratio(ret_m, ret_n);
6674}
6675
e69d0bc1
DV		 6676void
6677intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6678 int pixel_clock, int link_clock,
6679 struct intel_link_m_n *m_n)
2c07245f 6680{
e69d0bc1 6681 m_n->tu = 64;
a65851af
VS		 6682
6683 compute_m_n(bits_per_pixel * pixel_clock,
6684 link_clock * nlanes * 8,
6685 &m_n->gmch_m, &m_n->gmch_n);
6686
6687 compute_m_n(pixel_clock, link_clock,
6688 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 6689}
6690
a7615030
CW		 6691static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6692{
d330a953
JN		 6693 if (i915.panel_use_ssc >= 0)
6694 return i915.panel_use_ssc != 0;
41aa3448 6695 return dev_priv->vbt.lvds_use_ssc
435793df 6696 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 6697}
6698
a93e255f
ACO		 6699static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6700 int num_connectors)
c65d77d8 6701{
a93e255f 6702 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 6703 struct drm_i915_private *dev_priv = dev->dev_private;
6704 int refclk;
6705
a93e255f
ACO		 6706 WARN_ON(!crtc_state->base.state);
6707
5ab7b0b7 6708 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 6709 refclk = 100000;
a93e255f 6710 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 6711 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 6712 refclk = dev_priv->vbt.lvds_ssc_freq;
6713 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 6714 } else if (!IS_GEN2(dev)) {
6715 refclk = 96000;
6716 } else {
6717 refclk = 48000;
6718 }
6719
6720 return refclk;
6721}
6722
7429e9d4 6723static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 6724{
7df00d7a 6725 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 6726}
f47709a9 6727
7429e9d4
DV		 6728static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6729{
6730 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 6731}
6732
f47709a9 6733static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 6734 struct intel_crtc_state *crtc_state,
a7516a05
JB		 6735 intel_clock_t *reduced_clock)
6736{
f47709a9 6737 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 6738 u32 fp, fp2 = 0;
6739
6740 if (IS_PINEVIEW(dev)) {
190f68c5 6741 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6742 if (reduced_clock)
7429e9d4 6743 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 6744 } else {
190f68c5 6745 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6746 if (reduced_clock)
7429e9d4 6747 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 6748 }
6749
190f68c5 6750 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 6751
f47709a9 6752 crtc->lowfreq_avail = false;
a93e255f 6753 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 6754 reduced_clock) {
190f68c5 6755 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 6756 crtc->lowfreq_avail = true;
a7516a05 6757 } else {
190f68c5 6758 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 6759 }
6760}
6761
5e69f97f
CML		 6762static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6763 pipe)
89b667f8
JB		 6764{
6765 u32 reg_val;
6766
6767 /*
6768 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6769 * and set it to a reasonable value instead.
6770 */
ab3c759a 6771 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 6772 reg_val &= 0xffffff00;
6773 reg_val |= 0x00000030;
ab3c759a 6774 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6775
ab3c759a 6776 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6777 reg_val &= 0x8cffffff;
6778 reg_val = 0x8c000000;
ab3c759a 6779 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 6780
ab3c759a 6781 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 6782 reg_val &= 0xffffff00;
ab3c759a 6783 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6784
ab3c759a 6785 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6786 reg_val &= 0x00ffffff;
6787 reg_val |= 0xb0000000;
ab3c759a 6788 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 6789}
6790
b551842d
DV		 6791static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6792 struct intel_link_m_n *m_n)
6793{
6794 struct drm_device *dev = crtc->base.dev;
6795 struct drm_i915_private *dev_priv = dev->dev_private;
6796 int pipe = crtc->pipe;
6797
e3b95f1e
DV		 6798 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6799 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6800 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6801 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 6802}
6803
6804static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 6805 struct intel_link_m_n *m_n,
6806 struct intel_link_m_n *m2_n2)
b551842d
DV		 6807{
6808 struct drm_device *dev = crtc->base.dev;
6809 struct drm_i915_private *dev_priv = dev->dev_private;
6810 int pipe = crtc->pipe;
6e3c9717 6811 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 6812
6813 if (INTEL_INFO(dev)->gen >= 5) {
6814 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6815 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6816 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6817 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 6818 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6819 * for gen < 8) and if DRRS is supported (to make sure the
6820 * registers are not unnecessarily accessed).
6821 */
44395bfe 6822 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 6823 crtc->config->has_drrs) {
f769cd24
VK		 6824 I915_WRITE(PIPE_DATA_M2(transcoder),
6825 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6826 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6827 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6828 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6829 }
b551842d 6830 } else {
e3b95f1e
DV		 6831 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6832 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6833 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6834 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 6835 }
6836}
6837
fe3cd48d 6838void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 6839{
fe3cd48d
R		 6840 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6841
6842 if (m_n == M1_N1) {
6843 dp_m_n = &crtc->config->dp_m_n;
6844 dp_m2_n2 = &crtc->config->dp_m2_n2;
6845 } else if (m_n == M2_N2) {
6846
6847 /*
6848 * M2_N2 registers are not supported. Hence m2_n2 divider value
6849 * needs to be programmed into M1_N1.
6850 */
6851 dp_m_n = &crtc->config->dp_m2_n2;
6852 } else {
6853 DRM_ERROR("Unsupported divider value\n");
6854 return;
6855 }
6856
6e3c9717
ACO		 6857 if (crtc->config->has_pch_encoder)
6858 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 6859 else
fe3cd48d 6860 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 6861}
6862
d288f65f 6863static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 6864 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 6865{
6866 u32 dpll, dpll_md;
6867
6868 /*
6869 * Enable DPIO clock input. We should never disable the reference
6870 * clock for pipe B, since VGA hotplug / manual detection depends
6871 * on it.
6872 */
6873 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6874 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6875 /* We should never disable this, set it here for state tracking */
6876 if (crtc->pipe == PIPE_B)
6877 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6878 dpll |= DPLL_VCO_ENABLE;
d288f65f 6879 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 6880
d288f65f 6881 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 6882 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 6883 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 6884}
6885
d288f65f 6886static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6887 const struct intel_crtc_state *pipe_config)
a0c4da24 6888{
f47709a9 6889 struct drm_device *dev = crtc->base.dev;
a0c4da24 6890 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 6891 int pipe = crtc->pipe;
bdd4b6a6 6892 u32 mdiv;
a0c4da24 6893 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 6894 u32 coreclk, reg_val;
a0c4da24 6895
09153000
DV		 6896 mutex_lock(&dev_priv->dpio_lock);
6897
d288f65f
VS		 6898 bestn = pipe_config->dpll.n;
6899 bestm1 = pipe_config->dpll.m1;
6900 bestm2 = pipe_config->dpll.m2;
6901 bestp1 = pipe_config->dpll.p1;
6902 bestp2 = pipe_config->dpll.p2;
a0c4da24 6903
89b667f8
JB		 6904 /* See eDP HDMI DPIO driver vbios notes doc */
6905
6906 /* PLL B needs special handling */
bdd4b6a6 6907 if (pipe == PIPE_B)
5e69f97f 6908 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 6909
6910 /* Set up Tx target for periodic Rcomp update */
ab3c759a 6911 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 6912
6913 /* Disable target IRef on PLL */
ab3c759a 6914 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 6915 reg_val &= 0x00ffffff;
ab3c759a 6916 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 6917
6918 /* Disable fast lock */
ab3c759a 6919 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 6920
6921 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 6922 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6923 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6924 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 6925 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 6926
6927 /*
6928 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6929 * but we don't support that).
6930 * Note: don't use the DAC post divider as it seems unstable.
6931 */
6932 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 6933 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6934
a0c4da24 6935 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 6936 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6937
89b667f8 6938 /* Set HBR and RBR LPF coefficients */
d288f65f 6939 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 6940 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6941 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 6942 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 6943 0x009f0003);
89b667f8 6944 else
ab3c759a 6945 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 6946 0x00d0000f);
6947
681a8504 6948 if (pipe_config->has_dp_encoder) {
89b667f8 6949 /* Use SSC source */
bdd4b6a6 6950 if (pipe == PIPE_A)
ab3c759a 6951 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6952 0x0df40000);
6953 else
ab3c759a 6954 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6955 0x0df70000);
6956 } else { /* HDMI or VGA */
6957 /* Use bend source */
bdd4b6a6 6958 if (pipe == PIPE_A)
ab3c759a 6959 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6960 0x0df70000);
6961 else
ab3c759a 6962 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6963 0x0df40000);
6964 }
a0c4da24 6965
ab3c759a 6966 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 6967 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 6968 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6969 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 6970 coreclk |= 0x01000000;
ab3c759a 6971 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 6972
ab3c759a 6973 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
09153000 6974 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 6975}
6976
d288f65f 6977static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 6978 struct intel_crtc_state *pipe_config)
1ae0d137 6979{
d288f65f 6980 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 6981 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6982 DPLL_VCO_ENABLE;
6983 if (crtc->pipe != PIPE_A)
d288f65f 6984 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 6985
d288f65f
VS		 6986 pipe_config->dpll_hw_state.dpll_md =
6987 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 6988}
6989
d288f65f 6990static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6991 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 6992{
6993 struct drm_device *dev = crtc->base.dev;
6994 struct drm_i915_private *dev_priv = dev->dev_private;
6995 int pipe = crtc->pipe;
6996 int dpll_reg = DPLL(crtc->pipe);
6997 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 6998 u32 loopfilter, tribuf_calcntr;
9d556c99 6999 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7000 u32 dpio_val;
9cbe40c1 7001 int vco;
9d556c99 7002
d288f65f
VS		 7003 bestn = pipe_config->dpll.n;
7004 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7005 bestm1 = pipe_config->dpll.m1;
7006 bestm2 = pipe_config->dpll.m2 >> 22;
7007 bestp1 = pipe_config->dpll.p1;
7008 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7009 vco = pipe_config->dpll.vco;
a945ce7e 7010 dpio_val = 0;
9cbe40c1 7011 loopfilter = 0;
9d556c99
CML		 7012
7013 /*
7014 * Enable Refclk and SSC
7015 */
a11b0703 7016 I915_WRITE(dpll_reg,
d288f65f 7017 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703
VS		 7018
7019 mutex_lock(&dev_priv->dpio_lock);
9d556c99 7020
9d556c99
CML		 7021 /* p1 and p2 divider */
7022 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7023 5 << DPIO_CHV_S1_DIV_SHIFT |
7024 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7025 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7026 1 << DPIO_CHV_K_DIV_SHIFT);
7027
7028 /* Feedback post-divider - m2 */
7029 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7030
7031 /* Feedback refclk divider - n and m1 */
7032 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7033 DPIO_CHV_M1_DIV_BY_2 |
7034 1 << DPIO_CHV_N_DIV_SHIFT);
7035
7036 /* M2 fraction division */
a945ce7e
VP		 7037 if (bestm2_frac)
7038 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7039
7040 /* M2 fraction division enable */
a945ce7e
VP		 7041 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7042 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7043 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7044 if (bestm2_frac)
7045 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7046 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7047
de3a0fde
VP		 7048 /* Program digital lock detect threshold */
7049 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7050 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7051 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7052 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7053 if (!bestm2_frac)
7054 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7055 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7056
9d556c99 7057 /* Loop filter */
9cbe40c1
VP		 7058 if (vco == 5400000) {
7059 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7060 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7061 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7062 tribuf_calcntr = 0x9;
7063 } else if (vco <= 6200000) {
7064 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7065 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7066 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7067 tribuf_calcntr = 0x9;
7068 } else if (vco <= 6480000) {
7069 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7070 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7071 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7072 tribuf_calcntr = 0x8;
7073 } else {
7074 /* Not supported. Apply the same limits as in the max case */
7075 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7076 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7077 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7078 tribuf_calcntr = 0;
7079 }
9d556c99
CML		 7080 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7081
968040b2 7082 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7083 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7084 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7085 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7086
9d556c99
CML		 7087 /* AFC Recal */
7088 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7089 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7090 DPIO_AFC_RECAL);
7091
7092 mutex_unlock(&dev_priv->dpio_lock);
7093}
7094
d288f65f
VS		 7095/**
7096 * vlv_force_pll_on - forcibly enable just the PLL
7097 * @dev_priv: i915 private structure
7098 * @pipe: pipe PLL to enable
7099 * @dpll: PLL configuration
7100 *
7101 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7102 * in cases where we need the PLL enabled even when @pipe is not going to
7103 * be enabled.
7104 */
7105void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7106 const struct dpll *dpll)
7107{
7108 struct intel_crtc *crtc =
7109 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7110 struct intel_crtc_state pipe_config = {
a93e255f 7111 .base.crtc = &crtc->base,
d288f65f
VS		 7112 .pixel_multiplier = 1,
7113 .dpll = *dpll,
7114 };
7115
7116 if (IS_CHERRYVIEW(dev)) {
7117 chv_update_pll(crtc, &pipe_config);
7118 chv_prepare_pll(crtc, &pipe_config);
7119 chv_enable_pll(crtc, &pipe_config);
7120 } else {
7121 vlv_update_pll(crtc, &pipe_config);
7122 vlv_prepare_pll(crtc, &pipe_config);
7123 vlv_enable_pll(crtc, &pipe_config);
7124 }
7125}
7126
7127/**
7128 * vlv_force_pll_off - forcibly disable just the PLL
7129 * @dev_priv: i915 private structure
7130 * @pipe: pipe PLL to disable
7131 *
7132 * Disable the PLL for @pipe. To be used in cases where we need
7133 * the PLL enabled even when @pipe is not going to be enabled.
7134 */
7135void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7136{
7137 if (IS_CHERRYVIEW(dev))
7138 chv_disable_pll(to_i915(dev), pipe);
7139 else
7140 vlv_disable_pll(to_i915(dev), pipe);
7141}
7142
f47709a9 7143static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 7144 struct intel_crtc_state *crtc_state,
f47709a9 7145 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7146 int num_connectors)
7147{
f47709a9 7148 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7149 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7150 u32 dpll;
7151 bool is_sdvo;
190f68c5 7152 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7153
190f68c5 7154 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7155
a93e255f
ACO		 7156 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7157 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7158
7159 dpll = DPLL_VGA_MODE_DIS;
7160
a93e255f 7161 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7162 dpll |= DPLLB_MODE_LVDS;
7163 else
7164 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7165
ef1b460d 7166 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7167 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7168 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7169 }
198a037f
DV		 7170
7171 if (is_sdvo)
4a33e48d 7172 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7173
190f68c5 7174 if (crtc_state->has_dp_encoder)
4a33e48d 7175 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7176
7177 /* compute bitmask from p1 value */
7178 if (IS_PINEVIEW(dev))
7179 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7180 else {
7181 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7182 if (IS_G4X(dev) && reduced_clock)
7183 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7184 }
7185 switch (clock->p2) {
7186 case 5:
7187 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7188 break;
7189 case 7:
7190 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7191 break;
7192 case 10:
7193 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7194 break;
7195 case 14:
7196 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7197 break;
7198 }
7199 if (INTEL_INFO(dev)->gen >= 4)
7200 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7201
190f68c5 7202 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7203 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7204 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7205 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7206 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7207 else
7208 dpll |= PLL_REF_INPUT_DREFCLK;
7209
7210 dpll |= DPLL_VCO_ENABLE;
190f68c5 7211 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7212
eb1cbe48 7213 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7214 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7215 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7216 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7217 }
7218}
7219
f47709a9 7220static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 7221 struct intel_crtc_state *crtc_state,
f47709a9 7222 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7223 int num_connectors)
7224{
f47709a9 7225 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7226 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7227 u32 dpll;
190f68c5 7228 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7229
190f68c5 7230 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7231
eb1cbe48
DV		 7232 dpll = DPLL_VGA_MODE_DIS;
7233
a93e255f 7234 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7235 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7236 } else {
7237 if (clock->p1 == 2)
7238 dpll |= PLL_P1_DIVIDE_BY_TWO;
7239 else
7240 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7241 if (clock->p2 == 4)
7242 dpll |= PLL_P2_DIVIDE_BY_4;
7243 }
7244
a93e255f 7245 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7246 dpll |= DPLL_DVO_2X_MODE;
7247
a93e255f 7248 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7249 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7250 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7251 else
7252 dpll |= PLL_REF_INPUT_DREFCLK;
7253
7254 dpll |= DPLL_VCO_ENABLE;
190f68c5 7255 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7256}
7257
8a654f3b 7258static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7259{
7260 struct drm_device *dev = intel_crtc->base.dev;
7261 struct drm_i915_private *dev_priv = dev->dev_private;
7262 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7263 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7264 struct drm_display_mode *adjusted_mode =
6e3c9717 7265 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7266 uint32_t crtc_vtotal, crtc_vblank_end;
7267 int vsyncshift = 0;
4d8a62ea
DV		 7268
7269 /* We need to be careful not to changed the adjusted mode, for otherwise
7270 * the hw state checker will get angry at the mismatch. */
7271 crtc_vtotal = adjusted_mode->crtc_vtotal;
7272 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7273
609aeaca 7274 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7275 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7276 crtc_vtotal -= 1;
7277 crtc_vblank_end -= 1;
609aeaca 7278
409ee761 7279 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7280 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7281 else
7282 vsyncshift = adjusted_mode->crtc_hsync_start -
7283 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7284 if (vsyncshift < 0)
7285 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7286 }
7287
7288 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7289 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7290
fe2b8f9d 7291 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7292 (adjusted_mode->crtc_hdisplay - 1) |
7293 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7294 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7295 (adjusted_mode->crtc_hblank_start - 1) |
7296 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7297 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7298 (adjusted_mode->crtc_hsync_start - 1) |
7299 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7300
fe2b8f9d 7301 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7302 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7303 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7304 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7305 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7306 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7307 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7308 (adjusted_mode->crtc_vsync_start - 1) |
7309 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7310
b5e508d4
PZ		 7311 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7312 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7313 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7314 * bits. */
7315 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7316 (pipe == PIPE_B || pipe == PIPE_C))
7317 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7318
b0e77b9c
PZ		 7319 /* pipesrc controls the size that is scaled from, which should
7320 * always be the user's requested size.
7321 */
7322 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7323 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7324 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7325}
7326
1bd1bd80 7327static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7328 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7329{
7330 struct drm_device *dev = crtc->base.dev;
7331 struct drm_i915_private *dev_priv = dev->dev_private;
7332 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7333 uint32_t tmp;
7334
7335 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7336 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7337 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7338 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7339 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7340 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7341 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7342 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7343 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7344
7345 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7346 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7347 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7348 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7349 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7350 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7351 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7352 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7353 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7354
7355 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7356 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7357 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7358 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7359 }
7360
7361 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7362 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7363 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7364
2d112de7
ACO		 7365 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7366 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7367}
7368
f6a83288 7369void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7370 struct intel_crtc_state *pipe_config)
babea61d 7371{
2d112de7
ACO		 7372 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7373 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7374 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7375 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7376
2d112de7
ACO		 7377 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7378 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7379 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7380 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7381
2d112de7 7382 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7383
2d112de7
ACO		 7384 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7385 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7386}
7387
84b046f3
DV		 7388static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7389{
7390 struct drm_device *dev = intel_crtc->base.dev;
7391 struct drm_i915_private *dev_priv = dev->dev_private;
7392 uint32_t pipeconf;
7393
9f11a9e4 7394 pipeconf = 0;
84b046f3 7395
b6b5d049
VS		 7396 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7397 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7398 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7399
6e3c9717 7400 if (intel_crtc->config->double_wide)
cf532bb2 7401 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7402
ff9ce46e
DV		 7403 /* only g4x and later have fancy bpc/dither controls */
7404 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7405 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7406 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7407 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7408 PIPECONF_DITHER_TYPE_SP;
84b046f3 7409
6e3c9717 7410 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7411 case 18:
7412 pipeconf |= PIPECONF_6BPC;
7413 break;
7414 case 24:
7415 pipeconf |= PIPECONF_8BPC;
7416 break;
7417 case 30:
7418 pipeconf |= PIPECONF_10BPC;
7419 break;
7420 default:
7421 /* Case prevented by intel_choose_pipe_bpp_dither. */
7422 BUG();
84b046f3
DV		 7423 }
7424 }
7425
7426 if (HAS_PIPE_CXSR(dev)) {
7427 if (intel_crtc->lowfreq_avail) {
7428 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7429 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7430 } else {
7431 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7432 }
7433 }
7434
6e3c9717 7435 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7436 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7437 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7438 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7439 else
7440 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7441 } else
84b046f3
DV		 7442 pipeconf |= PIPECONF_PROGRESSIVE;
7443
6e3c9717 7444 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7445 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7446
84b046f3
DV		 7447 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7448 POSTING_READ(PIPECONF(intel_crtc->pipe));
7449}
7450
190f68c5
ACO		 7451static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7452 struct intel_crtc_state *crtc_state)
79e53945 7453{
c7653199 7454 struct drm_device *dev = crtc->base.dev;
79e53945 7455 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7456 int refclk, num_connectors = 0;
652c393a 7457 intel_clock_t clock, reduced_clock;
a16af721 7458 bool ok, has_reduced_clock = false;
e9fd1c02 7459 bool is_lvds = false, is_dsi = false;
5eddb70b 7460 struct intel_encoder *encoder;
d4906093 7461 const intel_limit_t *limit;
55bb9992 7462 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7463 struct drm_connector *connector;
55bb9992
ACO		 7464 struct drm_connector_state *connector_state;
7465 int i;
79e53945 7466
dd3cd74a
ACO		 7467 memset(&crtc_state->dpll_hw_state, 0,
7468 sizeof(crtc_state->dpll_hw_state));
7469
da3ced29 7470 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7471 if (connector_state->crtc != &crtc->base)
7472 continue;
7473
7474 encoder = to_intel_encoder(connector_state->best_encoder);
7475
5eddb70b 7476 switch (encoder->type) {
79e53945
JB		 7477 case INTEL_OUTPUT_LVDS:
7478 is_lvds = true;
7479 break;
e9fd1c02
JN		 7480 case INTEL_OUTPUT_DSI:
7481 is_dsi = true;
7482 break;
6847d71b
PZ		 7483 default:
7484 break;
79e53945 7485 }
43565a06 7486
c751ce4f 7487 num_connectors++;
79e53945
JB		 7488 }
7489
f2335330 7490 if (is_dsi)
5b18e57c 7491 return 0;
f2335330 7492
190f68c5 7493 if (!crtc_state->clock_set) {
a93e255f 7494 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7495
e9fd1c02
JN		 7496 /*
7497 * Returns a set of divisors for the desired target clock with
7498 * the given refclk, or FALSE. The returned values represent
7499 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7500 * 2) / p1 / p2.
7501 */
a93e255f
ACO		 7502 limit = intel_limit(crtc_state, refclk);
7503 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7504 crtc_state->port_clock,
e9fd1c02 7505 refclk, NULL, &clock);
f2335330 7506 if (!ok) {
e9fd1c02
JN		 7507 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7508 return -EINVAL;
7509 }
79e53945 7510
f2335330
JN		 7511 if (is_lvds && dev_priv->lvds_downclock_avail) {
7512 /*
7513 * Ensure we match the reduced clock's P to the target
7514 * clock. If the clocks don't match, we can't switch
7515 * the display clock by using the FP0/FP1. In such case
7516 * we will disable the LVDS downclock feature.
7517 */
7518 has_reduced_clock =
a93e255f 7519 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 7520 dev_priv->lvds_downclock,
7521 refclk, &clock,
7522 &reduced_clock);
7523 }
7524 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7525 crtc_state->dpll.n = clock.n;
7526 crtc_state->dpll.m1 = clock.m1;
7527 crtc_state->dpll.m2 = clock.m2;
7528 crtc_state->dpll.p1 = clock.p1;
7529 crtc_state->dpll.p2 = clock.p2;
f47709a9 7530 }
7026d4ac 7531
e9fd1c02 7532 if (IS_GEN2(dev)) {
190f68c5 7533 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 7534 has_reduced_clock ? &reduced_clock : NULL,
7535 num_connectors);
9d556c99 7536 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 7537 chv_update_pll(crtc, crtc_state);
e9fd1c02 7538 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 7539 vlv_update_pll(crtc, crtc_state);
e9fd1c02 7540 } else {
190f68c5 7541 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 7542 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 7543 num_connectors);
e9fd1c02 7544 }
79e53945 7545
c8f7a0db 7546 return 0;
f564048e
EA		 7547}
7548
2fa2fe9a 7549static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7550 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7551{
7552 struct drm_device *dev = crtc->base.dev;
7553 struct drm_i915_private *dev_priv = dev->dev_private;
7554 uint32_t tmp;
7555
dc9e7dec
VS		 7556 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7557 return;
7558
2fa2fe9a 7559 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7560 if (!(tmp & PFIT_ENABLE))
7561 return;
2fa2fe9a 7562
06922821 7563 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7564 if (INTEL_INFO(dev)->gen < 4) {
7565 if (crtc->pipe != PIPE_B)
7566 return;
2fa2fe9a
DV		 7567 } else {
7568 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7569 return;
7570 }
7571
06922821 7572 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7573 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7574 if (INTEL_INFO(dev)->gen < 5)
7575 pipe_config->gmch_pfit.lvds_border_bits =
7576 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7577}
7578
acbec814 7579static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7580 struct intel_crtc_state *pipe_config)
acbec814
JB		 7581{
7582 struct drm_device *dev = crtc->base.dev;
7583 struct drm_i915_private *dev_priv = dev->dev_private;
7584 int pipe = pipe_config->cpu_transcoder;
7585 intel_clock_t clock;
7586 u32 mdiv;
662c6ecb 7587 int refclk = 100000;
acbec814 7588
f573de5a
SK		 7589 /* In case of MIPI DPLL will not even be used */
7590 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7591 return;
7592
acbec814 7593 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 7594 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
acbec814
JB		 7595 mutex_unlock(&dev_priv->dpio_lock);
7596
7597 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7598 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7599 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7600 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7601 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7602
f646628b 7603 vlv_clock(refclk, &clock);
acbec814 7604
f646628b
VS		 7605 /* clock.dot is the fast clock */
7606 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 7607}
7608
5724dbd1
DL		 7609static void
7610i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7611 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7612{
7613 struct drm_device *dev = crtc->base.dev;
7614 struct drm_i915_private *dev_priv = dev->dev_private;
7615 u32 val, base, offset;
7616 int pipe = crtc->pipe, plane = crtc->plane;
7617 int fourcc, pixel_format;
6761dd31 7618 unsigned int aligned_height;
b113d5ee 7619 struct drm_framebuffer *fb;
1b842c89 7620 struct intel_framebuffer *intel_fb;
1ad292b5 7621
42a7b088
DL		 7622 val = I915_READ(DSPCNTR(plane));
7623 if (!(val & DISPLAY_PLANE_ENABLE))
7624 return;
7625
d9806c9f 7626 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7627 if (!intel_fb) {
1ad292b5
JB		 7628 DRM_DEBUG_KMS("failed to alloc fb\n");
7629 return;
7630 }
7631
1b842c89
DL		 7632 fb = &intel_fb->base;
7633
18c5247e
DV		 7634 if (INTEL_INFO(dev)->gen >= 4) {
7635 if (val & DISPPLANE_TILED) {
49af449b 7636 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7637 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7638 }
7639 }
1ad292b5
JB		 7640
7641 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7642 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7643 fb->pixel_format = fourcc;
7644 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7645
7646 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7647 if (plane_config->tiling)
1ad292b5
JB		 7648 offset = I915_READ(DSPTILEOFF(plane));
7649 else
7650 offset = I915_READ(DSPLINOFF(plane));
7651 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7652 } else {
7653 base = I915_READ(DSPADDR(plane));
7654 }
7655 plane_config->base = base;
7656
7657 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7658 fb->width = ((val >> 16) & 0xfff) + 1;
7659 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7660
7661 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7662 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7663
b113d5ee 7664 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7665 fb->pixel_format,
7666 fb->modifier[0]);
1ad292b5 7667
f37b5c2b 7668 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7669
2844a921
DL		 7670 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7671 pipe_name(pipe), plane, fb->width, fb->height,
7672 fb->bits_per_pixel, base, fb->pitches[0],
7673 plane_config->size);
1ad292b5 7674
2d14030b 7675 plane_config->fb = intel_fb;
1ad292b5
JB		 7676}
7677
70b23a98 7678static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7679 struct intel_crtc_state *pipe_config)
70b23a98
VS		 7680{
7681 struct drm_device *dev = crtc->base.dev;
7682 struct drm_i915_private *dev_priv = dev->dev_private;
7683 int pipe = pipe_config->cpu_transcoder;
7684 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7685 intel_clock_t clock;
7686 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7687 int refclk = 100000;
7688
7689 mutex_lock(&dev_priv->dpio_lock);
7690 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7691 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7692 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7693 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7694 mutex_unlock(&dev_priv->dpio_lock);
7695
7696 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7697 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7698 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7699 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7700 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7701
7702 chv_clock(refclk, &clock);
7703
7704 /* clock.dot is the fast clock */
7705 pipe_config->port_clock = clock.dot / 5;
7706}
7707
0e8ffe1b 7708static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 7709 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 7710{
7711 struct drm_device *dev = crtc->base.dev;
7712 struct drm_i915_private *dev_priv = dev->dev_private;
7713 uint32_t tmp;
7714
f458ebbc
DV		 7715 if (!intel_display_power_is_enabled(dev_priv,
7716 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 7717 return false;
7718
e143a21c 7719 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 7720 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 7721
0e8ffe1b
DV		 7722 tmp = I915_READ(PIPECONF(crtc->pipe));
7723 if (!(tmp & PIPECONF_ENABLE))
7724 return false;
7725
42571aef
VS		 7726 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7727 switch (tmp & PIPECONF_BPC_MASK) {
7728 case PIPECONF_6BPC:
7729 pipe_config->pipe_bpp = 18;
7730 break;
7731 case PIPECONF_8BPC:
7732 pipe_config->pipe_bpp = 24;
7733 break;
7734 case PIPECONF_10BPC:
7735 pipe_config->pipe_bpp = 30;
7736 break;
7737 default:
7738 break;
7739 }
7740 }
7741
b5a9fa09
DV		 7742 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7743 pipe_config->limited_color_range = true;
7744
282740f7
VS		 7745 if (INTEL_INFO(dev)->gen < 4)
7746 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7747
1bd1bd80
DV		 7748 intel_get_pipe_timings(crtc, pipe_config);
7749
2fa2fe9a
DV		 7750 i9xx_get_pfit_config(crtc, pipe_config);
7751
6c49f241
DV		 7752 if (INTEL_INFO(dev)->gen >= 4) {
7753 tmp = I915_READ(DPLL_MD(crtc->pipe));
7754 pipe_config->pixel_multiplier =
7755 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7756 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 7757 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 7758 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7759 tmp = I915_READ(DPLL(crtc->pipe));
7760 pipe_config->pixel_multiplier =
7761 ((tmp & SDVO_MULTIPLIER_MASK)
7762 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7763 } else {
7764 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7765 * port and will be fixed up in the encoder->get_config
7766 * function. */
7767 pipe_config->pixel_multiplier = 1;
7768 }
8bcc2795
DV		 7769 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7770 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 7771 /*
7772 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7773 * on 830. Filter it out here so that we don't
7774 * report errors due to that.
7775 */
7776 if (IS_I830(dev))
7777 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7778
8bcc2795
DV		 7779 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7780 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 7781 } else {
7782 /* Mask out read-only status bits. */
7783 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7784 DPLL_PORTC_READY_MASK |
7785 DPLL_PORTB_READY_MASK);
8bcc2795 7786 }
6c49f241 7787
70b23a98
VS		 7788 if (IS_CHERRYVIEW(dev))
7789 chv_crtc_clock_get(crtc, pipe_config);
7790 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 7791 vlv_crtc_clock_get(crtc, pipe_config);
7792 else
7793 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 7794
0e8ffe1b
DV		 7795 return true;
7796}
7797
dde86e2d 7798static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 7799{
7800 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 7801 struct intel_encoder *encoder;
74cfd7ac 7802 u32 val, final;
13d83a67 7803 bool has_lvds = false;
199e5d79 7804 bool has_cpu_edp = false;
199e5d79 7805 bool has_panel = false;
99eb6a01
KP		 7806 bool has_ck505 = false;
7807 bool can_ssc = false;
13d83a67
JB		 7808
7809 /* We need to take the global config into account */
b2784e15 7810 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 7811 switch (encoder->type) {
7812 case INTEL_OUTPUT_LVDS:
7813 has_panel = true;
7814 has_lvds = true;
7815 break;
7816 case INTEL_OUTPUT_EDP:
7817 has_panel = true;
2de6905f 7818 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 7819 has_cpu_edp = true;
7820 break;
6847d71b
PZ		 7821 default:
7822 break;
13d83a67
JB		 7823 }
7824 }
7825
99eb6a01 7826 if (HAS_PCH_IBX(dev)) {
41aa3448 7827 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 7828 can_ssc = has_ck505;
7829 } else {
7830 has_ck505 = false;
7831 can_ssc = true;
7832 }
7833
2de6905f
ID		 7834 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7835 has_panel, has_lvds, has_ck505);
13d83a67
JB		 7836
7837 /* Ironlake: try to setup display ref clock before DPLL
7838 * enabling. This is only under driver's control after
7839 * PCH B stepping, previous chipset stepping should be
7840 * ignoring this setting.
7841 */
74cfd7ac
CW		 7842 val = I915_READ(PCH_DREF_CONTROL);
7843
7844 /* As we must carefully and slowly disable/enable each source in turn,
7845 * compute the final state we want first and check if we need to
7846 * make any changes at all.
7847 */
7848 final = val;
7849 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7850 if (has_ck505)
7851 final |= DREF_NONSPREAD_CK505_ENABLE;
7852 else
7853 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7854
7855 final &= ~DREF_SSC_SOURCE_MASK;
7856 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7857 final &= ~DREF_SSC1_ENABLE;
7858
7859 if (has_panel) {
7860 final |= DREF_SSC_SOURCE_ENABLE;
7861
7862 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7863 final |= DREF_SSC1_ENABLE;
7864
7865 if (has_cpu_edp) {
7866 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7867 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7868 else
7869 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7870 } else
7871 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7872 } else {
7873 final |= DREF_SSC_SOURCE_DISABLE;
7874 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7875 }
7876
7877 if (final == val)
7878 return;
7879
13d83a67 7880 /* Always enable nonspread source */
74cfd7ac 7881 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 7882
99eb6a01 7883 if (has_ck505)
74cfd7ac 7884 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 7885 else
74cfd7ac 7886 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 7887
199e5d79 7888 if (has_panel) {
74cfd7ac
CW		 7889 val &= ~DREF_SSC_SOURCE_MASK;
7890 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 7891
199e5d79 7892 /* SSC must be turned on before enabling the CPU output */
99eb6a01 7893 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7894 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 7895 val |= DREF_SSC1_ENABLE;
e77166b5 7896 } else
74cfd7ac 7897 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 7898
7899 /* Get SSC going before enabling the outputs */
74cfd7ac 7900 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7901 POSTING_READ(PCH_DREF_CONTROL);
7902 udelay(200);
7903
74cfd7ac 7904 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 7905
7906 /* Enable CPU source on CPU attached eDP */
199e5d79 7907 if (has_cpu_edp) {
99eb6a01 7908 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7909 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 7910 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 7911 } else
74cfd7ac 7912 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 7913 } else
74cfd7ac 7914 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7915
74cfd7ac 7916 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7917 POSTING_READ(PCH_DREF_CONTROL);
7918 udelay(200);
7919 } else {
7920 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7921
74cfd7ac 7922 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 7923
7924 /* Turn off CPU output */
74cfd7ac 7925 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7926
74cfd7ac 7927 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7928 POSTING_READ(PCH_DREF_CONTROL);
7929 udelay(200);
7930
7931 /* Turn off the SSC source */
74cfd7ac
CW		 7932 val &= ~DREF_SSC_SOURCE_MASK;
7933 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 7934
7935 /* Turn off SSC1 */
74cfd7ac 7936 val &= ~DREF_SSC1_ENABLE;
199e5d79 7937
74cfd7ac 7938 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 7939 POSTING_READ(PCH_DREF_CONTROL);
7940 udelay(200);
7941 }
74cfd7ac
CW		 7942
7943 BUG_ON(val != final);
13d83a67
JB		 7944}
7945
f31f2d55 7946static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 7947{
f31f2d55 7948 uint32_t tmp;
dde86e2d 7949
0ff066a9
PZ		 7950 tmp = I915_READ(SOUTH_CHICKEN2);
7951 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7952 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7953
0ff066a9
PZ		 7954 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7955 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7956 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 7957
0ff066a9
PZ		 7958 tmp = I915_READ(SOUTH_CHICKEN2);
7959 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7960 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7961
0ff066a9
PZ		 7962 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7963 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7964 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 7965}
7966
7967/* WaMPhyProgramming:hsw */
7968static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7969{
7970 uint32_t tmp;
dde86e2d
PZ		 7971
7972 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7973 tmp &= ~(0xFF << 24);
7974 tmp |= (0x12 << 24);
7975 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7976
dde86e2d
PZ		 7977 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7978 tmp |= (1 << 11);
7979 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7980
7981 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7982 tmp |= (1 << 11);
7983 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7984
dde86e2d
PZ		 7985 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7986 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7987 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7988
7989 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7990 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7991 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7992
0ff066a9
PZ		 7993 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7994 tmp &= ~(7 << 13);
7995 tmp |= (5 << 13);
7996 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 7997
0ff066a9
PZ		 7998 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7999 tmp &= ~(7 << 13);
8000 tmp |= (5 << 13);
8001 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8002
8003 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8004 tmp &= ~0xFF;
8005 tmp |= 0x1C;
8006 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8007
8008 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8009 tmp &= ~0xFF;
8010 tmp |= 0x1C;
8011 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8012
8013 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8014 tmp &= ~(0xFF << 16);
8015 tmp |= (0x1C << 16);
8016 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8017
8018 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8019 tmp &= ~(0xFF << 16);
8020 tmp |= (0x1C << 16);
8021 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8022
0ff066a9
PZ		 8023 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8024 tmp |= (1 << 27);
8025 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8026
0ff066a9
PZ		 8027 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8028 tmp |= (1 << 27);
8029 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8030
0ff066a9
PZ		 8031 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8032 tmp &= ~(0xF << 28);
8033 tmp |= (4 << 28);
8034 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8035
0ff066a9
PZ		 8036 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8037 tmp &= ~(0xF << 28);
8038 tmp |= (4 << 28);
8039 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8040}
8041
2fa86a1f
PZ		 8042/* Implements 3 different sequences from BSpec chapter "Display iCLK
8043 * Programming" based on the parameters passed:
8044 * - Sequence to enable CLKOUT_DP
8045 * - Sequence to enable CLKOUT_DP without spread
8046 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8047 */
8048static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8049 bool with_fdi)
f31f2d55
PZ		 8050{
8051 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8052 uint32_t reg, tmp;
8053
8054 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8055 with_spread = true;
8056 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8057 with_fdi, "LP PCH doesn't have FDI\n"))
8058 with_fdi = false;
f31f2d55
PZ		 8059
8060 mutex_lock(&dev_priv->dpio_lock);
8061
8062 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8063 tmp &= ~SBI_SSCCTL_DISABLE;
8064 tmp |= SBI_SSCCTL_PATHALT;
8065 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8066
8067 udelay(24);
8068
2fa86a1f
PZ		 8069 if (with_spread) {
8070 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8071 tmp &= ~SBI_SSCCTL_PATHALT;
8072 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8073
2fa86a1f
PZ		 8074 if (with_fdi) {
8075 lpt_reset_fdi_mphy(dev_priv);
8076 lpt_program_fdi_mphy(dev_priv);
8077 }
8078 }
dde86e2d 8079
2fa86a1f
PZ		 8080 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8081 SBI_GEN0 : SBI_DBUFF0;
8082 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8083 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8084 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 8085
8086 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 8087}
8088
47701c3b
PZ		 8089/* Sequence to disable CLKOUT_DP */
8090static void lpt_disable_clkout_dp(struct drm_device *dev)
8091{
8092 struct drm_i915_private *dev_priv = dev->dev_private;
8093 uint32_t reg, tmp;
8094
8095 mutex_lock(&dev_priv->dpio_lock);
8096
8097 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8098 SBI_GEN0 : SBI_DBUFF0;
8099 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8100 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8101 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8102
8103 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8104 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8105 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8106 tmp |= SBI_SSCCTL_PATHALT;
8107 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8108 udelay(32);
8109 }
8110 tmp |= SBI_SSCCTL_DISABLE;
8111 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8112 }
8113
8114 mutex_unlock(&dev_priv->dpio_lock);
8115}
8116
bf8fa3d3
PZ		 8117static void lpt_init_pch_refclk(struct drm_device *dev)
8118{
bf8fa3d3
PZ		 8119 struct intel_encoder *encoder;
8120 bool has_vga = false;
8121
b2784e15 8122 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8123 switch (encoder->type) {
8124 case INTEL_OUTPUT_ANALOG:
8125 has_vga = true;
8126 break;
6847d71b
PZ		 8127 default:
8128 break;
bf8fa3d3
PZ		 8129 }
8130 }
8131
47701c3b
PZ		 8132 if (has_vga)
8133 lpt_enable_clkout_dp(dev, true, true);
8134 else
8135 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8136}
8137
dde86e2d
PZ		 8138/*
8139 * Initialize reference clocks when the driver loads
8140 */
8141void intel_init_pch_refclk(struct drm_device *dev)
8142{
8143 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8144 ironlake_init_pch_refclk(dev);
8145 else if (HAS_PCH_LPT(dev))
8146 lpt_init_pch_refclk(dev);
8147}
8148
55bb9992 8149static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8150{
55bb9992 8151 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8152 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8153 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8154 struct drm_connector *connector;
55bb9992 8155 struct drm_connector_state *connector_state;
d9d444cb 8156 struct intel_encoder *encoder;
55bb9992 8157 int num_connectors = 0, i;
d9d444cb
JB		 8158 bool is_lvds = false;
8159
da3ced29 8160 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8161 if (connector_state->crtc != crtc_state->base.crtc)
8162 continue;
8163
8164 encoder = to_intel_encoder(connector_state->best_encoder);
8165
d9d444cb
JB		 8166 switch (encoder->type) {
8167 case INTEL_OUTPUT_LVDS:
8168 is_lvds = true;
8169 break;
6847d71b
PZ		 8170 default:
8171 break;
d9d444cb
JB		 8172 }
8173 num_connectors++;
8174 }
8175
8176 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8177 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8178 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8179 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8180 }
8181
8182 return 120000;
8183}
8184
6ff93609 8185static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8186{
c8203565 8187 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8189 int pipe = intel_crtc->pipe;
c8203565
PZ		 8190 uint32_t val;
8191
78114071 8192 val = 0;
c8203565 8193
6e3c9717 8194 switch (intel_crtc->config->pipe_bpp) {
c8203565 8195 case 18:
dfd07d72 8196 val |= PIPECONF_6BPC;
c8203565
PZ		 8197 break;
8198 case 24:
dfd07d72 8199 val |= PIPECONF_8BPC;
c8203565
PZ		 8200 break;
8201 case 30:
dfd07d72 8202 val |= PIPECONF_10BPC;
c8203565
PZ		 8203 break;
8204 case 36:
dfd07d72 8205 val |= PIPECONF_12BPC;
c8203565
PZ		 8206 break;
8207 default:
cc769b62
PZ		 8208 /* Case prevented by intel_choose_pipe_bpp_dither. */
8209 BUG();
c8203565
PZ		 8210 }
8211
6e3c9717 8212 if (intel_crtc->config->dither)
c8203565
PZ		 8213 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8214
6e3c9717 8215 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8216 val |= PIPECONF_INTERLACED_ILK;
8217 else
8218 val |= PIPECONF_PROGRESSIVE;
8219
6e3c9717 8220 if (intel_crtc->config->limited_color_range)
3685a8f3 8221 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8222
c8203565
PZ		 8223 I915_WRITE(PIPECONF(pipe), val);
8224 POSTING_READ(PIPECONF(pipe));
8225}
8226
86d3efce
VS		 8227/*
8228 * Set up the pipe CSC unit.
8229 *
8230 * Currently only full range RGB to limited range RGB conversion
8231 * is supported, but eventually this should handle various
8232 * RGB<->YCbCr scenarios as well.
8233 */
50f3b016 8234static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8235{
8236 struct drm_device *dev = crtc->dev;
8237 struct drm_i915_private *dev_priv = dev->dev_private;
8238 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8239 int pipe = intel_crtc->pipe;
8240 uint16_t coeff = 0x7800; /* 1.0 */
8241
8242 /*
8243 * TODO: Check what kind of values actually come out of the pipe
8244 * with these coeff/postoff values and adjust to get the best
8245 * accuracy. Perhaps we even need to take the bpc value into
8246 * consideration.
8247 */
8248
6e3c9717 8249 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8250 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8251
8252 /*
8253 * GY/GU and RY/RU should be the other way around according
8254 * to BSpec, but reality doesn't agree. Just set them up in
8255 * a way that results in the correct picture.
8256 */
8257 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8258 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8259
8260 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8261 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8262
8263 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8264 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8265
8266 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8267 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8268 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8269
8270 if (INTEL_INFO(dev)->gen > 6) {
8271 uint16_t postoff = 0;
8272
6e3c9717 8273 if (intel_crtc->config->limited_color_range)
32cf0cb0 8274 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8275
8276 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8277 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8278 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8279
8280 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8281 } else {
8282 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8283
6e3c9717 8284 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8285 mode |= CSC_BLACK_SCREEN_OFFSET;
8286
8287 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8288 }
8289}
8290
6ff93609 8291static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8292{
756f85cf
PZ		 8293 struct drm_device *dev = crtc->dev;
8294 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8295 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8296 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8297 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8298 uint32_t val;
8299
3eff4faa 8300 val = 0;
ee2b0b38 8301
6e3c9717 8302 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8303 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8304
6e3c9717 8305 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8306 val |= PIPECONF_INTERLACED_ILK;
8307 else
8308 val |= PIPECONF_PROGRESSIVE;
8309
702e7a56
PZ		 8310 I915_WRITE(PIPECONF(cpu_transcoder), val);
8311 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8312
8313 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8314 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8315
3cdf122c 8316 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8317 val = 0;
8318
6e3c9717 8319 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8320 case 18:
8321 val |= PIPEMISC_DITHER_6_BPC;
8322 break;
8323 case 24:
8324 val |= PIPEMISC_DITHER_8_BPC;
8325 break;
8326 case 30:
8327 val |= PIPEMISC_DITHER_10_BPC;
8328 break;
8329 case 36:
8330 val |= PIPEMISC_DITHER_12_BPC;
8331 break;
8332 default:
8333 /* Case prevented by pipe_config_set_bpp. */
8334 BUG();
8335 }
8336
6e3c9717 8337 if (intel_crtc->config->dither)
756f85cf
PZ		 8338 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8339
8340 I915_WRITE(PIPEMISC(pipe), val);
8341 }
ee2b0b38
PZ		 8342}
8343
6591c6e4 8344static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8345 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8346 intel_clock_t *clock,
8347 bool *has_reduced_clock,
8348 intel_clock_t *reduced_clock)
8349{
8350 struct drm_device *dev = crtc->dev;
8351 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8352 int refclk;
d4906093 8353 const intel_limit_t *limit;
a16af721 8354 bool ret, is_lvds = false;
79e53945 8355
a93e255f 8356 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 8357
55bb9992 8358 refclk = ironlake_get_refclk(crtc_state);
79e53945 8359
d4906093
ML		 8360 /*
8361 * Returns a set of divisors for the desired target clock with the given
8362 * refclk, or FALSE. The returned values represent the clock equation:
8363 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8364 */
a93e255f
ACO		 8365 limit = intel_limit(crtc_state, refclk);
8366 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8367 crtc_state->port_clock,
ee9300bb 8368 refclk, NULL, clock);
6591c6e4
PZ		 8369 if (!ret)
8370 return false;
cda4b7d3 8371
ddc9003c 8372 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 8373 /*
8374 * Ensure we match the reduced clock's P to the target clock.
8375 * If the clocks don't match, we can't switch the display clock
8376 * by using the FP0/FP1. In such case we will disable the LVDS
8377 * downclock feature.
8378 */
ee9300bb 8379 *has_reduced_clock =
a93e255f 8380 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV		 8381 dev_priv->lvds_downclock,
8382 refclk, clock,
8383 reduced_clock);
652c393a 8384 }
61e9653f 8385
6591c6e4
PZ		 8386 return true;
8387}
8388
d4b1931c
PZ		 8389int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8390{
8391 /*
8392 * Account for spread spectrum to avoid
8393 * oversubscribing the link. Max center spread
8394 * is 2.5%; use 5% for safety's sake.
8395 */
8396 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8397 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8398}
8399
7429e9d4 8400static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8401{
7429e9d4 8402 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8403}
8404
de13a2e3 8405static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8406 struct intel_crtc_state *crtc_state,
7429e9d4 8407 u32 *fp,
9a7c7890 8408 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8409{
de13a2e3 8410 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8411 struct drm_device *dev = crtc->dev;
8412 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8413 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8414 struct drm_connector *connector;
55bb9992
ACO		 8415 struct drm_connector_state *connector_state;
8416 struct intel_encoder *encoder;
de13a2e3 8417 uint32_t dpll;
55bb9992 8418 int factor, num_connectors = 0, i;
09ede541 8419 bool is_lvds = false, is_sdvo = false;
79e53945 8420
da3ced29 8421 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8422 if (connector_state->crtc != crtc_state->base.crtc)
8423 continue;
8424
8425 encoder = to_intel_encoder(connector_state->best_encoder);
8426
8427 switch (encoder->type) {
79e53945
JB		 8428 case INTEL_OUTPUT_LVDS:
8429 is_lvds = true;
8430 break;
8431 case INTEL_OUTPUT_SDVO:
7d57382e 8432 case INTEL_OUTPUT_HDMI:
79e53945 8433 is_sdvo = true;
79e53945 8434 break;
6847d71b
PZ		 8435 default:
8436 break;
79e53945 8437 }
43565a06 8438
c751ce4f 8439 num_connectors++;
79e53945 8440 }
79e53945 8441
c1858123 8442 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8443 factor = 21;
8444 if (is_lvds) {
8445 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8446 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8447 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8448 factor = 25;
190f68c5 8449 } else if (crtc_state->sdvo_tv_clock)
8febb297 8450 factor = 20;
c1858123 8451
190f68c5 8452 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8453 *fp |= FP_CB_TUNE;
2c07245f 8454
9a7c7890
DV		 8455 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8456 *fp2 |= FP_CB_TUNE;
8457
5eddb70b 8458 dpll = 0;
2c07245f 8459
a07d6787
EA		 8460 if (is_lvds)
8461 dpll |= DPLLB_MODE_LVDS;
8462 else
8463 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8464
190f68c5 8465 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8466 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8467
8468 if (is_sdvo)
4a33e48d 8469 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8470 if (crtc_state->has_dp_encoder)
4a33e48d 8471 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8472
a07d6787 8473 /* compute bitmask from p1 value */
190f68c5 8474 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8475 /* also FPA1 */
190f68c5 8476 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8477
190f68c5 8478 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8479 case 5:
8480 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8481 break;
8482 case 7:
8483 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8484 break;
8485 case 10:
8486 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8487 break;
8488 case 14:
8489 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8490 break;
79e53945
JB		 8491 }
8492
b4c09f3b 8493 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8494 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8495 else
8496 dpll |= PLL_REF_INPUT_DREFCLK;
8497
959e16d6 8498 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8499}
8500
190f68c5
ACO		 8501static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8502 struct intel_crtc_state *crtc_state)
de13a2e3 8503{
c7653199 8504 struct drm_device *dev = crtc->base.dev;
de13a2e3 8505 intel_clock_t clock, reduced_clock;
cbbab5bd 8506 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8507 bool ok, has_reduced_clock = false;
8b47047b 8508 bool is_lvds = false;
e2b78267 8509 struct intel_shared_dpll *pll;
de13a2e3 8510
dd3cd74a
ACO		 8511 memset(&crtc_state->dpll_hw_state, 0,
8512 sizeof(crtc_state->dpll_hw_state));
8513
409ee761 8514 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8515
5dc5298b
PZ		 8516 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8517 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8518
190f68c5 8519 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8520 &has_reduced_clock, &reduced_clock);
190f68c5 8521 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8522 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8523 return -EINVAL;
79e53945 8524 }
f47709a9 8525 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8526 if (!crtc_state->clock_set) {
8527 crtc_state->dpll.n = clock.n;
8528 crtc_state->dpll.m1 = clock.m1;
8529 crtc_state->dpll.m2 = clock.m2;
8530 crtc_state->dpll.p1 = clock.p1;
8531 crtc_state->dpll.p2 = clock.p2;
f47709a9 8532 }
79e53945 8533
5dc5298b 8534 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8535 if (crtc_state->has_pch_encoder) {
8536 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8537 if (has_reduced_clock)
7429e9d4 8538 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8539
190f68c5 8540 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8541 &fp, &reduced_clock,
8542 has_reduced_clock ? &fp2 : NULL);
8543
190f68c5
ACO		 8544 crtc_state->dpll_hw_state.dpll = dpll;
8545 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8546 if (has_reduced_clock)
190f68c5 8547 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8548 else
190f68c5 8549 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8550
190f68c5 8551 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8552 if (pll == NULL) {
84f44ce7 8553 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8554 pipe_name(crtc->pipe));
4b645f14
JB		 8555 return -EINVAL;
8556 }
3fb37703 8557 }
79e53945 8558
ab585dea 8559 if (is_lvds && has_reduced_clock)
c7653199 8560 crtc->lowfreq_avail = true;
bcd644e0 8561 else
c7653199 8562 crtc->lowfreq_avail = false;
e2b78267 8563
c8f7a0db 8564 return 0;
79e53945
JB		 8565}
8566
eb14cb74
VS		 8567static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8568 struct intel_link_m_n *m_n)
8569{
8570 struct drm_device *dev = crtc->base.dev;
8571 struct drm_i915_private *dev_priv = dev->dev_private;
8572 enum pipe pipe = crtc->pipe;
8573
8574 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8575 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8576 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8577 & ~TU_SIZE_MASK;
8578 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8579 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8580 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8581}
8582
8583static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8584 enum transcoder transcoder,
b95af8be
VK		 8585 struct intel_link_m_n *m_n,
8586 struct intel_link_m_n *m2_n2)
72419203
DV		 8587{
8588 struct drm_device *dev = crtc->base.dev;
8589 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8590 enum pipe pipe = crtc->pipe;
72419203 8591
eb14cb74
VS		 8592 if (INTEL_INFO(dev)->gen >= 5) {
8593 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8594 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8595 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8596 & ~TU_SIZE_MASK;
8597 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8598 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8599 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8600 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8601 * gen < 8) and if DRRS is supported (to make sure the
8602 * registers are not unnecessarily read).
8603 */
8604 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8605 crtc->config->has_drrs) {
b95af8be
VK		 8606 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8607 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8608 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8609 & ~TU_SIZE_MASK;
8610 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8611 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8612 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8613 }
eb14cb74
VS		 8614 } else {
8615 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8616 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8617 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8618 & ~TU_SIZE_MASK;
8619 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8620 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8621 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8622 }
8623}
8624
8625void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8626 struct intel_crtc_state *pipe_config)
eb14cb74 8627{
681a8504 8628 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8629 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8630 else
8631 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8632 &pipe_config->dp_m_n,
8633 &pipe_config->dp_m2_n2);
eb14cb74 8634}
72419203 8635
eb14cb74 8636static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8637 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8638{
8639 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8640 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8641}
8642
bd2e244f 8643static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8644 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8645{
8646 struct drm_device *dev = crtc->base.dev;
8647 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8648 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8649 uint32_t ps_ctrl = 0;
8650 int id = -1;
8651 int i;
bd2e244f 8652
a1b2278e
CK		 8653 /* find scaler attached to this pipe */
8654 for (i = 0; i < crtc->num_scalers; i++) {
8655 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8656 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8657 id = i;
8658 pipe_config->pch_pfit.enabled = true;
8659 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8660 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8661 break;
8662 }
8663 }
bd2e244f 8664
a1b2278e
CK		 8665 scaler_state->scaler_id = id;
8666 if (id >= 0) {
8667 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8668 } else {
8669 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8670 }
8671}
8672
5724dbd1
DL		 8673static void
8674skylake_get_initial_plane_config(struct intel_crtc *crtc,
8675 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8676{
8677 struct drm_device *dev = crtc->base.dev;
8678 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8679 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8680 int pipe = crtc->pipe;
8681 int fourcc, pixel_format;
6761dd31 8682 unsigned int aligned_height;
bc8d7dff 8683 struct drm_framebuffer *fb;
1b842c89 8684 struct intel_framebuffer *intel_fb;
bc8d7dff 8685
d9806c9f 8686 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8687 if (!intel_fb) {
bc8d7dff
DL		 8688 DRM_DEBUG_KMS("failed to alloc fb\n");
8689 return;
8690 }
8691
1b842c89
DL		 8692 fb = &intel_fb->base;
8693
bc8d7dff 8694 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 8695 if (!(val & PLANE_CTL_ENABLE))
8696 goto error;
8697
bc8d7dff
DL		 8698 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8699 fourcc = skl_format_to_fourcc(pixel_format,
8700 val & PLANE_CTL_ORDER_RGBX,
8701 val & PLANE_CTL_ALPHA_MASK);
8702 fb->pixel_format = fourcc;
8703 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8704
40f46283
DL		 8705 tiling = val & PLANE_CTL_TILED_MASK;
8706 switch (tiling) {
8707 case PLANE_CTL_TILED_LINEAR:
8708 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8709 break;
8710 case PLANE_CTL_TILED_X:
8711 plane_config->tiling = I915_TILING_X;
8712 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8713 break;
8714 case PLANE_CTL_TILED_Y:
8715 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8716 break;
8717 case PLANE_CTL_TILED_YF:
8718 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8719 break;
8720 default:
8721 MISSING_CASE(tiling);
8722 goto error;
8723 }
8724
bc8d7dff
DL		 8725 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8726 plane_config->base = base;
8727
8728 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8729
8730 val = I915_READ(PLANE_SIZE(pipe, 0));
8731 fb->height = ((val >> 16) & 0xfff) + 1;
8732 fb->width = ((val >> 0) & 0x1fff) + 1;
8733
8734 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 8735 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8736 fb->pixel_format);
bc8d7dff
DL		 8737 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8738
8739 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8740 fb->pixel_format,
8741 fb->modifier[0]);
bc8d7dff 8742
f37b5c2b 8743 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 8744
8745 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8746 pipe_name(pipe), fb->width, fb->height,
8747 fb->bits_per_pixel, base, fb->pitches[0],
8748 plane_config->size);
8749
2d14030b 8750 plane_config->fb = intel_fb;
bc8d7dff
DL		 8751 return;
8752
8753error:
8754 kfree(fb);
8755}
8756
2fa2fe9a 8757static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8758 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 8759{
8760 struct drm_device *dev = crtc->base.dev;
8761 struct drm_i915_private *dev_priv = dev->dev_private;
8762 uint32_t tmp;
8763
8764 tmp = I915_READ(PF_CTL(crtc->pipe));
8765
8766 if (tmp & PF_ENABLE) {
fd4daa9c 8767 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 8768 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8769 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 8770
8771 /* We currently do not free assignements of panel fitters on
8772 * ivb/hsw (since we don't use the higher upscaling modes which
8773 * differentiates them) so just WARN about this case for now. */
8774 if (IS_GEN7(dev)) {
8775 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8776 PF_PIPE_SEL_IVB(crtc->pipe));
8777 }
2fa2fe9a 8778 }
79e53945
JB		 8779}
8780
5724dbd1
DL		 8781static void
8782ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8783 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 8784{
8785 struct drm_device *dev = crtc->base.dev;
8786 struct drm_i915_private *dev_priv = dev->dev_private;
8787 u32 val, base, offset;
aeee5a49 8788 int pipe = crtc->pipe;
4c6baa59 8789 int fourcc, pixel_format;
6761dd31 8790 unsigned int aligned_height;
b113d5ee 8791 struct drm_framebuffer *fb;
1b842c89 8792 struct intel_framebuffer *intel_fb;
4c6baa59 8793
42a7b088
DL		 8794 val = I915_READ(DSPCNTR(pipe));
8795 if (!(val & DISPLAY_PLANE_ENABLE))
8796 return;
8797
d9806c9f 8798 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8799 if (!intel_fb) {
4c6baa59
JB		 8800 DRM_DEBUG_KMS("failed to alloc fb\n");
8801 return;
8802 }
8803
1b842c89
DL		 8804 fb = &intel_fb->base;
8805
18c5247e
DV		 8806 if (INTEL_INFO(dev)->gen >= 4) {
8807 if (val & DISPPLANE_TILED) {
49af449b 8808 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8809 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8810 }
8811 }
4c6baa59
JB		 8812
8813 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8814 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8815 fb->pixel_format = fourcc;
8816 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 8817
aeee5a49 8818 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 8819 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 8820 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 8821 } else {
49af449b 8822 if (plane_config->tiling)
aeee5a49 8823 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 8824 else
aeee5a49 8825 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 8826 }
8827 plane_config->base = base;
8828
8829 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8830 fb->width = ((val >> 16) & 0xfff) + 1;
8831 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 8832
8833 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8834 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 8835
b113d5ee 8836 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8837 fb->pixel_format,
8838 fb->modifier[0]);
4c6baa59 8839
f37b5c2b 8840 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 8841
2844a921
DL		 8842 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8843 pipe_name(pipe), fb->width, fb->height,
8844 fb->bits_per_pixel, base, fb->pitches[0],
8845 plane_config->size);
b113d5ee 8846
2d14030b 8847 plane_config->fb = intel_fb;
4c6baa59
JB		 8848}
8849
0e8ffe1b 8850static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8851 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8852{
8853 struct drm_device *dev = crtc->base.dev;
8854 struct drm_i915_private *dev_priv = dev->dev_private;
8855 uint32_t tmp;
8856
f458ebbc
DV		 8857 if (!intel_display_power_is_enabled(dev_priv,
8858 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 8859 return false;
8860
e143a21c 8861 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8862 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8863
0e8ffe1b
DV		 8864 tmp = I915_READ(PIPECONF(crtc->pipe));
8865 if (!(tmp & PIPECONF_ENABLE))
8866 return false;
8867
42571aef
VS		 8868 switch (tmp & PIPECONF_BPC_MASK) {
8869 case PIPECONF_6BPC:
8870 pipe_config->pipe_bpp = 18;
8871 break;
8872 case PIPECONF_8BPC:
8873 pipe_config->pipe_bpp = 24;
8874 break;
8875 case PIPECONF_10BPC:
8876 pipe_config->pipe_bpp = 30;
8877 break;
8878 case PIPECONF_12BPC:
8879 pipe_config->pipe_bpp = 36;
8880 break;
8881 default:
8882 break;
8883 }
8884
b5a9fa09
DV		 8885 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8886 pipe_config->limited_color_range = true;
8887
ab9412ba 8888 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 8889 struct intel_shared_dpll *pll;
8890
88adfff1
DV		 8891 pipe_config->has_pch_encoder = true;
8892
627eb5a3
DV		 8893 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8894 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8895 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 8896
8897 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 8898
c0d43d62 8899 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 8900 pipe_config->shared_dpll =
8901 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 8902 } else {
8903 tmp = I915_READ(PCH_DPLL_SEL);
8904 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8905 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8906 else
8907 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8908 }
66e985c0
DV		 8909
8910 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8911
8912 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8913 &pipe_config->dpll_hw_state));
c93f54cf
DV		 8914
8915 tmp = pipe_config->dpll_hw_state.dpll;
8916 pipe_config->pixel_multiplier =
8917 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8918 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 8919
8920 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 8921 } else {
8922 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 8923 }
8924
1bd1bd80
DV		 8925 intel_get_pipe_timings(crtc, pipe_config);
8926
2fa2fe9a
DV		 8927 ironlake_get_pfit_config(crtc, pipe_config);
8928
0e8ffe1b
DV		 8929 return true;
8930}
8931
be256dc7
PZ		 8932static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8933{
8934 struct drm_device *dev = dev_priv->dev;
be256dc7 8935 struct intel_crtc *crtc;
be256dc7 8936
d3fcc808 8937 for_each_intel_crtc(dev, crtc)
e2c719b7 8938 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 8939 pipe_name(crtc->pipe));
8940
e2c719b7
RC		 8941 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8942 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8943 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8944 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8945 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8946 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 8947 "CPU PWM1 enabled\n");
c5107b87 8948 if (IS_HASWELL(dev))
e2c719b7 8949 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 8950 "CPU PWM2 enabled\n");
e2c719b7 8951 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 8952 "PCH PWM1 enabled\n");
e2c719b7 8953 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 8954 "Utility pin enabled\n");
e2c719b7 8955 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 8956
9926ada1
PZ		 8957 /*
8958 * In theory we can still leave IRQs enabled, as long as only the HPD
8959 * interrupts remain enabled. We used to check for that, but since it's
8960 * gen-specific and since we only disable LCPLL after we fully disable
8961 * the interrupts, the check below should be enough.
8962 */
e2c719b7 8963 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 8964}
8965
9ccd5aeb
PZ		 8966static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8967{
8968 struct drm_device *dev = dev_priv->dev;
8969
8970 if (IS_HASWELL(dev))
8971 return I915_READ(D_COMP_HSW);
8972 else
8973 return I915_READ(D_COMP_BDW);
8974}
8975
3c4c9b81
PZ		 8976static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8977{
8978 struct drm_device *dev = dev_priv->dev;
8979
8980 if (IS_HASWELL(dev)) {
8981 mutex_lock(&dev_priv->rps.hw_lock);
8982 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8983 val))
f475dadf 8984 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 8985 mutex_unlock(&dev_priv->rps.hw_lock);
8986 } else {
9ccd5aeb
PZ		 8987 I915_WRITE(D_COMP_BDW, val);
8988 POSTING_READ(D_COMP_BDW);
3c4c9b81 8989 }
be256dc7
PZ		 8990}
8991
8992/*
8993 * This function implements pieces of two sequences from BSpec:
8994 * - Sequence for display software to disable LCPLL
8995 * - Sequence for display software to allow package C8+
8996 * The steps implemented here are just the steps that actually touch the LCPLL
8997 * register. Callers should take care of disabling all the display engine
8998 * functions, doing the mode unset, fixing interrupts, etc.
8999 */
6ff58d53
PZ		 9000static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9001 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9002{
9003 uint32_t val;
9004
9005 assert_can_disable_lcpll(dev_priv);
9006
9007 val = I915_READ(LCPLL_CTL);
9008
9009 if (switch_to_fclk) {
9010 val |= LCPLL_CD_SOURCE_FCLK;
9011 I915_WRITE(LCPLL_CTL, val);
9012
9013 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9014 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9015 DRM_ERROR("Switching to FCLK failed\n");
9016
9017 val = I915_READ(LCPLL_CTL);
9018 }
9019
9020 val |= LCPLL_PLL_DISABLE;
9021 I915_WRITE(LCPLL_CTL, val);
9022 POSTING_READ(LCPLL_CTL);
9023
9024 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9025 DRM_ERROR("LCPLL still locked\n");
9026
9ccd5aeb 9027 val = hsw_read_dcomp(dev_priv);
be256dc7 9028 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9029 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9030 ndelay(100);
9031
9ccd5aeb
PZ		 9032 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9033 1))
be256dc7
PZ		 9034 DRM_ERROR("D_COMP RCOMP still in progress\n");
9035
9036 if (allow_power_down) {
9037 val = I915_READ(LCPLL_CTL);
9038 val |= LCPLL_POWER_DOWN_ALLOW;
9039 I915_WRITE(LCPLL_CTL, val);
9040 POSTING_READ(LCPLL_CTL);
9041 }
9042}
9043
9044/*
9045 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9046 * source.
9047 */
6ff58d53 9048static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9049{
9050 uint32_t val;
9051
9052 val = I915_READ(LCPLL_CTL);
9053
9054 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9055 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9056 return;
9057
a8a8bd54
PZ		 9058 /*
9059 * Make sure we're not on PC8 state before disabling PC8, otherwise
9060 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9061 */
59bad947 9062 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9063
be256dc7
PZ		 9064 if (val & LCPLL_POWER_DOWN_ALLOW) {
9065 val &= ~LCPLL_POWER_DOWN_ALLOW;
9066 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9067 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9068 }
9069
9ccd5aeb 9070 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9071 val |= D_COMP_COMP_FORCE;
9072 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9073 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9074
9075 val = I915_READ(LCPLL_CTL);
9076 val &= ~LCPLL_PLL_DISABLE;
9077 I915_WRITE(LCPLL_CTL, val);
9078
9079 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9080 DRM_ERROR("LCPLL not locked yet\n");
9081
9082 if (val & LCPLL_CD_SOURCE_FCLK) {
9083 val = I915_READ(LCPLL_CTL);
9084 val &= ~LCPLL_CD_SOURCE_FCLK;
9085 I915_WRITE(LCPLL_CTL, val);
9086
9087 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9088 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9089 DRM_ERROR("Switching back to LCPLL failed\n");
9090 }
215733fa 9091
59bad947 9092 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
be256dc7
PZ		 9093}
9094
765dab67
PZ		 9095/*
9096 * Package states C8 and deeper are really deep PC states that can only be
9097 * reached when all the devices on the system allow it, so even if the graphics
9098 * device allows PC8+, it doesn't mean the system will actually get to these
9099 * states. Our driver only allows PC8+ when going into runtime PM.
9100 *
9101 * The requirements for PC8+ are that all the outputs are disabled, the power
9102 * well is disabled and most interrupts are disabled, and these are also
9103 * requirements for runtime PM. When these conditions are met, we manually do
9104 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9105 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9106 * hang the machine.
9107 *
9108 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9109 * the state of some registers, so when we come back from PC8+ we need to
9110 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9111 * need to take care of the registers kept by RC6. Notice that this happens even
9112 * if we don't put the device in PCI D3 state (which is what currently happens
9113 * because of the runtime PM support).
9114 *
9115 * For more, read "Display Sequences for Package C8" on the hardware
9116 * documentation.
9117 */
a14cb6fc 9118void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9119{
c67a470b
PZ		 9120 struct drm_device *dev = dev_priv->dev;
9121 uint32_t val;
9122
c67a470b
PZ		 9123 DRM_DEBUG_KMS("Enabling package C8+\n");
9124
c67a470b
PZ		 9125 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9126 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9127 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9128 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9129 }
9130
9131 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9132 hsw_disable_lcpll(dev_priv, true, true);
9133}
9134
a14cb6fc 9135void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9136{
9137 struct drm_device *dev = dev_priv->dev;
9138 uint32_t val;
9139
c67a470b
PZ		 9140 DRM_DEBUG_KMS("Disabling package C8+\n");
9141
9142 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9143 lpt_init_pch_refclk(dev);
9144
9145 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9146 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9147 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9148 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9149 }
9150
9151 intel_prepare_ddi(dev);
c67a470b
PZ		 9152}
9153
a821fc46 9154static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
f8437dd1 9155{
a821fc46 9156 struct drm_device *dev = old_state->dev;
f8437dd1 9157 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 9158 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
f8437dd1
VK		 9159 int req_cdclk;
9160
9161 /* see the comment in valleyview_modeset_global_resources */
9162 if (WARN_ON(max_pixclk < 0))
9163 return;
9164
9165 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9166
9167 if (req_cdclk != dev_priv->cdclk_freq)
9168 broxton_set_cdclk(dev, req_cdclk);
9169}
9170
190f68c5
ACO		 9171static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9172 struct intel_crtc_state *crtc_state)
09b4ddf9 9173{
190f68c5 9174 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9175 return -EINVAL;
716c2e55 9176
c7653199 9177 crtc->lowfreq_avail = false;
644cef34 9178
c8f7a0db 9179 return 0;
79e53945
JB		 9180}
9181
3760b59c
S		 9182static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9183 enum port port,
9184 struct intel_crtc_state *pipe_config)
9185{
9186 switch (port) {
9187 case PORT_A:
9188 pipe_config->ddi_pll_sel = SKL_DPLL0;
9189 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9190 break;
9191 case PORT_B:
9192 pipe_config->ddi_pll_sel = SKL_DPLL1;
9193 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9194 break;
9195 case PORT_C:
9196 pipe_config->ddi_pll_sel = SKL_DPLL2;
9197 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9198 break;
9199 default:
9200 DRM_ERROR("Incorrect port type\n");
9201 }
9202}
9203
96b7dfb7
S		 9204static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9205 enum port port,
5cec258b 9206 struct intel_crtc_state *pipe_config)
96b7dfb7 9207{
3148ade7 9208 u32 temp, dpll_ctl1;
96b7dfb7
S		 9209
9210 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9211 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9212
9213 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9214 case SKL_DPLL0:
9215 /*
9216 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9217 * of the shared DPLL framework and thus needs to be read out
9218 * separately
9219 */
9220 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9221 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9222 break;
96b7dfb7
S		 9223 case SKL_DPLL1:
9224 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9225 break;
9226 case SKL_DPLL2:
9227 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9228 break;
9229 case SKL_DPLL3:
9230 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9231 break;
96b7dfb7
S		 9232 }
9233}
9234
7d2c8175
DL		 9235static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9236 enum port port,
5cec258b 9237 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9238{
9239 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9240
9241 switch (pipe_config->ddi_pll_sel) {
9242 case PORT_CLK_SEL_WRPLL1:
9243 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9244 break;
9245 case PORT_CLK_SEL_WRPLL2:
9246 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9247 break;
9248 }
9249}
9250
26804afd 9251static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9252 struct intel_crtc_state *pipe_config)
26804afd
DV		 9253{
9254 struct drm_device *dev = crtc->base.dev;
9255 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9256 struct intel_shared_dpll *pll;
26804afd
DV		 9257 enum port port;
9258 uint32_t tmp;
9259
9260 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9261
9262 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9263
96b7dfb7
S		 9264 if (IS_SKYLAKE(dev))
9265 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9266 else if (IS_BROXTON(dev))
9267 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9268 else
9269 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9270
d452c5b6
DV		 9271 if (pipe_config->shared_dpll >= 0) {
9272 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9273
9274 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9275 &pipe_config->dpll_hw_state));
9276 }
9277
26804afd
DV		 9278 /*
9279 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9280 * DDI E. So just check whether this pipe is wired to DDI E and whether
9281 * the PCH transcoder is on.
9282 */
ca370455
DL		 9283 if (INTEL_INFO(dev)->gen < 9 &&
9284 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9285 pipe_config->has_pch_encoder = true;
9286
9287 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9288 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9289 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9290
9291 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9292 }
9293}
9294
0e8ffe1b 9295static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9296 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9297{
9298 struct drm_device *dev = crtc->base.dev;
9299 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9300 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9301 uint32_t tmp;
9302
f458ebbc 9303 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9304 POWER_DOMAIN_PIPE(crtc->pipe)))
9305 return false;
9306
e143a21c 9307 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9308 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9309
eccb140b
DV		 9310 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9311 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9312 enum pipe trans_edp_pipe;
9313 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9314 default:
9315 WARN(1, "unknown pipe linked to edp transcoder\n");
9316 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9317 case TRANS_DDI_EDP_INPUT_A_ON:
9318 trans_edp_pipe = PIPE_A;
9319 break;
9320 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9321 trans_edp_pipe = PIPE_B;
9322 break;
9323 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9324 trans_edp_pipe = PIPE_C;
9325 break;
9326 }
9327
9328 if (trans_edp_pipe == crtc->pipe)
9329 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9330 }
9331
f458ebbc 9332 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9333 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9334 return false;
9335
eccb140b 9336 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9337 if (!(tmp & PIPECONF_ENABLE))
9338 return false;
9339
26804afd 9340 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9341
1bd1bd80
DV		 9342 intel_get_pipe_timings(crtc, pipe_config);
9343
a1b2278e
CK		 9344 if (INTEL_INFO(dev)->gen >= 9) {
9345 skl_init_scalers(dev, crtc, pipe_config);
9346 }
9347
2fa2fe9a 9348 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9349
9350 if (INTEL_INFO(dev)->gen >= 9) {
9351 pipe_config->scaler_state.scaler_id = -1;
9352 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9353 }
9354
bd2e244f 9355 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9356 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9357 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9358 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9359 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9360 else
9361 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9362 }
88adfff1 9363
e59150dc
JB		 9364 if (IS_HASWELL(dev))
9365 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9366 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9367
ebb69c95
CT		 9368 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9369 pipe_config->pixel_multiplier =
9370 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9371 } else {
9372 pipe_config->pixel_multiplier = 1;
9373 }
6c49f241 9374
0e8ffe1b
DV		 9375 return true;
9376}
9377
560b85bb
CW		 9378static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9379{
9380 struct drm_device *dev = crtc->dev;
9381 struct drm_i915_private *dev_priv = dev->dev_private;
9382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9383 uint32_t cntl = 0, size = 0;
560b85bb 9384
dc41c154 9385 if (base) {
3dd512fb
MR		 9386 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9387 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9388 unsigned int stride = roundup_pow_of_two(width) * 4;
9389
9390 switch (stride) {
9391 default:
9392 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9393 width, stride);
9394 stride = 256;
9395 /* fallthrough */
9396 case 256:
9397 case 512:
9398 case 1024:
9399 case 2048:
9400 break;
4b0e333e
CW		 9401 }
9402
dc41c154
VS		 9403 cntl |= CURSOR_ENABLE |
9404 CURSOR_GAMMA_ENABLE |
9405 CURSOR_FORMAT_ARGB |
9406 CURSOR_STRIDE(stride);
9407
9408 size = (height << 12) | width;
4b0e333e 9409 }
560b85bb 9410
dc41c154
VS		 9411 if (intel_crtc->cursor_cntl != 0 &&
9412 (intel_crtc->cursor_base != base ||
9413 intel_crtc->cursor_size != size ||
9414 intel_crtc->cursor_cntl != cntl)) {
9415 /* On these chipsets we can only modify the base/size/stride
9416 * whilst the cursor is disabled.
9417 */
9418 I915_WRITE(_CURACNTR, 0);
4b0e333e 9419 POSTING_READ(_CURACNTR);
dc41c154 9420 intel_crtc->cursor_cntl = 0;
4b0e333e 9421 }
560b85bb 9422
99d1f387 9423 if (intel_crtc->cursor_base != base) {
9db4a9c7 9424 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9425 intel_crtc->cursor_base = base;
9426 }
4726e0b0 9427
dc41c154
VS		 9428 if (intel_crtc->cursor_size != size) {
9429 I915_WRITE(CURSIZE, size);
9430 intel_crtc->cursor_size = size;
4b0e333e 9431 }
560b85bb 9432
4b0e333e 9433 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9434 I915_WRITE(_CURACNTR, cntl);
9435 POSTING_READ(_CURACNTR);
4b0e333e 9436 intel_crtc->cursor_cntl = cntl;
560b85bb 9437 }
560b85bb
CW		 9438}
9439
560b85bb 9440static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9441{
9442 struct drm_device *dev = crtc->dev;
9443 struct drm_i915_private *dev_priv = dev->dev_private;
9444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9445 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9446 uint32_t cntl;
9447
9448 cntl = 0;
9449 if (base) {
9450 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9451 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9452 case 64:
9453 cntl |= CURSOR_MODE_64_ARGB_AX;
9454 break;
9455 case 128:
9456 cntl |= CURSOR_MODE_128_ARGB_AX;
9457 break;
9458 case 256:
9459 cntl |= CURSOR_MODE_256_ARGB_AX;
9460 break;
9461 default:
3dd512fb 9462 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9463 return;
65a21cd6 9464 }
4b0e333e 9465 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9466
9467 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9468 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9469 }
65a21cd6 9470
8e7d688b 9471 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9472 cntl |= CURSOR_ROTATE_180;
9473
4b0e333e
CW		 9474 if (intel_crtc->cursor_cntl != cntl) {
9475 I915_WRITE(CURCNTR(pipe), cntl);
9476 POSTING_READ(CURCNTR(pipe));
9477 intel_crtc->cursor_cntl = cntl;
65a21cd6 9478 }
4b0e333e 9479
65a21cd6 9480 /* and commit changes on next vblank */
5efb3e28
VS		 9481 I915_WRITE(CURBASE(pipe), base);
9482 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9483
9484 intel_crtc->cursor_base = base;
65a21cd6
JB		 9485}
9486
cda4b7d3 9487/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9488static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9489 bool on)
cda4b7d3
CW		 9490{
9491 struct drm_device *dev = crtc->dev;
9492 struct drm_i915_private *dev_priv = dev->dev_private;
9493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9494 int pipe = intel_crtc->pipe;
3d7d6510
MR		 9495 int x = crtc->cursor_x;
9496 int y = crtc->cursor_y;
d6e4db15 9497 u32 base = 0, pos = 0;
cda4b7d3 9498
d6e4db15 9499 if (on)
cda4b7d3 9500 base = intel_crtc->cursor_addr;
cda4b7d3 9501
6e3c9717 9502 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9503 base = 0;
9504
6e3c9717 9505 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9506 base = 0;
9507
9508 if (x < 0) {
3dd512fb 9509 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 9510 base = 0;
9511
9512 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9513 x = -x;
9514 }
9515 pos |= x << CURSOR_X_SHIFT;
9516
9517 if (y < 0) {
3dd512fb 9518 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 9519 base = 0;
9520
9521 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9522 y = -y;
9523 }
9524 pos |= y << CURSOR_Y_SHIFT;
9525
4b0e333e 9526 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9527 return;
9528
5efb3e28
VS		 9529 I915_WRITE(CURPOS(pipe), pos);
9530
4398ad45
VS		 9531 /* ILK+ do this automagically */
9532 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9533 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 9534 base += (intel_crtc->base.cursor->state->crtc_h *
9535 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 9536 }
9537
8ac54669 9538 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9539 i845_update_cursor(crtc, base);
9540 else
9541 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9542}
9543
dc41c154
VS		 9544static bool cursor_size_ok(struct drm_device *dev,
9545 uint32_t width, uint32_t height)
9546{
9547 if (width == 0 || height == 0)
9548 return false;
9549
9550 /*
9551 * 845g/865g are special in that they are only limited by
9552 * the width of their cursors, the height is arbitrary up to
9553 * the precision of the register. Everything else requires
9554 * square cursors, limited to a few power-of-two sizes.
9555 */
9556 if (IS_845G(dev) || IS_I865G(dev)) {
9557 if ((width & 63) != 0)
9558 return false;
9559
9560 if (width > (IS_845G(dev) ? 64 : 512))
9561 return false;
9562
9563 if (height > 1023)
9564 return false;
9565 } else {
9566 switch (width | height) {
9567 case 256:
9568 case 128:
9569 if (IS_GEN2(dev))
9570 return false;
9571 case 64:
9572 break;
9573 default:
9574 return false;
9575 }
9576 }
9577
9578 return true;
9579}
9580
79e53945 9581static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 9582 u16 *blue, uint32_t start, uint32_t size)
79e53945 9583{
7203425a 9584 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 9585 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 9586
7203425a 9587 for (i = start; i < end; i++) {
79e53945
JB		 9588 intel_crtc->lut_r[i] = red[i] >> 8;
9589 intel_crtc->lut_g[i] = green[i] >> 8;
9590 intel_crtc->lut_b[i] = blue[i] >> 8;
9591 }
9592
9593 intel_crtc_load_lut(crtc);
9594}
9595
79e53945
JB		 9596/* VESA 640x480x72Hz mode to set on the pipe */
9597static struct drm_display_mode load_detect_mode = {
9598 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9599 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9600};
9601
a8bb6818
DV		 9602struct drm_framebuffer *
9603__intel_framebuffer_create(struct drm_device *dev,
9604 struct drm_mode_fb_cmd2 *mode_cmd,
9605 struct drm_i915_gem_object *obj)
d2dff872
CW		 9606{
9607 struct intel_framebuffer *intel_fb;
9608 int ret;
9609
9610 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9611 if (!intel_fb) {
6ccb81f2 9612 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 9613 return ERR_PTR(-ENOMEM);
9614 }
9615
9616 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 9617 if (ret)
9618 goto err;
d2dff872
CW		 9619
9620 return &intel_fb->base;
dd4916c5 9621err:
6ccb81f2 9622 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 9623 kfree(intel_fb);
9624
9625 return ERR_PTR(ret);
d2dff872
CW		 9626}
9627
b5ea642a 9628static struct drm_framebuffer *
a8bb6818
DV		 9629intel_framebuffer_create(struct drm_device *dev,
9630 struct drm_mode_fb_cmd2 *mode_cmd,
9631 struct drm_i915_gem_object *obj)
9632{
9633 struct drm_framebuffer *fb;
9634 int ret;
9635
9636 ret = i915_mutex_lock_interruptible(dev);
9637 if (ret)
9638 return ERR_PTR(ret);
9639 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9640 mutex_unlock(&dev->struct_mutex);
9641
9642 return fb;
9643}
9644
d2dff872
CW		 9645static u32
9646intel_framebuffer_pitch_for_width(int width, int bpp)
9647{
9648 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9649 return ALIGN(pitch, 64);
9650}
9651
9652static u32
9653intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9654{
9655 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 9656 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 9657}
9658
9659static struct drm_framebuffer *
9660intel_framebuffer_create_for_mode(struct drm_device *dev,
9661 struct drm_display_mode *mode,
9662 int depth, int bpp)
9663{
9664 struct drm_i915_gem_object *obj;
0fed39bd 9665 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 9666
9667 obj = i915_gem_alloc_object(dev,
9668 intel_framebuffer_size_for_mode(mode, bpp));
9669 if (obj == NULL)
9670 return ERR_PTR(-ENOMEM);
9671
9672 mode_cmd.width = mode->hdisplay;
9673 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 9674 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9675 bpp);
5ca0c34a 9676 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 9677
9678 return intel_framebuffer_create(dev, &mode_cmd, obj);
9679}
9680
9681static struct drm_framebuffer *
9682mode_fits_in_fbdev(struct drm_device *dev,
9683 struct drm_display_mode *mode)
9684{
4520f53a 9685#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 9686 struct drm_i915_private *dev_priv = dev->dev_private;
9687 struct drm_i915_gem_object *obj;
9688 struct drm_framebuffer *fb;
9689
4c0e5528 9690 if (!dev_priv->fbdev)
d2dff872
CW		 9691 return NULL;
9692
4c0e5528 9693 if (!dev_priv->fbdev->fb)
d2dff872
CW		 9694 return NULL;
9695
4c0e5528
DV		 9696 obj = dev_priv->fbdev->fb->obj;
9697 BUG_ON(!obj);
9698
8bcd4553 9699 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 9700 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9701 fb->bits_per_pixel))
d2dff872
CW		 9702 return NULL;
9703
01f2c773 9704 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 9705 return NULL;
9706
9707 return fb;
4520f53a
DV		 9708#else
9709 return NULL;
9710#endif
d2dff872
CW		 9711}
9712
d3a40d1b
ACO		 9713static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9714 struct drm_crtc *crtc,
9715 struct drm_display_mode *mode,
9716 struct drm_framebuffer *fb,
9717 int x, int y)
9718{
9719 struct drm_plane_state *plane_state;
9720 int hdisplay, vdisplay;
9721 int ret;
9722
9723 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9724 if (IS_ERR(plane_state))
9725 return PTR_ERR(plane_state);
9726
9727 if (mode)
9728 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
9729 else
9730 hdisplay = vdisplay = 0;
9731
9732 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9733 if (ret)
9734 return ret;
9735 drm_atomic_set_fb_for_plane(plane_state, fb);
9736 plane_state->crtc_x = 0;
9737 plane_state->crtc_y = 0;
9738 plane_state->crtc_w = hdisplay;
9739 plane_state->crtc_h = vdisplay;
9740 plane_state->src_x = x << 16;
9741 plane_state->src_y = y << 16;
9742 plane_state->src_w = hdisplay << 16;
9743 plane_state->src_h = vdisplay << 16;
9744
9745 return 0;
9746}
9747
d2434ab7 9748bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 9749 struct drm_display_mode *mode,
51fd371b
RC		 9750 struct intel_load_detect_pipe *old,
9751 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 9752{
9753 struct intel_crtc *intel_crtc;
d2434ab7
DV		 9754 struct intel_encoder *intel_encoder =
9755 intel_attached_encoder(connector);
79e53945 9756 struct drm_crtc *possible_crtc;
4ef69c7a 9757 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 9758 struct drm_crtc *crtc = NULL;
9759 struct drm_device *dev = encoder->dev;
94352cf9 9760 struct drm_framebuffer *fb;
51fd371b 9761 struct drm_mode_config *config = &dev->mode_config;
83a57153 9762 struct drm_atomic_state *state = NULL;
944b0c76 9763 struct drm_connector_state *connector_state;
4be07317 9764 struct intel_crtc_state *crtc_state;
51fd371b 9765 int ret, i = -1;
79e53945 9766
d2dff872 9767 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9768 connector->base.id, connector->name,
8e329a03 9769 encoder->base.id, encoder->name);
d2dff872 9770
51fd371b
RC		 9771retry:
9772 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9773 if (ret)
9774 goto fail_unlock;
6e9f798d 9775
79e53945
JB		 9776 /*
9777 * Algorithm gets a little messy:
7a5e4805 9778 *
79e53945
JB		 9779 * - if the connector already has an assigned crtc, use it (but make
9780 * sure it's on first)
7a5e4805 9781 *
79e53945
JB		 9782 * - try to find the first unused crtc that can drive this connector,
9783 * and use that if we find one
79e53945
JB		 9784 */
9785
9786 /* See if we already have a CRTC for this connector */
9787 if (encoder->crtc) {
9788 crtc = encoder->crtc;
8261b191 9789
51fd371b 9790 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 9791 if (ret)
9792 goto fail_unlock;
9793 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 9794 if (ret)
9795 goto fail_unlock;
7b24056b 9796
24218aac 9797 old->dpms_mode = connector->dpms;
8261b191
CW		 9798 old->load_detect_temp = false;
9799
9800 /* Make sure the crtc and connector are running */
24218aac
DV		 9801 if (connector->dpms != DRM_MODE_DPMS_ON)
9802 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 9803
7173188d 9804 return true;
79e53945
JB		 9805 }
9806
9807 /* Find an unused one (if possible) */
70e1e0ec 9808 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 9809 i++;
9810 if (!(encoder->possible_crtcs & (1 << i)))
9811 continue;
83d65738 9812 if (possible_crtc->state->enable)
a459249c
VS		 9813 continue;
9814 /* This can occur when applying the pipe A quirk on resume. */
9815 if (to_intel_crtc(possible_crtc)->new_enabled)
9816 continue;
9817
9818 crtc = possible_crtc;
9819 break;
79e53945
JB		 9820 }
9821
9822 /*
9823 * If we didn't find an unused CRTC, don't use any.
9824 */
9825 if (!crtc) {
7173188d 9826 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 9827 goto fail_unlock;
79e53945
JB		 9828 }
9829
51fd371b
RC		 9830 ret = drm_modeset_lock(&crtc->mutex, ctx);
9831 if (ret)
4d02e2de
DV		 9832 goto fail_unlock;
9833 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
9834 if (ret)
51fd371b 9835 goto fail_unlock;
fc303101
DV		 9836 intel_encoder->new_crtc = to_intel_crtc(crtc);
9837 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 9838
9839 intel_crtc = to_intel_crtc(crtc);
412b61d8 9840 intel_crtc->new_enabled = true;
24218aac 9841 old->dpms_mode = connector->dpms;
8261b191 9842 old->load_detect_temp = true;
d2dff872 9843 old->release_fb = NULL;
79e53945 9844
83a57153
ACO		 9845 state = drm_atomic_state_alloc(dev);
9846 if (!state)
9847 return false;
9848
9849 state->acquire_ctx = ctx;
9850
944b0c76
ACO		 9851 connector_state = drm_atomic_get_connector_state(state, connector);
9852 if (IS_ERR(connector_state)) {
9853 ret = PTR_ERR(connector_state);
9854 goto fail;
9855 }
9856
9857 connector_state->crtc = crtc;
9858 connector_state->best_encoder = &intel_encoder->base;
9859
4be07317
ACO		 9860 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9861 if (IS_ERR(crtc_state)) {
9862 ret = PTR_ERR(crtc_state);
9863 goto fail;
9864 }
9865
49d6fa21 9866 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 9867
6492711d
CW		 9868 if (!mode)
9869 mode = &load_detect_mode;
79e53945 9870
d2dff872
CW		 9871 /* We need a framebuffer large enough to accommodate all accesses
9872 * that the plane may generate whilst we perform load detection.
9873 * We can not rely on the fbcon either being present (we get called
9874 * during its initialisation to detect all boot displays, or it may
9875 * not even exist) or that it is large enough to satisfy the
9876 * requested mode.
9877 */
94352cf9
DV		 9878 fb = mode_fits_in_fbdev(dev, mode);
9879 if (fb == NULL) {
d2dff872 9880 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 9881 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9882 old->release_fb = fb;
d2dff872
CW		 9883 } else
9884 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 9885 if (IS_ERR(fb)) {
d2dff872 9886 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 9887 goto fail;
79e53945 9888 }
79e53945 9889
d3a40d1b
ACO		 9890 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
9891 if (ret)
9892 goto fail;
9893
8c7b5ccb
ACO		 9894 drm_mode_copy(&crtc_state->base.mode, mode);
9895
9896 if (intel_set_mode(crtc, state)) {
6492711d 9897 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 9898 if (old->release_fb)
9899 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 9900 goto fail;
79e53945 9901 }
9128b040 9902 crtc->primary->crtc = crtc;
7173188d 9903
79e53945 9904 /* let the connector get through one full cycle before testing */
9d0498a2 9905 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 9906 return true;
412b61d8
VS		 9907
9908 fail:
83d65738 9909 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 9910fail_unlock:
e5d958ef
ACO		 9911 drm_atomic_state_free(state);
9912 state = NULL;
83a57153 9913
51fd371b
RC		 9914 if (ret == -EDEADLK) {
9915 drm_modeset_backoff(ctx);
9916 goto retry;
9917 }
9918
412b61d8 9919 return false;
79e53945
JB		 9920}
9921
d2434ab7 9922void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 9923 struct intel_load_detect_pipe *old,
9924 struct drm_modeset_acquire_ctx *ctx)
79e53945 9925{
83a57153 9926 struct drm_device *dev = connector->dev;
d2434ab7
DV		 9927 struct intel_encoder *intel_encoder =
9928 intel_attached_encoder(connector);
4ef69c7a 9929 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 9930 struct drm_crtc *crtc = encoder->crtc;
412b61d8 9931 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 9932 struct drm_atomic_state *state;
944b0c76 9933 struct drm_connector_state *connector_state;
4be07317 9934 struct intel_crtc_state *crtc_state;
d3a40d1b 9935 int ret;
79e53945 9936
d2dff872 9937 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9938 connector->base.id, connector->name,
8e329a03 9939 encoder->base.id, encoder->name);
d2dff872 9940
8261b191 9941 if (old->load_detect_temp) {
83a57153 9942 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 9943 if (!state)
9944 goto fail;
83a57153
ACO		 9945
9946 state->acquire_ctx = ctx;
9947
944b0c76
ACO		 9948 connector_state = drm_atomic_get_connector_state(state, connector);
9949 if (IS_ERR(connector_state))
9950 goto fail;
9951
4be07317
ACO		 9952 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
9953 if (IS_ERR(crtc_state))
9954 goto fail;
9955
fc303101
DV		 9956 to_intel_connector(connector)->new_encoder = NULL;
9957 intel_encoder->new_crtc = NULL;
412b61d8 9958 intel_crtc->new_enabled = false;
944b0c76
ACO		 9959
9960 connector_state->best_encoder = NULL;
9961 connector_state->crtc = NULL;
9962
49d6fa21 9963 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 9964
d3a40d1b
ACO		 9965 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
9966 0, 0);
9967 if (ret)
9968 goto fail;
9969
2bfb4627
ACO		 9970 ret = intel_set_mode(crtc, state);
9971 if (ret)
9972 goto fail;
d2dff872 9973
36206361
DV		 9974 if (old->release_fb) {
9975 drm_framebuffer_unregister_private(old->release_fb);
9976 drm_framebuffer_unreference(old->release_fb);
9977 }
d2dff872 9978
0622a53c 9979 return;
79e53945
JB		 9980 }
9981
c751ce4f 9982 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 9983 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9984 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 9985
9986 return;
9987fail:
9988 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
9989 drm_atomic_state_free(state);
79e53945
JB		 9990}
9991
da4a1efa 9992static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 9993 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 9994{
9995 struct drm_i915_private *dev_priv = dev->dev_private;
9996 u32 dpll = pipe_config->dpll_hw_state.dpll;
9997
9998 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 9999 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10000 else if (HAS_PCH_SPLIT(dev))
10001 return 120000;
10002 else if (!IS_GEN2(dev))
10003 return 96000;
10004 else
10005 return 48000;
10006}
10007
79e53945 10008/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10009static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10010 struct intel_crtc_state *pipe_config)
79e53945 10011{
f1f644dc 10012 struct drm_device *dev = crtc->base.dev;
79e53945 10013 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10014 int pipe = pipe_config->cpu_transcoder;
293623f7 10015 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10016 u32 fp;
10017 intel_clock_t clock;
da4a1efa 10018 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10019
10020 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10021 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10022 else
293623f7 10023 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10024
10025 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10026 if (IS_PINEVIEW(dev)) {
10027 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10028 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10029 } else {
10030 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10031 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10032 }
10033
a6c45cf0 10034 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10035 if (IS_PINEVIEW(dev))
10036 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10037 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10038 else
10039 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10040 DPLL_FPA01_P1_POST_DIV_SHIFT);
10041
10042 switch (dpll & DPLL_MODE_MASK) {
10043 case DPLLB_MODE_DAC_SERIAL:
10044 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10045 5 : 10;
10046 break;
10047 case DPLLB_MODE_LVDS:
10048 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10049 7 : 14;
10050 break;
10051 default:
28c97730 10052 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10053 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10054 return;
79e53945
JB		 10055 }
10056
ac58c3f0 10057 if (IS_PINEVIEW(dev))
da4a1efa 10058 pineview_clock(refclk, &clock);
ac58c3f0 10059 else
da4a1efa 10060 i9xx_clock(refclk, &clock);
79e53945 10061 } else {
0fb58223 10062 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10063 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10064
10065 if (is_lvds) {
10066 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10067 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10068
10069 if (lvds & LVDS_CLKB_POWER_UP)
10070 clock.p2 = 7;
10071 else
10072 clock.p2 = 14;
79e53945
JB		 10073 } else {
10074 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10075 clock.p1 = 2;
10076 else {
10077 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10078 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10079 }
10080 if (dpll & PLL_P2_DIVIDE_BY_4)
10081 clock.p2 = 4;
10082 else
10083 clock.p2 = 2;
79e53945 10084 }
da4a1efa
VS		 10085
10086 i9xx_clock(refclk, &clock);
79e53945
JB		 10087 }
10088
18442d08
VS		 10089 /*
10090 * This value includes pixel_multiplier. We will use
241bfc38 10091 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10092 * encoder's get_config() function.
10093 */
10094 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 10095}
10096
6878da05
VS		 10097int intel_dotclock_calculate(int link_freq,
10098 const struct intel_link_m_n *m_n)
f1f644dc 10099{
f1f644dc
JB		 10100 /*
10101 * The calculation for the data clock is:
1041a02f 10102 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10103 * But we want to avoid losing precison if possible, so:
1041a02f 10104 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10105 *
10106 * and the link clock is simpler:
1041a02f 10107 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10108 */
10109
6878da05
VS		 10110 if (!m_n->link_n)
10111 return 0;
f1f644dc 10112
6878da05
VS		 10113 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10114}
f1f644dc 10115
18442d08 10116static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10117 struct intel_crtc_state *pipe_config)
6878da05
VS		 10118{
10119 struct drm_device *dev = crtc->base.dev;
79e53945 10120
18442d08
VS		 10121 /* read out port_clock from the DPLL */
10122 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10123
f1f644dc 10124 /*
18442d08 10125 * This value does not include pixel_multiplier.
241bfc38 10126 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10127 * agree once we know their relationship in the encoder's
10128 * get_config() function.
79e53945 10129 */
2d112de7 10130 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10131 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10132 &pipe_config->fdi_m_n);
79e53945
JB		 10133}
10134
10135/** Returns the currently programmed mode of the given pipe. */
10136struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10137 struct drm_crtc *crtc)
10138{
548f245b 10139 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10141 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10142 struct drm_display_mode *mode;
5cec258b 10143 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10144 int htot = I915_READ(HTOTAL(cpu_transcoder));
10145 int hsync = I915_READ(HSYNC(cpu_transcoder));
10146 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10147 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10148 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10149
10150 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10151 if (!mode)
10152 return NULL;
10153
f1f644dc
JB		 10154 /*
10155 * Construct a pipe_config sufficient for getting the clock info
10156 * back out of crtc_clock_get.
10157 *
10158 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10159 * to use a real value here instead.
10160 */
293623f7 10161 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10162 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10163 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10164 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10165 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10166 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10167
773ae034 10168 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10169 mode->hdisplay = (htot & 0xffff) + 1;
10170 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10171 mode->hsync_start = (hsync & 0xffff) + 1;
10172 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10173 mode->vdisplay = (vtot & 0xffff) + 1;
10174 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10175 mode->vsync_start = (vsync & 0xffff) + 1;
10176 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10177
10178 drm_mode_set_name(mode);
79e53945
JB		 10179
10180 return mode;
10181}
10182
652c393a
JB		 10183static void intel_decrease_pllclock(struct drm_crtc *crtc)
10184{
10185 struct drm_device *dev = crtc->dev;
fbee40df 10186 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10187 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 10188
baff296c 10189 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 10190 return;
10191
10192 if (!dev_priv->lvds_downclock_avail)
10193 return;
10194
10195 /*
10196 * Since this is called by a timer, we should never get here in
10197 * the manual case.
10198 */
10199 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 10200 int pipe = intel_crtc->pipe;
10201 int dpll_reg = DPLL(pipe);
10202 int dpll;
f6e5b160 10203
44d98a61 10204 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 10205
8ac5a6d5 10206 assert_panel_unlocked(dev_priv, pipe);
652c393a 10207
dc257cf1 10208 dpll = I915_READ(dpll_reg);
652c393a
JB		 10209 dpll |= DISPLAY_RATE_SELECT_FPA1;
10210 I915_WRITE(dpll_reg, dpll);
9d0498a2 10211 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 10212 dpll = I915_READ(dpll_reg);
10213 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 10214 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 10215 }
10216
10217}
10218
f047e395
CW		 10219void intel_mark_busy(struct drm_device *dev)
10220{
c67a470b
PZ		 10221 struct drm_i915_private *dev_priv = dev->dev_private;
10222
f62a0076
CW		 10223 if (dev_priv->mm.busy)
10224 return;
10225
43694d69 10226 intel_runtime_pm_get(dev_priv);
c67a470b 10227 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10228 if (INTEL_INFO(dev)->gen >= 6)
10229 gen6_rps_busy(dev_priv);
f62a0076 10230 dev_priv->mm.busy = true;
f047e395
CW		 10231}
10232
10233void intel_mark_idle(struct drm_device *dev)
652c393a 10234{
c67a470b 10235 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10236 struct drm_crtc *crtc;
652c393a 10237
f62a0076
CW		 10238 if (!dev_priv->mm.busy)
10239 return;
10240
10241 dev_priv->mm.busy = false;
10242
70e1e0ec 10243 for_each_crtc(dev, crtc) {
f4510a27 10244 if (!crtc->primary->fb)
652c393a
JB		 10245 continue;
10246
725a5b54 10247 intel_decrease_pllclock(crtc);
652c393a 10248 }
b29c19b6 10249
3d13ef2e 10250 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10251 gen6_rps_idle(dev->dev_private);
bb4cdd53 10252
43694d69 10253 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10254}
10255
79e53945
JB		 10256static void intel_crtc_destroy(struct drm_crtc *crtc)
10257{
10258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10259 struct drm_device *dev = crtc->dev;
10260 struct intel_unpin_work *work;
67e77c5a 10261
5e2d7afc 10262 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10263 work = intel_crtc->unpin_work;
10264 intel_crtc->unpin_work = NULL;
5e2d7afc 10265 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10266
10267 if (work) {
10268 cancel_work_sync(&work->work);
10269 kfree(work);
10270 }
79e53945
JB		 10271
10272 drm_crtc_cleanup(crtc);
67e77c5a 10273
79e53945
JB		 10274 kfree(intel_crtc);
10275}
10276
6b95a207
KH		 10277static void intel_unpin_work_fn(struct work_struct *__work)
10278{
10279 struct intel_unpin_work *work =
10280 container_of(__work, struct intel_unpin_work, work);
b4a98e57 10281 struct drm_device *dev = work->crtc->dev;
f99d7069 10282 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 10283
b4a98e57 10284 mutex_lock(&dev->struct_mutex);
82bc3b2d 10285 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 10286 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10287
7ff0ebcc 10288 intel_fbc_update(dev);
f06cc1b9
JH		 10289
10290 if (work->flip_queued_req)
146d84f0 10291 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10292 mutex_unlock(&dev->struct_mutex);
10293
f99d7069 10294 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 10295 drm_framebuffer_unreference(work->old_fb);
f99d7069 10296
b4a98e57
CW		 10297 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10298 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10299
6b95a207
KH		 10300 kfree(work);
10301}
10302
1afe3e9d 10303static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10304 struct drm_crtc *crtc)
6b95a207 10305{
6b95a207
KH		 10306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10307 struct intel_unpin_work *work;
6b95a207
KH		 10308 unsigned long flags;
10309
10310 /* Ignore early vblank irqs */
10311 if (intel_crtc == NULL)
10312 return;
10313
f326038a
DV		 10314 /*
10315 * This is called both by irq handlers and the reset code (to complete
10316 * lost pageflips) so needs the full irqsave spinlocks.
10317 */
6b95a207
KH		 10318 spin_lock_irqsave(&dev->event_lock, flags);
10319 work = intel_crtc->unpin_work;
e7d841ca
CW		 10320
10321 /* Ensure we don't miss a work->pending update ... */
10322 smp_rmb();
10323
10324 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10325 spin_unlock_irqrestore(&dev->event_lock, flags);
10326 return;
10327 }
10328
d6bbafa1 10329 page_flip_completed(intel_crtc);
0af7e4df 10330
6b95a207 10331 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10332}
10333
1afe3e9d
JB		 10334void intel_finish_page_flip(struct drm_device *dev, int pipe)
10335{
fbee40df 10336 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10337 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10338
49b14a5c 10339 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10340}
10341
10342void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10343{
fbee40df 10344 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10345 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10346
49b14a5c 10347 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10348}
10349
75f7f3ec
VS		 10350/* Is 'a' after or equal to 'b'? */
10351static bool g4x_flip_count_after_eq(u32 a, u32 b)
10352{
10353 return !((a - b) & 0x80000000);
10354}
10355
10356static bool page_flip_finished(struct intel_crtc *crtc)
10357{
10358 struct drm_device *dev = crtc->base.dev;
10359 struct drm_i915_private *dev_priv = dev->dev_private;
10360
bdfa7542
VS		 10361 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10362 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10363 return true;
10364
75f7f3ec
VS		 10365 /*
10366 * The relevant registers doen't exist on pre-ctg.
10367 * As the flip done interrupt doesn't trigger for mmio
10368 * flips on gmch platforms, a flip count check isn't
10369 * really needed there. But since ctg has the registers,
10370 * include it in the check anyway.
10371 */
10372 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10373 return true;
10374
10375 /*
10376 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10377 * used the same base address. In that case the mmio flip might
10378 * have completed, but the CS hasn't even executed the flip yet.
10379 *
10380 * A flip count check isn't enough as the CS might have updated
10381 * the base address just after start of vblank, but before we
10382 * managed to process the interrupt. This means we'd complete the
10383 * CS flip too soon.
10384 *
10385 * Combining both checks should get us a good enough result. It may
10386 * still happen that the CS flip has been executed, but has not
10387 * yet actually completed. But in case the base address is the same
10388 * anyway, we don't really care.
10389 */
10390 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10391 crtc->unpin_work->gtt_offset &&
10392 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10393 crtc->unpin_work->flip_count);
10394}
10395
6b95a207
KH		 10396void intel_prepare_page_flip(struct drm_device *dev, int plane)
10397{
fbee40df 10398 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10399 struct intel_crtc *intel_crtc =
10400 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10401 unsigned long flags;
10402
f326038a
DV		 10403
10404 /*
10405 * This is called both by irq handlers and the reset code (to complete
10406 * lost pageflips) so needs the full irqsave spinlocks.
10407 *
10408 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10409 * generate a page-flip completion irq, i.e. every modeset
10410 * is also accompanied by a spurious intel_prepare_page_flip().
10411 */
6b95a207 10412 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10413 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10414 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10415 spin_unlock_irqrestore(&dev->event_lock, flags);
10416}
10417
eba905b2 10418static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10419{
10420 /* Ensure that the work item is consistent when activating it ... */
10421 smp_wmb();
10422 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10423 /* and that it is marked active as soon as the irq could fire. */
10424 smp_wmb();
10425}
10426
8c9f3aaf
JB		 10427static int intel_gen2_queue_flip(struct drm_device *dev,
10428 struct drm_crtc *crtc,
10429 struct drm_framebuffer *fb,
ed8d1975 10430 struct drm_i915_gem_object *obj,
a4872ba6 10431 struct intel_engine_cs *ring,
ed8d1975 10432 uint32_t flags)
8c9f3aaf 10433{
8c9f3aaf 10434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10435 u32 flip_mask;
10436 int ret;
10437
6d90c952 10438 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10439 if (ret)
4fa62c89 10440 return ret;
8c9f3aaf
JB		 10441
10442 /* Can't queue multiple flips, so wait for the previous
10443 * one to finish before executing the next.
10444 */
10445 if (intel_crtc->plane)
10446 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10447 else
10448 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10449 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10450 intel_ring_emit(ring, MI_NOOP);
10451 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10452 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10453 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10454 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10455 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10456
10457 intel_mark_page_flip_active(intel_crtc);
09246732 10458 __intel_ring_advance(ring);
83d4092b 10459 return 0;
8c9f3aaf
JB		 10460}
10461
10462static int intel_gen3_queue_flip(struct drm_device *dev,
10463 struct drm_crtc *crtc,
10464 struct drm_framebuffer *fb,
ed8d1975 10465 struct drm_i915_gem_object *obj,
a4872ba6 10466 struct intel_engine_cs *ring,
ed8d1975 10467 uint32_t flags)
8c9f3aaf 10468{
8c9f3aaf 10469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10470 u32 flip_mask;
10471 int ret;
10472
6d90c952 10473 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10474 if (ret)
4fa62c89 10475 return ret;
8c9f3aaf
JB		 10476
10477 if (intel_crtc->plane)
10478 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10479 else
10480 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10481 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10482 intel_ring_emit(ring, MI_NOOP);
10483 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10484 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10485 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10486 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10487 intel_ring_emit(ring, MI_NOOP);
10488
e7d841ca 10489 intel_mark_page_flip_active(intel_crtc);
09246732 10490 __intel_ring_advance(ring);
83d4092b 10491 return 0;
8c9f3aaf
JB		 10492}
10493
10494static int intel_gen4_queue_flip(struct drm_device *dev,
10495 struct drm_crtc *crtc,
10496 struct drm_framebuffer *fb,
ed8d1975 10497 struct drm_i915_gem_object *obj,
a4872ba6 10498 struct intel_engine_cs *ring,
ed8d1975 10499 uint32_t flags)
8c9f3aaf
JB		 10500{
10501 struct drm_i915_private *dev_priv = dev->dev_private;
10502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10503 uint32_t pf, pipesrc;
10504 int ret;
10505
6d90c952 10506 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10507 if (ret)
4fa62c89 10508 return ret;
8c9f3aaf
JB		 10509
10510 /* i965+ uses the linear or tiled offsets from the
10511 * Display Registers (which do not change across a page-flip)
10512 * so we need only reprogram the base address.
10513 */
6d90c952
DV		 10514 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10515 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10516 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10517 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10518 obj->tiling_mode);
8c9f3aaf
JB		 10519
10520 /* XXX Enabling the panel-fitter across page-flip is so far
10521 * untested on non-native modes, so ignore it for now.
10522 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10523 */
10524 pf = 0;
10525 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10526 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10527
10528 intel_mark_page_flip_active(intel_crtc);
09246732 10529 __intel_ring_advance(ring);
83d4092b 10530 return 0;
8c9f3aaf
JB		 10531}
10532
10533static int intel_gen6_queue_flip(struct drm_device *dev,
10534 struct drm_crtc *crtc,
10535 struct drm_framebuffer *fb,
ed8d1975 10536 struct drm_i915_gem_object *obj,
a4872ba6 10537 struct intel_engine_cs *ring,
ed8d1975 10538 uint32_t flags)
8c9f3aaf
JB		 10539{
10540 struct drm_i915_private *dev_priv = dev->dev_private;
10541 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10542 uint32_t pf, pipesrc;
10543 int ret;
10544
6d90c952 10545 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10546 if (ret)
4fa62c89 10547 return ret;
8c9f3aaf 10548
6d90c952
DV		 10549 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10550 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10551 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10552 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10553
dc257cf1
DV		 10554 /* Contrary to the suggestions in the documentation,
10555 * "Enable Panel Fitter" does not seem to be required when page
10556 * flipping with a non-native mode, and worse causes a normal
10557 * modeset to fail.
10558 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10559 */
10560 pf = 0;
8c9f3aaf 10561 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10562 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10563
10564 intel_mark_page_flip_active(intel_crtc);
09246732 10565 __intel_ring_advance(ring);
83d4092b 10566 return 0;
8c9f3aaf
JB		 10567}
10568
7c9017e5
JB		 10569static int intel_gen7_queue_flip(struct drm_device *dev,
10570 struct drm_crtc *crtc,
10571 struct drm_framebuffer *fb,
ed8d1975 10572 struct drm_i915_gem_object *obj,
a4872ba6 10573 struct intel_engine_cs *ring,
ed8d1975 10574 uint32_t flags)
7c9017e5 10575{
7c9017e5 10576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10577 uint32_t plane_bit = 0;
ffe74d75
CW		 10578 int len, ret;
10579
eba905b2 10580 switch (intel_crtc->plane) {
cb05d8de
DV		 10581 case PLANE_A:
10582 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10583 break;
10584 case PLANE_B:
10585 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10586 break;
10587 case PLANE_C:
10588 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10589 break;
10590 default:
10591 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10592 return -ENODEV;
cb05d8de
DV		 10593 }
10594
ffe74d75 10595 len = 4;
f476828a 10596 if (ring->id == RCS) {
ffe74d75 10597 len += 6;
f476828a
DL		 10598 /*
10599 * On Gen 8, SRM is now taking an extra dword to accommodate
10600 * 48bits addresses, and we need a NOOP for the batch size to
10601 * stay even.
10602 */
10603 if (IS_GEN8(dev))
10604 len += 2;
10605 }
ffe74d75 10606
f66fab8e
VS		 10607 /*
10608 * BSpec MI_DISPLAY_FLIP for IVB:
10609 * "The full packet must be contained within the same cache line."
10610 *
10611 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10612 * cacheline, if we ever start emitting more commands before
10613 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10614 * then do the cacheline alignment, and finally emit the
10615 * MI_DISPLAY_FLIP.
10616 */
10617 ret = intel_ring_cacheline_align(ring);
10618 if (ret)
4fa62c89 10619 return ret;
f66fab8e 10620
ffe74d75 10621 ret = intel_ring_begin(ring, len);
7c9017e5 10622 if (ret)
4fa62c89 10623 return ret;
7c9017e5 10624
ffe74d75
CW		 10625 /* Unmask the flip-done completion message. Note that the bspec says that
10626 * we should do this for both the BCS and RCS, and that we must not unmask
10627 * more than one flip event at any time (or ensure that one flip message
10628 * can be sent by waiting for flip-done prior to queueing new flips).
10629 * Experimentation says that BCS works despite DERRMR masking all
10630 * flip-done completion events and that unmasking all planes at once
10631 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10632 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10633 */
10634 if (ring->id == RCS) {
10635 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10636 intel_ring_emit(ring, DERRMR);
10637 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10638 DERRMR_PIPEB_PRI_FLIP_DONE |
10639 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 10640 if (IS_GEN8(dev))
10641 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10642 MI_SRM_LRM_GLOBAL_GTT);
10643 else
10644 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10645 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 10646 intel_ring_emit(ring, DERRMR);
10647 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 10648 if (IS_GEN8(dev)) {
10649 intel_ring_emit(ring, 0);
10650 intel_ring_emit(ring, MI_NOOP);
10651 }
ffe74d75
CW		 10652 }
10653
cb05d8de 10654 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 10655 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 10656 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 10657 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 10658
10659 intel_mark_page_flip_active(intel_crtc);
09246732 10660 __intel_ring_advance(ring);
83d4092b 10661 return 0;
7c9017e5
JB		 10662}
10663
84c33a64
SG		 10664static bool use_mmio_flip(struct intel_engine_cs *ring,
10665 struct drm_i915_gem_object *obj)
10666{
10667 /*
10668 * This is not being used for older platforms, because
10669 * non-availability of flip done interrupt forces us to use
10670 * CS flips. Older platforms derive flip done using some clever
10671 * tricks involving the flip_pending status bits and vblank irqs.
10672 * So using MMIO flips there would disrupt this mechanism.
10673 */
10674
8e09bf83
CW		 10675 if (ring == NULL)
10676 return true;
10677
84c33a64
SG		 10678 if (INTEL_INFO(ring->dev)->gen < 5)
10679 return false;
10680
10681 if (i915.use_mmio_flip < 0)
10682 return false;
10683 else if (i915.use_mmio_flip > 0)
10684 return true;
14bf993e
OM		 10685 else if (i915.enable_execlists)
10686 return true;
84c33a64 10687 else
41c52415 10688 return ring != i915_gem_request_get_ring(obj->last_read_req);
84c33a64
SG		 10689}
10690
ff944564
DL		 10691static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10692{
10693 struct drm_device *dev = intel_crtc->base.dev;
10694 struct drm_i915_private *dev_priv = dev->dev_private;
10695 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 10696 const enum pipe pipe = intel_crtc->pipe;
10697 u32 ctl, stride;
10698
10699 ctl = I915_READ(PLANE_CTL(pipe, 0));
10700 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 10701 switch (fb->modifier[0]) {
10702 case DRM_FORMAT_MOD_NONE:
10703 break;
10704 case I915_FORMAT_MOD_X_TILED:
ff944564 10705 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 10706 break;
10707 case I915_FORMAT_MOD_Y_TILED:
10708 ctl |= PLANE_CTL_TILED_Y;
10709 break;
10710 case I915_FORMAT_MOD_Yf_TILED:
10711 ctl |= PLANE_CTL_TILED_YF;
10712 break;
10713 default:
10714 MISSING_CASE(fb->modifier[0]);
10715 }
ff944564
DL		 10716
10717 /*
10718 * The stride is either expressed as a multiple of 64 bytes chunks for
10719 * linear buffers or in number of tiles for tiled buffers.
10720 */
2ebef630
TU		 10721 stride = fb->pitches[0] /
10722 intel_fb_stride_alignment(dev, fb->modifier[0],
10723 fb->pixel_format);
ff944564
DL		 10724
10725 /*
10726 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10727 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10728 */
10729 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10730 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10731
10732 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10733 POSTING_READ(PLANE_SURF(pipe, 0));
10734}
10735
10736static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 10737{
10738 struct drm_device *dev = intel_crtc->base.dev;
10739 struct drm_i915_private *dev_priv = dev->dev_private;
10740 struct intel_framebuffer *intel_fb =
10741 to_intel_framebuffer(intel_crtc->base.primary->fb);
10742 struct drm_i915_gem_object *obj = intel_fb->obj;
10743 u32 dspcntr;
10744 u32 reg;
10745
84c33a64
SG		 10746 reg = DSPCNTR(intel_crtc->plane);
10747 dspcntr = I915_READ(reg);
10748
c5d97472
DL		 10749 if (obj->tiling_mode != I915_TILING_NONE)
10750 dspcntr |= DISPPLANE_TILED;
10751 else
10752 dspcntr &= ~DISPPLANE_TILED;
10753
84c33a64
SG		 10754 I915_WRITE(reg, dspcntr);
10755
10756 I915_WRITE(DSPSURF(intel_crtc->plane),
10757 intel_crtc->unpin_work->gtt_offset);
10758 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 10759
ff944564
DL		 10760}
10761
10762/*
10763 * XXX: This is the temporary way to update the plane registers until we get
10764 * around to using the usual plane update functions for MMIO flips
10765 */
10766static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10767{
10768 struct drm_device *dev = intel_crtc->base.dev;
10769 bool atomic_update;
10770 u32 start_vbl_count;
10771
10772 intel_mark_page_flip_active(intel_crtc);
10773
10774 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10775
10776 if (INTEL_INFO(dev)->gen >= 9)
10777 skl_do_mmio_flip(intel_crtc);
10778 else
10779 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10780 ilk_do_mmio_flip(intel_crtc);
10781
9362c7c5
ACO		 10782 if (atomic_update)
10783 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 10784}
10785
9362c7c5 10786static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 10787{
b2cfe0ab
CW		 10788 struct intel_mmio_flip *mmio_flip =
10789 container_of(work, struct intel_mmio_flip, work);
84c33a64 10790
b2cfe0ab
CW		 10791 if (mmio_flip->rq)
10792 WARN_ON(__i915_wait_request(mmio_flip->rq,
10793 mmio_flip->crtc->reset_counter,
10794 false, NULL, NULL));
84c33a64 10795
b2cfe0ab
CW		 10796 intel_do_mmio_flip(mmio_flip->crtc);
10797
10798 i915_gem_request_unreference__unlocked(mmio_flip->rq);
10799 kfree(mmio_flip);
84c33a64
SG		 10800}
10801
10802static int intel_queue_mmio_flip(struct drm_device *dev,
10803 struct drm_crtc *crtc,
10804 struct drm_framebuffer *fb,
10805 struct drm_i915_gem_object *obj,
10806 struct intel_engine_cs *ring,
10807 uint32_t flags)
10808{
b2cfe0ab
CW		 10809 struct intel_mmio_flip *mmio_flip;
10810
10811 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
10812 if (mmio_flip == NULL)
10813 return -ENOMEM;
84c33a64 10814
b2cfe0ab
CW		 10815 mmio_flip->rq = i915_gem_request_reference(obj->last_write_req);
10816 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 10817
b2cfe0ab
CW		 10818 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
10819 schedule_work(&mmio_flip->work);
84c33a64 10820
84c33a64
SG		 10821 return 0;
10822}
10823
8c9f3aaf
JB		 10824static int intel_default_queue_flip(struct drm_device *dev,
10825 struct drm_crtc *crtc,
10826 struct drm_framebuffer *fb,
ed8d1975 10827 struct drm_i915_gem_object *obj,
a4872ba6 10828 struct intel_engine_cs *ring,
ed8d1975 10829 uint32_t flags)
8c9f3aaf
JB		 10830{
10831 return -ENODEV;
10832}
10833
d6bbafa1
CW		 10834static bool __intel_pageflip_stall_check(struct drm_device *dev,
10835 struct drm_crtc *crtc)
10836{
10837 struct drm_i915_private *dev_priv = dev->dev_private;
10838 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10839 struct intel_unpin_work *work = intel_crtc->unpin_work;
10840 u32 addr;
10841
10842 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
10843 return true;
10844
10845 if (!work->enable_stall_check)
10846 return false;
10847
10848 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 10849 if (work->flip_queued_req &&
10850 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 10851 return false;
10852
1e3feefd 10853 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 10854 }
10855
1e3feefd 10856 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 10857 return false;
10858
10859 /* Potential stall - if we see that the flip has happened,
10860 * assume a missed interrupt. */
10861 if (INTEL_INFO(dev)->gen >= 4)
10862 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
10863 else
10864 addr = I915_READ(DSPADDR(intel_crtc->plane));
10865
10866 /* There is a potential issue here with a false positive after a flip
10867 * to the same address. We could address this by checking for a
10868 * non-incrementing frame counter.
10869 */
10870 return addr == work->gtt_offset;
10871}
10872
10873void intel_check_page_flip(struct drm_device *dev, int pipe)
10874{
10875 struct drm_i915_private *dev_priv = dev->dev_private;
10876 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 10878 struct intel_unpin_work *work;
f326038a 10879
6c51d46f 10880 WARN_ON(!in_interrupt());
d6bbafa1
CW		 10881
10882 if (crtc == NULL)
10883 return;
10884
f326038a 10885 spin_lock(&dev->event_lock);
6ad790c0
CW		 10886 work = intel_crtc->unpin_work;
10887 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 10888 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 10889 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 10890 page_flip_completed(intel_crtc);
6ad790c0 10891 work = NULL;
d6bbafa1 10892 }
6ad790c0
CW		 10893 if (work != NULL &&
10894 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
10895 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 10896 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 10897}
10898
6b95a207
KH		 10899static int intel_crtc_page_flip(struct drm_crtc *crtc,
10900 struct drm_framebuffer *fb,
ed8d1975
KP		 10901 struct drm_pending_vblank_event *event,
10902 uint32_t page_flip_flags)
6b95a207
KH		 10903{
10904 struct drm_device *dev = crtc->dev;
10905 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 10906 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 10907 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 10908 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 10909 struct drm_plane *primary = crtc->primary;
a071fa00 10910 enum pipe pipe = intel_crtc->pipe;
6b95a207 10911 struct intel_unpin_work *work;
a4872ba6 10912 struct intel_engine_cs *ring;
cf5d8a46 10913 bool mmio_flip;
52e68630 10914 int ret;
6b95a207 10915
2ff8fde1
MR		 10916 /*
10917 * drm_mode_page_flip_ioctl() should already catch this, but double
10918 * check to be safe. In the future we may enable pageflipping from
10919 * a disabled primary plane.
10920 */
10921 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
10922 return -EBUSY;
10923
e6a595d2 10924 /* Can't change pixel format via MI display flips. */
f4510a27 10925 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 10926 return -EINVAL;
10927
10928 /*
10929 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10930 * Note that pitch changes could also affect these register.
10931 */
10932 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 10933 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10934 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 10935 return -EINVAL;
10936
f900db47
CW		 10937 if (i915_terminally_wedged(&dev_priv->gpu_error))
10938 goto out_hang;
10939
b14c5679 10940 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 10941 if (work == NULL)
10942 return -ENOMEM;
10943
6b95a207 10944 work->event = event;
b4a98e57 10945 work->crtc = crtc;
ab8d6675 10946 work->old_fb = old_fb;
6b95a207
KH		 10947 INIT_WORK(&work->work, intel_unpin_work_fn);
10948
87b6b101 10949 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 10950 if (ret)
10951 goto free_work;
10952
6b95a207 10953 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 10954 spin_lock_irq(&dev->event_lock);
6b95a207 10955 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 10956 /* Before declaring the flip queue wedged, check if
10957 * the hardware completed the operation behind our backs.
10958 */
10959 if (__intel_pageflip_stall_check(dev, crtc)) {
10960 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10961 page_flip_completed(intel_crtc);
10962 } else {
10963 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 10964 spin_unlock_irq(&dev->event_lock);
468f0b44 10965
d6bbafa1
CW		 10966 drm_crtc_vblank_put(crtc);
10967 kfree(work);
10968 return -EBUSY;
10969 }
6b95a207
KH		 10970 }
10971 intel_crtc->unpin_work = work;
5e2d7afc 10972 spin_unlock_irq(&dev->event_lock);
6b95a207 10973
b4a98e57
CW		 10974 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10975 flush_workqueue(dev_priv->wq);
10976
75dfca80 10977 /* Reference the objects for the scheduled work. */
ab8d6675 10978 drm_framebuffer_reference(work->old_fb);
05394f39 10979 drm_gem_object_reference(&obj->base);
6b95a207 10980
f4510a27 10981 crtc->primary->fb = fb;
afd65eb4 10982 update_state_fb(crtc->primary);
1ed1f968 10983
e1f99ce6 10984 work->pending_flip_obj = obj;
e1f99ce6 10985
89ed88ba
CW		 10986 ret = i915_mutex_lock_interruptible(dev);
10987 if (ret)
10988 goto cleanup;
10989
b4a98e57 10990 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 10991 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 10992
75f7f3ec 10993 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 10994 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 10995
4fa62c89
VS		 10996 if (IS_VALLEYVIEW(dev)) {
10997 ring = &dev_priv->ring[BCS];
ab8d6675 10998 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 10999 /* vlv: DISPLAY_FLIP fails to change tiling */
11000 ring = NULL;
48bf5b2d 11001 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11002 ring = &dev_priv->ring[BCS];
4fa62c89 11003 } else if (INTEL_INFO(dev)->gen >= 7) {
41c52415 11004 ring = i915_gem_request_get_ring(obj->last_read_req);
4fa62c89
VS		 11005 if (ring == NULL || ring->id != RCS)
11006 ring = &dev_priv->ring[BCS];
11007 } else {
11008 ring = &dev_priv->ring[RCS];
11009 }
11010
cf5d8a46
CW		 11011 mmio_flip = use_mmio_flip(ring, obj);
11012
11013 /* When using CS flips, we want to emit semaphores between rings.
11014 * However, when using mmio flips we will create a task to do the
11015 * synchronisation, so all we want here is to pin the framebuffer
11016 * into the display plane and skip any waits.
11017 */
82bc3b2d 11018 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46
CW		 11019 crtc->primary->state,
11020 mmio_flip ? i915_gem_request_get_ring(obj->last_read_req) : ring);
8c9f3aaf
JB		 11021 if (ret)
11022 goto cleanup_pending;
6b95a207 11023
121920fa
TU		 11024 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11025 + intel_crtc->dspaddr_offset;
4fa62c89 11026
cf5d8a46 11027 if (mmio_flip) {
84c33a64
SG		 11028 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11029 page_flip_flags);
d6bbafa1
CW		 11030 if (ret)
11031 goto cleanup_unpin;
11032
f06cc1b9
JH		 11033 i915_gem_request_assign(&work->flip_queued_req,
11034 obj->last_write_req);
d6bbafa1 11035 } else {
d94b5030
CW		 11036 if (obj->last_write_req) {
11037 ret = i915_gem_check_olr(obj->last_write_req);
11038 if (ret)
11039 goto cleanup_unpin;
11040 }
11041
84c33a64 11042 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 11043 page_flip_flags);
11044 if (ret)
11045 goto cleanup_unpin;
11046
f06cc1b9
JH		 11047 i915_gem_request_assign(&work->flip_queued_req,
11048 intel_ring_get_request(ring));
d6bbafa1
CW		 11049 }
11050
1e3feefd 11051 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11052 work->enable_stall_check = true;
4fa62c89 11053
ab8d6675 11054 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 11055 INTEL_FRONTBUFFER_PRIMARY(pipe));
11056
7ff0ebcc 11057 intel_fbc_disable(dev);
f99d7069 11058 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 11059 mutex_unlock(&dev->struct_mutex);
11060
e5510fac
JB		 11061 trace_i915_flip_request(intel_crtc->plane, obj);
11062
6b95a207 11063 return 0;
96b099fd 11064
4fa62c89 11065cleanup_unpin:
82bc3b2d 11066 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11067cleanup_pending:
b4a98e57 11068 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11069 mutex_unlock(&dev->struct_mutex);
11070cleanup:
f4510a27 11071 crtc->primary->fb = old_fb;
afd65eb4 11072 update_state_fb(crtc->primary);
89ed88ba
CW		 11073
11074 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11075 drm_framebuffer_unreference(work->old_fb);
96b099fd 11076
5e2d7afc 11077 spin_lock_irq(&dev->event_lock);
96b099fd 11078 intel_crtc->unpin_work = NULL;
5e2d7afc 11079 spin_unlock_irq(&dev->event_lock);
96b099fd 11080
87b6b101 11081 drm_crtc_vblank_put(crtc);
7317c75e 11082free_work:
96b099fd
CW		 11083 kfree(work);
11084
f900db47
CW		 11085 if (ret == -EIO) {
11086out_hang:
53a366b9 11087 ret = intel_plane_restore(primary);
f0d3dad3 11088 if (ret == 0 && event) {
5e2d7afc 11089 spin_lock_irq(&dev->event_lock);
a071fa00 11090 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11091 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11092 }
f900db47 11093 }
96b099fd 11094 return ret;
6b95a207
KH		 11095}
11096
65b38e0d 11097static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11098 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11099 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11100 .atomic_begin = intel_begin_crtc_commit,
11101 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 11102};
11103
9a935856
DV		 11104/**
11105 * intel_modeset_update_staged_output_state
11106 *
11107 * Updates the staged output configuration state, e.g. after we've read out the
11108 * current hw state.
11109 */
11110static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11111{
7668851f 11112 struct intel_crtc *crtc;
9a935856
DV		 11113 struct intel_encoder *encoder;
11114 struct intel_connector *connector;
f6e5b160 11115
3a3371ff 11116 for_each_intel_connector(dev, connector) {
9a935856
DV		 11117 connector->new_encoder =
11118 to_intel_encoder(connector->base.encoder);
11119 }
f6e5b160 11120
b2784e15 11121 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11122 encoder->new_crtc =
11123 to_intel_crtc(encoder->base.crtc);
11124 }
7668851f 11125
d3fcc808 11126 for_each_intel_crtc(dev, crtc) {
83d65738 11127 crtc->new_enabled = crtc->base.state->enable;
7668851f 11128 }
f6e5b160
CW		 11129}
11130
d29b2f9d
ACO		 11131/* Transitional helper to copy current connector/encoder state to
11132 * connector->state. This is needed so that code that is partially
11133 * converted to atomic does the right thing.
11134 */
11135static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11136{
11137 struct intel_connector *connector;
11138
11139 for_each_intel_connector(dev, connector) {
11140 if (connector->base.encoder) {
11141 connector->base.state->best_encoder =
11142 connector->base.encoder;
11143 connector->base.state->crtc =
11144 connector->base.encoder->crtc;
11145 } else {
11146 connector->base.state->best_encoder = NULL;
11147 connector->base.state->crtc = NULL;
11148 }
11149 }
11150}
11151
a821fc46 11152/* Fixup legacy state after an atomic state swap.
9a935856 11153 */
a821fc46 11154static void intel_modeset_fixup_state(struct drm_atomic_state *state)
9a935856 11155{
a821fc46 11156 struct intel_crtc *crtc;
9a935856 11157 struct intel_encoder *encoder;
a821fc46 11158 struct intel_connector *connector;
d5432a9d 11159
a821fc46
ACO		 11160 for_each_intel_connector(state->dev, connector) {
11161 connector->base.encoder = connector->base.state->best_encoder;
11162 if (connector->base.encoder)
11163 connector->base.encoder->crtc =
11164 connector->base.state->crtc;
9a935856 11165 }
f6e5b160 11166
d5432a9d
ACO		 11167 /* Update crtc of disabled encoders */
11168 for_each_intel_encoder(state->dev, encoder) {
11169 int num_connectors = 0;
11170
a821fc46
ACO		 11171 for_each_intel_connector(state->dev, connector)
11172 if (connector->base.encoder == &encoder->base)
d5432a9d
ACO		 11173 num_connectors++;
11174
11175 if (num_connectors == 0)
11176 encoder->base.crtc = NULL;
9a935856 11177 }
7668851f 11178
a821fc46
ACO		 11179 for_each_intel_crtc(state->dev, crtc) {
11180 crtc->base.enabled = crtc->base.state->enable;
11181 crtc->config = to_intel_crtc_state(crtc->base.state);
7668851f 11182 }
d29b2f9d 11183
d5432a9d
ACO		 11184 /* Copy the new configuration to the staged state, to keep the few
11185 * pieces of code that haven't been converted yet happy */
11186 intel_modeset_update_staged_output_state(state->dev);
9a935856
DV		 11187}
11188
050f7aeb 11189static void
eba905b2 11190connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11191 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11192{
11193 int bpp = pipe_config->pipe_bpp;
11194
11195 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11196 connector->base.base.id,
c23cc417 11197 connector->base.name);
050f7aeb
DV		 11198
11199 /* Don't use an invalid EDID bpc value */
11200 if (connector->base.display_info.bpc &&
11201 connector->base.display_info.bpc * 3 < bpp) {
11202 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11203 bpp, connector->base.display_info.bpc*3);
11204 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11205 }
11206
11207 /* Clamp bpp to 8 on screens without EDID 1.4 */
11208 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11209 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11210 bpp);
11211 pipe_config->pipe_bpp = 24;
11212 }
11213}
11214
4e53c2e0 11215static int
050f7aeb 11216compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11217 struct intel_crtc_state *pipe_config)
4e53c2e0 11218{
050f7aeb 11219 struct drm_device *dev = crtc->base.dev;
1486017f 11220 struct drm_atomic_state *state;
da3ced29
ACO		 11221 struct drm_connector *connector;
11222 struct drm_connector_state *connector_state;
1486017f 11223 int bpp, i;
4e53c2e0 11224
d328c9d7 11225 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11226 bpp = 10*3;
d328c9d7
DV		 11227 else if (INTEL_INFO(dev)->gen >= 5)
11228 bpp = 12*3;
11229 else
11230 bpp = 8*3;
11231
4e53c2e0 11232
4e53c2e0
DV		 11233 pipe_config->pipe_bpp = bpp;
11234
1486017f
ACO		 11235 state = pipe_config->base.state;
11236
4e53c2e0 11237 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11238 for_each_connector_in_state(state, connector, connector_state, i) {
11239 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11240 continue;
11241
da3ced29
ACO		 11242 connected_sink_compute_bpp(to_intel_connector(connector),
11243 pipe_config);
4e53c2e0
DV		 11244 }
11245
11246 return bpp;
11247}
11248
644db711
DV		 11249static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11250{
11251 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11252 "type: 0x%x flags: 0x%x\n",
1342830c 11253 mode->crtc_clock,
644db711
DV		 11254 mode->crtc_hdisplay, mode->crtc_hsync_start,
11255 mode->crtc_hsync_end, mode->crtc_htotal,
11256 mode->crtc_vdisplay, mode->crtc_vsync_start,
11257 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11258}
11259
c0b03411 11260static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11261 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11262 const char *context)
11263{
6a60cd87
CK		 11264 struct drm_device *dev = crtc->base.dev;
11265 struct drm_plane *plane;
11266 struct intel_plane *intel_plane;
11267 struct intel_plane_state *state;
11268 struct drm_framebuffer *fb;
11269
11270 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11271 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11272
11273 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11274 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11275 pipe_config->pipe_bpp, pipe_config->dither);
11276 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11277 pipe_config->has_pch_encoder,
11278 pipe_config->fdi_lanes,
11279 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11280 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11281 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11282 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11283 pipe_config->has_dp_encoder,
11284 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11285 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11286 pipe_config->dp_m_n.tu);
b95af8be
VK		 11287
11288 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11289 pipe_config->has_dp_encoder,
11290 pipe_config->dp_m2_n2.gmch_m,
11291 pipe_config->dp_m2_n2.gmch_n,
11292 pipe_config->dp_m2_n2.link_m,
11293 pipe_config->dp_m2_n2.link_n,
11294 pipe_config->dp_m2_n2.tu);
11295
55072d19
DV		 11296 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11297 pipe_config->has_audio,
11298 pipe_config->has_infoframe);
11299
c0b03411 11300 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11301 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11302 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11303 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11304 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11305 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11306 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11307 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11308 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11309 crtc->num_scalers,
11310 pipe_config->scaler_state.scaler_users,
11311 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11312 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11313 pipe_config->gmch_pfit.control,
11314 pipe_config->gmch_pfit.pgm_ratios,
11315 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11316 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11317 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11318 pipe_config->pch_pfit.size,
11319 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11320 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11321 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11322
415ff0f6
TU		 11323 if (IS_BROXTON(dev)) {
11324 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11325 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11326 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11327 pipe_config->ddi_pll_sel,
11328 pipe_config->dpll_hw_state.ebb0,
11329 pipe_config->dpll_hw_state.pll0,
11330 pipe_config->dpll_hw_state.pll1,
11331 pipe_config->dpll_hw_state.pll2,
11332 pipe_config->dpll_hw_state.pll3,
11333 pipe_config->dpll_hw_state.pll6,
11334 pipe_config->dpll_hw_state.pll8,
11335 pipe_config->dpll_hw_state.pcsdw12);
11336 } else if (IS_SKYLAKE(dev)) {
11337 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11338 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11339 pipe_config->ddi_pll_sel,
11340 pipe_config->dpll_hw_state.ctrl1,
11341 pipe_config->dpll_hw_state.cfgcr1,
11342 pipe_config->dpll_hw_state.cfgcr2);
11343 } else if (HAS_DDI(dev)) {
11344 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11345 pipe_config->ddi_pll_sel,
11346 pipe_config->dpll_hw_state.wrpll);
11347 } else {
11348 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11349 "fp0: 0x%x, fp1: 0x%x\n",
11350 pipe_config->dpll_hw_state.dpll,
11351 pipe_config->dpll_hw_state.dpll_md,
11352 pipe_config->dpll_hw_state.fp0,
11353 pipe_config->dpll_hw_state.fp1);
11354 }
11355
6a60cd87
CK		 11356 DRM_DEBUG_KMS("planes on this crtc\n");
11357 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11358 intel_plane = to_intel_plane(plane);
11359 if (intel_plane->pipe != crtc->pipe)
11360 continue;
11361
11362 state = to_intel_plane_state(plane->state);
11363 fb = state->base.fb;
11364 if (!fb) {
11365 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11366 "disabled, scaler_id = %d\n",
11367 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11368 plane->base.id, intel_plane->pipe,
11369 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11370 drm_plane_index(plane), state->scaler_id);
11371 continue;
11372 }
11373
11374 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11375 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11376 plane->base.id, intel_plane->pipe,
11377 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11378 drm_plane_index(plane));
11379 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11380 fb->base.id, fb->width, fb->height, fb->pixel_format);
11381 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11382 state->scaler_id,
11383 state->src.x1 >> 16, state->src.y1 >> 16,
11384 drm_rect_width(&state->src) >> 16,
11385 drm_rect_height(&state->src) >> 16,
11386 state->dst.x1, state->dst.y1,
11387 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11388 }
c0b03411
DV		 11389}
11390
bc079e8b
VS		 11391static bool encoders_cloneable(const struct intel_encoder *a,
11392 const struct intel_encoder *b)
accfc0c5 11393{
bc079e8b
VS		 11394 /* masks could be asymmetric, so check both ways */
11395 return a == b || (a->cloneable & (1 << b->type) &&
11396 b->cloneable & (1 << a->type));
11397}
11398
98a221da
ACO		 11399static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11400 struct intel_crtc *crtc,
bc079e8b
VS		 11401 struct intel_encoder *encoder)
11402{
bc079e8b 11403 struct intel_encoder *source_encoder;
da3ced29 11404 struct drm_connector *connector;
98a221da
ACO		 11405 struct drm_connector_state *connector_state;
11406 int i;
bc079e8b 11407
da3ced29 11408 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da 11409 if (connector_state->crtc != &crtc->base)
bc079e8b
VS		 11410 continue;
11411
98a221da
ACO		 11412 source_encoder =
11413 to_intel_encoder(connector_state->best_encoder);
bc079e8b
VS		 11414 if (!encoders_cloneable(encoder, source_encoder))
11415 return false;
11416 }
11417
11418 return true;
11419}
11420
98a221da
ACO		 11421static bool check_encoder_cloning(struct drm_atomic_state *state,
11422 struct intel_crtc *crtc)
bc079e8b 11423{
accfc0c5 11424 struct intel_encoder *encoder;
da3ced29 11425 struct drm_connector *connector;
98a221da
ACO		 11426 struct drm_connector_state *connector_state;
11427 int i;
accfc0c5 11428
da3ced29 11429 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da
ACO		 11430 if (connector_state->crtc != &crtc->base)
11431 continue;
11432
11433 encoder = to_intel_encoder(connector_state->best_encoder);
11434 if (!check_single_encoder_cloning(state, crtc, encoder))
bc079e8b 11435 return false;
accfc0c5
DV		 11436 }
11437
bc079e8b 11438 return true;
accfc0c5
DV		 11439}
11440
5448a00d 11441static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 11442{
5448a00d
ACO		 11443 struct drm_device *dev = state->dev;
11444 struct intel_encoder *encoder;
da3ced29 11445 struct drm_connector *connector;
5448a00d 11446 struct drm_connector_state *connector_state;
00f0b378 11447 unsigned int used_ports = 0;
5448a00d 11448 int i;
00f0b378
VS		 11449
11450 /*
11451 * Walk the connector list instead of the encoder
11452 * list to detect the problem on ddi platforms
11453 * where there's just one encoder per digital port.
11454 */
da3ced29 11455 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 11456 if (!connector_state->best_encoder)
00f0b378
VS		 11457 continue;
11458
5448a00d
ACO		 11459 encoder = to_intel_encoder(connector_state->best_encoder);
11460
11461 WARN_ON(!connector_state->crtc);
00f0b378
VS		 11462
11463 switch (encoder->type) {
11464 unsigned int port_mask;
11465 case INTEL_OUTPUT_UNKNOWN:
11466 if (WARN_ON(!HAS_DDI(dev)))
11467 break;
11468 case INTEL_OUTPUT_DISPLAYPORT:
11469 case INTEL_OUTPUT_HDMI:
11470 case INTEL_OUTPUT_EDP:
11471 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11472
11473 /* the same port mustn't appear more than once */
11474 if (used_ports & port_mask)
11475 return false;
11476
11477 used_ports |= port_mask;
11478 default:
11479 break;
11480 }
11481 }
11482
11483 return true;
11484}
11485
83a57153
ACO		 11486static void
11487clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11488{
11489 struct drm_crtc_state tmp_state;
663a3640 11490 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 11491 struct intel_dpll_hw_state dpll_hw_state;
11492 enum intel_dpll_id shared_dpll;
83a57153 11493
663a3640 11494 /* Clear only the intel specific part of the crtc state excluding scalers */
83a57153 11495 tmp_state = crtc_state->base;
663a3640 11496 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 11497 shared_dpll = crtc_state->shared_dpll;
11498 dpll_hw_state = crtc_state->dpll_hw_state;
11499
83a57153 11500 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 11501
83a57153 11502 crtc_state->base = tmp_state;
663a3640 11503 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 11504 crtc_state->shared_dpll = shared_dpll;
11505 crtc_state->dpll_hw_state = dpll_hw_state;
83a57153
ACO		 11506}
11507
548ee15b 11508static int
b8cecdf5 11509intel_modeset_pipe_config(struct drm_crtc *crtc,
548ee15b
ACO		 11510 struct drm_atomic_state *state,
11511 struct intel_crtc_state *pipe_config)
ee7b9f93 11512{
7758a113 11513 struct intel_encoder *encoder;
da3ced29 11514 struct drm_connector *connector;
0b901879 11515 struct drm_connector_state *connector_state;
d328c9d7 11516 int base_bpp, ret = -EINVAL;
0b901879 11517 int i;
e29c22c0 11518 bool retry = true;
ee7b9f93 11519
98a221da 11520 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
accfc0c5 11521 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
548ee15b 11522 return -EINVAL;
accfc0c5
DV		 11523 }
11524
5448a00d 11525 if (!check_digital_port_conflicts(state)) {
00f0b378 11526 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
548ee15b 11527 return -EINVAL;
00f0b378
VS		 11528 }
11529
83a57153 11530 clear_intel_crtc_state(pipe_config);
7758a113 11531
e143a21c
DV		 11532 pipe_config->cpu_transcoder =
11533 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 11534
2960bc9c
ID		 11535 /*
11536 * Sanitize sync polarity flags based on requested ones. If neither
11537 * positive or negative polarity is requested, treat this as meaning
11538 * negative polarity.
11539 */
2d112de7 11540 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11541 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 11542 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 11543
2d112de7 11544 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11545 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 11546 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 11547
050f7aeb
DV		 11548 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11549 * plane pixel format and any sink constraints into account. Returns the
11550 * source plane bpp so that dithering can be selected on mismatches
11551 * after encoders and crtc also have had their say. */
d328c9d7
DV		 11552 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11553 pipe_config);
11554 if (base_bpp < 0)
4e53c2e0
DV		 11555 goto fail;
11556
e41a56be
VS		 11557 /*
11558 * Determine the real pipe dimensions. Note that stereo modes can
11559 * increase the actual pipe size due to the frame doubling and
11560 * insertion of additional space for blanks between the frame. This
11561 * is stored in the crtc timings. We use the requested mode to do this
11562 * computation to clearly distinguish it from the adjusted mode, which
11563 * can be changed by the connectors in the below retry loop.
11564 */
2d112de7 11565 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 11566 &pipe_config->pipe_src_w,
11567 &pipe_config->pipe_src_h);
e41a56be 11568
e29c22c0 11569encoder_retry:
ef1b460d 11570 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 11571 pipe_config->port_clock = 0;
ef1b460d 11572 pipe_config->pixel_multiplier = 1;
ff9a6750 11573
135c81b8 11574 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 11575 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11576 CRTC_STEREO_DOUBLE);
135c81b8 11577
7758a113
DV		 11578 /* Pass our mode to the connectors and the CRTC to give them a chance to
11579 * adjust it according to limitations or connector properties, and also
11580 * a chance to reject the mode entirely.
47f1c6c9 11581 */
da3ced29 11582 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 11583 if (connector_state->crtc != crtc)
7758a113 11584 continue;
7ae89233 11585
0b901879
ACO		 11586 encoder = to_intel_encoder(connector_state->best_encoder);
11587
efea6e8e
DV		 11588 if (!(encoder->compute_config(encoder, pipe_config))) {
11589 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 11590 goto fail;
11591 }
ee7b9f93 11592 }
47f1c6c9 11593
ff9a6750
DV		 11594 /* Set default port clock if not overwritten by the encoder. Needs to be
11595 * done afterwards in case the encoder adjusts the mode. */
11596 if (!pipe_config->port_clock)
2d112de7 11597 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 11598 * pipe_config->pixel_multiplier;
ff9a6750 11599
a43f6e0f 11600 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 11601 if (ret < 0) {
7758a113
DV		 11602 DRM_DEBUG_KMS("CRTC fixup failed\n");
11603 goto fail;
ee7b9f93 11604 }
e29c22c0
DV		 11605
11606 if (ret == RETRY) {
11607 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11608 ret = -EINVAL;
11609 goto fail;
11610 }
11611
11612 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11613 retry = false;
11614 goto encoder_retry;
11615 }
11616
d328c9d7 11617 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 11618 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 11619 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 11620
548ee15b 11621 return 0;
7758a113 11622fail:
548ee15b 11623 return ret;
ee7b9f93 11624}
47f1c6c9 11625
ea9d758d 11626static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 11627{
ea9d758d 11628 struct drm_encoder *encoder;
f6e5b160 11629 struct drm_device *dev = crtc->dev;
f6e5b160 11630
ea9d758d
DV		 11631 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11632 if (encoder->crtc == crtc)
11633 return true;
11634
11635 return false;
11636}
11637
0a9ab303
ACO		 11638static bool
11639needs_modeset(struct drm_crtc_state *state)
11640{
11641 return state->mode_changed || state->active_changed;
11642}
11643
ea9d758d 11644static void
0a9ab303 11645intel_modeset_update_state(struct drm_atomic_state *state)
ea9d758d 11646{
0a9ab303 11647 struct drm_device *dev = state->dev;
ba41c0de 11648 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d 11649 struct intel_encoder *intel_encoder;
0a9ab303
ACO		 11650 struct drm_crtc *crtc;
11651 struct drm_crtc_state *crtc_state;
ea9d758d 11652 struct drm_connector *connector;
0a9ab303 11653 int i;
ea9d758d 11654
ba41c0de
DV		 11655 intel_shared_dpll_commit(dev_priv);
11656
b2784e15 11657 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 11658 if (!intel_encoder->base.crtc)
11659 continue;
11660
0a9ab303
ACO		 11661 for_each_crtc_in_state(state, crtc, crtc_state, i)
11662 if (crtc == intel_encoder->base.crtc)
11663 break;
11664
11665 if (crtc != intel_encoder->base.crtc)
11666 continue;
ea9d758d 11667
0a9ab303 11668 if (crtc_state->enable && needs_modeset(crtc_state))
ea9d758d
DV		 11669 intel_encoder->connectors_active = false;
11670 }
11671
a821fc46
ACO		 11672 drm_atomic_helper_swap_state(state->dev, state);
11673 intel_modeset_fixup_state(state);
ea9d758d 11674
7668851f 11675 /* Double check state. */
0a9ab303
ACO		 11676 for_each_crtc(dev, crtc) {
11677 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
ea9d758d
DV		 11678 }
11679
11680 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11681 if (!connector->encoder || !connector->encoder->crtc)
11682 continue;
11683
0a9ab303
ACO		 11684 for_each_crtc_in_state(state, crtc, crtc_state, i)
11685 if (crtc == connector->encoder->crtc)
11686 break;
11687
11688 if (crtc != connector->encoder->crtc)
11689 continue;
ea9d758d 11690
a821fc46 11691 if (crtc->state->enable && needs_modeset(crtc->state)) {
68d34720
DV		 11692 struct drm_property *dpms_property =
11693 dev->mode_config.dpms_property;
11694
ea9d758d 11695 connector->dpms = DRM_MODE_DPMS_ON;
662595df 11696 drm_object_property_set_value(&connector->base,
68d34720
DV		 11697 dpms_property,
11698 DRM_MODE_DPMS_ON);
ea9d758d
DV		 11699
11700 intel_encoder = to_intel_encoder(connector->encoder);
11701 intel_encoder->connectors_active = true;
11702 }
11703 }
11704
11705}
11706
3bd26263 11707static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 11708{
3bd26263 11709 int diff;
f1f644dc
JB		 11710
11711 if (clock1 == clock2)
11712 return true;
11713
11714 if (!clock1 || !clock2)
11715 return false;
11716
11717 diff = abs(clock1 - clock2);
11718
11719 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11720 return true;
11721
11722 return false;
11723}
11724
25c5b266
DV		 11725#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11726 list_for_each_entry((intel_crtc), \
11727 &(dev)->mode_config.crtc_list, \
11728 base.head) \
0973f18f 11729 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 11730
0e8ffe1b 11731static bool
2fa2fe9a 11732intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 11733 struct intel_crtc_state *current_config,
11734 struct intel_crtc_state *pipe_config)
0e8ffe1b 11735{
66e985c0
DV		 11736#define PIPE_CONF_CHECK_X(name) \
11737 if (current_config->name != pipe_config->name) { \
11738 DRM_ERROR("mismatch in " #name " " \
11739 "(expected 0x%08x, found 0x%08x)\n", \
11740 current_config->name, \
11741 pipe_config->name); \
11742 return false; \
11743 }
11744
08a24034
DV		 11745#define PIPE_CONF_CHECK_I(name) \
11746 if (current_config->name != pipe_config->name) { \
11747 DRM_ERROR("mismatch in " #name " " \
11748 "(expected %i, found %i)\n", \
11749 current_config->name, \
11750 pipe_config->name); \
11751 return false; \
88adfff1
DV		 11752 }
11753
b95af8be
VK		 11754/* This is required for BDW+ where there is only one set of registers for
11755 * switching between high and low RR.
11756 * This macro can be used whenever a comparison has to be made between one
11757 * hw state and multiple sw state variables.
11758 */
11759#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11760 if ((current_config->name != pipe_config->name) && \
11761 (current_config->alt_name != pipe_config->name)) { \
11762 DRM_ERROR("mismatch in " #name " " \
11763 "(expected %i or %i, found %i)\n", \
11764 current_config->name, \
11765 current_config->alt_name, \
11766 pipe_config->name); \
11767 return false; \
11768 }
11769
1bd1bd80
DV		 11770#define PIPE_CONF_CHECK_FLAGS(name, mask) \
11771 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 11772 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 11773 "(expected %i, found %i)\n", \
11774 current_config->name & (mask), \
11775 pipe_config->name & (mask)); \
11776 return false; \
11777 }
11778
5e550656
VS		 11779#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11780 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11781 DRM_ERROR("mismatch in " #name " " \
11782 "(expected %i, found %i)\n", \
11783 current_config->name, \
11784 pipe_config->name); \
11785 return false; \
11786 }
11787
bb760063
DV		 11788#define PIPE_CONF_QUIRK(quirk) \
11789 ((current_config->quirks | pipe_config->quirks) & (quirk))
11790
eccb140b
DV		 11791 PIPE_CONF_CHECK_I(cpu_transcoder);
11792
08a24034
DV		 11793 PIPE_CONF_CHECK_I(has_pch_encoder);
11794 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 11795 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
11796 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
11797 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
11798 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
11799 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 11800
eb14cb74 11801 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 11802
11803 if (INTEL_INFO(dev)->gen < 8) {
11804 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
11805 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
11806 PIPE_CONF_CHECK_I(dp_m_n.link_m);
11807 PIPE_CONF_CHECK_I(dp_m_n.link_n);
11808 PIPE_CONF_CHECK_I(dp_m_n.tu);
11809
11810 if (current_config->has_drrs) {
11811 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
11812 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
11813 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
11814 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
11815 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
11816 }
11817 } else {
11818 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
11819 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
11820 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
11821 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
11822 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
11823 }
eb14cb74 11824
2d112de7
ACO		 11825 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
11826 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
11827 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
11828 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
11829 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
11830 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 11831
2d112de7
ACO		 11832 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
11833 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
11834 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
11835 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
11836 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
11837 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 11838
c93f54cf 11839 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 11840 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 11841 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
11842 IS_VALLEYVIEW(dev))
11843 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 11844 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 11845
9ed109a7
DV		 11846 PIPE_CONF_CHECK_I(has_audio);
11847
2d112de7 11848 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 11849 DRM_MODE_FLAG_INTERLACE);
11850
bb760063 11851 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 11852 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11853 DRM_MODE_FLAG_PHSYNC);
2d112de7 11854 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11855 DRM_MODE_FLAG_NHSYNC);
2d112de7 11856 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 11857 DRM_MODE_FLAG_PVSYNC);
2d112de7 11858 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 11859 DRM_MODE_FLAG_NVSYNC);
11860 }
045ac3b5 11861
37327abd
VS		 11862 PIPE_CONF_CHECK_I(pipe_src_w);
11863 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 11864
9953599b
DV		 11865 /*
11866 * FIXME: BIOS likes to set up a cloned config with lvds+external
11867 * screen. Since we don't yet re-compute the pipe config when moving
11868 * just the lvds port away to another pipe the sw tracking won't match.
11869 *
11870 * Proper atomic modesets with recomputed global state will fix this.
11871 * Until then just don't check gmch state for inherited modes.
11872 */
11873 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
11874 PIPE_CONF_CHECK_I(gmch_pfit.control);
11875 /* pfit ratios are autocomputed by the hw on gen4+ */
11876 if (INTEL_INFO(dev)->gen < 4)
11877 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
11878 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
11879 }
11880
fd4daa9c
CW		 11881 PIPE_CONF_CHECK_I(pch_pfit.enabled);
11882 if (current_config->pch_pfit.enabled) {
11883 PIPE_CONF_CHECK_I(pch_pfit.pos);
11884 PIPE_CONF_CHECK_I(pch_pfit.size);
11885 }
2fa2fe9a 11886
a1b2278e
CK		 11887 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
11888
e59150dc
JB		 11889 /* BDW+ don't expose a synchronous way to read the state */
11890 if (IS_HASWELL(dev))
11891 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 11892
282740f7
VS		 11893 PIPE_CONF_CHECK_I(double_wide);
11894
26804afd
DV		 11895 PIPE_CONF_CHECK_X(ddi_pll_sel);
11896
c0d43d62 11897 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 11898 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 11899 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 11900 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
11901 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 11902 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 11903 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
11904 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
11905 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 11906
42571aef
VS		 11907 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
11908 PIPE_CONF_CHECK_I(pipe_bpp);
11909
2d112de7 11910 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 11911 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 11912
66e985c0 11913#undef PIPE_CONF_CHECK_X
08a24034 11914#undef PIPE_CONF_CHECK_I
b95af8be 11915#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 11916#undef PIPE_CONF_CHECK_FLAGS
5e550656 11917#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 11918#undef PIPE_CONF_QUIRK
88adfff1 11919
0e8ffe1b
DV		 11920 return true;
11921}
11922
08db6652
DL		 11923static void check_wm_state(struct drm_device *dev)
11924{
11925 struct drm_i915_private *dev_priv = dev->dev_private;
11926 struct skl_ddb_allocation hw_ddb, *sw_ddb;
11927 struct intel_crtc *intel_crtc;
11928 int plane;
11929
11930 if (INTEL_INFO(dev)->gen < 9)
11931 return;
11932
11933 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
11934 sw_ddb = &dev_priv->wm.skl_hw.ddb;
11935
11936 for_each_intel_crtc(dev, intel_crtc) {
11937 struct skl_ddb_entry *hw_entry, *sw_entry;
11938 const enum pipe pipe = intel_crtc->pipe;
11939
11940 if (!intel_crtc->active)
11941 continue;
11942
11943 /* planes */
dd740780 11944 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 11945 hw_entry = &hw_ddb.plane[pipe][plane];
11946 sw_entry = &sw_ddb->plane[pipe][plane];
11947
11948 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11949 continue;
11950
11951 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
11952 "(expected (%u,%u), found (%u,%u))\n",
11953 pipe_name(pipe), plane + 1,
11954 sw_entry->start, sw_entry->end,
11955 hw_entry->start, hw_entry->end);
11956 }
11957
11958 /* cursor */
11959 hw_entry = &hw_ddb.cursor[pipe];
11960 sw_entry = &sw_ddb->cursor[pipe];
11961
11962 if (skl_ddb_entry_equal(hw_entry, sw_entry))
11963 continue;
11964
11965 DRM_ERROR("mismatch in DDB state pipe %c cursor "
11966 "(expected (%u,%u), found (%u,%u))\n",
11967 pipe_name(pipe),
11968 sw_entry->start, sw_entry->end,
11969 hw_entry->start, hw_entry->end);
11970 }
11971}
11972
91d1b4bd
DV		 11973static void
11974check_connector_state(struct drm_device *dev)
8af6cf88 11975{
8af6cf88
DV		 11976 struct intel_connector *connector;
11977
3a3371ff 11978 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11979 /* This also checks the encoder/connector hw state with the
11980 * ->get_hw_state callbacks. */
11981 intel_connector_check_state(connector);
11982
e2c719b7 11983 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 11984 "connector's staged encoder doesn't match current encoder\n");
11985 }
91d1b4bd
DV		 11986}
11987
11988static void
11989check_encoder_state(struct drm_device *dev)
11990{
11991 struct intel_encoder *encoder;
11992 struct intel_connector *connector;
8af6cf88 11993
b2784e15 11994 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 11995 bool enabled = false;
11996 bool active = false;
11997 enum pipe pipe, tracked_pipe;
11998
11999 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12000 encoder->base.base.id,
8e329a03 12001 encoder->base.name);
8af6cf88 12002
e2c719b7 12003 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 12004 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 12005 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 12006 "encoder's active_connectors set, but no crtc\n");
12007
3a3371ff 12008 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12009 if (connector->base.encoder != &encoder->base)
12010 continue;
12011 enabled = true;
12012 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12013 active = true;
12014 }
0e32b39c
DA		 12015 /*
12016 * for MST connectors if we unplug the connector is gone
12017 * away but the encoder is still connected to a crtc
12018 * until a modeset happens in response to the hotplug.
12019 */
12020 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12021 continue;
12022
e2c719b7 12023 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12024 "encoder's enabled state mismatch "
12025 "(expected %i, found %i)\n",
12026 !!encoder->base.crtc, enabled);
e2c719b7 12027 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 12028 "active encoder with no crtc\n");
12029
e2c719b7 12030 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 12031 "encoder's computed active state doesn't match tracked active state "
12032 "(expected %i, found %i)\n", active, encoder->connectors_active);
12033
12034 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 12035 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 12036 "encoder's hw state doesn't match sw tracking "
12037 "(expected %i, found %i)\n",
12038 encoder->connectors_active, active);
12039
12040 if (!encoder->base.crtc)
12041 continue;
12042
12043 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 12044 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 12045 "active encoder's pipe doesn't match"
12046 "(expected %i, found %i)\n",
12047 tracked_pipe, pipe);
12048
12049 }
91d1b4bd
DV		 12050}
12051
12052static void
12053check_crtc_state(struct drm_device *dev)
12054{
fbee40df 12055 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12056 struct intel_crtc *crtc;
12057 struct intel_encoder *encoder;
5cec258b 12058 struct intel_crtc_state pipe_config;
8af6cf88 12059
d3fcc808 12060 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 12061 bool enabled = false;
12062 bool active = false;
12063
045ac3b5
JB		 12064 memset(&pipe_config, 0, sizeof(pipe_config));
12065
8af6cf88
DV		 12066 DRM_DEBUG_KMS("[CRTC:%d]\n",
12067 crtc->base.base.id);
12068
83d65738 12069 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 12070 "active crtc, but not enabled in sw tracking\n");
12071
b2784e15 12072 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12073 if (encoder->base.crtc != &crtc->base)
12074 continue;
12075 enabled = true;
12076 if (encoder->connectors_active)
12077 active = true;
12078 }
6c49f241 12079
e2c719b7 12080 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 12081 "crtc's computed active state doesn't match tracked active state "
12082 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12083 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12084 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 12085 "(expected %i, found %i)\n", enabled,
12086 crtc->base.state->enable);
8af6cf88 12087
0e8ffe1b
DV		 12088 active = dev_priv->display.get_pipe_config(crtc,
12089 &pipe_config);
d62cf62a 12090
b6b5d049
VS		 12091 /* hw state is inconsistent with the pipe quirk */
12092 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12093 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 12094 active = crtc->active;
12095
b2784e15 12096 for_each_intel_encoder(dev, encoder) {
3eaba51c 12097 enum pipe pipe;
6c49f241
DV		 12098 if (encoder->base.crtc != &crtc->base)
12099 continue;
1d37b689 12100 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 12101 encoder->get_config(encoder, &pipe_config);
12102 }
12103
e2c719b7 12104 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 12105 "crtc active state doesn't match with hw state "
12106 "(expected %i, found %i)\n", crtc->active, active);
12107
c0b03411 12108 if (active &&
6e3c9717 12109 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 12110 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 12111 intel_dump_pipe_config(crtc, &pipe_config,
12112 "[hw state]");
6e3c9717 12113 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12114 "[sw state]");
12115 }
8af6cf88
DV		 12116 }
12117}
12118
91d1b4bd
DV		 12119static void
12120check_shared_dpll_state(struct drm_device *dev)
12121{
fbee40df 12122 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12123 struct intel_crtc *crtc;
12124 struct intel_dpll_hw_state dpll_hw_state;
12125 int i;
5358901f
DV		 12126
12127 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12128 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12129 int enabled_crtcs = 0, active_crtcs = 0;
12130 bool active;
12131
12132 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12133
12134 DRM_DEBUG_KMS("%s\n", pll->name);
12135
12136 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12137
e2c719b7 12138 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12139 "more active pll users than references: %i vs %i\n",
3e369b76 12140 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12141 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12142 "pll in active use but not on in sw tracking\n");
e2c719b7 12143 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12144 "pll in on but not on in use in sw tracking\n");
e2c719b7 12145 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12146 "pll on state mismatch (expected %i, found %i)\n",
12147 pll->on, active);
12148
d3fcc808 12149 for_each_intel_crtc(dev, crtc) {
83d65738 12150 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12151 enabled_crtcs++;
12152 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12153 active_crtcs++;
12154 }
e2c719b7 12155 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12156 "pll active crtcs mismatch (expected %i, found %i)\n",
12157 pll->active, active_crtcs);
e2c719b7 12158 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12159 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12160 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12161
e2c719b7 12162 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12163 sizeof(dpll_hw_state)),
12164 "pll hw state mismatch\n");
5358901f 12165 }
8af6cf88
DV		 12166}
12167
91d1b4bd
DV		 12168void
12169intel_modeset_check_state(struct drm_device *dev)
12170{
08db6652 12171 check_wm_state(dev);
91d1b4bd
DV		 12172 check_connector_state(dev);
12173 check_encoder_state(dev);
12174 check_crtc_state(dev);
12175 check_shared_dpll_state(dev);
12176}
12177
5cec258b 12178void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12179 int dotclock)
12180{
12181 /*
12182 * FDI already provided one idea for the dotclock.
12183 * Yell if the encoder disagrees.
12184 */
2d112de7 12185 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12186 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12187 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12188}
12189
80715b2f
VS		 12190static void update_scanline_offset(struct intel_crtc *crtc)
12191{
12192 struct drm_device *dev = crtc->base.dev;
12193
12194 /*
12195 * The scanline counter increments at the leading edge of hsync.
12196 *
12197 * On most platforms it starts counting from vtotal-1 on the
12198 * first active line. That means the scanline counter value is
12199 * always one less than what we would expect. Ie. just after
12200 * start of vblank, which also occurs at start of hsync (on the
12201 * last active line), the scanline counter will read vblank_start-1.
12202 *
12203 * On gen2 the scanline counter starts counting from 1 instead
12204 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12205 * to keep the value positive), instead of adding one.
12206 *
12207 * On HSW+ the behaviour of the scanline counter depends on the output
12208 * type. For DP ports it behaves like most other platforms, but on HDMI
12209 * there's an extra 1 line difference. So we need to add two instead of
12210 * one to the value.
12211 */
12212 if (IS_GEN2(dev)) {
6e3c9717 12213 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12214 int vtotal;
12215
12216 vtotal = mode->crtc_vtotal;
12217 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12218 vtotal /= 2;
12219
12220 crtc->scanline_offset = vtotal - 1;
12221 } else if (HAS_DDI(dev) &&
409ee761 12222 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12223 crtc->scanline_offset = 2;
12224 } else
12225 crtc->scanline_offset = 1;
12226}
12227
5cec258b 12228static struct intel_crtc_state *
7f27126e 12229intel_modeset_compute_config(struct drm_crtc *crtc,
0a9ab303 12230 struct drm_atomic_state *state)
7f27126e 12231{
548ee15b 12232 struct intel_crtc_state *pipe_config;
0b901879
ACO		 12233 int ret = 0;
12234
12235 ret = drm_atomic_add_affected_connectors(state, crtc);
12236 if (ret)
12237 return ERR_PTR(ret);
7f27126e 12238
8c7b5ccb
ACO		 12239 ret = drm_atomic_helper_check_modeset(state->dev, state);
12240 if (ret)
12241 return ERR_PTR(ret);
7f27126e 12242
7f27126e
JB		 12243 /*
12244 * Note this needs changes when we start tracking multiple modes
12245 * and crtcs. At that point we'll need to compute the whole config
12246 * (i.e. one pipe_config for each crtc) rather than just the one
12247 * for this crtc.
12248 */
548ee15b
ACO		 12249 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12250 if (IS_ERR(pipe_config))
12251 return pipe_config;
83a57153 12252
4fed33f6 12253 if (!pipe_config->base.enable)
548ee15b 12254 return pipe_config;
7f27126e 12255
8c7b5ccb 12256 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
548ee15b
ACO		 12257 if (ret)
12258 return ERR_PTR(ret);
12259
8d8c9b51
ACO		 12260 /* Check things that can only be changed through modeset */
12261 if (pipe_config->has_audio !=
12262 to_intel_crtc(crtc)->config->has_audio)
12263 pipe_config->base.mode_changed = true;
12264
12265 /*
12266 * Note we have an issue here with infoframes: current code
12267 * only updates them on the full mode set path per hw
12268 * requirements. So here we should be checking for any
12269 * required changes and forcing a mode set.
12270 */
12271
548ee15b 12272 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
db7542dd 12273
8c7b5ccb
ACO		 12274 ret = drm_atomic_helper_check_planes(state->dev, state);
12275 if (ret)
12276 return ERR_PTR(ret);
12277
548ee15b 12278 return pipe_config;
7f27126e
JB		 12279}
12280
0a9ab303 12281static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
ed6739ef 12282{
225da59b 12283 struct drm_device *dev = state->dev;
ed6739ef 12284 struct drm_i915_private *dev_priv = to_i915(dev);
0a9ab303 12285 unsigned clear_pipes = 0;
ed6739ef 12286 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12287 struct intel_crtc_state *intel_crtc_state;
12288 struct drm_crtc *crtc;
12289 struct drm_crtc_state *crtc_state;
ed6739ef 12290 int ret = 0;
0a9ab303 12291 int i;
ed6739ef
ACO		 12292
12293 if (!dev_priv->display.crtc_compute_clock)
12294 return 0;
12295
0a9ab303
ACO		 12296 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12297 intel_crtc = to_intel_crtc(crtc);
4978cc93 12298 intel_crtc_state = to_intel_crtc_state(crtc_state);
0a9ab303 12299
4978cc93 12300 if (needs_modeset(crtc_state)) {
0a9ab303 12301 clear_pipes |= 1 << intel_crtc->pipe;
4978cc93 12302 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
4978cc93 12303 }
0a9ab303
ACO		 12304 }
12305
ed6739ef
ACO		 12306 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12307 if (ret)
12308 goto done;
12309
0a9ab303
ACO		 12310 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12311 if (!needs_modeset(crtc_state) || !crtc_state->enable)
225da59b
ACO		 12312 continue;
12313
0a9ab303
ACO		 12314 intel_crtc = to_intel_crtc(crtc);
12315 intel_crtc_state = to_intel_crtc_state(crtc_state);
12316
ed6739ef 12317 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
0a9ab303 12318 intel_crtc_state);
ed6739ef
ACO		 12319 if (ret) {
12320 intel_shared_dpll_abort_config(dev_priv);
12321 goto done;
12322 }
12323 }
12324
12325done:
12326 return ret;
12327}
12328
054518dd
ACO		 12329/* Code that should eventually be part of atomic_check() */
12330static int __intel_set_mode_checks(struct drm_atomic_state *state)
12331{
12332 struct drm_device *dev = state->dev;
12333 int ret;
12334
12335 /*
12336 * See if the config requires any additional preparation, e.g.
12337 * to adjust global state with pipes off. We need to do this
12338 * here so we can get the modeset_pipe updated config for the new
12339 * mode set on this crtc. For other crtcs we need to use the
12340 * adjusted_mode bits in the crtc directly.
12341 */
12342 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12343 ret = valleyview_modeset_global_pipes(state);
12344 if (ret)
12345 return ret;
12346 }
12347
12348 ret = __intel_set_mode_setup_plls(state);
12349 if (ret)
12350 return ret;
12351
12352 return 0;
12353}
12354
0a9ab303 12355static int __intel_set_mode(struct drm_crtc *modeset_crtc,
0a9ab303 12356 struct intel_crtc_state *pipe_config)
a6778b3c 12357{
0a9ab303 12358 struct drm_device *dev = modeset_crtc->dev;
fbee40df 12359 struct drm_i915_private *dev_priv = dev->dev_private;
304603f4 12360 struct drm_atomic_state *state = pipe_config->base.state;
0a9ab303
ACO		 12361 struct drm_crtc *crtc;
12362 struct drm_crtc_state *crtc_state;
c0c36b94 12363 int ret = 0;
0a9ab303 12364 int i;
a6778b3c 12365
054518dd
ACO		 12366 ret = __intel_set_mode_checks(state);
12367 if (ret < 0)
12368 return ret;
12369
d4afb8cc
ACO		 12370 ret = drm_atomic_helper_prepare_planes(dev, state);
12371 if (ret)
12372 return ret;
12373
0a9ab303
ACO		 12374 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12375 if (!needs_modeset(crtc_state))
12376 continue;
460da916 12377
0a9ab303
ACO		 12378 if (!crtc_state->enable) {
12379 intel_crtc_disable(crtc);
12380 } else if (crtc->state->enable) {
12381 intel_crtc_disable_planes(crtc);
12382 dev_priv->display.crtc_disable(crtc);
ce22dba9 12383 }
ea9d758d 12384 }
a6778b3c 12385
6c4c86f5
DV		 12386 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12387 * to set it here already despite that we pass it down the callchain.
7f27126e
JB		 12388 *
12389 * Note we'll need to fix this up when we start tracking multiple
12390 * pipes; here we assume a single modeset_pipe and only track the
12391 * single crtc and mode.
f6e5b160 12392 */
0a9ab303 12393 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
8c7b5ccb 12394 modeset_crtc->mode = pipe_config->base.mode;
c326c0a9
VS		 12395
12396 /*
12397 * Calculate and store various constants which
12398 * are later needed by vblank and swap-completion
12399 * timestamping. They are derived from true hwmode.
12400 */
0a9ab303 12401 drm_calc_timestamping_constants(modeset_crtc,
2d112de7 12402 &pipe_config->base.adjusted_mode);
b8cecdf5 12403 }
7758a113 12404
ea9d758d
DV		 12405 /* Only after disabling all output pipelines that will be changed can we
12406 * update the the output configuration. */
0a9ab303 12407 intel_modeset_update_state(state);
f6e5b160 12408
a821fc46
ACO		 12409 /* The state has been swaped above, so state actually contains the
12410 * old state now. */
12411
304603f4 12412 modeset_update_crtc_power_domains(state);
47fab737 12413
d4afb8cc 12414 drm_atomic_helper_commit_planes(dev, state);
a6778b3c
DV		 12415
12416 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 12417 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a821fc46 12418 if (!needs_modeset(crtc->state) || !crtc->state->enable)
0a9ab303
ACO		 12419 continue;
12420
12421 update_scanline_offset(to_intel_crtc(crtc));
80715b2f 12422
0a9ab303
ACO		 12423 dev_priv->display.crtc_enable(crtc);
12424 intel_crtc_enable_planes(crtc);
80715b2f 12425 }
a6778b3c 12426
a6778b3c 12427 /* FIXME: add subpixel order */
83a57153 12428
d4afb8cc
ACO		 12429 drm_atomic_helper_cleanup_planes(dev, state);
12430
2bfb4627
ACO		 12431 drm_atomic_state_free(state);
12432
9eb45f22 12433 return 0;
f6e5b160
CW		 12434}
12435
0a9ab303 12436static int intel_set_mode_with_config(struct drm_crtc *crtc,
0a9ab303 12437 struct intel_crtc_state *pipe_config)
f30da187
DV		 12438{
12439 int ret;
12440
8c7b5ccb 12441 ret = __intel_set_mode(crtc, pipe_config);
f30da187
DV		 12442
12443 if (ret == 0)
12444 intel_modeset_check_state(crtc->dev);
12445
12446 return ret;
12447}
12448
7f27126e 12449static int intel_set_mode(struct drm_crtc *crtc,
83a57153 12450 struct drm_atomic_state *state)
7f27126e 12451{
5cec258b 12452 struct intel_crtc_state *pipe_config;
83a57153 12453 int ret = 0;
7f27126e 12454
8c7b5ccb 12455 pipe_config = intel_modeset_compute_config(crtc, state);
83a57153
ACO		 12456 if (IS_ERR(pipe_config)) {
12457 ret = PTR_ERR(pipe_config);
12458 goto out;
12459 }
12460
8c7b5ccb 12461 ret = intel_set_mode_with_config(crtc, pipe_config);
83a57153
ACO		 12462 if (ret)
12463 goto out;
7f27126e 12464
83a57153
ACO		 12465out:
12466 return ret;
7f27126e
JB		 12467}
12468
c0c36b94
CW		 12469void intel_crtc_restore_mode(struct drm_crtc *crtc)
12470{
83a57153
ACO		 12471 struct drm_device *dev = crtc->dev;
12472 struct drm_atomic_state *state;
4be07317 12473 struct intel_crtc *intel_crtc;
83a57153
ACO		 12474 struct intel_encoder *encoder;
12475 struct intel_connector *connector;
12476 struct drm_connector_state *connector_state;
4be07317 12477 struct intel_crtc_state *crtc_state;
2bfb4627 12478 int ret;
83a57153
ACO		 12479
12480 state = drm_atomic_state_alloc(dev);
12481 if (!state) {
12482 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12483 crtc->base.id);
12484 return;
12485 }
12486
12487 state->acquire_ctx = dev->mode_config.acquire_ctx;
12488
12489 /* The force restore path in the HW readout code relies on the staged
12490 * config still keeping the user requested config while the actual
12491 * state has been overwritten by the configuration read from HW. We
12492 * need to copy the staged config to the atomic state, otherwise the
12493 * mode set will just reapply the state the HW is already in. */
12494 for_each_intel_encoder(dev, encoder) {
12495 if (&encoder->new_crtc->base != crtc)
12496 continue;
12497
12498 for_each_intel_connector(dev, connector) {
12499 if (connector->new_encoder != encoder)
12500 continue;
12501
12502 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12503 if (IS_ERR(connector_state)) {
12504 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12505 connector->base.base.id,
12506 connector->base.name,
12507 PTR_ERR(connector_state));
12508 continue;
12509 }
12510
12511 connector_state->crtc = crtc;
12512 connector_state->best_encoder = &encoder->base;
12513 }
12514 }
12515
4be07317
ACO		 12516 for_each_intel_crtc(dev, intel_crtc) {
12517 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
12518 continue;
12519
12520 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12521 if (IS_ERR(crtc_state)) {
12522 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12523 intel_crtc->base.base.id,
12524 PTR_ERR(crtc_state));
12525 continue;
12526 }
12527
49d6fa21
ML		 12528 crtc_state->base.active = crtc_state->base.enable =
12529 intel_crtc->new_enabled;
8c7b5ccb
ACO		 12530
12531 if (&intel_crtc->base == crtc)
12532 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
4be07317
ACO		 12533 }
12534
d3a40d1b
ACO		 12535 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
12536 crtc->primary->fb, crtc->x, crtc->y);
12537
2bfb4627
ACO		 12538 ret = intel_set_mode(crtc, state);
12539 if (ret)
12540 drm_atomic_state_free(state);
c0c36b94
CW		 12541}
12542
25c5b266
DV		 12543#undef for_each_intel_crtc_masked
12544
b7885264
ACO		 12545static bool intel_connector_in_mode_set(struct intel_connector *connector,
12546 struct drm_mode_set *set)
12547{
12548 int ro;
12549
12550 for (ro = 0; ro < set->num_connectors; ro++)
12551 if (set->connectors[ro] == &connector->base)
12552 return true;
12553
12554 return false;
12555}
12556
2e431051 12557static int
9a935856
DV		 12558intel_modeset_stage_output_state(struct drm_device *dev,
12559 struct drm_mode_set *set,
944b0c76 12560 struct drm_atomic_state *state)
50f56119 12561{
9a935856 12562 struct intel_connector *connector;
d5432a9d 12563 struct drm_connector *drm_connector;
944b0c76 12564 struct drm_connector_state *connector_state;
d5432a9d
ACO		 12565 struct drm_crtc *crtc;
12566 struct drm_crtc_state *crtc_state;
12567 int i, ret;
50f56119 12568
9abdda74 12569 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 12570 * of connectors. For paranoia, double-check this. */
12571 WARN_ON(!set->fb && (set->num_connectors != 0));
12572 WARN_ON(set->fb && (set->num_connectors == 0));
12573
3a3371ff 12574 for_each_intel_connector(dev, connector) {
b7885264
ACO		 12575 bool in_mode_set = intel_connector_in_mode_set(connector, set);
12576
d5432a9d
ACO		 12577 if (!in_mode_set && connector->base.state->crtc != set->crtc)
12578 continue;
12579
12580 connector_state =
12581 drm_atomic_get_connector_state(state, &connector->base);
12582 if (IS_ERR(connector_state))
12583 return PTR_ERR(connector_state);
12584
b7885264
ACO		 12585 if (in_mode_set) {
12586 int pipe = to_intel_crtc(set->crtc)->pipe;
d5432a9d
ACO		 12587 connector_state->best_encoder =
12588 &intel_find_encoder(connector, pipe)->base;
50f56119
DV		 12589 }
12590
d5432a9d 12591 if (connector->base.state->crtc != set->crtc)
b7885264
ACO		 12592 continue;
12593
9a935856
DV		 12594 /* If we disable the crtc, disable all its connectors. Also, if
12595 * the connector is on the changing crtc but not on the new
12596 * connector list, disable it. */
b7885264 12597 if (!set->fb || !in_mode_set) {
d5432a9d 12598 connector_state->best_encoder = NULL;
9a935856
DV		 12599
12600 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12601 connector->base.base.id,
c23cc417 12602 connector->base.name);
9a935856 12603 }
50f56119 12604 }
9a935856 12605 /* connector->new_encoder is now updated for all connectors. */
50f56119 12606
d5432a9d
ACO		 12607 for_each_connector_in_state(state, drm_connector, connector_state, i) {
12608 connector = to_intel_connector(drm_connector);
12609
12610 if (!connector_state->best_encoder) {
12611 ret = drm_atomic_set_crtc_for_connector(connector_state,
12612 NULL);
12613 if (ret)
12614 return ret;
7668851f 12615
50f56119 12616 continue;
d5432a9d 12617 }
50f56119 12618
d5432a9d
ACO		 12619 if (intel_connector_in_mode_set(connector, set)) {
12620 struct drm_crtc *crtc = connector->base.state->crtc;
12621
12622 /* If this connector was in a previous crtc, add it
12623 * to the state. We might need to disable it. */
12624 if (crtc) {
12625 crtc_state =
12626 drm_atomic_get_crtc_state(state, crtc);
12627 if (IS_ERR(crtc_state))
12628 return PTR_ERR(crtc_state);
12629 }
12630
12631 ret = drm_atomic_set_crtc_for_connector(connector_state,
12632 set->crtc);
12633 if (ret)
12634 return ret;
12635 }
50f56119
DV		 12636
12637 /* Make sure the new CRTC will work with the encoder */
d5432a9d
ACO		 12638 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
12639 connector_state->crtc)) {
5e2b584e 12640 return -EINVAL;
50f56119 12641 }
944b0c76 12642
9a935856
DV		 12643 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12644 connector->base.base.id,
c23cc417 12645 connector->base.name,
d5432a9d 12646 connector_state->crtc->base.id);
944b0c76 12647
d5432a9d
ACO		 12648 if (connector_state->best_encoder != &connector->encoder->base)
12649 connector->encoder =
12650 to_intel_encoder(connector_state->best_encoder);
0e32b39c 12651 }
7668851f 12652
d5432a9d 12653 for_each_crtc_in_state(state, crtc, crtc_state, i) {
49d6fa21
ML		 12654 bool has_connectors;
12655
d5432a9d
ACO		 12656 ret = drm_atomic_add_affected_connectors(state, crtc);
12657 if (ret)
12658 return ret;
4be07317 12659
49d6fa21
ML		 12660 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
12661 if (has_connectors != crtc_state->enable)
12662 crtc_state->enable =
12663 crtc_state->active = has_connectors;
7668851f
VS		 12664 }
12665
8c7b5ccb
ACO		 12666 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
12667 set->fb, set->x, set->y);
12668 if (ret)
12669 return ret;
12670
12671 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
12672 if (IS_ERR(crtc_state))
12673 return PTR_ERR(crtc_state);
12674
12675 if (set->mode)
12676 drm_mode_copy(&crtc_state->mode, set->mode);
12677
12678 if (set->num_connectors)
12679 crtc_state->active = true;
12680
2e431051
DV		 12681 return 0;
12682}
12683
bb546623
ACO		 12684static bool primary_plane_visible(struct drm_crtc *crtc)
12685{
12686 struct intel_plane_state *plane_state =
12687 to_intel_plane_state(crtc->primary->state);
12688
12689 return plane_state->visible;
12690}
12691
2e431051
DV		 12692static int intel_crtc_set_config(struct drm_mode_set *set)
12693{
12694 struct drm_device *dev;
83a57153 12695 struct drm_atomic_state *state = NULL;
5cec258b 12696 struct intel_crtc_state *pipe_config;
bb546623 12697 bool primary_plane_was_visible;
2e431051 12698 int ret;
2e431051 12699
8d3e375e
DV		 12700 BUG_ON(!set);
12701 BUG_ON(!set->crtc);
12702 BUG_ON(!set->crtc->helper_private);
2e431051 12703
7e53f3a4
DV		 12704 /* Enforce sane interface api - has been abused by the fb helper. */
12705 BUG_ON(!set->mode && set->fb);
12706 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 12707
2e431051
DV		 12708 if (set->fb) {
12709 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12710 set->crtc->base.id, set->fb->base.id,
12711 (int)set->num_connectors, set->x, set->y);
12712 } else {
12713 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 12714 }
12715
12716 dev = set->crtc->dev;
12717
83a57153 12718 state = drm_atomic_state_alloc(dev);
7cbf41d6
ACO		 12719 if (!state)
12720 return -ENOMEM;
83a57153
ACO		 12721
12722 state->acquire_ctx = dev->mode_config.acquire_ctx;
12723
462a425a 12724 ret = intel_modeset_stage_output_state(dev, set, state);
2e431051 12725 if (ret)
7cbf41d6 12726 goto out;
2e431051 12727
8c7b5ccb 12728 pipe_config = intel_modeset_compute_config(set->crtc, state);
20664591 12729 if (IS_ERR(pipe_config)) {
6ac0483b 12730 ret = PTR_ERR(pipe_config);
7cbf41d6 12731 goto out;
20664591 12732 }
50f52756 12733
1f9954d0
JB		 12734 intel_update_pipe_size(to_intel_crtc(set->crtc));
12735
bb546623
ACO		 12736 primary_plane_was_visible = primary_plane_visible(set->crtc);
12737
8c7b5ccb 12738 ret = intel_set_mode_with_config(set->crtc, pipe_config);
bb546623
ACO		 12739
12740 if (ret == 0 &&
12741 pipe_config->base.enable &&
12742 pipe_config->base.planes_changed &&
12743 !needs_modeset(&pipe_config->base)) {
3b150f08 12744 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
3b150f08
MR		 12745
12746 /*
12747 * We need to make sure the primary plane is re-enabled if it
12748 * has previously been turned off.
12749 */
bb546623
ACO		 12750 if (ret == 0 && !primary_plane_was_visible &&
12751 primary_plane_visible(set->crtc)) {
3b150f08 12752 WARN_ON(!intel_crtc->active);
87d4300a 12753 intel_post_enable_primary(set->crtc);
3b150f08
MR		 12754 }
12755
7ca51a3a
JB		 12756 /*
12757 * In the fastboot case this may be our only check of the
12758 * state after boot. It would be better to only do it on
12759 * the first update, but we don't have a nice way of doing that
12760 * (and really, set_config isn't used much for high freq page
12761 * flipping, so increasing its cost here shouldn't be a big
12762 * deal).
12763 */
d330a953 12764 if (i915.fastboot && ret == 0)
7ca51a3a 12765 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 12766 }
12767
2d05eae1 12768 if (ret) {
bf67dfeb
DV		 12769 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12770 set->crtc->base.id, ret);
2d05eae1 12771 }
50f56119 12772
7cbf41d6 12773out:
2bfb4627
ACO		 12774 if (ret)
12775 drm_atomic_state_free(state);
50f56119
DV		 12776 return ret;
12777}
f6e5b160
CW		 12778
12779static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 12780 .gamma_set = intel_crtc_gamma_set,
50f56119 12781 .set_config = intel_crtc_set_config,
f6e5b160
CW		 12782 .destroy = intel_crtc_destroy,
12783 .page_flip = intel_crtc_page_flip,
1356837e
MR		 12784 .atomic_duplicate_state = intel_crtc_duplicate_state,
12785 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 12786};
12787
5358901f
DV		 12788static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
12789 struct intel_shared_dpll *pll,
12790 struct intel_dpll_hw_state *hw_state)
ee7b9f93 12791{
5358901f 12792 uint32_t val;
ee7b9f93 12793
f458ebbc 12794 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 12795 return false;
12796
5358901f 12797 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 12798 hw_state->dpll = val;
12799 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
12800 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 12801
12802 return val & DPLL_VCO_ENABLE;
12803}
12804
15bdd4cf
DV		 12805static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
12806 struct intel_shared_dpll *pll)
12807{
3e369b76
ACO		 12808 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
12809 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 12810}
12811
e7b903d2
DV		 12812static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
12813 struct intel_shared_dpll *pll)
12814{
e7b903d2 12815 /* PCH refclock must be enabled first */
89eff4be 12816 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 12817
3e369b76 12818 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 12819
12820 /* Wait for the clocks to stabilize. */
12821 POSTING_READ(PCH_DPLL(pll->id));
12822 udelay(150);
12823
12824 /* The pixel multiplier can only be updated once the
12825 * DPLL is enabled and the clocks are stable.
12826 *
12827 * So write it again.
12828 */
3e369b76 12829 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 12830 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 12831 udelay(200);
12832}
12833
12834static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
12835 struct intel_shared_dpll *pll)
12836{
12837 struct drm_device *dev = dev_priv->dev;
12838 struct intel_crtc *crtc;
e7b903d2
DV		 12839
12840 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 12841 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 12842 if (intel_crtc_to_shared_dpll(crtc) == pll)
12843 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 12844 }
12845
15bdd4cf
DV		 12846 I915_WRITE(PCH_DPLL(pll->id), 0);
12847 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 12848 udelay(200);
12849}
12850
46edb027
DV		 12851static char *ibx_pch_dpll_names[] = {
12852 "PCH DPLL A",
12853 "PCH DPLL B",
12854};
12855
7c74ade1 12856static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 12857{
e7b903d2 12858 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 12859 int i;
12860
7c74ade1 12861 dev_priv->num_shared_dpll = 2;
ee7b9f93 12862
e72f9fbf 12863 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 12864 dev_priv->shared_dplls[i].id = i;
12865 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 12866 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 12867 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12868 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 12869 dev_priv->shared_dplls[i].get_hw_state =
12870 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 12871 }
12872}
12873
7c74ade1
DV		 12874static void intel_shared_dpll_init(struct drm_device *dev)
12875{
e7b903d2 12876 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 12877
9cd86933
DV		 12878 if (HAS_DDI(dev))
12879 intel_ddi_pll_init(dev);
12880 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 12881 ibx_pch_dpll_init(dev);
12882 else
12883 dev_priv->num_shared_dpll = 0;
12884
12885 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 12886}
12887
1fc0a8f7
TU		 12888/**
12889 * intel_wm_need_update - Check whether watermarks need updating
12890 * @plane: drm plane
12891 * @state: new plane state
12892 *
12893 * Check current plane state versus the new one to determine whether
12894 * watermarks need to be recalculated.
12895 *
12896 * Returns true or false.
12897 */
12898bool intel_wm_need_update(struct drm_plane *plane,
12899 struct drm_plane_state *state)
12900{
12901 /* Update watermarks on tiling changes. */
12902 if (!plane->state->fb || !state->fb ||
12903 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12904 plane->state->rotation != state->rotation)
12905 return true;
12906
12907 return false;
12908}
12909
6beb8c23
MR		 12910/**
12911 * intel_prepare_plane_fb - Prepare fb for usage on plane
12912 * @plane: drm plane to prepare for
12913 * @fb: framebuffer to prepare for presentation
12914 *
12915 * Prepares a framebuffer for usage on a display plane. Generally this
12916 * involves pinning the underlying object and updating the frontbuffer tracking
12917 * bits. Some older platforms need special physical address handling for
12918 * cursor planes.
12919 *
12920 * Returns 0 on success, negative error code on failure.
12921 */
12922int
12923intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 12924 struct drm_framebuffer *fb,
12925 const struct drm_plane_state *new_state)
465c120c
MR		 12926{
12927 struct drm_device *dev = plane->dev;
6beb8c23
MR		 12928 struct intel_plane *intel_plane = to_intel_plane(plane);
12929 enum pipe pipe = intel_plane->pipe;
12930 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12931 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12932 unsigned frontbuffer_bits = 0;
12933 int ret = 0;
465c120c 12934
ea2c67bb 12935 if (!obj)
465c120c
MR		 12936 return 0;
12937
6beb8c23
MR		 12938 switch (plane->type) {
12939 case DRM_PLANE_TYPE_PRIMARY:
12940 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12941 break;
12942 case DRM_PLANE_TYPE_CURSOR:
12943 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12944 break;
12945 case DRM_PLANE_TYPE_OVERLAY:
12946 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12947 break;
12948 }
465c120c 12949
6beb8c23 12950 mutex_lock(&dev->struct_mutex);
465c120c 12951
6beb8c23
MR		 12952 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12953 INTEL_INFO(dev)->cursor_needs_physical) {
12954 int align = IS_I830(dev) ? 16 * 1024 : 256;
12955 ret = i915_gem_object_attach_phys(obj, align);
12956 if (ret)
12957 DRM_DEBUG_KMS("failed to attach phys object\n");
12958 } else {
82bc3b2d 12959 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 12960 }
465c120c 12961
6beb8c23
MR		 12962 if (ret == 0)
12963 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 12964
4c34574f 12965 mutex_unlock(&dev->struct_mutex);
465c120c 12966
6beb8c23
MR		 12967 return ret;
12968}
12969
38f3ce3a
MR		 12970/**
12971 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12972 * @plane: drm plane to clean up for
12973 * @fb: old framebuffer that was on plane
12974 *
12975 * Cleans up a framebuffer that has just been removed from a plane.
12976 */
12977void
12978intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 12979 struct drm_framebuffer *fb,
12980 const struct drm_plane_state *old_state)
38f3ce3a
MR		 12981{
12982 struct drm_device *dev = plane->dev;
12983 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12984
12985 if (WARN_ON(!obj))
12986 return;
12987
12988 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12989 !INTEL_INFO(dev)->cursor_needs_physical) {
12990 mutex_lock(&dev->struct_mutex);
82bc3b2d 12991 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 12992 mutex_unlock(&dev->struct_mutex);
12993 }
465c120c
MR		 12994}
12995
6156a456
CK		 12996int
12997skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
12998{
12999 int max_scale;
13000 struct drm_device *dev;
13001 struct drm_i915_private *dev_priv;
13002 int crtc_clock, cdclk;
13003
13004 if (!intel_crtc || !crtc_state)
13005 return DRM_PLANE_HELPER_NO_SCALING;
13006
13007 dev = intel_crtc->base.dev;
13008 dev_priv = dev->dev_private;
13009 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13010 cdclk = dev_priv->display.get_display_clock_speed(dev);
13011
13012 if (!crtc_clock || !cdclk)
13013 return DRM_PLANE_HELPER_NO_SCALING;
13014
13015 /*
13016 * skl max scale is lower of:
13017 * close to 3 but not 3, -1 is for that purpose
13018 * or
13019 * cdclk/crtc_clock
13020 */
13021 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13022
13023 return max_scale;
13024}
13025
465c120c 13026static int
3c692a41
GP		 13027intel_check_primary_plane(struct drm_plane *plane,
13028 struct intel_plane_state *state)
13029{
32b7eeec
MR		 13030 struct drm_device *dev = plane->dev;
13031 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 13032 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13033 struct intel_crtc *intel_crtc;
6156a456 13034 struct intel_crtc_state *crtc_state;
2b875c22 13035 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 13036 struct drm_rect *dest = &state->dst;
13037 struct drm_rect *src = &state->src;
13038 const struct drm_rect *clip = &state->clip;
d8106366 13039 bool can_position = false;
6156a456
CK		 13040 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13041 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
465c120c
MR		 13042 int ret;
13043
ea2c67bb
MR		 13044 crtc = crtc ? crtc : plane->crtc;
13045 intel_crtc = to_intel_crtc(crtc);
6156a456
CK		 13046 crtc_state = state->base.state ?
13047 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
ea2c67bb 13048
6156a456
CK		 13049 if (INTEL_INFO(dev)->gen >= 9) {
13050 min_scale = 1;
13051 max_scale = skl_max_scale(intel_crtc, crtc_state);
d8106366 13052 can_position = true;
6156a456 13053 }
d8106366 13054
c59cb179
MR		 13055 ret = drm_plane_helper_check_update(plane, crtc, fb,
13056 src, dest, clip,
6156a456
CK		 13057 min_scale,
13058 max_scale,
d8106366
SJ		 13059 can_position, true,
13060 &state->visible);
c59cb179
MR		 13061 if (ret)
13062 return ret;
465c120c 13063
32b7eeec 13064 if (intel_crtc->active) {
b70709a6
ML		 13065 struct intel_plane_state *old_state =
13066 to_intel_plane_state(plane->state);
13067
32b7eeec
MR		 13068 intel_crtc->atomic.wait_for_flips = true;
13069
13070 /*
13071 * FBC does not work on some platforms for rotated
13072 * planes, so disable it when rotation is not 0 and
13073 * update it when rotation is set back to 0.
13074 *
13075 * FIXME: This is redundant with the fbc update done in
13076 * the primary plane enable function except that that
13077 * one is done too late. We eventually need to unify
13078 * this.
13079 */
b70709a6 13080 if (state->visible &&
32b7eeec 13081 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 13082 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 13083 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 13084 intel_crtc->atomic.disable_fbc = true;
13085 }
13086
b70709a6 13087 if (state->visible && !old_state->visible) {
32b7eeec
MR		 13088 /*
13089 * BDW signals flip done immediately if the plane
13090 * is disabled, even if the plane enable is already
13091 * armed to occur at the next vblank :(
13092 */
b70709a6 13093 if (IS_BROADWELL(dev))
32b7eeec
MR		 13094 intel_crtc->atomic.wait_vblank = true;
13095 }
13096
13097 intel_crtc->atomic.fb_bits |=
13098 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13099
13100 intel_crtc->atomic.update_fbc = true;
0fda6568 13101
1fc0a8f7 13102 if (intel_wm_need_update(plane, &state->base))
0fda6568 13103 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 13104 }
13105
6156a456
CK		 13106 if (INTEL_INFO(dev)->gen >= 9) {
13107 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13108 to_intel_plane(plane), state, 0);
13109 if (ret)
13110 return ret;
13111 }
13112
14af293f
GP		 13113 return 0;
13114}
13115
13116static void
13117intel_commit_primary_plane(struct drm_plane *plane,
13118 struct intel_plane_state *state)
13119{
2b875c22
MR		 13120 struct drm_crtc *crtc = state->base.crtc;
13121 struct drm_framebuffer *fb = state->base.fb;
13122 struct drm_device *dev = plane->dev;
14af293f 13123 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13124 struct intel_crtc *intel_crtc;
14af293f
GP		 13125 struct drm_rect *src = &state->src;
13126
ea2c67bb
MR		 13127 crtc = crtc ? crtc : plane->crtc;
13128 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13129
13130 plane->fb = fb;
9dc806fc
MR		 13131 crtc->x = src->x1 >> 16;
13132 crtc->y = src->y1 >> 16;
ccc759dc 13133
ccc759dc 13134 if (intel_crtc->active) {
27321ae8 13135 if (state->visible)
ccc759dc
GP		 13136 /* FIXME: kill this fastboot hack */
13137 intel_update_pipe_size(intel_crtc);
465c120c 13138
27321ae8
ML		 13139 dev_priv->display.update_primary_plane(crtc, plane->fb,
13140 crtc->x, crtc->y);
ccc759dc 13141 }
465c120c
MR		 13142}
13143
a8ad0d8e
ML		 13144static void
13145intel_disable_primary_plane(struct drm_plane *plane,
13146 struct drm_crtc *crtc,
13147 bool force)
13148{
13149 struct drm_device *dev = plane->dev;
13150 struct drm_i915_private *dev_priv = dev->dev_private;
13151
a8ad0d8e
ML		 13152 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13153}
13154
32b7eeec 13155static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13156{
32b7eeec 13157 struct drm_device *dev = crtc->dev;
140fd38d 13158 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13159 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 13160 struct intel_plane *intel_plane;
13161 struct drm_plane *p;
13162 unsigned fb_bits = 0;
13163
13164 /* Track fb's for any planes being disabled */
13165 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13166 intel_plane = to_intel_plane(p);
13167
13168 if (intel_crtc->atomic.disabled_planes &
13169 (1 << drm_plane_index(p))) {
13170 switch (p->type) {
13171 case DRM_PLANE_TYPE_PRIMARY:
13172 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13173 break;
13174 case DRM_PLANE_TYPE_CURSOR:
13175 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13176 break;
13177 case DRM_PLANE_TYPE_OVERLAY:
13178 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13179 break;
13180 }
3c692a41 13181
ea2c67bb
MR		 13182 mutex_lock(&dev->struct_mutex);
13183 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13184 mutex_unlock(&dev->struct_mutex);
13185 }
13186 }
3c692a41 13187
32b7eeec
MR		 13188 if (intel_crtc->atomic.wait_for_flips)
13189 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 13190
32b7eeec
MR		 13191 if (intel_crtc->atomic.disable_fbc)
13192 intel_fbc_disable(dev);
3c692a41 13193
32b7eeec
MR		 13194 if (intel_crtc->atomic.pre_disable_primary)
13195 intel_pre_disable_primary(crtc);
3c692a41 13196
32b7eeec
MR		 13197 if (intel_crtc->atomic.update_wm)
13198 intel_update_watermarks(crtc);
3c692a41 13199
32b7eeec 13200 intel_runtime_pm_get(dev_priv);
3c692a41 13201
c34c9ee4
MR		 13202 /* Perform vblank evasion around commit operation */
13203 if (intel_crtc->active)
13204 intel_crtc->atomic.evade =
13205 intel_pipe_update_start(intel_crtc,
13206 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 13207}
13208
13209static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13210{
13211 struct drm_device *dev = crtc->dev;
13212 struct drm_i915_private *dev_priv = dev->dev_private;
13213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13214 struct drm_plane *p;
13215
c34c9ee4
MR		 13216 if (intel_crtc->atomic.evade)
13217 intel_pipe_update_end(intel_crtc,
13218 intel_crtc->atomic.start_vbl_count);
3c692a41 13219
140fd38d 13220 intel_runtime_pm_put(dev_priv);
3c692a41 13221
32b7eeec
MR		 13222 if (intel_crtc->atomic.wait_vblank)
13223 intel_wait_for_vblank(dev, intel_crtc->pipe);
13224
13225 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13226
13227 if (intel_crtc->atomic.update_fbc) {
ccc759dc 13228 mutex_lock(&dev->struct_mutex);
7ff0ebcc 13229 intel_fbc_update(dev);
ccc759dc 13230 mutex_unlock(&dev->struct_mutex);
38f3ce3a 13231 }
3c692a41 13232
32b7eeec
MR		 13233 if (intel_crtc->atomic.post_enable_primary)
13234 intel_post_enable_primary(crtc);
3c692a41 13235
32b7eeec
MR		 13236 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13237 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13238 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13239 false, false);
13240
13241 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 13242}
13243
cf4c7c12 13244/**
4a3b8769
MR		 13245 * intel_plane_destroy - destroy a plane
13246 * @plane: plane to destroy
cf4c7c12 13247 *
4a3b8769
MR		 13248 * Common destruction function for all types of planes (primary, cursor,
13249 * sprite).
cf4c7c12 13250 */
4a3b8769 13251void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13252{
13253 struct intel_plane *intel_plane = to_intel_plane(plane);
13254 drm_plane_cleanup(plane);
13255 kfree(intel_plane);
13256}
13257
65a3fea0 13258const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13259 .update_plane = drm_atomic_helper_update_plane,
13260 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13261 .destroy = intel_plane_destroy,
c196e1d6 13262 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13263 .atomic_get_property = intel_plane_atomic_get_property,
13264 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13265 .atomic_duplicate_state = intel_plane_duplicate_state,
13266 .atomic_destroy_state = intel_plane_destroy_state,
13267
465c120c
MR		 13268};
13269
13270static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13271 int pipe)
13272{
13273 struct intel_plane *primary;
8e7d688b 13274 struct intel_plane_state *state;
465c120c
MR		 13275 const uint32_t *intel_primary_formats;
13276 int num_formats;
13277
13278 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13279 if (primary == NULL)
13280 return NULL;
13281
8e7d688b
MR		 13282 state = intel_create_plane_state(&primary->base);
13283 if (!state) {
ea2c67bb
MR		 13284 kfree(primary);
13285 return NULL;
13286 }
8e7d688b 13287 primary->base.state = &state->base;
ea2c67bb 13288
465c120c
MR		 13289 primary->can_scale = false;
13290 primary->max_downscale = 1;
6156a456
CK		 13291 if (INTEL_INFO(dev)->gen >= 9) {
13292 primary->can_scale = true;
af99ceda 13293 state->scaler_id = -1;
6156a456 13294 }
465c120c
MR		 13295 primary->pipe = pipe;
13296 primary->plane = pipe;
c59cb179
MR		 13297 primary->check_plane = intel_check_primary_plane;
13298 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13299 primary->disable_plane = intel_disable_primary_plane;
08e221fb 13300 primary->ckey.flags = I915_SET_COLORKEY_NONE;
465c120c
MR		 13301 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13302 primary->plane = !pipe;
13303
13304 if (INTEL_INFO(dev)->gen <= 3) {
568db4f2
DL		 13305 intel_primary_formats = i8xx_primary_formats;
13306 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c 13307 } else {
568db4f2
DL		 13308 intel_primary_formats = i965_primary_formats;
13309 num_formats = ARRAY_SIZE(i965_primary_formats);
465c120c
MR		 13310 }
13311
13312 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13313 &intel_plane_funcs,
465c120c
MR		 13314 intel_primary_formats, num_formats,
13315 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13316
3b7a5119
SJ		 13317 if (INTEL_INFO(dev)->gen >= 4)
13318 intel_create_rotation_property(dev, primary);
48404c1e 13319
ea2c67bb
MR		 13320 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13321
465c120c
MR		 13322 return &primary->base;
13323}
13324
3b7a5119
SJ		 13325void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13326{
13327 if (!dev->mode_config.rotation_property) {
13328 unsigned long flags = BIT(DRM_ROTATE_0) |
13329 BIT(DRM_ROTATE_180);
13330
13331 if (INTEL_INFO(dev)->gen >= 9)
13332 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13333
13334 dev->mode_config.rotation_property =
13335 drm_mode_create_rotation_property(dev, flags);
13336 }
13337 if (dev->mode_config.rotation_property)
13338 drm_object_attach_property(&plane->base.base,
13339 dev->mode_config.rotation_property,
13340 plane->base.state->rotation);
13341}
13342
3d7d6510 13343static int
852e787c
GP		 13344intel_check_cursor_plane(struct drm_plane *plane,
13345 struct intel_plane_state *state)
3d7d6510 13346{
2b875c22 13347 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13348 struct drm_device *dev = plane->dev;
2b875c22 13349 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 13350 struct drm_rect *dest = &state->dst;
13351 struct drm_rect *src = &state->src;
13352 const struct drm_rect *clip = &state->clip;
757f9a3e 13353 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 13354 struct intel_crtc *intel_crtc;
757f9a3e
GP		 13355 unsigned stride;
13356 int ret;
3d7d6510 13357
ea2c67bb
MR		 13358 crtc = crtc ? crtc : plane->crtc;
13359 intel_crtc = to_intel_crtc(crtc);
13360
757f9a3e 13361 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 13362 src, dest, clip,
3d7d6510
MR		 13363 DRM_PLANE_HELPER_NO_SCALING,
13364 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13365 true, true, &state->visible);
757f9a3e
GP		 13366 if (ret)
13367 return ret;
13368
13369
13370 /* if we want to turn off the cursor ignore width and height */
13371 if (!obj)
32b7eeec 13372 goto finish;
757f9a3e 13373
757f9a3e 13374 /* Check for which cursor types we support */
ea2c67bb
MR		 13375 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13376 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13377 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13378 return -EINVAL;
13379 }
13380
ea2c67bb
MR		 13381 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13382 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13383 DRM_DEBUG_KMS("buffer is too small\n");
13384 return -ENOMEM;
13385 }
13386
3a656b54 13387 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 13388 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13389 ret = -EINVAL;
13390 }
757f9a3e 13391
32b7eeec
MR		 13392finish:
13393 if (intel_crtc->active) {
3749f463 13394 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 13395 intel_crtc->atomic.update_wm = true;
13396
13397 intel_crtc->atomic.fb_bits |=
13398 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13399 }
13400
757f9a3e 13401 return ret;
852e787c 13402}
3d7d6510 13403
a8ad0d8e
ML		 13404static void
13405intel_disable_cursor_plane(struct drm_plane *plane,
13406 struct drm_crtc *crtc,
13407 bool force)
13408{
13409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13410
13411 if (!force) {
13412 plane->fb = NULL;
13413 intel_crtc->cursor_bo = NULL;
13414 intel_crtc->cursor_addr = 0;
13415 }
13416
13417 intel_crtc_update_cursor(crtc, false);
13418}
13419
f4a2cf29 13420static void
852e787c
GP		 13421intel_commit_cursor_plane(struct drm_plane *plane,
13422 struct intel_plane_state *state)
13423{
2b875c22 13424 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13425 struct drm_device *dev = plane->dev;
13426 struct intel_crtc *intel_crtc;
2b875c22 13427 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13428 uint32_t addr;
852e787c 13429
ea2c67bb
MR		 13430 crtc = crtc ? crtc : plane->crtc;
13431 intel_crtc = to_intel_crtc(crtc);
13432
2b875c22 13433 plane->fb = state->base.fb;
ea2c67bb
MR		 13434 crtc->cursor_x = state->base.crtc_x;
13435 crtc->cursor_y = state->base.crtc_y;
13436
a912f12f
GP		 13437 if (intel_crtc->cursor_bo == obj)
13438 goto update;
4ed91096 13439
f4a2cf29 13440 if (!obj)
a912f12f 13441 addr = 0;
f4a2cf29 13442 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13443 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13444 else
a912f12f 13445 addr = obj->phys_handle->busaddr;
852e787c 13446
a912f12f
GP		 13447 intel_crtc->cursor_addr = addr;
13448 intel_crtc->cursor_bo = obj;
13449update:
852e787c 13450
32b7eeec 13451 if (intel_crtc->active)
a912f12f 13452 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13453}
13454
3d7d6510
MR		 13455static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13456 int pipe)
13457{
13458 struct intel_plane *cursor;
8e7d688b 13459 struct intel_plane_state *state;
3d7d6510
MR		 13460
13461 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13462 if (cursor == NULL)
13463 return NULL;
13464
8e7d688b
MR		 13465 state = intel_create_plane_state(&cursor->base);
13466 if (!state) {
ea2c67bb
MR		 13467 kfree(cursor);
13468 return NULL;
13469 }
8e7d688b 13470 cursor->base.state = &state->base;
ea2c67bb 13471
3d7d6510
MR		 13472 cursor->can_scale = false;
13473 cursor->max_downscale = 1;
13474 cursor->pipe = pipe;
13475 cursor->plane = pipe;
c59cb179
MR		 13476 cursor->check_plane = intel_check_cursor_plane;
13477 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13478 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13479
13480 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13481 &intel_plane_funcs,
3d7d6510
MR		 13482 intel_cursor_formats,
13483 ARRAY_SIZE(intel_cursor_formats),
13484 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13485
13486 if (INTEL_INFO(dev)->gen >= 4) {
13487 if (!dev->mode_config.rotation_property)
13488 dev->mode_config.rotation_property =
13489 drm_mode_create_rotation_property(dev,
13490 BIT(DRM_ROTATE_0) |
13491 BIT(DRM_ROTATE_180));
13492 if (dev->mode_config.rotation_property)
13493 drm_object_attach_property(&cursor->base.base,
13494 dev->mode_config.rotation_property,
8e7d688b 13495 state->base.rotation);
4398ad45
VS		 13496 }
13497
af99ceda
CK		 13498 if (INTEL_INFO(dev)->gen >=9)
13499 state->scaler_id = -1;
13500
ea2c67bb
MR		 13501 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13502
3d7d6510
MR		 13503 return &cursor->base;
13504}
13505
549e2bfb
CK		 13506static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13507 struct intel_crtc_state *crtc_state)
13508{
13509 int i;
13510 struct intel_scaler *intel_scaler;
13511 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13512
13513 for (i = 0; i < intel_crtc->num_scalers; i++) {
13514 intel_scaler = &scaler_state->scalers[i];
13515 intel_scaler->in_use = 0;
13516 intel_scaler->id = i;
13517
13518 intel_scaler->mode = PS_SCALER_MODE_DYN;
13519 }
13520
13521 scaler_state->scaler_id = -1;
13522}
13523
b358d0a6 13524static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13525{
fbee40df 13526 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13527 struct intel_crtc *intel_crtc;
f5de6e07 13528 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13529 struct drm_plane *primary = NULL;
13530 struct drm_plane *cursor = NULL;
465c120c 13531 int i, ret;
79e53945 13532
955382f3 13533 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13534 if (intel_crtc == NULL)
13535 return;
13536
f5de6e07
ACO		 13537 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13538 if (!crtc_state)
13539 goto fail;
550acefd
ACO		 13540 intel_crtc->config = crtc_state;
13541 intel_crtc->base.state = &crtc_state->base;
07878248 13542 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13543
549e2bfb
CK		 13544 /* initialize shared scalers */
13545 if (INTEL_INFO(dev)->gen >= 9) {
13546 if (pipe == PIPE_C)
13547 intel_crtc->num_scalers = 1;
13548 else
13549 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13550
13551 skl_init_scalers(dev, intel_crtc, crtc_state);
13552 }
13553
465c120c 13554 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13555 if (!primary)
13556 goto fail;
13557
13558 cursor = intel_cursor_plane_create(dev, pipe);
13559 if (!cursor)
13560 goto fail;
13561
465c120c 13562 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13563 cursor, &intel_crtc_funcs);
13564 if (ret)
13565 goto fail;
79e53945
JB		 13566
13567 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13568 for (i = 0; i < 256; i++) {
13569 intel_crtc->lut_r[i] = i;
13570 intel_crtc->lut_g[i] = i;
13571 intel_crtc->lut_b[i] = i;
13572 }
13573
1f1c2e24
VS		 13574 /*
13575 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13576 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13577 */
80824003
JB		 13578 intel_crtc->pipe = pipe;
13579 intel_crtc->plane = pipe;
3a77c4c4 13580 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13581 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13582 intel_crtc->plane = !pipe;
80824003
JB		 13583 }
13584
4b0e333e
CW		 13585 intel_crtc->cursor_base = ~0;
13586 intel_crtc->cursor_cntl = ~0;
dc41c154 13587 intel_crtc->cursor_size = ~0;
8d7849db 13588
22fd0fab
JB		 13589 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13590 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13591 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13592 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13593
79e53945 13594 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 13595
13596 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13597 return;
13598
13599fail:
13600 if (primary)
13601 drm_plane_cleanup(primary);
13602 if (cursor)
13603 drm_plane_cleanup(cursor);
f5de6e07 13604 kfree(crtc_state);
3d7d6510 13605 kfree(intel_crtc);
79e53945
JB		 13606}
13607
752aa88a
JB		 13608enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13609{
13610 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13611 struct drm_device *dev = connector->base.dev;
752aa88a 13612
51fd371b 13613 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13614
d3babd3f 13615 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 13616 return INVALID_PIPE;
13617
13618 return to_intel_crtc(encoder->crtc)->pipe;
13619}
13620
08d7b3d1 13621int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13622 struct drm_file *file)
08d7b3d1 13623{
08d7b3d1 13624 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13625 struct drm_crtc *drmmode_crtc;
c05422d5 13626 struct intel_crtc *crtc;
08d7b3d1 13627
7707e653 13628 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13629
7707e653 13630 if (!drmmode_crtc) {
08d7b3d1 13631 DRM_ERROR("no such CRTC id\n");
3f2c2057 13632 return -ENOENT;
08d7b3d1
CW		 13633 }
13634
7707e653 13635 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13636 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13637
c05422d5 13638 return 0;
08d7b3d1
CW		 13639}
13640
66a9278e 13641static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13642{
66a9278e
DV		 13643 struct drm_device *dev = encoder->base.dev;
13644 struct intel_encoder *source_encoder;
79e53945 13645 int index_mask = 0;
79e53945
JB		 13646 int entry = 0;
13647
b2784e15 13648 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13649 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 13650 index_mask |= (1 << entry);
13651
79e53945
JB		 13652 entry++;
13653 }
4ef69c7a 13654
79e53945
JB		 13655 return index_mask;
13656}
13657
4d302442
CW		 13658static bool has_edp_a(struct drm_device *dev)
13659{
13660 struct drm_i915_private *dev_priv = dev->dev_private;
13661
13662 if (!IS_MOBILE(dev))
13663 return false;
13664
13665 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13666 return false;
13667
e3589908 13668 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 13669 return false;
13670
13671 return true;
13672}
13673
84b4e042
JB		 13674static bool intel_crt_present(struct drm_device *dev)
13675{
13676 struct drm_i915_private *dev_priv = dev->dev_private;
13677
884497ed
DL		 13678 if (INTEL_INFO(dev)->gen >= 9)
13679 return false;
13680
cf404ce4 13681 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 13682 return false;
13683
13684 if (IS_CHERRYVIEW(dev))
13685 return false;
13686
13687 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13688 return false;
13689
13690 return true;
13691}
13692
79e53945
JB		 13693static void intel_setup_outputs(struct drm_device *dev)
13694{
725e30ad 13695 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13696 struct intel_encoder *encoder;
cb0953d7 13697 bool dpd_is_edp = false;
79e53945 13698
c9093354 13699 intel_lvds_init(dev);
79e53945 13700
84b4e042 13701 if (intel_crt_present(dev))
79935fca 13702 intel_crt_init(dev);
cb0953d7 13703
c776eb2e
VK		 13704 if (IS_BROXTON(dev)) {
13705 /*
13706 * FIXME: Broxton doesn't support port detection via the
13707 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13708 * detect the ports.
13709 */
13710 intel_ddi_init(dev, PORT_A);
13711 intel_ddi_init(dev, PORT_B);
13712 intel_ddi_init(dev, PORT_C);
13713 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 13714 int found;
13715
de31facd
JB		 13716 /*
13717 * Haswell uses DDI functions to detect digital outputs.
13718 * On SKL pre-D0 the strap isn't connected, so we assume
13719 * it's there.
13720 */
0e72a5b5 13721 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 13722 /* WaIgnoreDDIAStrap: skl */
13723 if (found ||
13724 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 13725 intel_ddi_init(dev, PORT_A);
13726
13727 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13728 * register */
13729 found = I915_READ(SFUSE_STRAP);
13730
13731 if (found & SFUSE_STRAP_DDIB_DETECTED)
13732 intel_ddi_init(dev, PORT_B);
13733 if (found & SFUSE_STRAP_DDIC_DETECTED)
13734 intel_ddi_init(dev, PORT_C);
13735 if (found & SFUSE_STRAP_DDID_DETECTED)
13736 intel_ddi_init(dev, PORT_D);
13737 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 13738 int found;
5d8a7752 13739 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 13740
13741 if (has_edp_a(dev))
13742 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 13743
dc0fa718 13744 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 13745 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 13746 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 13747 if (!found)
e2debe91 13748 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 13749 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 13750 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 13751 }
13752
dc0fa718 13753 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 13754 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 13755
dc0fa718 13756 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 13757 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 13758
5eb08b69 13759 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 13760 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 13761
270b3042 13762 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 13763 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 13764 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 13765 /*
13766 * The DP_DETECTED bit is the latched state of the DDC
13767 * SDA pin at boot. However since eDP doesn't require DDC
13768 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13769 * eDP ports may have been muxed to an alternate function.
13770 * Thus we can't rely on the DP_DETECTED bit alone to detect
13771 * eDP ports. Consult the VBT as well as DP_DETECTED to
13772 * detect eDP ports.
13773 */
d2182a66
VS		 13774 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13775 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 13776 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13777 PORT_B);
e17ac6db
VS		 13778 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13779 intel_dp_is_edp(dev, PORT_B))
13780 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 13781
d2182a66
VS		 13782 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
13783 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 13784 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
13785 PORT_C);
e17ac6db
VS		 13786 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
13787 intel_dp_is_edp(dev, PORT_C))
13788 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 13789
9418c1f1 13790 if (IS_CHERRYVIEW(dev)) {
e17ac6db 13791 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 13792 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
13793 PORT_D);
e17ac6db
VS		 13794 /* eDP not supported on port D, so don't check VBT */
13795 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
13796 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 13797 }
13798
3cfca973 13799 intel_dsi_init(dev);
103a196f 13800 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 13801 bool found = false;
7d57382e 13802
e2debe91 13803 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13804 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 13805 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 13806 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
13807 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 13808 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 13809 }
27185ae1 13810
e7281eab 13811 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 13812 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 13813 }
13520b05
KH		 13814
13815 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 13816
e2debe91 13817 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 13818 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 13819 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 13820 }
27185ae1 13821
e2debe91 13822 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 13823
b01f2c3a
JB		 13824 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
13825 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 13826 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 13827 }
e7281eab 13828 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 13829 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 13830 }
27185ae1 13831
b01f2c3a 13832 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 13833 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 13834 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 13835 } else if (IS_GEN2(dev))
79e53945
JB		 13836 intel_dvo_init(dev);
13837
103a196f 13838 if (SUPPORTS_TV(dev))
79e53945
JB		 13839 intel_tv_init(dev);
13840
0bc12bcb 13841 intel_psr_init(dev);
7c8f8a70 13842
b2784e15 13843 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 13844 encoder->base.possible_crtcs = encoder->crtc_mask;
13845 encoder->base.possible_clones =
66a9278e 13846 intel_encoder_clones(encoder);
79e53945 13847 }
47356eb6 13848
dde86e2d 13849 intel_init_pch_refclk(dev);
270b3042
DV		 13850
13851 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 13852}
13853
13854static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
13855{
60a5ca01 13856 struct drm_device *dev = fb->dev;
79e53945 13857 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 13858
ef2d633e 13859 drm_framebuffer_cleanup(fb);
60a5ca01 13860 mutex_lock(&dev->struct_mutex);
ef2d633e 13861 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 13862 drm_gem_object_unreference(&intel_fb->obj->base);
13863 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 13864 kfree(intel_fb);
13865}
13866
13867static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 13868 struct drm_file *file,
79e53945
JB		 13869 unsigned int *handle)
13870{
13871 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 13872 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 13873
05394f39 13874 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 13875}
13876
13877static const struct drm_framebuffer_funcs intel_fb_funcs = {
13878 .destroy = intel_user_framebuffer_destroy,
13879 .create_handle = intel_user_framebuffer_create_handle,
13880};
13881
b321803d
DL		 13882static
13883u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
13884 uint32_t pixel_format)
13885{
13886 u32 gen = INTEL_INFO(dev)->gen;
13887
13888 if (gen >= 9) {
13889 /* "The stride in bytes must not exceed the of the size of 8K
13890 * pixels and 32K bytes."
13891 */
13892 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
13893 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
13894 return 32*1024;
13895 } else if (gen >= 4) {
13896 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13897 return 16*1024;
13898 else
13899 return 32*1024;
13900 } else if (gen >= 3) {
13901 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
13902 return 8*1024;
13903 else
13904 return 16*1024;
13905 } else {
13906 /* XXX DSPC is limited to 4k tiled */
13907 return 8*1024;
13908 }
13909}
13910
b5ea642a
DV		 13911static int intel_framebuffer_init(struct drm_device *dev,
13912 struct intel_framebuffer *intel_fb,
13913 struct drm_mode_fb_cmd2 *mode_cmd,
13914 struct drm_i915_gem_object *obj)
79e53945 13915{
6761dd31 13916 unsigned int aligned_height;
79e53945 13917 int ret;
b321803d 13918 u32 pitch_limit, stride_alignment;
79e53945 13919
dd4916c5
DV		 13920 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
13921
2a80eada
DV		 13922 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
13923 /* Enforce that fb modifier and tiling mode match, but only for
13924 * X-tiled. This is needed for FBC. */
13925 if (!!(obj->tiling_mode == I915_TILING_X) !=
13926 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
13927 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
13928 return -EINVAL;
13929 }
13930 } else {
13931 if (obj->tiling_mode == I915_TILING_X)
13932 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
13933 else if (obj->tiling_mode == I915_TILING_Y) {
13934 DRM_DEBUG("No Y tiling for legacy addfb\n");
13935 return -EINVAL;
13936 }
13937 }
13938
9a8f0a12
TU		 13939 /* Passed in modifier sanity checking. */
13940 switch (mode_cmd->modifier[0]) {
13941 case I915_FORMAT_MOD_Y_TILED:
13942 case I915_FORMAT_MOD_Yf_TILED:
13943 if (INTEL_INFO(dev)->gen < 9) {
13944 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13945 mode_cmd->modifier[0]);
13946 return -EINVAL;
13947 }
13948 case DRM_FORMAT_MOD_NONE:
13949 case I915_FORMAT_MOD_X_TILED:
13950 break;
13951 default:
c0f40428
JB		 13952 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
13953 mode_cmd->modifier[0]);
57cd6508 13954 return -EINVAL;
c16ed4be 13955 }
57cd6508 13956
b321803d
DL		 13957 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13958 mode_cmd->pixel_format);
13959 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13960 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13961 mode_cmd->pitches[0], stride_alignment);
57cd6508 13962 return -EINVAL;
c16ed4be 13963 }
57cd6508 13964
b321803d
DL		 13965 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13966 mode_cmd->pixel_format);
a35cdaa0 13967 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 13968 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13969 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 13970 "tiled" : "linear",
a35cdaa0 13971 mode_cmd->pitches[0], pitch_limit);
5d7bd705 13972 return -EINVAL;
c16ed4be 13973 }
5d7bd705 13974
2a80eada 13975 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 13976 mode_cmd->pitches[0] != obj->stride) {
13977 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13978 mode_cmd->pitches[0], obj->stride);
5d7bd705 13979 return -EINVAL;
c16ed4be 13980 }
5d7bd705 13981
57779d06 13982 /* Reject formats not supported by any plane early. */
308e5bcb 13983 switch (mode_cmd->pixel_format) {
57779d06 13984 case DRM_FORMAT_C8:
04b3924d
VS		 13985 case DRM_FORMAT_RGB565:
13986 case DRM_FORMAT_XRGB8888:
13987 case DRM_FORMAT_ARGB8888:
57779d06
VS		 13988 break;
13989 case DRM_FORMAT_XRGB1555:
13990 case DRM_FORMAT_ARGB1555:
c16ed4be 13991 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 13992 DRM_DEBUG("unsupported pixel format: %s\n",
13993 drm_get_format_name(mode_cmd->pixel_format));
57779d06 13994 return -EINVAL;
c16ed4be 13995 }
57779d06
VS		 13996 break;
13997 case DRM_FORMAT_XBGR8888:
13998 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 13999 case DRM_FORMAT_XRGB2101010:
14000 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 14001 case DRM_FORMAT_XBGR2101010:
14002 case DRM_FORMAT_ABGR2101010:
c16ed4be 14003 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14004 DRM_DEBUG("unsupported pixel format: %s\n",
14005 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14006 return -EINVAL;
c16ed4be 14007 }
b5626747 14008 break;
04b3924d
VS		 14009 case DRM_FORMAT_YUYV:
14010 case DRM_FORMAT_UYVY:
14011 case DRM_FORMAT_YVYU:
14012 case DRM_FORMAT_VYUY:
c16ed4be 14013 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14014 DRM_DEBUG("unsupported pixel format: %s\n",
14015 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14016 return -EINVAL;
c16ed4be 14017 }
57cd6508
CW		 14018 break;
14019 default:
4ee62c76
VS		 14020 DRM_DEBUG("unsupported pixel format: %s\n",
14021 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14022 return -EINVAL;
14023 }
14024
90f9a336
VS		 14025 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14026 if (mode_cmd->offsets[0] != 0)
14027 return -EINVAL;
14028
ec2c981e 14029 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14030 mode_cmd->pixel_format,
14031 mode_cmd->modifier[0]);
53155c0a
DV		 14032 /* FIXME drm helper for size checks (especially planar formats)? */
14033 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14034 return -EINVAL;
14035
c7d73f6a
DV		 14036 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14037 intel_fb->obj = obj;
80075d49 14038 intel_fb->obj->framebuffer_references++;
c7d73f6a 14039
79e53945
JB		 14040 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14041 if (ret) {
14042 DRM_ERROR("framebuffer init failed %d\n", ret);
14043 return ret;
14044 }
14045
79e53945
JB		 14046 return 0;
14047}
14048
79e53945
JB		 14049static struct drm_framebuffer *
14050intel_user_framebuffer_create(struct drm_device *dev,
14051 struct drm_file *filp,
308e5bcb 14052 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14053{
05394f39 14054 struct drm_i915_gem_object *obj;
79e53945 14055
308e5bcb
JB		 14056 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14057 mode_cmd->handles[0]));
c8725226 14058 if (&obj->base == NULL)
cce13ff7 14059 return ERR_PTR(-ENOENT);
79e53945 14060
d2dff872 14061 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14062}
14063
4520f53a 14064#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14065static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14066{
14067}
14068#endif
14069
79e53945 14070static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14071 .fb_create = intel_user_framebuffer_create,
0632fef6 14072 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14073 .atomic_check = intel_atomic_check,
14074 .atomic_commit = intel_atomic_commit,
79e53945
JB		 14075};
14076
e70236a8
JB		 14077/* Set up chip specific display functions */
14078static void intel_init_display(struct drm_device *dev)
14079{
14080 struct drm_i915_private *dev_priv = dev->dev_private;
14081
ee9300bb
DV		 14082 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14083 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14084 else if (IS_CHERRYVIEW(dev))
14085 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14086 else if (IS_VALLEYVIEW(dev))
14087 dev_priv->display.find_dpll = vlv_find_best_dpll;
14088 else if (IS_PINEVIEW(dev))
14089 dev_priv->display.find_dpll = pnv_find_best_dpll;
14090 else
14091 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14092
bc8d7dff
DL		 14093 if (INTEL_INFO(dev)->gen >= 9) {
14094 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14095 dev_priv->display.get_initial_plane_config =
14096 skylake_get_initial_plane_config;
bc8d7dff
DL		 14097 dev_priv->display.crtc_compute_clock =
14098 haswell_crtc_compute_clock;
14099 dev_priv->display.crtc_enable = haswell_crtc_enable;
14100 dev_priv->display.crtc_disable = haswell_crtc_disable;
14101 dev_priv->display.off = ironlake_crtc_off;
14102 dev_priv->display.update_primary_plane =
14103 skylake_update_primary_plane;
14104 } else if (HAS_DDI(dev)) {
0e8ffe1b 14105 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14106 dev_priv->display.get_initial_plane_config =
14107 ironlake_get_initial_plane_config;
797d0259
ACO		 14108 dev_priv->display.crtc_compute_clock =
14109 haswell_crtc_compute_clock;
4f771f10
PZ		 14110 dev_priv->display.crtc_enable = haswell_crtc_enable;
14111 dev_priv->display.crtc_disable = haswell_crtc_disable;
df8ad70c 14112 dev_priv->display.off = ironlake_crtc_off;
bc8d7dff
DL		 14113 dev_priv->display.update_primary_plane =
14114 ironlake_update_primary_plane;
09b4ddf9 14115 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14116 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14117 dev_priv->display.get_initial_plane_config =
14118 ironlake_get_initial_plane_config;
3fb37703
ACO		 14119 dev_priv->display.crtc_compute_clock =
14120 ironlake_crtc_compute_clock;
76e5a89c
DV		 14121 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14122 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 14123 dev_priv->display.off = ironlake_crtc_off;
262ca2b0
MR		 14124 dev_priv->display.update_primary_plane =
14125 ironlake_update_primary_plane;
89b667f8
JB		 14126 } else if (IS_VALLEYVIEW(dev)) {
14127 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14128 dev_priv->display.get_initial_plane_config =
14129 i9xx_get_initial_plane_config;
d6dfee7a 14130 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14131 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14132 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14133 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14134 dev_priv->display.update_primary_plane =
14135 i9xx_update_primary_plane;
f564048e 14136 } else {
0e8ffe1b 14137 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14138 dev_priv->display.get_initial_plane_config =
14139 i9xx_get_initial_plane_config;
d6dfee7a 14140 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14141 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14142 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 14143 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14144 dev_priv->display.update_primary_plane =
14145 i9xx_update_primary_plane;
f564048e 14146 }
e70236a8 14147
e70236a8 14148 /* Returns the core display clock speed */
1652d19e
VS		 14149 if (IS_SKYLAKE(dev))
14150 dev_priv->display.get_display_clock_speed =
14151 skylake_get_display_clock_speed;
14152 else if (IS_BROADWELL(dev))
14153 dev_priv->display.get_display_clock_speed =
14154 broadwell_get_display_clock_speed;
14155 else if (IS_HASWELL(dev))
14156 dev_priv->display.get_display_clock_speed =
14157 haswell_get_display_clock_speed;
14158 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14159 dev_priv->display.get_display_clock_speed =
14160 valleyview_get_display_clock_speed;
b37a6434
VS		 14161 else if (IS_GEN5(dev))
14162 dev_priv->display.get_display_clock_speed =
14163 ilk_get_display_clock_speed;
a7c66cd8
VS		 14164 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14165 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 14166 dev_priv->display.get_display_clock_speed =
14167 i945_get_display_clock_speed;
14168 else if (IS_I915G(dev))
14169 dev_priv->display.get_display_clock_speed =
14170 i915_get_display_clock_speed;
257a7ffc 14171 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14172 dev_priv->display.get_display_clock_speed =
14173 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14174 else if (IS_PINEVIEW(dev))
14175 dev_priv->display.get_display_clock_speed =
14176 pnv_get_display_clock_speed;
e70236a8
JB		 14177 else if (IS_I915GM(dev))
14178 dev_priv->display.get_display_clock_speed =
14179 i915gm_get_display_clock_speed;
14180 else if (IS_I865G(dev))
14181 dev_priv->display.get_display_clock_speed =
14182 i865_get_display_clock_speed;
f0f8a9ce 14183 else if (IS_I85X(dev))
e70236a8
JB		 14184 dev_priv->display.get_display_clock_speed =
14185 i855_get_display_clock_speed;
14186 else /* 852, 830 */
14187 dev_priv->display.get_display_clock_speed =
14188 i830_get_display_clock_speed;
14189
7c10a2b5 14190 if (IS_GEN5(dev)) {
3bb11b53 14191 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14192 } else if (IS_GEN6(dev)) {
14193 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14194 } else if (IS_IVYBRIDGE(dev)) {
14195 /* FIXME: detect B0+ stepping and use auto training */
14196 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14197 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14198 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
30a970c6
JB		 14199 } else if (IS_VALLEYVIEW(dev)) {
14200 dev_priv->display.modeset_global_resources =
14201 valleyview_modeset_global_resources;
f8437dd1
VK		 14202 } else if (IS_BROXTON(dev)) {
14203 dev_priv->display.modeset_global_resources =
14204 broxton_modeset_global_resources;
e70236a8 14205 }
8c9f3aaf 14206
8c9f3aaf
JB		 14207 switch (INTEL_INFO(dev)->gen) {
14208 case 2:
14209 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14210 break;
14211
14212 case 3:
14213 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14214 break;
14215
14216 case 4:
14217 case 5:
14218 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14219 break;
14220
14221 case 6:
14222 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14223 break;
7c9017e5 14224 case 7:
4e0bbc31 14225 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14226 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14227 break;
830c81db 14228 case 9:
ba343e02
TU		 14229 /* Drop through - unsupported since execlist only. */
14230 default:
14231 /* Default just returns -ENODEV to indicate unsupported */
14232 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14233 }
7bd688cd
JN		 14234
14235 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14236
14237 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14238}
14239
b690e96c
JB		 14240/*
14241 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14242 * resume, or other times. This quirk makes sure that's the case for
14243 * affected systems.
14244 */
0206e353 14245static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14246{
14247 struct drm_i915_private *dev_priv = dev->dev_private;
14248
14249 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14250 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14251}
14252
b6b5d049
VS		 14253static void quirk_pipeb_force(struct drm_device *dev)
14254{
14255 struct drm_i915_private *dev_priv = dev->dev_private;
14256
14257 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14258 DRM_INFO("applying pipe b force quirk\n");
14259}
14260
435793df
KP		 14261/*
14262 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14263 */
14264static void quirk_ssc_force_disable(struct drm_device *dev)
14265{
14266 struct drm_i915_private *dev_priv = dev->dev_private;
14267 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14268 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14269}
14270
4dca20ef 14271/*
5a15ab5b
CE		 14272 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14273 * brightness value
4dca20ef
CE		 14274 */
14275static void quirk_invert_brightness(struct drm_device *dev)
14276{
14277 struct drm_i915_private *dev_priv = dev->dev_private;
14278 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14279 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14280}
14281
9c72cc6f
SD		 14282/* Some VBT's incorrectly indicate no backlight is present */
14283static void quirk_backlight_present(struct drm_device *dev)
14284{
14285 struct drm_i915_private *dev_priv = dev->dev_private;
14286 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14287 DRM_INFO("applying backlight present quirk\n");
14288}
14289
b690e96c
JB		 14290struct intel_quirk {
14291 int device;
14292 int subsystem_vendor;
14293 int subsystem_device;
14294 void (*hook)(struct drm_device *dev);
14295};
14296
5f85f176
EE		 14297/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14298struct intel_dmi_quirk {
14299 void (*hook)(struct drm_device *dev);
14300 const struct dmi_system_id (*dmi_id_list)[];
14301};
14302
14303static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14304{
14305 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14306 return 1;
14307}
14308
14309static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14310 {
14311 .dmi_id_list = &(const struct dmi_system_id[]) {
14312 {
14313 .callback = intel_dmi_reverse_brightness,
14314 .ident = "NCR Corporation",
14315 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14316 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14317 },
14318 },
14319 { } /* terminating entry */
14320 },
14321 .hook = quirk_invert_brightness,
14322 },
14323};
14324
c43b5634 14325static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14326 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14327 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14328
b690e96c
JB		 14329 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14330 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14331
5f080c0f
VS		 14332 /* 830 needs to leave pipe A & dpll A up */
14333 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14334
b6b5d049
VS		 14335 /* 830 needs to leave pipe B & dpll B up */
14336 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14337
435793df
KP		 14338 /* Lenovo U160 cannot use SSC on LVDS */
14339 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14340
14341 /* Sony Vaio Y cannot use SSC on LVDS */
14342 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14343
be505f64
AH		 14344 /* Acer Aspire 5734Z must invert backlight brightness */
14345 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14346
14347 /* Acer/eMachines G725 */
14348 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14349
14350 /* Acer/eMachines e725 */
14351 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14352
14353 /* Acer/Packard Bell NCL20 */
14354 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14355
14356 /* Acer Aspire 4736Z */
14357 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14358
14359 /* Acer Aspire 5336 */
14360 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14361
14362 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14363 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14364
dfb3d47b
SD		 14365 /* Acer C720 Chromebook (Core i3 4005U) */
14366 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14367
b2a9601c 14368 /* Apple Macbook 2,1 (Core 2 T7400) */
14369 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14370
d4967d8c
SD		 14371 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14372 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14373
14374 /* HP Chromebook 14 (Celeron 2955U) */
14375 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14376
14377 /* Dell Chromebook 11 */
14378 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14379};
14380
14381static void intel_init_quirks(struct drm_device *dev)
14382{
14383 struct pci_dev *d = dev->pdev;
14384 int i;
14385
14386 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14387 struct intel_quirk *q = &intel_quirks[i];
14388
14389 if (d->device == q->device &&
14390 (d->subsystem_vendor == q->subsystem_vendor ||
14391 q->subsystem_vendor == PCI_ANY_ID) &&
14392 (d->subsystem_device == q->subsystem_device ||
14393 q->subsystem_device == PCI_ANY_ID))
14394 q->hook(dev);
14395 }
5f85f176
EE		 14396 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14397 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14398 intel_dmi_quirks[i].hook(dev);
14399 }
b690e96c
JB		 14400}
14401
9cce37f4
JB		 14402/* Disable the VGA plane that we never use */
14403static void i915_disable_vga(struct drm_device *dev)
14404{
14405 struct drm_i915_private *dev_priv = dev->dev_private;
14406 u8 sr1;
766aa1c4 14407 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14408
2b37c616 14409 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14410 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14411 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14412 sr1 = inb(VGA_SR_DATA);
14413 outb(sr1 | 1<<5, VGA_SR_DATA);
14414 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14415 udelay(300);
14416
01f5a626 14417 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14418 POSTING_READ(vga_reg);
14419}
14420
f817586c
DV		 14421void intel_modeset_init_hw(struct drm_device *dev)
14422{
a8f78b58
ED		 14423 intel_prepare_ddi(dev);
14424
f8bf63fd
VS		 14425 if (IS_VALLEYVIEW(dev))
14426 vlv_update_cdclk(dev);
14427
f817586c
DV		 14428 intel_init_clock_gating(dev);
14429
8090c6b9 14430 intel_enable_gt_powersave(dev);
f817586c
DV		 14431}
14432
79e53945
JB		 14433void intel_modeset_init(struct drm_device *dev)
14434{
652c393a 14435 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14436 int sprite, ret;
8cc87b75 14437 enum pipe pipe;
46f297fb 14438 struct intel_crtc *crtc;
79e53945
JB		 14439
14440 drm_mode_config_init(dev);
14441
14442 dev->mode_config.min_width = 0;
14443 dev->mode_config.min_height = 0;
14444
019d96cb
DA		 14445 dev->mode_config.preferred_depth = 24;
14446 dev->mode_config.prefer_shadow = 1;
14447
25bab385
TU		 14448 dev->mode_config.allow_fb_modifiers = true;
14449
e6ecefaa 14450 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14451
b690e96c
JB		 14452 intel_init_quirks(dev);
14453
1fa61106
ED		 14454 intel_init_pm(dev);
14455
e3c74757
BW		 14456 if (INTEL_INFO(dev)->num_pipes == 0)
14457 return;
14458
e70236a8 14459 intel_init_display(dev);
7c10a2b5 14460 intel_init_audio(dev);
e70236a8 14461
a6c45cf0
CW		 14462 if (IS_GEN2(dev)) {
14463 dev->mode_config.max_width = 2048;
14464 dev->mode_config.max_height = 2048;
14465 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14466 dev->mode_config.max_width = 4096;
14467 dev->mode_config.max_height = 4096;
79e53945 14468 } else {
a6c45cf0
CW		 14469 dev->mode_config.max_width = 8192;
14470 dev->mode_config.max_height = 8192;
79e53945 14471 }
068be561 14472
dc41c154
VS		 14473 if (IS_845G(dev) || IS_I865G(dev)) {
14474 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14475 dev->mode_config.cursor_height = 1023;
14476 } else if (IS_GEN2(dev)) {
068be561
DL		 14477 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14478 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14479 } else {
14480 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14481 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14482 }
14483
5d4545ae 14484 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14485
28c97730 14486 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14487 INTEL_INFO(dev)->num_pipes,
14488 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14489
055e393f 14490 for_each_pipe(dev_priv, pipe) {
8cc87b75 14491 intel_crtc_init(dev, pipe);
3bdcfc0c 14492 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14493 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14494 if (ret)
06da8da2 14495 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14496 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14497 }
79e53945
JB		 14498 }
14499
f42bb70d
JB		 14500 intel_init_dpio(dev);
14501
e72f9fbf 14502 intel_shared_dpll_init(dev);
ee7b9f93 14503
9cce37f4
JB		 14504 /* Just disable it once at startup */
14505 i915_disable_vga(dev);
79e53945 14506 intel_setup_outputs(dev);
11be49eb
CW		 14507
14508 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 14509 intel_fbc_disable(dev);
fa9fa083 14510
6e9f798d 14511 drm_modeset_lock_all(dev);
fa9fa083 14512 intel_modeset_setup_hw_state(dev, false);
6e9f798d 14513 drm_modeset_unlock_all(dev);
46f297fb 14514
d3fcc808 14515 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 14516 if (!crtc->active)
14517 continue;
14518
46f297fb 14519 /*
46f297fb
JB		 14520 * Note that reserving the BIOS fb up front prevents us
14521 * from stuffing other stolen allocations like the ring
14522 * on top. This prevents some ugliness at boot time, and
14523 * can even allow for smooth boot transitions if the BIOS
14524 * fb is large enough for the active pipe configuration.
14525 */
5724dbd1
DL		 14526 if (dev_priv->display.get_initial_plane_config) {
14527 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 14528 &crtc->plane_config);
14529 /*
14530 * If the fb is shared between multiple heads, we'll
14531 * just get the first one.
14532 */
f6936e29 14533 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 14534 }
46f297fb 14535 }
2c7111db
CW		 14536}
14537
7fad798e
DV		 14538static void intel_enable_pipe_a(struct drm_device *dev)
14539{
14540 struct intel_connector *connector;
14541 struct drm_connector *crt = NULL;
14542 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14543 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14544
14545 /* We can't just switch on the pipe A, we need to set things up with a
14546 * proper mode and output configuration. As a gross hack, enable pipe A
14547 * by enabling the load detect pipe once. */
3a3371ff 14548 for_each_intel_connector(dev, connector) {
7fad798e
DV		 14549 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14550 crt = &connector->base;
14551 break;
14552 }
14553 }
14554
14555 if (!crt)
14556 return;
14557
208bf9fd 14558 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14559 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 14560}
14561
fa555837
DV		 14562static bool
14563intel_check_plane_mapping(struct intel_crtc *crtc)
14564{
7eb552ae
BW		 14565 struct drm_device *dev = crtc->base.dev;
14566 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 14567 u32 reg, val;
14568
7eb552ae 14569 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 14570 return true;
14571
14572 reg = DSPCNTR(!crtc->plane);
14573 val = I915_READ(reg);
14574
14575 if ((val & DISPLAY_PLANE_ENABLE) &&
14576 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14577 return false;
14578
14579 return true;
14580}
14581
24929352
DV		 14582static void intel_sanitize_crtc(struct intel_crtc *crtc)
14583{
14584 struct drm_device *dev = crtc->base.dev;
14585 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 14586 u32 reg;
24929352 14587
24929352 14588 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 14589 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 14590 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14591
d3eaf884 14592 /* restore vblank interrupts to correct state */
9625604c 14593 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 14594 if (crtc->active) {
14595 update_scanline_offset(crtc);
9625604c
DV		 14596 drm_crtc_vblank_on(&crtc->base);
14597 }
d3eaf884 14598
24929352 14599 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 14600 * disable the crtc (and hence change the state) if it is wrong. Note
14601 * that gen4+ has a fixed plane -> pipe mapping. */
14602 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 14603 struct intel_connector *connector;
14604 bool plane;
14605
24929352
DV		 14606 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14607 crtc->base.base.id);
14608
14609 /* Pipe has the wrong plane attached and the plane is active.
14610 * Temporarily change the plane mapping and disable everything
14611 * ... */
14612 plane = crtc->plane;
b70709a6 14613 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 14614 crtc->plane = !plane;
ce22dba9 14615 intel_crtc_disable_planes(&crtc->base);
24929352
DV		 14616 dev_priv->display.crtc_disable(&crtc->base);
14617 crtc->plane = plane;
14618
14619 /* ... and break all links. */
3a3371ff 14620 for_each_intel_connector(dev, connector) {
24929352
DV		 14621 if (connector->encoder->base.crtc != &crtc->base)
14622 continue;
14623
7f1950fb
EE		 14624 connector->base.dpms = DRM_MODE_DPMS_OFF;
14625 connector->base.encoder = NULL;
24929352 14626 }
7f1950fb
EE		 14627 /* multiple connectors may have the same encoder:
14628 * handle them and break crtc link separately */
3a3371ff 14629 for_each_intel_connector(dev, connector)
7f1950fb
EE		 14630 if (connector->encoder->base.crtc == &crtc->base) {
14631 connector->encoder->base.crtc = NULL;
14632 connector->encoder->connectors_active = false;
14633 }
24929352
DV		 14634
14635 WARN_ON(crtc->active);
83d65738 14636 crtc->base.state->enable = false;
49d6fa21 14637 crtc->base.state->active = false;
24929352
DV		 14638 crtc->base.enabled = false;
14639 }
24929352 14640
7fad798e
DV		 14641 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14642 crtc->pipe == PIPE_A && !crtc->active) {
14643 /* BIOS forgot to enable pipe A, this mostly happens after
14644 * resume. Force-enable the pipe to fix this, the update_dpms
14645 * call below we restore the pipe to the right state, but leave
14646 * the required bits on. */
14647 intel_enable_pipe_a(dev);
14648 }
14649
24929352
DV		 14650 /* Adjust the state of the output pipe according to whether we
14651 * have active connectors/encoders. */
14652 intel_crtc_update_dpms(&crtc->base);
14653
83d65738 14654 if (crtc->active != crtc->base.state->enable) {
24929352
DV		 14655 struct intel_encoder *encoder;
14656
14657 /* This can happen either due to bugs in the get_hw_state
14658 * functions or because the pipe is force-enabled due to the
14659 * pipe A quirk. */
14660 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14661 crtc->base.base.id,
83d65738 14662 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 14663 crtc->active ? "enabled" : "disabled");
14664
83d65738 14665 crtc->base.state->enable = crtc->active;
49d6fa21 14666 crtc->base.state->active = crtc->active;
24929352
DV		 14667 crtc->base.enabled = crtc->active;
14668
14669 /* Because we only establish the connector -> encoder ->
14670 * crtc links if something is active, this means the
14671 * crtc is now deactivated. Break the links. connector
14672 * -> encoder links are only establish when things are
14673 * actually up, hence no need to break them. */
14674 WARN_ON(crtc->active);
14675
14676 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14677 WARN_ON(encoder->connectors_active);
14678 encoder->base.crtc = NULL;
14679 }
14680 }
c5ab3bc0 14681
a3ed6aad 14682 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 14683 /*
14684 * We start out with underrun reporting disabled to avoid races.
14685 * For correct bookkeeping mark this on active crtcs.
14686 *
c5ab3bc0
DV		 14687 * Also on gmch platforms we dont have any hardware bits to
14688 * disable the underrun reporting. Which means we need to start
14689 * out with underrun reporting disabled also on inactive pipes,
14690 * since otherwise we'll complain about the garbage we read when
14691 * e.g. coming up after runtime pm.
14692 *
4cc31489
DV		 14693 * No protection against concurrent access is required - at
14694 * worst a fifo underrun happens which also sets this to false.
14695 */
14696 crtc->cpu_fifo_underrun_disabled = true;
14697 crtc->pch_fifo_underrun_disabled = true;
14698 }
24929352
DV		 14699}
14700
14701static void intel_sanitize_encoder(struct intel_encoder *encoder)
14702{
14703 struct intel_connector *connector;
14704 struct drm_device *dev = encoder->base.dev;
14705
14706 /* We need to check both for a crtc link (meaning that the
14707 * encoder is active and trying to read from a pipe) and the
14708 * pipe itself being active. */
14709 bool has_active_crtc = encoder->base.crtc &&
14710 to_intel_crtc(encoder->base.crtc)->active;
14711
14712 if (encoder->connectors_active && !has_active_crtc) {
14713 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14714 encoder->base.base.id,
8e329a03 14715 encoder->base.name);
24929352
DV		 14716
14717 /* Connector is active, but has no active pipe. This is
14718 * fallout from our resume register restoring. Disable
14719 * the encoder manually again. */
14720 if (encoder->base.crtc) {
14721 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14722 encoder->base.base.id,
8e329a03 14723 encoder->base.name);
24929352 14724 encoder->disable(encoder);
a62d1497
VS		 14725 if (encoder->post_disable)
14726 encoder->post_disable(encoder);
24929352 14727 }
7f1950fb
EE		 14728 encoder->base.crtc = NULL;
14729 encoder->connectors_active = false;
24929352
DV		 14730
14731 /* Inconsistent output/port/pipe state happens presumably due to
14732 * a bug in one of the get_hw_state functions. Or someplace else
14733 * in our code, like the register restore mess on resume. Clamp
14734 * things to off as a safer default. */
3a3371ff 14735 for_each_intel_connector(dev, connector) {
24929352
DV		 14736 if (connector->encoder != encoder)
14737 continue;
7f1950fb
EE		 14738 connector->base.dpms = DRM_MODE_DPMS_OFF;
14739 connector->base.encoder = NULL;
24929352
DV		 14740 }
14741 }
14742 /* Enabled encoders without active connectors will be fixed in
14743 * the crtc fixup. */
14744}
14745
04098753 14746void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 14747{
14748 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 14749 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 14750
04098753
ID		 14751 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14752 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14753 i915_disable_vga(dev);
14754 }
14755}
14756
14757void i915_redisable_vga(struct drm_device *dev)
14758{
14759 struct drm_i915_private *dev_priv = dev->dev_private;
14760
8dc8a27c
PZ		 14761 /* This function can be called both from intel_modeset_setup_hw_state or
14762 * at a very early point in our resume sequence, where the power well
14763 * structures are not yet restored. Since this function is at a very
14764 * paranoid "someone might have enabled VGA while we were not looking"
14765 * level, just check if the power well is enabled instead of trying to
14766 * follow the "don't touch the power well if we don't need it" policy
14767 * the rest of the driver uses. */
f458ebbc 14768 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 14769 return;
14770
04098753 14771 i915_redisable_vga_power_on(dev);
0fde901f
KM		 14772}
14773
98ec7739
VS		 14774static bool primary_get_hw_state(struct intel_crtc *crtc)
14775{
14776 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
14777
14778 if (!crtc->active)
14779 return false;
14780
14781 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
14782}
14783
30e984df 14784static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 14785{
14786 struct drm_i915_private *dev_priv = dev->dev_private;
14787 enum pipe pipe;
24929352
DV		 14788 struct intel_crtc *crtc;
14789 struct intel_encoder *encoder;
14790 struct intel_connector *connector;
5358901f 14791 int i;
24929352 14792
d3fcc808 14793 for_each_intel_crtc(dev, crtc) {
b70709a6
ML		 14794 struct drm_plane *primary = crtc->base.primary;
14795 struct intel_plane_state *plane_state;
14796
6e3c9717 14797 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 14798
6e3c9717 14799 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 14800
0e8ffe1b 14801 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 14802 crtc->config);
24929352 14803
83d65738 14804 crtc->base.state->enable = crtc->active;
49d6fa21 14805 crtc->base.state->active = crtc->active;
24929352 14806 crtc->base.enabled = crtc->active;
b70709a6
ML		 14807
14808 plane_state = to_intel_plane_state(primary->state);
14809 plane_state->visible = primary_get_hw_state(crtc);
24929352
DV		 14810
14811 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
14812 crtc->base.base.id,
14813 crtc->active ? "enabled" : "disabled");
14814 }
14815
5358901f
DV		 14816 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14817 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14818
3e369b76
ACO		 14819 pll->on = pll->get_hw_state(dev_priv, pll,
14820 &pll->config.hw_state);
5358901f 14821 pll->active = 0;
3e369b76 14822 pll->config.crtc_mask = 0;
d3fcc808 14823 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 14824 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 14825 pll->active++;
3e369b76 14826 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 14827 }
5358901f 14828 }
5358901f 14829
1e6f2ddc 14830 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 14831 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 14832
3e369b76 14833 if (pll->config.crtc_mask)
bd2bb1b9 14834 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 14835 }
14836
b2784e15 14837 for_each_intel_encoder(dev, encoder) {
24929352
DV		 14838 pipe = 0;
14839
14840 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 14841 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14842 encoder->base.crtc = &crtc->base;
6e3c9717 14843 encoder->get_config(encoder, crtc->config);
24929352
DV		 14844 } else {
14845 encoder->base.crtc = NULL;
14846 }
14847
14848 encoder->connectors_active = false;
6f2bcceb 14849 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 14850 encoder->base.base.id,
8e329a03 14851 encoder->base.name,
24929352 14852 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 14853 pipe_name(pipe));
24929352
DV		 14854 }
14855
3a3371ff 14856 for_each_intel_connector(dev, connector) {
24929352
DV		 14857 if (connector->get_hw_state(connector)) {
14858 connector->base.dpms = DRM_MODE_DPMS_ON;
14859 connector->encoder->connectors_active = true;
14860 connector->base.encoder = &connector->encoder->base;
14861 } else {
14862 connector->base.dpms = DRM_MODE_DPMS_OFF;
14863 connector->base.encoder = NULL;
14864 }
14865 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
14866 connector->base.base.id,
c23cc417 14867 connector->base.name,
24929352
DV		 14868 connector->base.encoder ? "enabled" : "disabled");
14869 }
30e984df
DV		 14870}
14871
14872/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
14873 * and i915 state tracking structures. */
14874void intel_modeset_setup_hw_state(struct drm_device *dev,
14875 bool force_restore)
14876{
14877 struct drm_i915_private *dev_priv = dev->dev_private;
14878 enum pipe pipe;
30e984df
DV		 14879 struct intel_crtc *crtc;
14880 struct intel_encoder *encoder;
35c95375 14881 int i;
30e984df
DV		 14882
14883 intel_modeset_readout_hw_state(dev);
24929352 14884
babea61d
JB		 14885 /*
14886 * Now that we have the config, copy it to each CRTC struct
14887 * Note that this could go away if we move to using crtc_config
14888 * checking everywhere.
14889 */
d3fcc808 14890 for_each_intel_crtc(dev, crtc) {
d330a953 14891 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 14892 intel_mode_from_pipe_config(&crtc->base.mode,
14893 crtc->config);
babea61d
JB		 14894 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
14895 crtc->base.base.id);
14896 drm_mode_debug_printmodeline(&crtc->base.mode);
14897 }
14898 }
14899
24929352 14900 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 14901 for_each_intel_encoder(dev, encoder) {
24929352
DV		 14902 intel_sanitize_encoder(encoder);
14903 }
14904
055e393f 14905 for_each_pipe(dev_priv, pipe) {
24929352
DV		 14906 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
14907 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 14908 intel_dump_pipe_config(crtc, crtc->config,
14909 "[setup_hw_state]");
24929352 14910 }
9a935856 14911
d29b2f9d
ACO		 14912 intel_modeset_update_connector_atomic_state(dev);
14913
35c95375
DV		 14914 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
14915 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
14916
14917 if (!pll->on || pll->active)
14918 continue;
14919
14920 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
14921
14922 pll->disable(dev_priv, pll);
14923 pll->on = false;
14924 }
14925
3078999f
PB		 14926 if (IS_GEN9(dev))
14927 skl_wm_get_hw_state(dev);
14928 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 14929 ilk_wm_get_hw_state(dev);
14930
45e2b5f6 14931 if (force_restore) {
7d0bc1ea
VS		 14932 i915_redisable_vga(dev);
14933
f30da187
DV		 14934 /*
14935 * We need to use raw interfaces for restoring state to avoid
14936 * checking (bogus) intermediate states.
14937 */
055e393f 14938 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 14939 struct drm_crtc *crtc =
14940 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 14941
83a57153 14942 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 14943 }
14944 } else {
14945 intel_modeset_update_staged_output_state(dev);
14946 }
8af6cf88
DV		 14947
14948 intel_modeset_check_state(dev);
2c7111db
CW		 14949}
14950
14951void intel_modeset_gem_init(struct drm_device *dev)
14952{
92122789 14953 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 14954 struct drm_crtc *c;
2ff8fde1 14955 struct drm_i915_gem_object *obj;
e0d6149b 14956 int ret;
484b41dd 14957
ae48434c
ID		 14958 mutex_lock(&dev->struct_mutex);
14959 intel_init_gt_powersave(dev);
14960 mutex_unlock(&dev->struct_mutex);
14961
92122789
JB		 14962 /*
14963 * There may be no VBT; and if the BIOS enabled SSC we can
14964 * just keep using it to avoid unnecessary flicker. Whereas if the
14965 * BIOS isn't using it, don't assume it will work even if the VBT
14966 * indicates as much.
14967 */
14968 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14969 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14970 DREF_SSC1_ENABLE);
14971
1833b134 14972 intel_modeset_init_hw(dev);
02e792fb
DV		 14973
14974 intel_setup_overlay(dev);
484b41dd
JB		 14975
14976 /*
14977 * Make sure any fbs we allocated at startup are properly
14978 * pinned & fenced. When we do the allocation it's too early
14979 * for this.
14980 */
70e1e0ec 14981 for_each_crtc(dev, c) {
2ff8fde1
MR		 14982 obj = intel_fb_obj(c->primary->fb);
14983 if (obj == NULL)
484b41dd
JB		 14984 continue;
14985
e0d6149b
TU		 14986 mutex_lock(&dev->struct_mutex);
14987 ret = intel_pin_and_fence_fb_obj(c->primary,
14988 c->primary->fb,
14989 c->primary->state,
14990 NULL);
14991 mutex_unlock(&dev->struct_mutex);
14992 if (ret) {
484b41dd
JB		 14993 DRM_ERROR("failed to pin boot fb on pipe %d\n",
14994 to_intel_crtc(c)->pipe);
66e514c1
DA		 14995 drm_framebuffer_unreference(c->primary->fb);
14996 c->primary->fb = NULL;
afd65eb4 14997 update_state_fb(c->primary);
484b41dd
JB		 14998 }
14999 }
0962c3c9
VS		 15000
15001 intel_backlight_register(dev);
79e53945
JB		 15002}
15003
4932e2c3
ID		 15004void intel_connector_unregister(struct intel_connector *intel_connector)
15005{
15006 struct drm_connector *connector = &intel_connector->base;
15007
15008 intel_panel_destroy_backlight(connector);
34ea3d38 15009 drm_connector_unregister(connector);
4932e2c3
ID		 15010}
15011
79e53945
JB		 15012void intel_modeset_cleanup(struct drm_device *dev)
15013{
652c393a 15014 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15015 struct drm_connector *connector;
652c393a 15016
2eb5252e
ID		 15017 intel_disable_gt_powersave(dev);
15018
0962c3c9
VS		 15019 intel_backlight_unregister(dev);
15020
fd0c0642
DV		 15021 /*
15022 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15023 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15024 * experience fancy races otherwise.
15025 */
2aeb7d3a 15026 intel_irq_uninstall(dev_priv);
eb21b92b 15027
fd0c0642
DV		 15028 /*
15029 * Due to the hpd irq storm handling the hotplug work can re-arm the
15030 * poll handlers. Hence disable polling after hpd handling is shut down.
15031 */
f87ea761 15032 drm_kms_helper_poll_fini(dev);
fd0c0642 15033
652c393a
JB		 15034 mutex_lock(&dev->struct_mutex);
15035
723bfd70
JB		 15036 intel_unregister_dsm_handler();
15037
7ff0ebcc 15038 intel_fbc_disable(dev);
e70236a8 15039
69341a5e
KH		 15040 mutex_unlock(&dev->struct_mutex);
15041
1630fe75
CW		 15042 /* flush any delayed tasks or pending work */
15043 flush_scheduled_work();
15044
db31af1d
JN		 15045 /* destroy the backlight and sysfs files before encoders/connectors */
15046 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15047 struct intel_connector *intel_connector;
15048
15049 intel_connector = to_intel_connector(connector);
15050 intel_connector->unregister(intel_connector);
db31af1d 15051 }
d9255d57 15052
79e53945 15053 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15054
15055 intel_cleanup_overlay(dev);
ae48434c
ID		 15056
15057 mutex_lock(&dev->struct_mutex);
15058 intel_cleanup_gt_powersave(dev);
15059 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15060}
15061
f1c79df3
ZW		 15062/*
15063 * Return which encoder is currently attached for connector.
15064 */
df0e9248 15065struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15066{
df0e9248
CW		 15067 return &intel_attached_encoder(connector)->base;
15068}
f1c79df3 15069
df0e9248
CW		 15070void intel_connector_attach_encoder(struct intel_connector *connector,
15071 struct intel_encoder *encoder)
15072{
15073 connector->encoder = encoder;
15074 drm_mode_connector_attach_encoder(&connector->base,
15075 &encoder->base);
79e53945 15076}
28d52043
DA		 15077
15078/*
15079 * set vga decode state - true == enable VGA decode
15080 */
15081int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15082{
15083 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15084 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15085 u16 gmch_ctrl;
15086
75fa041d
CW		 15087 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15088 DRM_ERROR("failed to read control word\n");
15089 return -EIO;
15090 }
15091
c0cc8a55
CW		 15092 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15093 return 0;
15094
28d52043
DA		 15095 if (state)
15096 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15097 else
15098 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15099
15100 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15101 DRM_ERROR("failed to write control word\n");
15102 return -EIO;
15103 }
15104
28d52043
DA		 15105 return 0;
15106}
c4a1d9e4 15107
c4a1d9e4 15108struct intel_display_error_state {
ff57f1b0
PZ		 15109
15110 u32 power_well_driver;
15111
63b66e5b
CW		 15112 int num_transcoders;
15113
c4a1d9e4
CW		 15114 struct intel_cursor_error_state {
15115 u32 control;
15116 u32 position;
15117 u32 base;
15118 u32 size;
52331309 15119 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15120
15121 struct intel_pipe_error_state {
ddf9c536 15122 bool power_domain_on;
c4a1d9e4 15123 u32 source;
f301b1e1 15124 u32 stat;
52331309 15125 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15126
15127 struct intel_plane_error_state {
15128 u32 control;
15129 u32 stride;
15130 u32 size;
15131 u32 pos;
15132 u32 addr;
15133 u32 surface;
15134 u32 tile_offset;
52331309 15135 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15136
15137 struct intel_transcoder_error_state {
ddf9c536 15138 bool power_domain_on;
63b66e5b
CW		 15139 enum transcoder cpu_transcoder;
15140
15141 u32 conf;
15142
15143 u32 htotal;
15144 u32 hblank;
15145 u32 hsync;
15146 u32 vtotal;
15147 u32 vblank;
15148 u32 vsync;
15149 } transcoder[4];
c4a1d9e4
CW		 15150};
15151
15152struct intel_display_error_state *
15153intel_display_capture_error_state(struct drm_device *dev)
15154{
fbee40df 15155 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15156 struct intel_display_error_state *error;
63b66e5b
CW		 15157 int transcoders[] = {
15158 TRANSCODER_A,
15159 TRANSCODER_B,
15160 TRANSCODER_C,
15161 TRANSCODER_EDP,
15162 };
c4a1d9e4
CW		 15163 int i;
15164
63b66e5b
CW		 15165 if (INTEL_INFO(dev)->num_pipes == 0)
15166 return NULL;
15167
9d1cb914 15168 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15169 if (error == NULL)
15170 return NULL;
15171
190be112 15172 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15173 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15174
055e393f 15175 for_each_pipe(dev_priv, i) {
ddf9c536 15176 error->pipe[i].power_domain_on =
f458ebbc
DV		 15177 __intel_display_power_is_enabled(dev_priv,
15178 POWER_DOMAIN_PIPE(i));
ddf9c536 15179 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15180 continue;
15181
5efb3e28
VS		 15182 error->cursor[i].control = I915_READ(CURCNTR(i));
15183 error->cursor[i].position = I915_READ(CURPOS(i));
15184 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15185
15186 error->plane[i].control = I915_READ(DSPCNTR(i));
15187 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15188 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15189 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15190 error->plane[i].pos = I915_READ(DSPPOS(i));
15191 }
ca291363
PZ		 15192 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15193 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15194 if (INTEL_INFO(dev)->gen >= 4) {
15195 error->plane[i].surface = I915_READ(DSPSURF(i));
15196 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15197 }
15198
c4a1d9e4 15199 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15200
3abfce77 15201 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15202 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15203 }
15204
15205 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15206 if (HAS_DDI(dev_priv->dev))
15207 error->num_transcoders++; /* Account for eDP. */
15208
15209 for (i = 0; i < error->num_transcoders; i++) {
15210 enum transcoder cpu_transcoder = transcoders[i];
15211
ddf9c536 15212 error->transcoder[i].power_domain_on =
f458ebbc 15213 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15214 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15215 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15216 continue;
15217
63b66e5b
CW		 15218 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15219
15220 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15221 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15222 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15223 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15224 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15225 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15226 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15227 }
15228
15229 return error;
15230}
15231
edc3d884
MK		 15232#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15233
c4a1d9e4 15234void
edc3d884 15235intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15236 struct drm_device *dev,
15237 struct intel_display_error_state *error)
15238{
055e393f 15239 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15240 int i;
15241
63b66e5b
CW		 15242 if (!error)
15243 return;
15244
edc3d884 15245 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15246 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15247 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15248 error->power_well_driver);
055e393f 15249 for_each_pipe(dev_priv, i) {
edc3d884 15250 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15251 err_printf(m, " Power: %s\n",
15252 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15253 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15254 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15255
15256 err_printf(m, "Plane [%d]:\n", i);
15257 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15258 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15259 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15260 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15261 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15262 }
4b71a570 15263 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15264 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15265 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15266 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15267 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15268 }
15269
edc3d884
MK		 15270 err_printf(m, "Cursor [%d]:\n", i);
15271 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15272 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15273 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15274 }
63b66e5b
CW		 15275
15276 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15277 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15278 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15279 err_printf(m, " Power: %s\n",
15280 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15281 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15282 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15283 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15284 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15285 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15286 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15287 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15288 }
c4a1d9e4 15289}
e2fcdaa9
VS		 15290
15291void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15292{
15293 struct intel_crtc *crtc;
15294
15295 for_each_intel_crtc(dev, crtc) {
15296 struct intel_unpin_work *work;
e2fcdaa9 15297
5e2d7afc 15298 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15299
15300 work = crtc->unpin_work;
15301
15302 if (work && work->event &&
15303 work->event->base.file_priv == file) {
15304 kfree(work->event);
15305 work->event = NULL;
15306 }
15307
5e2d7afc 15308 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15309 }
15310}
Linux kernel - Deliverables
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