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drm/i915: add PLL sharing support to handle 3 pipes
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
23b2f8bb 27#include <linux/cpufreq.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945
JB		 41
42#include "drm_crtc_helper.h"
43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
7662c8bd 47static void intel_update_watermarks(struct drm_device *dev);
3dec0095 48static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 49static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 50
51typedef struct {
0206e353
AJ		 52 /* given values */
53 int n;
54 int m1, m2;
55 int p1, p2;
56 /* derived values */
57 int dot;
58 int vco;
59 int m;
60 int p;
79e53945
JB		 61} intel_clock_t;
62
63typedef struct {
0206e353 64 int min, max;
79e53945
JB		 65} intel_range_t;
66
67typedef struct {
0206e353
AJ		 68 int dot_limit;
69 int p2_slow, p2_fast;
79e53945
JB		 70} intel_p2_t;
71
72#define INTEL_P2_NUM 2
d4906093
ML		 73typedef struct intel_limit intel_limit_t;
74struct intel_limit {
0206e353
AJ		 75 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 intel_p2_t p2;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
78 int, int, intel_clock_t *);
d4906093 79};
79e53945 80
2377b741
JB		 81/* FDI */
82#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
83
d4906093
ML		 84static bool
85intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
86 int target, int refclk, intel_clock_t *best_clock);
87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *best_clock);
79e53945 90
a4fc5ed6
KP		 91static bool
92intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
93 int target, int refclk, intel_clock_t *best_clock);
5eb08b69 94static bool
f2b115e6
AJ		 95intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
96 int target, int refclk, intel_clock_t *best_clock);
a4fc5ed6 97
021357ac
CW		 98static inline u32 /* units of 100MHz */
99intel_fdi_link_freq(struct drm_device *dev)
100{
8b99e68c
CW		 101 if (IS_GEN5(dev)) {
102 struct drm_i915_private *dev_priv = dev->dev_private;
103 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
104 } else
105 return 27;
021357ac
CW		 106}
107
e4b36699 108static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 109 .dot = { .min = 25000, .max = 350000 },
110 .vco = { .min = 930000, .max = 1400000 },
111 .n = { .min = 3, .max = 16 },
112 .m = { .min = 96, .max = 140 },
113 .m1 = { .min = 18, .max = 26 },
114 .m2 = { .min = 6, .max = 16 },
115 .p = { .min = 4, .max = 128 },
116 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 117 .p2 = { .dot_limit = 165000,
118 .p2_slow = 4, .p2_fast = 2 },
d4906093 119 .find_pll = intel_find_best_PLL,
e4b36699
KP		 120};
121
122static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 123 .dot = { .min = 25000, .max = 350000 },
124 .vco = { .min = 930000, .max = 1400000 },
125 .n = { .min = 3, .max = 16 },
126 .m = { .min = 96, .max = 140 },
127 .m1 = { .min = 18, .max = 26 },
128 .m2 = { .min = 6, .max = 16 },
129 .p = { .min = 4, .max = 128 },
130 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 131 .p2 = { .dot_limit = 165000,
132 .p2_slow = 14, .p2_fast = 7 },
d4906093 133 .find_pll = intel_find_best_PLL,
e4b36699 134};
273e27ca 135
e4b36699 136static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 137 .dot = { .min = 20000, .max = 400000 },
138 .vco = { .min = 1400000, .max = 2800000 },
139 .n = { .min = 1, .max = 6 },
140 .m = { .min = 70, .max = 120 },
141 .m1 = { .min = 10, .max = 22 },
142 .m2 = { .min = 5, .max = 9 },
143 .p = { .min = 5, .max = 80 },
144 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 145 .p2 = { .dot_limit = 200000,
146 .p2_slow = 10, .p2_fast = 5 },
d4906093 147 .find_pll = intel_find_best_PLL,
e4b36699
KP		 148};
149
150static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 151 .dot = { .min = 20000, .max = 400000 },
152 .vco = { .min = 1400000, .max = 2800000 },
153 .n = { .min = 1, .max = 6 },
154 .m = { .min = 70, .max = 120 },
155 .m1 = { .min = 10, .max = 22 },
156 .m2 = { .min = 5, .max = 9 },
157 .p = { .min = 7, .max = 98 },
158 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 159 .p2 = { .dot_limit = 112000,
160 .p2_slow = 14, .p2_fast = 7 },
d4906093 161 .find_pll = intel_find_best_PLL,
e4b36699
KP		 162};
163
273e27ca 164
e4b36699 165static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 166 .dot = { .min = 25000, .max = 270000 },
167 .vco = { .min = 1750000, .max = 3500000},
168 .n = { .min = 1, .max = 4 },
169 .m = { .min = 104, .max = 138 },
170 .m1 = { .min = 17, .max = 23 },
171 .m2 = { .min = 5, .max = 11 },
172 .p = { .min = 10, .max = 30 },
173 .p1 = { .min = 1, .max = 3},
174 .p2 = { .dot_limit = 270000,
175 .p2_slow = 10,
176 .p2_fast = 10
044c7c41 177 },
d4906093 178 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 179};
180
181static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 182 .dot = { .min = 22000, .max = 400000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 16, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 5, .max = 80 },
189 .p1 = { .min = 1, .max = 8},
190 .p2 = { .dot_limit = 165000,
191 .p2_slow = 10, .p2_fast = 5 },
d4906093 192 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 193};
194
195static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 196 .dot = { .min = 20000, .max = 115000 },
197 .vco = { .min = 1750000, .max = 3500000 },
198 .n = { .min = 1, .max = 3 },
199 .m = { .min = 104, .max = 138 },
200 .m1 = { .min = 17, .max = 23 },
201 .m2 = { .min = 5, .max = 11 },
202 .p = { .min = 28, .max = 112 },
203 .p1 = { .min = 2, .max = 8 },
204 .p2 = { .dot_limit = 0,
205 .p2_slow = 14, .p2_fast = 14
044c7c41 206 },
d4906093 207 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 208};
209
210static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 211 .dot = { .min = 80000, .max = 224000 },
212 .vco = { .min = 1750000, .max = 3500000 },
213 .n = { .min = 1, .max = 3 },
214 .m = { .min = 104, .max = 138 },
215 .m1 = { .min = 17, .max = 23 },
216 .m2 = { .min = 5, .max = 11 },
217 .p = { .min = 14, .max = 42 },
218 .p1 = { .min = 2, .max = 6 },
219 .p2 = { .dot_limit = 0,
220 .p2_slow = 7, .p2_fast = 7
044c7c41 221 },
d4906093 222 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 223};
224
225static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 226 .dot = { .min = 161670, .max = 227000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 2 },
229 .m = { .min = 97, .max = 108 },
230 .m1 = { .min = 0x10, .max = 0x12 },
231 .m2 = { .min = 0x05, .max = 0x06 },
232 .p = { .min = 10, .max = 20 },
233 .p1 = { .min = 1, .max = 2},
234 .p2 = { .dot_limit = 0,
273e27ca 235 .p2_slow = 10, .p2_fast = 10 },
0206e353 236 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 237};
238
f2b115e6 239static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 240 .dot = { .min = 20000, .max = 400000},
241 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 242 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 243 .n = { .min = 3, .max = 6 },
244 .m = { .min = 2, .max = 256 },
273e27ca 245 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 246 .m1 = { .min = 0, .max = 0 },
247 .m2 = { .min = 0, .max = 254 },
248 .p = { .min = 5, .max = 80 },
249 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 250 .p2 = { .dot_limit = 200000,
251 .p2_slow = 10, .p2_fast = 5 },
6115707b 252 .find_pll = intel_find_best_PLL,
e4b36699
KP		 253};
254
f2b115e6 255static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 256 .dot = { .min = 20000, .max = 400000 },
257 .vco = { .min = 1700000, .max = 3500000 },
258 .n = { .min = 3, .max = 6 },
259 .m = { .min = 2, .max = 256 },
260 .m1 = { .min = 0, .max = 0 },
261 .m2 = { .min = 0, .max = 254 },
262 .p = { .min = 7, .max = 112 },
263 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 264 .p2 = { .dot_limit = 112000,
265 .p2_slow = 14, .p2_fast = 14 },
6115707b 266 .find_pll = intel_find_best_PLL,
e4b36699
KP		 267};
268
273e27ca
EA		 269/* Ironlake / Sandybridge
270 *
271 * We calculate clock using (register_value + 2) for N/M1/M2, so here
272 * the range value for them is (actual_value - 2).
273 */
b91ad0ec 274static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 1760000, .max = 3510000 },
277 .n = { .min = 1, .max = 5 },
278 .m = { .min = 79, .max = 127 },
279 .m1 = { .min = 12, .max = 22 },
280 .m2 = { .min = 5, .max = 9 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
283 .p2 = { .dot_limit = 225000,
284 .p2_slow = 10, .p2_fast = 5 },
4547668a 285 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 286};
287
b91ad0ec 288static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 289 .dot = { .min = 25000, .max = 350000 },
290 .vco = { .min = 1760000, .max = 3510000 },
291 .n = { .min = 1, .max = 3 },
292 .m = { .min = 79, .max = 118 },
293 .m1 = { .min = 12, .max = 22 },
294 .m2 = { .min = 5, .max = 9 },
295 .p = { .min = 28, .max = 112 },
296 .p1 = { .min = 2, .max = 8 },
297 .p2 = { .dot_limit = 225000,
298 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 299 .find_pll = intel_g4x_find_best_PLL,
300};
301
302static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 303 .dot = { .min = 25000, .max = 350000 },
304 .vco = { .min = 1760000, .max = 3510000 },
305 .n = { .min = 1, .max = 3 },
306 .m = { .min = 79, .max = 127 },
307 .m1 = { .min = 12, .max = 22 },
308 .m2 = { .min = 5, .max = 9 },
309 .p = { .min = 14, .max = 56 },
310 .p1 = { .min = 2, .max = 8 },
311 .p2 = { .dot_limit = 225000,
312 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 313 .find_pll = intel_g4x_find_best_PLL,
314};
315
273e27ca 316/* LVDS 100mhz refclk limits. */
b91ad0ec 317static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 318 .dot = { .min = 25000, .max = 350000 },
319 .vco = { .min = 1760000, .max = 3510000 },
320 .n = { .min = 1, .max = 2 },
321 .m = { .min = 79, .max = 126 },
322 .m1 = { .min = 12, .max = 22 },
323 .m2 = { .min = 5, .max = 9 },
324 .p = { .min = 28, .max = 112 },
0206e353 325 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 326 .p2 = { .dot_limit = 225000,
327 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 328 .find_pll = intel_g4x_find_best_PLL,
329};
330
331static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 332 .dot = { .min = 25000, .max = 350000 },
333 .vco = { .min = 1760000, .max = 3510000 },
334 .n = { .min = 1, .max = 3 },
335 .m = { .min = 79, .max = 126 },
336 .m1 = { .min = 12, .max = 22 },
337 .m2 = { .min = 5, .max = 9 },
338 .p = { .min = 14, .max = 42 },
0206e353 339 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 340 .p2 = { .dot_limit = 225000,
341 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 342 .find_pll = intel_g4x_find_best_PLL,
343};
344
345static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 346 .dot = { .min = 25000, .max = 350000 },
347 .vco = { .min = 1760000, .max = 3510000},
348 .n = { .min = 1, .max = 2 },
349 .m = { .min = 81, .max = 90 },
350 .m1 = { .min = 12, .max = 22 },
351 .m2 = { .min = 5, .max = 9 },
352 .p = { .min = 10, .max = 20 },
353 .p1 = { .min = 1, .max = 2},
354 .p2 = { .dot_limit = 0,
273e27ca 355 .p2_slow = 10, .p2_fast = 10 },
0206e353 356 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 357};
358
1b894b59
CW		 359static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
360 int refclk)
2c07245f 361{
b91ad0ec
ZW		 362 struct drm_device *dev = crtc->dev;
363 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 364 const intel_limit_t *limit;
b91ad0ec
ZW		 365
366 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b91ad0ec
ZW		 367 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
368 LVDS_CLKB_POWER_UP) {
369 /* LVDS dual channel */
1b894b59 370 if (refclk == 100000)
b91ad0ec
ZW		 371 limit = &intel_limits_ironlake_dual_lvds_100m;
372 else
373 limit = &intel_limits_ironlake_dual_lvds;
374 } else {
1b894b59 375 if (refclk == 100000)
b91ad0ec
ZW		 376 limit = &intel_limits_ironlake_single_lvds_100m;
377 else
378 limit = &intel_limits_ironlake_single_lvds;
379 }
380 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 381 HAS_eDP)
382 limit = &intel_limits_ironlake_display_port;
2c07245f 383 else
b91ad0ec 384 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 385
386 return limit;
387}
388
044c7c41
ML		 389static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
390{
391 struct drm_device *dev = crtc->dev;
392 struct drm_i915_private *dev_priv = dev->dev_private;
393 const intel_limit_t *limit;
394
395 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
396 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
397 LVDS_CLKB_POWER_UP)
398 /* LVDS with dual channel */
e4b36699 399 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 400 else
401 /* LVDS with dual channel */
e4b36699 402 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 403 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
404 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 405 limit = &intel_limits_g4x_hdmi;
044c7c41 406 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 407 limit = &intel_limits_g4x_sdvo;
0206e353 408 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 409 limit = &intel_limits_g4x_display_port;
044c7c41 410 } else /* The option is for other outputs */
e4b36699 411 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 412
413 return limit;
414}
415
1b894b59 416static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 417{
418 struct drm_device *dev = crtc->dev;
419 const intel_limit_t *limit;
420
bad720ff 421 if (HAS_PCH_SPLIT(dev))
1b894b59 422 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 423 else if (IS_G4X(dev)) {
044c7c41 424 limit = intel_g4x_limit(crtc);
f2b115e6 425 } else if (IS_PINEVIEW(dev)) {
2177832f 426 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 427 limit = &intel_limits_pineview_lvds;
2177832f 428 else
f2b115e6 429 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 430 } else if (!IS_GEN2(dev)) {
431 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
432 limit = &intel_limits_i9xx_lvds;
433 else
434 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 435 } else {
436 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 437 limit = &intel_limits_i8xx_lvds;
79e53945 438 else
e4b36699 439 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 440 }
441 return limit;
442}
443
f2b115e6
AJ		 444/* m1 is reserved as 0 in Pineview, n is a ring counter */
445static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 446{
2177832f
SL		 447 clock->m = clock->m2 + 2;
448 clock->p = clock->p1 * clock->p2;
449 clock->vco = refclk * clock->m / clock->n;
450 clock->dot = clock->vco / clock->p;
451}
452
453static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
454{
f2b115e6
AJ		 455 if (IS_PINEVIEW(dev)) {
456 pineview_clock(refclk, clock);
2177832f
SL		 457 return;
458 }
79e53945
JB		 459 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
460 clock->p = clock->p1 * clock->p2;
461 clock->vco = refclk * clock->m / (clock->n + 2);
462 clock->dot = clock->vco / clock->p;
463}
464
79e53945
JB		 465/**
466 * Returns whether any output on the specified pipe is of the specified type
467 */
4ef69c7a 468bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 469{
4ef69c7a
CW		 470 struct drm_device *dev = crtc->dev;
471 struct drm_mode_config *mode_config = &dev->mode_config;
472 struct intel_encoder *encoder;
473
474 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
475 if (encoder->base.crtc == crtc && encoder->type == type)
476 return true;
477
478 return false;
79e53945
JB		 479}
480
7c04d1d9 481#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 482/**
483 * Returns whether the given set of divisors are valid for a given refclk with
484 * the given connectors.
485 */
486
1b894b59
CW		 487static bool intel_PLL_is_valid(struct drm_device *dev,
488 const intel_limit_t *limit,
489 const intel_clock_t *clock)
79e53945 490{
79e53945 491 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 492 INTELPllInvalid("p1 out of range\n");
79e53945 493 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 494 INTELPllInvalid("p out of range\n");
79e53945 495 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 496 INTELPllInvalid("m2 out of range\n");
79e53945 497 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 498 INTELPllInvalid("m1 out of range\n");
f2b115e6 499 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 500 INTELPllInvalid("m1 <= m2\n");
79e53945 501 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 502 INTELPllInvalid("m out of range\n");
79e53945 503 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 504 INTELPllInvalid("n out of range\n");
79e53945 505 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 506 INTELPllInvalid("vco out of range\n");
79e53945
JB		 507 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
508 * connector, etc., rather than just a single range.
509 */
510 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 511 INTELPllInvalid("dot out of range\n");
79e53945
JB		 512
513 return true;
514}
515
d4906093
ML		 516static bool
517intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
518 int target, int refclk, intel_clock_t *best_clock)
519
79e53945
JB		 520{
521 struct drm_device *dev = crtc->dev;
522 struct drm_i915_private *dev_priv = dev->dev_private;
523 intel_clock_t clock;
79e53945
JB		 524 int err = target;
525
bc5e5718 526 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 527 (I915_READ(LVDS)) != 0) {
79e53945
JB		 528 /*
529 * For LVDS, if the panel is on, just rely on its current
530 * settings for dual-channel. We haven't figured out how to
531 * reliably set up different single/dual channel state, if we
532 * even can.
533 */
534 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
535 LVDS_CLKB_POWER_UP)
536 clock.p2 = limit->p2.p2_fast;
537 else
538 clock.p2 = limit->p2.p2_slow;
539 } else {
540 if (target < limit->p2.dot_limit)
541 clock.p2 = limit->p2.p2_slow;
542 else
543 clock.p2 = limit->p2.p2_fast;
544 }
545
0206e353 546 memset(best_clock, 0, sizeof(*best_clock));
79e53945 547
42158660
ZY		 548 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
549 clock.m1++) {
550 for (clock.m2 = limit->m2.min;
551 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 552 /* m1 is always 0 in Pineview */
553 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 554 break;
555 for (clock.n = limit->n.min;
556 clock.n <= limit->n.max; clock.n++) {
557 for (clock.p1 = limit->p1.min;
558 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 559 int this_err;
560
2177832f 561 intel_clock(dev, refclk, &clock);
1b894b59
CW		 562 if (!intel_PLL_is_valid(dev, limit,
563 &clock))
79e53945
JB		 564 continue;
565
566 this_err = abs(clock.dot - target);
567 if (this_err < err) {
568 *best_clock = clock;
569 err = this_err;
570 }
571 }
572 }
573 }
574 }
575
576 return (err != target);
577}
578
d4906093
ML		 579static bool
580intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
581 int target, int refclk, intel_clock_t *best_clock)
582{
583 struct drm_device *dev = crtc->dev;
584 struct drm_i915_private *dev_priv = dev->dev_private;
585 intel_clock_t clock;
586 int max_n;
587 bool found;
6ba770dc
AJ		 588 /* approximately equals target * 0.00585 */
589 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 590 found = false;
591
592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 593 int lvds_reg;
594
c619eed4 595 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 596 lvds_reg = PCH_LVDS;
597 else
598 lvds_reg = LVDS;
599 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 600 LVDS_CLKB_POWER_UP)
601 clock.p2 = limit->p2.p2_fast;
602 else
603 clock.p2 = limit->p2.p2_slow;
604 } else {
605 if (target < limit->p2.dot_limit)
606 clock.p2 = limit->p2.p2_slow;
607 else
608 clock.p2 = limit->p2.p2_fast;
609 }
610
611 memset(best_clock, 0, sizeof(*best_clock));
612 max_n = limit->n.max;
f77f13e2 613 /* based on hardware requirement, prefer smaller n to precision */
d4906093 614 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 615 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 616 for (clock.m1 = limit->m1.max;
617 clock.m1 >= limit->m1.min; clock.m1--) {
618 for (clock.m2 = limit->m2.max;
619 clock.m2 >= limit->m2.min; clock.m2--) {
620 for (clock.p1 = limit->p1.max;
621 clock.p1 >= limit->p1.min; clock.p1--) {
622 int this_err;
623
2177832f 624 intel_clock(dev, refclk, &clock);
1b894b59
CW		 625 if (!intel_PLL_is_valid(dev, limit,
626 &clock))
d4906093 627 continue;
1b894b59
CW		 628
629 this_err = abs(clock.dot - target);
d4906093
ML		 630 if (this_err < err_most) {
631 *best_clock = clock;
632 err_most = this_err;
633 max_n = clock.n;
634 found = true;
635 }
636 }
637 }
638 }
639 }
2c07245f
ZW		 640 return found;
641}
642
5eb08b69 643static bool
f2b115e6
AJ		 644intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
645 int target, int refclk, intel_clock_t *best_clock)
5eb08b69
ZW		 646{
647 struct drm_device *dev = crtc->dev;
648 intel_clock_t clock;
4547668a 649
5eb08b69
ZW		 650 if (target < 200000) {
651 clock.n = 1;
652 clock.p1 = 2;
653 clock.p2 = 10;
654 clock.m1 = 12;
655 clock.m2 = 9;
656 } else {
657 clock.n = 2;
658 clock.p1 = 1;
659 clock.p2 = 10;
660 clock.m1 = 14;
661 clock.m2 = 8;
662 }
663 intel_clock(dev, refclk, &clock);
664 memcpy(best_clock, &clock, sizeof(intel_clock_t));
665 return true;
666}
667
a4fc5ed6
KP		 668/* DisplayPort has only two frequencies, 162MHz and 270MHz */
669static bool
670intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
671 int target, int refclk, intel_clock_t *best_clock)
672{
5eddb70b
CW		 673 intel_clock_t clock;
674 if (target < 200000) {
675 clock.p1 = 2;
676 clock.p2 = 10;
677 clock.n = 2;
678 clock.m1 = 23;
679 clock.m2 = 8;
680 } else {
681 clock.p1 = 1;
682 clock.p2 = 10;
683 clock.n = 1;
684 clock.m1 = 14;
685 clock.m2 = 2;
686 }
687 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
688 clock.p = (clock.p1 * clock.p2);
689 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
690 clock.vco = 0;
691 memcpy(best_clock, &clock, sizeof(intel_clock_t));
692 return true;
a4fc5ed6
KP		 693}
694
9d0498a2
JB		 695/**
696 * intel_wait_for_vblank - wait for vblank on a given pipe
697 * @dev: drm device
698 * @pipe: pipe to wait for
699 *
700 * Wait for vblank to occur on a given pipe. Needed for various bits of
701 * mode setting code.
702 */
703void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 704{
9d0498a2 705 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 706 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 707
300387c0
CW		 708 /* Clear existing vblank status. Note this will clear any other
709 * sticky status fields as well.
710 *
711 * This races with i915_driver_irq_handler() with the result
712 * that either function could miss a vblank event. Here it is not
713 * fatal, as we will either wait upon the next vblank interrupt or
714 * timeout. Generally speaking intel_wait_for_vblank() is only
715 * called during modeset at which time the GPU should be idle and
716 * should *not* be performing page flips and thus not waiting on
717 * vblanks...
718 * Currently, the result of us stealing a vblank from the irq
719 * handler is that a single frame will be skipped during swapbuffers.
720 */
721 I915_WRITE(pipestat_reg,
722 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
723
9d0498a2 724 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 725 if (wait_for(I915_READ(pipestat_reg) &
726 PIPE_VBLANK_INTERRUPT_STATUS,
727 50))
9d0498a2
JB		 728 DRM_DEBUG_KMS("vblank wait timed out\n");
729}
730
ab7ad7f6
KP		 731/*
732 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 733 * @dev: drm device
734 * @pipe: pipe to wait for
735 *
736 * After disabling a pipe, we can't wait for vblank in the usual way,
737 * spinning on the vblank interrupt status bit, since we won't actually
738 * see an interrupt when the pipe is disabled.
739 *
ab7ad7f6
KP		 740 * On Gen4 and above:
741 * wait for the pipe register state bit to turn off
742 *
743 * Otherwise:
744 * wait for the display line value to settle (it usually
745 * ends up stopping at the start of the next frame).
58e10eb9 746 *
9d0498a2 747 */
58e10eb9 748void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 749{
750 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 751
752 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 753 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 754
755 /* Wait for the Pipe State to go off */
58e10eb9
CW		 756 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
757 100))
ab7ad7f6
KP		 758 DRM_DEBUG_KMS("pipe_off wait timed out\n");
759 } else {
760 u32 last_line;
58e10eb9 761 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 762 unsigned long timeout = jiffies + msecs_to_jiffies(100);
763
764 /* Wait for the display line to settle */
765 do {
58e10eb9 766 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 767 mdelay(5);
58e10eb9 768 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 769 time_after(timeout, jiffies));
770 if (time_after(jiffies, timeout))
771 DRM_DEBUG_KMS("pipe_off wait timed out\n");
772 }
79e53945
JB		 773}
774
b24e7179
JB		 775static const char *state_string(bool enabled)
776{
777 return enabled ? "on" : "off";
778}
779
780/* Only for pre-ILK configs */
781static void assert_pll(struct drm_i915_private *dev_priv,
782 enum pipe pipe, bool state)
783{
784 int reg;
785 u32 val;
786 bool cur_state;
787
788 reg = DPLL(pipe);
789 val = I915_READ(reg);
790 cur_state = !!(val & DPLL_VCO_ENABLE);
791 WARN(cur_state != state,
792 "PLL state assertion failure (expected %s, current %s)\n",
793 state_string(state), state_string(cur_state));
794}
795#define assert_pll_enabled(d, p) assert_pll(d, p, true)
796#define assert_pll_disabled(d, p) assert_pll(d, p, false)
797
040484af
JB		 798/* For ILK+ */
799static void assert_pch_pll(struct drm_i915_private *dev_priv,
800 enum pipe pipe, bool state)
801{
802 int reg;
803 u32 val;
804 bool cur_state;
805
d3ccbe86
JB		 806 if (HAS_PCH_CPT(dev_priv->dev)) {
807 u32 pch_dpll;
808
809 pch_dpll = I915_READ(PCH_DPLL_SEL);
810
811 /* Make sure the selected PLL is enabled to the transcoder */
812 WARN(!((pch_dpll >> (4 * pipe)) & 8),
813 "transcoder %d PLL not enabled\n", pipe);
814
815 /* Convert the transcoder pipe number to a pll pipe number */
816 pipe = (pch_dpll >> (4 * pipe)) & 1;
817 }
818
040484af
JB		 819 reg = PCH_DPLL(pipe);
820 val = I915_READ(reg);
821 cur_state = !!(val & DPLL_VCO_ENABLE);
822 WARN(cur_state != state,
823 "PCH PLL state assertion failure (expected %s, current %s)\n",
824 state_string(state), state_string(cur_state));
825}
826#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
827#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
828
829static void assert_fdi_tx(struct drm_i915_private *dev_priv,
830 enum pipe pipe, bool state)
831{
832 int reg;
833 u32 val;
834 bool cur_state;
835
836 reg = FDI_TX_CTL(pipe);
837 val = I915_READ(reg);
838 cur_state = !!(val & FDI_TX_ENABLE);
839 WARN(cur_state != state,
840 "FDI TX state assertion failure (expected %s, current %s)\n",
841 state_string(state), state_string(cur_state));
842}
843#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
844#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
845
846static void assert_fdi_rx(struct drm_i915_private *dev_priv,
847 enum pipe pipe, bool state)
848{
849 int reg;
850 u32 val;
851 bool cur_state;
852
853 reg = FDI_RX_CTL(pipe);
854 val = I915_READ(reg);
855 cur_state = !!(val & FDI_RX_ENABLE);
856 WARN(cur_state != state,
857 "FDI RX state assertion failure (expected %s, current %s)\n",
858 state_string(state), state_string(cur_state));
859}
860#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
861#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
862
863static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
864 enum pipe pipe)
865{
866 int reg;
867 u32 val;
868
869 /* ILK FDI PLL is always enabled */
870 if (dev_priv->info->gen == 5)
871 return;
872
873 reg = FDI_TX_CTL(pipe);
874 val = I915_READ(reg);
875 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
876}
877
878static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
879 enum pipe pipe)
880{
881 int reg;
882 u32 val;
883
884 reg = FDI_RX_CTL(pipe);
885 val = I915_READ(reg);
886 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
887}
888
ea0760cf
JB		 889static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
890 enum pipe pipe)
891{
892 int pp_reg, lvds_reg;
893 u32 val;
894 enum pipe panel_pipe = PIPE_A;
0de3b485 895 bool locked = true;
ea0760cf
JB		 896
897 if (HAS_PCH_SPLIT(dev_priv->dev)) {
898 pp_reg = PCH_PP_CONTROL;
899 lvds_reg = PCH_LVDS;
900 } else {
901 pp_reg = PP_CONTROL;
902 lvds_reg = LVDS;
903 }
904
905 val = I915_READ(pp_reg);
906 if (!(val & PANEL_POWER_ON) ||
907 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
908 locked = false;
909
910 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
911 panel_pipe = PIPE_B;
912
913 WARN(panel_pipe == pipe && locked,
914 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 915 pipe_name(pipe));
ea0760cf
JB		 916}
917
63d7bbe9
JB		 918static void assert_pipe(struct drm_i915_private *dev_priv,
919 enum pipe pipe, bool state)
b24e7179
JB		 920{
921 int reg;
922 u32 val;
63d7bbe9 923 bool cur_state;
b24e7179
JB		 924
925 reg = PIPECONF(pipe);
926 val = I915_READ(reg);
63d7bbe9
JB		 927 cur_state = !!(val & PIPECONF_ENABLE);
928 WARN(cur_state != state,
929 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 930 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179 931}
63d7bbe9
JB		 932#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
933#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
b24e7179
JB		 934
935static void assert_plane_enabled(struct drm_i915_private *dev_priv,
936 enum plane plane)
937{
938 int reg;
939 u32 val;
940
941 reg = DSPCNTR(plane);
942 val = I915_READ(reg);
943 WARN(!(val & DISPLAY_PLANE_ENABLE),
944 "plane %c assertion failure, should be active but is disabled\n",
9db4a9c7 945 plane_name(plane));
b24e7179
JB		 946}
947
948static void assert_planes_disabled(struct drm_i915_private *dev_priv,
949 enum pipe pipe)
950{
951 int reg, i;
952 u32 val;
953 int cur_pipe;
954
19ec1358
JB		 955 /* Planes are fixed to pipes on ILK+ */
956 if (HAS_PCH_SPLIT(dev_priv->dev))
957 return;
958
b24e7179
JB		 959 /* Need to check both planes against the pipe */
960 for (i = 0; i < 2; i++) {
961 reg = DSPCNTR(i);
962 val = I915_READ(reg);
963 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
964 DISPPLANE_SEL_PIPE_SHIFT;
965 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 966 "plane %c assertion failure, should be off on pipe %c but is still active\n",
967 plane_name(i), pipe_name(pipe));
b24e7179
JB		 968 }
969}
970
92f2584a
JB		 971static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
972{
973 u32 val;
974 bool enabled;
975
976 val = I915_READ(PCH_DREF_CONTROL);
977 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
978 DREF_SUPERSPREAD_SOURCE_MASK));
979 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
980}
981
982static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
983 enum pipe pipe)
984{
985 int reg;
986 u32 val;
987 bool enabled;
988
989 reg = TRANSCONF(pipe);
990 val = I915_READ(reg);
991 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 992 WARN(enabled,
993 "transcoder assertion failed, should be off on pipe %c but is still active\n",
994 pipe_name(pipe));
92f2584a
JB		 995}
996
4e634389
KP		 997static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
998 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 999{
1000 if ((val & DP_PORT_EN) == 0)
1001 return false;
1002
1003 if (HAS_PCH_CPT(dev_priv->dev)) {
1004 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1005 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1006 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1007 return false;
1008 } else {
1009 if ((val & DP_PIPE_MASK) != (pipe << 30))
1010 return false;
1011 }
1012 return true;
1013}
1014
1519b995
KP		 1015static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1016 enum pipe pipe, u32 val)
1017{
1018 if ((val & PORT_ENABLE) == 0)
1019 return false;
1020
1021 if (HAS_PCH_CPT(dev_priv->dev)) {
1022 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1023 return false;
1024 } else {
1025 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1026 return false;
1027 }
1028 return true;
1029}
1030
1031static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1032 enum pipe pipe, u32 val)
1033{
1034 if ((val & LVDS_PORT_EN) == 0)
1035 return false;
1036
1037 if (HAS_PCH_CPT(dev_priv->dev)) {
1038 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1039 return false;
1040 } else {
1041 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1042 return false;
1043 }
1044 return true;
1045}
1046
1047static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1048 enum pipe pipe, u32 val)
1049{
1050 if ((val & ADPA_DAC_ENABLE) == 0)
1051 return false;
1052 if (HAS_PCH_CPT(dev_priv->dev)) {
1053 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1054 return false;
1055 } else {
1056 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1057 return false;
1058 }
1059 return true;
1060}
1061
291906f1 1062static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1063 enum pipe pipe, int reg, u32 port_sel)
291906f1 1064{
47a05eca 1065 u32 val = I915_READ(reg);
4e634389 1066 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1067 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1068 reg, pipe_name(pipe));
291906f1
JB		 1069}
1070
1071static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1072 enum pipe pipe, int reg)
1073{
47a05eca 1074 u32 val = I915_READ(reg);
1519b995 1075 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
291906f1 1076 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1077 reg, pipe_name(pipe));
291906f1
JB		 1078}
1079
1080static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1081 enum pipe pipe)
1082{
1083 int reg;
1084 u32 val;
291906f1 1085
f0575e92
KP		 1086 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1087 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1088 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1089
1090 reg = PCH_ADPA;
1091 val = I915_READ(reg);
1519b995 1092 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1093 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1094 pipe_name(pipe));
291906f1
JB		 1095
1096 reg = PCH_LVDS;
1097 val = I915_READ(reg);
1519b995 1098 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1099 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1100 pipe_name(pipe));
291906f1
JB		 1101
1102 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1103 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1104 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1105}
1106
63d7bbe9
JB		 1107/**
1108 * intel_enable_pll - enable a PLL
1109 * @dev_priv: i915 private structure
1110 * @pipe: pipe PLL to enable
1111 *
1112 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1113 * make sure the PLL reg is writable first though, since the panel write
1114 * protect mechanism may be enabled.
1115 *
1116 * Note! This is for pre-ILK only.
1117 */
1118static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1119{
1120 int reg;
1121 u32 val;
1122
1123 /* No really, not for ILK+ */
1124 BUG_ON(dev_priv->info->gen >= 5);
1125
1126 /* PLL is protected by panel, make sure we can write it */
1127 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1128 assert_panel_unlocked(dev_priv, pipe);
1129
1130 reg = DPLL(pipe);
1131 val = I915_READ(reg);
1132 val |= DPLL_VCO_ENABLE;
1133
1134 /* We do this three times for luck */
1135 I915_WRITE(reg, val);
1136 POSTING_READ(reg);
1137 udelay(150); /* wait for warmup */
1138 I915_WRITE(reg, val);
1139 POSTING_READ(reg);
1140 udelay(150); /* wait for warmup */
1141 I915_WRITE(reg, val);
1142 POSTING_READ(reg);
1143 udelay(150); /* wait for warmup */
1144}
1145
1146/**
1147 * intel_disable_pll - disable a PLL
1148 * @dev_priv: i915 private structure
1149 * @pipe: pipe PLL to disable
1150 *
1151 * Disable the PLL for @pipe, making sure the pipe is off first.
1152 *
1153 * Note! This is for pre-ILK only.
1154 */
1155static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1156{
1157 int reg;
1158 u32 val;
1159
1160 /* Don't disable pipe A or pipe A PLLs if needed */
1161 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1162 return;
1163
1164 /* Make sure the pipe isn't still relying on us */
1165 assert_pipe_disabled(dev_priv, pipe);
1166
1167 reg = DPLL(pipe);
1168 val = I915_READ(reg);
1169 val &= ~DPLL_VCO_ENABLE;
1170 I915_WRITE(reg, val);
1171 POSTING_READ(reg);
1172}
1173
92f2584a
JB		 1174/**
1175 * intel_enable_pch_pll - enable PCH PLL
1176 * @dev_priv: i915 private structure
1177 * @pipe: pipe PLL to enable
1178 *
1179 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1180 * drives the transcoder clock.
1181 */
1182static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1183 enum pipe pipe)
1184{
1185 int reg;
1186 u32 val;
1187
4c609cb8
JB		 1188 if (pipe > 1)
1189 return;
1190
92f2584a
JB		 1191 /* PCH only available on ILK+ */
1192 BUG_ON(dev_priv->info->gen < 5);
1193
1194 /* PCH refclock must be enabled first */
1195 assert_pch_refclk_enabled(dev_priv);
1196
1197 reg = PCH_DPLL(pipe);
1198 val = I915_READ(reg);
1199 val |= DPLL_VCO_ENABLE;
1200 I915_WRITE(reg, val);
1201 POSTING_READ(reg);
1202 udelay(200);
1203}
1204
1205static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1206 enum pipe pipe)
1207{
1208 int reg;
1209 u32 val;
1210
4c609cb8
JB		 1211 if (pipe > 1)
1212 return;
1213
92f2584a
JB		 1214 /* PCH only available on ILK+ */
1215 BUG_ON(dev_priv->info->gen < 5);
1216
1217 /* Make sure transcoder isn't still depending on us */
1218 assert_transcoder_disabled(dev_priv, pipe);
1219
1220 reg = PCH_DPLL(pipe);
1221 val = I915_READ(reg);
1222 val &= ~DPLL_VCO_ENABLE;
1223 I915_WRITE(reg, val);
1224 POSTING_READ(reg);
1225 udelay(200);
1226}
1227
040484af
JB		 1228static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1229 enum pipe pipe)
1230{
1231 int reg;
1232 u32 val;
1233
1234 /* PCH only available on ILK+ */
1235 BUG_ON(dev_priv->info->gen < 5);
1236
1237 /* Make sure PCH DPLL is enabled */
1238 assert_pch_pll_enabled(dev_priv, pipe);
1239
1240 /* FDI must be feeding us bits for PCH ports */
1241 assert_fdi_tx_enabled(dev_priv, pipe);
1242 assert_fdi_rx_enabled(dev_priv, pipe);
1243
1244 reg = TRANSCONF(pipe);
1245 val = I915_READ(reg);
e9bcff5c
JB		 1246
1247 if (HAS_PCH_IBX(dev_priv->dev)) {
1248 /*
1249 * make the BPC in transcoder be consistent with
1250 * that in pipeconf reg.
1251 */
1252 val &= ~PIPE_BPC_MASK;
1253 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1254 }
040484af
JB		 1255 I915_WRITE(reg, val | TRANS_ENABLE);
1256 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1257 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1258}
1259
1260static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1261 enum pipe pipe)
1262{
1263 int reg;
1264 u32 val;
1265
1266 /* FDI relies on the transcoder */
1267 assert_fdi_tx_disabled(dev_priv, pipe);
1268 assert_fdi_rx_disabled(dev_priv, pipe);
1269
291906f1
JB		 1270 /* Ports must be off as well */
1271 assert_pch_ports_disabled(dev_priv, pipe);
1272
040484af
JB		 1273 reg = TRANSCONF(pipe);
1274 val = I915_READ(reg);
1275 val &= ~TRANS_ENABLE;
1276 I915_WRITE(reg, val);
1277 /* wait for PCH transcoder off, transcoder state */
1278 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1279 DRM_ERROR("failed to disable transcoder\n");
1280}
1281
b24e7179 1282/**
309cfea8 1283 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1284 * @dev_priv: i915 private structure
1285 * @pipe: pipe to enable
040484af 1286 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1287 *
1288 * Enable @pipe, making sure that various hardware specific requirements
1289 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1290 *
1291 * @pipe should be %PIPE_A or %PIPE_B.
1292 *
1293 * Will wait until the pipe is actually running (i.e. first vblank) before
1294 * returning.
1295 */
040484af
JB		 1296static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1297 bool pch_port)
b24e7179
JB		 1298{
1299 int reg;
1300 u32 val;
1301
1302 /*
1303 * A pipe without a PLL won't actually be able to drive bits from
1304 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1305 * need the check.
1306 */
1307 if (!HAS_PCH_SPLIT(dev_priv->dev))
1308 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1309 else {
1310 if (pch_port) {
1311 /* if driving the PCH, we need FDI enabled */
1312 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1313 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1314 }
1315 /* FIXME: assert CPU port conditions for SNB+ */
1316 }
b24e7179
JB		 1317
1318 reg = PIPECONF(pipe);
1319 val = I915_READ(reg);
00d70b15
CW		 1320 if (val & PIPECONF_ENABLE)
1321 return;
1322
1323 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1324 intel_wait_for_vblank(dev_priv->dev, pipe);
1325}
1326
1327/**
309cfea8 1328 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1329 * @dev_priv: i915 private structure
1330 * @pipe: pipe to disable
1331 *
1332 * Disable @pipe, making sure that various hardware specific requirements
1333 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1334 *
1335 * @pipe should be %PIPE_A or %PIPE_B.
1336 *
1337 * Will wait until the pipe has shut down before returning.
1338 */
1339static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1340 enum pipe pipe)
1341{
1342 int reg;
1343 u32 val;
1344
1345 /*
1346 * Make sure planes won't keep trying to pump pixels to us,
1347 * or we might hang the display.
1348 */
1349 assert_planes_disabled(dev_priv, pipe);
1350
1351 /* Don't disable pipe A or pipe A PLLs if needed */
1352 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1353 return;
1354
1355 reg = PIPECONF(pipe);
1356 val = I915_READ(reg);
00d70b15
CW		 1357 if ((val & PIPECONF_ENABLE) == 0)
1358 return;
1359
1360 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1361 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1362}
1363
d74362c9
KP		 1364/*
1365 * Plane regs are double buffered, going from enabled->disabled needs a
1366 * trigger in order to latch. The display address reg provides this.
1367 */
1368static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1369 enum plane plane)
1370{
1371 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1372 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1373}
1374
b24e7179
JB		 1375/**
1376 * intel_enable_plane - enable a display plane on a given pipe
1377 * @dev_priv: i915 private structure
1378 * @plane: plane to enable
1379 * @pipe: pipe being fed
1380 *
1381 * Enable @plane on @pipe, making sure that @pipe is running first.
1382 */
1383static void intel_enable_plane(struct drm_i915_private *dev_priv,
1384 enum plane plane, enum pipe pipe)
1385{
1386 int reg;
1387 u32 val;
1388
1389 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1390 assert_pipe_enabled(dev_priv, pipe);
1391
1392 reg = DSPCNTR(plane);
1393 val = I915_READ(reg);
00d70b15
CW		 1394 if (val & DISPLAY_PLANE_ENABLE)
1395 return;
1396
1397 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1398 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1399 intel_wait_for_vblank(dev_priv->dev, pipe);
1400}
1401
b24e7179
JB		 1402/**
1403 * intel_disable_plane - disable a display plane
1404 * @dev_priv: i915 private structure
1405 * @plane: plane to disable
1406 * @pipe: pipe consuming the data
1407 *
1408 * Disable @plane; should be an independent operation.
1409 */
1410static void intel_disable_plane(struct drm_i915_private *dev_priv,
1411 enum plane plane, enum pipe pipe)
1412{
1413 int reg;
1414 u32 val;
1415
1416 reg = DSPCNTR(plane);
1417 val = I915_READ(reg);
00d70b15
CW		 1418 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1419 return;
1420
1421 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1422 intel_flush_display_plane(dev_priv, plane);
1423 intel_wait_for_vblank(dev_priv->dev, pipe);
1424}
1425
47a05eca 1426static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1427 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1428{
1429 u32 val = I915_READ(reg);
4e634389 1430 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1431 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1432 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1433 }
47a05eca
JB		 1434}
1435
1436static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1437 enum pipe pipe, int reg)
1438{
1439 u32 val = I915_READ(reg);
1519b995 1440 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1441 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1442 reg, pipe);
47a05eca 1443 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1444 }
47a05eca
JB		 1445}
1446
1447/* Disable any ports connected to this transcoder */
1448static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1449 enum pipe pipe)
1450{
1451 u32 reg, val;
1452
1453 val = I915_READ(PCH_PP_CONTROL);
1454 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1455
f0575e92
KP		 1456 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1457 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1458 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1459
1460 reg = PCH_ADPA;
1461 val = I915_READ(reg);
1519b995 1462 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1463 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1464
1465 reg = PCH_LVDS;
1466 val = I915_READ(reg);
1519b995
KP		 1467 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1468 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1469 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1470 POSTING_READ(reg);
1471 udelay(100);
1472 }
1473
1474 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1475 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1476 disable_pch_hdmi(dev_priv, pipe, HDMID);
1477}
1478
43a9539f
CW		 1479static void i8xx_disable_fbc(struct drm_device *dev)
1480{
1481 struct drm_i915_private *dev_priv = dev->dev_private;
1482 u32 fbc_ctl;
1483
1484 /* Disable compression */
1485 fbc_ctl = I915_READ(FBC_CONTROL);
1486 if ((fbc_ctl & FBC_CTL_EN) == 0)
1487 return;
1488
1489 fbc_ctl &= ~FBC_CTL_EN;
1490 I915_WRITE(FBC_CONTROL, fbc_ctl);
1491
1492 /* Wait for compressing bit to clear */
1493 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1494 DRM_DEBUG_KMS("FBC idle timed out\n");
1495 return;
1496 }
1497
1498 DRM_DEBUG_KMS("disabled FBC\n");
1499}
1500
80824003
JB		 1501static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1502{
1503 struct drm_device *dev = crtc->dev;
1504 struct drm_i915_private *dev_priv = dev->dev_private;
1505 struct drm_framebuffer *fb = crtc->fb;
1506 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1507 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003 1508 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
016b9b61 1509 int cfb_pitch;
80824003
JB		 1510 int plane, i;
1511 u32 fbc_ctl, fbc_ctl2;
1512
016b9b61
CW		 1513 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1514 if (fb->pitch < cfb_pitch)
1515 cfb_pitch = fb->pitch;
80824003
JB		 1516
1517 /* FBC_CTL wants 64B units */
016b9b61
CW		 1518 cfb_pitch = (cfb_pitch / 64) - 1;
1519 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
80824003
JB		 1520
1521 /* Clear old tags */
1522 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1523 I915_WRITE(FBC_TAG + (i * 4), 0);
1524
1525 /* Set it up... */
de568510
CW		 1526 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1527 fbc_ctl2 |= plane;
80824003
JB		 1528 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1529 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1530
1531 /* enable it... */
1532 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1533 if (IS_I945GM(dev))
49677901 1534 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
016b9b61 1535 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
80824003 1536 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
016b9b61 1537 fbc_ctl |= obj->fence_reg;
80824003
JB		 1538 I915_WRITE(FBC_CONTROL, fbc_ctl);
1539
016b9b61
CW		 1540 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1541 cfb_pitch, crtc->y, intel_crtc->plane);
80824003
JB		 1542}
1543
ee5382ae 1544static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1545{
80824003
JB		 1546 struct drm_i915_private *dev_priv = dev->dev_private;
1547
1548 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1549}
1550
74dff282
JB		 1551static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1552{
1553 struct drm_device *dev = crtc->dev;
1554 struct drm_i915_private *dev_priv = dev->dev_private;
1555 struct drm_framebuffer *fb = crtc->fb;
1556 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1557 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1559 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB		 1560 unsigned long stall_watermark = 200;
1561 u32 dpfc_ctl;
1562
74dff282 1563 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
016b9b61 1564 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
de568510 1565 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
74dff282 1566
74dff282
JB		 1567 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1568 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1569 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1570 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1571
1572 /* enable it... */
1573 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1574
28c97730 1575 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB		 1576}
1577
43a9539f 1578static void g4x_disable_fbc(struct drm_device *dev)
74dff282
JB		 1579{
1580 struct drm_i915_private *dev_priv = dev->dev_private;
1581 u32 dpfc_ctl;
1582
1583 /* Disable compression */
1584 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW		 1585 if (dpfc_ctl & DPFC_CTL_EN) {
1586 dpfc_ctl &= ~DPFC_CTL_EN;
1587 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1588
bed4a673
CW		 1589 DRM_DEBUG_KMS("disabled FBC\n");
1590 }
74dff282
JB		 1591}
1592
ee5382ae 1593static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1594{
74dff282
JB		 1595 struct drm_i915_private *dev_priv = dev->dev_private;
1596
1597 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1598}
1599
4efe0708
JB		 1600static void sandybridge_blit_fbc_update(struct drm_device *dev)
1601{
1602 struct drm_i915_private *dev_priv = dev->dev_private;
1603 u32 blt_ecoskpd;
1604
1605 /* Make sure blitter notifies FBC of writes */
fcca7926 1606 gen6_gt_force_wake_get(dev_priv);
4efe0708
JB		 1607 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1608 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1609 GEN6_BLITTER_LOCK_SHIFT;
1610 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1611 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1612 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1613 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1614 GEN6_BLITTER_LOCK_SHIFT);
1615 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1616 POSTING_READ(GEN6_BLITTER_ECOSKPD);
fcca7926 1617 gen6_gt_force_wake_put(dev_priv);
4efe0708
JB		 1618}
1619
b52eb4dc
ZY		 1620static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1621{
1622 struct drm_device *dev = crtc->dev;
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1624 struct drm_framebuffer *fb = crtc->fb;
1625 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1626 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1627 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1628 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY		 1629 unsigned long stall_watermark = 200;
1630 u32 dpfc_ctl;
1631
bed4a673 1632 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
b52eb4dc
ZY		 1633 dpfc_ctl &= DPFC_RESERVED;
1634 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
9ce9d069
CW		 1635 /* Set persistent mode for front-buffer rendering, ala X. */
1636 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
016b9b61 1637 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
de568510 1638 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
b52eb4dc 1639
b52eb4dc
ZY		 1640 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1641 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1642 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1643 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1644 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1645 /* enable it... */
bed4a673 1646 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc 1647
9c04f015
YL		 1648 if (IS_GEN6(dev)) {
1649 I915_WRITE(SNB_DPFC_CTL_SA,
016b9b61 1650 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
9c04f015 1651 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
4efe0708 1652 sandybridge_blit_fbc_update(dev);
9c04f015
YL		 1653 }
1654
b52eb4dc
ZY		 1655 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1656}
1657
43a9539f 1658static void ironlake_disable_fbc(struct drm_device *dev)
b52eb4dc
ZY		 1659{
1660 struct drm_i915_private *dev_priv = dev->dev_private;
1661 u32 dpfc_ctl;
1662
1663 /* Disable compression */
1664 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW		 1665 if (dpfc_ctl & DPFC_CTL_EN) {
1666 dpfc_ctl &= ~DPFC_CTL_EN;
1667 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1668
bed4a673
CW		 1669 DRM_DEBUG_KMS("disabled FBC\n");
1670 }
b52eb4dc
ZY		 1671}
1672
1673static bool ironlake_fbc_enabled(struct drm_device *dev)
1674{
1675 struct drm_i915_private *dev_priv = dev->dev_private;
1676
1677 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1678}
1679
ee5382ae
AJ		 1680bool intel_fbc_enabled(struct drm_device *dev)
1681{
1682 struct drm_i915_private *dev_priv = dev->dev_private;
1683
1684 if (!dev_priv->display.fbc_enabled)
1685 return false;
1686
1687 return dev_priv->display.fbc_enabled(dev);
1688}
1689
1630fe75
CW		 1690static void intel_fbc_work_fn(struct work_struct *__work)
1691{
1692 struct intel_fbc_work *work =
1693 container_of(to_delayed_work(__work),
1694 struct intel_fbc_work, work);
1695 struct drm_device *dev = work->crtc->dev;
1696 struct drm_i915_private *dev_priv = dev->dev_private;
1697
1698 mutex_lock(&dev->struct_mutex);
1699 if (work == dev_priv->fbc_work) {
1700 /* Double check that we haven't switched fb without cancelling
1701 * the prior work.
1702 */
016b9b61 1703 if (work->crtc->fb == work->fb) {
1630fe75
CW		 1704 dev_priv->display.enable_fbc(work->crtc,
1705 work->interval);
1706
016b9b61
CW		 1707 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1708 dev_priv->cfb_fb = work->crtc->fb->base.id;
1709 dev_priv->cfb_y = work->crtc->y;
1710 }
1711
1630fe75
CW		 1712 dev_priv->fbc_work = NULL;
1713 }
1714 mutex_unlock(&dev->struct_mutex);
1715
1716 kfree(work);
1717}
1718
1719static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1720{
1721 if (dev_priv->fbc_work == NULL)
1722 return;
1723
1724 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1725
1726 /* Synchronisation is provided by struct_mutex and checking of
1727 * dev_priv->fbc_work, so we can perform the cancellation
1728 * entirely asynchronously.
1729 */
1730 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1731 /* tasklet was killed before being run, clean up */
1732 kfree(dev_priv->fbc_work);
1733
1734 /* Mark the work as no longer wanted so that if it does
1735 * wake-up (because the work was already running and waiting
1736 * for our mutex), it will discover that is no longer
1737 * necessary to run.
1738 */
1739 dev_priv->fbc_work = NULL;
1740}
1741
43a9539f 1742static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
ee5382ae 1743{
1630fe75
CW		 1744 struct intel_fbc_work *work;
1745 struct drm_device *dev = crtc->dev;
1746 struct drm_i915_private *dev_priv = dev->dev_private;
ee5382ae
AJ		 1747
1748 if (!dev_priv->display.enable_fbc)
1749 return;
1750
1630fe75
CW		 1751 intel_cancel_fbc_work(dev_priv);
1752
1753 work = kzalloc(sizeof *work, GFP_KERNEL);
1754 if (work == NULL) {
1755 dev_priv->display.enable_fbc(crtc, interval);
1756 return;
1757 }
1758
1759 work->crtc = crtc;
1760 work->fb = crtc->fb;
1761 work->interval = interval;
1762 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1763
1764 dev_priv->fbc_work = work;
1765
1766 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1767
1768 /* Delay the actual enabling to let pageflipping cease and the
016b9b61
CW		 1769 * display to settle before starting the compression. Note that
1770 * this delay also serves a second purpose: it allows for a
1771 * vblank to pass after disabling the FBC before we attempt
1772 * to modify the control registers.
1630fe75
CW		 1773 *
1774 * A more complicated solution would involve tracking vblanks
1775 * following the termination of the page-flipping sequence
1776 * and indeed performing the enable as a co-routine and not
1777 * waiting synchronously upon the vblank.
1778 */
1779 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
ee5382ae
AJ		 1780}
1781
1782void intel_disable_fbc(struct drm_device *dev)
1783{
1784 struct drm_i915_private *dev_priv = dev->dev_private;
1785
1630fe75
CW		 1786 intel_cancel_fbc_work(dev_priv);
1787
ee5382ae
AJ		 1788 if (!dev_priv->display.disable_fbc)
1789 return;
1790
1791 dev_priv->display.disable_fbc(dev);
016b9b61 1792 dev_priv->cfb_plane = -1;
ee5382ae
AJ		 1793}
1794
80824003
JB		 1795/**
1796 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1797 * @dev: the drm_device
80824003
JB		 1798 *
1799 * Set up the framebuffer compression hardware at mode set time. We
1800 * enable it if possible:
1801 * - plane A only (on pre-965)
1802 * - no pixel mulitply/line duplication
1803 * - no alpha buffer discard
1804 * - no dual wide
1805 * - framebuffer <= 2048 in width, 1536 in height
1806 *
1807 * We can't assume that any compression will take place (worst case),
1808 * so the compressed buffer has to be the same size as the uncompressed
1809 * one. It also must reside (along with the line length buffer) in
1810 * stolen memory.
1811 *
1812 * We need to enable/disable FBC on a global basis.
1813 */
bed4a673 1814static void intel_update_fbc(struct drm_device *dev)
80824003 1815{
80824003 1816 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW		 1817 struct drm_crtc *crtc = NULL, *tmp_crtc;
1818 struct intel_crtc *intel_crtc;
1819 struct drm_framebuffer *fb;
80824003 1820 struct intel_framebuffer *intel_fb;
05394f39 1821 struct drm_i915_gem_object *obj;
cd0de039 1822 int enable_fbc;
9c928d16
JB		 1823
1824 DRM_DEBUG_KMS("\n");
80824003
JB		 1825
1826 if (!i915_powersave)
1827 return;
1828
ee5382ae 1829 if (!I915_HAS_FBC(dev))
e70236a8
JB		 1830 return;
1831
80824003
JB		 1832 /*
1833 * If FBC is already on, we just have to verify that we can
1834 * keep it that way...
1835 * Need to disable if:
9c928d16 1836 * - more than one pipe is active
80824003
JB		 1837 * - changing FBC params (stride, fence, mode)
1838 * - new fb is too large to fit in compressed buffer
1839 * - going to an unsupported config (interlace, pixel multiply, etc.)
1840 */
9c928d16 1841 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
d210246a 1842 if (tmp_crtc->enabled && tmp_crtc->fb) {
bed4a673
CW		 1843 if (crtc) {
1844 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1845 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1846 goto out_disable;
1847 }
1848 crtc = tmp_crtc;
1849 }
9c928d16 1850 }
bed4a673
CW		 1851
1852 if (!crtc || crtc->fb == NULL) {
1853 DRM_DEBUG_KMS("no output, disabling\n");
1854 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB		 1855 goto out_disable;
1856 }
bed4a673
CW		 1857
1858 intel_crtc = to_intel_crtc(crtc);
1859 fb = crtc->fb;
1860 intel_fb = to_intel_framebuffer(fb);
05394f39 1861 obj = intel_fb->obj;
bed4a673 1862
cd0de039
KP		 1863 enable_fbc = i915_enable_fbc;
1864 if (enable_fbc < 0) {
1865 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1866 enable_fbc = 1;
1867 if (INTEL_INFO(dev)->gen <= 5)
1868 enable_fbc = 0;
1869 }
1870 if (!enable_fbc) {
1871 DRM_DEBUG_KMS("fbc disabled per module param\n");
c1a9f047
JB		 1872 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1873 goto out_disable;
1874 }
05394f39 1875 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 1876 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 1877 "compression\n");
b5e50c3f 1878 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1879 goto out_disable;
1880 }
bed4a673
CW		 1881 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1882 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 1883 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 1884 "disabling\n");
b5e50c3f 1885 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB		 1886 goto out_disable;
1887 }
bed4a673
CW		 1888 if ((crtc->mode.hdisplay > 2048) ||
1889 (crtc->mode.vdisplay > 1536)) {
28c97730 1890 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 1891 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB		 1892 goto out_disable;
1893 }
bed4a673 1894 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 1895 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 1896 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB		 1897 goto out_disable;
1898 }
de568510
CW		 1899
1900 /* The use of a CPU fence is mandatory in order to detect writes
1901 * by the CPU to the scanout and trigger updates to the FBC.
1902 */
1903 if (obj->tiling_mode != I915_TILING_X ||
1904 obj->fence_reg == I915_FENCE_REG_NONE) {
1905 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
b5e50c3f 1906 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB		 1907 goto out_disable;
1908 }
1909
c924b934
JW		 1910 /* If the kernel debugger is active, always disable compression */
1911 if (in_dbg_master())
1912 goto out_disable;
1913
016b9b61
CW		 1914 /* If the scanout has not changed, don't modify the FBC settings.
1915 * Note that we make the fundamental assumption that the fb->obj
1916 * cannot be unpinned (and have its GTT offset and fence revoked)
1917 * without first being decoupled from the scanout and FBC disabled.
1918 */
1919 if (dev_priv->cfb_plane == intel_crtc->plane &&
1920 dev_priv->cfb_fb == fb->base.id &&
1921 dev_priv->cfb_y == crtc->y)
1922 return;
1923
1924 if (intel_fbc_enabled(dev)) {
1925 /* We update FBC along two paths, after changing fb/crtc
1926 * configuration (modeswitching) and after page-flipping
1927 * finishes. For the latter, we know that not only did
1928 * we disable the FBC at the start of the page-flip
1929 * sequence, but also more than one vblank has passed.
1930 *
1931 * For the former case of modeswitching, it is possible
1932 * to switch between two FBC valid configurations
1933 * instantaneously so we do need to disable the FBC
1934 * before we can modify its control registers. We also
1935 * have to wait for the next vblank for that to take
1936 * effect. However, since we delay enabling FBC we can
1937 * assume that a vblank has passed since disabling and
1938 * that we can safely alter the registers in the deferred
1939 * callback.
1940 *
1941 * In the scenario that we go from a valid to invalid
1942 * and then back to valid FBC configuration we have
1943 * no strict enforcement that a vblank occurred since
1944 * disabling the FBC. However, along all current pipe
1945 * disabling paths we do need to wait for a vblank at
1946 * some point. And we wait before enabling FBC anyway.
1947 */
1948 DRM_DEBUG_KMS("disabling active FBC for update\n");
1949 intel_disable_fbc(dev);
1950 }
1951
bed4a673 1952 intel_enable_fbc(crtc, 500);
80824003
JB		 1953 return;
1954
1955out_disable:
80824003 1956 /* Multiple disables should be harmless */
a939406f
CW		 1957 if (intel_fbc_enabled(dev)) {
1958 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 1959 intel_disable_fbc(dev);
a939406f 1960 }
80824003
JB		 1961}
1962
127bd2ac 1963int
48b956c5 1964intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1965 struct drm_i915_gem_object *obj,
919926ae 1966 struct intel_ring_buffer *pipelined)
6b95a207 1967{
ce453d81 1968 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1969 u32 alignment;
1970 int ret;
1971
05394f39 1972 switch (obj->tiling_mode) {
6b95a207 1973 case I915_TILING_NONE:
534843da
CW		 1974 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1975 alignment = 128 * 1024;
a6c45cf0 1976 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1977 alignment = 4 * 1024;
1978 else
1979 alignment = 64 * 1024;
6b95a207
KH		 1980 break;
1981 case I915_TILING_X:
1982 /* pin() will align the object as required by fence */
1983 alignment = 0;
1984 break;
1985 case I915_TILING_Y:
1986 /* FIXME: Is this true? */
1987 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1988 return -EINVAL;
1989 default:
1990 BUG();
1991 }
1992
ce453d81 1993 dev_priv->mm.interruptible = false;
2da3b9b9 1994 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1995 if (ret)
ce453d81 1996 goto err_interruptible;
6b95a207
KH		 1997
1998 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1999 * fence, whereas 965+ only requires a fence if using
2000 * framebuffer compression. For simplicity, we always install
2001 * a fence as the cost is not that onerous.
2002 */
05394f39 2003 if (obj->tiling_mode != I915_TILING_NONE) {
ce453d81 2004 ret = i915_gem_object_get_fence(obj, pipelined);
48b956c5
CW		 2005 if (ret)
2006 goto err_unpin;
6b95a207
KH		 2007 }
2008
ce453d81 2009 dev_priv->mm.interruptible = true;
6b95a207 2010 return 0;
48b956c5
CW		 2011
2012err_unpin:
2013 i915_gem_object_unpin(obj);
ce453d81
CW		 2014err_interruptible:
2015 dev_priv->mm.interruptible = true;
48b956c5 2016 return ret;
6b95a207
KH		 2017}
2018
17638cd6
JB		 2019static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2020 int x, int y)
81255565
JB		 2021{
2022 struct drm_device *dev = crtc->dev;
2023 struct drm_i915_private *dev_priv = dev->dev_private;
2024 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2025 struct intel_framebuffer *intel_fb;
05394f39 2026 struct drm_i915_gem_object *obj;
81255565
JB		 2027 int plane = intel_crtc->plane;
2028 unsigned long Start, Offset;
81255565 2029 u32 dspcntr;
5eddb70b 2030 u32 reg;
81255565
JB		 2031
2032 switch (plane) {
2033 case 0:
2034 case 1:
2035 break;
2036 default:
2037 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2038 return -EINVAL;
2039 }
2040
2041 intel_fb = to_intel_framebuffer(fb);
2042 obj = intel_fb->obj;
81255565 2043
5eddb70b
CW		 2044 reg = DSPCNTR(plane);
2045 dspcntr = I915_READ(reg);
81255565
JB		 2046 /* Mask out pixel format bits in case we change it */
2047 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2048 switch (fb->bits_per_pixel) {
2049 case 8:
2050 dspcntr |= DISPPLANE_8BPP;
2051 break;
2052 case 16:
2053 if (fb->depth == 15)
2054 dspcntr |= DISPPLANE_15_16BPP;
2055 else
2056 dspcntr |= DISPPLANE_16BPP;
2057 break;
2058 case 24:
2059 case 32:
2060 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2061 break;
2062 default:
17638cd6 2063 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2064 return -EINVAL;
2065 }
a6c45cf0 2066 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2067 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2068 dspcntr |= DISPPLANE_TILED;
2069 else
2070 dspcntr &= ~DISPPLANE_TILED;
2071 }
2072
5eddb70b 2073 I915_WRITE(reg, dspcntr);
81255565 2074
05394f39 2075 Start = obj->gtt_offset;
81255565
JB		 2076 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2077
4e6cfefc
CW		 2078 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2079 Start, Offset, x, y, fb->pitch);
5eddb70b 2080 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
a6c45cf0 2081 if (INTEL_INFO(dev)->gen >= 4) {
5eddb70b
CW		 2082 I915_WRITE(DSPSURF(plane), Start);
2083 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2084 I915_WRITE(DSPADDR(plane), Offset);
2085 } else
2086 I915_WRITE(DSPADDR(plane), Start + Offset);
2087 POSTING_READ(reg);
81255565 2088
17638cd6
JB		 2089 return 0;
2090}
2091
2092static int ironlake_update_plane(struct drm_crtc *crtc,
2093 struct drm_framebuffer *fb, int x, int y)
2094{
2095 struct drm_device *dev = crtc->dev;
2096 struct drm_i915_private *dev_priv = dev->dev_private;
2097 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2098 struct intel_framebuffer *intel_fb;
2099 struct drm_i915_gem_object *obj;
2100 int plane = intel_crtc->plane;
2101 unsigned long Start, Offset;
2102 u32 dspcntr;
2103 u32 reg;
2104
2105 switch (plane) {
2106 case 0:
2107 case 1:
27f8227b 2108 case 2:
17638cd6
JB		 2109 break;
2110 default:
2111 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2112 return -EINVAL;
2113 }
2114
2115 intel_fb = to_intel_framebuffer(fb);
2116 obj = intel_fb->obj;
2117
2118 reg = DSPCNTR(plane);
2119 dspcntr = I915_READ(reg);
2120 /* Mask out pixel format bits in case we change it */
2121 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2122 switch (fb->bits_per_pixel) {
2123 case 8:
2124 dspcntr |= DISPPLANE_8BPP;
2125 break;
2126 case 16:
2127 if (fb->depth != 16)
2128 return -EINVAL;
2129
2130 dspcntr |= DISPPLANE_16BPP;
2131 break;
2132 case 24:
2133 case 32:
2134 if (fb->depth == 24)
2135 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2136 else if (fb->depth == 30)
2137 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2138 else
2139 return -EINVAL;
2140 break;
2141 default:
2142 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2143 return -EINVAL;
2144 }
2145
2146 if (obj->tiling_mode != I915_TILING_NONE)
2147 dspcntr |= DISPPLANE_TILED;
2148 else
2149 dspcntr &= ~DISPPLANE_TILED;
2150
2151 /* must disable */
2152 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2153
2154 I915_WRITE(reg, dspcntr);
2155
2156 Start = obj->gtt_offset;
2157 Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
2158
2159 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2160 Start, Offset, x, y, fb->pitch);
2161 I915_WRITE(DSPSTRIDE(plane), fb->pitch);
2162 I915_WRITE(DSPSURF(plane), Start);
2163 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2164 I915_WRITE(DSPADDR(plane), Offset);
2165 POSTING_READ(reg);
2166
2167 return 0;
2168}
2169
2170/* Assume fb object is pinned & idle & fenced and just update base pointers */
2171static int
2172intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2173 int x, int y, enum mode_set_atomic state)
2174{
2175 struct drm_device *dev = crtc->dev;
2176 struct drm_i915_private *dev_priv = dev->dev_private;
2177 int ret;
2178
2179 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2180 if (ret)
2181 return ret;
2182
bed4a673 2183 intel_update_fbc(dev);
3dec0095 2184 intel_increase_pllclock(crtc);
81255565
JB		 2185
2186 return 0;
2187}
2188
5c3b82e2 2189static int
3c4fdcfb
KH		 2190intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2191 struct drm_framebuffer *old_fb)
79e53945
JB		 2192{
2193 struct drm_device *dev = crtc->dev;
79e53945
JB		 2194 struct drm_i915_master_private *master_priv;
2195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2196 int ret;
79e53945
JB		 2197
2198 /* no fb bound */
2199 if (!crtc->fb) {
a5071c2f 2200 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2201 return 0;
2202 }
2203
265db958 2204 switch (intel_crtc->plane) {
5c3b82e2
CW		 2205 case 0:
2206 case 1:
2207 break;
27f8227b
JB		 2208 case 2:
2209 if (IS_IVYBRIDGE(dev))
2210 break;
2211 /* fall through otherwise */
5c3b82e2 2212 default:
a5071c2f 2213 DRM_ERROR("no plane for crtc\n");
5c3b82e2 2214 return -EINVAL;
79e53945
JB		 2215 }
2216
5c3b82e2 2217 mutex_lock(&dev->struct_mutex);
265db958
CW		 2218 ret = intel_pin_and_fence_fb_obj(dev,
2219 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2220 NULL);
5c3b82e2
CW		 2221 if (ret != 0) {
2222 mutex_unlock(&dev->struct_mutex);
a5071c2f 2223 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2224 return ret;
2225 }
79e53945 2226
265db958 2227 if (old_fb) {
e6c3a2a6 2228 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 2229 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
265db958 2230
e6c3a2a6 2231 wait_event(dev_priv->pending_flip_queue,
01eec727 2232 atomic_read(&dev_priv->mm.wedged) ||
05394f39 2233 atomic_read(&obj->pending_flip) == 0);
85345517
CW		 2234
2235 /* Big Hammer, we also need to ensure that any pending
2236 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2237 * current scanout is retired before unpinning the old
2238 * framebuffer.
01eec727
CW		 2239 *
2240 * This should only fail upon a hung GPU, in which case we
2241 * can safely continue.
85345517 2242 */
a8198eea 2243 ret = i915_gem_object_finish_gpu(obj);
01eec727 2244 (void) ret;
265db958
CW		 2245 }
2246
21c74a8e
JW		 2247 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2248 LEAVE_ATOMIC_MODE_SET);
4e6cfefc 2249 if (ret) {
265db958 2250 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2251 mutex_unlock(&dev->struct_mutex);
a5071c2f 2252 DRM_ERROR("failed to update base address\n");
4e6cfefc 2253 return ret;
79e53945 2254 }
3c4fdcfb 2255
b7f1de28
CW		 2256 if (old_fb) {
2257 intel_wait_for_vblank(dev, intel_crtc->pipe);
265db958 2258 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2259 }
652c393a 2260
5c3b82e2 2261 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2262
2263 if (!dev->primary->master)
5c3b82e2 2264 return 0;
79e53945
JB		 2265
2266 master_priv = dev->primary->master->driver_priv;
2267 if (!master_priv->sarea_priv)
5c3b82e2 2268 return 0;
79e53945 2269
265db958 2270 if (intel_crtc->pipe) {
79e53945
JB		 2271 master_priv->sarea_priv->pipeB_x = x;
2272 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2273 } else {
2274 master_priv->sarea_priv->pipeA_x = x;
2275 master_priv->sarea_priv->pipeA_y = y;
79e53945 2276 }
5c3b82e2
CW		 2277
2278 return 0;
79e53945
JB		 2279}
2280
5eddb70b 2281static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2282{
2283 struct drm_device *dev = crtc->dev;
2284 struct drm_i915_private *dev_priv = dev->dev_private;
2285 u32 dpa_ctl;
2286
28c97730 2287 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2288 dpa_ctl = I915_READ(DP_A);
2289 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2290
2291 if (clock < 200000) {
2292 u32 temp;
2293 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2294 /* workaround for 160Mhz:
2295 1) program 0x4600c bits 15:0 = 0x8124
2296 2) program 0x46010 bit 0 = 1
2297 3) program 0x46034 bit 24 = 1
2298 4) program 0x64000 bit 14 = 1
2299 */
2300 temp = I915_READ(0x4600c);
2301 temp &= 0xffff0000;
2302 I915_WRITE(0x4600c, temp | 0x8124);
2303
2304 temp = I915_READ(0x46010);
2305 I915_WRITE(0x46010, temp | 1);
2306
2307 temp = I915_READ(0x46034);
2308 I915_WRITE(0x46034, temp | (1 << 24));
2309 } else {
2310 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2311 }
2312 I915_WRITE(DP_A, dpa_ctl);
2313
5eddb70b 2314 POSTING_READ(DP_A);
32f9d658
ZW		 2315 udelay(500);
2316}
2317
5e84e1a4
ZW		 2318static void intel_fdi_normal_train(struct drm_crtc *crtc)
2319{
2320 struct drm_device *dev = crtc->dev;
2321 struct drm_i915_private *dev_priv = dev->dev_private;
2322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2323 int pipe = intel_crtc->pipe;
2324 u32 reg, temp;
2325
2326 /* enable normal train */
2327 reg = FDI_TX_CTL(pipe);
2328 temp = I915_READ(reg);
61e499bf 2329 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2330 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2331 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2332 } else {
2333 temp &= ~FDI_LINK_TRAIN_NONE;
2334 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2335 }
5e84e1a4
ZW		 2336 I915_WRITE(reg, temp);
2337
2338 reg = FDI_RX_CTL(pipe);
2339 temp = I915_READ(reg);
2340 if (HAS_PCH_CPT(dev)) {
2341 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2342 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2343 } else {
2344 temp &= ~FDI_LINK_TRAIN_NONE;
2345 temp |= FDI_LINK_TRAIN_NONE;
2346 }
2347 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2348
2349 /* wait one idle pattern time */
2350 POSTING_READ(reg);
2351 udelay(1000);
357555c0
JB		 2352
2353 /* IVB wants error correction enabled */
2354 if (IS_IVYBRIDGE(dev))
2355 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2356 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2357}
2358
291427f5
JB		 2359static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2360{
2361 struct drm_i915_private *dev_priv = dev->dev_private;
2362 u32 flags = I915_READ(SOUTH_CHICKEN1);
2363
2364 flags |= FDI_PHASE_SYNC_OVR(pipe);
2365 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2366 flags |= FDI_PHASE_SYNC_EN(pipe);
2367 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2368 POSTING_READ(SOUTH_CHICKEN1);
2369}
2370
8db9d77b
ZW		 2371/* The FDI link training functions for ILK/Ibexpeak. */
2372static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2373{
2374 struct drm_device *dev = crtc->dev;
2375 struct drm_i915_private *dev_priv = dev->dev_private;
2376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2377 int pipe = intel_crtc->pipe;
0fc932b8 2378 int plane = intel_crtc->plane;
5eddb70b 2379 u32 reg, temp, tries;
8db9d77b 2380
0fc932b8
JB		 2381 /* FDI needs bits from pipe & plane first */
2382 assert_pipe_enabled(dev_priv, pipe);
2383 assert_plane_enabled(dev_priv, plane);
2384
e1a44743
AJ		 2385 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2386 for train result */
5eddb70b
CW		 2387 reg = FDI_RX_IMR(pipe);
2388 temp = I915_READ(reg);
e1a44743
AJ		 2389 temp &= ~FDI_RX_SYMBOL_LOCK;
2390 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2391 I915_WRITE(reg, temp);
2392 I915_READ(reg);
e1a44743
AJ		 2393 udelay(150);
2394
8db9d77b 2395 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2396 reg = FDI_TX_CTL(pipe);
2397 temp = I915_READ(reg);
77ffb597
AJ		 2398 temp &= ~(7 << 19);
2399 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2400 temp &= ~FDI_LINK_TRAIN_NONE;
2401 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2402 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2403
5eddb70b
CW		 2404 reg = FDI_RX_CTL(pipe);
2405 temp = I915_READ(reg);
8db9d77b
ZW		 2406 temp &= ~FDI_LINK_TRAIN_NONE;
2407 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2408 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2409
2410 POSTING_READ(reg);
8db9d77b
ZW		 2411 udelay(150);
2412
5b2adf89 2413 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2414 if (HAS_PCH_IBX(dev)) {
2415 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2416 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2417 FDI_RX_PHASE_SYNC_POINTER_EN);
2418 }
5b2adf89 2419
5eddb70b 2420 reg = FDI_RX_IIR(pipe);
e1a44743 2421 for (tries = 0; tries < 5; tries++) {
5eddb70b 2422 temp = I915_READ(reg);
8db9d77b
ZW		 2423 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2424
2425 if ((temp & FDI_RX_BIT_LOCK)) {
2426 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2427 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2428 break;
2429 }
8db9d77b 2430 }
e1a44743 2431 if (tries == 5)
5eddb70b 2432 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2433
2434 /* Train 2 */
5eddb70b
CW		 2435 reg = FDI_TX_CTL(pipe);
2436 temp = I915_READ(reg);
8db9d77b
ZW		 2437 temp &= ~FDI_LINK_TRAIN_NONE;
2438 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2439 I915_WRITE(reg, temp);
8db9d77b 2440
5eddb70b
CW		 2441 reg = FDI_RX_CTL(pipe);
2442 temp = I915_READ(reg);
8db9d77b
ZW		 2443 temp &= ~FDI_LINK_TRAIN_NONE;
2444 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2445 I915_WRITE(reg, temp);
8db9d77b 2446
5eddb70b
CW		 2447 POSTING_READ(reg);
2448 udelay(150);
8db9d77b 2449
5eddb70b 2450 reg = FDI_RX_IIR(pipe);
e1a44743 2451 for (tries = 0; tries < 5; tries++) {
5eddb70b 2452 temp = I915_READ(reg);
8db9d77b
ZW		 2453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2456 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2457 DRM_DEBUG_KMS("FDI train 2 done.\n");
2458 break;
2459 }
8db9d77b 2460 }
e1a44743 2461 if (tries == 5)
5eddb70b 2462 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2463
2464 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2465
8db9d77b
ZW		 2466}
2467
0206e353 2468static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2469 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2470 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2471 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2472 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2473};
2474
2475/* The FDI link training functions for SNB/Cougarpoint. */
2476static void gen6_fdi_link_train(struct drm_crtc *crtc)
2477{
2478 struct drm_device *dev = crtc->dev;
2479 struct drm_i915_private *dev_priv = dev->dev_private;
2480 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2481 int pipe = intel_crtc->pipe;
5eddb70b 2482 u32 reg, temp, i;
8db9d77b 2483
e1a44743
AJ		 2484 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2485 for train result */
5eddb70b
CW		 2486 reg = FDI_RX_IMR(pipe);
2487 temp = I915_READ(reg);
e1a44743
AJ		 2488 temp &= ~FDI_RX_SYMBOL_LOCK;
2489 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2490 I915_WRITE(reg, temp);
2491
2492 POSTING_READ(reg);
e1a44743
AJ		 2493 udelay(150);
2494
8db9d77b 2495 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2496 reg = FDI_TX_CTL(pipe);
2497 temp = I915_READ(reg);
77ffb597
AJ		 2498 temp &= ~(7 << 19);
2499 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2500 temp &= ~FDI_LINK_TRAIN_NONE;
2501 temp |= FDI_LINK_TRAIN_PATTERN_1;
2502 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2503 /* SNB-B */
2504 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2505 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2506
5eddb70b
CW		 2507 reg = FDI_RX_CTL(pipe);
2508 temp = I915_READ(reg);
8db9d77b
ZW		 2509 if (HAS_PCH_CPT(dev)) {
2510 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2511 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2512 } else {
2513 temp &= ~FDI_LINK_TRAIN_NONE;
2514 temp |= FDI_LINK_TRAIN_PATTERN_1;
2515 }
5eddb70b
CW		 2516 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2517
2518 POSTING_READ(reg);
8db9d77b
ZW		 2519 udelay(150);
2520
291427f5
JB		 2521 if (HAS_PCH_CPT(dev))
2522 cpt_phase_pointer_enable(dev, pipe);
2523
0206e353 2524 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2525 reg = FDI_TX_CTL(pipe);
2526 temp = I915_READ(reg);
8db9d77b
ZW		 2527 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2528 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2529 I915_WRITE(reg, temp);
2530
2531 POSTING_READ(reg);
8db9d77b
ZW		 2532 udelay(500);
2533
5eddb70b
CW		 2534 reg = FDI_RX_IIR(pipe);
2535 temp = I915_READ(reg);
8db9d77b
ZW		 2536 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2537
2538 if (temp & FDI_RX_BIT_LOCK) {
5eddb70b 2539 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2540 DRM_DEBUG_KMS("FDI train 1 done.\n");
2541 break;
2542 }
2543 }
2544 if (i == 4)
5eddb70b 2545 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2546
2547 /* Train 2 */
5eddb70b
CW		 2548 reg = FDI_TX_CTL(pipe);
2549 temp = I915_READ(reg);
8db9d77b
ZW		 2550 temp &= ~FDI_LINK_TRAIN_NONE;
2551 temp |= FDI_LINK_TRAIN_PATTERN_2;
2552 if (IS_GEN6(dev)) {
2553 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2554 /* SNB-B */
2555 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2556 }
5eddb70b 2557 I915_WRITE(reg, temp);
8db9d77b 2558
5eddb70b
CW		 2559 reg = FDI_RX_CTL(pipe);
2560 temp = I915_READ(reg);
8db9d77b
ZW		 2561 if (HAS_PCH_CPT(dev)) {
2562 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2563 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2564 } else {
2565 temp &= ~FDI_LINK_TRAIN_NONE;
2566 temp |= FDI_LINK_TRAIN_PATTERN_2;
2567 }
5eddb70b
CW		 2568 I915_WRITE(reg, temp);
2569
2570 POSTING_READ(reg);
8db9d77b
ZW		 2571 udelay(150);
2572
0206e353 2573 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2574 reg = FDI_TX_CTL(pipe);
2575 temp = I915_READ(reg);
8db9d77b
ZW		 2576 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2577 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2578 I915_WRITE(reg, temp);
2579
2580 POSTING_READ(reg);
8db9d77b
ZW		 2581 udelay(500);
2582
5eddb70b
CW		 2583 reg = FDI_RX_IIR(pipe);
2584 temp = I915_READ(reg);
8db9d77b
ZW		 2585 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2586
2587 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2588 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2589 DRM_DEBUG_KMS("FDI train 2 done.\n");
2590 break;
2591 }
2592 }
2593 if (i == 4)
5eddb70b 2594 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2595
2596 DRM_DEBUG_KMS("FDI train done.\n");
2597}
2598
357555c0
JB		 2599/* Manual link training for Ivy Bridge A0 parts */
2600static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2601{
2602 struct drm_device *dev = crtc->dev;
2603 struct drm_i915_private *dev_priv = dev->dev_private;
2604 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2605 int pipe = intel_crtc->pipe;
2606 u32 reg, temp, i;
2607
2608 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2609 for train result */
2610 reg = FDI_RX_IMR(pipe);
2611 temp = I915_READ(reg);
2612 temp &= ~FDI_RX_SYMBOL_LOCK;
2613 temp &= ~FDI_RX_BIT_LOCK;
2614 I915_WRITE(reg, temp);
2615
2616 POSTING_READ(reg);
2617 udelay(150);
2618
2619 /* enable CPU FDI TX and PCH FDI RX */
2620 reg = FDI_TX_CTL(pipe);
2621 temp = I915_READ(reg);
2622 temp &= ~(7 << 19);
2623 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2624 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2625 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2626 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2627 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2628 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2629 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2630
2631 reg = FDI_RX_CTL(pipe);
2632 temp = I915_READ(reg);
2633 temp &= ~FDI_LINK_TRAIN_AUTO;
2634 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2635 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2636 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2637 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2638
2639 POSTING_READ(reg);
2640 udelay(150);
2641
291427f5
JB		 2642 if (HAS_PCH_CPT(dev))
2643 cpt_phase_pointer_enable(dev, pipe);
2644
0206e353 2645 for (i = 0; i < 4; i++) {
357555c0
JB		 2646 reg = FDI_TX_CTL(pipe);
2647 temp = I915_READ(reg);
2648 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2649 temp |= snb_b_fdi_train_param[i];
2650 I915_WRITE(reg, temp);
2651
2652 POSTING_READ(reg);
2653 udelay(500);
2654
2655 reg = FDI_RX_IIR(pipe);
2656 temp = I915_READ(reg);
2657 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2658
2659 if (temp & FDI_RX_BIT_LOCK ||
2660 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2661 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2662 DRM_DEBUG_KMS("FDI train 1 done.\n");
2663 break;
2664 }
2665 }
2666 if (i == 4)
2667 DRM_ERROR("FDI train 1 fail!\n");
2668
2669 /* Train 2 */
2670 reg = FDI_TX_CTL(pipe);
2671 temp = I915_READ(reg);
2672 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2673 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2674 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2675 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2676 I915_WRITE(reg, temp);
2677
2678 reg = FDI_RX_CTL(pipe);
2679 temp = I915_READ(reg);
2680 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2681 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2682 I915_WRITE(reg, temp);
2683
2684 POSTING_READ(reg);
2685 udelay(150);
2686
0206e353 2687 for (i = 0; i < 4; i++) {
357555c0
JB		 2688 reg = FDI_TX_CTL(pipe);
2689 temp = I915_READ(reg);
2690 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2691 temp |= snb_b_fdi_train_param[i];
2692 I915_WRITE(reg, temp);
2693
2694 POSTING_READ(reg);
2695 udelay(500);
2696
2697 reg = FDI_RX_IIR(pipe);
2698 temp = I915_READ(reg);
2699 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2700
2701 if (temp & FDI_RX_SYMBOL_LOCK) {
2702 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2703 DRM_DEBUG_KMS("FDI train 2 done.\n");
2704 break;
2705 }
2706 }
2707 if (i == 4)
2708 DRM_ERROR("FDI train 2 fail!\n");
2709
2710 DRM_DEBUG_KMS("FDI train done.\n");
2711}
2712
2713static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2714{
2715 struct drm_device *dev = crtc->dev;
2716 struct drm_i915_private *dev_priv = dev->dev_private;
2717 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2718 int pipe = intel_crtc->pipe;
5eddb70b 2719 u32 reg, temp;
79e53945 2720
c64e311e 2721 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2722 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2723 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2724
c98e9dcf 2725 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2726 reg = FDI_RX_CTL(pipe);
2727 temp = I915_READ(reg);
2728 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2729 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2730 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2731 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2732
2733 POSTING_READ(reg);
c98e9dcf
JB		 2734 udelay(200);
2735
2736 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2737 temp = I915_READ(reg);
2738 I915_WRITE(reg, temp | FDI_PCDCLK);
2739
2740 POSTING_READ(reg);
c98e9dcf
JB		 2741 udelay(200);
2742
2743 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2744 reg = FDI_TX_CTL(pipe);
2745 temp = I915_READ(reg);
c98e9dcf 2746 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2747 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2748
2749 POSTING_READ(reg);
c98e9dcf 2750 udelay(100);
6be4a607 2751 }
0e23b99d
JB		 2752}
2753
291427f5
JB		 2754static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2755{
2756 struct drm_i915_private *dev_priv = dev->dev_private;
2757 u32 flags = I915_READ(SOUTH_CHICKEN1);
2758
2759 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2760 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2761 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2762 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2763 POSTING_READ(SOUTH_CHICKEN1);
2764}
0fc932b8
JB		 2765static void ironlake_fdi_disable(struct drm_crtc *crtc)
2766{
2767 struct drm_device *dev = crtc->dev;
2768 struct drm_i915_private *dev_priv = dev->dev_private;
2769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2770 int pipe = intel_crtc->pipe;
2771 u32 reg, temp;
2772
2773 /* disable CPU FDI tx and PCH FDI rx */
2774 reg = FDI_TX_CTL(pipe);
2775 temp = I915_READ(reg);
2776 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2777 POSTING_READ(reg);
2778
2779 reg = FDI_RX_CTL(pipe);
2780 temp = I915_READ(reg);
2781 temp &= ~(0x7 << 16);
2782 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2783 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2784
2785 POSTING_READ(reg);
2786 udelay(100);
2787
2788 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2789 if (HAS_PCH_IBX(dev)) {
2790 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2791 I915_WRITE(FDI_RX_CHICKEN(pipe),
2792 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2793 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2794 } else if (HAS_PCH_CPT(dev)) {
2795 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2796 }
0fc932b8
JB		 2797
2798 /* still set train pattern 1 */
2799 reg = FDI_TX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 temp &= ~FDI_LINK_TRAIN_NONE;
2802 temp |= FDI_LINK_TRAIN_PATTERN_1;
2803 I915_WRITE(reg, temp);
2804
2805 reg = FDI_RX_CTL(pipe);
2806 temp = I915_READ(reg);
2807 if (HAS_PCH_CPT(dev)) {
2808 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2809 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2810 } else {
2811 temp &= ~FDI_LINK_TRAIN_NONE;
2812 temp |= FDI_LINK_TRAIN_PATTERN_1;
2813 }
2814 /* BPC in FDI rx is consistent with that in PIPECONF */
2815 temp &= ~(0x07 << 16);
2816 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2817 I915_WRITE(reg, temp);
2818
2819 POSTING_READ(reg);
2820 udelay(100);
2821}
2822
6b383a7f
CW		 2823/*
2824 * When we disable a pipe, we need to clear any pending scanline wait events
2825 * to avoid hanging the ring, which we assume we are waiting on.
2826 */
2827static void intel_clear_scanline_wait(struct drm_device *dev)
2828{
2829 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 2830 struct intel_ring_buffer *ring;
6b383a7f
CW		 2831 u32 tmp;
2832
2833 if (IS_GEN2(dev))
2834 /* Can't break the hang on i8xx */
2835 return;
2836
1ec14ad3 2837 ring = LP_RING(dev_priv);
8168bd48
CW		 2838 tmp = I915_READ_CTL(ring);
2839 if (tmp & RING_WAIT)
2840 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 2841}
2842
e6c3a2a6
CW		 2843static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2844{
05394f39 2845 struct drm_i915_gem_object *obj;
e6c3a2a6
CW		 2846 struct drm_i915_private *dev_priv;
2847
2848 if (crtc->fb == NULL)
2849 return;
2850
05394f39 2851 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW		 2852 dev_priv = crtc->dev->dev_private;
2853 wait_event(dev_priv->pending_flip_queue,
05394f39 2854 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW		 2855}
2856
040484af
JB		 2857static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2858{
2859 struct drm_device *dev = crtc->dev;
2860 struct drm_mode_config *mode_config = &dev->mode_config;
2861 struct intel_encoder *encoder;
2862
2863 /*
2864 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2865 * must be driven by its own crtc; no sharing is possible.
2866 */
2867 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2868 if (encoder->base.crtc != crtc)
2869 continue;
2870
2871 switch (encoder->type) {
2872 case INTEL_OUTPUT_EDP:
2873 if (!intel_encoder_is_pch_edp(&encoder->base))
2874 return false;
2875 continue;
2876 }
2877 }
2878
2879 return true;
2880}
2881
f67a559d
JB		 2882/*
2883 * Enable PCH resources required for PCH ports:
2884 * - PCH PLLs
2885 * - FDI training & RX/TX
2886 * - update transcoder timings
2887 * - DP transcoding bits
2888 * - transcoder
2889 */
2890static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2891{
2892 struct drm_device *dev = crtc->dev;
2893 struct drm_i915_private *dev_priv = dev->dev_private;
2894 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2895 int pipe = intel_crtc->pipe;
4b645f14 2896 u32 reg, temp, transc_sel;
2c07245f 2897
c98e9dcf 2898 /* For PCH output, training FDI link */
674cf967 2899 dev_priv->display.fdi_link_train(crtc);
2c07245f 2900
92f2584a 2901 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 2902
c98e9dcf 2903 if (HAS_PCH_CPT(dev)) {
4b645f14
JB		 2904 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2905 TRANSC_DPLLB_SEL;
2906
c98e9dcf
JB		 2907 /* Be sure PCH DPLL SEL is set */
2908 temp = I915_READ(PCH_DPLL_SEL);
5eddb70b 2909 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
c98e9dcf 2910 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
5eddb70b 2911 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
c98e9dcf 2912 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
27f8227b 2913 else if (pipe == 2 && (temp & TRANSC_DPLL_ENABLE) == 0)
4b645f14 2914 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
c98e9dcf 2915 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2916 }
5eddb70b 2917
d9b6cb56
JB		 2918 /* set transcoder timing, panel must allow it */
2919 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2920 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2921 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2922 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2923
5eddb70b
CW		 2924 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2925 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2926 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
8db9d77b 2927
5e84e1a4
ZW		 2928 intel_fdi_normal_train(crtc);
2929
c98e9dcf
JB		 2930 /* For PCH DP, enable TRANS_DP_CTL */
2931 if (HAS_PCH_CPT(dev) &&
2932 intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
9325c9f0 2933 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 2934 reg = TRANS_DP_CTL(pipe);
2935 temp = I915_READ(reg);
2936 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2937 TRANS_DP_SYNC_MASK |
2938 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2939 temp |= (TRANS_DP_OUTPUT_ENABLE |
2940 TRANS_DP_ENH_FRAMING);
9325c9f0 2941 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2942
2943 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2944 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2945 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2946 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2947
2948 switch (intel_trans_dp_port_sel(crtc)) {
2949 case PCH_DP_B:
5eddb70b 2950 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2951 break;
2952 case PCH_DP_C:
5eddb70b 2953 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2954 break;
2955 case PCH_DP_D:
5eddb70b 2956 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2957 break;
2958 default:
2959 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2960 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2961 break;
32f9d658 2962 }
2c07245f 2963
5eddb70b 2964 I915_WRITE(reg, temp);
6be4a607 2965 }
b52eb4dc 2966
040484af 2967 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2968}
2969
2970static void ironlake_crtc_enable(struct drm_crtc *crtc)
2971{
2972 struct drm_device *dev = crtc->dev;
2973 struct drm_i915_private *dev_priv = dev->dev_private;
2974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2975 int pipe = intel_crtc->pipe;
2976 int plane = intel_crtc->plane;
2977 u32 temp;
2978 bool is_pch_port;
2979
2980 if (intel_crtc->active)
2981 return;
2982
2983 intel_crtc->active = true;
2984 intel_update_watermarks(dev);
2985
2986 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2987 temp = I915_READ(PCH_LVDS);
2988 if ((temp & LVDS_PORT_EN) == 0)
2989 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
2990 }
2991
2992 is_pch_port = intel_crtc_driving_pch(crtc);
2993
2994 if (is_pch_port)
357555c0 2995 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 2996 else
2997 ironlake_fdi_disable(crtc);
2998
2999 /* Enable panel fitting for LVDS */
3000 if (dev_priv->pch_pf_size &&
3001 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3002 /* Force use of hard-coded filter coefficients
3003 * as some pre-programmed values are broken,
3004 * e.g. x201.
3005 */
9db4a9c7
JB		 3006 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3007 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3008 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3009 }
3010
9c54c0dd
JB		 3011 /*
3012 * On ILK+ LUT must be loaded before the pipe is running but with
3013 * clocks enabled
3014 */
3015 intel_crtc_load_lut(crtc);
3016
f67a559d
JB		 3017 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3018 intel_enable_plane(dev_priv, plane, pipe);
3019
3020 if (is_pch_port)
3021 ironlake_pch_enable(crtc);
c98e9dcf 3022
d1ebd816 3023 mutex_lock(&dev->struct_mutex);
bed4a673 3024 intel_update_fbc(dev);
d1ebd816
BW		 3025 mutex_unlock(&dev->struct_mutex);
3026
6b383a7f 3027 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 3028}
3029
3030static void ironlake_crtc_disable(struct drm_crtc *crtc)
3031{
3032 struct drm_device *dev = crtc->dev;
3033 struct drm_i915_private *dev_priv = dev->dev_private;
3034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3035 int pipe = intel_crtc->pipe;
3036 int plane = intel_crtc->plane;
5eddb70b 3037 u32 reg, temp;
b52eb4dc 3038
f7abfe8b
CW		 3039 if (!intel_crtc->active)
3040 return;
3041
e6c3a2a6 3042 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3043 drm_vblank_off(dev, pipe);
6b383a7f 3044 intel_crtc_update_cursor(crtc, false);
5eddb70b 3045
b24e7179 3046 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3047
973d04f9
CW		 3048 if (dev_priv->cfb_plane == plane)
3049 intel_disable_fbc(dev);
2c07245f 3050
b24e7179 3051 intel_disable_pipe(dev_priv, pipe);
32f9d658 3052
6be4a607 3053 /* Disable PF */
9db4a9c7
JB		 3054 I915_WRITE(PF_CTL(pipe), 0);
3055 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3056
0fc932b8 3057 ironlake_fdi_disable(crtc);
2c07245f 3058
47a05eca
JB		 3059 /* This is a horrible layering violation; we should be doing this in
3060 * the connector/encoder ->prepare instead, but we don't always have
3061 * enough information there about the config to know whether it will
3062 * actually be necessary or just cause undesired flicker.
3063 */
3064 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 3065
040484af 3066 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3067
6be4a607
JB		 3068 if (HAS_PCH_CPT(dev)) {
3069 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3070 reg = TRANS_DP_CTL(pipe);
3071 temp = I915_READ(reg);
3072 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3073 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3074 I915_WRITE(reg, temp);
6be4a607
JB		 3075
3076 /* disable DPLL_SEL */
3077 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3078 switch (pipe) {
3079 case 0:
3080 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
3081 break;
3082 case 1:
6be4a607 3083 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3084 break;
3085 case 2:
4b645f14
JB		 3086 /* C shares PLL A or B */
3087 temp &= ~(TRANSC_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3088 break;
3089 default:
3090 BUG(); /* wtf */
3091 }
6be4a607 3092 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3093 }
e3421a18 3094
6be4a607 3095 /* disable PCH DPLL */
4b645f14
JB		 3096 if (!intel_crtc->no_pll)
3097 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 3098
6be4a607 3099 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 3100 reg = FDI_RX_CTL(pipe);
3101 temp = I915_READ(reg);
3102 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 3103
6be4a607 3104 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 3105 reg = FDI_TX_CTL(pipe);
3106 temp = I915_READ(reg);
3107 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3108
3109 POSTING_READ(reg);
6be4a607 3110 udelay(100);
8db9d77b 3111
5eddb70b
CW		 3112 reg = FDI_RX_CTL(pipe);
3113 temp = I915_READ(reg);
3114 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 3115
6be4a607 3116 /* Wait for the clocks to turn off. */
5eddb70b 3117 POSTING_READ(reg);
6be4a607 3118 udelay(100);
6b383a7f 3119
f7abfe8b 3120 intel_crtc->active = false;
6b383a7f 3121 intel_update_watermarks(dev);
d1ebd816
BW		 3122
3123 mutex_lock(&dev->struct_mutex);
6b383a7f
CW		 3124 intel_update_fbc(dev);
3125 intel_clear_scanline_wait(dev);
d1ebd816 3126 mutex_unlock(&dev->struct_mutex);
6be4a607 3127}
1b3c7a47 3128
6be4a607
JB		 3129static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3130{
3131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3132 int pipe = intel_crtc->pipe;
3133 int plane = intel_crtc->plane;
8db9d77b 3134
6be4a607
JB		 3135 /* XXX: When our outputs are all unaware of DPMS modes other than off
3136 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3137 */
3138 switch (mode) {
3139 case DRM_MODE_DPMS_ON:
3140 case DRM_MODE_DPMS_STANDBY:
3141 case DRM_MODE_DPMS_SUSPEND:
3142 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3143 ironlake_crtc_enable(crtc);
3144 break;
1b3c7a47 3145
6be4a607
JB		 3146 case DRM_MODE_DPMS_OFF:
3147 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3148 ironlake_crtc_disable(crtc);
2c07245f
ZW		 3149 break;
3150 }
3151}
3152
02e792fb
DV		 3153static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3154{
02e792fb 3155 if (!enable && intel_crtc->overlay) {
23f09ce3 3156 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3157 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3158
23f09ce3 3159 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3160 dev_priv->mm.interruptible = false;
3161 (void) intel_overlay_switch_off(intel_crtc->overlay);
3162 dev_priv->mm.interruptible = true;
23f09ce3 3163 mutex_unlock(&dev->struct_mutex);
02e792fb 3164 }
02e792fb 3165
5dcdbcb0
CW		 3166 /* Let userspace switch the overlay on again. In most cases userspace
3167 * has to recompute where to put it anyway.
3168 */
02e792fb
DV		 3169}
3170
0b8765c6 3171static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3172{
3173 struct drm_device *dev = crtc->dev;
79e53945
JB		 3174 struct drm_i915_private *dev_priv = dev->dev_private;
3175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3176 int pipe = intel_crtc->pipe;
80824003 3177 int plane = intel_crtc->plane;
79e53945 3178
f7abfe8b
CW		 3179 if (intel_crtc->active)
3180 return;
3181
3182 intel_crtc->active = true;
6b383a7f
CW		 3183 intel_update_watermarks(dev);
3184
63d7bbe9 3185 intel_enable_pll(dev_priv, pipe);
040484af 3186 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3187 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3188
0b8765c6 3189 intel_crtc_load_lut(crtc);
bed4a673 3190 intel_update_fbc(dev);
79e53945 3191
0b8765c6
JB		 3192 /* Give the overlay scaler a chance to enable if it's on this pipe */
3193 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3194 intel_crtc_update_cursor(crtc, true);
0b8765c6 3195}
79e53945 3196
0b8765c6
JB		 3197static void i9xx_crtc_disable(struct drm_crtc *crtc)
3198{
3199 struct drm_device *dev = crtc->dev;
3200 struct drm_i915_private *dev_priv = dev->dev_private;
3201 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3202 int pipe = intel_crtc->pipe;
3203 int plane = intel_crtc->plane;
b690e96c 3204
f7abfe8b
CW		 3205 if (!intel_crtc->active)
3206 return;
3207
0b8765c6 3208 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3209 intel_crtc_wait_for_pending_flips(crtc);
3210 drm_vblank_off(dev, pipe);
0b8765c6 3211 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3212 intel_crtc_update_cursor(crtc, false);
0b8765c6 3213
973d04f9
CW		 3214 if (dev_priv->cfb_plane == plane)
3215 intel_disable_fbc(dev);
79e53945 3216
b24e7179 3217 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3218 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3219 intel_disable_pll(dev_priv, pipe);
0b8765c6 3220
f7abfe8b 3221 intel_crtc->active = false;
6b383a7f
CW		 3222 intel_update_fbc(dev);
3223 intel_update_watermarks(dev);
3224 intel_clear_scanline_wait(dev);
0b8765c6
JB		 3225}
3226
3227static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3228{
3229 /* XXX: When our outputs are all unaware of DPMS modes other than off
3230 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3231 */
3232 switch (mode) {
3233 case DRM_MODE_DPMS_ON:
3234 case DRM_MODE_DPMS_STANDBY:
3235 case DRM_MODE_DPMS_SUSPEND:
3236 i9xx_crtc_enable(crtc);
3237 break;
3238 case DRM_MODE_DPMS_OFF:
3239 i9xx_crtc_disable(crtc);
79e53945
JB		 3240 break;
3241 }
2c07245f
ZW		 3242}
3243
3244/**
3245 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3246 */
3247static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3248{
3249 struct drm_device *dev = crtc->dev;
e70236a8 3250 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3251 struct drm_i915_master_private *master_priv;
3252 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3253 int pipe = intel_crtc->pipe;
3254 bool enabled;
3255
032d2a0d
CW		 3256 if (intel_crtc->dpms_mode == mode)
3257 return;
3258
65655d4a 3259 intel_crtc->dpms_mode = mode;
debcaddc 3260
e70236a8 3261 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3262
3263 if (!dev->primary->master)
3264 return;
3265
3266 master_priv = dev->primary->master->driver_priv;
3267 if (!master_priv->sarea_priv)
3268 return;
3269
3270 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3271
3272 switch (pipe) {
3273 case 0:
3274 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3275 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3276 break;
3277 case 1:
3278 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3279 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3280 break;
3281 default:
9db4a9c7 3282 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3283 break;
3284 }
79e53945
JB		 3285}
3286
cdd59983
CW		 3287static void intel_crtc_disable(struct drm_crtc *crtc)
3288{
3289 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3290 struct drm_device *dev = crtc->dev;
3291
3292 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3293
3294 if (crtc->fb) {
3295 mutex_lock(&dev->struct_mutex);
3296 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3297 mutex_unlock(&dev->struct_mutex);
3298 }
3299}
3300
7e7d76c3
JB		 3301/* Prepare for a mode set.
3302 *
3303 * Note we could be a lot smarter here. We need to figure out which outputs
3304 * will be enabled, which disabled (in short, how the config will changes)
3305 * and perform the minimum necessary steps to accomplish that, e.g. updating
3306 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3307 * panel fitting is in the proper state, etc.
3308 */
3309static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3310{
7e7d76c3 3311 i9xx_crtc_disable(crtc);
79e53945
JB		 3312}
3313
7e7d76c3 3314static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3315{
7e7d76c3 3316 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3317}
3318
3319static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3320{
7e7d76c3 3321 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3322}
3323
3324static void ironlake_crtc_commit(struct drm_crtc *crtc)
3325{
7e7d76c3 3326 ironlake_crtc_enable(crtc);
79e53945
JB		 3327}
3328
0206e353 3329void intel_encoder_prepare(struct drm_encoder *encoder)
79e53945
JB		 3330{
3331 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3332 /* lvds has its own version of prepare see intel_lvds_prepare */
3333 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3334}
3335
0206e353 3336void intel_encoder_commit(struct drm_encoder *encoder)
79e53945
JB		 3337{
3338 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3339 /* lvds has its own version of commit see intel_lvds_commit */
3340 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3341}
3342
ea5b213a
CW		 3343void intel_encoder_destroy(struct drm_encoder *encoder)
3344{
4ef69c7a 3345 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3346
ea5b213a
CW		 3347 drm_encoder_cleanup(encoder);
3348 kfree(intel_encoder);
3349}
3350
79e53945
JB		 3351static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3352 struct drm_display_mode *mode,
3353 struct drm_display_mode *adjusted_mode)
3354{
2c07245f 3355 struct drm_device *dev = crtc->dev;
89749350 3356
bad720ff 3357 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3358 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3359 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3360 return false;
2c07245f 3361 }
89749350
CW		 3362
3363 /* XXX some encoders set the crtcinfo, others don't.
3364 * Obviously we need some form of conflict resolution here...
3365 */
3366 if (adjusted_mode->crtc_htotal == 0)
3367 drm_mode_set_crtcinfo(adjusted_mode, 0);
3368
79e53945
JB		 3369 return true;
3370}
3371
e70236a8
JB		 3372static int i945_get_display_clock_speed(struct drm_device *dev)
3373{
3374 return 400000;
3375}
79e53945 3376
e70236a8 3377static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3378{
e70236a8
JB		 3379 return 333000;
3380}
79e53945 3381
e70236a8
JB		 3382static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3383{
3384 return 200000;
3385}
79e53945 3386
e70236a8
JB		 3387static int i915gm_get_display_clock_speed(struct drm_device *dev)
3388{
3389 u16 gcfgc = 0;
79e53945 3390
e70236a8
JB		 3391 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3392
3393 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3394 return 133000;
3395 else {
3396 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3397 case GC_DISPLAY_CLOCK_333_MHZ:
3398 return 333000;
3399 default:
3400 case GC_DISPLAY_CLOCK_190_200_MHZ:
3401 return 190000;
79e53945 3402 }
e70236a8
JB		 3403 }
3404}
3405
3406static int i865_get_display_clock_speed(struct drm_device *dev)
3407{
3408 return 266000;
3409}
3410
3411static int i855_get_display_clock_speed(struct drm_device *dev)
3412{
3413 u16 hpllcc = 0;
3414 /* Assume that the hardware is in the high speed state. This
3415 * should be the default.
3416 */
3417 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3418 case GC_CLOCK_133_200:
3419 case GC_CLOCK_100_200:
3420 return 200000;
3421 case GC_CLOCK_166_250:
3422 return 250000;
3423 case GC_CLOCK_100_133:
79e53945 3424 return 133000;
e70236a8 3425 }
79e53945 3426
e70236a8
JB		 3427 /* Shouldn't happen */
3428 return 0;
3429}
79e53945 3430
e70236a8
JB		 3431static int i830_get_display_clock_speed(struct drm_device *dev)
3432{
3433 return 133000;
79e53945
JB		 3434}
3435
2c07245f
ZW		 3436struct fdi_m_n {
3437 u32 tu;
3438 u32 gmch_m;
3439 u32 gmch_n;
3440 u32 link_m;
3441 u32 link_n;
3442};
3443
3444static void
3445fdi_reduce_ratio(u32 *num, u32 *den)
3446{
3447 while (*num > 0xffffff || *den > 0xffffff) {
3448 *num >>= 1;
3449 *den >>= 1;
3450 }
3451}
3452
2c07245f 3453static void
f2b115e6
AJ		 3454ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3455 int link_clock, struct fdi_m_n *m_n)
2c07245f 3456{
2c07245f
ZW		 3457 m_n->tu = 64; /* default size */
3458
22ed1113
CW		 3459 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3460 m_n->gmch_m = bits_per_pixel * pixel_clock;
3461 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3462 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3463
22ed1113
CW		 3464 m_n->link_m = pixel_clock;
3465 m_n->link_n = link_clock;
2c07245f
ZW		 3466 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3467}
3468
3469
7662c8bd
SL		 3470struct intel_watermark_params {
3471 unsigned long fifo_size;
3472 unsigned long max_wm;
3473 unsigned long default_wm;
3474 unsigned long guard_size;
3475 unsigned long cacheline_size;
3476};
3477
f2b115e6 3478/* Pineview has different values for various configs */
d210246a 3479static const struct intel_watermark_params pineview_display_wm = {
f2b115e6
AJ		 3480 PINEVIEW_DISPLAY_FIFO,
3481 PINEVIEW_MAX_WM,
3482 PINEVIEW_DFT_WM,
3483 PINEVIEW_GUARD_WM,
3484 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3485};
d210246a 3486static const struct intel_watermark_params pineview_display_hplloff_wm = {
f2b115e6
AJ		 3487 PINEVIEW_DISPLAY_FIFO,
3488 PINEVIEW_MAX_WM,
3489 PINEVIEW_DFT_HPLLOFF_WM,
3490 PINEVIEW_GUARD_WM,
3491 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3492};
d210246a 3493static const struct intel_watermark_params pineview_cursor_wm = {
f2b115e6
AJ		 3494 PINEVIEW_CURSOR_FIFO,
3495 PINEVIEW_CURSOR_MAX_WM,
3496 PINEVIEW_CURSOR_DFT_WM,
3497 PINEVIEW_CURSOR_GUARD_WM,
3498 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 3499};
d210246a 3500static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
f2b115e6
AJ		 3501 PINEVIEW_CURSOR_FIFO,
3502 PINEVIEW_CURSOR_MAX_WM,
3503 PINEVIEW_CURSOR_DFT_WM,
3504 PINEVIEW_CURSOR_GUARD_WM,
3505 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3506};
d210246a 3507static const struct intel_watermark_params g4x_wm_info = {
0e442c60
JB		 3508 G4X_FIFO_SIZE,
3509 G4X_MAX_WM,
3510 G4X_MAX_WM,
3511 2,
3512 G4X_FIFO_LINE_SIZE,
3513};
d210246a 3514static const struct intel_watermark_params g4x_cursor_wm_info = {
4fe5e611
ZY		 3515 I965_CURSOR_FIFO,
3516 I965_CURSOR_MAX_WM,
3517 I965_CURSOR_DFT_WM,
3518 2,
3519 G4X_FIFO_LINE_SIZE,
3520};
d210246a 3521static const struct intel_watermark_params i965_cursor_wm_info = {
4fe5e611
ZY		 3522 I965_CURSOR_FIFO,
3523 I965_CURSOR_MAX_WM,
3524 I965_CURSOR_DFT_WM,
3525 2,
3526 I915_FIFO_LINE_SIZE,
3527};
d210246a 3528static const struct intel_watermark_params i945_wm_info = {
dff33cfc 3529 I945_FIFO_SIZE,
7662c8bd
SL		 3530 I915_MAX_WM,
3531 1,
dff33cfc
JB		 3532 2,
3533 I915_FIFO_LINE_SIZE
7662c8bd 3534};
d210246a 3535static const struct intel_watermark_params i915_wm_info = {
dff33cfc 3536 I915_FIFO_SIZE,
7662c8bd
SL		 3537 I915_MAX_WM,
3538 1,
dff33cfc 3539 2,
7662c8bd
SL		 3540 I915_FIFO_LINE_SIZE
3541};
d210246a 3542static const struct intel_watermark_params i855_wm_info = {
7662c8bd
SL		 3543 I855GM_FIFO_SIZE,
3544 I915_MAX_WM,
3545 1,
dff33cfc 3546 2,
7662c8bd
SL		 3547 I830_FIFO_LINE_SIZE
3548};
d210246a 3549static const struct intel_watermark_params i830_wm_info = {
7662c8bd
SL		 3550 I830_FIFO_SIZE,
3551 I915_MAX_WM,
3552 1,
dff33cfc 3553 2,
7662c8bd
SL		 3554 I830_FIFO_LINE_SIZE
3555};
3556
d210246a 3557static const struct intel_watermark_params ironlake_display_wm_info = {
7f8a8569
ZW		 3558 ILK_DISPLAY_FIFO,
3559 ILK_DISPLAY_MAXWM,
3560 ILK_DISPLAY_DFTWM,
3561 2,
3562 ILK_FIFO_LINE_SIZE
3563};
d210246a 3564static const struct intel_watermark_params ironlake_cursor_wm_info = {
c936f44d
ZY		 3565 ILK_CURSOR_FIFO,
3566 ILK_CURSOR_MAXWM,
3567 ILK_CURSOR_DFTWM,
3568 2,
3569 ILK_FIFO_LINE_SIZE
3570};
d210246a 3571static const struct intel_watermark_params ironlake_display_srwm_info = {
7f8a8569
ZW		 3572 ILK_DISPLAY_SR_FIFO,
3573 ILK_DISPLAY_MAX_SRWM,
3574 ILK_DISPLAY_DFT_SRWM,
3575 2,
3576 ILK_FIFO_LINE_SIZE
3577};
d210246a 3578static const struct intel_watermark_params ironlake_cursor_srwm_info = {
7f8a8569
ZW		 3579 ILK_CURSOR_SR_FIFO,
3580 ILK_CURSOR_MAX_SRWM,
3581 ILK_CURSOR_DFT_SRWM,
3582 2,
3583 ILK_FIFO_LINE_SIZE
3584};
3585
d210246a 3586static const struct intel_watermark_params sandybridge_display_wm_info = {
1398261a
YL		 3587 SNB_DISPLAY_FIFO,
3588 SNB_DISPLAY_MAXWM,
3589 SNB_DISPLAY_DFTWM,
3590 2,
3591 SNB_FIFO_LINE_SIZE
3592};
d210246a 3593static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1398261a
YL		 3594 SNB_CURSOR_FIFO,
3595 SNB_CURSOR_MAXWM,
3596 SNB_CURSOR_DFTWM,
3597 2,
3598 SNB_FIFO_LINE_SIZE
3599};
d210246a 3600static const struct intel_watermark_params sandybridge_display_srwm_info = {
1398261a
YL		 3601 SNB_DISPLAY_SR_FIFO,
3602 SNB_DISPLAY_MAX_SRWM,
3603 SNB_DISPLAY_DFT_SRWM,
3604 2,
3605 SNB_FIFO_LINE_SIZE
3606};
d210246a 3607static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1398261a
YL		 3608 SNB_CURSOR_SR_FIFO,
3609 SNB_CURSOR_MAX_SRWM,
3610 SNB_CURSOR_DFT_SRWM,
3611 2,
3612 SNB_FIFO_LINE_SIZE
3613};
3614
3615
dff33cfc
JB		 3616/**
3617 * intel_calculate_wm - calculate watermark level
3618 * @clock_in_khz: pixel clock
3619 * @wm: chip FIFO params
3620 * @pixel_size: display pixel size
3621 * @latency_ns: memory latency for the platform
3622 *
3623 * Calculate the watermark level (the level at which the display plane will
3624 * start fetching from memory again). Each chip has a different display
3625 * FIFO size and allocation, so the caller needs to figure that out and pass
3626 * in the correct intel_watermark_params structure.
3627 *
3628 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3629 * on the pixel size. When it reaches the watermark level, it'll start
3630 * fetching FIFO line sized based chunks from memory until the FIFO fills
3631 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3632 * will occur, and a display engine hang could result.
3633 */
7662c8bd 3634static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
d210246a
CW		 3635 const struct intel_watermark_params *wm,
3636 int fifo_size,
7662c8bd
SL		 3637 int pixel_size,
3638 unsigned long latency_ns)
3639{
390c4dd4 3640 long entries_required, wm_size;
dff33cfc 3641
d660467c
JB		 3642 /*
3643 * Note: we need to make sure we don't overflow for various clock &
3644 * latency values.
3645 * clocks go from a few thousand to several hundred thousand.
3646 * latency is usually a few thousand
3647 */
3648 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3649 1000;
8de9b311 3650 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 3651
bbb0aef5 3652 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
dff33cfc 3653
d210246a 3654 wm_size = fifo_size - (entries_required + wm->guard_size);
dff33cfc 3655
bbb0aef5 3656 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
7662c8bd 3657
390c4dd4
JB		 3658 /* Don't promote wm_size to unsigned... */
3659 if (wm_size > (long)wm->max_wm)
7662c8bd 3660 wm_size = wm->max_wm;
c3add4b6 3661 if (wm_size <= 0)
7662c8bd
SL		 3662 wm_size = wm->default_wm;
3663 return wm_size;
3664}
3665
3666struct cxsr_latency {
3667 int is_desktop;
95534263 3668 int is_ddr3;
7662c8bd
SL		 3669 unsigned long fsb_freq;
3670 unsigned long mem_freq;
3671 unsigned long display_sr;
3672 unsigned long display_hpll_disable;
3673 unsigned long cursor_sr;
3674 unsigned long cursor_hpll_disable;
3675};
3676
403c89ff 3677static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP		 3678 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3679 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3680 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3681 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3682 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3683
3684 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3685 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3686 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3687 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3688 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3689
3690 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3691 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3692 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3693 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3694 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3695
3696 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3697 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3698 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3699 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3700 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3701
3702 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3703 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3704 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3705 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3706 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3707
3708 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3709 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3710 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3711 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3712 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL		 3713};
3714
403c89ff
CW		 3715static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3716 int is_ddr3,
3717 int fsb,
3718 int mem)
7662c8bd 3719{
403c89ff 3720 const struct cxsr_latency *latency;
7662c8bd 3721 int i;
7662c8bd
SL		 3722
3723 if (fsb == 0 || mem == 0)
3724 return NULL;
3725
3726 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3727 latency = &cxsr_latency_table[i];
3728 if (is_desktop == latency->is_desktop &&
95534263 3729 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR		 3730 fsb == latency->fsb_freq && mem == latency->mem_freq)
3731 return latency;
7662c8bd 3732 }
decbbcda 3733
28c97730 3734 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR		 3735
3736 return NULL;
7662c8bd
SL		 3737}
3738
f2b115e6 3739static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL		 3740{
3741 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL		 3742
3743 /* deactivate cxsr */
3e33d94d 3744 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL		 3745}
3746
bcc24fb4
JB		 3747/*
3748 * Latency for FIFO fetches is dependent on several factors:
3749 * - memory configuration (speed, channels)
3750 * - chipset
3751 * - current MCH state
3752 * It can be fairly high in some situations, so here we assume a fairly
3753 * pessimal value. It's a tradeoff between extra memory fetches (if we
3754 * set this value too high, the FIFO will fetch frequently to stay full)
3755 * and power consumption (set it too low to save power and we might see
3756 * FIFO underruns and display "flicker").
3757 *
3758 * A value of 5us seems to be a good balance; safe for very low end
3759 * platforms but not overly aggressive on lower latency configs.
3760 */
69e302a9 3761static const int latency_ns = 5000;
7662c8bd 3762
e70236a8 3763static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB		 3764{
3765 struct drm_i915_private *dev_priv = dev->dev_private;
3766 uint32_t dsparb = I915_READ(DSPARB);
3767 int size;
3768
8de9b311
CW		 3769 size = dsparb & 0x7f;
3770 if (plane)
3771 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 3772
28c97730 3773 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3774 plane ? "B" : "A", size);
dff33cfc
JB		 3775
3776 return size;
3777}
7662c8bd 3778
e70236a8
JB		 3779static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3780{
3781 struct drm_i915_private *dev_priv = dev->dev_private;
3782 uint32_t dsparb = I915_READ(DSPARB);
3783 int size;
3784
8de9b311
CW		 3785 size = dsparb & 0x1ff;
3786 if (plane)
3787 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 3788 size >>= 1; /* Convert to cachelines */
dff33cfc 3789
28c97730 3790 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3791 plane ? "B" : "A", size);
dff33cfc
JB		 3792
3793 return size;
3794}
7662c8bd 3795
e70236a8
JB		 3796static int i845_get_fifo_size(struct drm_device *dev, int plane)
3797{
3798 struct drm_i915_private *dev_priv = dev->dev_private;
3799 uint32_t dsparb = I915_READ(DSPARB);
3800 int size;
3801
3802 size = dsparb & 0x7f;
3803 size >>= 2; /* Convert to cachelines */
3804
28c97730 3805 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW		 3806 plane ? "B" : "A",
3807 size);
e70236a8
JB		 3808
3809 return size;
3810}
3811
3812static int i830_get_fifo_size(struct drm_device *dev, int plane)
3813{
3814 struct drm_i915_private *dev_priv = dev->dev_private;
3815 uint32_t dsparb = I915_READ(DSPARB);
3816 int size;
3817
3818 size = dsparb & 0x7f;
3819 size >>= 1; /* Convert to cachelines */
3820
28c97730 3821 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3822 plane ? "B" : "A", size);
e70236a8
JB		 3823
3824 return size;
3825}
3826
d210246a
CW		 3827static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3828{
3829 struct drm_crtc *crtc, *enabled = NULL;
3830
3831 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3832 if (crtc->enabled && crtc->fb) {
3833 if (enabled)
3834 return NULL;
3835 enabled = crtc;
3836 }
3837 }
3838
3839 return enabled;
3840}
3841
3842static void pineview_update_wm(struct drm_device *dev)
d4294342
ZY		 3843{
3844 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3845 struct drm_crtc *crtc;
403c89ff 3846 const struct cxsr_latency *latency;
d4294342
ZY		 3847 u32 reg;
3848 unsigned long wm;
d4294342 3849
403c89ff 3850 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 3851 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY		 3852 if (!latency) {
3853 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3854 pineview_disable_cxsr(dev);
3855 return;
3856 }
3857
d210246a
CW		 3858 crtc = single_enabled_crtc(dev);
3859 if (crtc) {
3860 int clock = crtc->mode.clock;
3861 int pixel_size = crtc->fb->bits_per_pixel / 8;
d4294342
ZY		 3862
3863 /* Display SR */
d210246a
CW		 3864 wm = intel_calculate_wm(clock, &pineview_display_wm,
3865 pineview_display_wm.fifo_size,
d4294342
ZY		 3866 pixel_size, latency->display_sr);
3867 reg = I915_READ(DSPFW1);
3868 reg &= ~DSPFW_SR_MASK;
3869 reg |= wm << DSPFW_SR_SHIFT;
3870 I915_WRITE(DSPFW1, reg);
3871 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3872
3873 /* cursor SR */
d210246a
CW		 3874 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3875 pineview_display_wm.fifo_size,
d4294342
ZY		 3876 pixel_size, latency->cursor_sr);
3877 reg = I915_READ(DSPFW3);
3878 reg &= ~DSPFW_CURSOR_SR_MASK;
3879 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3880 I915_WRITE(DSPFW3, reg);
3881
3882 /* Display HPLL off SR */
d210246a
CW		 3883 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3884 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3885 pixel_size, latency->display_hpll_disable);
3886 reg = I915_READ(DSPFW3);
3887 reg &= ~DSPFW_HPLL_SR_MASK;
3888 reg |= wm & DSPFW_HPLL_SR_MASK;
3889 I915_WRITE(DSPFW3, reg);
3890
3891 /* cursor HPLL off SR */
d210246a
CW		 3892 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3893 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3894 pixel_size, latency->cursor_hpll_disable);
3895 reg = I915_READ(DSPFW3);
3896 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3897 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3898 I915_WRITE(DSPFW3, reg);
3899 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3900
3901 /* activate cxsr */
3e33d94d
CW		 3902 I915_WRITE(DSPFW3,
3903 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY		 3904 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3905 } else {
3906 pineview_disable_cxsr(dev);
3907 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3908 }
3909}
3910
417ae147
CW		 3911static bool g4x_compute_wm0(struct drm_device *dev,
3912 int plane,
3913 const struct intel_watermark_params *display,
3914 int display_latency_ns,
3915 const struct intel_watermark_params *cursor,
3916 int cursor_latency_ns,
3917 int *plane_wm,
3918 int *cursor_wm)
3919{
3920 struct drm_crtc *crtc;
3921 int htotal, hdisplay, clock, pixel_size;
3922 int line_time_us, line_count;
3923 int entries, tlb_miss;
3924
3925 crtc = intel_get_crtc_for_plane(dev, plane);
5c72d064
CW		 3926 if (crtc->fb == NULL || !crtc->enabled) {
3927 *cursor_wm = cursor->guard_size;
3928 *plane_wm = display->guard_size;
417ae147 3929 return false;
5c72d064 3930 }
417ae147
CW		 3931
3932 htotal = crtc->mode.htotal;
3933 hdisplay = crtc->mode.hdisplay;
3934 clock = crtc->mode.clock;
3935 pixel_size = crtc->fb->bits_per_pixel / 8;
3936
3937 /* Use the small buffer method to calculate plane watermark */
3938 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3939 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3940 if (tlb_miss > 0)
3941 entries += tlb_miss;
3942 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3943 *plane_wm = entries + display->guard_size;
3944 if (*plane_wm > (int)display->max_wm)
3945 *plane_wm = display->max_wm;
3946
3947 /* Use the large buffer method to calculate cursor watermark */
3948 line_time_us = ((htotal * 1000) / clock);
3949 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3950 entries = line_count * 64 * pixel_size;
3951 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3952 if (tlb_miss > 0)
3953 entries += tlb_miss;
3954 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3955 *cursor_wm = entries + cursor->guard_size;
3956 if (*cursor_wm > (int)cursor->max_wm)
3957 *cursor_wm = (int)cursor->max_wm;
3958
3959 return true;
3960}
3961
3962/*
3963 * Check the wm result.
3964 *
3965 * If any calculated watermark values is larger than the maximum value that
3966 * can be programmed into the associated watermark register, that watermark
3967 * must be disabled.
3968 */
3969static bool g4x_check_srwm(struct drm_device *dev,
3970 int display_wm, int cursor_wm,
3971 const struct intel_watermark_params *display,
3972 const struct intel_watermark_params *cursor)
652c393a 3973{
417ae147
CW		 3974 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
3975 display_wm, cursor_wm);
652c393a 3976
417ae147 3977 if (display_wm > display->max_wm) {
bbb0aef5 3978 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 3979 display_wm, display->max_wm);
3980 return false;
3981 }
0e442c60 3982
417ae147 3983 if (cursor_wm > cursor->max_wm) {
bbb0aef5 3984 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 3985 cursor_wm, cursor->max_wm);
3986 return false;
3987 }
0e442c60 3988
417ae147
CW		 3989 if (!(display_wm || cursor_wm)) {
3990 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
3991 return false;
3992 }
0e442c60 3993
417ae147
CW		 3994 return true;
3995}
0e442c60 3996
417ae147 3997static bool g4x_compute_srwm(struct drm_device *dev,
d210246a
CW		 3998 int plane,
3999 int latency_ns,
417ae147
CW		 4000 const struct intel_watermark_params *display,
4001 const struct intel_watermark_params *cursor,
4002 int *display_wm, int *cursor_wm)
4003{
d210246a
CW		 4004 struct drm_crtc *crtc;
4005 int hdisplay, htotal, pixel_size, clock;
417ae147
CW		 4006 unsigned long line_time_us;
4007 int line_count, line_size;
4008 int small, large;
4009 int entries;
0e442c60 4010
417ae147
CW		 4011 if (!latency_ns) {
4012 *display_wm = *cursor_wm = 0;
4013 return false;
4014 }
0e442c60 4015
d210246a
CW		 4016 crtc = intel_get_crtc_for_plane(dev, plane);
4017 hdisplay = crtc->mode.hdisplay;
4018 htotal = crtc->mode.htotal;
4019 clock = crtc->mode.clock;
4020 pixel_size = crtc->fb->bits_per_pixel / 8;
4021
417ae147
CW		 4022 line_time_us = (htotal * 1000) / clock;
4023 line_count = (latency_ns / line_time_us + 1000) / 1000;
4024 line_size = hdisplay * pixel_size;
0e442c60 4025
417ae147
CW		 4026 /* Use the minimum of the small and large buffer method for primary */
4027 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4028 large = line_count * line_size;
0e442c60 4029
417ae147
CW		 4030 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4031 *display_wm = entries + display->guard_size;
4fe5e611 4032
417ae147
CW		 4033 /* calculate the self-refresh watermark for display cursor */
4034 entries = line_count * pixel_size * 64;
4035 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4036 *cursor_wm = entries + cursor->guard_size;
4fe5e611 4037
417ae147
CW		 4038 return g4x_check_srwm(dev,
4039 *display_wm, *cursor_wm,
4040 display, cursor);
4041}
4fe5e611 4042
7ccb4a53 4043#define single_plane_enabled(mask) is_power_of_2(mask)
d210246a
CW		 4044
4045static void g4x_update_wm(struct drm_device *dev)
417ae147
CW		 4046{
4047 static const int sr_latency_ns = 12000;
4048 struct drm_i915_private *dev_priv = dev->dev_private;
4049 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
d210246a
CW		 4050 int plane_sr, cursor_sr;
4051 unsigned int enabled = 0;
417ae147
CW		 4052
4053 if (g4x_compute_wm0(dev, 0,
4054 &g4x_wm_info, latency_ns,
4055 &g4x_cursor_wm_info, latency_ns,
4056 &planea_wm, &cursora_wm))
d210246a 4057 enabled |= 1;
417ae147
CW		 4058
4059 if (g4x_compute_wm0(dev, 1,
4060 &g4x_wm_info, latency_ns,
4061 &g4x_cursor_wm_info, latency_ns,
4062 &planeb_wm, &cursorb_wm))
d210246a 4063 enabled |= 2;
417ae147
CW		 4064
4065 plane_sr = cursor_sr = 0;
d210246a
CW		 4066 if (single_plane_enabled(enabled) &&
4067 g4x_compute_srwm(dev, ffs(enabled) - 1,
4068 sr_latency_ns,
417ae147
CW		 4069 &g4x_wm_info,
4070 &g4x_cursor_wm_info,
4071 &plane_sr, &cursor_sr))
0e442c60 4072 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
417ae147
CW		 4073 else
4074 I915_WRITE(FW_BLC_SELF,
4075 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
0e442c60 4076
308977ac
CW		 4077 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4078 planea_wm, cursora_wm,
4079 planeb_wm, cursorb_wm,
4080 plane_sr, cursor_sr);
0e442c60 4081
417ae147
CW		 4082 I915_WRITE(DSPFW1,
4083 (plane_sr << DSPFW_SR_SHIFT) |
0e442c60 4084 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
417ae147
CW		 4085 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4086 planea_wm);
4087 I915_WRITE(DSPFW2,
4088 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
0e442c60
JB		 4089 (cursora_wm << DSPFW_CURSORA_SHIFT));
4090 /* HPLL off in SR has some issues on G4x... disable it */
417ae147
CW		 4091 I915_WRITE(DSPFW3,
4092 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
0e442c60 4093 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB		 4094}
4095
d210246a 4096static void i965_update_wm(struct drm_device *dev)
7662c8bd
SL		 4097{
4098 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4099 struct drm_crtc *crtc;
4100 int srwm = 1;
4fe5e611 4101 int cursor_sr = 16;
1dc7546d
JB		 4102
4103 /* Calc sr entries for one plane configs */
d210246a
CW		 4104 crtc = single_enabled_crtc(dev);
4105 if (crtc) {
1dc7546d 4106 /* self-refresh has much higher latency */
69e302a9 4107 static const int sr_latency_ns = 12000;
d210246a
CW		 4108 int clock = crtc->mode.clock;
4109 int htotal = crtc->mode.htotal;
4110 int hdisplay = crtc->mode.hdisplay;
4111 int pixel_size = crtc->fb->bits_per_pixel / 8;
4112 unsigned long line_time_us;
4113 int entries;
1dc7546d 4114
d210246a 4115 line_time_us = ((htotal * 1000) / clock);
1dc7546d
JB		 4116
4117 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4118 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4119 pixel_size * hdisplay;
4120 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
d210246a 4121 srwm = I965_FIFO_SIZE - entries;
1dc7546d
JB		 4122 if (srwm < 0)
4123 srwm = 1;
1b07e04e 4124 srwm &= 0x1ff;
308977ac
CW		 4125 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4126 entries, srwm);
4fe5e611 4127
d210246a 4128 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 4129 pixel_size * 64;
d210246a 4130 entries = DIV_ROUND_UP(entries,
8de9b311 4131 i965_cursor_wm_info.cacheline_size);
4fe5e611 4132 cursor_sr = i965_cursor_wm_info.fifo_size -
d210246a 4133 (entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY		 4134
4135 if (cursor_sr > i965_cursor_wm_info.max_wm)
4136 cursor_sr = i965_cursor_wm_info.max_wm;
4137
4138 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4139 "cursor %d\n", srwm, cursor_sr);
4140
a6c45cf0 4141 if (IS_CRESTLINE(dev))
adcdbc66 4142 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ		 4143 } else {
4144 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 4145 if (IS_CRESTLINE(dev))
adcdbc66
JB		 4146 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4147 & ~FW_BLC_SELF_EN);
1dc7546d 4148 }
7662c8bd 4149
1dc7546d
JB		 4150 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4151 srwm);
7662c8bd
SL		 4152
4153 /* 965 has limitations... */
417ae147
CW		 4154 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4155 (8 << 16) | (8 << 8) | (8 << 0));
7662c8bd 4156 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY		 4157 /* update cursor SR watermark */
4158 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL		 4159}
4160
d210246a 4161static void i9xx_update_wm(struct drm_device *dev)
7662c8bd
SL		 4162{
4163 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 4164 const struct intel_watermark_params *wm_info;
dff33cfc
JB		 4165 uint32_t fwater_lo;
4166 uint32_t fwater_hi;
d210246a
CW		 4167 int cwm, srwm = 1;
4168 int fifo_size;
dff33cfc 4169 int planea_wm, planeb_wm;
d210246a 4170 struct drm_crtc *crtc, *enabled = NULL;
7662c8bd 4171
72557b4f 4172 if (IS_I945GM(dev))
d210246a 4173 wm_info = &i945_wm_info;
a6c45cf0 4174 else if (!IS_GEN2(dev))
d210246a 4175 wm_info = &i915_wm_info;
7662c8bd 4176 else
d210246a
CW		 4177 wm_info = &i855_wm_info;
4178
4179 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4180 crtc = intel_get_crtc_for_plane(dev, 0);
4181 if (crtc->enabled && crtc->fb) {
4182 planea_wm = intel_calculate_wm(crtc->mode.clock,
4183 wm_info, fifo_size,
4184 crtc->fb->bits_per_pixel / 8,
4185 latency_ns);
4186 enabled = crtc;
4187 } else
4188 planea_wm = fifo_size - wm_info->guard_size;
4189
4190 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4191 crtc = intel_get_crtc_for_plane(dev, 1);
4192 if (crtc->enabled && crtc->fb) {
4193 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4194 wm_info, fifo_size,
4195 crtc->fb->bits_per_pixel / 8,
4196 latency_ns);
4197 if (enabled == NULL)
4198 enabled = crtc;
4199 else
4200 enabled = NULL;
4201 } else
4202 planeb_wm = fifo_size - wm_info->guard_size;
7662c8bd 4203
28c97730 4204 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL		 4205
4206 /*
4207 * Overlay gets an aggressive default since video jitter is bad.
4208 */
4209 cwm = 2;
4210
18b2190c
AL		 4211 /* Play safe and disable self-refresh before adjusting watermarks. */
4212 if (IS_I945G(dev) || IS_I945GM(dev))
4213 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4214 else if (IS_I915GM(dev))
4215 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4216
dff33cfc 4217 /* Calc sr entries for one plane configs */
d210246a 4218 if (HAS_FW_BLC(dev) && enabled) {
dff33cfc 4219 /* self-refresh has much higher latency */
69e302a9 4220 static const int sr_latency_ns = 6000;
d210246a
CW		 4221 int clock = enabled->mode.clock;
4222 int htotal = enabled->mode.htotal;
4223 int hdisplay = enabled->mode.hdisplay;
4224 int pixel_size = enabled->fb->bits_per_pixel / 8;
4225 unsigned long line_time_us;
4226 int entries;
dff33cfc 4227
d210246a 4228 line_time_us = (htotal * 1000) / clock;
dff33cfc
JB		 4229
4230 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4231 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4232 pixel_size * hdisplay;
4233 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4234 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4235 srwm = wm_info->fifo_size - entries;
dff33cfc
JB		 4236 if (srwm < 0)
4237 srwm = 1;
ee980b80
LP		 4238
4239 if (IS_I945G(dev) || IS_I945GM(dev))
18b2190c
AL		 4240 I915_WRITE(FW_BLC_SELF,
4241 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4242 else if (IS_I915GM(dev))
ee980b80 4243 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
7662c8bd
SL		 4244 }
4245
28c97730 4246 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 4247 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 4248
dff33cfc
JB		 4249 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4250 fwater_hi = (cwm & 0x1f);
4251
4252 /* Set request length to 8 cachelines per fetch */
4253 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4254 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL		 4255
4256 I915_WRITE(FW_BLC, fwater_lo);
4257 I915_WRITE(FW_BLC2, fwater_hi);
18b2190c 4258
d210246a
CW		 4259 if (HAS_FW_BLC(dev)) {
4260 if (enabled) {
4261 if (IS_I945G(dev) || IS_I945GM(dev))
4262 I915_WRITE(FW_BLC_SELF,
4263 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4264 else if (IS_I915GM(dev))
4265 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4266 DRM_DEBUG_KMS("memory self refresh enabled\n");
4267 } else
4268 DRM_DEBUG_KMS("memory self refresh disabled\n");
4269 }
7662c8bd
SL		 4270}
4271
d210246a 4272static void i830_update_wm(struct drm_device *dev)
7662c8bd
SL		 4273{
4274 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4275 struct drm_crtc *crtc;
4276 uint32_t fwater_lo;
dff33cfc 4277 int planea_wm;
7662c8bd 4278
d210246a
CW		 4279 crtc = single_enabled_crtc(dev);
4280 if (crtc == NULL)
4281 return;
7662c8bd 4282
d210246a
CW		 4283 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4284 dev_priv->display.get_fifo_size(dev, 0),
4285 crtc->fb->bits_per_pixel / 8,
4286 latency_ns);
4287 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
f3601326
JB		 4288 fwater_lo |= (3<<8) | planea_wm;
4289
28c97730 4290 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL		 4291
4292 I915_WRITE(FW_BLC, fwater_lo);
4293}
4294
7f8a8569 4295#define ILK_LP0_PLANE_LATENCY 700
c936f44d 4296#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 4297
1398261a
YL		 4298/*
4299 * Check the wm result.
4300 *
4301 * If any calculated watermark values is larger than the maximum value that
4302 * can be programmed into the associated watermark register, that watermark
4303 * must be disabled.
1398261a 4304 */
b79d4990
JB		 4305static bool ironlake_check_srwm(struct drm_device *dev, int level,
4306 int fbc_wm, int display_wm, int cursor_wm,
4307 const struct intel_watermark_params *display,
4308 const struct intel_watermark_params *cursor)
1398261a
YL		 4309{
4310 struct drm_i915_private *dev_priv = dev->dev_private;
4311
4312 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4313 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4314
4315 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4316 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4317 fbc_wm, SNB_FBC_MAX_SRWM, level);
1398261a
YL		 4318
4319 /* fbc has it's own way to disable FBC WM */
4320 I915_WRITE(DISP_ARB_CTL,
4321 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4322 return false;
4323 }
4324
b79d4990 4325 if (display_wm > display->max_wm) {
1398261a 4326 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4327 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1398261a
YL		 4328 return false;
4329 }
4330
b79d4990 4331 if (cursor_wm > cursor->max_wm) {
1398261a 4332 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4333 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1398261a
YL		 4334 return false;
4335 }
4336
4337 if (!(fbc_wm || display_wm || cursor_wm)) {
4338 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4339 return false;
4340 }
4341
4342 return true;
4343}
4344
4345/*
4346 * Compute watermark values of WM[1-3],
4347 */
d210246a
CW		 4348static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4349 int latency_ns,
b79d4990
JB		 4350 const struct intel_watermark_params *display,
4351 const struct intel_watermark_params *cursor,
4352 int *fbc_wm, int *display_wm, int *cursor_wm)
1398261a 4353{
d210246a 4354 struct drm_crtc *crtc;
1398261a 4355 unsigned long line_time_us;
d210246a 4356 int hdisplay, htotal, pixel_size, clock;
b79d4990 4357 int line_count, line_size;
1398261a
YL		 4358 int small, large;
4359 int entries;
1398261a
YL		 4360
4361 if (!latency_ns) {
4362 *fbc_wm = *display_wm = *cursor_wm = 0;
4363 return false;
4364 }
4365
d210246a
CW		 4366 crtc = intel_get_crtc_for_plane(dev, plane);
4367 hdisplay = crtc->mode.hdisplay;
4368 htotal = crtc->mode.htotal;
4369 clock = crtc->mode.clock;
4370 pixel_size = crtc->fb->bits_per_pixel / 8;
4371
1398261a
YL		 4372 line_time_us = (htotal * 1000) / clock;
4373 line_count = (latency_ns / line_time_us + 1000) / 1000;
4374 line_size = hdisplay * pixel_size;
4375
4376 /* Use the minimum of the small and large buffer method for primary */
4377 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4378 large = line_count * line_size;
4379
b79d4990
JB		 4380 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4381 *display_wm = entries + display->guard_size;
1398261a
YL		 4382
4383 /*
b79d4990 4384 * Spec says:
1398261a
YL		 4385 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4386 */
4387 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4388
4389 /* calculate the self-refresh watermark for display cursor */
4390 entries = line_count * pixel_size * 64;
b79d4990
JB		 4391 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4392 *cursor_wm = entries + cursor->guard_size;
1398261a 4393
b79d4990
JB		 4394 return ironlake_check_srwm(dev, level,
4395 *fbc_wm, *display_wm, *cursor_wm,
4396 display, cursor);
4397}
4398
d210246a 4399static void ironlake_update_wm(struct drm_device *dev)
b79d4990
JB		 4400{
4401 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4402 int fbc_wm, plane_wm, cursor_wm;
4403 unsigned int enabled;
b79d4990
JB		 4404
4405 enabled = 0;
9f405100
CW		 4406 if (g4x_compute_wm0(dev, 0,
4407 &ironlake_display_wm_info,
4408 ILK_LP0_PLANE_LATENCY,
4409 &ironlake_cursor_wm_info,
4410 ILK_LP0_CURSOR_LATENCY,
4411 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4412 I915_WRITE(WM0_PIPEA_ILK,
4413 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4414 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4415 " plane %d, " "cursor: %d\n",
4416 plane_wm, cursor_wm);
d210246a 4417 enabled |= 1;
b79d4990
JB		 4418 }
4419
9f405100
CW		 4420 if (g4x_compute_wm0(dev, 1,
4421 &ironlake_display_wm_info,
4422 ILK_LP0_PLANE_LATENCY,
4423 &ironlake_cursor_wm_info,
4424 ILK_LP0_CURSOR_LATENCY,
4425 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4426 I915_WRITE(WM0_PIPEB_ILK,
4427 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4428 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4429 " plane %d, cursor: %d\n",
4430 plane_wm, cursor_wm);
d210246a 4431 enabled |= 2;
b79d4990
JB		 4432 }
4433
4434 /*
4435 * Calculate and update the self-refresh watermark only when one
4436 * display plane is used.
4437 */
4438 I915_WRITE(WM3_LP_ILK, 0);
4439 I915_WRITE(WM2_LP_ILK, 0);
4440 I915_WRITE(WM1_LP_ILK, 0);
4441
d210246a 4442 if (!single_plane_enabled(enabled))
b79d4990 4443 return;
d210246a 4444 enabled = ffs(enabled) - 1;
b79d4990
JB		 4445
4446 /* WM1 */
d210246a
CW		 4447 if (!ironlake_compute_srwm(dev, 1, enabled,
4448 ILK_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4449 &ironlake_display_srwm_info,
4450 &ironlake_cursor_srwm_info,
4451 &fbc_wm, &plane_wm, &cursor_wm))
4452 return;
4453
4454 I915_WRITE(WM1_LP_ILK,
4455 WM1_LP_SR_EN |
4456 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4457 (fbc_wm << WM1_LP_FBC_SHIFT) |
4458 (plane_wm << WM1_LP_SR_SHIFT) |
4459 cursor_wm);
4460
4461 /* WM2 */
d210246a
CW		 4462 if (!ironlake_compute_srwm(dev, 2, enabled,
4463 ILK_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4464 &ironlake_display_srwm_info,
4465 &ironlake_cursor_srwm_info,
4466 &fbc_wm, &plane_wm, &cursor_wm))
4467 return;
4468
4469 I915_WRITE(WM2_LP_ILK,
4470 WM2_LP_EN |
4471 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4472 (fbc_wm << WM1_LP_FBC_SHIFT) |
4473 (plane_wm << WM1_LP_SR_SHIFT) |
4474 cursor_wm);
4475
4476 /*
4477 * WM3 is unsupported on ILK, probably because we don't have latency
4478 * data for that power state
4479 */
1398261a
YL		 4480}
4481
d210246a 4482static void sandybridge_update_wm(struct drm_device *dev)
1398261a
YL		 4483{
4484 struct drm_i915_private *dev_priv = dev->dev_private;
a0fa62d3 4485 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
d210246a
CW		 4486 int fbc_wm, plane_wm, cursor_wm;
4487 unsigned int enabled;
1398261a
YL		 4488
4489 enabled = 0;
9f405100
CW		 4490 if (g4x_compute_wm0(dev, 0,
4491 &sandybridge_display_wm_info, latency,
4492 &sandybridge_cursor_wm_info, latency,
4493 &plane_wm, &cursor_wm)) {
1398261a
YL		 4494 I915_WRITE(WM0_PIPEA_ILK,
4495 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4496 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4497 " plane %d, " "cursor: %d\n",
4498 plane_wm, cursor_wm);
d210246a 4499 enabled |= 1;
1398261a
YL		 4500 }
4501
9f405100
CW		 4502 if (g4x_compute_wm0(dev, 1,
4503 &sandybridge_display_wm_info, latency,
4504 &sandybridge_cursor_wm_info, latency,
4505 &plane_wm, &cursor_wm)) {
1398261a
YL		 4506 I915_WRITE(WM0_PIPEB_ILK,
4507 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4508 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4509 " plane %d, cursor: %d\n",
4510 plane_wm, cursor_wm);
d210246a 4511 enabled |= 2;
1398261a
YL		 4512 }
4513
4514 /*
4515 * Calculate and update the self-refresh watermark only when one
4516 * display plane is used.
4517 *
4518 * SNB support 3 levels of watermark.
4519 *
4520 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4521 * and disabled in the descending order
4522 *
4523 */
4524 I915_WRITE(WM3_LP_ILK, 0);
4525 I915_WRITE(WM2_LP_ILK, 0);
4526 I915_WRITE(WM1_LP_ILK, 0);
4527
d210246a 4528 if (!single_plane_enabled(enabled))
1398261a 4529 return;
d210246a 4530 enabled = ffs(enabled) - 1;
1398261a
YL		 4531
4532 /* WM1 */
d210246a
CW		 4533 if (!ironlake_compute_srwm(dev, 1, enabled,
4534 SNB_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4535 &sandybridge_display_srwm_info,
4536 &sandybridge_cursor_srwm_info,
4537 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4538 return;
4539
4540 I915_WRITE(WM1_LP_ILK,
4541 WM1_LP_SR_EN |
4542 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4543 (fbc_wm << WM1_LP_FBC_SHIFT) |
4544 (plane_wm << WM1_LP_SR_SHIFT) |
4545 cursor_wm);
4546
4547 /* WM2 */
d210246a
CW		 4548 if (!ironlake_compute_srwm(dev, 2, enabled,
4549 SNB_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4550 &sandybridge_display_srwm_info,
4551 &sandybridge_cursor_srwm_info,
4552 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4553 return;
4554
4555 I915_WRITE(WM2_LP_ILK,
4556 WM2_LP_EN |
4557 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4558 (fbc_wm << WM1_LP_FBC_SHIFT) |
4559 (plane_wm << WM1_LP_SR_SHIFT) |
4560 cursor_wm);
4561
4562 /* WM3 */
d210246a
CW		 4563 if (!ironlake_compute_srwm(dev, 3, enabled,
4564 SNB_READ_WM3_LATENCY() * 500,
b79d4990
JB		 4565 &sandybridge_display_srwm_info,
4566 &sandybridge_cursor_srwm_info,
4567 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4568 return;
4569
4570 I915_WRITE(WM3_LP_ILK,
4571 WM3_LP_EN |
4572 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4573 (fbc_wm << WM1_LP_FBC_SHIFT) |
4574 (plane_wm << WM1_LP_SR_SHIFT) |
4575 cursor_wm);
4576}
4577
7662c8bd
SL		 4578/**
4579 * intel_update_watermarks - update FIFO watermark values based on current modes
4580 *
4581 * Calculate watermark values for the various WM regs based on current mode
4582 * and plane configuration.
4583 *
4584 * There are several cases to deal with here:
4585 * - normal (i.e. non-self-refresh)
4586 * - self-refresh (SR) mode
4587 * - lines are large relative to FIFO size (buffer can hold up to 2)
4588 * - lines are small relative to FIFO size (buffer can hold more than 2
4589 * lines), so need to account for TLB latency
4590 *
4591 * The normal calculation is:
4592 * watermark = dotclock * bytes per pixel * latency
4593 * where latency is platform & configuration dependent (we assume pessimal
4594 * values here).
4595 *
4596 * The SR calculation is:
4597 * watermark = (trunc(latency/line time)+1) * surface width *
4598 * bytes per pixel
4599 * where
4600 * line time = htotal / dotclock
fa143215 4601 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL		 4602 * and latency is assumed to be high, as above.
4603 *
4604 * The final value programmed to the register should always be rounded up,
4605 * and include an extra 2 entries to account for clock crossings.
4606 *
4607 * We don't use the sprite, so we can ignore that. And on Crestline we have
4608 * to set the non-SR watermarks to 8.
5eddb70b 4609 */
7662c8bd
SL		 4610static void intel_update_watermarks(struct drm_device *dev)
4611{
e70236a8 4612 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 4613
d210246a
CW		 4614 if (dev_priv->display.update_wm)
4615 dev_priv->display.update_wm(dev);
7662c8bd
SL		 4616}
4617
a7615030
CW		 4618static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4619{
72bbe58c
KP		 4620 if (i915_panel_use_ssc >= 0)
4621 return i915_panel_use_ssc != 0;
4622 return dev_priv->lvds_use_ssc
435793df 4623 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4624}
4625
5a354204
JB		 4626/**
4627 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4628 * @crtc: CRTC structure
4629 *
4630 * A pipe may be connected to one or more outputs. Based on the depth of the
4631 * attached framebuffer, choose a good color depth to use on the pipe.
4632 *
4633 * If possible, match the pipe depth to the fb depth. In some cases, this
4634 * isn't ideal, because the connected output supports a lesser or restricted
4635 * set of depths. Resolve that here:
4636 * LVDS typically supports only 6bpc, so clamp down in that case
4637 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4638 * Displays may support a restricted set as well, check EDID and clamp as
4639 * appropriate.
4640 *
4641 * RETURNS:
4642 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4643 * true if they don't match).
4644 */
4645static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4646 unsigned int *pipe_bpp)
4647{
4648 struct drm_device *dev = crtc->dev;
4649 struct drm_i915_private *dev_priv = dev->dev_private;
4650 struct drm_encoder *encoder;
4651 struct drm_connector *connector;
4652 unsigned int display_bpc = UINT_MAX, bpc;
4653
4654 /* Walk the encoders & connectors on this crtc, get min bpc */
4655 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4656 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4657
4658 if (encoder->crtc != crtc)
4659 continue;
4660
4661 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4662 unsigned int lvds_bpc;
4663
4664 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4665 LVDS_A3_POWER_UP)
4666 lvds_bpc = 8;
4667 else
4668 lvds_bpc = 6;
4669
4670 if (lvds_bpc < display_bpc) {
4671 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4672 display_bpc = lvds_bpc;
4673 }
4674 continue;
4675 }
4676
4677 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4678 /* Use VBT settings if we have an eDP panel */
4679 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4680
4681 if (edp_bpc < display_bpc) {
4682 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4683 display_bpc = edp_bpc;
4684 }
4685 continue;
4686 }
4687
4688 /* Not one of the known troublemakers, check the EDID */
4689 list_for_each_entry(connector, &dev->mode_config.connector_list,
4690 head) {
4691 if (connector->encoder != encoder)
4692 continue;
4693
62ac41a6
JB		 4694 /* Don't use an invalid EDID bpc value */
4695 if (connector->display_info.bpc &&
4696 connector->display_info.bpc < display_bpc) {
5a354204
JB		 4697 DRM_DEBUG_DRIVER("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4698 display_bpc = connector->display_info.bpc;
4699 }
4700 }
4701
4702 /*
4703 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4704 * through, clamp it down. (Note: >12bpc will be caught below.)
4705 */
4706 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4707 if (display_bpc > 8 && display_bpc < 12) {
4708 DRM_DEBUG_DRIVER("forcing bpc to 12 for HDMI\n");
4709 display_bpc = 12;
4710 } else {
4711 DRM_DEBUG_DRIVER("forcing bpc to 8 for HDMI\n");
4712 display_bpc = 8;
4713 }
4714 }
4715 }
4716
4717 /*
4718 * We could just drive the pipe at the highest bpc all the time and
4719 * enable dithering as needed, but that costs bandwidth. So choose
4720 * the minimum value that expresses the full color range of the fb but
4721 * also stays within the max display bpc discovered above.
4722 */
4723
4724 switch (crtc->fb->depth) {
4725 case 8:
4726 bpc = 8; /* since we go through a colormap */
4727 break;
4728 case 15:
4729 case 16:
4730 bpc = 6; /* min is 18bpp */
4731 break;
4732 case 24:
578393cd 4733 bpc = 8;
5a354204
JB		 4734 break;
4735 case 30:
578393cd 4736 bpc = 10;
5a354204
JB		 4737 break;
4738 case 48:
578393cd 4739 bpc = 12;
5a354204
JB		 4740 break;
4741 default:
4742 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4743 bpc = min((unsigned int)8, display_bpc);
4744 break;
4745 }
4746
578393cd
KP		 4747 display_bpc = min(display_bpc, bpc);
4748
5a354204
JB		 4749 DRM_DEBUG_DRIVER("setting pipe bpc to %d (max display bpc %d)\n",
4750 bpc, display_bpc);
4751
578393cd 4752 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4753
4754 return display_bpc != bpc;
4755}
4756
f564048e
EA		 4757static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4758 struct drm_display_mode *mode,
4759 struct drm_display_mode *adjusted_mode,
4760 int x, int y,
4761 struct drm_framebuffer *old_fb)
79e53945
JB		 4762{
4763 struct drm_device *dev = crtc->dev;
4764 struct drm_i915_private *dev_priv = dev->dev_private;
4765 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4766 int pipe = intel_crtc->pipe;
80824003 4767 int plane = intel_crtc->plane;
c751ce4f 4768 int refclk, num_connectors = 0;
652c393a 4769 intel_clock_t clock, reduced_clock;
5eddb70b 4770 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
652c393a 4771 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
a4fc5ed6 4772 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 4773 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 4774 struct intel_encoder *encoder;
d4906093 4775 const intel_limit_t *limit;
5c3b82e2 4776 int ret;
fae14981 4777 u32 temp;
aa9b500d 4778 u32 lvds_sync = 0;
79e53945 4779
5eddb70b
CW		 4780 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4781 if (encoder->base.crtc != crtc)
79e53945
JB		 4782 continue;
4783
5eddb70b 4784 switch (encoder->type) {
79e53945
JB		 4785 case INTEL_OUTPUT_LVDS:
4786 is_lvds = true;
4787 break;
4788 case INTEL_OUTPUT_SDVO:
7d57382e 4789 case INTEL_OUTPUT_HDMI:
79e53945 4790 is_sdvo = true;
5eddb70b 4791 if (encoder->needs_tv_clock)
e2f0ba97 4792 is_tv = true;
79e53945
JB		 4793 break;
4794 case INTEL_OUTPUT_DVO:
4795 is_dvo = true;
4796 break;
4797 case INTEL_OUTPUT_TVOUT:
4798 is_tv = true;
4799 break;
4800 case INTEL_OUTPUT_ANALOG:
4801 is_crt = true;
4802 break;
a4fc5ed6
KP		 4803 case INTEL_OUTPUT_DISPLAYPORT:
4804 is_dp = true;
4805 break;
79e53945 4806 }
43565a06 4807
c751ce4f 4808 num_connectors++;
79e53945
JB		 4809 }
4810
a7615030 4811 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 4812 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 4813 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 4814 refclk / 1000);
a6c45cf0 4815 } else if (!IS_GEN2(dev)) {
79e53945
JB		 4816 refclk = 96000;
4817 } else {
4818 refclk = 48000;
4819 }
4820
d4906093
ML		 4821 /*
4822 * Returns a set of divisors for the desired target clock with the given
4823 * refclk, or FALSE. The returned values represent the clock equation:
4824 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4825 */
1b894b59 4826 limit = intel_limit(crtc, refclk);
d4906093 4827 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 4828 if (!ok) {
4829 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4830 return -EINVAL;
79e53945
JB		 4831 }
4832
cda4b7d3 4833 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4834 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4835
ddc9003c
ZY		 4836 if (is_lvds && dev_priv->lvds_downclock_avail) {
4837 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4838 dev_priv->lvds_downclock,
4839 refclk,
4840 &reduced_clock);
18f9ed12
ZY		 4841 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
4842 /*
4843 * If the different P is found, it means that we can't
4844 * switch the display clock by using the FP0/FP1.
4845 * In such case we will disable the LVDS downclock
4846 * feature.
4847 */
4848 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 4849 "LVDS clock/downclock\n");
18f9ed12
ZY		 4850 has_reduced_clock = 0;
4851 }
652c393a 4852 }
7026d4ac
ZW		 4853 /* SDVO TV has fixed PLL values depend on its clock range,
4854 this mirrors vbios setting. */
4855 if (is_sdvo && is_tv) {
4856 if (adjusted_mode->clock >= 100000
5eddb70b 4857 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 4858 clock.p1 = 2;
4859 clock.p2 = 10;
4860 clock.n = 3;
4861 clock.m1 = 16;
4862 clock.m2 = 8;
4863 } else if (adjusted_mode->clock >= 140500
5eddb70b 4864 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 4865 clock.p1 = 1;
4866 clock.p2 = 10;
4867 clock.n = 6;
4868 clock.m1 = 12;
4869 clock.m2 = 8;
4870 }
4871 }
4872
f2b115e6 4873 if (IS_PINEVIEW(dev)) {
2177832f 4874 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 4875 if (has_reduced_clock)
4876 fp2 = (1 << reduced_clock.n) << 16 |
4877 reduced_clock.m1 << 8 | reduced_clock.m2;
4878 } else {
2177832f 4879 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 4880 if (has_reduced_clock)
4881 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4882 reduced_clock.m2;
4883 }
79e53945 4884
929c77fb 4885 dpll = DPLL_VGA_MODE_DIS;
2c07245f 4886
a6c45cf0 4887 if (!IS_GEN2(dev)) {
79e53945
JB		 4888 if (is_lvds)
4889 dpll |= DPLLB_MODE_LVDS;
4890 else
4891 dpll |= DPLLB_MODE_DAC_SERIAL;
4892 if (is_sdvo) {
6c9547ff
CW		 4893 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4894 if (pixel_multiplier > 1) {
4895 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4896 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
6c9547ff 4897 }
79e53945 4898 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4899 }
929c77fb 4900 if (is_dp)
a4fc5ed6 4901 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945
JB		 4902
4903 /* compute bitmask from p1 value */
f2b115e6
AJ		 4904 if (IS_PINEVIEW(dev))
4905 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
2c07245f 4906 else {
2177832f 4907 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
652c393a
JB		 4908 if (IS_G4X(dev) && has_reduced_clock)
4909 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2c07245f 4910 }
79e53945
JB		 4911 switch (clock.p2) {
4912 case 5:
4913 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4914 break;
4915 case 7:
4916 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4917 break;
4918 case 10:
4919 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4920 break;
4921 case 14:
4922 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4923 break;
4924 }
929c77fb 4925 if (INTEL_INFO(dev)->gen >= 4)
79e53945
JB		 4926 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4927 } else {
4928 if (is_lvds) {
4929 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4930 } else {
4931 if (clock.p1 == 2)
4932 dpll |= PLL_P1_DIVIDE_BY_TWO;
4933 else
4934 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4935 if (clock.p2 == 4)
4936 dpll |= PLL_P2_DIVIDE_BY_4;
4937 }
4938 }
4939
43565a06
KH		 4940 if (is_sdvo && is_tv)
4941 dpll |= PLL_REF_INPUT_TVCLKINBC;
4942 else if (is_tv)
79e53945 4943 /* XXX: just matching BIOS for now */
43565a06 4944 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4945 dpll |= 3;
a7615030 4946 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4947 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4948 else
4949 dpll |= PLL_REF_INPUT_DREFCLK;
4950
4951 /* setup pipeconf */
5eddb70b 4952 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4953
4954 /* Set up the display plane register */
4955 dspcntr = DISPPLANE_GAMMA_ENABLE;
4956
f2b115e6 4957 /* Ironlake's plane is forced to pipe, bit 24 is to
2c07245f 4958 enable color space conversion */
929c77fb
EA		 4959 if (pipe == 0)
4960 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4961 else
4962 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4963
a6c45cf0 4964 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4965 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4966 * core speed.
4967 *
4968 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4969 * pipe == 0 check?
4970 */
e70236a8
JB		 4971 if (mode->clock >
4972 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4973 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4974 else
5eddb70b 4975 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4976 }
4977
929c77fb 4978 dpll |= DPLL_VCO_ENABLE;
8d86dc6a 4979
28c97730 4980 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4981 drm_mode_debug_printmodeline(mode);
4982
fae14981
EA		 4983 I915_WRITE(FP0(pipe), fp);
4984 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 4985
fae14981 4986 POSTING_READ(DPLL(pipe));
c713bb08 4987 udelay(150);
8db9d77b 4988
79e53945
JB		 4989 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4990 * This is an exception to the general rule that mode_set doesn't turn
4991 * things on.
4992 */
4993 if (is_lvds) {
fae14981 4994 temp = I915_READ(LVDS);
5eddb70b 4995 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3 4996 if (pipe == 1) {
929c77fb 4997 temp |= LVDS_PIPEB_SELECT;
b3b095b3 4998 } else {
929c77fb 4999 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 5000 }
a3e17eb8 5001 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5002 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5003 /* Set the B0-B3 data pairs corresponding to whether we're going to
5004 * set the DPLLs for dual-channel mode or not.
5005 */
5006 if (clock.p2 == 7)
5eddb70b 5007 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5008 else
5eddb70b 5009 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5010
5011 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5012 * appropriately here, but we need to look more thoroughly into how
5013 * panels behave in the two modes.
5014 */
929c77fb
EA		 5015 /* set the dithering flag on LVDS as needed */
5016 if (INTEL_INFO(dev)->gen >= 4) {
434ed097 5017 if (dev_priv->lvds_dither)
5eddb70b 5018 temp |= LVDS_ENABLE_DITHER;
434ed097 5019 else
5eddb70b 5020 temp &= ~LVDS_ENABLE_DITHER;
898822ce 5021 }
aa9b500d
BF		 5022 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5023 lvds_sync |= LVDS_HSYNC_POLARITY;
5024 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5025 lvds_sync |= LVDS_VSYNC_POLARITY;
5026 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5027 != lvds_sync) {
5028 char flags[2] = "-+";
5029 DRM_INFO("Changing LVDS panel from "
5030 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5031 flags[!(temp & LVDS_HSYNC_POLARITY)],
5032 flags[!(temp & LVDS_VSYNC_POLARITY)],
5033 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5034 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5035 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5036 temp |= lvds_sync;
5037 }
fae14981 5038 I915_WRITE(LVDS, temp);
79e53945 5039 }
434ed097 5040
929c77fb 5041 if (is_dp) {
a4fc5ed6 5042 intel_dp_set_m_n(crtc, mode, adjusted_mode);
434ed097
JB		 5043 }
5044
fae14981 5045 I915_WRITE(DPLL(pipe), dpll);
5eddb70b 5046
c713bb08 5047 /* Wait for the clocks to stabilize. */
fae14981 5048 POSTING_READ(DPLL(pipe));
c713bb08 5049 udelay(150);
32f9d658 5050
c713bb08
EA		 5051 if (INTEL_INFO(dev)->gen >= 4) {
5052 temp = 0;
5053 if (is_sdvo) {
5054 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5055 if (temp > 1)
5056 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5057 else
5058 temp = 0;
32f9d658 5059 }
c713bb08
EA		 5060 I915_WRITE(DPLL_MD(pipe), temp);
5061 } else {
5062 /* The pixel multiplier can only be updated once the
5063 * DPLL is enabled and the clocks are stable.
5064 *
5065 * So write it again.
5066 */
fae14981 5067 I915_WRITE(DPLL(pipe), dpll);
79e53945 5068 }
79e53945 5069
5eddb70b 5070 intel_crtc->lowfreq_avail = false;
652c393a 5071 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 5072 I915_WRITE(FP1(pipe), fp2);
652c393a
JB		 5073 intel_crtc->lowfreq_avail = true;
5074 if (HAS_PIPE_CXSR(dev)) {
28c97730 5075 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 5076 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5077 }
5078 } else {
fae14981 5079 I915_WRITE(FP1(pipe), fp);
652c393a 5080 if (HAS_PIPE_CXSR(dev)) {
28c97730 5081 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5082 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5083 }
5084 }
5085
734b4157
KH		 5086 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5087 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5088 /* the chip adds 2 halflines automatically */
5089 adjusted_mode->crtc_vdisplay -= 1;
5090 adjusted_mode->crtc_vtotal -= 1;
5091 adjusted_mode->crtc_vblank_start -= 1;
5092 adjusted_mode->crtc_vblank_end -= 1;
5093 adjusted_mode->crtc_vsync_end -= 1;
5094 adjusted_mode->crtc_vsync_start -= 1;
5095 } else
5096 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5097
5eddb70b
CW		 5098 I915_WRITE(HTOTAL(pipe),
5099 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5100 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5101 I915_WRITE(HBLANK(pipe),
5102 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5103 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5104 I915_WRITE(HSYNC(pipe),
5105 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5106 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5107
5108 I915_WRITE(VTOTAL(pipe),
5109 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5110 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5111 I915_WRITE(VBLANK(pipe),
5112 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5113 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5114 I915_WRITE(VSYNC(pipe),
5115 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5116 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 5117
5118 /* pipesrc and dspsize control the size that is scaled from,
5119 * which should always be the user's requested size.
79e53945 5120 */
929c77fb
EA		 5121 I915_WRITE(DSPSIZE(plane),
5122 ((mode->vdisplay - 1) << 16) |
5123 (mode->hdisplay - 1));
5124 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 5125 I915_WRITE(PIPESRC(pipe),
5126 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5127
f564048e
EA		 5128 I915_WRITE(PIPECONF(pipe), pipeconf);
5129 POSTING_READ(PIPECONF(pipe));
929c77fb 5130 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 5131
5132 intel_wait_for_vblank(dev, pipe);
5133
f564048e
EA		 5134 I915_WRITE(DSPCNTR(plane), dspcntr);
5135 POSTING_READ(DSPCNTR(plane));
284d9529 5136 intel_enable_plane(dev_priv, plane, pipe);
f564048e
EA		 5137
5138 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5139
5140 intel_update_watermarks(dev);
5141
f564048e
EA		 5142 return ret;
5143}
5144
9fb526db
KP		 5145/*
5146 * Initialize reference clocks when the driver loads
5147 */
5148void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5149{
5150 struct drm_i915_private *dev_priv = dev->dev_private;
5151 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5152 struct intel_encoder *encoder;
13d83a67
JB		 5153 u32 temp;
5154 bool has_lvds = false;
199e5d79
KP		 5155 bool has_cpu_edp = false;
5156 bool has_pch_edp = false;
5157 bool has_panel = false;
99eb6a01
KP		 5158 bool has_ck505 = false;
5159 bool can_ssc = false;
13d83a67
JB		 5160
5161 /* We need to take the global config into account */
199e5d79
KP		 5162 list_for_each_entry(encoder, &mode_config->encoder_list,
5163 base.head) {
5164 switch (encoder->type) {
5165 case INTEL_OUTPUT_LVDS:
5166 has_panel = true;
5167 has_lvds = true;
5168 break;
5169 case INTEL_OUTPUT_EDP:
5170 has_panel = true;
5171 if (intel_encoder_is_pch_edp(&encoder->base))
5172 has_pch_edp = true;
5173 else
5174 has_cpu_edp = true;
5175 break;
13d83a67
JB		 5176 }
5177 }
5178
99eb6a01
KP		 5179 if (HAS_PCH_IBX(dev)) {
5180 has_ck505 = dev_priv->display_clock_mode;
5181 can_ssc = has_ck505;
5182 } else {
5183 has_ck505 = false;
5184 can_ssc = true;
5185 }
5186
5187 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5188 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5189 has_ck505);
13d83a67
JB		 5190
5191 /* Ironlake: try to setup display ref clock before DPLL
5192 * enabling. This is only under driver's control after
5193 * PCH B stepping, previous chipset stepping should be
5194 * ignoring this setting.
5195 */
5196 temp = I915_READ(PCH_DREF_CONTROL);
5197 /* Always enable nonspread source */
5198 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5199
99eb6a01
KP		 5200 if (has_ck505)
5201 temp |= DREF_NONSPREAD_CK505_ENABLE;
5202 else
5203 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5204
199e5d79
KP		 5205 if (has_panel) {
5206 temp &= ~DREF_SSC_SOURCE_MASK;
5207 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5208
199e5d79 5209 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5210 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5211 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 5212 temp |= DREF_SSC1_ENABLE;
13d83a67 5213 }
199e5d79
KP		 5214
5215 /* Get SSC going before enabling the outputs */
5216 I915_WRITE(PCH_DREF_CONTROL, temp);
5217 POSTING_READ(PCH_DREF_CONTROL);
5218 udelay(200);
5219
13d83a67
JB		 5220 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5221
5222 /* Enable CPU source on CPU attached eDP */
199e5d79 5223 if (has_cpu_edp) {
99eb6a01 5224 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5225 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 5226 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5227 }
13d83a67
JB		 5228 else
5229 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 5230 } else
5231 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5232
5233 I915_WRITE(PCH_DREF_CONTROL, temp);
5234 POSTING_READ(PCH_DREF_CONTROL);
5235 udelay(200);
5236 } else {
5237 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5238
5239 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5240
5241 /* Turn off CPU output */
5242 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5243
5244 I915_WRITE(PCH_DREF_CONTROL, temp);
5245 POSTING_READ(PCH_DREF_CONTROL);
5246 udelay(200);
5247
5248 /* Turn off the SSC source */
5249 temp &= ~DREF_SSC_SOURCE_MASK;
5250 temp |= DREF_SSC_SOURCE_DISABLE;
5251
5252 /* Turn off SSC1 */
5253 temp &= ~ DREF_SSC1_ENABLE;
5254
13d83a67
JB		 5255 I915_WRITE(PCH_DREF_CONTROL, temp);
5256 POSTING_READ(PCH_DREF_CONTROL);
5257 udelay(200);
5258 }
5259}
5260
d9d444cb
JB		 5261static int ironlake_get_refclk(struct drm_crtc *crtc)
5262{
5263 struct drm_device *dev = crtc->dev;
5264 struct drm_i915_private *dev_priv = dev->dev_private;
5265 struct intel_encoder *encoder;
5266 struct drm_mode_config *mode_config = &dev->mode_config;
5267 struct intel_encoder *edp_encoder = NULL;
5268 int num_connectors = 0;
5269 bool is_lvds = false;
5270
5271 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5272 if (encoder->base.crtc != crtc)
5273 continue;
5274
5275 switch (encoder->type) {
5276 case INTEL_OUTPUT_LVDS:
5277 is_lvds = true;
5278 break;
5279 case INTEL_OUTPUT_EDP:
5280 edp_encoder = encoder;
5281 break;
5282 }
5283 num_connectors++;
5284 }
5285
5286 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5287 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5288 dev_priv->lvds_ssc_freq);
5289 return dev_priv->lvds_ssc_freq * 1000;
5290 }
5291
5292 return 120000;
5293}
5294
f564048e
EA		 5295static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5296 struct drm_display_mode *mode,
5297 struct drm_display_mode *adjusted_mode,
5298 int x, int y,
5299 struct drm_framebuffer *old_fb)
79e53945
JB		 5300{
5301 struct drm_device *dev = crtc->dev;
5302 struct drm_i915_private *dev_priv = dev->dev_private;
5303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5304 int pipe = intel_crtc->pipe;
80824003 5305 int plane = intel_crtc->plane;
c751ce4f 5306 int refclk, num_connectors = 0;
652c393a 5307 intel_clock_t clock, reduced_clock;
5eddb70b 5308 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 5309 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 5310 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
8e647a27 5311 struct intel_encoder *has_edp_encoder = NULL;
79e53945 5312 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 5313 struct intel_encoder *encoder;
d4906093 5314 const intel_limit_t *limit;
5c3b82e2 5315 int ret;
2c07245f 5316 struct fdi_m_n m_n = {0};
fae14981 5317 u32 temp;
aa9b500d 5318 u32 lvds_sync = 0;
5a354204
JB		 5319 int target_clock, pixel_multiplier, lane, link_bw, factor;
5320 unsigned int pipe_bpp;
5321 bool dither;
79e53945 5322
5eddb70b
CW		 5323 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5324 if (encoder->base.crtc != crtc)
79e53945
JB		 5325 continue;
5326
5eddb70b 5327 switch (encoder->type) {
79e53945
JB		 5328 case INTEL_OUTPUT_LVDS:
5329 is_lvds = true;
5330 break;
5331 case INTEL_OUTPUT_SDVO:
7d57382e 5332 case INTEL_OUTPUT_HDMI:
79e53945 5333 is_sdvo = true;
5eddb70b 5334 if (encoder->needs_tv_clock)
e2f0ba97 5335 is_tv = true;
79e53945 5336 break;
79e53945
JB		 5337 case INTEL_OUTPUT_TVOUT:
5338 is_tv = true;
5339 break;
5340 case INTEL_OUTPUT_ANALOG:
5341 is_crt = true;
5342 break;
a4fc5ed6
KP		 5343 case INTEL_OUTPUT_DISPLAYPORT:
5344 is_dp = true;
5345 break;
32f9d658 5346 case INTEL_OUTPUT_EDP:
5eddb70b 5347 has_edp_encoder = encoder;
32f9d658 5348 break;
79e53945 5349 }
43565a06 5350
c751ce4f 5351 num_connectors++;
79e53945
JB		 5352 }
5353
d9d444cb 5354 refclk = ironlake_get_refclk(crtc);
79e53945 5355
d4906093
ML		 5356 /*
5357 * Returns a set of divisors for the desired target clock with the given
5358 * refclk, or FALSE. The returned values represent the clock equation:
5359 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5360 */
1b894b59 5361 limit = intel_limit(crtc, refclk);
d4906093 5362 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 5363 if (!ok) {
5364 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 5365 return -EINVAL;
79e53945
JB		 5366 }
5367
cda4b7d3 5368 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 5369 intel_crtc_update_cursor(crtc, true);
cda4b7d3 5370
ddc9003c
ZY		 5371 if (is_lvds && dev_priv->lvds_downclock_avail) {
5372 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 5373 dev_priv->lvds_downclock,
5374 refclk,
5375 &reduced_clock);
18f9ed12
ZY		 5376 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5377 /*
5378 * If the different P is found, it means that we can't
5379 * switch the display clock by using the FP0/FP1.
5380 * In such case we will disable the LVDS downclock
5381 * feature.
5382 */
5383 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 5384 "LVDS clock/downclock\n");
18f9ed12
ZY		 5385 has_reduced_clock = 0;
5386 }
652c393a 5387 }
7026d4ac
ZW		 5388 /* SDVO TV has fixed PLL values depend on its clock range,
5389 this mirrors vbios setting. */
5390 if (is_sdvo && is_tv) {
5391 if (adjusted_mode->clock >= 100000
5eddb70b 5392 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 5393 clock.p1 = 2;
5394 clock.p2 = 10;
5395 clock.n = 3;
5396 clock.m1 = 16;
5397 clock.m2 = 8;
5398 } else if (adjusted_mode->clock >= 140500
5eddb70b 5399 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 5400 clock.p1 = 1;
5401 clock.p2 = 10;
5402 clock.n = 6;
5403 clock.m1 = 12;
5404 clock.m2 = 8;
5405 }
5406 }
5407
2c07245f 5408 /* FDI link */
8febb297
EA		 5409 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5410 lane = 0;
5411 /* CPU eDP doesn't require FDI link, so just set DP M/N
5412 according to current link config */
5413 if (has_edp_encoder &&
5414 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5415 target_clock = mode->clock;
5416 intel_edp_link_config(has_edp_encoder,
5417 &lane, &link_bw);
5418 } else {
5419 /* [e]DP over FDI requires target mode clock
5420 instead of link clock */
5421 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5eb08b69 5422 target_clock = mode->clock;
8febb297
EA		 5423 else
5424 target_clock = adjusted_mode->clock;
5425
5426 /* FDI is a binary signal running at ~2.7GHz, encoding
5427 * each output octet as 10 bits. The actual frequency
5428 * is stored as a divider into a 100MHz clock, and the
5429 * mode pixel clock is stored in units of 1KHz.
5430 * Hence the bw of each lane in terms of the mode signal
5431 * is:
5432 */
5433 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5434 }
58a27471 5435
8febb297
EA		 5436 /* determine panel color depth */
5437 temp = I915_READ(PIPECONF(pipe));
5438 temp &= ~PIPE_BPC_MASK;
5a354204
JB		 5439 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp);
5440 switch (pipe_bpp) {
5441 case 18:
5442 temp |= PIPE_6BPC;
8febb297 5443 break;
5a354204
JB		 5444 case 24:
5445 temp |= PIPE_8BPC;
8febb297 5446 break;
5a354204
JB		 5447 case 30:
5448 temp |= PIPE_10BPC;
8febb297 5449 break;
5a354204
JB		 5450 case 36:
5451 temp |= PIPE_12BPC;
8febb297
EA		 5452 break;
5453 default:
62ac41a6
JB		 5454 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5455 pipe_bpp);
5a354204
JB		 5456 temp |= PIPE_8BPC;
5457 pipe_bpp = 24;
5458 break;
8febb297 5459 }
77ffb597 5460
5a354204
JB		 5461 intel_crtc->bpp = pipe_bpp;
5462 I915_WRITE(PIPECONF(pipe), temp);
5463
8febb297
EA		 5464 if (!lane) {
5465 /*
5466 * Account for spread spectrum to avoid
5467 * oversubscribing the link. Max center spread
5468 * is 2.5%; use 5% for safety's sake.
5469 */
5a354204 5470 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 5471 lane = bps / (link_bw * 8) + 1;
5eb08b69 5472 }
2c07245f 5473
8febb297
EA		 5474 intel_crtc->fdi_lanes = lane;
5475
5476 if (pixel_multiplier > 1)
5477 link_bw *= pixel_multiplier;
5a354204
JB		 5478 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5479 &m_n);
8febb297 5480
a07d6787
EA		 5481 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5482 if (has_reduced_clock)
5483 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5484 reduced_clock.m2;
79e53945 5485
c1858123 5486 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5487 factor = 21;
5488 if (is_lvds) {
5489 if ((intel_panel_use_ssc(dev_priv) &&
5490 dev_priv->lvds_ssc_freq == 100) ||
5491 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5492 factor = 25;
5493 } else if (is_sdvo && is_tv)
5494 factor = 20;
c1858123 5495
cb0e0931 5496 if (clock.m < factor * clock.n)
8febb297 5497 fp |= FP_CB_TUNE;
2c07245f 5498
5eddb70b 5499 dpll = 0;
2c07245f 5500
a07d6787
EA		 5501 if (is_lvds)
5502 dpll |= DPLLB_MODE_LVDS;
5503 else
5504 dpll |= DPLLB_MODE_DAC_SERIAL;
5505 if (is_sdvo) {
5506 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5507 if (pixel_multiplier > 1) {
5508 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5509 }
a07d6787
EA		 5510 dpll |= DPLL_DVO_HIGH_SPEED;
5511 }
5512 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5513 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5514
a07d6787
EA		 5515 /* compute bitmask from p1 value */
5516 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5517 /* also FPA1 */
5518 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5519
5520 switch (clock.p2) {
5521 case 5:
5522 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5523 break;
5524 case 7:
5525 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5526 break;
5527 case 10:
5528 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5529 break;
5530 case 14:
5531 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5532 break;
79e53945
JB		 5533 }
5534
43565a06
KH		 5535 if (is_sdvo && is_tv)
5536 dpll |= PLL_REF_INPUT_TVCLKINBC;
5537 else if (is_tv)
79e53945 5538 /* XXX: just matching BIOS for now */
43565a06 5539 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5540 dpll |= 3;
a7615030 5541 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5542 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5543 else
5544 dpll |= PLL_REF_INPUT_DREFCLK;
5545
5546 /* setup pipeconf */
5eddb70b 5547 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5548
5549 /* Set up the display plane register */
5550 dspcntr = DISPPLANE_GAMMA_ENABLE;
5551
28c97730 5552 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 5553 drm_mode_debug_printmodeline(mode);
5554
5c5313c8 5555 /* PCH eDP needs FDI, but CPU eDP does not */
4b645f14
JB		 5556 if (!intel_crtc->no_pll) {
5557 if (!has_edp_encoder ||
5558 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5559 I915_WRITE(PCH_FP0(pipe), fp);
5560 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5561
5562 POSTING_READ(PCH_DPLL(pipe));
5563 udelay(150);
5564 }
5565 } else {
5566 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5567 fp == I915_READ(PCH_FP0(0))) {
5568 intel_crtc->use_pll_a = true;
5569 DRM_DEBUG_KMS("using pipe a dpll\n");
5570 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5571 fp == I915_READ(PCH_FP0(1))) {
5572 intel_crtc->use_pll_a = false;
5573 DRM_DEBUG_KMS("using pipe b dpll\n");
5574 } else {
5575 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5576 return -EINVAL;
5577 }
79e53945
JB		 5578 }
5579
8db9d77b
ZW		 5580 /* enable transcoder DPLL */
5581 if (HAS_PCH_CPT(dev)) {
4b645f14
JB		 5582 u32 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
5583 TRANSC_DPLLB_SEL;
8db9d77b 5584 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 5585 switch (pipe) {
5586 case 0:
5eddb70b 5587 temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
9db4a9c7
JB		 5588 break;
5589 case 1:
5eddb70b 5590 temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
9db4a9c7
JB		 5591 break;
5592 case 2:
4b645f14 5593 temp |= TRANSC_DPLL_ENABLE | transc_sel;
9db4a9c7
JB		 5594 break;
5595 default:
5596 BUG();
32f9d658 5597 }
8db9d77b 5598 I915_WRITE(PCH_DPLL_SEL, temp);
5eddb70b
CW		 5599
5600 POSTING_READ(PCH_DPLL_SEL);
8db9d77b
ZW		 5601 udelay(150);
5602 }
5603
79e53945
JB		 5604 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5605 * This is an exception to the general rule that mode_set doesn't turn
5606 * things on.
5607 */
5608 if (is_lvds) {
fae14981 5609 temp = I915_READ(PCH_LVDS);
5eddb70b 5610 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4b645f14
JB		 5611 if (HAS_PCH_CPT(dev))
5612 temp |= PORT_TRANS_SEL_CPT(pipe);
5613 else if (pipe == 1)
5614 temp |= LVDS_PIPEB_SELECT;
5615 else
5616 temp &= ~LVDS_PIPEB_SELECT;
5617
a3e17eb8 5618 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5619 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5620 /* Set the B0-B3 data pairs corresponding to whether we're going to
5621 * set the DPLLs for dual-channel mode or not.
5622 */
5623 if (clock.p2 == 7)
5eddb70b 5624 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5625 else
5eddb70b 5626 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5627
5628 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5629 * appropriately here, but we need to look more thoroughly into how
5630 * panels behave in the two modes.
5631 */
aa9b500d
BF		 5632 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5633 lvds_sync |= LVDS_HSYNC_POLARITY;
5634 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5635 lvds_sync |= LVDS_VSYNC_POLARITY;
5636 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5637 != lvds_sync) {
5638 char flags[2] = "-+";
5639 DRM_INFO("Changing LVDS panel from "
5640 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5641 flags[!(temp & LVDS_HSYNC_POLARITY)],
5642 flags[!(temp & LVDS_VSYNC_POLARITY)],
5643 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5644 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5645 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5646 temp |= lvds_sync;
5647 }
fae14981 5648 I915_WRITE(PCH_LVDS, temp);
79e53945 5649 }
434ed097 5650
8febb297
EA		 5651 pipeconf &= ~PIPECONF_DITHER_EN;
5652 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 5653 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297
EA		 5654 pipeconf |= PIPECONF_DITHER_EN;
5655 pipeconf |= PIPECONF_DITHER_TYPE_ST1;
434ed097 5656 }
5c5313c8 5657 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
a4fc5ed6 5658 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5659 } else {
8db9d77b 5660 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5661 I915_WRITE(TRANSDATA_M1(pipe), 0);
5662 I915_WRITE(TRANSDATA_N1(pipe), 0);
5663 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5664 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5665 }
79e53945 5666
4b645f14
JB		 5667 if (!intel_crtc->no_pll &&
5668 (!has_edp_encoder ||
5669 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
fae14981 5670 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 5671
32f9d658 5672 /* Wait for the clocks to stabilize. */
fae14981 5673 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 5674 udelay(150);
5675
8febb297
EA		 5676 /* The pixel multiplier can only be updated once the
5677 * DPLL is enabled and the clocks are stable.
5678 *
5679 * So write it again.
5680 */
fae14981 5681 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 5682 }
79e53945 5683
5eddb70b 5684 intel_crtc->lowfreq_avail = false;
4b645f14
JB		 5685 if (!intel_crtc->no_pll) {
5686 if (is_lvds && has_reduced_clock && i915_powersave) {
5687 I915_WRITE(PCH_FP1(pipe), fp2);
5688 intel_crtc->lowfreq_avail = true;
5689 if (HAS_PIPE_CXSR(dev)) {
5690 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5691 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5692 }
5693 } else {
5694 I915_WRITE(PCH_FP1(pipe), fp);
5695 if (HAS_PIPE_CXSR(dev)) {
5696 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5697 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5698 }
652c393a
JB		 5699 }
5700 }
5701
734b4157
KH		 5702 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5703 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5704 /* the chip adds 2 halflines automatically */
5705 adjusted_mode->crtc_vdisplay -= 1;
5706 adjusted_mode->crtc_vtotal -= 1;
5707 adjusted_mode->crtc_vblank_start -= 1;
5708 adjusted_mode->crtc_vblank_end -= 1;
5709 adjusted_mode->crtc_vsync_end -= 1;
5710 adjusted_mode->crtc_vsync_start -= 1;
5711 } else
5712 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
5713
5eddb70b
CW		 5714 I915_WRITE(HTOTAL(pipe),
5715 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5716 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5717 I915_WRITE(HBLANK(pipe),
5718 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5719 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5720 I915_WRITE(HSYNC(pipe),
5721 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5722 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5723
5724 I915_WRITE(VTOTAL(pipe),
5725 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5726 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5727 I915_WRITE(VBLANK(pipe),
5728 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5729 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5730 I915_WRITE(VSYNC(pipe),
5731 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5732 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 5733
8febb297
EA		 5734 /* pipesrc controls the size that is scaled from, which should
5735 * always be the user's requested size.
79e53945 5736 */
5eddb70b
CW		 5737 I915_WRITE(PIPESRC(pipe),
5738 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5739
8febb297
EA		 5740 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5741 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5742 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5743 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 5744
8febb297
EA		 5745 if (has_edp_encoder &&
5746 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5747 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f
ZW		 5748 }
5749
5eddb70b
CW		 5750 I915_WRITE(PIPECONF(pipe), pipeconf);
5751 POSTING_READ(PIPECONF(pipe));
79e53945 5752
9d0498a2 5753 intel_wait_for_vblank(dev, pipe);
79e53945 5754
f00a3ddf 5755 if (IS_GEN5(dev)) {
553bd149
ZW		 5756 /* enable address swizzle for tiling buffer */
5757 temp = I915_READ(DISP_ARB_CTL);
5758 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5759 }
5760
5eddb70b 5761 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 5762 POSTING_READ(DSPCNTR(plane));
79e53945 5763
5c3b82e2 5764 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 5765
5766 intel_update_watermarks(dev);
5767
1f803ee5 5768 return ret;
79e53945
JB		 5769}
5770
f564048e
EA		 5771static int intel_crtc_mode_set(struct drm_crtc *crtc,
5772 struct drm_display_mode *mode,
5773 struct drm_display_mode *adjusted_mode,
5774 int x, int y,
5775 struct drm_framebuffer *old_fb)
5776{
5777 struct drm_device *dev = crtc->dev;
5778 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5779 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5780 int pipe = intel_crtc->pipe;
f564048e
EA		 5781 int ret;
5782
0b701d27 5783 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5784
f564048e
EA		 5785 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5786 x, y, old_fb);
7662c8bd 5787
79e53945 5788 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5789
120eced9
KP		 5790 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
5791
1f803ee5 5792 return ret;
79e53945
JB		 5793}
5794
e0dac65e
WF		 5795static void g4x_write_eld(struct drm_connector *connector,
5796 struct drm_crtc *crtc)
5797{
5798 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5799 uint8_t *eld = connector->eld;
5800 uint32_t eldv;
5801 uint32_t len;
5802 uint32_t i;
5803
5804 i = I915_READ(G4X_AUD_VID_DID);
5805
5806 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5807 eldv = G4X_ELDV_DEVCL_DEVBLC;
5808 else
5809 eldv = G4X_ELDV_DEVCTG;
5810
5811 i = I915_READ(G4X_AUD_CNTL_ST);
5812 i &= ~(eldv | G4X_ELD_ADDR);
5813 len = (i >> 9) & 0x1f; /* ELD buffer size */
5814 I915_WRITE(G4X_AUD_CNTL_ST, i);
5815
5816 if (!eld[0])
5817 return;
5818
5819 len = min_t(uint8_t, eld[2], len);
5820 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5821 for (i = 0; i < len; i++)
5822 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5823
5824 i = I915_READ(G4X_AUD_CNTL_ST);
5825 i |= eldv;
5826 I915_WRITE(G4X_AUD_CNTL_ST, i);
5827}
5828
5829static void ironlake_write_eld(struct drm_connector *connector,
5830 struct drm_crtc *crtc)
5831{
5832 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5833 uint8_t *eld = connector->eld;
5834 uint32_t eldv;
5835 uint32_t i;
5836 int len;
5837 int hdmiw_hdmiedid;
5838 int aud_cntl_st;
5839 int aud_cntrl_st2;
5840
5841 if (IS_IVYBRIDGE(connector->dev)) {
5842 hdmiw_hdmiedid = GEN7_HDMIW_HDMIEDID_A;
5843 aud_cntl_st = GEN7_AUD_CNTRL_ST_A;
5844 aud_cntrl_st2 = GEN7_AUD_CNTRL_ST2;
5845 } else {
5846 hdmiw_hdmiedid = GEN5_HDMIW_HDMIEDID_A;
5847 aud_cntl_st = GEN5_AUD_CNTL_ST_A;
5848 aud_cntrl_st2 = GEN5_AUD_CNTL_ST2;
5849 }
5850
5851 i = to_intel_crtc(crtc)->pipe;
5852 hdmiw_hdmiedid += i * 0x100;
5853 aud_cntl_st += i * 0x100;
5854
5855 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
5856
5857 i = I915_READ(aud_cntl_st);
5858 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
5859 if (!i) {
5860 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5861 /* operate blindly on all ports */
5862 eldv = GEN5_ELD_VALIDB;
5863 eldv |= GEN5_ELD_VALIDB << 4;
5864 eldv |= GEN5_ELD_VALIDB << 8;
5865 } else {
5866 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5867 eldv = GEN5_ELD_VALIDB << ((i - 1) * 4);
5868 }
5869
5870 i = I915_READ(aud_cntrl_st2);
5871 i &= ~eldv;
5872 I915_WRITE(aud_cntrl_st2, i);
5873
5874 if (!eld[0])
5875 return;
5876
5877 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5878 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5879 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5880 }
5881
5882 i = I915_READ(aud_cntl_st);
5883 i &= ~GEN5_ELD_ADDRESS;
5884 I915_WRITE(aud_cntl_st, i);
5885
5886 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5887 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5888 for (i = 0; i < len; i++)
5889 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5890
5891 i = I915_READ(aud_cntrl_st2);
5892 i |= eldv;
5893 I915_WRITE(aud_cntrl_st2, i);
5894}
5895
5896void intel_write_eld(struct drm_encoder *encoder,
5897 struct drm_display_mode *mode)
5898{
5899 struct drm_crtc *crtc = encoder->crtc;
5900 struct drm_connector *connector;
5901 struct drm_device *dev = encoder->dev;
5902 struct drm_i915_private *dev_priv = dev->dev_private;
5903
5904 connector = drm_select_eld(encoder, mode);
5905 if (!connector)
5906 return;
5907
5908 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5909 connector->base.id,
5910 drm_get_connector_name(connector),
5911 connector->encoder->base.id,
5912 drm_get_encoder_name(connector->encoder));
5913
5914 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5915
5916 if (dev_priv->display.write_eld)
5917 dev_priv->display.write_eld(connector, crtc);
5918}
5919
79e53945
JB		 5920/** Loads the palette/gamma unit for the CRTC with the prepared values */
5921void intel_crtc_load_lut(struct drm_crtc *crtc)
5922{
5923 struct drm_device *dev = crtc->dev;
5924 struct drm_i915_private *dev_priv = dev->dev_private;
5925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5926 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5927 int i;
5928
5929 /* The clocks have to be on to load the palette. */
5930 if (!crtc->enabled)
5931 return;
5932
f2b115e6 5933 /* use legacy palette for Ironlake */
bad720ff 5934 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5935 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5936
79e53945
JB		 5937 for (i = 0; i < 256; i++) {
5938 I915_WRITE(palreg + 4 * i,
5939 (intel_crtc->lut_r[i] << 16) |
5940 (intel_crtc->lut_g[i] << 8) |
5941 intel_crtc->lut_b[i]);
5942 }
5943}
5944
560b85bb
CW		 5945static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5946{
5947 struct drm_device *dev = crtc->dev;
5948 struct drm_i915_private *dev_priv = dev->dev_private;
5949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5950 bool visible = base != 0;
5951 u32 cntl;
5952
5953 if (intel_crtc->cursor_visible == visible)
5954 return;
5955
9db4a9c7 5956 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5957 if (visible) {
5958 /* On these chipsets we can only modify the base whilst
5959 * the cursor is disabled.
5960 */
9db4a9c7 5961 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5962
5963 cntl &= ~(CURSOR_FORMAT_MASK);
5964 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5965 cntl |= CURSOR_ENABLE |
5966 CURSOR_GAMMA_ENABLE |
5967 CURSOR_FORMAT_ARGB;
5968 } else
5969 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5970 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5971
5972 intel_crtc->cursor_visible = visible;
5973}
5974
5975static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5976{
5977 struct drm_device *dev = crtc->dev;
5978 struct drm_i915_private *dev_priv = dev->dev_private;
5979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5980 int pipe = intel_crtc->pipe;
5981 bool visible = base != 0;
5982
5983 if (intel_crtc->cursor_visible != visible) {
548f245b 5984 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5985 if (base) {
5986 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5987 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5988 cntl |= pipe << 28; /* Connect to correct pipe */
5989 } else {
5990 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5991 cntl |= CURSOR_MODE_DISABLE;
5992 }
9db4a9c7 5993 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5994
5995 intel_crtc->cursor_visible = visible;
5996 }
5997 /* and commit changes on next vblank */
9db4a9c7 5998 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5999}
6000
cda4b7d3 6001/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6002static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6003 bool on)
cda4b7d3
CW		 6004{
6005 struct drm_device *dev = crtc->dev;
6006 struct drm_i915_private *dev_priv = dev->dev_private;
6007 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6008 int pipe = intel_crtc->pipe;
6009 int x = intel_crtc->cursor_x;
6010 int y = intel_crtc->cursor_y;
560b85bb 6011 u32 base, pos;
cda4b7d3
CW		 6012 bool visible;
6013
6014 pos = 0;
6015
6b383a7f 6016 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6017 base = intel_crtc->cursor_addr;
6018 if (x > (int) crtc->fb->width)
6019 base = 0;
6020
6021 if (y > (int) crtc->fb->height)
6022 base = 0;
6023 } else
6024 base = 0;
6025
6026 if (x < 0) {
6027 if (x + intel_crtc->cursor_width < 0)
6028 base = 0;
6029
6030 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6031 x = -x;
6032 }
6033 pos |= x << CURSOR_X_SHIFT;
6034
6035 if (y < 0) {
6036 if (y + intel_crtc->cursor_height < 0)
6037 base = 0;
6038
6039 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6040 y = -y;
6041 }
6042 pos |= y << CURSOR_Y_SHIFT;
6043
6044 visible = base != 0;
560b85bb 6045 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6046 return;
6047
9db4a9c7 6048 I915_WRITE(CURPOS(pipe), pos);
560b85bb
CW		 6049 if (IS_845G(dev) || IS_I865G(dev))
6050 i845_update_cursor(crtc, base);
6051 else
6052 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 6053
6054 if (visible)
6055 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6056}
6057
79e53945 6058static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6059 struct drm_file *file,
79e53945
JB		 6060 uint32_t handle,
6061 uint32_t width, uint32_t height)
6062{
6063 struct drm_device *dev = crtc->dev;
6064 struct drm_i915_private *dev_priv = dev->dev_private;
6065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6066 struct drm_i915_gem_object *obj;
cda4b7d3 6067 uint32_t addr;
3f8bc370 6068 int ret;
79e53945 6069
28c97730 6070 DRM_DEBUG_KMS("\n");
79e53945
JB		 6071
6072 /* if we want to turn off the cursor ignore width and height */
6073 if (!handle) {
28c97730 6074 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6075 addr = 0;
05394f39 6076 obj = NULL;
5004417d 6077 mutex_lock(&dev->struct_mutex);
3f8bc370 6078 goto finish;
79e53945
JB		 6079 }
6080
6081 /* Currently we only support 64x64 cursors */
6082 if (width != 64 || height != 64) {
6083 DRM_ERROR("we currently only support 64x64 cursors\n");
6084 return -EINVAL;
6085 }
6086
05394f39 6087 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6088 if (&obj->base == NULL)
79e53945
JB		 6089 return -ENOENT;
6090
05394f39 6091 if (obj->base.size < width * height * 4) {
79e53945 6092 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6093 ret = -ENOMEM;
6094 goto fail;
79e53945
JB		 6095 }
6096
71acb5eb 6097 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6098 mutex_lock(&dev->struct_mutex);
b295d1b6 6099 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6100 if (obj->tiling_mode) {
6101 DRM_ERROR("cursor cannot be tiled\n");
6102 ret = -EINVAL;
6103 goto fail_locked;
6104 }
6105
2da3b9b9 6106 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6107 if (ret) {
6108 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6109 goto fail_locked;
e7b526bb
CW		 6110 }
6111
d9e86c0e
CW		 6112 ret = i915_gem_object_put_fence(obj);
6113 if (ret) {
2da3b9b9 6114 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6115 goto fail_unpin;
6116 }
6117
05394f39 6118 addr = obj->gtt_offset;
71acb5eb 6119 } else {
6eeefaf3 6120 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6121 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6122 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6123 align);
71acb5eb
DA		 6124 if (ret) {
6125 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6126 goto fail_locked;
71acb5eb 6127 }
05394f39 6128 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6129 }
6130
a6c45cf0 6131 if (IS_GEN2(dev))
14b60391
JB		 6132 I915_WRITE(CURSIZE, (height << 12) | width);
6133
3f8bc370 6134 finish:
3f8bc370 6135 if (intel_crtc->cursor_bo) {
b295d1b6 6136 if (dev_priv->info->cursor_needs_physical) {
05394f39 6137 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6138 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6139 } else
6140 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6141 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6142 }
80824003 6143
7f9872e0 6144 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6145
6146 intel_crtc->cursor_addr = addr;
05394f39 6147 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6148 intel_crtc->cursor_width = width;
6149 intel_crtc->cursor_height = height;
6150
6b383a7f 6151 intel_crtc_update_cursor(crtc, true);
3f8bc370 6152
79e53945 6153 return 0;
e7b526bb 6154fail_unpin:
05394f39 6155 i915_gem_object_unpin(obj);
7f9872e0 6156fail_locked:
34b8686e 6157 mutex_unlock(&dev->struct_mutex);
bc9025bd 6158fail:
05394f39 6159 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6160 return ret;
79e53945
JB		 6161}
6162
6163static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6164{
79e53945 6165 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6166
cda4b7d3
CW		 6167 intel_crtc->cursor_x = x;
6168 intel_crtc->cursor_y = y;
652c393a 6169
6b383a7f 6170 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6171
6172 return 0;
6173}
6174
6175/** Sets the color ramps on behalf of RandR */
6176void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6177 u16 blue, int regno)
6178{
6179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6180
6181 intel_crtc->lut_r[regno] = red >> 8;
6182 intel_crtc->lut_g[regno] = green >> 8;
6183 intel_crtc->lut_b[regno] = blue >> 8;
6184}
6185
b8c00ac5
DA		 6186void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6187 u16 *blue, int regno)
6188{
6189 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6190
6191 *red = intel_crtc->lut_r[regno] << 8;
6192 *green = intel_crtc->lut_g[regno] << 8;
6193 *blue = intel_crtc->lut_b[regno] << 8;
6194}
6195
79e53945 6196static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6197 u16 *blue, uint32_t start, uint32_t size)
79e53945 6198{
7203425a 6199 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6200 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6201
7203425a 6202 for (i = start; i < end; i++) {
79e53945
JB		 6203 intel_crtc->lut_r[i] = red[i] >> 8;
6204 intel_crtc->lut_g[i] = green[i] >> 8;
6205 intel_crtc->lut_b[i] = blue[i] >> 8;
6206 }
6207
6208 intel_crtc_load_lut(crtc);
6209}
6210
6211/**
6212 * Get a pipe with a simple mode set on it for doing load-based monitor
6213 * detection.
6214 *
6215 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6216 * its requirements. The pipe will be connected to no other encoders.
79e53945 6217 *
c751ce4f 6218 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6219 * configured for it. In the future, it could choose to temporarily disable
6220 * some outputs to free up a pipe for its use.
6221 *
6222 * \return crtc, or NULL if no pipes are available.
6223 */
6224
6225/* VESA 640x480x72Hz mode to set on the pipe */
6226static struct drm_display_mode load_detect_mode = {
6227 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6228 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6229};
6230
d2dff872
CW		 6231static struct drm_framebuffer *
6232intel_framebuffer_create(struct drm_device *dev,
6233 struct drm_mode_fb_cmd *mode_cmd,
6234 struct drm_i915_gem_object *obj)
6235{
6236 struct intel_framebuffer *intel_fb;
6237 int ret;
6238
6239 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6240 if (!intel_fb) {
6241 drm_gem_object_unreference_unlocked(&obj->base);
6242 return ERR_PTR(-ENOMEM);
6243 }
6244
6245 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6246 if (ret) {
6247 drm_gem_object_unreference_unlocked(&obj->base);
6248 kfree(intel_fb);
6249 return ERR_PTR(ret);
6250 }
6251
6252 return &intel_fb->base;
6253}
6254
6255static u32
6256intel_framebuffer_pitch_for_width(int width, int bpp)
6257{
6258 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6259 return ALIGN(pitch, 64);
6260}
6261
6262static u32
6263intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6264{
6265 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6266 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6267}
6268
6269static struct drm_framebuffer *
6270intel_framebuffer_create_for_mode(struct drm_device *dev,
6271 struct drm_display_mode *mode,
6272 int depth, int bpp)
6273{
6274 struct drm_i915_gem_object *obj;
6275 struct drm_mode_fb_cmd mode_cmd;
6276
6277 obj = i915_gem_alloc_object(dev,
6278 intel_framebuffer_size_for_mode(mode, bpp));
6279 if (obj == NULL)
6280 return ERR_PTR(-ENOMEM);
6281
6282 mode_cmd.width = mode->hdisplay;
6283 mode_cmd.height = mode->vdisplay;
6284 mode_cmd.depth = depth;
6285 mode_cmd.bpp = bpp;
6286 mode_cmd.pitch = intel_framebuffer_pitch_for_width(mode_cmd.width, bpp);
6287
6288 return intel_framebuffer_create(dev, &mode_cmd, obj);
6289}
6290
6291static struct drm_framebuffer *
6292mode_fits_in_fbdev(struct drm_device *dev,
6293 struct drm_display_mode *mode)
6294{
6295 struct drm_i915_private *dev_priv = dev->dev_private;
6296 struct drm_i915_gem_object *obj;
6297 struct drm_framebuffer *fb;
6298
6299 if (dev_priv->fbdev == NULL)
6300 return NULL;
6301
6302 obj = dev_priv->fbdev->ifb.obj;
6303 if (obj == NULL)
6304 return NULL;
6305
6306 fb = &dev_priv->fbdev->ifb.base;
6307 if (fb->pitch < intel_framebuffer_pitch_for_width(mode->hdisplay,
6308 fb->bits_per_pixel))
6309 return NULL;
6310
6311 if (obj->base.size < mode->vdisplay * fb->pitch)
6312 return NULL;
6313
6314 return fb;
6315}
6316
7173188d
CW		 6317bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6318 struct drm_connector *connector,
6319 struct drm_display_mode *mode,
8261b191 6320 struct intel_load_detect_pipe *old)
79e53945
JB		 6321{
6322 struct intel_crtc *intel_crtc;
6323 struct drm_crtc *possible_crtc;
4ef69c7a 6324 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6325 struct drm_crtc *crtc = NULL;
6326 struct drm_device *dev = encoder->dev;
d2dff872 6327 struct drm_framebuffer *old_fb;
79e53945
JB		 6328 int i = -1;
6329
d2dff872
CW		 6330 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6331 connector->base.id, drm_get_connector_name(connector),
6332 encoder->base.id, drm_get_encoder_name(encoder));
6333
79e53945
JB		 6334 /*
6335 * Algorithm gets a little messy:
7a5e4805 6336 *
79e53945
JB		 6337 * - if the connector already has an assigned crtc, use it (but make
6338 * sure it's on first)
7a5e4805 6339 *
79e53945
JB		 6340 * - try to find the first unused crtc that can drive this connector,
6341 * and use that if we find one
79e53945
JB		 6342 */
6343
6344 /* See if we already have a CRTC for this connector */
6345 if (encoder->crtc) {
6346 crtc = encoder->crtc;
8261b191 6347
79e53945 6348 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6349 old->dpms_mode = intel_crtc->dpms_mode;
6350 old->load_detect_temp = false;
6351
6352 /* Make sure the crtc and connector are running */
79e53945 6353 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 6354 struct drm_encoder_helper_funcs *encoder_funcs;
6355 struct drm_crtc_helper_funcs *crtc_funcs;
6356
79e53945
JB		 6357 crtc_funcs = crtc->helper_private;
6358 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 6359
6360 encoder_funcs = encoder->helper_private;
79e53945
JB		 6361 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6362 }
8261b191 6363
7173188d 6364 return true;
79e53945
JB		 6365 }
6366
6367 /* Find an unused one (if possible) */
6368 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6369 i++;
6370 if (!(encoder->possible_crtcs & (1 << i)))
6371 continue;
6372 if (!possible_crtc->enabled) {
6373 crtc = possible_crtc;
6374 break;
6375 }
79e53945
JB		 6376 }
6377
6378 /*
6379 * If we didn't find an unused CRTC, don't use any.
6380 */
6381 if (!crtc) {
7173188d
CW		 6382 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6383 return false;
79e53945
JB		 6384 }
6385
6386 encoder->crtc = crtc;
c1c43977 6387 connector->encoder = encoder;
79e53945
JB		 6388
6389 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6390 old->dpms_mode = intel_crtc->dpms_mode;
6391 old->load_detect_temp = true;
d2dff872 6392 old->release_fb = NULL;
79e53945 6393
6492711d
CW		 6394 if (!mode)
6395 mode = &load_detect_mode;
79e53945 6396
d2dff872
CW		 6397 old_fb = crtc->fb;
6398
6399 /* We need a framebuffer large enough to accommodate all accesses
6400 * that the plane may generate whilst we perform load detection.
6401 * We can not rely on the fbcon either being present (we get called
6402 * during its initialisation to detect all boot displays, or it may
6403 * not even exist) or that it is large enough to satisfy the
6404 * requested mode.
6405 */
6406 crtc->fb = mode_fits_in_fbdev(dev, mode);
6407 if (crtc->fb == NULL) {
6408 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6409 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6410 old->release_fb = crtc->fb;
6411 } else
6412 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6413 if (IS_ERR(crtc->fb)) {
6414 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6415 crtc->fb = old_fb;
6416 return false;
79e53945 6417 }
79e53945 6418
d2dff872 6419 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 6420 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6421 if (old->release_fb)
6422 old->release_fb->funcs->destroy(old->release_fb);
6423 crtc->fb = old_fb;
6492711d 6424 return false;
79e53945 6425 }
7173188d 6426
79e53945 6427 /* let the connector get through one full cycle before testing */
9d0498a2 6428 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6429
7173188d 6430 return true;
79e53945
JB		 6431}
6432
c1c43977 6433void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 6434 struct drm_connector *connector,
6435 struct intel_load_detect_pipe *old)
79e53945 6436{
4ef69c7a 6437 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6438 struct drm_device *dev = encoder->dev;
6439 struct drm_crtc *crtc = encoder->crtc;
6440 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6441 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6442
d2dff872
CW		 6443 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6444 connector->base.id, drm_get_connector_name(connector),
6445 encoder->base.id, drm_get_encoder_name(encoder));
6446
8261b191 6447 if (old->load_detect_temp) {
c1c43977 6448 connector->encoder = NULL;
79e53945 6449 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 6450
6451 if (old->release_fb)
6452 old->release_fb->funcs->destroy(old->release_fb);
6453
0622a53c 6454 return;
79e53945
JB		 6455 }
6456
c751ce4f 6457 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 6458 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6459 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 6460 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 6461 }
6462}
6463
6464/* Returns the clock of the currently programmed mode of the given pipe. */
6465static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6466{
6467 struct drm_i915_private *dev_priv = dev->dev_private;
6468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6469 int pipe = intel_crtc->pipe;
548f245b 6470 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6471 u32 fp;
6472 intel_clock_t clock;
6473
6474 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6475 fp = I915_READ(FP0(pipe));
79e53945 6476 else
39adb7a5 6477 fp = I915_READ(FP1(pipe));
79e53945
JB		 6478
6479 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6480 if (IS_PINEVIEW(dev)) {
6481 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6482 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6483 } else {
6484 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6485 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6486 }
6487
a6c45cf0 6488 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6489 if (IS_PINEVIEW(dev))
6490 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6491 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6492 else
6493 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6494 DPLL_FPA01_P1_POST_DIV_SHIFT);
6495
6496 switch (dpll & DPLL_MODE_MASK) {
6497 case DPLLB_MODE_DAC_SERIAL:
6498 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6499 5 : 10;
6500 break;
6501 case DPLLB_MODE_LVDS:
6502 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6503 7 : 14;
6504 break;
6505 default:
28c97730 6506 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6507 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6508 return 0;
6509 }
6510
6511 /* XXX: Handle the 100Mhz refclk */
2177832f 6512 intel_clock(dev, 96000, &clock);
79e53945
JB		 6513 } else {
6514 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6515
6516 if (is_lvds) {
6517 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6518 DPLL_FPA01_P1_POST_DIV_SHIFT);
6519 clock.p2 = 14;
6520
6521 if ((dpll & PLL_REF_INPUT_MASK) ==
6522 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6523 /* XXX: might not be 66MHz */
2177832f 6524 intel_clock(dev, 66000, &clock);
79e53945 6525 } else
2177832f 6526 intel_clock(dev, 48000, &clock);
79e53945
JB		 6527 } else {
6528 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6529 clock.p1 = 2;
6530 else {
6531 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6532 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6533 }
6534 if (dpll & PLL_P2_DIVIDE_BY_4)
6535 clock.p2 = 4;
6536 else
6537 clock.p2 = 2;
6538
2177832f 6539 intel_clock(dev, 48000, &clock);
79e53945
JB		 6540 }
6541 }
6542
6543 /* XXX: It would be nice to validate the clocks, but we can't reuse
6544 * i830PllIsValid() because it relies on the xf86_config connector
6545 * configuration being accurate, which it isn't necessarily.
6546 */
6547
6548 return clock.dot;
6549}
6550
6551/** Returns the currently programmed mode of the given pipe. */
6552struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6553 struct drm_crtc *crtc)
6554{
548f245b 6555 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 6556 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6557 int pipe = intel_crtc->pipe;
6558 struct drm_display_mode *mode;
548f245b
JB		 6559 int htot = I915_READ(HTOTAL(pipe));
6560 int hsync = I915_READ(HSYNC(pipe));
6561 int vtot = I915_READ(VTOTAL(pipe));
6562 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 6563
6564 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6565 if (!mode)
6566 return NULL;
6567
6568 mode->clock = intel_crtc_clock_get(dev, crtc);
6569 mode->hdisplay = (htot & 0xffff) + 1;
6570 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6571 mode->hsync_start = (hsync & 0xffff) + 1;
6572 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6573 mode->vdisplay = (vtot & 0xffff) + 1;
6574 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6575 mode->vsync_start = (vsync & 0xffff) + 1;
6576 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6577
6578 drm_mode_set_name(mode);
6579 drm_mode_set_crtcinfo(mode, 0);
6580
6581 return mode;
6582}
6583
652c393a
JB		 6584#define GPU_IDLE_TIMEOUT 500 /* ms */
6585
6586/* When this timer fires, we've been idle for awhile */
6587static void intel_gpu_idle_timer(unsigned long arg)
6588{
6589 struct drm_device *dev = (struct drm_device *)arg;
6590 drm_i915_private_t *dev_priv = dev->dev_private;
6591
ff7ea4c0
CW		 6592 if (!list_empty(&dev_priv->mm.active_list)) {
6593 /* Still processing requests, so just re-arm the timer. */
6594 mod_timer(&dev_priv->idle_timer, jiffies +
6595 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6596 return;
6597 }
652c393a 6598
ff7ea4c0 6599 dev_priv->busy = false;
01dfba93 6600 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6601}
6602
652c393a
JB		 6603#define CRTC_IDLE_TIMEOUT 1000 /* ms */
6604
6605static void intel_crtc_idle_timer(unsigned long arg)
6606{
6607 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6608 struct drm_crtc *crtc = &intel_crtc->base;
6609 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 6610 struct intel_framebuffer *intel_fb;
652c393a 6611
ff7ea4c0
CW		 6612 intel_fb = to_intel_framebuffer(crtc->fb);
6613 if (intel_fb && intel_fb->obj->active) {
6614 /* The framebuffer is still being accessed by the GPU. */
6615 mod_timer(&intel_crtc->idle_timer, jiffies +
6616 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6617 return;
6618 }
652c393a 6619
ff7ea4c0 6620 intel_crtc->busy = false;
01dfba93 6621 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6622}
6623
3dec0095 6624static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6625{
6626 struct drm_device *dev = crtc->dev;
6627 drm_i915_private_t *dev_priv = dev->dev_private;
6628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6629 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6630 int dpll_reg = DPLL(pipe);
6631 int dpll;
652c393a 6632
bad720ff 6633 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6634 return;
6635
6636 if (!dev_priv->lvds_downclock_avail)
6637 return;
6638
dbdc6479 6639 dpll = I915_READ(dpll_reg);
652c393a 6640 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6641 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a
JB		 6642
6643 /* Unlock panel regs */
dbdc6479
JB		 6644 I915_WRITE(PP_CONTROL,
6645 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
652c393a
JB		 6646
6647 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6648 I915_WRITE(dpll_reg, dpll);
9d0498a2 6649 intel_wait_for_vblank(dev, pipe);
dbdc6479 6650
652c393a
JB		 6651 dpll = I915_READ(dpll_reg);
6652 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6653 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 6654
6655 /* ...and lock them again */
6656 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6657 }
6658
6659 /* Schedule downclock */
3dec0095
DV		 6660 mod_timer(&intel_crtc->idle_timer, jiffies +
6661 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 6662}
6663
6664static void intel_decrease_pllclock(struct drm_crtc *crtc)
6665{
6666 struct drm_device *dev = crtc->dev;
6667 drm_i915_private_t *dev_priv = dev->dev_private;
6668 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6669 int pipe = intel_crtc->pipe;
9db4a9c7 6670 int dpll_reg = DPLL(pipe);
652c393a
JB		 6671 int dpll = I915_READ(dpll_reg);
6672
bad720ff 6673 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6674 return;
6675
6676 if (!dev_priv->lvds_downclock_avail)
6677 return;
6678
6679 /*
6680 * Since this is called by a timer, we should never get here in
6681 * the manual case.
6682 */
6683 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 6684 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a
JB		 6685
6686 /* Unlock panel regs */
4a655f04
JB		 6687 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6688 PANEL_UNLOCK_REGS);
652c393a
JB		 6689
6690 dpll |= DISPLAY_RATE_SELECT_FPA1;
6691 I915_WRITE(dpll_reg, dpll);
9d0498a2 6692 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6693 dpll = I915_READ(dpll_reg);
6694 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6695 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6696
6697 /* ...and lock them again */
6698 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6699 }
6700
6701}
6702
6703/**
6704 * intel_idle_update - adjust clocks for idleness
6705 * @work: work struct
6706 *
6707 * Either the GPU or display (or both) went idle. Check the busy status
6708 * here and adjust the CRTC and GPU clocks as necessary.
6709 */
6710static void intel_idle_update(struct work_struct *work)
6711{
6712 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6713 idle_work);
6714 struct drm_device *dev = dev_priv->dev;
6715 struct drm_crtc *crtc;
6716 struct intel_crtc *intel_crtc;
6717
6718 if (!i915_powersave)
6719 return;
6720
6721 mutex_lock(&dev->struct_mutex);
6722
7648fa99
JB		 6723 i915_update_gfx_val(dev_priv);
6724
652c393a
JB		 6725 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6726 /* Skip inactive CRTCs */
6727 if (!crtc->fb)
6728 continue;
6729
6730 intel_crtc = to_intel_crtc(crtc);
6731 if (!intel_crtc->busy)
6732 intel_decrease_pllclock(crtc);
6733 }
6734
45ac22c8 6735
652c393a
JB		 6736 mutex_unlock(&dev->struct_mutex);
6737}
6738
6739/**
6740 * intel_mark_busy - mark the GPU and possibly the display busy
6741 * @dev: drm device
6742 * @obj: object we're operating on
6743 *
6744 * Callers can use this function to indicate that the GPU is busy processing
6745 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6746 * buffer), we'll also mark the display as busy, so we know to increase its
6747 * clock frequency.
6748 */
05394f39 6749void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 6750{
6751 drm_i915_private_t *dev_priv = dev->dev_private;
6752 struct drm_crtc *crtc = NULL;
6753 struct intel_framebuffer *intel_fb;
6754 struct intel_crtc *intel_crtc;
6755
5e17ee74
ZW		 6756 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6757 return;
6758
18b2190c 6759 if (!dev_priv->busy)
28cf798f 6760 dev_priv->busy = true;
18b2190c 6761 else
28cf798f
CW		 6762 mod_timer(&dev_priv->idle_timer, jiffies +
6763 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 6764
6765 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6766 if (!crtc->fb)
6767 continue;
6768
6769 intel_crtc = to_intel_crtc(crtc);
6770 intel_fb = to_intel_framebuffer(crtc->fb);
6771 if (intel_fb->obj == obj) {
6772 if (!intel_crtc->busy) {
6773 /* Non-busy -> busy, upclock */
3dec0095 6774 intel_increase_pllclock(crtc);
652c393a
JB		 6775 intel_crtc->busy = true;
6776 } else {
6777 /* Busy -> busy, put off timer */
6778 mod_timer(&intel_crtc->idle_timer, jiffies +
6779 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6780 }
6781 }
6782 }
6783}
6784
79e53945
JB		 6785static void intel_crtc_destroy(struct drm_crtc *crtc)
6786{
6787 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6788 struct drm_device *dev = crtc->dev;
6789 struct intel_unpin_work *work;
6790 unsigned long flags;
6791
6792 spin_lock_irqsave(&dev->event_lock, flags);
6793 work = intel_crtc->unpin_work;
6794 intel_crtc->unpin_work = NULL;
6795 spin_unlock_irqrestore(&dev->event_lock, flags);
6796
6797 if (work) {
6798 cancel_work_sync(&work->work);
6799 kfree(work);
6800 }
79e53945
JB		 6801
6802 drm_crtc_cleanup(crtc);
67e77c5a 6803
79e53945
JB		 6804 kfree(intel_crtc);
6805}
6806
6b95a207
KH		 6807static void intel_unpin_work_fn(struct work_struct *__work)
6808{
6809 struct intel_unpin_work *work =
6810 container_of(__work, struct intel_unpin_work, work);
6811
6812 mutex_lock(&work->dev->struct_mutex);
b1b87f6b 6813 i915_gem_object_unpin(work->old_fb_obj);
05394f39
CW		 6814 drm_gem_object_unreference(&work->pending_flip_obj->base);
6815 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6816
7782de3b 6817 intel_update_fbc(work->dev);
6b95a207
KH		 6818 mutex_unlock(&work->dev->struct_mutex);
6819 kfree(work);
6820}
6821
1afe3e9d 6822static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6823 struct drm_crtc *crtc)
6b95a207
KH		 6824{
6825 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6827 struct intel_unpin_work *work;
05394f39 6828 struct drm_i915_gem_object *obj;
6b95a207 6829 struct drm_pending_vblank_event *e;
49b14a5c 6830 struct timeval tnow, tvbl;
6b95a207
KH		 6831 unsigned long flags;
6832
6833 /* Ignore early vblank irqs */
6834 if (intel_crtc == NULL)
6835 return;
6836
49b14a5c
MK		 6837 do_gettimeofday(&tnow);
6838
6b95a207
KH		 6839 spin_lock_irqsave(&dev->event_lock, flags);
6840 work = intel_crtc->unpin_work;
6841 if (work == NULL || !work->pending) {
6842 spin_unlock_irqrestore(&dev->event_lock, flags);
6843 return;
6844 }
6845
6846 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6847
6848 if (work->event) {
6849 e = work->event;
49b14a5c 6850 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6851
6852 /* Called before vblank count and timestamps have
6853 * been updated for the vblank interval of flip
6854 * completion? Need to increment vblank count and
6855 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6856 * to account for this. We assume this happened if we
6857 * get called over 0.9 frame durations after the last
6858 * timestamped vblank.
6859 *
6860 * This calculation can not be used with vrefresh rates
6861 * below 5Hz (10Hz to be on the safe side) without
6862 * promoting to 64 integers.
0af7e4df 6863 */
49b14a5c
MK		 6864 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6865 9 * crtc->framedur_ns) {
0af7e4df 6866 e->event.sequence++;
49b14a5c
MK		 6867 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6868 crtc->framedur_ns);
0af7e4df
MK		 6869 }
6870
49b14a5c
MK		 6871 e->event.tv_sec = tvbl.tv_sec;
6872 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6873
6b95a207
KH		 6874 list_add_tail(&e->base.link,
6875 &e->base.file_priv->event_list);
6876 wake_up_interruptible(&e->base.file_priv->event_wait);
6877 }
6878
0af7e4df
MK		 6879 drm_vblank_put(dev, intel_crtc->pipe);
6880
6b95a207
KH		 6881 spin_unlock_irqrestore(&dev->event_lock, flags);
6882
05394f39 6883 obj = work->old_fb_obj;
d9e86c0e 6884
e59f2bac 6885 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6886 &obj->pending_flip.counter);
6887 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6888 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6889
6b95a207 6890 schedule_work(&work->work);
e5510fac
JB		 6891
6892 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6893}
6894
1afe3e9d
JB		 6895void intel_finish_page_flip(struct drm_device *dev, int pipe)
6896{
6897 drm_i915_private_t *dev_priv = dev->dev_private;
6898 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6899
49b14a5c 6900 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6901}
6902
6903void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6904{
6905 drm_i915_private_t *dev_priv = dev->dev_private;
6906 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6907
49b14a5c 6908 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6909}
6910
6b95a207
KH		 6911void intel_prepare_page_flip(struct drm_device *dev, int plane)
6912{
6913 drm_i915_private_t *dev_priv = dev->dev_private;
6914 struct intel_crtc *intel_crtc =
6915 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6916 unsigned long flags;
6917
6918 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6919 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6920 if ((++intel_crtc->unpin_work->pending) > 1)
6921 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6922 } else {
6923 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6924 }
6b95a207
KH		 6925 spin_unlock_irqrestore(&dev->event_lock, flags);
6926}
6927
8c9f3aaf
JB		 6928static int intel_gen2_queue_flip(struct drm_device *dev,
6929 struct drm_crtc *crtc,
6930 struct drm_framebuffer *fb,
6931 struct drm_i915_gem_object *obj)
6932{
6933 struct drm_i915_private *dev_priv = dev->dev_private;
6934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6935 unsigned long offset;
6936 u32 flip_mask;
6937 int ret;
6938
6939 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6940 if (ret)
6941 goto out;
6942
6943 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6944 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6945
6946 ret = BEGIN_LP_RING(6);
6947 if (ret)
6948 goto out;
6949
6950 /* Can't queue multiple flips, so wait for the previous
6951 * one to finish before executing the next.
6952 */
6953 if (intel_crtc->plane)
6954 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6955 else
6956 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6957 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6958 OUT_RING(MI_NOOP);
6959 OUT_RING(MI_DISPLAY_FLIP |
6960 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6961 OUT_RING(fb->pitch);
6962 OUT_RING(obj->gtt_offset + offset);
6963 OUT_RING(MI_NOOP);
6964 ADVANCE_LP_RING();
6965out:
6966 return ret;
6967}
6968
6969static int intel_gen3_queue_flip(struct drm_device *dev,
6970 struct drm_crtc *crtc,
6971 struct drm_framebuffer *fb,
6972 struct drm_i915_gem_object *obj)
6973{
6974 struct drm_i915_private *dev_priv = dev->dev_private;
6975 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6976 unsigned long offset;
6977 u32 flip_mask;
6978 int ret;
6979
6980 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
6981 if (ret)
6982 goto out;
6983
6984 /* Offset into the new buffer for cases of shared fbs between CRTCs */
6985 offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
6986
6987 ret = BEGIN_LP_RING(6);
6988 if (ret)
6989 goto out;
6990
6991 if (intel_crtc->plane)
6992 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6993 else
6994 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6995 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
6996 OUT_RING(MI_NOOP);
6997 OUT_RING(MI_DISPLAY_FLIP_I915 |
6998 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6999 OUT_RING(fb->pitch);
7000 OUT_RING(obj->gtt_offset + offset);
7001 OUT_RING(MI_NOOP);
7002
7003 ADVANCE_LP_RING();
7004out:
7005 return ret;
7006}
7007
7008static int intel_gen4_queue_flip(struct drm_device *dev,
7009 struct drm_crtc *crtc,
7010 struct drm_framebuffer *fb,
7011 struct drm_i915_gem_object *obj)
7012{
7013 struct drm_i915_private *dev_priv = dev->dev_private;
7014 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7015 uint32_t pf, pipesrc;
7016 int ret;
7017
7018 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7019 if (ret)
7020 goto out;
7021
7022 ret = BEGIN_LP_RING(4);
7023 if (ret)
7024 goto out;
7025
7026 /* i965+ uses the linear or tiled offsets from the
7027 * Display Registers (which do not change across a page-flip)
7028 * so we need only reprogram the base address.
7029 */
7030 OUT_RING(MI_DISPLAY_FLIP |
7031 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7032 OUT_RING(fb->pitch);
7033 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7034
7035 /* XXX Enabling the panel-fitter across page-flip is so far
7036 * untested on non-native modes, so ignore it for now.
7037 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7038 */
7039 pf = 0;
7040 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7041 OUT_RING(pf | pipesrc);
7042 ADVANCE_LP_RING();
7043out:
7044 return ret;
7045}
7046
7047static int intel_gen6_queue_flip(struct drm_device *dev,
7048 struct drm_crtc *crtc,
7049 struct drm_framebuffer *fb,
7050 struct drm_i915_gem_object *obj)
7051{
7052 struct drm_i915_private *dev_priv = dev->dev_private;
7053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7054 uint32_t pf, pipesrc;
7055 int ret;
7056
7057 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7058 if (ret)
7059 goto out;
7060
7061 ret = BEGIN_LP_RING(4);
7062 if (ret)
7063 goto out;
7064
7065 OUT_RING(MI_DISPLAY_FLIP |
7066 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7067 OUT_RING(fb->pitch | obj->tiling_mode);
7068 OUT_RING(obj->gtt_offset);
7069
7070 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7071 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7072 OUT_RING(pf | pipesrc);
7073 ADVANCE_LP_RING();
7074out:
7075 return ret;
7076}
7077
7c9017e5
JB		 7078/*
7079 * On gen7 we currently use the blit ring because (in early silicon at least)
7080 * the render ring doesn't give us interrpts for page flip completion, which
7081 * means clients will hang after the first flip is queued. Fortunately the
7082 * blit ring generates interrupts properly, so use it instead.
7083 */
7084static int intel_gen7_queue_flip(struct drm_device *dev,
7085 struct drm_crtc *crtc,
7086 struct drm_framebuffer *fb,
7087 struct drm_i915_gem_object *obj)
7088{
7089 struct drm_i915_private *dev_priv = dev->dev_private;
7090 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7091 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7092 int ret;
7093
7094 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7095 if (ret)
7096 goto out;
7097
7098 ret = intel_ring_begin(ring, 4);
7099 if (ret)
7100 goto out;
7101
7102 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
7103 intel_ring_emit(ring, (fb->pitch | obj->tiling_mode));
7104 intel_ring_emit(ring, (obj->gtt_offset));
7105 intel_ring_emit(ring, (MI_NOOP));
7106 intel_ring_advance(ring);
7107out:
7108 return ret;
7109}
7110
8c9f3aaf
JB		 7111static int intel_default_queue_flip(struct drm_device *dev,
7112 struct drm_crtc *crtc,
7113 struct drm_framebuffer *fb,
7114 struct drm_i915_gem_object *obj)
7115{
7116 return -ENODEV;
7117}
7118
6b95a207
KH		 7119static int intel_crtc_page_flip(struct drm_crtc *crtc,
7120 struct drm_framebuffer *fb,
7121 struct drm_pending_vblank_event *event)
7122{
7123 struct drm_device *dev = crtc->dev;
7124 struct drm_i915_private *dev_priv = dev->dev_private;
7125 struct intel_framebuffer *intel_fb;
05394f39 7126 struct drm_i915_gem_object *obj;
6b95a207
KH		 7127 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7128 struct intel_unpin_work *work;
8c9f3aaf 7129 unsigned long flags;
52e68630 7130 int ret;
6b95a207
KH		 7131
7132 work = kzalloc(sizeof *work, GFP_KERNEL);
7133 if (work == NULL)
7134 return -ENOMEM;
7135
6b95a207
KH		 7136 work->event = event;
7137 work->dev = crtc->dev;
7138 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7139 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7140 INIT_WORK(&work->work, intel_unpin_work_fn);
7141
7142 /* We borrow the event spin lock for protecting unpin_work */
7143 spin_lock_irqsave(&dev->event_lock, flags);
7144 if (intel_crtc->unpin_work) {
7145 spin_unlock_irqrestore(&dev->event_lock, flags);
7146 kfree(work);
468f0b44
CW		 7147
7148 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7149 return -EBUSY;
7150 }
7151 intel_crtc->unpin_work = work;
7152 spin_unlock_irqrestore(&dev->event_lock, flags);
7153
7154 intel_fb = to_intel_framebuffer(fb);
7155 obj = intel_fb->obj;
7156
468f0b44 7157 mutex_lock(&dev->struct_mutex);
6b95a207 7158
75dfca80 7159 /* Reference the objects for the scheduled work. */
05394f39
CW		 7160 drm_gem_object_reference(&work->old_fb_obj->base);
7161 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7162
7163 crtc->fb = fb;
96b099fd
CW		 7164
7165 ret = drm_vblank_get(dev, intel_crtc->pipe);
7166 if (ret)
7167 goto cleanup_objs;
7168
e1f99ce6 7169 work->pending_flip_obj = obj;
e1f99ce6 7170
4e5359cd
SF		 7171 work->enable_stall_check = true;
7172
e1f99ce6
CW		 7173 /* Block clients from rendering to the new back buffer until
7174 * the flip occurs and the object is no longer visible.
7175 */
05394f39 7176 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 7177
8c9f3aaf
JB		 7178 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7179 if (ret)
7180 goto cleanup_pending;
6b95a207 7181
7782de3b 7182 intel_disable_fbc(dev);
6b95a207
KH		 7183 mutex_unlock(&dev->struct_mutex);
7184
e5510fac
JB		 7185 trace_i915_flip_request(intel_crtc->plane, obj);
7186
6b95a207 7187 return 0;
96b099fd 7188
8c9f3aaf
JB		 7189cleanup_pending:
7190 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
96b099fd 7191cleanup_objs:
05394f39
CW		 7192 drm_gem_object_unreference(&work->old_fb_obj->base);
7193 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7194 mutex_unlock(&dev->struct_mutex);
7195
7196 spin_lock_irqsave(&dev->event_lock, flags);
7197 intel_crtc->unpin_work = NULL;
7198 spin_unlock_irqrestore(&dev->event_lock, flags);
7199
7200 kfree(work);
7201
7202 return ret;
6b95a207
KH		 7203}
7204
47f1c6c9
CW		 7205static void intel_sanitize_modesetting(struct drm_device *dev,
7206 int pipe, int plane)
7207{
7208 struct drm_i915_private *dev_priv = dev->dev_private;
7209 u32 reg, val;
7210
7211 if (HAS_PCH_SPLIT(dev))
7212 return;
7213
7214 /* Who knows what state these registers were left in by the BIOS or
7215 * grub?
7216 *
7217 * If we leave the registers in a conflicting state (e.g. with the
7218 * display plane reading from the other pipe than the one we intend
7219 * to use) then when we attempt to teardown the active mode, we will
7220 * not disable the pipes and planes in the correct order -- leaving
7221 * a plane reading from a disabled pipe and possibly leading to
7222 * undefined behaviour.
7223 */
7224
7225 reg = DSPCNTR(plane);
7226 val = I915_READ(reg);
7227
7228 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7229 return;
7230 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7231 return;
7232
7233 /* This display plane is active and attached to the other CPU pipe. */
7234 pipe = !pipe;
7235
7236 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 7237 intel_disable_plane(dev_priv, plane, pipe);
7238 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 7239}
79e53945 7240
f6e5b160
CW		 7241static void intel_crtc_reset(struct drm_crtc *crtc)
7242{
7243 struct drm_device *dev = crtc->dev;
7244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7245
7246 /* Reset flags back to the 'unknown' status so that they
7247 * will be correctly set on the initial modeset.
7248 */
7249 intel_crtc->dpms_mode = -1;
7250
7251 /* We need to fix up any BIOS configuration that conflicts with
7252 * our expectations.
7253 */
7254 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7255}
7256
7257static struct drm_crtc_helper_funcs intel_helper_funcs = {
7258 .dpms = intel_crtc_dpms,
7259 .mode_fixup = intel_crtc_mode_fixup,
7260 .mode_set = intel_crtc_mode_set,
7261 .mode_set_base = intel_pipe_set_base,
7262 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7263 .load_lut = intel_crtc_load_lut,
7264 .disable = intel_crtc_disable,
7265};
7266
7267static const struct drm_crtc_funcs intel_crtc_funcs = {
7268 .reset = intel_crtc_reset,
7269 .cursor_set = intel_crtc_cursor_set,
7270 .cursor_move = intel_crtc_cursor_move,
7271 .gamma_set = intel_crtc_gamma_set,
7272 .set_config = drm_crtc_helper_set_config,
7273 .destroy = intel_crtc_destroy,
7274 .page_flip = intel_crtc_page_flip,
7275};
7276
b358d0a6 7277static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 7278{
22fd0fab 7279 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 7280 struct intel_crtc *intel_crtc;
7281 int i;
7282
7283 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7284 if (intel_crtc == NULL)
7285 return;
7286
7287 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7288
7289 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7290 for (i = 0; i < 256; i++) {
7291 intel_crtc->lut_r[i] = i;
7292 intel_crtc->lut_g[i] = i;
7293 intel_crtc->lut_b[i] = i;
7294 }
7295
80824003
JB		 7296 /* Swap pipes & planes for FBC on pre-965 */
7297 intel_crtc->pipe = pipe;
7298 intel_crtc->plane = pipe;
e2e767ab 7299 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7300 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7301 intel_crtc->plane = !pipe;
80824003
JB		 7302 }
7303
22fd0fab
JB		 7304 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7305 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7306 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7307 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7308
5d1d0cc8 7309 intel_crtc_reset(&intel_crtc->base);
04dbff52 7310 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 7311 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 7312
7313 if (HAS_PCH_SPLIT(dev)) {
4b645f14
JB		 7314 if (pipe == 2 && IS_IVYBRIDGE(dev))
7315 intel_crtc->no_pll = true;
7e7d76c3
JB		 7316 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7317 intel_helper_funcs.commit = ironlake_crtc_commit;
7318 } else {
7319 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7320 intel_helper_funcs.commit = i9xx_crtc_commit;
7321 }
7322
79e53945
JB		 7323 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7324
652c393a
JB		 7325 intel_crtc->busy = false;
7326
7327 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7328 (unsigned long)intel_crtc);
79e53945
JB		 7329}
7330
08d7b3d1 7331int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7332 struct drm_file *file)
08d7b3d1
CW		 7333{
7334 drm_i915_private_t *dev_priv = dev->dev_private;
7335 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 7336 struct drm_mode_object *drmmode_obj;
7337 struct intel_crtc *crtc;
08d7b3d1
CW		 7338
7339 if (!dev_priv) {
7340 DRM_ERROR("called with no initialization\n");
7341 return -EINVAL;
7342 }
7343
c05422d5
DV		 7344 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7345 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7346
c05422d5 7347 if (!drmmode_obj) {
08d7b3d1
CW		 7348 DRM_ERROR("no such CRTC id\n");
7349 return -EINVAL;
7350 }
7351
c05422d5
DV		 7352 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7353 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7354
c05422d5 7355 return 0;
08d7b3d1
CW		 7356}
7357
c5e4df33 7358static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 7359{
4ef69c7a 7360 struct intel_encoder *encoder;
79e53945 7361 int index_mask = 0;
79e53945
JB		 7362 int entry = 0;
7363
4ef69c7a
CW		 7364 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7365 if (type_mask & encoder->clone_mask)
79e53945
JB		 7366 index_mask |= (1 << entry);
7367 entry++;
7368 }
4ef69c7a 7369
79e53945
JB		 7370 return index_mask;
7371}
7372
4d302442
CW		 7373static bool has_edp_a(struct drm_device *dev)
7374{
7375 struct drm_i915_private *dev_priv = dev->dev_private;
7376
7377 if (!IS_MOBILE(dev))
7378 return false;
7379
7380 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7381 return false;
7382
7383 if (IS_GEN5(dev) &&
7384 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7385 return false;
7386
7387 return true;
7388}
7389
79e53945
JB		 7390static void intel_setup_outputs(struct drm_device *dev)
7391{
725e30ad 7392 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 7393 struct intel_encoder *encoder;
cb0953d7 7394 bool dpd_is_edp = false;
c5d1b51d 7395 bool has_lvds = false;
79e53945 7396
541998a1 7397 if (IS_MOBILE(dev) && !IS_I830(dev))
c5d1b51d
CW		 7398 has_lvds = intel_lvds_init(dev);
7399 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7400 /* disable the panel fitter on everything but LVDS */
7401 I915_WRITE(PFIT_CONTROL, 0);
7402 }
79e53945 7403
bad720ff 7404 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 7405 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 7406
4d302442 7407 if (has_edp_a(dev))
32f9d658
ZW		 7408 intel_dp_init(dev, DP_A);
7409
cb0953d7
AJ		 7410 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7411 intel_dp_init(dev, PCH_DP_D);
7412 }
7413
7414 intel_crt_init(dev);
7415
7416 if (HAS_PCH_SPLIT(dev)) {
7417 int found;
7418
30ad48b7 7419 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca
ZY		 7420 /* PCH SDVOB multiplex with HDMIB */
7421 found = intel_sdvo_init(dev, PCH_SDVOB);
30ad48b7
ZW		 7422 if (!found)
7423 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 7424 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7425 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 7426 }
7427
7428 if (I915_READ(HDMIC) & PORT_DETECTED)
7429 intel_hdmi_init(dev, HDMIC);
7430
7431 if (I915_READ(HDMID) & PORT_DETECTED)
7432 intel_hdmi_init(dev, HDMID);
7433
5eb08b69
ZW		 7434 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7435 intel_dp_init(dev, PCH_DP_C);
7436
cb0953d7 7437 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 7438 intel_dp_init(dev, PCH_DP_D);
7439
103a196f 7440 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 7441 bool found = false;
7d57382e 7442
725e30ad 7443 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 7444 DRM_DEBUG_KMS("probing SDVOB\n");
725e30ad 7445 found = intel_sdvo_init(dev, SDVOB);
b01f2c3a
JB		 7446 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7447 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 7448 intel_hdmi_init(dev, SDVOB);
b01f2c3a 7449 }
27185ae1 7450
b01f2c3a
JB		 7451 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7452 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 7453 intel_dp_init(dev, DP_B);
b01f2c3a 7454 }
725e30ad 7455 }
13520b05
KH		 7456
7457 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 7458
b01f2c3a
JB		 7459 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7460 DRM_DEBUG_KMS("probing SDVOC\n");
725e30ad 7461 found = intel_sdvo_init(dev, SDVOC);
b01f2c3a 7462 }
27185ae1
ML		 7463
7464 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7465
b01f2c3a
JB		 7466 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7467 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 7468 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 7469 }
7470 if (SUPPORTS_INTEGRATED_DP(dev)) {
7471 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 7472 intel_dp_init(dev, DP_C);
b01f2c3a 7473 }
725e30ad 7474 }
27185ae1 7475
b01f2c3a
JB		 7476 if (SUPPORTS_INTEGRATED_DP(dev) &&
7477 (I915_READ(DP_D) & DP_DETECTED)) {
7478 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 7479 intel_dp_init(dev, DP_D);
b01f2c3a 7480 }
bad720ff 7481 } else if (IS_GEN2(dev))
79e53945
JB		 7482 intel_dvo_init(dev);
7483
103a196f 7484 if (SUPPORTS_TV(dev))
79e53945
JB		 7485 intel_tv_init(dev);
7486
4ef69c7a
CW		 7487 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7488 encoder->base.possible_crtcs = encoder->crtc_mask;
7489 encoder->base.possible_clones =
7490 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 7491 }
47356eb6 7492
2c7111db
CW		 7493 /* disable all the possible outputs/crtcs before entering KMS mode */
7494 drm_helper_disable_unused_functions(dev);
9fb526db
KP		 7495
7496 if (HAS_PCH_SPLIT(dev))
7497 ironlake_init_pch_refclk(dev);
79e53945
JB		 7498}
7499
7500static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7501{
7502 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 7503
7504 drm_framebuffer_cleanup(fb);
05394f39 7505 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 7506
7507 kfree(intel_fb);
7508}
7509
7510static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 7511 struct drm_file *file,
79e53945
JB		 7512 unsigned int *handle)
7513{
7514 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 7515 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 7516
05394f39 7517 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 7518}
7519
7520static const struct drm_framebuffer_funcs intel_fb_funcs = {
7521 .destroy = intel_user_framebuffer_destroy,
7522 .create_handle = intel_user_framebuffer_create_handle,
7523};
7524
38651674
DA		 7525int intel_framebuffer_init(struct drm_device *dev,
7526 struct intel_framebuffer *intel_fb,
7527 struct drm_mode_fb_cmd *mode_cmd,
05394f39 7528 struct drm_i915_gem_object *obj)
79e53945 7529{
79e53945
JB		 7530 int ret;
7531
05394f39 7532 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 7533 return -EINVAL;
7534
7535 if (mode_cmd->pitch & 63)
7536 return -EINVAL;
7537
7538 switch (mode_cmd->bpp) {
7539 case 8:
7540 case 16:
b5626747
JB		 7541 /* Only pre-ILK can handle 5:5:5 */
7542 if (mode_cmd->depth == 15 && !HAS_PCH_SPLIT(dev))
7543 return -EINVAL;
7544 break;
7545
57cd6508
CW		 7546 case 24:
7547 case 32:
7548 break;
7549 default:
7550 return -EINVAL;
7551 }
7552
79e53945
JB		 7553 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7554 if (ret) {
7555 DRM_ERROR("framebuffer init failed %d\n", ret);
7556 return ret;
7557 }
7558
7559 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 7560 intel_fb->obj = obj;
79e53945
JB		 7561 return 0;
7562}
7563
79e53945
JB		 7564static struct drm_framebuffer *
7565intel_user_framebuffer_create(struct drm_device *dev,
7566 struct drm_file *filp,
7567 struct drm_mode_fb_cmd *mode_cmd)
7568{
05394f39 7569 struct drm_i915_gem_object *obj;
79e53945 7570
05394f39 7571 obj = to_intel_bo(drm_gem_object_lookup(dev, filp, mode_cmd->handle));
c8725226 7572 if (&obj->base == NULL)
cce13ff7 7573 return ERR_PTR(-ENOENT);
79e53945 7574
d2dff872 7575 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 7576}
7577
79e53945 7578static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 7579 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 7580 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 7581};
7582
05394f39 7583static struct drm_i915_gem_object *
aa40d6bb 7584intel_alloc_context_page(struct drm_device *dev)
9ea8d059 7585{
05394f39 7586 struct drm_i915_gem_object *ctx;
9ea8d059
CW		 7587 int ret;
7588
2c34b850
BW		 7589 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7590
aa40d6bb
ZN		 7591 ctx = i915_gem_alloc_object(dev, 4096);
7592 if (!ctx) {
9ea8d059
CW		 7593 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7594 return NULL;
7595 }
7596
75e9e915 7597 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW		 7598 if (ret) {
7599 DRM_ERROR("failed to pin power context: %d\n", ret);
7600 goto err_unref;
7601 }
7602
aa40d6bb 7603 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW		 7604 if (ret) {
7605 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7606 goto err_unpin;
7607 }
9ea8d059 7608
aa40d6bb 7609 return ctx;
9ea8d059
CW		 7610
7611err_unpin:
aa40d6bb 7612 i915_gem_object_unpin(ctx);
9ea8d059 7613err_unref:
05394f39 7614 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW		 7615 mutex_unlock(&dev->struct_mutex);
7616 return NULL;
7617}
7618
7648fa99
JB		 7619bool ironlake_set_drps(struct drm_device *dev, u8 val)
7620{
7621 struct drm_i915_private *dev_priv = dev->dev_private;
7622 u16 rgvswctl;
7623
7624 rgvswctl = I915_READ16(MEMSWCTL);
7625 if (rgvswctl & MEMCTL_CMD_STS) {
7626 DRM_DEBUG("gpu busy, RCS change rejected\n");
7627 return false; /* still busy with another command */
7628 }
7629
7630 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7631 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7632 I915_WRITE16(MEMSWCTL, rgvswctl);
7633 POSTING_READ16(MEMSWCTL);
7634
7635 rgvswctl |= MEMCTL_CMD_STS;
7636 I915_WRITE16(MEMSWCTL, rgvswctl);
7637
7638 return true;
7639}
7640
f97108d1
JB		 7641void ironlake_enable_drps(struct drm_device *dev)
7642{
7643 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7644 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 7645 u8 fmax, fmin, fstart, vstart;
f97108d1 7646
ea056c14
JB		 7647 /* Enable temp reporting */
7648 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7649 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7650
f97108d1
JB		 7651 /* 100ms RC evaluation intervals */
7652 I915_WRITE(RCUPEI, 100000);
7653 I915_WRITE(RCDNEI, 100000);
7654
7655 /* Set max/min thresholds to 90ms and 80ms respectively */
7656 I915_WRITE(RCBMAXAVG, 90000);
7657 I915_WRITE(RCBMINAVG, 80000);
7658
7659 I915_WRITE(MEMIHYST, 1);
7660
7661 /* Set up min, max, and cur for interrupt handling */
7662 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7663 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7664 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7665 MEMMODE_FSTART_SHIFT;
7648fa99 7666
f97108d1
JB		 7667 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7668 PXVFREQ_PX_SHIFT;
7669
80dbf4b7 7670 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB		 7671 dev_priv->fstart = fstart;
7672
80dbf4b7 7673 dev_priv->max_delay = fstart;
f97108d1
JB		 7674 dev_priv->min_delay = fmin;
7675 dev_priv->cur_delay = fstart;
7676
80dbf4b7
JB		 7677 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7678 fmax, fmin, fstart);
7648fa99 7679
f97108d1
JB		 7680 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7681
7682 /*
7683 * Interrupts will be enabled in ironlake_irq_postinstall
7684 */
7685
7686 I915_WRITE(VIDSTART, vstart);
7687 POSTING_READ(VIDSTART);
7688
7689 rgvmodectl |= MEMMODE_SWMODE_EN;
7690 I915_WRITE(MEMMODECTL, rgvmodectl);
7691
481b6af3 7692 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 7693 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB		 7694 msleep(1);
7695
7648fa99 7696 ironlake_set_drps(dev, fstart);
f97108d1 7697
7648fa99
JB		 7698 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7699 I915_READ(0x112e0);
7700 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7701 dev_priv->last_count2 = I915_READ(0x112f4);
7702 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB		 7703}
7704
7705void ironlake_disable_drps(struct drm_device *dev)
7706{
7707 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7708 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB		 7709
7710 /* Ack interrupts, disable EFC interrupt */
7711 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7712 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7713 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7714 I915_WRITE(DEIIR, DE_PCU_EVENT);
7715 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7716
7717 /* Go back to the starting frequency */
7648fa99 7718 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB		 7719 msleep(1);
7720 rgvswctl |= MEMCTL_CMD_STS;
7721 I915_WRITE(MEMSWCTL, rgvswctl);
7722 msleep(1);
7723
7724}
7725
3b8d8d91
JB		 7726void gen6_set_rps(struct drm_device *dev, u8 val)
7727{
7728 struct drm_i915_private *dev_priv = dev->dev_private;
7729 u32 swreq;
7730
7731 swreq = (val & 0x3ff) << 25;
7732 I915_WRITE(GEN6_RPNSWREQ, swreq);
7733}
7734
7735void gen6_disable_rps(struct drm_device *dev)
7736{
7737 struct drm_i915_private *dev_priv = dev->dev_private;
7738
7739 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
7740 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
7741 I915_WRITE(GEN6_PMIER, 0);
6fdd4d98
DV		 7742 /* Complete PM interrupt masking here doesn't race with the rps work
7743 * item again unmasking PM interrupts because that is using a different
7744 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
7745 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
4912d041
BW		 7746
7747 spin_lock_irq(&dev_priv->rps_lock);
7748 dev_priv->pm_iir = 0;
7749 spin_unlock_irq(&dev_priv->rps_lock);
7750
3b8d8d91
JB		 7751 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
7752}
7753
7648fa99
JB		 7754static unsigned long intel_pxfreq(u32 vidfreq)
7755{
7756 unsigned long freq;
7757 int div = (vidfreq & 0x3f0000) >> 16;
7758 int post = (vidfreq & 0x3000) >> 12;
7759 int pre = (vidfreq & 0x7);
7760
7761 if (!pre)
7762 return 0;
7763
7764 freq = ((div * 133333) / ((1<<post) * pre));
7765
7766 return freq;
7767}
7768
7769void intel_init_emon(struct drm_device *dev)
7770{
7771 struct drm_i915_private *dev_priv = dev->dev_private;
7772 u32 lcfuse;
7773 u8 pxw[16];
7774 int i;
7775
7776 /* Disable to program */
7777 I915_WRITE(ECR, 0);
7778 POSTING_READ(ECR);
7779
7780 /* Program energy weights for various events */
7781 I915_WRITE(SDEW, 0x15040d00);
7782 I915_WRITE(CSIEW0, 0x007f0000);
7783 I915_WRITE(CSIEW1, 0x1e220004);
7784 I915_WRITE(CSIEW2, 0x04000004);
7785
7786 for (i = 0; i < 5; i++)
7787 I915_WRITE(PEW + (i * 4), 0);
7788 for (i = 0; i < 3; i++)
7789 I915_WRITE(DEW + (i * 4), 0);
7790
7791 /* Program P-state weights to account for frequency power adjustment */
7792 for (i = 0; i < 16; i++) {
7793 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
7794 unsigned long freq = intel_pxfreq(pxvidfreq);
7795 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
7796 PXVFREQ_PX_SHIFT;
7797 unsigned long val;
7798
7799 val = vid * vid;
7800 val *= (freq / 1000);
7801 val *= 255;
7802 val /= (127*127*900);
7803 if (val > 0xff)
7804 DRM_ERROR("bad pxval: %ld\n", val);
7805 pxw[i] = val;
7806 }
7807 /* Render standby states get 0 weight */
7808 pxw[14] = 0;
7809 pxw[15] = 0;
7810
7811 for (i = 0; i < 4; i++) {
7812 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
7813 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
7814 I915_WRITE(PXW + (i * 4), val);
7815 }
7816
7817 /* Adjust magic regs to magic values (more experimental results) */
7818 I915_WRITE(OGW0, 0);
7819 I915_WRITE(OGW1, 0);
7820 I915_WRITE(EG0, 0x00007f00);
7821 I915_WRITE(EG1, 0x0000000e);
7822 I915_WRITE(EG2, 0x000e0000);
7823 I915_WRITE(EG3, 0x68000300);
7824 I915_WRITE(EG4, 0x42000000);
7825 I915_WRITE(EG5, 0x00140031);
7826 I915_WRITE(EG6, 0);
7827 I915_WRITE(EG7, 0);
7828
7829 for (i = 0; i < 8; i++)
7830 I915_WRITE(PXWL + (i * 4), 0);
7831
7832 /* Enable PMON + select events */
7833 I915_WRITE(ECR, 0x80000019);
7834
7835 lcfuse = I915_READ(LCFUSE02);
7836
7837 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
7838}
7839
3b8d8d91 7840void gen6_enable_rps(struct drm_i915_private *dev_priv)
8fd26859 7841{
a6044e23
JB		 7842 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
7843 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7df8721b 7844 u32 pcu_mbox, rc6_mask = 0;
a6044e23 7845 int cur_freq, min_freq, max_freq;
8fd26859
CW		 7846 int i;
7847
7848 /* Here begins a magic sequence of register writes to enable
7849 * auto-downclocking.
7850 *
7851 * Perhaps there might be some value in exposing these to
7852 * userspace...
7853 */
7854 I915_WRITE(GEN6_RC_STATE, 0);
d1ebd816 7855 mutex_lock(&dev_priv->dev->struct_mutex);
fcca7926 7856 gen6_gt_force_wake_get(dev_priv);
8fd26859 7857
3b8d8d91 7858 /* disable the counters and set deterministic thresholds */
8fd26859
CW		 7859 I915_WRITE(GEN6_RC_CONTROL, 0);
7860
7861 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
7862 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
7863 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
7864 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
7865 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
7866
7867 for (i = 0; i < I915_NUM_RINGS; i++)
7868 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
7869
7870 I915_WRITE(GEN6_RC_SLEEP, 0);
7871 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
7872 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
7873 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
7874 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
7875
7df8721b
JB		 7876 if (i915_enable_rc6)
7877 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
7878 GEN6_RC_CTL_RC6_ENABLE;
7879
8fd26859 7880 I915_WRITE(GEN6_RC_CONTROL,
7df8721b 7881 rc6_mask |
9c3d2f7f 7882 GEN6_RC_CTL_EI_MODE(1) |
8fd26859
CW		 7883 GEN6_RC_CTL_HW_ENABLE);
7884
3b8d8d91 7885 I915_WRITE(GEN6_RPNSWREQ,
8fd26859
CW		 7886 GEN6_FREQUENCY(10) |
7887 GEN6_OFFSET(0) |
7888 GEN6_AGGRESSIVE_TURBO);
7889 I915_WRITE(GEN6_RC_VIDEO_FREQ,
7890 GEN6_FREQUENCY(12));
7891
7892 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
7893 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
7894 18 << 24 |
7895 6 << 16);
ccab5c82
JB		 7896 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
7897 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8fd26859 7898 I915_WRITE(GEN6_RP_UP_EI, 100000);
ccab5c82 7899 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8fd26859
CW		 7900 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
7901 I915_WRITE(GEN6_RP_CONTROL,
7902 GEN6_RP_MEDIA_TURBO |
7903 GEN6_RP_USE_NORMAL_FREQ |
7904 GEN6_RP_MEDIA_IS_GFX |
7905 GEN6_RP_ENABLE |
ccab5c82
JB		 7906 GEN6_RP_UP_BUSY_AVG |
7907 GEN6_RP_DOWN_IDLE_CONT);
8fd26859
CW		 7908
7909 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7910 500))
7911 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7912
7913 I915_WRITE(GEN6_PCODE_DATA, 0);
7914 I915_WRITE(GEN6_PCODE_MAILBOX,
7915 GEN6_PCODE_READY |
7916 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
7917 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7918 500))
7919 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7920
a6044e23
JB		 7921 min_freq = (rp_state_cap & 0xff0000) >> 16;
7922 max_freq = rp_state_cap & 0xff;
7923 cur_freq = (gt_perf_status & 0xff00) >> 8;
7924
7925 /* Check for overclock support */
7926 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7927 500))
7928 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
7929 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
7930 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
7931 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7932 500))
7933 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
7934 if (pcu_mbox & (1<<31)) { /* OC supported */
7935 max_freq = pcu_mbox & 0xff;
e281fcaa 7936 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
a6044e23
JB		 7937 }
7938
7939 /* In units of 100MHz */
7940 dev_priv->max_delay = max_freq;
7941 dev_priv->min_delay = min_freq;
7942 dev_priv->cur_delay = cur_freq;
7943
8fd26859
CW		 7944 /* requires MSI enabled */
7945 I915_WRITE(GEN6_PMIER,
7946 GEN6_PM_MBOX_EVENT |
7947 GEN6_PM_THERMAL_EVENT |
7948 GEN6_PM_RP_DOWN_TIMEOUT |
7949 GEN6_PM_RP_UP_THRESHOLD |
7950 GEN6_PM_RP_DOWN_THRESHOLD |
7951 GEN6_PM_RP_UP_EI_EXPIRED |
7952 GEN6_PM_RP_DOWN_EI_EXPIRED);
4912d041
BW		 7953 spin_lock_irq(&dev_priv->rps_lock);
7954 WARN_ON(dev_priv->pm_iir != 0);
3b8d8d91 7955 I915_WRITE(GEN6_PMIMR, 0);
4912d041 7956 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91
JB		 7957 /* enable all PM interrupts */
7958 I915_WRITE(GEN6_PMINTRMSK, 0);
8fd26859 7959
fcca7926 7960 gen6_gt_force_wake_put(dev_priv);
d1ebd816 7961 mutex_unlock(&dev_priv->dev->struct_mutex);
8fd26859
CW		 7962}
7963
23b2f8bb
JB		 7964void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
7965{
7966 int min_freq = 15;
7967 int gpu_freq, ia_freq, max_ia_freq;
7968 int scaling_factor = 180;
7969
7970 max_ia_freq = cpufreq_quick_get_max(0);
7971 /*
7972 * Default to measured freq if none found, PCU will ensure we don't go
7973 * over
7974 */
7975 if (!max_ia_freq)
7976 max_ia_freq = tsc_khz;
7977
7978 /* Convert from kHz to MHz */
7979 max_ia_freq /= 1000;
7980
7981 mutex_lock(&dev_priv->dev->struct_mutex);
7982
7983 /*
7984 * For each potential GPU frequency, load a ring frequency we'd like
7985 * to use for memory access. We do this by specifying the IA frequency
7986 * the PCU should use as a reference to determine the ring frequency.
7987 */
7988 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
7989 gpu_freq--) {
7990 int diff = dev_priv->max_delay - gpu_freq;
7991
7992 /*
7993 * For GPU frequencies less than 750MHz, just use the lowest
7994 * ring freq.
7995 */
7996 if (gpu_freq < min_freq)
7997 ia_freq = 800;
7998 else
7999 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8000 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8001
8002 I915_WRITE(GEN6_PCODE_DATA,
8003 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8004 gpu_freq);
8005 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8006 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8007 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8008 GEN6_PCODE_READY) == 0, 10)) {
8009 DRM_ERROR("pcode write of freq table timed out\n");
8010 continue;
8011 }
8012 }
8013
8014 mutex_unlock(&dev_priv->dev->struct_mutex);
8015}
8016
6067aaea
JB		 8017static void ironlake_init_clock_gating(struct drm_device *dev)
8018{
8019 struct drm_i915_private *dev_priv = dev->dev_private;
8020 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8021
8022 /* Required for FBC */
8023 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8024 DPFCRUNIT_CLOCK_GATE_DISABLE |
8025 DPFDUNIT_CLOCK_GATE_DISABLE;
8026 /* Required for CxSR */
8027 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8028
8029 I915_WRITE(PCH_3DCGDIS0,
8030 MARIUNIT_CLOCK_GATE_DISABLE |
8031 SVSMUNIT_CLOCK_GATE_DISABLE);
8032 I915_WRITE(PCH_3DCGDIS1,
8033 VFMUNIT_CLOCK_GATE_DISABLE);
8034
8035 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8036
6067aaea
JB		 8037 /*
8038 * According to the spec the following bits should be set in
8039 * order to enable memory self-refresh
8040 * The bit 22/21 of 0x42004
8041 * The bit 5 of 0x42020
8042 * The bit 15 of 0x45000
8043 */
8044 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8045 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8046 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8047 I915_WRITE(ILK_DSPCLK_GATE,
8048 (I915_READ(ILK_DSPCLK_GATE) |
8049 ILK_DPARB_CLK_GATE));
8050 I915_WRITE(DISP_ARB_CTL,
8051 (I915_READ(DISP_ARB_CTL) |
8052 DISP_FBC_WM_DIS));
8053 I915_WRITE(WM3_LP_ILK, 0);
8054 I915_WRITE(WM2_LP_ILK, 0);
8055 I915_WRITE(WM1_LP_ILK, 0);
8056
8057 /*
8058 * Based on the document from hardware guys the following bits
8059 * should be set unconditionally in order to enable FBC.
8060 * The bit 22 of 0x42000
8061 * The bit 22 of 0x42004
8062 * The bit 7,8,9 of 0x42020.
8063 */
8064 if (IS_IRONLAKE_M(dev)) {
8065 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8066 I915_READ(ILK_DISPLAY_CHICKEN1) |
8067 ILK_FBCQ_DIS);
8068 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8069 I915_READ(ILK_DISPLAY_CHICKEN2) |
8070 ILK_DPARB_GATE);
8071 I915_WRITE(ILK_DSPCLK_GATE,
8072 I915_READ(ILK_DSPCLK_GATE) |
8073 ILK_DPFC_DIS1 |
8074 ILK_DPFC_DIS2 |
8075 ILK_CLK_FBC);
8076 }
8077
8078 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8079 I915_READ(ILK_DISPLAY_CHICKEN2) |
8080 ILK_ELPIN_409_SELECT);
8081 I915_WRITE(_3D_CHICKEN2,
8082 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8083 _3D_CHICKEN2_WM_READ_PIPELINED);
8fd26859
CW		 8084}
8085
6067aaea 8086static void gen6_init_clock_gating(struct drm_device *dev)
652c393a
JB		 8087{
8088 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 8089 int pipe;
6067aaea
JB		 8090 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8091
8092 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
652c393a 8093
6067aaea
JB		 8094 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8095 I915_READ(ILK_DISPLAY_CHICKEN2) |
8096 ILK_ELPIN_409_SELECT);
8956c8bb 8097
6067aaea
JB		 8098 I915_WRITE(WM3_LP_ILK, 0);
8099 I915_WRITE(WM2_LP_ILK, 0);
8100 I915_WRITE(WM1_LP_ILK, 0);
652c393a
JB		 8101
8102 /*
6067aaea
JB		 8103 * According to the spec the following bits should be
8104 * set in order to enable memory self-refresh and fbc:
8105 * The bit21 and bit22 of 0x42000
8106 * The bit21 and bit22 of 0x42004
8107 * The bit5 and bit7 of 0x42020
8108 * The bit14 of 0x70180
8109 * The bit14 of 0x71180
652c393a 8110 */
6067aaea
JB		 8111 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8112 I915_READ(ILK_DISPLAY_CHICKEN1) |
8113 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8114 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8115 I915_READ(ILK_DISPLAY_CHICKEN2) |
8116 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8117 I915_WRITE(ILK_DSPCLK_GATE,
8118 I915_READ(ILK_DSPCLK_GATE) |
8119 ILK_DPARB_CLK_GATE |
8120 ILK_DPFD_CLK_GATE);
8956c8bb 8121
d74362c9 8122 for_each_pipe(pipe) {
6067aaea
JB		 8123 I915_WRITE(DSPCNTR(pipe),
8124 I915_READ(DSPCNTR(pipe)) |
8125 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 8126 intel_flush_display_plane(dev_priv, pipe);
8127 }
6067aaea 8128}
8956c8bb 8129
28963a3e
JB		 8130static void ivybridge_init_clock_gating(struct drm_device *dev)
8131{
8132 struct drm_i915_private *dev_priv = dev->dev_private;
8133 int pipe;
8134 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7f8a8569 8135
28963a3e 8136 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
382b0936 8137
28963a3e
JB		 8138 I915_WRITE(WM3_LP_ILK, 0);
8139 I915_WRITE(WM2_LP_ILK, 0);
8140 I915_WRITE(WM1_LP_ILK, 0);
de6e2eaf 8141
28963a3e 8142 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
67e92af0 8143
d74362c9 8144 for_each_pipe(pipe) {
28963a3e
JB		 8145 I915_WRITE(DSPCNTR(pipe),
8146 I915_READ(DSPCNTR(pipe)) |
8147 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 8148 intel_flush_display_plane(dev_priv, pipe);
8149 }
28963a3e
JB		 8150}
8151
6067aaea
JB		 8152static void g4x_init_clock_gating(struct drm_device *dev)
8153{
8154 struct drm_i915_private *dev_priv = dev->dev_private;
8155 uint32_t dspclk_gate;
8fd26859 8156
6067aaea
JB		 8157 I915_WRITE(RENCLK_GATE_D1, 0);
8158 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8159 GS_UNIT_CLOCK_GATE_DISABLE |
8160 CL_UNIT_CLOCK_GATE_DISABLE);
8161 I915_WRITE(RAMCLK_GATE_D, 0);
8162 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8163 OVRUNIT_CLOCK_GATE_DISABLE |
8164 OVCUNIT_CLOCK_GATE_DISABLE;
8165 if (IS_GM45(dev))
8166 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8167 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8168}
1398261a 8169
6067aaea
JB		 8170static void crestline_init_clock_gating(struct drm_device *dev)
8171{
8172 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 8173
6067aaea
JB		 8174 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8175 I915_WRITE(RENCLK_GATE_D2, 0);
8176 I915_WRITE(DSPCLK_GATE_D, 0);
8177 I915_WRITE(RAMCLK_GATE_D, 0);
8178 I915_WRITE16(DEUC, 0);
8179}
652c393a 8180
6067aaea
JB		 8181static void broadwater_init_clock_gating(struct drm_device *dev)
8182{
8183 struct drm_i915_private *dev_priv = dev->dev_private;
8184
8185 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8186 I965_RCC_CLOCK_GATE_DISABLE |
8187 I965_RCPB_CLOCK_GATE_DISABLE |
8188 I965_ISC_CLOCK_GATE_DISABLE |
8189 I965_FBC_CLOCK_GATE_DISABLE);
8190 I915_WRITE(RENCLK_GATE_D2, 0);
8191}
8192
8193static void gen3_init_clock_gating(struct drm_device *dev)
8194{
8195 struct drm_i915_private *dev_priv = dev->dev_private;
8196 u32 dstate = I915_READ(D_STATE);
8197
8198 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8199 DSTATE_DOT_CLOCK_GATING;
8200 I915_WRITE(D_STATE, dstate);
8201}
8202
8203static void i85x_init_clock_gating(struct drm_device *dev)
8204{
8205 struct drm_i915_private *dev_priv = dev->dev_private;
8206
8207 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8208}
8209
8210static void i830_init_clock_gating(struct drm_device *dev)
8211{
8212 struct drm_i915_private *dev_priv = dev->dev_private;
8213
8214 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
652c393a
JB		 8215}
8216
645c62a5
JB		 8217static void ibx_init_clock_gating(struct drm_device *dev)
8218{
8219 struct drm_i915_private *dev_priv = dev->dev_private;
8220
8221 /*
8222 * On Ibex Peak and Cougar Point, we need to disable clock
8223 * gating for the panel power sequencer or it will fail to
8224 * start up when no ports are active.
8225 */
8226 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8227}
8228
8229static void cpt_init_clock_gating(struct drm_device *dev)
8230{
8231 struct drm_i915_private *dev_priv = dev->dev_private;
3bcf603f 8232 int pipe;
645c62a5
JB		 8233
8234 /*
8235 * On Ibex Peak and Cougar Point, we need to disable clock
8236 * gating for the panel power sequencer or it will fail to
8237 * start up when no ports are active.
8238 */
8239 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8240 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8241 DPLS_EDP_PPS_FIX_DIS);
3bcf603f
JB		 8242 /* Without this, mode sets may fail silently on FDI */
8243 for_each_pipe(pipe)
8244 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
652c393a
JB		 8245}
8246
ac668088 8247static void ironlake_teardown_rc6(struct drm_device *dev)
0cdab21f
CW		 8248{
8249 struct drm_i915_private *dev_priv = dev->dev_private;
8250
8251 if (dev_priv->renderctx) {
ac668088
CW		 8252 i915_gem_object_unpin(dev_priv->renderctx);
8253 drm_gem_object_unreference(&dev_priv->renderctx->base);
0cdab21f
CW		 8254 dev_priv->renderctx = NULL;
8255 }
8256
8257 if (dev_priv->pwrctx) {
ac668088
CW		 8258 i915_gem_object_unpin(dev_priv->pwrctx);
8259 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8260 dev_priv->pwrctx = NULL;
8261 }
8262}
8263
8264static void ironlake_disable_rc6(struct drm_device *dev)
8265{
8266 struct drm_i915_private *dev_priv = dev->dev_private;
8267
8268 if (I915_READ(PWRCTXA)) {
8269 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8270 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8271 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8272 50);
0cdab21f
CW		 8273
8274 I915_WRITE(PWRCTXA, 0);
8275 POSTING_READ(PWRCTXA);
8276
ac668088
CW		 8277 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8278 POSTING_READ(RSTDBYCTL);
0cdab21f 8279 }
ac668088 8280
99507307 8281 ironlake_teardown_rc6(dev);
0cdab21f
CW		 8282}
8283
ac668088 8284static int ironlake_setup_rc6(struct drm_device *dev)
d5bb081b
JB		 8285{
8286 struct drm_i915_private *dev_priv = dev->dev_private;
8287
ac668088
CW		 8288 if (dev_priv->renderctx == NULL)
8289 dev_priv->renderctx = intel_alloc_context_page(dev);
8290 if (!dev_priv->renderctx)
8291 return -ENOMEM;
8292
8293 if (dev_priv->pwrctx == NULL)
8294 dev_priv->pwrctx = intel_alloc_context_page(dev);
8295 if (!dev_priv->pwrctx) {
8296 ironlake_teardown_rc6(dev);
8297 return -ENOMEM;
8298 }
8299
8300 return 0;
d5bb081b
JB		 8301}
8302
8303void ironlake_enable_rc6(struct drm_device *dev)
8304{
8305 struct drm_i915_private *dev_priv = dev->dev_private;
8306 int ret;
8307
ac668088
CW		 8308 /* rc6 disabled by default due to repeated reports of hanging during
8309 * boot and resume.
8310 */
8311 if (!i915_enable_rc6)
8312 return;
8313
2c34b850 8314 mutex_lock(&dev->struct_mutex);
ac668088 8315 ret = ironlake_setup_rc6(dev);
2c34b850
BW		 8316 if (ret) {
8317 mutex_unlock(&dev->struct_mutex);
ac668088 8318 return;
2c34b850 8319 }
ac668088 8320
d5bb081b
JB		 8321 /*
8322 * GPU can automatically power down the render unit if given a page
8323 * to save state.
8324 */
8325 ret = BEGIN_LP_RING(6);
8326 if (ret) {
ac668088 8327 ironlake_teardown_rc6(dev);
2c34b850 8328 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8329 return;
8330 }
ac668088 8331
d5bb081b
JB		 8332 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8333 OUT_RING(MI_SET_CONTEXT);
8334 OUT_RING(dev_priv->renderctx->gtt_offset |
8335 MI_MM_SPACE_GTT |
8336 MI_SAVE_EXT_STATE_EN |
8337 MI_RESTORE_EXT_STATE_EN |
8338 MI_RESTORE_INHIBIT);
8339 OUT_RING(MI_SUSPEND_FLUSH);
8340 OUT_RING(MI_NOOP);
8341 OUT_RING(MI_FLUSH);
8342 ADVANCE_LP_RING();
8343
4a246cfc
BW		 8344 /*
8345 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8346 * does an implicit flush, combined with MI_FLUSH above, it should be
8347 * safe to assume that renderctx is valid
8348 */
8349 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8350 if (ret) {
8351 DRM_ERROR("failed to enable ironlake power power savings\n");
8352 ironlake_teardown_rc6(dev);
8353 mutex_unlock(&dev->struct_mutex);
8354 return;
8355 }
8356
d5bb081b
JB		 8357 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8358 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2c34b850 8359 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8360}
8361
645c62a5
JB		 8362void intel_init_clock_gating(struct drm_device *dev)
8363{
8364 struct drm_i915_private *dev_priv = dev->dev_private;
8365
8366 dev_priv->display.init_clock_gating(dev);
8367
8368 if (dev_priv->display.init_pch_clock_gating)
8369 dev_priv->display.init_pch_clock_gating(dev);
8370}
ac668088 8371
e70236a8
JB		 8372/* Set up chip specific display functions */
8373static void intel_init_display(struct drm_device *dev)
8374{
8375 struct drm_i915_private *dev_priv = dev->dev_private;
8376
8377 /* We always want a DPMS function */
f564048e 8378 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 8379 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 8380 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
17638cd6 8381 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8382 } else {
e70236a8 8383 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 8384 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
17638cd6 8385 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8386 }
e70236a8 8387
ee5382ae 8388 if (I915_HAS_FBC(dev)) {
9c04f015 8389 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 8390 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8391 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8392 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8393 } else if (IS_GM45(dev)) {
74dff282
JB		 8394 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8395 dev_priv->display.enable_fbc = g4x_enable_fbc;
8396 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 8397 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 8398 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8399 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8400 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8401 }
74dff282 8402 /* 855GM needs testing */
e70236a8
JB		 8403 }
8404
8405 /* Returns the core display clock speed */
0206e353 8406 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8407 dev_priv->display.get_display_clock_speed =
8408 i945_get_display_clock_speed;
8409 else if (IS_I915G(dev))
8410 dev_priv->display.get_display_clock_speed =
8411 i915_get_display_clock_speed;
f2b115e6 8412 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8413 dev_priv->display.get_display_clock_speed =
8414 i9xx_misc_get_display_clock_speed;
8415 else if (IS_I915GM(dev))
8416 dev_priv->display.get_display_clock_speed =
8417 i915gm_get_display_clock_speed;
8418 else if (IS_I865G(dev))
8419 dev_priv->display.get_display_clock_speed =
8420 i865_get_display_clock_speed;
f0f8a9ce 8421 else if (IS_I85X(dev))
e70236a8
JB		 8422 dev_priv->display.get_display_clock_speed =
8423 i855_get_display_clock_speed;
8424 else /* 852, 830 */
8425 dev_priv->display.get_display_clock_speed =
8426 i830_get_display_clock_speed;
8427
8428 /* For FIFO watermark updates */
7f8a8569 8429 if (HAS_PCH_SPLIT(dev)) {
645c62a5
JB		 8430 if (HAS_PCH_IBX(dev))
8431 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8432 else if (HAS_PCH_CPT(dev))
8433 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8434
f00a3ddf 8435 if (IS_GEN5(dev)) {
7f8a8569
ZW		 8436 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8437 dev_priv->display.update_wm = ironlake_update_wm;
8438 else {
8439 DRM_DEBUG_KMS("Failed to get proper latency. "
8440 "Disable CxSR\n");
8441 dev_priv->display.update_wm = NULL;
1398261a 8442 }
674cf967 8443 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6067aaea 8444 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
e0dac65e 8445 dev_priv->display.write_eld = ironlake_write_eld;
1398261a
YL		 8446 } else if (IS_GEN6(dev)) {
8447 if (SNB_READ_WM0_LATENCY()) {
8448 dev_priv->display.update_wm = sandybridge_update_wm;
8449 } else {
8450 DRM_DEBUG_KMS("Failed to read display plane latency. "
8451 "Disable CxSR\n");
8452 dev_priv->display.update_wm = NULL;
7f8a8569 8453 }
674cf967 8454 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6067aaea 8455 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
e0dac65e 8456 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8457 } else if (IS_IVYBRIDGE(dev)) {
8458 /* FIXME: detect B0+ stepping and use auto training */
8459 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
fe100d4d
JB		 8460 if (SNB_READ_WM0_LATENCY()) {
8461 dev_priv->display.update_wm = sandybridge_update_wm;
8462 } else {
8463 DRM_DEBUG_KMS("Failed to read display plane latency. "
8464 "Disable CxSR\n");
8465 dev_priv->display.update_wm = NULL;
8466 }
28963a3e 8467 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
e0dac65e 8468 dev_priv->display.write_eld = ironlake_write_eld;
7f8a8569
ZW		 8469 } else
8470 dev_priv->display.update_wm = NULL;
8471 } else if (IS_PINEVIEW(dev)) {
d4294342 8472 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 8473 dev_priv->is_ddr3,
d4294342
ZY		 8474 dev_priv->fsb_freq,
8475 dev_priv->mem_freq)) {
8476 DRM_INFO("failed to find known CxSR latency "
95534263 8477 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 8478 "disabling CxSR\n",
0206e353 8479 (dev_priv->is_ddr3 == 1) ? "3" : "2",
d4294342
ZY		 8480 dev_priv->fsb_freq, dev_priv->mem_freq);
8481 /* Disable CxSR and never update its watermark again */
8482 pineview_disable_cxsr(dev);
8483 dev_priv->display.update_wm = NULL;
8484 } else
8485 dev_priv->display.update_wm = pineview_update_wm;
95e0ee92 8486 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6067aaea 8487 } else if (IS_G4X(dev)) {
e0dac65e 8488 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8489 dev_priv->display.update_wm = g4x_update_wm;
6067aaea
JB		 8490 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8491 } else if (IS_GEN4(dev)) {
e70236a8 8492 dev_priv->display.update_wm = i965_update_wm;
6067aaea
JB		 8493 if (IS_CRESTLINE(dev))
8494 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8495 else if (IS_BROADWATER(dev))
8496 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8497 } else if (IS_GEN3(dev)) {
e70236a8
JB		 8498 dev_priv->display.update_wm = i9xx_update_wm;
8499 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6067aaea
JB		 8500 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8501 } else if (IS_I865G(dev)) {
8502 dev_priv->display.update_wm = i830_update_wm;
8503 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8504 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8f4695ed
AJ		 8505 } else if (IS_I85X(dev)) {
8506 dev_priv->display.update_wm = i9xx_update_wm;
8507 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6067aaea 8508 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
e70236a8 8509 } else {
8f4695ed 8510 dev_priv->display.update_wm = i830_update_wm;
6067aaea 8511 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8f4695ed 8512 if (IS_845G(dev))
e70236a8
JB		 8513 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8514 else
8515 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8 8516 }
8c9f3aaf
JB		 8517
8518 /* Default just returns -ENODEV to indicate unsupported */
8519 dev_priv->display.queue_flip = intel_default_queue_flip;
8520
8521 switch (INTEL_INFO(dev)->gen) {
8522 case 2:
8523 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8524 break;
8525
8526 case 3:
8527 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8528 break;
8529
8530 case 4:
8531 case 5:
8532 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8533 break;
8534
8535 case 6:
8536 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8537 break;
7c9017e5
JB		 8538 case 7:
8539 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8540 break;
8c9f3aaf 8541 }
e70236a8
JB		 8542}
8543
b690e96c
JB		 8544/*
8545 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8546 * resume, or other times. This quirk makes sure that's the case for
8547 * affected systems.
8548 */
0206e353 8549static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8550{
8551 struct drm_i915_private *dev_priv = dev->dev_private;
8552
8553 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8554 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8555}
8556
435793df
KP		 8557/*
8558 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8559 */
8560static void quirk_ssc_force_disable(struct drm_device *dev)
8561{
8562 struct drm_i915_private *dev_priv = dev->dev_private;
8563 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8564}
8565
b690e96c
JB		 8566struct intel_quirk {
8567 int device;
8568 int subsystem_vendor;
8569 int subsystem_device;
8570 void (*hook)(struct drm_device *dev);
8571};
8572
8573struct intel_quirk intel_quirks[] = {
8574 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8575 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8576 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8577 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c
JB		 8578
8579 /* Thinkpad R31 needs pipe A force quirk */
8580 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8581 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8582 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8583
8584 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8585 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
8586 /* ThinkPad X40 needs pipe A force quirk */
8587
8588 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8589 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8590
8591 /* 855 & before need to leave pipe A & dpll A up */
8592 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8593 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8594
8595 /* Lenovo U160 cannot use SSC on LVDS */
8596 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8597
8598 /* Sony Vaio Y cannot use SSC on LVDS */
8599 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
b690e96c
JB		 8600};
8601
8602static void intel_init_quirks(struct drm_device *dev)
8603{
8604 struct pci_dev *d = dev->pdev;
8605 int i;
8606
8607 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8608 struct intel_quirk *q = &intel_quirks[i];
8609
8610 if (d->device == q->device &&
8611 (d->subsystem_vendor == q->subsystem_vendor ||
8612 q->subsystem_vendor == PCI_ANY_ID) &&
8613 (d->subsystem_device == q->subsystem_device ||
8614 q->subsystem_device == PCI_ANY_ID))
8615 q->hook(dev);
8616 }
8617}
8618
9cce37f4
JB		 8619/* Disable the VGA plane that we never use */
8620static void i915_disable_vga(struct drm_device *dev)
8621{
8622 struct drm_i915_private *dev_priv = dev->dev_private;
8623 u8 sr1;
8624 u32 vga_reg;
8625
8626 if (HAS_PCH_SPLIT(dev))
8627 vga_reg = CPU_VGACNTRL;
8628 else
8629 vga_reg = VGACNTRL;
8630
8631 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8632 outb(1, VGA_SR_INDEX);
8633 sr1 = inb(VGA_SR_DATA);
8634 outb(sr1 | 1<<5, VGA_SR_DATA);
8635 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8636 udelay(300);
8637
8638 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8639 POSTING_READ(vga_reg);
8640}
8641
79e53945
JB		 8642void intel_modeset_init(struct drm_device *dev)
8643{
652c393a 8644 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 8645 int i;
8646
8647 drm_mode_config_init(dev);
8648
8649 dev->mode_config.min_width = 0;
8650 dev->mode_config.min_height = 0;
8651
8652 dev->mode_config.funcs = (void *)&intel_mode_funcs;
8653
b690e96c
JB		 8654 intel_init_quirks(dev);
8655
e70236a8
JB		 8656 intel_init_display(dev);
8657
a6c45cf0
CW		 8658 if (IS_GEN2(dev)) {
8659 dev->mode_config.max_width = 2048;
8660 dev->mode_config.max_height = 2048;
8661 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8662 dev->mode_config.max_width = 4096;
8663 dev->mode_config.max_height = 4096;
79e53945 8664 } else {
a6c45cf0
CW		 8665 dev->mode_config.max_width = 8192;
8666 dev->mode_config.max_height = 8192;
79e53945 8667 }
35c3047a 8668 dev->mode_config.fb_base = dev->agp->base;
79e53945 8669
28c97730 8670 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8671 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8672
a3524f1b 8673 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945
JB		 8674 intel_crtc_init(dev, i);
8675 }
8676
9cce37f4
JB		 8677 /* Just disable it once at startup */
8678 i915_disable_vga(dev);
79e53945 8679 intel_setup_outputs(dev);
652c393a 8680
645c62a5 8681 intel_init_clock_gating(dev);
9cce37f4 8682
7648fa99 8683 if (IS_IRONLAKE_M(dev)) {
f97108d1 8684 ironlake_enable_drps(dev);
7648fa99
JB		 8685 intel_init_emon(dev);
8686 }
f97108d1 8687
1c70c0ce 8688 if (IS_GEN6(dev) || IS_GEN7(dev)) {
3b8d8d91 8689 gen6_enable_rps(dev_priv);
23b2f8bb
JB		 8690 gen6_update_ring_freq(dev_priv);
8691 }
3b8d8d91 8692
652c393a
JB		 8693 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
8694 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
8695 (unsigned long)dev);
2c7111db
CW		 8696}
8697
8698void intel_modeset_gem_init(struct drm_device *dev)
8699{
8700 if (IS_IRONLAKE_M(dev))
8701 ironlake_enable_rc6(dev);
02e792fb
DV		 8702
8703 intel_setup_overlay(dev);
79e53945
JB		 8704}
8705
8706void intel_modeset_cleanup(struct drm_device *dev)
8707{
652c393a
JB		 8708 struct drm_i915_private *dev_priv = dev->dev_private;
8709 struct drm_crtc *crtc;
8710 struct intel_crtc *intel_crtc;
8711
f87ea761 8712 drm_kms_helper_poll_fini(dev);
652c393a
JB		 8713 mutex_lock(&dev->struct_mutex);
8714
723bfd70
JB		 8715 intel_unregister_dsm_handler();
8716
8717
652c393a
JB		 8718 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8719 /* Skip inactive CRTCs */
8720 if (!crtc->fb)
8721 continue;
8722
8723 intel_crtc = to_intel_crtc(crtc);
3dec0095 8724 intel_increase_pllclock(crtc);
652c393a
JB		 8725 }
8726
973d04f9 8727 intel_disable_fbc(dev);
e70236a8 8728
f97108d1
JB		 8729 if (IS_IRONLAKE_M(dev))
8730 ironlake_disable_drps(dev);
1c70c0ce 8731 if (IS_GEN6(dev) || IS_GEN7(dev))
3b8d8d91 8732 gen6_disable_rps(dev);
f97108d1 8733
d5bb081b
JB		 8734 if (IS_IRONLAKE_M(dev))
8735 ironlake_disable_rc6(dev);
0cdab21f 8736
69341a5e
KH		 8737 mutex_unlock(&dev->struct_mutex);
8738
6c0d9350
DV		 8739 /* Disable the irq before mode object teardown, for the irq might
8740 * enqueue unpin/hotplug work. */
8741 drm_irq_uninstall(dev);
8742 cancel_work_sync(&dev_priv->hotplug_work);
6fdd4d98 8743 cancel_work_sync(&dev_priv->rps_work);
6c0d9350 8744
1630fe75
CW		 8745 /* flush any delayed tasks or pending work */
8746 flush_scheduled_work();
8747
3dec0095
DV		 8748 /* Shut off idle work before the crtcs get freed. */
8749 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8750 intel_crtc = to_intel_crtc(crtc);
8751 del_timer_sync(&intel_crtc->idle_timer);
8752 }
8753 del_timer_sync(&dev_priv->idle_timer);
8754 cancel_work_sync(&dev_priv->idle_work);
8755
79e53945
JB		 8756 drm_mode_config_cleanup(dev);
8757}
8758
f1c79df3
ZW		 8759/*
8760 * Return which encoder is currently attached for connector.
8761 */
df0e9248 8762struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 8763{
df0e9248
CW		 8764 return &intel_attached_encoder(connector)->base;
8765}
f1c79df3 8766
df0e9248
CW		 8767void intel_connector_attach_encoder(struct intel_connector *connector,
8768 struct intel_encoder *encoder)
8769{
8770 connector->encoder = encoder;
8771 drm_mode_connector_attach_encoder(&connector->base,
8772 &encoder->base);
79e53945 8773}
28d52043
DA		 8774
8775/*
8776 * set vga decode state - true == enable VGA decode
8777 */
8778int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8779{
8780 struct drm_i915_private *dev_priv = dev->dev_private;
8781 u16 gmch_ctrl;
8782
8783 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8784 if (state)
8785 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8786 else
8787 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8788 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8789 return 0;
8790}
c4a1d9e4
CW		 8791
8792#ifdef CONFIG_DEBUG_FS
8793#include <linux/seq_file.h>
8794
8795struct intel_display_error_state {
8796 struct intel_cursor_error_state {
8797 u32 control;
8798 u32 position;
8799 u32 base;
8800 u32 size;
8801 } cursor[2];
8802
8803 struct intel_pipe_error_state {
8804 u32 conf;
8805 u32 source;
8806
8807 u32 htotal;
8808 u32 hblank;
8809 u32 hsync;
8810 u32 vtotal;
8811 u32 vblank;
8812 u32 vsync;
8813 } pipe[2];
8814
8815 struct intel_plane_error_state {
8816 u32 control;
8817 u32 stride;
8818 u32 size;
8819 u32 pos;
8820 u32 addr;
8821 u32 surface;
8822 u32 tile_offset;
8823 } plane[2];
8824};
8825
8826struct intel_display_error_state *
8827intel_display_capture_error_state(struct drm_device *dev)
8828{
0206e353 8829 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 8830 struct intel_display_error_state *error;
8831 int i;
8832
8833 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8834 if (error == NULL)
8835 return NULL;
8836
8837 for (i = 0; i < 2; i++) {
8838 error->cursor[i].control = I915_READ(CURCNTR(i));
8839 error->cursor[i].position = I915_READ(CURPOS(i));
8840 error->cursor[i].base = I915_READ(CURBASE(i));
8841
8842 error->plane[i].control = I915_READ(DSPCNTR(i));
8843 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8844 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 8845 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 8846 error->plane[i].addr = I915_READ(DSPADDR(i));
8847 if (INTEL_INFO(dev)->gen >= 4) {
8848 error->plane[i].surface = I915_READ(DSPSURF(i));
8849 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8850 }
8851
8852 error->pipe[i].conf = I915_READ(PIPECONF(i));
8853 error->pipe[i].source = I915_READ(PIPESRC(i));
8854 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8855 error->pipe[i].hblank = I915_READ(HBLANK(i));
8856 error->pipe[i].hsync = I915_READ(HSYNC(i));
8857 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8858 error->pipe[i].vblank = I915_READ(VBLANK(i));
8859 error->pipe[i].vsync = I915_READ(VSYNC(i));
8860 }
8861
8862 return error;
8863}
8864
8865void
8866intel_display_print_error_state(struct seq_file *m,
8867 struct drm_device *dev,
8868 struct intel_display_error_state *error)
8869{
8870 int i;
8871
8872 for (i = 0; i < 2; i++) {
8873 seq_printf(m, "Pipe [%d]:\n", i);
8874 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8875 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8876 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8877 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8878 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8879 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8880 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8881 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8882
8883 seq_printf(m, "Plane [%d]:\n", i);
8884 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8885 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8886 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8887 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8888 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8889 if (INTEL_INFO(dev)->gen >= 4) {
8890 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8891 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8892 }
8893
8894 seq_printf(m, "Cursor [%d]:\n", i);
8895 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8896 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8897 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8898 }
8899}
8900#endif
Linux kernel - Deliverables
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