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drm/i915: fixup interlaced support on ilk+
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
23b2f8bb 27#include <linux/cpufreq.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
7662c8bd 47static void intel_update_watermarks(struct drm_device *dev);
3dec0095 48static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 49static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 50
51typedef struct {
0206e353
AJ		 52 /* given values */
53 int n;
54 int m1, m2;
55 int p1, p2;
56 /* derived values */
57 int dot;
58 int vco;
59 int m;
60 int p;
79e53945
JB		 61} intel_clock_t;
62
63typedef struct {
0206e353 64 int min, max;
79e53945
JB		 65} intel_range_t;
66
67typedef struct {
0206e353
AJ		 68 int dot_limit;
69 int p2_slow, p2_fast;
79e53945
JB		 70} intel_p2_t;
71
72#define INTEL_P2_NUM 2
d4906093
ML		 73typedef struct intel_limit intel_limit_t;
74struct intel_limit {
0206e353
AJ		 75 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 intel_p2_t p2;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 78 int, int, intel_clock_t *, intel_clock_t *);
d4906093 79};
79e53945 80
2377b741
JB		 81/* FDI */
82#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
83
d4906093
ML		 84static bool
85intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 86 int target, int refclk, intel_clock_t *match_clock,
87 intel_clock_t *best_clock);
d4906093
ML		 88static bool
89intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 90 int target, int refclk, intel_clock_t *match_clock,
91 intel_clock_t *best_clock);
79e53945 92
a4fc5ed6
KP		 93static bool
94intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 95 int target, int refclk, intel_clock_t *match_clock,
96 intel_clock_t *best_clock);
5eb08b69 97static bool
f2b115e6 98intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 99 int target, int refclk, intel_clock_t *match_clock,
100 intel_clock_t *best_clock);
a4fc5ed6 101
021357ac
CW		 102static inline u32 /* units of 100MHz */
103intel_fdi_link_freq(struct drm_device *dev)
104{
8b99e68c
CW		 105 if (IS_GEN5(dev)) {
106 struct drm_i915_private *dev_priv = dev->dev_private;
107 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
108 } else
109 return 27;
021357ac
CW		 110}
111
e4b36699 112static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 113 .dot = { .min = 25000, .max = 350000 },
114 .vco = { .min = 930000, .max = 1400000 },
115 .n = { .min = 3, .max = 16 },
116 .m = { .min = 96, .max = 140 },
117 .m1 = { .min = 18, .max = 26 },
118 .m2 = { .min = 6, .max = 16 },
119 .p = { .min = 4, .max = 128 },
120 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 121 .p2 = { .dot_limit = 165000,
122 .p2_slow = 4, .p2_fast = 2 },
d4906093 123 .find_pll = intel_find_best_PLL,
e4b36699
KP		 124};
125
126static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 127 .dot = { .min = 25000, .max = 350000 },
128 .vco = { .min = 930000, .max = 1400000 },
129 .n = { .min = 3, .max = 16 },
130 .m = { .min = 96, .max = 140 },
131 .m1 = { .min = 18, .max = 26 },
132 .m2 = { .min = 6, .max = 16 },
133 .p = { .min = 4, .max = 128 },
134 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 135 .p2 = { .dot_limit = 165000,
136 .p2_slow = 14, .p2_fast = 7 },
d4906093 137 .find_pll = intel_find_best_PLL,
e4b36699 138};
273e27ca 139
e4b36699 140static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 141 .dot = { .min = 20000, .max = 400000 },
142 .vco = { .min = 1400000, .max = 2800000 },
143 .n = { .min = 1, .max = 6 },
144 .m = { .min = 70, .max = 120 },
145 .m1 = { .min = 10, .max = 22 },
146 .m2 = { .min = 5, .max = 9 },
147 .p = { .min = 5, .max = 80 },
148 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 149 .p2 = { .dot_limit = 200000,
150 .p2_slow = 10, .p2_fast = 5 },
d4906093 151 .find_pll = intel_find_best_PLL,
e4b36699
KP		 152};
153
154static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 155 .dot = { .min = 20000, .max = 400000 },
156 .vco = { .min = 1400000, .max = 2800000 },
157 .n = { .min = 1, .max = 6 },
158 .m = { .min = 70, .max = 120 },
159 .m1 = { .min = 10, .max = 22 },
160 .m2 = { .min = 5, .max = 9 },
161 .p = { .min = 7, .max = 98 },
162 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 163 .p2 = { .dot_limit = 112000,
164 .p2_slow = 14, .p2_fast = 7 },
d4906093 165 .find_pll = intel_find_best_PLL,
e4b36699
KP		 166};
167
273e27ca 168
e4b36699 169static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 170 .dot = { .min = 25000, .max = 270000 },
171 .vco = { .min = 1750000, .max = 3500000},
172 .n = { .min = 1, .max = 4 },
173 .m = { .min = 104, .max = 138 },
174 .m1 = { .min = 17, .max = 23 },
175 .m2 = { .min = 5, .max = 11 },
176 .p = { .min = 10, .max = 30 },
177 .p1 = { .min = 1, .max = 3},
178 .p2 = { .dot_limit = 270000,
179 .p2_slow = 10,
180 .p2_fast = 10
044c7c41 181 },
d4906093 182 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 183};
184
185static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 186 .dot = { .min = 22000, .max = 400000 },
187 .vco = { .min = 1750000, .max = 3500000},
188 .n = { .min = 1, .max = 4 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 16, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 5, .max = 80 },
193 .p1 = { .min = 1, .max = 8},
194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 10, .p2_fast = 5 },
d4906093 196 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 200 .dot = { .min = 20000, .max = 115000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 28, .max = 112 },
207 .p1 = { .min = 2, .max = 8 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 14, .p2_fast = 14
044c7c41 210 },
d4906093 211 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 212};
213
214static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 215 .dot = { .min = 80000, .max = 224000 },
216 .vco = { .min = 1750000, .max = 3500000 },
217 .n = { .min = 1, .max = 3 },
218 .m = { .min = 104, .max = 138 },
219 .m1 = { .min = 17, .max = 23 },
220 .m2 = { .min = 5, .max = 11 },
221 .p = { .min = 14, .max = 42 },
222 .p1 = { .min = 2, .max = 6 },
223 .p2 = { .dot_limit = 0,
224 .p2_slow = 7, .p2_fast = 7
044c7c41 225 },
d4906093 226 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 227};
228
229static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 230 .dot = { .min = 161670, .max = 227000 },
231 .vco = { .min = 1750000, .max = 3500000},
232 .n = { .min = 1, .max = 2 },
233 .m = { .min = 97, .max = 108 },
234 .m1 = { .min = 0x10, .max = 0x12 },
235 .m2 = { .min = 0x05, .max = 0x06 },
236 .p = { .min = 10, .max = 20 },
237 .p1 = { .min = 1, .max = 2},
238 .p2 = { .dot_limit = 0,
273e27ca 239 .p2_slow = 10, .p2_fast = 10 },
0206e353 240 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 241};
242
f2b115e6 243static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 244 .dot = { .min = 20000, .max = 400000},
245 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 246 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 247 .n = { .min = 3, .max = 6 },
248 .m = { .min = 2, .max = 256 },
273e27ca 249 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 250 .m1 = { .min = 0, .max = 0 },
251 .m2 = { .min = 0, .max = 254 },
252 .p = { .min = 5, .max = 80 },
253 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 254 .p2 = { .dot_limit = 200000,
255 .p2_slow = 10, .p2_fast = 5 },
6115707b 256 .find_pll = intel_find_best_PLL,
e4b36699
KP		 257};
258
f2b115e6 259static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 260 .dot = { .min = 20000, .max = 400000 },
261 .vco = { .min = 1700000, .max = 3500000 },
262 .n = { .min = 3, .max = 6 },
263 .m = { .min = 2, .max = 256 },
264 .m1 = { .min = 0, .max = 0 },
265 .m2 = { .min = 0, .max = 254 },
266 .p = { .min = 7, .max = 112 },
267 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 268 .p2 = { .dot_limit = 112000,
269 .p2_slow = 14, .p2_fast = 14 },
6115707b 270 .find_pll = intel_find_best_PLL,
e4b36699
KP		 271};
272
273e27ca
EA		 273/* Ironlake / Sandybridge
274 *
275 * We calculate clock using (register_value + 2) for N/M1/M2, so here
276 * the range value for them is (actual_value - 2).
277 */
b91ad0ec 278static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 279 .dot = { .min = 25000, .max = 350000 },
280 .vco = { .min = 1760000, .max = 3510000 },
281 .n = { .min = 1, .max = 5 },
282 .m = { .min = 79, .max = 127 },
283 .m1 = { .min = 12, .max = 22 },
284 .m2 = { .min = 5, .max = 9 },
285 .p = { .min = 5, .max = 80 },
286 .p1 = { .min = 1, .max = 8 },
287 .p2 = { .dot_limit = 225000,
288 .p2_slow = 10, .p2_fast = 5 },
4547668a 289 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 290};
291
b91ad0ec 292static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 293 .dot = { .min = 25000, .max = 350000 },
294 .vco = { .min = 1760000, .max = 3510000 },
295 .n = { .min = 1, .max = 3 },
296 .m = { .min = 79, .max = 118 },
297 .m1 = { .min = 12, .max = 22 },
298 .m2 = { .min = 5, .max = 9 },
299 .p = { .min = 28, .max = 112 },
300 .p1 = { .min = 2, .max = 8 },
301 .p2 = { .dot_limit = 225000,
302 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 303 .find_pll = intel_g4x_find_best_PLL,
304};
305
306static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 307 .dot = { .min = 25000, .max = 350000 },
308 .vco = { .min = 1760000, .max = 3510000 },
309 .n = { .min = 1, .max = 3 },
310 .m = { .min = 79, .max = 127 },
311 .m1 = { .min = 12, .max = 22 },
312 .m2 = { .min = 5, .max = 9 },
313 .p = { .min = 14, .max = 56 },
314 .p1 = { .min = 2, .max = 8 },
315 .p2 = { .dot_limit = 225000,
316 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 317 .find_pll = intel_g4x_find_best_PLL,
318};
319
273e27ca 320/* LVDS 100mhz refclk limits. */
b91ad0ec 321static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 322 .dot = { .min = 25000, .max = 350000 },
323 .vco = { .min = 1760000, .max = 3510000 },
324 .n = { .min = 1, .max = 2 },
325 .m = { .min = 79, .max = 126 },
326 .m1 = { .min = 12, .max = 22 },
327 .m2 = { .min = 5, .max = 9 },
328 .p = { .min = 28, .max = 112 },
0206e353 329 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 330 .p2 = { .dot_limit = 225000,
331 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 332 .find_pll = intel_g4x_find_best_PLL,
333};
334
335static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 336 .dot = { .min = 25000, .max = 350000 },
337 .vco = { .min = 1760000, .max = 3510000 },
338 .n = { .min = 1, .max = 3 },
339 .m = { .min = 79, .max = 126 },
340 .m1 = { .min = 12, .max = 22 },
341 .m2 = { .min = 5, .max = 9 },
342 .p = { .min = 14, .max = 42 },
0206e353 343 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 344 .p2 = { .dot_limit = 225000,
345 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 346 .find_pll = intel_g4x_find_best_PLL,
347};
348
349static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 350 .dot = { .min = 25000, .max = 350000 },
351 .vco = { .min = 1760000, .max = 3510000},
352 .n = { .min = 1, .max = 2 },
353 .m = { .min = 81, .max = 90 },
354 .m1 = { .min = 12, .max = 22 },
355 .m2 = { .min = 5, .max = 9 },
356 .p = { .min = 10, .max = 20 },
357 .p1 = { .min = 1, .max = 2},
358 .p2 = { .dot_limit = 0,
273e27ca 359 .p2_slow = 10, .p2_fast = 10 },
0206e353 360 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 361};
362
1b894b59
CW		 363static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
364 int refclk)
2c07245f 365{
b91ad0ec
ZW		 366 struct drm_device *dev = crtc->dev;
367 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 368 const intel_limit_t *limit;
b91ad0ec
ZW		 369
370 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b91ad0ec
ZW		 371 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
372 LVDS_CLKB_POWER_UP) {
373 /* LVDS dual channel */
1b894b59 374 if (refclk == 100000)
b91ad0ec
ZW		 375 limit = &intel_limits_ironlake_dual_lvds_100m;
376 else
377 limit = &intel_limits_ironlake_dual_lvds;
378 } else {
1b894b59 379 if (refclk == 100000)
b91ad0ec
ZW		 380 limit = &intel_limits_ironlake_single_lvds_100m;
381 else
382 limit = &intel_limits_ironlake_single_lvds;
383 }
384 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 385 HAS_eDP)
386 limit = &intel_limits_ironlake_display_port;
2c07245f 387 else
b91ad0ec 388 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 389
390 return limit;
391}
392
044c7c41
ML		 393static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
394{
395 struct drm_device *dev = crtc->dev;
396 struct drm_i915_private *dev_priv = dev->dev_private;
397 const intel_limit_t *limit;
398
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
400 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
401 LVDS_CLKB_POWER_UP)
402 /* LVDS with dual channel */
e4b36699 403 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 404 else
405 /* LVDS with dual channel */
e4b36699 406 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 407 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
408 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 409 limit = &intel_limits_g4x_hdmi;
044c7c41 410 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 411 limit = &intel_limits_g4x_sdvo;
0206e353 412 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 413 limit = &intel_limits_g4x_display_port;
044c7c41 414 } else /* The option is for other outputs */
e4b36699 415 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 416
417 return limit;
418}
419
1b894b59 420static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 421{
422 struct drm_device *dev = crtc->dev;
423 const intel_limit_t *limit;
424
bad720ff 425 if (HAS_PCH_SPLIT(dev))
1b894b59 426 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 427 else if (IS_G4X(dev)) {
044c7c41 428 limit = intel_g4x_limit(crtc);
f2b115e6 429 } else if (IS_PINEVIEW(dev)) {
2177832f 430 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 431 limit = &intel_limits_pineview_lvds;
2177832f 432 else
f2b115e6 433 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 434 } else if (!IS_GEN2(dev)) {
435 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
436 limit = &intel_limits_i9xx_lvds;
437 else
438 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 439 } else {
440 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 441 limit = &intel_limits_i8xx_lvds;
79e53945 442 else
e4b36699 443 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 444 }
445 return limit;
446}
447
f2b115e6
AJ		 448/* m1 is reserved as 0 in Pineview, n is a ring counter */
449static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 450{
2177832f
SL		 451 clock->m = clock->m2 + 2;
452 clock->p = clock->p1 * clock->p2;
453 clock->vco = refclk * clock->m / clock->n;
454 clock->dot = clock->vco / clock->p;
455}
456
457static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
458{
f2b115e6
AJ		 459 if (IS_PINEVIEW(dev)) {
460 pineview_clock(refclk, clock);
2177832f
SL		 461 return;
462 }
79e53945
JB		 463 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
464 clock->p = clock->p1 * clock->p2;
465 clock->vco = refclk * clock->m / (clock->n + 2);
466 clock->dot = clock->vco / clock->p;
467}
468
79e53945
JB		 469/**
470 * Returns whether any output on the specified pipe is of the specified type
471 */
4ef69c7a 472bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 473{
4ef69c7a
CW		 474 struct drm_device *dev = crtc->dev;
475 struct drm_mode_config *mode_config = &dev->mode_config;
476 struct intel_encoder *encoder;
477
478 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
479 if (encoder->base.crtc == crtc && encoder->type == type)
480 return true;
481
482 return false;
79e53945
JB		 483}
484
7c04d1d9 485#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 486/**
487 * Returns whether the given set of divisors are valid for a given refclk with
488 * the given connectors.
489 */
490
1b894b59
CW		 491static bool intel_PLL_is_valid(struct drm_device *dev,
492 const intel_limit_t *limit,
493 const intel_clock_t *clock)
79e53945 494{
79e53945 495 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 496 INTELPllInvalid("p1 out of range\n");
79e53945 497 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 498 INTELPllInvalid("p out of range\n");
79e53945 499 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 500 INTELPllInvalid("m2 out of range\n");
79e53945 501 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 502 INTELPllInvalid("m1 out of range\n");
f2b115e6 503 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 504 INTELPllInvalid("m1 <= m2\n");
79e53945 505 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 506 INTELPllInvalid("m out of range\n");
79e53945 507 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 508 INTELPllInvalid("n out of range\n");
79e53945 509 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 510 INTELPllInvalid("vco out of range\n");
79e53945
JB		 511 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
512 * connector, etc., rather than just a single range.
513 */
514 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 515 INTELPllInvalid("dot out of range\n");
79e53945
JB		 516
517 return true;
518}
519
d4906093
ML		 520static bool
521intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 522 int target, int refclk, intel_clock_t *match_clock,
523 intel_clock_t *best_clock)
d4906093 524
79e53945
JB		 525{
526 struct drm_device *dev = crtc->dev;
527 struct drm_i915_private *dev_priv = dev->dev_private;
528 intel_clock_t clock;
79e53945
JB		 529 int err = target;
530
bc5e5718 531 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 532 (I915_READ(LVDS)) != 0) {
79e53945
JB		 533 /*
534 * For LVDS, if the panel is on, just rely on its current
535 * settings for dual-channel. We haven't figured out how to
536 * reliably set up different single/dual channel state, if we
537 * even can.
538 */
539 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
540 LVDS_CLKB_POWER_UP)
541 clock.p2 = limit->p2.p2_fast;
542 else
543 clock.p2 = limit->p2.p2_slow;
544 } else {
545 if (target < limit->p2.dot_limit)
546 clock.p2 = limit->p2.p2_slow;
547 else
548 clock.p2 = limit->p2.p2_fast;
549 }
550
0206e353 551 memset(best_clock, 0, sizeof(*best_clock));
79e53945 552
42158660
ZY		 553 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
554 clock.m1++) {
555 for (clock.m2 = limit->m2.min;
556 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 557 /* m1 is always 0 in Pineview */
558 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 559 break;
560 for (clock.n = limit->n.min;
561 clock.n <= limit->n.max; clock.n++) {
562 for (clock.p1 = limit->p1.min;
563 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 564 int this_err;
565
2177832f 566 intel_clock(dev, refclk, &clock);
1b894b59
CW		 567 if (!intel_PLL_is_valid(dev, limit,
568 &clock))
79e53945 569 continue;
cec2f356
SP		 570 if (match_clock &&
571 clock.p != match_clock->p)
572 continue;
79e53945
JB		 573
574 this_err = abs(clock.dot - target);
575 if (this_err < err) {
576 *best_clock = clock;
577 err = this_err;
578 }
579 }
580 }
581 }
582 }
583
584 return (err != target);
585}
586
d4906093
ML		 587static bool
588intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 589 int target, int refclk, intel_clock_t *match_clock,
590 intel_clock_t *best_clock)
d4906093
ML		 591{
592 struct drm_device *dev = crtc->dev;
593 struct drm_i915_private *dev_priv = dev->dev_private;
594 intel_clock_t clock;
595 int max_n;
596 bool found;
6ba770dc
AJ		 597 /* approximately equals target * 0.00585 */
598 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 599 found = false;
600
601 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 602 int lvds_reg;
603
c619eed4 604 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 605 lvds_reg = PCH_LVDS;
606 else
607 lvds_reg = LVDS;
608 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 609 LVDS_CLKB_POWER_UP)
610 clock.p2 = limit->p2.p2_fast;
611 else
612 clock.p2 = limit->p2.p2_slow;
613 } else {
614 if (target < limit->p2.dot_limit)
615 clock.p2 = limit->p2.p2_slow;
616 else
617 clock.p2 = limit->p2.p2_fast;
618 }
619
620 memset(best_clock, 0, sizeof(*best_clock));
621 max_n = limit->n.max;
f77f13e2 622 /* based on hardware requirement, prefer smaller n to precision */
d4906093 623 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 624 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 625 for (clock.m1 = limit->m1.max;
626 clock.m1 >= limit->m1.min; clock.m1--) {
627 for (clock.m2 = limit->m2.max;
628 clock.m2 >= limit->m2.min; clock.m2--) {
629 for (clock.p1 = limit->p1.max;
630 clock.p1 >= limit->p1.min; clock.p1--) {
631 int this_err;
632
2177832f 633 intel_clock(dev, refclk, &clock);
1b894b59
CW		 634 if (!intel_PLL_is_valid(dev, limit,
635 &clock))
d4906093 636 continue;
cec2f356
SP		 637 if (match_clock &&
638 clock.p != match_clock->p)
639 continue;
1b894b59
CW		 640
641 this_err = abs(clock.dot - target);
d4906093
ML		 642 if (this_err < err_most) {
643 *best_clock = clock;
644 err_most = this_err;
645 max_n = clock.n;
646 found = true;
647 }
648 }
649 }
650 }
651 }
2c07245f
ZW		 652 return found;
653}
654
5eb08b69 655static bool
f2b115e6 656intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 657 int target, int refclk, intel_clock_t *match_clock,
658 intel_clock_t *best_clock)
5eb08b69
ZW		 659{
660 struct drm_device *dev = crtc->dev;
661 intel_clock_t clock;
4547668a 662
5eb08b69
ZW		 663 if (target < 200000) {
664 clock.n = 1;
665 clock.p1 = 2;
666 clock.p2 = 10;
667 clock.m1 = 12;
668 clock.m2 = 9;
669 } else {
670 clock.n = 2;
671 clock.p1 = 1;
672 clock.p2 = 10;
673 clock.m1 = 14;
674 clock.m2 = 8;
675 }
676 intel_clock(dev, refclk, &clock);
677 memcpy(best_clock, &clock, sizeof(intel_clock_t));
678 return true;
679}
680
a4fc5ed6
KP		 681/* DisplayPort has only two frequencies, 162MHz and 270MHz */
682static bool
683intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
a4fc5ed6 686{
5eddb70b
CW		 687 intel_clock_t clock;
688 if (target < 200000) {
689 clock.p1 = 2;
690 clock.p2 = 10;
691 clock.n = 2;
692 clock.m1 = 23;
693 clock.m2 = 8;
694 } else {
695 clock.p1 = 1;
696 clock.p2 = 10;
697 clock.n = 1;
698 clock.m1 = 14;
699 clock.m2 = 2;
700 }
701 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
702 clock.p = (clock.p1 * clock.p2);
703 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
704 clock.vco = 0;
705 memcpy(best_clock, &clock, sizeof(intel_clock_t));
706 return true;
a4fc5ed6
KP		 707}
708
9d0498a2
JB		 709/**
710 * intel_wait_for_vblank - wait for vblank on a given pipe
711 * @dev: drm device
712 * @pipe: pipe to wait for
713 *
714 * Wait for vblank to occur on a given pipe. Needed for various bits of
715 * mode setting code.
716 */
717void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 718{
9d0498a2 719 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 720 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 721
300387c0
CW		 722 /* Clear existing vblank status. Note this will clear any other
723 * sticky status fields as well.
724 *
725 * This races with i915_driver_irq_handler() with the result
726 * that either function could miss a vblank event. Here it is not
727 * fatal, as we will either wait upon the next vblank interrupt or
728 * timeout. Generally speaking intel_wait_for_vblank() is only
729 * called during modeset at which time the GPU should be idle and
730 * should *not* be performing page flips and thus not waiting on
731 * vblanks...
732 * Currently, the result of us stealing a vblank from the irq
733 * handler is that a single frame will be skipped during swapbuffers.
734 */
735 I915_WRITE(pipestat_reg,
736 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
737
9d0498a2 738 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 739 if (wait_for(I915_READ(pipestat_reg) &
740 PIPE_VBLANK_INTERRUPT_STATUS,
741 50))
9d0498a2
JB		 742 DRM_DEBUG_KMS("vblank wait timed out\n");
743}
744
ab7ad7f6
KP		 745/*
746 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 747 * @dev: drm device
748 * @pipe: pipe to wait for
749 *
750 * After disabling a pipe, we can't wait for vblank in the usual way,
751 * spinning on the vblank interrupt status bit, since we won't actually
752 * see an interrupt when the pipe is disabled.
753 *
ab7ad7f6
KP		 754 * On Gen4 and above:
755 * wait for the pipe register state bit to turn off
756 *
757 * Otherwise:
758 * wait for the display line value to settle (it usually
759 * ends up stopping at the start of the next frame).
58e10eb9 760 *
9d0498a2 761 */
58e10eb9 762void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 763{
764 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 765
766 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 767 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 768
769 /* Wait for the Pipe State to go off */
58e10eb9
CW		 770 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
771 100))
ab7ad7f6
KP		 772 DRM_DEBUG_KMS("pipe_off wait timed out\n");
773 } else {
774 u32 last_line;
58e10eb9 775 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 776 unsigned long timeout = jiffies + msecs_to_jiffies(100);
777
778 /* Wait for the display line to settle */
779 do {
58e10eb9 780 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 781 mdelay(5);
58e10eb9 782 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 783 time_after(timeout, jiffies));
784 if (time_after(jiffies, timeout))
785 DRM_DEBUG_KMS("pipe_off wait timed out\n");
786 }
79e53945
JB		 787}
788
b24e7179
JB		 789static const char *state_string(bool enabled)
790{
791 return enabled ? "on" : "off";
792}
793
794/* Only for pre-ILK configs */
795static void assert_pll(struct drm_i915_private *dev_priv,
796 enum pipe pipe, bool state)
797{
798 int reg;
799 u32 val;
800 bool cur_state;
801
802 reg = DPLL(pipe);
803 val = I915_READ(reg);
804 cur_state = !!(val & DPLL_VCO_ENABLE);
805 WARN(cur_state != state,
806 "PLL state assertion failure (expected %s, current %s)\n",
807 state_string(state), state_string(cur_state));
808}
809#define assert_pll_enabled(d, p) assert_pll(d, p, true)
810#define assert_pll_disabled(d, p) assert_pll(d, p, false)
811
040484af
JB		 812/* For ILK+ */
813static void assert_pch_pll(struct drm_i915_private *dev_priv,
814 enum pipe pipe, bool state)
815{
816 int reg;
817 u32 val;
818 bool cur_state;
819
d3ccbe86
JB		 820 if (HAS_PCH_CPT(dev_priv->dev)) {
821 u32 pch_dpll;
822
823 pch_dpll = I915_READ(PCH_DPLL_SEL);
824
825 /* Make sure the selected PLL is enabled to the transcoder */
826 WARN(!((pch_dpll >> (4 * pipe)) & 8),
827 "transcoder %d PLL not enabled\n", pipe);
828
829 /* Convert the transcoder pipe number to a pll pipe number */
830 pipe = (pch_dpll >> (4 * pipe)) & 1;
831 }
832
040484af
JB		 833 reg = PCH_DPLL(pipe);
834 val = I915_READ(reg);
835 cur_state = !!(val & DPLL_VCO_ENABLE);
836 WARN(cur_state != state,
837 "PCH PLL state assertion failure (expected %s, current %s)\n",
838 state_string(state), state_string(cur_state));
839}
840#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
841#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
842
843static void assert_fdi_tx(struct drm_i915_private *dev_priv,
844 enum pipe pipe, bool state)
845{
846 int reg;
847 u32 val;
848 bool cur_state;
849
850 reg = FDI_TX_CTL(pipe);
851 val = I915_READ(reg);
852 cur_state = !!(val & FDI_TX_ENABLE);
853 WARN(cur_state != state,
854 "FDI TX state assertion failure (expected %s, current %s)\n",
855 state_string(state), state_string(cur_state));
856}
857#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
858#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
859
860static void assert_fdi_rx(struct drm_i915_private *dev_priv,
861 enum pipe pipe, bool state)
862{
863 int reg;
864 u32 val;
865 bool cur_state;
866
867 reg = FDI_RX_CTL(pipe);
868 val = I915_READ(reg);
869 cur_state = !!(val & FDI_RX_ENABLE);
870 WARN(cur_state != state,
871 "FDI RX state assertion failure (expected %s, current %s)\n",
872 state_string(state), state_string(cur_state));
873}
874#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
875#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
876
877static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
878 enum pipe pipe)
879{
880 int reg;
881 u32 val;
882
883 /* ILK FDI PLL is always enabled */
884 if (dev_priv->info->gen == 5)
885 return;
886
887 reg = FDI_TX_CTL(pipe);
888 val = I915_READ(reg);
889 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
890}
891
892static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
893 enum pipe pipe)
894{
895 int reg;
896 u32 val;
897
898 reg = FDI_RX_CTL(pipe);
899 val = I915_READ(reg);
900 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
901}
902
ea0760cf
JB		 903static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
904 enum pipe pipe)
905{
906 int pp_reg, lvds_reg;
907 u32 val;
908 enum pipe panel_pipe = PIPE_A;
0de3b485 909 bool locked = true;
ea0760cf
JB		 910
911 if (HAS_PCH_SPLIT(dev_priv->dev)) {
912 pp_reg = PCH_PP_CONTROL;
913 lvds_reg = PCH_LVDS;
914 } else {
915 pp_reg = PP_CONTROL;
916 lvds_reg = LVDS;
917 }
918
919 val = I915_READ(pp_reg);
920 if (!(val & PANEL_POWER_ON) ||
921 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
922 locked = false;
923
924 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
925 panel_pipe = PIPE_B;
926
927 WARN(panel_pipe == pipe && locked,
928 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 929 pipe_name(pipe));
ea0760cf
JB		 930}
931
b840d907
JB		 932void assert_pipe(struct drm_i915_private *dev_priv,
933 enum pipe pipe, bool state)
b24e7179
JB		 934{
935 int reg;
936 u32 val;
63d7bbe9 937 bool cur_state;
b24e7179 938
8e636784
DV		 939 /* if we need the pipe A quirk it must be always on */
940 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
941 state = true;
942
b24e7179
JB		 943 reg = PIPECONF(pipe);
944 val = I915_READ(reg);
63d7bbe9
JB		 945 cur_state = !!(val & PIPECONF_ENABLE);
946 WARN(cur_state != state,
947 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 948 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 949}
950
931872fc
CW		 951static void assert_plane(struct drm_i915_private *dev_priv,
952 enum plane plane, bool state)
b24e7179
JB		 953{
954 int reg;
955 u32 val;
931872fc 956 bool cur_state;
b24e7179
JB		 957
958 reg = DSPCNTR(plane);
959 val = I915_READ(reg);
931872fc
CW		 960 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
961 WARN(cur_state != state,
962 "plane %c assertion failure (expected %s, current %s)\n",
963 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 964}
965
931872fc
CW		 966#define assert_plane_enabled(d, p) assert_plane(d, p, true)
967#define assert_plane_disabled(d, p) assert_plane(d, p, false)
968
b24e7179
JB		 969static void assert_planes_disabled(struct drm_i915_private *dev_priv,
970 enum pipe pipe)
971{
972 int reg, i;
973 u32 val;
974 int cur_pipe;
975
19ec1358 976 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 977 if (HAS_PCH_SPLIT(dev_priv->dev)) {
978 reg = DSPCNTR(pipe);
979 val = I915_READ(reg);
980 WARN((val & DISPLAY_PLANE_ENABLE),
981 "plane %c assertion failure, should be disabled but not\n",
982 plane_name(pipe));
19ec1358 983 return;
28c05794 984 }
19ec1358 985
b24e7179
JB		 986 /* Need to check both planes against the pipe */
987 for (i = 0; i < 2; i++) {
988 reg = DSPCNTR(i);
989 val = I915_READ(reg);
990 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
991 DISPPLANE_SEL_PIPE_SHIFT;
992 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 993 "plane %c assertion failure, should be off on pipe %c but is still active\n",
994 plane_name(i), pipe_name(pipe));
b24e7179
JB		 995 }
996}
997
92f2584a
JB		 998static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
999{
1000 u32 val;
1001 bool enabled;
1002
1003 val = I915_READ(PCH_DREF_CONTROL);
1004 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1005 DREF_SUPERSPREAD_SOURCE_MASK));
1006 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1007}
1008
1009static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1010 enum pipe pipe)
1011{
1012 int reg;
1013 u32 val;
1014 bool enabled;
1015
1016 reg = TRANSCONF(pipe);
1017 val = I915_READ(reg);
1018 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1019 WARN(enabled,
1020 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1021 pipe_name(pipe));
92f2584a
JB		 1022}
1023
4e634389
KP		 1024static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1025 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1026{
1027 if ((val & DP_PORT_EN) == 0)
1028 return false;
1029
1030 if (HAS_PCH_CPT(dev_priv->dev)) {
1031 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1032 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1033 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1034 return false;
1035 } else {
1036 if ((val & DP_PIPE_MASK) != (pipe << 30))
1037 return false;
1038 }
1039 return true;
1040}
1041
1519b995
KP		 1042static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1043 enum pipe pipe, u32 val)
1044{
1045 if ((val & PORT_ENABLE) == 0)
1046 return false;
1047
1048 if (HAS_PCH_CPT(dev_priv->dev)) {
1049 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1050 return false;
1051 } else {
1052 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1053 return false;
1054 }
1055 return true;
1056}
1057
1058static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1059 enum pipe pipe, u32 val)
1060{
1061 if ((val & LVDS_PORT_EN) == 0)
1062 return false;
1063
1064 if (HAS_PCH_CPT(dev_priv->dev)) {
1065 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1066 return false;
1067 } else {
1068 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1069 return false;
1070 }
1071 return true;
1072}
1073
1074static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1075 enum pipe pipe, u32 val)
1076{
1077 if ((val & ADPA_DAC_ENABLE) == 0)
1078 return false;
1079 if (HAS_PCH_CPT(dev_priv->dev)) {
1080 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1081 return false;
1082 } else {
1083 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1084 return false;
1085 }
1086 return true;
1087}
1088
291906f1 1089static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1090 enum pipe pipe, int reg, u32 port_sel)
291906f1 1091{
47a05eca 1092 u32 val = I915_READ(reg);
4e634389 1093 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1094 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1095 reg, pipe_name(pipe));
291906f1
JB		 1096}
1097
1098static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1099 enum pipe pipe, int reg)
1100{
47a05eca 1101 u32 val = I915_READ(reg);
1519b995 1102 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
23c99e77 1103 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1104 reg, pipe_name(pipe));
291906f1
JB		 1105}
1106
1107static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1108 enum pipe pipe)
1109{
1110 int reg;
1111 u32 val;
291906f1 1112
f0575e92
KP		 1113 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1114 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1115 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1116
1117 reg = PCH_ADPA;
1118 val = I915_READ(reg);
1519b995 1119 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1120 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1121 pipe_name(pipe));
291906f1
JB		 1122
1123 reg = PCH_LVDS;
1124 val = I915_READ(reg);
1519b995 1125 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1126 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1127 pipe_name(pipe));
291906f1
JB		 1128
1129 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1130 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1131 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1132}
1133
63d7bbe9
JB		 1134/**
1135 * intel_enable_pll - enable a PLL
1136 * @dev_priv: i915 private structure
1137 * @pipe: pipe PLL to enable
1138 *
1139 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1140 * make sure the PLL reg is writable first though, since the panel write
1141 * protect mechanism may be enabled.
1142 *
1143 * Note! This is for pre-ILK only.
1144 */
1145static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1146{
1147 int reg;
1148 u32 val;
1149
1150 /* No really, not for ILK+ */
1151 BUG_ON(dev_priv->info->gen >= 5);
1152
1153 /* PLL is protected by panel, make sure we can write it */
1154 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1155 assert_panel_unlocked(dev_priv, pipe);
1156
1157 reg = DPLL(pipe);
1158 val = I915_READ(reg);
1159 val |= DPLL_VCO_ENABLE;
1160
1161 /* We do this three times for luck */
1162 I915_WRITE(reg, val);
1163 POSTING_READ(reg);
1164 udelay(150); /* wait for warmup */
1165 I915_WRITE(reg, val);
1166 POSTING_READ(reg);
1167 udelay(150); /* wait for warmup */
1168 I915_WRITE(reg, val);
1169 POSTING_READ(reg);
1170 udelay(150); /* wait for warmup */
1171}
1172
1173/**
1174 * intel_disable_pll - disable a PLL
1175 * @dev_priv: i915 private structure
1176 * @pipe: pipe PLL to disable
1177 *
1178 * Disable the PLL for @pipe, making sure the pipe is off first.
1179 *
1180 * Note! This is for pre-ILK only.
1181 */
1182static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1183{
1184 int reg;
1185 u32 val;
1186
1187 /* Don't disable pipe A or pipe A PLLs if needed */
1188 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1189 return;
1190
1191 /* Make sure the pipe isn't still relying on us */
1192 assert_pipe_disabled(dev_priv, pipe);
1193
1194 reg = DPLL(pipe);
1195 val = I915_READ(reg);
1196 val &= ~DPLL_VCO_ENABLE;
1197 I915_WRITE(reg, val);
1198 POSTING_READ(reg);
1199}
1200
92f2584a
JB		 1201/**
1202 * intel_enable_pch_pll - enable PCH PLL
1203 * @dev_priv: i915 private structure
1204 * @pipe: pipe PLL to enable
1205 *
1206 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1207 * drives the transcoder clock.
1208 */
1209static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1210 enum pipe pipe)
1211{
1212 int reg;
1213 u32 val;
1214
4c609cb8
JB		 1215 if (pipe > 1)
1216 return;
1217
92f2584a
JB		 1218 /* PCH only available on ILK+ */
1219 BUG_ON(dev_priv->info->gen < 5);
1220
1221 /* PCH refclock must be enabled first */
1222 assert_pch_refclk_enabled(dev_priv);
1223
1224 reg = PCH_DPLL(pipe);
1225 val = I915_READ(reg);
1226 val |= DPLL_VCO_ENABLE;
1227 I915_WRITE(reg, val);
1228 POSTING_READ(reg);
1229 udelay(200);
1230}
1231
1232static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1233 enum pipe pipe)
1234{
1235 int reg;
7a419866
JB		 1236 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1237 pll_sel = TRANSC_DPLL_ENABLE;
92f2584a 1238
4c609cb8
JB		 1239 if (pipe > 1)
1240 return;
1241
92f2584a
JB		 1242 /* PCH only available on ILK+ */
1243 BUG_ON(dev_priv->info->gen < 5);
1244
1245 /* Make sure transcoder isn't still depending on us */
1246 assert_transcoder_disabled(dev_priv, pipe);
1247
7a419866
JB		 1248 if (pipe == 0)
1249 pll_sel |= TRANSC_DPLLA_SEL;
1250 else if (pipe == 1)
1251 pll_sel |= TRANSC_DPLLB_SEL;
1252
1253
1254 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1255 return;
1256
92f2584a
JB		 1257 reg = PCH_DPLL(pipe);
1258 val = I915_READ(reg);
1259 val &= ~DPLL_VCO_ENABLE;
1260 I915_WRITE(reg, val);
1261 POSTING_READ(reg);
1262 udelay(200);
1263}
1264
040484af
JB		 1265static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1266 enum pipe pipe)
1267{
1268 int reg;
1269 u32 val;
1270
1271 /* PCH only available on ILK+ */
1272 BUG_ON(dev_priv->info->gen < 5);
1273
1274 /* Make sure PCH DPLL is enabled */
1275 assert_pch_pll_enabled(dev_priv, pipe);
1276
1277 /* FDI must be feeding us bits for PCH ports */
1278 assert_fdi_tx_enabled(dev_priv, pipe);
1279 assert_fdi_rx_enabled(dev_priv, pipe);
1280
1281 reg = TRANSCONF(pipe);
1282 val = I915_READ(reg);
e9bcff5c
JB		 1283
1284 if (HAS_PCH_IBX(dev_priv->dev)) {
1285 /*
1286 * make the BPC in transcoder be consistent with
1287 * that in pipeconf reg.
1288 */
1289 val &= ~PIPE_BPC_MASK;
1290 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1291 }
040484af
JB		 1292 I915_WRITE(reg, val | TRANS_ENABLE);
1293 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1294 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1295}
1296
1297static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1298 enum pipe pipe)
1299{
1300 int reg;
1301 u32 val;
1302
1303 /* FDI relies on the transcoder */
1304 assert_fdi_tx_disabled(dev_priv, pipe);
1305 assert_fdi_rx_disabled(dev_priv, pipe);
1306
291906f1
JB		 1307 /* Ports must be off as well */
1308 assert_pch_ports_disabled(dev_priv, pipe);
1309
040484af
JB		 1310 reg = TRANSCONF(pipe);
1311 val = I915_READ(reg);
1312 val &= ~TRANS_ENABLE;
1313 I915_WRITE(reg, val);
1314 /* wait for PCH transcoder off, transcoder state */
1315 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1316 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1317}
1318
b24e7179 1319/**
309cfea8 1320 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1321 * @dev_priv: i915 private structure
1322 * @pipe: pipe to enable
040484af 1323 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1324 *
1325 * Enable @pipe, making sure that various hardware specific requirements
1326 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1327 *
1328 * @pipe should be %PIPE_A or %PIPE_B.
1329 *
1330 * Will wait until the pipe is actually running (i.e. first vblank) before
1331 * returning.
1332 */
040484af
JB		 1333static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1334 bool pch_port)
b24e7179
JB		 1335{
1336 int reg;
1337 u32 val;
1338
1339 /*
1340 * A pipe without a PLL won't actually be able to drive bits from
1341 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1342 * need the check.
1343 */
1344 if (!HAS_PCH_SPLIT(dev_priv->dev))
1345 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1346 else {
1347 if (pch_port) {
1348 /* if driving the PCH, we need FDI enabled */
1349 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1350 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1351 }
1352 /* FIXME: assert CPU port conditions for SNB+ */
1353 }
b24e7179
JB		 1354
1355 reg = PIPECONF(pipe);
1356 val = I915_READ(reg);
00d70b15
CW		 1357 if (val & PIPECONF_ENABLE)
1358 return;
1359
1360 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1361 intel_wait_for_vblank(dev_priv->dev, pipe);
1362}
1363
1364/**
309cfea8 1365 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1366 * @dev_priv: i915 private structure
1367 * @pipe: pipe to disable
1368 *
1369 * Disable @pipe, making sure that various hardware specific requirements
1370 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1371 *
1372 * @pipe should be %PIPE_A or %PIPE_B.
1373 *
1374 * Will wait until the pipe has shut down before returning.
1375 */
1376static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1377 enum pipe pipe)
1378{
1379 int reg;
1380 u32 val;
1381
1382 /*
1383 * Make sure planes won't keep trying to pump pixels to us,
1384 * or we might hang the display.
1385 */
1386 assert_planes_disabled(dev_priv, pipe);
1387
1388 /* Don't disable pipe A or pipe A PLLs if needed */
1389 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1390 return;
1391
1392 reg = PIPECONF(pipe);
1393 val = I915_READ(reg);
00d70b15
CW		 1394 if ((val & PIPECONF_ENABLE) == 0)
1395 return;
1396
1397 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1398 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1399}
1400
d74362c9
KP		 1401/*
1402 * Plane regs are double buffered, going from enabled->disabled needs a
1403 * trigger in order to latch. The display address reg provides this.
1404 */
1405static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1406 enum plane plane)
1407{
1408 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1409 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1410}
1411
b24e7179
JB		 1412/**
1413 * intel_enable_plane - enable a display plane on a given pipe
1414 * @dev_priv: i915 private structure
1415 * @plane: plane to enable
1416 * @pipe: pipe being fed
1417 *
1418 * Enable @plane on @pipe, making sure that @pipe is running first.
1419 */
1420static void intel_enable_plane(struct drm_i915_private *dev_priv,
1421 enum plane plane, enum pipe pipe)
1422{
1423 int reg;
1424 u32 val;
1425
1426 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1427 assert_pipe_enabled(dev_priv, pipe);
1428
1429 reg = DSPCNTR(plane);
1430 val = I915_READ(reg);
00d70b15
CW		 1431 if (val & DISPLAY_PLANE_ENABLE)
1432 return;
1433
1434 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1435 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1436 intel_wait_for_vblank(dev_priv->dev, pipe);
1437}
1438
b24e7179
JB		 1439/**
1440 * intel_disable_plane - disable a display plane
1441 * @dev_priv: i915 private structure
1442 * @plane: plane to disable
1443 * @pipe: pipe consuming the data
1444 *
1445 * Disable @plane; should be an independent operation.
1446 */
1447static void intel_disable_plane(struct drm_i915_private *dev_priv,
1448 enum plane plane, enum pipe pipe)
1449{
1450 int reg;
1451 u32 val;
1452
1453 reg = DSPCNTR(plane);
1454 val = I915_READ(reg);
00d70b15
CW		 1455 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1456 return;
1457
1458 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1459 intel_flush_display_plane(dev_priv, plane);
1460 intel_wait_for_vblank(dev_priv->dev, pipe);
1461}
1462
47a05eca 1463static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1464 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1465{
1466 u32 val = I915_READ(reg);
4e634389 1467 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1468 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1469 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1470 }
47a05eca
JB		 1471}
1472
1473static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1474 enum pipe pipe, int reg)
1475{
1476 u32 val = I915_READ(reg);
1519b995 1477 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1478 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1479 reg, pipe);
47a05eca 1480 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1481 }
47a05eca
JB		 1482}
1483
1484/* Disable any ports connected to this transcoder */
1485static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1486 enum pipe pipe)
1487{
1488 u32 reg, val;
1489
1490 val = I915_READ(PCH_PP_CONTROL);
1491 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1492
f0575e92
KP		 1493 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1494 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1495 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1496
1497 reg = PCH_ADPA;
1498 val = I915_READ(reg);
1519b995 1499 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1500 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1501
1502 reg = PCH_LVDS;
1503 val = I915_READ(reg);
1519b995
KP		 1504 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1505 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1506 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1507 POSTING_READ(reg);
1508 udelay(100);
1509 }
1510
1511 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1512 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1513 disable_pch_hdmi(dev_priv, pipe, HDMID);
1514}
1515
43a9539f
CW		 1516static void i8xx_disable_fbc(struct drm_device *dev)
1517{
1518 struct drm_i915_private *dev_priv = dev->dev_private;
1519 u32 fbc_ctl;
1520
1521 /* Disable compression */
1522 fbc_ctl = I915_READ(FBC_CONTROL);
1523 if ((fbc_ctl & FBC_CTL_EN) == 0)
1524 return;
1525
1526 fbc_ctl &= ~FBC_CTL_EN;
1527 I915_WRITE(FBC_CONTROL, fbc_ctl);
1528
1529 /* Wait for compressing bit to clear */
1530 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1531 DRM_DEBUG_KMS("FBC idle timed out\n");
1532 return;
1533 }
1534
1535 DRM_DEBUG_KMS("disabled FBC\n");
1536}
1537
80824003
JB		 1538static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1539{
1540 struct drm_device *dev = crtc->dev;
1541 struct drm_i915_private *dev_priv = dev->dev_private;
1542 struct drm_framebuffer *fb = crtc->fb;
1543 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1544 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003 1545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
016b9b61 1546 int cfb_pitch;
80824003
JB		 1547 int plane, i;
1548 u32 fbc_ctl, fbc_ctl2;
1549
016b9b61 1550 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
01f2c773
VS		 1551 if (fb->pitches[0] < cfb_pitch)
1552 cfb_pitch = fb->pitches[0];
80824003
JB		 1553
1554 /* FBC_CTL wants 64B units */
016b9b61
CW		 1555 cfb_pitch = (cfb_pitch / 64) - 1;
1556 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
80824003
JB		 1557
1558 /* Clear old tags */
1559 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1560 I915_WRITE(FBC_TAG + (i * 4), 0);
1561
1562 /* Set it up... */
de568510
CW		 1563 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1564 fbc_ctl2 |= plane;
80824003
JB		 1565 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1566 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1567
1568 /* enable it... */
1569 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1570 if (IS_I945GM(dev))
49677901 1571 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
016b9b61 1572 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
80824003 1573 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
016b9b61 1574 fbc_ctl |= obj->fence_reg;
80824003
JB		 1575 I915_WRITE(FBC_CONTROL, fbc_ctl);
1576
016b9b61
CW		 1577 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1578 cfb_pitch, crtc->y, intel_crtc->plane);
80824003
JB		 1579}
1580
ee5382ae 1581static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1582{
80824003
JB		 1583 struct drm_i915_private *dev_priv = dev->dev_private;
1584
1585 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1586}
1587
74dff282
JB		 1588static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1589{
1590 struct drm_device *dev = crtc->dev;
1591 struct drm_i915_private *dev_priv = dev->dev_private;
1592 struct drm_framebuffer *fb = crtc->fb;
1593 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1594 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1596 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB		 1597 unsigned long stall_watermark = 200;
1598 u32 dpfc_ctl;
1599
74dff282 1600 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
016b9b61 1601 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
de568510 1602 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
74dff282 1603
74dff282
JB		 1604 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1605 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1606 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1607 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1608
1609 /* enable it... */
1610 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1611
28c97730 1612 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB		 1613}
1614
43a9539f 1615static void g4x_disable_fbc(struct drm_device *dev)
74dff282
JB		 1616{
1617 struct drm_i915_private *dev_priv = dev->dev_private;
1618 u32 dpfc_ctl;
1619
1620 /* Disable compression */
1621 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW		 1622 if (dpfc_ctl & DPFC_CTL_EN) {
1623 dpfc_ctl &= ~DPFC_CTL_EN;
1624 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1625
bed4a673
CW		 1626 DRM_DEBUG_KMS("disabled FBC\n");
1627 }
74dff282
JB		 1628}
1629
ee5382ae 1630static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1631{
74dff282
JB		 1632 struct drm_i915_private *dev_priv = dev->dev_private;
1633
1634 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1635}
1636
4efe0708
JB		 1637static void sandybridge_blit_fbc_update(struct drm_device *dev)
1638{
1639 struct drm_i915_private *dev_priv = dev->dev_private;
1640 u32 blt_ecoskpd;
1641
1642 /* Make sure blitter notifies FBC of writes */
fcca7926 1643 gen6_gt_force_wake_get(dev_priv);
4efe0708
JB		 1644 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1645 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1646 GEN6_BLITTER_LOCK_SHIFT;
1647 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1648 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1649 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1650 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1651 GEN6_BLITTER_LOCK_SHIFT);
1652 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1653 POSTING_READ(GEN6_BLITTER_ECOSKPD);
fcca7926 1654 gen6_gt_force_wake_put(dev_priv);
4efe0708
JB		 1655}
1656
b52eb4dc
ZY		 1657static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1658{
1659 struct drm_device *dev = crtc->dev;
1660 struct drm_i915_private *dev_priv = dev->dev_private;
1661 struct drm_framebuffer *fb = crtc->fb;
1662 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1663 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1664 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1665 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY		 1666 unsigned long stall_watermark = 200;
1667 u32 dpfc_ctl;
1668
bed4a673 1669 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
b52eb4dc
ZY		 1670 dpfc_ctl &= DPFC_RESERVED;
1671 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
9ce9d069
CW		 1672 /* Set persistent mode for front-buffer rendering, ala X. */
1673 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
016b9b61 1674 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
de568510 1675 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
b52eb4dc 1676
b52eb4dc
ZY		 1677 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1678 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1679 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1680 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1681 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1682 /* enable it... */
bed4a673 1683 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc 1684
9c04f015
YL		 1685 if (IS_GEN6(dev)) {
1686 I915_WRITE(SNB_DPFC_CTL_SA,
016b9b61 1687 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
9c04f015 1688 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
4efe0708 1689 sandybridge_blit_fbc_update(dev);
9c04f015
YL		 1690 }
1691
b52eb4dc
ZY		 1692 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1693}
1694
43a9539f 1695static void ironlake_disable_fbc(struct drm_device *dev)
b52eb4dc
ZY		 1696{
1697 struct drm_i915_private *dev_priv = dev->dev_private;
1698 u32 dpfc_ctl;
1699
1700 /* Disable compression */
1701 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW		 1702 if (dpfc_ctl & DPFC_CTL_EN) {
1703 dpfc_ctl &= ~DPFC_CTL_EN;
1704 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1705
bed4a673
CW		 1706 DRM_DEBUG_KMS("disabled FBC\n");
1707 }
b52eb4dc
ZY		 1708}
1709
1710static bool ironlake_fbc_enabled(struct drm_device *dev)
1711{
1712 struct drm_i915_private *dev_priv = dev->dev_private;
1713
1714 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1715}
1716
ee5382ae
AJ		 1717bool intel_fbc_enabled(struct drm_device *dev)
1718{
1719 struct drm_i915_private *dev_priv = dev->dev_private;
1720
1721 if (!dev_priv->display.fbc_enabled)
1722 return false;
1723
1724 return dev_priv->display.fbc_enabled(dev);
1725}
1726
1630fe75
CW		 1727static void intel_fbc_work_fn(struct work_struct *__work)
1728{
1729 struct intel_fbc_work *work =
1730 container_of(to_delayed_work(__work),
1731 struct intel_fbc_work, work);
1732 struct drm_device *dev = work->crtc->dev;
1733 struct drm_i915_private *dev_priv = dev->dev_private;
1734
1735 mutex_lock(&dev->struct_mutex);
1736 if (work == dev_priv->fbc_work) {
1737 /* Double check that we haven't switched fb without cancelling
1738 * the prior work.
1739 */
016b9b61 1740 if (work->crtc->fb == work->fb) {
1630fe75
CW		 1741 dev_priv->display.enable_fbc(work->crtc,
1742 work->interval);
1743
016b9b61
CW		 1744 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1745 dev_priv->cfb_fb = work->crtc->fb->base.id;
1746 dev_priv->cfb_y = work->crtc->y;
1747 }
1748
1630fe75
CW		 1749 dev_priv->fbc_work = NULL;
1750 }
1751 mutex_unlock(&dev->struct_mutex);
1752
1753 kfree(work);
1754}
1755
1756static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1757{
1758 if (dev_priv->fbc_work == NULL)
1759 return;
1760
1761 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1762
1763 /* Synchronisation is provided by struct_mutex and checking of
1764 * dev_priv->fbc_work, so we can perform the cancellation
1765 * entirely asynchronously.
1766 */
1767 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1768 /* tasklet was killed before being run, clean up */
1769 kfree(dev_priv->fbc_work);
1770
1771 /* Mark the work as no longer wanted so that if it does
1772 * wake-up (because the work was already running and waiting
1773 * for our mutex), it will discover that is no longer
1774 * necessary to run.
1775 */
1776 dev_priv->fbc_work = NULL;
1777}
1778
43a9539f 1779static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
ee5382ae 1780{
1630fe75
CW		 1781 struct intel_fbc_work *work;
1782 struct drm_device *dev = crtc->dev;
1783 struct drm_i915_private *dev_priv = dev->dev_private;
ee5382ae
AJ		 1784
1785 if (!dev_priv->display.enable_fbc)
1786 return;
1787
1630fe75
CW		 1788 intel_cancel_fbc_work(dev_priv);
1789
1790 work = kzalloc(sizeof *work, GFP_KERNEL);
1791 if (work == NULL) {
1792 dev_priv->display.enable_fbc(crtc, interval);
1793 return;
1794 }
1795
1796 work->crtc = crtc;
1797 work->fb = crtc->fb;
1798 work->interval = interval;
1799 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1800
1801 dev_priv->fbc_work = work;
1802
1803 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1804
1805 /* Delay the actual enabling to let pageflipping cease and the
016b9b61
CW		 1806 * display to settle before starting the compression. Note that
1807 * this delay also serves a second purpose: it allows for a
1808 * vblank to pass after disabling the FBC before we attempt
1809 * to modify the control registers.
1630fe75
CW		 1810 *
1811 * A more complicated solution would involve tracking vblanks
1812 * following the termination of the page-flipping sequence
1813 * and indeed performing the enable as a co-routine and not
1814 * waiting synchronously upon the vblank.
1815 */
1816 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
ee5382ae
AJ		 1817}
1818
1819void intel_disable_fbc(struct drm_device *dev)
1820{
1821 struct drm_i915_private *dev_priv = dev->dev_private;
1822
1630fe75
CW		 1823 intel_cancel_fbc_work(dev_priv);
1824
ee5382ae
AJ		 1825 if (!dev_priv->display.disable_fbc)
1826 return;
1827
1828 dev_priv->display.disable_fbc(dev);
016b9b61 1829 dev_priv->cfb_plane = -1;
ee5382ae
AJ		 1830}
1831
80824003
JB		 1832/**
1833 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1834 * @dev: the drm_device
80824003
JB		 1835 *
1836 * Set up the framebuffer compression hardware at mode set time. We
1837 * enable it if possible:
1838 * - plane A only (on pre-965)
1839 * - no pixel mulitply/line duplication
1840 * - no alpha buffer discard
1841 * - no dual wide
1842 * - framebuffer <= 2048 in width, 1536 in height
1843 *
1844 * We can't assume that any compression will take place (worst case),
1845 * so the compressed buffer has to be the same size as the uncompressed
1846 * one. It also must reside (along with the line length buffer) in
1847 * stolen memory.
1848 *
1849 * We need to enable/disable FBC on a global basis.
1850 */
bed4a673 1851static void intel_update_fbc(struct drm_device *dev)
80824003 1852{
80824003 1853 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW		 1854 struct drm_crtc *crtc = NULL, *tmp_crtc;
1855 struct intel_crtc *intel_crtc;
1856 struct drm_framebuffer *fb;
80824003 1857 struct intel_framebuffer *intel_fb;
05394f39 1858 struct drm_i915_gem_object *obj;
cd0de039 1859 int enable_fbc;
9c928d16
JB		 1860
1861 DRM_DEBUG_KMS("\n");
80824003
JB		 1862
1863 if (!i915_powersave)
1864 return;
1865
ee5382ae 1866 if (!I915_HAS_FBC(dev))
e70236a8
JB		 1867 return;
1868
80824003
JB		 1869 /*
1870 * If FBC is already on, we just have to verify that we can
1871 * keep it that way...
1872 * Need to disable if:
9c928d16 1873 * - more than one pipe is active
80824003
JB		 1874 * - changing FBC params (stride, fence, mode)
1875 * - new fb is too large to fit in compressed buffer
1876 * - going to an unsupported config (interlace, pixel multiply, etc.)
1877 */
9c928d16 1878 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
d210246a 1879 if (tmp_crtc->enabled && tmp_crtc->fb) {
bed4a673
CW		 1880 if (crtc) {
1881 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1882 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1883 goto out_disable;
1884 }
1885 crtc = tmp_crtc;
1886 }
9c928d16 1887 }
bed4a673
CW		 1888
1889 if (!crtc || crtc->fb == NULL) {
1890 DRM_DEBUG_KMS("no output, disabling\n");
1891 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB		 1892 goto out_disable;
1893 }
bed4a673
CW		 1894
1895 intel_crtc = to_intel_crtc(crtc);
1896 fb = crtc->fb;
1897 intel_fb = to_intel_framebuffer(fb);
05394f39 1898 obj = intel_fb->obj;
bed4a673 1899
cd0de039
KP		 1900 enable_fbc = i915_enable_fbc;
1901 if (enable_fbc < 0) {
1902 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1903 enable_fbc = 1;
d56d8b28 1904 if (INTEL_INFO(dev)->gen <= 6)
cd0de039
KP		 1905 enable_fbc = 0;
1906 }
1907 if (!enable_fbc) {
1908 DRM_DEBUG_KMS("fbc disabled per module param\n");
c1a9f047
JB		 1909 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1910 goto out_disable;
1911 }
05394f39 1912 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 1913 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 1914 "compression\n");
b5e50c3f 1915 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1916 goto out_disable;
1917 }
bed4a673
CW		 1918 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1919 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 1920 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 1921 "disabling\n");
b5e50c3f 1922 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB		 1923 goto out_disable;
1924 }
bed4a673
CW		 1925 if ((crtc->mode.hdisplay > 2048) ||
1926 (crtc->mode.vdisplay > 1536)) {
28c97730 1927 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 1928 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB		 1929 goto out_disable;
1930 }
bed4a673 1931 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 1932 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 1933 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB		 1934 goto out_disable;
1935 }
de568510
CW		 1936
1937 /* The use of a CPU fence is mandatory in order to detect writes
1938 * by the CPU to the scanout and trigger updates to the FBC.
1939 */
1940 if (obj->tiling_mode != I915_TILING_X ||
1941 obj->fence_reg == I915_FENCE_REG_NONE) {
1942 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
b5e50c3f 1943 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB		 1944 goto out_disable;
1945 }
1946
c924b934
JW		 1947 /* If the kernel debugger is active, always disable compression */
1948 if (in_dbg_master())
1949 goto out_disable;
1950
016b9b61
CW		 1951 /* If the scanout has not changed, don't modify the FBC settings.
1952 * Note that we make the fundamental assumption that the fb->obj
1953 * cannot be unpinned (and have its GTT offset and fence revoked)
1954 * without first being decoupled from the scanout and FBC disabled.
1955 */
1956 if (dev_priv->cfb_plane == intel_crtc->plane &&
1957 dev_priv->cfb_fb == fb->base.id &&
1958 dev_priv->cfb_y == crtc->y)
1959 return;
1960
1961 if (intel_fbc_enabled(dev)) {
1962 /* We update FBC along two paths, after changing fb/crtc
1963 * configuration (modeswitching) and after page-flipping
1964 * finishes. For the latter, we know that not only did
1965 * we disable the FBC at the start of the page-flip
1966 * sequence, but also more than one vblank has passed.
1967 *
1968 * For the former case of modeswitching, it is possible
1969 * to switch between two FBC valid configurations
1970 * instantaneously so we do need to disable the FBC
1971 * before we can modify its control registers. We also
1972 * have to wait for the next vblank for that to take
1973 * effect. However, since we delay enabling FBC we can
1974 * assume that a vblank has passed since disabling and
1975 * that we can safely alter the registers in the deferred
1976 * callback.
1977 *
1978 * In the scenario that we go from a valid to invalid
1979 * and then back to valid FBC configuration we have
1980 * no strict enforcement that a vblank occurred since
1981 * disabling the FBC. However, along all current pipe
1982 * disabling paths we do need to wait for a vblank at
1983 * some point. And we wait before enabling FBC anyway.
1984 */
1985 DRM_DEBUG_KMS("disabling active FBC for update\n");
1986 intel_disable_fbc(dev);
1987 }
1988
bed4a673 1989 intel_enable_fbc(crtc, 500);
80824003
JB		 1990 return;
1991
1992out_disable:
80824003 1993 /* Multiple disables should be harmless */
a939406f
CW		 1994 if (intel_fbc_enabled(dev)) {
1995 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 1996 intel_disable_fbc(dev);
a939406f 1997 }
80824003
JB		 1998}
1999
127bd2ac 2000int
48b956c5 2001intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 2002 struct drm_i915_gem_object *obj,
919926ae 2003 struct intel_ring_buffer *pipelined)
6b95a207 2004{
ce453d81 2005 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 2006 u32 alignment;
2007 int ret;
2008
05394f39 2009 switch (obj->tiling_mode) {
6b95a207 2010 case I915_TILING_NONE:
534843da
CW		 2011 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
2012 alignment = 128 * 1024;
a6c45cf0 2013 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2014 alignment = 4 * 1024;
2015 else
2016 alignment = 64 * 1024;
6b95a207
KH		 2017 break;
2018 case I915_TILING_X:
2019 /* pin() will align the object as required by fence */
2020 alignment = 0;
2021 break;
2022 case I915_TILING_Y:
2023 /* FIXME: Is this true? */
2024 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
2025 return -EINVAL;
2026 default:
2027 BUG();
2028 }
2029
ce453d81 2030 dev_priv->mm.interruptible = false;
2da3b9b9 2031 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 2032 if (ret)
ce453d81 2033 goto err_interruptible;
6b95a207
KH		 2034
2035 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2036 * fence, whereas 965+ only requires a fence if using
2037 * framebuffer compression. For simplicity, we always install
2038 * a fence as the cost is not that onerous.
2039 */
05394f39 2040 if (obj->tiling_mode != I915_TILING_NONE) {
ce453d81 2041 ret = i915_gem_object_get_fence(obj, pipelined);
48b956c5
CW		 2042 if (ret)
2043 goto err_unpin;
1690e1eb
CW		 2044
2045 i915_gem_object_pin_fence(obj);
6b95a207
KH		 2046 }
2047
ce453d81 2048 dev_priv->mm.interruptible = true;
6b95a207 2049 return 0;
48b956c5
CW		 2050
2051err_unpin:
2052 i915_gem_object_unpin(obj);
ce453d81
CW		 2053err_interruptible:
2054 dev_priv->mm.interruptible = true;
48b956c5 2055 return ret;
6b95a207
KH		 2056}
2057
1690e1eb
CW		 2058void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2059{
2060 i915_gem_object_unpin_fence(obj);
2061 i915_gem_object_unpin(obj);
2062}
2063
17638cd6
JB		 2064static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2065 int x, int y)
81255565
JB		 2066{
2067 struct drm_device *dev = crtc->dev;
2068 struct drm_i915_private *dev_priv = dev->dev_private;
2069 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2070 struct intel_framebuffer *intel_fb;
05394f39 2071 struct drm_i915_gem_object *obj;
81255565
JB		 2072 int plane = intel_crtc->plane;
2073 unsigned long Start, Offset;
81255565 2074 u32 dspcntr;
5eddb70b 2075 u32 reg;
81255565
JB		 2076
2077 switch (plane) {
2078 case 0:
2079 case 1:
2080 break;
2081 default:
2082 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2083 return -EINVAL;
2084 }
2085
2086 intel_fb = to_intel_framebuffer(fb);
2087 obj = intel_fb->obj;
81255565 2088
5eddb70b
CW		 2089 reg = DSPCNTR(plane);
2090 dspcntr = I915_READ(reg);
81255565
JB		 2091 /* Mask out pixel format bits in case we change it */
2092 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2093 switch (fb->bits_per_pixel) {
2094 case 8:
2095 dspcntr |= DISPPLANE_8BPP;
2096 break;
2097 case 16:
2098 if (fb->depth == 15)
2099 dspcntr |= DISPPLANE_15_16BPP;
2100 else
2101 dspcntr |= DISPPLANE_16BPP;
2102 break;
2103 case 24:
2104 case 32:
2105 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2106 break;
2107 default:
17638cd6 2108 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2109 return -EINVAL;
2110 }
a6c45cf0 2111 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2112 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2113 dspcntr |= DISPPLANE_TILED;
2114 else
2115 dspcntr &= ~DISPPLANE_TILED;
2116 }
2117
5eddb70b 2118 I915_WRITE(reg, dspcntr);
81255565 2119
05394f39 2120 Start = obj->gtt_offset;
01f2c773 2121 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2122
4e6cfefc 2123 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 2124 Start, Offset, x, y, fb->pitches[0]);
2125 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2126 if (INTEL_INFO(dev)->gen >= 4) {
5eddb70b
CW		 2127 I915_WRITE(DSPSURF(plane), Start);
2128 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2129 I915_WRITE(DSPADDR(plane), Offset);
2130 } else
2131 I915_WRITE(DSPADDR(plane), Start + Offset);
2132 POSTING_READ(reg);
81255565 2133
17638cd6
JB		 2134 return 0;
2135}
2136
2137static int ironlake_update_plane(struct drm_crtc *crtc,
2138 struct drm_framebuffer *fb, int x, int y)
2139{
2140 struct drm_device *dev = crtc->dev;
2141 struct drm_i915_private *dev_priv = dev->dev_private;
2142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2143 struct intel_framebuffer *intel_fb;
2144 struct drm_i915_gem_object *obj;
2145 int plane = intel_crtc->plane;
2146 unsigned long Start, Offset;
2147 u32 dspcntr;
2148 u32 reg;
2149
2150 switch (plane) {
2151 case 0:
2152 case 1:
27f8227b 2153 case 2:
17638cd6
JB		 2154 break;
2155 default:
2156 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2157 return -EINVAL;
2158 }
2159
2160 intel_fb = to_intel_framebuffer(fb);
2161 obj = intel_fb->obj;
2162
2163 reg = DSPCNTR(plane);
2164 dspcntr = I915_READ(reg);
2165 /* Mask out pixel format bits in case we change it */
2166 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2167 switch (fb->bits_per_pixel) {
2168 case 8:
2169 dspcntr |= DISPPLANE_8BPP;
2170 break;
2171 case 16:
2172 if (fb->depth != 16)
2173 return -EINVAL;
2174
2175 dspcntr |= DISPPLANE_16BPP;
2176 break;
2177 case 24:
2178 case 32:
2179 if (fb->depth == 24)
2180 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2181 else if (fb->depth == 30)
2182 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2183 else
2184 return -EINVAL;
2185 break;
2186 default:
2187 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2188 return -EINVAL;
2189 }
2190
2191 if (obj->tiling_mode != I915_TILING_NONE)
2192 dspcntr |= DISPPLANE_TILED;
2193 else
2194 dspcntr &= ~DISPPLANE_TILED;
2195
2196 /* must disable */
2197 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2198
2199 I915_WRITE(reg, dspcntr);
2200
2201 Start = obj->gtt_offset;
01f2c773 2202 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
17638cd6
JB		 2203
2204 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 2205 Start, Offset, x, y, fb->pitches[0]);
2206 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
17638cd6
JB		 2207 I915_WRITE(DSPSURF(plane), Start);
2208 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2209 I915_WRITE(DSPADDR(plane), Offset);
2210 POSTING_READ(reg);
2211
2212 return 0;
2213}
2214
2215/* Assume fb object is pinned & idle & fenced and just update base pointers */
2216static int
2217intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2218 int x, int y, enum mode_set_atomic state)
2219{
2220 struct drm_device *dev = crtc->dev;
2221 struct drm_i915_private *dev_priv = dev->dev_private;
2222 int ret;
2223
2224 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2225 if (ret)
2226 return ret;
2227
bed4a673 2228 intel_update_fbc(dev);
3dec0095 2229 intel_increase_pllclock(crtc);
81255565
JB		 2230
2231 return 0;
2232}
2233
5c3b82e2 2234static int
3c4fdcfb
KH		 2235intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2236 struct drm_framebuffer *old_fb)
79e53945
JB		 2237{
2238 struct drm_device *dev = crtc->dev;
79e53945
JB		 2239 struct drm_i915_master_private *master_priv;
2240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2241 int ret;
79e53945
JB		 2242
2243 /* no fb bound */
2244 if (!crtc->fb) {
a5071c2f 2245 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2246 return 0;
2247 }
2248
265db958 2249 switch (intel_crtc->plane) {
5c3b82e2
CW		 2250 case 0:
2251 case 1:
2252 break;
27f8227b
JB		 2253 case 2:
2254 if (IS_IVYBRIDGE(dev))
2255 break;
2256 /* fall through otherwise */
5c3b82e2 2257 default:
a5071c2f 2258 DRM_ERROR("no plane for crtc\n");
5c3b82e2 2259 return -EINVAL;
79e53945
JB		 2260 }
2261
5c3b82e2 2262 mutex_lock(&dev->struct_mutex);
265db958
CW		 2263 ret = intel_pin_and_fence_fb_obj(dev,
2264 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2265 NULL);
5c3b82e2
CW		 2266 if (ret != 0) {
2267 mutex_unlock(&dev->struct_mutex);
a5071c2f 2268 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2269 return ret;
2270 }
79e53945 2271
265db958 2272 if (old_fb) {
e6c3a2a6 2273 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 2274 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
265db958 2275
e6c3a2a6 2276 wait_event(dev_priv->pending_flip_queue,
01eec727 2277 atomic_read(&dev_priv->mm.wedged) ||
05394f39 2278 atomic_read(&obj->pending_flip) == 0);
85345517
CW		 2279
2280 /* Big Hammer, we also need to ensure that any pending
2281 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2282 * current scanout is retired before unpinning the old
2283 * framebuffer.
01eec727
CW		 2284 *
2285 * This should only fail upon a hung GPU, in which case we
2286 * can safely continue.
85345517 2287 */
a8198eea 2288 ret = i915_gem_object_finish_gpu(obj);
01eec727 2289 (void) ret;
265db958
CW		 2290 }
2291
21c74a8e
JW		 2292 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2293 LEAVE_ATOMIC_MODE_SET);
4e6cfefc 2294 if (ret) {
1690e1eb 2295 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2296 mutex_unlock(&dev->struct_mutex);
a5071c2f 2297 DRM_ERROR("failed to update base address\n");
4e6cfefc 2298 return ret;
79e53945 2299 }
3c4fdcfb 2300
b7f1de28
CW		 2301 if (old_fb) {
2302 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2303 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2304 }
652c393a 2305
5c3b82e2 2306 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2307
2308 if (!dev->primary->master)
5c3b82e2 2309 return 0;
79e53945
JB		 2310
2311 master_priv = dev->primary->master->driver_priv;
2312 if (!master_priv->sarea_priv)
5c3b82e2 2313 return 0;
79e53945 2314
265db958 2315 if (intel_crtc->pipe) {
79e53945
JB		 2316 master_priv->sarea_priv->pipeB_x = x;
2317 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2318 } else {
2319 master_priv->sarea_priv->pipeA_x = x;
2320 master_priv->sarea_priv->pipeA_y = y;
79e53945 2321 }
5c3b82e2
CW		 2322
2323 return 0;
79e53945
JB		 2324}
2325
5eddb70b 2326static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2327{
2328 struct drm_device *dev = crtc->dev;
2329 struct drm_i915_private *dev_priv = dev->dev_private;
2330 u32 dpa_ctl;
2331
28c97730 2332 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2333 dpa_ctl = I915_READ(DP_A);
2334 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2335
2336 if (clock < 200000) {
2337 u32 temp;
2338 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2339 /* workaround for 160Mhz:
2340 1) program 0x4600c bits 15:0 = 0x8124
2341 2) program 0x46010 bit 0 = 1
2342 3) program 0x46034 bit 24 = 1
2343 4) program 0x64000 bit 14 = 1
2344 */
2345 temp = I915_READ(0x4600c);
2346 temp &= 0xffff0000;
2347 I915_WRITE(0x4600c, temp | 0x8124);
2348
2349 temp = I915_READ(0x46010);
2350 I915_WRITE(0x46010, temp | 1);
2351
2352 temp = I915_READ(0x46034);
2353 I915_WRITE(0x46034, temp | (1 << 24));
2354 } else {
2355 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2356 }
2357 I915_WRITE(DP_A, dpa_ctl);
2358
5eddb70b 2359 POSTING_READ(DP_A);
32f9d658
ZW		 2360 udelay(500);
2361}
2362
5e84e1a4
ZW		 2363static void intel_fdi_normal_train(struct drm_crtc *crtc)
2364{
2365 struct drm_device *dev = crtc->dev;
2366 struct drm_i915_private *dev_priv = dev->dev_private;
2367 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2368 int pipe = intel_crtc->pipe;
2369 u32 reg, temp;
2370
2371 /* enable normal train */
2372 reg = FDI_TX_CTL(pipe);
2373 temp = I915_READ(reg);
61e499bf 2374 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2375 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2376 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2377 } else {
2378 temp &= ~FDI_LINK_TRAIN_NONE;
2379 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2380 }
5e84e1a4
ZW		 2381 I915_WRITE(reg, temp);
2382
2383 reg = FDI_RX_CTL(pipe);
2384 temp = I915_READ(reg);
2385 if (HAS_PCH_CPT(dev)) {
2386 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2387 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2388 } else {
2389 temp &= ~FDI_LINK_TRAIN_NONE;
2390 temp |= FDI_LINK_TRAIN_NONE;
2391 }
2392 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2393
2394 /* wait one idle pattern time */
2395 POSTING_READ(reg);
2396 udelay(1000);
357555c0
JB		 2397
2398 /* IVB wants error correction enabled */
2399 if (IS_IVYBRIDGE(dev))
2400 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2401 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2402}
2403
291427f5
JB		 2404static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2405{
2406 struct drm_i915_private *dev_priv = dev->dev_private;
2407 u32 flags = I915_READ(SOUTH_CHICKEN1);
2408
2409 flags |= FDI_PHASE_SYNC_OVR(pipe);
2410 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2411 flags |= FDI_PHASE_SYNC_EN(pipe);
2412 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2413 POSTING_READ(SOUTH_CHICKEN1);
2414}
2415
8db9d77b
ZW		 2416/* The FDI link training functions for ILK/Ibexpeak. */
2417static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2418{
2419 struct drm_device *dev = crtc->dev;
2420 struct drm_i915_private *dev_priv = dev->dev_private;
2421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2422 int pipe = intel_crtc->pipe;
0fc932b8 2423 int plane = intel_crtc->plane;
5eddb70b 2424 u32 reg, temp, tries;
8db9d77b 2425
0fc932b8
JB		 2426 /* FDI needs bits from pipe & plane first */
2427 assert_pipe_enabled(dev_priv, pipe);
2428 assert_plane_enabled(dev_priv, plane);
2429
e1a44743
AJ		 2430 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2431 for train result */
5eddb70b
CW		 2432 reg = FDI_RX_IMR(pipe);
2433 temp = I915_READ(reg);
e1a44743
AJ		 2434 temp &= ~FDI_RX_SYMBOL_LOCK;
2435 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2436 I915_WRITE(reg, temp);
2437 I915_READ(reg);
e1a44743
AJ		 2438 udelay(150);
2439
8db9d77b 2440 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2441 reg = FDI_TX_CTL(pipe);
2442 temp = I915_READ(reg);
77ffb597
AJ		 2443 temp &= ~(7 << 19);
2444 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2445 temp &= ~FDI_LINK_TRAIN_NONE;
2446 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2447 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2448
5eddb70b
CW		 2449 reg = FDI_RX_CTL(pipe);
2450 temp = I915_READ(reg);
8db9d77b
ZW		 2451 temp &= ~FDI_LINK_TRAIN_NONE;
2452 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2453 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2454
2455 POSTING_READ(reg);
8db9d77b
ZW		 2456 udelay(150);
2457
5b2adf89 2458 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2459 if (HAS_PCH_IBX(dev)) {
2460 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2461 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2462 FDI_RX_PHASE_SYNC_POINTER_EN);
2463 }
5b2adf89 2464
5eddb70b 2465 reg = FDI_RX_IIR(pipe);
e1a44743 2466 for (tries = 0; tries < 5; tries++) {
5eddb70b 2467 temp = I915_READ(reg);
8db9d77b
ZW		 2468 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2469
2470 if ((temp & FDI_RX_BIT_LOCK)) {
2471 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2472 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2473 break;
2474 }
8db9d77b 2475 }
e1a44743 2476 if (tries == 5)
5eddb70b 2477 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2478
2479 /* Train 2 */
5eddb70b
CW		 2480 reg = FDI_TX_CTL(pipe);
2481 temp = I915_READ(reg);
8db9d77b
ZW		 2482 temp &= ~FDI_LINK_TRAIN_NONE;
2483 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2484 I915_WRITE(reg, temp);
8db9d77b 2485
5eddb70b
CW		 2486 reg = FDI_RX_CTL(pipe);
2487 temp = I915_READ(reg);
8db9d77b
ZW		 2488 temp &= ~FDI_LINK_TRAIN_NONE;
2489 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2490 I915_WRITE(reg, temp);
8db9d77b 2491
5eddb70b
CW		 2492 POSTING_READ(reg);
2493 udelay(150);
8db9d77b 2494
5eddb70b 2495 reg = FDI_RX_IIR(pipe);
e1a44743 2496 for (tries = 0; tries < 5; tries++) {
5eddb70b 2497 temp = I915_READ(reg);
8db9d77b
ZW		 2498 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2499
2500 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2501 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2502 DRM_DEBUG_KMS("FDI train 2 done.\n");
2503 break;
2504 }
8db9d77b 2505 }
e1a44743 2506 if (tries == 5)
5eddb70b 2507 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2508
2509 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2510
8db9d77b
ZW		 2511}
2512
0206e353 2513static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2514 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2515 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2516 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2517 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2518};
2519
2520/* The FDI link training functions for SNB/Cougarpoint. */
2521static void gen6_fdi_link_train(struct drm_crtc *crtc)
2522{
2523 struct drm_device *dev = crtc->dev;
2524 struct drm_i915_private *dev_priv = dev->dev_private;
2525 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2526 int pipe = intel_crtc->pipe;
5eddb70b 2527 u32 reg, temp, i;
8db9d77b 2528
e1a44743
AJ		 2529 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2530 for train result */
5eddb70b
CW		 2531 reg = FDI_RX_IMR(pipe);
2532 temp = I915_READ(reg);
e1a44743
AJ		 2533 temp &= ~FDI_RX_SYMBOL_LOCK;
2534 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2535 I915_WRITE(reg, temp);
2536
2537 POSTING_READ(reg);
e1a44743
AJ		 2538 udelay(150);
2539
8db9d77b 2540 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2541 reg = FDI_TX_CTL(pipe);
2542 temp = I915_READ(reg);
77ffb597
AJ		 2543 temp &= ~(7 << 19);
2544 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2545 temp &= ~FDI_LINK_TRAIN_NONE;
2546 temp |= FDI_LINK_TRAIN_PATTERN_1;
2547 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2548 /* SNB-B */
2549 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2550 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2551
5eddb70b
CW		 2552 reg = FDI_RX_CTL(pipe);
2553 temp = I915_READ(reg);
8db9d77b
ZW		 2554 if (HAS_PCH_CPT(dev)) {
2555 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2556 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2557 } else {
2558 temp &= ~FDI_LINK_TRAIN_NONE;
2559 temp |= FDI_LINK_TRAIN_PATTERN_1;
2560 }
5eddb70b
CW		 2561 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2562
2563 POSTING_READ(reg);
8db9d77b
ZW		 2564 udelay(150);
2565
291427f5
JB		 2566 if (HAS_PCH_CPT(dev))
2567 cpt_phase_pointer_enable(dev, pipe);
2568
0206e353 2569 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2570 reg = FDI_TX_CTL(pipe);
2571 temp = I915_READ(reg);
8db9d77b
ZW		 2572 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2573 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2574 I915_WRITE(reg, temp);
2575
2576 POSTING_READ(reg);
8db9d77b
ZW		 2577 udelay(500);
2578
5eddb70b
CW		 2579 reg = FDI_RX_IIR(pipe);
2580 temp = I915_READ(reg);
8db9d77b
ZW		 2581 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2582
2583 if (temp & FDI_RX_BIT_LOCK) {
5eddb70b 2584 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2585 DRM_DEBUG_KMS("FDI train 1 done.\n");
2586 break;
2587 }
2588 }
2589 if (i == 4)
5eddb70b 2590 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2591
2592 /* Train 2 */
5eddb70b
CW		 2593 reg = FDI_TX_CTL(pipe);
2594 temp = I915_READ(reg);
8db9d77b
ZW		 2595 temp &= ~FDI_LINK_TRAIN_NONE;
2596 temp |= FDI_LINK_TRAIN_PATTERN_2;
2597 if (IS_GEN6(dev)) {
2598 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2599 /* SNB-B */
2600 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2601 }
5eddb70b 2602 I915_WRITE(reg, temp);
8db9d77b 2603
5eddb70b
CW		 2604 reg = FDI_RX_CTL(pipe);
2605 temp = I915_READ(reg);
8db9d77b
ZW		 2606 if (HAS_PCH_CPT(dev)) {
2607 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2608 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2609 } else {
2610 temp &= ~FDI_LINK_TRAIN_NONE;
2611 temp |= FDI_LINK_TRAIN_PATTERN_2;
2612 }
5eddb70b
CW		 2613 I915_WRITE(reg, temp);
2614
2615 POSTING_READ(reg);
8db9d77b
ZW		 2616 udelay(150);
2617
0206e353 2618 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2619 reg = FDI_TX_CTL(pipe);
2620 temp = I915_READ(reg);
8db9d77b
ZW		 2621 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2622 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2623 I915_WRITE(reg, temp);
2624
2625 POSTING_READ(reg);
8db9d77b
ZW		 2626 udelay(500);
2627
5eddb70b
CW		 2628 reg = FDI_RX_IIR(pipe);
2629 temp = I915_READ(reg);
8db9d77b
ZW		 2630 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2631
2632 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2633 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2634 DRM_DEBUG_KMS("FDI train 2 done.\n");
2635 break;
2636 }
2637 }
2638 if (i == 4)
5eddb70b 2639 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2640
2641 DRM_DEBUG_KMS("FDI train done.\n");
2642}
2643
357555c0
JB		 2644/* Manual link training for Ivy Bridge A0 parts */
2645static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2646{
2647 struct drm_device *dev = crtc->dev;
2648 struct drm_i915_private *dev_priv = dev->dev_private;
2649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2650 int pipe = intel_crtc->pipe;
2651 u32 reg, temp, i;
2652
2653 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2654 for train result */
2655 reg = FDI_RX_IMR(pipe);
2656 temp = I915_READ(reg);
2657 temp &= ~FDI_RX_SYMBOL_LOCK;
2658 temp &= ~FDI_RX_BIT_LOCK;
2659 I915_WRITE(reg, temp);
2660
2661 POSTING_READ(reg);
2662 udelay(150);
2663
2664 /* enable CPU FDI TX and PCH FDI RX */
2665 reg = FDI_TX_CTL(pipe);
2666 temp = I915_READ(reg);
2667 temp &= ~(7 << 19);
2668 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2669 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2670 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2671 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2672 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2673 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2674 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2675
2676 reg = FDI_RX_CTL(pipe);
2677 temp = I915_READ(reg);
2678 temp &= ~FDI_LINK_TRAIN_AUTO;
2679 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2680 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2681 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2682 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2683
2684 POSTING_READ(reg);
2685 udelay(150);
2686
291427f5
JB		 2687 if (HAS_PCH_CPT(dev))
2688 cpt_phase_pointer_enable(dev, pipe);
2689
0206e353 2690 for (i = 0; i < 4; i++) {
357555c0
JB		 2691 reg = FDI_TX_CTL(pipe);
2692 temp = I915_READ(reg);
2693 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2694 temp |= snb_b_fdi_train_param[i];
2695 I915_WRITE(reg, temp);
2696
2697 POSTING_READ(reg);
2698 udelay(500);
2699
2700 reg = FDI_RX_IIR(pipe);
2701 temp = I915_READ(reg);
2702 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2703
2704 if (temp & FDI_RX_BIT_LOCK ||
2705 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2706 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2707 DRM_DEBUG_KMS("FDI train 1 done.\n");
2708 break;
2709 }
2710 }
2711 if (i == 4)
2712 DRM_ERROR("FDI train 1 fail!\n");
2713
2714 /* Train 2 */
2715 reg = FDI_TX_CTL(pipe);
2716 temp = I915_READ(reg);
2717 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2718 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2719 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2720 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2721 I915_WRITE(reg, temp);
2722
2723 reg = FDI_RX_CTL(pipe);
2724 temp = I915_READ(reg);
2725 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2726 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2727 I915_WRITE(reg, temp);
2728
2729 POSTING_READ(reg);
2730 udelay(150);
2731
0206e353 2732 for (i = 0; i < 4; i++) {
357555c0
JB		 2733 reg = FDI_TX_CTL(pipe);
2734 temp = I915_READ(reg);
2735 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2736 temp |= snb_b_fdi_train_param[i];
2737 I915_WRITE(reg, temp);
2738
2739 POSTING_READ(reg);
2740 udelay(500);
2741
2742 reg = FDI_RX_IIR(pipe);
2743 temp = I915_READ(reg);
2744 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2745
2746 if (temp & FDI_RX_SYMBOL_LOCK) {
2747 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2748 DRM_DEBUG_KMS("FDI train 2 done.\n");
2749 break;
2750 }
2751 }
2752 if (i == 4)
2753 DRM_ERROR("FDI train 2 fail!\n");
2754
2755 DRM_DEBUG_KMS("FDI train done.\n");
2756}
2757
2758static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2759{
2760 struct drm_device *dev = crtc->dev;
2761 struct drm_i915_private *dev_priv = dev->dev_private;
2762 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2763 int pipe = intel_crtc->pipe;
5eddb70b 2764 u32 reg, temp;
79e53945 2765
c64e311e 2766 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2767 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2768 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2769
c98e9dcf 2770 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2771 reg = FDI_RX_CTL(pipe);
2772 temp = I915_READ(reg);
2773 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2774 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2775 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2776 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2777
2778 POSTING_READ(reg);
c98e9dcf
JB		 2779 udelay(200);
2780
2781 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2782 temp = I915_READ(reg);
2783 I915_WRITE(reg, temp | FDI_PCDCLK);
2784
2785 POSTING_READ(reg);
c98e9dcf
JB		 2786 udelay(200);
2787
2788 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2789 reg = FDI_TX_CTL(pipe);
2790 temp = I915_READ(reg);
c98e9dcf 2791 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2792 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2793
2794 POSTING_READ(reg);
c98e9dcf 2795 udelay(100);
6be4a607 2796 }
0e23b99d
JB		 2797}
2798
291427f5
JB		 2799static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2800{
2801 struct drm_i915_private *dev_priv = dev->dev_private;
2802 u32 flags = I915_READ(SOUTH_CHICKEN1);
2803
2804 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2805 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2806 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2807 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2808 POSTING_READ(SOUTH_CHICKEN1);
2809}
0fc932b8
JB		 2810static void ironlake_fdi_disable(struct drm_crtc *crtc)
2811{
2812 struct drm_device *dev = crtc->dev;
2813 struct drm_i915_private *dev_priv = dev->dev_private;
2814 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2815 int pipe = intel_crtc->pipe;
2816 u32 reg, temp;
2817
2818 /* disable CPU FDI tx and PCH FDI rx */
2819 reg = FDI_TX_CTL(pipe);
2820 temp = I915_READ(reg);
2821 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2822 POSTING_READ(reg);
2823
2824 reg = FDI_RX_CTL(pipe);
2825 temp = I915_READ(reg);
2826 temp &= ~(0x7 << 16);
2827 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2828 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2829
2830 POSTING_READ(reg);
2831 udelay(100);
2832
2833 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2834 if (HAS_PCH_IBX(dev)) {
2835 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2836 I915_WRITE(FDI_RX_CHICKEN(pipe),
2837 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2838 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2839 } else if (HAS_PCH_CPT(dev)) {
2840 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2841 }
0fc932b8
JB		 2842
2843 /* still set train pattern 1 */
2844 reg = FDI_TX_CTL(pipe);
2845 temp = I915_READ(reg);
2846 temp &= ~FDI_LINK_TRAIN_NONE;
2847 temp |= FDI_LINK_TRAIN_PATTERN_1;
2848 I915_WRITE(reg, temp);
2849
2850 reg = FDI_RX_CTL(pipe);
2851 temp = I915_READ(reg);
2852 if (HAS_PCH_CPT(dev)) {
2853 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2854 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2855 } else {
2856 temp &= ~FDI_LINK_TRAIN_NONE;
2857 temp |= FDI_LINK_TRAIN_PATTERN_1;
2858 }
2859 /* BPC in FDI rx is consistent with that in PIPECONF */
2860 temp &= ~(0x07 << 16);
2861 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2862 I915_WRITE(reg, temp);
2863
2864 POSTING_READ(reg);
2865 udelay(100);
2866}
2867
6b383a7f
CW		 2868/*
2869 * When we disable a pipe, we need to clear any pending scanline wait events
2870 * to avoid hanging the ring, which we assume we are waiting on.
2871 */
2872static void intel_clear_scanline_wait(struct drm_device *dev)
2873{
2874 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 2875 struct intel_ring_buffer *ring;
6b383a7f
CW		 2876 u32 tmp;
2877
2878 if (IS_GEN2(dev))
2879 /* Can't break the hang on i8xx */
2880 return;
2881
1ec14ad3 2882 ring = LP_RING(dev_priv);
8168bd48
CW		 2883 tmp = I915_READ_CTL(ring);
2884 if (tmp & RING_WAIT)
2885 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 2886}
2887
e6c3a2a6
CW		 2888static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2889{
05394f39 2890 struct drm_i915_gem_object *obj;
e6c3a2a6
CW		 2891 struct drm_i915_private *dev_priv;
2892
2893 if (crtc->fb == NULL)
2894 return;
2895
05394f39 2896 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW		 2897 dev_priv = crtc->dev->dev_private;
2898 wait_event(dev_priv->pending_flip_queue,
05394f39 2899 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW		 2900}
2901
040484af
JB		 2902static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2903{
2904 struct drm_device *dev = crtc->dev;
2905 struct drm_mode_config *mode_config = &dev->mode_config;
2906 struct intel_encoder *encoder;
2907
2908 /*
2909 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2910 * must be driven by its own crtc; no sharing is possible.
2911 */
2912 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2913 if (encoder->base.crtc != crtc)
2914 continue;
2915
2916 switch (encoder->type) {
2917 case INTEL_OUTPUT_EDP:
2918 if (!intel_encoder_is_pch_edp(&encoder->base))
2919 return false;
2920 continue;
2921 }
2922 }
2923
2924 return true;
2925}
2926
f67a559d
JB		 2927/*
2928 * Enable PCH resources required for PCH ports:
2929 * - PCH PLLs
2930 * - FDI training & RX/TX
2931 * - update transcoder timings
2932 * - DP transcoding bits
2933 * - transcoder
2934 */
2935static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2936{
2937 struct drm_device *dev = crtc->dev;
2938 struct drm_i915_private *dev_priv = dev->dev_private;
2939 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2940 int pipe = intel_crtc->pipe;
4b645f14 2941 u32 reg, temp, transc_sel;
2c07245f 2942
c98e9dcf 2943 /* For PCH output, training FDI link */
674cf967 2944 dev_priv->display.fdi_link_train(crtc);
2c07245f 2945
92f2584a 2946 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 2947
c98e9dcf 2948 if (HAS_PCH_CPT(dev)) {
4b645f14
JB		 2949 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2950 TRANSC_DPLLB_SEL;
2951
c98e9dcf
JB		 2952 /* Be sure PCH DPLL SEL is set */
2953 temp = I915_READ(PCH_DPLL_SEL);
d64311ab
JB		 2954 if (pipe == 0) {
2955 temp &= ~(TRANSA_DPLLB_SEL);
c98e9dcf 2956 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
d64311ab
JB		 2957 } else if (pipe == 1) {
2958 temp &= ~(TRANSB_DPLLB_SEL);
c98e9dcf 2959 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
d64311ab
JB		 2960 } else if (pipe == 2) {
2961 temp &= ~(TRANSC_DPLLB_SEL);
4b645f14 2962 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
d64311ab 2963 }
c98e9dcf 2964 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2965 }
5eddb70b 2966
d9b6cb56
JB		 2967 /* set transcoder timing, panel must allow it */
2968 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2969 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2970 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2971 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2972
5eddb70b
CW		 2973 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2974 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2975 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
8db9d77b 2976
5e84e1a4
ZW		 2977 intel_fdi_normal_train(crtc);
2978
c98e9dcf
JB		 2979 /* For PCH DP, enable TRANS_DP_CTL */
2980 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2981 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2982 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 2983 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 2984 reg = TRANS_DP_CTL(pipe);
2985 temp = I915_READ(reg);
2986 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2987 TRANS_DP_SYNC_MASK |
2988 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2989 temp |= (TRANS_DP_OUTPUT_ENABLE |
2990 TRANS_DP_ENH_FRAMING);
9325c9f0 2991 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2992
2993 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2994 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2995 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2996 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2997
2998 switch (intel_trans_dp_port_sel(crtc)) {
2999 case PCH_DP_B:
5eddb70b 3000 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3001 break;
3002 case PCH_DP_C:
5eddb70b 3003 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3004 break;
3005 case PCH_DP_D:
5eddb70b 3006 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3007 break;
3008 default:
3009 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 3010 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 3011 break;
32f9d658 3012 }
2c07245f 3013
5eddb70b 3014 I915_WRITE(reg, temp);
6be4a607 3015 }
b52eb4dc 3016
040484af 3017 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3018}
3019
d4270e57
JB		 3020void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3021{
3022 struct drm_i915_private *dev_priv = dev->dev_private;
3023 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3024 u32 temp;
3025
3026 temp = I915_READ(dslreg);
3027 udelay(500);
3028 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3029 /* Without this, mode sets may fail silently on FDI */
3030 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3031 udelay(250);
3032 I915_WRITE(tc2reg, 0);
3033 if (wait_for(I915_READ(dslreg) != temp, 5))
3034 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3035 }
3036}
3037
f67a559d
JB		 3038static void ironlake_crtc_enable(struct drm_crtc *crtc)
3039{
3040 struct drm_device *dev = crtc->dev;
3041 struct drm_i915_private *dev_priv = dev->dev_private;
3042 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3043 int pipe = intel_crtc->pipe;
3044 int plane = intel_crtc->plane;
3045 u32 temp;
3046 bool is_pch_port;
3047
3048 if (intel_crtc->active)
3049 return;
3050
3051 intel_crtc->active = true;
3052 intel_update_watermarks(dev);
3053
3054 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3055 temp = I915_READ(PCH_LVDS);
3056 if ((temp & LVDS_PORT_EN) == 0)
3057 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3058 }
3059
3060 is_pch_port = intel_crtc_driving_pch(crtc);
3061
3062 if (is_pch_port)
357555c0 3063 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 3064 else
3065 ironlake_fdi_disable(crtc);
3066
3067 /* Enable panel fitting for LVDS */
3068 if (dev_priv->pch_pf_size &&
3069 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3070 /* Force use of hard-coded filter coefficients
3071 * as some pre-programmed values are broken,
3072 * e.g. x201.
3073 */
9db4a9c7
JB		 3074 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3075 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3076 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3077 }
3078
9c54c0dd
JB		 3079 /*
3080 * On ILK+ LUT must be loaded before the pipe is running but with
3081 * clocks enabled
3082 */
3083 intel_crtc_load_lut(crtc);
3084
f67a559d
JB		 3085 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3086 intel_enable_plane(dev_priv, plane, pipe);
3087
3088 if (is_pch_port)
3089 ironlake_pch_enable(crtc);
c98e9dcf 3090
d1ebd816 3091 mutex_lock(&dev->struct_mutex);
bed4a673 3092 intel_update_fbc(dev);
d1ebd816
BW		 3093 mutex_unlock(&dev->struct_mutex);
3094
6b383a7f 3095 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 3096}
3097
3098static void ironlake_crtc_disable(struct drm_crtc *crtc)
3099{
3100 struct drm_device *dev = crtc->dev;
3101 struct drm_i915_private *dev_priv = dev->dev_private;
3102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3103 int pipe = intel_crtc->pipe;
3104 int plane = intel_crtc->plane;
5eddb70b 3105 u32 reg, temp;
b52eb4dc 3106
f7abfe8b
CW		 3107 if (!intel_crtc->active)
3108 return;
3109
e6c3a2a6 3110 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3111 drm_vblank_off(dev, pipe);
6b383a7f 3112 intel_crtc_update_cursor(crtc, false);
5eddb70b 3113
b24e7179 3114 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3115
973d04f9
CW		 3116 if (dev_priv->cfb_plane == plane)
3117 intel_disable_fbc(dev);
2c07245f 3118
b24e7179 3119 intel_disable_pipe(dev_priv, pipe);
32f9d658 3120
6be4a607 3121 /* Disable PF */
9db4a9c7
JB		 3122 I915_WRITE(PF_CTL(pipe), 0);
3123 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3124
0fc932b8 3125 ironlake_fdi_disable(crtc);
2c07245f 3126
47a05eca
JB		 3127 /* This is a horrible layering violation; we should be doing this in
3128 * the connector/encoder ->prepare instead, but we don't always have
3129 * enough information there about the config to know whether it will
3130 * actually be necessary or just cause undesired flicker.
3131 */
3132 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 3133
040484af 3134 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3135
6be4a607
JB		 3136 if (HAS_PCH_CPT(dev)) {
3137 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3138 reg = TRANS_DP_CTL(pipe);
3139 temp = I915_READ(reg);
3140 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3141 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3142 I915_WRITE(reg, temp);
6be4a607
JB		 3143
3144 /* disable DPLL_SEL */
3145 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3146 switch (pipe) {
3147 case 0:
d64311ab 3148 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3149 break;
3150 case 1:
6be4a607 3151 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3152 break;
3153 case 2:
4b645f14 3154 /* C shares PLL A or B */
d64311ab 3155 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3156 break;
3157 default:
3158 BUG(); /* wtf */
3159 }
6be4a607 3160 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3161 }
e3421a18 3162
6be4a607 3163 /* disable PCH DPLL */
4b645f14
JB		 3164 if (!intel_crtc->no_pll)
3165 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 3166
6be4a607 3167 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 3168 reg = FDI_RX_CTL(pipe);
3169 temp = I915_READ(reg);
3170 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 3171
6be4a607 3172 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 3173 reg = FDI_TX_CTL(pipe);
3174 temp = I915_READ(reg);
3175 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3176
3177 POSTING_READ(reg);
6be4a607 3178 udelay(100);
8db9d77b 3179
5eddb70b
CW		 3180 reg = FDI_RX_CTL(pipe);
3181 temp = I915_READ(reg);
3182 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 3183
6be4a607 3184 /* Wait for the clocks to turn off. */
5eddb70b 3185 POSTING_READ(reg);
6be4a607 3186 udelay(100);
6b383a7f 3187
f7abfe8b 3188 intel_crtc->active = false;
6b383a7f 3189 intel_update_watermarks(dev);
d1ebd816
BW		 3190
3191 mutex_lock(&dev->struct_mutex);
6b383a7f
CW		 3192 intel_update_fbc(dev);
3193 intel_clear_scanline_wait(dev);
d1ebd816 3194 mutex_unlock(&dev->struct_mutex);
6be4a607 3195}
1b3c7a47 3196
6be4a607
JB		 3197static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3198{
3199 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3200 int pipe = intel_crtc->pipe;
3201 int plane = intel_crtc->plane;
8db9d77b 3202
6be4a607
JB		 3203 /* XXX: When our outputs are all unaware of DPMS modes other than off
3204 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3205 */
3206 switch (mode) {
3207 case DRM_MODE_DPMS_ON:
3208 case DRM_MODE_DPMS_STANDBY:
3209 case DRM_MODE_DPMS_SUSPEND:
3210 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3211 ironlake_crtc_enable(crtc);
3212 break;
1b3c7a47 3213
6be4a607
JB		 3214 case DRM_MODE_DPMS_OFF:
3215 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3216 ironlake_crtc_disable(crtc);
2c07245f
ZW		 3217 break;
3218 }
3219}
3220
02e792fb
DV		 3221static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3222{
02e792fb 3223 if (!enable && intel_crtc->overlay) {
23f09ce3 3224 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3225 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3226
23f09ce3 3227 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3228 dev_priv->mm.interruptible = false;
3229 (void) intel_overlay_switch_off(intel_crtc->overlay);
3230 dev_priv->mm.interruptible = true;
23f09ce3 3231 mutex_unlock(&dev->struct_mutex);
02e792fb 3232 }
02e792fb 3233
5dcdbcb0
CW		 3234 /* Let userspace switch the overlay on again. In most cases userspace
3235 * has to recompute where to put it anyway.
3236 */
02e792fb
DV		 3237}
3238
0b8765c6 3239static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3240{
3241 struct drm_device *dev = crtc->dev;
79e53945
JB		 3242 struct drm_i915_private *dev_priv = dev->dev_private;
3243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3244 int pipe = intel_crtc->pipe;
80824003 3245 int plane = intel_crtc->plane;
79e53945 3246
f7abfe8b
CW		 3247 if (intel_crtc->active)
3248 return;
3249
3250 intel_crtc->active = true;
6b383a7f
CW		 3251 intel_update_watermarks(dev);
3252
63d7bbe9 3253 intel_enable_pll(dev_priv, pipe);
040484af 3254 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3255 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3256
0b8765c6 3257 intel_crtc_load_lut(crtc);
bed4a673 3258 intel_update_fbc(dev);
79e53945 3259
0b8765c6
JB		 3260 /* Give the overlay scaler a chance to enable if it's on this pipe */
3261 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3262 intel_crtc_update_cursor(crtc, true);
0b8765c6 3263}
79e53945 3264
0b8765c6
JB		 3265static void i9xx_crtc_disable(struct drm_crtc *crtc)
3266{
3267 struct drm_device *dev = crtc->dev;
3268 struct drm_i915_private *dev_priv = dev->dev_private;
3269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3270 int pipe = intel_crtc->pipe;
3271 int plane = intel_crtc->plane;
b690e96c 3272
f7abfe8b
CW		 3273 if (!intel_crtc->active)
3274 return;
3275
0b8765c6 3276 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3277 intel_crtc_wait_for_pending_flips(crtc);
3278 drm_vblank_off(dev, pipe);
0b8765c6 3279 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3280 intel_crtc_update_cursor(crtc, false);
0b8765c6 3281
973d04f9
CW		 3282 if (dev_priv->cfb_plane == plane)
3283 intel_disable_fbc(dev);
79e53945 3284
b24e7179 3285 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3286 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3287 intel_disable_pll(dev_priv, pipe);
0b8765c6 3288
f7abfe8b 3289 intel_crtc->active = false;
6b383a7f
CW		 3290 intel_update_fbc(dev);
3291 intel_update_watermarks(dev);
3292 intel_clear_scanline_wait(dev);
0b8765c6
JB		 3293}
3294
3295static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3296{
3297 /* XXX: When our outputs are all unaware of DPMS modes other than off
3298 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3299 */
3300 switch (mode) {
3301 case DRM_MODE_DPMS_ON:
3302 case DRM_MODE_DPMS_STANDBY:
3303 case DRM_MODE_DPMS_SUSPEND:
3304 i9xx_crtc_enable(crtc);
3305 break;
3306 case DRM_MODE_DPMS_OFF:
3307 i9xx_crtc_disable(crtc);
79e53945
JB		 3308 break;
3309 }
2c07245f
ZW		 3310}
3311
3312/**
3313 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3314 */
3315static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3316{
3317 struct drm_device *dev = crtc->dev;
e70236a8 3318 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3319 struct drm_i915_master_private *master_priv;
3320 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3321 int pipe = intel_crtc->pipe;
3322 bool enabled;
3323
032d2a0d
CW		 3324 if (intel_crtc->dpms_mode == mode)
3325 return;
3326
65655d4a 3327 intel_crtc->dpms_mode = mode;
debcaddc 3328
e70236a8 3329 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3330
3331 if (!dev->primary->master)
3332 return;
3333
3334 master_priv = dev->primary->master->driver_priv;
3335 if (!master_priv->sarea_priv)
3336 return;
3337
3338 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3339
3340 switch (pipe) {
3341 case 0:
3342 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3343 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3344 break;
3345 case 1:
3346 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3347 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3348 break;
3349 default:
9db4a9c7 3350 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3351 break;
3352 }
79e53945
JB		 3353}
3354
cdd59983
CW		 3355static void intel_crtc_disable(struct drm_crtc *crtc)
3356{
3357 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3358 struct drm_device *dev = crtc->dev;
3359
3360 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
931872fc
CW		 3361 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3362 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3363
3364 if (crtc->fb) {
3365 mutex_lock(&dev->struct_mutex);
1690e1eb 3366 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983
CW		 3367 mutex_unlock(&dev->struct_mutex);
3368 }
3369}
3370
7e7d76c3
JB		 3371/* Prepare for a mode set.
3372 *
3373 * Note we could be a lot smarter here. We need to figure out which outputs
3374 * will be enabled, which disabled (in short, how the config will changes)
3375 * and perform the minimum necessary steps to accomplish that, e.g. updating
3376 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3377 * panel fitting is in the proper state, etc.
3378 */
3379static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3380{
7e7d76c3 3381 i9xx_crtc_disable(crtc);
79e53945
JB		 3382}
3383
7e7d76c3 3384static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3385{
7e7d76c3 3386 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3387}
3388
3389static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3390{
7e7d76c3 3391 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3392}
3393
3394static void ironlake_crtc_commit(struct drm_crtc *crtc)
3395{
7e7d76c3 3396 ironlake_crtc_enable(crtc);
79e53945
JB		 3397}
3398
0206e353 3399void intel_encoder_prepare(struct drm_encoder *encoder)
79e53945
JB		 3400{
3401 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3402 /* lvds has its own version of prepare see intel_lvds_prepare */
3403 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3404}
3405
0206e353 3406void intel_encoder_commit(struct drm_encoder *encoder)
79e53945
JB		 3407{
3408 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
d4270e57
JB		 3409 struct drm_device *dev = encoder->dev;
3410 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3411 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3412
79e53945
JB		 3413 /* lvds has its own version of commit see intel_lvds_commit */
3414 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
d4270e57
JB		 3415
3416 if (HAS_PCH_CPT(dev))
3417 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
79e53945
JB		 3418}
3419
ea5b213a
CW		 3420void intel_encoder_destroy(struct drm_encoder *encoder)
3421{
4ef69c7a 3422 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3423
ea5b213a
CW		 3424 drm_encoder_cleanup(encoder);
3425 kfree(intel_encoder);
3426}
3427
79e53945
JB		 3428static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3429 struct drm_display_mode *mode,
3430 struct drm_display_mode *adjusted_mode)
3431{
2c07245f 3432 struct drm_device *dev = crtc->dev;
89749350 3433
bad720ff 3434 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3435 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3436 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3437 return false;
2c07245f 3438 }
89749350 3439
ca9bfa7e
DV		 3440 /* All interlaced capable intel hw wants timings in frames. */
3441 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3442
79e53945
JB		 3443 return true;
3444}
3445
e70236a8
JB		 3446static int i945_get_display_clock_speed(struct drm_device *dev)
3447{
3448 return 400000;
3449}
79e53945 3450
e70236a8 3451static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3452{
e70236a8
JB		 3453 return 333000;
3454}
79e53945 3455
e70236a8
JB		 3456static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3457{
3458 return 200000;
3459}
79e53945 3460
e70236a8
JB		 3461static int i915gm_get_display_clock_speed(struct drm_device *dev)
3462{
3463 u16 gcfgc = 0;
79e53945 3464
e70236a8
JB		 3465 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3466
3467 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3468 return 133000;
3469 else {
3470 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3471 case GC_DISPLAY_CLOCK_333_MHZ:
3472 return 333000;
3473 default:
3474 case GC_DISPLAY_CLOCK_190_200_MHZ:
3475 return 190000;
79e53945 3476 }
e70236a8
JB		 3477 }
3478}
3479
3480static int i865_get_display_clock_speed(struct drm_device *dev)
3481{
3482 return 266000;
3483}
3484
3485static int i855_get_display_clock_speed(struct drm_device *dev)
3486{
3487 u16 hpllcc = 0;
3488 /* Assume that the hardware is in the high speed state. This
3489 * should be the default.
3490 */
3491 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3492 case GC_CLOCK_133_200:
3493 case GC_CLOCK_100_200:
3494 return 200000;
3495 case GC_CLOCK_166_250:
3496 return 250000;
3497 case GC_CLOCK_100_133:
79e53945 3498 return 133000;
e70236a8 3499 }
79e53945 3500
e70236a8
JB		 3501 /* Shouldn't happen */
3502 return 0;
3503}
79e53945 3504
e70236a8
JB		 3505static int i830_get_display_clock_speed(struct drm_device *dev)
3506{
3507 return 133000;
79e53945
JB		 3508}
3509
2c07245f
ZW		 3510struct fdi_m_n {
3511 u32 tu;
3512 u32 gmch_m;
3513 u32 gmch_n;
3514 u32 link_m;
3515 u32 link_n;
3516};
3517
3518static void
3519fdi_reduce_ratio(u32 *num, u32 *den)
3520{
3521 while (*num > 0xffffff || *den > 0xffffff) {
3522 *num >>= 1;
3523 *den >>= 1;
3524 }
3525}
3526
2c07245f 3527static void
f2b115e6
AJ		 3528ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3529 int link_clock, struct fdi_m_n *m_n)
2c07245f 3530{
2c07245f
ZW		 3531 m_n->tu = 64; /* default size */
3532
22ed1113
CW		 3533 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3534 m_n->gmch_m = bits_per_pixel * pixel_clock;
3535 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3536 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3537
22ed1113
CW		 3538 m_n->link_m = pixel_clock;
3539 m_n->link_n = link_clock;
2c07245f
ZW		 3540 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3541}
3542
3543
7662c8bd
SL		 3544struct intel_watermark_params {
3545 unsigned long fifo_size;
3546 unsigned long max_wm;
3547 unsigned long default_wm;
3548 unsigned long guard_size;
3549 unsigned long cacheline_size;
3550};
3551
f2b115e6 3552/* Pineview has different values for various configs */
d210246a 3553static const struct intel_watermark_params pineview_display_wm = {
f2b115e6
AJ		 3554 PINEVIEW_DISPLAY_FIFO,
3555 PINEVIEW_MAX_WM,
3556 PINEVIEW_DFT_WM,
3557 PINEVIEW_GUARD_WM,
3558 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3559};
d210246a 3560static const struct intel_watermark_params pineview_display_hplloff_wm = {
f2b115e6
AJ		 3561 PINEVIEW_DISPLAY_FIFO,
3562 PINEVIEW_MAX_WM,
3563 PINEVIEW_DFT_HPLLOFF_WM,
3564 PINEVIEW_GUARD_WM,
3565 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3566};
d210246a 3567static const struct intel_watermark_params pineview_cursor_wm = {
f2b115e6
AJ		 3568 PINEVIEW_CURSOR_FIFO,
3569 PINEVIEW_CURSOR_MAX_WM,
3570 PINEVIEW_CURSOR_DFT_WM,
3571 PINEVIEW_CURSOR_GUARD_WM,
3572 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 3573};
d210246a 3574static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
f2b115e6
AJ		 3575 PINEVIEW_CURSOR_FIFO,
3576 PINEVIEW_CURSOR_MAX_WM,
3577 PINEVIEW_CURSOR_DFT_WM,
3578 PINEVIEW_CURSOR_GUARD_WM,
3579 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3580};
d210246a 3581static const struct intel_watermark_params g4x_wm_info = {
0e442c60
JB		 3582 G4X_FIFO_SIZE,
3583 G4X_MAX_WM,
3584 G4X_MAX_WM,
3585 2,
3586 G4X_FIFO_LINE_SIZE,
3587};
d210246a 3588static const struct intel_watermark_params g4x_cursor_wm_info = {
4fe5e611
ZY		 3589 I965_CURSOR_FIFO,
3590 I965_CURSOR_MAX_WM,
3591 I965_CURSOR_DFT_WM,
3592 2,
3593 G4X_FIFO_LINE_SIZE,
3594};
d210246a 3595static const struct intel_watermark_params i965_cursor_wm_info = {
4fe5e611
ZY		 3596 I965_CURSOR_FIFO,
3597 I965_CURSOR_MAX_WM,
3598 I965_CURSOR_DFT_WM,
3599 2,
3600 I915_FIFO_LINE_SIZE,
3601};
d210246a 3602static const struct intel_watermark_params i945_wm_info = {
dff33cfc 3603 I945_FIFO_SIZE,
7662c8bd
SL		 3604 I915_MAX_WM,
3605 1,
dff33cfc
JB		 3606 2,
3607 I915_FIFO_LINE_SIZE
7662c8bd 3608};
d210246a 3609static const struct intel_watermark_params i915_wm_info = {
dff33cfc 3610 I915_FIFO_SIZE,
7662c8bd
SL		 3611 I915_MAX_WM,
3612 1,
dff33cfc 3613 2,
7662c8bd
SL		 3614 I915_FIFO_LINE_SIZE
3615};
d210246a 3616static const struct intel_watermark_params i855_wm_info = {
7662c8bd
SL		 3617 I855GM_FIFO_SIZE,
3618 I915_MAX_WM,
3619 1,
dff33cfc 3620 2,
7662c8bd
SL		 3621 I830_FIFO_LINE_SIZE
3622};
d210246a 3623static const struct intel_watermark_params i830_wm_info = {
7662c8bd
SL		 3624 I830_FIFO_SIZE,
3625 I915_MAX_WM,
3626 1,
dff33cfc 3627 2,
7662c8bd
SL		 3628 I830_FIFO_LINE_SIZE
3629};
3630
d210246a 3631static const struct intel_watermark_params ironlake_display_wm_info = {
7f8a8569
ZW		 3632 ILK_DISPLAY_FIFO,
3633 ILK_DISPLAY_MAXWM,
3634 ILK_DISPLAY_DFTWM,
3635 2,
3636 ILK_FIFO_LINE_SIZE
3637};
d210246a 3638static const struct intel_watermark_params ironlake_cursor_wm_info = {
c936f44d
ZY		 3639 ILK_CURSOR_FIFO,
3640 ILK_CURSOR_MAXWM,
3641 ILK_CURSOR_DFTWM,
3642 2,
3643 ILK_FIFO_LINE_SIZE
3644};
d210246a 3645static const struct intel_watermark_params ironlake_display_srwm_info = {
7f8a8569
ZW		 3646 ILK_DISPLAY_SR_FIFO,
3647 ILK_DISPLAY_MAX_SRWM,
3648 ILK_DISPLAY_DFT_SRWM,
3649 2,
3650 ILK_FIFO_LINE_SIZE
3651};
d210246a 3652static const struct intel_watermark_params ironlake_cursor_srwm_info = {
7f8a8569
ZW		 3653 ILK_CURSOR_SR_FIFO,
3654 ILK_CURSOR_MAX_SRWM,
3655 ILK_CURSOR_DFT_SRWM,
3656 2,
3657 ILK_FIFO_LINE_SIZE
3658};
3659
d210246a 3660static const struct intel_watermark_params sandybridge_display_wm_info = {
1398261a
YL		 3661 SNB_DISPLAY_FIFO,
3662 SNB_DISPLAY_MAXWM,
3663 SNB_DISPLAY_DFTWM,
3664 2,
3665 SNB_FIFO_LINE_SIZE
3666};
d210246a 3667static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1398261a
YL		 3668 SNB_CURSOR_FIFO,
3669 SNB_CURSOR_MAXWM,
3670 SNB_CURSOR_DFTWM,
3671 2,
3672 SNB_FIFO_LINE_SIZE
3673};
d210246a 3674static const struct intel_watermark_params sandybridge_display_srwm_info = {
1398261a
YL		 3675 SNB_DISPLAY_SR_FIFO,
3676 SNB_DISPLAY_MAX_SRWM,
3677 SNB_DISPLAY_DFT_SRWM,
3678 2,
3679 SNB_FIFO_LINE_SIZE
3680};
d210246a 3681static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1398261a
YL		 3682 SNB_CURSOR_SR_FIFO,
3683 SNB_CURSOR_MAX_SRWM,
3684 SNB_CURSOR_DFT_SRWM,
3685 2,
3686 SNB_FIFO_LINE_SIZE
3687};
3688
3689
dff33cfc
JB		 3690/**
3691 * intel_calculate_wm - calculate watermark level
3692 * @clock_in_khz: pixel clock
3693 * @wm: chip FIFO params
3694 * @pixel_size: display pixel size
3695 * @latency_ns: memory latency for the platform
3696 *
3697 * Calculate the watermark level (the level at which the display plane will
3698 * start fetching from memory again). Each chip has a different display
3699 * FIFO size and allocation, so the caller needs to figure that out and pass
3700 * in the correct intel_watermark_params structure.
3701 *
3702 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3703 * on the pixel size. When it reaches the watermark level, it'll start
3704 * fetching FIFO line sized based chunks from memory until the FIFO fills
3705 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3706 * will occur, and a display engine hang could result.
3707 */
7662c8bd 3708static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
d210246a
CW		 3709 const struct intel_watermark_params *wm,
3710 int fifo_size,
7662c8bd
SL		 3711 int pixel_size,
3712 unsigned long latency_ns)
3713{
390c4dd4 3714 long entries_required, wm_size;
dff33cfc 3715
d660467c
JB		 3716 /*
3717 * Note: we need to make sure we don't overflow for various clock &
3718 * latency values.
3719 * clocks go from a few thousand to several hundred thousand.
3720 * latency is usually a few thousand
3721 */
3722 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3723 1000;
8de9b311 3724 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 3725
bbb0aef5 3726 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
dff33cfc 3727
d210246a 3728 wm_size = fifo_size - (entries_required + wm->guard_size);
dff33cfc 3729
bbb0aef5 3730 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
7662c8bd 3731
390c4dd4
JB		 3732 /* Don't promote wm_size to unsigned... */
3733 if (wm_size > (long)wm->max_wm)
7662c8bd 3734 wm_size = wm->max_wm;
c3add4b6 3735 if (wm_size <= 0)
7662c8bd
SL		 3736 wm_size = wm->default_wm;
3737 return wm_size;
3738}
3739
3740struct cxsr_latency {
3741 int is_desktop;
95534263 3742 int is_ddr3;
7662c8bd
SL		 3743 unsigned long fsb_freq;
3744 unsigned long mem_freq;
3745 unsigned long display_sr;
3746 unsigned long display_hpll_disable;
3747 unsigned long cursor_sr;
3748 unsigned long cursor_hpll_disable;
3749};
3750
403c89ff 3751static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP		 3752 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3753 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3754 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3755 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3756 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3757
3758 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3759 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3760 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3761 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3762 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3763
3764 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3765 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3766 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3767 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3768 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3769
3770 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3771 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3772 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3773 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3774 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3775
3776 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3777 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3778 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3779 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3780 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3781
3782 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3783 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3784 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3785 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3786 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL		 3787};
3788
403c89ff
CW		 3789static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3790 int is_ddr3,
3791 int fsb,
3792 int mem)
7662c8bd 3793{
403c89ff 3794 const struct cxsr_latency *latency;
7662c8bd 3795 int i;
7662c8bd
SL		 3796
3797 if (fsb == 0 || mem == 0)
3798 return NULL;
3799
3800 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3801 latency = &cxsr_latency_table[i];
3802 if (is_desktop == latency->is_desktop &&
95534263 3803 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR		 3804 fsb == latency->fsb_freq && mem == latency->mem_freq)
3805 return latency;
7662c8bd 3806 }
decbbcda 3807
28c97730 3808 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR		 3809
3810 return NULL;
7662c8bd
SL		 3811}
3812
f2b115e6 3813static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL		 3814{
3815 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL		 3816
3817 /* deactivate cxsr */
3e33d94d 3818 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL		 3819}
3820
bcc24fb4
JB		 3821/*
3822 * Latency for FIFO fetches is dependent on several factors:
3823 * - memory configuration (speed, channels)
3824 * - chipset
3825 * - current MCH state
3826 * It can be fairly high in some situations, so here we assume a fairly
3827 * pessimal value. It's a tradeoff between extra memory fetches (if we
3828 * set this value too high, the FIFO will fetch frequently to stay full)
3829 * and power consumption (set it too low to save power and we might see
3830 * FIFO underruns and display "flicker").
3831 *
3832 * A value of 5us seems to be a good balance; safe for very low end
3833 * platforms but not overly aggressive on lower latency configs.
3834 */
69e302a9 3835static const int latency_ns = 5000;
7662c8bd 3836
e70236a8 3837static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB		 3838{
3839 struct drm_i915_private *dev_priv = dev->dev_private;
3840 uint32_t dsparb = I915_READ(DSPARB);
3841 int size;
3842
8de9b311
CW		 3843 size = dsparb & 0x7f;
3844 if (plane)
3845 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 3846
28c97730 3847 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3848 plane ? "B" : "A", size);
dff33cfc
JB		 3849
3850 return size;
3851}
7662c8bd 3852
e70236a8
JB		 3853static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3854{
3855 struct drm_i915_private *dev_priv = dev->dev_private;
3856 uint32_t dsparb = I915_READ(DSPARB);
3857 int size;
3858
8de9b311
CW		 3859 size = dsparb & 0x1ff;
3860 if (plane)
3861 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 3862 size >>= 1; /* Convert to cachelines */
dff33cfc 3863
28c97730 3864 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3865 plane ? "B" : "A", size);
dff33cfc
JB		 3866
3867 return size;
3868}
7662c8bd 3869
e70236a8
JB		 3870static int i845_get_fifo_size(struct drm_device *dev, int plane)
3871{
3872 struct drm_i915_private *dev_priv = dev->dev_private;
3873 uint32_t dsparb = I915_READ(DSPARB);
3874 int size;
3875
3876 size = dsparb & 0x7f;
3877 size >>= 2; /* Convert to cachelines */
3878
28c97730 3879 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW		 3880 plane ? "B" : "A",
3881 size);
e70236a8
JB		 3882
3883 return size;
3884}
3885
3886static int i830_get_fifo_size(struct drm_device *dev, int plane)
3887{
3888 struct drm_i915_private *dev_priv = dev->dev_private;
3889 uint32_t dsparb = I915_READ(DSPARB);
3890 int size;
3891
3892 size = dsparb & 0x7f;
3893 size >>= 1; /* Convert to cachelines */
3894
28c97730 3895 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3896 plane ? "B" : "A", size);
e70236a8
JB		 3897
3898 return size;
3899}
3900
d210246a
CW		 3901static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3902{
3903 struct drm_crtc *crtc, *enabled = NULL;
3904
3905 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3906 if (crtc->enabled && crtc->fb) {
3907 if (enabled)
3908 return NULL;
3909 enabled = crtc;
3910 }
3911 }
3912
3913 return enabled;
3914}
3915
3916static void pineview_update_wm(struct drm_device *dev)
d4294342
ZY		 3917{
3918 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3919 struct drm_crtc *crtc;
403c89ff 3920 const struct cxsr_latency *latency;
d4294342
ZY		 3921 u32 reg;
3922 unsigned long wm;
d4294342 3923
403c89ff 3924 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 3925 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY		 3926 if (!latency) {
3927 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3928 pineview_disable_cxsr(dev);
3929 return;
3930 }
3931
d210246a
CW		 3932 crtc = single_enabled_crtc(dev);
3933 if (crtc) {
3934 int clock = crtc->mode.clock;
3935 int pixel_size = crtc->fb->bits_per_pixel / 8;
d4294342
ZY		 3936
3937 /* Display SR */
d210246a
CW		 3938 wm = intel_calculate_wm(clock, &pineview_display_wm,
3939 pineview_display_wm.fifo_size,
d4294342
ZY		 3940 pixel_size, latency->display_sr);
3941 reg = I915_READ(DSPFW1);
3942 reg &= ~DSPFW_SR_MASK;
3943 reg |= wm << DSPFW_SR_SHIFT;
3944 I915_WRITE(DSPFW1, reg);
3945 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3946
3947 /* cursor SR */
d210246a
CW		 3948 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3949 pineview_display_wm.fifo_size,
d4294342
ZY		 3950 pixel_size, latency->cursor_sr);
3951 reg = I915_READ(DSPFW3);
3952 reg &= ~DSPFW_CURSOR_SR_MASK;
3953 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3954 I915_WRITE(DSPFW3, reg);
3955
3956 /* Display HPLL off SR */
d210246a
CW		 3957 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3958 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3959 pixel_size, latency->display_hpll_disable);
3960 reg = I915_READ(DSPFW3);
3961 reg &= ~DSPFW_HPLL_SR_MASK;
3962 reg |= wm & DSPFW_HPLL_SR_MASK;
3963 I915_WRITE(DSPFW3, reg);
3964
3965 /* cursor HPLL off SR */
d210246a
CW		 3966 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3967 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3968 pixel_size, latency->cursor_hpll_disable);
3969 reg = I915_READ(DSPFW3);
3970 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3971 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3972 I915_WRITE(DSPFW3, reg);
3973 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3974
3975 /* activate cxsr */
3e33d94d
CW		 3976 I915_WRITE(DSPFW3,
3977 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY		 3978 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3979 } else {
3980 pineview_disable_cxsr(dev);
3981 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3982 }
3983}
3984
417ae147
CW		 3985static bool g4x_compute_wm0(struct drm_device *dev,
3986 int plane,
3987 const struct intel_watermark_params *display,
3988 int display_latency_ns,
3989 const struct intel_watermark_params *cursor,
3990 int cursor_latency_ns,
3991 int *plane_wm,
3992 int *cursor_wm)
3993{
3994 struct drm_crtc *crtc;
3995 int htotal, hdisplay, clock, pixel_size;
3996 int line_time_us, line_count;
3997 int entries, tlb_miss;
3998
3999 crtc = intel_get_crtc_for_plane(dev, plane);
5c72d064
CW		 4000 if (crtc->fb == NULL || !crtc->enabled) {
4001 *cursor_wm = cursor->guard_size;
4002 *plane_wm = display->guard_size;
417ae147 4003 return false;
5c72d064 4004 }
417ae147
CW		 4005
4006 htotal = crtc->mode.htotal;
4007 hdisplay = crtc->mode.hdisplay;
4008 clock = crtc->mode.clock;
4009 pixel_size = crtc->fb->bits_per_pixel / 8;
4010
4011 /* Use the small buffer method to calculate plane watermark */
4012 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4013 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
4014 if (tlb_miss > 0)
4015 entries += tlb_miss;
4016 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4017 *plane_wm = entries + display->guard_size;
4018 if (*plane_wm > (int)display->max_wm)
4019 *plane_wm = display->max_wm;
4020
4021 /* Use the large buffer method to calculate cursor watermark */
4022 line_time_us = ((htotal * 1000) / clock);
4023 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
4024 entries = line_count * 64 * pixel_size;
4025 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
4026 if (tlb_miss > 0)
4027 entries += tlb_miss;
4028 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4029 *cursor_wm = entries + cursor->guard_size;
4030 if (*cursor_wm > (int)cursor->max_wm)
4031 *cursor_wm = (int)cursor->max_wm;
4032
4033 return true;
4034}
4035
4036/*
4037 * Check the wm result.
4038 *
4039 * If any calculated watermark values is larger than the maximum value that
4040 * can be programmed into the associated watermark register, that watermark
4041 * must be disabled.
4042 */
4043static bool g4x_check_srwm(struct drm_device *dev,
4044 int display_wm, int cursor_wm,
4045 const struct intel_watermark_params *display,
4046 const struct intel_watermark_params *cursor)
652c393a 4047{
417ae147
CW		 4048 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4049 display_wm, cursor_wm);
652c393a 4050
417ae147 4051 if (display_wm > display->max_wm) {
bbb0aef5 4052 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 4053 display_wm, display->max_wm);
4054 return false;
4055 }
0e442c60 4056
417ae147 4057 if (cursor_wm > cursor->max_wm) {
bbb0aef5 4058 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 4059 cursor_wm, cursor->max_wm);
4060 return false;
4061 }
0e442c60 4062
417ae147
CW		 4063 if (!(display_wm || cursor_wm)) {
4064 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4065 return false;
4066 }
0e442c60 4067
417ae147
CW		 4068 return true;
4069}
0e442c60 4070
417ae147 4071static bool g4x_compute_srwm(struct drm_device *dev,
d210246a
CW		 4072 int plane,
4073 int latency_ns,
417ae147
CW		 4074 const struct intel_watermark_params *display,
4075 const struct intel_watermark_params *cursor,
4076 int *display_wm, int *cursor_wm)
4077{
d210246a
CW		 4078 struct drm_crtc *crtc;
4079 int hdisplay, htotal, pixel_size, clock;
417ae147
CW		 4080 unsigned long line_time_us;
4081 int line_count, line_size;
4082 int small, large;
4083 int entries;
0e442c60 4084
417ae147
CW		 4085 if (!latency_ns) {
4086 *display_wm = *cursor_wm = 0;
4087 return false;
4088 }
0e442c60 4089
d210246a
CW		 4090 crtc = intel_get_crtc_for_plane(dev, plane);
4091 hdisplay = crtc->mode.hdisplay;
4092 htotal = crtc->mode.htotal;
4093 clock = crtc->mode.clock;
4094 pixel_size = crtc->fb->bits_per_pixel / 8;
4095
417ae147
CW		 4096 line_time_us = (htotal * 1000) / clock;
4097 line_count = (latency_ns / line_time_us + 1000) / 1000;
4098 line_size = hdisplay * pixel_size;
0e442c60 4099
417ae147
CW		 4100 /* Use the minimum of the small and large buffer method for primary */
4101 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4102 large = line_count * line_size;
0e442c60 4103
417ae147
CW		 4104 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4105 *display_wm = entries + display->guard_size;
4fe5e611 4106
417ae147
CW		 4107 /* calculate the self-refresh watermark for display cursor */
4108 entries = line_count * pixel_size * 64;
4109 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4110 *cursor_wm = entries + cursor->guard_size;
4fe5e611 4111
417ae147
CW		 4112 return g4x_check_srwm(dev,
4113 *display_wm, *cursor_wm,
4114 display, cursor);
4115}
4fe5e611 4116
7ccb4a53 4117#define single_plane_enabled(mask) is_power_of_2(mask)
d210246a
CW		 4118
4119static void g4x_update_wm(struct drm_device *dev)
417ae147
CW		 4120{
4121 static const int sr_latency_ns = 12000;
4122 struct drm_i915_private *dev_priv = dev->dev_private;
4123 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
d210246a
CW		 4124 int plane_sr, cursor_sr;
4125 unsigned int enabled = 0;
417ae147
CW		 4126
4127 if (g4x_compute_wm0(dev, 0,
4128 &g4x_wm_info, latency_ns,
4129 &g4x_cursor_wm_info, latency_ns,
4130 &planea_wm, &cursora_wm))
d210246a 4131 enabled |= 1;
417ae147
CW		 4132
4133 if (g4x_compute_wm0(dev, 1,
4134 &g4x_wm_info, latency_ns,
4135 &g4x_cursor_wm_info, latency_ns,
4136 &planeb_wm, &cursorb_wm))
d210246a 4137 enabled |= 2;
417ae147
CW		 4138
4139 plane_sr = cursor_sr = 0;
d210246a
CW		 4140 if (single_plane_enabled(enabled) &&
4141 g4x_compute_srwm(dev, ffs(enabled) - 1,
4142 sr_latency_ns,
417ae147
CW		 4143 &g4x_wm_info,
4144 &g4x_cursor_wm_info,
4145 &plane_sr, &cursor_sr))
0e442c60 4146 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
417ae147
CW		 4147 else
4148 I915_WRITE(FW_BLC_SELF,
4149 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
0e442c60 4150
308977ac
CW		 4151 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4152 planea_wm, cursora_wm,
4153 planeb_wm, cursorb_wm,
4154 plane_sr, cursor_sr);
0e442c60 4155
417ae147
CW		 4156 I915_WRITE(DSPFW1,
4157 (plane_sr << DSPFW_SR_SHIFT) |
0e442c60 4158 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
417ae147
CW		 4159 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4160 planea_wm);
4161 I915_WRITE(DSPFW2,
4162 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
0e442c60
JB		 4163 (cursora_wm << DSPFW_CURSORA_SHIFT));
4164 /* HPLL off in SR has some issues on G4x... disable it */
417ae147
CW		 4165 I915_WRITE(DSPFW3,
4166 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
0e442c60 4167 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB		 4168}
4169
d210246a 4170static void i965_update_wm(struct drm_device *dev)
7662c8bd
SL		 4171{
4172 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4173 struct drm_crtc *crtc;
4174 int srwm = 1;
4fe5e611 4175 int cursor_sr = 16;
1dc7546d
JB		 4176
4177 /* Calc sr entries for one plane configs */
d210246a
CW		 4178 crtc = single_enabled_crtc(dev);
4179 if (crtc) {
1dc7546d 4180 /* self-refresh has much higher latency */
69e302a9 4181 static const int sr_latency_ns = 12000;
d210246a
CW		 4182 int clock = crtc->mode.clock;
4183 int htotal = crtc->mode.htotal;
4184 int hdisplay = crtc->mode.hdisplay;
4185 int pixel_size = crtc->fb->bits_per_pixel / 8;
4186 unsigned long line_time_us;
4187 int entries;
1dc7546d 4188
d210246a 4189 line_time_us = ((htotal * 1000) / clock);
1dc7546d
JB		 4190
4191 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4192 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4193 pixel_size * hdisplay;
4194 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
d210246a 4195 srwm = I965_FIFO_SIZE - entries;
1dc7546d
JB		 4196 if (srwm < 0)
4197 srwm = 1;
1b07e04e 4198 srwm &= 0x1ff;
308977ac
CW		 4199 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4200 entries, srwm);
4fe5e611 4201
d210246a 4202 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 4203 pixel_size * 64;
d210246a 4204 entries = DIV_ROUND_UP(entries,
8de9b311 4205 i965_cursor_wm_info.cacheline_size);
4fe5e611 4206 cursor_sr = i965_cursor_wm_info.fifo_size -
d210246a 4207 (entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY		 4208
4209 if (cursor_sr > i965_cursor_wm_info.max_wm)
4210 cursor_sr = i965_cursor_wm_info.max_wm;
4211
4212 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4213 "cursor %d\n", srwm, cursor_sr);
4214
a6c45cf0 4215 if (IS_CRESTLINE(dev))
adcdbc66 4216 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ		 4217 } else {
4218 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 4219 if (IS_CRESTLINE(dev))
adcdbc66
JB		 4220 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4221 & ~FW_BLC_SELF_EN);
1dc7546d 4222 }
7662c8bd 4223
1dc7546d
JB		 4224 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4225 srwm);
7662c8bd
SL		 4226
4227 /* 965 has limitations... */
417ae147
CW		 4228 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4229 (8 << 16) | (8 << 8) | (8 << 0));
7662c8bd 4230 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY		 4231 /* update cursor SR watermark */
4232 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL		 4233}
4234
d210246a 4235static void i9xx_update_wm(struct drm_device *dev)
7662c8bd
SL		 4236{
4237 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 4238 const struct intel_watermark_params *wm_info;
dff33cfc
JB		 4239 uint32_t fwater_lo;
4240 uint32_t fwater_hi;
d210246a
CW		 4241 int cwm, srwm = 1;
4242 int fifo_size;
dff33cfc 4243 int planea_wm, planeb_wm;
d210246a 4244 struct drm_crtc *crtc, *enabled = NULL;
7662c8bd 4245
72557b4f 4246 if (IS_I945GM(dev))
d210246a 4247 wm_info = &i945_wm_info;
a6c45cf0 4248 else if (!IS_GEN2(dev))
d210246a 4249 wm_info = &i915_wm_info;
7662c8bd 4250 else
d210246a
CW		 4251 wm_info = &i855_wm_info;
4252
4253 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4254 crtc = intel_get_crtc_for_plane(dev, 0);
4255 if (crtc->enabled && crtc->fb) {
4256 planea_wm = intel_calculate_wm(crtc->mode.clock,
4257 wm_info, fifo_size,
4258 crtc->fb->bits_per_pixel / 8,
4259 latency_ns);
4260 enabled = crtc;
4261 } else
4262 planea_wm = fifo_size - wm_info->guard_size;
4263
4264 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4265 crtc = intel_get_crtc_for_plane(dev, 1);
4266 if (crtc->enabled && crtc->fb) {
4267 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4268 wm_info, fifo_size,
4269 crtc->fb->bits_per_pixel / 8,
4270 latency_ns);
4271 if (enabled == NULL)
4272 enabled = crtc;
4273 else
4274 enabled = NULL;
4275 } else
4276 planeb_wm = fifo_size - wm_info->guard_size;
7662c8bd 4277
28c97730 4278 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL		 4279
4280 /*
4281 * Overlay gets an aggressive default since video jitter is bad.
4282 */
4283 cwm = 2;
4284
18b2190c
AL		 4285 /* Play safe and disable self-refresh before adjusting watermarks. */
4286 if (IS_I945G(dev) || IS_I945GM(dev))
4287 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4288 else if (IS_I915GM(dev))
4289 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4290
dff33cfc 4291 /* Calc sr entries for one plane configs */
d210246a 4292 if (HAS_FW_BLC(dev) && enabled) {
dff33cfc 4293 /* self-refresh has much higher latency */
69e302a9 4294 static const int sr_latency_ns = 6000;
d210246a
CW		 4295 int clock = enabled->mode.clock;
4296 int htotal = enabled->mode.htotal;
4297 int hdisplay = enabled->mode.hdisplay;
4298 int pixel_size = enabled->fb->bits_per_pixel / 8;
4299 unsigned long line_time_us;
4300 int entries;
dff33cfc 4301
d210246a 4302 line_time_us = (htotal * 1000) / clock;
dff33cfc
JB		 4303
4304 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4305 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4306 pixel_size * hdisplay;
4307 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4308 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4309 srwm = wm_info->fifo_size - entries;
dff33cfc
JB		 4310 if (srwm < 0)
4311 srwm = 1;
ee980b80
LP		 4312
4313 if (IS_I945G(dev) || IS_I945GM(dev))
18b2190c
AL		 4314 I915_WRITE(FW_BLC_SELF,
4315 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4316 else if (IS_I915GM(dev))
ee980b80 4317 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
7662c8bd
SL		 4318 }
4319
28c97730 4320 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 4321 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 4322
dff33cfc
JB		 4323 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4324 fwater_hi = (cwm & 0x1f);
4325
4326 /* Set request length to 8 cachelines per fetch */
4327 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4328 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL		 4329
4330 I915_WRITE(FW_BLC, fwater_lo);
4331 I915_WRITE(FW_BLC2, fwater_hi);
18b2190c 4332
d210246a
CW		 4333 if (HAS_FW_BLC(dev)) {
4334 if (enabled) {
4335 if (IS_I945G(dev) || IS_I945GM(dev))
4336 I915_WRITE(FW_BLC_SELF,
4337 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4338 else if (IS_I915GM(dev))
4339 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4340 DRM_DEBUG_KMS("memory self refresh enabled\n");
4341 } else
4342 DRM_DEBUG_KMS("memory self refresh disabled\n");
4343 }
7662c8bd
SL		 4344}
4345
d210246a 4346static void i830_update_wm(struct drm_device *dev)
7662c8bd
SL		 4347{
4348 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4349 struct drm_crtc *crtc;
4350 uint32_t fwater_lo;
dff33cfc 4351 int planea_wm;
7662c8bd 4352
d210246a
CW		 4353 crtc = single_enabled_crtc(dev);
4354 if (crtc == NULL)
4355 return;
7662c8bd 4356
d210246a
CW		 4357 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4358 dev_priv->display.get_fifo_size(dev, 0),
4359 crtc->fb->bits_per_pixel / 8,
4360 latency_ns);
4361 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
f3601326
JB		 4362 fwater_lo |= (3<<8) | planea_wm;
4363
28c97730 4364 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL		 4365
4366 I915_WRITE(FW_BLC, fwater_lo);
4367}
4368
7f8a8569 4369#define ILK_LP0_PLANE_LATENCY 700
c936f44d 4370#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 4371
1398261a
YL		 4372/*
4373 * Check the wm result.
4374 *
4375 * If any calculated watermark values is larger than the maximum value that
4376 * can be programmed into the associated watermark register, that watermark
4377 * must be disabled.
1398261a 4378 */
b79d4990
JB		 4379static bool ironlake_check_srwm(struct drm_device *dev, int level,
4380 int fbc_wm, int display_wm, int cursor_wm,
4381 const struct intel_watermark_params *display,
4382 const struct intel_watermark_params *cursor)
1398261a
YL		 4383{
4384 struct drm_i915_private *dev_priv = dev->dev_private;
4385
4386 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4387 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4388
4389 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4390 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4391 fbc_wm, SNB_FBC_MAX_SRWM, level);
1398261a
YL		 4392
4393 /* fbc has it's own way to disable FBC WM */
4394 I915_WRITE(DISP_ARB_CTL,
4395 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4396 return false;
4397 }
4398
b79d4990 4399 if (display_wm > display->max_wm) {
1398261a 4400 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4401 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1398261a
YL		 4402 return false;
4403 }
4404
b79d4990 4405 if (cursor_wm > cursor->max_wm) {
1398261a 4406 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4407 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1398261a
YL		 4408 return false;
4409 }
4410
4411 if (!(fbc_wm || display_wm || cursor_wm)) {
4412 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4413 return false;
4414 }
4415
4416 return true;
4417}
4418
4419/*
4420 * Compute watermark values of WM[1-3],
4421 */
d210246a
CW		 4422static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4423 int latency_ns,
b79d4990
JB		 4424 const struct intel_watermark_params *display,
4425 const struct intel_watermark_params *cursor,
4426 int *fbc_wm, int *display_wm, int *cursor_wm)
1398261a 4427{
d210246a 4428 struct drm_crtc *crtc;
1398261a 4429 unsigned long line_time_us;
d210246a 4430 int hdisplay, htotal, pixel_size, clock;
b79d4990 4431 int line_count, line_size;
1398261a
YL		 4432 int small, large;
4433 int entries;
1398261a
YL		 4434
4435 if (!latency_ns) {
4436 *fbc_wm = *display_wm = *cursor_wm = 0;
4437 return false;
4438 }
4439
d210246a
CW		 4440 crtc = intel_get_crtc_for_plane(dev, plane);
4441 hdisplay = crtc->mode.hdisplay;
4442 htotal = crtc->mode.htotal;
4443 clock = crtc->mode.clock;
4444 pixel_size = crtc->fb->bits_per_pixel / 8;
4445
1398261a
YL		 4446 line_time_us = (htotal * 1000) / clock;
4447 line_count = (latency_ns / line_time_us + 1000) / 1000;
4448 line_size = hdisplay * pixel_size;
4449
4450 /* Use the minimum of the small and large buffer method for primary */
4451 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4452 large = line_count * line_size;
4453
b79d4990
JB		 4454 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4455 *display_wm = entries + display->guard_size;
1398261a
YL		 4456
4457 /*
b79d4990 4458 * Spec says:
1398261a
YL		 4459 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4460 */
4461 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4462
4463 /* calculate the self-refresh watermark for display cursor */
4464 entries = line_count * pixel_size * 64;
b79d4990
JB		 4465 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4466 *cursor_wm = entries + cursor->guard_size;
1398261a 4467
b79d4990
JB		 4468 return ironlake_check_srwm(dev, level,
4469 *fbc_wm, *display_wm, *cursor_wm,
4470 display, cursor);
4471}
4472
d210246a 4473static void ironlake_update_wm(struct drm_device *dev)
b79d4990
JB		 4474{
4475 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4476 int fbc_wm, plane_wm, cursor_wm;
4477 unsigned int enabled;
b79d4990
JB		 4478
4479 enabled = 0;
9f405100
CW		 4480 if (g4x_compute_wm0(dev, 0,
4481 &ironlake_display_wm_info,
4482 ILK_LP0_PLANE_LATENCY,
4483 &ironlake_cursor_wm_info,
4484 ILK_LP0_CURSOR_LATENCY,
4485 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4486 I915_WRITE(WM0_PIPEA_ILK,
4487 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4488 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4489 " plane %d, " "cursor: %d\n",
4490 plane_wm, cursor_wm);
d210246a 4491 enabled |= 1;
b79d4990
JB		 4492 }
4493
9f405100
CW		 4494 if (g4x_compute_wm0(dev, 1,
4495 &ironlake_display_wm_info,
4496 ILK_LP0_PLANE_LATENCY,
4497 &ironlake_cursor_wm_info,
4498 ILK_LP0_CURSOR_LATENCY,
4499 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4500 I915_WRITE(WM0_PIPEB_ILK,
4501 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4502 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4503 " plane %d, cursor: %d\n",
4504 plane_wm, cursor_wm);
d210246a 4505 enabled |= 2;
b79d4990
JB		 4506 }
4507
4508 /*
4509 * Calculate and update the self-refresh watermark only when one
4510 * display plane is used.
4511 */
4512 I915_WRITE(WM3_LP_ILK, 0);
4513 I915_WRITE(WM2_LP_ILK, 0);
4514 I915_WRITE(WM1_LP_ILK, 0);
4515
d210246a 4516 if (!single_plane_enabled(enabled))
b79d4990 4517 return;
d210246a 4518 enabled = ffs(enabled) - 1;
b79d4990
JB		 4519
4520 /* WM1 */
d210246a
CW		 4521 if (!ironlake_compute_srwm(dev, 1, enabled,
4522 ILK_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4523 &ironlake_display_srwm_info,
4524 &ironlake_cursor_srwm_info,
4525 &fbc_wm, &plane_wm, &cursor_wm))
4526 return;
4527
4528 I915_WRITE(WM1_LP_ILK,
4529 WM1_LP_SR_EN |
4530 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4531 (fbc_wm << WM1_LP_FBC_SHIFT) |
4532 (plane_wm << WM1_LP_SR_SHIFT) |
4533 cursor_wm);
4534
4535 /* WM2 */
d210246a
CW		 4536 if (!ironlake_compute_srwm(dev, 2, enabled,
4537 ILK_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4538 &ironlake_display_srwm_info,
4539 &ironlake_cursor_srwm_info,
4540 &fbc_wm, &plane_wm, &cursor_wm))
4541 return;
4542
4543 I915_WRITE(WM2_LP_ILK,
4544 WM2_LP_EN |
4545 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4546 (fbc_wm << WM1_LP_FBC_SHIFT) |
4547 (plane_wm << WM1_LP_SR_SHIFT) |
4548 cursor_wm);
4549
4550 /*
4551 * WM3 is unsupported on ILK, probably because we don't have latency
4552 * data for that power state
4553 */
1398261a
YL		 4554}
4555
b840d907 4556void sandybridge_update_wm(struct drm_device *dev)
1398261a
YL		 4557{
4558 struct drm_i915_private *dev_priv = dev->dev_private;
a0fa62d3 4559 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
47842649 4560 u32 val;
d210246a
CW		 4561 int fbc_wm, plane_wm, cursor_wm;
4562 unsigned int enabled;
1398261a
YL		 4563
4564 enabled = 0;
9f405100
CW		 4565 if (g4x_compute_wm0(dev, 0,
4566 &sandybridge_display_wm_info, latency,
4567 &sandybridge_cursor_wm_info, latency,
4568 &plane_wm, &cursor_wm)) {
47842649
JB		 4569 val = I915_READ(WM0_PIPEA_ILK);
4570 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4571 I915_WRITE(WM0_PIPEA_ILK, val |
4572 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1398261a
YL		 4573 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4574 " plane %d, " "cursor: %d\n",
4575 plane_wm, cursor_wm);
d210246a 4576 enabled |= 1;
1398261a
YL		 4577 }
4578
9f405100
CW		 4579 if (g4x_compute_wm0(dev, 1,
4580 &sandybridge_display_wm_info, latency,
4581 &sandybridge_cursor_wm_info, latency,
4582 &plane_wm, &cursor_wm)) {
47842649
JB		 4583 val = I915_READ(WM0_PIPEB_ILK);
4584 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4585 I915_WRITE(WM0_PIPEB_ILK, val |
4586 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1398261a
YL		 4587 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4588 " plane %d, cursor: %d\n",
4589 plane_wm, cursor_wm);
d210246a 4590 enabled |= 2;
1398261a
YL		 4591 }
4592
d6c892df
JB		 4593 /* IVB has 3 pipes */
4594 if (IS_IVYBRIDGE(dev) &&
4595 g4x_compute_wm0(dev, 2,
4596 &sandybridge_display_wm_info, latency,
4597 &sandybridge_cursor_wm_info, latency,
4598 &plane_wm, &cursor_wm)) {
47842649
JB		 4599 val = I915_READ(WM0_PIPEC_IVB);
4600 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
4601 I915_WRITE(WM0_PIPEC_IVB, val |
4602 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
d6c892df
JB		 4603 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4604 " plane %d, cursor: %d\n",
4605 plane_wm, cursor_wm);
4606 enabled |= 3;
4607 }
4608
1398261a
YL		 4609 /*
4610 * Calculate and update the self-refresh watermark only when one
4611 * display plane is used.
4612 *
4613 * SNB support 3 levels of watermark.
4614 *
4615 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4616 * and disabled in the descending order
4617 *
4618 */
4619 I915_WRITE(WM3_LP_ILK, 0);
4620 I915_WRITE(WM2_LP_ILK, 0);
4621 I915_WRITE(WM1_LP_ILK, 0);
4622
b840d907
JB		 4623 if (!single_plane_enabled(enabled) ||
4624 dev_priv->sprite_scaling_enabled)
1398261a 4625 return;
d210246a 4626 enabled = ffs(enabled) - 1;
1398261a
YL		 4627
4628 /* WM1 */
d210246a
CW		 4629 if (!ironlake_compute_srwm(dev, 1, enabled,
4630 SNB_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4631 &sandybridge_display_srwm_info,
4632 &sandybridge_cursor_srwm_info,
4633 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4634 return;
4635
4636 I915_WRITE(WM1_LP_ILK,
4637 WM1_LP_SR_EN |
4638 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4639 (fbc_wm << WM1_LP_FBC_SHIFT) |
4640 (plane_wm << WM1_LP_SR_SHIFT) |
4641 cursor_wm);
4642
4643 /* WM2 */
d210246a
CW		 4644 if (!ironlake_compute_srwm(dev, 2, enabled,
4645 SNB_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4646 &sandybridge_display_srwm_info,
4647 &sandybridge_cursor_srwm_info,
4648 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4649 return;
4650
4651 I915_WRITE(WM2_LP_ILK,
4652 WM2_LP_EN |
4653 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4654 (fbc_wm << WM1_LP_FBC_SHIFT) |
4655 (plane_wm << WM1_LP_SR_SHIFT) |
4656 cursor_wm);
4657
4658 /* WM3 */
d210246a
CW		 4659 if (!ironlake_compute_srwm(dev, 3, enabled,
4660 SNB_READ_WM3_LATENCY() * 500,
b79d4990
JB		 4661 &sandybridge_display_srwm_info,
4662 &sandybridge_cursor_srwm_info,
4663 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4664 return;
4665
4666 I915_WRITE(WM3_LP_ILK,
4667 WM3_LP_EN |
4668 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4669 (fbc_wm << WM1_LP_FBC_SHIFT) |
4670 (plane_wm << WM1_LP_SR_SHIFT) |
4671 cursor_wm);
4672}
4673
b840d907
JB		 4674static bool
4675sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4676 uint32_t sprite_width, int pixel_size,
4677 const struct intel_watermark_params *display,
4678 int display_latency_ns, int *sprite_wm)
4679{
4680 struct drm_crtc *crtc;
4681 int clock;
4682 int entries, tlb_miss;
4683
4684 crtc = intel_get_crtc_for_plane(dev, plane);
4685 if (crtc->fb == NULL || !crtc->enabled) {
4686 *sprite_wm = display->guard_size;
4687 return false;
4688 }
4689
4690 clock = crtc->mode.clock;
4691
4692 /* Use the small buffer method to calculate the sprite watermark */
4693 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4694 tlb_miss = display->fifo_size*display->cacheline_size -
4695 sprite_width * 8;
4696 if (tlb_miss > 0)
4697 entries += tlb_miss;
4698 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4699 *sprite_wm = entries + display->guard_size;
4700 if (*sprite_wm > (int)display->max_wm)
4701 *sprite_wm = display->max_wm;
4702
4703 return true;
4704}
4705
4706static bool
4707sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4708 uint32_t sprite_width, int pixel_size,
4709 const struct intel_watermark_params *display,
4710 int latency_ns, int *sprite_wm)
4711{
4712 struct drm_crtc *crtc;
4713 unsigned long line_time_us;
4714 int clock;
4715 int line_count, line_size;
4716 int small, large;
4717 int entries;
4718
4719 if (!latency_ns) {
4720 *sprite_wm = 0;
4721 return false;
4722 }
4723
4724 crtc = intel_get_crtc_for_plane(dev, plane);
4725 clock = crtc->mode.clock;
4726
4727 line_time_us = (sprite_width * 1000) / clock;
4728 line_count = (latency_ns / line_time_us + 1000) / 1000;
4729 line_size = sprite_width * pixel_size;
4730
4731 /* Use the minimum of the small and large buffer method for primary */
4732 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4733 large = line_count * line_size;
4734
4735 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4736 *sprite_wm = entries + display->guard_size;
4737
4738 return *sprite_wm > 0x3ff ? false : true;
4739}
4740
4741static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4742 uint32_t sprite_width, int pixel_size)
4743{
4744 struct drm_i915_private *dev_priv = dev->dev_private;
4745 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
47842649 4746 u32 val;
b840d907
JB		 4747 int sprite_wm, reg;
4748 int ret;
4749
4750 switch (pipe) {
4751 case 0:
4752 reg = WM0_PIPEA_ILK;
4753 break;
4754 case 1:
4755 reg = WM0_PIPEB_ILK;
4756 break;
4757 case 2:
4758 reg = WM0_PIPEC_IVB;
4759 break;
4760 default:
4761 return; /* bad pipe */
4762 }
4763
4764 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4765 &sandybridge_display_wm_info,
4766 latency, &sprite_wm);
4767 if (!ret) {
4768 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4769 pipe);
4770 return;
4771 }
4772
47842649
JB		 4773 val = I915_READ(reg);
4774 val &= ~WM0_PIPE_SPRITE_MASK;
4775 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
b840d907
JB		 4776 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4777
4778
4779 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4780 pixel_size,
4781 &sandybridge_display_srwm_info,
4782 SNB_READ_WM1_LATENCY() * 500,
4783 &sprite_wm);
4784 if (!ret) {
4785 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4786 pipe);
4787 return;
4788 }
4789 I915_WRITE(WM1S_LP_ILK, sprite_wm);
4790
4791 /* Only IVB has two more LP watermarks for sprite */
4792 if (!IS_IVYBRIDGE(dev))
4793 return;
4794
4795 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4796 pixel_size,
4797 &sandybridge_display_srwm_info,
4798 SNB_READ_WM2_LATENCY() * 500,
4799 &sprite_wm);
4800 if (!ret) {
4801 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4802 pipe);
4803 return;
4804 }
4805 I915_WRITE(WM2S_LP_IVB, sprite_wm);
4806
4807 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4808 pixel_size,
4809 &sandybridge_display_srwm_info,
4810 SNB_READ_WM3_LATENCY() * 500,
4811 &sprite_wm);
4812 if (!ret) {
4813 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4814 pipe);
4815 return;
4816 }
4817 I915_WRITE(WM3S_LP_IVB, sprite_wm);
4818}
4819
7662c8bd
SL		 4820/**
4821 * intel_update_watermarks - update FIFO watermark values based on current modes
4822 *
4823 * Calculate watermark values for the various WM regs based on current mode
4824 * and plane configuration.
4825 *
4826 * There are several cases to deal with here:
4827 * - normal (i.e. non-self-refresh)
4828 * - self-refresh (SR) mode
4829 * - lines are large relative to FIFO size (buffer can hold up to 2)
4830 * - lines are small relative to FIFO size (buffer can hold more than 2
4831 * lines), so need to account for TLB latency
4832 *
4833 * The normal calculation is:
4834 * watermark = dotclock * bytes per pixel * latency
4835 * where latency is platform & configuration dependent (we assume pessimal
4836 * values here).
4837 *
4838 * The SR calculation is:
4839 * watermark = (trunc(latency/line time)+1) * surface width *
4840 * bytes per pixel
4841 * where
4842 * line time = htotal / dotclock
fa143215 4843 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL		 4844 * and latency is assumed to be high, as above.
4845 *
4846 * The final value programmed to the register should always be rounded up,
4847 * and include an extra 2 entries to account for clock crossings.
4848 *
4849 * We don't use the sprite, so we can ignore that. And on Crestline we have
4850 * to set the non-SR watermarks to 8.
5eddb70b 4851 */
7662c8bd
SL		 4852static void intel_update_watermarks(struct drm_device *dev)
4853{
e70236a8 4854 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 4855
d210246a
CW		 4856 if (dev_priv->display.update_wm)
4857 dev_priv->display.update_wm(dev);
7662c8bd
SL		 4858}
4859
b840d907
JB		 4860void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4861 uint32_t sprite_width, int pixel_size)
4862{
4863 struct drm_i915_private *dev_priv = dev->dev_private;
4864
4865 if (dev_priv->display.update_sprite_wm)
4866 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4867 pixel_size);
4868}
4869
a7615030
CW		 4870static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4871{
72bbe58c
KP		 4872 if (i915_panel_use_ssc >= 0)
4873 return i915_panel_use_ssc != 0;
4874 return dev_priv->lvds_use_ssc
435793df 4875 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4876}
4877
5a354204
JB		 4878/**
4879 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4880 * @crtc: CRTC structure
3b5c78a3 4881 * @mode: requested mode
5a354204
JB		 4882 *
4883 * A pipe may be connected to one or more outputs. Based on the depth of the
4884 * attached framebuffer, choose a good color depth to use on the pipe.
4885 *
4886 * If possible, match the pipe depth to the fb depth. In some cases, this
4887 * isn't ideal, because the connected output supports a lesser or restricted
4888 * set of depths. Resolve that here:
4889 * LVDS typically supports only 6bpc, so clamp down in that case
4890 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4891 * Displays may support a restricted set as well, check EDID and clamp as
4892 * appropriate.
3b5c78a3 4893 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4894 *
4895 * RETURNS:
4896 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4897 * true if they don't match).
4898 */
4899static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3b5c78a3
AJ		 4900 unsigned int *pipe_bpp,
4901 struct drm_display_mode *mode)
5a354204
JB		 4902{
4903 struct drm_device *dev = crtc->dev;
4904 struct drm_i915_private *dev_priv = dev->dev_private;
4905 struct drm_encoder *encoder;
4906 struct drm_connector *connector;
4907 unsigned int display_bpc = UINT_MAX, bpc;
4908
4909 /* Walk the encoders & connectors on this crtc, get min bpc */
4910 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4911 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4912
4913 if (encoder->crtc != crtc)
4914 continue;
4915
4916 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4917 unsigned int lvds_bpc;
4918
4919 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4920 LVDS_A3_POWER_UP)
4921 lvds_bpc = 8;
4922 else
4923 lvds_bpc = 6;
4924
4925 if (lvds_bpc < display_bpc) {
82820490 4926 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4927 display_bpc = lvds_bpc;
4928 }
4929 continue;
4930 }
4931
4932 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4933 /* Use VBT settings if we have an eDP panel */
4934 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4935
4936 if (edp_bpc < display_bpc) {
82820490 4937 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5a354204
JB		 4938 display_bpc = edp_bpc;
4939 }
4940 continue;
4941 }
4942
4943 /* Not one of the known troublemakers, check the EDID */
4944 list_for_each_entry(connector, &dev->mode_config.connector_list,
4945 head) {
4946 if (connector->encoder != encoder)
4947 continue;
4948
62ac41a6
JB		 4949 /* Don't use an invalid EDID bpc value */
4950 if (connector->display_info.bpc &&
4951 connector->display_info.bpc < display_bpc) {
82820490 4952 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4953 display_bpc = connector->display_info.bpc;
4954 }
4955 }
4956
4957 /*
4958 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4959 * through, clamp it down. (Note: >12bpc will be caught below.)
4960 */
4961 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4962 if (display_bpc > 8 && display_bpc < 12) {
82820490 4963 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4964 display_bpc = 12;
4965 } else {
82820490 4966 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4967 display_bpc = 8;
4968 }
4969 }
4970 }
4971
3b5c78a3
AJ		 4972 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4973 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4974 display_bpc = 6;
4975 }
4976
5a354204
JB		 4977 /*
4978 * We could just drive the pipe at the highest bpc all the time and
4979 * enable dithering as needed, but that costs bandwidth. So choose
4980 * the minimum value that expresses the full color range of the fb but
4981 * also stays within the max display bpc discovered above.
4982 */
4983
4984 switch (crtc->fb->depth) {
4985 case 8:
4986 bpc = 8; /* since we go through a colormap */
4987 break;
4988 case 15:
4989 case 16:
4990 bpc = 6; /* min is 18bpp */
4991 break;
4992 case 24:
578393cd 4993 bpc = 8;
5a354204
JB		 4994 break;
4995 case 30:
578393cd 4996 bpc = 10;
5a354204
JB		 4997 break;
4998 case 48:
578393cd 4999 bpc = 12;
5a354204
JB		 5000 break;
5001 default:
5002 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
5003 bpc = min((unsigned int)8, display_bpc);
5004 break;
5005 }
5006
578393cd
KP		 5007 display_bpc = min(display_bpc, bpc);
5008
82820490
AJ		 5009 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
5010 bpc, display_bpc);
5a354204 5011
578393cd 5012 *pipe_bpp = display_bpc * 3;
5a354204
JB		 5013
5014 return display_bpc != bpc;
5015}
5016
c65d77d8
JB		 5017static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
5018{
5019 struct drm_device *dev = crtc->dev;
5020 struct drm_i915_private *dev_priv = dev->dev_private;
5021 int refclk;
5022
5023 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5024 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5025 refclk = dev_priv->lvds_ssc_freq * 1000;
5026 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5027 refclk / 1000);
5028 } else if (!IS_GEN2(dev)) {
5029 refclk = 96000;
5030 } else {
5031 refclk = 48000;
5032 }
5033
5034 return refclk;
5035}
5036
5037static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
5038 intel_clock_t *clock)
5039{
5040 /* SDVO TV has fixed PLL values depend on its clock range,
5041 this mirrors vbios setting. */
5042 if (adjusted_mode->clock >= 100000
5043 && adjusted_mode->clock < 140500) {
5044 clock->p1 = 2;
5045 clock->p2 = 10;
5046 clock->n = 3;
5047 clock->m1 = 16;
5048 clock->m2 = 8;
5049 } else if (adjusted_mode->clock >= 140500
5050 && adjusted_mode->clock <= 200000) {
5051 clock->p1 = 1;
5052 clock->p2 = 10;
5053 clock->n = 6;
5054 clock->m1 = 12;
5055 clock->m2 = 8;
5056 }
5057}
5058
a7516a05
JB		 5059static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
5060 intel_clock_t *clock,
5061 intel_clock_t *reduced_clock)
5062{
5063 struct drm_device *dev = crtc->dev;
5064 struct drm_i915_private *dev_priv = dev->dev_private;
5065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5066 int pipe = intel_crtc->pipe;
5067 u32 fp, fp2 = 0;
5068
5069 if (IS_PINEVIEW(dev)) {
5070 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
5071 if (reduced_clock)
5072 fp2 = (1 << reduced_clock->n) << 16 |
5073 reduced_clock->m1 << 8 | reduced_clock->m2;
5074 } else {
5075 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
5076 if (reduced_clock)
5077 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
5078 reduced_clock->m2;
5079 }
5080
5081 I915_WRITE(FP0(pipe), fp);
5082
5083 intel_crtc->lowfreq_avail = false;
5084 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
5085 reduced_clock && i915_powersave) {
5086 I915_WRITE(FP1(pipe), fp2);
5087 intel_crtc->lowfreq_avail = true;
5088 } else {
5089 I915_WRITE(FP1(pipe), fp);
5090 }
5091}
5092
f564048e
EA		 5093static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
5094 struct drm_display_mode *mode,
5095 struct drm_display_mode *adjusted_mode,
5096 int x, int y,
5097 struct drm_framebuffer *old_fb)
79e53945
JB		 5098{
5099 struct drm_device *dev = crtc->dev;
5100 struct drm_i915_private *dev_priv = dev->dev_private;
5101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5102 int pipe = intel_crtc->pipe;
80824003 5103 int plane = intel_crtc->plane;
c751ce4f 5104 int refclk, num_connectors = 0;
652c393a 5105 intel_clock_t clock, reduced_clock;
a7516a05 5106 u32 dpll, dspcntr, pipeconf;
652c393a 5107 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
a4fc5ed6 5108 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 5109 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 5110 struct intel_encoder *encoder;
d4906093 5111 const intel_limit_t *limit;
5c3b82e2 5112 int ret;
fae14981 5113 u32 temp;
aa9b500d 5114 u32 lvds_sync = 0;
79e53945 5115
5eddb70b
CW		 5116 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5117 if (encoder->base.crtc != crtc)
79e53945
JB		 5118 continue;
5119
5eddb70b 5120 switch (encoder->type) {
79e53945
JB		 5121 case INTEL_OUTPUT_LVDS:
5122 is_lvds = true;
5123 break;
5124 case INTEL_OUTPUT_SDVO:
7d57382e 5125 case INTEL_OUTPUT_HDMI:
79e53945 5126 is_sdvo = true;
5eddb70b 5127 if (encoder->needs_tv_clock)
e2f0ba97 5128 is_tv = true;
79e53945
JB		 5129 break;
5130 case INTEL_OUTPUT_DVO:
5131 is_dvo = true;
5132 break;
5133 case INTEL_OUTPUT_TVOUT:
5134 is_tv = true;
5135 break;
5136 case INTEL_OUTPUT_ANALOG:
5137 is_crt = true;
5138 break;
a4fc5ed6
KP		 5139 case INTEL_OUTPUT_DISPLAYPORT:
5140 is_dp = true;
5141 break;
79e53945 5142 }
43565a06 5143
c751ce4f 5144 num_connectors++;
79e53945
JB		 5145 }
5146
c65d77d8 5147 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 5148
d4906093
ML		 5149 /*
5150 * Returns a set of divisors for the desired target clock with the given
5151 * refclk, or FALSE. The returned values represent the clock equation:
5152 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5153 */
1b894b59 5154 limit = intel_limit(crtc, refclk);
cec2f356
SP		 5155 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5156 &clock);
79e53945
JB		 5157 if (!ok) {
5158 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 5159 return -EINVAL;
79e53945
JB		 5160 }
5161
cda4b7d3 5162 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 5163 intel_crtc_update_cursor(crtc, true);
cda4b7d3 5164
ddc9003c 5165 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5166 /*
5167 * Ensure we match the reduced clock's P to the target clock.
5168 * If the clocks don't match, we can't switch the display clock
5169 * by using the FP0/FP1. In such case we will disable the LVDS
5170 * downclock feature.
5171 */
ddc9003c 5172 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 5173 dev_priv->lvds_downclock,
5174 refclk,
cec2f356 5175 &clock,
5eddb70b 5176 &reduced_clock);
652c393a 5177 }
c65d77d8
JB		 5178
5179 if (is_sdvo && is_tv)
5180 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 5181
a7516a05
JB		 5182 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
5183 &reduced_clock : NULL);
79e53945 5184
929c77fb 5185 dpll = DPLL_VGA_MODE_DIS;
2c07245f 5186
a6c45cf0 5187 if (!IS_GEN2(dev)) {
79e53945
JB		 5188 if (is_lvds)
5189 dpll |= DPLLB_MODE_LVDS;
5190 else
5191 dpll |= DPLLB_MODE_DAC_SERIAL;
5192 if (is_sdvo) {
6c9547ff
CW		 5193 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5194 if (pixel_multiplier > 1) {
5195 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5196 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
6c9547ff 5197 }
79e53945 5198 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5199 }
929c77fb 5200 if (is_dp)
a4fc5ed6 5201 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945
JB		 5202
5203 /* compute bitmask from p1 value */
f2b115e6
AJ		 5204 if (IS_PINEVIEW(dev))
5205 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
2c07245f 5206 else {
2177832f 5207 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
652c393a
JB		 5208 if (IS_G4X(dev) && has_reduced_clock)
5209 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2c07245f 5210 }
79e53945
JB		 5211 switch (clock.p2) {
5212 case 5:
5213 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5214 break;
5215 case 7:
5216 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5217 break;
5218 case 10:
5219 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5220 break;
5221 case 14:
5222 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5223 break;
5224 }
929c77fb 5225 if (INTEL_INFO(dev)->gen >= 4)
79e53945
JB		 5226 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5227 } else {
5228 if (is_lvds) {
5229 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5230 } else {
5231 if (clock.p1 == 2)
5232 dpll |= PLL_P1_DIVIDE_BY_TWO;
5233 else
5234 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5235 if (clock.p2 == 4)
5236 dpll |= PLL_P2_DIVIDE_BY_4;
5237 }
5238 }
5239
43565a06
KH		 5240 if (is_sdvo && is_tv)
5241 dpll |= PLL_REF_INPUT_TVCLKINBC;
5242 else if (is_tv)
79e53945 5243 /* XXX: just matching BIOS for now */
43565a06 5244 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5245 dpll |= 3;
a7615030 5246 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5247 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5248 else
5249 dpll |= PLL_REF_INPUT_DREFCLK;
5250
5251 /* setup pipeconf */
5eddb70b 5252 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5253
5254 /* Set up the display plane register */
5255 dspcntr = DISPPLANE_GAMMA_ENABLE;
5256
929c77fb
EA		 5257 if (pipe == 0)
5258 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5259 else
5260 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 5261
a6c45cf0 5262 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 5263 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5264 * core speed.
5265 *
5266 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5267 * pipe == 0 check?
5268 */
e70236a8
JB		 5269 if (mode->clock >
5270 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 5271 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 5272 else
5eddb70b 5273 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 5274 }
5275
3b5c78a3
AJ		 5276 /* default to 8bpc */
5277 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5278 if (is_dp) {
5279 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5280 pipeconf |= PIPECONF_BPP_6 |
5281 PIPECONF_DITHER_EN |
5282 PIPECONF_DITHER_TYPE_SP;
5283 }
5284 }
5285
929c77fb 5286 dpll |= DPLL_VCO_ENABLE;
8d86dc6a 5287
28c97730 5288 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 5289 drm_mode_debug_printmodeline(mode);
5290
fae14981 5291 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 5292
fae14981 5293 POSTING_READ(DPLL(pipe));
c713bb08 5294 udelay(150);
8db9d77b 5295
79e53945
JB		 5296 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5297 * This is an exception to the general rule that mode_set doesn't turn
5298 * things on.
5299 */
5300 if (is_lvds) {
fae14981 5301 temp = I915_READ(LVDS);
5eddb70b 5302 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3 5303 if (pipe == 1) {
929c77fb 5304 temp |= LVDS_PIPEB_SELECT;
b3b095b3 5305 } else {
929c77fb 5306 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 5307 }
a3e17eb8 5308 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5309 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5310 /* Set the B0-B3 data pairs corresponding to whether we're going to
5311 * set the DPLLs for dual-channel mode or not.
5312 */
5313 if (clock.p2 == 7)
5eddb70b 5314 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5315 else
5eddb70b 5316 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5317
5318 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5319 * appropriately here, but we need to look more thoroughly into how
5320 * panels behave in the two modes.
5321 */
929c77fb
EA		 5322 /* set the dithering flag on LVDS as needed */
5323 if (INTEL_INFO(dev)->gen >= 4) {
434ed097 5324 if (dev_priv->lvds_dither)
5eddb70b 5325 temp |= LVDS_ENABLE_DITHER;
434ed097 5326 else
5eddb70b 5327 temp &= ~LVDS_ENABLE_DITHER;
898822ce 5328 }
aa9b500d
BF		 5329 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5330 lvds_sync |= LVDS_HSYNC_POLARITY;
5331 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5332 lvds_sync |= LVDS_VSYNC_POLARITY;
5333 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5334 != lvds_sync) {
5335 char flags[2] = "-+";
5336 DRM_INFO("Changing LVDS panel from "
5337 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5338 flags[!(temp & LVDS_HSYNC_POLARITY)],
5339 flags[!(temp & LVDS_VSYNC_POLARITY)],
5340 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5341 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5342 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5343 temp |= lvds_sync;
5344 }
fae14981 5345 I915_WRITE(LVDS, temp);
79e53945 5346 }
434ed097 5347
929c77fb 5348 if (is_dp) {
a4fc5ed6 5349 intel_dp_set_m_n(crtc, mode, adjusted_mode);
434ed097
JB		 5350 }
5351
fae14981 5352 I915_WRITE(DPLL(pipe), dpll);
5eddb70b 5353
c713bb08 5354 /* Wait for the clocks to stabilize. */
fae14981 5355 POSTING_READ(DPLL(pipe));
c713bb08 5356 udelay(150);
32f9d658 5357
c713bb08
EA		 5358 if (INTEL_INFO(dev)->gen >= 4) {
5359 temp = 0;
5360 if (is_sdvo) {
5361 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5362 if (temp > 1)
5363 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5364 else
5365 temp = 0;
32f9d658 5366 }
c713bb08
EA		 5367 I915_WRITE(DPLL_MD(pipe), temp);
5368 } else {
5369 /* The pixel multiplier can only be updated once the
5370 * DPLL is enabled and the clocks are stable.
5371 *
5372 * So write it again.
5373 */
fae14981 5374 I915_WRITE(DPLL(pipe), dpll);
79e53945 5375 }
79e53945 5376
a7516a05
JB		 5377 if (HAS_PIPE_CXSR(dev)) {
5378 if (intel_crtc->lowfreq_avail) {
28c97730 5379 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 5380 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 5381 } else {
28c97730 5382 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5383 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5384 }
5385 }
5386
617cf884 5387 pipeconf &= ~PIPECONF_INTERLACE_MASK;
734b4157
KH		 5388 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5389 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5390 /* the chip adds 2 halflines automatically */
734b4157 5391 adjusted_mode->crtc_vtotal -= 1;
734b4157 5392 adjusted_mode->crtc_vblank_end -= 1;
734b4157 5393 } else
617cf884 5394 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 5395
5eddb70b
CW		 5396 I915_WRITE(HTOTAL(pipe),
5397 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5398 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5399 I915_WRITE(HBLANK(pipe),
5400 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5401 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5402 I915_WRITE(HSYNC(pipe),
5403 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5404 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5405
5406 I915_WRITE(VTOTAL(pipe),
5407 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5408 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5409 I915_WRITE(VBLANK(pipe),
5410 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5411 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5412 I915_WRITE(VSYNC(pipe),
5413 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5414 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 5415
5416 /* pipesrc and dspsize control the size that is scaled from,
5417 * which should always be the user's requested size.
79e53945 5418 */
929c77fb
EA		 5419 I915_WRITE(DSPSIZE(plane),
5420 ((mode->vdisplay - 1) << 16) |
5421 (mode->hdisplay - 1));
5422 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 5423 I915_WRITE(PIPESRC(pipe),
5424 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5425
f564048e
EA		 5426 I915_WRITE(PIPECONF(pipe), pipeconf);
5427 POSTING_READ(PIPECONF(pipe));
929c77fb 5428 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 5429
5430 intel_wait_for_vblank(dev, pipe);
5431
f564048e
EA		 5432 I915_WRITE(DSPCNTR(plane), dspcntr);
5433 POSTING_READ(DSPCNTR(plane));
284d9529 5434 intel_enable_plane(dev_priv, plane, pipe);
f564048e
EA		 5435
5436 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5437
5438 intel_update_watermarks(dev);
5439
f564048e
EA		 5440 return ret;
5441}
5442
9fb526db
KP		 5443/*
5444 * Initialize reference clocks when the driver loads
5445 */
5446void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5447{
5448 struct drm_i915_private *dev_priv = dev->dev_private;
5449 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5450 struct intel_encoder *encoder;
13d83a67
JB		 5451 u32 temp;
5452 bool has_lvds = false;
199e5d79
KP		 5453 bool has_cpu_edp = false;
5454 bool has_pch_edp = false;
5455 bool has_panel = false;
99eb6a01
KP		 5456 bool has_ck505 = false;
5457 bool can_ssc = false;
13d83a67
JB		 5458
5459 /* We need to take the global config into account */
199e5d79
KP		 5460 list_for_each_entry(encoder, &mode_config->encoder_list,
5461 base.head) {
5462 switch (encoder->type) {
5463 case INTEL_OUTPUT_LVDS:
5464 has_panel = true;
5465 has_lvds = true;
5466 break;
5467 case INTEL_OUTPUT_EDP:
5468 has_panel = true;
5469 if (intel_encoder_is_pch_edp(&encoder->base))
5470 has_pch_edp = true;
5471 else
5472 has_cpu_edp = true;
5473 break;
13d83a67
JB		 5474 }
5475 }
5476
99eb6a01
KP		 5477 if (HAS_PCH_IBX(dev)) {
5478 has_ck505 = dev_priv->display_clock_mode;
5479 can_ssc = has_ck505;
5480 } else {
5481 has_ck505 = false;
5482 can_ssc = true;
5483 }
5484
5485 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5486 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5487 has_ck505);
13d83a67
JB		 5488
5489 /* Ironlake: try to setup display ref clock before DPLL
5490 * enabling. This is only under driver's control after
5491 * PCH B stepping, previous chipset stepping should be
5492 * ignoring this setting.
5493 */
5494 temp = I915_READ(PCH_DREF_CONTROL);
5495 /* Always enable nonspread source */
5496 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5497
99eb6a01
KP		 5498 if (has_ck505)
5499 temp |= DREF_NONSPREAD_CK505_ENABLE;
5500 else
5501 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5502
199e5d79
KP		 5503 if (has_panel) {
5504 temp &= ~DREF_SSC_SOURCE_MASK;
5505 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5506
199e5d79 5507 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5508 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5509 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 5510 temp |= DREF_SSC1_ENABLE;
13d83a67 5511 }
199e5d79
KP		 5512
5513 /* Get SSC going before enabling the outputs */
5514 I915_WRITE(PCH_DREF_CONTROL, temp);
5515 POSTING_READ(PCH_DREF_CONTROL);
5516 udelay(200);
5517
13d83a67
JB		 5518 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5519
5520 /* Enable CPU source on CPU attached eDP */
199e5d79 5521 if (has_cpu_edp) {
99eb6a01 5522 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5523 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 5524 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5525 }
13d83a67
JB		 5526 else
5527 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 5528 } else
5529 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5530
5531 I915_WRITE(PCH_DREF_CONTROL, temp);
5532 POSTING_READ(PCH_DREF_CONTROL);
5533 udelay(200);
5534 } else {
5535 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5536
5537 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5538
5539 /* Turn off CPU output */
5540 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5541
5542 I915_WRITE(PCH_DREF_CONTROL, temp);
5543 POSTING_READ(PCH_DREF_CONTROL);
5544 udelay(200);
5545
5546 /* Turn off the SSC source */
5547 temp &= ~DREF_SSC_SOURCE_MASK;
5548 temp |= DREF_SSC_SOURCE_DISABLE;
5549
5550 /* Turn off SSC1 */
5551 temp &= ~ DREF_SSC1_ENABLE;
5552
13d83a67
JB		 5553 I915_WRITE(PCH_DREF_CONTROL, temp);
5554 POSTING_READ(PCH_DREF_CONTROL);
5555 udelay(200);
5556 }
5557}
5558
d9d444cb
JB		 5559static int ironlake_get_refclk(struct drm_crtc *crtc)
5560{
5561 struct drm_device *dev = crtc->dev;
5562 struct drm_i915_private *dev_priv = dev->dev_private;
5563 struct intel_encoder *encoder;
5564 struct drm_mode_config *mode_config = &dev->mode_config;
5565 struct intel_encoder *edp_encoder = NULL;
5566 int num_connectors = 0;
5567 bool is_lvds = false;
5568
5569 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5570 if (encoder->base.crtc != crtc)
5571 continue;
5572
5573 switch (encoder->type) {
5574 case INTEL_OUTPUT_LVDS:
5575 is_lvds = true;
5576 break;
5577 case INTEL_OUTPUT_EDP:
5578 edp_encoder = encoder;
5579 break;
5580 }
5581 num_connectors++;
5582 }
5583
5584 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5585 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5586 dev_priv->lvds_ssc_freq);
5587 return dev_priv->lvds_ssc_freq * 1000;
5588 }
5589
5590 return 120000;
5591}
5592
f564048e
EA		 5593static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5594 struct drm_display_mode *mode,
5595 struct drm_display_mode *adjusted_mode,
5596 int x, int y,
5597 struct drm_framebuffer *old_fb)
79e53945
JB		 5598{
5599 struct drm_device *dev = crtc->dev;
5600 struct drm_i915_private *dev_priv = dev->dev_private;
5601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5602 int pipe = intel_crtc->pipe;
80824003 5603 int plane = intel_crtc->plane;
c751ce4f 5604 int refclk, num_connectors = 0;
652c393a 5605 intel_clock_t clock, reduced_clock;
5eddb70b 5606 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 5607 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 5608 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
8e647a27 5609 struct intel_encoder *has_edp_encoder = NULL;
79e53945 5610 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 5611 struct intel_encoder *encoder;
d4906093 5612 const intel_limit_t *limit;
5c3b82e2 5613 int ret;
2c07245f 5614 struct fdi_m_n m_n = {0};
fae14981 5615 u32 temp;
aa9b500d 5616 u32 lvds_sync = 0;
5a354204
JB		 5617 int target_clock, pixel_multiplier, lane, link_bw, factor;
5618 unsigned int pipe_bpp;
5619 bool dither;
79e53945 5620
5eddb70b
CW		 5621 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5622 if (encoder->base.crtc != crtc)
79e53945
JB		 5623 continue;
5624
5eddb70b 5625 switch (encoder->type) {
79e53945
JB		 5626 case INTEL_OUTPUT_LVDS:
5627 is_lvds = true;
5628 break;
5629 case INTEL_OUTPUT_SDVO:
7d57382e 5630 case INTEL_OUTPUT_HDMI:
79e53945 5631 is_sdvo = true;
5eddb70b 5632 if (encoder->needs_tv_clock)
e2f0ba97 5633 is_tv = true;
79e53945 5634 break;
79e53945
JB		 5635 case INTEL_OUTPUT_TVOUT:
5636 is_tv = true;
5637 break;
5638 case INTEL_OUTPUT_ANALOG:
5639 is_crt = true;
5640 break;
a4fc5ed6
KP		 5641 case INTEL_OUTPUT_DISPLAYPORT:
5642 is_dp = true;
5643 break;
32f9d658 5644 case INTEL_OUTPUT_EDP:
5eddb70b 5645 has_edp_encoder = encoder;
32f9d658 5646 break;
79e53945 5647 }
43565a06 5648
c751ce4f 5649 num_connectors++;
79e53945
JB		 5650 }
5651
d9d444cb 5652 refclk = ironlake_get_refclk(crtc);
79e53945 5653
d4906093
ML		 5654 /*
5655 * Returns a set of divisors for the desired target clock with the given
5656 * refclk, or FALSE. The returned values represent the clock equation:
5657 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5658 */
1b894b59 5659 limit = intel_limit(crtc, refclk);
cec2f356
SP		 5660 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5661 &clock);
79e53945
JB		 5662 if (!ok) {
5663 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 5664 return -EINVAL;
79e53945
JB		 5665 }
5666
cda4b7d3 5667 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 5668 intel_crtc_update_cursor(crtc, true);
cda4b7d3 5669
ddc9003c 5670 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5671 /*
5672 * Ensure we match the reduced clock's P to the target clock.
5673 * If the clocks don't match, we can't switch the display clock
5674 * by using the FP0/FP1. In such case we will disable the LVDS
5675 * downclock feature.
5676 */
ddc9003c 5677 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 5678 dev_priv->lvds_downclock,
5679 refclk,
cec2f356 5680 &clock,
5eddb70b 5681 &reduced_clock);
652c393a 5682 }
7026d4ac
ZW		 5683 /* SDVO TV has fixed PLL values depend on its clock range,
5684 this mirrors vbios setting. */
5685 if (is_sdvo && is_tv) {
5686 if (adjusted_mode->clock >= 100000
5eddb70b 5687 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 5688 clock.p1 = 2;
5689 clock.p2 = 10;
5690 clock.n = 3;
5691 clock.m1 = 16;
5692 clock.m2 = 8;
5693 } else if (adjusted_mode->clock >= 140500
5eddb70b 5694 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 5695 clock.p1 = 1;
5696 clock.p2 = 10;
5697 clock.n = 6;
5698 clock.m1 = 12;
5699 clock.m2 = 8;
5700 }
5701 }
5702
2c07245f 5703 /* FDI link */
8febb297
EA		 5704 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5705 lane = 0;
5706 /* CPU eDP doesn't require FDI link, so just set DP M/N
5707 according to current link config */
5708 if (has_edp_encoder &&
5709 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5710 target_clock = mode->clock;
5711 intel_edp_link_config(has_edp_encoder,
5712 &lane, &link_bw);
5713 } else {
5714 /* [e]DP over FDI requires target mode clock
5715 instead of link clock */
5716 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5eb08b69 5717 target_clock = mode->clock;
8febb297
EA		 5718 else
5719 target_clock = adjusted_mode->clock;
5720
5721 /* FDI is a binary signal running at ~2.7GHz, encoding
5722 * each output octet as 10 bits. The actual frequency
5723 * is stored as a divider into a 100MHz clock, and the
5724 * mode pixel clock is stored in units of 1KHz.
5725 * Hence the bw of each lane in terms of the mode signal
5726 * is:
5727 */
5728 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5729 }
58a27471 5730
8febb297
EA		 5731 /* determine panel color depth */
5732 temp = I915_READ(PIPECONF(pipe));
5733 temp &= ~PIPE_BPC_MASK;
3b5c78a3 5734 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5a354204
JB		 5735 switch (pipe_bpp) {
5736 case 18:
5737 temp |= PIPE_6BPC;
8febb297 5738 break;
5a354204
JB		 5739 case 24:
5740 temp |= PIPE_8BPC;
8febb297 5741 break;
5a354204
JB		 5742 case 30:
5743 temp |= PIPE_10BPC;
8febb297 5744 break;
5a354204
JB		 5745 case 36:
5746 temp |= PIPE_12BPC;
8febb297
EA		 5747 break;
5748 default:
62ac41a6
JB		 5749 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5750 pipe_bpp);
5a354204
JB		 5751 temp |= PIPE_8BPC;
5752 pipe_bpp = 24;
5753 break;
8febb297 5754 }
77ffb597 5755
5a354204
JB		 5756 intel_crtc->bpp = pipe_bpp;
5757 I915_WRITE(PIPECONF(pipe), temp);
5758
8febb297
EA		 5759 if (!lane) {
5760 /*
5761 * Account for spread spectrum to avoid
5762 * oversubscribing the link. Max center spread
5763 * is 2.5%; use 5% for safety's sake.
5764 */
5a354204 5765 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 5766 lane = bps / (link_bw * 8) + 1;
5eb08b69 5767 }
2c07245f 5768
8febb297
EA		 5769 intel_crtc->fdi_lanes = lane;
5770
5771 if (pixel_multiplier > 1)
5772 link_bw *= pixel_multiplier;
5a354204
JB		 5773 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5774 &m_n);
8febb297 5775
a07d6787
EA		 5776 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5777 if (has_reduced_clock)
5778 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5779 reduced_clock.m2;
79e53945 5780
c1858123 5781 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5782 factor = 21;
5783 if (is_lvds) {
5784 if ((intel_panel_use_ssc(dev_priv) &&
5785 dev_priv->lvds_ssc_freq == 100) ||
5786 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5787 factor = 25;
5788 } else if (is_sdvo && is_tv)
5789 factor = 20;
c1858123 5790
cb0e0931 5791 if (clock.m < factor * clock.n)
8febb297 5792 fp |= FP_CB_TUNE;
2c07245f 5793
5eddb70b 5794 dpll = 0;
2c07245f 5795
a07d6787
EA		 5796 if (is_lvds)
5797 dpll |= DPLLB_MODE_LVDS;
5798 else
5799 dpll |= DPLLB_MODE_DAC_SERIAL;
5800 if (is_sdvo) {
5801 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5802 if (pixel_multiplier > 1) {
5803 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5804 }
a07d6787
EA		 5805 dpll |= DPLL_DVO_HIGH_SPEED;
5806 }
5807 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5808 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5809
a07d6787
EA		 5810 /* compute bitmask from p1 value */
5811 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5812 /* also FPA1 */
5813 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5814
5815 switch (clock.p2) {
5816 case 5:
5817 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5818 break;
5819 case 7:
5820 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5821 break;
5822 case 10:
5823 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5824 break;
5825 case 14:
5826 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5827 break;
79e53945
JB		 5828 }
5829
43565a06
KH		 5830 if (is_sdvo && is_tv)
5831 dpll |= PLL_REF_INPUT_TVCLKINBC;
5832 else if (is_tv)
79e53945 5833 /* XXX: just matching BIOS for now */
43565a06 5834 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5835 dpll |= 3;
a7615030 5836 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5837 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5838 else
5839 dpll |= PLL_REF_INPUT_DREFCLK;
5840
5841 /* setup pipeconf */
5eddb70b 5842 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5843
5844 /* Set up the display plane register */
5845 dspcntr = DISPPLANE_GAMMA_ENABLE;
5846
f7cb34d4 5847 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5848 drm_mode_debug_printmodeline(mode);
5849
5c5313c8 5850 /* PCH eDP needs FDI, but CPU eDP does not */
4b645f14
JB		 5851 if (!intel_crtc->no_pll) {
5852 if (!has_edp_encoder ||
5853 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5854 I915_WRITE(PCH_FP0(pipe), fp);
5855 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5856
5857 POSTING_READ(PCH_DPLL(pipe));
5858 udelay(150);
5859 }
5860 } else {
5861 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5862 fp == I915_READ(PCH_FP0(0))) {
5863 intel_crtc->use_pll_a = true;
5864 DRM_DEBUG_KMS("using pipe a dpll\n");
5865 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5866 fp == I915_READ(PCH_FP0(1))) {
5867 intel_crtc->use_pll_a = false;
5868 DRM_DEBUG_KMS("using pipe b dpll\n");
5869 } else {
5870 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5871 return -EINVAL;
5872 }
79e53945
JB		 5873 }
5874
5875 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5876 * This is an exception to the general rule that mode_set doesn't turn
5877 * things on.
5878 */
5879 if (is_lvds) {
fae14981 5880 temp = I915_READ(PCH_LVDS);
5eddb70b 5881 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 5882 if (HAS_PCH_CPT(dev)) {
5883 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 5884 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 5885 } else {
5886 if (pipe == 1)
5887 temp |= LVDS_PIPEB_SELECT;
5888 else
5889 temp &= ~LVDS_PIPEB_SELECT;
5890 }
4b645f14 5891
a3e17eb8 5892 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5893 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5894 /* Set the B0-B3 data pairs corresponding to whether we're going to
5895 * set the DPLLs for dual-channel mode or not.
5896 */
5897 if (clock.p2 == 7)
5eddb70b 5898 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5899 else
5eddb70b 5900 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5901
5902 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5903 * appropriately here, but we need to look more thoroughly into how
5904 * panels behave in the two modes.
5905 */
aa9b500d
BF		 5906 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5907 lvds_sync |= LVDS_HSYNC_POLARITY;
5908 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5909 lvds_sync |= LVDS_VSYNC_POLARITY;
5910 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5911 != lvds_sync) {
5912 char flags[2] = "-+";
5913 DRM_INFO("Changing LVDS panel from "
5914 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5915 flags[!(temp & LVDS_HSYNC_POLARITY)],
5916 flags[!(temp & LVDS_VSYNC_POLARITY)],
5917 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5918 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5919 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5920 temp |= lvds_sync;
5921 }
fae14981 5922 I915_WRITE(PCH_LVDS, temp);
79e53945 5923 }
434ed097 5924
8febb297
EA		 5925 pipeconf &= ~PIPECONF_DITHER_EN;
5926 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 5927 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 5928 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 5929 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 5930 }
5c5313c8 5931 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
a4fc5ed6 5932 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5933 } else {
8db9d77b 5934 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5935 I915_WRITE(TRANSDATA_M1(pipe), 0);
5936 I915_WRITE(TRANSDATA_N1(pipe), 0);
5937 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5938 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5939 }
79e53945 5940
4b645f14
JB		 5941 if (!intel_crtc->no_pll &&
5942 (!has_edp_encoder ||
5943 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
fae14981 5944 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 5945
32f9d658 5946 /* Wait for the clocks to stabilize. */
fae14981 5947 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 5948 udelay(150);
5949
8febb297
EA		 5950 /* The pixel multiplier can only be updated once the
5951 * DPLL is enabled and the clocks are stable.
5952 *
5953 * So write it again.
5954 */
fae14981 5955 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 5956 }
79e53945 5957
5eddb70b 5958 intel_crtc->lowfreq_avail = false;
4b645f14
JB		 5959 if (!intel_crtc->no_pll) {
5960 if (is_lvds && has_reduced_clock && i915_powersave) {
5961 I915_WRITE(PCH_FP1(pipe), fp2);
5962 intel_crtc->lowfreq_avail = true;
5963 if (HAS_PIPE_CXSR(dev)) {
5964 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5965 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5966 }
5967 } else {
5968 I915_WRITE(PCH_FP1(pipe), fp);
5969 if (HAS_PIPE_CXSR(dev)) {
5970 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5971 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5972 }
652c393a
JB		 5973 }
5974 }
5975
617cf884 5976 pipeconf &= ~PIPECONF_INTERLACE_MASK;
734b4157 5977 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5def474e 5978 pipeconf |= PIPECONF_INTERLACED_ILK;
734b4157 5979 /* the chip adds 2 halflines automatically */
734b4157 5980 adjusted_mode->crtc_vtotal -= 1;
734b4157 5981 adjusted_mode->crtc_vblank_end -= 1;
734b4157 5982 } else
617cf884 5983 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 5984
5eddb70b
CW		 5985 I915_WRITE(HTOTAL(pipe),
5986 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5987 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5988 I915_WRITE(HBLANK(pipe),
5989 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5990 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5991 I915_WRITE(HSYNC(pipe),
5992 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5993 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5994
5995 I915_WRITE(VTOTAL(pipe),
5996 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5997 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5998 I915_WRITE(VBLANK(pipe),
5999 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 6000 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 6001 I915_WRITE(VSYNC(pipe),
6002 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 6003 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 6004
8febb297
EA		 6005 /* pipesrc controls the size that is scaled from, which should
6006 * always be the user's requested size.
79e53945 6007 */
5eddb70b
CW		 6008 I915_WRITE(PIPESRC(pipe),
6009 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 6010
8febb297
EA		 6011 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
6012 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
6013 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
6014 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 6015
8febb297
EA		 6016 if (has_edp_encoder &&
6017 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
6018 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f
ZW		 6019 }
6020
5eddb70b
CW		 6021 I915_WRITE(PIPECONF(pipe), pipeconf);
6022 POSTING_READ(PIPECONF(pipe));
79e53945 6023
9d0498a2 6024 intel_wait_for_vblank(dev, pipe);
79e53945 6025
5eddb70b 6026 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 6027 POSTING_READ(DSPCNTR(plane));
79e53945 6028
5c3b82e2 6029 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 6030
6031 intel_update_watermarks(dev);
6032
1f803ee5 6033 return ret;
79e53945
JB		 6034}
6035
f564048e
EA		 6036static int intel_crtc_mode_set(struct drm_crtc *crtc,
6037 struct drm_display_mode *mode,
6038 struct drm_display_mode *adjusted_mode,
6039 int x, int y,
6040 struct drm_framebuffer *old_fb)
6041{
6042 struct drm_device *dev = crtc->dev;
6043 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 6044 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6045 int pipe = intel_crtc->pipe;
f564048e
EA		 6046 int ret;
6047
0b701d27 6048 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6049
f564048e
EA		 6050 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
6051 x, y, old_fb);
79e53945 6052 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6053
d8e70a25
JB		 6054 if (ret)
6055 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
6056 else
6057 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
120eced9 6058
1f803ee5 6059 return ret;
79e53945
JB		 6060}
6061
3a9627f4
WF		 6062static bool intel_eld_uptodate(struct drm_connector *connector,
6063 int reg_eldv, uint32_t bits_eldv,
6064 int reg_elda, uint32_t bits_elda,
6065 int reg_edid)
6066{
6067 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6068 uint8_t *eld = connector->eld;
6069 uint32_t i;
6070
6071 i = I915_READ(reg_eldv);
6072 i &= bits_eldv;
6073
6074 if (!eld[0])
6075 return !i;
6076
6077 if (!i)
6078 return false;
6079
6080 i = I915_READ(reg_elda);
6081 i &= ~bits_elda;
6082 I915_WRITE(reg_elda, i);
6083
6084 for (i = 0; i < eld[2]; i++)
6085 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6086 return false;
6087
6088 return true;
6089}
6090
e0dac65e
WF		 6091static void g4x_write_eld(struct drm_connector *connector,
6092 struct drm_crtc *crtc)
6093{
6094 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6095 uint8_t *eld = connector->eld;
6096 uint32_t eldv;
6097 uint32_t len;
6098 uint32_t i;
6099
6100 i = I915_READ(G4X_AUD_VID_DID);
6101
6102 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6103 eldv = G4X_ELDV_DEVCL_DEVBLC;
6104 else
6105 eldv = G4X_ELDV_DEVCTG;
6106
3a9627f4
WF		 6107 if (intel_eld_uptodate(connector,
6108 G4X_AUD_CNTL_ST, eldv,
6109 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6110 G4X_HDMIW_HDMIEDID))
6111 return;
6112
e0dac65e
WF		 6113 i = I915_READ(G4X_AUD_CNTL_ST);
6114 i &= ~(eldv | G4X_ELD_ADDR);
6115 len = (i >> 9) & 0x1f; /* ELD buffer size */
6116 I915_WRITE(G4X_AUD_CNTL_ST, i);
6117
6118 if (!eld[0])
6119 return;
6120
6121 len = min_t(uint8_t, eld[2], len);
6122 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6123 for (i = 0; i < len; i++)
6124 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6125
6126 i = I915_READ(G4X_AUD_CNTL_ST);
6127 i |= eldv;
6128 I915_WRITE(G4X_AUD_CNTL_ST, i);
6129}
6130
6131static void ironlake_write_eld(struct drm_connector *connector,
6132 struct drm_crtc *crtc)
6133{
6134 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6135 uint8_t *eld = connector->eld;
6136 uint32_t eldv;
6137 uint32_t i;
6138 int len;
6139 int hdmiw_hdmiedid;
b6daa025 6140 int aud_config;
e0dac65e
WF		 6141 int aud_cntl_st;
6142 int aud_cntrl_st2;
6143
b3f33cbf 6144 if (HAS_PCH_IBX(connector->dev)) {
1202b4c6 6145 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
b6daa025 6146 aud_config = IBX_AUD_CONFIG_A;
1202b4c6
WF		 6147 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6148 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6149 } else {
1202b4c6 6150 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
b6daa025 6151 aud_config = CPT_AUD_CONFIG_A;
1202b4c6
WF		 6152 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6153 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6154 }
6155
6156 i = to_intel_crtc(crtc)->pipe;
6157 hdmiw_hdmiedid += i * 0x100;
6158 aud_cntl_st += i * 0x100;
b6daa025 6159 aud_config += i * 0x100;
e0dac65e
WF		 6160
6161 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6162
6163 i = I915_READ(aud_cntl_st);
6164 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
6165 if (!i) {
6166 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6167 /* operate blindly on all ports */
1202b4c6
WF		 6168 eldv = IBX_ELD_VALIDB;
6169 eldv |= IBX_ELD_VALIDB << 4;
6170 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6171 } else {
6172 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6173 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6174 }
6175
3a9627f4
WF		 6176 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6177 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6178 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6179 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6180 } else
6181 I915_WRITE(aud_config, 0);
e0dac65e 6182
3a9627f4
WF		 6183 if (intel_eld_uptodate(connector,
6184 aud_cntrl_st2, eldv,
6185 aud_cntl_st, IBX_ELD_ADDRESS,
6186 hdmiw_hdmiedid))
6187 return;
6188
e0dac65e
WF		 6189 i = I915_READ(aud_cntrl_st2);
6190 i &= ~eldv;
6191 I915_WRITE(aud_cntrl_st2, i);
6192
6193 if (!eld[0])
6194 return;
6195
e0dac65e 6196 i = I915_READ(aud_cntl_st);
1202b4c6 6197 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6198 I915_WRITE(aud_cntl_st, i);
6199
6200 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6201 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6202 for (i = 0; i < len; i++)
6203 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6204
6205 i = I915_READ(aud_cntrl_st2);
6206 i |= eldv;
6207 I915_WRITE(aud_cntrl_st2, i);
6208}
6209
6210void intel_write_eld(struct drm_encoder *encoder,
6211 struct drm_display_mode *mode)
6212{
6213 struct drm_crtc *crtc = encoder->crtc;
6214 struct drm_connector *connector;
6215 struct drm_device *dev = encoder->dev;
6216 struct drm_i915_private *dev_priv = dev->dev_private;
6217
6218 connector = drm_select_eld(encoder, mode);
6219 if (!connector)
6220 return;
6221
6222 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6223 connector->base.id,
6224 drm_get_connector_name(connector),
6225 connector->encoder->base.id,
6226 drm_get_encoder_name(connector->encoder));
6227
6228 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6229
6230 if (dev_priv->display.write_eld)
6231 dev_priv->display.write_eld(connector, crtc);
6232}
6233
79e53945
JB		 6234/** Loads the palette/gamma unit for the CRTC with the prepared values */
6235void intel_crtc_load_lut(struct drm_crtc *crtc)
6236{
6237 struct drm_device *dev = crtc->dev;
6238 struct drm_i915_private *dev_priv = dev->dev_private;
6239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6240 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6241 int i;
6242
6243 /* The clocks have to be on to load the palette. */
6244 if (!crtc->enabled)
6245 return;
6246
f2b115e6 6247 /* use legacy palette for Ironlake */
bad720ff 6248 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6249 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6250
79e53945
JB		 6251 for (i = 0; i < 256; i++) {
6252 I915_WRITE(palreg + 4 * i,
6253 (intel_crtc->lut_r[i] << 16) |
6254 (intel_crtc->lut_g[i] << 8) |
6255 intel_crtc->lut_b[i]);
6256 }
6257}
6258
560b85bb
CW		 6259static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6260{
6261 struct drm_device *dev = crtc->dev;
6262 struct drm_i915_private *dev_priv = dev->dev_private;
6263 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6264 bool visible = base != 0;
6265 u32 cntl;
6266
6267 if (intel_crtc->cursor_visible == visible)
6268 return;
6269
9db4a9c7 6270 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6271 if (visible) {
6272 /* On these chipsets we can only modify the base whilst
6273 * the cursor is disabled.
6274 */
9db4a9c7 6275 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6276
6277 cntl &= ~(CURSOR_FORMAT_MASK);
6278 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6279 cntl |= CURSOR_ENABLE |
6280 CURSOR_GAMMA_ENABLE |
6281 CURSOR_FORMAT_ARGB;
6282 } else
6283 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6284 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6285
6286 intel_crtc->cursor_visible = visible;
6287}
6288
6289static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6290{
6291 struct drm_device *dev = crtc->dev;
6292 struct drm_i915_private *dev_priv = dev->dev_private;
6293 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6294 int pipe = intel_crtc->pipe;
6295 bool visible = base != 0;
6296
6297 if (intel_crtc->cursor_visible != visible) {
548f245b 6298 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6299 if (base) {
6300 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6301 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6302 cntl |= pipe << 28; /* Connect to correct pipe */
6303 } else {
6304 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6305 cntl |= CURSOR_MODE_DISABLE;
6306 }
9db4a9c7 6307 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6308
6309 intel_crtc->cursor_visible = visible;
6310 }
6311 /* and commit changes on next vblank */
9db4a9c7 6312 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6313}
6314
65a21cd6
JB		 6315static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6316{
6317 struct drm_device *dev = crtc->dev;
6318 struct drm_i915_private *dev_priv = dev->dev_private;
6319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6320 int pipe = intel_crtc->pipe;
6321 bool visible = base != 0;
6322
6323 if (intel_crtc->cursor_visible != visible) {
6324 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6325 if (base) {
6326 cntl &= ~CURSOR_MODE;
6327 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6328 } else {
6329 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6330 cntl |= CURSOR_MODE_DISABLE;
6331 }
6332 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6333
6334 intel_crtc->cursor_visible = visible;
6335 }
6336 /* and commit changes on next vblank */
6337 I915_WRITE(CURBASE_IVB(pipe), base);
6338}
6339
cda4b7d3 6340/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6341static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6342 bool on)
cda4b7d3
CW		 6343{
6344 struct drm_device *dev = crtc->dev;
6345 struct drm_i915_private *dev_priv = dev->dev_private;
6346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6347 int pipe = intel_crtc->pipe;
6348 int x = intel_crtc->cursor_x;
6349 int y = intel_crtc->cursor_y;
560b85bb 6350 u32 base, pos;
cda4b7d3
CW		 6351 bool visible;
6352
6353 pos = 0;
6354
6b383a7f 6355 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6356 base = intel_crtc->cursor_addr;
6357 if (x > (int) crtc->fb->width)
6358 base = 0;
6359
6360 if (y > (int) crtc->fb->height)
6361 base = 0;
6362 } else
6363 base = 0;
6364
6365 if (x < 0) {
6366 if (x + intel_crtc->cursor_width < 0)
6367 base = 0;
6368
6369 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6370 x = -x;
6371 }
6372 pos |= x << CURSOR_X_SHIFT;
6373
6374 if (y < 0) {
6375 if (y + intel_crtc->cursor_height < 0)
6376 base = 0;
6377
6378 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6379 y = -y;
6380 }
6381 pos |= y << CURSOR_Y_SHIFT;
6382
6383 visible = base != 0;
560b85bb 6384 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6385 return;
6386
65a21cd6
JB		 6387 if (IS_IVYBRIDGE(dev)) {
6388 I915_WRITE(CURPOS_IVB(pipe), pos);
6389 ivb_update_cursor(crtc, base);
6390 } else {
6391 I915_WRITE(CURPOS(pipe), pos);
6392 if (IS_845G(dev) || IS_I865G(dev))
6393 i845_update_cursor(crtc, base);
6394 else
6395 i9xx_update_cursor(crtc, base);
6396 }
cda4b7d3
CW		 6397
6398 if (visible)
6399 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6400}
6401
79e53945 6402static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6403 struct drm_file *file,
79e53945
JB		 6404 uint32_t handle,
6405 uint32_t width, uint32_t height)
6406{
6407 struct drm_device *dev = crtc->dev;
6408 struct drm_i915_private *dev_priv = dev->dev_private;
6409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6410 struct drm_i915_gem_object *obj;
cda4b7d3 6411 uint32_t addr;
3f8bc370 6412 int ret;
79e53945 6413
28c97730 6414 DRM_DEBUG_KMS("\n");
79e53945
JB		 6415
6416 /* if we want to turn off the cursor ignore width and height */
6417 if (!handle) {
28c97730 6418 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6419 addr = 0;
05394f39 6420 obj = NULL;
5004417d 6421 mutex_lock(&dev->struct_mutex);
3f8bc370 6422 goto finish;
79e53945
JB		 6423 }
6424
6425 /* Currently we only support 64x64 cursors */
6426 if (width != 64 || height != 64) {
6427 DRM_ERROR("we currently only support 64x64 cursors\n");
6428 return -EINVAL;
6429 }
6430
05394f39 6431 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6432 if (&obj->base == NULL)
79e53945
JB		 6433 return -ENOENT;
6434
05394f39 6435 if (obj->base.size < width * height * 4) {
79e53945 6436 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6437 ret = -ENOMEM;
6438 goto fail;
79e53945
JB		 6439 }
6440
71acb5eb 6441 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6442 mutex_lock(&dev->struct_mutex);
b295d1b6 6443 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6444 if (obj->tiling_mode) {
6445 DRM_ERROR("cursor cannot be tiled\n");
6446 ret = -EINVAL;
6447 goto fail_locked;
6448 }
6449
2da3b9b9 6450 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6451 if (ret) {
6452 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6453 goto fail_locked;
e7b526bb
CW		 6454 }
6455
d9e86c0e
CW		 6456 ret = i915_gem_object_put_fence(obj);
6457 if (ret) {
2da3b9b9 6458 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6459 goto fail_unpin;
6460 }
6461
05394f39 6462 addr = obj->gtt_offset;
71acb5eb 6463 } else {
6eeefaf3 6464 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6465 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6466 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6467 align);
71acb5eb
DA		 6468 if (ret) {
6469 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6470 goto fail_locked;
71acb5eb 6471 }
05394f39 6472 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6473 }
6474
a6c45cf0 6475 if (IS_GEN2(dev))
14b60391
JB		 6476 I915_WRITE(CURSIZE, (height << 12) | width);
6477
3f8bc370 6478 finish:
3f8bc370 6479 if (intel_crtc->cursor_bo) {
b295d1b6 6480 if (dev_priv->info->cursor_needs_physical) {
05394f39 6481 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6482 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6483 } else
6484 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6485 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6486 }
80824003 6487
7f9872e0 6488 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6489
6490 intel_crtc->cursor_addr = addr;
05394f39 6491 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6492 intel_crtc->cursor_width = width;
6493 intel_crtc->cursor_height = height;
6494
6b383a7f 6495 intel_crtc_update_cursor(crtc, true);
3f8bc370 6496
79e53945 6497 return 0;
e7b526bb 6498fail_unpin:
05394f39 6499 i915_gem_object_unpin(obj);
7f9872e0 6500fail_locked:
34b8686e 6501 mutex_unlock(&dev->struct_mutex);
bc9025bd 6502fail:
05394f39 6503 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6504 return ret;
79e53945
JB		 6505}
6506
6507static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6508{
79e53945 6509 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6510
cda4b7d3
CW		 6511 intel_crtc->cursor_x = x;
6512 intel_crtc->cursor_y = y;
652c393a 6513
6b383a7f 6514 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6515
6516 return 0;
6517}
6518
6519/** Sets the color ramps on behalf of RandR */
6520void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6521 u16 blue, int regno)
6522{
6523 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6524
6525 intel_crtc->lut_r[regno] = red >> 8;
6526 intel_crtc->lut_g[regno] = green >> 8;
6527 intel_crtc->lut_b[regno] = blue >> 8;
6528}
6529
b8c00ac5
DA		 6530void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6531 u16 *blue, int regno)
6532{
6533 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6534
6535 *red = intel_crtc->lut_r[regno] << 8;
6536 *green = intel_crtc->lut_g[regno] << 8;
6537 *blue = intel_crtc->lut_b[regno] << 8;
6538}
6539
79e53945 6540static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6541 u16 *blue, uint32_t start, uint32_t size)
79e53945 6542{
7203425a 6543 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6544 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6545
7203425a 6546 for (i = start; i < end; i++) {
79e53945
JB		 6547 intel_crtc->lut_r[i] = red[i] >> 8;
6548 intel_crtc->lut_g[i] = green[i] >> 8;
6549 intel_crtc->lut_b[i] = blue[i] >> 8;
6550 }
6551
6552 intel_crtc_load_lut(crtc);
6553}
6554
6555/**
6556 * Get a pipe with a simple mode set on it for doing load-based monitor
6557 * detection.
6558 *
6559 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6560 * its requirements. The pipe will be connected to no other encoders.
79e53945 6561 *
c751ce4f 6562 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6563 * configured for it. In the future, it could choose to temporarily disable
6564 * some outputs to free up a pipe for its use.
6565 *
6566 * \return crtc, or NULL if no pipes are available.
6567 */
6568
6569/* VESA 640x480x72Hz mode to set on the pipe */
6570static struct drm_display_mode load_detect_mode = {
6571 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6572 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6573};
6574
d2dff872
CW		 6575static struct drm_framebuffer *
6576intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6577 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6578 struct drm_i915_gem_object *obj)
6579{
6580 struct intel_framebuffer *intel_fb;
6581 int ret;
6582
6583 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6584 if (!intel_fb) {
6585 drm_gem_object_unreference_unlocked(&obj->base);
6586 return ERR_PTR(-ENOMEM);
6587 }
6588
6589 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6590 if (ret) {
6591 drm_gem_object_unreference_unlocked(&obj->base);
6592 kfree(intel_fb);
6593 return ERR_PTR(ret);
6594 }
6595
6596 return &intel_fb->base;
6597}
6598
6599static u32
6600intel_framebuffer_pitch_for_width(int width, int bpp)
6601{
6602 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6603 return ALIGN(pitch, 64);
6604}
6605
6606static u32
6607intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6608{
6609 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6610 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6611}
6612
6613static struct drm_framebuffer *
6614intel_framebuffer_create_for_mode(struct drm_device *dev,
6615 struct drm_display_mode *mode,
6616 int depth, int bpp)
6617{
6618 struct drm_i915_gem_object *obj;
308e5bcb 6619 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 6620
6621 obj = i915_gem_alloc_object(dev,
6622 intel_framebuffer_size_for_mode(mode, bpp));
6623 if (obj == NULL)
6624 return ERR_PTR(-ENOMEM);
6625
6626 mode_cmd.width = mode->hdisplay;
6627 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6628 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6629 bpp);
6630 mode_cmd.pixel_format = 0;
d2dff872
CW		 6631
6632 return intel_framebuffer_create(dev, &mode_cmd, obj);
6633}
6634
6635static struct drm_framebuffer *
6636mode_fits_in_fbdev(struct drm_device *dev,
6637 struct drm_display_mode *mode)
6638{
6639 struct drm_i915_private *dev_priv = dev->dev_private;
6640 struct drm_i915_gem_object *obj;
6641 struct drm_framebuffer *fb;
6642
6643 if (dev_priv->fbdev == NULL)
6644 return NULL;
6645
6646 obj = dev_priv->fbdev->ifb.obj;
6647 if (obj == NULL)
6648 return NULL;
6649
6650 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6651 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6652 fb->bits_per_pixel))
d2dff872
CW		 6653 return NULL;
6654
01f2c773 6655 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6656 return NULL;
6657
6658 return fb;
6659}
6660
7173188d
CW		 6661bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6662 struct drm_connector *connector,
6663 struct drm_display_mode *mode,
8261b191 6664 struct intel_load_detect_pipe *old)
79e53945
JB		 6665{
6666 struct intel_crtc *intel_crtc;
6667 struct drm_crtc *possible_crtc;
4ef69c7a 6668 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6669 struct drm_crtc *crtc = NULL;
6670 struct drm_device *dev = encoder->dev;
d2dff872 6671 struct drm_framebuffer *old_fb;
79e53945
JB		 6672 int i = -1;
6673
d2dff872
CW		 6674 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6675 connector->base.id, drm_get_connector_name(connector),
6676 encoder->base.id, drm_get_encoder_name(encoder));
6677
79e53945
JB		 6678 /*
6679 * Algorithm gets a little messy:
7a5e4805 6680 *
79e53945
JB		 6681 * - if the connector already has an assigned crtc, use it (but make
6682 * sure it's on first)
7a5e4805 6683 *
79e53945
JB		 6684 * - try to find the first unused crtc that can drive this connector,
6685 * and use that if we find one
79e53945
JB		 6686 */
6687
6688 /* See if we already have a CRTC for this connector */
6689 if (encoder->crtc) {
6690 crtc = encoder->crtc;
8261b191 6691
79e53945 6692 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6693 old->dpms_mode = intel_crtc->dpms_mode;
6694 old->load_detect_temp = false;
6695
6696 /* Make sure the crtc and connector are running */
79e53945 6697 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 6698 struct drm_encoder_helper_funcs *encoder_funcs;
6699 struct drm_crtc_helper_funcs *crtc_funcs;
6700
79e53945
JB		 6701 crtc_funcs = crtc->helper_private;
6702 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 6703
6704 encoder_funcs = encoder->helper_private;
79e53945
JB		 6705 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6706 }
8261b191 6707
7173188d 6708 return true;
79e53945
JB		 6709 }
6710
6711 /* Find an unused one (if possible) */
6712 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6713 i++;
6714 if (!(encoder->possible_crtcs & (1 << i)))
6715 continue;
6716 if (!possible_crtc->enabled) {
6717 crtc = possible_crtc;
6718 break;
6719 }
79e53945
JB		 6720 }
6721
6722 /*
6723 * If we didn't find an unused CRTC, don't use any.
6724 */
6725 if (!crtc) {
7173188d
CW		 6726 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6727 return false;
79e53945
JB		 6728 }
6729
6730 encoder->crtc = crtc;
c1c43977 6731 connector->encoder = encoder;
79e53945
JB		 6732
6733 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6734 old->dpms_mode = intel_crtc->dpms_mode;
6735 old->load_detect_temp = true;
d2dff872 6736 old->release_fb = NULL;
79e53945 6737
6492711d
CW		 6738 if (!mode)
6739 mode = &load_detect_mode;
79e53945 6740
d2dff872
CW		 6741 old_fb = crtc->fb;
6742
6743 /* We need a framebuffer large enough to accommodate all accesses
6744 * that the plane may generate whilst we perform load detection.
6745 * We can not rely on the fbcon either being present (we get called
6746 * during its initialisation to detect all boot displays, or it may
6747 * not even exist) or that it is large enough to satisfy the
6748 * requested mode.
6749 */
6750 crtc->fb = mode_fits_in_fbdev(dev, mode);
6751 if (crtc->fb == NULL) {
6752 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6753 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6754 old->release_fb = crtc->fb;
6755 } else
6756 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6757 if (IS_ERR(crtc->fb)) {
6758 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6759 crtc->fb = old_fb;
6760 return false;
79e53945 6761 }
79e53945 6762
d2dff872 6763 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 6764 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6765 if (old->release_fb)
6766 old->release_fb->funcs->destroy(old->release_fb);
6767 crtc->fb = old_fb;
6492711d 6768 return false;
79e53945 6769 }
7173188d 6770
79e53945 6771 /* let the connector get through one full cycle before testing */
9d0498a2 6772 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6773
7173188d 6774 return true;
79e53945
JB		 6775}
6776
c1c43977 6777void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 6778 struct drm_connector *connector,
6779 struct intel_load_detect_pipe *old)
79e53945 6780{
4ef69c7a 6781 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6782 struct drm_device *dev = encoder->dev;
6783 struct drm_crtc *crtc = encoder->crtc;
6784 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6785 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6786
d2dff872
CW		 6787 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6788 connector->base.id, drm_get_connector_name(connector),
6789 encoder->base.id, drm_get_encoder_name(encoder));
6790
8261b191 6791 if (old->load_detect_temp) {
c1c43977 6792 connector->encoder = NULL;
79e53945 6793 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 6794
6795 if (old->release_fb)
6796 old->release_fb->funcs->destroy(old->release_fb);
6797
0622a53c 6798 return;
79e53945
JB		 6799 }
6800
c751ce4f 6801 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 6802 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6803 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 6804 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 6805 }
6806}
6807
6808/* Returns the clock of the currently programmed mode of the given pipe. */
6809static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6810{
6811 struct drm_i915_private *dev_priv = dev->dev_private;
6812 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6813 int pipe = intel_crtc->pipe;
548f245b 6814 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6815 u32 fp;
6816 intel_clock_t clock;
6817
6818 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6819 fp = I915_READ(FP0(pipe));
79e53945 6820 else
39adb7a5 6821 fp = I915_READ(FP1(pipe));
79e53945
JB		 6822
6823 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6824 if (IS_PINEVIEW(dev)) {
6825 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6826 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6827 } else {
6828 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6829 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6830 }
6831
a6c45cf0 6832 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6833 if (IS_PINEVIEW(dev))
6834 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6835 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6836 else
6837 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6838 DPLL_FPA01_P1_POST_DIV_SHIFT);
6839
6840 switch (dpll & DPLL_MODE_MASK) {
6841 case DPLLB_MODE_DAC_SERIAL:
6842 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6843 5 : 10;
6844 break;
6845 case DPLLB_MODE_LVDS:
6846 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6847 7 : 14;
6848 break;
6849 default:
28c97730 6850 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6851 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6852 return 0;
6853 }
6854
6855 /* XXX: Handle the 100Mhz refclk */
2177832f 6856 intel_clock(dev, 96000, &clock);
79e53945
JB		 6857 } else {
6858 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6859
6860 if (is_lvds) {
6861 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6862 DPLL_FPA01_P1_POST_DIV_SHIFT);
6863 clock.p2 = 14;
6864
6865 if ((dpll & PLL_REF_INPUT_MASK) ==
6866 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6867 /* XXX: might not be 66MHz */
2177832f 6868 intel_clock(dev, 66000, &clock);
79e53945 6869 } else
2177832f 6870 intel_clock(dev, 48000, &clock);
79e53945
JB		 6871 } else {
6872 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6873 clock.p1 = 2;
6874 else {
6875 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6876 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6877 }
6878 if (dpll & PLL_P2_DIVIDE_BY_4)
6879 clock.p2 = 4;
6880 else
6881 clock.p2 = 2;
6882
2177832f 6883 intel_clock(dev, 48000, &clock);
79e53945
JB		 6884 }
6885 }
6886
6887 /* XXX: It would be nice to validate the clocks, but we can't reuse
6888 * i830PllIsValid() because it relies on the xf86_config connector
6889 * configuration being accurate, which it isn't necessarily.
6890 */
6891
6892 return clock.dot;
6893}
6894
6895/** Returns the currently programmed mode of the given pipe. */
6896struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6897 struct drm_crtc *crtc)
6898{
548f245b 6899 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 6900 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6901 int pipe = intel_crtc->pipe;
6902 struct drm_display_mode *mode;
548f245b
JB		 6903 int htot = I915_READ(HTOTAL(pipe));
6904 int hsync = I915_READ(HSYNC(pipe));
6905 int vtot = I915_READ(VTOTAL(pipe));
6906 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 6907
6908 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6909 if (!mode)
6910 return NULL;
6911
6912 mode->clock = intel_crtc_clock_get(dev, crtc);
6913 mode->hdisplay = (htot & 0xffff) + 1;
6914 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6915 mode->hsync_start = (hsync & 0xffff) + 1;
6916 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6917 mode->vdisplay = (vtot & 0xffff) + 1;
6918 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6919 mode->vsync_start = (vsync & 0xffff) + 1;
6920 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6921
6922 drm_mode_set_name(mode);
6923 drm_mode_set_crtcinfo(mode, 0);
6924
6925 return mode;
6926}
6927
652c393a
JB		 6928#define GPU_IDLE_TIMEOUT 500 /* ms */
6929
6930/* When this timer fires, we've been idle for awhile */
6931static void intel_gpu_idle_timer(unsigned long arg)
6932{
6933 struct drm_device *dev = (struct drm_device *)arg;
6934 drm_i915_private_t *dev_priv = dev->dev_private;
6935
ff7ea4c0
CW		 6936 if (!list_empty(&dev_priv->mm.active_list)) {
6937 /* Still processing requests, so just re-arm the timer. */
6938 mod_timer(&dev_priv->idle_timer, jiffies +
6939 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6940 return;
6941 }
652c393a 6942
ff7ea4c0 6943 dev_priv->busy = false;
01dfba93 6944 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6945}
6946
652c393a
JB		 6947#define CRTC_IDLE_TIMEOUT 1000 /* ms */
6948
6949static void intel_crtc_idle_timer(unsigned long arg)
6950{
6951 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6952 struct drm_crtc *crtc = &intel_crtc->base;
6953 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 6954 struct intel_framebuffer *intel_fb;
652c393a 6955
ff7ea4c0
CW		 6956 intel_fb = to_intel_framebuffer(crtc->fb);
6957 if (intel_fb && intel_fb->obj->active) {
6958 /* The framebuffer is still being accessed by the GPU. */
6959 mod_timer(&intel_crtc->idle_timer, jiffies +
6960 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6961 return;
6962 }
652c393a 6963
ff7ea4c0 6964 intel_crtc->busy = false;
01dfba93 6965 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6966}
6967
3dec0095 6968static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6969{
6970 struct drm_device *dev = crtc->dev;
6971 drm_i915_private_t *dev_priv = dev->dev_private;
6972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6973 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6974 int dpll_reg = DPLL(pipe);
6975 int dpll;
652c393a 6976
bad720ff 6977 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6978 return;
6979
6980 if (!dev_priv->lvds_downclock_avail)
6981 return;
6982
dbdc6479 6983 dpll = I915_READ(dpll_reg);
652c393a 6984 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6985 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a
JB		 6986
6987 /* Unlock panel regs */
dbdc6479
JB		 6988 I915_WRITE(PP_CONTROL,
6989 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
652c393a
JB		 6990
6991 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6992 I915_WRITE(dpll_reg, dpll);
9d0498a2 6993 intel_wait_for_vblank(dev, pipe);
dbdc6479 6994
652c393a
JB		 6995 dpll = I915_READ(dpll_reg);
6996 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6997 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 6998
6999 /* ...and lock them again */
7000 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
7001 }
7002
7003 /* Schedule downclock */
3dec0095
DV		 7004 mod_timer(&intel_crtc->idle_timer, jiffies +
7005 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 7006}
7007
7008static void intel_decrease_pllclock(struct drm_crtc *crtc)
7009{
7010 struct drm_device *dev = crtc->dev;
7011 drm_i915_private_t *dev_priv = dev->dev_private;
7012 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7013 int pipe = intel_crtc->pipe;
9db4a9c7 7014 int dpll_reg = DPLL(pipe);
652c393a
JB		 7015 int dpll = I915_READ(dpll_reg);
7016
bad720ff 7017 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7018 return;
7019
7020 if (!dev_priv->lvds_downclock_avail)
7021 return;
7022
7023 /*
7024 * Since this is called by a timer, we should never get here in
7025 * the manual case.
7026 */
7027 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 7028 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a
JB		 7029
7030 /* Unlock panel regs */
4a655f04
JB		 7031 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
7032 PANEL_UNLOCK_REGS);
652c393a
JB		 7033
7034 dpll |= DISPLAY_RATE_SELECT_FPA1;
7035 I915_WRITE(dpll_reg, dpll);
9d0498a2 7036 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7037 dpll = I915_READ(dpll_reg);
7038 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7039 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7040
7041 /* ...and lock them again */
7042 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
7043 }
7044
7045}
7046
7047/**
7048 * intel_idle_update - adjust clocks for idleness
7049 * @work: work struct
7050 *
7051 * Either the GPU or display (or both) went idle. Check the busy status
7052 * here and adjust the CRTC and GPU clocks as necessary.
7053 */
7054static void intel_idle_update(struct work_struct *work)
7055{
7056 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
7057 idle_work);
7058 struct drm_device *dev = dev_priv->dev;
7059 struct drm_crtc *crtc;
7060 struct intel_crtc *intel_crtc;
7061
7062 if (!i915_powersave)
7063 return;
7064
7065 mutex_lock(&dev->struct_mutex);
7066
7648fa99
JB		 7067 i915_update_gfx_val(dev_priv);
7068
652c393a
JB		 7069 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7070 /* Skip inactive CRTCs */
7071 if (!crtc->fb)
7072 continue;
7073
7074 intel_crtc = to_intel_crtc(crtc);
7075 if (!intel_crtc->busy)
7076 intel_decrease_pllclock(crtc);
7077 }
7078
45ac22c8 7079
652c393a
JB		 7080 mutex_unlock(&dev->struct_mutex);
7081}
7082
7083/**
7084 * intel_mark_busy - mark the GPU and possibly the display busy
7085 * @dev: drm device
7086 * @obj: object we're operating on
7087 *
7088 * Callers can use this function to indicate that the GPU is busy processing
7089 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
7090 * buffer), we'll also mark the display as busy, so we know to increase its
7091 * clock frequency.
7092 */
05394f39 7093void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 7094{
7095 drm_i915_private_t *dev_priv = dev->dev_private;
7096 struct drm_crtc *crtc = NULL;
7097 struct intel_framebuffer *intel_fb;
7098 struct intel_crtc *intel_crtc;
7099
5e17ee74
ZW		 7100 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7101 return;
7102
18b2190c 7103 if (!dev_priv->busy)
28cf798f 7104 dev_priv->busy = true;
18b2190c 7105 else
28cf798f
CW		 7106 mod_timer(&dev_priv->idle_timer, jiffies +
7107 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 7108
7109 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7110 if (!crtc->fb)
7111 continue;
7112
7113 intel_crtc = to_intel_crtc(crtc);
7114 intel_fb = to_intel_framebuffer(crtc->fb);
7115 if (intel_fb->obj == obj) {
7116 if (!intel_crtc->busy) {
7117 /* Non-busy -> busy, upclock */
3dec0095 7118 intel_increase_pllclock(crtc);
652c393a
JB		 7119 intel_crtc->busy = true;
7120 } else {
7121 /* Busy -> busy, put off timer */
7122 mod_timer(&intel_crtc->idle_timer, jiffies +
7123 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7124 }
7125 }
7126 }
7127}
7128
79e53945
JB		 7129static void intel_crtc_destroy(struct drm_crtc *crtc)
7130{
7131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7132 struct drm_device *dev = crtc->dev;
7133 struct intel_unpin_work *work;
7134 unsigned long flags;
7135
7136 spin_lock_irqsave(&dev->event_lock, flags);
7137 work = intel_crtc->unpin_work;
7138 intel_crtc->unpin_work = NULL;
7139 spin_unlock_irqrestore(&dev->event_lock, flags);
7140
7141 if (work) {
7142 cancel_work_sync(&work->work);
7143 kfree(work);
7144 }
79e53945
JB		 7145
7146 drm_crtc_cleanup(crtc);
67e77c5a 7147
79e53945
JB		 7148 kfree(intel_crtc);
7149}
7150
6b95a207
KH		 7151static void intel_unpin_work_fn(struct work_struct *__work)
7152{
7153 struct intel_unpin_work *work =
7154 container_of(__work, struct intel_unpin_work, work);
7155
7156 mutex_lock(&work->dev->struct_mutex);
1690e1eb 7157 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7158 drm_gem_object_unreference(&work->pending_flip_obj->base);
7159 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7160
7782de3b 7161 intel_update_fbc(work->dev);
6b95a207
KH		 7162 mutex_unlock(&work->dev->struct_mutex);
7163 kfree(work);
7164}
7165
1afe3e9d 7166static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7167 struct drm_crtc *crtc)
6b95a207
KH		 7168{
7169 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7171 struct intel_unpin_work *work;
05394f39 7172 struct drm_i915_gem_object *obj;
6b95a207 7173 struct drm_pending_vblank_event *e;
49b14a5c 7174 struct timeval tnow, tvbl;
6b95a207
KH		 7175 unsigned long flags;
7176
7177 /* Ignore early vblank irqs */
7178 if (intel_crtc == NULL)
7179 return;
7180
49b14a5c
MK		 7181 do_gettimeofday(&tnow);
7182
6b95a207
KH		 7183 spin_lock_irqsave(&dev->event_lock, flags);
7184 work = intel_crtc->unpin_work;
7185 if (work == NULL || !work->pending) {
7186 spin_unlock_irqrestore(&dev->event_lock, flags);
7187 return;
7188 }
7189
7190 intel_crtc->unpin_work = NULL;
6b95a207
KH		 7191
7192 if (work->event) {
7193 e = work->event;
49b14a5c 7194 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 7195
7196 /* Called before vblank count and timestamps have
7197 * been updated for the vblank interval of flip
7198 * completion? Need to increment vblank count and
7199 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 7200 * to account for this. We assume this happened if we
7201 * get called over 0.9 frame durations after the last
7202 * timestamped vblank.
7203 *
7204 * This calculation can not be used with vrefresh rates
7205 * below 5Hz (10Hz to be on the safe side) without
7206 * promoting to 64 integers.
0af7e4df 7207 */
49b14a5c
MK		 7208 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7209 9 * crtc->framedur_ns) {
0af7e4df 7210 e->event.sequence++;
49b14a5c
MK		 7211 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7212 crtc->framedur_ns);
0af7e4df
MK		 7213 }
7214
49b14a5c
MK		 7215 e->event.tv_sec = tvbl.tv_sec;
7216 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 7217
6b95a207
KH		 7218 list_add_tail(&e->base.link,
7219 &e->base.file_priv->event_list);
7220 wake_up_interruptible(&e->base.file_priv->event_wait);
7221 }
7222
0af7e4df
MK		 7223 drm_vblank_put(dev, intel_crtc->pipe);
7224
6b95a207
KH		 7225 spin_unlock_irqrestore(&dev->event_lock, flags);
7226
05394f39 7227 obj = work->old_fb_obj;
d9e86c0e 7228
e59f2bac 7229 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 7230 &obj->pending_flip.counter);
7231 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 7232 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 7233
6b95a207 7234 schedule_work(&work->work);
e5510fac
JB		 7235
7236 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7237}
7238
1afe3e9d
JB		 7239void intel_finish_page_flip(struct drm_device *dev, int pipe)
7240{
7241 drm_i915_private_t *dev_priv = dev->dev_private;
7242 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7243
49b14a5c 7244 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7245}
7246
7247void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7248{
7249 drm_i915_private_t *dev_priv = dev->dev_private;
7250 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7251
49b14a5c 7252 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7253}
7254
6b95a207
KH		 7255void intel_prepare_page_flip(struct drm_device *dev, int plane)
7256{
7257 drm_i915_private_t *dev_priv = dev->dev_private;
7258 struct intel_crtc *intel_crtc =
7259 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7260 unsigned long flags;
7261
7262 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 7263 if (intel_crtc->unpin_work) {
4e5359cd
SF		 7264 if ((++intel_crtc->unpin_work->pending) > 1)
7265 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 7266 } else {
7267 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7268 }
6b95a207
KH		 7269 spin_unlock_irqrestore(&dev->event_lock, flags);
7270}
7271
8c9f3aaf
JB		 7272static int intel_gen2_queue_flip(struct drm_device *dev,
7273 struct drm_crtc *crtc,
7274 struct drm_framebuffer *fb,
7275 struct drm_i915_gem_object *obj)
7276{
7277 struct drm_i915_private *dev_priv = dev->dev_private;
7278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7279 unsigned long offset;
7280 u32 flip_mask;
7281 int ret;
7282
7283 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7284 if (ret)
7285 goto out;
7286
7287 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 7288 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf
JB		 7289
7290 ret = BEGIN_LP_RING(6);
7291 if (ret)
7292 goto out;
7293
7294 /* Can't queue multiple flips, so wait for the previous
7295 * one to finish before executing the next.
7296 */
7297 if (intel_crtc->plane)
7298 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7299 else
7300 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7301 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7302 OUT_RING(MI_NOOP);
7303 OUT_RING(MI_DISPLAY_FLIP |
7304 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7305 OUT_RING(fb->pitches[0]);
8c9f3aaf 7306 OUT_RING(obj->gtt_offset + offset);
c6a32fcb 7307 OUT_RING(0); /* aux display base address, unused */
8c9f3aaf
JB		 7308 ADVANCE_LP_RING();
7309out:
7310 return ret;
7311}
7312
7313static int intel_gen3_queue_flip(struct drm_device *dev,
7314 struct drm_crtc *crtc,
7315 struct drm_framebuffer *fb,
7316 struct drm_i915_gem_object *obj)
7317{
7318 struct drm_i915_private *dev_priv = dev->dev_private;
7319 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7320 unsigned long offset;
7321 u32 flip_mask;
7322 int ret;
7323
7324 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7325 if (ret)
7326 goto out;
7327
7328 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 7329 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf
JB		 7330
7331 ret = BEGIN_LP_RING(6);
7332 if (ret)
7333 goto out;
7334
7335 if (intel_crtc->plane)
7336 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7337 else
7338 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7339 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7340 OUT_RING(MI_NOOP);
7341 OUT_RING(MI_DISPLAY_FLIP_I915 |
7342 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7343 OUT_RING(fb->pitches[0]);
8c9f3aaf
JB		 7344 OUT_RING(obj->gtt_offset + offset);
7345 OUT_RING(MI_NOOP);
7346
7347 ADVANCE_LP_RING();
7348out:
7349 return ret;
7350}
7351
7352static int intel_gen4_queue_flip(struct drm_device *dev,
7353 struct drm_crtc *crtc,
7354 struct drm_framebuffer *fb,
7355 struct drm_i915_gem_object *obj)
7356{
7357 struct drm_i915_private *dev_priv = dev->dev_private;
7358 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7359 uint32_t pf, pipesrc;
7360 int ret;
7361
7362 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7363 if (ret)
7364 goto out;
7365
7366 ret = BEGIN_LP_RING(4);
7367 if (ret)
7368 goto out;
7369
7370 /* i965+ uses the linear or tiled offsets from the
7371 * Display Registers (which do not change across a page-flip)
7372 * so we need only reprogram the base address.
7373 */
7374 OUT_RING(MI_DISPLAY_FLIP |
7375 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7376 OUT_RING(fb->pitches[0]);
8c9f3aaf
JB		 7377 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7378
7379 /* XXX Enabling the panel-fitter across page-flip is so far
7380 * untested on non-native modes, so ignore it for now.
7381 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7382 */
7383 pf = 0;
7384 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7385 OUT_RING(pf | pipesrc);
7386 ADVANCE_LP_RING();
7387out:
7388 return ret;
7389}
7390
7391static int intel_gen6_queue_flip(struct drm_device *dev,
7392 struct drm_crtc *crtc,
7393 struct drm_framebuffer *fb,
7394 struct drm_i915_gem_object *obj)
7395{
7396 struct drm_i915_private *dev_priv = dev->dev_private;
7397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7398 uint32_t pf, pipesrc;
7399 int ret;
7400
7401 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7402 if (ret)
7403 goto out;
7404
7405 ret = BEGIN_LP_RING(4);
7406 if (ret)
7407 goto out;
7408
7409 OUT_RING(MI_DISPLAY_FLIP |
7410 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7411 OUT_RING(fb->pitches[0] | obj->tiling_mode);
8c9f3aaf
JB		 7412 OUT_RING(obj->gtt_offset);
7413
7414 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7415 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7416 OUT_RING(pf | pipesrc);
7417 ADVANCE_LP_RING();
7418out:
7419 return ret;
7420}
7421
7c9017e5
JB		 7422/*
7423 * On gen7 we currently use the blit ring because (in early silicon at least)
7424 * the render ring doesn't give us interrpts for page flip completion, which
7425 * means clients will hang after the first flip is queued. Fortunately the
7426 * blit ring generates interrupts properly, so use it instead.
7427 */
7428static int intel_gen7_queue_flip(struct drm_device *dev,
7429 struct drm_crtc *crtc,
7430 struct drm_framebuffer *fb,
7431 struct drm_i915_gem_object *obj)
7432{
7433 struct drm_i915_private *dev_priv = dev->dev_private;
7434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7435 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7436 int ret;
7437
7438 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7439 if (ret)
7440 goto out;
7441
7442 ret = intel_ring_begin(ring, 4);
7443 if (ret)
7444 goto out;
7445
7446 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
01f2c773 7447 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7c9017e5
JB		 7448 intel_ring_emit(ring, (obj->gtt_offset));
7449 intel_ring_emit(ring, (MI_NOOP));
7450 intel_ring_advance(ring);
7451out:
7452 return ret;
7453}
7454
8c9f3aaf
JB		 7455static int intel_default_queue_flip(struct drm_device *dev,
7456 struct drm_crtc *crtc,
7457 struct drm_framebuffer *fb,
7458 struct drm_i915_gem_object *obj)
7459{
7460 return -ENODEV;
7461}
7462
6b95a207
KH		 7463static int intel_crtc_page_flip(struct drm_crtc *crtc,
7464 struct drm_framebuffer *fb,
7465 struct drm_pending_vblank_event *event)
7466{
7467 struct drm_device *dev = crtc->dev;
7468 struct drm_i915_private *dev_priv = dev->dev_private;
7469 struct intel_framebuffer *intel_fb;
05394f39 7470 struct drm_i915_gem_object *obj;
6b95a207
KH		 7471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7472 struct intel_unpin_work *work;
8c9f3aaf 7473 unsigned long flags;
52e68630 7474 int ret;
6b95a207
KH		 7475
7476 work = kzalloc(sizeof *work, GFP_KERNEL);
7477 if (work == NULL)
7478 return -ENOMEM;
7479
6b95a207
KH		 7480 work->event = event;
7481 work->dev = crtc->dev;
7482 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7483 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7484 INIT_WORK(&work->work, intel_unpin_work_fn);
7485
7317c75e
JB		 7486 ret = drm_vblank_get(dev, intel_crtc->pipe);
7487 if (ret)
7488 goto free_work;
7489
6b95a207
KH		 7490 /* We borrow the event spin lock for protecting unpin_work */
7491 spin_lock_irqsave(&dev->event_lock, flags);
7492 if (intel_crtc->unpin_work) {
7493 spin_unlock_irqrestore(&dev->event_lock, flags);
7494 kfree(work);
7317c75e 7495 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7496
7497 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7498 return -EBUSY;
7499 }
7500 intel_crtc->unpin_work = work;
7501 spin_unlock_irqrestore(&dev->event_lock, flags);
7502
7503 intel_fb = to_intel_framebuffer(fb);
7504 obj = intel_fb->obj;
7505
468f0b44 7506 mutex_lock(&dev->struct_mutex);
6b95a207 7507
75dfca80 7508 /* Reference the objects for the scheduled work. */
05394f39
CW		 7509 drm_gem_object_reference(&work->old_fb_obj->base);
7510 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7511
7512 crtc->fb = fb;
96b099fd 7513
e1f99ce6 7514 work->pending_flip_obj = obj;
e1f99ce6 7515
4e5359cd
SF		 7516 work->enable_stall_check = true;
7517
e1f99ce6
CW		 7518 /* Block clients from rendering to the new back buffer until
7519 * the flip occurs and the object is no longer visible.
7520 */
05394f39 7521 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 7522
8c9f3aaf
JB		 7523 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7524 if (ret)
7525 goto cleanup_pending;
6b95a207 7526
7782de3b 7527 intel_disable_fbc(dev);
6b95a207
KH		 7528 mutex_unlock(&dev->struct_mutex);
7529
e5510fac
JB		 7530 trace_i915_flip_request(intel_crtc->plane, obj);
7531
6b95a207 7532 return 0;
96b099fd 7533
8c9f3aaf
JB		 7534cleanup_pending:
7535 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 7536 drm_gem_object_unreference(&work->old_fb_obj->base);
7537 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7538 mutex_unlock(&dev->struct_mutex);
7539
7540 spin_lock_irqsave(&dev->event_lock, flags);
7541 intel_crtc->unpin_work = NULL;
7542 spin_unlock_irqrestore(&dev->event_lock, flags);
7543
7317c75e
JB		 7544 drm_vblank_put(dev, intel_crtc->pipe);
7545free_work:
96b099fd
CW		 7546 kfree(work);
7547
7548 return ret;
6b95a207
KH		 7549}
7550
47f1c6c9
CW		 7551static void intel_sanitize_modesetting(struct drm_device *dev,
7552 int pipe, int plane)
7553{
7554 struct drm_i915_private *dev_priv = dev->dev_private;
7555 u32 reg, val;
7556
7557 if (HAS_PCH_SPLIT(dev))
7558 return;
7559
7560 /* Who knows what state these registers were left in by the BIOS or
7561 * grub?
7562 *
7563 * If we leave the registers in a conflicting state (e.g. with the
7564 * display plane reading from the other pipe than the one we intend
7565 * to use) then when we attempt to teardown the active mode, we will
7566 * not disable the pipes and planes in the correct order -- leaving
7567 * a plane reading from a disabled pipe and possibly leading to
7568 * undefined behaviour.
7569 */
7570
7571 reg = DSPCNTR(plane);
7572 val = I915_READ(reg);
7573
7574 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7575 return;
7576 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7577 return;
7578
7579 /* This display plane is active and attached to the other CPU pipe. */
7580 pipe = !pipe;
7581
7582 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 7583 intel_disable_plane(dev_priv, plane, pipe);
7584 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 7585}
79e53945 7586
f6e5b160
CW		 7587static void intel_crtc_reset(struct drm_crtc *crtc)
7588{
7589 struct drm_device *dev = crtc->dev;
7590 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7591
7592 /* Reset flags back to the 'unknown' status so that they
7593 * will be correctly set on the initial modeset.
7594 */
7595 intel_crtc->dpms_mode = -1;
7596
7597 /* We need to fix up any BIOS configuration that conflicts with
7598 * our expectations.
7599 */
7600 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7601}
7602
7603static struct drm_crtc_helper_funcs intel_helper_funcs = {
7604 .dpms = intel_crtc_dpms,
7605 .mode_fixup = intel_crtc_mode_fixup,
7606 .mode_set = intel_crtc_mode_set,
7607 .mode_set_base = intel_pipe_set_base,
7608 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7609 .load_lut = intel_crtc_load_lut,
7610 .disable = intel_crtc_disable,
7611};
7612
7613static const struct drm_crtc_funcs intel_crtc_funcs = {
7614 .reset = intel_crtc_reset,
7615 .cursor_set = intel_crtc_cursor_set,
7616 .cursor_move = intel_crtc_cursor_move,
7617 .gamma_set = intel_crtc_gamma_set,
7618 .set_config = drm_crtc_helper_set_config,
7619 .destroy = intel_crtc_destroy,
7620 .page_flip = intel_crtc_page_flip,
7621};
7622
b358d0a6 7623static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 7624{
22fd0fab 7625 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 7626 struct intel_crtc *intel_crtc;
7627 int i;
7628
7629 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7630 if (intel_crtc == NULL)
7631 return;
7632
7633 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7634
7635 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7636 for (i = 0; i < 256; i++) {
7637 intel_crtc->lut_r[i] = i;
7638 intel_crtc->lut_g[i] = i;
7639 intel_crtc->lut_b[i] = i;
7640 }
7641
80824003
JB		 7642 /* Swap pipes & planes for FBC on pre-965 */
7643 intel_crtc->pipe = pipe;
7644 intel_crtc->plane = pipe;
e2e767ab 7645 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7646 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7647 intel_crtc->plane = !pipe;
80824003
JB		 7648 }
7649
22fd0fab
JB		 7650 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7651 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7652 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7653 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7654
5d1d0cc8 7655 intel_crtc_reset(&intel_crtc->base);
04dbff52 7656 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 7657 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 7658
7659 if (HAS_PCH_SPLIT(dev)) {
4b645f14
JB		 7660 if (pipe == 2 && IS_IVYBRIDGE(dev))
7661 intel_crtc->no_pll = true;
7e7d76c3
JB		 7662 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7663 intel_helper_funcs.commit = ironlake_crtc_commit;
7664 } else {
7665 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7666 intel_helper_funcs.commit = i9xx_crtc_commit;
7667 }
7668
79e53945
JB		 7669 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7670
652c393a
JB		 7671 intel_crtc->busy = false;
7672
7673 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7674 (unsigned long)intel_crtc);
79e53945
JB		 7675}
7676
08d7b3d1 7677int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7678 struct drm_file *file)
08d7b3d1
CW		 7679{
7680 drm_i915_private_t *dev_priv = dev->dev_private;
7681 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 7682 struct drm_mode_object *drmmode_obj;
7683 struct intel_crtc *crtc;
08d7b3d1
CW		 7684
7685 if (!dev_priv) {
7686 DRM_ERROR("called with no initialization\n");
7687 return -EINVAL;
7688 }
7689
c05422d5
DV		 7690 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7691 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7692
c05422d5 7693 if (!drmmode_obj) {
08d7b3d1
CW		 7694 DRM_ERROR("no such CRTC id\n");
7695 return -EINVAL;
7696 }
7697
c05422d5
DV		 7698 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7699 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7700
c05422d5 7701 return 0;
08d7b3d1
CW		 7702}
7703
c5e4df33 7704static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 7705{
4ef69c7a 7706 struct intel_encoder *encoder;
79e53945 7707 int index_mask = 0;
79e53945
JB		 7708 int entry = 0;
7709
4ef69c7a
CW		 7710 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7711 if (type_mask & encoder->clone_mask)
79e53945
JB		 7712 index_mask |= (1 << entry);
7713 entry++;
7714 }
4ef69c7a 7715
79e53945
JB		 7716 return index_mask;
7717}
7718
4d302442
CW		 7719static bool has_edp_a(struct drm_device *dev)
7720{
7721 struct drm_i915_private *dev_priv = dev->dev_private;
7722
7723 if (!IS_MOBILE(dev))
7724 return false;
7725
7726 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7727 return false;
7728
7729 if (IS_GEN5(dev) &&
7730 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7731 return false;
7732
7733 return true;
7734}
7735
79e53945
JB		 7736static void intel_setup_outputs(struct drm_device *dev)
7737{
725e30ad 7738 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 7739 struct intel_encoder *encoder;
cb0953d7 7740 bool dpd_is_edp = false;
c5d1b51d 7741 bool has_lvds = false;
79e53945 7742
541998a1 7743 if (IS_MOBILE(dev) && !IS_I830(dev))
c5d1b51d
CW		 7744 has_lvds = intel_lvds_init(dev);
7745 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7746 /* disable the panel fitter on everything but LVDS */
7747 I915_WRITE(PFIT_CONTROL, 0);
7748 }
79e53945 7749
bad720ff 7750 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 7751 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 7752
4d302442 7753 if (has_edp_a(dev))
32f9d658
ZW		 7754 intel_dp_init(dev, DP_A);
7755
cb0953d7
AJ		 7756 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7757 intel_dp_init(dev, PCH_DP_D);
7758 }
7759
7760 intel_crt_init(dev);
7761
7762 if (HAS_PCH_SPLIT(dev)) {
7763 int found;
7764
30ad48b7 7765 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca
ZY		 7766 /* PCH SDVOB multiplex with HDMIB */
7767 found = intel_sdvo_init(dev, PCH_SDVOB);
30ad48b7
ZW		 7768 if (!found)
7769 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 7770 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7771 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 7772 }
7773
7774 if (I915_READ(HDMIC) & PORT_DETECTED)
7775 intel_hdmi_init(dev, HDMIC);
7776
7777 if (I915_READ(HDMID) & PORT_DETECTED)
7778 intel_hdmi_init(dev, HDMID);
7779
5eb08b69
ZW		 7780 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7781 intel_dp_init(dev, PCH_DP_C);
7782
cb0953d7 7783 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 7784 intel_dp_init(dev, PCH_DP_D);
7785
103a196f 7786 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 7787 bool found = false;
7d57382e 7788
725e30ad 7789 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 7790 DRM_DEBUG_KMS("probing SDVOB\n");
725e30ad 7791 found = intel_sdvo_init(dev, SDVOB);
b01f2c3a
JB		 7792 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7793 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 7794 intel_hdmi_init(dev, SDVOB);
b01f2c3a 7795 }
27185ae1 7796
b01f2c3a
JB		 7797 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7798 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 7799 intel_dp_init(dev, DP_B);
b01f2c3a 7800 }
725e30ad 7801 }
13520b05
KH		 7802
7803 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 7804
b01f2c3a
JB		 7805 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7806 DRM_DEBUG_KMS("probing SDVOC\n");
725e30ad 7807 found = intel_sdvo_init(dev, SDVOC);
b01f2c3a 7808 }
27185ae1
ML		 7809
7810 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7811
b01f2c3a
JB		 7812 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7813 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 7814 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 7815 }
7816 if (SUPPORTS_INTEGRATED_DP(dev)) {
7817 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 7818 intel_dp_init(dev, DP_C);
b01f2c3a 7819 }
725e30ad 7820 }
27185ae1 7821
b01f2c3a
JB		 7822 if (SUPPORTS_INTEGRATED_DP(dev) &&
7823 (I915_READ(DP_D) & DP_DETECTED)) {
7824 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 7825 intel_dp_init(dev, DP_D);
b01f2c3a 7826 }
bad720ff 7827 } else if (IS_GEN2(dev))
79e53945
JB		 7828 intel_dvo_init(dev);
7829
103a196f 7830 if (SUPPORTS_TV(dev))
79e53945
JB		 7831 intel_tv_init(dev);
7832
4ef69c7a
CW		 7833 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7834 encoder->base.possible_crtcs = encoder->crtc_mask;
7835 encoder->base.possible_clones =
7836 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 7837 }
47356eb6 7838
2c7111db
CW		 7839 /* disable all the possible outputs/crtcs before entering KMS mode */
7840 drm_helper_disable_unused_functions(dev);
9fb526db
KP		 7841
7842 if (HAS_PCH_SPLIT(dev))
7843 ironlake_init_pch_refclk(dev);
79e53945
JB		 7844}
7845
7846static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7847{
7848 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 7849
7850 drm_framebuffer_cleanup(fb);
05394f39 7851 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 7852
7853 kfree(intel_fb);
7854}
7855
7856static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 7857 struct drm_file *file,
79e53945
JB		 7858 unsigned int *handle)
7859{
7860 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 7861 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 7862
05394f39 7863 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 7864}
7865
7866static const struct drm_framebuffer_funcs intel_fb_funcs = {
7867 .destroy = intel_user_framebuffer_destroy,
7868 .create_handle = intel_user_framebuffer_create_handle,
7869};
7870
38651674
DA		 7871int intel_framebuffer_init(struct drm_device *dev,
7872 struct intel_framebuffer *intel_fb,
308e5bcb 7873 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 7874 struct drm_i915_gem_object *obj)
79e53945 7875{
79e53945
JB		 7876 int ret;
7877
05394f39 7878 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 7879 return -EINVAL;
7880
308e5bcb 7881 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 7882 return -EINVAL;
7883
308e5bcb 7884 switch (mode_cmd->pixel_format) {
04b3924d
VS		 7885 case DRM_FORMAT_RGB332:
7886 case DRM_FORMAT_RGB565:
7887 case DRM_FORMAT_XRGB8888:
7888 case DRM_FORMAT_ARGB8888:
7889 case DRM_FORMAT_XRGB2101010:
7890 case DRM_FORMAT_ARGB2101010:
308e5bcb 7891 /* RGB formats are common across chipsets */
b5626747 7892 break;
04b3924d
VS		 7893 case DRM_FORMAT_YUYV:
7894 case DRM_FORMAT_UYVY:
7895 case DRM_FORMAT_YVYU:
7896 case DRM_FORMAT_VYUY:
57cd6508
CW		 7897 break;
7898 default:
aca25848
ED		 7899 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7900 mode_cmd->pixel_format);
57cd6508
CW		 7901 return -EINVAL;
7902 }
7903
79e53945
JB		 7904 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7905 if (ret) {
7906 DRM_ERROR("framebuffer init failed %d\n", ret);
7907 return ret;
7908 }
7909
7910 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 7911 intel_fb->obj = obj;
79e53945
JB		 7912 return 0;
7913}
7914
79e53945
JB		 7915static struct drm_framebuffer *
7916intel_user_framebuffer_create(struct drm_device *dev,
7917 struct drm_file *filp,
308e5bcb 7918 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 7919{
05394f39 7920 struct drm_i915_gem_object *obj;
79e53945 7921
308e5bcb
JB		 7922 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7923 mode_cmd->handles[0]));
c8725226 7924 if (&obj->base == NULL)
cce13ff7 7925 return ERR_PTR(-ENOENT);
79e53945 7926
d2dff872 7927 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 7928}
7929
79e53945 7930static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 7931 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 7932 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 7933};
7934
05394f39 7935static struct drm_i915_gem_object *
aa40d6bb 7936intel_alloc_context_page(struct drm_device *dev)
9ea8d059 7937{
05394f39 7938 struct drm_i915_gem_object *ctx;
9ea8d059
CW		 7939 int ret;
7940
2c34b850
BW		 7941 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7942
aa40d6bb
ZN		 7943 ctx = i915_gem_alloc_object(dev, 4096);
7944 if (!ctx) {
9ea8d059
CW		 7945 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7946 return NULL;
7947 }
7948
75e9e915 7949 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW		 7950 if (ret) {
7951 DRM_ERROR("failed to pin power context: %d\n", ret);
7952 goto err_unref;
7953 }
7954
aa40d6bb 7955 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW		 7956 if (ret) {
7957 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7958 goto err_unpin;
7959 }
9ea8d059 7960
aa40d6bb 7961 return ctx;
9ea8d059
CW		 7962
7963err_unpin:
aa40d6bb 7964 i915_gem_object_unpin(ctx);
9ea8d059 7965err_unref:
05394f39 7966 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW		 7967 mutex_unlock(&dev->struct_mutex);
7968 return NULL;
7969}
7970
7648fa99
JB		 7971bool ironlake_set_drps(struct drm_device *dev, u8 val)
7972{
7973 struct drm_i915_private *dev_priv = dev->dev_private;
7974 u16 rgvswctl;
7975
7976 rgvswctl = I915_READ16(MEMSWCTL);
7977 if (rgvswctl & MEMCTL_CMD_STS) {
7978 DRM_DEBUG("gpu busy, RCS change rejected\n");
7979 return false; /* still busy with another command */
7980 }
7981
7982 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7983 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7984 I915_WRITE16(MEMSWCTL, rgvswctl);
7985 POSTING_READ16(MEMSWCTL);
7986
7987 rgvswctl |= MEMCTL_CMD_STS;
7988 I915_WRITE16(MEMSWCTL, rgvswctl);
7989
7990 return true;
7991}
7992
f97108d1
JB		 7993void ironlake_enable_drps(struct drm_device *dev)
7994{
7995 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7996 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 7997 u8 fmax, fmin, fstart, vstart;
f97108d1 7998
ea056c14
JB		 7999 /* Enable temp reporting */
8000 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
8001 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
8002
f97108d1
JB		 8003 /* 100ms RC evaluation intervals */
8004 I915_WRITE(RCUPEI, 100000);
8005 I915_WRITE(RCDNEI, 100000);
8006
8007 /* Set max/min thresholds to 90ms and 80ms respectively */
8008 I915_WRITE(RCBMAXAVG, 90000);
8009 I915_WRITE(RCBMINAVG, 80000);
8010
8011 I915_WRITE(MEMIHYST, 1);
8012
8013 /* Set up min, max, and cur for interrupt handling */
8014 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
8015 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
8016 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
8017 MEMMODE_FSTART_SHIFT;
7648fa99 8018
f97108d1
JB		 8019 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
8020 PXVFREQ_PX_SHIFT;
8021
80dbf4b7 8022 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB		 8023 dev_priv->fstart = fstart;
8024
80dbf4b7 8025 dev_priv->max_delay = fstart;
f97108d1
JB		 8026 dev_priv->min_delay = fmin;
8027 dev_priv->cur_delay = fstart;
8028
80dbf4b7
JB		 8029 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
8030 fmax, fmin, fstart);
7648fa99 8031
f97108d1
JB		 8032 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
8033
8034 /*
8035 * Interrupts will be enabled in ironlake_irq_postinstall
8036 */
8037
8038 I915_WRITE(VIDSTART, vstart);
8039 POSTING_READ(VIDSTART);
8040
8041 rgvmodectl |= MEMMODE_SWMODE_EN;
8042 I915_WRITE(MEMMODECTL, rgvmodectl);
8043
481b6af3 8044 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 8045 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB		 8046 msleep(1);
8047
7648fa99 8048 ironlake_set_drps(dev, fstart);
f97108d1 8049
7648fa99
JB		 8050 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
8051 I915_READ(0x112e0);
8052 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
8053 dev_priv->last_count2 = I915_READ(0x112f4);
8054 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB		 8055}
8056
8057void ironlake_disable_drps(struct drm_device *dev)
8058{
8059 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 8060 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB		 8061
8062 /* Ack interrupts, disable EFC interrupt */
8063 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
8064 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
8065 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
8066 I915_WRITE(DEIIR, DE_PCU_EVENT);
8067 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
8068
8069 /* Go back to the starting frequency */
7648fa99 8070 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB		 8071 msleep(1);
8072 rgvswctl |= MEMCTL_CMD_STS;
8073 I915_WRITE(MEMSWCTL, rgvswctl);
8074 msleep(1);
8075
8076}
8077
3b8d8d91
JB		 8078void gen6_set_rps(struct drm_device *dev, u8 val)
8079{
8080 struct drm_i915_private *dev_priv = dev->dev_private;
8081 u32 swreq;
8082
8083 swreq = (val & 0x3ff) << 25;
8084 I915_WRITE(GEN6_RPNSWREQ, swreq);
8085}
8086
8087void gen6_disable_rps(struct drm_device *dev)
8088{
8089 struct drm_i915_private *dev_priv = dev->dev_private;
8090
8091 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8092 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8093 I915_WRITE(GEN6_PMIER, 0);
6fdd4d98
DV		 8094 /* Complete PM interrupt masking here doesn't race with the rps work
8095 * item again unmasking PM interrupts because that is using a different
8096 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8097 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
4912d041
BW		 8098
8099 spin_lock_irq(&dev_priv->rps_lock);
8100 dev_priv->pm_iir = 0;
8101 spin_unlock_irq(&dev_priv->rps_lock);
8102
3b8d8d91
JB		 8103 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8104}
8105
7648fa99
JB		 8106static unsigned long intel_pxfreq(u32 vidfreq)
8107{
8108 unsigned long freq;
8109 int div = (vidfreq & 0x3f0000) >> 16;
8110 int post = (vidfreq & 0x3000) >> 12;
8111 int pre = (vidfreq & 0x7);
8112
8113 if (!pre)
8114 return 0;
8115
8116 freq = ((div * 133333) / ((1<<post) * pre));
8117
8118 return freq;
8119}
8120
8121void intel_init_emon(struct drm_device *dev)
8122{
8123 struct drm_i915_private *dev_priv = dev->dev_private;
8124 u32 lcfuse;
8125 u8 pxw[16];
8126 int i;
8127
8128 /* Disable to program */
8129 I915_WRITE(ECR, 0);
8130 POSTING_READ(ECR);
8131
8132 /* Program energy weights for various events */
8133 I915_WRITE(SDEW, 0x15040d00);
8134 I915_WRITE(CSIEW0, 0x007f0000);
8135 I915_WRITE(CSIEW1, 0x1e220004);
8136 I915_WRITE(CSIEW2, 0x04000004);
8137
8138 for (i = 0; i < 5; i++)
8139 I915_WRITE(PEW + (i * 4), 0);
8140 for (i = 0; i < 3; i++)
8141 I915_WRITE(DEW + (i * 4), 0);
8142
8143 /* Program P-state weights to account for frequency power adjustment */
8144 for (i = 0; i < 16; i++) {
8145 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8146 unsigned long freq = intel_pxfreq(pxvidfreq);
8147 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8148 PXVFREQ_PX_SHIFT;
8149 unsigned long val;
8150
8151 val = vid * vid;
8152 val *= (freq / 1000);
8153 val *= 255;
8154 val /= (127*127*900);
8155 if (val > 0xff)
8156 DRM_ERROR("bad pxval: %ld\n", val);
8157 pxw[i] = val;
8158 }
8159 /* Render standby states get 0 weight */
8160 pxw[14] = 0;
8161 pxw[15] = 0;
8162
8163 for (i = 0; i < 4; i++) {
8164 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8165 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8166 I915_WRITE(PXW + (i * 4), val);
8167 }
8168
8169 /* Adjust magic regs to magic values (more experimental results) */
8170 I915_WRITE(OGW0, 0);
8171 I915_WRITE(OGW1, 0);
8172 I915_WRITE(EG0, 0x00007f00);
8173 I915_WRITE(EG1, 0x0000000e);
8174 I915_WRITE(EG2, 0x000e0000);
8175 I915_WRITE(EG3, 0x68000300);
8176 I915_WRITE(EG4, 0x42000000);
8177 I915_WRITE(EG5, 0x00140031);
8178 I915_WRITE(EG6, 0);
8179 I915_WRITE(EG7, 0);
8180
8181 for (i = 0; i < 8; i++)
8182 I915_WRITE(PXWL + (i * 4), 0);
8183
8184 /* Enable PMON + select events */
8185 I915_WRITE(ECR, 0x80000019);
8186
8187 lcfuse = I915_READ(LCFUSE02);
8188
8189 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8190}
8191
c0f372b3
KP		 8192static bool intel_enable_rc6(struct drm_device *dev)
8193{
8194 /*
8195 * Respect the kernel parameter if it is set
8196 */
8197 if (i915_enable_rc6 >= 0)
8198 return i915_enable_rc6;
8199
8200 /*
8201 * Disable RC6 on Ironlake
8202 */
8203 if (INTEL_INFO(dev)->gen == 5)
8204 return 0;
8205
8206 /*
371de6e4 8207 * Disable rc6 on Sandybridge
c0f372b3
KP		 8208 */
8209 if (INTEL_INFO(dev)->gen == 6) {
371de6e4
KP		 8210 DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
8211 return 0;
c0f372b3
KP		 8212 }
8213 DRM_DEBUG_DRIVER("RC6 enabled\n");
8214 return 1;
8215}
8216
3b8d8d91 8217void gen6_enable_rps(struct drm_i915_private *dev_priv)
8fd26859 8218{
a6044e23
JB		 8219 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8220 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7df8721b 8221 u32 pcu_mbox, rc6_mask = 0;
a6044e23 8222 int cur_freq, min_freq, max_freq;
8fd26859
CW		 8223 int i;
8224
8225 /* Here begins a magic sequence of register writes to enable
8226 * auto-downclocking.
8227 *
8228 * Perhaps there might be some value in exposing these to
8229 * userspace...
8230 */
8231 I915_WRITE(GEN6_RC_STATE, 0);
d1ebd816 8232 mutex_lock(&dev_priv->dev->struct_mutex);
fcca7926 8233 gen6_gt_force_wake_get(dev_priv);
8fd26859 8234
3b8d8d91 8235 /* disable the counters and set deterministic thresholds */
8fd26859
CW		 8236 I915_WRITE(GEN6_RC_CONTROL, 0);
8237
8238 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8239 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8240 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8241 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8242 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8243
8244 for (i = 0; i < I915_NUM_RINGS; i++)
8245 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8246
8247 I915_WRITE(GEN6_RC_SLEEP, 0);
8248 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8249 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8250 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8251 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8252
c0f372b3 8253 if (intel_enable_rc6(dev_priv->dev))
7df8721b
JB		 8254 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
8255 GEN6_RC_CTL_RC6_ENABLE;
8256
8fd26859 8257 I915_WRITE(GEN6_RC_CONTROL,
7df8721b 8258 rc6_mask |
9c3d2f7f 8259 GEN6_RC_CTL_EI_MODE(1) |
8fd26859
CW		 8260 GEN6_RC_CTL_HW_ENABLE);
8261
3b8d8d91 8262 I915_WRITE(GEN6_RPNSWREQ,
8fd26859
CW		 8263 GEN6_FREQUENCY(10) |
8264 GEN6_OFFSET(0) |
8265 GEN6_AGGRESSIVE_TURBO);
8266 I915_WRITE(GEN6_RC_VIDEO_FREQ,
8267 GEN6_FREQUENCY(12));
8268
8269 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8270 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8271 18 << 24 |
8272 6 << 16);
ccab5c82
JB		 8273 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8274 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8fd26859 8275 I915_WRITE(GEN6_RP_UP_EI, 100000);
ccab5c82 8276 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8fd26859
CW		 8277 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8278 I915_WRITE(GEN6_RP_CONTROL,
8279 GEN6_RP_MEDIA_TURBO |
6ed55ee7 8280 GEN6_RP_MEDIA_HW_MODE |
8fd26859
CW		 8281 GEN6_RP_MEDIA_IS_GFX |
8282 GEN6_RP_ENABLE |
ccab5c82
JB		 8283 GEN6_RP_UP_BUSY_AVG |
8284 GEN6_RP_DOWN_IDLE_CONT);
8fd26859
CW		 8285
8286 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8287 500))
8288 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8289
8290 I915_WRITE(GEN6_PCODE_DATA, 0);
8291 I915_WRITE(GEN6_PCODE_MAILBOX,
8292 GEN6_PCODE_READY |
8293 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8294 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8295 500))
8296 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8297
a6044e23
JB		 8298 min_freq = (rp_state_cap & 0xff0000) >> 16;
8299 max_freq = rp_state_cap & 0xff;
8300 cur_freq = (gt_perf_status & 0xff00) >> 8;
8301
8302 /* Check for overclock support */
8303 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8304 500))
8305 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8306 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8307 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8308 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8309 500))
8310 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8311 if (pcu_mbox & (1<<31)) { /* OC supported */
8312 max_freq = pcu_mbox & 0xff;
e281fcaa 8313 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
a6044e23
JB		 8314 }
8315
8316 /* In units of 100MHz */
8317 dev_priv->max_delay = max_freq;
8318 dev_priv->min_delay = min_freq;
8319 dev_priv->cur_delay = cur_freq;
8320
8fd26859
CW		 8321 /* requires MSI enabled */
8322 I915_WRITE(GEN6_PMIER,
8323 GEN6_PM_MBOX_EVENT |
8324 GEN6_PM_THERMAL_EVENT |
8325 GEN6_PM_RP_DOWN_TIMEOUT |
8326 GEN6_PM_RP_UP_THRESHOLD |
8327 GEN6_PM_RP_DOWN_THRESHOLD |
8328 GEN6_PM_RP_UP_EI_EXPIRED |
8329 GEN6_PM_RP_DOWN_EI_EXPIRED);
4912d041
BW		 8330 spin_lock_irq(&dev_priv->rps_lock);
8331 WARN_ON(dev_priv->pm_iir != 0);
3b8d8d91 8332 I915_WRITE(GEN6_PMIMR, 0);
4912d041 8333 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91
JB		 8334 /* enable all PM interrupts */
8335 I915_WRITE(GEN6_PMINTRMSK, 0);
8fd26859 8336
fcca7926 8337 gen6_gt_force_wake_put(dev_priv);
d1ebd816 8338 mutex_unlock(&dev_priv->dev->struct_mutex);
8fd26859
CW		 8339}
8340
23b2f8bb
JB		 8341void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8342{
8343 int min_freq = 15;
8344 int gpu_freq, ia_freq, max_ia_freq;
8345 int scaling_factor = 180;
8346
8347 max_ia_freq = cpufreq_quick_get_max(0);
8348 /*
8349 * Default to measured freq if none found, PCU will ensure we don't go
8350 * over
8351 */
8352 if (!max_ia_freq)
8353 max_ia_freq = tsc_khz;
8354
8355 /* Convert from kHz to MHz */
8356 max_ia_freq /= 1000;
8357
8358 mutex_lock(&dev_priv->dev->struct_mutex);
8359
8360 /*
8361 * For each potential GPU frequency, load a ring frequency we'd like
8362 * to use for memory access. We do this by specifying the IA frequency
8363 * the PCU should use as a reference to determine the ring frequency.
8364 */
8365 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8366 gpu_freq--) {
8367 int diff = dev_priv->max_delay - gpu_freq;
8368
8369 /*
8370 * For GPU frequencies less than 750MHz, just use the lowest
8371 * ring freq.
8372 */
8373 if (gpu_freq < min_freq)
8374 ia_freq = 800;
8375 else
8376 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8377 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8378
8379 I915_WRITE(GEN6_PCODE_DATA,
8380 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8381 gpu_freq);
8382 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8383 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8384 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8385 GEN6_PCODE_READY) == 0, 10)) {
8386 DRM_ERROR("pcode write of freq table timed out\n");
8387 continue;
8388 }
8389 }
8390
8391 mutex_unlock(&dev_priv->dev->struct_mutex);
8392}
8393
6067aaea
JB		 8394static void ironlake_init_clock_gating(struct drm_device *dev)
8395{
8396 struct drm_i915_private *dev_priv = dev->dev_private;
8397 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8398
8399 /* Required for FBC */
8400 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8401 DPFCRUNIT_CLOCK_GATE_DISABLE |
8402 DPFDUNIT_CLOCK_GATE_DISABLE;
8403 /* Required for CxSR */
8404 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8405
8406 I915_WRITE(PCH_3DCGDIS0,
8407 MARIUNIT_CLOCK_GATE_DISABLE |
8408 SVSMUNIT_CLOCK_GATE_DISABLE);
8409 I915_WRITE(PCH_3DCGDIS1,
8410 VFMUNIT_CLOCK_GATE_DISABLE);
8411
8412 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8413
6067aaea
JB		 8414 /*
8415 * According to the spec the following bits should be set in
8416 * order to enable memory self-refresh
8417 * The bit 22/21 of 0x42004
8418 * The bit 5 of 0x42020
8419 * The bit 15 of 0x45000
8420 */
8421 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8422 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8423 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8424 I915_WRITE(ILK_DSPCLK_GATE,
8425 (I915_READ(ILK_DSPCLK_GATE) |
8426 ILK_DPARB_CLK_GATE));
8427 I915_WRITE(DISP_ARB_CTL,
8428 (I915_READ(DISP_ARB_CTL) |
8429 DISP_FBC_WM_DIS));
8430 I915_WRITE(WM3_LP_ILK, 0);
8431 I915_WRITE(WM2_LP_ILK, 0);
8432 I915_WRITE(WM1_LP_ILK, 0);
8433
8434 /*
8435 * Based on the document from hardware guys the following bits
8436 * should be set unconditionally in order to enable FBC.
8437 * The bit 22 of 0x42000
8438 * The bit 22 of 0x42004
8439 * The bit 7,8,9 of 0x42020.
8440 */
8441 if (IS_IRONLAKE_M(dev)) {
8442 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8443 I915_READ(ILK_DISPLAY_CHICKEN1) |
8444 ILK_FBCQ_DIS);
8445 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8446 I915_READ(ILK_DISPLAY_CHICKEN2) |
8447 ILK_DPARB_GATE);
8448 I915_WRITE(ILK_DSPCLK_GATE,
8449 I915_READ(ILK_DSPCLK_GATE) |
8450 ILK_DPFC_DIS1 |
8451 ILK_DPFC_DIS2 |
8452 ILK_CLK_FBC);
8453 }
8454
8455 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8456 I915_READ(ILK_DISPLAY_CHICKEN2) |
8457 ILK_ELPIN_409_SELECT);
8458 I915_WRITE(_3D_CHICKEN2,
8459 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8460 _3D_CHICKEN2_WM_READ_PIPELINED);
8fd26859
CW		 8461}
8462
6067aaea 8463static void gen6_init_clock_gating(struct drm_device *dev)
652c393a
JB		 8464{
8465 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 8466 int pipe;
6067aaea
JB		 8467 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8468
8469 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
652c393a 8470
6067aaea
JB		 8471 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8472 I915_READ(ILK_DISPLAY_CHICKEN2) |
8473 ILK_ELPIN_409_SELECT);
8956c8bb 8474
6067aaea
JB		 8475 I915_WRITE(WM3_LP_ILK, 0);
8476 I915_WRITE(WM2_LP_ILK, 0);
8477 I915_WRITE(WM1_LP_ILK, 0);
652c393a 8478
406478dc
EA		 8479 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8480 * gating disable must be set. Failure to set it results in
8481 * flickering pixels due to Z write ordering failures after
8482 * some amount of runtime in the Mesa "fire" demo, and Unigine
8483 * Sanctuary and Tropics, and apparently anything else with
8484 * alpha test or pixel discard.
9ca1d10d
EA		 8485 *
8486 * According to the spec, bit 11 (RCCUNIT) must also be set,
8487 * but we didn't debug actual testcases to find it out.
406478dc 8488 */
9ca1d10d
EA		 8489 I915_WRITE(GEN6_UCGCTL2,
8490 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8491 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
406478dc 8492
652c393a 8493 /*
6067aaea
JB		 8494 * According to the spec the following bits should be
8495 * set in order to enable memory self-refresh and fbc:
8496 * The bit21 and bit22 of 0x42000
8497 * The bit21 and bit22 of 0x42004
8498 * The bit5 and bit7 of 0x42020
8499 * The bit14 of 0x70180
8500 * The bit14 of 0x71180
652c393a 8501 */
6067aaea
JB		 8502 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8503 I915_READ(ILK_DISPLAY_CHICKEN1) |
8504 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8505 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8506 I915_READ(ILK_DISPLAY_CHICKEN2) |
8507 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8508 I915_WRITE(ILK_DSPCLK_GATE,
8509 I915_READ(ILK_DSPCLK_GATE) |
8510 ILK_DPARB_CLK_GATE |
8511 ILK_DPFD_CLK_GATE);
8956c8bb 8512
d74362c9 8513 for_each_pipe(pipe) {
6067aaea
JB		 8514 I915_WRITE(DSPCNTR(pipe),
8515 I915_READ(DSPCNTR(pipe)) |
8516 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 8517 intel_flush_display_plane(dev_priv, pipe);
8518 }
6067aaea 8519}
8956c8bb 8520
28963a3e
JB		 8521static void ivybridge_init_clock_gating(struct drm_device *dev)
8522{
8523 struct drm_i915_private *dev_priv = dev->dev_private;
8524 int pipe;
8525 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7f8a8569 8526
28963a3e 8527 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
382b0936 8528
28963a3e
JB		 8529 I915_WRITE(WM3_LP_ILK, 0);
8530 I915_WRITE(WM2_LP_ILK, 0);
8531 I915_WRITE(WM1_LP_ILK, 0);
de6e2eaf 8532
28963a3e 8533 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
67e92af0 8534
116ac8d2
EA		 8535 I915_WRITE(IVB_CHICKEN3,
8536 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8537 CHICKEN3_DGMG_DONE_FIX_DISABLE);
8538
d74362c9 8539 for_each_pipe(pipe) {
28963a3e
JB		 8540 I915_WRITE(DSPCNTR(pipe),
8541 I915_READ(DSPCNTR(pipe)) |
8542 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 8543 intel_flush_display_plane(dev_priv, pipe);
8544 }
28963a3e
JB		 8545}
8546
6067aaea
JB		 8547static void g4x_init_clock_gating(struct drm_device *dev)
8548{
8549 struct drm_i915_private *dev_priv = dev->dev_private;
8550 uint32_t dspclk_gate;
8fd26859 8551
6067aaea
JB		 8552 I915_WRITE(RENCLK_GATE_D1, 0);
8553 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8554 GS_UNIT_CLOCK_GATE_DISABLE |
8555 CL_UNIT_CLOCK_GATE_DISABLE);
8556 I915_WRITE(RAMCLK_GATE_D, 0);
8557 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8558 OVRUNIT_CLOCK_GATE_DISABLE |
8559 OVCUNIT_CLOCK_GATE_DISABLE;
8560 if (IS_GM45(dev))
8561 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8562 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8563}
1398261a 8564
6067aaea
JB		 8565static void crestline_init_clock_gating(struct drm_device *dev)
8566{
8567 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 8568
6067aaea
JB		 8569 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8570 I915_WRITE(RENCLK_GATE_D2, 0);
8571 I915_WRITE(DSPCLK_GATE_D, 0);
8572 I915_WRITE(RAMCLK_GATE_D, 0);
8573 I915_WRITE16(DEUC, 0);
8574}
652c393a 8575
6067aaea
JB		 8576static void broadwater_init_clock_gating(struct drm_device *dev)
8577{
8578 struct drm_i915_private *dev_priv = dev->dev_private;
8579
8580 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8581 I965_RCC_CLOCK_GATE_DISABLE |
8582 I965_RCPB_CLOCK_GATE_DISABLE |
8583 I965_ISC_CLOCK_GATE_DISABLE |
8584 I965_FBC_CLOCK_GATE_DISABLE);
8585 I915_WRITE(RENCLK_GATE_D2, 0);
8586}
8587
8588static void gen3_init_clock_gating(struct drm_device *dev)
8589{
8590 struct drm_i915_private *dev_priv = dev->dev_private;
8591 u32 dstate = I915_READ(D_STATE);
8592
8593 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8594 DSTATE_DOT_CLOCK_GATING;
8595 I915_WRITE(D_STATE, dstate);
8596}
8597
8598static void i85x_init_clock_gating(struct drm_device *dev)
8599{
8600 struct drm_i915_private *dev_priv = dev->dev_private;
8601
8602 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8603}
8604
8605static void i830_init_clock_gating(struct drm_device *dev)
8606{
8607 struct drm_i915_private *dev_priv = dev->dev_private;
8608
8609 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
652c393a
JB		 8610}
8611
645c62a5
JB		 8612static void ibx_init_clock_gating(struct drm_device *dev)
8613{
8614 struct drm_i915_private *dev_priv = dev->dev_private;
8615
8616 /*
8617 * On Ibex Peak and Cougar Point, we need to disable clock
8618 * gating for the panel power sequencer or it will fail to
8619 * start up when no ports are active.
8620 */
8621 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8622}
8623
8624static void cpt_init_clock_gating(struct drm_device *dev)
8625{
8626 struct drm_i915_private *dev_priv = dev->dev_private;
3bcf603f 8627 int pipe;
645c62a5
JB		 8628
8629 /*
8630 * On Ibex Peak and Cougar Point, we need to disable clock
8631 * gating for the panel power sequencer or it will fail to
8632 * start up when no ports are active.
8633 */
8634 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8635 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8636 DPLS_EDP_PPS_FIX_DIS);
3bcf603f
JB		 8637 /* Without this, mode sets may fail silently on FDI */
8638 for_each_pipe(pipe)
8639 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
652c393a
JB		 8640}
8641
ac668088 8642static void ironlake_teardown_rc6(struct drm_device *dev)
0cdab21f
CW		 8643{
8644 struct drm_i915_private *dev_priv = dev->dev_private;
8645
8646 if (dev_priv->renderctx) {
ac668088
CW		 8647 i915_gem_object_unpin(dev_priv->renderctx);
8648 drm_gem_object_unreference(&dev_priv->renderctx->base);
0cdab21f
CW		 8649 dev_priv->renderctx = NULL;
8650 }
8651
8652 if (dev_priv->pwrctx) {
ac668088
CW		 8653 i915_gem_object_unpin(dev_priv->pwrctx);
8654 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8655 dev_priv->pwrctx = NULL;
8656 }
8657}
8658
8659static void ironlake_disable_rc6(struct drm_device *dev)
8660{
8661 struct drm_i915_private *dev_priv = dev->dev_private;
8662
8663 if (I915_READ(PWRCTXA)) {
8664 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8665 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8666 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8667 50);
0cdab21f
CW		 8668
8669 I915_WRITE(PWRCTXA, 0);
8670 POSTING_READ(PWRCTXA);
8671
ac668088
CW		 8672 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8673 POSTING_READ(RSTDBYCTL);
0cdab21f 8674 }
ac668088 8675
99507307 8676 ironlake_teardown_rc6(dev);
0cdab21f
CW		 8677}
8678
ac668088 8679static int ironlake_setup_rc6(struct drm_device *dev)
d5bb081b
JB		 8680{
8681 struct drm_i915_private *dev_priv = dev->dev_private;
8682
ac668088
CW		 8683 if (dev_priv->renderctx == NULL)
8684 dev_priv->renderctx = intel_alloc_context_page(dev);
8685 if (!dev_priv->renderctx)
8686 return -ENOMEM;
8687
8688 if (dev_priv->pwrctx == NULL)
8689 dev_priv->pwrctx = intel_alloc_context_page(dev);
8690 if (!dev_priv->pwrctx) {
8691 ironlake_teardown_rc6(dev);
8692 return -ENOMEM;
8693 }
8694
8695 return 0;
d5bb081b
JB		 8696}
8697
8698void ironlake_enable_rc6(struct drm_device *dev)
8699{
8700 struct drm_i915_private *dev_priv = dev->dev_private;
8701 int ret;
8702
ac668088
CW		 8703 /* rc6 disabled by default due to repeated reports of hanging during
8704 * boot and resume.
8705 */
c0f372b3 8706 if (!intel_enable_rc6(dev))
ac668088
CW		 8707 return;
8708
2c34b850 8709 mutex_lock(&dev->struct_mutex);
ac668088 8710 ret = ironlake_setup_rc6(dev);
2c34b850
BW		 8711 if (ret) {
8712 mutex_unlock(&dev->struct_mutex);
ac668088 8713 return;
2c34b850 8714 }
ac668088 8715
d5bb081b
JB		 8716 /*
8717 * GPU can automatically power down the render unit if given a page
8718 * to save state.
8719 */
8720 ret = BEGIN_LP_RING(6);
8721 if (ret) {
ac668088 8722 ironlake_teardown_rc6(dev);
2c34b850 8723 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8724 return;
8725 }
ac668088 8726
d5bb081b
JB		 8727 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8728 OUT_RING(MI_SET_CONTEXT);
8729 OUT_RING(dev_priv->renderctx->gtt_offset |
8730 MI_MM_SPACE_GTT |
8731 MI_SAVE_EXT_STATE_EN |
8732 MI_RESTORE_EXT_STATE_EN |
8733 MI_RESTORE_INHIBIT);
8734 OUT_RING(MI_SUSPEND_FLUSH);
8735 OUT_RING(MI_NOOP);
8736 OUT_RING(MI_FLUSH);
8737 ADVANCE_LP_RING();
8738
4a246cfc
BW		 8739 /*
8740 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8741 * does an implicit flush, combined with MI_FLUSH above, it should be
8742 * safe to assume that renderctx is valid
8743 */
8744 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8745 if (ret) {
8746 DRM_ERROR("failed to enable ironlake power power savings\n");
8747 ironlake_teardown_rc6(dev);
8748 mutex_unlock(&dev->struct_mutex);
8749 return;
8750 }
8751
d5bb081b
JB		 8752 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8753 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2c34b850 8754 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8755}
8756
645c62a5
JB		 8757void intel_init_clock_gating(struct drm_device *dev)
8758{
8759 struct drm_i915_private *dev_priv = dev->dev_private;
8760
8761 dev_priv->display.init_clock_gating(dev);
8762
8763 if (dev_priv->display.init_pch_clock_gating)
8764 dev_priv->display.init_pch_clock_gating(dev);
8765}
ac668088 8766
e70236a8
JB		 8767/* Set up chip specific display functions */
8768static void intel_init_display(struct drm_device *dev)
8769{
8770 struct drm_i915_private *dev_priv = dev->dev_private;
8771
8772 /* We always want a DPMS function */
f564048e 8773 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 8774 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 8775 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
17638cd6 8776 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8777 } else {
e70236a8 8778 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 8779 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
17638cd6 8780 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8781 }
e70236a8 8782
ee5382ae 8783 if (I915_HAS_FBC(dev)) {
9c04f015 8784 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 8785 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8786 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8787 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8788 } else if (IS_GM45(dev)) {
74dff282
JB		 8789 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8790 dev_priv->display.enable_fbc = g4x_enable_fbc;
8791 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 8792 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 8793 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8794 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8795 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8796 }
74dff282 8797 /* 855GM needs testing */
e70236a8
JB		 8798 }
8799
8800 /* Returns the core display clock speed */
0206e353 8801 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8802 dev_priv->display.get_display_clock_speed =
8803 i945_get_display_clock_speed;
8804 else if (IS_I915G(dev))
8805 dev_priv->display.get_display_clock_speed =
8806 i915_get_display_clock_speed;
f2b115e6 8807 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8808 dev_priv->display.get_display_clock_speed =
8809 i9xx_misc_get_display_clock_speed;
8810 else if (IS_I915GM(dev))
8811 dev_priv->display.get_display_clock_speed =
8812 i915gm_get_display_clock_speed;
8813 else if (IS_I865G(dev))
8814 dev_priv->display.get_display_clock_speed =
8815 i865_get_display_clock_speed;
f0f8a9ce 8816 else if (IS_I85X(dev))
e70236a8
JB		 8817 dev_priv->display.get_display_clock_speed =
8818 i855_get_display_clock_speed;
8819 else /* 852, 830 */
8820 dev_priv->display.get_display_clock_speed =
8821 i830_get_display_clock_speed;
8822
8823 /* For FIFO watermark updates */
7f8a8569 8824 if (HAS_PCH_SPLIT(dev)) {
8d715f00
KP		 8825 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8826 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8827
8828 /* IVB configs may use multi-threaded forcewake */
8829 if (IS_IVYBRIDGE(dev)) {
8830 u32 ecobus;
8831
c7dffff7
KP		 8832 /* A small trick here - if the bios hasn't configured MT forcewake,
8833 * and if the device is in RC6, then force_wake_mt_get will not wake
8834 * the device and the ECOBUS read will return zero. Which will be
8835 * (correctly) interpreted by the test below as MT forcewake being
8836 * disabled.
8837 */
8d715f00
KP		 8838 mutex_lock(&dev->struct_mutex);
8839 __gen6_gt_force_wake_mt_get(dev_priv);
c7dffff7 8840 ecobus = I915_READ_NOTRACE(ECOBUS);
8d715f00
KP		 8841 __gen6_gt_force_wake_mt_put(dev_priv);
8842 mutex_unlock(&dev->struct_mutex);
8843
8844 if (ecobus & FORCEWAKE_MT_ENABLE) {
8845 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8846 dev_priv->display.force_wake_get =
8847 __gen6_gt_force_wake_mt_get;
8848 dev_priv->display.force_wake_put =
8849 __gen6_gt_force_wake_mt_put;
8850 }
8851 }
8852
645c62a5
JB		 8853 if (HAS_PCH_IBX(dev))
8854 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8855 else if (HAS_PCH_CPT(dev))
8856 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8857
f00a3ddf 8858 if (IS_GEN5(dev)) {
7f8a8569
ZW		 8859 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8860 dev_priv->display.update_wm = ironlake_update_wm;
8861 else {
8862 DRM_DEBUG_KMS("Failed to get proper latency. "
8863 "Disable CxSR\n");
8864 dev_priv->display.update_wm = NULL;
1398261a 8865 }
674cf967 8866 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6067aaea 8867 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
e0dac65e 8868 dev_priv->display.write_eld = ironlake_write_eld;
1398261a
YL		 8869 } else if (IS_GEN6(dev)) {
8870 if (SNB_READ_WM0_LATENCY()) {
8871 dev_priv->display.update_wm = sandybridge_update_wm;
b840d907 8872 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
1398261a
YL		 8873 } else {
8874 DRM_DEBUG_KMS("Failed to read display plane latency. "
8875 "Disable CxSR\n");
8876 dev_priv->display.update_wm = NULL;
7f8a8569 8877 }
674cf967 8878 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6067aaea 8879 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
e0dac65e 8880 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8881 } else if (IS_IVYBRIDGE(dev)) {
8882 /* FIXME: detect B0+ stepping and use auto training */
8883 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
fe100d4d
JB		 8884 if (SNB_READ_WM0_LATENCY()) {
8885 dev_priv->display.update_wm = sandybridge_update_wm;
b840d907 8886 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
fe100d4d
JB		 8887 } else {
8888 DRM_DEBUG_KMS("Failed to read display plane latency. "
8889 "Disable CxSR\n");
8890 dev_priv->display.update_wm = NULL;
8891 }
28963a3e 8892 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
e0dac65e 8893 dev_priv->display.write_eld = ironlake_write_eld;
7f8a8569
ZW		 8894 } else
8895 dev_priv->display.update_wm = NULL;
8896 } else if (IS_PINEVIEW(dev)) {
d4294342 8897 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 8898 dev_priv->is_ddr3,
d4294342
ZY		 8899 dev_priv->fsb_freq,
8900 dev_priv->mem_freq)) {
8901 DRM_INFO("failed to find known CxSR latency "
95534263 8902 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 8903 "disabling CxSR\n",
0206e353 8904 (dev_priv->is_ddr3 == 1) ? "3" : "2",
d4294342
ZY		 8905 dev_priv->fsb_freq, dev_priv->mem_freq);
8906 /* Disable CxSR and never update its watermark again */
8907 pineview_disable_cxsr(dev);
8908 dev_priv->display.update_wm = NULL;
8909 } else
8910 dev_priv->display.update_wm = pineview_update_wm;
95e0ee92 8911 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6067aaea 8912 } else if (IS_G4X(dev)) {
e0dac65e 8913 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8914 dev_priv->display.update_wm = g4x_update_wm;
6067aaea
JB		 8915 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8916 } else if (IS_GEN4(dev)) {
e70236a8 8917 dev_priv->display.update_wm = i965_update_wm;
6067aaea
JB		 8918 if (IS_CRESTLINE(dev))
8919 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8920 else if (IS_BROADWATER(dev))
8921 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8922 } else if (IS_GEN3(dev)) {
e70236a8
JB		 8923 dev_priv->display.update_wm = i9xx_update_wm;
8924 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6067aaea
JB		 8925 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8926 } else if (IS_I865G(dev)) {
8927 dev_priv->display.update_wm = i830_update_wm;
8928 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8929 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8f4695ed
AJ		 8930 } else if (IS_I85X(dev)) {
8931 dev_priv->display.update_wm = i9xx_update_wm;
8932 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6067aaea 8933 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
e70236a8 8934 } else {
8f4695ed 8935 dev_priv->display.update_wm = i830_update_wm;
6067aaea 8936 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8f4695ed 8937 if (IS_845G(dev))
e70236a8
JB		 8938 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8939 else
8940 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8 8941 }
8c9f3aaf
JB		 8942
8943 /* Default just returns -ENODEV to indicate unsupported */
8944 dev_priv->display.queue_flip = intel_default_queue_flip;
8945
8946 switch (INTEL_INFO(dev)->gen) {
8947 case 2:
8948 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8949 break;
8950
8951 case 3:
8952 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8953 break;
8954
8955 case 4:
8956 case 5:
8957 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8958 break;
8959
8960 case 6:
8961 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8962 break;
7c9017e5
JB		 8963 case 7:
8964 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8965 break;
8c9f3aaf 8966 }
e70236a8
JB		 8967}
8968
b690e96c
JB		 8969/*
8970 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8971 * resume, or other times. This quirk makes sure that's the case for
8972 * affected systems.
8973 */
0206e353 8974static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8975{
8976 struct drm_i915_private *dev_priv = dev->dev_private;
8977
8978 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8979 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8980}
8981
435793df
KP		 8982/*
8983 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8984 */
8985static void quirk_ssc_force_disable(struct drm_device *dev)
8986{
8987 struct drm_i915_private *dev_priv = dev->dev_private;
8988 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8989}
8990
b690e96c
JB		 8991struct intel_quirk {
8992 int device;
8993 int subsystem_vendor;
8994 int subsystem_device;
8995 void (*hook)(struct drm_device *dev);
8996};
8997
8998struct intel_quirk intel_quirks[] = {
8999 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
9000 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
9001 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9002 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c
JB		 9003
9004 /* Thinkpad R31 needs pipe A force quirk */
9005 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
9006 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9007 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9008
9009 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
9010 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
9011 /* ThinkPad X40 needs pipe A force quirk */
9012
9013 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9014 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9015
9016 /* 855 & before need to leave pipe A & dpll A up */
9017 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
9018 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9019
9020 /* Lenovo U160 cannot use SSC on LVDS */
9021 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9022
9023 /* Sony Vaio Y cannot use SSC on LVDS */
9024 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
b690e96c
JB		 9025};
9026
9027static void intel_init_quirks(struct drm_device *dev)
9028{
9029 struct pci_dev *d = dev->pdev;
9030 int i;
9031
9032 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9033 struct intel_quirk *q = &intel_quirks[i];
9034
9035 if (d->device == q->device &&
9036 (d->subsystem_vendor == q->subsystem_vendor ||
9037 q->subsystem_vendor == PCI_ANY_ID) &&
9038 (d->subsystem_device == q->subsystem_device ||
9039 q->subsystem_device == PCI_ANY_ID))
9040 q->hook(dev);
9041 }
9042}
9043
9cce37f4
JB		 9044/* Disable the VGA plane that we never use */
9045static void i915_disable_vga(struct drm_device *dev)
9046{
9047 struct drm_i915_private *dev_priv = dev->dev_private;
9048 u8 sr1;
9049 u32 vga_reg;
9050
9051 if (HAS_PCH_SPLIT(dev))
9052 vga_reg = CPU_VGACNTRL;
9053 else
9054 vga_reg = VGACNTRL;
9055
9056 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
9057 outb(1, VGA_SR_INDEX);
9058 sr1 = inb(VGA_SR_DATA);
9059 outb(sr1 | 1<<5, VGA_SR_DATA);
9060 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9061 udelay(300);
9062
9063 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9064 POSTING_READ(vga_reg);
9065}
9066
79e53945
JB		 9067void intel_modeset_init(struct drm_device *dev)
9068{
652c393a 9069 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 9070 int i, ret;
79e53945
JB		 9071
9072 drm_mode_config_init(dev);
9073
9074 dev->mode_config.min_width = 0;
9075 dev->mode_config.min_height = 0;
9076
9077 dev->mode_config.funcs = (void *)&intel_mode_funcs;
9078
b690e96c
JB		 9079 intel_init_quirks(dev);
9080
e70236a8
JB		 9081 intel_init_display(dev);
9082
a6c45cf0
CW		 9083 if (IS_GEN2(dev)) {
9084 dev->mode_config.max_width = 2048;
9085 dev->mode_config.max_height = 2048;
9086 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9087 dev->mode_config.max_width = 4096;
9088 dev->mode_config.max_height = 4096;
79e53945 9089 } else {
a6c45cf0
CW		 9090 dev->mode_config.max_width = 8192;
9091 dev->mode_config.max_height = 8192;
79e53945 9092 }
35c3047a 9093 dev->mode_config.fb_base = dev->agp->base;
79e53945 9094
28c97730 9095 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 9096 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 9097
a3524f1b 9098 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 9099 intel_crtc_init(dev, i);
00c2064b
JB		 9100 ret = intel_plane_init(dev, i);
9101 if (ret)
9102 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 9103 }
9104
9cce37f4
JB		 9105 /* Just disable it once at startup */
9106 i915_disable_vga(dev);
79e53945 9107 intel_setup_outputs(dev);
652c393a 9108
645c62a5 9109 intel_init_clock_gating(dev);
9cce37f4 9110
7648fa99 9111 if (IS_IRONLAKE_M(dev)) {
f97108d1 9112 ironlake_enable_drps(dev);
7648fa99
JB		 9113 intel_init_emon(dev);
9114 }
f97108d1 9115
1c70c0ce 9116 if (IS_GEN6(dev) || IS_GEN7(dev)) {
3b8d8d91 9117 gen6_enable_rps(dev_priv);
23b2f8bb
JB		 9118 gen6_update_ring_freq(dev_priv);
9119 }
3b8d8d91 9120
652c393a
JB		 9121 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9122 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9123 (unsigned long)dev);
2c7111db
CW		 9124}
9125
9126void intel_modeset_gem_init(struct drm_device *dev)
9127{
9128 if (IS_IRONLAKE_M(dev))
9129 ironlake_enable_rc6(dev);
02e792fb
DV		 9130
9131 intel_setup_overlay(dev);
79e53945
JB		 9132}
9133
9134void intel_modeset_cleanup(struct drm_device *dev)
9135{
652c393a
JB		 9136 struct drm_i915_private *dev_priv = dev->dev_private;
9137 struct drm_crtc *crtc;
9138 struct intel_crtc *intel_crtc;
9139
f87ea761 9140 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9141 mutex_lock(&dev->struct_mutex);
9142
723bfd70
JB		 9143 intel_unregister_dsm_handler();
9144
9145
652c393a
JB		 9146 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9147 /* Skip inactive CRTCs */
9148 if (!crtc->fb)
9149 continue;
9150
9151 intel_crtc = to_intel_crtc(crtc);
3dec0095 9152 intel_increase_pllclock(crtc);
652c393a
JB		 9153 }
9154
973d04f9 9155 intel_disable_fbc(dev);
e70236a8 9156
f97108d1
JB		 9157 if (IS_IRONLAKE_M(dev))
9158 ironlake_disable_drps(dev);
1c70c0ce 9159 if (IS_GEN6(dev) || IS_GEN7(dev))
3b8d8d91 9160 gen6_disable_rps(dev);
f97108d1 9161
d5bb081b
JB		 9162 if (IS_IRONLAKE_M(dev))
9163 ironlake_disable_rc6(dev);
0cdab21f 9164
69341a5e
KH		 9165 mutex_unlock(&dev->struct_mutex);
9166
6c0d9350
DV		 9167 /* Disable the irq before mode object teardown, for the irq might
9168 * enqueue unpin/hotplug work. */
9169 drm_irq_uninstall(dev);
9170 cancel_work_sync(&dev_priv->hotplug_work);
6fdd4d98 9171 cancel_work_sync(&dev_priv->rps_work);
6c0d9350 9172
1630fe75
CW		 9173 /* flush any delayed tasks or pending work */
9174 flush_scheduled_work();
9175
3dec0095
DV		 9176 /* Shut off idle work before the crtcs get freed. */
9177 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9178 intel_crtc = to_intel_crtc(crtc);
9179 del_timer_sync(&intel_crtc->idle_timer);
9180 }
9181 del_timer_sync(&dev_priv->idle_timer);
9182 cancel_work_sync(&dev_priv->idle_work);
9183
79e53945
JB		 9184 drm_mode_config_cleanup(dev);
9185}
9186
f1c79df3
ZW		 9187/*
9188 * Return which encoder is currently attached for connector.
9189 */
df0e9248 9190struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9191{
df0e9248
CW		 9192 return &intel_attached_encoder(connector)->base;
9193}
f1c79df3 9194
df0e9248
CW		 9195void intel_connector_attach_encoder(struct intel_connector *connector,
9196 struct intel_encoder *encoder)
9197{
9198 connector->encoder = encoder;
9199 drm_mode_connector_attach_encoder(&connector->base,
9200 &encoder->base);
79e53945 9201}
28d52043
DA		 9202
9203/*
9204 * set vga decode state - true == enable VGA decode
9205 */
9206int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9207{
9208 struct drm_i915_private *dev_priv = dev->dev_private;
9209 u16 gmch_ctrl;
9210
9211 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9212 if (state)
9213 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9214 else
9215 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9216 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9217 return 0;
9218}
c4a1d9e4
CW		 9219
9220#ifdef CONFIG_DEBUG_FS
9221#include <linux/seq_file.h>
9222
9223struct intel_display_error_state {
9224 struct intel_cursor_error_state {
9225 u32 control;
9226 u32 position;
9227 u32 base;
9228 u32 size;
9229 } cursor[2];
9230
9231 struct intel_pipe_error_state {
9232 u32 conf;
9233 u32 source;
9234
9235 u32 htotal;
9236 u32 hblank;
9237 u32 hsync;
9238 u32 vtotal;
9239 u32 vblank;
9240 u32 vsync;
9241 } pipe[2];
9242
9243 struct intel_plane_error_state {
9244 u32 control;
9245 u32 stride;
9246 u32 size;
9247 u32 pos;
9248 u32 addr;
9249 u32 surface;
9250 u32 tile_offset;
9251 } plane[2];
9252};
9253
9254struct intel_display_error_state *
9255intel_display_capture_error_state(struct drm_device *dev)
9256{
0206e353 9257 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9258 struct intel_display_error_state *error;
9259 int i;
9260
9261 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9262 if (error == NULL)
9263 return NULL;
9264
9265 for (i = 0; i < 2; i++) {
9266 error->cursor[i].control = I915_READ(CURCNTR(i));
9267 error->cursor[i].position = I915_READ(CURPOS(i));
9268 error->cursor[i].base = I915_READ(CURBASE(i));
9269
9270 error->plane[i].control = I915_READ(DSPCNTR(i));
9271 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9272 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9273 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9274 error->plane[i].addr = I915_READ(DSPADDR(i));
9275 if (INTEL_INFO(dev)->gen >= 4) {
9276 error->plane[i].surface = I915_READ(DSPSURF(i));
9277 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9278 }
9279
9280 error->pipe[i].conf = I915_READ(PIPECONF(i));
9281 error->pipe[i].source = I915_READ(PIPESRC(i));
9282 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9283 error->pipe[i].hblank = I915_READ(HBLANK(i));
9284 error->pipe[i].hsync = I915_READ(HSYNC(i));
9285 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9286 error->pipe[i].vblank = I915_READ(VBLANK(i));
9287 error->pipe[i].vsync = I915_READ(VSYNC(i));
9288 }
9289
9290 return error;
9291}
9292
9293void
9294intel_display_print_error_state(struct seq_file *m,
9295 struct drm_device *dev,
9296 struct intel_display_error_state *error)
9297{
9298 int i;
9299
9300 for (i = 0; i < 2; i++) {
9301 seq_printf(m, "Pipe [%d]:\n", i);
9302 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9303 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9304 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9305 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9306 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9307 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9308 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9309 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9310
9311 seq_printf(m, "Plane [%d]:\n", i);
9312 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9313 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9314 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9315 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9316 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9317 if (INTEL_INFO(dev)->gen >= 4) {
9318 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9319 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9320 }
9321
9322 seq_printf(m, "Cursor [%d]:\n", i);
9323 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9324 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9325 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9326 }
9327}
9328#endif
Linux kernel - Deliverables
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