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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
21 | * DEALINGS IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eric Anholt <eric@anholt.net> | |
25 | */ | |
26 | ||
618563e3 | 27 | #include <linux/dmi.h> |
c1c7af60 JB |
28 | #include <linux/module.h> |
29 | #include <linux/input.h> | |
79e53945 | 30 | #include <linux/i2c.h> |
7662c8bd | 31 | #include <linux/kernel.h> |
5a0e3ad6 | 32 | #include <linux/slab.h> |
9cce37f4 | 33 | #include <linux/vgaarb.h> |
e0dac65e | 34 | #include <drm/drm_edid.h> |
760285e7 | 35 | #include <drm/drmP.h> |
79e53945 | 36 | #include "intel_drv.h" |
760285e7 | 37 | #include <drm/i915_drm.h> |
79e53945 | 38 | #include "i915_drv.h" |
e5510fac | 39 | #include "i915_trace.h" |
760285e7 DH |
40 | #include <drm/drm_dp_helper.h> |
41 | #include <drm/drm_crtc_helper.h> | |
465c120c MR |
42 | #include <drm/drm_plane_helper.h> |
43 | #include <drm/drm_rect.h> | |
c0f372b3 | 44 | #include <linux/dma_remapping.h> |
79e53945 | 45 | |
465c120c MR |
46 | /* Primary plane formats supported by all gen */ |
47 | #define COMMON_PRIMARY_FORMATS \ | |
48 | DRM_FORMAT_C8, \ | |
49 | DRM_FORMAT_RGB565, \ | |
50 | DRM_FORMAT_XRGB8888, \ | |
51 | DRM_FORMAT_ARGB8888 | |
52 | ||
53 | /* Primary plane formats for gen <= 3 */ | |
54 | static const uint32_t intel_primary_formats_gen2[] = { | |
55 | COMMON_PRIMARY_FORMATS, | |
56 | DRM_FORMAT_XRGB1555, | |
57 | DRM_FORMAT_ARGB1555, | |
58 | }; | |
59 | ||
60 | /* Primary plane formats for gen >= 4 */ | |
61 | static const uint32_t intel_primary_formats_gen4[] = { | |
62 | COMMON_PRIMARY_FORMATS, \ | |
63 | DRM_FORMAT_XBGR8888, | |
64 | DRM_FORMAT_ABGR8888, | |
65 | DRM_FORMAT_XRGB2101010, | |
66 | DRM_FORMAT_ARGB2101010, | |
67 | DRM_FORMAT_XBGR2101010, | |
68 | DRM_FORMAT_ABGR2101010, | |
69 | }; | |
70 | ||
3d7d6510 MR |
71 | /* Cursor formats */ |
72 | static const uint32_t intel_cursor_formats[] = { | |
73 | DRM_FORMAT_ARGB8888, | |
74 | }; | |
75 | ||
ef9348c8 | 76 | #define DIV_ROUND_CLOSEST_ULL(ll, d) \ |
465c120c | 77 | ({ unsigned long long _tmp = (ll)+(d)/2; do_div(_tmp, d); _tmp; }) |
ef9348c8 | 78 | |
cc36513c DV |
79 | static void intel_increase_pllclock(struct drm_device *dev, |
80 | enum pipe pipe); | |
6b383a7f | 81 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on); |
79e53945 | 82 | |
f1f644dc JB |
83 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
84 | struct intel_crtc_config *pipe_config); | |
18442d08 VS |
85 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
86 | struct intel_crtc_config *pipe_config); | |
f1f644dc | 87 | |
e7457a9a DL |
88 | static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode, |
89 | int x, int y, struct drm_framebuffer *old_fb); | |
eb1bfe80 JB |
90 | static int intel_framebuffer_init(struct drm_device *dev, |
91 | struct intel_framebuffer *ifb, | |
92 | struct drm_mode_fb_cmd2 *mode_cmd, | |
93 | struct drm_i915_gem_object *obj); | |
5b18e57c DV |
94 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); |
95 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); | |
29407aab | 96 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, |
f769cd24 VK |
97 | struct intel_link_m_n *m_n, |
98 | struct intel_link_m_n *m2_n2); | |
29407aab | 99 | static void ironlake_set_pipeconf(struct drm_crtc *crtc); |
229fca97 DV |
100 | static void haswell_set_pipeconf(struct drm_crtc *crtc); |
101 | static void intel_set_pipe_csc(struct drm_crtc *crtc); | |
bdd4b6a6 | 102 | static void vlv_prepare_pll(struct intel_crtc *crtc); |
1ae0d137 | 103 | static void chv_prepare_pll(struct intel_crtc *crtc); |
e7457a9a | 104 | |
0e32b39c DA |
105 | static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe) |
106 | { | |
107 | if (!connector->mst_port) | |
108 | return connector->encoder; | |
109 | else | |
110 | return &connector->mst_port->mst_encoders[pipe]->base; | |
111 | } | |
112 | ||
79e53945 | 113 | typedef struct { |
0206e353 | 114 | int min, max; |
79e53945 JB |
115 | } intel_range_t; |
116 | ||
117 | typedef struct { | |
0206e353 AJ |
118 | int dot_limit; |
119 | int p2_slow, p2_fast; | |
79e53945 JB |
120 | } intel_p2_t; |
121 | ||
d4906093 ML |
122 | typedef struct intel_limit intel_limit_t; |
123 | struct intel_limit { | |
0206e353 AJ |
124 | intel_range_t dot, vco, n, m, m1, m2, p, p1; |
125 | intel_p2_t p2; | |
d4906093 | 126 | }; |
79e53945 | 127 | |
d2acd215 DV |
128 | int |
129 | intel_pch_rawclk(struct drm_device *dev) | |
130 | { | |
131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
132 | ||
133 | WARN_ON(!HAS_PCH_SPLIT(dev)); | |
134 | ||
135 | return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK; | |
136 | } | |
137 | ||
021357ac CW |
138 | static inline u32 /* units of 100MHz */ |
139 | intel_fdi_link_freq(struct drm_device *dev) | |
140 | { | |
8b99e68c CW |
141 | if (IS_GEN5(dev)) { |
142 | struct drm_i915_private *dev_priv = dev->dev_private; | |
143 | return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2; | |
144 | } else | |
145 | return 27; | |
021357ac CW |
146 | } |
147 | ||
5d536e28 | 148 | static const intel_limit_t intel_limits_i8xx_dac = { |
0206e353 | 149 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 150 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 151 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
152 | .m = { .min = 96, .max = 140 }, |
153 | .m1 = { .min = 18, .max = 26 }, | |
154 | .m2 = { .min = 6, .max = 16 }, | |
155 | .p = { .min = 4, .max = 128 }, | |
156 | .p1 = { .min = 2, .max = 33 }, | |
273e27ca EA |
157 | .p2 = { .dot_limit = 165000, |
158 | .p2_slow = 4, .p2_fast = 2 }, | |
e4b36699 KP |
159 | }; |
160 | ||
5d536e28 DV |
161 | static const intel_limit_t intel_limits_i8xx_dvo = { |
162 | .dot = { .min = 25000, .max = 350000 }, | |
9c333719 | 163 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 164 | .n = { .min = 2, .max = 16 }, |
5d536e28 DV |
165 | .m = { .min = 96, .max = 140 }, |
166 | .m1 = { .min = 18, .max = 26 }, | |
167 | .m2 = { .min = 6, .max = 16 }, | |
168 | .p = { .min = 4, .max = 128 }, | |
169 | .p1 = { .min = 2, .max = 33 }, | |
170 | .p2 = { .dot_limit = 165000, | |
171 | .p2_slow = 4, .p2_fast = 4 }, | |
172 | }; | |
173 | ||
e4b36699 | 174 | static const intel_limit_t intel_limits_i8xx_lvds = { |
0206e353 | 175 | .dot = { .min = 25000, .max = 350000 }, |
9c333719 | 176 | .vco = { .min = 908000, .max = 1512000 }, |
91dbe5fb | 177 | .n = { .min = 2, .max = 16 }, |
0206e353 AJ |
178 | .m = { .min = 96, .max = 140 }, |
179 | .m1 = { .min = 18, .max = 26 }, | |
180 | .m2 = { .min = 6, .max = 16 }, | |
181 | .p = { .min = 4, .max = 128 }, | |
182 | .p1 = { .min = 1, .max = 6 }, | |
273e27ca EA |
183 | .p2 = { .dot_limit = 165000, |
184 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 | 185 | }; |
273e27ca | 186 | |
e4b36699 | 187 | static const intel_limit_t intel_limits_i9xx_sdvo = { |
0206e353 AJ |
188 | .dot = { .min = 20000, .max = 400000 }, |
189 | .vco = { .min = 1400000, .max = 2800000 }, | |
190 | .n = { .min = 1, .max = 6 }, | |
191 | .m = { .min = 70, .max = 120 }, | |
4f7dfb67 PJ |
192 | .m1 = { .min = 8, .max = 18 }, |
193 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
194 | .p = { .min = 5, .max = 80 }, |
195 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
196 | .p2 = { .dot_limit = 200000, |
197 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
198 | }; |
199 | ||
200 | static const intel_limit_t intel_limits_i9xx_lvds = { | |
0206e353 AJ |
201 | .dot = { .min = 20000, .max = 400000 }, |
202 | .vco = { .min = 1400000, .max = 2800000 }, | |
203 | .n = { .min = 1, .max = 6 }, | |
204 | .m = { .min = 70, .max = 120 }, | |
53a7d2d1 PJ |
205 | .m1 = { .min = 8, .max = 18 }, |
206 | .m2 = { .min = 3, .max = 7 }, | |
0206e353 AJ |
207 | .p = { .min = 7, .max = 98 }, |
208 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
209 | .p2 = { .dot_limit = 112000, |
210 | .p2_slow = 14, .p2_fast = 7 }, | |
e4b36699 KP |
211 | }; |
212 | ||
273e27ca | 213 | |
e4b36699 | 214 | static const intel_limit_t intel_limits_g4x_sdvo = { |
273e27ca EA |
215 | .dot = { .min = 25000, .max = 270000 }, |
216 | .vco = { .min = 1750000, .max = 3500000}, | |
217 | .n = { .min = 1, .max = 4 }, | |
218 | .m = { .min = 104, .max = 138 }, | |
219 | .m1 = { .min = 17, .max = 23 }, | |
220 | .m2 = { .min = 5, .max = 11 }, | |
221 | .p = { .min = 10, .max = 30 }, | |
222 | .p1 = { .min = 1, .max = 3}, | |
223 | .p2 = { .dot_limit = 270000, | |
224 | .p2_slow = 10, | |
225 | .p2_fast = 10 | |
044c7c41 | 226 | }, |
e4b36699 KP |
227 | }; |
228 | ||
229 | static const intel_limit_t intel_limits_g4x_hdmi = { | |
273e27ca EA |
230 | .dot = { .min = 22000, .max = 400000 }, |
231 | .vco = { .min = 1750000, .max = 3500000}, | |
232 | .n = { .min = 1, .max = 4 }, | |
233 | .m = { .min = 104, .max = 138 }, | |
234 | .m1 = { .min = 16, .max = 23 }, | |
235 | .m2 = { .min = 5, .max = 11 }, | |
236 | .p = { .min = 5, .max = 80 }, | |
237 | .p1 = { .min = 1, .max = 8}, | |
238 | .p2 = { .dot_limit = 165000, | |
239 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
240 | }; |
241 | ||
242 | static const intel_limit_t intel_limits_g4x_single_channel_lvds = { | |
273e27ca EA |
243 | .dot = { .min = 20000, .max = 115000 }, |
244 | .vco = { .min = 1750000, .max = 3500000 }, | |
245 | .n = { .min = 1, .max = 3 }, | |
246 | .m = { .min = 104, .max = 138 }, | |
247 | .m1 = { .min = 17, .max = 23 }, | |
248 | .m2 = { .min = 5, .max = 11 }, | |
249 | .p = { .min = 28, .max = 112 }, | |
250 | .p1 = { .min = 2, .max = 8 }, | |
251 | .p2 = { .dot_limit = 0, | |
252 | .p2_slow = 14, .p2_fast = 14 | |
044c7c41 | 253 | }, |
e4b36699 KP |
254 | }; |
255 | ||
256 | static const intel_limit_t intel_limits_g4x_dual_channel_lvds = { | |
273e27ca EA |
257 | .dot = { .min = 80000, .max = 224000 }, |
258 | .vco = { .min = 1750000, .max = 3500000 }, | |
259 | .n = { .min = 1, .max = 3 }, | |
260 | .m = { .min = 104, .max = 138 }, | |
261 | .m1 = { .min = 17, .max = 23 }, | |
262 | .m2 = { .min = 5, .max = 11 }, | |
263 | .p = { .min = 14, .max = 42 }, | |
264 | .p1 = { .min = 2, .max = 6 }, | |
265 | .p2 = { .dot_limit = 0, | |
266 | .p2_slow = 7, .p2_fast = 7 | |
044c7c41 | 267 | }, |
e4b36699 KP |
268 | }; |
269 | ||
f2b115e6 | 270 | static const intel_limit_t intel_limits_pineview_sdvo = { |
0206e353 AJ |
271 | .dot = { .min = 20000, .max = 400000}, |
272 | .vco = { .min = 1700000, .max = 3500000 }, | |
273e27ca | 273 | /* Pineview's Ncounter is a ring counter */ |
0206e353 AJ |
274 | .n = { .min = 3, .max = 6 }, |
275 | .m = { .min = 2, .max = 256 }, | |
273e27ca | 276 | /* Pineview only has one combined m divider, which we treat as m2. */ |
0206e353 AJ |
277 | .m1 = { .min = 0, .max = 0 }, |
278 | .m2 = { .min = 0, .max = 254 }, | |
279 | .p = { .min = 5, .max = 80 }, | |
280 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
281 | .p2 = { .dot_limit = 200000, |
282 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
283 | }; |
284 | ||
f2b115e6 | 285 | static const intel_limit_t intel_limits_pineview_lvds = { |
0206e353 AJ |
286 | .dot = { .min = 20000, .max = 400000 }, |
287 | .vco = { .min = 1700000, .max = 3500000 }, | |
288 | .n = { .min = 3, .max = 6 }, | |
289 | .m = { .min = 2, .max = 256 }, | |
290 | .m1 = { .min = 0, .max = 0 }, | |
291 | .m2 = { .min = 0, .max = 254 }, | |
292 | .p = { .min = 7, .max = 112 }, | |
293 | .p1 = { .min = 1, .max = 8 }, | |
273e27ca EA |
294 | .p2 = { .dot_limit = 112000, |
295 | .p2_slow = 14, .p2_fast = 14 }, | |
e4b36699 KP |
296 | }; |
297 | ||
273e27ca EA |
298 | /* Ironlake / Sandybridge |
299 | * | |
300 | * We calculate clock using (register_value + 2) for N/M1/M2, so here | |
301 | * the range value for them is (actual_value - 2). | |
302 | */ | |
b91ad0ec | 303 | static const intel_limit_t intel_limits_ironlake_dac = { |
273e27ca EA |
304 | .dot = { .min = 25000, .max = 350000 }, |
305 | .vco = { .min = 1760000, .max = 3510000 }, | |
306 | .n = { .min = 1, .max = 5 }, | |
307 | .m = { .min = 79, .max = 127 }, | |
308 | .m1 = { .min = 12, .max = 22 }, | |
309 | .m2 = { .min = 5, .max = 9 }, | |
310 | .p = { .min = 5, .max = 80 }, | |
311 | .p1 = { .min = 1, .max = 8 }, | |
312 | .p2 = { .dot_limit = 225000, | |
313 | .p2_slow = 10, .p2_fast = 5 }, | |
e4b36699 KP |
314 | }; |
315 | ||
b91ad0ec | 316 | static const intel_limit_t intel_limits_ironlake_single_lvds = { |
273e27ca EA |
317 | .dot = { .min = 25000, .max = 350000 }, |
318 | .vco = { .min = 1760000, .max = 3510000 }, | |
319 | .n = { .min = 1, .max = 3 }, | |
320 | .m = { .min = 79, .max = 118 }, | |
321 | .m1 = { .min = 12, .max = 22 }, | |
322 | .m2 = { .min = 5, .max = 9 }, | |
323 | .p = { .min = 28, .max = 112 }, | |
324 | .p1 = { .min = 2, .max = 8 }, | |
325 | .p2 = { .dot_limit = 225000, | |
326 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
327 | }; |
328 | ||
329 | static const intel_limit_t intel_limits_ironlake_dual_lvds = { | |
273e27ca EA |
330 | .dot = { .min = 25000, .max = 350000 }, |
331 | .vco = { .min = 1760000, .max = 3510000 }, | |
332 | .n = { .min = 1, .max = 3 }, | |
333 | .m = { .min = 79, .max = 127 }, | |
334 | .m1 = { .min = 12, .max = 22 }, | |
335 | .m2 = { .min = 5, .max = 9 }, | |
336 | .p = { .min = 14, .max = 56 }, | |
337 | .p1 = { .min = 2, .max = 8 }, | |
338 | .p2 = { .dot_limit = 225000, | |
339 | .p2_slow = 7, .p2_fast = 7 }, | |
b91ad0ec ZW |
340 | }; |
341 | ||
273e27ca | 342 | /* LVDS 100mhz refclk limits. */ |
b91ad0ec | 343 | static const intel_limit_t intel_limits_ironlake_single_lvds_100m = { |
273e27ca EA |
344 | .dot = { .min = 25000, .max = 350000 }, |
345 | .vco = { .min = 1760000, .max = 3510000 }, | |
346 | .n = { .min = 1, .max = 2 }, | |
347 | .m = { .min = 79, .max = 126 }, | |
348 | .m1 = { .min = 12, .max = 22 }, | |
349 | .m2 = { .min = 5, .max = 9 }, | |
350 | .p = { .min = 28, .max = 112 }, | |
0206e353 | 351 | .p1 = { .min = 2, .max = 8 }, |
273e27ca EA |
352 | .p2 = { .dot_limit = 225000, |
353 | .p2_slow = 14, .p2_fast = 14 }, | |
b91ad0ec ZW |
354 | }; |
355 | ||
356 | static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = { | |
273e27ca EA |
357 | .dot = { .min = 25000, .max = 350000 }, |
358 | .vco = { .min = 1760000, .max = 3510000 }, | |
359 | .n = { .min = 1, .max = 3 }, | |
360 | .m = { .min = 79, .max = 126 }, | |
361 | .m1 = { .min = 12, .max = 22 }, | |
362 | .m2 = { .min = 5, .max = 9 }, | |
363 | .p = { .min = 14, .max = 42 }, | |
0206e353 | 364 | .p1 = { .min = 2, .max = 6 }, |
273e27ca EA |
365 | .p2 = { .dot_limit = 225000, |
366 | .p2_slow = 7, .p2_fast = 7 }, | |
4547668a ZY |
367 | }; |
368 | ||
dc730512 | 369 | static const intel_limit_t intel_limits_vlv = { |
f01b7962 VS |
370 | /* |
371 | * These are the data rate limits (measured in fast clocks) | |
372 | * since those are the strictest limits we have. The fast | |
373 | * clock and actual rate limits are more relaxed, so checking | |
374 | * them would make no difference. | |
375 | */ | |
376 | .dot = { .min = 25000 * 5, .max = 270000 * 5 }, | |
75e53986 | 377 | .vco = { .min = 4000000, .max = 6000000 }, |
a0c4da24 | 378 | .n = { .min = 1, .max = 7 }, |
a0c4da24 JB |
379 | .m1 = { .min = 2, .max = 3 }, |
380 | .m2 = { .min = 11, .max = 156 }, | |
b99ab663 | 381 | .p1 = { .min = 2, .max = 3 }, |
5fdc9c49 | 382 | .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ |
a0c4da24 JB |
383 | }; |
384 | ||
ef9348c8 CML |
385 | static const intel_limit_t intel_limits_chv = { |
386 | /* | |
387 | * These are the data rate limits (measured in fast clocks) | |
388 | * since those are the strictest limits we have. The fast | |
389 | * clock and actual rate limits are more relaxed, so checking | |
390 | * them would make no difference. | |
391 | */ | |
392 | .dot = { .min = 25000 * 5, .max = 540000 * 5}, | |
393 | .vco = { .min = 4860000, .max = 6700000 }, | |
394 | .n = { .min = 1, .max = 1 }, | |
395 | .m1 = { .min = 2, .max = 2 }, | |
396 | .m2 = { .min = 24 << 22, .max = 175 << 22 }, | |
397 | .p1 = { .min = 2, .max = 4 }, | |
398 | .p2 = { .p2_slow = 1, .p2_fast = 14 }, | |
399 | }; | |
400 | ||
6b4bf1c4 VS |
401 | static void vlv_clock(int refclk, intel_clock_t *clock) |
402 | { | |
403 | clock->m = clock->m1 * clock->m2; | |
404 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
405 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
406 | return; | |
fb03ac01 VS |
407 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
408 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
6b4bf1c4 VS |
409 | } |
410 | ||
e0638cdf PZ |
411 | /** |
412 | * Returns whether any output on the specified pipe is of the specified type | |
413 | */ | |
414 | static bool intel_pipe_has_type(struct drm_crtc *crtc, int type) | |
415 | { | |
416 | struct drm_device *dev = crtc->dev; | |
417 | struct intel_encoder *encoder; | |
418 | ||
419 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
420 | if (encoder->type == type) | |
421 | return true; | |
422 | ||
423 | return false; | |
424 | } | |
425 | ||
1b894b59 CW |
426 | static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc, |
427 | int refclk) | |
2c07245f | 428 | { |
b91ad0ec | 429 | struct drm_device *dev = crtc->dev; |
2c07245f | 430 | const intel_limit_t *limit; |
b91ad0ec ZW |
431 | |
432 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 433 | if (intel_is_dual_link_lvds(dev)) { |
1b894b59 | 434 | if (refclk == 100000) |
b91ad0ec ZW |
435 | limit = &intel_limits_ironlake_dual_lvds_100m; |
436 | else | |
437 | limit = &intel_limits_ironlake_dual_lvds; | |
438 | } else { | |
1b894b59 | 439 | if (refclk == 100000) |
b91ad0ec ZW |
440 | limit = &intel_limits_ironlake_single_lvds_100m; |
441 | else | |
442 | limit = &intel_limits_ironlake_single_lvds; | |
443 | } | |
c6bb3538 | 444 | } else |
b91ad0ec | 445 | limit = &intel_limits_ironlake_dac; |
2c07245f ZW |
446 | |
447 | return limit; | |
448 | } | |
449 | ||
044c7c41 ML |
450 | static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc) |
451 | { | |
452 | struct drm_device *dev = crtc->dev; | |
044c7c41 ML |
453 | const intel_limit_t *limit; |
454 | ||
455 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 456 | if (intel_is_dual_link_lvds(dev)) |
e4b36699 | 457 | limit = &intel_limits_g4x_dual_channel_lvds; |
044c7c41 | 458 | else |
e4b36699 | 459 | limit = &intel_limits_g4x_single_channel_lvds; |
044c7c41 ML |
460 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) || |
461 | intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) { | |
e4b36699 | 462 | limit = &intel_limits_g4x_hdmi; |
044c7c41 | 463 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) { |
e4b36699 | 464 | limit = &intel_limits_g4x_sdvo; |
044c7c41 | 465 | } else /* The option is for other outputs */ |
e4b36699 | 466 | limit = &intel_limits_i9xx_sdvo; |
044c7c41 ML |
467 | |
468 | return limit; | |
469 | } | |
470 | ||
1b894b59 | 471 | static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk) |
79e53945 JB |
472 | { |
473 | struct drm_device *dev = crtc->dev; | |
474 | const intel_limit_t *limit; | |
475 | ||
bad720ff | 476 | if (HAS_PCH_SPLIT(dev)) |
1b894b59 | 477 | limit = intel_ironlake_limit(crtc, refclk); |
2c07245f | 478 | else if (IS_G4X(dev)) { |
044c7c41 | 479 | limit = intel_g4x_limit(crtc); |
f2b115e6 | 480 | } else if (IS_PINEVIEW(dev)) { |
2177832f | 481 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) |
f2b115e6 | 482 | limit = &intel_limits_pineview_lvds; |
2177832f | 483 | else |
f2b115e6 | 484 | limit = &intel_limits_pineview_sdvo; |
ef9348c8 CML |
485 | } else if (IS_CHERRYVIEW(dev)) { |
486 | limit = &intel_limits_chv; | |
a0c4da24 | 487 | } else if (IS_VALLEYVIEW(dev)) { |
dc730512 | 488 | limit = &intel_limits_vlv; |
a6c45cf0 CW |
489 | } else if (!IS_GEN2(dev)) { |
490 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
491 | limit = &intel_limits_i9xx_lvds; | |
492 | else | |
493 | limit = &intel_limits_i9xx_sdvo; | |
79e53945 JB |
494 | } else { |
495 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) | |
e4b36699 | 496 | limit = &intel_limits_i8xx_lvds; |
5d536e28 | 497 | else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO)) |
e4b36699 | 498 | limit = &intel_limits_i8xx_dvo; |
5d536e28 DV |
499 | else |
500 | limit = &intel_limits_i8xx_dac; | |
79e53945 JB |
501 | } |
502 | return limit; | |
503 | } | |
504 | ||
f2b115e6 AJ |
505 | /* m1 is reserved as 0 in Pineview, n is a ring counter */ |
506 | static void pineview_clock(int refclk, intel_clock_t *clock) | |
79e53945 | 507 | { |
2177832f SL |
508 | clock->m = clock->m2 + 2; |
509 | clock->p = clock->p1 * clock->p2; | |
ed5ca77e VS |
510 | if (WARN_ON(clock->n == 0 || clock->p == 0)) |
511 | return; | |
fb03ac01 VS |
512 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); |
513 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
2177832f SL |
514 | } |
515 | ||
7429e9d4 DV |
516 | static uint32_t i9xx_dpll_compute_m(struct dpll *dpll) |
517 | { | |
518 | return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); | |
519 | } | |
520 | ||
ac58c3f0 | 521 | static void i9xx_clock(int refclk, intel_clock_t *clock) |
2177832f | 522 | { |
7429e9d4 | 523 | clock->m = i9xx_dpll_compute_m(clock); |
79e53945 | 524 | clock->p = clock->p1 * clock->p2; |
ed5ca77e VS |
525 | if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) |
526 | return; | |
fb03ac01 VS |
527 | clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); |
528 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
79e53945 JB |
529 | } |
530 | ||
ef9348c8 CML |
531 | static void chv_clock(int refclk, intel_clock_t *clock) |
532 | { | |
533 | clock->m = clock->m1 * clock->m2; | |
534 | clock->p = clock->p1 * clock->p2; | |
535 | if (WARN_ON(clock->n == 0 || clock->p == 0)) | |
536 | return; | |
537 | clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m, | |
538 | clock->n << 22); | |
539 | clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); | |
540 | } | |
541 | ||
7c04d1d9 | 542 | #define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0) |
79e53945 JB |
543 | /** |
544 | * Returns whether the given set of divisors are valid for a given refclk with | |
545 | * the given connectors. | |
546 | */ | |
547 | ||
1b894b59 CW |
548 | static bool intel_PLL_is_valid(struct drm_device *dev, |
549 | const intel_limit_t *limit, | |
550 | const intel_clock_t *clock) | |
79e53945 | 551 | { |
f01b7962 VS |
552 | if (clock->n < limit->n.min || limit->n.max < clock->n) |
553 | INTELPllInvalid("n out of range\n"); | |
79e53945 | 554 | if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) |
0206e353 | 555 | INTELPllInvalid("p1 out of range\n"); |
79e53945 | 556 | if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) |
0206e353 | 557 | INTELPllInvalid("m2 out of range\n"); |
79e53945 | 558 | if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) |
0206e353 | 559 | INTELPllInvalid("m1 out of range\n"); |
f01b7962 VS |
560 | |
561 | if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev)) | |
562 | if (clock->m1 <= clock->m2) | |
563 | INTELPllInvalid("m1 <= m2\n"); | |
564 | ||
565 | if (!IS_VALLEYVIEW(dev)) { | |
566 | if (clock->p < limit->p.min || limit->p.max < clock->p) | |
567 | INTELPllInvalid("p out of range\n"); | |
568 | if (clock->m < limit->m.min || limit->m.max < clock->m) | |
569 | INTELPllInvalid("m out of range\n"); | |
570 | } | |
571 | ||
79e53945 | 572 | if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) |
0206e353 | 573 | INTELPllInvalid("vco out of range\n"); |
79e53945 JB |
574 | /* XXX: We may need to be checking "Dot clock" depending on the multiplier, |
575 | * connector, etc., rather than just a single range. | |
576 | */ | |
577 | if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) | |
0206e353 | 578 | INTELPllInvalid("dot out of range\n"); |
79e53945 JB |
579 | |
580 | return true; | |
581 | } | |
582 | ||
d4906093 | 583 | static bool |
ee9300bb | 584 | i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
cec2f356 SP |
585 | int target, int refclk, intel_clock_t *match_clock, |
586 | intel_clock_t *best_clock) | |
79e53945 JB |
587 | { |
588 | struct drm_device *dev = crtc->dev; | |
79e53945 | 589 | intel_clock_t clock; |
79e53945 JB |
590 | int err = target; |
591 | ||
a210b028 | 592 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 593 | /* |
a210b028 DV |
594 | * For LVDS just rely on its current settings for dual-channel. |
595 | * We haven't figured out how to reliably set up different | |
596 | * single/dual channel state, if we even can. | |
79e53945 | 597 | */ |
1974cad0 | 598 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
599 | clock.p2 = limit->p2.p2_fast; |
600 | else | |
601 | clock.p2 = limit->p2.p2_slow; | |
602 | } else { | |
603 | if (target < limit->p2.dot_limit) | |
604 | clock.p2 = limit->p2.p2_slow; | |
605 | else | |
606 | clock.p2 = limit->p2.p2_fast; | |
607 | } | |
608 | ||
0206e353 | 609 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 610 | |
42158660 ZY |
611 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
612 | clock.m1++) { | |
613 | for (clock.m2 = limit->m2.min; | |
614 | clock.m2 <= limit->m2.max; clock.m2++) { | |
c0efc387 | 615 | if (clock.m2 >= clock.m1) |
42158660 ZY |
616 | break; |
617 | for (clock.n = limit->n.min; | |
618 | clock.n <= limit->n.max; clock.n++) { | |
619 | for (clock.p1 = limit->p1.min; | |
620 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
621 | int this_err; |
622 | ||
ac58c3f0 DV |
623 | i9xx_clock(refclk, &clock); |
624 | if (!intel_PLL_is_valid(dev, limit, | |
625 | &clock)) | |
626 | continue; | |
627 | if (match_clock && | |
628 | clock.p != match_clock->p) | |
629 | continue; | |
630 | ||
631 | this_err = abs(clock.dot - target); | |
632 | if (this_err < err) { | |
633 | *best_clock = clock; | |
634 | err = this_err; | |
635 | } | |
636 | } | |
637 | } | |
638 | } | |
639 | } | |
640 | ||
641 | return (err != target); | |
642 | } | |
643 | ||
644 | static bool | |
ee9300bb DV |
645 | pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
646 | int target, int refclk, intel_clock_t *match_clock, | |
647 | intel_clock_t *best_clock) | |
79e53945 JB |
648 | { |
649 | struct drm_device *dev = crtc->dev; | |
79e53945 | 650 | intel_clock_t clock; |
79e53945 JB |
651 | int err = target; |
652 | ||
a210b028 | 653 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { |
79e53945 | 654 | /* |
a210b028 DV |
655 | * For LVDS just rely on its current settings for dual-channel. |
656 | * We haven't figured out how to reliably set up different | |
657 | * single/dual channel state, if we even can. | |
79e53945 | 658 | */ |
1974cad0 | 659 | if (intel_is_dual_link_lvds(dev)) |
79e53945 JB |
660 | clock.p2 = limit->p2.p2_fast; |
661 | else | |
662 | clock.p2 = limit->p2.p2_slow; | |
663 | } else { | |
664 | if (target < limit->p2.dot_limit) | |
665 | clock.p2 = limit->p2.p2_slow; | |
666 | else | |
667 | clock.p2 = limit->p2.p2_fast; | |
668 | } | |
669 | ||
0206e353 | 670 | memset(best_clock, 0, sizeof(*best_clock)); |
79e53945 | 671 | |
42158660 ZY |
672 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; |
673 | clock.m1++) { | |
674 | for (clock.m2 = limit->m2.min; | |
675 | clock.m2 <= limit->m2.max; clock.m2++) { | |
42158660 ZY |
676 | for (clock.n = limit->n.min; |
677 | clock.n <= limit->n.max; clock.n++) { | |
678 | for (clock.p1 = limit->p1.min; | |
679 | clock.p1 <= limit->p1.max; clock.p1++) { | |
79e53945 JB |
680 | int this_err; |
681 | ||
ac58c3f0 | 682 | pineview_clock(refclk, &clock); |
1b894b59 CW |
683 | if (!intel_PLL_is_valid(dev, limit, |
684 | &clock)) | |
79e53945 | 685 | continue; |
cec2f356 SP |
686 | if (match_clock && |
687 | clock.p != match_clock->p) | |
688 | continue; | |
79e53945 JB |
689 | |
690 | this_err = abs(clock.dot - target); | |
691 | if (this_err < err) { | |
692 | *best_clock = clock; | |
693 | err = this_err; | |
694 | } | |
695 | } | |
696 | } | |
697 | } | |
698 | } | |
699 | ||
700 | return (err != target); | |
701 | } | |
702 | ||
d4906093 | 703 | static bool |
ee9300bb DV |
704 | g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
705 | int target, int refclk, intel_clock_t *match_clock, | |
706 | intel_clock_t *best_clock) | |
d4906093 ML |
707 | { |
708 | struct drm_device *dev = crtc->dev; | |
d4906093 ML |
709 | intel_clock_t clock; |
710 | int max_n; | |
711 | bool found; | |
6ba770dc AJ |
712 | /* approximately equals target * 0.00585 */ |
713 | int err_most = (target >> 8) + (target >> 9); | |
d4906093 ML |
714 | found = false; |
715 | ||
716 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) { | |
1974cad0 | 717 | if (intel_is_dual_link_lvds(dev)) |
d4906093 ML |
718 | clock.p2 = limit->p2.p2_fast; |
719 | else | |
720 | clock.p2 = limit->p2.p2_slow; | |
721 | } else { | |
722 | if (target < limit->p2.dot_limit) | |
723 | clock.p2 = limit->p2.p2_slow; | |
724 | else | |
725 | clock.p2 = limit->p2.p2_fast; | |
726 | } | |
727 | ||
728 | memset(best_clock, 0, sizeof(*best_clock)); | |
729 | max_n = limit->n.max; | |
f77f13e2 | 730 | /* based on hardware requirement, prefer smaller n to precision */ |
d4906093 | 731 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
f77f13e2 | 732 | /* based on hardware requirement, prefere larger m1,m2 */ |
d4906093 ML |
733 | for (clock.m1 = limit->m1.max; |
734 | clock.m1 >= limit->m1.min; clock.m1--) { | |
735 | for (clock.m2 = limit->m2.max; | |
736 | clock.m2 >= limit->m2.min; clock.m2--) { | |
737 | for (clock.p1 = limit->p1.max; | |
738 | clock.p1 >= limit->p1.min; clock.p1--) { | |
739 | int this_err; | |
740 | ||
ac58c3f0 | 741 | i9xx_clock(refclk, &clock); |
1b894b59 CW |
742 | if (!intel_PLL_is_valid(dev, limit, |
743 | &clock)) | |
d4906093 | 744 | continue; |
1b894b59 CW |
745 | |
746 | this_err = abs(clock.dot - target); | |
d4906093 ML |
747 | if (this_err < err_most) { |
748 | *best_clock = clock; | |
749 | err_most = this_err; | |
750 | max_n = clock.n; | |
751 | found = true; | |
752 | } | |
753 | } | |
754 | } | |
755 | } | |
756 | } | |
2c07245f ZW |
757 | return found; |
758 | } | |
759 | ||
a0c4da24 | 760 | static bool |
ee9300bb DV |
761 | vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, |
762 | int target, int refclk, intel_clock_t *match_clock, | |
763 | intel_clock_t *best_clock) | |
a0c4da24 | 764 | { |
f01b7962 | 765 | struct drm_device *dev = crtc->dev; |
6b4bf1c4 | 766 | intel_clock_t clock; |
69e4f900 | 767 | unsigned int bestppm = 1000000; |
27e639bf VS |
768 | /* min update 19.2 MHz */ |
769 | int max_n = min(limit->n.max, refclk / 19200); | |
49e497ef | 770 | bool found = false; |
a0c4da24 | 771 | |
6b4bf1c4 VS |
772 | target *= 5; /* fast clock */ |
773 | ||
774 | memset(best_clock, 0, sizeof(*best_clock)); | |
a0c4da24 JB |
775 | |
776 | /* based on hardware requirement, prefer smaller n to precision */ | |
27e639bf | 777 | for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { |
811bbf05 | 778 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { |
889059d8 | 779 | for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; |
c1a9ae43 | 780 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { |
6b4bf1c4 | 781 | clock.p = clock.p1 * clock.p2; |
a0c4da24 | 782 | /* based on hardware requirement, prefer bigger m1,m2 values */ |
6b4bf1c4 | 783 | for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { |
69e4f900 VS |
784 | unsigned int ppm, diff; |
785 | ||
6b4bf1c4 VS |
786 | clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, |
787 | refclk * clock.m1); | |
788 | ||
789 | vlv_clock(refclk, &clock); | |
43b0ac53 | 790 | |
f01b7962 VS |
791 | if (!intel_PLL_is_valid(dev, limit, |
792 | &clock)) | |
43b0ac53 VS |
793 | continue; |
794 | ||
6b4bf1c4 VS |
795 | diff = abs(clock.dot - target); |
796 | ppm = div_u64(1000000ULL * diff, target); | |
797 | ||
798 | if (ppm < 100 && clock.p > best_clock->p) { | |
43b0ac53 | 799 | bestppm = 0; |
6b4bf1c4 | 800 | *best_clock = clock; |
49e497ef | 801 | found = true; |
43b0ac53 | 802 | } |
6b4bf1c4 | 803 | |
c686122c | 804 | if (bestppm >= 10 && ppm < bestppm - 10) { |
69e4f900 | 805 | bestppm = ppm; |
6b4bf1c4 | 806 | *best_clock = clock; |
49e497ef | 807 | found = true; |
a0c4da24 JB |
808 | } |
809 | } | |
810 | } | |
811 | } | |
812 | } | |
a0c4da24 | 813 | |
49e497ef | 814 | return found; |
a0c4da24 | 815 | } |
a4fc5ed6 | 816 | |
ef9348c8 CML |
817 | static bool |
818 | chv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc, | |
819 | int target, int refclk, intel_clock_t *match_clock, | |
820 | intel_clock_t *best_clock) | |
821 | { | |
822 | struct drm_device *dev = crtc->dev; | |
823 | intel_clock_t clock; | |
824 | uint64_t m2; | |
825 | int found = false; | |
826 | ||
827 | memset(best_clock, 0, sizeof(*best_clock)); | |
828 | ||
829 | /* | |
830 | * Based on hardware doc, the n always set to 1, and m1 always | |
831 | * set to 2. If requires to support 200Mhz refclk, we need to | |
832 | * revisit this because n may not 1 anymore. | |
833 | */ | |
834 | clock.n = 1, clock.m1 = 2; | |
835 | target *= 5; /* fast clock */ | |
836 | ||
837 | for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { | |
838 | for (clock.p2 = limit->p2.p2_fast; | |
839 | clock.p2 >= limit->p2.p2_slow; | |
840 | clock.p2 -= clock.p2 > 10 ? 2 : 1) { | |
841 | ||
842 | clock.p = clock.p1 * clock.p2; | |
843 | ||
844 | m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p * | |
845 | clock.n) << 22, refclk * clock.m1); | |
846 | ||
847 | if (m2 > INT_MAX/clock.m1) | |
848 | continue; | |
849 | ||
850 | clock.m2 = m2; | |
851 | ||
852 | chv_clock(refclk, &clock); | |
853 | ||
854 | if (!intel_PLL_is_valid(dev, limit, &clock)) | |
855 | continue; | |
856 | ||
857 | /* based on hardware requirement, prefer bigger p | |
858 | */ | |
859 | if (clock.p > best_clock->p) { | |
860 | *best_clock = clock; | |
861 | found = true; | |
862 | } | |
863 | } | |
864 | } | |
865 | ||
866 | return found; | |
867 | } | |
868 | ||
20ddf665 VS |
869 | bool intel_crtc_active(struct drm_crtc *crtc) |
870 | { | |
871 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
872 | ||
873 | /* Be paranoid as we can arrive here with only partial | |
874 | * state retrieved from the hardware during setup. | |
875 | * | |
241bfc38 | 876 | * We can ditch the adjusted_mode.crtc_clock check as soon |
20ddf665 VS |
877 | * as Haswell has gained clock readout/fastboot support. |
878 | * | |
66e514c1 | 879 | * We can ditch the crtc->primary->fb check as soon as we can |
20ddf665 VS |
880 | * properly reconstruct framebuffers. |
881 | */ | |
f4510a27 | 882 | return intel_crtc->active && crtc->primary->fb && |
241bfc38 | 883 | intel_crtc->config.adjusted_mode.crtc_clock; |
20ddf665 VS |
884 | } |
885 | ||
a5c961d1 PZ |
886 | enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, |
887 | enum pipe pipe) | |
888 | { | |
889 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
890 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
891 | ||
3b117c8f | 892 | return intel_crtc->config.cpu_transcoder; |
a5c961d1 PZ |
893 | } |
894 | ||
57e22f4a | 895 | static void g4x_wait_for_vblank(struct drm_device *dev, int pipe) |
a928d536 PZ |
896 | { |
897 | struct drm_i915_private *dev_priv = dev->dev_private; | |
57e22f4a | 898 | u32 frame, frame_reg = PIPE_FRMCOUNT_GM45(pipe); |
a928d536 PZ |
899 | |
900 | frame = I915_READ(frame_reg); | |
901 | ||
902 | if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50)) | |
31e4b89a DL |
903 | WARN(1, "vblank wait on pipe %c timed out\n", |
904 | pipe_name(pipe)); | |
a928d536 PZ |
905 | } |
906 | ||
9d0498a2 JB |
907 | /** |
908 | * intel_wait_for_vblank - wait for vblank on a given pipe | |
909 | * @dev: drm device | |
910 | * @pipe: pipe to wait for | |
911 | * | |
912 | * Wait for vblank to occur on a given pipe. Needed for various bits of | |
913 | * mode setting code. | |
914 | */ | |
915 | void intel_wait_for_vblank(struct drm_device *dev, int pipe) | |
79e53945 | 916 | { |
9d0498a2 | 917 | struct drm_i915_private *dev_priv = dev->dev_private; |
9db4a9c7 | 918 | int pipestat_reg = PIPESTAT(pipe); |
9d0498a2 | 919 | |
57e22f4a VS |
920 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
921 | g4x_wait_for_vblank(dev, pipe); | |
a928d536 PZ |
922 | return; |
923 | } | |
924 | ||
300387c0 CW |
925 | /* Clear existing vblank status. Note this will clear any other |
926 | * sticky status fields as well. | |
927 | * | |
928 | * This races with i915_driver_irq_handler() with the result | |
929 | * that either function could miss a vblank event. Here it is not | |
930 | * fatal, as we will either wait upon the next vblank interrupt or | |
931 | * timeout. Generally speaking intel_wait_for_vblank() is only | |
932 | * called during modeset at which time the GPU should be idle and | |
933 | * should *not* be performing page flips and thus not waiting on | |
934 | * vblanks... | |
935 | * Currently, the result of us stealing a vblank from the irq | |
936 | * handler is that a single frame will be skipped during swapbuffers. | |
937 | */ | |
938 | I915_WRITE(pipestat_reg, | |
939 | I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS); | |
940 | ||
9d0498a2 | 941 | /* Wait for vblank interrupt bit to set */ |
481b6af3 CW |
942 | if (wait_for(I915_READ(pipestat_reg) & |
943 | PIPE_VBLANK_INTERRUPT_STATUS, | |
944 | 50)) | |
31e4b89a DL |
945 | DRM_DEBUG_KMS("vblank wait on pipe %c timed out\n", |
946 | pipe_name(pipe)); | |
9d0498a2 JB |
947 | } |
948 | ||
fbf49ea2 VS |
949 | static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe) |
950 | { | |
951 | struct drm_i915_private *dev_priv = dev->dev_private; | |
952 | u32 reg = PIPEDSL(pipe); | |
953 | u32 line1, line2; | |
954 | u32 line_mask; | |
955 | ||
956 | if (IS_GEN2(dev)) | |
957 | line_mask = DSL_LINEMASK_GEN2; | |
958 | else | |
959 | line_mask = DSL_LINEMASK_GEN3; | |
960 | ||
961 | line1 = I915_READ(reg) & line_mask; | |
962 | mdelay(5); | |
963 | line2 = I915_READ(reg) & line_mask; | |
964 | ||
965 | return line1 == line2; | |
966 | } | |
967 | ||
ab7ad7f6 KP |
968 | /* |
969 | * intel_wait_for_pipe_off - wait for pipe to turn off | |
575f7ab7 | 970 | * @crtc: crtc whose pipe to wait for |
9d0498a2 JB |
971 | * |
972 | * After disabling a pipe, we can't wait for vblank in the usual way, | |
973 | * spinning on the vblank interrupt status bit, since we won't actually | |
974 | * see an interrupt when the pipe is disabled. | |
975 | * | |
ab7ad7f6 KP |
976 | * On Gen4 and above: |
977 | * wait for the pipe register state bit to turn off | |
978 | * | |
979 | * Otherwise: | |
980 | * wait for the display line value to settle (it usually | |
981 | * ends up stopping at the start of the next frame). | |
58e10eb9 | 982 | * |
9d0498a2 | 983 | */ |
575f7ab7 | 984 | static void intel_wait_for_pipe_off(struct intel_crtc *crtc) |
9d0498a2 | 985 | { |
575f7ab7 | 986 | struct drm_device *dev = crtc->base.dev; |
9d0498a2 | 987 | struct drm_i915_private *dev_priv = dev->dev_private; |
575f7ab7 VS |
988 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; |
989 | enum pipe pipe = crtc->pipe; | |
ab7ad7f6 KP |
990 | |
991 | if (INTEL_INFO(dev)->gen >= 4) { | |
702e7a56 | 992 | int reg = PIPECONF(cpu_transcoder); |
ab7ad7f6 KP |
993 | |
994 | /* Wait for the Pipe State to go off */ | |
58e10eb9 CW |
995 | if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, |
996 | 100)) | |
284637d9 | 997 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 998 | } else { |
ab7ad7f6 | 999 | /* Wait for the display line to settle */ |
fbf49ea2 | 1000 | if (wait_for(pipe_dsl_stopped(dev, pipe), 100)) |
284637d9 | 1001 | WARN(1, "pipe_off wait timed out\n"); |
ab7ad7f6 | 1002 | } |
79e53945 JB |
1003 | } |
1004 | ||
b0ea7d37 DL |
1005 | /* |
1006 | * ibx_digital_port_connected - is the specified port connected? | |
1007 | * @dev_priv: i915 private structure | |
1008 | * @port: the port to test | |
1009 | * | |
1010 | * Returns true if @port is connected, false otherwise. | |
1011 | */ | |
1012 | bool ibx_digital_port_connected(struct drm_i915_private *dev_priv, | |
1013 | struct intel_digital_port *port) | |
1014 | { | |
1015 | u32 bit; | |
1016 | ||
c36346e3 | 1017 | if (HAS_PCH_IBX(dev_priv->dev)) { |
eba905b2 | 1018 | switch (port->port) { |
c36346e3 DL |
1019 | case PORT_B: |
1020 | bit = SDE_PORTB_HOTPLUG; | |
1021 | break; | |
1022 | case PORT_C: | |
1023 | bit = SDE_PORTC_HOTPLUG; | |
1024 | break; | |
1025 | case PORT_D: | |
1026 | bit = SDE_PORTD_HOTPLUG; | |
1027 | break; | |
1028 | default: | |
1029 | return true; | |
1030 | } | |
1031 | } else { | |
eba905b2 | 1032 | switch (port->port) { |
c36346e3 DL |
1033 | case PORT_B: |
1034 | bit = SDE_PORTB_HOTPLUG_CPT; | |
1035 | break; | |
1036 | case PORT_C: | |
1037 | bit = SDE_PORTC_HOTPLUG_CPT; | |
1038 | break; | |
1039 | case PORT_D: | |
1040 | bit = SDE_PORTD_HOTPLUG_CPT; | |
1041 | break; | |
1042 | default: | |
1043 | return true; | |
1044 | } | |
b0ea7d37 DL |
1045 | } |
1046 | ||
1047 | return I915_READ(SDEISR) & bit; | |
1048 | } | |
1049 | ||
b24e7179 JB |
1050 | static const char *state_string(bool enabled) |
1051 | { | |
1052 | return enabled ? "on" : "off"; | |
1053 | } | |
1054 | ||
1055 | /* Only for pre-ILK configs */ | |
55607e8a DV |
1056 | void assert_pll(struct drm_i915_private *dev_priv, |
1057 | enum pipe pipe, bool state) | |
b24e7179 JB |
1058 | { |
1059 | int reg; | |
1060 | u32 val; | |
1061 | bool cur_state; | |
1062 | ||
1063 | reg = DPLL(pipe); | |
1064 | val = I915_READ(reg); | |
1065 | cur_state = !!(val & DPLL_VCO_ENABLE); | |
1066 | WARN(cur_state != state, | |
1067 | "PLL state assertion failure (expected %s, current %s)\n", | |
1068 | state_string(state), state_string(cur_state)); | |
1069 | } | |
b24e7179 | 1070 | |
23538ef1 JN |
1071 | /* XXX: the dsi pll is shared between MIPI DSI ports */ |
1072 | static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state) | |
1073 | { | |
1074 | u32 val; | |
1075 | bool cur_state; | |
1076 | ||
1077 | mutex_lock(&dev_priv->dpio_lock); | |
1078 | val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL); | |
1079 | mutex_unlock(&dev_priv->dpio_lock); | |
1080 | ||
1081 | cur_state = val & DSI_PLL_VCO_EN; | |
1082 | WARN(cur_state != state, | |
1083 | "DSI PLL state assertion failure (expected %s, current %s)\n", | |
1084 | state_string(state), state_string(cur_state)); | |
1085 | } | |
1086 | #define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true) | |
1087 | #define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false) | |
1088 | ||
55607e8a | 1089 | struct intel_shared_dpll * |
e2b78267 DV |
1090 | intel_crtc_to_shared_dpll(struct intel_crtc *crtc) |
1091 | { | |
1092 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
1093 | ||
a43f6e0f | 1094 | if (crtc->config.shared_dpll < 0) |
e2b78267 DV |
1095 | return NULL; |
1096 | ||
a43f6e0f | 1097 | return &dev_priv->shared_dplls[crtc->config.shared_dpll]; |
e2b78267 DV |
1098 | } |
1099 | ||
040484af | 1100 | /* For ILK+ */ |
55607e8a DV |
1101 | void assert_shared_dpll(struct drm_i915_private *dev_priv, |
1102 | struct intel_shared_dpll *pll, | |
1103 | bool state) | |
040484af | 1104 | { |
040484af | 1105 | bool cur_state; |
5358901f | 1106 | struct intel_dpll_hw_state hw_state; |
040484af | 1107 | |
92b27b08 | 1108 | if (WARN (!pll, |
46edb027 | 1109 | "asserting DPLL %s with no DPLL\n", state_string(state))) |
ee7b9f93 | 1110 | return; |
ee7b9f93 | 1111 | |
5358901f | 1112 | cur_state = pll->get_hw_state(dev_priv, pll, &hw_state); |
92b27b08 | 1113 | WARN(cur_state != state, |
5358901f DV |
1114 | "%s assertion failure (expected %s, current %s)\n", |
1115 | pll->name, state_string(state), state_string(cur_state)); | |
040484af | 1116 | } |
040484af JB |
1117 | |
1118 | static void assert_fdi_tx(struct drm_i915_private *dev_priv, | |
1119 | enum pipe pipe, bool state) | |
1120 | { | |
1121 | int reg; | |
1122 | u32 val; | |
1123 | bool cur_state; | |
ad80a810 PZ |
1124 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1125 | pipe); | |
040484af | 1126 | |
affa9354 PZ |
1127 | if (HAS_DDI(dev_priv->dev)) { |
1128 | /* DDI does not have a specific FDI_TX register */ | |
ad80a810 | 1129 | reg = TRANS_DDI_FUNC_CTL(cpu_transcoder); |
bf507ef7 | 1130 | val = I915_READ(reg); |
ad80a810 | 1131 | cur_state = !!(val & TRANS_DDI_FUNC_ENABLE); |
bf507ef7 ED |
1132 | } else { |
1133 | reg = FDI_TX_CTL(pipe); | |
1134 | val = I915_READ(reg); | |
1135 | cur_state = !!(val & FDI_TX_ENABLE); | |
1136 | } | |
040484af JB |
1137 | WARN(cur_state != state, |
1138 | "FDI TX state assertion failure (expected %s, current %s)\n", | |
1139 | state_string(state), state_string(cur_state)); | |
1140 | } | |
1141 | #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true) | |
1142 | #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false) | |
1143 | ||
1144 | static void assert_fdi_rx(struct drm_i915_private *dev_priv, | |
1145 | enum pipe pipe, bool state) | |
1146 | { | |
1147 | int reg; | |
1148 | u32 val; | |
1149 | bool cur_state; | |
1150 | ||
d63fa0dc PZ |
1151 | reg = FDI_RX_CTL(pipe); |
1152 | val = I915_READ(reg); | |
1153 | cur_state = !!(val & FDI_RX_ENABLE); | |
040484af JB |
1154 | WARN(cur_state != state, |
1155 | "FDI RX state assertion failure (expected %s, current %s)\n", | |
1156 | state_string(state), state_string(cur_state)); | |
1157 | } | |
1158 | #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true) | |
1159 | #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false) | |
1160 | ||
1161 | static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv, | |
1162 | enum pipe pipe) | |
1163 | { | |
1164 | int reg; | |
1165 | u32 val; | |
1166 | ||
1167 | /* ILK FDI PLL is always enabled */ | |
3d13ef2e | 1168 | if (INTEL_INFO(dev_priv->dev)->gen == 5) |
040484af JB |
1169 | return; |
1170 | ||
bf507ef7 | 1171 | /* On Haswell, DDI ports are responsible for the FDI PLL setup */ |
affa9354 | 1172 | if (HAS_DDI(dev_priv->dev)) |
bf507ef7 ED |
1173 | return; |
1174 | ||
040484af JB |
1175 | reg = FDI_TX_CTL(pipe); |
1176 | val = I915_READ(reg); | |
1177 | WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n"); | |
1178 | } | |
1179 | ||
55607e8a DV |
1180 | void assert_fdi_rx_pll(struct drm_i915_private *dev_priv, |
1181 | enum pipe pipe, bool state) | |
040484af JB |
1182 | { |
1183 | int reg; | |
1184 | u32 val; | |
55607e8a | 1185 | bool cur_state; |
040484af JB |
1186 | |
1187 | reg = FDI_RX_CTL(pipe); | |
1188 | val = I915_READ(reg); | |
55607e8a DV |
1189 | cur_state = !!(val & FDI_RX_PLL_ENABLE); |
1190 | WARN(cur_state != state, | |
1191 | "FDI RX PLL assertion failure (expected %s, current %s)\n", | |
1192 | state_string(state), state_string(cur_state)); | |
040484af JB |
1193 | } |
1194 | ||
ea0760cf JB |
1195 | static void assert_panel_unlocked(struct drm_i915_private *dev_priv, |
1196 | enum pipe pipe) | |
1197 | { | |
bedd4dba JN |
1198 | struct drm_device *dev = dev_priv->dev; |
1199 | int pp_reg; | |
ea0760cf JB |
1200 | u32 val; |
1201 | enum pipe panel_pipe = PIPE_A; | |
0de3b485 | 1202 | bool locked = true; |
ea0760cf | 1203 | |
bedd4dba JN |
1204 | if (WARN_ON(HAS_DDI(dev))) |
1205 | return; | |
1206 | ||
1207 | if (HAS_PCH_SPLIT(dev)) { | |
1208 | u32 port_sel; | |
1209 | ||
ea0760cf | 1210 | pp_reg = PCH_PP_CONTROL; |
bedd4dba JN |
1211 | port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK; |
1212 | ||
1213 | if (port_sel == PANEL_PORT_SELECT_LVDS && | |
1214 | I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) | |
1215 | panel_pipe = PIPE_B; | |
1216 | /* XXX: else fix for eDP */ | |
1217 | } else if (IS_VALLEYVIEW(dev)) { | |
1218 | /* presumably write lock depends on pipe, not port select */ | |
1219 | pp_reg = VLV_PIPE_PP_CONTROL(pipe); | |
1220 | panel_pipe = pipe; | |
ea0760cf JB |
1221 | } else { |
1222 | pp_reg = PP_CONTROL; | |
bedd4dba JN |
1223 | if (I915_READ(LVDS) & LVDS_PIPEB_SELECT) |
1224 | panel_pipe = PIPE_B; | |
ea0760cf JB |
1225 | } |
1226 | ||
1227 | val = I915_READ(pp_reg); | |
1228 | if (!(val & PANEL_POWER_ON) || | |
ec49ba2d | 1229 | ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS)) |
ea0760cf JB |
1230 | locked = false; |
1231 | ||
ea0760cf JB |
1232 | WARN(panel_pipe == pipe && locked, |
1233 | "panel assertion failure, pipe %c regs locked\n", | |
9db4a9c7 | 1234 | pipe_name(pipe)); |
ea0760cf JB |
1235 | } |
1236 | ||
93ce0ba6 JN |
1237 | static void assert_cursor(struct drm_i915_private *dev_priv, |
1238 | enum pipe pipe, bool state) | |
1239 | { | |
1240 | struct drm_device *dev = dev_priv->dev; | |
1241 | bool cur_state; | |
1242 | ||
d9d82081 | 1243 | if (IS_845G(dev) || IS_I865G(dev)) |
93ce0ba6 | 1244 | cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE; |
d9d82081 | 1245 | else |
5efb3e28 | 1246 | cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE; |
93ce0ba6 JN |
1247 | |
1248 | WARN(cur_state != state, | |
1249 | "cursor on pipe %c assertion failure (expected %s, current %s)\n", | |
1250 | pipe_name(pipe), state_string(state), state_string(cur_state)); | |
1251 | } | |
1252 | #define assert_cursor_enabled(d, p) assert_cursor(d, p, true) | |
1253 | #define assert_cursor_disabled(d, p) assert_cursor(d, p, false) | |
1254 | ||
b840d907 JB |
1255 | void assert_pipe(struct drm_i915_private *dev_priv, |
1256 | enum pipe pipe, bool state) | |
b24e7179 JB |
1257 | { |
1258 | int reg; | |
1259 | u32 val; | |
63d7bbe9 | 1260 | bool cur_state; |
702e7a56 PZ |
1261 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
1262 | pipe); | |
b24e7179 | 1263 | |
b6b5d049 VS |
1264 | /* if we need the pipe quirk it must be always on */ |
1265 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1266 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
8e636784 DV |
1267 | state = true; |
1268 | ||
da7e29bd | 1269 | if (!intel_display_power_enabled(dev_priv, |
b97186f0 | 1270 | POWER_DOMAIN_TRANSCODER(cpu_transcoder))) { |
69310161 PZ |
1271 | cur_state = false; |
1272 | } else { | |
1273 | reg = PIPECONF(cpu_transcoder); | |
1274 | val = I915_READ(reg); | |
1275 | cur_state = !!(val & PIPECONF_ENABLE); | |
1276 | } | |
1277 | ||
63d7bbe9 JB |
1278 | WARN(cur_state != state, |
1279 | "pipe %c assertion failure (expected %s, current %s)\n", | |
9db4a9c7 | 1280 | pipe_name(pipe), state_string(state), state_string(cur_state)); |
b24e7179 JB |
1281 | } |
1282 | ||
931872fc CW |
1283 | static void assert_plane(struct drm_i915_private *dev_priv, |
1284 | enum plane plane, bool state) | |
b24e7179 JB |
1285 | { |
1286 | int reg; | |
1287 | u32 val; | |
931872fc | 1288 | bool cur_state; |
b24e7179 JB |
1289 | |
1290 | reg = DSPCNTR(plane); | |
1291 | val = I915_READ(reg); | |
931872fc CW |
1292 | cur_state = !!(val & DISPLAY_PLANE_ENABLE); |
1293 | WARN(cur_state != state, | |
1294 | "plane %c assertion failure (expected %s, current %s)\n", | |
1295 | plane_name(plane), state_string(state), state_string(cur_state)); | |
b24e7179 JB |
1296 | } |
1297 | ||
931872fc CW |
1298 | #define assert_plane_enabled(d, p) assert_plane(d, p, true) |
1299 | #define assert_plane_disabled(d, p) assert_plane(d, p, false) | |
1300 | ||
b24e7179 JB |
1301 | static void assert_planes_disabled(struct drm_i915_private *dev_priv, |
1302 | enum pipe pipe) | |
1303 | { | |
653e1026 | 1304 | struct drm_device *dev = dev_priv->dev; |
b24e7179 JB |
1305 | int reg, i; |
1306 | u32 val; | |
1307 | int cur_pipe; | |
1308 | ||
653e1026 VS |
1309 | /* Primary planes are fixed to pipes on gen4+ */ |
1310 | if (INTEL_INFO(dev)->gen >= 4) { | |
28c05794 AJ |
1311 | reg = DSPCNTR(pipe); |
1312 | val = I915_READ(reg); | |
83f26f16 | 1313 | WARN(val & DISPLAY_PLANE_ENABLE, |
28c05794 AJ |
1314 | "plane %c assertion failure, should be disabled but not\n", |
1315 | plane_name(pipe)); | |
19ec1358 | 1316 | return; |
28c05794 | 1317 | } |
19ec1358 | 1318 | |
b24e7179 | 1319 | /* Need to check both planes against the pipe */ |
055e393f | 1320 | for_each_pipe(dev_priv, i) { |
b24e7179 JB |
1321 | reg = DSPCNTR(i); |
1322 | val = I915_READ(reg); | |
1323 | cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >> | |
1324 | DISPPLANE_SEL_PIPE_SHIFT; | |
1325 | WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe, | |
9db4a9c7 JB |
1326 | "plane %c assertion failure, should be off on pipe %c but is still active\n", |
1327 | plane_name(i), pipe_name(pipe)); | |
b24e7179 JB |
1328 | } |
1329 | } | |
1330 | ||
19332d7a JB |
1331 | static void assert_sprites_disabled(struct drm_i915_private *dev_priv, |
1332 | enum pipe pipe) | |
1333 | { | |
20674eef | 1334 | struct drm_device *dev = dev_priv->dev; |
1fe47785 | 1335 | int reg, sprite; |
19332d7a JB |
1336 | u32 val; |
1337 | ||
20674eef | 1338 | if (IS_VALLEYVIEW(dev)) { |
1fe47785 DL |
1339 | for_each_sprite(pipe, sprite) { |
1340 | reg = SPCNTR(pipe, sprite); | |
20674eef | 1341 | val = I915_READ(reg); |
83f26f16 | 1342 | WARN(val & SP_ENABLE, |
20674eef | 1343 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
1fe47785 | 1344 | sprite_name(pipe, sprite), pipe_name(pipe)); |
20674eef VS |
1345 | } |
1346 | } else if (INTEL_INFO(dev)->gen >= 7) { | |
1347 | reg = SPRCTL(pipe); | |
19332d7a | 1348 | val = I915_READ(reg); |
83f26f16 | 1349 | WARN(val & SPRITE_ENABLE, |
06da8da2 | 1350 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef VS |
1351 | plane_name(pipe), pipe_name(pipe)); |
1352 | } else if (INTEL_INFO(dev)->gen >= 5) { | |
1353 | reg = DVSCNTR(pipe); | |
19332d7a | 1354 | val = I915_READ(reg); |
83f26f16 | 1355 | WARN(val & DVS_ENABLE, |
06da8da2 | 1356 | "sprite %c assertion failure, should be off on pipe %c but is still active\n", |
20674eef | 1357 | plane_name(pipe), pipe_name(pipe)); |
19332d7a JB |
1358 | } |
1359 | } | |
1360 | ||
08c71e5e VS |
1361 | static void assert_vblank_disabled(struct drm_crtc *crtc) |
1362 | { | |
1363 | if (WARN_ON(drm_crtc_vblank_get(crtc) == 0)) | |
1364 | drm_crtc_vblank_put(crtc); | |
1365 | } | |
1366 | ||
89eff4be | 1367 | static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv) |
92f2584a JB |
1368 | { |
1369 | u32 val; | |
1370 | bool enabled; | |
1371 | ||
89eff4be | 1372 | WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev))); |
9d82aa17 | 1373 | |
92f2584a JB |
1374 | val = I915_READ(PCH_DREF_CONTROL); |
1375 | enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK | | |
1376 | DREF_SUPERSPREAD_SOURCE_MASK)); | |
1377 | WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n"); | |
1378 | } | |
1379 | ||
ab9412ba DV |
1380 | static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv, |
1381 | enum pipe pipe) | |
92f2584a JB |
1382 | { |
1383 | int reg; | |
1384 | u32 val; | |
1385 | bool enabled; | |
1386 | ||
ab9412ba | 1387 | reg = PCH_TRANSCONF(pipe); |
92f2584a JB |
1388 | val = I915_READ(reg); |
1389 | enabled = !!(val & TRANS_ENABLE); | |
9db4a9c7 JB |
1390 | WARN(enabled, |
1391 | "transcoder assertion failed, should be off on pipe %c but is still active\n", | |
1392 | pipe_name(pipe)); | |
92f2584a JB |
1393 | } |
1394 | ||
4e634389 KP |
1395 | static bool dp_pipe_enabled(struct drm_i915_private *dev_priv, |
1396 | enum pipe pipe, u32 port_sel, u32 val) | |
f0575e92 KP |
1397 | { |
1398 | if ((val & DP_PORT_EN) == 0) | |
1399 | return false; | |
1400 | ||
1401 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1402 | u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe); | |
1403 | u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg); | |
1404 | if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel) | |
1405 | return false; | |
44f37d1f CML |
1406 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1407 | if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe)) | |
1408 | return false; | |
f0575e92 KP |
1409 | } else { |
1410 | if ((val & DP_PIPE_MASK) != (pipe << 30)) | |
1411 | return false; | |
1412 | } | |
1413 | return true; | |
1414 | } | |
1415 | ||
1519b995 KP |
1416 | static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv, |
1417 | enum pipe pipe, u32 val) | |
1418 | { | |
dc0fa718 | 1419 | if ((val & SDVO_ENABLE) == 0) |
1519b995 KP |
1420 | return false; |
1421 | ||
1422 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
dc0fa718 | 1423 | if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe)) |
1519b995 | 1424 | return false; |
44f37d1f CML |
1425 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
1426 | if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe)) | |
1427 | return false; | |
1519b995 | 1428 | } else { |
dc0fa718 | 1429 | if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe)) |
1519b995 KP |
1430 | return false; |
1431 | } | |
1432 | return true; | |
1433 | } | |
1434 | ||
1435 | static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv, | |
1436 | enum pipe pipe, u32 val) | |
1437 | { | |
1438 | if ((val & LVDS_PORT_EN) == 0) | |
1439 | return false; | |
1440 | ||
1441 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1442 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1443 | return false; | |
1444 | } else { | |
1445 | if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe)) | |
1446 | return false; | |
1447 | } | |
1448 | return true; | |
1449 | } | |
1450 | ||
1451 | static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv, | |
1452 | enum pipe pipe, u32 val) | |
1453 | { | |
1454 | if ((val & ADPA_DAC_ENABLE) == 0) | |
1455 | return false; | |
1456 | if (HAS_PCH_CPT(dev_priv->dev)) { | |
1457 | if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe)) | |
1458 | return false; | |
1459 | } else { | |
1460 | if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe)) | |
1461 | return false; | |
1462 | } | |
1463 | return true; | |
1464 | } | |
1465 | ||
291906f1 | 1466 | static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv, |
f0575e92 | 1467 | enum pipe pipe, int reg, u32 port_sel) |
291906f1 | 1468 | { |
47a05eca | 1469 | u32 val = I915_READ(reg); |
4e634389 | 1470 | WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val), |
291906f1 | 1471 | "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1472 | reg, pipe_name(pipe)); |
de9a35ab | 1473 | |
75c5da27 DV |
1474 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0 |
1475 | && (val & DP_PIPEB_SELECT), | |
de9a35ab | 1476 | "IBX PCH dp port still using transcoder B\n"); |
291906f1 JB |
1477 | } |
1478 | ||
1479 | static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv, | |
1480 | enum pipe pipe, int reg) | |
1481 | { | |
47a05eca | 1482 | u32 val = I915_READ(reg); |
b70ad586 | 1483 | WARN(hdmi_pipe_enabled(dev_priv, pipe, val), |
23c99e77 | 1484 | "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1485 | reg, pipe_name(pipe)); |
de9a35ab | 1486 | |
dc0fa718 | 1487 | WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0 |
75c5da27 | 1488 | && (val & SDVO_PIPE_B_SELECT), |
de9a35ab | 1489 | "IBX PCH hdmi port still using transcoder B\n"); |
291906f1 JB |
1490 | } |
1491 | ||
1492 | static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv, | |
1493 | enum pipe pipe) | |
1494 | { | |
1495 | int reg; | |
1496 | u32 val; | |
291906f1 | 1497 | |
f0575e92 KP |
1498 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B); |
1499 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C); | |
1500 | assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D); | |
291906f1 JB |
1501 | |
1502 | reg = PCH_ADPA; | |
1503 | val = I915_READ(reg); | |
b70ad586 | 1504 | WARN(adpa_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1505 | "PCH VGA enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1506 | pipe_name(pipe)); |
291906f1 JB |
1507 | |
1508 | reg = PCH_LVDS; | |
1509 | val = I915_READ(reg); | |
b70ad586 | 1510 | WARN(lvds_pipe_enabled(dev_priv, pipe, val), |
291906f1 | 1511 | "PCH LVDS enabled on transcoder %c, should be disabled\n", |
9db4a9c7 | 1512 | pipe_name(pipe)); |
291906f1 | 1513 | |
e2debe91 PZ |
1514 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB); |
1515 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC); | |
1516 | assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID); | |
291906f1 JB |
1517 | } |
1518 | ||
40e9cf64 JB |
1519 | static void intel_init_dpio(struct drm_device *dev) |
1520 | { | |
1521 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1522 | ||
1523 | if (!IS_VALLEYVIEW(dev)) | |
1524 | return; | |
1525 | ||
a09caddd CML |
1526 | /* |
1527 | * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C), | |
1528 | * CHV x1 PHY (DP/HDMI D) | |
1529 | * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C) | |
1530 | */ | |
1531 | if (IS_CHERRYVIEW(dev)) { | |
1532 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2; | |
1533 | DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO; | |
1534 | } else { | |
1535 | DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO; | |
1536 | } | |
5382f5f3 JB |
1537 | } |
1538 | ||
426115cf | 1539 | static void vlv_enable_pll(struct intel_crtc *crtc) |
87442f73 | 1540 | { |
426115cf DV |
1541 | struct drm_device *dev = crtc->base.dev; |
1542 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1543 | int reg = DPLL(crtc->pipe); | |
1544 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
87442f73 | 1545 | |
426115cf | 1546 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87442f73 DV |
1547 | |
1548 | /* No really, not for ILK+ */ | |
1549 | BUG_ON(!IS_VALLEYVIEW(dev_priv->dev)); | |
1550 | ||
1551 | /* PLL is protected by panel, make sure we can write it */ | |
6a9e7363 | 1552 | if (IS_MOBILE(dev_priv->dev)) |
426115cf | 1553 | assert_panel_unlocked(dev_priv, crtc->pipe); |
87442f73 | 1554 | |
426115cf DV |
1555 | I915_WRITE(reg, dpll); |
1556 | POSTING_READ(reg); | |
1557 | udelay(150); | |
1558 | ||
1559 | if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) | |
1560 | DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe); | |
1561 | ||
1562 | I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md); | |
1563 | POSTING_READ(DPLL_MD(crtc->pipe)); | |
87442f73 DV |
1564 | |
1565 | /* We do this three times for luck */ | |
426115cf | 1566 | I915_WRITE(reg, dpll); |
87442f73 DV |
1567 | POSTING_READ(reg); |
1568 | udelay(150); /* wait for warmup */ | |
426115cf | 1569 | I915_WRITE(reg, dpll); |
87442f73 DV |
1570 | POSTING_READ(reg); |
1571 | udelay(150); /* wait for warmup */ | |
426115cf | 1572 | I915_WRITE(reg, dpll); |
87442f73 DV |
1573 | POSTING_READ(reg); |
1574 | udelay(150); /* wait for warmup */ | |
1575 | } | |
1576 | ||
9d556c99 CML |
1577 | static void chv_enable_pll(struct intel_crtc *crtc) |
1578 | { | |
1579 | struct drm_device *dev = crtc->base.dev; | |
1580 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1581 | int pipe = crtc->pipe; | |
1582 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
9d556c99 CML |
1583 | u32 tmp; |
1584 | ||
1585 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
1586 | ||
1587 | BUG_ON(!IS_CHERRYVIEW(dev_priv->dev)); | |
1588 | ||
1589 | mutex_lock(&dev_priv->dpio_lock); | |
1590 | ||
1591 | /* Enable back the 10bit clock to display controller */ | |
1592 | tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1593 | tmp |= DPIO_DCLKP_EN; | |
1594 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); | |
1595 | ||
1596 | /* | |
1597 | * Need to wait > 100ns between dclkp clock enable bit and PLL enable. | |
1598 | */ | |
1599 | udelay(1); | |
1600 | ||
1601 | /* Enable PLL */ | |
a11b0703 | 1602 | I915_WRITE(DPLL(pipe), crtc->config.dpll_hw_state.dpll); |
9d556c99 CML |
1603 | |
1604 | /* Check PLL is locked */ | |
a11b0703 | 1605 | if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1)) |
9d556c99 CML |
1606 | DRM_ERROR("PLL %d failed to lock\n", pipe); |
1607 | ||
a11b0703 VS |
1608 | /* not sure when this should be written */ |
1609 | I915_WRITE(DPLL_MD(pipe), crtc->config.dpll_hw_state.dpll_md); | |
1610 | POSTING_READ(DPLL_MD(pipe)); | |
1611 | ||
9d556c99 CML |
1612 | mutex_unlock(&dev_priv->dpio_lock); |
1613 | } | |
1614 | ||
1c4e0274 VS |
1615 | static int intel_num_dvo_pipes(struct drm_device *dev) |
1616 | { | |
1617 | struct intel_crtc *crtc; | |
1618 | int count = 0; | |
1619 | ||
1620 | for_each_intel_crtc(dev, crtc) | |
1621 | count += crtc->active && | |
1622 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO); | |
1623 | ||
1624 | return count; | |
1625 | } | |
1626 | ||
66e3d5c0 | 1627 | static void i9xx_enable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1628 | { |
66e3d5c0 DV |
1629 | struct drm_device *dev = crtc->base.dev; |
1630 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1631 | int reg = DPLL(crtc->pipe); | |
1632 | u32 dpll = crtc->config.dpll_hw_state.dpll; | |
63d7bbe9 | 1633 | |
66e3d5c0 | 1634 | assert_pipe_disabled(dev_priv, crtc->pipe); |
58c6eaa2 | 1635 | |
63d7bbe9 | 1636 | /* No really, not for ILK+ */ |
3d13ef2e | 1637 | BUG_ON(INTEL_INFO(dev)->gen >= 5); |
63d7bbe9 JB |
1638 | |
1639 | /* PLL is protected by panel, make sure we can write it */ | |
66e3d5c0 DV |
1640 | if (IS_MOBILE(dev) && !IS_I830(dev)) |
1641 | assert_panel_unlocked(dev_priv, crtc->pipe); | |
63d7bbe9 | 1642 | |
1c4e0274 VS |
1643 | /* Enable DVO 2x clock on both PLLs if necessary */ |
1644 | if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) { | |
1645 | /* | |
1646 | * It appears to be important that we don't enable this | |
1647 | * for the current pipe before otherwise configuring the | |
1648 | * PLL. No idea how this should be handled if multiple | |
1649 | * DVO outputs are enabled simultaneosly. | |
1650 | */ | |
1651 | dpll |= DPLL_DVO_2X_MODE; | |
1652 | I915_WRITE(DPLL(!crtc->pipe), | |
1653 | I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE); | |
1654 | } | |
66e3d5c0 DV |
1655 | |
1656 | /* Wait for the clocks to stabilize. */ | |
1657 | POSTING_READ(reg); | |
1658 | udelay(150); | |
1659 | ||
1660 | if (INTEL_INFO(dev)->gen >= 4) { | |
1661 | I915_WRITE(DPLL_MD(crtc->pipe), | |
1662 | crtc->config.dpll_hw_state.dpll_md); | |
1663 | } else { | |
1664 | /* The pixel multiplier can only be updated once the | |
1665 | * DPLL is enabled and the clocks are stable. | |
1666 | * | |
1667 | * So write it again. | |
1668 | */ | |
1669 | I915_WRITE(reg, dpll); | |
1670 | } | |
63d7bbe9 JB |
1671 | |
1672 | /* We do this three times for luck */ | |
66e3d5c0 | 1673 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1674 | POSTING_READ(reg); |
1675 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1676 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1677 | POSTING_READ(reg); |
1678 | udelay(150); /* wait for warmup */ | |
66e3d5c0 | 1679 | I915_WRITE(reg, dpll); |
63d7bbe9 JB |
1680 | POSTING_READ(reg); |
1681 | udelay(150); /* wait for warmup */ | |
1682 | } | |
1683 | ||
1684 | /** | |
50b44a44 | 1685 | * i9xx_disable_pll - disable a PLL |
63d7bbe9 JB |
1686 | * @dev_priv: i915 private structure |
1687 | * @pipe: pipe PLL to disable | |
1688 | * | |
1689 | * Disable the PLL for @pipe, making sure the pipe is off first. | |
1690 | * | |
1691 | * Note! This is for pre-ILK only. | |
1692 | */ | |
1c4e0274 | 1693 | static void i9xx_disable_pll(struct intel_crtc *crtc) |
63d7bbe9 | 1694 | { |
1c4e0274 VS |
1695 | struct drm_device *dev = crtc->base.dev; |
1696 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1697 | enum pipe pipe = crtc->pipe; | |
1698 | ||
1699 | /* Disable DVO 2x clock on both PLLs if necessary */ | |
1700 | if (IS_I830(dev) && | |
1701 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO) && | |
1702 | intel_num_dvo_pipes(dev) == 1) { | |
1703 | I915_WRITE(DPLL(PIPE_B), | |
1704 | I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE); | |
1705 | I915_WRITE(DPLL(PIPE_A), | |
1706 | I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE); | |
1707 | } | |
1708 | ||
b6b5d049 VS |
1709 | /* Don't disable pipe or pipe PLLs if needed */ |
1710 | if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
1711 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
63d7bbe9 JB |
1712 | return; |
1713 | ||
1714 | /* Make sure the pipe isn't still relying on us */ | |
1715 | assert_pipe_disabled(dev_priv, pipe); | |
1716 | ||
50b44a44 DV |
1717 | I915_WRITE(DPLL(pipe), 0); |
1718 | POSTING_READ(DPLL(pipe)); | |
63d7bbe9 JB |
1719 | } |
1720 | ||
f6071166 JB |
1721 | static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) |
1722 | { | |
1723 | u32 val = 0; | |
1724 | ||
1725 | /* Make sure the pipe isn't still relying on us */ | |
1726 | assert_pipe_disabled(dev_priv, pipe); | |
1727 | ||
e5cbfbfb ID |
1728 | /* |
1729 | * Leave integrated clock source and reference clock enabled for pipe B. | |
1730 | * The latter is needed for VGA hotplug / manual detection. | |
1731 | */ | |
f6071166 | 1732 | if (pipe == PIPE_B) |
e5cbfbfb | 1733 | val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV; |
f6071166 JB |
1734 | I915_WRITE(DPLL(pipe), val); |
1735 | POSTING_READ(DPLL(pipe)); | |
076ed3b2 CML |
1736 | |
1737 | } | |
1738 | ||
1739 | static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) | |
1740 | { | |
d752048d | 1741 | enum dpio_channel port = vlv_pipe_to_channel(pipe); |
076ed3b2 CML |
1742 | u32 val; |
1743 | ||
a11b0703 VS |
1744 | /* Make sure the pipe isn't still relying on us */ |
1745 | assert_pipe_disabled(dev_priv, pipe); | |
076ed3b2 | 1746 | |
a11b0703 | 1747 | /* Set PLL en = 0 */ |
d17ec4ce | 1748 | val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV; |
a11b0703 VS |
1749 | if (pipe != PIPE_A) |
1750 | val |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
1751 | I915_WRITE(DPLL(pipe), val); | |
1752 | POSTING_READ(DPLL(pipe)); | |
d752048d VS |
1753 | |
1754 | mutex_lock(&dev_priv->dpio_lock); | |
1755 | ||
1756 | /* Disable 10bit clock to display controller */ | |
1757 | val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); | |
1758 | val &= ~DPIO_DCLKP_EN; | |
1759 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); | |
1760 | ||
61407f6d VS |
1761 | /* disable left/right clock distribution */ |
1762 | if (pipe != PIPE_B) { | |
1763 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); | |
1764 | val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); | |
1765 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); | |
1766 | } else { | |
1767 | val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); | |
1768 | val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); | |
1769 | vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); | |
1770 | } | |
1771 | ||
d752048d | 1772 | mutex_unlock(&dev_priv->dpio_lock); |
f6071166 JB |
1773 | } |
1774 | ||
e4607fcf CML |
1775 | void vlv_wait_port_ready(struct drm_i915_private *dev_priv, |
1776 | struct intel_digital_port *dport) | |
89b667f8 JB |
1777 | { |
1778 | u32 port_mask; | |
00fc31b7 | 1779 | int dpll_reg; |
89b667f8 | 1780 | |
e4607fcf CML |
1781 | switch (dport->port) { |
1782 | case PORT_B: | |
89b667f8 | 1783 | port_mask = DPLL_PORTB_READY_MASK; |
00fc31b7 | 1784 | dpll_reg = DPLL(0); |
e4607fcf CML |
1785 | break; |
1786 | case PORT_C: | |
89b667f8 | 1787 | port_mask = DPLL_PORTC_READY_MASK; |
00fc31b7 CML |
1788 | dpll_reg = DPLL(0); |
1789 | break; | |
1790 | case PORT_D: | |
1791 | port_mask = DPLL_PORTD_READY_MASK; | |
1792 | dpll_reg = DPIO_PHY_STATUS; | |
e4607fcf CML |
1793 | break; |
1794 | default: | |
1795 | BUG(); | |
1796 | } | |
89b667f8 | 1797 | |
00fc31b7 | 1798 | if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000)) |
89b667f8 | 1799 | WARN(1, "timed out waiting for port %c ready: 0x%08x\n", |
00fc31b7 | 1800 | port_name(dport->port), I915_READ(dpll_reg)); |
89b667f8 JB |
1801 | } |
1802 | ||
b14b1055 DV |
1803 | static void intel_prepare_shared_dpll(struct intel_crtc *crtc) |
1804 | { | |
1805 | struct drm_device *dev = crtc->base.dev; | |
1806 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1807 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
1808 | ||
be19f0ff CW |
1809 | if (WARN_ON(pll == NULL)) |
1810 | return; | |
1811 | ||
b14b1055 DV |
1812 | WARN_ON(!pll->refcount); |
1813 | if (pll->active == 0) { | |
1814 | DRM_DEBUG_DRIVER("setting up %s\n", pll->name); | |
1815 | WARN_ON(pll->on); | |
1816 | assert_shared_dpll_disabled(dev_priv, pll); | |
1817 | ||
1818 | pll->mode_set(dev_priv, pll); | |
1819 | } | |
1820 | } | |
1821 | ||
92f2584a | 1822 | /** |
85b3894f | 1823 | * intel_enable_shared_dpll - enable PCH PLL |
92f2584a JB |
1824 | * @dev_priv: i915 private structure |
1825 | * @pipe: pipe PLL to enable | |
1826 | * | |
1827 | * The PCH PLL needs to be enabled before the PCH transcoder, since it | |
1828 | * drives the transcoder clock. | |
1829 | */ | |
85b3894f | 1830 | static void intel_enable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1831 | { |
3d13ef2e DL |
1832 | struct drm_device *dev = crtc->base.dev; |
1833 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1834 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
92f2584a | 1835 | |
87a875bb | 1836 | if (WARN_ON(pll == NULL)) |
48da64a8 CW |
1837 | return; |
1838 | ||
1839 | if (WARN_ON(pll->refcount == 0)) | |
1840 | return; | |
ee7b9f93 | 1841 | |
74dd6928 | 1842 | DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n", |
46edb027 | 1843 | pll->name, pll->active, pll->on, |
e2b78267 | 1844 | crtc->base.base.id); |
92f2584a | 1845 | |
cdbd2316 DV |
1846 | if (pll->active++) { |
1847 | WARN_ON(!pll->on); | |
e9d6944e | 1848 | assert_shared_dpll_enabled(dev_priv, pll); |
ee7b9f93 JB |
1849 | return; |
1850 | } | |
f4a091c7 | 1851 | WARN_ON(pll->on); |
ee7b9f93 | 1852 | |
bd2bb1b9 PZ |
1853 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); |
1854 | ||
46edb027 | 1855 | DRM_DEBUG_KMS("enabling %s\n", pll->name); |
e7b903d2 | 1856 | pll->enable(dev_priv, pll); |
ee7b9f93 | 1857 | pll->on = true; |
92f2584a JB |
1858 | } |
1859 | ||
f6daaec2 | 1860 | static void intel_disable_shared_dpll(struct intel_crtc *crtc) |
92f2584a | 1861 | { |
3d13ef2e DL |
1862 | struct drm_device *dev = crtc->base.dev; |
1863 | struct drm_i915_private *dev_priv = dev->dev_private; | |
e2b78267 | 1864 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
4c609cb8 | 1865 | |
92f2584a | 1866 | /* PCH only available on ILK+ */ |
3d13ef2e | 1867 | BUG_ON(INTEL_INFO(dev)->gen < 5); |
87a875bb | 1868 | if (WARN_ON(pll == NULL)) |
ee7b9f93 | 1869 | return; |
92f2584a | 1870 | |
48da64a8 CW |
1871 | if (WARN_ON(pll->refcount == 0)) |
1872 | return; | |
7a419866 | 1873 | |
46edb027 DV |
1874 | DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n", |
1875 | pll->name, pll->active, pll->on, | |
e2b78267 | 1876 | crtc->base.base.id); |
7a419866 | 1877 | |
48da64a8 | 1878 | if (WARN_ON(pll->active == 0)) { |
e9d6944e | 1879 | assert_shared_dpll_disabled(dev_priv, pll); |
48da64a8 CW |
1880 | return; |
1881 | } | |
1882 | ||
e9d6944e | 1883 | assert_shared_dpll_enabled(dev_priv, pll); |
f4a091c7 | 1884 | WARN_ON(!pll->on); |
cdbd2316 | 1885 | if (--pll->active) |
7a419866 | 1886 | return; |
ee7b9f93 | 1887 | |
46edb027 | 1888 | DRM_DEBUG_KMS("disabling %s\n", pll->name); |
e7b903d2 | 1889 | pll->disable(dev_priv, pll); |
ee7b9f93 | 1890 | pll->on = false; |
bd2bb1b9 PZ |
1891 | |
1892 | intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS); | |
92f2584a JB |
1893 | } |
1894 | ||
b8a4f404 PZ |
1895 | static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
1896 | enum pipe pipe) | |
040484af | 1897 | { |
23670b32 | 1898 | struct drm_device *dev = dev_priv->dev; |
7c26e5c6 | 1899 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
e2b78267 | 1900 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
23670b32 | 1901 | uint32_t reg, val, pipeconf_val; |
040484af JB |
1902 | |
1903 | /* PCH only available on ILK+ */ | |
55522f37 | 1904 | BUG_ON(!HAS_PCH_SPLIT(dev)); |
040484af JB |
1905 | |
1906 | /* Make sure PCH DPLL is enabled */ | |
e72f9fbf | 1907 | assert_shared_dpll_enabled(dev_priv, |
e9d6944e | 1908 | intel_crtc_to_shared_dpll(intel_crtc)); |
040484af JB |
1909 | |
1910 | /* FDI must be feeding us bits for PCH ports */ | |
1911 | assert_fdi_tx_enabled(dev_priv, pipe); | |
1912 | assert_fdi_rx_enabled(dev_priv, pipe); | |
1913 | ||
23670b32 DV |
1914 | if (HAS_PCH_CPT(dev)) { |
1915 | /* Workaround: Set the timing override bit before enabling the | |
1916 | * pch transcoder. */ | |
1917 | reg = TRANS_CHICKEN2(pipe); | |
1918 | val = I915_READ(reg); | |
1919 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
1920 | I915_WRITE(reg, val); | |
59c859d6 | 1921 | } |
23670b32 | 1922 | |
ab9412ba | 1923 | reg = PCH_TRANSCONF(pipe); |
040484af | 1924 | val = I915_READ(reg); |
5f7f726d | 1925 | pipeconf_val = I915_READ(PIPECONF(pipe)); |
e9bcff5c JB |
1926 | |
1927 | if (HAS_PCH_IBX(dev_priv->dev)) { | |
1928 | /* | |
1929 | * make the BPC in transcoder be consistent with | |
1930 | * that in pipeconf reg. | |
1931 | */ | |
dfd07d72 DV |
1932 | val &= ~PIPECONF_BPC_MASK; |
1933 | val |= pipeconf_val & PIPECONF_BPC_MASK; | |
e9bcff5c | 1934 | } |
5f7f726d PZ |
1935 | |
1936 | val &= ~TRANS_INTERLACE_MASK; | |
1937 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK) | |
7c26e5c6 PZ |
1938 | if (HAS_PCH_IBX(dev_priv->dev) && |
1939 | intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) | |
1940 | val |= TRANS_LEGACY_INTERLACED_ILK; | |
1941 | else | |
1942 | val |= TRANS_INTERLACED; | |
5f7f726d PZ |
1943 | else |
1944 | val |= TRANS_PROGRESSIVE; | |
1945 | ||
040484af JB |
1946 | I915_WRITE(reg, val | TRANS_ENABLE); |
1947 | if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100)) | |
4bb6f1f3 | 1948 | DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); |
040484af JB |
1949 | } |
1950 | ||
8fb033d7 | 1951 | static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv, |
937bb610 | 1952 | enum transcoder cpu_transcoder) |
040484af | 1953 | { |
8fb033d7 | 1954 | u32 val, pipeconf_val; |
8fb033d7 PZ |
1955 | |
1956 | /* PCH only available on ILK+ */ | |
55522f37 | 1957 | BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev)); |
8fb033d7 | 1958 | |
8fb033d7 | 1959 | /* FDI must be feeding us bits for PCH ports */ |
1a240d4d | 1960 | assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder); |
937bb610 | 1961 | assert_fdi_rx_enabled(dev_priv, TRANSCODER_A); |
8fb033d7 | 1962 | |
223a6fdf PZ |
1963 | /* Workaround: set timing override bit. */ |
1964 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 1965 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf PZ |
1966 | I915_WRITE(_TRANSA_CHICKEN2, val); |
1967 | ||
25f3ef11 | 1968 | val = TRANS_ENABLE; |
937bb610 | 1969 | pipeconf_val = I915_READ(PIPECONF(cpu_transcoder)); |
8fb033d7 | 1970 | |
9a76b1c6 PZ |
1971 | if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) == |
1972 | PIPECONF_INTERLACED_ILK) | |
a35f2679 | 1973 | val |= TRANS_INTERLACED; |
8fb033d7 PZ |
1974 | else |
1975 | val |= TRANS_PROGRESSIVE; | |
1976 | ||
ab9412ba DV |
1977 | I915_WRITE(LPT_TRANSCONF, val); |
1978 | if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100)) | |
937bb610 | 1979 | DRM_ERROR("Failed to enable PCH transcoder\n"); |
8fb033d7 PZ |
1980 | } |
1981 | ||
b8a4f404 PZ |
1982 | static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv, |
1983 | enum pipe pipe) | |
040484af | 1984 | { |
23670b32 DV |
1985 | struct drm_device *dev = dev_priv->dev; |
1986 | uint32_t reg, val; | |
040484af JB |
1987 | |
1988 | /* FDI relies on the transcoder */ | |
1989 | assert_fdi_tx_disabled(dev_priv, pipe); | |
1990 | assert_fdi_rx_disabled(dev_priv, pipe); | |
1991 | ||
291906f1 JB |
1992 | /* Ports must be off as well */ |
1993 | assert_pch_ports_disabled(dev_priv, pipe); | |
1994 | ||
ab9412ba | 1995 | reg = PCH_TRANSCONF(pipe); |
040484af JB |
1996 | val = I915_READ(reg); |
1997 | val &= ~TRANS_ENABLE; | |
1998 | I915_WRITE(reg, val); | |
1999 | /* wait for PCH transcoder off, transcoder state */ | |
2000 | if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50)) | |
4bb6f1f3 | 2001 | DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); |
23670b32 DV |
2002 | |
2003 | if (!HAS_PCH_IBX(dev)) { | |
2004 | /* Workaround: Clear the timing override chicken bit again. */ | |
2005 | reg = TRANS_CHICKEN2(pipe); | |
2006 | val = I915_READ(reg); | |
2007 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; | |
2008 | I915_WRITE(reg, val); | |
2009 | } | |
040484af JB |
2010 | } |
2011 | ||
ab4d966c | 2012 | static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv) |
8fb033d7 | 2013 | { |
8fb033d7 PZ |
2014 | u32 val; |
2015 | ||
ab9412ba | 2016 | val = I915_READ(LPT_TRANSCONF); |
8fb033d7 | 2017 | val &= ~TRANS_ENABLE; |
ab9412ba | 2018 | I915_WRITE(LPT_TRANSCONF, val); |
8fb033d7 | 2019 | /* wait for PCH transcoder off, transcoder state */ |
ab9412ba | 2020 | if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50)) |
8a52fd9f | 2021 | DRM_ERROR("Failed to disable PCH transcoder\n"); |
223a6fdf PZ |
2022 | |
2023 | /* Workaround: clear timing override bit. */ | |
2024 | val = I915_READ(_TRANSA_CHICKEN2); | |
23670b32 | 2025 | val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE; |
223a6fdf | 2026 | I915_WRITE(_TRANSA_CHICKEN2, val); |
040484af JB |
2027 | } |
2028 | ||
b24e7179 | 2029 | /** |
309cfea8 | 2030 | * intel_enable_pipe - enable a pipe, asserting requirements |
0372264a | 2031 | * @crtc: crtc responsible for the pipe |
b24e7179 | 2032 | * |
0372264a | 2033 | * Enable @crtc's pipe, making sure that various hardware specific requirements |
b24e7179 | 2034 | * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc. |
b24e7179 | 2035 | */ |
e1fdc473 | 2036 | static void intel_enable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2037 | { |
0372264a PZ |
2038 | struct drm_device *dev = crtc->base.dev; |
2039 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2040 | enum pipe pipe = crtc->pipe; | |
702e7a56 PZ |
2041 | enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, |
2042 | pipe); | |
1a240d4d | 2043 | enum pipe pch_transcoder; |
b24e7179 JB |
2044 | int reg; |
2045 | u32 val; | |
2046 | ||
58c6eaa2 | 2047 | assert_planes_disabled(dev_priv, pipe); |
93ce0ba6 | 2048 | assert_cursor_disabled(dev_priv, pipe); |
58c6eaa2 DV |
2049 | assert_sprites_disabled(dev_priv, pipe); |
2050 | ||
681e5811 | 2051 | if (HAS_PCH_LPT(dev_priv->dev)) |
cc391bbb PZ |
2052 | pch_transcoder = TRANSCODER_A; |
2053 | else | |
2054 | pch_transcoder = pipe; | |
2055 | ||
b24e7179 JB |
2056 | /* |
2057 | * A pipe without a PLL won't actually be able to drive bits from | |
2058 | * a plane. On ILK+ the pipe PLLs are integrated, so we don't | |
2059 | * need the check. | |
2060 | */ | |
2061 | if (!HAS_PCH_SPLIT(dev_priv->dev)) | |
fbf3218a | 2062 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DSI)) |
23538ef1 JN |
2063 | assert_dsi_pll_enabled(dev_priv); |
2064 | else | |
2065 | assert_pll_enabled(dev_priv, pipe); | |
040484af | 2066 | else { |
30421c4f | 2067 | if (crtc->config.has_pch_encoder) { |
040484af | 2068 | /* if driving the PCH, we need FDI enabled */ |
cc391bbb | 2069 | assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder); |
1a240d4d DV |
2070 | assert_fdi_tx_pll_enabled(dev_priv, |
2071 | (enum pipe) cpu_transcoder); | |
040484af JB |
2072 | } |
2073 | /* FIXME: assert CPU port conditions for SNB+ */ | |
2074 | } | |
b24e7179 | 2075 | |
702e7a56 | 2076 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2077 | val = I915_READ(reg); |
7ad25d48 | 2078 | if (val & PIPECONF_ENABLE) { |
b6b5d049 VS |
2079 | WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
2080 | (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))); | |
00d70b15 | 2081 | return; |
7ad25d48 | 2082 | } |
00d70b15 CW |
2083 | |
2084 | I915_WRITE(reg, val | PIPECONF_ENABLE); | |
851855d8 | 2085 | POSTING_READ(reg); |
b24e7179 JB |
2086 | } |
2087 | ||
2088 | /** | |
309cfea8 | 2089 | * intel_disable_pipe - disable a pipe, asserting requirements |
575f7ab7 | 2090 | * @crtc: crtc whose pipes is to be disabled |
b24e7179 | 2091 | * |
575f7ab7 VS |
2092 | * Disable the pipe of @crtc, making sure that various hardware |
2093 | * specific requirements are met, if applicable, e.g. plane | |
2094 | * disabled, panel fitter off, etc. | |
b24e7179 JB |
2095 | * |
2096 | * Will wait until the pipe has shut down before returning. | |
2097 | */ | |
575f7ab7 | 2098 | static void intel_disable_pipe(struct intel_crtc *crtc) |
b24e7179 | 2099 | { |
575f7ab7 VS |
2100 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
2101 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
2102 | enum pipe pipe = crtc->pipe; | |
b24e7179 JB |
2103 | int reg; |
2104 | u32 val; | |
2105 | ||
2106 | /* | |
2107 | * Make sure planes won't keep trying to pump pixels to us, | |
2108 | * or we might hang the display. | |
2109 | */ | |
2110 | assert_planes_disabled(dev_priv, pipe); | |
93ce0ba6 | 2111 | assert_cursor_disabled(dev_priv, pipe); |
19332d7a | 2112 | assert_sprites_disabled(dev_priv, pipe); |
b24e7179 | 2113 | |
702e7a56 | 2114 | reg = PIPECONF(cpu_transcoder); |
b24e7179 | 2115 | val = I915_READ(reg); |
00d70b15 CW |
2116 | if ((val & PIPECONF_ENABLE) == 0) |
2117 | return; | |
2118 | ||
67adc644 VS |
2119 | /* |
2120 | * Double wide has implications for planes | |
2121 | * so best keep it disabled when not needed. | |
2122 | */ | |
2123 | if (crtc->config.double_wide) | |
2124 | val &= ~PIPECONF_DOUBLE_WIDE; | |
2125 | ||
2126 | /* Don't disable pipe or pipe PLLs if needed */ | |
b6b5d049 VS |
2127 | if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) && |
2128 | !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
67adc644 VS |
2129 | val &= ~PIPECONF_ENABLE; |
2130 | ||
2131 | I915_WRITE(reg, val); | |
2132 | if ((val & PIPECONF_ENABLE) == 0) | |
2133 | intel_wait_for_pipe_off(crtc); | |
b24e7179 JB |
2134 | } |
2135 | ||
d74362c9 KP |
2136 | /* |
2137 | * Plane regs are double buffered, going from enabled->disabled needs a | |
2138 | * trigger in order to latch. The display address reg provides this. | |
2139 | */ | |
1dba99f4 VS |
2140 | void intel_flush_primary_plane(struct drm_i915_private *dev_priv, |
2141 | enum plane plane) | |
d74362c9 | 2142 | { |
3d13ef2e DL |
2143 | struct drm_device *dev = dev_priv->dev; |
2144 | u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane); | |
1dba99f4 VS |
2145 | |
2146 | I915_WRITE(reg, I915_READ(reg)); | |
2147 | POSTING_READ(reg); | |
d74362c9 KP |
2148 | } |
2149 | ||
b24e7179 | 2150 | /** |
262ca2b0 | 2151 | * intel_enable_primary_hw_plane - enable the primary plane on a given pipe |
fdd508a6 VS |
2152 | * @plane: plane to be enabled |
2153 | * @crtc: crtc for the plane | |
b24e7179 | 2154 | * |
fdd508a6 | 2155 | * Enable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2156 | */ |
fdd508a6 VS |
2157 | static void intel_enable_primary_hw_plane(struct drm_plane *plane, |
2158 | struct drm_crtc *crtc) | |
b24e7179 | 2159 | { |
fdd508a6 VS |
2160 | struct drm_device *dev = plane->dev; |
2161 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2162 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
b24e7179 JB |
2163 | |
2164 | /* If the pipe isn't enabled, we can't pump pixels and may hang */ | |
fdd508a6 | 2165 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); |
b24e7179 | 2166 | |
98ec7739 VS |
2167 | if (intel_crtc->primary_enabled) |
2168 | return; | |
0037f71c | 2169 | |
4c445e0e | 2170 | intel_crtc->primary_enabled = true; |
939c2fe8 | 2171 | |
fdd508a6 VS |
2172 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2173 | crtc->x, crtc->y); | |
33c3b0d1 VS |
2174 | |
2175 | /* | |
2176 | * BDW signals flip done immediately if the plane | |
2177 | * is disabled, even if the plane enable is already | |
2178 | * armed to occur at the next vblank :( | |
2179 | */ | |
2180 | if (IS_BROADWELL(dev)) | |
2181 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
b24e7179 JB |
2182 | } |
2183 | ||
b24e7179 | 2184 | /** |
262ca2b0 | 2185 | * intel_disable_primary_hw_plane - disable the primary hardware plane |
fdd508a6 VS |
2186 | * @plane: plane to be disabled |
2187 | * @crtc: crtc for the plane | |
b24e7179 | 2188 | * |
fdd508a6 | 2189 | * Disable @plane on @crtc, making sure that the pipe is running first. |
b24e7179 | 2190 | */ |
fdd508a6 VS |
2191 | static void intel_disable_primary_hw_plane(struct drm_plane *plane, |
2192 | struct drm_crtc *crtc) | |
b24e7179 | 2193 | { |
fdd508a6 VS |
2194 | struct drm_device *dev = plane->dev; |
2195 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2196 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2197 | ||
2198 | assert_pipe_enabled(dev_priv, intel_crtc->pipe); | |
b24e7179 | 2199 | |
98ec7739 VS |
2200 | if (!intel_crtc->primary_enabled) |
2201 | return; | |
0037f71c | 2202 | |
4c445e0e | 2203 | intel_crtc->primary_enabled = false; |
939c2fe8 | 2204 | |
fdd508a6 VS |
2205 | dev_priv->display.update_primary_plane(crtc, plane->fb, |
2206 | crtc->x, crtc->y); | |
b24e7179 JB |
2207 | } |
2208 | ||
693db184 CW |
2209 | static bool need_vtd_wa(struct drm_device *dev) |
2210 | { | |
2211 | #ifdef CONFIG_INTEL_IOMMU | |
2212 | if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped) | |
2213 | return true; | |
2214 | #endif | |
2215 | return false; | |
2216 | } | |
2217 | ||
a57ce0b2 JB |
2218 | static int intel_align_height(struct drm_device *dev, int height, bool tiled) |
2219 | { | |
2220 | int tile_height; | |
2221 | ||
2222 | tile_height = tiled ? (IS_GEN2(dev) ? 16 : 8) : 1; | |
2223 | return ALIGN(height, tile_height); | |
2224 | } | |
2225 | ||
127bd2ac | 2226 | int |
48b956c5 | 2227 | intel_pin_and_fence_fb_obj(struct drm_device *dev, |
05394f39 | 2228 | struct drm_i915_gem_object *obj, |
a4872ba6 | 2229 | struct intel_engine_cs *pipelined) |
6b95a207 | 2230 | { |
ce453d81 | 2231 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
2232 | u32 alignment; |
2233 | int ret; | |
2234 | ||
ebcdd39e MR |
2235 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
2236 | ||
05394f39 | 2237 | switch (obj->tiling_mode) { |
6b95a207 | 2238 | case I915_TILING_NONE: |
534843da CW |
2239 | if (IS_BROADWATER(dev) || IS_CRESTLINE(dev)) |
2240 | alignment = 128 * 1024; | |
a6c45cf0 | 2241 | else if (INTEL_INFO(dev)->gen >= 4) |
534843da CW |
2242 | alignment = 4 * 1024; |
2243 | else | |
2244 | alignment = 64 * 1024; | |
6b95a207 KH |
2245 | break; |
2246 | case I915_TILING_X: | |
2247 | /* pin() will align the object as required by fence */ | |
2248 | alignment = 0; | |
2249 | break; | |
2250 | case I915_TILING_Y: | |
80075d49 | 2251 | WARN(1, "Y tiled bo slipped through, driver bug!\n"); |
6b95a207 KH |
2252 | return -EINVAL; |
2253 | default: | |
2254 | BUG(); | |
2255 | } | |
2256 | ||
693db184 CW |
2257 | /* Note that the w/a also requires 64 PTE of padding following the |
2258 | * bo. We currently fill all unused PTE with the shadow page and so | |
2259 | * we should always have valid PTE following the scanout preventing | |
2260 | * the VT-d warning. | |
2261 | */ | |
2262 | if (need_vtd_wa(dev) && alignment < 256 * 1024) | |
2263 | alignment = 256 * 1024; | |
2264 | ||
d6dd6843 PZ |
2265 | /* |
2266 | * Global gtt pte registers are special registers which actually forward | |
2267 | * writes to a chunk of system memory. Which means that there is no risk | |
2268 | * that the register values disappear as soon as we call | |
2269 | * intel_runtime_pm_put(), so it is correct to wrap only the | |
2270 | * pin/unpin/fence and not more. | |
2271 | */ | |
2272 | intel_runtime_pm_get(dev_priv); | |
2273 | ||
ce453d81 | 2274 | dev_priv->mm.interruptible = false; |
2da3b9b9 | 2275 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined); |
48b956c5 | 2276 | if (ret) |
ce453d81 | 2277 | goto err_interruptible; |
6b95a207 KH |
2278 | |
2279 | /* Install a fence for tiled scan-out. Pre-i965 always needs a | |
2280 | * fence, whereas 965+ only requires a fence if using | |
2281 | * framebuffer compression. For simplicity, we always install | |
2282 | * a fence as the cost is not that onerous. | |
2283 | */ | |
06d98131 | 2284 | ret = i915_gem_object_get_fence(obj); |
9a5a53b3 CW |
2285 | if (ret) |
2286 | goto err_unpin; | |
1690e1eb | 2287 | |
9a5a53b3 | 2288 | i915_gem_object_pin_fence(obj); |
6b95a207 | 2289 | |
ce453d81 | 2290 | dev_priv->mm.interruptible = true; |
d6dd6843 | 2291 | intel_runtime_pm_put(dev_priv); |
6b95a207 | 2292 | return 0; |
48b956c5 CW |
2293 | |
2294 | err_unpin: | |
cc98b413 | 2295 | i915_gem_object_unpin_from_display_plane(obj); |
ce453d81 CW |
2296 | err_interruptible: |
2297 | dev_priv->mm.interruptible = true; | |
d6dd6843 | 2298 | intel_runtime_pm_put(dev_priv); |
48b956c5 | 2299 | return ret; |
6b95a207 KH |
2300 | } |
2301 | ||
1690e1eb CW |
2302 | void intel_unpin_fb_obj(struct drm_i915_gem_object *obj) |
2303 | { | |
ebcdd39e MR |
2304 | WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex)); |
2305 | ||
1690e1eb | 2306 | i915_gem_object_unpin_fence(obj); |
cc98b413 | 2307 | i915_gem_object_unpin_from_display_plane(obj); |
1690e1eb CW |
2308 | } |
2309 | ||
c2c75131 DV |
2310 | /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel |
2311 | * is assumed to be a power-of-two. */ | |
bc752862 CW |
2312 | unsigned long intel_gen4_compute_page_offset(int *x, int *y, |
2313 | unsigned int tiling_mode, | |
2314 | unsigned int cpp, | |
2315 | unsigned int pitch) | |
c2c75131 | 2316 | { |
bc752862 CW |
2317 | if (tiling_mode != I915_TILING_NONE) { |
2318 | unsigned int tile_rows, tiles; | |
c2c75131 | 2319 | |
bc752862 CW |
2320 | tile_rows = *y / 8; |
2321 | *y %= 8; | |
c2c75131 | 2322 | |
bc752862 CW |
2323 | tiles = *x / (512/cpp); |
2324 | *x %= 512/cpp; | |
2325 | ||
2326 | return tile_rows * pitch * 8 + tiles * 4096; | |
2327 | } else { | |
2328 | unsigned int offset; | |
2329 | ||
2330 | offset = *y * pitch + *x * cpp; | |
2331 | *y = 0; | |
2332 | *x = (offset & 4095) / cpp; | |
2333 | return offset & -4096; | |
2334 | } | |
c2c75131 DV |
2335 | } |
2336 | ||
46f297fb JB |
2337 | int intel_format_to_fourcc(int format) |
2338 | { | |
2339 | switch (format) { | |
2340 | case DISPPLANE_8BPP: | |
2341 | return DRM_FORMAT_C8; | |
2342 | case DISPPLANE_BGRX555: | |
2343 | return DRM_FORMAT_XRGB1555; | |
2344 | case DISPPLANE_BGRX565: | |
2345 | return DRM_FORMAT_RGB565; | |
2346 | default: | |
2347 | case DISPPLANE_BGRX888: | |
2348 | return DRM_FORMAT_XRGB8888; | |
2349 | case DISPPLANE_RGBX888: | |
2350 | return DRM_FORMAT_XBGR8888; | |
2351 | case DISPPLANE_BGRX101010: | |
2352 | return DRM_FORMAT_XRGB2101010; | |
2353 | case DISPPLANE_RGBX101010: | |
2354 | return DRM_FORMAT_XBGR2101010; | |
2355 | } | |
2356 | } | |
2357 | ||
484b41dd | 2358 | static bool intel_alloc_plane_obj(struct intel_crtc *crtc, |
46f297fb JB |
2359 | struct intel_plane_config *plane_config) |
2360 | { | |
2361 | struct drm_device *dev = crtc->base.dev; | |
2362 | struct drm_i915_gem_object *obj = NULL; | |
2363 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; | |
2364 | u32 base = plane_config->base; | |
2365 | ||
ff2652ea CW |
2366 | if (plane_config->size == 0) |
2367 | return false; | |
2368 | ||
46f297fb JB |
2369 | obj = i915_gem_object_create_stolen_for_preallocated(dev, base, base, |
2370 | plane_config->size); | |
2371 | if (!obj) | |
484b41dd | 2372 | return false; |
46f297fb JB |
2373 | |
2374 | if (plane_config->tiled) { | |
2375 | obj->tiling_mode = I915_TILING_X; | |
66e514c1 | 2376 | obj->stride = crtc->base.primary->fb->pitches[0]; |
46f297fb JB |
2377 | } |
2378 | ||
66e514c1 DA |
2379 | mode_cmd.pixel_format = crtc->base.primary->fb->pixel_format; |
2380 | mode_cmd.width = crtc->base.primary->fb->width; | |
2381 | mode_cmd.height = crtc->base.primary->fb->height; | |
2382 | mode_cmd.pitches[0] = crtc->base.primary->fb->pitches[0]; | |
46f297fb JB |
2383 | |
2384 | mutex_lock(&dev->struct_mutex); | |
2385 | ||
66e514c1 | 2386 | if (intel_framebuffer_init(dev, to_intel_framebuffer(crtc->base.primary->fb), |
484b41dd | 2387 | &mode_cmd, obj)) { |
46f297fb JB |
2388 | DRM_DEBUG_KMS("intel fb init failed\n"); |
2389 | goto out_unref_obj; | |
2390 | } | |
2391 | ||
a071fa00 | 2392 | obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe); |
46f297fb | 2393 | mutex_unlock(&dev->struct_mutex); |
484b41dd JB |
2394 | |
2395 | DRM_DEBUG_KMS("plane fb obj %p\n", obj); | |
2396 | return true; | |
46f297fb JB |
2397 | |
2398 | out_unref_obj: | |
2399 | drm_gem_object_unreference(&obj->base); | |
2400 | mutex_unlock(&dev->struct_mutex); | |
484b41dd JB |
2401 | return false; |
2402 | } | |
2403 | ||
2404 | static void intel_find_plane_obj(struct intel_crtc *intel_crtc, | |
2405 | struct intel_plane_config *plane_config) | |
2406 | { | |
2407 | struct drm_device *dev = intel_crtc->base.dev; | |
2408 | struct drm_crtc *c; | |
2409 | struct intel_crtc *i; | |
2ff8fde1 | 2410 | struct drm_i915_gem_object *obj; |
484b41dd | 2411 | |
66e514c1 | 2412 | if (!intel_crtc->base.primary->fb) |
484b41dd JB |
2413 | return; |
2414 | ||
2415 | if (intel_alloc_plane_obj(intel_crtc, plane_config)) | |
2416 | return; | |
2417 | ||
66e514c1 DA |
2418 | kfree(intel_crtc->base.primary->fb); |
2419 | intel_crtc->base.primary->fb = NULL; | |
484b41dd JB |
2420 | |
2421 | /* | |
2422 | * Failed to alloc the obj, check to see if we should share | |
2423 | * an fb with another CRTC instead | |
2424 | */ | |
70e1e0ec | 2425 | for_each_crtc(dev, c) { |
484b41dd JB |
2426 | i = to_intel_crtc(c); |
2427 | ||
2428 | if (c == &intel_crtc->base) | |
2429 | continue; | |
2430 | ||
2ff8fde1 MR |
2431 | if (!i->active) |
2432 | continue; | |
2433 | ||
2434 | obj = intel_fb_obj(c->primary->fb); | |
2435 | if (obj == NULL) | |
484b41dd JB |
2436 | continue; |
2437 | ||
2ff8fde1 | 2438 | if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) { |
66e514c1 DA |
2439 | drm_framebuffer_reference(c->primary->fb); |
2440 | intel_crtc->base.primary->fb = c->primary->fb; | |
2ff8fde1 | 2441 | obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe); |
484b41dd JB |
2442 | break; |
2443 | } | |
2444 | } | |
46f297fb JB |
2445 | } |
2446 | ||
29b9bde6 DV |
2447 | static void i9xx_update_primary_plane(struct drm_crtc *crtc, |
2448 | struct drm_framebuffer *fb, | |
2449 | int x, int y) | |
81255565 JB |
2450 | { |
2451 | struct drm_device *dev = crtc->dev; | |
2452 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2453 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c9ba6fad | 2454 | struct drm_i915_gem_object *obj; |
81255565 | 2455 | int plane = intel_crtc->plane; |
e506a0c6 | 2456 | unsigned long linear_offset; |
81255565 | 2457 | u32 dspcntr; |
f45651ba | 2458 | u32 reg = DSPCNTR(plane); |
48404c1e | 2459 | int pixel_size; |
f45651ba | 2460 | |
fdd508a6 VS |
2461 | if (!intel_crtc->primary_enabled) { |
2462 | I915_WRITE(reg, 0); | |
2463 | if (INTEL_INFO(dev)->gen >= 4) | |
2464 | I915_WRITE(DSPSURF(plane), 0); | |
2465 | else | |
2466 | I915_WRITE(DSPADDR(plane), 0); | |
2467 | POSTING_READ(reg); | |
2468 | return; | |
2469 | } | |
2470 | ||
c9ba6fad VS |
2471 | obj = intel_fb_obj(fb); |
2472 | if (WARN_ON(obj == NULL)) | |
2473 | return; | |
2474 | ||
2475 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2476 | ||
f45651ba VS |
2477 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2478 | ||
fdd508a6 | 2479 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2480 | |
2481 | if (INTEL_INFO(dev)->gen < 4) { | |
2482 | if (intel_crtc->pipe == PIPE_B) | |
2483 | dspcntr |= DISPPLANE_SEL_PIPE_B; | |
2484 | ||
2485 | /* pipesrc and dspsize control the size that is scaled from, | |
2486 | * which should always be the user's requested size. | |
2487 | */ | |
2488 | I915_WRITE(DSPSIZE(plane), | |
2489 | ((intel_crtc->config.pipe_src_h - 1) << 16) | | |
2490 | (intel_crtc->config.pipe_src_w - 1)); | |
2491 | I915_WRITE(DSPPOS(plane), 0); | |
2492 | } | |
81255565 | 2493 | |
57779d06 VS |
2494 | switch (fb->pixel_format) { |
2495 | case DRM_FORMAT_C8: | |
81255565 JB |
2496 | dspcntr |= DISPPLANE_8BPP; |
2497 | break; | |
57779d06 VS |
2498 | case DRM_FORMAT_XRGB1555: |
2499 | case DRM_FORMAT_ARGB1555: | |
2500 | dspcntr |= DISPPLANE_BGRX555; | |
81255565 | 2501 | break; |
57779d06 VS |
2502 | case DRM_FORMAT_RGB565: |
2503 | dspcntr |= DISPPLANE_BGRX565; | |
2504 | break; | |
2505 | case DRM_FORMAT_XRGB8888: | |
2506 | case DRM_FORMAT_ARGB8888: | |
2507 | dspcntr |= DISPPLANE_BGRX888; | |
2508 | break; | |
2509 | case DRM_FORMAT_XBGR8888: | |
2510 | case DRM_FORMAT_ABGR8888: | |
2511 | dspcntr |= DISPPLANE_RGBX888; | |
2512 | break; | |
2513 | case DRM_FORMAT_XRGB2101010: | |
2514 | case DRM_FORMAT_ARGB2101010: | |
2515 | dspcntr |= DISPPLANE_BGRX101010; | |
2516 | break; | |
2517 | case DRM_FORMAT_XBGR2101010: | |
2518 | case DRM_FORMAT_ABGR2101010: | |
2519 | dspcntr |= DISPPLANE_RGBX101010; | |
81255565 JB |
2520 | break; |
2521 | default: | |
baba133a | 2522 | BUG(); |
81255565 | 2523 | } |
57779d06 | 2524 | |
f45651ba VS |
2525 | if (INTEL_INFO(dev)->gen >= 4 && |
2526 | obj->tiling_mode != I915_TILING_NONE) | |
2527 | dspcntr |= DISPPLANE_TILED; | |
81255565 | 2528 | |
de1aa629 VS |
2529 | if (IS_G4X(dev)) |
2530 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; | |
2531 | ||
b9897127 | 2532 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
81255565 | 2533 | |
c2c75131 DV |
2534 | if (INTEL_INFO(dev)->gen >= 4) { |
2535 | intel_crtc->dspaddr_offset = | |
bc752862 | 2536 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2537 | pixel_size, |
bc752862 | 2538 | fb->pitches[0]); |
c2c75131 DV |
2539 | linear_offset -= intel_crtc->dspaddr_offset; |
2540 | } else { | |
e506a0c6 | 2541 | intel_crtc->dspaddr_offset = linear_offset; |
c2c75131 | 2542 | } |
e506a0c6 | 2543 | |
48404c1e SJ |
2544 | if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) { |
2545 | dspcntr |= DISPPLANE_ROTATE_180; | |
2546 | ||
2547 | x += (intel_crtc->config.pipe_src_w - 1); | |
2548 | y += (intel_crtc->config.pipe_src_h - 1); | |
2549 | ||
2550 | /* Finding the last pixel of the last line of the display | |
2551 | data and adding to linear_offset*/ | |
2552 | linear_offset += | |
2553 | (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] + | |
2554 | (intel_crtc->config.pipe_src_w - 1) * pixel_size; | |
2555 | } | |
2556 | ||
2557 | I915_WRITE(reg, dspcntr); | |
2558 | ||
f343c5f6 BW |
2559 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2560 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2561 | fb->pitches[0]); | |
01f2c773 | 2562 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
a6c45cf0 | 2563 | if (INTEL_INFO(dev)->gen >= 4) { |
85ba7b7d DV |
2564 | I915_WRITE(DSPSURF(plane), |
2565 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
5eddb70b | 2566 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); |
e506a0c6 | 2567 | I915_WRITE(DSPLINOFF(plane), linear_offset); |
5eddb70b | 2568 | } else |
f343c5f6 | 2569 | I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset); |
5eddb70b | 2570 | POSTING_READ(reg); |
17638cd6 JB |
2571 | } |
2572 | ||
29b9bde6 DV |
2573 | static void ironlake_update_primary_plane(struct drm_crtc *crtc, |
2574 | struct drm_framebuffer *fb, | |
2575 | int x, int y) | |
17638cd6 JB |
2576 | { |
2577 | struct drm_device *dev = crtc->dev; | |
2578 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2579 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c9ba6fad | 2580 | struct drm_i915_gem_object *obj; |
17638cd6 | 2581 | int plane = intel_crtc->plane; |
e506a0c6 | 2582 | unsigned long linear_offset; |
17638cd6 | 2583 | u32 dspcntr; |
f45651ba | 2584 | u32 reg = DSPCNTR(plane); |
48404c1e | 2585 | int pixel_size; |
f45651ba | 2586 | |
fdd508a6 VS |
2587 | if (!intel_crtc->primary_enabled) { |
2588 | I915_WRITE(reg, 0); | |
2589 | I915_WRITE(DSPSURF(plane), 0); | |
2590 | POSTING_READ(reg); | |
2591 | return; | |
2592 | } | |
2593 | ||
c9ba6fad VS |
2594 | obj = intel_fb_obj(fb); |
2595 | if (WARN_ON(obj == NULL)) | |
2596 | return; | |
2597 | ||
2598 | pixel_size = drm_format_plane_cpp(fb->pixel_format, 0); | |
2599 | ||
f45651ba VS |
2600 | dspcntr = DISPPLANE_GAMMA_ENABLE; |
2601 | ||
fdd508a6 | 2602 | dspcntr |= DISPLAY_PLANE_ENABLE; |
f45651ba VS |
2603 | |
2604 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
2605 | dspcntr |= DISPPLANE_PIPE_CSC_ENABLE; | |
17638cd6 | 2606 | |
57779d06 VS |
2607 | switch (fb->pixel_format) { |
2608 | case DRM_FORMAT_C8: | |
17638cd6 JB |
2609 | dspcntr |= DISPPLANE_8BPP; |
2610 | break; | |
57779d06 VS |
2611 | case DRM_FORMAT_RGB565: |
2612 | dspcntr |= DISPPLANE_BGRX565; | |
17638cd6 | 2613 | break; |
57779d06 VS |
2614 | case DRM_FORMAT_XRGB8888: |
2615 | case DRM_FORMAT_ARGB8888: | |
2616 | dspcntr |= DISPPLANE_BGRX888; | |
2617 | break; | |
2618 | case DRM_FORMAT_XBGR8888: | |
2619 | case DRM_FORMAT_ABGR8888: | |
2620 | dspcntr |= DISPPLANE_RGBX888; | |
2621 | break; | |
2622 | case DRM_FORMAT_XRGB2101010: | |
2623 | case DRM_FORMAT_ARGB2101010: | |
2624 | dspcntr |= DISPPLANE_BGRX101010; | |
2625 | break; | |
2626 | case DRM_FORMAT_XBGR2101010: | |
2627 | case DRM_FORMAT_ABGR2101010: | |
2628 | dspcntr |= DISPPLANE_RGBX101010; | |
17638cd6 JB |
2629 | break; |
2630 | default: | |
baba133a | 2631 | BUG(); |
17638cd6 JB |
2632 | } |
2633 | ||
2634 | if (obj->tiling_mode != I915_TILING_NONE) | |
2635 | dspcntr |= DISPPLANE_TILED; | |
17638cd6 | 2636 | |
f45651ba | 2637 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) |
1f5d76db | 2638 | dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE; |
17638cd6 | 2639 | |
b9897127 | 2640 | linear_offset = y * fb->pitches[0] + x * pixel_size; |
c2c75131 | 2641 | intel_crtc->dspaddr_offset = |
bc752862 | 2642 | intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode, |
b9897127 | 2643 | pixel_size, |
bc752862 | 2644 | fb->pitches[0]); |
c2c75131 | 2645 | linear_offset -= intel_crtc->dspaddr_offset; |
48404c1e SJ |
2646 | if (to_intel_plane(crtc->primary)->rotation == BIT(DRM_ROTATE_180)) { |
2647 | dspcntr |= DISPPLANE_ROTATE_180; | |
2648 | ||
2649 | if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) { | |
2650 | x += (intel_crtc->config.pipe_src_w - 1); | |
2651 | y += (intel_crtc->config.pipe_src_h - 1); | |
2652 | ||
2653 | /* Finding the last pixel of the last line of the display | |
2654 | data and adding to linear_offset*/ | |
2655 | linear_offset += | |
2656 | (intel_crtc->config.pipe_src_h - 1) * fb->pitches[0] + | |
2657 | (intel_crtc->config.pipe_src_w - 1) * pixel_size; | |
2658 | } | |
2659 | } | |
2660 | ||
2661 | I915_WRITE(reg, dspcntr); | |
17638cd6 | 2662 | |
f343c5f6 BW |
2663 | DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n", |
2664 | i915_gem_obj_ggtt_offset(obj), linear_offset, x, y, | |
2665 | fb->pitches[0]); | |
01f2c773 | 2666 | I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]); |
85ba7b7d DV |
2667 | I915_WRITE(DSPSURF(plane), |
2668 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset); | |
b3dc685e | 2669 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
bc1c91eb DL |
2670 | I915_WRITE(DSPOFFSET(plane), (y << 16) | x); |
2671 | } else { | |
2672 | I915_WRITE(DSPTILEOFF(plane), (y << 16) | x); | |
2673 | I915_WRITE(DSPLINOFF(plane), linear_offset); | |
2674 | } | |
17638cd6 | 2675 | POSTING_READ(reg); |
17638cd6 JB |
2676 | } |
2677 | ||
2678 | /* Assume fb object is pinned & idle & fenced and just update base pointers */ | |
2679 | static int | |
2680 | intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb, | |
2681 | int x, int y, enum mode_set_atomic state) | |
2682 | { | |
2683 | struct drm_device *dev = crtc->dev; | |
2684 | struct drm_i915_private *dev_priv = dev->dev_private; | |
17638cd6 | 2685 | |
6b8e6ed0 CW |
2686 | if (dev_priv->display.disable_fbc) |
2687 | dev_priv->display.disable_fbc(dev); | |
cc36513c | 2688 | intel_increase_pllclock(dev, to_intel_crtc(crtc)->pipe); |
81255565 | 2689 | |
29b9bde6 DV |
2690 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
2691 | ||
2692 | return 0; | |
81255565 JB |
2693 | } |
2694 | ||
96a02917 VS |
2695 | void intel_display_handle_reset(struct drm_device *dev) |
2696 | { | |
2697 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2698 | struct drm_crtc *crtc; | |
2699 | ||
2700 | /* | |
2701 | * Flips in the rings have been nuked by the reset, | |
2702 | * so complete all pending flips so that user space | |
2703 | * will get its events and not get stuck. | |
2704 | * | |
2705 | * Also update the base address of all primary | |
2706 | * planes to the the last fb to make sure we're | |
2707 | * showing the correct fb after a reset. | |
2708 | * | |
2709 | * Need to make two loops over the crtcs so that we | |
2710 | * don't try to grab a crtc mutex before the | |
2711 | * pending_flip_queue really got woken up. | |
2712 | */ | |
2713 | ||
70e1e0ec | 2714 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2715 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2716 | enum plane plane = intel_crtc->plane; | |
2717 | ||
2718 | intel_prepare_page_flip(dev, plane); | |
2719 | intel_finish_page_flip_plane(dev, plane); | |
2720 | } | |
2721 | ||
70e1e0ec | 2722 | for_each_crtc(dev, crtc) { |
96a02917 VS |
2723 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2724 | ||
51fd371b | 2725 | drm_modeset_lock(&crtc->mutex, NULL); |
947fdaad CW |
2726 | /* |
2727 | * FIXME: Once we have proper support for primary planes (and | |
2728 | * disabling them without disabling the entire crtc) allow again | |
66e514c1 | 2729 | * a NULL crtc->primary->fb. |
947fdaad | 2730 | */ |
f4510a27 | 2731 | if (intel_crtc->active && crtc->primary->fb) |
262ca2b0 | 2732 | dev_priv->display.update_primary_plane(crtc, |
66e514c1 | 2733 | crtc->primary->fb, |
262ca2b0 MR |
2734 | crtc->x, |
2735 | crtc->y); | |
51fd371b | 2736 | drm_modeset_unlock(&crtc->mutex); |
96a02917 VS |
2737 | } |
2738 | } | |
2739 | ||
14667a4b CW |
2740 | static int |
2741 | intel_finish_fb(struct drm_framebuffer *old_fb) | |
2742 | { | |
2ff8fde1 | 2743 | struct drm_i915_gem_object *obj = intel_fb_obj(old_fb); |
14667a4b CW |
2744 | struct drm_i915_private *dev_priv = obj->base.dev->dev_private; |
2745 | bool was_interruptible = dev_priv->mm.interruptible; | |
2746 | int ret; | |
2747 | ||
14667a4b CW |
2748 | /* Big Hammer, we also need to ensure that any pending |
2749 | * MI_WAIT_FOR_EVENT inside a user batch buffer on the | |
2750 | * current scanout is retired before unpinning the old | |
2751 | * framebuffer. | |
2752 | * | |
2753 | * This should only fail upon a hung GPU, in which case we | |
2754 | * can safely continue. | |
2755 | */ | |
2756 | dev_priv->mm.interruptible = false; | |
2757 | ret = i915_gem_object_finish_gpu(obj); | |
2758 | dev_priv->mm.interruptible = was_interruptible; | |
2759 | ||
2760 | return ret; | |
2761 | } | |
2762 | ||
7d5e3799 CW |
2763 | static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc) |
2764 | { | |
2765 | struct drm_device *dev = crtc->dev; | |
2766 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2767 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2768 | unsigned long flags; | |
2769 | bool pending; | |
2770 | ||
2771 | if (i915_reset_in_progress(&dev_priv->gpu_error) || | |
2772 | intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter)) | |
2773 | return false; | |
2774 | ||
2775 | spin_lock_irqsave(&dev->event_lock, flags); | |
2776 | pending = to_intel_crtc(crtc)->unpin_work != NULL; | |
2777 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
2778 | ||
2779 | return pending; | |
2780 | } | |
2781 | ||
e30e8f75 GP |
2782 | static void intel_update_pipe_size(struct intel_crtc *crtc) |
2783 | { | |
2784 | struct drm_device *dev = crtc->base.dev; | |
2785 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2786 | const struct drm_display_mode *adjusted_mode; | |
2787 | ||
2788 | if (!i915.fastboot) | |
2789 | return; | |
2790 | ||
2791 | /* | |
2792 | * Update pipe size and adjust fitter if needed: the reason for this is | |
2793 | * that in compute_mode_changes we check the native mode (not the pfit | |
2794 | * mode) to see if we can flip rather than do a full mode set. In the | |
2795 | * fastboot case, we'll flip, but if we don't update the pipesrc and | |
2796 | * pfit state, we'll end up with a big fb scanned out into the wrong | |
2797 | * sized surface. | |
2798 | * | |
2799 | * To fix this properly, we need to hoist the checks up into | |
2800 | * compute_mode_changes (or above), check the actual pfit state and | |
2801 | * whether the platform allows pfit disable with pipe active, and only | |
2802 | * then update the pipesrc and pfit state, even on the flip path. | |
2803 | */ | |
2804 | ||
2805 | adjusted_mode = &crtc->config.adjusted_mode; | |
2806 | ||
2807 | I915_WRITE(PIPESRC(crtc->pipe), | |
2808 | ((adjusted_mode->crtc_hdisplay - 1) << 16) | | |
2809 | (adjusted_mode->crtc_vdisplay - 1)); | |
2810 | if (!crtc->config.pch_pfit.enabled && | |
2811 | (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) || | |
2812 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))) { | |
2813 | I915_WRITE(PF_CTL(crtc->pipe), 0); | |
2814 | I915_WRITE(PF_WIN_POS(crtc->pipe), 0); | |
2815 | I915_WRITE(PF_WIN_SZ(crtc->pipe), 0); | |
2816 | } | |
2817 | crtc->config.pipe_src_w = adjusted_mode->crtc_hdisplay; | |
2818 | crtc->config.pipe_src_h = adjusted_mode->crtc_vdisplay; | |
2819 | } | |
2820 | ||
5c3b82e2 | 2821 | static int |
3c4fdcfb | 2822 | intel_pipe_set_base(struct drm_crtc *crtc, int x, int y, |
94352cf9 | 2823 | struct drm_framebuffer *fb) |
79e53945 JB |
2824 | { |
2825 | struct drm_device *dev = crtc->dev; | |
6b8e6ed0 | 2826 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 2827 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
a071fa00 | 2828 | enum pipe pipe = intel_crtc->pipe; |
2ff8fde1 MR |
2829 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2830 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
2831 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb); | |
5c3b82e2 | 2832 | int ret; |
79e53945 | 2833 | |
7d5e3799 CW |
2834 | if (intel_crtc_has_pending_flip(crtc)) { |
2835 | DRM_ERROR("pipe is still busy with an old pageflip\n"); | |
2836 | return -EBUSY; | |
2837 | } | |
2838 | ||
79e53945 | 2839 | /* no fb bound */ |
94352cf9 | 2840 | if (!fb) { |
a5071c2f | 2841 | DRM_ERROR("No FB bound\n"); |
5c3b82e2 CW |
2842 | return 0; |
2843 | } | |
2844 | ||
7eb552ae | 2845 | if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) { |
84f44ce7 VS |
2846 | DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n", |
2847 | plane_name(intel_crtc->plane), | |
2848 | INTEL_INFO(dev)->num_pipes); | |
5c3b82e2 | 2849 | return -EINVAL; |
79e53945 JB |
2850 | } |
2851 | ||
5c3b82e2 | 2852 | mutex_lock(&dev->struct_mutex); |
a071fa00 DV |
2853 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
2854 | if (ret == 0) | |
91565c85 | 2855 | i915_gem_track_fb(old_obj, obj, |
a071fa00 | 2856 | INTEL_FRONTBUFFER_PRIMARY(pipe)); |
8ac36ec1 | 2857 | mutex_unlock(&dev->struct_mutex); |
5c3b82e2 | 2858 | if (ret != 0) { |
a5071c2f | 2859 | DRM_ERROR("pin & fence failed\n"); |
5c3b82e2 CW |
2860 | return ret; |
2861 | } | |
79e53945 | 2862 | |
e30e8f75 | 2863 | intel_update_pipe_size(intel_crtc); |
4d6a3e63 | 2864 | |
29b9bde6 | 2865 | dev_priv->display.update_primary_plane(crtc, fb, x, y); |
3c4fdcfb | 2866 | |
f99d7069 DV |
2867 | if (intel_crtc->active) |
2868 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); | |
2869 | ||
f4510a27 | 2870 | crtc->primary->fb = fb; |
6c4c86f5 DV |
2871 | crtc->x = x; |
2872 | crtc->y = y; | |
94352cf9 | 2873 | |
b7f1de28 | 2874 | if (old_fb) { |
d7697eea DV |
2875 | if (intel_crtc->active && old_fb != fb) |
2876 | intel_wait_for_vblank(dev, intel_crtc->pipe); | |
8ac36ec1 | 2877 | mutex_lock(&dev->struct_mutex); |
2ff8fde1 | 2878 | intel_unpin_fb_obj(old_obj); |
8ac36ec1 | 2879 | mutex_unlock(&dev->struct_mutex); |
b7f1de28 | 2880 | } |
652c393a | 2881 | |
8ac36ec1 | 2882 | mutex_lock(&dev->struct_mutex); |
6b8e6ed0 | 2883 | intel_update_fbc(dev); |
5c3b82e2 | 2884 | mutex_unlock(&dev->struct_mutex); |
79e53945 | 2885 | |
5c3b82e2 | 2886 | return 0; |
79e53945 JB |
2887 | } |
2888 | ||
5e84e1a4 ZW |
2889 | static void intel_fdi_normal_train(struct drm_crtc *crtc) |
2890 | { | |
2891 | struct drm_device *dev = crtc->dev; | |
2892 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2893 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2894 | int pipe = intel_crtc->pipe; | |
2895 | u32 reg, temp; | |
2896 | ||
2897 | /* enable normal train */ | |
2898 | reg = FDI_TX_CTL(pipe); | |
2899 | temp = I915_READ(reg); | |
61e499bf | 2900 | if (IS_IVYBRIDGE(dev)) { |
357555c0 JB |
2901 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
2902 | temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE; | |
61e499bf KP |
2903 | } else { |
2904 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2905 | temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE; | |
357555c0 | 2906 | } |
5e84e1a4 ZW |
2907 | I915_WRITE(reg, temp); |
2908 | ||
2909 | reg = FDI_RX_CTL(pipe); | |
2910 | temp = I915_READ(reg); | |
2911 | if (HAS_PCH_CPT(dev)) { | |
2912 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
2913 | temp |= FDI_LINK_TRAIN_NORMAL_CPT; | |
2914 | } else { | |
2915 | temp &= ~FDI_LINK_TRAIN_NONE; | |
2916 | temp |= FDI_LINK_TRAIN_NONE; | |
2917 | } | |
2918 | I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE); | |
2919 | ||
2920 | /* wait one idle pattern time */ | |
2921 | POSTING_READ(reg); | |
2922 | udelay(1000); | |
357555c0 JB |
2923 | |
2924 | /* IVB wants error correction enabled */ | |
2925 | if (IS_IVYBRIDGE(dev)) | |
2926 | I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE | | |
2927 | FDI_FE_ERRC_ENABLE); | |
5e84e1a4 ZW |
2928 | } |
2929 | ||
1fbc0d78 | 2930 | static bool pipe_has_enabled_pch(struct intel_crtc *crtc) |
1e833f40 | 2931 | { |
1fbc0d78 DV |
2932 | return crtc->base.enabled && crtc->active && |
2933 | crtc->config.has_pch_encoder; | |
1e833f40 DV |
2934 | } |
2935 | ||
01a415fd DV |
2936 | static void ivb_modeset_global_resources(struct drm_device *dev) |
2937 | { | |
2938 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2939 | struct intel_crtc *pipe_B_crtc = | |
2940 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
2941 | struct intel_crtc *pipe_C_crtc = | |
2942 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]); | |
2943 | uint32_t temp; | |
2944 | ||
1e833f40 DV |
2945 | /* |
2946 | * When everything is off disable fdi C so that we could enable fdi B | |
2947 | * with all lanes. Note that we don't care about enabled pipes without | |
2948 | * an enabled pch encoder. | |
2949 | */ | |
2950 | if (!pipe_has_enabled_pch(pipe_B_crtc) && | |
2951 | !pipe_has_enabled_pch(pipe_C_crtc)) { | |
01a415fd DV |
2952 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); |
2953 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
2954 | ||
2955 | temp = I915_READ(SOUTH_CHICKEN1); | |
2956 | temp &= ~FDI_BC_BIFURCATION_SELECT; | |
2957 | DRM_DEBUG_KMS("disabling fdi C rx\n"); | |
2958 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
2959 | } | |
2960 | } | |
2961 | ||
8db9d77b ZW |
2962 | /* The FDI link training functions for ILK/Ibexpeak. */ |
2963 | static void ironlake_fdi_link_train(struct drm_crtc *crtc) | |
2964 | { | |
2965 | struct drm_device *dev = crtc->dev; | |
2966 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2967 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2968 | int pipe = intel_crtc->pipe; | |
5eddb70b | 2969 | u32 reg, temp, tries; |
8db9d77b | 2970 | |
1c8562f6 | 2971 | /* FDI needs bits from pipe first */ |
0fc932b8 | 2972 | assert_pipe_enabled(dev_priv, pipe); |
0fc932b8 | 2973 | |
e1a44743 AJ |
2974 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
2975 | for train result */ | |
5eddb70b CW |
2976 | reg = FDI_RX_IMR(pipe); |
2977 | temp = I915_READ(reg); | |
e1a44743 AJ |
2978 | temp &= ~FDI_RX_SYMBOL_LOCK; |
2979 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
2980 | I915_WRITE(reg, temp); |
2981 | I915_READ(reg); | |
e1a44743 AJ |
2982 | udelay(150); |
2983 | ||
8db9d77b | 2984 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
2985 | reg = FDI_TX_CTL(pipe); |
2986 | temp = I915_READ(reg); | |
627eb5a3 DV |
2987 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
2988 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
2989 | temp &= ~FDI_LINK_TRAIN_NONE; |
2990 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b | 2991 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 2992 | |
5eddb70b CW |
2993 | reg = FDI_RX_CTL(pipe); |
2994 | temp = I915_READ(reg); | |
8db9d77b ZW |
2995 | temp &= ~FDI_LINK_TRAIN_NONE; |
2996 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
5eddb70b CW |
2997 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
2998 | ||
2999 | POSTING_READ(reg); | |
8db9d77b ZW |
3000 | udelay(150); |
3001 | ||
5b2adf89 | 3002 | /* Ironlake workaround, enable clock pointer after FDI enable*/ |
8f5718a6 DV |
3003 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
3004 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR | | |
3005 | FDI_RX_PHASE_SYNC_POINTER_EN); | |
5b2adf89 | 3006 | |
5eddb70b | 3007 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3008 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3009 | temp = I915_READ(reg); |
8db9d77b ZW |
3010 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3011 | ||
3012 | if ((temp & FDI_RX_BIT_LOCK)) { | |
3013 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
5eddb70b | 3014 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); |
8db9d77b ZW |
3015 | break; |
3016 | } | |
8db9d77b | 3017 | } |
e1a44743 | 3018 | if (tries == 5) |
5eddb70b | 3019 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3020 | |
3021 | /* Train 2 */ | |
5eddb70b CW |
3022 | reg = FDI_TX_CTL(pipe); |
3023 | temp = I915_READ(reg); | |
8db9d77b ZW |
3024 | temp &= ~FDI_LINK_TRAIN_NONE; |
3025 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3026 | I915_WRITE(reg, temp); |
8db9d77b | 3027 | |
5eddb70b CW |
3028 | reg = FDI_RX_CTL(pipe); |
3029 | temp = I915_READ(reg); | |
8db9d77b ZW |
3030 | temp &= ~FDI_LINK_TRAIN_NONE; |
3031 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
5eddb70b | 3032 | I915_WRITE(reg, temp); |
8db9d77b | 3033 | |
5eddb70b CW |
3034 | POSTING_READ(reg); |
3035 | udelay(150); | |
8db9d77b | 3036 | |
5eddb70b | 3037 | reg = FDI_RX_IIR(pipe); |
e1a44743 | 3038 | for (tries = 0; tries < 5; tries++) { |
5eddb70b | 3039 | temp = I915_READ(reg); |
8db9d77b ZW |
3040 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); |
3041 | ||
3042 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
5eddb70b | 3043 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); |
8db9d77b ZW |
3044 | DRM_DEBUG_KMS("FDI train 2 done.\n"); |
3045 | break; | |
3046 | } | |
8db9d77b | 3047 | } |
e1a44743 | 3048 | if (tries == 5) |
5eddb70b | 3049 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3050 | |
3051 | DRM_DEBUG_KMS("FDI train done\n"); | |
5c5313c8 | 3052 | |
8db9d77b ZW |
3053 | } |
3054 | ||
0206e353 | 3055 | static const int snb_b_fdi_train_param[] = { |
8db9d77b ZW |
3056 | FDI_LINK_TRAIN_400MV_0DB_SNB_B, |
3057 | FDI_LINK_TRAIN_400MV_6DB_SNB_B, | |
3058 | FDI_LINK_TRAIN_600MV_3_5DB_SNB_B, | |
3059 | FDI_LINK_TRAIN_800MV_0DB_SNB_B, | |
3060 | }; | |
3061 | ||
3062 | /* The FDI link training functions for SNB/Cougarpoint. */ | |
3063 | static void gen6_fdi_link_train(struct drm_crtc *crtc) | |
3064 | { | |
3065 | struct drm_device *dev = crtc->dev; | |
3066 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3067 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3068 | int pipe = intel_crtc->pipe; | |
fa37d39e | 3069 | u32 reg, temp, i, retry; |
8db9d77b | 3070 | |
e1a44743 AJ |
3071 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit |
3072 | for train result */ | |
5eddb70b CW |
3073 | reg = FDI_RX_IMR(pipe); |
3074 | temp = I915_READ(reg); | |
e1a44743 AJ |
3075 | temp &= ~FDI_RX_SYMBOL_LOCK; |
3076 | temp &= ~FDI_RX_BIT_LOCK; | |
5eddb70b CW |
3077 | I915_WRITE(reg, temp); |
3078 | ||
3079 | POSTING_READ(reg); | |
e1a44743 AJ |
3080 | udelay(150); |
3081 | ||
8db9d77b | 3082 | /* enable CPU FDI TX and PCH FDI RX */ |
5eddb70b CW |
3083 | reg = FDI_TX_CTL(pipe); |
3084 | temp = I915_READ(reg); | |
627eb5a3 DV |
3085 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
3086 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
8db9d77b ZW |
3087 | temp &= ~FDI_LINK_TRAIN_NONE; |
3088 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3089 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3090 | /* SNB-B */ | |
3091 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
5eddb70b | 3092 | I915_WRITE(reg, temp | FDI_TX_ENABLE); |
8db9d77b | 3093 | |
d74cf324 DV |
3094 | I915_WRITE(FDI_RX_MISC(pipe), |
3095 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
3096 | ||
5eddb70b CW |
3097 | reg = FDI_RX_CTL(pipe); |
3098 | temp = I915_READ(reg); | |
8db9d77b ZW |
3099 | if (HAS_PCH_CPT(dev)) { |
3100 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3101 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3102 | } else { | |
3103 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3104 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3105 | } | |
5eddb70b CW |
3106 | I915_WRITE(reg, temp | FDI_RX_ENABLE); |
3107 | ||
3108 | POSTING_READ(reg); | |
8db9d77b ZW |
3109 | udelay(150); |
3110 | ||
0206e353 | 3111 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3112 | reg = FDI_TX_CTL(pipe); |
3113 | temp = I915_READ(reg); | |
8db9d77b ZW |
3114 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3115 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3116 | I915_WRITE(reg, temp); |
3117 | ||
3118 | POSTING_READ(reg); | |
8db9d77b ZW |
3119 | udelay(500); |
3120 | ||
fa37d39e SP |
3121 | for (retry = 0; retry < 5; retry++) { |
3122 | reg = FDI_RX_IIR(pipe); | |
3123 | temp = I915_READ(reg); | |
3124 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3125 | if (temp & FDI_RX_BIT_LOCK) { | |
3126 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3127 | DRM_DEBUG_KMS("FDI train 1 done.\n"); | |
3128 | break; | |
3129 | } | |
3130 | udelay(50); | |
8db9d77b | 3131 | } |
fa37d39e SP |
3132 | if (retry < 5) |
3133 | break; | |
8db9d77b ZW |
3134 | } |
3135 | if (i == 4) | |
5eddb70b | 3136 | DRM_ERROR("FDI train 1 fail!\n"); |
8db9d77b ZW |
3137 | |
3138 | /* Train 2 */ | |
5eddb70b CW |
3139 | reg = FDI_TX_CTL(pipe); |
3140 | temp = I915_READ(reg); | |
8db9d77b ZW |
3141 | temp &= ~FDI_LINK_TRAIN_NONE; |
3142 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3143 | if (IS_GEN6(dev)) { | |
3144 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; | |
3145 | /* SNB-B */ | |
3146 | temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B; | |
3147 | } | |
5eddb70b | 3148 | I915_WRITE(reg, temp); |
8db9d77b | 3149 | |
5eddb70b CW |
3150 | reg = FDI_RX_CTL(pipe); |
3151 | temp = I915_READ(reg); | |
8db9d77b ZW |
3152 | if (HAS_PCH_CPT(dev)) { |
3153 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3154 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
3155 | } else { | |
3156 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3157 | temp |= FDI_LINK_TRAIN_PATTERN_2; | |
3158 | } | |
5eddb70b CW |
3159 | I915_WRITE(reg, temp); |
3160 | ||
3161 | POSTING_READ(reg); | |
8db9d77b ZW |
3162 | udelay(150); |
3163 | ||
0206e353 | 3164 | for (i = 0; i < 4; i++) { |
5eddb70b CW |
3165 | reg = FDI_TX_CTL(pipe); |
3166 | temp = I915_READ(reg); | |
8db9d77b ZW |
3167 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
3168 | temp |= snb_b_fdi_train_param[i]; | |
5eddb70b CW |
3169 | I915_WRITE(reg, temp); |
3170 | ||
3171 | POSTING_READ(reg); | |
8db9d77b ZW |
3172 | udelay(500); |
3173 | ||
fa37d39e SP |
3174 | for (retry = 0; retry < 5; retry++) { |
3175 | reg = FDI_RX_IIR(pipe); | |
3176 | temp = I915_READ(reg); | |
3177 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
3178 | if (temp & FDI_RX_SYMBOL_LOCK) { | |
3179 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3180 | DRM_DEBUG_KMS("FDI train 2 done.\n"); | |
3181 | break; | |
3182 | } | |
3183 | udelay(50); | |
8db9d77b | 3184 | } |
fa37d39e SP |
3185 | if (retry < 5) |
3186 | break; | |
8db9d77b ZW |
3187 | } |
3188 | if (i == 4) | |
5eddb70b | 3189 | DRM_ERROR("FDI train 2 fail!\n"); |
8db9d77b ZW |
3190 | |
3191 | DRM_DEBUG_KMS("FDI train done.\n"); | |
3192 | } | |
3193 | ||
357555c0 JB |
3194 | /* Manual link training for Ivy Bridge A0 parts */ |
3195 | static void ivb_manual_fdi_link_train(struct drm_crtc *crtc) | |
3196 | { | |
3197 | struct drm_device *dev = crtc->dev; | |
3198 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3199 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3200 | int pipe = intel_crtc->pipe; | |
139ccd3f | 3201 | u32 reg, temp, i, j; |
357555c0 JB |
3202 | |
3203 | /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit | |
3204 | for train result */ | |
3205 | reg = FDI_RX_IMR(pipe); | |
3206 | temp = I915_READ(reg); | |
3207 | temp &= ~FDI_RX_SYMBOL_LOCK; | |
3208 | temp &= ~FDI_RX_BIT_LOCK; | |
3209 | I915_WRITE(reg, temp); | |
3210 | ||
3211 | POSTING_READ(reg); | |
3212 | udelay(150); | |
3213 | ||
01a415fd DV |
3214 | DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n", |
3215 | I915_READ(FDI_RX_IIR(pipe))); | |
3216 | ||
139ccd3f JB |
3217 | /* Try each vswing and preemphasis setting twice before moving on */ |
3218 | for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) { | |
3219 | /* disable first in case we need to retry */ | |
3220 | reg = FDI_TX_CTL(pipe); | |
3221 | temp = I915_READ(reg); | |
3222 | temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB); | |
3223 | temp &= ~FDI_TX_ENABLE; | |
3224 | I915_WRITE(reg, temp); | |
357555c0 | 3225 | |
139ccd3f JB |
3226 | reg = FDI_RX_CTL(pipe); |
3227 | temp = I915_READ(reg); | |
3228 | temp &= ~FDI_LINK_TRAIN_AUTO; | |
3229 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3230 | temp &= ~FDI_RX_ENABLE; | |
3231 | I915_WRITE(reg, temp); | |
357555c0 | 3232 | |
139ccd3f | 3233 | /* enable CPU FDI TX and PCH FDI RX */ |
357555c0 JB |
3234 | reg = FDI_TX_CTL(pipe); |
3235 | temp = I915_READ(reg); | |
139ccd3f JB |
3236 | temp &= ~FDI_DP_PORT_WIDTH_MASK; |
3237 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
3238 | temp |= FDI_LINK_TRAIN_PATTERN_1_IVB; | |
357555c0 | 3239 | temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK; |
139ccd3f JB |
3240 | temp |= snb_b_fdi_train_param[j/2]; |
3241 | temp |= FDI_COMPOSITE_SYNC; | |
3242 | I915_WRITE(reg, temp | FDI_TX_ENABLE); | |
357555c0 | 3243 | |
139ccd3f JB |
3244 | I915_WRITE(FDI_RX_MISC(pipe), |
3245 | FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90); | |
357555c0 | 3246 | |
139ccd3f | 3247 | reg = FDI_RX_CTL(pipe); |
357555c0 | 3248 | temp = I915_READ(reg); |
139ccd3f JB |
3249 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; |
3250 | temp |= FDI_COMPOSITE_SYNC; | |
3251 | I915_WRITE(reg, temp | FDI_RX_ENABLE); | |
357555c0 | 3252 | |
139ccd3f JB |
3253 | POSTING_READ(reg); |
3254 | udelay(1); /* should be 0.5us */ | |
357555c0 | 3255 | |
139ccd3f JB |
3256 | for (i = 0; i < 4; i++) { |
3257 | reg = FDI_RX_IIR(pipe); | |
3258 | temp = I915_READ(reg); | |
3259 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3260 | |
139ccd3f JB |
3261 | if (temp & FDI_RX_BIT_LOCK || |
3262 | (I915_READ(reg) & FDI_RX_BIT_LOCK)) { | |
3263 | I915_WRITE(reg, temp | FDI_RX_BIT_LOCK); | |
3264 | DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", | |
3265 | i); | |
3266 | break; | |
3267 | } | |
3268 | udelay(1); /* should be 0.5us */ | |
3269 | } | |
3270 | if (i == 4) { | |
3271 | DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2); | |
3272 | continue; | |
3273 | } | |
357555c0 | 3274 | |
139ccd3f | 3275 | /* Train 2 */ |
357555c0 JB |
3276 | reg = FDI_TX_CTL(pipe); |
3277 | temp = I915_READ(reg); | |
139ccd3f JB |
3278 | temp &= ~FDI_LINK_TRAIN_NONE_IVB; |
3279 | temp |= FDI_LINK_TRAIN_PATTERN_2_IVB; | |
3280 | I915_WRITE(reg, temp); | |
3281 | ||
3282 | reg = FDI_RX_CTL(pipe); | |
3283 | temp = I915_READ(reg); | |
3284 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3285 | temp |= FDI_LINK_TRAIN_PATTERN_2_CPT; | |
357555c0 JB |
3286 | I915_WRITE(reg, temp); |
3287 | ||
3288 | POSTING_READ(reg); | |
139ccd3f | 3289 | udelay(2); /* should be 1.5us */ |
357555c0 | 3290 | |
139ccd3f JB |
3291 | for (i = 0; i < 4; i++) { |
3292 | reg = FDI_RX_IIR(pipe); | |
3293 | temp = I915_READ(reg); | |
3294 | DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp); | |
357555c0 | 3295 | |
139ccd3f JB |
3296 | if (temp & FDI_RX_SYMBOL_LOCK || |
3297 | (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) { | |
3298 | I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK); | |
3299 | DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", | |
3300 | i); | |
3301 | goto train_done; | |
3302 | } | |
3303 | udelay(2); /* should be 1.5us */ | |
357555c0 | 3304 | } |
139ccd3f JB |
3305 | if (i == 4) |
3306 | DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2); | |
357555c0 | 3307 | } |
357555c0 | 3308 | |
139ccd3f | 3309 | train_done: |
357555c0 JB |
3310 | DRM_DEBUG_KMS("FDI train done.\n"); |
3311 | } | |
3312 | ||
88cefb6c | 3313 | static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc) |
2c07245f | 3314 | { |
88cefb6c | 3315 | struct drm_device *dev = intel_crtc->base.dev; |
2c07245f | 3316 | struct drm_i915_private *dev_priv = dev->dev_private; |
2c07245f | 3317 | int pipe = intel_crtc->pipe; |
5eddb70b | 3318 | u32 reg, temp; |
79e53945 | 3319 | |
c64e311e | 3320 | |
c98e9dcf | 3321 | /* enable PCH FDI RX PLL, wait warmup plus DMI latency */ |
5eddb70b CW |
3322 | reg = FDI_RX_CTL(pipe); |
3323 | temp = I915_READ(reg); | |
627eb5a3 DV |
3324 | temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16)); |
3325 | temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes); | |
dfd07d72 | 3326 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
5eddb70b CW |
3327 | I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE); |
3328 | ||
3329 | POSTING_READ(reg); | |
c98e9dcf JB |
3330 | udelay(200); |
3331 | ||
3332 | /* Switch from Rawclk to PCDclk */ | |
5eddb70b CW |
3333 | temp = I915_READ(reg); |
3334 | I915_WRITE(reg, temp | FDI_PCDCLK); | |
3335 | ||
3336 | POSTING_READ(reg); | |
c98e9dcf JB |
3337 | udelay(200); |
3338 | ||
20749730 PZ |
3339 | /* Enable CPU FDI TX PLL, always on for Ironlake */ |
3340 | reg = FDI_TX_CTL(pipe); | |
3341 | temp = I915_READ(reg); | |
3342 | if ((temp & FDI_TX_PLL_ENABLE) == 0) { | |
3343 | I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE); | |
5eddb70b | 3344 | |
20749730 PZ |
3345 | POSTING_READ(reg); |
3346 | udelay(100); | |
6be4a607 | 3347 | } |
0e23b99d JB |
3348 | } |
3349 | ||
88cefb6c DV |
3350 | static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc) |
3351 | { | |
3352 | struct drm_device *dev = intel_crtc->base.dev; | |
3353 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3354 | int pipe = intel_crtc->pipe; | |
3355 | u32 reg, temp; | |
3356 | ||
3357 | /* Switch from PCDclk to Rawclk */ | |
3358 | reg = FDI_RX_CTL(pipe); | |
3359 | temp = I915_READ(reg); | |
3360 | I915_WRITE(reg, temp & ~FDI_PCDCLK); | |
3361 | ||
3362 | /* Disable CPU FDI TX PLL */ | |
3363 | reg = FDI_TX_CTL(pipe); | |
3364 | temp = I915_READ(reg); | |
3365 | I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE); | |
3366 | ||
3367 | POSTING_READ(reg); | |
3368 | udelay(100); | |
3369 | ||
3370 | reg = FDI_RX_CTL(pipe); | |
3371 | temp = I915_READ(reg); | |
3372 | I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE); | |
3373 | ||
3374 | /* Wait for the clocks to turn off. */ | |
3375 | POSTING_READ(reg); | |
3376 | udelay(100); | |
3377 | } | |
3378 | ||
0fc932b8 JB |
3379 | static void ironlake_fdi_disable(struct drm_crtc *crtc) |
3380 | { | |
3381 | struct drm_device *dev = crtc->dev; | |
3382 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3383 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3384 | int pipe = intel_crtc->pipe; | |
3385 | u32 reg, temp; | |
3386 | ||
3387 | /* disable CPU FDI tx and PCH FDI rx */ | |
3388 | reg = FDI_TX_CTL(pipe); | |
3389 | temp = I915_READ(reg); | |
3390 | I915_WRITE(reg, temp & ~FDI_TX_ENABLE); | |
3391 | POSTING_READ(reg); | |
3392 | ||
3393 | reg = FDI_RX_CTL(pipe); | |
3394 | temp = I915_READ(reg); | |
3395 | temp &= ~(0x7 << 16); | |
dfd07d72 | 3396 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3397 | I915_WRITE(reg, temp & ~FDI_RX_ENABLE); |
3398 | ||
3399 | POSTING_READ(reg); | |
3400 | udelay(100); | |
3401 | ||
3402 | /* Ironlake workaround, disable clock pointer after downing FDI */ | |
eba905b2 | 3403 | if (HAS_PCH_IBX(dev)) |
6f06ce18 | 3404 | I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR); |
0fc932b8 JB |
3405 | |
3406 | /* still set train pattern 1 */ | |
3407 | reg = FDI_TX_CTL(pipe); | |
3408 | temp = I915_READ(reg); | |
3409 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3410 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3411 | I915_WRITE(reg, temp); | |
3412 | ||
3413 | reg = FDI_RX_CTL(pipe); | |
3414 | temp = I915_READ(reg); | |
3415 | if (HAS_PCH_CPT(dev)) { | |
3416 | temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT; | |
3417 | temp |= FDI_LINK_TRAIN_PATTERN_1_CPT; | |
3418 | } else { | |
3419 | temp &= ~FDI_LINK_TRAIN_NONE; | |
3420 | temp |= FDI_LINK_TRAIN_PATTERN_1; | |
3421 | } | |
3422 | /* BPC in FDI rx is consistent with that in PIPECONF */ | |
3423 | temp &= ~(0x07 << 16); | |
dfd07d72 | 3424 | temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11; |
0fc932b8 JB |
3425 | I915_WRITE(reg, temp); |
3426 | ||
3427 | POSTING_READ(reg); | |
3428 | udelay(100); | |
3429 | } | |
3430 | ||
5dce5b93 CW |
3431 | bool intel_has_pending_fb_unpin(struct drm_device *dev) |
3432 | { | |
3433 | struct intel_crtc *crtc; | |
3434 | ||
3435 | /* Note that we don't need to be called with mode_config.lock here | |
3436 | * as our list of CRTC objects is static for the lifetime of the | |
3437 | * device and so cannot disappear as we iterate. Similarly, we can | |
3438 | * happily treat the predicates as racy, atomic checks as userspace | |
3439 | * cannot claim and pin a new fb without at least acquring the | |
3440 | * struct_mutex and so serialising with us. | |
3441 | */ | |
d3fcc808 | 3442 | for_each_intel_crtc(dev, crtc) { |
5dce5b93 CW |
3443 | if (atomic_read(&crtc->unpin_work_count) == 0) |
3444 | continue; | |
3445 | ||
3446 | if (crtc->unpin_work) | |
3447 | intel_wait_for_vblank(dev, crtc->pipe); | |
3448 | ||
3449 | return true; | |
3450 | } | |
3451 | ||
3452 | return false; | |
3453 | } | |
3454 | ||
d6bbafa1 CW |
3455 | static void page_flip_completed(struct intel_crtc *intel_crtc) |
3456 | { | |
3457 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); | |
3458 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
3459 | ||
3460 | /* ensure that the unpin work is consistent wrt ->pending. */ | |
3461 | smp_rmb(); | |
3462 | intel_crtc->unpin_work = NULL; | |
3463 | ||
3464 | if (work->event) | |
3465 | drm_send_vblank_event(intel_crtc->base.dev, | |
3466 | intel_crtc->pipe, | |
3467 | work->event); | |
3468 | ||
3469 | drm_crtc_vblank_put(&intel_crtc->base); | |
3470 | ||
3471 | wake_up_all(&dev_priv->pending_flip_queue); | |
3472 | queue_work(dev_priv->wq, &work->work); | |
3473 | ||
3474 | trace_i915_flip_complete(intel_crtc->plane, | |
3475 | work->pending_flip_obj); | |
3476 | } | |
3477 | ||
46a55d30 | 3478 | void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc) |
e6c3a2a6 | 3479 | { |
0f91128d | 3480 | struct drm_device *dev = crtc->dev; |
5bb61643 | 3481 | struct drm_i915_private *dev_priv = dev->dev_private; |
e6c3a2a6 | 3482 | |
2c10d571 | 3483 | WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue)); |
9c787942 CW |
3484 | if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue, |
3485 | !intel_crtc_has_pending_flip(crtc), | |
3486 | 60*HZ) == 0)) { | |
3487 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3488 | unsigned long flags; | |
2c10d571 | 3489 | |
9c787942 CW |
3490 | spin_lock_irqsave(&dev->event_lock, flags); |
3491 | if (intel_crtc->unpin_work) { | |
3492 | WARN_ONCE(1, "Removing stuck page flip\n"); | |
3493 | page_flip_completed(intel_crtc); | |
3494 | } | |
3495 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
3496 | } | |
5bb61643 | 3497 | |
975d568a CW |
3498 | if (crtc->primary->fb) { |
3499 | mutex_lock(&dev->struct_mutex); | |
3500 | intel_finish_fb(crtc->primary->fb); | |
3501 | mutex_unlock(&dev->struct_mutex); | |
3502 | } | |
e6c3a2a6 CW |
3503 | } |
3504 | ||
e615efe4 ED |
3505 | /* Program iCLKIP clock to the desired frequency */ |
3506 | static void lpt_program_iclkip(struct drm_crtc *crtc) | |
3507 | { | |
3508 | struct drm_device *dev = crtc->dev; | |
3509 | struct drm_i915_private *dev_priv = dev->dev_private; | |
241bfc38 | 3510 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
e615efe4 ED |
3511 | u32 divsel, phaseinc, auxdiv, phasedir = 0; |
3512 | u32 temp; | |
3513 | ||
09153000 DV |
3514 | mutex_lock(&dev_priv->dpio_lock); |
3515 | ||
e615efe4 ED |
3516 | /* It is necessary to ungate the pixclk gate prior to programming |
3517 | * the divisors, and gate it back when it is done. | |
3518 | */ | |
3519 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE); | |
3520 | ||
3521 | /* Disable SSCCTL */ | |
3522 | intel_sbi_write(dev_priv, SBI_SSCCTL6, | |
988d6ee8 PZ |
3523 | intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) | |
3524 | SBI_SSCCTL_DISABLE, | |
3525 | SBI_ICLK); | |
e615efe4 ED |
3526 | |
3527 | /* 20MHz is a corner case which is out of range for the 7-bit divisor */ | |
12d7ceed | 3528 | if (clock == 20000) { |
e615efe4 ED |
3529 | auxdiv = 1; |
3530 | divsel = 0x41; | |
3531 | phaseinc = 0x20; | |
3532 | } else { | |
3533 | /* The iCLK virtual clock root frequency is in MHz, | |
241bfc38 DL |
3534 | * but the adjusted_mode->crtc_clock in in KHz. To get the |
3535 | * divisors, it is necessary to divide one by another, so we | |
e615efe4 ED |
3536 | * convert the virtual clock precision to KHz here for higher |
3537 | * precision. | |
3538 | */ | |
3539 | u32 iclk_virtual_root_freq = 172800 * 1000; | |
3540 | u32 iclk_pi_range = 64; | |
3541 | u32 desired_divisor, msb_divisor_value, pi_value; | |
3542 | ||
12d7ceed | 3543 | desired_divisor = (iclk_virtual_root_freq / clock); |
e615efe4 ED |
3544 | msb_divisor_value = desired_divisor / iclk_pi_range; |
3545 | pi_value = desired_divisor % iclk_pi_range; | |
3546 | ||
3547 | auxdiv = 0; | |
3548 | divsel = msb_divisor_value - 2; | |
3549 | phaseinc = pi_value; | |
3550 | } | |
3551 | ||
3552 | /* This should not happen with any sane values */ | |
3553 | WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) & | |
3554 | ~SBI_SSCDIVINTPHASE_DIVSEL_MASK); | |
3555 | WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) & | |
3556 | ~SBI_SSCDIVINTPHASE_INCVAL_MASK); | |
3557 | ||
3558 | DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n", | |
12d7ceed | 3559 | clock, |
e615efe4 ED |
3560 | auxdiv, |
3561 | divsel, | |
3562 | phasedir, | |
3563 | phaseinc); | |
3564 | ||
3565 | /* Program SSCDIVINTPHASE6 */ | |
988d6ee8 | 3566 | temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK); |
e615efe4 ED |
3567 | temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK; |
3568 | temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel); | |
3569 | temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK; | |
3570 | temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc); | |
3571 | temp |= SBI_SSCDIVINTPHASE_DIR(phasedir); | |
3572 | temp |= SBI_SSCDIVINTPHASE_PROPAGATE; | |
988d6ee8 | 3573 | intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK); |
e615efe4 ED |
3574 | |
3575 | /* Program SSCAUXDIV */ | |
988d6ee8 | 3576 | temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); |
e615efe4 ED |
3577 | temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1); |
3578 | temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv); | |
988d6ee8 | 3579 | intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK); |
e615efe4 ED |
3580 | |
3581 | /* Enable modulator and associated divider */ | |
988d6ee8 | 3582 | temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); |
e615efe4 | 3583 | temp &= ~SBI_SSCCTL_DISABLE; |
988d6ee8 | 3584 | intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK); |
e615efe4 ED |
3585 | |
3586 | /* Wait for initialization time */ | |
3587 | udelay(24); | |
3588 | ||
3589 | I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); | |
09153000 DV |
3590 | |
3591 | mutex_unlock(&dev_priv->dpio_lock); | |
e615efe4 ED |
3592 | } |
3593 | ||
275f01b2 DV |
3594 | static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc, |
3595 | enum pipe pch_transcoder) | |
3596 | { | |
3597 | struct drm_device *dev = crtc->base.dev; | |
3598 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3599 | enum transcoder cpu_transcoder = crtc->config.cpu_transcoder; | |
3600 | ||
3601 | I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder), | |
3602 | I915_READ(HTOTAL(cpu_transcoder))); | |
3603 | I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder), | |
3604 | I915_READ(HBLANK(cpu_transcoder))); | |
3605 | I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder), | |
3606 | I915_READ(HSYNC(cpu_transcoder))); | |
3607 | ||
3608 | I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder), | |
3609 | I915_READ(VTOTAL(cpu_transcoder))); | |
3610 | I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder), | |
3611 | I915_READ(VBLANK(cpu_transcoder))); | |
3612 | I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder), | |
3613 | I915_READ(VSYNC(cpu_transcoder))); | |
3614 | I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder), | |
3615 | I915_READ(VSYNCSHIFT(cpu_transcoder))); | |
3616 | } | |
3617 | ||
1fbc0d78 DV |
3618 | static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev) |
3619 | { | |
3620 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3621 | uint32_t temp; | |
3622 | ||
3623 | temp = I915_READ(SOUTH_CHICKEN1); | |
3624 | if (temp & FDI_BC_BIFURCATION_SELECT) | |
3625 | return; | |
3626 | ||
3627 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE); | |
3628 | WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE); | |
3629 | ||
3630 | temp |= FDI_BC_BIFURCATION_SELECT; | |
3631 | DRM_DEBUG_KMS("enabling fdi C rx\n"); | |
3632 | I915_WRITE(SOUTH_CHICKEN1, temp); | |
3633 | POSTING_READ(SOUTH_CHICKEN1); | |
3634 | } | |
3635 | ||
3636 | static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc) | |
3637 | { | |
3638 | struct drm_device *dev = intel_crtc->base.dev; | |
3639 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3640 | ||
3641 | switch (intel_crtc->pipe) { | |
3642 | case PIPE_A: | |
3643 | break; | |
3644 | case PIPE_B: | |
3645 | if (intel_crtc->config.fdi_lanes > 2) | |
3646 | WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT); | |
3647 | else | |
3648 | cpt_enable_fdi_bc_bifurcation(dev); | |
3649 | ||
3650 | break; | |
3651 | case PIPE_C: | |
3652 | cpt_enable_fdi_bc_bifurcation(dev); | |
3653 | ||
3654 | break; | |
3655 | default: | |
3656 | BUG(); | |
3657 | } | |
3658 | } | |
3659 | ||
f67a559d JB |
3660 | /* |
3661 | * Enable PCH resources required for PCH ports: | |
3662 | * - PCH PLLs | |
3663 | * - FDI training & RX/TX | |
3664 | * - update transcoder timings | |
3665 | * - DP transcoding bits | |
3666 | * - transcoder | |
3667 | */ | |
3668 | static void ironlake_pch_enable(struct drm_crtc *crtc) | |
0e23b99d JB |
3669 | { |
3670 | struct drm_device *dev = crtc->dev; | |
3671 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3672 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3673 | int pipe = intel_crtc->pipe; | |
ee7b9f93 | 3674 | u32 reg, temp; |
2c07245f | 3675 | |
ab9412ba | 3676 | assert_pch_transcoder_disabled(dev_priv, pipe); |
e7e164db | 3677 | |
1fbc0d78 DV |
3678 | if (IS_IVYBRIDGE(dev)) |
3679 | ivybridge_update_fdi_bc_bifurcation(intel_crtc); | |
3680 | ||
cd986abb DV |
3681 | /* Write the TU size bits before fdi link training, so that error |
3682 | * detection works. */ | |
3683 | I915_WRITE(FDI_RX_TUSIZE1(pipe), | |
3684 | I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK); | |
3685 | ||
c98e9dcf | 3686 | /* For PCH output, training FDI link */ |
674cf967 | 3687 | dev_priv->display.fdi_link_train(crtc); |
2c07245f | 3688 | |
3ad8a208 DV |
3689 | /* We need to program the right clock selection before writing the pixel |
3690 | * mutliplier into the DPLL. */ | |
303b81e0 | 3691 | if (HAS_PCH_CPT(dev)) { |
ee7b9f93 | 3692 | u32 sel; |
4b645f14 | 3693 | |
c98e9dcf | 3694 | temp = I915_READ(PCH_DPLL_SEL); |
11887397 DV |
3695 | temp |= TRANS_DPLL_ENABLE(pipe); |
3696 | sel = TRANS_DPLLB_SEL(pipe); | |
a43f6e0f | 3697 | if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B) |
ee7b9f93 JB |
3698 | temp |= sel; |
3699 | else | |
3700 | temp &= ~sel; | |
c98e9dcf | 3701 | I915_WRITE(PCH_DPLL_SEL, temp); |
c98e9dcf | 3702 | } |
5eddb70b | 3703 | |
3ad8a208 DV |
3704 | /* XXX: pch pll's can be enabled any time before we enable the PCH |
3705 | * transcoder, and we actually should do this to not upset any PCH | |
3706 | * transcoder that already use the clock when we share it. | |
3707 | * | |
3708 | * Note that enable_shared_dpll tries to do the right thing, but | |
3709 | * get_shared_dpll unconditionally resets the pll - we need that to have | |
3710 | * the right LVDS enable sequence. */ | |
85b3894f | 3711 | intel_enable_shared_dpll(intel_crtc); |
3ad8a208 | 3712 | |
d9b6cb56 JB |
3713 | /* set transcoder timing, panel must allow it */ |
3714 | assert_panel_unlocked(dev_priv, pipe); | |
275f01b2 | 3715 | ironlake_pch_transcoder_set_timings(intel_crtc, pipe); |
8db9d77b | 3716 | |
303b81e0 | 3717 | intel_fdi_normal_train(crtc); |
5e84e1a4 | 3718 | |
c98e9dcf JB |
3719 | /* For PCH DP, enable TRANS_DP_CTL */ |
3720 | if (HAS_PCH_CPT(dev) && | |
417e822d KP |
3721 | (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) || |
3722 | intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) { | |
dfd07d72 | 3723 | u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5; |
5eddb70b CW |
3724 | reg = TRANS_DP_CTL(pipe); |
3725 | temp = I915_READ(reg); | |
3726 | temp &= ~(TRANS_DP_PORT_SEL_MASK | | |
220cad3c EA |
3727 | TRANS_DP_SYNC_MASK | |
3728 | TRANS_DP_BPC_MASK); | |
5eddb70b CW |
3729 | temp |= (TRANS_DP_OUTPUT_ENABLE | |
3730 | TRANS_DP_ENH_FRAMING); | |
9325c9f0 | 3731 | temp |= bpc << 9; /* same format but at 11:9 */ |
c98e9dcf JB |
3732 | |
3733 | if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC) | |
5eddb70b | 3734 | temp |= TRANS_DP_HSYNC_ACTIVE_HIGH; |
c98e9dcf | 3735 | if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC) |
5eddb70b | 3736 | temp |= TRANS_DP_VSYNC_ACTIVE_HIGH; |
c98e9dcf JB |
3737 | |
3738 | switch (intel_trans_dp_port_sel(crtc)) { | |
3739 | case PCH_DP_B: | |
5eddb70b | 3740 | temp |= TRANS_DP_PORT_SEL_B; |
c98e9dcf JB |
3741 | break; |
3742 | case PCH_DP_C: | |
5eddb70b | 3743 | temp |= TRANS_DP_PORT_SEL_C; |
c98e9dcf JB |
3744 | break; |
3745 | case PCH_DP_D: | |
5eddb70b | 3746 | temp |= TRANS_DP_PORT_SEL_D; |
c98e9dcf JB |
3747 | break; |
3748 | default: | |
e95d41e1 | 3749 | BUG(); |
32f9d658 | 3750 | } |
2c07245f | 3751 | |
5eddb70b | 3752 | I915_WRITE(reg, temp); |
6be4a607 | 3753 | } |
b52eb4dc | 3754 | |
b8a4f404 | 3755 | ironlake_enable_pch_transcoder(dev_priv, pipe); |
f67a559d JB |
3756 | } |
3757 | ||
1507e5bd PZ |
3758 | static void lpt_pch_enable(struct drm_crtc *crtc) |
3759 | { | |
3760 | struct drm_device *dev = crtc->dev; | |
3761 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3762 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3b117c8f | 3763 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
1507e5bd | 3764 | |
ab9412ba | 3765 | assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A); |
1507e5bd | 3766 | |
8c52b5e8 | 3767 | lpt_program_iclkip(crtc); |
1507e5bd | 3768 | |
0540e488 | 3769 | /* Set transcoder timing. */ |
275f01b2 | 3770 | ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A); |
1507e5bd | 3771 | |
937bb610 | 3772 | lpt_enable_pch_transcoder(dev_priv, cpu_transcoder); |
f67a559d JB |
3773 | } |
3774 | ||
716c2e55 | 3775 | void intel_put_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3776 | { |
e2b78267 | 3777 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); |
ee7b9f93 JB |
3778 | |
3779 | if (pll == NULL) | |
3780 | return; | |
3781 | ||
3782 | if (pll->refcount == 0) { | |
46edb027 | 3783 | WARN(1, "bad %s refcount\n", pll->name); |
ee7b9f93 JB |
3784 | return; |
3785 | } | |
3786 | ||
f4a091c7 DV |
3787 | if (--pll->refcount == 0) { |
3788 | WARN_ON(pll->on); | |
3789 | WARN_ON(pll->active); | |
3790 | } | |
3791 | ||
a43f6e0f | 3792 | crtc->config.shared_dpll = DPLL_ID_PRIVATE; |
ee7b9f93 JB |
3793 | } |
3794 | ||
716c2e55 | 3795 | struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc) |
ee7b9f93 | 3796 | { |
e2b78267 DV |
3797 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; |
3798 | struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc); | |
3799 | enum intel_dpll_id i; | |
ee7b9f93 | 3800 | |
ee7b9f93 | 3801 | if (pll) { |
46edb027 DV |
3802 | DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n", |
3803 | crtc->base.base.id, pll->name); | |
e2b78267 | 3804 | intel_put_shared_dpll(crtc); |
ee7b9f93 JB |
3805 | } |
3806 | ||
98b6bd99 DV |
3807 | if (HAS_PCH_IBX(dev_priv->dev)) { |
3808 | /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */ | |
d94ab068 | 3809 | i = (enum intel_dpll_id) crtc->pipe; |
e72f9fbf | 3810 | pll = &dev_priv->shared_dplls[i]; |
98b6bd99 | 3811 | |
46edb027 DV |
3812 | DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n", |
3813 | crtc->base.base.id, pll->name); | |
98b6bd99 | 3814 | |
f2a69f44 DV |
3815 | WARN_ON(pll->refcount); |
3816 | ||
98b6bd99 DV |
3817 | goto found; |
3818 | } | |
3819 | ||
e72f9fbf DV |
3820 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3821 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 JB |
3822 | |
3823 | /* Only want to check enabled timings first */ | |
3824 | if (pll->refcount == 0) | |
3825 | continue; | |
3826 | ||
b89a1d39 DV |
3827 | if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state, |
3828 | sizeof(pll->hw_state)) == 0) { | |
46edb027 | 3829 | DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n", |
e2b78267 | 3830 | crtc->base.base.id, |
46edb027 | 3831 | pll->name, pll->refcount, pll->active); |
ee7b9f93 JB |
3832 | |
3833 | goto found; | |
3834 | } | |
3835 | } | |
3836 | ||
3837 | /* Ok no matching timings, maybe there's a free one? */ | |
e72f9fbf DV |
3838 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
3839 | pll = &dev_priv->shared_dplls[i]; | |
ee7b9f93 | 3840 | if (pll->refcount == 0) { |
46edb027 DV |
3841 | DRM_DEBUG_KMS("CRTC:%d allocated %s\n", |
3842 | crtc->base.base.id, pll->name); | |
ee7b9f93 JB |
3843 | goto found; |
3844 | } | |
3845 | } | |
3846 | ||
3847 | return NULL; | |
3848 | ||
3849 | found: | |
f2a69f44 DV |
3850 | if (pll->refcount == 0) |
3851 | pll->hw_state = crtc->config.dpll_hw_state; | |
3852 | ||
a43f6e0f | 3853 | crtc->config.shared_dpll = i; |
46edb027 DV |
3854 | DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name, |
3855 | pipe_name(crtc->pipe)); | |
ee7b9f93 | 3856 | |
cdbd2316 | 3857 | pll->refcount++; |
e04c7350 | 3858 | |
ee7b9f93 JB |
3859 | return pll; |
3860 | } | |
3861 | ||
a1520318 | 3862 | static void cpt_verify_modeset(struct drm_device *dev, int pipe) |
d4270e57 JB |
3863 | { |
3864 | struct drm_i915_private *dev_priv = dev->dev_private; | |
23670b32 | 3865 | int dslreg = PIPEDSL(pipe); |
d4270e57 JB |
3866 | u32 temp; |
3867 | ||
3868 | temp = I915_READ(dslreg); | |
3869 | udelay(500); | |
3870 | if (wait_for(I915_READ(dslreg) != temp, 5)) { | |
d4270e57 | 3871 | if (wait_for(I915_READ(dslreg) != temp, 5)) |
84f44ce7 | 3872 | DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe)); |
d4270e57 JB |
3873 | } |
3874 | } | |
3875 | ||
b074cec8 JB |
3876 | static void ironlake_pfit_enable(struct intel_crtc *crtc) |
3877 | { | |
3878 | struct drm_device *dev = crtc->base.dev; | |
3879 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3880 | int pipe = crtc->pipe; | |
3881 | ||
fd4daa9c | 3882 | if (crtc->config.pch_pfit.enabled) { |
b074cec8 JB |
3883 | /* Force use of hard-coded filter coefficients |
3884 | * as some pre-programmed values are broken, | |
3885 | * e.g. x201. | |
3886 | */ | |
3887 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) | |
3888 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 | | |
3889 | PF_PIPE_SEL_IVB(pipe)); | |
3890 | else | |
3891 | I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3); | |
3892 | I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos); | |
3893 | I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size); | |
d4270e57 JB |
3894 | } |
3895 | } | |
3896 | ||
bb53d4ae VS |
3897 | static void intel_enable_planes(struct drm_crtc *crtc) |
3898 | { | |
3899 | struct drm_device *dev = crtc->dev; | |
3900 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 3901 | struct drm_plane *plane; |
bb53d4ae VS |
3902 | struct intel_plane *intel_plane; |
3903 | ||
af2b653b MR |
3904 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
3905 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
3906 | if (intel_plane->pipe == pipe) |
3907 | intel_plane_restore(&intel_plane->base); | |
af2b653b | 3908 | } |
bb53d4ae VS |
3909 | } |
3910 | ||
3911 | static void intel_disable_planes(struct drm_crtc *crtc) | |
3912 | { | |
3913 | struct drm_device *dev = crtc->dev; | |
3914 | enum pipe pipe = to_intel_crtc(crtc)->pipe; | |
af2b653b | 3915 | struct drm_plane *plane; |
bb53d4ae VS |
3916 | struct intel_plane *intel_plane; |
3917 | ||
af2b653b MR |
3918 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
3919 | intel_plane = to_intel_plane(plane); | |
bb53d4ae VS |
3920 | if (intel_plane->pipe == pipe) |
3921 | intel_plane_disable(&intel_plane->base); | |
af2b653b | 3922 | } |
bb53d4ae VS |
3923 | } |
3924 | ||
20bc8673 | 3925 | void hsw_enable_ips(struct intel_crtc *crtc) |
d77e4531 | 3926 | { |
cea165c3 VS |
3927 | struct drm_device *dev = crtc->base.dev; |
3928 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d77e4531 PZ |
3929 | |
3930 | if (!crtc->config.ips_enabled) | |
3931 | return; | |
3932 | ||
cea165c3 VS |
3933 | /* We can only enable IPS after we enable a plane and wait for a vblank */ |
3934 | intel_wait_for_vblank(dev, crtc->pipe); | |
3935 | ||
d77e4531 | 3936 | assert_plane_enabled(dev_priv, crtc->plane); |
cea165c3 | 3937 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
3938 | mutex_lock(&dev_priv->rps.hw_lock); |
3939 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000)); | |
3940 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3941 | /* Quoting Art Runyan: "its not safe to expect any particular | |
3942 | * value in IPS_CTL bit 31 after enabling IPS through the | |
e59150dc JB |
3943 | * mailbox." Moreover, the mailbox may return a bogus state, |
3944 | * so we need to just enable it and continue on. | |
2a114cc1 BW |
3945 | */ |
3946 | } else { | |
3947 | I915_WRITE(IPS_CTL, IPS_ENABLE); | |
3948 | /* The bit only becomes 1 in the next vblank, so this wait here | |
3949 | * is essentially intel_wait_for_vblank. If we don't have this | |
3950 | * and don't wait for vblanks until the end of crtc_enable, then | |
3951 | * the HW state readout code will complain that the expected | |
3952 | * IPS_CTL value is not the one we read. */ | |
3953 | if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50)) | |
3954 | DRM_ERROR("Timed out waiting for IPS enable\n"); | |
3955 | } | |
d77e4531 PZ |
3956 | } |
3957 | ||
20bc8673 | 3958 | void hsw_disable_ips(struct intel_crtc *crtc) |
d77e4531 PZ |
3959 | { |
3960 | struct drm_device *dev = crtc->base.dev; | |
3961 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3962 | ||
3963 | if (!crtc->config.ips_enabled) | |
3964 | return; | |
3965 | ||
3966 | assert_plane_enabled(dev_priv, crtc->plane); | |
23d0b130 | 3967 | if (IS_BROADWELL(dev)) { |
2a114cc1 BW |
3968 | mutex_lock(&dev_priv->rps.hw_lock); |
3969 | WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0)); | |
3970 | mutex_unlock(&dev_priv->rps.hw_lock); | |
23d0b130 BW |
3971 | /* wait for pcode to finish disabling IPS, which may take up to 42ms */ |
3972 | if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42)) | |
3973 | DRM_ERROR("Timed out waiting for IPS disable\n"); | |
e59150dc | 3974 | } else { |
2a114cc1 | 3975 | I915_WRITE(IPS_CTL, 0); |
e59150dc JB |
3976 | POSTING_READ(IPS_CTL); |
3977 | } | |
d77e4531 PZ |
3978 | |
3979 | /* We need to wait for a vblank before we can disable the plane. */ | |
3980 | intel_wait_for_vblank(dev, crtc->pipe); | |
3981 | } | |
3982 | ||
3983 | /** Loads the palette/gamma unit for the CRTC with the prepared values */ | |
3984 | static void intel_crtc_load_lut(struct drm_crtc *crtc) | |
3985 | { | |
3986 | struct drm_device *dev = crtc->dev; | |
3987 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3988 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3989 | enum pipe pipe = intel_crtc->pipe; | |
3990 | int palreg = PALETTE(pipe); | |
3991 | int i; | |
3992 | bool reenable_ips = false; | |
3993 | ||
3994 | /* The clocks have to be on to load the palette. */ | |
3995 | if (!crtc->enabled || !intel_crtc->active) | |
3996 | return; | |
3997 | ||
3998 | if (!HAS_PCH_SPLIT(dev_priv->dev)) { | |
3999 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) | |
4000 | assert_dsi_pll_enabled(dev_priv); | |
4001 | else | |
4002 | assert_pll_enabled(dev_priv, pipe); | |
4003 | } | |
4004 | ||
4005 | /* use legacy palette for Ironlake */ | |
7a1db49a | 4006 | if (!HAS_GMCH_DISPLAY(dev)) |
d77e4531 PZ |
4007 | palreg = LGC_PALETTE(pipe); |
4008 | ||
4009 | /* Workaround : Do not read or write the pipe palette/gamma data while | |
4010 | * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled. | |
4011 | */ | |
41e6fc4c | 4012 | if (IS_HASWELL(dev) && intel_crtc->config.ips_enabled && |
d77e4531 PZ |
4013 | ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) == |
4014 | GAMMA_MODE_MODE_SPLIT)) { | |
4015 | hsw_disable_ips(intel_crtc); | |
4016 | reenable_ips = true; | |
4017 | } | |
4018 | ||
4019 | for (i = 0; i < 256; i++) { | |
4020 | I915_WRITE(palreg + 4 * i, | |
4021 | (intel_crtc->lut_r[i] << 16) | | |
4022 | (intel_crtc->lut_g[i] << 8) | | |
4023 | intel_crtc->lut_b[i]); | |
4024 | } | |
4025 | ||
4026 | if (reenable_ips) | |
4027 | hsw_enable_ips(intel_crtc); | |
4028 | } | |
4029 | ||
d3eedb1a VS |
4030 | static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable) |
4031 | { | |
4032 | if (!enable && intel_crtc->overlay) { | |
4033 | struct drm_device *dev = intel_crtc->base.dev; | |
4034 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4035 | ||
4036 | mutex_lock(&dev->struct_mutex); | |
4037 | dev_priv->mm.interruptible = false; | |
4038 | (void) intel_overlay_switch_off(intel_crtc->overlay); | |
4039 | dev_priv->mm.interruptible = true; | |
4040 | mutex_unlock(&dev->struct_mutex); | |
4041 | } | |
4042 | ||
4043 | /* Let userspace switch the overlay on again. In most cases userspace | |
4044 | * has to recompute where to put it anyway. | |
4045 | */ | |
4046 | } | |
4047 | ||
d3eedb1a | 4048 | static void intel_crtc_enable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
4049 | { |
4050 | struct drm_device *dev = crtc->dev; | |
a5c4d7bc VS |
4051 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4052 | int pipe = intel_crtc->pipe; | |
a5c4d7bc | 4053 | |
08c71e5e VS |
4054 | assert_vblank_disabled(crtc); |
4055 | ||
f98551ae VS |
4056 | drm_vblank_on(dev, pipe); |
4057 | ||
fdd508a6 | 4058 | intel_enable_primary_hw_plane(crtc->primary, crtc); |
a5c4d7bc VS |
4059 | intel_enable_planes(crtc); |
4060 | intel_crtc_update_cursor(crtc, true); | |
d3eedb1a | 4061 | intel_crtc_dpms_overlay(intel_crtc, true); |
a5c4d7bc VS |
4062 | |
4063 | hsw_enable_ips(intel_crtc); | |
4064 | ||
4065 | mutex_lock(&dev->struct_mutex); | |
4066 | intel_update_fbc(dev); | |
4067 | mutex_unlock(&dev->struct_mutex); | |
f99d7069 DV |
4068 | |
4069 | /* | |
4070 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4071 | * to compute the mask of flip planes precisely. For the time being | |
4072 | * consider this a flip from a NULL plane. | |
4073 | */ | |
4074 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
a5c4d7bc VS |
4075 | } |
4076 | ||
d3eedb1a | 4077 | static void intel_crtc_disable_planes(struct drm_crtc *crtc) |
a5c4d7bc VS |
4078 | { |
4079 | struct drm_device *dev = crtc->dev; | |
4080 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4081 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4082 | int pipe = intel_crtc->pipe; | |
4083 | int plane = intel_crtc->plane; | |
4084 | ||
4085 | intel_crtc_wait_for_pending_flips(crtc); | |
a5c4d7bc VS |
4086 | |
4087 | if (dev_priv->fbc.plane == plane) | |
4088 | intel_disable_fbc(dev); | |
4089 | ||
4090 | hsw_disable_ips(intel_crtc); | |
4091 | ||
d3eedb1a | 4092 | intel_crtc_dpms_overlay(intel_crtc, false); |
a5c4d7bc VS |
4093 | intel_crtc_update_cursor(crtc, false); |
4094 | intel_disable_planes(crtc); | |
fdd508a6 | 4095 | intel_disable_primary_hw_plane(crtc->primary, crtc); |
f98551ae | 4096 | |
f99d7069 DV |
4097 | /* |
4098 | * FIXME: Once we grow proper nuclear flip support out of this we need | |
4099 | * to compute the mask of flip planes precisely. For the time being | |
4100 | * consider this a flip to a NULL plane. | |
4101 | */ | |
4102 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe)); | |
4103 | ||
f98551ae | 4104 | drm_vblank_off(dev, pipe); |
08c71e5e VS |
4105 | |
4106 | assert_vblank_disabled(crtc); | |
a5c4d7bc VS |
4107 | } |
4108 | ||
f67a559d JB |
4109 | static void ironlake_crtc_enable(struct drm_crtc *crtc) |
4110 | { | |
4111 | struct drm_device *dev = crtc->dev; | |
4112 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4113 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4114 | struct intel_encoder *encoder; |
f67a559d | 4115 | int pipe = intel_crtc->pipe; |
f67a559d | 4116 | |
08a48469 DV |
4117 | WARN_ON(!crtc->enabled); |
4118 | ||
f67a559d JB |
4119 | if (intel_crtc->active) |
4120 | return; | |
4121 | ||
b14b1055 DV |
4122 | if (intel_crtc->config.has_pch_encoder) |
4123 | intel_prepare_shared_dpll(intel_crtc); | |
4124 | ||
29407aab DV |
4125 | if (intel_crtc->config.has_dp_encoder) |
4126 | intel_dp_set_m_n(intel_crtc); | |
4127 | ||
4128 | intel_set_pipe_timings(intel_crtc); | |
4129 | ||
4130 | if (intel_crtc->config.has_pch_encoder) { | |
4131 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
f769cd24 | 4132 | &intel_crtc->config.fdi_m_n, NULL); |
29407aab DV |
4133 | } |
4134 | ||
4135 | ironlake_set_pipeconf(crtc); | |
4136 | ||
f67a559d | 4137 | intel_crtc->active = true; |
8664281b PZ |
4138 | |
4139 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4140 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
4141 | ||
f6736a1a | 4142 | for_each_encoder_on_crtc(dev, crtc, encoder) |
952735ee DV |
4143 | if (encoder->pre_enable) |
4144 | encoder->pre_enable(encoder); | |
f67a559d | 4145 | |
5bfe2ac0 | 4146 | if (intel_crtc->config.has_pch_encoder) { |
fff367c7 DV |
4147 | /* Note: FDI PLL enabling _must_ be done before we enable the |
4148 | * cpu pipes, hence this is separate from all the other fdi/pch | |
4149 | * enabling. */ | |
88cefb6c | 4150 | ironlake_fdi_pll_enable(intel_crtc); |
46b6f814 DV |
4151 | } else { |
4152 | assert_fdi_tx_disabled(dev_priv, pipe); | |
4153 | assert_fdi_rx_disabled(dev_priv, pipe); | |
4154 | } | |
f67a559d | 4155 | |
b074cec8 | 4156 | ironlake_pfit_enable(intel_crtc); |
f67a559d | 4157 | |
9c54c0dd JB |
4158 | /* |
4159 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4160 | * clocks enabled | |
4161 | */ | |
4162 | intel_crtc_load_lut(crtc); | |
4163 | ||
f37fcc2a | 4164 | intel_update_watermarks(crtc); |
e1fdc473 | 4165 | intel_enable_pipe(intel_crtc); |
f67a559d | 4166 | |
5bfe2ac0 | 4167 | if (intel_crtc->config.has_pch_encoder) |
f67a559d | 4168 | ironlake_pch_enable(crtc); |
c98e9dcf | 4169 | |
fa5c73b1 DV |
4170 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4171 | encoder->enable(encoder); | |
61b77ddd DV |
4172 | |
4173 | if (HAS_PCH_CPT(dev)) | |
a1520318 | 4174 | cpt_verify_modeset(dev, intel_crtc->pipe); |
6ce94100 | 4175 | |
d3eedb1a | 4176 | intel_crtc_enable_planes(crtc); |
6be4a607 JB |
4177 | } |
4178 | ||
42db64ef PZ |
4179 | /* IPS only exists on ULT machines and is tied to pipe A. */ |
4180 | static bool hsw_crtc_supports_ips(struct intel_crtc *crtc) | |
4181 | { | |
f5adf94e | 4182 | return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A; |
42db64ef PZ |
4183 | } |
4184 | ||
e4916946 PZ |
4185 | /* |
4186 | * This implements the workaround described in the "notes" section of the mode | |
4187 | * set sequence documentation. When going from no pipes or single pipe to | |
4188 | * multiple pipes, and planes are enabled after the pipe, we need to wait at | |
4189 | * least 2 vblanks on the first pipe before enabling planes on the second pipe. | |
4190 | */ | |
4191 | static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) | |
4192 | { | |
4193 | struct drm_device *dev = crtc->base.dev; | |
4194 | struct intel_crtc *crtc_it, *other_active_crtc = NULL; | |
4195 | ||
4196 | /* We want to get the other_active_crtc only if there's only 1 other | |
4197 | * active crtc. */ | |
d3fcc808 | 4198 | for_each_intel_crtc(dev, crtc_it) { |
e4916946 PZ |
4199 | if (!crtc_it->active || crtc_it == crtc) |
4200 | continue; | |
4201 | ||
4202 | if (other_active_crtc) | |
4203 | return; | |
4204 | ||
4205 | other_active_crtc = crtc_it; | |
4206 | } | |
4207 | if (!other_active_crtc) | |
4208 | return; | |
4209 | ||
4210 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4211 | intel_wait_for_vblank(dev, other_active_crtc->pipe); | |
4212 | } | |
4213 | ||
4f771f10 PZ |
4214 | static void haswell_crtc_enable(struct drm_crtc *crtc) |
4215 | { | |
4216 | struct drm_device *dev = crtc->dev; | |
4217 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4218 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4219 | struct intel_encoder *encoder; | |
4220 | int pipe = intel_crtc->pipe; | |
4f771f10 PZ |
4221 | |
4222 | WARN_ON(!crtc->enabled); | |
4223 | ||
4224 | if (intel_crtc->active) | |
4225 | return; | |
4226 | ||
df8ad70c DV |
4227 | if (intel_crtc_to_shared_dpll(intel_crtc)) |
4228 | intel_enable_shared_dpll(intel_crtc); | |
4229 | ||
229fca97 DV |
4230 | if (intel_crtc->config.has_dp_encoder) |
4231 | intel_dp_set_m_n(intel_crtc); | |
4232 | ||
4233 | intel_set_pipe_timings(intel_crtc); | |
4234 | ||
4235 | if (intel_crtc->config.has_pch_encoder) { | |
4236 | intel_cpu_transcoder_set_m_n(intel_crtc, | |
f769cd24 | 4237 | &intel_crtc->config.fdi_m_n, NULL); |
229fca97 DV |
4238 | } |
4239 | ||
4240 | haswell_set_pipeconf(crtc); | |
4241 | ||
4242 | intel_set_pipe_csc(crtc); | |
4243 | ||
4f771f10 | 4244 | intel_crtc->active = true; |
8664281b PZ |
4245 | |
4246 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4f771f10 PZ |
4247 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4248 | if (encoder->pre_enable) | |
4249 | encoder->pre_enable(encoder); | |
4250 | ||
4fe9467d ID |
4251 | if (intel_crtc->config.has_pch_encoder) { |
4252 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); | |
4253 | dev_priv->display.fdi_link_train(crtc); | |
4254 | } | |
4255 | ||
1f544388 | 4256 | intel_ddi_enable_pipe_clock(intel_crtc); |
4f771f10 | 4257 | |
b074cec8 | 4258 | ironlake_pfit_enable(intel_crtc); |
4f771f10 PZ |
4259 | |
4260 | /* | |
4261 | * On ILK+ LUT must be loaded before the pipe is running but with | |
4262 | * clocks enabled | |
4263 | */ | |
4264 | intel_crtc_load_lut(crtc); | |
4265 | ||
1f544388 | 4266 | intel_ddi_set_pipe_settings(crtc); |
8228c251 | 4267 | intel_ddi_enable_transcoder_func(crtc); |
4f771f10 | 4268 | |
f37fcc2a | 4269 | intel_update_watermarks(crtc); |
e1fdc473 | 4270 | intel_enable_pipe(intel_crtc); |
42db64ef | 4271 | |
5bfe2ac0 | 4272 | if (intel_crtc->config.has_pch_encoder) |
1507e5bd | 4273 | lpt_pch_enable(crtc); |
4f771f10 | 4274 | |
0e32b39c DA |
4275 | if (intel_crtc->config.dp_encoder_is_mst) |
4276 | intel_ddi_set_vc_payload_alloc(crtc, true); | |
4277 | ||
8807e55b | 4278 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4f771f10 | 4279 | encoder->enable(encoder); |
8807e55b JN |
4280 | intel_opregion_notify_encoder(encoder, true); |
4281 | } | |
4f771f10 | 4282 | |
e4916946 PZ |
4283 | /* If we change the relative order between pipe/planes enabling, we need |
4284 | * to change the workaround. */ | |
4285 | haswell_mode_set_planes_workaround(intel_crtc); | |
d3eedb1a | 4286 | intel_crtc_enable_planes(crtc); |
4f771f10 PZ |
4287 | } |
4288 | ||
3f8dce3a DV |
4289 | static void ironlake_pfit_disable(struct intel_crtc *crtc) |
4290 | { | |
4291 | struct drm_device *dev = crtc->base.dev; | |
4292 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4293 | int pipe = crtc->pipe; | |
4294 | ||
4295 | /* To avoid upsetting the power well on haswell only disable the pfit if | |
4296 | * it's in use. The hw state code will make sure we get this right. */ | |
fd4daa9c | 4297 | if (crtc->config.pch_pfit.enabled) { |
3f8dce3a DV |
4298 | I915_WRITE(PF_CTL(pipe), 0); |
4299 | I915_WRITE(PF_WIN_POS(pipe), 0); | |
4300 | I915_WRITE(PF_WIN_SZ(pipe), 0); | |
4301 | } | |
4302 | } | |
4303 | ||
6be4a607 JB |
4304 | static void ironlake_crtc_disable(struct drm_crtc *crtc) |
4305 | { | |
4306 | struct drm_device *dev = crtc->dev; | |
4307 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4308 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4309 | struct intel_encoder *encoder; |
6be4a607 | 4310 | int pipe = intel_crtc->pipe; |
5eddb70b | 4311 | u32 reg, temp; |
b52eb4dc | 4312 | |
f7abfe8b CW |
4313 | if (!intel_crtc->active) |
4314 | return; | |
4315 | ||
d3eedb1a | 4316 | intel_crtc_disable_planes(crtc); |
a5c4d7bc | 4317 | |
ea9d758d DV |
4318 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4319 | encoder->disable(encoder); | |
4320 | ||
d925c59a DV |
4321 | if (intel_crtc->config.has_pch_encoder) |
4322 | intel_set_pch_fifo_underrun_reporting(dev, pipe, false); | |
4323 | ||
575f7ab7 | 4324 | intel_disable_pipe(intel_crtc); |
32f9d658 | 4325 | |
3f8dce3a | 4326 | ironlake_pfit_disable(intel_crtc); |
2c07245f | 4327 | |
bf49ec8c DV |
4328 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4329 | if (encoder->post_disable) | |
4330 | encoder->post_disable(encoder); | |
2c07245f | 4331 | |
d925c59a DV |
4332 | if (intel_crtc->config.has_pch_encoder) { |
4333 | ironlake_fdi_disable(crtc); | |
913d8d11 | 4334 | |
d925c59a DV |
4335 | ironlake_disable_pch_transcoder(dev_priv, pipe); |
4336 | intel_set_pch_fifo_underrun_reporting(dev, pipe, true); | |
6be4a607 | 4337 | |
d925c59a DV |
4338 | if (HAS_PCH_CPT(dev)) { |
4339 | /* disable TRANS_DP_CTL */ | |
4340 | reg = TRANS_DP_CTL(pipe); | |
4341 | temp = I915_READ(reg); | |
4342 | temp &= ~(TRANS_DP_OUTPUT_ENABLE | | |
4343 | TRANS_DP_PORT_SEL_MASK); | |
4344 | temp |= TRANS_DP_PORT_SEL_NONE; | |
4345 | I915_WRITE(reg, temp); | |
4346 | ||
4347 | /* disable DPLL_SEL */ | |
4348 | temp = I915_READ(PCH_DPLL_SEL); | |
11887397 | 4349 | temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe)); |
d925c59a | 4350 | I915_WRITE(PCH_DPLL_SEL, temp); |
9db4a9c7 | 4351 | } |
e3421a18 | 4352 | |
d925c59a | 4353 | /* disable PCH DPLL */ |
e72f9fbf | 4354 | intel_disable_shared_dpll(intel_crtc); |
8db9d77b | 4355 | |
d925c59a DV |
4356 | ironlake_fdi_pll_disable(intel_crtc); |
4357 | } | |
6b383a7f | 4358 | |
f7abfe8b | 4359 | intel_crtc->active = false; |
46ba614c | 4360 | intel_update_watermarks(crtc); |
d1ebd816 BW |
4361 | |
4362 | mutex_lock(&dev->struct_mutex); | |
6b383a7f | 4363 | intel_update_fbc(dev); |
d1ebd816 | 4364 | mutex_unlock(&dev->struct_mutex); |
6be4a607 | 4365 | } |
1b3c7a47 | 4366 | |
4f771f10 | 4367 | static void haswell_crtc_disable(struct drm_crtc *crtc) |
ee7b9f93 | 4368 | { |
4f771f10 PZ |
4369 | struct drm_device *dev = crtc->dev; |
4370 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee7b9f93 | 4371 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4f771f10 | 4372 | struct intel_encoder *encoder; |
3b117c8f | 4373 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee7b9f93 | 4374 | |
4f771f10 PZ |
4375 | if (!intel_crtc->active) |
4376 | return; | |
4377 | ||
d3eedb1a | 4378 | intel_crtc_disable_planes(crtc); |
dda9a66a | 4379 | |
8807e55b JN |
4380 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
4381 | intel_opregion_notify_encoder(encoder, false); | |
4f771f10 | 4382 | encoder->disable(encoder); |
8807e55b | 4383 | } |
4f771f10 | 4384 | |
8664281b PZ |
4385 | if (intel_crtc->config.has_pch_encoder) |
4386 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false); | |
575f7ab7 | 4387 | intel_disable_pipe(intel_crtc); |
4f771f10 | 4388 | |
a4bf214f VS |
4389 | if (intel_crtc->config.dp_encoder_is_mst) |
4390 | intel_ddi_set_vc_payload_alloc(crtc, false); | |
4391 | ||
ad80a810 | 4392 | intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder); |
4f771f10 | 4393 | |
3f8dce3a | 4394 | ironlake_pfit_disable(intel_crtc); |
4f771f10 | 4395 | |
1f544388 | 4396 | intel_ddi_disable_pipe_clock(intel_crtc); |
4f771f10 | 4397 | |
88adfff1 | 4398 | if (intel_crtc->config.has_pch_encoder) { |
ab4d966c | 4399 | lpt_disable_pch_transcoder(dev_priv); |
8664281b | 4400 | intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true); |
1ad960f2 | 4401 | intel_ddi_fdi_disable(crtc); |
83616634 | 4402 | } |
4f771f10 | 4403 | |
97b040aa ID |
4404 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4405 | if (encoder->post_disable) | |
4406 | encoder->post_disable(encoder); | |
4407 | ||
4f771f10 | 4408 | intel_crtc->active = false; |
46ba614c | 4409 | intel_update_watermarks(crtc); |
4f771f10 PZ |
4410 | |
4411 | mutex_lock(&dev->struct_mutex); | |
4412 | intel_update_fbc(dev); | |
4413 | mutex_unlock(&dev->struct_mutex); | |
df8ad70c DV |
4414 | |
4415 | if (intel_crtc_to_shared_dpll(intel_crtc)) | |
4416 | intel_disable_shared_dpll(intel_crtc); | |
4f771f10 PZ |
4417 | } |
4418 | ||
ee7b9f93 JB |
4419 | static void ironlake_crtc_off(struct drm_crtc *crtc) |
4420 | { | |
4421 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
e72f9fbf | 4422 | intel_put_shared_dpll(intel_crtc); |
ee7b9f93 JB |
4423 | } |
4424 | ||
6441ab5f | 4425 | |
2dd24552 JB |
4426 | static void i9xx_pfit_enable(struct intel_crtc *crtc) |
4427 | { | |
4428 | struct drm_device *dev = crtc->base.dev; | |
4429 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4430 | struct intel_crtc_config *pipe_config = &crtc->config; | |
4431 | ||
328d8e82 | 4432 | if (!crtc->config.gmch_pfit.control) |
2dd24552 JB |
4433 | return; |
4434 | ||
2dd24552 | 4435 | /* |
c0b03411 DV |
4436 | * The panel fitter should only be adjusted whilst the pipe is disabled, |
4437 | * according to register description and PRM. | |
2dd24552 | 4438 | */ |
c0b03411 DV |
4439 | WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE); |
4440 | assert_pipe_disabled(dev_priv, crtc->pipe); | |
2dd24552 | 4441 | |
b074cec8 JB |
4442 | I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios); |
4443 | I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control); | |
5a80c45c DV |
4444 | |
4445 | /* Border color in case we don't scale up to the full screen. Black by | |
4446 | * default, change to something else for debugging. */ | |
4447 | I915_WRITE(BCLRPAT(crtc->pipe), 0); | |
2dd24552 JB |
4448 | } |
4449 | ||
d05410f9 DA |
4450 | static enum intel_display_power_domain port_to_power_domain(enum port port) |
4451 | { | |
4452 | switch (port) { | |
4453 | case PORT_A: | |
4454 | return POWER_DOMAIN_PORT_DDI_A_4_LANES; | |
4455 | case PORT_B: | |
4456 | return POWER_DOMAIN_PORT_DDI_B_4_LANES; | |
4457 | case PORT_C: | |
4458 | return POWER_DOMAIN_PORT_DDI_C_4_LANES; | |
4459 | case PORT_D: | |
4460 | return POWER_DOMAIN_PORT_DDI_D_4_LANES; | |
4461 | default: | |
4462 | WARN_ON_ONCE(1); | |
4463 | return POWER_DOMAIN_PORT_OTHER; | |
4464 | } | |
4465 | } | |
4466 | ||
77d22dca ID |
4467 | #define for_each_power_domain(domain, mask) \ |
4468 | for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \ | |
4469 | if ((1 << (domain)) & (mask)) | |
4470 | ||
319be8ae ID |
4471 | enum intel_display_power_domain |
4472 | intel_display_port_power_domain(struct intel_encoder *intel_encoder) | |
4473 | { | |
4474 | struct drm_device *dev = intel_encoder->base.dev; | |
4475 | struct intel_digital_port *intel_dig_port; | |
4476 | ||
4477 | switch (intel_encoder->type) { | |
4478 | case INTEL_OUTPUT_UNKNOWN: | |
4479 | /* Only DDI platforms should ever use this output type */ | |
4480 | WARN_ON_ONCE(!HAS_DDI(dev)); | |
4481 | case INTEL_OUTPUT_DISPLAYPORT: | |
4482 | case INTEL_OUTPUT_HDMI: | |
4483 | case INTEL_OUTPUT_EDP: | |
4484 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
d05410f9 | 4485 | return port_to_power_domain(intel_dig_port->port); |
0e32b39c DA |
4486 | case INTEL_OUTPUT_DP_MST: |
4487 | intel_dig_port = enc_to_mst(&intel_encoder->base)->primary; | |
4488 | return port_to_power_domain(intel_dig_port->port); | |
319be8ae ID |
4489 | case INTEL_OUTPUT_ANALOG: |
4490 | return POWER_DOMAIN_PORT_CRT; | |
4491 | case INTEL_OUTPUT_DSI: | |
4492 | return POWER_DOMAIN_PORT_DSI; | |
4493 | default: | |
4494 | return POWER_DOMAIN_PORT_OTHER; | |
4495 | } | |
4496 | } | |
4497 | ||
4498 | static unsigned long get_crtc_power_domains(struct drm_crtc *crtc) | |
77d22dca | 4499 | { |
319be8ae ID |
4500 | struct drm_device *dev = crtc->dev; |
4501 | struct intel_encoder *intel_encoder; | |
4502 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4503 | enum pipe pipe = intel_crtc->pipe; | |
77d22dca ID |
4504 | unsigned long mask; |
4505 | enum transcoder transcoder; | |
4506 | ||
4507 | transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); | |
4508 | ||
4509 | mask = BIT(POWER_DOMAIN_PIPE(pipe)); | |
4510 | mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); | |
fabf6e51 DV |
4511 | if (intel_crtc->config.pch_pfit.enabled || |
4512 | intel_crtc->config.pch_pfit.force_thru) | |
77d22dca ID |
4513 | mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe)); |
4514 | ||
319be8ae ID |
4515 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) |
4516 | mask |= BIT(intel_display_port_power_domain(intel_encoder)); | |
4517 | ||
77d22dca ID |
4518 | return mask; |
4519 | } | |
4520 | ||
4521 | void intel_display_set_init_power(struct drm_i915_private *dev_priv, | |
4522 | bool enable) | |
4523 | { | |
4524 | if (dev_priv->power_domains.init_power_on == enable) | |
4525 | return; | |
4526 | ||
4527 | if (enable) | |
4528 | intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); | |
4529 | else | |
4530 | intel_display_power_put(dev_priv, POWER_DOMAIN_INIT); | |
4531 | ||
4532 | dev_priv->power_domains.init_power_on = enable; | |
4533 | } | |
4534 | ||
4535 | static void modeset_update_crtc_power_domains(struct drm_device *dev) | |
4536 | { | |
4537 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4538 | unsigned long pipe_domains[I915_MAX_PIPES] = { 0, }; | |
4539 | struct intel_crtc *crtc; | |
4540 | ||
4541 | /* | |
4542 | * First get all needed power domains, then put all unneeded, to avoid | |
4543 | * any unnecessary toggling of the power wells. | |
4544 | */ | |
d3fcc808 | 4545 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4546 | enum intel_display_power_domain domain; |
4547 | ||
4548 | if (!crtc->base.enabled) | |
4549 | continue; | |
4550 | ||
319be8ae | 4551 | pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base); |
77d22dca ID |
4552 | |
4553 | for_each_power_domain(domain, pipe_domains[crtc->pipe]) | |
4554 | intel_display_power_get(dev_priv, domain); | |
4555 | } | |
4556 | ||
d3fcc808 | 4557 | for_each_intel_crtc(dev, crtc) { |
77d22dca ID |
4558 | enum intel_display_power_domain domain; |
4559 | ||
4560 | for_each_power_domain(domain, crtc->enabled_power_domains) | |
4561 | intel_display_power_put(dev_priv, domain); | |
4562 | ||
4563 | crtc->enabled_power_domains = pipe_domains[crtc->pipe]; | |
4564 | } | |
4565 | ||
4566 | intel_display_set_init_power(dev_priv, false); | |
4567 | } | |
4568 | ||
dfcab17e | 4569 | /* returns HPLL frequency in kHz */ |
f8bf63fd | 4570 | static int valleyview_get_vco(struct drm_i915_private *dev_priv) |
30a970c6 | 4571 | { |
586f49dc | 4572 | int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 }; |
30a970c6 | 4573 | |
586f49dc JB |
4574 | /* Obtain SKU information */ |
4575 | mutex_lock(&dev_priv->dpio_lock); | |
4576 | hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) & | |
4577 | CCK_FUSE_HPLL_FREQ_MASK; | |
4578 | mutex_unlock(&dev_priv->dpio_lock); | |
30a970c6 | 4579 | |
dfcab17e | 4580 | return vco_freq[hpll_freq] * 1000; |
30a970c6 JB |
4581 | } |
4582 | ||
f8bf63fd VS |
4583 | static void vlv_update_cdclk(struct drm_device *dev) |
4584 | { | |
4585 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4586 | ||
4587 | dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev); | |
4588 | DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz", | |
4589 | dev_priv->vlv_cdclk_freq); | |
4590 | ||
4591 | /* | |
4592 | * Program the gmbus_freq based on the cdclk frequency. | |
4593 | * BSpec erroneously claims we should aim for 4MHz, but | |
4594 | * in fact 1MHz is the correct frequency. | |
4595 | */ | |
4596 | I915_WRITE(GMBUSFREQ_VLV, dev_priv->vlv_cdclk_freq); | |
4597 | } | |
4598 | ||
30a970c6 JB |
4599 | /* Adjust CDclk dividers to allow high res or save power if possible */ |
4600 | static void valleyview_set_cdclk(struct drm_device *dev, int cdclk) | |
4601 | { | |
4602 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4603 | u32 val, cmd; | |
4604 | ||
d197b7d3 | 4605 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); |
d60c4473 | 4606 | |
dfcab17e | 4607 | if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ |
30a970c6 | 4608 | cmd = 2; |
dfcab17e | 4609 | else if (cdclk == 266667) |
30a970c6 JB |
4610 | cmd = 1; |
4611 | else | |
4612 | cmd = 0; | |
4613 | ||
4614 | mutex_lock(&dev_priv->rps.hw_lock); | |
4615 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4616 | val &= ~DSPFREQGUAR_MASK; | |
4617 | val |= (cmd << DSPFREQGUAR_SHIFT); | |
4618 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4619 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4620 | DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT), | |
4621 | 50)) { | |
4622 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4623 | } | |
4624 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4625 | ||
dfcab17e | 4626 | if (cdclk == 400000) { |
30a970c6 JB |
4627 | u32 divider, vco; |
4628 | ||
4629 | vco = valleyview_get_vco(dev_priv); | |
dfcab17e | 4630 | divider = DIV_ROUND_CLOSEST(vco << 1, cdclk) - 1; |
30a970c6 JB |
4631 | |
4632 | mutex_lock(&dev_priv->dpio_lock); | |
4633 | /* adjust cdclk divider */ | |
4634 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
9cf33db5 | 4635 | val &= ~DISPLAY_FREQUENCY_VALUES; |
30a970c6 JB |
4636 | val |= divider; |
4637 | vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val); | |
a877e801 VS |
4638 | |
4639 | if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) & | |
4640 | DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
4641 | 50)) | |
4642 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
30a970c6 JB |
4643 | mutex_unlock(&dev_priv->dpio_lock); |
4644 | } | |
4645 | ||
4646 | mutex_lock(&dev_priv->dpio_lock); | |
4647 | /* adjust self-refresh exit latency value */ | |
4648 | val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC); | |
4649 | val &= ~0x7f; | |
4650 | ||
4651 | /* | |
4652 | * For high bandwidth configs, we set a higher latency in the bunit | |
4653 | * so that the core display fetch happens in time to avoid underruns. | |
4654 | */ | |
dfcab17e | 4655 | if (cdclk == 400000) |
30a970c6 JB |
4656 | val |= 4500 / 250; /* 4.5 usec */ |
4657 | else | |
4658 | val |= 3000 / 250; /* 3.0 usec */ | |
4659 | vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val); | |
4660 | mutex_unlock(&dev_priv->dpio_lock); | |
4661 | ||
f8bf63fd | 4662 | vlv_update_cdclk(dev); |
30a970c6 JB |
4663 | } |
4664 | ||
383c5a6a VS |
4665 | static void cherryview_set_cdclk(struct drm_device *dev, int cdclk) |
4666 | { | |
4667 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4668 | u32 val, cmd; | |
4669 | ||
4670 | WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq); | |
4671 | ||
4672 | switch (cdclk) { | |
4673 | case 400000: | |
4674 | cmd = 3; | |
4675 | break; | |
4676 | case 333333: | |
4677 | case 320000: | |
4678 | cmd = 2; | |
4679 | break; | |
4680 | case 266667: | |
4681 | cmd = 1; | |
4682 | break; | |
4683 | case 200000: | |
4684 | cmd = 0; | |
4685 | break; | |
4686 | default: | |
4687 | WARN_ON(1); | |
4688 | return; | |
4689 | } | |
4690 | ||
4691 | mutex_lock(&dev_priv->rps.hw_lock); | |
4692 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
4693 | val &= ~DSPFREQGUAR_MASK_CHV; | |
4694 | val |= (cmd << DSPFREQGUAR_SHIFT_CHV); | |
4695 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
4696 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & | |
4697 | DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV), | |
4698 | 50)) { | |
4699 | DRM_ERROR("timed out waiting for CDclk change\n"); | |
4700 | } | |
4701 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4702 | ||
4703 | vlv_update_cdclk(dev); | |
4704 | } | |
4705 | ||
30a970c6 JB |
4706 | static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv, |
4707 | int max_pixclk) | |
4708 | { | |
29dc7ef3 VS |
4709 | int vco = valleyview_get_vco(dev_priv); |
4710 | int freq_320 = (vco << 1) % 320000 != 0 ? 333333 : 320000; | |
4711 | ||
d49a340d VS |
4712 | /* FIXME: Punit isn't quite ready yet */ |
4713 | if (IS_CHERRYVIEW(dev_priv->dev)) | |
4714 | return 400000; | |
4715 | ||
30a970c6 JB |
4716 | /* |
4717 | * Really only a few cases to deal with, as only 4 CDclks are supported: | |
4718 | * 200MHz | |
4719 | * 267MHz | |
29dc7ef3 | 4720 | * 320/333MHz (depends on HPLL freq) |
30a970c6 JB |
4721 | * 400MHz |
4722 | * So we check to see whether we're above 90% of the lower bin and | |
4723 | * adjust if needed. | |
e37c67a1 VS |
4724 | * |
4725 | * We seem to get an unstable or solid color picture at 200MHz. | |
4726 | * Not sure what's wrong. For now use 200MHz only when all pipes | |
4727 | * are off. | |
30a970c6 | 4728 | */ |
29dc7ef3 | 4729 | if (max_pixclk > freq_320*9/10) |
dfcab17e VS |
4730 | return 400000; |
4731 | else if (max_pixclk > 266667*9/10) | |
29dc7ef3 | 4732 | return freq_320; |
e37c67a1 | 4733 | else if (max_pixclk > 0) |
dfcab17e | 4734 | return 266667; |
e37c67a1 VS |
4735 | else |
4736 | return 200000; | |
30a970c6 JB |
4737 | } |
4738 | ||
2f2d7aa1 VS |
4739 | /* compute the max pixel clock for new configuration */ |
4740 | static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv) | |
30a970c6 JB |
4741 | { |
4742 | struct drm_device *dev = dev_priv->dev; | |
4743 | struct intel_crtc *intel_crtc; | |
4744 | int max_pixclk = 0; | |
4745 | ||
d3fcc808 | 4746 | for_each_intel_crtc(dev, intel_crtc) { |
2f2d7aa1 | 4747 | if (intel_crtc->new_enabled) |
30a970c6 | 4748 | max_pixclk = max(max_pixclk, |
2f2d7aa1 | 4749 | intel_crtc->new_config->adjusted_mode.crtc_clock); |
30a970c6 JB |
4750 | } |
4751 | ||
4752 | return max_pixclk; | |
4753 | } | |
4754 | ||
4755 | static void valleyview_modeset_global_pipes(struct drm_device *dev, | |
2f2d7aa1 | 4756 | unsigned *prepare_pipes) |
30a970c6 JB |
4757 | { |
4758 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4759 | struct intel_crtc *intel_crtc; | |
2f2d7aa1 | 4760 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 | 4761 | |
d60c4473 ID |
4762 | if (valleyview_calc_cdclk(dev_priv, max_pixclk) == |
4763 | dev_priv->vlv_cdclk_freq) | |
30a970c6 JB |
4764 | return; |
4765 | ||
2f2d7aa1 | 4766 | /* disable/enable all currently active pipes while we change cdclk */ |
d3fcc808 | 4767 | for_each_intel_crtc(dev, intel_crtc) |
30a970c6 JB |
4768 | if (intel_crtc->base.enabled) |
4769 | *prepare_pipes |= (1 << intel_crtc->pipe); | |
4770 | } | |
4771 | ||
4772 | static void valleyview_modeset_global_resources(struct drm_device *dev) | |
4773 | { | |
4774 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2f2d7aa1 | 4775 | int max_pixclk = intel_mode_max_pixclk(dev_priv); |
30a970c6 JB |
4776 | int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk); |
4777 | ||
383c5a6a VS |
4778 | if (req_cdclk != dev_priv->vlv_cdclk_freq) { |
4779 | if (IS_CHERRYVIEW(dev)) | |
4780 | cherryview_set_cdclk(dev, req_cdclk); | |
4781 | else | |
4782 | valleyview_set_cdclk(dev, req_cdclk); | |
4783 | } | |
4784 | ||
77961eb9 | 4785 | modeset_update_crtc_power_domains(dev); |
30a970c6 JB |
4786 | } |
4787 | ||
89b667f8 JB |
4788 | static void valleyview_crtc_enable(struct drm_crtc *crtc) |
4789 | { | |
4790 | struct drm_device *dev = crtc->dev; | |
89b667f8 JB |
4791 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4792 | struct intel_encoder *encoder; | |
4793 | int pipe = intel_crtc->pipe; | |
23538ef1 | 4794 | bool is_dsi; |
89b667f8 JB |
4795 | |
4796 | WARN_ON(!crtc->enabled); | |
4797 | ||
4798 | if (intel_crtc->active) | |
4799 | return; | |
4800 | ||
8525a235 SK |
4801 | is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI); |
4802 | ||
1ae0d137 VS |
4803 | if (!is_dsi) { |
4804 | if (IS_CHERRYVIEW(dev)) | |
4805 | chv_prepare_pll(intel_crtc); | |
4806 | else | |
4807 | vlv_prepare_pll(intel_crtc); | |
4808 | } | |
5b18e57c DV |
4809 | |
4810 | if (intel_crtc->config.has_dp_encoder) | |
4811 | intel_dp_set_m_n(intel_crtc); | |
4812 | ||
4813 | intel_set_pipe_timings(intel_crtc); | |
4814 | ||
5b18e57c DV |
4815 | i9xx_set_pipeconf(intel_crtc); |
4816 | ||
89b667f8 | 4817 | intel_crtc->active = true; |
89b667f8 | 4818 | |
4a3436e8 VS |
4819 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); |
4820 | ||
89b667f8 JB |
4821 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4822 | if (encoder->pre_pll_enable) | |
4823 | encoder->pre_pll_enable(encoder); | |
4824 | ||
9d556c99 CML |
4825 | if (!is_dsi) { |
4826 | if (IS_CHERRYVIEW(dev)) | |
4827 | chv_enable_pll(intel_crtc); | |
4828 | else | |
4829 | vlv_enable_pll(intel_crtc); | |
4830 | } | |
89b667f8 JB |
4831 | |
4832 | for_each_encoder_on_crtc(dev, crtc, encoder) | |
4833 | if (encoder->pre_enable) | |
4834 | encoder->pre_enable(encoder); | |
4835 | ||
2dd24552 JB |
4836 | i9xx_pfit_enable(intel_crtc); |
4837 | ||
63cbb074 VS |
4838 | intel_crtc_load_lut(crtc); |
4839 | ||
f37fcc2a | 4840 | intel_update_watermarks(crtc); |
e1fdc473 | 4841 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 4842 | |
5004945f JN |
4843 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4844 | encoder->enable(encoder); | |
9ab0460b VS |
4845 | |
4846 | intel_crtc_enable_planes(crtc); | |
d40d9187 | 4847 | |
56b80e1f VS |
4848 | /* Underruns don't raise interrupts, so check manually. */ |
4849 | i9xx_check_fifo_underruns(dev); | |
89b667f8 JB |
4850 | } |
4851 | ||
f13c2ef3 DV |
4852 | static void i9xx_set_pll_dividers(struct intel_crtc *crtc) |
4853 | { | |
4854 | struct drm_device *dev = crtc->base.dev; | |
4855 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4856 | ||
4857 | I915_WRITE(FP0(crtc->pipe), crtc->config.dpll_hw_state.fp0); | |
4858 | I915_WRITE(FP1(crtc->pipe), crtc->config.dpll_hw_state.fp1); | |
4859 | } | |
4860 | ||
0b8765c6 | 4861 | static void i9xx_crtc_enable(struct drm_crtc *crtc) |
79e53945 JB |
4862 | { |
4863 | struct drm_device *dev = crtc->dev; | |
79e53945 | 4864 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
ef9c3aee | 4865 | struct intel_encoder *encoder; |
79e53945 | 4866 | int pipe = intel_crtc->pipe; |
79e53945 | 4867 | |
08a48469 DV |
4868 | WARN_ON(!crtc->enabled); |
4869 | ||
f7abfe8b CW |
4870 | if (intel_crtc->active) |
4871 | return; | |
4872 | ||
f13c2ef3 DV |
4873 | i9xx_set_pll_dividers(intel_crtc); |
4874 | ||
5b18e57c DV |
4875 | if (intel_crtc->config.has_dp_encoder) |
4876 | intel_dp_set_m_n(intel_crtc); | |
4877 | ||
4878 | intel_set_pipe_timings(intel_crtc); | |
4879 | ||
5b18e57c DV |
4880 | i9xx_set_pipeconf(intel_crtc); |
4881 | ||
f7abfe8b | 4882 | intel_crtc->active = true; |
6b383a7f | 4883 | |
4a3436e8 VS |
4884 | if (!IS_GEN2(dev)) |
4885 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4886 | ||
9d6d9f19 MK |
4887 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4888 | if (encoder->pre_enable) | |
4889 | encoder->pre_enable(encoder); | |
4890 | ||
f6736a1a DV |
4891 | i9xx_enable_pll(intel_crtc); |
4892 | ||
2dd24552 JB |
4893 | i9xx_pfit_enable(intel_crtc); |
4894 | ||
63cbb074 VS |
4895 | intel_crtc_load_lut(crtc); |
4896 | ||
f37fcc2a | 4897 | intel_update_watermarks(crtc); |
e1fdc473 | 4898 | intel_enable_pipe(intel_crtc); |
be6a6f8e | 4899 | |
fa5c73b1 DV |
4900 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4901 | encoder->enable(encoder); | |
9ab0460b VS |
4902 | |
4903 | intel_crtc_enable_planes(crtc); | |
d40d9187 | 4904 | |
4a3436e8 VS |
4905 | /* |
4906 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4907 | * So don't enable underrun reporting before at least some planes | |
4908 | * are enabled. | |
4909 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4910 | * but leave the pipe running. | |
4911 | */ | |
4912 | if (IS_GEN2(dev)) | |
4913 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, true); | |
4914 | ||
56b80e1f VS |
4915 | /* Underruns don't raise interrupts, so check manually. */ |
4916 | i9xx_check_fifo_underruns(dev); | |
0b8765c6 | 4917 | } |
79e53945 | 4918 | |
87476d63 DV |
4919 | static void i9xx_pfit_disable(struct intel_crtc *crtc) |
4920 | { | |
4921 | struct drm_device *dev = crtc->base.dev; | |
4922 | struct drm_i915_private *dev_priv = dev->dev_private; | |
87476d63 | 4923 | |
328d8e82 DV |
4924 | if (!crtc->config.gmch_pfit.control) |
4925 | return; | |
87476d63 | 4926 | |
328d8e82 | 4927 | assert_pipe_disabled(dev_priv, crtc->pipe); |
87476d63 | 4928 | |
328d8e82 DV |
4929 | DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n", |
4930 | I915_READ(PFIT_CONTROL)); | |
4931 | I915_WRITE(PFIT_CONTROL, 0); | |
87476d63 DV |
4932 | } |
4933 | ||
0b8765c6 JB |
4934 | static void i9xx_crtc_disable(struct drm_crtc *crtc) |
4935 | { | |
4936 | struct drm_device *dev = crtc->dev; | |
4937 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4938 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
ef9c3aee | 4939 | struct intel_encoder *encoder; |
0b8765c6 | 4940 | int pipe = intel_crtc->pipe; |
ef9c3aee | 4941 | |
f7abfe8b CW |
4942 | if (!intel_crtc->active) |
4943 | return; | |
4944 | ||
4a3436e8 VS |
4945 | /* |
4946 | * Gen2 reports pipe underruns whenever all planes are disabled. | |
4947 | * So diasble underrun reporting before all the planes get disabled. | |
4948 | * FIXME: Need to fix the logic to work when we turn off all planes | |
4949 | * but leave the pipe running. | |
4950 | */ | |
4951 | if (IS_GEN2(dev)) | |
4952 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); | |
4953 | ||
564ed191 ID |
4954 | /* |
4955 | * Vblank time updates from the shadow to live plane control register | |
4956 | * are blocked if the memory self-refresh mode is active at that | |
4957 | * moment. So to make sure the plane gets truly disabled, disable | |
4958 | * first the self-refresh mode. The self-refresh enable bit in turn | |
4959 | * will be checked/applied by the HW only at the next frame start | |
4960 | * event which is after the vblank start event, so we need to have a | |
4961 | * wait-for-vblank between disabling the plane and the pipe. | |
4962 | */ | |
4963 | intel_set_memory_cxsr(dev_priv, false); | |
9ab0460b VS |
4964 | intel_crtc_disable_planes(crtc); |
4965 | ||
ea9d758d DV |
4966 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4967 | encoder->disable(encoder); | |
4968 | ||
6304cd91 VS |
4969 | /* |
4970 | * On gen2 planes are double buffered but the pipe isn't, so we must | |
4971 | * wait for planes to fully turn off before disabling the pipe. | |
564ed191 ID |
4972 | * We also need to wait on all gmch platforms because of the |
4973 | * self-refresh mode constraint explained above. | |
6304cd91 | 4974 | */ |
564ed191 | 4975 | intel_wait_for_vblank(dev, pipe); |
6304cd91 | 4976 | |
575f7ab7 | 4977 | intel_disable_pipe(intel_crtc); |
24a1f16d | 4978 | |
87476d63 | 4979 | i9xx_pfit_disable(intel_crtc); |
24a1f16d | 4980 | |
89b667f8 JB |
4981 | for_each_encoder_on_crtc(dev, crtc, encoder) |
4982 | if (encoder->post_disable) | |
4983 | encoder->post_disable(encoder); | |
4984 | ||
076ed3b2 CML |
4985 | if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI)) { |
4986 | if (IS_CHERRYVIEW(dev)) | |
4987 | chv_disable_pll(dev_priv, pipe); | |
4988 | else if (IS_VALLEYVIEW(dev)) | |
4989 | vlv_disable_pll(dev_priv, pipe); | |
4990 | else | |
1c4e0274 | 4991 | i9xx_disable_pll(intel_crtc); |
076ed3b2 | 4992 | } |
0b8765c6 | 4993 | |
4a3436e8 VS |
4994 | if (!IS_GEN2(dev)) |
4995 | intel_set_cpu_fifo_underrun_reporting(dev, pipe, false); | |
4996 | ||
f7abfe8b | 4997 | intel_crtc->active = false; |
46ba614c | 4998 | intel_update_watermarks(crtc); |
f37fcc2a | 4999 | |
efa9624e | 5000 | mutex_lock(&dev->struct_mutex); |
6b383a7f | 5001 | intel_update_fbc(dev); |
efa9624e | 5002 | mutex_unlock(&dev->struct_mutex); |
0b8765c6 JB |
5003 | } |
5004 | ||
ee7b9f93 JB |
5005 | static void i9xx_crtc_off(struct drm_crtc *crtc) |
5006 | { | |
5007 | } | |
5008 | ||
976f8a20 DV |
5009 | static void intel_crtc_update_sarea(struct drm_crtc *crtc, |
5010 | bool enabled) | |
2c07245f ZW |
5011 | { |
5012 | struct drm_device *dev = crtc->dev; | |
5013 | struct drm_i915_master_private *master_priv; | |
5014 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
5015 | int pipe = intel_crtc->pipe; | |
79e53945 JB |
5016 | |
5017 | if (!dev->primary->master) | |
5018 | return; | |
5019 | ||
5020 | master_priv = dev->primary->master->driver_priv; | |
5021 | if (!master_priv->sarea_priv) | |
5022 | return; | |
5023 | ||
79e53945 JB |
5024 | switch (pipe) { |
5025 | case 0: | |
5026 | master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0; | |
5027 | master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0; | |
5028 | break; | |
5029 | case 1: | |
5030 | master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0; | |
5031 | master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0; | |
5032 | break; | |
5033 | default: | |
9db4a9c7 | 5034 | DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe)); |
79e53945 JB |
5035 | break; |
5036 | } | |
79e53945 JB |
5037 | } |
5038 | ||
b04c5bd6 BF |
5039 | /* Master function to enable/disable CRTC and corresponding power wells */ |
5040 | void intel_crtc_control(struct drm_crtc *crtc, bool enable) | |
976f8a20 DV |
5041 | { |
5042 | struct drm_device *dev = crtc->dev; | |
5043 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0e572fe7 | 5044 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
0e572fe7 DV |
5045 | enum intel_display_power_domain domain; |
5046 | unsigned long domains; | |
976f8a20 | 5047 | |
0e572fe7 DV |
5048 | if (enable) { |
5049 | if (!intel_crtc->active) { | |
e1e9fb84 DV |
5050 | domains = get_crtc_power_domains(crtc); |
5051 | for_each_power_domain(domain, domains) | |
5052 | intel_display_power_get(dev_priv, domain); | |
5053 | intel_crtc->enabled_power_domains = domains; | |
0e572fe7 DV |
5054 | |
5055 | dev_priv->display.crtc_enable(crtc); | |
5056 | } | |
5057 | } else { | |
5058 | if (intel_crtc->active) { | |
5059 | dev_priv->display.crtc_disable(crtc); | |
5060 | ||
e1e9fb84 DV |
5061 | domains = intel_crtc->enabled_power_domains; |
5062 | for_each_power_domain(domain, domains) | |
5063 | intel_display_power_put(dev_priv, domain); | |
5064 | intel_crtc->enabled_power_domains = 0; | |
0e572fe7 DV |
5065 | } |
5066 | } | |
b04c5bd6 BF |
5067 | } |
5068 | ||
5069 | /** | |
5070 | * Sets the power management mode of the pipe and plane. | |
5071 | */ | |
5072 | void intel_crtc_update_dpms(struct drm_crtc *crtc) | |
5073 | { | |
5074 | struct drm_device *dev = crtc->dev; | |
5075 | struct intel_encoder *intel_encoder; | |
5076 | bool enable = false; | |
5077 | ||
5078 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) | |
5079 | enable |= intel_encoder->connectors_active; | |
5080 | ||
5081 | intel_crtc_control(crtc, enable); | |
976f8a20 DV |
5082 | |
5083 | intel_crtc_update_sarea(crtc, enable); | |
5084 | } | |
5085 | ||
cdd59983 CW |
5086 | static void intel_crtc_disable(struct drm_crtc *crtc) |
5087 | { | |
cdd59983 | 5088 | struct drm_device *dev = crtc->dev; |
976f8a20 | 5089 | struct drm_connector *connector; |
ee7b9f93 | 5090 | struct drm_i915_private *dev_priv = dev->dev_private; |
2ff8fde1 | 5091 | struct drm_i915_gem_object *old_obj = intel_fb_obj(crtc->primary->fb); |
a071fa00 | 5092 | enum pipe pipe = to_intel_crtc(crtc)->pipe; |
cdd59983 | 5093 | |
976f8a20 DV |
5094 | /* crtc should still be enabled when we disable it. */ |
5095 | WARN_ON(!crtc->enabled); | |
5096 | ||
5097 | dev_priv->display.crtc_disable(crtc); | |
5098 | intel_crtc_update_sarea(crtc, false); | |
ee7b9f93 JB |
5099 | dev_priv->display.off(crtc); |
5100 | ||
f4510a27 | 5101 | if (crtc->primary->fb) { |
cdd59983 | 5102 | mutex_lock(&dev->struct_mutex); |
a071fa00 DV |
5103 | intel_unpin_fb_obj(old_obj); |
5104 | i915_gem_track_fb(old_obj, NULL, | |
5105 | INTEL_FRONTBUFFER_PRIMARY(pipe)); | |
cdd59983 | 5106 | mutex_unlock(&dev->struct_mutex); |
f4510a27 | 5107 | crtc->primary->fb = NULL; |
976f8a20 DV |
5108 | } |
5109 | ||
5110 | /* Update computed state. */ | |
5111 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
5112 | if (!connector->encoder || !connector->encoder->crtc) | |
5113 | continue; | |
5114 | ||
5115 | if (connector->encoder->crtc != crtc) | |
5116 | continue; | |
5117 | ||
5118 | connector->dpms = DRM_MODE_DPMS_OFF; | |
5119 | to_intel_encoder(connector->encoder)->connectors_active = false; | |
cdd59983 CW |
5120 | } |
5121 | } | |
5122 | ||
ea5b213a | 5123 | void intel_encoder_destroy(struct drm_encoder *encoder) |
7e7d76c3 | 5124 | { |
4ef69c7a | 5125 | struct intel_encoder *intel_encoder = to_intel_encoder(encoder); |
ea5b213a | 5126 | |
ea5b213a CW |
5127 | drm_encoder_cleanup(encoder); |
5128 | kfree(intel_encoder); | |
7e7d76c3 JB |
5129 | } |
5130 | ||
9237329d | 5131 | /* Simple dpms helper for encoders with just one connector, no cloning and only |
5ab432ef DV |
5132 | * one kind of off state. It clamps all !ON modes to fully OFF and changes the |
5133 | * state of the entire output pipe. */ | |
9237329d | 5134 | static void intel_encoder_dpms(struct intel_encoder *encoder, int mode) |
7e7d76c3 | 5135 | { |
5ab432ef DV |
5136 | if (mode == DRM_MODE_DPMS_ON) { |
5137 | encoder->connectors_active = true; | |
5138 | ||
b2cabb0e | 5139 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef DV |
5140 | } else { |
5141 | encoder->connectors_active = false; | |
5142 | ||
b2cabb0e | 5143 | intel_crtc_update_dpms(encoder->base.crtc); |
5ab432ef | 5144 | } |
79e53945 JB |
5145 | } |
5146 | ||
0a91ca29 DV |
5147 | /* Cross check the actual hw state with our own modeset state tracking (and it's |
5148 | * internal consistency). */ | |
b980514c | 5149 | static void intel_connector_check_state(struct intel_connector *connector) |
79e53945 | 5150 | { |
0a91ca29 DV |
5151 | if (connector->get_hw_state(connector)) { |
5152 | struct intel_encoder *encoder = connector->encoder; | |
5153 | struct drm_crtc *crtc; | |
5154 | bool encoder_enabled; | |
5155 | enum pipe pipe; | |
5156 | ||
5157 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", | |
5158 | connector->base.base.id, | |
c23cc417 | 5159 | connector->base.name); |
0a91ca29 | 5160 | |
0e32b39c DA |
5161 | /* there is no real hw state for MST connectors */ |
5162 | if (connector->mst_port) | |
5163 | return; | |
5164 | ||
0a91ca29 DV |
5165 | WARN(connector->base.dpms == DRM_MODE_DPMS_OFF, |
5166 | "wrong connector dpms state\n"); | |
5167 | WARN(connector->base.encoder != &encoder->base, | |
5168 | "active connector not linked to encoder\n"); | |
0a91ca29 | 5169 | |
36cd7444 DA |
5170 | if (encoder) { |
5171 | WARN(!encoder->connectors_active, | |
5172 | "encoder->connectors_active not set\n"); | |
5173 | ||
5174 | encoder_enabled = encoder->get_hw_state(encoder, &pipe); | |
5175 | WARN(!encoder_enabled, "encoder not enabled\n"); | |
5176 | if (WARN_ON(!encoder->base.crtc)) | |
5177 | return; | |
0a91ca29 | 5178 | |
36cd7444 | 5179 | crtc = encoder->base.crtc; |
0a91ca29 | 5180 | |
36cd7444 DA |
5181 | WARN(!crtc->enabled, "crtc not enabled\n"); |
5182 | WARN(!to_intel_crtc(crtc)->active, "crtc not active\n"); | |
5183 | WARN(pipe != to_intel_crtc(crtc)->pipe, | |
5184 | "encoder active on the wrong pipe\n"); | |
5185 | } | |
0a91ca29 | 5186 | } |
79e53945 JB |
5187 | } |
5188 | ||
5ab432ef DV |
5189 | /* Even simpler default implementation, if there's really no special case to |
5190 | * consider. */ | |
5191 | void intel_connector_dpms(struct drm_connector *connector, int mode) | |
79e53945 | 5192 | { |
5ab432ef DV |
5193 | /* All the simple cases only support two dpms states. */ |
5194 | if (mode != DRM_MODE_DPMS_ON) | |
5195 | mode = DRM_MODE_DPMS_OFF; | |
d4270e57 | 5196 | |
5ab432ef DV |
5197 | if (mode == connector->dpms) |
5198 | return; | |
5199 | ||
5200 | connector->dpms = mode; | |
5201 | ||
5202 | /* Only need to change hw state when actually enabled */ | |
c9976dcf CW |
5203 | if (connector->encoder) |
5204 | intel_encoder_dpms(to_intel_encoder(connector->encoder), mode); | |
0a91ca29 | 5205 | |
b980514c | 5206 | intel_modeset_check_state(connector->dev); |
79e53945 JB |
5207 | } |
5208 | ||
f0947c37 DV |
5209 | /* Simple connector->get_hw_state implementation for encoders that support only |
5210 | * one connector and no cloning and hence the encoder state determines the state | |
5211 | * of the connector. */ | |
5212 | bool intel_connector_get_hw_state(struct intel_connector *connector) | |
ea5b213a | 5213 | { |
24929352 | 5214 | enum pipe pipe = 0; |
f0947c37 | 5215 | struct intel_encoder *encoder = connector->encoder; |
ea5b213a | 5216 | |
f0947c37 | 5217 | return encoder->get_hw_state(encoder, &pipe); |
ea5b213a CW |
5218 | } |
5219 | ||
1857e1da DV |
5220 | static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe, |
5221 | struct intel_crtc_config *pipe_config) | |
5222 | { | |
5223 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5224 | struct intel_crtc *pipe_B_crtc = | |
5225 | to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]); | |
5226 | ||
5227 | DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n", | |
5228 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5229 | if (pipe_config->fdi_lanes > 4) { | |
5230 | DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n", | |
5231 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5232 | return false; | |
5233 | } | |
5234 | ||
bafb6553 | 5235 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
1857e1da DV |
5236 | if (pipe_config->fdi_lanes > 2) { |
5237 | DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n", | |
5238 | pipe_config->fdi_lanes); | |
5239 | return false; | |
5240 | } else { | |
5241 | return true; | |
5242 | } | |
5243 | } | |
5244 | ||
5245 | if (INTEL_INFO(dev)->num_pipes == 2) | |
5246 | return true; | |
5247 | ||
5248 | /* Ivybridge 3 pipe is really complicated */ | |
5249 | switch (pipe) { | |
5250 | case PIPE_A: | |
5251 | return true; | |
5252 | case PIPE_B: | |
5253 | if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled && | |
5254 | pipe_config->fdi_lanes > 2) { | |
5255 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
5256 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5257 | return false; | |
5258 | } | |
5259 | return true; | |
5260 | case PIPE_C: | |
1e833f40 | 5261 | if (!pipe_has_enabled_pch(pipe_B_crtc) || |
1857e1da DV |
5262 | pipe_B_crtc->config.fdi_lanes <= 2) { |
5263 | if (pipe_config->fdi_lanes > 2) { | |
5264 | DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n", | |
5265 | pipe_name(pipe), pipe_config->fdi_lanes); | |
5266 | return false; | |
5267 | } | |
5268 | } else { | |
5269 | DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n"); | |
5270 | return false; | |
5271 | } | |
5272 | return true; | |
5273 | default: | |
5274 | BUG(); | |
5275 | } | |
5276 | } | |
5277 | ||
e29c22c0 DV |
5278 | #define RETRY 1 |
5279 | static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc, | |
5280 | struct intel_crtc_config *pipe_config) | |
877d48d5 | 5281 | { |
1857e1da | 5282 | struct drm_device *dev = intel_crtc->base.dev; |
877d48d5 | 5283 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
ff9a6750 | 5284 | int lane, link_bw, fdi_dotclock; |
e29c22c0 | 5285 | bool setup_ok, needs_recompute = false; |
877d48d5 | 5286 | |
e29c22c0 | 5287 | retry: |
877d48d5 DV |
5288 | /* FDI is a binary signal running at ~2.7GHz, encoding |
5289 | * each output octet as 10 bits. The actual frequency | |
5290 | * is stored as a divider into a 100MHz clock, and the | |
5291 | * mode pixel clock is stored in units of 1KHz. | |
5292 | * Hence the bw of each lane in terms of the mode signal | |
5293 | * is: | |
5294 | */ | |
5295 | link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10; | |
5296 | ||
241bfc38 | 5297 | fdi_dotclock = adjusted_mode->crtc_clock; |
877d48d5 | 5298 | |
2bd89a07 | 5299 | lane = ironlake_get_lanes_required(fdi_dotclock, link_bw, |
877d48d5 DV |
5300 | pipe_config->pipe_bpp); |
5301 | ||
5302 | pipe_config->fdi_lanes = lane; | |
5303 | ||
2bd89a07 | 5304 | intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock, |
877d48d5 | 5305 | link_bw, &pipe_config->fdi_m_n); |
1857e1da | 5306 | |
e29c22c0 DV |
5307 | setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev, |
5308 | intel_crtc->pipe, pipe_config); | |
5309 | if (!setup_ok && pipe_config->pipe_bpp > 6*3) { | |
5310 | pipe_config->pipe_bpp -= 2*3; | |
5311 | DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n", | |
5312 | pipe_config->pipe_bpp); | |
5313 | needs_recompute = true; | |
5314 | pipe_config->bw_constrained = true; | |
5315 | ||
5316 | goto retry; | |
5317 | } | |
5318 | ||
5319 | if (needs_recompute) | |
5320 | return RETRY; | |
5321 | ||
5322 | return setup_ok ? 0 : -EINVAL; | |
877d48d5 DV |
5323 | } |
5324 | ||
42db64ef PZ |
5325 | static void hsw_compute_ips_config(struct intel_crtc *crtc, |
5326 | struct intel_crtc_config *pipe_config) | |
5327 | { | |
d330a953 | 5328 | pipe_config->ips_enabled = i915.enable_ips && |
3c4ca58c | 5329 | hsw_crtc_supports_ips(crtc) && |
b6dfdc9b | 5330 | pipe_config->pipe_bpp <= 24; |
42db64ef PZ |
5331 | } |
5332 | ||
a43f6e0f | 5333 | static int intel_crtc_compute_config(struct intel_crtc *crtc, |
e29c22c0 | 5334 | struct intel_crtc_config *pipe_config) |
79e53945 | 5335 | { |
a43f6e0f | 5336 | struct drm_device *dev = crtc->base.dev; |
b8cecdf5 | 5337 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
89749350 | 5338 | |
ad3a4479 | 5339 | /* FIXME should check pixel clock limits on all platforms */ |
cf532bb2 VS |
5340 | if (INTEL_INFO(dev)->gen < 4) { |
5341 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5342 | int clock_limit = | |
5343 | dev_priv->display.get_display_clock_speed(dev); | |
5344 | ||
5345 | /* | |
5346 | * Enable pixel doubling when the dot clock | |
5347 | * is > 90% of the (display) core speed. | |
5348 | * | |
b397c96b VS |
5349 | * GDG double wide on either pipe, |
5350 | * otherwise pipe A only. | |
cf532bb2 | 5351 | */ |
b397c96b | 5352 | if ((crtc->pipe == PIPE_A || IS_I915G(dev)) && |
241bfc38 | 5353 | adjusted_mode->crtc_clock > clock_limit * 9 / 10) { |
ad3a4479 | 5354 | clock_limit *= 2; |
cf532bb2 | 5355 | pipe_config->double_wide = true; |
ad3a4479 VS |
5356 | } |
5357 | ||
241bfc38 | 5358 | if (adjusted_mode->crtc_clock > clock_limit * 9 / 10) |
e29c22c0 | 5359 | return -EINVAL; |
2c07245f | 5360 | } |
89749350 | 5361 | |
1d1d0e27 VS |
5362 | /* |
5363 | * Pipe horizontal size must be even in: | |
5364 | * - DVO ganged mode | |
5365 | * - LVDS dual channel mode | |
5366 | * - Double wide pipe | |
5367 | */ | |
5368 | if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
5369 | intel_is_dual_link_lvds(dev)) || pipe_config->double_wide) | |
5370 | pipe_config->pipe_src_w &= ~1; | |
5371 | ||
8693a824 DL |
5372 | /* Cantiga+ cannot handle modes with a hsync front porch of 0. |
5373 | * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw. | |
44f46b42 CW |
5374 | */ |
5375 | if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && | |
5376 | adjusted_mode->hsync_start == adjusted_mode->hdisplay) | |
e29c22c0 | 5377 | return -EINVAL; |
44f46b42 | 5378 | |
bd080ee5 | 5379 | if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) { |
5d2d38dd | 5380 | pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */ |
bd080ee5 | 5381 | } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) { |
5d2d38dd DV |
5382 | /* only a 8bpc pipe, with 6bpc dither through the panel fitter |
5383 | * for lvds. */ | |
5384 | pipe_config->pipe_bpp = 8*3; | |
5385 | } | |
5386 | ||
f5adf94e | 5387 | if (HAS_IPS(dev)) |
a43f6e0f DV |
5388 | hsw_compute_ips_config(crtc, pipe_config); |
5389 | ||
12030431 DV |
5390 | /* |
5391 | * XXX: PCH/WRPLL clock sharing is done in ->mode_set, so make sure the | |
5392 | * old clock survives for now. | |
5393 | */ | |
5394 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev) || HAS_DDI(dev)) | |
a43f6e0f | 5395 | pipe_config->shared_dpll = crtc->config.shared_dpll; |
42db64ef | 5396 | |
877d48d5 | 5397 | if (pipe_config->has_pch_encoder) |
a43f6e0f | 5398 | return ironlake_fdi_compute_config(crtc, pipe_config); |
877d48d5 | 5399 | |
e29c22c0 | 5400 | return 0; |
79e53945 JB |
5401 | } |
5402 | ||
25eb05fc JB |
5403 | static int valleyview_get_display_clock_speed(struct drm_device *dev) |
5404 | { | |
d197b7d3 VS |
5405 | struct drm_i915_private *dev_priv = dev->dev_private; |
5406 | int vco = valleyview_get_vco(dev_priv); | |
5407 | u32 val; | |
5408 | int divider; | |
5409 | ||
d49a340d VS |
5410 | /* FIXME: Punit isn't quite ready yet */ |
5411 | if (IS_CHERRYVIEW(dev)) | |
5412 | return 400000; | |
5413 | ||
d197b7d3 VS |
5414 | mutex_lock(&dev_priv->dpio_lock); |
5415 | val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL); | |
5416 | mutex_unlock(&dev_priv->dpio_lock); | |
5417 | ||
5418 | divider = val & DISPLAY_FREQUENCY_VALUES; | |
5419 | ||
7d007f40 VS |
5420 | WARN((val & DISPLAY_FREQUENCY_STATUS) != |
5421 | (divider << DISPLAY_FREQUENCY_STATUS_SHIFT), | |
5422 | "cdclk change in progress\n"); | |
5423 | ||
d197b7d3 | 5424 | return DIV_ROUND_CLOSEST(vco << 1, divider + 1); |
25eb05fc JB |
5425 | } |
5426 | ||
e70236a8 JB |
5427 | static int i945_get_display_clock_speed(struct drm_device *dev) |
5428 | { | |
5429 | return 400000; | |
5430 | } | |
79e53945 | 5431 | |
e70236a8 | 5432 | static int i915_get_display_clock_speed(struct drm_device *dev) |
79e53945 | 5433 | { |
e70236a8 JB |
5434 | return 333000; |
5435 | } | |
79e53945 | 5436 | |
e70236a8 JB |
5437 | static int i9xx_misc_get_display_clock_speed(struct drm_device *dev) |
5438 | { | |
5439 | return 200000; | |
5440 | } | |
79e53945 | 5441 | |
257a7ffc DV |
5442 | static int pnv_get_display_clock_speed(struct drm_device *dev) |
5443 | { | |
5444 | u16 gcfgc = 0; | |
5445 | ||
5446 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); | |
5447 | ||
5448 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5449 | case GC_DISPLAY_CLOCK_267_MHZ_PNV: | |
5450 | return 267000; | |
5451 | case GC_DISPLAY_CLOCK_333_MHZ_PNV: | |
5452 | return 333000; | |
5453 | case GC_DISPLAY_CLOCK_444_MHZ_PNV: | |
5454 | return 444000; | |
5455 | case GC_DISPLAY_CLOCK_200_MHZ_PNV: | |
5456 | return 200000; | |
5457 | default: | |
5458 | DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); | |
5459 | case GC_DISPLAY_CLOCK_133_MHZ_PNV: | |
5460 | return 133000; | |
5461 | case GC_DISPLAY_CLOCK_167_MHZ_PNV: | |
5462 | return 167000; | |
5463 | } | |
5464 | } | |
5465 | ||
e70236a8 JB |
5466 | static int i915gm_get_display_clock_speed(struct drm_device *dev) |
5467 | { | |
5468 | u16 gcfgc = 0; | |
79e53945 | 5469 | |
e70236a8 JB |
5470 | pci_read_config_word(dev->pdev, GCFGC, &gcfgc); |
5471 | ||
5472 | if (gcfgc & GC_LOW_FREQUENCY_ENABLE) | |
5473 | return 133000; | |
5474 | else { | |
5475 | switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { | |
5476 | case GC_DISPLAY_CLOCK_333_MHZ: | |
5477 | return 333000; | |
5478 | default: | |
5479 | case GC_DISPLAY_CLOCK_190_200_MHZ: | |
5480 | return 190000; | |
79e53945 | 5481 | } |
e70236a8 JB |
5482 | } |
5483 | } | |
5484 | ||
5485 | static int i865_get_display_clock_speed(struct drm_device *dev) | |
5486 | { | |
5487 | return 266000; | |
5488 | } | |
5489 | ||
5490 | static int i855_get_display_clock_speed(struct drm_device *dev) | |
5491 | { | |
5492 | u16 hpllcc = 0; | |
5493 | /* Assume that the hardware is in the high speed state. This | |
5494 | * should be the default. | |
5495 | */ | |
5496 | switch (hpllcc & GC_CLOCK_CONTROL_MASK) { | |
5497 | case GC_CLOCK_133_200: | |
5498 | case GC_CLOCK_100_200: | |
5499 | return 200000; | |
5500 | case GC_CLOCK_166_250: | |
5501 | return 250000; | |
5502 | case GC_CLOCK_100_133: | |
79e53945 | 5503 | return 133000; |
e70236a8 | 5504 | } |
79e53945 | 5505 | |
e70236a8 JB |
5506 | /* Shouldn't happen */ |
5507 | return 0; | |
5508 | } | |
79e53945 | 5509 | |
e70236a8 JB |
5510 | static int i830_get_display_clock_speed(struct drm_device *dev) |
5511 | { | |
5512 | return 133000; | |
79e53945 JB |
5513 | } |
5514 | ||
2c07245f | 5515 | static void |
a65851af | 5516 | intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den) |
2c07245f | 5517 | { |
a65851af VS |
5518 | while (*num > DATA_LINK_M_N_MASK || |
5519 | *den > DATA_LINK_M_N_MASK) { | |
2c07245f ZW |
5520 | *num >>= 1; |
5521 | *den >>= 1; | |
5522 | } | |
5523 | } | |
5524 | ||
a65851af VS |
5525 | static void compute_m_n(unsigned int m, unsigned int n, |
5526 | uint32_t *ret_m, uint32_t *ret_n) | |
5527 | { | |
5528 | *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX); | |
5529 | *ret_m = div_u64((uint64_t) m * *ret_n, n); | |
5530 | intel_reduce_m_n_ratio(ret_m, ret_n); | |
5531 | } | |
5532 | ||
e69d0bc1 DV |
5533 | void |
5534 | intel_link_compute_m_n(int bits_per_pixel, int nlanes, | |
5535 | int pixel_clock, int link_clock, | |
5536 | struct intel_link_m_n *m_n) | |
2c07245f | 5537 | { |
e69d0bc1 | 5538 | m_n->tu = 64; |
a65851af VS |
5539 | |
5540 | compute_m_n(bits_per_pixel * pixel_clock, | |
5541 | link_clock * nlanes * 8, | |
5542 | &m_n->gmch_m, &m_n->gmch_n); | |
5543 | ||
5544 | compute_m_n(pixel_clock, link_clock, | |
5545 | &m_n->link_m, &m_n->link_n); | |
2c07245f ZW |
5546 | } |
5547 | ||
a7615030 CW |
5548 | static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv) |
5549 | { | |
d330a953 JN |
5550 | if (i915.panel_use_ssc >= 0) |
5551 | return i915.panel_use_ssc != 0; | |
41aa3448 | 5552 | return dev_priv->vbt.lvds_use_ssc |
435793df | 5553 | && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE); |
a7615030 CW |
5554 | } |
5555 | ||
c65d77d8 JB |
5556 | static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors) |
5557 | { | |
5558 | struct drm_device *dev = crtc->dev; | |
5559 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5560 | int refclk; | |
5561 | ||
a0c4da24 | 5562 | if (IS_VALLEYVIEW(dev)) { |
9a0ea498 | 5563 | refclk = 100000; |
a0c4da24 | 5564 | } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) && |
c65d77d8 | 5565 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) { |
e91e941b VS |
5566 | refclk = dev_priv->vbt.lvds_ssc_freq; |
5567 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk); | |
c65d77d8 JB |
5568 | } else if (!IS_GEN2(dev)) { |
5569 | refclk = 96000; | |
5570 | } else { | |
5571 | refclk = 48000; | |
5572 | } | |
5573 | ||
5574 | return refclk; | |
5575 | } | |
5576 | ||
7429e9d4 | 5577 | static uint32_t pnv_dpll_compute_fp(struct dpll *dpll) |
c65d77d8 | 5578 | { |
7df00d7a | 5579 | return (1 << dpll->n) << 16 | dpll->m2; |
7429e9d4 | 5580 | } |
f47709a9 | 5581 | |
7429e9d4 DV |
5582 | static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll) |
5583 | { | |
5584 | return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; | |
c65d77d8 JB |
5585 | } |
5586 | ||
f47709a9 | 5587 | static void i9xx_update_pll_dividers(struct intel_crtc *crtc, |
a7516a05 JB |
5588 | intel_clock_t *reduced_clock) |
5589 | { | |
f47709a9 | 5590 | struct drm_device *dev = crtc->base.dev; |
a7516a05 JB |
5591 | u32 fp, fp2 = 0; |
5592 | ||
5593 | if (IS_PINEVIEW(dev)) { | |
7429e9d4 | 5594 | fp = pnv_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 5595 | if (reduced_clock) |
7429e9d4 | 5596 | fp2 = pnv_dpll_compute_fp(reduced_clock); |
a7516a05 | 5597 | } else { |
7429e9d4 | 5598 | fp = i9xx_dpll_compute_fp(&crtc->config.dpll); |
a7516a05 | 5599 | if (reduced_clock) |
7429e9d4 | 5600 | fp2 = i9xx_dpll_compute_fp(reduced_clock); |
a7516a05 JB |
5601 | } |
5602 | ||
8bcc2795 | 5603 | crtc->config.dpll_hw_state.fp0 = fp; |
a7516a05 | 5604 | |
f47709a9 DV |
5605 | crtc->lowfreq_avail = false; |
5606 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && | |
d330a953 | 5607 | reduced_clock && i915.powersave) { |
8bcc2795 | 5608 | crtc->config.dpll_hw_state.fp1 = fp2; |
f47709a9 | 5609 | crtc->lowfreq_avail = true; |
a7516a05 | 5610 | } else { |
8bcc2795 | 5611 | crtc->config.dpll_hw_state.fp1 = fp; |
a7516a05 JB |
5612 | } |
5613 | } | |
5614 | ||
5e69f97f CML |
5615 | static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe |
5616 | pipe) | |
89b667f8 JB |
5617 | { |
5618 | u32 reg_val; | |
5619 | ||
5620 | /* | |
5621 | * PLLB opamp always calibrates to max value of 0x3f, force enable it | |
5622 | * and set it to a reasonable value instead. | |
5623 | */ | |
ab3c759a | 5624 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 JB |
5625 | reg_val &= 0xffffff00; |
5626 | reg_val |= 0x00000030; | |
ab3c759a | 5627 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5628 | |
ab3c759a | 5629 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5630 | reg_val &= 0x8cffffff; |
5631 | reg_val = 0x8c000000; | |
ab3c759a | 5632 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 | 5633 | |
ab3c759a | 5634 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); |
89b667f8 | 5635 | reg_val &= 0xffffff00; |
ab3c759a | 5636 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); |
89b667f8 | 5637 | |
ab3c759a | 5638 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); |
89b667f8 JB |
5639 | reg_val &= 0x00ffffff; |
5640 | reg_val |= 0xb0000000; | |
ab3c759a | 5641 | vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); |
89b667f8 JB |
5642 | } |
5643 | ||
b551842d DV |
5644 | static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc, |
5645 | struct intel_link_m_n *m_n) | |
5646 | { | |
5647 | struct drm_device *dev = crtc->base.dev; | |
5648 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5649 | int pipe = crtc->pipe; | |
5650 | ||
e3b95f1e DV |
5651 | I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5652 | I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n); | |
5653 | I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m); | |
5654 | I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n); | |
b551842d DV |
5655 | } |
5656 | ||
5657 | static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, | |
f769cd24 VK |
5658 | struct intel_link_m_n *m_n, |
5659 | struct intel_link_m_n *m2_n2) | |
b551842d DV |
5660 | { |
5661 | struct drm_device *dev = crtc->base.dev; | |
5662 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5663 | int pipe = crtc->pipe; | |
5664 | enum transcoder transcoder = crtc->config.cpu_transcoder; | |
5665 | ||
5666 | if (INTEL_INFO(dev)->gen >= 5) { | |
5667 | I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); | |
5668 | I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); | |
5669 | I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); | |
5670 | I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); | |
f769cd24 VK |
5671 | /* M2_N2 registers to be set only for gen < 8 (M2_N2 available |
5672 | * for gen < 8) and if DRRS is supported (to make sure the | |
5673 | * registers are not unnecessarily accessed). | |
5674 | */ | |
5675 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
5676 | crtc->config.has_drrs) { | |
5677 | I915_WRITE(PIPE_DATA_M2(transcoder), | |
5678 | TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); | |
5679 | I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); | |
5680 | I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); | |
5681 | I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); | |
5682 | } | |
b551842d | 5683 | } else { |
e3b95f1e DV |
5684 | I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m); |
5685 | I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); | |
5686 | I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m); | |
5687 | I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n); | |
b551842d DV |
5688 | } |
5689 | } | |
5690 | ||
f769cd24 | 5691 | void intel_dp_set_m_n(struct intel_crtc *crtc) |
03afc4a2 DV |
5692 | { |
5693 | if (crtc->config.has_pch_encoder) | |
5694 | intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); | |
5695 | else | |
f769cd24 VK |
5696 | intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n, |
5697 | &crtc->config.dp_m2_n2); | |
03afc4a2 DV |
5698 | } |
5699 | ||
f47709a9 | 5700 | static void vlv_update_pll(struct intel_crtc *crtc) |
bdd4b6a6 DV |
5701 | { |
5702 | u32 dpll, dpll_md; | |
5703 | ||
5704 | /* | |
5705 | * Enable DPIO clock input. We should never disable the reference | |
5706 | * clock for pipe B, since VGA hotplug / manual detection depends | |
5707 | * on it. | |
5708 | */ | |
5709 | dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV | | |
5710 | DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV; | |
5711 | /* We should never disable this, set it here for state tracking */ | |
5712 | if (crtc->pipe == PIPE_B) | |
5713 | dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
5714 | dpll |= DPLL_VCO_ENABLE; | |
5715 | crtc->config.dpll_hw_state.dpll = dpll; | |
5716 | ||
5717 | dpll_md = (crtc->config.pixel_multiplier - 1) | |
5718 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
5719 | crtc->config.dpll_hw_state.dpll_md = dpll_md; | |
5720 | } | |
5721 | ||
5722 | static void vlv_prepare_pll(struct intel_crtc *crtc) | |
a0c4da24 | 5723 | { |
f47709a9 | 5724 | struct drm_device *dev = crtc->base.dev; |
a0c4da24 | 5725 | struct drm_i915_private *dev_priv = dev->dev_private; |
f47709a9 | 5726 | int pipe = crtc->pipe; |
bdd4b6a6 | 5727 | u32 mdiv; |
a0c4da24 | 5728 | u32 bestn, bestm1, bestm2, bestp1, bestp2; |
bdd4b6a6 | 5729 | u32 coreclk, reg_val; |
a0c4da24 | 5730 | |
09153000 DV |
5731 | mutex_lock(&dev_priv->dpio_lock); |
5732 | ||
f47709a9 DV |
5733 | bestn = crtc->config.dpll.n; |
5734 | bestm1 = crtc->config.dpll.m1; | |
5735 | bestm2 = crtc->config.dpll.m2; | |
5736 | bestp1 = crtc->config.dpll.p1; | |
5737 | bestp2 = crtc->config.dpll.p2; | |
a0c4da24 | 5738 | |
89b667f8 JB |
5739 | /* See eDP HDMI DPIO driver vbios notes doc */ |
5740 | ||
5741 | /* PLL B needs special handling */ | |
bdd4b6a6 | 5742 | if (pipe == PIPE_B) |
5e69f97f | 5743 | vlv_pllb_recal_opamp(dev_priv, pipe); |
89b667f8 JB |
5744 | |
5745 | /* Set up Tx target for periodic Rcomp update */ | |
ab3c759a | 5746 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); |
89b667f8 JB |
5747 | |
5748 | /* Disable target IRef on PLL */ | |
ab3c759a | 5749 | reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); |
89b667f8 | 5750 | reg_val &= 0x00ffffff; |
ab3c759a | 5751 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); |
89b667f8 JB |
5752 | |
5753 | /* Disable fast lock */ | |
ab3c759a | 5754 | vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); |
89b667f8 JB |
5755 | |
5756 | /* Set idtafcrecal before PLL is enabled */ | |
a0c4da24 JB |
5757 | mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); |
5758 | mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); | |
5759 | mdiv |= ((bestn << DPIO_N_SHIFT)); | |
a0c4da24 | 5760 | mdiv |= (1 << DPIO_K_SHIFT); |
7df5080b JB |
5761 | |
5762 | /* | |
5763 | * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, | |
5764 | * but we don't support that). | |
5765 | * Note: don't use the DAC post divider as it seems unstable. | |
5766 | */ | |
5767 | mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); | |
ab3c759a | 5768 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5769 | |
a0c4da24 | 5770 | mdiv |= DPIO_ENABLE_CALIBRATION; |
ab3c759a | 5771 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); |
a0c4da24 | 5772 | |
89b667f8 | 5773 | /* Set HBR and RBR LPF coefficients */ |
ff9a6750 | 5774 | if (crtc->config.port_clock == 162000 || |
99750bd4 | 5775 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) || |
89b667f8 | 5776 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) |
ab3c759a | 5777 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
885b0120 | 5778 | 0x009f0003); |
89b667f8 | 5779 | else |
ab3c759a | 5780 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), |
89b667f8 JB |
5781 | 0x00d0000f); |
5782 | ||
5783 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) || | |
5784 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) { | |
5785 | /* Use SSC source */ | |
bdd4b6a6 | 5786 | if (pipe == PIPE_A) |
ab3c759a | 5787 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5788 | 0x0df40000); |
5789 | else | |
ab3c759a | 5790 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5791 | 0x0df70000); |
5792 | } else { /* HDMI or VGA */ | |
5793 | /* Use bend source */ | |
bdd4b6a6 | 5794 | if (pipe == PIPE_A) |
ab3c759a | 5795 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5796 | 0x0df70000); |
5797 | else | |
ab3c759a | 5798 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), |
89b667f8 JB |
5799 | 0x0df40000); |
5800 | } | |
a0c4da24 | 5801 | |
ab3c759a | 5802 | coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); |
89b667f8 JB |
5803 | coreclk = (coreclk & 0x0000ff00) | 0x01c00000; |
5804 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) || | |
5805 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP)) | |
5806 | coreclk |= 0x01000000; | |
ab3c759a | 5807 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); |
a0c4da24 | 5808 | |
ab3c759a | 5809 | vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); |
09153000 | 5810 | mutex_unlock(&dev_priv->dpio_lock); |
a0c4da24 JB |
5811 | } |
5812 | ||
9d556c99 | 5813 | static void chv_update_pll(struct intel_crtc *crtc) |
1ae0d137 VS |
5814 | { |
5815 | crtc->config.dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV | | |
5816 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS | | |
5817 | DPLL_VCO_ENABLE; | |
5818 | if (crtc->pipe != PIPE_A) | |
5819 | crtc->config.dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; | |
5820 | ||
5821 | crtc->config.dpll_hw_state.dpll_md = | |
5822 | (crtc->config.pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
5823 | } | |
5824 | ||
5825 | static void chv_prepare_pll(struct intel_crtc *crtc) | |
9d556c99 CML |
5826 | { |
5827 | struct drm_device *dev = crtc->base.dev; | |
5828 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5829 | int pipe = crtc->pipe; | |
5830 | int dpll_reg = DPLL(crtc->pipe); | |
5831 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
580d3811 | 5832 | u32 loopfilter, intcoeff; |
9d556c99 CML |
5833 | u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; |
5834 | int refclk; | |
5835 | ||
9d556c99 CML |
5836 | bestn = crtc->config.dpll.n; |
5837 | bestm2_frac = crtc->config.dpll.m2 & 0x3fffff; | |
5838 | bestm1 = crtc->config.dpll.m1; | |
5839 | bestm2 = crtc->config.dpll.m2 >> 22; | |
5840 | bestp1 = crtc->config.dpll.p1; | |
5841 | bestp2 = crtc->config.dpll.p2; | |
5842 | ||
5843 | /* | |
5844 | * Enable Refclk and SSC | |
5845 | */ | |
a11b0703 VS |
5846 | I915_WRITE(dpll_reg, |
5847 | crtc->config.dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); | |
5848 | ||
5849 | mutex_lock(&dev_priv->dpio_lock); | |
9d556c99 | 5850 | |
9d556c99 CML |
5851 | /* p1 and p2 divider */ |
5852 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), | |
5853 | 5 << DPIO_CHV_S1_DIV_SHIFT | | |
5854 | bestp1 << DPIO_CHV_P1_DIV_SHIFT | | |
5855 | bestp2 << DPIO_CHV_P2_DIV_SHIFT | | |
5856 | 1 << DPIO_CHV_K_DIV_SHIFT); | |
5857 | ||
5858 | /* Feedback post-divider - m2 */ | |
5859 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); | |
5860 | ||
5861 | /* Feedback refclk divider - n and m1 */ | |
5862 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), | |
5863 | DPIO_CHV_M1_DIV_BY_2 | | |
5864 | 1 << DPIO_CHV_N_DIV_SHIFT); | |
5865 | ||
5866 | /* M2 fraction division */ | |
5867 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); | |
5868 | ||
5869 | /* M2 fraction division enable */ | |
5870 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), | |
5871 | DPIO_CHV_FRAC_DIV_EN | | |
5872 | (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT)); | |
5873 | ||
5874 | /* Loop filter */ | |
5875 | refclk = i9xx_get_refclk(&crtc->base, 0); | |
5876 | loopfilter = 5 << DPIO_CHV_PROP_COEFF_SHIFT | | |
5877 | 2 << DPIO_CHV_GAIN_CTRL_SHIFT; | |
5878 | if (refclk == 100000) | |
5879 | intcoeff = 11; | |
5880 | else if (refclk == 38400) | |
5881 | intcoeff = 10; | |
5882 | else | |
5883 | intcoeff = 9; | |
5884 | loopfilter |= intcoeff << DPIO_CHV_INT_COEFF_SHIFT; | |
5885 | vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); | |
5886 | ||
5887 | /* AFC Recal */ | |
5888 | vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), | |
5889 | vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | | |
5890 | DPIO_AFC_RECAL); | |
5891 | ||
5892 | mutex_unlock(&dev_priv->dpio_lock); | |
5893 | } | |
5894 | ||
f47709a9 DV |
5895 | static void i9xx_update_pll(struct intel_crtc *crtc, |
5896 | intel_clock_t *reduced_clock, | |
eb1cbe48 DV |
5897 | int num_connectors) |
5898 | { | |
f47709a9 | 5899 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5900 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 DV |
5901 | u32 dpll; |
5902 | bool is_sdvo; | |
f47709a9 | 5903 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5904 | |
f47709a9 | 5905 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5906 | |
f47709a9 DV |
5907 | is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) || |
5908 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI); | |
eb1cbe48 DV |
5909 | |
5910 | dpll = DPLL_VGA_MODE_DIS; | |
5911 | ||
f47709a9 | 5912 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) |
eb1cbe48 DV |
5913 | dpll |= DPLLB_MODE_LVDS; |
5914 | else | |
5915 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
6cc5f341 | 5916 | |
ef1b460d | 5917 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
198a037f DV |
5918 | dpll |= (crtc->config.pixel_multiplier - 1) |
5919 | << SDVO_MULTIPLIER_SHIFT_HIRES; | |
eb1cbe48 | 5920 | } |
198a037f DV |
5921 | |
5922 | if (is_sdvo) | |
4a33e48d | 5923 | dpll |= DPLL_SDVO_HIGH_SPEED; |
198a037f | 5924 | |
f47709a9 | 5925 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) |
4a33e48d | 5926 | dpll |= DPLL_SDVO_HIGH_SPEED; |
eb1cbe48 DV |
5927 | |
5928 | /* compute bitmask from p1 value */ | |
5929 | if (IS_PINEVIEW(dev)) | |
5930 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; | |
5931 | else { | |
5932 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5933 | if (IS_G4X(dev) && reduced_clock) | |
5934 | dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; | |
5935 | } | |
5936 | switch (clock->p2) { | |
5937 | case 5: | |
5938 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
5939 | break; | |
5940 | case 7: | |
5941 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
5942 | break; | |
5943 | case 10: | |
5944 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
5945 | break; | |
5946 | case 14: | |
5947 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
5948 | break; | |
5949 | } | |
5950 | if (INTEL_INFO(dev)->gen >= 4) | |
5951 | dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); | |
5952 | ||
09ede541 | 5953 | if (crtc->config.sdvo_tv_clock) |
eb1cbe48 | 5954 | dpll |= PLL_REF_INPUT_TVCLKINBC; |
f47709a9 | 5955 | else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5956 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
5957 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
5958 | else | |
5959 | dpll |= PLL_REF_INPUT_DREFCLK; | |
5960 | ||
5961 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 DV |
5962 | crtc->config.dpll_hw_state.dpll = dpll; |
5963 | ||
eb1cbe48 | 5964 | if (INTEL_INFO(dev)->gen >= 4) { |
ef1b460d DV |
5965 | u32 dpll_md = (crtc->config.pixel_multiplier - 1) |
5966 | << DPLL_MD_UDI_MULTIPLIER_SHIFT; | |
8bcc2795 | 5967 | crtc->config.dpll_hw_state.dpll_md = dpll_md; |
eb1cbe48 DV |
5968 | } |
5969 | } | |
5970 | ||
f47709a9 | 5971 | static void i8xx_update_pll(struct intel_crtc *crtc, |
f47709a9 | 5972 | intel_clock_t *reduced_clock, |
eb1cbe48 DV |
5973 | int num_connectors) |
5974 | { | |
f47709a9 | 5975 | struct drm_device *dev = crtc->base.dev; |
eb1cbe48 | 5976 | struct drm_i915_private *dev_priv = dev->dev_private; |
eb1cbe48 | 5977 | u32 dpll; |
f47709a9 | 5978 | struct dpll *clock = &crtc->config.dpll; |
eb1cbe48 | 5979 | |
f47709a9 | 5980 | i9xx_update_pll_dividers(crtc, reduced_clock); |
2a8f64ca | 5981 | |
eb1cbe48 DV |
5982 | dpll = DPLL_VGA_MODE_DIS; |
5983 | ||
f47709a9 | 5984 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) { |
eb1cbe48 DV |
5985 | dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
5986 | } else { | |
5987 | if (clock->p1 == 2) | |
5988 | dpll |= PLL_P1_DIVIDE_BY_TWO; | |
5989 | else | |
5990 | dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; | |
5991 | if (clock->p2 == 4) | |
5992 | dpll |= PLL_P2_DIVIDE_BY_4; | |
5993 | } | |
5994 | ||
1c4e0274 | 5995 | if (!IS_I830(dev) && intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO)) |
4a33e48d DV |
5996 | dpll |= DPLL_DVO_2X_MODE; |
5997 | ||
f47709a9 | 5998 | if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) && |
eb1cbe48 DV |
5999 | intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
6000 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; | |
6001 | else | |
6002 | dpll |= PLL_REF_INPUT_DREFCLK; | |
6003 | ||
6004 | dpll |= DPLL_VCO_ENABLE; | |
8bcc2795 | 6005 | crtc->config.dpll_hw_state.dpll = dpll; |
eb1cbe48 DV |
6006 | } |
6007 | ||
8a654f3b | 6008 | static void intel_set_pipe_timings(struct intel_crtc *intel_crtc) |
b0e77b9c PZ |
6009 | { |
6010 | struct drm_device *dev = intel_crtc->base.dev; | |
6011 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6012 | enum pipe pipe = intel_crtc->pipe; | |
3b117c8f | 6013 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
8a654f3b DV |
6014 | struct drm_display_mode *adjusted_mode = |
6015 | &intel_crtc->config.adjusted_mode; | |
1caea6e9 VS |
6016 | uint32_t crtc_vtotal, crtc_vblank_end; |
6017 | int vsyncshift = 0; | |
4d8a62ea DV |
6018 | |
6019 | /* We need to be careful not to changed the adjusted mode, for otherwise | |
6020 | * the hw state checker will get angry at the mismatch. */ | |
6021 | crtc_vtotal = adjusted_mode->crtc_vtotal; | |
6022 | crtc_vblank_end = adjusted_mode->crtc_vblank_end; | |
b0e77b9c | 6023 | |
609aeaca | 6024 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) { |
b0e77b9c | 6025 | /* the chip adds 2 halflines automatically */ |
4d8a62ea DV |
6026 | crtc_vtotal -= 1; |
6027 | crtc_vblank_end -= 1; | |
609aeaca VS |
6028 | |
6029 | if (intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) | |
6030 | vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2; | |
6031 | else | |
6032 | vsyncshift = adjusted_mode->crtc_hsync_start - | |
6033 | adjusted_mode->crtc_htotal / 2; | |
1caea6e9 VS |
6034 | if (vsyncshift < 0) |
6035 | vsyncshift += adjusted_mode->crtc_htotal; | |
b0e77b9c PZ |
6036 | } |
6037 | ||
6038 | if (INTEL_INFO(dev)->gen > 3) | |
fe2b8f9d | 6039 | I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift); |
b0e77b9c | 6040 | |
fe2b8f9d | 6041 | I915_WRITE(HTOTAL(cpu_transcoder), |
b0e77b9c PZ |
6042 | (adjusted_mode->crtc_hdisplay - 1) | |
6043 | ((adjusted_mode->crtc_htotal - 1) << 16)); | |
fe2b8f9d | 6044 | I915_WRITE(HBLANK(cpu_transcoder), |
b0e77b9c PZ |
6045 | (adjusted_mode->crtc_hblank_start - 1) | |
6046 | ((adjusted_mode->crtc_hblank_end - 1) << 16)); | |
fe2b8f9d | 6047 | I915_WRITE(HSYNC(cpu_transcoder), |
b0e77b9c PZ |
6048 | (adjusted_mode->crtc_hsync_start - 1) | |
6049 | ((adjusted_mode->crtc_hsync_end - 1) << 16)); | |
6050 | ||
fe2b8f9d | 6051 | I915_WRITE(VTOTAL(cpu_transcoder), |
b0e77b9c | 6052 | (adjusted_mode->crtc_vdisplay - 1) | |
4d8a62ea | 6053 | ((crtc_vtotal - 1) << 16)); |
fe2b8f9d | 6054 | I915_WRITE(VBLANK(cpu_transcoder), |
b0e77b9c | 6055 | (adjusted_mode->crtc_vblank_start - 1) | |
4d8a62ea | 6056 | ((crtc_vblank_end - 1) << 16)); |
fe2b8f9d | 6057 | I915_WRITE(VSYNC(cpu_transcoder), |
b0e77b9c PZ |
6058 | (adjusted_mode->crtc_vsync_start - 1) | |
6059 | ((adjusted_mode->crtc_vsync_end - 1) << 16)); | |
6060 | ||
b5e508d4 PZ |
6061 | /* Workaround: when the EDP input selection is B, the VTOTAL_B must be |
6062 | * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is | |
6063 | * documented on the DDI_FUNC_CTL register description, EDP Input Select | |
6064 | * bits. */ | |
6065 | if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP && | |
6066 | (pipe == PIPE_B || pipe == PIPE_C)) | |
6067 | I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder))); | |
6068 | ||
b0e77b9c PZ |
6069 | /* pipesrc controls the size that is scaled from, which should |
6070 | * always be the user's requested size. | |
6071 | */ | |
6072 | I915_WRITE(PIPESRC(pipe), | |
37327abd VS |
6073 | ((intel_crtc->config.pipe_src_w - 1) << 16) | |
6074 | (intel_crtc->config.pipe_src_h - 1)); | |
b0e77b9c PZ |
6075 | } |
6076 | ||
1bd1bd80 DV |
6077 | static void intel_get_pipe_timings(struct intel_crtc *crtc, |
6078 | struct intel_crtc_config *pipe_config) | |
6079 | { | |
6080 | struct drm_device *dev = crtc->base.dev; | |
6081 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6082 | enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; | |
6083 | uint32_t tmp; | |
6084 | ||
6085 | tmp = I915_READ(HTOTAL(cpu_transcoder)); | |
6086 | pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1; | |
6087 | pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1; | |
6088 | tmp = I915_READ(HBLANK(cpu_transcoder)); | |
6089 | pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1; | |
6090 | pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1; | |
6091 | tmp = I915_READ(HSYNC(cpu_transcoder)); | |
6092 | pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1; | |
6093 | pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1; | |
6094 | ||
6095 | tmp = I915_READ(VTOTAL(cpu_transcoder)); | |
6096 | pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1; | |
6097 | pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1; | |
6098 | tmp = I915_READ(VBLANK(cpu_transcoder)); | |
6099 | pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1; | |
6100 | pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1; | |
6101 | tmp = I915_READ(VSYNC(cpu_transcoder)); | |
6102 | pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1; | |
6103 | pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1; | |
6104 | ||
6105 | if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) { | |
6106 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE; | |
6107 | pipe_config->adjusted_mode.crtc_vtotal += 1; | |
6108 | pipe_config->adjusted_mode.crtc_vblank_end += 1; | |
6109 | } | |
6110 | ||
6111 | tmp = I915_READ(PIPESRC(crtc->pipe)); | |
37327abd VS |
6112 | pipe_config->pipe_src_h = (tmp & 0xffff) + 1; |
6113 | pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1; | |
6114 | ||
6115 | pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h; | |
6116 | pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w; | |
1bd1bd80 DV |
6117 | } |
6118 | ||
f6a83288 DV |
6119 | void intel_mode_from_pipe_config(struct drm_display_mode *mode, |
6120 | struct intel_crtc_config *pipe_config) | |
babea61d | 6121 | { |
f6a83288 DV |
6122 | mode->hdisplay = pipe_config->adjusted_mode.crtc_hdisplay; |
6123 | mode->htotal = pipe_config->adjusted_mode.crtc_htotal; | |
6124 | mode->hsync_start = pipe_config->adjusted_mode.crtc_hsync_start; | |
6125 | mode->hsync_end = pipe_config->adjusted_mode.crtc_hsync_end; | |
babea61d | 6126 | |
f6a83288 DV |
6127 | mode->vdisplay = pipe_config->adjusted_mode.crtc_vdisplay; |
6128 | mode->vtotal = pipe_config->adjusted_mode.crtc_vtotal; | |
6129 | mode->vsync_start = pipe_config->adjusted_mode.crtc_vsync_start; | |
6130 | mode->vsync_end = pipe_config->adjusted_mode.crtc_vsync_end; | |
babea61d | 6131 | |
f6a83288 | 6132 | mode->flags = pipe_config->adjusted_mode.flags; |
babea61d | 6133 | |
f6a83288 DV |
6134 | mode->clock = pipe_config->adjusted_mode.crtc_clock; |
6135 | mode->flags |= pipe_config->adjusted_mode.flags; | |
babea61d JB |
6136 | } |
6137 | ||
84b046f3 DV |
6138 | static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc) |
6139 | { | |
6140 | struct drm_device *dev = intel_crtc->base.dev; | |
6141 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6142 | uint32_t pipeconf; | |
6143 | ||
9f11a9e4 | 6144 | pipeconf = 0; |
84b046f3 | 6145 | |
b6b5d049 VS |
6146 | if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || |
6147 | (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
6148 | pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE; | |
67c72a12 | 6149 | |
cf532bb2 VS |
6150 | if (intel_crtc->config.double_wide) |
6151 | pipeconf |= PIPECONF_DOUBLE_WIDE; | |
84b046f3 | 6152 | |
ff9ce46e DV |
6153 | /* only g4x and later have fancy bpc/dither controls */ |
6154 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { | |
ff9ce46e DV |
6155 | /* Bspec claims that we can't use dithering for 30bpp pipes. */ |
6156 | if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30) | |
6157 | pipeconf |= PIPECONF_DITHER_EN | | |
84b046f3 | 6158 | PIPECONF_DITHER_TYPE_SP; |
84b046f3 | 6159 | |
ff9ce46e DV |
6160 | switch (intel_crtc->config.pipe_bpp) { |
6161 | case 18: | |
6162 | pipeconf |= PIPECONF_6BPC; | |
6163 | break; | |
6164 | case 24: | |
6165 | pipeconf |= PIPECONF_8BPC; | |
6166 | break; | |
6167 | case 30: | |
6168 | pipeconf |= PIPECONF_10BPC; | |
6169 | break; | |
6170 | default: | |
6171 | /* Case prevented by intel_choose_pipe_bpp_dither. */ | |
6172 | BUG(); | |
84b046f3 DV |
6173 | } |
6174 | } | |
6175 | ||
6176 | if (HAS_PIPE_CXSR(dev)) { | |
6177 | if (intel_crtc->lowfreq_avail) { | |
6178 | DRM_DEBUG_KMS("enabling CxSR downclocking\n"); | |
6179 | pipeconf |= PIPECONF_CXSR_DOWNCLOCK; | |
6180 | } else { | |
6181 | DRM_DEBUG_KMS("disabling CxSR downclocking\n"); | |
84b046f3 DV |
6182 | } |
6183 | } | |
6184 | ||
efc2cfff VS |
6185 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) { |
6186 | if (INTEL_INFO(dev)->gen < 4 || | |
6187 | intel_pipe_has_type(&intel_crtc->base, INTEL_OUTPUT_SDVO)) | |
6188 | pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; | |
6189 | else | |
6190 | pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT; | |
6191 | } else | |
84b046f3 DV |
6192 | pipeconf |= PIPECONF_PROGRESSIVE; |
6193 | ||
9f11a9e4 DV |
6194 | if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range) |
6195 | pipeconf |= PIPECONF_COLOR_RANGE_SELECT; | |
9c8e09b7 | 6196 | |
84b046f3 DV |
6197 | I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf); |
6198 | POSTING_READ(PIPECONF(intel_crtc->pipe)); | |
6199 | } | |
6200 | ||
f564048e | 6201 | static int i9xx_crtc_mode_set(struct drm_crtc *crtc, |
f564048e | 6202 | int x, int y, |
94352cf9 | 6203 | struct drm_framebuffer *fb) |
79e53945 JB |
6204 | { |
6205 | struct drm_device *dev = crtc->dev; | |
6206 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6207 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
c751ce4f | 6208 | int refclk, num_connectors = 0; |
652c393a | 6209 | intel_clock_t clock, reduced_clock; |
a16af721 | 6210 | bool ok, has_reduced_clock = false; |
e9fd1c02 | 6211 | bool is_lvds = false, is_dsi = false; |
5eddb70b | 6212 | struct intel_encoder *encoder; |
d4906093 | 6213 | const intel_limit_t *limit; |
79e53945 | 6214 | |
6c2b7c12 | 6215 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
5eddb70b | 6216 | switch (encoder->type) { |
79e53945 JB |
6217 | case INTEL_OUTPUT_LVDS: |
6218 | is_lvds = true; | |
6219 | break; | |
e9fd1c02 JN |
6220 | case INTEL_OUTPUT_DSI: |
6221 | is_dsi = true; | |
6222 | break; | |
79e53945 | 6223 | } |
43565a06 | 6224 | |
c751ce4f | 6225 | num_connectors++; |
79e53945 JB |
6226 | } |
6227 | ||
f2335330 | 6228 | if (is_dsi) |
5b18e57c | 6229 | return 0; |
f2335330 JN |
6230 | |
6231 | if (!intel_crtc->config.clock_set) { | |
6232 | refclk = i9xx_get_refclk(crtc, num_connectors); | |
79e53945 | 6233 | |
e9fd1c02 JN |
6234 | /* |
6235 | * Returns a set of divisors for the desired target clock with | |
6236 | * the given refclk, or FALSE. The returned values represent | |
6237 | * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + | |
6238 | * 2) / p1 / p2. | |
6239 | */ | |
6240 | limit = intel_limit(crtc, refclk); | |
6241 | ok = dev_priv->display.find_dpll(limit, crtc, | |
6242 | intel_crtc->config.port_clock, | |
6243 | refclk, NULL, &clock); | |
f2335330 | 6244 | if (!ok) { |
e9fd1c02 JN |
6245 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
6246 | return -EINVAL; | |
6247 | } | |
79e53945 | 6248 | |
f2335330 JN |
6249 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
6250 | /* | |
6251 | * Ensure we match the reduced clock's P to the target | |
6252 | * clock. If the clocks don't match, we can't switch | |
6253 | * the display clock by using the FP0/FP1. In such case | |
6254 | * we will disable the LVDS downclock feature. | |
6255 | */ | |
6256 | has_reduced_clock = | |
6257 | dev_priv->display.find_dpll(limit, crtc, | |
6258 | dev_priv->lvds_downclock, | |
6259 | refclk, &clock, | |
6260 | &reduced_clock); | |
6261 | } | |
6262 | /* Compat-code for transition, will disappear. */ | |
f47709a9 DV |
6263 | intel_crtc->config.dpll.n = clock.n; |
6264 | intel_crtc->config.dpll.m1 = clock.m1; | |
6265 | intel_crtc->config.dpll.m2 = clock.m2; | |
6266 | intel_crtc->config.dpll.p1 = clock.p1; | |
6267 | intel_crtc->config.dpll.p2 = clock.p2; | |
6268 | } | |
7026d4ac | 6269 | |
e9fd1c02 | 6270 | if (IS_GEN2(dev)) { |
8a654f3b | 6271 | i8xx_update_pll(intel_crtc, |
2a8f64ca VP |
6272 | has_reduced_clock ? &reduced_clock : NULL, |
6273 | num_connectors); | |
9d556c99 CML |
6274 | } else if (IS_CHERRYVIEW(dev)) { |
6275 | chv_update_pll(intel_crtc); | |
e9fd1c02 | 6276 | } else if (IS_VALLEYVIEW(dev)) { |
f2335330 | 6277 | vlv_update_pll(intel_crtc); |
e9fd1c02 | 6278 | } else { |
f47709a9 | 6279 | i9xx_update_pll(intel_crtc, |
eb1cbe48 | 6280 | has_reduced_clock ? &reduced_clock : NULL, |
eba905b2 | 6281 | num_connectors); |
e9fd1c02 | 6282 | } |
79e53945 | 6283 | |
c8f7a0db | 6284 | return 0; |
f564048e EA |
6285 | } |
6286 | ||
2fa2fe9a DV |
6287 | static void i9xx_get_pfit_config(struct intel_crtc *crtc, |
6288 | struct intel_crtc_config *pipe_config) | |
6289 | { | |
6290 | struct drm_device *dev = crtc->base.dev; | |
6291 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6292 | uint32_t tmp; | |
6293 | ||
dc9e7dec VS |
6294 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
6295 | return; | |
6296 | ||
2fa2fe9a | 6297 | tmp = I915_READ(PFIT_CONTROL); |
06922821 DV |
6298 | if (!(tmp & PFIT_ENABLE)) |
6299 | return; | |
2fa2fe9a | 6300 | |
06922821 | 6301 | /* Check whether the pfit is attached to our pipe. */ |
2fa2fe9a DV |
6302 | if (INTEL_INFO(dev)->gen < 4) { |
6303 | if (crtc->pipe != PIPE_B) | |
6304 | return; | |
2fa2fe9a DV |
6305 | } else { |
6306 | if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT)) | |
6307 | return; | |
6308 | } | |
6309 | ||
06922821 | 6310 | pipe_config->gmch_pfit.control = tmp; |
2fa2fe9a DV |
6311 | pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS); |
6312 | if (INTEL_INFO(dev)->gen < 5) | |
6313 | pipe_config->gmch_pfit.lvds_border_bits = | |
6314 | I915_READ(LVDS) & LVDS_BORDER_ENABLE; | |
6315 | } | |
6316 | ||
acbec814 JB |
6317 | static void vlv_crtc_clock_get(struct intel_crtc *crtc, |
6318 | struct intel_crtc_config *pipe_config) | |
6319 | { | |
6320 | struct drm_device *dev = crtc->base.dev; | |
6321 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6322 | int pipe = pipe_config->cpu_transcoder; | |
6323 | intel_clock_t clock; | |
6324 | u32 mdiv; | |
662c6ecb | 6325 | int refclk = 100000; |
acbec814 | 6326 | |
f573de5a SK |
6327 | /* In case of MIPI DPLL will not even be used */ |
6328 | if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE)) | |
6329 | return; | |
6330 | ||
acbec814 | 6331 | mutex_lock(&dev_priv->dpio_lock); |
ab3c759a | 6332 | mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe)); |
acbec814 JB |
6333 | mutex_unlock(&dev_priv->dpio_lock); |
6334 | ||
6335 | clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7; | |
6336 | clock.m2 = mdiv & DPIO_M2DIV_MASK; | |
6337 | clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf; | |
6338 | clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7; | |
6339 | clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f; | |
6340 | ||
f646628b | 6341 | vlv_clock(refclk, &clock); |
acbec814 | 6342 | |
f646628b VS |
6343 | /* clock.dot is the fast clock */ |
6344 | pipe_config->port_clock = clock.dot / 5; | |
acbec814 JB |
6345 | } |
6346 | ||
1ad292b5 JB |
6347 | static void i9xx_get_plane_config(struct intel_crtc *crtc, |
6348 | struct intel_plane_config *plane_config) | |
6349 | { | |
6350 | struct drm_device *dev = crtc->base.dev; | |
6351 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6352 | u32 val, base, offset; | |
6353 | int pipe = crtc->pipe, plane = crtc->plane; | |
6354 | int fourcc, pixel_format; | |
6355 | int aligned_height; | |
6356 | ||
66e514c1 DA |
6357 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
6358 | if (!crtc->base.primary->fb) { | |
1ad292b5 JB |
6359 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
6360 | return; | |
6361 | } | |
6362 | ||
6363 | val = I915_READ(DSPCNTR(plane)); | |
6364 | ||
6365 | if (INTEL_INFO(dev)->gen >= 4) | |
6366 | if (val & DISPPLANE_TILED) | |
6367 | plane_config->tiled = true; | |
6368 | ||
6369 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
6370 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
6371 | crtc->base.primary->fb->pixel_format = fourcc; |
6372 | crtc->base.primary->fb->bits_per_pixel = | |
1ad292b5 JB |
6373 | drm_format_plane_cpp(fourcc, 0) * 8; |
6374 | ||
6375 | if (INTEL_INFO(dev)->gen >= 4) { | |
6376 | if (plane_config->tiled) | |
6377 | offset = I915_READ(DSPTILEOFF(plane)); | |
6378 | else | |
6379 | offset = I915_READ(DSPLINOFF(plane)); | |
6380 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
6381 | } else { | |
6382 | base = I915_READ(DSPADDR(plane)); | |
6383 | } | |
6384 | plane_config->base = base; | |
6385 | ||
6386 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
6387 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
6388 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
1ad292b5 JB |
6389 | |
6390 | val = I915_READ(DSPSTRIDE(pipe)); | |
026b96e2 | 6391 | crtc->base.primary->fb->pitches[0] = val & 0xffffffc0; |
1ad292b5 | 6392 | |
66e514c1 | 6393 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
1ad292b5 JB |
6394 | plane_config->tiled); |
6395 | ||
1267a26b FF |
6396 | plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] * |
6397 | aligned_height); | |
1ad292b5 JB |
6398 | |
6399 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
6400 | pipe, plane, crtc->base.primary->fb->width, |
6401 | crtc->base.primary->fb->height, | |
6402 | crtc->base.primary->fb->bits_per_pixel, base, | |
6403 | crtc->base.primary->fb->pitches[0], | |
1ad292b5 JB |
6404 | plane_config->size); |
6405 | ||
6406 | } | |
6407 | ||
70b23a98 VS |
6408 | static void chv_crtc_clock_get(struct intel_crtc *crtc, |
6409 | struct intel_crtc_config *pipe_config) | |
6410 | { | |
6411 | struct drm_device *dev = crtc->base.dev; | |
6412 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6413 | int pipe = pipe_config->cpu_transcoder; | |
6414 | enum dpio_channel port = vlv_pipe_to_channel(pipe); | |
6415 | intel_clock_t clock; | |
6416 | u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2; | |
6417 | int refclk = 100000; | |
6418 | ||
6419 | mutex_lock(&dev_priv->dpio_lock); | |
6420 | cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port)); | |
6421 | pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port)); | |
6422 | pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port)); | |
6423 | pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port)); | |
6424 | mutex_unlock(&dev_priv->dpio_lock); | |
6425 | ||
6426 | clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0; | |
6427 | clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff); | |
6428 | clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf; | |
6429 | clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7; | |
6430 | clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f; | |
6431 | ||
6432 | chv_clock(refclk, &clock); | |
6433 | ||
6434 | /* clock.dot is the fast clock */ | |
6435 | pipe_config->port_clock = clock.dot / 5; | |
6436 | } | |
6437 | ||
0e8ffe1b DV |
6438 | static bool i9xx_get_pipe_config(struct intel_crtc *crtc, |
6439 | struct intel_crtc_config *pipe_config) | |
6440 | { | |
6441 | struct drm_device *dev = crtc->base.dev; | |
6442 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6443 | uint32_t tmp; | |
6444 | ||
b5482bd0 ID |
6445 | if (!intel_display_power_enabled(dev_priv, |
6446 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
6447 | return false; | |
6448 | ||
e143a21c | 6449 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 6450 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 6451 | |
0e8ffe1b DV |
6452 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
6453 | if (!(tmp & PIPECONF_ENABLE)) | |
6454 | return false; | |
6455 | ||
42571aef VS |
6456 | if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) { |
6457 | switch (tmp & PIPECONF_BPC_MASK) { | |
6458 | case PIPECONF_6BPC: | |
6459 | pipe_config->pipe_bpp = 18; | |
6460 | break; | |
6461 | case PIPECONF_8BPC: | |
6462 | pipe_config->pipe_bpp = 24; | |
6463 | break; | |
6464 | case PIPECONF_10BPC: | |
6465 | pipe_config->pipe_bpp = 30; | |
6466 | break; | |
6467 | default: | |
6468 | break; | |
6469 | } | |
6470 | } | |
6471 | ||
b5a9fa09 DV |
6472 | if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT)) |
6473 | pipe_config->limited_color_range = true; | |
6474 | ||
282740f7 VS |
6475 | if (INTEL_INFO(dev)->gen < 4) |
6476 | pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE; | |
6477 | ||
1bd1bd80 DV |
6478 | intel_get_pipe_timings(crtc, pipe_config); |
6479 | ||
2fa2fe9a DV |
6480 | i9xx_get_pfit_config(crtc, pipe_config); |
6481 | ||
6c49f241 DV |
6482 | if (INTEL_INFO(dev)->gen >= 4) { |
6483 | tmp = I915_READ(DPLL_MD(crtc->pipe)); | |
6484 | pipe_config->pixel_multiplier = | |
6485 | ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK) | |
6486 | >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1; | |
8bcc2795 | 6487 | pipe_config->dpll_hw_state.dpll_md = tmp; |
6c49f241 DV |
6488 | } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) { |
6489 | tmp = I915_READ(DPLL(crtc->pipe)); | |
6490 | pipe_config->pixel_multiplier = | |
6491 | ((tmp & SDVO_MULTIPLIER_MASK) | |
6492 | >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1; | |
6493 | } else { | |
6494 | /* Note that on i915G/GM the pixel multiplier is in the sdvo | |
6495 | * port and will be fixed up in the encoder->get_config | |
6496 | * function. */ | |
6497 | pipe_config->pixel_multiplier = 1; | |
6498 | } | |
8bcc2795 DV |
6499 | pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe)); |
6500 | if (!IS_VALLEYVIEW(dev)) { | |
1c4e0274 VS |
6501 | /* |
6502 | * DPLL_DVO_2X_MODE must be enabled for both DPLLs | |
6503 | * on 830. Filter it out here so that we don't | |
6504 | * report errors due to that. | |
6505 | */ | |
6506 | if (IS_I830(dev)) | |
6507 | pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE; | |
6508 | ||
8bcc2795 DV |
6509 | pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe)); |
6510 | pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe)); | |
165e901c VS |
6511 | } else { |
6512 | /* Mask out read-only status bits. */ | |
6513 | pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV | | |
6514 | DPLL_PORTC_READY_MASK | | |
6515 | DPLL_PORTB_READY_MASK); | |
8bcc2795 | 6516 | } |
6c49f241 | 6517 | |
70b23a98 VS |
6518 | if (IS_CHERRYVIEW(dev)) |
6519 | chv_crtc_clock_get(crtc, pipe_config); | |
6520 | else if (IS_VALLEYVIEW(dev)) | |
acbec814 JB |
6521 | vlv_crtc_clock_get(crtc, pipe_config); |
6522 | else | |
6523 | i9xx_crtc_clock_get(crtc, pipe_config); | |
18442d08 | 6524 | |
0e8ffe1b DV |
6525 | return true; |
6526 | } | |
6527 | ||
dde86e2d | 6528 | static void ironlake_init_pch_refclk(struct drm_device *dev) |
13d83a67 JB |
6529 | { |
6530 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13d83a67 | 6531 | struct intel_encoder *encoder; |
74cfd7ac | 6532 | u32 val, final; |
13d83a67 | 6533 | bool has_lvds = false; |
199e5d79 | 6534 | bool has_cpu_edp = false; |
199e5d79 | 6535 | bool has_panel = false; |
99eb6a01 KP |
6536 | bool has_ck505 = false; |
6537 | bool can_ssc = false; | |
13d83a67 JB |
6538 | |
6539 | /* We need to take the global config into account */ | |
b2784e15 | 6540 | for_each_intel_encoder(dev, encoder) { |
199e5d79 KP |
6541 | switch (encoder->type) { |
6542 | case INTEL_OUTPUT_LVDS: | |
6543 | has_panel = true; | |
6544 | has_lvds = true; | |
6545 | break; | |
6546 | case INTEL_OUTPUT_EDP: | |
6547 | has_panel = true; | |
2de6905f | 6548 | if (enc_to_dig_port(&encoder->base)->port == PORT_A) |
199e5d79 KP |
6549 | has_cpu_edp = true; |
6550 | break; | |
13d83a67 JB |
6551 | } |
6552 | } | |
6553 | ||
99eb6a01 | 6554 | if (HAS_PCH_IBX(dev)) { |
41aa3448 | 6555 | has_ck505 = dev_priv->vbt.display_clock_mode; |
99eb6a01 KP |
6556 | can_ssc = has_ck505; |
6557 | } else { | |
6558 | has_ck505 = false; | |
6559 | can_ssc = true; | |
6560 | } | |
6561 | ||
2de6905f ID |
6562 | DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n", |
6563 | has_panel, has_lvds, has_ck505); | |
13d83a67 JB |
6564 | |
6565 | /* Ironlake: try to setup display ref clock before DPLL | |
6566 | * enabling. This is only under driver's control after | |
6567 | * PCH B stepping, previous chipset stepping should be | |
6568 | * ignoring this setting. | |
6569 | */ | |
74cfd7ac CW |
6570 | val = I915_READ(PCH_DREF_CONTROL); |
6571 | ||
6572 | /* As we must carefully and slowly disable/enable each source in turn, | |
6573 | * compute the final state we want first and check if we need to | |
6574 | * make any changes at all. | |
6575 | */ | |
6576 | final = val; | |
6577 | final &= ~DREF_NONSPREAD_SOURCE_MASK; | |
6578 | if (has_ck505) | |
6579 | final |= DREF_NONSPREAD_CK505_ENABLE; | |
6580 | else | |
6581 | final |= DREF_NONSPREAD_SOURCE_ENABLE; | |
6582 | ||
6583 | final &= ~DREF_SSC_SOURCE_MASK; | |
6584 | final &= ~DREF_CPU_SOURCE_OUTPUT_MASK; | |
6585 | final &= ~DREF_SSC1_ENABLE; | |
6586 | ||
6587 | if (has_panel) { | |
6588 | final |= DREF_SSC_SOURCE_ENABLE; | |
6589 | ||
6590 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6591 | final |= DREF_SSC1_ENABLE; | |
6592 | ||
6593 | if (has_cpu_edp) { | |
6594 | if (intel_panel_use_ssc(dev_priv) && can_ssc) | |
6595 | final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; | |
6596 | else | |
6597 | final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; | |
6598 | } else | |
6599 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6600 | } else { | |
6601 | final |= DREF_SSC_SOURCE_DISABLE; | |
6602 | final |= DREF_CPU_SOURCE_OUTPUT_DISABLE; | |
6603 | } | |
6604 | ||
6605 | if (final == val) | |
6606 | return; | |
6607 | ||
13d83a67 | 6608 | /* Always enable nonspread source */ |
74cfd7ac | 6609 | val &= ~DREF_NONSPREAD_SOURCE_MASK; |
13d83a67 | 6610 | |
99eb6a01 | 6611 | if (has_ck505) |
74cfd7ac | 6612 | val |= DREF_NONSPREAD_CK505_ENABLE; |
99eb6a01 | 6613 | else |
74cfd7ac | 6614 | val |= DREF_NONSPREAD_SOURCE_ENABLE; |
13d83a67 | 6615 | |
199e5d79 | 6616 | if (has_panel) { |
74cfd7ac CW |
6617 | val &= ~DREF_SSC_SOURCE_MASK; |
6618 | val |= DREF_SSC_SOURCE_ENABLE; | |
13d83a67 | 6619 | |
199e5d79 | 6620 | /* SSC must be turned on before enabling the CPU output */ |
99eb6a01 | 6621 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6622 | DRM_DEBUG_KMS("Using SSC on panel\n"); |
74cfd7ac | 6623 | val |= DREF_SSC1_ENABLE; |
e77166b5 | 6624 | } else |
74cfd7ac | 6625 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 KP |
6626 | |
6627 | /* Get SSC going before enabling the outputs */ | |
74cfd7ac | 6628 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6629 | POSTING_READ(PCH_DREF_CONTROL); |
6630 | udelay(200); | |
6631 | ||
74cfd7ac | 6632 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
13d83a67 JB |
6633 | |
6634 | /* Enable CPU source on CPU attached eDP */ | |
199e5d79 | 6635 | if (has_cpu_edp) { |
99eb6a01 | 6636 | if (intel_panel_use_ssc(dev_priv) && can_ssc) { |
199e5d79 | 6637 | DRM_DEBUG_KMS("Using SSC on eDP\n"); |
74cfd7ac | 6638 | val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD; |
eba905b2 | 6639 | } else |
74cfd7ac | 6640 | val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD; |
199e5d79 | 6641 | } else |
74cfd7ac | 6642 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6643 | |
74cfd7ac | 6644 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6645 | POSTING_READ(PCH_DREF_CONTROL); |
6646 | udelay(200); | |
6647 | } else { | |
6648 | DRM_DEBUG_KMS("Disabling SSC entirely\n"); | |
6649 | ||
74cfd7ac | 6650 | val &= ~DREF_CPU_SOURCE_OUTPUT_MASK; |
199e5d79 KP |
6651 | |
6652 | /* Turn off CPU output */ | |
74cfd7ac | 6653 | val |= DREF_CPU_SOURCE_OUTPUT_DISABLE; |
199e5d79 | 6654 | |
74cfd7ac | 6655 | I915_WRITE(PCH_DREF_CONTROL, val); |
199e5d79 KP |
6656 | POSTING_READ(PCH_DREF_CONTROL); |
6657 | udelay(200); | |
6658 | ||
6659 | /* Turn off the SSC source */ | |
74cfd7ac CW |
6660 | val &= ~DREF_SSC_SOURCE_MASK; |
6661 | val |= DREF_SSC_SOURCE_DISABLE; | |
199e5d79 KP |
6662 | |
6663 | /* Turn off SSC1 */ | |
74cfd7ac | 6664 | val &= ~DREF_SSC1_ENABLE; |
199e5d79 | 6665 | |
74cfd7ac | 6666 | I915_WRITE(PCH_DREF_CONTROL, val); |
13d83a67 JB |
6667 | POSTING_READ(PCH_DREF_CONTROL); |
6668 | udelay(200); | |
6669 | } | |
74cfd7ac CW |
6670 | |
6671 | BUG_ON(val != final); | |
13d83a67 JB |
6672 | } |
6673 | ||
f31f2d55 | 6674 | static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv) |
dde86e2d | 6675 | { |
f31f2d55 | 6676 | uint32_t tmp; |
dde86e2d | 6677 | |
0ff066a9 PZ |
6678 | tmp = I915_READ(SOUTH_CHICKEN2); |
6679 | tmp |= FDI_MPHY_IOSFSB_RESET_CTL; | |
6680 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6681 | |
0ff066a9 PZ |
6682 | if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) & |
6683 | FDI_MPHY_IOSFSB_RESET_STATUS, 100)) | |
6684 | DRM_ERROR("FDI mPHY reset assert timeout\n"); | |
dde86e2d | 6685 | |
0ff066a9 PZ |
6686 | tmp = I915_READ(SOUTH_CHICKEN2); |
6687 | tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL; | |
6688 | I915_WRITE(SOUTH_CHICKEN2, tmp); | |
dde86e2d | 6689 | |
0ff066a9 PZ |
6690 | if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) & |
6691 | FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100)) | |
6692 | DRM_ERROR("FDI mPHY reset de-assert timeout\n"); | |
f31f2d55 PZ |
6693 | } |
6694 | ||
6695 | /* WaMPhyProgramming:hsw */ | |
6696 | static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv) | |
6697 | { | |
6698 | uint32_t tmp; | |
dde86e2d PZ |
6699 | |
6700 | tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY); | |
6701 | tmp &= ~(0xFF << 24); | |
6702 | tmp |= (0x12 << 24); | |
6703 | intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY); | |
6704 | ||
dde86e2d PZ |
6705 | tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY); |
6706 | tmp |= (1 << 11); | |
6707 | intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY); | |
6708 | ||
6709 | tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY); | |
6710 | tmp |= (1 << 11); | |
6711 | intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY); | |
6712 | ||
dde86e2d PZ |
6713 | tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY); |
6714 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6715 | intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY); | |
6716 | ||
6717 | tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY); | |
6718 | tmp |= (1 << 24) | (1 << 21) | (1 << 18); | |
6719 | intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY); | |
6720 | ||
0ff066a9 PZ |
6721 | tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY); |
6722 | tmp &= ~(7 << 13); | |
6723 | tmp |= (5 << 13); | |
6724 | intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY); | |
dde86e2d | 6725 | |
0ff066a9 PZ |
6726 | tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY); |
6727 | tmp &= ~(7 << 13); | |
6728 | tmp |= (5 << 13); | |
6729 | intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY); | |
dde86e2d PZ |
6730 | |
6731 | tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY); | |
6732 | tmp &= ~0xFF; | |
6733 | tmp |= 0x1C; | |
6734 | intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY); | |
6735 | ||
6736 | tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY); | |
6737 | tmp &= ~0xFF; | |
6738 | tmp |= 0x1C; | |
6739 | intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY); | |
6740 | ||
6741 | tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY); | |
6742 | tmp &= ~(0xFF << 16); | |
6743 | tmp |= (0x1C << 16); | |
6744 | intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY); | |
6745 | ||
6746 | tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY); | |
6747 | tmp &= ~(0xFF << 16); | |
6748 | tmp |= (0x1C << 16); | |
6749 | intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY); | |
6750 | ||
0ff066a9 PZ |
6751 | tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY); |
6752 | tmp |= (1 << 27); | |
6753 | intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY); | |
dde86e2d | 6754 | |
0ff066a9 PZ |
6755 | tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY); |
6756 | tmp |= (1 << 27); | |
6757 | intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY); | |
dde86e2d | 6758 | |
0ff066a9 PZ |
6759 | tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY); |
6760 | tmp &= ~(0xF << 28); | |
6761 | tmp |= (4 << 28); | |
6762 | intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY); | |
dde86e2d | 6763 | |
0ff066a9 PZ |
6764 | tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY); |
6765 | tmp &= ~(0xF << 28); | |
6766 | tmp |= (4 << 28); | |
6767 | intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY); | |
f31f2d55 PZ |
6768 | } |
6769 | ||
2fa86a1f PZ |
6770 | /* Implements 3 different sequences from BSpec chapter "Display iCLK |
6771 | * Programming" based on the parameters passed: | |
6772 | * - Sequence to enable CLKOUT_DP | |
6773 | * - Sequence to enable CLKOUT_DP without spread | |
6774 | * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O | |
6775 | */ | |
6776 | static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread, | |
6777 | bool with_fdi) | |
f31f2d55 PZ |
6778 | { |
6779 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa86a1f PZ |
6780 | uint32_t reg, tmp; |
6781 | ||
6782 | if (WARN(with_fdi && !with_spread, "FDI requires downspread\n")) | |
6783 | with_spread = true; | |
6784 | if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE && | |
6785 | with_fdi, "LP PCH doesn't have FDI\n")) | |
6786 | with_fdi = false; | |
f31f2d55 PZ |
6787 | |
6788 | mutex_lock(&dev_priv->dpio_lock); | |
6789 | ||
6790 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6791 | tmp &= ~SBI_SSCCTL_DISABLE; | |
6792 | tmp |= SBI_SSCCTL_PATHALT; | |
6793 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6794 | ||
6795 | udelay(24); | |
6796 | ||
2fa86a1f PZ |
6797 | if (with_spread) { |
6798 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6799 | tmp &= ~SBI_SSCCTL_PATHALT; | |
6800 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
f31f2d55 | 6801 | |
2fa86a1f PZ |
6802 | if (with_fdi) { |
6803 | lpt_reset_fdi_mphy(dev_priv); | |
6804 | lpt_program_fdi_mphy(dev_priv); | |
6805 | } | |
6806 | } | |
dde86e2d | 6807 | |
2fa86a1f PZ |
6808 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? |
6809 | SBI_GEN0 : SBI_DBUFF0; | |
6810 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
6811 | tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
6812 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
c00db246 DV |
6813 | |
6814 | mutex_unlock(&dev_priv->dpio_lock); | |
dde86e2d PZ |
6815 | } |
6816 | ||
47701c3b PZ |
6817 | /* Sequence to disable CLKOUT_DP */ |
6818 | static void lpt_disable_clkout_dp(struct drm_device *dev) | |
6819 | { | |
6820 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6821 | uint32_t reg, tmp; | |
6822 | ||
6823 | mutex_lock(&dev_priv->dpio_lock); | |
6824 | ||
6825 | reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ? | |
6826 | SBI_GEN0 : SBI_DBUFF0; | |
6827 | tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK); | |
6828 | tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE; | |
6829 | intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK); | |
6830 | ||
6831 | tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK); | |
6832 | if (!(tmp & SBI_SSCCTL_DISABLE)) { | |
6833 | if (!(tmp & SBI_SSCCTL_PATHALT)) { | |
6834 | tmp |= SBI_SSCCTL_PATHALT; | |
6835 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6836 | udelay(32); | |
6837 | } | |
6838 | tmp |= SBI_SSCCTL_DISABLE; | |
6839 | intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK); | |
6840 | } | |
6841 | ||
6842 | mutex_unlock(&dev_priv->dpio_lock); | |
6843 | } | |
6844 | ||
bf8fa3d3 PZ |
6845 | static void lpt_init_pch_refclk(struct drm_device *dev) |
6846 | { | |
bf8fa3d3 PZ |
6847 | struct intel_encoder *encoder; |
6848 | bool has_vga = false; | |
6849 | ||
b2784e15 | 6850 | for_each_intel_encoder(dev, encoder) { |
bf8fa3d3 PZ |
6851 | switch (encoder->type) { |
6852 | case INTEL_OUTPUT_ANALOG: | |
6853 | has_vga = true; | |
6854 | break; | |
6855 | } | |
6856 | } | |
6857 | ||
47701c3b PZ |
6858 | if (has_vga) |
6859 | lpt_enable_clkout_dp(dev, true, true); | |
6860 | else | |
6861 | lpt_disable_clkout_dp(dev); | |
bf8fa3d3 PZ |
6862 | } |
6863 | ||
dde86e2d PZ |
6864 | /* |
6865 | * Initialize reference clocks when the driver loads | |
6866 | */ | |
6867 | void intel_init_pch_refclk(struct drm_device *dev) | |
6868 | { | |
6869 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
6870 | ironlake_init_pch_refclk(dev); | |
6871 | else if (HAS_PCH_LPT(dev)) | |
6872 | lpt_init_pch_refclk(dev); | |
6873 | } | |
6874 | ||
d9d444cb JB |
6875 | static int ironlake_get_refclk(struct drm_crtc *crtc) |
6876 | { | |
6877 | struct drm_device *dev = crtc->dev; | |
6878 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6879 | struct intel_encoder *encoder; | |
d9d444cb JB |
6880 | int num_connectors = 0; |
6881 | bool is_lvds = false; | |
6882 | ||
6c2b7c12 | 6883 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
d9d444cb JB |
6884 | switch (encoder->type) { |
6885 | case INTEL_OUTPUT_LVDS: | |
6886 | is_lvds = true; | |
6887 | break; | |
d9d444cb JB |
6888 | } |
6889 | num_connectors++; | |
6890 | } | |
6891 | ||
6892 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) { | |
e91e941b | 6893 | DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", |
41aa3448 | 6894 | dev_priv->vbt.lvds_ssc_freq); |
e91e941b | 6895 | return dev_priv->vbt.lvds_ssc_freq; |
d9d444cb JB |
6896 | } |
6897 | ||
6898 | return 120000; | |
6899 | } | |
6900 | ||
6ff93609 | 6901 | static void ironlake_set_pipeconf(struct drm_crtc *crtc) |
79e53945 | 6902 | { |
c8203565 | 6903 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
79e53945 JB |
6904 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6905 | int pipe = intel_crtc->pipe; | |
c8203565 PZ |
6906 | uint32_t val; |
6907 | ||
78114071 | 6908 | val = 0; |
c8203565 | 6909 | |
965e0c48 | 6910 | switch (intel_crtc->config.pipe_bpp) { |
c8203565 | 6911 | case 18: |
dfd07d72 | 6912 | val |= PIPECONF_6BPC; |
c8203565 PZ |
6913 | break; |
6914 | case 24: | |
dfd07d72 | 6915 | val |= PIPECONF_8BPC; |
c8203565 PZ |
6916 | break; |
6917 | case 30: | |
dfd07d72 | 6918 | val |= PIPECONF_10BPC; |
c8203565 PZ |
6919 | break; |
6920 | case 36: | |
dfd07d72 | 6921 | val |= PIPECONF_12BPC; |
c8203565 PZ |
6922 | break; |
6923 | default: | |
cc769b62 PZ |
6924 | /* Case prevented by intel_choose_pipe_bpp_dither. */ |
6925 | BUG(); | |
c8203565 PZ |
6926 | } |
6927 | ||
d8b32247 | 6928 | if (intel_crtc->config.dither) |
c8203565 PZ |
6929 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
6930 | ||
6ff93609 | 6931 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
c8203565 PZ |
6932 | val |= PIPECONF_INTERLACED_ILK; |
6933 | else | |
6934 | val |= PIPECONF_PROGRESSIVE; | |
6935 | ||
50f3b016 | 6936 | if (intel_crtc->config.limited_color_range) |
3685a8f3 | 6937 | val |= PIPECONF_COLOR_RANGE_SELECT; |
3685a8f3 | 6938 | |
c8203565 PZ |
6939 | I915_WRITE(PIPECONF(pipe), val); |
6940 | POSTING_READ(PIPECONF(pipe)); | |
6941 | } | |
6942 | ||
86d3efce VS |
6943 | /* |
6944 | * Set up the pipe CSC unit. | |
6945 | * | |
6946 | * Currently only full range RGB to limited range RGB conversion | |
6947 | * is supported, but eventually this should handle various | |
6948 | * RGB<->YCbCr scenarios as well. | |
6949 | */ | |
50f3b016 | 6950 | static void intel_set_pipe_csc(struct drm_crtc *crtc) |
86d3efce VS |
6951 | { |
6952 | struct drm_device *dev = crtc->dev; | |
6953 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6954 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
6955 | int pipe = intel_crtc->pipe; | |
6956 | uint16_t coeff = 0x7800; /* 1.0 */ | |
6957 | ||
6958 | /* | |
6959 | * TODO: Check what kind of values actually come out of the pipe | |
6960 | * with these coeff/postoff values and adjust to get the best | |
6961 | * accuracy. Perhaps we even need to take the bpc value into | |
6962 | * consideration. | |
6963 | */ | |
6964 | ||
50f3b016 | 6965 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
6966 | coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */ |
6967 | ||
6968 | /* | |
6969 | * GY/GU and RY/RU should be the other way around according | |
6970 | * to BSpec, but reality doesn't agree. Just set them up in | |
6971 | * a way that results in the correct picture. | |
6972 | */ | |
6973 | I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16); | |
6974 | I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0); | |
6975 | ||
6976 | I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff); | |
6977 | I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0); | |
6978 | ||
6979 | I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0); | |
6980 | I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16); | |
6981 | ||
6982 | I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0); | |
6983 | I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0); | |
6984 | I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0); | |
6985 | ||
6986 | if (INTEL_INFO(dev)->gen > 6) { | |
6987 | uint16_t postoff = 0; | |
6988 | ||
50f3b016 | 6989 | if (intel_crtc->config.limited_color_range) |
32cf0cb0 | 6990 | postoff = (16 * (1 << 12) / 255) & 0x1fff; |
86d3efce VS |
6991 | |
6992 | I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff); | |
6993 | I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff); | |
6994 | I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff); | |
6995 | ||
6996 | I915_WRITE(PIPE_CSC_MODE(pipe), 0); | |
6997 | } else { | |
6998 | uint32_t mode = CSC_MODE_YUV_TO_RGB; | |
6999 | ||
50f3b016 | 7000 | if (intel_crtc->config.limited_color_range) |
86d3efce VS |
7001 | mode |= CSC_BLACK_SCREEN_OFFSET; |
7002 | ||
7003 | I915_WRITE(PIPE_CSC_MODE(pipe), mode); | |
7004 | } | |
7005 | } | |
7006 | ||
6ff93609 | 7007 | static void haswell_set_pipeconf(struct drm_crtc *crtc) |
ee2b0b38 | 7008 | { |
756f85cf PZ |
7009 | struct drm_device *dev = crtc->dev; |
7010 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ee2b0b38 | 7011 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
756f85cf | 7012 | enum pipe pipe = intel_crtc->pipe; |
3b117c8f | 7013 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
ee2b0b38 PZ |
7014 | uint32_t val; |
7015 | ||
3eff4faa | 7016 | val = 0; |
ee2b0b38 | 7017 | |
756f85cf | 7018 | if (IS_HASWELL(dev) && intel_crtc->config.dither) |
ee2b0b38 PZ |
7019 | val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP); |
7020 | ||
6ff93609 | 7021 | if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
ee2b0b38 PZ |
7022 | val |= PIPECONF_INTERLACED_ILK; |
7023 | else | |
7024 | val |= PIPECONF_PROGRESSIVE; | |
7025 | ||
702e7a56 PZ |
7026 | I915_WRITE(PIPECONF(cpu_transcoder), val); |
7027 | POSTING_READ(PIPECONF(cpu_transcoder)); | |
3eff4faa DV |
7028 | |
7029 | I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT); | |
7030 | POSTING_READ(GAMMA_MODE(intel_crtc->pipe)); | |
756f85cf PZ |
7031 | |
7032 | if (IS_BROADWELL(dev)) { | |
7033 | val = 0; | |
7034 | ||
7035 | switch (intel_crtc->config.pipe_bpp) { | |
7036 | case 18: | |
7037 | val |= PIPEMISC_DITHER_6_BPC; | |
7038 | break; | |
7039 | case 24: | |
7040 | val |= PIPEMISC_DITHER_8_BPC; | |
7041 | break; | |
7042 | case 30: | |
7043 | val |= PIPEMISC_DITHER_10_BPC; | |
7044 | break; | |
7045 | case 36: | |
7046 | val |= PIPEMISC_DITHER_12_BPC; | |
7047 | break; | |
7048 | default: | |
7049 | /* Case prevented by pipe_config_set_bpp. */ | |
7050 | BUG(); | |
7051 | } | |
7052 | ||
7053 | if (intel_crtc->config.dither) | |
7054 | val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP; | |
7055 | ||
7056 | I915_WRITE(PIPEMISC(pipe), val); | |
7057 | } | |
ee2b0b38 PZ |
7058 | } |
7059 | ||
6591c6e4 | 7060 | static bool ironlake_compute_clocks(struct drm_crtc *crtc, |
6591c6e4 PZ |
7061 | intel_clock_t *clock, |
7062 | bool *has_reduced_clock, | |
7063 | intel_clock_t *reduced_clock) | |
7064 | { | |
7065 | struct drm_device *dev = crtc->dev; | |
7066 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7067 | struct intel_encoder *intel_encoder; | |
7068 | int refclk; | |
d4906093 | 7069 | const intel_limit_t *limit; |
a16af721 | 7070 | bool ret, is_lvds = false; |
79e53945 | 7071 | |
6591c6e4 PZ |
7072 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
7073 | switch (intel_encoder->type) { | |
79e53945 JB |
7074 | case INTEL_OUTPUT_LVDS: |
7075 | is_lvds = true; | |
7076 | break; | |
79e53945 JB |
7077 | } |
7078 | } | |
7079 | ||
d9d444cb | 7080 | refclk = ironlake_get_refclk(crtc); |
79e53945 | 7081 | |
d4906093 ML |
7082 | /* |
7083 | * Returns a set of divisors for the desired target clock with the given | |
7084 | * refclk, or FALSE. The returned values represent the clock equation: | |
7085 | * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. | |
7086 | */ | |
1b894b59 | 7087 | limit = intel_limit(crtc, refclk); |
ff9a6750 DV |
7088 | ret = dev_priv->display.find_dpll(limit, crtc, |
7089 | to_intel_crtc(crtc)->config.port_clock, | |
ee9300bb | 7090 | refclk, NULL, clock); |
6591c6e4 PZ |
7091 | if (!ret) |
7092 | return false; | |
cda4b7d3 | 7093 | |
ddc9003c | 7094 | if (is_lvds && dev_priv->lvds_downclock_avail) { |
cec2f356 SP |
7095 | /* |
7096 | * Ensure we match the reduced clock's P to the target clock. | |
7097 | * If the clocks don't match, we can't switch the display clock | |
7098 | * by using the FP0/FP1. In such case we will disable the LVDS | |
7099 | * downclock feature. | |
7100 | */ | |
ee9300bb DV |
7101 | *has_reduced_clock = |
7102 | dev_priv->display.find_dpll(limit, crtc, | |
7103 | dev_priv->lvds_downclock, | |
7104 | refclk, clock, | |
7105 | reduced_clock); | |
652c393a | 7106 | } |
61e9653f | 7107 | |
6591c6e4 PZ |
7108 | return true; |
7109 | } | |
7110 | ||
d4b1931c PZ |
7111 | int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp) |
7112 | { | |
7113 | /* | |
7114 | * Account for spread spectrum to avoid | |
7115 | * oversubscribing the link. Max center spread | |
7116 | * is 2.5%; use 5% for safety's sake. | |
7117 | */ | |
7118 | u32 bps = target_clock * bpp * 21 / 20; | |
619d4d04 | 7119 | return DIV_ROUND_UP(bps, link_bw * 8); |
d4b1931c PZ |
7120 | } |
7121 | ||
7429e9d4 | 7122 | static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor) |
6cf86a5e | 7123 | { |
7429e9d4 | 7124 | return i9xx_dpll_compute_m(dpll) < factor * dpll->n; |
f48d8f23 PZ |
7125 | } |
7126 | ||
de13a2e3 | 7127 | static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, |
7429e9d4 | 7128 | u32 *fp, |
9a7c7890 | 7129 | intel_clock_t *reduced_clock, u32 *fp2) |
79e53945 | 7130 | { |
de13a2e3 | 7131 | struct drm_crtc *crtc = &intel_crtc->base; |
79e53945 JB |
7132 | struct drm_device *dev = crtc->dev; |
7133 | struct drm_i915_private *dev_priv = dev->dev_private; | |
de13a2e3 PZ |
7134 | struct intel_encoder *intel_encoder; |
7135 | uint32_t dpll; | |
6cc5f341 | 7136 | int factor, num_connectors = 0; |
09ede541 | 7137 | bool is_lvds = false, is_sdvo = false; |
79e53945 | 7138 | |
de13a2e3 PZ |
7139 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
7140 | switch (intel_encoder->type) { | |
79e53945 JB |
7141 | case INTEL_OUTPUT_LVDS: |
7142 | is_lvds = true; | |
7143 | break; | |
7144 | case INTEL_OUTPUT_SDVO: | |
7d57382e | 7145 | case INTEL_OUTPUT_HDMI: |
79e53945 | 7146 | is_sdvo = true; |
79e53945 | 7147 | break; |
79e53945 | 7148 | } |
43565a06 | 7149 | |
c751ce4f | 7150 | num_connectors++; |
79e53945 | 7151 | } |
79e53945 | 7152 | |
c1858123 | 7153 | /* Enable autotuning of the PLL clock (if permissible) */ |
8febb297 EA |
7154 | factor = 21; |
7155 | if (is_lvds) { | |
7156 | if ((intel_panel_use_ssc(dev_priv) && | |
e91e941b | 7157 | dev_priv->vbt.lvds_ssc_freq == 100000) || |
f0b44056 | 7158 | (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev))) |
8febb297 | 7159 | factor = 25; |
09ede541 | 7160 | } else if (intel_crtc->config.sdvo_tv_clock) |
8febb297 | 7161 | factor = 20; |
c1858123 | 7162 | |
7429e9d4 | 7163 | if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor)) |
7d0ac5b7 | 7164 | *fp |= FP_CB_TUNE; |
2c07245f | 7165 | |
9a7c7890 DV |
7166 | if (fp2 && (reduced_clock->m < factor * reduced_clock->n)) |
7167 | *fp2 |= FP_CB_TUNE; | |
7168 | ||
5eddb70b | 7169 | dpll = 0; |
2c07245f | 7170 | |
a07d6787 EA |
7171 | if (is_lvds) |
7172 | dpll |= DPLLB_MODE_LVDS; | |
7173 | else | |
7174 | dpll |= DPLLB_MODE_DAC_SERIAL; | |
198a037f | 7175 | |
ef1b460d DV |
7176 | dpll |= (intel_crtc->config.pixel_multiplier - 1) |
7177 | << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; | |
198a037f DV |
7178 | |
7179 | if (is_sdvo) | |
4a33e48d | 7180 | dpll |= DPLL_SDVO_HIGH_SPEED; |
9566e9af | 7181 | if (intel_crtc->config.has_dp_encoder) |
4a33e48d | 7182 | dpll |= DPLL_SDVO_HIGH_SPEED; |
79e53945 | 7183 | |
a07d6787 | 7184 | /* compute bitmask from p1 value */ |
7429e9d4 | 7185 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; |
a07d6787 | 7186 | /* also FPA1 */ |
7429e9d4 | 7187 | dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; |
a07d6787 | 7188 | |
7429e9d4 | 7189 | switch (intel_crtc->config.dpll.p2) { |
a07d6787 EA |
7190 | case 5: |
7191 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; | |
7192 | break; | |
7193 | case 7: | |
7194 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; | |
7195 | break; | |
7196 | case 10: | |
7197 | dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; | |
7198 | break; | |
7199 | case 14: | |
7200 | dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; | |
7201 | break; | |
79e53945 JB |
7202 | } |
7203 | ||
b4c09f3b | 7204 | if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) |
43565a06 | 7205 | dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; |
79e53945 JB |
7206 | else |
7207 | dpll |= PLL_REF_INPUT_DREFCLK; | |
7208 | ||
959e16d6 | 7209 | return dpll | DPLL_VCO_ENABLE; |
de13a2e3 PZ |
7210 | } |
7211 | ||
7212 | static int ironlake_crtc_mode_set(struct drm_crtc *crtc, | |
de13a2e3 PZ |
7213 | int x, int y, |
7214 | struct drm_framebuffer *fb) | |
7215 | { | |
7216 | struct drm_device *dev = crtc->dev; | |
de13a2e3 | 7217 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
de13a2e3 PZ |
7218 | int num_connectors = 0; |
7219 | intel_clock_t clock, reduced_clock; | |
cbbab5bd | 7220 | u32 dpll = 0, fp = 0, fp2 = 0; |
e2f12b07 | 7221 | bool ok, has_reduced_clock = false; |
8b47047b | 7222 | bool is_lvds = false; |
de13a2e3 | 7223 | struct intel_encoder *encoder; |
e2b78267 | 7224 | struct intel_shared_dpll *pll; |
de13a2e3 PZ |
7225 | |
7226 | for_each_encoder_on_crtc(dev, crtc, encoder) { | |
7227 | switch (encoder->type) { | |
7228 | case INTEL_OUTPUT_LVDS: | |
7229 | is_lvds = true; | |
7230 | break; | |
de13a2e3 PZ |
7231 | } |
7232 | ||
7233 | num_connectors++; | |
a07d6787 | 7234 | } |
79e53945 | 7235 | |
5dc5298b PZ |
7236 | WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)), |
7237 | "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev)); | |
a07d6787 | 7238 | |
ff9a6750 | 7239 | ok = ironlake_compute_clocks(crtc, &clock, |
de13a2e3 | 7240 | &has_reduced_clock, &reduced_clock); |
ee9300bb | 7241 | if (!ok && !intel_crtc->config.clock_set) { |
de13a2e3 PZ |
7242 | DRM_ERROR("Couldn't find PLL settings for mode!\n"); |
7243 | return -EINVAL; | |
79e53945 | 7244 | } |
f47709a9 DV |
7245 | /* Compat-code for transition, will disappear. */ |
7246 | if (!intel_crtc->config.clock_set) { | |
7247 | intel_crtc->config.dpll.n = clock.n; | |
7248 | intel_crtc->config.dpll.m1 = clock.m1; | |
7249 | intel_crtc->config.dpll.m2 = clock.m2; | |
7250 | intel_crtc->config.dpll.p1 = clock.p1; | |
7251 | intel_crtc->config.dpll.p2 = clock.p2; | |
7252 | } | |
79e53945 | 7253 | |
5dc5298b | 7254 | /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ |
8b47047b | 7255 | if (intel_crtc->config.has_pch_encoder) { |
7429e9d4 | 7256 | fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll); |
cbbab5bd | 7257 | if (has_reduced_clock) |
7429e9d4 | 7258 | fp2 = i9xx_dpll_compute_fp(&reduced_clock); |
cbbab5bd | 7259 | |
7429e9d4 | 7260 | dpll = ironlake_compute_dpll(intel_crtc, |
cbbab5bd DV |
7261 | &fp, &reduced_clock, |
7262 | has_reduced_clock ? &fp2 : NULL); | |
7263 | ||
959e16d6 | 7264 | intel_crtc->config.dpll_hw_state.dpll = dpll; |
66e985c0 DV |
7265 | intel_crtc->config.dpll_hw_state.fp0 = fp; |
7266 | if (has_reduced_clock) | |
7267 | intel_crtc->config.dpll_hw_state.fp1 = fp2; | |
7268 | else | |
7269 | intel_crtc->config.dpll_hw_state.fp1 = fp; | |
7270 | ||
b89a1d39 | 7271 | pll = intel_get_shared_dpll(intel_crtc); |
ee7b9f93 | 7272 | if (pll == NULL) { |
84f44ce7 | 7273 | DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n", |
29407aab | 7274 | pipe_name(intel_crtc->pipe)); |
4b645f14 JB |
7275 | return -EINVAL; |
7276 | } | |
ee7b9f93 | 7277 | } else |
e72f9fbf | 7278 | intel_put_shared_dpll(intel_crtc); |
79e53945 | 7279 | |
d330a953 | 7280 | if (is_lvds && has_reduced_clock && i915.powersave) |
bcd644e0 DV |
7281 | intel_crtc->lowfreq_avail = true; |
7282 | else | |
7283 | intel_crtc->lowfreq_avail = false; | |
e2b78267 | 7284 | |
c8f7a0db | 7285 | return 0; |
79e53945 JB |
7286 | } |
7287 | ||
eb14cb74 VS |
7288 | static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc, |
7289 | struct intel_link_m_n *m_n) | |
7290 | { | |
7291 | struct drm_device *dev = crtc->base.dev; | |
7292 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7293 | enum pipe pipe = crtc->pipe; | |
7294 | ||
7295 | m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe)); | |
7296 | m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe)); | |
7297 | m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7298 | & ~TU_SIZE_MASK; | |
7299 | m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe)); | |
7300 | m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe)) | |
7301 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7302 | } | |
7303 | ||
7304 | static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, | |
7305 | enum transcoder transcoder, | |
b95af8be VK |
7306 | struct intel_link_m_n *m_n, |
7307 | struct intel_link_m_n *m2_n2) | |
72419203 DV |
7308 | { |
7309 | struct drm_device *dev = crtc->base.dev; | |
7310 | struct drm_i915_private *dev_priv = dev->dev_private; | |
eb14cb74 | 7311 | enum pipe pipe = crtc->pipe; |
72419203 | 7312 | |
eb14cb74 VS |
7313 | if (INTEL_INFO(dev)->gen >= 5) { |
7314 | m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); | |
7315 | m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); | |
7316 | m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) | |
7317 | & ~TU_SIZE_MASK; | |
7318 | m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); | |
7319 | m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) | |
7320 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
b95af8be VK |
7321 | /* Read M2_N2 registers only for gen < 8 (M2_N2 available for |
7322 | * gen < 8) and if DRRS is supported (to make sure the | |
7323 | * registers are not unnecessarily read). | |
7324 | */ | |
7325 | if (m2_n2 && INTEL_INFO(dev)->gen < 8 && | |
7326 | crtc->config.has_drrs) { | |
7327 | m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); | |
7328 | m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); | |
7329 | m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) | |
7330 | & ~TU_SIZE_MASK; | |
7331 | m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); | |
7332 | m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) | |
7333 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7334 | } | |
eb14cb74 VS |
7335 | } else { |
7336 | m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe)); | |
7337 | m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe)); | |
7338 | m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7339 | & ~TU_SIZE_MASK; | |
7340 | m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe)); | |
7341 | m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe)) | |
7342 | & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1; | |
7343 | } | |
7344 | } | |
7345 | ||
7346 | void intel_dp_get_m_n(struct intel_crtc *crtc, | |
7347 | struct intel_crtc_config *pipe_config) | |
7348 | { | |
7349 | if (crtc->config.has_pch_encoder) | |
7350 | intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n); | |
7351 | else | |
7352 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be VK |
7353 | &pipe_config->dp_m_n, |
7354 | &pipe_config->dp_m2_n2); | |
eb14cb74 | 7355 | } |
72419203 | 7356 | |
eb14cb74 VS |
7357 | static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc, |
7358 | struct intel_crtc_config *pipe_config) | |
7359 | { | |
7360 | intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder, | |
b95af8be | 7361 | &pipe_config->fdi_m_n, NULL); |
72419203 DV |
7362 | } |
7363 | ||
2fa2fe9a DV |
7364 | static void ironlake_get_pfit_config(struct intel_crtc *crtc, |
7365 | struct intel_crtc_config *pipe_config) | |
7366 | { | |
7367 | struct drm_device *dev = crtc->base.dev; | |
7368 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7369 | uint32_t tmp; | |
7370 | ||
7371 | tmp = I915_READ(PF_CTL(crtc->pipe)); | |
7372 | ||
7373 | if (tmp & PF_ENABLE) { | |
fd4daa9c | 7374 | pipe_config->pch_pfit.enabled = true; |
2fa2fe9a DV |
7375 | pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe)); |
7376 | pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe)); | |
cb8b2a30 DV |
7377 | |
7378 | /* We currently do not free assignements of panel fitters on | |
7379 | * ivb/hsw (since we don't use the higher upscaling modes which | |
7380 | * differentiates them) so just WARN about this case for now. */ | |
7381 | if (IS_GEN7(dev)) { | |
7382 | WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) != | |
7383 | PF_PIPE_SEL_IVB(crtc->pipe)); | |
7384 | } | |
2fa2fe9a | 7385 | } |
79e53945 JB |
7386 | } |
7387 | ||
4c6baa59 JB |
7388 | static void ironlake_get_plane_config(struct intel_crtc *crtc, |
7389 | struct intel_plane_config *plane_config) | |
7390 | { | |
7391 | struct drm_device *dev = crtc->base.dev; | |
7392 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7393 | u32 val, base, offset; | |
7394 | int pipe = crtc->pipe, plane = crtc->plane; | |
7395 | int fourcc, pixel_format; | |
7396 | int aligned_height; | |
7397 | ||
66e514c1 DA |
7398 | crtc->base.primary->fb = kzalloc(sizeof(struct intel_framebuffer), GFP_KERNEL); |
7399 | if (!crtc->base.primary->fb) { | |
4c6baa59 JB |
7400 | DRM_DEBUG_KMS("failed to alloc fb\n"); |
7401 | return; | |
7402 | } | |
7403 | ||
7404 | val = I915_READ(DSPCNTR(plane)); | |
7405 | ||
7406 | if (INTEL_INFO(dev)->gen >= 4) | |
7407 | if (val & DISPPLANE_TILED) | |
7408 | plane_config->tiled = true; | |
7409 | ||
7410 | pixel_format = val & DISPPLANE_PIXFORMAT_MASK; | |
7411 | fourcc = intel_format_to_fourcc(pixel_format); | |
66e514c1 DA |
7412 | crtc->base.primary->fb->pixel_format = fourcc; |
7413 | crtc->base.primary->fb->bits_per_pixel = | |
4c6baa59 JB |
7414 | drm_format_plane_cpp(fourcc, 0) * 8; |
7415 | ||
7416 | base = I915_READ(DSPSURF(plane)) & 0xfffff000; | |
7417 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
7418 | offset = I915_READ(DSPOFFSET(plane)); | |
7419 | } else { | |
7420 | if (plane_config->tiled) | |
7421 | offset = I915_READ(DSPTILEOFF(plane)); | |
7422 | else | |
7423 | offset = I915_READ(DSPLINOFF(plane)); | |
7424 | } | |
7425 | plane_config->base = base; | |
7426 | ||
7427 | val = I915_READ(PIPESRC(pipe)); | |
66e514c1 DA |
7428 | crtc->base.primary->fb->width = ((val >> 16) & 0xfff) + 1; |
7429 | crtc->base.primary->fb->height = ((val >> 0) & 0xfff) + 1; | |
4c6baa59 JB |
7430 | |
7431 | val = I915_READ(DSPSTRIDE(pipe)); | |
026b96e2 | 7432 | crtc->base.primary->fb->pitches[0] = val & 0xffffffc0; |
4c6baa59 | 7433 | |
66e514c1 | 7434 | aligned_height = intel_align_height(dev, crtc->base.primary->fb->height, |
4c6baa59 JB |
7435 | plane_config->tiled); |
7436 | ||
1267a26b FF |
7437 | plane_config->size = PAGE_ALIGN(crtc->base.primary->fb->pitches[0] * |
7438 | aligned_height); | |
4c6baa59 JB |
7439 | |
7440 | DRM_DEBUG_KMS("pipe/plane %d/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n", | |
66e514c1 DA |
7441 | pipe, plane, crtc->base.primary->fb->width, |
7442 | crtc->base.primary->fb->height, | |
7443 | crtc->base.primary->fb->bits_per_pixel, base, | |
7444 | crtc->base.primary->fb->pitches[0], | |
4c6baa59 JB |
7445 | plane_config->size); |
7446 | } | |
7447 | ||
0e8ffe1b DV |
7448 | static bool ironlake_get_pipe_config(struct intel_crtc *crtc, |
7449 | struct intel_crtc_config *pipe_config) | |
7450 | { | |
7451 | struct drm_device *dev = crtc->base.dev; | |
7452 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7453 | uint32_t tmp; | |
7454 | ||
930e8c9e PZ |
7455 | if (!intel_display_power_enabled(dev_priv, |
7456 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
7457 | return false; | |
7458 | ||
e143a21c | 7459 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 | 7460 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
eccb140b | 7461 | |
0e8ffe1b DV |
7462 | tmp = I915_READ(PIPECONF(crtc->pipe)); |
7463 | if (!(tmp & PIPECONF_ENABLE)) | |
7464 | return false; | |
7465 | ||
42571aef VS |
7466 | switch (tmp & PIPECONF_BPC_MASK) { |
7467 | case PIPECONF_6BPC: | |
7468 | pipe_config->pipe_bpp = 18; | |
7469 | break; | |
7470 | case PIPECONF_8BPC: | |
7471 | pipe_config->pipe_bpp = 24; | |
7472 | break; | |
7473 | case PIPECONF_10BPC: | |
7474 | pipe_config->pipe_bpp = 30; | |
7475 | break; | |
7476 | case PIPECONF_12BPC: | |
7477 | pipe_config->pipe_bpp = 36; | |
7478 | break; | |
7479 | default: | |
7480 | break; | |
7481 | } | |
7482 | ||
b5a9fa09 DV |
7483 | if (tmp & PIPECONF_COLOR_RANGE_SELECT) |
7484 | pipe_config->limited_color_range = true; | |
7485 | ||
ab9412ba | 7486 | if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) { |
66e985c0 DV |
7487 | struct intel_shared_dpll *pll; |
7488 | ||
88adfff1 DV |
7489 | pipe_config->has_pch_encoder = true; |
7490 | ||
627eb5a3 DV |
7491 | tmp = I915_READ(FDI_RX_CTL(crtc->pipe)); |
7492 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7493 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
72419203 DV |
7494 | |
7495 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
6c49f241 | 7496 | |
c0d43d62 | 7497 | if (HAS_PCH_IBX(dev_priv->dev)) { |
d94ab068 DV |
7498 | pipe_config->shared_dpll = |
7499 | (enum intel_dpll_id) crtc->pipe; | |
c0d43d62 DV |
7500 | } else { |
7501 | tmp = I915_READ(PCH_DPLL_SEL); | |
7502 | if (tmp & TRANS_DPLLB_SEL(crtc->pipe)) | |
7503 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B; | |
7504 | else | |
7505 | pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A; | |
7506 | } | |
66e985c0 DV |
7507 | |
7508 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
7509 | ||
7510 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
7511 | &pipe_config->dpll_hw_state)); | |
c93f54cf DV |
7512 | |
7513 | tmp = pipe_config->dpll_hw_state.dpll; | |
7514 | pipe_config->pixel_multiplier = | |
7515 | ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK) | |
7516 | >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1; | |
18442d08 VS |
7517 | |
7518 | ironlake_pch_clock_get(crtc, pipe_config); | |
6c49f241 DV |
7519 | } else { |
7520 | pipe_config->pixel_multiplier = 1; | |
627eb5a3 DV |
7521 | } |
7522 | ||
1bd1bd80 DV |
7523 | intel_get_pipe_timings(crtc, pipe_config); |
7524 | ||
2fa2fe9a DV |
7525 | ironlake_get_pfit_config(crtc, pipe_config); |
7526 | ||
0e8ffe1b DV |
7527 | return true; |
7528 | } | |
7529 | ||
be256dc7 PZ |
7530 | static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv) |
7531 | { | |
7532 | struct drm_device *dev = dev_priv->dev; | |
be256dc7 | 7533 | struct intel_crtc *crtc; |
be256dc7 | 7534 | |
d3fcc808 | 7535 | for_each_intel_crtc(dev, crtc) |
798183c5 | 7536 | WARN(crtc->active, "CRTC for pipe %c enabled\n", |
be256dc7 PZ |
7537 | pipe_name(crtc->pipe)); |
7538 | ||
7539 | WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n"); | |
8cc3e169 DV |
7540 | WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n"); |
7541 | WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n"); | |
7542 | WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n"); | |
be256dc7 PZ |
7543 | WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n"); |
7544 | WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE, | |
7545 | "CPU PWM1 enabled\n"); | |
c5107b87 PZ |
7546 | if (IS_HASWELL(dev)) |
7547 | WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE, | |
7548 | "CPU PWM2 enabled\n"); | |
be256dc7 PZ |
7549 | WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE, |
7550 | "PCH PWM1 enabled\n"); | |
7551 | WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE, | |
7552 | "Utility pin enabled\n"); | |
7553 | WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n"); | |
7554 | ||
9926ada1 PZ |
7555 | /* |
7556 | * In theory we can still leave IRQs enabled, as long as only the HPD | |
7557 | * interrupts remain enabled. We used to check for that, but since it's | |
7558 | * gen-specific and since we only disable LCPLL after we fully disable | |
7559 | * the interrupts, the check below should be enough. | |
7560 | */ | |
9df7575f | 7561 | WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n"); |
be256dc7 PZ |
7562 | } |
7563 | ||
9ccd5aeb PZ |
7564 | static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv) |
7565 | { | |
7566 | struct drm_device *dev = dev_priv->dev; | |
7567 | ||
7568 | if (IS_HASWELL(dev)) | |
7569 | return I915_READ(D_COMP_HSW); | |
7570 | else | |
7571 | return I915_READ(D_COMP_BDW); | |
7572 | } | |
7573 | ||
3c4c9b81 PZ |
7574 | static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val) |
7575 | { | |
7576 | struct drm_device *dev = dev_priv->dev; | |
7577 | ||
7578 | if (IS_HASWELL(dev)) { | |
7579 | mutex_lock(&dev_priv->rps.hw_lock); | |
7580 | if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, | |
7581 | val)) | |
f475dadf | 7582 | DRM_ERROR("Failed to write to D_COMP\n"); |
3c4c9b81 PZ |
7583 | mutex_unlock(&dev_priv->rps.hw_lock); |
7584 | } else { | |
9ccd5aeb PZ |
7585 | I915_WRITE(D_COMP_BDW, val); |
7586 | POSTING_READ(D_COMP_BDW); | |
3c4c9b81 | 7587 | } |
be256dc7 PZ |
7588 | } |
7589 | ||
7590 | /* | |
7591 | * This function implements pieces of two sequences from BSpec: | |
7592 | * - Sequence for display software to disable LCPLL | |
7593 | * - Sequence for display software to allow package C8+ | |
7594 | * The steps implemented here are just the steps that actually touch the LCPLL | |
7595 | * register. Callers should take care of disabling all the display engine | |
7596 | * functions, doing the mode unset, fixing interrupts, etc. | |
7597 | */ | |
6ff58d53 PZ |
7598 | static void hsw_disable_lcpll(struct drm_i915_private *dev_priv, |
7599 | bool switch_to_fclk, bool allow_power_down) | |
be256dc7 PZ |
7600 | { |
7601 | uint32_t val; | |
7602 | ||
7603 | assert_can_disable_lcpll(dev_priv); | |
7604 | ||
7605 | val = I915_READ(LCPLL_CTL); | |
7606 | ||
7607 | if (switch_to_fclk) { | |
7608 | val |= LCPLL_CD_SOURCE_FCLK; | |
7609 | I915_WRITE(LCPLL_CTL, val); | |
7610 | ||
7611 | if (wait_for_atomic_us(I915_READ(LCPLL_CTL) & | |
7612 | LCPLL_CD_SOURCE_FCLK_DONE, 1)) | |
7613 | DRM_ERROR("Switching to FCLK failed\n"); | |
7614 | ||
7615 | val = I915_READ(LCPLL_CTL); | |
7616 | } | |
7617 | ||
7618 | val |= LCPLL_PLL_DISABLE; | |
7619 | I915_WRITE(LCPLL_CTL, val); | |
7620 | POSTING_READ(LCPLL_CTL); | |
7621 | ||
7622 | if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1)) | |
7623 | DRM_ERROR("LCPLL still locked\n"); | |
7624 | ||
9ccd5aeb | 7625 | val = hsw_read_dcomp(dev_priv); |
be256dc7 | 7626 | val |= D_COMP_COMP_DISABLE; |
3c4c9b81 | 7627 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7628 | ndelay(100); |
7629 | ||
9ccd5aeb PZ |
7630 | if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0, |
7631 | 1)) | |
be256dc7 PZ |
7632 | DRM_ERROR("D_COMP RCOMP still in progress\n"); |
7633 | ||
7634 | if (allow_power_down) { | |
7635 | val = I915_READ(LCPLL_CTL); | |
7636 | val |= LCPLL_POWER_DOWN_ALLOW; | |
7637 | I915_WRITE(LCPLL_CTL, val); | |
7638 | POSTING_READ(LCPLL_CTL); | |
7639 | } | |
7640 | } | |
7641 | ||
7642 | /* | |
7643 | * Fully restores LCPLL, disallowing power down and switching back to LCPLL | |
7644 | * source. | |
7645 | */ | |
6ff58d53 | 7646 | static void hsw_restore_lcpll(struct drm_i915_private *dev_priv) |
be256dc7 PZ |
7647 | { |
7648 | uint32_t val; | |
a8a8bd54 | 7649 | unsigned long irqflags; |
be256dc7 PZ |
7650 | |
7651 | val = I915_READ(LCPLL_CTL); | |
7652 | ||
7653 | if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK | | |
7654 | LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK) | |
7655 | return; | |
7656 | ||
a8a8bd54 PZ |
7657 | /* |
7658 | * Make sure we're not on PC8 state before disabling PC8, otherwise | |
7659 | * we'll hang the machine. To prevent PC8 state, just enable force_wake. | |
7660 | * | |
7661 | * The other problem is that hsw_restore_lcpll() is called as part of | |
7662 | * the runtime PM resume sequence, so we can't just call | |
7663 | * gen6_gt_force_wake_get() because that function calls | |
7664 | * intel_runtime_pm_get(), and we can't change the runtime PM refcount | |
7665 | * while we are on the resume sequence. So to solve this problem we have | |
7666 | * to call special forcewake code that doesn't touch runtime PM and | |
7667 | * doesn't enable the forcewake delayed work. | |
7668 | */ | |
7669 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
7670 | if (dev_priv->uncore.forcewake_count++ == 0) | |
7671 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); | |
7672 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
215733fa | 7673 | |
be256dc7 PZ |
7674 | if (val & LCPLL_POWER_DOWN_ALLOW) { |
7675 | val &= ~LCPLL_POWER_DOWN_ALLOW; | |
7676 | I915_WRITE(LCPLL_CTL, val); | |
35d8f2eb | 7677 | POSTING_READ(LCPLL_CTL); |
be256dc7 PZ |
7678 | } |
7679 | ||
9ccd5aeb | 7680 | val = hsw_read_dcomp(dev_priv); |
be256dc7 PZ |
7681 | val |= D_COMP_COMP_FORCE; |
7682 | val &= ~D_COMP_COMP_DISABLE; | |
3c4c9b81 | 7683 | hsw_write_dcomp(dev_priv, val); |
be256dc7 PZ |
7684 | |
7685 | val = I915_READ(LCPLL_CTL); | |
7686 | val &= ~LCPLL_PLL_DISABLE; | |
7687 | I915_WRITE(LCPLL_CTL, val); | |
7688 | ||
7689 | if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5)) | |
7690 | DRM_ERROR("LCPLL not locked yet\n"); | |
7691 | ||
7692 | if (val & LCPLL_CD_SOURCE_FCLK) { | |
7693 | val = I915_READ(LCPLL_CTL); | |
7694 | val &= ~LCPLL_CD_SOURCE_FCLK; | |
7695 | I915_WRITE(LCPLL_CTL, val); | |
7696 | ||
7697 | if (wait_for_atomic_us((I915_READ(LCPLL_CTL) & | |
7698 | LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1)) | |
7699 | DRM_ERROR("Switching back to LCPLL failed\n"); | |
7700 | } | |
215733fa | 7701 | |
a8a8bd54 PZ |
7702 | /* See the big comment above. */ |
7703 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); | |
7704 | if (--dev_priv->uncore.forcewake_count == 0) | |
7705 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); | |
7706 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); | |
be256dc7 PZ |
7707 | } |
7708 | ||
765dab67 PZ |
7709 | /* |
7710 | * Package states C8 and deeper are really deep PC states that can only be | |
7711 | * reached when all the devices on the system allow it, so even if the graphics | |
7712 | * device allows PC8+, it doesn't mean the system will actually get to these | |
7713 | * states. Our driver only allows PC8+ when going into runtime PM. | |
7714 | * | |
7715 | * The requirements for PC8+ are that all the outputs are disabled, the power | |
7716 | * well is disabled and most interrupts are disabled, and these are also | |
7717 | * requirements for runtime PM. When these conditions are met, we manually do | |
7718 | * the other conditions: disable the interrupts, clocks and switch LCPLL refclk | |
7719 | * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard | |
7720 | * hang the machine. | |
7721 | * | |
7722 | * When we really reach PC8 or deeper states (not just when we allow it) we lose | |
7723 | * the state of some registers, so when we come back from PC8+ we need to | |
7724 | * restore this state. We don't get into PC8+ if we're not in RC6, so we don't | |
7725 | * need to take care of the registers kept by RC6. Notice that this happens even | |
7726 | * if we don't put the device in PCI D3 state (which is what currently happens | |
7727 | * because of the runtime PM support). | |
7728 | * | |
7729 | * For more, read "Display Sequences for Package C8" on the hardware | |
7730 | * documentation. | |
7731 | */ | |
a14cb6fc | 7732 | void hsw_enable_pc8(struct drm_i915_private *dev_priv) |
c67a470b | 7733 | { |
c67a470b PZ |
7734 | struct drm_device *dev = dev_priv->dev; |
7735 | uint32_t val; | |
7736 | ||
c67a470b PZ |
7737 | DRM_DEBUG_KMS("Enabling package C8+\n"); |
7738 | ||
c67a470b PZ |
7739 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
7740 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7741 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
7742 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7743 | } | |
7744 | ||
7745 | lpt_disable_clkout_dp(dev); | |
c67a470b PZ |
7746 | hsw_disable_lcpll(dev_priv, true, true); |
7747 | } | |
7748 | ||
a14cb6fc | 7749 | void hsw_disable_pc8(struct drm_i915_private *dev_priv) |
c67a470b PZ |
7750 | { |
7751 | struct drm_device *dev = dev_priv->dev; | |
7752 | uint32_t val; | |
7753 | ||
c67a470b PZ |
7754 | DRM_DEBUG_KMS("Disabling package C8+\n"); |
7755 | ||
7756 | hsw_restore_lcpll(dev_priv); | |
c67a470b PZ |
7757 | lpt_init_pch_refclk(dev); |
7758 | ||
7759 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
7760 | val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
7761 | val |= PCH_LP_PARTITION_LEVEL_DISABLE; | |
7762 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
7763 | } | |
7764 | ||
7765 | intel_prepare_ddi(dev); | |
c67a470b PZ |
7766 | } |
7767 | ||
9a952a0d PZ |
7768 | static void snb_modeset_global_resources(struct drm_device *dev) |
7769 | { | |
7770 | modeset_update_crtc_power_domains(dev); | |
7771 | } | |
7772 | ||
4f074129 ID |
7773 | static void haswell_modeset_global_resources(struct drm_device *dev) |
7774 | { | |
da723569 | 7775 | modeset_update_crtc_power_domains(dev); |
d6dd9eb1 DV |
7776 | } |
7777 | ||
09b4ddf9 | 7778 | static int haswell_crtc_mode_set(struct drm_crtc *crtc, |
09b4ddf9 PZ |
7779 | int x, int y, |
7780 | struct drm_framebuffer *fb) | |
7781 | { | |
09b4ddf9 | 7782 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
09b4ddf9 | 7783 | |
566b734a | 7784 | if (!intel_ddi_pll_select(intel_crtc)) |
6441ab5f | 7785 | return -EINVAL; |
716c2e55 | 7786 | |
644cef34 DV |
7787 | intel_crtc->lowfreq_avail = false; |
7788 | ||
c8f7a0db | 7789 | return 0; |
79e53945 JB |
7790 | } |
7791 | ||
7d2c8175 DL |
7792 | static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv, |
7793 | enum port port, | |
7794 | struct intel_crtc_config *pipe_config) | |
7795 | { | |
7796 | pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port)); | |
7797 | ||
7798 | switch (pipe_config->ddi_pll_sel) { | |
7799 | case PORT_CLK_SEL_WRPLL1: | |
7800 | pipe_config->shared_dpll = DPLL_ID_WRPLL1; | |
7801 | break; | |
7802 | case PORT_CLK_SEL_WRPLL2: | |
7803 | pipe_config->shared_dpll = DPLL_ID_WRPLL2; | |
7804 | break; | |
7805 | } | |
7806 | } | |
7807 | ||
26804afd DV |
7808 | static void haswell_get_ddi_port_state(struct intel_crtc *crtc, |
7809 | struct intel_crtc_config *pipe_config) | |
7810 | { | |
7811 | struct drm_device *dev = crtc->base.dev; | |
7812 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d452c5b6 | 7813 | struct intel_shared_dpll *pll; |
26804afd DV |
7814 | enum port port; |
7815 | uint32_t tmp; | |
7816 | ||
7817 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder)); | |
7818 | ||
7819 | port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT; | |
7820 | ||
7d2c8175 | 7821 | haswell_get_ddi_pll(dev_priv, port, pipe_config); |
9cd86933 | 7822 | |
d452c5b6 DV |
7823 | if (pipe_config->shared_dpll >= 0) { |
7824 | pll = &dev_priv->shared_dplls[pipe_config->shared_dpll]; | |
7825 | ||
7826 | WARN_ON(!pll->get_hw_state(dev_priv, pll, | |
7827 | &pipe_config->dpll_hw_state)); | |
7828 | } | |
7829 | ||
26804afd DV |
7830 | /* |
7831 | * Haswell has only FDI/PCH transcoder A. It is which is connected to | |
7832 | * DDI E. So just check whether this pipe is wired to DDI E and whether | |
7833 | * the PCH transcoder is on. | |
7834 | */ | |
7835 | if ((port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) { | |
7836 | pipe_config->has_pch_encoder = true; | |
7837 | ||
7838 | tmp = I915_READ(FDI_RX_CTL(PIPE_A)); | |
7839 | pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >> | |
7840 | FDI_DP_PORT_WIDTH_SHIFT) + 1; | |
7841 | ||
7842 | ironlake_get_fdi_m_n_config(crtc, pipe_config); | |
7843 | } | |
7844 | } | |
7845 | ||
0e8ffe1b DV |
7846 | static bool haswell_get_pipe_config(struct intel_crtc *crtc, |
7847 | struct intel_crtc_config *pipe_config) | |
7848 | { | |
7849 | struct drm_device *dev = crtc->base.dev; | |
7850 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2fa2fe9a | 7851 | enum intel_display_power_domain pfit_domain; |
0e8ffe1b DV |
7852 | uint32_t tmp; |
7853 | ||
b5482bd0 ID |
7854 | if (!intel_display_power_enabled(dev_priv, |
7855 | POWER_DOMAIN_PIPE(crtc->pipe))) | |
7856 | return false; | |
7857 | ||
e143a21c | 7858 | pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; |
c0d43d62 DV |
7859 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
7860 | ||
eccb140b DV |
7861 | tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP)); |
7862 | if (tmp & TRANS_DDI_FUNC_ENABLE) { | |
7863 | enum pipe trans_edp_pipe; | |
7864 | switch (tmp & TRANS_DDI_EDP_INPUT_MASK) { | |
7865 | default: | |
7866 | WARN(1, "unknown pipe linked to edp transcoder\n"); | |
7867 | case TRANS_DDI_EDP_INPUT_A_ONOFF: | |
7868 | case TRANS_DDI_EDP_INPUT_A_ON: | |
7869 | trans_edp_pipe = PIPE_A; | |
7870 | break; | |
7871 | case TRANS_DDI_EDP_INPUT_B_ONOFF: | |
7872 | trans_edp_pipe = PIPE_B; | |
7873 | break; | |
7874 | case TRANS_DDI_EDP_INPUT_C_ONOFF: | |
7875 | trans_edp_pipe = PIPE_C; | |
7876 | break; | |
7877 | } | |
7878 | ||
7879 | if (trans_edp_pipe == crtc->pipe) | |
7880 | pipe_config->cpu_transcoder = TRANSCODER_EDP; | |
7881 | } | |
7882 | ||
da7e29bd | 7883 | if (!intel_display_power_enabled(dev_priv, |
eccb140b | 7884 | POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder))) |
2bfce950 PZ |
7885 | return false; |
7886 | ||
eccb140b | 7887 | tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder)); |
0e8ffe1b DV |
7888 | if (!(tmp & PIPECONF_ENABLE)) |
7889 | return false; | |
7890 | ||
26804afd | 7891 | haswell_get_ddi_port_state(crtc, pipe_config); |
627eb5a3 | 7892 | |
1bd1bd80 DV |
7893 | intel_get_pipe_timings(crtc, pipe_config); |
7894 | ||
2fa2fe9a | 7895 | pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe); |
da7e29bd | 7896 | if (intel_display_power_enabled(dev_priv, pfit_domain)) |
2fa2fe9a | 7897 | ironlake_get_pfit_config(crtc, pipe_config); |
88adfff1 | 7898 | |
e59150dc JB |
7899 | if (IS_HASWELL(dev)) |
7900 | pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) && | |
7901 | (I915_READ(IPS_CTL) & IPS_ENABLE); | |
42db64ef | 7902 | |
6c49f241 DV |
7903 | pipe_config->pixel_multiplier = 1; |
7904 | ||
0e8ffe1b DV |
7905 | return true; |
7906 | } | |
7907 | ||
1a91510d JN |
7908 | static struct { |
7909 | int clock; | |
7910 | u32 config; | |
7911 | } hdmi_audio_clock[] = { | |
7912 | { DIV_ROUND_UP(25200 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_25175 }, | |
7913 | { 25200, AUD_CONFIG_PIXEL_CLOCK_HDMI_25200 }, /* default per bspec */ | |
7914 | { 27000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27000 }, | |
7915 | { 27000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_27027 }, | |
7916 | { 54000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54000 }, | |
7917 | { 54000 * 1001 / 1000, AUD_CONFIG_PIXEL_CLOCK_HDMI_54054 }, | |
7918 | { DIV_ROUND_UP(74250 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_74176 }, | |
7919 | { 74250, AUD_CONFIG_PIXEL_CLOCK_HDMI_74250 }, | |
7920 | { DIV_ROUND_UP(148500 * 1000, 1001), AUD_CONFIG_PIXEL_CLOCK_HDMI_148352 }, | |
7921 | { 148500, AUD_CONFIG_PIXEL_CLOCK_HDMI_148500 }, | |
7922 | }; | |
7923 | ||
7924 | /* get AUD_CONFIG_PIXEL_CLOCK_HDMI_* value for mode */ | |
7925 | static u32 audio_config_hdmi_pixel_clock(struct drm_display_mode *mode) | |
7926 | { | |
7927 | int i; | |
7928 | ||
7929 | for (i = 0; i < ARRAY_SIZE(hdmi_audio_clock); i++) { | |
7930 | if (mode->clock == hdmi_audio_clock[i].clock) | |
7931 | break; | |
7932 | } | |
7933 | ||
7934 | if (i == ARRAY_SIZE(hdmi_audio_clock)) { | |
7935 | DRM_DEBUG_KMS("HDMI audio pixel clock setting for %d not found, falling back to defaults\n", mode->clock); | |
7936 | i = 1; | |
7937 | } | |
7938 | ||
7939 | DRM_DEBUG_KMS("Configuring HDMI audio for pixel clock %d (0x%08x)\n", | |
7940 | hdmi_audio_clock[i].clock, | |
7941 | hdmi_audio_clock[i].config); | |
7942 | ||
7943 | return hdmi_audio_clock[i].config; | |
7944 | } | |
7945 | ||
3a9627f4 WF |
7946 | static bool intel_eld_uptodate(struct drm_connector *connector, |
7947 | int reg_eldv, uint32_t bits_eldv, | |
7948 | int reg_elda, uint32_t bits_elda, | |
7949 | int reg_edid) | |
7950 | { | |
7951 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7952 | uint8_t *eld = connector->eld; | |
7953 | uint32_t i; | |
7954 | ||
7955 | i = I915_READ(reg_eldv); | |
7956 | i &= bits_eldv; | |
7957 | ||
7958 | if (!eld[0]) | |
7959 | return !i; | |
7960 | ||
7961 | if (!i) | |
7962 | return false; | |
7963 | ||
7964 | i = I915_READ(reg_elda); | |
7965 | i &= ~bits_elda; | |
7966 | I915_WRITE(reg_elda, i); | |
7967 | ||
7968 | for (i = 0; i < eld[2]; i++) | |
7969 | if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) | |
7970 | return false; | |
7971 | ||
7972 | return true; | |
7973 | } | |
7974 | ||
e0dac65e | 7975 | static void g4x_write_eld(struct drm_connector *connector, |
34427052 JN |
7976 | struct drm_crtc *crtc, |
7977 | struct drm_display_mode *mode) | |
e0dac65e WF |
7978 | { |
7979 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
7980 | uint8_t *eld = connector->eld; | |
7981 | uint32_t eldv; | |
7982 | uint32_t len; | |
7983 | uint32_t i; | |
7984 | ||
7985 | i = I915_READ(G4X_AUD_VID_DID); | |
7986 | ||
7987 | if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL) | |
7988 | eldv = G4X_ELDV_DEVCL_DEVBLC; | |
7989 | else | |
7990 | eldv = G4X_ELDV_DEVCTG; | |
7991 | ||
3a9627f4 WF |
7992 | if (intel_eld_uptodate(connector, |
7993 | G4X_AUD_CNTL_ST, eldv, | |
7994 | G4X_AUD_CNTL_ST, G4X_ELD_ADDR, | |
7995 | G4X_HDMIW_HDMIEDID)) | |
7996 | return; | |
7997 | ||
e0dac65e WF |
7998 | i = I915_READ(G4X_AUD_CNTL_ST); |
7999 | i &= ~(eldv | G4X_ELD_ADDR); | |
8000 | len = (i >> 9) & 0x1f; /* ELD buffer size */ | |
8001 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
8002 | ||
8003 | if (!eld[0]) | |
8004 | return; | |
8005 | ||
8006 | len = min_t(uint8_t, eld[2], len); | |
8007 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
8008 | for (i = 0; i < len; i++) | |
8009 | I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); | |
8010 | ||
8011 | i = I915_READ(G4X_AUD_CNTL_ST); | |
8012 | i |= eldv; | |
8013 | I915_WRITE(G4X_AUD_CNTL_ST, i); | |
8014 | } | |
8015 | ||
83358c85 | 8016 | static void haswell_write_eld(struct drm_connector *connector, |
34427052 JN |
8017 | struct drm_crtc *crtc, |
8018 | struct drm_display_mode *mode) | |
83358c85 WX |
8019 | { |
8020 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
8021 | uint8_t *eld = connector->eld; | |
83358c85 WX |
8022 | uint32_t eldv; |
8023 | uint32_t i; | |
8024 | int len; | |
8025 | int pipe = to_intel_crtc(crtc)->pipe; | |
8026 | int tmp; | |
8027 | ||
8028 | int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe); | |
8029 | int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe); | |
8030 | int aud_config = HSW_AUD_CFG(pipe); | |
8031 | int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD; | |
8032 | ||
83358c85 WX |
8033 | /* Audio output enable */ |
8034 | DRM_DEBUG_DRIVER("HDMI audio: enable codec\n"); | |
8035 | tmp = I915_READ(aud_cntrl_st2); | |
8036 | tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4)); | |
8037 | I915_WRITE(aud_cntrl_st2, tmp); | |
c7905792 | 8038 | POSTING_READ(aud_cntrl_st2); |
83358c85 | 8039 | |
c7905792 | 8040 | assert_pipe_disabled(dev_priv, to_intel_crtc(crtc)->pipe); |
83358c85 WX |
8041 | |
8042 | /* Set ELD valid state */ | |
8043 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 8044 | DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp); |
83358c85 WX |
8045 | tmp |= (AUDIO_ELD_VALID_A << (pipe * 4)); |
8046 | I915_WRITE(aud_cntrl_st2, tmp); | |
8047 | tmp = I915_READ(aud_cntrl_st2); | |
7e7cb34f | 8048 | DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp); |
83358c85 WX |
8049 | |
8050 | /* Enable HDMI mode */ | |
8051 | tmp = I915_READ(aud_config); | |
7e7cb34f | 8052 | DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp); |
83358c85 WX |
8053 | /* clear N_programing_enable and N_value_index */ |
8054 | tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE); | |
8055 | I915_WRITE(aud_config, tmp); | |
8056 | ||
8057 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); | |
8058 | ||
8059 | eldv = AUDIO_ELD_VALID_A << (pipe * 4); | |
8060 | ||
8061 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { | |
8062 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
8063 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
8064 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ | |
1a91510d JN |
8065 | } else { |
8066 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
8067 | } | |
83358c85 WX |
8068 | |
8069 | if (intel_eld_uptodate(connector, | |
8070 | aud_cntrl_st2, eldv, | |
8071 | aud_cntl_st, IBX_ELD_ADDRESS, | |
8072 | hdmiw_hdmiedid)) | |
8073 | return; | |
8074 | ||
8075 | i = I915_READ(aud_cntrl_st2); | |
8076 | i &= ~eldv; | |
8077 | I915_WRITE(aud_cntrl_st2, i); | |
8078 | ||
8079 | if (!eld[0]) | |
8080 | return; | |
8081 | ||
8082 | i = I915_READ(aud_cntl_st); | |
8083 | i &= ~IBX_ELD_ADDRESS; | |
8084 | I915_WRITE(aud_cntl_st, i); | |
8085 | i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */ | |
8086 | DRM_DEBUG_DRIVER("port num:%d\n", i); | |
8087 | ||
8088 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
8089 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
8090 | for (i = 0; i < len; i++) | |
8091 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
8092 | ||
8093 | i = I915_READ(aud_cntrl_st2); | |
8094 | i |= eldv; | |
8095 | I915_WRITE(aud_cntrl_st2, i); | |
8096 | ||
8097 | } | |
8098 | ||
e0dac65e | 8099 | static void ironlake_write_eld(struct drm_connector *connector, |
34427052 JN |
8100 | struct drm_crtc *crtc, |
8101 | struct drm_display_mode *mode) | |
e0dac65e WF |
8102 | { |
8103 | struct drm_i915_private *dev_priv = connector->dev->dev_private; | |
8104 | uint8_t *eld = connector->eld; | |
8105 | uint32_t eldv; | |
8106 | uint32_t i; | |
8107 | int len; | |
8108 | int hdmiw_hdmiedid; | |
b6daa025 | 8109 | int aud_config; |
e0dac65e WF |
8110 | int aud_cntl_st; |
8111 | int aud_cntrl_st2; | |
9b138a83 | 8112 | int pipe = to_intel_crtc(crtc)->pipe; |
e0dac65e | 8113 | |
b3f33cbf | 8114 | if (HAS_PCH_IBX(connector->dev)) { |
9b138a83 WX |
8115 | hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); |
8116 | aud_config = IBX_AUD_CFG(pipe); | |
8117 | aud_cntl_st = IBX_AUD_CNTL_ST(pipe); | |
1202b4c6 | 8118 | aud_cntrl_st2 = IBX_AUD_CNTL_ST2; |
9ca2fe73 ML |
8119 | } else if (IS_VALLEYVIEW(connector->dev)) { |
8120 | hdmiw_hdmiedid = VLV_HDMIW_HDMIEDID(pipe); | |
8121 | aud_config = VLV_AUD_CFG(pipe); | |
8122 | aud_cntl_st = VLV_AUD_CNTL_ST(pipe); | |
8123 | aud_cntrl_st2 = VLV_AUD_CNTL_ST2; | |
e0dac65e | 8124 | } else { |
9b138a83 WX |
8125 | hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe); |
8126 | aud_config = CPT_AUD_CFG(pipe); | |
8127 | aud_cntl_st = CPT_AUD_CNTL_ST(pipe); | |
1202b4c6 | 8128 | aud_cntrl_st2 = CPT_AUD_CNTRL_ST2; |
e0dac65e WF |
8129 | } |
8130 | ||
9b138a83 | 8131 | DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe)); |
e0dac65e | 8132 | |
9ca2fe73 ML |
8133 | if (IS_VALLEYVIEW(connector->dev)) { |
8134 | struct intel_encoder *intel_encoder; | |
8135 | struct intel_digital_port *intel_dig_port; | |
8136 | ||
8137 | intel_encoder = intel_attached_encoder(connector); | |
8138 | intel_dig_port = enc_to_dig_port(&intel_encoder->base); | |
8139 | i = intel_dig_port->port; | |
8140 | } else { | |
8141 | i = I915_READ(aud_cntl_st); | |
8142 | i = (i >> 29) & DIP_PORT_SEL_MASK; | |
8143 | /* DIP_Port_Select, 0x1 = PortB */ | |
8144 | } | |
8145 | ||
e0dac65e WF |
8146 | if (!i) { |
8147 | DRM_DEBUG_DRIVER("Audio directed to unknown port\n"); | |
8148 | /* operate blindly on all ports */ | |
1202b4c6 WF |
8149 | eldv = IBX_ELD_VALIDB; |
8150 | eldv |= IBX_ELD_VALIDB << 4; | |
8151 | eldv |= IBX_ELD_VALIDB << 8; | |
e0dac65e | 8152 | } else { |
2582a850 | 8153 | DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i)); |
1202b4c6 | 8154 | eldv = IBX_ELD_VALIDB << ((i - 1) * 4); |
e0dac65e WF |
8155 | } |
8156 | ||
3a9627f4 WF |
8157 | if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) { |
8158 | DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n"); | |
8159 | eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */ | |
b6daa025 | 8160 | I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */ |
1a91510d JN |
8161 | } else { |
8162 | I915_WRITE(aud_config, audio_config_hdmi_pixel_clock(mode)); | |
8163 | } | |
e0dac65e | 8164 | |
3a9627f4 WF |
8165 | if (intel_eld_uptodate(connector, |
8166 | aud_cntrl_st2, eldv, | |
8167 | aud_cntl_st, IBX_ELD_ADDRESS, | |
8168 | hdmiw_hdmiedid)) | |
8169 | return; | |
8170 | ||
e0dac65e WF |
8171 | i = I915_READ(aud_cntrl_st2); |
8172 | i &= ~eldv; | |
8173 | I915_WRITE(aud_cntrl_st2, i); | |
8174 | ||
8175 | if (!eld[0]) | |
8176 | return; | |
8177 | ||
e0dac65e | 8178 | i = I915_READ(aud_cntl_st); |
1202b4c6 | 8179 | i &= ~IBX_ELD_ADDRESS; |
e0dac65e WF |
8180 | I915_WRITE(aud_cntl_st, i); |
8181 | ||
8182 | len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */ | |
8183 | DRM_DEBUG_DRIVER("ELD size %d\n", len); | |
8184 | for (i = 0; i < len; i++) | |
8185 | I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); | |
8186 | ||
8187 | i = I915_READ(aud_cntrl_st2); | |
8188 | i |= eldv; | |
8189 | I915_WRITE(aud_cntrl_st2, i); | |
8190 | } | |
8191 | ||
8192 | void intel_write_eld(struct drm_encoder *encoder, | |
8193 | struct drm_display_mode *mode) | |
8194 | { | |
8195 | struct drm_crtc *crtc = encoder->crtc; | |
8196 | struct drm_connector *connector; | |
8197 | struct drm_device *dev = encoder->dev; | |
8198 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8199 | ||
8200 | connector = drm_select_eld(encoder, mode); | |
8201 | if (!connector) | |
8202 | return; | |
8203 | ||
8204 | DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", | |
8205 | connector->base.id, | |
c23cc417 | 8206 | connector->name, |
e0dac65e | 8207 | connector->encoder->base.id, |
8e329a03 | 8208 | connector->encoder->name); |
e0dac65e WF |
8209 | |
8210 | connector->eld[6] = drm_av_sync_delay(connector, mode) / 2; | |
8211 | ||
8212 | if (dev_priv->display.write_eld) | |
34427052 | 8213 | dev_priv->display.write_eld(connector, crtc, mode); |
e0dac65e WF |
8214 | } |
8215 | ||
560b85bb CW |
8216 | static void i845_update_cursor(struct drm_crtc *crtc, u32 base) |
8217 | { | |
8218 | struct drm_device *dev = crtc->dev; | |
8219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8220 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
dc41c154 | 8221 | uint32_t cntl = 0, size = 0; |
560b85bb | 8222 | |
dc41c154 VS |
8223 | if (base) { |
8224 | unsigned int width = intel_crtc->cursor_width; | |
8225 | unsigned int height = intel_crtc->cursor_height; | |
8226 | unsigned int stride = roundup_pow_of_two(width) * 4; | |
8227 | ||
8228 | switch (stride) { | |
8229 | default: | |
8230 | WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n", | |
8231 | width, stride); | |
8232 | stride = 256; | |
8233 | /* fallthrough */ | |
8234 | case 256: | |
8235 | case 512: | |
8236 | case 1024: | |
8237 | case 2048: | |
8238 | break; | |
4b0e333e CW |
8239 | } |
8240 | ||
dc41c154 VS |
8241 | cntl |= CURSOR_ENABLE | |
8242 | CURSOR_GAMMA_ENABLE | | |
8243 | CURSOR_FORMAT_ARGB | | |
8244 | CURSOR_STRIDE(stride); | |
8245 | ||
8246 | size = (height << 12) | width; | |
4b0e333e | 8247 | } |
560b85bb | 8248 | |
dc41c154 VS |
8249 | if (intel_crtc->cursor_cntl != 0 && |
8250 | (intel_crtc->cursor_base != base || | |
8251 | intel_crtc->cursor_size != size || | |
8252 | intel_crtc->cursor_cntl != cntl)) { | |
8253 | /* On these chipsets we can only modify the base/size/stride | |
8254 | * whilst the cursor is disabled. | |
8255 | */ | |
8256 | I915_WRITE(_CURACNTR, 0); | |
4b0e333e | 8257 | POSTING_READ(_CURACNTR); |
dc41c154 | 8258 | intel_crtc->cursor_cntl = 0; |
4b0e333e | 8259 | } |
560b85bb | 8260 | |
99d1f387 | 8261 | if (intel_crtc->cursor_base != base) { |
9db4a9c7 | 8262 | I915_WRITE(_CURABASE, base); |
99d1f387 VS |
8263 | intel_crtc->cursor_base = base; |
8264 | } | |
4726e0b0 | 8265 | |
dc41c154 VS |
8266 | if (intel_crtc->cursor_size != size) { |
8267 | I915_WRITE(CURSIZE, size); | |
8268 | intel_crtc->cursor_size = size; | |
4b0e333e | 8269 | } |
560b85bb | 8270 | |
4b0e333e | 8271 | if (intel_crtc->cursor_cntl != cntl) { |
4b0e333e CW |
8272 | I915_WRITE(_CURACNTR, cntl); |
8273 | POSTING_READ(_CURACNTR); | |
4b0e333e | 8274 | intel_crtc->cursor_cntl = cntl; |
560b85bb | 8275 | } |
560b85bb CW |
8276 | } |
8277 | ||
560b85bb | 8278 | static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base) |
65a21cd6 JB |
8279 | { |
8280 | struct drm_device *dev = crtc->dev; | |
8281 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8282 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8283 | int pipe = intel_crtc->pipe; | |
4b0e333e CW |
8284 | uint32_t cntl; |
8285 | ||
8286 | cntl = 0; | |
8287 | if (base) { | |
8288 | cntl = MCURSOR_GAMMA_ENABLE; | |
8289 | switch (intel_crtc->cursor_width) { | |
4726e0b0 SK |
8290 | case 64: |
8291 | cntl |= CURSOR_MODE_64_ARGB_AX; | |
8292 | break; | |
8293 | case 128: | |
8294 | cntl |= CURSOR_MODE_128_ARGB_AX; | |
8295 | break; | |
8296 | case 256: | |
8297 | cntl |= CURSOR_MODE_256_ARGB_AX; | |
8298 | break; | |
8299 | default: | |
8300 | WARN_ON(1); | |
8301 | return; | |
65a21cd6 | 8302 | } |
4b0e333e | 8303 | cntl |= pipe << 28; /* Connect to correct pipe */ |
4b0e333e CW |
8304 | } |
8305 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
8306 | cntl |= CURSOR_PIPE_CSC_ENABLE; | |
65a21cd6 | 8307 | |
4b0e333e CW |
8308 | if (intel_crtc->cursor_cntl != cntl) { |
8309 | I915_WRITE(CURCNTR(pipe), cntl); | |
8310 | POSTING_READ(CURCNTR(pipe)); | |
8311 | intel_crtc->cursor_cntl = cntl; | |
65a21cd6 | 8312 | } |
4b0e333e | 8313 | |
65a21cd6 | 8314 | /* and commit changes on next vblank */ |
5efb3e28 VS |
8315 | I915_WRITE(CURBASE(pipe), base); |
8316 | POSTING_READ(CURBASE(pipe)); | |
99d1f387 VS |
8317 | |
8318 | intel_crtc->cursor_base = base; | |
65a21cd6 JB |
8319 | } |
8320 | ||
cda4b7d3 | 8321 | /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */ |
6b383a7f CW |
8322 | static void intel_crtc_update_cursor(struct drm_crtc *crtc, |
8323 | bool on) | |
cda4b7d3 CW |
8324 | { |
8325 | struct drm_device *dev = crtc->dev; | |
8326 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8327 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
8328 | int pipe = intel_crtc->pipe; | |
3d7d6510 MR |
8329 | int x = crtc->cursor_x; |
8330 | int y = crtc->cursor_y; | |
d6e4db15 | 8331 | u32 base = 0, pos = 0; |
cda4b7d3 | 8332 | |
d6e4db15 | 8333 | if (on) |
cda4b7d3 | 8334 | base = intel_crtc->cursor_addr; |
cda4b7d3 | 8335 | |
d6e4db15 VS |
8336 | if (x >= intel_crtc->config.pipe_src_w) |
8337 | base = 0; | |
8338 | ||
8339 | if (y >= intel_crtc->config.pipe_src_h) | |
cda4b7d3 CW |
8340 | base = 0; |
8341 | ||
8342 | if (x < 0) { | |
efc9064e | 8343 | if (x + intel_crtc->cursor_width <= 0) |
cda4b7d3 CW |
8344 | base = 0; |
8345 | ||
8346 | pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT; | |
8347 | x = -x; | |
8348 | } | |
8349 | pos |= x << CURSOR_X_SHIFT; | |
8350 | ||
8351 | if (y < 0) { | |
efc9064e | 8352 | if (y + intel_crtc->cursor_height <= 0) |
cda4b7d3 CW |
8353 | base = 0; |
8354 | ||
8355 | pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT; | |
8356 | y = -y; | |
8357 | } | |
8358 | pos |= y << CURSOR_Y_SHIFT; | |
8359 | ||
4b0e333e | 8360 | if (base == 0 && intel_crtc->cursor_base == 0) |
cda4b7d3 CW |
8361 | return; |
8362 | ||
5efb3e28 VS |
8363 | I915_WRITE(CURPOS(pipe), pos); |
8364 | ||
8ac54669 | 8365 | if (IS_845G(dev) || IS_I865G(dev)) |
5efb3e28 VS |
8366 | i845_update_cursor(crtc, base); |
8367 | else | |
8368 | i9xx_update_cursor(crtc, base); | |
cda4b7d3 CW |
8369 | } |
8370 | ||
dc41c154 VS |
8371 | static bool cursor_size_ok(struct drm_device *dev, |
8372 | uint32_t width, uint32_t height) | |
8373 | { | |
8374 | if (width == 0 || height == 0) | |
8375 | return false; | |
8376 | ||
8377 | /* | |
8378 | * 845g/865g are special in that they are only limited by | |
8379 | * the width of their cursors, the height is arbitrary up to | |
8380 | * the precision of the register. Everything else requires | |
8381 | * square cursors, limited to a few power-of-two sizes. | |
8382 | */ | |
8383 | if (IS_845G(dev) || IS_I865G(dev)) { | |
8384 | if ((width & 63) != 0) | |
8385 | return false; | |
8386 | ||
8387 | if (width > (IS_845G(dev) ? 64 : 512)) | |
8388 | return false; | |
8389 | ||
8390 | if (height > 1023) | |
8391 | return false; | |
8392 | } else { | |
8393 | switch (width | height) { | |
8394 | case 256: | |
8395 | case 128: | |
8396 | if (IS_GEN2(dev)) | |
8397 | return false; | |
8398 | case 64: | |
8399 | break; | |
8400 | default: | |
8401 | return false; | |
8402 | } | |
8403 | } | |
8404 | ||
8405 | return true; | |
8406 | } | |
8407 | ||
e3287951 MR |
8408 | /* |
8409 | * intel_crtc_cursor_set_obj - Set cursor to specified GEM object | |
8410 | * | |
8411 | * Note that the object's reference will be consumed if the update fails. If | |
8412 | * the update succeeds, the reference of the old object (if any) will be | |
8413 | * consumed. | |
8414 | */ | |
8415 | static int intel_crtc_cursor_set_obj(struct drm_crtc *crtc, | |
8416 | struct drm_i915_gem_object *obj, | |
8417 | uint32_t width, uint32_t height) | |
79e53945 JB |
8418 | { |
8419 | struct drm_device *dev = crtc->dev; | |
8420 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8421 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
a071fa00 | 8422 | enum pipe pipe = intel_crtc->pipe; |
dc41c154 | 8423 | unsigned old_width, stride; |
cda4b7d3 | 8424 | uint32_t addr; |
3f8bc370 | 8425 | int ret; |
79e53945 | 8426 | |
79e53945 | 8427 | /* if we want to turn off the cursor ignore width and height */ |
e3287951 | 8428 | if (!obj) { |
28c97730 | 8429 | DRM_DEBUG_KMS("cursor off\n"); |
3f8bc370 | 8430 | addr = 0; |
5004417d | 8431 | mutex_lock(&dev->struct_mutex); |
3f8bc370 | 8432 | goto finish; |
79e53945 JB |
8433 | } |
8434 | ||
4726e0b0 | 8435 | /* Check for which cursor types we support */ |
dc41c154 | 8436 | if (!cursor_size_ok(dev, width, height)) { |
4726e0b0 | 8437 | DRM_DEBUG("Cursor dimension not supported\n"); |
79e53945 JB |
8438 | return -EINVAL; |
8439 | } | |
8440 | ||
dc41c154 VS |
8441 | stride = roundup_pow_of_two(width) * 4; |
8442 | if (obj->base.size < stride * height) { | |
e3287951 | 8443 | DRM_DEBUG_KMS("buffer is too small\n"); |
34b8686e DA |
8444 | ret = -ENOMEM; |
8445 | goto fail; | |
79e53945 JB |
8446 | } |
8447 | ||
71acb5eb | 8448 | /* we only need to pin inside GTT if cursor is non-phy */ |
7f9872e0 | 8449 | mutex_lock(&dev->struct_mutex); |
3d13ef2e | 8450 | if (!INTEL_INFO(dev)->cursor_needs_physical) { |
693db184 CW |
8451 | unsigned alignment; |
8452 | ||
d9e86c0e | 8453 | if (obj->tiling_mode) { |
3b25b31f | 8454 | DRM_DEBUG_KMS("cursor cannot be tiled\n"); |
d9e86c0e CW |
8455 | ret = -EINVAL; |
8456 | goto fail_locked; | |
8457 | } | |
8458 | ||
d6dd6843 PZ |
8459 | /* |
8460 | * Global gtt pte registers are special registers which actually | |
8461 | * forward writes to a chunk of system memory. Which means that | |
8462 | * there is no risk that the register values disappear as soon | |
8463 | * as we call intel_runtime_pm_put(), so it is correct to wrap | |
8464 | * only the pin/unpin/fence and not more. | |
8465 | */ | |
8466 | intel_runtime_pm_get(dev_priv); | |
8467 | ||
693db184 CW |
8468 | /* Note that the w/a also requires 2 PTE of padding following |
8469 | * the bo. We currently fill all unused PTE with the shadow | |
8470 | * page and so we should always have valid PTE following the | |
8471 | * cursor preventing the VT-d warning. | |
8472 | */ | |
8473 | alignment = 0; | |
8474 | if (need_vtd_wa(dev)) | |
8475 | alignment = 64*1024; | |
8476 | ||
8477 | ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL); | |
e7b526bb | 8478 | if (ret) { |
3b25b31f | 8479 | DRM_DEBUG_KMS("failed to move cursor bo into the GTT\n"); |
d6dd6843 | 8480 | intel_runtime_pm_put(dev_priv); |
2da3b9b9 | 8481 | goto fail_locked; |
e7b526bb CW |
8482 | } |
8483 | ||
d9e86c0e CW |
8484 | ret = i915_gem_object_put_fence(obj); |
8485 | if (ret) { | |
3b25b31f | 8486 | DRM_DEBUG_KMS("failed to release fence for cursor"); |
d6dd6843 | 8487 | intel_runtime_pm_put(dev_priv); |
d9e86c0e CW |
8488 | goto fail_unpin; |
8489 | } | |
8490 | ||
f343c5f6 | 8491 | addr = i915_gem_obj_ggtt_offset(obj); |
d6dd6843 PZ |
8492 | |
8493 | intel_runtime_pm_put(dev_priv); | |
71acb5eb | 8494 | } else { |
6eeefaf3 | 8495 | int align = IS_I830(dev) ? 16 * 1024 : 256; |
00731155 | 8496 | ret = i915_gem_object_attach_phys(obj, align); |
71acb5eb | 8497 | if (ret) { |
3b25b31f | 8498 | DRM_DEBUG_KMS("failed to attach phys object\n"); |
7f9872e0 | 8499 | goto fail_locked; |
71acb5eb | 8500 | } |
00731155 | 8501 | addr = obj->phys_handle->busaddr; |
3f8bc370 KH |
8502 | } |
8503 | ||
3f8bc370 | 8504 | finish: |
3f8bc370 | 8505 | if (intel_crtc->cursor_bo) { |
00731155 | 8506 | if (!INTEL_INFO(dev)->cursor_needs_physical) |
cc98b413 | 8507 | i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo); |
3f8bc370 | 8508 | } |
80824003 | 8509 | |
a071fa00 DV |
8510 | i915_gem_track_fb(intel_crtc->cursor_bo, obj, |
8511 | INTEL_FRONTBUFFER_CURSOR(pipe)); | |
7f9872e0 | 8512 | mutex_unlock(&dev->struct_mutex); |
3f8bc370 | 8513 | |
64f962e3 CW |
8514 | old_width = intel_crtc->cursor_width; |
8515 | ||
3f8bc370 | 8516 | intel_crtc->cursor_addr = addr; |
05394f39 | 8517 | intel_crtc->cursor_bo = obj; |
cda4b7d3 CW |
8518 | intel_crtc->cursor_width = width; |
8519 | intel_crtc->cursor_height = height; | |
8520 | ||
64f962e3 CW |
8521 | if (intel_crtc->active) { |
8522 | if (old_width != width) | |
8523 | intel_update_watermarks(crtc); | |
f2f5f771 | 8524 | intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL); |
64f962e3 | 8525 | } |
3f8bc370 | 8526 | |
f99d7069 DV |
8527 | intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_CURSOR(pipe)); |
8528 | ||
79e53945 | 8529 | return 0; |
e7b526bb | 8530 | fail_unpin: |
cc98b413 | 8531 | i915_gem_object_unpin_from_display_plane(obj); |
7f9872e0 | 8532 | fail_locked: |
34b8686e | 8533 | mutex_unlock(&dev->struct_mutex); |
bc9025bd | 8534 | fail: |
05394f39 | 8535 | drm_gem_object_unreference_unlocked(&obj->base); |
34b8686e | 8536 | return ret; |
79e53945 JB |
8537 | } |
8538 | ||
79e53945 | 8539 | static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, |
7203425a | 8540 | u16 *blue, uint32_t start, uint32_t size) |
79e53945 | 8541 | { |
7203425a | 8542 | int end = (start + size > 256) ? 256 : start + size, i; |
79e53945 | 8543 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8544 | |
7203425a | 8545 | for (i = start; i < end; i++) { |
79e53945 JB |
8546 | intel_crtc->lut_r[i] = red[i] >> 8; |
8547 | intel_crtc->lut_g[i] = green[i] >> 8; | |
8548 | intel_crtc->lut_b[i] = blue[i] >> 8; | |
8549 | } | |
8550 | ||
8551 | intel_crtc_load_lut(crtc); | |
8552 | } | |
8553 | ||
79e53945 JB |
8554 | /* VESA 640x480x72Hz mode to set on the pipe */ |
8555 | static struct drm_display_mode load_detect_mode = { | |
8556 | DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664, | |
8557 | 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), | |
8558 | }; | |
8559 | ||
a8bb6818 DV |
8560 | struct drm_framebuffer * |
8561 | __intel_framebuffer_create(struct drm_device *dev, | |
8562 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8563 | struct drm_i915_gem_object *obj) | |
d2dff872 CW |
8564 | { |
8565 | struct intel_framebuffer *intel_fb; | |
8566 | int ret; | |
8567 | ||
8568 | intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL); | |
8569 | if (!intel_fb) { | |
8570 | drm_gem_object_unreference_unlocked(&obj->base); | |
8571 | return ERR_PTR(-ENOMEM); | |
8572 | } | |
8573 | ||
8574 | ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj); | |
dd4916c5 DV |
8575 | if (ret) |
8576 | goto err; | |
d2dff872 CW |
8577 | |
8578 | return &intel_fb->base; | |
dd4916c5 DV |
8579 | err: |
8580 | drm_gem_object_unreference_unlocked(&obj->base); | |
8581 | kfree(intel_fb); | |
8582 | ||
8583 | return ERR_PTR(ret); | |
d2dff872 CW |
8584 | } |
8585 | ||
b5ea642a | 8586 | static struct drm_framebuffer * |
a8bb6818 DV |
8587 | intel_framebuffer_create(struct drm_device *dev, |
8588 | struct drm_mode_fb_cmd2 *mode_cmd, | |
8589 | struct drm_i915_gem_object *obj) | |
8590 | { | |
8591 | struct drm_framebuffer *fb; | |
8592 | int ret; | |
8593 | ||
8594 | ret = i915_mutex_lock_interruptible(dev); | |
8595 | if (ret) | |
8596 | return ERR_PTR(ret); | |
8597 | fb = __intel_framebuffer_create(dev, mode_cmd, obj); | |
8598 | mutex_unlock(&dev->struct_mutex); | |
8599 | ||
8600 | return fb; | |
8601 | } | |
8602 | ||
d2dff872 CW |
8603 | static u32 |
8604 | intel_framebuffer_pitch_for_width(int width, int bpp) | |
8605 | { | |
8606 | u32 pitch = DIV_ROUND_UP(width * bpp, 8); | |
8607 | return ALIGN(pitch, 64); | |
8608 | } | |
8609 | ||
8610 | static u32 | |
8611 | intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp) | |
8612 | { | |
8613 | u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp); | |
1267a26b | 8614 | return PAGE_ALIGN(pitch * mode->vdisplay); |
d2dff872 CW |
8615 | } |
8616 | ||
8617 | static struct drm_framebuffer * | |
8618 | intel_framebuffer_create_for_mode(struct drm_device *dev, | |
8619 | struct drm_display_mode *mode, | |
8620 | int depth, int bpp) | |
8621 | { | |
8622 | struct drm_i915_gem_object *obj; | |
0fed39bd | 8623 | struct drm_mode_fb_cmd2 mode_cmd = { 0 }; |
d2dff872 CW |
8624 | |
8625 | obj = i915_gem_alloc_object(dev, | |
8626 | intel_framebuffer_size_for_mode(mode, bpp)); | |
8627 | if (obj == NULL) | |
8628 | return ERR_PTR(-ENOMEM); | |
8629 | ||
8630 | mode_cmd.width = mode->hdisplay; | |
8631 | mode_cmd.height = mode->vdisplay; | |
308e5bcb JB |
8632 | mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width, |
8633 | bpp); | |
5ca0c34a | 8634 | mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth); |
d2dff872 CW |
8635 | |
8636 | return intel_framebuffer_create(dev, &mode_cmd, obj); | |
8637 | } | |
8638 | ||
8639 | static struct drm_framebuffer * | |
8640 | mode_fits_in_fbdev(struct drm_device *dev, | |
8641 | struct drm_display_mode *mode) | |
8642 | { | |
4520f53a | 8643 | #ifdef CONFIG_DRM_I915_FBDEV |
d2dff872 CW |
8644 | struct drm_i915_private *dev_priv = dev->dev_private; |
8645 | struct drm_i915_gem_object *obj; | |
8646 | struct drm_framebuffer *fb; | |
8647 | ||
4c0e5528 | 8648 | if (!dev_priv->fbdev) |
d2dff872 CW |
8649 | return NULL; |
8650 | ||
4c0e5528 | 8651 | if (!dev_priv->fbdev->fb) |
d2dff872 CW |
8652 | return NULL; |
8653 | ||
4c0e5528 DV |
8654 | obj = dev_priv->fbdev->fb->obj; |
8655 | BUG_ON(!obj); | |
8656 | ||
8bcd4553 | 8657 | fb = &dev_priv->fbdev->fb->base; |
01f2c773 VS |
8658 | if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay, |
8659 | fb->bits_per_pixel)) | |
d2dff872 CW |
8660 | return NULL; |
8661 | ||
01f2c773 | 8662 | if (obj->base.size < mode->vdisplay * fb->pitches[0]) |
d2dff872 CW |
8663 | return NULL; |
8664 | ||
8665 | return fb; | |
4520f53a DV |
8666 | #else |
8667 | return NULL; | |
8668 | #endif | |
d2dff872 CW |
8669 | } |
8670 | ||
d2434ab7 | 8671 | bool intel_get_load_detect_pipe(struct drm_connector *connector, |
7173188d | 8672 | struct drm_display_mode *mode, |
51fd371b RC |
8673 | struct intel_load_detect_pipe *old, |
8674 | struct drm_modeset_acquire_ctx *ctx) | |
79e53945 JB |
8675 | { |
8676 | struct intel_crtc *intel_crtc; | |
d2434ab7 DV |
8677 | struct intel_encoder *intel_encoder = |
8678 | intel_attached_encoder(connector); | |
79e53945 | 8679 | struct drm_crtc *possible_crtc; |
4ef69c7a | 8680 | struct drm_encoder *encoder = &intel_encoder->base; |
79e53945 JB |
8681 | struct drm_crtc *crtc = NULL; |
8682 | struct drm_device *dev = encoder->dev; | |
94352cf9 | 8683 | struct drm_framebuffer *fb; |
51fd371b RC |
8684 | struct drm_mode_config *config = &dev->mode_config; |
8685 | int ret, i = -1; | |
79e53945 | 8686 | |
d2dff872 | 8687 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8688 | connector->base.id, connector->name, |
8e329a03 | 8689 | encoder->base.id, encoder->name); |
d2dff872 | 8690 | |
51fd371b RC |
8691 | retry: |
8692 | ret = drm_modeset_lock(&config->connection_mutex, ctx); | |
8693 | if (ret) | |
8694 | goto fail_unlock; | |
6e9f798d | 8695 | |
79e53945 JB |
8696 | /* |
8697 | * Algorithm gets a little messy: | |
7a5e4805 | 8698 | * |
79e53945 JB |
8699 | * - if the connector already has an assigned crtc, use it (but make |
8700 | * sure it's on first) | |
7a5e4805 | 8701 | * |
79e53945 JB |
8702 | * - try to find the first unused crtc that can drive this connector, |
8703 | * and use that if we find one | |
79e53945 JB |
8704 | */ |
8705 | ||
8706 | /* See if we already have a CRTC for this connector */ | |
8707 | if (encoder->crtc) { | |
8708 | crtc = encoder->crtc; | |
8261b191 | 8709 | |
51fd371b RC |
8710 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
8711 | if (ret) | |
8712 | goto fail_unlock; | |
7b24056b | 8713 | |
24218aac | 8714 | old->dpms_mode = connector->dpms; |
8261b191 CW |
8715 | old->load_detect_temp = false; |
8716 | ||
8717 | /* Make sure the crtc and connector are running */ | |
24218aac DV |
8718 | if (connector->dpms != DRM_MODE_DPMS_ON) |
8719 | connector->funcs->dpms(connector, DRM_MODE_DPMS_ON); | |
8261b191 | 8720 | |
7173188d | 8721 | return true; |
79e53945 JB |
8722 | } |
8723 | ||
8724 | /* Find an unused one (if possible) */ | |
70e1e0ec | 8725 | for_each_crtc(dev, possible_crtc) { |
79e53945 JB |
8726 | i++; |
8727 | if (!(encoder->possible_crtcs & (1 << i))) | |
8728 | continue; | |
a459249c VS |
8729 | if (possible_crtc->enabled) |
8730 | continue; | |
8731 | /* This can occur when applying the pipe A quirk on resume. */ | |
8732 | if (to_intel_crtc(possible_crtc)->new_enabled) | |
8733 | continue; | |
8734 | ||
8735 | crtc = possible_crtc; | |
8736 | break; | |
79e53945 JB |
8737 | } |
8738 | ||
8739 | /* | |
8740 | * If we didn't find an unused CRTC, don't use any. | |
8741 | */ | |
8742 | if (!crtc) { | |
7173188d | 8743 | DRM_DEBUG_KMS("no pipe available for load-detect\n"); |
51fd371b | 8744 | goto fail_unlock; |
79e53945 JB |
8745 | } |
8746 | ||
51fd371b RC |
8747 | ret = drm_modeset_lock(&crtc->mutex, ctx); |
8748 | if (ret) | |
8749 | goto fail_unlock; | |
fc303101 DV |
8750 | intel_encoder->new_crtc = to_intel_crtc(crtc); |
8751 | to_intel_connector(connector)->new_encoder = intel_encoder; | |
79e53945 JB |
8752 | |
8753 | intel_crtc = to_intel_crtc(crtc); | |
412b61d8 VS |
8754 | intel_crtc->new_enabled = true; |
8755 | intel_crtc->new_config = &intel_crtc->config; | |
24218aac | 8756 | old->dpms_mode = connector->dpms; |
8261b191 | 8757 | old->load_detect_temp = true; |
d2dff872 | 8758 | old->release_fb = NULL; |
79e53945 | 8759 | |
6492711d CW |
8760 | if (!mode) |
8761 | mode = &load_detect_mode; | |
79e53945 | 8762 | |
d2dff872 CW |
8763 | /* We need a framebuffer large enough to accommodate all accesses |
8764 | * that the plane may generate whilst we perform load detection. | |
8765 | * We can not rely on the fbcon either being present (we get called | |
8766 | * during its initialisation to detect all boot displays, or it may | |
8767 | * not even exist) or that it is large enough to satisfy the | |
8768 | * requested mode. | |
8769 | */ | |
94352cf9 DV |
8770 | fb = mode_fits_in_fbdev(dev, mode); |
8771 | if (fb == NULL) { | |
d2dff872 | 8772 | DRM_DEBUG_KMS("creating tmp fb for load-detection\n"); |
94352cf9 DV |
8773 | fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32); |
8774 | old->release_fb = fb; | |
d2dff872 CW |
8775 | } else |
8776 | DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n"); | |
94352cf9 | 8777 | if (IS_ERR(fb)) { |
d2dff872 | 8778 | DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n"); |
412b61d8 | 8779 | goto fail; |
79e53945 | 8780 | } |
79e53945 | 8781 | |
c0c36b94 | 8782 | if (intel_set_mode(crtc, mode, 0, 0, fb)) { |
6492711d | 8783 | DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n"); |
d2dff872 CW |
8784 | if (old->release_fb) |
8785 | old->release_fb->funcs->destroy(old->release_fb); | |
412b61d8 | 8786 | goto fail; |
79e53945 | 8787 | } |
7173188d | 8788 | |
79e53945 | 8789 | /* let the connector get through one full cycle before testing */ |
9d0498a2 | 8790 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
7173188d | 8791 | return true; |
412b61d8 VS |
8792 | |
8793 | fail: | |
8794 | intel_crtc->new_enabled = crtc->enabled; | |
8795 | if (intel_crtc->new_enabled) | |
8796 | intel_crtc->new_config = &intel_crtc->config; | |
8797 | else | |
8798 | intel_crtc->new_config = NULL; | |
51fd371b RC |
8799 | fail_unlock: |
8800 | if (ret == -EDEADLK) { | |
8801 | drm_modeset_backoff(ctx); | |
8802 | goto retry; | |
8803 | } | |
8804 | ||
412b61d8 | 8805 | return false; |
79e53945 JB |
8806 | } |
8807 | ||
d2434ab7 | 8808 | void intel_release_load_detect_pipe(struct drm_connector *connector, |
208bf9fd | 8809 | struct intel_load_detect_pipe *old) |
79e53945 | 8810 | { |
d2434ab7 DV |
8811 | struct intel_encoder *intel_encoder = |
8812 | intel_attached_encoder(connector); | |
4ef69c7a | 8813 | struct drm_encoder *encoder = &intel_encoder->base; |
7b24056b | 8814 | struct drm_crtc *crtc = encoder->crtc; |
412b61d8 | 8815 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
79e53945 | 8816 | |
d2dff872 | 8817 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n", |
c23cc417 | 8818 | connector->base.id, connector->name, |
8e329a03 | 8819 | encoder->base.id, encoder->name); |
d2dff872 | 8820 | |
8261b191 | 8821 | if (old->load_detect_temp) { |
fc303101 DV |
8822 | to_intel_connector(connector)->new_encoder = NULL; |
8823 | intel_encoder->new_crtc = NULL; | |
412b61d8 VS |
8824 | intel_crtc->new_enabled = false; |
8825 | intel_crtc->new_config = NULL; | |
fc303101 | 8826 | intel_set_mode(crtc, NULL, 0, 0, NULL); |
d2dff872 | 8827 | |
36206361 DV |
8828 | if (old->release_fb) { |
8829 | drm_framebuffer_unregister_private(old->release_fb); | |
8830 | drm_framebuffer_unreference(old->release_fb); | |
8831 | } | |
d2dff872 | 8832 | |
0622a53c | 8833 | return; |
79e53945 JB |
8834 | } |
8835 | ||
c751ce4f | 8836 | /* Switch crtc and encoder back off if necessary */ |
24218aac DV |
8837 | if (old->dpms_mode != DRM_MODE_DPMS_ON) |
8838 | connector->funcs->dpms(connector, old->dpms_mode); | |
79e53945 JB |
8839 | } |
8840 | ||
da4a1efa VS |
8841 | static int i9xx_pll_refclk(struct drm_device *dev, |
8842 | const struct intel_crtc_config *pipe_config) | |
8843 | { | |
8844 | struct drm_i915_private *dev_priv = dev->dev_private; | |
8845 | u32 dpll = pipe_config->dpll_hw_state.dpll; | |
8846 | ||
8847 | if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN) | |
e91e941b | 8848 | return dev_priv->vbt.lvds_ssc_freq; |
da4a1efa VS |
8849 | else if (HAS_PCH_SPLIT(dev)) |
8850 | return 120000; | |
8851 | else if (!IS_GEN2(dev)) | |
8852 | return 96000; | |
8853 | else | |
8854 | return 48000; | |
8855 | } | |
8856 | ||
79e53945 | 8857 | /* Returns the clock of the currently programmed mode of the given pipe. */ |
f1f644dc JB |
8858 | static void i9xx_crtc_clock_get(struct intel_crtc *crtc, |
8859 | struct intel_crtc_config *pipe_config) | |
79e53945 | 8860 | { |
f1f644dc | 8861 | struct drm_device *dev = crtc->base.dev; |
79e53945 | 8862 | struct drm_i915_private *dev_priv = dev->dev_private; |
f1f644dc | 8863 | int pipe = pipe_config->cpu_transcoder; |
293623f7 | 8864 | u32 dpll = pipe_config->dpll_hw_state.dpll; |
79e53945 JB |
8865 | u32 fp; |
8866 | intel_clock_t clock; | |
da4a1efa | 8867 | int refclk = i9xx_pll_refclk(dev, pipe_config); |
79e53945 JB |
8868 | |
8869 | if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) | |
293623f7 | 8870 | fp = pipe_config->dpll_hw_state.fp0; |
79e53945 | 8871 | else |
293623f7 | 8872 | fp = pipe_config->dpll_hw_state.fp1; |
79e53945 JB |
8873 | |
8874 | clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; | |
f2b115e6 AJ |
8875 | if (IS_PINEVIEW(dev)) { |
8876 | clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1; | |
8877 | clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
2177832f SL |
8878 | } else { |
8879 | clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT; | |
8880 | clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT; | |
8881 | } | |
8882 | ||
a6c45cf0 | 8883 | if (!IS_GEN2(dev)) { |
f2b115e6 AJ |
8884 | if (IS_PINEVIEW(dev)) |
8885 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >> | |
8886 | DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW); | |
2177832f SL |
8887 | else |
8888 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >> | |
79e53945 JB |
8889 | DPLL_FPA01_P1_POST_DIV_SHIFT); |
8890 | ||
8891 | switch (dpll & DPLL_MODE_MASK) { | |
8892 | case DPLLB_MODE_DAC_SERIAL: | |
8893 | clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? | |
8894 | 5 : 10; | |
8895 | break; | |
8896 | case DPLLB_MODE_LVDS: | |
8897 | clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? | |
8898 | 7 : 14; | |
8899 | break; | |
8900 | default: | |
28c97730 | 8901 | DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " |
79e53945 | 8902 | "mode\n", (int)(dpll & DPLL_MODE_MASK)); |
f1f644dc | 8903 | return; |
79e53945 JB |
8904 | } |
8905 | ||
ac58c3f0 | 8906 | if (IS_PINEVIEW(dev)) |
da4a1efa | 8907 | pineview_clock(refclk, &clock); |
ac58c3f0 | 8908 | else |
da4a1efa | 8909 | i9xx_clock(refclk, &clock); |
79e53945 | 8910 | } else { |
0fb58223 | 8911 | u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS); |
b1c560d1 | 8912 | bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN); |
79e53945 JB |
8913 | |
8914 | if (is_lvds) { | |
8915 | clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >> | |
8916 | DPLL_FPA01_P1_POST_DIV_SHIFT); | |
b1c560d1 VS |
8917 | |
8918 | if (lvds & LVDS_CLKB_POWER_UP) | |
8919 | clock.p2 = 7; | |
8920 | else | |
8921 | clock.p2 = 14; | |
79e53945 JB |
8922 | } else { |
8923 | if (dpll & PLL_P1_DIVIDE_BY_TWO) | |
8924 | clock.p1 = 2; | |
8925 | else { | |
8926 | clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >> | |
8927 | DPLL_FPA01_P1_POST_DIV_SHIFT) + 2; | |
8928 | } | |
8929 | if (dpll & PLL_P2_DIVIDE_BY_4) | |
8930 | clock.p2 = 4; | |
8931 | else | |
8932 | clock.p2 = 2; | |
79e53945 | 8933 | } |
da4a1efa VS |
8934 | |
8935 | i9xx_clock(refclk, &clock); | |
79e53945 JB |
8936 | } |
8937 | ||
18442d08 VS |
8938 | /* |
8939 | * This value includes pixel_multiplier. We will use | |
241bfc38 | 8940 | * port_clock to compute adjusted_mode.crtc_clock in the |
18442d08 VS |
8941 | * encoder's get_config() function. |
8942 | */ | |
8943 | pipe_config->port_clock = clock.dot; | |
f1f644dc JB |
8944 | } |
8945 | ||
6878da05 VS |
8946 | int intel_dotclock_calculate(int link_freq, |
8947 | const struct intel_link_m_n *m_n) | |
f1f644dc | 8948 | { |
f1f644dc JB |
8949 | /* |
8950 | * The calculation for the data clock is: | |
1041a02f | 8951 | * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp |
f1f644dc | 8952 | * But we want to avoid losing precison if possible, so: |
1041a02f | 8953 | * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp)) |
f1f644dc JB |
8954 | * |
8955 | * and the link clock is simpler: | |
1041a02f | 8956 | * link_clock = (m * link_clock) / n |
f1f644dc JB |
8957 | */ |
8958 | ||
6878da05 VS |
8959 | if (!m_n->link_n) |
8960 | return 0; | |
f1f644dc | 8961 | |
6878da05 VS |
8962 | return div_u64((u64)m_n->link_m * link_freq, m_n->link_n); |
8963 | } | |
f1f644dc | 8964 | |
18442d08 VS |
8965 | static void ironlake_pch_clock_get(struct intel_crtc *crtc, |
8966 | struct intel_crtc_config *pipe_config) | |
6878da05 VS |
8967 | { |
8968 | struct drm_device *dev = crtc->base.dev; | |
79e53945 | 8969 | |
18442d08 VS |
8970 | /* read out port_clock from the DPLL */ |
8971 | i9xx_crtc_clock_get(crtc, pipe_config); | |
f1f644dc | 8972 | |
f1f644dc | 8973 | /* |
18442d08 | 8974 | * This value does not include pixel_multiplier. |
241bfc38 | 8975 | * We will check that port_clock and adjusted_mode.crtc_clock |
18442d08 VS |
8976 | * agree once we know their relationship in the encoder's |
8977 | * get_config() function. | |
79e53945 | 8978 | */ |
241bfc38 | 8979 | pipe_config->adjusted_mode.crtc_clock = |
18442d08 VS |
8980 | intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000, |
8981 | &pipe_config->fdi_m_n); | |
79e53945 JB |
8982 | } |
8983 | ||
8984 | /** Returns the currently programmed mode of the given pipe. */ | |
8985 | struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, | |
8986 | struct drm_crtc *crtc) | |
8987 | { | |
548f245b | 8988 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 8989 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3b117c8f | 8990 | enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder; |
79e53945 | 8991 | struct drm_display_mode *mode; |
f1f644dc | 8992 | struct intel_crtc_config pipe_config; |
fe2b8f9d PZ |
8993 | int htot = I915_READ(HTOTAL(cpu_transcoder)); |
8994 | int hsync = I915_READ(HSYNC(cpu_transcoder)); | |
8995 | int vtot = I915_READ(VTOTAL(cpu_transcoder)); | |
8996 | int vsync = I915_READ(VSYNC(cpu_transcoder)); | |
293623f7 | 8997 | enum pipe pipe = intel_crtc->pipe; |
79e53945 JB |
8998 | |
8999 | mode = kzalloc(sizeof(*mode), GFP_KERNEL); | |
9000 | if (!mode) | |
9001 | return NULL; | |
9002 | ||
f1f644dc JB |
9003 | /* |
9004 | * Construct a pipe_config sufficient for getting the clock info | |
9005 | * back out of crtc_clock_get. | |
9006 | * | |
9007 | * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need | |
9008 | * to use a real value here instead. | |
9009 | */ | |
293623f7 | 9010 | pipe_config.cpu_transcoder = (enum transcoder) pipe; |
f1f644dc | 9011 | pipe_config.pixel_multiplier = 1; |
293623f7 VS |
9012 | pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe)); |
9013 | pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe)); | |
9014 | pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe)); | |
f1f644dc JB |
9015 | i9xx_crtc_clock_get(intel_crtc, &pipe_config); |
9016 | ||
773ae034 | 9017 | mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier; |
79e53945 JB |
9018 | mode->hdisplay = (htot & 0xffff) + 1; |
9019 | mode->htotal = ((htot & 0xffff0000) >> 16) + 1; | |
9020 | mode->hsync_start = (hsync & 0xffff) + 1; | |
9021 | mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1; | |
9022 | mode->vdisplay = (vtot & 0xffff) + 1; | |
9023 | mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1; | |
9024 | mode->vsync_start = (vsync & 0xffff) + 1; | |
9025 | mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1; | |
9026 | ||
9027 | drm_mode_set_name(mode); | |
79e53945 JB |
9028 | |
9029 | return mode; | |
9030 | } | |
9031 | ||
cc36513c DV |
9032 | static void intel_increase_pllclock(struct drm_device *dev, |
9033 | enum pipe pipe) | |
652c393a | 9034 | { |
fbee40df | 9035 | struct drm_i915_private *dev_priv = dev->dev_private; |
dbdc6479 JB |
9036 | int dpll_reg = DPLL(pipe); |
9037 | int dpll; | |
652c393a | 9038 | |
baff296c | 9039 | if (!HAS_GMCH_DISPLAY(dev)) |
652c393a JB |
9040 | return; |
9041 | ||
9042 | if (!dev_priv->lvds_downclock_avail) | |
9043 | return; | |
9044 | ||
dbdc6479 | 9045 | dpll = I915_READ(dpll_reg); |
652c393a | 9046 | if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) { |
44d98a61 | 9047 | DRM_DEBUG_DRIVER("upclocking LVDS\n"); |
652c393a | 9048 | |
8ac5a6d5 | 9049 | assert_panel_unlocked(dev_priv, pipe); |
652c393a JB |
9050 | |
9051 | dpll &= ~DISPLAY_RATE_SELECT_FPA1; | |
9052 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 9053 | intel_wait_for_vblank(dev, pipe); |
dbdc6479 | 9054 | |
652c393a JB |
9055 | dpll = I915_READ(dpll_reg); |
9056 | if (dpll & DISPLAY_RATE_SELECT_FPA1) | |
44d98a61 | 9057 | DRM_DEBUG_DRIVER("failed to upclock LVDS!\n"); |
652c393a | 9058 | } |
652c393a JB |
9059 | } |
9060 | ||
9061 | static void intel_decrease_pllclock(struct drm_crtc *crtc) | |
9062 | { | |
9063 | struct drm_device *dev = crtc->dev; | |
fbee40df | 9064 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 9065 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
652c393a | 9066 | |
baff296c | 9067 | if (!HAS_GMCH_DISPLAY(dev)) |
652c393a JB |
9068 | return; |
9069 | ||
9070 | if (!dev_priv->lvds_downclock_avail) | |
9071 | return; | |
9072 | ||
9073 | /* | |
9074 | * Since this is called by a timer, we should never get here in | |
9075 | * the manual case. | |
9076 | */ | |
9077 | if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) { | |
dc257cf1 DV |
9078 | int pipe = intel_crtc->pipe; |
9079 | int dpll_reg = DPLL(pipe); | |
9080 | int dpll; | |
f6e5b160 | 9081 | |
44d98a61 | 9082 | DRM_DEBUG_DRIVER("downclocking LVDS\n"); |
652c393a | 9083 | |
8ac5a6d5 | 9084 | assert_panel_unlocked(dev_priv, pipe); |
652c393a | 9085 | |
dc257cf1 | 9086 | dpll = I915_READ(dpll_reg); |
652c393a JB |
9087 | dpll |= DISPLAY_RATE_SELECT_FPA1; |
9088 | I915_WRITE(dpll_reg, dpll); | |
9d0498a2 | 9089 | intel_wait_for_vblank(dev, pipe); |
652c393a JB |
9090 | dpll = I915_READ(dpll_reg); |
9091 | if (!(dpll & DISPLAY_RATE_SELECT_FPA1)) | |
44d98a61 | 9092 | DRM_DEBUG_DRIVER("failed to downclock LVDS!\n"); |
652c393a JB |
9093 | } |
9094 | ||
9095 | } | |
9096 | ||
f047e395 CW |
9097 | void intel_mark_busy(struct drm_device *dev) |
9098 | { | |
c67a470b PZ |
9099 | struct drm_i915_private *dev_priv = dev->dev_private; |
9100 | ||
f62a0076 CW |
9101 | if (dev_priv->mm.busy) |
9102 | return; | |
9103 | ||
43694d69 | 9104 | intel_runtime_pm_get(dev_priv); |
c67a470b | 9105 | i915_update_gfx_val(dev_priv); |
f62a0076 | 9106 | dev_priv->mm.busy = true; |
f047e395 CW |
9107 | } |
9108 | ||
9109 | void intel_mark_idle(struct drm_device *dev) | |
652c393a | 9110 | { |
c67a470b | 9111 | struct drm_i915_private *dev_priv = dev->dev_private; |
652c393a | 9112 | struct drm_crtc *crtc; |
652c393a | 9113 | |
f62a0076 CW |
9114 | if (!dev_priv->mm.busy) |
9115 | return; | |
9116 | ||
9117 | dev_priv->mm.busy = false; | |
9118 | ||
d330a953 | 9119 | if (!i915.powersave) |
bb4cdd53 | 9120 | goto out; |
652c393a | 9121 | |
70e1e0ec | 9122 | for_each_crtc(dev, crtc) { |
f4510a27 | 9123 | if (!crtc->primary->fb) |
652c393a JB |
9124 | continue; |
9125 | ||
725a5b54 | 9126 | intel_decrease_pllclock(crtc); |
652c393a | 9127 | } |
b29c19b6 | 9128 | |
3d13ef2e | 9129 | if (INTEL_INFO(dev)->gen >= 6) |
b29c19b6 | 9130 | gen6_rps_idle(dev->dev_private); |
bb4cdd53 PZ |
9131 | |
9132 | out: | |
43694d69 | 9133 | intel_runtime_pm_put(dev_priv); |
652c393a JB |
9134 | } |
9135 | ||
7c8f8a70 | 9136 | |
f99d7069 DV |
9137 | /** |
9138 | * intel_mark_fb_busy - mark given planes as busy | |
9139 | * @dev: DRM device | |
9140 | * @frontbuffer_bits: bits for the affected planes | |
9141 | * @ring: optional ring for asynchronous commands | |
9142 | * | |
9143 | * This function gets called every time the screen contents change. It can be | |
9144 | * used to keep e.g. the update rate at the nominal refresh rate with DRRS. | |
9145 | */ | |
9146 | static void intel_mark_fb_busy(struct drm_device *dev, | |
9147 | unsigned frontbuffer_bits, | |
9148 | struct intel_engine_cs *ring) | |
652c393a | 9149 | { |
055e393f | 9150 | struct drm_i915_private *dev_priv = dev->dev_private; |
cc36513c | 9151 | enum pipe pipe; |
652c393a | 9152 | |
d330a953 | 9153 | if (!i915.powersave) |
acb87dfb CW |
9154 | return; |
9155 | ||
055e393f | 9156 | for_each_pipe(dev_priv, pipe) { |
f99d7069 | 9157 | if (!(frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe))) |
c65355bb CW |
9158 | continue; |
9159 | ||
cc36513c | 9160 | intel_increase_pllclock(dev, pipe); |
c65355bb CW |
9161 | if (ring && intel_fbc_enabled(dev)) |
9162 | ring->fbc_dirty = true; | |
652c393a JB |
9163 | } |
9164 | } | |
9165 | ||
f99d7069 DV |
9166 | /** |
9167 | * intel_fb_obj_invalidate - invalidate frontbuffer object | |
9168 | * @obj: GEM object to invalidate | |
9169 | * @ring: set for asynchronous rendering | |
9170 | * | |
9171 | * This function gets called every time rendering on the given object starts and | |
9172 | * frontbuffer caching (fbc, low refresh rate for DRRS, panel self refresh) must | |
9173 | * be invalidated. If @ring is non-NULL any subsequent invalidation will be delayed | |
9174 | * until the rendering completes or a flip on this frontbuffer plane is | |
9175 | * scheduled. | |
9176 | */ | |
9177 | void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, | |
9178 | struct intel_engine_cs *ring) | |
9179 | { | |
9180 | struct drm_device *dev = obj->base.dev; | |
9181 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9182 | ||
9183 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
9184 | ||
9185 | if (!obj->frontbuffer_bits) | |
9186 | return; | |
9187 | ||
9188 | if (ring) { | |
9189 | mutex_lock(&dev_priv->fb_tracking.lock); | |
9190 | dev_priv->fb_tracking.busy_bits | |
9191 | |= obj->frontbuffer_bits; | |
9192 | dev_priv->fb_tracking.flip_bits | |
9193 | &= ~obj->frontbuffer_bits; | |
9194 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
9195 | } | |
9196 | ||
9197 | intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring); | |
9198 | ||
9ca15301 | 9199 | intel_edp_psr_invalidate(dev, obj->frontbuffer_bits); |
f99d7069 DV |
9200 | } |
9201 | ||
9202 | /** | |
9203 | * intel_frontbuffer_flush - flush frontbuffer | |
9204 | * @dev: DRM device | |
9205 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
9206 | * | |
9207 | * This function gets called every time rendering on the given planes has | |
9208 | * completed and frontbuffer caching can be started again. Flushes will get | |
9209 | * delayed if they're blocked by some oustanding asynchronous rendering. | |
9210 | * | |
9211 | * Can be called without any locks held. | |
9212 | */ | |
9213 | void intel_frontbuffer_flush(struct drm_device *dev, | |
9214 | unsigned frontbuffer_bits) | |
9215 | { | |
9216 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9217 | ||
9218 | /* Delay flushing when rings are still busy.*/ | |
9219 | mutex_lock(&dev_priv->fb_tracking.lock); | |
9220 | frontbuffer_bits &= ~dev_priv->fb_tracking.busy_bits; | |
9221 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
9222 | ||
9223 | intel_mark_fb_busy(dev, frontbuffer_bits, NULL); | |
9224 | ||
9ca15301 | 9225 | intel_edp_psr_flush(dev, frontbuffer_bits); |
c5ad011d | 9226 | |
c317adcd VS |
9227 | /* |
9228 | * FIXME: Unconditional fbc flushing here is a rather gross hack and | |
9229 | * needs to be reworked into a proper frontbuffer tracking scheme like | |
9230 | * psr employs. | |
9231 | */ | |
9232 | if (IS_BROADWELL(dev)) | |
c5ad011d | 9233 | gen8_fbc_sw_flush(dev, FBC_REND_CACHE_CLEAN); |
f99d7069 DV |
9234 | } |
9235 | ||
9236 | /** | |
9237 | * intel_fb_obj_flush - flush frontbuffer object | |
9238 | * @obj: GEM object to flush | |
9239 | * @retire: set when retiring asynchronous rendering | |
9240 | * | |
9241 | * This function gets called every time rendering on the given object has | |
9242 | * completed and frontbuffer caching can be started again. If @retire is true | |
9243 | * then any delayed flushes will be unblocked. | |
9244 | */ | |
9245 | void intel_fb_obj_flush(struct drm_i915_gem_object *obj, | |
9246 | bool retire) | |
9247 | { | |
9248 | struct drm_device *dev = obj->base.dev; | |
9249 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9250 | unsigned frontbuffer_bits; | |
9251 | ||
9252 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
9253 | ||
9254 | if (!obj->frontbuffer_bits) | |
9255 | return; | |
9256 | ||
9257 | frontbuffer_bits = obj->frontbuffer_bits; | |
9258 | ||
9259 | if (retire) { | |
9260 | mutex_lock(&dev_priv->fb_tracking.lock); | |
9261 | /* Filter out new bits since rendering started. */ | |
9262 | frontbuffer_bits &= dev_priv->fb_tracking.busy_bits; | |
9263 | ||
9264 | dev_priv->fb_tracking.busy_bits &= ~frontbuffer_bits; | |
9265 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
9266 | } | |
9267 | ||
9268 | intel_frontbuffer_flush(dev, frontbuffer_bits); | |
9269 | } | |
9270 | ||
9271 | /** | |
9272 | * intel_frontbuffer_flip_prepare - prepare asnychronous frontbuffer flip | |
9273 | * @dev: DRM device | |
9274 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
9275 | * | |
9276 | * This function gets called after scheduling a flip on @obj. The actual | |
9277 | * frontbuffer flushing will be delayed until completion is signalled with | |
9278 | * intel_frontbuffer_flip_complete. If an invalidate happens in between this | |
9279 | * flush will be cancelled. | |
9280 | * | |
9281 | * Can be called without any locks held. | |
9282 | */ | |
9283 | void intel_frontbuffer_flip_prepare(struct drm_device *dev, | |
9284 | unsigned frontbuffer_bits) | |
9285 | { | |
9286 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9287 | ||
9288 | mutex_lock(&dev_priv->fb_tracking.lock); | |
9289 | dev_priv->fb_tracking.flip_bits | |
9290 | |= frontbuffer_bits; | |
9291 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
9292 | } | |
9293 | ||
9294 | /** | |
9295 | * intel_frontbuffer_flip_complete - complete asynchronous frontbuffer flush | |
9296 | * @dev: DRM device | |
9297 | * @frontbuffer_bits: frontbuffer plane tracking bits | |
9298 | * | |
9299 | * This function gets called after the flip has been latched and will complete | |
9300 | * on the next vblank. It will execute the fush if it hasn't been cancalled yet. | |
9301 | * | |
9302 | * Can be called without any locks held. | |
9303 | */ | |
9304 | void intel_frontbuffer_flip_complete(struct drm_device *dev, | |
9305 | unsigned frontbuffer_bits) | |
9306 | { | |
9307 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9308 | ||
9309 | mutex_lock(&dev_priv->fb_tracking.lock); | |
9310 | /* Mask any cancelled flips. */ | |
9311 | frontbuffer_bits &= dev_priv->fb_tracking.flip_bits; | |
9312 | dev_priv->fb_tracking.flip_bits &= ~frontbuffer_bits; | |
9313 | mutex_unlock(&dev_priv->fb_tracking.lock); | |
9314 | ||
9315 | intel_frontbuffer_flush(dev, frontbuffer_bits); | |
9316 | } | |
9317 | ||
79e53945 JB |
9318 | static void intel_crtc_destroy(struct drm_crtc *crtc) |
9319 | { | |
9320 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
67e77c5a DV |
9321 | struct drm_device *dev = crtc->dev; |
9322 | struct intel_unpin_work *work; | |
9323 | unsigned long flags; | |
9324 | ||
9325 | spin_lock_irqsave(&dev->event_lock, flags); | |
9326 | work = intel_crtc->unpin_work; | |
9327 | intel_crtc->unpin_work = NULL; | |
9328 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9329 | ||
9330 | if (work) { | |
9331 | cancel_work_sync(&work->work); | |
9332 | kfree(work); | |
9333 | } | |
79e53945 JB |
9334 | |
9335 | drm_crtc_cleanup(crtc); | |
67e77c5a | 9336 | |
79e53945 JB |
9337 | kfree(intel_crtc); |
9338 | } | |
9339 | ||
6b95a207 KH |
9340 | static void intel_unpin_work_fn(struct work_struct *__work) |
9341 | { | |
9342 | struct intel_unpin_work *work = | |
9343 | container_of(__work, struct intel_unpin_work, work); | |
b4a98e57 | 9344 | struct drm_device *dev = work->crtc->dev; |
f99d7069 | 9345 | enum pipe pipe = to_intel_crtc(work->crtc)->pipe; |
6b95a207 | 9346 | |
b4a98e57 | 9347 | mutex_lock(&dev->struct_mutex); |
1690e1eb | 9348 | intel_unpin_fb_obj(work->old_fb_obj); |
05394f39 CW |
9349 | drm_gem_object_unreference(&work->pending_flip_obj->base); |
9350 | drm_gem_object_unreference(&work->old_fb_obj->base); | |
d9e86c0e | 9351 | |
b4a98e57 CW |
9352 | intel_update_fbc(dev); |
9353 | mutex_unlock(&dev->struct_mutex); | |
9354 | ||
f99d7069 DV |
9355 | intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
9356 | ||
b4a98e57 CW |
9357 | BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0); |
9358 | atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count); | |
9359 | ||
6b95a207 KH |
9360 | kfree(work); |
9361 | } | |
9362 | ||
1afe3e9d | 9363 | static void do_intel_finish_page_flip(struct drm_device *dev, |
49b14a5c | 9364 | struct drm_crtc *crtc) |
6b95a207 | 9365 | { |
6b95a207 KH |
9366 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
9367 | struct intel_unpin_work *work; | |
6b95a207 KH |
9368 | unsigned long flags; |
9369 | ||
9370 | /* Ignore early vblank irqs */ | |
9371 | if (intel_crtc == NULL) | |
9372 | return; | |
9373 | ||
9374 | spin_lock_irqsave(&dev->event_lock, flags); | |
9375 | work = intel_crtc->unpin_work; | |
e7d841ca CW |
9376 | |
9377 | /* Ensure we don't miss a work->pending update ... */ | |
9378 | smp_rmb(); | |
9379 | ||
9380 | if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) { | |
6b95a207 KH |
9381 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9382 | return; | |
9383 | } | |
9384 | ||
d6bbafa1 | 9385 | page_flip_completed(intel_crtc); |
0af7e4df | 9386 | |
6b95a207 | 9387 | spin_unlock_irqrestore(&dev->event_lock, flags); |
6b95a207 KH |
9388 | } |
9389 | ||
1afe3e9d JB |
9390 | void intel_finish_page_flip(struct drm_device *dev, int pipe) |
9391 | { | |
fbee40df | 9392 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9393 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; |
9394 | ||
49b14a5c | 9395 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9396 | } |
9397 | ||
9398 | void intel_finish_page_flip_plane(struct drm_device *dev, int plane) | |
9399 | { | |
fbee40df | 9400 | struct drm_i915_private *dev_priv = dev->dev_private; |
1afe3e9d JB |
9401 | struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane]; |
9402 | ||
49b14a5c | 9403 | do_intel_finish_page_flip(dev, crtc); |
1afe3e9d JB |
9404 | } |
9405 | ||
75f7f3ec VS |
9406 | /* Is 'a' after or equal to 'b'? */ |
9407 | static bool g4x_flip_count_after_eq(u32 a, u32 b) | |
9408 | { | |
9409 | return !((a - b) & 0x80000000); | |
9410 | } | |
9411 | ||
9412 | static bool page_flip_finished(struct intel_crtc *crtc) | |
9413 | { | |
9414 | struct drm_device *dev = crtc->base.dev; | |
9415 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9416 | ||
9417 | /* | |
9418 | * The relevant registers doen't exist on pre-ctg. | |
9419 | * As the flip done interrupt doesn't trigger for mmio | |
9420 | * flips on gmch platforms, a flip count check isn't | |
9421 | * really needed there. But since ctg has the registers, | |
9422 | * include it in the check anyway. | |
9423 | */ | |
9424 | if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev)) | |
9425 | return true; | |
9426 | ||
9427 | /* | |
9428 | * A DSPSURFLIVE check isn't enough in case the mmio and CS flips | |
9429 | * used the same base address. In that case the mmio flip might | |
9430 | * have completed, but the CS hasn't even executed the flip yet. | |
9431 | * | |
9432 | * A flip count check isn't enough as the CS might have updated | |
9433 | * the base address just after start of vblank, but before we | |
9434 | * managed to process the interrupt. This means we'd complete the | |
9435 | * CS flip too soon. | |
9436 | * | |
9437 | * Combining both checks should get us a good enough result. It may | |
9438 | * still happen that the CS flip has been executed, but has not | |
9439 | * yet actually completed. But in case the base address is the same | |
9440 | * anyway, we don't really care. | |
9441 | */ | |
9442 | return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) == | |
9443 | crtc->unpin_work->gtt_offset && | |
9444 | g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)), | |
9445 | crtc->unpin_work->flip_count); | |
9446 | } | |
9447 | ||
6b95a207 KH |
9448 | void intel_prepare_page_flip(struct drm_device *dev, int plane) |
9449 | { | |
fbee40df | 9450 | struct drm_i915_private *dev_priv = dev->dev_private; |
6b95a207 KH |
9451 | struct intel_crtc *intel_crtc = |
9452 | to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]); | |
9453 | unsigned long flags; | |
9454 | ||
e7d841ca CW |
9455 | /* NB: An MMIO update of the plane base pointer will also |
9456 | * generate a page-flip completion irq, i.e. every modeset | |
9457 | * is also accompanied by a spurious intel_prepare_page_flip(). | |
9458 | */ | |
6b95a207 | 9459 | spin_lock_irqsave(&dev->event_lock, flags); |
75f7f3ec | 9460 | if (intel_crtc->unpin_work && page_flip_finished(intel_crtc)) |
e7d841ca | 9461 | atomic_inc_not_zero(&intel_crtc->unpin_work->pending); |
6b95a207 KH |
9462 | spin_unlock_irqrestore(&dev->event_lock, flags); |
9463 | } | |
9464 | ||
eba905b2 | 9465 | static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc) |
e7d841ca CW |
9466 | { |
9467 | /* Ensure that the work item is consistent when activating it ... */ | |
9468 | smp_wmb(); | |
9469 | atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING); | |
9470 | /* and that it is marked active as soon as the irq could fire. */ | |
9471 | smp_wmb(); | |
9472 | } | |
9473 | ||
8c9f3aaf JB |
9474 | static int intel_gen2_queue_flip(struct drm_device *dev, |
9475 | struct drm_crtc *crtc, | |
9476 | struct drm_framebuffer *fb, | |
ed8d1975 | 9477 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9478 | struct intel_engine_cs *ring, |
ed8d1975 | 9479 | uint32_t flags) |
8c9f3aaf | 9480 | { |
8c9f3aaf | 9481 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9482 | u32 flip_mask; |
9483 | int ret; | |
9484 | ||
6d90c952 | 9485 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9486 | if (ret) |
4fa62c89 | 9487 | return ret; |
8c9f3aaf JB |
9488 | |
9489 | /* Can't queue multiple flips, so wait for the previous | |
9490 | * one to finish before executing the next. | |
9491 | */ | |
9492 | if (intel_crtc->plane) | |
9493 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9494 | else | |
9495 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9496 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9497 | intel_ring_emit(ring, MI_NOOP); | |
9498 | intel_ring_emit(ring, MI_DISPLAY_FLIP | | |
9499 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9500 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9501 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 | 9502 | intel_ring_emit(ring, 0); /* aux display base address, unused */ |
e7d841ca CW |
9503 | |
9504 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9505 | __intel_ring_advance(ring); |
83d4092b | 9506 | return 0; |
8c9f3aaf JB |
9507 | } |
9508 | ||
9509 | static int intel_gen3_queue_flip(struct drm_device *dev, | |
9510 | struct drm_crtc *crtc, | |
9511 | struct drm_framebuffer *fb, | |
ed8d1975 | 9512 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9513 | struct intel_engine_cs *ring, |
ed8d1975 | 9514 | uint32_t flags) |
8c9f3aaf | 9515 | { |
8c9f3aaf | 9516 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
8c9f3aaf JB |
9517 | u32 flip_mask; |
9518 | int ret; | |
9519 | ||
6d90c952 | 9520 | ret = intel_ring_begin(ring, 6); |
8c9f3aaf | 9521 | if (ret) |
4fa62c89 | 9522 | return ret; |
8c9f3aaf JB |
9523 | |
9524 | if (intel_crtc->plane) | |
9525 | flip_mask = MI_WAIT_FOR_PLANE_B_FLIP; | |
9526 | else | |
9527 | flip_mask = MI_WAIT_FOR_PLANE_A_FLIP; | |
6d90c952 DV |
9528 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask); |
9529 | intel_ring_emit(ring, MI_NOOP); | |
9530 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | | |
9531 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9532 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9533 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
6d90c952 DV |
9534 | intel_ring_emit(ring, MI_NOOP); |
9535 | ||
e7d841ca | 9536 | intel_mark_page_flip_active(intel_crtc); |
09246732 | 9537 | __intel_ring_advance(ring); |
83d4092b | 9538 | return 0; |
8c9f3aaf JB |
9539 | } |
9540 | ||
9541 | static int intel_gen4_queue_flip(struct drm_device *dev, | |
9542 | struct drm_crtc *crtc, | |
9543 | struct drm_framebuffer *fb, | |
ed8d1975 | 9544 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9545 | struct intel_engine_cs *ring, |
ed8d1975 | 9546 | uint32_t flags) |
8c9f3aaf JB |
9547 | { |
9548 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9549 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9550 | uint32_t pf, pipesrc; | |
9551 | int ret; | |
9552 | ||
6d90c952 | 9553 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9554 | if (ret) |
4fa62c89 | 9555 | return ret; |
8c9f3aaf JB |
9556 | |
9557 | /* i965+ uses the linear or tiled offsets from the | |
9558 | * Display Registers (which do not change across a page-flip) | |
9559 | * so we need only reprogram the base address. | |
9560 | */ | |
6d90c952 DV |
9561 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9562 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9563 | intel_ring_emit(ring, fb->pitches[0]); | |
75f7f3ec | 9564 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset | |
c2c75131 | 9565 | obj->tiling_mode); |
8c9f3aaf JB |
9566 | |
9567 | /* XXX Enabling the panel-fitter across page-flip is so far | |
9568 | * untested on non-native modes, so ignore it for now. | |
9569 | * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE; | |
9570 | */ | |
9571 | pf = 0; | |
9572 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; | |
6d90c952 | 9573 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9574 | |
9575 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9576 | __intel_ring_advance(ring); |
83d4092b | 9577 | return 0; |
8c9f3aaf JB |
9578 | } |
9579 | ||
9580 | static int intel_gen6_queue_flip(struct drm_device *dev, | |
9581 | struct drm_crtc *crtc, | |
9582 | struct drm_framebuffer *fb, | |
ed8d1975 | 9583 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9584 | struct intel_engine_cs *ring, |
ed8d1975 | 9585 | uint32_t flags) |
8c9f3aaf JB |
9586 | { |
9587 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9588 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9589 | uint32_t pf, pipesrc; | |
9590 | int ret; | |
9591 | ||
6d90c952 | 9592 | ret = intel_ring_begin(ring, 4); |
8c9f3aaf | 9593 | if (ret) |
4fa62c89 | 9594 | return ret; |
8c9f3aaf | 9595 | |
6d90c952 DV |
9596 | intel_ring_emit(ring, MI_DISPLAY_FLIP | |
9597 | MI_DISPLAY_FLIP_PLANE(intel_crtc->plane)); | |
9598 | intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode); | |
75f7f3ec | 9599 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
8c9f3aaf | 9600 | |
dc257cf1 DV |
9601 | /* Contrary to the suggestions in the documentation, |
9602 | * "Enable Panel Fitter" does not seem to be required when page | |
9603 | * flipping with a non-native mode, and worse causes a normal | |
9604 | * modeset to fail. | |
9605 | * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE; | |
9606 | */ | |
9607 | pf = 0; | |
8c9f3aaf | 9608 | pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff; |
6d90c952 | 9609 | intel_ring_emit(ring, pf | pipesrc); |
e7d841ca CW |
9610 | |
9611 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9612 | __intel_ring_advance(ring); |
83d4092b | 9613 | return 0; |
8c9f3aaf JB |
9614 | } |
9615 | ||
7c9017e5 JB |
9616 | static int intel_gen7_queue_flip(struct drm_device *dev, |
9617 | struct drm_crtc *crtc, | |
9618 | struct drm_framebuffer *fb, | |
ed8d1975 | 9619 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9620 | struct intel_engine_cs *ring, |
ed8d1975 | 9621 | uint32_t flags) |
7c9017e5 | 9622 | { |
7c9017e5 | 9623 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
cb05d8de | 9624 | uint32_t plane_bit = 0; |
ffe74d75 CW |
9625 | int len, ret; |
9626 | ||
eba905b2 | 9627 | switch (intel_crtc->plane) { |
cb05d8de DV |
9628 | case PLANE_A: |
9629 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A; | |
9630 | break; | |
9631 | case PLANE_B: | |
9632 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B; | |
9633 | break; | |
9634 | case PLANE_C: | |
9635 | plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C; | |
9636 | break; | |
9637 | default: | |
9638 | WARN_ONCE(1, "unknown plane in flip command\n"); | |
4fa62c89 | 9639 | return -ENODEV; |
cb05d8de DV |
9640 | } |
9641 | ||
ffe74d75 | 9642 | len = 4; |
f476828a | 9643 | if (ring->id == RCS) { |
ffe74d75 | 9644 | len += 6; |
f476828a DL |
9645 | /* |
9646 | * On Gen 8, SRM is now taking an extra dword to accommodate | |
9647 | * 48bits addresses, and we need a NOOP for the batch size to | |
9648 | * stay even. | |
9649 | */ | |
9650 | if (IS_GEN8(dev)) | |
9651 | len += 2; | |
9652 | } | |
ffe74d75 | 9653 | |
f66fab8e VS |
9654 | /* |
9655 | * BSpec MI_DISPLAY_FLIP for IVB: | |
9656 | * "The full packet must be contained within the same cache line." | |
9657 | * | |
9658 | * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same | |
9659 | * cacheline, if we ever start emitting more commands before | |
9660 | * the MI_DISPLAY_FLIP we may need to first emit everything else, | |
9661 | * then do the cacheline alignment, and finally emit the | |
9662 | * MI_DISPLAY_FLIP. | |
9663 | */ | |
9664 | ret = intel_ring_cacheline_align(ring); | |
9665 | if (ret) | |
4fa62c89 | 9666 | return ret; |
f66fab8e | 9667 | |
ffe74d75 | 9668 | ret = intel_ring_begin(ring, len); |
7c9017e5 | 9669 | if (ret) |
4fa62c89 | 9670 | return ret; |
7c9017e5 | 9671 | |
ffe74d75 CW |
9672 | /* Unmask the flip-done completion message. Note that the bspec says that |
9673 | * we should do this for both the BCS and RCS, and that we must not unmask | |
9674 | * more than one flip event at any time (or ensure that one flip message | |
9675 | * can be sent by waiting for flip-done prior to queueing new flips). | |
9676 | * Experimentation says that BCS works despite DERRMR masking all | |
9677 | * flip-done completion events and that unmasking all planes at once | |
9678 | * for the RCS also doesn't appear to drop events. Setting the DERRMR | |
9679 | * to zero does lead to lockups within MI_DISPLAY_FLIP. | |
9680 | */ | |
9681 | if (ring->id == RCS) { | |
9682 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); | |
9683 | intel_ring_emit(ring, DERRMR); | |
9684 | intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE | | |
9685 | DERRMR_PIPEB_PRI_FLIP_DONE | | |
9686 | DERRMR_PIPEC_PRI_FLIP_DONE)); | |
f476828a DL |
9687 | if (IS_GEN8(dev)) |
9688 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) | | |
9689 | MI_SRM_LRM_GLOBAL_GTT); | |
9690 | else | |
9691 | intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) | | |
9692 | MI_SRM_LRM_GLOBAL_GTT); | |
ffe74d75 CW |
9693 | intel_ring_emit(ring, DERRMR); |
9694 | intel_ring_emit(ring, ring->scratch.gtt_offset + 256); | |
f476828a DL |
9695 | if (IS_GEN8(dev)) { |
9696 | intel_ring_emit(ring, 0); | |
9697 | intel_ring_emit(ring, MI_NOOP); | |
9698 | } | |
ffe74d75 CW |
9699 | } |
9700 | ||
cb05d8de | 9701 | intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit); |
01f2c773 | 9702 | intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode)); |
75f7f3ec | 9703 | intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset); |
7c9017e5 | 9704 | intel_ring_emit(ring, (MI_NOOP)); |
e7d841ca CW |
9705 | |
9706 | intel_mark_page_flip_active(intel_crtc); | |
09246732 | 9707 | __intel_ring_advance(ring); |
83d4092b | 9708 | return 0; |
7c9017e5 JB |
9709 | } |
9710 | ||
84c33a64 SG |
9711 | static bool use_mmio_flip(struct intel_engine_cs *ring, |
9712 | struct drm_i915_gem_object *obj) | |
9713 | { | |
9714 | /* | |
9715 | * This is not being used for older platforms, because | |
9716 | * non-availability of flip done interrupt forces us to use | |
9717 | * CS flips. Older platforms derive flip done using some clever | |
9718 | * tricks involving the flip_pending status bits and vblank irqs. | |
9719 | * So using MMIO flips there would disrupt this mechanism. | |
9720 | */ | |
9721 | ||
8e09bf83 CW |
9722 | if (ring == NULL) |
9723 | return true; | |
9724 | ||
84c33a64 SG |
9725 | if (INTEL_INFO(ring->dev)->gen < 5) |
9726 | return false; | |
9727 | ||
9728 | if (i915.use_mmio_flip < 0) | |
9729 | return false; | |
9730 | else if (i915.use_mmio_flip > 0) | |
9731 | return true; | |
14bf993e OM |
9732 | else if (i915.enable_execlists) |
9733 | return true; | |
84c33a64 SG |
9734 | else |
9735 | return ring != obj->ring; | |
9736 | } | |
9737 | ||
9738 | static void intel_do_mmio_flip(struct intel_crtc *intel_crtc) | |
9739 | { | |
9740 | struct drm_device *dev = intel_crtc->base.dev; | |
9741 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9742 | struct intel_framebuffer *intel_fb = | |
9743 | to_intel_framebuffer(intel_crtc->base.primary->fb); | |
9744 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
9745 | u32 dspcntr; | |
9746 | u32 reg; | |
9747 | ||
9748 | intel_mark_page_flip_active(intel_crtc); | |
9749 | ||
9750 | reg = DSPCNTR(intel_crtc->plane); | |
9751 | dspcntr = I915_READ(reg); | |
9752 | ||
9753 | if (INTEL_INFO(dev)->gen >= 4) { | |
9754 | if (obj->tiling_mode != I915_TILING_NONE) | |
9755 | dspcntr |= DISPPLANE_TILED; | |
9756 | else | |
9757 | dspcntr &= ~DISPPLANE_TILED; | |
9758 | } | |
9759 | I915_WRITE(reg, dspcntr); | |
9760 | ||
9761 | I915_WRITE(DSPSURF(intel_crtc->plane), | |
9762 | intel_crtc->unpin_work->gtt_offset); | |
9763 | POSTING_READ(DSPSURF(intel_crtc->plane)); | |
9764 | } | |
9765 | ||
9766 | static int intel_postpone_flip(struct drm_i915_gem_object *obj) | |
9767 | { | |
9768 | struct intel_engine_cs *ring; | |
9769 | int ret; | |
9770 | ||
9771 | lockdep_assert_held(&obj->base.dev->struct_mutex); | |
9772 | ||
9773 | if (!obj->last_write_seqno) | |
9774 | return 0; | |
9775 | ||
9776 | ring = obj->ring; | |
9777 | ||
9778 | if (i915_seqno_passed(ring->get_seqno(ring, true), | |
9779 | obj->last_write_seqno)) | |
9780 | return 0; | |
9781 | ||
9782 | ret = i915_gem_check_olr(ring, obj->last_write_seqno); | |
9783 | if (ret) | |
9784 | return ret; | |
9785 | ||
9786 | if (WARN_ON(!ring->irq_get(ring))) | |
9787 | return 0; | |
9788 | ||
9789 | return 1; | |
9790 | } | |
9791 | ||
9792 | void intel_notify_mmio_flip(struct intel_engine_cs *ring) | |
9793 | { | |
9794 | struct drm_i915_private *dev_priv = to_i915(ring->dev); | |
9795 | struct intel_crtc *intel_crtc; | |
9796 | unsigned long irq_flags; | |
9797 | u32 seqno; | |
9798 | ||
9799 | seqno = ring->get_seqno(ring, false); | |
9800 | ||
9801 | spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags); | |
9802 | for_each_intel_crtc(ring->dev, intel_crtc) { | |
9803 | struct intel_mmio_flip *mmio_flip; | |
9804 | ||
9805 | mmio_flip = &intel_crtc->mmio_flip; | |
9806 | if (mmio_flip->seqno == 0) | |
9807 | continue; | |
9808 | ||
9809 | if (ring->id != mmio_flip->ring_id) | |
9810 | continue; | |
9811 | ||
9812 | if (i915_seqno_passed(seqno, mmio_flip->seqno)) { | |
9813 | intel_do_mmio_flip(intel_crtc); | |
9814 | mmio_flip->seqno = 0; | |
9815 | ring->irq_put(ring); | |
9816 | } | |
9817 | } | |
9818 | spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags); | |
9819 | } | |
9820 | ||
9821 | static int intel_queue_mmio_flip(struct drm_device *dev, | |
9822 | struct drm_crtc *crtc, | |
9823 | struct drm_framebuffer *fb, | |
9824 | struct drm_i915_gem_object *obj, | |
9825 | struct intel_engine_cs *ring, | |
9826 | uint32_t flags) | |
9827 | { | |
9828 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9829 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9830 | unsigned long irq_flags; | |
9831 | int ret; | |
9832 | ||
9833 | if (WARN_ON(intel_crtc->mmio_flip.seqno)) | |
9834 | return -EBUSY; | |
9835 | ||
9836 | ret = intel_postpone_flip(obj); | |
9837 | if (ret < 0) | |
9838 | return ret; | |
9839 | if (ret == 0) { | |
9840 | intel_do_mmio_flip(intel_crtc); | |
9841 | return 0; | |
9842 | } | |
9843 | ||
9844 | spin_lock_irqsave(&dev_priv->mmio_flip_lock, irq_flags); | |
9845 | intel_crtc->mmio_flip.seqno = obj->last_write_seqno; | |
9846 | intel_crtc->mmio_flip.ring_id = obj->ring->id; | |
9847 | spin_unlock_irqrestore(&dev_priv->mmio_flip_lock, irq_flags); | |
9848 | ||
9849 | /* | |
9850 | * Double check to catch cases where irq fired before | |
9851 | * mmio flip data was ready | |
9852 | */ | |
9853 | intel_notify_mmio_flip(obj->ring); | |
9854 | return 0; | |
9855 | } | |
9856 | ||
8c9f3aaf JB |
9857 | static int intel_default_queue_flip(struct drm_device *dev, |
9858 | struct drm_crtc *crtc, | |
9859 | struct drm_framebuffer *fb, | |
ed8d1975 | 9860 | struct drm_i915_gem_object *obj, |
a4872ba6 | 9861 | struct intel_engine_cs *ring, |
ed8d1975 | 9862 | uint32_t flags) |
8c9f3aaf JB |
9863 | { |
9864 | return -ENODEV; | |
9865 | } | |
9866 | ||
d6bbafa1 CW |
9867 | static bool __intel_pageflip_stall_check(struct drm_device *dev, |
9868 | struct drm_crtc *crtc) | |
9869 | { | |
9870 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9871 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9872 | struct intel_unpin_work *work = intel_crtc->unpin_work; | |
9873 | u32 addr; | |
9874 | ||
9875 | if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE) | |
9876 | return true; | |
9877 | ||
9878 | if (!work->enable_stall_check) | |
9879 | return false; | |
9880 | ||
9881 | if (work->flip_ready_vblank == 0) { | |
9882 | if (work->flip_queued_ring && | |
9883 | !i915_seqno_passed(work->flip_queued_ring->get_seqno(work->flip_queued_ring, true), | |
9884 | work->flip_queued_seqno)) | |
9885 | return false; | |
9886 | ||
9887 | work->flip_ready_vblank = drm_vblank_count(dev, intel_crtc->pipe); | |
9888 | } | |
9889 | ||
9890 | if (drm_vblank_count(dev, intel_crtc->pipe) - work->flip_ready_vblank < 3) | |
9891 | return false; | |
9892 | ||
9893 | /* Potential stall - if we see that the flip has happened, | |
9894 | * assume a missed interrupt. */ | |
9895 | if (INTEL_INFO(dev)->gen >= 4) | |
9896 | addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane))); | |
9897 | else | |
9898 | addr = I915_READ(DSPADDR(intel_crtc->plane)); | |
9899 | ||
9900 | /* There is a potential issue here with a false positive after a flip | |
9901 | * to the same address. We could address this by checking for a | |
9902 | * non-incrementing frame counter. | |
9903 | */ | |
9904 | return addr == work->gtt_offset; | |
9905 | } | |
9906 | ||
9907 | void intel_check_page_flip(struct drm_device *dev, int pipe) | |
9908 | { | |
9909 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9910 | struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe]; | |
9911 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
9912 | unsigned long flags; | |
9913 | ||
9914 | if (crtc == NULL) | |
9915 | return; | |
9916 | ||
9917 | spin_lock_irqsave(&dev->event_lock, flags); | |
9918 | if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) { | |
9919 | WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n", | |
9920 | intel_crtc->unpin_work->flip_queued_vblank, drm_vblank_count(dev, pipe)); | |
9921 | page_flip_completed(intel_crtc); | |
9922 | } | |
9923 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
9924 | } | |
9925 | ||
6b95a207 KH |
9926 | static int intel_crtc_page_flip(struct drm_crtc *crtc, |
9927 | struct drm_framebuffer *fb, | |
ed8d1975 KP |
9928 | struct drm_pending_vblank_event *event, |
9929 | uint32_t page_flip_flags) | |
6b95a207 KH |
9930 | { |
9931 | struct drm_device *dev = crtc->dev; | |
9932 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 9933 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
2ff8fde1 | 9934 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
6b95a207 | 9935 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
a071fa00 | 9936 | enum pipe pipe = intel_crtc->pipe; |
6b95a207 | 9937 | struct intel_unpin_work *work; |
a4872ba6 | 9938 | struct intel_engine_cs *ring; |
8c9f3aaf | 9939 | unsigned long flags; |
52e68630 | 9940 | int ret; |
6b95a207 | 9941 | |
c76bb61a DS |
9942 | //trigger software GT busyness calculation |
9943 | gen8_flip_interrupt(dev); | |
9944 | ||
2ff8fde1 MR |
9945 | /* |
9946 | * drm_mode_page_flip_ioctl() should already catch this, but double | |
9947 | * check to be safe. In the future we may enable pageflipping from | |
9948 | * a disabled primary plane. | |
9949 | */ | |
9950 | if (WARN_ON(intel_fb_obj(old_fb) == NULL)) | |
9951 | return -EBUSY; | |
9952 | ||
e6a595d2 | 9953 | /* Can't change pixel format via MI display flips. */ |
f4510a27 | 9954 | if (fb->pixel_format != crtc->primary->fb->pixel_format) |
e6a595d2 VS |
9955 | return -EINVAL; |
9956 | ||
9957 | /* | |
9958 | * TILEOFF/LINOFF registers can't be changed via MI display flips. | |
9959 | * Note that pitch changes could also affect these register. | |
9960 | */ | |
9961 | if (INTEL_INFO(dev)->gen > 3 && | |
f4510a27 MR |
9962 | (fb->offsets[0] != crtc->primary->fb->offsets[0] || |
9963 | fb->pitches[0] != crtc->primary->fb->pitches[0])) | |
e6a595d2 VS |
9964 | return -EINVAL; |
9965 | ||
f900db47 CW |
9966 | if (i915_terminally_wedged(&dev_priv->gpu_error)) |
9967 | goto out_hang; | |
9968 | ||
b14c5679 | 9969 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
6b95a207 KH |
9970 | if (work == NULL) |
9971 | return -ENOMEM; | |
9972 | ||
6b95a207 | 9973 | work->event = event; |
b4a98e57 | 9974 | work->crtc = crtc; |
2ff8fde1 | 9975 | work->old_fb_obj = intel_fb_obj(old_fb); |
6b95a207 KH |
9976 | INIT_WORK(&work->work, intel_unpin_work_fn); |
9977 | ||
87b6b101 | 9978 | ret = drm_crtc_vblank_get(crtc); |
7317c75e JB |
9979 | if (ret) |
9980 | goto free_work; | |
9981 | ||
6b95a207 KH |
9982 | /* We borrow the event spin lock for protecting unpin_work */ |
9983 | spin_lock_irqsave(&dev->event_lock, flags); | |
9984 | if (intel_crtc->unpin_work) { | |
d6bbafa1 CW |
9985 | /* Before declaring the flip queue wedged, check if |
9986 | * the hardware completed the operation behind our backs. | |
9987 | */ | |
9988 | if (__intel_pageflip_stall_check(dev, crtc)) { | |
9989 | DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n"); | |
9990 | page_flip_completed(intel_crtc); | |
9991 | } else { | |
9992 | DRM_DEBUG_DRIVER("flip queue: crtc already busy\n"); | |
9993 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
468f0b44 | 9994 | |
d6bbafa1 CW |
9995 | drm_crtc_vblank_put(crtc); |
9996 | kfree(work); | |
9997 | return -EBUSY; | |
9998 | } | |
6b95a207 KH |
9999 | } |
10000 | intel_crtc->unpin_work = work; | |
10001 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
10002 | ||
b4a98e57 CW |
10003 | if (atomic_read(&intel_crtc->unpin_work_count) >= 2) |
10004 | flush_workqueue(dev_priv->wq); | |
10005 | ||
79158103 CW |
10006 | ret = i915_mutex_lock_interruptible(dev); |
10007 | if (ret) | |
10008 | goto cleanup; | |
6b95a207 | 10009 | |
75dfca80 | 10010 | /* Reference the objects for the scheduled work. */ |
05394f39 CW |
10011 | drm_gem_object_reference(&work->old_fb_obj->base); |
10012 | drm_gem_object_reference(&obj->base); | |
6b95a207 | 10013 | |
f4510a27 | 10014 | crtc->primary->fb = fb; |
96b099fd | 10015 | |
e1f99ce6 | 10016 | work->pending_flip_obj = obj; |
e1f99ce6 | 10017 | |
b4a98e57 | 10018 | atomic_inc(&intel_crtc->unpin_work_count); |
10d83730 | 10019 | intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter); |
e1f99ce6 | 10020 | |
75f7f3ec | 10021 | if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) |
a071fa00 | 10022 | work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1; |
75f7f3ec | 10023 | |
4fa62c89 VS |
10024 | if (IS_VALLEYVIEW(dev)) { |
10025 | ring = &dev_priv->ring[BCS]; | |
8e09bf83 CW |
10026 | if (obj->tiling_mode != work->old_fb_obj->tiling_mode) |
10027 | /* vlv: DISPLAY_FLIP fails to change tiling */ | |
10028 | ring = NULL; | |
2a92d5bc CW |
10029 | } else if (IS_IVYBRIDGE(dev)) { |
10030 | ring = &dev_priv->ring[BCS]; | |
4fa62c89 VS |
10031 | } else if (INTEL_INFO(dev)->gen >= 7) { |
10032 | ring = obj->ring; | |
10033 | if (ring == NULL || ring->id != RCS) | |
10034 | ring = &dev_priv->ring[BCS]; | |
10035 | } else { | |
10036 | ring = &dev_priv->ring[RCS]; | |
10037 | } | |
10038 | ||
10039 | ret = intel_pin_and_fence_fb_obj(dev, obj, ring); | |
8c9f3aaf JB |
10040 | if (ret) |
10041 | goto cleanup_pending; | |
6b95a207 | 10042 | |
4fa62c89 VS |
10043 | work->gtt_offset = |
10044 | i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset; | |
10045 | ||
d6bbafa1 | 10046 | if (use_mmio_flip(ring, obj)) { |
84c33a64 SG |
10047 | ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring, |
10048 | page_flip_flags); | |
d6bbafa1 CW |
10049 | if (ret) |
10050 | goto cleanup_unpin; | |
10051 | ||
10052 | work->flip_queued_seqno = obj->last_write_seqno; | |
10053 | work->flip_queued_ring = obj->ring; | |
10054 | } else { | |
84c33a64 | 10055 | ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring, |
d6bbafa1 CW |
10056 | page_flip_flags); |
10057 | if (ret) | |
10058 | goto cleanup_unpin; | |
10059 | ||
10060 | work->flip_queued_seqno = intel_ring_get_seqno(ring); | |
10061 | work->flip_queued_ring = ring; | |
10062 | } | |
10063 | ||
10064 | work->flip_queued_vblank = drm_vblank_count(dev, intel_crtc->pipe); | |
10065 | work->enable_stall_check = true; | |
4fa62c89 | 10066 | |
a071fa00 DV |
10067 | i915_gem_track_fb(work->old_fb_obj, obj, |
10068 | INTEL_FRONTBUFFER_PRIMARY(pipe)); | |
10069 | ||
7782de3b | 10070 | intel_disable_fbc(dev); |
f99d7069 | 10071 | intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe)); |
6b95a207 KH |
10072 | mutex_unlock(&dev->struct_mutex); |
10073 | ||
e5510fac JB |
10074 | trace_i915_flip_request(intel_crtc->plane, obj); |
10075 | ||
6b95a207 | 10076 | return 0; |
96b099fd | 10077 | |
4fa62c89 VS |
10078 | cleanup_unpin: |
10079 | intel_unpin_fb_obj(obj); | |
8c9f3aaf | 10080 | cleanup_pending: |
b4a98e57 | 10081 | atomic_dec(&intel_crtc->unpin_work_count); |
f4510a27 | 10082 | crtc->primary->fb = old_fb; |
05394f39 CW |
10083 | drm_gem_object_unreference(&work->old_fb_obj->base); |
10084 | drm_gem_object_unreference(&obj->base); | |
96b099fd CW |
10085 | mutex_unlock(&dev->struct_mutex); |
10086 | ||
79158103 | 10087 | cleanup: |
96b099fd CW |
10088 | spin_lock_irqsave(&dev->event_lock, flags); |
10089 | intel_crtc->unpin_work = NULL; | |
10090 | spin_unlock_irqrestore(&dev->event_lock, flags); | |
10091 | ||
87b6b101 | 10092 | drm_crtc_vblank_put(crtc); |
7317c75e | 10093 | free_work: |
96b099fd CW |
10094 | kfree(work); |
10095 | ||
f900db47 CW |
10096 | if (ret == -EIO) { |
10097 | out_hang: | |
10098 | intel_crtc_wait_for_pending_flips(crtc); | |
10099 | ret = intel_pipe_set_base(crtc, crtc->x, crtc->y, fb); | |
f0d3dad3 CW |
10100 | if (ret == 0 && event) { |
10101 | spin_lock_irqsave(&dev->event_lock, flags); | |
a071fa00 | 10102 | drm_send_vblank_event(dev, pipe, event); |
f0d3dad3 CW |
10103 | spin_unlock_irqrestore(&dev->event_lock, flags); |
10104 | } | |
f900db47 | 10105 | } |
96b099fd | 10106 | return ret; |
6b95a207 KH |
10107 | } |
10108 | ||
f6e5b160 | 10109 | static struct drm_crtc_helper_funcs intel_helper_funcs = { |
f6e5b160 CW |
10110 | .mode_set_base_atomic = intel_pipe_set_base_atomic, |
10111 | .load_lut = intel_crtc_load_lut, | |
f6e5b160 CW |
10112 | }; |
10113 | ||
9a935856 DV |
10114 | /** |
10115 | * intel_modeset_update_staged_output_state | |
10116 | * | |
10117 | * Updates the staged output configuration state, e.g. after we've read out the | |
10118 | * current hw state. | |
10119 | */ | |
10120 | static void intel_modeset_update_staged_output_state(struct drm_device *dev) | |
f6e5b160 | 10121 | { |
7668851f | 10122 | struct intel_crtc *crtc; |
9a935856 DV |
10123 | struct intel_encoder *encoder; |
10124 | struct intel_connector *connector; | |
f6e5b160 | 10125 | |
9a935856 DV |
10126 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10127 | base.head) { | |
10128 | connector->new_encoder = | |
10129 | to_intel_encoder(connector->base.encoder); | |
10130 | } | |
f6e5b160 | 10131 | |
b2784e15 | 10132 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
10133 | encoder->new_crtc = |
10134 | to_intel_crtc(encoder->base.crtc); | |
10135 | } | |
7668851f | 10136 | |
d3fcc808 | 10137 | for_each_intel_crtc(dev, crtc) { |
7668851f | 10138 | crtc->new_enabled = crtc->base.enabled; |
7bd0a8e7 VS |
10139 | |
10140 | if (crtc->new_enabled) | |
10141 | crtc->new_config = &crtc->config; | |
10142 | else | |
10143 | crtc->new_config = NULL; | |
7668851f | 10144 | } |
f6e5b160 CW |
10145 | } |
10146 | ||
9a935856 DV |
10147 | /** |
10148 | * intel_modeset_commit_output_state | |
10149 | * | |
10150 | * This function copies the stage display pipe configuration to the real one. | |
10151 | */ | |
10152 | static void intel_modeset_commit_output_state(struct drm_device *dev) | |
10153 | { | |
7668851f | 10154 | struct intel_crtc *crtc; |
9a935856 DV |
10155 | struct intel_encoder *encoder; |
10156 | struct intel_connector *connector; | |
f6e5b160 | 10157 | |
9a935856 DV |
10158 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
10159 | base.head) { | |
10160 | connector->base.encoder = &connector->new_encoder->base; | |
10161 | } | |
f6e5b160 | 10162 | |
b2784e15 | 10163 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
10164 | encoder->base.crtc = &encoder->new_crtc->base; |
10165 | } | |
7668851f | 10166 | |
d3fcc808 | 10167 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
10168 | crtc->base.enabled = crtc->new_enabled; |
10169 | } | |
9a935856 DV |
10170 | } |
10171 | ||
050f7aeb | 10172 | static void |
eba905b2 | 10173 | connected_sink_compute_bpp(struct intel_connector *connector, |
050f7aeb DV |
10174 | struct intel_crtc_config *pipe_config) |
10175 | { | |
10176 | int bpp = pipe_config->pipe_bpp; | |
10177 | ||
10178 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n", | |
10179 | connector->base.base.id, | |
c23cc417 | 10180 | connector->base.name); |
050f7aeb DV |
10181 | |
10182 | /* Don't use an invalid EDID bpc value */ | |
10183 | if (connector->base.display_info.bpc && | |
10184 | connector->base.display_info.bpc * 3 < bpp) { | |
10185 | DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n", | |
10186 | bpp, connector->base.display_info.bpc*3); | |
10187 | pipe_config->pipe_bpp = connector->base.display_info.bpc*3; | |
10188 | } | |
10189 | ||
10190 | /* Clamp bpp to 8 on screens without EDID 1.4 */ | |
10191 | if (connector->base.display_info.bpc == 0 && bpp > 24) { | |
10192 | DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n", | |
10193 | bpp); | |
10194 | pipe_config->pipe_bpp = 24; | |
10195 | } | |
10196 | } | |
10197 | ||
4e53c2e0 | 10198 | static int |
050f7aeb DV |
10199 | compute_baseline_pipe_bpp(struct intel_crtc *crtc, |
10200 | struct drm_framebuffer *fb, | |
10201 | struct intel_crtc_config *pipe_config) | |
4e53c2e0 | 10202 | { |
050f7aeb DV |
10203 | struct drm_device *dev = crtc->base.dev; |
10204 | struct intel_connector *connector; | |
4e53c2e0 DV |
10205 | int bpp; |
10206 | ||
d42264b1 DV |
10207 | switch (fb->pixel_format) { |
10208 | case DRM_FORMAT_C8: | |
4e53c2e0 DV |
10209 | bpp = 8*3; /* since we go through a colormap */ |
10210 | break; | |
d42264b1 DV |
10211 | case DRM_FORMAT_XRGB1555: |
10212 | case DRM_FORMAT_ARGB1555: | |
10213 | /* checked in intel_framebuffer_init already */ | |
10214 | if (WARN_ON(INTEL_INFO(dev)->gen > 3)) | |
10215 | return -EINVAL; | |
10216 | case DRM_FORMAT_RGB565: | |
4e53c2e0 DV |
10217 | bpp = 6*3; /* min is 18bpp */ |
10218 | break; | |
d42264b1 DV |
10219 | case DRM_FORMAT_XBGR8888: |
10220 | case DRM_FORMAT_ABGR8888: | |
10221 | /* checked in intel_framebuffer_init already */ | |
10222 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
10223 | return -EINVAL; | |
10224 | case DRM_FORMAT_XRGB8888: | |
10225 | case DRM_FORMAT_ARGB8888: | |
4e53c2e0 DV |
10226 | bpp = 8*3; |
10227 | break; | |
d42264b1 DV |
10228 | case DRM_FORMAT_XRGB2101010: |
10229 | case DRM_FORMAT_ARGB2101010: | |
10230 | case DRM_FORMAT_XBGR2101010: | |
10231 | case DRM_FORMAT_ABGR2101010: | |
10232 | /* checked in intel_framebuffer_init already */ | |
10233 | if (WARN_ON(INTEL_INFO(dev)->gen < 4)) | |
baba133a | 10234 | return -EINVAL; |
4e53c2e0 DV |
10235 | bpp = 10*3; |
10236 | break; | |
baba133a | 10237 | /* TODO: gen4+ supports 16 bpc floating point, too. */ |
4e53c2e0 DV |
10238 | default: |
10239 | DRM_DEBUG_KMS("unsupported depth\n"); | |
10240 | return -EINVAL; | |
10241 | } | |
10242 | ||
4e53c2e0 DV |
10243 | pipe_config->pipe_bpp = bpp; |
10244 | ||
10245 | /* Clamp display bpp to EDID value */ | |
10246 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
050f7aeb | 10247 | base.head) { |
1b829e05 DV |
10248 | if (!connector->new_encoder || |
10249 | connector->new_encoder->new_crtc != crtc) | |
4e53c2e0 DV |
10250 | continue; |
10251 | ||
050f7aeb | 10252 | connected_sink_compute_bpp(connector, pipe_config); |
4e53c2e0 DV |
10253 | } |
10254 | ||
10255 | return bpp; | |
10256 | } | |
10257 | ||
644db711 DV |
10258 | static void intel_dump_crtc_timings(const struct drm_display_mode *mode) |
10259 | { | |
10260 | DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, " | |
10261 | "type: 0x%x flags: 0x%x\n", | |
1342830c | 10262 | mode->crtc_clock, |
644db711 DV |
10263 | mode->crtc_hdisplay, mode->crtc_hsync_start, |
10264 | mode->crtc_hsync_end, mode->crtc_htotal, | |
10265 | mode->crtc_vdisplay, mode->crtc_vsync_start, | |
10266 | mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags); | |
10267 | } | |
10268 | ||
c0b03411 DV |
10269 | static void intel_dump_pipe_config(struct intel_crtc *crtc, |
10270 | struct intel_crtc_config *pipe_config, | |
10271 | const char *context) | |
10272 | { | |
10273 | DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id, | |
10274 | context, pipe_name(crtc->pipe)); | |
10275 | ||
10276 | DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder)); | |
10277 | DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n", | |
10278 | pipe_config->pipe_bpp, pipe_config->dither); | |
10279 | DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", | |
10280 | pipe_config->has_pch_encoder, | |
10281 | pipe_config->fdi_lanes, | |
10282 | pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n, | |
10283 | pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n, | |
10284 | pipe_config->fdi_m_n.tu); | |
eb14cb74 VS |
10285 | DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n", |
10286 | pipe_config->has_dp_encoder, | |
10287 | pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n, | |
10288 | pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n, | |
10289 | pipe_config->dp_m_n.tu); | |
b95af8be VK |
10290 | |
10291 | DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n", | |
10292 | pipe_config->has_dp_encoder, | |
10293 | pipe_config->dp_m2_n2.gmch_m, | |
10294 | pipe_config->dp_m2_n2.gmch_n, | |
10295 | pipe_config->dp_m2_n2.link_m, | |
10296 | pipe_config->dp_m2_n2.link_n, | |
10297 | pipe_config->dp_m2_n2.tu); | |
10298 | ||
c0b03411 DV |
10299 | DRM_DEBUG_KMS("requested mode:\n"); |
10300 | drm_mode_debug_printmodeline(&pipe_config->requested_mode); | |
10301 | DRM_DEBUG_KMS("adjusted mode:\n"); | |
10302 | drm_mode_debug_printmodeline(&pipe_config->adjusted_mode); | |
644db711 | 10303 | intel_dump_crtc_timings(&pipe_config->adjusted_mode); |
d71b8d4a | 10304 | DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock); |
37327abd VS |
10305 | DRM_DEBUG_KMS("pipe src size: %dx%d\n", |
10306 | pipe_config->pipe_src_w, pipe_config->pipe_src_h); | |
c0b03411 DV |
10307 | DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n", |
10308 | pipe_config->gmch_pfit.control, | |
10309 | pipe_config->gmch_pfit.pgm_ratios, | |
10310 | pipe_config->gmch_pfit.lvds_border_bits); | |
fd4daa9c | 10311 | DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n", |
c0b03411 | 10312 | pipe_config->pch_pfit.pos, |
fd4daa9c CW |
10313 | pipe_config->pch_pfit.size, |
10314 | pipe_config->pch_pfit.enabled ? "enabled" : "disabled"); | |
42db64ef | 10315 | DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled); |
cf532bb2 | 10316 | DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide); |
c0b03411 DV |
10317 | } |
10318 | ||
bc079e8b VS |
10319 | static bool encoders_cloneable(const struct intel_encoder *a, |
10320 | const struct intel_encoder *b) | |
accfc0c5 | 10321 | { |
bc079e8b VS |
10322 | /* masks could be asymmetric, so check both ways */ |
10323 | return a == b || (a->cloneable & (1 << b->type) && | |
10324 | b->cloneable & (1 << a->type)); | |
10325 | } | |
10326 | ||
10327 | static bool check_single_encoder_cloning(struct intel_crtc *crtc, | |
10328 | struct intel_encoder *encoder) | |
10329 | { | |
10330 | struct drm_device *dev = crtc->base.dev; | |
10331 | struct intel_encoder *source_encoder; | |
10332 | ||
b2784e15 | 10333 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b VS |
10334 | if (source_encoder->new_crtc != crtc) |
10335 | continue; | |
10336 | ||
10337 | if (!encoders_cloneable(encoder, source_encoder)) | |
10338 | return false; | |
10339 | } | |
10340 | ||
10341 | return true; | |
10342 | } | |
10343 | ||
10344 | static bool check_encoder_cloning(struct intel_crtc *crtc) | |
10345 | { | |
10346 | struct drm_device *dev = crtc->base.dev; | |
accfc0c5 DV |
10347 | struct intel_encoder *encoder; |
10348 | ||
b2784e15 | 10349 | for_each_intel_encoder(dev, encoder) { |
bc079e8b | 10350 | if (encoder->new_crtc != crtc) |
accfc0c5 DV |
10351 | continue; |
10352 | ||
bc079e8b VS |
10353 | if (!check_single_encoder_cloning(crtc, encoder)) |
10354 | return false; | |
accfc0c5 DV |
10355 | } |
10356 | ||
bc079e8b | 10357 | return true; |
accfc0c5 DV |
10358 | } |
10359 | ||
b8cecdf5 DV |
10360 | static struct intel_crtc_config * |
10361 | intel_modeset_pipe_config(struct drm_crtc *crtc, | |
4e53c2e0 | 10362 | struct drm_framebuffer *fb, |
b8cecdf5 | 10363 | struct drm_display_mode *mode) |
ee7b9f93 | 10364 | { |
7758a113 | 10365 | struct drm_device *dev = crtc->dev; |
7758a113 | 10366 | struct intel_encoder *encoder; |
b8cecdf5 | 10367 | struct intel_crtc_config *pipe_config; |
e29c22c0 DV |
10368 | int plane_bpp, ret = -EINVAL; |
10369 | bool retry = true; | |
ee7b9f93 | 10370 | |
bc079e8b | 10371 | if (!check_encoder_cloning(to_intel_crtc(crtc))) { |
accfc0c5 DV |
10372 | DRM_DEBUG_KMS("rejecting invalid cloning configuration\n"); |
10373 | return ERR_PTR(-EINVAL); | |
10374 | } | |
10375 | ||
b8cecdf5 DV |
10376 | pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL); |
10377 | if (!pipe_config) | |
7758a113 DV |
10378 | return ERR_PTR(-ENOMEM); |
10379 | ||
b8cecdf5 DV |
10380 | drm_mode_copy(&pipe_config->adjusted_mode, mode); |
10381 | drm_mode_copy(&pipe_config->requested_mode, mode); | |
37327abd | 10382 | |
e143a21c DV |
10383 | pipe_config->cpu_transcoder = |
10384 | (enum transcoder) to_intel_crtc(crtc)->pipe; | |
c0d43d62 | 10385 | pipe_config->shared_dpll = DPLL_ID_PRIVATE; |
b8cecdf5 | 10386 | |
2960bc9c ID |
10387 | /* |
10388 | * Sanitize sync polarity flags based on requested ones. If neither | |
10389 | * positive or negative polarity is requested, treat this as meaning | |
10390 | * negative polarity. | |
10391 | */ | |
10392 | if (!(pipe_config->adjusted_mode.flags & | |
10393 | (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) | |
10394 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC; | |
10395 | ||
10396 | if (!(pipe_config->adjusted_mode.flags & | |
10397 | (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) | |
10398 | pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC; | |
10399 | ||
050f7aeb DV |
10400 | /* Compute a starting value for pipe_config->pipe_bpp taking the source |
10401 | * plane pixel format and any sink constraints into account. Returns the | |
10402 | * source plane bpp so that dithering can be selected on mismatches | |
10403 | * after encoders and crtc also have had their say. */ | |
10404 | plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc), | |
10405 | fb, pipe_config); | |
4e53c2e0 DV |
10406 | if (plane_bpp < 0) |
10407 | goto fail; | |
10408 | ||
e41a56be VS |
10409 | /* |
10410 | * Determine the real pipe dimensions. Note that stereo modes can | |
10411 | * increase the actual pipe size due to the frame doubling and | |
10412 | * insertion of additional space for blanks between the frame. This | |
10413 | * is stored in the crtc timings. We use the requested mode to do this | |
10414 | * computation to clearly distinguish it from the adjusted mode, which | |
10415 | * can be changed by the connectors in the below retry loop. | |
10416 | */ | |
10417 | drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE); | |
10418 | pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay; | |
10419 | pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay; | |
10420 | ||
e29c22c0 | 10421 | encoder_retry: |
ef1b460d | 10422 | /* Ensure the port clock defaults are reset when retrying. */ |
ff9a6750 | 10423 | pipe_config->port_clock = 0; |
ef1b460d | 10424 | pipe_config->pixel_multiplier = 1; |
ff9a6750 | 10425 | |
135c81b8 | 10426 | /* Fill in default crtc timings, allow encoders to overwrite them. */ |
6ce70f5e | 10427 | drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE); |
135c81b8 | 10428 | |
7758a113 DV |
10429 | /* Pass our mode to the connectors and the CRTC to give them a chance to |
10430 | * adjust it according to limitations or connector properties, and also | |
10431 | * a chance to reject the mode entirely. | |
47f1c6c9 | 10432 | */ |
b2784e15 | 10433 | for_each_intel_encoder(dev, encoder) { |
47f1c6c9 | 10434 | |
7758a113 DV |
10435 | if (&encoder->new_crtc->base != crtc) |
10436 | continue; | |
7ae89233 | 10437 | |
efea6e8e DV |
10438 | if (!(encoder->compute_config(encoder, pipe_config))) { |
10439 | DRM_DEBUG_KMS("Encoder config failure\n"); | |
7758a113 DV |
10440 | goto fail; |
10441 | } | |
ee7b9f93 | 10442 | } |
47f1c6c9 | 10443 | |
ff9a6750 DV |
10444 | /* Set default port clock if not overwritten by the encoder. Needs to be |
10445 | * done afterwards in case the encoder adjusts the mode. */ | |
10446 | if (!pipe_config->port_clock) | |
241bfc38 DL |
10447 | pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock |
10448 | * pipe_config->pixel_multiplier; | |
ff9a6750 | 10449 | |
a43f6e0f | 10450 | ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config); |
e29c22c0 | 10451 | if (ret < 0) { |
7758a113 DV |
10452 | DRM_DEBUG_KMS("CRTC fixup failed\n"); |
10453 | goto fail; | |
ee7b9f93 | 10454 | } |
e29c22c0 DV |
10455 | |
10456 | if (ret == RETRY) { | |
10457 | if (WARN(!retry, "loop in pipe configuration computation\n")) { | |
10458 | ret = -EINVAL; | |
10459 | goto fail; | |
10460 | } | |
10461 | ||
10462 | DRM_DEBUG_KMS("CRTC bw constrained, retrying\n"); | |
10463 | retry = false; | |
10464 | goto encoder_retry; | |
10465 | } | |
10466 | ||
4e53c2e0 DV |
10467 | pipe_config->dither = pipe_config->pipe_bpp != plane_bpp; |
10468 | DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n", | |
10469 | plane_bpp, pipe_config->pipe_bpp, pipe_config->dither); | |
10470 | ||
b8cecdf5 | 10471 | return pipe_config; |
7758a113 | 10472 | fail: |
b8cecdf5 | 10473 | kfree(pipe_config); |
e29c22c0 | 10474 | return ERR_PTR(ret); |
ee7b9f93 | 10475 | } |
47f1c6c9 | 10476 | |
e2e1ed41 DV |
10477 | /* Computes which crtcs are affected and sets the relevant bits in the mask. For |
10478 | * simplicity we use the crtc's pipe number (because it's easier to obtain). */ | |
10479 | static void | |
10480 | intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes, | |
10481 | unsigned *prepare_pipes, unsigned *disable_pipes) | |
79e53945 JB |
10482 | { |
10483 | struct intel_crtc *intel_crtc; | |
e2e1ed41 DV |
10484 | struct drm_device *dev = crtc->dev; |
10485 | struct intel_encoder *encoder; | |
10486 | struct intel_connector *connector; | |
10487 | struct drm_crtc *tmp_crtc; | |
79e53945 | 10488 | |
e2e1ed41 | 10489 | *disable_pipes = *modeset_pipes = *prepare_pipes = 0; |
79e53945 | 10490 | |
e2e1ed41 DV |
10491 | /* Check which crtcs have changed outputs connected to them, these need |
10492 | * to be part of the prepare_pipes mask. We don't (yet) support global | |
10493 | * modeset across multiple crtcs, so modeset_pipes will only have one | |
10494 | * bit set at most. */ | |
10495 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10496 | base.head) { | |
10497 | if (connector->base.encoder == &connector->new_encoder->base) | |
10498 | continue; | |
79e53945 | 10499 | |
e2e1ed41 DV |
10500 | if (connector->base.encoder) { |
10501 | tmp_crtc = connector->base.encoder->crtc; | |
10502 | ||
10503 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10504 | } | |
10505 | ||
10506 | if (connector->new_encoder) | |
10507 | *prepare_pipes |= | |
10508 | 1 << connector->new_encoder->new_crtc->pipe; | |
79e53945 JB |
10509 | } |
10510 | ||
b2784e15 | 10511 | for_each_intel_encoder(dev, encoder) { |
e2e1ed41 DV |
10512 | if (encoder->base.crtc == &encoder->new_crtc->base) |
10513 | continue; | |
10514 | ||
10515 | if (encoder->base.crtc) { | |
10516 | tmp_crtc = encoder->base.crtc; | |
10517 | ||
10518 | *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe; | |
10519 | } | |
10520 | ||
10521 | if (encoder->new_crtc) | |
10522 | *prepare_pipes |= 1 << encoder->new_crtc->pipe; | |
80824003 JB |
10523 | } |
10524 | ||
7668851f | 10525 | /* Check for pipes that will be enabled/disabled ... */ |
d3fcc808 | 10526 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 10527 | if (intel_crtc->base.enabled == intel_crtc->new_enabled) |
e2e1ed41 | 10528 | continue; |
7e7d76c3 | 10529 | |
7668851f | 10530 | if (!intel_crtc->new_enabled) |
e2e1ed41 | 10531 | *disable_pipes |= 1 << intel_crtc->pipe; |
7668851f VS |
10532 | else |
10533 | *prepare_pipes |= 1 << intel_crtc->pipe; | |
7e7d76c3 JB |
10534 | } |
10535 | ||
e2e1ed41 DV |
10536 | |
10537 | /* set_mode is also used to update properties on life display pipes. */ | |
10538 | intel_crtc = to_intel_crtc(crtc); | |
7668851f | 10539 | if (intel_crtc->new_enabled) |
e2e1ed41 DV |
10540 | *prepare_pipes |= 1 << intel_crtc->pipe; |
10541 | ||
b6c5164d DV |
10542 | /* |
10543 | * For simplicity do a full modeset on any pipe where the output routing | |
10544 | * changed. We could be more clever, but that would require us to be | |
10545 | * more careful with calling the relevant encoder->mode_set functions. | |
10546 | */ | |
e2e1ed41 DV |
10547 | if (*prepare_pipes) |
10548 | *modeset_pipes = *prepare_pipes; | |
10549 | ||
10550 | /* ... and mask these out. */ | |
10551 | *modeset_pipes &= ~(*disable_pipes); | |
10552 | *prepare_pipes &= ~(*disable_pipes); | |
b6c5164d DV |
10553 | |
10554 | /* | |
10555 | * HACK: We don't (yet) fully support global modesets. intel_set_config | |
10556 | * obies this rule, but the modeset restore mode of | |
10557 | * intel_modeset_setup_hw_state does not. | |
10558 | */ | |
10559 | *modeset_pipes &= 1 << intel_crtc->pipe; | |
10560 | *prepare_pipes &= 1 << intel_crtc->pipe; | |
e3641d3f DV |
10561 | |
10562 | DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n", | |
10563 | *modeset_pipes, *prepare_pipes, *disable_pipes); | |
47f1c6c9 | 10564 | } |
79e53945 | 10565 | |
ea9d758d | 10566 | static bool intel_crtc_in_use(struct drm_crtc *crtc) |
f6e5b160 | 10567 | { |
ea9d758d | 10568 | struct drm_encoder *encoder; |
f6e5b160 | 10569 | struct drm_device *dev = crtc->dev; |
f6e5b160 | 10570 | |
ea9d758d DV |
10571 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) |
10572 | if (encoder->crtc == crtc) | |
10573 | return true; | |
10574 | ||
10575 | return false; | |
10576 | } | |
10577 | ||
10578 | static void | |
10579 | intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes) | |
10580 | { | |
10581 | struct intel_encoder *intel_encoder; | |
10582 | struct intel_crtc *intel_crtc; | |
10583 | struct drm_connector *connector; | |
10584 | ||
b2784e15 | 10585 | for_each_intel_encoder(dev, intel_encoder) { |
ea9d758d DV |
10586 | if (!intel_encoder->base.crtc) |
10587 | continue; | |
10588 | ||
10589 | intel_crtc = to_intel_crtc(intel_encoder->base.crtc); | |
10590 | ||
10591 | if (prepare_pipes & (1 << intel_crtc->pipe)) | |
10592 | intel_encoder->connectors_active = false; | |
10593 | } | |
10594 | ||
10595 | intel_modeset_commit_output_state(dev); | |
10596 | ||
7668851f | 10597 | /* Double check state. */ |
d3fcc808 | 10598 | for_each_intel_crtc(dev, intel_crtc) { |
7668851f | 10599 | WARN_ON(intel_crtc->base.enabled != intel_crtc_in_use(&intel_crtc->base)); |
7bd0a8e7 VS |
10600 | WARN_ON(intel_crtc->new_config && |
10601 | intel_crtc->new_config != &intel_crtc->config); | |
10602 | WARN_ON(intel_crtc->base.enabled != !!intel_crtc->new_config); | |
ea9d758d DV |
10603 | } |
10604 | ||
10605 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
10606 | if (!connector->encoder || !connector->encoder->crtc) | |
10607 | continue; | |
10608 | ||
10609 | intel_crtc = to_intel_crtc(connector->encoder->crtc); | |
10610 | ||
10611 | if (prepare_pipes & (1 << intel_crtc->pipe)) { | |
68d34720 DV |
10612 | struct drm_property *dpms_property = |
10613 | dev->mode_config.dpms_property; | |
10614 | ||
ea9d758d | 10615 | connector->dpms = DRM_MODE_DPMS_ON; |
662595df | 10616 | drm_object_property_set_value(&connector->base, |
68d34720 DV |
10617 | dpms_property, |
10618 | DRM_MODE_DPMS_ON); | |
ea9d758d DV |
10619 | |
10620 | intel_encoder = to_intel_encoder(connector->encoder); | |
10621 | intel_encoder->connectors_active = true; | |
10622 | } | |
10623 | } | |
10624 | ||
10625 | } | |
10626 | ||
3bd26263 | 10627 | static bool intel_fuzzy_clock_check(int clock1, int clock2) |
f1f644dc | 10628 | { |
3bd26263 | 10629 | int diff; |
f1f644dc JB |
10630 | |
10631 | if (clock1 == clock2) | |
10632 | return true; | |
10633 | ||
10634 | if (!clock1 || !clock2) | |
10635 | return false; | |
10636 | ||
10637 | diff = abs(clock1 - clock2); | |
10638 | ||
10639 | if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105) | |
10640 | return true; | |
10641 | ||
10642 | return false; | |
10643 | } | |
10644 | ||
25c5b266 DV |
10645 | #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \ |
10646 | list_for_each_entry((intel_crtc), \ | |
10647 | &(dev)->mode_config.crtc_list, \ | |
10648 | base.head) \ | |
0973f18f | 10649 | if (mask & (1 <<(intel_crtc)->pipe)) |
25c5b266 | 10650 | |
0e8ffe1b | 10651 | static bool |
2fa2fe9a DV |
10652 | intel_pipe_config_compare(struct drm_device *dev, |
10653 | struct intel_crtc_config *current_config, | |
0e8ffe1b DV |
10654 | struct intel_crtc_config *pipe_config) |
10655 | { | |
66e985c0 DV |
10656 | #define PIPE_CONF_CHECK_X(name) \ |
10657 | if (current_config->name != pipe_config->name) { \ | |
10658 | DRM_ERROR("mismatch in " #name " " \ | |
10659 | "(expected 0x%08x, found 0x%08x)\n", \ | |
10660 | current_config->name, \ | |
10661 | pipe_config->name); \ | |
10662 | return false; \ | |
10663 | } | |
10664 | ||
08a24034 DV |
10665 | #define PIPE_CONF_CHECK_I(name) \ |
10666 | if (current_config->name != pipe_config->name) { \ | |
10667 | DRM_ERROR("mismatch in " #name " " \ | |
10668 | "(expected %i, found %i)\n", \ | |
10669 | current_config->name, \ | |
10670 | pipe_config->name); \ | |
10671 | return false; \ | |
88adfff1 DV |
10672 | } |
10673 | ||
b95af8be VK |
10674 | /* This is required for BDW+ where there is only one set of registers for |
10675 | * switching between high and low RR. | |
10676 | * This macro can be used whenever a comparison has to be made between one | |
10677 | * hw state and multiple sw state variables. | |
10678 | */ | |
10679 | #define PIPE_CONF_CHECK_I_ALT(name, alt_name) \ | |
10680 | if ((current_config->name != pipe_config->name) && \ | |
10681 | (current_config->alt_name != pipe_config->name)) { \ | |
10682 | DRM_ERROR("mismatch in " #name " " \ | |
10683 | "(expected %i or %i, found %i)\n", \ | |
10684 | current_config->name, \ | |
10685 | current_config->alt_name, \ | |
10686 | pipe_config->name); \ | |
10687 | return false; \ | |
10688 | } | |
10689 | ||
1bd1bd80 DV |
10690 | #define PIPE_CONF_CHECK_FLAGS(name, mask) \ |
10691 | if ((current_config->name ^ pipe_config->name) & (mask)) { \ | |
6f02488e | 10692 | DRM_ERROR("mismatch in " #name "(" #mask ") " \ |
1bd1bd80 DV |
10693 | "(expected %i, found %i)\n", \ |
10694 | current_config->name & (mask), \ | |
10695 | pipe_config->name & (mask)); \ | |
10696 | return false; \ | |
10697 | } | |
10698 | ||
5e550656 VS |
10699 | #define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \ |
10700 | if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \ | |
10701 | DRM_ERROR("mismatch in " #name " " \ | |
10702 | "(expected %i, found %i)\n", \ | |
10703 | current_config->name, \ | |
10704 | pipe_config->name); \ | |
10705 | return false; \ | |
10706 | } | |
10707 | ||
bb760063 DV |
10708 | #define PIPE_CONF_QUIRK(quirk) \ |
10709 | ((current_config->quirks | pipe_config->quirks) & (quirk)) | |
10710 | ||
eccb140b DV |
10711 | PIPE_CONF_CHECK_I(cpu_transcoder); |
10712 | ||
08a24034 DV |
10713 | PIPE_CONF_CHECK_I(has_pch_encoder); |
10714 | PIPE_CONF_CHECK_I(fdi_lanes); | |
72419203 DV |
10715 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_m); |
10716 | PIPE_CONF_CHECK_I(fdi_m_n.gmch_n); | |
10717 | PIPE_CONF_CHECK_I(fdi_m_n.link_m); | |
10718 | PIPE_CONF_CHECK_I(fdi_m_n.link_n); | |
10719 | PIPE_CONF_CHECK_I(fdi_m_n.tu); | |
08a24034 | 10720 | |
eb14cb74 | 10721 | PIPE_CONF_CHECK_I(has_dp_encoder); |
b95af8be VK |
10722 | |
10723 | if (INTEL_INFO(dev)->gen < 8) { | |
10724 | PIPE_CONF_CHECK_I(dp_m_n.gmch_m); | |
10725 | PIPE_CONF_CHECK_I(dp_m_n.gmch_n); | |
10726 | PIPE_CONF_CHECK_I(dp_m_n.link_m); | |
10727 | PIPE_CONF_CHECK_I(dp_m_n.link_n); | |
10728 | PIPE_CONF_CHECK_I(dp_m_n.tu); | |
10729 | ||
10730 | if (current_config->has_drrs) { | |
10731 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m); | |
10732 | PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n); | |
10733 | PIPE_CONF_CHECK_I(dp_m2_n2.link_m); | |
10734 | PIPE_CONF_CHECK_I(dp_m2_n2.link_n); | |
10735 | PIPE_CONF_CHECK_I(dp_m2_n2.tu); | |
10736 | } | |
10737 | } else { | |
10738 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m); | |
10739 | PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n); | |
10740 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m); | |
10741 | PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n); | |
10742 | PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu); | |
10743 | } | |
eb14cb74 | 10744 | |
1bd1bd80 DV |
10745 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay); |
10746 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal); | |
10747 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start); | |
10748 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end); | |
10749 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start); | |
10750 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end); | |
10751 | ||
10752 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay); | |
10753 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal); | |
10754 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start); | |
10755 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end); | |
10756 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start); | |
10757 | PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end); | |
10758 | ||
c93f54cf | 10759 | PIPE_CONF_CHECK_I(pixel_multiplier); |
6897b4b5 | 10760 | PIPE_CONF_CHECK_I(has_hdmi_sink); |
b5a9fa09 DV |
10761 | if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) || |
10762 | IS_VALLEYVIEW(dev)) | |
10763 | PIPE_CONF_CHECK_I(limited_color_range); | |
6c49f241 | 10764 | |
9ed109a7 DV |
10765 | PIPE_CONF_CHECK_I(has_audio); |
10766 | ||
1bd1bd80 DV |
10767 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, |
10768 | DRM_MODE_FLAG_INTERLACE); | |
10769 | ||
bb760063 DV |
10770 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) { |
10771 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10772 | DRM_MODE_FLAG_PHSYNC); | |
10773 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10774 | DRM_MODE_FLAG_NHSYNC); | |
10775 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10776 | DRM_MODE_FLAG_PVSYNC); | |
10777 | PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags, | |
10778 | DRM_MODE_FLAG_NVSYNC); | |
10779 | } | |
045ac3b5 | 10780 | |
37327abd VS |
10781 | PIPE_CONF_CHECK_I(pipe_src_w); |
10782 | PIPE_CONF_CHECK_I(pipe_src_h); | |
1bd1bd80 | 10783 | |
9953599b DV |
10784 | /* |
10785 | * FIXME: BIOS likes to set up a cloned config with lvds+external | |
10786 | * screen. Since we don't yet re-compute the pipe config when moving | |
10787 | * just the lvds port away to another pipe the sw tracking won't match. | |
10788 | * | |
10789 | * Proper atomic modesets with recomputed global state will fix this. | |
10790 | * Until then just don't check gmch state for inherited modes. | |
10791 | */ | |
10792 | if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) { | |
10793 | PIPE_CONF_CHECK_I(gmch_pfit.control); | |
10794 | /* pfit ratios are autocomputed by the hw on gen4+ */ | |
10795 | if (INTEL_INFO(dev)->gen < 4) | |
10796 | PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios); | |
10797 | PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits); | |
10798 | } | |
10799 | ||
fd4daa9c CW |
10800 | PIPE_CONF_CHECK_I(pch_pfit.enabled); |
10801 | if (current_config->pch_pfit.enabled) { | |
10802 | PIPE_CONF_CHECK_I(pch_pfit.pos); | |
10803 | PIPE_CONF_CHECK_I(pch_pfit.size); | |
10804 | } | |
2fa2fe9a | 10805 | |
e59150dc JB |
10806 | /* BDW+ don't expose a synchronous way to read the state */ |
10807 | if (IS_HASWELL(dev)) | |
10808 | PIPE_CONF_CHECK_I(ips_enabled); | |
42db64ef | 10809 | |
282740f7 VS |
10810 | PIPE_CONF_CHECK_I(double_wide); |
10811 | ||
26804afd DV |
10812 | PIPE_CONF_CHECK_X(ddi_pll_sel); |
10813 | ||
c0d43d62 | 10814 | PIPE_CONF_CHECK_I(shared_dpll); |
66e985c0 | 10815 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll); |
8bcc2795 | 10816 | PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md); |
66e985c0 DV |
10817 | PIPE_CONF_CHECK_X(dpll_hw_state.fp0); |
10818 | PIPE_CONF_CHECK_X(dpll_hw_state.fp1); | |
d452c5b6 | 10819 | PIPE_CONF_CHECK_X(dpll_hw_state.wrpll); |
c0d43d62 | 10820 | |
42571aef VS |
10821 | if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) |
10822 | PIPE_CONF_CHECK_I(pipe_bpp); | |
10823 | ||
a9a7e98a JB |
10824 | PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock); |
10825 | PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock); | |
5e550656 | 10826 | |
66e985c0 | 10827 | #undef PIPE_CONF_CHECK_X |
08a24034 | 10828 | #undef PIPE_CONF_CHECK_I |
b95af8be | 10829 | #undef PIPE_CONF_CHECK_I_ALT |
1bd1bd80 | 10830 | #undef PIPE_CONF_CHECK_FLAGS |
5e550656 | 10831 | #undef PIPE_CONF_CHECK_CLOCK_FUZZY |
bb760063 | 10832 | #undef PIPE_CONF_QUIRK |
88adfff1 | 10833 | |
0e8ffe1b DV |
10834 | return true; |
10835 | } | |
10836 | ||
91d1b4bd DV |
10837 | static void |
10838 | check_connector_state(struct drm_device *dev) | |
8af6cf88 | 10839 | { |
8af6cf88 DV |
10840 | struct intel_connector *connector; |
10841 | ||
10842 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10843 | base.head) { | |
10844 | /* This also checks the encoder/connector hw state with the | |
10845 | * ->get_hw_state callbacks. */ | |
10846 | intel_connector_check_state(connector); | |
10847 | ||
10848 | WARN(&connector->new_encoder->base != connector->base.encoder, | |
10849 | "connector's staged encoder doesn't match current encoder\n"); | |
10850 | } | |
91d1b4bd DV |
10851 | } |
10852 | ||
10853 | static void | |
10854 | check_encoder_state(struct drm_device *dev) | |
10855 | { | |
10856 | struct intel_encoder *encoder; | |
10857 | struct intel_connector *connector; | |
8af6cf88 | 10858 | |
b2784e15 | 10859 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
10860 | bool enabled = false; |
10861 | bool active = false; | |
10862 | enum pipe pipe, tracked_pipe; | |
10863 | ||
10864 | DRM_DEBUG_KMS("[ENCODER:%d:%s]\n", | |
10865 | encoder->base.base.id, | |
8e329a03 | 10866 | encoder->base.name); |
8af6cf88 DV |
10867 | |
10868 | WARN(&encoder->new_crtc->base != encoder->base.crtc, | |
10869 | "encoder's stage crtc doesn't match current crtc\n"); | |
10870 | WARN(encoder->connectors_active && !encoder->base.crtc, | |
10871 | "encoder's active_connectors set, but no crtc\n"); | |
10872 | ||
10873 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
10874 | base.head) { | |
10875 | if (connector->base.encoder != &encoder->base) | |
10876 | continue; | |
10877 | enabled = true; | |
10878 | if (connector->base.dpms != DRM_MODE_DPMS_OFF) | |
10879 | active = true; | |
10880 | } | |
0e32b39c DA |
10881 | /* |
10882 | * for MST connectors if we unplug the connector is gone | |
10883 | * away but the encoder is still connected to a crtc | |
10884 | * until a modeset happens in response to the hotplug. | |
10885 | */ | |
10886 | if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST) | |
10887 | continue; | |
10888 | ||
8af6cf88 DV |
10889 | WARN(!!encoder->base.crtc != enabled, |
10890 | "encoder's enabled state mismatch " | |
10891 | "(expected %i, found %i)\n", | |
10892 | !!encoder->base.crtc, enabled); | |
10893 | WARN(active && !encoder->base.crtc, | |
10894 | "active encoder with no crtc\n"); | |
10895 | ||
10896 | WARN(encoder->connectors_active != active, | |
10897 | "encoder's computed active state doesn't match tracked active state " | |
10898 | "(expected %i, found %i)\n", active, encoder->connectors_active); | |
10899 | ||
10900 | active = encoder->get_hw_state(encoder, &pipe); | |
10901 | WARN(active != encoder->connectors_active, | |
10902 | "encoder's hw state doesn't match sw tracking " | |
10903 | "(expected %i, found %i)\n", | |
10904 | encoder->connectors_active, active); | |
10905 | ||
10906 | if (!encoder->base.crtc) | |
10907 | continue; | |
10908 | ||
10909 | tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe; | |
10910 | WARN(active && pipe != tracked_pipe, | |
10911 | "active encoder's pipe doesn't match" | |
10912 | "(expected %i, found %i)\n", | |
10913 | tracked_pipe, pipe); | |
10914 | ||
10915 | } | |
91d1b4bd DV |
10916 | } |
10917 | ||
10918 | static void | |
10919 | check_crtc_state(struct drm_device *dev) | |
10920 | { | |
fbee40df | 10921 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10922 | struct intel_crtc *crtc; |
10923 | struct intel_encoder *encoder; | |
10924 | struct intel_crtc_config pipe_config; | |
8af6cf88 | 10925 | |
d3fcc808 | 10926 | for_each_intel_crtc(dev, crtc) { |
8af6cf88 DV |
10927 | bool enabled = false; |
10928 | bool active = false; | |
10929 | ||
045ac3b5 JB |
10930 | memset(&pipe_config, 0, sizeof(pipe_config)); |
10931 | ||
8af6cf88 DV |
10932 | DRM_DEBUG_KMS("[CRTC:%d]\n", |
10933 | crtc->base.base.id); | |
10934 | ||
10935 | WARN(crtc->active && !crtc->base.enabled, | |
10936 | "active crtc, but not enabled in sw tracking\n"); | |
10937 | ||
b2784e15 | 10938 | for_each_intel_encoder(dev, encoder) { |
8af6cf88 DV |
10939 | if (encoder->base.crtc != &crtc->base) |
10940 | continue; | |
10941 | enabled = true; | |
10942 | if (encoder->connectors_active) | |
10943 | active = true; | |
10944 | } | |
6c49f241 | 10945 | |
8af6cf88 DV |
10946 | WARN(active != crtc->active, |
10947 | "crtc's computed active state doesn't match tracked active state " | |
10948 | "(expected %i, found %i)\n", active, crtc->active); | |
10949 | WARN(enabled != crtc->base.enabled, | |
10950 | "crtc's computed enabled state doesn't match tracked enabled state " | |
10951 | "(expected %i, found %i)\n", enabled, crtc->base.enabled); | |
10952 | ||
0e8ffe1b DV |
10953 | active = dev_priv->display.get_pipe_config(crtc, |
10954 | &pipe_config); | |
d62cf62a | 10955 | |
b6b5d049 VS |
10956 | /* hw state is inconsistent with the pipe quirk */ |
10957 | if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) || | |
10958 | (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)) | |
d62cf62a DV |
10959 | active = crtc->active; |
10960 | ||
b2784e15 | 10961 | for_each_intel_encoder(dev, encoder) { |
3eaba51c | 10962 | enum pipe pipe; |
6c49f241 DV |
10963 | if (encoder->base.crtc != &crtc->base) |
10964 | continue; | |
1d37b689 | 10965 | if (encoder->get_hw_state(encoder, &pipe)) |
6c49f241 DV |
10966 | encoder->get_config(encoder, &pipe_config); |
10967 | } | |
10968 | ||
0e8ffe1b DV |
10969 | WARN(crtc->active != active, |
10970 | "crtc active state doesn't match with hw state " | |
10971 | "(expected %i, found %i)\n", crtc->active, active); | |
10972 | ||
c0b03411 DV |
10973 | if (active && |
10974 | !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) { | |
10975 | WARN(1, "pipe state doesn't match!\n"); | |
10976 | intel_dump_pipe_config(crtc, &pipe_config, | |
10977 | "[hw state]"); | |
10978 | intel_dump_pipe_config(crtc, &crtc->config, | |
10979 | "[sw state]"); | |
10980 | } | |
8af6cf88 DV |
10981 | } |
10982 | } | |
10983 | ||
91d1b4bd DV |
10984 | static void |
10985 | check_shared_dpll_state(struct drm_device *dev) | |
10986 | { | |
fbee40df | 10987 | struct drm_i915_private *dev_priv = dev->dev_private; |
91d1b4bd DV |
10988 | struct intel_crtc *crtc; |
10989 | struct intel_dpll_hw_state dpll_hw_state; | |
10990 | int i; | |
5358901f DV |
10991 | |
10992 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { | |
10993 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
10994 | int enabled_crtcs = 0, active_crtcs = 0; | |
10995 | bool active; | |
10996 | ||
10997 | memset(&dpll_hw_state, 0, sizeof(dpll_hw_state)); | |
10998 | ||
10999 | DRM_DEBUG_KMS("%s\n", pll->name); | |
11000 | ||
11001 | active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state); | |
11002 | ||
11003 | WARN(pll->active > pll->refcount, | |
11004 | "more active pll users than references: %i vs %i\n", | |
11005 | pll->active, pll->refcount); | |
11006 | WARN(pll->active && !pll->on, | |
11007 | "pll in active use but not on in sw tracking\n"); | |
35c95375 DV |
11008 | WARN(pll->on && !pll->active, |
11009 | "pll in on but not on in use in sw tracking\n"); | |
5358901f DV |
11010 | WARN(pll->on != active, |
11011 | "pll on state mismatch (expected %i, found %i)\n", | |
11012 | pll->on, active); | |
11013 | ||
d3fcc808 | 11014 | for_each_intel_crtc(dev, crtc) { |
5358901f DV |
11015 | if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll) |
11016 | enabled_crtcs++; | |
11017 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) | |
11018 | active_crtcs++; | |
11019 | } | |
11020 | WARN(pll->active != active_crtcs, | |
11021 | "pll active crtcs mismatch (expected %i, found %i)\n", | |
11022 | pll->active, active_crtcs); | |
11023 | WARN(pll->refcount != enabled_crtcs, | |
11024 | "pll enabled crtcs mismatch (expected %i, found %i)\n", | |
11025 | pll->refcount, enabled_crtcs); | |
66e985c0 DV |
11026 | |
11027 | WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state, | |
11028 | sizeof(dpll_hw_state)), | |
11029 | "pll hw state mismatch\n"); | |
5358901f | 11030 | } |
8af6cf88 DV |
11031 | } |
11032 | ||
91d1b4bd DV |
11033 | void |
11034 | intel_modeset_check_state(struct drm_device *dev) | |
11035 | { | |
11036 | check_connector_state(dev); | |
11037 | check_encoder_state(dev); | |
11038 | check_crtc_state(dev); | |
11039 | check_shared_dpll_state(dev); | |
11040 | } | |
11041 | ||
18442d08 VS |
11042 | void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, |
11043 | int dotclock) | |
11044 | { | |
11045 | /* | |
11046 | * FDI already provided one idea for the dotclock. | |
11047 | * Yell if the encoder disagrees. | |
11048 | */ | |
241bfc38 | 11049 | WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock), |
18442d08 | 11050 | "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n", |
241bfc38 | 11051 | pipe_config->adjusted_mode.crtc_clock, dotclock); |
18442d08 VS |
11052 | } |
11053 | ||
80715b2f VS |
11054 | static void update_scanline_offset(struct intel_crtc *crtc) |
11055 | { | |
11056 | struct drm_device *dev = crtc->base.dev; | |
11057 | ||
11058 | /* | |
11059 | * The scanline counter increments at the leading edge of hsync. | |
11060 | * | |
11061 | * On most platforms it starts counting from vtotal-1 on the | |
11062 | * first active line. That means the scanline counter value is | |
11063 | * always one less than what we would expect. Ie. just after | |
11064 | * start of vblank, which also occurs at start of hsync (on the | |
11065 | * last active line), the scanline counter will read vblank_start-1. | |
11066 | * | |
11067 | * On gen2 the scanline counter starts counting from 1 instead | |
11068 | * of vtotal-1, so we have to subtract one (or rather add vtotal-1 | |
11069 | * to keep the value positive), instead of adding one. | |
11070 | * | |
11071 | * On HSW+ the behaviour of the scanline counter depends on the output | |
11072 | * type. For DP ports it behaves like most other platforms, but on HDMI | |
11073 | * there's an extra 1 line difference. So we need to add two instead of | |
11074 | * one to the value. | |
11075 | */ | |
11076 | if (IS_GEN2(dev)) { | |
11077 | const struct drm_display_mode *mode = &crtc->config.adjusted_mode; | |
11078 | int vtotal; | |
11079 | ||
11080 | vtotal = mode->crtc_vtotal; | |
11081 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) | |
11082 | vtotal /= 2; | |
11083 | ||
11084 | crtc->scanline_offset = vtotal - 1; | |
11085 | } else if (HAS_DDI(dev) && | |
11086 | intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI)) { | |
11087 | crtc->scanline_offset = 2; | |
11088 | } else | |
11089 | crtc->scanline_offset = 1; | |
11090 | } | |
11091 | ||
f30da187 DV |
11092 | static int __intel_set_mode(struct drm_crtc *crtc, |
11093 | struct drm_display_mode *mode, | |
11094 | int x, int y, struct drm_framebuffer *fb) | |
a6778b3c DV |
11095 | { |
11096 | struct drm_device *dev = crtc->dev; | |
fbee40df | 11097 | struct drm_i915_private *dev_priv = dev->dev_private; |
4b4b9238 | 11098 | struct drm_display_mode *saved_mode; |
b8cecdf5 | 11099 | struct intel_crtc_config *pipe_config = NULL; |
25c5b266 DV |
11100 | struct intel_crtc *intel_crtc; |
11101 | unsigned disable_pipes, prepare_pipes, modeset_pipes; | |
c0c36b94 | 11102 | int ret = 0; |
a6778b3c | 11103 | |
4b4b9238 | 11104 | saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL); |
c0c36b94 CW |
11105 | if (!saved_mode) |
11106 | return -ENOMEM; | |
a6778b3c | 11107 | |
e2e1ed41 | 11108 | intel_modeset_affected_pipes(crtc, &modeset_pipes, |
25c5b266 DV |
11109 | &prepare_pipes, &disable_pipes); |
11110 | ||
3ac18232 | 11111 | *saved_mode = crtc->mode; |
a6778b3c | 11112 | |
25c5b266 DV |
11113 | /* Hack: Because we don't (yet) support global modeset on multiple |
11114 | * crtcs, we don't keep track of the new mode for more than one crtc. | |
11115 | * Hence simply check whether any bit is set in modeset_pipes in all the | |
11116 | * pieces of code that are not yet converted to deal with mutliple crtcs | |
11117 | * changing their mode at the same time. */ | |
25c5b266 | 11118 | if (modeset_pipes) { |
4e53c2e0 | 11119 | pipe_config = intel_modeset_pipe_config(crtc, fb, mode); |
b8cecdf5 DV |
11120 | if (IS_ERR(pipe_config)) { |
11121 | ret = PTR_ERR(pipe_config); | |
11122 | pipe_config = NULL; | |
11123 | ||
3ac18232 | 11124 | goto out; |
25c5b266 | 11125 | } |
c0b03411 DV |
11126 | intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config, |
11127 | "[modeset]"); | |
50741abc | 11128 | to_intel_crtc(crtc)->new_config = pipe_config; |
25c5b266 | 11129 | } |
a6778b3c | 11130 | |
30a970c6 JB |
11131 | /* |
11132 | * See if the config requires any additional preparation, e.g. | |
11133 | * to adjust global state with pipes off. We need to do this | |
11134 | * here so we can get the modeset_pipe updated config for the new | |
11135 | * mode set on this crtc. For other crtcs we need to use the | |
11136 | * adjusted_mode bits in the crtc directly. | |
11137 | */ | |
c164f833 | 11138 | if (IS_VALLEYVIEW(dev)) { |
2f2d7aa1 | 11139 | valleyview_modeset_global_pipes(dev, &prepare_pipes); |
30a970c6 | 11140 | |
c164f833 VS |
11141 | /* may have added more to prepare_pipes than we should */ |
11142 | prepare_pipes &= ~disable_pipes; | |
11143 | } | |
11144 | ||
460da916 DV |
11145 | for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc) |
11146 | intel_crtc_disable(&intel_crtc->base); | |
11147 | ||
ea9d758d DV |
11148 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
11149 | if (intel_crtc->base.enabled) | |
11150 | dev_priv->display.crtc_disable(&intel_crtc->base); | |
11151 | } | |
a6778b3c | 11152 | |
6c4c86f5 DV |
11153 | /* crtc->mode is already used by the ->mode_set callbacks, hence we need |
11154 | * to set it here already despite that we pass it down the callchain. | |
f6e5b160 | 11155 | */ |
b8cecdf5 | 11156 | if (modeset_pipes) { |
25c5b266 | 11157 | crtc->mode = *mode; |
b8cecdf5 DV |
11158 | /* mode_set/enable/disable functions rely on a correct pipe |
11159 | * config. */ | |
11160 | to_intel_crtc(crtc)->config = *pipe_config; | |
50741abc | 11161 | to_intel_crtc(crtc)->new_config = &to_intel_crtc(crtc)->config; |
c326c0a9 VS |
11162 | |
11163 | /* | |
11164 | * Calculate and store various constants which | |
11165 | * are later needed by vblank and swap-completion | |
11166 | * timestamping. They are derived from true hwmode. | |
11167 | */ | |
11168 | drm_calc_timestamping_constants(crtc, | |
11169 | &pipe_config->adjusted_mode); | |
b8cecdf5 | 11170 | } |
7758a113 | 11171 | |
ea9d758d DV |
11172 | /* Only after disabling all output pipelines that will be changed can we |
11173 | * update the the output configuration. */ | |
11174 | intel_modeset_update_state(dev, prepare_pipes); | |
f6e5b160 | 11175 | |
47fab737 DV |
11176 | if (dev_priv->display.modeset_global_resources) |
11177 | dev_priv->display.modeset_global_resources(dev); | |
11178 | ||
a6778b3c DV |
11179 | /* Set up the DPLL and any encoders state that needs to adjust or depend |
11180 | * on the DPLL. | |
f6e5b160 | 11181 | */ |
25c5b266 | 11182 | for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) { |
2ff8fde1 MR |
11183 | struct drm_framebuffer *old_fb = crtc->primary->fb; |
11184 | struct drm_i915_gem_object *old_obj = intel_fb_obj(old_fb); | |
11185 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); | |
4c10794f DV |
11186 | |
11187 | mutex_lock(&dev->struct_mutex); | |
11188 | ret = intel_pin_and_fence_fb_obj(dev, | |
a071fa00 | 11189 | obj, |
4c10794f DV |
11190 | NULL); |
11191 | if (ret != 0) { | |
11192 | DRM_ERROR("pin & fence failed\n"); | |
11193 | mutex_unlock(&dev->struct_mutex); | |
11194 | goto done; | |
11195 | } | |
2ff8fde1 | 11196 | if (old_fb) |
a071fa00 | 11197 | intel_unpin_fb_obj(old_obj); |
a071fa00 DV |
11198 | i915_gem_track_fb(old_obj, obj, |
11199 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); | |
4c10794f DV |
11200 | mutex_unlock(&dev->struct_mutex); |
11201 | ||
11202 | crtc->primary->fb = fb; | |
11203 | crtc->x = x; | |
11204 | crtc->y = y; | |
11205 | ||
4271b753 DV |
11206 | ret = dev_priv->display.crtc_mode_set(&intel_crtc->base, |
11207 | x, y, fb); | |
c0c36b94 CW |
11208 | if (ret) |
11209 | goto done; | |
a6778b3c DV |
11210 | } |
11211 | ||
11212 | /* Now enable the clocks, plane, pipe, and connectors that we set up. */ | |
80715b2f VS |
11213 | for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) { |
11214 | update_scanline_offset(intel_crtc); | |
11215 | ||
25c5b266 | 11216 | dev_priv->display.crtc_enable(&intel_crtc->base); |
80715b2f | 11217 | } |
a6778b3c | 11218 | |
a6778b3c DV |
11219 | /* FIXME: add subpixel order */ |
11220 | done: | |
4b4b9238 | 11221 | if (ret && crtc->enabled) |
3ac18232 | 11222 | crtc->mode = *saved_mode; |
a6778b3c | 11223 | |
3ac18232 | 11224 | out: |
b8cecdf5 | 11225 | kfree(pipe_config); |
3ac18232 | 11226 | kfree(saved_mode); |
a6778b3c | 11227 | return ret; |
f6e5b160 CW |
11228 | } |
11229 | ||
e7457a9a DL |
11230 | static int intel_set_mode(struct drm_crtc *crtc, |
11231 | struct drm_display_mode *mode, | |
11232 | int x, int y, struct drm_framebuffer *fb) | |
f30da187 DV |
11233 | { |
11234 | int ret; | |
11235 | ||
11236 | ret = __intel_set_mode(crtc, mode, x, y, fb); | |
11237 | ||
11238 | if (ret == 0) | |
11239 | intel_modeset_check_state(crtc->dev); | |
11240 | ||
11241 | return ret; | |
11242 | } | |
11243 | ||
c0c36b94 CW |
11244 | void intel_crtc_restore_mode(struct drm_crtc *crtc) |
11245 | { | |
f4510a27 | 11246 | intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb); |
c0c36b94 CW |
11247 | } |
11248 | ||
25c5b266 DV |
11249 | #undef for_each_intel_crtc_masked |
11250 | ||
d9e55608 DV |
11251 | static void intel_set_config_free(struct intel_set_config *config) |
11252 | { | |
11253 | if (!config) | |
11254 | return; | |
11255 | ||
1aa4b628 DV |
11256 | kfree(config->save_connector_encoders); |
11257 | kfree(config->save_encoder_crtcs); | |
7668851f | 11258 | kfree(config->save_crtc_enabled); |
d9e55608 DV |
11259 | kfree(config); |
11260 | } | |
11261 | ||
85f9eb71 DV |
11262 | static int intel_set_config_save_state(struct drm_device *dev, |
11263 | struct intel_set_config *config) | |
11264 | { | |
7668851f | 11265 | struct drm_crtc *crtc; |
85f9eb71 DV |
11266 | struct drm_encoder *encoder; |
11267 | struct drm_connector *connector; | |
11268 | int count; | |
11269 | ||
7668851f VS |
11270 | config->save_crtc_enabled = |
11271 | kcalloc(dev->mode_config.num_crtc, | |
11272 | sizeof(bool), GFP_KERNEL); | |
11273 | if (!config->save_crtc_enabled) | |
11274 | return -ENOMEM; | |
11275 | ||
1aa4b628 DV |
11276 | config->save_encoder_crtcs = |
11277 | kcalloc(dev->mode_config.num_encoder, | |
11278 | sizeof(struct drm_crtc *), GFP_KERNEL); | |
11279 | if (!config->save_encoder_crtcs) | |
85f9eb71 DV |
11280 | return -ENOMEM; |
11281 | ||
1aa4b628 DV |
11282 | config->save_connector_encoders = |
11283 | kcalloc(dev->mode_config.num_connector, | |
11284 | sizeof(struct drm_encoder *), GFP_KERNEL); | |
11285 | if (!config->save_connector_encoders) | |
85f9eb71 DV |
11286 | return -ENOMEM; |
11287 | ||
11288 | /* Copy data. Note that driver private data is not affected. | |
11289 | * Should anything bad happen only the expected state is | |
11290 | * restored, not the drivers personal bookkeeping. | |
11291 | */ | |
7668851f | 11292 | count = 0; |
70e1e0ec | 11293 | for_each_crtc(dev, crtc) { |
7668851f VS |
11294 | config->save_crtc_enabled[count++] = crtc->enabled; |
11295 | } | |
11296 | ||
85f9eb71 DV |
11297 | count = 0; |
11298 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { | |
1aa4b628 | 11299 | config->save_encoder_crtcs[count++] = encoder->crtc; |
85f9eb71 DV |
11300 | } |
11301 | ||
11302 | count = 0; | |
11303 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
1aa4b628 | 11304 | config->save_connector_encoders[count++] = connector->encoder; |
85f9eb71 DV |
11305 | } |
11306 | ||
11307 | return 0; | |
11308 | } | |
11309 | ||
11310 | static void intel_set_config_restore_state(struct drm_device *dev, | |
11311 | struct intel_set_config *config) | |
11312 | { | |
7668851f | 11313 | struct intel_crtc *crtc; |
9a935856 DV |
11314 | struct intel_encoder *encoder; |
11315 | struct intel_connector *connector; | |
85f9eb71 DV |
11316 | int count; |
11317 | ||
7668851f | 11318 | count = 0; |
d3fcc808 | 11319 | for_each_intel_crtc(dev, crtc) { |
7668851f | 11320 | crtc->new_enabled = config->save_crtc_enabled[count++]; |
7bd0a8e7 VS |
11321 | |
11322 | if (crtc->new_enabled) | |
11323 | crtc->new_config = &crtc->config; | |
11324 | else | |
11325 | crtc->new_config = NULL; | |
7668851f VS |
11326 | } |
11327 | ||
85f9eb71 | 11328 | count = 0; |
b2784e15 | 11329 | for_each_intel_encoder(dev, encoder) { |
9a935856 DV |
11330 | encoder->new_crtc = |
11331 | to_intel_crtc(config->save_encoder_crtcs[count++]); | |
85f9eb71 DV |
11332 | } |
11333 | ||
11334 | count = 0; | |
9a935856 DV |
11335 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { |
11336 | connector->new_encoder = | |
11337 | to_intel_encoder(config->save_connector_encoders[count++]); | |
85f9eb71 DV |
11338 | } |
11339 | } | |
11340 | ||
e3de42b6 | 11341 | static bool |
2e57f47d | 11342 | is_crtc_connector_off(struct drm_mode_set *set) |
e3de42b6 ID |
11343 | { |
11344 | int i; | |
11345 | ||
2e57f47d CW |
11346 | if (set->num_connectors == 0) |
11347 | return false; | |
11348 | ||
11349 | if (WARN_ON(set->connectors == NULL)) | |
11350 | return false; | |
11351 | ||
11352 | for (i = 0; i < set->num_connectors; i++) | |
11353 | if (set->connectors[i]->encoder && | |
11354 | set->connectors[i]->encoder->crtc == set->crtc && | |
11355 | set->connectors[i]->dpms != DRM_MODE_DPMS_ON) | |
e3de42b6 ID |
11356 | return true; |
11357 | ||
11358 | return false; | |
11359 | } | |
11360 | ||
5e2b584e DV |
11361 | static void |
11362 | intel_set_config_compute_mode_changes(struct drm_mode_set *set, | |
11363 | struct intel_set_config *config) | |
11364 | { | |
11365 | ||
11366 | /* We should be able to check here if the fb has the same properties | |
11367 | * and then just flip_or_move it */ | |
2e57f47d CW |
11368 | if (is_crtc_connector_off(set)) { |
11369 | config->mode_changed = true; | |
f4510a27 | 11370 | } else if (set->crtc->primary->fb != set->fb) { |
3b150f08 MR |
11371 | /* |
11372 | * If we have no fb, we can only flip as long as the crtc is | |
11373 | * active, otherwise we need a full mode set. The crtc may | |
11374 | * be active if we've only disabled the primary plane, or | |
11375 | * in fastboot situations. | |
11376 | */ | |
f4510a27 | 11377 | if (set->crtc->primary->fb == NULL) { |
319d9827 JB |
11378 | struct intel_crtc *intel_crtc = |
11379 | to_intel_crtc(set->crtc); | |
11380 | ||
3b150f08 | 11381 | if (intel_crtc->active) { |
319d9827 JB |
11382 | DRM_DEBUG_KMS("crtc has no fb, will flip\n"); |
11383 | config->fb_changed = true; | |
11384 | } else { | |
11385 | DRM_DEBUG_KMS("inactive crtc, full mode set\n"); | |
11386 | config->mode_changed = true; | |
11387 | } | |
5e2b584e DV |
11388 | } else if (set->fb == NULL) { |
11389 | config->mode_changed = true; | |
72f4901e | 11390 | } else if (set->fb->pixel_format != |
f4510a27 | 11391 | set->crtc->primary->fb->pixel_format) { |
5e2b584e | 11392 | config->mode_changed = true; |
e3de42b6 | 11393 | } else { |
5e2b584e | 11394 | config->fb_changed = true; |
e3de42b6 | 11395 | } |
5e2b584e DV |
11396 | } |
11397 | ||
835c5873 | 11398 | if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y)) |
5e2b584e DV |
11399 | config->fb_changed = true; |
11400 | ||
11401 | if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) { | |
11402 | DRM_DEBUG_KMS("modes are different, full mode set\n"); | |
11403 | drm_mode_debug_printmodeline(&set->crtc->mode); | |
11404 | drm_mode_debug_printmodeline(set->mode); | |
11405 | config->mode_changed = true; | |
11406 | } | |
a1d95703 CW |
11407 | |
11408 | DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n", | |
11409 | set->crtc->base.id, config->mode_changed, config->fb_changed); | |
5e2b584e DV |
11410 | } |
11411 | ||
2e431051 | 11412 | static int |
9a935856 DV |
11413 | intel_modeset_stage_output_state(struct drm_device *dev, |
11414 | struct drm_mode_set *set, | |
11415 | struct intel_set_config *config) | |
50f56119 | 11416 | { |
9a935856 DV |
11417 | struct intel_connector *connector; |
11418 | struct intel_encoder *encoder; | |
7668851f | 11419 | struct intel_crtc *crtc; |
f3f08572 | 11420 | int ro; |
50f56119 | 11421 | |
9abdda74 | 11422 | /* The upper layers ensure that we either disable a crtc or have a list |
9a935856 DV |
11423 | * of connectors. For paranoia, double-check this. */ |
11424 | WARN_ON(!set->fb && (set->num_connectors != 0)); | |
11425 | WARN_ON(set->fb && (set->num_connectors == 0)); | |
11426 | ||
9a935856 DV |
11427 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11428 | base.head) { | |
11429 | /* Otherwise traverse passed in connector list and get encoders | |
11430 | * for them. */ | |
50f56119 | 11431 | for (ro = 0; ro < set->num_connectors; ro++) { |
9a935856 | 11432 | if (set->connectors[ro] == &connector->base) { |
0e32b39c | 11433 | connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe); |
50f56119 DV |
11434 | break; |
11435 | } | |
11436 | } | |
11437 | ||
9a935856 DV |
11438 | /* If we disable the crtc, disable all its connectors. Also, if |
11439 | * the connector is on the changing crtc but not on the new | |
11440 | * connector list, disable it. */ | |
11441 | if ((!set->fb || ro == set->num_connectors) && | |
11442 | connector->base.encoder && | |
11443 | connector->base.encoder->crtc == set->crtc) { | |
11444 | connector->new_encoder = NULL; | |
11445 | ||
11446 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n", | |
11447 | connector->base.base.id, | |
c23cc417 | 11448 | connector->base.name); |
9a935856 DV |
11449 | } |
11450 | ||
11451 | ||
11452 | if (&connector->new_encoder->base != connector->base.encoder) { | |
50f56119 | 11453 | DRM_DEBUG_KMS("encoder changed, full mode switch\n"); |
5e2b584e | 11454 | config->mode_changed = true; |
50f56119 DV |
11455 | } |
11456 | } | |
9a935856 | 11457 | /* connector->new_encoder is now updated for all connectors. */ |
50f56119 | 11458 | |
9a935856 | 11459 | /* Update crtc of enabled connectors. */ |
9a935856 DV |
11460 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11461 | base.head) { | |
7668851f VS |
11462 | struct drm_crtc *new_crtc; |
11463 | ||
9a935856 | 11464 | if (!connector->new_encoder) |
50f56119 DV |
11465 | continue; |
11466 | ||
9a935856 | 11467 | new_crtc = connector->new_encoder->base.crtc; |
50f56119 DV |
11468 | |
11469 | for (ro = 0; ro < set->num_connectors; ro++) { | |
9a935856 | 11470 | if (set->connectors[ro] == &connector->base) |
50f56119 DV |
11471 | new_crtc = set->crtc; |
11472 | } | |
11473 | ||
11474 | /* Make sure the new CRTC will work with the encoder */ | |
14509916 TR |
11475 | if (!drm_encoder_crtc_ok(&connector->new_encoder->base, |
11476 | new_crtc)) { | |
5e2b584e | 11477 | return -EINVAL; |
50f56119 | 11478 | } |
0e32b39c | 11479 | connector->new_encoder->new_crtc = to_intel_crtc(new_crtc); |
9a935856 DV |
11480 | |
11481 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n", | |
11482 | connector->base.base.id, | |
c23cc417 | 11483 | connector->base.name, |
9a935856 DV |
11484 | new_crtc->base.id); |
11485 | } | |
11486 | ||
11487 | /* Check for any encoders that needs to be disabled. */ | |
b2784e15 | 11488 | for_each_intel_encoder(dev, encoder) { |
5a65f358 | 11489 | int num_connectors = 0; |
9a935856 DV |
11490 | list_for_each_entry(connector, |
11491 | &dev->mode_config.connector_list, | |
11492 | base.head) { | |
11493 | if (connector->new_encoder == encoder) { | |
11494 | WARN_ON(!connector->new_encoder->new_crtc); | |
5a65f358 | 11495 | num_connectors++; |
9a935856 DV |
11496 | } |
11497 | } | |
5a65f358 PZ |
11498 | |
11499 | if (num_connectors == 0) | |
11500 | encoder->new_crtc = NULL; | |
11501 | else if (num_connectors > 1) | |
11502 | return -EINVAL; | |
11503 | ||
9a935856 DV |
11504 | /* Only now check for crtc changes so we don't miss encoders |
11505 | * that will be disabled. */ | |
11506 | if (&encoder->new_crtc->base != encoder->base.crtc) { | |
50f56119 | 11507 | DRM_DEBUG_KMS("crtc changed, full mode switch\n"); |
5e2b584e | 11508 | config->mode_changed = true; |
50f56119 DV |
11509 | } |
11510 | } | |
9a935856 | 11511 | /* Now we've also updated encoder->new_crtc for all encoders. */ |
0e32b39c DA |
11512 | list_for_each_entry(connector, &dev->mode_config.connector_list, |
11513 | base.head) { | |
11514 | if (connector->new_encoder) | |
11515 | if (connector->new_encoder != connector->encoder) | |
11516 | connector->encoder = connector->new_encoder; | |
11517 | } | |
d3fcc808 | 11518 | for_each_intel_crtc(dev, crtc) { |
7668851f VS |
11519 | crtc->new_enabled = false; |
11520 | ||
b2784e15 | 11521 | for_each_intel_encoder(dev, encoder) { |
7668851f VS |
11522 | if (encoder->new_crtc == crtc) { |
11523 | crtc->new_enabled = true; | |
11524 | break; | |
11525 | } | |
11526 | } | |
11527 | ||
11528 | if (crtc->new_enabled != crtc->base.enabled) { | |
11529 | DRM_DEBUG_KMS("crtc %sabled, full mode switch\n", | |
11530 | crtc->new_enabled ? "en" : "dis"); | |
11531 | config->mode_changed = true; | |
11532 | } | |
7bd0a8e7 VS |
11533 | |
11534 | if (crtc->new_enabled) | |
11535 | crtc->new_config = &crtc->config; | |
11536 | else | |
11537 | crtc->new_config = NULL; | |
7668851f VS |
11538 | } |
11539 | ||
2e431051 DV |
11540 | return 0; |
11541 | } | |
11542 | ||
7d00a1f5 VS |
11543 | static void disable_crtc_nofb(struct intel_crtc *crtc) |
11544 | { | |
11545 | struct drm_device *dev = crtc->base.dev; | |
11546 | struct intel_encoder *encoder; | |
11547 | struct intel_connector *connector; | |
11548 | ||
11549 | DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n", | |
11550 | pipe_name(crtc->pipe)); | |
11551 | ||
11552 | list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) { | |
11553 | if (connector->new_encoder && | |
11554 | connector->new_encoder->new_crtc == crtc) | |
11555 | connector->new_encoder = NULL; | |
11556 | } | |
11557 | ||
b2784e15 | 11558 | for_each_intel_encoder(dev, encoder) { |
7d00a1f5 VS |
11559 | if (encoder->new_crtc == crtc) |
11560 | encoder->new_crtc = NULL; | |
11561 | } | |
11562 | ||
11563 | crtc->new_enabled = false; | |
7bd0a8e7 | 11564 | crtc->new_config = NULL; |
7d00a1f5 VS |
11565 | } |
11566 | ||
2e431051 DV |
11567 | static int intel_crtc_set_config(struct drm_mode_set *set) |
11568 | { | |
11569 | struct drm_device *dev; | |
2e431051 DV |
11570 | struct drm_mode_set save_set; |
11571 | struct intel_set_config *config; | |
11572 | int ret; | |
2e431051 | 11573 | |
8d3e375e DV |
11574 | BUG_ON(!set); |
11575 | BUG_ON(!set->crtc); | |
11576 | BUG_ON(!set->crtc->helper_private); | |
2e431051 | 11577 | |
7e53f3a4 DV |
11578 | /* Enforce sane interface api - has been abused by the fb helper. */ |
11579 | BUG_ON(!set->mode && set->fb); | |
11580 | BUG_ON(set->fb && set->num_connectors == 0); | |
431e50f7 | 11581 | |
2e431051 DV |
11582 | if (set->fb) { |
11583 | DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n", | |
11584 | set->crtc->base.id, set->fb->base.id, | |
11585 | (int)set->num_connectors, set->x, set->y); | |
11586 | } else { | |
11587 | DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id); | |
2e431051 DV |
11588 | } |
11589 | ||
11590 | dev = set->crtc->dev; | |
11591 | ||
11592 | ret = -ENOMEM; | |
11593 | config = kzalloc(sizeof(*config), GFP_KERNEL); | |
11594 | if (!config) | |
11595 | goto out_config; | |
11596 | ||
11597 | ret = intel_set_config_save_state(dev, config); | |
11598 | if (ret) | |
11599 | goto out_config; | |
11600 | ||
11601 | save_set.crtc = set->crtc; | |
11602 | save_set.mode = &set->crtc->mode; | |
11603 | save_set.x = set->crtc->x; | |
11604 | save_set.y = set->crtc->y; | |
f4510a27 | 11605 | save_set.fb = set->crtc->primary->fb; |
2e431051 DV |
11606 | |
11607 | /* Compute whether we need a full modeset, only an fb base update or no | |
11608 | * change at all. In the future we might also check whether only the | |
11609 | * mode changed, e.g. for LVDS where we only change the panel fitter in | |
11610 | * such cases. */ | |
11611 | intel_set_config_compute_mode_changes(set, config); | |
11612 | ||
9a935856 | 11613 | ret = intel_modeset_stage_output_state(dev, set, config); |
2e431051 DV |
11614 | if (ret) |
11615 | goto fail; | |
11616 | ||
5e2b584e | 11617 | if (config->mode_changed) { |
c0c36b94 CW |
11618 | ret = intel_set_mode(set->crtc, set->mode, |
11619 | set->x, set->y, set->fb); | |
5e2b584e | 11620 | } else if (config->fb_changed) { |
3b150f08 MR |
11621 | struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc); |
11622 | ||
4878cae2 VS |
11623 | intel_crtc_wait_for_pending_flips(set->crtc); |
11624 | ||
4f660f49 | 11625 | ret = intel_pipe_set_base(set->crtc, |
94352cf9 | 11626 | set->x, set->y, set->fb); |
3b150f08 MR |
11627 | |
11628 | /* | |
11629 | * We need to make sure the primary plane is re-enabled if it | |
11630 | * has previously been turned off. | |
11631 | */ | |
11632 | if (!intel_crtc->primary_enabled && ret == 0) { | |
11633 | WARN_ON(!intel_crtc->active); | |
fdd508a6 | 11634 | intel_enable_primary_hw_plane(set->crtc->primary, set->crtc); |
3b150f08 MR |
11635 | } |
11636 | ||
7ca51a3a JB |
11637 | /* |
11638 | * In the fastboot case this may be our only check of the | |
11639 | * state after boot. It would be better to only do it on | |
11640 | * the first update, but we don't have a nice way of doing that | |
11641 | * (and really, set_config isn't used much for high freq page | |
11642 | * flipping, so increasing its cost here shouldn't be a big | |
11643 | * deal). | |
11644 | */ | |
d330a953 | 11645 | if (i915.fastboot && ret == 0) |
7ca51a3a | 11646 | intel_modeset_check_state(set->crtc->dev); |
50f56119 DV |
11647 | } |
11648 | ||
2d05eae1 | 11649 | if (ret) { |
bf67dfeb DV |
11650 | DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n", |
11651 | set->crtc->base.id, ret); | |
50f56119 | 11652 | fail: |
2d05eae1 | 11653 | intel_set_config_restore_state(dev, config); |
50f56119 | 11654 | |
7d00a1f5 VS |
11655 | /* |
11656 | * HACK: if the pipe was on, but we didn't have a framebuffer, | |
11657 | * force the pipe off to avoid oopsing in the modeset code | |
11658 | * due to fb==NULL. This should only happen during boot since | |
11659 | * we don't yet reconstruct the FB from the hardware state. | |
11660 | */ | |
11661 | if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb) | |
11662 | disable_crtc_nofb(to_intel_crtc(save_set.crtc)); | |
11663 | ||
2d05eae1 CW |
11664 | /* Try to restore the config */ |
11665 | if (config->mode_changed && | |
11666 | intel_set_mode(save_set.crtc, save_set.mode, | |
11667 | save_set.x, save_set.y, save_set.fb)) | |
11668 | DRM_ERROR("failed to restore config after modeset failure\n"); | |
11669 | } | |
50f56119 | 11670 | |
d9e55608 DV |
11671 | out_config: |
11672 | intel_set_config_free(config); | |
50f56119 DV |
11673 | return ret; |
11674 | } | |
f6e5b160 CW |
11675 | |
11676 | static const struct drm_crtc_funcs intel_crtc_funcs = { | |
f6e5b160 | 11677 | .gamma_set = intel_crtc_gamma_set, |
50f56119 | 11678 | .set_config = intel_crtc_set_config, |
f6e5b160 CW |
11679 | .destroy = intel_crtc_destroy, |
11680 | .page_flip = intel_crtc_page_flip, | |
11681 | }; | |
11682 | ||
5358901f DV |
11683 | static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv, |
11684 | struct intel_shared_dpll *pll, | |
11685 | struct intel_dpll_hw_state *hw_state) | |
ee7b9f93 | 11686 | { |
5358901f | 11687 | uint32_t val; |
ee7b9f93 | 11688 | |
bd2bb1b9 PZ |
11689 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_PLLS)) |
11690 | return false; | |
11691 | ||
5358901f | 11692 | val = I915_READ(PCH_DPLL(pll->id)); |
66e985c0 DV |
11693 | hw_state->dpll = val; |
11694 | hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); | |
11695 | hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); | |
5358901f DV |
11696 | |
11697 | return val & DPLL_VCO_ENABLE; | |
11698 | } | |
11699 | ||
15bdd4cf DV |
11700 | static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv, |
11701 | struct intel_shared_dpll *pll) | |
11702 | { | |
11703 | I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0); | |
11704 | I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1); | |
11705 | } | |
11706 | ||
e7b903d2 DV |
11707 | static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv, |
11708 | struct intel_shared_dpll *pll) | |
11709 | { | |
e7b903d2 | 11710 | /* PCH refclock must be enabled first */ |
89eff4be | 11711 | ibx_assert_pch_refclk_enabled(dev_priv); |
e7b903d2 | 11712 | |
15bdd4cf DV |
11713 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); |
11714 | ||
11715 | /* Wait for the clocks to stabilize. */ | |
11716 | POSTING_READ(PCH_DPLL(pll->id)); | |
11717 | udelay(150); | |
11718 | ||
11719 | /* The pixel multiplier can only be updated once the | |
11720 | * DPLL is enabled and the clocks are stable. | |
11721 | * | |
11722 | * So write it again. | |
11723 | */ | |
11724 | I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll); | |
11725 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
11726 | udelay(200); |
11727 | } | |
11728 | ||
11729 | static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv, | |
11730 | struct intel_shared_dpll *pll) | |
11731 | { | |
11732 | struct drm_device *dev = dev_priv->dev; | |
11733 | struct intel_crtc *crtc; | |
e7b903d2 DV |
11734 | |
11735 | /* Make sure no transcoder isn't still depending on us. */ | |
d3fcc808 | 11736 | for_each_intel_crtc(dev, crtc) { |
e7b903d2 DV |
11737 | if (intel_crtc_to_shared_dpll(crtc) == pll) |
11738 | assert_pch_transcoder_disabled(dev_priv, crtc->pipe); | |
ee7b9f93 JB |
11739 | } |
11740 | ||
15bdd4cf DV |
11741 | I915_WRITE(PCH_DPLL(pll->id), 0); |
11742 | POSTING_READ(PCH_DPLL(pll->id)); | |
e7b903d2 DV |
11743 | udelay(200); |
11744 | } | |
11745 | ||
46edb027 DV |
11746 | static char *ibx_pch_dpll_names[] = { |
11747 | "PCH DPLL A", | |
11748 | "PCH DPLL B", | |
11749 | }; | |
11750 | ||
7c74ade1 | 11751 | static void ibx_pch_dpll_init(struct drm_device *dev) |
ee7b9f93 | 11752 | { |
e7b903d2 | 11753 | struct drm_i915_private *dev_priv = dev->dev_private; |
ee7b9f93 JB |
11754 | int i; |
11755 | ||
7c74ade1 | 11756 | dev_priv->num_shared_dpll = 2; |
ee7b9f93 | 11757 | |
e72f9fbf | 11758 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
46edb027 DV |
11759 | dev_priv->shared_dplls[i].id = i; |
11760 | dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i]; | |
15bdd4cf | 11761 | dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set; |
e7b903d2 DV |
11762 | dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable; |
11763 | dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable; | |
5358901f DV |
11764 | dev_priv->shared_dplls[i].get_hw_state = |
11765 | ibx_pch_dpll_get_hw_state; | |
ee7b9f93 JB |
11766 | } |
11767 | } | |
11768 | ||
7c74ade1 DV |
11769 | static void intel_shared_dpll_init(struct drm_device *dev) |
11770 | { | |
e7b903d2 | 11771 | struct drm_i915_private *dev_priv = dev->dev_private; |
7c74ade1 | 11772 | |
9cd86933 DV |
11773 | if (HAS_DDI(dev)) |
11774 | intel_ddi_pll_init(dev); | |
11775 | else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) | |
7c74ade1 DV |
11776 | ibx_pch_dpll_init(dev); |
11777 | else | |
11778 | dev_priv->num_shared_dpll = 0; | |
11779 | ||
11780 | BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS); | |
7c74ade1 DV |
11781 | } |
11782 | ||
465c120c MR |
11783 | static int |
11784 | intel_primary_plane_disable(struct drm_plane *plane) | |
11785 | { | |
11786 | struct drm_device *dev = plane->dev; | |
465c120c MR |
11787 | struct intel_crtc *intel_crtc; |
11788 | ||
11789 | if (!plane->fb) | |
11790 | return 0; | |
11791 | ||
11792 | BUG_ON(!plane->crtc); | |
11793 | ||
11794 | intel_crtc = to_intel_crtc(plane->crtc); | |
11795 | ||
11796 | /* | |
11797 | * Even though we checked plane->fb above, it's still possible that | |
11798 | * the primary plane has been implicitly disabled because the crtc | |
11799 | * coordinates given weren't visible, or because we detected | |
11800 | * that it was 100% covered by a sprite plane. Or, the CRTC may be | |
11801 | * off and we've set a fb, but haven't actually turned on the CRTC yet. | |
11802 | * In either case, we need to unpin the FB and let the fb pointer get | |
11803 | * updated, but otherwise we don't need to touch the hardware. | |
11804 | */ | |
11805 | if (!intel_crtc->primary_enabled) | |
11806 | goto disable_unpin; | |
11807 | ||
11808 | intel_crtc_wait_for_pending_flips(plane->crtc); | |
fdd508a6 VS |
11809 | intel_disable_primary_hw_plane(plane, plane->crtc); |
11810 | ||
465c120c | 11811 | disable_unpin: |
4c34574f | 11812 | mutex_lock(&dev->struct_mutex); |
2ff8fde1 | 11813 | i915_gem_track_fb(intel_fb_obj(plane->fb), NULL, |
a071fa00 | 11814 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); |
2ff8fde1 | 11815 | intel_unpin_fb_obj(intel_fb_obj(plane->fb)); |
4c34574f | 11816 | mutex_unlock(&dev->struct_mutex); |
465c120c MR |
11817 | plane->fb = NULL; |
11818 | ||
11819 | return 0; | |
11820 | } | |
11821 | ||
11822 | static int | |
3c692a41 GP |
11823 | intel_check_primary_plane(struct drm_plane *plane, |
11824 | struct intel_plane_state *state) | |
11825 | { | |
11826 | struct drm_crtc *crtc = state->crtc; | |
11827 | struct drm_framebuffer *fb = state->fb; | |
11828 | struct drm_rect *dest = &state->dst; | |
11829 | struct drm_rect *src = &state->src; | |
11830 | const struct drm_rect *clip = &state->clip; | |
11831 | ||
11832 | return drm_plane_helper_check_update(plane, crtc, fb, | |
11833 | src, dest, clip, | |
11834 | DRM_PLANE_HELPER_NO_SCALING, | |
11835 | DRM_PLANE_HELPER_NO_SCALING, | |
11836 | false, true, &state->visible); | |
11837 | } | |
11838 | ||
11839 | static int | |
11840 | intel_commit_primary_plane(struct drm_plane *plane, | |
11841 | struct intel_plane_state *state) | |
465c120c | 11842 | { |
3c692a41 GP |
11843 | struct drm_crtc *crtc = state->crtc; |
11844 | struct drm_framebuffer *fb = state->fb; | |
465c120c | 11845 | struct drm_device *dev = crtc->dev; |
48404c1e | 11846 | struct drm_i915_private *dev_priv = dev->dev_private; |
465c120c | 11847 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2ff8fde1 MR |
11848 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
11849 | struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); | |
ce54d85a | 11850 | struct intel_plane *intel_plane = to_intel_plane(plane); |
3c692a41 | 11851 | struct drm_rect *src = &state->src; |
465c120c MR |
11852 | int ret; |
11853 | ||
465c120c MR |
11854 | intel_crtc_wait_for_pending_flips(crtc); |
11855 | ||
11856 | /* | |
11857 | * If clipping results in a non-visible primary plane, we'll disable | |
11858 | * the primary plane. Note that this is a bit different than what | |
11859 | * happens if userspace explicitly disables the plane by passing fb=0 | |
11860 | * because plane->fb still gets set and pinned. | |
11861 | */ | |
3c692a41 | 11862 | if (!state->visible) { |
4c34574f MR |
11863 | mutex_lock(&dev->struct_mutex); |
11864 | ||
465c120c MR |
11865 | /* |
11866 | * Try to pin the new fb first so that we can bail out if we | |
11867 | * fail. | |
11868 | */ | |
11869 | if (plane->fb != fb) { | |
a071fa00 | 11870 | ret = intel_pin_and_fence_fb_obj(dev, obj, NULL); |
4c34574f MR |
11871 | if (ret) { |
11872 | mutex_unlock(&dev->struct_mutex); | |
465c120c | 11873 | return ret; |
4c34574f | 11874 | } |
465c120c MR |
11875 | } |
11876 | ||
a071fa00 DV |
11877 | i915_gem_track_fb(old_obj, obj, |
11878 | INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe)); | |
11879 | ||
465c120c | 11880 | if (intel_crtc->primary_enabled) |
fdd508a6 | 11881 | intel_disable_primary_hw_plane(plane, crtc); |
465c120c MR |
11882 | |
11883 | ||
11884 | if (plane->fb != fb) | |
11885 | if (plane->fb) | |
a071fa00 | 11886 | intel_unpin_fb_obj(old_obj); |
465c120c | 11887 | |
4c34574f MR |
11888 | mutex_unlock(&dev->struct_mutex); |
11889 | ||
ce54d85a | 11890 | } else { |
48404c1e SJ |
11891 | if (intel_crtc && intel_crtc->active && |
11892 | intel_crtc->primary_enabled) { | |
11893 | /* | |
11894 | * FBC does not work on some platforms for rotated | |
11895 | * planes, so disable it when rotation is not 0 and | |
11896 | * update it when rotation is set back to 0. | |
11897 | * | |
11898 | * FIXME: This is redundant with the fbc update done in | |
11899 | * the primary plane enable function except that that | |
11900 | * one is done too late. We eventually need to unify | |
11901 | * this. | |
11902 | */ | |
11903 | if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && | |
11904 | dev_priv->fbc.plane == intel_crtc->plane && | |
11905 | intel_plane->rotation != BIT(DRM_ROTATE_0)) { | |
11906 | intel_disable_fbc(dev); | |
11907 | } | |
11908 | } | |
3c692a41 | 11909 | ret = intel_pipe_set_base(crtc, src->x1, src->y1, fb); |
ce54d85a SJ |
11910 | if (ret) |
11911 | return ret; | |
465c120c | 11912 | |
ce54d85a SJ |
11913 | if (!intel_crtc->primary_enabled) |
11914 | intel_enable_primary_hw_plane(plane, crtc); | |
11915 | } | |
465c120c | 11916 | |
3c692a41 GP |
11917 | intel_plane->crtc_x = state->orig_dst.x1; |
11918 | intel_plane->crtc_y = state->orig_dst.y1; | |
11919 | intel_plane->crtc_w = drm_rect_width(&state->orig_dst); | |
11920 | intel_plane->crtc_h = drm_rect_height(&state->orig_dst); | |
11921 | intel_plane->src_x = state->orig_src.x1; | |
11922 | intel_plane->src_y = state->orig_src.y1; | |
11923 | intel_plane->src_w = drm_rect_width(&state->orig_src); | |
11924 | intel_plane->src_h = drm_rect_height(&state->orig_src); | |
ce54d85a | 11925 | intel_plane->obj = obj; |
465c120c MR |
11926 | |
11927 | return 0; | |
11928 | } | |
11929 | ||
3c692a41 GP |
11930 | static int |
11931 | intel_primary_plane_setplane(struct drm_plane *plane, struct drm_crtc *crtc, | |
11932 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
11933 | unsigned int crtc_w, unsigned int crtc_h, | |
11934 | uint32_t src_x, uint32_t src_y, | |
11935 | uint32_t src_w, uint32_t src_h) | |
11936 | { | |
11937 | struct intel_plane_state state; | |
11938 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
11939 | int ret; | |
11940 | ||
11941 | state.crtc = crtc; | |
11942 | state.fb = fb; | |
11943 | ||
11944 | /* sample coordinates in 16.16 fixed point */ | |
11945 | state.src.x1 = src_x; | |
11946 | state.src.x2 = src_x + src_w; | |
11947 | state.src.y1 = src_y; | |
11948 | state.src.y2 = src_y + src_h; | |
11949 | ||
11950 | /* integer pixels */ | |
11951 | state.dst.x1 = crtc_x; | |
11952 | state.dst.x2 = crtc_x + crtc_w; | |
11953 | state.dst.y1 = crtc_y; | |
11954 | state.dst.y2 = crtc_y + crtc_h; | |
11955 | ||
11956 | state.clip.x1 = 0; | |
11957 | state.clip.y1 = 0; | |
11958 | state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0; | |
11959 | state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0; | |
11960 | ||
11961 | state.orig_src = state.src; | |
11962 | state.orig_dst = state.dst; | |
11963 | ||
11964 | ret = intel_check_primary_plane(plane, &state); | |
11965 | if (ret) | |
11966 | return ret; | |
11967 | ||
11968 | intel_commit_primary_plane(plane, &state); | |
11969 | ||
11970 | return 0; | |
11971 | } | |
11972 | ||
3d7d6510 MR |
11973 | /* Common destruction function for both primary and cursor planes */ |
11974 | static void intel_plane_destroy(struct drm_plane *plane) | |
465c120c MR |
11975 | { |
11976 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
11977 | drm_plane_cleanup(plane); | |
11978 | kfree(intel_plane); | |
11979 | } | |
11980 | ||
11981 | static const struct drm_plane_funcs intel_primary_plane_funcs = { | |
11982 | .update_plane = intel_primary_plane_setplane, | |
11983 | .disable_plane = intel_primary_plane_disable, | |
3d7d6510 | 11984 | .destroy = intel_plane_destroy, |
48404c1e | 11985 | .set_property = intel_plane_set_property |
465c120c MR |
11986 | }; |
11987 | ||
11988 | static struct drm_plane *intel_primary_plane_create(struct drm_device *dev, | |
11989 | int pipe) | |
11990 | { | |
11991 | struct intel_plane *primary; | |
11992 | const uint32_t *intel_primary_formats; | |
11993 | int num_formats; | |
11994 | ||
11995 | primary = kzalloc(sizeof(*primary), GFP_KERNEL); | |
11996 | if (primary == NULL) | |
11997 | return NULL; | |
11998 | ||
11999 | primary->can_scale = false; | |
12000 | primary->max_downscale = 1; | |
12001 | primary->pipe = pipe; | |
12002 | primary->plane = pipe; | |
48404c1e | 12003 | primary->rotation = BIT(DRM_ROTATE_0); |
465c120c MR |
12004 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) |
12005 | primary->plane = !pipe; | |
12006 | ||
12007 | if (INTEL_INFO(dev)->gen <= 3) { | |
12008 | intel_primary_formats = intel_primary_formats_gen2; | |
12009 | num_formats = ARRAY_SIZE(intel_primary_formats_gen2); | |
12010 | } else { | |
12011 | intel_primary_formats = intel_primary_formats_gen4; | |
12012 | num_formats = ARRAY_SIZE(intel_primary_formats_gen4); | |
12013 | } | |
12014 | ||
12015 | drm_universal_plane_init(dev, &primary->base, 0, | |
12016 | &intel_primary_plane_funcs, | |
12017 | intel_primary_formats, num_formats, | |
12018 | DRM_PLANE_TYPE_PRIMARY); | |
48404c1e SJ |
12019 | |
12020 | if (INTEL_INFO(dev)->gen >= 4) { | |
12021 | if (!dev->mode_config.rotation_property) | |
12022 | dev->mode_config.rotation_property = | |
12023 | drm_mode_create_rotation_property(dev, | |
12024 | BIT(DRM_ROTATE_0) | | |
12025 | BIT(DRM_ROTATE_180)); | |
12026 | if (dev->mode_config.rotation_property) | |
12027 | drm_object_attach_property(&primary->base.base, | |
12028 | dev->mode_config.rotation_property, | |
12029 | primary->rotation); | |
12030 | } | |
12031 | ||
465c120c MR |
12032 | return &primary->base; |
12033 | } | |
12034 | ||
3d7d6510 MR |
12035 | static int |
12036 | intel_cursor_plane_disable(struct drm_plane *plane) | |
12037 | { | |
12038 | if (!plane->fb) | |
12039 | return 0; | |
12040 | ||
12041 | BUG_ON(!plane->crtc); | |
12042 | ||
12043 | return intel_crtc_cursor_set_obj(plane->crtc, NULL, 0, 0); | |
12044 | } | |
12045 | ||
12046 | static int | |
852e787c GP |
12047 | intel_check_cursor_plane(struct drm_plane *plane, |
12048 | struct intel_plane_state *state) | |
3d7d6510 | 12049 | { |
852e787c GP |
12050 | struct drm_crtc *crtc = state->crtc; |
12051 | struct drm_framebuffer *fb = state->fb; | |
12052 | struct drm_rect *dest = &state->dst; | |
12053 | struct drm_rect *src = &state->src; | |
12054 | const struct drm_rect *clip = &state->clip; | |
3d7d6510 | 12055 | |
852e787c GP |
12056 | return drm_plane_helper_check_update(plane, crtc, fb, |
12057 | src, dest, clip, | |
3d7d6510 MR |
12058 | DRM_PLANE_HELPER_NO_SCALING, |
12059 | DRM_PLANE_HELPER_NO_SCALING, | |
852e787c GP |
12060 | true, true, &state->visible); |
12061 | } | |
3d7d6510 | 12062 | |
852e787c GP |
12063 | static int |
12064 | intel_commit_cursor_plane(struct drm_plane *plane, | |
12065 | struct intel_plane_state *state) | |
12066 | { | |
12067 | struct drm_crtc *crtc = state->crtc; | |
12068 | struct drm_framebuffer *fb = state->fb; | |
12069 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12070 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
12071 | struct drm_i915_gem_object *obj = intel_fb->obj; | |
12072 | int crtc_w, crtc_h; | |
12073 | ||
12074 | crtc->cursor_x = state->orig_dst.x1; | |
12075 | crtc->cursor_y = state->orig_dst.y1; | |
3d7d6510 | 12076 | if (fb != crtc->cursor->fb) { |
852e787c GP |
12077 | crtc_w = drm_rect_width(&state->orig_dst); |
12078 | crtc_h = drm_rect_height(&state->orig_dst); | |
3d7d6510 MR |
12079 | return intel_crtc_cursor_set_obj(crtc, obj, crtc_w, crtc_h); |
12080 | } else { | |
852e787c | 12081 | intel_crtc_update_cursor(crtc, state->visible); |
4ed91096 DV |
12082 | |
12083 | intel_frontbuffer_flip(crtc->dev, | |
12084 | INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe)); | |
12085 | ||
3d7d6510 MR |
12086 | return 0; |
12087 | } | |
12088 | } | |
852e787c GP |
12089 | |
12090 | static int | |
12091 | intel_cursor_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, | |
12092 | struct drm_framebuffer *fb, int crtc_x, int crtc_y, | |
12093 | unsigned int crtc_w, unsigned int crtc_h, | |
12094 | uint32_t src_x, uint32_t src_y, | |
12095 | uint32_t src_w, uint32_t src_h) | |
12096 | { | |
12097 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
12098 | struct intel_plane_state state; | |
12099 | int ret; | |
12100 | ||
12101 | state.crtc = crtc; | |
12102 | state.fb = fb; | |
12103 | ||
12104 | /* sample coordinates in 16.16 fixed point */ | |
12105 | state.src.x1 = src_x; | |
12106 | state.src.x2 = src_x + src_w; | |
12107 | state.src.y1 = src_y; | |
12108 | state.src.y2 = src_y + src_h; | |
12109 | ||
12110 | /* integer pixels */ | |
12111 | state.dst.x1 = crtc_x; | |
12112 | state.dst.x2 = crtc_x + crtc_w; | |
12113 | state.dst.y1 = crtc_y; | |
12114 | state.dst.y2 = crtc_y + crtc_h; | |
12115 | ||
12116 | state.clip.x1 = 0; | |
12117 | state.clip.y1 = 0; | |
12118 | state.clip.x2 = intel_crtc->active ? intel_crtc->config.pipe_src_w : 0; | |
12119 | state.clip.y2 = intel_crtc->active ? intel_crtc->config.pipe_src_h : 0; | |
12120 | ||
12121 | state.orig_src = state.src; | |
12122 | state.orig_dst = state.dst; | |
12123 | ||
12124 | ret = intel_check_cursor_plane(plane, &state); | |
12125 | if (ret) | |
12126 | return ret; | |
12127 | ||
12128 | return intel_commit_cursor_plane(plane, &state); | |
12129 | } | |
12130 | ||
3d7d6510 MR |
12131 | static const struct drm_plane_funcs intel_cursor_plane_funcs = { |
12132 | .update_plane = intel_cursor_plane_update, | |
12133 | .disable_plane = intel_cursor_plane_disable, | |
12134 | .destroy = intel_plane_destroy, | |
12135 | }; | |
12136 | ||
12137 | static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev, | |
12138 | int pipe) | |
12139 | { | |
12140 | struct intel_plane *cursor; | |
12141 | ||
12142 | cursor = kzalloc(sizeof(*cursor), GFP_KERNEL); | |
12143 | if (cursor == NULL) | |
12144 | return NULL; | |
12145 | ||
12146 | cursor->can_scale = false; | |
12147 | cursor->max_downscale = 1; | |
12148 | cursor->pipe = pipe; | |
12149 | cursor->plane = pipe; | |
12150 | ||
12151 | drm_universal_plane_init(dev, &cursor->base, 0, | |
12152 | &intel_cursor_plane_funcs, | |
12153 | intel_cursor_formats, | |
12154 | ARRAY_SIZE(intel_cursor_formats), | |
12155 | DRM_PLANE_TYPE_CURSOR); | |
12156 | return &cursor->base; | |
12157 | } | |
12158 | ||
b358d0a6 | 12159 | static void intel_crtc_init(struct drm_device *dev, int pipe) |
79e53945 | 12160 | { |
fbee40df | 12161 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 12162 | struct intel_crtc *intel_crtc; |
3d7d6510 MR |
12163 | struct drm_plane *primary = NULL; |
12164 | struct drm_plane *cursor = NULL; | |
465c120c | 12165 | int i, ret; |
79e53945 | 12166 | |
955382f3 | 12167 | intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL); |
79e53945 JB |
12168 | if (intel_crtc == NULL) |
12169 | return; | |
12170 | ||
465c120c | 12171 | primary = intel_primary_plane_create(dev, pipe); |
3d7d6510 MR |
12172 | if (!primary) |
12173 | goto fail; | |
12174 | ||
12175 | cursor = intel_cursor_plane_create(dev, pipe); | |
12176 | if (!cursor) | |
12177 | goto fail; | |
12178 | ||
465c120c | 12179 | ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary, |
3d7d6510 MR |
12180 | cursor, &intel_crtc_funcs); |
12181 | if (ret) | |
12182 | goto fail; | |
79e53945 JB |
12183 | |
12184 | drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256); | |
79e53945 JB |
12185 | for (i = 0; i < 256; i++) { |
12186 | intel_crtc->lut_r[i] = i; | |
12187 | intel_crtc->lut_g[i] = i; | |
12188 | intel_crtc->lut_b[i] = i; | |
12189 | } | |
12190 | ||
1f1c2e24 VS |
12191 | /* |
12192 | * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port | |
8c0f92e1 | 12193 | * is hooked to pipe B. Hence we want plane A feeding pipe B. |
1f1c2e24 | 12194 | */ |
80824003 JB |
12195 | intel_crtc->pipe = pipe; |
12196 | intel_crtc->plane = pipe; | |
3a77c4c4 | 12197 | if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) { |
28c97730 | 12198 | DRM_DEBUG_KMS("swapping pipes & planes for FBC\n"); |
e2e767ab | 12199 | intel_crtc->plane = !pipe; |
80824003 JB |
12200 | } |
12201 | ||
4b0e333e CW |
12202 | intel_crtc->cursor_base = ~0; |
12203 | intel_crtc->cursor_cntl = ~0; | |
dc41c154 | 12204 | intel_crtc->cursor_size = ~0; |
8d7849db | 12205 | |
22fd0fab JB |
12206 | BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) || |
12207 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL); | |
12208 | dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base; | |
12209 | dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base; | |
12210 | ||
79e53945 | 12211 | drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs); |
87b6b101 DV |
12212 | |
12213 | WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe); | |
3d7d6510 MR |
12214 | return; |
12215 | ||
12216 | fail: | |
12217 | if (primary) | |
12218 | drm_plane_cleanup(primary); | |
12219 | if (cursor) | |
12220 | drm_plane_cleanup(cursor); | |
12221 | kfree(intel_crtc); | |
79e53945 JB |
12222 | } |
12223 | ||
752aa88a JB |
12224 | enum pipe intel_get_pipe_from_connector(struct intel_connector *connector) |
12225 | { | |
12226 | struct drm_encoder *encoder = connector->base.encoder; | |
6e9f798d | 12227 | struct drm_device *dev = connector->base.dev; |
752aa88a | 12228 | |
51fd371b | 12229 | WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
752aa88a JB |
12230 | |
12231 | if (!encoder) | |
12232 | return INVALID_PIPE; | |
12233 | ||
12234 | return to_intel_crtc(encoder->crtc)->pipe; | |
12235 | } | |
12236 | ||
08d7b3d1 | 12237 | int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data, |
05394f39 | 12238 | struct drm_file *file) |
08d7b3d1 | 12239 | { |
08d7b3d1 | 12240 | struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data; |
7707e653 | 12241 | struct drm_crtc *drmmode_crtc; |
c05422d5 | 12242 | struct intel_crtc *crtc; |
08d7b3d1 | 12243 | |
1cff8f6b DV |
12244 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
12245 | return -ENODEV; | |
08d7b3d1 | 12246 | |
7707e653 | 12247 | drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id); |
08d7b3d1 | 12248 | |
7707e653 | 12249 | if (!drmmode_crtc) { |
08d7b3d1 | 12250 | DRM_ERROR("no such CRTC id\n"); |
3f2c2057 | 12251 | return -ENOENT; |
08d7b3d1 CW |
12252 | } |
12253 | ||
7707e653 | 12254 | crtc = to_intel_crtc(drmmode_crtc); |
c05422d5 | 12255 | pipe_from_crtc_id->pipe = crtc->pipe; |
08d7b3d1 | 12256 | |
c05422d5 | 12257 | return 0; |
08d7b3d1 CW |
12258 | } |
12259 | ||
66a9278e | 12260 | static int intel_encoder_clones(struct intel_encoder *encoder) |
79e53945 | 12261 | { |
66a9278e DV |
12262 | struct drm_device *dev = encoder->base.dev; |
12263 | struct intel_encoder *source_encoder; | |
79e53945 | 12264 | int index_mask = 0; |
79e53945 JB |
12265 | int entry = 0; |
12266 | ||
b2784e15 | 12267 | for_each_intel_encoder(dev, source_encoder) { |
bc079e8b | 12268 | if (encoders_cloneable(encoder, source_encoder)) |
66a9278e DV |
12269 | index_mask |= (1 << entry); |
12270 | ||
79e53945 JB |
12271 | entry++; |
12272 | } | |
4ef69c7a | 12273 | |
79e53945 JB |
12274 | return index_mask; |
12275 | } | |
12276 | ||
4d302442 CW |
12277 | static bool has_edp_a(struct drm_device *dev) |
12278 | { | |
12279 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12280 | ||
12281 | if (!IS_MOBILE(dev)) | |
12282 | return false; | |
12283 | ||
12284 | if ((I915_READ(DP_A) & DP_DETECTED) == 0) | |
12285 | return false; | |
12286 | ||
e3589908 | 12287 | if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE)) |
4d302442 CW |
12288 | return false; |
12289 | ||
12290 | return true; | |
12291 | } | |
12292 | ||
ba0fbca4 DL |
12293 | const char *intel_output_name(int output) |
12294 | { | |
12295 | static const char *names[] = { | |
12296 | [INTEL_OUTPUT_UNUSED] = "Unused", | |
12297 | [INTEL_OUTPUT_ANALOG] = "Analog", | |
12298 | [INTEL_OUTPUT_DVO] = "DVO", | |
12299 | [INTEL_OUTPUT_SDVO] = "SDVO", | |
12300 | [INTEL_OUTPUT_LVDS] = "LVDS", | |
12301 | [INTEL_OUTPUT_TVOUT] = "TV", | |
12302 | [INTEL_OUTPUT_HDMI] = "HDMI", | |
12303 | [INTEL_OUTPUT_DISPLAYPORT] = "DisplayPort", | |
12304 | [INTEL_OUTPUT_EDP] = "eDP", | |
12305 | [INTEL_OUTPUT_DSI] = "DSI", | |
12306 | [INTEL_OUTPUT_UNKNOWN] = "Unknown", | |
12307 | }; | |
12308 | ||
12309 | if (output < 0 || output >= ARRAY_SIZE(names) || !names[output]) | |
12310 | return "Invalid"; | |
12311 | ||
12312 | return names[output]; | |
12313 | } | |
12314 | ||
84b4e042 JB |
12315 | static bool intel_crt_present(struct drm_device *dev) |
12316 | { | |
12317 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12318 | ||
12319 | if (IS_ULT(dev)) | |
12320 | return false; | |
12321 | ||
12322 | if (IS_CHERRYVIEW(dev)) | |
12323 | return false; | |
12324 | ||
12325 | if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support) | |
12326 | return false; | |
12327 | ||
12328 | return true; | |
12329 | } | |
12330 | ||
79e53945 JB |
12331 | static void intel_setup_outputs(struct drm_device *dev) |
12332 | { | |
725e30ad | 12333 | struct drm_i915_private *dev_priv = dev->dev_private; |
4ef69c7a | 12334 | struct intel_encoder *encoder; |
cb0953d7 | 12335 | bool dpd_is_edp = false; |
79e53945 | 12336 | |
c9093354 | 12337 | intel_lvds_init(dev); |
79e53945 | 12338 | |
84b4e042 | 12339 | if (intel_crt_present(dev)) |
79935fca | 12340 | intel_crt_init(dev); |
cb0953d7 | 12341 | |
affa9354 | 12342 | if (HAS_DDI(dev)) { |
0e72a5b5 ED |
12343 | int found; |
12344 | ||
12345 | /* Haswell uses DDI functions to detect digital outputs */ | |
12346 | found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED; | |
12347 | /* DDI A only supports eDP */ | |
12348 | if (found) | |
12349 | intel_ddi_init(dev, PORT_A); | |
12350 | ||
12351 | /* DDI B, C and D detection is indicated by the SFUSE_STRAP | |
12352 | * register */ | |
12353 | found = I915_READ(SFUSE_STRAP); | |
12354 | ||
12355 | if (found & SFUSE_STRAP_DDIB_DETECTED) | |
12356 | intel_ddi_init(dev, PORT_B); | |
12357 | if (found & SFUSE_STRAP_DDIC_DETECTED) | |
12358 | intel_ddi_init(dev, PORT_C); | |
12359 | if (found & SFUSE_STRAP_DDID_DETECTED) | |
12360 | intel_ddi_init(dev, PORT_D); | |
12361 | } else if (HAS_PCH_SPLIT(dev)) { | |
cb0953d7 | 12362 | int found; |
5d8a7752 | 12363 | dpd_is_edp = intel_dp_is_edp(dev, PORT_D); |
270b3042 DV |
12364 | |
12365 | if (has_edp_a(dev)) | |
12366 | intel_dp_init(dev, DP_A, PORT_A); | |
cb0953d7 | 12367 | |
dc0fa718 | 12368 | if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) { |
461ed3ca | 12369 | /* PCH SDVOB multiplex with HDMIB */ |
eef4eacb | 12370 | found = intel_sdvo_init(dev, PCH_SDVOB, true); |
30ad48b7 | 12371 | if (!found) |
e2debe91 | 12372 | intel_hdmi_init(dev, PCH_HDMIB, PORT_B); |
5eb08b69 | 12373 | if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED)) |
ab9d7c30 | 12374 | intel_dp_init(dev, PCH_DP_B, PORT_B); |
30ad48b7 ZW |
12375 | } |
12376 | ||
dc0fa718 | 12377 | if (I915_READ(PCH_HDMIC) & SDVO_DETECTED) |
e2debe91 | 12378 | intel_hdmi_init(dev, PCH_HDMIC, PORT_C); |
30ad48b7 | 12379 | |
dc0fa718 | 12380 | if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED) |
e2debe91 | 12381 | intel_hdmi_init(dev, PCH_HDMID, PORT_D); |
30ad48b7 | 12382 | |
5eb08b69 | 12383 | if (I915_READ(PCH_DP_C) & DP_DETECTED) |
ab9d7c30 | 12384 | intel_dp_init(dev, PCH_DP_C, PORT_C); |
5eb08b69 | 12385 | |
270b3042 | 12386 | if (I915_READ(PCH_DP_D) & DP_DETECTED) |
ab9d7c30 | 12387 | intel_dp_init(dev, PCH_DP_D, PORT_D); |
4a87d65d | 12388 | } else if (IS_VALLEYVIEW(dev)) { |
585a94b8 AB |
12389 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) { |
12390 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB, | |
12391 | PORT_B); | |
12392 | if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED) | |
12393 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B); | |
12394 | } | |
12395 | ||
6f6005a5 JB |
12396 | if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) { |
12397 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC, | |
12398 | PORT_C); | |
12399 | if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED) | |
5d8a7752 | 12400 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C); |
6f6005a5 | 12401 | } |
19c03924 | 12402 | |
9418c1f1 VS |
12403 | if (IS_CHERRYVIEW(dev)) { |
12404 | if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED) { | |
12405 | intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID, | |
12406 | PORT_D); | |
12407 | if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED) | |
12408 | intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D); | |
12409 | } | |
12410 | } | |
12411 | ||
3cfca973 | 12412 | intel_dsi_init(dev); |
103a196f | 12413 | } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) { |
27185ae1 | 12414 | bool found = false; |
7d57382e | 12415 | |
e2debe91 | 12416 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 12417 | DRM_DEBUG_KMS("probing SDVOB\n"); |
e2debe91 | 12418 | found = intel_sdvo_init(dev, GEN3_SDVOB, true); |
b01f2c3a JB |
12419 | if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) { |
12420 | DRM_DEBUG_KMS("probing HDMI on SDVOB\n"); | |
e2debe91 | 12421 | intel_hdmi_init(dev, GEN4_HDMIB, PORT_B); |
b01f2c3a | 12422 | } |
27185ae1 | 12423 | |
e7281eab | 12424 | if (!found && SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 12425 | intel_dp_init(dev, DP_B, PORT_B); |
725e30ad | 12426 | } |
13520b05 KH |
12427 | |
12428 | /* Before G4X SDVOC doesn't have its own detect register */ | |
13520b05 | 12429 | |
e2debe91 | 12430 | if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) { |
b01f2c3a | 12431 | DRM_DEBUG_KMS("probing SDVOC\n"); |
e2debe91 | 12432 | found = intel_sdvo_init(dev, GEN3_SDVOC, false); |
b01f2c3a | 12433 | } |
27185ae1 | 12434 | |
e2debe91 | 12435 | if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) { |
27185ae1 | 12436 | |
b01f2c3a JB |
12437 | if (SUPPORTS_INTEGRATED_HDMI(dev)) { |
12438 | DRM_DEBUG_KMS("probing HDMI on SDVOC\n"); | |
e2debe91 | 12439 | intel_hdmi_init(dev, GEN4_HDMIC, PORT_C); |
b01f2c3a | 12440 | } |
e7281eab | 12441 | if (SUPPORTS_INTEGRATED_DP(dev)) |
ab9d7c30 | 12442 | intel_dp_init(dev, DP_C, PORT_C); |
725e30ad | 12443 | } |
27185ae1 | 12444 | |
b01f2c3a | 12445 | if (SUPPORTS_INTEGRATED_DP(dev) && |
e7281eab | 12446 | (I915_READ(DP_D) & DP_DETECTED)) |
ab9d7c30 | 12447 | intel_dp_init(dev, DP_D, PORT_D); |
bad720ff | 12448 | } else if (IS_GEN2(dev)) |
79e53945 JB |
12449 | intel_dvo_init(dev); |
12450 | ||
103a196f | 12451 | if (SUPPORTS_TV(dev)) |
79e53945 JB |
12452 | intel_tv_init(dev); |
12453 | ||
7c8f8a70 RV |
12454 | intel_edp_psr_init(dev); |
12455 | ||
b2784e15 | 12456 | for_each_intel_encoder(dev, encoder) { |
4ef69c7a CW |
12457 | encoder->base.possible_crtcs = encoder->crtc_mask; |
12458 | encoder->base.possible_clones = | |
66a9278e | 12459 | intel_encoder_clones(encoder); |
79e53945 | 12460 | } |
47356eb6 | 12461 | |
dde86e2d | 12462 | intel_init_pch_refclk(dev); |
270b3042 DV |
12463 | |
12464 | drm_helper_move_panel_connectors_to_head(dev); | |
79e53945 JB |
12465 | } |
12466 | ||
12467 | static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb) | |
12468 | { | |
60a5ca01 | 12469 | struct drm_device *dev = fb->dev; |
79e53945 | 12470 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); |
79e53945 | 12471 | |
ef2d633e | 12472 | drm_framebuffer_cleanup(fb); |
60a5ca01 | 12473 | mutex_lock(&dev->struct_mutex); |
ef2d633e | 12474 | WARN_ON(!intel_fb->obj->framebuffer_references--); |
60a5ca01 VS |
12475 | drm_gem_object_unreference(&intel_fb->obj->base); |
12476 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
12477 | kfree(intel_fb); |
12478 | } | |
12479 | ||
12480 | static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb, | |
05394f39 | 12481 | struct drm_file *file, |
79e53945 JB |
12482 | unsigned int *handle) |
12483 | { | |
12484 | struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb); | |
05394f39 | 12485 | struct drm_i915_gem_object *obj = intel_fb->obj; |
79e53945 | 12486 | |
05394f39 | 12487 | return drm_gem_handle_create(file, &obj->base, handle); |
79e53945 JB |
12488 | } |
12489 | ||
12490 | static const struct drm_framebuffer_funcs intel_fb_funcs = { | |
12491 | .destroy = intel_user_framebuffer_destroy, | |
12492 | .create_handle = intel_user_framebuffer_create_handle, | |
12493 | }; | |
12494 | ||
b5ea642a DV |
12495 | static int intel_framebuffer_init(struct drm_device *dev, |
12496 | struct intel_framebuffer *intel_fb, | |
12497 | struct drm_mode_fb_cmd2 *mode_cmd, | |
12498 | struct drm_i915_gem_object *obj) | |
79e53945 | 12499 | { |
a57ce0b2 | 12500 | int aligned_height; |
a35cdaa0 | 12501 | int pitch_limit; |
79e53945 JB |
12502 | int ret; |
12503 | ||
dd4916c5 DV |
12504 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
12505 | ||
c16ed4be CW |
12506 | if (obj->tiling_mode == I915_TILING_Y) { |
12507 | DRM_DEBUG("hardware does not support tiling Y\n"); | |
57cd6508 | 12508 | return -EINVAL; |
c16ed4be | 12509 | } |
57cd6508 | 12510 | |
c16ed4be CW |
12511 | if (mode_cmd->pitches[0] & 63) { |
12512 | DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n", | |
12513 | mode_cmd->pitches[0]); | |
57cd6508 | 12514 | return -EINVAL; |
c16ed4be | 12515 | } |
57cd6508 | 12516 | |
a35cdaa0 CW |
12517 | if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) { |
12518 | pitch_limit = 32*1024; | |
12519 | } else if (INTEL_INFO(dev)->gen >= 4) { | |
12520 | if (obj->tiling_mode) | |
12521 | pitch_limit = 16*1024; | |
12522 | else | |
12523 | pitch_limit = 32*1024; | |
12524 | } else if (INTEL_INFO(dev)->gen >= 3) { | |
12525 | if (obj->tiling_mode) | |
12526 | pitch_limit = 8*1024; | |
12527 | else | |
12528 | pitch_limit = 16*1024; | |
12529 | } else | |
12530 | /* XXX DSPC is limited to 4k tiled */ | |
12531 | pitch_limit = 8*1024; | |
12532 | ||
12533 | if (mode_cmd->pitches[0] > pitch_limit) { | |
12534 | DRM_DEBUG("%s pitch (%d) must be at less than %d\n", | |
12535 | obj->tiling_mode ? "tiled" : "linear", | |
12536 | mode_cmd->pitches[0], pitch_limit); | |
5d7bd705 | 12537 | return -EINVAL; |
c16ed4be | 12538 | } |
5d7bd705 VS |
12539 | |
12540 | if (obj->tiling_mode != I915_TILING_NONE && | |
c16ed4be CW |
12541 | mode_cmd->pitches[0] != obj->stride) { |
12542 | DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n", | |
12543 | mode_cmd->pitches[0], obj->stride); | |
5d7bd705 | 12544 | return -EINVAL; |
c16ed4be | 12545 | } |
5d7bd705 | 12546 | |
57779d06 | 12547 | /* Reject formats not supported by any plane early. */ |
308e5bcb | 12548 | switch (mode_cmd->pixel_format) { |
57779d06 | 12549 | case DRM_FORMAT_C8: |
04b3924d VS |
12550 | case DRM_FORMAT_RGB565: |
12551 | case DRM_FORMAT_XRGB8888: | |
12552 | case DRM_FORMAT_ARGB8888: | |
57779d06 VS |
12553 | break; |
12554 | case DRM_FORMAT_XRGB1555: | |
12555 | case DRM_FORMAT_ARGB1555: | |
c16ed4be | 12556 | if (INTEL_INFO(dev)->gen > 3) { |
4ee62c76 VS |
12557 | DRM_DEBUG("unsupported pixel format: %s\n", |
12558 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12559 | return -EINVAL; |
c16ed4be | 12560 | } |
57779d06 VS |
12561 | break; |
12562 | case DRM_FORMAT_XBGR8888: | |
12563 | case DRM_FORMAT_ABGR8888: | |
04b3924d VS |
12564 | case DRM_FORMAT_XRGB2101010: |
12565 | case DRM_FORMAT_ARGB2101010: | |
57779d06 VS |
12566 | case DRM_FORMAT_XBGR2101010: |
12567 | case DRM_FORMAT_ABGR2101010: | |
c16ed4be | 12568 | if (INTEL_INFO(dev)->gen < 4) { |
4ee62c76 VS |
12569 | DRM_DEBUG("unsupported pixel format: %s\n", |
12570 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12571 | return -EINVAL; |
c16ed4be | 12572 | } |
b5626747 | 12573 | break; |
04b3924d VS |
12574 | case DRM_FORMAT_YUYV: |
12575 | case DRM_FORMAT_UYVY: | |
12576 | case DRM_FORMAT_YVYU: | |
12577 | case DRM_FORMAT_VYUY: | |
c16ed4be | 12578 | if (INTEL_INFO(dev)->gen < 5) { |
4ee62c76 VS |
12579 | DRM_DEBUG("unsupported pixel format: %s\n", |
12580 | drm_get_format_name(mode_cmd->pixel_format)); | |
57779d06 | 12581 | return -EINVAL; |
c16ed4be | 12582 | } |
57cd6508 CW |
12583 | break; |
12584 | default: | |
4ee62c76 VS |
12585 | DRM_DEBUG("unsupported pixel format: %s\n", |
12586 | drm_get_format_name(mode_cmd->pixel_format)); | |
57cd6508 CW |
12587 | return -EINVAL; |
12588 | } | |
12589 | ||
90f9a336 VS |
12590 | /* FIXME need to adjust LINOFF/TILEOFF accordingly. */ |
12591 | if (mode_cmd->offsets[0] != 0) | |
12592 | return -EINVAL; | |
12593 | ||
a57ce0b2 JB |
12594 | aligned_height = intel_align_height(dev, mode_cmd->height, |
12595 | obj->tiling_mode); | |
53155c0a DV |
12596 | /* FIXME drm helper for size checks (especially planar formats)? */ |
12597 | if (obj->base.size < aligned_height * mode_cmd->pitches[0]) | |
12598 | return -EINVAL; | |
12599 | ||
c7d73f6a DV |
12600 | drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd); |
12601 | intel_fb->obj = obj; | |
80075d49 | 12602 | intel_fb->obj->framebuffer_references++; |
c7d73f6a | 12603 | |
79e53945 JB |
12604 | ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs); |
12605 | if (ret) { | |
12606 | DRM_ERROR("framebuffer init failed %d\n", ret); | |
12607 | return ret; | |
12608 | } | |
12609 | ||
79e53945 JB |
12610 | return 0; |
12611 | } | |
12612 | ||
79e53945 JB |
12613 | static struct drm_framebuffer * |
12614 | intel_user_framebuffer_create(struct drm_device *dev, | |
12615 | struct drm_file *filp, | |
308e5bcb | 12616 | struct drm_mode_fb_cmd2 *mode_cmd) |
79e53945 | 12617 | { |
05394f39 | 12618 | struct drm_i915_gem_object *obj; |
79e53945 | 12619 | |
308e5bcb JB |
12620 | obj = to_intel_bo(drm_gem_object_lookup(dev, filp, |
12621 | mode_cmd->handles[0])); | |
c8725226 | 12622 | if (&obj->base == NULL) |
cce13ff7 | 12623 | return ERR_PTR(-ENOENT); |
79e53945 | 12624 | |
d2dff872 | 12625 | return intel_framebuffer_create(dev, mode_cmd, obj); |
79e53945 JB |
12626 | } |
12627 | ||
4520f53a | 12628 | #ifndef CONFIG_DRM_I915_FBDEV |
0632fef6 | 12629 | static inline void intel_fbdev_output_poll_changed(struct drm_device *dev) |
4520f53a DV |
12630 | { |
12631 | } | |
12632 | #endif | |
12633 | ||
79e53945 | 12634 | static const struct drm_mode_config_funcs intel_mode_funcs = { |
79e53945 | 12635 | .fb_create = intel_user_framebuffer_create, |
0632fef6 | 12636 | .output_poll_changed = intel_fbdev_output_poll_changed, |
79e53945 JB |
12637 | }; |
12638 | ||
e70236a8 JB |
12639 | /* Set up chip specific display functions */ |
12640 | static void intel_init_display(struct drm_device *dev) | |
12641 | { | |
12642 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12643 | ||
ee9300bb DV |
12644 | if (HAS_PCH_SPLIT(dev) || IS_G4X(dev)) |
12645 | dev_priv->display.find_dpll = g4x_find_best_dpll; | |
ef9348c8 CML |
12646 | else if (IS_CHERRYVIEW(dev)) |
12647 | dev_priv->display.find_dpll = chv_find_best_dpll; | |
ee9300bb DV |
12648 | else if (IS_VALLEYVIEW(dev)) |
12649 | dev_priv->display.find_dpll = vlv_find_best_dpll; | |
12650 | else if (IS_PINEVIEW(dev)) | |
12651 | dev_priv->display.find_dpll = pnv_find_best_dpll; | |
12652 | else | |
12653 | dev_priv->display.find_dpll = i9xx_find_best_dpll; | |
12654 | ||
affa9354 | 12655 | if (HAS_DDI(dev)) { |
0e8ffe1b | 12656 | dev_priv->display.get_pipe_config = haswell_get_pipe_config; |
4c6baa59 | 12657 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
09b4ddf9 | 12658 | dev_priv->display.crtc_mode_set = haswell_crtc_mode_set; |
4f771f10 PZ |
12659 | dev_priv->display.crtc_enable = haswell_crtc_enable; |
12660 | dev_priv->display.crtc_disable = haswell_crtc_disable; | |
df8ad70c | 12661 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
12662 | dev_priv->display.update_primary_plane = |
12663 | ironlake_update_primary_plane; | |
09b4ddf9 | 12664 | } else if (HAS_PCH_SPLIT(dev)) { |
0e8ffe1b | 12665 | dev_priv->display.get_pipe_config = ironlake_get_pipe_config; |
4c6baa59 | 12666 | dev_priv->display.get_plane_config = ironlake_get_plane_config; |
f564048e | 12667 | dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set; |
76e5a89c DV |
12668 | dev_priv->display.crtc_enable = ironlake_crtc_enable; |
12669 | dev_priv->display.crtc_disable = ironlake_crtc_disable; | |
ee7b9f93 | 12670 | dev_priv->display.off = ironlake_crtc_off; |
262ca2b0 MR |
12671 | dev_priv->display.update_primary_plane = |
12672 | ironlake_update_primary_plane; | |
89b667f8 JB |
12673 | } else if (IS_VALLEYVIEW(dev)) { |
12674 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; | |
1ad292b5 | 12675 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
89b667f8 JB |
12676 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
12677 | dev_priv->display.crtc_enable = valleyview_crtc_enable; | |
12678 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
12679 | dev_priv->display.off = i9xx_crtc_off; | |
262ca2b0 MR |
12680 | dev_priv->display.update_primary_plane = |
12681 | i9xx_update_primary_plane; | |
f564048e | 12682 | } else { |
0e8ffe1b | 12683 | dev_priv->display.get_pipe_config = i9xx_get_pipe_config; |
1ad292b5 | 12684 | dev_priv->display.get_plane_config = i9xx_get_plane_config; |
f564048e | 12685 | dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set; |
76e5a89c DV |
12686 | dev_priv->display.crtc_enable = i9xx_crtc_enable; |
12687 | dev_priv->display.crtc_disable = i9xx_crtc_disable; | |
ee7b9f93 | 12688 | dev_priv->display.off = i9xx_crtc_off; |
262ca2b0 MR |
12689 | dev_priv->display.update_primary_plane = |
12690 | i9xx_update_primary_plane; | |
f564048e | 12691 | } |
e70236a8 | 12692 | |
e70236a8 | 12693 | /* Returns the core display clock speed */ |
25eb05fc JB |
12694 | if (IS_VALLEYVIEW(dev)) |
12695 | dev_priv->display.get_display_clock_speed = | |
12696 | valleyview_get_display_clock_speed; | |
12697 | else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev))) | |
e70236a8 JB |
12698 | dev_priv->display.get_display_clock_speed = |
12699 | i945_get_display_clock_speed; | |
12700 | else if (IS_I915G(dev)) | |
12701 | dev_priv->display.get_display_clock_speed = | |
12702 | i915_get_display_clock_speed; | |
257a7ffc | 12703 | else if (IS_I945GM(dev) || IS_845G(dev)) |
e70236a8 JB |
12704 | dev_priv->display.get_display_clock_speed = |
12705 | i9xx_misc_get_display_clock_speed; | |
257a7ffc DV |
12706 | else if (IS_PINEVIEW(dev)) |
12707 | dev_priv->display.get_display_clock_speed = | |
12708 | pnv_get_display_clock_speed; | |
e70236a8 JB |
12709 | else if (IS_I915GM(dev)) |
12710 | dev_priv->display.get_display_clock_speed = | |
12711 | i915gm_get_display_clock_speed; | |
12712 | else if (IS_I865G(dev)) | |
12713 | dev_priv->display.get_display_clock_speed = | |
12714 | i865_get_display_clock_speed; | |
f0f8a9ce | 12715 | else if (IS_I85X(dev)) |
e70236a8 JB |
12716 | dev_priv->display.get_display_clock_speed = |
12717 | i855_get_display_clock_speed; | |
12718 | else /* 852, 830 */ | |
12719 | dev_priv->display.get_display_clock_speed = | |
12720 | i830_get_display_clock_speed; | |
12721 | ||
3bb11b53 | 12722 | if (IS_G4X(dev)) { |
e0dac65e | 12723 | dev_priv->display.write_eld = g4x_write_eld; |
3bb11b53 SJ |
12724 | } else if (IS_GEN5(dev)) { |
12725 | dev_priv->display.fdi_link_train = ironlake_fdi_link_train; | |
12726 | dev_priv->display.write_eld = ironlake_write_eld; | |
12727 | } else if (IS_GEN6(dev)) { | |
12728 | dev_priv->display.fdi_link_train = gen6_fdi_link_train; | |
12729 | dev_priv->display.write_eld = ironlake_write_eld; | |
12730 | dev_priv->display.modeset_global_resources = | |
12731 | snb_modeset_global_resources; | |
12732 | } else if (IS_IVYBRIDGE(dev)) { | |
12733 | /* FIXME: detect B0+ stepping and use auto training */ | |
12734 | dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train; | |
12735 | dev_priv->display.write_eld = ironlake_write_eld; | |
12736 | dev_priv->display.modeset_global_resources = | |
12737 | ivb_modeset_global_resources; | |
059b2fe9 | 12738 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
3bb11b53 SJ |
12739 | dev_priv->display.fdi_link_train = hsw_fdi_link_train; |
12740 | dev_priv->display.write_eld = haswell_write_eld; | |
12741 | dev_priv->display.modeset_global_resources = | |
12742 | haswell_modeset_global_resources; | |
30a970c6 JB |
12743 | } else if (IS_VALLEYVIEW(dev)) { |
12744 | dev_priv->display.modeset_global_resources = | |
12745 | valleyview_modeset_global_resources; | |
9ca2fe73 | 12746 | dev_priv->display.write_eld = ironlake_write_eld; |
e70236a8 | 12747 | } |
8c9f3aaf JB |
12748 | |
12749 | /* Default just returns -ENODEV to indicate unsupported */ | |
12750 | dev_priv->display.queue_flip = intel_default_queue_flip; | |
12751 | ||
12752 | switch (INTEL_INFO(dev)->gen) { | |
12753 | case 2: | |
12754 | dev_priv->display.queue_flip = intel_gen2_queue_flip; | |
12755 | break; | |
12756 | ||
12757 | case 3: | |
12758 | dev_priv->display.queue_flip = intel_gen3_queue_flip; | |
12759 | break; | |
12760 | ||
12761 | case 4: | |
12762 | case 5: | |
12763 | dev_priv->display.queue_flip = intel_gen4_queue_flip; | |
12764 | break; | |
12765 | ||
12766 | case 6: | |
12767 | dev_priv->display.queue_flip = intel_gen6_queue_flip; | |
12768 | break; | |
7c9017e5 | 12769 | case 7: |
4e0bbc31 | 12770 | case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */ |
7c9017e5 JB |
12771 | dev_priv->display.queue_flip = intel_gen7_queue_flip; |
12772 | break; | |
8c9f3aaf | 12773 | } |
7bd688cd JN |
12774 | |
12775 | intel_panel_init_backlight_funcs(dev); | |
e39b999a VS |
12776 | |
12777 | mutex_init(&dev_priv->pps_mutex); | |
e70236a8 JB |
12778 | } |
12779 | ||
b690e96c JB |
12780 | /* |
12781 | * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend, | |
12782 | * resume, or other times. This quirk makes sure that's the case for | |
12783 | * affected systems. | |
12784 | */ | |
0206e353 | 12785 | static void quirk_pipea_force(struct drm_device *dev) |
b690e96c JB |
12786 | { |
12787 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12788 | ||
12789 | dev_priv->quirks |= QUIRK_PIPEA_FORCE; | |
bc0daf48 | 12790 | DRM_INFO("applying pipe a force quirk\n"); |
b690e96c JB |
12791 | } |
12792 | ||
b6b5d049 VS |
12793 | static void quirk_pipeb_force(struct drm_device *dev) |
12794 | { | |
12795 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12796 | ||
12797 | dev_priv->quirks |= QUIRK_PIPEB_FORCE; | |
12798 | DRM_INFO("applying pipe b force quirk\n"); | |
12799 | } | |
12800 | ||
435793df KP |
12801 | /* |
12802 | * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason | |
12803 | */ | |
12804 | static void quirk_ssc_force_disable(struct drm_device *dev) | |
12805 | { | |
12806 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12807 | dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE; | |
bc0daf48 | 12808 | DRM_INFO("applying lvds SSC disable quirk\n"); |
435793df KP |
12809 | } |
12810 | ||
4dca20ef | 12811 | /* |
5a15ab5b CE |
12812 | * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight |
12813 | * brightness value | |
4dca20ef CE |
12814 | */ |
12815 | static void quirk_invert_brightness(struct drm_device *dev) | |
12816 | { | |
12817 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12818 | dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS; | |
bc0daf48 | 12819 | DRM_INFO("applying inverted panel brightness quirk\n"); |
435793df KP |
12820 | } |
12821 | ||
9c72cc6f SD |
12822 | /* Some VBT's incorrectly indicate no backlight is present */ |
12823 | static void quirk_backlight_present(struct drm_device *dev) | |
12824 | { | |
12825 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12826 | dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT; | |
12827 | DRM_INFO("applying backlight present quirk\n"); | |
12828 | } | |
12829 | ||
b690e96c JB |
12830 | struct intel_quirk { |
12831 | int device; | |
12832 | int subsystem_vendor; | |
12833 | int subsystem_device; | |
12834 | void (*hook)(struct drm_device *dev); | |
12835 | }; | |
12836 | ||
5f85f176 EE |
12837 | /* For systems that don't have a meaningful PCI subdevice/subvendor ID */ |
12838 | struct intel_dmi_quirk { | |
12839 | void (*hook)(struct drm_device *dev); | |
12840 | const struct dmi_system_id (*dmi_id_list)[]; | |
12841 | }; | |
12842 | ||
12843 | static int intel_dmi_reverse_brightness(const struct dmi_system_id *id) | |
12844 | { | |
12845 | DRM_INFO("Backlight polarity reversed on %s\n", id->ident); | |
12846 | return 1; | |
12847 | } | |
12848 | ||
12849 | static const struct intel_dmi_quirk intel_dmi_quirks[] = { | |
12850 | { | |
12851 | .dmi_id_list = &(const struct dmi_system_id[]) { | |
12852 | { | |
12853 | .callback = intel_dmi_reverse_brightness, | |
12854 | .ident = "NCR Corporation", | |
12855 | .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"), | |
12856 | DMI_MATCH(DMI_PRODUCT_NAME, ""), | |
12857 | }, | |
12858 | }, | |
12859 | { } /* terminating entry */ | |
12860 | }, | |
12861 | .hook = quirk_invert_brightness, | |
12862 | }, | |
12863 | }; | |
12864 | ||
c43b5634 | 12865 | static struct intel_quirk intel_quirks[] = { |
b690e96c | 12866 | /* HP Mini needs pipe A force quirk (LP: #322104) */ |
0206e353 | 12867 | { 0x27ae, 0x103c, 0x361a, quirk_pipea_force }, |
b690e96c | 12868 | |
b690e96c JB |
12869 | /* Toshiba Protege R-205, S-209 needs pipe A force quirk */ |
12870 | { 0x2592, 0x1179, 0x0001, quirk_pipea_force }, | |
12871 | ||
b690e96c JB |
12872 | /* ThinkPad T60 needs pipe A force quirk (bug #16494) */ |
12873 | { 0x2782, 0x17aa, 0x201a, quirk_pipea_force }, | |
12874 | ||
5f080c0f VS |
12875 | /* 830 needs to leave pipe A & dpll A up */ |
12876 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force }, | |
12877 | ||
b6b5d049 VS |
12878 | /* 830 needs to leave pipe B & dpll B up */ |
12879 | { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force }, | |
12880 | ||
435793df KP |
12881 | /* Lenovo U160 cannot use SSC on LVDS */ |
12882 | { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable }, | |
070d329a MAS |
12883 | |
12884 | /* Sony Vaio Y cannot use SSC on LVDS */ | |
12885 | { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable }, | |
5a15ab5b | 12886 | |
be505f64 AH |
12887 | /* Acer Aspire 5734Z must invert backlight brightness */ |
12888 | { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness }, | |
12889 | ||
12890 | /* Acer/eMachines G725 */ | |
12891 | { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness }, | |
12892 | ||
12893 | /* Acer/eMachines e725 */ | |
12894 | { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness }, | |
12895 | ||
12896 | /* Acer/Packard Bell NCL20 */ | |
12897 | { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness }, | |
12898 | ||
12899 | /* Acer Aspire 4736Z */ | |
12900 | { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness }, | |
0f540c3a JN |
12901 | |
12902 | /* Acer Aspire 5336 */ | |
12903 | { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness }, | |
2e93a1aa SD |
12904 | |
12905 | /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */ | |
12906 | { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present }, | |
d4967d8c | 12907 | |
dfb3d47b SD |
12908 | /* Acer C720 Chromebook (Core i3 4005U) */ |
12909 | { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present }, | |
12910 | ||
d4967d8c SD |
12911 | /* Toshiba CB35 Chromebook (Celeron 2955U) */ |
12912 | { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present }, | |
724cb06f SD |
12913 | |
12914 | /* HP Chromebook 14 (Celeron 2955U) */ | |
12915 | { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present }, | |
b690e96c JB |
12916 | }; |
12917 | ||
12918 | static void intel_init_quirks(struct drm_device *dev) | |
12919 | { | |
12920 | struct pci_dev *d = dev->pdev; | |
12921 | int i; | |
12922 | ||
12923 | for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) { | |
12924 | struct intel_quirk *q = &intel_quirks[i]; | |
12925 | ||
12926 | if (d->device == q->device && | |
12927 | (d->subsystem_vendor == q->subsystem_vendor || | |
12928 | q->subsystem_vendor == PCI_ANY_ID) && | |
12929 | (d->subsystem_device == q->subsystem_device || | |
12930 | q->subsystem_device == PCI_ANY_ID)) | |
12931 | q->hook(dev); | |
12932 | } | |
5f85f176 EE |
12933 | for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) { |
12934 | if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0) | |
12935 | intel_dmi_quirks[i].hook(dev); | |
12936 | } | |
b690e96c JB |
12937 | } |
12938 | ||
9cce37f4 JB |
12939 | /* Disable the VGA plane that we never use */ |
12940 | static void i915_disable_vga(struct drm_device *dev) | |
12941 | { | |
12942 | struct drm_i915_private *dev_priv = dev->dev_private; | |
12943 | u8 sr1; | |
766aa1c4 | 12944 | u32 vga_reg = i915_vgacntrl_reg(dev); |
9cce37f4 | 12945 | |
2b37c616 | 12946 | /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */ |
9cce37f4 | 12947 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
3fdcf431 | 12948 | outb(SR01, VGA_SR_INDEX); |
9cce37f4 JB |
12949 | sr1 = inb(VGA_SR_DATA); |
12950 | outb(sr1 | 1<<5, VGA_SR_DATA); | |
12951 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); | |
12952 | udelay(300); | |
12953 | ||
69769f9a VS |
12954 | /* |
12955 | * Fujitsu-Siemens Lifebook S6010 (830) has problems resuming | |
12956 | * from S3 without preserving (some of?) the other bits. | |
12957 | */ | |
12958 | I915_WRITE(vga_reg, dev_priv->bios_vgacntr | VGA_DISP_DISABLE); | |
9cce37f4 JB |
12959 | POSTING_READ(vga_reg); |
12960 | } | |
12961 | ||
f817586c DV |
12962 | void intel_modeset_init_hw(struct drm_device *dev) |
12963 | { | |
a8f78b58 ED |
12964 | intel_prepare_ddi(dev); |
12965 | ||
f8bf63fd VS |
12966 | if (IS_VALLEYVIEW(dev)) |
12967 | vlv_update_cdclk(dev); | |
12968 | ||
f817586c DV |
12969 | intel_init_clock_gating(dev); |
12970 | ||
8090c6b9 | 12971 | intel_enable_gt_powersave(dev); |
f817586c DV |
12972 | } |
12973 | ||
7d708ee4 ID |
12974 | void intel_modeset_suspend_hw(struct drm_device *dev) |
12975 | { | |
12976 | intel_suspend_hw(dev); | |
12977 | } | |
12978 | ||
79e53945 JB |
12979 | void intel_modeset_init(struct drm_device *dev) |
12980 | { | |
652c393a | 12981 | struct drm_i915_private *dev_priv = dev->dev_private; |
1fe47785 | 12982 | int sprite, ret; |
8cc87b75 | 12983 | enum pipe pipe; |
46f297fb | 12984 | struct intel_crtc *crtc; |
79e53945 JB |
12985 | |
12986 | drm_mode_config_init(dev); | |
12987 | ||
12988 | dev->mode_config.min_width = 0; | |
12989 | dev->mode_config.min_height = 0; | |
12990 | ||
019d96cb DA |
12991 | dev->mode_config.preferred_depth = 24; |
12992 | dev->mode_config.prefer_shadow = 1; | |
12993 | ||
e6ecefaa | 12994 | dev->mode_config.funcs = &intel_mode_funcs; |
79e53945 | 12995 | |
b690e96c JB |
12996 | intel_init_quirks(dev); |
12997 | ||
1fa61106 ED |
12998 | intel_init_pm(dev); |
12999 | ||
e3c74757 BW |
13000 | if (INTEL_INFO(dev)->num_pipes == 0) |
13001 | return; | |
13002 | ||
e70236a8 JB |
13003 | intel_init_display(dev); |
13004 | ||
a6c45cf0 CW |
13005 | if (IS_GEN2(dev)) { |
13006 | dev->mode_config.max_width = 2048; | |
13007 | dev->mode_config.max_height = 2048; | |
13008 | } else if (IS_GEN3(dev)) { | |
5e4d6fa7 KP |
13009 | dev->mode_config.max_width = 4096; |
13010 | dev->mode_config.max_height = 4096; | |
79e53945 | 13011 | } else { |
a6c45cf0 CW |
13012 | dev->mode_config.max_width = 8192; |
13013 | dev->mode_config.max_height = 8192; | |
79e53945 | 13014 | } |
068be561 | 13015 | |
dc41c154 VS |
13016 | if (IS_845G(dev) || IS_I865G(dev)) { |
13017 | dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512; | |
13018 | dev->mode_config.cursor_height = 1023; | |
13019 | } else if (IS_GEN2(dev)) { | |
068be561 DL |
13020 | dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH; |
13021 | dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT; | |
13022 | } else { | |
13023 | dev->mode_config.cursor_width = MAX_CURSOR_WIDTH; | |
13024 | dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT; | |
13025 | } | |
13026 | ||
5d4545ae | 13027 | dev->mode_config.fb_base = dev_priv->gtt.mappable_base; |
79e53945 | 13028 | |
28c97730 | 13029 | DRM_DEBUG_KMS("%d display pipe%s available.\n", |
7eb552ae BW |
13030 | INTEL_INFO(dev)->num_pipes, |
13031 | INTEL_INFO(dev)->num_pipes > 1 ? "s" : ""); | |
79e53945 | 13032 | |
055e393f | 13033 | for_each_pipe(dev_priv, pipe) { |
8cc87b75 | 13034 | intel_crtc_init(dev, pipe); |
1fe47785 DL |
13035 | for_each_sprite(pipe, sprite) { |
13036 | ret = intel_plane_init(dev, pipe, sprite); | |
7f1f3851 | 13037 | if (ret) |
06da8da2 | 13038 | DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n", |
1fe47785 | 13039 | pipe_name(pipe), sprite_name(pipe, sprite), ret); |
7f1f3851 | 13040 | } |
79e53945 JB |
13041 | } |
13042 | ||
f42bb70d JB |
13043 | intel_init_dpio(dev); |
13044 | ||
e72f9fbf | 13045 | intel_shared_dpll_init(dev); |
ee7b9f93 | 13046 | |
69769f9a VS |
13047 | /* save the BIOS value before clobbering it */ |
13048 | dev_priv->bios_vgacntr = I915_READ(i915_vgacntrl_reg(dev)); | |
9cce37f4 JB |
13049 | /* Just disable it once at startup */ |
13050 | i915_disable_vga(dev); | |
79e53945 | 13051 | intel_setup_outputs(dev); |
11be49eb CW |
13052 | |
13053 | /* Just in case the BIOS is doing something questionable. */ | |
13054 | intel_disable_fbc(dev); | |
fa9fa083 | 13055 | |
6e9f798d | 13056 | drm_modeset_lock_all(dev); |
fa9fa083 | 13057 | intel_modeset_setup_hw_state(dev, false); |
6e9f798d | 13058 | drm_modeset_unlock_all(dev); |
46f297fb | 13059 | |
d3fcc808 | 13060 | for_each_intel_crtc(dev, crtc) { |
46f297fb JB |
13061 | if (!crtc->active) |
13062 | continue; | |
13063 | ||
46f297fb | 13064 | /* |
46f297fb JB |
13065 | * Note that reserving the BIOS fb up front prevents us |
13066 | * from stuffing other stolen allocations like the ring | |
13067 | * on top. This prevents some ugliness at boot time, and | |
13068 | * can even allow for smooth boot transitions if the BIOS | |
13069 | * fb is large enough for the active pipe configuration. | |
13070 | */ | |
13071 | if (dev_priv->display.get_plane_config) { | |
13072 | dev_priv->display.get_plane_config(crtc, | |
13073 | &crtc->plane_config); | |
13074 | /* | |
13075 | * If the fb is shared between multiple heads, we'll | |
13076 | * just get the first one. | |
13077 | */ | |
484b41dd | 13078 | intel_find_plane_obj(crtc, &crtc->plane_config); |
46f297fb | 13079 | } |
46f297fb | 13080 | } |
2c7111db CW |
13081 | } |
13082 | ||
7fad798e DV |
13083 | static void intel_enable_pipe_a(struct drm_device *dev) |
13084 | { | |
13085 | struct intel_connector *connector; | |
13086 | struct drm_connector *crt = NULL; | |
13087 | struct intel_load_detect_pipe load_detect_temp; | |
208bf9fd | 13088 | struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx; |
7fad798e DV |
13089 | |
13090 | /* We can't just switch on the pipe A, we need to set things up with a | |
13091 | * proper mode and output configuration. As a gross hack, enable pipe A | |
13092 | * by enabling the load detect pipe once. */ | |
13093 | list_for_each_entry(connector, | |
13094 | &dev->mode_config.connector_list, | |
13095 | base.head) { | |
13096 | if (connector->encoder->type == INTEL_OUTPUT_ANALOG) { | |
13097 | crt = &connector->base; | |
13098 | break; | |
13099 | } | |
13100 | } | |
13101 | ||
13102 | if (!crt) | |
13103 | return; | |
13104 | ||
208bf9fd VS |
13105 | if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx)) |
13106 | intel_release_load_detect_pipe(crt, &load_detect_temp); | |
7fad798e DV |
13107 | } |
13108 | ||
fa555837 DV |
13109 | static bool |
13110 | intel_check_plane_mapping(struct intel_crtc *crtc) | |
13111 | { | |
7eb552ae BW |
13112 | struct drm_device *dev = crtc->base.dev; |
13113 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 DV |
13114 | u32 reg, val; |
13115 | ||
7eb552ae | 13116 | if (INTEL_INFO(dev)->num_pipes == 1) |
fa555837 DV |
13117 | return true; |
13118 | ||
13119 | reg = DSPCNTR(!crtc->plane); | |
13120 | val = I915_READ(reg); | |
13121 | ||
13122 | if ((val & DISPLAY_PLANE_ENABLE) && | |
13123 | (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe)) | |
13124 | return false; | |
13125 | ||
13126 | return true; | |
13127 | } | |
13128 | ||
24929352 DV |
13129 | static void intel_sanitize_crtc(struct intel_crtc *crtc) |
13130 | { | |
13131 | struct drm_device *dev = crtc->base.dev; | |
13132 | struct drm_i915_private *dev_priv = dev->dev_private; | |
fa555837 | 13133 | u32 reg; |
24929352 | 13134 | |
24929352 | 13135 | /* Clear any frame start delays used for debugging left by the BIOS */ |
3b117c8f | 13136 | reg = PIPECONF(crtc->config.cpu_transcoder); |
24929352 DV |
13137 | I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); |
13138 | ||
d3eaf884 | 13139 | /* restore vblank interrupts to correct state */ |
d297e103 VS |
13140 | if (crtc->active) { |
13141 | update_scanline_offset(crtc); | |
d3eaf884 | 13142 | drm_vblank_on(dev, crtc->pipe); |
d297e103 | 13143 | } else |
d3eaf884 VS |
13144 | drm_vblank_off(dev, crtc->pipe); |
13145 | ||
24929352 | 13146 | /* We need to sanitize the plane -> pipe mapping first because this will |
fa555837 DV |
13147 | * disable the crtc (and hence change the state) if it is wrong. Note |
13148 | * that gen4+ has a fixed plane -> pipe mapping. */ | |
13149 | if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) { | |
24929352 DV |
13150 | struct intel_connector *connector; |
13151 | bool plane; | |
13152 | ||
24929352 DV |
13153 | DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n", |
13154 | crtc->base.base.id); | |
13155 | ||
13156 | /* Pipe has the wrong plane attached and the plane is active. | |
13157 | * Temporarily change the plane mapping and disable everything | |
13158 | * ... */ | |
13159 | plane = crtc->plane; | |
13160 | crtc->plane = !plane; | |
9c8958bc | 13161 | crtc->primary_enabled = true; |
24929352 DV |
13162 | dev_priv->display.crtc_disable(&crtc->base); |
13163 | crtc->plane = plane; | |
13164 | ||
13165 | /* ... and break all links. */ | |
13166 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
13167 | base.head) { | |
13168 | if (connector->encoder->base.crtc != &crtc->base) | |
13169 | continue; | |
13170 | ||
7f1950fb EE |
13171 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
13172 | connector->base.encoder = NULL; | |
24929352 | 13173 | } |
7f1950fb EE |
13174 | /* multiple connectors may have the same encoder: |
13175 | * handle them and break crtc link separately */ | |
13176 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
13177 | base.head) | |
13178 | if (connector->encoder->base.crtc == &crtc->base) { | |
13179 | connector->encoder->base.crtc = NULL; | |
13180 | connector->encoder->connectors_active = false; | |
13181 | } | |
24929352 DV |
13182 | |
13183 | WARN_ON(crtc->active); | |
13184 | crtc->base.enabled = false; | |
13185 | } | |
24929352 | 13186 | |
7fad798e DV |
13187 | if (dev_priv->quirks & QUIRK_PIPEA_FORCE && |
13188 | crtc->pipe == PIPE_A && !crtc->active) { | |
13189 | /* BIOS forgot to enable pipe A, this mostly happens after | |
13190 | * resume. Force-enable the pipe to fix this, the update_dpms | |
13191 | * call below we restore the pipe to the right state, but leave | |
13192 | * the required bits on. */ | |
13193 | intel_enable_pipe_a(dev); | |
13194 | } | |
13195 | ||
24929352 DV |
13196 | /* Adjust the state of the output pipe according to whether we |
13197 | * have active connectors/encoders. */ | |
13198 | intel_crtc_update_dpms(&crtc->base); | |
13199 | ||
13200 | if (crtc->active != crtc->base.enabled) { | |
13201 | struct intel_encoder *encoder; | |
13202 | ||
13203 | /* This can happen either due to bugs in the get_hw_state | |
13204 | * functions or because the pipe is force-enabled due to the | |
13205 | * pipe A quirk. */ | |
13206 | DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n", | |
13207 | crtc->base.base.id, | |
13208 | crtc->base.enabled ? "enabled" : "disabled", | |
13209 | crtc->active ? "enabled" : "disabled"); | |
13210 | ||
13211 | crtc->base.enabled = crtc->active; | |
13212 | ||
13213 | /* Because we only establish the connector -> encoder -> | |
13214 | * crtc links if something is active, this means the | |
13215 | * crtc is now deactivated. Break the links. connector | |
13216 | * -> encoder links are only establish when things are | |
13217 | * actually up, hence no need to break them. */ | |
13218 | WARN_ON(crtc->active); | |
13219 | ||
13220 | for_each_encoder_on_crtc(dev, &crtc->base, encoder) { | |
13221 | WARN_ON(encoder->connectors_active); | |
13222 | encoder->base.crtc = NULL; | |
13223 | } | |
13224 | } | |
c5ab3bc0 | 13225 | |
a3ed6aad | 13226 | if (crtc->active || HAS_GMCH_DISPLAY(dev)) { |
4cc31489 DV |
13227 | /* |
13228 | * We start out with underrun reporting disabled to avoid races. | |
13229 | * For correct bookkeeping mark this on active crtcs. | |
13230 | * | |
c5ab3bc0 DV |
13231 | * Also on gmch platforms we dont have any hardware bits to |
13232 | * disable the underrun reporting. Which means we need to start | |
13233 | * out with underrun reporting disabled also on inactive pipes, | |
13234 | * since otherwise we'll complain about the garbage we read when | |
13235 | * e.g. coming up after runtime pm. | |
13236 | * | |
4cc31489 DV |
13237 | * No protection against concurrent access is required - at |
13238 | * worst a fifo underrun happens which also sets this to false. | |
13239 | */ | |
13240 | crtc->cpu_fifo_underrun_disabled = true; | |
13241 | crtc->pch_fifo_underrun_disabled = true; | |
13242 | } | |
24929352 DV |
13243 | } |
13244 | ||
13245 | static void intel_sanitize_encoder(struct intel_encoder *encoder) | |
13246 | { | |
13247 | struct intel_connector *connector; | |
13248 | struct drm_device *dev = encoder->base.dev; | |
13249 | ||
13250 | /* We need to check both for a crtc link (meaning that the | |
13251 | * encoder is active and trying to read from a pipe) and the | |
13252 | * pipe itself being active. */ | |
13253 | bool has_active_crtc = encoder->base.crtc && | |
13254 | to_intel_crtc(encoder->base.crtc)->active; | |
13255 | ||
13256 | if (encoder->connectors_active && !has_active_crtc) { | |
13257 | DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n", | |
13258 | encoder->base.base.id, | |
8e329a03 | 13259 | encoder->base.name); |
24929352 DV |
13260 | |
13261 | /* Connector is active, but has no active pipe. This is | |
13262 | * fallout from our resume register restoring. Disable | |
13263 | * the encoder manually again. */ | |
13264 | if (encoder->base.crtc) { | |
13265 | DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n", | |
13266 | encoder->base.base.id, | |
8e329a03 | 13267 | encoder->base.name); |
24929352 | 13268 | encoder->disable(encoder); |
a62d1497 VS |
13269 | if (encoder->post_disable) |
13270 | encoder->post_disable(encoder); | |
24929352 | 13271 | } |
7f1950fb EE |
13272 | encoder->base.crtc = NULL; |
13273 | encoder->connectors_active = false; | |
24929352 DV |
13274 | |
13275 | /* Inconsistent output/port/pipe state happens presumably due to | |
13276 | * a bug in one of the get_hw_state functions. Or someplace else | |
13277 | * in our code, like the register restore mess on resume. Clamp | |
13278 | * things to off as a safer default. */ | |
13279 | list_for_each_entry(connector, | |
13280 | &dev->mode_config.connector_list, | |
13281 | base.head) { | |
13282 | if (connector->encoder != encoder) | |
13283 | continue; | |
7f1950fb EE |
13284 | connector->base.dpms = DRM_MODE_DPMS_OFF; |
13285 | connector->base.encoder = NULL; | |
24929352 DV |
13286 | } |
13287 | } | |
13288 | /* Enabled encoders without active connectors will be fixed in | |
13289 | * the crtc fixup. */ | |
13290 | } | |
13291 | ||
04098753 | 13292 | void i915_redisable_vga_power_on(struct drm_device *dev) |
0fde901f KM |
13293 | { |
13294 | struct drm_i915_private *dev_priv = dev->dev_private; | |
766aa1c4 | 13295 | u32 vga_reg = i915_vgacntrl_reg(dev); |
0fde901f | 13296 | |
04098753 ID |
13297 | if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) { |
13298 | DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n"); | |
13299 | i915_disable_vga(dev); | |
13300 | } | |
13301 | } | |
13302 | ||
13303 | void i915_redisable_vga(struct drm_device *dev) | |
13304 | { | |
13305 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13306 | ||
8dc8a27c PZ |
13307 | /* This function can be called both from intel_modeset_setup_hw_state or |
13308 | * at a very early point in our resume sequence, where the power well | |
13309 | * structures are not yet restored. Since this function is at a very | |
13310 | * paranoid "someone might have enabled VGA while we were not looking" | |
13311 | * level, just check if the power well is enabled instead of trying to | |
13312 | * follow the "don't touch the power well if we don't need it" policy | |
13313 | * the rest of the driver uses. */ | |
04098753 | 13314 | if (!intel_display_power_enabled(dev_priv, POWER_DOMAIN_VGA)) |
8dc8a27c PZ |
13315 | return; |
13316 | ||
04098753 | 13317 | i915_redisable_vga_power_on(dev); |
0fde901f KM |
13318 | } |
13319 | ||
98ec7739 VS |
13320 | static bool primary_get_hw_state(struct intel_crtc *crtc) |
13321 | { | |
13322 | struct drm_i915_private *dev_priv = crtc->base.dev->dev_private; | |
13323 | ||
13324 | if (!crtc->active) | |
13325 | return false; | |
13326 | ||
13327 | return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE; | |
13328 | } | |
13329 | ||
30e984df | 13330 | static void intel_modeset_readout_hw_state(struct drm_device *dev) |
24929352 DV |
13331 | { |
13332 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13333 | enum pipe pipe; | |
24929352 DV |
13334 | struct intel_crtc *crtc; |
13335 | struct intel_encoder *encoder; | |
13336 | struct intel_connector *connector; | |
5358901f | 13337 | int i; |
24929352 | 13338 | |
d3fcc808 | 13339 | for_each_intel_crtc(dev, crtc) { |
88adfff1 | 13340 | memset(&crtc->config, 0, sizeof(crtc->config)); |
3b117c8f | 13341 | |
9953599b DV |
13342 | crtc->config.quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE; |
13343 | ||
0e8ffe1b DV |
13344 | crtc->active = dev_priv->display.get_pipe_config(crtc, |
13345 | &crtc->config); | |
24929352 DV |
13346 | |
13347 | crtc->base.enabled = crtc->active; | |
98ec7739 | 13348 | crtc->primary_enabled = primary_get_hw_state(crtc); |
24929352 DV |
13349 | |
13350 | DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n", | |
13351 | crtc->base.base.id, | |
13352 | crtc->active ? "enabled" : "disabled"); | |
13353 | } | |
13354 | ||
5358901f DV |
13355 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
13356 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
13357 | ||
13358 | pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state); | |
13359 | pll->active = 0; | |
d3fcc808 | 13360 | for_each_intel_crtc(dev, crtc) { |
5358901f DV |
13361 | if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) |
13362 | pll->active++; | |
13363 | } | |
13364 | pll->refcount = pll->active; | |
13365 | ||
35c95375 DV |
13366 | DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n", |
13367 | pll->name, pll->refcount, pll->on); | |
bd2bb1b9 PZ |
13368 | |
13369 | if (pll->refcount) | |
13370 | intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS); | |
5358901f DV |
13371 | } |
13372 | ||
b2784e15 | 13373 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
13374 | pipe = 0; |
13375 | ||
13376 | if (encoder->get_hw_state(encoder, &pipe)) { | |
045ac3b5 JB |
13377 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
13378 | encoder->base.crtc = &crtc->base; | |
1d37b689 | 13379 | encoder->get_config(encoder, &crtc->config); |
24929352 DV |
13380 | } else { |
13381 | encoder->base.crtc = NULL; | |
13382 | } | |
13383 | ||
13384 | encoder->connectors_active = false; | |
6f2bcceb | 13385 | DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n", |
24929352 | 13386 | encoder->base.base.id, |
8e329a03 | 13387 | encoder->base.name, |
24929352 | 13388 | encoder->base.crtc ? "enabled" : "disabled", |
6f2bcceb | 13389 | pipe_name(pipe)); |
24929352 DV |
13390 | } |
13391 | ||
13392 | list_for_each_entry(connector, &dev->mode_config.connector_list, | |
13393 | base.head) { | |
13394 | if (connector->get_hw_state(connector)) { | |
13395 | connector->base.dpms = DRM_MODE_DPMS_ON; | |
13396 | connector->encoder->connectors_active = true; | |
13397 | connector->base.encoder = &connector->encoder->base; | |
13398 | } else { | |
13399 | connector->base.dpms = DRM_MODE_DPMS_OFF; | |
13400 | connector->base.encoder = NULL; | |
13401 | } | |
13402 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n", | |
13403 | connector->base.base.id, | |
c23cc417 | 13404 | connector->base.name, |
24929352 DV |
13405 | connector->base.encoder ? "enabled" : "disabled"); |
13406 | } | |
30e984df DV |
13407 | } |
13408 | ||
13409 | /* Scan out the current hw modeset state, sanitizes it and maps it into the drm | |
13410 | * and i915 state tracking structures. */ | |
13411 | void intel_modeset_setup_hw_state(struct drm_device *dev, | |
13412 | bool force_restore) | |
13413 | { | |
13414 | struct drm_i915_private *dev_priv = dev->dev_private; | |
13415 | enum pipe pipe; | |
30e984df DV |
13416 | struct intel_crtc *crtc; |
13417 | struct intel_encoder *encoder; | |
35c95375 | 13418 | int i; |
30e984df DV |
13419 | |
13420 | intel_modeset_readout_hw_state(dev); | |
24929352 | 13421 | |
babea61d JB |
13422 | /* |
13423 | * Now that we have the config, copy it to each CRTC struct | |
13424 | * Note that this could go away if we move to using crtc_config | |
13425 | * checking everywhere. | |
13426 | */ | |
d3fcc808 | 13427 | for_each_intel_crtc(dev, crtc) { |
d330a953 | 13428 | if (crtc->active && i915.fastboot) { |
f6a83288 | 13429 | intel_mode_from_pipe_config(&crtc->base.mode, &crtc->config); |
babea61d JB |
13430 | DRM_DEBUG_KMS("[CRTC:%d] found active mode: ", |
13431 | crtc->base.base.id); | |
13432 | drm_mode_debug_printmodeline(&crtc->base.mode); | |
13433 | } | |
13434 | } | |
13435 | ||
24929352 | 13436 | /* HW state is read out, now we need to sanitize this mess. */ |
b2784e15 | 13437 | for_each_intel_encoder(dev, encoder) { |
24929352 DV |
13438 | intel_sanitize_encoder(encoder); |
13439 | } | |
13440 | ||
055e393f | 13441 | for_each_pipe(dev_priv, pipe) { |
24929352 DV |
13442 | crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); |
13443 | intel_sanitize_crtc(crtc); | |
c0b03411 | 13444 | intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]"); |
24929352 | 13445 | } |
9a935856 | 13446 | |
35c95375 DV |
13447 | for (i = 0; i < dev_priv->num_shared_dpll; i++) { |
13448 | struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i]; | |
13449 | ||
13450 | if (!pll->on || pll->active) | |
13451 | continue; | |
13452 | ||
13453 | DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name); | |
13454 | ||
13455 | pll->disable(dev_priv, pll); | |
13456 | pll->on = false; | |
13457 | } | |
13458 | ||
96f90c54 | 13459 | if (HAS_PCH_SPLIT(dev)) |
243e6a44 VS |
13460 | ilk_wm_get_hw_state(dev); |
13461 | ||
45e2b5f6 | 13462 | if (force_restore) { |
7d0bc1ea VS |
13463 | i915_redisable_vga(dev); |
13464 | ||
f30da187 DV |
13465 | /* |
13466 | * We need to use raw interfaces for restoring state to avoid | |
13467 | * checking (bogus) intermediate states. | |
13468 | */ | |
055e393f | 13469 | for_each_pipe(dev_priv, pipe) { |
b5644d05 JB |
13470 | struct drm_crtc *crtc = |
13471 | dev_priv->pipe_to_crtc_mapping[pipe]; | |
f30da187 DV |
13472 | |
13473 | __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, | |
f4510a27 | 13474 | crtc->primary->fb); |
45e2b5f6 DV |
13475 | } |
13476 | } else { | |
13477 | intel_modeset_update_staged_output_state(dev); | |
13478 | } | |
8af6cf88 DV |
13479 | |
13480 | intel_modeset_check_state(dev); | |
2c7111db CW |
13481 | } |
13482 | ||
13483 | void intel_modeset_gem_init(struct drm_device *dev) | |
13484 | { | |
484b41dd | 13485 | struct drm_crtc *c; |
2ff8fde1 | 13486 | struct drm_i915_gem_object *obj; |
484b41dd | 13487 | |
ae48434c ID |
13488 | mutex_lock(&dev->struct_mutex); |
13489 | intel_init_gt_powersave(dev); | |
13490 | mutex_unlock(&dev->struct_mutex); | |
13491 | ||
1833b134 | 13492 | intel_modeset_init_hw(dev); |
02e792fb DV |
13493 | |
13494 | intel_setup_overlay(dev); | |
484b41dd JB |
13495 | |
13496 | /* | |
13497 | * Make sure any fbs we allocated at startup are properly | |
13498 | * pinned & fenced. When we do the allocation it's too early | |
13499 | * for this. | |
13500 | */ | |
13501 | mutex_lock(&dev->struct_mutex); | |
70e1e0ec | 13502 | for_each_crtc(dev, c) { |
2ff8fde1 MR |
13503 | obj = intel_fb_obj(c->primary->fb); |
13504 | if (obj == NULL) | |
484b41dd JB |
13505 | continue; |
13506 | ||
2ff8fde1 | 13507 | if (intel_pin_and_fence_fb_obj(dev, obj, NULL)) { |
484b41dd JB |
13508 | DRM_ERROR("failed to pin boot fb on pipe %d\n", |
13509 | to_intel_crtc(c)->pipe); | |
66e514c1 DA |
13510 | drm_framebuffer_unreference(c->primary->fb); |
13511 | c->primary->fb = NULL; | |
484b41dd JB |
13512 | } |
13513 | } | |
13514 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
13515 | } |
13516 | ||
4932e2c3 ID |
13517 | void intel_connector_unregister(struct intel_connector *intel_connector) |
13518 | { | |
13519 | struct drm_connector *connector = &intel_connector->base; | |
13520 | ||
13521 | intel_panel_destroy_backlight(connector); | |
34ea3d38 | 13522 | drm_connector_unregister(connector); |
4932e2c3 ID |
13523 | } |
13524 | ||
79e53945 JB |
13525 | void intel_modeset_cleanup(struct drm_device *dev) |
13526 | { | |
652c393a | 13527 | struct drm_i915_private *dev_priv = dev->dev_private; |
d9255d57 | 13528 | struct drm_connector *connector; |
652c393a | 13529 | |
fd0c0642 DV |
13530 | /* |
13531 | * Interrupts and polling as the first thing to avoid creating havoc. | |
13532 | * Too much stuff here (turning of rps, connectors, ...) would | |
13533 | * experience fancy races otherwise. | |
13534 | */ | |
13535 | drm_irq_uninstall(dev); | |
1d0d343a | 13536 | intel_hpd_cancel_work(dev_priv); |
eb21b92b JB |
13537 | dev_priv->pm._irqs_disabled = true; |
13538 | ||
fd0c0642 DV |
13539 | /* |
13540 | * Due to the hpd irq storm handling the hotplug work can re-arm the | |
13541 | * poll handlers. Hence disable polling after hpd handling is shut down. | |
13542 | */ | |
f87ea761 | 13543 | drm_kms_helper_poll_fini(dev); |
fd0c0642 | 13544 | |
652c393a JB |
13545 | mutex_lock(&dev->struct_mutex); |
13546 | ||
723bfd70 JB |
13547 | intel_unregister_dsm_handler(); |
13548 | ||
973d04f9 | 13549 | intel_disable_fbc(dev); |
e70236a8 | 13550 | |
8090c6b9 | 13551 | intel_disable_gt_powersave(dev); |
0cdab21f | 13552 | |
930ebb46 DV |
13553 | ironlake_teardown_rc6(dev); |
13554 | ||
69341a5e KH |
13555 | mutex_unlock(&dev->struct_mutex); |
13556 | ||
1630fe75 CW |
13557 | /* flush any delayed tasks or pending work */ |
13558 | flush_scheduled_work(); | |
13559 | ||
db31af1d JN |
13560 | /* destroy the backlight and sysfs files before encoders/connectors */ |
13561 | list_for_each_entry(connector, &dev->mode_config.connector_list, head) { | |
4932e2c3 ID |
13562 | struct intel_connector *intel_connector; |
13563 | ||
13564 | intel_connector = to_intel_connector(connector); | |
13565 | intel_connector->unregister(intel_connector); | |
db31af1d | 13566 | } |
d9255d57 | 13567 | |
79e53945 | 13568 | drm_mode_config_cleanup(dev); |
4d7bb011 DV |
13569 | |
13570 | intel_cleanup_overlay(dev); | |
ae48434c ID |
13571 | |
13572 | mutex_lock(&dev->struct_mutex); | |
13573 | intel_cleanup_gt_powersave(dev); | |
13574 | mutex_unlock(&dev->struct_mutex); | |
79e53945 JB |
13575 | } |
13576 | ||
f1c79df3 ZW |
13577 | /* |
13578 | * Return which encoder is currently attached for connector. | |
13579 | */ | |
df0e9248 | 13580 | struct drm_encoder *intel_best_encoder(struct drm_connector *connector) |
79e53945 | 13581 | { |
df0e9248 CW |
13582 | return &intel_attached_encoder(connector)->base; |
13583 | } | |
f1c79df3 | 13584 | |
df0e9248 CW |
13585 | void intel_connector_attach_encoder(struct intel_connector *connector, |
13586 | struct intel_encoder *encoder) | |
13587 | { | |
13588 | connector->encoder = encoder; | |
13589 | drm_mode_connector_attach_encoder(&connector->base, | |
13590 | &encoder->base); | |
79e53945 | 13591 | } |
28d52043 DA |
13592 | |
13593 | /* | |
13594 | * set vga decode state - true == enable VGA decode | |
13595 | */ | |
13596 | int intel_modeset_vga_set_state(struct drm_device *dev, bool state) | |
13597 | { | |
13598 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a885b3cc | 13599 | unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL; |
28d52043 DA |
13600 | u16 gmch_ctrl; |
13601 | ||
75fa041d CW |
13602 | if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) { |
13603 | DRM_ERROR("failed to read control word\n"); | |
13604 | return -EIO; | |
13605 | } | |
13606 | ||
c0cc8a55 CW |
13607 | if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state) |
13608 | return 0; | |
13609 | ||
28d52043 DA |
13610 | if (state) |
13611 | gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE; | |
13612 | else | |
13613 | gmch_ctrl |= INTEL_GMCH_VGA_DISABLE; | |
75fa041d CW |
13614 | |
13615 | if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) { | |
13616 | DRM_ERROR("failed to write control word\n"); | |
13617 | return -EIO; | |
13618 | } | |
13619 | ||
28d52043 DA |
13620 | return 0; |
13621 | } | |
c4a1d9e4 | 13622 | |
c4a1d9e4 | 13623 | struct intel_display_error_state { |
ff57f1b0 PZ |
13624 | |
13625 | u32 power_well_driver; | |
13626 | ||
63b66e5b CW |
13627 | int num_transcoders; |
13628 | ||
c4a1d9e4 CW |
13629 | struct intel_cursor_error_state { |
13630 | u32 control; | |
13631 | u32 position; | |
13632 | u32 base; | |
13633 | u32 size; | |
52331309 | 13634 | } cursor[I915_MAX_PIPES]; |
c4a1d9e4 CW |
13635 | |
13636 | struct intel_pipe_error_state { | |
ddf9c536 | 13637 | bool power_domain_on; |
c4a1d9e4 | 13638 | u32 source; |
f301b1e1 | 13639 | u32 stat; |
52331309 | 13640 | } pipe[I915_MAX_PIPES]; |
c4a1d9e4 CW |
13641 | |
13642 | struct intel_plane_error_state { | |
13643 | u32 control; | |
13644 | u32 stride; | |
13645 | u32 size; | |
13646 | u32 pos; | |
13647 | u32 addr; | |
13648 | u32 surface; | |
13649 | u32 tile_offset; | |
52331309 | 13650 | } plane[I915_MAX_PIPES]; |
63b66e5b CW |
13651 | |
13652 | struct intel_transcoder_error_state { | |
ddf9c536 | 13653 | bool power_domain_on; |
63b66e5b CW |
13654 | enum transcoder cpu_transcoder; |
13655 | ||
13656 | u32 conf; | |
13657 | ||
13658 | u32 htotal; | |
13659 | u32 hblank; | |
13660 | u32 hsync; | |
13661 | u32 vtotal; | |
13662 | u32 vblank; | |
13663 | u32 vsync; | |
13664 | } transcoder[4]; | |
c4a1d9e4 CW |
13665 | }; |
13666 | ||
13667 | struct intel_display_error_state * | |
13668 | intel_display_capture_error_state(struct drm_device *dev) | |
13669 | { | |
fbee40df | 13670 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 | 13671 | struct intel_display_error_state *error; |
63b66e5b CW |
13672 | int transcoders[] = { |
13673 | TRANSCODER_A, | |
13674 | TRANSCODER_B, | |
13675 | TRANSCODER_C, | |
13676 | TRANSCODER_EDP, | |
13677 | }; | |
c4a1d9e4 CW |
13678 | int i; |
13679 | ||
63b66e5b CW |
13680 | if (INTEL_INFO(dev)->num_pipes == 0) |
13681 | return NULL; | |
13682 | ||
9d1cb914 | 13683 | error = kzalloc(sizeof(*error), GFP_ATOMIC); |
c4a1d9e4 CW |
13684 | if (error == NULL) |
13685 | return NULL; | |
13686 | ||
190be112 | 13687 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ff57f1b0 PZ |
13688 | error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER); |
13689 | ||
055e393f | 13690 | for_each_pipe(dev_priv, i) { |
ddf9c536 | 13691 | error->pipe[i].power_domain_on = |
bfafe93a ID |
13692 | intel_display_power_enabled_unlocked(dev_priv, |
13693 | POWER_DOMAIN_PIPE(i)); | |
ddf9c536 | 13694 | if (!error->pipe[i].power_domain_on) |
9d1cb914 PZ |
13695 | continue; |
13696 | ||
5efb3e28 VS |
13697 | error->cursor[i].control = I915_READ(CURCNTR(i)); |
13698 | error->cursor[i].position = I915_READ(CURPOS(i)); | |
13699 | error->cursor[i].base = I915_READ(CURBASE(i)); | |
c4a1d9e4 CW |
13700 | |
13701 | error->plane[i].control = I915_READ(DSPCNTR(i)); | |
13702 | error->plane[i].stride = I915_READ(DSPSTRIDE(i)); | |
80ca378b | 13703 | if (INTEL_INFO(dev)->gen <= 3) { |
51889b35 | 13704 | error->plane[i].size = I915_READ(DSPSIZE(i)); |
80ca378b PZ |
13705 | error->plane[i].pos = I915_READ(DSPPOS(i)); |
13706 | } | |
ca291363 PZ |
13707 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
13708 | error->plane[i].addr = I915_READ(DSPADDR(i)); | |
c4a1d9e4 CW |
13709 | if (INTEL_INFO(dev)->gen >= 4) { |
13710 | error->plane[i].surface = I915_READ(DSPSURF(i)); | |
13711 | error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); | |
13712 | } | |
13713 | ||
c4a1d9e4 | 13714 | error->pipe[i].source = I915_READ(PIPESRC(i)); |
f301b1e1 | 13715 | |
3abfce77 | 13716 | if (HAS_GMCH_DISPLAY(dev)) |
f301b1e1 | 13717 | error->pipe[i].stat = I915_READ(PIPESTAT(i)); |
63b66e5b CW |
13718 | } |
13719 | ||
13720 | error->num_transcoders = INTEL_INFO(dev)->num_pipes; | |
13721 | if (HAS_DDI(dev_priv->dev)) | |
13722 | error->num_transcoders++; /* Account for eDP. */ | |
13723 | ||
13724 | for (i = 0; i < error->num_transcoders; i++) { | |
13725 | enum transcoder cpu_transcoder = transcoders[i]; | |
13726 | ||
ddf9c536 | 13727 | error->transcoder[i].power_domain_on = |
bfafe93a | 13728 | intel_display_power_enabled_unlocked(dev_priv, |
38cc1daf | 13729 | POWER_DOMAIN_TRANSCODER(cpu_transcoder)); |
ddf9c536 | 13730 | if (!error->transcoder[i].power_domain_on) |
9d1cb914 PZ |
13731 | continue; |
13732 | ||
63b66e5b CW |
13733 | error->transcoder[i].cpu_transcoder = cpu_transcoder; |
13734 | ||
13735 | error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder)); | |
13736 | error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder)); | |
13737 | error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder)); | |
13738 | error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder)); | |
13739 | error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder)); | |
13740 | error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder)); | |
13741 | error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder)); | |
c4a1d9e4 CW |
13742 | } |
13743 | ||
13744 | return error; | |
13745 | } | |
13746 | ||
edc3d884 MK |
13747 | #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__) |
13748 | ||
c4a1d9e4 | 13749 | void |
edc3d884 | 13750 | intel_display_print_error_state(struct drm_i915_error_state_buf *m, |
c4a1d9e4 CW |
13751 | struct drm_device *dev, |
13752 | struct intel_display_error_state *error) | |
13753 | { | |
055e393f | 13754 | struct drm_i915_private *dev_priv = dev->dev_private; |
c4a1d9e4 CW |
13755 | int i; |
13756 | ||
63b66e5b CW |
13757 | if (!error) |
13758 | return; | |
13759 | ||
edc3d884 | 13760 | err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes); |
190be112 | 13761 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
edc3d884 | 13762 | err_printf(m, "PWR_WELL_CTL2: %08x\n", |
ff57f1b0 | 13763 | error->power_well_driver); |
055e393f | 13764 | for_each_pipe(dev_priv, i) { |
edc3d884 | 13765 | err_printf(m, "Pipe [%d]:\n", i); |
ddf9c536 ID |
13766 | err_printf(m, " Power: %s\n", |
13767 | error->pipe[i].power_domain_on ? "on" : "off"); | |
edc3d884 | 13768 | err_printf(m, " SRC: %08x\n", error->pipe[i].source); |
f301b1e1 | 13769 | err_printf(m, " STAT: %08x\n", error->pipe[i].stat); |
edc3d884 MK |
13770 | |
13771 | err_printf(m, "Plane [%d]:\n", i); | |
13772 | err_printf(m, " CNTR: %08x\n", error->plane[i].control); | |
13773 | err_printf(m, " STRIDE: %08x\n", error->plane[i].stride); | |
80ca378b | 13774 | if (INTEL_INFO(dev)->gen <= 3) { |
edc3d884 MK |
13775 | err_printf(m, " SIZE: %08x\n", error->plane[i].size); |
13776 | err_printf(m, " POS: %08x\n", error->plane[i].pos); | |
80ca378b | 13777 | } |
4b71a570 | 13778 | if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) |
edc3d884 | 13779 | err_printf(m, " ADDR: %08x\n", error->plane[i].addr); |
c4a1d9e4 | 13780 | if (INTEL_INFO(dev)->gen >= 4) { |
edc3d884 MK |
13781 | err_printf(m, " SURF: %08x\n", error->plane[i].surface); |
13782 | err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset); | |
c4a1d9e4 CW |
13783 | } |
13784 | ||
edc3d884 MK |
13785 | err_printf(m, "Cursor [%d]:\n", i); |
13786 | err_printf(m, " CNTR: %08x\n", error->cursor[i].control); | |
13787 | err_printf(m, " POS: %08x\n", error->cursor[i].position); | |
13788 | err_printf(m, " BASE: %08x\n", error->cursor[i].base); | |
c4a1d9e4 | 13789 | } |
63b66e5b CW |
13790 | |
13791 | for (i = 0; i < error->num_transcoders; i++) { | |
1cf84bb6 | 13792 | err_printf(m, "CPU transcoder: %c\n", |
63b66e5b | 13793 | transcoder_name(error->transcoder[i].cpu_transcoder)); |
ddf9c536 ID |
13794 | err_printf(m, " Power: %s\n", |
13795 | error->transcoder[i].power_domain_on ? "on" : "off"); | |
63b66e5b CW |
13796 | err_printf(m, " CONF: %08x\n", error->transcoder[i].conf); |
13797 | err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal); | |
13798 | err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank); | |
13799 | err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync); | |
13800 | err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal); | |
13801 | err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank); | |
13802 | err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync); | |
13803 | } | |
c4a1d9e4 | 13804 | } |
e2fcdaa9 VS |
13805 | |
13806 | void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file) | |
13807 | { | |
13808 | struct intel_crtc *crtc; | |
13809 | ||
13810 | for_each_intel_crtc(dev, crtc) { | |
13811 | struct intel_unpin_work *work; | |
13812 | unsigned long irqflags; | |
13813 | ||
13814 | spin_lock_irqsave(&dev->event_lock, irqflags); | |
13815 | ||
13816 | work = crtc->unpin_work; | |
13817 | ||
13818 | if (work && work->event && | |
13819 | work->event->base.file_priv == file) { | |
13820 | kfree(work->event); | |
13821 | work->event = NULL; | |
13822 | } | |
13823 | ||
13824 | spin_unlock_irqrestore(&dev->event_lock, irqflags); | |
13825 | } | |
13826 | } |