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drm/i915: replace ad-hoc dual-link lvds checks
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 75 int, int, intel_clock_t *, intel_clock_t *);
d4906093 76};
79e53945 77
2377b741
JB		 78/* FDI */
79#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
80
d2acd215
DV		 81int
82intel_pch_rawclk(struct drm_device *dev)
83{
84 struct drm_i915_private *dev_priv = dev->dev_private;
85
86 WARN_ON(!HAS_PCH_SPLIT(dev));
87
88 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
89}
90
d4906093
ML		 91static bool
92intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 93 int target, int refclk, intel_clock_t *match_clock,
94 intel_clock_t *best_clock);
d4906093
ML		 95static bool
96intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
79e53945 99
a4fc5ed6
KP		 100static bool
101intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 102 int target, int refclk, intel_clock_t *match_clock,
103 intel_clock_t *best_clock);
5eb08b69 104static bool
f2b115e6 105intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
a4fc5ed6 108
a0c4da24
JB		 109static bool
110intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111 int target, int refclk, intel_clock_t *match_clock,
112 intel_clock_t *best_clock);
113
021357ac
CW		 114static inline u32 /* units of 100MHz */
115intel_fdi_link_freq(struct drm_device *dev)
116{
8b99e68c
CW		 117 if (IS_GEN5(dev)) {
118 struct drm_i915_private *dev_priv = dev->dev_private;
119 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
120 } else
121 return 27;
021357ac
CW		 122}
123
e4b36699 124static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 125 .dot = { .min = 25000, .max = 350000 },
126 .vco = { .min = 930000, .max = 1400000 },
127 .n = { .min = 3, .max = 16 },
128 .m = { .min = 96, .max = 140 },
129 .m1 = { .min = 18, .max = 26 },
130 .m2 = { .min = 6, .max = 16 },
131 .p = { .min = 4, .max = 128 },
132 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 133 .p2 = { .dot_limit = 165000,
134 .p2_slow = 4, .p2_fast = 2 },
d4906093 135 .find_pll = intel_find_best_PLL,
e4b36699
KP		 136};
137
138static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 930000, .max = 1400000 },
141 .n = { .min = 3, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 14, .p2_fast = 7 },
d4906093 149 .find_pll = intel_find_best_PLL,
e4b36699 150};
273e27ca 151
e4b36699 152static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 153 .dot = { .min = 20000, .max = 400000 },
154 .vco = { .min = 1400000, .max = 2800000 },
155 .n = { .min = 1, .max = 6 },
156 .m = { .min = 70, .max = 120 },
157 .m1 = { .min = 10, .max = 22 },
158 .m2 = { .min = 5, .max = 9 },
159 .p = { .min = 5, .max = 80 },
160 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 161 .p2 = { .dot_limit = 200000,
162 .p2_slow = 10, .p2_fast = 5 },
d4906093 163 .find_pll = intel_find_best_PLL,
e4b36699
KP		 164};
165
166static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 167 .dot = { .min = 20000, .max = 400000 },
168 .vco = { .min = 1400000, .max = 2800000 },
169 .n = { .min = 1, .max = 6 },
170 .m = { .min = 70, .max = 120 },
171 .m1 = { .min = 10, .max = 22 },
172 .m2 = { .min = 5, .max = 9 },
173 .p = { .min = 7, .max = 98 },
174 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 175 .p2 = { .dot_limit = 112000,
176 .p2_slow = 14, .p2_fast = 7 },
d4906093 177 .find_pll = intel_find_best_PLL,
e4b36699
KP		 178};
179
273e27ca 180
e4b36699 181static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 182 .dot = { .min = 25000, .max = 270000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 17, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 10, .max = 30 },
189 .p1 = { .min = 1, .max = 3},
190 .p2 = { .dot_limit = 270000,
191 .p2_slow = 10,
192 .p2_fast = 10
044c7c41 193 },
d4906093 194 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 195};
196
197static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 198 .dot = { .min = 22000, .max = 400000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 16, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8},
206 .p2 = { .dot_limit = 165000,
207 .p2_slow = 10, .p2_fast = 5 },
d4906093 208 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 212 .dot = { .min = 20000, .max = 115000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 28, .max = 112 },
219 .p1 = { .min = 2, .max = 8 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 14, .p2_fast = 14
044c7c41 222 },
d4906093 223 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 224};
225
226static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 227 .dot = { .min = 80000, .max = 224000 },
228 .vco = { .min = 1750000, .max = 3500000 },
229 .n = { .min = 1, .max = 3 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 14, .max = 42 },
234 .p1 = { .min = 2, .max = 6 },
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 7, .p2_fast = 7
044c7c41 237 },
d4906093 238 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 239};
240
241static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 242 .dot = { .min = 161670, .max = 227000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 2 },
245 .m = { .min = 97, .max = 108 },
246 .m1 = { .min = 0x10, .max = 0x12 },
247 .m2 = { .min = 0x05, .max = 0x06 },
248 .p = { .min = 10, .max = 20 },
249 .p1 = { .min = 1, .max = 2},
250 .p2 = { .dot_limit = 0,
273e27ca 251 .p2_slow = 10, .p2_fast = 10 },
0206e353 252 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 253};
254
f2b115e6 255static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 256 .dot = { .min = 20000, .max = 400000},
257 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 258 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
273e27ca 261 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 262 .m1 = { .min = 0, .max = 0 },
263 .m2 = { .min = 0, .max = 254 },
264 .p = { .min = 5, .max = 80 },
265 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 266 .p2 = { .dot_limit = 200000,
267 .p2_slow = 10, .p2_fast = 5 },
6115707b 268 .find_pll = intel_find_best_PLL,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000 },
273 .vco = { .min = 1700000, .max = 3500000 },
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 7, .max = 112 },
279 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 280 .p2 = { .dot_limit = 112000,
281 .p2_slow = 14, .p2_fast = 14 },
6115707b 282 .find_pll = intel_find_best_PLL,
e4b36699
KP		 283};
284
273e27ca
EA		 285/* Ironlake / Sandybridge
286 *
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
289 */
b91ad0ec 290static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 5 },
294 .m = { .min = 79, .max = 127 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 10, .p2_fast = 5 },
4547668a 301 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 302};
303
b91ad0ec 304static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 3 },
308 .m = { .min = 79, .max = 118 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 28, .max = 112 },
312 .p1 = { .min = 2, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 315 .find_pll = intel_g4x_find_best_PLL,
316};
317
318static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 127 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 14, .max = 56 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 329 .find_pll = intel_g4x_find_best_PLL,
330};
331
273e27ca 332/* LVDS 100mhz refclk limits. */
b91ad0ec 333static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
0206e353 341 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 344 .find_pll = intel_g4x_find_best_PLL,
345};
346
347static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
0206e353 355 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 358 .find_pll = intel_g4x_find_best_PLL,
359};
360
361static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 362 .dot = { .min = 25000, .max = 350000 },
363 .vco = { .min = 1760000, .max = 3510000},
364 .n = { .min = 1, .max = 2 },
365 .m = { .min = 81, .max = 90 },
366 .m1 = { .min = 12, .max = 22 },
367 .m2 = { .min = 5, .max = 9 },
368 .p = { .min = 10, .max = 20 },
369 .p1 = { .min = 1, .max = 2},
370 .p2 = { .dot_limit = 0,
273e27ca 371 .p2_slow = 10, .p2_fast = 10 },
0206e353 372 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 373};
374
a0c4da24
JB		 375static const intel_limit_t intel_limits_vlv_dac = {
376 .dot = { .min = 25000, .max = 270000 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m = { .min = 22, .max = 450 }, /* guess */
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p = { .min = 10, .max = 30 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .dot_limit = 270000,
385 .p2_slow = 2, .p2_fast = 20 },
386 .find_pll = intel_vlv_find_best_pll,
387};
388
389static const intel_limit_t intel_limits_vlv_hdmi = {
390 .dot = { .min = 20000, .max = 165000 },
17dc9257 391 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 392 .n = { .min = 1, .max = 7 },
393 .m = { .min = 60, .max = 300 }, /* guess */
394 .m1 = { .min = 2, .max = 3 },
395 .m2 = { .min = 11, .max = 156 },
396 .p = { .min = 10, .max = 30 },
397 .p1 = { .min = 2, .max = 3 },
398 .p2 = { .dot_limit = 270000,
399 .p2_slow = 2, .p2_fast = 20 },
400 .find_pll = intel_vlv_find_best_pll,
401};
402
403static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 404 .dot = { .min = 25000, .max = 270000 },
405 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 406 .n = { .min = 1, .max = 7 },
74a4dd2e 407 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 408 .m1 = { .min = 2, .max = 3 },
409 .m2 = { .min = 11, .max = 156 },
410 .p = { .min = 10, .max = 30 },
411 .p1 = { .min = 2, .max = 3 },
412 .p2 = { .dot_limit = 270000,
413 .p2_slow = 2, .p2_fast = 20 },
414 .find_pll = intel_vlv_find_best_pll,
415};
416
57f350b6
JB		 417u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
418{
419 unsigned long flags;
420 u32 val = 0;
421
422 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO idle wait timed out\n");
425 goto out_unlock;
426 }
427
428 I915_WRITE(DPIO_REG, reg);
429 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
430 DPIO_BYTE);
431 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
432 DRM_ERROR("DPIO read wait timed out\n");
433 goto out_unlock;
434 }
435 val = I915_READ(DPIO_DATA);
436
437out_unlock:
438 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
439 return val;
440}
441
a0c4da24
JB		 442static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
443 u32 val)
444{
445 unsigned long flags;
446
447 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
448 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
449 DRM_ERROR("DPIO idle wait timed out\n");
450 goto out_unlock;
451 }
452
453 I915_WRITE(DPIO_DATA, val);
454 I915_WRITE(DPIO_REG, reg);
455 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
456 DPIO_BYTE);
457 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
458 DRM_ERROR("DPIO write wait timed out\n");
459
460out_unlock:
461 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
462}
463
57f350b6
JB		 464static void vlv_init_dpio(struct drm_device *dev)
465{
466 struct drm_i915_private *dev_priv = dev->dev_private;
467
468 /* Reset the DPIO config */
469 I915_WRITE(DPIO_CTL, 0);
470 POSTING_READ(DPIO_CTL);
471 I915_WRITE(DPIO_CTL, 1);
472 POSTING_READ(DPIO_CTL);
473}
474
618563e3
DV		 475static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
476{
477 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
478 return 1;
479}
480
481static const struct dmi_system_id intel_dual_link_lvds[] = {
482 {
483 .callback = intel_dual_link_lvds_callback,
484 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
485 .matches = {
486 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
487 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
488 },
489 },
490 { } /* terminating entry */
491};
492
b0354385
TI		 493static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
494 unsigned int reg)
495{
496 unsigned int val;
497
121d527a
TI		 498 /* use the module option value if specified */
499 if (i915_lvds_channel_mode > 0)
500 return i915_lvds_channel_mode == 2;
501
618563e3
DV		 502 if (dmi_check_system(intel_dual_link_lvds))
503 return true;
504
b0354385
TI		 505 if (dev_priv->lvds_val)
506 val = dev_priv->lvds_val;
507 else {
508 /* BIOS should set the proper LVDS register value at boot, but
509 * in reality, it doesn't set the value when the lid is closed;
510 * we need to check "the value to be set" in VBT when LVDS
511 * register is uninitialized.
512 */
513 val = I915_READ(reg);
14d94a3d 514 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 515 val = dev_priv->bios_lvds_val;
516 dev_priv->lvds_val = val;
517 }
518 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
519}
520
1b894b59
CW		 521static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
522 int refclk)
2c07245f 523{
b91ad0ec
ZW		 524 struct drm_device *dev = crtc->dev;
525 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 526 const intel_limit_t *limit;
b91ad0ec
ZW		 527
528 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 529 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 530 /* LVDS dual channel */
1b894b59 531 if (refclk == 100000)
b91ad0ec
ZW		 532 limit = &intel_limits_ironlake_dual_lvds_100m;
533 else
534 limit = &intel_limits_ironlake_dual_lvds;
535 } else {
1b894b59 536 if (refclk == 100000)
b91ad0ec
ZW		 537 limit = &intel_limits_ironlake_single_lvds_100m;
538 else
539 limit = &intel_limits_ironlake_single_lvds;
540 }
541 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 542 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 543 limit = &intel_limits_ironlake_display_port;
2c07245f 544 else
b91ad0ec 545 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 546
547 return limit;
548}
549
044c7c41
ML		 550static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
551{
552 struct drm_device *dev = crtc->dev;
553 struct drm_i915_private *dev_priv = dev->dev_private;
554 const intel_limit_t *limit;
555
556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 557 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 558 /* LVDS with dual channel */
e4b36699 559 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 560 else
561 /* LVDS with dual channel */
e4b36699 562 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 563 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
564 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 565 limit = &intel_limits_g4x_hdmi;
044c7c41 566 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 567 limit = &intel_limits_g4x_sdvo;
0206e353 568 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 569 limit = &intel_limits_g4x_display_port;
044c7c41 570 } else /* The option is for other outputs */
e4b36699 571 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 572
573 return limit;
574}
575
1b894b59 576static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 577{
578 struct drm_device *dev = crtc->dev;
579 const intel_limit_t *limit;
580
bad720ff 581 if (HAS_PCH_SPLIT(dev))
1b894b59 582 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 583 else if (IS_G4X(dev)) {
044c7c41 584 limit = intel_g4x_limit(crtc);
f2b115e6 585 } else if (IS_PINEVIEW(dev)) {
2177832f 586 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 587 limit = &intel_limits_pineview_lvds;
2177832f 588 else
f2b115e6 589 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 590 } else if (IS_VALLEYVIEW(dev)) {
591 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
592 limit = &intel_limits_vlv_dac;
593 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
594 limit = &intel_limits_vlv_hdmi;
595 else
596 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 597 } else if (!IS_GEN2(dev)) {
598 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
599 limit = &intel_limits_i9xx_lvds;
600 else
601 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 602 } else {
603 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 604 limit = &intel_limits_i8xx_lvds;
79e53945 605 else
e4b36699 606 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 607 }
608 return limit;
609}
610
f2b115e6
AJ		 611/* m1 is reserved as 0 in Pineview, n is a ring counter */
612static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 613{
2177832f
SL		 614 clock->m = clock->m2 + 2;
615 clock->p = clock->p1 * clock->p2;
616 clock->vco = refclk * clock->m / clock->n;
617 clock->dot = clock->vco / clock->p;
618}
619
620static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
621{
f2b115e6
AJ		 622 if (IS_PINEVIEW(dev)) {
623 pineview_clock(refclk, clock);
2177832f
SL		 624 return;
625 }
79e53945
JB		 626 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
627 clock->p = clock->p1 * clock->p2;
628 clock->vco = refclk * clock->m / (clock->n + 2);
629 clock->dot = clock->vco / clock->p;
630}
631
79e53945
JB		 632/**
633 * Returns whether any output on the specified pipe is of the specified type
634 */
4ef69c7a 635bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 636{
4ef69c7a 637 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 638 struct intel_encoder *encoder;
639
6c2b7c12
DV		 640 for_each_encoder_on_crtc(dev, crtc, encoder)
641 if (encoder->type == type)
4ef69c7a
CW		 642 return true;
643
644 return false;
79e53945
JB		 645}
646
7c04d1d9 647#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 648/**
649 * Returns whether the given set of divisors are valid for a given refclk with
650 * the given connectors.
651 */
652
1b894b59
CW		 653static bool intel_PLL_is_valid(struct drm_device *dev,
654 const intel_limit_t *limit,
655 const intel_clock_t *clock)
79e53945 656{
79e53945 657 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 658 INTELPllInvalid("p1 out of range\n");
79e53945 659 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 660 INTELPllInvalid("p out of range\n");
79e53945 661 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 662 INTELPllInvalid("m2 out of range\n");
79e53945 663 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 664 INTELPllInvalid("m1 out of range\n");
f2b115e6 665 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 666 INTELPllInvalid("m1 <= m2\n");
79e53945 667 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 668 INTELPllInvalid("m out of range\n");
79e53945 669 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 670 INTELPllInvalid("n out of range\n");
79e53945 671 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 672 INTELPllInvalid("vco out of range\n");
79e53945
JB		 673 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
674 * connector, etc., rather than just a single range.
675 */
676 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 677 INTELPllInvalid("dot out of range\n");
79e53945
JB		 678
679 return true;
680}
681
d4906093
ML		 682static bool
683intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 684 int target, int refclk, intel_clock_t *match_clock,
685 intel_clock_t *best_clock)
d4906093 686
79e53945
JB		 687{
688 struct drm_device *dev = crtc->dev;
689 struct drm_i915_private *dev_priv = dev->dev_private;
690 intel_clock_t clock;
79e53945
JB		 691 int err = target;
692
a210b028 693 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 694 /*
a210b028
DV		 695 * For LVDS just rely on its current settings for dual-channel.
696 * We haven't figured out how to reliably set up different
697 * single/dual channel state, if we even can.
79e53945 698 */
b0354385 699 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 700 clock.p2 = limit->p2.p2_fast;
701 else
702 clock.p2 = limit->p2.p2_slow;
703 } else {
704 if (target < limit->p2.dot_limit)
705 clock.p2 = limit->p2.p2_slow;
706 else
707 clock.p2 = limit->p2.p2_fast;
708 }
709
0206e353 710 memset(best_clock, 0, sizeof(*best_clock));
79e53945 711
42158660
ZY		 712 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
713 clock.m1++) {
714 for (clock.m2 = limit->m2.min;
715 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 716 /* m1 is always 0 in Pineview */
717 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 718 break;
719 for (clock.n = limit->n.min;
720 clock.n <= limit->n.max; clock.n++) {
721 for (clock.p1 = limit->p1.min;
722 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 723 int this_err;
724
2177832f 725 intel_clock(dev, refclk, &clock);
1b894b59
CW		 726 if (!intel_PLL_is_valid(dev, limit,
727 &clock))
79e53945 728 continue;
cec2f356
SP		 729 if (match_clock &&
730 clock.p != match_clock->p)
731 continue;
79e53945
JB		 732
733 this_err = abs(clock.dot - target);
734 if (this_err < err) {
735 *best_clock = clock;
736 err = this_err;
737 }
738 }
739 }
740 }
741 }
742
743 return (err != target);
744}
745
d4906093
ML		 746static bool
747intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 748 int target, int refclk, intel_clock_t *match_clock,
749 intel_clock_t *best_clock)
d4906093
ML		 750{
751 struct drm_device *dev = crtc->dev;
752 struct drm_i915_private *dev_priv = dev->dev_private;
753 intel_clock_t clock;
754 int max_n;
755 bool found;
6ba770dc
AJ		 756 /* approximately equals target * 0.00585 */
757 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 758 found = false;
759
760 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 761 int lvds_reg;
762
c619eed4 763 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 764 lvds_reg = PCH_LVDS;
765 else
766 lvds_reg = LVDS;
a210b028 767 if (is_dual_link_lvds(dev_priv, lvds_reg))
d4906093
ML		 768 clock.p2 = limit->p2.p2_fast;
769 else
770 clock.p2 = limit->p2.p2_slow;
771 } else {
772 if (target < limit->p2.dot_limit)
773 clock.p2 = limit->p2.p2_slow;
774 else
775 clock.p2 = limit->p2.p2_fast;
776 }
777
778 memset(best_clock, 0, sizeof(*best_clock));
779 max_n = limit->n.max;
f77f13e2 780 /* based on hardware requirement, prefer smaller n to precision */
d4906093 781 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 782 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 783 for (clock.m1 = limit->m1.max;
784 clock.m1 >= limit->m1.min; clock.m1--) {
785 for (clock.m2 = limit->m2.max;
786 clock.m2 >= limit->m2.min; clock.m2--) {
787 for (clock.p1 = limit->p1.max;
788 clock.p1 >= limit->p1.min; clock.p1--) {
789 int this_err;
790
2177832f 791 intel_clock(dev, refclk, &clock);
1b894b59
CW		 792 if (!intel_PLL_is_valid(dev, limit,
793 &clock))
d4906093 794 continue;
cec2f356
SP		 795 if (match_clock &&
796 clock.p != match_clock->p)
797 continue;
1b894b59
CW		 798
799 this_err = abs(clock.dot - target);
d4906093
ML		 800 if (this_err < err_most) {
801 *best_clock = clock;
802 err_most = this_err;
803 max_n = clock.n;
804 found = true;
805 }
806 }
807 }
808 }
809 }
2c07245f
ZW		 810 return found;
811}
812
5eb08b69 813static bool
f2b115e6 814intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 815 int target, int refclk, intel_clock_t *match_clock,
816 intel_clock_t *best_clock)
5eb08b69
ZW		 817{
818 struct drm_device *dev = crtc->dev;
819 intel_clock_t clock;
4547668a 820
5eb08b69
ZW		 821 if (target < 200000) {
822 clock.n = 1;
823 clock.p1 = 2;
824 clock.p2 = 10;
825 clock.m1 = 12;
826 clock.m2 = 9;
827 } else {
828 clock.n = 2;
829 clock.p1 = 1;
830 clock.p2 = 10;
831 clock.m1 = 14;
832 clock.m2 = 8;
833 }
834 intel_clock(dev, refclk, &clock);
835 memcpy(best_clock, &clock, sizeof(intel_clock_t));
836 return true;
837}
838
a4fc5ed6
KP		 839/* DisplayPort has only two frequencies, 162MHz and 270MHz */
840static bool
841intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 842 int target, int refclk, intel_clock_t *match_clock,
843 intel_clock_t *best_clock)
a4fc5ed6 844{
5eddb70b
CW		 845 intel_clock_t clock;
846 if (target < 200000) {
847 clock.p1 = 2;
848 clock.p2 = 10;
849 clock.n = 2;
850 clock.m1 = 23;
851 clock.m2 = 8;
852 } else {
853 clock.p1 = 1;
854 clock.p2 = 10;
855 clock.n = 1;
856 clock.m1 = 14;
857 clock.m2 = 2;
858 }
859 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
860 clock.p = (clock.p1 * clock.p2);
861 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
862 clock.vco = 0;
863 memcpy(best_clock, &clock, sizeof(intel_clock_t));
864 return true;
a4fc5ed6 865}
a0c4da24
JB		 866static bool
867intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
868 int target, int refclk, intel_clock_t *match_clock,
869 intel_clock_t *best_clock)
870{
871 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
872 u32 m, n, fastclk;
873 u32 updrate, minupdate, fracbits, p;
874 unsigned long bestppm, ppm, absppm;
875 int dotclk, flag;
876
af447bd3 877 flag = 0;
a0c4da24
JB		 878 dotclk = target * 1000;
879 bestppm = 1000000;
880 ppm = absppm = 0;
881 fastclk = dotclk / (2*100);
882 updrate = 0;
883 minupdate = 19200;
884 fracbits = 1;
885 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
886 bestm1 = bestm2 = bestp1 = bestp2 = 0;
887
888 /* based on hardware requirement, prefer smaller n to precision */
889 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
890 updrate = refclk / n;
891 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
892 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
893 if (p2 > 10)
894 p2 = p2 - 1;
895 p = p1 * p2;
896 /* based on hardware requirement, prefer bigger m1,m2 values */
897 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
898 m2 = (((2*(fastclk * p * n / m1 )) +
899 refclk) / (2*refclk));
900 m = m1 * m2;
901 vco = updrate * m;
902 if (vco >= limit->vco.min && vco < limit->vco.max) {
903 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
904 absppm = (ppm > 0) ? ppm : (-ppm);
905 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
906 bestppm = 0;
907 flag = 1;
908 }
909 if (absppm < bestppm - 10) {
910 bestppm = absppm;
911 flag = 1;
912 }
913 if (flag) {
914 bestn = n;
915 bestm1 = m1;
916 bestm2 = m2;
917 bestp1 = p1;
918 bestp2 = p2;
919 flag = 0;
920 }
921 }
922 }
923 }
924 }
925 }
926 best_clock->n = bestn;
927 best_clock->m1 = bestm1;
928 best_clock->m2 = bestm2;
929 best_clock->p1 = bestp1;
930 best_clock->p2 = bestp2;
931
932 return true;
933}
a4fc5ed6 934
a5c961d1
PZ		 935enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
936 enum pipe pipe)
937{
938 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
939 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
940
941 return intel_crtc->cpu_transcoder;
942}
943
a928d536
PZ		 944static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
945{
946 struct drm_i915_private *dev_priv = dev->dev_private;
947 u32 frame, frame_reg = PIPEFRAME(pipe);
948
949 frame = I915_READ(frame_reg);
950
951 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
952 DRM_DEBUG_KMS("vblank wait timed out\n");
953}
954
9d0498a2
JB		 955/**
956 * intel_wait_for_vblank - wait for vblank on a given pipe
957 * @dev: drm device
958 * @pipe: pipe to wait for
959 *
960 * Wait for vblank to occur on a given pipe. Needed for various bits of
961 * mode setting code.
962 */
963void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 964{
9d0498a2 965 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 966 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 967
a928d536
PZ		 968 if (INTEL_INFO(dev)->gen >= 5) {
969 ironlake_wait_for_vblank(dev, pipe);
970 return;
971 }
972
300387c0
CW		 973 /* Clear existing vblank status. Note this will clear any other
974 * sticky status fields as well.
975 *
976 * This races with i915_driver_irq_handler() with the result
977 * that either function could miss a vblank event. Here it is not
978 * fatal, as we will either wait upon the next vblank interrupt or
979 * timeout. Generally speaking intel_wait_for_vblank() is only
980 * called during modeset at which time the GPU should be idle and
981 * should *not* be performing page flips and thus not waiting on
982 * vblanks...
983 * Currently, the result of us stealing a vblank from the irq
984 * handler is that a single frame will be skipped during swapbuffers.
985 */
986 I915_WRITE(pipestat_reg,
987 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
988
9d0498a2 989 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 990 if (wait_for(I915_READ(pipestat_reg) &
991 PIPE_VBLANK_INTERRUPT_STATUS,
992 50))
9d0498a2
JB		 993 DRM_DEBUG_KMS("vblank wait timed out\n");
994}
995
ab7ad7f6
KP		 996/*
997 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 998 * @dev: drm device
999 * @pipe: pipe to wait for
1000 *
1001 * After disabling a pipe, we can't wait for vblank in the usual way,
1002 * spinning on the vblank interrupt status bit, since we won't actually
1003 * see an interrupt when the pipe is disabled.
1004 *
ab7ad7f6
KP		 1005 * On Gen4 and above:
1006 * wait for the pipe register state bit to turn off
1007 *
1008 * Otherwise:
1009 * wait for the display line value to settle (it usually
1010 * ends up stopping at the start of the next frame).
58e10eb9 1011 *
9d0498a2 1012 */
58e10eb9 1013void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1014{
1015 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 1016 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1017 pipe);
ab7ad7f6
KP		 1018
1019 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1020 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1021
1022 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1023 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1024 100))
284637d9 1025 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1026 } else {
837ba00f 1027 u32 last_line, line_mask;
58e10eb9 1028 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1029 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1030
837ba00f
PZ		 1031 if (IS_GEN2(dev))
1032 line_mask = DSL_LINEMASK_GEN2;
1033 else
1034 line_mask = DSL_LINEMASK_GEN3;
1035
ab7ad7f6
KP		 1036 /* Wait for the display line to settle */
1037 do {
837ba00f 1038 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1039 mdelay(5);
837ba00f 1040 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1041 time_after(timeout, jiffies));
1042 if (time_after(jiffies, timeout))
284637d9 1043 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1044 }
79e53945
JB		 1045}
1046
b24e7179
JB		 1047static const char *state_string(bool enabled)
1048{
1049 return enabled ? "on" : "off";
1050}
1051
1052/* Only for pre-ILK configs */
1053static void assert_pll(struct drm_i915_private *dev_priv,
1054 enum pipe pipe, bool state)
1055{
1056 int reg;
1057 u32 val;
1058 bool cur_state;
1059
1060 reg = DPLL(pipe);
1061 val = I915_READ(reg);
1062 cur_state = !!(val & DPLL_VCO_ENABLE);
1063 WARN(cur_state != state,
1064 "PLL state assertion failure (expected %s, current %s)\n",
1065 state_string(state), state_string(cur_state));
1066}
1067#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1068#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1069
040484af
JB		 1070/* For ILK+ */
1071static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1072 struct intel_pch_pll *pll,
1073 struct intel_crtc *crtc,
1074 bool state)
040484af 1075{
040484af
JB		 1076 u32 val;
1077 bool cur_state;
1078
9d82aa17
ED		 1079 if (HAS_PCH_LPT(dev_priv->dev)) {
1080 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1081 return;
1082 }
1083
92b27b08
CW		 1084 if (WARN (!pll,
1085 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1086 return;
ee7b9f93 1087
92b27b08
CW		 1088 val = I915_READ(pll->pll_reg);
1089 cur_state = !!(val & DPLL_VCO_ENABLE);
1090 WARN(cur_state != state,
1091 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1092 pll->pll_reg, state_string(state), state_string(cur_state), val);
1093
1094 /* Make sure the selected PLL is correctly attached to the transcoder */
1095 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1096 u32 pch_dpll;
1097
1098 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1099 cur_state = pll->pll_reg == _PCH_DPLL_B;
1100 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1101 "PLL[%d] not attached to this transcoder %d: %08x\n",
1102 cur_state, crtc->pipe, pch_dpll)) {
1103 cur_state = !!(val >> (4*crtc->pipe + 3));
1104 WARN(cur_state != state,
1105 "PLL[%d] not %s on this transcoder %d: %08x\n",
1106 pll->pll_reg == _PCH_DPLL_B,
1107 state_string(state),
1108 crtc->pipe,
1109 val);
1110 }
d3ccbe86 1111 }
040484af 1112}
92b27b08
CW		 1113#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1114#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1115
1116static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1117 enum pipe pipe, bool state)
1118{
1119 int reg;
1120 u32 val;
1121 bool cur_state;
ad80a810
PZ		 1122 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1123 pipe);
040484af 1124
bf507ef7
ED		 1125 if (IS_HASWELL(dev_priv->dev)) {
1126 /* On Haswell, DDI is used instead of FDI_TX_CTL */
ad80a810 1127 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1128 val = I915_READ(reg);
ad80a810 1129 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1130 } else {
1131 reg = FDI_TX_CTL(pipe);
1132 val = I915_READ(reg);
1133 cur_state = !!(val & FDI_TX_ENABLE);
1134 }
040484af
JB		 1135 WARN(cur_state != state,
1136 "FDI TX state assertion failure (expected %s, current %s)\n",
1137 state_string(state), state_string(cur_state));
1138}
1139#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1140#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1141
1142static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1143 enum pipe pipe, bool state)
1144{
1145 int reg;
1146 u32 val;
1147 bool cur_state;
1148
d63fa0dc
PZ		 1149 reg = FDI_RX_CTL(pipe);
1150 val = I915_READ(reg);
1151 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1152 WARN(cur_state != state,
1153 "FDI RX state assertion failure (expected %s, current %s)\n",
1154 state_string(state), state_string(cur_state));
1155}
1156#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1157#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1158
1159static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1160 enum pipe pipe)
1161{
1162 int reg;
1163 u32 val;
1164
1165 /* ILK FDI PLL is always enabled */
1166 if (dev_priv->info->gen == 5)
1167 return;
1168
bf507ef7
ED		 1169 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1170 if (IS_HASWELL(dev_priv->dev))
1171 return;
1172
040484af
JB		 1173 reg = FDI_TX_CTL(pipe);
1174 val = I915_READ(reg);
1175 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1176}
1177
1178static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1179 enum pipe pipe)
1180{
1181 int reg;
1182 u32 val;
1183
1184 reg = FDI_RX_CTL(pipe);
1185 val = I915_READ(reg);
1186 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1187}
1188
ea0760cf
JB		 1189static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1190 enum pipe pipe)
1191{
1192 int pp_reg, lvds_reg;
1193 u32 val;
1194 enum pipe panel_pipe = PIPE_A;
0de3b485 1195 bool locked = true;
ea0760cf
JB		 1196
1197 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1198 pp_reg = PCH_PP_CONTROL;
1199 lvds_reg = PCH_LVDS;
1200 } else {
1201 pp_reg = PP_CONTROL;
1202 lvds_reg = LVDS;
1203 }
1204
1205 val = I915_READ(pp_reg);
1206 if (!(val & PANEL_POWER_ON) ||
1207 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1208 locked = false;
1209
1210 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1211 panel_pipe = PIPE_B;
1212
1213 WARN(panel_pipe == pipe && locked,
1214 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1215 pipe_name(pipe));
ea0760cf
JB		 1216}
1217
b840d907
JB		 1218void assert_pipe(struct drm_i915_private *dev_priv,
1219 enum pipe pipe, bool state)
b24e7179
JB		 1220{
1221 int reg;
1222 u32 val;
63d7bbe9 1223 bool cur_state;
702e7a56
PZ		 1224 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1225 pipe);
b24e7179 1226
8e636784
DV		 1227 /* if we need the pipe A quirk it must be always on */
1228 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1229 state = true;
1230
702e7a56 1231 reg = PIPECONF(cpu_transcoder);
b24e7179 1232 val = I915_READ(reg);
63d7bbe9
JB		 1233 cur_state = !!(val & PIPECONF_ENABLE);
1234 WARN(cur_state != state,
1235 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1236 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1237}
1238
931872fc
CW		 1239static void assert_plane(struct drm_i915_private *dev_priv,
1240 enum plane plane, bool state)
b24e7179
JB		 1241{
1242 int reg;
1243 u32 val;
931872fc 1244 bool cur_state;
b24e7179
JB		 1245
1246 reg = DSPCNTR(plane);
1247 val = I915_READ(reg);
931872fc
CW		 1248 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1249 WARN(cur_state != state,
1250 "plane %c assertion failure (expected %s, current %s)\n",
1251 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1252}
1253
931872fc
CW		 1254#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1255#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1256
b24e7179
JB		 1257static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1258 enum pipe pipe)
1259{
1260 int reg, i;
1261 u32 val;
1262 int cur_pipe;
1263
19ec1358 1264 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1265 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1266 reg = DSPCNTR(pipe);
1267 val = I915_READ(reg);
1268 WARN((val & DISPLAY_PLANE_ENABLE),
1269 "plane %c assertion failure, should be disabled but not\n",
1270 plane_name(pipe));
19ec1358 1271 return;
28c05794 1272 }
19ec1358 1273
b24e7179
JB		 1274 /* Need to check both planes against the pipe */
1275 for (i = 0; i < 2; i++) {
1276 reg = DSPCNTR(i);
1277 val = I915_READ(reg);
1278 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1279 DISPPLANE_SEL_PIPE_SHIFT;
1280 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1281 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1282 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1283 }
1284}
1285
92f2584a
JB		 1286static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1287{
1288 u32 val;
1289 bool enabled;
1290
9d82aa17
ED		 1291 if (HAS_PCH_LPT(dev_priv->dev)) {
1292 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1293 return;
1294 }
1295
92f2584a
JB		 1296 val = I915_READ(PCH_DREF_CONTROL);
1297 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1298 DREF_SUPERSPREAD_SOURCE_MASK));
1299 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1300}
1301
1302static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1303 enum pipe pipe)
1304{
1305 int reg;
1306 u32 val;
1307 bool enabled;
1308
1309 reg = TRANSCONF(pipe);
1310 val = I915_READ(reg);
1311 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1312 WARN(enabled,
1313 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1314 pipe_name(pipe));
92f2584a
JB		 1315}
1316
4e634389
KP		 1317static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1318 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1319{
1320 if ((val & DP_PORT_EN) == 0)
1321 return false;
1322
1323 if (HAS_PCH_CPT(dev_priv->dev)) {
1324 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1325 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1326 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1327 return false;
1328 } else {
1329 if ((val & DP_PIPE_MASK) != (pipe << 30))
1330 return false;
1331 }
1332 return true;
1333}
1334
1519b995
KP		 1335static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1336 enum pipe pipe, u32 val)
1337{
1338 if ((val & PORT_ENABLE) == 0)
1339 return false;
1340
1341 if (HAS_PCH_CPT(dev_priv->dev)) {
1342 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1343 return false;
1344 } else {
1345 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1346 return false;
1347 }
1348 return true;
1349}
1350
1351static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1352 enum pipe pipe, u32 val)
1353{
1354 if ((val & LVDS_PORT_EN) == 0)
1355 return false;
1356
1357 if (HAS_PCH_CPT(dev_priv->dev)) {
1358 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1359 return false;
1360 } else {
1361 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1362 return false;
1363 }
1364 return true;
1365}
1366
1367static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1368 enum pipe pipe, u32 val)
1369{
1370 if ((val & ADPA_DAC_ENABLE) == 0)
1371 return false;
1372 if (HAS_PCH_CPT(dev_priv->dev)) {
1373 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1374 return false;
1375 } else {
1376 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1377 return false;
1378 }
1379 return true;
1380}
1381
291906f1 1382static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1383 enum pipe pipe, int reg, u32 port_sel)
291906f1 1384{
47a05eca 1385 u32 val = I915_READ(reg);
4e634389 1386 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1387 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1388 reg, pipe_name(pipe));
de9a35ab 1389
75c5da27
DV		 1390 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1391 && (val & DP_PIPEB_SELECT),
de9a35ab 1392 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1393}
1394
1395static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe, int reg)
1397{
47a05eca 1398 u32 val = I915_READ(reg);
b70ad586 1399 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1400 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1401 reg, pipe_name(pipe));
de9a35ab 1402
75c5da27
DV		 1403 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1404 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1405 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1406}
1407
1408static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1409 enum pipe pipe)
1410{
1411 int reg;
1412 u32 val;
291906f1 1413
f0575e92
KP		 1414 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1415 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1416 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1417
1418 reg = PCH_ADPA;
1419 val = I915_READ(reg);
b70ad586 1420 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1421 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1422 pipe_name(pipe));
291906f1
JB		 1423
1424 reg = PCH_LVDS;
1425 val = I915_READ(reg);
b70ad586 1426 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1427 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1428 pipe_name(pipe));
291906f1
JB		 1429
1430 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1431 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1432 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1433}
1434
63d7bbe9
JB		 1435/**
1436 * intel_enable_pll - enable a PLL
1437 * @dev_priv: i915 private structure
1438 * @pipe: pipe PLL to enable
1439 *
1440 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1441 * make sure the PLL reg is writable first though, since the panel write
1442 * protect mechanism may be enabled.
1443 *
1444 * Note! This is for pre-ILK only.
7434a255
TR		 1445 *
1446 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1447 */
1448static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1449{
1450 int reg;
1451 u32 val;
1452
1453 /* No really, not for ILK+ */
a0c4da24 1454 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1455
1456 /* PLL is protected by panel, make sure we can write it */
1457 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1458 assert_panel_unlocked(dev_priv, pipe);
1459
1460 reg = DPLL(pipe);
1461 val = I915_READ(reg);
1462 val |= DPLL_VCO_ENABLE;
1463
1464 /* We do this three times for luck */
1465 I915_WRITE(reg, val);
1466 POSTING_READ(reg);
1467 udelay(150); /* wait for warmup */
1468 I915_WRITE(reg, val);
1469 POSTING_READ(reg);
1470 udelay(150); /* wait for warmup */
1471 I915_WRITE(reg, val);
1472 POSTING_READ(reg);
1473 udelay(150); /* wait for warmup */
1474}
1475
1476/**
1477 * intel_disable_pll - disable a PLL
1478 * @dev_priv: i915 private structure
1479 * @pipe: pipe PLL to disable
1480 *
1481 * Disable the PLL for @pipe, making sure the pipe is off first.
1482 *
1483 * Note! This is for pre-ILK only.
1484 */
1485static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1486{
1487 int reg;
1488 u32 val;
1489
1490 /* Don't disable pipe A or pipe A PLLs if needed */
1491 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1492 return;
1493
1494 /* Make sure the pipe isn't still relying on us */
1495 assert_pipe_disabled(dev_priv, pipe);
1496
1497 reg = DPLL(pipe);
1498 val = I915_READ(reg);
1499 val &= ~DPLL_VCO_ENABLE;
1500 I915_WRITE(reg, val);
1501 POSTING_READ(reg);
1502}
1503
a416edef
ED		 1504/* SBI access */
1505static void
1506intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1507{
1508 unsigned long flags;
1509
1510 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1511 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1512 100)) {
1513 DRM_ERROR("timeout waiting for SBI to become ready\n");
1514 goto out_unlock;
1515 }
1516
1517 I915_WRITE(SBI_ADDR,
1518 (reg << 16));
1519 I915_WRITE(SBI_DATA,
1520 value);
1521 I915_WRITE(SBI_CTL_STAT,
1522 SBI_BUSY |
1523 SBI_CTL_OP_CRWR);
1524
39fb50f6 1525 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1526 100)) {
1527 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1528 goto out_unlock;
1529 }
1530
1531out_unlock:
1532 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1533}
1534
1535static u32
1536intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1537{
1538 unsigned long flags;
39fb50f6 1539 u32 value = 0;
a416edef
ED		 1540
1541 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1542 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1543 100)) {
1544 DRM_ERROR("timeout waiting for SBI to become ready\n");
1545 goto out_unlock;
1546 }
1547
1548 I915_WRITE(SBI_ADDR,
1549 (reg << 16));
1550 I915_WRITE(SBI_CTL_STAT,
1551 SBI_BUSY |
1552 SBI_CTL_OP_CRRD);
1553
39fb50f6 1554 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1555 100)) {
1556 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1557 goto out_unlock;
1558 }
1559
1560 value = I915_READ(SBI_DATA);
1561
1562out_unlock:
1563 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1564 return value;
1565}
1566
92f2584a 1567/**
b6b4e185 1568 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1569 * @dev_priv: i915 private structure
1570 * @pipe: pipe PLL to enable
1571 *
1572 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1573 * drives the transcoder clock.
1574 */
b6b4e185 1575static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1576{
ee7b9f93 1577 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1578 struct intel_pch_pll *pll;
92f2584a
JB		 1579 int reg;
1580 u32 val;
1581
48da64a8 1582 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1583 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1584 pll = intel_crtc->pch_pll;
1585 if (pll == NULL)
1586 return;
1587
1588 if (WARN_ON(pll->refcount == 0))
1589 return;
ee7b9f93
JB		 1590
1591 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1592 pll->pll_reg, pll->active, pll->on,
1593 intel_crtc->base.base.id);
92f2584a
JB		 1594
1595 /* PCH refclock must be enabled first */
1596 assert_pch_refclk_enabled(dev_priv);
1597
ee7b9f93 1598 if (pll->active++ && pll->on) {
92b27b08 1599 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1600 return;
1601 }
1602
1603 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1604
1605 reg = pll->pll_reg;
92f2584a
JB		 1606 val = I915_READ(reg);
1607 val |= DPLL_VCO_ENABLE;
1608 I915_WRITE(reg, val);
1609 POSTING_READ(reg);
1610 udelay(200);
ee7b9f93
JB		 1611
1612 pll->on = true;
92f2584a
JB		 1613}
1614
ee7b9f93 1615static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1616{
ee7b9f93
JB		 1617 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1618 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1619 int reg;
ee7b9f93 1620 u32 val;
4c609cb8 1621
92f2584a
JB		 1622 /* PCH only available on ILK+ */
1623 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1624 if (pll == NULL)
1625 return;
92f2584a 1626
48da64a8
CW		 1627 if (WARN_ON(pll->refcount == 0))
1628 return;
7a419866 1629
ee7b9f93
JB		 1630 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1631 pll->pll_reg, pll->active, pll->on,
1632 intel_crtc->base.base.id);
7a419866 1633
48da64a8 1634 if (WARN_ON(pll->active == 0)) {
92b27b08 1635 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1636 return;
1637 }
1638
ee7b9f93 1639 if (--pll->active) {
92b27b08 1640 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1641 return;
ee7b9f93
JB		 1642 }
1643
1644 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1645
1646 /* Make sure transcoder isn't still depending on us */
1647 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1648
ee7b9f93 1649 reg = pll->pll_reg;
92f2584a
JB		 1650 val = I915_READ(reg);
1651 val &= ~DPLL_VCO_ENABLE;
1652 I915_WRITE(reg, val);
1653 POSTING_READ(reg);
1654 udelay(200);
ee7b9f93
JB		 1655
1656 pll->on = false;
92f2584a
JB		 1657}
1658
b8a4f404
PZ		 1659static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1660 enum pipe pipe)
040484af 1661{
23670b32 1662 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1663 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1664 uint32_t reg, val, pipeconf_val;
040484af
JB		 1665
1666 /* PCH only available on ILK+ */
1667 BUG_ON(dev_priv->info->gen < 5);
1668
1669 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1670 assert_pch_pll_enabled(dev_priv,
1671 to_intel_crtc(crtc)->pch_pll,
1672 to_intel_crtc(crtc));
040484af
JB		 1673
1674 /* FDI must be feeding us bits for PCH ports */
1675 assert_fdi_tx_enabled(dev_priv, pipe);
1676 assert_fdi_rx_enabled(dev_priv, pipe);
1677
23670b32
DV		 1678 if (HAS_PCH_CPT(dev)) {
1679 /* Workaround: Set the timing override bit before enabling the
1680 * pch transcoder. */
1681 reg = TRANS_CHICKEN2(pipe);
1682 val = I915_READ(reg);
1683 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1684 I915_WRITE(reg, val);
59c859d6 1685 }
23670b32 1686
040484af
JB		 1687 reg = TRANSCONF(pipe);
1688 val = I915_READ(reg);
5f7f726d 1689 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1690
1691 if (HAS_PCH_IBX(dev_priv->dev)) {
1692 /*
1693 * make the BPC in transcoder be consistent with
1694 * that in pipeconf reg.
1695 */
1696 val &= ~PIPE_BPC_MASK;
5f7f726d 1697 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1698 }
5f7f726d
PZ		 1699
1700 val &= ~TRANS_INTERLACE_MASK;
1701 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1702 if (HAS_PCH_IBX(dev_priv->dev) &&
1703 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1704 val |= TRANS_LEGACY_INTERLACED_ILK;
1705 else
1706 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1707 else
1708 val |= TRANS_PROGRESSIVE;
1709
040484af
JB		 1710 I915_WRITE(reg, val | TRANS_ENABLE);
1711 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1712 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1713}
1714
8fb033d7 1715static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1716 enum transcoder cpu_transcoder)
040484af 1717{
8fb033d7 1718 u32 val, pipeconf_val;
8fb033d7
PZ		 1719
1720 /* PCH only available on ILK+ */
1721 BUG_ON(dev_priv->info->gen < 5);
1722
8fb033d7 1723 /* FDI must be feeding us bits for PCH ports */
937bb610
PZ		 1724 assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1725 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1726
223a6fdf
PZ		 1727 /* Workaround: set timing override bit. */
1728 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1729 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1730 I915_WRITE(_TRANSA_CHICKEN2, val);
1731
25f3ef11 1732 val = TRANS_ENABLE;
937bb610 1733 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1734
9a76b1c6
PZ		 1735 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1736 PIPECONF_INTERLACED_ILK)
a35f2679 1737 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1738 else
1739 val |= TRANS_PROGRESSIVE;
1740
25f3ef11 1741 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1742 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1743 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1744}
1745
b8a4f404
PZ		 1746static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1747 enum pipe pipe)
040484af 1748{
23670b32
DV		 1749 struct drm_device *dev = dev_priv->dev;
1750 uint32_t reg, val;
040484af
JB		 1751
1752 /* FDI relies on the transcoder */
1753 assert_fdi_tx_disabled(dev_priv, pipe);
1754 assert_fdi_rx_disabled(dev_priv, pipe);
1755
291906f1
JB		 1756 /* Ports must be off as well */
1757 assert_pch_ports_disabled(dev_priv, pipe);
1758
040484af
JB		 1759 reg = TRANSCONF(pipe);
1760 val = I915_READ(reg);
1761 val &= ~TRANS_ENABLE;
1762 I915_WRITE(reg, val);
1763 /* wait for PCH transcoder off, transcoder state */
1764 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1765 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1766
1767 if (!HAS_PCH_IBX(dev)) {
1768 /* Workaround: Clear the timing override chicken bit again. */
1769 reg = TRANS_CHICKEN2(pipe);
1770 val = I915_READ(reg);
1771 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1772 I915_WRITE(reg, val);
1773 }
040484af
JB		 1774}
1775
ab4d966c 1776static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1777{
8fb033d7
PZ		 1778 u32 val;
1779
8a52fd9f 1780 val = I915_READ(_TRANSACONF);
8fb033d7 1781 val &= ~TRANS_ENABLE;
8a52fd9f 1782 I915_WRITE(_TRANSACONF, val);
8fb033d7 1783 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1784 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1785 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1786
1787 /* Workaround: clear timing override bit. */
1788 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1789 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1790 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1791}
1792
b24e7179 1793/**
309cfea8 1794 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1795 * @dev_priv: i915 private structure
1796 * @pipe: pipe to enable
040484af 1797 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1798 *
1799 * Enable @pipe, making sure that various hardware specific requirements
1800 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1801 *
1802 * @pipe should be %PIPE_A or %PIPE_B.
1803 *
1804 * Will wait until the pipe is actually running (i.e. first vblank) before
1805 * returning.
1806 */
040484af
JB		 1807static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1808 bool pch_port)
b24e7179 1809{
702e7a56
PZ		 1810 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1811 pipe);
cc391bbb 1812 enum transcoder pch_transcoder;
b24e7179
JB		 1813 int reg;
1814 u32 val;
1815
cc391bbb
PZ		 1816 if (IS_HASWELL(dev_priv->dev))
1817 pch_transcoder = TRANSCODER_A;
1818 else
1819 pch_transcoder = pipe;
1820
b24e7179
JB		 1821 /*
1822 * A pipe without a PLL won't actually be able to drive bits from
1823 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1824 * need the check.
1825 */
1826 if (!HAS_PCH_SPLIT(dev_priv->dev))
1827 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1828 else {
1829 if (pch_port) {
1830 /* if driving the PCH, we need FDI enabled */
cc391bbb
PZ		 1831 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1832 assert_fdi_tx_pll_enabled(dev_priv, cpu_transcoder);
040484af
JB		 1833 }
1834 /* FIXME: assert CPU port conditions for SNB+ */
1835 }
b24e7179 1836
702e7a56 1837 reg = PIPECONF(cpu_transcoder);
b24e7179 1838 val = I915_READ(reg);
00d70b15
CW		 1839 if (val & PIPECONF_ENABLE)
1840 return;
1841
1842 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1843 intel_wait_for_vblank(dev_priv->dev, pipe);
1844}
1845
1846/**
309cfea8 1847 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1848 * @dev_priv: i915 private structure
1849 * @pipe: pipe to disable
1850 *
1851 * Disable @pipe, making sure that various hardware specific requirements
1852 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1853 *
1854 * @pipe should be %PIPE_A or %PIPE_B.
1855 *
1856 * Will wait until the pipe has shut down before returning.
1857 */
1858static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1859 enum pipe pipe)
1860{
702e7a56
PZ		 1861 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1862 pipe);
b24e7179
JB		 1863 int reg;
1864 u32 val;
1865
1866 /*
1867 * Make sure planes won't keep trying to pump pixels to us,
1868 * or we might hang the display.
1869 */
1870 assert_planes_disabled(dev_priv, pipe);
1871
1872 /* Don't disable pipe A or pipe A PLLs if needed */
1873 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1874 return;
1875
702e7a56 1876 reg = PIPECONF(cpu_transcoder);
b24e7179 1877 val = I915_READ(reg);
00d70b15
CW		 1878 if ((val & PIPECONF_ENABLE) == 0)
1879 return;
1880
1881 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1882 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1883}
1884
d74362c9
KP		 1885/*
1886 * Plane regs are double buffered, going from enabled->disabled needs a
1887 * trigger in order to latch. The display address reg provides this.
1888 */
6f1d69b0 1889void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1890 enum plane plane)
1891{
14f86147
DL		 1892 if (dev_priv->info->gen >= 4)
1893 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1894 else
1895 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1896}
1897
b24e7179
JB		 1898/**
1899 * intel_enable_plane - enable a display plane on a given pipe
1900 * @dev_priv: i915 private structure
1901 * @plane: plane to enable
1902 * @pipe: pipe being fed
1903 *
1904 * Enable @plane on @pipe, making sure that @pipe is running first.
1905 */
1906static void intel_enable_plane(struct drm_i915_private *dev_priv,
1907 enum plane plane, enum pipe pipe)
1908{
1909 int reg;
1910 u32 val;
1911
1912 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1913 assert_pipe_enabled(dev_priv, pipe);
1914
1915 reg = DSPCNTR(plane);
1916 val = I915_READ(reg);
00d70b15
CW		 1917 if (val & DISPLAY_PLANE_ENABLE)
1918 return;
1919
1920 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1921 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1922 intel_wait_for_vblank(dev_priv->dev, pipe);
1923}
1924
b24e7179
JB		 1925/**
1926 * intel_disable_plane - disable a display plane
1927 * @dev_priv: i915 private structure
1928 * @plane: plane to disable
1929 * @pipe: pipe consuming the data
1930 *
1931 * Disable @plane; should be an independent operation.
1932 */
1933static void intel_disable_plane(struct drm_i915_private *dev_priv,
1934 enum plane plane, enum pipe pipe)
1935{
1936 int reg;
1937 u32 val;
1938
1939 reg = DSPCNTR(plane);
1940 val = I915_READ(reg);
00d70b15
CW		 1941 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1942 return;
1943
1944 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1945 intel_flush_display_plane(dev_priv, plane);
1946 intel_wait_for_vblank(dev_priv->dev, pipe);
1947}
1948
127bd2ac 1949int
48b956c5 1950intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1951 struct drm_i915_gem_object *obj,
919926ae 1952 struct intel_ring_buffer *pipelined)
6b95a207 1953{
ce453d81 1954 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1955 u32 alignment;
1956 int ret;
1957
05394f39 1958 switch (obj->tiling_mode) {
6b95a207 1959 case I915_TILING_NONE:
534843da
CW		 1960 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1961 alignment = 128 * 1024;
a6c45cf0 1962 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1963 alignment = 4 * 1024;
1964 else
1965 alignment = 64 * 1024;
6b95a207
KH		 1966 break;
1967 case I915_TILING_X:
1968 /* pin() will align the object as required by fence */
1969 alignment = 0;
1970 break;
1971 case I915_TILING_Y:
1972 /* FIXME: Is this true? */
1973 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1974 return -EINVAL;
1975 default:
1976 BUG();
1977 }
1978
ce453d81 1979 dev_priv->mm.interruptible = false;
2da3b9b9 1980 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1981 if (ret)
ce453d81 1982 goto err_interruptible;
6b95a207
KH		 1983
1984 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1985 * fence, whereas 965+ only requires a fence if using
1986 * framebuffer compression. For simplicity, we always install
1987 * a fence as the cost is not that onerous.
1988 */
06d98131 1989 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1990 if (ret)
1991 goto err_unpin;
1690e1eb 1992
9a5a53b3 1993 i915_gem_object_pin_fence(obj);
6b95a207 1994
ce453d81 1995 dev_priv->mm.interruptible = true;
6b95a207 1996 return 0;
48b956c5
CW		 1997
1998err_unpin:
1999 i915_gem_object_unpin(obj);
ce453d81
CW		 2000err_interruptible:
2001 dev_priv->mm.interruptible = true;
48b956c5 2002 return ret;
6b95a207
KH		 2003}
2004
1690e1eb
CW		 2005void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
2006{
2007 i915_gem_object_unpin_fence(obj);
2008 i915_gem_object_unpin(obj);
2009}
2010
c2c75131
DV		 2011/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2012 * is assumed to be a power-of-two. */
5a35e99e
DL		 2013unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2014 unsigned int bpp,
2015 unsigned int pitch)
c2c75131
DV		 2016{
2017 int tile_rows, tiles;
2018
2019 tile_rows = *y / 8;
2020 *y %= 8;
2021 tiles = *x / (512/bpp);
2022 *x %= 512/bpp;
2023
2024 return tile_rows * pitch * 8 + tiles * 4096;
2025}
2026
17638cd6
JB		 2027static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2028 int x, int y)
81255565
JB		 2029{
2030 struct drm_device *dev = crtc->dev;
2031 struct drm_i915_private *dev_priv = dev->dev_private;
2032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2033 struct intel_framebuffer *intel_fb;
05394f39 2034 struct drm_i915_gem_object *obj;
81255565 2035 int plane = intel_crtc->plane;
e506a0c6 2036 unsigned long linear_offset;
81255565 2037 u32 dspcntr;
5eddb70b 2038 u32 reg;
81255565
JB		 2039
2040 switch (plane) {
2041 case 0:
2042 case 1:
2043 break;
2044 default:
2045 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2046 return -EINVAL;
2047 }
2048
2049 intel_fb = to_intel_framebuffer(fb);
2050 obj = intel_fb->obj;
81255565 2051
5eddb70b
CW		 2052 reg = DSPCNTR(plane);
2053 dspcntr = I915_READ(reg);
81255565
JB		 2054 /* Mask out pixel format bits in case we change it */
2055 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2056 switch (fb->pixel_format) {
2057 case DRM_FORMAT_C8:
81255565
JB		 2058 dspcntr |= DISPPLANE_8BPP;
2059 break;
57779d06
VS		 2060 case DRM_FORMAT_XRGB1555:
2061 case DRM_FORMAT_ARGB1555:
2062 dspcntr |= DISPPLANE_BGRX555;
81255565 2063 break;
57779d06
VS		 2064 case DRM_FORMAT_RGB565:
2065 dspcntr |= DISPPLANE_BGRX565;
2066 break;
2067 case DRM_FORMAT_XRGB8888:
2068 case DRM_FORMAT_ARGB8888:
2069 dspcntr |= DISPPLANE_BGRX888;
2070 break;
2071 case DRM_FORMAT_XBGR8888:
2072 case DRM_FORMAT_ABGR8888:
2073 dspcntr |= DISPPLANE_RGBX888;
2074 break;
2075 case DRM_FORMAT_XRGB2101010:
2076 case DRM_FORMAT_ARGB2101010:
2077 dspcntr |= DISPPLANE_BGRX101010;
2078 break;
2079 case DRM_FORMAT_XBGR2101010:
2080 case DRM_FORMAT_ABGR2101010:
2081 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2082 break;
2083 default:
57779d06 2084 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2085 return -EINVAL;
2086 }
57779d06 2087
a6c45cf0 2088 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2089 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2090 dspcntr |= DISPPLANE_TILED;
2091 else
2092 dspcntr &= ~DISPPLANE_TILED;
2093 }
2094
5eddb70b 2095 I915_WRITE(reg, dspcntr);
81255565 2096
e506a0c6 2097 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2098
c2c75131
DV		 2099 if (INTEL_INFO(dev)->gen >= 4) {
2100 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2101 intel_gen4_compute_offset_xtiled(&x, &y,
2102 fb->bits_per_pixel / 8,
2103 fb->pitches[0]);
c2c75131
DV		 2104 linear_offset -= intel_crtc->dspaddr_offset;
2105 } else {
e506a0c6 2106 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2107 }
e506a0c6
DV		 2108
2109 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2110 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2111 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2112 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2113 I915_MODIFY_DISPBASE(DSPSURF(plane),
2114 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2115 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2116 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2117 } else
e506a0c6 2118 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2119 POSTING_READ(reg);
81255565 2120
17638cd6
JB		 2121 return 0;
2122}
2123
2124static int ironlake_update_plane(struct drm_crtc *crtc,
2125 struct drm_framebuffer *fb, int x, int y)
2126{
2127 struct drm_device *dev = crtc->dev;
2128 struct drm_i915_private *dev_priv = dev->dev_private;
2129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2130 struct intel_framebuffer *intel_fb;
2131 struct drm_i915_gem_object *obj;
2132 int plane = intel_crtc->plane;
e506a0c6 2133 unsigned long linear_offset;
17638cd6
JB		 2134 u32 dspcntr;
2135 u32 reg;
2136
2137 switch (plane) {
2138 case 0:
2139 case 1:
27f8227b 2140 case 2:
17638cd6
JB		 2141 break;
2142 default:
2143 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2144 return -EINVAL;
2145 }
2146
2147 intel_fb = to_intel_framebuffer(fb);
2148 obj = intel_fb->obj;
2149
2150 reg = DSPCNTR(plane);
2151 dspcntr = I915_READ(reg);
2152 /* Mask out pixel format bits in case we change it */
2153 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2154 switch (fb->pixel_format) {
2155 case DRM_FORMAT_C8:
17638cd6
JB		 2156 dspcntr |= DISPPLANE_8BPP;
2157 break;
57779d06
VS		 2158 case DRM_FORMAT_RGB565:
2159 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2160 break;
57779d06
VS		 2161 case DRM_FORMAT_XRGB8888:
2162 case DRM_FORMAT_ARGB8888:
2163 dspcntr |= DISPPLANE_BGRX888;
2164 break;
2165 case DRM_FORMAT_XBGR8888:
2166 case DRM_FORMAT_ABGR8888:
2167 dspcntr |= DISPPLANE_RGBX888;
2168 break;
2169 case DRM_FORMAT_XRGB2101010:
2170 case DRM_FORMAT_ARGB2101010:
2171 dspcntr |= DISPPLANE_BGRX101010;
2172 break;
2173 case DRM_FORMAT_XBGR2101010:
2174 case DRM_FORMAT_ABGR2101010:
2175 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2176 break;
2177 default:
57779d06 2178 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2179 return -EINVAL;
2180 }
2181
2182 if (obj->tiling_mode != I915_TILING_NONE)
2183 dspcntr |= DISPPLANE_TILED;
2184 else
2185 dspcntr &= ~DISPPLANE_TILED;
2186
2187 /* must disable */
2188 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2189
2190 I915_WRITE(reg, dspcntr);
2191
e506a0c6 2192 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2193 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2194 intel_gen4_compute_offset_xtiled(&x, &y,
2195 fb->bits_per_pixel / 8,
2196 fb->pitches[0]);
c2c75131 2197 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2198
e506a0c6
DV		 2199 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2200 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2201 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2202 I915_MODIFY_DISPBASE(DSPSURF(plane),
2203 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2204 if (IS_HASWELL(dev)) {
2205 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2206 } else {
2207 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2208 I915_WRITE(DSPLINOFF(plane), linear_offset);
2209 }
17638cd6
JB		 2210 POSTING_READ(reg);
2211
2212 return 0;
2213}
2214
2215/* Assume fb object is pinned & idle & fenced and just update base pointers */
2216static int
2217intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2218 int x, int y, enum mode_set_atomic state)
2219{
2220 struct drm_device *dev = crtc->dev;
2221 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2222
6b8e6ed0
CW		 2223 if (dev_priv->display.disable_fbc)
2224 dev_priv->display.disable_fbc(dev);
3dec0095 2225 intel_increase_pllclock(crtc);
81255565 2226
6b8e6ed0 2227 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2228}
2229
14667a4b
CW		 2230static int
2231intel_finish_fb(struct drm_framebuffer *old_fb)
2232{
2233 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2234 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2235 bool was_interruptible = dev_priv->mm.interruptible;
2236 int ret;
2237
2238 wait_event(dev_priv->pending_flip_queue,
2239 atomic_read(&dev_priv->mm.wedged) ||
2240 atomic_read(&obj->pending_flip) == 0);
2241
2242 /* Big Hammer, we also need to ensure that any pending
2243 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2244 * current scanout is retired before unpinning the old
2245 * framebuffer.
2246 *
2247 * This should only fail upon a hung GPU, in which case we
2248 * can safely continue.
2249 */
2250 dev_priv->mm.interruptible = false;
2251 ret = i915_gem_object_finish_gpu(obj);
2252 dev_priv->mm.interruptible = was_interruptible;
2253
2254 return ret;
2255}
2256
198598d0
VS		 2257static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2258{
2259 struct drm_device *dev = crtc->dev;
2260 struct drm_i915_master_private *master_priv;
2261 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2262
2263 if (!dev->primary->master)
2264 return;
2265
2266 master_priv = dev->primary->master->driver_priv;
2267 if (!master_priv->sarea_priv)
2268 return;
2269
2270 switch (intel_crtc->pipe) {
2271 case 0:
2272 master_priv->sarea_priv->pipeA_x = x;
2273 master_priv->sarea_priv->pipeA_y = y;
2274 break;
2275 case 1:
2276 master_priv->sarea_priv->pipeB_x = x;
2277 master_priv->sarea_priv->pipeB_y = y;
2278 break;
2279 default:
2280 break;
2281 }
2282}
2283
5c3b82e2 2284static int
3c4fdcfb 2285intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2286 struct drm_framebuffer *fb)
79e53945
JB		 2287{
2288 struct drm_device *dev = crtc->dev;
6b8e6ed0 2289 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2291 struct drm_framebuffer *old_fb;
5c3b82e2 2292 int ret;
79e53945
JB		 2293
2294 /* no fb bound */
94352cf9 2295 if (!fb) {
a5071c2f 2296 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2297 return 0;
2298 }
2299
5826eca5
ED		 2300 if(intel_crtc->plane > dev_priv->num_pipe) {
2301 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2302 intel_crtc->plane,
2303 dev_priv->num_pipe);
5c3b82e2 2304 return -EINVAL;
79e53945
JB		 2305 }
2306
5c3b82e2 2307 mutex_lock(&dev->struct_mutex);
265db958 2308 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2309 to_intel_framebuffer(fb)->obj,
919926ae 2310 NULL);
5c3b82e2
CW		 2311 if (ret != 0) {
2312 mutex_unlock(&dev->struct_mutex);
a5071c2f 2313 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2314 return ret;
2315 }
79e53945 2316
94352cf9
DV		 2317 if (crtc->fb)
2318 intel_finish_fb(crtc->fb);
265db958 2319
94352cf9 2320 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2321 if (ret) {
94352cf9 2322 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2323 mutex_unlock(&dev->struct_mutex);
a5071c2f 2324 DRM_ERROR("failed to update base address\n");
4e6cfefc 2325 return ret;
79e53945 2326 }
3c4fdcfb 2327
94352cf9
DV		 2328 old_fb = crtc->fb;
2329 crtc->fb = fb;
6c4c86f5
DV		 2330 crtc->x = x;
2331 crtc->y = y;
94352cf9 2332
b7f1de28
CW		 2333 if (old_fb) {
2334 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2335 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2336 }
652c393a 2337
6b8e6ed0 2338 intel_update_fbc(dev);
5c3b82e2 2339 mutex_unlock(&dev->struct_mutex);
79e53945 2340
198598d0 2341 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2342
2343 return 0;
79e53945
JB		 2344}
2345
5eddb70b 2346static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2347{
2348 struct drm_device *dev = crtc->dev;
2349 struct drm_i915_private *dev_priv = dev->dev_private;
2350 u32 dpa_ctl;
2351
28c97730 2352 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2353 dpa_ctl = I915_READ(DP_A);
2354 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2355
2356 if (clock < 200000) {
2357 u32 temp;
2358 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2359 /* workaround for 160Mhz:
2360 1) program 0x4600c bits 15:0 = 0x8124
2361 2) program 0x46010 bit 0 = 1
2362 3) program 0x46034 bit 24 = 1
2363 4) program 0x64000 bit 14 = 1
2364 */
2365 temp = I915_READ(0x4600c);
2366 temp &= 0xffff0000;
2367 I915_WRITE(0x4600c, temp | 0x8124);
2368
2369 temp = I915_READ(0x46010);
2370 I915_WRITE(0x46010, temp | 1);
2371
2372 temp = I915_READ(0x46034);
2373 I915_WRITE(0x46034, temp | (1 << 24));
2374 } else {
2375 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2376 }
2377 I915_WRITE(DP_A, dpa_ctl);
2378
5eddb70b 2379 POSTING_READ(DP_A);
32f9d658
ZW		 2380 udelay(500);
2381}
2382
5e84e1a4
ZW		 2383static void intel_fdi_normal_train(struct drm_crtc *crtc)
2384{
2385 struct drm_device *dev = crtc->dev;
2386 struct drm_i915_private *dev_priv = dev->dev_private;
2387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2388 int pipe = intel_crtc->pipe;
2389 u32 reg, temp;
2390
2391 /* enable normal train */
2392 reg = FDI_TX_CTL(pipe);
2393 temp = I915_READ(reg);
61e499bf 2394 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2395 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2396 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2397 } else {
2398 temp &= ~FDI_LINK_TRAIN_NONE;
2399 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2400 }
5e84e1a4
ZW		 2401 I915_WRITE(reg, temp);
2402
2403 reg = FDI_RX_CTL(pipe);
2404 temp = I915_READ(reg);
2405 if (HAS_PCH_CPT(dev)) {
2406 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2407 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2408 } else {
2409 temp &= ~FDI_LINK_TRAIN_NONE;
2410 temp |= FDI_LINK_TRAIN_NONE;
2411 }
2412 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2413
2414 /* wait one idle pattern time */
2415 POSTING_READ(reg);
2416 udelay(1000);
357555c0
JB		 2417
2418 /* IVB wants error correction enabled */
2419 if (IS_IVYBRIDGE(dev))
2420 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2421 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2422}
2423
291427f5
JB		 2424static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2425{
2426 struct drm_i915_private *dev_priv = dev->dev_private;
2427 u32 flags = I915_READ(SOUTH_CHICKEN1);
2428
2429 flags |= FDI_PHASE_SYNC_OVR(pipe);
2430 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2431 flags |= FDI_PHASE_SYNC_EN(pipe);
2432 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2433 POSTING_READ(SOUTH_CHICKEN1);
2434}
2435
01a415fd
DV		 2436static void ivb_modeset_global_resources(struct drm_device *dev)
2437{
2438 struct drm_i915_private *dev_priv = dev->dev_private;
2439 struct intel_crtc *pipe_B_crtc =
2440 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2441 struct intel_crtc *pipe_C_crtc =
2442 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2443 uint32_t temp;
2444
2445 /* When everything is off disable fdi C so that we could enable fdi B
2446 * with all lanes. XXX: This misses the case where a pipe is not using
2447 * any pch resources and so doesn't need any fdi lanes. */
2448 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2449 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2450 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2451
2452 temp = I915_READ(SOUTH_CHICKEN1);
2453 temp &= ~FDI_BC_BIFURCATION_SELECT;
2454 DRM_DEBUG_KMS("disabling fdi C rx\n");
2455 I915_WRITE(SOUTH_CHICKEN1, temp);
2456 }
2457}
2458
8db9d77b
ZW		 2459/* The FDI link training functions for ILK/Ibexpeak. */
2460static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2461{
2462 struct drm_device *dev = crtc->dev;
2463 struct drm_i915_private *dev_priv = dev->dev_private;
2464 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2465 int pipe = intel_crtc->pipe;
0fc932b8 2466 int plane = intel_crtc->plane;
5eddb70b 2467 u32 reg, temp, tries;
8db9d77b 2468
0fc932b8
JB		 2469 /* FDI needs bits from pipe & plane first */
2470 assert_pipe_enabled(dev_priv, pipe);
2471 assert_plane_enabled(dev_priv, plane);
2472
e1a44743
AJ		 2473 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2474 for train result */
5eddb70b
CW		 2475 reg = FDI_RX_IMR(pipe);
2476 temp = I915_READ(reg);
e1a44743
AJ		 2477 temp &= ~FDI_RX_SYMBOL_LOCK;
2478 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2479 I915_WRITE(reg, temp);
2480 I915_READ(reg);
e1a44743
AJ		 2481 udelay(150);
2482
8db9d77b 2483 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2484 reg = FDI_TX_CTL(pipe);
2485 temp = I915_READ(reg);
77ffb597
AJ		 2486 temp &= ~(7 << 19);
2487 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2488 temp &= ~FDI_LINK_TRAIN_NONE;
2489 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2490 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2491
5eddb70b
CW		 2492 reg = FDI_RX_CTL(pipe);
2493 temp = I915_READ(reg);
8db9d77b
ZW		 2494 temp &= ~FDI_LINK_TRAIN_NONE;
2495 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2496 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2497
2498 POSTING_READ(reg);
8db9d77b
ZW		 2499 udelay(150);
2500
5b2adf89 2501 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2502 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2503 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2504 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2505
5eddb70b 2506 reg = FDI_RX_IIR(pipe);
e1a44743 2507 for (tries = 0; tries < 5; tries++) {
5eddb70b 2508 temp = I915_READ(reg);
8db9d77b
ZW		 2509 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2510
2511 if ((temp & FDI_RX_BIT_LOCK)) {
2512 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2513 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2514 break;
2515 }
8db9d77b 2516 }
e1a44743 2517 if (tries == 5)
5eddb70b 2518 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2519
2520 /* Train 2 */
5eddb70b
CW		 2521 reg = FDI_TX_CTL(pipe);
2522 temp = I915_READ(reg);
8db9d77b
ZW		 2523 temp &= ~FDI_LINK_TRAIN_NONE;
2524 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2525 I915_WRITE(reg, temp);
8db9d77b 2526
5eddb70b
CW		 2527 reg = FDI_RX_CTL(pipe);
2528 temp = I915_READ(reg);
8db9d77b
ZW		 2529 temp &= ~FDI_LINK_TRAIN_NONE;
2530 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2531 I915_WRITE(reg, temp);
8db9d77b 2532
5eddb70b
CW		 2533 POSTING_READ(reg);
2534 udelay(150);
8db9d77b 2535
5eddb70b 2536 reg = FDI_RX_IIR(pipe);
e1a44743 2537 for (tries = 0; tries < 5; tries++) {
5eddb70b 2538 temp = I915_READ(reg);
8db9d77b
ZW		 2539 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2540
2541 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2542 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2543 DRM_DEBUG_KMS("FDI train 2 done.\n");
2544 break;
2545 }
8db9d77b 2546 }
e1a44743 2547 if (tries == 5)
5eddb70b 2548 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2549
2550 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2551
8db9d77b
ZW		 2552}
2553
0206e353 2554static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2555 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2556 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2557 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2558 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2559};
2560
2561/* The FDI link training functions for SNB/Cougarpoint. */
2562static void gen6_fdi_link_train(struct drm_crtc *crtc)
2563{
2564 struct drm_device *dev = crtc->dev;
2565 struct drm_i915_private *dev_priv = dev->dev_private;
2566 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2567 int pipe = intel_crtc->pipe;
fa37d39e 2568 u32 reg, temp, i, retry;
8db9d77b 2569
e1a44743
AJ		 2570 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2571 for train result */
5eddb70b
CW		 2572 reg = FDI_RX_IMR(pipe);
2573 temp = I915_READ(reg);
e1a44743
AJ		 2574 temp &= ~FDI_RX_SYMBOL_LOCK;
2575 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2576 I915_WRITE(reg, temp);
2577
2578 POSTING_READ(reg);
e1a44743
AJ		 2579 udelay(150);
2580
8db9d77b 2581 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2582 reg = FDI_TX_CTL(pipe);
2583 temp = I915_READ(reg);
77ffb597
AJ		 2584 temp &= ~(7 << 19);
2585 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2586 temp &= ~FDI_LINK_TRAIN_NONE;
2587 temp |= FDI_LINK_TRAIN_PATTERN_1;
2588 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2589 /* SNB-B */
2590 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2591 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2592
d74cf324
DV		 2593 I915_WRITE(FDI_RX_MISC(pipe),
2594 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2595
5eddb70b
CW		 2596 reg = FDI_RX_CTL(pipe);
2597 temp = I915_READ(reg);
8db9d77b
ZW		 2598 if (HAS_PCH_CPT(dev)) {
2599 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2600 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2601 } else {
2602 temp &= ~FDI_LINK_TRAIN_NONE;
2603 temp |= FDI_LINK_TRAIN_PATTERN_1;
2604 }
5eddb70b
CW		 2605 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2606
2607 POSTING_READ(reg);
8db9d77b
ZW		 2608 udelay(150);
2609
8f5718a6 2610 cpt_phase_pointer_enable(dev, pipe);
291427f5 2611
0206e353 2612 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2613 reg = FDI_TX_CTL(pipe);
2614 temp = I915_READ(reg);
8db9d77b
ZW		 2615 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2616 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2617 I915_WRITE(reg, temp);
2618
2619 POSTING_READ(reg);
8db9d77b
ZW		 2620 udelay(500);
2621
fa37d39e
SP		 2622 for (retry = 0; retry < 5; retry++) {
2623 reg = FDI_RX_IIR(pipe);
2624 temp = I915_READ(reg);
2625 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2626 if (temp & FDI_RX_BIT_LOCK) {
2627 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2628 DRM_DEBUG_KMS("FDI train 1 done.\n");
2629 break;
2630 }
2631 udelay(50);
8db9d77b 2632 }
fa37d39e
SP		 2633 if (retry < 5)
2634 break;
8db9d77b
ZW		 2635 }
2636 if (i == 4)
5eddb70b 2637 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2638
2639 /* Train 2 */
5eddb70b
CW		 2640 reg = FDI_TX_CTL(pipe);
2641 temp = I915_READ(reg);
8db9d77b
ZW		 2642 temp &= ~FDI_LINK_TRAIN_NONE;
2643 temp |= FDI_LINK_TRAIN_PATTERN_2;
2644 if (IS_GEN6(dev)) {
2645 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2646 /* SNB-B */
2647 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2648 }
5eddb70b 2649 I915_WRITE(reg, temp);
8db9d77b 2650
5eddb70b
CW		 2651 reg = FDI_RX_CTL(pipe);
2652 temp = I915_READ(reg);
8db9d77b
ZW		 2653 if (HAS_PCH_CPT(dev)) {
2654 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2655 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2656 } else {
2657 temp &= ~FDI_LINK_TRAIN_NONE;
2658 temp |= FDI_LINK_TRAIN_PATTERN_2;
2659 }
5eddb70b
CW		 2660 I915_WRITE(reg, temp);
2661
2662 POSTING_READ(reg);
8db9d77b
ZW		 2663 udelay(150);
2664
0206e353 2665 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2666 reg = FDI_TX_CTL(pipe);
2667 temp = I915_READ(reg);
8db9d77b
ZW		 2668 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2669 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2670 I915_WRITE(reg, temp);
2671
2672 POSTING_READ(reg);
8db9d77b
ZW		 2673 udelay(500);
2674
fa37d39e
SP		 2675 for (retry = 0; retry < 5; retry++) {
2676 reg = FDI_RX_IIR(pipe);
2677 temp = I915_READ(reg);
2678 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2679 if (temp & FDI_RX_SYMBOL_LOCK) {
2680 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2681 DRM_DEBUG_KMS("FDI train 2 done.\n");
2682 break;
2683 }
2684 udelay(50);
8db9d77b 2685 }
fa37d39e
SP		 2686 if (retry < 5)
2687 break;
8db9d77b
ZW		 2688 }
2689 if (i == 4)
5eddb70b 2690 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2691
2692 DRM_DEBUG_KMS("FDI train done.\n");
2693}
2694
357555c0
JB		 2695/* Manual link training for Ivy Bridge A0 parts */
2696static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2697{
2698 struct drm_device *dev = crtc->dev;
2699 struct drm_i915_private *dev_priv = dev->dev_private;
2700 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2701 int pipe = intel_crtc->pipe;
2702 u32 reg, temp, i;
2703
2704 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2705 for train result */
2706 reg = FDI_RX_IMR(pipe);
2707 temp = I915_READ(reg);
2708 temp &= ~FDI_RX_SYMBOL_LOCK;
2709 temp &= ~FDI_RX_BIT_LOCK;
2710 I915_WRITE(reg, temp);
2711
2712 POSTING_READ(reg);
2713 udelay(150);
2714
01a415fd
DV		 2715 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2716 I915_READ(FDI_RX_IIR(pipe)));
2717
357555c0
JB		 2718 /* enable CPU FDI TX and PCH FDI RX */
2719 reg = FDI_TX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 temp &= ~(7 << 19);
2722 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2723 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2724 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2725 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2726 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2727 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2728 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2729
d74cf324
DV		 2730 I915_WRITE(FDI_RX_MISC(pipe),
2731 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2732
357555c0
JB		 2733 reg = FDI_RX_CTL(pipe);
2734 temp = I915_READ(reg);
2735 temp &= ~FDI_LINK_TRAIN_AUTO;
2736 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2737 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2738 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2739 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2740
2741 POSTING_READ(reg);
2742 udelay(150);
2743
8f5718a6 2744 cpt_phase_pointer_enable(dev, pipe);
291427f5 2745
0206e353 2746 for (i = 0; i < 4; i++) {
357555c0
JB		 2747 reg = FDI_TX_CTL(pipe);
2748 temp = I915_READ(reg);
2749 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2750 temp |= snb_b_fdi_train_param[i];
2751 I915_WRITE(reg, temp);
2752
2753 POSTING_READ(reg);
2754 udelay(500);
2755
2756 reg = FDI_RX_IIR(pipe);
2757 temp = I915_READ(reg);
2758 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2759
2760 if (temp & FDI_RX_BIT_LOCK ||
2761 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2762 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2763 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2764 break;
2765 }
2766 }
2767 if (i == 4)
2768 DRM_ERROR("FDI train 1 fail!\n");
2769
2770 /* Train 2 */
2771 reg = FDI_TX_CTL(pipe);
2772 temp = I915_READ(reg);
2773 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2774 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2775 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2776 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2777 I915_WRITE(reg, temp);
2778
2779 reg = FDI_RX_CTL(pipe);
2780 temp = I915_READ(reg);
2781 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2782 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2783 I915_WRITE(reg, temp);
2784
2785 POSTING_READ(reg);
2786 udelay(150);
2787
0206e353 2788 for (i = 0; i < 4; i++) {
357555c0
JB		 2789 reg = FDI_TX_CTL(pipe);
2790 temp = I915_READ(reg);
2791 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2792 temp |= snb_b_fdi_train_param[i];
2793 I915_WRITE(reg, temp);
2794
2795 POSTING_READ(reg);
2796 udelay(500);
2797
2798 reg = FDI_RX_IIR(pipe);
2799 temp = I915_READ(reg);
2800 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2801
2802 if (temp & FDI_RX_SYMBOL_LOCK) {
2803 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2804 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2805 break;
2806 }
2807 }
2808 if (i == 4)
2809 DRM_ERROR("FDI train 2 fail!\n");
2810
2811 DRM_DEBUG_KMS("FDI train done.\n");
2812}
2813
88cefb6c 2814static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2815{
88cefb6c 2816 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2817 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2818 int pipe = intel_crtc->pipe;
5eddb70b 2819 u32 reg, temp;
79e53945 2820
c64e311e 2821
c98e9dcf 2822 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2823 reg = FDI_RX_CTL(pipe);
2824 temp = I915_READ(reg);
2825 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2826 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2827 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2828 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2829
2830 POSTING_READ(reg);
c98e9dcf
JB		 2831 udelay(200);
2832
2833 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2834 temp = I915_READ(reg);
2835 I915_WRITE(reg, temp | FDI_PCDCLK);
2836
2837 POSTING_READ(reg);
c98e9dcf
JB		 2838 udelay(200);
2839
bf507ef7
ED		 2840 /* On Haswell, the PLL configuration for ports and pipes is handled
2841 * separately, as part of DDI setup */
2842 if (!IS_HASWELL(dev)) {
2843 /* Enable CPU FDI TX PLL, always on for Ironlake */
2844 reg = FDI_TX_CTL(pipe);
2845 temp = I915_READ(reg);
2846 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2847 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2848
bf507ef7
ED		 2849 POSTING_READ(reg);
2850 udelay(100);
2851 }
6be4a607 2852 }
0e23b99d
JB		 2853}
2854
88cefb6c
DV		 2855static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2856{
2857 struct drm_device *dev = intel_crtc->base.dev;
2858 struct drm_i915_private *dev_priv = dev->dev_private;
2859 int pipe = intel_crtc->pipe;
2860 u32 reg, temp;
2861
2862 /* Switch from PCDclk to Rawclk */
2863 reg = FDI_RX_CTL(pipe);
2864 temp = I915_READ(reg);
2865 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2866
2867 /* Disable CPU FDI TX PLL */
2868 reg = FDI_TX_CTL(pipe);
2869 temp = I915_READ(reg);
2870 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2871
2872 POSTING_READ(reg);
2873 udelay(100);
2874
2875 reg = FDI_RX_CTL(pipe);
2876 temp = I915_READ(reg);
2877 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2878
2879 /* Wait for the clocks to turn off. */
2880 POSTING_READ(reg);
2881 udelay(100);
2882}
2883
291427f5
JB		 2884static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2885{
2886 struct drm_i915_private *dev_priv = dev->dev_private;
2887 u32 flags = I915_READ(SOUTH_CHICKEN1);
2888
2889 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2890 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2891 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2892 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2893 POSTING_READ(SOUTH_CHICKEN1);
2894}
0fc932b8
JB		 2895static void ironlake_fdi_disable(struct drm_crtc *crtc)
2896{
2897 struct drm_device *dev = crtc->dev;
2898 struct drm_i915_private *dev_priv = dev->dev_private;
2899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2900 int pipe = intel_crtc->pipe;
2901 u32 reg, temp;
2902
2903 /* disable CPU FDI tx and PCH FDI rx */
2904 reg = FDI_TX_CTL(pipe);
2905 temp = I915_READ(reg);
2906 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2907 POSTING_READ(reg);
2908
2909 reg = FDI_RX_CTL(pipe);
2910 temp = I915_READ(reg);
2911 temp &= ~(0x7 << 16);
2912 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2913 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2914
2915 POSTING_READ(reg);
2916 udelay(100);
2917
2918 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2919 if (HAS_PCH_IBX(dev)) {
2920 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
291427f5
JB		 2921 } else if (HAS_PCH_CPT(dev)) {
2922 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2923 }
0fc932b8
JB		 2924
2925 /* still set train pattern 1 */
2926 reg = FDI_TX_CTL(pipe);
2927 temp = I915_READ(reg);
2928 temp &= ~FDI_LINK_TRAIN_NONE;
2929 temp |= FDI_LINK_TRAIN_PATTERN_1;
2930 I915_WRITE(reg, temp);
2931
2932 reg = FDI_RX_CTL(pipe);
2933 temp = I915_READ(reg);
2934 if (HAS_PCH_CPT(dev)) {
2935 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2936 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2937 } else {
2938 temp &= ~FDI_LINK_TRAIN_NONE;
2939 temp |= FDI_LINK_TRAIN_PATTERN_1;
2940 }
2941 /* BPC in FDI rx is consistent with that in PIPECONF */
2942 temp &= ~(0x07 << 16);
2943 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2944 I915_WRITE(reg, temp);
2945
2946 POSTING_READ(reg);
2947 udelay(100);
2948}
2949
5bb61643
CW		 2950static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2951{
2952 struct drm_device *dev = crtc->dev;
2953 struct drm_i915_private *dev_priv = dev->dev_private;
2954 unsigned long flags;
2955 bool pending;
2956
2957 if (atomic_read(&dev_priv->mm.wedged))
2958 return false;
2959
2960 spin_lock_irqsave(&dev->event_lock, flags);
2961 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2962 spin_unlock_irqrestore(&dev->event_lock, flags);
2963
2964 return pending;
2965}
2966
e6c3a2a6
CW		 2967static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2968{
0f91128d 2969 struct drm_device *dev = crtc->dev;
5bb61643 2970 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2971
2972 if (crtc->fb == NULL)
2973 return;
2974
5bb61643
CW		 2975 wait_event(dev_priv->pending_flip_queue,
2976 !intel_crtc_has_pending_flip(crtc));
2977
0f91128d
CW		 2978 mutex_lock(&dev->struct_mutex);
2979 intel_finish_fb(crtc->fb);
2980 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2981}
2982
fc316cbe 2983static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2984{
2985 struct drm_device *dev = crtc->dev;
228d3e36 2986 struct intel_encoder *intel_encoder;
040484af
JB		 2987
2988 /*
2989 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2990 * must be driven by its own crtc; no sharing is possible.
2991 */
228d3e36 2992 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2993 switch (intel_encoder->type) {
040484af 2994 case INTEL_OUTPUT_EDP:
228d3e36 2995 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2996 return false;
2997 continue;
2998 }
2999 }
3000
3001 return true;
3002}
3003
fc316cbe
PZ		 3004static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
3005{
3006 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
3007}
3008
e615efe4
ED		 3009/* Program iCLKIP clock to the desired frequency */
3010static void lpt_program_iclkip(struct drm_crtc *crtc)
3011{
3012 struct drm_device *dev = crtc->dev;
3013 struct drm_i915_private *dev_priv = dev->dev_private;
3014 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3015 u32 temp;
3016
3017 /* It is necessary to ungate the pixclk gate prior to programming
3018 * the divisors, and gate it back when it is done.
3019 */
3020 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3021
3022 /* Disable SSCCTL */
3023 intel_sbi_write(dev_priv, SBI_SSCCTL6,
3024 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
3025 SBI_SSCCTL_DISABLE);
3026
3027 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
3028 if (crtc->mode.clock == 20000) {
3029 auxdiv = 1;
3030 divsel = 0x41;
3031 phaseinc = 0x20;
3032 } else {
3033 /* The iCLK virtual clock root frequency is in MHz,
3034 * but the crtc->mode.clock in in KHz. To get the divisors,
3035 * it is necessary to divide one by another, so we
3036 * convert the virtual clock precision to KHz here for higher
3037 * precision.
3038 */
3039 u32 iclk_virtual_root_freq = 172800 * 1000;
3040 u32 iclk_pi_range = 64;
3041 u32 desired_divisor, msb_divisor_value, pi_value;
3042
3043 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
3044 msb_divisor_value = desired_divisor / iclk_pi_range;
3045 pi_value = desired_divisor % iclk_pi_range;
3046
3047 auxdiv = 0;
3048 divsel = msb_divisor_value - 2;
3049 phaseinc = pi_value;
3050 }
3051
3052 /* This should not happen with any sane values */
3053 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3054 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3055 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3056 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3057
3058 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3059 crtc->mode.clock,
3060 auxdiv,
3061 divsel,
3062 phasedir,
3063 phaseinc);
3064
3065 /* Program SSCDIVINTPHASE6 */
3066 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3067 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3068 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3069 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3070 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3071 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3072 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3073
3074 intel_sbi_write(dev_priv,
3075 SBI_SSCDIVINTPHASE6,
3076 temp);
3077
3078 /* Program SSCAUXDIV */
3079 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3080 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3081 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3082 intel_sbi_write(dev_priv,
3083 SBI_SSCAUXDIV6,
3084 temp);
3085
3086
3087 /* Enable modulator and associated divider */
3088 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3089 temp &= ~SBI_SSCCTL_DISABLE;
3090 intel_sbi_write(dev_priv,
3091 SBI_SSCCTL6,
3092 temp);
3093
3094 /* Wait for initialization time */
3095 udelay(24);
3096
3097 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3098}
3099
f67a559d
JB		 3100/*
3101 * Enable PCH resources required for PCH ports:
3102 * - PCH PLLs
3103 * - FDI training & RX/TX
3104 * - update transcoder timings
3105 * - DP transcoding bits
3106 * - transcoder
3107 */
3108static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3109{
3110 struct drm_device *dev = crtc->dev;
3111 struct drm_i915_private *dev_priv = dev->dev_private;
3112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3113 int pipe = intel_crtc->pipe;
ee7b9f93 3114 u32 reg, temp;
2c07245f 3115
e7e164db
CW		 3116 assert_transcoder_disabled(dev_priv, pipe);
3117
cd986abb
DV		 3118 /* Write the TU size bits before fdi link training, so that error
3119 * detection works. */
3120 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3121 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3122
c98e9dcf 3123 /* For PCH output, training FDI link */
674cf967 3124 dev_priv->display.fdi_link_train(crtc);
2c07245f 3125
572deb37
DV		 3126 /* XXX: pch pll's can be enabled any time before we enable the PCH
3127 * transcoder, and we actually should do this to not upset any PCH
3128 * transcoder that already use the clock when we share it.
3129 *
3130 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3131 * unconditionally resets the pll - we need that to have the right LVDS
3132 * enable sequence. */
b6b4e185 3133 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3134
303b81e0 3135 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3136 u32 sel;
4b645f14 3137
c98e9dcf 3138 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3139 switch (pipe) {
3140 default:
3141 case 0:
3142 temp |= TRANSA_DPLL_ENABLE;
3143 sel = TRANSA_DPLLB_SEL;
3144 break;
3145 case 1:
3146 temp |= TRANSB_DPLL_ENABLE;
3147 sel = TRANSB_DPLLB_SEL;
3148 break;
3149 case 2:
3150 temp |= TRANSC_DPLL_ENABLE;
3151 sel = TRANSC_DPLLB_SEL;
3152 break;
d64311ab 3153 }
ee7b9f93
JB		 3154 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3155 temp |= sel;
3156 else
3157 temp &= ~sel;
c98e9dcf 3158 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3159 }
5eddb70b 3160
d9b6cb56
JB		 3161 /* set transcoder timing, panel must allow it */
3162 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3163 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3164 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3165 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3166
5eddb70b
CW		 3167 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3168 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3169 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3170 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3171
303b81e0 3172 intel_fdi_normal_train(crtc);
5e84e1a4 3173
c98e9dcf
JB		 3174 /* For PCH DP, enable TRANS_DP_CTL */
3175 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3176 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3177 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3178 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3179 reg = TRANS_DP_CTL(pipe);
3180 temp = I915_READ(reg);
3181 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3182 TRANS_DP_SYNC_MASK |
3183 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3184 temp |= (TRANS_DP_OUTPUT_ENABLE |
3185 TRANS_DP_ENH_FRAMING);
9325c9f0 3186 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3187
3188 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3189 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3190 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3191 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3192
3193 switch (intel_trans_dp_port_sel(crtc)) {
3194 case PCH_DP_B:
5eddb70b 3195 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3196 break;
3197 case PCH_DP_C:
5eddb70b 3198 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3199 break;
3200 case PCH_DP_D:
5eddb70b 3201 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3202 break;
3203 default:
e95d41e1 3204 BUG();
32f9d658 3205 }
2c07245f 3206
5eddb70b 3207 I915_WRITE(reg, temp);
6be4a607 3208 }
b52eb4dc 3209
b8a4f404 3210 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3211}
3212
1507e5bd
PZ		 3213static void lpt_pch_enable(struct drm_crtc *crtc)
3214{
3215 struct drm_device *dev = crtc->dev;
3216 struct drm_i915_private *dev_priv = dev->dev_private;
3217 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3218 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3219
daed2dbb 3220 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3221
8c52b5e8 3222 lpt_program_iclkip(crtc);
1507e5bd 3223
0540e488 3224 /* Set transcoder timing. */
daed2dbb
PZ		 3225 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3226 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3227 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3228
daed2dbb
PZ		 3229 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3230 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3231 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3232 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3233
937bb610 3234 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3235}
3236
ee7b9f93
JB		 3237static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3238{
3239 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3240
3241 if (pll == NULL)
3242 return;
3243
3244 if (pll->refcount == 0) {
3245 WARN(1, "bad PCH PLL refcount\n");
3246 return;
3247 }
3248
3249 --pll->refcount;
3250 intel_crtc->pch_pll = NULL;
3251}
3252
3253static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3254{
3255 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3256 struct intel_pch_pll *pll;
3257 int i;
3258
3259 pll = intel_crtc->pch_pll;
3260 if (pll) {
3261 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3262 intel_crtc->base.base.id, pll->pll_reg);
3263 goto prepare;
3264 }
3265
98b6bd99
DV		 3266 if (HAS_PCH_IBX(dev_priv->dev)) {
3267 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3268 i = intel_crtc->pipe;
3269 pll = &dev_priv->pch_plls[i];
3270
3271 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3272 intel_crtc->base.base.id, pll->pll_reg);
3273
3274 goto found;
3275 }
3276
ee7b9f93
JB		 3277 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3278 pll = &dev_priv->pch_plls[i];
3279
3280 /* Only want to check enabled timings first */
3281 if (pll->refcount == 0)
3282 continue;
3283
3284 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3285 fp == I915_READ(pll->fp0_reg)) {
3286 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3287 intel_crtc->base.base.id,
3288 pll->pll_reg, pll->refcount, pll->active);
3289
3290 goto found;
3291 }
3292 }
3293
3294 /* Ok no matching timings, maybe there's a free one? */
3295 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3296 pll = &dev_priv->pch_plls[i];
3297 if (pll->refcount == 0) {
3298 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3299 intel_crtc->base.base.id, pll->pll_reg);
3300 goto found;
3301 }
3302 }
3303
3304 return NULL;
3305
3306found:
3307 intel_crtc->pch_pll = pll;
3308 pll->refcount++;
3309 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3310prepare: /* separate function? */
3311 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3312
e04c7350
CW		 3313 /* Wait for the clocks to stabilize before rewriting the regs */
3314 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3315 POSTING_READ(pll->pll_reg);
3316 udelay(150);
e04c7350
CW		 3317
3318 I915_WRITE(pll->fp0_reg, fp);
3319 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3320 pll->on = false;
3321 return pll;
3322}
3323
d4270e57
JB		 3324void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3325{
3326 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3327 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3328 u32 temp;
3329
3330 temp = I915_READ(dslreg);
3331 udelay(500);
3332 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3333 if (wait_for(I915_READ(dslreg) != temp, 5))
3334 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3335 }
3336}
3337
f67a559d
JB		 3338static void ironlake_crtc_enable(struct drm_crtc *crtc)
3339{
3340 struct drm_device *dev = crtc->dev;
3341 struct drm_i915_private *dev_priv = dev->dev_private;
3342 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3343 struct intel_encoder *encoder;
f67a559d
JB		 3344 int pipe = intel_crtc->pipe;
3345 int plane = intel_crtc->plane;
3346 u32 temp;
3347 bool is_pch_port;
3348
08a48469
DV		 3349 WARN_ON(!crtc->enabled);
3350
f67a559d
JB		 3351 if (intel_crtc->active)
3352 return;
3353
3354 intel_crtc->active = true;
3355 intel_update_watermarks(dev);
3356
3357 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3358 temp = I915_READ(PCH_LVDS);
3359 if ((temp & LVDS_PORT_EN) == 0)
3360 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3361 }
3362
fc316cbe 3363 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3364
46b6f814 3365 if (is_pch_port) {
fff367c7
DV		 3366 /* Note: FDI PLL enabling _must_ be done before we enable the
3367 * cpu pipes, hence this is separate from all the other fdi/pch
3368 * enabling. */
88cefb6c 3369 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3370 } else {
3371 assert_fdi_tx_disabled(dev_priv, pipe);
3372 assert_fdi_rx_disabled(dev_priv, pipe);
3373 }
f67a559d 3374
bf49ec8c
DV		 3375 for_each_encoder_on_crtc(dev, crtc, encoder)
3376 if (encoder->pre_enable)
3377 encoder->pre_enable(encoder);
f67a559d
JB		 3378
3379 /* Enable panel fitting for LVDS */
3380 if (dev_priv->pch_pf_size &&
547dc041
JN		 3381 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3382 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3383 /* Force use of hard-coded filter coefficients
3384 * as some pre-programmed values are broken,
3385 * e.g. x201.
3386 */
13888d78
PZ		 3387 if (IS_IVYBRIDGE(dev))
3388 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3389 PF_PIPE_SEL_IVB(pipe));
3390 else
3391 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3392 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3393 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3394 }
3395
9c54c0dd
JB		 3396 /*
3397 * On ILK+ LUT must be loaded before the pipe is running but with
3398 * clocks enabled
3399 */
3400 intel_crtc_load_lut(crtc);
3401
f67a559d
JB		 3402 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3403 intel_enable_plane(dev_priv, plane, pipe);
3404
3405 if (is_pch_port)
3406 ironlake_pch_enable(crtc);
c98e9dcf 3407
d1ebd816 3408 mutex_lock(&dev->struct_mutex);
bed4a673 3409 intel_update_fbc(dev);
d1ebd816
BW		 3410 mutex_unlock(&dev->struct_mutex);
3411
6b383a7f 3412 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3413
fa5c73b1
DV		 3414 for_each_encoder_on_crtc(dev, crtc, encoder)
3415 encoder->enable(encoder);
61b77ddd
DV		 3416
3417 if (HAS_PCH_CPT(dev))
3418 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3419
3420 /*
3421 * There seems to be a race in PCH platform hw (at least on some
3422 * outputs) where an enabled pipe still completes any pageflip right
3423 * away (as if the pipe is off) instead of waiting for vblank. As soon
3424 * as the first vblank happend, everything works as expected. Hence just
3425 * wait for one vblank before returning to avoid strange things
3426 * happening.
3427 */
3428 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3429}
3430
4f771f10
PZ		 3431static void haswell_crtc_enable(struct drm_crtc *crtc)
3432{
3433 struct drm_device *dev = crtc->dev;
3434 struct drm_i915_private *dev_priv = dev->dev_private;
3435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3436 struct intel_encoder *encoder;
3437 int pipe = intel_crtc->pipe;
3438 int plane = intel_crtc->plane;
4f771f10
PZ		 3439 bool is_pch_port;
3440
3441 WARN_ON(!crtc->enabled);
3442
3443 if (intel_crtc->active)
3444 return;
3445
3446 intel_crtc->active = true;
3447 intel_update_watermarks(dev);
3448
fc316cbe 3449 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3450
83616634 3451 if (is_pch_port)
04945641 3452 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3453
3454 for_each_encoder_on_crtc(dev, crtc, encoder)
3455 if (encoder->pre_enable)
3456 encoder->pre_enable(encoder);
3457
1f544388 3458 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3459
1f544388 3460 /* Enable panel fitting for eDP */
547dc041
JN		 3461 if (dev_priv->pch_pf_size &&
3462 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3463 /* Force use of hard-coded filter coefficients
3464 * as some pre-programmed values are broken,
3465 * e.g. x201.
3466 */
54075a7d
PZ		 3467 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3468 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3469 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3470 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3471 }
3472
3473 /*
3474 * On ILK+ LUT must be loaded before the pipe is running but with
3475 * clocks enabled
3476 */
3477 intel_crtc_load_lut(crtc);
3478
1f544388
PZ		 3479 intel_ddi_set_pipe_settings(crtc);
3480 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3481
3482 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3483 intel_enable_plane(dev_priv, plane, pipe);
3484
3485 if (is_pch_port)
1507e5bd 3486 lpt_pch_enable(crtc);
4f771f10
PZ		 3487
3488 mutex_lock(&dev->struct_mutex);
3489 intel_update_fbc(dev);
3490 mutex_unlock(&dev->struct_mutex);
3491
3492 intel_crtc_update_cursor(crtc, true);
3493
3494 for_each_encoder_on_crtc(dev, crtc, encoder)
3495 encoder->enable(encoder);
3496
4f771f10
PZ		 3497 /*
3498 * There seems to be a race in PCH platform hw (at least on some
3499 * outputs) where an enabled pipe still completes any pageflip right
3500 * away (as if the pipe is off) instead of waiting for vblank. As soon
3501 * as the first vblank happend, everything works as expected. Hence just
3502 * wait for one vblank before returning to avoid strange things
3503 * happening.
3504 */
3505 intel_wait_for_vblank(dev, intel_crtc->pipe);
3506}
3507
6be4a607
JB		 3508static void ironlake_crtc_disable(struct drm_crtc *crtc)
3509{
3510 struct drm_device *dev = crtc->dev;
3511 struct drm_i915_private *dev_priv = dev->dev_private;
3512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3513 struct intel_encoder *encoder;
6be4a607
JB		 3514 int pipe = intel_crtc->pipe;
3515 int plane = intel_crtc->plane;
5eddb70b 3516 u32 reg, temp;
b52eb4dc 3517
ef9c3aee 3518
f7abfe8b
CW		 3519 if (!intel_crtc->active)
3520 return;
3521
ea9d758d
DV		 3522 for_each_encoder_on_crtc(dev, crtc, encoder)
3523 encoder->disable(encoder);
3524
e6c3a2a6 3525 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3526 drm_vblank_off(dev, pipe);
6b383a7f 3527 intel_crtc_update_cursor(crtc, false);
5eddb70b 3528
b24e7179 3529 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3530
973d04f9
CW		 3531 if (dev_priv->cfb_plane == plane)
3532 intel_disable_fbc(dev);
2c07245f 3533
b24e7179 3534 intel_disable_pipe(dev_priv, pipe);
32f9d658 3535
6be4a607 3536 /* Disable PF */
9db4a9c7
JB		 3537 I915_WRITE(PF_CTL(pipe), 0);
3538 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3539
bf49ec8c
DV		 3540 for_each_encoder_on_crtc(dev, crtc, encoder)
3541 if (encoder->post_disable)
3542 encoder->post_disable(encoder);
2c07245f 3543
0fc932b8 3544 ironlake_fdi_disable(crtc);
249c0e64 3545
b8a4f404 3546 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3547
6be4a607
JB		 3548 if (HAS_PCH_CPT(dev)) {
3549 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3550 reg = TRANS_DP_CTL(pipe);
3551 temp = I915_READ(reg);
3552 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3553 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3554 I915_WRITE(reg, temp);
6be4a607
JB		 3555
3556 /* disable DPLL_SEL */
3557 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3558 switch (pipe) {
3559 case 0:
d64311ab 3560 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3561 break;
3562 case 1:
6be4a607 3563 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3564 break;
3565 case 2:
4b645f14 3566 /* C shares PLL A or B */
d64311ab 3567 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3568 break;
3569 default:
3570 BUG(); /* wtf */
3571 }
6be4a607 3572 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3573 }
e3421a18 3574
6be4a607 3575 /* disable PCH DPLL */
ee7b9f93 3576 intel_disable_pch_pll(intel_crtc);
8db9d77b 3577
88cefb6c 3578 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3579
f7abfe8b 3580 intel_crtc->active = false;
6b383a7f 3581 intel_update_watermarks(dev);
d1ebd816
BW		 3582
3583 mutex_lock(&dev->struct_mutex);
6b383a7f 3584 intel_update_fbc(dev);
d1ebd816 3585 mutex_unlock(&dev->struct_mutex);
6be4a607 3586}
1b3c7a47 3587
4f771f10 3588static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3589{
4f771f10
PZ		 3590 struct drm_device *dev = crtc->dev;
3591 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3592 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3593 struct intel_encoder *encoder;
3594 int pipe = intel_crtc->pipe;
3595 int plane = intel_crtc->plane;
ad80a810 3596 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3597 bool is_pch_port;
ee7b9f93 3598
4f771f10
PZ		 3599 if (!intel_crtc->active)
3600 return;
3601
83616634
PZ		 3602 is_pch_port = haswell_crtc_driving_pch(crtc);
3603
4f771f10
PZ		 3604 for_each_encoder_on_crtc(dev, crtc, encoder)
3605 encoder->disable(encoder);
3606
3607 intel_crtc_wait_for_pending_flips(crtc);
3608 drm_vblank_off(dev, pipe);
3609 intel_crtc_update_cursor(crtc, false);
3610
3611 intel_disable_plane(dev_priv, plane, pipe);
3612
3613 if (dev_priv->cfb_plane == plane)
3614 intel_disable_fbc(dev);
3615
3616 intel_disable_pipe(dev_priv, pipe);
3617
ad80a810 3618 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3619
3620 /* Disable PF */
3621 I915_WRITE(PF_CTL(pipe), 0);
3622 I915_WRITE(PF_WIN_SZ(pipe), 0);
3623
1f544388 3624 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3625
3626 for_each_encoder_on_crtc(dev, crtc, encoder)
3627 if (encoder->post_disable)
3628 encoder->post_disable(encoder);
3629
83616634 3630 if (is_pch_port) {
ab4d966c 3631 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3632 intel_ddi_fdi_disable(crtc);
83616634 3633 }
4f771f10
PZ		 3634
3635 intel_crtc->active = false;
3636 intel_update_watermarks(dev);
3637
3638 mutex_lock(&dev->struct_mutex);
3639 intel_update_fbc(dev);
3640 mutex_unlock(&dev->struct_mutex);
3641}
3642
ee7b9f93
JB		 3643static void ironlake_crtc_off(struct drm_crtc *crtc)
3644{
3645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3646 intel_put_pch_pll(intel_crtc);
3647}
3648
6441ab5f
PZ		 3649static void haswell_crtc_off(struct drm_crtc *crtc)
3650{
a5c961d1
PZ		 3651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3652
3653 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3654 * start using it. */
3655 intel_crtc->cpu_transcoder = intel_crtc->pipe;
3656
6441ab5f
PZ		 3657 intel_ddi_put_crtc_pll(crtc);
3658}
3659
02e792fb
DV		 3660static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3661{
02e792fb 3662 if (!enable && intel_crtc->overlay) {
23f09ce3 3663 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3664 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3665
23f09ce3 3666 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3667 dev_priv->mm.interruptible = false;
3668 (void) intel_overlay_switch_off(intel_crtc->overlay);
3669 dev_priv->mm.interruptible = true;
23f09ce3 3670 mutex_unlock(&dev->struct_mutex);
02e792fb 3671 }
02e792fb 3672
5dcdbcb0
CW		 3673 /* Let userspace switch the overlay on again. In most cases userspace
3674 * has to recompute where to put it anyway.
3675 */
02e792fb
DV		 3676}
3677
0b8765c6 3678static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3679{
3680 struct drm_device *dev = crtc->dev;
79e53945
JB		 3681 struct drm_i915_private *dev_priv = dev->dev_private;
3682 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3683 struct intel_encoder *encoder;
79e53945 3684 int pipe = intel_crtc->pipe;
80824003 3685 int plane = intel_crtc->plane;
79e53945 3686
08a48469
DV		 3687 WARN_ON(!crtc->enabled);
3688
f7abfe8b
CW		 3689 if (intel_crtc->active)
3690 return;
3691
3692 intel_crtc->active = true;
6b383a7f
CW		 3693 intel_update_watermarks(dev);
3694
63d7bbe9 3695 intel_enable_pll(dev_priv, pipe);
040484af 3696 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3697 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3698
0b8765c6 3699 intel_crtc_load_lut(crtc);
bed4a673 3700 intel_update_fbc(dev);
79e53945 3701
0b8765c6
JB		 3702 /* Give the overlay scaler a chance to enable if it's on this pipe */
3703 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3704 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3705
fa5c73b1
DV		 3706 for_each_encoder_on_crtc(dev, crtc, encoder)
3707 encoder->enable(encoder);
0b8765c6 3708}
79e53945 3709
0b8765c6
JB		 3710static void i9xx_crtc_disable(struct drm_crtc *crtc)
3711{
3712 struct drm_device *dev = crtc->dev;
3713 struct drm_i915_private *dev_priv = dev->dev_private;
3714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3715 struct intel_encoder *encoder;
0b8765c6
JB		 3716 int pipe = intel_crtc->pipe;
3717 int plane = intel_crtc->plane;
b690e96c 3718
ef9c3aee 3719
f7abfe8b
CW		 3720 if (!intel_crtc->active)
3721 return;
3722
ea9d758d
DV		 3723 for_each_encoder_on_crtc(dev, crtc, encoder)
3724 encoder->disable(encoder);
3725
0b8765c6 3726 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3727 intel_crtc_wait_for_pending_flips(crtc);
3728 drm_vblank_off(dev, pipe);
0b8765c6 3729 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3730 intel_crtc_update_cursor(crtc, false);
0b8765c6 3731
973d04f9
CW		 3732 if (dev_priv->cfb_plane == plane)
3733 intel_disable_fbc(dev);
79e53945 3734
b24e7179 3735 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3736 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3737 intel_disable_pll(dev_priv, pipe);
0b8765c6 3738
f7abfe8b 3739 intel_crtc->active = false;
6b383a7f
CW		 3740 intel_update_fbc(dev);
3741 intel_update_watermarks(dev);
0b8765c6
JB		 3742}
3743
ee7b9f93
JB		 3744static void i9xx_crtc_off(struct drm_crtc *crtc)
3745{
3746}
3747
976f8a20
DV		 3748static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3749 bool enabled)
2c07245f
ZW		 3750{
3751 struct drm_device *dev = crtc->dev;
3752 struct drm_i915_master_private *master_priv;
3753 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3754 int pipe = intel_crtc->pipe;
79e53945
JB		 3755
3756 if (!dev->primary->master)
3757 return;
3758
3759 master_priv = dev->primary->master->driver_priv;
3760 if (!master_priv->sarea_priv)
3761 return;
3762
79e53945
JB		 3763 switch (pipe) {
3764 case 0:
3765 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3766 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3767 break;
3768 case 1:
3769 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3770 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3771 break;
3772 default:
9db4a9c7 3773 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3774 break;
3775 }
79e53945
JB		 3776}
3777
976f8a20
DV		 3778/**
3779 * Sets the power management mode of the pipe and plane.
3780 */
3781void intel_crtc_update_dpms(struct drm_crtc *crtc)
3782{
3783 struct drm_device *dev = crtc->dev;
3784 struct drm_i915_private *dev_priv = dev->dev_private;
3785 struct intel_encoder *intel_encoder;
3786 bool enable = false;
3787
3788 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3789 enable |= intel_encoder->connectors_active;
3790
3791 if (enable)
3792 dev_priv->display.crtc_enable(crtc);
3793 else
3794 dev_priv->display.crtc_disable(crtc);
3795
3796 intel_crtc_update_sarea(crtc, enable);
3797}
3798
3799static void intel_crtc_noop(struct drm_crtc *crtc)
3800{
3801}
3802
cdd59983
CW		 3803static void intel_crtc_disable(struct drm_crtc *crtc)
3804{
cdd59983 3805 struct drm_device *dev = crtc->dev;
976f8a20 3806 struct drm_connector *connector;
ee7b9f93 3807 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3808
976f8a20
DV		 3809 /* crtc should still be enabled when we disable it. */
3810 WARN_ON(!crtc->enabled);
3811
3812 dev_priv->display.crtc_disable(crtc);
3813 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3814 dev_priv->display.off(crtc);
3815
931872fc
CW		 3816 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3817 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3818
3819 if (crtc->fb) {
3820 mutex_lock(&dev->struct_mutex);
1690e1eb 3821 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3822 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3823 crtc->fb = NULL;
3824 }
3825
3826 /* Update computed state. */
3827 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3828 if (!connector->encoder || !connector->encoder->crtc)
3829 continue;
3830
3831 if (connector->encoder->crtc != crtc)
3832 continue;
3833
3834 connector->dpms = DRM_MODE_DPMS_OFF;
3835 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3836 }
3837}
3838
a261b246 3839void intel_modeset_disable(struct drm_device *dev)
79e53945 3840{
a261b246
DV		 3841 struct drm_crtc *crtc;
3842
3843 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3844 if (crtc->enabled)
3845 intel_crtc_disable(crtc);
3846 }
79e53945
JB		 3847}
3848
1f703855 3849void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3850{
7e7d76c3
JB		 3851}
3852
ea5b213a 3853void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3854{
4ef69c7a 3855 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3856
ea5b213a
CW		 3857 drm_encoder_cleanup(encoder);
3858 kfree(intel_encoder);
7e7d76c3
JB		 3859}
3860
5ab432ef
DV		 3861/* Simple dpms helper for encodres with just one connector, no cloning and only
3862 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3863 * state of the entire output pipe. */
3864void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3865{
5ab432ef
DV		 3866 if (mode == DRM_MODE_DPMS_ON) {
3867 encoder->connectors_active = true;
3868
b2cabb0e 3869 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3870 } else {
3871 encoder->connectors_active = false;
3872
b2cabb0e 3873 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3874 }
79e53945
JB		 3875}
3876
0a91ca29
DV		 3877/* Cross check the actual hw state with our own modeset state tracking (and it's
3878 * internal consistency). */
b980514c 3879static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3880{
0a91ca29
DV		 3881 if (connector->get_hw_state(connector)) {
3882 struct intel_encoder *encoder = connector->encoder;
3883 struct drm_crtc *crtc;
3884 bool encoder_enabled;
3885 enum pipe pipe;
3886
3887 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3888 connector->base.base.id,
3889 drm_get_connector_name(&connector->base));
3890
3891 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3892 "wrong connector dpms state\n");
3893 WARN(connector->base.encoder != &encoder->base,
3894 "active connector not linked to encoder\n");
3895 WARN(!encoder->connectors_active,
3896 "encoder->connectors_active not set\n");
3897
3898 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3899 WARN(!encoder_enabled, "encoder not enabled\n");
3900 if (WARN_ON(!encoder->base.crtc))
3901 return;
3902
3903 crtc = encoder->base.crtc;
3904
3905 WARN(!crtc->enabled, "crtc not enabled\n");
3906 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3907 WARN(pipe != to_intel_crtc(crtc)->pipe,
3908 "encoder active on the wrong pipe\n");
3909 }
79e53945
JB		 3910}
3911
5ab432ef
DV		 3912/* Even simpler default implementation, if there's really no special case to
3913 * consider. */
3914void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3915{
5ab432ef 3916 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3917
5ab432ef
DV		 3918 /* All the simple cases only support two dpms states. */
3919 if (mode != DRM_MODE_DPMS_ON)
3920 mode = DRM_MODE_DPMS_OFF;
d4270e57 3921
5ab432ef
DV		 3922 if (mode == connector->dpms)
3923 return;
3924
3925 connector->dpms = mode;
3926
3927 /* Only need to change hw state when actually enabled */
3928 if (encoder->base.crtc)
3929 intel_encoder_dpms(encoder, mode);
3930 else
8af6cf88 3931 WARN_ON(encoder->connectors_active != false);
0a91ca29 3932
b980514c 3933 intel_modeset_check_state(connector->dev);
79e53945
JB		 3934}
3935
f0947c37
DV		 3936/* Simple connector->get_hw_state implementation for encoders that support only
3937 * one connector and no cloning and hence the encoder state determines the state
3938 * of the connector. */
3939bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3940{
24929352 3941 enum pipe pipe = 0;
f0947c37 3942 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3943
f0947c37 3944 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3945}
3946
79e53945 3947static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3948 const struct drm_display_mode *mode,
79e53945
JB		 3949 struct drm_display_mode *adjusted_mode)
3950{
2c07245f 3951 struct drm_device *dev = crtc->dev;
89749350 3952
bad720ff 3953 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3954 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3955 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3956 return false;
2c07245f 3957 }
89749350 3958
f9bef081
DV		 3959 /* All interlaced capable intel hw wants timings in frames. Note though
3960 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3961 * timings, so we need to be careful not to clobber these.*/
3962 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3963 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3964
44f46b42
CW		 3965 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3966 * with a hsync front porch of 0.
3967 */
3968 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3969 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3970 return false;
3971
79e53945
JB		 3972 return true;
3973}
3974
25eb05fc
JB		 3975static int valleyview_get_display_clock_speed(struct drm_device *dev)
3976{
3977 return 400000; /* FIXME */
3978}
3979
e70236a8
JB		 3980static int i945_get_display_clock_speed(struct drm_device *dev)
3981{
3982 return 400000;
3983}
79e53945 3984
e70236a8 3985static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3986{
e70236a8
JB		 3987 return 333000;
3988}
79e53945 3989
e70236a8
JB		 3990static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3991{
3992 return 200000;
3993}
79e53945 3994
e70236a8
JB		 3995static int i915gm_get_display_clock_speed(struct drm_device *dev)
3996{
3997 u16 gcfgc = 0;
79e53945 3998
e70236a8
JB		 3999 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4000
4001 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4002 return 133000;
4003 else {
4004 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4005 case GC_DISPLAY_CLOCK_333_MHZ:
4006 return 333000;
4007 default:
4008 case GC_DISPLAY_CLOCK_190_200_MHZ:
4009 return 190000;
79e53945 4010 }
e70236a8
JB		 4011 }
4012}
4013
4014static int i865_get_display_clock_speed(struct drm_device *dev)
4015{
4016 return 266000;
4017}
4018
4019static int i855_get_display_clock_speed(struct drm_device *dev)
4020{
4021 u16 hpllcc = 0;
4022 /* Assume that the hardware is in the high speed state. This
4023 * should be the default.
4024 */
4025 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4026 case GC_CLOCK_133_200:
4027 case GC_CLOCK_100_200:
4028 return 200000;
4029 case GC_CLOCK_166_250:
4030 return 250000;
4031 case GC_CLOCK_100_133:
79e53945 4032 return 133000;
e70236a8 4033 }
79e53945 4034
e70236a8
JB		 4035 /* Shouldn't happen */
4036 return 0;
4037}
79e53945 4038
e70236a8
JB		 4039static int i830_get_display_clock_speed(struct drm_device *dev)
4040{
4041 return 133000;
79e53945
JB		 4042}
4043
2c07245f
ZW		 4044struct fdi_m_n {
4045 u32 tu;
4046 u32 gmch_m;
4047 u32 gmch_n;
4048 u32 link_m;
4049 u32 link_n;
4050};
4051
4052static void
4053fdi_reduce_ratio(u32 *num, u32 *den)
4054{
4055 while (*num > 0xffffff || *den > 0xffffff) {
4056 *num >>= 1;
4057 *den >>= 1;
4058 }
4059}
4060
2c07245f 4061static void
f2b115e6
AJ		 4062ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4063 int link_clock, struct fdi_m_n *m_n)
2c07245f 4064{
2c07245f
ZW		 4065 m_n->tu = 64; /* default size */
4066
22ed1113
CW		 4067 /* BUG_ON(pixel_clock > INT_MAX / 36); */
4068 m_n->gmch_m = bits_per_pixel * pixel_clock;
4069 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 4070 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4071
22ed1113
CW		 4072 m_n->link_m = pixel_clock;
4073 m_n->link_n = link_clock;
2c07245f
ZW		 4074 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4075}
4076
a7615030
CW		 4077static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4078{
72bbe58c
KP		 4079 if (i915_panel_use_ssc >= 0)
4080 return i915_panel_use_ssc != 0;
4081 return dev_priv->lvds_use_ssc
435793df 4082 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4083}
4084
5a354204
JB		 4085/**
4086 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4087 * @crtc: CRTC structure
3b5c78a3 4088 * @mode: requested mode
5a354204
JB		 4089 *
4090 * A pipe may be connected to one or more outputs. Based on the depth of the
4091 * attached framebuffer, choose a good color depth to use on the pipe.
4092 *
4093 * If possible, match the pipe depth to the fb depth. In some cases, this
4094 * isn't ideal, because the connected output supports a lesser or restricted
4095 * set of depths. Resolve that here:
4096 * LVDS typically supports only 6bpc, so clamp down in that case
4097 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4098 * Displays may support a restricted set as well, check EDID and clamp as
4099 * appropriate.
3b5c78a3 4100 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4101 *
4102 * RETURNS:
4103 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4104 * true if they don't match).
4105 */
4106static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4107 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4108 unsigned int *pipe_bpp,
4109 struct drm_display_mode *mode)
5a354204
JB		 4110{
4111 struct drm_device *dev = crtc->dev;
4112 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4113 struct drm_connector *connector;
6c2b7c12 4114 struct intel_encoder *intel_encoder;
5a354204
JB		 4115 unsigned int display_bpc = UINT_MAX, bpc;
4116
4117 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4118 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4119
4120 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4121 unsigned int lvds_bpc;
4122
4123 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4124 LVDS_A3_POWER_UP)
4125 lvds_bpc = 8;
4126 else
4127 lvds_bpc = 6;
4128
4129 if (lvds_bpc < display_bpc) {
82820490 4130 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4131 display_bpc = lvds_bpc;
4132 }
4133 continue;
4134 }
4135
5a354204
JB		 4136 /* Not one of the known troublemakers, check the EDID */
4137 list_for_each_entry(connector, &dev->mode_config.connector_list,
4138 head) {
6c2b7c12 4139 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4140 continue;
4141
62ac41a6
JB		 4142 /* Don't use an invalid EDID bpc value */
4143 if (connector->display_info.bpc &&
4144 connector->display_info.bpc < display_bpc) {
82820490 4145 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4146 display_bpc = connector->display_info.bpc;
4147 }
4148 }
4149
4150 /*
4151 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4152 * through, clamp it down. (Note: >12bpc will be caught below.)
4153 */
4154 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4155 if (display_bpc > 8 && display_bpc < 12) {
82820490 4156 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4157 display_bpc = 12;
4158 } else {
82820490 4159 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4160 display_bpc = 8;
4161 }
4162 }
4163 }
4164
3b5c78a3
AJ		 4165 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4166 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4167 display_bpc = 6;
4168 }
4169
5a354204
JB		 4170 /*
4171 * We could just drive the pipe at the highest bpc all the time and
4172 * enable dithering as needed, but that costs bandwidth. So choose
4173 * the minimum value that expresses the full color range of the fb but
4174 * also stays within the max display bpc discovered above.
4175 */
4176
94352cf9 4177 switch (fb->depth) {
5a354204
JB		 4178 case 8:
4179 bpc = 8; /* since we go through a colormap */
4180 break;
4181 case 15:
4182 case 16:
4183 bpc = 6; /* min is 18bpp */
4184 break;
4185 case 24:
578393cd 4186 bpc = 8;
5a354204
JB		 4187 break;
4188 case 30:
578393cd 4189 bpc = 10;
5a354204
JB		 4190 break;
4191 case 48:
578393cd 4192 bpc = 12;
5a354204
JB		 4193 break;
4194 default:
4195 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4196 bpc = min((unsigned int)8, display_bpc);
4197 break;
4198 }
4199
578393cd
KP		 4200 display_bpc = min(display_bpc, bpc);
4201
82820490
AJ		 4202 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4203 bpc, display_bpc);
5a354204 4204
578393cd 4205 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4206
4207 return display_bpc != bpc;
4208}
4209
a0c4da24
JB		 4210static int vlv_get_refclk(struct drm_crtc *crtc)
4211{
4212 struct drm_device *dev = crtc->dev;
4213 struct drm_i915_private *dev_priv = dev->dev_private;
4214 int refclk = 27000; /* for DP & HDMI */
4215
4216 return 100000; /* only one validated so far */
4217
4218 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4219 refclk = 96000;
4220 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4221 if (intel_panel_use_ssc(dev_priv))
4222 refclk = 100000;
4223 else
4224 refclk = 96000;
4225 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4226 refclk = 100000;
4227 }
4228
4229 return refclk;
4230}
4231
c65d77d8
JB		 4232static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4233{
4234 struct drm_device *dev = crtc->dev;
4235 struct drm_i915_private *dev_priv = dev->dev_private;
4236 int refclk;
4237
a0c4da24
JB		 4238 if (IS_VALLEYVIEW(dev)) {
4239 refclk = vlv_get_refclk(crtc);
4240 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4241 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4242 refclk = dev_priv->lvds_ssc_freq * 1000;
4243 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4244 refclk / 1000);
4245 } else if (!IS_GEN2(dev)) {
4246 refclk = 96000;
4247 } else {
4248 refclk = 48000;
4249 }
4250
4251 return refclk;
4252}
4253
4254static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4255 intel_clock_t *clock)
4256{
4257 /* SDVO TV has fixed PLL values depend on its clock range,
4258 this mirrors vbios setting. */
4259 if (adjusted_mode->clock >= 100000
4260 && adjusted_mode->clock < 140500) {
4261 clock->p1 = 2;
4262 clock->p2 = 10;
4263 clock->n = 3;
4264 clock->m1 = 16;
4265 clock->m2 = 8;
4266 } else if (adjusted_mode->clock >= 140500
4267 && adjusted_mode->clock <= 200000) {
4268 clock->p1 = 1;
4269 clock->p2 = 10;
4270 clock->n = 6;
4271 clock->m1 = 12;
4272 clock->m2 = 8;
4273 }
4274}
4275
a7516a05
JB		 4276static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4277 intel_clock_t *clock,
4278 intel_clock_t *reduced_clock)
4279{
4280 struct drm_device *dev = crtc->dev;
4281 struct drm_i915_private *dev_priv = dev->dev_private;
4282 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4283 int pipe = intel_crtc->pipe;
4284 u32 fp, fp2 = 0;
4285
4286 if (IS_PINEVIEW(dev)) {
4287 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4288 if (reduced_clock)
4289 fp2 = (1 << reduced_clock->n) << 16 |
4290 reduced_clock->m1 << 8 | reduced_clock->m2;
4291 } else {
4292 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4293 if (reduced_clock)
4294 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4295 reduced_clock->m2;
4296 }
4297
4298 I915_WRITE(FP0(pipe), fp);
4299
4300 intel_crtc->lowfreq_avail = false;
4301 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4302 reduced_clock && i915_powersave) {
4303 I915_WRITE(FP1(pipe), fp2);
4304 intel_crtc->lowfreq_avail = true;
4305 } else {
4306 I915_WRITE(FP1(pipe), fp);
4307 }
4308}
4309
93e537a1
DV		 4310static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
4311 struct drm_display_mode *adjusted_mode)
4312{
4313 struct drm_device *dev = crtc->dev;
4314 struct drm_i915_private *dev_priv = dev->dev_private;
4315 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4316 int pipe = intel_crtc->pipe;
284d5df5 4317 u32 temp;
93e537a1
DV		 4318
4319 temp = I915_READ(LVDS);
4320 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
4321 if (pipe == 1) {
4322 temp |= LVDS_PIPEB_SELECT;
4323 } else {
4324 temp &= ~LVDS_PIPEB_SELECT;
4325 }
4326 /* set the corresponsding LVDS_BORDER bit */
4327 temp |= dev_priv->lvds_border_bits;
4328 /* Set the B0-B3 data pairs corresponding to whether we're going to
4329 * set the DPLLs for dual-channel mode or not.
4330 */
4331 if (clock->p2 == 7)
4332 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4333 else
4334 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4335
4336 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4337 * appropriately here, but we need to look more thoroughly into how
4338 * panels behave in the two modes.
4339 */
4340 /* set the dithering flag on LVDS as needed */
4341 if (INTEL_INFO(dev)->gen >= 4) {
4342 if (dev_priv->lvds_dither)
4343 temp |= LVDS_ENABLE_DITHER;
4344 else
4345 temp &= ~LVDS_ENABLE_DITHER;
4346 }
284d5df5 4347 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 4348 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4349 temp |= LVDS_HSYNC_POLARITY;
93e537a1 4350 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4351 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 4352 I915_WRITE(LVDS, temp);
4353}
4354
a0c4da24
JB		 4355static void vlv_update_pll(struct drm_crtc *crtc,
4356 struct drm_display_mode *mode,
4357 struct drm_display_mode *adjusted_mode,
4358 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4359 int num_connectors)
a0c4da24
JB		 4360{
4361 struct drm_device *dev = crtc->dev;
4362 struct drm_i915_private *dev_priv = dev->dev_private;
4363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4364 int pipe = intel_crtc->pipe;
4365 u32 dpll, mdiv, pdiv;
4366 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4367 bool is_sdvo;
4368 u32 temp;
a0c4da24 4369
2a8f64ca
VP		 4370 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4371 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4372
2a8f64ca
VP		 4373 dpll = DPLL_VGA_MODE_DIS;
4374 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4375 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4376 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4377
4378 I915_WRITE(DPLL(pipe), dpll);
4379 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4380
4381 bestn = clock->n;
4382 bestm1 = clock->m1;
4383 bestm2 = clock->m2;
4384 bestp1 = clock->p1;
4385 bestp2 = clock->p2;
4386
2a8f64ca
VP		 4387 /*
4388 * In Valleyview PLL and program lane counter registers are exposed
4389 * through DPIO interface
4390 */
a0c4da24
JB		 4391 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4392 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4393 mdiv |= ((bestn << DPIO_N_SHIFT));
4394 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4395 mdiv |= (1 << DPIO_K_SHIFT);
4396 mdiv |= DPIO_ENABLE_CALIBRATION;
4397 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4398
4399 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4400
2a8f64ca 4401 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4402 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4403 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4404 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4405 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4406
2a8f64ca 4407 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4408
4409 dpll |= DPLL_VCO_ENABLE;
4410 I915_WRITE(DPLL(pipe), dpll);
4411 POSTING_READ(DPLL(pipe));
4412 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4413 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4414
2a8f64ca
VP		 4415 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4416
4417 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4418 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4419
4420 I915_WRITE(DPLL(pipe), dpll);
4421
4422 /* Wait for the clocks to stabilize. */
4423 POSTING_READ(DPLL(pipe));
4424 udelay(150);
a0c4da24 4425
2a8f64ca
VP		 4426 temp = 0;
4427 if (is_sdvo) {
4428 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4429 if (temp > 1)
4430 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4431 else
4432 temp = 0;
a0c4da24 4433 }
2a8f64ca
VP		 4434 I915_WRITE(DPLL_MD(pipe), temp);
4435 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4436
2a8f64ca
VP		 4437 /* Now program lane control registers */
4438 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4439 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4440 {
4441 temp = 0x1000C4;
4442 if(pipe == 1)
4443 temp |= (1 << 21);
4444 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4445 }
4446 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4447 {
4448 temp = 0x1000C4;
4449 if(pipe == 1)
4450 temp |= (1 << 21);
4451 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4452 }
a0c4da24
JB		 4453}
4454
eb1cbe48
DV		 4455static void i9xx_update_pll(struct drm_crtc *crtc,
4456 struct drm_display_mode *mode,
4457 struct drm_display_mode *adjusted_mode,
4458 intel_clock_t *clock, intel_clock_t *reduced_clock,
4459 int num_connectors)
4460{
4461 struct drm_device *dev = crtc->dev;
4462 struct drm_i915_private *dev_priv = dev->dev_private;
4463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4464 struct intel_encoder *encoder;
eb1cbe48
DV		 4465 int pipe = intel_crtc->pipe;
4466 u32 dpll;
4467 bool is_sdvo;
4468
2a8f64ca
VP		 4469 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4470
eb1cbe48
DV		 4471 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4472 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4473
4474 dpll = DPLL_VGA_MODE_DIS;
4475
4476 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4477 dpll |= DPLLB_MODE_LVDS;
4478 else
4479 dpll |= DPLLB_MODE_DAC_SERIAL;
4480 if (is_sdvo) {
4481 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4482 if (pixel_multiplier > 1) {
4483 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4484 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4485 }
4486 dpll |= DPLL_DVO_HIGH_SPEED;
4487 }
4488 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4489 dpll |= DPLL_DVO_HIGH_SPEED;
4490
4491 /* compute bitmask from p1 value */
4492 if (IS_PINEVIEW(dev))
4493 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4494 else {
4495 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4496 if (IS_G4X(dev) && reduced_clock)
4497 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4498 }
4499 switch (clock->p2) {
4500 case 5:
4501 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4502 break;
4503 case 7:
4504 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4505 break;
4506 case 10:
4507 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4508 break;
4509 case 14:
4510 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4511 break;
4512 }
4513 if (INTEL_INFO(dev)->gen >= 4)
4514 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4515
4516 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4517 dpll |= PLL_REF_INPUT_TVCLKINBC;
4518 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4519 /* XXX: just matching BIOS for now */
4520 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4521 dpll |= 3;
4522 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4523 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4524 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4525 else
4526 dpll |= PLL_REF_INPUT_DREFCLK;
4527
4528 dpll |= DPLL_VCO_ENABLE;
4529 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4530 POSTING_READ(DPLL(pipe));
4531 udelay(150);
4532
dafd226c
DV		 4533 for_each_encoder_on_crtc(dev, crtc, encoder)
4534 if (encoder->pre_pll_enable)
4535 encoder->pre_pll_enable(encoder);
4536
eb1cbe48
DV		 4537 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4538 * This is an exception to the general rule that mode_set doesn't turn
4539 * things on.
4540 */
4541 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4542 intel_update_lvds(crtc, clock, adjusted_mode);
4543
4544 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4545 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4546
4547 I915_WRITE(DPLL(pipe), dpll);
4548
4549 /* Wait for the clocks to stabilize. */
4550 POSTING_READ(DPLL(pipe));
4551 udelay(150);
4552
4553 if (INTEL_INFO(dev)->gen >= 4) {
4554 u32 temp = 0;
4555 if (is_sdvo) {
4556 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4557 if (temp > 1)
4558 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4559 else
4560 temp = 0;
4561 }
4562 I915_WRITE(DPLL_MD(pipe), temp);
4563 } else {
4564 /* The pixel multiplier can only be updated once the
4565 * DPLL is enabled and the clocks are stable.
4566 *
4567 * So write it again.
4568 */
4569 I915_WRITE(DPLL(pipe), dpll);
4570 }
4571}
4572
4573static void i8xx_update_pll(struct drm_crtc *crtc,
4574 struct drm_display_mode *adjusted_mode,
2a8f64ca 4575 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4576 int num_connectors)
4577{
4578 struct drm_device *dev = crtc->dev;
4579 struct drm_i915_private *dev_priv = dev->dev_private;
4580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4581 struct intel_encoder *encoder;
eb1cbe48
DV		 4582 int pipe = intel_crtc->pipe;
4583 u32 dpll;
4584
2a8f64ca
VP		 4585 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4586
eb1cbe48
DV		 4587 dpll = DPLL_VGA_MODE_DIS;
4588
4589 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4590 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4591 } else {
4592 if (clock->p1 == 2)
4593 dpll |= PLL_P1_DIVIDE_BY_TWO;
4594 else
4595 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4596 if (clock->p2 == 4)
4597 dpll |= PLL_P2_DIVIDE_BY_4;
4598 }
4599
4600 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4601 /* XXX: just matching BIOS for now */
4602 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4603 dpll |= 3;
4604 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4605 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4606 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4607 else
4608 dpll |= PLL_REF_INPUT_DREFCLK;
4609
4610 dpll |= DPLL_VCO_ENABLE;
4611 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4612 POSTING_READ(DPLL(pipe));
4613 udelay(150);
4614
dafd226c
DV		 4615 for_each_encoder_on_crtc(dev, crtc, encoder)
4616 if (encoder->pre_pll_enable)
4617 encoder->pre_pll_enable(encoder);
4618
eb1cbe48
DV		 4619 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4620 * This is an exception to the general rule that mode_set doesn't turn
4621 * things on.
4622 */
4623 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4624 intel_update_lvds(crtc, clock, adjusted_mode);
4625
5b5896e4
DV		 4626 I915_WRITE(DPLL(pipe), dpll);
4627
4628 /* Wait for the clocks to stabilize. */
4629 POSTING_READ(DPLL(pipe));
4630 udelay(150);
4631
eb1cbe48
DV		 4632 /* The pixel multiplier can only be updated once the
4633 * DPLL is enabled and the clocks are stable.
4634 *
4635 * So write it again.
4636 */
4637 I915_WRITE(DPLL(pipe), dpll);
4638}
4639
b0e77b9c
PZ		 4640static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4641 struct drm_display_mode *mode,
4642 struct drm_display_mode *adjusted_mode)
4643{
4644 struct drm_device *dev = intel_crtc->base.dev;
4645 struct drm_i915_private *dev_priv = dev->dev_private;
4646 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4647 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4648 uint32_t vsyncshift;
4649
4650 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4651 /* the chip adds 2 halflines automatically */
4652 adjusted_mode->crtc_vtotal -= 1;
4653 adjusted_mode->crtc_vblank_end -= 1;
4654 vsyncshift = adjusted_mode->crtc_hsync_start
4655 - adjusted_mode->crtc_htotal / 2;
4656 } else {
4657 vsyncshift = 0;
4658 }
4659
4660 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4661 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4662
fe2b8f9d 4663 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4664 (adjusted_mode->crtc_hdisplay - 1) |
4665 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4666 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4667 (adjusted_mode->crtc_hblank_start - 1) |
4668 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4669 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4670 (adjusted_mode->crtc_hsync_start - 1) |
4671 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4672
fe2b8f9d 4673 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4674 (adjusted_mode->crtc_vdisplay - 1) |
4675 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4676 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4677 (adjusted_mode->crtc_vblank_start - 1) |
4678 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4679 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4680 (adjusted_mode->crtc_vsync_start - 1) |
4681 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4682
b5e508d4
PZ		 4683 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4684 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4685 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4686 * bits. */
4687 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4688 (pipe == PIPE_B || pipe == PIPE_C))
4689 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4690
b0e77b9c
PZ		 4691 /* pipesrc controls the size that is scaled from, which should
4692 * always be the user's requested size.
4693 */
4694 I915_WRITE(PIPESRC(pipe),
4695 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4696}
4697
f564048e
EA		 4698static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4699 struct drm_display_mode *mode,
4700 struct drm_display_mode *adjusted_mode,
4701 int x, int y,
94352cf9 4702 struct drm_framebuffer *fb)
79e53945
JB		 4703{
4704 struct drm_device *dev = crtc->dev;
4705 struct drm_i915_private *dev_priv = dev->dev_private;
4706 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4707 int pipe = intel_crtc->pipe;
80824003 4708 int plane = intel_crtc->plane;
c751ce4f 4709 int refclk, num_connectors = 0;
652c393a 4710 intel_clock_t clock, reduced_clock;
b0e77b9c 4711 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4712 bool ok, has_reduced_clock = false, is_sdvo = false;
4713 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4714 struct intel_encoder *encoder;
d4906093 4715 const intel_limit_t *limit;
5c3b82e2 4716 int ret;
79e53945 4717
6c2b7c12 4718 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4719 switch (encoder->type) {
79e53945
JB		 4720 case INTEL_OUTPUT_LVDS:
4721 is_lvds = true;
4722 break;
4723 case INTEL_OUTPUT_SDVO:
7d57382e 4724 case INTEL_OUTPUT_HDMI:
79e53945 4725 is_sdvo = true;
5eddb70b 4726 if (encoder->needs_tv_clock)
e2f0ba97 4727 is_tv = true;
79e53945 4728 break;
79e53945
JB		 4729 case INTEL_OUTPUT_TVOUT:
4730 is_tv = true;
4731 break;
a4fc5ed6
KP		 4732 case INTEL_OUTPUT_DISPLAYPORT:
4733 is_dp = true;
4734 break;
79e53945 4735 }
43565a06 4736
c751ce4f 4737 num_connectors++;
79e53945
JB		 4738 }
4739
c65d77d8 4740 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4741
d4906093
ML		 4742 /*
4743 * Returns a set of divisors for the desired target clock with the given
4744 * refclk, or FALSE. The returned values represent the clock equation:
4745 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4746 */
1b894b59 4747 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4748 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4749 &clock);
79e53945
JB		 4750 if (!ok) {
4751 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4752 return -EINVAL;
79e53945
JB		 4753 }
4754
cda4b7d3 4755 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4756 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4757
ddc9003c 4758 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4759 /*
4760 * Ensure we match the reduced clock's P to the target clock.
4761 * If the clocks don't match, we can't switch the display clock
4762 * by using the FP0/FP1. In such case we will disable the LVDS
4763 * downclock feature.
4764 */
ddc9003c 4765 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4766 dev_priv->lvds_downclock,
4767 refclk,
cec2f356 4768 &clock,
5eddb70b 4769 &reduced_clock);
7026d4ac
ZW		 4770 }
4771
c65d77d8
JB		 4772 if (is_sdvo && is_tv)
4773 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4774
eb1cbe48 4775 if (IS_GEN2(dev))
2a8f64ca
VP		 4776 i8xx_update_pll(crtc, adjusted_mode, &clock,
4777 has_reduced_clock ? &reduced_clock : NULL,
4778 num_connectors);
a0c4da24 4779 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4780 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4781 has_reduced_clock ? &reduced_clock : NULL,
4782 num_connectors);
79e53945 4783 else
eb1cbe48
DV		 4784 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4785 has_reduced_clock ? &reduced_clock : NULL,
4786 num_connectors);
79e53945
JB		 4787
4788 /* setup pipeconf */
5eddb70b 4789 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4790
4791 /* Set up the display plane register */
4792 dspcntr = DISPPLANE_GAMMA_ENABLE;
4793
929c77fb
EA		 4794 if (pipe == 0)
4795 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4796 else
4797 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4798
a6c45cf0 4799 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4800 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4801 * core speed.
4802 *
4803 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4804 * pipe == 0 check?
4805 */
e70236a8
JB		 4806 if (mode->clock >
4807 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4808 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4809 else
5eddb70b 4810 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4811 }
4812
3b5c78a3
AJ		 4813 /* default to 8bpc */
4814 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4815 if (is_dp) {
0c96c65b 4816 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3b5c78a3
AJ		 4817 pipeconf |= PIPECONF_BPP_6 |
4818 PIPECONF_DITHER_EN |
4819 PIPECONF_DITHER_TYPE_SP;
4820 }
4821 }
4822
19c03924
GB		 4823 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4824 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4825 pipeconf |= PIPECONF_BPP_6 |
4826 PIPECONF_ENABLE |
4827 I965_PIPECONF_ACTIVE;
4828 }
4829 }
4830
28c97730 4831 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4832 drm_mode_debug_printmodeline(mode);
4833
a7516a05
JB		 4834 if (HAS_PIPE_CXSR(dev)) {
4835 if (intel_crtc->lowfreq_avail) {
28c97730 4836 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4837 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4838 } else {
28c97730 4839 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4840 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4841 }
4842 }
4843
617cf884 4844 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4845 if (!IS_GEN2(dev) &&
b0e77b9c 4846 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4847 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4848 else
617cf884 4849 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4850
b0e77b9c 4851 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4852
4853 /* pipesrc and dspsize control the size that is scaled from,
4854 * which should always be the user's requested size.
79e53945 4855 */
929c77fb
EA		 4856 I915_WRITE(DSPSIZE(plane),
4857 ((mode->vdisplay - 1) << 16) |
4858 (mode->hdisplay - 1));
4859 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4860
f564048e
EA		 4861 I915_WRITE(PIPECONF(pipe), pipeconf);
4862 POSTING_READ(PIPECONF(pipe));
929c77fb 4863 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4864
4865 intel_wait_for_vblank(dev, pipe);
4866
f564048e
EA		 4867 I915_WRITE(DSPCNTR(plane), dspcntr);
4868 POSTING_READ(DSPCNTR(plane));
4869
94352cf9 4870 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4871
4872 intel_update_watermarks(dev);
4873
f564048e
EA		 4874 return ret;
4875}
4876
9fb526db
KP		 4877/*
4878 * Initialize reference clocks when the driver loads
4879 */
4880void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4881{
4882 struct drm_i915_private *dev_priv = dev->dev_private;
4883 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4884 struct intel_encoder *encoder;
13d83a67
JB		 4885 u32 temp;
4886 bool has_lvds = false;
199e5d79
KP		 4887 bool has_cpu_edp = false;
4888 bool has_pch_edp = false;
4889 bool has_panel = false;
99eb6a01
KP		 4890 bool has_ck505 = false;
4891 bool can_ssc = false;
13d83a67
JB		 4892
4893 /* We need to take the global config into account */
199e5d79
KP		 4894 list_for_each_entry(encoder, &mode_config->encoder_list,
4895 base.head) {
4896 switch (encoder->type) {
4897 case INTEL_OUTPUT_LVDS:
4898 has_panel = true;
4899 has_lvds = true;
4900 break;
4901 case INTEL_OUTPUT_EDP:
4902 has_panel = true;
4903 if (intel_encoder_is_pch_edp(&encoder->base))
4904 has_pch_edp = true;
4905 else
4906 has_cpu_edp = true;
4907 break;
13d83a67
JB		 4908 }
4909 }
4910
99eb6a01
KP		 4911 if (HAS_PCH_IBX(dev)) {
4912 has_ck505 = dev_priv->display_clock_mode;
4913 can_ssc = has_ck505;
4914 } else {
4915 has_ck505 = false;
4916 can_ssc = true;
4917 }
4918
4919 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4920 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4921 has_ck505);
13d83a67
JB		 4922
4923 /* Ironlake: try to setup display ref clock before DPLL
4924 * enabling. This is only under driver's control after
4925 * PCH B stepping, previous chipset stepping should be
4926 * ignoring this setting.
4927 */
4928 temp = I915_READ(PCH_DREF_CONTROL);
4929 /* Always enable nonspread source */
4930 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4931
99eb6a01
KP		 4932 if (has_ck505)
4933 temp |= DREF_NONSPREAD_CK505_ENABLE;
4934 else
4935 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4936
199e5d79
KP		 4937 if (has_panel) {
4938 temp &= ~DREF_SSC_SOURCE_MASK;
4939 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4940
199e5d79 4941 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4942 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4943 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4944 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4945 } else
4946 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4947
4948 /* Get SSC going before enabling the outputs */
4949 I915_WRITE(PCH_DREF_CONTROL, temp);
4950 POSTING_READ(PCH_DREF_CONTROL);
4951 udelay(200);
4952
13d83a67
JB		 4953 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4954
4955 /* Enable CPU source on CPU attached eDP */
199e5d79 4956 if (has_cpu_edp) {
99eb6a01 4957 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4958 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4959 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4960 }
13d83a67
JB		 4961 else
4962 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4963 } else
4964 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4965
4966 I915_WRITE(PCH_DREF_CONTROL, temp);
4967 POSTING_READ(PCH_DREF_CONTROL);
4968 udelay(200);
4969 } else {
4970 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4971
4972 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4973
4974 /* Turn off CPU output */
4975 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4976
4977 I915_WRITE(PCH_DREF_CONTROL, temp);
4978 POSTING_READ(PCH_DREF_CONTROL);
4979 udelay(200);
4980
4981 /* Turn off the SSC source */
4982 temp &= ~DREF_SSC_SOURCE_MASK;
4983 temp |= DREF_SSC_SOURCE_DISABLE;
4984
4985 /* Turn off SSC1 */
4986 temp &= ~ DREF_SSC1_ENABLE;
4987
13d83a67
JB		 4988 I915_WRITE(PCH_DREF_CONTROL, temp);
4989 POSTING_READ(PCH_DREF_CONTROL);
4990 udelay(200);
4991 }
4992}
4993
d9d444cb
JB		 4994static int ironlake_get_refclk(struct drm_crtc *crtc)
4995{
4996 struct drm_device *dev = crtc->dev;
4997 struct drm_i915_private *dev_priv = dev->dev_private;
4998 struct intel_encoder *encoder;
d9d444cb
JB		 4999 struct intel_encoder *edp_encoder = NULL;
5000 int num_connectors = 0;
5001 bool is_lvds = false;
5002
6c2b7c12 5003 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5004 switch (encoder->type) {
5005 case INTEL_OUTPUT_LVDS:
5006 is_lvds = true;
5007 break;
5008 case INTEL_OUTPUT_EDP:
5009 edp_encoder = encoder;
5010 break;
5011 }
5012 num_connectors++;
5013 }
5014
5015 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5016 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5017 dev_priv->lvds_ssc_freq);
5018 return dev_priv->lvds_ssc_freq * 1000;
5019 }
5020
5021 return 120000;
5022}
5023
c8203565 5024static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5025 struct drm_display_mode *adjusted_mode,
c8203565 5026 bool dither)
79e53945 5027{
c8203565 5028 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5029 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5030 int pipe = intel_crtc->pipe;
c8203565
PZ		 5031 uint32_t val;
5032
5033 val = I915_READ(PIPECONF(pipe));
5034
5035 val &= ~PIPE_BPC_MASK;
5036 switch (intel_crtc->bpp) {
5037 case 18:
5038 val |= PIPE_6BPC;
5039 break;
5040 case 24:
5041 val |= PIPE_8BPC;
5042 break;
5043 case 30:
5044 val |= PIPE_10BPC;
5045 break;
5046 case 36:
5047 val |= PIPE_12BPC;
5048 break;
5049 default:
cc769b62
PZ		 5050 /* Case prevented by intel_choose_pipe_bpp_dither. */
5051 BUG();
c8203565
PZ		 5052 }
5053
5054 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5055 if (dither)
5056 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5057
5058 val &= ~PIPECONF_INTERLACE_MASK;
5059 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5060 val |= PIPECONF_INTERLACED_ILK;
5061 else
5062 val |= PIPECONF_PROGRESSIVE;
5063
5064 I915_WRITE(PIPECONF(pipe), val);
5065 POSTING_READ(PIPECONF(pipe));
5066}
5067
ee2b0b38
PZ		 5068static void haswell_set_pipeconf(struct drm_crtc *crtc,
5069 struct drm_display_mode *adjusted_mode,
5070 bool dither)
5071{
5072 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5073 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5074 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5075 uint32_t val;
5076
702e7a56 5077 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5078
5079 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5080 if (dither)
5081 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5082
5083 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5084 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5085 val |= PIPECONF_INTERLACED_ILK;
5086 else
5087 val |= PIPECONF_PROGRESSIVE;
5088
702e7a56
PZ		 5089 I915_WRITE(PIPECONF(cpu_transcoder), val);
5090 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5091}
5092
6591c6e4
PZ		 5093static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5094 struct drm_display_mode *adjusted_mode,
5095 intel_clock_t *clock,
5096 bool *has_reduced_clock,
5097 intel_clock_t *reduced_clock)
5098{
5099 struct drm_device *dev = crtc->dev;
5100 struct drm_i915_private *dev_priv = dev->dev_private;
5101 struct intel_encoder *intel_encoder;
5102 int refclk;
d4906093 5103 const intel_limit_t *limit;
6591c6e4 5104 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5105
6591c6e4
PZ		 5106 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5107 switch (intel_encoder->type) {
79e53945
JB		 5108 case INTEL_OUTPUT_LVDS:
5109 is_lvds = true;
5110 break;
5111 case INTEL_OUTPUT_SDVO:
7d57382e 5112 case INTEL_OUTPUT_HDMI:
79e53945 5113 is_sdvo = true;
6591c6e4 5114 if (intel_encoder->needs_tv_clock)
e2f0ba97 5115 is_tv = true;
79e53945 5116 break;
79e53945
JB		 5117 case INTEL_OUTPUT_TVOUT:
5118 is_tv = true;
5119 break;
79e53945
JB		 5120 }
5121 }
5122
d9d444cb 5123 refclk = ironlake_get_refclk(crtc);
79e53945 5124
d4906093
ML		 5125 /*
5126 * Returns a set of divisors for the desired target clock with the given
5127 * refclk, or FALSE. The returned values represent the clock equation:
5128 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5129 */
1b894b59 5130 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5131 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5132 clock);
5133 if (!ret)
5134 return false;
cda4b7d3 5135
ddc9003c 5136 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5137 /*
5138 * Ensure we match the reduced clock's P to the target clock.
5139 * If the clocks don't match, we can't switch the display clock
5140 * by using the FP0/FP1. In such case we will disable the LVDS
5141 * downclock feature.
5142 */
6591c6e4
PZ		 5143 *has_reduced_clock = limit->find_pll(limit, crtc,
5144 dev_priv->lvds_downclock,
5145 refclk,
5146 clock,
5147 reduced_clock);
652c393a 5148 }
61e9653f
DV		 5149
5150 if (is_sdvo && is_tv)
6591c6e4
PZ		 5151 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5152
5153 return true;
5154}
5155
01a415fd
DV		 5156static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5157{
5158 struct drm_i915_private *dev_priv = dev->dev_private;
5159 uint32_t temp;
5160
5161 temp = I915_READ(SOUTH_CHICKEN1);
5162 if (temp & FDI_BC_BIFURCATION_SELECT)
5163 return;
5164
5165 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5166 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5167
5168 temp |= FDI_BC_BIFURCATION_SELECT;
5169 DRM_DEBUG_KMS("enabling fdi C rx\n");
5170 I915_WRITE(SOUTH_CHICKEN1, temp);
5171 POSTING_READ(SOUTH_CHICKEN1);
5172}
5173
5174static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5175{
5176 struct drm_device *dev = intel_crtc->base.dev;
5177 struct drm_i915_private *dev_priv = dev->dev_private;
5178 struct intel_crtc *pipe_B_crtc =
5179 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5180
5181 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5182 intel_crtc->pipe, intel_crtc->fdi_lanes);
5183 if (intel_crtc->fdi_lanes > 4) {
5184 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5185 intel_crtc->pipe, intel_crtc->fdi_lanes);
5186 /* Clamp lanes to avoid programming the hw with bogus values. */
5187 intel_crtc->fdi_lanes = 4;
5188
5189 return false;
5190 }
5191
5192 if (dev_priv->num_pipe == 2)
5193 return true;
5194
5195 switch (intel_crtc->pipe) {
5196 case PIPE_A:
5197 return true;
5198 case PIPE_B:
5199 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5200 intel_crtc->fdi_lanes > 2) {
5201 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5202 intel_crtc->pipe, intel_crtc->fdi_lanes);
5203 /* Clamp lanes to avoid programming the hw with bogus values. */
5204 intel_crtc->fdi_lanes = 2;
5205
5206 return false;
5207 }
5208
5209 if (intel_crtc->fdi_lanes > 2)
5210 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5211 else
5212 cpt_enable_fdi_bc_bifurcation(dev);
5213
5214 return true;
5215 case PIPE_C:
5216 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5217 if (intel_crtc->fdi_lanes > 2) {
5218 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5219 intel_crtc->pipe, intel_crtc->fdi_lanes);
5220 /* Clamp lanes to avoid programming the hw with bogus values. */
5221 intel_crtc->fdi_lanes = 2;
5222
5223 return false;
5224 }
5225 } else {
5226 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5227 return false;
5228 }
5229
5230 cpt_enable_fdi_bc_bifurcation(dev);
5231
5232 return true;
5233 default:
5234 BUG();
5235 }
5236}
5237
f48d8f23
PZ		 5238static void ironlake_set_m_n(struct drm_crtc *crtc,
5239 struct drm_display_mode *mode,
5240 struct drm_display_mode *adjusted_mode)
79e53945
JB		 5241{
5242 struct drm_device *dev = crtc->dev;
5243 struct drm_i915_private *dev_priv = dev->dev_private;
5244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5245 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23 5246 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
2c07245f 5247 struct fdi_m_n m_n = {0};
f48d8f23
PZ		 5248 int target_clock, pixel_multiplier, lane, link_bw;
5249 bool is_dp = false, is_cpu_edp = false;
79e53945 5250
f48d8f23
PZ		 5251 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5252 switch (intel_encoder->type) {
a4fc5ed6
KP		 5253 case INTEL_OUTPUT_DISPLAYPORT:
5254 is_dp = true;
5255 break;
32f9d658 5256 case INTEL_OUTPUT_EDP:
e3aef172 5257 is_dp = true;
f48d8f23 5258 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5259 is_cpu_edp = true;
f48d8f23 5260 edp_encoder = intel_encoder;
32f9d658 5261 break;
79e53945 5262 }
79e53945 5263 }
61e9653f 5264
2c07245f 5265 /* FDI link */
8febb297
EA		 5266 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5267 lane = 0;
5268 /* CPU eDP doesn't require FDI link, so just set DP M/N
5269 according to current link config */
e3aef172 5270 if (is_cpu_edp) {
e3aef172 5271 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 5272 } else {
8febb297
EA		 5273 /* FDI is a binary signal running at ~2.7GHz, encoding
5274 * each output octet as 10 bits. The actual frequency
5275 * is stored as a divider into a 100MHz clock, and the
5276 * mode pixel clock is stored in units of 1KHz.
5277 * Hence the bw of each lane in terms of the mode signal
5278 * is:
5279 */
5280 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5281 }
58a27471 5282
94bf2ced
DV		 5283 /* [e]DP over FDI requires target mode clock instead of link clock. */
5284 if (edp_encoder)
5285 target_clock = intel_edp_target_clock(edp_encoder, mode);
5286 else if (is_dp)
5287 target_clock = mode->clock;
5288 else
5289 target_clock = adjusted_mode->clock;
5290
8febb297
EA		 5291 if (!lane) {
5292 /*
5293 * Account for spread spectrum to avoid
5294 * oversubscribing the link. Max center spread
5295 * is 2.5%; use 5% for safety's sake.
5296 */
5a354204 5297 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 5298 lane = bps / (link_bw * 8) + 1;
5eb08b69 5299 }
2c07245f 5300
8febb297
EA		 5301 intel_crtc->fdi_lanes = lane;
5302
5303 if (pixel_multiplier > 1)
5304 link_bw *= pixel_multiplier;
5a354204
JB		 5305 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5306 &m_n);
8febb297 5307
afe2fcf5
PZ		 5308 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5309 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5310 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5311 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5312}
5313
de13a2e3
PZ		 5314static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5315 struct drm_display_mode *adjusted_mode,
5316 intel_clock_t *clock, u32 fp)
79e53945 5317{
de13a2e3 5318 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5319 struct drm_device *dev = crtc->dev;
5320 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5321 struct intel_encoder *intel_encoder;
5322 uint32_t dpll;
5323 int factor, pixel_multiplier, num_connectors = 0;
5324 bool is_lvds = false, is_sdvo = false, is_tv = false;
5325 bool is_dp = false, is_cpu_edp = false;
79e53945 5326
de13a2e3
PZ		 5327 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5328 switch (intel_encoder->type) {
79e53945
JB		 5329 case INTEL_OUTPUT_LVDS:
5330 is_lvds = true;
5331 break;
5332 case INTEL_OUTPUT_SDVO:
7d57382e 5333 case INTEL_OUTPUT_HDMI:
79e53945 5334 is_sdvo = true;
de13a2e3 5335 if (intel_encoder->needs_tv_clock)
e2f0ba97 5336 is_tv = true;
79e53945 5337 break;
79e53945
JB		 5338 case INTEL_OUTPUT_TVOUT:
5339 is_tv = true;
5340 break;
a4fc5ed6
KP		 5341 case INTEL_OUTPUT_DISPLAYPORT:
5342 is_dp = true;
5343 break;
32f9d658 5344 case INTEL_OUTPUT_EDP:
e3aef172 5345 is_dp = true;
de13a2e3 5346 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5347 is_cpu_edp = true;
32f9d658 5348 break;
79e53945 5349 }
43565a06 5350
c751ce4f 5351 num_connectors++;
79e53945 5352 }
79e53945 5353
c1858123 5354 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5355 factor = 21;
5356 if (is_lvds) {
5357 if ((intel_panel_use_ssc(dev_priv) &&
5358 dev_priv->lvds_ssc_freq == 100) ||
a210b028 5359 is_dual_link_lvds(dev_priv, PCH_LVDS))
8febb297
EA		 5360 factor = 25;
5361 } else if (is_sdvo && is_tv)
5362 factor = 20;
c1858123 5363
de13a2e3 5364 if (clock->m < factor * clock->n)
8febb297 5365 fp |= FP_CB_TUNE;
2c07245f 5366
5eddb70b 5367 dpll = 0;
2c07245f 5368
a07d6787
EA		 5369 if (is_lvds)
5370 dpll |= DPLLB_MODE_LVDS;
5371 else
5372 dpll |= DPLLB_MODE_DAC_SERIAL;
5373 if (is_sdvo) {
de13a2e3 5374 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5375 if (pixel_multiplier > 1) {
5376 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5377 }
a07d6787
EA		 5378 dpll |= DPLL_DVO_HIGH_SPEED;
5379 }
e3aef172 5380 if (is_dp && !is_cpu_edp)
a07d6787 5381 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5382
a07d6787 5383 /* compute bitmask from p1 value */
de13a2e3 5384 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5385 /* also FPA1 */
de13a2e3 5386 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5387
de13a2e3 5388 switch (clock->p2) {
a07d6787
EA		 5389 case 5:
5390 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5391 break;
5392 case 7:
5393 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5394 break;
5395 case 10:
5396 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5397 break;
5398 case 14:
5399 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5400 break;
79e53945
JB		 5401 }
5402
43565a06
KH		 5403 if (is_sdvo && is_tv)
5404 dpll |= PLL_REF_INPUT_TVCLKINBC;
5405 else if (is_tv)
79e53945 5406 /* XXX: just matching BIOS for now */
43565a06 5407 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5408 dpll |= 3;
a7615030 5409 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5410 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5411 else
5412 dpll |= PLL_REF_INPUT_DREFCLK;
5413
de13a2e3
PZ		 5414 return dpll;
5415}
5416
5417static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5418 struct drm_display_mode *mode,
5419 struct drm_display_mode *adjusted_mode,
5420 int x, int y,
5421 struct drm_framebuffer *fb)
5422{
5423 struct drm_device *dev = crtc->dev;
5424 struct drm_i915_private *dev_priv = dev->dev_private;
5425 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5426 int pipe = intel_crtc->pipe;
5427 int plane = intel_crtc->plane;
5428 int num_connectors = 0;
5429 intel_clock_t clock, reduced_clock;
5430 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5431 bool ok, has_reduced_clock = false;
5432 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3
PZ		 5433 struct intel_encoder *encoder;
5434 u32 temp;
5435 int ret;
01a415fd 5436 bool dither, fdi_config_ok;
de13a2e3
PZ		 5437
5438 for_each_encoder_on_crtc(dev, crtc, encoder) {
5439 switch (encoder->type) {
5440 case INTEL_OUTPUT_LVDS:
5441 is_lvds = true;
5442 break;
de13a2e3
PZ		 5443 case INTEL_OUTPUT_DISPLAYPORT:
5444 is_dp = true;
5445 break;
5446 case INTEL_OUTPUT_EDP:
5447 is_dp = true;
e2f12b07 5448 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5449 is_cpu_edp = true;
5450 break;
5451 }
5452
5453 num_connectors++;
a07d6787 5454 }
79e53945 5455
5dc5298b
PZ		 5456 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5457 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5458
de13a2e3
PZ		 5459 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5460 &has_reduced_clock, &reduced_clock);
5461 if (!ok) {
5462 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5463 return -EINVAL;
79e53945
JB		 5464 }
5465
de13a2e3
PZ		 5466 /* Ensure that the cursor is valid for the new mode before changing... */
5467 intel_crtc_update_cursor(crtc, true);
5468
5469 /* determine panel color depth */
c8241969
JN		 5470 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5471 adjusted_mode);
de13a2e3
PZ		 5472 if (is_lvds && dev_priv->lvds_dither)
5473 dither = true;
5474
5475 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5476 if (has_reduced_clock)
5477 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5478 reduced_clock.m2;
5479
5480 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
79e53945 5481
f7cb34d4 5482 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5483 drm_mode_debug_printmodeline(mode);
5484
5dc5298b
PZ		 5485 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5486 if (!is_cpu_edp) {
ee7b9f93 5487 struct intel_pch_pll *pll;
4b645f14 5488
ee7b9f93
JB		 5489 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5490 if (pll == NULL) {
5491 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5492 pipe);
4b645f14
JB		 5493 return -EINVAL;
5494 }
ee7b9f93
JB		 5495 } else
5496 intel_put_pch_pll(intel_crtc);
79e53945
JB		 5497
5498 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5499 * This is an exception to the general rule that mode_set doesn't turn
5500 * things on.
5501 */
5502 if (is_lvds) {
fae14981 5503 temp = I915_READ(PCH_LVDS);
5eddb70b 5504 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 5505 if (HAS_PCH_CPT(dev)) {
5506 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 5507 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 5508 } else {
5509 if (pipe == 1)
5510 temp |= LVDS_PIPEB_SELECT;
5511 else
5512 temp &= ~LVDS_PIPEB_SELECT;
5513 }
4b645f14 5514
a3e17eb8 5515 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5516 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5517 /* Set the B0-B3 data pairs corresponding to whether we're going to
5518 * set the DPLLs for dual-channel mode or not.
5519 */
5520 if (clock.p2 == 7)
5eddb70b 5521 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5522 else
5eddb70b 5523 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5524
5525 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5526 * appropriately here, but we need to look more thoroughly into how
5527 * panels behave in the two modes.
5528 */
284d5df5 5529 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 5530 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 5531 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 5532 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 5533 temp |= LVDS_VSYNC_POLARITY;
fae14981 5534 I915_WRITE(PCH_LVDS, temp);
79e53945 5535 }
434ed097 5536
e3aef172 5537 if (is_dp && !is_cpu_edp) {
a4fc5ed6 5538 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5539 } else {
8db9d77b 5540 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5541 I915_WRITE(TRANSDATA_M1(pipe), 0);
5542 I915_WRITE(TRANSDATA_N1(pipe), 0);
5543 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5544 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5545 }
79e53945 5546
dafd226c
DV		 5547 for_each_encoder_on_crtc(dev, crtc, encoder)
5548 if (encoder->pre_pll_enable)
5549 encoder->pre_pll_enable(encoder);
5550
ee7b9f93
JB		 5551 if (intel_crtc->pch_pll) {
5552 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5553
32f9d658 5554 /* Wait for the clocks to stabilize. */
ee7b9f93 5555 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5556 udelay(150);
5557
8febb297
EA		 5558 /* The pixel multiplier can only be updated once the
5559 * DPLL is enabled and the clocks are stable.
5560 *
5561 * So write it again.
5562 */
ee7b9f93 5563 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5564 }
79e53945 5565
5eddb70b 5566 intel_crtc->lowfreq_avail = false;
ee7b9f93 5567 if (intel_crtc->pch_pll) {
4b645f14 5568 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5569 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5570 intel_crtc->lowfreq_avail = true;
4b645f14 5571 } else {
ee7b9f93 5572 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5573 }
5574 }
5575
b0e77b9c 5576 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5577
01a415fd
DV		 5578 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5579 * ironlake_check_fdi_lanes. */
f48d8f23 5580 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5581
01a415fd 5582 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5583
e3aef172 5584 if (is_cpu_edp)
8febb297 5585 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 5586
c8203565 5587 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5588
9d0498a2 5589 intel_wait_for_vblank(dev, pipe);
79e53945 5590
a1f9e77e
PZ		 5591 /* Set up the display plane register */
5592 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5593 POSTING_READ(DSPCNTR(plane));
79e53945 5594
94352cf9 5595 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5596
5597 intel_update_watermarks(dev);
5598
1f8eeabf
ED		 5599 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5600
01a415fd 5601 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5602}
5603
09b4ddf9
PZ		 5604static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5605 struct drm_display_mode *mode,
5606 struct drm_display_mode *adjusted_mode,
5607 int x, int y,
5608 struct drm_framebuffer *fb)
5609{
5610 struct drm_device *dev = crtc->dev;
5611 struct drm_i915_private *dev_priv = dev->dev_private;
5612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5613 int pipe = intel_crtc->pipe;
5614 int plane = intel_crtc->plane;
5615 int num_connectors = 0;
5616 intel_clock_t clock, reduced_clock;
5dc5298b 5617 u32 dpll = 0, fp = 0, fp2 = 0;
09b4ddf9
PZ		 5618 bool ok, has_reduced_clock = false;
5619 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5620 struct intel_encoder *encoder;
5621 u32 temp;
5622 int ret;
5623 bool dither;
5624
5625 for_each_encoder_on_crtc(dev, crtc, encoder) {
5626 switch (encoder->type) {
5627 case INTEL_OUTPUT_LVDS:
5628 is_lvds = true;
5629 break;
5630 case INTEL_OUTPUT_DISPLAYPORT:
5631 is_dp = true;
5632 break;
5633 case INTEL_OUTPUT_EDP:
5634 is_dp = true;
5635 if (!intel_encoder_is_pch_edp(&encoder->base))
5636 is_cpu_edp = true;
5637 break;
5638 }
5639
5640 num_connectors++;
5641 }
5642
a5c961d1
PZ		 5643 if (is_cpu_edp)
5644 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5645 else
5646 intel_crtc->cpu_transcoder = pipe;
5647
5dc5298b
PZ		 5648 /* We are not sure yet this won't happen. */
5649 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5650 INTEL_PCH_TYPE(dev));
5651
5652 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5653 num_connectors, pipe_name(pipe));
5654
702e7a56 5655 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5656 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5657
5658 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5659
6441ab5f
PZ		 5660 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5661 return -EINVAL;
5662
5dc5298b
PZ		 5663 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5664 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5665 &has_reduced_clock,
5666 &reduced_clock);
5667 if (!ok) {
5668 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5669 return -EINVAL;
5670 }
09b4ddf9
PZ		 5671 }
5672
5673 /* Ensure that the cursor is valid for the new mode before changing... */
5674 intel_crtc_update_cursor(crtc, true);
5675
5676 /* determine panel color depth */
c8241969
JN		 5677 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5678 adjusted_mode);
09b4ddf9
PZ		 5679 if (is_lvds && dev_priv->lvds_dither)
5680 dither = true;
5681
09b4ddf9
PZ		 5682 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5683 drm_mode_debug_printmodeline(mode);
5684
5dc5298b
PZ		 5685 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5686 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5687 if (has_reduced_clock)
5688 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5689 reduced_clock.m2;
5690
5691 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5692 fp);
5693
5694 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5695 * own on pre-Haswell/LPT generation */
5696 if (!is_cpu_edp) {
5697 struct intel_pch_pll *pll;
5698
5699 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5700 if (pll == NULL) {
5701 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5702 pipe);
5703 return -EINVAL;
5704 }
5705 } else
5706 intel_put_pch_pll(intel_crtc);
09b4ddf9 5707
5dc5298b
PZ		 5708 /* The LVDS pin pair needs to be on before the DPLLs are
5709 * enabled. This is an exception to the general rule that
5710 * mode_set doesn't turn things on.
5711 */
5712 if (is_lvds) {
5713 temp = I915_READ(PCH_LVDS);
5714 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5715 if (HAS_PCH_CPT(dev)) {
5716 temp &= ~PORT_TRANS_SEL_MASK;
5717 temp |= PORT_TRANS_SEL_CPT(pipe);
5718 } else {
5719 if (pipe == 1)
5720 temp |= LVDS_PIPEB_SELECT;
5721 else
5722 temp &= ~LVDS_PIPEB_SELECT;
5723 }
09b4ddf9 5724
5dc5298b
PZ		 5725 /* set the corresponsding LVDS_BORDER bit */
5726 temp |= dev_priv->lvds_border_bits;
5727 /* Set the B0-B3 data pairs corresponding to whether
5728 * we're going to set the DPLLs for dual-channel mode or
5729 * not.
5730 */
5731 if (clock.p2 == 7)
5732 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
09b4ddf9 5733 else
5dc5298b
PZ		 5734 temp &= ~(LVDS_B0B3_POWER_UP |
5735 LVDS_CLKB_POWER_UP);
5736
5737 /* It would be nice to set 24 vs 18-bit mode
5738 * (LVDS_A3_POWER_UP) appropriately here, but we need to
5739 * look more thoroughly into how panels behave in the
5740 * two modes.
5741 */
5742 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5743 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5744 temp |= LVDS_HSYNC_POLARITY;
5745 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5746 temp |= LVDS_VSYNC_POLARITY;
5747 I915_WRITE(PCH_LVDS, temp);
09b4ddf9 5748 }
09b4ddf9
PZ		 5749 }
5750
5751 if (is_dp && !is_cpu_edp) {
5752 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5753 } else {
5dc5298b
PZ		 5754 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5755 /* For non-DP output, clear any trans DP clock recovery
5756 * setting.*/
5757 I915_WRITE(TRANSDATA_M1(pipe), 0);
5758 I915_WRITE(TRANSDATA_N1(pipe), 0);
5759 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5760 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5761 }
09b4ddf9
PZ		 5762 }
5763
5764 intel_crtc->lowfreq_avail = false;
5dc5298b
PZ		 5765 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5766 if (intel_crtc->pch_pll) {
5767 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5768
5769 /* Wait for the clocks to stabilize. */
5770 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5771 udelay(150);
5772
5773 /* The pixel multiplier can only be updated once the
5774 * DPLL is enabled and the clocks are stable.
5775 *
5776 * So write it again.
5777 */
5778 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5779 }
5780
5781 if (intel_crtc->pch_pll) {
5782 if (is_lvds && has_reduced_clock && i915_powersave) {
5783 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5784 intel_crtc->lowfreq_avail = true;
5785 } else {
5786 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5787 }
09b4ddf9
PZ		 5788 }
5789 }
5790
5791 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5792
1eb8dfec
PZ		 5793 if (!is_dp || is_cpu_edp)
5794 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5795
5dc5298b
PZ		 5796 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5797 if (is_cpu_edp)
5798 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
09b4ddf9 5799
ee2b0b38 5800 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5801
09b4ddf9
PZ		 5802 /* Set up the display plane register */
5803 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5804 POSTING_READ(DSPCNTR(plane));
5805
5806 ret = intel_pipe_set_base(crtc, x, y, fb);
5807
5808 intel_update_watermarks(dev);
5809
5810 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5811
1f803ee5 5812 return ret;
79e53945
JB		 5813}
5814
f564048e
EA		 5815static int intel_crtc_mode_set(struct drm_crtc *crtc,
5816 struct drm_display_mode *mode,
5817 struct drm_display_mode *adjusted_mode,
5818 int x, int y,
94352cf9 5819 struct drm_framebuffer *fb)
f564048e
EA		 5820{
5821 struct drm_device *dev = crtc->dev;
5822 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5823 struct drm_encoder_helper_funcs *encoder_funcs;
5824 struct intel_encoder *encoder;
0b701d27
EA		 5825 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5826 int pipe = intel_crtc->pipe;
f564048e
EA		 5827 int ret;
5828
0b701d27 5829 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5830
f564048e 5831 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5832 x, y, fb);
79e53945 5833 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5834
9256aa19
DV		 5835 if (ret != 0)
5836 return ret;
5837
5838 for_each_encoder_on_crtc(dev, crtc, encoder) {
5839 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5840 encoder->base.base.id,
5841 drm_get_encoder_name(&encoder->base),
5842 mode->base.id, mode->name);
5843 encoder_funcs = encoder->base.helper_private;
5844 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5845 }
5846
5847 return 0;
79e53945
JB		 5848}
5849
3a9627f4
WF		 5850static bool intel_eld_uptodate(struct drm_connector *connector,
5851 int reg_eldv, uint32_t bits_eldv,
5852 int reg_elda, uint32_t bits_elda,
5853 int reg_edid)
5854{
5855 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5856 uint8_t *eld = connector->eld;
5857 uint32_t i;
5858
5859 i = I915_READ(reg_eldv);
5860 i &= bits_eldv;
5861
5862 if (!eld[0])
5863 return !i;
5864
5865 if (!i)
5866 return false;
5867
5868 i = I915_READ(reg_elda);
5869 i &= ~bits_elda;
5870 I915_WRITE(reg_elda, i);
5871
5872 for (i = 0; i < eld[2]; i++)
5873 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5874 return false;
5875
5876 return true;
5877}
5878
e0dac65e
WF		 5879static void g4x_write_eld(struct drm_connector *connector,
5880 struct drm_crtc *crtc)
5881{
5882 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5883 uint8_t *eld = connector->eld;
5884 uint32_t eldv;
5885 uint32_t len;
5886 uint32_t i;
5887
5888 i = I915_READ(G4X_AUD_VID_DID);
5889
5890 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5891 eldv = G4X_ELDV_DEVCL_DEVBLC;
5892 else
5893 eldv = G4X_ELDV_DEVCTG;
5894
3a9627f4
WF		 5895 if (intel_eld_uptodate(connector,
5896 G4X_AUD_CNTL_ST, eldv,
5897 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5898 G4X_HDMIW_HDMIEDID))
5899 return;
5900
e0dac65e
WF		 5901 i = I915_READ(G4X_AUD_CNTL_ST);
5902 i &= ~(eldv | G4X_ELD_ADDR);
5903 len = (i >> 9) & 0x1f; /* ELD buffer size */
5904 I915_WRITE(G4X_AUD_CNTL_ST, i);
5905
5906 if (!eld[0])
5907 return;
5908
5909 len = min_t(uint8_t, eld[2], len);
5910 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5911 for (i = 0; i < len; i++)
5912 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5913
5914 i = I915_READ(G4X_AUD_CNTL_ST);
5915 i |= eldv;
5916 I915_WRITE(G4X_AUD_CNTL_ST, i);
5917}
5918
83358c85
WX		 5919static void haswell_write_eld(struct drm_connector *connector,
5920 struct drm_crtc *crtc)
5921{
5922 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5923 uint8_t *eld = connector->eld;
5924 struct drm_device *dev = crtc->dev;
5925 uint32_t eldv;
5926 uint32_t i;
5927 int len;
5928 int pipe = to_intel_crtc(crtc)->pipe;
5929 int tmp;
5930
5931 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5932 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5933 int aud_config = HSW_AUD_CFG(pipe);
5934 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5935
5936
5937 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5938
5939 /* Audio output enable */
5940 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5941 tmp = I915_READ(aud_cntrl_st2);
5942 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5943 I915_WRITE(aud_cntrl_st2, tmp);
5944
5945 /* Wait for 1 vertical blank */
5946 intel_wait_for_vblank(dev, pipe);
5947
5948 /* Set ELD valid state */
5949 tmp = I915_READ(aud_cntrl_st2);
5950 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5951 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5952 I915_WRITE(aud_cntrl_st2, tmp);
5953 tmp = I915_READ(aud_cntrl_st2);
5954 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5955
5956 /* Enable HDMI mode */
5957 tmp = I915_READ(aud_config);
5958 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5959 /* clear N_programing_enable and N_value_index */
5960 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5961 I915_WRITE(aud_config, tmp);
5962
5963 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5964
5965 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5966
5967 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5968 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5969 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5970 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5971 } else
5972 I915_WRITE(aud_config, 0);
5973
5974 if (intel_eld_uptodate(connector,
5975 aud_cntrl_st2, eldv,
5976 aud_cntl_st, IBX_ELD_ADDRESS,
5977 hdmiw_hdmiedid))
5978 return;
5979
5980 i = I915_READ(aud_cntrl_st2);
5981 i &= ~eldv;
5982 I915_WRITE(aud_cntrl_st2, i);
5983
5984 if (!eld[0])
5985 return;
5986
5987 i = I915_READ(aud_cntl_st);
5988 i &= ~IBX_ELD_ADDRESS;
5989 I915_WRITE(aud_cntl_st, i);
5990 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5991 DRM_DEBUG_DRIVER("port num:%d\n", i);
5992
5993 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5994 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5995 for (i = 0; i < len; i++)
5996 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5997
5998 i = I915_READ(aud_cntrl_st2);
5999 i |= eldv;
6000 I915_WRITE(aud_cntrl_st2, i);
6001
6002}
6003
e0dac65e
WF		 6004static void ironlake_write_eld(struct drm_connector *connector,
6005 struct drm_crtc *crtc)
6006{
6007 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6008 uint8_t *eld = connector->eld;
6009 uint32_t eldv;
6010 uint32_t i;
6011 int len;
6012 int hdmiw_hdmiedid;
b6daa025 6013 int aud_config;
e0dac65e
WF		 6014 int aud_cntl_st;
6015 int aud_cntrl_st2;
9b138a83 6016 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6017
b3f33cbf 6018 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6019 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6020 aud_config = IBX_AUD_CFG(pipe);
6021 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6022 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6023 } else {
9b138a83
WX		 6024 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6025 aud_config = CPT_AUD_CFG(pipe);
6026 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6027 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6028 }
6029
9b138a83 6030 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6031
6032 i = I915_READ(aud_cntl_st);
9b138a83 6033 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6034 if (!i) {
6035 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6036 /* operate blindly on all ports */
1202b4c6
WF		 6037 eldv = IBX_ELD_VALIDB;
6038 eldv |= IBX_ELD_VALIDB << 4;
6039 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6040 } else {
6041 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6042 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6043 }
6044
3a9627f4
WF		 6045 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6046 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6047 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6048 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6049 } else
6050 I915_WRITE(aud_config, 0);
e0dac65e 6051
3a9627f4
WF		 6052 if (intel_eld_uptodate(connector,
6053 aud_cntrl_st2, eldv,
6054 aud_cntl_st, IBX_ELD_ADDRESS,
6055 hdmiw_hdmiedid))
6056 return;
6057
e0dac65e
WF		 6058 i = I915_READ(aud_cntrl_st2);
6059 i &= ~eldv;
6060 I915_WRITE(aud_cntrl_st2, i);
6061
6062 if (!eld[0])
6063 return;
6064
e0dac65e 6065 i = I915_READ(aud_cntl_st);
1202b4c6 6066 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6067 I915_WRITE(aud_cntl_st, i);
6068
6069 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6070 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6071 for (i = 0; i < len; i++)
6072 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6073
6074 i = I915_READ(aud_cntrl_st2);
6075 i |= eldv;
6076 I915_WRITE(aud_cntrl_st2, i);
6077}
6078
6079void intel_write_eld(struct drm_encoder *encoder,
6080 struct drm_display_mode *mode)
6081{
6082 struct drm_crtc *crtc = encoder->crtc;
6083 struct drm_connector *connector;
6084 struct drm_device *dev = encoder->dev;
6085 struct drm_i915_private *dev_priv = dev->dev_private;
6086
6087 connector = drm_select_eld(encoder, mode);
6088 if (!connector)
6089 return;
6090
6091 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6092 connector->base.id,
6093 drm_get_connector_name(connector),
6094 connector->encoder->base.id,
6095 drm_get_encoder_name(connector->encoder));
6096
6097 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6098
6099 if (dev_priv->display.write_eld)
6100 dev_priv->display.write_eld(connector, crtc);
6101}
6102
79e53945
JB		 6103/** Loads the palette/gamma unit for the CRTC with the prepared values */
6104void intel_crtc_load_lut(struct drm_crtc *crtc)
6105{
6106 struct drm_device *dev = crtc->dev;
6107 struct drm_i915_private *dev_priv = dev->dev_private;
6108 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6109 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6110 int i;
6111
6112 /* The clocks have to be on to load the palette. */
aed3f09d 6113 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6114 return;
6115
f2b115e6 6116 /* use legacy palette for Ironlake */
bad720ff 6117 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6118 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6119
79e53945
JB		 6120 for (i = 0; i < 256; i++) {
6121 I915_WRITE(palreg + 4 * i,
6122 (intel_crtc->lut_r[i] << 16) |
6123 (intel_crtc->lut_g[i] << 8) |
6124 intel_crtc->lut_b[i]);
6125 }
6126}
6127
560b85bb
CW		 6128static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6129{
6130 struct drm_device *dev = crtc->dev;
6131 struct drm_i915_private *dev_priv = dev->dev_private;
6132 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6133 bool visible = base != 0;
6134 u32 cntl;
6135
6136 if (intel_crtc->cursor_visible == visible)
6137 return;
6138
9db4a9c7 6139 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6140 if (visible) {
6141 /* On these chipsets we can only modify the base whilst
6142 * the cursor is disabled.
6143 */
9db4a9c7 6144 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6145
6146 cntl &= ~(CURSOR_FORMAT_MASK);
6147 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6148 cntl |= CURSOR_ENABLE |
6149 CURSOR_GAMMA_ENABLE |
6150 CURSOR_FORMAT_ARGB;
6151 } else
6152 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6153 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6154
6155 intel_crtc->cursor_visible = visible;
6156}
6157
6158static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6159{
6160 struct drm_device *dev = crtc->dev;
6161 struct drm_i915_private *dev_priv = dev->dev_private;
6162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6163 int pipe = intel_crtc->pipe;
6164 bool visible = base != 0;
6165
6166 if (intel_crtc->cursor_visible != visible) {
548f245b 6167 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6168 if (base) {
6169 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6170 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6171 cntl |= pipe << 28; /* Connect to correct pipe */
6172 } else {
6173 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6174 cntl |= CURSOR_MODE_DISABLE;
6175 }
9db4a9c7 6176 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6177
6178 intel_crtc->cursor_visible = visible;
6179 }
6180 /* and commit changes on next vblank */
9db4a9c7 6181 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6182}
6183
65a21cd6
JB		 6184static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6185{
6186 struct drm_device *dev = crtc->dev;
6187 struct drm_i915_private *dev_priv = dev->dev_private;
6188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6189 int pipe = intel_crtc->pipe;
6190 bool visible = base != 0;
6191
6192 if (intel_crtc->cursor_visible != visible) {
6193 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6194 if (base) {
6195 cntl &= ~CURSOR_MODE;
6196 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6197 } else {
6198 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6199 cntl |= CURSOR_MODE_DISABLE;
6200 }
6201 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6202
6203 intel_crtc->cursor_visible = visible;
6204 }
6205 /* and commit changes on next vblank */
6206 I915_WRITE(CURBASE_IVB(pipe), base);
6207}
6208
cda4b7d3 6209/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6210static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6211 bool on)
cda4b7d3
CW		 6212{
6213 struct drm_device *dev = crtc->dev;
6214 struct drm_i915_private *dev_priv = dev->dev_private;
6215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6216 int pipe = intel_crtc->pipe;
6217 int x = intel_crtc->cursor_x;
6218 int y = intel_crtc->cursor_y;
560b85bb 6219 u32 base, pos;
cda4b7d3
CW		 6220 bool visible;
6221
6222 pos = 0;
6223
6b383a7f 6224 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6225 base = intel_crtc->cursor_addr;
6226 if (x > (int) crtc->fb->width)
6227 base = 0;
6228
6229 if (y > (int) crtc->fb->height)
6230 base = 0;
6231 } else
6232 base = 0;
6233
6234 if (x < 0) {
6235 if (x + intel_crtc->cursor_width < 0)
6236 base = 0;
6237
6238 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6239 x = -x;
6240 }
6241 pos |= x << CURSOR_X_SHIFT;
6242
6243 if (y < 0) {
6244 if (y + intel_crtc->cursor_height < 0)
6245 base = 0;
6246
6247 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6248 y = -y;
6249 }
6250 pos |= y << CURSOR_Y_SHIFT;
6251
6252 visible = base != 0;
560b85bb 6253 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6254 return;
6255
0cd83aa9 6256 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6257 I915_WRITE(CURPOS_IVB(pipe), pos);
6258 ivb_update_cursor(crtc, base);
6259 } else {
6260 I915_WRITE(CURPOS(pipe), pos);
6261 if (IS_845G(dev) || IS_I865G(dev))
6262 i845_update_cursor(crtc, base);
6263 else
6264 i9xx_update_cursor(crtc, base);
6265 }
cda4b7d3
CW		 6266}
6267
79e53945 6268static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6269 struct drm_file *file,
79e53945
JB		 6270 uint32_t handle,
6271 uint32_t width, uint32_t height)
6272{
6273 struct drm_device *dev = crtc->dev;
6274 struct drm_i915_private *dev_priv = dev->dev_private;
6275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6276 struct drm_i915_gem_object *obj;
cda4b7d3 6277 uint32_t addr;
3f8bc370 6278 int ret;
79e53945 6279
79e53945
JB		 6280 /* if we want to turn off the cursor ignore width and height */
6281 if (!handle) {
28c97730 6282 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6283 addr = 0;
05394f39 6284 obj = NULL;
5004417d 6285 mutex_lock(&dev->struct_mutex);
3f8bc370 6286 goto finish;
79e53945
JB		 6287 }
6288
6289 /* Currently we only support 64x64 cursors */
6290 if (width != 64 || height != 64) {
6291 DRM_ERROR("we currently only support 64x64 cursors\n");
6292 return -EINVAL;
6293 }
6294
05394f39 6295 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6296 if (&obj->base == NULL)
79e53945
JB		 6297 return -ENOENT;
6298
05394f39 6299 if (obj->base.size < width * height * 4) {
79e53945 6300 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6301 ret = -ENOMEM;
6302 goto fail;
79e53945
JB		 6303 }
6304
71acb5eb 6305 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6306 mutex_lock(&dev->struct_mutex);
b295d1b6 6307 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6308 if (obj->tiling_mode) {
6309 DRM_ERROR("cursor cannot be tiled\n");
6310 ret = -EINVAL;
6311 goto fail_locked;
6312 }
6313
2da3b9b9 6314 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6315 if (ret) {
6316 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6317 goto fail_locked;
e7b526bb
CW		 6318 }
6319
d9e86c0e
CW		 6320 ret = i915_gem_object_put_fence(obj);
6321 if (ret) {
2da3b9b9 6322 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6323 goto fail_unpin;
6324 }
6325
05394f39 6326 addr = obj->gtt_offset;
71acb5eb 6327 } else {
6eeefaf3 6328 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6329 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6330 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6331 align);
71acb5eb
DA		 6332 if (ret) {
6333 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6334 goto fail_locked;
71acb5eb 6335 }
05394f39 6336 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6337 }
6338
a6c45cf0 6339 if (IS_GEN2(dev))
14b60391
JB		 6340 I915_WRITE(CURSIZE, (height << 12) | width);
6341
3f8bc370 6342 finish:
3f8bc370 6343 if (intel_crtc->cursor_bo) {
b295d1b6 6344 if (dev_priv->info->cursor_needs_physical) {
05394f39 6345 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6346 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6347 } else
6348 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6349 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6350 }
80824003 6351
7f9872e0 6352 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6353
6354 intel_crtc->cursor_addr = addr;
05394f39 6355 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6356 intel_crtc->cursor_width = width;
6357 intel_crtc->cursor_height = height;
6358
6b383a7f 6359 intel_crtc_update_cursor(crtc, true);
3f8bc370 6360
79e53945 6361 return 0;
e7b526bb 6362fail_unpin:
05394f39 6363 i915_gem_object_unpin(obj);
7f9872e0 6364fail_locked:
34b8686e 6365 mutex_unlock(&dev->struct_mutex);
bc9025bd 6366fail:
05394f39 6367 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6368 return ret;
79e53945
JB		 6369}
6370
6371static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6372{
79e53945 6373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6374
cda4b7d3
CW		 6375 intel_crtc->cursor_x = x;
6376 intel_crtc->cursor_y = y;
652c393a 6377
6b383a7f 6378 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6379
6380 return 0;
6381}
6382
6383/** Sets the color ramps on behalf of RandR */
6384void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6385 u16 blue, int regno)
6386{
6387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6388
6389 intel_crtc->lut_r[regno] = red >> 8;
6390 intel_crtc->lut_g[regno] = green >> 8;
6391 intel_crtc->lut_b[regno] = blue >> 8;
6392}
6393
b8c00ac5
DA		 6394void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6395 u16 *blue, int regno)
6396{
6397 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6398
6399 *red = intel_crtc->lut_r[regno] << 8;
6400 *green = intel_crtc->lut_g[regno] << 8;
6401 *blue = intel_crtc->lut_b[regno] << 8;
6402}
6403
79e53945 6404static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6405 u16 *blue, uint32_t start, uint32_t size)
79e53945 6406{
7203425a 6407 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6409
7203425a 6410 for (i = start; i < end; i++) {
79e53945
JB		 6411 intel_crtc->lut_r[i] = red[i] >> 8;
6412 intel_crtc->lut_g[i] = green[i] >> 8;
6413 intel_crtc->lut_b[i] = blue[i] >> 8;
6414 }
6415
6416 intel_crtc_load_lut(crtc);
6417}
6418
6419/**
6420 * Get a pipe with a simple mode set on it for doing load-based monitor
6421 * detection.
6422 *
6423 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6424 * its requirements. The pipe will be connected to no other encoders.
79e53945 6425 *
c751ce4f 6426 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6427 * configured for it. In the future, it could choose to temporarily disable
6428 * some outputs to free up a pipe for its use.
6429 *
6430 * \return crtc, or NULL if no pipes are available.
6431 */
6432
6433/* VESA 640x480x72Hz mode to set on the pipe */
6434static struct drm_display_mode load_detect_mode = {
6435 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6436 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6437};
6438
d2dff872
CW		 6439static struct drm_framebuffer *
6440intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6441 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6442 struct drm_i915_gem_object *obj)
6443{
6444 struct intel_framebuffer *intel_fb;
6445 int ret;
6446
6447 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6448 if (!intel_fb) {
6449 drm_gem_object_unreference_unlocked(&obj->base);
6450 return ERR_PTR(-ENOMEM);
6451 }
6452
6453 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6454 if (ret) {
6455 drm_gem_object_unreference_unlocked(&obj->base);
6456 kfree(intel_fb);
6457 return ERR_PTR(ret);
6458 }
6459
6460 return &intel_fb->base;
6461}
6462
6463static u32
6464intel_framebuffer_pitch_for_width(int width, int bpp)
6465{
6466 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6467 return ALIGN(pitch, 64);
6468}
6469
6470static u32
6471intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6472{
6473 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6474 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6475}
6476
6477static struct drm_framebuffer *
6478intel_framebuffer_create_for_mode(struct drm_device *dev,
6479 struct drm_display_mode *mode,
6480 int depth, int bpp)
6481{
6482 struct drm_i915_gem_object *obj;
0fed39bd 6483 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6484
6485 obj = i915_gem_alloc_object(dev,
6486 intel_framebuffer_size_for_mode(mode, bpp));
6487 if (obj == NULL)
6488 return ERR_PTR(-ENOMEM);
6489
6490 mode_cmd.width = mode->hdisplay;
6491 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6492 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6493 bpp);
5ca0c34a 6494 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6495
6496 return intel_framebuffer_create(dev, &mode_cmd, obj);
6497}
6498
6499static struct drm_framebuffer *
6500mode_fits_in_fbdev(struct drm_device *dev,
6501 struct drm_display_mode *mode)
6502{
6503 struct drm_i915_private *dev_priv = dev->dev_private;
6504 struct drm_i915_gem_object *obj;
6505 struct drm_framebuffer *fb;
6506
6507 if (dev_priv->fbdev == NULL)
6508 return NULL;
6509
6510 obj = dev_priv->fbdev->ifb.obj;
6511 if (obj == NULL)
6512 return NULL;
6513
6514 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6515 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6516 fb->bits_per_pixel))
d2dff872
CW		 6517 return NULL;
6518
01f2c773 6519 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6520 return NULL;
6521
6522 return fb;
6523}
6524
d2434ab7 6525bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6526 struct drm_display_mode *mode,
8261b191 6527 struct intel_load_detect_pipe *old)
79e53945
JB		 6528{
6529 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6530 struct intel_encoder *intel_encoder =
6531 intel_attached_encoder(connector);
79e53945 6532 struct drm_crtc *possible_crtc;
4ef69c7a 6533 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6534 struct drm_crtc *crtc = NULL;
6535 struct drm_device *dev = encoder->dev;
94352cf9 6536 struct drm_framebuffer *fb;
79e53945
JB		 6537 int i = -1;
6538
d2dff872
CW		 6539 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6540 connector->base.id, drm_get_connector_name(connector),
6541 encoder->base.id, drm_get_encoder_name(encoder));
6542
79e53945
JB		 6543 /*
6544 * Algorithm gets a little messy:
7a5e4805 6545 *
79e53945
JB		 6546 * - if the connector already has an assigned crtc, use it (but make
6547 * sure it's on first)
7a5e4805 6548 *
79e53945
JB		 6549 * - try to find the first unused crtc that can drive this connector,
6550 * and use that if we find one
79e53945
JB		 6551 */
6552
6553 /* See if we already have a CRTC for this connector */
6554 if (encoder->crtc) {
6555 crtc = encoder->crtc;
8261b191 6556
24218aac 6557 old->dpms_mode = connector->dpms;
8261b191
CW		 6558 old->load_detect_temp = false;
6559
6560 /* Make sure the crtc and connector are running */
24218aac
DV		 6561 if (connector->dpms != DRM_MODE_DPMS_ON)
6562 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6563
7173188d 6564 return true;
79e53945
JB		 6565 }
6566
6567 /* Find an unused one (if possible) */
6568 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6569 i++;
6570 if (!(encoder->possible_crtcs & (1 << i)))
6571 continue;
6572 if (!possible_crtc->enabled) {
6573 crtc = possible_crtc;
6574 break;
6575 }
79e53945
JB		 6576 }
6577
6578 /*
6579 * If we didn't find an unused CRTC, don't use any.
6580 */
6581 if (!crtc) {
7173188d
CW		 6582 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6583 return false;
79e53945
JB		 6584 }
6585
fc303101
DV		 6586 intel_encoder->new_crtc = to_intel_crtc(crtc);
6587 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6588
6589 intel_crtc = to_intel_crtc(crtc);
24218aac 6590 old->dpms_mode = connector->dpms;
8261b191 6591 old->load_detect_temp = true;
d2dff872 6592 old->release_fb = NULL;
79e53945 6593
6492711d
CW		 6594 if (!mode)
6595 mode = &load_detect_mode;
79e53945 6596
d2dff872
CW		 6597 /* We need a framebuffer large enough to accommodate all accesses
6598 * that the plane may generate whilst we perform load detection.
6599 * We can not rely on the fbcon either being present (we get called
6600 * during its initialisation to detect all boot displays, or it may
6601 * not even exist) or that it is large enough to satisfy the
6602 * requested mode.
6603 */
94352cf9
DV		 6604 fb = mode_fits_in_fbdev(dev, mode);
6605 if (fb == NULL) {
d2dff872 6606 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6607 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6608 old->release_fb = fb;
d2dff872
CW		 6609 } else
6610 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6611 if (IS_ERR(fb)) {
d2dff872 6612 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
0e8b3d3e 6613 return false;
79e53945 6614 }
79e53945 6615
94352cf9 6616 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6617 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6618 if (old->release_fb)
6619 old->release_fb->funcs->destroy(old->release_fb);
0e8b3d3e 6620 return false;
79e53945 6621 }
7173188d 6622
79e53945 6623 /* let the connector get through one full cycle before testing */
9d0498a2 6624 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6625 return true;
79e53945
JB		 6626}
6627
d2434ab7 6628void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6629 struct intel_load_detect_pipe *old)
79e53945 6630{
d2434ab7
DV		 6631 struct intel_encoder *intel_encoder =
6632 intel_attached_encoder(connector);
4ef69c7a 6633 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 6634
d2dff872
CW		 6635 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6636 connector->base.id, drm_get_connector_name(connector),
6637 encoder->base.id, drm_get_encoder_name(encoder));
6638
8261b191 6639 if (old->load_detect_temp) {
fc303101
DV		 6640 struct drm_crtc *crtc = encoder->crtc;
6641
6642 to_intel_connector(connector)->new_encoder = NULL;
6643 intel_encoder->new_crtc = NULL;
6644 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 6645
6646 if (old->release_fb)
6647 old->release_fb->funcs->destroy(old->release_fb);
6648
0622a53c 6649 return;
79e53945
JB		 6650 }
6651
c751ce4f 6652 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6653 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6654 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 6655}
6656
6657/* Returns the clock of the currently programmed mode of the given pipe. */
6658static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6659{
6660 struct drm_i915_private *dev_priv = dev->dev_private;
6661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6662 int pipe = intel_crtc->pipe;
548f245b 6663 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6664 u32 fp;
6665 intel_clock_t clock;
6666
6667 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6668 fp = I915_READ(FP0(pipe));
79e53945 6669 else
39adb7a5 6670 fp = I915_READ(FP1(pipe));
79e53945
JB		 6671
6672 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6673 if (IS_PINEVIEW(dev)) {
6674 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6675 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6676 } else {
6677 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6678 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6679 }
6680
a6c45cf0 6681 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6682 if (IS_PINEVIEW(dev))
6683 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6684 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6685 else
6686 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6687 DPLL_FPA01_P1_POST_DIV_SHIFT);
6688
6689 switch (dpll & DPLL_MODE_MASK) {
6690 case DPLLB_MODE_DAC_SERIAL:
6691 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6692 5 : 10;
6693 break;
6694 case DPLLB_MODE_LVDS:
6695 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6696 7 : 14;
6697 break;
6698 default:
28c97730 6699 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6700 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6701 return 0;
6702 }
6703
6704 /* XXX: Handle the 100Mhz refclk */
2177832f 6705 intel_clock(dev, 96000, &clock);
79e53945
JB		 6706 } else {
6707 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6708
6709 if (is_lvds) {
6710 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6711 DPLL_FPA01_P1_POST_DIV_SHIFT);
6712 clock.p2 = 14;
6713
6714 if ((dpll & PLL_REF_INPUT_MASK) ==
6715 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6716 /* XXX: might not be 66MHz */
2177832f 6717 intel_clock(dev, 66000, &clock);
79e53945 6718 } else
2177832f 6719 intel_clock(dev, 48000, &clock);
79e53945
JB		 6720 } else {
6721 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6722 clock.p1 = 2;
6723 else {
6724 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6725 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6726 }
6727 if (dpll & PLL_P2_DIVIDE_BY_4)
6728 clock.p2 = 4;
6729 else
6730 clock.p2 = 2;
6731
2177832f 6732 intel_clock(dev, 48000, &clock);
79e53945
JB		 6733 }
6734 }
6735
6736 /* XXX: It would be nice to validate the clocks, but we can't reuse
6737 * i830PllIsValid() because it relies on the xf86_config connector
6738 * configuration being accurate, which it isn't necessarily.
6739 */
6740
6741 return clock.dot;
6742}
6743
6744/** Returns the currently programmed mode of the given pipe. */
6745struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6746 struct drm_crtc *crtc)
6747{
548f245b 6748 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6749 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6750 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6751 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6752 int htot = I915_READ(HTOTAL(cpu_transcoder));
6753 int hsync = I915_READ(HSYNC(cpu_transcoder));
6754 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6755 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6756
6757 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6758 if (!mode)
6759 return NULL;
6760
6761 mode->clock = intel_crtc_clock_get(dev, crtc);
6762 mode->hdisplay = (htot & 0xffff) + 1;
6763 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6764 mode->hsync_start = (hsync & 0xffff) + 1;
6765 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6766 mode->vdisplay = (vtot & 0xffff) + 1;
6767 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6768 mode->vsync_start = (vsync & 0xffff) + 1;
6769 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6770
6771 drm_mode_set_name(mode);
79e53945
JB		 6772
6773 return mode;
6774}
6775
3dec0095 6776static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6777{
6778 struct drm_device *dev = crtc->dev;
6779 drm_i915_private_t *dev_priv = dev->dev_private;
6780 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6781 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6782 int dpll_reg = DPLL(pipe);
6783 int dpll;
652c393a 6784
bad720ff 6785 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6786 return;
6787
6788 if (!dev_priv->lvds_downclock_avail)
6789 return;
6790
dbdc6479 6791 dpll = I915_READ(dpll_reg);
652c393a 6792 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6793 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6794
8ac5a6d5 6795 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6796
6797 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6798 I915_WRITE(dpll_reg, dpll);
9d0498a2 6799 intel_wait_for_vblank(dev, pipe);
dbdc6479 6800
652c393a
JB		 6801 dpll = I915_READ(dpll_reg);
6802 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6803 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6804 }
652c393a
JB		 6805}
6806
6807static void intel_decrease_pllclock(struct drm_crtc *crtc)
6808{
6809 struct drm_device *dev = crtc->dev;
6810 drm_i915_private_t *dev_priv = dev->dev_private;
6811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6812
bad720ff 6813 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6814 return;
6815
6816 if (!dev_priv->lvds_downclock_avail)
6817 return;
6818
6819 /*
6820 * Since this is called by a timer, we should never get here in
6821 * the manual case.
6822 */
6823 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6824 int pipe = intel_crtc->pipe;
6825 int dpll_reg = DPLL(pipe);
6826 int dpll;
f6e5b160 6827
44d98a61 6828 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6829
8ac5a6d5 6830 assert_panel_unlocked(dev_priv, pipe);
652c393a 6831
dc257cf1 6832 dpll = I915_READ(dpll_reg);
652c393a
JB		 6833 dpll |= DISPLAY_RATE_SELECT_FPA1;
6834 I915_WRITE(dpll_reg, dpll);
9d0498a2 6835 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6836 dpll = I915_READ(dpll_reg);
6837 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6838 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6839 }
6840
6841}
6842
f047e395
CW		 6843void intel_mark_busy(struct drm_device *dev)
6844{
f047e395
CW		 6845 i915_update_gfx_val(dev->dev_private);
6846}
6847
6848void intel_mark_idle(struct drm_device *dev)
652c393a 6849{
f047e395
CW		 6850}
6851
6852void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6853{
6854 struct drm_device *dev = obj->base.dev;
652c393a 6855 struct drm_crtc *crtc;
652c393a
JB		 6856
6857 if (!i915_powersave)
6858 return;
6859
652c393a 6860 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6861 if (!crtc->fb)
6862 continue;
6863
f047e395
CW		 6864 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6865 intel_increase_pllclock(crtc);
652c393a 6866 }
652c393a
JB		 6867}
6868
f047e395 6869void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6870{
f047e395
CW		 6871 struct drm_device *dev = obj->base.dev;
6872 struct drm_crtc *crtc;
652c393a 6873
f047e395 6874 if (!i915_powersave)
acb87dfb
CW		 6875 return;
6876
652c393a
JB		 6877 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6878 if (!crtc->fb)
6879 continue;
6880
f047e395
CW		 6881 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6882 intel_decrease_pllclock(crtc);
652c393a
JB		 6883 }
6884}
6885
79e53945
JB		 6886static void intel_crtc_destroy(struct drm_crtc *crtc)
6887{
6888 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6889 struct drm_device *dev = crtc->dev;
6890 struct intel_unpin_work *work;
6891 unsigned long flags;
6892
6893 spin_lock_irqsave(&dev->event_lock, flags);
6894 work = intel_crtc->unpin_work;
6895 intel_crtc->unpin_work = NULL;
6896 spin_unlock_irqrestore(&dev->event_lock, flags);
6897
6898 if (work) {
6899 cancel_work_sync(&work->work);
6900 kfree(work);
6901 }
79e53945
JB		 6902
6903 drm_crtc_cleanup(crtc);
67e77c5a 6904
79e53945
JB		 6905 kfree(intel_crtc);
6906}
6907
6b95a207
KH		 6908static void intel_unpin_work_fn(struct work_struct *__work)
6909{
6910 struct intel_unpin_work *work =
6911 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6912 struct drm_device *dev = work->crtc->dev;
6b95a207 6913
b4a98e57 6914 mutex_lock(&dev->struct_mutex);
1690e1eb 6915 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6916 drm_gem_object_unreference(&work->pending_flip_obj->base);
6917 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6918
b4a98e57
CW		 6919 intel_update_fbc(dev);
6920 mutex_unlock(&dev->struct_mutex);
6921
6922 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6923 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6924
6b95a207
KH		 6925 kfree(work);
6926}
6927
1afe3e9d 6928static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6929 struct drm_crtc *crtc)
6b95a207
KH		 6930{
6931 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6933 struct intel_unpin_work *work;
05394f39 6934 struct drm_i915_gem_object *obj;
6b95a207
KH		 6935 unsigned long flags;
6936
6937 /* Ignore early vblank irqs */
6938 if (intel_crtc == NULL)
6939 return;
6940
6941 spin_lock_irqsave(&dev->event_lock, flags);
6942 work = intel_crtc->unpin_work;
6943 if (work == NULL || !work->pending) {
6944 spin_unlock_irqrestore(&dev->event_lock, flags);
6945 return;
6946 }
6947
6948 intel_crtc->unpin_work = NULL;
6b95a207 6949
45a066eb
RC		 6950 if (work->event)
6951 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 6952
0af7e4df
MK		 6953 drm_vblank_put(dev, intel_crtc->pipe);
6954
6b95a207
KH		 6955 spin_unlock_irqrestore(&dev->event_lock, flags);
6956
05394f39 6957 obj = work->old_fb_obj;
d9e86c0e 6958
5bb61643 6959 wake_up(&dev_priv->pending_flip_queue);
b4a98e57
CW		 6960
6961 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 6962
6963 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6964}
6965
1afe3e9d
JB		 6966void intel_finish_page_flip(struct drm_device *dev, int pipe)
6967{
6968 drm_i915_private_t *dev_priv = dev->dev_private;
6969 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6970
49b14a5c 6971 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6972}
6973
6974void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6975{
6976 drm_i915_private_t *dev_priv = dev->dev_private;
6977 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6978
49b14a5c 6979 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6980}
6981
6b95a207
KH		 6982void intel_prepare_page_flip(struct drm_device *dev, int plane)
6983{
6984 drm_i915_private_t *dev_priv = dev->dev_private;
6985 struct intel_crtc *intel_crtc =
6986 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6987 unsigned long flags;
6988
6989 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6990 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6991 if ((++intel_crtc->unpin_work->pending) > 1)
6992 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6993 } else {
6994 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6995 }
6b95a207
KH		 6996 spin_unlock_irqrestore(&dev->event_lock, flags);
6997}
6998
8c9f3aaf
JB		 6999static int intel_gen2_queue_flip(struct drm_device *dev,
7000 struct drm_crtc *crtc,
7001 struct drm_framebuffer *fb,
7002 struct drm_i915_gem_object *obj)
7003{
7004 struct drm_i915_private *dev_priv = dev->dev_private;
7005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7006 u32 flip_mask;
6d90c952 7007 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7008 int ret;
7009
6d90c952 7010 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7011 if (ret)
83d4092b 7012 goto err;
8c9f3aaf 7013
6d90c952 7014 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7015 if (ret)
83d4092b 7016 goto err_unpin;
8c9f3aaf
JB		 7017
7018 /* Can't queue multiple flips, so wait for the previous
7019 * one to finish before executing the next.
7020 */
7021 if (intel_crtc->plane)
7022 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7023 else
7024 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7025 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7026 intel_ring_emit(ring, MI_NOOP);
7027 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7028 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7029 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7030 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7031 intel_ring_emit(ring, 0); /* aux display base address, unused */
7032 intel_ring_advance(ring);
83d4092b
CW		 7033 return 0;
7034
7035err_unpin:
7036 intel_unpin_fb_obj(obj);
7037err:
8c9f3aaf
JB		 7038 return ret;
7039}
7040
7041static int intel_gen3_queue_flip(struct drm_device *dev,
7042 struct drm_crtc *crtc,
7043 struct drm_framebuffer *fb,
7044 struct drm_i915_gem_object *obj)
7045{
7046 struct drm_i915_private *dev_priv = dev->dev_private;
7047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7048 u32 flip_mask;
6d90c952 7049 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7050 int ret;
7051
6d90c952 7052 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7053 if (ret)
83d4092b 7054 goto err;
8c9f3aaf 7055
6d90c952 7056 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7057 if (ret)
83d4092b 7058 goto err_unpin;
8c9f3aaf
JB		 7059
7060 if (intel_crtc->plane)
7061 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7062 else
7063 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7064 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7065 intel_ring_emit(ring, MI_NOOP);
7066 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7067 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7068 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7069 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7070 intel_ring_emit(ring, MI_NOOP);
7071
7072 intel_ring_advance(ring);
83d4092b
CW		 7073 return 0;
7074
7075err_unpin:
7076 intel_unpin_fb_obj(obj);
7077err:
8c9f3aaf
JB		 7078 return ret;
7079}
7080
7081static int intel_gen4_queue_flip(struct drm_device *dev,
7082 struct drm_crtc *crtc,
7083 struct drm_framebuffer *fb,
7084 struct drm_i915_gem_object *obj)
7085{
7086 struct drm_i915_private *dev_priv = dev->dev_private;
7087 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7088 uint32_t pf, pipesrc;
6d90c952 7089 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7090 int ret;
7091
6d90c952 7092 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7093 if (ret)
83d4092b 7094 goto err;
8c9f3aaf 7095
6d90c952 7096 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7097 if (ret)
83d4092b 7098 goto err_unpin;
8c9f3aaf
JB		 7099
7100 /* i965+ uses the linear or tiled offsets from the
7101 * Display Registers (which do not change across a page-flip)
7102 * so we need only reprogram the base address.
7103 */
6d90c952
DV		 7104 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7105 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7106 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7107 intel_ring_emit(ring,
7108 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7109 obj->tiling_mode);
8c9f3aaf
JB		 7110
7111 /* XXX Enabling the panel-fitter across page-flip is so far
7112 * untested on non-native modes, so ignore it for now.
7113 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7114 */
7115 pf = 0;
7116 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7117 intel_ring_emit(ring, pf | pipesrc);
7118 intel_ring_advance(ring);
83d4092b
CW		 7119 return 0;
7120
7121err_unpin:
7122 intel_unpin_fb_obj(obj);
7123err:
8c9f3aaf
JB		 7124 return ret;
7125}
7126
7127static int intel_gen6_queue_flip(struct drm_device *dev,
7128 struct drm_crtc *crtc,
7129 struct drm_framebuffer *fb,
7130 struct drm_i915_gem_object *obj)
7131{
7132 struct drm_i915_private *dev_priv = dev->dev_private;
7133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7134 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7135 uint32_t pf, pipesrc;
7136 int ret;
7137
6d90c952 7138 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7139 if (ret)
83d4092b 7140 goto err;
8c9f3aaf 7141
6d90c952 7142 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7143 if (ret)
83d4092b 7144 goto err_unpin;
8c9f3aaf 7145
6d90c952
DV		 7146 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7147 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7148 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7149 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7150
dc257cf1
DV		 7151 /* Contrary to the suggestions in the documentation,
7152 * "Enable Panel Fitter" does not seem to be required when page
7153 * flipping with a non-native mode, and worse causes a normal
7154 * modeset to fail.
7155 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7156 */
7157 pf = 0;
8c9f3aaf 7158 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 7159 intel_ring_emit(ring, pf | pipesrc);
7160 intel_ring_advance(ring);
83d4092b
CW		 7161 return 0;
7162
7163err_unpin:
7164 intel_unpin_fb_obj(obj);
7165err:
8c9f3aaf
JB		 7166 return ret;
7167}
7168
7c9017e5
JB		 7169/*
7170 * On gen7 we currently use the blit ring because (in early silicon at least)
7171 * the render ring doesn't give us interrpts for page flip completion, which
7172 * means clients will hang after the first flip is queued. Fortunately the
7173 * blit ring generates interrupts properly, so use it instead.
7174 */
7175static int intel_gen7_queue_flip(struct drm_device *dev,
7176 struct drm_crtc *crtc,
7177 struct drm_framebuffer *fb,
7178 struct drm_i915_gem_object *obj)
7179{
7180 struct drm_i915_private *dev_priv = dev->dev_private;
7181 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7182 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7183 uint32_t plane_bit = 0;
7c9017e5
JB		 7184 int ret;
7185
7186 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7187 if (ret)
83d4092b 7188 goto err;
7c9017e5 7189
cb05d8de
DV		 7190 switch(intel_crtc->plane) {
7191 case PLANE_A:
7192 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7193 break;
7194 case PLANE_B:
7195 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7196 break;
7197 case PLANE_C:
7198 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7199 break;
7200 default:
7201 WARN_ONCE(1, "unknown plane in flip command\n");
7202 ret = -ENODEV;
ab3951eb 7203 goto err_unpin;
cb05d8de
DV		 7204 }
7205
7c9017e5
JB		 7206 ret = intel_ring_begin(ring, 4);
7207 if (ret)
83d4092b 7208 goto err_unpin;
7c9017e5 7209
cb05d8de 7210 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7211 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7212 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 7213 intel_ring_emit(ring, (MI_NOOP));
7214 intel_ring_advance(ring);
83d4092b
CW		 7215 return 0;
7216
7217err_unpin:
7218 intel_unpin_fb_obj(obj);
7219err:
7c9017e5
JB		 7220 return ret;
7221}
7222
8c9f3aaf
JB		 7223static int intel_default_queue_flip(struct drm_device *dev,
7224 struct drm_crtc *crtc,
7225 struct drm_framebuffer *fb,
7226 struct drm_i915_gem_object *obj)
7227{
7228 return -ENODEV;
7229}
7230
6b95a207
KH		 7231static int intel_crtc_page_flip(struct drm_crtc *crtc,
7232 struct drm_framebuffer *fb,
7233 struct drm_pending_vblank_event *event)
7234{
7235 struct drm_device *dev = crtc->dev;
7236 struct drm_i915_private *dev_priv = dev->dev_private;
7237 struct intel_framebuffer *intel_fb;
05394f39 7238 struct drm_i915_gem_object *obj;
6b95a207
KH		 7239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7240 struct intel_unpin_work *work;
8c9f3aaf 7241 unsigned long flags;
52e68630 7242 int ret;
6b95a207 7243
e6a595d2
VS		 7244 /* Can't change pixel format via MI display flips. */
7245 if (fb->pixel_format != crtc->fb->pixel_format)
7246 return -EINVAL;
7247
7248 /*
7249 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7250 * Note that pitch changes could also affect these register.
7251 */
7252 if (INTEL_INFO(dev)->gen > 3 &&
7253 (fb->offsets[0] != crtc->fb->offsets[0] ||
7254 fb->pitches[0] != crtc->fb->pitches[0]))
7255 return -EINVAL;
7256
6b95a207
KH		 7257 work = kzalloc(sizeof *work, GFP_KERNEL);
7258 if (work == NULL)
7259 return -ENOMEM;
7260
6b95a207 7261 work->event = event;
b4a98e57 7262 work->crtc = crtc;
6b95a207 7263 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7264 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7265 INIT_WORK(&work->work, intel_unpin_work_fn);
7266
7317c75e
JB		 7267 ret = drm_vblank_get(dev, intel_crtc->pipe);
7268 if (ret)
7269 goto free_work;
7270
6b95a207
KH		 7271 /* We borrow the event spin lock for protecting unpin_work */
7272 spin_lock_irqsave(&dev->event_lock, flags);
7273 if (intel_crtc->unpin_work) {
7274 spin_unlock_irqrestore(&dev->event_lock, flags);
7275 kfree(work);
7317c75e 7276 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7277
7278 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7279 return -EBUSY;
7280 }
7281 intel_crtc->unpin_work = work;
7282 spin_unlock_irqrestore(&dev->event_lock, flags);
7283
7284 intel_fb = to_intel_framebuffer(fb);
7285 obj = intel_fb->obj;
7286
b4a98e57
CW		 7287 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7288 flush_workqueue(dev_priv->wq);
7289
79158103
CW		 7290 ret = i915_mutex_lock_interruptible(dev);
7291 if (ret)
7292 goto cleanup;
6b95a207 7293
75dfca80 7294 /* Reference the objects for the scheduled work. */
05394f39
CW		 7295 drm_gem_object_reference(&work->old_fb_obj->base);
7296 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7297
7298 crtc->fb = fb;
96b099fd 7299
e1f99ce6 7300 work->pending_flip_obj = obj;
e1f99ce6 7301
4e5359cd
SF		 7302 work->enable_stall_check = true;
7303
b4a98e57 7304 atomic_inc(&intel_crtc->unpin_work_count);
e1f99ce6 7305
8c9f3aaf
JB		 7306 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7307 if (ret)
7308 goto cleanup_pending;
6b95a207 7309
7782de3b 7310 intel_disable_fbc(dev);
f047e395 7311 intel_mark_fb_busy(obj);
6b95a207
KH		 7312 mutex_unlock(&dev->struct_mutex);
7313
e5510fac
JB		 7314 trace_i915_flip_request(intel_crtc->plane, obj);
7315
6b95a207 7316 return 0;
96b099fd 7317
8c9f3aaf 7318cleanup_pending:
b4a98e57 7319 atomic_dec(&intel_crtc->unpin_work_count);
05394f39
CW		 7320 drm_gem_object_unreference(&work->old_fb_obj->base);
7321 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7322 mutex_unlock(&dev->struct_mutex);
7323
79158103 7324cleanup:
96b099fd
CW		 7325 spin_lock_irqsave(&dev->event_lock, flags);
7326 intel_crtc->unpin_work = NULL;
7327 spin_unlock_irqrestore(&dev->event_lock, flags);
7328
7317c75e
JB		 7329 drm_vblank_put(dev, intel_crtc->pipe);
7330free_work:
96b099fd
CW		 7331 kfree(work);
7332
7333 return ret;
6b95a207
KH		 7334}
7335
f6e5b160 7336static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7337 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7338 .load_lut = intel_crtc_load_lut,
976f8a20 7339 .disable = intel_crtc_noop,
f6e5b160
CW		 7340};
7341
6ed0f796 7342bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7343{
6ed0f796
DV		 7344 struct intel_encoder *other_encoder;
7345 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7346
6ed0f796
DV		 7347 if (WARN_ON(!crtc))
7348 return false;
7349
7350 list_for_each_entry(other_encoder,
7351 &crtc->dev->mode_config.encoder_list,
7352 base.head) {
7353
7354 if (&other_encoder->new_crtc->base != crtc ||
7355 encoder == other_encoder)
7356 continue;
7357 else
7358 return true;
f47166d2
CW		 7359 }
7360
6ed0f796
DV		 7361 return false;
7362}
47f1c6c9 7363
50f56119
DV		 7364static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7365 struct drm_crtc *crtc)
7366{
7367 struct drm_device *dev;
7368 struct drm_crtc *tmp;
7369 int crtc_mask = 1;
47f1c6c9 7370
50f56119 7371 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7372
50f56119 7373 dev = crtc->dev;
47f1c6c9 7374
50f56119
DV		 7375 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7376 if (tmp == crtc)
7377 break;
7378 crtc_mask <<= 1;
7379 }
47f1c6c9 7380
50f56119
DV		 7381 if (encoder->possible_crtcs & crtc_mask)
7382 return true;
7383 return false;
47f1c6c9 7384}
79e53945 7385
9a935856
DV		 7386/**
7387 * intel_modeset_update_staged_output_state
7388 *
7389 * Updates the staged output configuration state, e.g. after we've read out the
7390 * current hw state.
7391 */
7392static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7393{
9a935856
DV		 7394 struct intel_encoder *encoder;
7395 struct intel_connector *connector;
f6e5b160 7396
9a935856
DV		 7397 list_for_each_entry(connector, &dev->mode_config.connector_list,
7398 base.head) {
7399 connector->new_encoder =
7400 to_intel_encoder(connector->base.encoder);
7401 }
f6e5b160 7402
9a935856
DV		 7403 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7404 base.head) {
7405 encoder->new_crtc =
7406 to_intel_crtc(encoder->base.crtc);
7407 }
f6e5b160
CW		 7408}
7409
9a935856
DV		 7410/**
7411 * intel_modeset_commit_output_state
7412 *
7413 * This function copies the stage display pipe configuration to the real one.
7414 */
7415static void intel_modeset_commit_output_state(struct drm_device *dev)
7416{
7417 struct intel_encoder *encoder;
7418 struct intel_connector *connector;
f6e5b160 7419
9a935856
DV		 7420 list_for_each_entry(connector, &dev->mode_config.connector_list,
7421 base.head) {
7422 connector->base.encoder = &connector->new_encoder->base;
7423 }
f6e5b160 7424
9a935856
DV		 7425 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7426 base.head) {
7427 encoder->base.crtc = &encoder->new_crtc->base;
7428 }
7429}
7430
7758a113
DV		 7431static struct drm_display_mode *
7432intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7433 struct drm_display_mode *mode)
ee7b9f93 7434{
7758a113
DV		 7435 struct drm_device *dev = crtc->dev;
7436 struct drm_display_mode *adjusted_mode;
7437 struct drm_encoder_helper_funcs *encoder_funcs;
7438 struct intel_encoder *encoder;
ee7b9f93 7439
7758a113
DV		 7440 adjusted_mode = drm_mode_duplicate(dev, mode);
7441 if (!adjusted_mode)
7442 return ERR_PTR(-ENOMEM);
7443
7444 /* Pass our mode to the connectors and the CRTC to give them a chance to
7445 * adjust it according to limitations or connector properties, and also
7446 * a chance to reject the mode entirely.
47f1c6c9 7447 */
7758a113
DV		 7448 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7449 base.head) {
47f1c6c9 7450
7758a113
DV		 7451 if (&encoder->new_crtc->base != crtc)
7452 continue;
7453 encoder_funcs = encoder->base.helper_private;
7454 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7455 adjusted_mode))) {
7456 DRM_DEBUG_KMS("Encoder fixup failed\n");
7457 goto fail;
7458 }
ee7b9f93 7459 }
47f1c6c9 7460
7758a113
DV		 7461 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7462 DRM_DEBUG_KMS("CRTC fixup failed\n");
7463 goto fail;
ee7b9f93 7464 }
7758a113 7465 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7466
7758a113
DV		 7467 return adjusted_mode;
7468fail:
7469 drm_mode_destroy(dev, adjusted_mode);
7470 return ERR_PTR(-EINVAL);
ee7b9f93 7471}
47f1c6c9 7472
e2e1ed41
DV		 7473/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7474 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7475static void
7476intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7477 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7478{
7479 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7480 struct drm_device *dev = crtc->dev;
7481 struct intel_encoder *encoder;
7482 struct intel_connector *connector;
7483 struct drm_crtc *tmp_crtc;
79e53945 7484
e2e1ed41 7485 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7486
e2e1ed41
DV		 7487 /* Check which crtcs have changed outputs connected to them, these need
7488 * to be part of the prepare_pipes mask. We don't (yet) support global
7489 * modeset across multiple crtcs, so modeset_pipes will only have one
7490 * bit set at most. */
7491 list_for_each_entry(connector, &dev->mode_config.connector_list,
7492 base.head) {
7493 if (connector->base.encoder == &connector->new_encoder->base)
7494 continue;
79e53945 7495
e2e1ed41
DV		 7496 if (connector->base.encoder) {
7497 tmp_crtc = connector->base.encoder->crtc;
7498
7499 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7500 }
7501
7502 if (connector->new_encoder)
7503 *prepare_pipes |=
7504 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7505 }
7506
e2e1ed41
DV		 7507 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7508 base.head) {
7509 if (encoder->base.crtc == &encoder->new_crtc->base)
7510 continue;
7511
7512 if (encoder->base.crtc) {
7513 tmp_crtc = encoder->base.crtc;
7514
7515 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7516 }
7517
7518 if (encoder->new_crtc)
7519 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7520 }
7521
e2e1ed41
DV		 7522 /* Check for any pipes that will be fully disabled ... */
7523 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7524 base.head) {
7525 bool used = false;
22fd0fab 7526
e2e1ed41
DV		 7527 /* Don't try to disable disabled crtcs. */
7528 if (!intel_crtc->base.enabled)
7529 continue;
7e7d76c3 7530
e2e1ed41
DV		 7531 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7532 base.head) {
7533 if (encoder->new_crtc == intel_crtc)
7534 used = true;
7535 }
7536
7537 if (!used)
7538 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7539 }
7540
e2e1ed41
DV		 7541
7542 /* set_mode is also used to update properties on life display pipes. */
7543 intel_crtc = to_intel_crtc(crtc);
7544 if (crtc->enabled)
7545 *prepare_pipes |= 1 << intel_crtc->pipe;
7546
7547 /* We only support modeset on one single crtc, hence we need to do that
7548 * only for the passed in crtc iff we change anything else than just
7549 * disable crtcs.
7550 *
7551 * This is actually not true, to be fully compatible with the old crtc
7552 * helper we automatically disable _any_ output (i.e. doesn't need to be
7553 * connected to the crtc we're modesetting on) if it's disconnected.
7554 * Which is a rather nutty api (since changed the output configuration
7555 * without userspace's explicit request can lead to confusion), but
7556 * alas. Hence we currently need to modeset on all pipes we prepare. */
7557 if (*prepare_pipes)
7558 *modeset_pipes = *prepare_pipes;
7559
7560 /* ... and mask these out. */
7561 *modeset_pipes &= ~(*disable_pipes);
7562 *prepare_pipes &= ~(*disable_pipes);
47f1c6c9 7563}
79e53945 7564
ea9d758d 7565static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7566{
ea9d758d 7567 struct drm_encoder *encoder;
f6e5b160 7568 struct drm_device *dev = crtc->dev;
f6e5b160 7569
ea9d758d
DV		 7570 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7571 if (encoder->crtc == crtc)
7572 return true;
7573
7574 return false;
7575}
7576
7577static void
7578intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7579{
7580 struct intel_encoder *intel_encoder;
7581 struct intel_crtc *intel_crtc;
7582 struct drm_connector *connector;
7583
7584 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7585 base.head) {
7586 if (!intel_encoder->base.crtc)
7587 continue;
7588
7589 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7590
7591 if (prepare_pipes & (1 << intel_crtc->pipe))
7592 intel_encoder->connectors_active = false;
7593 }
7594
7595 intel_modeset_commit_output_state(dev);
7596
7597 /* Update computed state. */
7598 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7599 base.head) {
7600 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7601 }
7602
7603 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7604 if (!connector->encoder || !connector->encoder->crtc)
7605 continue;
7606
7607 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7608
7609 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7610 struct drm_property *dpms_property =
7611 dev->mode_config.dpms_property;
7612
ea9d758d 7613 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7614 drm_object_property_set_value(&connector->base,
68d34720
DV		 7615 dpms_property,
7616 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7617
7618 intel_encoder = to_intel_encoder(connector->encoder);
7619 intel_encoder->connectors_active = true;
7620 }
7621 }
7622
7623}
7624
25c5b266
DV		 7625#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7626 list_for_each_entry((intel_crtc), \
7627 &(dev)->mode_config.crtc_list, \
7628 base.head) \
7629 if (mask & (1 <<(intel_crtc)->pipe)) \
7630
b980514c 7631void
8af6cf88
DV		 7632intel_modeset_check_state(struct drm_device *dev)
7633{
7634 struct intel_crtc *crtc;
7635 struct intel_encoder *encoder;
7636 struct intel_connector *connector;
7637
7638 list_for_each_entry(connector, &dev->mode_config.connector_list,
7639 base.head) {
7640 /* This also checks the encoder/connector hw state with the
7641 * ->get_hw_state callbacks. */
7642 intel_connector_check_state(connector);
7643
7644 WARN(&connector->new_encoder->base != connector->base.encoder,
7645 "connector's staged encoder doesn't match current encoder\n");
7646 }
7647
7648 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7649 base.head) {
7650 bool enabled = false;
7651 bool active = false;
7652 enum pipe pipe, tracked_pipe;
7653
7654 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7655 encoder->base.base.id,
7656 drm_get_encoder_name(&encoder->base));
7657
7658 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7659 "encoder's stage crtc doesn't match current crtc\n");
7660 WARN(encoder->connectors_active && !encoder->base.crtc,
7661 "encoder's active_connectors set, but no crtc\n");
7662
7663 list_for_each_entry(connector, &dev->mode_config.connector_list,
7664 base.head) {
7665 if (connector->base.encoder != &encoder->base)
7666 continue;
7667 enabled = true;
7668 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7669 active = true;
7670 }
7671 WARN(!!encoder->base.crtc != enabled,
7672 "encoder's enabled state mismatch "
7673 "(expected %i, found %i)\n",
7674 !!encoder->base.crtc, enabled);
7675 WARN(active && !encoder->base.crtc,
7676 "active encoder with no crtc\n");
7677
7678 WARN(encoder->connectors_active != active,
7679 "encoder's computed active state doesn't match tracked active state "
7680 "(expected %i, found %i)\n", active, encoder->connectors_active);
7681
7682 active = encoder->get_hw_state(encoder, &pipe);
7683 WARN(active != encoder->connectors_active,
7684 "encoder's hw state doesn't match sw tracking "
7685 "(expected %i, found %i)\n",
7686 encoder->connectors_active, active);
7687
7688 if (!encoder->base.crtc)
7689 continue;
7690
7691 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7692 WARN(active && pipe != tracked_pipe,
7693 "active encoder's pipe doesn't match"
7694 "(expected %i, found %i)\n",
7695 tracked_pipe, pipe);
7696
7697 }
7698
7699 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7700 base.head) {
7701 bool enabled = false;
7702 bool active = false;
7703
7704 DRM_DEBUG_KMS("[CRTC:%d]\n",
7705 crtc->base.base.id);
7706
7707 WARN(crtc->active && !crtc->base.enabled,
7708 "active crtc, but not enabled in sw tracking\n");
7709
7710 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7711 base.head) {
7712 if (encoder->base.crtc != &crtc->base)
7713 continue;
7714 enabled = true;
7715 if (encoder->connectors_active)
7716 active = true;
7717 }
7718 WARN(active != crtc->active,
7719 "crtc's computed active state doesn't match tracked active state "
7720 "(expected %i, found %i)\n", active, crtc->active);
7721 WARN(enabled != crtc->base.enabled,
7722 "crtc's computed enabled state doesn't match tracked enabled state "
7723 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7724
7725 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7726 }
7727}
7728
a6778b3c
DV		 7729bool intel_set_mode(struct drm_crtc *crtc,
7730 struct drm_display_mode *mode,
94352cf9 7731 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7732{
7733 struct drm_device *dev = crtc->dev;
dbf2b54e 7734 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 7735 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
25c5b266
DV		 7736 struct intel_crtc *intel_crtc;
7737 unsigned disable_pipes, prepare_pipes, modeset_pipes;
a6778b3c
DV		 7738 bool ret = true;
7739
e2e1ed41 7740 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7741 &prepare_pipes, &disable_pipes);
7742
7743 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7744 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7745
976f8a20
DV		 7746 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7747 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7748
a6778b3c
DV		 7749 saved_hwmode = crtc->hwmode;
7750 saved_mode = crtc->mode;
a6778b3c 7751
25c5b266
DV		 7752 /* Hack: Because we don't (yet) support global modeset on multiple
7753 * crtcs, we don't keep track of the new mode for more than one crtc.
7754 * Hence simply check whether any bit is set in modeset_pipes in all the
7755 * pieces of code that are not yet converted to deal with mutliple crtcs
7756 * changing their mode at the same time. */
7757 adjusted_mode = NULL;
7758 if (modeset_pipes) {
7759 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7760 if (IS_ERR(adjusted_mode)) {
7761 return false;
7762 }
25c5b266 7763 }
a6778b3c 7764
ea9d758d
DV		 7765 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7766 if (intel_crtc->base.enabled)
7767 dev_priv->display.crtc_disable(&intel_crtc->base);
7768 }
a6778b3c 7769
6c4c86f5
DV		 7770 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7771 * to set it here already despite that we pass it down the callchain.
f6e5b160 7772 */
6c4c86f5 7773 if (modeset_pipes)
25c5b266 7774 crtc->mode = *mode;
7758a113 7775
ea9d758d
DV		 7776 /* Only after disabling all output pipelines that will be changed can we
7777 * update the the output configuration. */
7778 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 7779
47fab737
DV		 7780 if (dev_priv->display.modeset_global_resources)
7781 dev_priv->display.modeset_global_resources(dev);
7782
a6778b3c
DV		 7783 /* Set up the DPLL and any encoders state that needs to adjust or depend
7784 * on the DPLL.
f6e5b160 7785 */
25c5b266
DV		 7786 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7787 ret = !intel_crtc_mode_set(&intel_crtc->base,
7788 mode, adjusted_mode,
7789 x, y, fb);
7790 if (!ret)
7791 goto done;
a6778b3c
DV		 7792 }
7793
7794 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7795 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7796 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7797
25c5b266
DV		 7798 if (modeset_pipes) {
7799 /* Store real post-adjustment hardware mode. */
7800 crtc->hwmode = *adjusted_mode;
a6778b3c 7801
25c5b266
DV		 7802 /* Calculate and store various constants which
7803 * are later needed by vblank and swap-completion
7804 * timestamping. They are derived from true hwmode.
7805 */
7806 drm_calc_timestamping_constants(crtc);
7807 }
a6778b3c
DV		 7808
7809 /* FIXME: add subpixel order */
7810done:
7811 drm_mode_destroy(dev, adjusted_mode);
25c5b266 7812 if (!ret && crtc->enabled) {
a6778b3c
DV		 7813 crtc->hwmode = saved_hwmode;
7814 crtc->mode = saved_mode;
8af6cf88
DV		 7815 } else {
7816 intel_modeset_check_state(dev);
a6778b3c
DV		 7817 }
7818
7819 return ret;
f6e5b160
CW		 7820}
7821
25c5b266
DV		 7822#undef for_each_intel_crtc_masked
7823
d9e55608
DV		 7824static void intel_set_config_free(struct intel_set_config *config)
7825{
7826 if (!config)
7827 return;
7828
1aa4b628
DV		 7829 kfree(config->save_connector_encoders);
7830 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7831 kfree(config);
7832}
7833
85f9eb71
DV		 7834static int intel_set_config_save_state(struct drm_device *dev,
7835 struct intel_set_config *config)
7836{
85f9eb71
DV		 7837 struct drm_encoder *encoder;
7838 struct drm_connector *connector;
7839 int count;
7840
1aa4b628
DV		 7841 config->save_encoder_crtcs =
7842 kcalloc(dev->mode_config.num_encoder,
7843 sizeof(struct drm_crtc *), GFP_KERNEL);
7844 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7845 return -ENOMEM;
7846
1aa4b628
DV		 7847 config->save_connector_encoders =
7848 kcalloc(dev->mode_config.num_connector,
7849 sizeof(struct drm_encoder *), GFP_KERNEL);
7850 if (!config->save_connector_encoders)
85f9eb71
DV		 7851 return -ENOMEM;
7852
7853 /* Copy data. Note that driver private data is not affected.
7854 * Should anything bad happen only the expected state is
7855 * restored, not the drivers personal bookkeeping.
7856 */
85f9eb71
DV		 7857 count = 0;
7858 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7859 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7860 }
7861
7862 count = 0;
7863 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7864 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7865 }
7866
7867 return 0;
7868}
7869
7870static void intel_set_config_restore_state(struct drm_device *dev,
7871 struct intel_set_config *config)
7872{
9a935856
DV		 7873 struct intel_encoder *encoder;
7874 struct intel_connector *connector;
85f9eb71
DV		 7875 int count;
7876
85f9eb71 7877 count = 0;
9a935856
DV		 7878 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7879 encoder->new_crtc =
7880 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7881 }
7882
7883 count = 0;
9a935856
DV		 7884 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7885 connector->new_encoder =
7886 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7887 }
7888}
7889
5e2b584e
DV		 7890static void
7891intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7892 struct intel_set_config *config)
7893{
7894
7895 /* We should be able to check here if the fb has the same properties
7896 * and then just flip_or_move it */
7897 if (set->crtc->fb != set->fb) {
7898 /* If we have no fb then treat it as a full mode set */
7899 if (set->crtc->fb == NULL) {
7900 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7901 config->mode_changed = true;
7902 } else if (set->fb == NULL) {
7903 config->mode_changed = true;
7904 } else if (set->fb->depth != set->crtc->fb->depth) {
7905 config->mode_changed = true;
7906 } else if (set->fb->bits_per_pixel !=
7907 set->crtc->fb->bits_per_pixel) {
7908 config->mode_changed = true;
7909 } else
7910 config->fb_changed = true;
7911 }
7912
835c5873 7913 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7914 config->fb_changed = true;
7915
7916 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7917 DRM_DEBUG_KMS("modes are different, full mode set\n");
7918 drm_mode_debug_printmodeline(&set->crtc->mode);
7919 drm_mode_debug_printmodeline(set->mode);
7920 config->mode_changed = true;
7921 }
7922}
7923
2e431051 7924static int
9a935856
DV		 7925intel_modeset_stage_output_state(struct drm_device *dev,
7926 struct drm_mode_set *set,
7927 struct intel_set_config *config)
50f56119 7928{
85f9eb71 7929 struct drm_crtc *new_crtc;
9a935856
DV		 7930 struct intel_connector *connector;
7931 struct intel_encoder *encoder;
2e431051 7932 int count, ro;
50f56119 7933
9a935856
DV		 7934 /* The upper layers ensure that we either disabl a crtc or have a list
7935 * of connectors. For paranoia, double-check this. */
7936 WARN_ON(!set->fb && (set->num_connectors != 0));
7937 WARN_ON(set->fb && (set->num_connectors == 0));
7938
50f56119 7939 count = 0;
9a935856
DV		 7940 list_for_each_entry(connector, &dev->mode_config.connector_list,
7941 base.head) {
7942 /* Otherwise traverse passed in connector list and get encoders
7943 * for them. */
50f56119 7944 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7945 if (set->connectors[ro] == &connector->base) {
7946 connector->new_encoder = connector->encoder;
50f56119
DV		 7947 break;
7948 }
7949 }
7950
9a935856
DV		 7951 /* If we disable the crtc, disable all its connectors. Also, if
7952 * the connector is on the changing crtc but not on the new
7953 * connector list, disable it. */
7954 if ((!set->fb || ro == set->num_connectors) &&
7955 connector->base.encoder &&
7956 connector->base.encoder->crtc == set->crtc) {
7957 connector->new_encoder = NULL;
7958
7959 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7960 connector->base.base.id,
7961 drm_get_connector_name(&connector->base));
7962 }
7963
7964
7965 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7966 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7967 config->mode_changed = true;
50f56119 7968 }
9a935856
DV		 7969
7970 /* Disable all disconnected encoders. */
7971 if (connector->base.status == connector_status_disconnected)
7972 connector->new_encoder = NULL;
50f56119 7973 }
9a935856 7974 /* connector->new_encoder is now updated for all connectors. */
50f56119 7975
9a935856 7976 /* Update crtc of enabled connectors. */
50f56119 7977 count = 0;
9a935856
DV		 7978 list_for_each_entry(connector, &dev->mode_config.connector_list,
7979 base.head) {
7980 if (!connector->new_encoder)
50f56119
DV		 7981 continue;
7982
9a935856 7983 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 7984
7985 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7986 if (set->connectors[ro] == &connector->base)
50f56119
DV		 7987 new_crtc = set->crtc;
7988 }
7989
7990 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 7991 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7992 new_crtc)) {
5e2b584e 7993 return -EINVAL;
50f56119 7994 }
9a935856
DV		 7995 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7996
7997 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7998 connector->base.base.id,
7999 drm_get_connector_name(&connector->base),
8000 new_crtc->base.id);
8001 }
8002
8003 /* Check for any encoders that needs to be disabled. */
8004 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8005 base.head) {
8006 list_for_each_entry(connector,
8007 &dev->mode_config.connector_list,
8008 base.head) {
8009 if (connector->new_encoder == encoder) {
8010 WARN_ON(!connector->new_encoder->new_crtc);
8011
8012 goto next_encoder;
8013 }
8014 }
8015 encoder->new_crtc = NULL;
8016next_encoder:
8017 /* Only now check for crtc changes so we don't miss encoders
8018 * that will be disabled. */
8019 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8020 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8021 config->mode_changed = true;
50f56119
DV		 8022 }
8023 }
9a935856 8024 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8025
2e431051
DV		 8026 return 0;
8027}
8028
8029static int intel_crtc_set_config(struct drm_mode_set *set)
8030{
8031 struct drm_device *dev;
2e431051
DV		 8032 struct drm_mode_set save_set;
8033 struct intel_set_config *config;
8034 int ret;
2e431051 8035
8d3e375e
DV		 8036 BUG_ON(!set);
8037 BUG_ON(!set->crtc);
8038 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 8039
8040 if (!set->mode)
8041 set->fb = NULL;
8042
431e50f7
DV		 8043 /* The fb helper likes to play gross jokes with ->mode_set_config.
8044 * Unfortunately the crtc helper doesn't do much at all for this case,
8045 * so we have to cope with this madness until the fb helper is fixed up. */
8046 if (set->fb && set->num_connectors == 0)
8047 return 0;
8048
2e431051
DV		 8049 if (set->fb) {
8050 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8051 set->crtc->base.id, set->fb->base.id,
8052 (int)set->num_connectors, set->x, set->y);
8053 } else {
8054 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8055 }
8056
8057 dev = set->crtc->dev;
8058
8059 ret = -ENOMEM;
8060 config = kzalloc(sizeof(*config), GFP_KERNEL);
8061 if (!config)
8062 goto out_config;
8063
8064 ret = intel_set_config_save_state(dev, config);
8065 if (ret)
8066 goto out_config;
8067
8068 save_set.crtc = set->crtc;
8069 save_set.mode = &set->crtc->mode;
8070 save_set.x = set->crtc->x;
8071 save_set.y = set->crtc->y;
8072 save_set.fb = set->crtc->fb;
8073
8074 /* Compute whether we need a full modeset, only an fb base update or no
8075 * change at all. In the future we might also check whether only the
8076 * mode changed, e.g. for LVDS where we only change the panel fitter in
8077 * such cases. */
8078 intel_set_config_compute_mode_changes(set, config);
8079
9a935856 8080 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8081 if (ret)
8082 goto fail;
8083
5e2b584e 8084 if (config->mode_changed) {
87f1faa6 8085 if (set->mode) {
50f56119
DV		 8086 DRM_DEBUG_KMS("attempting to set mode from"
8087 " userspace\n");
8088 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8089 }
8090
8091 if (!intel_set_mode(set->crtc, set->mode,
8092 set->x, set->y, set->fb)) {
8093 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
8094 set->crtc->base.id);
8095 ret = -EINVAL;
8096 goto fail;
8097 }
5e2b584e 8098 } else if (config->fb_changed) {
4f660f49 8099 ret = intel_pipe_set_base(set->crtc,
94352cf9 8100 set->x, set->y, set->fb);
50f56119
DV		 8101 }
8102
d9e55608
DV		 8103 intel_set_config_free(config);
8104
50f56119
DV		 8105 return 0;
8106
8107fail:
85f9eb71 8108 intel_set_config_restore_state(dev, config);
50f56119
DV		 8109
8110 /* Try to restore the config */
5e2b584e 8111 if (config->mode_changed &&
a6778b3c
DV		 8112 !intel_set_mode(save_set.crtc, save_set.mode,
8113 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8114 DRM_ERROR("failed to restore config after modeset failure\n");
8115
d9e55608
DV		 8116out_config:
8117 intel_set_config_free(config);
50f56119
DV		 8118 return ret;
8119}
f6e5b160
CW		 8120
8121static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8122 .cursor_set = intel_crtc_cursor_set,
8123 .cursor_move = intel_crtc_cursor_move,
8124 .gamma_set = intel_crtc_gamma_set,
50f56119 8125 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8126 .destroy = intel_crtc_destroy,
8127 .page_flip = intel_crtc_page_flip,
8128};
8129
79f689aa
PZ		 8130static void intel_cpu_pll_init(struct drm_device *dev)
8131{
8132 if (IS_HASWELL(dev))
8133 intel_ddi_pll_init(dev);
8134}
8135
ee7b9f93
JB		 8136static void intel_pch_pll_init(struct drm_device *dev)
8137{
8138 drm_i915_private_t *dev_priv = dev->dev_private;
8139 int i;
8140
8141 if (dev_priv->num_pch_pll == 0) {
8142 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8143 return;
8144 }
8145
8146 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8147 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8148 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8149 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8150 }
8151}
8152
b358d0a6 8153static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8154{
22fd0fab 8155 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8156 struct intel_crtc *intel_crtc;
8157 int i;
8158
8159 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8160 if (intel_crtc == NULL)
8161 return;
8162
8163 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8164
8165 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8166 for (i = 0; i < 256; i++) {
8167 intel_crtc->lut_r[i] = i;
8168 intel_crtc->lut_g[i] = i;
8169 intel_crtc->lut_b[i] = i;
8170 }
8171
80824003
JB		 8172 /* Swap pipes & planes for FBC on pre-965 */
8173 intel_crtc->pipe = pipe;
8174 intel_crtc->plane = pipe;
a5c961d1 8175 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8176 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8177 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8178 intel_crtc->plane = !pipe;
80824003
JB		 8179 }
8180
22fd0fab
JB		 8181 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8182 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8183 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8184 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8185
5a354204 8186 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8187
79e53945 8188 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8189}
8190
08d7b3d1 8191int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8192 struct drm_file *file)
08d7b3d1 8193{
08d7b3d1 8194 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8195 struct drm_mode_object *drmmode_obj;
8196 struct intel_crtc *crtc;
08d7b3d1 8197
1cff8f6b
DV		 8198 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8199 return -ENODEV;
08d7b3d1 8200
c05422d5
DV		 8201 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8202 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8203
c05422d5 8204 if (!drmmode_obj) {
08d7b3d1
CW		 8205 DRM_ERROR("no such CRTC id\n");
8206 return -EINVAL;
8207 }
8208
c05422d5
DV		 8209 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8210 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8211
c05422d5 8212 return 0;
08d7b3d1
CW		 8213}
8214
66a9278e 8215static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8216{
66a9278e
DV		 8217 struct drm_device *dev = encoder->base.dev;
8218 struct intel_encoder *source_encoder;
79e53945 8219 int index_mask = 0;
79e53945
JB		 8220 int entry = 0;
8221
66a9278e
DV		 8222 list_for_each_entry(source_encoder,
8223 &dev->mode_config.encoder_list, base.head) {
8224
8225 if (encoder == source_encoder)
79e53945 8226 index_mask |= (1 << entry);
66a9278e
DV		 8227
8228 /* Intel hw has only one MUX where enocoders could be cloned. */
8229 if (encoder->cloneable && source_encoder->cloneable)
8230 index_mask |= (1 << entry);
8231
79e53945
JB		 8232 entry++;
8233 }
4ef69c7a 8234
79e53945
JB		 8235 return index_mask;
8236}
8237
4d302442
CW		 8238static bool has_edp_a(struct drm_device *dev)
8239{
8240 struct drm_i915_private *dev_priv = dev->dev_private;
8241
8242 if (!IS_MOBILE(dev))
8243 return false;
8244
8245 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8246 return false;
8247
8248 if (IS_GEN5(dev) &&
8249 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8250 return false;
8251
8252 return true;
8253}
8254
79e53945
JB		 8255static void intel_setup_outputs(struct drm_device *dev)
8256{
725e30ad 8257 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8258 struct intel_encoder *encoder;
cb0953d7 8259 bool dpd_is_edp = false;
f3cfcba6 8260 bool has_lvds;
79e53945 8261
f3cfcba6 8262 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8263 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8264 /* disable the panel fitter on everything but LVDS */
8265 I915_WRITE(PFIT_CONTROL, 0);
8266 }
79e53945 8267
79935fca
PZ		 8268 if (!(IS_HASWELL(dev) &&
8269 (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8270 intel_crt_init(dev);
cb0953d7 8271
0e72a5b5
ED		 8272 if (IS_HASWELL(dev)) {
8273 int found;
8274
8275 /* Haswell uses DDI functions to detect digital outputs */
8276 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8277 /* DDI A only supports eDP */
8278 if (found)
8279 intel_ddi_init(dev, PORT_A);
8280
8281 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8282 * register */
8283 found = I915_READ(SFUSE_STRAP);
8284
8285 if (found & SFUSE_STRAP_DDIB_DETECTED)
8286 intel_ddi_init(dev, PORT_B);
8287 if (found & SFUSE_STRAP_DDIC_DETECTED)
8288 intel_ddi_init(dev, PORT_C);
8289 if (found & SFUSE_STRAP_DDID_DETECTED)
8290 intel_ddi_init(dev, PORT_D);
8291 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8292 int found;
270b3042
DV		 8293 dpd_is_edp = intel_dpd_is_edp(dev);
8294
8295 if (has_edp_a(dev))
8296 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8297
30ad48b7 8298 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8299 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8300 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8301 if (!found)
08d644ad 8302 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8303 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8304 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8305 }
8306
8307 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8308 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8309
b708a1d5 8310 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8311 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8312
5eb08b69 8313 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8314 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8315
270b3042 8316 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8317 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 8318 } else if (IS_VALLEYVIEW(dev)) {
8319 int found;
8320
19c03924
GB		 8321 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8322 if (I915_READ(DP_C) & DP_DETECTED)
8323 intel_dp_init(dev, DP_C, PORT_C);
8324
4a87d65d
JB		 8325 if (I915_READ(SDVOB) & PORT_DETECTED) {
8326 /* SDVOB multiplex with HDMIB */
8327 found = intel_sdvo_init(dev, SDVOB, true);
8328 if (!found)
08d644ad 8329 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 8330 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 8331 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 8332 }
8333
8334 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 8335 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 8336
103a196f 8337 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8338 bool found = false;
7d57382e 8339
725e30ad 8340 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8341 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8342 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8343 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8344 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8345 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8346 }
27185ae1 8347
b01f2c3a
JB		 8348 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8349 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8350 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8351 }
725e30ad 8352 }
13520b05
KH		 8353
8354 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8355
b01f2c3a
JB		 8356 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8357 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8358 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8359 }
27185ae1
ML		 8360
8361 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8362
b01f2c3a
JB		 8363 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8364 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8365 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8366 }
8367 if (SUPPORTS_INTEGRATED_DP(dev)) {
8368 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8369 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8370 }
725e30ad 8371 }
27185ae1 8372
b01f2c3a
JB		 8373 if (SUPPORTS_INTEGRATED_DP(dev) &&
8374 (I915_READ(DP_D) & DP_DETECTED)) {
8375 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8376 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8377 }
bad720ff 8378 } else if (IS_GEN2(dev))
79e53945
JB		 8379 intel_dvo_init(dev);
8380
103a196f 8381 if (SUPPORTS_TV(dev))
79e53945
JB		 8382 intel_tv_init(dev);
8383
4ef69c7a
CW		 8384 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8385 encoder->base.possible_crtcs = encoder->crtc_mask;
8386 encoder->base.possible_clones =
66a9278e 8387 intel_encoder_clones(encoder);
79e53945 8388 }
47356eb6 8389
40579abe 8390 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 8391 ironlake_init_pch_refclk(dev);
270b3042
DV		 8392
8393 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8394}
8395
8396static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8397{
8398 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8399
8400 drm_framebuffer_cleanup(fb);
05394f39 8401 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8402
8403 kfree(intel_fb);
8404}
8405
8406static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8407 struct drm_file *file,
79e53945
JB		 8408 unsigned int *handle)
8409{
8410 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8411 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8412
05394f39 8413 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8414}
8415
8416static const struct drm_framebuffer_funcs intel_fb_funcs = {
8417 .destroy = intel_user_framebuffer_destroy,
8418 .create_handle = intel_user_framebuffer_create_handle,
8419};
8420
38651674
DA		 8421int intel_framebuffer_init(struct drm_device *dev,
8422 struct intel_framebuffer *intel_fb,
308e5bcb 8423 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8424 struct drm_i915_gem_object *obj)
79e53945 8425{
79e53945
JB		 8426 int ret;
8427
05394f39 8428 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 8429 return -EINVAL;
8430
308e5bcb 8431 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 8432 return -EINVAL;
8433
5d7bd705
VS		 8434 /* FIXME <= Gen4 stride limits are bit unclear */
8435 if (mode_cmd->pitches[0] > 32768)
8436 return -EINVAL;
8437
8438 if (obj->tiling_mode != I915_TILING_NONE &&
8439 mode_cmd->pitches[0] != obj->stride)
8440 return -EINVAL;
8441
57779d06 8442 /* Reject formats not supported by any plane early. */
308e5bcb 8443 switch (mode_cmd->pixel_format) {
57779d06 8444 case DRM_FORMAT_C8:
04b3924d
VS		 8445 case DRM_FORMAT_RGB565:
8446 case DRM_FORMAT_XRGB8888:
8447 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8448 break;
8449 case DRM_FORMAT_XRGB1555:
8450 case DRM_FORMAT_ARGB1555:
8451 if (INTEL_INFO(dev)->gen > 3)
8452 return -EINVAL;
8453 break;
8454 case DRM_FORMAT_XBGR8888:
8455 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8456 case DRM_FORMAT_XRGB2101010:
8457 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8458 case DRM_FORMAT_XBGR2101010:
8459 case DRM_FORMAT_ABGR2101010:
8460 if (INTEL_INFO(dev)->gen < 4)
8461 return -EINVAL;
b5626747 8462 break;
04b3924d
VS		 8463 case DRM_FORMAT_YUYV:
8464 case DRM_FORMAT_UYVY:
8465 case DRM_FORMAT_YVYU:
8466 case DRM_FORMAT_VYUY:
57779d06
VS		 8467 if (INTEL_INFO(dev)->gen < 6)
8468 return -EINVAL;
57cd6508
CW		 8469 break;
8470 default:
57779d06 8471 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8472 return -EINVAL;
8473 }
8474
90f9a336
VS		 8475 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8476 if (mode_cmd->offsets[0] != 0)
8477 return -EINVAL;
8478
79e53945
JB		 8479 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8480 if (ret) {
8481 DRM_ERROR("framebuffer init failed %d\n", ret);
8482 return ret;
8483 }
8484
8485 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 8486 intel_fb->obj = obj;
79e53945
JB		 8487 return 0;
8488}
8489
79e53945
JB		 8490static struct drm_framebuffer *
8491intel_user_framebuffer_create(struct drm_device *dev,
8492 struct drm_file *filp,
308e5bcb 8493 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8494{
05394f39 8495 struct drm_i915_gem_object *obj;
79e53945 8496
308e5bcb
JB		 8497 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8498 mode_cmd->handles[0]));
c8725226 8499 if (&obj->base == NULL)
cce13ff7 8500 return ERR_PTR(-ENOENT);
79e53945 8501
d2dff872 8502 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8503}
8504
79e53945 8505static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8506 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8507 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8508};
8509
e70236a8
JB		 8510/* Set up chip specific display functions */
8511static void intel_init_display(struct drm_device *dev)
8512{
8513 struct drm_i915_private *dev_priv = dev->dev_private;
8514
8515 /* We always want a DPMS function */
09b4ddf9
PZ		 8516 if (IS_HASWELL(dev)) {
8517 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8518 dev_priv->display.crtc_enable = haswell_crtc_enable;
8519 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8520 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8521 dev_priv->display.update_plane = ironlake_update_plane;
8522 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8523 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8524 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8525 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8526 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8527 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8528 } else {
f564048e 8529 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8530 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8531 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8532 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8533 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8534 }
e70236a8 8535
e70236a8 8536 /* Returns the core display clock speed */
25eb05fc
JB		 8537 if (IS_VALLEYVIEW(dev))
8538 dev_priv->display.get_display_clock_speed =
8539 valleyview_get_display_clock_speed;
8540 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8541 dev_priv->display.get_display_clock_speed =
8542 i945_get_display_clock_speed;
8543 else if (IS_I915G(dev))
8544 dev_priv->display.get_display_clock_speed =
8545 i915_get_display_clock_speed;
f2b115e6 8546 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8547 dev_priv->display.get_display_clock_speed =
8548 i9xx_misc_get_display_clock_speed;
8549 else if (IS_I915GM(dev))
8550 dev_priv->display.get_display_clock_speed =
8551 i915gm_get_display_clock_speed;
8552 else if (IS_I865G(dev))
8553 dev_priv->display.get_display_clock_speed =
8554 i865_get_display_clock_speed;
f0f8a9ce 8555 else if (IS_I85X(dev))
e70236a8
JB		 8556 dev_priv->display.get_display_clock_speed =
8557 i855_get_display_clock_speed;
8558 else /* 852, 830 */
8559 dev_priv->display.get_display_clock_speed =
8560 i830_get_display_clock_speed;
8561
7f8a8569 8562 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8563 if (IS_GEN5(dev)) {
674cf967 8564 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8565 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8566 } else if (IS_GEN6(dev)) {
674cf967 8567 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8568 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8569 } else if (IS_IVYBRIDGE(dev)) {
8570 /* FIXME: detect B0+ stepping and use auto training */
8571 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8572 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8573 dev_priv->display.modeset_global_resources =
8574 ivb_modeset_global_resources;
c82e4d26
ED		 8575 } else if (IS_HASWELL(dev)) {
8576 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8577 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 8578 } else
8579 dev_priv->display.update_wm = NULL;
6067aaea 8580 } else if (IS_G4X(dev)) {
e0dac65e 8581 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8582 }
8c9f3aaf
JB		 8583
8584 /* Default just returns -ENODEV to indicate unsupported */
8585 dev_priv->display.queue_flip = intel_default_queue_flip;
8586
8587 switch (INTEL_INFO(dev)->gen) {
8588 case 2:
8589 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8590 break;
8591
8592 case 3:
8593 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8594 break;
8595
8596 case 4:
8597 case 5:
8598 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8599 break;
8600
8601 case 6:
8602 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8603 break;
7c9017e5
JB		 8604 case 7:
8605 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8606 break;
8c9f3aaf 8607 }
e70236a8
JB		 8608}
8609
b690e96c
JB		 8610/*
8611 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8612 * resume, or other times. This quirk makes sure that's the case for
8613 * affected systems.
8614 */
0206e353 8615static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8616{
8617 struct drm_i915_private *dev_priv = dev->dev_private;
8618
8619 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8620 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8621}
8622
435793df
KP		 8623/*
8624 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8625 */
8626static void quirk_ssc_force_disable(struct drm_device *dev)
8627{
8628 struct drm_i915_private *dev_priv = dev->dev_private;
8629 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8630 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8631}
8632
4dca20ef 8633/*
5a15ab5b
CE		 8634 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8635 * brightness value
4dca20ef
CE		 8636 */
8637static void quirk_invert_brightness(struct drm_device *dev)
8638{
8639 struct drm_i915_private *dev_priv = dev->dev_private;
8640 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8641 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8642}
8643
b690e96c
JB		 8644struct intel_quirk {
8645 int device;
8646 int subsystem_vendor;
8647 int subsystem_device;
8648 void (*hook)(struct drm_device *dev);
8649};
8650
5f85f176
EE		 8651/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8652struct intel_dmi_quirk {
8653 void (*hook)(struct drm_device *dev);
8654 const struct dmi_system_id (*dmi_id_list)[];
8655};
8656
8657static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8658{
8659 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8660 return 1;
8661}
8662
8663static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8664 {
8665 .dmi_id_list = &(const struct dmi_system_id[]) {
8666 {
8667 .callback = intel_dmi_reverse_brightness,
8668 .ident = "NCR Corporation",
8669 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8670 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8671 },
8672 },
8673 { } /* terminating entry */
8674 },
8675 .hook = quirk_invert_brightness,
8676 },
8677};
8678
c43b5634 8679static struct intel_quirk intel_quirks[] = {
b690e96c 8680 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8681 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8682
b690e96c
JB		 8683 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8684 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8685
b690e96c
JB		 8686 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8687 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8688
ccd0d36e 8689 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8690 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8691 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8692
8693 /* Lenovo U160 cannot use SSC on LVDS */
8694 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8695
8696 /* Sony Vaio Y cannot use SSC on LVDS */
8697 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8698
8699 /* Acer Aspire 5734Z must invert backlight brightness */
8700 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 8701};
8702
8703static void intel_init_quirks(struct drm_device *dev)
8704{
8705 struct pci_dev *d = dev->pdev;
8706 int i;
8707
8708 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8709 struct intel_quirk *q = &intel_quirks[i];
8710
8711 if (d->device == q->device &&
8712 (d->subsystem_vendor == q->subsystem_vendor ||
8713 q->subsystem_vendor == PCI_ANY_ID) &&
8714 (d->subsystem_device == q->subsystem_device ||
8715 q->subsystem_device == PCI_ANY_ID))
8716 q->hook(dev);
8717 }
5f85f176
EE		 8718 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8719 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8720 intel_dmi_quirks[i].hook(dev);
8721 }
b690e96c
JB		 8722}
8723
9cce37f4
JB		 8724/* Disable the VGA plane that we never use */
8725static void i915_disable_vga(struct drm_device *dev)
8726{
8727 struct drm_i915_private *dev_priv = dev->dev_private;
8728 u8 sr1;
8729 u32 vga_reg;
8730
8731 if (HAS_PCH_SPLIT(dev))
8732 vga_reg = CPU_VGACNTRL;
8733 else
8734 vga_reg = VGACNTRL;
8735
8736 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8737 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8738 sr1 = inb(VGA_SR_DATA);
8739 outb(sr1 | 1<<5, VGA_SR_DATA);
8740 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8741 udelay(300);
8742
8743 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8744 POSTING_READ(vga_reg);
8745}
8746
f817586c
DV		 8747void intel_modeset_init_hw(struct drm_device *dev)
8748{
0232e927
ED		 8749 /* We attempt to init the necessary power wells early in the initialization
8750 * time, so the subsystems that expect power to be enabled can work.
8751 */
8752 intel_init_power_wells(dev);
8753
a8f78b58
ED		 8754 intel_prepare_ddi(dev);
8755
f817586c
DV		 8756 intel_init_clock_gating(dev);
8757
79f5b2c7 8758 mutex_lock(&dev->struct_mutex);
8090c6b9 8759 intel_enable_gt_powersave(dev);
79f5b2c7 8760 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8761}
8762
79e53945
JB		 8763void intel_modeset_init(struct drm_device *dev)
8764{
652c393a 8765 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8766 int i, ret;
79e53945
JB		 8767
8768 drm_mode_config_init(dev);
8769
8770 dev->mode_config.min_width = 0;
8771 dev->mode_config.min_height = 0;
8772
019d96cb
DA		 8773 dev->mode_config.preferred_depth = 24;
8774 dev->mode_config.prefer_shadow = 1;
8775
e6ecefaa 8776 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8777
b690e96c
JB		 8778 intel_init_quirks(dev);
8779
1fa61106
ED		 8780 intel_init_pm(dev);
8781
e70236a8
JB		 8782 intel_init_display(dev);
8783
a6c45cf0
CW		 8784 if (IS_GEN2(dev)) {
8785 dev->mode_config.max_width = 2048;
8786 dev->mode_config.max_height = 2048;
8787 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8788 dev->mode_config.max_width = 4096;
8789 dev->mode_config.max_height = 4096;
79e53945 8790 } else {
a6c45cf0
CW		 8791 dev->mode_config.max_width = 8192;
8792 dev->mode_config.max_height = 8192;
79e53945 8793 }
dd2757f8 8794 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 8795
28c97730 8796 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8797 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8798
a3524f1b 8799 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8800 intel_crtc_init(dev, i);
00c2064b
JB		 8801 ret = intel_plane_init(dev, i);
8802 if (ret)
8803 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8804 }
8805
79f689aa 8806 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8807 intel_pch_pll_init(dev);
8808
9cce37f4
JB		 8809 /* Just disable it once at startup */
8810 i915_disable_vga(dev);
79e53945 8811 intel_setup_outputs(dev);
2c7111db
CW		 8812}
8813
24929352
DV		 8814static void
8815intel_connector_break_all_links(struct intel_connector *connector)
8816{
8817 connector->base.dpms = DRM_MODE_DPMS_OFF;
8818 connector->base.encoder = NULL;
8819 connector->encoder->connectors_active = false;
8820 connector->encoder->base.crtc = NULL;
8821}
8822
7fad798e
DV		 8823static void intel_enable_pipe_a(struct drm_device *dev)
8824{
8825 struct intel_connector *connector;
8826 struct drm_connector *crt = NULL;
8827 struct intel_load_detect_pipe load_detect_temp;
8828
8829 /* We can't just switch on the pipe A, we need to set things up with a
8830 * proper mode and output configuration. As a gross hack, enable pipe A
8831 * by enabling the load detect pipe once. */
8832 list_for_each_entry(connector,
8833 &dev->mode_config.connector_list,
8834 base.head) {
8835 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8836 crt = &connector->base;
8837 break;
8838 }
8839 }
8840
8841 if (!crt)
8842 return;
8843
8844 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8845 intel_release_load_detect_pipe(crt, &load_detect_temp);
8846
652c393a 8847
7fad798e
DV		 8848}
8849
fa555837
DV		 8850static bool
8851intel_check_plane_mapping(struct intel_crtc *crtc)
8852{
8853 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8854 u32 reg, val;
8855
8856 if (dev_priv->num_pipe == 1)
8857 return true;
8858
8859 reg = DSPCNTR(!crtc->plane);
8860 val = I915_READ(reg);
8861
8862 if ((val & DISPLAY_PLANE_ENABLE) &&
8863 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8864 return false;
8865
8866 return true;
8867}
8868
24929352
DV		 8869static void intel_sanitize_crtc(struct intel_crtc *crtc)
8870{
8871 struct drm_device *dev = crtc->base.dev;
8872 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8873 u32 reg;
24929352 8874
24929352 8875 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8876 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8877 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8878
8879 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8880 * disable the crtc (and hence change the state) if it is wrong. Note
8881 * that gen4+ has a fixed plane -> pipe mapping. */
8882 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8883 struct intel_connector *connector;
8884 bool plane;
8885
24929352
DV		 8886 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8887 crtc->base.base.id);
8888
8889 /* Pipe has the wrong plane attached and the plane is active.
8890 * Temporarily change the plane mapping and disable everything
8891 * ... */
8892 plane = crtc->plane;
8893 crtc->plane = !plane;
8894 dev_priv->display.crtc_disable(&crtc->base);
8895 crtc->plane = plane;
8896
8897 /* ... and break all links. */
8898 list_for_each_entry(connector, &dev->mode_config.connector_list,
8899 base.head) {
8900 if (connector->encoder->base.crtc != &crtc->base)
8901 continue;
8902
8903 intel_connector_break_all_links(connector);
8904 }
8905
8906 WARN_ON(crtc->active);
8907 crtc->base.enabled = false;
8908 }
24929352 8909
7fad798e
DV		 8910 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8911 crtc->pipe == PIPE_A && !crtc->active) {
8912 /* BIOS forgot to enable pipe A, this mostly happens after
8913 * resume. Force-enable the pipe to fix this, the update_dpms
8914 * call below we restore the pipe to the right state, but leave
8915 * the required bits on. */
8916 intel_enable_pipe_a(dev);
8917 }
8918
24929352
DV		 8919 /* Adjust the state of the output pipe according to whether we
8920 * have active connectors/encoders. */
8921 intel_crtc_update_dpms(&crtc->base);
8922
8923 if (crtc->active != crtc->base.enabled) {
8924 struct intel_encoder *encoder;
8925
8926 /* This can happen either due to bugs in the get_hw_state
8927 * functions or because the pipe is force-enabled due to the
8928 * pipe A quirk. */
8929 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8930 crtc->base.base.id,
8931 crtc->base.enabled ? "enabled" : "disabled",
8932 crtc->active ? "enabled" : "disabled");
8933
8934 crtc->base.enabled = crtc->active;
8935
8936 /* Because we only establish the connector -> encoder ->
8937 * crtc links if something is active, this means the
8938 * crtc is now deactivated. Break the links. connector
8939 * -> encoder links are only establish when things are
8940 * actually up, hence no need to break them. */
8941 WARN_ON(crtc->active);
8942
8943 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8944 WARN_ON(encoder->connectors_active);
8945 encoder->base.crtc = NULL;
8946 }
8947 }
8948}
8949
8950static void intel_sanitize_encoder(struct intel_encoder *encoder)
8951{
8952 struct intel_connector *connector;
8953 struct drm_device *dev = encoder->base.dev;
8954
8955 /* We need to check both for a crtc link (meaning that the
8956 * encoder is active and trying to read from a pipe) and the
8957 * pipe itself being active. */
8958 bool has_active_crtc = encoder->base.crtc &&
8959 to_intel_crtc(encoder->base.crtc)->active;
8960
8961 if (encoder->connectors_active && !has_active_crtc) {
8962 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8963 encoder->base.base.id,
8964 drm_get_encoder_name(&encoder->base));
8965
8966 /* Connector is active, but has no active pipe. This is
8967 * fallout from our resume register restoring. Disable
8968 * the encoder manually again. */
8969 if (encoder->base.crtc) {
8970 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8971 encoder->base.base.id,
8972 drm_get_encoder_name(&encoder->base));
8973 encoder->disable(encoder);
8974 }
8975
8976 /* Inconsistent output/port/pipe state happens presumably due to
8977 * a bug in one of the get_hw_state functions. Or someplace else
8978 * in our code, like the register restore mess on resume. Clamp
8979 * things to off as a safer default. */
8980 list_for_each_entry(connector,
8981 &dev->mode_config.connector_list,
8982 base.head) {
8983 if (connector->encoder != encoder)
8984 continue;
8985
8986 intel_connector_break_all_links(connector);
8987 }
8988 }
8989 /* Enabled encoders without active connectors will be fixed in
8990 * the crtc fixup. */
8991}
8992
8993/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8994 * and i915 state tracking structures. */
45e2b5f6
DV		 8995void intel_modeset_setup_hw_state(struct drm_device *dev,
8996 bool force_restore)
24929352
DV		 8997{
8998 struct drm_i915_private *dev_priv = dev->dev_private;
8999 enum pipe pipe;
9000 u32 tmp;
9001 struct intel_crtc *crtc;
9002 struct intel_encoder *encoder;
9003 struct intel_connector *connector;
9004
e28d54cb
PZ		 9005 if (IS_HASWELL(dev)) {
9006 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9007
9008 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9009 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9010 case TRANS_DDI_EDP_INPUT_A_ON:
9011 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9012 pipe = PIPE_A;
9013 break;
9014 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9015 pipe = PIPE_B;
9016 break;
9017 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9018 pipe = PIPE_C;
9019 break;
9020 }
9021
9022 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9023 crtc->cpu_transcoder = TRANSCODER_EDP;
9024
9025 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
9026 pipe_name(pipe));
9027 }
9028 }
9029
24929352
DV		 9030 for_each_pipe(pipe) {
9031 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9032
702e7a56 9033 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 9034 if (tmp & PIPECONF_ENABLE)
9035 crtc->active = true;
9036 else
9037 crtc->active = false;
9038
9039 crtc->base.enabled = crtc->active;
9040
9041 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9042 crtc->base.base.id,
9043 crtc->active ? "enabled" : "disabled");
9044 }
9045
6441ab5f
PZ		 9046 if (IS_HASWELL(dev))
9047 intel_ddi_setup_hw_pll_state(dev);
9048
24929352
DV		 9049 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9050 base.head) {
9051 pipe = 0;
9052
9053 if (encoder->get_hw_state(encoder, &pipe)) {
9054 encoder->base.crtc =
9055 dev_priv->pipe_to_crtc_mapping[pipe];
9056 } else {
9057 encoder->base.crtc = NULL;
9058 }
9059
9060 encoder->connectors_active = false;
9061 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9062 encoder->base.base.id,
9063 drm_get_encoder_name(&encoder->base),
9064 encoder->base.crtc ? "enabled" : "disabled",
9065 pipe);
9066 }
9067
9068 list_for_each_entry(connector, &dev->mode_config.connector_list,
9069 base.head) {
9070 if (connector->get_hw_state(connector)) {
9071 connector->base.dpms = DRM_MODE_DPMS_ON;
9072 connector->encoder->connectors_active = true;
9073 connector->base.encoder = &connector->encoder->base;
9074 } else {
9075 connector->base.dpms = DRM_MODE_DPMS_OFF;
9076 connector->base.encoder = NULL;
9077 }
9078 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9079 connector->base.base.id,
9080 drm_get_connector_name(&connector->base),
9081 connector->base.encoder ? "enabled" : "disabled");
9082 }
9083
9084 /* HW state is read out, now we need to sanitize this mess. */
9085 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9086 base.head) {
9087 intel_sanitize_encoder(encoder);
9088 }
9089
9090 for_each_pipe(pipe) {
9091 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9092 intel_sanitize_crtc(crtc);
9093 }
9a935856 9094
45e2b5f6
DV		 9095 if (force_restore) {
9096 for_each_pipe(pipe) {
9097 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9098 intel_set_mode(&crtc->base, &crtc->base.mode,
9099 crtc->base.x, crtc->base.y, crtc->base.fb);
9100 }
9101 } else {
9102 intel_modeset_update_staged_output_state(dev);
9103 }
8af6cf88
DV		 9104
9105 intel_modeset_check_state(dev);
2e938892
DV		 9106
9107 drm_mode_config_reset(dev);
2c7111db
CW		 9108}
9109
9110void intel_modeset_gem_init(struct drm_device *dev)
9111{
1833b134 9112 intel_modeset_init_hw(dev);
02e792fb
DV		 9113
9114 intel_setup_overlay(dev);
24929352 9115
45e2b5f6 9116 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9117}
9118
9119void intel_modeset_cleanup(struct drm_device *dev)
9120{
652c393a
JB		 9121 struct drm_i915_private *dev_priv = dev->dev_private;
9122 struct drm_crtc *crtc;
9123 struct intel_crtc *intel_crtc;
9124
f87ea761 9125 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9126 mutex_lock(&dev->struct_mutex);
9127
723bfd70
JB		 9128 intel_unregister_dsm_handler();
9129
9130
652c393a
JB		 9131 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9132 /* Skip inactive CRTCs */
9133 if (!crtc->fb)
9134 continue;
9135
9136 intel_crtc = to_intel_crtc(crtc);
3dec0095 9137 intel_increase_pllclock(crtc);
652c393a
JB		 9138 }
9139
973d04f9 9140 intel_disable_fbc(dev);
e70236a8 9141
8090c6b9 9142 intel_disable_gt_powersave(dev);
0cdab21f 9143
930ebb46
DV		 9144 ironlake_teardown_rc6(dev);
9145
57f350b6
JB		 9146 if (IS_VALLEYVIEW(dev))
9147 vlv_init_dpio(dev);
9148
69341a5e
KH		 9149 mutex_unlock(&dev->struct_mutex);
9150
6c0d9350
DV		 9151 /* Disable the irq before mode object teardown, for the irq might
9152 * enqueue unpin/hotplug work. */
9153 drm_irq_uninstall(dev);
9154 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9155 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9156
1630fe75
CW		 9157 /* flush any delayed tasks or pending work */
9158 flush_scheduled_work();
9159
79e53945
JB		 9160 drm_mode_config_cleanup(dev);
9161}
9162
f1c79df3
ZW		 9163/*
9164 * Return which encoder is currently attached for connector.
9165 */
df0e9248 9166struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9167{
df0e9248
CW		 9168 return &intel_attached_encoder(connector)->base;
9169}
f1c79df3 9170
df0e9248
CW		 9171void intel_connector_attach_encoder(struct intel_connector *connector,
9172 struct intel_encoder *encoder)
9173{
9174 connector->encoder = encoder;
9175 drm_mode_connector_attach_encoder(&connector->base,
9176 &encoder->base);
79e53945 9177}
28d52043
DA		 9178
9179/*
9180 * set vga decode state - true == enable VGA decode
9181 */
9182int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9183{
9184 struct drm_i915_private *dev_priv = dev->dev_private;
9185 u16 gmch_ctrl;
9186
9187 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9188 if (state)
9189 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9190 else
9191 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9192 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9193 return 0;
9194}
c4a1d9e4
CW		 9195
9196#ifdef CONFIG_DEBUG_FS
9197#include <linux/seq_file.h>
9198
9199struct intel_display_error_state {
9200 struct intel_cursor_error_state {
9201 u32 control;
9202 u32 position;
9203 u32 base;
9204 u32 size;
52331309 9205 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9206
9207 struct intel_pipe_error_state {
9208 u32 conf;
9209 u32 source;
9210
9211 u32 htotal;
9212 u32 hblank;
9213 u32 hsync;
9214 u32 vtotal;
9215 u32 vblank;
9216 u32 vsync;
52331309 9217 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9218
9219 struct intel_plane_error_state {
9220 u32 control;
9221 u32 stride;
9222 u32 size;
9223 u32 pos;
9224 u32 addr;
9225 u32 surface;
9226 u32 tile_offset;
52331309 9227 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9228};
9229
9230struct intel_display_error_state *
9231intel_display_capture_error_state(struct drm_device *dev)
9232{
0206e353 9233 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9234 struct intel_display_error_state *error;
702e7a56 9235 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9236 int i;
9237
9238 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9239 if (error == NULL)
9240 return NULL;
9241
52331309 9242 for_each_pipe(i) {
702e7a56
PZ		 9243 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9244
c4a1d9e4
CW		 9245 error->cursor[i].control = I915_READ(CURCNTR(i));
9246 error->cursor[i].position = I915_READ(CURPOS(i));
9247 error->cursor[i].base = I915_READ(CURBASE(i));
9248
9249 error->plane[i].control = I915_READ(DSPCNTR(i));
9250 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9251 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9252 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9253 error->plane[i].addr = I915_READ(DSPADDR(i));
9254 if (INTEL_INFO(dev)->gen >= 4) {
9255 error->plane[i].surface = I915_READ(DSPSURF(i));
9256 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9257 }
9258
702e7a56 9259 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9260 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9261 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9262 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9263 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9264 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9265 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9266 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9267 }
9268
9269 return error;
9270}
9271
9272void
9273intel_display_print_error_state(struct seq_file *m,
9274 struct drm_device *dev,
9275 struct intel_display_error_state *error)
9276{
52331309 9277 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9278 int i;
9279
52331309
DL		 9280 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9281 for_each_pipe(i) {
c4a1d9e4
CW		 9282 seq_printf(m, "Pipe [%d]:\n", i);
9283 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9284 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9285 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9286 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9287 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9288 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9289 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9290 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9291
9292 seq_printf(m, "Plane [%d]:\n", i);
9293 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9294 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9295 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9296 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9297 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9298 if (INTEL_INFO(dev)->gen >= 4) {
9299 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9300 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9301 }
9302
9303 seq_printf(m, "Cursor [%d]:\n", i);
9304 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9305 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9306 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9307 }
9308}
9309#endif
Linux kernel - Deliverables
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