projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Split i915_gem_flush_ring() into seperate invalidate/flush funcs
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
d4906093
ML		 87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
79e53945 91
a4fc5ed6
KP		 92static bool
93intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
5eb08b69 96static bool
f2b115e6 97intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
a4fc5ed6 100
a0c4da24
JB		 101static bool
102intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103 int target, int refclk, intel_clock_t *match_clock,
104 intel_clock_t *best_clock);
105
021357ac
CW		 106static inline u32 /* units of 100MHz */
107intel_fdi_link_freq(struct drm_device *dev)
108{
8b99e68c
CW		 109 if (IS_GEN5(dev)) {
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
112 } else
113 return 27;
021357ac
CW		 114}
115
e4b36699 116static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 117 .dot = { .min = 25000, .max = 350000 },
118 .vco = { .min = 930000, .max = 1400000 },
119 .n = { .min = 3, .max = 16 },
120 .m = { .min = 96, .max = 140 },
121 .m1 = { .min = 18, .max = 26 },
122 .m2 = { .min = 6, .max = 16 },
123 .p = { .min = 4, .max = 128 },
124 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 125 .p2 = { .dot_limit = 165000,
126 .p2_slow = 4, .p2_fast = 2 },
d4906093 127 .find_pll = intel_find_best_PLL,
e4b36699
KP		 128};
129
130static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 131 .dot = { .min = 25000, .max = 350000 },
132 .vco = { .min = 930000, .max = 1400000 },
133 .n = { .min = 3, .max = 16 },
134 .m = { .min = 96, .max = 140 },
135 .m1 = { .min = 18, .max = 26 },
136 .m2 = { .min = 6, .max = 16 },
137 .p = { .min = 4, .max = 128 },
138 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 139 .p2 = { .dot_limit = 165000,
140 .p2_slow = 14, .p2_fast = 7 },
d4906093 141 .find_pll = intel_find_best_PLL,
e4b36699 142};
273e27ca 143
e4b36699 144static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 10, .max = 22 },
150 .m2 = { .min = 5, .max = 9 },
151 .p = { .min = 5, .max = 80 },
152 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 153 .p2 = { .dot_limit = 200000,
154 .p2_slow = 10, .p2_fast = 5 },
d4906093 155 .find_pll = intel_find_best_PLL,
e4b36699
KP		 156};
157
158static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 10, .max = 22 },
164 .m2 = { .min = 5, .max = 9 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
d4906093 169 .find_pll = intel_find_best_PLL,
e4b36699
KP		 170};
171
273e27ca 172
e4b36699 173static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 174 .dot = { .min = 25000, .max = 270000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 10, .max = 30 },
181 .p1 = { .min = 1, .max = 3},
182 .p2 = { .dot_limit = 270000,
183 .p2_slow = 10,
184 .p2_fast = 10
044c7c41 185 },
d4906093 186 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 187};
188
189static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 190 .dot = { .min = 22000, .max = 400000 },
191 .vco = { .min = 1750000, .max = 3500000},
192 .n = { .min = 1, .max = 4 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 16, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8},
198 .p2 = { .dot_limit = 165000,
199 .p2_slow = 10, .p2_fast = 5 },
d4906093 200 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 201};
202
203static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 204 .dot = { .min = 20000, .max = 115000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 28, .max = 112 },
211 .p1 = { .min = 2, .max = 8 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 14, .p2_fast = 14
044c7c41 214 },
d4906093 215 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 216};
217
218static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 219 .dot = { .min = 80000, .max = 224000 },
220 .vco = { .min = 1750000, .max = 3500000 },
221 .n = { .min = 1, .max = 3 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 14, .max = 42 },
226 .p1 = { .min = 2, .max = 6 },
227 .p2 = { .dot_limit = 0,
228 .p2_slow = 7, .p2_fast = 7
044c7c41 229 },
d4906093 230 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 231};
232
233static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 234 .dot = { .min = 161670, .max = 227000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 2 },
237 .m = { .min = 97, .max = 108 },
238 .m1 = { .min = 0x10, .max = 0x12 },
239 .m2 = { .min = 0x05, .max = 0x06 },
240 .p = { .min = 10, .max = 20 },
241 .p1 = { .min = 1, .max = 2},
242 .p2 = { .dot_limit = 0,
273e27ca 243 .p2_slow = 10, .p2_fast = 10 },
0206e353 244 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 245};
246
f2b115e6 247static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 248 .dot = { .min = 20000, .max = 400000},
249 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 250 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 251 .n = { .min = 3, .max = 6 },
252 .m = { .min = 2, .max = 256 },
273e27ca 253 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 254 .m1 = { .min = 0, .max = 0 },
255 .m2 = { .min = 0, .max = 254 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 258 .p2 = { .dot_limit = 200000,
259 .p2_slow = 10, .p2_fast = 5 },
6115707b 260 .find_pll = intel_find_best_PLL,
e4b36699
KP		 261};
262
f2b115e6 263static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1700000, .max = 3500000 },
266 .n = { .min = 3, .max = 6 },
267 .m = { .min = 2, .max = 256 },
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 7, .max = 112 },
271 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 272 .p2 = { .dot_limit = 112000,
273 .p2_slow = 14, .p2_fast = 14 },
6115707b 274 .find_pll = intel_find_best_PLL,
e4b36699
KP		 275};
276
273e27ca
EA		 277/* Ironlake / Sandybridge
278 *
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
281 */
b91ad0ec 282static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 5 },
286 .m = { .min = 79, .max = 127 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 10, .p2_fast = 5 },
4547668a 293 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 294};
295
b91ad0ec 296static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 297 .dot = { .min = 25000, .max = 350000 },
298 .vco = { .min = 1760000, .max = 3510000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 79, .max = 118 },
301 .m1 = { .min = 12, .max = 22 },
302 .m2 = { .min = 5, .max = 9 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 225000,
306 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 307 .find_pll = intel_g4x_find_best_PLL,
308};
309
310static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 14, .max = 56 },
318 .p1 = { .min = 2, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 321 .find_pll = intel_g4x_find_best_PLL,
322};
323
273e27ca 324/* LVDS 100mhz refclk limits. */
b91ad0ec 325static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 2 },
329 .m = { .min = 79, .max = 126 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
0206e353 333 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 336 .find_pll = intel_g4x_find_best_PLL,
337};
338
339static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 126 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 42 },
0206e353 347 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 350 .find_pll = intel_g4x_find_best_PLL,
351};
352
353static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000},
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 81, .max = 90 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 10, .max = 20 },
361 .p1 = { .min = 1, .max = 2},
362 .p2 = { .dot_limit = 0,
273e27ca 363 .p2_slow = 10, .p2_fast = 10 },
0206e353 364 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 365};
366
a0c4da24
JB		 367static const intel_limit_t intel_limits_vlv_dac = {
368 .dot = { .min = 25000, .max = 270000 },
369 .vco = { .min = 4000000, .max = 6000000 },
370 .n = { .min = 1, .max = 7 },
371 .m = { .min = 22, .max = 450 }, /* guess */
372 .m1 = { .min = 2, .max = 3 },
373 .m2 = { .min = 11, .max = 156 },
374 .p = { .min = 10, .max = 30 },
375 .p1 = { .min = 2, .max = 3 },
376 .p2 = { .dot_limit = 270000,
377 .p2_slow = 2, .p2_fast = 20 },
378 .find_pll = intel_vlv_find_best_pll,
379};
380
381static const intel_limit_t intel_limits_vlv_hdmi = {
382 .dot = { .min = 20000, .max = 165000 },
383 .vco = { .min = 5994000, .max = 4000000 },
384 .n = { .min = 1, .max = 7 },
385 .m = { .min = 60, .max = 300 }, /* guess */
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p = { .min = 10, .max = 30 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .dot_limit = 270000,
391 .p2_slow = 2, .p2_fast = 20 },
392 .find_pll = intel_vlv_find_best_pll,
393};
394
395static const intel_limit_t intel_limits_vlv_dp = {
396 .dot = { .min = 162000, .max = 270000 },
397 .vco = { .min = 5994000, .max = 4000000 },
398 .n = { .min = 1, .max = 7 },
399 .m = { .min = 60, .max = 300 }, /* guess */
400 .m1 = { .min = 2, .max = 3 },
401 .m2 = { .min = 11, .max = 156 },
402 .p = { .min = 10, .max = 30 },
403 .p1 = { .min = 2, .max = 3 },
404 .p2 = { .dot_limit = 270000,
405 .p2_slow = 2, .p2_fast = 20 },
406 .find_pll = intel_vlv_find_best_pll,
407};
408
57f350b6
JB		 409u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
410{
411 unsigned long flags;
412 u32 val = 0;
413
414 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
417 goto out_unlock;
418 }
419
420 I915_WRITE(DPIO_REG, reg);
421 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
422 DPIO_BYTE);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
425 goto out_unlock;
426 }
427 val = I915_READ(DPIO_DATA);
428
429out_unlock:
430 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
431 return val;
432}
433
a0c4da24
JB		 434static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
435 u32 val)
436{
437 unsigned long flags;
438
439 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
442 goto out_unlock;
443 }
444
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
448 DPIO_BYTE);
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
451
452out_unlock:
453 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
454}
455
57f350b6
JB		 456static void vlv_init_dpio(struct drm_device *dev)
457{
458 struct drm_i915_private *dev_priv = dev->dev_private;
459
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
465}
466
618563e3
DV		 467static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
468{
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
470 return 1;
471}
472
473static const struct dmi_system_id intel_dual_link_lvds[] = {
474 {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
477 .matches = {
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
480 },
481 },
482 { } /* terminating entry */
483};
484
b0354385
TI		 485static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
486 unsigned int reg)
487{
488 unsigned int val;
489
121d527a
TI		 490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
493
618563e3
DV		 494 if (dmi_check_system(intel_dual_link_lvds))
495 return true;
496
b0354385
TI		 497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
499 else {
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
504 */
505 val = I915_READ(reg);
14d94a3d 506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
509 }
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
511}
512
1b894b59
CW		 513static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
514 int refclk)
2c07245f 515{
b91ad0ec
ZW		 516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 518 const intel_limit_t *limit;
b91ad0ec
ZW		 519
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 522 /* LVDS dual channel */
1b894b59 523 if (refclk == 100000)
b91ad0ec
ZW		 524 limit = &intel_limits_ironlake_dual_lvds_100m;
525 else
526 limit = &intel_limits_ironlake_dual_lvds;
527 } else {
1b894b59 528 if (refclk == 100000)
b91ad0ec
ZW		 529 limit = &intel_limits_ironlake_single_lvds_100m;
530 else
531 limit = &intel_limits_ironlake_single_lvds;
532 }
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 534 HAS_eDP)
535 limit = &intel_limits_ironlake_display_port;
2c07245f 536 else
b91ad0ec 537 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 538
539 return limit;
540}
541
044c7c41
ML		 542static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
543{
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
547
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 549 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 550 /* LVDS with dual channel */
e4b36699 551 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 552 else
553 /* LVDS with dual channel */
e4b36699 554 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 557 limit = &intel_limits_g4x_hdmi;
044c7c41 558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 559 limit = &intel_limits_g4x_sdvo;
0206e353 560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 561 limit = &intel_limits_g4x_display_port;
044c7c41 562 } else /* The option is for other outputs */
e4b36699 563 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 564
565 return limit;
566}
567
1b894b59 568static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 569{
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
572
bad720ff 573 if (HAS_PCH_SPLIT(dev))
1b894b59 574 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 575 else if (IS_G4X(dev)) {
044c7c41 576 limit = intel_g4x_limit(crtc);
f2b115e6 577 } else if (IS_PINEVIEW(dev)) {
2177832f 578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 579 limit = &intel_limits_pineview_lvds;
2177832f 580 else
f2b115e6 581 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
587 else
588 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
592 else
593 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 594 } else {
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 596 limit = &intel_limits_i8xx_lvds;
79e53945 597 else
e4b36699 598 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 599 }
600 return limit;
601}
602
f2b115e6
AJ		 603/* m1 is reserved as 0 in Pineview, n is a ring counter */
604static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 605{
2177832f
SL		 606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
610}
611
612static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
613{
f2b115e6
AJ		 614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
2177832f
SL		 616 return;
617 }
79e53945
JB		 618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
622}
623
79e53945
JB		 624/**
625 * Returns whether any output on the specified pipe is of the specified type
626 */
4ef69c7a 627bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 628{
4ef69c7a 629 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 630 struct intel_encoder *encoder;
631
6c2b7c12
DV		 632 for_each_encoder_on_crtc(dev, crtc, encoder)
633 if (encoder->type == type)
4ef69c7a
CW		 634 return true;
635
636 return false;
79e53945
JB		 637}
638
7c04d1d9 639#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 640/**
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
643 */
644
1b894b59
CW		 645static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
79e53945 648{
79e53945 649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 650 INTELPllInvalid("p1 out of range\n");
79e53945 651 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 652 INTELPllInvalid("p out of range\n");
79e53945 653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 654 INTELPllInvalid("m2 out of range\n");
79e53945 655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 656 INTELPllInvalid("m1 out of range\n");
f2b115e6 657 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 658 INTELPllInvalid("m1 <= m2\n");
79e53945 659 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 660 INTELPllInvalid("m out of range\n");
79e53945 661 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 662 INTELPllInvalid("n out of range\n");
79e53945 663 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 664 INTELPllInvalid("vco out of range\n");
79e53945
JB		 665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
667 */
668 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 669 INTELPllInvalid("dot out of range\n");
79e53945
JB		 670
671 return true;
672}
673
d4906093
ML		 674static bool
675intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
d4906093 678
79e53945
JB		 679{
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 intel_clock_t clock;
79e53945
JB		 683 int err = target;
684
bc5e5718 685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 686 (I915_READ(LVDS)) != 0) {
79e53945
JB		 687 /*
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
691 * even can.
692 */
b0354385 693 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 694 clock.p2 = limit->p2.p2_fast;
695 else
696 clock.p2 = limit->p2.p2_slow;
697 } else {
698 if (target < limit->p2.dot_limit)
699 clock.p2 = limit->p2.p2_slow;
700 else
701 clock.p2 = limit->p2.p2_fast;
702 }
703
0206e353 704 memset(best_clock, 0, sizeof(*best_clock));
79e53945 705
42158660
ZY		 706 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
707 clock.m1++) {
708 for (clock.m2 = limit->m2.min;
709 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 710 /* m1 is always 0 in Pineview */
711 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 712 break;
713 for (clock.n = limit->n.min;
714 clock.n <= limit->n.max; clock.n++) {
715 for (clock.p1 = limit->p1.min;
716 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 717 int this_err;
718
2177832f 719 intel_clock(dev, refclk, &clock);
1b894b59
CW		 720 if (!intel_PLL_is_valid(dev, limit,
721 &clock))
79e53945 722 continue;
cec2f356
SP		 723 if (match_clock &&
724 clock.p != match_clock->p)
725 continue;
79e53945
JB		 726
727 this_err = abs(clock.dot - target);
728 if (this_err < err) {
729 *best_clock = clock;
730 err = this_err;
731 }
732 }
733 }
734 }
735 }
736
737 return (err != target);
738}
739
d4906093
ML		 740static bool
741intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 742 int target, int refclk, intel_clock_t *match_clock,
743 intel_clock_t *best_clock)
d4906093
ML		 744{
745 struct drm_device *dev = crtc->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
747 intel_clock_t clock;
748 int max_n;
749 bool found;
6ba770dc
AJ		 750 /* approximately equals target * 0.00585 */
751 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 752 found = false;
753
754 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 755 int lvds_reg;
756
c619eed4 757 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 758 lvds_reg = PCH_LVDS;
759 else
760 lvds_reg = LVDS;
761 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 762 LVDS_CLKB_POWER_UP)
763 clock.p2 = limit->p2.p2_fast;
764 else
765 clock.p2 = limit->p2.p2_slow;
766 } else {
767 if (target < limit->p2.dot_limit)
768 clock.p2 = limit->p2.p2_slow;
769 else
770 clock.p2 = limit->p2.p2_fast;
771 }
772
773 memset(best_clock, 0, sizeof(*best_clock));
774 max_n = limit->n.max;
f77f13e2 775 /* based on hardware requirement, prefer smaller n to precision */
d4906093 776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 777 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 778 for (clock.m1 = limit->m1.max;
779 clock.m1 >= limit->m1.min; clock.m1--) {
780 for (clock.m2 = limit->m2.max;
781 clock.m2 >= limit->m2.min; clock.m2--) {
782 for (clock.p1 = limit->p1.max;
783 clock.p1 >= limit->p1.min; clock.p1--) {
784 int this_err;
785
2177832f 786 intel_clock(dev, refclk, &clock);
1b894b59
CW		 787 if (!intel_PLL_is_valid(dev, limit,
788 &clock))
d4906093 789 continue;
cec2f356
SP		 790 if (match_clock &&
791 clock.p != match_clock->p)
792 continue;
1b894b59
CW		 793
794 this_err = abs(clock.dot - target);
d4906093
ML		 795 if (this_err < err_most) {
796 *best_clock = clock;
797 err_most = this_err;
798 max_n = clock.n;
799 found = true;
800 }
801 }
802 }
803 }
804 }
2c07245f
ZW		 805 return found;
806}
807
5eb08b69 808static bool
f2b115e6 809intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
5eb08b69
ZW		 812{
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
4547668a 815
5eb08b69
ZW		 816 if (target < 200000) {
817 clock.n = 1;
818 clock.p1 = 2;
819 clock.p2 = 10;
820 clock.m1 = 12;
821 clock.m2 = 9;
822 } else {
823 clock.n = 2;
824 clock.p1 = 1;
825 clock.p2 = 10;
826 clock.m1 = 14;
827 clock.m2 = 8;
828 }
829 intel_clock(dev, refclk, &clock);
830 memcpy(best_clock, &clock, sizeof(intel_clock_t));
831 return true;
832}
833
a4fc5ed6
KP		 834/* DisplayPort has only two frequencies, 162MHz and 270MHz */
835static bool
836intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
a4fc5ed6 839{
5eddb70b
CW		 840 intel_clock_t clock;
841 if (target < 200000) {
842 clock.p1 = 2;
843 clock.p2 = 10;
844 clock.n = 2;
845 clock.m1 = 23;
846 clock.m2 = 8;
847 } else {
848 clock.p1 = 1;
849 clock.p2 = 10;
850 clock.n = 1;
851 clock.m1 = 14;
852 clock.m2 = 2;
853 }
854 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855 clock.p = (clock.p1 * clock.p2);
856 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
857 clock.vco = 0;
858 memcpy(best_clock, &clock, sizeof(intel_clock_t));
859 return true;
a4fc5ed6 860}
a0c4da24
JB		 861static bool
862intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865{
866 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
867 u32 m, n, fastclk;
868 u32 updrate, minupdate, fracbits, p;
869 unsigned long bestppm, ppm, absppm;
870 int dotclk, flag;
871
872 dotclk = target * 1000;
873 bestppm = 1000000;
874 ppm = absppm = 0;
875 fastclk = dotclk / (2*100);
876 updrate = 0;
877 minupdate = 19200;
878 fracbits = 1;
879 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
880 bestm1 = bestm2 = bestp1 = bestp2 = 0;
881
882 /* based on hardware requirement, prefer smaller n to precision */
883 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
884 updrate = refclk / n;
885 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
886 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
887 if (p2 > 10)
888 p2 = p2 - 1;
889 p = p1 * p2;
890 /* based on hardware requirement, prefer bigger m1,m2 values */
891 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
892 m2 = (((2*(fastclk * p * n / m1 )) +
893 refclk) / (2*refclk));
894 m = m1 * m2;
895 vco = updrate * m;
896 if (vco >= limit->vco.min && vco < limit->vco.max) {
897 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
898 absppm = (ppm > 0) ? ppm : (-ppm);
899 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
900 bestppm = 0;
901 flag = 1;
902 }
903 if (absppm < bestppm - 10) {
904 bestppm = absppm;
905 flag = 1;
906 }
907 if (flag) {
908 bestn = n;
909 bestm1 = m1;
910 bestm2 = m2;
911 bestp1 = p1;
912 bestp2 = p2;
913 flag = 0;
914 }
915 }
916 }
917 }
918 }
919 }
920 best_clock->n = bestn;
921 best_clock->m1 = bestm1;
922 best_clock->m2 = bestm2;
923 best_clock->p1 = bestp1;
924 best_clock->p2 = bestp2;
925
926 return true;
927}
a4fc5ed6 928
a928d536
PZ		 929static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
930{
931 struct drm_i915_private *dev_priv = dev->dev_private;
932 u32 frame, frame_reg = PIPEFRAME(pipe);
933
934 frame = I915_READ(frame_reg);
935
936 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
937 DRM_DEBUG_KMS("vblank wait timed out\n");
938}
939
9d0498a2
JB		 940/**
941 * intel_wait_for_vblank - wait for vblank on a given pipe
942 * @dev: drm device
943 * @pipe: pipe to wait for
944 *
945 * Wait for vblank to occur on a given pipe. Needed for various bits of
946 * mode setting code.
947 */
948void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 949{
9d0498a2 950 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 951 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 952
a928d536
PZ		 953 if (INTEL_INFO(dev)->gen >= 5) {
954 ironlake_wait_for_vblank(dev, pipe);
955 return;
956 }
957
300387c0
CW		 958 /* Clear existing vblank status. Note this will clear any other
959 * sticky status fields as well.
960 *
961 * This races with i915_driver_irq_handler() with the result
962 * that either function could miss a vblank event. Here it is not
963 * fatal, as we will either wait upon the next vblank interrupt or
964 * timeout. Generally speaking intel_wait_for_vblank() is only
965 * called during modeset at which time the GPU should be idle and
966 * should *not* be performing page flips and thus not waiting on
967 * vblanks...
968 * Currently, the result of us stealing a vblank from the irq
969 * handler is that a single frame will be skipped during swapbuffers.
970 */
971 I915_WRITE(pipestat_reg,
972 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
973
9d0498a2 974 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 975 if (wait_for(I915_READ(pipestat_reg) &
976 PIPE_VBLANK_INTERRUPT_STATUS,
977 50))
9d0498a2
JB		 978 DRM_DEBUG_KMS("vblank wait timed out\n");
979}
980
ab7ad7f6
KP		 981/*
982 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 983 * @dev: drm device
984 * @pipe: pipe to wait for
985 *
986 * After disabling a pipe, we can't wait for vblank in the usual way,
987 * spinning on the vblank interrupt status bit, since we won't actually
988 * see an interrupt when the pipe is disabled.
989 *
ab7ad7f6
KP		 990 * On Gen4 and above:
991 * wait for the pipe register state bit to turn off
992 *
993 * Otherwise:
994 * wait for the display line value to settle (it usually
995 * ends up stopping at the start of the next frame).
58e10eb9 996 *
9d0498a2 997 */
58e10eb9 998void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 999{
1000 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 1001
1002 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 1003 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 1004
1005 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1006 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1007 100))
ab7ad7f6
KP		 1008 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1009 } else {
837ba00f 1010 u32 last_line, line_mask;
58e10eb9 1011 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1012 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1013
837ba00f
PZ		 1014 if (IS_GEN2(dev))
1015 line_mask = DSL_LINEMASK_GEN2;
1016 else
1017 line_mask = DSL_LINEMASK_GEN3;
1018
ab7ad7f6
KP		 1019 /* Wait for the display line to settle */
1020 do {
837ba00f 1021 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1022 mdelay(5);
837ba00f 1023 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1024 time_after(timeout, jiffies));
1025 if (time_after(jiffies, timeout))
1026 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1027 }
79e53945
JB		 1028}
1029
b24e7179
JB		 1030static const char *state_string(bool enabled)
1031{
1032 return enabled ? "on" : "off";
1033}
1034
1035/* Only for pre-ILK configs */
1036static void assert_pll(struct drm_i915_private *dev_priv,
1037 enum pipe pipe, bool state)
1038{
1039 int reg;
1040 u32 val;
1041 bool cur_state;
1042
1043 reg = DPLL(pipe);
1044 val = I915_READ(reg);
1045 cur_state = !!(val & DPLL_VCO_ENABLE);
1046 WARN(cur_state != state,
1047 "PLL state assertion failure (expected %s, current %s)\n",
1048 state_string(state), state_string(cur_state));
1049}
1050#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1051#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1052
040484af
JB		 1053/* For ILK+ */
1054static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1055 struct intel_pch_pll *pll,
1056 struct intel_crtc *crtc,
1057 bool state)
040484af 1058{
040484af
JB		 1059 u32 val;
1060 bool cur_state;
1061
9d82aa17
ED		 1062 if (HAS_PCH_LPT(dev_priv->dev)) {
1063 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1064 return;
1065 }
1066
92b27b08
CW		 1067 if (WARN (!pll,
1068 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1069 return;
ee7b9f93 1070
92b27b08
CW		 1071 val = I915_READ(pll->pll_reg);
1072 cur_state = !!(val & DPLL_VCO_ENABLE);
1073 WARN(cur_state != state,
1074 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1075 pll->pll_reg, state_string(state), state_string(cur_state), val);
1076
1077 /* Make sure the selected PLL is correctly attached to the transcoder */
1078 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1079 u32 pch_dpll;
1080
1081 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1082 cur_state = pll->pll_reg == _PCH_DPLL_B;
1083 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1084 "PLL[%d] not attached to this transcoder %d: %08x\n",
1085 cur_state, crtc->pipe, pch_dpll)) {
1086 cur_state = !!(val >> (4*crtc->pipe + 3));
1087 WARN(cur_state != state,
1088 "PLL[%d] not %s on this transcoder %d: %08x\n",
1089 pll->pll_reg == _PCH_DPLL_B,
1090 state_string(state),
1091 crtc->pipe,
1092 val);
1093 }
d3ccbe86 1094 }
040484af 1095}
92b27b08
CW		 1096#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1097#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1098
1099static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1100 enum pipe pipe, bool state)
1101{
1102 int reg;
1103 u32 val;
1104 bool cur_state;
1105
bf507ef7
ED		 1106 if (IS_HASWELL(dev_priv->dev)) {
1107 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1108 reg = DDI_FUNC_CTL(pipe);
1109 val = I915_READ(reg);
1110 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1111 } else {
1112 reg = FDI_TX_CTL(pipe);
1113 val = I915_READ(reg);
1114 cur_state = !!(val & FDI_TX_ENABLE);
1115 }
040484af
JB		 1116 WARN(cur_state != state,
1117 "FDI TX state assertion failure (expected %s, current %s)\n",
1118 state_string(state), state_string(cur_state));
1119}
1120#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1121#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1122
1123static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1124 enum pipe pipe, bool state)
1125{
1126 int reg;
1127 u32 val;
1128 bool cur_state;
1129
59c859d6
ED		 1130 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1131 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1132 return;
1133 } else {
1134 reg = FDI_RX_CTL(pipe);
1135 val = I915_READ(reg);
1136 cur_state = !!(val & FDI_RX_ENABLE);
1137 }
040484af
JB		 1138 WARN(cur_state != state,
1139 "FDI RX state assertion failure (expected %s, current %s)\n",
1140 state_string(state), state_string(cur_state));
1141}
1142#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1143#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1144
1145static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1146 enum pipe pipe)
1147{
1148 int reg;
1149 u32 val;
1150
1151 /* ILK FDI PLL is always enabled */
1152 if (dev_priv->info->gen == 5)
1153 return;
1154
bf507ef7
ED		 1155 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1156 if (IS_HASWELL(dev_priv->dev))
1157 return;
1158
040484af
JB		 1159 reg = FDI_TX_CTL(pipe);
1160 val = I915_READ(reg);
1161 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1162}
1163
1164static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1165 enum pipe pipe)
1166{
1167 int reg;
1168 u32 val;
1169
59c859d6
ED		 1170 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1171 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1172 return;
1173 }
040484af
JB		 1174 reg = FDI_RX_CTL(pipe);
1175 val = I915_READ(reg);
1176 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1177}
1178
ea0760cf
JB		 1179static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1180 enum pipe pipe)
1181{
1182 int pp_reg, lvds_reg;
1183 u32 val;
1184 enum pipe panel_pipe = PIPE_A;
0de3b485 1185 bool locked = true;
ea0760cf
JB		 1186
1187 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1188 pp_reg = PCH_PP_CONTROL;
1189 lvds_reg = PCH_LVDS;
1190 } else {
1191 pp_reg = PP_CONTROL;
1192 lvds_reg = LVDS;
1193 }
1194
1195 val = I915_READ(pp_reg);
1196 if (!(val & PANEL_POWER_ON) ||
1197 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1198 locked = false;
1199
1200 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1201 panel_pipe = PIPE_B;
1202
1203 WARN(panel_pipe == pipe && locked,
1204 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1205 pipe_name(pipe));
ea0760cf
JB		 1206}
1207
b840d907
JB		 1208void assert_pipe(struct drm_i915_private *dev_priv,
1209 enum pipe pipe, bool state)
b24e7179
JB		 1210{
1211 int reg;
1212 u32 val;
63d7bbe9 1213 bool cur_state;
b24e7179 1214
8e636784
DV		 1215 /* if we need the pipe A quirk it must be always on */
1216 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1217 state = true;
1218
b24e7179
JB		 1219 reg = PIPECONF(pipe);
1220 val = I915_READ(reg);
63d7bbe9
JB		 1221 cur_state = !!(val & PIPECONF_ENABLE);
1222 WARN(cur_state != state,
1223 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1224 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1225}
1226
931872fc
CW		 1227static void assert_plane(struct drm_i915_private *dev_priv,
1228 enum plane plane, bool state)
b24e7179
JB		 1229{
1230 int reg;
1231 u32 val;
931872fc 1232 bool cur_state;
b24e7179
JB		 1233
1234 reg = DSPCNTR(plane);
1235 val = I915_READ(reg);
931872fc
CW		 1236 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1237 WARN(cur_state != state,
1238 "plane %c assertion failure (expected %s, current %s)\n",
1239 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1240}
1241
931872fc
CW		 1242#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1243#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1244
b24e7179
JB		 1245static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1246 enum pipe pipe)
1247{
1248 int reg, i;
1249 u32 val;
1250 int cur_pipe;
1251
19ec1358 1252 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1253 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1254 reg = DSPCNTR(pipe);
1255 val = I915_READ(reg);
1256 WARN((val & DISPLAY_PLANE_ENABLE),
1257 "plane %c assertion failure, should be disabled but not\n",
1258 plane_name(pipe));
19ec1358 1259 return;
28c05794 1260 }
19ec1358 1261
b24e7179
JB		 1262 /* Need to check both planes against the pipe */
1263 for (i = 0; i < 2; i++) {
1264 reg = DSPCNTR(i);
1265 val = I915_READ(reg);
1266 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1267 DISPPLANE_SEL_PIPE_SHIFT;
1268 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1269 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1270 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1271 }
1272}
1273
92f2584a
JB		 1274static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1275{
1276 u32 val;
1277 bool enabled;
1278
9d82aa17
ED		 1279 if (HAS_PCH_LPT(dev_priv->dev)) {
1280 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1281 return;
1282 }
1283
92f2584a
JB		 1284 val = I915_READ(PCH_DREF_CONTROL);
1285 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1286 DREF_SUPERSPREAD_SOURCE_MASK));
1287 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1288}
1289
1290static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1291 enum pipe pipe)
1292{
1293 int reg;
1294 u32 val;
1295 bool enabled;
1296
1297 reg = TRANSCONF(pipe);
1298 val = I915_READ(reg);
1299 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1300 WARN(enabled,
1301 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1302 pipe_name(pipe));
92f2584a
JB		 1303}
1304
4e634389
KP		 1305static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1306 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1307{
1308 if ((val & DP_PORT_EN) == 0)
1309 return false;
1310
1311 if (HAS_PCH_CPT(dev_priv->dev)) {
1312 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1313 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1314 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1315 return false;
1316 } else {
1317 if ((val & DP_PIPE_MASK) != (pipe << 30))
1318 return false;
1319 }
1320 return true;
1321}
1322
1519b995
KP		 1323static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1324 enum pipe pipe, u32 val)
1325{
1326 if ((val & PORT_ENABLE) == 0)
1327 return false;
1328
1329 if (HAS_PCH_CPT(dev_priv->dev)) {
1330 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1331 return false;
1332 } else {
1333 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1334 return false;
1335 }
1336 return true;
1337}
1338
1339static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1340 enum pipe pipe, u32 val)
1341{
1342 if ((val & LVDS_PORT_EN) == 0)
1343 return false;
1344
1345 if (HAS_PCH_CPT(dev_priv->dev)) {
1346 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1347 return false;
1348 } else {
1349 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1350 return false;
1351 }
1352 return true;
1353}
1354
1355static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1356 enum pipe pipe, u32 val)
1357{
1358 if ((val & ADPA_DAC_ENABLE) == 0)
1359 return false;
1360 if (HAS_PCH_CPT(dev_priv->dev)) {
1361 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1362 return false;
1363 } else {
1364 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1365 return false;
1366 }
1367 return true;
1368}
1369
291906f1 1370static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1371 enum pipe pipe, int reg, u32 port_sel)
291906f1 1372{
47a05eca 1373 u32 val = I915_READ(reg);
4e634389 1374 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1375 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1376 reg, pipe_name(pipe));
de9a35ab
DV		 1377
1378 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1379 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1380}
1381
1382static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1383 enum pipe pipe, int reg)
1384{
47a05eca 1385 u32 val = I915_READ(reg);
1519b995 1386 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
23c99e77 1387 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1388 reg, pipe_name(pipe));
de9a35ab
DV		 1389
1390 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1391 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1392}
1393
1394static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1395 enum pipe pipe)
1396{
1397 int reg;
1398 u32 val;
291906f1 1399
f0575e92
KP		 1400 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1401 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1402 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1403
1404 reg = PCH_ADPA;
1405 val = I915_READ(reg);
1519b995 1406 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1407 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1408 pipe_name(pipe));
291906f1
JB		 1409
1410 reg = PCH_LVDS;
1411 val = I915_READ(reg);
1519b995 1412 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1413 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1414 pipe_name(pipe));
291906f1
JB		 1415
1416 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1417 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1418 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1419}
1420
63d7bbe9
JB		 1421/**
1422 * intel_enable_pll - enable a PLL
1423 * @dev_priv: i915 private structure
1424 * @pipe: pipe PLL to enable
1425 *
1426 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1427 * make sure the PLL reg is writable first though, since the panel write
1428 * protect mechanism may be enabled.
1429 *
1430 * Note! This is for pre-ILK only.
7434a255
TR		 1431 *
1432 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9 1433 */
7434a255 1434void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9
JB		 1435{
1436 int reg;
1437 u32 val;
1438
1439 /* No really, not for ILK+ */
a0c4da24 1440 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1441
1442 /* PLL is protected by panel, make sure we can write it */
1443 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1444 assert_panel_unlocked(dev_priv, pipe);
1445
1446 reg = DPLL(pipe);
1447 val = I915_READ(reg);
1448 val |= DPLL_VCO_ENABLE;
1449
1450 /* We do this three times for luck */
1451 I915_WRITE(reg, val);
1452 POSTING_READ(reg);
1453 udelay(150); /* wait for warmup */
1454 I915_WRITE(reg, val);
1455 POSTING_READ(reg);
1456 udelay(150); /* wait for warmup */
1457 I915_WRITE(reg, val);
1458 POSTING_READ(reg);
1459 udelay(150); /* wait for warmup */
1460}
1461
1462/**
1463 * intel_disable_pll - disable a PLL
1464 * @dev_priv: i915 private structure
1465 * @pipe: pipe PLL to disable
1466 *
1467 * Disable the PLL for @pipe, making sure the pipe is off first.
1468 *
1469 * Note! This is for pre-ILK only.
1470 */
1471static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1472{
1473 int reg;
1474 u32 val;
1475
1476 /* Don't disable pipe A or pipe A PLLs if needed */
1477 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1478 return;
1479
1480 /* Make sure the pipe isn't still relying on us */
1481 assert_pipe_disabled(dev_priv, pipe);
1482
1483 reg = DPLL(pipe);
1484 val = I915_READ(reg);
1485 val &= ~DPLL_VCO_ENABLE;
1486 I915_WRITE(reg, val);
1487 POSTING_READ(reg);
1488}
1489
a416edef
ED		 1490/* SBI access */
1491static void
1492intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1493{
1494 unsigned long flags;
1495
1496 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1497 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1498 100)) {
1499 DRM_ERROR("timeout waiting for SBI to become ready\n");
1500 goto out_unlock;
1501 }
1502
1503 I915_WRITE(SBI_ADDR,
1504 (reg << 16));
1505 I915_WRITE(SBI_DATA,
1506 value);
1507 I915_WRITE(SBI_CTL_STAT,
1508 SBI_BUSY |
1509 SBI_CTL_OP_CRWR);
1510
39fb50f6 1511 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1512 100)) {
1513 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1514 goto out_unlock;
1515 }
1516
1517out_unlock:
1518 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1519}
1520
1521static u32
1522intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1523{
1524 unsigned long flags;
39fb50f6 1525 u32 value = 0;
a416edef
ED		 1526
1527 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1528 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1529 100)) {
1530 DRM_ERROR("timeout waiting for SBI to become ready\n");
1531 goto out_unlock;
1532 }
1533
1534 I915_WRITE(SBI_ADDR,
1535 (reg << 16));
1536 I915_WRITE(SBI_CTL_STAT,
1537 SBI_BUSY |
1538 SBI_CTL_OP_CRRD);
1539
39fb50f6 1540 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1541 100)) {
1542 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1543 goto out_unlock;
1544 }
1545
1546 value = I915_READ(SBI_DATA);
1547
1548out_unlock:
1549 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1550 return value;
1551}
1552
92f2584a
JB		 1553/**
1554 * intel_enable_pch_pll - enable PCH PLL
1555 * @dev_priv: i915 private structure
1556 * @pipe: pipe PLL to enable
1557 *
1558 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1559 * drives the transcoder clock.
1560 */
ee7b9f93 1561static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1562{
ee7b9f93 1563 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1564 struct intel_pch_pll *pll;
92f2584a
JB		 1565 int reg;
1566 u32 val;
1567
48da64a8 1568 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1569 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1570 pll = intel_crtc->pch_pll;
1571 if (pll == NULL)
1572 return;
1573
1574 if (WARN_ON(pll->refcount == 0))
1575 return;
ee7b9f93
JB		 1576
1577 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1578 pll->pll_reg, pll->active, pll->on,
1579 intel_crtc->base.base.id);
92f2584a
JB		 1580
1581 /* PCH refclock must be enabled first */
1582 assert_pch_refclk_enabled(dev_priv);
1583
ee7b9f93 1584 if (pll->active++ && pll->on) {
92b27b08 1585 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1586 return;
1587 }
1588
1589 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1590
1591 reg = pll->pll_reg;
92f2584a
JB		 1592 val = I915_READ(reg);
1593 val |= DPLL_VCO_ENABLE;
1594 I915_WRITE(reg, val);
1595 POSTING_READ(reg);
1596 udelay(200);
ee7b9f93
JB		 1597
1598 pll->on = true;
92f2584a
JB		 1599}
1600
ee7b9f93 1601static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1602{
ee7b9f93
JB		 1603 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1604 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1605 int reg;
ee7b9f93 1606 u32 val;
4c609cb8 1607
92f2584a
JB		 1608 /* PCH only available on ILK+ */
1609 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1610 if (pll == NULL)
1611 return;
92f2584a 1612
48da64a8
CW		 1613 if (WARN_ON(pll->refcount == 0))
1614 return;
7a419866 1615
ee7b9f93
JB		 1616 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1617 pll->pll_reg, pll->active, pll->on,
1618 intel_crtc->base.base.id);
7a419866 1619
48da64a8 1620 if (WARN_ON(pll->active == 0)) {
92b27b08 1621 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1622 return;
1623 }
1624
ee7b9f93 1625 if (--pll->active) {
92b27b08 1626 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1627 return;
ee7b9f93
JB		 1628 }
1629
1630 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1631
1632 /* Make sure transcoder isn't still depending on us */
1633 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1634
ee7b9f93 1635 reg = pll->pll_reg;
92f2584a
JB		 1636 val = I915_READ(reg);
1637 val &= ~DPLL_VCO_ENABLE;
1638 I915_WRITE(reg, val);
1639 POSTING_READ(reg);
1640 udelay(200);
ee7b9f93
JB		 1641
1642 pll->on = false;
92f2584a
JB		 1643}
1644
040484af
JB		 1645static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1646 enum pipe pipe)
1647{
1648 int reg;
5f7f726d 1649 u32 val, pipeconf_val;
7c26e5c6 1650 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1651
1652 /* PCH only available on ILK+ */
1653 BUG_ON(dev_priv->info->gen < 5);
1654
1655 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1656 assert_pch_pll_enabled(dev_priv,
1657 to_intel_crtc(crtc)->pch_pll,
1658 to_intel_crtc(crtc));
040484af
JB		 1659
1660 /* FDI must be feeding us bits for PCH ports */
1661 assert_fdi_tx_enabled(dev_priv, pipe);
1662 assert_fdi_rx_enabled(dev_priv, pipe);
1663
59c859d6
ED		 1664 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1665 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1666 return;
1667 }
040484af
JB		 1668 reg = TRANSCONF(pipe);
1669 val = I915_READ(reg);
5f7f726d 1670 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1671
1672 if (HAS_PCH_IBX(dev_priv->dev)) {
1673 /*
1674 * make the BPC in transcoder be consistent with
1675 * that in pipeconf reg.
1676 */
1677 val &= ~PIPE_BPC_MASK;
5f7f726d 1678 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1679 }
5f7f726d
PZ		 1680
1681 val &= ~TRANS_INTERLACE_MASK;
1682 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1683 if (HAS_PCH_IBX(dev_priv->dev) &&
1684 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1685 val |= TRANS_LEGACY_INTERLACED_ILK;
1686 else
1687 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1688 else
1689 val |= TRANS_PROGRESSIVE;
1690
040484af
JB		 1691 I915_WRITE(reg, val | TRANS_ENABLE);
1692 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1693 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1694}
1695
1696static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1697 enum pipe pipe)
1698{
1699 int reg;
1700 u32 val;
1701
1702 /* FDI relies on the transcoder */
1703 assert_fdi_tx_disabled(dev_priv, pipe);
1704 assert_fdi_rx_disabled(dev_priv, pipe);
1705
291906f1
JB		 1706 /* Ports must be off as well */
1707 assert_pch_ports_disabled(dev_priv, pipe);
1708
040484af
JB		 1709 reg = TRANSCONF(pipe);
1710 val = I915_READ(reg);
1711 val &= ~TRANS_ENABLE;
1712 I915_WRITE(reg, val);
1713 /* wait for PCH transcoder off, transcoder state */
1714 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1715 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1716}
1717
b24e7179 1718/**
309cfea8 1719 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1720 * @dev_priv: i915 private structure
1721 * @pipe: pipe to enable
040484af 1722 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1723 *
1724 * Enable @pipe, making sure that various hardware specific requirements
1725 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1726 *
1727 * @pipe should be %PIPE_A or %PIPE_B.
1728 *
1729 * Will wait until the pipe is actually running (i.e. first vblank) before
1730 * returning.
1731 */
040484af
JB		 1732static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1733 bool pch_port)
b24e7179
JB		 1734{
1735 int reg;
1736 u32 val;
1737
1738 /*
1739 * A pipe without a PLL won't actually be able to drive bits from
1740 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1741 * need the check.
1742 */
1743 if (!HAS_PCH_SPLIT(dev_priv->dev))
1744 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1745 else {
1746 if (pch_port) {
1747 /* if driving the PCH, we need FDI enabled */
1748 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1749 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1750 }
1751 /* FIXME: assert CPU port conditions for SNB+ */
1752 }
b24e7179
JB		 1753
1754 reg = PIPECONF(pipe);
1755 val = I915_READ(reg);
00d70b15
CW		 1756 if (val & PIPECONF_ENABLE)
1757 return;
1758
1759 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1760 intel_wait_for_vblank(dev_priv->dev, pipe);
1761}
1762
1763/**
309cfea8 1764 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1765 * @dev_priv: i915 private structure
1766 * @pipe: pipe to disable
1767 *
1768 * Disable @pipe, making sure that various hardware specific requirements
1769 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1770 *
1771 * @pipe should be %PIPE_A or %PIPE_B.
1772 *
1773 * Will wait until the pipe has shut down before returning.
1774 */
1775static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1776 enum pipe pipe)
1777{
1778 int reg;
1779 u32 val;
1780
1781 /*
1782 * Make sure planes won't keep trying to pump pixels to us,
1783 * or we might hang the display.
1784 */
1785 assert_planes_disabled(dev_priv, pipe);
1786
1787 /* Don't disable pipe A or pipe A PLLs if needed */
1788 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1789 return;
1790
1791 reg = PIPECONF(pipe);
1792 val = I915_READ(reg);
00d70b15
CW		 1793 if ((val & PIPECONF_ENABLE) == 0)
1794 return;
1795
1796 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1797 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1798}
1799
d74362c9
KP		 1800/*
1801 * Plane regs are double buffered, going from enabled->disabled needs a
1802 * trigger in order to latch. The display address reg provides this.
1803 */
6f1d69b0 1804void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1805 enum plane plane)
1806{
1807 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1808 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1809}
1810
b24e7179
JB		 1811/**
1812 * intel_enable_plane - enable a display plane on a given pipe
1813 * @dev_priv: i915 private structure
1814 * @plane: plane to enable
1815 * @pipe: pipe being fed
1816 *
1817 * Enable @plane on @pipe, making sure that @pipe is running first.
1818 */
1819static void intel_enable_plane(struct drm_i915_private *dev_priv,
1820 enum plane plane, enum pipe pipe)
1821{
1822 int reg;
1823 u32 val;
1824
1825 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1826 assert_pipe_enabled(dev_priv, pipe);
1827
1828 reg = DSPCNTR(plane);
1829 val = I915_READ(reg);
00d70b15
CW		 1830 if (val & DISPLAY_PLANE_ENABLE)
1831 return;
1832
1833 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1834 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1835 intel_wait_for_vblank(dev_priv->dev, pipe);
1836}
1837
b24e7179
JB		 1838/**
1839 * intel_disable_plane - disable a display plane
1840 * @dev_priv: i915 private structure
1841 * @plane: plane to disable
1842 * @pipe: pipe consuming the data
1843 *
1844 * Disable @plane; should be an independent operation.
1845 */
1846static void intel_disable_plane(struct drm_i915_private *dev_priv,
1847 enum plane plane, enum pipe pipe)
1848{
1849 int reg;
1850 u32 val;
1851
1852 reg = DSPCNTR(plane);
1853 val = I915_READ(reg);
00d70b15
CW		 1854 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1855 return;
1856
1857 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1858 intel_flush_display_plane(dev_priv, plane);
1859 intel_wait_for_vblank(dev_priv->dev, pipe);
1860}
1861
47a05eca 1862static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1863 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1864{
1865 u32 val = I915_READ(reg);
4e634389 1866 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1867 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1868 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1869 }
47a05eca
JB		 1870}
1871
1872static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1873 enum pipe pipe, int reg)
1874{
1875 u32 val = I915_READ(reg);
1519b995 1876 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1877 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1878 reg, pipe);
47a05eca 1879 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1880 }
47a05eca
JB		 1881}
1882
1883/* Disable any ports connected to this transcoder */
1884static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1885 enum pipe pipe)
1886{
1887 u32 reg, val;
1888
1889 val = I915_READ(PCH_PP_CONTROL);
1890 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1891
f0575e92
KP		 1892 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1893 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1894 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1895
1896 reg = PCH_ADPA;
1897 val = I915_READ(reg);
1519b995 1898 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1899 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1900
1901 reg = PCH_LVDS;
1902 val = I915_READ(reg);
1519b995
KP		 1903 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1904 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1905 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1906 POSTING_READ(reg);
1907 udelay(100);
1908 }
1909
1910 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1911 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1912 disable_pch_hdmi(dev_priv, pipe, HDMID);
1913}
1914
127bd2ac 1915int
48b956c5 1916intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1917 struct drm_i915_gem_object *obj,
919926ae 1918 struct intel_ring_buffer *pipelined)
6b95a207 1919{
ce453d81 1920 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1921 u32 alignment;
1922 int ret;
1923
05394f39 1924 switch (obj->tiling_mode) {
6b95a207 1925 case I915_TILING_NONE:
534843da
CW		 1926 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1927 alignment = 128 * 1024;
a6c45cf0 1928 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1929 alignment = 4 * 1024;
1930 else
1931 alignment = 64 * 1024;
6b95a207
KH		 1932 break;
1933 case I915_TILING_X:
1934 /* pin() will align the object as required by fence */
1935 alignment = 0;
1936 break;
1937 case I915_TILING_Y:
1938 /* FIXME: Is this true? */
1939 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1940 return -EINVAL;
1941 default:
1942 BUG();
1943 }
1944
ce453d81 1945 dev_priv->mm.interruptible = false;
2da3b9b9 1946 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1947 if (ret)
ce453d81 1948 goto err_interruptible;
6b95a207
KH		 1949
1950 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1951 * fence, whereas 965+ only requires a fence if using
1952 * framebuffer compression. For simplicity, we always install
1953 * a fence as the cost is not that onerous.
1954 */
06d98131 1955 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1956 if (ret)
1957 goto err_unpin;
1690e1eb 1958
9a5a53b3 1959 i915_gem_object_pin_fence(obj);
6b95a207 1960
ce453d81 1961 dev_priv->mm.interruptible = true;
6b95a207 1962 return 0;
48b956c5
CW		 1963
1964err_unpin:
1965 i915_gem_object_unpin(obj);
ce453d81
CW		 1966err_interruptible:
1967 dev_priv->mm.interruptible = true;
48b956c5 1968 return ret;
6b95a207
KH		 1969}
1970
1690e1eb
CW		 1971void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1972{
1973 i915_gem_object_unpin_fence(obj);
1974 i915_gem_object_unpin(obj);
1975}
1976
c2c75131
DV		 1977/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1978 * is assumed to be a power-of-two. */
1979static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1980 unsigned int bpp,
1981 unsigned int pitch)
1982{
1983 int tile_rows, tiles;
1984
1985 tile_rows = *y / 8;
1986 *y %= 8;
1987 tiles = *x / (512/bpp);
1988 *x %= 512/bpp;
1989
1990 return tile_rows * pitch * 8 + tiles * 4096;
1991}
1992
17638cd6
JB		 1993static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1994 int x, int y)
81255565
JB		 1995{
1996 struct drm_device *dev = crtc->dev;
1997 struct drm_i915_private *dev_priv = dev->dev_private;
1998 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1999 struct intel_framebuffer *intel_fb;
05394f39 2000 struct drm_i915_gem_object *obj;
81255565 2001 int plane = intel_crtc->plane;
e506a0c6 2002 unsigned long linear_offset;
81255565 2003 u32 dspcntr;
5eddb70b 2004 u32 reg;
81255565
JB		 2005
2006 switch (plane) {
2007 case 0:
2008 case 1:
2009 break;
2010 default:
2011 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2012 return -EINVAL;
2013 }
2014
2015 intel_fb = to_intel_framebuffer(fb);
2016 obj = intel_fb->obj;
81255565 2017
5eddb70b
CW		 2018 reg = DSPCNTR(plane);
2019 dspcntr = I915_READ(reg);
81255565
JB		 2020 /* Mask out pixel format bits in case we change it */
2021 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2022 switch (fb->bits_per_pixel) {
2023 case 8:
2024 dspcntr |= DISPPLANE_8BPP;
2025 break;
2026 case 16:
2027 if (fb->depth == 15)
2028 dspcntr |= DISPPLANE_15_16BPP;
2029 else
2030 dspcntr |= DISPPLANE_16BPP;
2031 break;
2032 case 24:
2033 case 32:
2034 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2035 break;
2036 default:
17638cd6 2037 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2038 return -EINVAL;
2039 }
a6c45cf0 2040 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2041 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2042 dspcntr |= DISPPLANE_TILED;
2043 else
2044 dspcntr &= ~DISPPLANE_TILED;
2045 }
2046
5eddb70b 2047 I915_WRITE(reg, dspcntr);
81255565 2048
e506a0c6 2049 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2050
c2c75131
DV		 2051 if (INTEL_INFO(dev)->gen >= 4) {
2052 intel_crtc->dspaddr_offset =
2053 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2054 fb->bits_per_pixel / 8,
2055 fb->pitches[0]);
2056 linear_offset -= intel_crtc->dspaddr_offset;
2057 } else {
e506a0c6 2058 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2059 }
e506a0c6
DV		 2060
2061 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2062 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2063 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2064 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2065 I915_MODIFY_DISPBASE(DSPSURF(plane),
2066 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2067 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2068 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2069 } else
e506a0c6 2070 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2071 POSTING_READ(reg);
81255565 2072
17638cd6
JB		 2073 return 0;
2074}
2075
2076static int ironlake_update_plane(struct drm_crtc *crtc,
2077 struct drm_framebuffer *fb, int x, int y)
2078{
2079 struct drm_device *dev = crtc->dev;
2080 struct drm_i915_private *dev_priv = dev->dev_private;
2081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2082 struct intel_framebuffer *intel_fb;
2083 struct drm_i915_gem_object *obj;
2084 int plane = intel_crtc->plane;
e506a0c6 2085 unsigned long linear_offset;
17638cd6
JB		 2086 u32 dspcntr;
2087 u32 reg;
2088
2089 switch (plane) {
2090 case 0:
2091 case 1:
27f8227b 2092 case 2:
17638cd6
JB		 2093 break;
2094 default:
2095 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2096 return -EINVAL;
2097 }
2098
2099 intel_fb = to_intel_framebuffer(fb);
2100 obj = intel_fb->obj;
2101
2102 reg = DSPCNTR(plane);
2103 dspcntr = I915_READ(reg);
2104 /* Mask out pixel format bits in case we change it */
2105 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2106 switch (fb->bits_per_pixel) {
2107 case 8:
2108 dspcntr |= DISPPLANE_8BPP;
2109 break;
2110 case 16:
2111 if (fb->depth != 16)
2112 return -EINVAL;
2113
2114 dspcntr |= DISPPLANE_16BPP;
2115 break;
2116 case 24:
2117 case 32:
2118 if (fb->depth == 24)
2119 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2120 else if (fb->depth == 30)
2121 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2122 else
2123 return -EINVAL;
2124 break;
2125 default:
2126 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2127 return -EINVAL;
2128 }
2129
2130 if (obj->tiling_mode != I915_TILING_NONE)
2131 dspcntr |= DISPPLANE_TILED;
2132 else
2133 dspcntr &= ~DISPPLANE_TILED;
2134
2135 /* must disable */
2136 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2137
2138 I915_WRITE(reg, dspcntr);
2139
e506a0c6 2140 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131
DV		 2141 intel_crtc->dspaddr_offset =
2142 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2143 fb->bits_per_pixel / 8,
2144 fb->pitches[0]);
2145 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2146
e506a0c6
DV		 2147 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2148 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2149 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2150 I915_MODIFY_DISPBASE(DSPSURF(plane),
2151 obj->gtt_offset + intel_crtc->dspaddr_offset);
17638cd6 2152 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2153 I915_WRITE(DSPLINOFF(plane), linear_offset);
17638cd6
JB		 2154 POSTING_READ(reg);
2155
2156 return 0;
2157}
2158
2159/* Assume fb object is pinned & idle & fenced and just update base pointers */
2160static int
2161intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2162 int x, int y, enum mode_set_atomic state)
2163{
2164 struct drm_device *dev = crtc->dev;
2165 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2166
6b8e6ed0
CW		 2167 if (dev_priv->display.disable_fbc)
2168 dev_priv->display.disable_fbc(dev);
3dec0095 2169 intel_increase_pllclock(crtc);
81255565 2170
6b8e6ed0 2171 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2172}
2173
14667a4b
CW		 2174static int
2175intel_finish_fb(struct drm_framebuffer *old_fb)
2176{
2177 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2178 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2179 bool was_interruptible = dev_priv->mm.interruptible;
2180 int ret;
2181
2182 wait_event(dev_priv->pending_flip_queue,
2183 atomic_read(&dev_priv->mm.wedged) ||
2184 atomic_read(&obj->pending_flip) == 0);
2185
2186 /* Big Hammer, we also need to ensure that any pending
2187 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2188 * current scanout is retired before unpinning the old
2189 * framebuffer.
2190 *
2191 * This should only fail upon a hung GPU, in which case we
2192 * can safely continue.
2193 */
2194 dev_priv->mm.interruptible = false;
2195 ret = i915_gem_object_finish_gpu(obj);
2196 dev_priv->mm.interruptible = was_interruptible;
2197
2198 return ret;
2199}
2200
5c3b82e2 2201static int
3c4fdcfb
KH		 2202intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2203 struct drm_framebuffer *old_fb)
79e53945
JB		 2204{
2205 struct drm_device *dev = crtc->dev;
6b8e6ed0 2206 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 2207 struct drm_i915_master_private *master_priv;
2208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2209 int ret;
79e53945
JB		 2210
2211 /* no fb bound */
2212 if (!crtc->fb) {
a5071c2f 2213 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2214 return 0;
2215 }
2216
5826eca5
ED		 2217 if(intel_crtc->plane > dev_priv->num_pipe) {
2218 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2219 intel_crtc->plane,
2220 dev_priv->num_pipe);
5c3b82e2 2221 return -EINVAL;
79e53945
JB		 2222 }
2223
5c3b82e2 2224 mutex_lock(&dev->struct_mutex);
265db958
CW		 2225 ret = intel_pin_and_fence_fb_obj(dev,
2226 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2227 NULL);
5c3b82e2
CW		 2228 if (ret != 0) {
2229 mutex_unlock(&dev->struct_mutex);
a5071c2f 2230 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2231 return ret;
2232 }
79e53945 2233
14667a4b
CW		 2234 if (old_fb)
2235 intel_finish_fb(old_fb);
265db958 2236
6b8e6ed0 2237 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
4e6cfefc 2238 if (ret) {
1690e1eb 2239 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2240 mutex_unlock(&dev->struct_mutex);
a5071c2f 2241 DRM_ERROR("failed to update base address\n");
4e6cfefc 2242 return ret;
79e53945 2243 }
3c4fdcfb 2244
b7f1de28
CW		 2245 if (old_fb) {
2246 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2247 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2248 }
652c393a 2249
6b8e6ed0 2250 intel_update_fbc(dev);
5c3b82e2 2251 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2252
2253 if (!dev->primary->master)
5c3b82e2 2254 return 0;
79e53945
JB		 2255
2256 master_priv = dev->primary->master->driver_priv;
2257 if (!master_priv->sarea_priv)
5c3b82e2 2258 return 0;
79e53945 2259
265db958 2260 if (intel_crtc->pipe) {
79e53945
JB		 2261 master_priv->sarea_priv->pipeB_x = x;
2262 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2263 } else {
2264 master_priv->sarea_priv->pipeA_x = x;
2265 master_priv->sarea_priv->pipeA_y = y;
79e53945 2266 }
5c3b82e2
CW		 2267
2268 return 0;
79e53945
JB		 2269}
2270
5eddb70b 2271static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2272{
2273 struct drm_device *dev = crtc->dev;
2274 struct drm_i915_private *dev_priv = dev->dev_private;
2275 u32 dpa_ctl;
2276
28c97730 2277 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2278 dpa_ctl = I915_READ(DP_A);
2279 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2280
2281 if (clock < 200000) {
2282 u32 temp;
2283 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2284 /* workaround for 160Mhz:
2285 1) program 0x4600c bits 15:0 = 0x8124
2286 2) program 0x46010 bit 0 = 1
2287 3) program 0x46034 bit 24 = 1
2288 4) program 0x64000 bit 14 = 1
2289 */
2290 temp = I915_READ(0x4600c);
2291 temp &= 0xffff0000;
2292 I915_WRITE(0x4600c, temp | 0x8124);
2293
2294 temp = I915_READ(0x46010);
2295 I915_WRITE(0x46010, temp | 1);
2296
2297 temp = I915_READ(0x46034);
2298 I915_WRITE(0x46034, temp | (1 << 24));
2299 } else {
2300 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2301 }
2302 I915_WRITE(DP_A, dpa_ctl);
2303
5eddb70b 2304 POSTING_READ(DP_A);
32f9d658
ZW		 2305 udelay(500);
2306}
2307
5e84e1a4
ZW		 2308static void intel_fdi_normal_train(struct drm_crtc *crtc)
2309{
2310 struct drm_device *dev = crtc->dev;
2311 struct drm_i915_private *dev_priv = dev->dev_private;
2312 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2313 int pipe = intel_crtc->pipe;
2314 u32 reg, temp;
2315
2316 /* enable normal train */
2317 reg = FDI_TX_CTL(pipe);
2318 temp = I915_READ(reg);
61e499bf 2319 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2320 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2321 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2322 } else {
2323 temp &= ~FDI_LINK_TRAIN_NONE;
2324 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2325 }
5e84e1a4
ZW		 2326 I915_WRITE(reg, temp);
2327
2328 reg = FDI_RX_CTL(pipe);
2329 temp = I915_READ(reg);
2330 if (HAS_PCH_CPT(dev)) {
2331 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2332 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2333 } else {
2334 temp &= ~FDI_LINK_TRAIN_NONE;
2335 temp |= FDI_LINK_TRAIN_NONE;
2336 }
2337 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2338
2339 /* wait one idle pattern time */
2340 POSTING_READ(reg);
2341 udelay(1000);
357555c0
JB		 2342
2343 /* IVB wants error correction enabled */
2344 if (IS_IVYBRIDGE(dev))
2345 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2346 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2347}
2348
291427f5
JB		 2349static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2350{
2351 struct drm_i915_private *dev_priv = dev->dev_private;
2352 u32 flags = I915_READ(SOUTH_CHICKEN1);
2353
2354 flags |= FDI_PHASE_SYNC_OVR(pipe);
2355 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2356 flags |= FDI_PHASE_SYNC_EN(pipe);
2357 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2358 POSTING_READ(SOUTH_CHICKEN1);
2359}
2360
8db9d77b
ZW		 2361/* The FDI link training functions for ILK/Ibexpeak. */
2362static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2363{
2364 struct drm_device *dev = crtc->dev;
2365 struct drm_i915_private *dev_priv = dev->dev_private;
2366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2367 int pipe = intel_crtc->pipe;
0fc932b8 2368 int plane = intel_crtc->plane;
5eddb70b 2369 u32 reg, temp, tries;
8db9d77b 2370
0fc932b8
JB		 2371 /* FDI needs bits from pipe & plane first */
2372 assert_pipe_enabled(dev_priv, pipe);
2373 assert_plane_enabled(dev_priv, plane);
2374
e1a44743
AJ		 2375 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2376 for train result */
5eddb70b
CW		 2377 reg = FDI_RX_IMR(pipe);
2378 temp = I915_READ(reg);
e1a44743
AJ		 2379 temp &= ~FDI_RX_SYMBOL_LOCK;
2380 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2381 I915_WRITE(reg, temp);
2382 I915_READ(reg);
e1a44743
AJ		 2383 udelay(150);
2384
8db9d77b 2385 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2386 reg = FDI_TX_CTL(pipe);
2387 temp = I915_READ(reg);
77ffb597
AJ		 2388 temp &= ~(7 << 19);
2389 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2390 temp &= ~FDI_LINK_TRAIN_NONE;
2391 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2392 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2393
5eddb70b
CW		 2394 reg = FDI_RX_CTL(pipe);
2395 temp = I915_READ(reg);
8db9d77b
ZW		 2396 temp &= ~FDI_LINK_TRAIN_NONE;
2397 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2398 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2399
2400 POSTING_READ(reg);
8db9d77b
ZW		 2401 udelay(150);
2402
5b2adf89 2403 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2404 if (HAS_PCH_IBX(dev)) {
2405 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2406 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2407 FDI_RX_PHASE_SYNC_POINTER_EN);
2408 }
5b2adf89 2409
5eddb70b 2410 reg = FDI_RX_IIR(pipe);
e1a44743 2411 for (tries = 0; tries < 5; tries++) {
5eddb70b 2412 temp = I915_READ(reg);
8db9d77b
ZW		 2413 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2414
2415 if ((temp & FDI_RX_BIT_LOCK)) {
2416 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2417 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2418 break;
2419 }
8db9d77b 2420 }
e1a44743 2421 if (tries == 5)
5eddb70b 2422 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2423
2424 /* Train 2 */
5eddb70b
CW		 2425 reg = FDI_TX_CTL(pipe);
2426 temp = I915_READ(reg);
8db9d77b
ZW		 2427 temp &= ~FDI_LINK_TRAIN_NONE;
2428 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2429 I915_WRITE(reg, temp);
8db9d77b 2430
5eddb70b
CW		 2431 reg = FDI_RX_CTL(pipe);
2432 temp = I915_READ(reg);
8db9d77b
ZW		 2433 temp &= ~FDI_LINK_TRAIN_NONE;
2434 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2435 I915_WRITE(reg, temp);
8db9d77b 2436
5eddb70b
CW		 2437 POSTING_READ(reg);
2438 udelay(150);
8db9d77b 2439
5eddb70b 2440 reg = FDI_RX_IIR(pipe);
e1a44743 2441 for (tries = 0; tries < 5; tries++) {
5eddb70b 2442 temp = I915_READ(reg);
8db9d77b
ZW		 2443 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2444
2445 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2446 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2447 DRM_DEBUG_KMS("FDI train 2 done.\n");
2448 break;
2449 }
8db9d77b 2450 }
e1a44743 2451 if (tries == 5)
5eddb70b 2452 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2453
2454 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2455
8db9d77b
ZW		 2456}
2457
0206e353 2458static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2459 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2460 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2461 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2462 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2463};
2464
2465/* The FDI link training functions for SNB/Cougarpoint. */
2466static void gen6_fdi_link_train(struct drm_crtc *crtc)
2467{
2468 struct drm_device *dev = crtc->dev;
2469 struct drm_i915_private *dev_priv = dev->dev_private;
2470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2471 int pipe = intel_crtc->pipe;
fa37d39e 2472 u32 reg, temp, i, retry;
8db9d77b 2473
e1a44743
AJ		 2474 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2475 for train result */
5eddb70b
CW		 2476 reg = FDI_RX_IMR(pipe);
2477 temp = I915_READ(reg);
e1a44743
AJ		 2478 temp &= ~FDI_RX_SYMBOL_LOCK;
2479 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2480 I915_WRITE(reg, temp);
2481
2482 POSTING_READ(reg);
e1a44743
AJ		 2483 udelay(150);
2484
8db9d77b 2485 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2486 reg = FDI_TX_CTL(pipe);
2487 temp = I915_READ(reg);
77ffb597
AJ		 2488 temp &= ~(7 << 19);
2489 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2490 temp &= ~FDI_LINK_TRAIN_NONE;
2491 temp |= FDI_LINK_TRAIN_PATTERN_1;
2492 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2493 /* SNB-B */
2494 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2495 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2496
5eddb70b
CW		 2497 reg = FDI_RX_CTL(pipe);
2498 temp = I915_READ(reg);
8db9d77b
ZW		 2499 if (HAS_PCH_CPT(dev)) {
2500 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2501 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2502 } else {
2503 temp &= ~FDI_LINK_TRAIN_NONE;
2504 temp |= FDI_LINK_TRAIN_PATTERN_1;
2505 }
5eddb70b
CW		 2506 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2507
2508 POSTING_READ(reg);
8db9d77b
ZW		 2509 udelay(150);
2510
291427f5
JB		 2511 if (HAS_PCH_CPT(dev))
2512 cpt_phase_pointer_enable(dev, pipe);
2513
0206e353 2514 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2515 reg = FDI_TX_CTL(pipe);
2516 temp = I915_READ(reg);
8db9d77b
ZW		 2517 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2518 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2519 I915_WRITE(reg, temp);
2520
2521 POSTING_READ(reg);
8db9d77b
ZW		 2522 udelay(500);
2523
fa37d39e
SP		 2524 for (retry = 0; retry < 5; retry++) {
2525 reg = FDI_RX_IIR(pipe);
2526 temp = I915_READ(reg);
2527 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2528 if (temp & FDI_RX_BIT_LOCK) {
2529 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2530 DRM_DEBUG_KMS("FDI train 1 done.\n");
2531 break;
2532 }
2533 udelay(50);
8db9d77b 2534 }
fa37d39e
SP		 2535 if (retry < 5)
2536 break;
8db9d77b
ZW		 2537 }
2538 if (i == 4)
5eddb70b 2539 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2540
2541 /* Train 2 */
5eddb70b
CW		 2542 reg = FDI_TX_CTL(pipe);
2543 temp = I915_READ(reg);
8db9d77b
ZW		 2544 temp &= ~FDI_LINK_TRAIN_NONE;
2545 temp |= FDI_LINK_TRAIN_PATTERN_2;
2546 if (IS_GEN6(dev)) {
2547 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2548 /* SNB-B */
2549 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2550 }
5eddb70b 2551 I915_WRITE(reg, temp);
8db9d77b 2552
5eddb70b
CW		 2553 reg = FDI_RX_CTL(pipe);
2554 temp = I915_READ(reg);
8db9d77b
ZW		 2555 if (HAS_PCH_CPT(dev)) {
2556 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2557 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2558 } else {
2559 temp &= ~FDI_LINK_TRAIN_NONE;
2560 temp |= FDI_LINK_TRAIN_PATTERN_2;
2561 }
5eddb70b
CW		 2562 I915_WRITE(reg, temp);
2563
2564 POSTING_READ(reg);
8db9d77b
ZW		 2565 udelay(150);
2566
0206e353 2567 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2568 reg = FDI_TX_CTL(pipe);
2569 temp = I915_READ(reg);
8db9d77b
ZW		 2570 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2571 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2572 I915_WRITE(reg, temp);
2573
2574 POSTING_READ(reg);
8db9d77b
ZW		 2575 udelay(500);
2576
fa37d39e
SP		 2577 for (retry = 0; retry < 5; retry++) {
2578 reg = FDI_RX_IIR(pipe);
2579 temp = I915_READ(reg);
2580 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2581 if (temp & FDI_RX_SYMBOL_LOCK) {
2582 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2583 DRM_DEBUG_KMS("FDI train 2 done.\n");
2584 break;
2585 }
2586 udelay(50);
8db9d77b 2587 }
fa37d39e
SP		 2588 if (retry < 5)
2589 break;
8db9d77b
ZW		 2590 }
2591 if (i == 4)
5eddb70b 2592 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2593
2594 DRM_DEBUG_KMS("FDI train done.\n");
2595}
2596
357555c0
JB		 2597/* Manual link training for Ivy Bridge A0 parts */
2598static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2599{
2600 struct drm_device *dev = crtc->dev;
2601 struct drm_i915_private *dev_priv = dev->dev_private;
2602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2603 int pipe = intel_crtc->pipe;
2604 u32 reg, temp, i;
2605
2606 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2607 for train result */
2608 reg = FDI_RX_IMR(pipe);
2609 temp = I915_READ(reg);
2610 temp &= ~FDI_RX_SYMBOL_LOCK;
2611 temp &= ~FDI_RX_BIT_LOCK;
2612 I915_WRITE(reg, temp);
2613
2614 POSTING_READ(reg);
2615 udelay(150);
2616
2617 /* enable CPU FDI TX and PCH FDI RX */
2618 reg = FDI_TX_CTL(pipe);
2619 temp = I915_READ(reg);
2620 temp &= ~(7 << 19);
2621 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2622 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2623 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2624 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2625 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2626 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2627 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2628
2629 reg = FDI_RX_CTL(pipe);
2630 temp = I915_READ(reg);
2631 temp &= ~FDI_LINK_TRAIN_AUTO;
2632 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2633 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2634 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2635 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2636
2637 POSTING_READ(reg);
2638 udelay(150);
2639
291427f5
JB		 2640 if (HAS_PCH_CPT(dev))
2641 cpt_phase_pointer_enable(dev, pipe);
2642
0206e353 2643 for (i = 0; i < 4; i++) {
357555c0
JB		 2644 reg = FDI_TX_CTL(pipe);
2645 temp = I915_READ(reg);
2646 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2647 temp |= snb_b_fdi_train_param[i];
2648 I915_WRITE(reg, temp);
2649
2650 POSTING_READ(reg);
2651 udelay(500);
2652
2653 reg = FDI_RX_IIR(pipe);
2654 temp = I915_READ(reg);
2655 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2656
2657 if (temp & FDI_RX_BIT_LOCK ||
2658 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2659 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2660 DRM_DEBUG_KMS("FDI train 1 done.\n");
2661 break;
2662 }
2663 }
2664 if (i == 4)
2665 DRM_ERROR("FDI train 1 fail!\n");
2666
2667 /* Train 2 */
2668 reg = FDI_TX_CTL(pipe);
2669 temp = I915_READ(reg);
2670 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2671 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2672 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2673 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2674 I915_WRITE(reg, temp);
2675
2676 reg = FDI_RX_CTL(pipe);
2677 temp = I915_READ(reg);
2678 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2679 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2680 I915_WRITE(reg, temp);
2681
2682 POSTING_READ(reg);
2683 udelay(150);
2684
0206e353 2685 for (i = 0; i < 4; i++) {
357555c0
JB		 2686 reg = FDI_TX_CTL(pipe);
2687 temp = I915_READ(reg);
2688 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2689 temp |= snb_b_fdi_train_param[i];
2690 I915_WRITE(reg, temp);
2691
2692 POSTING_READ(reg);
2693 udelay(500);
2694
2695 reg = FDI_RX_IIR(pipe);
2696 temp = I915_READ(reg);
2697 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2698
2699 if (temp & FDI_RX_SYMBOL_LOCK) {
2700 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2701 DRM_DEBUG_KMS("FDI train 2 done.\n");
2702 break;
2703 }
2704 }
2705 if (i == 4)
2706 DRM_ERROR("FDI train 2 fail!\n");
2707
2708 DRM_DEBUG_KMS("FDI train done.\n");
2709}
2710
2711static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2712{
2713 struct drm_device *dev = crtc->dev;
2714 struct drm_i915_private *dev_priv = dev->dev_private;
2715 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2716 int pipe = intel_crtc->pipe;
5eddb70b 2717 u32 reg, temp;
79e53945 2718
c64e311e 2719 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2720 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2721 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2722
c98e9dcf 2723 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2724 reg = FDI_RX_CTL(pipe);
2725 temp = I915_READ(reg);
2726 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2727 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2728 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2729 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2730
2731 POSTING_READ(reg);
c98e9dcf
JB		 2732 udelay(200);
2733
2734 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2735 temp = I915_READ(reg);
2736 I915_WRITE(reg, temp | FDI_PCDCLK);
2737
2738 POSTING_READ(reg);
c98e9dcf
JB		 2739 udelay(200);
2740
bf507ef7
ED		 2741 /* On Haswell, the PLL configuration for ports and pipes is handled
2742 * separately, as part of DDI setup */
2743 if (!IS_HASWELL(dev)) {
2744 /* Enable CPU FDI TX PLL, always on for Ironlake */
2745 reg = FDI_TX_CTL(pipe);
2746 temp = I915_READ(reg);
2747 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2748 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2749
bf507ef7
ED		 2750 POSTING_READ(reg);
2751 udelay(100);
2752 }
6be4a607 2753 }
0e23b99d
JB		 2754}
2755
291427f5
JB		 2756static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2757{
2758 struct drm_i915_private *dev_priv = dev->dev_private;
2759 u32 flags = I915_READ(SOUTH_CHICKEN1);
2760
2761 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2762 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2763 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2764 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2765 POSTING_READ(SOUTH_CHICKEN1);
2766}
0fc932b8
JB		 2767static void ironlake_fdi_disable(struct drm_crtc *crtc)
2768{
2769 struct drm_device *dev = crtc->dev;
2770 struct drm_i915_private *dev_priv = dev->dev_private;
2771 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2772 int pipe = intel_crtc->pipe;
2773 u32 reg, temp;
2774
2775 /* disable CPU FDI tx and PCH FDI rx */
2776 reg = FDI_TX_CTL(pipe);
2777 temp = I915_READ(reg);
2778 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2779 POSTING_READ(reg);
2780
2781 reg = FDI_RX_CTL(pipe);
2782 temp = I915_READ(reg);
2783 temp &= ~(0x7 << 16);
2784 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2785 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2786
2787 POSTING_READ(reg);
2788 udelay(100);
2789
2790 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2791 if (HAS_PCH_IBX(dev)) {
2792 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2793 I915_WRITE(FDI_RX_CHICKEN(pipe),
2794 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2795 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2796 } else if (HAS_PCH_CPT(dev)) {
2797 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2798 }
0fc932b8
JB		 2799
2800 /* still set train pattern 1 */
2801 reg = FDI_TX_CTL(pipe);
2802 temp = I915_READ(reg);
2803 temp &= ~FDI_LINK_TRAIN_NONE;
2804 temp |= FDI_LINK_TRAIN_PATTERN_1;
2805 I915_WRITE(reg, temp);
2806
2807 reg = FDI_RX_CTL(pipe);
2808 temp = I915_READ(reg);
2809 if (HAS_PCH_CPT(dev)) {
2810 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2811 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2812 } else {
2813 temp &= ~FDI_LINK_TRAIN_NONE;
2814 temp |= FDI_LINK_TRAIN_PATTERN_1;
2815 }
2816 /* BPC in FDI rx is consistent with that in PIPECONF */
2817 temp &= ~(0x07 << 16);
2818 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2819 I915_WRITE(reg, temp);
2820
2821 POSTING_READ(reg);
2822 udelay(100);
2823}
2824
e6c3a2a6
CW		 2825static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2826{
0f91128d 2827 struct drm_device *dev = crtc->dev;
e6c3a2a6
CW		 2828
2829 if (crtc->fb == NULL)
2830 return;
2831
0f91128d
CW		 2832 mutex_lock(&dev->struct_mutex);
2833 intel_finish_fb(crtc->fb);
2834 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2835}
2836
040484af
JB		 2837static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2838{
2839 struct drm_device *dev = crtc->dev;
040484af
JB		 2840 struct intel_encoder *encoder;
2841
2842 /*
2843 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2844 * must be driven by its own crtc; no sharing is possible.
2845 */
6c2b7c12 2846 for_each_encoder_on_crtc(dev, crtc, encoder) {
040484af 2847
6ee8bab0
ED		 2848 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2849 * CPU handles all others */
2850 if (IS_HASWELL(dev)) {
2851 /* It is still unclear how this will work on PPT, so throw up a warning */
2852 WARN_ON(!HAS_PCH_LPT(dev));
2853
2854 if (encoder->type == DRM_MODE_ENCODER_DAC) {
2855 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2856 return true;
2857 } else {
2858 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2859 encoder->type);
2860 return false;
2861 }
2862 }
2863
040484af
JB		 2864 switch (encoder->type) {
2865 case INTEL_OUTPUT_EDP:
2866 if (!intel_encoder_is_pch_edp(&encoder->base))
2867 return false;
2868 continue;
2869 }
2870 }
2871
2872 return true;
2873}
2874
e615efe4
ED		 2875/* Program iCLKIP clock to the desired frequency */
2876static void lpt_program_iclkip(struct drm_crtc *crtc)
2877{
2878 struct drm_device *dev = crtc->dev;
2879 struct drm_i915_private *dev_priv = dev->dev_private;
2880 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2881 u32 temp;
2882
2883 /* It is necessary to ungate the pixclk gate prior to programming
2884 * the divisors, and gate it back when it is done.
2885 */
2886 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2887
2888 /* Disable SSCCTL */
2889 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2890 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2891 SBI_SSCCTL_DISABLE);
2892
2893 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2894 if (crtc->mode.clock == 20000) {
2895 auxdiv = 1;
2896 divsel = 0x41;
2897 phaseinc = 0x20;
2898 } else {
2899 /* The iCLK virtual clock root frequency is in MHz,
2900 * but the crtc->mode.clock in in KHz. To get the divisors,
2901 * it is necessary to divide one by another, so we
2902 * convert the virtual clock precision to KHz here for higher
2903 * precision.
2904 */
2905 u32 iclk_virtual_root_freq = 172800 * 1000;
2906 u32 iclk_pi_range = 64;
2907 u32 desired_divisor, msb_divisor_value, pi_value;
2908
2909 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2910 msb_divisor_value = desired_divisor / iclk_pi_range;
2911 pi_value = desired_divisor % iclk_pi_range;
2912
2913 auxdiv = 0;
2914 divsel = msb_divisor_value - 2;
2915 phaseinc = pi_value;
2916 }
2917
2918 /* This should not happen with any sane values */
2919 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2920 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2921 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2922 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2923
2924 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2925 crtc->mode.clock,
2926 auxdiv,
2927 divsel,
2928 phasedir,
2929 phaseinc);
2930
2931 /* Program SSCDIVINTPHASE6 */
2932 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2933 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2934 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2935 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2936 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2937 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2938 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2939
2940 intel_sbi_write(dev_priv,
2941 SBI_SSCDIVINTPHASE6,
2942 temp);
2943
2944 /* Program SSCAUXDIV */
2945 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2946 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2947 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2948 intel_sbi_write(dev_priv,
2949 SBI_SSCAUXDIV6,
2950 temp);
2951
2952
2953 /* Enable modulator and associated divider */
2954 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2955 temp &= ~SBI_SSCCTL_DISABLE;
2956 intel_sbi_write(dev_priv,
2957 SBI_SSCCTL6,
2958 temp);
2959
2960 /* Wait for initialization time */
2961 udelay(24);
2962
2963 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2964}
2965
f67a559d
JB		 2966/*
2967 * Enable PCH resources required for PCH ports:
2968 * - PCH PLLs
2969 * - FDI training & RX/TX
2970 * - update transcoder timings
2971 * - DP transcoding bits
2972 * - transcoder
2973 */
2974static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2975{
2976 struct drm_device *dev = crtc->dev;
2977 struct drm_i915_private *dev_priv = dev->dev_private;
2978 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2979 int pipe = intel_crtc->pipe;
ee7b9f93 2980 u32 reg, temp;
2c07245f 2981
e7e164db
CW		 2982 assert_transcoder_disabled(dev_priv, pipe);
2983
c98e9dcf 2984 /* For PCH output, training FDI link */
674cf967 2985 dev_priv->display.fdi_link_train(crtc);
2c07245f 2986
6f13b7b5
CW		 2987 intel_enable_pch_pll(intel_crtc);
2988
e615efe4
ED		 2989 if (HAS_PCH_LPT(dev)) {
2990 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2991 lpt_program_iclkip(crtc);
2992 } else if (HAS_PCH_CPT(dev)) {
ee7b9f93 2993 u32 sel;
4b645f14 2994
c98e9dcf 2995 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 2996 switch (pipe) {
2997 default:
2998 case 0:
2999 temp |= TRANSA_DPLL_ENABLE;
3000 sel = TRANSA_DPLLB_SEL;
3001 break;
3002 case 1:
3003 temp |= TRANSB_DPLL_ENABLE;
3004 sel = TRANSB_DPLLB_SEL;
3005 break;
3006 case 2:
3007 temp |= TRANSC_DPLL_ENABLE;
3008 sel = TRANSC_DPLLB_SEL;
3009 break;
d64311ab 3010 }
ee7b9f93
JB		 3011 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3012 temp |= sel;
3013 else
3014 temp &= ~sel;
c98e9dcf 3015 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3016 }
5eddb70b 3017
d9b6cb56
JB		 3018 /* set transcoder timing, panel must allow it */
3019 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3020 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3021 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3022 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3023
5eddb70b
CW		 3024 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3025 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3026 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3027 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3028
f57e1e3a
ED		 3029 if (!IS_HASWELL(dev))
3030 intel_fdi_normal_train(crtc);
5e84e1a4 3031
c98e9dcf
JB		 3032 /* For PCH DP, enable TRANS_DP_CTL */
3033 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3034 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3035 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3036 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3037 reg = TRANS_DP_CTL(pipe);
3038 temp = I915_READ(reg);
3039 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3040 TRANS_DP_SYNC_MASK |
3041 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3042 temp |= (TRANS_DP_OUTPUT_ENABLE |
3043 TRANS_DP_ENH_FRAMING);
9325c9f0 3044 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3045
3046 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3047 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3048 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3049 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3050
3051 switch (intel_trans_dp_port_sel(crtc)) {
3052 case PCH_DP_B:
5eddb70b 3053 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3054 break;
3055 case PCH_DP_C:
5eddb70b 3056 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3057 break;
3058 case PCH_DP_D:
5eddb70b 3059 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3060 break;
3061 default:
3062 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 3063 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 3064 break;
32f9d658 3065 }
2c07245f 3066
5eddb70b 3067 I915_WRITE(reg, temp);
6be4a607 3068 }
b52eb4dc 3069
040484af 3070 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3071}
3072
ee7b9f93
JB		 3073static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3074{
3075 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3076
3077 if (pll == NULL)
3078 return;
3079
3080 if (pll->refcount == 0) {
3081 WARN(1, "bad PCH PLL refcount\n");
3082 return;
3083 }
3084
3085 --pll->refcount;
3086 intel_crtc->pch_pll = NULL;
3087}
3088
3089static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3090{
3091 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3092 struct intel_pch_pll *pll;
3093 int i;
3094
3095 pll = intel_crtc->pch_pll;
3096 if (pll) {
3097 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3098 intel_crtc->base.base.id, pll->pll_reg);
3099 goto prepare;
3100 }
3101
98b6bd99
DV		 3102 if (HAS_PCH_IBX(dev_priv->dev)) {
3103 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3104 i = intel_crtc->pipe;
3105 pll = &dev_priv->pch_plls[i];
3106
3107 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3108 intel_crtc->base.base.id, pll->pll_reg);
3109
3110 goto found;
3111 }
3112
ee7b9f93
JB		 3113 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3114 pll = &dev_priv->pch_plls[i];
3115
3116 /* Only want to check enabled timings first */
3117 if (pll->refcount == 0)
3118 continue;
3119
3120 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3121 fp == I915_READ(pll->fp0_reg)) {
3122 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3123 intel_crtc->base.base.id,
3124 pll->pll_reg, pll->refcount, pll->active);
3125
3126 goto found;
3127 }
3128 }
3129
3130 /* Ok no matching timings, maybe there's a free one? */
3131 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3132 pll = &dev_priv->pch_plls[i];
3133 if (pll->refcount == 0) {
3134 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3135 intel_crtc->base.base.id, pll->pll_reg);
3136 goto found;
3137 }
3138 }
3139
3140 return NULL;
3141
3142found:
3143 intel_crtc->pch_pll = pll;
3144 pll->refcount++;
3145 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3146prepare: /* separate function? */
3147 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3148
e04c7350
CW		 3149 /* Wait for the clocks to stabilize before rewriting the regs */
3150 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3151 POSTING_READ(pll->pll_reg);
3152 udelay(150);
e04c7350
CW		 3153
3154 I915_WRITE(pll->fp0_reg, fp);
3155 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3156 pll->on = false;
3157 return pll;
3158}
3159
d4270e57
JB		 3160void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3161{
3162 struct drm_i915_private *dev_priv = dev->dev_private;
3163 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3164 u32 temp;
3165
3166 temp = I915_READ(dslreg);
3167 udelay(500);
3168 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3169 /* Without this, mode sets may fail silently on FDI */
3170 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3171 udelay(250);
3172 I915_WRITE(tc2reg, 0);
3173 if (wait_for(I915_READ(dslreg) != temp, 5))
3174 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3175 }
3176}
3177
f67a559d
JB		 3178static void ironlake_crtc_enable(struct drm_crtc *crtc)
3179{
3180 struct drm_device *dev = crtc->dev;
3181 struct drm_i915_private *dev_priv = dev->dev_private;
3182 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3183 int pipe = intel_crtc->pipe;
3184 int plane = intel_crtc->plane;
3185 u32 temp;
3186 bool is_pch_port;
3187
3188 if (intel_crtc->active)
3189 return;
3190
3191 intel_crtc->active = true;
3192 intel_update_watermarks(dev);
3193
3194 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3195 temp = I915_READ(PCH_LVDS);
3196 if ((temp & LVDS_PORT_EN) == 0)
3197 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3198 }
3199
3200 is_pch_port = intel_crtc_driving_pch(crtc);
3201
3202 if (is_pch_port)
357555c0 3203 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 3204 else
3205 ironlake_fdi_disable(crtc);
3206
3207 /* Enable panel fitting for LVDS */
3208 if (dev_priv->pch_pf_size &&
3209 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3210 /* Force use of hard-coded filter coefficients
3211 * as some pre-programmed values are broken,
3212 * e.g. x201.
3213 */
9db4a9c7
JB		 3214 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3215 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3216 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3217 }
3218
9c54c0dd
JB		 3219 /*
3220 * On ILK+ LUT must be loaded before the pipe is running but with
3221 * clocks enabled
3222 */
3223 intel_crtc_load_lut(crtc);
3224
f67a559d
JB		 3225 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3226 intel_enable_plane(dev_priv, plane, pipe);
3227
3228 if (is_pch_port)
3229 ironlake_pch_enable(crtc);
c98e9dcf 3230
d1ebd816 3231 mutex_lock(&dev->struct_mutex);
bed4a673 3232 intel_update_fbc(dev);
d1ebd816
BW		 3233 mutex_unlock(&dev->struct_mutex);
3234
6b383a7f 3235 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 3236}
3237
3238static void ironlake_crtc_disable(struct drm_crtc *crtc)
3239{
3240 struct drm_device *dev = crtc->dev;
3241 struct drm_i915_private *dev_priv = dev->dev_private;
3242 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3243 int pipe = intel_crtc->pipe;
3244 int plane = intel_crtc->plane;
5eddb70b 3245 u32 reg, temp;
b52eb4dc 3246
f7abfe8b
CW		 3247 if (!intel_crtc->active)
3248 return;
3249
e6c3a2a6 3250 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3251 drm_vblank_off(dev, pipe);
6b383a7f 3252 intel_crtc_update_cursor(crtc, false);
5eddb70b 3253
b24e7179 3254 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3255
973d04f9
CW		 3256 if (dev_priv->cfb_plane == plane)
3257 intel_disable_fbc(dev);
2c07245f 3258
b24e7179 3259 intel_disable_pipe(dev_priv, pipe);
32f9d658 3260
6be4a607 3261 /* Disable PF */
9db4a9c7
JB		 3262 I915_WRITE(PF_CTL(pipe), 0);
3263 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3264
0fc932b8 3265 ironlake_fdi_disable(crtc);
2c07245f 3266
47a05eca
JB		 3267 /* This is a horrible layering violation; we should be doing this in
3268 * the connector/encoder ->prepare instead, but we don't always have
3269 * enough information there about the config to know whether it will
3270 * actually be necessary or just cause undesired flicker.
3271 */
3272 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 3273
040484af 3274 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3275
6be4a607
JB		 3276 if (HAS_PCH_CPT(dev)) {
3277 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3278 reg = TRANS_DP_CTL(pipe);
3279 temp = I915_READ(reg);
3280 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3281 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3282 I915_WRITE(reg, temp);
6be4a607
JB		 3283
3284 /* disable DPLL_SEL */
3285 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3286 switch (pipe) {
3287 case 0:
d64311ab 3288 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3289 break;
3290 case 1:
6be4a607 3291 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3292 break;
3293 case 2:
4b645f14 3294 /* C shares PLL A or B */
d64311ab 3295 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3296 break;
3297 default:
3298 BUG(); /* wtf */
3299 }
6be4a607 3300 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3301 }
e3421a18 3302
6be4a607 3303 /* disable PCH DPLL */
ee7b9f93 3304 intel_disable_pch_pll(intel_crtc);
8db9d77b 3305
6be4a607 3306 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 3307 reg = FDI_RX_CTL(pipe);
3308 temp = I915_READ(reg);
3309 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 3310
6be4a607 3311 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 3312 reg = FDI_TX_CTL(pipe);
3313 temp = I915_READ(reg);
3314 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3315
3316 POSTING_READ(reg);
6be4a607 3317 udelay(100);
8db9d77b 3318
5eddb70b
CW		 3319 reg = FDI_RX_CTL(pipe);
3320 temp = I915_READ(reg);
3321 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 3322
6be4a607 3323 /* Wait for the clocks to turn off. */
5eddb70b 3324 POSTING_READ(reg);
6be4a607 3325 udelay(100);
6b383a7f 3326
f7abfe8b 3327 intel_crtc->active = false;
6b383a7f 3328 intel_update_watermarks(dev);
d1ebd816
BW		 3329
3330 mutex_lock(&dev->struct_mutex);
6b383a7f 3331 intel_update_fbc(dev);
d1ebd816 3332 mutex_unlock(&dev->struct_mutex);
6be4a607 3333}
1b3c7a47 3334
6be4a607
JB		 3335static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3336{
3337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3338 int pipe = intel_crtc->pipe;
3339 int plane = intel_crtc->plane;
8db9d77b 3340
6be4a607
JB		 3341 /* XXX: When our outputs are all unaware of DPMS modes other than off
3342 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3343 */
3344 switch (mode) {
3345 case DRM_MODE_DPMS_ON:
3346 case DRM_MODE_DPMS_STANDBY:
3347 case DRM_MODE_DPMS_SUSPEND:
3348 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3349 ironlake_crtc_enable(crtc);
3350 break;
1b3c7a47 3351
6be4a607
JB		 3352 case DRM_MODE_DPMS_OFF:
3353 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3354 ironlake_crtc_disable(crtc);
2c07245f
ZW		 3355 break;
3356 }
3357}
3358
ee7b9f93
JB		 3359static void ironlake_crtc_off(struct drm_crtc *crtc)
3360{
3361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3362 intel_put_pch_pll(intel_crtc);
3363}
3364
02e792fb
DV		 3365static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3366{
02e792fb 3367 if (!enable && intel_crtc->overlay) {
23f09ce3 3368 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3369 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3370
23f09ce3 3371 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3372 dev_priv->mm.interruptible = false;
3373 (void) intel_overlay_switch_off(intel_crtc->overlay);
3374 dev_priv->mm.interruptible = true;
23f09ce3 3375 mutex_unlock(&dev->struct_mutex);
02e792fb 3376 }
02e792fb 3377
5dcdbcb0
CW		 3378 /* Let userspace switch the overlay on again. In most cases userspace
3379 * has to recompute where to put it anyway.
3380 */
02e792fb
DV		 3381}
3382
0b8765c6 3383static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3384{
3385 struct drm_device *dev = crtc->dev;
79e53945
JB		 3386 struct drm_i915_private *dev_priv = dev->dev_private;
3387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3388 int pipe = intel_crtc->pipe;
80824003 3389 int plane = intel_crtc->plane;
79e53945 3390
f7abfe8b
CW		 3391 if (intel_crtc->active)
3392 return;
3393
3394 intel_crtc->active = true;
6b383a7f
CW		 3395 intel_update_watermarks(dev);
3396
63d7bbe9 3397 intel_enable_pll(dev_priv, pipe);
040484af 3398 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3399 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3400
0b8765c6 3401 intel_crtc_load_lut(crtc);
bed4a673 3402 intel_update_fbc(dev);
79e53945 3403
0b8765c6
JB		 3404 /* Give the overlay scaler a chance to enable if it's on this pipe */
3405 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3406 intel_crtc_update_cursor(crtc, true);
0b8765c6 3407}
79e53945 3408
0b8765c6
JB		 3409static void i9xx_crtc_disable(struct drm_crtc *crtc)
3410{
3411 struct drm_device *dev = crtc->dev;
3412 struct drm_i915_private *dev_priv = dev->dev_private;
3413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3414 int pipe = intel_crtc->pipe;
3415 int plane = intel_crtc->plane;
b690e96c 3416
f7abfe8b
CW		 3417 if (!intel_crtc->active)
3418 return;
3419
0b8765c6 3420 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3421 intel_crtc_wait_for_pending_flips(crtc);
3422 drm_vblank_off(dev, pipe);
0b8765c6 3423 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3424 intel_crtc_update_cursor(crtc, false);
0b8765c6 3425
973d04f9
CW		 3426 if (dev_priv->cfb_plane == plane)
3427 intel_disable_fbc(dev);
79e53945 3428
b24e7179 3429 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3430 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3431 intel_disable_pll(dev_priv, pipe);
0b8765c6 3432
f7abfe8b 3433 intel_crtc->active = false;
6b383a7f
CW		 3434 intel_update_fbc(dev);
3435 intel_update_watermarks(dev);
0b8765c6
JB		 3436}
3437
3438static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3439{
3440 /* XXX: When our outputs are all unaware of DPMS modes other than off
3441 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3442 */
3443 switch (mode) {
3444 case DRM_MODE_DPMS_ON:
3445 case DRM_MODE_DPMS_STANDBY:
3446 case DRM_MODE_DPMS_SUSPEND:
3447 i9xx_crtc_enable(crtc);
3448 break;
3449 case DRM_MODE_DPMS_OFF:
3450 i9xx_crtc_disable(crtc);
79e53945
JB		 3451 break;
3452 }
2c07245f
ZW		 3453}
3454
ee7b9f93
JB		 3455static void i9xx_crtc_off(struct drm_crtc *crtc)
3456{
3457}
3458
2c07245f
ZW		 3459/**
3460 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3461 */
3462static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3463{
3464 struct drm_device *dev = crtc->dev;
e70236a8 3465 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3466 struct drm_i915_master_private *master_priv;
3467 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3468 int pipe = intel_crtc->pipe;
3469 bool enabled;
3470
032d2a0d
CW		 3471 if (intel_crtc->dpms_mode == mode)
3472 return;
3473
65655d4a 3474 intel_crtc->dpms_mode = mode;
debcaddc 3475
e70236a8 3476 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3477
3478 if (!dev->primary->master)
3479 return;
3480
3481 master_priv = dev->primary->master->driver_priv;
3482 if (!master_priv->sarea_priv)
3483 return;
3484
3485 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3486
3487 switch (pipe) {
3488 case 0:
3489 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3490 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3491 break;
3492 case 1:
3493 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3494 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3495 break;
3496 default:
9db4a9c7 3497 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3498 break;
3499 }
79e53945
JB		 3500}
3501
cdd59983
CW		 3502static void intel_crtc_disable(struct drm_crtc *crtc)
3503{
3504 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3505 struct drm_device *dev = crtc->dev;
ee7b9f93 3506 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983
CW		 3507
3508 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
ee7b9f93
JB		 3509 dev_priv->display.off(crtc);
3510
931872fc
CW		 3511 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3512 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3513
3514 if (crtc->fb) {
3515 mutex_lock(&dev->struct_mutex);
1690e1eb 3516 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983
CW		 3517 mutex_unlock(&dev->struct_mutex);
3518 }
3519}
3520
7e7d76c3
JB		 3521/* Prepare for a mode set.
3522 *
3523 * Note we could be a lot smarter here. We need to figure out which outputs
3524 * will be enabled, which disabled (in short, how the config will changes)
3525 * and perform the minimum necessary steps to accomplish that, e.g. updating
3526 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3527 * panel fitting is in the proper state, etc.
3528 */
3529static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3530{
7e7d76c3 3531 i9xx_crtc_disable(crtc);
79e53945
JB		 3532}
3533
7e7d76c3 3534static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3535{
7e7d76c3 3536 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3537}
3538
3539static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3540{
7e7d76c3 3541 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3542}
3543
3544static void ironlake_crtc_commit(struct drm_crtc *crtc)
3545{
7e7d76c3 3546 ironlake_crtc_enable(crtc);
79e53945
JB		 3547}
3548
0206e353 3549void intel_encoder_prepare(struct drm_encoder *encoder)
79e53945
JB		 3550{
3551 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3552 /* lvds has its own version of prepare see intel_lvds_prepare */
3553 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3554}
3555
0206e353 3556void intel_encoder_commit(struct drm_encoder *encoder)
79e53945
JB		 3557{
3558 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
d4270e57 3559 struct drm_device *dev = encoder->dev;
d47d7cb8 3560 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
d4270e57 3561
79e53945
JB		 3562 /* lvds has its own version of commit see intel_lvds_commit */
3563 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
d4270e57
JB		 3564
3565 if (HAS_PCH_CPT(dev))
3566 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
79e53945
JB		 3567}
3568
ea5b213a
CW		 3569void intel_encoder_destroy(struct drm_encoder *encoder)
3570{
4ef69c7a 3571 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3572
ea5b213a
CW		 3573 drm_encoder_cleanup(encoder);
3574 kfree(intel_encoder);
3575}
3576
79e53945 3577static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3578 const struct drm_display_mode *mode,
79e53945
JB		 3579 struct drm_display_mode *adjusted_mode)
3580{
2c07245f 3581 struct drm_device *dev = crtc->dev;
89749350 3582
bad720ff 3583 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3584 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3585 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3586 return false;
2c07245f 3587 }
89749350 3588
f9bef081
DV		 3589 /* All interlaced capable intel hw wants timings in frames. Note though
3590 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3591 * timings, so we need to be careful not to clobber these.*/
3592 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3593 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3594
79e53945
JB		 3595 return true;
3596}
3597
25eb05fc
JB		 3598static int valleyview_get_display_clock_speed(struct drm_device *dev)
3599{
3600 return 400000; /* FIXME */
3601}
3602
e70236a8
JB		 3603static int i945_get_display_clock_speed(struct drm_device *dev)
3604{
3605 return 400000;
3606}
79e53945 3607
e70236a8 3608static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3609{
e70236a8
JB		 3610 return 333000;
3611}
79e53945 3612
e70236a8
JB		 3613static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3614{
3615 return 200000;
3616}
79e53945 3617
e70236a8
JB		 3618static int i915gm_get_display_clock_speed(struct drm_device *dev)
3619{
3620 u16 gcfgc = 0;
79e53945 3621
e70236a8
JB		 3622 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3623
3624 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3625 return 133000;
3626 else {
3627 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3628 case GC_DISPLAY_CLOCK_333_MHZ:
3629 return 333000;
3630 default:
3631 case GC_DISPLAY_CLOCK_190_200_MHZ:
3632 return 190000;
79e53945 3633 }
e70236a8
JB		 3634 }
3635}
3636
3637static int i865_get_display_clock_speed(struct drm_device *dev)
3638{
3639 return 266000;
3640}
3641
3642static int i855_get_display_clock_speed(struct drm_device *dev)
3643{
3644 u16 hpllcc = 0;
3645 /* Assume that the hardware is in the high speed state. This
3646 * should be the default.
3647 */
3648 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3649 case GC_CLOCK_133_200:
3650 case GC_CLOCK_100_200:
3651 return 200000;
3652 case GC_CLOCK_166_250:
3653 return 250000;
3654 case GC_CLOCK_100_133:
79e53945 3655 return 133000;
e70236a8 3656 }
79e53945 3657
e70236a8
JB		 3658 /* Shouldn't happen */
3659 return 0;
3660}
79e53945 3661
e70236a8
JB		 3662static int i830_get_display_clock_speed(struct drm_device *dev)
3663{
3664 return 133000;
79e53945
JB		 3665}
3666
2c07245f
ZW		 3667struct fdi_m_n {
3668 u32 tu;
3669 u32 gmch_m;
3670 u32 gmch_n;
3671 u32 link_m;
3672 u32 link_n;
3673};
3674
3675static void
3676fdi_reduce_ratio(u32 *num, u32 *den)
3677{
3678 while (*num > 0xffffff || *den > 0xffffff) {
3679 *num >>= 1;
3680 *den >>= 1;
3681 }
3682}
3683
2c07245f 3684static void
f2b115e6
AJ		 3685ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3686 int link_clock, struct fdi_m_n *m_n)
2c07245f 3687{
2c07245f
ZW		 3688 m_n->tu = 64; /* default size */
3689
22ed1113
CW		 3690 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3691 m_n->gmch_m = bits_per_pixel * pixel_clock;
3692 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3693 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3694
22ed1113
CW		 3695 m_n->link_m = pixel_clock;
3696 m_n->link_n = link_clock;
2c07245f
ZW		 3697 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3698}
3699
a7615030
CW		 3700static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3701{
72bbe58c
KP		 3702 if (i915_panel_use_ssc >= 0)
3703 return i915_panel_use_ssc != 0;
3704 return dev_priv->lvds_use_ssc
435793df 3705 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3706}
3707
5a354204
JB		 3708/**
3709 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3710 * @crtc: CRTC structure
3b5c78a3 3711 * @mode: requested mode
5a354204
JB		 3712 *
3713 * A pipe may be connected to one or more outputs. Based on the depth of the
3714 * attached framebuffer, choose a good color depth to use on the pipe.
3715 *
3716 * If possible, match the pipe depth to the fb depth. In some cases, this
3717 * isn't ideal, because the connected output supports a lesser or restricted
3718 * set of depths. Resolve that here:
3719 * LVDS typically supports only 6bpc, so clamp down in that case
3720 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3721 * Displays may support a restricted set as well, check EDID and clamp as
3722 * appropriate.
3b5c78a3 3723 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 3724 *
3725 * RETURNS:
3726 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3727 * true if they don't match).
3728 */
3729static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3b5c78a3
AJ		 3730 unsigned int *pipe_bpp,
3731 struct drm_display_mode *mode)
5a354204
JB		 3732{
3733 struct drm_device *dev = crtc->dev;
3734 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 3735 struct drm_connector *connector;
6c2b7c12 3736 struct intel_encoder *intel_encoder;
5a354204
JB		 3737 unsigned int display_bpc = UINT_MAX, bpc;
3738
3739 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 3740 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 3741
3742 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3743 unsigned int lvds_bpc;
3744
3745 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3746 LVDS_A3_POWER_UP)
3747 lvds_bpc = 8;
3748 else
3749 lvds_bpc = 6;
3750
3751 if (lvds_bpc < display_bpc) {
82820490 3752 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 3753 display_bpc = lvds_bpc;
3754 }
3755 continue;
3756 }
3757
3758 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3759 /* Use VBT settings if we have an eDP panel */
3760 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3761
3762 if (edp_bpc < display_bpc) {
82820490 3763 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5a354204
JB		 3764 display_bpc = edp_bpc;
3765 }
3766 continue;
3767 }
3768
3769 /* Not one of the known troublemakers, check the EDID */
3770 list_for_each_entry(connector, &dev->mode_config.connector_list,
3771 head) {
6c2b7c12 3772 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 3773 continue;
3774
62ac41a6
JB		 3775 /* Don't use an invalid EDID bpc value */
3776 if (connector->display_info.bpc &&
3777 connector->display_info.bpc < display_bpc) {
82820490 3778 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 3779 display_bpc = connector->display_info.bpc;
3780 }
3781 }
3782
3783 /*
3784 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3785 * through, clamp it down. (Note: >12bpc will be caught below.)
3786 */
3787 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3788 if (display_bpc > 8 && display_bpc < 12) {
82820490 3789 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 3790 display_bpc = 12;
3791 } else {
82820490 3792 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 3793 display_bpc = 8;
3794 }
3795 }
3796 }
3797
3b5c78a3
AJ		 3798 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3799 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3800 display_bpc = 6;
3801 }
3802
5a354204
JB		 3803 /*
3804 * We could just drive the pipe at the highest bpc all the time and
3805 * enable dithering as needed, but that costs bandwidth. So choose
3806 * the minimum value that expresses the full color range of the fb but
3807 * also stays within the max display bpc discovered above.
3808 */
3809
3810 switch (crtc->fb->depth) {
3811 case 8:
3812 bpc = 8; /* since we go through a colormap */
3813 break;
3814 case 15:
3815 case 16:
3816 bpc = 6; /* min is 18bpp */
3817 break;
3818 case 24:
578393cd 3819 bpc = 8;
5a354204
JB		 3820 break;
3821 case 30:
578393cd 3822 bpc = 10;
5a354204
JB		 3823 break;
3824 case 48:
578393cd 3825 bpc = 12;
5a354204
JB		 3826 break;
3827 default:
3828 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3829 bpc = min((unsigned int)8, display_bpc);
3830 break;
3831 }
3832
578393cd
KP		 3833 display_bpc = min(display_bpc, bpc);
3834
82820490
AJ		 3835 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3836 bpc, display_bpc);
5a354204 3837
578393cd 3838 *pipe_bpp = display_bpc * 3;
5a354204
JB		 3839
3840 return display_bpc != bpc;
3841}
3842
a0c4da24
JB		 3843static int vlv_get_refclk(struct drm_crtc *crtc)
3844{
3845 struct drm_device *dev = crtc->dev;
3846 struct drm_i915_private *dev_priv = dev->dev_private;
3847 int refclk = 27000; /* for DP & HDMI */
3848
3849 return 100000; /* only one validated so far */
3850
3851 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3852 refclk = 96000;
3853 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3854 if (intel_panel_use_ssc(dev_priv))
3855 refclk = 100000;
3856 else
3857 refclk = 96000;
3858 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3859 refclk = 100000;
3860 }
3861
3862 return refclk;
3863}
3864
c65d77d8
JB		 3865static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3866{
3867 struct drm_device *dev = crtc->dev;
3868 struct drm_i915_private *dev_priv = dev->dev_private;
3869 int refclk;
3870
a0c4da24
JB		 3871 if (IS_VALLEYVIEW(dev)) {
3872 refclk = vlv_get_refclk(crtc);
3873 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 3874 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3875 refclk = dev_priv->lvds_ssc_freq * 1000;
3876 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3877 refclk / 1000);
3878 } else if (!IS_GEN2(dev)) {
3879 refclk = 96000;
3880 } else {
3881 refclk = 48000;
3882 }
3883
3884 return refclk;
3885}
3886
3887static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3888 intel_clock_t *clock)
3889{
3890 /* SDVO TV has fixed PLL values depend on its clock range,
3891 this mirrors vbios setting. */
3892 if (adjusted_mode->clock >= 100000
3893 && adjusted_mode->clock < 140500) {
3894 clock->p1 = 2;
3895 clock->p2 = 10;
3896 clock->n = 3;
3897 clock->m1 = 16;
3898 clock->m2 = 8;
3899 } else if (adjusted_mode->clock >= 140500
3900 && adjusted_mode->clock <= 200000) {
3901 clock->p1 = 1;
3902 clock->p2 = 10;
3903 clock->n = 6;
3904 clock->m1 = 12;
3905 clock->m2 = 8;
3906 }
3907}
3908
a7516a05
JB		 3909static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3910 intel_clock_t *clock,
3911 intel_clock_t *reduced_clock)
3912{
3913 struct drm_device *dev = crtc->dev;
3914 struct drm_i915_private *dev_priv = dev->dev_private;
3915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3916 int pipe = intel_crtc->pipe;
3917 u32 fp, fp2 = 0;
3918
3919 if (IS_PINEVIEW(dev)) {
3920 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3921 if (reduced_clock)
3922 fp2 = (1 << reduced_clock->n) << 16 |
3923 reduced_clock->m1 << 8 | reduced_clock->m2;
3924 } else {
3925 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3926 if (reduced_clock)
3927 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3928 reduced_clock->m2;
3929 }
3930
3931 I915_WRITE(FP0(pipe), fp);
3932
3933 intel_crtc->lowfreq_avail = false;
3934 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3935 reduced_clock && i915_powersave) {
3936 I915_WRITE(FP1(pipe), fp2);
3937 intel_crtc->lowfreq_avail = true;
3938 } else {
3939 I915_WRITE(FP1(pipe), fp);
3940 }
3941}
3942
93e537a1
DV		 3943static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3944 struct drm_display_mode *adjusted_mode)
3945{
3946 struct drm_device *dev = crtc->dev;
3947 struct drm_i915_private *dev_priv = dev->dev_private;
3948 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3949 int pipe = intel_crtc->pipe;
284d5df5 3950 u32 temp;
93e537a1
DV		 3951
3952 temp = I915_READ(LVDS);
3953 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3954 if (pipe == 1) {
3955 temp |= LVDS_PIPEB_SELECT;
3956 } else {
3957 temp &= ~LVDS_PIPEB_SELECT;
3958 }
3959 /* set the corresponsding LVDS_BORDER bit */
3960 temp |= dev_priv->lvds_border_bits;
3961 /* Set the B0-B3 data pairs corresponding to whether we're going to
3962 * set the DPLLs for dual-channel mode or not.
3963 */
3964 if (clock->p2 == 7)
3965 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3966 else
3967 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3968
3969 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3970 * appropriately here, but we need to look more thoroughly into how
3971 * panels behave in the two modes.
3972 */
3973 /* set the dithering flag on LVDS as needed */
3974 if (INTEL_INFO(dev)->gen >= 4) {
3975 if (dev_priv->lvds_dither)
3976 temp |= LVDS_ENABLE_DITHER;
3977 else
3978 temp &= ~LVDS_ENABLE_DITHER;
3979 }
284d5df5 3980 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 3981 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 3982 temp |= LVDS_HSYNC_POLARITY;
93e537a1 3983 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 3984 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 3985 I915_WRITE(LVDS, temp);
3986}
3987
a0c4da24
JB		 3988static void vlv_update_pll(struct drm_crtc *crtc,
3989 struct drm_display_mode *mode,
3990 struct drm_display_mode *adjusted_mode,
3991 intel_clock_t *clock, intel_clock_t *reduced_clock,
3992 int refclk, int num_connectors)
3993{
3994 struct drm_device *dev = crtc->dev;
3995 struct drm_i915_private *dev_priv = dev->dev_private;
3996 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3997 int pipe = intel_crtc->pipe;
3998 u32 dpll, mdiv, pdiv;
3999 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4000 bool is_hdmi;
4001
4002 is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4003
4004 bestn = clock->n;
4005 bestm1 = clock->m1;
4006 bestm2 = clock->m2;
4007 bestp1 = clock->p1;
4008 bestp2 = clock->p2;
4009
4010 /* Enable DPIO clock input */
4011 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4012 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4013 I915_WRITE(DPLL(pipe), dpll);
4014 POSTING_READ(DPLL(pipe));
4015
4016 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4017 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4018 mdiv |= ((bestn << DPIO_N_SHIFT));
4019 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4020 mdiv |= (1 << DPIO_K_SHIFT);
4021 mdiv |= DPIO_ENABLE_CALIBRATION;
4022 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4023
4024 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4025
4026 pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4027 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4028 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4029 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4030
4031 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4032
4033 dpll |= DPLL_VCO_ENABLE;
4034 I915_WRITE(DPLL(pipe), dpll);
4035 POSTING_READ(DPLL(pipe));
4036 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4037 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4038
4039 if (is_hdmi) {
4040 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4041
4042 if (temp > 1)
4043 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4044 else
4045 temp = 0;
4046
4047 I915_WRITE(DPLL_MD(pipe), temp);
4048 POSTING_READ(DPLL_MD(pipe));
4049 }
4050
4051 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4052}
4053
eb1cbe48
DV		 4054static void i9xx_update_pll(struct drm_crtc *crtc,
4055 struct drm_display_mode *mode,
4056 struct drm_display_mode *adjusted_mode,
4057 intel_clock_t *clock, intel_clock_t *reduced_clock,
4058 int num_connectors)
4059{
4060 struct drm_device *dev = crtc->dev;
4061 struct drm_i915_private *dev_priv = dev->dev_private;
4062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4063 int pipe = intel_crtc->pipe;
4064 u32 dpll;
4065 bool is_sdvo;
4066
4067 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4068 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4069
4070 dpll = DPLL_VGA_MODE_DIS;
4071
4072 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4073 dpll |= DPLLB_MODE_LVDS;
4074 else
4075 dpll |= DPLLB_MODE_DAC_SERIAL;
4076 if (is_sdvo) {
4077 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4078 if (pixel_multiplier > 1) {
4079 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4080 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4081 }
4082 dpll |= DPLL_DVO_HIGH_SPEED;
4083 }
4084 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4085 dpll |= DPLL_DVO_HIGH_SPEED;
4086
4087 /* compute bitmask from p1 value */
4088 if (IS_PINEVIEW(dev))
4089 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4090 else {
4091 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4092 if (IS_G4X(dev) && reduced_clock)
4093 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4094 }
4095 switch (clock->p2) {
4096 case 5:
4097 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4098 break;
4099 case 7:
4100 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4101 break;
4102 case 10:
4103 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4104 break;
4105 case 14:
4106 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4107 break;
4108 }
4109 if (INTEL_INFO(dev)->gen >= 4)
4110 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4111
4112 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4113 dpll |= PLL_REF_INPUT_TVCLKINBC;
4114 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4115 /* XXX: just matching BIOS for now */
4116 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4117 dpll |= 3;
4118 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4119 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4120 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4121 else
4122 dpll |= PLL_REF_INPUT_DREFCLK;
4123
4124 dpll |= DPLL_VCO_ENABLE;
4125 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4126 POSTING_READ(DPLL(pipe));
4127 udelay(150);
4128
4129 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4130 * This is an exception to the general rule that mode_set doesn't turn
4131 * things on.
4132 */
4133 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4134 intel_update_lvds(crtc, clock, adjusted_mode);
4135
4136 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4137 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4138
4139 I915_WRITE(DPLL(pipe), dpll);
4140
4141 /* Wait for the clocks to stabilize. */
4142 POSTING_READ(DPLL(pipe));
4143 udelay(150);
4144
4145 if (INTEL_INFO(dev)->gen >= 4) {
4146 u32 temp = 0;
4147 if (is_sdvo) {
4148 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4149 if (temp > 1)
4150 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4151 else
4152 temp = 0;
4153 }
4154 I915_WRITE(DPLL_MD(pipe), temp);
4155 } else {
4156 /* The pixel multiplier can only be updated once the
4157 * DPLL is enabled and the clocks are stable.
4158 *
4159 * So write it again.
4160 */
4161 I915_WRITE(DPLL(pipe), dpll);
4162 }
4163}
4164
4165static void i8xx_update_pll(struct drm_crtc *crtc,
4166 struct drm_display_mode *adjusted_mode,
4167 intel_clock_t *clock,
4168 int num_connectors)
4169{
4170 struct drm_device *dev = crtc->dev;
4171 struct drm_i915_private *dev_priv = dev->dev_private;
4172 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4173 int pipe = intel_crtc->pipe;
4174 u32 dpll;
4175
4176 dpll = DPLL_VGA_MODE_DIS;
4177
4178 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4179 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4180 } else {
4181 if (clock->p1 == 2)
4182 dpll |= PLL_P1_DIVIDE_BY_TWO;
4183 else
4184 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4185 if (clock->p2 == 4)
4186 dpll |= PLL_P2_DIVIDE_BY_4;
4187 }
4188
4189 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4190 /* XXX: just matching BIOS for now */
4191 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4192 dpll |= 3;
4193 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4194 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4195 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4196 else
4197 dpll |= PLL_REF_INPUT_DREFCLK;
4198
4199 dpll |= DPLL_VCO_ENABLE;
4200 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4201 POSTING_READ(DPLL(pipe));
4202 udelay(150);
4203
4204 I915_WRITE(DPLL(pipe), dpll);
4205
4206 /* Wait for the clocks to stabilize. */
4207 POSTING_READ(DPLL(pipe));
4208 udelay(150);
4209
4210 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4211 * This is an exception to the general rule that mode_set doesn't turn
4212 * things on.
4213 */
4214 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4215 intel_update_lvds(crtc, clock, adjusted_mode);
4216
4217 /* The pixel multiplier can only be updated once the
4218 * DPLL is enabled and the clocks are stable.
4219 *
4220 * So write it again.
4221 */
4222 I915_WRITE(DPLL(pipe), dpll);
4223}
4224
f564048e
EA		 4225static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4226 struct drm_display_mode *mode,
4227 struct drm_display_mode *adjusted_mode,
4228 int x, int y,
4229 struct drm_framebuffer *old_fb)
79e53945
JB		 4230{
4231 struct drm_device *dev = crtc->dev;
4232 struct drm_i915_private *dev_priv = dev->dev_private;
4233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4234 int pipe = intel_crtc->pipe;
80824003 4235 int plane = intel_crtc->plane;
c751ce4f 4236 int refclk, num_connectors = 0;
652c393a 4237 intel_clock_t clock, reduced_clock;
eb1cbe48
DV		 4238 u32 dspcntr, pipeconf, vsyncshift;
4239 bool ok, has_reduced_clock = false, is_sdvo = false;
4240 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4241 struct intel_encoder *encoder;
d4906093 4242 const intel_limit_t *limit;
5c3b82e2 4243 int ret;
79e53945 4244
6c2b7c12 4245 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4246 switch (encoder->type) {
79e53945
JB		 4247 case INTEL_OUTPUT_LVDS:
4248 is_lvds = true;
4249 break;
4250 case INTEL_OUTPUT_SDVO:
7d57382e 4251 case INTEL_OUTPUT_HDMI:
79e53945 4252 is_sdvo = true;
5eddb70b 4253 if (encoder->needs_tv_clock)
e2f0ba97 4254 is_tv = true;
79e53945 4255 break;
79e53945
JB		 4256 case INTEL_OUTPUT_TVOUT:
4257 is_tv = true;
4258 break;
a4fc5ed6
KP		 4259 case INTEL_OUTPUT_DISPLAYPORT:
4260 is_dp = true;
4261 break;
79e53945 4262 }
43565a06 4263
c751ce4f 4264 num_connectors++;
79e53945
JB		 4265 }
4266
c65d77d8 4267 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4268
d4906093
ML		 4269 /*
4270 * Returns a set of divisors for the desired target clock with the given
4271 * refclk, or FALSE. The returned values represent the clock equation:
4272 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4273 */
1b894b59 4274 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4275 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4276 &clock);
79e53945
JB		 4277 if (!ok) {
4278 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4279 return -EINVAL;
79e53945
JB		 4280 }
4281
cda4b7d3 4282 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4283 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4284
ddc9003c 4285 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4286 /*
4287 * Ensure we match the reduced clock's P to the target clock.
4288 * If the clocks don't match, we can't switch the display clock
4289 * by using the FP0/FP1. In such case we will disable the LVDS
4290 * downclock feature.
4291 */
ddc9003c 4292 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4293 dev_priv->lvds_downclock,
4294 refclk,
cec2f356 4295 &clock,
5eddb70b 4296 &reduced_clock);
7026d4ac
ZW		 4297 }
4298
c65d77d8
JB		 4299 if (is_sdvo && is_tv)
4300 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4301
a7516a05
JB		 4302 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4303 &reduced_clock : NULL);
79e53945 4304
eb1cbe48
DV		 4305 if (IS_GEN2(dev))
4306 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
a0c4da24
JB		 4307 else if (IS_VALLEYVIEW(dev))
4308 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4309 refclk, num_connectors);
79e53945 4310 else
eb1cbe48
DV		 4311 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4312 has_reduced_clock ? &reduced_clock : NULL,
4313 num_connectors);
79e53945
JB		 4314
4315 /* setup pipeconf */
5eddb70b 4316 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4317
4318 /* Set up the display plane register */
4319 dspcntr = DISPPLANE_GAMMA_ENABLE;
4320
929c77fb
EA		 4321 if (pipe == 0)
4322 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4323 else
4324 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4325
a6c45cf0 4326 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4327 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4328 * core speed.
4329 *
4330 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4331 * pipe == 0 check?
4332 */
e70236a8
JB		 4333 if (mode->clock >
4334 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4335 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4336 else
5eddb70b 4337 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4338 }
4339
3b5c78a3
AJ		 4340 /* default to 8bpc */
4341 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4342 if (is_dp) {
4343 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4344 pipeconf |= PIPECONF_BPP_6 |
4345 PIPECONF_DITHER_EN |
4346 PIPECONF_DITHER_TYPE_SP;
4347 }
4348 }
4349
28c97730 4350 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4351 drm_mode_debug_printmodeline(mode);
4352
a7516a05
JB		 4353 if (HAS_PIPE_CXSR(dev)) {
4354 if (intel_crtc->lowfreq_avail) {
28c97730 4355 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4356 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4357 } else {
28c97730 4358 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4359 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4360 }
4361 }
4362
617cf884 4363 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575
DV		 4364 if (!IS_GEN2(dev) &&
4365 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157
KH		 4366 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4367 /* the chip adds 2 halflines automatically */
734b4157 4368 adjusted_mode->crtc_vtotal -= 1;
734b4157 4369 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4370 vsyncshift = adjusted_mode->crtc_hsync_start
4371 - adjusted_mode->crtc_htotal/2;
4372 } else {
617cf884 4373 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4374 vsyncshift = 0;
4375 }
4376
4377 if (!IS_GEN3(dev))
4378 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
734b4157 4379
5eddb70b
CW		 4380 I915_WRITE(HTOTAL(pipe),
4381 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4382 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4383 I915_WRITE(HBLANK(pipe),
4384 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4385 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4386 I915_WRITE(HSYNC(pipe),
4387 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4388 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4389
4390 I915_WRITE(VTOTAL(pipe),
4391 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4392 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4393 I915_WRITE(VBLANK(pipe),
4394 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4395 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4396 I915_WRITE(VSYNC(pipe),
4397 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4398 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 4399
4400 /* pipesrc and dspsize control the size that is scaled from,
4401 * which should always be the user's requested size.
79e53945 4402 */
929c77fb
EA		 4403 I915_WRITE(DSPSIZE(plane),
4404 ((mode->vdisplay - 1) << 16) |
4405 (mode->hdisplay - 1));
4406 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 4407 I915_WRITE(PIPESRC(pipe),
4408 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4409
f564048e
EA		 4410 I915_WRITE(PIPECONF(pipe), pipeconf);
4411 POSTING_READ(PIPECONF(pipe));
929c77fb 4412 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4413
4414 intel_wait_for_vblank(dev, pipe);
4415
f564048e
EA		 4416 I915_WRITE(DSPCNTR(plane), dspcntr);
4417 POSTING_READ(DSPCNTR(plane));
4418
4419 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4420
4421 intel_update_watermarks(dev);
4422
f564048e
EA		 4423 return ret;
4424}
4425
9fb526db
KP		 4426/*
4427 * Initialize reference clocks when the driver loads
4428 */
4429void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4430{
4431 struct drm_i915_private *dev_priv = dev->dev_private;
4432 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4433 struct intel_encoder *encoder;
13d83a67
JB		 4434 u32 temp;
4435 bool has_lvds = false;
199e5d79
KP		 4436 bool has_cpu_edp = false;
4437 bool has_pch_edp = false;
4438 bool has_panel = false;
99eb6a01
KP		 4439 bool has_ck505 = false;
4440 bool can_ssc = false;
13d83a67
JB		 4441
4442 /* We need to take the global config into account */
199e5d79
KP		 4443 list_for_each_entry(encoder, &mode_config->encoder_list,
4444 base.head) {
4445 switch (encoder->type) {
4446 case INTEL_OUTPUT_LVDS:
4447 has_panel = true;
4448 has_lvds = true;
4449 break;
4450 case INTEL_OUTPUT_EDP:
4451 has_panel = true;
4452 if (intel_encoder_is_pch_edp(&encoder->base))
4453 has_pch_edp = true;
4454 else
4455 has_cpu_edp = true;
4456 break;
13d83a67
JB		 4457 }
4458 }
4459
99eb6a01
KP		 4460 if (HAS_PCH_IBX(dev)) {
4461 has_ck505 = dev_priv->display_clock_mode;
4462 can_ssc = has_ck505;
4463 } else {
4464 has_ck505 = false;
4465 can_ssc = true;
4466 }
4467
4468 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4469 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4470 has_ck505);
13d83a67
JB		 4471
4472 /* Ironlake: try to setup display ref clock before DPLL
4473 * enabling. This is only under driver's control after
4474 * PCH B stepping, previous chipset stepping should be
4475 * ignoring this setting.
4476 */
4477 temp = I915_READ(PCH_DREF_CONTROL);
4478 /* Always enable nonspread source */
4479 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4480
99eb6a01
KP		 4481 if (has_ck505)
4482 temp |= DREF_NONSPREAD_CK505_ENABLE;
4483 else
4484 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4485
199e5d79
KP		 4486 if (has_panel) {
4487 temp &= ~DREF_SSC_SOURCE_MASK;
4488 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4489
199e5d79 4490 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4491 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4492 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4493 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4494 } else
4495 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4496
4497 /* Get SSC going before enabling the outputs */
4498 I915_WRITE(PCH_DREF_CONTROL, temp);
4499 POSTING_READ(PCH_DREF_CONTROL);
4500 udelay(200);
4501
13d83a67
JB		 4502 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4503
4504 /* Enable CPU source on CPU attached eDP */
199e5d79 4505 if (has_cpu_edp) {
99eb6a01 4506 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4507 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4508 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4509 }
13d83a67
JB		 4510 else
4511 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4512 } else
4513 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4514
4515 I915_WRITE(PCH_DREF_CONTROL, temp);
4516 POSTING_READ(PCH_DREF_CONTROL);
4517 udelay(200);
4518 } else {
4519 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4520
4521 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4522
4523 /* Turn off CPU output */
4524 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4525
4526 I915_WRITE(PCH_DREF_CONTROL, temp);
4527 POSTING_READ(PCH_DREF_CONTROL);
4528 udelay(200);
4529
4530 /* Turn off the SSC source */
4531 temp &= ~DREF_SSC_SOURCE_MASK;
4532 temp |= DREF_SSC_SOURCE_DISABLE;
4533
4534 /* Turn off SSC1 */
4535 temp &= ~ DREF_SSC1_ENABLE;
4536
13d83a67
JB		 4537 I915_WRITE(PCH_DREF_CONTROL, temp);
4538 POSTING_READ(PCH_DREF_CONTROL);
4539 udelay(200);
4540 }
4541}
4542
d9d444cb
JB		 4543static int ironlake_get_refclk(struct drm_crtc *crtc)
4544{
4545 struct drm_device *dev = crtc->dev;
4546 struct drm_i915_private *dev_priv = dev->dev_private;
4547 struct intel_encoder *encoder;
d9d444cb
JB		 4548 struct intel_encoder *edp_encoder = NULL;
4549 int num_connectors = 0;
4550 bool is_lvds = false;
4551
6c2b7c12 4552 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4553 switch (encoder->type) {
4554 case INTEL_OUTPUT_LVDS:
4555 is_lvds = true;
4556 break;
4557 case INTEL_OUTPUT_EDP:
4558 edp_encoder = encoder;
4559 break;
4560 }
4561 num_connectors++;
4562 }
4563
4564 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4565 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4566 dev_priv->lvds_ssc_freq);
4567 return dev_priv->lvds_ssc_freq * 1000;
4568 }
4569
4570 return 120000;
4571}
4572
f564048e
EA		 4573static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4574 struct drm_display_mode *mode,
4575 struct drm_display_mode *adjusted_mode,
4576 int x, int y,
4577 struct drm_framebuffer *old_fb)
79e53945
JB		 4578{
4579 struct drm_device *dev = crtc->dev;
4580 struct drm_i915_private *dev_priv = dev->dev_private;
4581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4582 int pipe = intel_crtc->pipe;
80824003 4583 int plane = intel_crtc->plane;
c751ce4f 4584 int refclk, num_connectors = 0;
652c393a 4585 intel_clock_t clock, reduced_clock;
5eddb70b 4586 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4587 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4588 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
e3aef172 4589 struct intel_encoder *encoder, *edp_encoder = NULL;
d4906093 4590 const intel_limit_t *limit;
5c3b82e2 4591 int ret;
2c07245f 4592 struct fdi_m_n m_n = {0};
fae14981 4593 u32 temp;
5a354204
JB		 4594 int target_clock, pixel_multiplier, lane, link_bw, factor;
4595 unsigned int pipe_bpp;
4596 bool dither;
e3aef172 4597 bool is_cpu_edp = false, is_pch_edp = false;
79e53945 4598
6c2b7c12 4599 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4600 switch (encoder->type) {
79e53945
JB		 4601 case INTEL_OUTPUT_LVDS:
4602 is_lvds = true;
4603 break;
4604 case INTEL_OUTPUT_SDVO:
7d57382e 4605 case INTEL_OUTPUT_HDMI:
79e53945 4606 is_sdvo = true;
5eddb70b 4607 if (encoder->needs_tv_clock)
e2f0ba97 4608 is_tv = true;
79e53945 4609 break;
79e53945
JB		 4610 case INTEL_OUTPUT_TVOUT:
4611 is_tv = true;
4612 break;
4613 case INTEL_OUTPUT_ANALOG:
4614 is_crt = true;
4615 break;
a4fc5ed6
KP		 4616 case INTEL_OUTPUT_DISPLAYPORT:
4617 is_dp = true;
4618 break;
32f9d658 4619 case INTEL_OUTPUT_EDP:
e3aef172
JB		 4620 is_dp = true;
4621 if (intel_encoder_is_pch_edp(&encoder->base))
4622 is_pch_edp = true;
4623 else
4624 is_cpu_edp = true;
4625 edp_encoder = encoder;
32f9d658 4626 break;
79e53945 4627 }
43565a06 4628
c751ce4f 4629 num_connectors++;
79e53945
JB		 4630 }
4631
d9d444cb 4632 refclk = ironlake_get_refclk(crtc);
79e53945 4633
d4906093
ML		 4634 /*
4635 * Returns a set of divisors for the desired target clock with the given
4636 * refclk, or FALSE. The returned values represent the clock equation:
4637 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4638 */
1b894b59 4639 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4640 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4641 &clock);
79e53945
JB		 4642 if (!ok) {
4643 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4644 return -EINVAL;
79e53945
JB		 4645 }
4646
cda4b7d3 4647 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4648 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4649
ddc9003c 4650 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4651 /*
4652 * Ensure we match the reduced clock's P to the target clock.
4653 * If the clocks don't match, we can't switch the display clock
4654 * by using the FP0/FP1. In such case we will disable the LVDS
4655 * downclock feature.
4656 */
ddc9003c 4657 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4658 dev_priv->lvds_downclock,
4659 refclk,
cec2f356 4660 &clock,
5eddb70b 4661 &reduced_clock);
652c393a 4662 }
61e9653f
DV		 4663
4664 if (is_sdvo && is_tv)
4665 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4666
7026d4ac 4667
2c07245f 4668 /* FDI link */
8febb297
EA		 4669 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4670 lane = 0;
4671 /* CPU eDP doesn't require FDI link, so just set DP M/N
4672 according to current link config */
e3aef172 4673 if (is_cpu_edp) {
e3aef172 4674 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 4675 } else {
8febb297
EA		 4676 /* FDI is a binary signal running at ~2.7GHz, encoding
4677 * each output octet as 10 bits. The actual frequency
4678 * is stored as a divider into a 100MHz clock, and the
4679 * mode pixel clock is stored in units of 1KHz.
4680 * Hence the bw of each lane in terms of the mode signal
4681 * is:
4682 */
4683 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4684 }
58a27471 4685
94bf2ced
DV		 4686 /* [e]DP over FDI requires target mode clock instead of link clock. */
4687 if (edp_encoder)
4688 target_clock = intel_edp_target_clock(edp_encoder, mode);
4689 else if (is_dp)
4690 target_clock = mode->clock;
4691 else
4692 target_clock = adjusted_mode->clock;
4693
8febb297
EA		 4694 /* determine panel color depth */
4695 temp = I915_READ(PIPECONF(pipe));
4696 temp &= ~PIPE_BPC_MASK;
3b5c78a3 4697 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5a354204
JB		 4698 switch (pipe_bpp) {
4699 case 18:
4700 temp |= PIPE_6BPC;
8febb297 4701 break;
5a354204
JB		 4702 case 24:
4703 temp |= PIPE_8BPC;
8febb297 4704 break;
5a354204
JB		 4705 case 30:
4706 temp |= PIPE_10BPC;
8febb297 4707 break;
5a354204
JB		 4708 case 36:
4709 temp |= PIPE_12BPC;
8febb297
EA		 4710 break;
4711 default:
62ac41a6
JB		 4712 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4713 pipe_bpp);
5a354204
JB		 4714 temp |= PIPE_8BPC;
4715 pipe_bpp = 24;
4716 break;
8febb297 4717 }
77ffb597 4718
5a354204
JB		 4719 intel_crtc->bpp = pipe_bpp;
4720 I915_WRITE(PIPECONF(pipe), temp);
4721
8febb297
EA		 4722 if (!lane) {
4723 /*
4724 * Account for spread spectrum to avoid
4725 * oversubscribing the link. Max center spread
4726 * is 2.5%; use 5% for safety's sake.
4727 */
5a354204 4728 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 4729 lane = bps / (link_bw * 8) + 1;
5eb08b69 4730 }
2c07245f 4731
8febb297
EA		 4732 intel_crtc->fdi_lanes = lane;
4733
4734 if (pixel_multiplier > 1)
4735 link_bw *= pixel_multiplier;
5a354204
JB		 4736 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4737 &m_n);
8febb297 4738
a07d6787
EA		 4739 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4740 if (has_reduced_clock)
4741 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4742 reduced_clock.m2;
79e53945 4743
c1858123 4744 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4745 factor = 21;
4746 if (is_lvds) {
4747 if ((intel_panel_use_ssc(dev_priv) &&
4748 dev_priv->lvds_ssc_freq == 100) ||
4749 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4750 factor = 25;
4751 } else if (is_sdvo && is_tv)
4752 factor = 20;
c1858123 4753
cb0e0931 4754 if (clock.m < factor * clock.n)
8febb297 4755 fp |= FP_CB_TUNE;
2c07245f 4756
5eddb70b 4757 dpll = 0;
2c07245f 4758
a07d6787
EA		 4759 if (is_lvds)
4760 dpll |= DPLLB_MODE_LVDS;
4761 else
4762 dpll |= DPLLB_MODE_DAC_SERIAL;
4763 if (is_sdvo) {
4764 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4765 if (pixel_multiplier > 1) {
4766 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4767 }
a07d6787
EA		 4768 dpll |= DPLL_DVO_HIGH_SPEED;
4769 }
e3aef172 4770 if (is_dp && !is_cpu_edp)
a07d6787 4771 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4772
a07d6787
EA		 4773 /* compute bitmask from p1 value */
4774 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4775 /* also FPA1 */
4776 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4777
4778 switch (clock.p2) {
4779 case 5:
4780 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4781 break;
4782 case 7:
4783 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4784 break;
4785 case 10:
4786 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4787 break;
4788 case 14:
4789 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4790 break;
79e53945
JB		 4791 }
4792
43565a06
KH		 4793 if (is_sdvo && is_tv)
4794 dpll |= PLL_REF_INPUT_TVCLKINBC;
4795 else if (is_tv)
79e53945 4796 /* XXX: just matching BIOS for now */
43565a06 4797 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4798 dpll |= 3;
a7615030 4799 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4800 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4801 else
4802 dpll |= PLL_REF_INPUT_DREFCLK;
4803
4804 /* setup pipeconf */
5eddb70b 4805 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4806
4807 /* Set up the display plane register */
4808 dspcntr = DISPPLANE_GAMMA_ENABLE;
4809
f7cb34d4 4810 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 4811 drm_mode_debug_printmodeline(mode);
4812
9d82aa17
ED		 4813 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4814 * pre-Haswell/LPT generation */
4815 if (HAS_PCH_LPT(dev)) {
4816 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4817 pipe);
4818 } else if (!is_cpu_edp) {
ee7b9f93 4819 struct intel_pch_pll *pll;
4b645f14 4820
ee7b9f93
JB		 4821 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4822 if (pll == NULL) {
4823 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4824 pipe);
4b645f14
JB		 4825 return -EINVAL;
4826 }
ee7b9f93
JB		 4827 } else
4828 intel_put_pch_pll(intel_crtc);
79e53945
JB		 4829
4830 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4831 * This is an exception to the general rule that mode_set doesn't turn
4832 * things on.
4833 */
4834 if (is_lvds) {
fae14981 4835 temp = I915_READ(PCH_LVDS);
5eddb70b 4836 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 4837 if (HAS_PCH_CPT(dev)) {
4838 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 4839 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 4840 } else {
4841 if (pipe == 1)
4842 temp |= LVDS_PIPEB_SELECT;
4843 else
4844 temp &= ~LVDS_PIPEB_SELECT;
4845 }
4b645f14 4846
a3e17eb8 4847 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4848 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4849 /* Set the B0-B3 data pairs corresponding to whether we're going to
4850 * set the DPLLs for dual-channel mode or not.
4851 */
4852 if (clock.p2 == 7)
5eddb70b 4853 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4854 else
5eddb70b 4855 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4856
4857 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4858 * appropriately here, but we need to look more thoroughly into how
4859 * panels behave in the two modes.
4860 */
284d5df5 4861 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 4862 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4863 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 4864 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4865 temp |= LVDS_VSYNC_POLARITY;
fae14981 4866 I915_WRITE(PCH_LVDS, temp);
79e53945 4867 }
434ed097 4868
8febb297
EA		 4869 pipeconf &= ~PIPECONF_DITHER_EN;
4870 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 4871 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 4872 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 4873 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 4874 }
e3aef172 4875 if (is_dp && !is_cpu_edp) {
a4fc5ed6 4876 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 4877 } else {
8db9d77b 4878 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 4879 I915_WRITE(TRANSDATA_M1(pipe), 0);
4880 I915_WRITE(TRANSDATA_N1(pipe), 0);
4881 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4882 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 4883 }
79e53945 4884
ee7b9f93
JB		 4885 if (intel_crtc->pch_pll) {
4886 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 4887
32f9d658 4888 /* Wait for the clocks to stabilize. */
ee7b9f93 4889 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 4890 udelay(150);
4891
8febb297
EA		 4892 /* The pixel multiplier can only be updated once the
4893 * DPLL is enabled and the clocks are stable.
4894 *
4895 * So write it again.
4896 */
ee7b9f93 4897 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 4898 }
79e53945 4899
5eddb70b 4900 intel_crtc->lowfreq_avail = false;
ee7b9f93 4901 if (intel_crtc->pch_pll) {
4b645f14 4902 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 4903 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 4904 intel_crtc->lowfreq_avail = true;
4b645f14 4905 } else {
ee7b9f93 4906 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 4907 }
4908 }
4909
617cf884 4910 pipeconf &= ~PIPECONF_INTERLACE_MASK;
734b4157 4911 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5def474e 4912 pipeconf |= PIPECONF_INTERLACED_ILK;
734b4157 4913 /* the chip adds 2 halflines automatically */
734b4157 4914 adjusted_mode->crtc_vtotal -= 1;
734b4157 4915 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4916 I915_WRITE(VSYNCSHIFT(pipe),
4917 adjusted_mode->crtc_hsync_start
4918 - adjusted_mode->crtc_htotal/2);
4919 } else {
617cf884 4920 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4921 I915_WRITE(VSYNCSHIFT(pipe), 0);
4922 }
734b4157 4923
5eddb70b
CW		 4924 I915_WRITE(HTOTAL(pipe),
4925 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4926 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4927 I915_WRITE(HBLANK(pipe),
4928 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4929 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4930 I915_WRITE(HSYNC(pipe),
4931 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4932 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4933
4934 I915_WRITE(VTOTAL(pipe),
4935 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4936 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4937 I915_WRITE(VBLANK(pipe),
4938 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4939 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4940 I915_WRITE(VSYNC(pipe),
4941 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4942 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 4943
8febb297
EA		 4944 /* pipesrc controls the size that is scaled from, which should
4945 * always be the user's requested size.
79e53945 4946 */
5eddb70b
CW		 4947 I915_WRITE(PIPESRC(pipe),
4948 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4949
8febb297
EA		 4950 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4951 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4952 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4953 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 4954
e3aef172 4955 if (is_cpu_edp)
8febb297 4956 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 4957
5eddb70b
CW		 4958 I915_WRITE(PIPECONF(pipe), pipeconf);
4959 POSTING_READ(PIPECONF(pipe));
79e53945 4960
9d0498a2 4961 intel_wait_for_vblank(dev, pipe);
79e53945 4962
5eddb70b 4963 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 4964 POSTING_READ(DSPCNTR(plane));
79e53945 4965
5c3b82e2 4966 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 4967
4968 intel_update_watermarks(dev);
4969
1f8eeabf
ED		 4970 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
4971
1f803ee5 4972 return ret;
79e53945
JB		 4973}
4974
f564048e
EA		 4975static int intel_crtc_mode_set(struct drm_crtc *crtc,
4976 struct drm_display_mode *mode,
4977 struct drm_display_mode *adjusted_mode,
4978 int x, int y,
4979 struct drm_framebuffer *old_fb)
4980{
4981 struct drm_device *dev = crtc->dev;
4982 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 4983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4984 int pipe = intel_crtc->pipe;
f564048e
EA		 4985 int ret;
4986
0b701d27 4987 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 4988
f564048e
EA		 4989 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
4990 x, y, old_fb);
79e53945 4991 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 4992
d8e70a25
JB		 4993 if (ret)
4994 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4995 else
4996 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
120eced9 4997
1f803ee5 4998 return ret;
79e53945
JB		 4999}
5000
3a9627f4
WF		 5001static bool intel_eld_uptodate(struct drm_connector *connector,
5002 int reg_eldv, uint32_t bits_eldv,
5003 int reg_elda, uint32_t bits_elda,
5004 int reg_edid)
5005{
5006 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5007 uint8_t *eld = connector->eld;
5008 uint32_t i;
5009
5010 i = I915_READ(reg_eldv);
5011 i &= bits_eldv;
5012
5013 if (!eld[0])
5014 return !i;
5015
5016 if (!i)
5017 return false;
5018
5019 i = I915_READ(reg_elda);
5020 i &= ~bits_elda;
5021 I915_WRITE(reg_elda, i);
5022
5023 for (i = 0; i < eld[2]; i++)
5024 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5025 return false;
5026
5027 return true;
5028}
5029
e0dac65e
WF		 5030static void g4x_write_eld(struct drm_connector *connector,
5031 struct drm_crtc *crtc)
5032{
5033 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5034 uint8_t *eld = connector->eld;
5035 uint32_t eldv;
5036 uint32_t len;
5037 uint32_t i;
5038
5039 i = I915_READ(G4X_AUD_VID_DID);
5040
5041 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5042 eldv = G4X_ELDV_DEVCL_DEVBLC;
5043 else
5044 eldv = G4X_ELDV_DEVCTG;
5045
3a9627f4
WF		 5046 if (intel_eld_uptodate(connector,
5047 G4X_AUD_CNTL_ST, eldv,
5048 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5049 G4X_HDMIW_HDMIEDID))
5050 return;
5051
e0dac65e
WF		 5052 i = I915_READ(G4X_AUD_CNTL_ST);
5053 i &= ~(eldv | G4X_ELD_ADDR);
5054 len = (i >> 9) & 0x1f; /* ELD buffer size */
5055 I915_WRITE(G4X_AUD_CNTL_ST, i);
5056
5057 if (!eld[0])
5058 return;
5059
5060 len = min_t(uint8_t, eld[2], len);
5061 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5062 for (i = 0; i < len; i++)
5063 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5064
5065 i = I915_READ(G4X_AUD_CNTL_ST);
5066 i |= eldv;
5067 I915_WRITE(G4X_AUD_CNTL_ST, i);
5068}
5069
5070static void ironlake_write_eld(struct drm_connector *connector,
5071 struct drm_crtc *crtc)
5072{
5073 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5074 uint8_t *eld = connector->eld;
5075 uint32_t eldv;
5076 uint32_t i;
5077 int len;
5078 int hdmiw_hdmiedid;
b6daa025 5079 int aud_config;
e0dac65e
WF		 5080 int aud_cntl_st;
5081 int aud_cntrl_st2;
5082
b3f33cbf 5083 if (HAS_PCH_IBX(connector->dev)) {
1202b4c6 5084 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
b6daa025 5085 aud_config = IBX_AUD_CONFIG_A;
1202b4c6
WF		 5086 aud_cntl_st = IBX_AUD_CNTL_ST_A;
5087 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5088 } else {
1202b4c6 5089 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
b6daa025 5090 aud_config = CPT_AUD_CONFIG_A;
1202b4c6
WF		 5091 aud_cntl_st = CPT_AUD_CNTL_ST_A;
5092 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5093 }
5094
5095 i = to_intel_crtc(crtc)->pipe;
5096 hdmiw_hdmiedid += i * 0x100;
5097 aud_cntl_st += i * 0x100;
b6daa025 5098 aud_config += i * 0x100;
e0dac65e
WF		 5099
5100 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
5101
5102 i = I915_READ(aud_cntl_st);
5103 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
5104 if (!i) {
5105 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5106 /* operate blindly on all ports */
1202b4c6
WF		 5107 eldv = IBX_ELD_VALIDB;
5108 eldv |= IBX_ELD_VALIDB << 4;
5109 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5110 } else {
5111 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5112 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5113 }
5114
3a9627f4
WF		 5115 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5116 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5117 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5118 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5119 } else
5120 I915_WRITE(aud_config, 0);
e0dac65e 5121
3a9627f4
WF		 5122 if (intel_eld_uptodate(connector,
5123 aud_cntrl_st2, eldv,
5124 aud_cntl_st, IBX_ELD_ADDRESS,
5125 hdmiw_hdmiedid))
5126 return;
5127
e0dac65e
WF		 5128 i = I915_READ(aud_cntrl_st2);
5129 i &= ~eldv;
5130 I915_WRITE(aud_cntrl_st2, i);
5131
5132 if (!eld[0])
5133 return;
5134
e0dac65e 5135 i = I915_READ(aud_cntl_st);
1202b4c6 5136 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 5137 I915_WRITE(aud_cntl_st, i);
5138
5139 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5140 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5141 for (i = 0; i < len; i++)
5142 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5143
5144 i = I915_READ(aud_cntrl_st2);
5145 i |= eldv;
5146 I915_WRITE(aud_cntrl_st2, i);
5147}
5148
5149void intel_write_eld(struct drm_encoder *encoder,
5150 struct drm_display_mode *mode)
5151{
5152 struct drm_crtc *crtc = encoder->crtc;
5153 struct drm_connector *connector;
5154 struct drm_device *dev = encoder->dev;
5155 struct drm_i915_private *dev_priv = dev->dev_private;
5156
5157 connector = drm_select_eld(encoder, mode);
5158 if (!connector)
5159 return;
5160
5161 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5162 connector->base.id,
5163 drm_get_connector_name(connector),
5164 connector->encoder->base.id,
5165 drm_get_encoder_name(connector->encoder));
5166
5167 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5168
5169 if (dev_priv->display.write_eld)
5170 dev_priv->display.write_eld(connector, crtc);
5171}
5172
79e53945
JB		 5173/** Loads the palette/gamma unit for the CRTC with the prepared values */
5174void intel_crtc_load_lut(struct drm_crtc *crtc)
5175{
5176 struct drm_device *dev = crtc->dev;
5177 struct drm_i915_private *dev_priv = dev->dev_private;
5178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5179 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5180 int i;
5181
5182 /* The clocks have to be on to load the palette. */
aed3f09d 5183 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 5184 return;
5185
f2b115e6 5186 /* use legacy palette for Ironlake */
bad720ff 5187 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5188 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5189
79e53945
JB		 5190 for (i = 0; i < 256; i++) {
5191 I915_WRITE(palreg + 4 * i,
5192 (intel_crtc->lut_r[i] << 16) |
5193 (intel_crtc->lut_g[i] << 8) |
5194 intel_crtc->lut_b[i]);
5195 }
5196}
5197
560b85bb
CW		 5198static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5199{
5200 struct drm_device *dev = crtc->dev;
5201 struct drm_i915_private *dev_priv = dev->dev_private;
5202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5203 bool visible = base != 0;
5204 u32 cntl;
5205
5206 if (intel_crtc->cursor_visible == visible)
5207 return;
5208
9db4a9c7 5209 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5210 if (visible) {
5211 /* On these chipsets we can only modify the base whilst
5212 * the cursor is disabled.
5213 */
9db4a9c7 5214 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5215
5216 cntl &= ~(CURSOR_FORMAT_MASK);
5217 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5218 cntl |= CURSOR_ENABLE |
5219 CURSOR_GAMMA_ENABLE |
5220 CURSOR_FORMAT_ARGB;
5221 } else
5222 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5223 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5224
5225 intel_crtc->cursor_visible = visible;
5226}
5227
5228static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5229{
5230 struct drm_device *dev = crtc->dev;
5231 struct drm_i915_private *dev_priv = dev->dev_private;
5232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5233 int pipe = intel_crtc->pipe;
5234 bool visible = base != 0;
5235
5236 if (intel_crtc->cursor_visible != visible) {
548f245b 5237 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5238 if (base) {
5239 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5240 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5241 cntl |= pipe << 28; /* Connect to correct pipe */
5242 } else {
5243 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5244 cntl |= CURSOR_MODE_DISABLE;
5245 }
9db4a9c7 5246 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5247
5248 intel_crtc->cursor_visible = visible;
5249 }
5250 /* and commit changes on next vblank */
9db4a9c7 5251 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5252}
5253
65a21cd6
JB		 5254static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5255{
5256 struct drm_device *dev = crtc->dev;
5257 struct drm_i915_private *dev_priv = dev->dev_private;
5258 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5259 int pipe = intel_crtc->pipe;
5260 bool visible = base != 0;
5261
5262 if (intel_crtc->cursor_visible != visible) {
5263 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5264 if (base) {
5265 cntl &= ~CURSOR_MODE;
5266 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5267 } else {
5268 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5269 cntl |= CURSOR_MODE_DISABLE;
5270 }
5271 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5272
5273 intel_crtc->cursor_visible = visible;
5274 }
5275 /* and commit changes on next vblank */
5276 I915_WRITE(CURBASE_IVB(pipe), base);
5277}
5278
cda4b7d3 5279/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5280static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5281 bool on)
cda4b7d3
CW		 5282{
5283 struct drm_device *dev = crtc->dev;
5284 struct drm_i915_private *dev_priv = dev->dev_private;
5285 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5286 int pipe = intel_crtc->pipe;
5287 int x = intel_crtc->cursor_x;
5288 int y = intel_crtc->cursor_y;
560b85bb 5289 u32 base, pos;
cda4b7d3
CW		 5290 bool visible;
5291
5292 pos = 0;
5293
6b383a7f 5294 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5295 base = intel_crtc->cursor_addr;
5296 if (x > (int) crtc->fb->width)
5297 base = 0;
5298
5299 if (y > (int) crtc->fb->height)
5300 base = 0;
5301 } else
5302 base = 0;
5303
5304 if (x < 0) {
5305 if (x + intel_crtc->cursor_width < 0)
5306 base = 0;
5307
5308 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5309 x = -x;
5310 }
5311 pos |= x << CURSOR_X_SHIFT;
5312
5313 if (y < 0) {
5314 if (y + intel_crtc->cursor_height < 0)
5315 base = 0;
5316
5317 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5318 y = -y;
5319 }
5320 pos |= y << CURSOR_Y_SHIFT;
5321
5322 visible = base != 0;
560b85bb 5323 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5324 return;
5325
0cd83aa9 5326 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 5327 I915_WRITE(CURPOS_IVB(pipe), pos);
5328 ivb_update_cursor(crtc, base);
5329 } else {
5330 I915_WRITE(CURPOS(pipe), pos);
5331 if (IS_845G(dev) || IS_I865G(dev))
5332 i845_update_cursor(crtc, base);
5333 else
5334 i9xx_update_cursor(crtc, base);
5335 }
cda4b7d3
CW		 5336}
5337
79e53945 5338static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5339 struct drm_file *file,
79e53945
JB		 5340 uint32_t handle,
5341 uint32_t width, uint32_t height)
5342{
5343 struct drm_device *dev = crtc->dev;
5344 struct drm_i915_private *dev_priv = dev->dev_private;
5345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5346 struct drm_i915_gem_object *obj;
cda4b7d3 5347 uint32_t addr;
3f8bc370 5348 int ret;
79e53945 5349
28c97730 5350 DRM_DEBUG_KMS("\n");
79e53945
JB		 5351
5352 /* if we want to turn off the cursor ignore width and height */
5353 if (!handle) {
28c97730 5354 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5355 addr = 0;
05394f39 5356 obj = NULL;
5004417d 5357 mutex_lock(&dev->struct_mutex);
3f8bc370 5358 goto finish;
79e53945
JB		 5359 }
5360
5361 /* Currently we only support 64x64 cursors */
5362 if (width != 64 || height != 64) {
5363 DRM_ERROR("we currently only support 64x64 cursors\n");
5364 return -EINVAL;
5365 }
5366
05394f39 5367 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5368 if (&obj->base == NULL)
79e53945
JB		 5369 return -ENOENT;
5370
05394f39 5371 if (obj->base.size < width * height * 4) {
79e53945 5372 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5373 ret = -ENOMEM;
5374 goto fail;
79e53945
JB		 5375 }
5376
71acb5eb 5377 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5378 mutex_lock(&dev->struct_mutex);
b295d1b6 5379 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5380 if (obj->tiling_mode) {
5381 DRM_ERROR("cursor cannot be tiled\n");
5382 ret = -EINVAL;
5383 goto fail_locked;
5384 }
5385
2da3b9b9 5386 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 5387 if (ret) {
5388 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 5389 goto fail_locked;
e7b526bb
CW		 5390 }
5391
d9e86c0e
CW		 5392 ret = i915_gem_object_put_fence(obj);
5393 if (ret) {
2da3b9b9 5394 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 5395 goto fail_unpin;
5396 }
5397
05394f39 5398 addr = obj->gtt_offset;
71acb5eb 5399 } else {
6eeefaf3 5400 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5401 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5402 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5403 align);
71acb5eb
DA		 5404 if (ret) {
5405 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5406 goto fail_locked;
71acb5eb 5407 }
05394f39 5408 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5409 }
5410
a6c45cf0 5411 if (IS_GEN2(dev))
14b60391
JB		 5412 I915_WRITE(CURSIZE, (height << 12) | width);
5413
3f8bc370 5414 finish:
3f8bc370 5415 if (intel_crtc->cursor_bo) {
b295d1b6 5416 if (dev_priv->info->cursor_needs_physical) {
05394f39 5417 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5418 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5419 } else
5420 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5421 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5422 }
80824003 5423
7f9872e0 5424 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5425
5426 intel_crtc->cursor_addr = addr;
05394f39 5427 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5428 intel_crtc->cursor_width = width;
5429 intel_crtc->cursor_height = height;
5430
6b383a7f 5431 intel_crtc_update_cursor(crtc, true);
3f8bc370 5432
79e53945 5433 return 0;
e7b526bb 5434fail_unpin:
05394f39 5435 i915_gem_object_unpin(obj);
7f9872e0 5436fail_locked:
34b8686e 5437 mutex_unlock(&dev->struct_mutex);
bc9025bd 5438fail:
05394f39 5439 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5440 return ret;
79e53945
JB		 5441}
5442
5443static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5444{
79e53945 5445 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5446
cda4b7d3
CW		 5447 intel_crtc->cursor_x = x;
5448 intel_crtc->cursor_y = y;
652c393a 5449
6b383a7f 5450 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5451
5452 return 0;
5453}
5454
5455/** Sets the color ramps on behalf of RandR */
5456void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5457 u16 blue, int regno)
5458{
5459 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5460
5461 intel_crtc->lut_r[regno] = red >> 8;
5462 intel_crtc->lut_g[regno] = green >> 8;
5463 intel_crtc->lut_b[regno] = blue >> 8;
5464}
5465
b8c00ac5
DA		 5466void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5467 u16 *blue, int regno)
5468{
5469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5470
5471 *red = intel_crtc->lut_r[regno] << 8;
5472 *green = intel_crtc->lut_g[regno] << 8;
5473 *blue = intel_crtc->lut_b[regno] << 8;
5474}
5475
79e53945 5476static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5477 u16 *blue, uint32_t start, uint32_t size)
79e53945 5478{
7203425a 5479 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5480 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5481
7203425a 5482 for (i = start; i < end; i++) {
79e53945
JB		 5483 intel_crtc->lut_r[i] = red[i] >> 8;
5484 intel_crtc->lut_g[i] = green[i] >> 8;
5485 intel_crtc->lut_b[i] = blue[i] >> 8;
5486 }
5487
5488 intel_crtc_load_lut(crtc);
5489}
5490
5491/**
5492 * Get a pipe with a simple mode set on it for doing load-based monitor
5493 * detection.
5494 *
5495 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5496 * its requirements. The pipe will be connected to no other encoders.
79e53945 5497 *
c751ce4f 5498 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5499 * configured for it. In the future, it could choose to temporarily disable
5500 * some outputs to free up a pipe for its use.
5501 *
5502 * \return crtc, or NULL if no pipes are available.
5503 */
5504
5505/* VESA 640x480x72Hz mode to set on the pipe */
5506static struct drm_display_mode load_detect_mode = {
5507 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5508 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5509};
5510
d2dff872
CW		 5511static struct drm_framebuffer *
5512intel_framebuffer_create(struct drm_device *dev,
308e5bcb 5513 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 5514 struct drm_i915_gem_object *obj)
5515{
5516 struct intel_framebuffer *intel_fb;
5517 int ret;
5518
5519 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5520 if (!intel_fb) {
5521 drm_gem_object_unreference_unlocked(&obj->base);
5522 return ERR_PTR(-ENOMEM);
5523 }
5524
5525 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5526 if (ret) {
5527 drm_gem_object_unreference_unlocked(&obj->base);
5528 kfree(intel_fb);
5529 return ERR_PTR(ret);
5530 }
5531
5532 return &intel_fb->base;
5533}
5534
5535static u32
5536intel_framebuffer_pitch_for_width(int width, int bpp)
5537{
5538 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5539 return ALIGN(pitch, 64);
5540}
5541
5542static u32
5543intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5544{
5545 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5546 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5547}
5548
5549static struct drm_framebuffer *
5550intel_framebuffer_create_for_mode(struct drm_device *dev,
5551 struct drm_display_mode *mode,
5552 int depth, int bpp)
5553{
5554 struct drm_i915_gem_object *obj;
308e5bcb 5555 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 5556
5557 obj = i915_gem_alloc_object(dev,
5558 intel_framebuffer_size_for_mode(mode, bpp));
5559 if (obj == NULL)
5560 return ERR_PTR(-ENOMEM);
5561
5562 mode_cmd.width = mode->hdisplay;
5563 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 5564 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5565 bpp);
5ca0c34a 5566 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 5567
5568 return intel_framebuffer_create(dev, &mode_cmd, obj);
5569}
5570
5571static struct drm_framebuffer *
5572mode_fits_in_fbdev(struct drm_device *dev,
5573 struct drm_display_mode *mode)
5574{
5575 struct drm_i915_private *dev_priv = dev->dev_private;
5576 struct drm_i915_gem_object *obj;
5577 struct drm_framebuffer *fb;
5578
5579 if (dev_priv->fbdev == NULL)
5580 return NULL;
5581
5582 obj = dev_priv->fbdev->ifb.obj;
5583 if (obj == NULL)
5584 return NULL;
5585
5586 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 5587 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5588 fb->bits_per_pixel))
d2dff872
CW		 5589 return NULL;
5590
01f2c773 5591 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 5592 return NULL;
5593
5594 return fb;
5595}
5596
7173188d
CW		 5597bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5598 struct drm_connector *connector,
5599 struct drm_display_mode *mode,
8261b191 5600 struct intel_load_detect_pipe *old)
79e53945
JB		 5601{
5602 struct intel_crtc *intel_crtc;
5603 struct drm_crtc *possible_crtc;
4ef69c7a 5604 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5605 struct drm_crtc *crtc = NULL;
5606 struct drm_device *dev = encoder->dev;
d2dff872 5607 struct drm_framebuffer *old_fb;
79e53945
JB		 5608 int i = -1;
5609
d2dff872
CW		 5610 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5611 connector->base.id, drm_get_connector_name(connector),
5612 encoder->base.id, drm_get_encoder_name(encoder));
5613
79e53945
JB		 5614 /*
5615 * Algorithm gets a little messy:
7a5e4805 5616 *
79e53945
JB		 5617 * - if the connector already has an assigned crtc, use it (but make
5618 * sure it's on first)
7a5e4805 5619 *
79e53945
JB		 5620 * - try to find the first unused crtc that can drive this connector,
5621 * and use that if we find one
79e53945
JB		 5622 */
5623
5624 /* See if we already have a CRTC for this connector */
5625 if (encoder->crtc) {
5626 crtc = encoder->crtc;
8261b191 5627
79e53945 5628 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5629 old->dpms_mode = intel_crtc->dpms_mode;
5630 old->load_detect_temp = false;
5631
5632 /* Make sure the crtc and connector are running */
79e53945 5633 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 5634 struct drm_encoder_helper_funcs *encoder_funcs;
5635 struct drm_crtc_helper_funcs *crtc_funcs;
5636
79e53945
JB		 5637 crtc_funcs = crtc->helper_private;
5638 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 5639
5640 encoder_funcs = encoder->helper_private;
79e53945
JB		 5641 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5642 }
8261b191 5643
7173188d 5644 return true;
79e53945
JB		 5645 }
5646
5647 /* Find an unused one (if possible) */
5648 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5649 i++;
5650 if (!(encoder->possible_crtcs & (1 << i)))
5651 continue;
5652 if (!possible_crtc->enabled) {
5653 crtc = possible_crtc;
5654 break;
5655 }
79e53945
JB		 5656 }
5657
5658 /*
5659 * If we didn't find an unused CRTC, don't use any.
5660 */
5661 if (!crtc) {
7173188d
CW		 5662 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5663 return false;
79e53945
JB		 5664 }
5665
5666 encoder->crtc = crtc;
c1c43977 5667 connector->encoder = encoder;
79e53945
JB		 5668
5669 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5670 old->dpms_mode = intel_crtc->dpms_mode;
5671 old->load_detect_temp = true;
d2dff872 5672 old->release_fb = NULL;
79e53945 5673
6492711d
CW		 5674 if (!mode)
5675 mode = &load_detect_mode;
79e53945 5676
d2dff872
CW		 5677 old_fb = crtc->fb;
5678
5679 /* We need a framebuffer large enough to accommodate all accesses
5680 * that the plane may generate whilst we perform load detection.
5681 * We can not rely on the fbcon either being present (we get called
5682 * during its initialisation to detect all boot displays, or it may
5683 * not even exist) or that it is large enough to satisfy the
5684 * requested mode.
5685 */
5686 crtc->fb = mode_fits_in_fbdev(dev, mode);
5687 if (crtc->fb == NULL) {
5688 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5689 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5690 old->release_fb = crtc->fb;
5691 } else
5692 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5693 if (IS_ERR(crtc->fb)) {
5694 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5695 crtc->fb = old_fb;
5696 return false;
79e53945 5697 }
79e53945 5698
d2dff872 5699 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 5700 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5701 if (old->release_fb)
5702 old->release_fb->funcs->destroy(old->release_fb);
5703 crtc->fb = old_fb;
6492711d 5704 return false;
79e53945 5705 }
7173188d 5706
79e53945 5707 /* let the connector get through one full cycle before testing */
9d0498a2 5708 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5709
7173188d 5710 return true;
79e53945
JB		 5711}
5712
c1c43977 5713void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 5714 struct drm_connector *connector,
5715 struct intel_load_detect_pipe *old)
79e53945 5716{
4ef69c7a 5717 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5718 struct drm_device *dev = encoder->dev;
5719 struct drm_crtc *crtc = encoder->crtc;
5720 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5721 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5722
d2dff872
CW		 5723 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5724 connector->base.id, drm_get_connector_name(connector),
5725 encoder->base.id, drm_get_encoder_name(encoder));
5726
8261b191 5727 if (old->load_detect_temp) {
c1c43977 5728 connector->encoder = NULL;
79e53945 5729 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 5730
5731 if (old->release_fb)
5732 old->release_fb->funcs->destroy(old->release_fb);
5733
0622a53c 5734 return;
79e53945
JB		 5735 }
5736
c751ce4f 5737 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 5738 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5739 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 5740 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 5741 }
5742}
5743
5744/* Returns the clock of the currently programmed mode of the given pipe. */
5745static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5746{
5747 struct drm_i915_private *dev_priv = dev->dev_private;
5748 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5749 int pipe = intel_crtc->pipe;
548f245b 5750 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5751 u32 fp;
5752 intel_clock_t clock;
5753
5754 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5755 fp = I915_READ(FP0(pipe));
79e53945 5756 else
39adb7a5 5757 fp = I915_READ(FP1(pipe));
79e53945
JB		 5758
5759 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5760 if (IS_PINEVIEW(dev)) {
5761 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5762 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5763 } else {
5764 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5765 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5766 }
5767
a6c45cf0 5768 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5769 if (IS_PINEVIEW(dev))
5770 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5771 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5772 else
5773 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5774 DPLL_FPA01_P1_POST_DIV_SHIFT);
5775
5776 switch (dpll & DPLL_MODE_MASK) {
5777 case DPLLB_MODE_DAC_SERIAL:
5778 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5779 5 : 10;
5780 break;
5781 case DPLLB_MODE_LVDS:
5782 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5783 7 : 14;
5784 break;
5785 default:
28c97730 5786 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5787 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5788 return 0;
5789 }
5790
5791 /* XXX: Handle the 100Mhz refclk */
2177832f 5792 intel_clock(dev, 96000, &clock);
79e53945
JB		 5793 } else {
5794 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5795
5796 if (is_lvds) {
5797 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5798 DPLL_FPA01_P1_POST_DIV_SHIFT);
5799 clock.p2 = 14;
5800
5801 if ((dpll & PLL_REF_INPUT_MASK) ==
5802 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5803 /* XXX: might not be 66MHz */
2177832f 5804 intel_clock(dev, 66000, &clock);
79e53945 5805 } else
2177832f 5806 intel_clock(dev, 48000, &clock);
79e53945
JB		 5807 } else {
5808 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5809 clock.p1 = 2;
5810 else {
5811 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5812 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5813 }
5814 if (dpll & PLL_P2_DIVIDE_BY_4)
5815 clock.p2 = 4;
5816 else
5817 clock.p2 = 2;
5818
2177832f 5819 intel_clock(dev, 48000, &clock);
79e53945
JB		 5820 }
5821 }
5822
5823 /* XXX: It would be nice to validate the clocks, but we can't reuse
5824 * i830PllIsValid() because it relies on the xf86_config connector
5825 * configuration being accurate, which it isn't necessarily.
5826 */
5827
5828 return clock.dot;
5829}
5830
5831/** Returns the currently programmed mode of the given pipe. */
5832struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5833 struct drm_crtc *crtc)
5834{
548f245b 5835 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5837 int pipe = intel_crtc->pipe;
5838 struct drm_display_mode *mode;
548f245b
JB		 5839 int htot = I915_READ(HTOTAL(pipe));
5840 int hsync = I915_READ(HSYNC(pipe));
5841 int vtot = I915_READ(VTOTAL(pipe));
5842 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5843
5844 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5845 if (!mode)
5846 return NULL;
5847
5848 mode->clock = intel_crtc_clock_get(dev, crtc);
5849 mode->hdisplay = (htot & 0xffff) + 1;
5850 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5851 mode->hsync_start = (hsync & 0xffff) + 1;
5852 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5853 mode->vdisplay = (vtot & 0xffff) + 1;
5854 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5855 mode->vsync_start = (vsync & 0xffff) + 1;
5856 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5857
5858 drm_mode_set_name(mode);
79e53945
JB		 5859
5860 return mode;
5861}
5862
652c393a
JB		 5863#define GPU_IDLE_TIMEOUT 500 /* ms */
5864
5865/* When this timer fires, we've been idle for awhile */
5866static void intel_gpu_idle_timer(unsigned long arg)
5867{
5868 struct drm_device *dev = (struct drm_device *)arg;
5869 drm_i915_private_t *dev_priv = dev->dev_private;
5870
ff7ea4c0
CW		 5871 if (!list_empty(&dev_priv->mm.active_list)) {
5872 /* Still processing requests, so just re-arm the timer. */
5873 mod_timer(&dev_priv->idle_timer, jiffies +
5874 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5875 return;
5876 }
652c393a 5877
ff7ea4c0 5878 dev_priv->busy = false;
01dfba93 5879 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5880}
5881
652c393a
JB		 5882#define CRTC_IDLE_TIMEOUT 1000 /* ms */
5883
5884static void intel_crtc_idle_timer(unsigned long arg)
5885{
5886 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5887 struct drm_crtc *crtc = &intel_crtc->base;
5888 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 5889 struct intel_framebuffer *intel_fb;
652c393a 5890
ff7ea4c0
CW		 5891 intel_fb = to_intel_framebuffer(crtc->fb);
5892 if (intel_fb && intel_fb->obj->active) {
5893 /* The framebuffer is still being accessed by the GPU. */
5894 mod_timer(&intel_crtc->idle_timer, jiffies +
5895 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5896 return;
5897 }
652c393a 5898
ff7ea4c0 5899 intel_crtc->busy = false;
01dfba93 5900 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5901}
5902
3dec0095 5903static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 5904{
5905 struct drm_device *dev = crtc->dev;
5906 drm_i915_private_t *dev_priv = dev->dev_private;
5907 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5908 int pipe = intel_crtc->pipe;
dbdc6479
JB		 5909 int dpll_reg = DPLL(pipe);
5910 int dpll;
652c393a 5911
bad720ff 5912 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5913 return;
5914
5915 if (!dev_priv->lvds_downclock_avail)
5916 return;
5917
dbdc6479 5918 dpll = I915_READ(dpll_reg);
652c393a 5919 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 5920 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 5921
8ac5a6d5 5922 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 5923
5924 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5925 I915_WRITE(dpll_reg, dpll);
9d0498a2 5926 intel_wait_for_vblank(dev, pipe);
dbdc6479 5927
652c393a
JB		 5928 dpll = I915_READ(dpll_reg);
5929 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 5930 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 5931 }
5932
5933 /* Schedule downclock */
3dec0095
DV		 5934 mod_timer(&intel_crtc->idle_timer, jiffies +
5935 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 5936}
5937
5938static void intel_decrease_pllclock(struct drm_crtc *crtc)
5939{
5940 struct drm_device *dev = crtc->dev;
5941 drm_i915_private_t *dev_priv = dev->dev_private;
5942 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 5943
bad720ff 5944 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5945 return;
5946
5947 if (!dev_priv->lvds_downclock_avail)
5948 return;
5949
5950 /*
5951 * Since this is called by a timer, we should never get here in
5952 * the manual case.
5953 */
5954 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 5955 int pipe = intel_crtc->pipe;
5956 int dpll_reg = DPLL(pipe);
5957 int dpll;
f6e5b160 5958
44d98a61 5959 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 5960
8ac5a6d5 5961 assert_panel_unlocked(dev_priv, pipe);
652c393a 5962
dc257cf1 5963 dpll = I915_READ(dpll_reg);
652c393a
JB		 5964 dpll |= DISPLAY_RATE_SELECT_FPA1;
5965 I915_WRITE(dpll_reg, dpll);
9d0498a2 5966 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 5967 dpll = I915_READ(dpll_reg);
5968 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 5969 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 5970 }
5971
5972}
5973
5974/**
5975 * intel_idle_update - adjust clocks for idleness
5976 * @work: work struct
5977 *
5978 * Either the GPU or display (or both) went idle. Check the busy status
5979 * here and adjust the CRTC and GPU clocks as necessary.
5980 */
5981static void intel_idle_update(struct work_struct *work)
5982{
5983 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
5984 idle_work);
5985 struct drm_device *dev = dev_priv->dev;
5986 struct drm_crtc *crtc;
5987 struct intel_crtc *intel_crtc;
5988
5989 if (!i915_powersave)
5990 return;
5991
5992 mutex_lock(&dev->struct_mutex);
5993
7648fa99
JB		 5994 i915_update_gfx_val(dev_priv);
5995
652c393a
JB		 5996 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
5997 /* Skip inactive CRTCs */
5998 if (!crtc->fb)
5999 continue;
6000
6001 intel_crtc = to_intel_crtc(crtc);
6002 if (!intel_crtc->busy)
6003 intel_decrease_pllclock(crtc);
6004 }
6005
45ac22c8 6006
652c393a
JB		 6007 mutex_unlock(&dev->struct_mutex);
6008}
6009
6010/**
6011 * intel_mark_busy - mark the GPU and possibly the display busy
6012 * @dev: drm device
6013 * @obj: object we're operating on
6014 *
6015 * Callers can use this function to indicate that the GPU is busy processing
6016 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6017 * buffer), we'll also mark the display as busy, so we know to increase its
6018 * clock frequency.
6019 */
05394f39 6020void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 6021{
6022 drm_i915_private_t *dev_priv = dev->dev_private;
6023 struct drm_crtc *crtc = NULL;
6024 struct intel_framebuffer *intel_fb;
6025 struct intel_crtc *intel_crtc;
6026
5e17ee74
ZW		 6027 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6028 return;
6029
9104183d
CW		 6030 if (!dev_priv->busy) {
6031 intel_sanitize_pm(dev);
28cf798f 6032 dev_priv->busy = true;
9104183d 6033 } else
28cf798f
CW		 6034 mod_timer(&dev_priv->idle_timer, jiffies +
6035 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a 6036
acb87dfb
CW		 6037 if (obj == NULL)
6038 return;
6039
652c393a
JB		 6040 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6041 if (!crtc->fb)
6042 continue;
6043
6044 intel_crtc = to_intel_crtc(crtc);
6045 intel_fb = to_intel_framebuffer(crtc->fb);
6046 if (intel_fb->obj == obj) {
6047 if (!intel_crtc->busy) {
6048 /* Non-busy -> busy, upclock */
3dec0095 6049 intel_increase_pllclock(crtc);
652c393a
JB		 6050 intel_crtc->busy = true;
6051 } else {
6052 /* Busy -> busy, put off timer */
6053 mod_timer(&intel_crtc->idle_timer, jiffies +
6054 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6055 }
6056 }
6057 }
6058}
6059
79e53945
JB		 6060static void intel_crtc_destroy(struct drm_crtc *crtc)
6061{
6062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6063 struct drm_device *dev = crtc->dev;
6064 struct intel_unpin_work *work;
6065 unsigned long flags;
6066
6067 spin_lock_irqsave(&dev->event_lock, flags);
6068 work = intel_crtc->unpin_work;
6069 intel_crtc->unpin_work = NULL;
6070 spin_unlock_irqrestore(&dev->event_lock, flags);
6071
6072 if (work) {
6073 cancel_work_sync(&work->work);
6074 kfree(work);
6075 }
79e53945
JB		 6076
6077 drm_crtc_cleanup(crtc);
67e77c5a 6078
79e53945
JB		 6079 kfree(intel_crtc);
6080}
6081
6b95a207
KH		 6082static void intel_unpin_work_fn(struct work_struct *__work)
6083{
6084 struct intel_unpin_work *work =
6085 container_of(__work, struct intel_unpin_work, work);
6086
6087 mutex_lock(&work->dev->struct_mutex);
1690e1eb 6088 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6089 drm_gem_object_unreference(&work->pending_flip_obj->base);
6090 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6091
7782de3b 6092 intel_update_fbc(work->dev);
6b95a207
KH		 6093 mutex_unlock(&work->dev->struct_mutex);
6094 kfree(work);
6095}
6096
1afe3e9d 6097static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6098 struct drm_crtc *crtc)
6b95a207
KH		 6099{
6100 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6102 struct intel_unpin_work *work;
05394f39 6103 struct drm_i915_gem_object *obj;
6b95a207 6104 struct drm_pending_vblank_event *e;
49b14a5c 6105 struct timeval tnow, tvbl;
6b95a207
KH		 6106 unsigned long flags;
6107
6108 /* Ignore early vblank irqs */
6109 if (intel_crtc == NULL)
6110 return;
6111
49b14a5c
MK		 6112 do_gettimeofday(&tnow);
6113
6b95a207
KH		 6114 spin_lock_irqsave(&dev->event_lock, flags);
6115 work = intel_crtc->unpin_work;
6116 if (work == NULL || !work->pending) {
6117 spin_unlock_irqrestore(&dev->event_lock, flags);
6118 return;
6119 }
6120
6121 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6122
6123 if (work->event) {
6124 e = work->event;
49b14a5c 6125 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6126
6127 /* Called before vblank count and timestamps have
6128 * been updated for the vblank interval of flip
6129 * completion? Need to increment vblank count and
6130 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6131 * to account for this. We assume this happened if we
6132 * get called over 0.9 frame durations after the last
6133 * timestamped vblank.
6134 *
6135 * This calculation can not be used with vrefresh rates
6136 * below 5Hz (10Hz to be on the safe side) without
6137 * promoting to 64 integers.
0af7e4df 6138 */
49b14a5c
MK		 6139 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6140 9 * crtc->framedur_ns) {
0af7e4df 6141 e->event.sequence++;
49b14a5c
MK		 6142 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6143 crtc->framedur_ns);
0af7e4df
MK		 6144 }
6145
49b14a5c
MK		 6146 e->event.tv_sec = tvbl.tv_sec;
6147 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6148
6b95a207
KH		 6149 list_add_tail(&e->base.link,
6150 &e->base.file_priv->event_list);
6151 wake_up_interruptible(&e->base.file_priv->event_wait);
6152 }
6153
0af7e4df
MK		 6154 drm_vblank_put(dev, intel_crtc->pipe);
6155
6b95a207
KH		 6156 spin_unlock_irqrestore(&dev->event_lock, flags);
6157
05394f39 6158 obj = work->old_fb_obj;
d9e86c0e 6159
e59f2bac 6160 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6161 &obj->pending_flip.counter);
6162 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6163 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6164
6b95a207 6165 schedule_work(&work->work);
e5510fac
JB		 6166
6167 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6168}
6169
1afe3e9d
JB		 6170void intel_finish_page_flip(struct drm_device *dev, int pipe)
6171{
6172 drm_i915_private_t *dev_priv = dev->dev_private;
6173 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6174
49b14a5c 6175 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6176}
6177
6178void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6179{
6180 drm_i915_private_t *dev_priv = dev->dev_private;
6181 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6182
49b14a5c 6183 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6184}
6185
6b95a207
KH		 6186void intel_prepare_page_flip(struct drm_device *dev, int plane)
6187{
6188 drm_i915_private_t *dev_priv = dev->dev_private;
6189 struct intel_crtc *intel_crtc =
6190 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6191 unsigned long flags;
6192
6193 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6194 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6195 if ((++intel_crtc->unpin_work->pending) > 1)
6196 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6197 } else {
6198 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6199 }
6b95a207
KH		 6200 spin_unlock_irqrestore(&dev->event_lock, flags);
6201}
6202
8c9f3aaf
JB		 6203static int intel_gen2_queue_flip(struct drm_device *dev,
6204 struct drm_crtc *crtc,
6205 struct drm_framebuffer *fb,
6206 struct drm_i915_gem_object *obj)
6207{
6208 struct drm_i915_private *dev_priv = dev->dev_private;
6209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6210 u32 flip_mask;
6d90c952 6211 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6212 int ret;
6213
6d90c952 6214 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6215 if (ret)
83d4092b 6216 goto err;
8c9f3aaf 6217
6d90c952 6218 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6219 if (ret)
83d4092b 6220 goto err_unpin;
8c9f3aaf
JB		 6221
6222 /* Can't queue multiple flips, so wait for the previous
6223 * one to finish before executing the next.
6224 */
6225 if (intel_crtc->plane)
6226 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6227 else
6228 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6229 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6230 intel_ring_emit(ring, MI_NOOP);
6231 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6232 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6233 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6234 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6235 intel_ring_emit(ring, 0); /* aux display base address, unused */
6236 intel_ring_advance(ring);
83d4092b
CW		 6237 return 0;
6238
6239err_unpin:
6240 intel_unpin_fb_obj(obj);
6241err:
8c9f3aaf
JB		 6242 return ret;
6243}
6244
6245static int intel_gen3_queue_flip(struct drm_device *dev,
6246 struct drm_crtc *crtc,
6247 struct drm_framebuffer *fb,
6248 struct drm_i915_gem_object *obj)
6249{
6250 struct drm_i915_private *dev_priv = dev->dev_private;
6251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6252 u32 flip_mask;
6d90c952 6253 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6254 int ret;
6255
6d90c952 6256 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6257 if (ret)
83d4092b 6258 goto err;
8c9f3aaf 6259
6d90c952 6260 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6261 if (ret)
83d4092b 6262 goto err_unpin;
8c9f3aaf
JB		 6263
6264 if (intel_crtc->plane)
6265 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6266 else
6267 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6268 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6269 intel_ring_emit(ring, MI_NOOP);
6270 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6271 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6272 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6273 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6274 intel_ring_emit(ring, MI_NOOP);
6275
6276 intel_ring_advance(ring);
83d4092b
CW		 6277 return 0;
6278
6279err_unpin:
6280 intel_unpin_fb_obj(obj);
6281err:
8c9f3aaf
JB		 6282 return ret;
6283}
6284
6285static int intel_gen4_queue_flip(struct drm_device *dev,
6286 struct drm_crtc *crtc,
6287 struct drm_framebuffer *fb,
6288 struct drm_i915_gem_object *obj)
6289{
6290 struct drm_i915_private *dev_priv = dev->dev_private;
6291 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6292 uint32_t pf, pipesrc;
6d90c952 6293 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6294 int ret;
6295
6d90c952 6296 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6297 if (ret)
83d4092b 6298 goto err;
8c9f3aaf 6299
6d90c952 6300 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6301 if (ret)
83d4092b 6302 goto err_unpin;
8c9f3aaf
JB		 6303
6304 /* i965+ uses the linear or tiled offsets from the
6305 * Display Registers (which do not change across a page-flip)
6306 * so we need only reprogram the base address.
6307 */
6d90c952
DV		 6308 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6309 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6310 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 6311 intel_ring_emit(ring,
6312 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6313 obj->tiling_mode);
8c9f3aaf
JB		 6314
6315 /* XXX Enabling the panel-fitter across page-flip is so far
6316 * untested on non-native modes, so ignore it for now.
6317 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6318 */
6319 pf = 0;
6320 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6321 intel_ring_emit(ring, pf | pipesrc);
6322 intel_ring_advance(ring);
83d4092b
CW		 6323 return 0;
6324
6325err_unpin:
6326 intel_unpin_fb_obj(obj);
6327err:
8c9f3aaf
JB		 6328 return ret;
6329}
6330
6331static int intel_gen6_queue_flip(struct drm_device *dev,
6332 struct drm_crtc *crtc,
6333 struct drm_framebuffer *fb,
6334 struct drm_i915_gem_object *obj)
6335{
6336 struct drm_i915_private *dev_priv = dev->dev_private;
6337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 6338 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6339 uint32_t pf, pipesrc;
6340 int ret;
6341
6d90c952 6342 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6343 if (ret)
83d4092b 6344 goto err;
8c9f3aaf 6345
6d90c952 6346 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6347 if (ret)
83d4092b 6348 goto err_unpin;
8c9f3aaf 6349
6d90c952
DV		 6350 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6351 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6352 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 6353 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 6354
dc257cf1
DV		 6355 /* Contrary to the suggestions in the documentation,
6356 * "Enable Panel Fitter" does not seem to be required when page
6357 * flipping with a non-native mode, and worse causes a normal
6358 * modeset to fail.
6359 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6360 */
6361 pf = 0;
8c9f3aaf 6362 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6363 intel_ring_emit(ring, pf | pipesrc);
6364 intel_ring_advance(ring);
83d4092b
CW		 6365 return 0;
6366
6367err_unpin:
6368 intel_unpin_fb_obj(obj);
6369err:
8c9f3aaf
JB		 6370 return ret;
6371}
6372
7c9017e5
JB		 6373/*
6374 * On gen7 we currently use the blit ring because (in early silicon at least)
6375 * the render ring doesn't give us interrpts for page flip completion, which
6376 * means clients will hang after the first flip is queued. Fortunately the
6377 * blit ring generates interrupts properly, so use it instead.
6378 */
6379static int intel_gen7_queue_flip(struct drm_device *dev,
6380 struct drm_crtc *crtc,
6381 struct drm_framebuffer *fb,
6382 struct drm_i915_gem_object *obj)
6383{
6384 struct drm_i915_private *dev_priv = dev->dev_private;
6385 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6386 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 6387 uint32_t plane_bit = 0;
7c9017e5
JB		 6388 int ret;
6389
6390 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6391 if (ret)
83d4092b 6392 goto err;
7c9017e5 6393
cb05d8de
DV		 6394 switch(intel_crtc->plane) {
6395 case PLANE_A:
6396 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6397 break;
6398 case PLANE_B:
6399 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6400 break;
6401 case PLANE_C:
6402 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6403 break;
6404 default:
6405 WARN_ONCE(1, "unknown plane in flip command\n");
6406 ret = -ENODEV;
6407 goto err;
6408 }
6409
7c9017e5
JB		 6410 ret = intel_ring_begin(ring, 4);
6411 if (ret)
83d4092b 6412 goto err_unpin;
7c9017e5 6413
cb05d8de 6414 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 6415 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 6416 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 6417 intel_ring_emit(ring, (MI_NOOP));
6418 intel_ring_advance(ring);
83d4092b
CW		 6419 return 0;
6420
6421err_unpin:
6422 intel_unpin_fb_obj(obj);
6423err:
7c9017e5
JB		 6424 return ret;
6425}
6426
8c9f3aaf
JB		 6427static int intel_default_queue_flip(struct drm_device *dev,
6428 struct drm_crtc *crtc,
6429 struct drm_framebuffer *fb,
6430 struct drm_i915_gem_object *obj)
6431{
6432 return -ENODEV;
6433}
6434
6b95a207
KH		 6435static int intel_crtc_page_flip(struct drm_crtc *crtc,
6436 struct drm_framebuffer *fb,
6437 struct drm_pending_vblank_event *event)
6438{
6439 struct drm_device *dev = crtc->dev;
6440 struct drm_i915_private *dev_priv = dev->dev_private;
6441 struct intel_framebuffer *intel_fb;
05394f39 6442 struct drm_i915_gem_object *obj;
6b95a207
KH		 6443 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6444 struct intel_unpin_work *work;
8c9f3aaf 6445 unsigned long flags;
52e68630 6446 int ret;
6b95a207 6447
e6a595d2
VS		 6448 /* Can't change pixel format via MI display flips. */
6449 if (fb->pixel_format != crtc->fb->pixel_format)
6450 return -EINVAL;
6451
6452 /*
6453 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6454 * Note that pitch changes could also affect these register.
6455 */
6456 if (INTEL_INFO(dev)->gen > 3 &&
6457 (fb->offsets[0] != crtc->fb->offsets[0] ||
6458 fb->pitches[0] != crtc->fb->pitches[0]))
6459 return -EINVAL;
6460
6b95a207
KH		 6461 work = kzalloc(sizeof *work, GFP_KERNEL);
6462 if (work == NULL)
6463 return -ENOMEM;
6464
6b95a207
KH		 6465 work->event = event;
6466 work->dev = crtc->dev;
6467 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6468 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6469 INIT_WORK(&work->work, intel_unpin_work_fn);
6470
7317c75e
JB		 6471 ret = drm_vblank_get(dev, intel_crtc->pipe);
6472 if (ret)
6473 goto free_work;
6474
6b95a207
KH		 6475 /* We borrow the event spin lock for protecting unpin_work */
6476 spin_lock_irqsave(&dev->event_lock, flags);
6477 if (intel_crtc->unpin_work) {
6478 spin_unlock_irqrestore(&dev->event_lock, flags);
6479 kfree(work);
7317c75e 6480 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 6481
6482 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6483 return -EBUSY;
6484 }
6485 intel_crtc->unpin_work = work;
6486 spin_unlock_irqrestore(&dev->event_lock, flags);
6487
6488 intel_fb = to_intel_framebuffer(fb);
6489 obj = intel_fb->obj;
6490
79158103
CW		 6491 ret = i915_mutex_lock_interruptible(dev);
6492 if (ret)
6493 goto cleanup;
6b95a207 6494
75dfca80 6495 /* Reference the objects for the scheduled work. */
05394f39
CW		 6496 drm_gem_object_reference(&work->old_fb_obj->base);
6497 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6498
6499 crtc->fb = fb;
96b099fd 6500
e1f99ce6 6501 work->pending_flip_obj = obj;
e1f99ce6 6502
4e5359cd
SF		 6503 work->enable_stall_check = true;
6504
e1f99ce6
CW		 6505 /* Block clients from rendering to the new back buffer until
6506 * the flip occurs and the object is no longer visible.
6507 */
05394f39 6508 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6509
8c9f3aaf
JB		 6510 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6511 if (ret)
6512 goto cleanup_pending;
6b95a207 6513
7782de3b 6514 intel_disable_fbc(dev);
acb87dfb 6515 intel_mark_busy(dev, obj);
6b95a207
KH		 6516 mutex_unlock(&dev->struct_mutex);
6517
e5510fac
JB		 6518 trace_i915_flip_request(intel_crtc->plane, obj);
6519
6b95a207 6520 return 0;
96b099fd 6521
8c9f3aaf
JB		 6522cleanup_pending:
6523 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 6524 drm_gem_object_unreference(&work->old_fb_obj->base);
6525 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6526 mutex_unlock(&dev->struct_mutex);
6527
79158103 6528cleanup:
96b099fd
CW		 6529 spin_lock_irqsave(&dev->event_lock, flags);
6530 intel_crtc->unpin_work = NULL;
6531 spin_unlock_irqrestore(&dev->event_lock, flags);
6532
7317c75e
JB		 6533 drm_vblank_put(dev, intel_crtc->pipe);
6534free_work:
96b099fd
CW		 6535 kfree(work);
6536
6537 return ret;
6b95a207
KH		 6538}
6539
47f1c6c9
CW		 6540static void intel_sanitize_modesetting(struct drm_device *dev,
6541 int pipe, int plane)
6542{
6543 struct drm_i915_private *dev_priv = dev->dev_private;
6544 u32 reg, val;
a9dcf84b 6545 int i;
47f1c6c9 6546
f47166d2 6547 /* Clear any frame start delays used for debugging left by the BIOS */
a9dcf84b
DV		 6548 for_each_pipe(i) {
6549 reg = PIPECONF(i);
f47166d2
CW		 6550 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6551 }
6552
47f1c6c9
CW		 6553 if (HAS_PCH_SPLIT(dev))
6554 return;
6555
6556 /* Who knows what state these registers were left in by the BIOS or
6557 * grub?
6558 *
6559 * If we leave the registers in a conflicting state (e.g. with the
6560 * display plane reading from the other pipe than the one we intend
6561 * to use) then when we attempt to teardown the active mode, we will
6562 * not disable the pipes and planes in the correct order -- leaving
6563 * a plane reading from a disabled pipe and possibly leading to
6564 * undefined behaviour.
6565 */
6566
6567 reg = DSPCNTR(plane);
6568 val = I915_READ(reg);
6569
6570 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6571 return;
6572 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6573 return;
6574
6575 /* This display plane is active and attached to the other CPU pipe. */
6576 pipe = !pipe;
6577
6578 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6579 intel_disable_plane(dev_priv, plane, pipe);
6580 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 6581}
79e53945 6582
f6e5b160
CW		 6583static void intel_crtc_reset(struct drm_crtc *crtc)
6584{
6585 struct drm_device *dev = crtc->dev;
6586 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6587
6588 /* Reset flags back to the 'unknown' status so that they
6589 * will be correctly set on the initial modeset.
6590 */
6591 intel_crtc->dpms_mode = -1;
6592
6593 /* We need to fix up any BIOS configuration that conflicts with
6594 * our expectations.
6595 */
6596 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6597}
6598
6599static struct drm_crtc_helper_funcs intel_helper_funcs = {
6600 .dpms = intel_crtc_dpms,
6601 .mode_fixup = intel_crtc_mode_fixup,
6602 .mode_set = intel_crtc_mode_set,
6603 .mode_set_base = intel_pipe_set_base,
6604 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6605 .load_lut = intel_crtc_load_lut,
6606 .disable = intel_crtc_disable,
6607};
6608
6609static const struct drm_crtc_funcs intel_crtc_funcs = {
6610 .reset = intel_crtc_reset,
6611 .cursor_set = intel_crtc_cursor_set,
6612 .cursor_move = intel_crtc_cursor_move,
6613 .gamma_set = intel_crtc_gamma_set,
6614 .set_config = drm_crtc_helper_set_config,
6615 .destroy = intel_crtc_destroy,
6616 .page_flip = intel_crtc_page_flip,
6617};
6618
ee7b9f93
JB		 6619static void intel_pch_pll_init(struct drm_device *dev)
6620{
6621 drm_i915_private_t *dev_priv = dev->dev_private;
6622 int i;
6623
6624 if (dev_priv->num_pch_pll == 0) {
6625 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6626 return;
6627 }
6628
6629 for (i = 0; i < dev_priv->num_pch_pll; i++) {
6630 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6631 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6632 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6633 }
6634}
6635
b358d0a6 6636static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 6637{
22fd0fab 6638 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 6639 struct intel_crtc *intel_crtc;
6640 int i;
6641
6642 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6643 if (intel_crtc == NULL)
6644 return;
6645
6646 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6647
6648 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 6649 for (i = 0; i < 256; i++) {
6650 intel_crtc->lut_r[i] = i;
6651 intel_crtc->lut_g[i] = i;
6652 intel_crtc->lut_b[i] = i;
6653 }
6654
80824003
JB		 6655 /* Swap pipes & planes for FBC on pre-965 */
6656 intel_crtc->pipe = pipe;
6657 intel_crtc->plane = pipe;
e2e767ab 6658 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 6659 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 6660 intel_crtc->plane = !pipe;
80824003
JB		 6661 }
6662
22fd0fab
JB		 6663 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6664 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6665 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6666 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6667
5d1d0cc8 6668 intel_crtc_reset(&intel_crtc->base);
04dbff52 6669 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 6670 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 6671
6672 if (HAS_PCH_SPLIT(dev)) {
6673 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6674 intel_helper_funcs.commit = ironlake_crtc_commit;
6675 } else {
6676 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6677 intel_helper_funcs.commit = i9xx_crtc_commit;
6678 }
6679
79e53945
JB		 6680 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6681
652c393a
JB		 6682 intel_crtc->busy = false;
6683
6684 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6685 (unsigned long)intel_crtc);
79e53945
JB		 6686}
6687
08d7b3d1 6688int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 6689 struct drm_file *file)
08d7b3d1 6690{
08d7b3d1 6691 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 6692 struct drm_mode_object *drmmode_obj;
6693 struct intel_crtc *crtc;
08d7b3d1 6694
1cff8f6b
DV		 6695 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6696 return -ENODEV;
08d7b3d1 6697
c05422d5
DV		 6698 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6699 DRM_MODE_OBJECT_CRTC);
08d7b3d1 6700
c05422d5 6701 if (!drmmode_obj) {
08d7b3d1
CW		 6702 DRM_ERROR("no such CRTC id\n");
6703 return -EINVAL;
6704 }
6705
c05422d5
DV		 6706 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6707 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 6708
c05422d5 6709 return 0;
08d7b3d1
CW		 6710}
6711
66a9278e 6712static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 6713{
66a9278e
DV		 6714 struct drm_device *dev = encoder->base.dev;
6715 struct intel_encoder *source_encoder;
79e53945 6716 int index_mask = 0;
79e53945
JB		 6717 int entry = 0;
6718
66a9278e
DV		 6719 list_for_each_entry(source_encoder,
6720 &dev->mode_config.encoder_list, base.head) {
6721
6722 if (encoder == source_encoder)
79e53945 6723 index_mask |= (1 << entry);
66a9278e
DV		 6724
6725 /* Intel hw has only one MUX where enocoders could be cloned. */
6726 if (encoder->cloneable && source_encoder->cloneable)
6727 index_mask |= (1 << entry);
6728
79e53945
JB		 6729 entry++;
6730 }
4ef69c7a 6731
79e53945
JB		 6732 return index_mask;
6733}
6734
4d302442
CW		 6735static bool has_edp_a(struct drm_device *dev)
6736{
6737 struct drm_i915_private *dev_priv = dev->dev_private;
6738
6739 if (!IS_MOBILE(dev))
6740 return false;
6741
6742 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6743 return false;
6744
6745 if (IS_GEN5(dev) &&
6746 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6747 return false;
6748
6749 return true;
6750}
6751
79e53945
JB		 6752static void intel_setup_outputs(struct drm_device *dev)
6753{
725e30ad 6754 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 6755 struct intel_encoder *encoder;
cb0953d7 6756 bool dpd_is_edp = false;
f3cfcba6 6757 bool has_lvds;
79e53945 6758
f3cfcba6 6759 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 6760 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6761 /* disable the panel fitter on everything but LVDS */
6762 I915_WRITE(PFIT_CONTROL, 0);
6763 }
79e53945 6764
bad720ff 6765 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 6766 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 6767
4d302442 6768 if (has_edp_a(dev))
ab9d7c30 6769 intel_dp_init(dev, DP_A, PORT_A);
32f9d658 6770
cb0953d7 6771 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 6772 intel_dp_init(dev, PCH_DP_D, PORT_D);
cb0953d7
AJ		 6773 }
6774
6775 intel_crt_init(dev);
6776
0e72a5b5
ED		 6777 if (IS_HASWELL(dev)) {
6778 int found;
6779
6780 /* Haswell uses DDI functions to detect digital outputs */
6781 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
6782 /* DDI A only supports eDP */
6783 if (found)
6784 intel_ddi_init(dev, PORT_A);
6785
6786 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
6787 * register */
6788 found = I915_READ(SFUSE_STRAP);
6789
6790 if (found & SFUSE_STRAP_DDIB_DETECTED)
6791 intel_ddi_init(dev, PORT_B);
6792 if (found & SFUSE_STRAP_DDIC_DETECTED)
6793 intel_ddi_init(dev, PORT_C);
6794 if (found & SFUSE_STRAP_DDID_DETECTED)
6795 intel_ddi_init(dev, PORT_D);
6796 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7
AJ		 6797 int found;
6798
30ad48b7 6799 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 6800 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 6801 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 6802 if (!found)
08d644ad 6803 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 6804 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 6805 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 6806 }
6807
6808 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 6809 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 6810
b708a1d5 6811 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 6812 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 6813
5eb08b69 6814 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 6815 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 6816
cb0953d7 6817 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 6818 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 6819 } else if (IS_VALLEYVIEW(dev)) {
6820 int found;
6821
6822 if (I915_READ(SDVOB) & PORT_DETECTED) {
6823 /* SDVOB multiplex with HDMIB */
6824 found = intel_sdvo_init(dev, SDVOB, true);
6825 if (!found)
08d644ad 6826 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 6827 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 6828 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 6829 }
6830
6831 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 6832 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 6833
4a87d65d
JB		 6834 /* Shares lanes with HDMI on SDVOC */
6835 if (I915_READ(DP_C) & DP_DETECTED)
ab9d7c30 6836 intel_dp_init(dev, DP_C, PORT_C);
103a196f 6837 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 6838 bool found = false;
7d57382e 6839
725e30ad 6840 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 6841 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 6842 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 6843 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6844 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 6845 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 6846 }
27185ae1 6847
b01f2c3a
JB		 6848 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6849 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 6850 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 6851 }
725e30ad 6852 }
13520b05
KH		 6853
6854 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 6855
b01f2c3a
JB		 6856 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6857 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 6858 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 6859 }
27185ae1
ML		 6860
6861 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6862
b01f2c3a
JB		 6863 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6864 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 6865 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 6866 }
6867 if (SUPPORTS_INTEGRATED_DP(dev)) {
6868 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 6869 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 6870 }
725e30ad 6871 }
27185ae1 6872
b01f2c3a
JB		 6873 if (SUPPORTS_INTEGRATED_DP(dev) &&
6874 (I915_READ(DP_D) & DP_DETECTED)) {
6875 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 6876 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 6877 }
bad720ff 6878 } else if (IS_GEN2(dev))
79e53945
JB		 6879 intel_dvo_init(dev);
6880
103a196f 6881 if (SUPPORTS_TV(dev))
79e53945
JB		 6882 intel_tv_init(dev);
6883
4ef69c7a
CW		 6884 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6885 encoder->base.possible_crtcs = encoder->crtc_mask;
6886 encoder->base.possible_clones =
66a9278e 6887 intel_encoder_clones(encoder);
79e53945 6888 }
47356eb6 6889
2c7111db
CW		 6890 /* disable all the possible outputs/crtcs before entering KMS mode */
6891 drm_helper_disable_unused_functions(dev);
9fb526db 6892
40579abe 6893 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 6894 ironlake_init_pch_refclk(dev);
79e53945
JB		 6895}
6896
6897static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6898{
6899 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 6900
6901 drm_framebuffer_cleanup(fb);
05394f39 6902 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 6903
6904 kfree(intel_fb);
6905}
6906
6907static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 6908 struct drm_file *file,
79e53945
JB		 6909 unsigned int *handle)
6910{
6911 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 6912 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 6913
05394f39 6914 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 6915}
6916
6917static const struct drm_framebuffer_funcs intel_fb_funcs = {
6918 .destroy = intel_user_framebuffer_destroy,
6919 .create_handle = intel_user_framebuffer_create_handle,
6920};
6921
38651674
DA		 6922int intel_framebuffer_init(struct drm_device *dev,
6923 struct intel_framebuffer *intel_fb,
308e5bcb 6924 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 6925 struct drm_i915_gem_object *obj)
79e53945 6926{
79e53945
JB		 6927 int ret;
6928
05394f39 6929 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 6930 return -EINVAL;
6931
308e5bcb 6932 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 6933 return -EINVAL;
6934
308e5bcb 6935 switch (mode_cmd->pixel_format) {
04b3924d
VS		 6936 case DRM_FORMAT_RGB332:
6937 case DRM_FORMAT_RGB565:
6938 case DRM_FORMAT_XRGB8888:
b250da79 6939 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 6940 case DRM_FORMAT_ARGB8888:
6941 case DRM_FORMAT_XRGB2101010:
6942 case DRM_FORMAT_ARGB2101010:
308e5bcb 6943 /* RGB formats are common across chipsets */
b5626747 6944 break;
04b3924d
VS		 6945 case DRM_FORMAT_YUYV:
6946 case DRM_FORMAT_UYVY:
6947 case DRM_FORMAT_YVYU:
6948 case DRM_FORMAT_VYUY:
57cd6508
CW		 6949 break;
6950 default:
aca25848
ED		 6951 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6952 mode_cmd->pixel_format);
57cd6508
CW		 6953 return -EINVAL;
6954 }
6955
79e53945
JB		 6956 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6957 if (ret) {
6958 DRM_ERROR("framebuffer init failed %d\n", ret);
6959 return ret;
6960 }
6961
6962 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 6963 intel_fb->obj = obj;
79e53945
JB		 6964 return 0;
6965}
6966
79e53945
JB		 6967static struct drm_framebuffer *
6968intel_user_framebuffer_create(struct drm_device *dev,
6969 struct drm_file *filp,
308e5bcb 6970 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 6971{
05394f39 6972 struct drm_i915_gem_object *obj;
79e53945 6973
308e5bcb
JB		 6974 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6975 mode_cmd->handles[0]));
c8725226 6976 if (&obj->base == NULL)
cce13ff7 6977 return ERR_PTR(-ENOENT);
79e53945 6978
d2dff872 6979 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 6980}
6981
79e53945 6982static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 6983 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 6984 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 6985};
6986
e70236a8
JB		 6987/* Set up chip specific display functions */
6988static void intel_init_display(struct drm_device *dev)
6989{
6990 struct drm_i915_private *dev_priv = dev->dev_private;
6991
6992 /* We always want a DPMS function */
f564048e 6993 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 6994 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 6995 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
ee7b9f93 6996 dev_priv->display.off = ironlake_crtc_off;
17638cd6 6997 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 6998 } else {
e70236a8 6999 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 7000 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
ee7b9f93 7001 dev_priv->display.off = i9xx_crtc_off;
17638cd6 7002 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 7003 }
e70236a8 7004
e70236a8 7005 /* Returns the core display clock speed */
25eb05fc
JB		 7006 if (IS_VALLEYVIEW(dev))
7007 dev_priv->display.get_display_clock_speed =
7008 valleyview_get_display_clock_speed;
7009 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 7010 dev_priv->display.get_display_clock_speed =
7011 i945_get_display_clock_speed;
7012 else if (IS_I915G(dev))
7013 dev_priv->display.get_display_clock_speed =
7014 i915_get_display_clock_speed;
f2b115e6 7015 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 7016 dev_priv->display.get_display_clock_speed =
7017 i9xx_misc_get_display_clock_speed;
7018 else if (IS_I915GM(dev))
7019 dev_priv->display.get_display_clock_speed =
7020 i915gm_get_display_clock_speed;
7021 else if (IS_I865G(dev))
7022 dev_priv->display.get_display_clock_speed =
7023 i865_get_display_clock_speed;
f0f8a9ce 7024 else if (IS_I85X(dev))
e70236a8
JB		 7025 dev_priv->display.get_display_clock_speed =
7026 i855_get_display_clock_speed;
7027 else /* 852, 830 */
7028 dev_priv->display.get_display_clock_speed =
7029 i830_get_display_clock_speed;
7030
7f8a8569 7031 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 7032 if (IS_GEN5(dev)) {
674cf967 7033 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 7034 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 7035 } else if (IS_GEN6(dev)) {
674cf967 7036 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 7037 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 7038 } else if (IS_IVYBRIDGE(dev)) {
7039 /* FIXME: detect B0+ stepping and use auto training */
7040 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 7041 dev_priv->display.write_eld = ironlake_write_eld;
c82e4d26
ED		 7042 } else if (IS_HASWELL(dev)) {
7043 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
4abb3c8c 7044 dev_priv->display.write_eld = ironlake_write_eld;
7f8a8569
ZW		 7045 } else
7046 dev_priv->display.update_wm = NULL;
6067aaea 7047 } else if (IS_G4X(dev)) {
e0dac65e 7048 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 7049 }
8c9f3aaf
JB		 7050
7051 /* Default just returns -ENODEV to indicate unsupported */
7052 dev_priv->display.queue_flip = intel_default_queue_flip;
7053
7054 switch (INTEL_INFO(dev)->gen) {
7055 case 2:
7056 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7057 break;
7058
7059 case 3:
7060 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7061 break;
7062
7063 case 4:
7064 case 5:
7065 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7066 break;
7067
7068 case 6:
7069 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7070 break;
7c9017e5
JB		 7071 case 7:
7072 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7073 break;
8c9f3aaf 7074 }
e70236a8
JB		 7075}
7076
b690e96c
JB		 7077/*
7078 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7079 * resume, or other times. This quirk makes sure that's the case for
7080 * affected systems.
7081 */
0206e353 7082static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 7083{
7084 struct drm_i915_private *dev_priv = dev->dev_private;
7085
7086 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 7087 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 7088}
7089
435793df
KP		 7090/*
7091 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7092 */
7093static void quirk_ssc_force_disable(struct drm_device *dev)
7094{
7095 struct drm_i915_private *dev_priv = dev->dev_private;
7096 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 7097 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 7098}
7099
4dca20ef 7100/*
5a15ab5b
CE		 7101 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7102 * brightness value
4dca20ef
CE		 7103 */
7104static void quirk_invert_brightness(struct drm_device *dev)
7105{
7106 struct drm_i915_private *dev_priv = dev->dev_private;
7107 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 7108 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 7109}
7110
b690e96c
JB		 7111struct intel_quirk {
7112 int device;
7113 int subsystem_vendor;
7114 int subsystem_device;
7115 void (*hook)(struct drm_device *dev);
7116};
7117
c43b5634 7118static struct intel_quirk intel_quirks[] = {
b690e96c 7119 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 7120 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c
JB		 7121
7122 /* Thinkpad R31 needs pipe A force quirk */
7123 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7124 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7125 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7126
7127 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7128 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
7129 /* ThinkPad X40 needs pipe A force quirk */
7130
7131 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7132 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7133
7134 /* 855 & before need to leave pipe A & dpll A up */
7135 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7136 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 7137
7138 /* Lenovo U160 cannot use SSC on LVDS */
7139 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 7140
7141 /* Sony Vaio Y cannot use SSC on LVDS */
7142 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 7143
7144 /* Acer Aspire 5734Z must invert backlight brightness */
7145 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 7146};
7147
7148static void intel_init_quirks(struct drm_device *dev)
7149{
7150 struct pci_dev *d = dev->pdev;
7151 int i;
7152
7153 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7154 struct intel_quirk *q = &intel_quirks[i];
7155
7156 if (d->device == q->device &&
7157 (d->subsystem_vendor == q->subsystem_vendor ||
7158 q->subsystem_vendor == PCI_ANY_ID) &&
7159 (d->subsystem_device == q->subsystem_device ||
7160 q->subsystem_device == PCI_ANY_ID))
7161 q->hook(dev);
7162 }
7163}
7164
9cce37f4
JB		 7165/* Disable the VGA plane that we never use */
7166static void i915_disable_vga(struct drm_device *dev)
7167{
7168 struct drm_i915_private *dev_priv = dev->dev_private;
7169 u8 sr1;
7170 u32 vga_reg;
7171
7172 if (HAS_PCH_SPLIT(dev))
7173 vga_reg = CPU_VGACNTRL;
7174 else
7175 vga_reg = VGACNTRL;
7176
7177 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 7178 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 7179 sr1 = inb(VGA_SR_DATA);
7180 outb(sr1 | 1<<5, VGA_SR_DATA);
7181 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7182 udelay(300);
7183
7184 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7185 POSTING_READ(vga_reg);
7186}
7187
f82cfb6b
JB		 7188static void ivb_pch_pwm_override(struct drm_device *dev)
7189{
7190 struct drm_i915_private *dev_priv = dev->dev_private;
7191
7192 /*
7193 * IVB has CPU eDP backlight regs too, set things up to let the
7194 * PCH regs control the backlight
7195 */
7cf41601 7196 I915_WRITE(BLC_PWM_CPU_CTL2, BLM_PWM_ENABLE);
f82cfb6b 7197 I915_WRITE(BLC_PWM_CPU_CTL, 0);
7cf41601 7198 I915_WRITE(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE | BLM_PCH_OVERRIDE_ENABLE);
f82cfb6b
JB		 7199}
7200
f817586c
DV		 7201void intel_modeset_init_hw(struct drm_device *dev)
7202{
0232e927
ED		 7203 /* We attempt to init the necessary power wells early in the initialization
7204 * time, so the subsystems that expect power to be enabled can work.
7205 */
7206 intel_init_power_wells(dev);
7207
a8f78b58
ED		 7208 intel_prepare_ddi(dev);
7209
f817586c
DV		 7210 intel_init_clock_gating(dev);
7211
79f5b2c7 7212 mutex_lock(&dev->struct_mutex);
8090c6b9 7213 intel_enable_gt_powersave(dev);
79f5b2c7 7214 mutex_unlock(&dev->struct_mutex);
f82cfb6b
JB		 7215
7216 if (IS_IVYBRIDGE(dev))
7217 ivb_pch_pwm_override(dev);
f817586c
DV		 7218}
7219
79e53945
JB		 7220void intel_modeset_init(struct drm_device *dev)
7221{
652c393a 7222 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 7223 int i, ret;
79e53945
JB		 7224
7225 drm_mode_config_init(dev);
7226
7227 dev->mode_config.min_width = 0;
7228 dev->mode_config.min_height = 0;
7229
019d96cb
DA		 7230 dev->mode_config.preferred_depth = 24;
7231 dev->mode_config.prefer_shadow = 1;
7232
e6ecefaa 7233 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 7234
b690e96c
JB		 7235 intel_init_quirks(dev);
7236
1fa61106
ED		 7237 intel_init_pm(dev);
7238
e70236a8
JB		 7239 intel_init_display(dev);
7240
a6c45cf0
CW		 7241 if (IS_GEN2(dev)) {
7242 dev->mode_config.max_width = 2048;
7243 dev->mode_config.max_height = 2048;
7244 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 7245 dev->mode_config.max_width = 4096;
7246 dev->mode_config.max_height = 4096;
79e53945 7247 } else {
a6c45cf0
CW		 7248 dev->mode_config.max_width = 8192;
7249 dev->mode_config.max_height = 8192;
79e53945 7250 }
dd2757f8 7251 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 7252
28c97730 7253 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 7254 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 7255
a3524f1b 7256 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 7257 intel_crtc_init(dev, i);
00c2064b
JB		 7258 ret = intel_plane_init(dev, i);
7259 if (ret)
7260 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 7261 }
7262
ee7b9f93
JB		 7263 intel_pch_pll_init(dev);
7264
9cce37f4
JB		 7265 /* Just disable it once at startup */
7266 i915_disable_vga(dev);
79e53945 7267 intel_setup_outputs(dev);
652c393a 7268
652c393a
JB		 7269 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7270 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7271 (unsigned long)dev);
2c7111db
CW		 7272}
7273
7274void intel_modeset_gem_init(struct drm_device *dev)
7275{
1833b134 7276 intel_modeset_init_hw(dev);
02e792fb
DV		 7277
7278 intel_setup_overlay(dev);
79e53945
JB		 7279}
7280
7281void intel_modeset_cleanup(struct drm_device *dev)
7282{
652c393a
JB		 7283 struct drm_i915_private *dev_priv = dev->dev_private;
7284 struct drm_crtc *crtc;
7285 struct intel_crtc *intel_crtc;
7286
f87ea761 7287 drm_kms_helper_poll_fini(dev);
652c393a
JB		 7288 mutex_lock(&dev->struct_mutex);
7289
723bfd70
JB		 7290 intel_unregister_dsm_handler();
7291
7292
652c393a
JB		 7293 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7294 /* Skip inactive CRTCs */
7295 if (!crtc->fb)
7296 continue;
7297
7298 intel_crtc = to_intel_crtc(crtc);
3dec0095 7299 intel_increase_pllclock(crtc);
652c393a
JB		 7300 }
7301
973d04f9 7302 intel_disable_fbc(dev);
e70236a8 7303
8090c6b9 7304 intel_disable_gt_powersave(dev);
0cdab21f 7305
930ebb46
DV		 7306 ironlake_teardown_rc6(dev);
7307
57f350b6
JB		 7308 if (IS_VALLEYVIEW(dev))
7309 vlv_init_dpio(dev);
7310
69341a5e
KH		 7311 mutex_unlock(&dev->struct_mutex);
7312
6c0d9350
DV		 7313 /* Disable the irq before mode object teardown, for the irq might
7314 * enqueue unpin/hotplug work. */
7315 drm_irq_uninstall(dev);
7316 cancel_work_sync(&dev_priv->hotplug_work);
6fdd4d98 7317 cancel_work_sync(&dev_priv->rps_work);
6c0d9350 7318
1630fe75
CW		 7319 /* flush any delayed tasks or pending work */
7320 flush_scheduled_work();
7321
3dec0095
DV		 7322 /* Shut off idle work before the crtcs get freed. */
7323 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7324 intel_crtc = to_intel_crtc(crtc);
7325 del_timer_sync(&intel_crtc->idle_timer);
7326 }
7327 del_timer_sync(&dev_priv->idle_timer);
7328 cancel_work_sync(&dev_priv->idle_work);
7329
79e53945
JB		 7330 drm_mode_config_cleanup(dev);
7331}
7332
f1c79df3
ZW		 7333/*
7334 * Return which encoder is currently attached for connector.
7335 */
df0e9248 7336struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 7337{
df0e9248
CW		 7338 return &intel_attached_encoder(connector)->base;
7339}
f1c79df3 7340
df0e9248
CW		 7341void intel_connector_attach_encoder(struct intel_connector *connector,
7342 struct intel_encoder *encoder)
7343{
7344 connector->encoder = encoder;
7345 drm_mode_connector_attach_encoder(&connector->base,
7346 &encoder->base);
79e53945 7347}
28d52043
DA		 7348
7349/*
7350 * set vga decode state - true == enable VGA decode
7351 */
7352int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7353{
7354 struct drm_i915_private *dev_priv = dev->dev_private;
7355 u16 gmch_ctrl;
7356
7357 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7358 if (state)
7359 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7360 else
7361 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7362 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7363 return 0;
7364}
c4a1d9e4
CW		 7365
7366#ifdef CONFIG_DEBUG_FS
7367#include <linux/seq_file.h>
7368
7369struct intel_display_error_state {
7370 struct intel_cursor_error_state {
7371 u32 control;
7372 u32 position;
7373 u32 base;
7374 u32 size;
7375 } cursor[2];
7376
7377 struct intel_pipe_error_state {
7378 u32 conf;
7379 u32 source;
7380
7381 u32 htotal;
7382 u32 hblank;
7383 u32 hsync;
7384 u32 vtotal;
7385 u32 vblank;
7386 u32 vsync;
7387 } pipe[2];
7388
7389 struct intel_plane_error_state {
7390 u32 control;
7391 u32 stride;
7392 u32 size;
7393 u32 pos;
7394 u32 addr;
7395 u32 surface;
7396 u32 tile_offset;
7397 } plane[2];
7398};
7399
7400struct intel_display_error_state *
7401intel_display_capture_error_state(struct drm_device *dev)
7402{
0206e353 7403 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 7404 struct intel_display_error_state *error;
7405 int i;
7406
7407 error = kmalloc(sizeof(*error), GFP_ATOMIC);
7408 if (error == NULL)
7409 return NULL;
7410
7411 for (i = 0; i < 2; i++) {
7412 error->cursor[i].control = I915_READ(CURCNTR(i));
7413 error->cursor[i].position = I915_READ(CURPOS(i));
7414 error->cursor[i].base = I915_READ(CURBASE(i));
7415
7416 error->plane[i].control = I915_READ(DSPCNTR(i));
7417 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7418 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 7419 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 7420 error->plane[i].addr = I915_READ(DSPADDR(i));
7421 if (INTEL_INFO(dev)->gen >= 4) {
7422 error->plane[i].surface = I915_READ(DSPSURF(i));
7423 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7424 }
7425
7426 error->pipe[i].conf = I915_READ(PIPECONF(i));
7427 error->pipe[i].source = I915_READ(PIPESRC(i));
7428 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7429 error->pipe[i].hblank = I915_READ(HBLANK(i));
7430 error->pipe[i].hsync = I915_READ(HSYNC(i));
7431 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7432 error->pipe[i].vblank = I915_READ(VBLANK(i));
7433 error->pipe[i].vsync = I915_READ(VSYNC(i));
7434 }
7435
7436 return error;
7437}
7438
7439void
7440intel_display_print_error_state(struct seq_file *m,
7441 struct drm_device *dev,
7442 struct intel_display_error_state *error)
7443{
7444 int i;
7445
7446 for (i = 0; i < 2; i++) {
7447 seq_printf(m, "Pipe [%d]:\n", i);
7448 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7449 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7450 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7451 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7452 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7453 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7454 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7455 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7456
7457 seq_printf(m, "Plane [%d]:\n", i);
7458 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7459 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
7460 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
7461 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
7462 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
7463 if (INTEL_INFO(dev)->gen >= 4) {
7464 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
7465 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
7466 }
7467
7468 seq_printf(m, "Cursor [%d]:\n", i);
7469 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
7470 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
7471 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
7472 }
7473}
7474#endif
Linux kernel - Deliverables
This page took 1.637814 seconds and 5 git commands to generate.