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drm/i915: Check pixel clock limits on pre-gen4
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
f1f644dc
JB		 48static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
18442d08
VS		 50static void ironlake_pch_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
f1f644dc 52
e7457a9a
DL		 53static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
54 int x, int y, struct drm_framebuffer *old_fb);
55
56
79e53945 57typedef struct {
0206e353 58 int min, max;
79e53945
JB		 59} intel_range_t;
60
61typedef struct {
0206e353
AJ		 62 int dot_limit;
63 int p2_slow, p2_fast;
79e53945
JB		 64} intel_p2_t;
65
d4906093
ML		 66typedef struct intel_limit intel_limit_t;
67struct intel_limit {
0206e353
AJ		 68 intel_range_t dot, vco, n, m, m1, m2, p, p1;
69 intel_p2_t p2;
d4906093 70};
79e53945 71
d2acd215
DV		 72int
73intel_pch_rawclk(struct drm_device *dev)
74{
75 struct drm_i915_private *dev_priv = dev->dev_private;
76
77 WARN_ON(!HAS_PCH_SPLIT(dev));
78
79 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
80}
81
021357ac
CW		 82static inline u32 /* units of 100MHz */
83intel_fdi_link_freq(struct drm_device *dev)
84{
8b99e68c
CW		 85 if (IS_GEN5(dev)) {
86 struct drm_i915_private *dev_priv = dev->dev_private;
87 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
88 } else
89 return 27;
021357ac
CW		 90}
91
5d536e28 92static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 93 .dot = { .min = 25000, .max = 350000 },
94 .vco = { .min = 930000, .max = 1400000 },
95 .n = { .min = 3, .max = 16 },
96 .m = { .min = 96, .max = 140 },
97 .m1 = { .min = 18, .max = 26 },
98 .m2 = { .min = 6, .max = 16 },
99 .p = { .min = 4, .max = 128 },
100 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 101 .p2 = { .dot_limit = 165000,
102 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 103};
104
5d536e28
DV		 105static const intel_limit_t intel_limits_i8xx_dvo = {
106 .dot = { .min = 25000, .max = 350000 },
107 .vco = { .min = 930000, .max = 1400000 },
108 .n = { .min = 3, .max = 16 },
109 .m = { .min = 96, .max = 140 },
110 .m1 = { .min = 18, .max = 26 },
111 .m2 = { .min = 6, .max = 16 },
112 .p = { .min = 4, .max = 128 },
113 .p1 = { .min = 2, .max = 33 },
114 .p2 = { .dot_limit = 165000,
115 .p2_slow = 4, .p2_fast = 4 },
116};
117
e4b36699 118static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 119 .dot = { .min = 25000, .max = 350000 },
120 .vco = { .min = 930000, .max = 1400000 },
121 .n = { .min = 3, .max = 16 },
122 .m = { .min = 96, .max = 140 },
123 .m1 = { .min = 18, .max = 26 },
124 .m2 = { .min = 6, .max = 16 },
125 .p = { .min = 4, .max = 128 },
126 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 127 .p2 = { .dot_limit = 165000,
128 .p2_slow = 14, .p2_fast = 7 },
e4b36699 129};
273e27ca 130
e4b36699 131static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 132 .dot = { .min = 20000, .max = 400000 },
133 .vco = { .min = 1400000, .max = 2800000 },
134 .n = { .min = 1, .max = 6 },
135 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 136 .m1 = { .min = 8, .max = 18 },
137 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 138 .p = { .min = 5, .max = 80 },
139 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 140 .p2 = { .dot_limit = 200000,
141 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 142};
143
144static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 149 .m1 = { .min = 8, .max = 18 },
150 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 151 .p = { .min = 7, .max = 98 },
152 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 153 .p2 = { .dot_limit = 112000,
154 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 155};
156
273e27ca 157
e4b36699 158static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 159 .dot = { .min = 25000, .max = 270000 },
160 .vco = { .min = 1750000, .max = 3500000},
161 .n = { .min = 1, .max = 4 },
162 .m = { .min = 104, .max = 138 },
163 .m1 = { .min = 17, .max = 23 },
164 .m2 = { .min = 5, .max = 11 },
165 .p = { .min = 10, .max = 30 },
166 .p1 = { .min = 1, .max = 3},
167 .p2 = { .dot_limit = 270000,
168 .p2_slow = 10,
169 .p2_fast = 10
044c7c41 170 },
e4b36699
KP		 171};
172
173static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 174 .dot = { .min = 22000, .max = 400000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 16, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 5, .max = 80 },
181 .p1 = { .min = 1, .max = 8},
182 .p2 = { .dot_limit = 165000,
183 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 184};
185
186static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 187 .dot = { .min = 20000, .max = 115000 },
188 .vco = { .min = 1750000, .max = 3500000 },
189 .n = { .min = 1, .max = 3 },
190 .m = { .min = 104, .max = 138 },
191 .m1 = { .min = 17, .max = 23 },
192 .m2 = { .min = 5, .max = 11 },
193 .p = { .min = 28, .max = 112 },
194 .p1 = { .min = 2, .max = 8 },
195 .p2 = { .dot_limit = 0,
196 .p2_slow = 14, .p2_fast = 14
044c7c41 197 },
e4b36699
KP		 198};
199
200static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 201 .dot = { .min = 80000, .max = 224000 },
202 .vco = { .min = 1750000, .max = 3500000 },
203 .n = { .min = 1, .max = 3 },
204 .m = { .min = 104, .max = 138 },
205 .m1 = { .min = 17, .max = 23 },
206 .m2 = { .min = 5, .max = 11 },
207 .p = { .min = 14, .max = 42 },
208 .p1 = { .min = 2, .max = 6 },
209 .p2 = { .dot_limit = 0,
210 .p2_slow = 7, .p2_fast = 7
044c7c41 211 },
e4b36699
KP		 212};
213
f2b115e6 214static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 215 .dot = { .min = 20000, .max = 400000},
216 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 217 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 218 .n = { .min = 3, .max = 6 },
219 .m = { .min = 2, .max = 256 },
273e27ca 220 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 221 .m1 = { .min = 0, .max = 0 },
222 .m2 = { .min = 0, .max = 254 },
223 .p = { .min = 5, .max = 80 },
224 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 225 .p2 = { .dot_limit = 200000,
226 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 227};
228
f2b115e6 229static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 230 .dot = { .min = 20000, .max = 400000 },
231 .vco = { .min = 1700000, .max = 3500000 },
232 .n = { .min = 3, .max = 6 },
233 .m = { .min = 2, .max = 256 },
234 .m1 = { .min = 0, .max = 0 },
235 .m2 = { .min = 0, .max = 254 },
236 .p = { .min = 7, .max = 112 },
237 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 238 .p2 = { .dot_limit = 112000,
239 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 240};
241
273e27ca
EA		 242/* Ironlake / Sandybridge
243 *
244 * We calculate clock using (register_value + 2) for N/M1/M2, so here
245 * the range value for them is (actual_value - 2).
246 */
b91ad0ec 247static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 248 .dot = { .min = 25000, .max = 350000 },
249 .vco = { .min = 1760000, .max = 3510000 },
250 .n = { .min = 1, .max = 5 },
251 .m = { .min = 79, .max = 127 },
252 .m1 = { .min = 12, .max = 22 },
253 .m2 = { .min = 5, .max = 9 },
254 .p = { .min = 5, .max = 80 },
255 .p1 = { .min = 1, .max = 8 },
256 .p2 = { .dot_limit = 225000,
257 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 258};
259
b91ad0ec 260static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 261 .dot = { .min = 25000, .max = 350000 },
262 .vco = { .min = 1760000, .max = 3510000 },
263 .n = { .min = 1, .max = 3 },
264 .m = { .min = 79, .max = 118 },
265 .m1 = { .min = 12, .max = 22 },
266 .m2 = { .min = 5, .max = 9 },
267 .p = { .min = 28, .max = 112 },
268 .p1 = { .min = 2, .max = 8 },
269 .p2 = { .dot_limit = 225000,
270 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 271};
272
273static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 3 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 14, .max = 56 },
281 .p1 = { .min = 2, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 284};
285
273e27ca 286/* LVDS 100mhz refclk limits. */
b91ad0ec 287static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 2 },
291 .m = { .min = 79, .max = 126 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
0206e353 295 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 298};
299
300static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 3 },
304 .m = { .min = 79, .max = 126 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 14, .max = 42 },
0206e353 308 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 311};
312
a0c4da24
JB		 313static const intel_limit_t intel_limits_vlv_dac = {
314 .dot = { .min = 25000, .max = 270000 },
315 .vco = { .min = 4000000, .max = 6000000 },
316 .n = { .min = 1, .max = 7 },
317 .m = { .min = 22, .max = 450 }, /* guess */
318 .m1 = { .min = 2, .max = 3 },
319 .m2 = { .min = 11, .max = 156 },
320 .p = { .min = 10, .max = 30 },
75e53986 321 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 322 .p2 = { .dot_limit = 270000,
323 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 324};
325
326static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 327 .dot = { .min = 25000, .max = 270000 },
328 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 329 .n = { .min = 1, .max = 7 },
330 .m = { .min = 60, .max = 300 }, /* guess */
331 .m1 = { .min = 2, .max = 3 },
332 .m2 = { .min = 11, .max = 156 },
333 .p = { .min = 10, .max = 30 },
334 .p1 = { .min = 2, .max = 3 },
335 .p2 = { .dot_limit = 270000,
336 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 337};
338
1b894b59
CW		 339static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
340 int refclk)
2c07245f 341{
b91ad0ec 342 struct drm_device *dev = crtc->dev;
2c07245f 343 const intel_limit_t *limit;
b91ad0ec
ZW		 344
345 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 346 if (intel_is_dual_link_lvds(dev)) {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_dual_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_dual_lvds;
351 } else {
1b894b59 352 if (refclk == 100000)
b91ad0ec
ZW		 353 limit = &intel_limits_ironlake_single_lvds_100m;
354 else
355 limit = &intel_limits_ironlake_single_lvds;
356 }
c6bb3538 357 } else
b91ad0ec 358 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 359
360 return limit;
361}
362
044c7c41
ML		 363static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
364{
365 struct drm_device *dev = crtc->dev;
044c7c41
ML		 366 const intel_limit_t *limit;
367
368 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 369 if (intel_is_dual_link_lvds(dev))
e4b36699 370 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 371 else
e4b36699 372 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 373 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
374 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 375 limit = &intel_limits_g4x_hdmi;
044c7c41 376 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 377 limit = &intel_limits_g4x_sdvo;
044c7c41 378 } else /* The option is for other outputs */
e4b36699 379 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 380
381 return limit;
382}
383
1b894b59 384static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 385{
386 struct drm_device *dev = crtc->dev;
387 const intel_limit_t *limit;
388
bad720ff 389 if (HAS_PCH_SPLIT(dev))
1b894b59 390 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 391 else if (IS_G4X(dev)) {
044c7c41 392 limit = intel_g4x_limit(crtc);
f2b115e6 393 } else if (IS_PINEVIEW(dev)) {
2177832f 394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 395 limit = &intel_limits_pineview_lvds;
2177832f 396 else
f2b115e6 397 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 398 } else if (IS_VALLEYVIEW(dev)) {
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
400 limit = &intel_limits_vlv_dac;
a0c4da24 401 else
65ce4bf5 402 limit = &intel_limits_vlv_hdmi;
a6c45cf0
CW		 403 } else if (!IS_GEN2(dev)) {
404 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
405 limit = &intel_limits_i9xx_lvds;
406 else
407 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 408 } else {
409 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 410 limit = &intel_limits_i8xx_lvds;
5d536e28 411 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 412 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 413 else
414 limit = &intel_limits_i8xx_dac;
79e53945
JB		 415 }
416 return limit;
417}
418
f2b115e6
AJ		 419/* m1 is reserved as 0 in Pineview, n is a ring counter */
420static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 421{
2177832f
SL		 422 clock->m = clock->m2 + 2;
423 clock->p = clock->p1 * clock->p2;
424 clock->vco = refclk * clock->m / clock->n;
425 clock->dot = clock->vco / clock->p;
426}
427
7429e9d4
DV		 428static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
429{
430 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
431}
432
ac58c3f0 433static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 434{
7429e9d4 435 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 436 clock->p = clock->p1 * clock->p2;
437 clock->vco = refclk * clock->m / (clock->n + 2);
438 clock->dot = clock->vco / clock->p;
439}
440
79e53945
JB		 441/**
442 * Returns whether any output on the specified pipe is of the specified type
443 */
4ef69c7a 444bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 445{
4ef69c7a 446 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 447 struct intel_encoder *encoder;
448
6c2b7c12
DV		 449 for_each_encoder_on_crtc(dev, crtc, encoder)
450 if (encoder->type == type)
4ef69c7a
CW		 451 return true;
452
453 return false;
79e53945
JB		 454}
455
7c04d1d9 456#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 457/**
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
460 */
461
1b894b59
CW		 462static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
79e53945 465{
79e53945 466 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 467 INTELPllInvalid("p1 out of range\n");
79e53945 468 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 469 INTELPllInvalid("p out of range\n");
79e53945 470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 471 INTELPllInvalid("m2 out of range\n");
79e53945 472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 473 INTELPllInvalid("m1 out of range\n");
f2b115e6 474 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 475 INTELPllInvalid("m1 <= m2\n");
79e53945 476 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 477 INTELPllInvalid("m out of range\n");
79e53945 478 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 479 INTELPllInvalid("n out of range\n");
79e53945 480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 481 INTELPllInvalid("vco out of range\n");
79e53945
JB		 482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
484 */
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 486 INTELPllInvalid("dot out of range\n");
79e53945
JB		 487
488 return true;
489}
490
d4906093 491static bool
ee9300bb 492i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
79e53945
JB		 495{
496 struct drm_device *dev = crtc->dev;
79e53945 497 intel_clock_t clock;
79e53945
JB		 498 int err = target;
499
a210b028 500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 501 /*
a210b028
DV		 502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
79e53945 505 */
1974cad0 506 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 507 clock.p2 = limit->p2.p2_fast;
508 else
509 clock.p2 = limit->p2.p2_slow;
510 } else {
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
513 else
514 clock.p2 = limit->p2.p2_fast;
515 }
516
0206e353 517 memset(best_clock, 0, sizeof(*best_clock));
79e53945 518
42158660
ZY		 519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
520 clock.m1++) {
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 523 if (clock.m2 >= clock.m1)
42158660
ZY		 524 break;
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 529 int this_err;
530
ac58c3f0
DV		 531 i9xx_clock(refclk, &clock);
532 if (!intel_PLL_is_valid(dev, limit,
533 &clock))
534 continue;
535 if (match_clock &&
536 clock.p != match_clock->p)
537 continue;
538
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
541 *best_clock = clock;
542 err = this_err;
543 }
544 }
545 }
546 }
547 }
548
549 return (err != target);
550}
551
552static bool
ee9300bb
DV		 553pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
79e53945
JB		 556{
557 struct drm_device *dev = crtc->dev;
79e53945 558 intel_clock_t clock;
79e53945
JB		 559 int err = target;
560
a210b028 561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 562 /*
a210b028
DV		 563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
79e53945 566 */
1974cad0 567 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 568 clock.p2 = limit->p2.p2_fast;
569 else
570 clock.p2 = limit->p2.p2_slow;
571 } else {
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
574 else
575 clock.p2 = limit->p2.p2_fast;
576 }
577
0206e353 578 memset(best_clock, 0, sizeof(*best_clock));
79e53945 579
42158660
ZY		 580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
581 clock.m1++) {
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 588 int this_err;
589
ac58c3f0 590 pineview_clock(refclk, &clock);
1b894b59
CW		 591 if (!intel_PLL_is_valid(dev, limit,
592 &clock))
79e53945 593 continue;
cec2f356
SP		 594 if (match_clock &&
595 clock.p != match_clock->p)
596 continue;
79e53945
JB		 597
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
600 *best_clock = clock;
601 err = this_err;
602 }
603 }
604 }
605 }
606 }
607
608 return (err != target);
609}
610
d4906093 611static bool
ee9300bb
DV		 612g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
d4906093
ML		 615{
616 struct drm_device *dev = crtc->dev;
d4906093
ML		 617 intel_clock_t clock;
618 int max_n;
619 bool found;
6ba770dc
AJ		 620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 622 found = false;
623
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 625 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 626 clock.p2 = limit->p2.p2_fast;
627 else
628 clock.p2 = limit->p2.p2_slow;
629 } else {
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
632 else
633 clock.p2 = limit->p2.p2_fast;
634 }
635
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
f77f13e2 638 /* based on hardware requirement, prefer smaller n to precision */
d4906093 639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 640 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
647 int this_err;
648
ac58c3f0 649 i9xx_clock(refclk, &clock);
1b894b59
CW		 650 if (!intel_PLL_is_valid(dev, limit,
651 &clock))
d4906093 652 continue;
1b894b59
CW		 653
654 this_err = abs(clock.dot - target);
d4906093
ML		 655 if (this_err < err_most) {
656 *best_clock = clock;
657 err_most = this_err;
658 max_n = clock.n;
659 found = true;
660 }
661 }
662 }
663 }
664 }
2c07245f
ZW		 665 return found;
666}
667
a0c4da24 668static bool
ee9300bb
DV		 669vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
a0c4da24
JB		 672{
673 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
674 u32 m, n, fastclk;
f3f08572 675 u32 updrate, minupdate, p;
a0c4da24
JB		 676 unsigned long bestppm, ppm, absppm;
677 int dotclk, flag;
678
af447bd3 679 flag = 0;
a0c4da24
JB		 680 dotclk = target * 1000;
681 bestppm = 1000000;
682 ppm = absppm = 0;
683 fastclk = dotclk / (2*100);
684 updrate = 0;
685 minupdate = 19200;
a0c4da24
JB		 686 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
687 bestm1 = bestm2 = bestp1 = bestp2 = 0;
688
689 /* based on hardware requirement, prefer smaller n to precision */
690 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
691 updrate = refclk / n;
692 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
693 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
694 if (p2 > 10)
695 p2 = p2 - 1;
696 p = p1 * p2;
697 /* based on hardware requirement, prefer bigger m1,m2 values */
698 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
699 m2 = (((2*(fastclk * p * n / m1 )) +
700 refclk) / (2*refclk));
701 m = m1 * m2;
702 vco = updrate * m;
703 if (vco >= limit->vco.min && vco < limit->vco.max) {
704 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
705 absppm = (ppm > 0) ? ppm : (-ppm);
706 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
707 bestppm = 0;
708 flag = 1;
709 }
710 if (absppm < bestppm - 10) {
711 bestppm = absppm;
712 flag = 1;
713 }
714 if (flag) {
715 bestn = n;
716 bestm1 = m1;
717 bestm2 = m2;
718 bestp1 = p1;
719 bestp2 = p2;
720 flag = 0;
721 }
722 }
723 }
724 }
725 }
726 }
727 best_clock->n = bestn;
728 best_clock->m1 = bestm1;
729 best_clock->m2 = bestm2;
730 best_clock->p1 = bestp1;
731 best_clock->p2 = bestp2;
732
733 return true;
734}
a4fc5ed6 735
20ddf665
VS		 736bool intel_crtc_active(struct drm_crtc *crtc)
737{
738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
739
740 /* Be paranoid as we can arrive here with only partial
741 * state retrieved from the hardware during setup.
742 *
743 * We can ditch the adjusted_mode.clock check as soon
744 * as Haswell has gained clock readout/fastboot support.
745 *
746 * We can ditch the crtc->fb check as soon as we can
747 * properly reconstruct framebuffers.
748 */
749 return intel_crtc->active && crtc->fb &&
750 intel_crtc->config.adjusted_mode.clock;
751}
752
a5c961d1
PZ		 753enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
754 enum pipe pipe)
755{
756 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
758
3b117c8f 759 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 760}
761
a928d536
PZ		 762static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
763{
764 struct drm_i915_private *dev_priv = dev->dev_private;
765 u32 frame, frame_reg = PIPEFRAME(pipe);
766
767 frame = I915_READ(frame_reg);
768
769 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
770 DRM_DEBUG_KMS("vblank wait timed out\n");
771}
772
9d0498a2
JB		 773/**
774 * intel_wait_for_vblank - wait for vblank on a given pipe
775 * @dev: drm device
776 * @pipe: pipe to wait for
777 *
778 * Wait for vblank to occur on a given pipe. Needed for various bits of
779 * mode setting code.
780 */
781void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 782{
9d0498a2 783 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 784 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 785
a928d536
PZ		 786 if (INTEL_INFO(dev)->gen >= 5) {
787 ironlake_wait_for_vblank(dev, pipe);
788 return;
789 }
790
300387c0
CW		 791 /* Clear existing vblank status. Note this will clear any other
792 * sticky status fields as well.
793 *
794 * This races with i915_driver_irq_handler() with the result
795 * that either function could miss a vblank event. Here it is not
796 * fatal, as we will either wait upon the next vblank interrupt or
797 * timeout. Generally speaking intel_wait_for_vblank() is only
798 * called during modeset at which time the GPU should be idle and
799 * should *not* be performing page flips and thus not waiting on
800 * vblanks...
801 * Currently, the result of us stealing a vblank from the irq
802 * handler is that a single frame will be skipped during swapbuffers.
803 */
804 I915_WRITE(pipestat_reg,
805 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
806
9d0498a2 807 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 808 if (wait_for(I915_READ(pipestat_reg) &
809 PIPE_VBLANK_INTERRUPT_STATUS,
810 50))
9d0498a2
JB		 811 DRM_DEBUG_KMS("vblank wait timed out\n");
812}
813
ab7ad7f6
KP		 814/*
815 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 816 * @dev: drm device
817 * @pipe: pipe to wait for
818 *
819 * After disabling a pipe, we can't wait for vblank in the usual way,
820 * spinning on the vblank interrupt status bit, since we won't actually
821 * see an interrupt when the pipe is disabled.
822 *
ab7ad7f6
KP		 823 * On Gen4 and above:
824 * wait for the pipe register state bit to turn off
825 *
826 * Otherwise:
827 * wait for the display line value to settle (it usually
828 * ends up stopping at the start of the next frame).
58e10eb9 829 *
9d0498a2 830 */
58e10eb9 831void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 832{
833 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 834 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
835 pipe);
ab7ad7f6
KP		 836
837 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 838 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 839
840 /* Wait for the Pipe State to go off */
58e10eb9
CW		 841 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
842 100))
284637d9 843 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 844 } else {
837ba00f 845 u32 last_line, line_mask;
58e10eb9 846 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 847 unsigned long timeout = jiffies + msecs_to_jiffies(100);
848
837ba00f
PZ		 849 if (IS_GEN2(dev))
850 line_mask = DSL_LINEMASK_GEN2;
851 else
852 line_mask = DSL_LINEMASK_GEN3;
853
ab7ad7f6
KP		 854 /* Wait for the display line to settle */
855 do {
837ba00f 856 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 857 mdelay(5);
837ba00f 858 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 859 time_after(timeout, jiffies));
860 if (time_after(jiffies, timeout))
284637d9 861 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 862 }
79e53945
JB		 863}
864
b0ea7d37
DL		 865/*
866 * ibx_digital_port_connected - is the specified port connected?
867 * @dev_priv: i915 private structure
868 * @port: the port to test
869 *
870 * Returns true if @port is connected, false otherwise.
871 */
872bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
873 struct intel_digital_port *port)
874{
875 u32 bit;
876
c36346e3
DL		 877 if (HAS_PCH_IBX(dev_priv->dev)) {
878 switch(port->port) {
879 case PORT_B:
880 bit = SDE_PORTB_HOTPLUG;
881 break;
882 case PORT_C:
883 bit = SDE_PORTC_HOTPLUG;
884 break;
885 case PORT_D:
886 bit = SDE_PORTD_HOTPLUG;
887 break;
888 default:
889 return true;
890 }
891 } else {
892 switch(port->port) {
893 case PORT_B:
894 bit = SDE_PORTB_HOTPLUG_CPT;
895 break;
896 case PORT_C:
897 bit = SDE_PORTC_HOTPLUG_CPT;
898 break;
899 case PORT_D:
900 bit = SDE_PORTD_HOTPLUG_CPT;
901 break;
902 default:
903 return true;
904 }
b0ea7d37
DL		 905 }
906
907 return I915_READ(SDEISR) & bit;
908}
909
b24e7179
JB		 910static const char *state_string(bool enabled)
911{
912 return enabled ? "on" : "off";
913}
914
915/* Only for pre-ILK configs */
55607e8a
DV		 916void assert_pll(struct drm_i915_private *dev_priv,
917 enum pipe pipe, bool state)
b24e7179
JB		 918{
919 int reg;
920 u32 val;
921 bool cur_state;
922
923 reg = DPLL(pipe);
924 val = I915_READ(reg);
925 cur_state = !!(val & DPLL_VCO_ENABLE);
926 WARN(cur_state != state,
927 "PLL state assertion failure (expected %s, current %s)\n",
928 state_string(state), state_string(cur_state));
929}
b24e7179 930
23538ef1
JN		 931/* XXX: the dsi pll is shared between MIPI DSI ports */
932static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
933{
934 u32 val;
935 bool cur_state;
936
937 mutex_lock(&dev_priv->dpio_lock);
938 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
939 mutex_unlock(&dev_priv->dpio_lock);
940
941 cur_state = val & DSI_PLL_VCO_EN;
942 WARN(cur_state != state,
943 "DSI PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state), state_string(cur_state));
945}
946#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
947#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
948
55607e8a 949struct intel_shared_dpll *
e2b78267
DV		 950intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
951{
952 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
953
a43f6e0f 954 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 955 return NULL;
956
a43f6e0f 957 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 958}
959
040484af 960/* For ILK+ */
55607e8a
DV		 961void assert_shared_dpll(struct drm_i915_private *dev_priv,
962 struct intel_shared_dpll *pll,
963 bool state)
040484af 964{
040484af 965 bool cur_state;
5358901f 966 struct intel_dpll_hw_state hw_state;
040484af 967
9d82aa17
ED		 968 if (HAS_PCH_LPT(dev_priv->dev)) {
969 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
970 return;
971 }
972
92b27b08 973 if (WARN (!pll,
46edb027 974 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 975 return;
ee7b9f93 976
5358901f 977 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 978 WARN(cur_state != state,
5358901f
DV		 979 "%s assertion failure (expected %s, current %s)\n",
980 pll->name, state_string(state), state_string(cur_state));
040484af 981}
040484af
JB		 982
983static void assert_fdi_tx(struct drm_i915_private *dev_priv,
984 enum pipe pipe, bool state)
985{
986 int reg;
987 u32 val;
988 bool cur_state;
ad80a810
PZ		 989 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
990 pipe);
040484af 991
affa9354
PZ		 992 if (HAS_DDI(dev_priv->dev)) {
993 /* DDI does not have a specific FDI_TX register */
ad80a810 994 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 995 val = I915_READ(reg);
ad80a810 996 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 997 } else {
998 reg = FDI_TX_CTL(pipe);
999 val = I915_READ(reg);
1000 cur_state = !!(val & FDI_TX_ENABLE);
1001 }
040484af
JB		 1002 WARN(cur_state != state,
1003 "FDI TX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1005}
1006#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010 enum pipe pipe, bool state)
1011{
1012 int reg;
1013 u32 val;
1014 bool cur_state;
1015
d63fa0dc
PZ		 1016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1019 WARN(cur_state != state,
1020 "FDI RX state assertion failure (expected %s, current %s)\n",
1021 state_string(state), state_string(cur_state));
1022}
1023#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027 enum pipe pipe)
1028{
1029 int reg;
1030 u32 val;
1031
1032 /* ILK FDI PLL is always enabled */
1033 if (dev_priv->info->gen == 5)
1034 return;
1035
bf507ef7 1036 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1037 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1038 return;
1039
040484af
JB		 1040 reg = FDI_TX_CTL(pipe);
1041 val = I915_READ(reg);
1042 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043}
1044
55607e8a
DV		 1045void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
040484af
JB		 1047{
1048 int reg;
1049 u32 val;
55607e8a 1050 bool cur_state;
040484af
JB		 1051
1052 reg = FDI_RX_CTL(pipe);
1053 val = I915_READ(reg);
55607e8a
DV		 1054 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055 WARN(cur_state != state,
1056 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
040484af
JB		 1058}
1059
ea0760cf
JB		 1060static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061 enum pipe pipe)
1062{
1063 int pp_reg, lvds_reg;
1064 u32 val;
1065 enum pipe panel_pipe = PIPE_A;
0de3b485 1066 bool locked = true;
ea0760cf
JB		 1067
1068 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069 pp_reg = PCH_PP_CONTROL;
1070 lvds_reg = PCH_LVDS;
1071 } else {
1072 pp_reg = PP_CONTROL;
1073 lvds_reg = LVDS;
1074 }
1075
1076 val = I915_READ(pp_reg);
1077 if (!(val & PANEL_POWER_ON) ||
1078 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079 locked = false;
1080
1081 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082 panel_pipe = PIPE_B;
1083
1084 WARN(panel_pipe == pipe && locked,
1085 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1086 pipe_name(pipe));
ea0760cf
JB		 1087}
1088
93ce0ba6
JN		 1089static void assert_cursor(struct drm_i915_private *dev_priv,
1090 enum pipe pipe, bool state)
1091{
1092 struct drm_device *dev = dev_priv->dev;
1093 bool cur_state;
1094
1095 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097 else if (IS_845G(dev) || IS_I865G(dev))
1098 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1099 else
1100 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1101
1102 WARN(cur_state != state,
1103 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104 pipe_name(pipe), state_string(state), state_string(cur_state));
1105}
1106#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
b840d907
JB		 1109void assert_pipe(struct drm_i915_private *dev_priv,
1110 enum pipe pipe, bool state)
b24e7179
JB		 1111{
1112 int reg;
1113 u32 val;
63d7bbe9 1114 bool cur_state;
702e7a56
PZ		 1115 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116 pipe);
b24e7179 1117
8e636784
DV		 1118 /* if we need the pipe A quirk it must be always on */
1119 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120 state = true;
1121
b97186f0
PZ		 1122 if (!intel_display_power_enabled(dev_priv->dev,
1123 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1124 cur_state = false;
1125 } else {
1126 reg = PIPECONF(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & PIPECONF_ENABLE);
1129 }
1130
63d7bbe9
JB		 1131 WARN(cur_state != state,
1132 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1133 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1134}
1135
931872fc
CW		 1136static void assert_plane(struct drm_i915_private *dev_priv,
1137 enum plane plane, bool state)
b24e7179
JB		 1138{
1139 int reg;
1140 u32 val;
931872fc 1141 bool cur_state;
b24e7179
JB		 1142
1143 reg = DSPCNTR(plane);
1144 val = I915_READ(reg);
931872fc
CW		 1145 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146 WARN(cur_state != state,
1147 "plane %c assertion failure (expected %s, current %s)\n",
1148 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1149}
1150
931872fc
CW		 1151#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
b24e7179
JB		 1154static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155 enum pipe pipe)
1156{
653e1026 1157 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1158 int reg, i;
1159 u32 val;
1160 int cur_pipe;
1161
653e1026
VS		 1162 /* Primary planes are fixed to pipes on gen4+ */
1163 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1164 reg = DSPCNTR(pipe);
1165 val = I915_READ(reg);
1166 WARN((val & DISPLAY_PLANE_ENABLE),
1167 "plane %c assertion failure, should be disabled but not\n",
1168 plane_name(pipe));
19ec1358 1169 return;
28c05794 1170 }
19ec1358 1171
b24e7179 1172 /* Need to check both planes against the pipe */
08e2a7de 1173 for_each_pipe(i) {
b24e7179
JB		 1174 reg = DSPCNTR(i);
1175 val = I915_READ(reg);
1176 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177 DISPPLANE_SEL_PIPE_SHIFT;
1178 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1179 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1181 }
1182}
1183
19332d7a
JB		 1184static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185 enum pipe pipe)
1186{
20674eef 1187 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1188 int reg, i;
1189 u32 val;
1190
20674eef
VS		 1191 if (IS_VALLEYVIEW(dev)) {
1192 for (i = 0; i < dev_priv->num_plane; i++) {
1193 reg = SPCNTR(pipe, i);
1194 val = I915_READ(reg);
1195 WARN((val & SP_ENABLE),
1196 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197 sprite_name(pipe, i), pipe_name(pipe));
1198 }
1199 } else if (INTEL_INFO(dev)->gen >= 7) {
1200 reg = SPRCTL(pipe);
19332d7a 1201 val = I915_READ(reg);
20674eef 1202 WARN((val & SPRITE_ENABLE),
06da8da2 1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1204 plane_name(pipe), pipe_name(pipe));
1205 } else if (INTEL_INFO(dev)->gen >= 5) {
1206 reg = DVSCNTR(pipe);
19332d7a 1207 val = I915_READ(reg);
20674eef 1208 WARN((val & DVS_ENABLE),
06da8da2 1209 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1210 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1211 }
1212}
1213
92f2584a
JB		 1214static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215{
1216 u32 val;
1217 bool enabled;
1218
9d82aa17
ED		 1219 if (HAS_PCH_LPT(dev_priv->dev)) {
1220 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1221 return;
1222 }
1223
92f2584a
JB		 1224 val = I915_READ(PCH_DREF_CONTROL);
1225 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226 DREF_SUPERSPREAD_SOURCE_MASK));
1227 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228}
1229
ab9412ba
DV		 1230static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231 enum pipe pipe)
92f2584a
JB		 1232{
1233 int reg;
1234 u32 val;
1235 bool enabled;
1236
ab9412ba 1237 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1238 val = I915_READ(reg);
1239 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1240 WARN(enabled,
1241 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242 pipe_name(pipe));
92f2584a
JB		 1243}
1244
4e634389
KP		 1245static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1247{
1248 if ((val & DP_PORT_EN) == 0)
1249 return false;
1250
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255 return false;
1256 } else {
1257 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258 return false;
1259 }
1260 return true;
1261}
1262
1519b995
KP		 1263static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, u32 val)
1265{
dc0fa718 1266 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1267 return false;
1268
1269 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1270 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1271 return false;
1272 } else {
dc0fa718 1273 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1274 return false;
1275 }
1276 return true;
1277}
1278
1279static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, u32 val)
1281{
1282 if ((val & LVDS_PORT_EN) == 0)
1283 return false;
1284
1285 if (HAS_PCH_CPT(dev_priv->dev)) {
1286 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287 return false;
1288 } else {
1289 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290 return false;
1291 }
1292 return true;
1293}
1294
1295static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe, u32 val)
1297{
1298 if ((val & ADPA_DAC_ENABLE) == 0)
1299 return false;
1300 if (HAS_PCH_CPT(dev_priv->dev)) {
1301 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302 return false;
1303 } else {
1304 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305 return false;
1306 }
1307 return true;
1308}
1309
291906f1 1310static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1311 enum pipe pipe, int reg, u32 port_sel)
291906f1 1312{
47a05eca 1313 u32 val = I915_READ(reg);
4e634389 1314 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1315 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1316 reg, pipe_name(pipe));
de9a35ab 1317
75c5da27
DV		 1318 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319 && (val & DP_PIPEB_SELECT),
de9a35ab 1320 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1321}
1322
1323static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324 enum pipe pipe, int reg)
1325{
47a05eca 1326 u32 val = I915_READ(reg);
b70ad586 1327 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1328 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1329 reg, pipe_name(pipe));
de9a35ab 1330
dc0fa718 1331 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1332 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1333 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1334}
1335
1336static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337 enum pipe pipe)
1338{
1339 int reg;
1340 u32 val;
291906f1 1341
f0575e92
KP		 1342 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1345
1346 reg = PCH_ADPA;
1347 val = I915_READ(reg);
b70ad586 1348 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1349 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1350 pipe_name(pipe));
291906f1
JB		 1351
1352 reg = PCH_LVDS;
1353 val = I915_READ(reg);
b70ad586 1354 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1355 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1356 pipe_name(pipe));
291906f1 1357
e2debe91
PZ		 1358 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1361}
1362
426115cf 1363static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1364{
426115cf
DV		 1365 struct drm_device *dev = crtc->base.dev;
1366 struct drm_i915_private *dev_priv = dev->dev_private;
1367 int reg = DPLL(crtc->pipe);
1368 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1369
426115cf 1370 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1371
1372 /* No really, not for ILK+ */
1373 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1374
1375 /* PLL is protected by panel, make sure we can write it */
1376 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1377 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1378
426115cf
DV		 1379 I915_WRITE(reg, dpll);
1380 POSTING_READ(reg);
1381 udelay(150);
1382
1383 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1384 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1385
1386 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1387 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1388
1389 /* We do this three times for luck */
426115cf 1390 I915_WRITE(reg, dpll);
87442f73
DV		 1391 POSTING_READ(reg);
1392 udelay(150); /* wait for warmup */
426115cf 1393 I915_WRITE(reg, dpll);
87442f73
DV		 1394 POSTING_READ(reg);
1395 udelay(150); /* wait for warmup */
426115cf 1396 I915_WRITE(reg, dpll);
87442f73
DV		 1397 POSTING_READ(reg);
1398 udelay(150); /* wait for warmup */
1399}
1400
66e3d5c0 1401static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1402{
66e3d5c0
DV		 1403 struct drm_device *dev = crtc->base.dev;
1404 struct drm_i915_private *dev_priv = dev->dev_private;
1405 int reg = DPLL(crtc->pipe);
1406 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1407
66e3d5c0 1408 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1409
63d7bbe9 1410 /* No really, not for ILK+ */
87442f73 1411 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1412
1413 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1414 if (IS_MOBILE(dev) && !IS_I830(dev))
1415 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1416
66e3d5c0
DV		 1417 I915_WRITE(reg, dpll);
1418
1419 /* Wait for the clocks to stabilize. */
1420 POSTING_READ(reg);
1421 udelay(150);
1422
1423 if (INTEL_INFO(dev)->gen >= 4) {
1424 I915_WRITE(DPLL_MD(crtc->pipe),
1425 crtc->config.dpll_hw_state.dpll_md);
1426 } else {
1427 /* The pixel multiplier can only be updated once the
1428 * DPLL is enabled and the clocks are stable.
1429 *
1430 * So write it again.
1431 */
1432 I915_WRITE(reg, dpll);
1433 }
63d7bbe9
JB		 1434
1435 /* We do this three times for luck */
66e3d5c0 1436 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1437 POSTING_READ(reg);
1438 udelay(150); /* wait for warmup */
66e3d5c0 1439 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1440 POSTING_READ(reg);
1441 udelay(150); /* wait for warmup */
66e3d5c0 1442 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1443 POSTING_READ(reg);
1444 udelay(150); /* wait for warmup */
1445}
1446
1447/**
50b44a44 1448 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1449 * @dev_priv: i915 private structure
1450 * @pipe: pipe PLL to disable
1451 *
1452 * Disable the PLL for @pipe, making sure the pipe is off first.
1453 *
1454 * Note! This is for pre-ILK only.
1455 */
50b44a44 1456static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1457{
63d7bbe9
JB		 1458 /* Don't disable pipe A or pipe A PLLs if needed */
1459 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1460 return;
1461
1462 /* Make sure the pipe isn't still relying on us */
1463 assert_pipe_disabled(dev_priv, pipe);
1464
50b44a44
DV		 1465 I915_WRITE(DPLL(pipe), 0);
1466 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1467}
1468
89b667f8
JB		 1469void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1470{
1471 u32 port_mask;
1472
1473 if (!port)
1474 port_mask = DPLL_PORTB_READY_MASK;
1475 else
1476 port_mask = DPLL_PORTC_READY_MASK;
1477
1478 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1479 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1480 'B' + port, I915_READ(DPLL(0)));
1481}
1482
92f2584a 1483/**
e72f9fbf 1484 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1485 * @dev_priv: i915 private structure
1486 * @pipe: pipe PLL to enable
1487 *
1488 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1489 * drives the transcoder clock.
1490 */
e2b78267 1491static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1492{
e2b78267
DV		 1493 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1494 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1495
48da64a8 1496 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1497 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1498 if (WARN_ON(pll == NULL))
48da64a8
CW		 1499 return;
1500
1501 if (WARN_ON(pll->refcount == 0))
1502 return;
ee7b9f93 1503
46edb027
DV		 1504 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1505 pll->name, pll->active, pll->on,
e2b78267 1506 crtc->base.base.id);
92f2584a 1507
cdbd2316
DV		 1508 if (pll->active++) {
1509 WARN_ON(!pll->on);
e9d6944e 1510 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1511 return;
1512 }
f4a091c7 1513 WARN_ON(pll->on);
ee7b9f93 1514
46edb027 1515 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1516 pll->enable(dev_priv, pll);
ee7b9f93 1517 pll->on = true;
92f2584a
JB		 1518}
1519
e2b78267 1520static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1521{
e2b78267
DV		 1522 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1523 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1524
92f2584a
JB		 1525 /* PCH only available on ILK+ */
1526 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1527 if (WARN_ON(pll == NULL))
ee7b9f93 1528 return;
92f2584a 1529
48da64a8
CW		 1530 if (WARN_ON(pll->refcount == 0))
1531 return;
7a419866 1532
46edb027
DV		 1533 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1534 pll->name, pll->active, pll->on,
e2b78267 1535 crtc->base.base.id);
7a419866 1536
48da64a8 1537 if (WARN_ON(pll->active == 0)) {
e9d6944e 1538 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1539 return;
1540 }
1541
e9d6944e 1542 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1543 WARN_ON(!pll->on);
cdbd2316 1544 if (--pll->active)
7a419866 1545 return;
ee7b9f93 1546
46edb027 1547 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1548 pll->disable(dev_priv, pll);
ee7b9f93 1549 pll->on = false;
92f2584a
JB		 1550}
1551
b8a4f404
PZ		 1552static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1553 enum pipe pipe)
040484af 1554{
23670b32 1555 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1556 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1557 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1558 uint32_t reg, val, pipeconf_val;
040484af
JB		 1559
1560 /* PCH only available on ILK+ */
1561 BUG_ON(dev_priv->info->gen < 5);
1562
1563 /* Make sure PCH DPLL is enabled */
e72f9fbf 1564 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1565 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1566
1567 /* FDI must be feeding us bits for PCH ports */
1568 assert_fdi_tx_enabled(dev_priv, pipe);
1569 assert_fdi_rx_enabled(dev_priv, pipe);
1570
23670b32
DV		 1571 if (HAS_PCH_CPT(dev)) {
1572 /* Workaround: Set the timing override bit before enabling the
1573 * pch transcoder. */
1574 reg = TRANS_CHICKEN2(pipe);
1575 val = I915_READ(reg);
1576 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1577 I915_WRITE(reg, val);
59c859d6 1578 }
23670b32 1579
ab9412ba 1580 reg = PCH_TRANSCONF(pipe);
040484af 1581 val = I915_READ(reg);
5f7f726d 1582 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1583
1584 if (HAS_PCH_IBX(dev_priv->dev)) {
1585 /*
1586 * make the BPC in transcoder be consistent with
1587 * that in pipeconf reg.
1588 */
dfd07d72
DV		 1589 val &= ~PIPECONF_BPC_MASK;
1590 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1591 }
5f7f726d
PZ		 1592
1593 val &= ~TRANS_INTERLACE_MASK;
1594 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1595 if (HAS_PCH_IBX(dev_priv->dev) &&
1596 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1597 val |= TRANS_LEGACY_INTERLACED_ILK;
1598 else
1599 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1600 else
1601 val |= TRANS_PROGRESSIVE;
1602
040484af
JB		 1603 I915_WRITE(reg, val | TRANS_ENABLE);
1604 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1605 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1606}
1607
8fb033d7 1608static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1609 enum transcoder cpu_transcoder)
040484af 1610{
8fb033d7 1611 u32 val, pipeconf_val;
8fb033d7
PZ		 1612
1613 /* PCH only available on ILK+ */
1614 BUG_ON(dev_priv->info->gen < 5);
1615
8fb033d7 1616 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1617 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1618 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1619
223a6fdf
PZ		 1620 /* Workaround: set timing override bit. */
1621 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1622 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1623 I915_WRITE(_TRANSA_CHICKEN2, val);
1624
25f3ef11 1625 val = TRANS_ENABLE;
937bb610 1626 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1627
9a76b1c6
PZ		 1628 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1629 PIPECONF_INTERLACED_ILK)
a35f2679 1630 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1631 else
1632 val |= TRANS_PROGRESSIVE;
1633
ab9412ba
DV		 1634 I915_WRITE(LPT_TRANSCONF, val);
1635 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1636 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1637}
1638
b8a4f404
PZ		 1639static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1640 enum pipe pipe)
040484af 1641{
23670b32
DV		 1642 struct drm_device *dev = dev_priv->dev;
1643 uint32_t reg, val;
040484af
JB		 1644
1645 /* FDI relies on the transcoder */
1646 assert_fdi_tx_disabled(dev_priv, pipe);
1647 assert_fdi_rx_disabled(dev_priv, pipe);
1648
291906f1
JB		 1649 /* Ports must be off as well */
1650 assert_pch_ports_disabled(dev_priv, pipe);
1651
ab9412ba 1652 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1653 val = I915_READ(reg);
1654 val &= ~TRANS_ENABLE;
1655 I915_WRITE(reg, val);
1656 /* wait for PCH transcoder off, transcoder state */
1657 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1658 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1659
1660 if (!HAS_PCH_IBX(dev)) {
1661 /* Workaround: Clear the timing override chicken bit again. */
1662 reg = TRANS_CHICKEN2(pipe);
1663 val = I915_READ(reg);
1664 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1665 I915_WRITE(reg, val);
1666 }
040484af
JB		 1667}
1668
ab4d966c 1669static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1670{
8fb033d7
PZ		 1671 u32 val;
1672
ab9412ba 1673 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1674 val &= ~TRANS_ENABLE;
ab9412ba 1675 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1676 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1677 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1678 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1679
1680 /* Workaround: clear timing override bit. */
1681 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1682 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1683 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1684}
1685
b24e7179 1686/**
309cfea8 1687 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1688 * @dev_priv: i915 private structure
1689 * @pipe: pipe to enable
040484af 1690 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1691 *
1692 * Enable @pipe, making sure that various hardware specific requirements
1693 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1694 *
1695 * @pipe should be %PIPE_A or %PIPE_B.
1696 *
1697 * Will wait until the pipe is actually running (i.e. first vblank) before
1698 * returning.
1699 */
040484af 1700static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1701 bool pch_port, bool dsi)
b24e7179 1702{
702e7a56
PZ		 1703 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1704 pipe);
1a240d4d 1705 enum pipe pch_transcoder;
b24e7179
JB		 1706 int reg;
1707 u32 val;
1708
58c6eaa2 1709 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1710 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 1711 assert_sprites_disabled(dev_priv, pipe);
1712
681e5811 1713 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1714 pch_transcoder = TRANSCODER_A;
1715 else
1716 pch_transcoder = pipe;
1717
b24e7179
JB		 1718 /*
1719 * A pipe without a PLL won't actually be able to drive bits from
1720 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1721 * need the check.
1722 */
1723 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1724 if (dsi)
1725 assert_dsi_pll_enabled(dev_priv);
1726 else
1727 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1728 else {
1729 if (pch_port) {
1730 /* if driving the PCH, we need FDI enabled */
cc391bbb 1731 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1732 assert_fdi_tx_pll_enabled(dev_priv,
1733 (enum pipe) cpu_transcoder);
040484af
JB		 1734 }
1735 /* FIXME: assert CPU port conditions for SNB+ */
1736 }
b24e7179 1737
702e7a56 1738 reg = PIPECONF(cpu_transcoder);
b24e7179 1739 val = I915_READ(reg);
00d70b15
CW		 1740 if (val & PIPECONF_ENABLE)
1741 return;
1742
1743 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1744 intel_wait_for_vblank(dev_priv->dev, pipe);
1745}
1746
1747/**
309cfea8 1748 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1749 * @dev_priv: i915 private structure
1750 * @pipe: pipe to disable
1751 *
1752 * Disable @pipe, making sure that various hardware specific requirements
1753 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1754 *
1755 * @pipe should be %PIPE_A or %PIPE_B.
1756 *
1757 * Will wait until the pipe has shut down before returning.
1758 */
1759static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1760 enum pipe pipe)
1761{
702e7a56
PZ		 1762 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1763 pipe);
b24e7179
JB		 1764 int reg;
1765 u32 val;
1766
1767 /*
1768 * Make sure planes won't keep trying to pump pixels to us,
1769 * or we might hang the display.
1770 */
1771 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1772 assert_cursor_disabled(dev_priv, pipe);
19332d7a 1773 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1774
1775 /* Don't disable pipe A or pipe A PLLs if needed */
1776 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1777 return;
1778
702e7a56 1779 reg = PIPECONF(cpu_transcoder);
b24e7179 1780 val = I915_READ(reg);
00d70b15
CW		 1781 if ((val & PIPECONF_ENABLE) == 0)
1782 return;
1783
1784 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1785 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1786}
1787
d74362c9
KP		 1788/*
1789 * Plane regs are double buffered, going from enabled->disabled needs a
1790 * trigger in order to latch. The display address reg provides this.
1791 */
6f1d69b0 1792void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1793 enum plane plane)
1794{
14f86147
DL		 1795 if (dev_priv->info->gen >= 4)
1796 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1797 else
1798 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1799}
1800
b24e7179
JB		 1801/**
1802 * intel_enable_plane - enable a display plane on a given pipe
1803 * @dev_priv: i915 private structure
1804 * @plane: plane to enable
1805 * @pipe: pipe being fed
1806 *
1807 * Enable @plane on @pipe, making sure that @pipe is running first.
1808 */
1809static void intel_enable_plane(struct drm_i915_private *dev_priv,
1810 enum plane plane, enum pipe pipe)
1811{
1812 int reg;
1813 u32 val;
1814
1815 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1816 assert_pipe_enabled(dev_priv, pipe);
1817
1818 reg = DSPCNTR(plane);
1819 val = I915_READ(reg);
00d70b15
CW		 1820 if (val & DISPLAY_PLANE_ENABLE)
1821 return;
1822
1823 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1824 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1825 intel_wait_for_vblank(dev_priv->dev, pipe);
1826}
1827
b24e7179
JB		 1828/**
1829 * intel_disable_plane - disable a display plane
1830 * @dev_priv: i915 private structure
1831 * @plane: plane to disable
1832 * @pipe: pipe consuming the data
1833 *
1834 * Disable @plane; should be an independent operation.
1835 */
1836static void intel_disable_plane(struct drm_i915_private *dev_priv,
1837 enum plane plane, enum pipe pipe)
1838{
1839 int reg;
1840 u32 val;
1841
1842 reg = DSPCNTR(plane);
1843 val = I915_READ(reg);
00d70b15
CW		 1844 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1845 return;
1846
1847 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1848 intel_flush_display_plane(dev_priv, plane);
1849 intel_wait_for_vblank(dev_priv->dev, pipe);
1850}
1851
693db184
CW		 1852static bool need_vtd_wa(struct drm_device *dev)
1853{
1854#ifdef CONFIG_INTEL_IOMMU
1855 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1856 return true;
1857#endif
1858 return false;
1859}
1860
127bd2ac 1861int
48b956c5 1862intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1863 struct drm_i915_gem_object *obj,
919926ae 1864 struct intel_ring_buffer *pipelined)
6b95a207 1865{
ce453d81 1866 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1867 u32 alignment;
1868 int ret;
1869
05394f39 1870 switch (obj->tiling_mode) {
6b95a207 1871 case I915_TILING_NONE:
534843da
CW		 1872 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1873 alignment = 128 * 1024;
a6c45cf0 1874 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1875 alignment = 4 * 1024;
1876 else
1877 alignment = 64 * 1024;
6b95a207
KH		 1878 break;
1879 case I915_TILING_X:
1880 /* pin() will align the object as required by fence */
1881 alignment = 0;
1882 break;
1883 case I915_TILING_Y:
8bb6e959
DV		 1884 /* Despite that we check this in framebuffer_init userspace can
1885 * screw us over and change the tiling after the fact. Only
1886 * pinned buffers can't change their tiling. */
1887 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1888 return -EINVAL;
1889 default:
1890 BUG();
1891 }
1892
693db184
CW		 1893 /* Note that the w/a also requires 64 PTE of padding following the
1894 * bo. We currently fill all unused PTE with the shadow page and so
1895 * we should always have valid PTE following the scanout preventing
1896 * the VT-d warning.
1897 */
1898 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1899 alignment = 256 * 1024;
1900
ce453d81 1901 dev_priv->mm.interruptible = false;
2da3b9b9 1902 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1903 if (ret)
ce453d81 1904 goto err_interruptible;
6b95a207
KH		 1905
1906 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1907 * fence, whereas 965+ only requires a fence if using
1908 * framebuffer compression. For simplicity, we always install
1909 * a fence as the cost is not that onerous.
1910 */
06d98131 1911 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1912 if (ret)
1913 goto err_unpin;
1690e1eb 1914
9a5a53b3 1915 i915_gem_object_pin_fence(obj);
6b95a207 1916
ce453d81 1917 dev_priv->mm.interruptible = true;
6b95a207 1918 return 0;
48b956c5
CW		 1919
1920err_unpin:
cc98b413 1921 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1922err_interruptible:
1923 dev_priv->mm.interruptible = true;
48b956c5 1924 return ret;
6b95a207
KH		 1925}
1926
1690e1eb
CW		 1927void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1928{
1929 i915_gem_object_unpin_fence(obj);
cc98b413 1930 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1931}
1932
c2c75131
DV		 1933/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1934 * is assumed to be a power-of-two. */
bc752862
CW		 1935unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1936 unsigned int tiling_mode,
1937 unsigned int cpp,
1938 unsigned int pitch)
c2c75131 1939{
bc752862
CW		 1940 if (tiling_mode != I915_TILING_NONE) {
1941 unsigned int tile_rows, tiles;
c2c75131 1942
bc752862
CW		 1943 tile_rows = *y / 8;
1944 *y %= 8;
c2c75131 1945
bc752862
CW		 1946 tiles = *x / (512/cpp);
1947 *x %= 512/cpp;
1948
1949 return tile_rows * pitch * 8 + tiles * 4096;
1950 } else {
1951 unsigned int offset;
1952
1953 offset = *y * pitch + *x * cpp;
1954 *y = 0;
1955 *x = (offset & 4095) / cpp;
1956 return offset & -4096;
1957 }
c2c75131
DV		 1958}
1959
17638cd6
JB		 1960static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1961 int x, int y)
81255565
JB		 1962{
1963 struct drm_device *dev = crtc->dev;
1964 struct drm_i915_private *dev_priv = dev->dev_private;
1965 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1966 struct intel_framebuffer *intel_fb;
05394f39 1967 struct drm_i915_gem_object *obj;
81255565 1968 int plane = intel_crtc->plane;
e506a0c6 1969 unsigned long linear_offset;
81255565 1970 u32 dspcntr;
5eddb70b 1971 u32 reg;
81255565
JB		 1972
1973 switch (plane) {
1974 case 0:
1975 case 1:
1976 break;
1977 default:
84f44ce7 1978 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1979 return -EINVAL;
1980 }
1981
1982 intel_fb = to_intel_framebuffer(fb);
1983 obj = intel_fb->obj;
81255565 1984
5eddb70b
CW		 1985 reg = DSPCNTR(plane);
1986 dspcntr = I915_READ(reg);
81255565
JB		 1987 /* Mask out pixel format bits in case we change it */
1988 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1989 switch (fb->pixel_format) {
1990 case DRM_FORMAT_C8:
81255565
JB		 1991 dspcntr |= DISPPLANE_8BPP;
1992 break;
57779d06
VS		 1993 case DRM_FORMAT_XRGB1555:
1994 case DRM_FORMAT_ARGB1555:
1995 dspcntr |= DISPPLANE_BGRX555;
81255565 1996 break;
57779d06
VS		 1997 case DRM_FORMAT_RGB565:
1998 dspcntr |= DISPPLANE_BGRX565;
1999 break;
2000 case DRM_FORMAT_XRGB8888:
2001 case DRM_FORMAT_ARGB8888:
2002 dspcntr |= DISPPLANE_BGRX888;
2003 break;
2004 case DRM_FORMAT_XBGR8888:
2005 case DRM_FORMAT_ABGR8888:
2006 dspcntr |= DISPPLANE_RGBX888;
2007 break;
2008 case DRM_FORMAT_XRGB2101010:
2009 case DRM_FORMAT_ARGB2101010:
2010 dspcntr |= DISPPLANE_BGRX101010;
2011 break;
2012 case DRM_FORMAT_XBGR2101010:
2013 case DRM_FORMAT_ABGR2101010:
2014 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2015 break;
2016 default:
baba133a 2017 BUG();
81255565 2018 }
57779d06 2019
a6c45cf0 2020 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2021 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2022 dspcntr |= DISPPLANE_TILED;
2023 else
2024 dspcntr &= ~DISPPLANE_TILED;
2025 }
2026
de1aa629
VS		 2027 if (IS_G4X(dev))
2028 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2029
5eddb70b 2030 I915_WRITE(reg, dspcntr);
81255565 2031
e506a0c6 2032 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2033
c2c75131
DV		 2034 if (INTEL_INFO(dev)->gen >= 4) {
2035 intel_crtc->dspaddr_offset =
bc752862
CW		 2036 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2037 fb->bits_per_pixel / 8,
2038 fb->pitches[0]);
c2c75131
DV		 2039 linear_offset -= intel_crtc->dspaddr_offset;
2040 } else {
e506a0c6 2041 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2042 }
e506a0c6 2043
f343c5f6
BW		 2044 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2045 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2046 fb->pitches[0]);
01f2c773 2047 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2048 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2049 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2050 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2051 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2052 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2053 } else
f343c5f6 2054 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2055 POSTING_READ(reg);
81255565 2056
17638cd6
JB		 2057 return 0;
2058}
2059
2060static int ironlake_update_plane(struct drm_crtc *crtc,
2061 struct drm_framebuffer *fb, int x, int y)
2062{
2063 struct drm_device *dev = crtc->dev;
2064 struct drm_i915_private *dev_priv = dev->dev_private;
2065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2066 struct intel_framebuffer *intel_fb;
2067 struct drm_i915_gem_object *obj;
2068 int plane = intel_crtc->plane;
e506a0c6 2069 unsigned long linear_offset;
17638cd6
JB		 2070 u32 dspcntr;
2071 u32 reg;
2072
2073 switch (plane) {
2074 case 0:
2075 case 1:
27f8227b 2076 case 2:
17638cd6
JB		 2077 break;
2078 default:
84f44ce7 2079 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2080 return -EINVAL;
2081 }
2082
2083 intel_fb = to_intel_framebuffer(fb);
2084 obj = intel_fb->obj;
2085
2086 reg = DSPCNTR(plane);
2087 dspcntr = I915_READ(reg);
2088 /* Mask out pixel format bits in case we change it */
2089 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2090 switch (fb->pixel_format) {
2091 case DRM_FORMAT_C8:
17638cd6
JB		 2092 dspcntr |= DISPPLANE_8BPP;
2093 break;
57779d06
VS		 2094 case DRM_FORMAT_RGB565:
2095 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2096 break;
57779d06
VS		 2097 case DRM_FORMAT_XRGB8888:
2098 case DRM_FORMAT_ARGB8888:
2099 dspcntr |= DISPPLANE_BGRX888;
2100 break;
2101 case DRM_FORMAT_XBGR8888:
2102 case DRM_FORMAT_ABGR8888:
2103 dspcntr |= DISPPLANE_RGBX888;
2104 break;
2105 case DRM_FORMAT_XRGB2101010:
2106 case DRM_FORMAT_ARGB2101010:
2107 dspcntr |= DISPPLANE_BGRX101010;
2108 break;
2109 case DRM_FORMAT_XBGR2101010:
2110 case DRM_FORMAT_ABGR2101010:
2111 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2112 break;
2113 default:
baba133a 2114 BUG();
17638cd6
JB		 2115 }
2116
2117 if (obj->tiling_mode != I915_TILING_NONE)
2118 dspcntr |= DISPPLANE_TILED;
2119 else
2120 dspcntr &= ~DISPPLANE_TILED;
2121
1f5d76db
PZ		 2122 if (IS_HASWELL(dev))
2123 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2124 else
2125 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2126
2127 I915_WRITE(reg, dspcntr);
2128
e506a0c6 2129 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2130 intel_crtc->dspaddr_offset =
bc752862
CW		 2131 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2132 fb->bits_per_pixel / 8,
2133 fb->pitches[0]);
c2c75131 2134 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2135
f343c5f6
BW		 2136 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2137 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2138 fb->pitches[0]);
01f2c773 2139 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2140 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2141 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2142 if (IS_HASWELL(dev)) {
2143 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2144 } else {
2145 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2146 I915_WRITE(DSPLINOFF(plane), linear_offset);
2147 }
17638cd6
JB		 2148 POSTING_READ(reg);
2149
2150 return 0;
2151}
2152
2153/* Assume fb object is pinned & idle & fenced and just update base pointers */
2154static int
2155intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2156 int x, int y, enum mode_set_atomic state)
2157{
2158 struct drm_device *dev = crtc->dev;
2159 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2160
6b8e6ed0
CW		 2161 if (dev_priv->display.disable_fbc)
2162 dev_priv->display.disable_fbc(dev);
3dec0095 2163 intel_increase_pllclock(crtc);
81255565 2164
6b8e6ed0 2165 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2166}
2167
96a02917
VS		 2168void intel_display_handle_reset(struct drm_device *dev)
2169{
2170 struct drm_i915_private *dev_priv = dev->dev_private;
2171 struct drm_crtc *crtc;
2172
2173 /*
2174 * Flips in the rings have been nuked by the reset,
2175 * so complete all pending flips so that user space
2176 * will get its events and not get stuck.
2177 *
2178 * Also update the base address of all primary
2179 * planes to the the last fb to make sure we're
2180 * showing the correct fb after a reset.
2181 *
2182 * Need to make two loops over the crtcs so that we
2183 * don't try to grab a crtc mutex before the
2184 * pending_flip_queue really got woken up.
2185 */
2186
2187 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2189 enum plane plane = intel_crtc->plane;
2190
2191 intel_prepare_page_flip(dev, plane);
2192 intel_finish_page_flip_plane(dev, plane);
2193 }
2194
2195 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2197
2198 mutex_lock(&crtc->mutex);
2199 if (intel_crtc->active)
2200 dev_priv->display.update_plane(crtc, crtc->fb,
2201 crtc->x, crtc->y);
2202 mutex_unlock(&crtc->mutex);
2203 }
2204}
2205
14667a4b
CW		 2206static int
2207intel_finish_fb(struct drm_framebuffer *old_fb)
2208{
2209 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2210 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2211 bool was_interruptible = dev_priv->mm.interruptible;
2212 int ret;
2213
14667a4b
CW		 2214 /* Big Hammer, we also need to ensure that any pending
2215 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2216 * current scanout is retired before unpinning the old
2217 * framebuffer.
2218 *
2219 * This should only fail upon a hung GPU, in which case we
2220 * can safely continue.
2221 */
2222 dev_priv->mm.interruptible = false;
2223 ret = i915_gem_object_finish_gpu(obj);
2224 dev_priv->mm.interruptible = was_interruptible;
2225
2226 return ret;
2227}
2228
198598d0
VS		 2229static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2230{
2231 struct drm_device *dev = crtc->dev;
2232 struct drm_i915_master_private *master_priv;
2233 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2234
2235 if (!dev->primary->master)
2236 return;
2237
2238 master_priv = dev->primary->master->driver_priv;
2239 if (!master_priv->sarea_priv)
2240 return;
2241
2242 switch (intel_crtc->pipe) {
2243 case 0:
2244 master_priv->sarea_priv->pipeA_x = x;
2245 master_priv->sarea_priv->pipeA_y = y;
2246 break;
2247 case 1:
2248 master_priv->sarea_priv->pipeB_x = x;
2249 master_priv->sarea_priv->pipeB_y = y;
2250 break;
2251 default:
2252 break;
2253 }
2254}
2255
5c3b82e2 2256static int
3c4fdcfb 2257intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2258 struct drm_framebuffer *fb)
79e53945
JB		 2259{
2260 struct drm_device *dev = crtc->dev;
6b8e6ed0 2261 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2262 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2263 struct drm_framebuffer *old_fb;
5c3b82e2 2264 int ret;
79e53945
JB		 2265
2266 /* no fb bound */
94352cf9 2267 if (!fb) {
a5071c2f 2268 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2269 return 0;
2270 }
2271
7eb552ae 2272 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2273 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2274 plane_name(intel_crtc->plane),
2275 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2276 return -EINVAL;
79e53945
JB		 2277 }
2278
5c3b82e2 2279 mutex_lock(&dev->struct_mutex);
265db958 2280 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2281 to_intel_framebuffer(fb)->obj,
919926ae 2282 NULL);
5c3b82e2
CW		 2283 if (ret != 0) {
2284 mutex_unlock(&dev->struct_mutex);
a5071c2f 2285 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2286 return ret;
2287 }
79e53945 2288
4d6a3e63
JB		 2289 /* Update pipe size and adjust fitter if needed */
2290 if (i915_fastboot) {
2291 I915_WRITE(PIPESRC(intel_crtc->pipe),
2292 ((crtc->mode.hdisplay - 1) << 16) |
2293 (crtc->mode.vdisplay - 1));
2294 if (!intel_crtc->config.pch_pfit.size &&
2295 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2296 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2297 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2298 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2299 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2300 }
2301 }
2302
94352cf9 2303 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2304 if (ret) {
94352cf9 2305 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2306 mutex_unlock(&dev->struct_mutex);
a5071c2f 2307 DRM_ERROR("failed to update base address\n");
4e6cfefc 2308 return ret;
79e53945 2309 }
3c4fdcfb 2310
94352cf9
DV		 2311 old_fb = crtc->fb;
2312 crtc->fb = fb;
6c4c86f5
DV		 2313 crtc->x = x;
2314 crtc->y = y;
94352cf9 2315
b7f1de28 2316 if (old_fb) {
d7697eea
DV		 2317 if (intel_crtc->active && old_fb != fb)
2318 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2319 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2320 }
652c393a 2321
6b8e6ed0 2322 intel_update_fbc(dev);
4906557e 2323 intel_edp_psr_update(dev);
5c3b82e2 2324 mutex_unlock(&dev->struct_mutex);
79e53945 2325
198598d0 2326 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2327
2328 return 0;
79e53945
JB		 2329}
2330
5e84e1a4
ZW		 2331static void intel_fdi_normal_train(struct drm_crtc *crtc)
2332{
2333 struct drm_device *dev = crtc->dev;
2334 struct drm_i915_private *dev_priv = dev->dev_private;
2335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2336 int pipe = intel_crtc->pipe;
2337 u32 reg, temp;
2338
2339 /* enable normal train */
2340 reg = FDI_TX_CTL(pipe);
2341 temp = I915_READ(reg);
61e499bf 2342 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2343 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2344 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2345 } else {
2346 temp &= ~FDI_LINK_TRAIN_NONE;
2347 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2348 }
5e84e1a4
ZW		 2349 I915_WRITE(reg, temp);
2350
2351 reg = FDI_RX_CTL(pipe);
2352 temp = I915_READ(reg);
2353 if (HAS_PCH_CPT(dev)) {
2354 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2355 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2356 } else {
2357 temp &= ~FDI_LINK_TRAIN_NONE;
2358 temp |= FDI_LINK_TRAIN_NONE;
2359 }
2360 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2361
2362 /* wait one idle pattern time */
2363 POSTING_READ(reg);
2364 udelay(1000);
357555c0
JB		 2365
2366 /* IVB wants error correction enabled */
2367 if (IS_IVYBRIDGE(dev))
2368 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2369 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2370}
2371
1e833f40
DV		 2372static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2373{
2374 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2375}
2376
01a415fd
DV		 2377static void ivb_modeset_global_resources(struct drm_device *dev)
2378{
2379 struct drm_i915_private *dev_priv = dev->dev_private;
2380 struct intel_crtc *pipe_B_crtc =
2381 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2382 struct intel_crtc *pipe_C_crtc =
2383 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2384 uint32_t temp;
2385
1e833f40
DV		 2386 /*
2387 * When everything is off disable fdi C so that we could enable fdi B
2388 * with all lanes. Note that we don't care about enabled pipes without
2389 * an enabled pch encoder.
2390 */
2391 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2392 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2393 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2394 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2395
2396 temp = I915_READ(SOUTH_CHICKEN1);
2397 temp &= ~FDI_BC_BIFURCATION_SELECT;
2398 DRM_DEBUG_KMS("disabling fdi C rx\n");
2399 I915_WRITE(SOUTH_CHICKEN1, temp);
2400 }
2401}
2402
8db9d77b
ZW		 2403/* The FDI link training functions for ILK/Ibexpeak. */
2404static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2405{
2406 struct drm_device *dev = crtc->dev;
2407 struct drm_i915_private *dev_priv = dev->dev_private;
2408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409 int pipe = intel_crtc->pipe;
0fc932b8 2410 int plane = intel_crtc->plane;
5eddb70b 2411 u32 reg, temp, tries;
8db9d77b 2412
0fc932b8
JB		 2413 /* FDI needs bits from pipe & plane first */
2414 assert_pipe_enabled(dev_priv, pipe);
2415 assert_plane_enabled(dev_priv, plane);
2416
e1a44743
AJ		 2417 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2418 for train result */
5eddb70b
CW		 2419 reg = FDI_RX_IMR(pipe);
2420 temp = I915_READ(reg);
e1a44743
AJ		 2421 temp &= ~FDI_RX_SYMBOL_LOCK;
2422 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2423 I915_WRITE(reg, temp);
2424 I915_READ(reg);
e1a44743
AJ		 2425 udelay(150);
2426
8db9d77b 2427 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2428 reg = FDI_TX_CTL(pipe);
2429 temp = I915_READ(reg);
627eb5a3
DV		 2430 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2431 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2434 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2435
5eddb70b
CW		 2436 reg = FDI_RX_CTL(pipe);
2437 temp = I915_READ(reg);
8db9d77b
ZW		 2438 temp &= ~FDI_LINK_TRAIN_NONE;
2439 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2440 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2441
2442 POSTING_READ(reg);
8db9d77b
ZW		 2443 udelay(150);
2444
5b2adf89 2445 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2447 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2448 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2449
5eddb70b 2450 reg = FDI_RX_IIR(pipe);
e1a44743 2451 for (tries = 0; tries < 5; tries++) {
5eddb70b 2452 temp = I915_READ(reg);
8db9d77b
ZW		 2453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455 if ((temp & FDI_RX_BIT_LOCK)) {
2456 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2457 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2458 break;
2459 }
8db9d77b 2460 }
e1a44743 2461 if (tries == 5)
5eddb70b 2462 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2463
2464 /* Train 2 */
5eddb70b
CW		 2465 reg = FDI_TX_CTL(pipe);
2466 temp = I915_READ(reg);
8db9d77b
ZW		 2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2469 I915_WRITE(reg, temp);
8db9d77b 2470
5eddb70b
CW		 2471 reg = FDI_RX_CTL(pipe);
2472 temp = I915_READ(reg);
8db9d77b
ZW		 2473 temp &= ~FDI_LINK_TRAIN_NONE;
2474 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2475 I915_WRITE(reg, temp);
8db9d77b 2476
5eddb70b
CW		 2477 POSTING_READ(reg);
2478 udelay(150);
8db9d77b 2479
5eddb70b 2480 reg = FDI_RX_IIR(pipe);
e1a44743 2481 for (tries = 0; tries < 5; tries++) {
5eddb70b 2482 temp = I915_READ(reg);
8db9d77b
ZW		 2483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484
2485 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2486 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2487 DRM_DEBUG_KMS("FDI train 2 done.\n");
2488 break;
2489 }
8db9d77b 2490 }
e1a44743 2491 if (tries == 5)
5eddb70b 2492 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2493
2494 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2495
8db9d77b
ZW		 2496}
2497
0206e353 2498static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2499 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2500 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2501 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2502 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2503};
2504
2505/* The FDI link training functions for SNB/Cougarpoint. */
2506static void gen6_fdi_link_train(struct drm_crtc *crtc)
2507{
2508 struct drm_device *dev = crtc->dev;
2509 struct drm_i915_private *dev_priv = dev->dev_private;
2510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2511 int pipe = intel_crtc->pipe;
fa37d39e 2512 u32 reg, temp, i, retry;
8db9d77b 2513
e1a44743
AJ		 2514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2515 for train result */
5eddb70b
CW		 2516 reg = FDI_RX_IMR(pipe);
2517 temp = I915_READ(reg);
e1a44743
AJ		 2518 temp &= ~FDI_RX_SYMBOL_LOCK;
2519 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2520 I915_WRITE(reg, temp);
2521
2522 POSTING_READ(reg);
e1a44743
AJ		 2523 udelay(150);
2524
8db9d77b 2525 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2526 reg = FDI_TX_CTL(pipe);
2527 temp = I915_READ(reg);
627eb5a3
DV		 2528 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2529 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2530 temp &= ~FDI_LINK_TRAIN_NONE;
2531 temp |= FDI_LINK_TRAIN_PATTERN_1;
2532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2533 /* SNB-B */
2534 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2535 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2536
d74cf324
DV		 2537 I915_WRITE(FDI_RX_MISC(pipe),
2538 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2539
5eddb70b
CW		 2540 reg = FDI_RX_CTL(pipe);
2541 temp = I915_READ(reg);
8db9d77b
ZW		 2542 if (HAS_PCH_CPT(dev)) {
2543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2545 } else {
2546 temp &= ~FDI_LINK_TRAIN_NONE;
2547 temp |= FDI_LINK_TRAIN_PATTERN_1;
2548 }
5eddb70b
CW		 2549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2550
2551 POSTING_READ(reg);
8db9d77b
ZW		 2552 udelay(150);
2553
0206e353 2554 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2555 reg = FDI_TX_CTL(pipe);
2556 temp = I915_READ(reg);
8db9d77b
ZW		 2557 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2558 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2559 I915_WRITE(reg, temp);
2560
2561 POSTING_READ(reg);
8db9d77b
ZW		 2562 udelay(500);
2563
fa37d39e
SP		 2564 for (retry = 0; retry < 5; retry++) {
2565 reg = FDI_RX_IIR(pipe);
2566 temp = I915_READ(reg);
2567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2568 if (temp & FDI_RX_BIT_LOCK) {
2569 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2570 DRM_DEBUG_KMS("FDI train 1 done.\n");
2571 break;
2572 }
2573 udelay(50);
8db9d77b 2574 }
fa37d39e
SP		 2575 if (retry < 5)
2576 break;
8db9d77b
ZW		 2577 }
2578 if (i == 4)
5eddb70b 2579 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2580
2581 /* Train 2 */
5eddb70b
CW		 2582 reg = FDI_TX_CTL(pipe);
2583 temp = I915_READ(reg);
8db9d77b
ZW		 2584 temp &= ~FDI_LINK_TRAIN_NONE;
2585 temp |= FDI_LINK_TRAIN_PATTERN_2;
2586 if (IS_GEN6(dev)) {
2587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588 /* SNB-B */
2589 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2590 }
5eddb70b 2591 I915_WRITE(reg, temp);
8db9d77b 2592
5eddb70b
CW		 2593 reg = FDI_RX_CTL(pipe);
2594 temp = I915_READ(reg);
8db9d77b
ZW		 2595 if (HAS_PCH_CPT(dev)) {
2596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2598 } else {
2599 temp &= ~FDI_LINK_TRAIN_NONE;
2600 temp |= FDI_LINK_TRAIN_PATTERN_2;
2601 }
5eddb70b
CW		 2602 I915_WRITE(reg, temp);
2603
2604 POSTING_READ(reg);
8db9d77b
ZW		 2605 udelay(150);
2606
0206e353 2607 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2608 reg = FDI_TX_CTL(pipe);
2609 temp = I915_READ(reg);
8db9d77b
ZW		 2610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2612 I915_WRITE(reg, temp);
2613
2614 POSTING_READ(reg);
8db9d77b
ZW		 2615 udelay(500);
2616
fa37d39e
SP		 2617 for (retry = 0; retry < 5; retry++) {
2618 reg = FDI_RX_IIR(pipe);
2619 temp = I915_READ(reg);
2620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621 if (temp & FDI_RX_SYMBOL_LOCK) {
2622 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2623 DRM_DEBUG_KMS("FDI train 2 done.\n");
2624 break;
2625 }
2626 udelay(50);
8db9d77b 2627 }
fa37d39e
SP		 2628 if (retry < 5)
2629 break;
8db9d77b
ZW		 2630 }
2631 if (i == 4)
5eddb70b 2632 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2633
2634 DRM_DEBUG_KMS("FDI train done.\n");
2635}
2636
357555c0
JB		 2637/* Manual link training for Ivy Bridge A0 parts */
2638static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2639{
2640 struct drm_device *dev = crtc->dev;
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643 int pipe = intel_crtc->pipe;
139ccd3f 2644 u32 reg, temp, i, j;
357555c0
JB		 2645
2646 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2647 for train result */
2648 reg = FDI_RX_IMR(pipe);
2649 temp = I915_READ(reg);
2650 temp &= ~FDI_RX_SYMBOL_LOCK;
2651 temp &= ~FDI_RX_BIT_LOCK;
2652 I915_WRITE(reg, temp);
2653
2654 POSTING_READ(reg);
2655 udelay(150);
2656
01a415fd
DV		 2657 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2658 I915_READ(FDI_RX_IIR(pipe)));
2659
139ccd3f
JB		 2660 /* Try each vswing and preemphasis setting twice before moving on */
2661 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2662 /* disable first in case we need to retry */
2663 reg = FDI_TX_CTL(pipe);
2664 temp = I915_READ(reg);
2665 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2666 temp &= ~FDI_TX_ENABLE;
2667 I915_WRITE(reg, temp);
357555c0 2668
139ccd3f
JB		 2669 reg = FDI_RX_CTL(pipe);
2670 temp = I915_READ(reg);
2671 temp &= ~FDI_LINK_TRAIN_AUTO;
2672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2673 temp &= ~FDI_RX_ENABLE;
2674 I915_WRITE(reg, temp);
357555c0 2675
139ccd3f 2676 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2677 reg = FDI_TX_CTL(pipe);
2678 temp = I915_READ(reg);
139ccd3f
JB		 2679 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2680 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2681 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2682 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2683 temp |= snb_b_fdi_train_param[j/2];
2684 temp |= FDI_COMPOSITE_SYNC;
2685 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2686
139ccd3f
JB		 2687 I915_WRITE(FDI_RX_MISC(pipe),
2688 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2689
139ccd3f 2690 reg = FDI_RX_CTL(pipe);
357555c0 2691 temp = I915_READ(reg);
139ccd3f
JB		 2692 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2693 temp |= FDI_COMPOSITE_SYNC;
2694 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2695
139ccd3f
JB		 2696 POSTING_READ(reg);
2697 udelay(1); /* should be 0.5us */
357555c0 2698
139ccd3f
JB		 2699 for (i = 0; i < 4; i++) {
2700 reg = FDI_RX_IIR(pipe);
2701 temp = I915_READ(reg);
2702 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2703
139ccd3f
JB		 2704 if (temp & FDI_RX_BIT_LOCK ||
2705 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2706 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2707 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2708 i);
2709 break;
2710 }
2711 udelay(1); /* should be 0.5us */
2712 }
2713 if (i == 4) {
2714 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2715 continue;
2716 }
357555c0 2717
139ccd3f 2718 /* Train 2 */
357555c0
JB		 2719 reg = FDI_TX_CTL(pipe);
2720 temp = I915_READ(reg);
139ccd3f
JB		 2721 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2722 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2723 I915_WRITE(reg, temp);
2724
2725 reg = FDI_RX_CTL(pipe);
2726 temp = I915_READ(reg);
2727 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2728 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2729 I915_WRITE(reg, temp);
2730
2731 POSTING_READ(reg);
139ccd3f 2732 udelay(2); /* should be 1.5us */
357555c0 2733
139ccd3f
JB		 2734 for (i = 0; i < 4; i++) {
2735 reg = FDI_RX_IIR(pipe);
2736 temp = I915_READ(reg);
2737 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2738
139ccd3f
JB		 2739 if (temp & FDI_RX_SYMBOL_LOCK ||
2740 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2741 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2742 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2743 i);
2744 goto train_done;
2745 }
2746 udelay(2); /* should be 1.5us */
357555c0 2747 }
139ccd3f
JB		 2748 if (i == 4)
2749 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2750 }
357555c0 2751
139ccd3f 2752train_done:
357555c0
JB		 2753 DRM_DEBUG_KMS("FDI train done.\n");
2754}
2755
88cefb6c 2756static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2757{
88cefb6c 2758 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2759 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2760 int pipe = intel_crtc->pipe;
5eddb70b 2761 u32 reg, temp;
79e53945 2762
c64e311e 2763
c98e9dcf 2764 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2765 reg = FDI_RX_CTL(pipe);
2766 temp = I915_READ(reg);
627eb5a3
DV		 2767 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2768 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2769 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2770 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2771
2772 POSTING_READ(reg);
c98e9dcf
JB		 2773 udelay(200);
2774
2775 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2776 temp = I915_READ(reg);
2777 I915_WRITE(reg, temp | FDI_PCDCLK);
2778
2779 POSTING_READ(reg);
c98e9dcf
JB		 2780 udelay(200);
2781
20749730
PZ		 2782 /* Enable CPU FDI TX PLL, always on for Ironlake */
2783 reg = FDI_TX_CTL(pipe);
2784 temp = I915_READ(reg);
2785 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2786 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2787
20749730
PZ		 2788 POSTING_READ(reg);
2789 udelay(100);
6be4a607 2790 }
0e23b99d
JB		 2791}
2792
88cefb6c
DV		 2793static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2794{
2795 struct drm_device *dev = intel_crtc->base.dev;
2796 struct drm_i915_private *dev_priv = dev->dev_private;
2797 int pipe = intel_crtc->pipe;
2798 u32 reg, temp;
2799
2800 /* Switch from PCDclk to Rawclk */
2801 reg = FDI_RX_CTL(pipe);
2802 temp = I915_READ(reg);
2803 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2804
2805 /* Disable CPU FDI TX PLL */
2806 reg = FDI_TX_CTL(pipe);
2807 temp = I915_READ(reg);
2808 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2809
2810 POSTING_READ(reg);
2811 udelay(100);
2812
2813 reg = FDI_RX_CTL(pipe);
2814 temp = I915_READ(reg);
2815 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2816
2817 /* Wait for the clocks to turn off. */
2818 POSTING_READ(reg);
2819 udelay(100);
2820}
2821
0fc932b8
JB		 2822static void ironlake_fdi_disable(struct drm_crtc *crtc)
2823{
2824 struct drm_device *dev = crtc->dev;
2825 struct drm_i915_private *dev_priv = dev->dev_private;
2826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2827 int pipe = intel_crtc->pipe;
2828 u32 reg, temp;
2829
2830 /* disable CPU FDI tx and PCH FDI rx */
2831 reg = FDI_TX_CTL(pipe);
2832 temp = I915_READ(reg);
2833 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2834 POSTING_READ(reg);
2835
2836 reg = FDI_RX_CTL(pipe);
2837 temp = I915_READ(reg);
2838 temp &= ~(0x7 << 16);
dfd07d72 2839 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2840 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2841
2842 POSTING_READ(reg);
2843 udelay(100);
2844
2845 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2846 if (HAS_PCH_IBX(dev)) {
2847 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2848 }
0fc932b8
JB		 2849
2850 /* still set train pattern 1 */
2851 reg = FDI_TX_CTL(pipe);
2852 temp = I915_READ(reg);
2853 temp &= ~FDI_LINK_TRAIN_NONE;
2854 temp |= FDI_LINK_TRAIN_PATTERN_1;
2855 I915_WRITE(reg, temp);
2856
2857 reg = FDI_RX_CTL(pipe);
2858 temp = I915_READ(reg);
2859 if (HAS_PCH_CPT(dev)) {
2860 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2861 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2862 } else {
2863 temp &= ~FDI_LINK_TRAIN_NONE;
2864 temp |= FDI_LINK_TRAIN_PATTERN_1;
2865 }
2866 /* BPC in FDI rx is consistent with that in PIPECONF */
2867 temp &= ~(0x07 << 16);
dfd07d72 2868 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2869 I915_WRITE(reg, temp);
2870
2871 POSTING_READ(reg);
2872 udelay(100);
2873}
2874
5bb61643
CW		 2875static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2876{
2877 struct drm_device *dev = crtc->dev;
2878 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2879 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2880 unsigned long flags;
2881 bool pending;
2882
10d83730
VS		 2883 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2884 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2885 return false;
2886
2887 spin_lock_irqsave(&dev->event_lock, flags);
2888 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2889 spin_unlock_irqrestore(&dev->event_lock, flags);
2890
2891 return pending;
2892}
2893
e6c3a2a6
CW		 2894static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2895{
0f91128d 2896 struct drm_device *dev = crtc->dev;
5bb61643 2897 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2898
2899 if (crtc->fb == NULL)
2900 return;
2901
2c10d571
DV		 2902 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2903
5bb61643
CW		 2904 wait_event(dev_priv->pending_flip_queue,
2905 !intel_crtc_has_pending_flip(crtc));
2906
0f91128d
CW		 2907 mutex_lock(&dev->struct_mutex);
2908 intel_finish_fb(crtc->fb);
2909 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2910}
2911
e615efe4
ED		 2912/* Program iCLKIP clock to the desired frequency */
2913static void lpt_program_iclkip(struct drm_crtc *crtc)
2914{
2915 struct drm_device *dev = crtc->dev;
2916 struct drm_i915_private *dev_priv = dev->dev_private;
12d7ceed 2917 int clock = to_intel_crtc(crtc)->config.adjusted_mode.clock;
e615efe4
ED		 2918 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2919 u32 temp;
2920
09153000
DV		 2921 mutex_lock(&dev_priv->dpio_lock);
2922
e615efe4
ED		 2923 /* It is necessary to ungate the pixclk gate prior to programming
2924 * the divisors, and gate it back when it is done.
2925 */
2926 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2927
2928 /* Disable SSCCTL */
2929 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2930 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2931 SBI_SSCCTL_DISABLE,
2932 SBI_ICLK);
e615efe4
ED		 2933
2934 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 2935 if (clock == 20000) {
e615efe4
ED		 2936 auxdiv = 1;
2937 divsel = 0x41;
2938 phaseinc = 0x20;
2939 } else {
2940 /* The iCLK virtual clock root frequency is in MHz,
12d7ceed 2941 * but the adjusted_mode->clock in in KHz. To get the divisors,
e615efe4
ED		 2942 * it is necessary to divide one by another, so we
2943 * convert the virtual clock precision to KHz here for higher
2944 * precision.
2945 */
2946 u32 iclk_virtual_root_freq = 172800 * 1000;
2947 u32 iclk_pi_range = 64;
2948 u32 desired_divisor, msb_divisor_value, pi_value;
2949
12d7ceed 2950 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 2951 msb_divisor_value = desired_divisor / iclk_pi_range;
2952 pi_value = desired_divisor % iclk_pi_range;
2953
2954 auxdiv = 0;
2955 divsel = msb_divisor_value - 2;
2956 phaseinc = pi_value;
2957 }
2958
2959 /* This should not happen with any sane values */
2960 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2961 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2962 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2963 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2964
2965 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 2966 clock,
e615efe4
ED		 2967 auxdiv,
2968 divsel,
2969 phasedir,
2970 phaseinc);
2971
2972 /* Program SSCDIVINTPHASE6 */
988d6ee8 2973 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2974 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2975 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2976 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2977 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2978 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2979 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2980 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2981
2982 /* Program SSCAUXDIV */
988d6ee8 2983 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2984 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2985 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2986 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2987
2988 /* Enable modulator and associated divider */
988d6ee8 2989 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2990 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2991 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2992
2993 /* Wait for initialization time */
2994 udelay(24);
2995
2996 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2997
2998 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2999}
3000
275f01b2
DV		 3001static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3002 enum pipe pch_transcoder)
3003{
3004 struct drm_device *dev = crtc->base.dev;
3005 struct drm_i915_private *dev_priv = dev->dev_private;
3006 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3007
3008 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3009 I915_READ(HTOTAL(cpu_transcoder)));
3010 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3011 I915_READ(HBLANK(cpu_transcoder)));
3012 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3013 I915_READ(HSYNC(cpu_transcoder)));
3014
3015 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3016 I915_READ(VTOTAL(cpu_transcoder)));
3017 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3018 I915_READ(VBLANK(cpu_transcoder)));
3019 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3020 I915_READ(VSYNC(cpu_transcoder)));
3021 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3022 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3023}
3024
f67a559d
JB		 3025/*
3026 * Enable PCH resources required for PCH ports:
3027 * - PCH PLLs
3028 * - FDI training & RX/TX
3029 * - update transcoder timings
3030 * - DP transcoding bits
3031 * - transcoder
3032 */
3033static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3034{
3035 struct drm_device *dev = crtc->dev;
3036 struct drm_i915_private *dev_priv = dev->dev_private;
3037 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3038 int pipe = intel_crtc->pipe;
ee7b9f93 3039 u32 reg, temp;
2c07245f 3040
ab9412ba 3041 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3042
cd986abb
DV		 3043 /* Write the TU size bits before fdi link training, so that error
3044 * detection works. */
3045 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3046 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3047
c98e9dcf 3048 /* For PCH output, training FDI link */
674cf967 3049 dev_priv->display.fdi_link_train(crtc);
2c07245f 3050
3ad8a208
DV		 3051 /* We need to program the right clock selection before writing the pixel
3052 * mutliplier into the DPLL. */
303b81e0 3053 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3054 u32 sel;
4b645f14 3055
c98e9dcf 3056 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3057 temp |= TRANS_DPLL_ENABLE(pipe);
3058 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3059 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3060 temp |= sel;
3061 else
3062 temp &= ~sel;
c98e9dcf 3063 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3064 }
5eddb70b 3065
3ad8a208
DV		 3066 /* XXX: pch pll's can be enabled any time before we enable the PCH
3067 * transcoder, and we actually should do this to not upset any PCH
3068 * transcoder that already use the clock when we share it.
3069 *
3070 * Note that enable_shared_dpll tries to do the right thing, but
3071 * get_shared_dpll unconditionally resets the pll - we need that to have
3072 * the right LVDS enable sequence. */
3073 ironlake_enable_shared_dpll(intel_crtc);
3074
d9b6cb56
JB		 3075 /* set transcoder timing, panel must allow it */
3076 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3077 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3078
303b81e0 3079 intel_fdi_normal_train(crtc);
5e84e1a4 3080
c98e9dcf
JB		 3081 /* For PCH DP, enable TRANS_DP_CTL */
3082 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3083 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3084 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3085 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3086 reg = TRANS_DP_CTL(pipe);
3087 temp = I915_READ(reg);
3088 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3089 TRANS_DP_SYNC_MASK |
3090 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3091 temp |= (TRANS_DP_OUTPUT_ENABLE |
3092 TRANS_DP_ENH_FRAMING);
9325c9f0 3093 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3094
3095 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3096 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3097 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3098 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3099
3100 switch (intel_trans_dp_port_sel(crtc)) {
3101 case PCH_DP_B:
5eddb70b 3102 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3103 break;
3104 case PCH_DP_C:
5eddb70b 3105 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3106 break;
3107 case PCH_DP_D:
5eddb70b 3108 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3109 break;
3110 default:
e95d41e1 3111 BUG();
32f9d658 3112 }
2c07245f 3113
5eddb70b 3114 I915_WRITE(reg, temp);
6be4a607 3115 }
b52eb4dc 3116
b8a4f404 3117 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3118}
3119
1507e5bd
PZ		 3120static void lpt_pch_enable(struct drm_crtc *crtc)
3121{
3122 struct drm_device *dev = crtc->dev;
3123 struct drm_i915_private *dev_priv = dev->dev_private;
3124 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3125 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3126
ab9412ba 3127 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3128
8c52b5e8 3129 lpt_program_iclkip(crtc);
1507e5bd 3130
0540e488 3131 /* Set transcoder timing. */
275f01b2 3132 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3133
937bb610 3134 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3135}
3136
e2b78267 3137static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3138{
e2b78267 3139 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3140
3141 if (pll == NULL)
3142 return;
3143
3144 if (pll->refcount == 0) {
46edb027 3145 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3146 return;
3147 }
3148
f4a091c7
DV		 3149 if (--pll->refcount == 0) {
3150 WARN_ON(pll->on);
3151 WARN_ON(pll->active);
3152 }
3153
a43f6e0f 3154 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3155}
3156
b89a1d39 3157static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3158{
e2b78267
DV		 3159 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3160 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3161 enum intel_dpll_id i;
ee7b9f93 3162
ee7b9f93 3163 if (pll) {
46edb027
DV		 3164 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3165 crtc->base.base.id, pll->name);
e2b78267 3166 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3167 }
3168
98b6bd99
DV		 3169 if (HAS_PCH_IBX(dev_priv->dev)) {
3170 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3171 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3172 pll = &dev_priv->shared_dplls[i];
98b6bd99 3173
46edb027
DV		 3174 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3175 crtc->base.base.id, pll->name);
98b6bd99
DV		 3176
3177 goto found;
3178 }
3179
e72f9fbf
DV		 3180 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3181 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3182
3183 /* Only want to check enabled timings first */
3184 if (pll->refcount == 0)
3185 continue;
3186
b89a1d39
DV		 3187 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3188 sizeof(pll->hw_state)) == 0) {
46edb027 3189 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3190 crtc->base.base.id,
46edb027 3191 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3192
3193 goto found;
3194 }
3195 }
3196
3197 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3198 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3199 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3200 if (pll->refcount == 0) {
46edb027
DV		 3201 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3202 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3203 goto found;
3204 }
3205 }
3206
3207 return NULL;
3208
3209found:
a43f6e0f 3210 crtc->config.shared_dpll = i;
46edb027
DV		 3211 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3212 pipe_name(crtc->pipe));
ee7b9f93 3213
cdbd2316 3214 if (pll->active == 0) {
66e985c0
DV		 3215 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3216 sizeof(pll->hw_state));
3217
46edb027 3218 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3219 WARN_ON(pll->on);
e9d6944e 3220 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3221
15bdd4cf 3222 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3223 }
3224 pll->refcount++;
e04c7350 3225
ee7b9f93
JB		 3226 return pll;
3227}
3228
a1520318 3229static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3230{
3231 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3232 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3233 u32 temp;
3234
3235 temp = I915_READ(dslreg);
3236 udelay(500);
3237 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3238 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3239 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3240 }
3241}
3242
b074cec8
JB		 3243static void ironlake_pfit_enable(struct intel_crtc *crtc)
3244{
3245 struct drm_device *dev = crtc->base.dev;
3246 struct drm_i915_private *dev_priv = dev->dev_private;
3247 int pipe = crtc->pipe;
3248
0ef37f3f 3249 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3250 /* Force use of hard-coded filter coefficients
3251 * as some pre-programmed values are broken,
3252 * e.g. x201.
3253 */
3254 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3255 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3256 PF_PIPE_SEL_IVB(pipe));
3257 else
3258 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3259 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3260 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3261 }
3262}
3263
bb53d4ae
VS		 3264static void intel_enable_planes(struct drm_crtc *crtc)
3265{
3266 struct drm_device *dev = crtc->dev;
3267 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3268 struct intel_plane *intel_plane;
3269
3270 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3271 if (intel_plane->pipe == pipe)
3272 intel_plane_restore(&intel_plane->base);
3273}
3274
3275static void intel_disable_planes(struct drm_crtc *crtc)
3276{
3277 struct drm_device *dev = crtc->dev;
3278 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3279 struct intel_plane *intel_plane;
3280
3281 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3282 if (intel_plane->pipe == pipe)
3283 intel_plane_disable(&intel_plane->base);
3284}
3285
f67a559d
JB		 3286static void ironlake_crtc_enable(struct drm_crtc *crtc)
3287{
3288 struct drm_device *dev = crtc->dev;
3289 struct drm_i915_private *dev_priv = dev->dev_private;
3290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3291 struct intel_encoder *encoder;
f67a559d
JB		 3292 int pipe = intel_crtc->pipe;
3293 int plane = intel_crtc->plane;
f67a559d 3294
08a48469
DV		 3295 WARN_ON(!crtc->enabled);
3296
f67a559d
JB		 3297 if (intel_crtc->active)
3298 return;
3299
3300 intel_crtc->active = true;
8664281b
PZ		 3301
3302 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3303 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3304
f6736a1a 3305 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3306 if (encoder->pre_enable)
3307 encoder->pre_enable(encoder);
f67a559d 3308
5bfe2ac0 3309 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3310 /* Note: FDI PLL enabling _must_ be done before we enable the
3311 * cpu pipes, hence this is separate from all the other fdi/pch
3312 * enabling. */
88cefb6c 3313 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3314 } else {
3315 assert_fdi_tx_disabled(dev_priv, pipe);
3316 assert_fdi_rx_disabled(dev_priv, pipe);
3317 }
f67a559d 3318
b074cec8 3319 ironlake_pfit_enable(intel_crtc);
f67a559d 3320
9c54c0dd
JB		 3321 /*
3322 * On ILK+ LUT must be loaded before the pipe is running but with
3323 * clocks enabled
3324 */
3325 intel_crtc_load_lut(crtc);
3326
f37fcc2a 3327 intel_update_watermarks(crtc);
5bfe2ac0 3328 intel_enable_pipe(dev_priv, pipe,
23538ef1 3329 intel_crtc->config.has_pch_encoder, false);
f67a559d 3330 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3331 intel_enable_planes(crtc);
5c38d48c 3332 intel_crtc_update_cursor(crtc, true);
f67a559d 3333
5bfe2ac0 3334 if (intel_crtc->config.has_pch_encoder)
f67a559d 3335 ironlake_pch_enable(crtc);
c98e9dcf 3336
d1ebd816 3337 mutex_lock(&dev->struct_mutex);
bed4a673 3338 intel_update_fbc(dev);
d1ebd816
BW		 3339 mutex_unlock(&dev->struct_mutex);
3340
fa5c73b1
DV		 3341 for_each_encoder_on_crtc(dev, crtc, encoder)
3342 encoder->enable(encoder);
61b77ddd
DV		 3343
3344 if (HAS_PCH_CPT(dev))
a1520318 3345 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3346
3347 /*
3348 * There seems to be a race in PCH platform hw (at least on some
3349 * outputs) where an enabled pipe still completes any pageflip right
3350 * away (as if the pipe is off) instead of waiting for vblank. As soon
3351 * as the first vblank happend, everything works as expected. Hence just
3352 * wait for one vblank before returning to avoid strange things
3353 * happening.
3354 */
3355 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3356}
3357
42db64ef
PZ		 3358/* IPS only exists on ULT machines and is tied to pipe A. */
3359static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3360{
f5adf94e 3361 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3362}
3363
3364static void hsw_enable_ips(struct intel_crtc *crtc)
3365{
3366 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3367
3368 if (!crtc->config.ips_enabled)
3369 return;
3370
3371 /* We can only enable IPS after we enable a plane and wait for a vblank.
3372 * We guarantee that the plane is enabled by calling intel_enable_ips
3373 * only after intel_enable_plane. And intel_enable_plane already waits
3374 * for a vblank, so all we need to do here is to enable the IPS bit. */
3375 assert_plane_enabled(dev_priv, crtc->plane);
3376 I915_WRITE(IPS_CTL, IPS_ENABLE);
3377}
3378
3379static void hsw_disable_ips(struct intel_crtc *crtc)
3380{
3381 struct drm_device *dev = crtc->base.dev;
3382 struct drm_i915_private *dev_priv = dev->dev_private;
3383
3384 if (!crtc->config.ips_enabled)
3385 return;
3386
3387 assert_plane_enabled(dev_priv, crtc->plane);
3388 I915_WRITE(IPS_CTL, 0);
3389
3390 /* We need to wait for a vblank before we can disable the plane. */
3391 intel_wait_for_vblank(dev, crtc->pipe);
3392}
3393
4f771f10
PZ		 3394static void haswell_crtc_enable(struct drm_crtc *crtc)
3395{
3396 struct drm_device *dev = crtc->dev;
3397 struct drm_i915_private *dev_priv = dev->dev_private;
3398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3399 struct intel_encoder *encoder;
3400 int pipe = intel_crtc->pipe;
3401 int plane = intel_crtc->plane;
4f771f10
PZ		 3402
3403 WARN_ON(!crtc->enabled);
3404
3405 if (intel_crtc->active)
3406 return;
3407
3408 intel_crtc->active = true;
8664281b
PZ		 3409
3410 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3411 if (intel_crtc->config.has_pch_encoder)
3412 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3413
5bfe2ac0 3414 if (intel_crtc->config.has_pch_encoder)
04945641 3415 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3416
3417 for_each_encoder_on_crtc(dev, crtc, encoder)
3418 if (encoder->pre_enable)
3419 encoder->pre_enable(encoder);
3420
1f544388 3421 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3422
b074cec8 3423 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3424
3425 /*
3426 * On ILK+ LUT must be loaded before the pipe is running but with
3427 * clocks enabled
3428 */
3429 intel_crtc_load_lut(crtc);
3430
1f544388 3431 intel_ddi_set_pipe_settings(crtc);
8228c251 3432 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3433
f37fcc2a 3434 intel_update_watermarks(crtc);
5bfe2ac0 3435 intel_enable_pipe(dev_priv, pipe,
23538ef1 3436 intel_crtc->config.has_pch_encoder, false);
4f771f10 3437 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3438 intel_enable_planes(crtc);
5c38d48c 3439 intel_crtc_update_cursor(crtc, true);
4f771f10 3440
42db64ef
PZ		 3441 hsw_enable_ips(intel_crtc);
3442
5bfe2ac0 3443 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3444 lpt_pch_enable(crtc);
4f771f10
PZ		 3445
3446 mutex_lock(&dev->struct_mutex);
3447 intel_update_fbc(dev);
3448 mutex_unlock(&dev->struct_mutex);
3449
8807e55b 3450 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3451 encoder->enable(encoder);
8807e55b
JN		 3452 intel_opregion_notify_encoder(encoder, true);
3453 }
4f771f10 3454
4f771f10
PZ		 3455 /*
3456 * There seems to be a race in PCH platform hw (at least on some
3457 * outputs) where an enabled pipe still completes any pageflip right
3458 * away (as if the pipe is off) instead of waiting for vblank. As soon
3459 * as the first vblank happend, everything works as expected. Hence just
3460 * wait for one vblank before returning to avoid strange things
3461 * happening.
3462 */
3463 intel_wait_for_vblank(dev, intel_crtc->pipe);
3464}
3465
3f8dce3a
DV		 3466static void ironlake_pfit_disable(struct intel_crtc *crtc)
3467{
3468 struct drm_device *dev = crtc->base.dev;
3469 struct drm_i915_private *dev_priv = dev->dev_private;
3470 int pipe = crtc->pipe;
3471
3472 /* To avoid upsetting the power well on haswell only disable the pfit if
3473 * it's in use. The hw state code will make sure we get this right. */
3474 if (crtc->config.pch_pfit.size) {
3475 I915_WRITE(PF_CTL(pipe), 0);
3476 I915_WRITE(PF_WIN_POS(pipe), 0);
3477 I915_WRITE(PF_WIN_SZ(pipe), 0);
3478 }
3479}
3480
6be4a607
JB		 3481static void ironlake_crtc_disable(struct drm_crtc *crtc)
3482{
3483 struct drm_device *dev = crtc->dev;
3484 struct drm_i915_private *dev_priv = dev->dev_private;
3485 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3486 struct intel_encoder *encoder;
6be4a607
JB		 3487 int pipe = intel_crtc->pipe;
3488 int plane = intel_crtc->plane;
5eddb70b 3489 u32 reg, temp;
b52eb4dc 3490
ef9c3aee 3491
f7abfe8b
CW		 3492 if (!intel_crtc->active)
3493 return;
3494
ea9d758d
DV		 3495 for_each_encoder_on_crtc(dev, crtc, encoder)
3496 encoder->disable(encoder);
3497
e6c3a2a6 3498 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3499 drm_vblank_off(dev, pipe);
913d8d11 3500
5c3fe8b0 3501 if (dev_priv->fbc.plane == plane)
973d04f9 3502 intel_disable_fbc(dev);
2c07245f 3503
0d5b8c61 3504 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3505 intel_disable_planes(crtc);
0d5b8c61
VS		 3506 intel_disable_plane(dev_priv, plane, pipe);
3507
d925c59a
DV		 3508 if (intel_crtc->config.has_pch_encoder)
3509 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3510
b24e7179 3511 intel_disable_pipe(dev_priv, pipe);
32f9d658 3512
3f8dce3a 3513 ironlake_pfit_disable(intel_crtc);
2c07245f 3514
bf49ec8c
DV		 3515 for_each_encoder_on_crtc(dev, crtc, encoder)
3516 if (encoder->post_disable)
3517 encoder->post_disable(encoder);
2c07245f 3518
d925c59a
DV		 3519 if (intel_crtc->config.has_pch_encoder) {
3520 ironlake_fdi_disable(crtc);
913d8d11 3521
d925c59a
DV		 3522 ironlake_disable_pch_transcoder(dev_priv, pipe);
3523 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3524
d925c59a
DV		 3525 if (HAS_PCH_CPT(dev)) {
3526 /* disable TRANS_DP_CTL */
3527 reg = TRANS_DP_CTL(pipe);
3528 temp = I915_READ(reg);
3529 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3530 TRANS_DP_PORT_SEL_MASK);
3531 temp |= TRANS_DP_PORT_SEL_NONE;
3532 I915_WRITE(reg, temp);
3533
3534 /* disable DPLL_SEL */
3535 temp = I915_READ(PCH_DPLL_SEL);
11887397 3536 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3537 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3538 }
e3421a18 3539
d925c59a 3540 /* disable PCH DPLL */
e72f9fbf 3541 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3542
d925c59a
DV		 3543 ironlake_fdi_pll_disable(intel_crtc);
3544 }
6b383a7f 3545
f7abfe8b 3546 intel_crtc->active = false;
46ba614c 3547 intel_update_watermarks(crtc);
d1ebd816
BW		 3548
3549 mutex_lock(&dev->struct_mutex);
6b383a7f 3550 intel_update_fbc(dev);
d1ebd816 3551 mutex_unlock(&dev->struct_mutex);
6be4a607 3552}
1b3c7a47 3553
4f771f10 3554static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3555{
4f771f10
PZ		 3556 struct drm_device *dev = crtc->dev;
3557 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3558 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3559 struct intel_encoder *encoder;
3560 int pipe = intel_crtc->pipe;
3561 int plane = intel_crtc->plane;
3b117c8f 3562 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3563
4f771f10
PZ		 3564 if (!intel_crtc->active)
3565 return;
3566
8807e55b
JN		 3567 for_each_encoder_on_crtc(dev, crtc, encoder) {
3568 intel_opregion_notify_encoder(encoder, false);
4f771f10 3569 encoder->disable(encoder);
8807e55b 3570 }
4f771f10
PZ		 3571
3572 intel_crtc_wait_for_pending_flips(crtc);
3573 drm_vblank_off(dev, pipe);
4f771f10 3574
891348b2 3575 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3576 if (dev_priv->fbc.plane == plane)
4f771f10
PZ		 3577 intel_disable_fbc(dev);
3578
42db64ef
PZ		 3579 hsw_disable_ips(intel_crtc);
3580
0d5b8c61 3581 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3582 intel_disable_planes(crtc);
891348b2
RV		 3583 intel_disable_plane(dev_priv, plane, pipe);
3584
8664281b
PZ		 3585 if (intel_crtc->config.has_pch_encoder)
3586 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3587 intel_disable_pipe(dev_priv, pipe);
3588
ad80a810 3589 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3590
3f8dce3a 3591 ironlake_pfit_disable(intel_crtc);
4f771f10 3592
1f544388 3593 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3594
3595 for_each_encoder_on_crtc(dev, crtc, encoder)
3596 if (encoder->post_disable)
3597 encoder->post_disable(encoder);
3598
88adfff1 3599 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3600 lpt_disable_pch_transcoder(dev_priv);
8664281b 3601 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3602 intel_ddi_fdi_disable(crtc);
83616634 3603 }
4f771f10
PZ		 3604
3605 intel_crtc->active = false;
46ba614c 3606 intel_update_watermarks(crtc);
4f771f10
PZ		 3607
3608 mutex_lock(&dev->struct_mutex);
3609 intel_update_fbc(dev);
3610 mutex_unlock(&dev->struct_mutex);
3611}
3612
ee7b9f93
JB		 3613static void ironlake_crtc_off(struct drm_crtc *crtc)
3614{
3615 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3616 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3617}
3618
6441ab5f
PZ		 3619static void haswell_crtc_off(struct drm_crtc *crtc)
3620{
3621 intel_ddi_put_crtc_pll(crtc);
3622}
3623
02e792fb
DV		 3624static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3625{
02e792fb 3626 if (!enable && intel_crtc->overlay) {
23f09ce3 3627 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3628 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3629
23f09ce3 3630 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3631 dev_priv->mm.interruptible = false;
3632 (void) intel_overlay_switch_off(intel_crtc->overlay);
3633 dev_priv->mm.interruptible = true;
23f09ce3 3634 mutex_unlock(&dev->struct_mutex);
02e792fb 3635 }
02e792fb 3636
5dcdbcb0
CW		 3637 /* Let userspace switch the overlay on again. In most cases userspace
3638 * has to recompute where to put it anyway.
3639 */
02e792fb
DV		 3640}
3641
61bc95c1
EE		 3642/**
3643 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3644 * cursor plane briefly if not already running after enabling the display
3645 * plane.
3646 * This workaround avoids occasional blank screens when self refresh is
3647 * enabled.
3648 */
3649static void
3650g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3651{
3652 u32 cntl = I915_READ(CURCNTR(pipe));
3653
3654 if ((cntl & CURSOR_MODE) == 0) {
3655 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3656
3657 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3658 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3659 intel_wait_for_vblank(dev_priv->dev, pipe);
3660 I915_WRITE(CURCNTR(pipe), cntl);
3661 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3662 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3663 }
3664}
3665
2dd24552
JB		 3666static void i9xx_pfit_enable(struct intel_crtc *crtc)
3667{
3668 struct drm_device *dev = crtc->base.dev;
3669 struct drm_i915_private *dev_priv = dev->dev_private;
3670 struct intel_crtc_config *pipe_config = &crtc->config;
3671
328d8e82 3672 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3673 return;
3674
2dd24552 3675 /*
c0b03411
DV		 3676 * The panel fitter should only be adjusted whilst the pipe is disabled,
3677 * according to register description and PRM.
2dd24552 3678 */
c0b03411
DV		 3679 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3680 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3681
b074cec8
JB		 3682 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3683 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3684
3685 /* Border color in case we don't scale up to the full screen. Black by
3686 * default, change to something else for debugging. */
3687 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3688}
3689
89b667f8
JB		 3690static void valleyview_crtc_enable(struct drm_crtc *crtc)
3691{
3692 struct drm_device *dev = crtc->dev;
3693 struct drm_i915_private *dev_priv = dev->dev_private;
3694 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3695 struct intel_encoder *encoder;
3696 int pipe = intel_crtc->pipe;
3697 int plane = intel_crtc->plane;
23538ef1 3698 bool is_dsi;
89b667f8
JB		 3699
3700 WARN_ON(!crtc->enabled);
3701
3702 if (intel_crtc->active)
3703 return;
3704
3705 intel_crtc->active = true;
89b667f8 3706
89b667f8
JB		 3707 for_each_encoder_on_crtc(dev, crtc, encoder)
3708 if (encoder->pre_pll_enable)
3709 encoder->pre_pll_enable(encoder);
3710
23538ef1
JN		 3711 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3712
e9fd1c02
JN		 3713 if (!is_dsi)
3714 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3715
3716 for_each_encoder_on_crtc(dev, crtc, encoder)
3717 if (encoder->pre_enable)
3718 encoder->pre_enable(encoder);
3719
2dd24552
JB		 3720 i9xx_pfit_enable(intel_crtc);
3721
63cbb074
VS		 3722 intel_crtc_load_lut(crtc);
3723
f37fcc2a 3724 intel_update_watermarks(crtc);
23538ef1 3725 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
89b667f8 3726 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3727 intel_enable_planes(crtc);
5c38d48c 3728 intel_crtc_update_cursor(crtc, true);
89b667f8 3729
89b667f8 3730 intel_update_fbc(dev);
5004945f
JN		 3731
3732 for_each_encoder_on_crtc(dev, crtc, encoder)
3733 encoder->enable(encoder);
89b667f8
JB		 3734}
3735
0b8765c6 3736static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3737{
3738 struct drm_device *dev = crtc->dev;
79e53945
JB		 3739 struct drm_i915_private *dev_priv = dev->dev_private;
3740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3741 struct intel_encoder *encoder;
79e53945 3742 int pipe = intel_crtc->pipe;
80824003 3743 int plane = intel_crtc->plane;
79e53945 3744
08a48469
DV		 3745 WARN_ON(!crtc->enabled);
3746
f7abfe8b
CW		 3747 if (intel_crtc->active)
3748 return;
3749
3750 intel_crtc->active = true;
6b383a7f 3751
9d6d9f19
MK		 3752 for_each_encoder_on_crtc(dev, crtc, encoder)
3753 if (encoder->pre_enable)
3754 encoder->pre_enable(encoder);
3755
f6736a1a
DV		 3756 i9xx_enable_pll(intel_crtc);
3757
2dd24552
JB		 3758 i9xx_pfit_enable(intel_crtc);
3759
63cbb074
VS		 3760 intel_crtc_load_lut(crtc);
3761
f37fcc2a 3762 intel_update_watermarks(crtc);
23538ef1 3763 intel_enable_pipe(dev_priv, pipe, false, false);
b24e7179 3764 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3765 intel_enable_planes(crtc);
22e407d7 3766 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3767 if (IS_G4X(dev))
3768 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3769 intel_crtc_update_cursor(crtc, true);
79e53945 3770
0b8765c6
JB		 3771 /* Give the overlay scaler a chance to enable if it's on this pipe */
3772 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3773
f440eb13 3774 intel_update_fbc(dev);
ef9c3aee 3775
fa5c73b1
DV		 3776 for_each_encoder_on_crtc(dev, crtc, encoder)
3777 encoder->enable(encoder);
0b8765c6 3778}
79e53945 3779
87476d63
DV		 3780static void i9xx_pfit_disable(struct intel_crtc *crtc)
3781{
3782 struct drm_device *dev = crtc->base.dev;
3783 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3784
328d8e82
DV		 3785 if (!crtc->config.gmch_pfit.control)
3786 return;
87476d63 3787
328d8e82 3788 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3789
328d8e82
DV		 3790 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3791 I915_READ(PFIT_CONTROL));
3792 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3793}
3794
0b8765c6
JB		 3795static void i9xx_crtc_disable(struct drm_crtc *crtc)
3796{
3797 struct drm_device *dev = crtc->dev;
3798 struct drm_i915_private *dev_priv = dev->dev_private;
3799 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3800 struct intel_encoder *encoder;
0b8765c6
JB		 3801 int pipe = intel_crtc->pipe;
3802 int plane = intel_crtc->plane;
ef9c3aee 3803
f7abfe8b
CW		 3804 if (!intel_crtc->active)
3805 return;
3806
ea9d758d
DV		 3807 for_each_encoder_on_crtc(dev, crtc, encoder)
3808 encoder->disable(encoder);
3809
0b8765c6 3810 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3811 intel_crtc_wait_for_pending_flips(crtc);
3812 drm_vblank_off(dev, pipe);
0b8765c6 3813
5c3fe8b0 3814 if (dev_priv->fbc.plane == plane)
973d04f9 3815 intel_disable_fbc(dev);
79e53945 3816
0d5b8c61
VS		 3817 intel_crtc_dpms_overlay(intel_crtc, false);
3818 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3819 intel_disable_planes(crtc);
b24e7179 3820 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3821
b24e7179 3822 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3823
87476d63 3824 i9xx_pfit_disable(intel_crtc);
24a1f16d 3825
89b667f8
JB		 3826 for_each_encoder_on_crtc(dev, crtc, encoder)
3827 if (encoder->post_disable)
3828 encoder->post_disable(encoder);
3829
e9fd1c02
JN		 3830 if (!intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3831 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3832
f7abfe8b 3833 intel_crtc->active = false;
46ba614c 3834 intel_update_watermarks(crtc);
f37fcc2a
VS		 3835
3836 intel_update_fbc(dev);
0b8765c6
JB		 3837}
3838
ee7b9f93
JB		 3839static void i9xx_crtc_off(struct drm_crtc *crtc)
3840{
3841}
3842
976f8a20
DV		 3843static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3844 bool enabled)
2c07245f
ZW		 3845{
3846 struct drm_device *dev = crtc->dev;
3847 struct drm_i915_master_private *master_priv;
3848 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3849 int pipe = intel_crtc->pipe;
79e53945
JB		 3850
3851 if (!dev->primary->master)
3852 return;
3853
3854 master_priv = dev->primary->master->driver_priv;
3855 if (!master_priv->sarea_priv)
3856 return;
3857
79e53945
JB		 3858 switch (pipe) {
3859 case 0:
3860 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3861 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3862 break;
3863 case 1:
3864 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3865 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3866 break;
3867 default:
9db4a9c7 3868 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3869 break;
3870 }
79e53945
JB		 3871}
3872
976f8a20
DV		 3873/**
3874 * Sets the power management mode of the pipe and plane.
3875 */
3876void intel_crtc_update_dpms(struct drm_crtc *crtc)
3877{
3878 struct drm_device *dev = crtc->dev;
3879 struct drm_i915_private *dev_priv = dev->dev_private;
3880 struct intel_encoder *intel_encoder;
3881 bool enable = false;
3882
3883 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3884 enable |= intel_encoder->connectors_active;
3885
3886 if (enable)
3887 dev_priv->display.crtc_enable(crtc);
3888 else
3889 dev_priv->display.crtc_disable(crtc);
3890
3891 intel_crtc_update_sarea(crtc, enable);
3892}
3893
cdd59983
CW		 3894static void intel_crtc_disable(struct drm_crtc *crtc)
3895{
cdd59983 3896 struct drm_device *dev = crtc->dev;
976f8a20 3897 struct drm_connector *connector;
ee7b9f93 3898 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3899 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3900
976f8a20
DV		 3901 /* crtc should still be enabled when we disable it. */
3902 WARN_ON(!crtc->enabled);
3903
3904 dev_priv->display.crtc_disable(crtc);
c77bf565 3905 intel_crtc->eld_vld = false;
976f8a20 3906 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3907 dev_priv->display.off(crtc);
3908
931872fc 3909 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
93ce0ba6 3910 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
931872fc 3911 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3912
3913 if (crtc->fb) {
3914 mutex_lock(&dev->struct_mutex);
1690e1eb 3915 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3916 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3917 crtc->fb = NULL;
3918 }
3919
3920 /* Update computed state. */
3921 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3922 if (!connector->encoder || !connector->encoder->crtc)
3923 continue;
3924
3925 if (connector->encoder->crtc != crtc)
3926 continue;
3927
3928 connector->dpms = DRM_MODE_DPMS_OFF;
3929 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3930 }
3931}
3932
ea5b213a 3933void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3934{
4ef69c7a 3935 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3936
ea5b213a
CW		 3937 drm_encoder_cleanup(encoder);
3938 kfree(intel_encoder);
7e7d76c3
JB		 3939}
3940
9237329d 3941/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 3942 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3943 * state of the entire output pipe. */
9237329d 3944static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3945{
5ab432ef
DV		 3946 if (mode == DRM_MODE_DPMS_ON) {
3947 encoder->connectors_active = true;
3948
b2cabb0e 3949 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3950 } else {
3951 encoder->connectors_active = false;
3952
b2cabb0e 3953 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3954 }
79e53945
JB		 3955}
3956
0a91ca29
DV		 3957/* Cross check the actual hw state with our own modeset state tracking (and it's
3958 * internal consistency). */
b980514c 3959static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3960{
0a91ca29
DV		 3961 if (connector->get_hw_state(connector)) {
3962 struct intel_encoder *encoder = connector->encoder;
3963 struct drm_crtc *crtc;
3964 bool encoder_enabled;
3965 enum pipe pipe;
3966
3967 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3968 connector->base.base.id,
3969 drm_get_connector_name(&connector->base));
3970
3971 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3972 "wrong connector dpms state\n");
3973 WARN(connector->base.encoder != &encoder->base,
3974 "active connector not linked to encoder\n");
3975 WARN(!encoder->connectors_active,
3976 "encoder->connectors_active not set\n");
3977
3978 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3979 WARN(!encoder_enabled, "encoder not enabled\n");
3980 if (WARN_ON(!encoder->base.crtc))
3981 return;
3982
3983 crtc = encoder->base.crtc;
3984
3985 WARN(!crtc->enabled, "crtc not enabled\n");
3986 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3987 WARN(pipe != to_intel_crtc(crtc)->pipe,
3988 "encoder active on the wrong pipe\n");
3989 }
79e53945
JB		 3990}
3991
5ab432ef
DV		 3992/* Even simpler default implementation, if there's really no special case to
3993 * consider. */
3994void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3995{
5ab432ef 3996 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3997
5ab432ef
DV		 3998 /* All the simple cases only support two dpms states. */
3999 if (mode != DRM_MODE_DPMS_ON)
4000 mode = DRM_MODE_DPMS_OFF;
d4270e57 4001
5ab432ef
DV		 4002 if (mode == connector->dpms)
4003 return;
4004
4005 connector->dpms = mode;
4006
4007 /* Only need to change hw state when actually enabled */
4008 if (encoder->base.crtc)
4009 intel_encoder_dpms(encoder, mode);
4010 else
8af6cf88 4011 WARN_ON(encoder->connectors_active != false);
0a91ca29 4012
b980514c 4013 intel_modeset_check_state(connector->dev);
79e53945
JB		 4014}
4015
f0947c37
DV		 4016/* Simple connector->get_hw_state implementation for encoders that support only
4017 * one connector and no cloning and hence the encoder state determines the state
4018 * of the connector. */
4019bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4020{
24929352 4021 enum pipe pipe = 0;
f0947c37 4022 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4023
f0947c37 4024 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4025}
4026
1857e1da
DV		 4027static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4028 struct intel_crtc_config *pipe_config)
4029{
4030 struct drm_i915_private *dev_priv = dev->dev_private;
4031 struct intel_crtc *pipe_B_crtc =
4032 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4033
4034 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4035 pipe_name(pipe), pipe_config->fdi_lanes);
4036 if (pipe_config->fdi_lanes > 4) {
4037 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4038 pipe_name(pipe), pipe_config->fdi_lanes);
4039 return false;
4040 }
4041
4042 if (IS_HASWELL(dev)) {
4043 if (pipe_config->fdi_lanes > 2) {
4044 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4045 pipe_config->fdi_lanes);
4046 return false;
4047 } else {
4048 return true;
4049 }
4050 }
4051
4052 if (INTEL_INFO(dev)->num_pipes == 2)
4053 return true;
4054
4055 /* Ivybridge 3 pipe is really complicated */
4056 switch (pipe) {
4057 case PIPE_A:
4058 return true;
4059 case PIPE_B:
4060 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4061 pipe_config->fdi_lanes > 2) {
4062 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4063 pipe_name(pipe), pipe_config->fdi_lanes);
4064 return false;
4065 }
4066 return true;
4067 case PIPE_C:
1e833f40 4068 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4069 pipe_B_crtc->config.fdi_lanes <= 2) {
4070 if (pipe_config->fdi_lanes > 2) {
4071 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4072 pipe_name(pipe), pipe_config->fdi_lanes);
4073 return false;
4074 }
4075 } else {
4076 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4077 return false;
4078 }
4079 return true;
4080 default:
4081 BUG();
4082 }
4083}
4084
e29c22c0
DV		 4085#define RETRY 1
4086static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4087 struct intel_crtc_config *pipe_config)
877d48d5 4088{
1857e1da 4089 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4090 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4091 int lane, link_bw, fdi_dotclock;
e29c22c0 4092 bool setup_ok, needs_recompute = false;
877d48d5 4093
e29c22c0 4094retry:
877d48d5
DV		 4095 /* FDI is a binary signal running at ~2.7GHz, encoding
4096 * each output octet as 10 bits. The actual frequency
4097 * is stored as a divider into a 100MHz clock, and the
4098 * mode pixel clock is stored in units of 1KHz.
4099 * Hence the bw of each lane in terms of the mode signal
4100 * is:
4101 */
4102 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4103
ff9a6750 4104 fdi_dotclock = adjusted_mode->clock;
877d48d5 4105
2bd89a07 4106 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4107 pipe_config->pipe_bpp);
4108
4109 pipe_config->fdi_lanes = lane;
4110
2bd89a07 4111 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4112 link_bw, &pipe_config->fdi_m_n);
1857e1da 4113
e29c22c0
DV		 4114 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4115 intel_crtc->pipe, pipe_config);
4116 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4117 pipe_config->pipe_bpp -= 2*3;
4118 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4119 pipe_config->pipe_bpp);
4120 needs_recompute = true;
4121 pipe_config->bw_constrained = true;
4122
4123 goto retry;
4124 }
4125
4126 if (needs_recompute)
4127 return RETRY;
4128
4129 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4130}
4131
42db64ef
PZ		 4132static void hsw_compute_ips_config(struct intel_crtc *crtc,
4133 struct intel_crtc_config *pipe_config)
4134{
3c4ca58c
PZ		 4135 pipe_config->ips_enabled = i915_enable_ips &&
4136 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4137 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4138}
4139
a43f6e0f 4140static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4141 struct intel_crtc_config *pipe_config)
79e53945 4142{
a43f6e0f 4143 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4144 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4145
ad3a4479 4146 /* FIXME should check pixel clock limits on all platforms */
cf532bb2
VS		 4147 if (INTEL_INFO(dev)->gen < 4) {
4148 struct drm_i915_private *dev_priv = dev->dev_private;
4149 int clock_limit =
4150 dev_priv->display.get_display_clock_speed(dev);
4151
4152 /*
4153 * Enable pixel doubling when the dot clock
4154 * is > 90% of the (display) core speed.
4155 *
4156 * XXX: No double-wide on 915GM pipe B. Is that
4157 * the only reason for the pipe == PIPE_A check?
4158 */
4159 if (crtc->pipe == PIPE_A &&
ad3a4479
VS		 4160 adjusted_mode->clock > clock_limit * 9 / 10) {
4161 clock_limit *= 2;
cf532bb2 4162 pipe_config->double_wide = true;
ad3a4479
VS		 4163 }
4164
4165 if (adjusted_mode->clock > clock_limit * 9 / 10)
4166 return -EINVAL;
cf532bb2
VS		 4167 }
4168
8693a824
DL		 4169 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4170 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4171 */
4172 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4173 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4174 return -EINVAL;
44f46b42 4175
bd080ee5 4176 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4177 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4178 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4179 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4180 * for lvds. */
4181 pipe_config->pipe_bpp = 8*3;
4182 }
4183
f5adf94e 4184 if (HAS_IPS(dev))
a43f6e0f
DV		 4185 hsw_compute_ips_config(crtc, pipe_config);
4186
4187 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4188 * clock survives for now. */
4189 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4190 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4191
877d48d5 4192 if (pipe_config->has_pch_encoder)
a43f6e0f 4193 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4194
e29c22c0 4195 return 0;
79e53945
JB		 4196}
4197
25eb05fc
JB		 4198static int valleyview_get_display_clock_speed(struct drm_device *dev)
4199{
4200 return 400000; /* FIXME */
4201}
4202
e70236a8
JB		 4203static int i945_get_display_clock_speed(struct drm_device *dev)
4204{
4205 return 400000;
4206}
79e53945 4207
e70236a8 4208static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4209{
e70236a8
JB		 4210 return 333000;
4211}
79e53945 4212
e70236a8
JB		 4213static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4214{
4215 return 200000;
4216}
79e53945 4217
257a7ffc
DV		 4218static int pnv_get_display_clock_speed(struct drm_device *dev)
4219{
4220 u16 gcfgc = 0;
4221
4222 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4223
4224 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4225 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4226 return 267000;
4227 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4228 return 333000;
4229 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4230 return 444000;
4231 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4232 return 200000;
4233 default:
4234 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4235 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4236 return 133000;
4237 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4238 return 167000;
4239 }
4240}
4241
e70236a8
JB		 4242static int i915gm_get_display_clock_speed(struct drm_device *dev)
4243{
4244 u16 gcfgc = 0;
79e53945 4245
e70236a8
JB		 4246 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4247
4248 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4249 return 133000;
4250 else {
4251 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4252 case GC_DISPLAY_CLOCK_333_MHZ:
4253 return 333000;
4254 default:
4255 case GC_DISPLAY_CLOCK_190_200_MHZ:
4256 return 190000;
79e53945 4257 }
e70236a8
JB		 4258 }
4259}
4260
4261static int i865_get_display_clock_speed(struct drm_device *dev)
4262{
4263 return 266000;
4264}
4265
4266static int i855_get_display_clock_speed(struct drm_device *dev)
4267{
4268 u16 hpllcc = 0;
4269 /* Assume that the hardware is in the high speed state. This
4270 * should be the default.
4271 */
4272 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4273 case GC_CLOCK_133_200:
4274 case GC_CLOCK_100_200:
4275 return 200000;
4276 case GC_CLOCK_166_250:
4277 return 250000;
4278 case GC_CLOCK_100_133:
79e53945 4279 return 133000;
e70236a8 4280 }
79e53945 4281
e70236a8
JB		 4282 /* Shouldn't happen */
4283 return 0;
4284}
79e53945 4285
e70236a8
JB		 4286static int i830_get_display_clock_speed(struct drm_device *dev)
4287{
4288 return 133000;
79e53945
JB		 4289}
4290
2c07245f 4291static void
a65851af 4292intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4293{
a65851af
VS		 4294 while (*num > DATA_LINK_M_N_MASK ||
4295 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4296 *num >>= 1;
4297 *den >>= 1;
4298 }
4299}
4300
a65851af
VS		 4301static void compute_m_n(unsigned int m, unsigned int n,
4302 uint32_t *ret_m, uint32_t *ret_n)
4303{
4304 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4305 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4306 intel_reduce_m_n_ratio(ret_m, ret_n);
4307}
4308
e69d0bc1
DV		 4309void
4310intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4311 int pixel_clock, int link_clock,
4312 struct intel_link_m_n *m_n)
2c07245f 4313{
e69d0bc1 4314 m_n->tu = 64;
a65851af
VS		 4315
4316 compute_m_n(bits_per_pixel * pixel_clock,
4317 link_clock * nlanes * 8,
4318 &m_n->gmch_m, &m_n->gmch_n);
4319
4320 compute_m_n(pixel_clock, link_clock,
4321 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4322}
4323
a7615030
CW		 4324static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4325{
72bbe58c
KP		 4326 if (i915_panel_use_ssc >= 0)
4327 return i915_panel_use_ssc != 0;
41aa3448 4328 return dev_priv->vbt.lvds_use_ssc
435793df 4329 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4330}
4331
c65d77d8
JB		 4332static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4333{
4334 struct drm_device *dev = crtc->dev;
4335 struct drm_i915_private *dev_priv = dev->dev_private;
4336 int refclk;
4337
a0c4da24 4338 if (IS_VALLEYVIEW(dev)) {
9a0ea498 4339 refclk = 100000;
a0c4da24 4340 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4341 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4342 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4343 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4344 refclk / 1000);
4345 } else if (!IS_GEN2(dev)) {
4346 refclk = 96000;
4347 } else {
4348 refclk = 48000;
4349 }
4350
4351 return refclk;
4352}
4353
7429e9d4 4354static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4355{
7df00d7a 4356 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4357}
f47709a9 4358
7429e9d4
DV		 4359static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4360{
4361 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4362}
4363
f47709a9 4364static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4365 intel_clock_t *reduced_clock)
4366{
f47709a9 4367 struct drm_device *dev = crtc->base.dev;
a7516a05 4368 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4369 int pipe = crtc->pipe;
a7516a05
JB		 4370 u32 fp, fp2 = 0;
4371
4372 if (IS_PINEVIEW(dev)) {
7429e9d4 4373 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4374 if (reduced_clock)
7429e9d4 4375 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4376 } else {
7429e9d4 4377 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4378 if (reduced_clock)
7429e9d4 4379 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4380 }
4381
4382 I915_WRITE(FP0(pipe), fp);
8bcc2795 4383 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4384
f47709a9
DV		 4385 crtc->lowfreq_avail = false;
4386 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4387 reduced_clock && i915_powersave) {
4388 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4389 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4390 crtc->lowfreq_avail = true;
a7516a05
JB		 4391 } else {
4392 I915_WRITE(FP1(pipe), fp);
8bcc2795 4393 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4394 }
4395}
4396
5e69f97f
CML		 4397static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4398 pipe)
89b667f8
JB		 4399{
4400 u32 reg_val;
4401
4402 /*
4403 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4404 * and set it to a reasonable value instead.
4405 */
5e69f97f 4406 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8
JB		 4407 reg_val &= 0xffffff00;
4408 reg_val |= 0x00000030;
5e69f97f 4409 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4410
5e69f97f 4411 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4412 reg_val &= 0x8cffffff;
4413 reg_val = 0x8c000000;
5e69f97f 4414 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8 4415
5e69f97f 4416 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8 4417 reg_val &= 0xffffff00;
5e69f97f 4418 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4419
5e69f97f 4420 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4421 reg_val &= 0x00ffffff;
4422 reg_val |= 0xb0000000;
5e69f97f 4423 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4424}
4425
b551842d
DV		 4426static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4427 struct intel_link_m_n *m_n)
4428{
4429 struct drm_device *dev = crtc->base.dev;
4430 struct drm_i915_private *dev_priv = dev->dev_private;
4431 int pipe = crtc->pipe;
4432
e3b95f1e
DV		 4433 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4434 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4435 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4436 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4437}
4438
4439static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4440 struct intel_link_m_n *m_n)
4441{
4442 struct drm_device *dev = crtc->base.dev;
4443 struct drm_i915_private *dev_priv = dev->dev_private;
4444 int pipe = crtc->pipe;
4445 enum transcoder transcoder = crtc->config.cpu_transcoder;
4446
4447 if (INTEL_INFO(dev)->gen >= 5) {
4448 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4449 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4450 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4451 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4452 } else {
e3b95f1e
DV		 4453 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4454 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4455 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4456 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4457 }
4458}
4459
03afc4a2
DV		 4460static void intel_dp_set_m_n(struct intel_crtc *crtc)
4461{
4462 if (crtc->config.has_pch_encoder)
4463 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4464 else
4465 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4466}
4467
f47709a9 4468static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4469{
f47709a9 4470 struct drm_device *dev = crtc->base.dev;
a0c4da24 4471 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4472 int pipe = crtc->pipe;
89b667f8 4473 u32 dpll, mdiv;
a0c4da24 4474 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4475 u32 coreclk, reg_val, dpll_md;
a0c4da24 4476
09153000
DV		 4477 mutex_lock(&dev_priv->dpio_lock);
4478
f47709a9
DV		 4479 bestn = crtc->config.dpll.n;
4480 bestm1 = crtc->config.dpll.m1;
4481 bestm2 = crtc->config.dpll.m2;
4482 bestp1 = crtc->config.dpll.p1;
4483 bestp2 = crtc->config.dpll.p2;
a0c4da24 4484
89b667f8
JB		 4485 /* See eDP HDMI DPIO driver vbios notes doc */
4486
4487 /* PLL B needs special handling */
4488 if (pipe)
5e69f97f 4489 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 4490
4491 /* Set up Tx target for periodic Rcomp update */
5e69f97f 4492 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4493
4494 /* Disable target IRef on PLL */
5e69f97f 4495 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
89b667f8 4496 reg_val &= 0x00ffffff;
5e69f97f 4497 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4498
4499 /* Disable fast lock */
5e69f97f 4500 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4501
4502 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4503 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4504 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4505 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4506 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4507
4508 /*
4509 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4510 * but we don't support that).
4511 * Note: don't use the DAC post divider as it seems unstable.
4512 */
4513 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5e69f97f 4514 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4515
a0c4da24 4516 mdiv |= DPIO_ENABLE_CALIBRATION;
5e69f97f 4517 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4518
89b667f8 4519 /* Set HBR and RBR LPF coefficients */
ff9a6750 4520 if (crtc->config.port_clock == 162000 ||
99750bd4 4521 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4522 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5e69f97f 4523 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
885b0120 4524 0x009f0003);
89b667f8 4525 else
5e69f97f 4526 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4527 0x00d0000f);
4528
4529 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4530 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4531 /* Use SSC source */
4532 if (!pipe)
5e69f97f 4533 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4534 0x0df40000);
4535 else
5e69f97f 4536 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4537 0x0df70000);
4538 } else { /* HDMI or VGA */
4539 /* Use bend source */
4540 if (!pipe)
5e69f97f 4541 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4542 0x0df70000);
4543 else
5e69f97f 4544 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4545 0x0df40000);
4546 }
a0c4da24 4547
5e69f97f 4548 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4549 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4550 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4551 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4552 coreclk |= 0x01000000;
5e69f97f 4553 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4554
5e69f97f 4555 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4556
89b667f8
JB		 4557 /* Enable DPIO clock input */
4558 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4559 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4560 if (pipe)
4561 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4562
4563 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4564 crtc->config.dpll_hw_state.dpll = dpll;
4565
ef1b460d
DV		 4566 dpll_md = (crtc->config.pixel_multiplier - 1)
4567 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4568 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4569
89b667f8
JB		 4570 if (crtc->config.has_dp_encoder)
4571 intel_dp_set_m_n(crtc);
09153000
DV		 4572
4573 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4574}
4575
f47709a9
DV		 4576static void i9xx_update_pll(struct intel_crtc *crtc,
4577 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4578 int num_connectors)
4579{
f47709a9 4580 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4581 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4582 u32 dpll;
4583 bool is_sdvo;
f47709a9 4584 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4585
f47709a9 4586 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4587
f47709a9
DV		 4588 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4589 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4590
4591 dpll = DPLL_VGA_MODE_DIS;
4592
f47709a9 4593 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4594 dpll |= DPLLB_MODE_LVDS;
4595 else
4596 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4597
ef1b460d 4598 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4599 dpll |= (crtc->config.pixel_multiplier - 1)
4600 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4601 }
198a037f
DV		 4602
4603 if (is_sdvo)
4a33e48d 4604 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4605
f47709a9 4606 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4607 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4608
4609 /* compute bitmask from p1 value */
4610 if (IS_PINEVIEW(dev))
4611 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4612 else {
4613 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4614 if (IS_G4X(dev) && reduced_clock)
4615 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4616 }
4617 switch (clock->p2) {
4618 case 5:
4619 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4620 break;
4621 case 7:
4622 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4623 break;
4624 case 10:
4625 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4626 break;
4627 case 14:
4628 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4629 break;
4630 }
4631 if (INTEL_INFO(dev)->gen >= 4)
4632 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4633
09ede541 4634 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4635 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4636 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4637 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4638 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4639 else
4640 dpll |= PLL_REF_INPUT_DREFCLK;
4641
4642 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4643 crtc->config.dpll_hw_state.dpll = dpll;
4644
eb1cbe48 4645 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4646 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4647 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4648 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4649 }
66e3d5c0
DV		 4650
4651 if (crtc->config.has_dp_encoder)
4652 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4653}
4654
f47709a9 4655static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4656 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4657 int num_connectors)
4658{
f47709a9 4659 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4660 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4661 u32 dpll;
f47709a9 4662 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4663
f47709a9 4664 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4665
eb1cbe48
DV		 4666 dpll = DPLL_VGA_MODE_DIS;
4667
f47709a9 4668 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4669 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4670 } else {
4671 if (clock->p1 == 2)
4672 dpll |= PLL_P1_DIVIDE_BY_TWO;
4673 else
4674 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4675 if (clock->p2 == 4)
4676 dpll |= PLL_P2_DIVIDE_BY_4;
4677 }
4678
4a33e48d
DV		 4679 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4680 dpll |= DPLL_DVO_2X_MODE;
4681
f47709a9 4682 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4683 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4684 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4685 else
4686 dpll |= PLL_REF_INPUT_DREFCLK;
4687
4688 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4689 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4690}
4691
8a654f3b 4692static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4693{
4694 struct drm_device *dev = intel_crtc->base.dev;
4695 struct drm_i915_private *dev_priv = dev->dev_private;
4696 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4697 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4698 struct drm_display_mode *adjusted_mode =
4699 &intel_crtc->config.adjusted_mode;
4d8a62ea
DV		 4700 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4701
4702 /* We need to be careful not to changed the adjusted mode, for otherwise
4703 * the hw state checker will get angry at the mismatch. */
4704 crtc_vtotal = adjusted_mode->crtc_vtotal;
4705 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4706
4707 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4708 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4709 crtc_vtotal -= 1;
4710 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4711 vsyncshift = adjusted_mode->crtc_hsync_start
4712 - adjusted_mode->crtc_htotal / 2;
4713 } else {
4714 vsyncshift = 0;
4715 }
4716
4717 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4718 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4719
fe2b8f9d 4720 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4721 (adjusted_mode->crtc_hdisplay - 1) |
4722 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4723 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4724 (adjusted_mode->crtc_hblank_start - 1) |
4725 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4726 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4727 (adjusted_mode->crtc_hsync_start - 1) |
4728 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4729
fe2b8f9d 4730 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4731 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4732 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4733 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4734 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4735 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4736 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4737 (adjusted_mode->crtc_vsync_start - 1) |
4738 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4739
b5e508d4
PZ		 4740 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4741 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4742 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4743 * bits. */
4744 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4745 (pipe == PIPE_B || pipe == PIPE_C))
4746 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4747
b0e77b9c
PZ		 4748 /* pipesrc controls the size that is scaled from, which should
4749 * always be the user's requested size.
4750 */
4751 I915_WRITE(PIPESRC(pipe),
37327abd
VS		 4752 ((intel_crtc->config.pipe_src_w - 1) << 16) |
4753 (intel_crtc->config.pipe_src_h - 1));
b0e77b9c
PZ		 4754}
4755
1bd1bd80
DV		 4756static void intel_get_pipe_timings(struct intel_crtc *crtc,
4757 struct intel_crtc_config *pipe_config)
4758{
4759 struct drm_device *dev = crtc->base.dev;
4760 struct drm_i915_private *dev_priv = dev->dev_private;
4761 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4762 uint32_t tmp;
4763
4764 tmp = I915_READ(HTOTAL(cpu_transcoder));
4765 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4766 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4767 tmp = I915_READ(HBLANK(cpu_transcoder));
4768 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4769 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4770 tmp = I915_READ(HSYNC(cpu_transcoder));
4771 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4772 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4773
4774 tmp = I915_READ(VTOTAL(cpu_transcoder));
4775 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4776 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4777 tmp = I915_READ(VBLANK(cpu_transcoder));
4778 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4779 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4780 tmp = I915_READ(VSYNC(cpu_transcoder));
4781 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4782 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4783
4784 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4785 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4786 pipe_config->adjusted_mode.crtc_vtotal += 1;
4787 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4788 }
4789
4790 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 4791 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4792 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4793
4794 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4795 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 4796}
4797
babea61d
JB		 4798static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4799 struct intel_crtc_config *pipe_config)
4800{
4801 struct drm_crtc *crtc = &intel_crtc->base;
4802
4803 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4804 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4805 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4806 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4807
4808 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4809 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4810 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4811 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4812
4813 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4814
4815 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4816 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4817}
4818
84b046f3
DV		 4819static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4820{
4821 struct drm_device *dev = intel_crtc->base.dev;
4822 struct drm_i915_private *dev_priv = dev->dev_private;
4823 uint32_t pipeconf;
4824
9f11a9e4 4825 pipeconf = 0;
84b046f3 4826
cf532bb2
VS		 4827 if (intel_crtc->config.double_wide)
4828 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 4829
ff9ce46e
DV		 4830 /* only g4x and later have fancy bpc/dither controls */
4831 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4832 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4833 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4834 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4835 PIPECONF_DITHER_TYPE_SP;
84b046f3 4836
ff9ce46e
DV		 4837 switch (intel_crtc->config.pipe_bpp) {
4838 case 18:
4839 pipeconf |= PIPECONF_6BPC;
4840 break;
4841 case 24:
4842 pipeconf |= PIPECONF_8BPC;
4843 break;
4844 case 30:
4845 pipeconf |= PIPECONF_10BPC;
4846 break;
4847 default:
4848 /* Case prevented by intel_choose_pipe_bpp_dither. */
4849 BUG();
84b046f3
DV		 4850 }
4851 }
4852
4853 if (HAS_PIPE_CXSR(dev)) {
4854 if (intel_crtc->lowfreq_avail) {
4855 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4856 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4857 } else {
4858 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4859 }
4860 }
4861
84b046f3
DV		 4862 if (!IS_GEN2(dev) &&
4863 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4864 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4865 else
4866 pipeconf |= PIPECONF_PROGRESSIVE;
4867
9f11a9e4
DV		 4868 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4869 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4870
84b046f3
DV		 4871 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4872 POSTING_READ(PIPECONF(intel_crtc->pipe));
4873}
4874
f564048e 4875static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4876 int x, int y,
94352cf9 4877 struct drm_framebuffer *fb)
79e53945
JB		 4878{
4879 struct drm_device *dev = crtc->dev;
4880 struct drm_i915_private *dev_priv = dev->dev_private;
4881 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4882 int pipe = intel_crtc->pipe;
80824003 4883 int plane = intel_crtc->plane;
c751ce4f 4884 int refclk, num_connectors = 0;
652c393a 4885 intel_clock_t clock, reduced_clock;
84b046f3 4886 u32 dspcntr;
a16af721 4887 bool ok, has_reduced_clock = false;
e9fd1c02 4888 bool is_lvds = false, is_dsi = false;
5eddb70b 4889 struct intel_encoder *encoder;
d4906093 4890 const intel_limit_t *limit;
5c3b82e2 4891 int ret;
79e53945 4892
6c2b7c12 4893 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4894 switch (encoder->type) {
79e53945
JB		 4895 case INTEL_OUTPUT_LVDS:
4896 is_lvds = true;
4897 break;
e9fd1c02
JN		 4898 case INTEL_OUTPUT_DSI:
4899 is_dsi = true;
4900 break;
79e53945 4901 }
43565a06 4902
c751ce4f 4903 num_connectors++;
79e53945
JB		 4904 }
4905
c65d77d8 4906 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4907
65ce4bf5 4908 if (!is_dsi && !intel_crtc->config.clock_set) {
e9fd1c02
JN		 4909 /*
4910 * Returns a set of divisors for the desired target clock with
4911 * the given refclk, or FALSE. The returned values represent
4912 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
4913 * 2) / p1 / p2.
4914 */
4915 limit = intel_limit(crtc, refclk);
4916 ok = dev_priv->display.find_dpll(limit, crtc,
4917 intel_crtc->config.port_clock,
4918 refclk, NULL, &clock);
4919 if (!ok && !intel_crtc->config.clock_set) {
4920 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4921 return -EINVAL;
4922 }
79e53945
JB		 4923 }
4924
cda4b7d3 4925 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4926 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4927
e9fd1c02 4928 if (!is_dsi && is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4929 /*
4930 * Ensure we match the reduced clock's P to the target clock.
4931 * If the clocks don't match, we can't switch the display clock
4932 * by using the FP0/FP1. In such case we will disable the LVDS
4933 * downclock feature.
4934 */
65ce4bf5 4935 limit = intel_limit(crtc, refclk);
ee9300bb
DV		 4936 has_reduced_clock =
4937 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4938 dev_priv->lvds_downclock,
ee9300bb 4939 refclk, &clock,
5eddb70b 4940 &reduced_clock);
7026d4ac 4941 }
f47709a9
DV		 4942 /* Compat-code for transition, will disappear. */
4943 if (!intel_crtc->config.clock_set) {
4944 intel_crtc->config.dpll.n = clock.n;
4945 intel_crtc->config.dpll.m1 = clock.m1;
4946 intel_crtc->config.dpll.m2 = clock.m2;
4947 intel_crtc->config.dpll.p1 = clock.p1;
4948 intel_crtc->config.dpll.p2 = clock.p2;
4949 }
7026d4ac 4950
e9fd1c02 4951 if (IS_GEN2(dev)) {
8a654f3b 4952 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4953 has_reduced_clock ? &reduced_clock : NULL,
4954 num_connectors);
e9fd1c02
JN		 4955 } else if (IS_VALLEYVIEW(dev)) {
4956 if (!is_dsi)
4957 vlv_update_pll(intel_crtc);
4958 } else {
f47709a9 4959 i9xx_update_pll(intel_crtc,
eb1cbe48 4960 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4961 num_connectors);
e9fd1c02 4962 }
79e53945 4963
79e53945
JB		 4964 /* Set up the display plane register */
4965 dspcntr = DISPPLANE_GAMMA_ENABLE;
4966
da6ecc5d
JB		 4967 if (!IS_VALLEYVIEW(dev)) {
4968 if (pipe == 0)
4969 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4970 else
4971 dspcntr |= DISPPLANE_SEL_PIPE_B;
4972 }
79e53945 4973
8a654f3b 4974 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4975
4976 /* pipesrc and dspsize control the size that is scaled from,
4977 * which should always be the user's requested size.
79e53945 4978 */
929c77fb 4979 I915_WRITE(DSPSIZE(plane),
37327abd
VS		 4980 ((intel_crtc->config.pipe_src_h - 1) << 16) |
4981 (intel_crtc->config.pipe_src_w - 1));
929c77fb 4982 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4983
84b046f3
DV		 4984 i9xx_set_pipeconf(intel_crtc);
4985
f564048e
EA		 4986 I915_WRITE(DSPCNTR(plane), dspcntr);
4987 POSTING_READ(DSPCNTR(plane));
4988
94352cf9 4989 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e 4990
f564048e
EA		 4991 return ret;
4992}
4993
2fa2fe9a
DV		 4994static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4995 struct intel_crtc_config *pipe_config)
4996{
4997 struct drm_device *dev = crtc->base.dev;
4998 struct drm_i915_private *dev_priv = dev->dev_private;
4999 uint32_t tmp;
5000
5001 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 5002 if (!(tmp & PFIT_ENABLE))
5003 return;
2fa2fe9a 5004
06922821 5005 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 5006 if (INTEL_INFO(dev)->gen < 4) {
5007 if (crtc->pipe != PIPE_B)
5008 return;
2fa2fe9a
DV		 5009 } else {
5010 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5011 return;
5012 }
5013
06922821 5014 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 5015 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5016 if (INTEL_INFO(dev)->gen < 5)
5017 pipe_config->gmch_pfit.lvds_border_bits =
5018 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5019}
5020
0e8ffe1b
DV		 5021static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5022 struct intel_crtc_config *pipe_config)
5023{
5024 struct drm_device *dev = crtc->base.dev;
5025 struct drm_i915_private *dev_priv = dev->dev_private;
5026 uint32_t tmp;
5027
e143a21c 5028 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5029 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5030
0e8ffe1b
DV		 5031 tmp = I915_READ(PIPECONF(crtc->pipe));
5032 if (!(tmp & PIPECONF_ENABLE))
5033 return false;
5034
42571aef
VS		 5035 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5036 switch (tmp & PIPECONF_BPC_MASK) {
5037 case PIPECONF_6BPC:
5038 pipe_config->pipe_bpp = 18;
5039 break;
5040 case PIPECONF_8BPC:
5041 pipe_config->pipe_bpp = 24;
5042 break;
5043 case PIPECONF_10BPC:
5044 pipe_config->pipe_bpp = 30;
5045 break;
5046 default:
5047 break;
5048 }
5049 }
5050
282740f7
VS		 5051 if (INTEL_INFO(dev)->gen < 4)
5052 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5053
1bd1bd80
DV		 5054 intel_get_pipe_timings(crtc, pipe_config);
5055
2fa2fe9a
DV		 5056 i9xx_get_pfit_config(crtc, pipe_config);
5057
6c49f241
DV		 5058 if (INTEL_INFO(dev)->gen >= 4) {
5059 tmp = I915_READ(DPLL_MD(crtc->pipe));
5060 pipe_config->pixel_multiplier =
5061 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5062 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5063 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5064 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5065 tmp = I915_READ(DPLL(crtc->pipe));
5066 pipe_config->pixel_multiplier =
5067 ((tmp & SDVO_MULTIPLIER_MASK)
5068 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5069 } else {
5070 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5071 * port and will be fixed up in the encoder->get_config
5072 * function. */
5073 pipe_config->pixel_multiplier = 1;
5074 }
8bcc2795
DV		 5075 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5076 if (!IS_VALLEYVIEW(dev)) {
5077 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5078 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5079 } else {
5080 /* Mask out read-only status bits. */
5081 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5082 DPLL_PORTC_READY_MASK |
5083 DPLL_PORTB_READY_MASK);
8bcc2795 5084 }
6c49f241 5085
18442d08
VS		 5086 i9xx_crtc_clock_get(crtc, pipe_config);
5087
0e8ffe1b
DV		 5088 return true;
5089}
5090
dde86e2d 5091static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5092{
5093 struct drm_i915_private *dev_priv = dev->dev_private;
5094 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5095 struct intel_encoder *encoder;
74cfd7ac 5096 u32 val, final;
13d83a67 5097 bool has_lvds = false;
199e5d79 5098 bool has_cpu_edp = false;
199e5d79 5099 bool has_panel = false;
99eb6a01
KP		 5100 bool has_ck505 = false;
5101 bool can_ssc = false;
13d83a67
JB		 5102
5103 /* We need to take the global config into account */
199e5d79
KP		 5104 list_for_each_entry(encoder, &mode_config->encoder_list,
5105 base.head) {
5106 switch (encoder->type) {
5107 case INTEL_OUTPUT_LVDS:
5108 has_panel = true;
5109 has_lvds = true;
5110 break;
5111 case INTEL_OUTPUT_EDP:
5112 has_panel = true;
2de6905f 5113 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5114 has_cpu_edp = true;
5115 break;
13d83a67
JB		 5116 }
5117 }
5118
99eb6a01 5119 if (HAS_PCH_IBX(dev)) {
41aa3448 5120 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5121 can_ssc = has_ck505;
5122 } else {
5123 has_ck505 = false;
5124 can_ssc = true;
5125 }
5126
2de6905f
ID		 5127 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5128 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5129
5130 /* Ironlake: try to setup display ref clock before DPLL
5131 * enabling. This is only under driver's control after
5132 * PCH B stepping, previous chipset stepping should be
5133 * ignoring this setting.
5134 */
74cfd7ac
CW		 5135 val = I915_READ(PCH_DREF_CONTROL);
5136
5137 /* As we must carefully and slowly disable/enable each source in turn,
5138 * compute the final state we want first and check if we need to
5139 * make any changes at all.
5140 */
5141 final = val;
5142 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5143 if (has_ck505)
5144 final |= DREF_NONSPREAD_CK505_ENABLE;
5145 else
5146 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5147
5148 final &= ~DREF_SSC_SOURCE_MASK;
5149 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5150 final &= ~DREF_SSC1_ENABLE;
5151
5152 if (has_panel) {
5153 final |= DREF_SSC_SOURCE_ENABLE;
5154
5155 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5156 final |= DREF_SSC1_ENABLE;
5157
5158 if (has_cpu_edp) {
5159 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5160 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5161 else
5162 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5163 } else
5164 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5165 } else {
5166 final |= DREF_SSC_SOURCE_DISABLE;
5167 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5168 }
5169
5170 if (final == val)
5171 return;
5172
13d83a67 5173 /* Always enable nonspread source */
74cfd7ac 5174 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5175
99eb6a01 5176 if (has_ck505)
74cfd7ac 5177 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5178 else
74cfd7ac 5179 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5180
199e5d79 5181 if (has_panel) {
74cfd7ac
CW		 5182 val &= ~DREF_SSC_SOURCE_MASK;
5183 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5184
199e5d79 5185 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5186 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5187 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5188 val |= DREF_SSC1_ENABLE;
e77166b5 5189 } else
74cfd7ac 5190 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5191
5192 /* Get SSC going before enabling the outputs */
74cfd7ac 5193 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5194 POSTING_READ(PCH_DREF_CONTROL);
5195 udelay(200);
5196
74cfd7ac 5197 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5198
5199 /* Enable CPU source on CPU attached eDP */
199e5d79 5200 if (has_cpu_edp) {
99eb6a01 5201 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5202 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5203 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5204 }
13d83a67 5205 else
74cfd7ac 5206 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5207 } else
74cfd7ac 5208 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5209
74cfd7ac 5210 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5211 POSTING_READ(PCH_DREF_CONTROL);
5212 udelay(200);
5213 } else {
5214 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5215
74cfd7ac 5216 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5217
5218 /* Turn off CPU output */
74cfd7ac 5219 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5220
74cfd7ac 5221 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5222 POSTING_READ(PCH_DREF_CONTROL);
5223 udelay(200);
5224
5225 /* Turn off the SSC source */
74cfd7ac
CW		 5226 val &= ~DREF_SSC_SOURCE_MASK;
5227 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5228
5229 /* Turn off SSC1 */
74cfd7ac 5230 val &= ~DREF_SSC1_ENABLE;
199e5d79 5231
74cfd7ac 5232 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5233 POSTING_READ(PCH_DREF_CONTROL);
5234 udelay(200);
5235 }
74cfd7ac
CW		 5236
5237 BUG_ON(val != final);
13d83a67
JB		 5238}
5239
f31f2d55 5240static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5241{
f31f2d55 5242 uint32_t tmp;
dde86e2d 5243
0ff066a9
PZ		 5244 tmp = I915_READ(SOUTH_CHICKEN2);
5245 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5246 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5247
0ff066a9
PZ		 5248 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5249 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5250 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5251
0ff066a9
PZ		 5252 tmp = I915_READ(SOUTH_CHICKEN2);
5253 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5254 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5255
0ff066a9
PZ		 5256 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5257 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5258 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5259}
5260
5261/* WaMPhyProgramming:hsw */
5262static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5263{
5264 uint32_t tmp;
dde86e2d
PZ		 5265
5266 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5267 tmp &= ~(0xFF << 24);
5268 tmp |= (0x12 << 24);
5269 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5270
dde86e2d
PZ		 5271 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5272 tmp |= (1 << 11);
5273 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5274
5275 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5276 tmp |= (1 << 11);
5277 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5278
dde86e2d
PZ		 5279 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5280 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5281 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5282
5283 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5284 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5285 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5286
0ff066a9
PZ		 5287 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5288 tmp &= ~(7 << 13);
5289 tmp |= (5 << 13);
5290 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5291
0ff066a9
PZ		 5292 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5293 tmp &= ~(7 << 13);
5294 tmp |= (5 << 13);
5295 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5296
5297 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5298 tmp &= ~0xFF;
5299 tmp |= 0x1C;
5300 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5301
5302 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5303 tmp &= ~0xFF;
5304 tmp |= 0x1C;
5305 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5306
5307 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5308 tmp &= ~(0xFF << 16);
5309 tmp |= (0x1C << 16);
5310 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5311
5312 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5313 tmp &= ~(0xFF << 16);
5314 tmp |= (0x1C << 16);
5315 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5316
0ff066a9
PZ		 5317 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5318 tmp |= (1 << 27);
5319 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5320
0ff066a9
PZ		 5321 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5322 tmp |= (1 << 27);
5323 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5324
0ff066a9
PZ		 5325 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5326 tmp &= ~(0xF << 28);
5327 tmp |= (4 << 28);
5328 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5329
0ff066a9
PZ		 5330 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5331 tmp &= ~(0xF << 28);
5332 tmp |= (4 << 28);
5333 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5334}
5335
2fa86a1f
PZ		 5336/* Implements 3 different sequences from BSpec chapter "Display iCLK
5337 * Programming" based on the parameters passed:
5338 * - Sequence to enable CLKOUT_DP
5339 * - Sequence to enable CLKOUT_DP without spread
5340 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5341 */
5342static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5343 bool with_fdi)
f31f2d55
PZ		 5344{
5345 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5346 uint32_t reg, tmp;
5347
5348 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5349 with_spread = true;
5350 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5351 with_fdi, "LP PCH doesn't have FDI\n"))
5352 with_fdi = false;
f31f2d55
PZ		 5353
5354 mutex_lock(&dev_priv->dpio_lock);
5355
5356 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5357 tmp &= ~SBI_SSCCTL_DISABLE;
5358 tmp |= SBI_SSCCTL_PATHALT;
5359 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5360
5361 udelay(24);
5362
2fa86a1f
PZ		 5363 if (with_spread) {
5364 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5365 tmp &= ~SBI_SSCCTL_PATHALT;
5366 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5367
2fa86a1f
PZ		 5368 if (with_fdi) {
5369 lpt_reset_fdi_mphy(dev_priv);
5370 lpt_program_fdi_mphy(dev_priv);
5371 }
5372 }
dde86e2d 5373
2fa86a1f
PZ		 5374 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5375 SBI_GEN0 : SBI_DBUFF0;
5376 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5377 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5378 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5379
5380 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5381}
5382
47701c3b
PZ		 5383/* Sequence to disable CLKOUT_DP */
5384static void lpt_disable_clkout_dp(struct drm_device *dev)
5385{
5386 struct drm_i915_private *dev_priv = dev->dev_private;
5387 uint32_t reg, tmp;
5388
5389 mutex_lock(&dev_priv->dpio_lock);
5390
5391 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5392 SBI_GEN0 : SBI_DBUFF0;
5393 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5394 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5395 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5396
5397 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5398 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5399 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5400 tmp |= SBI_SSCCTL_PATHALT;
5401 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5402 udelay(32);
5403 }
5404 tmp |= SBI_SSCCTL_DISABLE;
5405 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5406 }
5407
5408 mutex_unlock(&dev_priv->dpio_lock);
5409}
5410
bf8fa3d3
PZ		 5411static void lpt_init_pch_refclk(struct drm_device *dev)
5412{
5413 struct drm_mode_config *mode_config = &dev->mode_config;
5414 struct intel_encoder *encoder;
5415 bool has_vga = false;
5416
5417 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5418 switch (encoder->type) {
5419 case INTEL_OUTPUT_ANALOG:
5420 has_vga = true;
5421 break;
5422 }
5423 }
5424
47701c3b
PZ		 5425 if (has_vga)
5426 lpt_enable_clkout_dp(dev, true, true);
5427 else
5428 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5429}
5430
dde86e2d
PZ		 5431/*
5432 * Initialize reference clocks when the driver loads
5433 */
5434void intel_init_pch_refclk(struct drm_device *dev)
5435{
5436 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5437 ironlake_init_pch_refclk(dev);
5438 else if (HAS_PCH_LPT(dev))
5439 lpt_init_pch_refclk(dev);
5440}
5441
d9d444cb
JB		 5442static int ironlake_get_refclk(struct drm_crtc *crtc)
5443{
5444 struct drm_device *dev = crtc->dev;
5445 struct drm_i915_private *dev_priv = dev->dev_private;
5446 struct intel_encoder *encoder;
d9d444cb
JB		 5447 int num_connectors = 0;
5448 bool is_lvds = false;
5449
6c2b7c12 5450 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5451 switch (encoder->type) {
5452 case INTEL_OUTPUT_LVDS:
5453 is_lvds = true;
5454 break;
d9d444cb
JB		 5455 }
5456 num_connectors++;
5457 }
5458
5459 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5460 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5461 dev_priv->vbt.lvds_ssc_freq);
5462 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5463 }
5464
5465 return 120000;
5466}
5467
6ff93609 5468static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5469{
c8203565 5470 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5472 int pipe = intel_crtc->pipe;
c8203565
PZ		 5473 uint32_t val;
5474
78114071 5475 val = 0;
c8203565 5476
965e0c48 5477 switch (intel_crtc->config.pipe_bpp) {
c8203565 5478 case 18:
dfd07d72 5479 val |= PIPECONF_6BPC;
c8203565
PZ		 5480 break;
5481 case 24:
dfd07d72 5482 val |= PIPECONF_8BPC;
c8203565
PZ		 5483 break;
5484 case 30:
dfd07d72 5485 val |= PIPECONF_10BPC;
c8203565
PZ		 5486 break;
5487 case 36:
dfd07d72 5488 val |= PIPECONF_12BPC;
c8203565
PZ		 5489 break;
5490 default:
cc769b62
PZ		 5491 /* Case prevented by intel_choose_pipe_bpp_dither. */
5492 BUG();
c8203565
PZ		 5493 }
5494
d8b32247 5495 if (intel_crtc->config.dither)
c8203565
PZ		 5496 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5497
6ff93609 5498 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5499 val |= PIPECONF_INTERLACED_ILK;
5500 else
5501 val |= PIPECONF_PROGRESSIVE;
5502
50f3b016 5503 if (intel_crtc->config.limited_color_range)
3685a8f3 5504 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5505
c8203565
PZ		 5506 I915_WRITE(PIPECONF(pipe), val);
5507 POSTING_READ(PIPECONF(pipe));
5508}
5509
86d3efce
VS		 5510/*
5511 * Set up the pipe CSC unit.
5512 *
5513 * Currently only full range RGB to limited range RGB conversion
5514 * is supported, but eventually this should handle various
5515 * RGB<->YCbCr scenarios as well.
5516 */
50f3b016 5517static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5518{
5519 struct drm_device *dev = crtc->dev;
5520 struct drm_i915_private *dev_priv = dev->dev_private;
5521 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5522 int pipe = intel_crtc->pipe;
5523 uint16_t coeff = 0x7800; /* 1.0 */
5524
5525 /*
5526 * TODO: Check what kind of values actually come out of the pipe
5527 * with these coeff/postoff values and adjust to get the best
5528 * accuracy. Perhaps we even need to take the bpc value into
5529 * consideration.
5530 */
5531
50f3b016 5532 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5533 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5534
5535 /*
5536 * GY/GU and RY/RU should be the other way around according
5537 * to BSpec, but reality doesn't agree. Just set them up in
5538 * a way that results in the correct picture.
5539 */
5540 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5541 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5542
5543 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5544 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5545
5546 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5547 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5548
5549 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5550 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5551 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5552
5553 if (INTEL_INFO(dev)->gen > 6) {
5554 uint16_t postoff = 0;
5555
50f3b016 5556 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5557 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5558
5559 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5560 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5561 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5562
5563 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5564 } else {
5565 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5566
50f3b016 5567 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5568 mode |= CSC_BLACK_SCREEN_OFFSET;
5569
5570 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5571 }
5572}
5573
6ff93609 5574static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5575{
5576 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5577 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5578 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5579 uint32_t val;
5580
3eff4faa 5581 val = 0;
ee2b0b38 5582
d8b32247 5583 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5584 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5585
6ff93609 5586 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5587 val |= PIPECONF_INTERLACED_ILK;
5588 else
5589 val |= PIPECONF_PROGRESSIVE;
5590
702e7a56
PZ		 5591 I915_WRITE(PIPECONF(cpu_transcoder), val);
5592 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5593
5594 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5595 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5596}
5597
6591c6e4 5598static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5599 intel_clock_t *clock,
5600 bool *has_reduced_clock,
5601 intel_clock_t *reduced_clock)
5602{
5603 struct drm_device *dev = crtc->dev;
5604 struct drm_i915_private *dev_priv = dev->dev_private;
5605 struct intel_encoder *intel_encoder;
5606 int refclk;
d4906093 5607 const intel_limit_t *limit;
a16af721 5608 bool ret, is_lvds = false;
79e53945 5609
6591c6e4
PZ		 5610 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5611 switch (intel_encoder->type) {
79e53945
JB		 5612 case INTEL_OUTPUT_LVDS:
5613 is_lvds = true;
5614 break;
79e53945
JB		 5615 }
5616 }
5617
d9d444cb 5618 refclk = ironlake_get_refclk(crtc);
79e53945 5619
d4906093
ML		 5620 /*
5621 * Returns a set of divisors for the desired target clock with the given
5622 * refclk, or FALSE. The returned values represent the clock equation:
5623 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5624 */
1b894b59 5625 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5626 ret = dev_priv->display.find_dpll(limit, crtc,
5627 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5628 refclk, NULL, clock);
6591c6e4
PZ		 5629 if (!ret)
5630 return false;
cda4b7d3 5631
ddc9003c 5632 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5633 /*
5634 * Ensure we match the reduced clock's P to the target clock.
5635 * If the clocks don't match, we can't switch the display clock
5636 * by using the FP0/FP1. In such case we will disable the LVDS
5637 * downclock feature.
5638 */
ee9300bb
DV		 5639 *has_reduced_clock =
5640 dev_priv->display.find_dpll(limit, crtc,
5641 dev_priv->lvds_downclock,
5642 refclk, clock,
5643 reduced_clock);
652c393a 5644 }
61e9653f 5645
6591c6e4
PZ		 5646 return true;
5647}
5648
01a415fd
DV		 5649static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5650{
5651 struct drm_i915_private *dev_priv = dev->dev_private;
5652 uint32_t temp;
5653
5654 temp = I915_READ(SOUTH_CHICKEN1);
5655 if (temp & FDI_BC_BIFURCATION_SELECT)
5656 return;
5657
5658 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5659 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5660
5661 temp |= FDI_BC_BIFURCATION_SELECT;
5662 DRM_DEBUG_KMS("enabling fdi C rx\n");
5663 I915_WRITE(SOUTH_CHICKEN1, temp);
5664 POSTING_READ(SOUTH_CHICKEN1);
5665}
5666
ebfd86fd 5667static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5668{
5669 struct drm_device *dev = intel_crtc->base.dev;
5670 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5671
5672 switch (intel_crtc->pipe) {
5673 case PIPE_A:
ebfd86fd 5674 break;
01a415fd 5675 case PIPE_B:
ebfd86fd 5676 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5677 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5678 else
5679 cpt_enable_fdi_bc_bifurcation(dev);
5680
ebfd86fd 5681 break;
01a415fd 5682 case PIPE_C:
01a415fd
DV		 5683 cpt_enable_fdi_bc_bifurcation(dev);
5684
ebfd86fd 5685 break;
01a415fd
DV		 5686 default:
5687 BUG();
5688 }
5689}
5690
d4b1931c
PZ		 5691int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5692{
5693 /*
5694 * Account for spread spectrum to avoid
5695 * oversubscribing the link. Max center spread
5696 * is 2.5%; use 5% for safety's sake.
5697 */
5698 u32 bps = target_clock * bpp * 21 / 20;
5699 return bps / (link_bw * 8) + 1;
5700}
5701
7429e9d4 5702static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5703{
7429e9d4 5704 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5705}
5706
de13a2e3 5707static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5708 u32 *fp,
9a7c7890 5709 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5710{
de13a2e3 5711 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5712 struct drm_device *dev = crtc->dev;
5713 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5714 struct intel_encoder *intel_encoder;
5715 uint32_t dpll;
6cc5f341 5716 int factor, num_connectors = 0;
09ede541 5717 bool is_lvds = false, is_sdvo = false;
79e53945 5718
de13a2e3
PZ		 5719 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5720 switch (intel_encoder->type) {
79e53945
JB		 5721 case INTEL_OUTPUT_LVDS:
5722 is_lvds = true;
5723 break;
5724 case INTEL_OUTPUT_SDVO:
7d57382e 5725 case INTEL_OUTPUT_HDMI:
79e53945 5726 is_sdvo = true;
79e53945 5727 break;
79e53945 5728 }
43565a06 5729
c751ce4f 5730 num_connectors++;
79e53945 5731 }
79e53945 5732
c1858123 5733 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5734 factor = 21;
5735 if (is_lvds) {
5736 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5737 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5738 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5739 factor = 25;
09ede541 5740 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5741 factor = 20;
c1858123 5742
7429e9d4 5743 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5744 *fp |= FP_CB_TUNE;
2c07245f 5745
9a7c7890
DV		 5746 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5747 *fp2 |= FP_CB_TUNE;
5748
5eddb70b 5749 dpll = 0;
2c07245f 5750
a07d6787
EA		 5751 if (is_lvds)
5752 dpll |= DPLLB_MODE_LVDS;
5753 else
5754 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5755
ef1b460d
DV		 5756 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5757 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5758
5759 if (is_sdvo)
4a33e48d 5760 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5761 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5762 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5763
a07d6787 5764 /* compute bitmask from p1 value */
7429e9d4 5765 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5766 /* also FPA1 */
7429e9d4 5767 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5768
7429e9d4 5769 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5770 case 5:
5771 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5772 break;
5773 case 7:
5774 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5775 break;
5776 case 10:
5777 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5778 break;
5779 case 14:
5780 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5781 break;
79e53945
JB		 5782 }
5783
b4c09f3b 5784 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5785 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5786 else
5787 dpll |= PLL_REF_INPUT_DREFCLK;
5788
959e16d6 5789 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5790}
5791
5792static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5793 int x, int y,
5794 struct drm_framebuffer *fb)
5795{
5796 struct drm_device *dev = crtc->dev;
5797 struct drm_i915_private *dev_priv = dev->dev_private;
5798 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5799 int pipe = intel_crtc->pipe;
5800 int plane = intel_crtc->plane;
5801 int num_connectors = 0;
5802 intel_clock_t clock, reduced_clock;
cbbab5bd 5803 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5804 bool ok, has_reduced_clock = false;
8b47047b 5805 bool is_lvds = false;
de13a2e3 5806 struct intel_encoder *encoder;
e2b78267 5807 struct intel_shared_dpll *pll;
de13a2e3 5808 int ret;
de13a2e3
PZ		 5809
5810 for_each_encoder_on_crtc(dev, crtc, encoder) {
5811 switch (encoder->type) {
5812 case INTEL_OUTPUT_LVDS:
5813 is_lvds = true;
5814 break;
de13a2e3
PZ		 5815 }
5816
5817 num_connectors++;
a07d6787 5818 }
79e53945 5819
5dc5298b
PZ		 5820 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5821 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5822
ff9a6750 5823 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5824 &has_reduced_clock, &reduced_clock);
ee9300bb 5825 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5826 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5827 return -EINVAL;
79e53945 5828 }
f47709a9
DV		 5829 /* Compat-code for transition, will disappear. */
5830 if (!intel_crtc->config.clock_set) {
5831 intel_crtc->config.dpll.n = clock.n;
5832 intel_crtc->config.dpll.m1 = clock.m1;
5833 intel_crtc->config.dpll.m2 = clock.m2;
5834 intel_crtc->config.dpll.p1 = clock.p1;
5835 intel_crtc->config.dpll.p2 = clock.p2;
5836 }
79e53945 5837
de13a2e3
PZ		 5838 /* Ensure that the cursor is valid for the new mode before changing... */
5839 intel_crtc_update_cursor(crtc, true);
5840
5dc5298b 5841 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5842 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5843 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5844 if (has_reduced_clock)
7429e9d4 5845 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5846
7429e9d4 5847 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5848 &fp, &reduced_clock,
5849 has_reduced_clock ? &fp2 : NULL);
5850
959e16d6 5851 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5852 intel_crtc->config.dpll_hw_state.fp0 = fp;
5853 if (has_reduced_clock)
5854 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5855 else
5856 intel_crtc->config.dpll_hw_state.fp1 = fp;
5857
b89a1d39 5858 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5859 if (pll == NULL) {
84f44ce7
VS		 5860 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5861 pipe_name(pipe));
4b645f14
JB		 5862 return -EINVAL;
5863 }
ee7b9f93 5864 } else
e72f9fbf 5865 intel_put_shared_dpll(intel_crtc);
79e53945 5866
03afc4a2
DV		 5867 if (intel_crtc->config.has_dp_encoder)
5868 intel_dp_set_m_n(intel_crtc);
79e53945 5869
bcd644e0
DV		 5870 if (is_lvds && has_reduced_clock && i915_powersave)
5871 intel_crtc->lowfreq_avail = true;
5872 else
5873 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5874
5875 if (intel_crtc->config.has_pch_encoder) {
5876 pll = intel_crtc_to_shared_dpll(intel_crtc);
5877
652c393a
JB		 5878 }
5879
8a654f3b 5880 intel_set_pipe_timings(intel_crtc);
5eddb70b 5881
ca3a0ff8 5882 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5883 intel_cpu_transcoder_set_m_n(intel_crtc,
5884 &intel_crtc->config.fdi_m_n);
5885 }
2c07245f 5886
ebfd86fd
DV		 5887 if (IS_IVYBRIDGE(dev))
5888 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5889
6ff93609 5890 ironlake_set_pipeconf(crtc);
79e53945 5891
a1f9e77e
PZ		 5892 /* Set up the display plane register */
5893 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5894 POSTING_READ(DSPCNTR(plane));
79e53945 5895
94352cf9 5896 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd 5897
1857e1da 5898 return ret;
79e53945
JB		 5899}
5900
eb14cb74
VS		 5901static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
5902 struct intel_link_m_n *m_n)
5903{
5904 struct drm_device *dev = crtc->base.dev;
5905 struct drm_i915_private *dev_priv = dev->dev_private;
5906 enum pipe pipe = crtc->pipe;
5907
5908 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
5909 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
5910 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
5911 & ~TU_SIZE_MASK;
5912 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
5913 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
5914 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5915}
5916
5917static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
5918 enum transcoder transcoder,
5919 struct intel_link_m_n *m_n)
72419203
DV		 5920{
5921 struct drm_device *dev = crtc->base.dev;
5922 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74
VS		 5923 enum pipe pipe = crtc->pipe;
5924
5925 if (INTEL_INFO(dev)->gen >= 5) {
5926 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
5927 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
5928 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5929 & ~TU_SIZE_MASK;
5930 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5931 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5932 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5933 } else {
5934 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
5935 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
5936 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
5937 & ~TU_SIZE_MASK;
5938 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
5939 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
5940 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5941 }
5942}
5943
5944void intel_dp_get_m_n(struct intel_crtc *crtc,
5945 struct intel_crtc_config *pipe_config)
5946{
5947 if (crtc->config.has_pch_encoder)
5948 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
5949 else
5950 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5951 &pipe_config->dp_m_n);
5952}
72419203 5953
eb14cb74
VS		 5954static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5955 struct intel_crtc_config *pipe_config)
5956{
5957 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
5958 &pipe_config->fdi_m_n);
72419203
DV		 5959}
5960
2fa2fe9a
DV		 5961static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5962 struct intel_crtc_config *pipe_config)
5963{
5964 struct drm_device *dev = crtc->base.dev;
5965 struct drm_i915_private *dev_priv = dev->dev_private;
5966 uint32_t tmp;
5967
5968 tmp = I915_READ(PF_CTL(crtc->pipe));
5969
5970 if (tmp & PF_ENABLE) {
5971 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5972 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5973
5974 /* We currently do not free assignements of panel fitters on
5975 * ivb/hsw (since we don't use the higher upscaling modes which
5976 * differentiates them) so just WARN about this case for now. */
5977 if (IS_GEN7(dev)) {
5978 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5979 PF_PIPE_SEL_IVB(crtc->pipe));
5980 }
2fa2fe9a 5981 }
79e53945
JB		 5982}
5983
0e8ffe1b
DV		 5984static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5985 struct intel_crtc_config *pipe_config)
5986{
5987 struct drm_device *dev = crtc->base.dev;
5988 struct drm_i915_private *dev_priv = dev->dev_private;
5989 uint32_t tmp;
5990
e143a21c 5991 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5992 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5993
0e8ffe1b
DV		 5994 tmp = I915_READ(PIPECONF(crtc->pipe));
5995 if (!(tmp & PIPECONF_ENABLE))
5996 return false;
5997
42571aef
VS		 5998 switch (tmp & PIPECONF_BPC_MASK) {
5999 case PIPECONF_6BPC:
6000 pipe_config->pipe_bpp = 18;
6001 break;
6002 case PIPECONF_8BPC:
6003 pipe_config->pipe_bpp = 24;
6004 break;
6005 case PIPECONF_10BPC:
6006 pipe_config->pipe_bpp = 30;
6007 break;
6008 case PIPECONF_12BPC:
6009 pipe_config->pipe_bpp = 36;
6010 break;
6011 default:
6012 break;
6013 }
6014
ab9412ba 6015 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 6016 struct intel_shared_dpll *pll;
6017
88adfff1
DV		 6018 pipe_config->has_pch_encoder = true;
6019
627eb5a3
DV		 6020 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6021 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6022 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6023
6024 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 6025
c0d43d62 6026 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 6027 pipe_config->shared_dpll =
6028 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 6029 } else {
6030 tmp = I915_READ(PCH_DPLL_SEL);
6031 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6032 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6033 else
6034 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6035 }
66e985c0
DV		 6036
6037 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6038
6039 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6040 &pipe_config->dpll_hw_state));
c93f54cf
DV		 6041
6042 tmp = pipe_config->dpll_hw_state.dpll;
6043 pipe_config->pixel_multiplier =
6044 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6045 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 6046
6047 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 6048 } else {
6049 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 6050 }
6051
1bd1bd80
DV		 6052 intel_get_pipe_timings(crtc, pipe_config);
6053
2fa2fe9a
DV		 6054 ironlake_get_pfit_config(crtc, pipe_config);
6055
0e8ffe1b
DV		 6056 return true;
6057}
6058
be256dc7
PZ		 6059static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6060{
6061 struct drm_device *dev = dev_priv->dev;
6062 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6063 struct intel_crtc *crtc;
6064 unsigned long irqflags;
bd633a7c 6065 uint32_t val;
be256dc7
PZ		 6066
6067 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6068 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6069 pipe_name(crtc->pipe));
6070
6071 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6072 WARN(plls->spll_refcount, "SPLL enabled\n");
6073 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6074 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6075 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6076 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6077 "CPU PWM1 enabled\n");
6078 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6079 "CPU PWM2 enabled\n");
6080 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6081 "PCH PWM1 enabled\n");
6082 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6083 "Utility pin enabled\n");
6084 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6085
6086 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6087 val = I915_READ(DEIMR);
6088 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6089 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6090 val = I915_READ(SDEIMR);
bd633a7c 6091 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 6092 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6093 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6094}
6095
6096/*
6097 * This function implements pieces of two sequences from BSpec:
6098 * - Sequence for display software to disable LCPLL
6099 * - Sequence for display software to allow package C8+
6100 * The steps implemented here are just the steps that actually touch the LCPLL
6101 * register. Callers should take care of disabling all the display engine
6102 * functions, doing the mode unset, fixing interrupts, etc.
6103 */
6104void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6105 bool switch_to_fclk, bool allow_power_down)
6106{
6107 uint32_t val;
6108
6109 assert_can_disable_lcpll(dev_priv);
6110
6111 val = I915_READ(LCPLL_CTL);
6112
6113 if (switch_to_fclk) {
6114 val |= LCPLL_CD_SOURCE_FCLK;
6115 I915_WRITE(LCPLL_CTL, val);
6116
6117 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6118 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6119 DRM_ERROR("Switching to FCLK failed\n");
6120
6121 val = I915_READ(LCPLL_CTL);
6122 }
6123
6124 val |= LCPLL_PLL_DISABLE;
6125 I915_WRITE(LCPLL_CTL, val);
6126 POSTING_READ(LCPLL_CTL);
6127
6128 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6129 DRM_ERROR("LCPLL still locked\n");
6130
6131 val = I915_READ(D_COMP);
6132 val |= D_COMP_COMP_DISABLE;
6133 I915_WRITE(D_COMP, val);
6134 POSTING_READ(D_COMP);
6135 ndelay(100);
6136
6137 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6138 DRM_ERROR("D_COMP RCOMP still in progress\n");
6139
6140 if (allow_power_down) {
6141 val = I915_READ(LCPLL_CTL);
6142 val |= LCPLL_POWER_DOWN_ALLOW;
6143 I915_WRITE(LCPLL_CTL, val);
6144 POSTING_READ(LCPLL_CTL);
6145 }
6146}
6147
6148/*
6149 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6150 * source.
6151 */
6152void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
6153{
6154 uint32_t val;
6155
6156 val = I915_READ(LCPLL_CTL);
6157
6158 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6159 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6160 return;
6161
215733fa
PZ		 6162 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6163 * we'll hang the machine! */
6164 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6165
be256dc7
PZ		 6166 if (val & LCPLL_POWER_DOWN_ALLOW) {
6167 val &= ~LCPLL_POWER_DOWN_ALLOW;
6168 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6169 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6170 }
6171
6172 val = I915_READ(D_COMP);
6173 val |= D_COMP_COMP_FORCE;
6174 val &= ~D_COMP_COMP_DISABLE;
6175 I915_WRITE(D_COMP, val);
35d8f2eb 6176 POSTING_READ(D_COMP);
be256dc7
PZ		 6177
6178 val = I915_READ(LCPLL_CTL);
6179 val &= ~LCPLL_PLL_DISABLE;
6180 I915_WRITE(LCPLL_CTL, val);
6181
6182 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6183 DRM_ERROR("LCPLL not locked yet\n");
6184
6185 if (val & LCPLL_CD_SOURCE_FCLK) {
6186 val = I915_READ(LCPLL_CTL);
6187 val &= ~LCPLL_CD_SOURCE_FCLK;
6188 I915_WRITE(LCPLL_CTL, val);
6189
6190 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6191 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6192 DRM_ERROR("Switching back to LCPLL failed\n");
6193 }
215733fa
PZ		 6194
6195 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6196}
6197
c67a470b
PZ		 6198void hsw_enable_pc8_work(struct work_struct *__work)
6199{
6200 struct drm_i915_private *dev_priv =
6201 container_of(to_delayed_work(__work), struct drm_i915_private,
6202 pc8.enable_work);
6203 struct drm_device *dev = dev_priv->dev;
6204 uint32_t val;
6205
6206 if (dev_priv->pc8.enabled)
6207 return;
6208
6209 DRM_DEBUG_KMS("Enabling package C8+\n");
6210
6211 dev_priv->pc8.enabled = true;
6212
6213 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6214 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6215 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6216 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6217 }
6218
6219 lpt_disable_clkout_dp(dev);
6220 hsw_pc8_disable_interrupts(dev);
6221 hsw_disable_lcpll(dev_priv, true, true);
6222}
6223
6224static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6225{
6226 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6227 WARN(dev_priv->pc8.disable_count < 1,
6228 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6229
6230 dev_priv->pc8.disable_count--;
6231 if (dev_priv->pc8.disable_count != 0)
6232 return;
6233
6234 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6235 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6236}
6237
6238static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6239{
6240 struct drm_device *dev = dev_priv->dev;
6241 uint32_t val;
6242
6243 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6244 WARN(dev_priv->pc8.disable_count < 0,
6245 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6246
6247 dev_priv->pc8.disable_count++;
6248 if (dev_priv->pc8.disable_count != 1)
6249 return;
6250
6251 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6252 if (!dev_priv->pc8.enabled)
6253 return;
6254
6255 DRM_DEBUG_KMS("Disabling package C8+\n");
6256
6257 hsw_restore_lcpll(dev_priv);
6258 hsw_pc8_restore_interrupts(dev);
6259 lpt_init_pch_refclk(dev);
6260
6261 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6262 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6263 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6264 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6265 }
6266
6267 intel_prepare_ddi(dev);
6268 i915_gem_init_swizzling(dev);
6269 mutex_lock(&dev_priv->rps.hw_lock);
6270 gen6_update_ring_freq(dev);
6271 mutex_unlock(&dev_priv->rps.hw_lock);
6272 dev_priv->pc8.enabled = false;
6273}
6274
6275void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6276{
6277 mutex_lock(&dev_priv->pc8.lock);
6278 __hsw_enable_package_c8(dev_priv);
6279 mutex_unlock(&dev_priv->pc8.lock);
6280}
6281
6282void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6283{
6284 mutex_lock(&dev_priv->pc8.lock);
6285 __hsw_disable_package_c8(dev_priv);
6286 mutex_unlock(&dev_priv->pc8.lock);
6287}
6288
6289static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6290{
6291 struct drm_device *dev = dev_priv->dev;
6292 struct intel_crtc *crtc;
6293 uint32_t val;
6294
6295 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6296 if (crtc->base.enabled)
6297 return false;
6298
6299 /* This case is still possible since we have the i915.disable_power_well
6300 * parameter and also the KVMr or something else might be requesting the
6301 * power well. */
6302 val = I915_READ(HSW_PWR_WELL_DRIVER);
6303 if (val != 0) {
6304 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6305 return false;
6306 }
6307
6308 return true;
6309}
6310
6311/* Since we're called from modeset_global_resources there's no way to
6312 * symmetrically increase and decrease the refcount, so we use
6313 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6314 * or not.
6315 */
6316static void hsw_update_package_c8(struct drm_device *dev)
6317{
6318 struct drm_i915_private *dev_priv = dev->dev_private;
6319 bool allow;
6320
6321 if (!i915_enable_pc8)
6322 return;
6323
6324 mutex_lock(&dev_priv->pc8.lock);
6325
6326 allow = hsw_can_enable_package_c8(dev_priv);
6327
6328 if (allow == dev_priv->pc8.requirements_met)
6329 goto done;
6330
6331 dev_priv->pc8.requirements_met = allow;
6332
6333 if (allow)
6334 __hsw_enable_package_c8(dev_priv);
6335 else
6336 __hsw_disable_package_c8(dev_priv);
6337
6338done:
6339 mutex_unlock(&dev_priv->pc8.lock);
6340}
6341
6342static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6343{
6344 if (!dev_priv->pc8.gpu_idle) {
6345 dev_priv->pc8.gpu_idle = true;
6346 hsw_enable_package_c8(dev_priv);
6347 }
6348}
6349
6350static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6351{
6352 if (dev_priv->pc8.gpu_idle) {
6353 dev_priv->pc8.gpu_idle = false;
6354 hsw_disable_package_c8(dev_priv);
6355 }
be256dc7
PZ		 6356}
6357
d6dd9eb1
DV		 6358static void haswell_modeset_global_resources(struct drm_device *dev)
6359{
d6dd9eb1
DV		 6360 bool enable = false;
6361 struct intel_crtc *crtc;
d6dd9eb1
DV		 6362
6363 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6364 if (!crtc->base.enabled)
6365 continue;
d6dd9eb1 6366
e7a639c4
DV		 6367 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
6368 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6369 enable = true;
6370 }
6371
d6dd9eb1 6372 intel_set_power_well(dev, enable);
c67a470b
PZ		 6373
6374 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6375}
6376
09b4ddf9 6377static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6378 int x, int y,
6379 struct drm_framebuffer *fb)
6380{
6381 struct drm_device *dev = crtc->dev;
6382 struct drm_i915_private *dev_priv = dev->dev_private;
6383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6384 int plane = intel_crtc->plane;
09b4ddf9 6385 int ret;
09b4ddf9 6386
ff9a6750 6387 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6388 return -EINVAL;
6389
09b4ddf9
PZ		 6390 /* Ensure that the cursor is valid for the new mode before changing... */
6391 intel_crtc_update_cursor(crtc, true);
6392
03afc4a2
DV		 6393 if (intel_crtc->config.has_dp_encoder)
6394 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6395
6396 intel_crtc->lowfreq_avail = false;
09b4ddf9 6397
8a654f3b 6398 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6399
ca3a0ff8 6400 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6401 intel_cpu_transcoder_set_m_n(intel_crtc,
6402 &intel_crtc->config.fdi_m_n);
6403 }
09b4ddf9 6404
6ff93609 6405 haswell_set_pipeconf(crtc);
09b4ddf9 6406
50f3b016 6407 intel_set_pipe_csc(crtc);
86d3efce 6408
09b4ddf9 6409 /* Set up the display plane register */
86d3efce 6410 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6411 POSTING_READ(DSPCNTR(plane));
6412
6413 ret = intel_pipe_set_base(crtc, x, y, fb);
6414
1f803ee5 6415 return ret;
79e53945
JB		 6416}
6417
0e8ffe1b
DV		 6418static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6419 struct intel_crtc_config *pipe_config)
6420{
6421 struct drm_device *dev = crtc->base.dev;
6422 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6423 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6424 uint32_t tmp;
6425
e143a21c 6426 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6427 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6428
eccb140b
DV		 6429 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6430 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6431 enum pipe trans_edp_pipe;
6432 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6433 default:
6434 WARN(1, "unknown pipe linked to edp transcoder\n");
6435 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6436 case TRANS_DDI_EDP_INPUT_A_ON:
6437 trans_edp_pipe = PIPE_A;
6438 break;
6439 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6440 trans_edp_pipe = PIPE_B;
6441 break;
6442 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6443 trans_edp_pipe = PIPE_C;
6444 break;
6445 }
6446
6447 if (trans_edp_pipe == crtc->pipe)
6448 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6449 }
6450
b97186f0 6451 if (!intel_display_power_enabled(dev,
eccb140b 6452 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6453 return false;
6454
eccb140b 6455 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6456 if (!(tmp & PIPECONF_ENABLE))
6457 return false;
6458
88adfff1 6459 /*
f196e6be 6460 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6461 * DDI E. So just check whether this pipe is wired to DDI E and whether
6462 * the PCH transcoder is on.
6463 */
eccb140b 6464 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6465 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6466 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6467 pipe_config->has_pch_encoder = true;
6468
627eb5a3
DV		 6469 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6470 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6471 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6472
6473 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6474 }
6475
1bd1bd80
DV		 6476 intel_get_pipe_timings(crtc, pipe_config);
6477
2fa2fe9a
DV		 6478 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6479 if (intel_display_power_enabled(dev, pfit_domain))
6480 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6481
42db64ef
PZ		 6482 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6483 (I915_READ(IPS_CTL) & IPS_ENABLE);
6484
6c49f241
DV		 6485 pipe_config->pixel_multiplier = 1;
6486
0e8ffe1b
DV		 6487 return true;
6488}
6489
f564048e 6490static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6491 int x, int y,
94352cf9 6492 struct drm_framebuffer *fb)
f564048e
EA		 6493{
6494 struct drm_device *dev = crtc->dev;
6495 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6496 struct intel_encoder *encoder;
0b701d27 6497 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6498 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6499 int pipe = intel_crtc->pipe;
f564048e
EA		 6500 int ret;
6501
0b701d27 6502 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6503
b8cecdf5
DV		 6504 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6505
79e53945 6506 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6507
9256aa19
DV		 6508 if (ret != 0)
6509 return ret;
6510
6511 for_each_encoder_on_crtc(dev, crtc, encoder) {
6512 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6513 encoder->base.base.id,
6514 drm_get_encoder_name(&encoder->base),
6515 mode->base.id, mode->name);
36f2d1f1 6516 encoder->mode_set(encoder);
9256aa19
DV		 6517 }
6518
6519 return 0;
79e53945
JB		 6520}
6521
3a9627f4
WF		 6522static bool intel_eld_uptodate(struct drm_connector *connector,
6523 int reg_eldv, uint32_t bits_eldv,
6524 int reg_elda, uint32_t bits_elda,
6525 int reg_edid)
6526{
6527 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6528 uint8_t *eld = connector->eld;
6529 uint32_t i;
6530
6531 i = I915_READ(reg_eldv);
6532 i &= bits_eldv;
6533
6534 if (!eld[0])
6535 return !i;
6536
6537 if (!i)
6538 return false;
6539
6540 i = I915_READ(reg_elda);
6541 i &= ~bits_elda;
6542 I915_WRITE(reg_elda, i);
6543
6544 for (i = 0; i < eld[2]; i++)
6545 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6546 return false;
6547
6548 return true;
6549}
6550
e0dac65e
WF		 6551static void g4x_write_eld(struct drm_connector *connector,
6552 struct drm_crtc *crtc)
6553{
6554 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6555 uint8_t *eld = connector->eld;
6556 uint32_t eldv;
6557 uint32_t len;
6558 uint32_t i;
6559
6560 i = I915_READ(G4X_AUD_VID_DID);
6561
6562 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6563 eldv = G4X_ELDV_DEVCL_DEVBLC;
6564 else
6565 eldv = G4X_ELDV_DEVCTG;
6566
3a9627f4
WF		 6567 if (intel_eld_uptodate(connector,
6568 G4X_AUD_CNTL_ST, eldv,
6569 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6570 G4X_HDMIW_HDMIEDID))
6571 return;
6572
e0dac65e
WF		 6573 i = I915_READ(G4X_AUD_CNTL_ST);
6574 i &= ~(eldv | G4X_ELD_ADDR);
6575 len = (i >> 9) & 0x1f; /* ELD buffer size */
6576 I915_WRITE(G4X_AUD_CNTL_ST, i);
6577
6578 if (!eld[0])
6579 return;
6580
6581 len = min_t(uint8_t, eld[2], len);
6582 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6583 for (i = 0; i < len; i++)
6584 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6585
6586 i = I915_READ(G4X_AUD_CNTL_ST);
6587 i |= eldv;
6588 I915_WRITE(G4X_AUD_CNTL_ST, i);
6589}
6590
83358c85
WX		 6591static void haswell_write_eld(struct drm_connector *connector,
6592 struct drm_crtc *crtc)
6593{
6594 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6595 uint8_t *eld = connector->eld;
6596 struct drm_device *dev = crtc->dev;
7b9f35a6 6597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6598 uint32_t eldv;
6599 uint32_t i;
6600 int len;
6601 int pipe = to_intel_crtc(crtc)->pipe;
6602 int tmp;
6603
6604 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6605 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6606 int aud_config = HSW_AUD_CFG(pipe);
6607 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6608
6609
6610 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6611
6612 /* Audio output enable */
6613 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6614 tmp = I915_READ(aud_cntrl_st2);
6615 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6616 I915_WRITE(aud_cntrl_st2, tmp);
6617
6618 /* Wait for 1 vertical blank */
6619 intel_wait_for_vblank(dev, pipe);
6620
6621 /* Set ELD valid state */
6622 tmp = I915_READ(aud_cntrl_st2);
6623 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6624 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6625 I915_WRITE(aud_cntrl_st2, tmp);
6626 tmp = I915_READ(aud_cntrl_st2);
6627 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6628
6629 /* Enable HDMI mode */
6630 tmp = I915_READ(aud_config);
6631 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6632 /* clear N_programing_enable and N_value_index */
6633 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6634 I915_WRITE(aud_config, tmp);
6635
6636 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6637
6638 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6639 intel_crtc->eld_vld = true;
83358c85
WX		 6640
6641 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6642 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6643 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6644 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6645 } else
6646 I915_WRITE(aud_config, 0);
6647
6648 if (intel_eld_uptodate(connector,
6649 aud_cntrl_st2, eldv,
6650 aud_cntl_st, IBX_ELD_ADDRESS,
6651 hdmiw_hdmiedid))
6652 return;
6653
6654 i = I915_READ(aud_cntrl_st2);
6655 i &= ~eldv;
6656 I915_WRITE(aud_cntrl_st2, i);
6657
6658 if (!eld[0])
6659 return;
6660
6661 i = I915_READ(aud_cntl_st);
6662 i &= ~IBX_ELD_ADDRESS;
6663 I915_WRITE(aud_cntl_st, i);
6664 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6665 DRM_DEBUG_DRIVER("port num:%d\n", i);
6666
6667 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6668 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6669 for (i = 0; i < len; i++)
6670 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6671
6672 i = I915_READ(aud_cntrl_st2);
6673 i |= eldv;
6674 I915_WRITE(aud_cntrl_st2, i);
6675
6676}
6677
e0dac65e
WF		 6678static void ironlake_write_eld(struct drm_connector *connector,
6679 struct drm_crtc *crtc)
6680{
6681 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6682 uint8_t *eld = connector->eld;
6683 uint32_t eldv;
6684 uint32_t i;
6685 int len;
6686 int hdmiw_hdmiedid;
b6daa025 6687 int aud_config;
e0dac65e
WF		 6688 int aud_cntl_st;
6689 int aud_cntrl_st2;
9b138a83 6690 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6691
b3f33cbf 6692 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6693 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6694 aud_config = IBX_AUD_CFG(pipe);
6695 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6696 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6697 } else {
9b138a83
WX		 6698 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6699 aud_config = CPT_AUD_CFG(pipe);
6700 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6701 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6702 }
6703
9b138a83 6704 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6705
6706 i = I915_READ(aud_cntl_st);
9b138a83 6707 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6708 if (!i) {
6709 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6710 /* operate blindly on all ports */
1202b4c6
WF		 6711 eldv = IBX_ELD_VALIDB;
6712 eldv |= IBX_ELD_VALIDB << 4;
6713 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6714 } else {
2582a850 6715 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6716 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6717 }
6718
3a9627f4
WF		 6719 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6720 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6721 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6722 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6723 } else
6724 I915_WRITE(aud_config, 0);
e0dac65e 6725
3a9627f4
WF		 6726 if (intel_eld_uptodate(connector,
6727 aud_cntrl_st2, eldv,
6728 aud_cntl_st, IBX_ELD_ADDRESS,
6729 hdmiw_hdmiedid))
6730 return;
6731
e0dac65e
WF		 6732 i = I915_READ(aud_cntrl_st2);
6733 i &= ~eldv;
6734 I915_WRITE(aud_cntrl_st2, i);
6735
6736 if (!eld[0])
6737 return;
6738
e0dac65e 6739 i = I915_READ(aud_cntl_st);
1202b4c6 6740 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6741 I915_WRITE(aud_cntl_st, i);
6742
6743 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6744 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6745 for (i = 0; i < len; i++)
6746 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6747
6748 i = I915_READ(aud_cntrl_st2);
6749 i |= eldv;
6750 I915_WRITE(aud_cntrl_st2, i);
6751}
6752
6753void intel_write_eld(struct drm_encoder *encoder,
6754 struct drm_display_mode *mode)
6755{
6756 struct drm_crtc *crtc = encoder->crtc;
6757 struct drm_connector *connector;
6758 struct drm_device *dev = encoder->dev;
6759 struct drm_i915_private *dev_priv = dev->dev_private;
6760
6761 connector = drm_select_eld(encoder, mode);
6762 if (!connector)
6763 return;
6764
6765 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6766 connector->base.id,
6767 drm_get_connector_name(connector),
6768 connector->encoder->base.id,
6769 drm_get_encoder_name(connector->encoder));
6770
6771 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6772
6773 if (dev_priv->display.write_eld)
6774 dev_priv->display.write_eld(connector, crtc);
6775}
6776
79e53945
JB		 6777/** Loads the palette/gamma unit for the CRTC with the prepared values */
6778void intel_crtc_load_lut(struct drm_crtc *crtc)
6779{
6780 struct drm_device *dev = crtc->dev;
6781 struct drm_i915_private *dev_priv = dev->dev_private;
6782 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6783 enum pipe pipe = intel_crtc->pipe;
6784 int palreg = PALETTE(pipe);
79e53945 6785 int i;
42db64ef 6786 bool reenable_ips = false;
79e53945
JB		 6787
6788 /* The clocks have to be on to load the palette. */
aed3f09d 6789 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6790 return;
6791
23538ef1
JN		 6792 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
6793 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
6794 assert_dsi_pll_enabled(dev_priv);
6795 else
6796 assert_pll_enabled(dev_priv, pipe);
6797 }
14420bd0 6798
f2b115e6 6799 /* use legacy palette for Ironlake */
bad720ff 6800 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6801 palreg = LGC_PALETTE(pipe);
6802
6803 /* Workaround : Do not read or write the pipe palette/gamma data while
6804 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6805 */
6806 if (intel_crtc->config.ips_enabled &&
6807 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6808 GAMMA_MODE_MODE_SPLIT)) {
6809 hsw_disable_ips(intel_crtc);
6810 reenable_ips = true;
6811 }
2c07245f 6812
79e53945
JB		 6813 for (i = 0; i < 256; i++) {
6814 I915_WRITE(palreg + 4 * i,
6815 (intel_crtc->lut_r[i] << 16) |
6816 (intel_crtc->lut_g[i] << 8) |
6817 intel_crtc->lut_b[i]);
6818 }
42db64ef
PZ		 6819
6820 if (reenable_ips)
6821 hsw_enable_ips(intel_crtc);
79e53945
JB		 6822}
6823
560b85bb
CW		 6824static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6825{
6826 struct drm_device *dev = crtc->dev;
6827 struct drm_i915_private *dev_priv = dev->dev_private;
6828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6829 bool visible = base != 0;
6830 u32 cntl;
6831
6832 if (intel_crtc->cursor_visible == visible)
6833 return;
6834
9db4a9c7 6835 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6836 if (visible) {
6837 /* On these chipsets we can only modify the base whilst
6838 * the cursor is disabled.
6839 */
9db4a9c7 6840 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6841
6842 cntl &= ~(CURSOR_FORMAT_MASK);
6843 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6844 cntl |= CURSOR_ENABLE |
6845 CURSOR_GAMMA_ENABLE |
6846 CURSOR_FORMAT_ARGB;
6847 } else
6848 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6849 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6850
6851 intel_crtc->cursor_visible = visible;
6852}
6853
6854static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6855{
6856 struct drm_device *dev = crtc->dev;
6857 struct drm_i915_private *dev_priv = dev->dev_private;
6858 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6859 int pipe = intel_crtc->pipe;
6860 bool visible = base != 0;
6861
6862 if (intel_crtc->cursor_visible != visible) {
548f245b 6863 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6864 if (base) {
6865 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6866 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6867 cntl |= pipe << 28; /* Connect to correct pipe */
6868 } else {
6869 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6870 cntl |= CURSOR_MODE_DISABLE;
6871 }
9db4a9c7 6872 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6873
6874 intel_crtc->cursor_visible = visible;
6875 }
6876 /* and commit changes on next vblank */
9db4a9c7 6877 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6878}
6879
65a21cd6
JB		 6880static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6881{
6882 struct drm_device *dev = crtc->dev;
6883 struct drm_i915_private *dev_priv = dev->dev_private;
6884 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6885 int pipe = intel_crtc->pipe;
6886 bool visible = base != 0;
6887
6888 if (intel_crtc->cursor_visible != visible) {
6889 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6890 if (base) {
6891 cntl &= ~CURSOR_MODE;
6892 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6893 } else {
6894 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6895 cntl |= CURSOR_MODE_DISABLE;
6896 }
1f5d76db 6897 if (IS_HASWELL(dev)) {
86d3efce 6898 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 6899 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
6900 }
65a21cd6
JB		 6901 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6902
6903 intel_crtc->cursor_visible = visible;
6904 }
6905 /* and commit changes on next vblank */
6906 I915_WRITE(CURBASE_IVB(pipe), base);
6907}
6908
cda4b7d3 6909/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6910static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6911 bool on)
cda4b7d3
CW		 6912{
6913 struct drm_device *dev = crtc->dev;
6914 struct drm_i915_private *dev_priv = dev->dev_private;
6915 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6916 int pipe = intel_crtc->pipe;
6917 int x = intel_crtc->cursor_x;
6918 int y = intel_crtc->cursor_y;
d6e4db15 6919 u32 base = 0, pos = 0;
cda4b7d3
CW		 6920 bool visible;
6921
d6e4db15 6922 if (on)
cda4b7d3 6923 base = intel_crtc->cursor_addr;
cda4b7d3 6924
d6e4db15
VS		 6925 if (x >= intel_crtc->config.pipe_src_w)
6926 base = 0;
6927
6928 if (y >= intel_crtc->config.pipe_src_h)
cda4b7d3
CW		 6929 base = 0;
6930
6931 if (x < 0) {
efc9064e 6932 if (x + intel_crtc->cursor_width <= 0)
cda4b7d3
CW		 6933 base = 0;
6934
6935 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6936 x = -x;
6937 }
6938 pos |= x << CURSOR_X_SHIFT;
6939
6940 if (y < 0) {
efc9064e 6941 if (y + intel_crtc->cursor_height <= 0)
cda4b7d3
CW		 6942 base = 0;
6943
6944 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6945 y = -y;
6946 }
6947 pos |= y << CURSOR_Y_SHIFT;
6948
6949 visible = base != 0;
560b85bb 6950 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6951 return;
6952
0cd83aa9 6953 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6954 I915_WRITE(CURPOS_IVB(pipe), pos);
6955 ivb_update_cursor(crtc, base);
6956 } else {
6957 I915_WRITE(CURPOS(pipe), pos);
6958 if (IS_845G(dev) || IS_I865G(dev))
6959 i845_update_cursor(crtc, base);
6960 else
6961 i9xx_update_cursor(crtc, base);
6962 }
cda4b7d3
CW		 6963}
6964
79e53945 6965static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6966 struct drm_file *file,
79e53945
JB		 6967 uint32_t handle,
6968 uint32_t width, uint32_t height)
6969{
6970 struct drm_device *dev = crtc->dev;
6971 struct drm_i915_private *dev_priv = dev->dev_private;
6972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6973 struct drm_i915_gem_object *obj;
cda4b7d3 6974 uint32_t addr;
3f8bc370 6975 int ret;
79e53945 6976
79e53945
JB		 6977 /* if we want to turn off the cursor ignore width and height */
6978 if (!handle) {
28c97730 6979 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6980 addr = 0;
05394f39 6981 obj = NULL;
5004417d 6982 mutex_lock(&dev->struct_mutex);
3f8bc370 6983 goto finish;
79e53945
JB		 6984 }
6985
6986 /* Currently we only support 64x64 cursors */
6987 if (width != 64 || height != 64) {
6988 DRM_ERROR("we currently only support 64x64 cursors\n");
6989 return -EINVAL;
6990 }
6991
05394f39 6992 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6993 if (&obj->base == NULL)
79e53945
JB		 6994 return -ENOENT;
6995
05394f39 6996 if (obj->base.size < width * height * 4) {
79e53945 6997 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6998 ret = -ENOMEM;
6999 goto fail;
79e53945
JB		 7000 }
7001
71acb5eb 7002 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 7003 mutex_lock(&dev->struct_mutex);
b295d1b6 7004 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 7005 unsigned alignment;
7006
d9e86c0e
CW		 7007 if (obj->tiling_mode) {
7008 DRM_ERROR("cursor cannot be tiled\n");
7009 ret = -EINVAL;
7010 goto fail_locked;
7011 }
7012
693db184
CW		 7013 /* Note that the w/a also requires 2 PTE of padding following
7014 * the bo. We currently fill all unused PTE with the shadow
7015 * page and so we should always have valid PTE following the
7016 * cursor preventing the VT-d warning.
7017 */
7018 alignment = 0;
7019 if (need_vtd_wa(dev))
7020 alignment = 64*1024;
7021
7022 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 7023 if (ret) {
7024 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 7025 goto fail_locked;
e7b526bb
CW		 7026 }
7027
d9e86c0e
CW		 7028 ret = i915_gem_object_put_fence(obj);
7029 if (ret) {
2da3b9b9 7030 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 7031 goto fail_unpin;
7032 }
7033
f343c5f6 7034 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 7035 } else {
6eeefaf3 7036 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 7037 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 7038 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7039 align);
71acb5eb
DA		 7040 if (ret) {
7041 DRM_ERROR("failed to attach phys object\n");
7f9872e0 7042 goto fail_locked;
71acb5eb 7043 }
05394f39 7044 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 7045 }
7046
a6c45cf0 7047 if (IS_GEN2(dev))
14b60391
JB		 7048 I915_WRITE(CURSIZE, (height << 12) | width);
7049
3f8bc370 7050 finish:
3f8bc370 7051 if (intel_crtc->cursor_bo) {
b295d1b6 7052 if (dev_priv->info->cursor_needs_physical) {
05394f39 7053 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 7054 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7055 } else
cc98b413 7056 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 7057 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 7058 }
80824003 7059
7f9872e0 7060 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 7061
7062 intel_crtc->cursor_addr = addr;
05394f39 7063 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 7064 intel_crtc->cursor_width = width;
7065 intel_crtc->cursor_height = height;
7066
40ccc72b 7067 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 7068
79e53945 7069 return 0;
e7b526bb 7070fail_unpin:
cc98b413 7071 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 7072fail_locked:
34b8686e 7073 mutex_unlock(&dev->struct_mutex);
bc9025bd 7074fail:
05394f39 7075 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 7076 return ret;
79e53945
JB		 7077}
7078
7079static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7080{
79e53945 7081 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7082
cda4b7d3
CW		 7083 intel_crtc->cursor_x = x;
7084 intel_crtc->cursor_y = y;
652c393a 7085
40ccc72b 7086 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 7087
7088 return 0;
7089}
7090
7091/** Sets the color ramps on behalf of RandR */
7092void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
7093 u16 blue, int regno)
7094{
7095 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7096
7097 intel_crtc->lut_r[regno] = red >> 8;
7098 intel_crtc->lut_g[regno] = green >> 8;
7099 intel_crtc->lut_b[regno] = blue >> 8;
7100}
7101
b8c00ac5
DA		 7102void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
7103 u16 *blue, int regno)
7104{
7105 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7106
7107 *red = intel_crtc->lut_r[regno] << 8;
7108 *green = intel_crtc->lut_g[regno] << 8;
7109 *blue = intel_crtc->lut_b[regno] << 8;
7110}
7111
79e53945 7112static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7113 u16 *blue, uint32_t start, uint32_t size)
79e53945 7114{
7203425a 7115 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7117
7203425a 7118 for (i = start; i < end; i++) {
79e53945
JB		 7119 intel_crtc->lut_r[i] = red[i] >> 8;
7120 intel_crtc->lut_g[i] = green[i] >> 8;
7121 intel_crtc->lut_b[i] = blue[i] >> 8;
7122 }
7123
7124 intel_crtc_load_lut(crtc);
7125}
7126
79e53945
JB		 7127/* VESA 640x480x72Hz mode to set on the pipe */
7128static struct drm_display_mode load_detect_mode = {
7129 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7130 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7131};
7132
d2dff872
CW		 7133static struct drm_framebuffer *
7134intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7135 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7136 struct drm_i915_gem_object *obj)
7137{
7138 struct intel_framebuffer *intel_fb;
7139 int ret;
7140
7141 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7142 if (!intel_fb) {
7143 drm_gem_object_unreference_unlocked(&obj->base);
7144 return ERR_PTR(-ENOMEM);
7145 }
7146
7147 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7148 if (ret) {
7149 drm_gem_object_unreference_unlocked(&obj->base);
7150 kfree(intel_fb);
7151 return ERR_PTR(ret);
7152 }
7153
7154 return &intel_fb->base;
7155}
7156
7157static u32
7158intel_framebuffer_pitch_for_width(int width, int bpp)
7159{
7160 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7161 return ALIGN(pitch, 64);
7162}
7163
7164static u32
7165intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7166{
7167 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7168 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7169}
7170
7171static struct drm_framebuffer *
7172intel_framebuffer_create_for_mode(struct drm_device *dev,
7173 struct drm_display_mode *mode,
7174 int depth, int bpp)
7175{
7176 struct drm_i915_gem_object *obj;
0fed39bd 7177 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7178
7179 obj = i915_gem_alloc_object(dev,
7180 intel_framebuffer_size_for_mode(mode, bpp));
7181 if (obj == NULL)
7182 return ERR_PTR(-ENOMEM);
7183
7184 mode_cmd.width = mode->hdisplay;
7185 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7186 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7187 bpp);
5ca0c34a 7188 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7189
7190 return intel_framebuffer_create(dev, &mode_cmd, obj);
7191}
7192
7193static struct drm_framebuffer *
7194mode_fits_in_fbdev(struct drm_device *dev,
7195 struct drm_display_mode *mode)
7196{
7197 struct drm_i915_private *dev_priv = dev->dev_private;
7198 struct drm_i915_gem_object *obj;
7199 struct drm_framebuffer *fb;
7200
7201 if (dev_priv->fbdev == NULL)
7202 return NULL;
7203
7204 obj = dev_priv->fbdev->ifb.obj;
7205 if (obj == NULL)
7206 return NULL;
7207
7208 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7209 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7210 fb->bits_per_pixel))
d2dff872
CW		 7211 return NULL;
7212
01f2c773 7213 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7214 return NULL;
7215
7216 return fb;
7217}
7218
d2434ab7 7219bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7220 struct drm_display_mode *mode,
8261b191 7221 struct intel_load_detect_pipe *old)
79e53945
JB		 7222{
7223 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7224 struct intel_encoder *intel_encoder =
7225 intel_attached_encoder(connector);
79e53945 7226 struct drm_crtc *possible_crtc;
4ef69c7a 7227 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7228 struct drm_crtc *crtc = NULL;
7229 struct drm_device *dev = encoder->dev;
94352cf9 7230 struct drm_framebuffer *fb;
79e53945
JB		 7231 int i = -1;
7232
d2dff872
CW		 7233 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7234 connector->base.id, drm_get_connector_name(connector),
7235 encoder->base.id, drm_get_encoder_name(encoder));
7236
79e53945
JB		 7237 /*
7238 * Algorithm gets a little messy:
7a5e4805 7239 *
79e53945
JB		 7240 * - if the connector already has an assigned crtc, use it (but make
7241 * sure it's on first)
7a5e4805 7242 *
79e53945
JB		 7243 * - try to find the first unused crtc that can drive this connector,
7244 * and use that if we find one
79e53945
JB		 7245 */
7246
7247 /* See if we already have a CRTC for this connector */
7248 if (encoder->crtc) {
7249 crtc = encoder->crtc;
8261b191 7250
7b24056b
DV		 7251 mutex_lock(&crtc->mutex);
7252
24218aac 7253 old->dpms_mode = connector->dpms;
8261b191
CW		 7254 old->load_detect_temp = false;
7255
7256 /* Make sure the crtc and connector are running */
24218aac
DV		 7257 if (connector->dpms != DRM_MODE_DPMS_ON)
7258 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7259
7173188d 7260 return true;
79e53945
JB		 7261 }
7262
7263 /* Find an unused one (if possible) */
7264 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7265 i++;
7266 if (!(encoder->possible_crtcs & (1 << i)))
7267 continue;
7268 if (!possible_crtc->enabled) {
7269 crtc = possible_crtc;
7270 break;
7271 }
79e53945
JB		 7272 }
7273
7274 /*
7275 * If we didn't find an unused CRTC, don't use any.
7276 */
7277 if (!crtc) {
7173188d
CW		 7278 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7279 return false;
79e53945
JB		 7280 }
7281
7b24056b 7282 mutex_lock(&crtc->mutex);
fc303101
DV		 7283 intel_encoder->new_crtc = to_intel_crtc(crtc);
7284 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7285
7286 intel_crtc = to_intel_crtc(crtc);
24218aac 7287 old->dpms_mode = connector->dpms;
8261b191 7288 old->load_detect_temp = true;
d2dff872 7289 old->release_fb = NULL;
79e53945 7290
6492711d
CW		 7291 if (!mode)
7292 mode = &load_detect_mode;
79e53945 7293
d2dff872
CW		 7294 /* We need a framebuffer large enough to accommodate all accesses
7295 * that the plane may generate whilst we perform load detection.
7296 * We can not rely on the fbcon either being present (we get called
7297 * during its initialisation to detect all boot displays, or it may
7298 * not even exist) or that it is large enough to satisfy the
7299 * requested mode.
7300 */
94352cf9
DV		 7301 fb = mode_fits_in_fbdev(dev, mode);
7302 if (fb == NULL) {
d2dff872 7303 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7304 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7305 old->release_fb = fb;
d2dff872
CW		 7306 } else
7307 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7308 if (IS_ERR(fb)) {
d2dff872 7309 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7310 mutex_unlock(&crtc->mutex);
0e8b3d3e 7311 return false;
79e53945 7312 }
79e53945 7313
c0c36b94 7314 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7315 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7316 if (old->release_fb)
7317 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7318 mutex_unlock(&crtc->mutex);
0e8b3d3e 7319 return false;
79e53945 7320 }
7173188d 7321
79e53945 7322 /* let the connector get through one full cycle before testing */
9d0498a2 7323 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7324 return true;
79e53945
JB		 7325}
7326
d2434ab7 7327void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7328 struct intel_load_detect_pipe *old)
79e53945 7329{
d2434ab7
DV		 7330 struct intel_encoder *intel_encoder =
7331 intel_attached_encoder(connector);
4ef69c7a 7332 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7333 struct drm_crtc *crtc = encoder->crtc;
79e53945 7334
d2dff872
CW		 7335 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7336 connector->base.id, drm_get_connector_name(connector),
7337 encoder->base.id, drm_get_encoder_name(encoder));
7338
8261b191 7339 if (old->load_detect_temp) {
fc303101
DV		 7340 to_intel_connector(connector)->new_encoder = NULL;
7341 intel_encoder->new_crtc = NULL;
7342 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7343
36206361
DV		 7344 if (old->release_fb) {
7345 drm_framebuffer_unregister_private(old->release_fb);
7346 drm_framebuffer_unreference(old->release_fb);
7347 }
d2dff872 7348
67c96400 7349 mutex_unlock(&crtc->mutex);
0622a53c 7350 return;
79e53945
JB		 7351 }
7352
c751ce4f 7353 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7354 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7355 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7356
7357 mutex_unlock(&crtc->mutex);
79e53945
JB		 7358}
7359
da4a1efa
VS		 7360static int i9xx_pll_refclk(struct drm_device *dev,
7361 const struct intel_crtc_config *pipe_config)
7362{
7363 struct drm_i915_private *dev_priv = dev->dev_private;
7364 u32 dpll = pipe_config->dpll_hw_state.dpll;
7365
7366 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7367 return dev_priv->vbt.lvds_ssc_freq * 1000;
7368 else if (HAS_PCH_SPLIT(dev))
7369 return 120000;
7370 else if (!IS_GEN2(dev))
7371 return 96000;
7372 else
7373 return 48000;
7374}
7375
79e53945 7376/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7377static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7378 struct intel_crtc_config *pipe_config)
79e53945 7379{
f1f644dc 7380 struct drm_device *dev = crtc->base.dev;
79e53945 7381 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7382 int pipe = pipe_config->cpu_transcoder;
293623f7 7383 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 7384 u32 fp;
7385 intel_clock_t clock;
da4a1efa 7386 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 7387
7388 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 7389 fp = pipe_config->dpll_hw_state.fp0;
79e53945 7390 else
293623f7 7391 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 7392
7393 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7394 if (IS_PINEVIEW(dev)) {
7395 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7396 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7397 } else {
7398 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7399 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7400 }
7401
a6c45cf0 7402 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7403 if (IS_PINEVIEW(dev))
7404 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7405 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7406 else
7407 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7408 DPLL_FPA01_P1_POST_DIV_SHIFT);
7409
7410 switch (dpll & DPLL_MODE_MASK) {
7411 case DPLLB_MODE_DAC_SERIAL:
7412 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7413 5 : 10;
7414 break;
7415 case DPLLB_MODE_LVDS:
7416 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7417 7 : 14;
7418 break;
7419 default:
28c97730 7420 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7421 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 7422 return;
79e53945
JB		 7423 }
7424
ac58c3f0 7425 if (IS_PINEVIEW(dev))
da4a1efa 7426 pineview_clock(refclk, &clock);
ac58c3f0 7427 else
da4a1efa 7428 i9xx_clock(refclk, &clock);
79e53945
JB		 7429 } else {
7430 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7431
7432 if (is_lvds) {
7433 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7434 DPLL_FPA01_P1_POST_DIV_SHIFT);
7435 clock.p2 = 14;
79e53945
JB		 7436 } else {
7437 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7438 clock.p1 = 2;
7439 else {
7440 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7441 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7442 }
7443 if (dpll & PLL_P2_DIVIDE_BY_4)
7444 clock.p2 = 4;
7445 else
7446 clock.p2 = 2;
79e53945 7447 }
da4a1efa
VS		 7448
7449 i9xx_clock(refclk, &clock);
79e53945
JB		 7450 }
7451
18442d08
VS		 7452 /*
7453 * This value includes pixel_multiplier. We will use
7454 * port_clock to compute adjusted_mode.clock in the
7455 * encoder's get_config() function.
7456 */
7457 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 7458}
7459
6878da05
VS		 7460int intel_dotclock_calculate(int link_freq,
7461 const struct intel_link_m_n *m_n)
f1f644dc 7462{
f1f644dc
JB		 7463 /*
7464 * The calculation for the data clock is:
1041a02f 7465 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 7466 * But we want to avoid losing precison if possible, so:
1041a02f 7467 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 7468 *
7469 * and the link clock is simpler:
1041a02f 7470 * link_clock = (m * link_clock) / n
f1f644dc
JB		 7471 */
7472
6878da05
VS		 7473 if (!m_n->link_n)
7474 return 0;
7475
7476 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7477}
7478
18442d08
VS		 7479static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7480 struct intel_crtc_config *pipe_config)
6878da05
VS		 7481{
7482 struct drm_device *dev = crtc->base.dev;
18442d08
VS		 7483
7484 /* read out port_clock from the DPLL */
7485 i9xx_crtc_clock_get(crtc, pipe_config);
6878da05 7486
f1f644dc 7487 /*
18442d08
VS		 7488 * This value does not include pixel_multiplier.
7489 * We will check that port_clock and adjusted_mode.clock
7490 * agree once we know their relationship in the encoder's
7491 * get_config() function.
79e53945 7492 */
18442d08
VS		 7493 pipe_config->adjusted_mode.clock =
7494 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7495 &pipe_config->fdi_m_n);
79e53945
JB		 7496}
7497
7498/** Returns the currently programmed mode of the given pipe. */
7499struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7500 struct drm_crtc *crtc)
7501{
548f245b 7502 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7503 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7504 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7505 struct drm_display_mode *mode;
f1f644dc 7506 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7507 int htot = I915_READ(HTOTAL(cpu_transcoder));
7508 int hsync = I915_READ(HSYNC(cpu_transcoder));
7509 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7510 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 7511 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 7512
7513 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7514 if (!mode)
7515 return NULL;
7516
f1f644dc
JB		 7517 /*
7518 * Construct a pipe_config sufficient for getting the clock info
7519 * back out of crtc_clock_get.
7520 *
7521 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7522 * to use a real value here instead.
7523 */
293623f7 7524 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 7525 pipe_config.pixel_multiplier = 1;
293623f7
VS		 7526 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7527 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7528 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 7529 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7530
7531 mode->clock = pipe_config.adjusted_mode.clock;
79e53945
JB		 7532 mode->hdisplay = (htot & 0xffff) + 1;
7533 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7534 mode->hsync_start = (hsync & 0xffff) + 1;
7535 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7536 mode->vdisplay = (vtot & 0xffff) + 1;
7537 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7538 mode->vsync_start = (vsync & 0xffff) + 1;
7539 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7540
7541 drm_mode_set_name(mode);
79e53945
JB		 7542
7543 return mode;
7544}
7545
3dec0095 7546static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7547{
7548 struct drm_device *dev = crtc->dev;
7549 drm_i915_private_t *dev_priv = dev->dev_private;
7550 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7551 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7552 int dpll_reg = DPLL(pipe);
7553 int dpll;
652c393a 7554
bad720ff 7555 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7556 return;
7557
7558 if (!dev_priv->lvds_downclock_avail)
7559 return;
7560
dbdc6479 7561 dpll = I915_READ(dpll_reg);
652c393a 7562 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7563 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7564
8ac5a6d5 7565 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7566
7567 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7568 I915_WRITE(dpll_reg, dpll);
9d0498a2 7569 intel_wait_for_vblank(dev, pipe);
dbdc6479 7570
652c393a
JB		 7571 dpll = I915_READ(dpll_reg);
7572 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7573 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7574 }
652c393a
JB		 7575}
7576
7577static void intel_decrease_pllclock(struct drm_crtc *crtc)
7578{
7579 struct drm_device *dev = crtc->dev;
7580 drm_i915_private_t *dev_priv = dev->dev_private;
7581 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7582
bad720ff 7583 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7584 return;
7585
7586 if (!dev_priv->lvds_downclock_avail)
7587 return;
7588
7589 /*
7590 * Since this is called by a timer, we should never get here in
7591 * the manual case.
7592 */
7593 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7594 int pipe = intel_crtc->pipe;
7595 int dpll_reg = DPLL(pipe);
7596 int dpll;
f6e5b160 7597
44d98a61 7598 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7599
8ac5a6d5 7600 assert_panel_unlocked(dev_priv, pipe);
652c393a 7601
dc257cf1 7602 dpll = I915_READ(dpll_reg);
652c393a
JB		 7603 dpll |= DISPLAY_RATE_SELECT_FPA1;
7604 I915_WRITE(dpll_reg, dpll);
9d0498a2 7605 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7606 dpll = I915_READ(dpll_reg);
7607 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7608 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7609 }
7610
7611}
7612
f047e395
CW		 7613void intel_mark_busy(struct drm_device *dev)
7614{
c67a470b
PZ		 7615 struct drm_i915_private *dev_priv = dev->dev_private;
7616
7617 hsw_package_c8_gpu_busy(dev_priv);
7618 i915_update_gfx_val(dev_priv);
f047e395
CW		 7619}
7620
7621void intel_mark_idle(struct drm_device *dev)
652c393a 7622{
c67a470b 7623 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7624 struct drm_crtc *crtc;
652c393a 7625
c67a470b
PZ		 7626 hsw_package_c8_gpu_idle(dev_priv);
7627
652c393a
JB		 7628 if (!i915_powersave)
7629 return;
7630
652c393a 7631 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7632 if (!crtc->fb)
7633 continue;
7634
725a5b54 7635 intel_decrease_pllclock(crtc);
652c393a 7636 }
652c393a
JB		 7637}
7638
c65355bb
CW		 7639void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7640 struct intel_ring_buffer *ring)
652c393a 7641{
f047e395
CW		 7642 struct drm_device *dev = obj->base.dev;
7643 struct drm_crtc *crtc;
652c393a 7644
f047e395 7645 if (!i915_powersave)
acb87dfb
CW		 7646 return;
7647
652c393a
JB		 7648 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7649 if (!crtc->fb)
7650 continue;
7651
c65355bb
CW		 7652 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7653 continue;
7654
7655 intel_increase_pllclock(crtc);
7656 if (ring && intel_fbc_enabled(dev))
7657 ring->fbc_dirty = true;
652c393a
JB		 7658 }
7659}
7660
79e53945
JB		 7661static void intel_crtc_destroy(struct drm_crtc *crtc)
7662{
7663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7664 struct drm_device *dev = crtc->dev;
7665 struct intel_unpin_work *work;
7666 unsigned long flags;
7667
7668 spin_lock_irqsave(&dev->event_lock, flags);
7669 work = intel_crtc->unpin_work;
7670 intel_crtc->unpin_work = NULL;
7671 spin_unlock_irqrestore(&dev->event_lock, flags);
7672
7673 if (work) {
7674 cancel_work_sync(&work->work);
7675 kfree(work);
7676 }
79e53945 7677
40ccc72b
MK		 7678 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7679
79e53945 7680 drm_crtc_cleanup(crtc);
67e77c5a 7681
79e53945
JB		 7682 kfree(intel_crtc);
7683}
7684
6b95a207
KH		 7685static void intel_unpin_work_fn(struct work_struct *__work)
7686{
7687 struct intel_unpin_work *work =
7688 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7689 struct drm_device *dev = work->crtc->dev;
6b95a207 7690
b4a98e57 7691 mutex_lock(&dev->struct_mutex);
1690e1eb 7692 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7693 drm_gem_object_unreference(&work->pending_flip_obj->base);
7694 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7695
b4a98e57
CW		 7696 intel_update_fbc(dev);
7697 mutex_unlock(&dev->struct_mutex);
7698
7699 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7700 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7701
6b95a207
KH		 7702 kfree(work);
7703}
7704
1afe3e9d 7705static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7706 struct drm_crtc *crtc)
6b95a207
KH		 7707{
7708 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7709 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7710 struct intel_unpin_work *work;
6b95a207
KH		 7711 unsigned long flags;
7712
7713 /* Ignore early vblank irqs */
7714 if (intel_crtc == NULL)
7715 return;
7716
7717 spin_lock_irqsave(&dev->event_lock, flags);
7718 work = intel_crtc->unpin_work;
e7d841ca
CW		 7719
7720 /* Ensure we don't miss a work->pending update ... */
7721 smp_rmb();
7722
7723 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7724 spin_unlock_irqrestore(&dev->event_lock, flags);
7725 return;
7726 }
7727
e7d841ca
CW		 7728 /* and that the unpin work is consistent wrt ->pending. */
7729 smp_rmb();
7730
6b95a207 7731 intel_crtc->unpin_work = NULL;
6b95a207 7732
45a066eb
RC		 7733 if (work->event)
7734 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7735
0af7e4df
MK		 7736 drm_vblank_put(dev, intel_crtc->pipe);
7737
6b95a207
KH		 7738 spin_unlock_irqrestore(&dev->event_lock, flags);
7739
2c10d571 7740 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7741
7742 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7743
7744 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7745}
7746
1afe3e9d
JB		 7747void intel_finish_page_flip(struct drm_device *dev, int pipe)
7748{
7749 drm_i915_private_t *dev_priv = dev->dev_private;
7750 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7751
49b14a5c 7752 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7753}
7754
7755void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7756{
7757 drm_i915_private_t *dev_priv = dev->dev_private;
7758 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7759
49b14a5c 7760 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7761}
7762
6b95a207
KH		 7763void intel_prepare_page_flip(struct drm_device *dev, int plane)
7764{
7765 drm_i915_private_t *dev_priv = dev->dev_private;
7766 struct intel_crtc *intel_crtc =
7767 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7768 unsigned long flags;
7769
e7d841ca
CW		 7770 /* NB: An MMIO update of the plane base pointer will also
7771 * generate a page-flip completion irq, i.e. every modeset
7772 * is also accompanied by a spurious intel_prepare_page_flip().
7773 */
6b95a207 7774 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7775 if (intel_crtc->unpin_work)
7776 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7777 spin_unlock_irqrestore(&dev->event_lock, flags);
7778}
7779
e7d841ca
CW		 7780inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7781{
7782 /* Ensure that the work item is consistent when activating it ... */
7783 smp_wmb();
7784 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7785 /* and that it is marked active as soon as the irq could fire. */
7786 smp_wmb();
7787}
7788
8c9f3aaf
JB		 7789static int intel_gen2_queue_flip(struct drm_device *dev,
7790 struct drm_crtc *crtc,
7791 struct drm_framebuffer *fb,
ed8d1975
KP		 7792 struct drm_i915_gem_object *obj,
7793 uint32_t flags)
8c9f3aaf
JB		 7794{
7795 struct drm_i915_private *dev_priv = dev->dev_private;
7796 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7797 u32 flip_mask;
6d90c952 7798 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7799 int ret;
7800
6d90c952 7801 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7802 if (ret)
83d4092b 7803 goto err;
8c9f3aaf 7804
6d90c952 7805 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7806 if (ret)
83d4092b 7807 goto err_unpin;
8c9f3aaf
JB		 7808
7809 /* Can't queue multiple flips, so wait for the previous
7810 * one to finish before executing the next.
7811 */
7812 if (intel_crtc->plane)
7813 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7814 else
7815 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7816 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7817 intel_ring_emit(ring, MI_NOOP);
7818 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7819 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7820 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7821 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7822 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7823
7824 intel_mark_page_flip_active(intel_crtc);
09246732 7825 __intel_ring_advance(ring);
83d4092b
CW		 7826 return 0;
7827
7828err_unpin:
7829 intel_unpin_fb_obj(obj);
7830err:
8c9f3aaf
JB		 7831 return ret;
7832}
7833
7834static int intel_gen3_queue_flip(struct drm_device *dev,
7835 struct drm_crtc *crtc,
7836 struct drm_framebuffer *fb,
ed8d1975
KP		 7837 struct drm_i915_gem_object *obj,
7838 uint32_t flags)
8c9f3aaf
JB		 7839{
7840 struct drm_i915_private *dev_priv = dev->dev_private;
7841 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7842 u32 flip_mask;
6d90c952 7843 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7844 int ret;
7845
6d90c952 7846 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7847 if (ret)
83d4092b 7848 goto err;
8c9f3aaf 7849
6d90c952 7850 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7851 if (ret)
83d4092b 7852 goto err_unpin;
8c9f3aaf
JB		 7853
7854 if (intel_crtc->plane)
7855 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7856 else
7857 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7858 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7859 intel_ring_emit(ring, MI_NOOP);
7860 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7861 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7862 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7863 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7864 intel_ring_emit(ring, MI_NOOP);
7865
e7d841ca 7866 intel_mark_page_flip_active(intel_crtc);
09246732 7867 __intel_ring_advance(ring);
83d4092b
CW		 7868 return 0;
7869
7870err_unpin:
7871 intel_unpin_fb_obj(obj);
7872err:
8c9f3aaf
JB		 7873 return ret;
7874}
7875
7876static int intel_gen4_queue_flip(struct drm_device *dev,
7877 struct drm_crtc *crtc,
7878 struct drm_framebuffer *fb,
ed8d1975
KP		 7879 struct drm_i915_gem_object *obj,
7880 uint32_t flags)
8c9f3aaf
JB		 7881{
7882 struct drm_i915_private *dev_priv = dev->dev_private;
7883 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7884 uint32_t pf, pipesrc;
6d90c952 7885 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7886 int ret;
7887
6d90c952 7888 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7889 if (ret)
83d4092b 7890 goto err;
8c9f3aaf 7891
6d90c952 7892 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7893 if (ret)
83d4092b 7894 goto err_unpin;
8c9f3aaf
JB		 7895
7896 /* i965+ uses the linear or tiled offsets from the
7897 * Display Registers (which do not change across a page-flip)
7898 * so we need only reprogram the base address.
7899 */
6d90c952
DV		 7900 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7901 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7902 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 7903 intel_ring_emit(ring,
f343c5f6 7904 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 7905 obj->tiling_mode);
8c9f3aaf
JB		 7906
7907 /* XXX Enabling the panel-fitter across page-flip is so far
7908 * untested on non-native modes, so ignore it for now.
7909 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7910 */
7911 pf = 0;
7912 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7913 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7914
7915 intel_mark_page_flip_active(intel_crtc);
09246732 7916 __intel_ring_advance(ring);
83d4092b
CW		 7917 return 0;
7918
7919err_unpin:
7920 intel_unpin_fb_obj(obj);
7921err:
8c9f3aaf
JB		 7922 return ret;
7923}
7924
7925static int intel_gen6_queue_flip(struct drm_device *dev,
7926 struct drm_crtc *crtc,
7927 struct drm_framebuffer *fb,
ed8d1975
KP		 7928 struct drm_i915_gem_object *obj,
7929 uint32_t flags)
8c9f3aaf
JB		 7930{
7931 struct drm_i915_private *dev_priv = dev->dev_private;
7932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7933 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7934 uint32_t pf, pipesrc;
7935 int ret;
7936
6d90c952 7937 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7938 if (ret)
83d4092b 7939 goto err;
8c9f3aaf 7940
6d90c952 7941 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7942 if (ret)
83d4092b 7943 goto err_unpin;
8c9f3aaf 7944
6d90c952
DV		 7945 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7946 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7947 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 7948 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 7949
dc257cf1
DV		 7950 /* Contrary to the suggestions in the documentation,
7951 * "Enable Panel Fitter" does not seem to be required when page
7952 * flipping with a non-native mode, and worse causes a normal
7953 * modeset to fail.
7954 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7955 */
7956 pf = 0;
8c9f3aaf 7957 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7958 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7959
7960 intel_mark_page_flip_active(intel_crtc);
09246732 7961 __intel_ring_advance(ring);
83d4092b
CW		 7962 return 0;
7963
7964err_unpin:
7965 intel_unpin_fb_obj(obj);
7966err:
8c9f3aaf
JB		 7967 return ret;
7968}
7969
7c9017e5
JB		 7970static int intel_gen7_queue_flip(struct drm_device *dev,
7971 struct drm_crtc *crtc,
7972 struct drm_framebuffer *fb,
ed8d1975
KP		 7973 struct drm_i915_gem_object *obj,
7974 uint32_t flags)
7c9017e5
JB		 7975{
7976 struct drm_i915_private *dev_priv = dev->dev_private;
7977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 7978 struct intel_ring_buffer *ring;
cb05d8de 7979 uint32_t plane_bit = 0;
ffe74d75
CW		 7980 int len, ret;
7981
7982 ring = obj->ring;
7983 if (ring == NULL || ring->id != RCS)
7984 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 7985
7986 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7987 if (ret)
83d4092b 7988 goto err;
7c9017e5 7989
cb05d8de
DV		 7990 switch(intel_crtc->plane) {
7991 case PLANE_A:
7992 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7993 break;
7994 case PLANE_B:
7995 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7996 break;
7997 case PLANE_C:
7998 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7999 break;
8000 default:
8001 WARN_ONCE(1, "unknown plane in flip command\n");
8002 ret = -ENODEV;
ab3951eb 8003 goto err_unpin;
cb05d8de
DV		 8004 }
8005
ffe74d75
CW		 8006 len = 4;
8007 if (ring->id == RCS)
8008 len += 6;
8009
8010 ret = intel_ring_begin(ring, len);
7c9017e5 8011 if (ret)
83d4092b 8012 goto err_unpin;
7c9017e5 8013
ffe74d75
CW		 8014 /* Unmask the flip-done completion message. Note that the bspec says that
8015 * we should do this for both the BCS and RCS, and that we must not unmask
8016 * more than one flip event at any time (or ensure that one flip message
8017 * can be sent by waiting for flip-done prior to queueing new flips).
8018 * Experimentation says that BCS works despite DERRMR masking all
8019 * flip-done completion events and that unmasking all planes at once
8020 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8021 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8022 */
8023 if (ring->id == RCS) {
8024 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8025 intel_ring_emit(ring, DERRMR);
8026 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8027 DERRMR_PIPEB_PRI_FLIP_DONE |
8028 DERRMR_PIPEC_PRI_FLIP_DONE));
8029 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8030 intel_ring_emit(ring, DERRMR);
8031 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8032 }
8033
cb05d8de 8034 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 8035 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 8036 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 8037 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 8038
8039 intel_mark_page_flip_active(intel_crtc);
09246732 8040 __intel_ring_advance(ring);
83d4092b
CW		 8041 return 0;
8042
8043err_unpin:
8044 intel_unpin_fb_obj(obj);
8045err:
7c9017e5
JB		 8046 return ret;
8047}
8048
8c9f3aaf
JB		 8049static int intel_default_queue_flip(struct drm_device *dev,
8050 struct drm_crtc *crtc,
8051 struct drm_framebuffer *fb,
ed8d1975
KP		 8052 struct drm_i915_gem_object *obj,
8053 uint32_t flags)
8c9f3aaf
JB		 8054{
8055 return -ENODEV;
8056}
8057
6b95a207
KH		 8058static int intel_crtc_page_flip(struct drm_crtc *crtc,
8059 struct drm_framebuffer *fb,
ed8d1975
KP		 8060 struct drm_pending_vblank_event *event,
8061 uint32_t page_flip_flags)
6b95a207
KH		 8062{
8063 struct drm_device *dev = crtc->dev;
8064 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 8065 struct drm_framebuffer *old_fb = crtc->fb;
8066 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 8067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8068 struct intel_unpin_work *work;
8c9f3aaf 8069 unsigned long flags;
52e68630 8070 int ret;
6b95a207 8071
e6a595d2
VS		 8072 /* Can't change pixel format via MI display flips. */
8073 if (fb->pixel_format != crtc->fb->pixel_format)
8074 return -EINVAL;
8075
8076 /*
8077 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8078 * Note that pitch changes could also affect these register.
8079 */
8080 if (INTEL_INFO(dev)->gen > 3 &&
8081 (fb->offsets[0] != crtc->fb->offsets[0] ||
8082 fb->pitches[0] != crtc->fb->pitches[0]))
8083 return -EINVAL;
8084
6b95a207
KH		 8085 work = kzalloc(sizeof *work, GFP_KERNEL);
8086 if (work == NULL)
8087 return -ENOMEM;
8088
6b95a207 8089 work->event = event;
b4a98e57 8090 work->crtc = crtc;
4a35f83b 8091 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 8092 INIT_WORK(&work->work, intel_unpin_work_fn);
8093
7317c75e
JB		 8094 ret = drm_vblank_get(dev, intel_crtc->pipe);
8095 if (ret)
8096 goto free_work;
8097
6b95a207
KH		 8098 /* We borrow the event spin lock for protecting unpin_work */
8099 spin_lock_irqsave(&dev->event_lock, flags);
8100 if (intel_crtc->unpin_work) {
8101 spin_unlock_irqrestore(&dev->event_lock, flags);
8102 kfree(work);
7317c75e 8103 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 8104
8105 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 8106 return -EBUSY;
8107 }
8108 intel_crtc->unpin_work = work;
8109 spin_unlock_irqrestore(&dev->event_lock, flags);
8110
b4a98e57
CW		 8111 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8112 flush_workqueue(dev_priv->wq);
8113
79158103
CW		 8114 ret = i915_mutex_lock_interruptible(dev);
8115 if (ret)
8116 goto cleanup;
6b95a207 8117
75dfca80 8118 /* Reference the objects for the scheduled work. */
05394f39
CW		 8119 drm_gem_object_reference(&work->old_fb_obj->base);
8120 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8121
8122 crtc->fb = fb;
96b099fd 8123
e1f99ce6 8124 work->pending_flip_obj = obj;
e1f99ce6 8125
4e5359cd
SF		 8126 work->enable_stall_check = true;
8127
b4a98e57 8128 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8129 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8130
ed8d1975 8131 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8132 if (ret)
8133 goto cleanup_pending;
6b95a207 8134
7782de3b 8135 intel_disable_fbc(dev);
c65355bb 8136 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8137 mutex_unlock(&dev->struct_mutex);
8138
e5510fac
JB		 8139 trace_i915_flip_request(intel_crtc->plane, obj);
8140
6b95a207 8141 return 0;
96b099fd 8142
8c9f3aaf 8143cleanup_pending:
b4a98e57 8144 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8145 crtc->fb = old_fb;
05394f39
CW		 8146 drm_gem_object_unreference(&work->old_fb_obj->base);
8147 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8148 mutex_unlock(&dev->struct_mutex);
8149
79158103 8150cleanup:
96b099fd
CW		 8151 spin_lock_irqsave(&dev->event_lock, flags);
8152 intel_crtc->unpin_work = NULL;
8153 spin_unlock_irqrestore(&dev->event_lock, flags);
8154
7317c75e
JB		 8155 drm_vblank_put(dev, intel_crtc->pipe);
8156free_work:
96b099fd
CW		 8157 kfree(work);
8158
8159 return ret;
6b95a207
KH		 8160}
8161
f6e5b160 8162static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8163 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8164 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8165};
8166
50f56119
DV		 8167static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8168 struct drm_crtc *crtc)
8169{
8170 struct drm_device *dev;
8171 struct drm_crtc *tmp;
8172 int crtc_mask = 1;
47f1c6c9 8173
50f56119 8174 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8175
50f56119 8176 dev = crtc->dev;
47f1c6c9 8177
50f56119
DV		 8178 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8179 if (tmp == crtc)
8180 break;
8181 crtc_mask <<= 1;
8182 }
47f1c6c9 8183
50f56119
DV		 8184 if (encoder->possible_crtcs & crtc_mask)
8185 return true;
8186 return false;
47f1c6c9 8187}
79e53945 8188
9a935856
DV		 8189/**
8190 * intel_modeset_update_staged_output_state
8191 *
8192 * Updates the staged output configuration state, e.g. after we've read out the
8193 * current hw state.
8194 */
8195static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8196{
9a935856
DV		 8197 struct intel_encoder *encoder;
8198 struct intel_connector *connector;
f6e5b160 8199
9a935856
DV		 8200 list_for_each_entry(connector, &dev->mode_config.connector_list,
8201 base.head) {
8202 connector->new_encoder =
8203 to_intel_encoder(connector->base.encoder);
8204 }
f6e5b160 8205
9a935856
DV		 8206 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8207 base.head) {
8208 encoder->new_crtc =
8209 to_intel_crtc(encoder->base.crtc);
8210 }
f6e5b160
CW		 8211}
8212
9a935856
DV		 8213/**
8214 * intel_modeset_commit_output_state
8215 *
8216 * This function copies the stage display pipe configuration to the real one.
8217 */
8218static void intel_modeset_commit_output_state(struct drm_device *dev)
8219{
8220 struct intel_encoder *encoder;
8221 struct intel_connector *connector;
f6e5b160 8222
9a935856
DV		 8223 list_for_each_entry(connector, &dev->mode_config.connector_list,
8224 base.head) {
8225 connector->base.encoder = &connector->new_encoder->base;
8226 }
f6e5b160 8227
9a935856
DV		 8228 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8229 base.head) {
8230 encoder->base.crtc = &encoder->new_crtc->base;
8231 }
8232}
8233
050f7aeb
DV		 8234static void
8235connected_sink_compute_bpp(struct intel_connector * connector,
8236 struct intel_crtc_config *pipe_config)
8237{
8238 int bpp = pipe_config->pipe_bpp;
8239
8240 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8241 connector->base.base.id,
8242 drm_get_connector_name(&connector->base));
8243
8244 /* Don't use an invalid EDID bpc value */
8245 if (connector->base.display_info.bpc &&
8246 connector->base.display_info.bpc * 3 < bpp) {
8247 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8248 bpp, connector->base.display_info.bpc*3);
8249 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8250 }
8251
8252 /* Clamp bpp to 8 on screens without EDID 1.4 */
8253 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8254 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8255 bpp);
8256 pipe_config->pipe_bpp = 24;
8257 }
8258}
8259
4e53c2e0 8260static int
050f7aeb
DV		 8261compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8262 struct drm_framebuffer *fb,
8263 struct intel_crtc_config *pipe_config)
4e53c2e0 8264{
050f7aeb
DV		 8265 struct drm_device *dev = crtc->base.dev;
8266 struct intel_connector *connector;
4e53c2e0
DV		 8267 int bpp;
8268
d42264b1
DV		 8269 switch (fb->pixel_format) {
8270 case DRM_FORMAT_C8:
4e53c2e0
DV		 8271 bpp = 8*3; /* since we go through a colormap */
8272 break;
d42264b1
DV		 8273 case DRM_FORMAT_XRGB1555:
8274 case DRM_FORMAT_ARGB1555:
8275 /* checked in intel_framebuffer_init already */
8276 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8277 return -EINVAL;
8278 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8279 bpp = 6*3; /* min is 18bpp */
8280 break;
d42264b1
DV		 8281 case DRM_FORMAT_XBGR8888:
8282 case DRM_FORMAT_ABGR8888:
8283 /* checked in intel_framebuffer_init already */
8284 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8285 return -EINVAL;
8286 case DRM_FORMAT_XRGB8888:
8287 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8288 bpp = 8*3;
8289 break;
d42264b1
DV		 8290 case DRM_FORMAT_XRGB2101010:
8291 case DRM_FORMAT_ARGB2101010:
8292 case DRM_FORMAT_XBGR2101010:
8293 case DRM_FORMAT_ABGR2101010:
8294 /* checked in intel_framebuffer_init already */
8295 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8296 return -EINVAL;
4e53c2e0
DV		 8297 bpp = 10*3;
8298 break;
baba133a 8299 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8300 default:
8301 DRM_DEBUG_KMS("unsupported depth\n");
8302 return -EINVAL;
8303 }
8304
4e53c2e0
DV		 8305 pipe_config->pipe_bpp = bpp;
8306
8307 /* Clamp display bpp to EDID value */
8308 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8309 base.head) {
1b829e05
DV		 8310 if (!connector->new_encoder ||
8311 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8312 continue;
8313
050f7aeb 8314 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8315 }
8316
8317 return bpp;
8318}
8319
c0b03411
DV		 8320static void intel_dump_pipe_config(struct intel_crtc *crtc,
8321 struct intel_crtc_config *pipe_config,
8322 const char *context)
8323{
8324 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8325 context, pipe_name(crtc->pipe));
8326
8327 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8328 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8329 pipe_config->pipe_bpp, pipe_config->dither);
8330 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8331 pipe_config->has_pch_encoder,
8332 pipe_config->fdi_lanes,
8333 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8334 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8335 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 8336 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8337 pipe_config->has_dp_encoder,
8338 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8339 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8340 pipe_config->dp_m_n.tu);
c0b03411
DV		 8341 DRM_DEBUG_KMS("requested mode:\n");
8342 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8343 DRM_DEBUG_KMS("adjusted mode:\n");
8344 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
d71b8d4a 8345 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 8346 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8347 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 8348 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8349 pipe_config->gmch_pfit.control,
8350 pipe_config->gmch_pfit.pgm_ratios,
8351 pipe_config->gmch_pfit.lvds_border_bits);
8352 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
8353 pipe_config->pch_pfit.pos,
8354 pipe_config->pch_pfit.size);
42db64ef 8355 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 8356 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
c0b03411
DV		 8357}
8358
accfc0c5
DV		 8359static bool check_encoder_cloning(struct drm_crtc *crtc)
8360{
8361 int num_encoders = 0;
8362 bool uncloneable_encoders = false;
8363 struct intel_encoder *encoder;
8364
8365 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8366 base.head) {
8367 if (&encoder->new_crtc->base != crtc)
8368 continue;
8369
8370 num_encoders++;
8371 if (!encoder->cloneable)
8372 uncloneable_encoders = true;
8373 }
8374
8375 return !(num_encoders > 1 && uncloneable_encoders);
8376}
8377
b8cecdf5
DV		 8378static struct intel_crtc_config *
8379intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8380 struct drm_framebuffer *fb,
b8cecdf5 8381 struct drm_display_mode *mode)
ee7b9f93 8382{
7758a113 8383 struct drm_device *dev = crtc->dev;
7758a113 8384 struct intel_encoder *encoder;
b8cecdf5 8385 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8386 int plane_bpp, ret = -EINVAL;
8387 bool retry = true;
ee7b9f93 8388
accfc0c5
DV		 8389 if (!check_encoder_cloning(crtc)) {
8390 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8391 return ERR_PTR(-EINVAL);
8392 }
8393
b8cecdf5
DV		 8394 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8395 if (!pipe_config)
7758a113
DV		 8396 return ERR_PTR(-ENOMEM);
8397
b8cecdf5
DV		 8398 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8399 drm_mode_copy(&pipe_config->requested_mode, mode);
37327abd
VS		 8400
8401 pipe_config->pipe_src_w = mode->hdisplay;
8402 pipe_config->pipe_src_h = mode->vdisplay;
8403
e143a21c
DV		 8404 pipe_config->cpu_transcoder =
8405 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8406 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8407
2960bc9c
ID		 8408 /*
8409 * Sanitize sync polarity flags based on requested ones. If neither
8410 * positive or negative polarity is requested, treat this as meaning
8411 * negative polarity.
8412 */
8413 if (!(pipe_config->adjusted_mode.flags &
8414 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8415 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8416
8417 if (!(pipe_config->adjusted_mode.flags &
8418 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8419 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8420
050f7aeb
DV		 8421 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8422 * plane pixel format and any sink constraints into account. Returns the
8423 * source plane bpp so that dithering can be selected on mismatches
8424 * after encoders and crtc also have had their say. */
8425 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8426 fb, pipe_config);
4e53c2e0
DV		 8427 if (plane_bpp < 0)
8428 goto fail;
8429
e29c22c0 8430encoder_retry:
ef1b460d 8431 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8432 pipe_config->port_clock = 0;
ef1b460d 8433 pipe_config->pixel_multiplier = 1;
ff9a6750 8434
135c81b8
DV		 8435 /* Fill in default crtc timings, allow encoders to overwrite them. */
8436 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, 0);
8437
7758a113
DV		 8438 /* Pass our mode to the connectors and the CRTC to give them a chance to
8439 * adjust it according to limitations or connector properties, and also
8440 * a chance to reject the mode entirely.
47f1c6c9 8441 */
7758a113
DV		 8442 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8443 base.head) {
47f1c6c9 8444
7758a113
DV		 8445 if (&encoder->new_crtc->base != crtc)
8446 continue;
7ae89233 8447
efea6e8e
DV		 8448 if (!(encoder->compute_config(encoder, pipe_config))) {
8449 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8450 goto fail;
8451 }
ee7b9f93 8452 }
47f1c6c9 8453
ff9a6750
DV		 8454 /* Set default port clock if not overwritten by the encoder. Needs to be
8455 * done afterwards in case the encoder adjusts the mode. */
8456 if (!pipe_config->port_clock)
3c52f4eb
VS		 8457 pipe_config->port_clock = pipe_config->adjusted_mode.clock *
8458 pipe_config->pixel_multiplier;
ff9a6750 8459
a43f6e0f 8460 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8461 if (ret < 0) {
7758a113
DV		 8462 DRM_DEBUG_KMS("CRTC fixup failed\n");
8463 goto fail;
ee7b9f93 8464 }
e29c22c0
DV		 8465
8466 if (ret == RETRY) {
8467 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8468 ret = -EINVAL;
8469 goto fail;
8470 }
8471
8472 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8473 retry = false;
8474 goto encoder_retry;
8475 }
8476
4e53c2e0
DV		 8477 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8478 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8479 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8480
b8cecdf5 8481 return pipe_config;
7758a113 8482fail:
b8cecdf5 8483 kfree(pipe_config);
e29c22c0 8484 return ERR_PTR(ret);
ee7b9f93 8485}
47f1c6c9 8486
e2e1ed41
DV		 8487/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8488 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8489static void
8490intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8491 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8492{
8493 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8494 struct drm_device *dev = crtc->dev;
8495 struct intel_encoder *encoder;
8496 struct intel_connector *connector;
8497 struct drm_crtc *tmp_crtc;
79e53945 8498
e2e1ed41 8499 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8500
e2e1ed41
DV		 8501 /* Check which crtcs have changed outputs connected to them, these need
8502 * to be part of the prepare_pipes mask. We don't (yet) support global
8503 * modeset across multiple crtcs, so modeset_pipes will only have one
8504 * bit set at most. */
8505 list_for_each_entry(connector, &dev->mode_config.connector_list,
8506 base.head) {
8507 if (connector->base.encoder == &connector->new_encoder->base)
8508 continue;
79e53945 8509
e2e1ed41
DV		 8510 if (connector->base.encoder) {
8511 tmp_crtc = connector->base.encoder->crtc;
8512
8513 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8514 }
8515
8516 if (connector->new_encoder)
8517 *prepare_pipes |=
8518 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8519 }
8520
e2e1ed41
DV		 8521 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8522 base.head) {
8523 if (encoder->base.crtc == &encoder->new_crtc->base)
8524 continue;
8525
8526 if (encoder->base.crtc) {
8527 tmp_crtc = encoder->base.crtc;
8528
8529 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8530 }
8531
8532 if (encoder->new_crtc)
8533 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8534 }
8535
e2e1ed41
DV		 8536 /* Check for any pipes that will be fully disabled ... */
8537 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8538 base.head) {
8539 bool used = false;
22fd0fab 8540
e2e1ed41
DV		 8541 /* Don't try to disable disabled crtcs. */
8542 if (!intel_crtc->base.enabled)
8543 continue;
7e7d76c3 8544
e2e1ed41
DV		 8545 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8546 base.head) {
8547 if (encoder->new_crtc == intel_crtc)
8548 used = true;
8549 }
8550
8551 if (!used)
8552 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8553 }
8554
e2e1ed41
DV		 8555
8556 /* set_mode is also used to update properties on life display pipes. */
8557 intel_crtc = to_intel_crtc(crtc);
8558 if (crtc->enabled)
8559 *prepare_pipes |= 1 << intel_crtc->pipe;
8560
b6c5164d
DV		 8561 /*
8562 * For simplicity do a full modeset on any pipe where the output routing
8563 * changed. We could be more clever, but that would require us to be
8564 * more careful with calling the relevant encoder->mode_set functions.
8565 */
e2e1ed41
DV		 8566 if (*prepare_pipes)
8567 *modeset_pipes = *prepare_pipes;
8568
8569 /* ... and mask these out. */
8570 *modeset_pipes &= ~(*disable_pipes);
8571 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8572
8573 /*
8574 * HACK: We don't (yet) fully support global modesets. intel_set_config
8575 * obies this rule, but the modeset restore mode of
8576 * intel_modeset_setup_hw_state does not.
8577 */
8578 *modeset_pipes &= 1 << intel_crtc->pipe;
8579 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8580
8581 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8582 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8583}
79e53945 8584
ea9d758d 8585static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8586{
ea9d758d 8587 struct drm_encoder *encoder;
f6e5b160 8588 struct drm_device *dev = crtc->dev;
f6e5b160 8589
ea9d758d
DV		 8590 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8591 if (encoder->crtc == crtc)
8592 return true;
8593
8594 return false;
8595}
8596
8597static void
8598intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8599{
8600 struct intel_encoder *intel_encoder;
8601 struct intel_crtc *intel_crtc;
8602 struct drm_connector *connector;
8603
8604 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8605 base.head) {
8606 if (!intel_encoder->base.crtc)
8607 continue;
8608
8609 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8610
8611 if (prepare_pipes & (1 << intel_crtc->pipe))
8612 intel_encoder->connectors_active = false;
8613 }
8614
8615 intel_modeset_commit_output_state(dev);
8616
8617 /* Update computed state. */
8618 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8619 base.head) {
8620 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8621 }
8622
8623 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8624 if (!connector->encoder || !connector->encoder->crtc)
8625 continue;
8626
8627 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8628
8629 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8630 struct drm_property *dpms_property =
8631 dev->mode_config.dpms_property;
8632
ea9d758d 8633 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8634 drm_object_property_set_value(&connector->base,
68d34720
DV		 8635 dpms_property,
8636 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8637
8638 intel_encoder = to_intel_encoder(connector->encoder);
8639 intel_encoder->connectors_active = true;
8640 }
8641 }
8642
8643}
8644
3bd26263 8645static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 8646{
3bd26263 8647 int diff;
f1f644dc
JB		 8648
8649 if (clock1 == clock2)
8650 return true;
8651
8652 if (!clock1 || !clock2)
8653 return false;
8654
8655 diff = abs(clock1 - clock2);
8656
8657 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8658 return true;
8659
8660 return false;
8661}
8662
25c5b266
DV		 8663#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8664 list_for_each_entry((intel_crtc), \
8665 &(dev)->mode_config.crtc_list, \
8666 base.head) \
0973f18f 8667 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8668
0e8ffe1b 8669static bool
2fa2fe9a
DV		 8670intel_pipe_config_compare(struct drm_device *dev,
8671 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8672 struct intel_crtc_config *pipe_config)
8673{
66e985c0
DV		 8674#define PIPE_CONF_CHECK_X(name) \
8675 if (current_config->name != pipe_config->name) { \
8676 DRM_ERROR("mismatch in " #name " " \
8677 "(expected 0x%08x, found 0x%08x)\n", \
8678 current_config->name, \
8679 pipe_config->name); \
8680 return false; \
8681 }
8682
08a24034
DV		 8683#define PIPE_CONF_CHECK_I(name) \
8684 if (current_config->name != pipe_config->name) { \
8685 DRM_ERROR("mismatch in " #name " " \
8686 "(expected %i, found %i)\n", \
8687 current_config->name, \
8688 pipe_config->name); \
8689 return false; \
88adfff1
DV		 8690 }
8691
1bd1bd80
DV		 8692#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8693 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8694 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8695 "(expected %i, found %i)\n", \
8696 current_config->name & (mask), \
8697 pipe_config->name & (mask)); \
8698 return false; \
8699 }
8700
5e550656
VS		 8701#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8702 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8703 DRM_ERROR("mismatch in " #name " " \
8704 "(expected %i, found %i)\n", \
8705 current_config->name, \
8706 pipe_config->name); \
8707 return false; \
8708 }
8709
bb760063
DV		 8710#define PIPE_CONF_QUIRK(quirk) \
8711 ((current_config->quirks | pipe_config->quirks) & (quirk))
8712
eccb140b
DV		 8713 PIPE_CONF_CHECK_I(cpu_transcoder);
8714
08a24034
DV		 8715 PIPE_CONF_CHECK_I(has_pch_encoder);
8716 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8717 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8718 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8719 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8720 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8721 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8722
eb14cb74
VS		 8723 PIPE_CONF_CHECK_I(has_dp_encoder);
8724 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8725 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8726 PIPE_CONF_CHECK_I(dp_m_n.link_m);
8727 PIPE_CONF_CHECK_I(dp_m_n.link_n);
8728 PIPE_CONF_CHECK_I(dp_m_n.tu);
8729
1bd1bd80
DV		 8730 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8731 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8732 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8733 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8734 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8735 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8736
8737 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8738 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8739 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8740 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8741 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8742 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8743
c93f54cf 8744 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8745
1bd1bd80
DV		 8746 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8747 DRM_MODE_FLAG_INTERLACE);
8748
bb760063
DV		 8749 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8750 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8751 DRM_MODE_FLAG_PHSYNC);
8752 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8753 DRM_MODE_FLAG_NHSYNC);
8754 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8755 DRM_MODE_FLAG_PVSYNC);
8756 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8757 DRM_MODE_FLAG_NVSYNC);
8758 }
045ac3b5 8759
37327abd
VS		 8760 PIPE_CONF_CHECK_I(pipe_src_w);
8761 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 8762
2fa2fe9a
DV		 8763 PIPE_CONF_CHECK_I(gmch_pfit.control);
8764 /* pfit ratios are autocomputed by the hw on gen4+ */
8765 if (INTEL_INFO(dev)->gen < 4)
8766 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8767 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8768 PIPE_CONF_CHECK_I(pch_pfit.pos);
8769 PIPE_CONF_CHECK_I(pch_pfit.size);
8770
42db64ef
PZ		 8771 PIPE_CONF_CHECK_I(ips_enabled);
8772
282740f7
VS		 8773 PIPE_CONF_CHECK_I(double_wide);
8774
c0d43d62 8775 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8776 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8777 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8778 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8779 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8780
42571aef
VS		 8781 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8782 PIPE_CONF_CHECK_I(pipe_bpp);
8783
d71b8d4a 8784 if (!IS_HASWELL(dev)) {
5e550656 8785 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.clock);
d71b8d4a
VS		 8786 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8787 }
5e550656 8788
66e985c0 8789#undef PIPE_CONF_CHECK_X
08a24034 8790#undef PIPE_CONF_CHECK_I
1bd1bd80 8791#undef PIPE_CONF_CHECK_FLAGS
5e550656 8792#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 8793#undef PIPE_CONF_QUIRK
88adfff1 8794
0e8ffe1b
DV		 8795 return true;
8796}
8797
91d1b4bd
DV		 8798static void
8799check_connector_state(struct drm_device *dev)
8af6cf88 8800{
8af6cf88
DV		 8801 struct intel_connector *connector;
8802
8803 list_for_each_entry(connector, &dev->mode_config.connector_list,
8804 base.head) {
8805 /* This also checks the encoder/connector hw state with the
8806 * ->get_hw_state callbacks. */
8807 intel_connector_check_state(connector);
8808
8809 WARN(&connector->new_encoder->base != connector->base.encoder,
8810 "connector's staged encoder doesn't match current encoder\n");
8811 }
91d1b4bd
DV		 8812}
8813
8814static void
8815check_encoder_state(struct drm_device *dev)
8816{
8817 struct intel_encoder *encoder;
8818 struct intel_connector *connector;
8af6cf88
DV		 8819
8820 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8821 base.head) {
8822 bool enabled = false;
8823 bool active = false;
8824 enum pipe pipe, tracked_pipe;
8825
8826 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8827 encoder->base.base.id,
8828 drm_get_encoder_name(&encoder->base));
8829
8830 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8831 "encoder's stage crtc doesn't match current crtc\n");
8832 WARN(encoder->connectors_active && !encoder->base.crtc,
8833 "encoder's active_connectors set, but no crtc\n");
8834
8835 list_for_each_entry(connector, &dev->mode_config.connector_list,
8836 base.head) {
8837 if (connector->base.encoder != &encoder->base)
8838 continue;
8839 enabled = true;
8840 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8841 active = true;
8842 }
8843 WARN(!!encoder->base.crtc != enabled,
8844 "encoder's enabled state mismatch "
8845 "(expected %i, found %i)\n",
8846 !!encoder->base.crtc, enabled);
8847 WARN(active && !encoder->base.crtc,
8848 "active encoder with no crtc\n");
8849
8850 WARN(encoder->connectors_active != active,
8851 "encoder's computed active state doesn't match tracked active state "
8852 "(expected %i, found %i)\n", active, encoder->connectors_active);
8853
8854 active = encoder->get_hw_state(encoder, &pipe);
8855 WARN(active != encoder->connectors_active,
8856 "encoder's hw state doesn't match sw tracking "
8857 "(expected %i, found %i)\n",
8858 encoder->connectors_active, active);
8859
8860 if (!encoder->base.crtc)
8861 continue;
8862
8863 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8864 WARN(active && pipe != tracked_pipe,
8865 "active encoder's pipe doesn't match"
8866 "(expected %i, found %i)\n",
8867 tracked_pipe, pipe);
8868
8869 }
91d1b4bd
DV		 8870}
8871
8872static void
8873check_crtc_state(struct drm_device *dev)
8874{
8875 drm_i915_private_t *dev_priv = dev->dev_private;
8876 struct intel_crtc *crtc;
8877 struct intel_encoder *encoder;
8878 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8879
8880 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8881 base.head) {
8882 bool enabled = false;
8883 bool active = false;
8884
045ac3b5
JB		 8885 memset(&pipe_config, 0, sizeof(pipe_config));
8886
8af6cf88
DV		 8887 DRM_DEBUG_KMS("[CRTC:%d]\n",
8888 crtc->base.base.id);
8889
8890 WARN(crtc->active && !crtc->base.enabled,
8891 "active crtc, but not enabled in sw tracking\n");
8892
8893 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8894 base.head) {
8895 if (encoder->base.crtc != &crtc->base)
8896 continue;
8897 enabled = true;
8898 if (encoder->connectors_active)
8899 active = true;
8900 }
6c49f241 8901
8af6cf88
DV		 8902 WARN(active != crtc->active,
8903 "crtc's computed active state doesn't match tracked active state "
8904 "(expected %i, found %i)\n", active, crtc->active);
8905 WARN(enabled != crtc->base.enabled,
8906 "crtc's computed enabled state doesn't match tracked enabled state "
8907 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8908
0e8ffe1b
DV		 8909 active = dev_priv->display.get_pipe_config(crtc,
8910 &pipe_config);
d62cf62a
DV		 8911
8912 /* hw state is inconsistent with the pipe A quirk */
8913 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8914 active = crtc->active;
8915
6c49f241
DV		 8916 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8917 base.head) {
3eaba51c 8918 enum pipe pipe;
6c49f241
DV		 8919 if (encoder->base.crtc != &crtc->base)
8920 continue;
3eaba51c
VS		 8921 if (encoder->get_config &&
8922 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 8923 encoder->get_config(encoder, &pipe_config);
8924 }
8925
0e8ffe1b
DV		 8926 WARN(crtc->active != active,
8927 "crtc active state doesn't match with hw state "
8928 "(expected %i, found %i)\n", crtc->active, active);
8929
c0b03411
DV		 8930 if (active &&
8931 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8932 WARN(1, "pipe state doesn't match!\n");
8933 intel_dump_pipe_config(crtc, &pipe_config,
8934 "[hw state]");
8935 intel_dump_pipe_config(crtc, &crtc->config,
8936 "[sw state]");
8937 }
8af6cf88
DV		 8938 }
8939}
8940
91d1b4bd
DV		 8941static void
8942check_shared_dpll_state(struct drm_device *dev)
8943{
8944 drm_i915_private_t *dev_priv = dev->dev_private;
8945 struct intel_crtc *crtc;
8946 struct intel_dpll_hw_state dpll_hw_state;
8947 int i;
5358901f
DV		 8948
8949 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8950 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8951 int enabled_crtcs = 0, active_crtcs = 0;
8952 bool active;
8953
8954 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8955
8956 DRM_DEBUG_KMS("%s\n", pll->name);
8957
8958 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8959
8960 WARN(pll->active > pll->refcount,
8961 "more active pll users than references: %i vs %i\n",
8962 pll->active, pll->refcount);
8963 WARN(pll->active && !pll->on,
8964 "pll in active use but not on in sw tracking\n");
35c95375
DV		 8965 WARN(pll->on && !pll->active,
8966 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 8967 WARN(pll->on != active,
8968 "pll on state mismatch (expected %i, found %i)\n",
8969 pll->on, active);
8970
8971 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8972 base.head) {
8973 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8974 enabled_crtcs++;
8975 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8976 active_crtcs++;
8977 }
8978 WARN(pll->active != active_crtcs,
8979 "pll active crtcs mismatch (expected %i, found %i)\n",
8980 pll->active, active_crtcs);
8981 WARN(pll->refcount != enabled_crtcs,
8982 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8983 pll->refcount, enabled_crtcs);
66e985c0
DV		 8984
8985 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8986 sizeof(dpll_hw_state)),
8987 "pll hw state mismatch\n");
5358901f 8988 }
8af6cf88
DV		 8989}
8990
91d1b4bd
DV		 8991void
8992intel_modeset_check_state(struct drm_device *dev)
8993{
8994 check_connector_state(dev);
8995 check_encoder_state(dev);
8996 check_crtc_state(dev);
8997 check_shared_dpll_state(dev);
8998}
8999
18442d08
VS		 9000void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9001 int dotclock)
9002{
9003 /*
9004 * FDI already provided one idea for the dotclock.
9005 * Yell if the encoder disagrees.
9006 */
9007 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.clock, dotclock),
9008 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
9009 pipe_config->adjusted_mode.clock, dotclock);
9010}
9011
f30da187
DV		 9012static int __intel_set_mode(struct drm_crtc *crtc,
9013 struct drm_display_mode *mode,
9014 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 9015{
9016 struct drm_device *dev = crtc->dev;
dbf2b54e 9017 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 9018 struct drm_display_mode *saved_mode, *saved_hwmode;
9019 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 9020 struct intel_crtc *intel_crtc;
9021 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 9022 int ret = 0;
a6778b3c 9023
3ac18232 9024 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 9025 if (!saved_mode)
9026 return -ENOMEM;
3ac18232 9027 saved_hwmode = saved_mode + 1;
a6778b3c 9028
e2e1ed41 9029 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 9030 &prepare_pipes, &disable_pipes);
9031
3ac18232
TG		 9032 *saved_hwmode = crtc->hwmode;
9033 *saved_mode = crtc->mode;
a6778b3c 9034
25c5b266
DV		 9035 /* Hack: Because we don't (yet) support global modeset on multiple
9036 * crtcs, we don't keep track of the new mode for more than one crtc.
9037 * Hence simply check whether any bit is set in modeset_pipes in all the
9038 * pieces of code that are not yet converted to deal with mutliple crtcs
9039 * changing their mode at the same time. */
25c5b266 9040 if (modeset_pipes) {
4e53c2e0 9041 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 9042 if (IS_ERR(pipe_config)) {
9043 ret = PTR_ERR(pipe_config);
9044 pipe_config = NULL;
9045
3ac18232 9046 goto out;
25c5b266 9047 }
c0b03411
DV		 9048 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9049 "[modeset]");
25c5b266 9050 }
a6778b3c 9051
460da916
DV		 9052 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9053 intel_crtc_disable(&intel_crtc->base);
9054
ea9d758d
DV		 9055 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9056 if (intel_crtc->base.enabled)
9057 dev_priv->display.crtc_disable(&intel_crtc->base);
9058 }
a6778b3c 9059
6c4c86f5
DV		 9060 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9061 * to set it here already despite that we pass it down the callchain.
f6e5b160 9062 */
b8cecdf5 9063 if (modeset_pipes) {
25c5b266 9064 crtc->mode = *mode;
b8cecdf5
DV		 9065 /* mode_set/enable/disable functions rely on a correct pipe
9066 * config. */
9067 to_intel_crtc(crtc)->config = *pipe_config;
9068 }
7758a113 9069
ea9d758d
DV		 9070 /* Only after disabling all output pipelines that will be changed can we
9071 * update the the output configuration. */
9072 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 9073
47fab737
DV		 9074 if (dev_priv->display.modeset_global_resources)
9075 dev_priv->display.modeset_global_resources(dev);
9076
a6778b3c
DV		 9077 /* Set up the DPLL and any encoders state that needs to adjust or depend
9078 * on the DPLL.
f6e5b160 9079 */
25c5b266 9080 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 9081 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 9082 x, y, fb);
9083 if (ret)
9084 goto done;
a6778b3c
DV		 9085 }
9086
9087 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 9088 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9089 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 9090
25c5b266
DV		 9091 if (modeset_pipes) {
9092 /* Store real post-adjustment hardware mode. */
b8cecdf5 9093 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 9094
25c5b266
DV		 9095 /* Calculate and store various constants which
9096 * are later needed by vblank and swap-completion
9097 * timestamping. They are derived from true hwmode.
9098 */
9099 drm_calc_timestamping_constants(crtc);
9100 }
a6778b3c
DV		 9101
9102 /* FIXME: add subpixel order */
9103done:
c0c36b94 9104 if (ret && crtc->enabled) {
3ac18232
TG		 9105 crtc->hwmode = *saved_hwmode;
9106 crtc->mode = *saved_mode;
a6778b3c
DV		 9107 }
9108
3ac18232 9109out:
b8cecdf5 9110 kfree(pipe_config);
3ac18232 9111 kfree(saved_mode);
a6778b3c 9112 return ret;
f6e5b160
CW		 9113}
9114
e7457a9a
DL		 9115static int intel_set_mode(struct drm_crtc *crtc,
9116 struct drm_display_mode *mode,
9117 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 9118{
9119 int ret;
9120
9121 ret = __intel_set_mode(crtc, mode, x, y, fb);
9122
9123 if (ret == 0)
9124 intel_modeset_check_state(crtc->dev);
9125
9126 return ret;
9127}
9128
c0c36b94
CW		 9129void intel_crtc_restore_mode(struct drm_crtc *crtc)
9130{
9131 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9132}
9133
25c5b266
DV		 9134#undef for_each_intel_crtc_masked
9135
d9e55608
DV		 9136static void intel_set_config_free(struct intel_set_config *config)
9137{
9138 if (!config)
9139 return;
9140
1aa4b628
DV		 9141 kfree(config->save_connector_encoders);
9142 kfree(config->save_encoder_crtcs);
d9e55608
DV		 9143 kfree(config);
9144}
9145
85f9eb71
DV		 9146static int intel_set_config_save_state(struct drm_device *dev,
9147 struct intel_set_config *config)
9148{
85f9eb71
DV		 9149 struct drm_encoder *encoder;
9150 struct drm_connector *connector;
9151 int count;
9152
1aa4b628
DV		 9153 config->save_encoder_crtcs =
9154 kcalloc(dev->mode_config.num_encoder,
9155 sizeof(struct drm_crtc *), GFP_KERNEL);
9156 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9157 return -ENOMEM;
9158
1aa4b628
DV		 9159 config->save_connector_encoders =
9160 kcalloc(dev->mode_config.num_connector,
9161 sizeof(struct drm_encoder *), GFP_KERNEL);
9162 if (!config->save_connector_encoders)
85f9eb71
DV		 9163 return -ENOMEM;
9164
9165 /* Copy data. Note that driver private data is not affected.
9166 * Should anything bad happen only the expected state is
9167 * restored, not the drivers personal bookkeeping.
9168 */
85f9eb71
DV		 9169 count = 0;
9170 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9171 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9172 }
9173
9174 count = 0;
9175 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9176 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9177 }
9178
9179 return 0;
9180}
9181
9182static void intel_set_config_restore_state(struct drm_device *dev,
9183 struct intel_set_config *config)
9184{
9a935856
DV		 9185 struct intel_encoder *encoder;
9186 struct intel_connector *connector;
85f9eb71
DV		 9187 int count;
9188
85f9eb71 9189 count = 0;
9a935856
DV		 9190 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9191 encoder->new_crtc =
9192 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9193 }
9194
9195 count = 0;
9a935856
DV		 9196 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9197 connector->new_encoder =
9198 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9199 }
9200}
9201
e3de42b6 9202static bool
2e57f47d 9203is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9204{
9205 int i;
9206
2e57f47d
CW		 9207 if (set->num_connectors == 0)
9208 return false;
9209
9210 if (WARN_ON(set->connectors == NULL))
9211 return false;
9212
9213 for (i = 0; i < set->num_connectors; i++)
9214 if (set->connectors[i]->encoder &&
9215 set->connectors[i]->encoder->crtc == set->crtc &&
9216 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9217 return true;
9218
9219 return false;
9220}
9221
5e2b584e
DV		 9222static void
9223intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9224 struct intel_set_config *config)
9225{
9226
9227 /* We should be able to check here if the fb has the same properties
9228 * and then just flip_or_move it */
2e57f47d
CW		 9229 if (is_crtc_connector_off(set)) {
9230 config->mode_changed = true;
e3de42b6 9231 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9232 /* If we have no fb then treat it as a full mode set */
9233 if (set->crtc->fb == NULL) {
319d9827
JB		 9234 struct intel_crtc *intel_crtc =
9235 to_intel_crtc(set->crtc);
9236
9237 if (intel_crtc->active && i915_fastboot) {
9238 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9239 config->fb_changed = true;
9240 } else {
9241 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9242 config->mode_changed = true;
9243 }
5e2b584e
DV		 9244 } else if (set->fb == NULL) {
9245 config->mode_changed = true;
72f4901e
DV		 9246 } else if (set->fb->pixel_format !=
9247 set->crtc->fb->pixel_format) {
5e2b584e 9248 config->mode_changed = true;
e3de42b6 9249 } else {
5e2b584e 9250 config->fb_changed = true;
e3de42b6 9251 }
5e2b584e
DV		 9252 }
9253
835c5873 9254 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9255 config->fb_changed = true;
9256
9257 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9258 DRM_DEBUG_KMS("modes are different, full mode set\n");
9259 drm_mode_debug_printmodeline(&set->crtc->mode);
9260 drm_mode_debug_printmodeline(set->mode);
9261 config->mode_changed = true;
9262 }
a1d95703
CW		 9263
9264 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9265 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9266}
9267
2e431051 9268static int
9a935856
DV		 9269intel_modeset_stage_output_state(struct drm_device *dev,
9270 struct drm_mode_set *set,
9271 struct intel_set_config *config)
50f56119 9272{
85f9eb71 9273 struct drm_crtc *new_crtc;
9a935856
DV		 9274 struct intel_connector *connector;
9275 struct intel_encoder *encoder;
f3f08572 9276 int ro;
50f56119 9277
9abdda74 9278 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9279 * of connectors. For paranoia, double-check this. */
9280 WARN_ON(!set->fb && (set->num_connectors != 0));
9281 WARN_ON(set->fb && (set->num_connectors == 0));
9282
9a935856
DV		 9283 list_for_each_entry(connector, &dev->mode_config.connector_list,
9284 base.head) {
9285 /* Otherwise traverse passed in connector list and get encoders
9286 * for them. */
50f56119 9287 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9288 if (set->connectors[ro] == &connector->base) {
9289 connector->new_encoder = connector->encoder;
50f56119
DV		 9290 break;
9291 }
9292 }
9293
9a935856
DV		 9294 /* If we disable the crtc, disable all its connectors. Also, if
9295 * the connector is on the changing crtc but not on the new
9296 * connector list, disable it. */
9297 if ((!set->fb || ro == set->num_connectors) &&
9298 connector->base.encoder &&
9299 connector->base.encoder->crtc == set->crtc) {
9300 connector->new_encoder = NULL;
9301
9302 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9303 connector->base.base.id,
9304 drm_get_connector_name(&connector->base));
9305 }
9306
9307
9308 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9309 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9310 config->mode_changed = true;
50f56119
DV		 9311 }
9312 }
9a935856 9313 /* connector->new_encoder is now updated for all connectors. */
50f56119 9314
9a935856 9315 /* Update crtc of enabled connectors. */
9a935856
DV		 9316 list_for_each_entry(connector, &dev->mode_config.connector_list,
9317 base.head) {
9318 if (!connector->new_encoder)
50f56119
DV		 9319 continue;
9320
9a935856 9321 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9322
9323 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9324 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9325 new_crtc = set->crtc;
9326 }
9327
9328 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9329 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9330 new_crtc)) {
5e2b584e 9331 return -EINVAL;
50f56119 9332 }
9a935856
DV		 9333 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9334
9335 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9336 connector->base.base.id,
9337 drm_get_connector_name(&connector->base),
9338 new_crtc->base.id);
9339 }
9340
9341 /* Check for any encoders that needs to be disabled. */
9342 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9343 base.head) {
9344 list_for_each_entry(connector,
9345 &dev->mode_config.connector_list,
9346 base.head) {
9347 if (connector->new_encoder == encoder) {
9348 WARN_ON(!connector->new_encoder->new_crtc);
9349
9350 goto next_encoder;
9351 }
9352 }
9353 encoder->new_crtc = NULL;
9354next_encoder:
9355 /* Only now check for crtc changes so we don't miss encoders
9356 * that will be disabled. */
9357 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9358 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9359 config->mode_changed = true;
50f56119
DV		 9360 }
9361 }
9a935856 9362 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9363
2e431051
DV		 9364 return 0;
9365}
9366
9367static int intel_crtc_set_config(struct drm_mode_set *set)
9368{
9369 struct drm_device *dev;
2e431051
DV		 9370 struct drm_mode_set save_set;
9371 struct intel_set_config *config;
9372 int ret;
2e431051 9373
8d3e375e
DV		 9374 BUG_ON(!set);
9375 BUG_ON(!set->crtc);
9376 BUG_ON(!set->crtc->helper_private);
2e431051 9377
7e53f3a4
DV		 9378 /* Enforce sane interface api - has been abused by the fb helper. */
9379 BUG_ON(!set->mode && set->fb);
9380 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9381
2e431051
DV		 9382 if (set->fb) {
9383 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9384 set->crtc->base.id, set->fb->base.id,
9385 (int)set->num_connectors, set->x, set->y);
9386 } else {
9387 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9388 }
9389
9390 dev = set->crtc->dev;
9391
9392 ret = -ENOMEM;
9393 config = kzalloc(sizeof(*config), GFP_KERNEL);
9394 if (!config)
9395 goto out_config;
9396
9397 ret = intel_set_config_save_state(dev, config);
9398 if (ret)
9399 goto out_config;
9400
9401 save_set.crtc = set->crtc;
9402 save_set.mode = &set->crtc->mode;
9403 save_set.x = set->crtc->x;
9404 save_set.y = set->crtc->y;
9405 save_set.fb = set->crtc->fb;
9406
9407 /* Compute whether we need a full modeset, only an fb base update or no
9408 * change at all. In the future we might also check whether only the
9409 * mode changed, e.g. for LVDS where we only change the panel fitter in
9410 * such cases. */
9411 intel_set_config_compute_mode_changes(set, config);
9412
9a935856 9413 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9414 if (ret)
9415 goto fail;
9416
5e2b584e 9417 if (config->mode_changed) {
c0c36b94
CW		 9418 ret = intel_set_mode(set->crtc, set->mode,
9419 set->x, set->y, set->fb);
5e2b584e 9420 } else if (config->fb_changed) {
4878cae2
VS		 9421 intel_crtc_wait_for_pending_flips(set->crtc);
9422
4f660f49 9423 ret = intel_pipe_set_base(set->crtc,
94352cf9 9424 set->x, set->y, set->fb);
50f56119
DV		 9425 }
9426
2d05eae1 9427 if (ret) {
bf67dfeb
DV		 9428 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9429 set->crtc->base.id, ret);
50f56119 9430fail:
2d05eae1 9431 intel_set_config_restore_state(dev, config);
50f56119 9432
2d05eae1
CW		 9433 /* Try to restore the config */
9434 if (config->mode_changed &&
9435 intel_set_mode(save_set.crtc, save_set.mode,
9436 save_set.x, save_set.y, save_set.fb))
9437 DRM_ERROR("failed to restore config after modeset failure\n");
9438 }
50f56119 9439
d9e55608
DV		 9440out_config:
9441 intel_set_config_free(config);
50f56119
DV		 9442 return ret;
9443}
f6e5b160
CW		 9444
9445static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9446 .cursor_set = intel_crtc_cursor_set,
9447 .cursor_move = intel_crtc_cursor_move,
9448 .gamma_set = intel_crtc_gamma_set,
50f56119 9449 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9450 .destroy = intel_crtc_destroy,
9451 .page_flip = intel_crtc_page_flip,
9452};
9453
79f689aa
PZ		 9454static void intel_cpu_pll_init(struct drm_device *dev)
9455{
affa9354 9456 if (HAS_DDI(dev))
79f689aa
PZ		 9457 intel_ddi_pll_init(dev);
9458}
9459
5358901f
DV		 9460static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9461 struct intel_shared_dpll *pll,
9462 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9463{
5358901f 9464 uint32_t val;
ee7b9f93 9465
5358901f 9466 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9467 hw_state->dpll = val;
9468 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9469 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9470
9471 return val & DPLL_VCO_ENABLE;
9472}
9473
15bdd4cf
DV		 9474static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9475 struct intel_shared_dpll *pll)
9476{
9477 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9478 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9479}
9480
e7b903d2
DV		 9481static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9482 struct intel_shared_dpll *pll)
9483{
e7b903d2
DV		 9484 /* PCH refclock must be enabled first */
9485 assert_pch_refclk_enabled(dev_priv);
9486
15bdd4cf
DV		 9487 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9488
9489 /* Wait for the clocks to stabilize. */
9490 POSTING_READ(PCH_DPLL(pll->id));
9491 udelay(150);
9492
9493 /* The pixel multiplier can only be updated once the
9494 * DPLL is enabled and the clocks are stable.
9495 *
9496 * So write it again.
9497 */
9498 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9499 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9500 udelay(200);
9501}
9502
9503static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9504 struct intel_shared_dpll *pll)
9505{
9506 struct drm_device *dev = dev_priv->dev;
9507 struct intel_crtc *crtc;
e7b903d2
DV		 9508
9509 /* Make sure no transcoder isn't still depending on us. */
9510 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9511 if (intel_crtc_to_shared_dpll(crtc) == pll)
9512 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9513 }
9514
15bdd4cf
DV		 9515 I915_WRITE(PCH_DPLL(pll->id), 0);
9516 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9517 udelay(200);
9518}
9519
46edb027
DV		 9520static char *ibx_pch_dpll_names[] = {
9521 "PCH DPLL A",
9522 "PCH DPLL B",
9523};
9524
7c74ade1 9525static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9526{
e7b903d2 9527 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9528 int i;
9529
7c74ade1 9530 dev_priv->num_shared_dpll = 2;
ee7b9f93 9531
e72f9fbf 9532 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9533 dev_priv->shared_dplls[i].id = i;
9534 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9535 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9536 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9537 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9538 dev_priv->shared_dplls[i].get_hw_state =
9539 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9540 }
9541}
9542
7c74ade1
DV		 9543static void intel_shared_dpll_init(struct drm_device *dev)
9544{
e7b903d2 9545 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9546
9547 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9548 ibx_pch_dpll_init(dev);
9549 else
9550 dev_priv->num_shared_dpll = 0;
9551
9552 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9553 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9554 dev_priv->num_shared_dpll);
9555}
9556
b358d0a6 9557static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9558{
22fd0fab 9559 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9560 struct intel_crtc *intel_crtc;
9561 int i;
9562
9563 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9564 if (intel_crtc == NULL)
9565 return;
9566
9567 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9568
9569 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9570 for (i = 0; i < 256; i++) {
9571 intel_crtc->lut_r[i] = i;
9572 intel_crtc->lut_g[i] = i;
9573 intel_crtc->lut_b[i] = i;
9574 }
9575
80824003
JB		 9576 /* Swap pipes & planes for FBC on pre-965 */
9577 intel_crtc->pipe = pipe;
9578 intel_crtc->plane = pipe;
e2e767ab 9579 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9580 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9581 intel_crtc->plane = !pipe;
80824003
JB		 9582 }
9583
22fd0fab
JB		 9584 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9585 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9586 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9587 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9588
79e53945 9589 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9590}
9591
08d7b3d1 9592int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9593 struct drm_file *file)
08d7b3d1 9594{
08d7b3d1 9595 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9596 struct drm_mode_object *drmmode_obj;
9597 struct intel_crtc *crtc;
08d7b3d1 9598
1cff8f6b
DV		 9599 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9600 return -ENODEV;
08d7b3d1 9601
c05422d5
DV		 9602 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9603 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9604
c05422d5 9605 if (!drmmode_obj) {
08d7b3d1
CW		 9606 DRM_ERROR("no such CRTC id\n");
9607 return -EINVAL;
9608 }
9609
c05422d5
DV		 9610 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9611 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9612
c05422d5 9613 return 0;
08d7b3d1
CW		 9614}
9615
66a9278e 9616static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9617{
66a9278e
DV		 9618 struct drm_device *dev = encoder->base.dev;
9619 struct intel_encoder *source_encoder;
79e53945 9620 int index_mask = 0;
79e53945
JB		 9621 int entry = 0;
9622
66a9278e
DV		 9623 list_for_each_entry(source_encoder,
9624 &dev->mode_config.encoder_list, base.head) {
9625
9626 if (encoder == source_encoder)
79e53945 9627 index_mask |= (1 << entry);
66a9278e
DV		 9628
9629 /* Intel hw has only one MUX where enocoders could be cloned. */
9630 if (encoder->cloneable && source_encoder->cloneable)
9631 index_mask |= (1 << entry);
9632
79e53945
JB		 9633 entry++;
9634 }
4ef69c7a 9635
79e53945
JB		 9636 return index_mask;
9637}
9638
4d302442
CW		 9639static bool has_edp_a(struct drm_device *dev)
9640{
9641 struct drm_i915_private *dev_priv = dev->dev_private;
9642
9643 if (!IS_MOBILE(dev))
9644 return false;
9645
9646 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9647 return false;
9648
9649 if (IS_GEN5(dev) &&
9650 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9651 return false;
9652
9653 return true;
9654}
9655
79e53945
JB		 9656static void intel_setup_outputs(struct drm_device *dev)
9657{
725e30ad 9658 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9659 struct intel_encoder *encoder;
cb0953d7 9660 bool dpd_is_edp = false;
79e53945 9661
c9093354 9662 intel_lvds_init(dev);
79e53945 9663
c40c0f5b 9664 if (!IS_ULT(dev))
79935fca 9665 intel_crt_init(dev);
cb0953d7 9666
affa9354 9667 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9668 int found;
9669
9670 /* Haswell uses DDI functions to detect digital outputs */
9671 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9672 /* DDI A only supports eDP */
9673 if (found)
9674 intel_ddi_init(dev, PORT_A);
9675
9676 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9677 * register */
9678 found = I915_READ(SFUSE_STRAP);
9679
9680 if (found & SFUSE_STRAP_DDIB_DETECTED)
9681 intel_ddi_init(dev, PORT_B);
9682 if (found & SFUSE_STRAP_DDIC_DETECTED)
9683 intel_ddi_init(dev, PORT_C);
9684 if (found & SFUSE_STRAP_DDID_DETECTED)
9685 intel_ddi_init(dev, PORT_D);
9686 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9687 int found;
270b3042
DV		 9688 dpd_is_edp = intel_dpd_is_edp(dev);
9689
9690 if (has_edp_a(dev))
9691 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9692
dc0fa718 9693 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9694 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9695 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9696 if (!found)
e2debe91 9697 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9698 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9699 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9700 }
9701
dc0fa718 9702 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9703 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9704
dc0fa718 9705 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9706 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9707
5eb08b69 9708 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9709 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9710
270b3042 9711 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9712 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9713 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9714 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB		 9715 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9716 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9717 PORT_C);
9718 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9719 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9720 PORT_C);
9721 }
19c03924 9722
dc0fa718 9723 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9724 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9725 PORT_B);
67cfc203
VS		 9726 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9727 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9728 }
3cfca973
JN		 9729
9730 intel_dsi_init(dev);
103a196f 9731 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9732 bool found = false;
7d57382e 9733
e2debe91 9734 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9735 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9736 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9737 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9738 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9739 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9740 }
27185ae1 9741
e7281eab 9742 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9743 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9744 }
13520b05
KH		 9745
9746 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9747
e2debe91 9748 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9749 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9750 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9751 }
27185ae1 9752
e2debe91 9753 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9754
b01f2c3a
JB		 9755 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9756 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9757 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9758 }
e7281eab 9759 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9760 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9761 }
27185ae1 9762
b01f2c3a 9763 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9764 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9765 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9766 } else if (IS_GEN2(dev))
79e53945
JB		 9767 intel_dvo_init(dev);
9768
103a196f 9769 if (SUPPORTS_TV(dev))
79e53945
JB		 9770 intel_tv_init(dev);
9771
4ef69c7a
CW		 9772 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9773 encoder->base.possible_crtcs = encoder->crtc_mask;
9774 encoder->base.possible_clones =
66a9278e 9775 intel_encoder_clones(encoder);
79e53945 9776 }
47356eb6 9777
dde86e2d 9778 intel_init_pch_refclk(dev);
270b3042
DV		 9779
9780 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9781}
9782
ddfe1567
CW		 9783void intel_framebuffer_fini(struct intel_framebuffer *fb)
9784{
9785 drm_framebuffer_cleanup(&fb->base);
9786 drm_gem_object_unreference_unlocked(&fb->obj->base);
9787}
9788
79e53945
JB		 9789static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9790{
9791 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9792
ddfe1567 9793 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9794 kfree(intel_fb);
9795}
9796
9797static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9798 struct drm_file *file,
79e53945
JB		 9799 unsigned int *handle)
9800{
9801 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9802 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9803
05394f39 9804 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9805}
9806
9807static const struct drm_framebuffer_funcs intel_fb_funcs = {
9808 .destroy = intel_user_framebuffer_destroy,
9809 .create_handle = intel_user_framebuffer_create_handle,
9810};
9811
38651674
DA		 9812int intel_framebuffer_init(struct drm_device *dev,
9813 struct intel_framebuffer *intel_fb,
308e5bcb 9814 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9815 struct drm_i915_gem_object *obj)
79e53945 9816{
a35cdaa0 9817 int pitch_limit;
79e53945
JB		 9818 int ret;
9819
c16ed4be
CW		 9820 if (obj->tiling_mode == I915_TILING_Y) {
9821 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9822 return -EINVAL;
c16ed4be 9823 }
57cd6508 9824
c16ed4be
CW		 9825 if (mode_cmd->pitches[0] & 63) {
9826 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9827 mode_cmd->pitches[0]);
57cd6508 9828 return -EINVAL;
c16ed4be 9829 }
57cd6508 9830
a35cdaa0
CW		 9831 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9832 pitch_limit = 32*1024;
9833 } else if (INTEL_INFO(dev)->gen >= 4) {
9834 if (obj->tiling_mode)
9835 pitch_limit = 16*1024;
9836 else
9837 pitch_limit = 32*1024;
9838 } else if (INTEL_INFO(dev)->gen >= 3) {
9839 if (obj->tiling_mode)
9840 pitch_limit = 8*1024;
9841 else
9842 pitch_limit = 16*1024;
9843 } else
9844 /* XXX DSPC is limited to 4k tiled */
9845 pitch_limit = 8*1024;
9846
9847 if (mode_cmd->pitches[0] > pitch_limit) {
9848 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9849 obj->tiling_mode ? "tiled" : "linear",
9850 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9851 return -EINVAL;
c16ed4be 9852 }
5d7bd705
VS		 9853
9854 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9855 mode_cmd->pitches[0] != obj->stride) {
9856 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9857 mode_cmd->pitches[0], obj->stride);
5d7bd705 9858 return -EINVAL;
c16ed4be 9859 }
5d7bd705 9860
57779d06 9861 /* Reject formats not supported by any plane early. */
308e5bcb 9862 switch (mode_cmd->pixel_format) {
57779d06 9863 case DRM_FORMAT_C8:
04b3924d
VS		 9864 case DRM_FORMAT_RGB565:
9865 case DRM_FORMAT_XRGB8888:
9866 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9867 break;
9868 case DRM_FORMAT_XRGB1555:
9869 case DRM_FORMAT_ARGB1555:
c16ed4be 9870 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9871 DRM_DEBUG("unsupported pixel format: %s\n",
9872 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9873 return -EINVAL;
c16ed4be 9874 }
57779d06
VS		 9875 break;
9876 case DRM_FORMAT_XBGR8888:
9877 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9878 case DRM_FORMAT_XRGB2101010:
9879 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9880 case DRM_FORMAT_XBGR2101010:
9881 case DRM_FORMAT_ABGR2101010:
c16ed4be 9882 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9883 DRM_DEBUG("unsupported pixel format: %s\n",
9884 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9885 return -EINVAL;
c16ed4be 9886 }
b5626747 9887 break;
04b3924d
VS		 9888 case DRM_FORMAT_YUYV:
9889 case DRM_FORMAT_UYVY:
9890 case DRM_FORMAT_YVYU:
9891 case DRM_FORMAT_VYUY:
c16ed4be 9892 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9893 DRM_DEBUG("unsupported pixel format: %s\n",
9894 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9895 return -EINVAL;
c16ed4be 9896 }
57cd6508
CW		 9897 break;
9898 default:
4ee62c76
VS		 9899 DRM_DEBUG("unsupported pixel format: %s\n",
9900 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9901 return -EINVAL;
9902 }
9903
90f9a336
VS		 9904 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9905 if (mode_cmd->offsets[0] != 0)
9906 return -EINVAL;
9907
c7d73f6a
DV		 9908 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9909 intel_fb->obj = obj;
9910
79e53945
JB		 9911 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9912 if (ret) {
9913 DRM_ERROR("framebuffer init failed %d\n", ret);
9914 return ret;
9915 }
9916
79e53945
JB		 9917 return 0;
9918}
9919
79e53945
JB		 9920static struct drm_framebuffer *
9921intel_user_framebuffer_create(struct drm_device *dev,
9922 struct drm_file *filp,
308e5bcb 9923 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9924{
05394f39 9925 struct drm_i915_gem_object *obj;
79e53945 9926
308e5bcb
JB		 9927 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9928 mode_cmd->handles[0]));
c8725226 9929 if (&obj->base == NULL)
cce13ff7 9930 return ERR_PTR(-ENOENT);
79e53945 9931
d2dff872 9932 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9933}
9934
79e53945 9935static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9936 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9937 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9938};
9939
e70236a8
JB		 9940/* Set up chip specific display functions */
9941static void intel_init_display(struct drm_device *dev)
9942{
9943 struct drm_i915_private *dev_priv = dev->dev_private;
9944
ee9300bb
DV		 9945 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9946 dev_priv->display.find_dpll = g4x_find_best_dpll;
9947 else if (IS_VALLEYVIEW(dev))
9948 dev_priv->display.find_dpll = vlv_find_best_dpll;
9949 else if (IS_PINEVIEW(dev))
9950 dev_priv->display.find_dpll = pnv_find_best_dpll;
9951 else
9952 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9953
affa9354 9954 if (HAS_DDI(dev)) {
0e8ffe1b 9955 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9956 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9957 dev_priv->display.crtc_enable = haswell_crtc_enable;
9958 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9959 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9960 dev_priv->display.update_plane = ironlake_update_plane;
9961 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9962 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9963 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9964 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9965 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9966 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9967 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9968 } else if (IS_VALLEYVIEW(dev)) {
9969 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9970 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9971 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9972 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9973 dev_priv->display.off = i9xx_crtc_off;
9974 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9975 } else {
0e8ffe1b 9976 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9977 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9978 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9979 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9980 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9981 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9982 }
e70236a8 9983
e70236a8 9984 /* Returns the core display clock speed */
25eb05fc
JB		 9985 if (IS_VALLEYVIEW(dev))
9986 dev_priv->display.get_display_clock_speed =
9987 valleyview_get_display_clock_speed;
9988 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9989 dev_priv->display.get_display_clock_speed =
9990 i945_get_display_clock_speed;
9991 else if (IS_I915G(dev))
9992 dev_priv->display.get_display_clock_speed =
9993 i915_get_display_clock_speed;
257a7ffc 9994 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 9995 dev_priv->display.get_display_clock_speed =
9996 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 9997 else if (IS_PINEVIEW(dev))
9998 dev_priv->display.get_display_clock_speed =
9999 pnv_get_display_clock_speed;
e70236a8
JB		 10000 else if (IS_I915GM(dev))
10001 dev_priv->display.get_display_clock_speed =
10002 i915gm_get_display_clock_speed;
10003 else if (IS_I865G(dev))
10004 dev_priv->display.get_display_clock_speed =
10005 i865_get_display_clock_speed;
f0f8a9ce 10006 else if (IS_I85X(dev))
e70236a8
JB		 10007 dev_priv->display.get_display_clock_speed =
10008 i855_get_display_clock_speed;
10009 else /* 852, 830 */
10010 dev_priv->display.get_display_clock_speed =
10011 i830_get_display_clock_speed;
10012
7f8a8569 10013 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 10014 if (IS_GEN5(dev)) {
674cf967 10015 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 10016 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 10017 } else if (IS_GEN6(dev)) {
674cf967 10018 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 10019 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 10020 } else if (IS_IVYBRIDGE(dev)) {
10021 /* FIXME: detect B0+ stepping and use auto training */
10022 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 10023 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 10024 dev_priv->display.modeset_global_resources =
10025 ivb_modeset_global_resources;
c82e4d26
ED		 10026 } else if (IS_HASWELL(dev)) {
10027 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 10028 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 10029 dev_priv->display.modeset_global_resources =
10030 haswell_modeset_global_resources;
a0e63c22 10031 }
6067aaea 10032 } else if (IS_G4X(dev)) {
e0dac65e 10033 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 10034 }
8c9f3aaf
JB		 10035
10036 /* Default just returns -ENODEV to indicate unsupported */
10037 dev_priv->display.queue_flip = intel_default_queue_flip;
10038
10039 switch (INTEL_INFO(dev)->gen) {
10040 case 2:
10041 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10042 break;
10043
10044 case 3:
10045 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10046 break;
10047
10048 case 4:
10049 case 5:
10050 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10051 break;
10052
10053 case 6:
10054 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10055 break;
7c9017e5
JB		 10056 case 7:
10057 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10058 break;
8c9f3aaf 10059 }
e70236a8
JB		 10060}
10061
b690e96c
JB		 10062/*
10063 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10064 * resume, or other times. This quirk makes sure that's the case for
10065 * affected systems.
10066 */
0206e353 10067static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 10068{
10069 struct drm_i915_private *dev_priv = dev->dev_private;
10070
10071 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 10072 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 10073}
10074
435793df
KP		 10075/*
10076 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10077 */
10078static void quirk_ssc_force_disable(struct drm_device *dev)
10079{
10080 struct drm_i915_private *dev_priv = dev->dev_private;
10081 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 10082 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 10083}
10084
4dca20ef 10085/*
5a15ab5b
CE		 10086 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10087 * brightness value
4dca20ef
CE		 10088 */
10089static void quirk_invert_brightness(struct drm_device *dev)
10090{
10091 struct drm_i915_private *dev_priv = dev->dev_private;
10092 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 10093 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 10094}
10095
e85843be
KM		 10096/*
10097 * Some machines (Dell XPS13) suffer broken backlight controls if
10098 * BLM_PCH_PWM_ENABLE is set.
10099 */
10100static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10101{
10102 struct drm_i915_private *dev_priv = dev->dev_private;
10103 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10104 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10105}
10106
b690e96c
JB		 10107struct intel_quirk {
10108 int device;
10109 int subsystem_vendor;
10110 int subsystem_device;
10111 void (*hook)(struct drm_device *dev);
10112};
10113
5f85f176
EE		 10114/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10115struct intel_dmi_quirk {
10116 void (*hook)(struct drm_device *dev);
10117 const struct dmi_system_id (*dmi_id_list)[];
10118};
10119
10120static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10121{
10122 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10123 return 1;
10124}
10125
10126static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10127 {
10128 .dmi_id_list = &(const struct dmi_system_id[]) {
10129 {
10130 .callback = intel_dmi_reverse_brightness,
10131 .ident = "NCR Corporation",
10132 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10133 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10134 },
10135 },
10136 { } /* terminating entry */
10137 },
10138 .hook = quirk_invert_brightness,
10139 },
10140};
10141
c43b5634 10142static struct intel_quirk intel_quirks[] = {
b690e96c 10143 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10144 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10145
b690e96c
JB		 10146 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10147 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10148
b690e96c
JB		 10149 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10150 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10151
ccd0d36e 10152 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 10153 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 10154 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10155
10156 /* Lenovo U160 cannot use SSC on LVDS */
10157 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10158
10159 /* Sony Vaio Y cannot use SSC on LVDS */
10160 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 10161
10162 /* Acer Aspire 5734Z must invert backlight brightness */
10163 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 10164
10165 /* Acer/eMachines G725 */
10166 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 10167
10168 /* Acer/eMachines e725 */
10169 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 10170
10171 /* Acer/Packard Bell NCL20 */
10172 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 10173
10174 /* Acer Aspire 4736Z */
10175 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
e85843be
KM		 10176
10177 /* Dell XPS13 HD Sandy Bridge */
10178 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10179 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10180 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10181};
10182
10183static void intel_init_quirks(struct drm_device *dev)
10184{
10185 struct pci_dev *d = dev->pdev;
10186 int i;
10187
10188 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10189 struct intel_quirk *q = &intel_quirks[i];
10190
10191 if (d->device == q->device &&
10192 (d->subsystem_vendor == q->subsystem_vendor ||
10193 q->subsystem_vendor == PCI_ANY_ID) &&
10194 (d->subsystem_device == q->subsystem_device ||
10195 q->subsystem_device == PCI_ANY_ID))
10196 q->hook(dev);
10197 }
5f85f176
EE		 10198 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10199 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10200 intel_dmi_quirks[i].hook(dev);
10201 }
b690e96c
JB		 10202}
10203
9cce37f4
JB		 10204/* Disable the VGA plane that we never use */
10205static void i915_disable_vga(struct drm_device *dev)
10206{
10207 struct drm_i915_private *dev_priv = dev->dev_private;
10208 u8 sr1;
766aa1c4 10209 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10210
10211 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10212 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10213 sr1 = inb(VGA_SR_DATA);
10214 outb(sr1 | 1<<5, VGA_SR_DATA);
81b5c7bc
AW		 10215
10216 /* Disable VGA memory on Intel HD */
10217 if (HAS_PCH_SPLIT(dev)) {
10218 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10219 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10220 VGA_RSRC_NORMAL_IO |
10221 VGA_RSRC_NORMAL_MEM);
10222 }
10223
9cce37f4
JB		 10224 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10225 udelay(300);
10226
10227 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10228 POSTING_READ(vga_reg);
10229}
10230
81b5c7bc
AW		 10231static void i915_enable_vga(struct drm_device *dev)
10232{
10233 /* Enable VGA memory on Intel HD */
10234 if (HAS_PCH_SPLIT(dev)) {
10235 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10236 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10237 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10238 VGA_RSRC_LEGACY_MEM |
10239 VGA_RSRC_NORMAL_IO |
10240 VGA_RSRC_NORMAL_MEM);
10241 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10242 }
10243}
10244
f817586c
DV		 10245void intel_modeset_init_hw(struct drm_device *dev)
10246{
fa42e23c 10247 intel_init_power_well(dev);
0232e927 10248
a8f78b58
ED		 10249 intel_prepare_ddi(dev);
10250
f817586c
DV		 10251 intel_init_clock_gating(dev);
10252
79f5b2c7 10253 mutex_lock(&dev->struct_mutex);
8090c6b9 10254 intel_enable_gt_powersave(dev);
79f5b2c7 10255 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10256}
10257
7d708ee4
ID		 10258void intel_modeset_suspend_hw(struct drm_device *dev)
10259{
10260 intel_suspend_hw(dev);
10261}
10262
79e53945
JB		 10263void intel_modeset_init(struct drm_device *dev)
10264{
652c393a 10265 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10266 int i, j, ret;
79e53945
JB		 10267
10268 drm_mode_config_init(dev);
10269
10270 dev->mode_config.min_width = 0;
10271 dev->mode_config.min_height = 0;
10272
019d96cb
DA		 10273 dev->mode_config.preferred_depth = 24;
10274 dev->mode_config.prefer_shadow = 1;
10275
e6ecefaa 10276 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10277
b690e96c
JB		 10278 intel_init_quirks(dev);
10279
1fa61106
ED		 10280 intel_init_pm(dev);
10281
e3c74757
BW		 10282 if (INTEL_INFO(dev)->num_pipes == 0)
10283 return;
10284
e70236a8
JB		 10285 intel_init_display(dev);
10286
a6c45cf0
CW		 10287 if (IS_GEN2(dev)) {
10288 dev->mode_config.max_width = 2048;
10289 dev->mode_config.max_height = 2048;
10290 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10291 dev->mode_config.max_width = 4096;
10292 dev->mode_config.max_height = 4096;
79e53945 10293 } else {
a6c45cf0
CW		 10294 dev->mode_config.max_width = 8192;
10295 dev->mode_config.max_height = 8192;
79e53945 10296 }
5d4545ae 10297 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10298
28c97730 10299 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10300 INTEL_INFO(dev)->num_pipes,
10301 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10302
08e2a7de 10303 for_each_pipe(i) {
79e53945 10304 intel_crtc_init(dev, i);
7f1f3851
JB		 10305 for (j = 0; j < dev_priv->num_plane; j++) {
10306 ret = intel_plane_init(dev, i, j);
10307 if (ret)
06da8da2
VS		 10308 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10309 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10310 }
79e53945
JB		 10311 }
10312
79f689aa 10313 intel_cpu_pll_init(dev);
e72f9fbf 10314 intel_shared_dpll_init(dev);
ee7b9f93 10315
9cce37f4
JB		 10316 /* Just disable it once at startup */
10317 i915_disable_vga(dev);
79e53945 10318 intel_setup_outputs(dev);
11be49eb
CW		 10319
10320 /* Just in case the BIOS is doing something questionable. */
10321 intel_disable_fbc(dev);
2c7111db
CW		 10322}
10323
24929352
DV		 10324static void
10325intel_connector_break_all_links(struct intel_connector *connector)
10326{
10327 connector->base.dpms = DRM_MODE_DPMS_OFF;
10328 connector->base.encoder = NULL;
10329 connector->encoder->connectors_active = false;
10330 connector->encoder->base.crtc = NULL;
10331}
10332
7fad798e
DV		 10333static void intel_enable_pipe_a(struct drm_device *dev)
10334{
10335 struct intel_connector *connector;
10336 struct drm_connector *crt = NULL;
10337 struct intel_load_detect_pipe load_detect_temp;
10338
10339 /* We can't just switch on the pipe A, we need to set things up with a
10340 * proper mode and output configuration. As a gross hack, enable pipe A
10341 * by enabling the load detect pipe once. */
10342 list_for_each_entry(connector,
10343 &dev->mode_config.connector_list,
10344 base.head) {
10345 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10346 crt = &connector->base;
10347 break;
10348 }
10349 }
10350
10351 if (!crt)
10352 return;
10353
10354 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10355 intel_release_load_detect_pipe(crt, &load_detect_temp);
10356
652c393a 10357
7fad798e
DV		 10358}
10359
fa555837
DV		 10360static bool
10361intel_check_plane_mapping(struct intel_crtc *crtc)
10362{
7eb552ae
BW		 10363 struct drm_device *dev = crtc->base.dev;
10364 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10365 u32 reg, val;
10366
7eb552ae 10367 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10368 return true;
10369
10370 reg = DSPCNTR(!crtc->plane);
10371 val = I915_READ(reg);
10372
10373 if ((val & DISPLAY_PLANE_ENABLE) &&
10374 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10375 return false;
10376
10377 return true;
10378}
10379
24929352
DV		 10380static void intel_sanitize_crtc(struct intel_crtc *crtc)
10381{
10382 struct drm_device *dev = crtc->base.dev;
10383 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10384 u32 reg;
24929352 10385
24929352 10386 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10387 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10388 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10389
10390 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10391 * disable the crtc (and hence change the state) if it is wrong. Note
10392 * that gen4+ has a fixed plane -> pipe mapping. */
10393 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10394 struct intel_connector *connector;
10395 bool plane;
10396
24929352
DV		 10397 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10398 crtc->base.base.id);
10399
10400 /* Pipe has the wrong plane attached and the plane is active.
10401 * Temporarily change the plane mapping and disable everything
10402 * ... */
10403 plane = crtc->plane;
10404 crtc->plane = !plane;
10405 dev_priv->display.crtc_disable(&crtc->base);
10406 crtc->plane = plane;
10407
10408 /* ... and break all links. */
10409 list_for_each_entry(connector, &dev->mode_config.connector_list,
10410 base.head) {
10411 if (connector->encoder->base.crtc != &crtc->base)
10412 continue;
10413
10414 intel_connector_break_all_links(connector);
10415 }
10416
10417 WARN_ON(crtc->active);
10418 crtc->base.enabled = false;
10419 }
24929352 10420
7fad798e
DV		 10421 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10422 crtc->pipe == PIPE_A && !crtc->active) {
10423 /* BIOS forgot to enable pipe A, this mostly happens after
10424 * resume. Force-enable the pipe to fix this, the update_dpms
10425 * call below we restore the pipe to the right state, but leave
10426 * the required bits on. */
10427 intel_enable_pipe_a(dev);
10428 }
10429
24929352
DV		 10430 /* Adjust the state of the output pipe according to whether we
10431 * have active connectors/encoders. */
10432 intel_crtc_update_dpms(&crtc->base);
10433
10434 if (crtc->active != crtc->base.enabled) {
10435 struct intel_encoder *encoder;
10436
10437 /* This can happen either due to bugs in the get_hw_state
10438 * functions or because the pipe is force-enabled due to the
10439 * pipe A quirk. */
10440 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10441 crtc->base.base.id,
10442 crtc->base.enabled ? "enabled" : "disabled",
10443 crtc->active ? "enabled" : "disabled");
10444
10445 crtc->base.enabled = crtc->active;
10446
10447 /* Because we only establish the connector -> encoder ->
10448 * crtc links if something is active, this means the
10449 * crtc is now deactivated. Break the links. connector
10450 * -> encoder links are only establish when things are
10451 * actually up, hence no need to break them. */
10452 WARN_ON(crtc->active);
10453
10454 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10455 WARN_ON(encoder->connectors_active);
10456 encoder->base.crtc = NULL;
10457 }
10458 }
10459}
10460
10461static void intel_sanitize_encoder(struct intel_encoder *encoder)
10462{
10463 struct intel_connector *connector;
10464 struct drm_device *dev = encoder->base.dev;
10465
10466 /* We need to check both for a crtc link (meaning that the
10467 * encoder is active and trying to read from a pipe) and the
10468 * pipe itself being active. */
10469 bool has_active_crtc = encoder->base.crtc &&
10470 to_intel_crtc(encoder->base.crtc)->active;
10471
10472 if (encoder->connectors_active && !has_active_crtc) {
10473 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10474 encoder->base.base.id,
10475 drm_get_encoder_name(&encoder->base));
10476
10477 /* Connector is active, but has no active pipe. This is
10478 * fallout from our resume register restoring. Disable
10479 * the encoder manually again. */
10480 if (encoder->base.crtc) {
10481 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10482 encoder->base.base.id,
10483 drm_get_encoder_name(&encoder->base));
10484 encoder->disable(encoder);
10485 }
10486
10487 /* Inconsistent output/port/pipe state happens presumably due to
10488 * a bug in one of the get_hw_state functions. Or someplace else
10489 * in our code, like the register restore mess on resume. Clamp
10490 * things to off as a safer default. */
10491 list_for_each_entry(connector,
10492 &dev->mode_config.connector_list,
10493 base.head) {
10494 if (connector->encoder != encoder)
10495 continue;
10496
10497 intel_connector_break_all_links(connector);
10498 }
10499 }
10500 /* Enabled encoders without active connectors will be fixed in
10501 * the crtc fixup. */
10502}
10503
44cec740 10504void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10505{
10506 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10507 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10508
8dc8a27c
PZ		 10509 /* This function can be called both from intel_modeset_setup_hw_state or
10510 * at a very early point in our resume sequence, where the power well
10511 * structures are not yet restored. Since this function is at a very
10512 * paranoid "someone might have enabled VGA while we were not looking"
10513 * level, just check if the power well is enabled instead of trying to
10514 * follow the "don't touch the power well if we don't need it" policy
10515 * the rest of the driver uses. */
10516 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10517 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10518 return;
10519
0fde901f
KM		 10520 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10521 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10522 i915_disable_vga(dev);
0fde901f
KM		 10523 }
10524}
10525
30e984df 10526static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10527{
10528 struct drm_i915_private *dev_priv = dev->dev_private;
10529 enum pipe pipe;
24929352
DV		 10530 struct intel_crtc *crtc;
10531 struct intel_encoder *encoder;
10532 struct intel_connector *connector;
5358901f 10533 int i;
24929352 10534
0e8ffe1b
DV		 10535 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10536 base.head) {
88adfff1 10537 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10538
0e8ffe1b
DV		 10539 crtc->active = dev_priv->display.get_pipe_config(crtc,
10540 &crtc->config);
24929352
DV		 10541
10542 crtc->base.enabled = crtc->active;
10543
10544 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10545 crtc->base.base.id,
10546 crtc->active ? "enabled" : "disabled");
10547 }
10548
5358901f 10549 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10550 if (HAS_DDI(dev))
6441ab5f
PZ		 10551 intel_ddi_setup_hw_pll_state(dev);
10552
5358901f
DV		 10553 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10554 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10555
10556 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10557 pll->active = 0;
10558 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10559 base.head) {
10560 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10561 pll->active++;
10562 }
10563 pll->refcount = pll->active;
10564
35c95375
DV		 10565 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10566 pll->name, pll->refcount, pll->on);
5358901f
DV		 10567 }
10568
24929352
DV		 10569 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10570 base.head) {
10571 pipe = 0;
10572
10573 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10574 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10575 encoder->base.crtc = &crtc->base;
510d5f2f 10576 if (encoder->get_config)
045ac3b5 10577 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10578 } else {
10579 encoder->base.crtc = NULL;
10580 }
10581
10582 encoder->connectors_active = false;
10583 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10584 encoder->base.base.id,
10585 drm_get_encoder_name(&encoder->base),
10586 encoder->base.crtc ? "enabled" : "disabled",
10587 pipe);
10588 }
10589
10590 list_for_each_entry(connector, &dev->mode_config.connector_list,
10591 base.head) {
10592 if (connector->get_hw_state(connector)) {
10593 connector->base.dpms = DRM_MODE_DPMS_ON;
10594 connector->encoder->connectors_active = true;
10595 connector->base.encoder = &connector->encoder->base;
10596 } else {
10597 connector->base.dpms = DRM_MODE_DPMS_OFF;
10598 connector->base.encoder = NULL;
10599 }
10600 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10601 connector->base.base.id,
10602 drm_get_connector_name(&connector->base),
10603 connector->base.encoder ? "enabled" : "disabled");
10604 }
30e984df
DV		 10605}
10606
10607/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10608 * and i915 state tracking structures. */
10609void intel_modeset_setup_hw_state(struct drm_device *dev,
10610 bool force_restore)
10611{
10612 struct drm_i915_private *dev_priv = dev->dev_private;
10613 enum pipe pipe;
10614 struct drm_plane *plane;
10615 struct intel_crtc *crtc;
10616 struct intel_encoder *encoder;
35c95375 10617 int i;
30e984df
DV		 10618
10619 intel_modeset_readout_hw_state(dev);
24929352 10620
babea61d
JB		 10621 /*
10622 * Now that we have the config, copy it to each CRTC struct
10623 * Note that this could go away if we move to using crtc_config
10624 * checking everywhere.
10625 */
10626 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10627 base.head) {
10628 if (crtc->active && i915_fastboot) {
10629 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10630
10631 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10632 crtc->base.base.id);
10633 drm_mode_debug_printmodeline(&crtc->base.mode);
10634 }
10635 }
10636
24929352
DV		 10637 /* HW state is read out, now we need to sanitize this mess. */
10638 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10639 base.head) {
10640 intel_sanitize_encoder(encoder);
10641 }
10642
10643 for_each_pipe(pipe) {
10644 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10645 intel_sanitize_crtc(crtc);
c0b03411 10646 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10647 }
9a935856 10648
35c95375
DV		 10649 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10650 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10651
10652 if (!pll->on || pll->active)
10653 continue;
10654
10655 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10656
10657 pll->disable(dev_priv, pll);
10658 pll->on = false;
10659 }
10660
45e2b5f6 10661 if (force_restore) {
f30da187
DV		 10662 /*
10663 * We need to use raw interfaces for restoring state to avoid
10664 * checking (bogus) intermediate states.
10665 */
45e2b5f6 10666 for_each_pipe(pipe) {
b5644d05
JB		 10667 struct drm_crtc *crtc =
10668 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10669
10670 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10671 crtc->fb);
45e2b5f6 10672 }
b5644d05
JB		 10673 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10674 intel_plane_restore(plane);
0fde901f
KM		 10675
10676 i915_redisable_vga(dev);
45e2b5f6
DV		 10677 } else {
10678 intel_modeset_update_staged_output_state(dev);
10679 }
8af6cf88
DV		 10680
10681 intel_modeset_check_state(dev);
2e938892
DV		 10682
10683 drm_mode_config_reset(dev);
2c7111db
CW		 10684}
10685
10686void intel_modeset_gem_init(struct drm_device *dev)
10687{
1833b134 10688 intel_modeset_init_hw(dev);
02e792fb
DV		 10689
10690 intel_setup_overlay(dev);
24929352 10691
45e2b5f6 10692 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10693}
10694
10695void intel_modeset_cleanup(struct drm_device *dev)
10696{
652c393a
JB		 10697 struct drm_i915_private *dev_priv = dev->dev_private;
10698 struct drm_crtc *crtc;
652c393a 10699
fd0c0642
DV		 10700 /*
10701 * Interrupts and polling as the first thing to avoid creating havoc.
10702 * Too much stuff here (turning of rps, connectors, ...) would
10703 * experience fancy races otherwise.
10704 */
10705 drm_irq_uninstall(dev);
10706 cancel_work_sync(&dev_priv->hotplug_work);
10707 /*
10708 * Due to the hpd irq storm handling the hotplug work can re-arm the
10709 * poll handlers. Hence disable polling after hpd handling is shut down.
10710 */
f87ea761 10711 drm_kms_helper_poll_fini(dev);
fd0c0642 10712
652c393a
JB		 10713 mutex_lock(&dev->struct_mutex);
10714
723bfd70
JB		 10715 intel_unregister_dsm_handler();
10716
652c393a
JB		 10717 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10718 /* Skip inactive CRTCs */
10719 if (!crtc->fb)
10720 continue;
10721
3dec0095 10722 intel_increase_pllclock(crtc);
652c393a
JB		 10723 }
10724
973d04f9 10725 intel_disable_fbc(dev);
e70236a8 10726
81b5c7bc
AW		 10727 i915_enable_vga(dev);
10728
8090c6b9 10729 intel_disable_gt_powersave(dev);
0cdab21f 10730
930ebb46
DV		 10731 ironlake_teardown_rc6(dev);
10732
69341a5e
KH		 10733 mutex_unlock(&dev->struct_mutex);
10734
1630fe75
CW		 10735 /* flush any delayed tasks or pending work */
10736 flush_scheduled_work();
10737
dc652f90
JN		 10738 /* destroy backlight, if any, before the connectors */
10739 intel_panel_destroy_backlight(dev);
10740
79e53945 10741 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10742
10743 intel_cleanup_overlay(dev);
79e53945
JB		 10744}
10745
f1c79df3
ZW		 10746/*
10747 * Return which encoder is currently attached for connector.
10748 */
df0e9248 10749struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10750{
df0e9248
CW		 10751 return &intel_attached_encoder(connector)->base;
10752}
f1c79df3 10753
df0e9248
CW		 10754void intel_connector_attach_encoder(struct intel_connector *connector,
10755 struct intel_encoder *encoder)
10756{
10757 connector->encoder = encoder;
10758 drm_mode_connector_attach_encoder(&connector->base,
10759 &encoder->base);
79e53945 10760}
28d52043
DA		 10761
10762/*
10763 * set vga decode state - true == enable VGA decode
10764 */
10765int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10766{
10767 struct drm_i915_private *dev_priv = dev->dev_private;
10768 u16 gmch_ctrl;
10769
10770 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10771 if (state)
10772 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10773 else
10774 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10775 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10776 return 0;
10777}
c4a1d9e4 10778
c4a1d9e4 10779struct intel_display_error_state {
ff57f1b0
PZ		 10780
10781 u32 power_well_driver;
10782
63b66e5b
CW		 10783 int num_transcoders;
10784
c4a1d9e4
CW		 10785 struct intel_cursor_error_state {
10786 u32 control;
10787 u32 position;
10788 u32 base;
10789 u32 size;
52331309 10790 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10791
10792 struct intel_pipe_error_state {
c4a1d9e4 10793 u32 source;
52331309 10794 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10795
10796 struct intel_plane_error_state {
10797 u32 control;
10798 u32 stride;
10799 u32 size;
10800 u32 pos;
10801 u32 addr;
10802 u32 surface;
10803 u32 tile_offset;
52331309 10804 } plane[I915_MAX_PIPES];
63b66e5b
CW		 10805
10806 struct intel_transcoder_error_state {
10807 enum transcoder cpu_transcoder;
10808
10809 u32 conf;
10810
10811 u32 htotal;
10812 u32 hblank;
10813 u32 hsync;
10814 u32 vtotal;
10815 u32 vblank;
10816 u32 vsync;
10817 } transcoder[4];
c4a1d9e4
CW		 10818};
10819
10820struct intel_display_error_state *
10821intel_display_capture_error_state(struct drm_device *dev)
10822{
0206e353 10823 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10824 struct intel_display_error_state *error;
63b66e5b
CW		 10825 int transcoders[] = {
10826 TRANSCODER_A,
10827 TRANSCODER_B,
10828 TRANSCODER_C,
10829 TRANSCODER_EDP,
10830 };
c4a1d9e4
CW		 10831 int i;
10832
63b66e5b
CW		 10833 if (INTEL_INFO(dev)->num_pipes == 0)
10834 return NULL;
10835
c4a1d9e4
CW		 10836 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10837 if (error == NULL)
10838 return NULL;
10839
ff57f1b0
PZ		 10840 if (HAS_POWER_WELL(dev))
10841 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10842
52331309 10843 for_each_pipe(i) {
a18c4c3d
PZ		 10844 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10845 error->cursor[i].control = I915_READ(CURCNTR(i));
10846 error->cursor[i].position = I915_READ(CURPOS(i));
10847 error->cursor[i].base = I915_READ(CURBASE(i));
10848 } else {
10849 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10850 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10851 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10852 }
c4a1d9e4
CW		 10853
10854 error->plane[i].control = I915_READ(DSPCNTR(i));
10855 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10856 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10857 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10858 error->plane[i].pos = I915_READ(DSPPOS(i));
10859 }
ca291363
PZ		 10860 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10861 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10862 if (INTEL_INFO(dev)->gen >= 4) {
10863 error->plane[i].surface = I915_READ(DSPSURF(i));
10864 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10865 }
10866
c4a1d9e4 10867 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 10868 }
10869
10870 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
10871 if (HAS_DDI(dev_priv->dev))
10872 error->num_transcoders++; /* Account for eDP. */
10873
10874 for (i = 0; i < error->num_transcoders; i++) {
10875 enum transcoder cpu_transcoder = transcoders[i];
10876
10877 error->transcoder[i].cpu_transcoder = cpu_transcoder;
10878
10879 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
10880 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10881 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10882 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10883 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10884 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10885 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10886 }
10887
12d217c7
PZ		 10888 /* In the code above we read the registers without checking if the power
10889 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10890 * prevent the next I915_WRITE from detecting it and printing an error
10891 * message. */
907b28c5 10892 intel_uncore_clear_errors(dev);
12d217c7 10893
c4a1d9e4
CW		 10894 return error;
10895}
10896
edc3d884
MK		 10897#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10898
c4a1d9e4 10899void
edc3d884 10900intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10901 struct drm_device *dev,
10902 struct intel_display_error_state *error)
10903{
10904 int i;
10905
63b66e5b
CW		 10906 if (!error)
10907 return;
10908
edc3d884 10909 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10910 if (HAS_POWER_WELL(dev))
edc3d884 10911 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10912 error->power_well_driver);
52331309 10913 for_each_pipe(i) {
edc3d884 10914 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 10915 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 10916
10917 err_printf(m, "Plane [%d]:\n", i);
10918 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10919 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10920 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10921 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10922 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10923 }
4b71a570 10924 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10925 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10926 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10927 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10928 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10929 }
10930
edc3d884
MK		 10931 err_printf(m, "Cursor [%d]:\n", i);
10932 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10933 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10934 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 10935 }
63b66e5b
CW		 10936
10937 for (i = 0; i < error->num_transcoders; i++) {
10938 err_printf(m, " CPU transcoder: %c\n",
10939 transcoder_name(error->transcoder[i].cpu_transcoder));
10940 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
10941 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
10942 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
10943 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
10944 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
10945 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
10946 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
10947 }
c4a1d9e4 10948}
Linux kernel - Deliverables
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