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drm/i915: Clean up the CPT DP .get_hw_state() port readout
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c 48/* Primary plane formats for gen <= 3 */
568db4f2 49static const uint32_t i8xx_primary_formats[] = {
67fe7dc5
DL		 50 DRM_FORMAT_C8,
51 DRM_FORMAT_RGB565,
465c120c 52 DRM_FORMAT_XRGB1555,
67fe7dc5 53 DRM_FORMAT_XRGB8888,
465c120c
MR		 54};
55
56/* Primary plane formats for gen >= 4 */
568db4f2 57static const uint32_t i965_primary_formats[] = {
6c0fd451
DL		 58 DRM_FORMAT_C8,
59 DRM_FORMAT_RGB565,
60 DRM_FORMAT_XRGB8888,
61 DRM_FORMAT_XBGR8888,
62 DRM_FORMAT_XRGB2101010,
63 DRM_FORMAT_XBGR2101010,
64};
65
66static const uint32_t skl_primary_formats[] = {
67fe7dc5
DL		 67 DRM_FORMAT_C8,
68 DRM_FORMAT_RGB565,
69 DRM_FORMAT_XRGB8888,
465c120c 70 DRM_FORMAT_XBGR8888,
67fe7dc5 71 DRM_FORMAT_ARGB8888,
465c120c
MR		 72 DRM_FORMAT_ABGR8888,
73 DRM_FORMAT_XRGB2101010,
465c120c 74 DRM_FORMAT_XBGR2101010,
465c120c
MR		 75};
76
3d7d6510
MR		 77/* Cursor formats */
78static const uint32_t intel_cursor_formats[] = {
79 DRM_FORMAT_ARGB8888,
80};
81
6b383a7f 82static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 83
f1f644dc 84static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 85 struct intel_crtc_state *pipe_config);
18442d08 86static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 87 struct intel_crtc_state *pipe_config);
f1f644dc 88
8c7b5ccb 89static int intel_set_mode(struct drm_crtc *crtc,
83a57153 90 struct drm_atomic_state *state);
eb1bfe80
JB		 91static int intel_framebuffer_init(struct drm_device *dev,
92 struct intel_framebuffer *ifb,
93 struct drm_mode_fb_cmd2 *mode_cmd,
94 struct drm_i915_gem_object *obj);
5b18e57c
DV		 95static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
96static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 97static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 98 struct intel_link_m_n *m_n,
99 struct intel_link_m_n *m2_n2);
29407aab 100static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 101static void haswell_set_pipeconf(struct drm_crtc *crtc);
102static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 103static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 104 const struct intel_crtc_state *pipe_config);
d288f65f 105static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 106 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 107static void intel_begin_crtc_commit(struct drm_crtc *crtc);
108static void intel_finish_crtc_commit(struct drm_crtc *crtc);
549e2bfb
CK		 109static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
110 struct intel_crtc_state *crtc_state);
5ab7b0b7
ID		 111static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
112 int num_connectors);
ce22dba9
ML		 113static void intel_crtc_enable_planes(struct drm_crtc *crtc);
114static void intel_crtc_disable_planes(struct drm_crtc *crtc);
e7457a9a 115
0e32b39c
DA		 116static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
117{
118 if (!connector->mst_port)
119 return connector->encoder;
120 else
121 return &connector->mst_port->mst_encoders[pipe]->base;
122}
123
79e53945 124typedef struct {
0206e353 125 int min, max;
79e53945
JB		 126} intel_range_t;
127
128typedef struct {
0206e353
AJ		 129 int dot_limit;
130 int p2_slow, p2_fast;
79e53945
JB		 131} intel_p2_t;
132
d4906093
ML		 133typedef struct intel_limit intel_limit_t;
134struct intel_limit {
0206e353
AJ		 135 intel_range_t dot, vco, n, m, m1, m2, p, p1;
136 intel_p2_t p2;
d4906093 137};
79e53945 138
d2acd215
DV		 139int
140intel_pch_rawclk(struct drm_device *dev)
141{
142 struct drm_i915_private *dev_priv = dev->dev_private;
143
144 WARN_ON(!HAS_PCH_SPLIT(dev));
145
146 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
147}
148
021357ac
CW		 149static inline u32 /* units of 100MHz */
150intel_fdi_link_freq(struct drm_device *dev)
151{
8b99e68c
CW		 152 if (IS_GEN5(dev)) {
153 struct drm_i915_private *dev_priv = dev->dev_private;
154 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
155 } else
156 return 27;
021357ac
CW		 157}
158
5d536e28 159static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 160 .dot = { .min = 25000, .max = 350000 },
9c333719 161 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 162 .n = { .min = 2, .max = 16 },
0206e353
AJ		 163 .m = { .min = 96, .max = 140 },
164 .m1 = { .min = 18, .max = 26 },
165 .m2 = { .min = 6, .max = 16 },
166 .p = { .min = 4, .max = 128 },
167 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 168 .p2 = { .dot_limit = 165000,
169 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 170};
171
5d536e28
DV		 172static const intel_limit_t intel_limits_i8xx_dvo = {
173 .dot = { .min = 25000, .max = 350000 },
9c333719 174 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 175 .n = { .min = 2, .max = 16 },
5d536e28
DV		 176 .m = { .min = 96, .max = 140 },
177 .m1 = { .min = 18, .max = 26 },
178 .m2 = { .min = 6, .max = 16 },
179 .p = { .min = 4, .max = 128 },
180 .p1 = { .min = 2, .max = 33 },
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 4, .p2_fast = 4 },
183};
184
e4b36699 185static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 186 .dot = { .min = 25000, .max = 350000 },
9c333719 187 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 188 .n = { .min = 2, .max = 16 },
0206e353
AJ		 189 .m = { .min = 96, .max = 140 },
190 .m1 = { .min = 18, .max = 26 },
191 .m2 = { .min = 6, .max = 16 },
192 .p = { .min = 4, .max = 128 },
193 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 194 .p2 = { .dot_limit = 165000,
195 .p2_slow = 14, .p2_fast = 7 },
e4b36699 196};
273e27ca 197
e4b36699 198static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 199 .dot = { .min = 20000, .max = 400000 },
200 .vco = { .min = 1400000, .max = 2800000 },
201 .n = { .min = 1, .max = 6 },
202 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 203 .m1 = { .min = 8, .max = 18 },
204 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1400000, .max = 2800000 },
214 .n = { .min = 1, .max = 6 },
215 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 216 .m1 = { .min = 8, .max = 18 },
217 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 218 .p = { .min = 7, .max = 98 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 222};
223
273e27ca 224
e4b36699 225static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 226 .dot = { .min = 25000, .max = 270000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 4 },
229 .m = { .min = 104, .max = 138 },
230 .m1 = { .min = 17, .max = 23 },
231 .m2 = { .min = 5, .max = 11 },
232 .p = { .min = 10, .max = 30 },
233 .p1 = { .min = 1, .max = 3},
234 .p2 = { .dot_limit = 270000,
235 .p2_slow = 10,
236 .p2_fast = 10
044c7c41 237 },
e4b36699
KP		 238};
239
240static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 241 .dot = { .min = 22000, .max = 400000 },
242 .vco = { .min = 1750000, .max = 3500000},
243 .n = { .min = 1, .max = 4 },
244 .m = { .min = 104, .max = 138 },
245 .m1 = { .min = 16, .max = 23 },
246 .m2 = { .min = 5, .max = 11 },
247 .p = { .min = 5, .max = 80 },
248 .p1 = { .min = 1, .max = 8},
249 .p2 = { .dot_limit = 165000,
250 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 251};
252
253static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 254 .dot = { .min = 20000, .max = 115000 },
255 .vco = { .min = 1750000, .max = 3500000 },
256 .n = { .min = 1, .max = 3 },
257 .m = { .min = 104, .max = 138 },
258 .m1 = { .min = 17, .max = 23 },
259 .m2 = { .min = 5, .max = 11 },
260 .p = { .min = 28, .max = 112 },
261 .p1 = { .min = 2, .max = 8 },
262 .p2 = { .dot_limit = 0,
263 .p2_slow = 14, .p2_fast = 14
044c7c41 264 },
e4b36699
KP		 265};
266
267static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 268 .dot = { .min = 80000, .max = 224000 },
269 .vco = { .min = 1750000, .max = 3500000 },
270 .n = { .min = 1, .max = 3 },
271 .m = { .min = 104, .max = 138 },
272 .m1 = { .min = 17, .max = 23 },
273 .m2 = { .min = 5, .max = 11 },
274 .p = { .min = 14, .max = 42 },
275 .p1 = { .min = 2, .max = 6 },
276 .p2 = { .dot_limit = 0,
277 .p2_slow = 7, .p2_fast = 7
044c7c41 278 },
e4b36699
KP		 279};
280
f2b115e6 281static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 282 .dot = { .min = 20000, .max = 400000},
283 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 284 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 285 .n = { .min = 3, .max = 6 },
286 .m = { .min = 2, .max = 256 },
273e27ca 287 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 288 .m1 = { .min = 0, .max = 0 },
289 .m2 = { .min = 0, .max = 254 },
290 .p = { .min = 5, .max = 80 },
291 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 292 .p2 = { .dot_limit = 200000,
293 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 294};
295
f2b115e6 296static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 297 .dot = { .min = 20000, .max = 400000 },
298 .vco = { .min = 1700000, .max = 3500000 },
299 .n = { .min = 3, .max = 6 },
300 .m = { .min = 2, .max = 256 },
301 .m1 = { .min = 0, .max = 0 },
302 .m2 = { .min = 0, .max = 254 },
303 .p = { .min = 7, .max = 112 },
304 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 305 .p2 = { .dot_limit = 112000,
306 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 307};
308
273e27ca
EA		 309/* Ironlake / Sandybridge
310 *
311 * We calculate clock using (register_value + 2) for N/M1/M2, so here
312 * the range value for them is (actual_value - 2).
313 */
b91ad0ec 314static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 315 .dot = { .min = 25000, .max = 350000 },
316 .vco = { .min = 1760000, .max = 3510000 },
317 .n = { .min = 1, .max = 5 },
318 .m = { .min = 79, .max = 127 },
319 .m1 = { .min = 12, .max = 22 },
320 .m2 = { .min = 5, .max = 9 },
321 .p = { .min = 5, .max = 80 },
322 .p1 = { .min = 1, .max = 8 },
323 .p2 = { .dot_limit = 225000,
324 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 325};
326
b91ad0ec 327static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 328 .dot = { .min = 25000, .max = 350000 },
329 .vco = { .min = 1760000, .max = 3510000 },
330 .n = { .min = 1, .max = 3 },
331 .m = { .min = 79, .max = 118 },
332 .m1 = { .min = 12, .max = 22 },
333 .m2 = { .min = 5, .max = 9 },
334 .p = { .min = 28, .max = 112 },
335 .p1 = { .min = 2, .max = 8 },
336 .p2 = { .dot_limit = 225000,
337 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 338};
339
340static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 341 .dot = { .min = 25000, .max = 350000 },
342 .vco = { .min = 1760000, .max = 3510000 },
343 .n = { .min = 1, .max = 3 },
344 .m = { .min = 79, .max = 127 },
345 .m1 = { .min = 12, .max = 22 },
346 .m2 = { .min = 5, .max = 9 },
347 .p = { .min = 14, .max = 56 },
348 .p1 = { .min = 2, .max = 8 },
349 .p2 = { .dot_limit = 225000,
350 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 351};
352
273e27ca 353/* LVDS 100mhz refclk limits. */
b91ad0ec 354static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 355 .dot = { .min = 25000, .max = 350000 },
356 .vco = { .min = 1760000, .max = 3510000 },
357 .n = { .min = 1, .max = 2 },
358 .m = { .min = 79, .max = 126 },
359 .m1 = { .min = 12, .max = 22 },
360 .m2 = { .min = 5, .max = 9 },
361 .p = { .min = 28, .max = 112 },
0206e353 362 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 363 .p2 = { .dot_limit = 225000,
364 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 365};
366
367static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 368 .dot = { .min = 25000, .max = 350000 },
369 .vco = { .min = 1760000, .max = 3510000 },
370 .n = { .min = 1, .max = 3 },
371 .m = { .min = 79, .max = 126 },
372 .m1 = { .min = 12, .max = 22 },
373 .m2 = { .min = 5, .max = 9 },
374 .p = { .min = 14, .max = 42 },
0206e353 375 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 376 .p2 = { .dot_limit = 225000,
377 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 378};
379
dc730512 380static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 381 /*
382 * These are the data rate limits (measured in fast clocks)
383 * since those are the strictest limits we have. The fast
384 * clock and actual rate limits are more relaxed, so checking
385 * them would make no difference.
386 */
387 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 388 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 389 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 390 .m1 = { .min = 2, .max = 3 },
391 .m2 = { .min = 11, .max = 156 },
b99ab663 392 .p1 = { .min = 2, .max = 3 },
5fdc9c49 393 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 394};
395
ef9348c8
CML		 396static const intel_limit_t intel_limits_chv = {
397 /*
398 * These are the data rate limits (measured in fast clocks)
399 * since those are the strictest limits we have. The fast
400 * clock and actual rate limits are more relaxed, so checking
401 * them would make no difference.
402 */
403 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 404 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 405 .n = { .min = 1, .max = 1 },
406 .m1 = { .min = 2, .max = 2 },
407 .m2 = { .min = 24 << 22, .max = 175 << 22 },
408 .p1 = { .min = 2, .max = 4 },
409 .p2 = { .p2_slow = 1, .p2_fast = 14 },
410};
411
5ab7b0b7
ID		 412static const intel_limit_t intel_limits_bxt = {
413 /* FIXME: find real dot limits */
414 .dot = { .min = 0, .max = INT_MAX },
415 .vco = { .min = 4800000, .max = 6480000 },
416 .n = { .min = 1, .max = 1 },
417 .m1 = { .min = 2, .max = 2 },
418 /* FIXME: find real m2 limits */
419 .m2 = { .min = 2 << 22, .max = 255 << 22 },
420 .p1 = { .min = 2, .max = 4 },
421 .p2 = { .p2_slow = 1, .p2_fast = 20 },
422};
423
6b4bf1c4
VS		 424static void vlv_clock(int refclk, intel_clock_t *clock)
425{
426 clock->m = clock->m1 * clock->m2;
427 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 428 if (WARN_ON(clock->n == 0 || clock->p == 0))
429 return;
fb03ac01
VS		 430 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
431 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 432}
433
e0638cdf
PZ		 434/**
435 * Returns whether any output on the specified pipe is of the specified type
436 */
4093561b 437bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 438{
409ee761 439 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 440 struct intel_encoder *encoder;
441
409ee761 442 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 443 if (encoder->type == type)
444 return true;
445
446 return false;
447}
448
d0737e1d
ACO		 449/**
450 * Returns whether any output on the specified pipe will have the specified
451 * type after a staged modeset is complete, i.e., the same as
452 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
453 * encoder->crtc.
454 */
a93e255f
ACO		 455static bool intel_pipe_will_have_type(const struct intel_crtc_state *crtc_state,
456 int type)
d0737e1d 457{
a93e255f 458 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 459 struct drm_connector *connector;
a93e255f 460 struct drm_connector_state *connector_state;
d0737e1d 461 struct intel_encoder *encoder;
a93e255f
ACO		 462 int i, num_connectors = 0;
463
da3ced29 464 for_each_connector_in_state(state, connector, connector_state, i) {
a93e255f
ACO		 465 if (connector_state->crtc != crtc_state->base.crtc)
466 continue;
467
468 num_connectors++;
d0737e1d 469
a93e255f
ACO		 470 encoder = to_intel_encoder(connector_state->best_encoder);
471 if (encoder->type == type)
d0737e1d 472 return true;
a93e255f
ACO		 473 }
474
475 WARN_ON(num_connectors == 0);
d0737e1d
ACO		 476
477 return false;
478}
479
a93e255f
ACO		 480static const intel_limit_t *
481intel_ironlake_limit(struct intel_crtc_state *crtc_state, int refclk)
2c07245f 482{
a93e255f 483 struct drm_device *dev = crtc_state->base.crtc->dev;
2c07245f 484 const intel_limit_t *limit;
b91ad0ec 485
a93e255f 486 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 487 if (intel_is_dual_link_lvds(dev)) {
1b894b59 488 if (refclk == 100000)
b91ad0ec
ZW		 489 limit = &intel_limits_ironlake_dual_lvds_100m;
490 else
491 limit = &intel_limits_ironlake_dual_lvds;
492 } else {
1b894b59 493 if (refclk == 100000)
b91ad0ec
ZW		 494 limit = &intel_limits_ironlake_single_lvds_100m;
495 else
496 limit = &intel_limits_ironlake_single_lvds;
497 }
c6bb3538 498 } else
b91ad0ec 499 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 500
501 return limit;
502}
503
a93e255f
ACO		 504static const intel_limit_t *
505intel_g4x_limit(struct intel_crtc_state *crtc_state)
044c7c41 506{
a93e255f 507 struct drm_device *dev = crtc_state->base.crtc->dev;
044c7c41
ML		 508 const intel_limit_t *limit;
509
a93e255f 510 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 511 if (intel_is_dual_link_lvds(dev))
e4b36699 512 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 513 else
e4b36699 514 limit = &intel_limits_g4x_single_channel_lvds;
a93e255f
ACO		 515 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI) ||
516 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_ANALOG)) {
e4b36699 517 limit = &intel_limits_g4x_hdmi;
a93e255f 518 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO)) {
e4b36699 519 limit = &intel_limits_g4x_sdvo;
044c7c41 520 } else /* The option is for other outputs */
e4b36699 521 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 522
523 return limit;
524}
525
a93e255f
ACO		 526static const intel_limit_t *
527intel_limit(struct intel_crtc_state *crtc_state, int refclk)
79e53945 528{
a93e255f 529 struct drm_device *dev = crtc_state->base.crtc->dev;
79e53945
JB		 530 const intel_limit_t *limit;
531
5ab7b0b7
ID		 532 if (IS_BROXTON(dev))
533 limit = &intel_limits_bxt;
534 else if (HAS_PCH_SPLIT(dev))
a93e255f 535 limit = intel_ironlake_limit(crtc_state, refclk);
2c07245f 536 else if (IS_G4X(dev)) {
a93e255f 537 limit = intel_g4x_limit(crtc_state);
f2b115e6 538 } else if (IS_PINEVIEW(dev)) {
a93e255f 539 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
f2b115e6 540 limit = &intel_limits_pineview_lvds;
2177832f 541 else
f2b115e6 542 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 543 } else if (IS_CHERRYVIEW(dev)) {
544 limit = &intel_limits_chv;
a0c4da24 545 } else if (IS_VALLEYVIEW(dev)) {
dc730512 546 limit = &intel_limits_vlv;
a6c45cf0 547 } else if (!IS_GEN2(dev)) {
a93e255f 548 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 549 limit = &intel_limits_i9xx_lvds;
550 else
551 limit = &intel_limits_i9xx_sdvo;
79e53945 552 } else {
a93e255f 553 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
e4b36699 554 limit = &intel_limits_i8xx_lvds;
a93e255f 555 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
e4b36699 556 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 557 else
558 limit = &intel_limits_i8xx_dac;
79e53945
JB		 559 }
560 return limit;
561}
562
f2b115e6
AJ		 563/* m1 is reserved as 0 in Pineview, n is a ring counter */
564static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 565{
2177832f
SL		 566 clock->m = clock->m2 + 2;
567 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 568 if (WARN_ON(clock->n == 0 || clock->p == 0))
569 return;
fb03ac01
VS		 570 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
571 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 572}
573
7429e9d4
DV		 574static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
575{
576 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
577}
578
ac58c3f0 579static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 580{
7429e9d4 581 clock->m = i9xx_dpll_compute_m(clock);
79e53945 582 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 583 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
584 return;
fb03ac01
VS		 585 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
586 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 587}
588
ef9348c8
CML		 589static void chv_clock(int refclk, intel_clock_t *clock)
590{
591 clock->m = clock->m1 * clock->m2;
592 clock->p = clock->p1 * clock->p2;
593 if (WARN_ON(clock->n == 0 || clock->p == 0))
594 return;
595 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
596 clock->n << 22);
597 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
598}
599
7c04d1d9 600#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 601/**
602 * Returns whether the given set of divisors are valid for a given refclk with
603 * the given connectors.
604 */
605
1b894b59
CW		 606static bool intel_PLL_is_valid(struct drm_device *dev,
607 const intel_limit_t *limit,
608 const intel_clock_t *clock)
79e53945 609{
f01b7962
VS		 610 if (clock->n < limit->n.min || limit->n.max < clock->n)
611 INTELPllInvalid("n out of range\n");
79e53945 612 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 613 INTELPllInvalid("p1 out of range\n");
79e53945 614 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 615 INTELPllInvalid("m2 out of range\n");
79e53945 616 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 617 INTELPllInvalid("m1 out of range\n");
f01b7962 618
5ab7b0b7 619 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
f01b7962
VS		 620 if (clock->m1 <= clock->m2)
621 INTELPllInvalid("m1 <= m2\n");
622
5ab7b0b7 623 if (!IS_VALLEYVIEW(dev) && !IS_BROXTON(dev)) {
f01b7962
VS		 624 if (clock->p < limit->p.min || limit->p.max < clock->p)
625 INTELPllInvalid("p out of range\n");
626 if (clock->m < limit->m.min || limit->m.max < clock->m)
627 INTELPllInvalid("m out of range\n");
628 }
629
79e53945 630 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 631 INTELPllInvalid("vco out of range\n");
79e53945
JB		 632 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
633 * connector, etc., rather than just a single range.
634 */
635 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 636 INTELPllInvalid("dot out of range\n");
79e53945
JB		 637
638 return true;
639}
640
d4906093 641static bool
a93e255f
ACO		 642i9xx_find_best_dpll(const intel_limit_t *limit,
643 struct intel_crtc_state *crtc_state,
cec2f356
SP		 644 int target, int refclk, intel_clock_t *match_clock,
645 intel_clock_t *best_clock)
79e53945 646{
a93e255f 647 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 648 struct drm_device *dev = crtc->base.dev;
79e53945 649 intel_clock_t clock;
79e53945
JB		 650 int err = target;
651
a93e255f 652 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 653 /*
a210b028
DV		 654 * For LVDS just rely on its current settings for dual-channel.
655 * We haven't figured out how to reliably set up different
656 * single/dual channel state, if we even can.
79e53945 657 */
1974cad0 658 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 659 clock.p2 = limit->p2.p2_fast;
660 else
661 clock.p2 = limit->p2.p2_slow;
662 } else {
663 if (target < limit->p2.dot_limit)
664 clock.p2 = limit->p2.p2_slow;
665 else
666 clock.p2 = limit->p2.p2_fast;
667 }
668
0206e353 669 memset(best_clock, 0, sizeof(*best_clock));
79e53945 670
42158660
ZY		 671 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
672 clock.m1++) {
673 for (clock.m2 = limit->m2.min;
674 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 675 if (clock.m2 >= clock.m1)
42158660
ZY		 676 break;
677 for (clock.n = limit->n.min;
678 clock.n <= limit->n.max; clock.n++) {
679 for (clock.p1 = limit->p1.min;
680 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 681 int this_err;
682
ac58c3f0
DV		 683 i9xx_clock(refclk, &clock);
684 if (!intel_PLL_is_valid(dev, limit,
685 &clock))
686 continue;
687 if (match_clock &&
688 clock.p != match_clock->p)
689 continue;
690
691 this_err = abs(clock.dot - target);
692 if (this_err < err) {
693 *best_clock = clock;
694 err = this_err;
695 }
696 }
697 }
698 }
699 }
700
701 return (err != target);
702}
703
704static bool
a93e255f
ACO		 705pnv_find_best_dpll(const intel_limit_t *limit,
706 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 707 int target, int refclk, intel_clock_t *match_clock,
708 intel_clock_t *best_clock)
79e53945 709{
a93e255f 710 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 711 struct drm_device *dev = crtc->base.dev;
79e53945 712 intel_clock_t clock;
79e53945
JB		 713 int err = target;
714
a93e255f 715 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
79e53945 716 /*
a210b028
DV		 717 * For LVDS just rely on its current settings for dual-channel.
718 * We haven't figured out how to reliably set up different
719 * single/dual channel state, if we even can.
79e53945 720 */
1974cad0 721 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 722 clock.p2 = limit->p2.p2_fast;
723 else
724 clock.p2 = limit->p2.p2_slow;
725 } else {
726 if (target < limit->p2.dot_limit)
727 clock.p2 = limit->p2.p2_slow;
728 else
729 clock.p2 = limit->p2.p2_fast;
730 }
731
0206e353 732 memset(best_clock, 0, sizeof(*best_clock));
79e53945 733
42158660
ZY		 734 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
735 clock.m1++) {
736 for (clock.m2 = limit->m2.min;
737 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 738 for (clock.n = limit->n.min;
739 clock.n <= limit->n.max; clock.n++) {
740 for (clock.p1 = limit->p1.min;
741 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 742 int this_err;
743
ac58c3f0 744 pineview_clock(refclk, &clock);
1b894b59
CW		 745 if (!intel_PLL_is_valid(dev, limit,
746 &clock))
79e53945 747 continue;
cec2f356
SP		 748 if (match_clock &&
749 clock.p != match_clock->p)
750 continue;
79e53945
JB		 751
752 this_err = abs(clock.dot - target);
753 if (this_err < err) {
754 *best_clock = clock;
755 err = this_err;
756 }
757 }
758 }
759 }
760 }
761
762 return (err != target);
763}
764
d4906093 765static bool
a93e255f
ACO		 766g4x_find_best_dpll(const intel_limit_t *limit,
767 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 768 int target, int refclk, intel_clock_t *match_clock,
769 intel_clock_t *best_clock)
d4906093 770{
a93e255f 771 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 772 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 773 intel_clock_t clock;
774 int max_n;
775 bool found;
6ba770dc
AJ		 776 /* approximately equals target * 0.00585 */
777 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 778 found = false;
779
a93e255f 780 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
1974cad0 781 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 782 clock.p2 = limit->p2.p2_fast;
783 else
784 clock.p2 = limit->p2.p2_slow;
785 } else {
786 if (target < limit->p2.dot_limit)
787 clock.p2 = limit->p2.p2_slow;
788 else
789 clock.p2 = limit->p2.p2_fast;
790 }
791
792 memset(best_clock, 0, sizeof(*best_clock));
793 max_n = limit->n.max;
f77f13e2 794 /* based on hardware requirement, prefer smaller n to precision */
d4906093 795 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 796 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 797 for (clock.m1 = limit->m1.max;
798 clock.m1 >= limit->m1.min; clock.m1--) {
799 for (clock.m2 = limit->m2.max;
800 clock.m2 >= limit->m2.min; clock.m2--) {
801 for (clock.p1 = limit->p1.max;
802 clock.p1 >= limit->p1.min; clock.p1--) {
803 int this_err;
804
ac58c3f0 805 i9xx_clock(refclk, &clock);
1b894b59
CW		 806 if (!intel_PLL_is_valid(dev, limit,
807 &clock))
d4906093 808 continue;
1b894b59
CW		 809
810 this_err = abs(clock.dot - target);
d4906093
ML		 811 if (this_err < err_most) {
812 *best_clock = clock;
813 err_most = this_err;
814 max_n = clock.n;
815 found = true;
816 }
817 }
818 }
819 }
820 }
2c07245f
ZW		 821 return found;
822}
823
d5dd62bd
ID		 824/*
825 * Check if the calculated PLL configuration is more optimal compared to the
826 * best configuration and error found so far. Return the calculated error.
827 */
828static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
829 const intel_clock_t *calculated_clock,
830 const intel_clock_t *best_clock,
831 unsigned int best_error_ppm,
832 unsigned int *error_ppm)
833{
9ca3ba01
ID		 834 /*
835 * For CHV ignore the error and consider only the P value.
836 * Prefer a bigger P value based on HW requirements.
837 */
838 if (IS_CHERRYVIEW(dev)) {
839 *error_ppm = 0;
840
841 return calculated_clock->p > best_clock->p;
842 }
843
24be4e46
ID		 844 if (WARN_ON_ONCE(!target_freq))
845 return false;
846
d5dd62bd
ID		 847 *error_ppm = div_u64(1000000ULL *
848 abs(target_freq - calculated_clock->dot),
849 target_freq);
850 /*
851 * Prefer a better P value over a better (smaller) error if the error
852 * is small. Ensure this preference for future configurations too by
853 * setting the error to 0.
854 */
855 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
856 *error_ppm = 0;
857
858 return true;
859 }
860
861 return *error_ppm + 10 < best_error_ppm;
862}
863
a0c4da24 864static bool
a93e255f
ACO		 865vlv_find_best_dpll(const intel_limit_t *limit,
866 struct intel_crtc_state *crtc_state,
ee9300bb
DV		 867 int target, int refclk, intel_clock_t *match_clock,
868 intel_clock_t *best_clock)
a0c4da24 869{
a93e255f 870 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 871 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 872 intel_clock_t clock;
69e4f900 873 unsigned int bestppm = 1000000;
27e639bf
VS		 874 /* min update 19.2 MHz */
875 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 876 bool found = false;
a0c4da24 877
6b4bf1c4
VS		 878 target *= 5; /* fast clock */
879
880 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 881
882 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 883 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 884 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 885 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 886 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 887 clock.p = clock.p1 * clock.p2;
a0c4da24 888 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 889 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 890 unsigned int ppm;
69e4f900 891
6b4bf1c4
VS		 892 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
893 refclk * clock.m1);
894
895 vlv_clock(refclk, &clock);
43b0ac53 896
f01b7962
VS		 897 if (!intel_PLL_is_valid(dev, limit,
898 &clock))
43b0ac53
VS		 899 continue;
900
d5dd62bd
ID		 901 if (!vlv_PLL_is_optimal(dev, target,
902 &clock,
903 best_clock,
904 bestppm, &ppm))
905 continue;
6b4bf1c4 906
d5dd62bd
ID		 907 *best_clock = clock;
908 bestppm = ppm;
909 found = true;
a0c4da24
JB		 910 }
911 }
912 }
913 }
a0c4da24 914
49e497ef 915 return found;
a0c4da24 916}
a4fc5ed6 917
ef9348c8 918static bool
a93e255f
ACO		 919chv_find_best_dpll(const intel_limit_t *limit,
920 struct intel_crtc_state *crtc_state,
ef9348c8
CML		 921 int target, int refclk, intel_clock_t *match_clock,
922 intel_clock_t *best_clock)
923{
a93e255f 924 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
a919ff14 925 struct drm_device *dev = crtc->base.dev;
9ca3ba01 926 unsigned int best_error_ppm;
ef9348c8
CML		 927 intel_clock_t clock;
928 uint64_t m2;
929 int found = false;
930
931 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 932 best_error_ppm = 1000000;
ef9348c8
CML		 933
934 /*
935 * Based on hardware doc, the n always set to 1, and m1 always
936 * set to 2. If requires to support 200Mhz refclk, we need to
937 * revisit this because n may not 1 anymore.
938 */
939 clock.n = 1, clock.m1 = 2;
940 target *= 5; /* fast clock */
941
942 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
943 for (clock.p2 = limit->p2.p2_fast;
944 clock.p2 >= limit->p2.p2_slow;
945 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 946 unsigned int error_ppm;
ef9348c8
CML		 947
948 clock.p = clock.p1 * clock.p2;
949
950 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
951 clock.n) << 22, refclk * clock.m1);
952
953 if (m2 > INT_MAX/clock.m1)
954 continue;
955
956 clock.m2 = m2;
957
958 chv_clock(refclk, &clock);
959
960 if (!intel_PLL_is_valid(dev, limit, &clock))
961 continue;
962
9ca3ba01
ID		 963 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
964 best_error_ppm, &error_ppm))
965 continue;
966
967 *best_clock = clock;
968 best_error_ppm = error_ppm;
969 found = true;
ef9348c8
CML		 970 }
971 }
972
973 return found;
974}
975
5ab7b0b7
ID		 976bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, int target_clock,
977 intel_clock_t *best_clock)
978{
979 int refclk = i9xx_get_refclk(crtc_state, 0);
980
981 return chv_find_best_dpll(intel_limit(crtc_state, refclk), crtc_state,
982 target_clock, refclk, NULL, best_clock);
983}
984
20ddf665
VS		 985bool intel_crtc_active(struct drm_crtc *crtc)
986{
987 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
988
989 /* Be paranoid as we can arrive here with only partial
990 * state retrieved from the hardware during setup.
991 *
241bfc38 992 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 993 * as Haswell has gained clock readout/fastboot support.
994 *
66e514c1 995 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 996 * properly reconstruct framebuffers.
c3d1f436
MR		 997 *
998 * FIXME: The intel_crtc->active here should be switched to
999 * crtc->state->active once we have proper CRTC states wired up
1000 * for atomic.
20ddf665 1001 */
c3d1f436 1002 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 1003 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 1004}
1005
a5c961d1
PZ		 1006enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
1007 enum pipe pipe)
1008{
1009 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1010 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011
6e3c9717 1012 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 1013}
1014
fbf49ea2
VS		 1015static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
1016{
1017 struct drm_i915_private *dev_priv = dev->dev_private;
1018 u32 reg = PIPEDSL(pipe);
1019 u32 line1, line2;
1020 u32 line_mask;
1021
1022 if (IS_GEN2(dev))
1023 line_mask = DSL_LINEMASK_GEN2;
1024 else
1025 line_mask = DSL_LINEMASK_GEN3;
1026
1027 line1 = I915_READ(reg) & line_mask;
1028 mdelay(5);
1029 line2 = I915_READ(reg) & line_mask;
1030
1031 return line1 == line2;
1032}
1033
ab7ad7f6
KP		 1034/*
1035 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 1036 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 1037 *
1038 * After disabling a pipe, we can't wait for vblank in the usual way,
1039 * spinning on the vblank interrupt status bit, since we won't actually
1040 * see an interrupt when the pipe is disabled.
1041 *
ab7ad7f6
KP		 1042 * On Gen4 and above:
1043 * wait for the pipe register state bit to turn off
1044 *
1045 * Otherwise:
1046 * wait for the display line value to settle (it usually
1047 * ends up stopping at the start of the next frame).
58e10eb9 1048 *
9d0498a2 1049 */
575f7ab7 1050static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 1051{
575f7ab7 1052 struct drm_device *dev = crtc->base.dev;
9d0498a2 1053 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 1054 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 1055 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 1056
1057 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1058 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1059
1060 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1061 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1062 100))
284637d9 1063 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1064 } else {
ab7ad7f6 1065 /* Wait for the display line to settle */
fbf49ea2 1066 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1067 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1068 }
79e53945
JB		 1069}
1070
b0ea7d37
DL		 1071/*
1072 * ibx_digital_port_connected - is the specified port connected?
1073 * @dev_priv: i915 private structure
1074 * @port: the port to test
1075 *
1076 * Returns true if @port is connected, false otherwise.
1077 */
1078bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1079 struct intel_digital_port *port)
1080{
1081 u32 bit;
1082
c36346e3 1083 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1084 switch (port->port) {
c36346e3
DL		 1085 case PORT_B:
1086 bit = SDE_PORTB_HOTPLUG;
1087 break;
1088 case PORT_C:
1089 bit = SDE_PORTC_HOTPLUG;
1090 break;
1091 case PORT_D:
1092 bit = SDE_PORTD_HOTPLUG;
1093 break;
1094 default:
1095 return true;
1096 }
1097 } else {
eba905b2 1098 switch (port->port) {
c36346e3
DL		 1099 case PORT_B:
1100 bit = SDE_PORTB_HOTPLUG_CPT;
1101 break;
1102 case PORT_C:
1103 bit = SDE_PORTC_HOTPLUG_CPT;
1104 break;
1105 case PORT_D:
1106 bit = SDE_PORTD_HOTPLUG_CPT;
1107 break;
1108 default:
1109 return true;
1110 }
b0ea7d37
DL		 1111 }
1112
1113 return I915_READ(SDEISR) & bit;
1114}
1115
b24e7179
JB		 1116static const char *state_string(bool enabled)
1117{
1118 return enabled ? "on" : "off";
1119}
1120
1121/* Only for pre-ILK configs */
55607e8a
DV		 1122void assert_pll(struct drm_i915_private *dev_priv,
1123 enum pipe pipe, bool state)
b24e7179
JB		 1124{
1125 int reg;
1126 u32 val;
1127 bool cur_state;
1128
1129 reg = DPLL(pipe);
1130 val = I915_READ(reg);
1131 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1132 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1133 "PLL state assertion failure (expected %s, current %s)\n",
1134 state_string(state), state_string(cur_state));
1135}
b24e7179 1136
23538ef1
JN		 1137/* XXX: the dsi pll is shared between MIPI DSI ports */
1138static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1139{
1140 u32 val;
1141 bool cur_state;
1142
1143 mutex_lock(&dev_priv->dpio_lock);
1144 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1145 mutex_unlock(&dev_priv->dpio_lock);
1146
1147 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1148 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1149 "DSI PLL state assertion failure (expected %s, current %s)\n",
1150 state_string(state), state_string(cur_state));
1151}
1152#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1153#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1154
55607e8a 1155struct intel_shared_dpll *
e2b78267
DV		 1156intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1157{
1158 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1159
6e3c9717 1160 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1161 return NULL;
1162
6e3c9717 1163 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1164}
1165
040484af 1166/* For ILK+ */
55607e8a
DV		 1167void assert_shared_dpll(struct drm_i915_private *dev_priv,
1168 struct intel_shared_dpll *pll,
1169 bool state)
040484af 1170{
040484af 1171 bool cur_state;
5358901f 1172 struct intel_dpll_hw_state hw_state;
040484af 1173
92b27b08 1174 if (WARN (!pll,
46edb027 1175 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1176 return;
ee7b9f93 1177
5358901f 1178 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1179 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1180 "%s assertion failure (expected %s, current %s)\n",
1181 pll->name, state_string(state), state_string(cur_state));
040484af 1182}
040484af
JB		 1183
1184static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1185 enum pipe pipe, bool state)
1186{
1187 int reg;
1188 u32 val;
1189 bool cur_state;
ad80a810
PZ		 1190 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1191 pipe);
040484af 1192
affa9354
PZ		 1193 if (HAS_DDI(dev_priv->dev)) {
1194 /* DDI does not have a specific FDI_TX register */
ad80a810 1195 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1196 val = I915_READ(reg);
ad80a810 1197 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1198 } else {
1199 reg = FDI_TX_CTL(pipe);
1200 val = I915_READ(reg);
1201 cur_state = !!(val & FDI_TX_ENABLE);
1202 }
e2c719b7 1203 I915_STATE_WARN(cur_state != state,
040484af
JB		 1204 "FDI TX state assertion failure (expected %s, current %s)\n",
1205 state_string(state), state_string(cur_state));
1206}
1207#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1208#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1209
1210static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1211 enum pipe pipe, bool state)
1212{
1213 int reg;
1214 u32 val;
1215 bool cur_state;
1216
d63fa0dc
PZ		 1217 reg = FDI_RX_CTL(pipe);
1218 val = I915_READ(reg);
1219 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1220 I915_STATE_WARN(cur_state != state,
040484af
JB		 1221 "FDI RX state assertion failure (expected %s, current %s)\n",
1222 state_string(state), state_string(cur_state));
1223}
1224#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1225#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1226
1227static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1228 enum pipe pipe)
1229{
1230 int reg;
1231 u32 val;
1232
1233 /* ILK FDI PLL is always enabled */
3d13ef2e 1234 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1235 return;
1236
bf507ef7 1237 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1238 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1239 return;
1240
040484af
JB		 1241 reg = FDI_TX_CTL(pipe);
1242 val = I915_READ(reg);
e2c719b7 1243 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1244}
1245
55607e8a
DV		 1246void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1247 enum pipe pipe, bool state)
040484af
JB		 1248{
1249 int reg;
1250 u32 val;
55607e8a 1251 bool cur_state;
040484af
JB		 1252
1253 reg = FDI_RX_CTL(pipe);
1254 val = I915_READ(reg);
55607e8a 1255 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1256 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1257 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1258 state_string(state), state_string(cur_state));
040484af
JB		 1259}
1260
b680c37a
DV		 1261void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1262 enum pipe pipe)
ea0760cf 1263{
bedd4dba
JN		 1264 struct drm_device *dev = dev_priv->dev;
1265 int pp_reg;
ea0760cf
JB		 1266 u32 val;
1267 enum pipe panel_pipe = PIPE_A;
0de3b485 1268 bool locked = true;
ea0760cf 1269
bedd4dba
JN		 1270 if (WARN_ON(HAS_DDI(dev)))
1271 return;
1272
1273 if (HAS_PCH_SPLIT(dev)) {
1274 u32 port_sel;
1275
ea0760cf 1276 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1277 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1278
1279 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1280 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1281 panel_pipe = PIPE_B;
1282 /* XXX: else fix for eDP */
1283 } else if (IS_VALLEYVIEW(dev)) {
1284 /* presumably write lock depends on pipe, not port select */
1285 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1286 panel_pipe = pipe;
ea0760cf
JB		 1287 } else {
1288 pp_reg = PP_CONTROL;
bedd4dba
JN		 1289 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1290 panel_pipe = PIPE_B;
ea0760cf
JB		 1291 }
1292
1293 val = I915_READ(pp_reg);
1294 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1295 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1296 locked = false;
1297
e2c719b7 1298 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1299 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1300 pipe_name(pipe));
ea0760cf
JB		 1301}
1302
93ce0ba6
JN		 1303static void assert_cursor(struct drm_i915_private *dev_priv,
1304 enum pipe pipe, bool state)
1305{
1306 struct drm_device *dev = dev_priv->dev;
1307 bool cur_state;
1308
d9d82081 1309 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1310 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1311 else
5efb3e28 1312 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1313
e2c719b7 1314 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1315 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1316 pipe_name(pipe), state_string(state), state_string(cur_state));
1317}
1318#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1319#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1320
b840d907
JB		 1321void assert_pipe(struct drm_i915_private *dev_priv,
1322 enum pipe pipe, bool state)
b24e7179
JB		 1323{
1324 int reg;
1325 u32 val;
63d7bbe9 1326 bool cur_state;
702e7a56
PZ		 1327 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1328 pipe);
b24e7179 1329
b6b5d049
VS		 1330 /* if we need the pipe quirk it must be always on */
1331 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1332 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1333 state = true;
1334
f458ebbc 1335 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1336 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1337 cur_state = false;
1338 } else {
1339 reg = PIPECONF(cpu_transcoder);
1340 val = I915_READ(reg);
1341 cur_state = !!(val & PIPECONF_ENABLE);
1342 }
1343
e2c719b7 1344 I915_STATE_WARN(cur_state != state,
63d7bbe9 1345 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1346 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1347}
1348
931872fc
CW		 1349static void assert_plane(struct drm_i915_private *dev_priv,
1350 enum plane plane, bool state)
b24e7179
JB		 1351{
1352 int reg;
1353 u32 val;
931872fc 1354 bool cur_state;
b24e7179
JB		 1355
1356 reg = DSPCNTR(plane);
1357 val = I915_READ(reg);
931872fc 1358 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1359 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1360 "plane %c assertion failure (expected %s, current %s)\n",
1361 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1362}
1363
931872fc
CW		 1364#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1365#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1366
b24e7179
JB		 1367static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1368 enum pipe pipe)
1369{
653e1026 1370 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1371 int reg, i;
1372 u32 val;
1373 int cur_pipe;
1374
653e1026
VS		 1375 /* Primary planes are fixed to pipes on gen4+ */
1376 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1377 reg = DSPCNTR(pipe);
1378 val = I915_READ(reg);
e2c719b7 1379 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1380 "plane %c assertion failure, should be disabled but not\n",
1381 plane_name(pipe));
19ec1358 1382 return;
28c05794 1383 }
19ec1358 1384
b24e7179 1385 /* Need to check both planes against the pipe */
055e393f 1386 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1387 reg = DSPCNTR(i);
1388 val = I915_READ(reg);
1389 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1390 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1391 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1392 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1393 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1394 }
1395}
1396
19332d7a
JB		 1397static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1398 enum pipe pipe)
1399{
20674eef 1400 struct drm_device *dev = dev_priv->dev;
1fe47785 1401 int reg, sprite;
19332d7a
JB		 1402 u32 val;
1403
7feb8b88 1404 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1405 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1406 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1407 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1408 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1409 sprite, pipe_name(pipe));
1410 }
1411 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1412 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1413 reg = SPCNTR(pipe, sprite);
20674eef 1414 val = I915_READ(reg);
e2c719b7 1415 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1416 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1417 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1418 }
1419 } else if (INTEL_INFO(dev)->gen >= 7) {
1420 reg = SPRCTL(pipe);
19332d7a 1421 val = I915_READ(reg);
e2c719b7 1422 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1423 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1424 plane_name(pipe), pipe_name(pipe));
1425 } else if (INTEL_INFO(dev)->gen >= 5) {
1426 reg = DVSCNTR(pipe);
19332d7a 1427 val = I915_READ(reg);
e2c719b7 1428 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1429 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1430 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1431 }
1432}
1433
08c71e5e
VS		 1434static void assert_vblank_disabled(struct drm_crtc *crtc)
1435{
e2c719b7 1436 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1437 drm_crtc_vblank_put(crtc);
1438}
1439
89eff4be 1440static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1441{
1442 u32 val;
1443 bool enabled;
1444
e2c719b7 1445 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1446
92f2584a
JB		 1447 val = I915_READ(PCH_DREF_CONTROL);
1448 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1449 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1450 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1451}
1452
ab9412ba
DV		 1453static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1454 enum pipe pipe)
92f2584a
JB		 1455{
1456 int reg;
1457 u32 val;
1458 bool enabled;
1459
ab9412ba 1460 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1461 val = I915_READ(reg);
1462 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1463 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1464 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1465 pipe_name(pipe));
92f2584a
JB		 1466}
1467
4e634389
KP		 1468static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1469 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1470{
1471 if ((val & DP_PORT_EN) == 0)
1472 return false;
1473
1474 if (HAS_PCH_CPT(dev_priv->dev)) {
1475 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1476 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1477 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1478 return false;
44f37d1f
CML		 1479 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1480 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1481 return false;
f0575e92
KP		 1482 } else {
1483 if ((val & DP_PIPE_MASK) != (pipe << 30))
1484 return false;
1485 }
1486 return true;
1487}
1488
1519b995
KP		 1489static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1490 enum pipe pipe, u32 val)
1491{
dc0fa718 1492 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1493 return false;
1494
1495 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1496 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1497 return false;
44f37d1f
CML		 1498 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1499 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1500 return false;
1519b995 1501 } else {
dc0fa718 1502 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1503 return false;
1504 }
1505 return true;
1506}
1507
1508static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1509 enum pipe pipe, u32 val)
1510{
1511 if ((val & LVDS_PORT_EN) == 0)
1512 return false;
1513
1514 if (HAS_PCH_CPT(dev_priv->dev)) {
1515 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1516 return false;
1517 } else {
1518 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1519 return false;
1520 }
1521 return true;
1522}
1523
1524static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1525 enum pipe pipe, u32 val)
1526{
1527 if ((val & ADPA_DAC_ENABLE) == 0)
1528 return false;
1529 if (HAS_PCH_CPT(dev_priv->dev)) {
1530 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1531 return false;
1532 } else {
1533 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1534 return false;
1535 }
1536 return true;
1537}
1538
291906f1 1539static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1540 enum pipe pipe, int reg, u32 port_sel)
291906f1 1541{
47a05eca 1542 u32 val = I915_READ(reg);
e2c719b7 1543 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1544 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1545 reg, pipe_name(pipe));
de9a35ab 1546
e2c719b7 1547 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1548 && (val & DP_PIPEB_SELECT),
de9a35ab 1549 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1550}
1551
1552static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1553 enum pipe pipe, int reg)
1554{
47a05eca 1555 u32 val = I915_READ(reg);
e2c719b7 1556 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1557 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1558 reg, pipe_name(pipe));
de9a35ab 1559
e2c719b7 1560 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1561 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1562 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1563}
1564
1565static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1566 enum pipe pipe)
1567{
1568 int reg;
1569 u32 val;
291906f1 1570
f0575e92
KP		 1571 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1572 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1573 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1574
1575 reg = PCH_ADPA;
1576 val = I915_READ(reg);
e2c719b7 1577 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1578 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1579 pipe_name(pipe));
291906f1
JB		 1580
1581 reg = PCH_LVDS;
1582 val = I915_READ(reg);
e2c719b7 1583 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1584 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1585 pipe_name(pipe));
291906f1 1586
e2debe91
PZ		 1587 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1588 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1589 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1590}
1591
40e9cf64
JB		 1592static void intel_init_dpio(struct drm_device *dev)
1593{
1594 struct drm_i915_private *dev_priv = dev->dev_private;
1595
1596 if (!IS_VALLEYVIEW(dev))
1597 return;
1598
a09caddd
CML		 1599 /*
1600 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1601 * CHV x1 PHY (DP/HDMI D)
1602 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1603 */
1604 if (IS_CHERRYVIEW(dev)) {
1605 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1606 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1607 } else {
1608 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1609 }
5382f5f3
JB		 1610}
1611
d288f65f 1612static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1613 const struct intel_crtc_state *pipe_config)
87442f73 1614{
426115cf
DV		 1615 struct drm_device *dev = crtc->base.dev;
1616 struct drm_i915_private *dev_priv = dev->dev_private;
1617 int reg = DPLL(crtc->pipe);
d288f65f 1618 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1619
426115cf 1620 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1621
1622 /* No really, not for ILK+ */
1623 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1624
1625 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1626 if (IS_MOBILE(dev_priv->dev))
426115cf 1627 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1628
426115cf
DV		 1629 I915_WRITE(reg, dpll);
1630 POSTING_READ(reg);
1631 udelay(150);
1632
1633 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1634 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1635
d288f65f 1636 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1637 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1638
1639 /* We do this three times for luck */
426115cf 1640 I915_WRITE(reg, dpll);
87442f73
DV		 1641 POSTING_READ(reg);
1642 udelay(150); /* wait for warmup */
426115cf 1643 I915_WRITE(reg, dpll);
87442f73
DV		 1644 POSTING_READ(reg);
1645 udelay(150); /* wait for warmup */
426115cf 1646 I915_WRITE(reg, dpll);
87442f73
DV		 1647 POSTING_READ(reg);
1648 udelay(150); /* wait for warmup */
1649}
1650
d288f65f 1651static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1652 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1653{
1654 struct drm_device *dev = crtc->base.dev;
1655 struct drm_i915_private *dev_priv = dev->dev_private;
1656 int pipe = crtc->pipe;
1657 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1658 u32 tmp;
1659
1660 assert_pipe_disabled(dev_priv, crtc->pipe);
1661
1662 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1663
1664 mutex_lock(&dev_priv->dpio_lock);
1665
1666 /* Enable back the 10bit clock to display controller */
1667 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1668 tmp |= DPIO_DCLKP_EN;
1669 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1670
1671 /*
1672 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1673 */
1674 udelay(1);
1675
1676 /* Enable PLL */
d288f65f 1677 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1678
1679 /* Check PLL is locked */
a11b0703 1680 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1681 DRM_ERROR("PLL %d failed to lock\n", pipe);
1682
a11b0703 1683 /* not sure when this should be written */
d288f65f 1684 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703
VS		 1685 POSTING_READ(DPLL_MD(pipe));
1686
9d556c99
CML		 1687 mutex_unlock(&dev_priv->dpio_lock);
1688}
1689
1c4e0274
VS		 1690static int intel_num_dvo_pipes(struct drm_device *dev)
1691{
1692 struct intel_crtc *crtc;
1693 int count = 0;
1694
1695 for_each_intel_crtc(dev, crtc)
1696 count += crtc->active &&
409ee761 1697 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1698
1699 return count;
1700}
1701
66e3d5c0 1702static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1703{
66e3d5c0
DV		 1704 struct drm_device *dev = crtc->base.dev;
1705 struct drm_i915_private *dev_priv = dev->dev_private;
1706 int reg = DPLL(crtc->pipe);
6e3c9717 1707 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1708
66e3d5c0 1709 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1710
63d7bbe9 1711 /* No really, not for ILK+ */
3d13ef2e 1712 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1713
1714 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1715 if (IS_MOBILE(dev) && !IS_I830(dev))
1716 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1717
1c4e0274
VS		 1718 /* Enable DVO 2x clock on both PLLs if necessary */
1719 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1720 /*
1721 * It appears to be important that we don't enable this
1722 * for the current pipe before otherwise configuring the
1723 * PLL. No idea how this should be handled if multiple
1724 * DVO outputs are enabled simultaneosly.
1725 */
1726 dpll |= DPLL_DVO_2X_MODE;
1727 I915_WRITE(DPLL(!crtc->pipe),
1728 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1729 }
66e3d5c0
DV		 1730
1731 /* Wait for the clocks to stabilize. */
1732 POSTING_READ(reg);
1733 udelay(150);
1734
1735 if (INTEL_INFO(dev)->gen >= 4) {
1736 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1737 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1738 } else {
1739 /* The pixel multiplier can only be updated once the
1740 * DPLL is enabled and the clocks are stable.
1741 *
1742 * So write it again.
1743 */
1744 I915_WRITE(reg, dpll);
1745 }
63d7bbe9
JB		 1746
1747 /* We do this three times for luck */
66e3d5c0 1748 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1749 POSTING_READ(reg);
1750 udelay(150); /* wait for warmup */
66e3d5c0 1751 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1752 POSTING_READ(reg);
1753 udelay(150); /* wait for warmup */
66e3d5c0 1754 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1755 POSTING_READ(reg);
1756 udelay(150); /* wait for warmup */
1757}
1758
1759/**
50b44a44 1760 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1761 * @dev_priv: i915 private structure
1762 * @pipe: pipe PLL to disable
1763 *
1764 * Disable the PLL for @pipe, making sure the pipe is off first.
1765 *
1766 * Note! This is for pre-ILK only.
1767 */
1c4e0274 1768static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1769{
1c4e0274
VS		 1770 struct drm_device *dev = crtc->base.dev;
1771 struct drm_i915_private *dev_priv = dev->dev_private;
1772 enum pipe pipe = crtc->pipe;
1773
1774 /* Disable DVO 2x clock on both PLLs if necessary */
1775 if (IS_I830(dev) &&
409ee761 1776 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1777 intel_num_dvo_pipes(dev) == 1) {
1778 I915_WRITE(DPLL(PIPE_B),
1779 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1780 I915_WRITE(DPLL(PIPE_A),
1781 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1782 }
1783
b6b5d049
VS		 1784 /* Don't disable pipe or pipe PLLs if needed */
1785 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1786 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1787 return;
1788
1789 /* Make sure the pipe isn't still relying on us */
1790 assert_pipe_disabled(dev_priv, pipe);
1791
50b44a44
DV		 1792 I915_WRITE(DPLL(pipe), 0);
1793 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1794}
1795
f6071166
JB		 1796static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1797{
1798 u32 val = 0;
1799
1800 /* Make sure the pipe isn't still relying on us */
1801 assert_pipe_disabled(dev_priv, pipe);
1802
e5cbfbfb
ID		 1803 /*
1804 * Leave integrated clock source and reference clock enabled for pipe B.
1805 * The latter is needed for VGA hotplug / manual detection.
1806 */
f6071166 1807 if (pipe == PIPE_B)
e5cbfbfb 1808 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1809 I915_WRITE(DPLL(pipe), val);
1810 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1811
1812}
1813
1814static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1815{
d752048d 1816 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1817 u32 val;
1818
a11b0703
VS		 1819 /* Make sure the pipe isn't still relying on us */
1820 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1821
a11b0703 1822 /* Set PLL en = 0 */
d17ec4ce 1823 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1824 if (pipe != PIPE_A)
1825 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1826 I915_WRITE(DPLL(pipe), val);
1827 POSTING_READ(DPLL(pipe));
d752048d
VS		 1828
1829 mutex_lock(&dev_priv->dpio_lock);
1830
1831 /* Disable 10bit clock to display controller */
1832 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1833 val &= ~DPIO_DCLKP_EN;
1834 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1835
61407f6d
VS		 1836 /* disable left/right clock distribution */
1837 if (pipe != PIPE_B) {
1838 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1839 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1840 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1841 } else {
1842 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1843 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1844 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1845 }
1846
d752048d 1847 mutex_unlock(&dev_priv->dpio_lock);
f6071166
JB		 1848}
1849
e4607fcf 1850void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
9b6de0a1
VS		 1851 struct intel_digital_port *dport,
1852 unsigned int expected_mask)
89b667f8
JB		 1853{
1854 u32 port_mask;
00fc31b7 1855 int dpll_reg;
89b667f8 1856
e4607fcf
CML		 1857 switch (dport->port) {
1858 case PORT_B:
89b667f8 1859 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1860 dpll_reg = DPLL(0);
e4607fcf
CML		 1861 break;
1862 case PORT_C:
89b667f8 1863 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7 1864 dpll_reg = DPLL(0);
9b6de0a1 1865 expected_mask <<= 4;
00fc31b7
CML		 1866 break;
1867 case PORT_D:
1868 port_mask = DPLL_PORTD_READY_MASK;
1869 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1870 break;
1871 default:
1872 BUG();
1873 }
89b667f8 1874
9b6de0a1
VS		 1875 if (wait_for((I915_READ(dpll_reg) & port_mask) == expected_mask, 1000))
1876 WARN(1, "timed out waiting for port %c ready: got 0x%x, expected 0x%x\n",
1877 port_name(dport->port), I915_READ(dpll_reg) & port_mask, expected_mask);
89b667f8
JB		 1878}
1879
b14b1055
DV		 1880static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1881{
1882 struct drm_device *dev = crtc->base.dev;
1883 struct drm_i915_private *dev_priv = dev->dev_private;
1884 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1885
be19f0ff
CW		 1886 if (WARN_ON(pll == NULL))
1887 return;
1888
3e369b76 1889 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1890 if (pll->active == 0) {
1891 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1892 WARN_ON(pll->on);
1893 assert_shared_dpll_disabled(dev_priv, pll);
1894
1895 pll->mode_set(dev_priv, pll);
1896 }
1897}
1898
92f2584a 1899/**
85b3894f 1900 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1901 * @dev_priv: i915 private structure
1902 * @pipe: pipe PLL to enable
1903 *
1904 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1905 * drives the transcoder clock.
1906 */
85b3894f 1907static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1908{
3d13ef2e
DL		 1909 struct drm_device *dev = crtc->base.dev;
1910 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1911 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1912
87a875bb 1913 if (WARN_ON(pll == NULL))
48da64a8
CW		 1914 return;
1915
3e369b76 1916 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1917 return;
ee7b9f93 1918
74dd6928 1919 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1920 pll->name, pll->active, pll->on,
e2b78267 1921 crtc->base.base.id);
92f2584a 1922
cdbd2316
DV		 1923 if (pll->active++) {
1924 WARN_ON(!pll->on);
e9d6944e 1925 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1926 return;
1927 }
f4a091c7 1928 WARN_ON(pll->on);
ee7b9f93 1929
bd2bb1b9
PZ		 1930 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1931
46edb027 1932 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1933 pll->enable(dev_priv, pll);
ee7b9f93 1934 pll->on = true;
92f2584a
JB		 1935}
1936
f6daaec2 1937static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1938{
3d13ef2e
DL		 1939 struct drm_device *dev = crtc->base.dev;
1940 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1941 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1942
92f2584a 1943 /* PCH only available on ILK+ */
3d13ef2e 1944 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1945 if (WARN_ON(pll == NULL))
ee7b9f93 1946 return;
92f2584a 1947
3e369b76 1948 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1949 return;
7a419866 1950
46edb027
DV		 1951 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1952 pll->name, pll->active, pll->on,
e2b78267 1953 crtc->base.base.id);
7a419866 1954
48da64a8 1955 if (WARN_ON(pll->active == 0)) {
e9d6944e 1956 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1957 return;
1958 }
1959
e9d6944e 1960 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1961 WARN_ON(!pll->on);
cdbd2316 1962 if (--pll->active)
7a419866 1963 return;
ee7b9f93 1964
46edb027 1965 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1966 pll->disable(dev_priv, pll);
ee7b9f93 1967 pll->on = false;
bd2bb1b9
PZ		 1968
1969 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1970}
1971
b8a4f404
PZ		 1972static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1973 enum pipe pipe)
040484af 1974{
23670b32 1975 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1976 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1978 uint32_t reg, val, pipeconf_val;
040484af
JB		 1979
1980 /* PCH only available on ILK+ */
55522f37 1981 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1982
1983 /* Make sure PCH DPLL is enabled */
e72f9fbf 1984 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1985 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1986
1987 /* FDI must be feeding us bits for PCH ports */
1988 assert_fdi_tx_enabled(dev_priv, pipe);
1989 assert_fdi_rx_enabled(dev_priv, pipe);
1990
23670b32
DV		 1991 if (HAS_PCH_CPT(dev)) {
1992 /* Workaround: Set the timing override bit before enabling the
1993 * pch transcoder. */
1994 reg = TRANS_CHICKEN2(pipe);
1995 val = I915_READ(reg);
1996 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1997 I915_WRITE(reg, val);
59c859d6 1998 }
23670b32 1999
ab9412ba 2000 reg = PCH_TRANSCONF(pipe);
040484af 2001 val = I915_READ(reg);
5f7f726d 2002 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 2003
2004 if (HAS_PCH_IBX(dev_priv->dev)) {
2005 /*
2006 * make the BPC in transcoder be consistent with
2007 * that in pipeconf reg.
2008 */
dfd07d72
DV		 2009 val &= ~PIPECONF_BPC_MASK;
2010 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 2011 }
5f7f726d
PZ		 2012
2013 val &= ~TRANS_INTERLACE_MASK;
2014 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 2015 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 2016 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 2017 val |= TRANS_LEGACY_INTERLACED_ILK;
2018 else
2019 val |= TRANS_INTERLACED;
5f7f726d
PZ		 2020 else
2021 val |= TRANS_PROGRESSIVE;
2022
040484af
JB		 2023 I915_WRITE(reg, val | TRANS_ENABLE);
2024 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 2025 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 2026}
2027
8fb033d7 2028static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 2029 enum transcoder cpu_transcoder)
040484af 2030{
8fb033d7 2031 u32 val, pipeconf_val;
8fb033d7
PZ		 2032
2033 /* PCH only available on ILK+ */
55522f37 2034 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 2035
8fb033d7 2036 /* FDI must be feeding us bits for PCH ports */
1a240d4d 2037 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 2038 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 2039
223a6fdf
PZ		 2040 /* Workaround: set timing override bit. */
2041 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2042 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 2043 I915_WRITE(_TRANSA_CHICKEN2, val);
2044
25f3ef11 2045 val = TRANS_ENABLE;
937bb610 2046 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 2047
9a76b1c6
PZ		 2048 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
2049 PIPECONF_INTERLACED_ILK)
a35f2679 2050 val |= TRANS_INTERLACED;
8fb033d7
PZ		 2051 else
2052 val |= TRANS_PROGRESSIVE;
2053
ab9412ba
DV		 2054 I915_WRITE(LPT_TRANSCONF, val);
2055 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 2056 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 2057}
2058
b8a4f404
PZ		 2059static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2060 enum pipe pipe)
040484af 2061{
23670b32
DV		 2062 struct drm_device *dev = dev_priv->dev;
2063 uint32_t reg, val;
040484af
JB		 2064
2065 /* FDI relies on the transcoder */
2066 assert_fdi_tx_disabled(dev_priv, pipe);
2067 assert_fdi_rx_disabled(dev_priv, pipe);
2068
291906f1
JB		 2069 /* Ports must be off as well */
2070 assert_pch_ports_disabled(dev_priv, pipe);
2071
ab9412ba 2072 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2073 val = I915_READ(reg);
2074 val &= ~TRANS_ENABLE;
2075 I915_WRITE(reg, val);
2076 /* wait for PCH transcoder off, transcoder state */
2077 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2078 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2079
2080 if (!HAS_PCH_IBX(dev)) {
2081 /* Workaround: Clear the timing override chicken bit again. */
2082 reg = TRANS_CHICKEN2(pipe);
2083 val = I915_READ(reg);
2084 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2085 I915_WRITE(reg, val);
2086 }
040484af
JB		 2087}
2088
ab4d966c 2089static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2090{
8fb033d7
PZ		 2091 u32 val;
2092
ab9412ba 2093 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2094 val &= ~TRANS_ENABLE;
ab9412ba 2095 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2096 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2097 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2098 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2099
2100 /* Workaround: clear timing override bit. */
2101 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2102 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2103 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2104}
2105
b24e7179 2106/**
309cfea8 2107 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2108 * @crtc: crtc responsible for the pipe
b24e7179 2109 *
0372264a 2110 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2111 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2112 */
e1fdc473 2113static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2114{
0372264a
PZ		 2115 struct drm_device *dev = crtc->base.dev;
2116 struct drm_i915_private *dev_priv = dev->dev_private;
2117 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2118 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2119 pipe);
1a240d4d 2120 enum pipe pch_transcoder;
b24e7179
JB		 2121 int reg;
2122 u32 val;
2123
58c6eaa2 2124 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2125 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2126 assert_sprites_disabled(dev_priv, pipe);
2127
681e5811 2128 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2129 pch_transcoder = TRANSCODER_A;
2130 else
2131 pch_transcoder = pipe;
2132
b24e7179
JB		 2133 /*
2134 * A pipe without a PLL won't actually be able to drive bits from
2135 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2136 * need the check.
2137 */
50360403 2138 if (HAS_GMCH_DISPLAY(dev_priv->dev))
409ee761 2139 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2140 assert_dsi_pll_enabled(dev_priv);
2141 else
2142 assert_pll_enabled(dev_priv, pipe);
040484af 2143 else {
6e3c9717 2144 if (crtc->config->has_pch_encoder) {
040484af 2145 /* if driving the PCH, we need FDI enabled */
cc391bbb 2146 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2147 assert_fdi_tx_pll_enabled(dev_priv,
2148 (enum pipe) cpu_transcoder);
040484af
JB		 2149 }
2150 /* FIXME: assert CPU port conditions for SNB+ */
2151 }
b24e7179 2152
702e7a56 2153 reg = PIPECONF(cpu_transcoder);
b24e7179 2154 val = I915_READ(reg);
7ad25d48 2155 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2156 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2157 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2158 return;
7ad25d48 2159 }
00d70b15
CW		 2160
2161 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2162 POSTING_READ(reg);
b24e7179
JB		 2163}
2164
2165/**
309cfea8 2166 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2167 * @crtc: crtc whose pipes is to be disabled
b24e7179 2168 *
575f7ab7
VS		 2169 * Disable the pipe of @crtc, making sure that various hardware
2170 * specific requirements are met, if applicable, e.g. plane
2171 * disabled, panel fitter off, etc.
b24e7179
JB		 2172 *
2173 * Will wait until the pipe has shut down before returning.
2174 */
575f7ab7 2175static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2176{
575f7ab7 2177 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2178 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2179 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2180 int reg;
2181 u32 val;
2182
2183 /*
2184 * Make sure planes won't keep trying to pump pixels to us,
2185 * or we might hang the display.
2186 */
2187 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2188 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2189 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2190
702e7a56 2191 reg = PIPECONF(cpu_transcoder);
b24e7179 2192 val = I915_READ(reg);
00d70b15
CW		 2193 if ((val & PIPECONF_ENABLE) == 0)
2194 return;
2195
67adc644
VS		 2196 /*
2197 * Double wide has implications for planes
2198 * so best keep it disabled when not needed.
2199 */
6e3c9717 2200 if (crtc->config->double_wide)
67adc644
VS		 2201 val &= ~PIPECONF_DOUBLE_WIDE;
2202
2203 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2204 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2205 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2206 val &= ~PIPECONF_ENABLE;
2207
2208 I915_WRITE(reg, val);
2209 if ((val & PIPECONF_ENABLE) == 0)
2210 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2211}
2212
d74362c9
KP		 2213/*
2214 * Plane regs are double buffered, going from enabled->disabled needs a
2215 * trigger in order to latch. The display address reg provides this.
2216 */
1dba99f4
VS		 2217void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2218 enum plane plane)
d74362c9 2219{
3d13ef2e
DL		 2220 struct drm_device *dev = dev_priv->dev;
2221 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1dba99f4
VS		 2222
2223 I915_WRITE(reg, I915_READ(reg));
2224 POSTING_READ(reg);
d74362c9
KP		 2225}
2226
b24e7179 2227/**
262ca2b0 2228 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2229 * @plane: plane to be enabled
2230 * @crtc: crtc for the plane
b24e7179 2231 *
fdd508a6 2232 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2233 */
fdd508a6
VS		 2234static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2235 struct drm_crtc *crtc)
b24e7179 2236{
fdd508a6
VS		 2237 struct drm_device *dev = plane->dev;
2238 struct drm_i915_private *dev_priv = dev->dev_private;
2239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2240
2241 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2242 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b70709a6 2243 to_intel_plane_state(plane->state)->visible = true;
939c2fe8 2244
fdd508a6
VS		 2245 dev_priv->display.update_primary_plane(crtc, plane->fb,
2246 crtc->x, crtc->y);
b24e7179
JB		 2247}
2248
693db184
CW		 2249static bool need_vtd_wa(struct drm_device *dev)
2250{
2251#ifdef CONFIG_INTEL_IOMMU
2252 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2253 return true;
2254#endif
2255 return false;
2256}
2257
50470bb0 2258unsigned int
6761dd31
TU		 2259intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2260 uint64_t fb_format_modifier)
a57ce0b2 2261{
6761dd31
TU		 2262 unsigned int tile_height;
2263 uint32_t pixel_bytes;
a57ce0b2 2264
b5d0e9bf
DL		 2265 switch (fb_format_modifier) {
2266 case DRM_FORMAT_MOD_NONE:
2267 tile_height = 1;
2268 break;
2269 case I915_FORMAT_MOD_X_TILED:
2270 tile_height = IS_GEN2(dev) ? 16 : 8;
2271 break;
2272 case I915_FORMAT_MOD_Y_TILED:
2273 tile_height = 32;
2274 break;
2275 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2276 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2277 switch (pixel_bytes) {
b5d0e9bf 2278 default:
6761dd31 2279 case 1:
b5d0e9bf
DL		 2280 tile_height = 64;
2281 break;
6761dd31
TU		 2282 case 2:
2283 case 4:
b5d0e9bf
DL		 2284 tile_height = 32;
2285 break;
6761dd31 2286 case 8:
b5d0e9bf
DL		 2287 tile_height = 16;
2288 break;
6761dd31 2289 case 16:
b5d0e9bf
DL		 2290 WARN_ONCE(1,
2291 "128-bit pixels are not supported for display!");
2292 tile_height = 16;
2293 break;
2294 }
2295 break;
2296 default:
2297 MISSING_CASE(fb_format_modifier);
2298 tile_height = 1;
2299 break;
2300 }
091df6cb 2301
6761dd31
TU		 2302 return tile_height;
2303}
2304
2305unsigned int
2306intel_fb_align_height(struct drm_device *dev, unsigned int height,
2307 uint32_t pixel_format, uint64_t fb_format_modifier)
2308{
2309 return ALIGN(height, intel_tile_height(dev, pixel_format,
2310 fb_format_modifier));
a57ce0b2
JB		 2311}
2312
f64b98cd
TU		 2313static int
2314intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2315 const struct drm_plane_state *plane_state)
2316{
50470bb0 2317 struct intel_rotation_info *info = &view->rotation_info;
50470bb0 2318
f64b98cd
TU		 2319 *view = i915_ggtt_view_normal;
2320
50470bb0
TU		 2321 if (!plane_state)
2322 return 0;
2323
121920fa 2324 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2325 return 0;
2326
9abc4648 2327 *view = i915_ggtt_view_rotated;
50470bb0
TU		 2328
2329 info->height = fb->height;
2330 info->pixel_format = fb->pixel_format;
2331 info->pitch = fb->pitches[0];
2332 info->fb_modifier = fb->modifier[0];
2333
f64b98cd
TU		 2334 return 0;
2335}
2336
127bd2ac 2337int
850c4cdc
TU		 2338intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2339 struct drm_framebuffer *fb,
82bc3b2d 2340 const struct drm_plane_state *plane_state,
a4872ba6 2341 struct intel_engine_cs *pipelined)
6b95a207 2342{
850c4cdc 2343 struct drm_device *dev = fb->dev;
ce453d81 2344 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2345 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2346 struct i915_ggtt_view view;
6b95a207
KH		 2347 u32 alignment;
2348 int ret;
2349
ebcdd39e
MR		 2350 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2351
7b911adc
TU		 2352 switch (fb->modifier[0]) {
2353 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2354 if (INTEL_INFO(dev)->gen >= 9)
2355 alignment = 256 * 1024;
2356 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2357 alignment = 128 * 1024;
a6c45cf0 2358 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2359 alignment = 4 * 1024;
2360 else
2361 alignment = 64 * 1024;
6b95a207 2362 break;
7b911adc 2363 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2364 if (INTEL_INFO(dev)->gen >= 9)
2365 alignment = 256 * 1024;
2366 else {
2367 /* pin() will align the object as required by fence */
2368 alignment = 0;
2369 }
6b95a207 2370 break;
7b911adc 2371 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2372 case I915_FORMAT_MOD_Yf_TILED:
2373 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2374 "Y tiling bo slipped through, driver bug!\n"))
2375 return -EINVAL;
2376 alignment = 1 * 1024 * 1024;
2377 break;
6b95a207 2378 default:
7b911adc
TU		 2379 MISSING_CASE(fb->modifier[0]);
2380 return -EINVAL;
6b95a207
KH		 2381 }
2382
f64b98cd
TU		 2383 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2384 if (ret)
2385 return ret;
2386
693db184
CW		 2387 /* Note that the w/a also requires 64 PTE of padding following the
2388 * bo. We currently fill all unused PTE with the shadow page and so
2389 * we should always have valid PTE following the scanout preventing
2390 * the VT-d warning.
2391 */
2392 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2393 alignment = 256 * 1024;
2394
d6dd6843
PZ		 2395 /*
2396 * Global gtt pte registers are special registers which actually forward
2397 * writes to a chunk of system memory. Which means that there is no risk
2398 * that the register values disappear as soon as we call
2399 * intel_runtime_pm_put(), so it is correct to wrap only the
2400 * pin/unpin/fence and not more.
2401 */
2402 intel_runtime_pm_get(dev_priv);
2403
ce453d81 2404 dev_priv->mm.interruptible = false;
e6617330 2405 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2406 &view);
48b956c5 2407 if (ret)
ce453d81 2408 goto err_interruptible;
6b95a207
KH		 2409
2410 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2411 * fence, whereas 965+ only requires a fence if using
2412 * framebuffer compression. For simplicity, we always install
2413 * a fence as the cost is not that onerous.
2414 */
06d98131 2415 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2416 if (ret)
2417 goto err_unpin;
1690e1eb 2418
9a5a53b3 2419 i915_gem_object_pin_fence(obj);
6b95a207 2420
ce453d81 2421 dev_priv->mm.interruptible = true;
d6dd6843 2422 intel_runtime_pm_put(dev_priv);
6b95a207 2423 return 0;
48b956c5
CW		 2424
2425err_unpin:
f64b98cd 2426 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2427err_interruptible:
2428 dev_priv->mm.interruptible = true;
d6dd6843 2429 intel_runtime_pm_put(dev_priv);
48b956c5 2430 return ret;
6b95a207
KH		 2431}
2432
82bc3b2d
TU		 2433static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2434 const struct drm_plane_state *plane_state)
1690e1eb 2435{
82bc3b2d 2436 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2437 struct i915_ggtt_view view;
2438 int ret;
82bc3b2d 2439
ebcdd39e
MR		 2440 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2441
f64b98cd
TU		 2442 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2443 WARN_ONCE(ret, "Couldn't get view from plane state!");
2444
1690e1eb 2445 i915_gem_object_unpin_fence(obj);
f64b98cd 2446 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2447}
2448
c2c75131
DV		 2449/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2450 * is assumed to be a power-of-two. */
bc752862
CW		 2451unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2452 unsigned int tiling_mode,
2453 unsigned int cpp,
2454 unsigned int pitch)
c2c75131 2455{
bc752862
CW		 2456 if (tiling_mode != I915_TILING_NONE) {
2457 unsigned int tile_rows, tiles;
c2c75131 2458
bc752862
CW		 2459 tile_rows = *y / 8;
2460 *y %= 8;
c2c75131 2461
bc752862
CW		 2462 tiles = *x / (512/cpp);
2463 *x %= 512/cpp;
2464
2465 return tile_rows * pitch * 8 + tiles * 4096;
2466 } else {
2467 unsigned int offset;
2468
2469 offset = *y * pitch + *x * cpp;
2470 *y = 0;
2471 *x = (offset & 4095) / cpp;
2472 return offset & -4096;
2473 }
c2c75131
DV		 2474}
2475
b35d63fa 2476static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2477{
2478 switch (format) {
2479 case DISPPLANE_8BPP:
2480 return DRM_FORMAT_C8;
2481 case DISPPLANE_BGRX555:
2482 return DRM_FORMAT_XRGB1555;
2483 case DISPPLANE_BGRX565:
2484 return DRM_FORMAT_RGB565;
2485 default:
2486 case DISPPLANE_BGRX888:
2487 return DRM_FORMAT_XRGB8888;
2488 case DISPPLANE_RGBX888:
2489 return DRM_FORMAT_XBGR8888;
2490 case DISPPLANE_BGRX101010:
2491 return DRM_FORMAT_XRGB2101010;
2492 case DISPPLANE_RGBX101010:
2493 return DRM_FORMAT_XBGR2101010;
2494 }
2495}
2496
bc8d7dff
DL		 2497static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2498{
2499 switch (format) {
2500 case PLANE_CTL_FORMAT_RGB_565:
2501 return DRM_FORMAT_RGB565;
2502 default:
2503 case PLANE_CTL_FORMAT_XRGB_8888:
2504 if (rgb_order) {
2505 if (alpha)
2506 return DRM_FORMAT_ABGR8888;
2507 else
2508 return DRM_FORMAT_XBGR8888;
2509 } else {
2510 if (alpha)
2511 return DRM_FORMAT_ARGB8888;
2512 else
2513 return DRM_FORMAT_XRGB8888;
2514 }
2515 case PLANE_CTL_FORMAT_XRGB_2101010:
2516 if (rgb_order)
2517 return DRM_FORMAT_XBGR2101010;
2518 else
2519 return DRM_FORMAT_XRGB2101010;
2520 }
2521}
2522
5724dbd1 2523static bool
f6936e29
DV		 2524intel_alloc_initial_plane_obj(struct intel_crtc *crtc,
2525 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2526{
2527 struct drm_device *dev = crtc->base.dev;
2528 struct drm_i915_gem_object *obj = NULL;
2529 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2530 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2531 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2532 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2533 PAGE_SIZE);
2534
2535 size_aligned -= base_aligned;
46f297fb 2536
ff2652ea
CW		 2537 if (plane_config->size == 0)
2538 return false;
2539
f37b5c2b
DV		 2540 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2541 base_aligned,
2542 base_aligned,
2543 size_aligned);
46f297fb 2544 if (!obj)
484b41dd 2545 return false;
46f297fb 2546
49af449b
DL		 2547 obj->tiling_mode = plane_config->tiling;
2548 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2549 obj->stride = fb->pitches[0];
46f297fb 2550
6bf129df
DL		 2551 mode_cmd.pixel_format = fb->pixel_format;
2552 mode_cmd.width = fb->width;
2553 mode_cmd.height = fb->height;
2554 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2555 mode_cmd.modifier[0] = fb->modifier[0];
2556 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2557
2558 mutex_lock(&dev->struct_mutex);
6bf129df 2559 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2560 &mode_cmd, obj)) {
46f297fb
JB		 2561 DRM_DEBUG_KMS("intel fb init failed\n");
2562 goto out_unref_obj;
2563 }
46f297fb 2564 mutex_unlock(&dev->struct_mutex);
484b41dd 2565
f6936e29 2566 DRM_DEBUG_KMS("initial plane fb obj %p\n", obj);
484b41dd 2567 return true;
46f297fb
JB		 2568
2569out_unref_obj:
2570 drm_gem_object_unreference(&obj->base);
2571 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2572 return false;
2573}
2574
afd65eb4
MR		 2575/* Update plane->state->fb to match plane->fb after driver-internal updates */
2576static void
2577update_state_fb(struct drm_plane *plane)
2578{
2579 if (plane->fb == plane->state->fb)
2580 return;
2581
2582 if (plane->state->fb)
2583 drm_framebuffer_unreference(plane->state->fb);
2584 plane->state->fb = plane->fb;
2585 if (plane->state->fb)
2586 drm_framebuffer_reference(plane->state->fb);
2587}
2588
5724dbd1 2589static void
f6936e29
DV		 2590intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
2591 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2592{
2593 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2594 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2595 struct drm_crtc *c;
2596 struct intel_crtc *i;
2ff8fde1 2597 struct drm_i915_gem_object *obj;
88595ac9
DV		 2598 struct drm_plane *primary = intel_crtc->base.primary;
2599 struct drm_framebuffer *fb;
484b41dd 2600
2d14030b 2601 if (!plane_config->fb)
484b41dd
JB		 2602 return;
2603
f6936e29 2604 if (intel_alloc_initial_plane_obj(intel_crtc, plane_config)) {
88595ac9
DV		 2605 fb = &plane_config->fb->base;
2606 goto valid_fb;
f55548b5 2607 }
484b41dd 2608
2d14030b 2609 kfree(plane_config->fb);
484b41dd
JB		 2610
2611 /*
2612 * Failed to alloc the obj, check to see if we should share
2613 * an fb with another CRTC instead
2614 */
70e1e0ec 2615 for_each_crtc(dev, c) {
484b41dd
JB		 2616 i = to_intel_crtc(c);
2617
2618 if (c == &intel_crtc->base)
2619 continue;
2620
2ff8fde1
MR		 2621 if (!i->active)
2622 continue;
2623
88595ac9
DV		 2624 fb = c->primary->fb;
2625 if (!fb)
484b41dd
JB		 2626 continue;
2627
88595ac9 2628 obj = intel_fb_obj(fb);
2ff8fde1 2629 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
88595ac9
DV		 2630 drm_framebuffer_reference(fb);
2631 goto valid_fb;
484b41dd
JB		 2632 }
2633 }
88595ac9
DV		 2634
2635 return;
2636
2637valid_fb:
2638 obj = intel_fb_obj(fb);
2639 if (obj->tiling_mode != I915_TILING_NONE)
2640 dev_priv->preserve_bios_swizzle = true;
2641
2642 primary->fb = fb;
2643 primary->state->crtc = &intel_crtc->base;
2644 primary->crtc = &intel_crtc->base;
2645 update_state_fb(primary);
2646 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
46f297fb
JB		 2647}
2648
29b9bde6
DV		 2649static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2650 struct drm_framebuffer *fb,
2651 int x, int y)
81255565
JB		 2652{
2653 struct drm_device *dev = crtc->dev;
2654 struct drm_i915_private *dev_priv = dev->dev_private;
2655 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2656 struct drm_plane *primary = crtc->primary;
2657 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2658 struct drm_i915_gem_object *obj;
81255565 2659 int plane = intel_crtc->plane;
e506a0c6 2660 unsigned long linear_offset;
81255565 2661 u32 dspcntr;
f45651ba 2662 u32 reg = DSPCNTR(plane);
48404c1e 2663 int pixel_size;
f45651ba 2664
b70709a6 2665 if (!visible || !fb) {
fdd508a6
VS		 2666 I915_WRITE(reg, 0);
2667 if (INTEL_INFO(dev)->gen >= 4)
2668 I915_WRITE(DSPSURF(plane), 0);
2669 else
2670 I915_WRITE(DSPADDR(plane), 0);
2671 POSTING_READ(reg);
2672 return;
2673 }
2674
c9ba6fad
VS		 2675 obj = intel_fb_obj(fb);
2676 if (WARN_ON(obj == NULL))
2677 return;
2678
2679 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2680
f45651ba
VS		 2681 dspcntr = DISPPLANE_GAMMA_ENABLE;
2682
fdd508a6 2683 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2684
2685 if (INTEL_INFO(dev)->gen < 4) {
2686 if (intel_crtc->pipe == PIPE_B)
2687 dspcntr |= DISPPLANE_SEL_PIPE_B;
2688
2689 /* pipesrc and dspsize control the size that is scaled from,
2690 * which should always be the user's requested size.
2691 */
2692 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2693 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2694 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2695 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2696 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2697 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2698 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2699 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2700 I915_WRITE(PRIMPOS(plane), 0);
2701 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2702 }
81255565 2703
57779d06
VS		 2704 switch (fb->pixel_format) {
2705 case DRM_FORMAT_C8:
81255565
JB		 2706 dspcntr |= DISPPLANE_8BPP;
2707 break;
57779d06 2708 case DRM_FORMAT_XRGB1555:
57779d06 2709 dspcntr |= DISPPLANE_BGRX555;
81255565 2710 break;
57779d06
VS		 2711 case DRM_FORMAT_RGB565:
2712 dspcntr |= DISPPLANE_BGRX565;
2713 break;
2714 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2715 dspcntr |= DISPPLANE_BGRX888;
2716 break;
2717 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2718 dspcntr |= DISPPLANE_RGBX888;
2719 break;
2720 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2721 dspcntr |= DISPPLANE_BGRX101010;
2722 break;
2723 case DRM_FORMAT_XBGR2101010:
57779d06 2724 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2725 break;
2726 default:
baba133a 2727 BUG();
81255565 2728 }
57779d06 2729
f45651ba
VS		 2730 if (INTEL_INFO(dev)->gen >= 4 &&
2731 obj->tiling_mode != I915_TILING_NONE)
2732 dspcntr |= DISPPLANE_TILED;
81255565 2733
de1aa629
VS		 2734 if (IS_G4X(dev))
2735 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2736
b9897127 2737 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2738
c2c75131
DV		 2739 if (INTEL_INFO(dev)->gen >= 4) {
2740 intel_crtc->dspaddr_offset =
bc752862 2741 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2742 pixel_size,
bc752862 2743 fb->pitches[0]);
c2c75131
DV		 2744 linear_offset -= intel_crtc->dspaddr_offset;
2745 } else {
e506a0c6 2746 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2747 }
e506a0c6 2748
8e7d688b 2749 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2750 dspcntr |= DISPPLANE_ROTATE_180;
2751
6e3c9717
ACO		 2752 x += (intel_crtc->config->pipe_src_w - 1);
2753 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2754
2755 /* Finding the last pixel of the last line of the display
2756 data and adding to linear_offset*/
2757 linear_offset +=
6e3c9717
ACO		 2758 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2759 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2760 }
2761
2762 I915_WRITE(reg, dspcntr);
2763
01f2c773 2764 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2765 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2766 I915_WRITE(DSPSURF(plane),
2767 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2768 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2769 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2770 } else
f343c5f6 2771 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2772 POSTING_READ(reg);
17638cd6
JB		 2773}
2774
29b9bde6
DV		 2775static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2776 struct drm_framebuffer *fb,
2777 int x, int y)
17638cd6
JB		 2778{
2779 struct drm_device *dev = crtc->dev;
2780 struct drm_i915_private *dev_priv = dev->dev_private;
2781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 2782 struct drm_plane *primary = crtc->primary;
2783 bool visible = to_intel_plane_state(primary->state)->visible;
c9ba6fad 2784 struct drm_i915_gem_object *obj;
17638cd6 2785 int plane = intel_crtc->plane;
e506a0c6 2786 unsigned long linear_offset;
17638cd6 2787 u32 dspcntr;
f45651ba 2788 u32 reg = DSPCNTR(plane);
48404c1e 2789 int pixel_size;
f45651ba 2790
b70709a6 2791 if (!visible || !fb) {
fdd508a6
VS		 2792 I915_WRITE(reg, 0);
2793 I915_WRITE(DSPSURF(plane), 0);
2794 POSTING_READ(reg);
2795 return;
2796 }
2797
c9ba6fad
VS		 2798 obj = intel_fb_obj(fb);
2799 if (WARN_ON(obj == NULL))
2800 return;
2801
2802 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2803
f45651ba
VS		 2804 dspcntr = DISPPLANE_GAMMA_ENABLE;
2805
fdd508a6 2806 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2807
2808 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2809 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2810
57779d06
VS		 2811 switch (fb->pixel_format) {
2812 case DRM_FORMAT_C8:
17638cd6
JB		 2813 dspcntr |= DISPPLANE_8BPP;
2814 break;
57779d06
VS		 2815 case DRM_FORMAT_RGB565:
2816 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2817 break;
57779d06 2818 case DRM_FORMAT_XRGB8888:
57779d06
VS		 2819 dspcntr |= DISPPLANE_BGRX888;
2820 break;
2821 case DRM_FORMAT_XBGR8888:
57779d06
VS		 2822 dspcntr |= DISPPLANE_RGBX888;
2823 break;
2824 case DRM_FORMAT_XRGB2101010:
57779d06
VS		 2825 dspcntr |= DISPPLANE_BGRX101010;
2826 break;
2827 case DRM_FORMAT_XBGR2101010:
57779d06 2828 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2829 break;
2830 default:
baba133a 2831 BUG();
17638cd6
JB		 2832 }
2833
2834 if (obj->tiling_mode != I915_TILING_NONE)
2835 dspcntr |= DISPPLANE_TILED;
17638cd6 2836
f45651ba 2837 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2838 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2839
b9897127 2840 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2841 intel_crtc->dspaddr_offset =
bc752862 2842 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2843 pixel_size,
bc752862 2844 fb->pitches[0]);
c2c75131 2845 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2846 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2847 dspcntr |= DISPPLANE_ROTATE_180;
2848
2849 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2850 x += (intel_crtc->config->pipe_src_w - 1);
2851 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2852
2853 /* Finding the last pixel of the last line of the display
2854 data and adding to linear_offset*/
2855 linear_offset +=
6e3c9717
ACO		 2856 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2857 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2858 }
2859 }
2860
2861 I915_WRITE(reg, dspcntr);
17638cd6 2862
01f2c773 2863 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2864 I915_WRITE(DSPSURF(plane),
2865 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2866 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2867 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2868 } else {
2869 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2870 I915_WRITE(DSPLINOFF(plane), linear_offset);
2871 }
17638cd6 2872 POSTING_READ(reg);
17638cd6
JB		 2873}
2874
b321803d
DL		 2875u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2876 uint32_t pixel_format)
2877{
2878 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2879
2880 /*
2881 * The stride is either expressed as a multiple of 64 bytes
2882 * chunks for linear buffers or in number of tiles for tiled
2883 * buffers.
2884 */
2885 switch (fb_modifier) {
2886 case DRM_FORMAT_MOD_NONE:
2887 return 64;
2888 case I915_FORMAT_MOD_X_TILED:
2889 if (INTEL_INFO(dev)->gen == 2)
2890 return 128;
2891 return 512;
2892 case I915_FORMAT_MOD_Y_TILED:
2893 /* No need to check for old gens and Y tiling since this is
2894 * about the display engine and those will be blocked before
2895 * we get here.
2896 */
2897 return 128;
2898 case I915_FORMAT_MOD_Yf_TILED:
2899 if (bits_per_pixel == 8)
2900 return 64;
2901 else
2902 return 128;
2903 default:
2904 MISSING_CASE(fb_modifier);
2905 return 64;
2906 }
2907}
2908
121920fa
TU		 2909unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2910 struct drm_i915_gem_object *obj)
2911{
9abc4648 2912 const struct i915_ggtt_view *view = &i915_ggtt_view_normal;
121920fa
TU		 2913
2914 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
9abc4648 2915 view = &i915_ggtt_view_rotated;
121920fa
TU		 2916
2917 return i915_gem_obj_ggtt_offset_view(obj, view);
2918}
2919
a1b2278e
CK		 2920/*
2921 * This function detaches (aka. unbinds) unused scalers in hardware
2922 */
2923void skl_detach_scalers(struct intel_crtc *intel_crtc)
2924{
2925 struct drm_device *dev;
2926 struct drm_i915_private *dev_priv;
2927 struct intel_crtc_scaler_state *scaler_state;
2928 int i;
2929
2930 if (!intel_crtc || !intel_crtc->config)
2931 return;
2932
2933 dev = intel_crtc->base.dev;
2934 dev_priv = dev->dev_private;
2935 scaler_state = &intel_crtc->config->scaler_state;
2936
2937 /* loop through and disable scalers that aren't in use */
2938 for (i = 0; i < intel_crtc->num_scalers; i++) {
2939 if (!scaler_state->scalers[i].in_use) {
2940 I915_WRITE(SKL_PS_CTRL(intel_crtc->pipe, i), 0);
2941 I915_WRITE(SKL_PS_WIN_POS(intel_crtc->pipe, i), 0);
2942 I915_WRITE(SKL_PS_WIN_SZ(intel_crtc->pipe, i), 0);
2943 DRM_DEBUG_KMS("CRTC:%d Disabled scaler id %u.%u\n",
2944 intel_crtc->base.base.id, intel_crtc->pipe, i);
2945 }
2946 }
2947}
2948
6156a456 2949u32 skl_plane_ctl_format(uint32_t pixel_format)
70d21f0e 2950{
6156a456 2951 switch (pixel_format) {
d161cf7a 2952 case DRM_FORMAT_C8:
c34ce3d1 2953 return PLANE_CTL_FORMAT_INDEXED;
70d21f0e 2954 case DRM_FORMAT_RGB565:
c34ce3d1 2955 return PLANE_CTL_FORMAT_RGB_565;
70d21f0e 2956 case DRM_FORMAT_XBGR8888:
c34ce3d1 2957 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX;
6156a456 2958 case DRM_FORMAT_XRGB8888:
c34ce3d1 2959 return PLANE_CTL_FORMAT_XRGB_8888;
6156a456
CK		 2960 /*
2961 * XXX: For ARBG/ABGR formats we default to expecting scanout buffers
2962 * to be already pre-multiplied. We need to add a knob (or a different
2963 * DRM_FORMAT) for user-space to configure that.
2964 */
f75fb42a 2965 case DRM_FORMAT_ABGR8888:
c34ce3d1 2966 return PLANE_CTL_FORMAT_XRGB_8888 | PLANE_CTL_ORDER_RGBX |
6156a456 2967 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
6156a456 2968 case DRM_FORMAT_ARGB8888:
c34ce3d1 2969 return PLANE_CTL_FORMAT_XRGB_8888 |
6156a456 2970 PLANE_CTL_ALPHA_SW_PREMULTIPLY;
70d21f0e 2971 case DRM_FORMAT_XRGB2101010:
c34ce3d1 2972 return PLANE_CTL_FORMAT_XRGB_2101010;
70d21f0e 2973 case DRM_FORMAT_XBGR2101010:
c34ce3d1 2974 return PLANE_CTL_ORDER_RGBX | PLANE_CTL_FORMAT_XRGB_2101010;
6156a456 2975 case DRM_FORMAT_YUYV:
c34ce3d1 2976 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YUYV;
6156a456 2977 case DRM_FORMAT_YVYU:
c34ce3d1 2978 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_YVYU;
6156a456 2979 case DRM_FORMAT_UYVY:
c34ce3d1 2980 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
6156a456 2981 case DRM_FORMAT_VYUY:
c34ce3d1 2982 return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
70d21f0e 2983 default:
4249eeef 2984 MISSING_CASE(pixel_format);
70d21f0e 2985 }
8cfcba41 2986
c34ce3d1 2987 return 0;
6156a456 2988}
70d21f0e 2989
6156a456
CK		 2990u32 skl_plane_ctl_tiling(uint64_t fb_modifier)
2991{
6156a456 2992 switch (fb_modifier) {
30af77c4 2993 case DRM_FORMAT_MOD_NONE:
70d21f0e 2994 break;
30af77c4 2995 case I915_FORMAT_MOD_X_TILED:
c34ce3d1 2996 return PLANE_CTL_TILED_X;
b321803d 2997 case I915_FORMAT_MOD_Y_TILED:
c34ce3d1 2998 return PLANE_CTL_TILED_Y;
b321803d 2999 case I915_FORMAT_MOD_Yf_TILED:
c34ce3d1 3000 return PLANE_CTL_TILED_YF;
70d21f0e 3001 default:
6156a456 3002 MISSING_CASE(fb_modifier);
70d21f0e 3003 }
8cfcba41 3004
c34ce3d1 3005 return 0;
6156a456 3006}
70d21f0e 3007
6156a456
CK		 3008u32 skl_plane_ctl_rotation(unsigned int rotation)
3009{
3b7a5119 3010 switch (rotation) {
6156a456
CK		 3011 case BIT(DRM_ROTATE_0):
3012 break;
1e8df167
SJ		 3013 /*
3014 * DRM_ROTATE_ is counter clockwise to stay compatible with Xrandr
3015 * while i915 HW rotation is clockwise, thats why this swapping.
3016 */
3b7a5119 3017 case BIT(DRM_ROTATE_90):
1e8df167 3018 return PLANE_CTL_ROTATE_270;
3b7a5119 3019 case BIT(DRM_ROTATE_180):
c34ce3d1 3020 return PLANE_CTL_ROTATE_180;
3b7a5119 3021 case BIT(DRM_ROTATE_270):
1e8df167 3022 return PLANE_CTL_ROTATE_90;
6156a456
CK		 3023 default:
3024 MISSING_CASE(rotation);
3025 }
3026
c34ce3d1 3027 return 0;
6156a456
CK		 3028}
3029
3030static void skylake_update_primary_plane(struct drm_crtc *crtc,
3031 struct drm_framebuffer *fb,
3032 int x, int y)
3033{
3034 struct drm_device *dev = crtc->dev;
3035 struct drm_i915_private *dev_priv = dev->dev_private;
3036 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b70709a6
ML		 3037 struct drm_plane *plane = crtc->primary;
3038 bool visible = to_intel_plane_state(plane->state)->visible;
6156a456
CK		 3039 struct drm_i915_gem_object *obj;
3040 int pipe = intel_crtc->pipe;
3041 u32 plane_ctl, stride_div, stride;
3042 u32 tile_height, plane_offset, plane_size;
3043 unsigned int rotation;
3044 int x_offset, y_offset;
3045 unsigned long surf_addr;
6156a456
CK		 3046 struct intel_crtc_state *crtc_state = intel_crtc->config;
3047 struct intel_plane_state *plane_state;
3048 int src_x = 0, src_y = 0, src_w = 0, src_h = 0;
3049 int dst_x = 0, dst_y = 0, dst_w = 0, dst_h = 0;
3050 int scaler_id = -1;
3051
6156a456
CK		 3052 plane_state = to_intel_plane_state(plane->state);
3053
b70709a6 3054 if (!visible || !fb) {
6156a456
CK		 3055 I915_WRITE(PLANE_CTL(pipe, 0), 0);
3056 I915_WRITE(PLANE_SURF(pipe, 0), 0);
3057 POSTING_READ(PLANE_CTL(pipe, 0));
3058 return;
3b7a5119 3059 }
70d21f0e 3060
6156a456
CK		 3061 plane_ctl = PLANE_CTL_ENABLE |
3062 PLANE_CTL_PIPE_GAMMA_ENABLE |
3063 PLANE_CTL_PIPE_CSC_ENABLE;
3064
3065 plane_ctl |= skl_plane_ctl_format(fb->pixel_format);
3066 plane_ctl |= skl_plane_ctl_tiling(fb->modifier[0]);
3067 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
3068
3069 rotation = plane->state->rotation;
3070 plane_ctl |= skl_plane_ctl_rotation(rotation);
3071
b321803d
DL		 3072 obj = intel_fb_obj(fb);
3073 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
3074 fb->pixel_format);
3b7a5119
SJ		 3075 surf_addr = intel_plane_obj_offset(to_intel_plane(plane), obj);
3076
6156a456
CK		 3077 /*
3078 * FIXME: intel_plane_state->src, dst aren't set when transitional
3079 * update_plane helpers are called from legacy paths.
3080 * Once full atomic crtc is available, below check can be avoided.
3081 */
3082 if (drm_rect_width(&plane_state->src)) {
3083 scaler_id = plane_state->scaler_id;
3084 src_x = plane_state->src.x1 >> 16;
3085 src_y = plane_state->src.y1 >> 16;
3086 src_w = drm_rect_width(&plane_state->src) >> 16;
3087 src_h = drm_rect_height(&plane_state->src) >> 16;
3088 dst_x = plane_state->dst.x1;
3089 dst_y = plane_state->dst.y1;
3090 dst_w = drm_rect_width(&plane_state->dst);
3091 dst_h = drm_rect_height(&plane_state->dst);
3092
3093 WARN_ON(x != src_x || y != src_y);
3094 } else {
3095 src_w = intel_crtc->config->pipe_src_w;
3096 src_h = intel_crtc->config->pipe_src_h;
3097 }
3098
3b7a5119
SJ		 3099 if (intel_rotation_90_or_270(rotation)) {
3100 /* stride = Surface height in tiles */
2614f17d 3101 tile_height = intel_tile_height(dev, fb->pixel_format,
3b7a5119
SJ		 3102 fb->modifier[0]);
3103 stride = DIV_ROUND_UP(fb->height, tile_height);
6156a456 3104 x_offset = stride * tile_height - y - src_h;
3b7a5119 3105 y_offset = x;
6156a456 3106 plane_size = (src_w - 1) << 16 | (src_h - 1);
3b7a5119
SJ		 3107 } else {
3108 stride = fb->pitches[0] / stride_div;
3109 x_offset = x;
3110 y_offset = y;
6156a456 3111 plane_size = (src_h - 1) << 16 | (src_w - 1);
3b7a5119
SJ		 3112 }
3113 plane_offset = y_offset << 16 | x_offset;
b321803d 3114
70d21f0e 3115 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
3b7a5119
SJ		 3116 I915_WRITE(PLANE_OFFSET(pipe, 0), plane_offset);
3117 I915_WRITE(PLANE_SIZE(pipe, 0), plane_size);
3118 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
6156a456
CK		 3119
3120 if (scaler_id >= 0) {
3121 uint32_t ps_ctrl = 0;
3122
3123 WARN_ON(!dst_w || !dst_h);
3124 ps_ctrl = PS_SCALER_EN | PS_PLANE_SEL(0) |
3125 crtc_state->scaler_state.scalers[scaler_id].mode;
3126 I915_WRITE(SKL_PS_CTRL(pipe, scaler_id), ps_ctrl);
3127 I915_WRITE(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
3128 I915_WRITE(SKL_PS_WIN_POS(pipe, scaler_id), (dst_x << 16) | dst_y);
3129 I915_WRITE(SKL_PS_WIN_SZ(pipe, scaler_id), (dst_w << 16) | dst_h);
3130 I915_WRITE(PLANE_POS(pipe, 0), 0);
3131 } else {
3132 I915_WRITE(PLANE_POS(pipe, 0), (dst_y << 16) | dst_x);
3133 }
3134
121920fa 3135 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3136
3137 POSTING_READ(PLANE_SURF(pipe, 0));
3138}
3139
17638cd6
JB		 3140/* Assume fb object is pinned & idle & fenced and just update base pointers */
3141static int
3142intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3143 int x, int y, enum mode_set_atomic state)
3144{
3145 struct drm_device *dev = crtc->dev;
3146 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3147
6b8e6ed0
CW		 3148 if (dev_priv->display.disable_fbc)
3149 dev_priv->display.disable_fbc(dev);
81255565 3150
29b9bde6
DV		 3151 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3152
3153 return 0;
81255565
JB		 3154}
3155
7514747d 3156static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3157{
96a02917
VS		 3158 struct drm_crtc *crtc;
3159
70e1e0ec 3160 for_each_crtc(dev, crtc) {
96a02917
VS		 3161 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3162 enum plane plane = intel_crtc->plane;
3163
3164 intel_prepare_page_flip(dev, plane);
3165 intel_finish_page_flip_plane(dev, plane);
3166 }
7514747d
VS		 3167}
3168
3169static void intel_update_primary_planes(struct drm_device *dev)
3170{
3171 struct drm_i915_private *dev_priv = dev->dev_private;
3172 struct drm_crtc *crtc;
96a02917 3173
70e1e0ec 3174 for_each_crtc(dev, crtc) {
96a02917
VS		 3175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3176
51fd371b 3177 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3178 /*
3179 * FIXME: Once we have proper support for primary planes (and
3180 * disabling them without disabling the entire crtc) allow again
66e514c1 3181 * a NULL crtc->primary->fb.
947fdaad 3182 */
f4510a27 3183 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3184 dev_priv->display.update_primary_plane(crtc,
66e514c1 3185 crtc->primary->fb,
262ca2b0
MR		 3186 crtc->x,
3187 crtc->y);
51fd371b 3188 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3189 }
3190}
3191
ce22dba9
ML		 3192void intel_crtc_reset(struct intel_crtc *crtc)
3193{
3194 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3195
3196 if (!crtc->active)
3197 return;
3198
3199 intel_crtc_disable_planes(&crtc->base);
3200 dev_priv->display.crtc_disable(&crtc->base);
3201 dev_priv->display.crtc_enable(&crtc->base);
3202 intel_crtc_enable_planes(&crtc->base);
3203}
3204
7514747d
VS		 3205void intel_prepare_reset(struct drm_device *dev)
3206{
f98ce92f
VS		 3207 struct drm_i915_private *dev_priv = to_i915(dev);
3208 struct intel_crtc *crtc;
3209
7514747d
VS		 3210 /* no reset support for gen2 */
3211 if (IS_GEN2(dev))
3212 return;
3213
3214 /* reset doesn't touch the display */
3215 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3216 return;
3217
3218 drm_modeset_lock_all(dev);
f98ce92f
VS		 3219
3220 /*
3221 * Disabling the crtcs gracefully seems nicer. Also the
3222 * g33 docs say we should at least disable all the planes.
3223 */
3224 for_each_intel_crtc(dev, crtc) {
ce22dba9
ML		 3225 if (!crtc->active)
3226 continue;
3227
3228 intel_crtc_disable_planes(&crtc->base);
3229 dev_priv->display.crtc_disable(&crtc->base);
f98ce92f 3230 }
7514747d
VS		 3231}
3232
3233void intel_finish_reset(struct drm_device *dev)
3234{
3235 struct drm_i915_private *dev_priv = to_i915(dev);
3236
3237 /*
3238 * Flips in the rings will be nuked by the reset,
3239 * so complete all pending flips so that user space
3240 * will get its events and not get stuck.
3241 */
3242 intel_complete_page_flips(dev);
3243
3244 /* no reset support for gen2 */
3245 if (IS_GEN2(dev))
3246 return;
3247
3248 /* reset doesn't touch the display */
3249 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3250 /*
3251 * Flips in the rings have been nuked by the reset,
3252 * so update the base address of all primary
3253 * planes to the the last fb to make sure we're
3254 * showing the correct fb after a reset.
3255 */
3256 intel_update_primary_planes(dev);
3257 return;
3258 }
3259
3260 /*
3261 * The display has been reset as well,
3262 * so need a full re-initialization.
3263 */
3264 intel_runtime_pm_disable_interrupts(dev_priv);
3265 intel_runtime_pm_enable_interrupts(dev_priv);
3266
3267 intel_modeset_init_hw(dev);
3268
3269 spin_lock_irq(&dev_priv->irq_lock);
3270 if (dev_priv->display.hpd_irq_setup)
3271 dev_priv->display.hpd_irq_setup(dev);
3272 spin_unlock_irq(&dev_priv->irq_lock);
3273
3274 intel_modeset_setup_hw_state(dev, true);
3275
3276 intel_hpd_init(dev_priv);
3277
3278 drm_modeset_unlock_all(dev);
3279}
3280
2e2f351d 3281static void
14667a4b
CW		 3282intel_finish_fb(struct drm_framebuffer *old_fb)
3283{
2ff8fde1 3284 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
2e2f351d 3285 struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
14667a4b
CW		 3286 bool was_interruptible = dev_priv->mm.interruptible;
3287 int ret;
3288
14667a4b
CW		 3289 /* Big Hammer, we also need to ensure that any pending
3290 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3291 * current scanout is retired before unpinning the old
2e2f351d
CW		 3292 * framebuffer. Note that we rely on userspace rendering
3293 * into the buffer attached to the pipe they are waiting
3294 * on. If not, userspace generates a GPU hang with IPEHR
3295 * point to the MI_WAIT_FOR_EVENT.
14667a4b
CW		 3296 *
3297 * This should only fail upon a hung GPU, in which case we
3298 * can safely continue.
3299 */
3300 dev_priv->mm.interruptible = false;
2e2f351d 3301 ret = i915_gem_object_wait_rendering(obj, true);
14667a4b
CW		 3302 dev_priv->mm.interruptible = was_interruptible;
3303
2e2f351d 3304 WARN_ON(ret);
14667a4b
CW		 3305}
3306
7d5e3799
CW		 3307static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3308{
3309 struct drm_device *dev = crtc->dev;
3310 struct drm_i915_private *dev_priv = dev->dev_private;
3311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3312 bool pending;
3313
3314 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3315 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3316 return false;
3317
5e2d7afc 3318 spin_lock_irq(&dev->event_lock);
7d5e3799 3319 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3320 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3321
3322 return pending;
3323}
3324
e30e8f75
GP		 3325static void intel_update_pipe_size(struct intel_crtc *crtc)
3326{
3327 struct drm_device *dev = crtc->base.dev;
3328 struct drm_i915_private *dev_priv = dev->dev_private;
3329 const struct drm_display_mode *adjusted_mode;
3330
3331 if (!i915.fastboot)
3332 return;
3333
3334 /*
3335 * Update pipe size and adjust fitter if needed: the reason for this is
3336 * that in compute_mode_changes we check the native mode (not the pfit
3337 * mode) to see if we can flip rather than do a full mode set. In the
3338 * fastboot case, we'll flip, but if we don't update the pipesrc and
3339 * pfit state, we'll end up with a big fb scanned out into the wrong
3340 * sized surface.
3341 *
3342 * To fix this properly, we need to hoist the checks up into
3343 * compute_mode_changes (or above), check the actual pfit state and
3344 * whether the platform allows pfit disable with pipe active, and only
3345 * then update the pipesrc and pfit state, even on the flip path.
3346 */
3347
6e3c9717 3348 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3349
3350 I915_WRITE(PIPESRC(crtc->pipe),
3351 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3352 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3353 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3354 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3355 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3356 I915_WRITE(PF_CTL(crtc->pipe), 0);
3357 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3358 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3359 }
6e3c9717
ACO		 3360 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3361 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3362}
3363
5e84e1a4
ZW		 3364static void intel_fdi_normal_train(struct drm_crtc *crtc)
3365{
3366 struct drm_device *dev = crtc->dev;
3367 struct drm_i915_private *dev_priv = dev->dev_private;
3368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3369 int pipe = intel_crtc->pipe;
3370 u32 reg, temp;
3371
3372 /* enable normal train */
3373 reg = FDI_TX_CTL(pipe);
3374 temp = I915_READ(reg);
61e499bf 3375 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3376 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3377 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3378 } else {
3379 temp &= ~FDI_LINK_TRAIN_NONE;
3380 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3381 }
5e84e1a4
ZW		 3382 I915_WRITE(reg, temp);
3383
3384 reg = FDI_RX_CTL(pipe);
3385 temp = I915_READ(reg);
3386 if (HAS_PCH_CPT(dev)) {
3387 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3388 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3389 } else {
3390 temp &= ~FDI_LINK_TRAIN_NONE;
3391 temp |= FDI_LINK_TRAIN_NONE;
3392 }
3393 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3394
3395 /* wait one idle pattern time */
3396 POSTING_READ(reg);
3397 udelay(1000);
357555c0
JB		 3398
3399 /* IVB wants error correction enabled */
3400 if (IS_IVYBRIDGE(dev))
3401 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3402 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3403}
3404
8db9d77b
ZW		 3405/* The FDI link training functions for ILK/Ibexpeak. */
3406static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3407{
3408 struct drm_device *dev = crtc->dev;
3409 struct drm_i915_private *dev_priv = dev->dev_private;
3410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3411 int pipe = intel_crtc->pipe;
5eddb70b 3412 u32 reg, temp, tries;
8db9d77b 3413
1c8562f6 3414 /* FDI needs bits from pipe first */
0fc932b8 3415 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3416
e1a44743
AJ		 3417 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3418 for train result */
5eddb70b
CW		 3419 reg = FDI_RX_IMR(pipe);
3420 temp = I915_READ(reg);
e1a44743
AJ		 3421 temp &= ~FDI_RX_SYMBOL_LOCK;
3422 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3423 I915_WRITE(reg, temp);
3424 I915_READ(reg);
e1a44743
AJ		 3425 udelay(150);
3426
8db9d77b 3427 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3428 reg = FDI_TX_CTL(pipe);
3429 temp = I915_READ(reg);
627eb5a3 3430 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3431 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3432 temp &= ~FDI_LINK_TRAIN_NONE;
3433 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3434 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3435
5eddb70b
CW		 3436 reg = FDI_RX_CTL(pipe);
3437 temp = I915_READ(reg);
8db9d77b
ZW		 3438 temp &= ~FDI_LINK_TRAIN_NONE;
3439 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3440 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3441
3442 POSTING_READ(reg);
8db9d77b
ZW		 3443 udelay(150);
3444
5b2adf89 3445 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3447 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3448 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3449
5eddb70b 3450 reg = FDI_RX_IIR(pipe);
e1a44743 3451 for (tries = 0; tries < 5; tries++) {
5eddb70b 3452 temp = I915_READ(reg);
8db9d77b
ZW		 3453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3454
3455 if ((temp & FDI_RX_BIT_LOCK)) {
3456 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3457 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3458 break;
3459 }
8db9d77b 3460 }
e1a44743 3461 if (tries == 5)
5eddb70b 3462 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3463
3464 /* Train 2 */
5eddb70b
CW		 3465 reg = FDI_TX_CTL(pipe);
3466 temp = I915_READ(reg);
8db9d77b
ZW		 3467 temp &= ~FDI_LINK_TRAIN_NONE;
3468 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3469 I915_WRITE(reg, temp);
8db9d77b 3470
5eddb70b
CW		 3471 reg = FDI_RX_CTL(pipe);
3472 temp = I915_READ(reg);
8db9d77b
ZW		 3473 temp &= ~FDI_LINK_TRAIN_NONE;
3474 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3475 I915_WRITE(reg, temp);
8db9d77b 3476
5eddb70b
CW		 3477 POSTING_READ(reg);
3478 udelay(150);
8db9d77b 3479
5eddb70b 3480 reg = FDI_RX_IIR(pipe);
e1a44743 3481 for (tries = 0; tries < 5; tries++) {
5eddb70b 3482 temp = I915_READ(reg);
8db9d77b
ZW		 3483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3484
3485 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3486 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3487 DRM_DEBUG_KMS("FDI train 2 done.\n");
3488 break;
3489 }
8db9d77b 3490 }
e1a44743 3491 if (tries == 5)
5eddb70b 3492 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3493
3494 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3495
8db9d77b
ZW		 3496}
3497
0206e353 3498static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3499 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3500 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3501 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3502 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3503};
3504
3505/* The FDI link training functions for SNB/Cougarpoint. */
3506static void gen6_fdi_link_train(struct drm_crtc *crtc)
3507{
3508 struct drm_device *dev = crtc->dev;
3509 struct drm_i915_private *dev_priv = dev->dev_private;
3510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3511 int pipe = intel_crtc->pipe;
fa37d39e 3512 u32 reg, temp, i, retry;
8db9d77b 3513
e1a44743
AJ		 3514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3515 for train result */
5eddb70b
CW		 3516 reg = FDI_RX_IMR(pipe);
3517 temp = I915_READ(reg);
e1a44743
AJ		 3518 temp &= ~FDI_RX_SYMBOL_LOCK;
3519 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3520 I915_WRITE(reg, temp);
3521
3522 POSTING_READ(reg);
e1a44743
AJ		 3523 udelay(150);
3524
8db9d77b 3525 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3526 reg = FDI_TX_CTL(pipe);
3527 temp = I915_READ(reg);
627eb5a3 3528 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3529 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3530 temp &= ~FDI_LINK_TRAIN_NONE;
3531 temp |= FDI_LINK_TRAIN_PATTERN_1;
3532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3533 /* SNB-B */
3534 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3535 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3536
d74cf324
DV		 3537 I915_WRITE(FDI_RX_MISC(pipe),
3538 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3539
5eddb70b
CW		 3540 reg = FDI_RX_CTL(pipe);
3541 temp = I915_READ(reg);
8db9d77b
ZW		 3542 if (HAS_PCH_CPT(dev)) {
3543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3545 } else {
3546 temp &= ~FDI_LINK_TRAIN_NONE;
3547 temp |= FDI_LINK_TRAIN_PATTERN_1;
3548 }
5eddb70b
CW		 3549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3550
3551 POSTING_READ(reg);
8db9d77b
ZW		 3552 udelay(150);
3553
0206e353 3554 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3555 reg = FDI_TX_CTL(pipe);
3556 temp = I915_READ(reg);
8db9d77b
ZW		 3557 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3558 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3559 I915_WRITE(reg, temp);
3560
3561 POSTING_READ(reg);
8db9d77b
ZW		 3562 udelay(500);
3563
fa37d39e
SP		 3564 for (retry = 0; retry < 5; retry++) {
3565 reg = FDI_RX_IIR(pipe);
3566 temp = I915_READ(reg);
3567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3568 if (temp & FDI_RX_BIT_LOCK) {
3569 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3570 DRM_DEBUG_KMS("FDI train 1 done.\n");
3571 break;
3572 }
3573 udelay(50);
8db9d77b 3574 }
fa37d39e
SP		 3575 if (retry < 5)
3576 break;
8db9d77b
ZW		 3577 }
3578 if (i == 4)
5eddb70b 3579 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3580
3581 /* Train 2 */
5eddb70b
CW		 3582 reg = FDI_TX_CTL(pipe);
3583 temp = I915_READ(reg);
8db9d77b
ZW		 3584 temp &= ~FDI_LINK_TRAIN_NONE;
3585 temp |= FDI_LINK_TRAIN_PATTERN_2;
3586 if (IS_GEN6(dev)) {
3587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3588 /* SNB-B */
3589 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3590 }
5eddb70b 3591 I915_WRITE(reg, temp);
8db9d77b 3592
5eddb70b
CW		 3593 reg = FDI_RX_CTL(pipe);
3594 temp = I915_READ(reg);
8db9d77b
ZW		 3595 if (HAS_PCH_CPT(dev)) {
3596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3597 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3598 } else {
3599 temp &= ~FDI_LINK_TRAIN_NONE;
3600 temp |= FDI_LINK_TRAIN_PATTERN_2;
3601 }
5eddb70b
CW		 3602 I915_WRITE(reg, temp);
3603
3604 POSTING_READ(reg);
8db9d77b
ZW		 3605 udelay(150);
3606
0206e353 3607 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3608 reg = FDI_TX_CTL(pipe);
3609 temp = I915_READ(reg);
8db9d77b
ZW		 3610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3611 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3612 I915_WRITE(reg, temp);
3613
3614 POSTING_READ(reg);
8db9d77b
ZW		 3615 udelay(500);
3616
fa37d39e
SP		 3617 for (retry = 0; retry < 5; retry++) {
3618 reg = FDI_RX_IIR(pipe);
3619 temp = I915_READ(reg);
3620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3621 if (temp & FDI_RX_SYMBOL_LOCK) {
3622 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3623 DRM_DEBUG_KMS("FDI train 2 done.\n");
3624 break;
3625 }
3626 udelay(50);
8db9d77b 3627 }
fa37d39e
SP		 3628 if (retry < 5)
3629 break;
8db9d77b
ZW		 3630 }
3631 if (i == 4)
5eddb70b 3632 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3633
3634 DRM_DEBUG_KMS("FDI train done.\n");
3635}
3636
357555c0
JB		 3637/* Manual link training for Ivy Bridge A0 parts */
3638static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3639{
3640 struct drm_device *dev = crtc->dev;
3641 struct drm_i915_private *dev_priv = dev->dev_private;
3642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3643 int pipe = intel_crtc->pipe;
139ccd3f 3644 u32 reg, temp, i, j;
357555c0
JB		 3645
3646 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3647 for train result */
3648 reg = FDI_RX_IMR(pipe);
3649 temp = I915_READ(reg);
3650 temp &= ~FDI_RX_SYMBOL_LOCK;
3651 temp &= ~FDI_RX_BIT_LOCK;
3652 I915_WRITE(reg, temp);
3653
3654 POSTING_READ(reg);
3655 udelay(150);
3656
01a415fd
DV		 3657 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3658 I915_READ(FDI_RX_IIR(pipe)));
3659
139ccd3f
JB		 3660 /* Try each vswing and preemphasis setting twice before moving on */
3661 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3662 /* disable first in case we need to retry */
3663 reg = FDI_TX_CTL(pipe);
3664 temp = I915_READ(reg);
3665 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3666 temp &= ~FDI_TX_ENABLE;
3667 I915_WRITE(reg, temp);
357555c0 3668
139ccd3f
JB		 3669 reg = FDI_RX_CTL(pipe);
3670 temp = I915_READ(reg);
3671 temp &= ~FDI_LINK_TRAIN_AUTO;
3672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3673 temp &= ~FDI_RX_ENABLE;
3674 I915_WRITE(reg, temp);
357555c0 3675
139ccd3f 3676 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3677 reg = FDI_TX_CTL(pipe);
3678 temp = I915_READ(reg);
139ccd3f 3679 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3680 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3681 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3682 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3683 temp |= snb_b_fdi_train_param[j/2];
3684 temp |= FDI_COMPOSITE_SYNC;
3685 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3686
139ccd3f
JB		 3687 I915_WRITE(FDI_RX_MISC(pipe),
3688 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3689
139ccd3f 3690 reg = FDI_RX_CTL(pipe);
357555c0 3691 temp = I915_READ(reg);
139ccd3f
JB		 3692 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3693 temp |= FDI_COMPOSITE_SYNC;
3694 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3695
139ccd3f
JB		 3696 POSTING_READ(reg);
3697 udelay(1); /* should be 0.5us */
357555c0 3698
139ccd3f
JB		 3699 for (i = 0; i < 4; i++) {
3700 reg = FDI_RX_IIR(pipe);
3701 temp = I915_READ(reg);
3702 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3703
139ccd3f
JB		 3704 if (temp & FDI_RX_BIT_LOCK ||
3705 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3706 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3707 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3708 i);
3709 break;
3710 }
3711 udelay(1); /* should be 0.5us */
3712 }
3713 if (i == 4) {
3714 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3715 continue;
3716 }
357555c0 3717
139ccd3f 3718 /* Train 2 */
357555c0
JB		 3719 reg = FDI_TX_CTL(pipe);
3720 temp = I915_READ(reg);
139ccd3f
JB		 3721 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3722 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3723 I915_WRITE(reg, temp);
3724
3725 reg = FDI_RX_CTL(pipe);
3726 temp = I915_READ(reg);
3727 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3728 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3729 I915_WRITE(reg, temp);
3730
3731 POSTING_READ(reg);
139ccd3f 3732 udelay(2); /* should be 1.5us */
357555c0 3733
139ccd3f
JB		 3734 for (i = 0; i < 4; i++) {
3735 reg = FDI_RX_IIR(pipe);
3736 temp = I915_READ(reg);
3737 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3738
139ccd3f
JB		 3739 if (temp & FDI_RX_SYMBOL_LOCK ||
3740 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3741 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3742 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3743 i);
3744 goto train_done;
3745 }
3746 udelay(2); /* should be 1.5us */
357555c0 3747 }
139ccd3f
JB		 3748 if (i == 4)
3749 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3750 }
357555c0 3751
139ccd3f 3752train_done:
357555c0
JB		 3753 DRM_DEBUG_KMS("FDI train done.\n");
3754}
3755
88cefb6c 3756static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3757{
88cefb6c 3758 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3759 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3760 int pipe = intel_crtc->pipe;
5eddb70b 3761 u32 reg, temp;
79e53945 3762
c64e311e 3763
c98e9dcf 3764 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3765 reg = FDI_RX_CTL(pipe);
3766 temp = I915_READ(reg);
627eb5a3 3767 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3768 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3769 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3770 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3771
3772 POSTING_READ(reg);
c98e9dcf
JB		 3773 udelay(200);
3774
3775 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3776 temp = I915_READ(reg);
3777 I915_WRITE(reg, temp | FDI_PCDCLK);
3778
3779 POSTING_READ(reg);
c98e9dcf
JB		 3780 udelay(200);
3781
20749730
PZ		 3782 /* Enable CPU FDI TX PLL, always on for Ironlake */
3783 reg = FDI_TX_CTL(pipe);
3784 temp = I915_READ(reg);
3785 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3786 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3787
20749730
PZ		 3788 POSTING_READ(reg);
3789 udelay(100);
6be4a607 3790 }
0e23b99d
JB		 3791}
3792
88cefb6c
DV		 3793static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3794{
3795 struct drm_device *dev = intel_crtc->base.dev;
3796 struct drm_i915_private *dev_priv = dev->dev_private;
3797 int pipe = intel_crtc->pipe;
3798 u32 reg, temp;
3799
3800 /* Switch from PCDclk to Rawclk */
3801 reg = FDI_RX_CTL(pipe);
3802 temp = I915_READ(reg);
3803 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3804
3805 /* Disable CPU FDI TX PLL */
3806 reg = FDI_TX_CTL(pipe);
3807 temp = I915_READ(reg);
3808 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3809
3810 POSTING_READ(reg);
3811 udelay(100);
3812
3813 reg = FDI_RX_CTL(pipe);
3814 temp = I915_READ(reg);
3815 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3816
3817 /* Wait for the clocks to turn off. */
3818 POSTING_READ(reg);
3819 udelay(100);
3820}
3821
0fc932b8
JB		 3822static void ironlake_fdi_disable(struct drm_crtc *crtc)
3823{
3824 struct drm_device *dev = crtc->dev;
3825 struct drm_i915_private *dev_priv = dev->dev_private;
3826 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3827 int pipe = intel_crtc->pipe;
3828 u32 reg, temp;
3829
3830 /* disable CPU FDI tx and PCH FDI rx */
3831 reg = FDI_TX_CTL(pipe);
3832 temp = I915_READ(reg);
3833 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3834 POSTING_READ(reg);
3835
3836 reg = FDI_RX_CTL(pipe);
3837 temp = I915_READ(reg);
3838 temp &= ~(0x7 << 16);
dfd07d72 3839 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3840 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3841
3842 POSTING_READ(reg);
3843 udelay(100);
3844
3845 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3846 if (HAS_PCH_IBX(dev))
6f06ce18 3847 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3848
3849 /* still set train pattern 1 */
3850 reg = FDI_TX_CTL(pipe);
3851 temp = I915_READ(reg);
3852 temp &= ~FDI_LINK_TRAIN_NONE;
3853 temp |= FDI_LINK_TRAIN_PATTERN_1;
3854 I915_WRITE(reg, temp);
3855
3856 reg = FDI_RX_CTL(pipe);
3857 temp = I915_READ(reg);
3858 if (HAS_PCH_CPT(dev)) {
3859 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3860 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3861 } else {
3862 temp &= ~FDI_LINK_TRAIN_NONE;
3863 temp |= FDI_LINK_TRAIN_PATTERN_1;
3864 }
3865 /* BPC in FDI rx is consistent with that in PIPECONF */
3866 temp &= ~(0x07 << 16);
dfd07d72 3867 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3868 I915_WRITE(reg, temp);
3869
3870 POSTING_READ(reg);
3871 udelay(100);
3872}
3873
5dce5b93
CW		 3874bool intel_has_pending_fb_unpin(struct drm_device *dev)
3875{
3876 struct intel_crtc *crtc;
3877
3878 /* Note that we don't need to be called with mode_config.lock here
3879 * as our list of CRTC objects is static for the lifetime of the
3880 * device and so cannot disappear as we iterate. Similarly, we can
3881 * happily treat the predicates as racy, atomic checks as userspace
3882 * cannot claim and pin a new fb without at least acquring the
3883 * struct_mutex and so serialising with us.
3884 */
d3fcc808 3885 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3886 if (atomic_read(&crtc->unpin_work_count) == 0)
3887 continue;
3888
3889 if (crtc->unpin_work)
3890 intel_wait_for_vblank(dev, crtc->pipe);
3891
3892 return true;
3893 }
3894
3895 return false;
3896}
3897
d6bbafa1
CW		 3898static void page_flip_completed(struct intel_crtc *intel_crtc)
3899{
3900 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3901 struct intel_unpin_work *work = intel_crtc->unpin_work;
3902
3903 /* ensure that the unpin work is consistent wrt ->pending. */
3904 smp_rmb();
3905 intel_crtc->unpin_work = NULL;
3906
3907 if (work->event)
3908 drm_send_vblank_event(intel_crtc->base.dev,
3909 intel_crtc->pipe,
3910 work->event);
3911
3912 drm_crtc_vblank_put(&intel_crtc->base);
3913
3914 wake_up_all(&dev_priv->pending_flip_queue);
3915 queue_work(dev_priv->wq, &work->work);
3916
3917 trace_i915_flip_complete(intel_crtc->plane,
3918 work->pending_flip_obj);
3919}
3920
46a55d30 3921void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3922{
0f91128d 3923 struct drm_device *dev = crtc->dev;
5bb61643 3924 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3925
2c10d571 3926 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3927 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3928 !intel_crtc_has_pending_flip(crtc),
3929 60*HZ) == 0)) {
3930 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3931
5e2d7afc 3932 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3933 if (intel_crtc->unpin_work) {
3934 WARN_ONCE(1, "Removing stuck page flip\n");
3935 page_flip_completed(intel_crtc);
3936 }
5e2d7afc 3937 spin_unlock_irq(&dev->event_lock);
9c787942 3938 }
5bb61643 3939
975d568a
CW		 3940 if (crtc->primary->fb) {
3941 mutex_lock(&dev->struct_mutex);
3942 intel_finish_fb(crtc->primary->fb);
3943 mutex_unlock(&dev->struct_mutex);
3944 }
e6c3a2a6
CW		 3945}
3946
e615efe4
ED		 3947/* Program iCLKIP clock to the desired frequency */
3948static void lpt_program_iclkip(struct drm_crtc *crtc)
3949{
3950 struct drm_device *dev = crtc->dev;
3951 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3952 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3953 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3954 u32 temp;
3955
09153000
DV		 3956 mutex_lock(&dev_priv->dpio_lock);
3957
e615efe4
ED		 3958 /* It is necessary to ungate the pixclk gate prior to programming
3959 * the divisors, and gate it back when it is done.
3960 */
3961 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3962
3963 /* Disable SSCCTL */
3964 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3965 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3966 SBI_SSCCTL_DISABLE,
3967 SBI_ICLK);
e615efe4
ED		 3968
3969 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3970 if (clock == 20000) {
e615efe4
ED		 3971 auxdiv = 1;
3972 divsel = 0x41;
3973 phaseinc = 0x20;
3974 } else {
3975 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3976 * but the adjusted_mode->crtc_clock in in KHz. To get the
3977 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3978 * convert the virtual clock precision to KHz here for higher
3979 * precision.
3980 */
3981 u32 iclk_virtual_root_freq = 172800 * 1000;
3982 u32 iclk_pi_range = 64;
3983 u32 desired_divisor, msb_divisor_value, pi_value;
3984
12d7ceed 3985 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3986 msb_divisor_value = desired_divisor / iclk_pi_range;
3987 pi_value = desired_divisor % iclk_pi_range;
3988
3989 auxdiv = 0;
3990 divsel = msb_divisor_value - 2;
3991 phaseinc = pi_value;
3992 }
3993
3994 /* This should not happen with any sane values */
3995 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3996 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3997 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3998 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3999
4000 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 4001 clock,
e615efe4
ED		 4002 auxdiv,
4003 divsel,
4004 phasedir,
4005 phaseinc);
4006
4007 /* Program SSCDIVINTPHASE6 */
988d6ee8 4008 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 4009 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
4010 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
4011 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
4012 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
4013 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
4014 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 4015 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 4016
4017 /* Program SSCAUXDIV */
988d6ee8 4018 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 4019 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
4020 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 4021 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 4022
4023 /* Enable modulator and associated divider */
988d6ee8 4024 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 4025 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 4026 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 4027
4028 /* Wait for initialization time */
4029 udelay(24);
4030
4031 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 4032
4033 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 4034}
4035
275f01b2
DV		 4036static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
4037 enum pipe pch_transcoder)
4038{
4039 struct drm_device *dev = crtc->base.dev;
4040 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4041 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 4042
4043 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
4044 I915_READ(HTOTAL(cpu_transcoder)));
4045 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
4046 I915_READ(HBLANK(cpu_transcoder)));
4047 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
4048 I915_READ(HSYNC(cpu_transcoder)));
4049
4050 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
4051 I915_READ(VTOTAL(cpu_transcoder)));
4052 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
4053 I915_READ(VBLANK(cpu_transcoder)));
4054 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
4055 I915_READ(VSYNC(cpu_transcoder)));
4056 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
4057 I915_READ(VSYNCSHIFT(cpu_transcoder)));
4058}
4059
003632d9 4060static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 4061{
4062 struct drm_i915_private *dev_priv = dev->dev_private;
4063 uint32_t temp;
4064
4065 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 4066 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 4067 return;
4068
4069 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
4070 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
4071
003632d9
ACO		 4072 temp &= ~FDI_BC_BIFURCATION_SELECT;
4073 if (enable)
4074 temp |= FDI_BC_BIFURCATION_SELECT;
4075
4076 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 4077 I915_WRITE(SOUTH_CHICKEN1, temp);
4078 POSTING_READ(SOUTH_CHICKEN1);
4079}
4080
4081static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
4082{
4083 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 4084
4085 switch (intel_crtc->pipe) {
4086 case PIPE_A:
4087 break;
4088 case PIPE_B:
6e3c9717 4089 if (intel_crtc->config->fdi_lanes > 2)
003632d9 4090 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 4091 else
003632d9 4092 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4093
4094 break;
4095 case PIPE_C:
003632d9 4096 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 4097
4098 break;
4099 default:
4100 BUG();
4101 }
4102}
4103
f67a559d
JB		 4104/*
4105 * Enable PCH resources required for PCH ports:
4106 * - PCH PLLs
4107 * - FDI training & RX/TX
4108 * - update transcoder timings
4109 * - DP transcoding bits
4110 * - transcoder
4111 */
4112static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 4113{
4114 struct drm_device *dev = crtc->dev;
4115 struct drm_i915_private *dev_priv = dev->dev_private;
4116 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4117 int pipe = intel_crtc->pipe;
ee7b9f93 4118 u32 reg, temp;
2c07245f 4119
ab9412ba 4120 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 4121
1fbc0d78
DV		 4122 if (IS_IVYBRIDGE(dev))
4123 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
4124
cd986abb
DV		 4125 /* Write the TU size bits before fdi link training, so that error
4126 * detection works. */
4127 I915_WRITE(FDI_RX_TUSIZE1(pipe),
4128 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
4129
c98e9dcf 4130 /* For PCH output, training FDI link */
674cf967 4131 dev_priv->display.fdi_link_train(crtc);
2c07245f 4132
3ad8a208
DV		 4133 /* We need to program the right clock selection before writing the pixel
4134 * mutliplier into the DPLL. */
303b81e0 4135 if (HAS_PCH_CPT(dev)) {
ee7b9f93 4136 u32 sel;
4b645f14 4137
c98e9dcf 4138 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 4139 temp |= TRANS_DPLL_ENABLE(pipe);
4140 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 4141 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 4142 temp |= sel;
4143 else
4144 temp &= ~sel;
c98e9dcf 4145 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 4146 }
5eddb70b 4147
3ad8a208
DV		 4148 /* XXX: pch pll's can be enabled any time before we enable the PCH
4149 * transcoder, and we actually should do this to not upset any PCH
4150 * transcoder that already use the clock when we share it.
4151 *
4152 * Note that enable_shared_dpll tries to do the right thing, but
4153 * get_shared_dpll unconditionally resets the pll - we need that to have
4154 * the right LVDS enable sequence. */
85b3894f 4155 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4156
d9b6cb56
JB		 4157 /* set transcoder timing, panel must allow it */
4158 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4159 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4160
303b81e0 4161 intel_fdi_normal_train(crtc);
5e84e1a4 4162
c98e9dcf 4163 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4164 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4165 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4166 reg = TRANS_DP_CTL(pipe);
4167 temp = I915_READ(reg);
4168 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4169 TRANS_DP_SYNC_MASK |
4170 TRANS_DP_BPC_MASK);
5eddb70b
CW		 4171 temp |= (TRANS_DP_OUTPUT_ENABLE |
4172 TRANS_DP_ENH_FRAMING);
9325c9f0 4173 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4174
4175 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4176 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4177 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4178 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4179
4180 switch (intel_trans_dp_port_sel(crtc)) {
4181 case PCH_DP_B:
5eddb70b 4182 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4183 break;
4184 case PCH_DP_C:
5eddb70b 4185 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4186 break;
4187 case PCH_DP_D:
5eddb70b 4188 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4189 break;
4190 default:
e95d41e1 4191 BUG();
32f9d658 4192 }
2c07245f 4193
5eddb70b 4194 I915_WRITE(reg, temp);
6be4a607 4195 }
b52eb4dc 4196
b8a4f404 4197 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4198}
4199
1507e5bd
PZ		 4200static void lpt_pch_enable(struct drm_crtc *crtc)
4201{
4202 struct drm_device *dev = crtc->dev;
4203 struct drm_i915_private *dev_priv = dev->dev_private;
4204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4205 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4206
ab9412ba 4207 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4208
8c52b5e8 4209 lpt_program_iclkip(crtc);
1507e5bd 4210
0540e488 4211 /* Set transcoder timing. */
275f01b2 4212 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4213
937bb610 4214 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4215}
4216
716c2e55 4217void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 4218{
e2b78267 4219 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 4220
4221 if (pll == NULL)
4222 return;
4223
3e369b76 4224 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
1e6f2ddc 4225 WARN(1, "bad %s crtc mask\n", pll->name);
ee7b9f93
JB		 4226 return;
4227 }
4228
3e369b76
ACO		 4229 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4230 if (pll->config.crtc_mask == 0) {
f4a091c7
DV		 4231 WARN_ON(pll->on);
4232 WARN_ON(pll->active);
4233 }
4234
6e3c9717 4235 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 4236}
4237
190f68c5
ACO		 4238struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4239 struct intel_crtc_state *crtc_state)
ee7b9f93 4240{
e2b78267 4241 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4242 struct intel_shared_dpll *pll;
e2b78267 4243 enum intel_dpll_id i;
ee7b9f93 4244
98b6bd99
DV		 4245 if (HAS_PCH_IBX(dev_priv->dev)) {
4246 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4247 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4248 pll = &dev_priv->shared_dplls[i];
98b6bd99 4249
46edb027
DV		 4250 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4251 crtc->base.base.id, pll->name);
98b6bd99 4252
8bd31e67 4253 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4254
98b6bd99
DV		 4255 goto found;
4256 }
4257
bcddf610
S		 4258 if (IS_BROXTON(dev_priv->dev)) {
4259 /* PLL is attached to port in bxt */
4260 struct intel_encoder *encoder;
4261 struct intel_digital_port *intel_dig_port;
4262
4263 encoder = intel_ddi_get_crtc_new_encoder(crtc_state);
4264 if (WARN_ON(!encoder))
4265 return NULL;
4266
4267 intel_dig_port = enc_to_dig_port(&encoder->base);
4268 /* 1:1 mapping between ports and PLLs */
4269 i = (enum intel_dpll_id)intel_dig_port->port;
4270 pll = &dev_priv->shared_dplls[i];
4271 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4272 crtc->base.base.id, pll->name);
4273 WARN_ON(pll->new_config->crtc_mask);
4274
4275 goto found;
4276 }
4277
e72f9fbf
DV		 4278 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4279 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4280
4281 /* Only want to check enabled timings first */
8bd31e67 4282 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4283 continue;
4284
190f68c5 4285 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4286 &pll->new_config->hw_state,
4287 sizeof(pll->new_config->hw_state)) == 0) {
4288 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4289 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4290 pll->new_config->crtc_mask,
4291 pll->active);
ee7b9f93
JB		 4292 goto found;
4293 }
4294 }
4295
4296 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4297 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4298 pll = &dev_priv->shared_dplls[i];
8bd31e67 4299 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4300 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4301 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4302 goto found;
4303 }
4304 }
4305
4306 return NULL;
4307
4308found:
8bd31e67 4309 if (pll->new_config->crtc_mask == 0)
190f68c5 4310 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4311
190f68c5 4312 crtc_state->shared_dpll = i;
46edb027
DV		 4313 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4314 pipe_name(crtc->pipe));
ee7b9f93 4315
8bd31e67 4316 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4317
ee7b9f93
JB		 4318 return pll;
4319}
4320
8bd31e67
ACO		 4321/**
4322 * intel_shared_dpll_start_config - start a new PLL staged config
4323 * @dev_priv: DRM device
4324 * @clear_pipes: mask of pipes that will have their PLLs freed
4325 *
4326 * Starts a new PLL staged config, copying the current config but
4327 * releasing the references of pipes specified in clear_pipes.
4328 */
4329static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4330 unsigned clear_pipes)
4331{
4332 struct intel_shared_dpll *pll;
4333 enum intel_dpll_id i;
4334
4335 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4336 pll = &dev_priv->shared_dplls[i];
4337
4338 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4339 GFP_KERNEL);
4340 if (!pll->new_config)
4341 goto cleanup;
4342
4343 pll->new_config->crtc_mask &= ~clear_pipes;
4344 }
4345
4346 return 0;
4347
4348cleanup:
4349 while (--i >= 0) {
4350 pll = &dev_priv->shared_dplls[i];
f354d733 4351 kfree(pll->new_config);
8bd31e67
ACO		 4352 pll->new_config = NULL;
4353 }
4354
4355 return -ENOMEM;
4356}
4357
4358static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4359{
4360 struct intel_shared_dpll *pll;
4361 enum intel_dpll_id i;
4362
4363 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4364 pll = &dev_priv->shared_dplls[i];
4365
4366 WARN_ON(pll->new_config == &pll->config);
4367
4368 pll->config = *pll->new_config;
4369 kfree(pll->new_config);
4370 pll->new_config = NULL;
4371 }
4372}
4373
4374static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4375{
4376 struct intel_shared_dpll *pll;
4377 enum intel_dpll_id i;
4378
4379 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4380 pll = &dev_priv->shared_dplls[i];
4381
4382 WARN_ON(pll->new_config == &pll->config);
4383
4384 kfree(pll->new_config);
4385 pll->new_config = NULL;
4386 }
4387}
4388
a1520318 4389static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4390{
4391 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4392 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4393 u32 temp;
4394
4395 temp = I915_READ(dslreg);
4396 udelay(500);
4397 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4398 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4399 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4400 }
4401}
4402
a1b2278e
CK		 4403/**
4404 * skl_update_scaler_users - Stages update to crtc's scaler state
4405 * @intel_crtc: crtc
4406 * @crtc_state: crtc_state
4407 * @plane: plane (NULL indicates crtc is requesting update)
4408 * @plane_state: plane's state
4409 * @force_detach: request unconditional detachment of scaler
4410 *
4411 * This function updates scaler state for requested plane or crtc.
4412 * To request scaler usage update for a plane, caller shall pass plane pointer.
4413 * To request scaler usage update for crtc, caller shall pass plane pointer
4414 * as NULL.
4415 *
4416 * Return
4417 * 0 - scaler_usage updated successfully
4418 * error - requested scaling cannot be supported or other error condition
4419 */
4420int
4421skl_update_scaler_users(
4422 struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state,
4423 struct intel_plane *intel_plane, struct intel_plane_state *plane_state,
4424 int force_detach)
4425{
4426 int need_scaling;
4427 int idx;
4428 int src_w, src_h, dst_w, dst_h;
4429 int *scaler_id;
4430 struct drm_framebuffer *fb;
4431 struct intel_crtc_scaler_state *scaler_state;
6156a456 4432 unsigned int rotation;
a1b2278e
CK		 4433
4434 if (!intel_crtc || !crtc_state)
4435 return 0;
4436
4437 scaler_state = &crtc_state->scaler_state;
4438
4439 idx = intel_plane ? drm_plane_index(&intel_plane->base) : SKL_CRTC_INDEX;
4440 fb = intel_plane ? plane_state->base.fb : NULL;
4441
4442 if (intel_plane) {
4443 src_w = drm_rect_width(&plane_state->src) >> 16;
4444 src_h = drm_rect_height(&plane_state->src) >> 16;
4445 dst_w = drm_rect_width(&plane_state->dst);
4446 dst_h = drm_rect_height(&plane_state->dst);
4447 scaler_id = &plane_state->scaler_id;
6156a456 4448 rotation = plane_state->base.rotation;
a1b2278e
CK		 4449 } else {
4450 struct drm_display_mode *adjusted_mode =
4451 &crtc_state->base.adjusted_mode;
4452 src_w = crtc_state->pipe_src_w;
4453 src_h = crtc_state->pipe_src_h;
4454 dst_w = adjusted_mode->hdisplay;
4455 dst_h = adjusted_mode->vdisplay;
4456 scaler_id = &scaler_state->scaler_id;
6156a456 4457 rotation = DRM_ROTATE_0;
a1b2278e 4458 }
6156a456
CK		 4459
4460 need_scaling = intel_rotation_90_or_270(rotation) ?
4461 (src_h != dst_w || src_w != dst_h):
4462 (src_w != dst_w || src_h != dst_h);
a1b2278e
CK		 4463
4464 /*
4465 * if plane is being disabled or scaler is no more required or force detach
4466 * - free scaler binded to this plane/crtc
4467 * - in order to do this, update crtc->scaler_usage
4468 *
4469 * Here scaler state in crtc_state is set free so that
4470 * scaler can be assigned to other user. Actual register
4471 * update to free the scaler is done in plane/panel-fit programming.
4472 * For this purpose crtc/plane_state->scaler_id isn't reset here.
4473 */
4474 if (force_detach || !need_scaling || (intel_plane &&
4475 (!fb || !plane_state->visible))) {
4476 if (*scaler_id >= 0) {
4477 scaler_state->scaler_users &= ~(1 << idx);
4478 scaler_state->scalers[*scaler_id].in_use = 0;
4479
4480 DRM_DEBUG_KMS("Staged freeing scaler id %d.%d from %s:%d "
4481 "crtc_state = %p scaler_users = 0x%x\n",
4482 intel_crtc->pipe, *scaler_id, intel_plane ? "PLANE" : "CRTC",
4483 intel_plane ? intel_plane->base.base.id :
4484 intel_crtc->base.base.id, crtc_state,
4485 scaler_state->scaler_users);
4486 *scaler_id = -1;
4487 }
4488 return 0;
4489 }
4490
4491 /* range checks */
4492 if (src_w < SKL_MIN_SRC_W || src_h < SKL_MIN_SRC_H ||
4493 dst_w < SKL_MIN_DST_W || dst_h < SKL_MIN_DST_H ||
4494
4495 src_w > SKL_MAX_SRC_W || src_h > SKL_MAX_SRC_H ||
4496 dst_w > SKL_MAX_DST_W || dst_h > SKL_MAX_DST_H) {
4497 DRM_DEBUG_KMS("%s:%d scaler_user index %u.%u: src %ux%u dst %ux%u "
4498 "size is out of scaler range\n",
4499 intel_plane ? "PLANE" : "CRTC",
4500 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4501 intel_crtc->pipe, idx, src_w, src_h, dst_w, dst_h);
4502 return -EINVAL;
4503 }
4504
4505 /* check colorkey */
4506 if (intel_plane && intel_plane->ckey.flags != I915_SET_COLORKEY_NONE) {
4507 DRM_DEBUG_KMS("PLANE:%d scaling with color key not allowed",
4508 intel_plane->base.base.id);
4509 return -EINVAL;
4510 }
4511
4512 /* Check src format */
4513 if (intel_plane) {
4514 switch (fb->pixel_format) {
4515 case DRM_FORMAT_RGB565:
4516 case DRM_FORMAT_XBGR8888:
4517 case DRM_FORMAT_XRGB8888:
4518 case DRM_FORMAT_ABGR8888:
4519 case DRM_FORMAT_ARGB8888:
4520 case DRM_FORMAT_XRGB2101010:
a1b2278e 4521 case DRM_FORMAT_XBGR2101010:
a1b2278e
CK		 4522 case DRM_FORMAT_YUYV:
4523 case DRM_FORMAT_YVYU:
4524 case DRM_FORMAT_UYVY:
4525 case DRM_FORMAT_VYUY:
4526 break;
4527 default:
4528 DRM_DEBUG_KMS("PLANE:%d FB:%d unsupported scaling format 0x%x\n",
4529 intel_plane->base.base.id, fb->base.id, fb->pixel_format);
4530 return -EINVAL;
4531 }
4532 }
4533
4534 /* mark this plane as a scaler user in crtc_state */
4535 scaler_state->scaler_users |= (1 << idx);
4536 DRM_DEBUG_KMS("%s:%d staged scaling request for %ux%u->%ux%u "
4537 "crtc_state = %p scaler_users = 0x%x\n",
4538 intel_plane ? "PLANE" : "CRTC",
4539 intel_plane ? intel_plane->base.base.id : intel_crtc->base.base.id,
4540 src_w, src_h, dst_w, dst_h, crtc_state, scaler_state->scaler_users);
4541 return 0;
4542}
4543
4544static void skylake_pfit_update(struct intel_crtc *crtc, int enable)
bd2e244f
JB		 4545{
4546 struct drm_device *dev = crtc->base.dev;
4547 struct drm_i915_private *dev_priv = dev->dev_private;
4548 int pipe = crtc->pipe;
a1b2278e
CK		 4549 struct intel_crtc_scaler_state *scaler_state =
4550 &crtc->config->scaler_state;
4551
4552 DRM_DEBUG_KMS("for crtc_state = %p\n", crtc->config);
4553
4554 /* To update pfit, first update scaler state */
4555 skl_update_scaler_users(crtc, crtc->config, NULL, NULL, !enable);
4556 intel_atomic_setup_scalers(crtc->base.dev, crtc, crtc->config);
4557 skl_detach_scalers(crtc);
4558 if (!enable)
4559 return;
bd2e244f 4560
6e3c9717 4561 if (crtc->config->pch_pfit.enabled) {
a1b2278e
CK		 4562 int id;
4563
4564 if (WARN_ON(crtc->config->scaler_state.scaler_id < 0)) {
4565 DRM_ERROR("Requesting pfit without getting a scaler first\n");
4566 return;
4567 }
4568
4569 id = scaler_state->scaler_id;
4570 I915_WRITE(SKL_PS_CTRL(pipe, id), PS_SCALER_EN |
4571 PS_FILTER_MEDIUM | scaler_state->scalers[id].mode);
4572 I915_WRITE(SKL_PS_WIN_POS(pipe, id), crtc->config->pch_pfit.pos);
4573 I915_WRITE(SKL_PS_WIN_SZ(pipe, id), crtc->config->pch_pfit.size);
4574
4575 DRM_DEBUG_KMS("for crtc_state = %p scaler_id = %d\n", crtc->config, id);
bd2e244f
JB		 4576 }
4577}
4578
b074cec8
JB		 4579static void ironlake_pfit_enable(struct intel_crtc *crtc)
4580{
4581 struct drm_device *dev = crtc->base.dev;
4582 struct drm_i915_private *dev_priv = dev->dev_private;
4583 int pipe = crtc->pipe;
4584
6e3c9717 4585 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4586 /* Force use of hard-coded filter coefficients
4587 * as some pre-programmed values are broken,
4588 * e.g. x201.
4589 */
4590 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4591 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4592 PF_PIPE_SEL_IVB(pipe));
4593 else
4594 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4595 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4596 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4597 }
4598}
4599
4a3b8769 4600static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4601{
4602 struct drm_device *dev = crtc->dev;
4603 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4604 struct drm_plane *plane;
bb53d4ae
VS		 4605 struct intel_plane *intel_plane;
4606
af2b653b
MR		 4607 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4608 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4609 if (intel_plane->pipe == pipe)
4610 intel_plane_restore(&intel_plane->base);
af2b653b 4611 }
bb53d4ae
VS		 4612}
4613
20bc8673 4614void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4615{
cea165c3
VS		 4616 struct drm_device *dev = crtc->base.dev;
4617 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4618
6e3c9717 4619 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4620 return;
4621
cea165c3
VS		 4622 /* We can only enable IPS after we enable a plane and wait for a vblank */
4623 intel_wait_for_vblank(dev, crtc->pipe);
4624
d77e4531 4625 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4626 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4627 mutex_lock(&dev_priv->rps.hw_lock);
4628 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4629 mutex_unlock(&dev_priv->rps.hw_lock);
4630 /* Quoting Art Runyan: "its not safe to expect any particular
4631 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4632 * mailbox." Moreover, the mailbox may return a bogus state,
4633 * so we need to just enable it and continue on.
2a114cc1
BW		 4634 */
4635 } else {
4636 I915_WRITE(IPS_CTL, IPS_ENABLE);
4637 /* The bit only becomes 1 in the next vblank, so this wait here
4638 * is essentially intel_wait_for_vblank. If we don't have this
4639 * and don't wait for vblanks until the end of crtc_enable, then
4640 * the HW state readout code will complain that the expected
4641 * IPS_CTL value is not the one we read. */
4642 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4643 DRM_ERROR("Timed out waiting for IPS enable\n");
4644 }
d77e4531
PZ		 4645}
4646
20bc8673 4647void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4648{
4649 struct drm_device *dev = crtc->base.dev;
4650 struct drm_i915_private *dev_priv = dev->dev_private;
4651
6e3c9717 4652 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4653 return;
4654
4655 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4656 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4657 mutex_lock(&dev_priv->rps.hw_lock);
4658 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4659 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4660 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4661 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4662 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4663 } else {
2a114cc1 4664 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4665 POSTING_READ(IPS_CTL);
4666 }
d77e4531
PZ		 4667
4668 /* We need to wait for a vblank before we can disable the plane. */
4669 intel_wait_for_vblank(dev, crtc->pipe);
4670}
4671
4672/** Loads the palette/gamma unit for the CRTC with the prepared values */
4673static void intel_crtc_load_lut(struct drm_crtc *crtc)
4674{
4675 struct drm_device *dev = crtc->dev;
4676 struct drm_i915_private *dev_priv = dev->dev_private;
4677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4678 enum pipe pipe = intel_crtc->pipe;
4679 int palreg = PALETTE(pipe);
4680 int i;
4681 bool reenable_ips = false;
4682
4683 /* The clocks have to be on to load the palette. */
83d65738 4684 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4685 return;
4686
50360403 4687 if (HAS_GMCH_DISPLAY(dev_priv->dev)) {
409ee761 4688 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4689 assert_dsi_pll_enabled(dev_priv);
4690 else
4691 assert_pll_enabled(dev_priv, pipe);
4692 }
4693
4694 /* use legacy palette for Ironlake */
7a1db49a 4695 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4696 palreg = LGC_PALETTE(pipe);
4697
4698 /* Workaround : Do not read or write the pipe palette/gamma data while
4699 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4700 */
6e3c9717 4701 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4702 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4703 GAMMA_MODE_MODE_SPLIT)) {
4704 hsw_disable_ips(intel_crtc);
4705 reenable_ips = true;
4706 }
4707
4708 for (i = 0; i < 256; i++) {
4709 I915_WRITE(palreg + 4 * i,
4710 (intel_crtc->lut_r[i] << 16) |
4711 (intel_crtc->lut_g[i] << 8) |
4712 intel_crtc->lut_b[i]);
4713 }
4714
4715 if (reenable_ips)
4716 hsw_enable_ips(intel_crtc);
4717}
4718
7cac945f 4719static void intel_crtc_dpms_overlay_disable(struct intel_crtc *intel_crtc)
d3eedb1a 4720{
7cac945f 4721 if (intel_crtc->overlay) {
d3eedb1a
VS		 4722 struct drm_device *dev = intel_crtc->base.dev;
4723 struct drm_i915_private *dev_priv = dev->dev_private;
4724
4725 mutex_lock(&dev->struct_mutex);
4726 dev_priv->mm.interruptible = false;
4727 (void) intel_overlay_switch_off(intel_crtc->overlay);
4728 dev_priv->mm.interruptible = true;
4729 mutex_unlock(&dev->struct_mutex);
4730 }
4731
4732 /* Let userspace switch the overlay on again. In most cases userspace
4733 * has to recompute where to put it anyway.
4734 */
4735}
4736
87d4300a
ML		 4737/**
4738 * intel_post_enable_primary - Perform operations after enabling primary plane
4739 * @crtc: the CRTC whose primary plane was just enabled
4740 *
4741 * Performs potentially sleeping operations that must be done after the primary
4742 * plane is enabled, such as updating FBC and IPS. Note that this may be
4743 * called due to an explicit primary plane update, or due to an implicit
4744 * re-enable that is caused when a sprite plane is updated to no longer
4745 * completely hide the primary plane.
4746 */
4747static void
4748intel_post_enable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4749{
4750 struct drm_device *dev = crtc->dev;
87d4300a 4751 struct drm_i915_private *dev_priv = dev->dev_private;
a5c4d7bc
VS		 4752 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4753 int pipe = intel_crtc->pipe;
a5c4d7bc 4754
87d4300a
ML		 4755 /*
4756 * BDW signals flip done immediately if the plane
4757 * is disabled, even if the plane enable is already
4758 * armed to occur at the next vblank :(
4759 */
4760 if (IS_BROADWELL(dev))
4761 intel_wait_for_vblank(dev, pipe);
a5c4d7bc 4762
87d4300a
ML		 4763 /*
4764 * FIXME IPS should be fine as long as one plane is
4765 * enabled, but in practice it seems to have problems
4766 * when going from primary only to sprite only and vice
4767 * versa.
4768 */
a5c4d7bc
VS		 4769 hsw_enable_ips(intel_crtc);
4770
4771 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4772 intel_fbc_update(dev);
a5c4d7bc 4773 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4774
4775 /*
87d4300a
ML		 4776 * Gen2 reports pipe underruns whenever all planes are disabled.
4777 * So don't enable underrun reporting before at least some planes
4778 * are enabled.
4779 * FIXME: Need to fix the logic to work when we turn off all planes
4780 * but leave the pipe running.
f99d7069 4781 */
87d4300a
ML		 4782 if (IS_GEN2(dev))
4783 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4784
4785 /* Underruns don't raise interrupts, so check manually. */
4786 if (HAS_GMCH_DISPLAY(dev))
4787 i9xx_check_fifo_underruns(dev_priv);
a5c4d7bc
VS		 4788}
4789
87d4300a
ML		 4790/**
4791 * intel_pre_disable_primary - Perform operations before disabling primary plane
4792 * @crtc: the CRTC whose primary plane is to be disabled
4793 *
4794 * Performs potentially sleeping operations that must be done before the
4795 * primary plane is disabled, such as updating FBC and IPS. Note that this may
4796 * be called due to an explicit primary plane update, or due to an implicit
4797 * disable that is caused when a sprite plane completely hides the primary
4798 * plane.
4799 */
4800static void
4801intel_pre_disable_primary(struct drm_crtc *crtc)
a5c4d7bc
VS		 4802{
4803 struct drm_device *dev = crtc->dev;
4804 struct drm_i915_private *dev_priv = dev->dev_private;
4805 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4806 int pipe = intel_crtc->pipe;
a5c4d7bc 4807
87d4300a
ML		 4808 /*
4809 * Gen2 reports pipe underruns whenever all planes are disabled.
4810 * So diasble underrun reporting before all the planes get disabled.
4811 * FIXME: Need to fix the logic to work when we turn off all planes
4812 * but leave the pipe running.
4813 */
4814 if (IS_GEN2(dev))
4815 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
a5c4d7bc 4816
87d4300a
ML		 4817 /*
4818 * Vblank time updates from the shadow to live plane control register
4819 * are blocked if the memory self-refresh mode is active at that
4820 * moment. So to make sure the plane gets truly disabled, disable
4821 * first the self-refresh mode. The self-refresh enable bit in turn
4822 * will be checked/applied by the HW only at the next frame start
4823 * event which is after the vblank start event, so we need to have a
4824 * wait-for-vblank between disabling the plane and the pipe.
4825 */
4826 if (HAS_GMCH_DISPLAY(dev))
4827 intel_set_memory_cxsr(dev_priv, false);
4828
4829 mutex_lock(&dev->struct_mutex);
e35fef21 4830 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4831 intel_fbc_disable(dev);
87d4300a 4832 mutex_unlock(&dev->struct_mutex);
a5c4d7bc 4833
87d4300a
ML		 4834 /*
4835 * FIXME IPS should be fine as long as one plane is
4836 * enabled, but in practice it seems to have problems
4837 * when going from primary only to sprite only and vice
4838 * versa.
4839 */
a5c4d7bc 4840 hsw_disable_ips(intel_crtc);
87d4300a
ML		 4841}
4842
4843static void intel_crtc_enable_planes(struct drm_crtc *crtc)
4844{
87d4300a
ML		 4845 intel_enable_primary_hw_plane(crtc->primary, crtc);
4846 intel_enable_sprite_planes(crtc);
4847 intel_crtc_update_cursor(crtc, true);
87d4300a
ML		 4848
4849 intel_post_enable_primary(crtc);
4850}
4851
4852static void intel_crtc_disable_planes(struct drm_crtc *crtc)
4853{
4854 struct drm_device *dev = crtc->dev;
4855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4856 struct intel_plane *intel_plane;
4857 int pipe = intel_crtc->pipe;
4858
4859 intel_crtc_wait_for_pending_flips(crtc);
4860
4861 intel_pre_disable_primary(crtc);
a5c4d7bc 4862
7cac945f 4863 intel_crtc_dpms_overlay_disable(intel_crtc);
27321ae8
ML		 4864 for_each_intel_plane(dev, intel_plane) {
4865 if (intel_plane->pipe == pipe) {
4866 struct drm_crtc *from = intel_plane->base.crtc;
4867
4868 intel_plane->disable_plane(&intel_plane->base,
4869 from ?: crtc, true);
4870 }
4871 }
f98551ae 4872
f99d7069
DV		 4873 /*
4874 * FIXME: Once we grow proper nuclear flip support out of this we need
4875 * to compute the mask of flip planes precisely. For the time being
4876 * consider this a flip to a NULL plane.
4877 */
4878 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4879}
4880
f67a559d
JB		 4881static void ironlake_crtc_enable(struct drm_crtc *crtc)
4882{
4883 struct drm_device *dev = crtc->dev;
4884 struct drm_i915_private *dev_priv = dev->dev_private;
4885 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4886 struct intel_encoder *encoder;
f67a559d 4887 int pipe = intel_crtc->pipe;
f67a559d 4888
83d65738 4889 WARN_ON(!crtc->state->enable);
08a48469 4890
f67a559d
JB		 4891 if (intel_crtc->active)
4892 return;
4893
6e3c9717 4894 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4895 intel_prepare_shared_dpll(intel_crtc);
4896
6e3c9717 4897 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4898 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4899
4900 intel_set_pipe_timings(intel_crtc);
4901
6e3c9717 4902 if (intel_crtc->config->has_pch_encoder) {
29407aab 4903 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4904 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4905 }
4906
4907 ironlake_set_pipeconf(crtc);
4908
f67a559d 4909 intel_crtc->active = true;
8664281b 4910
a72e4c9f
DV		 4911 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4912 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4913
f6736a1a 4914 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4915 if (encoder->pre_enable)
4916 encoder->pre_enable(encoder);
f67a559d 4917
6e3c9717 4918 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4919 /* Note: FDI PLL enabling _must_ be done before we enable the
4920 * cpu pipes, hence this is separate from all the other fdi/pch
4921 * enabling. */
88cefb6c 4922 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4923 } else {
4924 assert_fdi_tx_disabled(dev_priv, pipe);
4925 assert_fdi_rx_disabled(dev_priv, pipe);
4926 }
f67a559d 4927
b074cec8 4928 ironlake_pfit_enable(intel_crtc);
f67a559d 4929
9c54c0dd
JB		 4930 /*
4931 * On ILK+ LUT must be loaded before the pipe is running but with
4932 * clocks enabled
4933 */
4934 intel_crtc_load_lut(crtc);
4935
f37fcc2a 4936 intel_update_watermarks(crtc);
e1fdc473 4937 intel_enable_pipe(intel_crtc);
f67a559d 4938
6e3c9717 4939 if (intel_crtc->config->has_pch_encoder)
f67a559d 4940 ironlake_pch_enable(crtc);
c98e9dcf 4941
f9b61ff6
DV		 4942 assert_vblank_disabled(crtc);
4943 drm_crtc_vblank_on(crtc);
4944
fa5c73b1
DV		 4945 for_each_encoder_on_crtc(dev, crtc, encoder)
4946 encoder->enable(encoder);
61b77ddd
DV		 4947
4948 if (HAS_PCH_CPT(dev))
a1520318 4949 cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 4950}
4951
42db64ef
PZ		 4952/* IPS only exists on ULT machines and is tied to pipe A. */
4953static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4954{
f5adf94e 4955 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4956}
4957
e4916946
PZ		 4958/*
4959 * This implements the workaround described in the "notes" section of the mode
4960 * set sequence documentation. When going from no pipes or single pipe to
4961 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4962 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4963 */
4964static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4965{
4966 struct drm_device *dev = crtc->base.dev;
4967 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4968
4969 /* We want to get the other_active_crtc only if there's only 1 other
4970 * active crtc. */
d3fcc808 4971 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4972 if (!crtc_it->active || crtc_it == crtc)
4973 continue;
4974
4975 if (other_active_crtc)
4976 return;
4977
4978 other_active_crtc = crtc_it;
4979 }
4980 if (!other_active_crtc)
4981 return;
4982
4983 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4984 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4985}
4986
4f771f10
PZ		 4987static void haswell_crtc_enable(struct drm_crtc *crtc)
4988{
4989 struct drm_device *dev = crtc->dev;
4990 struct drm_i915_private *dev_priv = dev->dev_private;
4991 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4992 struct intel_encoder *encoder;
4993 int pipe = intel_crtc->pipe;
4f771f10 4994
83d65738 4995 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 4996
4997 if (intel_crtc->active)
4998 return;
4999
df8ad70c
DV		 5000 if (intel_crtc_to_shared_dpll(intel_crtc))
5001 intel_enable_shared_dpll(intel_crtc);
5002
6e3c9717 5003 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5004 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 5005
5006 intel_set_pipe_timings(intel_crtc);
5007
6e3c9717
ACO		 5008 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
5009 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
5010 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 5011 }
5012
6e3c9717 5013 if (intel_crtc->config->has_pch_encoder) {
229fca97 5014 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 5015 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 5016 }
5017
5018 haswell_set_pipeconf(crtc);
5019
5020 intel_set_pipe_csc(crtc);
5021
4f771f10 5022 intel_crtc->active = true;
8664281b 5023
a72e4c9f 5024 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 5025 for_each_encoder_on_crtc(dev, crtc, encoder)
5026 if (encoder->pre_enable)
5027 encoder->pre_enable(encoder);
5028
6e3c9717 5029 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 5030 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5031 true);
4fe9467d
ID		 5032 dev_priv->display.fdi_link_train(crtc);
5033 }
5034
1f544388 5035 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 5036
ff6d9f55 5037 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5038 skylake_pfit_update(intel_crtc, 1);
ff6d9f55 5039 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5040 ironlake_pfit_enable(intel_crtc);
ff6d9f55
JB		 5041 else
5042 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10
PZ		 5043
5044 /*
5045 * On ILK+ LUT must be loaded before the pipe is running but with
5046 * clocks enabled
5047 */
5048 intel_crtc_load_lut(crtc);
5049
1f544388 5050 intel_ddi_set_pipe_settings(crtc);
8228c251 5051 intel_ddi_enable_transcoder_func(crtc);
4f771f10 5052
f37fcc2a 5053 intel_update_watermarks(crtc);
e1fdc473 5054 intel_enable_pipe(intel_crtc);
42db64ef 5055
6e3c9717 5056 if (intel_crtc->config->has_pch_encoder)
1507e5bd 5057 lpt_pch_enable(crtc);
4f771f10 5058
6e3c9717 5059 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 5060 intel_ddi_set_vc_payload_alloc(crtc, true);
5061
f9b61ff6
DV		 5062 assert_vblank_disabled(crtc);
5063 drm_crtc_vblank_on(crtc);
5064
8807e55b 5065 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 5066 encoder->enable(encoder);
8807e55b
JN		 5067 intel_opregion_notify_encoder(encoder, true);
5068 }
4f771f10 5069
e4916946
PZ		 5070 /* If we change the relative order between pipe/planes enabling, we need
5071 * to change the workaround. */
5072 haswell_mode_set_planes_workaround(intel_crtc);
4f771f10
PZ		 5073}
5074
3f8dce3a
DV		 5075static void ironlake_pfit_disable(struct intel_crtc *crtc)
5076{
5077 struct drm_device *dev = crtc->base.dev;
5078 struct drm_i915_private *dev_priv = dev->dev_private;
5079 int pipe = crtc->pipe;
5080
5081 /* To avoid upsetting the power well on haswell only disable the pfit if
5082 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 5083 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 5084 I915_WRITE(PF_CTL(pipe), 0);
5085 I915_WRITE(PF_WIN_POS(pipe), 0);
5086 I915_WRITE(PF_WIN_SZ(pipe), 0);
5087 }
5088}
5089
6be4a607
JB		 5090static void ironlake_crtc_disable(struct drm_crtc *crtc)
5091{
5092 struct drm_device *dev = crtc->dev;
5093 struct drm_i915_private *dev_priv = dev->dev_private;
5094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5095 struct intel_encoder *encoder;
6be4a607 5096 int pipe = intel_crtc->pipe;
5eddb70b 5097 u32 reg, temp;
b52eb4dc 5098
f7abfe8b
CW		 5099 if (!intel_crtc->active)
5100 return;
5101
ea9d758d
DV		 5102 for_each_encoder_on_crtc(dev, crtc, encoder)
5103 encoder->disable(encoder);
5104
f9b61ff6
DV		 5105 drm_crtc_vblank_off(crtc);
5106 assert_vblank_disabled(crtc);
5107
6e3c9717 5108 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 5109 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 5110
575f7ab7 5111 intel_disable_pipe(intel_crtc);
32f9d658 5112
3f8dce3a 5113 ironlake_pfit_disable(intel_crtc);
2c07245f 5114
bf49ec8c
DV		 5115 for_each_encoder_on_crtc(dev, crtc, encoder)
5116 if (encoder->post_disable)
5117 encoder->post_disable(encoder);
2c07245f 5118
6e3c9717 5119 if (intel_crtc->config->has_pch_encoder) {
d925c59a 5120 ironlake_fdi_disable(crtc);
913d8d11 5121
d925c59a 5122 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 5123
d925c59a
DV		 5124 if (HAS_PCH_CPT(dev)) {
5125 /* disable TRANS_DP_CTL */
5126 reg = TRANS_DP_CTL(pipe);
5127 temp = I915_READ(reg);
5128 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
5129 TRANS_DP_PORT_SEL_MASK);
5130 temp |= TRANS_DP_PORT_SEL_NONE;
5131 I915_WRITE(reg, temp);
5132
5133 /* disable DPLL_SEL */
5134 temp = I915_READ(PCH_DPLL_SEL);
11887397 5135 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 5136 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 5137 }
e3421a18 5138
d925c59a 5139 /* disable PCH DPLL */
e72f9fbf 5140 intel_disable_shared_dpll(intel_crtc);
8db9d77b 5141
d925c59a
DV		 5142 ironlake_fdi_pll_disable(intel_crtc);
5143 }
6b383a7f 5144
f7abfe8b 5145 intel_crtc->active = false;
46ba614c 5146 intel_update_watermarks(crtc);
d1ebd816
BW		 5147
5148 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5149 intel_fbc_update(dev);
d1ebd816 5150 mutex_unlock(&dev->struct_mutex);
6be4a607 5151}
1b3c7a47 5152
4f771f10 5153static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 5154{
4f771f10
PZ		 5155 struct drm_device *dev = crtc->dev;
5156 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 5157 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 5158 struct intel_encoder *encoder;
6e3c9717 5159 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 5160
4f771f10
PZ		 5161 if (!intel_crtc->active)
5162 return;
5163
8807e55b
JN		 5164 for_each_encoder_on_crtc(dev, crtc, encoder) {
5165 intel_opregion_notify_encoder(encoder, false);
4f771f10 5166 encoder->disable(encoder);
8807e55b 5167 }
4f771f10 5168
f9b61ff6
DV		 5169 drm_crtc_vblank_off(crtc);
5170 assert_vblank_disabled(crtc);
5171
6e3c9717 5172 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 5173 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
5174 false);
575f7ab7 5175 intel_disable_pipe(intel_crtc);
4f771f10 5176
6e3c9717 5177 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 5178 intel_ddi_set_vc_payload_alloc(crtc, false);
5179
ad80a810 5180 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 5181
ff6d9f55 5182 if (INTEL_INFO(dev)->gen == 9)
a1b2278e 5183 skylake_pfit_update(intel_crtc, 0);
ff6d9f55 5184 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 5185 ironlake_pfit_disable(intel_crtc);
ff6d9f55
JB		 5186 else
5187 MISSING_CASE(INTEL_INFO(dev)->gen);
4f771f10 5188
1f544388 5189 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 5190
6e3c9717 5191 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 5192 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 5193 intel_ddi_fdi_disable(crtc);
83616634 5194 }
4f771f10 5195
97b040aa
ID		 5196 for_each_encoder_on_crtc(dev, crtc, encoder)
5197 if (encoder->post_disable)
5198 encoder->post_disable(encoder);
5199
4f771f10 5200 intel_crtc->active = false;
46ba614c 5201 intel_update_watermarks(crtc);
4f771f10
PZ		 5202
5203 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5204 intel_fbc_update(dev);
4f771f10 5205 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 5206
5207 if (intel_crtc_to_shared_dpll(intel_crtc))
5208 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 5209}
5210
ee7b9f93
JB		 5211static void ironlake_crtc_off(struct drm_crtc *crtc)
5212{
5213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 5214 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 5215}
5216
6441ab5f 5217
2dd24552
JB		 5218static void i9xx_pfit_enable(struct intel_crtc *crtc)
5219{
5220 struct drm_device *dev = crtc->base.dev;
5221 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 5222 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 5223
681a8504 5224 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 5225 return;
5226
2dd24552 5227 /*
c0b03411
DV		 5228 * The panel fitter should only be adjusted whilst the pipe is disabled,
5229 * according to register description and PRM.
2dd24552 5230 */
c0b03411
DV		 5231 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
5232 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 5233
b074cec8
JB		 5234 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
5235 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 5236
5237 /* Border color in case we don't scale up to the full screen. Black by
5238 * default, change to something else for debugging. */
5239 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 5240}
5241
d05410f9
DA		 5242static enum intel_display_power_domain port_to_power_domain(enum port port)
5243{
5244 switch (port) {
5245 case PORT_A:
5246 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
5247 case PORT_B:
5248 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
5249 case PORT_C:
5250 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
5251 case PORT_D:
5252 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
5253 default:
5254 WARN_ON_ONCE(1);
5255 return POWER_DOMAIN_PORT_OTHER;
5256 }
5257}
5258
77d22dca
ID		 5259#define for_each_power_domain(domain, mask) \
5260 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
5261 if ((1 << (domain)) & (mask))
5262
319be8ae
ID		 5263enum intel_display_power_domain
5264intel_display_port_power_domain(struct intel_encoder *intel_encoder)
5265{
5266 struct drm_device *dev = intel_encoder->base.dev;
5267 struct intel_digital_port *intel_dig_port;
5268
5269 switch (intel_encoder->type) {
5270 case INTEL_OUTPUT_UNKNOWN:
5271 /* Only DDI platforms should ever use this output type */
5272 WARN_ON_ONCE(!HAS_DDI(dev));
5273 case INTEL_OUTPUT_DISPLAYPORT:
5274 case INTEL_OUTPUT_HDMI:
5275 case INTEL_OUTPUT_EDP:
5276 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 5277 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 5278 case INTEL_OUTPUT_DP_MST:
5279 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
5280 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 5281 case INTEL_OUTPUT_ANALOG:
5282 return POWER_DOMAIN_PORT_CRT;
5283 case INTEL_OUTPUT_DSI:
5284 return POWER_DOMAIN_PORT_DSI;
5285 default:
5286 return POWER_DOMAIN_PORT_OTHER;
5287 }
5288}
5289
5290static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 5291{
319be8ae
ID		 5292 struct drm_device *dev = crtc->dev;
5293 struct intel_encoder *intel_encoder;
5294 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5295 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 5296 unsigned long mask;
5297 enum transcoder transcoder;
5298
5299 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
5300
5301 mask = BIT(POWER_DOMAIN_PIPE(pipe));
5302 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 5303 if (intel_crtc->config->pch_pfit.enabled ||
5304 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 5305 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
5306
319be8ae
ID		 5307 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5308 mask |= BIT(intel_display_port_power_domain(intel_encoder));
5309
77d22dca
ID		 5310 return mask;
5311}
5312
679dacd4 5313static void modeset_update_crtc_power_domains(struct drm_atomic_state *state)
77d22dca 5314{
679dacd4 5315 struct drm_device *dev = state->dev;
77d22dca
ID		 5316 struct drm_i915_private *dev_priv = dev->dev_private;
5317 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
5318 struct intel_crtc *crtc;
5319
5320 /*
5321 * First get all needed power domains, then put all unneeded, to avoid
5322 * any unnecessary toggling of the power wells.
5323 */
d3fcc808 5324 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5325 enum intel_display_power_domain domain;
5326
83d65738 5327 if (!crtc->base.state->enable)
77d22dca
ID		 5328 continue;
5329
319be8ae 5330 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 5331
5332 for_each_power_domain(domain, pipe_domains[crtc->pipe])
5333 intel_display_power_get(dev_priv, domain);
5334 }
5335
50f6e502 5336 if (dev_priv->display.modeset_global_resources)
679dacd4 5337 dev_priv->display.modeset_global_resources(state);
50f6e502 5338
d3fcc808 5339 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 5340 enum intel_display_power_domain domain;
5341
5342 for_each_power_domain(domain, crtc->enabled_power_domains)
5343 intel_display_power_put(dev_priv, domain);
5344
5345 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
5346 }
5347
5348 intel_display_set_init_power(dev_priv, false);
5349}
5350
f8437dd1
VK		 5351void broxton_set_cdclk(struct drm_device *dev, int frequency)
5352{
5353 struct drm_i915_private *dev_priv = dev->dev_private;
5354 uint32_t divider;
5355 uint32_t ratio;
5356 uint32_t current_freq;
5357 int ret;
5358
5359 /* frequency = 19.2MHz * ratio / 2 / div{1,1.5,2,4} */
5360 switch (frequency) {
5361 case 144000:
5362 divider = BXT_CDCLK_CD2X_DIV_SEL_4;
5363 ratio = BXT_DE_PLL_RATIO(60);
5364 break;
5365 case 288000:
5366 divider = BXT_CDCLK_CD2X_DIV_SEL_2;
5367 ratio = BXT_DE_PLL_RATIO(60);
5368 break;
5369 case 384000:
5370 divider = BXT_CDCLK_CD2X_DIV_SEL_1_5;
5371 ratio = BXT_DE_PLL_RATIO(60);
5372 break;
5373 case 576000:
5374 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5375 ratio = BXT_DE_PLL_RATIO(60);
5376 break;
5377 case 624000:
5378 divider = BXT_CDCLK_CD2X_DIV_SEL_1;
5379 ratio = BXT_DE_PLL_RATIO(65);
5380 break;
5381 case 19200:
5382 /*
5383 * Bypass frequency with DE PLL disabled. Init ratio, divider
5384 * to suppress GCC warning.
5385 */
5386 ratio = 0;
5387 divider = 0;
5388 break;
5389 default:
5390 DRM_ERROR("unsupported CDCLK freq %d", frequency);
5391
5392 return;
5393 }
5394
5395 mutex_lock(&dev_priv->rps.hw_lock);
5396 /* Inform power controller of upcoming frequency change */
5397 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5398 0x80000000);
5399 mutex_unlock(&dev_priv->rps.hw_lock);
5400
5401 if (ret) {
5402 DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
5403 ret, frequency);
5404 return;
5405 }
5406
5407 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK;
5408 /* convert from .1 fixpoint MHz with -1MHz offset to kHz */
5409 current_freq = current_freq * 500 + 1000;
5410
5411 /*
5412 * DE PLL has to be disabled when
5413 * - setting to 19.2MHz (bypass, PLL isn't used)
5414 * - before setting to 624MHz (PLL needs toggling)
5415 * - before setting to any frequency from 624MHz (PLL needs toggling)
5416 */
5417 if (frequency == 19200 || frequency == 624000 ||
5418 current_freq == 624000) {
5419 I915_WRITE(BXT_DE_PLL_ENABLE, ~BXT_DE_PLL_PLL_ENABLE);
5420 /* Timeout 200us */
5421 if (wait_for(!(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK),
5422 1))
5423 DRM_ERROR("timout waiting for DE PLL unlock\n");
5424 }
5425
5426 if (frequency != 19200) {
5427 uint32_t val;
5428
5429 val = I915_READ(BXT_DE_PLL_CTL);
5430 val &= ~BXT_DE_PLL_RATIO_MASK;
5431 val |= ratio;
5432 I915_WRITE(BXT_DE_PLL_CTL, val);
5433
5434 I915_WRITE(BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
5435 /* Timeout 200us */
5436 if (wait_for(I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_LOCK, 1))
5437 DRM_ERROR("timeout waiting for DE PLL lock\n");
5438
5439 val = I915_READ(CDCLK_CTL);
5440 val &= ~BXT_CDCLK_CD2X_DIV_SEL_MASK;
5441 val |= divider;
5442 /*
5443 * Disable SSA Precharge when CD clock frequency < 500 MHz,
5444 * enable otherwise.
5445 */
5446 val &= ~BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5447 if (frequency >= 500000)
5448 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
5449
5450 val &= ~CDCLK_FREQ_DECIMAL_MASK;
5451 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
5452 val |= (frequency - 1000) / 500;
5453 I915_WRITE(CDCLK_CTL, val);
5454 }
5455
5456 mutex_lock(&dev_priv->rps.hw_lock);
5457 ret = sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
5458 DIV_ROUND_UP(frequency, 25000));
5459 mutex_unlock(&dev_priv->rps.hw_lock);
5460
5461 if (ret) {
5462 DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
5463 ret, frequency);
5464 return;
5465 }
5466
5467 dev_priv->cdclk_freq = frequency;
5468}
5469
5470void broxton_init_cdclk(struct drm_device *dev)
5471{
5472 struct drm_i915_private *dev_priv = dev->dev_private;
5473 uint32_t val;
5474
5475 /*
5476 * NDE_RSTWRN_OPT RST PCH Handshake En must always be 0b on BXT
5477 * or else the reset will hang because there is no PCH to respond.
5478 * Move the handshake programming to initialization sequence.
5479 * Previously was left up to BIOS.
5480 */
5481 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5482 val &= ~RESET_PCH_HANDSHAKE_ENABLE;
5483 I915_WRITE(HSW_NDE_RSTWRN_OPT, val);
5484
5485 /* Enable PG1 for cdclk */
5486 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5487
5488 /* check if cd clock is enabled */
5489 if (I915_READ(BXT_DE_PLL_ENABLE) & BXT_DE_PLL_PLL_ENABLE) {
5490 DRM_DEBUG_KMS("Display already initialized\n");
5491 return;
5492 }
5493
5494 /*
5495 * FIXME:
5496 * - The initial CDCLK needs to be read from VBT.
5497 * Need to make this change after VBT has changes for BXT.
5498 * - check if setting the max (or any) cdclk freq is really necessary
5499 * here, it belongs to modeset time
5500 */
5501 broxton_set_cdclk(dev, 624000);
5502
5503 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
22e02c0b
VS		 5504 POSTING_READ(DBUF_CTL);
5505
f8437dd1
VK		 5506 udelay(10);
5507
5508 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5509 DRM_ERROR("DBuf power enable timeout!\n");
5510}
5511
5512void broxton_uninit_cdclk(struct drm_device *dev)
5513{
5514 struct drm_i915_private *dev_priv = dev->dev_private;
5515
5516 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
22e02c0b
VS		 5517 POSTING_READ(DBUF_CTL);
5518
f8437dd1
VK		 5519 udelay(10);
5520
5521 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5522 DRM_ERROR("DBuf power disable timeout!\n");
5523
5524 /* Set minimum (bypass) frequency, in effect turning off the DE PLL */
5525 broxton_set_cdclk(dev, 19200);
5526
5527 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5528}
5529
5d96d8af
DL		 5530static const struct skl_cdclk_entry {
5531 unsigned int freq;
5532 unsigned int vco;
5533} skl_cdclk_frequencies[] = {
5534 { .freq = 308570, .vco = 8640 },
5535 { .freq = 337500, .vco = 8100 },
5536 { .freq = 432000, .vco = 8640 },
5537 { .freq = 450000, .vco = 8100 },
5538 { .freq = 540000, .vco = 8100 },
5539 { .freq = 617140, .vco = 8640 },
5540 { .freq = 675000, .vco = 8100 },
5541};
5542
5543static unsigned int skl_cdclk_decimal(unsigned int freq)
5544{
5545 return (freq - 1000) / 500;
5546}
5547
5548static unsigned int skl_cdclk_get_vco(unsigned int freq)
5549{
5550 unsigned int i;
5551
5552 for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) {
5553 const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i];
5554
5555 if (e->freq == freq)
5556 return e->vco;
5557 }
5558
5559 return 8100;
5560}
5561
5562static void
5563skl_dpll0_enable(struct drm_i915_private *dev_priv, unsigned int required_vco)
5564{
5565 unsigned int min_freq;
5566 u32 val;
5567
5568 /* select the minimum CDCLK before enabling DPLL 0 */
5569 val = I915_READ(CDCLK_CTL);
5570 val &= ~CDCLK_FREQ_SEL_MASK | ~CDCLK_FREQ_DECIMAL_MASK;
5571 val |= CDCLK_FREQ_337_308;
5572
5573 if (required_vco == 8640)
5574 min_freq = 308570;
5575 else
5576 min_freq = 337500;
5577
5578 val = CDCLK_FREQ_337_308 | skl_cdclk_decimal(min_freq);
5579
5580 I915_WRITE(CDCLK_CTL, val);
5581 POSTING_READ(CDCLK_CTL);
5582
5583 /*
5584 * We always enable DPLL0 with the lowest link rate possible, but still
5585 * taking into account the VCO required to operate the eDP panel at the
5586 * desired frequency. The usual DP link rates operate with a VCO of
5587 * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
5588 * The modeset code is responsible for the selection of the exact link
5589 * rate later on, with the constraint of choosing a frequency that
5590 * works with required_vco.
5591 */
5592 val = I915_READ(DPLL_CTRL1);
5593
5594 val &= ~(DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) | DPLL_CTRL1_SSC(SKL_DPLL0) |
5595 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
5596 val |= DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
5597 if (required_vco == 8640)
5598 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
5599 SKL_DPLL0);
5600 else
5601 val |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
5602 SKL_DPLL0);
5603
5604 I915_WRITE(DPLL_CTRL1, val);
5605 POSTING_READ(DPLL_CTRL1);
5606
5607 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE);
5608
5609 if (wait_for(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK, 5))
5610 DRM_ERROR("DPLL0 not locked\n");
5611}
5612
5613static bool skl_cdclk_pcu_ready(struct drm_i915_private *dev_priv)
5614{
5615 int ret;
5616 u32 val;
5617
5618 /* inform PCU we want to change CDCLK */
5619 val = SKL_CDCLK_PREPARE_FOR_CHANGE;
5620 mutex_lock(&dev_priv->rps.hw_lock);
5621 ret = sandybridge_pcode_read(dev_priv, SKL_PCODE_CDCLK_CONTROL, &val);
5622 mutex_unlock(&dev_priv->rps.hw_lock);
5623
5624 return ret == 0 && (val & SKL_CDCLK_READY_FOR_CHANGE);
5625}
5626
5627static bool skl_cdclk_wait_for_pcu_ready(struct drm_i915_private *dev_priv)
5628{
5629 unsigned int i;
5630
5631 for (i = 0; i < 15; i++) {
5632 if (skl_cdclk_pcu_ready(dev_priv))
5633 return true;
5634 udelay(10);
5635 }
5636
5637 return false;
5638}
5639
5640static void skl_set_cdclk(struct drm_i915_private *dev_priv, unsigned int freq)
5641{
5642 u32 freq_select, pcu_ack;
5643
5644 DRM_DEBUG_DRIVER("Changing CDCLK to %dKHz\n", freq);
5645
5646 if (!skl_cdclk_wait_for_pcu_ready(dev_priv)) {
5647 DRM_ERROR("failed to inform PCU about cdclk change\n");
5648 return;
5649 }
5650
5651 /* set CDCLK_CTL */
5652 switch(freq) {
5653 case 450000:
5654 case 432000:
5655 freq_select = CDCLK_FREQ_450_432;
5656 pcu_ack = 1;
5657 break;
5658 case 540000:
5659 freq_select = CDCLK_FREQ_540;
5660 pcu_ack = 2;
5661 break;
5662 case 308570:
5663 case 337500:
5664 default:
5665 freq_select = CDCLK_FREQ_337_308;
5666 pcu_ack = 0;
5667 break;
5668 case 617140:
5669 case 675000:
5670 freq_select = CDCLK_FREQ_675_617;
5671 pcu_ack = 3;
5672 break;
5673 }
5674
5675 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq));
5676 POSTING_READ(CDCLK_CTL);
5677
5678 /* inform PCU of the change */
5679 mutex_lock(&dev_priv->rps.hw_lock);
5680 sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack);
5681 mutex_unlock(&dev_priv->rps.hw_lock);
5682}
5683
5684void skl_uninit_cdclk(struct drm_i915_private *dev_priv)
5685{
5686 /* disable DBUF power */
5687 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) & ~DBUF_POWER_REQUEST);
5688 POSTING_READ(DBUF_CTL);
5689
5690 udelay(10);
5691
5692 if (I915_READ(DBUF_CTL) & DBUF_POWER_STATE)
5693 DRM_ERROR("DBuf power disable timeout\n");
5694
5695 /* disable DPLL0 */
5696 I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) & ~LCPLL_PLL_ENABLE);
5697 if (wait_for(!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_LOCK), 1))
5698 DRM_ERROR("Couldn't disable DPLL0\n");
5699
5700 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
5701}
5702
5703void skl_init_cdclk(struct drm_i915_private *dev_priv)
5704{
5705 u32 val;
5706 unsigned int required_vco;
5707
5708 /* enable PCH reset handshake */
5709 val = I915_READ(HSW_NDE_RSTWRN_OPT);
5710 I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
5711
5712 /* enable PG1 and Misc I/O */
5713 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5714
5715 /* DPLL0 already enabed !? */
5716 if (I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE) {
5717 DRM_DEBUG_DRIVER("DPLL0 already running\n");
5718 return;
5719 }
5720
5721 /* enable DPLL0 */
5722 required_vco = skl_cdclk_get_vco(dev_priv->skl_boot_cdclk);
5723 skl_dpll0_enable(dev_priv, required_vco);
5724
5725 /* set CDCLK to the frequency the BIOS chose */
5726 skl_set_cdclk(dev_priv, dev_priv->skl_boot_cdclk);
5727
5728 /* enable DBUF power */
5729 I915_WRITE(DBUF_CTL, I915_READ(DBUF_CTL) | DBUF_POWER_REQUEST);
5730 POSTING_READ(DBUF_CTL);
5731
5732 udelay(10);
5733
5734 if (!(I915_READ(DBUF_CTL) & DBUF_POWER_STATE))
5735 DRM_ERROR("DBuf power enable timeout\n");
5736}
5737
dfcab17e 5738/* returns HPLL frequency in kHz */
f8bf63fd 5739static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 5740{
586f49dc 5741 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 5742
586f49dc
JB		 5743 /* Obtain SKU information */
5744 mutex_lock(&dev_priv->dpio_lock);
5745 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
5746 CCK_FUSE_HPLL_FREQ_MASK;
5747 mutex_unlock(&dev_priv->dpio_lock);
30a970c6 5748
dfcab17e 5749 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 5750}
5751
f8bf63fd
VS		 5752static void vlv_update_cdclk(struct drm_device *dev)
5753{
5754 struct drm_i915_private *dev_priv = dev->dev_private;
5755
164dfd28 5756 dev_priv->cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
43dc52c3 5757 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
164dfd28 5758 dev_priv->cdclk_freq);
f8bf63fd
VS		 5759
5760 /*
5761 * Program the gmbus_freq based on the cdclk frequency.
5762 * BSpec erroneously claims we should aim for 4MHz, but
5763 * in fact 1MHz is the correct frequency.
5764 */
164dfd28 5765 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, 1000));
f8bf63fd
VS		 5766}
5767
30a970c6
JB		 5768/* Adjust CDclk dividers to allow high res or save power if possible */
5769static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5770{
5771 struct drm_i915_private *dev_priv = dev->dev_private;
5772 u32 val, cmd;
5773
164dfd28
VK		 5774 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5775 != dev_priv->cdclk_freq);
d60c4473 5776
dfcab17e 5777 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5778 cmd = 2;
dfcab17e 5779 else if (cdclk == 266667)
30a970c6
JB		 5780 cmd = 1;
5781 else
5782 cmd = 0;
5783
5784 mutex_lock(&dev_priv->rps.hw_lock);
5785 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5786 val &= ~DSPFREQGUAR_MASK;
5787 val |= (cmd << DSPFREQGUAR_SHIFT);
5788 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5789 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5790 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5791 50)) {
5792 DRM_ERROR("timed out waiting for CDclk change\n");
5793 }
5794 mutex_unlock(&dev_priv->rps.hw_lock);
5795
dfcab17e 5796 if (cdclk == 400000) {
6bcda4f0 5797 u32 divider;
30a970c6 5798
6bcda4f0 5799 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6
JB		 5800
5801 mutex_lock(&dev_priv->dpio_lock);
5802 /* adjust cdclk divider */
5803 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5804 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5805 val |= divider;
5806 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5807
5808 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5809 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5810 50))
5811 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5812 mutex_unlock(&dev_priv->dpio_lock);
5813 }
5814
5815 mutex_lock(&dev_priv->dpio_lock);
5816 /* adjust self-refresh exit latency value */
5817 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5818 val &= ~0x7f;
5819
5820 /*
5821 * For high bandwidth configs, we set a higher latency in the bunit
5822 * so that the core display fetch happens in time to avoid underruns.
5823 */
dfcab17e 5824 if (cdclk == 400000)
30a970c6
JB		 5825 val |= 4500 / 250; /* 4.5 usec */
5826 else
5827 val |= 3000 / 250; /* 3.0 usec */
5828 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5829 mutex_unlock(&dev_priv->dpio_lock);
5830
f8bf63fd 5831 vlv_update_cdclk(dev);
30a970c6
JB		 5832}
5833
383c5a6a
VS		 5834static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5835{
5836 struct drm_i915_private *dev_priv = dev->dev_private;
5837 u32 val, cmd;
5838
164dfd28
VK		 5839 WARN_ON(dev_priv->display.get_display_clock_speed(dev)
5840 != dev_priv->cdclk_freq);
383c5a6a
VS		 5841
5842 switch (cdclk) {
383c5a6a
VS		 5843 case 333333:
5844 case 320000:
383c5a6a 5845 case 266667:
383c5a6a 5846 case 200000:
383c5a6a
VS		 5847 break;
5848 default:
5f77eeb0 5849 MISSING_CASE(cdclk);
383c5a6a
VS		 5850 return;
5851 }
5852
9d0d3fda
VS		 5853 /*
5854 * Specs are full of misinformation, but testing on actual
5855 * hardware has shown that we just need to write the desired
5856 * CCK divider into the Punit register.
5857 */
5858 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5859
383c5a6a
VS		 5860 mutex_lock(&dev_priv->rps.hw_lock);
5861 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5862 val &= ~DSPFREQGUAR_MASK_CHV;
5863 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5864 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5865 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5866 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5867 50)) {
5868 DRM_ERROR("timed out waiting for CDclk change\n");
5869 }
5870 mutex_unlock(&dev_priv->rps.hw_lock);
5871
5872 vlv_update_cdclk(dev);
5873}
5874
30a970c6
JB		 5875static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5876 int max_pixclk)
5877{
6bcda4f0 5878 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5879 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5880
30a970c6
JB		 5881 /*
5882 * Really only a few cases to deal with, as only 4 CDclks are supported:
5883 * 200MHz
5884 * 267MHz
29dc7ef3 5885 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5886 * 400MHz (VLV only)
5887 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5888 * of the lower bin and adjust if needed.
e37c67a1
VS		 5889 *
5890 * We seem to get an unstable or solid color picture at 200MHz.
5891 * Not sure what's wrong. For now use 200MHz only when all pipes
5892 * are off.
30a970c6 5893 */
6cca3195
VS		 5894 if (!IS_CHERRYVIEW(dev_priv) &&
5895 max_pixclk > freq_320*limit/100)
dfcab17e 5896 return 400000;
6cca3195 5897 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5898 return freq_320;
e37c67a1 5899 else if (max_pixclk > 0)
dfcab17e 5900 return 266667;
e37c67a1
VS		 5901 else
5902 return 200000;
30a970c6
JB		 5903}
5904
f8437dd1
VK		 5905static int broxton_calc_cdclk(struct drm_i915_private *dev_priv,
5906 int max_pixclk)
5907{
5908 /*
5909 * FIXME:
5910 * - remove the guardband, it's not needed on BXT
5911 * - set 19.2MHz bypass frequency if there are no active pipes
5912 */
5913 if (max_pixclk > 576000*9/10)
5914 return 624000;
5915 else if (max_pixclk > 384000*9/10)
5916 return 576000;
5917 else if (max_pixclk > 288000*9/10)
5918 return 384000;
5919 else if (max_pixclk > 144000*9/10)
5920 return 288000;
5921 else
5922 return 144000;
5923}
5924
a821fc46
ACO		 5925/* Compute the max pixel clock for new configuration. Uses atomic state if
5926 * that's non-NULL, look at current state otherwise. */
5927static int intel_mode_max_pixclk(struct drm_device *dev,
5928 struct drm_atomic_state *state)
30a970c6 5929{
30a970c6 5930 struct intel_crtc *intel_crtc;
304603f4 5931 struct intel_crtc_state *crtc_state;
30a970c6
JB		 5932 int max_pixclk = 0;
5933
d3fcc808 5934 for_each_intel_crtc(dev, intel_crtc) {
a821fc46
ACO		 5935 if (state)
5936 crtc_state =
5937 intel_atomic_get_crtc_state(state, intel_crtc);
5938 else
5939 crtc_state = intel_crtc->config;
304603f4
ACO		 5940 if (IS_ERR(crtc_state))
5941 return PTR_ERR(crtc_state);
5942
5943 if (!crtc_state->base.enable)
5944 continue;
5945
5946 max_pixclk = max(max_pixclk,
5947 crtc_state->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5948 }
5949
5950 return max_pixclk;
5951}
5952
0a9ab303 5953static int valleyview_modeset_global_pipes(struct drm_atomic_state *state)
30a970c6 5954{
304603f4 5955 struct drm_i915_private *dev_priv = to_i915(state->dev);
0a9ab303
ACO		 5956 struct drm_crtc *crtc;
5957 struct drm_crtc_state *crtc_state;
a821fc46 5958 int max_pixclk = intel_mode_max_pixclk(state->dev, state);
0a9ab303 5959 int cdclk, i;
30a970c6 5960
304603f4
ACO		 5961 if (max_pixclk < 0)
5962 return max_pixclk;
30a970c6 5963
f8437dd1
VK		 5964 if (IS_VALLEYVIEW(dev_priv))
5965 cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5966 else
5967 cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
5968
5969 if (cdclk == dev_priv->cdclk_freq)
304603f4 5970 return 0;
30a970c6 5971
0a9ab303
ACO		 5972 /* add all active pipes to the state */
5973 for_each_crtc(state->dev, crtc) {
5974 if (!crtc->state->enable)
5975 continue;
5976
5977 crtc_state = drm_atomic_get_crtc_state(state, crtc);
5978 if (IS_ERR(crtc_state))
5979 return PTR_ERR(crtc_state);
5980 }
5981
2f2d7aa1 5982 /* disable/enable all currently active pipes while we change cdclk */
0a9ab303
ACO		 5983 for_each_crtc_in_state(state, crtc, crtc_state, i)
5984 if (crtc_state->enable)
5985 crtc_state->mode_changed = true;
304603f4
ACO		 5986
5987 return 0;
30a970c6
JB		 5988}
5989
1e69cd74
VS		 5990static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5991{
5992 unsigned int credits, default_credits;
5993
5994 if (IS_CHERRYVIEW(dev_priv))
5995 default_credits = PFI_CREDIT(12);
5996 else
5997 default_credits = PFI_CREDIT(8);
5998
164dfd28 5999 if (DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
1e69cd74
VS		 6000 /* CHV suggested value is 31 or 63 */
6001 if (IS_CHERRYVIEW(dev_priv))
6002 credits = PFI_CREDIT_31;
6003 else
6004 credits = PFI_CREDIT(15);
6005 } else {
6006 credits = default_credits;
6007 }
6008
6009 /*
6010 * WA - write default credits before re-programming
6011 * FIXME: should we also set the resend bit here?
6012 */
6013 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6014 default_credits);
6015
6016 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
6017 credits | PFI_CREDIT_RESEND);
6018
6019 /*
6020 * FIXME is this guaranteed to clear
6021 * immediately or should we poll for it?
6022 */
6023 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
6024}
6025
a821fc46 6026static void valleyview_modeset_global_resources(struct drm_atomic_state *old_state)
30a970c6 6027{
a821fc46 6028 struct drm_device *dev = old_state->dev;
30a970c6 6029 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 6030 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
304603f4
ACO		 6031 int req_cdclk;
6032
a821fc46
ACO		 6033 /* The path in intel_mode_max_pixclk() with a NULL atomic state should
6034 * never fail. */
304603f4
ACO		 6035 if (WARN_ON(max_pixclk < 0))
6036 return;
30a970c6 6037
304603f4 6038 req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
30a970c6 6039
164dfd28 6040 if (req_cdclk != dev_priv->cdclk_freq) {
738c05c0
ID		 6041 /*
6042 * FIXME: We can end up here with all power domains off, yet
6043 * with a CDCLK frequency other than the minimum. To account
6044 * for this take the PIPE-A power domain, which covers the HW
6045 * blocks needed for the following programming. This can be
6046 * removed once it's guaranteed that we get here either with
6047 * the minimum CDCLK set, or the required power domains
6048 * enabled.
6049 */
6050 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
6051
383c5a6a
VS		 6052 if (IS_CHERRYVIEW(dev))
6053 cherryview_set_cdclk(dev, req_cdclk);
6054 else
6055 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 6056
1e69cd74
VS		 6057 vlv_program_pfi_credits(dev_priv);
6058
738c05c0 6059 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 6060 }
30a970c6
JB		 6061}
6062
89b667f8
JB		 6063static void valleyview_crtc_enable(struct drm_crtc *crtc)
6064{
6065 struct drm_device *dev = crtc->dev;
a72e4c9f 6066 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 6067 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6068 struct intel_encoder *encoder;
6069 int pipe = intel_crtc->pipe;
23538ef1 6070 bool is_dsi;
89b667f8 6071
83d65738 6072 WARN_ON(!crtc->state->enable);
89b667f8
JB		 6073
6074 if (intel_crtc->active)
6075 return;
6076
409ee761 6077 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 6078
1ae0d137
VS		 6079 if (!is_dsi) {
6080 if (IS_CHERRYVIEW(dev))
6e3c9717 6081 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6082 else
6e3c9717 6083 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 6084 }
5b18e57c 6085
6e3c9717 6086 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6087 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6088
6089 intel_set_pipe_timings(intel_crtc);
6090
c14b0485
VS		 6091 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
6092 struct drm_i915_private *dev_priv = dev->dev_private;
6093
6094 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
6095 I915_WRITE(CHV_CANVAS(pipe), 0);
6096 }
6097
5b18e57c
DV		 6098 i9xx_set_pipeconf(intel_crtc);
6099
89b667f8 6100 intel_crtc->active = true;
89b667f8 6101
a72e4c9f 6102 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6103
89b667f8
JB		 6104 for_each_encoder_on_crtc(dev, crtc, encoder)
6105 if (encoder->pre_pll_enable)
6106 encoder->pre_pll_enable(encoder);
6107
9d556c99
CML		 6108 if (!is_dsi) {
6109 if (IS_CHERRYVIEW(dev))
6e3c9717 6110 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6111 else
6e3c9717 6112 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 6113 }
89b667f8
JB		 6114
6115 for_each_encoder_on_crtc(dev, crtc, encoder)
6116 if (encoder->pre_enable)
6117 encoder->pre_enable(encoder);
6118
2dd24552
JB		 6119 i9xx_pfit_enable(intel_crtc);
6120
63cbb074
VS		 6121 intel_crtc_load_lut(crtc);
6122
f37fcc2a 6123 intel_update_watermarks(crtc);
e1fdc473 6124 intel_enable_pipe(intel_crtc);
be6a6f8e 6125
4b3a9526
VS		 6126 assert_vblank_disabled(crtc);
6127 drm_crtc_vblank_on(crtc);
6128
f9b61ff6
DV		 6129 for_each_encoder_on_crtc(dev, crtc, encoder)
6130 encoder->enable(encoder);
89b667f8
JB		 6131}
6132
f13c2ef3
DV		 6133static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
6134{
6135 struct drm_device *dev = crtc->base.dev;
6136 struct drm_i915_private *dev_priv = dev->dev_private;
6137
6e3c9717
ACO		 6138 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
6139 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 6140}
6141
0b8765c6 6142static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 6143{
6144 struct drm_device *dev = crtc->dev;
a72e4c9f 6145 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 6146 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6147 struct intel_encoder *encoder;
79e53945 6148 int pipe = intel_crtc->pipe;
79e53945 6149
83d65738 6150 WARN_ON(!crtc->state->enable);
08a48469 6151
f7abfe8b
CW		 6152 if (intel_crtc->active)
6153 return;
6154
f13c2ef3
DV		 6155 i9xx_set_pll_dividers(intel_crtc);
6156
6e3c9717 6157 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 6158 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 6159
6160 intel_set_pipe_timings(intel_crtc);
6161
5b18e57c
DV		 6162 i9xx_set_pipeconf(intel_crtc);
6163
f7abfe8b 6164 intel_crtc->active = true;
6b383a7f 6165
4a3436e8 6166 if (!IS_GEN2(dev))
a72e4c9f 6167 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 6168
9d6d9f19
MK		 6169 for_each_encoder_on_crtc(dev, crtc, encoder)
6170 if (encoder->pre_enable)
6171 encoder->pre_enable(encoder);
6172
f6736a1a
DV		 6173 i9xx_enable_pll(intel_crtc);
6174
2dd24552
JB		 6175 i9xx_pfit_enable(intel_crtc);
6176
63cbb074
VS		 6177 intel_crtc_load_lut(crtc);
6178
f37fcc2a 6179 intel_update_watermarks(crtc);
e1fdc473 6180 intel_enable_pipe(intel_crtc);
be6a6f8e 6181
4b3a9526
VS		 6182 assert_vblank_disabled(crtc);
6183 drm_crtc_vblank_on(crtc);
6184
f9b61ff6
DV		 6185 for_each_encoder_on_crtc(dev, crtc, encoder)
6186 encoder->enable(encoder);
0b8765c6 6187}
79e53945 6188
87476d63
DV		 6189static void i9xx_pfit_disable(struct intel_crtc *crtc)
6190{
6191 struct drm_device *dev = crtc->base.dev;
6192 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 6193
6e3c9717 6194 if (!crtc->config->gmch_pfit.control)
328d8e82 6195 return;
87476d63 6196
328d8e82 6197 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 6198
328d8e82
DV		 6199 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
6200 I915_READ(PFIT_CONTROL));
6201 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 6202}
6203
0b8765c6
JB		 6204static void i9xx_crtc_disable(struct drm_crtc *crtc)
6205{
6206 struct drm_device *dev = crtc->dev;
6207 struct drm_i915_private *dev_priv = dev->dev_private;
6208 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 6209 struct intel_encoder *encoder;
0b8765c6 6210 int pipe = intel_crtc->pipe;
ef9c3aee 6211
f7abfe8b
CW		 6212 if (!intel_crtc->active)
6213 return;
6214
6304cd91
VS		 6215 /*
6216 * On gen2 planes are double buffered but the pipe isn't, so we must
6217 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 6218 * We also need to wait on all gmch platforms because of the
6219 * self-refresh mode constraint explained above.
6304cd91 6220 */
564ed191 6221 intel_wait_for_vblank(dev, pipe);
6304cd91 6222
4b3a9526
VS		 6223 for_each_encoder_on_crtc(dev, crtc, encoder)
6224 encoder->disable(encoder);
6225
f9b61ff6
DV		 6226 drm_crtc_vblank_off(crtc);
6227 assert_vblank_disabled(crtc);
6228
575f7ab7 6229 intel_disable_pipe(intel_crtc);
24a1f16d 6230
87476d63 6231 i9xx_pfit_disable(intel_crtc);
24a1f16d 6232
89b667f8
JB		 6233 for_each_encoder_on_crtc(dev, crtc, encoder)
6234 if (encoder->post_disable)
6235 encoder->post_disable(encoder);
6236
409ee761 6237 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 6238 if (IS_CHERRYVIEW(dev))
6239 chv_disable_pll(dev_priv, pipe);
6240 else if (IS_VALLEYVIEW(dev))
6241 vlv_disable_pll(dev_priv, pipe);
6242 else
1c4e0274 6243 i9xx_disable_pll(intel_crtc);
076ed3b2 6244 }
0b8765c6 6245
4a3436e8 6246 if (!IS_GEN2(dev))
a72e4c9f 6247 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 6248
f7abfe8b 6249 intel_crtc->active = false;
46ba614c 6250 intel_update_watermarks(crtc);
f37fcc2a 6251
efa9624e 6252 mutex_lock(&dev->struct_mutex);
7ff0ebcc 6253 intel_fbc_update(dev);
efa9624e 6254 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 6255}
6256
ee7b9f93
JB		 6257static void i9xx_crtc_off(struct drm_crtc *crtc)
6258{
6259}
6260
b04c5bd6
BF		 6261/* Master function to enable/disable CRTC and corresponding power wells */
6262void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 6263{
6264 struct drm_device *dev = crtc->dev;
6265 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 6266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 6267 enum intel_display_power_domain domain;
6268 unsigned long domains;
976f8a20 6269
0e572fe7
DV		 6270 if (enable) {
6271 if (!intel_crtc->active) {
e1e9fb84
DV		 6272 domains = get_crtc_power_domains(crtc);
6273 for_each_power_domain(domain, domains)
6274 intel_display_power_get(dev_priv, domain);
6275 intel_crtc->enabled_power_domains = domains;
0e572fe7
DV		 6276
6277 dev_priv->display.crtc_enable(crtc);
ce22dba9 6278 intel_crtc_enable_planes(crtc);
0e572fe7
DV		 6279 }
6280 } else {
6281 if (intel_crtc->active) {
ce22dba9 6282 intel_crtc_disable_planes(crtc);
0e572fe7
DV		 6283 dev_priv->display.crtc_disable(crtc);
6284
e1e9fb84
DV		 6285 domains = intel_crtc->enabled_power_domains;
6286 for_each_power_domain(domain, domains)
6287 intel_display_power_put(dev_priv, domain);
6288 intel_crtc->enabled_power_domains = 0;
0e572fe7
DV		 6289 }
6290 }
b04c5bd6
BF		 6291}
6292
6293/**
6294 * Sets the power management mode of the pipe and plane.
6295 */
6296void intel_crtc_update_dpms(struct drm_crtc *crtc)
6297{
6298 struct drm_device *dev = crtc->dev;
6299 struct intel_encoder *intel_encoder;
6300 bool enable = false;
6301
6302 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
6303 enable |= intel_encoder->connectors_active;
6304
6305 intel_crtc_control(crtc, enable);
0f63cca2
ACO		 6306
6307 crtc->state->active = enable;
976f8a20
DV		 6308}
6309
cdd59983
CW		 6310static void intel_crtc_disable(struct drm_crtc *crtc)
6311{
cdd59983 6312 struct drm_device *dev = crtc->dev;
976f8a20 6313 struct drm_connector *connector;
ee7b9f93 6314 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 6315
976f8a20 6316 /* crtc should still be enabled when we disable it. */
83d65738 6317 WARN_ON(!crtc->state->enable);
976f8a20 6318
ce22dba9 6319 intel_crtc_disable_planes(crtc);
976f8a20 6320 dev_priv->display.crtc_disable(crtc);
ee7b9f93
JB		 6321 dev_priv->display.off(crtc);
6322
70a101f8 6323 drm_plane_helper_disable(crtc->primary);
976f8a20
DV		 6324
6325 /* Update computed state. */
6326 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
6327 if (!connector->encoder || !connector->encoder->crtc)
6328 continue;
6329
6330 if (connector->encoder->crtc != crtc)
6331 continue;
6332
6333 connector->dpms = DRM_MODE_DPMS_OFF;
6334 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 6335 }
6336}
6337
ea5b213a 6338void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 6339{
4ef69c7a 6340 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 6341
ea5b213a
CW		 6342 drm_encoder_cleanup(encoder);
6343 kfree(intel_encoder);
7e7d76c3
JB		 6344}
6345
9237329d 6346/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 6347 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
6348 * state of the entire output pipe. */
9237329d 6349static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 6350{
5ab432ef
DV		 6351 if (mode == DRM_MODE_DPMS_ON) {
6352 encoder->connectors_active = true;
6353
b2cabb0e 6354 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 6355 } else {
6356 encoder->connectors_active = false;
6357
b2cabb0e 6358 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 6359 }
79e53945
JB		 6360}
6361
0a91ca29
DV		 6362/* Cross check the actual hw state with our own modeset state tracking (and it's
6363 * internal consistency). */
b980514c 6364static void intel_connector_check_state(struct intel_connector *connector)
79e53945 6365{
0a91ca29
DV		 6366 if (connector->get_hw_state(connector)) {
6367 struct intel_encoder *encoder = connector->encoder;
6368 struct drm_crtc *crtc;
6369 bool encoder_enabled;
6370 enum pipe pipe;
6371
6372 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
6373 connector->base.base.id,
c23cc417 6374 connector->base.name);
0a91ca29 6375
0e32b39c
DA		 6376 /* there is no real hw state for MST connectors */
6377 if (connector->mst_port)
6378 return;
6379
e2c719b7 6380 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 6381 "wrong connector dpms state\n");
e2c719b7 6382 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 6383 "active connector not linked to encoder\n");
0a91ca29 6384
36cd7444 6385 if (encoder) {
e2c719b7 6386 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 6387 "encoder->connectors_active not set\n");
6388
6389 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 6390 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
6391 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 6392 return;
0a91ca29 6393
36cd7444 6394 crtc = encoder->base.crtc;
0a91ca29 6395
83d65738
MR		 6396 I915_STATE_WARN(!crtc->state->enable,
6397 "crtc not enabled\n");
e2c719b7
RC		 6398 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
6399 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 6400 "encoder active on the wrong pipe\n");
6401 }
0a91ca29 6402 }
79e53945
JB		 6403}
6404
08d9bc92
ACO		 6405int intel_connector_init(struct intel_connector *connector)
6406{
6407 struct drm_connector_state *connector_state;
6408
6409 connector_state = kzalloc(sizeof *connector_state, GFP_KERNEL);
6410 if (!connector_state)
6411 return -ENOMEM;
6412
6413 connector->base.state = connector_state;
6414 return 0;
6415}
6416
6417struct intel_connector *intel_connector_alloc(void)
6418{
6419 struct intel_connector *connector;
6420
6421 connector = kzalloc(sizeof *connector, GFP_KERNEL);
6422 if (!connector)
6423 return NULL;
6424
6425 if (intel_connector_init(connector) < 0) {
6426 kfree(connector);
6427 return NULL;
6428 }
6429
6430 return connector;
6431}
6432
5ab432ef
DV		 6433/* Even simpler default implementation, if there's really no special case to
6434 * consider. */
6435void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 6436{
5ab432ef
DV		 6437 /* All the simple cases only support two dpms states. */
6438 if (mode != DRM_MODE_DPMS_ON)
6439 mode = DRM_MODE_DPMS_OFF;
d4270e57 6440
5ab432ef
DV		 6441 if (mode == connector->dpms)
6442 return;
6443
6444 connector->dpms = mode;
6445
6446 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 6447 if (connector->encoder)
6448 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 6449
b980514c 6450 intel_modeset_check_state(connector->dev);
79e53945
JB		 6451}
6452
f0947c37
DV		 6453/* Simple connector->get_hw_state implementation for encoders that support only
6454 * one connector and no cloning and hence the encoder state determines the state
6455 * of the connector. */
6456bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 6457{
24929352 6458 enum pipe pipe = 0;
f0947c37 6459 struct intel_encoder *encoder = connector->encoder;
ea5b213a 6460
f0947c37 6461 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 6462}
6463
6d293983 6464static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
d272ddfa 6465{
6d293983
ACO		 6466 if (crtc_state->base.enable && crtc_state->has_pch_encoder)
6467 return crtc_state->fdi_lanes;
d272ddfa
VS		 6468
6469 return 0;
6470}
6471
6d293983 6472static int ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 6473 struct intel_crtc_state *pipe_config)
1857e1da 6474{
6d293983
ACO		 6475 struct drm_atomic_state *state = pipe_config->base.state;
6476 struct intel_crtc *other_crtc;
6477 struct intel_crtc_state *other_crtc_state;
6478
1857e1da
DV		 6479 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
6480 pipe_name(pipe), pipe_config->fdi_lanes);
6481 if (pipe_config->fdi_lanes > 4) {
6482 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
6483 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6484 return -EINVAL;
1857e1da
DV		 6485 }
6486
bafb6553 6487 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 6488 if (pipe_config->fdi_lanes > 2) {
6489 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
6490 pipe_config->fdi_lanes);
6d293983 6491 return -EINVAL;
1857e1da 6492 } else {
6d293983 6493 return 0;
1857e1da
DV		 6494 }
6495 }
6496
6497 if (INTEL_INFO(dev)->num_pipes == 2)
6d293983 6498 return 0;
1857e1da
DV		 6499
6500 /* Ivybridge 3 pipe is really complicated */
6501 switch (pipe) {
6502 case PIPE_A:
6d293983 6503 return 0;
1857e1da 6504 case PIPE_B:
6d293983
ACO		 6505 if (pipe_config->fdi_lanes <= 2)
6506 return 0;
6507
6508 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_C));
6509 other_crtc_state =
6510 intel_atomic_get_crtc_state(state, other_crtc);
6511 if (IS_ERR(other_crtc_state))
6512 return PTR_ERR(other_crtc_state);
6513
6514 if (pipe_required_fdi_lanes(other_crtc_state) > 0) {
1857e1da
DV		 6515 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
6516 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6517 return -EINVAL;
1857e1da 6518 }
6d293983 6519 return 0;
1857e1da 6520 case PIPE_C:
251cc67c
VS		 6521 if (pipe_config->fdi_lanes > 2) {
6522 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
6523 pipe_name(pipe), pipe_config->fdi_lanes);
6d293983 6524 return -EINVAL;
251cc67c 6525 }
6d293983
ACO		 6526
6527 other_crtc = to_intel_crtc(intel_get_crtc_for_pipe(dev, PIPE_B));
6528 other_crtc_state =
6529 intel_atomic_get_crtc_state(state, other_crtc);
6530 if (IS_ERR(other_crtc_state))
6531 return PTR_ERR(other_crtc_state);
6532
6533 if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
1857e1da 6534 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
6d293983 6535 return -EINVAL;
1857e1da 6536 }
6d293983 6537 return 0;
1857e1da
DV		 6538 default:
6539 BUG();
6540 }
6541}
6542
e29c22c0
DV		 6543#define RETRY 1
6544static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 6545 struct intel_crtc_state *pipe_config)
877d48d5 6546{
1857e1da 6547 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 6548 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
6d293983
ACO		 6549 int lane, link_bw, fdi_dotclock, ret;
6550 bool needs_recompute = false;
877d48d5 6551
e29c22c0 6552retry:
877d48d5
DV		 6553 /* FDI is a binary signal running at ~2.7GHz, encoding
6554 * each output octet as 10 bits. The actual frequency
6555 * is stored as a divider into a 100MHz clock, and the
6556 * mode pixel clock is stored in units of 1KHz.
6557 * Hence the bw of each lane in terms of the mode signal
6558 * is:
6559 */
6560 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
6561
241bfc38 6562 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 6563
2bd89a07 6564 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 6565 pipe_config->pipe_bpp);
6566
6567 pipe_config->fdi_lanes = lane;
6568
2bd89a07 6569 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 6570 link_bw, &pipe_config->fdi_m_n);
1857e1da 6571
6d293983
ACO		 6572 ret = ironlake_check_fdi_lanes(intel_crtc->base.dev,
6573 intel_crtc->pipe, pipe_config);
6574 if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
e29c22c0
DV		 6575 pipe_config->pipe_bpp -= 2*3;
6576 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
6577 pipe_config->pipe_bpp);
6578 needs_recompute = true;
6579 pipe_config->bw_constrained = true;
6580
6581 goto retry;
6582 }
6583
6584 if (needs_recompute)
6585 return RETRY;
6586
6d293983 6587 return ret;
877d48d5
DV		 6588}
6589
42db64ef 6590static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 6591 struct intel_crtc_state *pipe_config)
42db64ef 6592{
d330a953 6593 pipe_config->ips_enabled = i915.enable_ips &&
3c4ca58c 6594 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 6595 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 6596}
6597
a43f6e0f 6598static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 6599 struct intel_crtc_state *pipe_config)
79e53945 6600{
a43f6e0f 6601 struct drm_device *dev = crtc->base.dev;
8bd31e67 6602 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 6603 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
d03c93d4 6604 int ret;
89749350 6605
ad3a4479 6606 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 6607 if (INTEL_INFO(dev)->gen < 4) {
cf532bb2
VS		 6608 int clock_limit =
6609 dev_priv->display.get_display_clock_speed(dev);
6610
6611 /*
6612 * Enable pixel doubling when the dot clock
6613 * is > 90% of the (display) core speed.
6614 *
b397c96b
VS		 6615 * GDG double wide on either pipe,
6616 * otherwise pipe A only.
cf532bb2 6617 */
b397c96b 6618 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 6619 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 6620 clock_limit *= 2;
cf532bb2 6621 pipe_config->double_wide = true;
ad3a4479
VS		 6622 }
6623
241bfc38 6624 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 6625 return -EINVAL;
2c07245f 6626 }
89749350 6627
1d1d0e27
VS		 6628 /*
6629 * Pipe horizontal size must be even in:
6630 * - DVO ganged mode
6631 * - LVDS dual channel mode
6632 * - Double wide pipe
6633 */
a93e255f 6634 if ((intel_pipe_will_have_type(pipe_config, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 6635 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
6636 pipe_config->pipe_src_w &= ~1;
6637
8693a824
DL		 6638 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
6639 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 6640 */
6641 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
6642 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 6643 return -EINVAL;
44f46b42 6644
f5adf94e 6645 if (HAS_IPS(dev))
a43f6e0f
DV		 6646 hsw_compute_ips_config(crtc, pipe_config);
6647
877d48d5 6648 if (pipe_config->has_pch_encoder)
a43f6e0f 6649 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 6650
d03c93d4
CK		 6651 /* FIXME: remove below call once atomic mode set is place and all crtc
6652 * related checks called from atomic_crtc_check function */
6653 ret = 0;
6654 DRM_DEBUG_KMS("intel_crtc = %p drm_state (pipe_config->base.state) = %p\n",
6655 crtc, pipe_config->base.state);
6656 ret = intel_atomic_setup_scalers(dev, crtc, pipe_config);
6657
6658 return ret;
79e53945
JB		 6659}
6660
1652d19e
VS		 6661static int skylake_get_display_clock_speed(struct drm_device *dev)
6662{
6663 struct drm_i915_private *dev_priv = to_i915(dev);
6664 uint32_t lcpll1 = I915_READ(LCPLL1_CTL);
6665 uint32_t cdctl = I915_READ(CDCLK_CTL);
6666 uint32_t linkrate;
6667
6668 if (!(lcpll1 & LCPLL_PLL_ENABLE)) {
6669 WARN(1, "LCPLL1 not enabled\n");
6670 return 24000; /* 24MHz is the cd freq with NSSC ref */
6671 }
6672
6673 if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540)
6674 return 540000;
6675
6676 linkrate = (I915_READ(DPLL_CTRL1) &
71cd8423 6677 DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
1652d19e 6678
71cd8423
DL		 6679 if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
6680 linkrate == DPLL_CTRL1_LINK_RATE_1080) {
1652d19e
VS		 6681 /* vco 8640 */
6682 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6683 case CDCLK_FREQ_450_432:
6684 return 432000;
6685 case CDCLK_FREQ_337_308:
6686 return 308570;
6687 case CDCLK_FREQ_675_617:
6688 return 617140;
6689 default:
6690 WARN(1, "Unknown cd freq selection\n");
6691 }
6692 } else {
6693 /* vco 8100 */
6694 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
6695 case CDCLK_FREQ_450_432:
6696 return 450000;
6697 case CDCLK_FREQ_337_308:
6698 return 337500;
6699 case CDCLK_FREQ_675_617:
6700 return 675000;
6701 default:
6702 WARN(1, "Unknown cd freq selection\n");
6703 }
6704 }
6705
6706 /* error case, do as if DPLL0 isn't enabled */
6707 return 24000;
6708}
6709
6710static int broadwell_get_display_clock_speed(struct drm_device *dev)
6711{
6712 struct drm_i915_private *dev_priv = dev->dev_private;
6713 uint32_t lcpll = I915_READ(LCPLL_CTL);
6714 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6715
6716 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6717 return 800000;
6718 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6719 return 450000;
6720 else if (freq == LCPLL_CLK_FREQ_450)
6721 return 450000;
6722 else if (freq == LCPLL_CLK_FREQ_54O_BDW)
6723 return 540000;
6724 else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
6725 return 337500;
6726 else
6727 return 675000;
6728}
6729
6730static int haswell_get_display_clock_speed(struct drm_device *dev)
6731{
6732 struct drm_i915_private *dev_priv = dev->dev_private;
6733 uint32_t lcpll = I915_READ(LCPLL_CTL);
6734 uint32_t freq = lcpll & LCPLL_CLK_FREQ_MASK;
6735
6736 if (lcpll & LCPLL_CD_SOURCE_FCLK)
6737 return 800000;
6738 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT)
6739 return 450000;
6740 else if (freq == LCPLL_CLK_FREQ_450)
6741 return 450000;
6742 else if (IS_HSW_ULT(dev))
6743 return 337500;
6744 else
6745 return 540000;
79e53945
JB		 6746}
6747
25eb05fc
JB		 6748static int valleyview_get_display_clock_speed(struct drm_device *dev)
6749{
d197b7d3 6750 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 6751 u32 val;
6752 int divider;
6753
6bcda4f0
VS		 6754 if (dev_priv->hpll_freq == 0)
6755 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
6756
d197b7d3
VS		 6757 mutex_lock(&dev_priv->dpio_lock);
6758 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
6759 mutex_unlock(&dev_priv->dpio_lock);
6760
6761 divider = val & DISPLAY_FREQUENCY_VALUES;
6762
7d007f40
VS		 6763 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
6764 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
6765 "cdclk change in progress\n");
6766
6bcda4f0 6767 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 6768}
6769
b37a6434
VS		 6770static int ilk_get_display_clock_speed(struct drm_device *dev)
6771{
6772 return 450000;
6773}
6774
e70236a8
JB		 6775static int i945_get_display_clock_speed(struct drm_device *dev)
6776{
6777 return 400000;
6778}
79e53945 6779
e70236a8 6780static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 6781{
e907f170 6782 return 333333;
e70236a8 6783}
79e53945 6784
e70236a8
JB		 6785static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
6786{
6787 return 200000;
6788}
79e53945 6789
257a7ffc
DV		 6790static int pnv_get_display_clock_speed(struct drm_device *dev)
6791{
6792 u16 gcfgc = 0;
6793
6794 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6795
6796 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6797 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
e907f170 6798 return 266667;
257a7ffc 6799 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
e907f170 6800 return 333333;
257a7ffc 6801 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
e907f170 6802 return 444444;
257a7ffc
DV		 6803 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
6804 return 200000;
6805 default:
6806 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
6807 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
e907f170 6808 return 133333;
257a7ffc 6809 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
e907f170 6810 return 166667;
257a7ffc
DV		 6811 }
6812}
6813
e70236a8
JB		 6814static int i915gm_get_display_clock_speed(struct drm_device *dev)
6815{
6816 u16 gcfgc = 0;
79e53945 6817
e70236a8
JB		 6818 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
6819
6820 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
e907f170 6821 return 133333;
e70236a8
JB		 6822 else {
6823 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
6824 case GC_DISPLAY_CLOCK_333_MHZ:
e907f170 6825 return 333333;
e70236a8
JB		 6826 default:
6827 case GC_DISPLAY_CLOCK_190_200_MHZ:
6828 return 190000;
79e53945 6829 }
e70236a8
JB		 6830 }
6831}
6832
6833static int i865_get_display_clock_speed(struct drm_device *dev)
6834{
e907f170 6835 return 266667;
e70236a8
JB		 6836}
6837
6838static int i855_get_display_clock_speed(struct drm_device *dev)
6839{
6840 u16 hpllcc = 0;
6841 /* Assume that the hardware is in the high speed state. This
6842 * should be the default.
6843 */
6844 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
6845 case GC_CLOCK_133_200:
6846 case GC_CLOCK_100_200:
6847 return 200000;
6848 case GC_CLOCK_166_250:
6849 return 250000;
6850 case GC_CLOCK_100_133:
e907f170 6851 return 133333;
e70236a8 6852 }
79e53945 6853
e70236a8
JB		 6854 /* Shouldn't happen */
6855 return 0;
6856}
79e53945 6857
e70236a8
JB		 6858static int i830_get_display_clock_speed(struct drm_device *dev)
6859{
e907f170 6860 return 133333;
79e53945
JB		 6861}
6862
2c07245f 6863static void
a65851af 6864intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 6865{
a65851af
VS		 6866 while (*num > DATA_LINK_M_N_MASK ||
6867 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 6868 *num >>= 1;
6869 *den >>= 1;
6870 }
6871}
6872
a65851af
VS		 6873static void compute_m_n(unsigned int m, unsigned int n,
6874 uint32_t *ret_m, uint32_t *ret_n)
6875{
6876 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
6877 *ret_m = div_u64((uint64_t) m * *ret_n, n);
6878 intel_reduce_m_n_ratio(ret_m, ret_n);
6879}
6880
e69d0bc1
DV		 6881void
6882intel_link_compute_m_n(int bits_per_pixel, int nlanes,
6883 int pixel_clock, int link_clock,
6884 struct intel_link_m_n *m_n)
2c07245f 6885{
e69d0bc1 6886 m_n->tu = 64;
a65851af
VS		 6887
6888 compute_m_n(bits_per_pixel * pixel_clock,
6889 link_clock * nlanes * 8,
6890 &m_n->gmch_m, &m_n->gmch_n);
6891
6892 compute_m_n(pixel_clock, link_clock,
6893 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 6894}
6895
a7615030
CW		 6896static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
6897{
d330a953
JN		 6898 if (i915.panel_use_ssc >= 0)
6899 return i915.panel_use_ssc != 0;
41aa3448 6900 return dev_priv->vbt.lvds_use_ssc
435793df 6901 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 6902}
6903
a93e255f
ACO		 6904static int i9xx_get_refclk(const struct intel_crtc_state *crtc_state,
6905 int num_connectors)
c65d77d8 6906{
a93e255f 6907 struct drm_device *dev = crtc_state->base.crtc->dev;
c65d77d8
JB		 6908 struct drm_i915_private *dev_priv = dev->dev_private;
6909 int refclk;
6910
a93e255f
ACO		 6911 WARN_ON(!crtc_state->base.state);
6912
5ab7b0b7 6913 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
9a0ea498 6914 refclk = 100000;
a93e255f 6915 } else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
c65d77d8 6916 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 6917 refclk = dev_priv->vbt.lvds_ssc_freq;
6918 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 6919 } else if (!IS_GEN2(dev)) {
6920 refclk = 96000;
6921 } else {
6922 refclk = 48000;
6923 }
6924
6925 return refclk;
6926}
6927
7429e9d4 6928static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 6929{
7df00d7a 6930 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 6931}
f47709a9 6932
7429e9d4
DV		 6933static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6934{
6935 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 6936}
6937
f47709a9 6938static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 6939 struct intel_crtc_state *crtc_state,
a7516a05
JB		 6940 intel_clock_t *reduced_clock)
6941{
f47709a9 6942 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 6943 u32 fp, fp2 = 0;
6944
6945 if (IS_PINEVIEW(dev)) {
190f68c5 6946 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6947 if (reduced_clock)
7429e9d4 6948 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 6949 } else {
190f68c5 6950 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6951 if (reduced_clock)
7429e9d4 6952 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 6953 }
6954
190f68c5 6955 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 6956
f47709a9 6957 crtc->lowfreq_avail = false;
a93e255f 6958 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
ab585dea 6959 reduced_clock) {
190f68c5 6960 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 6961 crtc->lowfreq_avail = true;
a7516a05 6962 } else {
190f68c5 6963 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 6964 }
6965}
6966
5e69f97f
CML		 6967static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6968 pipe)
89b667f8
JB		 6969{
6970 u32 reg_val;
6971
6972 /*
6973 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6974 * and set it to a reasonable value instead.
6975 */
ab3c759a 6976 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 6977 reg_val &= 0xffffff00;
6978 reg_val |= 0x00000030;
ab3c759a 6979 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6980
ab3c759a 6981 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6982 reg_val &= 0x8cffffff;
6983 reg_val = 0x8c000000;
ab3c759a 6984 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 6985
ab3c759a 6986 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 6987 reg_val &= 0xffffff00;
ab3c759a 6988 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6989
ab3c759a 6990 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6991 reg_val &= 0x00ffffff;
6992 reg_val |= 0xb0000000;
ab3c759a 6993 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 6994}
6995
b551842d
DV		 6996static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6997 struct intel_link_m_n *m_n)
6998{
6999 struct drm_device *dev = crtc->base.dev;
7000 struct drm_i915_private *dev_priv = dev->dev_private;
7001 int pipe = crtc->pipe;
7002
e3b95f1e
DV		 7003 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7004 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
7005 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
7006 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 7007}
7008
7009static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 7010 struct intel_link_m_n *m_n,
7011 struct intel_link_m_n *m2_n2)
b551842d
DV		 7012{
7013 struct drm_device *dev = crtc->base.dev;
7014 struct drm_i915_private *dev_priv = dev->dev_private;
7015 int pipe = crtc->pipe;
6e3c9717 7016 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 7017
7018 if (INTEL_INFO(dev)->gen >= 5) {
7019 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
7020 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
7021 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
7022 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 7023 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
7024 * for gen < 8) and if DRRS is supported (to make sure the
7025 * registers are not unnecessarily accessed).
7026 */
44395bfe 7027 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 7028 crtc->config->has_drrs) {
f769cd24
VK		 7029 I915_WRITE(PIPE_DATA_M2(transcoder),
7030 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
7031 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
7032 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
7033 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
7034 }
b551842d 7035 } else {
e3b95f1e
DV		 7036 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
7037 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
7038 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
7039 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 7040 }
7041}
7042
fe3cd48d 7043void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 7044{
fe3cd48d
R		 7045 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
7046
7047 if (m_n == M1_N1) {
7048 dp_m_n = &crtc->config->dp_m_n;
7049 dp_m2_n2 = &crtc->config->dp_m2_n2;
7050 } else if (m_n == M2_N2) {
7051
7052 /*
7053 * M2_N2 registers are not supported. Hence m2_n2 divider value
7054 * needs to be programmed into M1_N1.
7055 */
7056 dp_m_n = &crtc->config->dp_m2_n2;
7057 } else {
7058 DRM_ERROR("Unsupported divider value\n");
7059 return;
7060 }
7061
6e3c9717
ACO		 7062 if (crtc->config->has_pch_encoder)
7063 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 7064 else
fe3cd48d 7065 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 7066}
7067
d288f65f 7068static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 7069 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 7070{
7071 u32 dpll, dpll_md;
7072
7073 /*
7074 * Enable DPIO clock input. We should never disable the reference
7075 * clock for pipe B, since VGA hotplug / manual detection depends
7076 * on it.
7077 */
7078 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
7079 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
7080 /* We should never disable this, set it here for state tracking */
7081 if (crtc->pipe == PIPE_B)
7082 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
7083 dpll |= DPLL_VCO_ENABLE;
d288f65f 7084 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 7085
d288f65f 7086 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 7087 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 7088 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 7089}
7090
d288f65f 7091static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7092 const struct intel_crtc_state *pipe_config)
a0c4da24 7093{
f47709a9 7094 struct drm_device *dev = crtc->base.dev;
a0c4da24 7095 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 7096 int pipe = crtc->pipe;
bdd4b6a6 7097 u32 mdiv;
a0c4da24 7098 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 7099 u32 coreclk, reg_val;
a0c4da24 7100
09153000
DV		 7101 mutex_lock(&dev_priv->dpio_lock);
7102
d288f65f
VS		 7103 bestn = pipe_config->dpll.n;
7104 bestm1 = pipe_config->dpll.m1;
7105 bestm2 = pipe_config->dpll.m2;
7106 bestp1 = pipe_config->dpll.p1;
7107 bestp2 = pipe_config->dpll.p2;
a0c4da24 7108
89b667f8
JB		 7109 /* See eDP HDMI DPIO driver vbios notes doc */
7110
7111 /* PLL B needs special handling */
bdd4b6a6 7112 if (pipe == PIPE_B)
5e69f97f 7113 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 7114
7115 /* Set up Tx target for periodic Rcomp update */
ab3c759a 7116 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 7117
7118 /* Disable target IRef on PLL */
ab3c759a 7119 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 7120 reg_val &= 0x00ffffff;
ab3c759a 7121 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 7122
7123 /* Disable fast lock */
ab3c759a 7124 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 7125
7126 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 7127 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
7128 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
7129 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 7130 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 7131
7132 /*
7133 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
7134 * but we don't support that).
7135 * Note: don't use the DAC post divider as it seems unstable.
7136 */
7137 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 7138 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7139
a0c4da24 7140 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 7141 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 7142
89b667f8 7143 /* Set HBR and RBR LPF coefficients */
d288f65f 7144 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 7145 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
7146 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 7147 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 7148 0x009f0003);
89b667f8 7149 else
ab3c759a 7150 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 7151 0x00d0000f);
7152
681a8504 7153 if (pipe_config->has_dp_encoder) {
89b667f8 7154 /* Use SSC source */
bdd4b6a6 7155 if (pipe == PIPE_A)
ab3c759a 7156 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7157 0x0df40000);
7158 else
ab3c759a 7159 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7160 0x0df70000);
7161 } else { /* HDMI or VGA */
7162 /* Use bend source */
bdd4b6a6 7163 if (pipe == PIPE_A)
ab3c759a 7164 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7165 0x0df70000);
7166 else
ab3c759a 7167 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 7168 0x0df40000);
7169 }
a0c4da24 7170
ab3c759a 7171 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 7172 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 7173 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
7174 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 7175 coreclk |= 0x01000000;
ab3c759a 7176 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 7177
ab3c759a 7178 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
09153000 7179 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 7180}
7181
d288f65f 7182static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 7183 struct intel_crtc_state *pipe_config)
1ae0d137 7184{
d288f65f 7185 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 7186 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
7187 DPLL_VCO_ENABLE;
7188 if (crtc->pipe != PIPE_A)
d288f65f 7189 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 7190
d288f65f
VS		 7191 pipe_config->dpll_hw_state.dpll_md =
7192 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 7193}
7194
d288f65f 7195static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 7196 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 7197{
7198 struct drm_device *dev = crtc->base.dev;
7199 struct drm_i915_private *dev_priv = dev->dev_private;
7200 int pipe = crtc->pipe;
7201 int dpll_reg = DPLL(crtc->pipe);
7202 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 7203 u32 loopfilter, tribuf_calcntr;
9d556c99 7204 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 7205 u32 dpio_val;
9cbe40c1 7206 int vco;
9d556c99 7207
d288f65f
VS		 7208 bestn = pipe_config->dpll.n;
7209 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
7210 bestm1 = pipe_config->dpll.m1;
7211 bestm2 = pipe_config->dpll.m2 >> 22;
7212 bestp1 = pipe_config->dpll.p1;
7213 bestp2 = pipe_config->dpll.p2;
9cbe40c1 7214 vco = pipe_config->dpll.vco;
a945ce7e 7215 dpio_val = 0;
9cbe40c1 7216 loopfilter = 0;
9d556c99
CML		 7217
7218 /*
7219 * Enable Refclk and SSC
7220 */
a11b0703 7221 I915_WRITE(dpll_reg,
d288f65f 7222 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703
VS		 7223
7224 mutex_lock(&dev_priv->dpio_lock);
9d556c99 7225
9d556c99
CML		 7226 /* p1 and p2 divider */
7227 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
7228 5 << DPIO_CHV_S1_DIV_SHIFT |
7229 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
7230 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
7231 1 << DPIO_CHV_K_DIV_SHIFT);
7232
7233 /* Feedback post-divider - m2 */
7234 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
7235
7236 /* Feedback refclk divider - n and m1 */
7237 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
7238 DPIO_CHV_M1_DIV_BY_2 |
7239 1 << DPIO_CHV_N_DIV_SHIFT);
7240
7241 /* M2 fraction division */
a945ce7e
VP		 7242 if (bestm2_frac)
7243 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 7244
7245 /* M2 fraction division enable */
a945ce7e
VP		 7246 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
7247 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
7248 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
7249 if (bestm2_frac)
7250 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
7251 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 7252
de3a0fde
VP		 7253 /* Program digital lock detect threshold */
7254 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
7255 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
7256 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
7257 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
7258 if (!bestm2_frac)
7259 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
7260 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
7261
9d556c99 7262 /* Loop filter */
9cbe40c1
VP		 7263 if (vco == 5400000) {
7264 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
7265 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
7266 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
7267 tribuf_calcntr = 0x9;
7268 } else if (vco <= 6200000) {
7269 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
7270 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
7271 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7272 tribuf_calcntr = 0x9;
7273 } else if (vco <= 6480000) {
7274 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7275 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7276 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7277 tribuf_calcntr = 0x8;
7278 } else {
7279 /* Not supported. Apply the same limits as in the max case */
7280 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
7281 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
7282 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
7283 tribuf_calcntr = 0;
7284 }
9d556c99
CML		 7285 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
7286
968040b2 7287 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 7288 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
7289 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
7290 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
7291
9d556c99
CML		 7292 /* AFC Recal */
7293 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
7294 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
7295 DPIO_AFC_RECAL);
7296
7297 mutex_unlock(&dev_priv->dpio_lock);
7298}
7299
d288f65f
VS		 7300/**
7301 * vlv_force_pll_on - forcibly enable just the PLL
7302 * @dev_priv: i915 private structure
7303 * @pipe: pipe PLL to enable
7304 * @dpll: PLL configuration
7305 *
7306 * Enable the PLL for @pipe using the supplied @dpll config. To be used
7307 * in cases where we need the PLL enabled even when @pipe is not going to
7308 * be enabled.
7309 */
7310void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
7311 const struct dpll *dpll)
7312{
7313 struct intel_crtc *crtc =
7314 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 7315 struct intel_crtc_state pipe_config = {
a93e255f 7316 .base.crtc = &crtc->base,
d288f65f
VS		 7317 .pixel_multiplier = 1,
7318 .dpll = *dpll,
7319 };
7320
7321 if (IS_CHERRYVIEW(dev)) {
7322 chv_update_pll(crtc, &pipe_config);
7323 chv_prepare_pll(crtc, &pipe_config);
7324 chv_enable_pll(crtc, &pipe_config);
7325 } else {
7326 vlv_update_pll(crtc, &pipe_config);
7327 vlv_prepare_pll(crtc, &pipe_config);
7328 vlv_enable_pll(crtc, &pipe_config);
7329 }
7330}
7331
7332/**
7333 * vlv_force_pll_off - forcibly disable just the PLL
7334 * @dev_priv: i915 private structure
7335 * @pipe: pipe PLL to disable
7336 *
7337 * Disable the PLL for @pipe. To be used in cases where we need
7338 * the PLL enabled even when @pipe is not going to be enabled.
7339 */
7340void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
7341{
7342 if (IS_CHERRYVIEW(dev))
7343 chv_disable_pll(to_i915(dev), pipe);
7344 else
7345 vlv_disable_pll(to_i915(dev), pipe);
7346}
7347
f47709a9 7348static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 7349 struct intel_crtc_state *crtc_state,
f47709a9 7350 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7351 int num_connectors)
7352{
f47709a9 7353 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7354 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 7355 u32 dpll;
7356 bool is_sdvo;
190f68c5 7357 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7358
190f68c5 7359 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7360
a93e255f
ACO		 7361 is_sdvo = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_SDVO) ||
7362 intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 7363
7364 dpll = DPLL_VGA_MODE_DIS;
7365
a93e255f 7366 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 7367 dpll |= DPLLB_MODE_LVDS;
7368 else
7369 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 7370
ef1b460d 7371 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 7372 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 7373 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 7374 }
198a037f
DV		 7375
7376 if (is_sdvo)
4a33e48d 7377 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 7378
190f68c5 7379 if (crtc_state->has_dp_encoder)
4a33e48d 7380 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 7381
7382 /* compute bitmask from p1 value */
7383 if (IS_PINEVIEW(dev))
7384 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
7385 else {
7386 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7387 if (IS_G4X(dev) && reduced_clock)
7388 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
7389 }
7390 switch (clock->p2) {
7391 case 5:
7392 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7393 break;
7394 case 7:
7395 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7396 break;
7397 case 10:
7398 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7399 break;
7400 case 14:
7401 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7402 break;
7403 }
7404 if (INTEL_INFO(dev)->gen >= 4)
7405 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
7406
190f68c5 7407 if (crtc_state->sdvo_tv_clock)
eb1cbe48 7408 dpll |= PLL_REF_INPUT_TVCLKINBC;
a93e255f 7409 else if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7410 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7411 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7412 else
7413 dpll |= PLL_REF_INPUT_DREFCLK;
7414
7415 dpll |= DPLL_VCO_ENABLE;
190f68c5 7416 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 7417
eb1cbe48 7418 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 7419 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 7420 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 7421 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 7422 }
7423}
7424
f47709a9 7425static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 7426 struct intel_crtc_state *crtc_state,
f47709a9 7427 intel_clock_t *reduced_clock,
eb1cbe48
DV		 7428 int num_connectors)
7429{
f47709a9 7430 struct drm_device *dev = crtc->base.dev;
eb1cbe48 7431 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 7432 u32 dpll;
190f68c5 7433 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 7434
190f68c5 7435 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 7436
eb1cbe48
DV		 7437 dpll = DPLL_VGA_MODE_DIS;
7438
a93e255f 7439 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 7440 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7441 } else {
7442 if (clock->p1 == 2)
7443 dpll |= PLL_P1_DIVIDE_BY_TWO;
7444 else
7445 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
7446 if (clock->p2 == 4)
7447 dpll |= PLL_P2_DIVIDE_BY_4;
7448 }
7449
a93e255f 7450 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_DVO))
4a33e48d
DV		 7451 dpll |= DPLL_DVO_2X_MODE;
7452
a93e255f 7453 if (intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 7454 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
7455 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
7456 else
7457 dpll |= PLL_REF_INPUT_DREFCLK;
7458
7459 dpll |= DPLL_VCO_ENABLE;
190f68c5 7460 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 7461}
7462
8a654f3b 7463static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 7464{
7465 struct drm_device *dev = intel_crtc->base.dev;
7466 struct drm_i915_private *dev_priv = dev->dev_private;
7467 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7468 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 7469 struct drm_display_mode *adjusted_mode =
6e3c9717 7470 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 7471 uint32_t crtc_vtotal, crtc_vblank_end;
7472 int vsyncshift = 0;
4d8a62ea
DV		 7473
7474 /* We need to be careful not to changed the adjusted mode, for otherwise
7475 * the hw state checker will get angry at the mismatch. */
7476 crtc_vtotal = adjusted_mode->crtc_vtotal;
7477 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 7478
609aeaca 7479 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 7480 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 7481 crtc_vtotal -= 1;
7482 crtc_vblank_end -= 1;
609aeaca 7483
409ee761 7484 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 7485 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
7486 else
7487 vsyncshift = adjusted_mode->crtc_hsync_start -
7488 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 7489 if (vsyncshift < 0)
7490 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 7491 }
7492
7493 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 7494 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 7495
fe2b8f9d 7496 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 7497 (adjusted_mode->crtc_hdisplay - 1) |
7498 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 7499 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 7500 (adjusted_mode->crtc_hblank_start - 1) |
7501 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 7502 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 7503 (adjusted_mode->crtc_hsync_start - 1) |
7504 ((adjusted_mode->crtc_hsync_end - 1) << 16));
7505
fe2b8f9d 7506 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 7507 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 7508 ((crtc_vtotal - 1) << 16));
fe2b8f9d 7509 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 7510 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 7511 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 7512 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 7513 (adjusted_mode->crtc_vsync_start - 1) |
7514 ((adjusted_mode->crtc_vsync_end - 1) << 16));
7515
b5e508d4
PZ		 7516 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
7517 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
7518 * documented on the DDI_FUNC_CTL register description, EDP Input Select
7519 * bits. */
7520 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
7521 (pipe == PIPE_B || pipe == PIPE_C))
7522 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
7523
b0e77b9c
PZ		 7524 /* pipesrc controls the size that is scaled from, which should
7525 * always be the user's requested size.
7526 */
7527 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 7528 ((intel_crtc->config->pipe_src_w - 1) << 16) |
7529 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 7530}
7531
1bd1bd80 7532static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 7533 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 7534{
7535 struct drm_device *dev = crtc->base.dev;
7536 struct drm_i915_private *dev_priv = dev->dev_private;
7537 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7538 uint32_t tmp;
7539
7540 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 7541 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
7542 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7543 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 7544 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
7545 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7546 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 7547 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
7548 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7549
7550 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 7551 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
7552 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7553 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 7554 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
7555 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 7556 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 7557 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
7558 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 7559
7560 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 7561 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
7562 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
7563 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 7564 }
7565
7566 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 7567 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
7568 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
7569
2d112de7
ACO		 7570 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
7571 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 7572}
7573
f6a83288 7574void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 7575 struct intel_crtc_state *pipe_config)
babea61d 7576{
2d112de7
ACO		 7577 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
7578 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
7579 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
7580 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 7581
2d112de7
ACO		 7582 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
7583 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
7584 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
7585 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 7586
2d112de7 7587 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 7588
2d112de7
ACO		 7589 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
7590 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 7591}
7592
84b046f3
DV		 7593static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
7594{
7595 struct drm_device *dev = intel_crtc->base.dev;
7596 struct drm_i915_private *dev_priv = dev->dev_private;
7597 uint32_t pipeconf;
7598
9f11a9e4 7599 pipeconf = 0;
84b046f3 7600
b6b5d049
VS		 7601 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
7602 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
7603 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 7604
6e3c9717 7605 if (intel_crtc->config->double_wide)
cf532bb2 7606 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 7607
ff9ce46e
DV		 7608 /* only g4x and later have fancy bpc/dither controls */
7609 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 7610 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 7611 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 7612 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 7613 PIPECONF_DITHER_TYPE_SP;
84b046f3 7614
6e3c9717 7615 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 7616 case 18:
7617 pipeconf |= PIPECONF_6BPC;
7618 break;
7619 case 24:
7620 pipeconf |= PIPECONF_8BPC;
7621 break;
7622 case 30:
7623 pipeconf |= PIPECONF_10BPC;
7624 break;
7625 default:
7626 /* Case prevented by intel_choose_pipe_bpp_dither. */
7627 BUG();
84b046f3
DV		 7628 }
7629 }
7630
7631 if (HAS_PIPE_CXSR(dev)) {
7632 if (intel_crtc->lowfreq_avail) {
7633 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
7634 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
7635 } else {
7636 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 7637 }
7638 }
7639
6e3c9717 7640 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 7641 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 7642 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 7643 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
7644 else
7645 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
7646 } else
84b046f3
DV		 7647 pipeconf |= PIPECONF_PROGRESSIVE;
7648
6e3c9717 7649 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 7650 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 7651
84b046f3
DV		 7652 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
7653 POSTING_READ(PIPECONF(intel_crtc->pipe));
7654}
7655
190f68c5
ACO		 7656static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
7657 struct intel_crtc_state *crtc_state)
79e53945 7658{
c7653199 7659 struct drm_device *dev = crtc->base.dev;
79e53945 7660 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 7661 int refclk, num_connectors = 0;
652c393a 7662 intel_clock_t clock, reduced_clock;
a16af721 7663 bool ok, has_reduced_clock = false;
e9fd1c02 7664 bool is_lvds = false, is_dsi = false;
5eddb70b 7665 struct intel_encoder *encoder;
d4906093 7666 const intel_limit_t *limit;
55bb9992 7667 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 7668 struct drm_connector *connector;
55bb9992
ACO		 7669 struct drm_connector_state *connector_state;
7670 int i;
79e53945 7671
dd3cd74a
ACO		 7672 memset(&crtc_state->dpll_hw_state, 0,
7673 sizeof(crtc_state->dpll_hw_state));
7674
da3ced29 7675 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 7676 if (connector_state->crtc != &crtc->base)
7677 continue;
7678
7679 encoder = to_intel_encoder(connector_state->best_encoder);
7680
5eddb70b 7681 switch (encoder->type) {
79e53945
JB		 7682 case INTEL_OUTPUT_LVDS:
7683 is_lvds = true;
7684 break;
e9fd1c02
JN		 7685 case INTEL_OUTPUT_DSI:
7686 is_dsi = true;
7687 break;
6847d71b
PZ		 7688 default:
7689 break;
79e53945 7690 }
43565a06 7691
c751ce4f 7692 num_connectors++;
79e53945
JB		 7693 }
7694
f2335330 7695 if (is_dsi)
5b18e57c 7696 return 0;
f2335330 7697
190f68c5 7698 if (!crtc_state->clock_set) {
a93e255f 7699 refclk = i9xx_get_refclk(crtc_state, num_connectors);
79e53945 7700
e9fd1c02
JN		 7701 /*
7702 * Returns a set of divisors for the desired target clock with
7703 * the given refclk, or FALSE. The returned values represent
7704 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
7705 * 2) / p1 / p2.
7706 */
a93e255f
ACO		 7707 limit = intel_limit(crtc_state, refclk);
7708 ok = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 7709 crtc_state->port_clock,
e9fd1c02 7710 refclk, NULL, &clock);
f2335330 7711 if (!ok) {
e9fd1c02
JN		 7712 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7713 return -EINVAL;
7714 }
79e53945 7715
f2335330
JN		 7716 if (is_lvds && dev_priv->lvds_downclock_avail) {
7717 /*
7718 * Ensure we match the reduced clock's P to the target
7719 * clock. If the clocks don't match, we can't switch
7720 * the display clock by using the FP0/FP1. In such case
7721 * we will disable the LVDS downclock feature.
7722 */
7723 has_reduced_clock =
a93e255f 7724 dev_priv->display.find_dpll(limit, crtc_state,
f2335330
JN		 7725 dev_priv->lvds_downclock,
7726 refclk, &clock,
7727 &reduced_clock);
7728 }
7729 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7730 crtc_state->dpll.n = clock.n;
7731 crtc_state->dpll.m1 = clock.m1;
7732 crtc_state->dpll.m2 = clock.m2;
7733 crtc_state->dpll.p1 = clock.p1;
7734 crtc_state->dpll.p2 = clock.p2;
f47709a9 7735 }
7026d4ac 7736
e9fd1c02 7737 if (IS_GEN2(dev)) {
190f68c5 7738 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 7739 has_reduced_clock ? &reduced_clock : NULL,
7740 num_connectors);
9d556c99 7741 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 7742 chv_update_pll(crtc, crtc_state);
e9fd1c02 7743 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 7744 vlv_update_pll(crtc, crtc_state);
e9fd1c02 7745 } else {
190f68c5 7746 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 7747 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 7748 num_connectors);
e9fd1c02 7749 }
79e53945 7750
c8f7a0db 7751 return 0;
f564048e
EA		 7752}
7753
2fa2fe9a 7754static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7755 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7756{
7757 struct drm_device *dev = crtc->base.dev;
7758 struct drm_i915_private *dev_priv = dev->dev_private;
7759 uint32_t tmp;
7760
dc9e7dec
VS		 7761 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
7762 return;
7763
2fa2fe9a 7764 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 7765 if (!(tmp & PFIT_ENABLE))
7766 return;
2fa2fe9a 7767
06922821 7768 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 7769 if (INTEL_INFO(dev)->gen < 4) {
7770 if (crtc->pipe != PIPE_B)
7771 return;
2fa2fe9a
DV		 7772 } else {
7773 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
7774 return;
7775 }
7776
06922821 7777 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 7778 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
7779 if (INTEL_INFO(dev)->gen < 5)
7780 pipe_config->gmch_pfit.lvds_border_bits =
7781 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
7782}
7783
acbec814 7784static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7785 struct intel_crtc_state *pipe_config)
acbec814
JB		 7786{
7787 struct drm_device *dev = crtc->base.dev;
7788 struct drm_i915_private *dev_priv = dev->dev_private;
7789 int pipe = pipe_config->cpu_transcoder;
7790 intel_clock_t clock;
7791 u32 mdiv;
662c6ecb 7792 int refclk = 100000;
acbec814 7793
f573de5a
SK		 7794 /* In case of MIPI DPLL will not even be used */
7795 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
7796 return;
7797
acbec814 7798 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 7799 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
acbec814
JB		 7800 mutex_unlock(&dev_priv->dpio_lock);
7801
7802 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
7803 clock.m2 = mdiv & DPIO_M2DIV_MASK;
7804 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
7805 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
7806 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
7807
f646628b 7808 vlv_clock(refclk, &clock);
acbec814 7809
f646628b
VS		 7810 /* clock.dot is the fast clock */
7811 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 7812}
7813
5724dbd1
DL		 7814static void
7815i9xx_get_initial_plane_config(struct intel_crtc *crtc,
7816 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 7817{
7818 struct drm_device *dev = crtc->base.dev;
7819 struct drm_i915_private *dev_priv = dev->dev_private;
7820 u32 val, base, offset;
7821 int pipe = crtc->pipe, plane = crtc->plane;
7822 int fourcc, pixel_format;
6761dd31 7823 unsigned int aligned_height;
b113d5ee 7824 struct drm_framebuffer *fb;
1b842c89 7825 struct intel_framebuffer *intel_fb;
1ad292b5 7826
42a7b088
DL		 7827 val = I915_READ(DSPCNTR(plane));
7828 if (!(val & DISPLAY_PLANE_ENABLE))
7829 return;
7830
d9806c9f 7831 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7832 if (!intel_fb) {
1ad292b5
JB		 7833 DRM_DEBUG_KMS("failed to alloc fb\n");
7834 return;
7835 }
7836
1b842c89
DL		 7837 fb = &intel_fb->base;
7838
18c5247e
DV		 7839 if (INTEL_INFO(dev)->gen >= 4) {
7840 if (val & DISPPLANE_TILED) {
49af449b 7841 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 7842 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7843 }
7844 }
1ad292b5
JB		 7845
7846 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 7847 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 7848 fb->pixel_format = fourcc;
7849 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 7850
7851 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 7852 if (plane_config->tiling)
1ad292b5
JB		 7853 offset = I915_READ(DSPTILEOFF(plane));
7854 else
7855 offset = I915_READ(DSPLINOFF(plane));
7856 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
7857 } else {
7858 base = I915_READ(DSPADDR(plane));
7859 }
7860 plane_config->base = base;
7861
7862 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 7863 fb->width = ((val >> 16) & 0xfff) + 1;
7864 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 7865
7866 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 7867 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 7868
b113d5ee 7869 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7870 fb->pixel_format,
7871 fb->modifier[0]);
1ad292b5 7872
f37b5c2b 7873 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 7874
2844a921
DL		 7875 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7876 pipe_name(pipe), plane, fb->width, fb->height,
7877 fb->bits_per_pixel, base, fb->pitches[0],
7878 plane_config->size);
1ad292b5 7879
2d14030b 7880 plane_config->fb = intel_fb;
1ad292b5
JB		 7881}
7882
70b23a98 7883static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 7884 struct intel_crtc_state *pipe_config)
70b23a98
VS		 7885{
7886 struct drm_device *dev = crtc->base.dev;
7887 struct drm_i915_private *dev_priv = dev->dev_private;
7888 int pipe = pipe_config->cpu_transcoder;
7889 enum dpio_channel port = vlv_pipe_to_channel(pipe);
7890 intel_clock_t clock;
7891 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
7892 int refclk = 100000;
7893
7894 mutex_lock(&dev_priv->dpio_lock);
7895 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
7896 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
7897 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
7898 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
7899 mutex_unlock(&dev_priv->dpio_lock);
7900
7901 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
7902 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
7903 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
7904 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
7905 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
7906
7907 chv_clock(refclk, &clock);
7908
7909 /* clock.dot is the fast clock */
7910 pipe_config->port_clock = clock.dot / 5;
7911}
7912
0e8ffe1b 7913static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 7914 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 7915{
7916 struct drm_device *dev = crtc->base.dev;
7917 struct drm_i915_private *dev_priv = dev->dev_private;
7918 uint32_t tmp;
7919
f458ebbc
DV		 7920 if (!intel_display_power_is_enabled(dev_priv,
7921 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 7922 return false;
7923
e143a21c 7924 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 7925 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 7926
0e8ffe1b
DV		 7927 tmp = I915_READ(PIPECONF(crtc->pipe));
7928 if (!(tmp & PIPECONF_ENABLE))
7929 return false;
7930
42571aef
VS		 7931 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
7932 switch (tmp & PIPECONF_BPC_MASK) {
7933 case PIPECONF_6BPC:
7934 pipe_config->pipe_bpp = 18;
7935 break;
7936 case PIPECONF_8BPC:
7937 pipe_config->pipe_bpp = 24;
7938 break;
7939 case PIPECONF_10BPC:
7940 pipe_config->pipe_bpp = 30;
7941 break;
7942 default:
7943 break;
7944 }
7945 }
7946
b5a9fa09
DV		 7947 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7948 pipe_config->limited_color_range = true;
7949
282740f7
VS		 7950 if (INTEL_INFO(dev)->gen < 4)
7951 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7952
1bd1bd80
DV		 7953 intel_get_pipe_timings(crtc, pipe_config);
7954
2fa2fe9a
DV		 7955 i9xx_get_pfit_config(crtc, pipe_config);
7956
6c49f241
DV		 7957 if (INTEL_INFO(dev)->gen >= 4) {
7958 tmp = I915_READ(DPLL_MD(crtc->pipe));
7959 pipe_config->pixel_multiplier =
7960 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7961 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 7962 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 7963 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7964 tmp = I915_READ(DPLL(crtc->pipe));
7965 pipe_config->pixel_multiplier =
7966 ((tmp & SDVO_MULTIPLIER_MASK)
7967 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7968 } else {
7969 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7970 * port and will be fixed up in the encoder->get_config
7971 * function. */
7972 pipe_config->pixel_multiplier = 1;
7973 }
8bcc2795
DV		 7974 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7975 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 7976 /*
7977 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7978 * on 830. Filter it out here so that we don't
7979 * report errors due to that.
7980 */
7981 if (IS_I830(dev))
7982 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7983
8bcc2795
DV		 7984 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7985 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 7986 } else {
7987 /* Mask out read-only status bits. */
7988 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7989 DPLL_PORTC_READY_MASK |
7990 DPLL_PORTB_READY_MASK);
8bcc2795 7991 }
6c49f241 7992
70b23a98
VS		 7993 if (IS_CHERRYVIEW(dev))
7994 chv_crtc_clock_get(crtc, pipe_config);
7995 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 7996 vlv_crtc_clock_get(crtc, pipe_config);
7997 else
7998 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 7999
0e8ffe1b
DV		 8000 return true;
8001}
8002
dde86e2d 8003static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 8004{
8005 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 8006 struct intel_encoder *encoder;
74cfd7ac 8007 u32 val, final;
13d83a67 8008 bool has_lvds = false;
199e5d79 8009 bool has_cpu_edp = false;
199e5d79 8010 bool has_panel = false;
99eb6a01
KP		 8011 bool has_ck505 = false;
8012 bool can_ssc = false;
13d83a67
JB		 8013
8014 /* We need to take the global config into account */
b2784e15 8015 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 8016 switch (encoder->type) {
8017 case INTEL_OUTPUT_LVDS:
8018 has_panel = true;
8019 has_lvds = true;
8020 break;
8021 case INTEL_OUTPUT_EDP:
8022 has_panel = true;
2de6905f 8023 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 8024 has_cpu_edp = true;
8025 break;
6847d71b
PZ		 8026 default:
8027 break;
13d83a67
JB		 8028 }
8029 }
8030
99eb6a01 8031 if (HAS_PCH_IBX(dev)) {
41aa3448 8032 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 8033 can_ssc = has_ck505;
8034 } else {
8035 has_ck505 = false;
8036 can_ssc = true;
8037 }
8038
2de6905f
ID		 8039 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
8040 has_panel, has_lvds, has_ck505);
13d83a67
JB		 8041
8042 /* Ironlake: try to setup display ref clock before DPLL
8043 * enabling. This is only under driver's control after
8044 * PCH B stepping, previous chipset stepping should be
8045 * ignoring this setting.
8046 */
74cfd7ac
CW		 8047 val = I915_READ(PCH_DREF_CONTROL);
8048
8049 /* As we must carefully and slowly disable/enable each source in turn,
8050 * compute the final state we want first and check if we need to
8051 * make any changes at all.
8052 */
8053 final = val;
8054 final &= ~DREF_NONSPREAD_SOURCE_MASK;
8055 if (has_ck505)
8056 final |= DREF_NONSPREAD_CK505_ENABLE;
8057 else
8058 final |= DREF_NONSPREAD_SOURCE_ENABLE;
8059
8060 final &= ~DREF_SSC_SOURCE_MASK;
8061 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
8062 final &= ~DREF_SSC1_ENABLE;
8063
8064 if (has_panel) {
8065 final |= DREF_SSC_SOURCE_ENABLE;
8066
8067 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8068 final |= DREF_SSC1_ENABLE;
8069
8070 if (has_cpu_edp) {
8071 if (intel_panel_use_ssc(dev_priv) && can_ssc)
8072 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
8073 else
8074 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
8075 } else
8076 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8077 } else {
8078 final |= DREF_SSC_SOURCE_DISABLE;
8079 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
8080 }
8081
8082 if (final == val)
8083 return;
8084
13d83a67 8085 /* Always enable nonspread source */
74cfd7ac 8086 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 8087
99eb6a01 8088 if (has_ck505)
74cfd7ac 8089 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 8090 else
74cfd7ac 8091 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 8092
199e5d79 8093 if (has_panel) {
74cfd7ac
CW		 8094 val &= ~DREF_SSC_SOURCE_MASK;
8095 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 8096
199e5d79 8097 /* SSC must be turned on before enabling the CPU output */
99eb6a01 8098 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8099 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 8100 val |= DREF_SSC1_ENABLE;
e77166b5 8101 } else
74cfd7ac 8102 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 8103
8104 /* Get SSC going before enabling the outputs */
74cfd7ac 8105 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8106 POSTING_READ(PCH_DREF_CONTROL);
8107 udelay(200);
8108
74cfd7ac 8109 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 8110
8111 /* Enable CPU source on CPU attached eDP */
199e5d79 8112 if (has_cpu_edp) {
99eb6a01 8113 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 8114 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 8115 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 8116 } else
74cfd7ac 8117 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 8118 } else
74cfd7ac 8119 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8120
74cfd7ac 8121 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8122 POSTING_READ(PCH_DREF_CONTROL);
8123 udelay(200);
8124 } else {
8125 DRM_DEBUG_KMS("Disabling SSC entirely\n");
8126
74cfd7ac 8127 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 8128
8129 /* Turn off CPU output */
74cfd7ac 8130 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 8131
74cfd7ac 8132 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 8133 POSTING_READ(PCH_DREF_CONTROL);
8134 udelay(200);
8135
8136 /* Turn off the SSC source */
74cfd7ac
CW		 8137 val &= ~DREF_SSC_SOURCE_MASK;
8138 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 8139
8140 /* Turn off SSC1 */
74cfd7ac 8141 val &= ~DREF_SSC1_ENABLE;
199e5d79 8142
74cfd7ac 8143 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 8144 POSTING_READ(PCH_DREF_CONTROL);
8145 udelay(200);
8146 }
74cfd7ac
CW		 8147
8148 BUG_ON(val != final);
13d83a67
JB		 8149}
8150
f31f2d55 8151static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 8152{
f31f2d55 8153 uint32_t tmp;
dde86e2d 8154
0ff066a9
PZ		 8155 tmp = I915_READ(SOUTH_CHICKEN2);
8156 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
8157 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8158
0ff066a9
PZ		 8159 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
8160 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
8161 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 8162
0ff066a9
PZ		 8163 tmp = I915_READ(SOUTH_CHICKEN2);
8164 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
8165 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 8166
0ff066a9
PZ		 8167 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
8168 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
8169 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 8170}
8171
8172/* WaMPhyProgramming:hsw */
8173static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
8174{
8175 uint32_t tmp;
dde86e2d
PZ		 8176
8177 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
8178 tmp &= ~(0xFF << 24);
8179 tmp |= (0x12 << 24);
8180 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
8181
dde86e2d
PZ		 8182 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
8183 tmp |= (1 << 11);
8184 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
8185
8186 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
8187 tmp |= (1 << 11);
8188 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
8189
dde86e2d
PZ		 8190 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
8191 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8192 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
8193
8194 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
8195 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
8196 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
8197
0ff066a9
PZ		 8198 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
8199 tmp &= ~(7 << 13);
8200 tmp |= (5 << 13);
8201 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 8202
0ff066a9
PZ		 8203 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
8204 tmp &= ~(7 << 13);
8205 tmp |= (5 << 13);
8206 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 8207
8208 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
8209 tmp &= ~0xFF;
8210 tmp |= 0x1C;
8211 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
8212
8213 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
8214 tmp &= ~0xFF;
8215 tmp |= 0x1C;
8216 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
8217
8218 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
8219 tmp &= ~(0xFF << 16);
8220 tmp |= (0x1C << 16);
8221 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
8222
8223 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
8224 tmp &= ~(0xFF << 16);
8225 tmp |= (0x1C << 16);
8226 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
8227
0ff066a9
PZ		 8228 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
8229 tmp |= (1 << 27);
8230 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 8231
0ff066a9
PZ		 8232 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
8233 tmp |= (1 << 27);
8234 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 8235
0ff066a9
PZ		 8236 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
8237 tmp &= ~(0xF << 28);
8238 tmp |= (4 << 28);
8239 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 8240
0ff066a9
PZ		 8241 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
8242 tmp &= ~(0xF << 28);
8243 tmp |= (4 << 28);
8244 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 8245}
8246
2fa86a1f
PZ		 8247/* Implements 3 different sequences from BSpec chapter "Display iCLK
8248 * Programming" based on the parameters passed:
8249 * - Sequence to enable CLKOUT_DP
8250 * - Sequence to enable CLKOUT_DP without spread
8251 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
8252 */
8253static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
8254 bool with_fdi)
f31f2d55
PZ		 8255{
8256 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 8257 uint32_t reg, tmp;
8258
8259 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
8260 with_spread = true;
8261 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
8262 with_fdi, "LP PCH doesn't have FDI\n"))
8263 with_fdi = false;
f31f2d55
PZ		 8264
8265 mutex_lock(&dev_priv->dpio_lock);
8266
8267 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8268 tmp &= ~SBI_SSCCTL_DISABLE;
8269 tmp |= SBI_SSCCTL_PATHALT;
8270 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8271
8272 udelay(24);
8273
2fa86a1f
PZ		 8274 if (with_spread) {
8275 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8276 tmp &= ~SBI_SSCCTL_PATHALT;
8277 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 8278
2fa86a1f
PZ		 8279 if (with_fdi) {
8280 lpt_reset_fdi_mphy(dev_priv);
8281 lpt_program_fdi_mphy(dev_priv);
8282 }
8283 }
dde86e2d 8284
2fa86a1f
PZ		 8285 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8286 SBI_GEN0 : SBI_DBUFF0;
8287 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8288 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8289 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 8290
8291 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 8292}
8293
47701c3b
PZ		 8294/* Sequence to disable CLKOUT_DP */
8295static void lpt_disable_clkout_dp(struct drm_device *dev)
8296{
8297 struct drm_i915_private *dev_priv = dev->dev_private;
8298 uint32_t reg, tmp;
8299
8300 mutex_lock(&dev_priv->dpio_lock);
8301
8302 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
8303 SBI_GEN0 : SBI_DBUFF0;
8304 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
8305 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
8306 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
8307
8308 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
8309 if (!(tmp & SBI_SSCCTL_DISABLE)) {
8310 if (!(tmp & SBI_SSCCTL_PATHALT)) {
8311 tmp |= SBI_SSCCTL_PATHALT;
8312 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8313 udelay(32);
8314 }
8315 tmp |= SBI_SSCCTL_DISABLE;
8316 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
8317 }
8318
8319 mutex_unlock(&dev_priv->dpio_lock);
8320}
8321
bf8fa3d3
PZ		 8322static void lpt_init_pch_refclk(struct drm_device *dev)
8323{
bf8fa3d3
PZ		 8324 struct intel_encoder *encoder;
8325 bool has_vga = false;
8326
b2784e15 8327 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 8328 switch (encoder->type) {
8329 case INTEL_OUTPUT_ANALOG:
8330 has_vga = true;
8331 break;
6847d71b
PZ		 8332 default:
8333 break;
bf8fa3d3
PZ		 8334 }
8335 }
8336
47701c3b
PZ		 8337 if (has_vga)
8338 lpt_enable_clkout_dp(dev, true, true);
8339 else
8340 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 8341}
8342
dde86e2d
PZ		 8343/*
8344 * Initialize reference clocks when the driver loads
8345 */
8346void intel_init_pch_refclk(struct drm_device *dev)
8347{
8348 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8349 ironlake_init_pch_refclk(dev);
8350 else if (HAS_PCH_LPT(dev))
8351 lpt_init_pch_refclk(dev);
8352}
8353
55bb9992 8354static int ironlake_get_refclk(struct intel_crtc_state *crtc_state)
d9d444cb 8355{
55bb9992 8356 struct drm_device *dev = crtc_state->base.crtc->dev;
d9d444cb 8357 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8358 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8359 struct drm_connector *connector;
55bb9992 8360 struct drm_connector_state *connector_state;
d9d444cb 8361 struct intel_encoder *encoder;
55bb9992 8362 int num_connectors = 0, i;
d9d444cb
JB		 8363 bool is_lvds = false;
8364
da3ced29 8365 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8366 if (connector_state->crtc != crtc_state->base.crtc)
8367 continue;
8368
8369 encoder = to_intel_encoder(connector_state->best_encoder);
8370
d9d444cb
JB		 8371 switch (encoder->type) {
8372 case INTEL_OUTPUT_LVDS:
8373 is_lvds = true;
8374 break;
6847d71b
PZ		 8375 default:
8376 break;
d9d444cb
JB		 8377 }
8378 num_connectors++;
8379 }
8380
8381 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 8382 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 8383 dev_priv->vbt.lvds_ssc_freq);
e91e941b 8384 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 8385 }
8386
8387 return 120000;
8388}
8389
6ff93609 8390static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 8391{
c8203565 8392 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 8393 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8394 int pipe = intel_crtc->pipe;
c8203565
PZ		 8395 uint32_t val;
8396
78114071 8397 val = 0;
c8203565 8398
6e3c9717 8399 switch (intel_crtc->config->pipe_bpp) {
c8203565 8400 case 18:
dfd07d72 8401 val |= PIPECONF_6BPC;
c8203565
PZ		 8402 break;
8403 case 24:
dfd07d72 8404 val |= PIPECONF_8BPC;
c8203565
PZ		 8405 break;
8406 case 30:
dfd07d72 8407 val |= PIPECONF_10BPC;
c8203565
PZ		 8408 break;
8409 case 36:
dfd07d72 8410 val |= PIPECONF_12BPC;
c8203565
PZ		 8411 break;
8412 default:
cc769b62
PZ		 8413 /* Case prevented by intel_choose_pipe_bpp_dither. */
8414 BUG();
c8203565
PZ		 8415 }
8416
6e3c9717 8417 if (intel_crtc->config->dither)
c8203565
PZ		 8418 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8419
6e3c9717 8420 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 8421 val |= PIPECONF_INTERLACED_ILK;
8422 else
8423 val |= PIPECONF_PROGRESSIVE;
8424
6e3c9717 8425 if (intel_crtc->config->limited_color_range)
3685a8f3 8426 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 8427
c8203565
PZ		 8428 I915_WRITE(PIPECONF(pipe), val);
8429 POSTING_READ(PIPECONF(pipe));
8430}
8431
86d3efce
VS		 8432/*
8433 * Set up the pipe CSC unit.
8434 *
8435 * Currently only full range RGB to limited range RGB conversion
8436 * is supported, but eventually this should handle various
8437 * RGB<->YCbCr scenarios as well.
8438 */
50f3b016 8439static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 8440{
8441 struct drm_device *dev = crtc->dev;
8442 struct drm_i915_private *dev_priv = dev->dev_private;
8443 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8444 int pipe = intel_crtc->pipe;
8445 uint16_t coeff = 0x7800; /* 1.0 */
8446
8447 /*
8448 * TODO: Check what kind of values actually come out of the pipe
8449 * with these coeff/postoff values and adjust to get the best
8450 * accuracy. Perhaps we even need to take the bpc value into
8451 * consideration.
8452 */
8453
6e3c9717 8454 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8455 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
8456
8457 /*
8458 * GY/GU and RY/RU should be the other way around according
8459 * to BSpec, but reality doesn't agree. Just set them up in
8460 * a way that results in the correct picture.
8461 */
8462 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
8463 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
8464
8465 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
8466 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
8467
8468 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
8469 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
8470
8471 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
8472 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
8473 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
8474
8475 if (INTEL_INFO(dev)->gen > 6) {
8476 uint16_t postoff = 0;
8477
6e3c9717 8478 if (intel_crtc->config->limited_color_range)
32cf0cb0 8479 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 8480
8481 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
8482 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
8483 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
8484
8485 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
8486 } else {
8487 uint32_t mode = CSC_MODE_YUV_TO_RGB;
8488
6e3c9717 8489 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 8490 mode |= CSC_BLACK_SCREEN_OFFSET;
8491
8492 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
8493 }
8494}
8495
6ff93609 8496static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 8497{
756f85cf
PZ		 8498 struct drm_device *dev = crtc->dev;
8499 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 8500 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 8501 enum pipe pipe = intel_crtc->pipe;
6e3c9717 8502 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 8503 uint32_t val;
8504
3eff4faa 8505 val = 0;
ee2b0b38 8506
6e3c9717 8507 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 8508 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
8509
6e3c9717 8510 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 8511 val |= PIPECONF_INTERLACED_ILK;
8512 else
8513 val |= PIPECONF_PROGRESSIVE;
8514
702e7a56
PZ		 8515 I915_WRITE(PIPECONF(cpu_transcoder), val);
8516 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 8517
8518 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
8519 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 8520
3cdf122c 8521 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 8522 val = 0;
8523
6e3c9717 8524 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 8525 case 18:
8526 val |= PIPEMISC_DITHER_6_BPC;
8527 break;
8528 case 24:
8529 val |= PIPEMISC_DITHER_8_BPC;
8530 break;
8531 case 30:
8532 val |= PIPEMISC_DITHER_10_BPC;
8533 break;
8534 case 36:
8535 val |= PIPEMISC_DITHER_12_BPC;
8536 break;
8537 default:
8538 /* Case prevented by pipe_config_set_bpp. */
8539 BUG();
8540 }
8541
6e3c9717 8542 if (intel_crtc->config->dither)
756f85cf
PZ		 8543 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
8544
8545 I915_WRITE(PIPEMISC(pipe), val);
8546 }
ee2b0b38
PZ		 8547}
8548
6591c6e4 8549static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 8550 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 8551 intel_clock_t *clock,
8552 bool *has_reduced_clock,
8553 intel_clock_t *reduced_clock)
8554{
8555 struct drm_device *dev = crtc->dev;
8556 struct drm_i915_private *dev_priv = dev->dev_private;
6591c6e4 8557 int refclk;
d4906093 8558 const intel_limit_t *limit;
a16af721 8559 bool ret, is_lvds = false;
79e53945 8560
a93e255f 8561 is_lvds = intel_pipe_will_have_type(crtc_state, INTEL_OUTPUT_LVDS);
79e53945 8562
55bb9992 8563 refclk = ironlake_get_refclk(crtc_state);
79e53945 8564
d4906093
ML		 8565 /*
8566 * Returns a set of divisors for the desired target clock with the given
8567 * refclk, or FALSE. The returned values represent the clock equation:
8568 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
8569 */
a93e255f
ACO		 8570 limit = intel_limit(crtc_state, refclk);
8571 ret = dev_priv->display.find_dpll(limit, crtc_state,
190f68c5 8572 crtc_state->port_clock,
ee9300bb 8573 refclk, NULL, clock);
6591c6e4
PZ		 8574 if (!ret)
8575 return false;
cda4b7d3 8576
ddc9003c 8577 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 8578 /*
8579 * Ensure we match the reduced clock's P to the target clock.
8580 * If the clocks don't match, we can't switch the display clock
8581 * by using the FP0/FP1. In such case we will disable the LVDS
8582 * downclock feature.
8583 */
ee9300bb 8584 *has_reduced_clock =
a93e255f 8585 dev_priv->display.find_dpll(limit, crtc_state,
ee9300bb
DV		 8586 dev_priv->lvds_downclock,
8587 refclk, clock,
8588 reduced_clock);
652c393a 8589 }
61e9653f 8590
6591c6e4
PZ		 8591 return true;
8592}
8593
d4b1931c
PZ		 8594int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
8595{
8596 /*
8597 * Account for spread spectrum to avoid
8598 * oversubscribing the link. Max center spread
8599 * is 2.5%; use 5% for safety's sake.
8600 */
8601 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 8602 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 8603}
8604
7429e9d4 8605static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 8606{
7429e9d4 8607 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 8608}
8609
de13a2e3 8610static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 8611 struct intel_crtc_state *crtc_state,
7429e9d4 8612 u32 *fp,
9a7c7890 8613 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 8614{
de13a2e3 8615 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 8616 struct drm_device *dev = crtc->dev;
8617 struct drm_i915_private *dev_priv = dev->dev_private;
55bb9992 8618 struct drm_atomic_state *state = crtc_state->base.state;
da3ced29 8619 struct drm_connector *connector;
55bb9992
ACO		 8620 struct drm_connector_state *connector_state;
8621 struct intel_encoder *encoder;
de13a2e3 8622 uint32_t dpll;
55bb9992 8623 int factor, num_connectors = 0, i;
09ede541 8624 bool is_lvds = false, is_sdvo = false;
79e53945 8625
da3ced29 8626 for_each_connector_in_state(state, connector, connector_state, i) {
55bb9992
ACO		 8627 if (connector_state->crtc != crtc_state->base.crtc)
8628 continue;
8629
8630 encoder = to_intel_encoder(connector_state->best_encoder);
8631
8632 switch (encoder->type) {
79e53945
JB		 8633 case INTEL_OUTPUT_LVDS:
8634 is_lvds = true;
8635 break;
8636 case INTEL_OUTPUT_SDVO:
7d57382e 8637 case INTEL_OUTPUT_HDMI:
79e53945 8638 is_sdvo = true;
79e53945 8639 break;
6847d71b
PZ		 8640 default:
8641 break;
79e53945 8642 }
43565a06 8643
c751ce4f 8644 num_connectors++;
79e53945 8645 }
79e53945 8646
c1858123 8647 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 8648 factor = 21;
8649 if (is_lvds) {
8650 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 8651 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 8652 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 8653 factor = 25;
190f68c5 8654 } else if (crtc_state->sdvo_tv_clock)
8febb297 8655 factor = 20;
c1858123 8656
190f68c5 8657 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 8658 *fp |= FP_CB_TUNE;
2c07245f 8659
9a7c7890
DV		 8660 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
8661 *fp2 |= FP_CB_TUNE;
8662
5eddb70b 8663 dpll = 0;
2c07245f 8664
a07d6787
EA		 8665 if (is_lvds)
8666 dpll |= DPLLB_MODE_LVDS;
8667 else
8668 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 8669
190f68c5 8670 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 8671 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 8672
8673 if (is_sdvo)
4a33e48d 8674 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 8675 if (crtc_state->has_dp_encoder)
4a33e48d 8676 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 8677
a07d6787 8678 /* compute bitmask from p1 value */
190f68c5 8679 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 8680 /* also FPA1 */
190f68c5 8681 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 8682
190f68c5 8683 switch (crtc_state->dpll.p2) {
a07d6787
EA		 8684 case 5:
8685 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
8686 break;
8687 case 7:
8688 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
8689 break;
8690 case 10:
8691 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
8692 break;
8693 case 14:
8694 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
8695 break;
79e53945
JB		 8696 }
8697
b4c09f3b 8698 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 8699 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 8700 else
8701 dpll |= PLL_REF_INPUT_DREFCLK;
8702
959e16d6 8703 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 8704}
8705
190f68c5
ACO		 8706static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
8707 struct intel_crtc_state *crtc_state)
de13a2e3 8708{
c7653199 8709 struct drm_device *dev = crtc->base.dev;
de13a2e3 8710 intel_clock_t clock, reduced_clock;
cbbab5bd 8711 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 8712 bool ok, has_reduced_clock = false;
8b47047b 8713 bool is_lvds = false;
e2b78267 8714 struct intel_shared_dpll *pll;
de13a2e3 8715
dd3cd74a
ACO		 8716 memset(&crtc_state->dpll_hw_state, 0,
8717 sizeof(crtc_state->dpll_hw_state));
8718
409ee761 8719 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 8720
5dc5298b
PZ		 8721 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
8722 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 8723
190f68c5 8724 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 8725 &has_reduced_clock, &reduced_clock);
190f68c5 8726 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 8727 DRM_ERROR("Couldn't find PLL settings for mode!\n");
8728 return -EINVAL;
79e53945 8729 }
f47709a9 8730 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 8731 if (!crtc_state->clock_set) {
8732 crtc_state->dpll.n = clock.n;
8733 crtc_state->dpll.m1 = clock.m1;
8734 crtc_state->dpll.m2 = clock.m2;
8735 crtc_state->dpll.p1 = clock.p1;
8736 crtc_state->dpll.p2 = clock.p2;
f47709a9 8737 }
79e53945 8738
5dc5298b 8739 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 8740 if (crtc_state->has_pch_encoder) {
8741 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 8742 if (has_reduced_clock)
7429e9d4 8743 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 8744
190f68c5 8745 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 8746 &fp, &reduced_clock,
8747 has_reduced_clock ? &fp2 : NULL);
8748
190f68c5
ACO		 8749 crtc_state->dpll_hw_state.dpll = dpll;
8750 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 8751 if (has_reduced_clock)
190f68c5 8752 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 8753 else
190f68c5 8754 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 8755
190f68c5 8756 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 8757 if (pll == NULL) {
84f44ce7 8758 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 8759 pipe_name(crtc->pipe));
4b645f14
JB		 8760 return -EINVAL;
8761 }
3fb37703 8762 }
79e53945 8763
ab585dea 8764 if (is_lvds && has_reduced_clock)
c7653199 8765 crtc->lowfreq_avail = true;
bcd644e0 8766 else
c7653199 8767 crtc->lowfreq_avail = false;
e2b78267 8768
c8f7a0db 8769 return 0;
79e53945
JB		 8770}
8771
eb14cb74
VS		 8772static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
8773 struct intel_link_m_n *m_n)
8774{
8775 struct drm_device *dev = crtc->base.dev;
8776 struct drm_i915_private *dev_priv = dev->dev_private;
8777 enum pipe pipe = crtc->pipe;
8778
8779 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
8780 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
8781 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
8782 & ~TU_SIZE_MASK;
8783 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
8784 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
8785 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8786}
8787
8788static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
8789 enum transcoder transcoder,
b95af8be
VK		 8790 struct intel_link_m_n *m_n,
8791 struct intel_link_m_n *m2_n2)
72419203
DV		 8792{
8793 struct drm_device *dev = crtc->base.dev;
8794 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 8795 enum pipe pipe = crtc->pipe;
72419203 8796
eb14cb74
VS		 8797 if (INTEL_INFO(dev)->gen >= 5) {
8798 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
8799 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
8800 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
8801 & ~TU_SIZE_MASK;
8802 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
8803 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
8804 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 8805 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
8806 * gen < 8) and if DRRS is supported (to make sure the
8807 * registers are not unnecessarily read).
8808 */
8809 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 8810 crtc->config->has_drrs) {
b95af8be
VK		 8811 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
8812 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
8813 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
8814 & ~TU_SIZE_MASK;
8815 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
8816 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
8817 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8818 }
eb14cb74
VS		 8819 } else {
8820 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
8821 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
8822 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
8823 & ~TU_SIZE_MASK;
8824 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
8825 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
8826 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
8827 }
8828}
8829
8830void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 8831 struct intel_crtc_state *pipe_config)
eb14cb74 8832{
681a8504 8833 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 8834 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
8835 else
8836 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 8837 &pipe_config->dp_m_n,
8838 &pipe_config->dp_m2_n2);
eb14cb74 8839}
72419203 8840
eb14cb74 8841static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 8842 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 8843{
8844 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 8845 &pipe_config->fdi_m_n, NULL);
72419203
DV		 8846}
8847
bd2e244f 8848static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8849 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 8850{
8851 struct drm_device *dev = crtc->base.dev;
8852 struct drm_i915_private *dev_priv = dev->dev_private;
a1b2278e
CK		 8853 struct intel_crtc_scaler_state *scaler_state = &pipe_config->scaler_state;
8854 uint32_t ps_ctrl = 0;
8855 int id = -1;
8856 int i;
bd2e244f 8857
a1b2278e
CK		 8858 /* find scaler attached to this pipe */
8859 for (i = 0; i < crtc->num_scalers; i++) {
8860 ps_ctrl = I915_READ(SKL_PS_CTRL(crtc->pipe, i));
8861 if (ps_ctrl & PS_SCALER_EN && !(ps_ctrl & PS_PLANE_SEL_MASK)) {
8862 id = i;
8863 pipe_config->pch_pfit.enabled = true;
8864 pipe_config->pch_pfit.pos = I915_READ(SKL_PS_WIN_POS(crtc->pipe, i));
8865 pipe_config->pch_pfit.size = I915_READ(SKL_PS_WIN_SZ(crtc->pipe, i));
8866 break;
8867 }
8868 }
bd2e244f 8869
a1b2278e
CK		 8870 scaler_state->scaler_id = id;
8871 if (id >= 0) {
8872 scaler_state->scaler_users |= (1 << SKL_CRTC_INDEX);
8873 } else {
8874 scaler_state->scaler_users &= ~(1 << SKL_CRTC_INDEX);
bd2e244f
JB		 8875 }
8876}
8877
5724dbd1
DL		 8878static void
8879skylake_get_initial_plane_config(struct intel_crtc *crtc,
8880 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 8881{
8882 struct drm_device *dev = crtc->base.dev;
8883 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 8884 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 8885 int pipe = crtc->pipe;
8886 int fourcc, pixel_format;
6761dd31 8887 unsigned int aligned_height;
bc8d7dff 8888 struct drm_framebuffer *fb;
1b842c89 8889 struct intel_framebuffer *intel_fb;
bc8d7dff 8890
d9806c9f 8891 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8892 if (!intel_fb) {
bc8d7dff
DL		 8893 DRM_DEBUG_KMS("failed to alloc fb\n");
8894 return;
8895 }
8896
1b842c89
DL		 8897 fb = &intel_fb->base;
8898
bc8d7dff 8899 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 8900 if (!(val & PLANE_CTL_ENABLE))
8901 goto error;
8902
bc8d7dff
DL		 8903 pixel_format = val & PLANE_CTL_FORMAT_MASK;
8904 fourcc = skl_format_to_fourcc(pixel_format,
8905 val & PLANE_CTL_ORDER_RGBX,
8906 val & PLANE_CTL_ALPHA_MASK);
8907 fb->pixel_format = fourcc;
8908 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
8909
40f46283
DL		 8910 tiling = val & PLANE_CTL_TILED_MASK;
8911 switch (tiling) {
8912 case PLANE_CTL_TILED_LINEAR:
8913 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
8914 break;
8915 case PLANE_CTL_TILED_X:
8916 plane_config->tiling = I915_TILING_X;
8917 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8918 break;
8919 case PLANE_CTL_TILED_Y:
8920 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
8921 break;
8922 case PLANE_CTL_TILED_YF:
8923 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
8924 break;
8925 default:
8926 MISSING_CASE(tiling);
8927 goto error;
8928 }
8929
bc8d7dff
DL		 8930 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
8931 plane_config->base = base;
8932
8933 offset = I915_READ(PLANE_OFFSET(pipe, 0));
8934
8935 val = I915_READ(PLANE_SIZE(pipe, 0));
8936 fb->height = ((val >> 16) & 0xfff) + 1;
8937 fb->width = ((val >> 0) & 0x1fff) + 1;
8938
8939 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 8940 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
8941 fb->pixel_format);
bc8d7dff
DL		 8942 fb->pitches[0] = (val & 0x3ff) * stride_mult;
8943
8944 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8945 fb->pixel_format,
8946 fb->modifier[0]);
bc8d7dff 8947
f37b5c2b 8948 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 8949
8950 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8951 pipe_name(pipe), fb->width, fb->height,
8952 fb->bits_per_pixel, base, fb->pitches[0],
8953 plane_config->size);
8954
2d14030b 8955 plane_config->fb = intel_fb;
bc8d7dff
DL		 8956 return;
8957
8958error:
8959 kfree(fb);
8960}
8961
2fa2fe9a 8962static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 8963 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 8964{
8965 struct drm_device *dev = crtc->base.dev;
8966 struct drm_i915_private *dev_priv = dev->dev_private;
8967 uint32_t tmp;
8968
8969 tmp = I915_READ(PF_CTL(crtc->pipe));
8970
8971 if (tmp & PF_ENABLE) {
fd4daa9c 8972 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 8973 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8974 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 8975
8976 /* We currently do not free assignements of panel fitters on
8977 * ivb/hsw (since we don't use the higher upscaling modes which
8978 * differentiates them) so just WARN about this case for now. */
8979 if (IS_GEN7(dev)) {
8980 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8981 PF_PIPE_SEL_IVB(crtc->pipe));
8982 }
2fa2fe9a 8983 }
79e53945
JB		 8984}
8985
5724dbd1
DL		 8986static void
8987ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8988 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 8989{
8990 struct drm_device *dev = crtc->base.dev;
8991 struct drm_i915_private *dev_priv = dev->dev_private;
8992 u32 val, base, offset;
aeee5a49 8993 int pipe = crtc->pipe;
4c6baa59 8994 int fourcc, pixel_format;
6761dd31 8995 unsigned int aligned_height;
b113d5ee 8996 struct drm_framebuffer *fb;
1b842c89 8997 struct intel_framebuffer *intel_fb;
4c6baa59 8998
42a7b088
DL		 8999 val = I915_READ(DSPCNTR(pipe));
9000 if (!(val & DISPLAY_PLANE_ENABLE))
9001 return;
9002
d9806c9f 9003 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 9004 if (!intel_fb) {
4c6baa59
JB		 9005 DRM_DEBUG_KMS("failed to alloc fb\n");
9006 return;
9007 }
9008
1b842c89
DL		 9009 fb = &intel_fb->base;
9010
18c5247e
DV		 9011 if (INTEL_INFO(dev)->gen >= 4) {
9012 if (val & DISPPLANE_TILED) {
49af449b 9013 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 9014 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
9015 }
9016 }
4c6baa59
JB		 9017
9018 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 9019 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 9020 fb->pixel_format = fourcc;
9021 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 9022
aeee5a49 9023 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 9024 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 9025 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 9026 } else {
49af449b 9027 if (plane_config->tiling)
aeee5a49 9028 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 9029 else
aeee5a49 9030 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 9031 }
9032 plane_config->base = base;
9033
9034 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 9035 fb->width = ((val >> 16) & 0xfff) + 1;
9036 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 9037
9038 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 9039 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 9040
b113d5ee 9041 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 9042 fb->pixel_format,
9043 fb->modifier[0]);
4c6baa59 9044
f37b5c2b 9045 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 9046
2844a921
DL		 9047 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
9048 pipe_name(pipe), fb->width, fb->height,
9049 fb->bits_per_pixel, base, fb->pitches[0],
9050 plane_config->size);
b113d5ee 9051
2d14030b 9052 plane_config->fb = intel_fb;
4c6baa59
JB		 9053}
9054
0e8ffe1b 9055static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9056 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9057{
9058 struct drm_device *dev = crtc->base.dev;
9059 struct drm_i915_private *dev_priv = dev->dev_private;
9060 uint32_t tmp;
9061
f458ebbc
DV		 9062 if (!intel_display_power_is_enabled(dev_priv,
9063 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 9064 return false;
9065
e143a21c 9066 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 9067 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 9068
0e8ffe1b
DV		 9069 tmp = I915_READ(PIPECONF(crtc->pipe));
9070 if (!(tmp & PIPECONF_ENABLE))
9071 return false;
9072
42571aef
VS		 9073 switch (tmp & PIPECONF_BPC_MASK) {
9074 case PIPECONF_6BPC:
9075 pipe_config->pipe_bpp = 18;
9076 break;
9077 case PIPECONF_8BPC:
9078 pipe_config->pipe_bpp = 24;
9079 break;
9080 case PIPECONF_10BPC:
9081 pipe_config->pipe_bpp = 30;
9082 break;
9083 case PIPECONF_12BPC:
9084 pipe_config->pipe_bpp = 36;
9085 break;
9086 default:
9087 break;
9088 }
9089
b5a9fa09
DV		 9090 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
9091 pipe_config->limited_color_range = true;
9092
ab9412ba 9093 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 9094 struct intel_shared_dpll *pll;
9095
88adfff1
DV		 9096 pipe_config->has_pch_encoder = true;
9097
627eb5a3
DV		 9098 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
9099 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9100 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 9101
9102 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 9103
c0d43d62 9104 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 9105 pipe_config->shared_dpll =
9106 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 9107 } else {
9108 tmp = I915_READ(PCH_DPLL_SEL);
9109 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
9110 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
9111 else
9112 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
9113 }
66e985c0
DV		 9114
9115 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9116
9117 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9118 &pipe_config->dpll_hw_state));
c93f54cf
DV		 9119
9120 tmp = pipe_config->dpll_hw_state.dpll;
9121 pipe_config->pixel_multiplier =
9122 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
9123 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 9124
9125 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 9126 } else {
9127 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 9128 }
9129
1bd1bd80
DV		 9130 intel_get_pipe_timings(crtc, pipe_config);
9131
2fa2fe9a
DV		 9132 ironlake_get_pfit_config(crtc, pipe_config);
9133
0e8ffe1b
DV		 9134 return true;
9135}
9136
be256dc7
PZ		 9137static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
9138{
9139 struct drm_device *dev = dev_priv->dev;
be256dc7 9140 struct intel_crtc *crtc;
be256dc7 9141
d3fcc808 9142 for_each_intel_crtc(dev, crtc)
e2c719b7 9143 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 9144 pipe_name(crtc->pipe));
9145
e2c719b7
RC		 9146 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
9147 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
9148 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
9149 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
9150 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
9151 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 9152 "CPU PWM1 enabled\n");
c5107b87 9153 if (IS_HASWELL(dev))
e2c719b7 9154 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 9155 "CPU PWM2 enabled\n");
e2c719b7 9156 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 9157 "PCH PWM1 enabled\n");
e2c719b7 9158 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 9159 "Utility pin enabled\n");
e2c719b7 9160 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 9161
9926ada1
PZ		 9162 /*
9163 * In theory we can still leave IRQs enabled, as long as only the HPD
9164 * interrupts remain enabled. We used to check for that, but since it's
9165 * gen-specific and since we only disable LCPLL after we fully disable
9166 * the interrupts, the check below should be enough.
9167 */
e2c719b7 9168 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 9169}
9170
9ccd5aeb
PZ		 9171static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
9172{
9173 struct drm_device *dev = dev_priv->dev;
9174
9175 if (IS_HASWELL(dev))
9176 return I915_READ(D_COMP_HSW);
9177 else
9178 return I915_READ(D_COMP_BDW);
9179}
9180
3c4c9b81
PZ		 9181static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
9182{
9183 struct drm_device *dev = dev_priv->dev;
9184
9185 if (IS_HASWELL(dev)) {
9186 mutex_lock(&dev_priv->rps.hw_lock);
9187 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
9188 val))
f475dadf 9189 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 9190 mutex_unlock(&dev_priv->rps.hw_lock);
9191 } else {
9ccd5aeb
PZ		 9192 I915_WRITE(D_COMP_BDW, val);
9193 POSTING_READ(D_COMP_BDW);
3c4c9b81 9194 }
be256dc7
PZ		 9195}
9196
9197/*
9198 * This function implements pieces of two sequences from BSpec:
9199 * - Sequence for display software to disable LCPLL
9200 * - Sequence for display software to allow package C8+
9201 * The steps implemented here are just the steps that actually touch the LCPLL
9202 * register. Callers should take care of disabling all the display engine
9203 * functions, doing the mode unset, fixing interrupts, etc.
9204 */
6ff58d53
PZ		 9205static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
9206 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 9207{
9208 uint32_t val;
9209
9210 assert_can_disable_lcpll(dev_priv);
9211
9212 val = I915_READ(LCPLL_CTL);
9213
9214 if (switch_to_fclk) {
9215 val |= LCPLL_CD_SOURCE_FCLK;
9216 I915_WRITE(LCPLL_CTL, val);
9217
9218 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
9219 LCPLL_CD_SOURCE_FCLK_DONE, 1))
9220 DRM_ERROR("Switching to FCLK failed\n");
9221
9222 val = I915_READ(LCPLL_CTL);
9223 }
9224
9225 val |= LCPLL_PLL_DISABLE;
9226 I915_WRITE(LCPLL_CTL, val);
9227 POSTING_READ(LCPLL_CTL);
9228
9229 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
9230 DRM_ERROR("LCPLL still locked\n");
9231
9ccd5aeb 9232 val = hsw_read_dcomp(dev_priv);
be256dc7 9233 val |= D_COMP_COMP_DISABLE;
3c4c9b81 9234 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9235 ndelay(100);
9236
9ccd5aeb
PZ		 9237 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
9238 1))
be256dc7
PZ		 9239 DRM_ERROR("D_COMP RCOMP still in progress\n");
9240
9241 if (allow_power_down) {
9242 val = I915_READ(LCPLL_CTL);
9243 val |= LCPLL_POWER_DOWN_ALLOW;
9244 I915_WRITE(LCPLL_CTL, val);
9245 POSTING_READ(LCPLL_CTL);
9246 }
9247}
9248
9249/*
9250 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
9251 * source.
9252 */
6ff58d53 9253static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 9254{
9255 uint32_t val;
9256
9257 val = I915_READ(LCPLL_CTL);
9258
9259 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
9260 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
9261 return;
9262
a8a8bd54
PZ		 9263 /*
9264 * Make sure we're not on PC8 state before disabling PC8, otherwise
9265 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 9266 */
59bad947 9267 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 9268
be256dc7
PZ		 9269 if (val & LCPLL_POWER_DOWN_ALLOW) {
9270 val &= ~LCPLL_POWER_DOWN_ALLOW;
9271 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 9272 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 9273 }
9274
9ccd5aeb 9275 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 9276 val |= D_COMP_COMP_FORCE;
9277 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 9278 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 9279
9280 val = I915_READ(LCPLL_CTL);
9281 val &= ~LCPLL_PLL_DISABLE;
9282 I915_WRITE(LCPLL_CTL, val);
9283
9284 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
9285 DRM_ERROR("LCPLL not locked yet\n");
9286
9287 if (val & LCPLL_CD_SOURCE_FCLK) {
9288 val = I915_READ(LCPLL_CTL);
9289 val &= ~LCPLL_CD_SOURCE_FCLK;
9290 I915_WRITE(LCPLL_CTL, val);
9291
9292 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
9293 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
9294 DRM_ERROR("Switching back to LCPLL failed\n");
9295 }
215733fa 9296
59bad947 9297 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
be256dc7
PZ		 9298}
9299
765dab67
PZ		 9300/*
9301 * Package states C8 and deeper are really deep PC states that can only be
9302 * reached when all the devices on the system allow it, so even if the graphics
9303 * device allows PC8+, it doesn't mean the system will actually get to these
9304 * states. Our driver only allows PC8+ when going into runtime PM.
9305 *
9306 * The requirements for PC8+ are that all the outputs are disabled, the power
9307 * well is disabled and most interrupts are disabled, and these are also
9308 * requirements for runtime PM. When these conditions are met, we manually do
9309 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
9310 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
9311 * hang the machine.
9312 *
9313 * When we really reach PC8 or deeper states (not just when we allow it) we lose
9314 * the state of some registers, so when we come back from PC8+ we need to
9315 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
9316 * need to take care of the registers kept by RC6. Notice that this happens even
9317 * if we don't put the device in PCI D3 state (which is what currently happens
9318 * because of the runtime PM support).
9319 *
9320 * For more, read "Display Sequences for Package C8" on the hardware
9321 * documentation.
9322 */
a14cb6fc 9323void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 9324{
c67a470b
PZ		 9325 struct drm_device *dev = dev_priv->dev;
9326 uint32_t val;
9327
c67a470b
PZ		 9328 DRM_DEBUG_KMS("Enabling package C8+\n");
9329
c67a470b
PZ		 9330 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9331 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9332 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
9333 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9334 }
9335
9336 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 9337 hsw_disable_lcpll(dev_priv, true, true);
9338}
9339
a14cb6fc 9340void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 9341{
9342 struct drm_device *dev = dev_priv->dev;
9343 uint32_t val;
9344
c67a470b
PZ		 9345 DRM_DEBUG_KMS("Disabling package C8+\n");
9346
9347 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 9348 lpt_init_pch_refclk(dev);
9349
9350 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
9351 val = I915_READ(SOUTH_DSPCLK_GATE_D);
9352 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
9353 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
9354 }
9355
9356 intel_prepare_ddi(dev);
c67a470b
PZ		 9357}
9358
a821fc46 9359static void broxton_modeset_global_resources(struct drm_atomic_state *old_state)
f8437dd1 9360{
a821fc46 9361 struct drm_device *dev = old_state->dev;
f8437dd1 9362 struct drm_i915_private *dev_priv = dev->dev_private;
a821fc46 9363 int max_pixclk = intel_mode_max_pixclk(dev, NULL);
f8437dd1
VK		 9364 int req_cdclk;
9365
9366 /* see the comment in valleyview_modeset_global_resources */
9367 if (WARN_ON(max_pixclk < 0))
9368 return;
9369
9370 req_cdclk = broxton_calc_cdclk(dev_priv, max_pixclk);
9371
9372 if (req_cdclk != dev_priv->cdclk_freq)
9373 broxton_set_cdclk(dev, req_cdclk);
9374}
9375
190f68c5
ACO		 9376static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
9377 struct intel_crtc_state *crtc_state)
09b4ddf9 9378{
190f68c5 9379 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 9380 return -EINVAL;
716c2e55 9381
c7653199 9382 crtc->lowfreq_avail = false;
644cef34 9383
c8f7a0db 9384 return 0;
79e53945
JB		 9385}
9386
3760b59c
S		 9387static void bxt_get_ddi_pll(struct drm_i915_private *dev_priv,
9388 enum port port,
9389 struct intel_crtc_state *pipe_config)
9390{
9391 switch (port) {
9392 case PORT_A:
9393 pipe_config->ddi_pll_sel = SKL_DPLL0;
9394 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9395 break;
9396 case PORT_B:
9397 pipe_config->ddi_pll_sel = SKL_DPLL1;
9398 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9399 break;
9400 case PORT_C:
9401 pipe_config->ddi_pll_sel = SKL_DPLL2;
9402 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9403 break;
9404 default:
9405 DRM_ERROR("Incorrect port type\n");
9406 }
9407}
9408
96b7dfb7
S		 9409static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
9410 enum port port,
5cec258b 9411 struct intel_crtc_state *pipe_config)
96b7dfb7 9412{
3148ade7 9413 u32 temp, dpll_ctl1;
96b7dfb7
S		 9414
9415 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
9416 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
9417
9418 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 9419 case SKL_DPLL0:
9420 /*
9421 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
9422 * of the shared DPLL framework and thus needs to be read out
9423 * separately
9424 */
9425 dpll_ctl1 = I915_READ(DPLL_CTRL1);
9426 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
9427 break;
96b7dfb7
S		 9428 case SKL_DPLL1:
9429 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
9430 break;
9431 case SKL_DPLL2:
9432 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
9433 break;
9434 case SKL_DPLL3:
9435 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
9436 break;
96b7dfb7
S		 9437 }
9438}
9439
7d2c8175
DL		 9440static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
9441 enum port port,
5cec258b 9442 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 9443{
9444 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
9445
9446 switch (pipe_config->ddi_pll_sel) {
9447 case PORT_CLK_SEL_WRPLL1:
9448 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
9449 break;
9450 case PORT_CLK_SEL_WRPLL2:
9451 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
9452 break;
9453 }
9454}
9455
26804afd 9456static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 9457 struct intel_crtc_state *pipe_config)
26804afd
DV		 9458{
9459 struct drm_device *dev = crtc->base.dev;
9460 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 9461 struct intel_shared_dpll *pll;
26804afd
DV		 9462 enum port port;
9463 uint32_t tmp;
9464
9465 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
9466
9467 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
9468
96b7dfb7
S		 9469 if (IS_SKYLAKE(dev))
9470 skylake_get_ddi_pll(dev_priv, port, pipe_config);
3760b59c
S		 9471 else if (IS_BROXTON(dev))
9472 bxt_get_ddi_pll(dev_priv, port, pipe_config);
96b7dfb7
S		 9473 else
9474 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 9475
d452c5b6
DV		 9476 if (pipe_config->shared_dpll >= 0) {
9477 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
9478
9479 WARN_ON(!pll->get_hw_state(dev_priv, pll,
9480 &pipe_config->dpll_hw_state));
9481 }
9482
26804afd
DV		 9483 /*
9484 * Haswell has only FDI/PCH transcoder A. It is which is connected to
9485 * DDI E. So just check whether this pipe is wired to DDI E and whether
9486 * the PCH transcoder is on.
9487 */
ca370455
DL		 9488 if (INTEL_INFO(dev)->gen < 9 &&
9489 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 9490 pipe_config->has_pch_encoder = true;
9491
9492 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
9493 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
9494 FDI_DP_PORT_WIDTH_SHIFT) + 1;
9495
9496 ironlake_get_fdi_m_n_config(crtc, pipe_config);
9497 }
9498}
9499
0e8ffe1b 9500static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 9501 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 9502{
9503 struct drm_device *dev = crtc->base.dev;
9504 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 9505 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 9506 uint32_t tmp;
9507
f458ebbc 9508 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 9509 POWER_DOMAIN_PIPE(crtc->pipe)))
9510 return false;
9511
e143a21c 9512 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 9513 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
9514
eccb140b
DV		 9515 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
9516 if (tmp & TRANS_DDI_FUNC_ENABLE) {
9517 enum pipe trans_edp_pipe;
9518 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
9519 default:
9520 WARN(1, "unknown pipe linked to edp transcoder\n");
9521 case TRANS_DDI_EDP_INPUT_A_ONOFF:
9522 case TRANS_DDI_EDP_INPUT_A_ON:
9523 trans_edp_pipe = PIPE_A;
9524 break;
9525 case TRANS_DDI_EDP_INPUT_B_ONOFF:
9526 trans_edp_pipe = PIPE_B;
9527 break;
9528 case TRANS_DDI_EDP_INPUT_C_ONOFF:
9529 trans_edp_pipe = PIPE_C;
9530 break;
9531 }
9532
9533 if (trans_edp_pipe == crtc->pipe)
9534 pipe_config->cpu_transcoder = TRANSCODER_EDP;
9535 }
9536
f458ebbc 9537 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 9538 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 9539 return false;
9540
eccb140b 9541 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 9542 if (!(tmp & PIPECONF_ENABLE))
9543 return false;
9544
26804afd 9545 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 9546
1bd1bd80
DV		 9547 intel_get_pipe_timings(crtc, pipe_config);
9548
a1b2278e
CK		 9549 if (INTEL_INFO(dev)->gen >= 9) {
9550 skl_init_scalers(dev, crtc, pipe_config);
9551 }
9552
2fa2fe9a 9553 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
af99ceda
CK		 9554
9555 if (INTEL_INFO(dev)->gen >= 9) {
9556 pipe_config->scaler_state.scaler_id = -1;
9557 pipe_config->scaler_state.scaler_users &= ~(1 << SKL_CRTC_INDEX);
9558 }
9559
bd2e244f 9560 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
ff6d9f55 9561 if (INTEL_INFO(dev)->gen == 9)
bd2e244f 9562 skylake_get_pfit_config(crtc, pipe_config);
ff6d9f55 9563 else if (INTEL_INFO(dev)->gen < 9)
bd2e244f 9564 ironlake_get_pfit_config(crtc, pipe_config);
ff6d9f55
JB		 9565 else
9566 MISSING_CASE(INTEL_INFO(dev)->gen);
bd2e244f 9567 }
88adfff1 9568
e59150dc
JB		 9569 if (IS_HASWELL(dev))
9570 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
9571 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 9572
ebb69c95
CT		 9573 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
9574 pipe_config->pixel_multiplier =
9575 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
9576 } else {
9577 pipe_config->pixel_multiplier = 1;
9578 }
6c49f241 9579
0e8ffe1b
DV		 9580 return true;
9581}
9582
560b85bb
CW		 9583static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
9584{
9585 struct drm_device *dev = crtc->dev;
9586 struct drm_i915_private *dev_priv = dev->dev_private;
9587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 9588 uint32_t cntl = 0, size = 0;
560b85bb 9589
dc41c154 9590 if (base) {
3dd512fb
MR		 9591 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
9592 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 9593 unsigned int stride = roundup_pow_of_two(width) * 4;
9594
9595 switch (stride) {
9596 default:
9597 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
9598 width, stride);
9599 stride = 256;
9600 /* fallthrough */
9601 case 256:
9602 case 512:
9603 case 1024:
9604 case 2048:
9605 break;
4b0e333e
CW		 9606 }
9607
dc41c154
VS		 9608 cntl |= CURSOR_ENABLE |
9609 CURSOR_GAMMA_ENABLE |
9610 CURSOR_FORMAT_ARGB |
9611 CURSOR_STRIDE(stride);
9612
9613 size = (height << 12) | width;
4b0e333e 9614 }
560b85bb 9615
dc41c154
VS		 9616 if (intel_crtc->cursor_cntl != 0 &&
9617 (intel_crtc->cursor_base != base ||
9618 intel_crtc->cursor_size != size ||
9619 intel_crtc->cursor_cntl != cntl)) {
9620 /* On these chipsets we can only modify the base/size/stride
9621 * whilst the cursor is disabled.
9622 */
9623 I915_WRITE(_CURACNTR, 0);
4b0e333e 9624 POSTING_READ(_CURACNTR);
dc41c154 9625 intel_crtc->cursor_cntl = 0;
4b0e333e 9626 }
560b85bb 9627
99d1f387 9628 if (intel_crtc->cursor_base != base) {
9db4a9c7 9629 I915_WRITE(_CURABASE, base);
99d1f387
VS		 9630 intel_crtc->cursor_base = base;
9631 }
4726e0b0 9632
dc41c154
VS		 9633 if (intel_crtc->cursor_size != size) {
9634 I915_WRITE(CURSIZE, size);
9635 intel_crtc->cursor_size = size;
4b0e333e 9636 }
560b85bb 9637
4b0e333e 9638 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 9639 I915_WRITE(_CURACNTR, cntl);
9640 POSTING_READ(_CURACNTR);
4b0e333e 9641 intel_crtc->cursor_cntl = cntl;
560b85bb 9642 }
560b85bb
CW		 9643}
9644
560b85bb 9645static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 9646{
9647 struct drm_device *dev = crtc->dev;
9648 struct drm_i915_private *dev_priv = dev->dev_private;
9649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9650 int pipe = intel_crtc->pipe;
4b0e333e
CW		 9651 uint32_t cntl;
9652
9653 cntl = 0;
9654 if (base) {
9655 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 9656 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 9657 case 64:
9658 cntl |= CURSOR_MODE_64_ARGB_AX;
9659 break;
9660 case 128:
9661 cntl |= CURSOR_MODE_128_ARGB_AX;
9662 break;
9663 case 256:
9664 cntl |= CURSOR_MODE_256_ARGB_AX;
9665 break;
9666 default:
3dd512fb 9667 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 9668 return;
65a21cd6 9669 }
4b0e333e 9670 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 9671
9672 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
9673 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 9674 }
65a21cd6 9675
8e7d688b 9676 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 9677 cntl |= CURSOR_ROTATE_180;
9678
4b0e333e
CW		 9679 if (intel_crtc->cursor_cntl != cntl) {
9680 I915_WRITE(CURCNTR(pipe), cntl);
9681 POSTING_READ(CURCNTR(pipe));
9682 intel_crtc->cursor_cntl = cntl;
65a21cd6 9683 }
4b0e333e 9684
65a21cd6 9685 /* and commit changes on next vblank */
5efb3e28
VS		 9686 I915_WRITE(CURBASE(pipe), base);
9687 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 9688
9689 intel_crtc->cursor_base = base;
65a21cd6
JB		 9690}
9691
cda4b7d3 9692/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 9693static void intel_crtc_update_cursor(struct drm_crtc *crtc,
9694 bool on)
cda4b7d3
CW		 9695{
9696 struct drm_device *dev = crtc->dev;
9697 struct drm_i915_private *dev_priv = dev->dev_private;
9698 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9699 int pipe = intel_crtc->pipe;
3d7d6510
MR		 9700 int x = crtc->cursor_x;
9701 int y = crtc->cursor_y;
d6e4db15 9702 u32 base = 0, pos = 0;
cda4b7d3 9703
d6e4db15 9704 if (on)
cda4b7d3 9705 base = intel_crtc->cursor_addr;
cda4b7d3 9706
6e3c9717 9707 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 9708 base = 0;
9709
6e3c9717 9710 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 9711 base = 0;
9712
9713 if (x < 0) {
3dd512fb 9714 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 9715 base = 0;
9716
9717 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
9718 x = -x;
9719 }
9720 pos |= x << CURSOR_X_SHIFT;
9721
9722 if (y < 0) {
3dd512fb 9723 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 9724 base = 0;
9725
9726 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
9727 y = -y;
9728 }
9729 pos |= y << CURSOR_Y_SHIFT;
9730
4b0e333e 9731 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 9732 return;
9733
5efb3e28
VS		 9734 I915_WRITE(CURPOS(pipe), pos);
9735
4398ad45
VS		 9736 /* ILK+ do this automagically */
9737 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 9738 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 9739 base += (intel_crtc->base.cursor->state->crtc_h *
9740 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 9741 }
9742
8ac54669 9743 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 9744 i845_update_cursor(crtc, base);
9745 else
9746 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 9747}
9748
dc41c154
VS		 9749static bool cursor_size_ok(struct drm_device *dev,
9750 uint32_t width, uint32_t height)
9751{
9752 if (width == 0 || height == 0)
9753 return false;
9754
9755 /*
9756 * 845g/865g are special in that they are only limited by
9757 * the width of their cursors, the height is arbitrary up to
9758 * the precision of the register. Everything else requires
9759 * square cursors, limited to a few power-of-two sizes.
9760 */
9761 if (IS_845G(dev) || IS_I865G(dev)) {
9762 if ((width & 63) != 0)
9763 return false;
9764
9765 if (width > (IS_845G(dev) ? 64 : 512))
9766 return false;
9767
9768 if (height > 1023)
9769 return false;
9770 } else {
9771 switch (width | height) {
9772 case 256:
9773 case 128:
9774 if (IS_GEN2(dev))
9775 return false;
9776 case 64:
9777 break;
9778 default:
9779 return false;
9780 }
9781 }
9782
9783 return true;
9784}
9785
79e53945 9786static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 9787 u16 *blue, uint32_t start, uint32_t size)
79e53945 9788{
7203425a 9789 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 9790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 9791
7203425a 9792 for (i = start; i < end; i++) {
79e53945
JB		 9793 intel_crtc->lut_r[i] = red[i] >> 8;
9794 intel_crtc->lut_g[i] = green[i] >> 8;
9795 intel_crtc->lut_b[i] = blue[i] >> 8;
9796 }
9797
9798 intel_crtc_load_lut(crtc);
9799}
9800
79e53945
JB		 9801/* VESA 640x480x72Hz mode to set on the pipe */
9802static struct drm_display_mode load_detect_mode = {
9803 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
9804 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
9805};
9806
a8bb6818
DV		 9807struct drm_framebuffer *
9808__intel_framebuffer_create(struct drm_device *dev,
9809 struct drm_mode_fb_cmd2 *mode_cmd,
9810 struct drm_i915_gem_object *obj)
d2dff872
CW		 9811{
9812 struct intel_framebuffer *intel_fb;
9813 int ret;
9814
9815 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
9816 if (!intel_fb) {
6ccb81f2 9817 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 9818 return ERR_PTR(-ENOMEM);
9819 }
9820
9821 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 9822 if (ret)
9823 goto err;
d2dff872
CW		 9824
9825 return &intel_fb->base;
dd4916c5 9826err:
6ccb81f2 9827 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 9828 kfree(intel_fb);
9829
9830 return ERR_PTR(ret);
d2dff872
CW		 9831}
9832
b5ea642a 9833static struct drm_framebuffer *
a8bb6818
DV		 9834intel_framebuffer_create(struct drm_device *dev,
9835 struct drm_mode_fb_cmd2 *mode_cmd,
9836 struct drm_i915_gem_object *obj)
9837{
9838 struct drm_framebuffer *fb;
9839 int ret;
9840
9841 ret = i915_mutex_lock_interruptible(dev);
9842 if (ret)
9843 return ERR_PTR(ret);
9844 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
9845 mutex_unlock(&dev->struct_mutex);
9846
9847 return fb;
9848}
9849
d2dff872
CW		 9850static u32
9851intel_framebuffer_pitch_for_width(int width, int bpp)
9852{
9853 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
9854 return ALIGN(pitch, 64);
9855}
9856
9857static u32
9858intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
9859{
9860 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 9861 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 9862}
9863
9864static struct drm_framebuffer *
9865intel_framebuffer_create_for_mode(struct drm_device *dev,
9866 struct drm_display_mode *mode,
9867 int depth, int bpp)
9868{
9869 struct drm_i915_gem_object *obj;
0fed39bd 9870 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 9871
9872 obj = i915_gem_alloc_object(dev,
9873 intel_framebuffer_size_for_mode(mode, bpp));
9874 if (obj == NULL)
9875 return ERR_PTR(-ENOMEM);
9876
9877 mode_cmd.width = mode->hdisplay;
9878 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 9879 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
9880 bpp);
5ca0c34a 9881 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 9882
9883 return intel_framebuffer_create(dev, &mode_cmd, obj);
9884}
9885
9886static struct drm_framebuffer *
9887mode_fits_in_fbdev(struct drm_device *dev,
9888 struct drm_display_mode *mode)
9889{
4520f53a 9890#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 9891 struct drm_i915_private *dev_priv = dev->dev_private;
9892 struct drm_i915_gem_object *obj;
9893 struct drm_framebuffer *fb;
9894
4c0e5528 9895 if (!dev_priv->fbdev)
d2dff872
CW		 9896 return NULL;
9897
4c0e5528 9898 if (!dev_priv->fbdev->fb)
d2dff872
CW		 9899 return NULL;
9900
4c0e5528
DV		 9901 obj = dev_priv->fbdev->fb->obj;
9902 BUG_ON(!obj);
9903
8bcd4553 9904 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 9905 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
9906 fb->bits_per_pixel))
d2dff872
CW		 9907 return NULL;
9908
01f2c773 9909 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 9910 return NULL;
9911
9912 return fb;
4520f53a
DV		 9913#else
9914 return NULL;
9915#endif
d2dff872
CW		 9916}
9917
d3a40d1b
ACO		 9918static int intel_modeset_setup_plane_state(struct drm_atomic_state *state,
9919 struct drm_crtc *crtc,
9920 struct drm_display_mode *mode,
9921 struct drm_framebuffer *fb,
9922 int x, int y)
9923{
9924 struct drm_plane_state *plane_state;
9925 int hdisplay, vdisplay;
9926 int ret;
9927
9928 plane_state = drm_atomic_get_plane_state(state, crtc->primary);
9929 if (IS_ERR(plane_state))
9930 return PTR_ERR(plane_state);
9931
9932 if (mode)
9933 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
9934 else
9935 hdisplay = vdisplay = 0;
9936
9937 ret = drm_atomic_set_crtc_for_plane(plane_state, fb ? crtc : NULL);
9938 if (ret)
9939 return ret;
9940 drm_atomic_set_fb_for_plane(plane_state, fb);
9941 plane_state->crtc_x = 0;
9942 plane_state->crtc_y = 0;
9943 plane_state->crtc_w = hdisplay;
9944 plane_state->crtc_h = vdisplay;
9945 plane_state->src_x = x << 16;
9946 plane_state->src_y = y << 16;
9947 plane_state->src_w = hdisplay << 16;
9948 plane_state->src_h = vdisplay << 16;
9949
9950 return 0;
9951}
9952
d2434ab7 9953bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 9954 struct drm_display_mode *mode,
51fd371b
RC		 9955 struct intel_load_detect_pipe *old,
9956 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 9957{
9958 struct intel_crtc *intel_crtc;
d2434ab7
DV		 9959 struct intel_encoder *intel_encoder =
9960 intel_attached_encoder(connector);
79e53945 9961 struct drm_crtc *possible_crtc;
4ef69c7a 9962 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 9963 struct drm_crtc *crtc = NULL;
9964 struct drm_device *dev = encoder->dev;
94352cf9 9965 struct drm_framebuffer *fb;
51fd371b 9966 struct drm_mode_config *config = &dev->mode_config;
83a57153 9967 struct drm_atomic_state *state = NULL;
944b0c76 9968 struct drm_connector_state *connector_state;
4be07317 9969 struct intel_crtc_state *crtc_state;
51fd371b 9970 int ret, i = -1;
79e53945 9971
d2dff872 9972 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9973 connector->base.id, connector->name,
8e329a03 9974 encoder->base.id, encoder->name);
d2dff872 9975
51fd371b
RC		 9976retry:
9977 ret = drm_modeset_lock(&config->connection_mutex, ctx);
9978 if (ret)
9979 goto fail_unlock;
6e9f798d 9980
79e53945
JB		 9981 /*
9982 * Algorithm gets a little messy:
7a5e4805 9983 *
79e53945
JB		 9984 * - if the connector already has an assigned crtc, use it (but make
9985 * sure it's on first)
7a5e4805 9986 *
79e53945
JB		 9987 * - try to find the first unused crtc that can drive this connector,
9988 * and use that if we find one
79e53945
JB		 9989 */
9990
9991 /* See if we already have a CRTC for this connector */
9992 if (encoder->crtc) {
9993 crtc = encoder->crtc;
8261b191 9994
51fd371b 9995 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 9996 if (ret)
9997 goto fail_unlock;
9998 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 9999 if (ret)
10000 goto fail_unlock;
7b24056b 10001
24218aac 10002 old->dpms_mode = connector->dpms;
8261b191
CW		 10003 old->load_detect_temp = false;
10004
10005 /* Make sure the crtc and connector are running */
24218aac
DV		 10006 if (connector->dpms != DRM_MODE_DPMS_ON)
10007 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 10008
7173188d 10009 return true;
79e53945
JB		 10010 }
10011
10012 /* Find an unused one (if possible) */
70e1e0ec 10013 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 10014 i++;
10015 if (!(encoder->possible_crtcs & (1 << i)))
10016 continue;
83d65738 10017 if (possible_crtc->state->enable)
a459249c
VS		 10018 continue;
10019 /* This can occur when applying the pipe A quirk on resume. */
10020 if (to_intel_crtc(possible_crtc)->new_enabled)
10021 continue;
10022
10023 crtc = possible_crtc;
10024 break;
79e53945
JB		 10025 }
10026
10027 /*
10028 * If we didn't find an unused CRTC, don't use any.
10029 */
10030 if (!crtc) {
7173188d 10031 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 10032 goto fail_unlock;
79e53945
JB		 10033 }
10034
51fd371b
RC		 10035 ret = drm_modeset_lock(&crtc->mutex, ctx);
10036 if (ret)
4d02e2de
DV		 10037 goto fail_unlock;
10038 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
10039 if (ret)
51fd371b 10040 goto fail_unlock;
fc303101
DV		 10041 intel_encoder->new_crtc = to_intel_crtc(crtc);
10042 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 10043
10044 intel_crtc = to_intel_crtc(crtc);
412b61d8 10045 intel_crtc->new_enabled = true;
24218aac 10046 old->dpms_mode = connector->dpms;
8261b191 10047 old->load_detect_temp = true;
d2dff872 10048 old->release_fb = NULL;
79e53945 10049
83a57153
ACO		 10050 state = drm_atomic_state_alloc(dev);
10051 if (!state)
10052 return false;
10053
10054 state->acquire_ctx = ctx;
10055
944b0c76
ACO		 10056 connector_state = drm_atomic_get_connector_state(state, connector);
10057 if (IS_ERR(connector_state)) {
10058 ret = PTR_ERR(connector_state);
10059 goto fail;
10060 }
10061
10062 connector_state->crtc = crtc;
10063 connector_state->best_encoder = &intel_encoder->base;
10064
4be07317
ACO		 10065 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10066 if (IS_ERR(crtc_state)) {
10067 ret = PTR_ERR(crtc_state);
10068 goto fail;
10069 }
10070
49d6fa21 10071 crtc_state->base.active = crtc_state->base.enable = true;
4be07317 10072
6492711d
CW		 10073 if (!mode)
10074 mode = &load_detect_mode;
79e53945 10075
d2dff872
CW		 10076 /* We need a framebuffer large enough to accommodate all accesses
10077 * that the plane may generate whilst we perform load detection.
10078 * We can not rely on the fbcon either being present (we get called
10079 * during its initialisation to detect all boot displays, or it may
10080 * not even exist) or that it is large enough to satisfy the
10081 * requested mode.
10082 */
94352cf9
DV		 10083 fb = mode_fits_in_fbdev(dev, mode);
10084 if (fb == NULL) {
d2dff872 10085 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 10086 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
10087 old->release_fb = fb;
d2dff872
CW		 10088 } else
10089 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 10090 if (IS_ERR(fb)) {
d2dff872 10091 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 10092 goto fail;
79e53945 10093 }
79e53945 10094
d3a40d1b
ACO		 10095 ret = intel_modeset_setup_plane_state(state, crtc, mode, fb, 0, 0);
10096 if (ret)
10097 goto fail;
10098
8c7b5ccb
ACO		 10099 drm_mode_copy(&crtc_state->base.mode, mode);
10100
10101 if (intel_set_mode(crtc, state)) {
6492711d 10102 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 10103 if (old->release_fb)
10104 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 10105 goto fail;
79e53945 10106 }
9128b040 10107 crtc->primary->crtc = crtc;
7173188d 10108
79e53945 10109 /* let the connector get through one full cycle before testing */
9d0498a2 10110 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 10111 return true;
412b61d8
VS		 10112
10113 fail:
83d65738 10114 intel_crtc->new_enabled = crtc->state->enable;
51fd371b 10115fail_unlock:
e5d958ef
ACO		 10116 drm_atomic_state_free(state);
10117 state = NULL;
83a57153 10118
51fd371b
RC		 10119 if (ret == -EDEADLK) {
10120 drm_modeset_backoff(ctx);
10121 goto retry;
10122 }
10123
412b61d8 10124 return false;
79e53945
JB		 10125}
10126
d2434ab7 10127void intel_release_load_detect_pipe(struct drm_connector *connector,
49172fee
ACO		 10128 struct intel_load_detect_pipe *old,
10129 struct drm_modeset_acquire_ctx *ctx)
79e53945 10130{
83a57153 10131 struct drm_device *dev = connector->dev;
d2434ab7
DV		 10132 struct intel_encoder *intel_encoder =
10133 intel_attached_encoder(connector);
4ef69c7a 10134 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 10135 struct drm_crtc *crtc = encoder->crtc;
412b61d8 10136 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83a57153 10137 struct drm_atomic_state *state;
944b0c76 10138 struct drm_connector_state *connector_state;
4be07317 10139 struct intel_crtc_state *crtc_state;
d3a40d1b 10140 int ret;
79e53945 10141
d2dff872 10142 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 10143 connector->base.id, connector->name,
8e329a03 10144 encoder->base.id, encoder->name);
d2dff872 10145
8261b191 10146 if (old->load_detect_temp) {
83a57153 10147 state = drm_atomic_state_alloc(dev);
944b0c76
ACO		 10148 if (!state)
10149 goto fail;
83a57153
ACO		 10150
10151 state->acquire_ctx = ctx;
10152
944b0c76
ACO		 10153 connector_state = drm_atomic_get_connector_state(state, connector);
10154 if (IS_ERR(connector_state))
10155 goto fail;
10156
4be07317
ACO		 10157 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
10158 if (IS_ERR(crtc_state))
10159 goto fail;
10160
fc303101
DV		 10161 to_intel_connector(connector)->new_encoder = NULL;
10162 intel_encoder->new_crtc = NULL;
412b61d8 10163 intel_crtc->new_enabled = false;
944b0c76
ACO		 10164
10165 connector_state->best_encoder = NULL;
10166 connector_state->crtc = NULL;
10167
49d6fa21 10168 crtc_state->base.enable = crtc_state->base.active = false;
4be07317 10169
d3a40d1b
ACO		 10170 ret = intel_modeset_setup_plane_state(state, crtc, NULL, NULL,
10171 0, 0);
10172 if (ret)
10173 goto fail;
10174
2bfb4627
ACO		 10175 ret = intel_set_mode(crtc, state);
10176 if (ret)
10177 goto fail;
d2dff872 10178
36206361
DV		 10179 if (old->release_fb) {
10180 drm_framebuffer_unregister_private(old->release_fb);
10181 drm_framebuffer_unreference(old->release_fb);
10182 }
d2dff872 10183
0622a53c 10184 return;
79e53945
JB		 10185 }
10186
c751ce4f 10187 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 10188 if (old->dpms_mode != DRM_MODE_DPMS_ON)
10189 connector->funcs->dpms(connector, old->dpms_mode);
944b0c76
ACO		 10190
10191 return;
10192fail:
10193 DRM_DEBUG_KMS("Couldn't release load detect pipe.\n");
10194 drm_atomic_state_free(state);
79e53945
JB		 10195}
10196
da4a1efa 10197static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 10198 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 10199{
10200 struct drm_i915_private *dev_priv = dev->dev_private;
10201 u32 dpll = pipe_config->dpll_hw_state.dpll;
10202
10203 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 10204 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 10205 else if (HAS_PCH_SPLIT(dev))
10206 return 120000;
10207 else if (!IS_GEN2(dev))
10208 return 96000;
10209 else
10210 return 48000;
10211}
10212
79e53945 10213/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 10214static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 10215 struct intel_crtc_state *pipe_config)
79e53945 10216{
f1f644dc 10217 struct drm_device *dev = crtc->base.dev;
79e53945 10218 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 10219 int pipe = pipe_config->cpu_transcoder;
293623f7 10220 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 10221 u32 fp;
10222 intel_clock_t clock;
da4a1efa 10223 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 10224
10225 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 10226 fp = pipe_config->dpll_hw_state.fp0;
79e53945 10227 else
293623f7 10228 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 10229
10230 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 10231 if (IS_PINEVIEW(dev)) {
10232 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
10233 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 10234 } else {
10235 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
10236 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
10237 }
10238
a6c45cf0 10239 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 10240 if (IS_PINEVIEW(dev))
10241 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
10242 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 10243 else
10244 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 10245 DPLL_FPA01_P1_POST_DIV_SHIFT);
10246
10247 switch (dpll & DPLL_MODE_MASK) {
10248 case DPLLB_MODE_DAC_SERIAL:
10249 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
10250 5 : 10;
10251 break;
10252 case DPLLB_MODE_LVDS:
10253 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
10254 7 : 14;
10255 break;
10256 default:
28c97730 10257 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 10258 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 10259 return;
79e53945
JB		 10260 }
10261
ac58c3f0 10262 if (IS_PINEVIEW(dev))
da4a1efa 10263 pineview_clock(refclk, &clock);
ac58c3f0 10264 else
da4a1efa 10265 i9xx_clock(refclk, &clock);
79e53945 10266 } else {
0fb58223 10267 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 10268 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 10269
10270 if (is_lvds) {
10271 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
10272 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 10273
10274 if (lvds & LVDS_CLKB_POWER_UP)
10275 clock.p2 = 7;
10276 else
10277 clock.p2 = 14;
79e53945
JB		 10278 } else {
10279 if (dpll & PLL_P1_DIVIDE_BY_TWO)
10280 clock.p1 = 2;
10281 else {
10282 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
10283 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
10284 }
10285 if (dpll & PLL_P2_DIVIDE_BY_4)
10286 clock.p2 = 4;
10287 else
10288 clock.p2 = 2;
79e53945 10289 }
da4a1efa
VS		 10290
10291 i9xx_clock(refclk, &clock);
79e53945
JB		 10292 }
10293
18442d08
VS		 10294 /*
10295 * This value includes pixel_multiplier. We will use
241bfc38 10296 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 10297 * encoder's get_config() function.
10298 */
10299 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 10300}
10301
6878da05
VS		 10302int intel_dotclock_calculate(int link_freq,
10303 const struct intel_link_m_n *m_n)
f1f644dc 10304{
f1f644dc
JB		 10305 /*
10306 * The calculation for the data clock is:
1041a02f 10307 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 10308 * But we want to avoid losing precison if possible, so:
1041a02f 10309 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 10310 *
10311 * and the link clock is simpler:
1041a02f 10312 * link_clock = (m * link_clock) / n
f1f644dc
JB		 10313 */
10314
6878da05
VS		 10315 if (!m_n->link_n)
10316 return 0;
f1f644dc 10317
6878da05
VS		 10318 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
10319}
f1f644dc 10320
18442d08 10321static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 10322 struct intel_crtc_state *pipe_config)
6878da05
VS		 10323{
10324 struct drm_device *dev = crtc->base.dev;
79e53945 10325
18442d08
VS		 10326 /* read out port_clock from the DPLL */
10327 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 10328
f1f644dc 10329 /*
18442d08 10330 * This value does not include pixel_multiplier.
241bfc38 10331 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 10332 * agree once we know their relationship in the encoder's
10333 * get_config() function.
79e53945 10334 */
2d112de7 10335 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 10336 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
10337 &pipe_config->fdi_m_n);
79e53945
JB		 10338}
10339
10340/** Returns the currently programmed mode of the given pipe. */
10341struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
10342 struct drm_crtc *crtc)
10343{
548f245b 10344 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 10345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 10346 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 10347 struct drm_display_mode *mode;
5cec258b 10348 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 10349 int htot = I915_READ(HTOTAL(cpu_transcoder));
10350 int hsync = I915_READ(HSYNC(cpu_transcoder));
10351 int vtot = I915_READ(VTOTAL(cpu_transcoder));
10352 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 10353 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 10354
10355 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
10356 if (!mode)
10357 return NULL;
10358
f1f644dc
JB		 10359 /*
10360 * Construct a pipe_config sufficient for getting the clock info
10361 * back out of crtc_clock_get.
10362 *
10363 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
10364 * to use a real value here instead.
10365 */
293623f7 10366 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 10367 pipe_config.pixel_multiplier = 1;
293623f7
VS		 10368 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
10369 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
10370 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 10371 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
10372
773ae034 10373 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 10374 mode->hdisplay = (htot & 0xffff) + 1;
10375 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
10376 mode->hsync_start = (hsync & 0xffff) + 1;
10377 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
10378 mode->vdisplay = (vtot & 0xffff) + 1;
10379 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
10380 mode->vsync_start = (vsync & 0xffff) + 1;
10381 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
10382
10383 drm_mode_set_name(mode);
79e53945
JB		 10384
10385 return mode;
10386}
10387
652c393a
JB		 10388static void intel_decrease_pllclock(struct drm_crtc *crtc)
10389{
10390 struct drm_device *dev = crtc->dev;
fbee40df 10391 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 10393
baff296c 10394 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 10395 return;
10396
10397 if (!dev_priv->lvds_downclock_avail)
10398 return;
10399
10400 /*
10401 * Since this is called by a timer, we should never get here in
10402 * the manual case.
10403 */
10404 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 10405 int pipe = intel_crtc->pipe;
10406 int dpll_reg = DPLL(pipe);
10407 int dpll;
f6e5b160 10408
44d98a61 10409 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 10410
8ac5a6d5 10411 assert_panel_unlocked(dev_priv, pipe);
652c393a 10412
dc257cf1 10413 dpll = I915_READ(dpll_reg);
652c393a
JB		 10414 dpll |= DISPLAY_RATE_SELECT_FPA1;
10415 I915_WRITE(dpll_reg, dpll);
9d0498a2 10416 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 10417 dpll = I915_READ(dpll_reg);
10418 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 10419 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 10420 }
10421
10422}
10423
f047e395
CW		 10424void intel_mark_busy(struct drm_device *dev)
10425{
c67a470b
PZ		 10426 struct drm_i915_private *dev_priv = dev->dev_private;
10427
f62a0076
CW		 10428 if (dev_priv->mm.busy)
10429 return;
10430
43694d69 10431 intel_runtime_pm_get(dev_priv);
c67a470b 10432 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 10433 if (INTEL_INFO(dev)->gen >= 6)
10434 gen6_rps_busy(dev_priv);
f62a0076 10435 dev_priv->mm.busy = true;
f047e395
CW		 10436}
10437
10438void intel_mark_idle(struct drm_device *dev)
652c393a 10439{
c67a470b 10440 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 10441 struct drm_crtc *crtc;
652c393a 10442
f62a0076
CW		 10443 if (!dev_priv->mm.busy)
10444 return;
10445
10446 dev_priv->mm.busy = false;
10447
70e1e0ec 10448 for_each_crtc(dev, crtc) {
f4510a27 10449 if (!crtc->primary->fb)
652c393a
JB		 10450 continue;
10451
725a5b54 10452 intel_decrease_pllclock(crtc);
652c393a 10453 }
b29c19b6 10454
3d13ef2e 10455 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 10456 gen6_rps_idle(dev->dev_private);
bb4cdd53 10457
43694d69 10458 intel_runtime_pm_put(dev_priv);
652c393a
JB		 10459}
10460
79e53945
JB		 10461static void intel_crtc_destroy(struct drm_crtc *crtc)
10462{
10463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 10464 struct drm_device *dev = crtc->dev;
10465 struct intel_unpin_work *work;
67e77c5a 10466
5e2d7afc 10467 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 10468 work = intel_crtc->unpin_work;
10469 intel_crtc->unpin_work = NULL;
5e2d7afc 10470 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 10471
10472 if (work) {
10473 cancel_work_sync(&work->work);
10474 kfree(work);
10475 }
79e53945
JB		 10476
10477 drm_crtc_cleanup(crtc);
67e77c5a 10478
79e53945
JB		 10479 kfree(intel_crtc);
10480}
10481
6b95a207
KH		 10482static void intel_unpin_work_fn(struct work_struct *__work)
10483{
10484 struct intel_unpin_work *work =
10485 container_of(__work, struct intel_unpin_work, work);
b4a98e57 10486 struct drm_device *dev = work->crtc->dev;
f99d7069 10487 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 10488
b4a98e57 10489 mutex_lock(&dev->struct_mutex);
82bc3b2d 10490 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 10491 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 10492
7ff0ebcc 10493 intel_fbc_update(dev);
f06cc1b9
JH		 10494
10495 if (work->flip_queued_req)
146d84f0 10496 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 10497 mutex_unlock(&dev->struct_mutex);
10498
f99d7069 10499 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 10500 drm_framebuffer_unreference(work->old_fb);
f99d7069 10501
b4a98e57
CW		 10502 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
10503 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
10504
6b95a207
KH		 10505 kfree(work);
10506}
10507
1afe3e9d 10508static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 10509 struct drm_crtc *crtc)
6b95a207 10510{
6b95a207
KH		 10511 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10512 struct intel_unpin_work *work;
6b95a207
KH		 10513 unsigned long flags;
10514
10515 /* Ignore early vblank irqs */
10516 if (intel_crtc == NULL)
10517 return;
10518
f326038a
DV		 10519 /*
10520 * This is called both by irq handlers and the reset code (to complete
10521 * lost pageflips) so needs the full irqsave spinlocks.
10522 */
6b95a207
KH		 10523 spin_lock_irqsave(&dev->event_lock, flags);
10524 work = intel_crtc->unpin_work;
e7d841ca
CW		 10525
10526 /* Ensure we don't miss a work->pending update ... */
10527 smp_rmb();
10528
10529 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 10530 spin_unlock_irqrestore(&dev->event_lock, flags);
10531 return;
10532 }
10533
d6bbafa1 10534 page_flip_completed(intel_crtc);
0af7e4df 10535
6b95a207 10536 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 10537}
10538
1afe3e9d
JB		 10539void intel_finish_page_flip(struct drm_device *dev, int pipe)
10540{
fbee40df 10541 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10542 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
10543
49b14a5c 10544 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10545}
10546
10547void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
10548{
fbee40df 10549 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 10550 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
10551
49b14a5c 10552 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 10553}
10554
75f7f3ec
VS		 10555/* Is 'a' after or equal to 'b'? */
10556static bool g4x_flip_count_after_eq(u32 a, u32 b)
10557{
10558 return !((a - b) & 0x80000000);
10559}
10560
10561static bool page_flip_finished(struct intel_crtc *crtc)
10562{
10563 struct drm_device *dev = crtc->base.dev;
10564 struct drm_i915_private *dev_priv = dev->dev_private;
10565
bdfa7542
VS		 10566 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
10567 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
10568 return true;
10569
75f7f3ec
VS		 10570 /*
10571 * The relevant registers doen't exist on pre-ctg.
10572 * As the flip done interrupt doesn't trigger for mmio
10573 * flips on gmch platforms, a flip count check isn't
10574 * really needed there. But since ctg has the registers,
10575 * include it in the check anyway.
10576 */
10577 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
10578 return true;
10579
10580 /*
10581 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
10582 * used the same base address. In that case the mmio flip might
10583 * have completed, but the CS hasn't even executed the flip yet.
10584 *
10585 * A flip count check isn't enough as the CS might have updated
10586 * the base address just after start of vblank, but before we
10587 * managed to process the interrupt. This means we'd complete the
10588 * CS flip too soon.
10589 *
10590 * Combining both checks should get us a good enough result. It may
10591 * still happen that the CS flip has been executed, but has not
10592 * yet actually completed. But in case the base address is the same
10593 * anyway, we don't really care.
10594 */
10595 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
10596 crtc->unpin_work->gtt_offset &&
10597 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
10598 crtc->unpin_work->flip_count);
10599}
10600
6b95a207
KH		 10601void intel_prepare_page_flip(struct drm_device *dev, int plane)
10602{
fbee40df 10603 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 10604 struct intel_crtc *intel_crtc =
10605 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
10606 unsigned long flags;
10607
f326038a
DV		 10608
10609 /*
10610 * This is called both by irq handlers and the reset code (to complete
10611 * lost pageflips) so needs the full irqsave spinlocks.
10612 *
10613 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 10614 * generate a page-flip completion irq, i.e. every modeset
10615 * is also accompanied by a spurious intel_prepare_page_flip().
10616 */
6b95a207 10617 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 10618 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 10619 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 10620 spin_unlock_irqrestore(&dev->event_lock, flags);
10621}
10622
eba905b2 10623static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 10624{
10625 /* Ensure that the work item is consistent when activating it ... */
10626 smp_wmb();
10627 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
10628 /* and that it is marked active as soon as the irq could fire. */
10629 smp_wmb();
10630}
10631
8c9f3aaf
JB		 10632static int intel_gen2_queue_flip(struct drm_device *dev,
10633 struct drm_crtc *crtc,
10634 struct drm_framebuffer *fb,
ed8d1975 10635 struct drm_i915_gem_object *obj,
a4872ba6 10636 struct intel_engine_cs *ring,
ed8d1975 10637 uint32_t flags)
8c9f3aaf 10638{
8c9f3aaf 10639 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10640 u32 flip_mask;
10641 int ret;
10642
6d90c952 10643 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10644 if (ret)
4fa62c89 10645 return ret;
8c9f3aaf
JB		 10646
10647 /* Can't queue multiple flips, so wait for the previous
10648 * one to finish before executing the next.
10649 */
10650 if (intel_crtc->plane)
10651 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10652 else
10653 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10654 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10655 intel_ring_emit(ring, MI_NOOP);
10656 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10657 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10658 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10659 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 10660 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 10661
10662 intel_mark_page_flip_active(intel_crtc);
09246732 10663 __intel_ring_advance(ring);
83d4092b 10664 return 0;
8c9f3aaf
JB		 10665}
10666
10667static int intel_gen3_queue_flip(struct drm_device *dev,
10668 struct drm_crtc *crtc,
10669 struct drm_framebuffer *fb,
ed8d1975 10670 struct drm_i915_gem_object *obj,
a4872ba6 10671 struct intel_engine_cs *ring,
ed8d1975 10672 uint32_t flags)
8c9f3aaf 10673{
8c9f3aaf 10674 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 10675 u32 flip_mask;
10676 int ret;
10677
6d90c952 10678 ret = intel_ring_begin(ring, 6);
8c9f3aaf 10679 if (ret)
4fa62c89 10680 return ret;
8c9f3aaf
JB		 10681
10682 if (intel_crtc->plane)
10683 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
10684 else
10685 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 10686 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
10687 intel_ring_emit(ring, MI_NOOP);
10688 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
10689 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10690 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10691 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 10692 intel_ring_emit(ring, MI_NOOP);
10693
e7d841ca 10694 intel_mark_page_flip_active(intel_crtc);
09246732 10695 __intel_ring_advance(ring);
83d4092b 10696 return 0;
8c9f3aaf
JB		 10697}
10698
10699static int intel_gen4_queue_flip(struct drm_device *dev,
10700 struct drm_crtc *crtc,
10701 struct drm_framebuffer *fb,
ed8d1975 10702 struct drm_i915_gem_object *obj,
a4872ba6 10703 struct intel_engine_cs *ring,
ed8d1975 10704 uint32_t flags)
8c9f3aaf
JB		 10705{
10706 struct drm_i915_private *dev_priv = dev->dev_private;
10707 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10708 uint32_t pf, pipesrc;
10709 int ret;
10710
6d90c952 10711 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10712 if (ret)
4fa62c89 10713 return ret;
8c9f3aaf
JB		 10714
10715 /* i965+ uses the linear or tiled offsets from the
10716 * Display Registers (which do not change across a page-flip)
10717 * so we need only reprogram the base address.
10718 */
6d90c952
DV		 10719 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10720 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10721 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 10722 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 10723 obj->tiling_mode);
8c9f3aaf
JB		 10724
10725 /* XXX Enabling the panel-fitter across page-flip is so far
10726 * untested on non-native modes, so ignore it for now.
10727 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
10728 */
10729 pf = 0;
10730 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10731 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10732
10733 intel_mark_page_flip_active(intel_crtc);
09246732 10734 __intel_ring_advance(ring);
83d4092b 10735 return 0;
8c9f3aaf
JB		 10736}
10737
10738static int intel_gen6_queue_flip(struct drm_device *dev,
10739 struct drm_crtc *crtc,
10740 struct drm_framebuffer *fb,
ed8d1975 10741 struct drm_i915_gem_object *obj,
a4872ba6 10742 struct intel_engine_cs *ring,
ed8d1975 10743 uint32_t flags)
8c9f3aaf
JB		 10744{
10745 struct drm_i915_private *dev_priv = dev->dev_private;
10746 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
10747 uint32_t pf, pipesrc;
10748 int ret;
10749
6d90c952 10750 ret = intel_ring_begin(ring, 4);
8c9f3aaf 10751 if (ret)
4fa62c89 10752 return ret;
8c9f3aaf 10753
6d90c952
DV		 10754 intel_ring_emit(ring, MI_DISPLAY_FLIP |
10755 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
10756 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 10757 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 10758
dc257cf1
DV		 10759 /* Contrary to the suggestions in the documentation,
10760 * "Enable Panel Fitter" does not seem to be required when page
10761 * flipping with a non-native mode, and worse causes a normal
10762 * modeset to fail.
10763 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
10764 */
10765 pf = 0;
8c9f3aaf 10766 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 10767 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 10768
10769 intel_mark_page_flip_active(intel_crtc);
09246732 10770 __intel_ring_advance(ring);
83d4092b 10771 return 0;
8c9f3aaf
JB		 10772}
10773
7c9017e5
JB		 10774static int intel_gen7_queue_flip(struct drm_device *dev,
10775 struct drm_crtc *crtc,
10776 struct drm_framebuffer *fb,
ed8d1975 10777 struct drm_i915_gem_object *obj,
a4872ba6 10778 struct intel_engine_cs *ring,
ed8d1975 10779 uint32_t flags)
7c9017e5 10780{
7c9017e5 10781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 10782 uint32_t plane_bit = 0;
ffe74d75
CW		 10783 int len, ret;
10784
eba905b2 10785 switch (intel_crtc->plane) {
cb05d8de
DV		 10786 case PLANE_A:
10787 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
10788 break;
10789 case PLANE_B:
10790 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
10791 break;
10792 case PLANE_C:
10793 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
10794 break;
10795 default:
10796 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 10797 return -ENODEV;
cb05d8de
DV		 10798 }
10799
ffe74d75 10800 len = 4;
f476828a 10801 if (ring->id == RCS) {
ffe74d75 10802 len += 6;
f476828a
DL		 10803 /*
10804 * On Gen 8, SRM is now taking an extra dword to accommodate
10805 * 48bits addresses, and we need a NOOP for the batch size to
10806 * stay even.
10807 */
10808 if (IS_GEN8(dev))
10809 len += 2;
10810 }
ffe74d75 10811
f66fab8e
VS		 10812 /*
10813 * BSpec MI_DISPLAY_FLIP for IVB:
10814 * "The full packet must be contained within the same cache line."
10815 *
10816 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
10817 * cacheline, if we ever start emitting more commands before
10818 * the MI_DISPLAY_FLIP we may need to first emit everything else,
10819 * then do the cacheline alignment, and finally emit the
10820 * MI_DISPLAY_FLIP.
10821 */
10822 ret = intel_ring_cacheline_align(ring);
10823 if (ret)
4fa62c89 10824 return ret;
f66fab8e 10825
ffe74d75 10826 ret = intel_ring_begin(ring, len);
7c9017e5 10827 if (ret)
4fa62c89 10828 return ret;
7c9017e5 10829
ffe74d75
CW		 10830 /* Unmask the flip-done completion message. Note that the bspec says that
10831 * we should do this for both the BCS and RCS, and that we must not unmask
10832 * more than one flip event at any time (or ensure that one flip message
10833 * can be sent by waiting for flip-done prior to queueing new flips).
10834 * Experimentation says that BCS works despite DERRMR masking all
10835 * flip-done completion events and that unmasking all planes at once
10836 * for the RCS also doesn't appear to drop events. Setting the DERRMR
10837 * to zero does lead to lockups within MI_DISPLAY_FLIP.
10838 */
10839 if (ring->id == RCS) {
10840 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
10841 intel_ring_emit(ring, DERRMR);
10842 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
10843 DERRMR_PIPEB_PRI_FLIP_DONE |
10844 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 10845 if (IS_GEN8(dev))
10846 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
10847 MI_SRM_LRM_GLOBAL_GTT);
10848 else
10849 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
10850 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 10851 intel_ring_emit(ring, DERRMR);
10852 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 10853 if (IS_GEN8(dev)) {
10854 intel_ring_emit(ring, 0);
10855 intel_ring_emit(ring, MI_NOOP);
10856 }
ffe74d75
CW		 10857 }
10858
cb05d8de 10859 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 10860 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 10861 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 10862 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 10863
10864 intel_mark_page_flip_active(intel_crtc);
09246732 10865 __intel_ring_advance(ring);
83d4092b 10866 return 0;
7c9017e5
JB		 10867}
10868
84c33a64
SG		 10869static bool use_mmio_flip(struct intel_engine_cs *ring,
10870 struct drm_i915_gem_object *obj)
10871{
10872 /*
10873 * This is not being used for older platforms, because
10874 * non-availability of flip done interrupt forces us to use
10875 * CS flips. Older platforms derive flip done using some clever
10876 * tricks involving the flip_pending status bits and vblank irqs.
10877 * So using MMIO flips there would disrupt this mechanism.
10878 */
10879
8e09bf83
CW		 10880 if (ring == NULL)
10881 return true;
10882
84c33a64
SG		 10883 if (INTEL_INFO(ring->dev)->gen < 5)
10884 return false;
10885
10886 if (i915.use_mmio_flip < 0)
10887 return false;
10888 else if (i915.use_mmio_flip > 0)
10889 return true;
14bf993e
OM		 10890 else if (i915.enable_execlists)
10891 return true;
84c33a64 10892 else
b4716185 10893 return ring != i915_gem_request_get_ring(obj->last_write_req);
84c33a64
SG		 10894}
10895
ff944564
DL		 10896static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
10897{
10898 struct drm_device *dev = intel_crtc->base.dev;
10899 struct drm_i915_private *dev_priv = dev->dev_private;
10900 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
ff944564
DL		 10901 const enum pipe pipe = intel_crtc->pipe;
10902 u32 ctl, stride;
10903
10904 ctl = I915_READ(PLANE_CTL(pipe, 0));
10905 ctl &= ~PLANE_CTL_TILED_MASK;
2ebef630
TU		 10906 switch (fb->modifier[0]) {
10907 case DRM_FORMAT_MOD_NONE:
10908 break;
10909 case I915_FORMAT_MOD_X_TILED:
ff944564 10910 ctl |= PLANE_CTL_TILED_X;
2ebef630
TU		 10911 break;
10912 case I915_FORMAT_MOD_Y_TILED:
10913 ctl |= PLANE_CTL_TILED_Y;
10914 break;
10915 case I915_FORMAT_MOD_Yf_TILED:
10916 ctl |= PLANE_CTL_TILED_YF;
10917 break;
10918 default:
10919 MISSING_CASE(fb->modifier[0]);
10920 }
ff944564
DL		 10921
10922 /*
10923 * The stride is either expressed as a multiple of 64 bytes chunks for
10924 * linear buffers or in number of tiles for tiled buffers.
10925 */
2ebef630
TU		 10926 stride = fb->pitches[0] /
10927 intel_fb_stride_alignment(dev, fb->modifier[0],
10928 fb->pixel_format);
ff944564
DL		 10929
10930 /*
10931 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
10932 * PLANE_SURF updates, the update is then guaranteed to be atomic.
10933 */
10934 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
10935 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
10936
10937 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
10938 POSTING_READ(PLANE_SURF(pipe, 0));
10939}
10940
10941static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 10942{
10943 struct drm_device *dev = intel_crtc->base.dev;
10944 struct drm_i915_private *dev_priv = dev->dev_private;
10945 struct intel_framebuffer *intel_fb =
10946 to_intel_framebuffer(intel_crtc->base.primary->fb);
10947 struct drm_i915_gem_object *obj = intel_fb->obj;
10948 u32 dspcntr;
10949 u32 reg;
10950
84c33a64
SG		 10951 reg = DSPCNTR(intel_crtc->plane);
10952 dspcntr = I915_READ(reg);
10953
c5d97472
DL		 10954 if (obj->tiling_mode != I915_TILING_NONE)
10955 dspcntr |= DISPPLANE_TILED;
10956 else
10957 dspcntr &= ~DISPPLANE_TILED;
10958
84c33a64
SG		 10959 I915_WRITE(reg, dspcntr);
10960
10961 I915_WRITE(DSPSURF(intel_crtc->plane),
10962 intel_crtc->unpin_work->gtt_offset);
10963 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 10964
ff944564
DL		 10965}
10966
10967/*
10968 * XXX: This is the temporary way to update the plane registers until we get
10969 * around to using the usual plane update functions for MMIO flips
10970 */
10971static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
10972{
10973 struct drm_device *dev = intel_crtc->base.dev;
10974 bool atomic_update;
10975 u32 start_vbl_count;
10976
10977 intel_mark_page_flip_active(intel_crtc);
10978
10979 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
10980
10981 if (INTEL_INFO(dev)->gen >= 9)
10982 skl_do_mmio_flip(intel_crtc);
10983 else
10984 /* use_mmio_flip() retricts MMIO flips to ilk+ */
10985 ilk_do_mmio_flip(intel_crtc);
10986
9362c7c5
ACO		 10987 if (atomic_update)
10988 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 10989}
10990
9362c7c5 10991static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 10992{
b2cfe0ab
CW		 10993 struct intel_mmio_flip *mmio_flip =
10994 container_of(work, struct intel_mmio_flip, work);
84c33a64 10995
eed29a5b
DV		 10996 if (mmio_flip->req)
10997 WARN_ON(__i915_wait_request(mmio_flip->req,
b2cfe0ab 10998 mmio_flip->crtc->reset_counter,
bcafc4e3
CW		 10999 false, NULL,
11000 &mmio_flip->i915->rps.mmioflips));
84c33a64 11001
b2cfe0ab
CW		 11002 intel_do_mmio_flip(mmio_flip->crtc);
11003
eed29a5b 11004 i915_gem_request_unreference__unlocked(mmio_flip->req);
b2cfe0ab 11005 kfree(mmio_flip);
84c33a64
SG		 11006}
11007
11008static int intel_queue_mmio_flip(struct drm_device *dev,
11009 struct drm_crtc *crtc,
11010 struct drm_framebuffer *fb,
11011 struct drm_i915_gem_object *obj,
11012 struct intel_engine_cs *ring,
11013 uint32_t flags)
11014{
b2cfe0ab
CW		 11015 struct intel_mmio_flip *mmio_flip;
11016
11017 mmio_flip = kmalloc(sizeof(*mmio_flip), GFP_KERNEL);
11018 if (mmio_flip == NULL)
11019 return -ENOMEM;
84c33a64 11020
bcafc4e3 11021 mmio_flip->i915 = to_i915(dev);
eed29a5b 11022 mmio_flip->req = i915_gem_request_reference(obj->last_write_req);
b2cfe0ab 11023 mmio_flip->crtc = to_intel_crtc(crtc);
536f5b5e 11024
b2cfe0ab
CW		 11025 INIT_WORK(&mmio_flip->work, intel_mmio_flip_work_func);
11026 schedule_work(&mmio_flip->work);
84c33a64 11027
84c33a64
SG		 11028 return 0;
11029}
11030
8c9f3aaf
JB		 11031static int intel_default_queue_flip(struct drm_device *dev,
11032 struct drm_crtc *crtc,
11033 struct drm_framebuffer *fb,
ed8d1975 11034 struct drm_i915_gem_object *obj,
a4872ba6 11035 struct intel_engine_cs *ring,
ed8d1975 11036 uint32_t flags)
8c9f3aaf
JB		 11037{
11038 return -ENODEV;
11039}
11040
d6bbafa1
CW		 11041static bool __intel_pageflip_stall_check(struct drm_device *dev,
11042 struct drm_crtc *crtc)
11043{
11044 struct drm_i915_private *dev_priv = dev->dev_private;
11045 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
11046 struct intel_unpin_work *work = intel_crtc->unpin_work;
11047 u32 addr;
11048
11049 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
11050 return true;
11051
11052 if (!work->enable_stall_check)
11053 return false;
11054
11055 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 11056 if (work->flip_queued_req &&
11057 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 11058 return false;
11059
1e3feefd 11060 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 11061 }
11062
1e3feefd 11063 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 11064 return false;
11065
11066 /* Potential stall - if we see that the flip has happened,
11067 * assume a missed interrupt. */
11068 if (INTEL_INFO(dev)->gen >= 4)
11069 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
11070 else
11071 addr = I915_READ(DSPADDR(intel_crtc->plane));
11072
11073 /* There is a potential issue here with a false positive after a flip
11074 * to the same address. We could address this by checking for a
11075 * non-incrementing frame counter.
11076 */
11077 return addr == work->gtt_offset;
11078}
11079
11080void intel_check_page_flip(struct drm_device *dev, int pipe)
11081{
11082 struct drm_i915_private *dev_priv = dev->dev_private;
11083 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
11084 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6ad790c0 11085 struct intel_unpin_work *work;
f326038a 11086
6c51d46f 11087 WARN_ON(!in_interrupt());
d6bbafa1
CW		 11088
11089 if (crtc == NULL)
11090 return;
11091
f326038a 11092 spin_lock(&dev->event_lock);
6ad790c0
CW		 11093 work = intel_crtc->unpin_work;
11094 if (work != NULL && __intel_pageflip_stall_check(dev, crtc)) {
d6bbafa1 11095 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
6ad790c0 11096 work->flip_queued_vblank, drm_vblank_count(dev, pipe));
d6bbafa1 11097 page_flip_completed(intel_crtc);
6ad790c0 11098 work = NULL;
d6bbafa1 11099 }
6ad790c0
CW		 11100 if (work != NULL &&
11101 drm_vblank_count(dev, pipe) - work->flip_queued_vblank > 1)
11102 intel_queue_rps_boost_for_request(dev, work->flip_queued_req);
f326038a 11103 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 11104}
11105
6b95a207
KH		 11106static int intel_crtc_page_flip(struct drm_crtc *crtc,
11107 struct drm_framebuffer *fb,
ed8d1975
KP		 11108 struct drm_pending_vblank_event *event,
11109 uint32_t page_flip_flags)
6b95a207
KH		 11110{
11111 struct drm_device *dev = crtc->dev;
11112 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 11113 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 11114 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 11115 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 11116 struct drm_plane *primary = crtc->primary;
a071fa00 11117 enum pipe pipe = intel_crtc->pipe;
6b95a207 11118 struct intel_unpin_work *work;
a4872ba6 11119 struct intel_engine_cs *ring;
cf5d8a46 11120 bool mmio_flip;
52e68630 11121 int ret;
6b95a207 11122
2ff8fde1
MR		 11123 /*
11124 * drm_mode_page_flip_ioctl() should already catch this, but double
11125 * check to be safe. In the future we may enable pageflipping from
11126 * a disabled primary plane.
11127 */
11128 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
11129 return -EBUSY;
11130
e6a595d2 11131 /* Can't change pixel format via MI display flips. */
f4510a27 11132 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 11133 return -EINVAL;
11134
11135 /*
11136 * TILEOFF/LINOFF registers can't be changed via MI display flips.
11137 * Note that pitch changes could also affect these register.
11138 */
11139 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 11140 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
11141 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 11142 return -EINVAL;
11143
f900db47
CW		 11144 if (i915_terminally_wedged(&dev_priv->gpu_error))
11145 goto out_hang;
11146
b14c5679 11147 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 11148 if (work == NULL)
11149 return -ENOMEM;
11150
6b95a207 11151 work->event = event;
b4a98e57 11152 work->crtc = crtc;
ab8d6675 11153 work->old_fb = old_fb;
6b95a207
KH		 11154 INIT_WORK(&work->work, intel_unpin_work_fn);
11155
87b6b101 11156 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 11157 if (ret)
11158 goto free_work;
11159
6b95a207 11160 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 11161 spin_lock_irq(&dev->event_lock);
6b95a207 11162 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 11163 /* Before declaring the flip queue wedged, check if
11164 * the hardware completed the operation behind our backs.
11165 */
11166 if (__intel_pageflip_stall_check(dev, crtc)) {
11167 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
11168 page_flip_completed(intel_crtc);
11169 } else {
11170 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 11171 spin_unlock_irq(&dev->event_lock);
468f0b44 11172
d6bbafa1
CW		 11173 drm_crtc_vblank_put(crtc);
11174 kfree(work);
11175 return -EBUSY;
11176 }
6b95a207
KH		 11177 }
11178 intel_crtc->unpin_work = work;
5e2d7afc 11179 spin_unlock_irq(&dev->event_lock);
6b95a207 11180
b4a98e57
CW		 11181 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
11182 flush_workqueue(dev_priv->wq);
11183
75dfca80 11184 /* Reference the objects for the scheduled work. */
ab8d6675 11185 drm_framebuffer_reference(work->old_fb);
05394f39 11186 drm_gem_object_reference(&obj->base);
6b95a207 11187
f4510a27 11188 crtc->primary->fb = fb;
afd65eb4 11189 update_state_fb(crtc->primary);
1ed1f968 11190
e1f99ce6 11191 work->pending_flip_obj = obj;
e1f99ce6 11192
89ed88ba
CW		 11193 ret = i915_mutex_lock_interruptible(dev);
11194 if (ret)
11195 goto cleanup;
11196
b4a98e57 11197 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 11198 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 11199
75f7f3ec 11200 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 11201 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 11202
4fa62c89
VS		 11203 if (IS_VALLEYVIEW(dev)) {
11204 ring = &dev_priv->ring[BCS];
ab8d6675 11205 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 11206 /* vlv: DISPLAY_FLIP fails to change tiling */
11207 ring = NULL;
48bf5b2d 11208 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 11209 ring = &dev_priv->ring[BCS];
4fa62c89 11210 } else if (INTEL_INFO(dev)->gen >= 7) {
b4716185 11211 ring = i915_gem_request_get_ring(obj->last_write_req);
4fa62c89
VS		 11212 if (ring == NULL || ring->id != RCS)
11213 ring = &dev_priv->ring[BCS];
11214 } else {
11215 ring = &dev_priv->ring[RCS];
11216 }
11217
cf5d8a46
CW		 11218 mmio_flip = use_mmio_flip(ring, obj);
11219
11220 /* When using CS flips, we want to emit semaphores between rings.
11221 * However, when using mmio flips we will create a task to do the
11222 * synchronisation, so all we want here is to pin the framebuffer
11223 * into the display plane and skip any waits.
11224 */
82bc3b2d 11225 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
cf5d8a46 11226 crtc->primary->state,
b4716185 11227 mmio_flip ? i915_gem_request_get_ring(obj->last_write_req) : ring);
8c9f3aaf
JB		 11228 if (ret)
11229 goto cleanup_pending;
6b95a207 11230
121920fa
TU		 11231 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
11232 + intel_crtc->dspaddr_offset;
4fa62c89 11233
cf5d8a46 11234 if (mmio_flip) {
84c33a64
SG		 11235 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
11236 page_flip_flags);
d6bbafa1
CW		 11237 if (ret)
11238 goto cleanup_unpin;
11239
f06cc1b9
JH		 11240 i915_gem_request_assign(&work->flip_queued_req,
11241 obj->last_write_req);
d6bbafa1 11242 } else {
d94b5030
CW		 11243 if (obj->last_write_req) {
11244 ret = i915_gem_check_olr(obj->last_write_req);
11245 if (ret)
11246 goto cleanup_unpin;
11247 }
11248
84c33a64 11249 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 11250 page_flip_flags);
11251 if (ret)
11252 goto cleanup_unpin;
11253
f06cc1b9
JH		 11254 i915_gem_request_assign(&work->flip_queued_req,
11255 intel_ring_get_request(ring));
d6bbafa1
CW		 11256 }
11257
1e3feefd 11258 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 11259 work->enable_stall_check = true;
4fa62c89 11260
ab8d6675 11261 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 11262 INTEL_FRONTBUFFER_PRIMARY(pipe));
11263
7ff0ebcc 11264 intel_fbc_disable(dev);
f99d7069 11265 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 11266 mutex_unlock(&dev->struct_mutex);
11267
e5510fac
JB		 11268 trace_i915_flip_request(intel_crtc->plane, obj);
11269
6b95a207 11270 return 0;
96b099fd 11271
4fa62c89 11272cleanup_unpin:
82bc3b2d 11273 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 11274cleanup_pending:
b4a98e57 11275 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 11276 mutex_unlock(&dev->struct_mutex);
11277cleanup:
f4510a27 11278 crtc->primary->fb = old_fb;
afd65eb4 11279 update_state_fb(crtc->primary);
89ed88ba
CW		 11280
11281 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 11282 drm_framebuffer_unreference(work->old_fb);
96b099fd 11283
5e2d7afc 11284 spin_lock_irq(&dev->event_lock);
96b099fd 11285 intel_crtc->unpin_work = NULL;
5e2d7afc 11286 spin_unlock_irq(&dev->event_lock);
96b099fd 11287
87b6b101 11288 drm_crtc_vblank_put(crtc);
7317c75e 11289free_work:
96b099fd
CW		 11290 kfree(work);
11291
f900db47
CW		 11292 if (ret == -EIO) {
11293out_hang:
53a366b9 11294 ret = intel_plane_restore(primary);
f0d3dad3 11295 if (ret == 0 && event) {
5e2d7afc 11296 spin_lock_irq(&dev->event_lock);
a071fa00 11297 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 11298 spin_unlock_irq(&dev->event_lock);
f0d3dad3 11299 }
f900db47 11300 }
96b099fd 11301 return ret;
6b95a207
KH		 11302}
11303
65b38e0d 11304static const struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 11305 .mode_set_base_atomic = intel_pipe_set_base_atomic,
11306 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 11307 .atomic_begin = intel_begin_crtc_commit,
11308 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 11309};
11310
9a935856
DV		 11311/**
11312 * intel_modeset_update_staged_output_state
11313 *
11314 * Updates the staged output configuration state, e.g. after we've read out the
11315 * current hw state.
11316 */
11317static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 11318{
7668851f 11319 struct intel_crtc *crtc;
9a935856
DV		 11320 struct intel_encoder *encoder;
11321 struct intel_connector *connector;
f6e5b160 11322
3a3371ff 11323 for_each_intel_connector(dev, connector) {
9a935856
DV		 11324 connector->new_encoder =
11325 to_intel_encoder(connector->base.encoder);
11326 }
f6e5b160 11327
b2784e15 11328 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11329 encoder->new_crtc =
11330 to_intel_crtc(encoder->base.crtc);
11331 }
7668851f 11332
d3fcc808 11333 for_each_intel_crtc(dev, crtc) {
83d65738 11334 crtc->new_enabled = crtc->base.state->enable;
7668851f 11335 }
f6e5b160
CW		 11336}
11337
d29b2f9d
ACO		 11338/* Transitional helper to copy current connector/encoder state to
11339 * connector->state. This is needed so that code that is partially
11340 * converted to atomic does the right thing.
11341 */
11342static void intel_modeset_update_connector_atomic_state(struct drm_device *dev)
11343{
11344 struct intel_connector *connector;
11345
11346 for_each_intel_connector(dev, connector) {
11347 if (connector->base.encoder) {
11348 connector->base.state->best_encoder =
11349 connector->base.encoder;
11350 connector->base.state->crtc =
11351 connector->base.encoder->crtc;
11352 } else {
11353 connector->base.state->best_encoder = NULL;
11354 connector->base.state->crtc = NULL;
11355 }
11356 }
11357}
11358
a821fc46 11359/* Fixup legacy state after an atomic state swap.
9a935856 11360 */
a821fc46 11361static void intel_modeset_fixup_state(struct drm_atomic_state *state)
9a935856 11362{
a821fc46 11363 struct intel_crtc *crtc;
9a935856 11364 struct intel_encoder *encoder;
a821fc46 11365 struct intel_connector *connector;
d5432a9d 11366
a821fc46
ACO		 11367 for_each_intel_connector(state->dev, connector) {
11368 connector->base.encoder = connector->base.state->best_encoder;
11369 if (connector->base.encoder)
11370 connector->base.encoder->crtc =
11371 connector->base.state->crtc;
9a935856 11372 }
f6e5b160 11373
d5432a9d
ACO		 11374 /* Update crtc of disabled encoders */
11375 for_each_intel_encoder(state->dev, encoder) {
11376 int num_connectors = 0;
11377
a821fc46
ACO		 11378 for_each_intel_connector(state->dev, connector)
11379 if (connector->base.encoder == &encoder->base)
d5432a9d
ACO		 11380 num_connectors++;
11381
11382 if (num_connectors == 0)
11383 encoder->base.crtc = NULL;
9a935856 11384 }
7668851f 11385
a821fc46
ACO		 11386 for_each_intel_crtc(state->dev, crtc) {
11387 crtc->base.enabled = crtc->base.state->enable;
11388 crtc->config = to_intel_crtc_state(crtc->base.state);
7668851f 11389 }
d29b2f9d 11390
d5432a9d
ACO		 11391 /* Copy the new configuration to the staged state, to keep the few
11392 * pieces of code that haven't been converted yet happy */
11393 intel_modeset_update_staged_output_state(state->dev);
9a935856
DV		 11394}
11395
050f7aeb 11396static void
eba905b2 11397connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 11398 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 11399{
11400 int bpp = pipe_config->pipe_bpp;
11401
11402 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
11403 connector->base.base.id,
c23cc417 11404 connector->base.name);
050f7aeb
DV		 11405
11406 /* Don't use an invalid EDID bpc value */
11407 if (connector->base.display_info.bpc &&
11408 connector->base.display_info.bpc * 3 < bpp) {
11409 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
11410 bpp, connector->base.display_info.bpc*3);
11411 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
11412 }
11413
11414 /* Clamp bpp to 8 on screens without EDID 1.4 */
11415 if (connector->base.display_info.bpc == 0 && bpp > 24) {
11416 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
11417 bpp);
11418 pipe_config->pipe_bpp = 24;
11419 }
11420}
11421
4e53c2e0 11422static int
050f7aeb 11423compute_baseline_pipe_bpp(struct intel_crtc *crtc,
5cec258b 11424 struct intel_crtc_state *pipe_config)
4e53c2e0 11425{
050f7aeb 11426 struct drm_device *dev = crtc->base.dev;
1486017f 11427 struct drm_atomic_state *state;
da3ced29
ACO		 11428 struct drm_connector *connector;
11429 struct drm_connector_state *connector_state;
1486017f 11430 int bpp, i;
4e53c2e0 11431
d328c9d7 11432 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)))
4e53c2e0 11433 bpp = 10*3;
d328c9d7
DV		 11434 else if (INTEL_INFO(dev)->gen >= 5)
11435 bpp = 12*3;
11436 else
11437 bpp = 8*3;
11438
4e53c2e0 11439
4e53c2e0
DV		 11440 pipe_config->pipe_bpp = bpp;
11441
1486017f
ACO		 11442 state = pipe_config->base.state;
11443
4e53c2e0 11444 /* Clamp display bpp to EDID value */
da3ced29
ACO		 11445 for_each_connector_in_state(state, connector, connector_state, i) {
11446 if (connector_state->crtc != &crtc->base)
4e53c2e0
DV		 11447 continue;
11448
da3ced29
ACO		 11449 connected_sink_compute_bpp(to_intel_connector(connector),
11450 pipe_config);
4e53c2e0
DV		 11451 }
11452
11453 return bpp;
11454}
11455
644db711
DV		 11456static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
11457{
11458 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
11459 "type: 0x%x flags: 0x%x\n",
1342830c 11460 mode->crtc_clock,
644db711
DV		 11461 mode->crtc_hdisplay, mode->crtc_hsync_start,
11462 mode->crtc_hsync_end, mode->crtc_htotal,
11463 mode->crtc_vdisplay, mode->crtc_vsync_start,
11464 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
11465}
11466
c0b03411 11467static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 11468 struct intel_crtc_state *pipe_config,
c0b03411
DV		 11469 const char *context)
11470{
6a60cd87
CK		 11471 struct drm_device *dev = crtc->base.dev;
11472 struct drm_plane *plane;
11473 struct intel_plane *intel_plane;
11474 struct intel_plane_state *state;
11475 struct drm_framebuffer *fb;
11476
11477 DRM_DEBUG_KMS("[CRTC:%d]%s config %p for pipe %c\n", crtc->base.base.id,
11478 context, pipe_config, pipe_name(crtc->pipe));
c0b03411
DV		 11479
11480 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
11481 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
11482 pipe_config->pipe_bpp, pipe_config->dither);
11483 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11484 pipe_config->has_pch_encoder,
11485 pipe_config->fdi_lanes,
11486 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
11487 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
11488 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 11489 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
11490 pipe_config->has_dp_encoder,
11491 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
11492 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
11493 pipe_config->dp_m_n.tu);
b95af8be
VK		 11494
11495 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
11496 pipe_config->has_dp_encoder,
11497 pipe_config->dp_m2_n2.gmch_m,
11498 pipe_config->dp_m2_n2.gmch_n,
11499 pipe_config->dp_m2_n2.link_m,
11500 pipe_config->dp_m2_n2.link_n,
11501 pipe_config->dp_m2_n2.tu);
11502
55072d19
DV		 11503 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
11504 pipe_config->has_audio,
11505 pipe_config->has_infoframe);
11506
c0b03411 11507 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 11508 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 11509 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 11510 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
11511 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 11512 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 11513 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
11514 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
0ec463d3
TU		 11515 DRM_DEBUG_KMS("num_scalers: %d, scaler_users: 0x%x, scaler_id: %d\n",
11516 crtc->num_scalers,
11517 pipe_config->scaler_state.scaler_users,
11518 pipe_config->scaler_state.scaler_id);
c0b03411
DV		 11519 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
11520 pipe_config->gmch_pfit.control,
11521 pipe_config->gmch_pfit.pgm_ratios,
11522 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 11523 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 11524 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 11525 pipe_config->pch_pfit.size,
11526 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 11527 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 11528 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
6a60cd87 11529
415ff0f6
TU		 11530 if (IS_BROXTON(dev)) {
11531 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: ebb0: 0x%x, "
11532 "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
11533 "pll6: 0x%x, pll8: 0x%x, pcsdw12: 0x%x\n",
11534 pipe_config->ddi_pll_sel,
11535 pipe_config->dpll_hw_state.ebb0,
11536 pipe_config->dpll_hw_state.pll0,
11537 pipe_config->dpll_hw_state.pll1,
11538 pipe_config->dpll_hw_state.pll2,
11539 pipe_config->dpll_hw_state.pll3,
11540 pipe_config->dpll_hw_state.pll6,
11541 pipe_config->dpll_hw_state.pll8,
11542 pipe_config->dpll_hw_state.pcsdw12);
11543 } else if (IS_SKYLAKE(dev)) {
11544 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: "
11545 "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
11546 pipe_config->ddi_pll_sel,
11547 pipe_config->dpll_hw_state.ctrl1,
11548 pipe_config->dpll_hw_state.cfgcr1,
11549 pipe_config->dpll_hw_state.cfgcr2);
11550 } else if (HAS_DDI(dev)) {
11551 DRM_DEBUG_KMS("ddi_pll_sel: %u; dpll_hw_state: wrpll: 0x%x\n",
11552 pipe_config->ddi_pll_sel,
11553 pipe_config->dpll_hw_state.wrpll);
11554 } else {
11555 DRM_DEBUG_KMS("dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
11556 "fp0: 0x%x, fp1: 0x%x\n",
11557 pipe_config->dpll_hw_state.dpll,
11558 pipe_config->dpll_hw_state.dpll_md,
11559 pipe_config->dpll_hw_state.fp0,
11560 pipe_config->dpll_hw_state.fp1);
11561 }
11562
6a60cd87
CK		 11563 DRM_DEBUG_KMS("planes on this crtc\n");
11564 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
11565 intel_plane = to_intel_plane(plane);
11566 if (intel_plane->pipe != crtc->pipe)
11567 continue;
11568
11569 state = to_intel_plane_state(plane->state);
11570 fb = state->base.fb;
11571 if (!fb) {
11572 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d "
11573 "disabled, scaler_id = %d\n",
11574 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11575 plane->base.id, intel_plane->pipe,
11576 (crtc->base.primary == plane) ? 0 : intel_plane->plane + 1,
11577 drm_plane_index(plane), state->scaler_id);
11578 continue;
11579 }
11580
11581 DRM_DEBUG_KMS("%s PLANE:%d plane: %u.%u idx: %d enabled",
11582 plane->type == DRM_PLANE_TYPE_CURSOR ? "CURSOR" : "STANDARD",
11583 plane->base.id, intel_plane->pipe,
11584 crtc->base.primary == plane ? 0 : intel_plane->plane + 1,
11585 drm_plane_index(plane));
11586 DRM_DEBUG_KMS("\tFB:%d, fb = %ux%u format = 0x%x",
11587 fb->base.id, fb->width, fb->height, fb->pixel_format);
11588 DRM_DEBUG_KMS("\tscaler:%d src (%u, %u) %ux%u dst (%u, %u) %ux%u\n",
11589 state->scaler_id,
11590 state->src.x1 >> 16, state->src.y1 >> 16,
11591 drm_rect_width(&state->src) >> 16,
11592 drm_rect_height(&state->src) >> 16,
11593 state->dst.x1, state->dst.y1,
11594 drm_rect_width(&state->dst), drm_rect_height(&state->dst));
11595 }
c0b03411
DV		 11596}
11597
bc079e8b
VS		 11598static bool encoders_cloneable(const struct intel_encoder *a,
11599 const struct intel_encoder *b)
accfc0c5 11600{
bc079e8b
VS		 11601 /* masks could be asymmetric, so check both ways */
11602 return a == b || (a->cloneable & (1 << b->type) &&
11603 b->cloneable & (1 << a->type));
11604}
11605
98a221da
ACO		 11606static bool check_single_encoder_cloning(struct drm_atomic_state *state,
11607 struct intel_crtc *crtc,
bc079e8b
VS		 11608 struct intel_encoder *encoder)
11609{
bc079e8b 11610 struct intel_encoder *source_encoder;
da3ced29 11611 struct drm_connector *connector;
98a221da
ACO		 11612 struct drm_connector_state *connector_state;
11613 int i;
bc079e8b 11614
da3ced29 11615 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da 11616 if (connector_state->crtc != &crtc->base)
bc079e8b
VS		 11617 continue;
11618
98a221da
ACO		 11619 source_encoder =
11620 to_intel_encoder(connector_state->best_encoder);
bc079e8b
VS		 11621 if (!encoders_cloneable(encoder, source_encoder))
11622 return false;
11623 }
11624
11625 return true;
11626}
11627
98a221da
ACO		 11628static bool check_encoder_cloning(struct drm_atomic_state *state,
11629 struct intel_crtc *crtc)
bc079e8b 11630{
accfc0c5 11631 struct intel_encoder *encoder;
da3ced29 11632 struct drm_connector *connector;
98a221da
ACO		 11633 struct drm_connector_state *connector_state;
11634 int i;
accfc0c5 11635
da3ced29 11636 for_each_connector_in_state(state, connector, connector_state, i) {
98a221da
ACO		 11637 if (connector_state->crtc != &crtc->base)
11638 continue;
11639
11640 encoder = to_intel_encoder(connector_state->best_encoder);
11641 if (!check_single_encoder_cloning(state, crtc, encoder))
bc079e8b 11642 return false;
accfc0c5
DV		 11643 }
11644
bc079e8b 11645 return true;
accfc0c5
DV		 11646}
11647
5448a00d 11648static bool check_digital_port_conflicts(struct drm_atomic_state *state)
00f0b378 11649{
5448a00d
ACO		 11650 struct drm_device *dev = state->dev;
11651 struct intel_encoder *encoder;
da3ced29 11652 struct drm_connector *connector;
5448a00d 11653 struct drm_connector_state *connector_state;
00f0b378 11654 unsigned int used_ports = 0;
5448a00d 11655 int i;
00f0b378
VS		 11656
11657 /*
11658 * Walk the connector list instead of the encoder
11659 * list to detect the problem on ddi platforms
11660 * where there's just one encoder per digital port.
11661 */
da3ced29 11662 for_each_connector_in_state(state, connector, connector_state, i) {
5448a00d 11663 if (!connector_state->best_encoder)
00f0b378
VS		 11664 continue;
11665
5448a00d
ACO		 11666 encoder = to_intel_encoder(connector_state->best_encoder);
11667
11668 WARN_ON(!connector_state->crtc);
00f0b378
VS		 11669
11670 switch (encoder->type) {
11671 unsigned int port_mask;
11672 case INTEL_OUTPUT_UNKNOWN:
11673 if (WARN_ON(!HAS_DDI(dev)))
11674 break;
11675 case INTEL_OUTPUT_DISPLAYPORT:
11676 case INTEL_OUTPUT_HDMI:
11677 case INTEL_OUTPUT_EDP:
11678 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
11679
11680 /* the same port mustn't appear more than once */
11681 if (used_ports & port_mask)
11682 return false;
11683
11684 used_ports |= port_mask;
11685 default:
11686 break;
11687 }
11688 }
11689
11690 return true;
11691}
11692
83a57153
ACO		 11693static void
11694clear_intel_crtc_state(struct intel_crtc_state *crtc_state)
11695{
11696 struct drm_crtc_state tmp_state;
663a3640 11697 struct intel_crtc_scaler_state scaler_state;
4978cc93
ACO		 11698 struct intel_dpll_hw_state dpll_hw_state;
11699 enum intel_dpll_id shared_dpll;
8504c74c 11700 uint32_t ddi_pll_sel;
83a57153 11701
7546a384
ACO		 11702 /* FIXME: before the switch to atomic started, a new pipe_config was
11703 * kzalloc'd. Code that depends on any field being zero should be
11704 * fixed, so that the crtc_state can be safely duplicated. For now,
11705 * only fields that are know to not cause problems are preserved. */
11706
83a57153 11707 tmp_state = crtc_state->base;
663a3640 11708 scaler_state = crtc_state->scaler_state;
4978cc93
ACO		 11709 shared_dpll = crtc_state->shared_dpll;
11710 dpll_hw_state = crtc_state->dpll_hw_state;
8504c74c 11711 ddi_pll_sel = crtc_state->ddi_pll_sel;
4978cc93 11712
83a57153 11713 memset(crtc_state, 0, sizeof *crtc_state);
4978cc93 11714
83a57153 11715 crtc_state->base = tmp_state;
663a3640 11716 crtc_state->scaler_state = scaler_state;
4978cc93
ACO		 11717 crtc_state->shared_dpll = shared_dpll;
11718 crtc_state->dpll_hw_state = dpll_hw_state;
8504c74c 11719 crtc_state->ddi_pll_sel = ddi_pll_sel;
83a57153
ACO		 11720}
11721
548ee15b 11722static int
b8cecdf5 11723intel_modeset_pipe_config(struct drm_crtc *crtc,
548ee15b
ACO		 11724 struct drm_atomic_state *state,
11725 struct intel_crtc_state *pipe_config)
ee7b9f93 11726{
7758a113 11727 struct intel_encoder *encoder;
da3ced29 11728 struct drm_connector *connector;
0b901879 11729 struct drm_connector_state *connector_state;
d328c9d7 11730 int base_bpp, ret = -EINVAL;
0b901879 11731 int i;
e29c22c0 11732 bool retry = true;
ee7b9f93 11733
98a221da 11734 if (!check_encoder_cloning(state, to_intel_crtc(crtc))) {
accfc0c5 11735 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
548ee15b 11736 return -EINVAL;
accfc0c5
DV		 11737 }
11738
5448a00d 11739 if (!check_digital_port_conflicts(state)) {
00f0b378 11740 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
548ee15b 11741 return -EINVAL;
00f0b378
VS		 11742 }
11743
83a57153 11744 clear_intel_crtc_state(pipe_config);
7758a113 11745
e143a21c
DV		 11746 pipe_config->cpu_transcoder =
11747 (enum transcoder) to_intel_crtc(crtc)->pipe;
b8cecdf5 11748
2960bc9c
ID		 11749 /*
11750 * Sanitize sync polarity flags based on requested ones. If neither
11751 * positive or negative polarity is requested, treat this as meaning
11752 * negative polarity.
11753 */
2d112de7 11754 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11755 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 11756 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 11757
2d112de7 11758 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 11759 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 11760 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 11761
050f7aeb
DV		 11762 /* Compute a starting value for pipe_config->pipe_bpp taking the source
11763 * plane pixel format and any sink constraints into account. Returns the
11764 * source plane bpp so that dithering can be selected on mismatches
11765 * after encoders and crtc also have had their say. */
d328c9d7
DV		 11766 base_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
11767 pipe_config);
11768 if (base_bpp < 0)
4e53c2e0
DV		 11769 goto fail;
11770
e41a56be
VS		 11771 /*
11772 * Determine the real pipe dimensions. Note that stereo modes can
11773 * increase the actual pipe size due to the frame doubling and
11774 * insertion of additional space for blanks between the frame. This
11775 * is stored in the crtc timings. We use the requested mode to do this
11776 * computation to clearly distinguish it from the adjusted mode, which
11777 * can be changed by the connectors in the below retry loop.
11778 */
2d112de7 11779 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 11780 &pipe_config->pipe_src_w,
11781 &pipe_config->pipe_src_h);
e41a56be 11782
e29c22c0 11783encoder_retry:
ef1b460d 11784 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 11785 pipe_config->port_clock = 0;
ef1b460d 11786 pipe_config->pixel_multiplier = 1;
ff9a6750 11787
135c81b8 11788 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 11789 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
11790 CRTC_STEREO_DOUBLE);
135c81b8 11791
7758a113
DV		 11792 /* Pass our mode to the connectors and the CRTC to give them a chance to
11793 * adjust it according to limitations or connector properties, and also
11794 * a chance to reject the mode entirely.
47f1c6c9 11795 */
da3ced29 11796 for_each_connector_in_state(state, connector, connector_state, i) {
0b901879 11797 if (connector_state->crtc != crtc)
7758a113 11798 continue;
7ae89233 11799
0b901879
ACO		 11800 encoder = to_intel_encoder(connector_state->best_encoder);
11801
efea6e8e
DV		 11802 if (!(encoder->compute_config(encoder, pipe_config))) {
11803 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 11804 goto fail;
11805 }
ee7b9f93 11806 }
47f1c6c9 11807
ff9a6750
DV		 11808 /* Set default port clock if not overwritten by the encoder. Needs to be
11809 * done afterwards in case the encoder adjusts the mode. */
11810 if (!pipe_config->port_clock)
2d112de7 11811 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 11812 * pipe_config->pixel_multiplier;
ff9a6750 11813
a43f6e0f 11814 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 11815 if (ret < 0) {
7758a113
DV		 11816 DRM_DEBUG_KMS("CRTC fixup failed\n");
11817 goto fail;
ee7b9f93 11818 }
e29c22c0
DV		 11819
11820 if (ret == RETRY) {
11821 if (WARN(!retry, "loop in pipe configuration computation\n")) {
11822 ret = -EINVAL;
11823 goto fail;
11824 }
11825
11826 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
11827 retry = false;
11828 goto encoder_retry;
11829 }
11830
d328c9d7 11831 pipe_config->dither = pipe_config->pipe_bpp != base_bpp;
4e53c2e0 11832 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
d328c9d7 11833 base_bpp, pipe_config->pipe_bpp, pipe_config->dither);
4e53c2e0 11834
548ee15b 11835 return 0;
7758a113 11836fail:
548ee15b 11837 return ret;
ee7b9f93 11838}
47f1c6c9 11839
ea9d758d 11840static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 11841{
ea9d758d 11842 struct drm_encoder *encoder;
f6e5b160 11843 struct drm_device *dev = crtc->dev;
f6e5b160 11844
ea9d758d
DV		 11845 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
11846 if (encoder->crtc == crtc)
11847 return true;
11848
11849 return false;
11850}
11851
0a9ab303
ACO		 11852static bool
11853needs_modeset(struct drm_crtc_state *state)
11854{
11855 return state->mode_changed || state->active_changed;
11856}
11857
ea9d758d 11858static void
0a9ab303 11859intel_modeset_update_state(struct drm_atomic_state *state)
ea9d758d 11860{
0a9ab303 11861 struct drm_device *dev = state->dev;
ba41c0de 11862 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d 11863 struct intel_encoder *intel_encoder;
0a9ab303
ACO		 11864 struct drm_crtc *crtc;
11865 struct drm_crtc_state *crtc_state;
ea9d758d 11866 struct drm_connector *connector;
0a9ab303 11867 int i;
ea9d758d 11868
ba41c0de
DV		 11869 intel_shared_dpll_commit(dev_priv);
11870
b2784e15 11871 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 11872 if (!intel_encoder->base.crtc)
11873 continue;
11874
0a9ab303
ACO		 11875 for_each_crtc_in_state(state, crtc, crtc_state, i)
11876 if (crtc == intel_encoder->base.crtc)
11877 break;
11878
11879 if (crtc != intel_encoder->base.crtc)
11880 continue;
ea9d758d 11881
0a9ab303 11882 if (crtc_state->enable && needs_modeset(crtc_state))
ea9d758d
DV		 11883 intel_encoder->connectors_active = false;
11884 }
11885
a821fc46
ACO		 11886 drm_atomic_helper_swap_state(state->dev, state);
11887 intel_modeset_fixup_state(state);
ea9d758d 11888
7668851f 11889 /* Double check state. */
0a9ab303
ACO		 11890 for_each_crtc(dev, crtc) {
11891 WARN_ON(crtc->state->enable != intel_crtc_in_use(crtc));
ea9d758d
DV		 11892 }
11893
11894 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
11895 if (!connector->encoder || !connector->encoder->crtc)
11896 continue;
11897
0a9ab303
ACO		 11898 for_each_crtc_in_state(state, crtc, crtc_state, i)
11899 if (crtc == connector->encoder->crtc)
11900 break;
11901
11902 if (crtc != connector->encoder->crtc)
11903 continue;
ea9d758d 11904
a821fc46 11905 if (crtc->state->enable && needs_modeset(crtc->state)) {
68d34720
DV		 11906 struct drm_property *dpms_property =
11907 dev->mode_config.dpms_property;
11908
ea9d758d 11909 connector->dpms = DRM_MODE_DPMS_ON;
662595df 11910 drm_object_property_set_value(&connector->base,
68d34720
DV		 11911 dpms_property,
11912 DRM_MODE_DPMS_ON);
ea9d758d
DV		 11913
11914 intel_encoder = to_intel_encoder(connector->encoder);
11915 intel_encoder->connectors_active = true;
11916 }
11917 }
11918
11919}
11920
3bd26263 11921static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 11922{
3bd26263 11923 int diff;
f1f644dc
JB		 11924
11925 if (clock1 == clock2)
11926 return true;
11927
11928 if (!clock1 || !clock2)
11929 return false;
11930
11931 diff = abs(clock1 - clock2);
11932
11933 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
11934 return true;
11935
11936 return false;
11937}
11938
25c5b266
DV		 11939#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
11940 list_for_each_entry((intel_crtc), \
11941 &(dev)->mode_config.crtc_list, \
11942 base.head) \
0973f18f 11943 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 11944
0e8ffe1b 11945static bool
2fa2fe9a 11946intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 11947 struct intel_crtc_state *current_config,
11948 struct intel_crtc_state *pipe_config)
0e8ffe1b 11949{
66e985c0
DV		 11950#define PIPE_CONF_CHECK_X(name) \
11951 if (current_config->name != pipe_config->name) { \
11952 DRM_ERROR("mismatch in " #name " " \
11953 "(expected 0x%08x, found 0x%08x)\n", \
11954 current_config->name, \
11955 pipe_config->name); \
11956 return false; \
11957 }
11958
08a24034
DV		 11959#define PIPE_CONF_CHECK_I(name) \
11960 if (current_config->name != pipe_config->name) { \
11961 DRM_ERROR("mismatch in " #name " " \
11962 "(expected %i, found %i)\n", \
11963 current_config->name, \
11964 pipe_config->name); \
11965 return false; \
88adfff1
DV		 11966 }
11967
b95af8be
VK		 11968/* This is required for BDW+ where there is only one set of registers for
11969 * switching between high and low RR.
11970 * This macro can be used whenever a comparison has to be made between one
11971 * hw state and multiple sw state variables.
11972 */
11973#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
11974 if ((current_config->name != pipe_config->name) && \
11975 (current_config->alt_name != pipe_config->name)) { \
11976 DRM_ERROR("mismatch in " #name " " \
11977 "(expected %i or %i, found %i)\n", \
11978 current_config->name, \
11979 current_config->alt_name, \
11980 pipe_config->name); \
11981 return false; \
11982 }
11983
1bd1bd80
DV		 11984#define PIPE_CONF_CHECK_FLAGS(name, mask) \
11985 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 11986 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 11987 "(expected %i, found %i)\n", \
11988 current_config->name & (mask), \
11989 pipe_config->name & (mask)); \
11990 return false; \
11991 }
11992
5e550656
VS		 11993#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
11994 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
11995 DRM_ERROR("mismatch in " #name " " \
11996 "(expected %i, found %i)\n", \
11997 current_config->name, \
11998 pipe_config->name); \
11999 return false; \
12000 }
12001
bb760063
DV		 12002#define PIPE_CONF_QUIRK(quirk) \
12003 ((current_config->quirks | pipe_config->quirks) & (quirk))
12004
eccb140b
DV		 12005 PIPE_CONF_CHECK_I(cpu_transcoder);
12006
08a24034
DV		 12007 PIPE_CONF_CHECK_I(has_pch_encoder);
12008 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 12009 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
12010 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
12011 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
12012 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
12013 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 12014
eb14cb74 12015 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 12016
12017 if (INTEL_INFO(dev)->gen < 8) {
12018 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
12019 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
12020 PIPE_CONF_CHECK_I(dp_m_n.link_m);
12021 PIPE_CONF_CHECK_I(dp_m_n.link_n);
12022 PIPE_CONF_CHECK_I(dp_m_n.tu);
12023
12024 if (current_config->has_drrs) {
12025 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
12026 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
12027 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
12028 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
12029 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
12030 }
12031 } else {
12032 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
12033 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
12034 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
12035 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
12036 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
12037 }
eb14cb74 12038
2d112de7
ACO		 12039 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
12040 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
12041 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
12042 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
12043 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
12044 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 12045
2d112de7
ACO		 12046 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
12047 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
12048 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
12049 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
12050 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
12051 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 12052
c93f54cf 12053 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 12054 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 12055 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
12056 IS_VALLEYVIEW(dev))
12057 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 12058 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 12059
9ed109a7
DV		 12060 PIPE_CONF_CHECK_I(has_audio);
12061
2d112de7 12062 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 12063 DRM_MODE_FLAG_INTERLACE);
12064
bb760063 12065 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 12066 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12067 DRM_MODE_FLAG_PHSYNC);
2d112de7 12068 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12069 DRM_MODE_FLAG_NHSYNC);
2d112de7 12070 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 12071 DRM_MODE_FLAG_PVSYNC);
2d112de7 12072 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 12073 DRM_MODE_FLAG_NVSYNC);
12074 }
045ac3b5 12075
37327abd
VS		 12076 PIPE_CONF_CHECK_I(pipe_src_w);
12077 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 12078
9953599b
DV		 12079 /*
12080 * FIXME: BIOS likes to set up a cloned config with lvds+external
12081 * screen. Since we don't yet re-compute the pipe config when moving
12082 * just the lvds port away to another pipe the sw tracking won't match.
12083 *
12084 * Proper atomic modesets with recomputed global state will fix this.
12085 * Until then just don't check gmch state for inherited modes.
12086 */
12087 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
12088 PIPE_CONF_CHECK_I(gmch_pfit.control);
12089 /* pfit ratios are autocomputed by the hw on gen4+ */
12090 if (INTEL_INFO(dev)->gen < 4)
12091 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
12092 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
12093 }
12094
fd4daa9c
CW		 12095 PIPE_CONF_CHECK_I(pch_pfit.enabled);
12096 if (current_config->pch_pfit.enabled) {
12097 PIPE_CONF_CHECK_I(pch_pfit.pos);
12098 PIPE_CONF_CHECK_I(pch_pfit.size);
12099 }
2fa2fe9a 12100
a1b2278e
CK		 12101 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
12102
e59150dc
JB		 12103 /* BDW+ don't expose a synchronous way to read the state */
12104 if (IS_HASWELL(dev))
12105 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 12106
282740f7
VS		 12107 PIPE_CONF_CHECK_I(double_wide);
12108
26804afd
DV		 12109 PIPE_CONF_CHECK_X(ddi_pll_sel);
12110
c0d43d62 12111 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 12112 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 12113 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 12114 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
12115 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 12116 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 12117 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
12118 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
12119 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 12120
42571aef
VS		 12121 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
12122 PIPE_CONF_CHECK_I(pipe_bpp);
12123
2d112de7 12124 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 12125 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 12126
66e985c0 12127#undef PIPE_CONF_CHECK_X
08a24034 12128#undef PIPE_CONF_CHECK_I
b95af8be 12129#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 12130#undef PIPE_CONF_CHECK_FLAGS
5e550656 12131#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 12132#undef PIPE_CONF_QUIRK
88adfff1 12133
0e8ffe1b
DV		 12134 return true;
12135}
12136
08db6652
DL		 12137static void check_wm_state(struct drm_device *dev)
12138{
12139 struct drm_i915_private *dev_priv = dev->dev_private;
12140 struct skl_ddb_allocation hw_ddb, *sw_ddb;
12141 struct intel_crtc *intel_crtc;
12142 int plane;
12143
12144 if (INTEL_INFO(dev)->gen < 9)
12145 return;
12146
12147 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
12148 sw_ddb = &dev_priv->wm.skl_hw.ddb;
12149
12150 for_each_intel_crtc(dev, intel_crtc) {
12151 struct skl_ddb_entry *hw_entry, *sw_entry;
12152 const enum pipe pipe = intel_crtc->pipe;
12153
12154 if (!intel_crtc->active)
12155 continue;
12156
12157 /* planes */
dd740780 12158 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 12159 hw_entry = &hw_ddb.plane[pipe][plane];
12160 sw_entry = &sw_ddb->plane[pipe][plane];
12161
12162 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12163 continue;
12164
12165 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
12166 "(expected (%u,%u), found (%u,%u))\n",
12167 pipe_name(pipe), plane + 1,
12168 sw_entry->start, sw_entry->end,
12169 hw_entry->start, hw_entry->end);
12170 }
12171
12172 /* cursor */
12173 hw_entry = &hw_ddb.cursor[pipe];
12174 sw_entry = &sw_ddb->cursor[pipe];
12175
12176 if (skl_ddb_entry_equal(hw_entry, sw_entry))
12177 continue;
12178
12179 DRM_ERROR("mismatch in DDB state pipe %c cursor "
12180 "(expected (%u,%u), found (%u,%u))\n",
12181 pipe_name(pipe),
12182 sw_entry->start, sw_entry->end,
12183 hw_entry->start, hw_entry->end);
12184 }
12185}
12186
91d1b4bd
DV		 12187static void
12188check_connector_state(struct drm_device *dev)
8af6cf88 12189{
8af6cf88
DV		 12190 struct intel_connector *connector;
12191
3a3371ff 12192 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12193 /* This also checks the encoder/connector hw state with the
12194 * ->get_hw_state callbacks. */
12195 intel_connector_check_state(connector);
12196
e2c719b7 12197 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 12198 "connector's staged encoder doesn't match current encoder\n");
12199 }
91d1b4bd
DV		 12200}
12201
12202static void
12203check_encoder_state(struct drm_device *dev)
12204{
12205 struct intel_encoder *encoder;
12206 struct intel_connector *connector;
8af6cf88 12207
b2784e15 12208 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12209 bool enabled = false;
12210 bool active = false;
12211 enum pipe pipe, tracked_pipe;
12212
12213 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
12214 encoder->base.base.id,
8e329a03 12215 encoder->base.name);
8af6cf88 12216
e2c719b7 12217 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 12218 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 12219 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 12220 "encoder's active_connectors set, but no crtc\n");
12221
3a3371ff 12222 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 12223 if (connector->base.encoder != &encoder->base)
12224 continue;
12225 enabled = true;
12226 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
12227 active = true;
12228 }
0e32b39c
DA		 12229 /*
12230 * for MST connectors if we unplug the connector is gone
12231 * away but the encoder is still connected to a crtc
12232 * until a modeset happens in response to the hotplug.
12233 */
12234 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
12235 continue;
12236
e2c719b7 12237 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 12238 "encoder's enabled state mismatch "
12239 "(expected %i, found %i)\n",
12240 !!encoder->base.crtc, enabled);
e2c719b7 12241 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 12242 "active encoder with no crtc\n");
12243
e2c719b7 12244 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 12245 "encoder's computed active state doesn't match tracked active state "
12246 "(expected %i, found %i)\n", active, encoder->connectors_active);
12247
12248 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 12249 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 12250 "encoder's hw state doesn't match sw tracking "
12251 "(expected %i, found %i)\n",
12252 encoder->connectors_active, active);
12253
12254 if (!encoder->base.crtc)
12255 continue;
12256
12257 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 12258 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 12259 "active encoder's pipe doesn't match"
12260 "(expected %i, found %i)\n",
12261 tracked_pipe, pipe);
12262
12263 }
91d1b4bd
DV		 12264}
12265
12266static void
12267check_crtc_state(struct drm_device *dev)
12268{
fbee40df 12269 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12270 struct intel_crtc *crtc;
12271 struct intel_encoder *encoder;
5cec258b 12272 struct intel_crtc_state pipe_config;
8af6cf88 12273
d3fcc808 12274 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 12275 bool enabled = false;
12276 bool active = false;
12277
045ac3b5
JB		 12278 memset(&pipe_config, 0, sizeof(pipe_config));
12279
8af6cf88
DV		 12280 DRM_DEBUG_KMS("[CRTC:%d]\n",
12281 crtc->base.base.id);
12282
83d65738 12283 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 12284 "active crtc, but not enabled in sw tracking\n");
12285
b2784e15 12286 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 12287 if (encoder->base.crtc != &crtc->base)
12288 continue;
12289 enabled = true;
12290 if (encoder->connectors_active)
12291 active = true;
12292 }
6c49f241 12293
e2c719b7 12294 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 12295 "crtc's computed active state doesn't match tracked active state "
12296 "(expected %i, found %i)\n", active, crtc->active);
83d65738 12297 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 12298 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 12299 "(expected %i, found %i)\n", enabled,
12300 crtc->base.state->enable);
8af6cf88 12301
0e8ffe1b
DV		 12302 active = dev_priv->display.get_pipe_config(crtc,
12303 &pipe_config);
d62cf62a 12304
b6b5d049
VS		 12305 /* hw state is inconsistent with the pipe quirk */
12306 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
12307 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 12308 active = crtc->active;
12309
b2784e15 12310 for_each_intel_encoder(dev, encoder) {
3eaba51c 12311 enum pipe pipe;
6c49f241
DV		 12312 if (encoder->base.crtc != &crtc->base)
12313 continue;
1d37b689 12314 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 12315 encoder->get_config(encoder, &pipe_config);
12316 }
12317
e2c719b7 12318 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 12319 "crtc active state doesn't match with hw state "
12320 "(expected %i, found %i)\n", crtc->active, active);
12321
c0b03411 12322 if (active &&
6e3c9717 12323 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 12324 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 12325 intel_dump_pipe_config(crtc, &pipe_config,
12326 "[hw state]");
6e3c9717 12327 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 12328 "[sw state]");
12329 }
8af6cf88
DV		 12330 }
12331}
12332
91d1b4bd
DV		 12333static void
12334check_shared_dpll_state(struct drm_device *dev)
12335{
fbee40df 12336 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 12337 struct intel_crtc *crtc;
12338 struct intel_dpll_hw_state dpll_hw_state;
12339 int i;
5358901f
DV		 12340
12341 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
12342 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
12343 int enabled_crtcs = 0, active_crtcs = 0;
12344 bool active;
12345
12346 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
12347
12348 DRM_DEBUG_KMS("%s\n", pll->name);
12349
12350 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
12351
e2c719b7 12352 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 12353 "more active pll users than references: %i vs %i\n",
3e369b76 12354 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 12355 I915_STATE_WARN(pll->active && !pll->on,
5358901f 12356 "pll in active use but not on in sw tracking\n");
e2c719b7 12357 I915_STATE_WARN(pll->on && !pll->active,
35c95375 12358 "pll in on but not on in use in sw tracking\n");
e2c719b7 12359 I915_STATE_WARN(pll->on != active,
5358901f
DV		 12360 "pll on state mismatch (expected %i, found %i)\n",
12361 pll->on, active);
12362
d3fcc808 12363 for_each_intel_crtc(dev, crtc) {
83d65738 12364 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 12365 enabled_crtcs++;
12366 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
12367 active_crtcs++;
12368 }
e2c719b7 12369 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 12370 "pll active crtcs mismatch (expected %i, found %i)\n",
12371 pll->active, active_crtcs);
e2c719b7 12372 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 12373 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 12374 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 12375
e2c719b7 12376 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 12377 sizeof(dpll_hw_state)),
12378 "pll hw state mismatch\n");
5358901f 12379 }
8af6cf88
DV		 12380}
12381
91d1b4bd
DV		 12382void
12383intel_modeset_check_state(struct drm_device *dev)
12384{
08db6652 12385 check_wm_state(dev);
91d1b4bd
DV		 12386 check_connector_state(dev);
12387 check_encoder_state(dev);
12388 check_crtc_state(dev);
12389 check_shared_dpll_state(dev);
12390}
12391
5cec258b 12392void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 12393 int dotclock)
12394{
12395 /*
12396 * FDI already provided one idea for the dotclock.
12397 * Yell if the encoder disagrees.
12398 */
2d112de7 12399 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 12400 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 12401 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 12402}
12403
80715b2f
VS		 12404static void update_scanline_offset(struct intel_crtc *crtc)
12405{
12406 struct drm_device *dev = crtc->base.dev;
12407
12408 /*
12409 * The scanline counter increments at the leading edge of hsync.
12410 *
12411 * On most platforms it starts counting from vtotal-1 on the
12412 * first active line. That means the scanline counter value is
12413 * always one less than what we would expect. Ie. just after
12414 * start of vblank, which also occurs at start of hsync (on the
12415 * last active line), the scanline counter will read vblank_start-1.
12416 *
12417 * On gen2 the scanline counter starts counting from 1 instead
12418 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
12419 * to keep the value positive), instead of adding one.
12420 *
12421 * On HSW+ the behaviour of the scanline counter depends on the output
12422 * type. For DP ports it behaves like most other platforms, but on HDMI
12423 * there's an extra 1 line difference. So we need to add two instead of
12424 * one to the value.
12425 */
12426 if (IS_GEN2(dev)) {
6e3c9717 12427 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 12428 int vtotal;
12429
12430 vtotal = mode->crtc_vtotal;
12431 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
12432 vtotal /= 2;
12433
12434 crtc->scanline_offset = vtotal - 1;
12435 } else if (HAS_DDI(dev) &&
409ee761 12436 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 12437 crtc->scanline_offset = 2;
12438 } else
12439 crtc->scanline_offset = 1;
12440}
12441
5cec258b 12442static struct intel_crtc_state *
7f27126e 12443intel_modeset_compute_config(struct drm_crtc *crtc,
0a9ab303 12444 struct drm_atomic_state *state)
7f27126e 12445{
548ee15b 12446 struct intel_crtc_state *pipe_config;
0b901879
ACO		 12447 int ret = 0;
12448
12449 ret = drm_atomic_add_affected_connectors(state, crtc);
12450 if (ret)
12451 return ERR_PTR(ret);
7f27126e 12452
8c7b5ccb
ACO		 12453 ret = drm_atomic_helper_check_modeset(state->dev, state);
12454 if (ret)
12455 return ERR_PTR(ret);
7f27126e 12456
7f27126e
JB		 12457 /*
12458 * Note this needs changes when we start tracking multiple modes
12459 * and crtcs. At that point we'll need to compute the whole config
12460 * (i.e. one pipe_config for each crtc) rather than just the one
12461 * for this crtc.
12462 */
548ee15b
ACO		 12463 pipe_config = intel_atomic_get_crtc_state(state, to_intel_crtc(crtc));
12464 if (IS_ERR(pipe_config))
12465 return pipe_config;
83a57153 12466
4fed33f6 12467 if (!pipe_config->base.enable)
548ee15b 12468 return pipe_config;
7f27126e 12469
8c7b5ccb 12470 ret = intel_modeset_pipe_config(crtc, state, pipe_config);
548ee15b
ACO		 12471 if (ret)
12472 return ERR_PTR(ret);
12473
8d8c9b51
ACO		 12474 /* Check things that can only be changed through modeset */
12475 if (pipe_config->has_audio !=
12476 to_intel_crtc(crtc)->config->has_audio)
12477 pipe_config->base.mode_changed = true;
12478
12479 /*
12480 * Note we have an issue here with infoframes: current code
12481 * only updates them on the full mode set path per hw
12482 * requirements. So here we should be checking for any
12483 * required changes and forcing a mode set.
12484 */
12485
548ee15b 12486 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,"[modeset]");
db7542dd 12487
8c7b5ccb
ACO		 12488 ret = drm_atomic_helper_check_planes(state->dev, state);
12489 if (ret)
12490 return ERR_PTR(ret);
12491
548ee15b 12492 return pipe_config;
7f27126e
JB		 12493}
12494
0a9ab303 12495static int __intel_set_mode_setup_plls(struct drm_atomic_state *state)
ed6739ef 12496{
225da59b 12497 struct drm_device *dev = state->dev;
ed6739ef 12498 struct drm_i915_private *dev_priv = to_i915(dev);
0a9ab303 12499 unsigned clear_pipes = 0;
ed6739ef 12500 struct intel_crtc *intel_crtc;
0a9ab303
ACO		 12501 struct intel_crtc_state *intel_crtc_state;
12502 struct drm_crtc *crtc;
12503 struct drm_crtc_state *crtc_state;
ed6739ef 12504 int ret = 0;
0a9ab303 12505 int i;
ed6739ef
ACO		 12506
12507 if (!dev_priv->display.crtc_compute_clock)
12508 return 0;
12509
0a9ab303
ACO		 12510 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12511 intel_crtc = to_intel_crtc(crtc);
4978cc93 12512 intel_crtc_state = to_intel_crtc_state(crtc_state);
0a9ab303 12513
4978cc93 12514 if (needs_modeset(crtc_state)) {
0a9ab303 12515 clear_pipes |= 1 << intel_crtc->pipe;
4978cc93 12516 intel_crtc_state->shared_dpll = DPLL_ID_PRIVATE;
4978cc93 12517 }
0a9ab303
ACO		 12518 }
12519
ed6739ef
ACO		 12520 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
12521 if (ret)
12522 goto done;
12523
0a9ab303
ACO		 12524 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12525 if (!needs_modeset(crtc_state) || !crtc_state->enable)
225da59b
ACO		 12526 continue;
12527
0a9ab303
ACO		 12528 intel_crtc = to_intel_crtc(crtc);
12529 intel_crtc_state = to_intel_crtc_state(crtc_state);
12530
ed6739ef 12531 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
0a9ab303 12532 intel_crtc_state);
ed6739ef
ACO		 12533 if (ret) {
12534 intel_shared_dpll_abort_config(dev_priv);
12535 goto done;
12536 }
12537 }
12538
12539done:
12540 return ret;
12541}
12542
054518dd
ACO		 12543/* Code that should eventually be part of atomic_check() */
12544static int __intel_set_mode_checks(struct drm_atomic_state *state)
12545{
12546 struct drm_device *dev = state->dev;
12547 int ret;
12548
12549 /*
12550 * See if the config requires any additional preparation, e.g.
12551 * to adjust global state with pipes off. We need to do this
12552 * here so we can get the modeset_pipe updated config for the new
12553 * mode set on this crtc. For other crtcs we need to use the
12554 * adjusted_mode bits in the crtc directly.
12555 */
12556 if (IS_VALLEYVIEW(dev) || IS_BROXTON(dev)) {
12557 ret = valleyview_modeset_global_pipes(state);
12558 if (ret)
12559 return ret;
12560 }
12561
12562 ret = __intel_set_mode_setup_plls(state);
12563 if (ret)
12564 return ret;
12565
12566 return 0;
12567}
12568
0a9ab303 12569static int __intel_set_mode(struct drm_crtc *modeset_crtc,
0a9ab303 12570 struct intel_crtc_state *pipe_config)
a6778b3c 12571{
0a9ab303 12572 struct drm_device *dev = modeset_crtc->dev;
fbee40df 12573 struct drm_i915_private *dev_priv = dev->dev_private;
304603f4 12574 struct drm_atomic_state *state = pipe_config->base.state;
0a9ab303
ACO		 12575 struct drm_crtc *crtc;
12576 struct drm_crtc_state *crtc_state;
c0c36b94 12577 int ret = 0;
0a9ab303 12578 int i;
a6778b3c 12579
054518dd
ACO		 12580 ret = __intel_set_mode_checks(state);
12581 if (ret < 0)
12582 return ret;
12583
d4afb8cc
ACO		 12584 ret = drm_atomic_helper_prepare_planes(dev, state);
12585 if (ret)
12586 return ret;
12587
0a9ab303
ACO		 12588 for_each_crtc_in_state(state, crtc, crtc_state, i) {
12589 if (!needs_modeset(crtc_state))
12590 continue;
460da916 12591
0a9ab303
ACO		 12592 if (!crtc_state->enable) {
12593 intel_crtc_disable(crtc);
12594 } else if (crtc->state->enable) {
12595 intel_crtc_disable_planes(crtc);
12596 dev_priv->display.crtc_disable(crtc);
ce22dba9 12597 }
ea9d758d 12598 }
a6778b3c 12599
6c4c86f5
DV		 12600 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
12601 * to set it here already despite that we pass it down the callchain.
7f27126e
JB		 12602 *
12603 * Note we'll need to fix this up when we start tracking multiple
12604 * pipes; here we assume a single modeset_pipe and only track the
12605 * single crtc and mode.
f6e5b160 12606 */
0a9ab303 12607 if (pipe_config->base.enable && needs_modeset(&pipe_config->base)) {
8c7b5ccb 12608 modeset_crtc->mode = pipe_config->base.mode;
c326c0a9
VS		 12609
12610 /*
12611 * Calculate and store various constants which
12612 * are later needed by vblank and swap-completion
12613 * timestamping. They are derived from true hwmode.
12614 */
0a9ab303 12615 drm_calc_timestamping_constants(modeset_crtc,
2d112de7 12616 &pipe_config->base.adjusted_mode);
b8cecdf5 12617 }
7758a113 12618
ea9d758d
DV		 12619 /* Only after disabling all output pipelines that will be changed can we
12620 * update the the output configuration. */
0a9ab303 12621 intel_modeset_update_state(state);
f6e5b160 12622
a821fc46
ACO		 12623 /* The state has been swaped above, so state actually contains the
12624 * old state now. */
12625
304603f4 12626 modeset_update_crtc_power_domains(state);
47fab737 12627
d4afb8cc 12628 drm_atomic_helper_commit_planes(dev, state);
a6778b3c
DV		 12629
12630 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
0a9ab303 12631 for_each_crtc_in_state(state, crtc, crtc_state, i) {
a821fc46 12632 if (!needs_modeset(crtc->state) || !crtc->state->enable)
0a9ab303
ACO		 12633 continue;
12634
12635 update_scanline_offset(to_intel_crtc(crtc));
80715b2f 12636
0a9ab303
ACO		 12637 dev_priv->display.crtc_enable(crtc);
12638 intel_crtc_enable_planes(crtc);
80715b2f 12639 }
a6778b3c 12640
a6778b3c 12641 /* FIXME: add subpixel order */
83a57153 12642
d4afb8cc
ACO		 12643 drm_atomic_helper_cleanup_planes(dev, state);
12644
2bfb4627
ACO		 12645 drm_atomic_state_free(state);
12646
9eb45f22 12647 return 0;
f6e5b160
CW		 12648}
12649
0a9ab303 12650static int intel_set_mode_with_config(struct drm_crtc *crtc,
0a9ab303 12651 struct intel_crtc_state *pipe_config)
f30da187
DV		 12652{
12653 int ret;
12654
8c7b5ccb 12655 ret = __intel_set_mode(crtc, pipe_config);
f30da187
DV		 12656
12657 if (ret == 0)
12658 intel_modeset_check_state(crtc->dev);
12659
12660 return ret;
12661}
12662
7f27126e 12663static int intel_set_mode(struct drm_crtc *crtc,
83a57153 12664 struct drm_atomic_state *state)
7f27126e 12665{
5cec258b 12666 struct intel_crtc_state *pipe_config;
83a57153 12667 int ret = 0;
7f27126e 12668
8c7b5ccb 12669 pipe_config = intel_modeset_compute_config(crtc, state);
83a57153
ACO		 12670 if (IS_ERR(pipe_config)) {
12671 ret = PTR_ERR(pipe_config);
12672 goto out;
12673 }
12674
8c7b5ccb 12675 ret = intel_set_mode_with_config(crtc, pipe_config);
83a57153
ACO		 12676 if (ret)
12677 goto out;
7f27126e 12678
83a57153
ACO		 12679out:
12680 return ret;
7f27126e
JB		 12681}
12682
c0c36b94
CW		 12683void intel_crtc_restore_mode(struct drm_crtc *crtc)
12684{
83a57153
ACO		 12685 struct drm_device *dev = crtc->dev;
12686 struct drm_atomic_state *state;
4be07317 12687 struct intel_crtc *intel_crtc;
83a57153
ACO		 12688 struct intel_encoder *encoder;
12689 struct intel_connector *connector;
12690 struct drm_connector_state *connector_state;
4be07317 12691 struct intel_crtc_state *crtc_state;
2bfb4627 12692 int ret;
83a57153
ACO		 12693
12694 state = drm_atomic_state_alloc(dev);
12695 if (!state) {
12696 DRM_DEBUG_KMS("[CRTC:%d] mode restore failed, out of memory",
12697 crtc->base.id);
12698 return;
12699 }
12700
12701 state->acquire_ctx = dev->mode_config.acquire_ctx;
12702
12703 /* The force restore path in the HW readout code relies on the staged
12704 * config still keeping the user requested config while the actual
12705 * state has been overwritten by the configuration read from HW. We
12706 * need to copy the staged config to the atomic state, otherwise the
12707 * mode set will just reapply the state the HW is already in. */
12708 for_each_intel_encoder(dev, encoder) {
12709 if (&encoder->new_crtc->base != crtc)
12710 continue;
12711
12712 for_each_intel_connector(dev, connector) {
12713 if (connector->new_encoder != encoder)
12714 continue;
12715
12716 connector_state = drm_atomic_get_connector_state(state, &connector->base);
12717 if (IS_ERR(connector_state)) {
12718 DRM_DEBUG_KMS("Failed to add [CONNECTOR:%d:%s] to state: %ld\n",
12719 connector->base.base.id,
12720 connector->base.name,
12721 PTR_ERR(connector_state));
12722 continue;
12723 }
12724
12725 connector_state->crtc = crtc;
12726 connector_state->best_encoder = &encoder->base;
12727 }
12728 }
12729
4be07317
ACO		 12730 for_each_intel_crtc(dev, intel_crtc) {
12731 if (intel_crtc->new_enabled == intel_crtc->base.enabled)
12732 continue;
12733
12734 crtc_state = intel_atomic_get_crtc_state(state, intel_crtc);
12735 if (IS_ERR(crtc_state)) {
12736 DRM_DEBUG_KMS("Failed to add [CRTC:%d] to state: %ld\n",
12737 intel_crtc->base.base.id,
12738 PTR_ERR(crtc_state));
12739 continue;
12740 }
12741
49d6fa21
ML		 12742 crtc_state->base.active = crtc_state->base.enable =
12743 intel_crtc->new_enabled;
8c7b5ccb
ACO		 12744
12745 if (&intel_crtc->base == crtc)
12746 drm_mode_copy(&crtc_state->base.mode, &crtc->mode);
4be07317
ACO		 12747 }
12748
d3a40d1b
ACO		 12749 intel_modeset_setup_plane_state(state, crtc, &crtc->mode,
12750 crtc->primary->fb, crtc->x, crtc->y);
12751
2bfb4627
ACO		 12752 ret = intel_set_mode(crtc, state);
12753 if (ret)
12754 drm_atomic_state_free(state);
c0c36b94
CW		 12755}
12756
25c5b266
DV		 12757#undef for_each_intel_crtc_masked
12758
b7885264
ACO		 12759static bool intel_connector_in_mode_set(struct intel_connector *connector,
12760 struct drm_mode_set *set)
12761{
12762 int ro;
12763
12764 for (ro = 0; ro < set->num_connectors; ro++)
12765 if (set->connectors[ro] == &connector->base)
12766 return true;
12767
12768 return false;
12769}
12770
2e431051 12771static int
9a935856
DV		 12772intel_modeset_stage_output_state(struct drm_device *dev,
12773 struct drm_mode_set *set,
944b0c76 12774 struct drm_atomic_state *state)
50f56119 12775{
9a935856 12776 struct intel_connector *connector;
d5432a9d 12777 struct drm_connector *drm_connector;
944b0c76 12778 struct drm_connector_state *connector_state;
d5432a9d
ACO		 12779 struct drm_crtc *crtc;
12780 struct drm_crtc_state *crtc_state;
12781 int i, ret;
50f56119 12782
9abdda74 12783 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 12784 * of connectors. For paranoia, double-check this. */
12785 WARN_ON(!set->fb && (set->num_connectors != 0));
12786 WARN_ON(set->fb && (set->num_connectors == 0));
12787
3a3371ff 12788 for_each_intel_connector(dev, connector) {
b7885264
ACO		 12789 bool in_mode_set = intel_connector_in_mode_set(connector, set);
12790
d5432a9d
ACO		 12791 if (!in_mode_set && connector->base.state->crtc != set->crtc)
12792 continue;
12793
12794 connector_state =
12795 drm_atomic_get_connector_state(state, &connector->base);
12796 if (IS_ERR(connector_state))
12797 return PTR_ERR(connector_state);
12798
b7885264
ACO		 12799 if (in_mode_set) {
12800 int pipe = to_intel_crtc(set->crtc)->pipe;
d5432a9d
ACO		 12801 connector_state->best_encoder =
12802 &intel_find_encoder(connector, pipe)->base;
50f56119
DV		 12803 }
12804
d5432a9d 12805 if (connector->base.state->crtc != set->crtc)
b7885264
ACO		 12806 continue;
12807
9a935856
DV		 12808 /* If we disable the crtc, disable all its connectors. Also, if
12809 * the connector is on the changing crtc but not on the new
12810 * connector list, disable it. */
b7885264 12811 if (!set->fb || !in_mode_set) {
d5432a9d 12812 connector_state->best_encoder = NULL;
9a935856
DV		 12813
12814 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
12815 connector->base.base.id,
c23cc417 12816 connector->base.name);
9a935856 12817 }
50f56119 12818 }
9a935856 12819 /* connector->new_encoder is now updated for all connectors. */
50f56119 12820
d5432a9d
ACO		 12821 for_each_connector_in_state(state, drm_connector, connector_state, i) {
12822 connector = to_intel_connector(drm_connector);
12823
12824 if (!connector_state->best_encoder) {
12825 ret = drm_atomic_set_crtc_for_connector(connector_state,
12826 NULL);
12827 if (ret)
12828 return ret;
7668851f 12829
50f56119 12830 continue;
d5432a9d 12831 }
50f56119 12832
d5432a9d
ACO		 12833 if (intel_connector_in_mode_set(connector, set)) {
12834 struct drm_crtc *crtc = connector->base.state->crtc;
12835
12836 /* If this connector was in a previous crtc, add it
12837 * to the state. We might need to disable it. */
12838 if (crtc) {
12839 crtc_state =
12840 drm_atomic_get_crtc_state(state, crtc);
12841 if (IS_ERR(crtc_state))
12842 return PTR_ERR(crtc_state);
12843 }
12844
12845 ret = drm_atomic_set_crtc_for_connector(connector_state,
12846 set->crtc);
12847 if (ret)
12848 return ret;
12849 }
50f56119
DV		 12850
12851 /* Make sure the new CRTC will work with the encoder */
d5432a9d
ACO		 12852 if (!drm_encoder_crtc_ok(connector_state->best_encoder,
12853 connector_state->crtc)) {
5e2b584e 12854 return -EINVAL;
50f56119 12855 }
944b0c76 12856
9a935856
DV		 12857 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
12858 connector->base.base.id,
c23cc417 12859 connector->base.name,
d5432a9d 12860 connector_state->crtc->base.id);
944b0c76 12861
d5432a9d
ACO		 12862 if (connector_state->best_encoder != &connector->encoder->base)
12863 connector->encoder =
12864 to_intel_encoder(connector_state->best_encoder);
0e32b39c 12865 }
7668851f 12866
d5432a9d 12867 for_each_crtc_in_state(state, crtc, crtc_state, i) {
49d6fa21
ML		 12868 bool has_connectors;
12869
d5432a9d
ACO		 12870 ret = drm_atomic_add_affected_connectors(state, crtc);
12871 if (ret)
12872 return ret;
4be07317 12873
49d6fa21
ML		 12874 has_connectors = !!drm_atomic_connectors_for_crtc(state, crtc);
12875 if (has_connectors != crtc_state->enable)
12876 crtc_state->enable =
12877 crtc_state->active = has_connectors;
7668851f
VS		 12878 }
12879
8c7b5ccb
ACO		 12880 ret = intel_modeset_setup_plane_state(state, set->crtc, set->mode,
12881 set->fb, set->x, set->y);
12882 if (ret)
12883 return ret;
12884
12885 crtc_state = drm_atomic_get_crtc_state(state, set->crtc);
12886 if (IS_ERR(crtc_state))
12887 return PTR_ERR(crtc_state);
12888
12889 if (set->mode)
12890 drm_mode_copy(&crtc_state->mode, set->mode);
12891
12892 if (set->num_connectors)
12893 crtc_state->active = true;
12894
2e431051
DV		 12895 return 0;
12896}
12897
bb546623
ACO		 12898static bool primary_plane_visible(struct drm_crtc *crtc)
12899{
12900 struct intel_plane_state *plane_state =
12901 to_intel_plane_state(crtc->primary->state);
12902
12903 return plane_state->visible;
12904}
12905
2e431051
DV		 12906static int intel_crtc_set_config(struct drm_mode_set *set)
12907{
12908 struct drm_device *dev;
83a57153 12909 struct drm_atomic_state *state = NULL;
5cec258b 12910 struct intel_crtc_state *pipe_config;
bb546623 12911 bool primary_plane_was_visible;
2e431051 12912 int ret;
2e431051 12913
8d3e375e
DV		 12914 BUG_ON(!set);
12915 BUG_ON(!set->crtc);
12916 BUG_ON(!set->crtc->helper_private);
2e431051 12917
7e53f3a4
DV		 12918 /* Enforce sane interface api - has been abused by the fb helper. */
12919 BUG_ON(!set->mode && set->fb);
12920 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 12921
2e431051
DV		 12922 if (set->fb) {
12923 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
12924 set->crtc->base.id, set->fb->base.id,
12925 (int)set->num_connectors, set->x, set->y);
12926 } else {
12927 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 12928 }
12929
12930 dev = set->crtc->dev;
12931
83a57153 12932 state = drm_atomic_state_alloc(dev);
7cbf41d6
ACO		 12933 if (!state)
12934 return -ENOMEM;
83a57153
ACO		 12935
12936 state->acquire_ctx = dev->mode_config.acquire_ctx;
12937
462a425a 12938 ret = intel_modeset_stage_output_state(dev, set, state);
2e431051 12939 if (ret)
7cbf41d6 12940 goto out;
2e431051 12941
8c7b5ccb 12942 pipe_config = intel_modeset_compute_config(set->crtc, state);
20664591 12943 if (IS_ERR(pipe_config)) {
6ac0483b 12944 ret = PTR_ERR(pipe_config);
7cbf41d6 12945 goto out;
20664591 12946 }
50f52756 12947
1f9954d0
JB		 12948 intel_update_pipe_size(to_intel_crtc(set->crtc));
12949
bb546623
ACO		 12950 primary_plane_was_visible = primary_plane_visible(set->crtc);
12951
8c7b5ccb 12952 ret = intel_set_mode_with_config(set->crtc, pipe_config);
bb546623
ACO		 12953
12954 if (ret == 0 &&
12955 pipe_config->base.enable &&
12956 pipe_config->base.planes_changed &&
12957 !needs_modeset(&pipe_config->base)) {
3b150f08 12958 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
3b150f08
MR		 12959
12960 /*
12961 * We need to make sure the primary plane is re-enabled if it
12962 * has previously been turned off.
12963 */
bb546623
ACO		 12964 if (ret == 0 && !primary_plane_was_visible &&
12965 primary_plane_visible(set->crtc)) {
3b150f08 12966 WARN_ON(!intel_crtc->active);
87d4300a 12967 intel_post_enable_primary(set->crtc);
3b150f08
MR		 12968 }
12969
7ca51a3a
JB		 12970 /*
12971 * In the fastboot case this may be our only check of the
12972 * state after boot. It would be better to only do it on
12973 * the first update, but we don't have a nice way of doing that
12974 * (and really, set_config isn't used much for high freq page
12975 * flipping, so increasing its cost here shouldn't be a big
12976 * deal).
12977 */
d330a953 12978 if (i915.fastboot && ret == 0)
7ca51a3a 12979 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 12980 }
12981
2d05eae1 12982 if (ret) {
bf67dfeb
DV		 12983 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
12984 set->crtc->base.id, ret);
2d05eae1 12985 }
50f56119 12986
7cbf41d6 12987out:
2bfb4627
ACO		 12988 if (ret)
12989 drm_atomic_state_free(state);
50f56119
DV		 12990 return ret;
12991}
f6e5b160
CW		 12992
12993static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 12994 .gamma_set = intel_crtc_gamma_set,
50f56119 12995 .set_config = intel_crtc_set_config,
f6e5b160
CW		 12996 .destroy = intel_crtc_destroy,
12997 .page_flip = intel_crtc_page_flip,
1356837e
MR		 12998 .atomic_duplicate_state = intel_crtc_duplicate_state,
12999 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 13000};
13001
5358901f
DV		 13002static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
13003 struct intel_shared_dpll *pll,
13004 struct intel_dpll_hw_state *hw_state)
ee7b9f93 13005{
5358901f 13006 uint32_t val;
ee7b9f93 13007
f458ebbc 13008 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 13009 return false;
13010
5358901f 13011 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 13012 hw_state->dpll = val;
13013 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
13014 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 13015
13016 return val & DPLL_VCO_ENABLE;
13017}
13018
15bdd4cf
DV		 13019static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
13020 struct intel_shared_dpll *pll)
13021{
3e369b76
ACO		 13022 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
13023 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 13024}
13025
e7b903d2
DV		 13026static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
13027 struct intel_shared_dpll *pll)
13028{
e7b903d2 13029 /* PCH refclock must be enabled first */
89eff4be 13030 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 13031
3e369b76 13032 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 13033
13034 /* Wait for the clocks to stabilize. */
13035 POSTING_READ(PCH_DPLL(pll->id));
13036 udelay(150);
13037
13038 /* The pixel multiplier can only be updated once the
13039 * DPLL is enabled and the clocks are stable.
13040 *
13041 * So write it again.
13042 */
3e369b76 13043 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 13044 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13045 udelay(200);
13046}
13047
13048static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
13049 struct intel_shared_dpll *pll)
13050{
13051 struct drm_device *dev = dev_priv->dev;
13052 struct intel_crtc *crtc;
e7b903d2
DV		 13053
13054 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 13055 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 13056 if (intel_crtc_to_shared_dpll(crtc) == pll)
13057 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 13058 }
13059
15bdd4cf
DV		 13060 I915_WRITE(PCH_DPLL(pll->id), 0);
13061 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 13062 udelay(200);
13063}
13064
46edb027
DV		 13065static char *ibx_pch_dpll_names[] = {
13066 "PCH DPLL A",
13067 "PCH DPLL B",
13068};
13069
7c74ade1 13070static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 13071{
e7b903d2 13072 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 13073 int i;
13074
7c74ade1 13075 dev_priv->num_shared_dpll = 2;
ee7b9f93 13076
e72f9fbf 13077 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 13078 dev_priv->shared_dplls[i].id = i;
13079 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 13080 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 13081 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
13082 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 13083 dev_priv->shared_dplls[i].get_hw_state =
13084 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 13085 }
13086}
13087
7c74ade1
DV		 13088static void intel_shared_dpll_init(struct drm_device *dev)
13089{
e7b903d2 13090 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 13091
9cd86933
DV		 13092 if (HAS_DDI(dev))
13093 intel_ddi_pll_init(dev);
13094 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 13095 ibx_pch_dpll_init(dev);
13096 else
13097 dev_priv->num_shared_dpll = 0;
13098
13099 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 13100}
13101
1fc0a8f7
TU		 13102/**
13103 * intel_wm_need_update - Check whether watermarks need updating
13104 * @plane: drm plane
13105 * @state: new plane state
13106 *
13107 * Check current plane state versus the new one to determine whether
13108 * watermarks need to be recalculated.
13109 *
13110 * Returns true or false.
13111 */
13112bool intel_wm_need_update(struct drm_plane *plane,
13113 struct drm_plane_state *state)
13114{
13115 /* Update watermarks on tiling changes. */
13116 if (!plane->state->fb || !state->fb ||
13117 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
13118 plane->state->rotation != state->rotation)
13119 return true;
13120
13121 return false;
13122}
13123
6beb8c23
MR		 13124/**
13125 * intel_prepare_plane_fb - Prepare fb for usage on plane
13126 * @plane: drm plane to prepare for
13127 * @fb: framebuffer to prepare for presentation
13128 *
13129 * Prepares a framebuffer for usage on a display plane. Generally this
13130 * involves pinning the underlying object and updating the frontbuffer tracking
13131 * bits. Some older platforms need special physical address handling for
13132 * cursor planes.
13133 *
13134 * Returns 0 on success, negative error code on failure.
13135 */
13136int
13137intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13138 struct drm_framebuffer *fb,
13139 const struct drm_plane_state *new_state)
465c120c
MR		 13140{
13141 struct drm_device *dev = plane->dev;
6beb8c23
MR		 13142 struct intel_plane *intel_plane = to_intel_plane(plane);
13143 enum pipe pipe = intel_plane->pipe;
13144 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13145 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
13146 unsigned frontbuffer_bits = 0;
13147 int ret = 0;
465c120c 13148
ea2c67bb 13149 if (!obj)
465c120c
MR		 13150 return 0;
13151
6beb8c23
MR		 13152 switch (plane->type) {
13153 case DRM_PLANE_TYPE_PRIMARY:
13154 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
13155 break;
13156 case DRM_PLANE_TYPE_CURSOR:
13157 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
13158 break;
13159 case DRM_PLANE_TYPE_OVERLAY:
13160 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
13161 break;
13162 }
465c120c 13163
6beb8c23 13164 mutex_lock(&dev->struct_mutex);
465c120c 13165
6beb8c23
MR		 13166 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
13167 INTEL_INFO(dev)->cursor_needs_physical) {
13168 int align = IS_I830(dev) ? 16 * 1024 : 256;
13169 ret = i915_gem_object_attach_phys(obj, align);
13170 if (ret)
13171 DRM_DEBUG_KMS("failed to attach phys object\n");
13172 } else {
82bc3b2d 13173 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 13174 }
465c120c 13175
6beb8c23
MR		 13176 if (ret == 0)
13177 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 13178
4c34574f 13179 mutex_unlock(&dev->struct_mutex);
465c120c 13180
6beb8c23
MR		 13181 return ret;
13182}
13183
38f3ce3a
MR		 13184/**
13185 * intel_cleanup_plane_fb - Cleans up an fb after plane use
13186 * @plane: drm plane to clean up for
13187 * @fb: old framebuffer that was on plane
13188 *
13189 * Cleans up a framebuffer that has just been removed from a plane.
13190 */
13191void
13192intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 13193 struct drm_framebuffer *fb,
13194 const struct drm_plane_state *old_state)
38f3ce3a
MR		 13195{
13196 struct drm_device *dev = plane->dev;
13197 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
13198
13199 if (WARN_ON(!obj))
13200 return;
13201
13202 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
13203 !INTEL_INFO(dev)->cursor_needs_physical) {
13204 mutex_lock(&dev->struct_mutex);
82bc3b2d 13205 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 13206 mutex_unlock(&dev->struct_mutex);
13207 }
465c120c
MR		 13208}
13209
6156a456
CK		 13210int
13211skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
13212{
13213 int max_scale;
13214 struct drm_device *dev;
13215 struct drm_i915_private *dev_priv;
13216 int crtc_clock, cdclk;
13217
13218 if (!intel_crtc || !crtc_state)
13219 return DRM_PLANE_HELPER_NO_SCALING;
13220
13221 dev = intel_crtc->base.dev;
13222 dev_priv = dev->dev_private;
13223 crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
13224 cdclk = dev_priv->display.get_display_clock_speed(dev);
13225
13226 if (!crtc_clock || !cdclk)
13227 return DRM_PLANE_HELPER_NO_SCALING;
13228
13229 /*
13230 * skl max scale is lower of:
13231 * close to 3 but not 3, -1 is for that purpose
13232 * or
13233 * cdclk/crtc_clock
13234 */
13235 max_scale = min((1 << 16) * 3 - 1, (1 << 8) * ((cdclk << 8) / crtc_clock));
13236
13237 return max_scale;
13238}
13239
465c120c 13240static int
3c692a41
GP		 13241intel_check_primary_plane(struct drm_plane *plane,
13242 struct intel_plane_state *state)
13243{
32b7eeec
MR		 13244 struct drm_device *dev = plane->dev;
13245 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 13246 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13247 struct intel_crtc *intel_crtc;
6156a456 13248 struct intel_crtc_state *crtc_state;
2b875c22 13249 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 13250 struct drm_rect *dest = &state->dst;
13251 struct drm_rect *src = &state->src;
13252 const struct drm_rect *clip = &state->clip;
d8106366 13253 bool can_position = false;
6156a456
CK		 13254 int max_scale = DRM_PLANE_HELPER_NO_SCALING;
13255 int min_scale = DRM_PLANE_HELPER_NO_SCALING;
465c120c
MR		 13256 int ret;
13257
ea2c67bb
MR		 13258 crtc = crtc ? crtc : plane->crtc;
13259 intel_crtc = to_intel_crtc(crtc);
6156a456
CK		 13260 crtc_state = state->base.state ?
13261 intel_atomic_get_crtc_state(state->base.state, intel_crtc) : NULL;
ea2c67bb 13262
6156a456
CK		 13263 if (INTEL_INFO(dev)->gen >= 9) {
13264 min_scale = 1;
13265 max_scale = skl_max_scale(intel_crtc, crtc_state);
d8106366 13266 can_position = true;
6156a456 13267 }
d8106366 13268
c59cb179
MR		 13269 ret = drm_plane_helper_check_update(plane, crtc, fb,
13270 src, dest, clip,
6156a456
CK		 13271 min_scale,
13272 max_scale,
d8106366
SJ		 13273 can_position, true,
13274 &state->visible);
c59cb179
MR		 13275 if (ret)
13276 return ret;
465c120c 13277
32b7eeec 13278 if (intel_crtc->active) {
b70709a6
ML		 13279 struct intel_plane_state *old_state =
13280 to_intel_plane_state(plane->state);
13281
32b7eeec
MR		 13282 intel_crtc->atomic.wait_for_flips = true;
13283
13284 /*
13285 * FBC does not work on some platforms for rotated
13286 * planes, so disable it when rotation is not 0 and
13287 * update it when rotation is set back to 0.
13288 *
13289 * FIXME: This is redundant with the fbc update done in
13290 * the primary plane enable function except that that
13291 * one is done too late. We eventually need to unify
13292 * this.
13293 */
b70709a6 13294 if (state->visible &&
32b7eeec 13295 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 13296 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 13297 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 13298 intel_crtc->atomic.disable_fbc = true;
13299 }
13300
b70709a6 13301 if (state->visible && !old_state->visible) {
32b7eeec
MR		 13302 /*
13303 * BDW signals flip done immediately if the plane
13304 * is disabled, even if the plane enable is already
13305 * armed to occur at the next vblank :(
13306 */
b70709a6 13307 if (IS_BROADWELL(dev))
32b7eeec
MR		 13308 intel_crtc->atomic.wait_vblank = true;
13309 }
13310
13311 intel_crtc->atomic.fb_bits |=
13312 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
13313
13314 intel_crtc->atomic.update_fbc = true;
0fda6568 13315
1fc0a8f7 13316 if (intel_wm_need_update(plane, &state->base))
0fda6568 13317 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 13318 }
13319
6156a456
CK		 13320 if (INTEL_INFO(dev)->gen >= 9) {
13321 ret = skl_update_scaler_users(intel_crtc, crtc_state,
13322 to_intel_plane(plane), state, 0);
13323 if (ret)
13324 return ret;
13325 }
13326
14af293f
GP		 13327 return 0;
13328}
13329
13330static void
13331intel_commit_primary_plane(struct drm_plane *plane,
13332 struct intel_plane_state *state)
13333{
2b875c22
MR		 13334 struct drm_crtc *crtc = state->base.crtc;
13335 struct drm_framebuffer *fb = state->base.fb;
13336 struct drm_device *dev = plane->dev;
14af293f 13337 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 13338 struct intel_crtc *intel_crtc;
14af293f
GP		 13339 struct drm_rect *src = &state->src;
13340
ea2c67bb
MR		 13341 crtc = crtc ? crtc : plane->crtc;
13342 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 13343
13344 plane->fb = fb;
9dc806fc
MR		 13345 crtc->x = src->x1 >> 16;
13346 crtc->y = src->y1 >> 16;
ccc759dc 13347
ccc759dc 13348 if (intel_crtc->active) {
27321ae8 13349 if (state->visible)
ccc759dc
GP		 13350 /* FIXME: kill this fastboot hack */
13351 intel_update_pipe_size(intel_crtc);
465c120c 13352
27321ae8
ML		 13353 dev_priv->display.update_primary_plane(crtc, plane->fb,
13354 crtc->x, crtc->y);
ccc759dc 13355 }
465c120c
MR		 13356}
13357
a8ad0d8e
ML		 13358static void
13359intel_disable_primary_plane(struct drm_plane *plane,
13360 struct drm_crtc *crtc,
13361 bool force)
13362{
13363 struct drm_device *dev = plane->dev;
13364 struct drm_i915_private *dev_priv = dev->dev_private;
13365
a8ad0d8e
ML		 13366 dev_priv->display.update_primary_plane(crtc, NULL, 0, 0);
13367}
13368
32b7eeec 13369static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 13370{
32b7eeec 13371 struct drm_device *dev = crtc->dev;
140fd38d 13372 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 13373 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 13374 struct intel_plane *intel_plane;
13375 struct drm_plane *p;
13376 unsigned fb_bits = 0;
13377
13378 /* Track fb's for any planes being disabled */
13379 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
13380 intel_plane = to_intel_plane(p);
13381
13382 if (intel_crtc->atomic.disabled_planes &
13383 (1 << drm_plane_index(p))) {
13384 switch (p->type) {
13385 case DRM_PLANE_TYPE_PRIMARY:
13386 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
13387 break;
13388 case DRM_PLANE_TYPE_CURSOR:
13389 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
13390 break;
13391 case DRM_PLANE_TYPE_OVERLAY:
13392 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
13393 break;
13394 }
3c692a41 13395
ea2c67bb
MR		 13396 mutex_lock(&dev->struct_mutex);
13397 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
13398 mutex_unlock(&dev->struct_mutex);
13399 }
13400 }
3c692a41 13401
32b7eeec
MR		 13402 if (intel_crtc->atomic.wait_for_flips)
13403 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 13404
32b7eeec
MR		 13405 if (intel_crtc->atomic.disable_fbc)
13406 intel_fbc_disable(dev);
3c692a41 13407
32b7eeec
MR		 13408 if (intel_crtc->atomic.pre_disable_primary)
13409 intel_pre_disable_primary(crtc);
3c692a41 13410
32b7eeec
MR		 13411 if (intel_crtc->atomic.update_wm)
13412 intel_update_watermarks(crtc);
3c692a41 13413
32b7eeec 13414 intel_runtime_pm_get(dev_priv);
3c692a41 13415
c34c9ee4
MR		 13416 /* Perform vblank evasion around commit operation */
13417 if (intel_crtc->active)
13418 intel_crtc->atomic.evade =
13419 intel_pipe_update_start(intel_crtc,
13420 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 13421}
13422
13423static void intel_finish_crtc_commit(struct drm_crtc *crtc)
13424{
13425 struct drm_device *dev = crtc->dev;
13426 struct drm_i915_private *dev_priv = dev->dev_private;
13427 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13428 struct drm_plane *p;
13429
c34c9ee4
MR		 13430 if (intel_crtc->atomic.evade)
13431 intel_pipe_update_end(intel_crtc,
13432 intel_crtc->atomic.start_vbl_count);
3c692a41 13433
140fd38d 13434 intel_runtime_pm_put(dev_priv);
3c692a41 13435
32b7eeec
MR		 13436 if (intel_crtc->atomic.wait_vblank)
13437 intel_wait_for_vblank(dev, intel_crtc->pipe);
13438
13439 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
13440
13441 if (intel_crtc->atomic.update_fbc) {
ccc759dc 13442 mutex_lock(&dev->struct_mutex);
7ff0ebcc 13443 intel_fbc_update(dev);
ccc759dc 13444 mutex_unlock(&dev->struct_mutex);
38f3ce3a 13445 }
3c692a41 13446
32b7eeec
MR		 13447 if (intel_crtc->atomic.post_enable_primary)
13448 intel_post_enable_primary(crtc);
3c692a41 13449
32b7eeec
MR		 13450 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
13451 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
13452 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
13453 false, false);
13454
13455 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 13456}
13457
cf4c7c12 13458/**
4a3b8769
MR		 13459 * intel_plane_destroy - destroy a plane
13460 * @plane: plane to destroy
cf4c7c12 13461 *
4a3b8769
MR		 13462 * Common destruction function for all types of planes (primary, cursor,
13463 * sprite).
cf4c7c12 13464 */
4a3b8769 13465void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 13466{
13467 struct intel_plane *intel_plane = to_intel_plane(plane);
13468 drm_plane_cleanup(plane);
13469 kfree(intel_plane);
13470}
13471
65a3fea0 13472const struct drm_plane_funcs intel_plane_funcs = {
70a101f8
MR		 13473 .update_plane = drm_atomic_helper_update_plane,
13474 .disable_plane = drm_atomic_helper_disable_plane,
3d7d6510 13475 .destroy = intel_plane_destroy,
c196e1d6 13476 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 13477 .atomic_get_property = intel_plane_atomic_get_property,
13478 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 13479 .atomic_duplicate_state = intel_plane_duplicate_state,
13480 .atomic_destroy_state = intel_plane_destroy_state,
13481
465c120c
MR		 13482};
13483
13484static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
13485 int pipe)
13486{
13487 struct intel_plane *primary;
8e7d688b 13488 struct intel_plane_state *state;
465c120c
MR		 13489 const uint32_t *intel_primary_formats;
13490 int num_formats;
13491
13492 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
13493 if (primary == NULL)
13494 return NULL;
13495
8e7d688b
MR		 13496 state = intel_create_plane_state(&primary->base);
13497 if (!state) {
ea2c67bb
MR		 13498 kfree(primary);
13499 return NULL;
13500 }
8e7d688b 13501 primary->base.state = &state->base;
ea2c67bb 13502
465c120c
MR		 13503 primary->can_scale = false;
13504 primary->max_downscale = 1;
6156a456
CK		 13505 if (INTEL_INFO(dev)->gen >= 9) {
13506 primary->can_scale = true;
af99ceda 13507 state->scaler_id = -1;
6156a456 13508 }
465c120c
MR		 13509 primary->pipe = pipe;
13510 primary->plane = pipe;
c59cb179
MR		 13511 primary->check_plane = intel_check_primary_plane;
13512 primary->commit_plane = intel_commit_primary_plane;
a8ad0d8e 13513 primary->disable_plane = intel_disable_primary_plane;
08e221fb 13514 primary->ckey.flags = I915_SET_COLORKEY_NONE;
465c120c
MR		 13515 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
13516 primary->plane = !pipe;
13517
6c0fd451
DL		 13518 if (INTEL_INFO(dev)->gen >= 9) {
13519 intel_primary_formats = skl_primary_formats;
13520 num_formats = ARRAY_SIZE(skl_primary_formats);
13521 } else if (INTEL_INFO(dev)->gen >= 4) {
568db4f2
DL		 13522 intel_primary_formats = i965_primary_formats;
13523 num_formats = ARRAY_SIZE(i965_primary_formats);
6c0fd451
DL		 13524 } else {
13525 intel_primary_formats = i8xx_primary_formats;
13526 num_formats = ARRAY_SIZE(i8xx_primary_formats);
465c120c
MR		 13527 }
13528
13529 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 13530 &intel_plane_funcs,
465c120c
MR		 13531 intel_primary_formats, num_formats,
13532 DRM_PLANE_TYPE_PRIMARY);
48404c1e 13533
3b7a5119
SJ		 13534 if (INTEL_INFO(dev)->gen >= 4)
13535 intel_create_rotation_property(dev, primary);
48404c1e 13536
ea2c67bb
MR		 13537 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
13538
465c120c
MR		 13539 return &primary->base;
13540}
13541
3b7a5119
SJ		 13542void intel_create_rotation_property(struct drm_device *dev, struct intel_plane *plane)
13543{
13544 if (!dev->mode_config.rotation_property) {
13545 unsigned long flags = BIT(DRM_ROTATE_0) |
13546 BIT(DRM_ROTATE_180);
13547
13548 if (INTEL_INFO(dev)->gen >= 9)
13549 flags |= BIT(DRM_ROTATE_90) | BIT(DRM_ROTATE_270);
13550
13551 dev->mode_config.rotation_property =
13552 drm_mode_create_rotation_property(dev, flags);
13553 }
13554 if (dev->mode_config.rotation_property)
13555 drm_object_attach_property(&plane->base.base,
13556 dev->mode_config.rotation_property,
13557 plane->base.state->rotation);
13558}
13559
3d7d6510 13560static int
852e787c
GP		 13561intel_check_cursor_plane(struct drm_plane *plane,
13562 struct intel_plane_state *state)
3d7d6510 13563{
2b875c22 13564 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 13565 struct drm_device *dev = plane->dev;
2b875c22 13566 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 13567 struct drm_rect *dest = &state->dst;
13568 struct drm_rect *src = &state->src;
13569 const struct drm_rect *clip = &state->clip;
757f9a3e 13570 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 13571 struct intel_crtc *intel_crtc;
757f9a3e
GP		 13572 unsigned stride;
13573 int ret;
3d7d6510 13574
ea2c67bb
MR		 13575 crtc = crtc ? crtc : plane->crtc;
13576 intel_crtc = to_intel_crtc(crtc);
13577
757f9a3e 13578 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 13579 src, dest, clip,
3d7d6510
MR		 13580 DRM_PLANE_HELPER_NO_SCALING,
13581 DRM_PLANE_HELPER_NO_SCALING,
852e787c 13582 true, true, &state->visible);
757f9a3e
GP		 13583 if (ret)
13584 return ret;
13585
13586
13587 /* if we want to turn off the cursor ignore width and height */
13588 if (!obj)
32b7eeec 13589 goto finish;
757f9a3e 13590
757f9a3e 13591 /* Check for which cursor types we support */
ea2c67bb
MR		 13592 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
13593 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
13594 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 13595 return -EINVAL;
13596 }
13597
ea2c67bb
MR		 13598 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
13599 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 13600 DRM_DEBUG_KMS("buffer is too small\n");
13601 return -ENOMEM;
13602 }
13603
3a656b54 13604 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 13605 DRM_DEBUG_KMS("cursor cannot be tiled\n");
13606 ret = -EINVAL;
13607 }
757f9a3e 13608
32b7eeec
MR		 13609finish:
13610 if (intel_crtc->active) {
3749f463 13611 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 13612 intel_crtc->atomic.update_wm = true;
13613
13614 intel_crtc->atomic.fb_bits |=
13615 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
13616 }
13617
757f9a3e 13618 return ret;
852e787c 13619}
3d7d6510 13620
a8ad0d8e
ML		 13621static void
13622intel_disable_cursor_plane(struct drm_plane *plane,
13623 struct drm_crtc *crtc,
13624 bool force)
13625{
13626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
13627
13628 if (!force) {
13629 plane->fb = NULL;
13630 intel_crtc->cursor_bo = NULL;
13631 intel_crtc->cursor_addr = 0;
13632 }
13633
13634 intel_crtc_update_cursor(crtc, false);
13635}
13636
f4a2cf29 13637static void
852e787c
GP		 13638intel_commit_cursor_plane(struct drm_plane *plane,
13639 struct intel_plane_state *state)
13640{
2b875c22 13641 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 13642 struct drm_device *dev = plane->dev;
13643 struct intel_crtc *intel_crtc;
2b875c22 13644 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 13645 uint32_t addr;
852e787c 13646
ea2c67bb
MR		 13647 crtc = crtc ? crtc : plane->crtc;
13648 intel_crtc = to_intel_crtc(crtc);
13649
2b875c22 13650 plane->fb = state->base.fb;
ea2c67bb
MR		 13651 crtc->cursor_x = state->base.crtc_x;
13652 crtc->cursor_y = state->base.crtc_y;
13653
a912f12f
GP		 13654 if (intel_crtc->cursor_bo == obj)
13655 goto update;
4ed91096 13656
f4a2cf29 13657 if (!obj)
a912f12f 13658 addr = 0;
f4a2cf29 13659 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 13660 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 13661 else
a912f12f 13662 addr = obj->phys_handle->busaddr;
852e787c 13663
a912f12f
GP		 13664 intel_crtc->cursor_addr = addr;
13665 intel_crtc->cursor_bo = obj;
13666update:
852e787c 13667
32b7eeec 13668 if (intel_crtc->active)
a912f12f 13669 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 13670}
13671
3d7d6510
MR		 13672static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
13673 int pipe)
13674{
13675 struct intel_plane *cursor;
8e7d688b 13676 struct intel_plane_state *state;
3d7d6510
MR		 13677
13678 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
13679 if (cursor == NULL)
13680 return NULL;
13681
8e7d688b
MR		 13682 state = intel_create_plane_state(&cursor->base);
13683 if (!state) {
ea2c67bb
MR		 13684 kfree(cursor);
13685 return NULL;
13686 }
8e7d688b 13687 cursor->base.state = &state->base;
ea2c67bb 13688
3d7d6510
MR		 13689 cursor->can_scale = false;
13690 cursor->max_downscale = 1;
13691 cursor->pipe = pipe;
13692 cursor->plane = pipe;
c59cb179
MR		 13693 cursor->check_plane = intel_check_cursor_plane;
13694 cursor->commit_plane = intel_commit_cursor_plane;
a8ad0d8e 13695 cursor->disable_plane = intel_disable_cursor_plane;
3d7d6510
MR		 13696
13697 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 13698 &intel_plane_funcs,
3d7d6510
MR		 13699 intel_cursor_formats,
13700 ARRAY_SIZE(intel_cursor_formats),
13701 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 13702
13703 if (INTEL_INFO(dev)->gen >= 4) {
13704 if (!dev->mode_config.rotation_property)
13705 dev->mode_config.rotation_property =
13706 drm_mode_create_rotation_property(dev,
13707 BIT(DRM_ROTATE_0) |
13708 BIT(DRM_ROTATE_180));
13709 if (dev->mode_config.rotation_property)
13710 drm_object_attach_property(&cursor->base.base,
13711 dev->mode_config.rotation_property,
8e7d688b 13712 state->base.rotation);
4398ad45
VS		 13713 }
13714
af99ceda
CK		 13715 if (INTEL_INFO(dev)->gen >=9)
13716 state->scaler_id = -1;
13717
ea2c67bb
MR		 13718 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
13719
3d7d6510
MR		 13720 return &cursor->base;
13721}
13722
549e2bfb
CK		 13723static void skl_init_scalers(struct drm_device *dev, struct intel_crtc *intel_crtc,
13724 struct intel_crtc_state *crtc_state)
13725{
13726 int i;
13727 struct intel_scaler *intel_scaler;
13728 struct intel_crtc_scaler_state *scaler_state = &crtc_state->scaler_state;
13729
13730 for (i = 0; i < intel_crtc->num_scalers; i++) {
13731 intel_scaler = &scaler_state->scalers[i];
13732 intel_scaler->in_use = 0;
13733 intel_scaler->id = i;
13734
13735 intel_scaler->mode = PS_SCALER_MODE_DYN;
13736 }
13737
13738 scaler_state->scaler_id = -1;
13739}
13740
b358d0a6 13741static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 13742{
fbee40df 13743 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 13744 struct intel_crtc *intel_crtc;
f5de6e07 13745 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 13746 struct drm_plane *primary = NULL;
13747 struct drm_plane *cursor = NULL;
465c120c 13748 int i, ret;
79e53945 13749
955382f3 13750 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 13751 if (intel_crtc == NULL)
13752 return;
13753
f5de6e07
ACO		 13754 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
13755 if (!crtc_state)
13756 goto fail;
550acefd
ACO		 13757 intel_crtc->config = crtc_state;
13758 intel_crtc->base.state = &crtc_state->base;
07878248 13759 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 13760
549e2bfb
CK		 13761 /* initialize shared scalers */
13762 if (INTEL_INFO(dev)->gen >= 9) {
13763 if (pipe == PIPE_C)
13764 intel_crtc->num_scalers = 1;
13765 else
13766 intel_crtc->num_scalers = SKL_NUM_SCALERS;
13767
13768 skl_init_scalers(dev, intel_crtc, crtc_state);
13769 }
13770
465c120c 13771 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 13772 if (!primary)
13773 goto fail;
13774
13775 cursor = intel_cursor_plane_create(dev, pipe);
13776 if (!cursor)
13777 goto fail;
13778
465c120c 13779 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 13780 cursor, &intel_crtc_funcs);
13781 if (ret)
13782 goto fail;
79e53945
JB		 13783
13784 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 13785 for (i = 0; i < 256; i++) {
13786 intel_crtc->lut_r[i] = i;
13787 intel_crtc->lut_g[i] = i;
13788 intel_crtc->lut_b[i] = i;
13789 }
13790
1f1c2e24
VS		 13791 /*
13792 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 13793 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 13794 */
80824003
JB		 13795 intel_crtc->pipe = pipe;
13796 intel_crtc->plane = pipe;
3a77c4c4 13797 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 13798 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 13799 intel_crtc->plane = !pipe;
80824003
JB		 13800 }
13801
4b0e333e
CW		 13802 intel_crtc->cursor_base = ~0;
13803 intel_crtc->cursor_cntl = ~0;
dc41c154 13804 intel_crtc->cursor_size = ~0;
8d7849db 13805
22fd0fab
JB		 13806 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
13807 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
13808 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
13809 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
13810
79e53945 13811 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 13812
13813 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 13814 return;
13815
13816fail:
13817 if (primary)
13818 drm_plane_cleanup(primary);
13819 if (cursor)
13820 drm_plane_cleanup(cursor);
f5de6e07 13821 kfree(crtc_state);
3d7d6510 13822 kfree(intel_crtc);
79e53945
JB		 13823}
13824
752aa88a
JB		 13825enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
13826{
13827 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 13828 struct drm_device *dev = connector->base.dev;
752aa88a 13829
51fd371b 13830 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 13831
d3babd3f 13832 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 13833 return INVALID_PIPE;
13834
13835 return to_intel_crtc(encoder->crtc)->pipe;
13836}
13837
08d7b3d1 13838int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 13839 struct drm_file *file)
08d7b3d1 13840{
08d7b3d1 13841 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 13842 struct drm_crtc *drmmode_crtc;
c05422d5 13843 struct intel_crtc *crtc;
08d7b3d1 13844
7707e653 13845 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 13846
7707e653 13847 if (!drmmode_crtc) {
08d7b3d1 13848 DRM_ERROR("no such CRTC id\n");
3f2c2057 13849 return -ENOENT;
08d7b3d1
CW		 13850 }
13851
7707e653 13852 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 13853 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 13854
c05422d5 13855 return 0;
08d7b3d1
CW		 13856}
13857
66a9278e 13858static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 13859{
66a9278e
DV		 13860 struct drm_device *dev = encoder->base.dev;
13861 struct intel_encoder *source_encoder;
79e53945 13862 int index_mask = 0;
79e53945
JB		 13863 int entry = 0;
13864
b2784e15 13865 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 13866 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 13867 index_mask |= (1 << entry);
13868
79e53945
JB		 13869 entry++;
13870 }
4ef69c7a 13871
79e53945
JB		 13872 return index_mask;
13873}
13874
4d302442
CW		 13875static bool has_edp_a(struct drm_device *dev)
13876{
13877 struct drm_i915_private *dev_priv = dev->dev_private;
13878
13879 if (!IS_MOBILE(dev))
13880 return false;
13881
13882 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
13883 return false;
13884
e3589908 13885 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 13886 return false;
13887
13888 return true;
13889}
13890
84b4e042
JB		 13891static bool intel_crt_present(struct drm_device *dev)
13892{
13893 struct drm_i915_private *dev_priv = dev->dev_private;
13894
884497ed
DL		 13895 if (INTEL_INFO(dev)->gen >= 9)
13896 return false;
13897
cf404ce4 13898 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 13899 return false;
13900
13901 if (IS_CHERRYVIEW(dev))
13902 return false;
13903
13904 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
13905 return false;
13906
13907 return true;
13908}
13909
79e53945
JB		 13910static void intel_setup_outputs(struct drm_device *dev)
13911{
725e30ad 13912 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 13913 struct intel_encoder *encoder;
cb0953d7 13914 bool dpd_is_edp = false;
79e53945 13915
c9093354 13916 intel_lvds_init(dev);
79e53945 13917
84b4e042 13918 if (intel_crt_present(dev))
79935fca 13919 intel_crt_init(dev);
cb0953d7 13920
c776eb2e
VK		 13921 if (IS_BROXTON(dev)) {
13922 /*
13923 * FIXME: Broxton doesn't support port detection via the
13924 * DDI_BUF_CTL_A or SFUSE_STRAP registers, find another way to
13925 * detect the ports.
13926 */
13927 intel_ddi_init(dev, PORT_A);
13928 intel_ddi_init(dev, PORT_B);
13929 intel_ddi_init(dev, PORT_C);
13930 } else if (HAS_DDI(dev)) {
0e72a5b5
ED		 13931 int found;
13932
de31facd
JB		 13933 /*
13934 * Haswell uses DDI functions to detect digital outputs.
13935 * On SKL pre-D0 the strap isn't connected, so we assume
13936 * it's there.
13937 */
0e72a5b5 13938 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 13939 /* WaIgnoreDDIAStrap: skl */
13940 if (found ||
13941 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 13942 intel_ddi_init(dev, PORT_A);
13943
13944 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
13945 * register */
13946 found = I915_READ(SFUSE_STRAP);
13947
13948 if (found & SFUSE_STRAP_DDIB_DETECTED)
13949 intel_ddi_init(dev, PORT_B);
13950 if (found & SFUSE_STRAP_DDIC_DETECTED)
13951 intel_ddi_init(dev, PORT_C);
13952 if (found & SFUSE_STRAP_DDID_DETECTED)
13953 intel_ddi_init(dev, PORT_D);
13954 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 13955 int found;
5d8a7752 13956 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 13957
13958 if (has_edp_a(dev))
13959 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 13960
dc0fa718 13961 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 13962 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 13963 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 13964 if (!found)
e2debe91 13965 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 13966 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 13967 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 13968 }
13969
dc0fa718 13970 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 13971 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 13972
dc0fa718 13973 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 13974 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 13975
5eb08b69 13976 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 13977 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 13978
270b3042 13979 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 13980 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 13981 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 13982 /*
13983 * The DP_DETECTED bit is the latched state of the DDC
13984 * SDA pin at boot. However since eDP doesn't require DDC
13985 * (no way to plug in a DP->HDMI dongle) the DDC pins for
13986 * eDP ports may have been muxed to an alternate function.
13987 * Thus we can't rely on the DP_DETECTED bit alone to detect
13988 * eDP ports. Consult the VBT as well as DP_DETECTED to
13989 * detect eDP ports.
13990 */
d2182a66
VS		 13991 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
13992 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 13993 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
13994 PORT_B);
e17ac6db
VS		 13995 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
13996 intel_dp_is_edp(dev, PORT_B))
13997 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 13998
d2182a66
VS		 13999 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
14000 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 14001 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
14002 PORT_C);
e17ac6db
VS		 14003 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
14004 intel_dp_is_edp(dev, PORT_C))
14005 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 14006
9418c1f1 14007 if (IS_CHERRYVIEW(dev)) {
e17ac6db 14008 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 14009 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
14010 PORT_D);
e17ac6db
VS		 14011 /* eDP not supported on port D, so don't check VBT */
14012 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
14013 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 14014 }
14015
3cfca973 14016 intel_dsi_init(dev);
103a196f 14017 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 14018 bool found = false;
7d57382e 14019
e2debe91 14020 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14021 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 14022 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 14023 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
14024 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 14025 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 14026 }
27185ae1 14027
e7281eab 14028 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14029 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 14030 }
13520b05
KH		 14031
14032 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 14033
e2debe91 14034 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 14035 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 14036 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 14037 }
27185ae1 14038
e2debe91 14039 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 14040
b01f2c3a
JB		 14041 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
14042 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 14043 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 14044 }
e7281eab 14045 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 14046 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 14047 }
27185ae1 14048
b01f2c3a 14049 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 14050 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 14051 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 14052 } else if (IS_GEN2(dev))
79e53945
JB		 14053 intel_dvo_init(dev);
14054
103a196f 14055 if (SUPPORTS_TV(dev))
79e53945
JB		 14056 intel_tv_init(dev);
14057
0bc12bcb 14058 intel_psr_init(dev);
7c8f8a70 14059
b2784e15 14060 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 14061 encoder->base.possible_crtcs = encoder->crtc_mask;
14062 encoder->base.possible_clones =
66a9278e 14063 intel_encoder_clones(encoder);
79e53945 14064 }
47356eb6 14065
dde86e2d 14066 intel_init_pch_refclk(dev);
270b3042
DV		 14067
14068 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 14069}
14070
14071static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
14072{
60a5ca01 14073 struct drm_device *dev = fb->dev;
79e53945 14074 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 14075
ef2d633e 14076 drm_framebuffer_cleanup(fb);
60a5ca01 14077 mutex_lock(&dev->struct_mutex);
ef2d633e 14078 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 14079 drm_gem_object_unreference(&intel_fb->obj->base);
14080 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14081 kfree(intel_fb);
14082}
14083
14084static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 14085 struct drm_file *file,
79e53945
JB		 14086 unsigned int *handle)
14087{
14088 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 14089 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 14090
05394f39 14091 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 14092}
14093
14094static const struct drm_framebuffer_funcs intel_fb_funcs = {
14095 .destroy = intel_user_framebuffer_destroy,
14096 .create_handle = intel_user_framebuffer_create_handle,
14097};
14098
b321803d
DL		 14099static
14100u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
14101 uint32_t pixel_format)
14102{
14103 u32 gen = INTEL_INFO(dev)->gen;
14104
14105 if (gen >= 9) {
14106 /* "The stride in bytes must not exceed the of the size of 8K
14107 * pixels and 32K bytes."
14108 */
14109 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
14110 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
14111 return 32*1024;
14112 } else if (gen >= 4) {
14113 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14114 return 16*1024;
14115 else
14116 return 32*1024;
14117 } else if (gen >= 3) {
14118 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
14119 return 8*1024;
14120 else
14121 return 16*1024;
14122 } else {
14123 /* XXX DSPC is limited to 4k tiled */
14124 return 8*1024;
14125 }
14126}
14127
b5ea642a
DV		 14128static int intel_framebuffer_init(struct drm_device *dev,
14129 struct intel_framebuffer *intel_fb,
14130 struct drm_mode_fb_cmd2 *mode_cmd,
14131 struct drm_i915_gem_object *obj)
79e53945 14132{
6761dd31 14133 unsigned int aligned_height;
79e53945 14134 int ret;
b321803d 14135 u32 pitch_limit, stride_alignment;
79e53945 14136
dd4916c5
DV		 14137 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
14138
2a80eada
DV		 14139 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
14140 /* Enforce that fb modifier and tiling mode match, but only for
14141 * X-tiled. This is needed for FBC. */
14142 if (!!(obj->tiling_mode == I915_TILING_X) !=
14143 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
14144 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
14145 return -EINVAL;
14146 }
14147 } else {
14148 if (obj->tiling_mode == I915_TILING_X)
14149 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
14150 else if (obj->tiling_mode == I915_TILING_Y) {
14151 DRM_DEBUG("No Y tiling for legacy addfb\n");
14152 return -EINVAL;
14153 }
14154 }
14155
9a8f0a12
TU		 14156 /* Passed in modifier sanity checking. */
14157 switch (mode_cmd->modifier[0]) {
14158 case I915_FORMAT_MOD_Y_TILED:
14159 case I915_FORMAT_MOD_Yf_TILED:
14160 if (INTEL_INFO(dev)->gen < 9) {
14161 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
14162 mode_cmd->modifier[0]);
14163 return -EINVAL;
14164 }
14165 case DRM_FORMAT_MOD_NONE:
14166 case I915_FORMAT_MOD_X_TILED:
14167 break;
14168 default:
c0f40428
JB		 14169 DRM_DEBUG("Unsupported fb modifier 0x%llx!\n",
14170 mode_cmd->modifier[0]);
57cd6508 14171 return -EINVAL;
c16ed4be 14172 }
57cd6508 14173
b321803d
DL		 14174 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
14175 mode_cmd->pixel_format);
14176 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
14177 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
14178 mode_cmd->pitches[0], stride_alignment);
57cd6508 14179 return -EINVAL;
c16ed4be 14180 }
57cd6508 14181
b321803d
DL		 14182 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
14183 mode_cmd->pixel_format);
a35cdaa0 14184 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 14185 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
14186 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 14187 "tiled" : "linear",
a35cdaa0 14188 mode_cmd->pitches[0], pitch_limit);
5d7bd705 14189 return -EINVAL;
c16ed4be 14190 }
5d7bd705 14191
2a80eada 14192 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 14193 mode_cmd->pitches[0] != obj->stride) {
14194 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
14195 mode_cmd->pitches[0], obj->stride);
5d7bd705 14196 return -EINVAL;
c16ed4be 14197 }
5d7bd705 14198
57779d06 14199 /* Reject formats not supported by any plane early. */
308e5bcb 14200 switch (mode_cmd->pixel_format) {
57779d06 14201 case DRM_FORMAT_C8:
04b3924d
VS		 14202 case DRM_FORMAT_RGB565:
14203 case DRM_FORMAT_XRGB8888:
14204 case DRM_FORMAT_ARGB8888:
57779d06
VS		 14205 break;
14206 case DRM_FORMAT_XRGB1555:
c16ed4be 14207 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 14208 DRM_DEBUG("unsupported pixel format: %s\n",
14209 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14210 return -EINVAL;
c16ed4be 14211 }
57779d06 14212 break;
57779d06 14213 case DRM_FORMAT_ABGR8888:
6c0fd451
DL		 14214 if (!IS_VALLEYVIEW(dev) && INTEL_INFO(dev)->gen < 9) {
14215 DRM_DEBUG("unsupported pixel format: %s\n",
14216 drm_get_format_name(mode_cmd->pixel_format));
14217 return -EINVAL;
14218 }
14219 break;
14220 case DRM_FORMAT_XBGR8888:
04b3924d 14221 case DRM_FORMAT_XRGB2101010:
57779d06 14222 case DRM_FORMAT_XBGR2101010:
c16ed4be 14223 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 14224 DRM_DEBUG("unsupported pixel format: %s\n",
14225 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14226 return -EINVAL;
c16ed4be 14227 }
b5626747 14228 break;
7531208b
DL		 14229 case DRM_FORMAT_ABGR2101010:
14230 if (!IS_VALLEYVIEW(dev)) {
14231 DRM_DEBUG("unsupported pixel format: %s\n",
14232 drm_get_format_name(mode_cmd->pixel_format));
14233 return -EINVAL;
14234 }
14235 break;
04b3924d
VS		 14236 case DRM_FORMAT_YUYV:
14237 case DRM_FORMAT_UYVY:
14238 case DRM_FORMAT_YVYU:
14239 case DRM_FORMAT_VYUY:
c16ed4be 14240 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 14241 DRM_DEBUG("unsupported pixel format: %s\n",
14242 drm_get_format_name(mode_cmd->pixel_format));
57779d06 14243 return -EINVAL;
c16ed4be 14244 }
57cd6508
CW		 14245 break;
14246 default:
4ee62c76
VS		 14247 DRM_DEBUG("unsupported pixel format: %s\n",
14248 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 14249 return -EINVAL;
14250 }
14251
90f9a336
VS		 14252 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
14253 if (mode_cmd->offsets[0] != 0)
14254 return -EINVAL;
14255
ec2c981e 14256 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 14257 mode_cmd->pixel_format,
14258 mode_cmd->modifier[0]);
53155c0a
DV		 14259 /* FIXME drm helper for size checks (especially planar formats)? */
14260 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
14261 return -EINVAL;
14262
c7d73f6a
DV		 14263 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
14264 intel_fb->obj = obj;
80075d49 14265 intel_fb->obj->framebuffer_references++;
c7d73f6a 14266
79e53945
JB		 14267 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
14268 if (ret) {
14269 DRM_ERROR("framebuffer init failed %d\n", ret);
14270 return ret;
14271 }
14272
79e53945
JB		 14273 return 0;
14274}
14275
79e53945
JB		 14276static struct drm_framebuffer *
14277intel_user_framebuffer_create(struct drm_device *dev,
14278 struct drm_file *filp,
308e5bcb 14279 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 14280{
05394f39 14281 struct drm_i915_gem_object *obj;
79e53945 14282
308e5bcb
JB		 14283 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
14284 mode_cmd->handles[0]));
c8725226 14285 if (&obj->base == NULL)
cce13ff7 14286 return ERR_PTR(-ENOENT);
79e53945 14287
d2dff872 14288 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 14289}
14290
4520f53a 14291#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 14292static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 14293{
14294}
14295#endif
14296
79e53945 14297static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 14298 .fb_create = intel_user_framebuffer_create,
0632fef6 14299 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 14300 .atomic_check = intel_atomic_check,
14301 .atomic_commit = intel_atomic_commit,
79e53945
JB		 14302};
14303
e70236a8
JB		 14304/* Set up chip specific display functions */
14305static void intel_init_display(struct drm_device *dev)
14306{
14307 struct drm_i915_private *dev_priv = dev->dev_private;
14308
ee9300bb
DV		 14309 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
14310 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 14311 else if (IS_CHERRYVIEW(dev))
14312 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 14313 else if (IS_VALLEYVIEW(dev))
14314 dev_priv->display.find_dpll = vlv_find_best_dpll;
14315 else if (IS_PINEVIEW(dev))
14316 dev_priv->display.find_dpll = pnv_find_best_dpll;
14317 else
14318 dev_priv->display.find_dpll = i9xx_find_best_dpll;
14319
bc8d7dff
DL		 14320 if (INTEL_INFO(dev)->gen >= 9) {
14321 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14322 dev_priv->display.get_initial_plane_config =
14323 skylake_get_initial_plane_config;
bc8d7dff
DL		 14324 dev_priv->display.crtc_compute_clock =
14325 haswell_crtc_compute_clock;
14326 dev_priv->display.crtc_enable = haswell_crtc_enable;
14327 dev_priv->display.crtc_disable = haswell_crtc_disable;
14328 dev_priv->display.off = ironlake_crtc_off;
14329 dev_priv->display.update_primary_plane =
14330 skylake_update_primary_plane;
14331 } else if (HAS_DDI(dev)) {
0e8ffe1b 14332 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 14333 dev_priv->display.get_initial_plane_config =
14334 ironlake_get_initial_plane_config;
797d0259
ACO		 14335 dev_priv->display.crtc_compute_clock =
14336 haswell_crtc_compute_clock;
4f771f10
PZ		 14337 dev_priv->display.crtc_enable = haswell_crtc_enable;
14338 dev_priv->display.crtc_disable = haswell_crtc_disable;
df8ad70c 14339 dev_priv->display.off = ironlake_crtc_off;
bc8d7dff
DL		 14340 dev_priv->display.update_primary_plane =
14341 ironlake_update_primary_plane;
09b4ddf9 14342 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 14343 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 14344 dev_priv->display.get_initial_plane_config =
14345 ironlake_get_initial_plane_config;
3fb37703
ACO		 14346 dev_priv->display.crtc_compute_clock =
14347 ironlake_crtc_compute_clock;
76e5a89c
DV		 14348 dev_priv->display.crtc_enable = ironlake_crtc_enable;
14349 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 14350 dev_priv->display.off = ironlake_crtc_off;
262ca2b0
MR		 14351 dev_priv->display.update_primary_plane =
14352 ironlake_update_primary_plane;
89b667f8
JB		 14353 } else if (IS_VALLEYVIEW(dev)) {
14354 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14355 dev_priv->display.get_initial_plane_config =
14356 i9xx_get_initial_plane_config;
d6dfee7a 14357 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 14358 dev_priv->display.crtc_enable = valleyview_crtc_enable;
14359 dev_priv->display.crtc_disable = i9xx_crtc_disable;
14360 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14361 dev_priv->display.update_primary_plane =
14362 i9xx_update_primary_plane;
f564048e 14363 } else {
0e8ffe1b 14364 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 14365 dev_priv->display.get_initial_plane_config =
14366 i9xx_get_initial_plane_config;
d6dfee7a 14367 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 14368 dev_priv->display.crtc_enable = i9xx_crtc_enable;
14369 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 14370 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 14371 dev_priv->display.update_primary_plane =
14372 i9xx_update_primary_plane;
f564048e 14373 }
e70236a8 14374
e70236a8 14375 /* Returns the core display clock speed */
1652d19e
VS		 14376 if (IS_SKYLAKE(dev))
14377 dev_priv->display.get_display_clock_speed =
14378 skylake_get_display_clock_speed;
14379 else if (IS_BROADWELL(dev))
14380 dev_priv->display.get_display_clock_speed =
14381 broadwell_get_display_clock_speed;
14382 else if (IS_HASWELL(dev))
14383 dev_priv->display.get_display_clock_speed =
14384 haswell_get_display_clock_speed;
14385 else if (IS_VALLEYVIEW(dev))
25eb05fc
JB		 14386 dev_priv->display.get_display_clock_speed =
14387 valleyview_get_display_clock_speed;
b37a6434
VS		 14388 else if (IS_GEN5(dev))
14389 dev_priv->display.get_display_clock_speed =
14390 ilk_get_display_clock_speed;
a7c66cd8
VS		 14391 else if (IS_I945G(dev) || IS_BROADWATER(dev) ||
14392 IS_GEN6(dev) || IS_IVYBRIDGE(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 14393 dev_priv->display.get_display_clock_speed =
14394 i945_get_display_clock_speed;
14395 else if (IS_I915G(dev))
14396 dev_priv->display.get_display_clock_speed =
14397 i915_get_display_clock_speed;
257a7ffc 14398 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 14399 dev_priv->display.get_display_clock_speed =
14400 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 14401 else if (IS_PINEVIEW(dev))
14402 dev_priv->display.get_display_clock_speed =
14403 pnv_get_display_clock_speed;
e70236a8
JB		 14404 else if (IS_I915GM(dev))
14405 dev_priv->display.get_display_clock_speed =
14406 i915gm_get_display_clock_speed;
14407 else if (IS_I865G(dev))
14408 dev_priv->display.get_display_clock_speed =
14409 i865_get_display_clock_speed;
f0f8a9ce 14410 else if (IS_I85X(dev))
e70236a8
JB		 14411 dev_priv->display.get_display_clock_speed =
14412 i855_get_display_clock_speed;
14413 else /* 852, 830 */
14414 dev_priv->display.get_display_clock_speed =
14415 i830_get_display_clock_speed;
14416
7c10a2b5 14417 if (IS_GEN5(dev)) {
3bb11b53 14418 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 14419 } else if (IS_GEN6(dev)) {
14420 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 14421 } else if (IS_IVYBRIDGE(dev)) {
14422 /* FIXME: detect B0+ stepping and use auto training */
14423 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 14424 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 14425 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
30a970c6
JB		 14426 } else if (IS_VALLEYVIEW(dev)) {
14427 dev_priv->display.modeset_global_resources =
14428 valleyview_modeset_global_resources;
f8437dd1
VK		 14429 } else if (IS_BROXTON(dev)) {
14430 dev_priv->display.modeset_global_resources =
14431 broxton_modeset_global_resources;
e70236a8 14432 }
8c9f3aaf 14433
8c9f3aaf
JB		 14434 switch (INTEL_INFO(dev)->gen) {
14435 case 2:
14436 dev_priv->display.queue_flip = intel_gen2_queue_flip;
14437 break;
14438
14439 case 3:
14440 dev_priv->display.queue_flip = intel_gen3_queue_flip;
14441 break;
14442
14443 case 4:
14444 case 5:
14445 dev_priv->display.queue_flip = intel_gen4_queue_flip;
14446 break;
14447
14448 case 6:
14449 dev_priv->display.queue_flip = intel_gen6_queue_flip;
14450 break;
7c9017e5 14451 case 7:
4e0bbc31 14452 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 14453 dev_priv->display.queue_flip = intel_gen7_queue_flip;
14454 break;
830c81db 14455 case 9:
ba343e02
TU		 14456 /* Drop through - unsupported since execlist only. */
14457 default:
14458 /* Default just returns -ENODEV to indicate unsupported */
14459 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 14460 }
7bd688cd
JN		 14461
14462 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 14463
14464 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 14465}
14466
b690e96c
JB		 14467/*
14468 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
14469 * resume, or other times. This quirk makes sure that's the case for
14470 * affected systems.
14471 */
0206e353 14472static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 14473{
14474 struct drm_i915_private *dev_priv = dev->dev_private;
14475
14476 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 14477 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 14478}
14479
b6b5d049
VS		 14480static void quirk_pipeb_force(struct drm_device *dev)
14481{
14482 struct drm_i915_private *dev_priv = dev->dev_private;
14483
14484 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
14485 DRM_INFO("applying pipe b force quirk\n");
14486}
14487
435793df
KP		 14488/*
14489 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
14490 */
14491static void quirk_ssc_force_disable(struct drm_device *dev)
14492{
14493 struct drm_i915_private *dev_priv = dev->dev_private;
14494 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 14495 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 14496}
14497
4dca20ef 14498/*
5a15ab5b
CE		 14499 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
14500 * brightness value
4dca20ef
CE		 14501 */
14502static void quirk_invert_brightness(struct drm_device *dev)
14503{
14504 struct drm_i915_private *dev_priv = dev->dev_private;
14505 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 14506 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 14507}
14508
9c72cc6f
SD		 14509/* Some VBT's incorrectly indicate no backlight is present */
14510static void quirk_backlight_present(struct drm_device *dev)
14511{
14512 struct drm_i915_private *dev_priv = dev->dev_private;
14513 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
14514 DRM_INFO("applying backlight present quirk\n");
14515}
14516
b690e96c
JB		 14517struct intel_quirk {
14518 int device;
14519 int subsystem_vendor;
14520 int subsystem_device;
14521 void (*hook)(struct drm_device *dev);
14522};
14523
5f85f176
EE		 14524/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
14525struct intel_dmi_quirk {
14526 void (*hook)(struct drm_device *dev);
14527 const struct dmi_system_id (*dmi_id_list)[];
14528};
14529
14530static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
14531{
14532 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
14533 return 1;
14534}
14535
14536static const struct intel_dmi_quirk intel_dmi_quirks[] = {
14537 {
14538 .dmi_id_list = &(const struct dmi_system_id[]) {
14539 {
14540 .callback = intel_dmi_reverse_brightness,
14541 .ident = "NCR Corporation",
14542 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
14543 DMI_MATCH(DMI_PRODUCT_NAME, ""),
14544 },
14545 },
14546 { } /* terminating entry */
14547 },
14548 .hook = quirk_invert_brightness,
14549 },
14550};
14551
c43b5634 14552static struct intel_quirk intel_quirks[] = {
b690e96c
JB		 14553 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
14554 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
14555
b690e96c
JB		 14556 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
14557 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
14558
5f080c0f
VS		 14559 /* 830 needs to leave pipe A & dpll A up */
14560 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
14561
b6b5d049
VS		 14562 /* 830 needs to leave pipe B & dpll B up */
14563 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
14564
435793df
KP		 14565 /* Lenovo U160 cannot use SSC on LVDS */
14566 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 14567
14568 /* Sony Vaio Y cannot use SSC on LVDS */
14569 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 14570
be505f64
AH		 14571 /* Acer Aspire 5734Z must invert backlight brightness */
14572 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
14573
14574 /* Acer/eMachines G725 */
14575 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
14576
14577 /* Acer/eMachines e725 */
14578 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
14579
14580 /* Acer/Packard Bell NCL20 */
14581 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
14582
14583 /* Acer Aspire 4736Z */
14584 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 14585
14586 /* Acer Aspire 5336 */
14587 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 14588
14589 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
14590 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 14591
dfb3d47b
SD		 14592 /* Acer C720 Chromebook (Core i3 4005U) */
14593 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
14594
b2a9601c 14595 /* Apple Macbook 2,1 (Core 2 T7400) */
14596 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
14597
d4967d8c
SD		 14598 /* Toshiba CB35 Chromebook (Celeron 2955U) */
14599 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 14600
14601 /* HP Chromebook 14 (Celeron 2955U) */
14602 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 14603
14604 /* Dell Chromebook 11 */
14605 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 14606};
14607
14608static void intel_init_quirks(struct drm_device *dev)
14609{
14610 struct pci_dev *d = dev->pdev;
14611 int i;
14612
14613 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
14614 struct intel_quirk *q = &intel_quirks[i];
14615
14616 if (d->device == q->device &&
14617 (d->subsystem_vendor == q->subsystem_vendor ||
14618 q->subsystem_vendor == PCI_ANY_ID) &&
14619 (d->subsystem_device == q->subsystem_device ||
14620 q->subsystem_device == PCI_ANY_ID))
14621 q->hook(dev);
14622 }
5f85f176
EE		 14623 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
14624 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
14625 intel_dmi_quirks[i].hook(dev);
14626 }
b690e96c
JB		 14627}
14628
9cce37f4
JB		 14629/* Disable the VGA plane that we never use */
14630static void i915_disable_vga(struct drm_device *dev)
14631{
14632 struct drm_i915_private *dev_priv = dev->dev_private;
14633 u8 sr1;
766aa1c4 14634 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 14635
2b37c616 14636 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 14637 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 14638 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 14639 sr1 = inb(VGA_SR_DATA);
14640 outb(sr1 | 1<<5, VGA_SR_DATA);
14641 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
14642 udelay(300);
14643
01f5a626 14644 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 14645 POSTING_READ(vga_reg);
14646}
14647
f817586c
DV		 14648void intel_modeset_init_hw(struct drm_device *dev)
14649{
a8f78b58
ED		 14650 intel_prepare_ddi(dev);
14651
f8bf63fd
VS		 14652 if (IS_VALLEYVIEW(dev))
14653 vlv_update_cdclk(dev);
14654
f817586c
DV		 14655 intel_init_clock_gating(dev);
14656
8090c6b9 14657 intel_enable_gt_powersave(dev);
f817586c
DV		 14658}
14659
79e53945
JB		 14660void intel_modeset_init(struct drm_device *dev)
14661{
652c393a 14662 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 14663 int sprite, ret;
8cc87b75 14664 enum pipe pipe;
46f297fb 14665 struct intel_crtc *crtc;
79e53945
JB		 14666
14667 drm_mode_config_init(dev);
14668
14669 dev->mode_config.min_width = 0;
14670 dev->mode_config.min_height = 0;
14671
019d96cb
DA		 14672 dev->mode_config.preferred_depth = 24;
14673 dev->mode_config.prefer_shadow = 1;
14674
25bab385
TU		 14675 dev->mode_config.allow_fb_modifiers = true;
14676
e6ecefaa 14677 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 14678
b690e96c
JB		 14679 intel_init_quirks(dev);
14680
1fa61106
ED		 14681 intel_init_pm(dev);
14682
e3c74757
BW		 14683 if (INTEL_INFO(dev)->num_pipes == 0)
14684 return;
14685
e70236a8 14686 intel_init_display(dev);
7c10a2b5 14687 intel_init_audio(dev);
e70236a8 14688
a6c45cf0
CW		 14689 if (IS_GEN2(dev)) {
14690 dev->mode_config.max_width = 2048;
14691 dev->mode_config.max_height = 2048;
14692 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 14693 dev->mode_config.max_width = 4096;
14694 dev->mode_config.max_height = 4096;
79e53945 14695 } else {
a6c45cf0
CW		 14696 dev->mode_config.max_width = 8192;
14697 dev->mode_config.max_height = 8192;
79e53945 14698 }
068be561 14699
dc41c154
VS		 14700 if (IS_845G(dev) || IS_I865G(dev)) {
14701 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
14702 dev->mode_config.cursor_height = 1023;
14703 } else if (IS_GEN2(dev)) {
068be561
DL		 14704 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
14705 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
14706 } else {
14707 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
14708 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
14709 }
14710
5d4545ae 14711 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 14712
28c97730 14713 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 14714 INTEL_INFO(dev)->num_pipes,
14715 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 14716
055e393f 14717 for_each_pipe(dev_priv, pipe) {
8cc87b75 14718 intel_crtc_init(dev, pipe);
3bdcfc0c 14719 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 14720 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 14721 if (ret)
06da8da2 14722 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 14723 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 14724 }
79e53945
JB		 14725 }
14726
f42bb70d
JB		 14727 intel_init_dpio(dev);
14728
e72f9fbf 14729 intel_shared_dpll_init(dev);
ee7b9f93 14730
9cce37f4
JB		 14731 /* Just disable it once at startup */
14732 i915_disable_vga(dev);
79e53945 14733 intel_setup_outputs(dev);
11be49eb
CW		 14734
14735 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 14736 intel_fbc_disable(dev);
fa9fa083 14737
6e9f798d 14738 drm_modeset_lock_all(dev);
fa9fa083 14739 intel_modeset_setup_hw_state(dev, false);
6e9f798d 14740 drm_modeset_unlock_all(dev);
46f297fb 14741
d3fcc808 14742 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 14743 if (!crtc->active)
14744 continue;
14745
46f297fb 14746 /*
46f297fb
JB		 14747 * Note that reserving the BIOS fb up front prevents us
14748 * from stuffing other stolen allocations like the ring
14749 * on top. This prevents some ugliness at boot time, and
14750 * can even allow for smooth boot transitions if the BIOS
14751 * fb is large enough for the active pipe configuration.
14752 */
5724dbd1
DL		 14753 if (dev_priv->display.get_initial_plane_config) {
14754 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 14755 &crtc->plane_config);
14756 /*
14757 * If the fb is shared between multiple heads, we'll
14758 * just get the first one.
14759 */
f6936e29 14760 intel_find_initial_plane_obj(crtc, &crtc->plane_config);
46f297fb 14761 }
46f297fb 14762 }
2c7111db
CW		 14763}
14764
7fad798e
DV		 14765static void intel_enable_pipe_a(struct drm_device *dev)
14766{
14767 struct intel_connector *connector;
14768 struct drm_connector *crt = NULL;
14769 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 14770 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 14771
14772 /* We can't just switch on the pipe A, we need to set things up with a
14773 * proper mode and output configuration. As a gross hack, enable pipe A
14774 * by enabling the load detect pipe once. */
3a3371ff 14775 for_each_intel_connector(dev, connector) {
7fad798e
DV		 14776 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
14777 crt = &connector->base;
14778 break;
14779 }
14780 }
14781
14782 if (!crt)
14783 return;
14784
208bf9fd 14785 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
49172fee 14786 intel_release_load_detect_pipe(crt, &load_detect_temp, ctx);
7fad798e
DV		 14787}
14788
fa555837
DV		 14789static bool
14790intel_check_plane_mapping(struct intel_crtc *crtc)
14791{
7eb552ae
BW		 14792 struct drm_device *dev = crtc->base.dev;
14793 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 14794 u32 reg, val;
14795
7eb552ae 14796 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 14797 return true;
14798
14799 reg = DSPCNTR(!crtc->plane);
14800 val = I915_READ(reg);
14801
14802 if ((val & DISPLAY_PLANE_ENABLE) &&
14803 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
14804 return false;
14805
14806 return true;
14807}
14808
24929352
DV		 14809static void intel_sanitize_crtc(struct intel_crtc *crtc)
14810{
14811 struct drm_device *dev = crtc->base.dev;
14812 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 14813 u32 reg;
24929352 14814
24929352 14815 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 14816 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 14817 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
14818
d3eaf884 14819 /* restore vblank interrupts to correct state */
9625604c 14820 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 14821 if (crtc->active) {
14822 update_scanline_offset(crtc);
9625604c
DV		 14823 drm_crtc_vblank_on(&crtc->base);
14824 }
d3eaf884 14825
24929352 14826 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 14827 * disable the crtc (and hence change the state) if it is wrong. Note
14828 * that gen4+ has a fixed plane -> pipe mapping. */
14829 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 14830 struct intel_connector *connector;
14831 bool plane;
14832
24929352
DV		 14833 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
14834 crtc->base.base.id);
14835
14836 /* Pipe has the wrong plane attached and the plane is active.
14837 * Temporarily change the plane mapping and disable everything
14838 * ... */
14839 plane = crtc->plane;
b70709a6 14840 to_intel_plane_state(crtc->base.primary->state)->visible = true;
24929352 14841 crtc->plane = !plane;
ce22dba9 14842 intel_crtc_disable_planes(&crtc->base);
24929352
DV		 14843 dev_priv->display.crtc_disable(&crtc->base);
14844 crtc->plane = plane;
14845
14846 /* ... and break all links. */
3a3371ff 14847 for_each_intel_connector(dev, connector) {
24929352
DV		 14848 if (connector->encoder->base.crtc != &crtc->base)
14849 continue;
14850
7f1950fb
EE		 14851 connector->base.dpms = DRM_MODE_DPMS_OFF;
14852 connector->base.encoder = NULL;
24929352 14853 }
7f1950fb
EE		 14854 /* multiple connectors may have the same encoder:
14855 * handle them and break crtc link separately */
3a3371ff 14856 for_each_intel_connector(dev, connector)
7f1950fb
EE		 14857 if (connector->encoder->base.crtc == &crtc->base) {
14858 connector->encoder->base.crtc = NULL;
14859 connector->encoder->connectors_active = false;
14860 }
24929352
DV		 14861
14862 WARN_ON(crtc->active);
83d65738 14863 crtc->base.state->enable = false;
49d6fa21 14864 crtc->base.state->active = false;
24929352
DV		 14865 crtc->base.enabled = false;
14866 }
24929352 14867
7fad798e
DV		 14868 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
14869 crtc->pipe == PIPE_A && !crtc->active) {
14870 /* BIOS forgot to enable pipe A, this mostly happens after
14871 * resume. Force-enable the pipe to fix this, the update_dpms
14872 * call below we restore the pipe to the right state, but leave
14873 * the required bits on. */
14874 intel_enable_pipe_a(dev);
14875 }
14876
24929352
DV		 14877 /* Adjust the state of the output pipe according to whether we
14878 * have active connectors/encoders. */
14879 intel_crtc_update_dpms(&crtc->base);
14880
83d65738 14881 if (crtc->active != crtc->base.state->enable) {
24929352
DV		 14882 struct intel_encoder *encoder;
14883
14884 /* This can happen either due to bugs in the get_hw_state
14885 * functions or because the pipe is force-enabled due to the
14886 * pipe A quirk. */
14887 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
14888 crtc->base.base.id,
83d65738 14889 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 14890 crtc->active ? "enabled" : "disabled");
14891
83d65738 14892 crtc->base.state->enable = crtc->active;
49d6fa21 14893 crtc->base.state->active = crtc->active;
24929352
DV		 14894 crtc->base.enabled = crtc->active;
14895
14896 /* Because we only establish the connector -> encoder ->
14897 * crtc links if something is active, this means the
14898 * crtc is now deactivated. Break the links. connector
14899 * -> encoder links are only establish when things are
14900 * actually up, hence no need to break them. */
14901 WARN_ON(crtc->active);
14902
14903 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
14904 WARN_ON(encoder->connectors_active);
14905 encoder->base.crtc = NULL;
14906 }
14907 }
c5ab3bc0 14908
a3ed6aad 14909 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 14910 /*
14911 * We start out with underrun reporting disabled to avoid races.
14912 * For correct bookkeeping mark this on active crtcs.
14913 *
c5ab3bc0
DV		 14914 * Also on gmch platforms we dont have any hardware bits to
14915 * disable the underrun reporting. Which means we need to start
14916 * out with underrun reporting disabled also on inactive pipes,
14917 * since otherwise we'll complain about the garbage we read when
14918 * e.g. coming up after runtime pm.
14919 *
4cc31489
DV		 14920 * No protection against concurrent access is required - at
14921 * worst a fifo underrun happens which also sets this to false.
14922 */
14923 crtc->cpu_fifo_underrun_disabled = true;
14924 crtc->pch_fifo_underrun_disabled = true;
14925 }
24929352
DV		 14926}
14927
14928static void intel_sanitize_encoder(struct intel_encoder *encoder)
14929{
14930 struct intel_connector *connector;
14931 struct drm_device *dev = encoder->base.dev;
14932
14933 /* We need to check both for a crtc link (meaning that the
14934 * encoder is active and trying to read from a pipe) and the
14935 * pipe itself being active. */
14936 bool has_active_crtc = encoder->base.crtc &&
14937 to_intel_crtc(encoder->base.crtc)->active;
14938
14939 if (encoder->connectors_active && !has_active_crtc) {
14940 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
14941 encoder->base.base.id,
8e329a03 14942 encoder->base.name);
24929352
DV		 14943
14944 /* Connector is active, but has no active pipe. This is
14945 * fallout from our resume register restoring. Disable
14946 * the encoder manually again. */
14947 if (encoder->base.crtc) {
14948 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
14949 encoder->base.base.id,
8e329a03 14950 encoder->base.name);
24929352 14951 encoder->disable(encoder);
a62d1497
VS		 14952 if (encoder->post_disable)
14953 encoder->post_disable(encoder);
24929352 14954 }
7f1950fb
EE		 14955 encoder->base.crtc = NULL;
14956 encoder->connectors_active = false;
24929352
DV		 14957
14958 /* Inconsistent output/port/pipe state happens presumably due to
14959 * a bug in one of the get_hw_state functions. Or someplace else
14960 * in our code, like the register restore mess on resume. Clamp
14961 * things to off as a safer default. */
3a3371ff 14962 for_each_intel_connector(dev, connector) {
24929352
DV		 14963 if (connector->encoder != encoder)
14964 continue;
7f1950fb
EE		 14965 connector->base.dpms = DRM_MODE_DPMS_OFF;
14966 connector->base.encoder = NULL;
24929352
DV		 14967 }
14968 }
14969 /* Enabled encoders without active connectors will be fixed in
14970 * the crtc fixup. */
14971}
14972
04098753 14973void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 14974{
14975 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 14976 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 14977
04098753
ID		 14978 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
14979 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
14980 i915_disable_vga(dev);
14981 }
14982}
14983
14984void i915_redisable_vga(struct drm_device *dev)
14985{
14986 struct drm_i915_private *dev_priv = dev->dev_private;
14987
8dc8a27c
PZ		 14988 /* This function can be called both from intel_modeset_setup_hw_state or
14989 * at a very early point in our resume sequence, where the power well
14990 * structures are not yet restored. Since this function is at a very
14991 * paranoid "someone might have enabled VGA while we were not looking"
14992 * level, just check if the power well is enabled instead of trying to
14993 * follow the "don't touch the power well if we don't need it" policy
14994 * the rest of the driver uses. */
f458ebbc 14995 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 14996 return;
14997
04098753 14998 i915_redisable_vga_power_on(dev);
0fde901f
KM		 14999}
15000
98ec7739
VS		 15001static bool primary_get_hw_state(struct intel_crtc *crtc)
15002{
15003 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
15004
15005 if (!crtc->active)
15006 return false;
15007
15008 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
15009}
15010
30e984df 15011static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 15012{
15013 struct drm_i915_private *dev_priv = dev->dev_private;
15014 enum pipe pipe;
24929352
DV		 15015 struct intel_crtc *crtc;
15016 struct intel_encoder *encoder;
15017 struct intel_connector *connector;
5358901f 15018 int i;
24929352 15019
d3fcc808 15020 for_each_intel_crtc(dev, crtc) {
b70709a6
ML		 15021 struct drm_plane *primary = crtc->base.primary;
15022 struct intel_plane_state *plane_state;
15023
6e3c9717 15024 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 15025
6e3c9717 15026 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 15027
0e8ffe1b 15028 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 15029 crtc->config);
24929352 15030
83d65738 15031 crtc->base.state->enable = crtc->active;
49d6fa21 15032 crtc->base.state->active = crtc->active;
24929352 15033 crtc->base.enabled = crtc->active;
b70709a6
ML		 15034
15035 plane_state = to_intel_plane_state(primary->state);
15036 plane_state->visible = primary_get_hw_state(crtc);
24929352
DV		 15037
15038 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
15039 crtc->base.base.id,
15040 crtc->active ? "enabled" : "disabled");
15041 }
15042
5358901f
DV		 15043 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15044 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15045
3e369b76
ACO		 15046 pll->on = pll->get_hw_state(dev_priv, pll,
15047 &pll->config.hw_state);
5358901f 15048 pll->active = 0;
3e369b76 15049 pll->config.crtc_mask = 0;
d3fcc808 15050 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 15051 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 15052 pll->active++;
3e369b76 15053 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 15054 }
5358901f 15055 }
5358901f 15056
1e6f2ddc 15057 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 15058 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 15059
3e369b76 15060 if (pll->config.crtc_mask)
bd2bb1b9 15061 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 15062 }
15063
b2784e15 15064 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15065 pipe = 0;
15066
15067 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 15068 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15069 encoder->base.crtc = &crtc->base;
6e3c9717 15070 encoder->get_config(encoder, crtc->config);
24929352
DV		 15071 } else {
15072 encoder->base.crtc = NULL;
15073 }
15074
15075 encoder->connectors_active = false;
6f2bcceb 15076 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 15077 encoder->base.base.id,
8e329a03 15078 encoder->base.name,
24929352 15079 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 15080 pipe_name(pipe));
24929352
DV		 15081 }
15082
3a3371ff 15083 for_each_intel_connector(dev, connector) {
24929352
DV		 15084 if (connector->get_hw_state(connector)) {
15085 connector->base.dpms = DRM_MODE_DPMS_ON;
15086 connector->encoder->connectors_active = true;
15087 connector->base.encoder = &connector->encoder->base;
15088 } else {
15089 connector->base.dpms = DRM_MODE_DPMS_OFF;
15090 connector->base.encoder = NULL;
15091 }
15092 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
15093 connector->base.base.id,
c23cc417 15094 connector->base.name,
24929352
DV		 15095 connector->base.encoder ? "enabled" : "disabled");
15096 }
30e984df
DV		 15097}
15098
15099/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
15100 * and i915 state tracking structures. */
15101void intel_modeset_setup_hw_state(struct drm_device *dev,
15102 bool force_restore)
15103{
15104 struct drm_i915_private *dev_priv = dev->dev_private;
15105 enum pipe pipe;
30e984df
DV		 15106 struct intel_crtc *crtc;
15107 struct intel_encoder *encoder;
35c95375 15108 int i;
30e984df
DV		 15109
15110 intel_modeset_readout_hw_state(dev);
24929352 15111
babea61d
JB		 15112 /*
15113 * Now that we have the config, copy it to each CRTC struct
15114 * Note that this could go away if we move to using crtc_config
15115 * checking everywhere.
15116 */
d3fcc808 15117 for_each_intel_crtc(dev, crtc) {
d330a953 15118 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 15119 intel_mode_from_pipe_config(&crtc->base.mode,
15120 crtc->config);
babea61d
JB		 15121 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
15122 crtc->base.base.id);
15123 drm_mode_debug_printmodeline(&crtc->base.mode);
15124 }
15125 }
15126
24929352 15127 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 15128 for_each_intel_encoder(dev, encoder) {
24929352
DV		 15129 intel_sanitize_encoder(encoder);
15130 }
15131
055e393f 15132 for_each_pipe(dev_priv, pipe) {
24929352
DV		 15133 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
15134 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 15135 intel_dump_pipe_config(crtc, crtc->config,
15136 "[setup_hw_state]");
24929352 15137 }
9a935856 15138
d29b2f9d
ACO		 15139 intel_modeset_update_connector_atomic_state(dev);
15140
35c95375
DV		 15141 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
15142 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
15143
15144 if (!pll->on || pll->active)
15145 continue;
15146
15147 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
15148
15149 pll->disable(dev_priv, pll);
15150 pll->on = false;
15151 }
15152
3078999f
PB		 15153 if (IS_GEN9(dev))
15154 skl_wm_get_hw_state(dev);
15155 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 15156 ilk_wm_get_hw_state(dev);
15157
45e2b5f6 15158 if (force_restore) {
7d0bc1ea
VS		 15159 i915_redisable_vga(dev);
15160
f30da187
DV		 15161 /*
15162 * We need to use raw interfaces for restoring state to avoid
15163 * checking (bogus) intermediate states.
15164 */
055e393f 15165 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 15166 struct drm_crtc *crtc =
15167 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 15168
83a57153 15169 intel_crtc_restore_mode(crtc);
45e2b5f6
DV		 15170 }
15171 } else {
15172 intel_modeset_update_staged_output_state(dev);
15173 }
8af6cf88
DV		 15174
15175 intel_modeset_check_state(dev);
2c7111db
CW		 15176}
15177
15178void intel_modeset_gem_init(struct drm_device *dev)
15179{
92122789 15180 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 15181 struct drm_crtc *c;
2ff8fde1 15182 struct drm_i915_gem_object *obj;
e0d6149b 15183 int ret;
484b41dd 15184
ae48434c
ID		 15185 mutex_lock(&dev->struct_mutex);
15186 intel_init_gt_powersave(dev);
15187 mutex_unlock(&dev->struct_mutex);
15188
92122789
JB		 15189 /*
15190 * There may be no VBT; and if the BIOS enabled SSC we can
15191 * just keep using it to avoid unnecessary flicker. Whereas if the
15192 * BIOS isn't using it, don't assume it will work even if the VBT
15193 * indicates as much.
15194 */
15195 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
15196 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
15197 DREF_SSC1_ENABLE);
15198
1833b134 15199 intel_modeset_init_hw(dev);
02e792fb
DV		 15200
15201 intel_setup_overlay(dev);
484b41dd
JB		 15202
15203 /*
15204 * Make sure any fbs we allocated at startup are properly
15205 * pinned & fenced. When we do the allocation it's too early
15206 * for this.
15207 */
70e1e0ec 15208 for_each_crtc(dev, c) {
2ff8fde1
MR		 15209 obj = intel_fb_obj(c->primary->fb);
15210 if (obj == NULL)
484b41dd
JB		 15211 continue;
15212
e0d6149b
TU		 15213 mutex_lock(&dev->struct_mutex);
15214 ret = intel_pin_and_fence_fb_obj(c->primary,
15215 c->primary->fb,
15216 c->primary->state,
15217 NULL);
15218 mutex_unlock(&dev->struct_mutex);
15219 if (ret) {
484b41dd
JB		 15220 DRM_ERROR("failed to pin boot fb on pipe %d\n",
15221 to_intel_crtc(c)->pipe);
66e514c1
DA		 15222 drm_framebuffer_unreference(c->primary->fb);
15223 c->primary->fb = NULL;
afd65eb4 15224 update_state_fb(c->primary);
484b41dd
JB		 15225 }
15226 }
0962c3c9
VS		 15227
15228 intel_backlight_register(dev);
79e53945
JB		 15229}
15230
4932e2c3
ID		 15231void intel_connector_unregister(struct intel_connector *intel_connector)
15232{
15233 struct drm_connector *connector = &intel_connector->base;
15234
15235 intel_panel_destroy_backlight(connector);
34ea3d38 15236 drm_connector_unregister(connector);
4932e2c3
ID		 15237}
15238
79e53945
JB		 15239void intel_modeset_cleanup(struct drm_device *dev)
15240{
652c393a 15241 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 15242 struct drm_connector *connector;
652c393a 15243
2eb5252e
ID		 15244 intel_disable_gt_powersave(dev);
15245
0962c3c9
VS		 15246 intel_backlight_unregister(dev);
15247
fd0c0642
DV		 15248 /*
15249 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 15250 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 15251 * experience fancy races otherwise.
15252 */
2aeb7d3a 15253 intel_irq_uninstall(dev_priv);
eb21b92b 15254
fd0c0642
DV		 15255 /*
15256 * Due to the hpd irq storm handling the hotplug work can re-arm the
15257 * poll handlers. Hence disable polling after hpd handling is shut down.
15258 */
f87ea761 15259 drm_kms_helper_poll_fini(dev);
fd0c0642 15260
652c393a
JB		 15261 mutex_lock(&dev->struct_mutex);
15262
723bfd70
JB		 15263 intel_unregister_dsm_handler();
15264
7ff0ebcc 15265 intel_fbc_disable(dev);
e70236a8 15266
69341a5e
KH		 15267 mutex_unlock(&dev->struct_mutex);
15268
1630fe75
CW		 15269 /* flush any delayed tasks or pending work */
15270 flush_scheduled_work();
15271
db31af1d
JN		 15272 /* destroy the backlight and sysfs files before encoders/connectors */
15273 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 15274 struct intel_connector *intel_connector;
15275
15276 intel_connector = to_intel_connector(connector);
15277 intel_connector->unregister(intel_connector);
db31af1d 15278 }
d9255d57 15279
79e53945 15280 drm_mode_config_cleanup(dev);
4d7bb011
DV		 15281
15282 intel_cleanup_overlay(dev);
ae48434c
ID		 15283
15284 mutex_lock(&dev->struct_mutex);
15285 intel_cleanup_gt_powersave(dev);
15286 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 15287}
15288
f1c79df3
ZW		 15289/*
15290 * Return which encoder is currently attached for connector.
15291 */
df0e9248 15292struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 15293{
df0e9248
CW		 15294 return &intel_attached_encoder(connector)->base;
15295}
f1c79df3 15296
df0e9248
CW		 15297void intel_connector_attach_encoder(struct intel_connector *connector,
15298 struct intel_encoder *encoder)
15299{
15300 connector->encoder = encoder;
15301 drm_mode_connector_attach_encoder(&connector->base,
15302 &encoder->base);
79e53945 15303}
28d52043
DA		 15304
15305/*
15306 * set vga decode state - true == enable VGA decode
15307 */
15308int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
15309{
15310 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 15311 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 15312 u16 gmch_ctrl;
15313
75fa041d
CW		 15314 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
15315 DRM_ERROR("failed to read control word\n");
15316 return -EIO;
15317 }
15318
c0cc8a55
CW		 15319 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
15320 return 0;
15321
28d52043
DA		 15322 if (state)
15323 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
15324 else
15325 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 15326
15327 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
15328 DRM_ERROR("failed to write control word\n");
15329 return -EIO;
15330 }
15331
28d52043
DA		 15332 return 0;
15333}
c4a1d9e4 15334
c4a1d9e4 15335struct intel_display_error_state {
ff57f1b0
PZ		 15336
15337 u32 power_well_driver;
15338
63b66e5b
CW		 15339 int num_transcoders;
15340
c4a1d9e4
CW		 15341 struct intel_cursor_error_state {
15342 u32 control;
15343 u32 position;
15344 u32 base;
15345 u32 size;
52331309 15346 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 15347
15348 struct intel_pipe_error_state {
ddf9c536 15349 bool power_domain_on;
c4a1d9e4 15350 u32 source;
f301b1e1 15351 u32 stat;
52331309 15352 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 15353
15354 struct intel_plane_error_state {
15355 u32 control;
15356 u32 stride;
15357 u32 size;
15358 u32 pos;
15359 u32 addr;
15360 u32 surface;
15361 u32 tile_offset;
52331309 15362 } plane[I915_MAX_PIPES];
63b66e5b
CW		 15363
15364 struct intel_transcoder_error_state {
ddf9c536 15365 bool power_domain_on;
63b66e5b
CW		 15366 enum transcoder cpu_transcoder;
15367
15368 u32 conf;
15369
15370 u32 htotal;
15371 u32 hblank;
15372 u32 hsync;
15373 u32 vtotal;
15374 u32 vblank;
15375 u32 vsync;
15376 } transcoder[4];
c4a1d9e4
CW		 15377};
15378
15379struct intel_display_error_state *
15380intel_display_capture_error_state(struct drm_device *dev)
15381{
fbee40df 15382 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 15383 struct intel_display_error_state *error;
63b66e5b
CW		 15384 int transcoders[] = {
15385 TRANSCODER_A,
15386 TRANSCODER_B,
15387 TRANSCODER_C,
15388 TRANSCODER_EDP,
15389 };
c4a1d9e4
CW		 15390 int i;
15391
63b66e5b
CW		 15392 if (INTEL_INFO(dev)->num_pipes == 0)
15393 return NULL;
15394
9d1cb914 15395 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 15396 if (error == NULL)
15397 return NULL;
15398
190be112 15399 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 15400 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
15401
055e393f 15402 for_each_pipe(dev_priv, i) {
ddf9c536 15403 error->pipe[i].power_domain_on =
f458ebbc
DV		 15404 __intel_display_power_is_enabled(dev_priv,
15405 POWER_DOMAIN_PIPE(i));
ddf9c536 15406 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 15407 continue;
15408
5efb3e28
VS		 15409 error->cursor[i].control = I915_READ(CURCNTR(i));
15410 error->cursor[i].position = I915_READ(CURPOS(i));
15411 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 15412
15413 error->plane[i].control = I915_READ(DSPCNTR(i));
15414 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 15415 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 15416 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 15417 error->plane[i].pos = I915_READ(DSPPOS(i));
15418 }
ca291363
PZ		 15419 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
15420 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 15421 if (INTEL_INFO(dev)->gen >= 4) {
15422 error->plane[i].surface = I915_READ(DSPSURF(i));
15423 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
15424 }
15425
c4a1d9e4 15426 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 15427
3abfce77 15428 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 15429 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 15430 }
15431
15432 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
15433 if (HAS_DDI(dev_priv->dev))
15434 error->num_transcoders++; /* Account for eDP. */
15435
15436 for (i = 0; i < error->num_transcoders; i++) {
15437 enum transcoder cpu_transcoder = transcoders[i];
15438
ddf9c536 15439 error->transcoder[i].power_domain_on =
f458ebbc 15440 __intel_display_power_is_enabled(dev_priv,
38cc1daf 15441 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 15442 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 15443 continue;
15444
63b66e5b
CW		 15445 error->transcoder[i].cpu_transcoder = cpu_transcoder;
15446
15447 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
15448 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
15449 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
15450 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
15451 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
15452 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
15453 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 15454 }
15455
15456 return error;
15457}
15458
edc3d884
MK		 15459#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
15460
c4a1d9e4 15461void
edc3d884 15462intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 15463 struct drm_device *dev,
15464 struct intel_display_error_state *error)
15465{
055e393f 15466 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 15467 int i;
15468
63b66e5b
CW		 15469 if (!error)
15470 return;
15471
edc3d884 15472 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 15473 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 15474 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 15475 error->power_well_driver);
055e393f 15476 for_each_pipe(dev_priv, i) {
edc3d884 15477 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 15478 err_printf(m, " Power: %s\n",
15479 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 15480 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 15481 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 15482
15483 err_printf(m, "Plane [%d]:\n", i);
15484 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
15485 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 15486 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 15487 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
15488 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 15489 }
4b71a570 15490 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 15491 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 15492 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 15493 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
15494 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 15495 }
15496
edc3d884
MK		 15497 err_printf(m, "Cursor [%d]:\n", i);
15498 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
15499 err_printf(m, " POS: %08x\n", error->cursor[i].position);
15500 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 15501 }
63b66e5b
CW		 15502
15503 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 15504 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 15505 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 15506 err_printf(m, " Power: %s\n",
15507 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 15508 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
15509 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
15510 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
15511 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
15512 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
15513 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
15514 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
15515 }
c4a1d9e4 15516}
e2fcdaa9
VS		 15517
15518void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
15519{
15520 struct intel_crtc *crtc;
15521
15522 for_each_intel_crtc(dev, crtc) {
15523 struct intel_unpin_work *work;
e2fcdaa9 15524
5e2d7afc 15525 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 15526
15527 work = crtc->unpin_work;
15528
15529 if (work && work->event &&
15530 work->event->base.file_priv == file) {
15531 kfree(work->event);
15532 work->event = NULL;
15533 }
15534
5e2d7afc 15535 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 15536 }
15537}
Linux kernel - Deliverables
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