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drm/i915: copy fetched mode state into crtc at setup_hw time v5
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
f1f644dc
JB		 48static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
50static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
52
79e53945 53typedef struct {
0206e353 54 int min, max;
79e53945
JB		 55} intel_range_t;
56
57typedef struct {
0206e353
AJ		 58 int dot_limit;
59 int p2_slow, p2_fast;
79e53945
JB		 60} intel_p2_t;
61
62#define INTEL_P2_NUM 2
d4906093
ML		 63typedef struct intel_limit intel_limit_t;
64struct intel_limit {
0206e353
AJ		 65 intel_range_t dot, vco, n, m, m1, m2, p, p1;
66 intel_p2_t p2;
d4906093 67};
79e53945 68
2377b741
JB		 69/* FDI */
70#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
71
d2acd215
DV		 72int
73intel_pch_rawclk(struct drm_device *dev)
74{
75 struct drm_i915_private *dev_priv = dev->dev_private;
76
77 WARN_ON(!HAS_PCH_SPLIT(dev));
78
79 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
80}
81
021357ac
CW		 82static inline u32 /* units of 100MHz */
83intel_fdi_link_freq(struct drm_device *dev)
84{
8b99e68c
CW		 85 if (IS_GEN5(dev)) {
86 struct drm_i915_private *dev_priv = dev->dev_private;
87 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
88 } else
89 return 27;
021357ac
CW		 90}
91
e4b36699 92static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 93 .dot = { .min = 25000, .max = 350000 },
94 .vco = { .min = 930000, .max = 1400000 },
95 .n = { .min = 3, .max = 16 },
96 .m = { .min = 96, .max = 140 },
97 .m1 = { .min = 18, .max = 26 },
98 .m2 = { .min = 6, .max = 16 },
99 .p = { .min = 4, .max = 128 },
100 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 101 .p2 = { .dot_limit = 165000,
102 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 103};
104
105static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 106 .dot = { .min = 25000, .max = 350000 },
107 .vco = { .min = 930000, .max = 1400000 },
108 .n = { .min = 3, .max = 16 },
109 .m = { .min = 96, .max = 140 },
110 .m1 = { .min = 18, .max = 26 },
111 .m2 = { .min = 6, .max = 16 },
112 .p = { .min = 4, .max = 128 },
113 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 114 .p2 = { .dot_limit = 165000,
115 .p2_slow = 14, .p2_fast = 7 },
e4b36699 116};
273e27ca 117
e4b36699 118static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 119 .dot = { .min = 20000, .max = 400000 },
120 .vco = { .min = 1400000, .max = 2800000 },
121 .n = { .min = 1, .max = 6 },
122 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 123 .m1 = { .min = 8, .max = 18 },
124 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 125 .p = { .min = 5, .max = 80 },
126 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 127 .p2 = { .dot_limit = 200000,
128 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 129};
130
131static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 132 .dot = { .min = 20000, .max = 400000 },
133 .vco = { .min = 1400000, .max = 2800000 },
134 .n = { .min = 1, .max = 6 },
135 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 136 .m1 = { .min = 8, .max = 18 },
137 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 138 .p = { .min = 7, .max = 98 },
139 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 140 .p2 = { .dot_limit = 112000,
141 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 142};
143
273e27ca 144
e4b36699 145static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 146 .dot = { .min = 25000, .max = 270000 },
147 .vco = { .min = 1750000, .max = 3500000},
148 .n = { .min = 1, .max = 4 },
149 .m = { .min = 104, .max = 138 },
150 .m1 = { .min = 17, .max = 23 },
151 .m2 = { .min = 5, .max = 11 },
152 .p = { .min = 10, .max = 30 },
153 .p1 = { .min = 1, .max = 3},
154 .p2 = { .dot_limit = 270000,
155 .p2_slow = 10,
156 .p2_fast = 10
044c7c41 157 },
e4b36699
KP		 158};
159
160static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 161 .dot = { .min = 22000, .max = 400000 },
162 .vco = { .min = 1750000, .max = 3500000},
163 .n = { .min = 1, .max = 4 },
164 .m = { .min = 104, .max = 138 },
165 .m1 = { .min = 16, .max = 23 },
166 .m2 = { .min = 5, .max = 11 },
167 .p = { .min = 5, .max = 80 },
168 .p1 = { .min = 1, .max = 8},
169 .p2 = { .dot_limit = 165000,
170 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 171};
172
173static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 174 .dot = { .min = 20000, .max = 115000 },
175 .vco = { .min = 1750000, .max = 3500000 },
176 .n = { .min = 1, .max = 3 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 28, .max = 112 },
181 .p1 = { .min = 2, .max = 8 },
182 .p2 = { .dot_limit = 0,
183 .p2_slow = 14, .p2_fast = 14
044c7c41 184 },
e4b36699
KP		 185};
186
187static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 188 .dot = { .min = 80000, .max = 224000 },
189 .vco = { .min = 1750000, .max = 3500000 },
190 .n = { .min = 1, .max = 3 },
191 .m = { .min = 104, .max = 138 },
192 .m1 = { .min = 17, .max = 23 },
193 .m2 = { .min = 5, .max = 11 },
194 .p = { .min = 14, .max = 42 },
195 .p1 = { .min = 2, .max = 6 },
196 .p2 = { .dot_limit = 0,
197 .p2_slow = 7, .p2_fast = 7
044c7c41 198 },
e4b36699
KP		 199};
200
f2b115e6 201static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 202 .dot = { .min = 20000, .max = 400000},
203 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 204 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 205 .n = { .min = 3, .max = 6 },
206 .m = { .min = 2, .max = 256 },
273e27ca 207 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 208 .m1 = { .min = 0, .max = 0 },
209 .m2 = { .min = 0, .max = 254 },
210 .p = { .min = 5, .max = 80 },
211 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 212 .p2 = { .dot_limit = 200000,
213 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 214};
215
f2b115e6 216static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 217 .dot = { .min = 20000, .max = 400000 },
218 .vco = { .min = 1700000, .max = 3500000 },
219 .n = { .min = 3, .max = 6 },
220 .m = { .min = 2, .max = 256 },
221 .m1 = { .min = 0, .max = 0 },
222 .m2 = { .min = 0, .max = 254 },
223 .p = { .min = 7, .max = 112 },
224 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 225 .p2 = { .dot_limit = 112000,
226 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 227};
228
273e27ca
EA		 229/* Ironlake / Sandybridge
230 *
231 * We calculate clock using (register_value + 2) for N/M1/M2, so here
232 * the range value for them is (actual_value - 2).
233 */
b91ad0ec 234static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 235 .dot = { .min = 25000, .max = 350000 },
236 .vco = { .min = 1760000, .max = 3510000 },
237 .n = { .min = 1, .max = 5 },
238 .m = { .min = 79, .max = 127 },
239 .m1 = { .min = 12, .max = 22 },
240 .m2 = { .min = 5, .max = 9 },
241 .p = { .min = 5, .max = 80 },
242 .p1 = { .min = 1, .max = 8 },
243 .p2 = { .dot_limit = 225000,
244 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 245};
246
b91ad0ec 247static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 248 .dot = { .min = 25000, .max = 350000 },
249 .vco = { .min = 1760000, .max = 3510000 },
250 .n = { .min = 1, .max = 3 },
251 .m = { .min = 79, .max = 118 },
252 .m1 = { .min = 12, .max = 22 },
253 .m2 = { .min = 5, .max = 9 },
254 .p = { .min = 28, .max = 112 },
255 .p1 = { .min = 2, .max = 8 },
256 .p2 = { .dot_limit = 225000,
257 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 258};
259
260static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 261 .dot = { .min = 25000, .max = 350000 },
262 .vco = { .min = 1760000, .max = 3510000 },
263 .n = { .min = 1, .max = 3 },
264 .m = { .min = 79, .max = 127 },
265 .m1 = { .min = 12, .max = 22 },
266 .m2 = { .min = 5, .max = 9 },
267 .p = { .min = 14, .max = 56 },
268 .p1 = { .min = 2, .max = 8 },
269 .p2 = { .dot_limit = 225000,
270 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 271};
272
273e27ca 273/* LVDS 100mhz refclk limits. */
b91ad0ec 274static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 1760000, .max = 3510000 },
277 .n = { .min = 1, .max = 2 },
278 .m = { .min = 79, .max = 126 },
279 .m1 = { .min = 12, .max = 22 },
280 .m2 = { .min = 5, .max = 9 },
281 .p = { .min = 28, .max = 112 },
0206e353 282 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 283 .p2 = { .dot_limit = 225000,
284 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 285};
286
287static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 3 },
291 .m = { .min = 79, .max = 126 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 14, .max = 42 },
0206e353 295 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 298};
299
a0c4da24
JB		 300static const intel_limit_t intel_limits_vlv_dac = {
301 .dot = { .min = 25000, .max = 270000 },
302 .vco = { .min = 4000000, .max = 6000000 },
303 .n = { .min = 1, .max = 7 },
304 .m = { .min = 22, .max = 450 }, /* guess */
305 .m1 = { .min = 2, .max = 3 },
306 .m2 = { .min = 11, .max = 156 },
307 .p = { .min = 10, .max = 30 },
75e53986 308 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 309 .p2 = { .dot_limit = 270000,
310 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 311};
312
313static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 314 .dot = { .min = 25000, .max = 270000 },
315 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 316 .n = { .min = 1, .max = 7 },
317 .m = { .min = 60, .max = 300 }, /* guess */
318 .m1 = { .min = 2, .max = 3 },
319 .m2 = { .min = 11, .max = 156 },
320 .p = { .min = 10, .max = 30 },
321 .p1 = { .min = 2, .max = 3 },
322 .p2 = { .dot_limit = 270000,
323 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 324};
325
326static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 327 .dot = { .min = 25000, .max = 270000 },
328 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 329 .n = { .min = 1, .max = 7 },
74a4dd2e 330 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 331 .m1 = { .min = 2, .max = 3 },
332 .m2 = { .min = 11, .max = 156 },
333 .p = { .min = 10, .max = 30 },
75e53986 334 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 335 .p2 = { .dot_limit = 270000,
336 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 337};
338
1b894b59
CW		 339static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
340 int refclk)
2c07245f 341{
b91ad0ec 342 struct drm_device *dev = crtc->dev;
2c07245f 343 const intel_limit_t *limit;
b91ad0ec
ZW		 344
345 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 346 if (intel_is_dual_link_lvds(dev)) {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_dual_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_dual_lvds;
351 } else {
1b894b59 352 if (refclk == 100000)
b91ad0ec
ZW		 353 limit = &intel_limits_ironlake_single_lvds_100m;
354 else
355 limit = &intel_limits_ironlake_single_lvds;
356 }
c6bb3538 357 } else
b91ad0ec 358 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 359
360 return limit;
361}
362
044c7c41
ML		 363static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
364{
365 struct drm_device *dev = crtc->dev;
044c7c41
ML		 366 const intel_limit_t *limit;
367
368 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 369 if (intel_is_dual_link_lvds(dev))
e4b36699 370 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 371 else
e4b36699 372 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 373 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
374 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 375 limit = &intel_limits_g4x_hdmi;
044c7c41 376 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 377 limit = &intel_limits_g4x_sdvo;
044c7c41 378 } else /* The option is for other outputs */
e4b36699 379 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 380
381 return limit;
382}
383
1b894b59 384static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 385{
386 struct drm_device *dev = crtc->dev;
387 const intel_limit_t *limit;
388
bad720ff 389 if (HAS_PCH_SPLIT(dev))
1b894b59 390 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 391 else if (IS_G4X(dev)) {
044c7c41 392 limit = intel_g4x_limit(crtc);
f2b115e6 393 } else if (IS_PINEVIEW(dev)) {
2177832f 394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 395 limit = &intel_limits_pineview_lvds;
2177832f 396 else
f2b115e6 397 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 398 } else if (IS_VALLEYVIEW(dev)) {
399 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
400 limit = &intel_limits_vlv_dac;
401 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
402 limit = &intel_limits_vlv_hdmi;
403 else
404 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 405 } else if (!IS_GEN2(dev)) {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
407 limit = &intel_limits_i9xx_lvds;
408 else
409 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 410 } else {
411 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 412 limit = &intel_limits_i8xx_lvds;
79e53945 413 else
e4b36699 414 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 415 }
416 return limit;
417}
418
f2b115e6
AJ		 419/* m1 is reserved as 0 in Pineview, n is a ring counter */
420static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 421{
2177832f
SL		 422 clock->m = clock->m2 + 2;
423 clock->p = clock->p1 * clock->p2;
424 clock->vco = refclk * clock->m / clock->n;
425 clock->dot = clock->vco / clock->p;
426}
427
7429e9d4
DV		 428static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
429{
430 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
431}
432
ac58c3f0 433static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 434{
7429e9d4 435 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 436 clock->p = clock->p1 * clock->p2;
437 clock->vco = refclk * clock->m / (clock->n + 2);
438 clock->dot = clock->vco / clock->p;
439}
440
79e53945
JB		 441/**
442 * Returns whether any output on the specified pipe is of the specified type
443 */
4ef69c7a 444bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 445{
4ef69c7a 446 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 447 struct intel_encoder *encoder;
448
6c2b7c12
DV		 449 for_each_encoder_on_crtc(dev, crtc, encoder)
450 if (encoder->type == type)
4ef69c7a
CW		 451 return true;
452
453 return false;
79e53945
JB		 454}
455
7c04d1d9 456#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 457/**
458 * Returns whether the given set of divisors are valid for a given refclk with
459 * the given connectors.
460 */
461
1b894b59
CW		 462static bool intel_PLL_is_valid(struct drm_device *dev,
463 const intel_limit_t *limit,
464 const intel_clock_t *clock)
79e53945 465{
79e53945 466 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 467 INTELPllInvalid("p1 out of range\n");
79e53945 468 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 469 INTELPllInvalid("p out of range\n");
79e53945 470 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 471 INTELPllInvalid("m2 out of range\n");
79e53945 472 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 473 INTELPllInvalid("m1 out of range\n");
f2b115e6 474 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 475 INTELPllInvalid("m1 <= m2\n");
79e53945 476 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 477 INTELPllInvalid("m out of range\n");
79e53945 478 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 479 INTELPllInvalid("n out of range\n");
79e53945 480 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 481 INTELPllInvalid("vco out of range\n");
79e53945
JB		 482 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
483 * connector, etc., rather than just a single range.
484 */
485 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 486 INTELPllInvalid("dot out of range\n");
79e53945
JB		 487
488 return true;
489}
490
d4906093 491static bool
ee9300bb 492i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 493 int target, int refclk, intel_clock_t *match_clock,
494 intel_clock_t *best_clock)
79e53945
JB		 495{
496 struct drm_device *dev = crtc->dev;
79e53945 497 intel_clock_t clock;
79e53945
JB		 498 int err = target;
499
a210b028 500 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 501 /*
a210b028
DV		 502 * For LVDS just rely on its current settings for dual-channel.
503 * We haven't figured out how to reliably set up different
504 * single/dual channel state, if we even can.
79e53945 505 */
1974cad0 506 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 507 clock.p2 = limit->p2.p2_fast;
508 else
509 clock.p2 = limit->p2.p2_slow;
510 } else {
511 if (target < limit->p2.dot_limit)
512 clock.p2 = limit->p2.p2_slow;
513 else
514 clock.p2 = limit->p2.p2_fast;
515 }
516
0206e353 517 memset(best_clock, 0, sizeof(*best_clock));
79e53945 518
42158660
ZY		 519 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
520 clock.m1++) {
521 for (clock.m2 = limit->m2.min;
522 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 523 if (clock.m2 >= clock.m1)
42158660
ZY		 524 break;
525 for (clock.n = limit->n.min;
526 clock.n <= limit->n.max; clock.n++) {
527 for (clock.p1 = limit->p1.min;
528 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 529 int this_err;
530
ac58c3f0
DV		 531 i9xx_clock(refclk, &clock);
532 if (!intel_PLL_is_valid(dev, limit,
533 &clock))
534 continue;
535 if (match_clock &&
536 clock.p != match_clock->p)
537 continue;
538
539 this_err = abs(clock.dot - target);
540 if (this_err < err) {
541 *best_clock = clock;
542 err = this_err;
543 }
544 }
545 }
546 }
547 }
548
549 return (err != target);
550}
551
552static bool
ee9300bb
DV		 553pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
554 int target, int refclk, intel_clock_t *match_clock,
555 intel_clock_t *best_clock)
79e53945
JB		 556{
557 struct drm_device *dev = crtc->dev;
79e53945 558 intel_clock_t clock;
79e53945
JB		 559 int err = target;
560
a210b028 561 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 562 /*
a210b028
DV		 563 * For LVDS just rely on its current settings for dual-channel.
564 * We haven't figured out how to reliably set up different
565 * single/dual channel state, if we even can.
79e53945 566 */
1974cad0 567 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 568 clock.p2 = limit->p2.p2_fast;
569 else
570 clock.p2 = limit->p2.p2_slow;
571 } else {
572 if (target < limit->p2.dot_limit)
573 clock.p2 = limit->p2.p2_slow;
574 else
575 clock.p2 = limit->p2.p2_fast;
576 }
577
0206e353 578 memset(best_clock, 0, sizeof(*best_clock));
79e53945 579
42158660
ZY		 580 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
581 clock.m1++) {
582 for (clock.m2 = limit->m2.min;
583 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 584 for (clock.n = limit->n.min;
585 clock.n <= limit->n.max; clock.n++) {
586 for (clock.p1 = limit->p1.min;
587 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 588 int this_err;
589
ac58c3f0 590 pineview_clock(refclk, &clock);
1b894b59
CW		 591 if (!intel_PLL_is_valid(dev, limit,
592 &clock))
79e53945 593 continue;
cec2f356
SP		 594 if (match_clock &&
595 clock.p != match_clock->p)
596 continue;
79e53945
JB		 597
598 this_err = abs(clock.dot - target);
599 if (this_err < err) {
600 *best_clock = clock;
601 err = this_err;
602 }
603 }
604 }
605 }
606 }
607
608 return (err != target);
609}
610
d4906093 611static bool
ee9300bb
DV		 612g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
613 int target, int refclk, intel_clock_t *match_clock,
614 intel_clock_t *best_clock)
d4906093
ML		 615{
616 struct drm_device *dev = crtc->dev;
d4906093
ML		 617 intel_clock_t clock;
618 int max_n;
619 bool found;
6ba770dc
AJ		 620 /* approximately equals target * 0.00585 */
621 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 622 found = false;
623
624 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 625 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 626 clock.p2 = limit->p2.p2_fast;
627 else
628 clock.p2 = limit->p2.p2_slow;
629 } else {
630 if (target < limit->p2.dot_limit)
631 clock.p2 = limit->p2.p2_slow;
632 else
633 clock.p2 = limit->p2.p2_fast;
634 }
635
636 memset(best_clock, 0, sizeof(*best_clock));
637 max_n = limit->n.max;
f77f13e2 638 /* based on hardware requirement, prefer smaller n to precision */
d4906093 639 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 640 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 641 for (clock.m1 = limit->m1.max;
642 clock.m1 >= limit->m1.min; clock.m1--) {
643 for (clock.m2 = limit->m2.max;
644 clock.m2 >= limit->m2.min; clock.m2--) {
645 for (clock.p1 = limit->p1.max;
646 clock.p1 >= limit->p1.min; clock.p1--) {
647 int this_err;
648
ac58c3f0 649 i9xx_clock(refclk, &clock);
1b894b59
CW		 650 if (!intel_PLL_is_valid(dev, limit,
651 &clock))
d4906093 652 continue;
1b894b59
CW		 653
654 this_err = abs(clock.dot - target);
d4906093
ML		 655 if (this_err < err_most) {
656 *best_clock = clock;
657 err_most = this_err;
658 max_n = clock.n;
659 found = true;
660 }
661 }
662 }
663 }
664 }
2c07245f
ZW		 665 return found;
666}
667
a0c4da24 668static bool
ee9300bb
DV		 669vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
670 int target, int refclk, intel_clock_t *match_clock,
671 intel_clock_t *best_clock)
a0c4da24
JB		 672{
673 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
674 u32 m, n, fastclk;
675 u32 updrate, minupdate, fracbits, p;
676 unsigned long bestppm, ppm, absppm;
677 int dotclk, flag;
678
af447bd3 679 flag = 0;
a0c4da24
JB		 680 dotclk = target * 1000;
681 bestppm = 1000000;
682 ppm = absppm = 0;
683 fastclk = dotclk / (2*100);
684 updrate = 0;
685 minupdate = 19200;
686 fracbits = 1;
687 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
688 bestm1 = bestm2 = bestp1 = bestp2 = 0;
689
690 /* based on hardware requirement, prefer smaller n to precision */
691 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
692 updrate = refclk / n;
693 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
694 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
695 if (p2 > 10)
696 p2 = p2 - 1;
697 p = p1 * p2;
698 /* based on hardware requirement, prefer bigger m1,m2 values */
699 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
700 m2 = (((2*(fastclk * p * n / m1 )) +
701 refclk) / (2*refclk));
702 m = m1 * m2;
703 vco = updrate * m;
704 if (vco >= limit->vco.min && vco < limit->vco.max) {
705 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
706 absppm = (ppm > 0) ? ppm : (-ppm);
707 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
708 bestppm = 0;
709 flag = 1;
710 }
711 if (absppm < bestppm - 10) {
712 bestppm = absppm;
713 flag = 1;
714 }
715 if (flag) {
716 bestn = n;
717 bestm1 = m1;
718 bestm2 = m2;
719 bestp1 = p1;
720 bestp2 = p2;
721 flag = 0;
722 }
723 }
724 }
725 }
726 }
727 }
728 best_clock->n = bestn;
729 best_clock->m1 = bestm1;
730 best_clock->m2 = bestm2;
731 best_clock->p1 = bestp1;
732 best_clock->p2 = bestp2;
733
734 return true;
735}
a4fc5ed6 736
a5c961d1
PZ		 737enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
738 enum pipe pipe)
739{
740 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
741 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
742
3b117c8f 743 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 744}
745
a928d536
PZ		 746static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
747{
748 struct drm_i915_private *dev_priv = dev->dev_private;
749 u32 frame, frame_reg = PIPEFRAME(pipe);
750
751 frame = I915_READ(frame_reg);
752
753 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
754 DRM_DEBUG_KMS("vblank wait timed out\n");
755}
756
9d0498a2
JB		 757/**
758 * intel_wait_for_vblank - wait for vblank on a given pipe
759 * @dev: drm device
760 * @pipe: pipe to wait for
761 *
762 * Wait for vblank to occur on a given pipe. Needed for various bits of
763 * mode setting code.
764 */
765void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 766{
9d0498a2 767 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 768 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 769
a928d536
PZ		 770 if (INTEL_INFO(dev)->gen >= 5) {
771 ironlake_wait_for_vblank(dev, pipe);
772 return;
773 }
774
300387c0
CW		 775 /* Clear existing vblank status. Note this will clear any other
776 * sticky status fields as well.
777 *
778 * This races with i915_driver_irq_handler() with the result
779 * that either function could miss a vblank event. Here it is not
780 * fatal, as we will either wait upon the next vblank interrupt or
781 * timeout. Generally speaking intel_wait_for_vblank() is only
782 * called during modeset at which time the GPU should be idle and
783 * should *not* be performing page flips and thus not waiting on
784 * vblanks...
785 * Currently, the result of us stealing a vblank from the irq
786 * handler is that a single frame will be skipped during swapbuffers.
787 */
788 I915_WRITE(pipestat_reg,
789 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
790
9d0498a2 791 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 792 if (wait_for(I915_READ(pipestat_reg) &
793 PIPE_VBLANK_INTERRUPT_STATUS,
794 50))
9d0498a2
JB		 795 DRM_DEBUG_KMS("vblank wait timed out\n");
796}
797
ab7ad7f6
KP		 798/*
799 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 800 * @dev: drm device
801 * @pipe: pipe to wait for
802 *
803 * After disabling a pipe, we can't wait for vblank in the usual way,
804 * spinning on the vblank interrupt status bit, since we won't actually
805 * see an interrupt when the pipe is disabled.
806 *
ab7ad7f6
KP		 807 * On Gen4 and above:
808 * wait for the pipe register state bit to turn off
809 *
810 * Otherwise:
811 * wait for the display line value to settle (it usually
812 * ends up stopping at the start of the next frame).
58e10eb9 813 *
9d0498a2 814 */
58e10eb9 815void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 816{
817 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 818 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
819 pipe);
ab7ad7f6
KP		 820
821 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 822 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 823
824 /* Wait for the Pipe State to go off */
58e10eb9
CW		 825 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
826 100))
284637d9 827 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 828 } else {
837ba00f 829 u32 last_line, line_mask;
58e10eb9 830 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 831 unsigned long timeout = jiffies + msecs_to_jiffies(100);
832
837ba00f
PZ		 833 if (IS_GEN2(dev))
834 line_mask = DSL_LINEMASK_GEN2;
835 else
836 line_mask = DSL_LINEMASK_GEN3;
837
ab7ad7f6
KP		 838 /* Wait for the display line to settle */
839 do {
837ba00f 840 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 841 mdelay(5);
837ba00f 842 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 843 time_after(timeout, jiffies));
844 if (time_after(jiffies, timeout))
284637d9 845 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 846 }
79e53945
JB		 847}
848
b0ea7d37
DL		 849/*
850 * ibx_digital_port_connected - is the specified port connected?
851 * @dev_priv: i915 private structure
852 * @port: the port to test
853 *
854 * Returns true if @port is connected, false otherwise.
855 */
856bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
857 struct intel_digital_port *port)
858{
859 u32 bit;
860
c36346e3
DL		 861 if (HAS_PCH_IBX(dev_priv->dev)) {
862 switch(port->port) {
863 case PORT_B:
864 bit = SDE_PORTB_HOTPLUG;
865 break;
866 case PORT_C:
867 bit = SDE_PORTC_HOTPLUG;
868 break;
869 case PORT_D:
870 bit = SDE_PORTD_HOTPLUG;
871 break;
872 default:
873 return true;
874 }
875 } else {
876 switch(port->port) {
877 case PORT_B:
878 bit = SDE_PORTB_HOTPLUG_CPT;
879 break;
880 case PORT_C:
881 bit = SDE_PORTC_HOTPLUG_CPT;
882 break;
883 case PORT_D:
884 bit = SDE_PORTD_HOTPLUG_CPT;
885 break;
886 default:
887 return true;
888 }
b0ea7d37
DL		 889 }
890
891 return I915_READ(SDEISR) & bit;
892}
893
b24e7179
JB		 894static const char *state_string(bool enabled)
895{
896 return enabled ? "on" : "off";
897}
898
899/* Only for pre-ILK configs */
55607e8a
DV		 900void assert_pll(struct drm_i915_private *dev_priv,
901 enum pipe pipe, bool state)
b24e7179
JB		 902{
903 int reg;
904 u32 val;
905 bool cur_state;
906
907 reg = DPLL(pipe);
908 val = I915_READ(reg);
909 cur_state = !!(val & DPLL_VCO_ENABLE);
910 WARN(cur_state != state,
911 "PLL state assertion failure (expected %s, current %s)\n",
912 state_string(state), state_string(cur_state));
913}
b24e7179 914
55607e8a 915struct intel_shared_dpll *
e2b78267
DV		 916intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
917{
918 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
919
a43f6e0f 920 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 921 return NULL;
922
a43f6e0f 923 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 924}
925
040484af 926/* For ILK+ */
55607e8a
DV		 927void assert_shared_dpll(struct drm_i915_private *dev_priv,
928 struct intel_shared_dpll *pll,
929 bool state)
040484af 930{
040484af 931 bool cur_state;
5358901f 932 struct intel_dpll_hw_state hw_state;
040484af 933
9d82aa17
ED		 934 if (HAS_PCH_LPT(dev_priv->dev)) {
935 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
936 return;
937 }
938
92b27b08 939 if (WARN (!pll,
46edb027 940 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 941 return;
ee7b9f93 942
5358901f 943 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 944 WARN(cur_state != state,
5358901f
DV		 945 "%s assertion failure (expected %s, current %s)\n",
946 pll->name, state_string(state), state_string(cur_state));
040484af 947}
040484af
JB		 948
949static void assert_fdi_tx(struct drm_i915_private *dev_priv,
950 enum pipe pipe, bool state)
951{
952 int reg;
953 u32 val;
954 bool cur_state;
ad80a810
PZ		 955 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
956 pipe);
040484af 957
affa9354
PZ		 958 if (HAS_DDI(dev_priv->dev)) {
959 /* DDI does not have a specific FDI_TX register */
ad80a810 960 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 961 val = I915_READ(reg);
ad80a810 962 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 963 } else {
964 reg = FDI_TX_CTL(pipe);
965 val = I915_READ(reg);
966 cur_state = !!(val & FDI_TX_ENABLE);
967 }
040484af
JB		 968 WARN(cur_state != state,
969 "FDI TX state assertion failure (expected %s, current %s)\n",
970 state_string(state), state_string(cur_state));
971}
972#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
973#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
974
975static void assert_fdi_rx(struct drm_i915_private *dev_priv,
976 enum pipe pipe, bool state)
977{
978 int reg;
979 u32 val;
980 bool cur_state;
981
d63fa0dc
PZ		 982 reg = FDI_RX_CTL(pipe);
983 val = I915_READ(reg);
984 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 985 WARN(cur_state != state,
986 "FDI RX state assertion failure (expected %s, current %s)\n",
987 state_string(state), state_string(cur_state));
988}
989#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
990#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
991
992static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
993 enum pipe pipe)
994{
995 int reg;
996 u32 val;
997
998 /* ILK FDI PLL is always enabled */
999 if (dev_priv->info->gen == 5)
1000 return;
1001
bf507ef7 1002 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1003 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1004 return;
1005
040484af
JB		 1006 reg = FDI_TX_CTL(pipe);
1007 val = I915_READ(reg);
1008 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1009}
1010
55607e8a
DV		 1011void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1012 enum pipe pipe, bool state)
040484af
JB		 1013{
1014 int reg;
1015 u32 val;
55607e8a 1016 bool cur_state;
040484af
JB		 1017
1018 reg = FDI_RX_CTL(pipe);
1019 val = I915_READ(reg);
55607e8a
DV		 1020 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1021 WARN(cur_state != state,
1022 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1023 state_string(state), state_string(cur_state));
040484af
JB		 1024}
1025
ea0760cf
JB		 1026static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1027 enum pipe pipe)
1028{
1029 int pp_reg, lvds_reg;
1030 u32 val;
1031 enum pipe panel_pipe = PIPE_A;
0de3b485 1032 bool locked = true;
ea0760cf
JB		 1033
1034 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1035 pp_reg = PCH_PP_CONTROL;
1036 lvds_reg = PCH_LVDS;
1037 } else {
1038 pp_reg = PP_CONTROL;
1039 lvds_reg = LVDS;
1040 }
1041
1042 val = I915_READ(pp_reg);
1043 if (!(val & PANEL_POWER_ON) ||
1044 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1045 locked = false;
1046
1047 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1048 panel_pipe = PIPE_B;
1049
1050 WARN(panel_pipe == pipe && locked,
1051 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1052 pipe_name(pipe));
ea0760cf
JB		 1053}
1054
b840d907
JB		 1055void assert_pipe(struct drm_i915_private *dev_priv,
1056 enum pipe pipe, bool state)
b24e7179
JB		 1057{
1058 int reg;
1059 u32 val;
63d7bbe9 1060 bool cur_state;
702e7a56
PZ		 1061 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1062 pipe);
b24e7179 1063
8e636784
DV		 1064 /* if we need the pipe A quirk it must be always on */
1065 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1066 state = true;
1067
b97186f0
PZ		 1068 if (!intel_display_power_enabled(dev_priv->dev,
1069 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1070 cur_state = false;
1071 } else {
1072 reg = PIPECONF(cpu_transcoder);
1073 val = I915_READ(reg);
1074 cur_state = !!(val & PIPECONF_ENABLE);
1075 }
1076
63d7bbe9
JB		 1077 WARN(cur_state != state,
1078 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1079 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1080}
1081
931872fc
CW		 1082static void assert_plane(struct drm_i915_private *dev_priv,
1083 enum plane plane, bool state)
b24e7179
JB		 1084{
1085 int reg;
1086 u32 val;
931872fc 1087 bool cur_state;
b24e7179
JB		 1088
1089 reg = DSPCNTR(plane);
1090 val = I915_READ(reg);
931872fc
CW		 1091 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1092 WARN(cur_state != state,
1093 "plane %c assertion failure (expected %s, current %s)\n",
1094 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1095}
1096
931872fc
CW		 1097#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1098#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1099
b24e7179
JB		 1100static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1101 enum pipe pipe)
1102{
653e1026 1103 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1104 int reg, i;
1105 u32 val;
1106 int cur_pipe;
1107
653e1026
VS		 1108 /* Primary planes are fixed to pipes on gen4+ */
1109 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1110 reg = DSPCNTR(pipe);
1111 val = I915_READ(reg);
1112 WARN((val & DISPLAY_PLANE_ENABLE),
1113 "plane %c assertion failure, should be disabled but not\n",
1114 plane_name(pipe));
19ec1358 1115 return;
28c05794 1116 }
19ec1358 1117
b24e7179 1118 /* Need to check both planes against the pipe */
653e1026 1119 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
b24e7179
JB		 1120 reg = DSPCNTR(i);
1121 val = I915_READ(reg);
1122 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1123 DISPPLANE_SEL_PIPE_SHIFT;
1124 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1125 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1126 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1127 }
1128}
1129
19332d7a
JB		 1130static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1131 enum pipe pipe)
1132{
20674eef 1133 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1134 int reg, i;
1135 u32 val;
1136
20674eef
VS		 1137 if (IS_VALLEYVIEW(dev)) {
1138 for (i = 0; i < dev_priv->num_plane; i++) {
1139 reg = SPCNTR(pipe, i);
1140 val = I915_READ(reg);
1141 WARN((val & SP_ENABLE),
1142 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1143 sprite_name(pipe, i), pipe_name(pipe));
1144 }
1145 } else if (INTEL_INFO(dev)->gen >= 7) {
1146 reg = SPRCTL(pipe);
19332d7a 1147 val = I915_READ(reg);
20674eef 1148 WARN((val & SPRITE_ENABLE),
06da8da2 1149 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1150 plane_name(pipe), pipe_name(pipe));
1151 } else if (INTEL_INFO(dev)->gen >= 5) {
1152 reg = DVSCNTR(pipe);
19332d7a 1153 val = I915_READ(reg);
20674eef 1154 WARN((val & DVS_ENABLE),
06da8da2 1155 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1156 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1157 }
1158}
1159
92f2584a
JB		 1160static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1161{
1162 u32 val;
1163 bool enabled;
1164
9d82aa17
ED		 1165 if (HAS_PCH_LPT(dev_priv->dev)) {
1166 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1167 return;
1168 }
1169
92f2584a
JB		 1170 val = I915_READ(PCH_DREF_CONTROL);
1171 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1172 DREF_SUPERSPREAD_SOURCE_MASK));
1173 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1174}
1175
ab9412ba
DV		 1176static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1177 enum pipe pipe)
92f2584a
JB		 1178{
1179 int reg;
1180 u32 val;
1181 bool enabled;
1182
ab9412ba 1183 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1184 val = I915_READ(reg);
1185 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1186 WARN(enabled,
1187 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1188 pipe_name(pipe));
92f2584a
JB		 1189}
1190
4e634389
KP		 1191static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1192 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1193{
1194 if ((val & DP_PORT_EN) == 0)
1195 return false;
1196
1197 if (HAS_PCH_CPT(dev_priv->dev)) {
1198 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1199 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1200 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1201 return false;
1202 } else {
1203 if ((val & DP_PIPE_MASK) != (pipe << 30))
1204 return false;
1205 }
1206 return true;
1207}
1208
1519b995
KP		 1209static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, u32 val)
1211{
dc0fa718 1212 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1213 return false;
1214
1215 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1216 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1217 return false;
1218 } else {
dc0fa718 1219 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1220 return false;
1221 }
1222 return true;
1223}
1224
1225static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1226 enum pipe pipe, u32 val)
1227{
1228 if ((val & LVDS_PORT_EN) == 0)
1229 return false;
1230
1231 if (HAS_PCH_CPT(dev_priv->dev)) {
1232 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1233 return false;
1234 } else {
1235 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1236 return false;
1237 }
1238 return true;
1239}
1240
1241static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1242 enum pipe pipe, u32 val)
1243{
1244 if ((val & ADPA_DAC_ENABLE) == 0)
1245 return false;
1246 if (HAS_PCH_CPT(dev_priv->dev)) {
1247 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1248 return false;
1249 } else {
1250 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1251 return false;
1252 }
1253 return true;
1254}
1255
291906f1 1256static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1257 enum pipe pipe, int reg, u32 port_sel)
291906f1 1258{
47a05eca 1259 u32 val = I915_READ(reg);
4e634389 1260 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1261 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1262 reg, pipe_name(pipe));
de9a35ab 1263
75c5da27
DV		 1264 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1265 && (val & DP_PIPEB_SELECT),
de9a35ab 1266 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1267}
1268
1269static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1270 enum pipe pipe, int reg)
1271{
47a05eca 1272 u32 val = I915_READ(reg);
b70ad586 1273 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1274 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1275 reg, pipe_name(pipe));
de9a35ab 1276
dc0fa718 1277 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1278 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1279 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1280}
1281
1282static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1283 enum pipe pipe)
1284{
1285 int reg;
1286 u32 val;
291906f1 1287
f0575e92
KP		 1288 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1289 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1290 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1291
1292 reg = PCH_ADPA;
1293 val = I915_READ(reg);
b70ad586 1294 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1295 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1296 pipe_name(pipe));
291906f1
JB		 1297
1298 reg = PCH_LVDS;
1299 val = I915_READ(reg);
b70ad586 1300 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1301 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1302 pipe_name(pipe));
291906f1 1303
e2debe91
PZ		 1304 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1305 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1306 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1307}
1308
87442f73
DV		 1309static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1310{
1311 int reg;
1312 u32 val;
1313
1314 assert_pipe_disabled(dev_priv, pipe);
1315
1316 /* No really, not for ILK+ */
1317 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1318
1319 /* PLL is protected by panel, make sure we can write it */
1320 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1321 assert_panel_unlocked(dev_priv, pipe);
1322
1323 reg = DPLL(pipe);
1324 val = I915_READ(reg);
1325 val |= DPLL_VCO_ENABLE;
1326
1327 /* We do this three times for luck */
1328 I915_WRITE(reg, val);
1329 POSTING_READ(reg);
1330 udelay(150); /* wait for warmup */
1331 I915_WRITE(reg, val);
1332 POSTING_READ(reg);
1333 udelay(150); /* wait for warmup */
1334 I915_WRITE(reg, val);
1335 POSTING_READ(reg);
1336 udelay(150); /* wait for warmup */
1337}
1338
66e3d5c0 1339static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1340{
66e3d5c0
DV		 1341 struct drm_device *dev = crtc->base.dev;
1342 struct drm_i915_private *dev_priv = dev->dev_private;
1343 int reg = DPLL(crtc->pipe);
1344 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1345
66e3d5c0 1346 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1347
63d7bbe9 1348 /* No really, not for ILK+ */
87442f73 1349 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1350
1351 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1352 if (IS_MOBILE(dev) && !IS_I830(dev))
1353 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1354
66e3d5c0
DV		 1355 I915_WRITE(reg, dpll);
1356
1357 /* Wait for the clocks to stabilize. */
1358 POSTING_READ(reg);
1359 udelay(150);
1360
1361 if (INTEL_INFO(dev)->gen >= 4) {
1362 I915_WRITE(DPLL_MD(crtc->pipe),
1363 crtc->config.dpll_hw_state.dpll_md);
1364 } else {
1365 /* The pixel multiplier can only be updated once the
1366 * DPLL is enabled and the clocks are stable.
1367 *
1368 * So write it again.
1369 */
1370 I915_WRITE(reg, dpll);
1371 }
63d7bbe9
JB		 1372
1373 /* We do this three times for luck */
66e3d5c0 1374 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1375 POSTING_READ(reg);
1376 udelay(150); /* wait for warmup */
66e3d5c0 1377 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1378 POSTING_READ(reg);
1379 udelay(150); /* wait for warmup */
66e3d5c0 1380 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1381 POSTING_READ(reg);
1382 udelay(150); /* wait for warmup */
1383}
1384
1385/**
1386 * intel_disable_pll - disable a PLL
1387 * @dev_priv: i915 private structure
1388 * @pipe: pipe PLL to disable
1389 *
1390 * Disable the PLL for @pipe, making sure the pipe is off first.
1391 *
1392 * Note! This is for pre-ILK only.
1393 */
1394static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1395{
1396 int reg;
1397 u32 val;
1398
1399 /* Don't disable pipe A or pipe A PLLs if needed */
1400 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1401 return;
1402
1403 /* Make sure the pipe isn't still relying on us */
1404 assert_pipe_disabled(dev_priv, pipe);
1405
1406 reg = DPLL(pipe);
1407 val = I915_READ(reg);
1408 val &= ~DPLL_VCO_ENABLE;
1409 I915_WRITE(reg, val);
1410 POSTING_READ(reg);
1411}
1412
89b667f8
JB		 1413void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1414{
1415 u32 port_mask;
1416
1417 if (!port)
1418 port_mask = DPLL_PORTB_READY_MASK;
1419 else
1420 port_mask = DPLL_PORTC_READY_MASK;
1421
1422 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1423 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1424 'B' + port, I915_READ(DPLL(0)));
1425}
1426
92f2584a 1427/**
e72f9fbf 1428 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1429 * @dev_priv: i915 private structure
1430 * @pipe: pipe PLL to enable
1431 *
1432 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1433 * drives the transcoder clock.
1434 */
e2b78267 1435static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1436{
e2b78267
DV		 1437 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1438 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1439
48da64a8 1440 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1441 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1442 if (WARN_ON(pll == NULL))
48da64a8
CW		 1443 return;
1444
1445 if (WARN_ON(pll->refcount == 0))
1446 return;
ee7b9f93 1447
46edb027
DV		 1448 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1449 pll->name, pll->active, pll->on,
e2b78267 1450 crtc->base.base.id);
92f2584a 1451
cdbd2316
DV		 1452 if (pll->active++) {
1453 WARN_ON(!pll->on);
e9d6944e 1454 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1455 return;
1456 }
f4a091c7 1457 WARN_ON(pll->on);
ee7b9f93 1458
46edb027 1459 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1460 pll->enable(dev_priv, pll);
ee7b9f93 1461 pll->on = true;
92f2584a
JB		 1462}
1463
e2b78267 1464static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1465{
e2b78267
DV		 1466 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1467 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1468
92f2584a
JB		 1469 /* PCH only available on ILK+ */
1470 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1471 if (WARN_ON(pll == NULL))
ee7b9f93 1472 return;
92f2584a 1473
48da64a8
CW		 1474 if (WARN_ON(pll->refcount == 0))
1475 return;
7a419866 1476
46edb027
DV		 1477 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1478 pll->name, pll->active, pll->on,
e2b78267 1479 crtc->base.base.id);
7a419866 1480
48da64a8 1481 if (WARN_ON(pll->active == 0)) {
e9d6944e 1482 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1483 return;
1484 }
1485
e9d6944e 1486 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1487 WARN_ON(!pll->on);
cdbd2316 1488 if (--pll->active)
7a419866 1489 return;
ee7b9f93 1490
46edb027 1491 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1492 pll->disable(dev_priv, pll);
ee7b9f93 1493 pll->on = false;
92f2584a
JB		 1494}
1495
b8a4f404
PZ		 1496static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1497 enum pipe pipe)
040484af 1498{
23670b32 1499 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1500 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1501 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1502 uint32_t reg, val, pipeconf_val;
040484af
JB		 1503
1504 /* PCH only available on ILK+ */
1505 BUG_ON(dev_priv->info->gen < 5);
1506
1507 /* Make sure PCH DPLL is enabled */
e72f9fbf 1508 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1509 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1510
1511 /* FDI must be feeding us bits for PCH ports */
1512 assert_fdi_tx_enabled(dev_priv, pipe);
1513 assert_fdi_rx_enabled(dev_priv, pipe);
1514
23670b32
DV		 1515 if (HAS_PCH_CPT(dev)) {
1516 /* Workaround: Set the timing override bit before enabling the
1517 * pch transcoder. */
1518 reg = TRANS_CHICKEN2(pipe);
1519 val = I915_READ(reg);
1520 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1521 I915_WRITE(reg, val);
59c859d6 1522 }
23670b32 1523
ab9412ba 1524 reg = PCH_TRANSCONF(pipe);
040484af 1525 val = I915_READ(reg);
5f7f726d 1526 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1527
1528 if (HAS_PCH_IBX(dev_priv->dev)) {
1529 /*
1530 * make the BPC in transcoder be consistent with
1531 * that in pipeconf reg.
1532 */
dfd07d72
DV		 1533 val &= ~PIPECONF_BPC_MASK;
1534 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1535 }
5f7f726d
PZ		 1536
1537 val &= ~TRANS_INTERLACE_MASK;
1538 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1539 if (HAS_PCH_IBX(dev_priv->dev) &&
1540 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1541 val |= TRANS_LEGACY_INTERLACED_ILK;
1542 else
1543 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1544 else
1545 val |= TRANS_PROGRESSIVE;
1546
040484af
JB		 1547 I915_WRITE(reg, val | TRANS_ENABLE);
1548 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1549 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1550}
1551
8fb033d7 1552static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1553 enum transcoder cpu_transcoder)
040484af 1554{
8fb033d7 1555 u32 val, pipeconf_val;
8fb033d7
PZ		 1556
1557 /* PCH only available on ILK+ */
1558 BUG_ON(dev_priv->info->gen < 5);
1559
8fb033d7 1560 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1561 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1562 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1563
223a6fdf
PZ		 1564 /* Workaround: set timing override bit. */
1565 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1566 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1567 I915_WRITE(_TRANSA_CHICKEN2, val);
1568
25f3ef11 1569 val = TRANS_ENABLE;
937bb610 1570 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1571
9a76b1c6
PZ		 1572 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1573 PIPECONF_INTERLACED_ILK)
a35f2679 1574 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1575 else
1576 val |= TRANS_PROGRESSIVE;
1577
ab9412ba
DV		 1578 I915_WRITE(LPT_TRANSCONF, val);
1579 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1580 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1581}
1582
b8a4f404
PZ		 1583static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1584 enum pipe pipe)
040484af 1585{
23670b32
DV		 1586 struct drm_device *dev = dev_priv->dev;
1587 uint32_t reg, val;
040484af
JB		 1588
1589 /* FDI relies on the transcoder */
1590 assert_fdi_tx_disabled(dev_priv, pipe);
1591 assert_fdi_rx_disabled(dev_priv, pipe);
1592
291906f1
JB		 1593 /* Ports must be off as well */
1594 assert_pch_ports_disabled(dev_priv, pipe);
1595
ab9412ba 1596 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1597 val = I915_READ(reg);
1598 val &= ~TRANS_ENABLE;
1599 I915_WRITE(reg, val);
1600 /* wait for PCH transcoder off, transcoder state */
1601 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1602 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1603
1604 if (!HAS_PCH_IBX(dev)) {
1605 /* Workaround: Clear the timing override chicken bit again. */
1606 reg = TRANS_CHICKEN2(pipe);
1607 val = I915_READ(reg);
1608 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1609 I915_WRITE(reg, val);
1610 }
040484af
JB		 1611}
1612
ab4d966c 1613static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1614{
8fb033d7
PZ		 1615 u32 val;
1616
ab9412ba 1617 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1618 val &= ~TRANS_ENABLE;
ab9412ba 1619 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1620 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1621 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1622 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1623
1624 /* Workaround: clear timing override bit. */
1625 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1626 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1627 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1628}
1629
b24e7179 1630/**
309cfea8 1631 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1632 * @dev_priv: i915 private structure
1633 * @pipe: pipe to enable
040484af 1634 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1635 *
1636 * Enable @pipe, making sure that various hardware specific requirements
1637 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1638 *
1639 * @pipe should be %PIPE_A or %PIPE_B.
1640 *
1641 * Will wait until the pipe is actually running (i.e. first vblank) before
1642 * returning.
1643 */
040484af
JB		 1644static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1645 bool pch_port)
b24e7179 1646{
702e7a56
PZ		 1647 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1648 pipe);
1a240d4d 1649 enum pipe pch_transcoder;
b24e7179
JB		 1650 int reg;
1651 u32 val;
1652
58c6eaa2
DV		 1653 assert_planes_disabled(dev_priv, pipe);
1654 assert_sprites_disabled(dev_priv, pipe);
1655
681e5811 1656 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1657 pch_transcoder = TRANSCODER_A;
1658 else
1659 pch_transcoder = pipe;
1660
b24e7179
JB		 1661 /*
1662 * A pipe without a PLL won't actually be able to drive bits from
1663 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1664 * need the check.
1665 */
1666 if (!HAS_PCH_SPLIT(dev_priv->dev))
1667 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1668 else {
1669 if (pch_port) {
1670 /* if driving the PCH, we need FDI enabled */
cc391bbb 1671 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1672 assert_fdi_tx_pll_enabled(dev_priv,
1673 (enum pipe) cpu_transcoder);
040484af
JB		 1674 }
1675 /* FIXME: assert CPU port conditions for SNB+ */
1676 }
b24e7179 1677
702e7a56 1678 reg = PIPECONF(cpu_transcoder);
b24e7179 1679 val = I915_READ(reg);
00d70b15
CW		 1680 if (val & PIPECONF_ENABLE)
1681 return;
1682
1683 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1684 intel_wait_for_vblank(dev_priv->dev, pipe);
1685}
1686
1687/**
309cfea8 1688 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1689 * @dev_priv: i915 private structure
1690 * @pipe: pipe to disable
1691 *
1692 * Disable @pipe, making sure that various hardware specific requirements
1693 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1694 *
1695 * @pipe should be %PIPE_A or %PIPE_B.
1696 *
1697 * Will wait until the pipe has shut down before returning.
1698 */
1699static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1700 enum pipe pipe)
1701{
702e7a56
PZ		 1702 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1703 pipe);
b24e7179
JB		 1704 int reg;
1705 u32 val;
1706
1707 /*
1708 * Make sure planes won't keep trying to pump pixels to us,
1709 * or we might hang the display.
1710 */
1711 assert_planes_disabled(dev_priv, pipe);
19332d7a 1712 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1713
1714 /* Don't disable pipe A or pipe A PLLs if needed */
1715 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1716 return;
1717
702e7a56 1718 reg = PIPECONF(cpu_transcoder);
b24e7179 1719 val = I915_READ(reg);
00d70b15
CW		 1720 if ((val & PIPECONF_ENABLE) == 0)
1721 return;
1722
1723 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1724 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1725}
1726
d74362c9
KP		 1727/*
1728 * Plane regs are double buffered, going from enabled->disabled needs a
1729 * trigger in order to latch. The display address reg provides this.
1730 */
6f1d69b0 1731void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1732 enum plane plane)
1733{
14f86147
DL		 1734 if (dev_priv->info->gen >= 4)
1735 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1736 else
1737 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1738}
1739
b24e7179
JB		 1740/**
1741 * intel_enable_plane - enable a display plane on a given pipe
1742 * @dev_priv: i915 private structure
1743 * @plane: plane to enable
1744 * @pipe: pipe being fed
1745 *
1746 * Enable @plane on @pipe, making sure that @pipe is running first.
1747 */
1748static void intel_enable_plane(struct drm_i915_private *dev_priv,
1749 enum plane plane, enum pipe pipe)
1750{
1751 int reg;
1752 u32 val;
1753
1754 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1755 assert_pipe_enabled(dev_priv, pipe);
1756
1757 reg = DSPCNTR(plane);
1758 val = I915_READ(reg);
00d70b15
CW		 1759 if (val & DISPLAY_PLANE_ENABLE)
1760 return;
1761
1762 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1763 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1764 intel_wait_for_vblank(dev_priv->dev, pipe);
1765}
1766
b24e7179
JB		 1767/**
1768 * intel_disable_plane - disable a display plane
1769 * @dev_priv: i915 private structure
1770 * @plane: plane to disable
1771 * @pipe: pipe consuming the data
1772 *
1773 * Disable @plane; should be an independent operation.
1774 */
1775static void intel_disable_plane(struct drm_i915_private *dev_priv,
1776 enum plane plane, enum pipe pipe)
1777{
1778 int reg;
1779 u32 val;
1780
1781 reg = DSPCNTR(plane);
1782 val = I915_READ(reg);
00d70b15
CW		 1783 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1784 return;
1785
1786 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1787 intel_flush_display_plane(dev_priv, plane);
1788 intel_wait_for_vblank(dev_priv->dev, pipe);
1789}
1790
693db184
CW		 1791static bool need_vtd_wa(struct drm_device *dev)
1792{
1793#ifdef CONFIG_INTEL_IOMMU
1794 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1795 return true;
1796#endif
1797 return false;
1798}
1799
127bd2ac 1800int
48b956c5 1801intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1802 struct drm_i915_gem_object *obj,
919926ae 1803 struct intel_ring_buffer *pipelined)
6b95a207 1804{
ce453d81 1805 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1806 u32 alignment;
1807 int ret;
1808
05394f39 1809 switch (obj->tiling_mode) {
6b95a207 1810 case I915_TILING_NONE:
534843da
CW		 1811 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1812 alignment = 128 * 1024;
a6c45cf0 1813 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1814 alignment = 4 * 1024;
1815 else
1816 alignment = 64 * 1024;
6b95a207
KH		 1817 break;
1818 case I915_TILING_X:
1819 /* pin() will align the object as required by fence */
1820 alignment = 0;
1821 break;
1822 case I915_TILING_Y:
8bb6e959
DV		 1823 /* Despite that we check this in framebuffer_init userspace can
1824 * screw us over and change the tiling after the fact. Only
1825 * pinned buffers can't change their tiling. */
1826 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1827 return -EINVAL;
1828 default:
1829 BUG();
1830 }
1831
693db184
CW		 1832 /* Note that the w/a also requires 64 PTE of padding following the
1833 * bo. We currently fill all unused PTE with the shadow page and so
1834 * we should always have valid PTE following the scanout preventing
1835 * the VT-d warning.
1836 */
1837 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1838 alignment = 256 * 1024;
1839
ce453d81 1840 dev_priv->mm.interruptible = false;
2da3b9b9 1841 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1842 if (ret)
ce453d81 1843 goto err_interruptible;
6b95a207
KH		 1844
1845 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1846 * fence, whereas 965+ only requires a fence if using
1847 * framebuffer compression. For simplicity, we always install
1848 * a fence as the cost is not that onerous.
1849 */
06d98131 1850 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1851 if (ret)
1852 goto err_unpin;
1690e1eb 1853
9a5a53b3 1854 i915_gem_object_pin_fence(obj);
6b95a207 1855
ce453d81 1856 dev_priv->mm.interruptible = true;
6b95a207 1857 return 0;
48b956c5
CW		 1858
1859err_unpin:
1860 i915_gem_object_unpin(obj);
ce453d81
CW		 1861err_interruptible:
1862 dev_priv->mm.interruptible = true;
48b956c5 1863 return ret;
6b95a207
KH		 1864}
1865
1690e1eb
CW		 1866void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1867{
1868 i915_gem_object_unpin_fence(obj);
1869 i915_gem_object_unpin(obj);
1870}
1871
c2c75131
DV		 1872/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1873 * is assumed to be a power-of-two. */
bc752862
CW		 1874unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1875 unsigned int tiling_mode,
1876 unsigned int cpp,
1877 unsigned int pitch)
c2c75131 1878{
bc752862
CW		 1879 if (tiling_mode != I915_TILING_NONE) {
1880 unsigned int tile_rows, tiles;
c2c75131 1881
bc752862
CW		 1882 tile_rows = *y / 8;
1883 *y %= 8;
c2c75131 1884
bc752862
CW		 1885 tiles = *x / (512/cpp);
1886 *x %= 512/cpp;
1887
1888 return tile_rows * pitch * 8 + tiles * 4096;
1889 } else {
1890 unsigned int offset;
1891
1892 offset = *y * pitch + *x * cpp;
1893 *y = 0;
1894 *x = (offset & 4095) / cpp;
1895 return offset & -4096;
1896 }
c2c75131
DV		 1897}
1898
17638cd6
JB		 1899static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1900 int x, int y)
81255565
JB		 1901{
1902 struct drm_device *dev = crtc->dev;
1903 struct drm_i915_private *dev_priv = dev->dev_private;
1904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1905 struct intel_framebuffer *intel_fb;
05394f39 1906 struct drm_i915_gem_object *obj;
81255565 1907 int plane = intel_crtc->plane;
e506a0c6 1908 unsigned long linear_offset;
81255565 1909 u32 dspcntr;
5eddb70b 1910 u32 reg;
81255565
JB		 1911
1912 switch (plane) {
1913 case 0:
1914 case 1:
1915 break;
1916 default:
84f44ce7 1917 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1918 return -EINVAL;
1919 }
1920
1921 intel_fb = to_intel_framebuffer(fb);
1922 obj = intel_fb->obj;
81255565 1923
5eddb70b
CW		 1924 reg = DSPCNTR(plane);
1925 dspcntr = I915_READ(reg);
81255565
JB		 1926 /* Mask out pixel format bits in case we change it */
1927 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1928 switch (fb->pixel_format) {
1929 case DRM_FORMAT_C8:
81255565
JB		 1930 dspcntr |= DISPPLANE_8BPP;
1931 break;
57779d06
VS		 1932 case DRM_FORMAT_XRGB1555:
1933 case DRM_FORMAT_ARGB1555:
1934 dspcntr |= DISPPLANE_BGRX555;
81255565 1935 break;
57779d06
VS		 1936 case DRM_FORMAT_RGB565:
1937 dspcntr |= DISPPLANE_BGRX565;
1938 break;
1939 case DRM_FORMAT_XRGB8888:
1940 case DRM_FORMAT_ARGB8888:
1941 dspcntr |= DISPPLANE_BGRX888;
1942 break;
1943 case DRM_FORMAT_XBGR8888:
1944 case DRM_FORMAT_ABGR8888:
1945 dspcntr |= DISPPLANE_RGBX888;
1946 break;
1947 case DRM_FORMAT_XRGB2101010:
1948 case DRM_FORMAT_ARGB2101010:
1949 dspcntr |= DISPPLANE_BGRX101010;
1950 break;
1951 case DRM_FORMAT_XBGR2101010:
1952 case DRM_FORMAT_ABGR2101010:
1953 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1954 break;
1955 default:
baba133a 1956 BUG();
81255565 1957 }
57779d06 1958
a6c45cf0 1959 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1960 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1961 dspcntr |= DISPPLANE_TILED;
1962 else
1963 dspcntr &= ~DISPPLANE_TILED;
1964 }
1965
de1aa629
VS		 1966 if (IS_G4X(dev))
1967 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1968
5eddb70b 1969 I915_WRITE(reg, dspcntr);
81255565 1970
e506a0c6 1971 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1972
c2c75131
DV		 1973 if (INTEL_INFO(dev)->gen >= 4) {
1974 intel_crtc->dspaddr_offset =
bc752862
CW		 1975 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1976 fb->bits_per_pixel / 8,
1977 fb->pitches[0]);
c2c75131
DV		 1978 linear_offset -= intel_crtc->dspaddr_offset;
1979 } else {
e506a0c6 1980 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 1981 }
e506a0c6
DV		 1982
1983 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1984 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 1985 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1986 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 1987 I915_MODIFY_DISPBASE(DSPSURF(plane),
1988 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 1989 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 1990 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 1991 } else
e506a0c6 1992 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 1993 POSTING_READ(reg);
81255565 1994
17638cd6
JB		 1995 return 0;
1996}
1997
1998static int ironlake_update_plane(struct drm_crtc *crtc,
1999 struct drm_framebuffer *fb, int x, int y)
2000{
2001 struct drm_device *dev = crtc->dev;
2002 struct drm_i915_private *dev_priv = dev->dev_private;
2003 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2004 struct intel_framebuffer *intel_fb;
2005 struct drm_i915_gem_object *obj;
2006 int plane = intel_crtc->plane;
e506a0c6 2007 unsigned long linear_offset;
17638cd6
JB		 2008 u32 dspcntr;
2009 u32 reg;
2010
2011 switch (plane) {
2012 case 0:
2013 case 1:
27f8227b 2014 case 2:
17638cd6
JB		 2015 break;
2016 default:
84f44ce7 2017 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2018 return -EINVAL;
2019 }
2020
2021 intel_fb = to_intel_framebuffer(fb);
2022 obj = intel_fb->obj;
2023
2024 reg = DSPCNTR(plane);
2025 dspcntr = I915_READ(reg);
2026 /* Mask out pixel format bits in case we change it */
2027 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2028 switch (fb->pixel_format) {
2029 case DRM_FORMAT_C8:
17638cd6
JB		 2030 dspcntr |= DISPPLANE_8BPP;
2031 break;
57779d06
VS		 2032 case DRM_FORMAT_RGB565:
2033 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2034 break;
57779d06
VS		 2035 case DRM_FORMAT_XRGB8888:
2036 case DRM_FORMAT_ARGB8888:
2037 dspcntr |= DISPPLANE_BGRX888;
2038 break;
2039 case DRM_FORMAT_XBGR8888:
2040 case DRM_FORMAT_ABGR8888:
2041 dspcntr |= DISPPLANE_RGBX888;
2042 break;
2043 case DRM_FORMAT_XRGB2101010:
2044 case DRM_FORMAT_ARGB2101010:
2045 dspcntr |= DISPPLANE_BGRX101010;
2046 break;
2047 case DRM_FORMAT_XBGR2101010:
2048 case DRM_FORMAT_ABGR2101010:
2049 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2050 break;
2051 default:
baba133a 2052 BUG();
17638cd6
JB		 2053 }
2054
2055 if (obj->tiling_mode != I915_TILING_NONE)
2056 dspcntr |= DISPPLANE_TILED;
2057 else
2058 dspcntr &= ~DISPPLANE_TILED;
2059
2060 /* must disable */
2061 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2062
2063 I915_WRITE(reg, dspcntr);
2064
e506a0c6 2065 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2066 intel_crtc->dspaddr_offset =
bc752862
CW		 2067 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2068 fb->bits_per_pixel / 8,
2069 fb->pitches[0]);
c2c75131 2070 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2071
e506a0c6
DV		 2072 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2073 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2074 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2075 I915_MODIFY_DISPBASE(DSPSURF(plane),
2076 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2077 if (IS_HASWELL(dev)) {
2078 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2079 } else {
2080 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2081 I915_WRITE(DSPLINOFF(plane), linear_offset);
2082 }
17638cd6
JB		 2083 POSTING_READ(reg);
2084
2085 return 0;
2086}
2087
2088/* Assume fb object is pinned & idle & fenced and just update base pointers */
2089static int
2090intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2091 int x, int y, enum mode_set_atomic state)
2092{
2093 struct drm_device *dev = crtc->dev;
2094 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2095
6b8e6ed0
CW		 2096 if (dev_priv->display.disable_fbc)
2097 dev_priv->display.disable_fbc(dev);
3dec0095 2098 intel_increase_pllclock(crtc);
81255565 2099
6b8e6ed0 2100 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2101}
2102
96a02917
VS		 2103void intel_display_handle_reset(struct drm_device *dev)
2104{
2105 struct drm_i915_private *dev_priv = dev->dev_private;
2106 struct drm_crtc *crtc;
2107
2108 /*
2109 * Flips in the rings have been nuked by the reset,
2110 * so complete all pending flips so that user space
2111 * will get its events and not get stuck.
2112 *
2113 * Also update the base address of all primary
2114 * planes to the the last fb to make sure we're
2115 * showing the correct fb after a reset.
2116 *
2117 * Need to make two loops over the crtcs so that we
2118 * don't try to grab a crtc mutex before the
2119 * pending_flip_queue really got woken up.
2120 */
2121
2122 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2124 enum plane plane = intel_crtc->plane;
2125
2126 intel_prepare_page_flip(dev, plane);
2127 intel_finish_page_flip_plane(dev, plane);
2128 }
2129
2130 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2131 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2132
2133 mutex_lock(&crtc->mutex);
2134 if (intel_crtc->active)
2135 dev_priv->display.update_plane(crtc, crtc->fb,
2136 crtc->x, crtc->y);
2137 mutex_unlock(&crtc->mutex);
2138 }
2139}
2140
14667a4b
CW		 2141static int
2142intel_finish_fb(struct drm_framebuffer *old_fb)
2143{
2144 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2145 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2146 bool was_interruptible = dev_priv->mm.interruptible;
2147 int ret;
2148
14667a4b
CW		 2149 /* Big Hammer, we also need to ensure that any pending
2150 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2151 * current scanout is retired before unpinning the old
2152 * framebuffer.
2153 *
2154 * This should only fail upon a hung GPU, in which case we
2155 * can safely continue.
2156 */
2157 dev_priv->mm.interruptible = false;
2158 ret = i915_gem_object_finish_gpu(obj);
2159 dev_priv->mm.interruptible = was_interruptible;
2160
2161 return ret;
2162}
2163
198598d0
VS		 2164static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2165{
2166 struct drm_device *dev = crtc->dev;
2167 struct drm_i915_master_private *master_priv;
2168 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2169
2170 if (!dev->primary->master)
2171 return;
2172
2173 master_priv = dev->primary->master->driver_priv;
2174 if (!master_priv->sarea_priv)
2175 return;
2176
2177 switch (intel_crtc->pipe) {
2178 case 0:
2179 master_priv->sarea_priv->pipeA_x = x;
2180 master_priv->sarea_priv->pipeA_y = y;
2181 break;
2182 case 1:
2183 master_priv->sarea_priv->pipeB_x = x;
2184 master_priv->sarea_priv->pipeB_y = y;
2185 break;
2186 default:
2187 break;
2188 }
2189}
2190
5c3b82e2 2191static int
3c4fdcfb 2192intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2193 struct drm_framebuffer *fb)
79e53945
JB		 2194{
2195 struct drm_device *dev = crtc->dev;
6b8e6ed0 2196 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2198 struct drm_framebuffer *old_fb;
5c3b82e2 2199 int ret;
79e53945
JB		 2200
2201 /* no fb bound */
94352cf9 2202 if (!fb) {
a5071c2f 2203 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2204 return 0;
2205 }
2206
7eb552ae 2207 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2208 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2209 plane_name(intel_crtc->plane),
2210 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2211 return -EINVAL;
79e53945
JB		 2212 }
2213
5c3b82e2 2214 mutex_lock(&dev->struct_mutex);
265db958 2215 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2216 to_intel_framebuffer(fb)->obj,
919926ae 2217 NULL);
5c3b82e2
CW		 2218 if (ret != 0) {
2219 mutex_unlock(&dev->struct_mutex);
a5071c2f 2220 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2221 return ret;
2222 }
79e53945 2223
94352cf9 2224 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2225 if (ret) {
94352cf9 2226 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2227 mutex_unlock(&dev->struct_mutex);
a5071c2f 2228 DRM_ERROR("failed to update base address\n");
4e6cfefc 2229 return ret;
79e53945 2230 }
3c4fdcfb 2231
94352cf9
DV		 2232 old_fb = crtc->fb;
2233 crtc->fb = fb;
6c4c86f5
DV		 2234 crtc->x = x;
2235 crtc->y = y;
94352cf9 2236
b7f1de28 2237 if (old_fb) {
d7697eea
DV		 2238 if (intel_crtc->active && old_fb != fb)
2239 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2240 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2241 }
652c393a 2242
6b8e6ed0 2243 intel_update_fbc(dev);
5c3b82e2 2244 mutex_unlock(&dev->struct_mutex);
79e53945 2245
198598d0 2246 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2247
2248 return 0;
79e53945
JB		 2249}
2250
5e84e1a4
ZW		 2251static void intel_fdi_normal_train(struct drm_crtc *crtc)
2252{
2253 struct drm_device *dev = crtc->dev;
2254 struct drm_i915_private *dev_priv = dev->dev_private;
2255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2256 int pipe = intel_crtc->pipe;
2257 u32 reg, temp;
2258
2259 /* enable normal train */
2260 reg = FDI_TX_CTL(pipe);
2261 temp = I915_READ(reg);
61e499bf 2262 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2263 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2264 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2265 } else {
2266 temp &= ~FDI_LINK_TRAIN_NONE;
2267 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2268 }
5e84e1a4
ZW		 2269 I915_WRITE(reg, temp);
2270
2271 reg = FDI_RX_CTL(pipe);
2272 temp = I915_READ(reg);
2273 if (HAS_PCH_CPT(dev)) {
2274 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2275 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2276 } else {
2277 temp &= ~FDI_LINK_TRAIN_NONE;
2278 temp |= FDI_LINK_TRAIN_NONE;
2279 }
2280 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2281
2282 /* wait one idle pattern time */
2283 POSTING_READ(reg);
2284 udelay(1000);
357555c0
JB		 2285
2286 /* IVB wants error correction enabled */
2287 if (IS_IVYBRIDGE(dev))
2288 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2289 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2290}
2291
1e833f40
DV		 2292static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2293{
2294 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2295}
2296
01a415fd
DV		 2297static void ivb_modeset_global_resources(struct drm_device *dev)
2298{
2299 struct drm_i915_private *dev_priv = dev->dev_private;
2300 struct intel_crtc *pipe_B_crtc =
2301 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2302 struct intel_crtc *pipe_C_crtc =
2303 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2304 uint32_t temp;
2305
1e833f40
DV		 2306 /*
2307 * When everything is off disable fdi C so that we could enable fdi B
2308 * with all lanes. Note that we don't care about enabled pipes without
2309 * an enabled pch encoder.
2310 */
2311 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2312 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2313 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2314 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2315
2316 temp = I915_READ(SOUTH_CHICKEN1);
2317 temp &= ~FDI_BC_BIFURCATION_SELECT;
2318 DRM_DEBUG_KMS("disabling fdi C rx\n");
2319 I915_WRITE(SOUTH_CHICKEN1, temp);
2320 }
2321}
2322
8db9d77b
ZW		 2323/* The FDI link training functions for ILK/Ibexpeak. */
2324static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2325{
2326 struct drm_device *dev = crtc->dev;
2327 struct drm_i915_private *dev_priv = dev->dev_private;
2328 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2329 int pipe = intel_crtc->pipe;
0fc932b8 2330 int plane = intel_crtc->plane;
5eddb70b 2331 u32 reg, temp, tries;
8db9d77b 2332
0fc932b8
JB		 2333 /* FDI needs bits from pipe & plane first */
2334 assert_pipe_enabled(dev_priv, pipe);
2335 assert_plane_enabled(dev_priv, plane);
2336
e1a44743
AJ		 2337 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2338 for train result */
5eddb70b
CW		 2339 reg = FDI_RX_IMR(pipe);
2340 temp = I915_READ(reg);
e1a44743
AJ		 2341 temp &= ~FDI_RX_SYMBOL_LOCK;
2342 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2343 I915_WRITE(reg, temp);
2344 I915_READ(reg);
e1a44743
AJ		 2345 udelay(150);
2346
8db9d77b 2347 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2348 reg = FDI_TX_CTL(pipe);
2349 temp = I915_READ(reg);
627eb5a3
DV		 2350 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2351 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2352 temp &= ~FDI_LINK_TRAIN_NONE;
2353 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2354 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2355
5eddb70b
CW		 2356 reg = FDI_RX_CTL(pipe);
2357 temp = I915_READ(reg);
8db9d77b
ZW		 2358 temp &= ~FDI_LINK_TRAIN_NONE;
2359 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2360 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2361
2362 POSTING_READ(reg);
8db9d77b
ZW		 2363 udelay(150);
2364
5b2adf89 2365 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2366 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2367 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2368 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2369
5eddb70b 2370 reg = FDI_RX_IIR(pipe);
e1a44743 2371 for (tries = 0; tries < 5; tries++) {
5eddb70b 2372 temp = I915_READ(reg);
8db9d77b
ZW		 2373 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2374
2375 if ((temp & FDI_RX_BIT_LOCK)) {
2376 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2377 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2378 break;
2379 }
8db9d77b 2380 }
e1a44743 2381 if (tries == 5)
5eddb70b 2382 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2383
2384 /* Train 2 */
5eddb70b
CW		 2385 reg = FDI_TX_CTL(pipe);
2386 temp = I915_READ(reg);
8db9d77b
ZW		 2387 temp &= ~FDI_LINK_TRAIN_NONE;
2388 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2389 I915_WRITE(reg, temp);
8db9d77b 2390
5eddb70b
CW		 2391 reg = FDI_RX_CTL(pipe);
2392 temp = I915_READ(reg);
8db9d77b
ZW		 2393 temp &= ~FDI_LINK_TRAIN_NONE;
2394 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2395 I915_WRITE(reg, temp);
8db9d77b 2396
5eddb70b
CW		 2397 POSTING_READ(reg);
2398 udelay(150);
8db9d77b 2399
5eddb70b 2400 reg = FDI_RX_IIR(pipe);
e1a44743 2401 for (tries = 0; tries < 5; tries++) {
5eddb70b 2402 temp = I915_READ(reg);
8db9d77b
ZW		 2403 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2404
2405 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2406 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2407 DRM_DEBUG_KMS("FDI train 2 done.\n");
2408 break;
2409 }
8db9d77b 2410 }
e1a44743 2411 if (tries == 5)
5eddb70b 2412 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2413
2414 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2415
8db9d77b
ZW		 2416}
2417
0206e353 2418static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2419 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2420 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2421 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2422 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2423};
2424
2425/* The FDI link training functions for SNB/Cougarpoint. */
2426static void gen6_fdi_link_train(struct drm_crtc *crtc)
2427{
2428 struct drm_device *dev = crtc->dev;
2429 struct drm_i915_private *dev_priv = dev->dev_private;
2430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2431 int pipe = intel_crtc->pipe;
fa37d39e 2432 u32 reg, temp, i, retry;
8db9d77b 2433
e1a44743
AJ		 2434 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2435 for train result */
5eddb70b
CW		 2436 reg = FDI_RX_IMR(pipe);
2437 temp = I915_READ(reg);
e1a44743
AJ		 2438 temp &= ~FDI_RX_SYMBOL_LOCK;
2439 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2440 I915_WRITE(reg, temp);
2441
2442 POSTING_READ(reg);
e1a44743
AJ		 2443 udelay(150);
2444
8db9d77b 2445 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2446 reg = FDI_TX_CTL(pipe);
2447 temp = I915_READ(reg);
627eb5a3
DV		 2448 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2449 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2450 temp &= ~FDI_LINK_TRAIN_NONE;
2451 temp |= FDI_LINK_TRAIN_PATTERN_1;
2452 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2453 /* SNB-B */
2454 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2455 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2456
d74cf324
DV		 2457 I915_WRITE(FDI_RX_MISC(pipe),
2458 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2459
5eddb70b
CW		 2460 reg = FDI_RX_CTL(pipe);
2461 temp = I915_READ(reg);
8db9d77b
ZW		 2462 if (HAS_PCH_CPT(dev)) {
2463 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2464 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2465 } else {
2466 temp &= ~FDI_LINK_TRAIN_NONE;
2467 temp |= FDI_LINK_TRAIN_PATTERN_1;
2468 }
5eddb70b
CW		 2469 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2470
2471 POSTING_READ(reg);
8db9d77b
ZW		 2472 udelay(150);
2473
0206e353 2474 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2475 reg = FDI_TX_CTL(pipe);
2476 temp = I915_READ(reg);
8db9d77b
ZW		 2477 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2478 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2479 I915_WRITE(reg, temp);
2480
2481 POSTING_READ(reg);
8db9d77b
ZW		 2482 udelay(500);
2483
fa37d39e
SP		 2484 for (retry = 0; retry < 5; retry++) {
2485 reg = FDI_RX_IIR(pipe);
2486 temp = I915_READ(reg);
2487 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2488 if (temp & FDI_RX_BIT_LOCK) {
2489 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2490 DRM_DEBUG_KMS("FDI train 1 done.\n");
2491 break;
2492 }
2493 udelay(50);
8db9d77b 2494 }
fa37d39e
SP		 2495 if (retry < 5)
2496 break;
8db9d77b
ZW		 2497 }
2498 if (i == 4)
5eddb70b 2499 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2500
2501 /* Train 2 */
5eddb70b
CW		 2502 reg = FDI_TX_CTL(pipe);
2503 temp = I915_READ(reg);
8db9d77b
ZW		 2504 temp &= ~FDI_LINK_TRAIN_NONE;
2505 temp |= FDI_LINK_TRAIN_PATTERN_2;
2506 if (IS_GEN6(dev)) {
2507 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2508 /* SNB-B */
2509 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2510 }
5eddb70b 2511 I915_WRITE(reg, temp);
8db9d77b 2512
5eddb70b
CW		 2513 reg = FDI_RX_CTL(pipe);
2514 temp = I915_READ(reg);
8db9d77b
ZW		 2515 if (HAS_PCH_CPT(dev)) {
2516 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2517 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2518 } else {
2519 temp &= ~FDI_LINK_TRAIN_NONE;
2520 temp |= FDI_LINK_TRAIN_PATTERN_2;
2521 }
5eddb70b
CW		 2522 I915_WRITE(reg, temp);
2523
2524 POSTING_READ(reg);
8db9d77b
ZW		 2525 udelay(150);
2526
0206e353 2527 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2528 reg = FDI_TX_CTL(pipe);
2529 temp = I915_READ(reg);
8db9d77b
ZW		 2530 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2531 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2532 I915_WRITE(reg, temp);
2533
2534 POSTING_READ(reg);
8db9d77b
ZW		 2535 udelay(500);
2536
fa37d39e
SP		 2537 for (retry = 0; retry < 5; retry++) {
2538 reg = FDI_RX_IIR(pipe);
2539 temp = I915_READ(reg);
2540 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2541 if (temp & FDI_RX_SYMBOL_LOCK) {
2542 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2543 DRM_DEBUG_KMS("FDI train 2 done.\n");
2544 break;
2545 }
2546 udelay(50);
8db9d77b 2547 }
fa37d39e
SP		 2548 if (retry < 5)
2549 break;
8db9d77b
ZW		 2550 }
2551 if (i == 4)
5eddb70b 2552 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2553
2554 DRM_DEBUG_KMS("FDI train done.\n");
2555}
2556
357555c0
JB		 2557/* Manual link training for Ivy Bridge A0 parts */
2558static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2559{
2560 struct drm_device *dev = crtc->dev;
2561 struct drm_i915_private *dev_priv = dev->dev_private;
2562 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2563 int pipe = intel_crtc->pipe;
2564 u32 reg, temp, i;
2565
2566 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2567 for train result */
2568 reg = FDI_RX_IMR(pipe);
2569 temp = I915_READ(reg);
2570 temp &= ~FDI_RX_SYMBOL_LOCK;
2571 temp &= ~FDI_RX_BIT_LOCK;
2572 I915_WRITE(reg, temp);
2573
2574 POSTING_READ(reg);
2575 udelay(150);
2576
01a415fd
DV		 2577 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2578 I915_READ(FDI_RX_IIR(pipe)));
2579
357555c0
JB		 2580 /* enable CPU FDI TX and PCH FDI RX */
2581 reg = FDI_TX_CTL(pipe);
2582 temp = I915_READ(reg);
627eb5a3
DV		 2583 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2584 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2585 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2586 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2589 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2590 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2591
d74cf324
DV		 2592 I915_WRITE(FDI_RX_MISC(pipe),
2593 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2594
357555c0
JB		 2595 reg = FDI_RX_CTL(pipe);
2596 temp = I915_READ(reg);
2597 temp &= ~FDI_LINK_TRAIN_AUTO;
2598 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2599 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2600 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2601 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2602
2603 POSTING_READ(reg);
2604 udelay(150);
2605
0206e353 2606 for (i = 0; i < 4; i++) {
357555c0
JB		 2607 reg = FDI_TX_CTL(pipe);
2608 temp = I915_READ(reg);
2609 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2610 temp |= snb_b_fdi_train_param[i];
2611 I915_WRITE(reg, temp);
2612
2613 POSTING_READ(reg);
2614 udelay(500);
2615
2616 reg = FDI_RX_IIR(pipe);
2617 temp = I915_READ(reg);
2618 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2619
2620 if (temp & FDI_RX_BIT_LOCK ||
2621 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2622 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2623 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2624 break;
2625 }
2626 }
2627 if (i == 4)
2628 DRM_ERROR("FDI train 1 fail!\n");
2629
2630 /* Train 2 */
2631 reg = FDI_TX_CTL(pipe);
2632 temp = I915_READ(reg);
2633 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2634 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2635 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2636 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2637 I915_WRITE(reg, temp);
2638
2639 reg = FDI_RX_CTL(pipe);
2640 temp = I915_READ(reg);
2641 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2642 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2643 I915_WRITE(reg, temp);
2644
2645 POSTING_READ(reg);
2646 udelay(150);
2647
0206e353 2648 for (i = 0; i < 4; i++) {
357555c0
JB		 2649 reg = FDI_TX_CTL(pipe);
2650 temp = I915_READ(reg);
2651 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2652 temp |= snb_b_fdi_train_param[i];
2653 I915_WRITE(reg, temp);
2654
2655 POSTING_READ(reg);
2656 udelay(500);
2657
2658 reg = FDI_RX_IIR(pipe);
2659 temp = I915_READ(reg);
2660 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2661
2662 if (temp & FDI_RX_SYMBOL_LOCK) {
2663 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2664 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2665 break;
2666 }
2667 }
2668 if (i == 4)
2669 DRM_ERROR("FDI train 2 fail!\n");
2670
2671 DRM_DEBUG_KMS("FDI train done.\n");
2672}
2673
88cefb6c 2674static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2675{
88cefb6c 2676 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2677 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2678 int pipe = intel_crtc->pipe;
5eddb70b 2679 u32 reg, temp;
79e53945 2680
c64e311e 2681
c98e9dcf 2682 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2683 reg = FDI_RX_CTL(pipe);
2684 temp = I915_READ(reg);
627eb5a3
DV		 2685 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2686 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2687 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2688 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2689
2690 POSTING_READ(reg);
c98e9dcf
JB		 2691 udelay(200);
2692
2693 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2694 temp = I915_READ(reg);
2695 I915_WRITE(reg, temp | FDI_PCDCLK);
2696
2697 POSTING_READ(reg);
c98e9dcf
JB		 2698 udelay(200);
2699
20749730
PZ		 2700 /* Enable CPU FDI TX PLL, always on for Ironlake */
2701 reg = FDI_TX_CTL(pipe);
2702 temp = I915_READ(reg);
2703 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2704 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2705
20749730
PZ		 2706 POSTING_READ(reg);
2707 udelay(100);
6be4a607 2708 }
0e23b99d
JB		 2709}
2710
88cefb6c
DV		 2711static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2712{
2713 struct drm_device *dev = intel_crtc->base.dev;
2714 struct drm_i915_private *dev_priv = dev->dev_private;
2715 int pipe = intel_crtc->pipe;
2716 u32 reg, temp;
2717
2718 /* Switch from PCDclk to Rawclk */
2719 reg = FDI_RX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2722
2723 /* Disable CPU FDI TX PLL */
2724 reg = FDI_TX_CTL(pipe);
2725 temp = I915_READ(reg);
2726 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2727
2728 POSTING_READ(reg);
2729 udelay(100);
2730
2731 reg = FDI_RX_CTL(pipe);
2732 temp = I915_READ(reg);
2733 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2734
2735 /* Wait for the clocks to turn off. */
2736 POSTING_READ(reg);
2737 udelay(100);
2738}
2739
0fc932b8
JB		 2740static void ironlake_fdi_disable(struct drm_crtc *crtc)
2741{
2742 struct drm_device *dev = crtc->dev;
2743 struct drm_i915_private *dev_priv = dev->dev_private;
2744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2745 int pipe = intel_crtc->pipe;
2746 u32 reg, temp;
2747
2748 /* disable CPU FDI tx and PCH FDI rx */
2749 reg = FDI_TX_CTL(pipe);
2750 temp = I915_READ(reg);
2751 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2752 POSTING_READ(reg);
2753
2754 reg = FDI_RX_CTL(pipe);
2755 temp = I915_READ(reg);
2756 temp &= ~(0x7 << 16);
dfd07d72 2757 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2758 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2759
2760 POSTING_READ(reg);
2761 udelay(100);
2762
2763 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2764 if (HAS_PCH_IBX(dev)) {
2765 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2766 }
0fc932b8
JB		 2767
2768 /* still set train pattern 1 */
2769 reg = FDI_TX_CTL(pipe);
2770 temp = I915_READ(reg);
2771 temp &= ~FDI_LINK_TRAIN_NONE;
2772 temp |= FDI_LINK_TRAIN_PATTERN_1;
2773 I915_WRITE(reg, temp);
2774
2775 reg = FDI_RX_CTL(pipe);
2776 temp = I915_READ(reg);
2777 if (HAS_PCH_CPT(dev)) {
2778 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2779 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2780 } else {
2781 temp &= ~FDI_LINK_TRAIN_NONE;
2782 temp |= FDI_LINK_TRAIN_PATTERN_1;
2783 }
2784 /* BPC in FDI rx is consistent with that in PIPECONF */
2785 temp &= ~(0x07 << 16);
dfd07d72 2786 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2787 I915_WRITE(reg, temp);
2788
2789 POSTING_READ(reg);
2790 udelay(100);
2791}
2792
5bb61643
CW		 2793static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2794{
2795 struct drm_device *dev = crtc->dev;
2796 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2797 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2798 unsigned long flags;
2799 bool pending;
2800
10d83730
VS		 2801 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2802 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2803 return false;
2804
2805 spin_lock_irqsave(&dev->event_lock, flags);
2806 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2807 spin_unlock_irqrestore(&dev->event_lock, flags);
2808
2809 return pending;
2810}
2811
e6c3a2a6
CW		 2812static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2813{
0f91128d 2814 struct drm_device *dev = crtc->dev;
5bb61643 2815 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2816
2817 if (crtc->fb == NULL)
2818 return;
2819
2c10d571
DV		 2820 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2821
5bb61643
CW		 2822 wait_event(dev_priv->pending_flip_queue,
2823 !intel_crtc_has_pending_flip(crtc));
2824
0f91128d
CW		 2825 mutex_lock(&dev->struct_mutex);
2826 intel_finish_fb(crtc->fb);
2827 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2828}
2829
e615efe4
ED		 2830/* Program iCLKIP clock to the desired frequency */
2831static void lpt_program_iclkip(struct drm_crtc *crtc)
2832{
2833 struct drm_device *dev = crtc->dev;
2834 struct drm_i915_private *dev_priv = dev->dev_private;
2835 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2836 u32 temp;
2837
09153000
DV		 2838 mutex_lock(&dev_priv->dpio_lock);
2839
e615efe4
ED		 2840 /* It is necessary to ungate the pixclk gate prior to programming
2841 * the divisors, and gate it back when it is done.
2842 */
2843 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2844
2845 /* Disable SSCCTL */
2846 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2847 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2848 SBI_SSCCTL_DISABLE,
2849 SBI_ICLK);
e615efe4
ED		 2850
2851 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2852 if (crtc->mode.clock == 20000) {
2853 auxdiv = 1;
2854 divsel = 0x41;
2855 phaseinc = 0x20;
2856 } else {
2857 /* The iCLK virtual clock root frequency is in MHz,
2858 * but the crtc->mode.clock in in KHz. To get the divisors,
2859 * it is necessary to divide one by another, so we
2860 * convert the virtual clock precision to KHz here for higher
2861 * precision.
2862 */
2863 u32 iclk_virtual_root_freq = 172800 * 1000;
2864 u32 iclk_pi_range = 64;
2865 u32 desired_divisor, msb_divisor_value, pi_value;
2866
2867 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2868 msb_divisor_value = desired_divisor / iclk_pi_range;
2869 pi_value = desired_divisor % iclk_pi_range;
2870
2871 auxdiv = 0;
2872 divsel = msb_divisor_value - 2;
2873 phaseinc = pi_value;
2874 }
2875
2876 /* This should not happen with any sane values */
2877 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2878 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2879 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2880 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2881
2882 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2883 crtc->mode.clock,
2884 auxdiv,
2885 divsel,
2886 phasedir,
2887 phaseinc);
2888
2889 /* Program SSCDIVINTPHASE6 */
988d6ee8 2890 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2891 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2892 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2893 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2894 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2895 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2896 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2897 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2898
2899 /* Program SSCAUXDIV */
988d6ee8 2900 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2901 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2902 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2903 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2904
2905 /* Enable modulator and associated divider */
988d6ee8 2906 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2907 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2908 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2909
2910 /* Wait for initialization time */
2911 udelay(24);
2912
2913 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2914
2915 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2916}
2917
275f01b2
DV		 2918static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2919 enum pipe pch_transcoder)
2920{
2921 struct drm_device *dev = crtc->base.dev;
2922 struct drm_i915_private *dev_priv = dev->dev_private;
2923 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2924
2925 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2926 I915_READ(HTOTAL(cpu_transcoder)));
2927 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2928 I915_READ(HBLANK(cpu_transcoder)));
2929 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2930 I915_READ(HSYNC(cpu_transcoder)));
2931
2932 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2933 I915_READ(VTOTAL(cpu_transcoder)));
2934 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2935 I915_READ(VBLANK(cpu_transcoder)));
2936 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2937 I915_READ(VSYNC(cpu_transcoder)));
2938 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2939 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2940}
2941
f67a559d
JB		 2942/*
2943 * Enable PCH resources required for PCH ports:
2944 * - PCH PLLs
2945 * - FDI training & RX/TX
2946 * - update transcoder timings
2947 * - DP transcoding bits
2948 * - transcoder
2949 */
2950static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2951{
2952 struct drm_device *dev = crtc->dev;
2953 struct drm_i915_private *dev_priv = dev->dev_private;
2954 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2955 int pipe = intel_crtc->pipe;
ee7b9f93 2956 u32 reg, temp;
2c07245f 2957
ab9412ba 2958 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2959
cd986abb
DV		 2960 /* Write the TU size bits before fdi link training, so that error
2961 * detection works. */
2962 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2963 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2964
c98e9dcf 2965 /* For PCH output, training FDI link */
674cf967 2966 dev_priv->display.fdi_link_train(crtc);
2c07245f 2967
572deb37
DV		 2968 /* XXX: pch pll's can be enabled any time before we enable the PCH
2969 * transcoder, and we actually should do this to not upset any PCH
2970 * transcoder that already use the clock when we share it.
2971 *
e72f9fbf
DV		 2972 * Note that enable_shared_dpll tries to do the right thing, but
2973 * get_shared_dpll unconditionally resets the pll - we need that to have
2974 * the right LVDS enable sequence. */
2975 ironlake_enable_shared_dpll(intel_crtc);
6f13b7b5 2976
303b81e0 2977 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2978 u32 sel;
4b645f14 2979
c98e9dcf 2980 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 2981 temp |= TRANS_DPLL_ENABLE(pipe);
2982 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 2983 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 2984 temp |= sel;
2985 else
2986 temp &= ~sel;
c98e9dcf 2987 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2988 }
5eddb70b 2989
d9b6cb56
JB		 2990 /* set transcoder timing, panel must allow it */
2991 assert_panel_unlocked(dev_priv, pipe);
275f01b2 2992 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 2993
303b81e0 2994 intel_fdi_normal_train(crtc);
5e84e1a4 2995
c98e9dcf
JB		 2996 /* For PCH DP, enable TRANS_DP_CTL */
2997 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2998 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2999 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3000 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3001 reg = TRANS_DP_CTL(pipe);
3002 temp = I915_READ(reg);
3003 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3004 TRANS_DP_SYNC_MASK |
3005 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3006 temp |= (TRANS_DP_OUTPUT_ENABLE |
3007 TRANS_DP_ENH_FRAMING);
9325c9f0 3008 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3009
3010 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3011 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3012 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3013 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3014
3015 switch (intel_trans_dp_port_sel(crtc)) {
3016 case PCH_DP_B:
5eddb70b 3017 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3018 break;
3019 case PCH_DP_C:
5eddb70b 3020 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3021 break;
3022 case PCH_DP_D:
5eddb70b 3023 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3024 break;
3025 default:
e95d41e1 3026 BUG();
32f9d658 3027 }
2c07245f 3028
5eddb70b 3029 I915_WRITE(reg, temp);
6be4a607 3030 }
b52eb4dc 3031
b8a4f404 3032 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3033}
3034
1507e5bd
PZ		 3035static void lpt_pch_enable(struct drm_crtc *crtc)
3036{
3037 struct drm_device *dev = crtc->dev;
3038 struct drm_i915_private *dev_priv = dev->dev_private;
3039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3040 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3041
ab9412ba 3042 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3043
8c52b5e8 3044 lpt_program_iclkip(crtc);
1507e5bd 3045
0540e488 3046 /* Set transcoder timing. */
275f01b2 3047 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3048
937bb610 3049 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3050}
3051
e2b78267 3052static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3053{
e2b78267 3054 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3055
3056 if (pll == NULL)
3057 return;
3058
3059 if (pll->refcount == 0) {
46edb027 3060 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3061 return;
3062 }
3063
f4a091c7
DV		 3064 if (--pll->refcount == 0) {
3065 WARN_ON(pll->on);
3066 WARN_ON(pll->active);
3067 }
3068
a43f6e0f 3069 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3070}
3071
b89a1d39 3072static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3073{
e2b78267
DV		 3074 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3075 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3076 enum intel_dpll_id i;
ee7b9f93 3077
ee7b9f93 3078 if (pll) {
46edb027
DV		 3079 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3080 crtc->base.base.id, pll->name);
e2b78267 3081 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3082 }
3083
98b6bd99
DV		 3084 if (HAS_PCH_IBX(dev_priv->dev)) {
3085 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
e2b78267 3086 i = crtc->pipe;
e72f9fbf 3087 pll = &dev_priv->shared_dplls[i];
98b6bd99 3088
46edb027
DV		 3089 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3090 crtc->base.base.id, pll->name);
98b6bd99
DV		 3091
3092 goto found;
3093 }
3094
e72f9fbf
DV		 3095 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3096 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3097
3098 /* Only want to check enabled timings first */
3099 if (pll->refcount == 0)
3100 continue;
3101
b89a1d39
DV		 3102 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3103 sizeof(pll->hw_state)) == 0) {
46edb027 3104 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3105 crtc->base.base.id,
46edb027 3106 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3107
3108 goto found;
3109 }
3110 }
3111
3112 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3113 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3114 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3115 if (pll->refcount == 0) {
46edb027
DV		 3116 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3117 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3118 goto found;
3119 }
3120 }
3121
3122 return NULL;
3123
3124found:
a43f6e0f 3125 crtc->config.shared_dpll = i;
46edb027
DV		 3126 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3127 pipe_name(crtc->pipe));
ee7b9f93 3128
cdbd2316 3129 if (pll->active == 0) {
66e985c0
DV		 3130 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3131 sizeof(pll->hw_state));
3132
46edb027 3133 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3134 WARN_ON(pll->on);
e9d6944e 3135 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3136
15bdd4cf 3137 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3138 }
3139 pll->refcount++;
e04c7350 3140
ee7b9f93
JB		 3141 return pll;
3142}
3143
a1520318 3144static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3145{
3146 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3147 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3148 u32 temp;
3149
3150 temp = I915_READ(dslreg);
3151 udelay(500);
3152 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3153 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3154 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3155 }
3156}
3157
b074cec8
JB		 3158static void ironlake_pfit_enable(struct intel_crtc *crtc)
3159{
3160 struct drm_device *dev = crtc->base.dev;
3161 struct drm_i915_private *dev_priv = dev->dev_private;
3162 int pipe = crtc->pipe;
3163
0ef37f3f 3164 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3165 /* Force use of hard-coded filter coefficients
3166 * as some pre-programmed values are broken,
3167 * e.g. x201.
3168 */
3169 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3170 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3171 PF_PIPE_SEL_IVB(pipe));
3172 else
3173 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3174 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3175 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3176 }
3177}
3178
bb53d4ae
VS		 3179static void intel_enable_planes(struct drm_crtc *crtc)
3180{
3181 struct drm_device *dev = crtc->dev;
3182 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3183 struct intel_plane *intel_plane;
3184
3185 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3186 if (intel_plane->pipe == pipe)
3187 intel_plane_restore(&intel_plane->base);
3188}
3189
3190static void intel_disable_planes(struct drm_crtc *crtc)
3191{
3192 struct drm_device *dev = crtc->dev;
3193 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3194 struct intel_plane *intel_plane;
3195
3196 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3197 if (intel_plane->pipe == pipe)
3198 intel_plane_disable(&intel_plane->base);
3199}
3200
f67a559d
JB		 3201static void ironlake_crtc_enable(struct drm_crtc *crtc)
3202{
3203 struct drm_device *dev = crtc->dev;
3204 struct drm_i915_private *dev_priv = dev->dev_private;
3205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3206 struct intel_encoder *encoder;
f67a559d
JB		 3207 int pipe = intel_crtc->pipe;
3208 int plane = intel_crtc->plane;
f67a559d 3209
08a48469
DV		 3210 WARN_ON(!crtc->enabled);
3211
f67a559d
JB		 3212 if (intel_crtc->active)
3213 return;
3214
3215 intel_crtc->active = true;
8664281b
PZ		 3216
3217 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3218 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3219
f67a559d
JB		 3220 intel_update_watermarks(dev);
3221
f6736a1a 3222 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3223 if (encoder->pre_enable)
3224 encoder->pre_enable(encoder);
f67a559d 3225
5bfe2ac0 3226 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3227 /* Note: FDI PLL enabling _must_ be done before we enable the
3228 * cpu pipes, hence this is separate from all the other fdi/pch
3229 * enabling. */
88cefb6c 3230 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3231 } else {
3232 assert_fdi_tx_disabled(dev_priv, pipe);
3233 assert_fdi_rx_disabled(dev_priv, pipe);
3234 }
f67a559d 3235
b074cec8 3236 ironlake_pfit_enable(intel_crtc);
f67a559d 3237
9c54c0dd
JB		 3238 /*
3239 * On ILK+ LUT must be loaded before the pipe is running but with
3240 * clocks enabled
3241 */
3242 intel_crtc_load_lut(crtc);
3243
5bfe2ac0
DV		 3244 intel_enable_pipe(dev_priv, pipe,
3245 intel_crtc->config.has_pch_encoder);
f67a559d 3246 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3247 intel_enable_planes(crtc);
5c38d48c 3248 intel_crtc_update_cursor(crtc, true);
f67a559d 3249
5bfe2ac0 3250 if (intel_crtc->config.has_pch_encoder)
f67a559d 3251 ironlake_pch_enable(crtc);
c98e9dcf 3252
d1ebd816 3253 mutex_lock(&dev->struct_mutex);
bed4a673 3254 intel_update_fbc(dev);
d1ebd816
BW		 3255 mutex_unlock(&dev->struct_mutex);
3256
fa5c73b1
DV		 3257 for_each_encoder_on_crtc(dev, crtc, encoder)
3258 encoder->enable(encoder);
61b77ddd
DV		 3259
3260 if (HAS_PCH_CPT(dev))
a1520318 3261 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3262
3263 /*
3264 * There seems to be a race in PCH platform hw (at least on some
3265 * outputs) where an enabled pipe still completes any pageflip right
3266 * away (as if the pipe is off) instead of waiting for vblank. As soon
3267 * as the first vblank happend, everything works as expected. Hence just
3268 * wait for one vblank before returning to avoid strange things
3269 * happening.
3270 */
3271 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3272}
3273
42db64ef
PZ		 3274/* IPS only exists on ULT machines and is tied to pipe A. */
3275static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3276{
f5adf94e 3277 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3278}
3279
3280static void hsw_enable_ips(struct intel_crtc *crtc)
3281{
3282 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3283
3284 if (!crtc->config.ips_enabled)
3285 return;
3286
3287 /* We can only enable IPS after we enable a plane and wait for a vblank.
3288 * We guarantee that the plane is enabled by calling intel_enable_ips
3289 * only after intel_enable_plane. And intel_enable_plane already waits
3290 * for a vblank, so all we need to do here is to enable the IPS bit. */
3291 assert_plane_enabled(dev_priv, crtc->plane);
3292 I915_WRITE(IPS_CTL, IPS_ENABLE);
3293}
3294
3295static void hsw_disable_ips(struct intel_crtc *crtc)
3296{
3297 struct drm_device *dev = crtc->base.dev;
3298 struct drm_i915_private *dev_priv = dev->dev_private;
3299
3300 if (!crtc->config.ips_enabled)
3301 return;
3302
3303 assert_plane_enabled(dev_priv, crtc->plane);
3304 I915_WRITE(IPS_CTL, 0);
3305
3306 /* We need to wait for a vblank before we can disable the plane. */
3307 intel_wait_for_vblank(dev, crtc->pipe);
3308}
3309
4f771f10
PZ		 3310static void haswell_crtc_enable(struct drm_crtc *crtc)
3311{
3312 struct drm_device *dev = crtc->dev;
3313 struct drm_i915_private *dev_priv = dev->dev_private;
3314 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3315 struct intel_encoder *encoder;
3316 int pipe = intel_crtc->pipe;
3317 int plane = intel_crtc->plane;
4f771f10
PZ		 3318
3319 WARN_ON(!crtc->enabled);
3320
3321 if (intel_crtc->active)
3322 return;
3323
3324 intel_crtc->active = true;
8664281b
PZ		 3325
3326 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3327 if (intel_crtc->config.has_pch_encoder)
3328 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3329
4f771f10
PZ		 3330 intel_update_watermarks(dev);
3331
5bfe2ac0 3332 if (intel_crtc->config.has_pch_encoder)
04945641 3333 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3334
3335 for_each_encoder_on_crtc(dev, crtc, encoder)
3336 if (encoder->pre_enable)
3337 encoder->pre_enable(encoder);
3338
1f544388 3339 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3340
b074cec8 3341 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3342
3343 /*
3344 * On ILK+ LUT must be loaded before the pipe is running but with
3345 * clocks enabled
3346 */
3347 intel_crtc_load_lut(crtc);
3348
1f544388 3349 intel_ddi_set_pipe_settings(crtc);
8228c251 3350 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3351
5bfe2ac0
DV		 3352 intel_enable_pipe(dev_priv, pipe,
3353 intel_crtc->config.has_pch_encoder);
4f771f10 3354 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3355 intel_enable_planes(crtc);
5c38d48c 3356 intel_crtc_update_cursor(crtc, true);
4f771f10 3357
42db64ef
PZ		 3358 hsw_enable_ips(intel_crtc);
3359
5bfe2ac0 3360 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3361 lpt_pch_enable(crtc);
4f771f10
PZ		 3362
3363 mutex_lock(&dev->struct_mutex);
3364 intel_update_fbc(dev);
3365 mutex_unlock(&dev->struct_mutex);
3366
4f771f10
PZ		 3367 for_each_encoder_on_crtc(dev, crtc, encoder)
3368 encoder->enable(encoder);
3369
4f771f10
PZ		 3370 /*
3371 * There seems to be a race in PCH platform hw (at least on some
3372 * outputs) where an enabled pipe still completes any pageflip right
3373 * away (as if the pipe is off) instead of waiting for vblank. As soon
3374 * as the first vblank happend, everything works as expected. Hence just
3375 * wait for one vblank before returning to avoid strange things
3376 * happening.
3377 */
3378 intel_wait_for_vblank(dev, intel_crtc->pipe);
3379}
3380
3f8dce3a
DV		 3381static void ironlake_pfit_disable(struct intel_crtc *crtc)
3382{
3383 struct drm_device *dev = crtc->base.dev;
3384 struct drm_i915_private *dev_priv = dev->dev_private;
3385 int pipe = crtc->pipe;
3386
3387 /* To avoid upsetting the power well on haswell only disable the pfit if
3388 * it's in use. The hw state code will make sure we get this right. */
3389 if (crtc->config.pch_pfit.size) {
3390 I915_WRITE(PF_CTL(pipe), 0);
3391 I915_WRITE(PF_WIN_POS(pipe), 0);
3392 I915_WRITE(PF_WIN_SZ(pipe), 0);
3393 }
3394}
3395
6be4a607
JB		 3396static void ironlake_crtc_disable(struct drm_crtc *crtc)
3397{
3398 struct drm_device *dev = crtc->dev;
3399 struct drm_i915_private *dev_priv = dev->dev_private;
3400 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3401 struct intel_encoder *encoder;
6be4a607
JB		 3402 int pipe = intel_crtc->pipe;
3403 int plane = intel_crtc->plane;
5eddb70b 3404 u32 reg, temp;
b52eb4dc 3405
ef9c3aee 3406
f7abfe8b
CW		 3407 if (!intel_crtc->active)
3408 return;
3409
ea9d758d
DV		 3410 for_each_encoder_on_crtc(dev, crtc, encoder)
3411 encoder->disable(encoder);
3412
e6c3a2a6 3413 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3414 drm_vblank_off(dev, pipe);
913d8d11 3415
5c3fe8b0 3416 if (dev_priv->fbc.plane == plane)
973d04f9 3417 intel_disable_fbc(dev);
2c07245f 3418
0d5b8c61 3419 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3420 intel_disable_planes(crtc);
0d5b8c61
VS		 3421 intel_disable_plane(dev_priv, plane, pipe);
3422
d925c59a
DV		 3423 if (intel_crtc->config.has_pch_encoder)
3424 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3425
b24e7179 3426 intel_disable_pipe(dev_priv, pipe);
32f9d658 3427
3f8dce3a 3428 ironlake_pfit_disable(intel_crtc);
2c07245f 3429
bf49ec8c
DV		 3430 for_each_encoder_on_crtc(dev, crtc, encoder)
3431 if (encoder->post_disable)
3432 encoder->post_disable(encoder);
2c07245f 3433
d925c59a
DV		 3434 if (intel_crtc->config.has_pch_encoder) {
3435 ironlake_fdi_disable(crtc);
913d8d11 3436
d925c59a
DV		 3437 ironlake_disable_pch_transcoder(dev_priv, pipe);
3438 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3439
d925c59a
DV		 3440 if (HAS_PCH_CPT(dev)) {
3441 /* disable TRANS_DP_CTL */
3442 reg = TRANS_DP_CTL(pipe);
3443 temp = I915_READ(reg);
3444 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3445 TRANS_DP_PORT_SEL_MASK);
3446 temp |= TRANS_DP_PORT_SEL_NONE;
3447 I915_WRITE(reg, temp);
3448
3449 /* disable DPLL_SEL */
3450 temp = I915_READ(PCH_DPLL_SEL);
11887397 3451 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3452 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3453 }
e3421a18 3454
d925c59a 3455 /* disable PCH DPLL */
e72f9fbf 3456 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3457
d925c59a
DV		 3458 ironlake_fdi_pll_disable(intel_crtc);
3459 }
6b383a7f 3460
f7abfe8b 3461 intel_crtc->active = false;
6b383a7f 3462 intel_update_watermarks(dev);
d1ebd816
BW		 3463
3464 mutex_lock(&dev->struct_mutex);
6b383a7f 3465 intel_update_fbc(dev);
d1ebd816 3466 mutex_unlock(&dev->struct_mutex);
6be4a607 3467}
1b3c7a47 3468
4f771f10 3469static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3470{
4f771f10
PZ		 3471 struct drm_device *dev = crtc->dev;
3472 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3473 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3474 struct intel_encoder *encoder;
3475 int pipe = intel_crtc->pipe;
3476 int plane = intel_crtc->plane;
3b117c8f 3477 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3478
4f771f10
PZ		 3479 if (!intel_crtc->active)
3480 return;
3481
3482 for_each_encoder_on_crtc(dev, crtc, encoder)
3483 encoder->disable(encoder);
3484
3485 intel_crtc_wait_for_pending_flips(crtc);
3486 drm_vblank_off(dev, pipe);
4f771f10 3487
891348b2 3488 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3489 if (dev_priv->fbc.plane == plane)
4f771f10
PZ		 3490 intel_disable_fbc(dev);
3491
42db64ef
PZ		 3492 hsw_disable_ips(intel_crtc);
3493
0d5b8c61 3494 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3495 intel_disable_planes(crtc);
891348b2
RV		 3496 intel_disable_plane(dev_priv, plane, pipe);
3497
8664281b
PZ		 3498 if (intel_crtc->config.has_pch_encoder)
3499 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3500 intel_disable_pipe(dev_priv, pipe);
3501
ad80a810 3502 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3503
3f8dce3a 3504 ironlake_pfit_disable(intel_crtc);
4f771f10 3505
1f544388 3506 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3507
3508 for_each_encoder_on_crtc(dev, crtc, encoder)
3509 if (encoder->post_disable)
3510 encoder->post_disable(encoder);
3511
88adfff1 3512 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3513 lpt_disable_pch_transcoder(dev_priv);
8664281b 3514 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3515 intel_ddi_fdi_disable(crtc);
83616634 3516 }
4f771f10
PZ		 3517
3518 intel_crtc->active = false;
3519 intel_update_watermarks(dev);
3520
3521 mutex_lock(&dev->struct_mutex);
3522 intel_update_fbc(dev);
3523 mutex_unlock(&dev->struct_mutex);
3524}
3525
ee7b9f93
JB		 3526static void ironlake_crtc_off(struct drm_crtc *crtc)
3527{
3528 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3529 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3530}
3531
6441ab5f
PZ		 3532static void haswell_crtc_off(struct drm_crtc *crtc)
3533{
3534 intel_ddi_put_crtc_pll(crtc);
3535}
3536
02e792fb
DV		 3537static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3538{
02e792fb 3539 if (!enable && intel_crtc->overlay) {
23f09ce3 3540 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3541 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3542
23f09ce3 3543 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3544 dev_priv->mm.interruptible = false;
3545 (void) intel_overlay_switch_off(intel_crtc->overlay);
3546 dev_priv->mm.interruptible = true;
23f09ce3 3547 mutex_unlock(&dev->struct_mutex);
02e792fb 3548 }
02e792fb 3549
5dcdbcb0
CW		 3550 /* Let userspace switch the overlay on again. In most cases userspace
3551 * has to recompute where to put it anyway.
3552 */
02e792fb
DV		 3553}
3554
61bc95c1
EE		 3555/**
3556 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3557 * cursor plane briefly if not already running after enabling the display
3558 * plane.
3559 * This workaround avoids occasional blank screens when self refresh is
3560 * enabled.
3561 */
3562static void
3563g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3564{
3565 u32 cntl = I915_READ(CURCNTR(pipe));
3566
3567 if ((cntl & CURSOR_MODE) == 0) {
3568 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3569
3570 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3571 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3572 intel_wait_for_vblank(dev_priv->dev, pipe);
3573 I915_WRITE(CURCNTR(pipe), cntl);
3574 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3575 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3576 }
3577}
3578
2dd24552
JB		 3579static void i9xx_pfit_enable(struct intel_crtc *crtc)
3580{
3581 struct drm_device *dev = crtc->base.dev;
3582 struct drm_i915_private *dev_priv = dev->dev_private;
3583 struct intel_crtc_config *pipe_config = &crtc->config;
3584
328d8e82 3585 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3586 return;
3587
2dd24552 3588 /*
c0b03411
DV		 3589 * The panel fitter should only be adjusted whilst the pipe is disabled,
3590 * according to register description and PRM.
2dd24552 3591 */
c0b03411
DV		 3592 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3593 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3594
b074cec8
JB		 3595 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3596 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3597
3598 /* Border color in case we don't scale up to the full screen. Black by
3599 * default, change to something else for debugging. */
3600 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3601}
3602
89b667f8
JB		 3603static void valleyview_crtc_enable(struct drm_crtc *crtc)
3604{
3605 struct drm_device *dev = crtc->dev;
3606 struct drm_i915_private *dev_priv = dev->dev_private;
3607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3608 struct intel_encoder *encoder;
3609 int pipe = intel_crtc->pipe;
3610 int plane = intel_crtc->plane;
3611
3612 WARN_ON(!crtc->enabled);
3613
3614 if (intel_crtc->active)
3615 return;
3616
3617 intel_crtc->active = true;
3618 intel_update_watermarks(dev);
3619
3620 mutex_lock(&dev_priv->dpio_lock);
3621
3622 for_each_encoder_on_crtc(dev, crtc, encoder)
3623 if (encoder->pre_pll_enable)
3624 encoder->pre_pll_enable(encoder);
3625
87442f73 3626 vlv_enable_pll(dev_priv, pipe);
89b667f8
JB		 3627
3628 for_each_encoder_on_crtc(dev, crtc, encoder)
3629 if (encoder->pre_enable)
3630 encoder->pre_enable(encoder);
3631
3632 /* VLV wants encoder enabling _before_ the pipe is up. */
3633 for_each_encoder_on_crtc(dev, crtc, encoder)
3634 encoder->enable(encoder);
3635
2dd24552
JB		 3636 i9xx_pfit_enable(intel_crtc);
3637
63cbb074
VS		 3638 intel_crtc_load_lut(crtc);
3639
89b667f8
JB		 3640 intel_enable_pipe(dev_priv, pipe, false);
3641 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3642 intel_enable_planes(crtc);
5c38d48c 3643 intel_crtc_update_cursor(crtc, true);
89b667f8 3644
89b667f8
JB		 3645 intel_update_fbc(dev);
3646
89b667f8
JB		 3647 mutex_unlock(&dev_priv->dpio_lock);
3648}
3649
0b8765c6 3650static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3651{
3652 struct drm_device *dev = crtc->dev;
79e53945
JB		 3653 struct drm_i915_private *dev_priv = dev->dev_private;
3654 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3655 struct intel_encoder *encoder;
79e53945 3656 int pipe = intel_crtc->pipe;
80824003 3657 int plane = intel_crtc->plane;
79e53945 3658
08a48469
DV		 3659 WARN_ON(!crtc->enabled);
3660
f7abfe8b
CW		 3661 if (intel_crtc->active)
3662 return;
3663
3664 intel_crtc->active = true;
6b383a7f
CW		 3665 intel_update_watermarks(dev);
3666
9d6d9f19
MK		 3667 for_each_encoder_on_crtc(dev, crtc, encoder)
3668 if (encoder->pre_enable)
3669 encoder->pre_enable(encoder);
3670
f6736a1a
DV		 3671 i9xx_enable_pll(intel_crtc);
3672
2dd24552
JB		 3673 i9xx_pfit_enable(intel_crtc);
3674
63cbb074
VS		 3675 intel_crtc_load_lut(crtc);
3676
040484af 3677 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3678 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3679 intel_enable_planes(crtc);
22e407d7 3680 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3681 if (IS_G4X(dev))
3682 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3683 intel_crtc_update_cursor(crtc, true);
79e53945 3684
0b8765c6
JB		 3685 /* Give the overlay scaler a chance to enable if it's on this pipe */
3686 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3687
f440eb13 3688 intel_update_fbc(dev);
ef9c3aee 3689
fa5c73b1
DV		 3690 for_each_encoder_on_crtc(dev, crtc, encoder)
3691 encoder->enable(encoder);
0b8765c6 3692}
79e53945 3693
87476d63
DV		 3694static void i9xx_pfit_disable(struct intel_crtc *crtc)
3695{
3696 struct drm_device *dev = crtc->base.dev;
3697 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3698
328d8e82
DV		 3699 if (!crtc->config.gmch_pfit.control)
3700 return;
87476d63 3701
328d8e82 3702 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3703
328d8e82
DV		 3704 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3705 I915_READ(PFIT_CONTROL));
3706 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3707}
3708
0b8765c6
JB		 3709static void i9xx_crtc_disable(struct drm_crtc *crtc)
3710{
3711 struct drm_device *dev = crtc->dev;
3712 struct drm_i915_private *dev_priv = dev->dev_private;
3713 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3714 struct intel_encoder *encoder;
0b8765c6
JB		 3715 int pipe = intel_crtc->pipe;
3716 int plane = intel_crtc->plane;
ef9c3aee 3717
f7abfe8b
CW		 3718 if (!intel_crtc->active)
3719 return;
3720
ea9d758d
DV		 3721 for_each_encoder_on_crtc(dev, crtc, encoder)
3722 encoder->disable(encoder);
3723
0b8765c6 3724 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3725 intel_crtc_wait_for_pending_flips(crtc);
3726 drm_vblank_off(dev, pipe);
0b8765c6 3727
5c3fe8b0 3728 if (dev_priv->fbc.plane == plane)
973d04f9 3729 intel_disable_fbc(dev);
79e53945 3730
0d5b8c61
VS		 3731 intel_crtc_dpms_overlay(intel_crtc, false);
3732 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3733 intel_disable_planes(crtc);
b24e7179 3734 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3735
b24e7179 3736 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3737
87476d63 3738 i9xx_pfit_disable(intel_crtc);
24a1f16d 3739
89b667f8
JB		 3740 for_each_encoder_on_crtc(dev, crtc, encoder)
3741 if (encoder->post_disable)
3742 encoder->post_disable(encoder);
3743
63d7bbe9 3744 intel_disable_pll(dev_priv, pipe);
0b8765c6 3745
f7abfe8b 3746 intel_crtc->active = false;
6b383a7f
CW		 3747 intel_update_fbc(dev);
3748 intel_update_watermarks(dev);
0b8765c6
JB		 3749}
3750
ee7b9f93
JB		 3751static void i9xx_crtc_off(struct drm_crtc *crtc)
3752{
3753}
3754
976f8a20
DV		 3755static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3756 bool enabled)
2c07245f
ZW		 3757{
3758 struct drm_device *dev = crtc->dev;
3759 struct drm_i915_master_private *master_priv;
3760 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3761 int pipe = intel_crtc->pipe;
79e53945
JB		 3762
3763 if (!dev->primary->master)
3764 return;
3765
3766 master_priv = dev->primary->master->driver_priv;
3767 if (!master_priv->sarea_priv)
3768 return;
3769
79e53945
JB		 3770 switch (pipe) {
3771 case 0:
3772 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3773 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3774 break;
3775 case 1:
3776 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3777 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3778 break;
3779 default:
9db4a9c7 3780 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3781 break;
3782 }
79e53945
JB		 3783}
3784
976f8a20
DV		 3785/**
3786 * Sets the power management mode of the pipe and plane.
3787 */
3788void intel_crtc_update_dpms(struct drm_crtc *crtc)
3789{
3790 struct drm_device *dev = crtc->dev;
3791 struct drm_i915_private *dev_priv = dev->dev_private;
3792 struct intel_encoder *intel_encoder;
3793 bool enable = false;
3794
3795 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3796 enable |= intel_encoder->connectors_active;
3797
3798 if (enable)
3799 dev_priv->display.crtc_enable(crtc);
3800 else
3801 dev_priv->display.crtc_disable(crtc);
3802
3803 intel_crtc_update_sarea(crtc, enable);
3804}
3805
cdd59983
CW		 3806static void intel_crtc_disable(struct drm_crtc *crtc)
3807{
cdd59983 3808 struct drm_device *dev = crtc->dev;
976f8a20 3809 struct drm_connector *connector;
ee7b9f93 3810 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3812
976f8a20
DV		 3813 /* crtc should still be enabled when we disable it. */
3814 WARN_ON(!crtc->enabled);
3815
3816 dev_priv->display.crtc_disable(crtc);
c77bf565 3817 intel_crtc->eld_vld = false;
976f8a20 3818 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3819 dev_priv->display.off(crtc);
3820
931872fc
CW		 3821 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3822 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3823
3824 if (crtc->fb) {
3825 mutex_lock(&dev->struct_mutex);
1690e1eb 3826 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3827 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3828 crtc->fb = NULL;
3829 }
3830
3831 /* Update computed state. */
3832 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3833 if (!connector->encoder || !connector->encoder->crtc)
3834 continue;
3835
3836 if (connector->encoder->crtc != crtc)
3837 continue;
3838
3839 connector->dpms = DRM_MODE_DPMS_OFF;
3840 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3841 }
3842}
3843
a261b246 3844void intel_modeset_disable(struct drm_device *dev)
79e53945 3845{
a261b246
DV		 3846 struct drm_crtc *crtc;
3847
3848 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3849 if (crtc->enabled)
3850 intel_crtc_disable(crtc);
3851 }
79e53945
JB		 3852}
3853
ea5b213a 3854void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3855{
4ef69c7a 3856 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3857
ea5b213a
CW		 3858 drm_encoder_cleanup(encoder);
3859 kfree(intel_encoder);
7e7d76c3
JB		 3860}
3861
5ab432ef
DV		 3862/* Simple dpms helper for encodres with just one connector, no cloning and only
3863 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3864 * state of the entire output pipe. */
3865void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3866{
5ab432ef
DV		 3867 if (mode == DRM_MODE_DPMS_ON) {
3868 encoder->connectors_active = true;
3869
b2cabb0e 3870 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3871 } else {
3872 encoder->connectors_active = false;
3873
b2cabb0e 3874 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3875 }
79e53945
JB		 3876}
3877
0a91ca29
DV		 3878/* Cross check the actual hw state with our own modeset state tracking (and it's
3879 * internal consistency). */
b980514c 3880static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3881{
0a91ca29
DV		 3882 if (connector->get_hw_state(connector)) {
3883 struct intel_encoder *encoder = connector->encoder;
3884 struct drm_crtc *crtc;
3885 bool encoder_enabled;
3886 enum pipe pipe;
3887
3888 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3889 connector->base.base.id,
3890 drm_get_connector_name(&connector->base));
3891
3892 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3893 "wrong connector dpms state\n");
3894 WARN(connector->base.encoder != &encoder->base,
3895 "active connector not linked to encoder\n");
3896 WARN(!encoder->connectors_active,
3897 "encoder->connectors_active not set\n");
3898
3899 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3900 WARN(!encoder_enabled, "encoder not enabled\n");
3901 if (WARN_ON(!encoder->base.crtc))
3902 return;
3903
3904 crtc = encoder->base.crtc;
3905
3906 WARN(!crtc->enabled, "crtc not enabled\n");
3907 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3908 WARN(pipe != to_intel_crtc(crtc)->pipe,
3909 "encoder active on the wrong pipe\n");
3910 }
79e53945
JB		 3911}
3912
5ab432ef
DV		 3913/* Even simpler default implementation, if there's really no special case to
3914 * consider. */
3915void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3916{
5ab432ef 3917 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3918
5ab432ef
DV		 3919 /* All the simple cases only support two dpms states. */
3920 if (mode != DRM_MODE_DPMS_ON)
3921 mode = DRM_MODE_DPMS_OFF;
d4270e57 3922
5ab432ef
DV		 3923 if (mode == connector->dpms)
3924 return;
3925
3926 connector->dpms = mode;
3927
3928 /* Only need to change hw state when actually enabled */
3929 if (encoder->base.crtc)
3930 intel_encoder_dpms(encoder, mode);
3931 else
8af6cf88 3932 WARN_ON(encoder->connectors_active != false);
0a91ca29 3933
b980514c 3934 intel_modeset_check_state(connector->dev);
79e53945
JB		 3935}
3936
f0947c37
DV		 3937/* Simple connector->get_hw_state implementation for encoders that support only
3938 * one connector and no cloning and hence the encoder state determines the state
3939 * of the connector. */
3940bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3941{
24929352 3942 enum pipe pipe = 0;
f0947c37 3943 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3944
f0947c37 3945 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3946}
3947
1857e1da
DV		 3948static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3949 struct intel_crtc_config *pipe_config)
3950{
3951 struct drm_i915_private *dev_priv = dev->dev_private;
3952 struct intel_crtc *pipe_B_crtc =
3953 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3954
3955 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3956 pipe_name(pipe), pipe_config->fdi_lanes);
3957 if (pipe_config->fdi_lanes > 4) {
3958 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3959 pipe_name(pipe), pipe_config->fdi_lanes);
3960 return false;
3961 }
3962
3963 if (IS_HASWELL(dev)) {
3964 if (pipe_config->fdi_lanes > 2) {
3965 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3966 pipe_config->fdi_lanes);
3967 return false;
3968 } else {
3969 return true;
3970 }
3971 }
3972
3973 if (INTEL_INFO(dev)->num_pipes == 2)
3974 return true;
3975
3976 /* Ivybridge 3 pipe is really complicated */
3977 switch (pipe) {
3978 case PIPE_A:
3979 return true;
3980 case PIPE_B:
3981 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3982 pipe_config->fdi_lanes > 2) {
3983 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3984 pipe_name(pipe), pipe_config->fdi_lanes);
3985 return false;
3986 }
3987 return true;
3988 case PIPE_C:
1e833f40 3989 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 3990 pipe_B_crtc->config.fdi_lanes <= 2) {
3991 if (pipe_config->fdi_lanes > 2) {
3992 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3993 pipe_name(pipe), pipe_config->fdi_lanes);
3994 return false;
3995 }
3996 } else {
3997 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3998 return false;
3999 }
4000 return true;
4001 default:
4002 BUG();
4003 }
4004}
4005
e29c22c0
DV		 4006#define RETRY 1
4007static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4008 struct intel_crtc_config *pipe_config)
877d48d5 4009{
1857e1da 4010 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4011 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4012 int lane, link_bw, fdi_dotclock;
e29c22c0 4013 bool setup_ok, needs_recompute = false;
877d48d5 4014
e29c22c0 4015retry:
877d48d5
DV		 4016 /* FDI is a binary signal running at ~2.7GHz, encoding
4017 * each output octet as 10 bits. The actual frequency
4018 * is stored as a divider into a 100MHz clock, and the
4019 * mode pixel clock is stored in units of 1KHz.
4020 * Hence the bw of each lane in terms of the mode signal
4021 * is:
4022 */
4023 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4024
ff9a6750 4025 fdi_dotclock = adjusted_mode->clock;
ef1b460d 4026 fdi_dotclock /= pipe_config->pixel_multiplier;
877d48d5 4027
2bd89a07 4028 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4029 pipe_config->pipe_bpp);
4030
4031 pipe_config->fdi_lanes = lane;
4032
2bd89a07 4033 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4034 link_bw, &pipe_config->fdi_m_n);
1857e1da 4035
e29c22c0
DV		 4036 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4037 intel_crtc->pipe, pipe_config);
4038 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4039 pipe_config->pipe_bpp -= 2*3;
4040 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4041 pipe_config->pipe_bpp);
4042 needs_recompute = true;
4043 pipe_config->bw_constrained = true;
4044
4045 goto retry;
4046 }
4047
4048 if (needs_recompute)
4049 return RETRY;
4050
4051 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4052}
4053
42db64ef
PZ		 4054static void hsw_compute_ips_config(struct intel_crtc *crtc,
4055 struct intel_crtc_config *pipe_config)
4056{
3c4ca58c
PZ		 4057 pipe_config->ips_enabled = i915_enable_ips &&
4058 hsw_crtc_supports_ips(crtc) &&
42db64ef
PZ		 4059 pipe_config->pipe_bpp == 24;
4060}
4061
a43f6e0f 4062static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4063 struct intel_crtc_config *pipe_config)
79e53945 4064{
a43f6e0f 4065 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4066 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4067
bad720ff 4068 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4069 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4070 if (pipe_config->requested_mode.clock * 3
4071 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4072 return -EINVAL;
2c07245f 4073 }
89749350 4074
f9bef081
DV		 4075 /* All interlaced capable intel hw wants timings in frames. Note though
4076 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4077 * timings, so we need to be careful not to clobber these.*/
7ae89233 4078 if (!pipe_config->timings_set)
f9bef081 4079 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4080
8693a824
DL		 4081 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4082 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4083 */
4084 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4085 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4086 return -EINVAL;
44f46b42 4087
bd080ee5 4088 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4089 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4090 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4091 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4092 * for lvds. */
4093 pipe_config->pipe_bpp = 8*3;
4094 }
4095
f5adf94e 4096 if (HAS_IPS(dev))
a43f6e0f
DV		 4097 hsw_compute_ips_config(crtc, pipe_config);
4098
4099 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4100 * clock survives for now. */
4101 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4102 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4103
877d48d5 4104 if (pipe_config->has_pch_encoder)
a43f6e0f 4105 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4106
e29c22c0 4107 return 0;
79e53945
JB		 4108}
4109
25eb05fc
JB		 4110static int valleyview_get_display_clock_speed(struct drm_device *dev)
4111{
4112 return 400000; /* FIXME */
4113}
4114
e70236a8
JB		 4115static int i945_get_display_clock_speed(struct drm_device *dev)
4116{
4117 return 400000;
4118}
79e53945 4119
e70236a8 4120static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4121{
e70236a8
JB		 4122 return 333000;
4123}
79e53945 4124
e70236a8
JB		 4125static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4126{
4127 return 200000;
4128}
79e53945 4129
e70236a8
JB		 4130static int i915gm_get_display_clock_speed(struct drm_device *dev)
4131{
4132 u16 gcfgc = 0;
79e53945 4133
e70236a8
JB		 4134 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4135
4136 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4137 return 133000;
4138 else {
4139 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4140 case GC_DISPLAY_CLOCK_333_MHZ:
4141 return 333000;
4142 default:
4143 case GC_DISPLAY_CLOCK_190_200_MHZ:
4144 return 190000;
79e53945 4145 }
e70236a8
JB		 4146 }
4147}
4148
4149static int i865_get_display_clock_speed(struct drm_device *dev)
4150{
4151 return 266000;
4152}
4153
4154static int i855_get_display_clock_speed(struct drm_device *dev)
4155{
4156 u16 hpllcc = 0;
4157 /* Assume that the hardware is in the high speed state. This
4158 * should be the default.
4159 */
4160 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4161 case GC_CLOCK_133_200:
4162 case GC_CLOCK_100_200:
4163 return 200000;
4164 case GC_CLOCK_166_250:
4165 return 250000;
4166 case GC_CLOCK_100_133:
79e53945 4167 return 133000;
e70236a8 4168 }
79e53945 4169
e70236a8
JB		 4170 /* Shouldn't happen */
4171 return 0;
4172}
79e53945 4173
e70236a8
JB		 4174static int i830_get_display_clock_speed(struct drm_device *dev)
4175{
4176 return 133000;
79e53945
JB		 4177}
4178
2c07245f 4179static void
a65851af 4180intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4181{
a65851af
VS		 4182 while (*num > DATA_LINK_M_N_MASK ||
4183 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4184 *num >>= 1;
4185 *den >>= 1;
4186 }
4187}
4188
a65851af
VS		 4189static void compute_m_n(unsigned int m, unsigned int n,
4190 uint32_t *ret_m, uint32_t *ret_n)
4191{
4192 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4193 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4194 intel_reduce_m_n_ratio(ret_m, ret_n);
4195}
4196
e69d0bc1
DV		 4197void
4198intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4199 int pixel_clock, int link_clock,
4200 struct intel_link_m_n *m_n)
2c07245f 4201{
e69d0bc1 4202 m_n->tu = 64;
a65851af
VS		 4203
4204 compute_m_n(bits_per_pixel * pixel_clock,
4205 link_clock * nlanes * 8,
4206 &m_n->gmch_m, &m_n->gmch_n);
4207
4208 compute_m_n(pixel_clock, link_clock,
4209 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4210}
4211
a7615030
CW		 4212static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4213{
72bbe58c
KP		 4214 if (i915_panel_use_ssc >= 0)
4215 return i915_panel_use_ssc != 0;
41aa3448 4216 return dev_priv->vbt.lvds_use_ssc
435793df 4217 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4218}
4219
a0c4da24
JB		 4220static int vlv_get_refclk(struct drm_crtc *crtc)
4221{
4222 struct drm_device *dev = crtc->dev;
4223 struct drm_i915_private *dev_priv = dev->dev_private;
4224 int refclk = 27000; /* for DP & HDMI */
4225
4226 return 100000; /* only one validated so far */
4227
4228 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4229 refclk = 96000;
4230 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4231 if (intel_panel_use_ssc(dev_priv))
4232 refclk = 100000;
4233 else
4234 refclk = 96000;
4235 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4236 refclk = 100000;
4237 }
4238
4239 return refclk;
4240}
4241
c65d77d8
JB		 4242static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4243{
4244 struct drm_device *dev = crtc->dev;
4245 struct drm_i915_private *dev_priv = dev->dev_private;
4246 int refclk;
4247
a0c4da24
JB		 4248 if (IS_VALLEYVIEW(dev)) {
4249 refclk = vlv_get_refclk(crtc);
4250 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4251 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4252 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4253 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4254 refclk / 1000);
4255 } else if (!IS_GEN2(dev)) {
4256 refclk = 96000;
4257 } else {
4258 refclk = 48000;
4259 }
4260
4261 return refclk;
4262}
4263
7429e9d4 4264static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4265{
7df00d7a 4266 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4267}
f47709a9 4268
7429e9d4
DV		 4269static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4270{
4271 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4272}
4273
f47709a9 4274static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4275 intel_clock_t *reduced_clock)
4276{
f47709a9 4277 struct drm_device *dev = crtc->base.dev;
a7516a05 4278 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4279 int pipe = crtc->pipe;
a7516a05
JB		 4280 u32 fp, fp2 = 0;
4281
4282 if (IS_PINEVIEW(dev)) {
7429e9d4 4283 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4284 if (reduced_clock)
7429e9d4 4285 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4286 } else {
7429e9d4 4287 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4288 if (reduced_clock)
7429e9d4 4289 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4290 }
4291
4292 I915_WRITE(FP0(pipe), fp);
8bcc2795 4293 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4294
f47709a9
DV		 4295 crtc->lowfreq_avail = false;
4296 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4297 reduced_clock && i915_powersave) {
4298 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4299 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4300 crtc->lowfreq_avail = true;
a7516a05
JB		 4301 } else {
4302 I915_WRITE(FP1(pipe), fp);
8bcc2795 4303 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4304 }
4305}
4306
89b667f8
JB		 4307static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4308{
4309 u32 reg_val;
4310
4311 /*
4312 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4313 * and set it to a reasonable value instead.
4314 */
ae99258f 4315 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4316 reg_val &= 0xffffff00;
4317 reg_val |= 0x00000030;
ae99258f 4318 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4319
ae99258f 4320 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4321 reg_val &= 0x8cffffff;
4322 reg_val = 0x8c000000;
ae99258f 4323 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4324
ae99258f 4325 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4326 reg_val &= 0xffffff00;
ae99258f 4327 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4328
ae99258f 4329 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4330 reg_val &= 0x00ffffff;
4331 reg_val |= 0xb0000000;
ae99258f 4332 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4333}
4334
b551842d
DV		 4335static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4336 struct intel_link_m_n *m_n)
4337{
4338 struct drm_device *dev = crtc->base.dev;
4339 struct drm_i915_private *dev_priv = dev->dev_private;
4340 int pipe = crtc->pipe;
4341
e3b95f1e
DV		 4342 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4343 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4344 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4345 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4346}
4347
4348static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4349 struct intel_link_m_n *m_n)
4350{
4351 struct drm_device *dev = crtc->base.dev;
4352 struct drm_i915_private *dev_priv = dev->dev_private;
4353 int pipe = crtc->pipe;
4354 enum transcoder transcoder = crtc->config.cpu_transcoder;
4355
4356 if (INTEL_INFO(dev)->gen >= 5) {
4357 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4358 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4359 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4360 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4361 } else {
e3b95f1e
DV		 4362 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4363 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4364 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4365 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4366 }
4367}
4368
03afc4a2
DV		 4369static void intel_dp_set_m_n(struct intel_crtc *crtc)
4370{
4371 if (crtc->config.has_pch_encoder)
4372 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4373 else
4374 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4375}
4376
f47709a9 4377static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4378{
f47709a9 4379 struct drm_device *dev = crtc->base.dev;
a0c4da24 4380 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8 4381 struct intel_encoder *encoder;
f47709a9 4382 int pipe = crtc->pipe;
89b667f8 4383 u32 dpll, mdiv;
a0c4da24 4384 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4385 bool is_hdmi;
198a037f 4386 u32 coreclk, reg_val, dpll_md;
a0c4da24 4387
09153000
DV		 4388 mutex_lock(&dev_priv->dpio_lock);
4389
89b667f8 4390 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4391
f47709a9
DV		 4392 bestn = crtc->config.dpll.n;
4393 bestm1 = crtc->config.dpll.m1;
4394 bestm2 = crtc->config.dpll.m2;
4395 bestp1 = crtc->config.dpll.p1;
4396 bestp2 = crtc->config.dpll.p2;
a0c4da24 4397
89b667f8
JB		 4398 /* See eDP HDMI DPIO driver vbios notes doc */
4399
4400 /* PLL B needs special handling */
4401 if (pipe)
4402 vlv_pllb_recal_opamp(dev_priv);
4403
4404 /* Set up Tx target for periodic Rcomp update */
ae99258f 4405 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4406
4407 /* Disable target IRef on PLL */
ae99258f 4408 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4409 reg_val &= 0x00ffffff;
ae99258f 4410 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4411
4412 /* Disable fast lock */
ae99258f 4413 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4414
4415 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4416 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4417 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4418 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4419 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4420
4421 /*
4422 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4423 * but we don't support that).
4424 * Note: don't use the DAC post divider as it seems unstable.
4425 */
4426 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4427 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4428
a0c4da24 4429 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4430 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4431
89b667f8 4432 /* Set HBR and RBR LPF coefficients */
ff9a6750 4433 if (crtc->config.port_clock == 162000 ||
99750bd4 4434 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4435 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4abb2c39 4436 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4437 0x005f0021);
4438 else
4abb2c39 4439 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4440 0x00d0000f);
4441
4442 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4443 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4444 /* Use SSC source */
4445 if (!pipe)
ae99258f 4446 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4447 0x0df40000);
4448 else
ae99258f 4449 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4450 0x0df70000);
4451 } else { /* HDMI or VGA */
4452 /* Use bend source */
4453 if (!pipe)
ae99258f 4454 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4455 0x0df70000);
4456 else
ae99258f 4457 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4458 0x0df40000);
4459 }
a0c4da24 4460
ae99258f 4461 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4462 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4463 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4464 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4465 coreclk |= 0x01000000;
ae99258f 4466 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4467
ae99258f 4468 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4469
89b667f8
JB		 4470 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4471 if (encoder->pre_pll_enable)
4472 encoder->pre_pll_enable(encoder);
a0c4da24 4473
89b667f8
JB		 4474 /* Enable DPIO clock input */
4475 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4476 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4477 if (pipe)
4478 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4479
4480 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4481 crtc->config.dpll_hw_state.dpll = dpll;
4482
a0c4da24
JB		 4483 I915_WRITE(DPLL(pipe), dpll);
4484 POSTING_READ(DPLL(pipe));
2a8f64ca 4485 udelay(150);
a0c4da24 4486
a0c4da24
JB		 4487 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4488 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4489
ef1b460d
DV		 4490 dpll_md = (crtc->config.pixel_multiplier - 1)
4491 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4492 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4493
198a037f 4494 I915_WRITE(DPLL_MD(pipe), dpll_md);
2a8f64ca 4495 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4496
89b667f8
JB		 4497 if (crtc->config.has_dp_encoder)
4498 intel_dp_set_m_n(crtc);
09153000
DV		 4499
4500 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4501}
4502
f47709a9
DV		 4503static void i9xx_update_pll(struct intel_crtc *crtc,
4504 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4505 int num_connectors)
4506{
f47709a9 4507 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4508 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4509 u32 dpll;
4510 bool is_sdvo;
f47709a9 4511 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4512
f47709a9 4513 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4514
f47709a9
DV		 4515 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4516 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4517
4518 dpll = DPLL_VGA_MODE_DIS;
4519
f47709a9 4520 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4521 dpll |= DPLLB_MODE_LVDS;
4522 else
4523 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4524
ef1b460d 4525 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4526 dpll |= (crtc->config.pixel_multiplier - 1)
4527 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4528 }
198a037f
DV		 4529
4530 if (is_sdvo)
4531 dpll |= DPLL_DVO_HIGH_SPEED;
4532
f47709a9 4533 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4534 dpll |= DPLL_DVO_HIGH_SPEED;
4535
4536 /* compute bitmask from p1 value */
4537 if (IS_PINEVIEW(dev))
4538 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4539 else {
4540 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4541 if (IS_G4X(dev) && reduced_clock)
4542 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4543 }
4544 switch (clock->p2) {
4545 case 5:
4546 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4547 break;
4548 case 7:
4549 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4550 break;
4551 case 10:
4552 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4553 break;
4554 case 14:
4555 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4556 break;
4557 }
4558 if (INTEL_INFO(dev)->gen >= 4)
4559 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4560
09ede541 4561 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4562 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4563 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4564 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4565 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4566 else
4567 dpll |= PLL_REF_INPUT_DREFCLK;
4568
4569 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4570 crtc->config.dpll_hw_state.dpll = dpll;
4571
eb1cbe48 4572 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4573 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4574 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4575 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4576 }
66e3d5c0
DV		 4577
4578 if (crtc->config.has_dp_encoder)
4579 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4580}
4581
f47709a9 4582static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4583 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4584 int num_connectors)
4585{
f47709a9 4586 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4587 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4588 u32 dpll;
f47709a9 4589 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4590
f47709a9 4591 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4592
eb1cbe48
DV		 4593 dpll = DPLL_VGA_MODE_DIS;
4594
f47709a9 4595 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4596 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4597 } else {
4598 if (clock->p1 == 2)
4599 dpll |= PLL_P1_DIVIDE_BY_TWO;
4600 else
4601 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4602 if (clock->p2 == 4)
4603 dpll |= PLL_P2_DIVIDE_BY_4;
4604 }
4605
f47709a9 4606 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4607 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4608 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4609 else
4610 dpll |= PLL_REF_INPUT_DREFCLK;
4611
4612 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4613 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4614}
4615
8a654f3b 4616static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4617{
4618 struct drm_device *dev = intel_crtc->base.dev;
4619 struct drm_i915_private *dev_priv = dev->dev_private;
4620 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4621 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4622 struct drm_display_mode *adjusted_mode =
4623 &intel_crtc->config.adjusted_mode;
4624 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4625 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4626
4627 /* We need to be careful not to changed the adjusted mode, for otherwise
4628 * the hw state checker will get angry at the mismatch. */
4629 crtc_vtotal = adjusted_mode->crtc_vtotal;
4630 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4631
4632 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4633 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4634 crtc_vtotal -= 1;
4635 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4636 vsyncshift = adjusted_mode->crtc_hsync_start
4637 - adjusted_mode->crtc_htotal / 2;
4638 } else {
4639 vsyncshift = 0;
4640 }
4641
4642 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4643 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4644
fe2b8f9d 4645 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4646 (adjusted_mode->crtc_hdisplay - 1) |
4647 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4648 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4649 (adjusted_mode->crtc_hblank_start - 1) |
4650 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4651 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4652 (adjusted_mode->crtc_hsync_start - 1) |
4653 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4654
fe2b8f9d 4655 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4656 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4657 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4658 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4659 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4660 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4661 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4662 (adjusted_mode->crtc_vsync_start - 1) |
4663 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4664
b5e508d4
PZ		 4665 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4666 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4667 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4668 * bits. */
4669 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4670 (pipe == PIPE_B || pipe == PIPE_C))
4671 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4672
b0e77b9c
PZ		 4673 /* pipesrc controls the size that is scaled from, which should
4674 * always be the user's requested size.
4675 */
4676 I915_WRITE(PIPESRC(pipe),
4677 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4678}
4679
1bd1bd80
DV		 4680static void intel_get_pipe_timings(struct intel_crtc *crtc,
4681 struct intel_crtc_config *pipe_config)
4682{
4683 struct drm_device *dev = crtc->base.dev;
4684 struct drm_i915_private *dev_priv = dev->dev_private;
4685 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4686 uint32_t tmp;
4687
4688 tmp = I915_READ(HTOTAL(cpu_transcoder));
4689 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4690 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4691 tmp = I915_READ(HBLANK(cpu_transcoder));
4692 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4693 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4694 tmp = I915_READ(HSYNC(cpu_transcoder));
4695 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4696 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4697
4698 tmp = I915_READ(VTOTAL(cpu_transcoder));
4699 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4700 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4701 tmp = I915_READ(VBLANK(cpu_transcoder));
4702 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4703 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4704 tmp = I915_READ(VSYNC(cpu_transcoder));
4705 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4706 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4707
4708 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4709 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4710 pipe_config->adjusted_mode.crtc_vtotal += 1;
4711 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4712 }
4713
4714 tmp = I915_READ(PIPESRC(crtc->pipe));
4715 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4716 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4717}
4718
babea61d
JB		 4719static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4720 struct intel_crtc_config *pipe_config)
4721{
4722 struct drm_crtc *crtc = &intel_crtc->base;
4723
4724 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4725 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4726 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4727 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4728
4729 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4730 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4731 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4732 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4733
4734 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4735
4736 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4737 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4738}
4739
84b046f3
DV		 4740static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4741{
4742 struct drm_device *dev = intel_crtc->base.dev;
4743 struct drm_i915_private *dev_priv = dev->dev_private;
4744 uint32_t pipeconf;
4745
9f11a9e4 4746 pipeconf = 0;
84b046f3
DV		 4747
4748 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4749 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4750 * core speed.
4751 *
4752 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4753 * pipe == 0 check?
4754 */
4755 if (intel_crtc->config.requested_mode.clock >
4756 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4757 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3
DV		 4758 }
4759
ff9ce46e
DV		 4760 /* only g4x and later have fancy bpc/dither controls */
4761 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4762 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4763 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4764 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4765 PIPECONF_DITHER_TYPE_SP;
84b046f3 4766
ff9ce46e
DV		 4767 switch (intel_crtc->config.pipe_bpp) {
4768 case 18:
4769 pipeconf |= PIPECONF_6BPC;
4770 break;
4771 case 24:
4772 pipeconf |= PIPECONF_8BPC;
4773 break;
4774 case 30:
4775 pipeconf |= PIPECONF_10BPC;
4776 break;
4777 default:
4778 /* Case prevented by intel_choose_pipe_bpp_dither. */
4779 BUG();
84b046f3
DV		 4780 }
4781 }
4782
4783 if (HAS_PIPE_CXSR(dev)) {
4784 if (intel_crtc->lowfreq_avail) {
4785 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4786 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4787 } else {
4788 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4789 }
4790 }
4791
84b046f3
DV		 4792 if (!IS_GEN2(dev) &&
4793 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4794 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4795 else
4796 pipeconf |= PIPECONF_PROGRESSIVE;
4797
9f11a9e4
DV		 4798 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4799 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4800
84b046f3
DV		 4801 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4802 POSTING_READ(PIPECONF(intel_crtc->pipe));
4803}
4804
f564048e 4805static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4806 int x, int y,
94352cf9 4807 struct drm_framebuffer *fb)
79e53945
JB		 4808{
4809 struct drm_device *dev = crtc->dev;
4810 struct drm_i915_private *dev_priv = dev->dev_private;
4811 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4812 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4813 int pipe = intel_crtc->pipe;
80824003 4814 int plane = intel_crtc->plane;
c751ce4f 4815 int refclk, num_connectors = 0;
652c393a 4816 intel_clock_t clock, reduced_clock;
84b046f3 4817 u32 dspcntr;
a16af721
DV		 4818 bool ok, has_reduced_clock = false;
4819 bool is_lvds = false;
5eddb70b 4820 struct intel_encoder *encoder;
d4906093 4821 const intel_limit_t *limit;
5c3b82e2 4822 int ret;
79e53945 4823
6c2b7c12 4824 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4825 switch (encoder->type) {
79e53945
JB		 4826 case INTEL_OUTPUT_LVDS:
4827 is_lvds = true;
4828 break;
79e53945 4829 }
43565a06 4830
c751ce4f 4831 num_connectors++;
79e53945
JB		 4832 }
4833
c65d77d8 4834 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4835
d4906093
ML		 4836 /*
4837 * Returns a set of divisors for the desired target clock with the given
4838 * refclk, or FALSE. The returned values represent the clock equation:
4839 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4840 */
1b894b59 4841 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 4842 ok = dev_priv->display.find_dpll(limit, crtc,
4843 intel_crtc->config.port_clock,
ee9300bb
DV		 4844 refclk, NULL, &clock);
4845 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4846 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4847 return -EINVAL;
79e53945
JB		 4848 }
4849
cda4b7d3 4850 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4851 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4852
ddc9003c 4853 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4854 /*
4855 * Ensure we match the reduced clock's P to the target clock.
4856 * If the clocks don't match, we can't switch the display clock
4857 * by using the FP0/FP1. In such case we will disable the LVDS
4858 * downclock feature.
4859 */
ee9300bb
DV		 4860 has_reduced_clock =
4861 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4862 dev_priv->lvds_downclock,
ee9300bb 4863 refclk, &clock,
5eddb70b 4864 &reduced_clock);
7026d4ac 4865 }
f47709a9
DV		 4866 /* Compat-code for transition, will disappear. */
4867 if (!intel_crtc->config.clock_set) {
4868 intel_crtc->config.dpll.n = clock.n;
4869 intel_crtc->config.dpll.m1 = clock.m1;
4870 intel_crtc->config.dpll.m2 = clock.m2;
4871 intel_crtc->config.dpll.p1 = clock.p1;
4872 intel_crtc->config.dpll.p2 = clock.p2;
4873 }
7026d4ac 4874
eb1cbe48 4875 if (IS_GEN2(dev))
8a654f3b 4876 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4877 has_reduced_clock ? &reduced_clock : NULL,
4878 num_connectors);
a0c4da24 4879 else if (IS_VALLEYVIEW(dev))
f47709a9 4880 vlv_update_pll(intel_crtc);
79e53945 4881 else
f47709a9 4882 i9xx_update_pll(intel_crtc,
eb1cbe48 4883 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4884 num_connectors);
79e53945 4885
79e53945
JB		 4886 /* Set up the display plane register */
4887 dspcntr = DISPPLANE_GAMMA_ENABLE;
4888
da6ecc5d
JB		 4889 if (!IS_VALLEYVIEW(dev)) {
4890 if (pipe == 0)
4891 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4892 else
4893 dspcntr |= DISPPLANE_SEL_PIPE_B;
4894 }
79e53945 4895
8a654f3b 4896 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4897
4898 /* pipesrc and dspsize control the size that is scaled from,
4899 * which should always be the user's requested size.
79e53945 4900 */
929c77fb
EA		 4901 I915_WRITE(DSPSIZE(plane),
4902 ((mode->vdisplay - 1) << 16) |
4903 (mode->hdisplay - 1));
4904 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4905
84b046f3
DV		 4906 i9xx_set_pipeconf(intel_crtc);
4907
f564048e
EA		 4908 I915_WRITE(DSPCNTR(plane), dspcntr);
4909 POSTING_READ(DSPCNTR(plane));
4910
94352cf9 4911 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4912
4913 intel_update_watermarks(dev);
4914
f564048e
EA		 4915 return ret;
4916}
4917
2fa2fe9a
DV		 4918static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4919 struct intel_crtc_config *pipe_config)
4920{
4921 struct drm_device *dev = crtc->base.dev;
4922 struct drm_i915_private *dev_priv = dev->dev_private;
4923 uint32_t tmp;
4924
4925 tmp = I915_READ(PFIT_CONTROL);
4926
4927 if (INTEL_INFO(dev)->gen < 4) {
4928 if (crtc->pipe != PIPE_B)
4929 return;
4930
4931 /* gen2/3 store dither state in pfit control, needs to match */
4932 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4933 } else {
4934 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4935 return;
4936 }
4937
4938 if (!(tmp & PFIT_ENABLE))
4939 return;
4940
4941 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4942 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4943 if (INTEL_INFO(dev)->gen < 5)
4944 pipe_config->gmch_pfit.lvds_border_bits =
4945 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4946}
4947
0e8ffe1b
DV		 4948static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4949 struct intel_crtc_config *pipe_config)
4950{
4951 struct drm_device *dev = crtc->base.dev;
4952 struct drm_i915_private *dev_priv = dev->dev_private;
4953 uint32_t tmp;
4954
eccb140b 4955 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62 4956 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 4957
0e8ffe1b
DV		 4958 tmp = I915_READ(PIPECONF(crtc->pipe));
4959 if (!(tmp & PIPECONF_ENABLE))
4960 return false;
4961
1bd1bd80
DV		 4962 intel_get_pipe_timings(crtc, pipe_config);
4963
2fa2fe9a
DV		 4964 i9xx_get_pfit_config(crtc, pipe_config);
4965
6c49f241
DV		 4966 if (INTEL_INFO(dev)->gen >= 4) {
4967 tmp = I915_READ(DPLL_MD(crtc->pipe));
4968 pipe_config->pixel_multiplier =
4969 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
4970 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 4971 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 4972 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
4973 tmp = I915_READ(DPLL(crtc->pipe));
4974 pipe_config->pixel_multiplier =
4975 ((tmp & SDVO_MULTIPLIER_MASK)
4976 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
4977 } else {
4978 /* Note that on i915G/GM the pixel multiplier is in the sdvo
4979 * port and will be fixed up in the encoder->get_config
4980 * function. */
4981 pipe_config->pixel_multiplier = 1;
4982 }
8bcc2795
DV		 4983 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
4984 if (!IS_VALLEYVIEW(dev)) {
4985 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
4986 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 4987 } else {
4988 /* Mask out read-only status bits. */
4989 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
4990 DPLL_PORTC_READY_MASK |
4991 DPLL_PORTB_READY_MASK);
8bcc2795 4992 }
6c49f241 4993
0e8ffe1b
DV		 4994 return true;
4995}
4996
dde86e2d 4997static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4998{
4999 struct drm_i915_private *dev_priv = dev->dev_private;
5000 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5001 struct intel_encoder *encoder;
74cfd7ac 5002 u32 val, final;
13d83a67 5003 bool has_lvds = false;
199e5d79 5004 bool has_cpu_edp = false;
199e5d79 5005 bool has_panel = false;
99eb6a01
KP		 5006 bool has_ck505 = false;
5007 bool can_ssc = false;
13d83a67
JB		 5008
5009 /* We need to take the global config into account */
199e5d79
KP		 5010 list_for_each_entry(encoder, &mode_config->encoder_list,
5011 base.head) {
5012 switch (encoder->type) {
5013 case INTEL_OUTPUT_LVDS:
5014 has_panel = true;
5015 has_lvds = true;
5016 break;
5017 case INTEL_OUTPUT_EDP:
5018 has_panel = true;
2de6905f 5019 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5020 has_cpu_edp = true;
5021 break;
13d83a67
JB		 5022 }
5023 }
5024
99eb6a01 5025 if (HAS_PCH_IBX(dev)) {
41aa3448 5026 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5027 can_ssc = has_ck505;
5028 } else {
5029 has_ck505 = false;
5030 can_ssc = true;
5031 }
5032
2de6905f
ID		 5033 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5034 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5035
5036 /* Ironlake: try to setup display ref clock before DPLL
5037 * enabling. This is only under driver's control after
5038 * PCH B stepping, previous chipset stepping should be
5039 * ignoring this setting.
5040 */
74cfd7ac
CW		 5041 val = I915_READ(PCH_DREF_CONTROL);
5042
5043 /* As we must carefully and slowly disable/enable each source in turn,
5044 * compute the final state we want first and check if we need to
5045 * make any changes at all.
5046 */
5047 final = val;
5048 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5049 if (has_ck505)
5050 final |= DREF_NONSPREAD_CK505_ENABLE;
5051 else
5052 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5053
5054 final &= ~DREF_SSC_SOURCE_MASK;
5055 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5056 final &= ~DREF_SSC1_ENABLE;
5057
5058 if (has_panel) {
5059 final |= DREF_SSC_SOURCE_ENABLE;
5060
5061 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5062 final |= DREF_SSC1_ENABLE;
5063
5064 if (has_cpu_edp) {
5065 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5066 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5067 else
5068 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5069 } else
5070 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5071 } else {
5072 final |= DREF_SSC_SOURCE_DISABLE;
5073 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5074 }
5075
5076 if (final == val)
5077 return;
5078
13d83a67 5079 /* Always enable nonspread source */
74cfd7ac 5080 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5081
99eb6a01 5082 if (has_ck505)
74cfd7ac 5083 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5084 else
74cfd7ac 5085 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5086
199e5d79 5087 if (has_panel) {
74cfd7ac
CW		 5088 val &= ~DREF_SSC_SOURCE_MASK;
5089 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5090
199e5d79 5091 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5092 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5093 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5094 val |= DREF_SSC1_ENABLE;
e77166b5 5095 } else
74cfd7ac 5096 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5097
5098 /* Get SSC going before enabling the outputs */
74cfd7ac 5099 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5100 POSTING_READ(PCH_DREF_CONTROL);
5101 udelay(200);
5102
74cfd7ac 5103 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5104
5105 /* Enable CPU source on CPU attached eDP */
199e5d79 5106 if (has_cpu_edp) {
99eb6a01 5107 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5108 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5109 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5110 }
13d83a67 5111 else
74cfd7ac 5112 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5113 } else
74cfd7ac 5114 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5115
74cfd7ac 5116 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5117 POSTING_READ(PCH_DREF_CONTROL);
5118 udelay(200);
5119 } else {
5120 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5121
74cfd7ac 5122 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5123
5124 /* Turn off CPU output */
74cfd7ac 5125 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5126
74cfd7ac 5127 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5128 POSTING_READ(PCH_DREF_CONTROL);
5129 udelay(200);
5130
5131 /* Turn off the SSC source */
74cfd7ac
CW		 5132 val &= ~DREF_SSC_SOURCE_MASK;
5133 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5134
5135 /* Turn off SSC1 */
74cfd7ac 5136 val &= ~DREF_SSC1_ENABLE;
199e5d79 5137
74cfd7ac 5138 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5139 POSTING_READ(PCH_DREF_CONTROL);
5140 udelay(200);
5141 }
74cfd7ac
CW		 5142
5143 BUG_ON(val != final);
13d83a67
JB		 5144}
5145
dde86e2d
PZ		 5146/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5147static void lpt_init_pch_refclk(struct drm_device *dev)
5148{
5149 struct drm_i915_private *dev_priv = dev->dev_private;
5150 struct drm_mode_config *mode_config = &dev->mode_config;
5151 struct intel_encoder *encoder;
5152 bool has_vga = false;
5153 bool is_sdv = false;
5154 u32 tmp;
5155
5156 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5157 switch (encoder->type) {
5158 case INTEL_OUTPUT_ANALOG:
5159 has_vga = true;
5160 break;
5161 }
5162 }
5163
5164 if (!has_vga)
5165 return;
5166
c00db246
DV		 5167 mutex_lock(&dev_priv->dpio_lock);
5168
dde86e2d
PZ		 5169 /* XXX: Rip out SDV support once Haswell ships for real. */
5170 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5171 is_sdv = true;
5172
5173 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5174 tmp &= ~SBI_SSCCTL_DISABLE;
5175 tmp |= SBI_SSCCTL_PATHALT;
5176 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5177
5178 udelay(24);
5179
5180 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5181 tmp &= ~SBI_SSCCTL_PATHALT;
5182 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5183
5184 if (!is_sdv) {
5185 tmp = I915_READ(SOUTH_CHICKEN2);
5186 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5187 I915_WRITE(SOUTH_CHICKEN2, tmp);
5188
5189 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5190 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5191 DRM_ERROR("FDI mPHY reset assert timeout\n");
5192
5193 tmp = I915_READ(SOUTH_CHICKEN2);
5194 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5195 I915_WRITE(SOUTH_CHICKEN2, tmp);
5196
5197 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5198 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5199 100))
5200 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5201 }
5202
5203 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5204 tmp &= ~(0xFF << 24);
5205 tmp |= (0x12 << 24);
5206 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5207
dde86e2d
PZ		 5208 if (is_sdv) {
5209 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5210 tmp |= 0x7FFF;
5211 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5212 }
5213
5214 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5215 tmp |= (1 << 11);
5216 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5217
5218 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5219 tmp |= (1 << 11);
5220 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5221
5222 if (is_sdv) {
5223 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5224 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5225 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5226
5227 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5228 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5229 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5230
5231 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5232 tmp |= (0x3F << 8);
5233 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5234
5235 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5236 tmp |= (0x3F << 8);
5237 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5238 }
5239
5240 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5241 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5242 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5243
5244 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5245 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5246 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5247
5248 if (!is_sdv) {
5249 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5250 tmp &= ~(7 << 13);
5251 tmp |= (5 << 13);
5252 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5253
5254 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5255 tmp &= ~(7 << 13);
5256 tmp |= (5 << 13);
5257 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5258 }
5259
5260 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5261 tmp &= ~0xFF;
5262 tmp |= 0x1C;
5263 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5264
5265 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5266 tmp &= ~0xFF;
5267 tmp |= 0x1C;
5268 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5269
5270 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5271 tmp &= ~(0xFF << 16);
5272 tmp |= (0x1C << 16);
5273 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5274
5275 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5276 tmp &= ~(0xFF << 16);
5277 tmp |= (0x1C << 16);
5278 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5279
5280 if (!is_sdv) {
5281 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5282 tmp |= (1 << 27);
5283 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5284
5285 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5286 tmp |= (1 << 27);
5287 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5288
5289 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5290 tmp &= ~(0xF << 28);
5291 tmp |= (4 << 28);
5292 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5293
5294 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5295 tmp &= ~(0xF << 28);
5296 tmp |= (4 << 28);
5297 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5298 }
5299
5300 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5301 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5302 tmp |= SBI_DBUFF0_ENABLE;
5303 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5304
5305 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5306}
5307
5308/*
5309 * Initialize reference clocks when the driver loads
5310 */
5311void intel_init_pch_refclk(struct drm_device *dev)
5312{
5313 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5314 ironlake_init_pch_refclk(dev);
5315 else if (HAS_PCH_LPT(dev))
5316 lpt_init_pch_refclk(dev);
5317}
5318
d9d444cb
JB		 5319static int ironlake_get_refclk(struct drm_crtc *crtc)
5320{
5321 struct drm_device *dev = crtc->dev;
5322 struct drm_i915_private *dev_priv = dev->dev_private;
5323 struct intel_encoder *encoder;
d9d444cb
JB		 5324 int num_connectors = 0;
5325 bool is_lvds = false;
5326
6c2b7c12 5327 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5328 switch (encoder->type) {
5329 case INTEL_OUTPUT_LVDS:
5330 is_lvds = true;
5331 break;
d9d444cb
JB		 5332 }
5333 num_connectors++;
5334 }
5335
5336 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5337 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5338 dev_priv->vbt.lvds_ssc_freq);
5339 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5340 }
5341
5342 return 120000;
5343}
5344
6ff93609 5345static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5346{
c8203565 5347 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5349 int pipe = intel_crtc->pipe;
c8203565
PZ		 5350 uint32_t val;
5351
78114071 5352 val = 0;
c8203565 5353
965e0c48 5354 switch (intel_crtc->config.pipe_bpp) {
c8203565 5355 case 18:
dfd07d72 5356 val |= PIPECONF_6BPC;
c8203565
PZ		 5357 break;
5358 case 24:
dfd07d72 5359 val |= PIPECONF_8BPC;
c8203565
PZ		 5360 break;
5361 case 30:
dfd07d72 5362 val |= PIPECONF_10BPC;
c8203565
PZ		 5363 break;
5364 case 36:
dfd07d72 5365 val |= PIPECONF_12BPC;
c8203565
PZ		 5366 break;
5367 default:
cc769b62
PZ		 5368 /* Case prevented by intel_choose_pipe_bpp_dither. */
5369 BUG();
c8203565
PZ		 5370 }
5371
d8b32247 5372 if (intel_crtc->config.dither)
c8203565
PZ		 5373 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5374
6ff93609 5375 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5376 val |= PIPECONF_INTERLACED_ILK;
5377 else
5378 val |= PIPECONF_PROGRESSIVE;
5379
50f3b016 5380 if (intel_crtc->config.limited_color_range)
3685a8f3 5381 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5382
c8203565
PZ		 5383 I915_WRITE(PIPECONF(pipe), val);
5384 POSTING_READ(PIPECONF(pipe));
5385}
5386
86d3efce
VS		 5387/*
5388 * Set up the pipe CSC unit.
5389 *
5390 * Currently only full range RGB to limited range RGB conversion
5391 * is supported, but eventually this should handle various
5392 * RGB<->YCbCr scenarios as well.
5393 */
50f3b016 5394static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5395{
5396 struct drm_device *dev = crtc->dev;
5397 struct drm_i915_private *dev_priv = dev->dev_private;
5398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5399 int pipe = intel_crtc->pipe;
5400 uint16_t coeff = 0x7800; /* 1.0 */
5401
5402 /*
5403 * TODO: Check what kind of values actually come out of the pipe
5404 * with these coeff/postoff values and adjust to get the best
5405 * accuracy. Perhaps we even need to take the bpc value into
5406 * consideration.
5407 */
5408
50f3b016 5409 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5410 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5411
5412 /*
5413 * GY/GU and RY/RU should be the other way around according
5414 * to BSpec, but reality doesn't agree. Just set them up in
5415 * a way that results in the correct picture.
5416 */
5417 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5418 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5419
5420 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5421 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5422
5423 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5424 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5425
5426 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5427 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5428 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5429
5430 if (INTEL_INFO(dev)->gen > 6) {
5431 uint16_t postoff = 0;
5432
50f3b016 5433 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5434 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5435
5436 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5437 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5438 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5439
5440 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5441 } else {
5442 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5443
50f3b016 5444 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5445 mode |= CSC_BLACK_SCREEN_OFFSET;
5446
5447 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5448 }
5449}
5450
6ff93609 5451static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5452{
5453 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5454 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5455 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5456 uint32_t val;
5457
3eff4faa 5458 val = 0;
ee2b0b38 5459
d8b32247 5460 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5461 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5462
6ff93609 5463 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5464 val |= PIPECONF_INTERLACED_ILK;
5465 else
5466 val |= PIPECONF_PROGRESSIVE;
5467
702e7a56
PZ		 5468 I915_WRITE(PIPECONF(cpu_transcoder), val);
5469 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5470
5471 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5472 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5473}
5474
6591c6e4 5475static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5476 intel_clock_t *clock,
5477 bool *has_reduced_clock,
5478 intel_clock_t *reduced_clock)
5479{
5480 struct drm_device *dev = crtc->dev;
5481 struct drm_i915_private *dev_priv = dev->dev_private;
5482 struct intel_encoder *intel_encoder;
5483 int refclk;
d4906093 5484 const intel_limit_t *limit;
a16af721 5485 bool ret, is_lvds = false;
79e53945 5486
6591c6e4
PZ		 5487 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5488 switch (intel_encoder->type) {
79e53945
JB		 5489 case INTEL_OUTPUT_LVDS:
5490 is_lvds = true;
5491 break;
79e53945
JB		 5492 }
5493 }
5494
d9d444cb 5495 refclk = ironlake_get_refclk(crtc);
79e53945 5496
d4906093
ML		 5497 /*
5498 * Returns a set of divisors for the desired target clock with the given
5499 * refclk, or FALSE. The returned values represent the clock equation:
5500 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5501 */
1b894b59 5502 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5503 ret = dev_priv->display.find_dpll(limit, crtc,
5504 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5505 refclk, NULL, clock);
6591c6e4
PZ		 5506 if (!ret)
5507 return false;
cda4b7d3 5508
ddc9003c 5509 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5510 /*
5511 * Ensure we match the reduced clock's P to the target clock.
5512 * If the clocks don't match, we can't switch the display clock
5513 * by using the FP0/FP1. In such case we will disable the LVDS
5514 * downclock feature.
5515 */
ee9300bb
DV		 5516 *has_reduced_clock =
5517 dev_priv->display.find_dpll(limit, crtc,
5518 dev_priv->lvds_downclock,
5519 refclk, clock,
5520 reduced_clock);
652c393a 5521 }
61e9653f 5522
6591c6e4
PZ		 5523 return true;
5524}
5525
01a415fd
DV		 5526static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5527{
5528 struct drm_i915_private *dev_priv = dev->dev_private;
5529 uint32_t temp;
5530
5531 temp = I915_READ(SOUTH_CHICKEN1);
5532 if (temp & FDI_BC_BIFURCATION_SELECT)
5533 return;
5534
5535 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5536 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5537
5538 temp |= FDI_BC_BIFURCATION_SELECT;
5539 DRM_DEBUG_KMS("enabling fdi C rx\n");
5540 I915_WRITE(SOUTH_CHICKEN1, temp);
5541 POSTING_READ(SOUTH_CHICKEN1);
5542}
5543
ebfd86fd 5544static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5545{
5546 struct drm_device *dev = intel_crtc->base.dev;
5547 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5548
5549 switch (intel_crtc->pipe) {
5550 case PIPE_A:
ebfd86fd 5551 break;
01a415fd 5552 case PIPE_B:
ebfd86fd 5553 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5554 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5555 else
5556 cpt_enable_fdi_bc_bifurcation(dev);
5557
ebfd86fd 5558 break;
01a415fd 5559 case PIPE_C:
01a415fd
DV		 5560 cpt_enable_fdi_bc_bifurcation(dev);
5561
ebfd86fd 5562 break;
01a415fd
DV		 5563 default:
5564 BUG();
5565 }
5566}
5567
d4b1931c
PZ		 5568int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5569{
5570 /*
5571 * Account for spread spectrum to avoid
5572 * oversubscribing the link. Max center spread
5573 * is 2.5%; use 5% for safety's sake.
5574 */
5575 u32 bps = target_clock * bpp * 21 / 20;
5576 return bps / (link_bw * 8) + 1;
5577}
5578
7429e9d4 5579static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5580{
7429e9d4 5581 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5582}
5583
de13a2e3 5584static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5585 u32 *fp,
9a7c7890 5586 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5587{
de13a2e3 5588 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5589 struct drm_device *dev = crtc->dev;
5590 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5591 struct intel_encoder *intel_encoder;
5592 uint32_t dpll;
6cc5f341 5593 int factor, num_connectors = 0;
09ede541 5594 bool is_lvds = false, is_sdvo = false;
79e53945 5595
de13a2e3
PZ		 5596 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5597 switch (intel_encoder->type) {
79e53945
JB		 5598 case INTEL_OUTPUT_LVDS:
5599 is_lvds = true;
5600 break;
5601 case INTEL_OUTPUT_SDVO:
7d57382e 5602 case INTEL_OUTPUT_HDMI:
79e53945 5603 is_sdvo = true;
79e53945 5604 break;
79e53945 5605 }
43565a06 5606
c751ce4f 5607 num_connectors++;
79e53945 5608 }
79e53945 5609
c1858123 5610 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5611 factor = 21;
5612 if (is_lvds) {
5613 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5614 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5615 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5616 factor = 25;
09ede541 5617 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5618 factor = 20;
c1858123 5619
7429e9d4 5620 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5621 *fp |= FP_CB_TUNE;
2c07245f 5622
9a7c7890
DV		 5623 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5624 *fp2 |= FP_CB_TUNE;
5625
5eddb70b 5626 dpll = 0;
2c07245f 5627
a07d6787
EA		 5628 if (is_lvds)
5629 dpll |= DPLLB_MODE_LVDS;
5630 else
5631 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5632
ef1b460d
DV		 5633 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5634 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5635
5636 if (is_sdvo)
5637 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5638 if (intel_crtc->config.has_dp_encoder)
a07d6787 5639 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5640
a07d6787 5641 /* compute bitmask from p1 value */
7429e9d4 5642 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5643 /* also FPA1 */
7429e9d4 5644 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5645
7429e9d4 5646 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5647 case 5:
5648 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5649 break;
5650 case 7:
5651 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5652 break;
5653 case 10:
5654 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5655 break;
5656 case 14:
5657 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5658 break;
79e53945
JB		 5659 }
5660
b4c09f3b 5661 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5662 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5663 else
5664 dpll |= PLL_REF_INPUT_DREFCLK;
5665
959e16d6 5666 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5667}
5668
5669static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5670 int x, int y,
5671 struct drm_framebuffer *fb)
5672{
5673 struct drm_device *dev = crtc->dev;
5674 struct drm_i915_private *dev_priv = dev->dev_private;
5675 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5676 int pipe = intel_crtc->pipe;
5677 int plane = intel_crtc->plane;
5678 int num_connectors = 0;
5679 intel_clock_t clock, reduced_clock;
cbbab5bd 5680 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5681 bool ok, has_reduced_clock = false;
8b47047b 5682 bool is_lvds = false;
de13a2e3 5683 struct intel_encoder *encoder;
e2b78267 5684 struct intel_shared_dpll *pll;
de13a2e3 5685 int ret;
de13a2e3
PZ		 5686
5687 for_each_encoder_on_crtc(dev, crtc, encoder) {
5688 switch (encoder->type) {
5689 case INTEL_OUTPUT_LVDS:
5690 is_lvds = true;
5691 break;
de13a2e3
PZ		 5692 }
5693
5694 num_connectors++;
a07d6787 5695 }
79e53945 5696
5dc5298b
PZ		 5697 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5698 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5699
ff9a6750 5700 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5701 &has_reduced_clock, &reduced_clock);
ee9300bb 5702 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5703 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5704 return -EINVAL;
79e53945 5705 }
f47709a9
DV		 5706 /* Compat-code for transition, will disappear. */
5707 if (!intel_crtc->config.clock_set) {
5708 intel_crtc->config.dpll.n = clock.n;
5709 intel_crtc->config.dpll.m1 = clock.m1;
5710 intel_crtc->config.dpll.m2 = clock.m2;
5711 intel_crtc->config.dpll.p1 = clock.p1;
5712 intel_crtc->config.dpll.p2 = clock.p2;
5713 }
79e53945 5714
de13a2e3
PZ		 5715 /* Ensure that the cursor is valid for the new mode before changing... */
5716 intel_crtc_update_cursor(crtc, true);
5717
5dc5298b 5718 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5719 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5720 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5721 if (has_reduced_clock)
7429e9d4 5722 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5723
7429e9d4 5724 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5725 &fp, &reduced_clock,
5726 has_reduced_clock ? &fp2 : NULL);
5727
959e16d6 5728 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5729 intel_crtc->config.dpll_hw_state.fp0 = fp;
5730 if (has_reduced_clock)
5731 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5732 else
5733 intel_crtc->config.dpll_hw_state.fp1 = fp;
5734
b89a1d39 5735 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5736 if (pll == NULL) {
84f44ce7
VS		 5737 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5738 pipe_name(pipe));
4b645f14
JB		 5739 return -EINVAL;
5740 }
ee7b9f93 5741 } else
e72f9fbf 5742 intel_put_shared_dpll(intel_crtc);
79e53945 5743
03afc4a2
DV		 5744 if (intel_crtc->config.has_dp_encoder)
5745 intel_dp_set_m_n(intel_crtc);
79e53945 5746
bcd644e0
DV		 5747 if (is_lvds && has_reduced_clock && i915_powersave)
5748 intel_crtc->lowfreq_avail = true;
5749 else
5750 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5751
5752 if (intel_crtc->config.has_pch_encoder) {
5753 pll = intel_crtc_to_shared_dpll(intel_crtc);
5754
652c393a
JB		 5755 }
5756
8a654f3b 5757 intel_set_pipe_timings(intel_crtc);
5eddb70b 5758
ca3a0ff8 5759 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5760 intel_cpu_transcoder_set_m_n(intel_crtc,
5761 &intel_crtc->config.fdi_m_n);
5762 }
2c07245f 5763
ebfd86fd
DV		 5764 if (IS_IVYBRIDGE(dev))
5765 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5766
6ff93609 5767 ironlake_set_pipeconf(crtc);
79e53945 5768
a1f9e77e
PZ		 5769 /* Set up the display plane register */
5770 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5771 POSTING_READ(DSPCNTR(plane));
79e53945 5772
94352cf9 5773 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5774
5775 intel_update_watermarks(dev);
5776
1857e1da 5777 return ret;
79e53945
JB		 5778}
5779
72419203
DV		 5780static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5781 struct intel_crtc_config *pipe_config)
5782{
5783 struct drm_device *dev = crtc->base.dev;
5784 struct drm_i915_private *dev_priv = dev->dev_private;
5785 enum transcoder transcoder = pipe_config->cpu_transcoder;
5786
5787 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5788 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5789 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5790 & ~TU_SIZE_MASK;
5791 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5792 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5793 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5794}
5795
2fa2fe9a
DV		 5796static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5797 struct intel_crtc_config *pipe_config)
5798{
5799 struct drm_device *dev = crtc->base.dev;
5800 struct drm_i915_private *dev_priv = dev->dev_private;
5801 uint32_t tmp;
5802
5803 tmp = I915_READ(PF_CTL(crtc->pipe));
5804
5805 if (tmp & PF_ENABLE) {
5806 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5807 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5808
5809 /* We currently do not free assignements of panel fitters on
5810 * ivb/hsw (since we don't use the higher upscaling modes which
5811 * differentiates them) so just WARN about this case for now. */
5812 if (IS_GEN7(dev)) {
5813 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5814 PF_PIPE_SEL_IVB(crtc->pipe));
5815 }
2fa2fe9a 5816 }
79e53945
JB		 5817}
5818
0e8ffe1b
DV		 5819static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5820 struct intel_crtc_config *pipe_config)
5821{
5822 struct drm_device *dev = crtc->base.dev;
5823 struct drm_i915_private *dev_priv = dev->dev_private;
5824 uint32_t tmp;
5825
eccb140b 5826 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62 5827 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5828
0e8ffe1b
DV		 5829 tmp = I915_READ(PIPECONF(crtc->pipe));
5830 if (!(tmp & PIPECONF_ENABLE))
5831 return false;
5832
ab9412ba 5833 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 5834 struct intel_shared_dpll *pll;
5835
88adfff1
DV		 5836 pipe_config->has_pch_encoder = true;
5837
627eb5a3
DV		 5838 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5839 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5840 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5841
5842 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 5843
c0d43d62
DV		 5844 if (HAS_PCH_IBX(dev_priv->dev)) {
5845 pipe_config->shared_dpll = crtc->pipe;
5846 } else {
5847 tmp = I915_READ(PCH_DPLL_SEL);
5848 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5849 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5850 else
5851 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5852 }
66e985c0
DV		 5853
5854 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5855
5856 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5857 &pipe_config->dpll_hw_state));
c93f54cf
DV		 5858
5859 tmp = pipe_config->dpll_hw_state.dpll;
5860 pipe_config->pixel_multiplier =
5861 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5862 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6c49f241
DV		 5863 } else {
5864 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 5865 }
5866
1bd1bd80
DV		 5867 intel_get_pipe_timings(crtc, pipe_config);
5868
2fa2fe9a
DV		 5869 ironlake_get_pfit_config(crtc, pipe_config);
5870
0e8ffe1b
DV		 5871 return true;
5872}
5873
d6dd9eb1
DV		 5874static void haswell_modeset_global_resources(struct drm_device *dev)
5875{
d6dd9eb1
DV		 5876 bool enable = false;
5877 struct intel_crtc *crtc;
d6dd9eb1
DV		 5878
5879 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 5880 if (!crtc->base.enabled)
5881 continue;
d6dd9eb1 5882
e7a639c4
DV		 5883 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5884 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 5885 enable = true;
5886 }
5887
d6dd9eb1
DV		 5888 intel_set_power_well(dev, enable);
5889}
5890
09b4ddf9 5891static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5892 int x, int y,
5893 struct drm_framebuffer *fb)
5894{
5895 struct drm_device *dev = crtc->dev;
5896 struct drm_i915_private *dev_priv = dev->dev_private;
5897 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 5898 int plane = intel_crtc->plane;
09b4ddf9 5899 int ret;
09b4ddf9 5900
ff9a6750 5901 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 5902 return -EINVAL;
5903
09b4ddf9
PZ		 5904 /* Ensure that the cursor is valid for the new mode before changing... */
5905 intel_crtc_update_cursor(crtc, true);
5906
03afc4a2
DV		 5907 if (intel_crtc->config.has_dp_encoder)
5908 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5909
5910 intel_crtc->lowfreq_avail = false;
09b4ddf9 5911
8a654f3b 5912 intel_set_pipe_timings(intel_crtc);
09b4ddf9 5913
ca3a0ff8 5914 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5915 intel_cpu_transcoder_set_m_n(intel_crtc,
5916 &intel_crtc->config.fdi_m_n);
5917 }
09b4ddf9 5918
6ff93609 5919 haswell_set_pipeconf(crtc);
09b4ddf9 5920
50f3b016 5921 intel_set_pipe_csc(crtc);
86d3efce 5922
09b4ddf9 5923 /* Set up the display plane register */
86d3efce 5924 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5925 POSTING_READ(DSPCNTR(plane));
5926
5927 ret = intel_pipe_set_base(crtc, x, y, fb);
5928
5929 intel_update_watermarks(dev);
5930
1f803ee5 5931 return ret;
79e53945
JB		 5932}
5933
0e8ffe1b
DV		 5934static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5935 struct intel_crtc_config *pipe_config)
5936{
5937 struct drm_device *dev = crtc->base.dev;
5938 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 5939 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 5940 uint32_t tmp;
5941
eccb140b 5942 pipe_config->cpu_transcoder = crtc->pipe;
c0d43d62
DV		 5943 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5944
eccb140b
DV		 5945 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5946 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5947 enum pipe trans_edp_pipe;
5948 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5949 default:
5950 WARN(1, "unknown pipe linked to edp transcoder\n");
5951 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5952 case TRANS_DDI_EDP_INPUT_A_ON:
5953 trans_edp_pipe = PIPE_A;
5954 break;
5955 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5956 trans_edp_pipe = PIPE_B;
5957 break;
5958 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5959 trans_edp_pipe = PIPE_C;
5960 break;
5961 }
5962
5963 if (trans_edp_pipe == crtc->pipe)
5964 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5965 }
5966
b97186f0 5967 if (!intel_display_power_enabled(dev,
eccb140b 5968 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 5969 return false;
5970
eccb140b 5971 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 5972 if (!(tmp & PIPECONF_ENABLE))
5973 return false;
5974
88adfff1 5975 /*
f196e6be 5976 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 5977 * DDI E. So just check whether this pipe is wired to DDI E and whether
5978 * the PCH transcoder is on.
5979 */
eccb140b 5980 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 5981 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 5982 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 5983 pipe_config->has_pch_encoder = true;
5984
627eb5a3
DV		 5985 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5986 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5987 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5988
5989 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5990 }
5991
1bd1bd80
DV		 5992 intel_get_pipe_timings(crtc, pipe_config);
5993
2fa2fe9a
DV		 5994 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5995 if (intel_display_power_enabled(dev, pfit_domain))
5996 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 5997
42db64ef
PZ		 5998 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
5999 (I915_READ(IPS_CTL) & IPS_ENABLE);
6000
6c49f241
DV		 6001 pipe_config->pixel_multiplier = 1;
6002
0e8ffe1b
DV		 6003 return true;
6004}
6005
f564048e 6006static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6007 int x, int y,
94352cf9 6008 struct drm_framebuffer *fb)
f564048e
EA		 6009{
6010 struct drm_device *dev = crtc->dev;
6011 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6012 struct drm_encoder_helper_funcs *encoder_funcs;
6013 struct intel_encoder *encoder;
0b701d27 6014 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6015 struct drm_display_mode *adjusted_mode =
6016 &intel_crtc->config.adjusted_mode;
6017 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6018 int pipe = intel_crtc->pipe;
f564048e
EA		 6019 int ret;
6020
0b701d27 6021 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6022
b8cecdf5
DV		 6023 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6024
79e53945 6025 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6026
9256aa19
DV		 6027 if (ret != 0)
6028 return ret;
6029
6030 for_each_encoder_on_crtc(dev, crtc, encoder) {
6031 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6032 encoder->base.base.id,
6033 drm_get_encoder_name(&encoder->base),
6034 mode->base.id, mode->name);
6cc5f341
DV		 6035 if (encoder->mode_set) {
6036 encoder->mode_set(encoder);
6037 } else {
6038 encoder_funcs = encoder->base.helper_private;
6039 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6040 }
9256aa19
DV		 6041 }
6042
6043 return 0;
79e53945
JB		 6044}
6045
3a9627f4
WF		 6046static bool intel_eld_uptodate(struct drm_connector *connector,
6047 int reg_eldv, uint32_t bits_eldv,
6048 int reg_elda, uint32_t bits_elda,
6049 int reg_edid)
6050{
6051 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6052 uint8_t *eld = connector->eld;
6053 uint32_t i;
6054
6055 i = I915_READ(reg_eldv);
6056 i &= bits_eldv;
6057
6058 if (!eld[0])
6059 return !i;
6060
6061 if (!i)
6062 return false;
6063
6064 i = I915_READ(reg_elda);
6065 i &= ~bits_elda;
6066 I915_WRITE(reg_elda, i);
6067
6068 for (i = 0; i < eld[2]; i++)
6069 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6070 return false;
6071
6072 return true;
6073}
6074
e0dac65e
WF		 6075static void g4x_write_eld(struct drm_connector *connector,
6076 struct drm_crtc *crtc)
6077{
6078 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6079 uint8_t *eld = connector->eld;
6080 uint32_t eldv;
6081 uint32_t len;
6082 uint32_t i;
6083
6084 i = I915_READ(G4X_AUD_VID_DID);
6085
6086 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6087 eldv = G4X_ELDV_DEVCL_DEVBLC;
6088 else
6089 eldv = G4X_ELDV_DEVCTG;
6090
3a9627f4
WF		 6091 if (intel_eld_uptodate(connector,
6092 G4X_AUD_CNTL_ST, eldv,
6093 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6094 G4X_HDMIW_HDMIEDID))
6095 return;
6096
e0dac65e
WF		 6097 i = I915_READ(G4X_AUD_CNTL_ST);
6098 i &= ~(eldv | G4X_ELD_ADDR);
6099 len = (i >> 9) & 0x1f; /* ELD buffer size */
6100 I915_WRITE(G4X_AUD_CNTL_ST, i);
6101
6102 if (!eld[0])
6103 return;
6104
6105 len = min_t(uint8_t, eld[2], len);
6106 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6107 for (i = 0; i < len; i++)
6108 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6109
6110 i = I915_READ(G4X_AUD_CNTL_ST);
6111 i |= eldv;
6112 I915_WRITE(G4X_AUD_CNTL_ST, i);
6113}
6114
83358c85
WX		 6115static void haswell_write_eld(struct drm_connector *connector,
6116 struct drm_crtc *crtc)
6117{
6118 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6119 uint8_t *eld = connector->eld;
6120 struct drm_device *dev = crtc->dev;
7b9f35a6 6121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6122 uint32_t eldv;
6123 uint32_t i;
6124 int len;
6125 int pipe = to_intel_crtc(crtc)->pipe;
6126 int tmp;
6127
6128 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6129 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6130 int aud_config = HSW_AUD_CFG(pipe);
6131 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6132
6133
6134 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6135
6136 /* Audio output enable */
6137 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6138 tmp = I915_READ(aud_cntrl_st2);
6139 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6140 I915_WRITE(aud_cntrl_st2, tmp);
6141
6142 /* Wait for 1 vertical blank */
6143 intel_wait_for_vblank(dev, pipe);
6144
6145 /* Set ELD valid state */
6146 tmp = I915_READ(aud_cntrl_st2);
6147 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6148 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6149 I915_WRITE(aud_cntrl_st2, tmp);
6150 tmp = I915_READ(aud_cntrl_st2);
6151 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6152
6153 /* Enable HDMI mode */
6154 tmp = I915_READ(aud_config);
6155 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6156 /* clear N_programing_enable and N_value_index */
6157 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6158 I915_WRITE(aud_config, tmp);
6159
6160 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6161
6162 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6163 intel_crtc->eld_vld = true;
83358c85
WX		 6164
6165 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6166 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6167 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6168 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6169 } else
6170 I915_WRITE(aud_config, 0);
6171
6172 if (intel_eld_uptodate(connector,
6173 aud_cntrl_st2, eldv,
6174 aud_cntl_st, IBX_ELD_ADDRESS,
6175 hdmiw_hdmiedid))
6176 return;
6177
6178 i = I915_READ(aud_cntrl_st2);
6179 i &= ~eldv;
6180 I915_WRITE(aud_cntrl_st2, i);
6181
6182 if (!eld[0])
6183 return;
6184
6185 i = I915_READ(aud_cntl_st);
6186 i &= ~IBX_ELD_ADDRESS;
6187 I915_WRITE(aud_cntl_st, i);
6188 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6189 DRM_DEBUG_DRIVER("port num:%d\n", i);
6190
6191 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6192 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6193 for (i = 0; i < len; i++)
6194 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6195
6196 i = I915_READ(aud_cntrl_st2);
6197 i |= eldv;
6198 I915_WRITE(aud_cntrl_st2, i);
6199
6200}
6201
e0dac65e
WF		 6202static void ironlake_write_eld(struct drm_connector *connector,
6203 struct drm_crtc *crtc)
6204{
6205 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6206 uint8_t *eld = connector->eld;
6207 uint32_t eldv;
6208 uint32_t i;
6209 int len;
6210 int hdmiw_hdmiedid;
b6daa025 6211 int aud_config;
e0dac65e
WF		 6212 int aud_cntl_st;
6213 int aud_cntrl_st2;
9b138a83 6214 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6215
b3f33cbf 6216 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6217 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6218 aud_config = IBX_AUD_CFG(pipe);
6219 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6220 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6221 } else {
9b138a83
WX		 6222 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6223 aud_config = CPT_AUD_CFG(pipe);
6224 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6225 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6226 }
6227
9b138a83 6228 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6229
6230 i = I915_READ(aud_cntl_st);
9b138a83 6231 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6232 if (!i) {
6233 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6234 /* operate blindly on all ports */
1202b4c6
WF		 6235 eldv = IBX_ELD_VALIDB;
6236 eldv |= IBX_ELD_VALIDB << 4;
6237 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6238 } else {
2582a850 6239 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6240 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6241 }
6242
3a9627f4
WF		 6243 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6244 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6245 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6246 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6247 } else
6248 I915_WRITE(aud_config, 0);
e0dac65e 6249
3a9627f4
WF		 6250 if (intel_eld_uptodate(connector,
6251 aud_cntrl_st2, eldv,
6252 aud_cntl_st, IBX_ELD_ADDRESS,
6253 hdmiw_hdmiedid))
6254 return;
6255
e0dac65e
WF		 6256 i = I915_READ(aud_cntrl_st2);
6257 i &= ~eldv;
6258 I915_WRITE(aud_cntrl_st2, i);
6259
6260 if (!eld[0])
6261 return;
6262
e0dac65e 6263 i = I915_READ(aud_cntl_st);
1202b4c6 6264 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6265 I915_WRITE(aud_cntl_st, i);
6266
6267 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6268 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6269 for (i = 0; i < len; i++)
6270 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6271
6272 i = I915_READ(aud_cntrl_st2);
6273 i |= eldv;
6274 I915_WRITE(aud_cntrl_st2, i);
6275}
6276
6277void intel_write_eld(struct drm_encoder *encoder,
6278 struct drm_display_mode *mode)
6279{
6280 struct drm_crtc *crtc = encoder->crtc;
6281 struct drm_connector *connector;
6282 struct drm_device *dev = encoder->dev;
6283 struct drm_i915_private *dev_priv = dev->dev_private;
6284
6285 connector = drm_select_eld(encoder, mode);
6286 if (!connector)
6287 return;
6288
6289 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6290 connector->base.id,
6291 drm_get_connector_name(connector),
6292 connector->encoder->base.id,
6293 drm_get_encoder_name(connector->encoder));
6294
6295 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6296
6297 if (dev_priv->display.write_eld)
6298 dev_priv->display.write_eld(connector, crtc);
6299}
6300
79e53945
JB		 6301/** Loads the palette/gamma unit for the CRTC with the prepared values */
6302void intel_crtc_load_lut(struct drm_crtc *crtc)
6303{
6304 struct drm_device *dev = crtc->dev;
6305 struct drm_i915_private *dev_priv = dev->dev_private;
6306 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6307 enum pipe pipe = intel_crtc->pipe;
6308 int palreg = PALETTE(pipe);
79e53945 6309 int i;
42db64ef 6310 bool reenable_ips = false;
79e53945
JB		 6311
6312 /* The clocks have to be on to load the palette. */
aed3f09d 6313 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6314 return;
6315
14420bd0
VS		 6316 if (!HAS_PCH_SPLIT(dev_priv->dev))
6317 assert_pll_enabled(dev_priv, pipe);
6318
f2b115e6 6319 /* use legacy palette for Ironlake */
bad720ff 6320 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6321 palreg = LGC_PALETTE(pipe);
6322
6323 /* Workaround : Do not read or write the pipe palette/gamma data while
6324 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6325 */
6326 if (intel_crtc->config.ips_enabled &&
6327 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6328 GAMMA_MODE_MODE_SPLIT)) {
6329 hsw_disable_ips(intel_crtc);
6330 reenable_ips = true;
6331 }
2c07245f 6332
79e53945
JB		 6333 for (i = 0; i < 256; i++) {
6334 I915_WRITE(palreg + 4 * i,
6335 (intel_crtc->lut_r[i] << 16) |
6336 (intel_crtc->lut_g[i] << 8) |
6337 intel_crtc->lut_b[i]);
6338 }
42db64ef
PZ		 6339
6340 if (reenable_ips)
6341 hsw_enable_ips(intel_crtc);
79e53945
JB		 6342}
6343
560b85bb
CW		 6344static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6345{
6346 struct drm_device *dev = crtc->dev;
6347 struct drm_i915_private *dev_priv = dev->dev_private;
6348 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6349 bool visible = base != 0;
6350 u32 cntl;
6351
6352 if (intel_crtc->cursor_visible == visible)
6353 return;
6354
9db4a9c7 6355 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6356 if (visible) {
6357 /* On these chipsets we can only modify the base whilst
6358 * the cursor is disabled.
6359 */
9db4a9c7 6360 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6361
6362 cntl &= ~(CURSOR_FORMAT_MASK);
6363 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6364 cntl |= CURSOR_ENABLE |
6365 CURSOR_GAMMA_ENABLE |
6366 CURSOR_FORMAT_ARGB;
6367 } else
6368 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6369 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6370
6371 intel_crtc->cursor_visible = visible;
6372}
6373
6374static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6375{
6376 struct drm_device *dev = crtc->dev;
6377 struct drm_i915_private *dev_priv = dev->dev_private;
6378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6379 int pipe = intel_crtc->pipe;
6380 bool visible = base != 0;
6381
6382 if (intel_crtc->cursor_visible != visible) {
548f245b 6383 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6384 if (base) {
6385 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6386 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6387 cntl |= pipe << 28; /* Connect to correct pipe */
6388 } else {
6389 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6390 cntl |= CURSOR_MODE_DISABLE;
6391 }
9db4a9c7 6392 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6393
6394 intel_crtc->cursor_visible = visible;
6395 }
6396 /* and commit changes on next vblank */
9db4a9c7 6397 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6398}
6399
65a21cd6
JB		 6400static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6401{
6402 struct drm_device *dev = crtc->dev;
6403 struct drm_i915_private *dev_priv = dev->dev_private;
6404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6405 int pipe = intel_crtc->pipe;
6406 bool visible = base != 0;
6407
6408 if (intel_crtc->cursor_visible != visible) {
6409 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6410 if (base) {
6411 cntl &= ~CURSOR_MODE;
6412 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6413 } else {
6414 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6415 cntl |= CURSOR_MODE_DISABLE;
6416 }
86d3efce
VS		 6417 if (IS_HASWELL(dev))
6418 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6419 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6420
6421 intel_crtc->cursor_visible = visible;
6422 }
6423 /* and commit changes on next vblank */
6424 I915_WRITE(CURBASE_IVB(pipe), base);
6425}
6426
cda4b7d3 6427/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6428static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6429 bool on)
cda4b7d3
CW		 6430{
6431 struct drm_device *dev = crtc->dev;
6432 struct drm_i915_private *dev_priv = dev->dev_private;
6433 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6434 int pipe = intel_crtc->pipe;
6435 int x = intel_crtc->cursor_x;
6436 int y = intel_crtc->cursor_y;
560b85bb 6437 u32 base, pos;
cda4b7d3
CW		 6438 bool visible;
6439
6440 pos = 0;
6441
6b383a7f 6442 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6443 base = intel_crtc->cursor_addr;
6444 if (x > (int) crtc->fb->width)
6445 base = 0;
6446
6447 if (y > (int) crtc->fb->height)
6448 base = 0;
6449 } else
6450 base = 0;
6451
6452 if (x < 0) {
6453 if (x + intel_crtc->cursor_width < 0)
6454 base = 0;
6455
6456 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6457 x = -x;
6458 }
6459 pos |= x << CURSOR_X_SHIFT;
6460
6461 if (y < 0) {
6462 if (y + intel_crtc->cursor_height < 0)
6463 base = 0;
6464
6465 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6466 y = -y;
6467 }
6468 pos |= y << CURSOR_Y_SHIFT;
6469
6470 visible = base != 0;
560b85bb 6471 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6472 return;
6473
0cd83aa9 6474 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6475 I915_WRITE(CURPOS_IVB(pipe), pos);
6476 ivb_update_cursor(crtc, base);
6477 } else {
6478 I915_WRITE(CURPOS(pipe), pos);
6479 if (IS_845G(dev) || IS_I865G(dev))
6480 i845_update_cursor(crtc, base);
6481 else
6482 i9xx_update_cursor(crtc, base);
6483 }
cda4b7d3
CW		 6484}
6485
79e53945 6486static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6487 struct drm_file *file,
79e53945
JB		 6488 uint32_t handle,
6489 uint32_t width, uint32_t height)
6490{
6491 struct drm_device *dev = crtc->dev;
6492 struct drm_i915_private *dev_priv = dev->dev_private;
6493 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6494 struct drm_i915_gem_object *obj;
cda4b7d3 6495 uint32_t addr;
3f8bc370 6496 int ret;
79e53945 6497
79e53945
JB		 6498 /* if we want to turn off the cursor ignore width and height */
6499 if (!handle) {
28c97730 6500 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6501 addr = 0;
05394f39 6502 obj = NULL;
5004417d 6503 mutex_lock(&dev->struct_mutex);
3f8bc370 6504 goto finish;
79e53945
JB		 6505 }
6506
6507 /* Currently we only support 64x64 cursors */
6508 if (width != 64 || height != 64) {
6509 DRM_ERROR("we currently only support 64x64 cursors\n");
6510 return -EINVAL;
6511 }
6512
05394f39 6513 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6514 if (&obj->base == NULL)
79e53945
JB		 6515 return -ENOENT;
6516
05394f39 6517 if (obj->base.size < width * height * 4) {
79e53945 6518 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6519 ret = -ENOMEM;
6520 goto fail;
79e53945
JB		 6521 }
6522
71acb5eb 6523 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6524 mutex_lock(&dev->struct_mutex);
b295d1b6 6525 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6526 unsigned alignment;
6527
d9e86c0e
CW		 6528 if (obj->tiling_mode) {
6529 DRM_ERROR("cursor cannot be tiled\n");
6530 ret = -EINVAL;
6531 goto fail_locked;
6532 }
6533
693db184
CW		 6534 /* Note that the w/a also requires 2 PTE of padding following
6535 * the bo. We currently fill all unused PTE with the shadow
6536 * page and so we should always have valid PTE following the
6537 * cursor preventing the VT-d warning.
6538 */
6539 alignment = 0;
6540 if (need_vtd_wa(dev))
6541 alignment = 64*1024;
6542
6543 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6544 if (ret) {
6545 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6546 goto fail_locked;
e7b526bb
CW		 6547 }
6548
d9e86c0e
CW		 6549 ret = i915_gem_object_put_fence(obj);
6550 if (ret) {
2da3b9b9 6551 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6552 goto fail_unpin;
6553 }
6554
05394f39 6555 addr = obj->gtt_offset;
71acb5eb 6556 } else {
6eeefaf3 6557 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6558 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6559 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6560 align);
71acb5eb
DA		 6561 if (ret) {
6562 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6563 goto fail_locked;
71acb5eb 6564 }
05394f39 6565 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6566 }
6567
a6c45cf0 6568 if (IS_GEN2(dev))
14b60391
JB		 6569 I915_WRITE(CURSIZE, (height << 12) | width);
6570
3f8bc370 6571 finish:
3f8bc370 6572 if (intel_crtc->cursor_bo) {
b295d1b6 6573 if (dev_priv->info->cursor_needs_physical) {
05394f39 6574 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6575 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6576 } else
6577 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6578 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6579 }
80824003 6580
7f9872e0 6581 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6582
6583 intel_crtc->cursor_addr = addr;
05394f39 6584 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6585 intel_crtc->cursor_width = width;
6586 intel_crtc->cursor_height = height;
6587
40ccc72b 6588 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6589
79e53945 6590 return 0;
e7b526bb 6591fail_unpin:
05394f39 6592 i915_gem_object_unpin(obj);
7f9872e0 6593fail_locked:
34b8686e 6594 mutex_unlock(&dev->struct_mutex);
bc9025bd 6595fail:
05394f39 6596 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6597 return ret;
79e53945
JB		 6598}
6599
6600static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6601{
79e53945 6602 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6603
cda4b7d3
CW		 6604 intel_crtc->cursor_x = x;
6605 intel_crtc->cursor_y = y;
652c393a 6606
40ccc72b 6607 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6608
6609 return 0;
6610}
6611
6612/** Sets the color ramps on behalf of RandR */
6613void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6614 u16 blue, int regno)
6615{
6616 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6617
6618 intel_crtc->lut_r[regno] = red >> 8;
6619 intel_crtc->lut_g[regno] = green >> 8;
6620 intel_crtc->lut_b[regno] = blue >> 8;
6621}
6622
b8c00ac5
DA		 6623void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6624 u16 *blue, int regno)
6625{
6626 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6627
6628 *red = intel_crtc->lut_r[regno] << 8;
6629 *green = intel_crtc->lut_g[regno] << 8;
6630 *blue = intel_crtc->lut_b[regno] << 8;
6631}
6632
79e53945 6633static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6634 u16 *blue, uint32_t start, uint32_t size)
79e53945 6635{
7203425a 6636 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6638
7203425a 6639 for (i = start; i < end; i++) {
79e53945
JB		 6640 intel_crtc->lut_r[i] = red[i] >> 8;
6641 intel_crtc->lut_g[i] = green[i] >> 8;
6642 intel_crtc->lut_b[i] = blue[i] >> 8;
6643 }
6644
6645 intel_crtc_load_lut(crtc);
6646}
6647
79e53945
JB		 6648/* VESA 640x480x72Hz mode to set on the pipe */
6649static struct drm_display_mode load_detect_mode = {
6650 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6651 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6652};
6653
d2dff872
CW		 6654static struct drm_framebuffer *
6655intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6656 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6657 struct drm_i915_gem_object *obj)
6658{
6659 struct intel_framebuffer *intel_fb;
6660 int ret;
6661
6662 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6663 if (!intel_fb) {
6664 drm_gem_object_unreference_unlocked(&obj->base);
6665 return ERR_PTR(-ENOMEM);
6666 }
6667
6668 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6669 if (ret) {
6670 drm_gem_object_unreference_unlocked(&obj->base);
6671 kfree(intel_fb);
6672 return ERR_PTR(ret);
6673 }
6674
6675 return &intel_fb->base;
6676}
6677
6678static u32
6679intel_framebuffer_pitch_for_width(int width, int bpp)
6680{
6681 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6682 return ALIGN(pitch, 64);
6683}
6684
6685static u32
6686intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6687{
6688 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6689 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6690}
6691
6692static struct drm_framebuffer *
6693intel_framebuffer_create_for_mode(struct drm_device *dev,
6694 struct drm_display_mode *mode,
6695 int depth, int bpp)
6696{
6697 struct drm_i915_gem_object *obj;
0fed39bd 6698 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6699
6700 obj = i915_gem_alloc_object(dev,
6701 intel_framebuffer_size_for_mode(mode, bpp));
6702 if (obj == NULL)
6703 return ERR_PTR(-ENOMEM);
6704
6705 mode_cmd.width = mode->hdisplay;
6706 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6707 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6708 bpp);
5ca0c34a 6709 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6710
6711 return intel_framebuffer_create(dev, &mode_cmd, obj);
6712}
6713
6714static struct drm_framebuffer *
6715mode_fits_in_fbdev(struct drm_device *dev,
6716 struct drm_display_mode *mode)
6717{
6718 struct drm_i915_private *dev_priv = dev->dev_private;
6719 struct drm_i915_gem_object *obj;
6720 struct drm_framebuffer *fb;
6721
6722 if (dev_priv->fbdev == NULL)
6723 return NULL;
6724
6725 obj = dev_priv->fbdev->ifb.obj;
6726 if (obj == NULL)
6727 return NULL;
6728
6729 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6730 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6731 fb->bits_per_pixel))
d2dff872
CW		 6732 return NULL;
6733
01f2c773 6734 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6735 return NULL;
6736
6737 return fb;
6738}
6739
d2434ab7 6740bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6741 struct drm_display_mode *mode,
8261b191 6742 struct intel_load_detect_pipe *old)
79e53945
JB		 6743{
6744 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6745 struct intel_encoder *intel_encoder =
6746 intel_attached_encoder(connector);
79e53945 6747 struct drm_crtc *possible_crtc;
4ef69c7a 6748 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6749 struct drm_crtc *crtc = NULL;
6750 struct drm_device *dev = encoder->dev;
94352cf9 6751 struct drm_framebuffer *fb;
79e53945
JB		 6752 int i = -1;
6753
d2dff872
CW		 6754 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6755 connector->base.id, drm_get_connector_name(connector),
6756 encoder->base.id, drm_get_encoder_name(encoder));
6757
79e53945
JB		 6758 /*
6759 * Algorithm gets a little messy:
7a5e4805 6760 *
79e53945
JB		 6761 * - if the connector already has an assigned crtc, use it (but make
6762 * sure it's on first)
7a5e4805 6763 *
79e53945
JB		 6764 * - try to find the first unused crtc that can drive this connector,
6765 * and use that if we find one
79e53945
JB		 6766 */
6767
6768 /* See if we already have a CRTC for this connector */
6769 if (encoder->crtc) {
6770 crtc = encoder->crtc;
8261b191 6771
7b24056b
DV		 6772 mutex_lock(&crtc->mutex);
6773
24218aac 6774 old->dpms_mode = connector->dpms;
8261b191
CW		 6775 old->load_detect_temp = false;
6776
6777 /* Make sure the crtc and connector are running */
24218aac
DV		 6778 if (connector->dpms != DRM_MODE_DPMS_ON)
6779 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6780
7173188d 6781 return true;
79e53945
JB		 6782 }
6783
6784 /* Find an unused one (if possible) */
6785 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6786 i++;
6787 if (!(encoder->possible_crtcs & (1 << i)))
6788 continue;
6789 if (!possible_crtc->enabled) {
6790 crtc = possible_crtc;
6791 break;
6792 }
79e53945
JB		 6793 }
6794
6795 /*
6796 * If we didn't find an unused CRTC, don't use any.
6797 */
6798 if (!crtc) {
7173188d
CW		 6799 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6800 return false;
79e53945
JB		 6801 }
6802
7b24056b 6803 mutex_lock(&crtc->mutex);
fc303101
DV		 6804 intel_encoder->new_crtc = to_intel_crtc(crtc);
6805 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6806
6807 intel_crtc = to_intel_crtc(crtc);
24218aac 6808 old->dpms_mode = connector->dpms;
8261b191 6809 old->load_detect_temp = true;
d2dff872 6810 old->release_fb = NULL;
79e53945 6811
6492711d
CW		 6812 if (!mode)
6813 mode = &load_detect_mode;
79e53945 6814
d2dff872
CW		 6815 /* We need a framebuffer large enough to accommodate all accesses
6816 * that the plane may generate whilst we perform load detection.
6817 * We can not rely on the fbcon either being present (we get called
6818 * during its initialisation to detect all boot displays, or it may
6819 * not even exist) or that it is large enough to satisfy the
6820 * requested mode.
6821 */
94352cf9
DV		 6822 fb = mode_fits_in_fbdev(dev, mode);
6823 if (fb == NULL) {
d2dff872 6824 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6825 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6826 old->release_fb = fb;
d2dff872
CW		 6827 } else
6828 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6829 if (IS_ERR(fb)) {
d2dff872 6830 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6831 mutex_unlock(&crtc->mutex);
0e8b3d3e 6832 return false;
79e53945 6833 }
79e53945 6834
c0c36b94 6835 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6836 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6837 if (old->release_fb)
6838 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6839 mutex_unlock(&crtc->mutex);
0e8b3d3e 6840 return false;
79e53945 6841 }
7173188d 6842
79e53945 6843 /* let the connector get through one full cycle before testing */
9d0498a2 6844 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6845 return true;
79e53945
JB		 6846}
6847
d2434ab7 6848void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6849 struct intel_load_detect_pipe *old)
79e53945 6850{
d2434ab7
DV		 6851 struct intel_encoder *intel_encoder =
6852 intel_attached_encoder(connector);
4ef69c7a 6853 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6854 struct drm_crtc *crtc = encoder->crtc;
79e53945 6855
d2dff872
CW		 6856 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6857 connector->base.id, drm_get_connector_name(connector),
6858 encoder->base.id, drm_get_encoder_name(encoder));
6859
8261b191 6860 if (old->load_detect_temp) {
fc303101
DV		 6861 to_intel_connector(connector)->new_encoder = NULL;
6862 intel_encoder->new_crtc = NULL;
6863 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6864
36206361
DV		 6865 if (old->release_fb) {
6866 drm_framebuffer_unregister_private(old->release_fb);
6867 drm_framebuffer_unreference(old->release_fb);
6868 }
d2dff872 6869
67c96400 6870 mutex_unlock(&crtc->mutex);
0622a53c 6871 return;
79e53945
JB		 6872 }
6873
c751ce4f 6874 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6875 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6876 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6877
6878 mutex_unlock(&crtc->mutex);
79e53945
JB		 6879}
6880
6881/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 6882static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
6883 struct intel_crtc_config *pipe_config)
79e53945 6884{
f1f644dc 6885 struct drm_device *dev = crtc->base.dev;
79e53945 6886 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 6887 int pipe = pipe_config->cpu_transcoder;
548f245b 6888 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6889 u32 fp;
6890 intel_clock_t clock;
6891
6892 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6893 fp = I915_READ(FP0(pipe));
79e53945 6894 else
39adb7a5 6895 fp = I915_READ(FP1(pipe));
79e53945
JB		 6896
6897 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6898 if (IS_PINEVIEW(dev)) {
6899 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6900 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6901 } else {
6902 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6903 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6904 }
6905
a6c45cf0 6906 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6907 if (IS_PINEVIEW(dev))
6908 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6909 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6910 else
6911 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6912 DPLL_FPA01_P1_POST_DIV_SHIFT);
6913
6914 switch (dpll & DPLL_MODE_MASK) {
6915 case DPLLB_MODE_DAC_SERIAL:
6916 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6917 5 : 10;
6918 break;
6919 case DPLLB_MODE_LVDS:
6920 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6921 7 : 14;
6922 break;
6923 default:
28c97730 6924 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 6925 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc
JB		 6926 pipe_config->adjusted_mode.clock = 0;
6927 return;
79e53945
JB		 6928 }
6929
ac58c3f0
DV		 6930 if (IS_PINEVIEW(dev))
6931 pineview_clock(96000, &clock);
6932 else
6933 i9xx_clock(96000, &clock);
79e53945
JB		 6934 } else {
6935 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6936
6937 if (is_lvds) {
6938 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6939 DPLL_FPA01_P1_POST_DIV_SHIFT);
6940 clock.p2 = 14;
6941
6942 if ((dpll & PLL_REF_INPUT_MASK) ==
6943 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6944 /* XXX: might not be 66MHz */
ac58c3f0 6945 i9xx_clock(66000, &clock);
79e53945 6946 } else
ac58c3f0 6947 i9xx_clock(48000, &clock);
79e53945
JB		 6948 } else {
6949 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6950 clock.p1 = 2;
6951 else {
6952 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6953 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6954 }
6955 if (dpll & PLL_P2_DIVIDE_BY_4)
6956 clock.p2 = 4;
6957 else
6958 clock.p2 = 2;
6959
ac58c3f0 6960 i9xx_clock(48000, &clock);
79e53945
JB		 6961 }
6962 }
6963
f1f644dc
JB		 6964 pipe_config->adjusted_mode.clock = clock.dot *
6965 pipe_config->pixel_multiplier;
6966}
6967
6968static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
6969 struct intel_crtc_config *pipe_config)
6970{
6971 struct drm_device *dev = crtc->base.dev;
6972 struct drm_i915_private *dev_priv = dev->dev_private;
6973 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6974 int link_freq, repeat;
6975 u64 clock;
6976 u32 link_m, link_n;
6977
6978 repeat = pipe_config->pixel_multiplier;
6979
6980 /*
6981 * The calculation for the data clock is:
6982 * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
6983 * But we want to avoid losing precison if possible, so:
6984 * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
6985 *
6986 * and the link clock is simpler:
6987 * link_clock = (m * link_clock * repeat) / n
6988 */
6989
6990 /*
6991 * We need to get the FDI or DP link clock here to derive
6992 * the M/N dividers.
6993 *
6994 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
6995 * For DP, it's either 1.62GHz or 2.7GHz.
6996 * We do our calculations in 10*MHz since we don't need much precison.
79e53945 6997 */
f1f644dc
JB		 6998 if (pipe_config->has_pch_encoder)
6999 link_freq = intel_fdi_link_freq(dev) * 10000;
7000 else
7001 link_freq = pipe_config->port_clock;
7002
7003 link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7004 link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7005
7006 if (!link_m || !link_n)
7007 return;
79e53945 7008
f1f644dc
JB		 7009 clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7010 do_div(clock, link_n);
7011
7012 pipe_config->adjusted_mode.clock = clock;
79e53945
JB		 7013}
7014
7015/** Returns the currently programmed mode of the given pipe. */
7016struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7017 struct drm_crtc *crtc)
7018{
548f245b 7019 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7020 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7021 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7022 struct drm_display_mode *mode;
f1f644dc 7023 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7024 int htot = I915_READ(HTOTAL(cpu_transcoder));
7025 int hsync = I915_READ(HSYNC(cpu_transcoder));
7026 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7027 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 7028
7029 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7030 if (!mode)
7031 return NULL;
7032
f1f644dc
JB		 7033 /*
7034 * Construct a pipe_config sufficient for getting the clock info
7035 * back out of crtc_clock_get.
7036 *
7037 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7038 * to use a real value here instead.
7039 */
7040 pipe_config.cpu_transcoder = intel_crtc->pipe;
7041 pipe_config.pixel_multiplier = 1;
7042 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7043
7044 mode->clock = pipe_config.adjusted_mode.clock;
79e53945
JB		 7045 mode->hdisplay = (htot & 0xffff) + 1;
7046 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7047 mode->hsync_start = (hsync & 0xffff) + 1;
7048 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7049 mode->vdisplay = (vtot & 0xffff) + 1;
7050 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7051 mode->vsync_start = (vsync & 0xffff) + 1;
7052 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7053
7054 drm_mode_set_name(mode);
79e53945
JB		 7055
7056 return mode;
7057}
7058
3dec0095 7059static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7060{
7061 struct drm_device *dev = crtc->dev;
7062 drm_i915_private_t *dev_priv = dev->dev_private;
7063 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7064 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7065 int dpll_reg = DPLL(pipe);
7066 int dpll;
652c393a 7067
bad720ff 7068 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7069 return;
7070
7071 if (!dev_priv->lvds_downclock_avail)
7072 return;
7073
dbdc6479 7074 dpll = I915_READ(dpll_reg);
652c393a 7075 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7076 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7077
8ac5a6d5 7078 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7079
7080 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7081 I915_WRITE(dpll_reg, dpll);
9d0498a2 7082 intel_wait_for_vblank(dev, pipe);
dbdc6479 7083
652c393a
JB		 7084 dpll = I915_READ(dpll_reg);
7085 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7086 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7087 }
652c393a
JB		 7088}
7089
7090static void intel_decrease_pllclock(struct drm_crtc *crtc)
7091{
7092 struct drm_device *dev = crtc->dev;
7093 drm_i915_private_t *dev_priv = dev->dev_private;
7094 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7095
bad720ff 7096 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7097 return;
7098
7099 if (!dev_priv->lvds_downclock_avail)
7100 return;
7101
7102 /*
7103 * Since this is called by a timer, we should never get here in
7104 * the manual case.
7105 */
7106 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7107 int pipe = intel_crtc->pipe;
7108 int dpll_reg = DPLL(pipe);
7109 int dpll;
f6e5b160 7110
44d98a61 7111 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7112
8ac5a6d5 7113 assert_panel_unlocked(dev_priv, pipe);
652c393a 7114
dc257cf1 7115 dpll = I915_READ(dpll_reg);
652c393a
JB		 7116 dpll |= DISPLAY_RATE_SELECT_FPA1;
7117 I915_WRITE(dpll_reg, dpll);
9d0498a2 7118 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7119 dpll = I915_READ(dpll_reg);
7120 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7121 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7122 }
7123
7124}
7125
f047e395
CW		 7126void intel_mark_busy(struct drm_device *dev)
7127{
f047e395
CW		 7128 i915_update_gfx_val(dev->dev_private);
7129}
7130
7131void intel_mark_idle(struct drm_device *dev)
652c393a 7132{
652c393a 7133 struct drm_crtc *crtc;
652c393a
JB		 7134
7135 if (!i915_powersave)
7136 return;
7137
652c393a 7138 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7139 if (!crtc->fb)
7140 continue;
7141
725a5b54 7142 intel_decrease_pllclock(crtc);
652c393a 7143 }
652c393a
JB		 7144}
7145
c65355bb
CW		 7146void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7147 struct intel_ring_buffer *ring)
652c393a 7148{
f047e395
CW		 7149 struct drm_device *dev = obj->base.dev;
7150 struct drm_crtc *crtc;
652c393a 7151
f047e395 7152 if (!i915_powersave)
acb87dfb
CW		 7153 return;
7154
652c393a
JB		 7155 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7156 if (!crtc->fb)
7157 continue;
7158
c65355bb
CW		 7159 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7160 continue;
7161
7162 intel_increase_pllclock(crtc);
7163 if (ring && intel_fbc_enabled(dev))
7164 ring->fbc_dirty = true;
652c393a
JB		 7165 }
7166}
7167
79e53945
JB		 7168static void intel_crtc_destroy(struct drm_crtc *crtc)
7169{
7170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7171 struct drm_device *dev = crtc->dev;
7172 struct intel_unpin_work *work;
7173 unsigned long flags;
7174
7175 spin_lock_irqsave(&dev->event_lock, flags);
7176 work = intel_crtc->unpin_work;
7177 intel_crtc->unpin_work = NULL;
7178 spin_unlock_irqrestore(&dev->event_lock, flags);
7179
7180 if (work) {
7181 cancel_work_sync(&work->work);
7182 kfree(work);
7183 }
79e53945 7184
40ccc72b
MK		 7185 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7186
79e53945 7187 drm_crtc_cleanup(crtc);
67e77c5a 7188
79e53945
JB		 7189 kfree(intel_crtc);
7190}
7191
6b95a207
KH		 7192static void intel_unpin_work_fn(struct work_struct *__work)
7193{
7194 struct intel_unpin_work *work =
7195 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7196 struct drm_device *dev = work->crtc->dev;
6b95a207 7197
b4a98e57 7198 mutex_lock(&dev->struct_mutex);
1690e1eb 7199 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7200 drm_gem_object_unreference(&work->pending_flip_obj->base);
7201 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7202
b4a98e57
CW		 7203 intel_update_fbc(dev);
7204 mutex_unlock(&dev->struct_mutex);
7205
7206 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7207 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7208
6b95a207
KH		 7209 kfree(work);
7210}
7211
1afe3e9d 7212static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7213 struct drm_crtc *crtc)
6b95a207
KH		 7214{
7215 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7217 struct intel_unpin_work *work;
6b95a207
KH		 7218 unsigned long flags;
7219
7220 /* Ignore early vblank irqs */
7221 if (intel_crtc == NULL)
7222 return;
7223
7224 spin_lock_irqsave(&dev->event_lock, flags);
7225 work = intel_crtc->unpin_work;
e7d841ca
CW		 7226
7227 /* Ensure we don't miss a work->pending update ... */
7228 smp_rmb();
7229
7230 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7231 spin_unlock_irqrestore(&dev->event_lock, flags);
7232 return;
7233 }
7234
e7d841ca
CW		 7235 /* and that the unpin work is consistent wrt ->pending. */
7236 smp_rmb();
7237
6b95a207 7238 intel_crtc->unpin_work = NULL;
6b95a207 7239
45a066eb
RC		 7240 if (work->event)
7241 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7242
0af7e4df
MK		 7243 drm_vblank_put(dev, intel_crtc->pipe);
7244
6b95a207
KH		 7245 spin_unlock_irqrestore(&dev->event_lock, flags);
7246
2c10d571 7247 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7248
7249 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7250
7251 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7252}
7253
1afe3e9d
JB		 7254void intel_finish_page_flip(struct drm_device *dev, int pipe)
7255{
7256 drm_i915_private_t *dev_priv = dev->dev_private;
7257 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7258
49b14a5c 7259 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7260}
7261
7262void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7263{
7264 drm_i915_private_t *dev_priv = dev->dev_private;
7265 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7266
49b14a5c 7267 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7268}
7269
6b95a207
KH		 7270void intel_prepare_page_flip(struct drm_device *dev, int plane)
7271{
7272 drm_i915_private_t *dev_priv = dev->dev_private;
7273 struct intel_crtc *intel_crtc =
7274 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7275 unsigned long flags;
7276
e7d841ca
CW		 7277 /* NB: An MMIO update of the plane base pointer will also
7278 * generate a page-flip completion irq, i.e. every modeset
7279 * is also accompanied by a spurious intel_prepare_page_flip().
7280 */
6b95a207 7281 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7282 if (intel_crtc->unpin_work)
7283 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7284 spin_unlock_irqrestore(&dev->event_lock, flags);
7285}
7286
e7d841ca
CW		 7287inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7288{
7289 /* Ensure that the work item is consistent when activating it ... */
7290 smp_wmb();
7291 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7292 /* and that it is marked active as soon as the irq could fire. */
7293 smp_wmb();
7294}
7295
8c9f3aaf
JB		 7296static int intel_gen2_queue_flip(struct drm_device *dev,
7297 struct drm_crtc *crtc,
7298 struct drm_framebuffer *fb,
7299 struct drm_i915_gem_object *obj)
7300{
7301 struct drm_i915_private *dev_priv = dev->dev_private;
7302 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7303 u32 flip_mask;
6d90c952 7304 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7305 int ret;
7306
6d90c952 7307 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7308 if (ret)
83d4092b 7309 goto err;
8c9f3aaf 7310
6d90c952 7311 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7312 if (ret)
83d4092b 7313 goto err_unpin;
8c9f3aaf
JB		 7314
7315 /* Can't queue multiple flips, so wait for the previous
7316 * one to finish before executing the next.
7317 */
7318 if (intel_crtc->plane)
7319 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7320 else
7321 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7322 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7323 intel_ring_emit(ring, MI_NOOP);
7324 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7325 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7326 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7327 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7328 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7329
7330 intel_mark_page_flip_active(intel_crtc);
6d90c952 7331 intel_ring_advance(ring);
83d4092b
CW		 7332 return 0;
7333
7334err_unpin:
7335 intel_unpin_fb_obj(obj);
7336err:
8c9f3aaf
JB		 7337 return ret;
7338}
7339
7340static int intel_gen3_queue_flip(struct drm_device *dev,
7341 struct drm_crtc *crtc,
7342 struct drm_framebuffer *fb,
7343 struct drm_i915_gem_object *obj)
7344{
7345 struct drm_i915_private *dev_priv = dev->dev_private;
7346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7347 u32 flip_mask;
6d90c952 7348 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7349 int ret;
7350
6d90c952 7351 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7352 if (ret)
83d4092b 7353 goto err;
8c9f3aaf 7354
6d90c952 7355 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7356 if (ret)
83d4092b 7357 goto err_unpin;
8c9f3aaf
JB		 7358
7359 if (intel_crtc->plane)
7360 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7361 else
7362 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7363 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7364 intel_ring_emit(ring, MI_NOOP);
7365 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7366 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7367 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7368 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7369 intel_ring_emit(ring, MI_NOOP);
7370
e7d841ca 7371 intel_mark_page_flip_active(intel_crtc);
6d90c952 7372 intel_ring_advance(ring);
83d4092b
CW		 7373 return 0;
7374
7375err_unpin:
7376 intel_unpin_fb_obj(obj);
7377err:
8c9f3aaf
JB		 7378 return ret;
7379}
7380
7381static int intel_gen4_queue_flip(struct drm_device *dev,
7382 struct drm_crtc *crtc,
7383 struct drm_framebuffer *fb,
7384 struct drm_i915_gem_object *obj)
7385{
7386 struct drm_i915_private *dev_priv = dev->dev_private;
7387 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7388 uint32_t pf, pipesrc;
6d90c952 7389 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7390 int ret;
7391
6d90c952 7392 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7393 if (ret)
83d4092b 7394 goto err;
8c9f3aaf 7395
6d90c952 7396 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7397 if (ret)
83d4092b 7398 goto err_unpin;
8c9f3aaf
JB		 7399
7400 /* i965+ uses the linear or tiled offsets from the
7401 * Display Registers (which do not change across a page-flip)
7402 * so we need only reprogram the base address.
7403 */
6d90c952
DV		 7404 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7405 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7406 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7407 intel_ring_emit(ring,
7408 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7409 obj->tiling_mode);
8c9f3aaf
JB		 7410
7411 /* XXX Enabling the panel-fitter across page-flip is so far
7412 * untested on non-native modes, so ignore it for now.
7413 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7414 */
7415 pf = 0;
7416 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7417 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7418
7419 intel_mark_page_flip_active(intel_crtc);
6d90c952 7420 intel_ring_advance(ring);
83d4092b
CW		 7421 return 0;
7422
7423err_unpin:
7424 intel_unpin_fb_obj(obj);
7425err:
8c9f3aaf
JB		 7426 return ret;
7427}
7428
7429static int intel_gen6_queue_flip(struct drm_device *dev,
7430 struct drm_crtc *crtc,
7431 struct drm_framebuffer *fb,
7432 struct drm_i915_gem_object *obj)
7433{
7434 struct drm_i915_private *dev_priv = dev->dev_private;
7435 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7436 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7437 uint32_t pf, pipesrc;
7438 int ret;
7439
6d90c952 7440 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7441 if (ret)
83d4092b 7442 goto err;
8c9f3aaf 7443
6d90c952 7444 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7445 if (ret)
83d4092b 7446 goto err_unpin;
8c9f3aaf 7447
6d90c952
DV		 7448 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7449 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7450 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7451 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7452
dc257cf1
DV		 7453 /* Contrary to the suggestions in the documentation,
7454 * "Enable Panel Fitter" does not seem to be required when page
7455 * flipping with a non-native mode, and worse causes a normal
7456 * modeset to fail.
7457 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7458 */
7459 pf = 0;
8c9f3aaf 7460 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7461 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7462
7463 intel_mark_page_flip_active(intel_crtc);
6d90c952 7464 intel_ring_advance(ring);
83d4092b
CW		 7465 return 0;
7466
7467err_unpin:
7468 intel_unpin_fb_obj(obj);
7469err:
8c9f3aaf
JB		 7470 return ret;
7471}
7472
7c9017e5
JB		 7473/*
7474 * On gen7 we currently use the blit ring because (in early silicon at least)
7475 * the render ring doesn't give us interrpts for page flip completion, which
7476 * means clients will hang after the first flip is queued. Fortunately the
7477 * blit ring generates interrupts properly, so use it instead.
7478 */
7479static int intel_gen7_queue_flip(struct drm_device *dev,
7480 struct drm_crtc *crtc,
7481 struct drm_framebuffer *fb,
7482 struct drm_i915_gem_object *obj)
7483{
7484 struct drm_i915_private *dev_priv = dev->dev_private;
7485 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7486 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7487 uint32_t plane_bit = 0;
7c9017e5
JB		 7488 int ret;
7489
7490 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7491 if (ret)
83d4092b 7492 goto err;
7c9017e5 7493
cb05d8de
DV		 7494 switch(intel_crtc->plane) {
7495 case PLANE_A:
7496 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7497 break;
7498 case PLANE_B:
7499 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7500 break;
7501 case PLANE_C:
7502 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7503 break;
7504 default:
7505 WARN_ONCE(1, "unknown plane in flip command\n");
7506 ret = -ENODEV;
ab3951eb 7507 goto err_unpin;
cb05d8de
DV		 7508 }
7509
7c9017e5
JB		 7510 ret = intel_ring_begin(ring, 4);
7511 if (ret)
83d4092b 7512 goto err_unpin;
7c9017e5 7513
cb05d8de 7514 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7515 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7516 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7517 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7518
7519 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7520 intel_ring_advance(ring);
83d4092b
CW		 7521 return 0;
7522
7523err_unpin:
7524 intel_unpin_fb_obj(obj);
7525err:
7c9017e5
JB		 7526 return ret;
7527}
7528
8c9f3aaf
JB		 7529static int intel_default_queue_flip(struct drm_device *dev,
7530 struct drm_crtc *crtc,
7531 struct drm_framebuffer *fb,
7532 struct drm_i915_gem_object *obj)
7533{
7534 return -ENODEV;
7535}
7536
6b95a207
KH		 7537static int intel_crtc_page_flip(struct drm_crtc *crtc,
7538 struct drm_framebuffer *fb,
7539 struct drm_pending_vblank_event *event)
7540{
7541 struct drm_device *dev = crtc->dev;
7542 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7543 struct drm_framebuffer *old_fb = crtc->fb;
7544 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7545 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7546 struct intel_unpin_work *work;
8c9f3aaf 7547 unsigned long flags;
52e68630 7548 int ret;
6b95a207 7549
e6a595d2
VS		 7550 /* Can't change pixel format via MI display flips. */
7551 if (fb->pixel_format != crtc->fb->pixel_format)
7552 return -EINVAL;
7553
7554 /*
7555 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7556 * Note that pitch changes could also affect these register.
7557 */
7558 if (INTEL_INFO(dev)->gen > 3 &&
7559 (fb->offsets[0] != crtc->fb->offsets[0] ||
7560 fb->pitches[0] != crtc->fb->pitches[0]))
7561 return -EINVAL;
7562
6b95a207
KH		 7563 work = kzalloc(sizeof *work, GFP_KERNEL);
7564 if (work == NULL)
7565 return -ENOMEM;
7566
6b95a207 7567 work->event = event;
b4a98e57 7568 work->crtc = crtc;
4a35f83b 7569 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7570 INIT_WORK(&work->work, intel_unpin_work_fn);
7571
7317c75e
JB		 7572 ret = drm_vblank_get(dev, intel_crtc->pipe);
7573 if (ret)
7574 goto free_work;
7575
6b95a207
KH		 7576 /* We borrow the event spin lock for protecting unpin_work */
7577 spin_lock_irqsave(&dev->event_lock, flags);
7578 if (intel_crtc->unpin_work) {
7579 spin_unlock_irqrestore(&dev->event_lock, flags);
7580 kfree(work);
7317c75e 7581 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7582
7583 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7584 return -EBUSY;
7585 }
7586 intel_crtc->unpin_work = work;
7587 spin_unlock_irqrestore(&dev->event_lock, flags);
7588
b4a98e57
CW		 7589 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7590 flush_workqueue(dev_priv->wq);
7591
79158103
CW		 7592 ret = i915_mutex_lock_interruptible(dev);
7593 if (ret)
7594 goto cleanup;
6b95a207 7595
75dfca80 7596 /* Reference the objects for the scheduled work. */
05394f39
CW		 7597 drm_gem_object_reference(&work->old_fb_obj->base);
7598 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7599
7600 crtc->fb = fb;
96b099fd 7601
e1f99ce6 7602 work->pending_flip_obj = obj;
e1f99ce6 7603
4e5359cd
SF		 7604 work->enable_stall_check = true;
7605
b4a98e57 7606 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7607 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7608
8c9f3aaf
JB		 7609 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7610 if (ret)
7611 goto cleanup_pending;
6b95a207 7612
7782de3b 7613 intel_disable_fbc(dev);
c65355bb 7614 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 7615 mutex_unlock(&dev->struct_mutex);
7616
e5510fac
JB		 7617 trace_i915_flip_request(intel_crtc->plane, obj);
7618
6b95a207 7619 return 0;
96b099fd 7620
8c9f3aaf 7621cleanup_pending:
b4a98e57 7622 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7623 crtc->fb = old_fb;
05394f39
CW		 7624 drm_gem_object_unreference(&work->old_fb_obj->base);
7625 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7626 mutex_unlock(&dev->struct_mutex);
7627
79158103 7628cleanup:
96b099fd
CW		 7629 spin_lock_irqsave(&dev->event_lock, flags);
7630 intel_crtc->unpin_work = NULL;
7631 spin_unlock_irqrestore(&dev->event_lock, flags);
7632
7317c75e
JB		 7633 drm_vblank_put(dev, intel_crtc->pipe);
7634free_work:
96b099fd
CW		 7635 kfree(work);
7636
7637 return ret;
6b95a207
KH		 7638}
7639
f6e5b160 7640static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7641 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7642 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7643};
7644
50f56119
DV		 7645static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7646 struct drm_crtc *crtc)
7647{
7648 struct drm_device *dev;
7649 struct drm_crtc *tmp;
7650 int crtc_mask = 1;
47f1c6c9 7651
50f56119 7652 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7653
50f56119 7654 dev = crtc->dev;
47f1c6c9 7655
50f56119
DV		 7656 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7657 if (tmp == crtc)
7658 break;
7659 crtc_mask <<= 1;
7660 }
47f1c6c9 7661
50f56119
DV		 7662 if (encoder->possible_crtcs & crtc_mask)
7663 return true;
7664 return false;
47f1c6c9 7665}
79e53945 7666
9a935856
DV		 7667/**
7668 * intel_modeset_update_staged_output_state
7669 *
7670 * Updates the staged output configuration state, e.g. after we've read out the
7671 * current hw state.
7672 */
7673static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7674{
9a935856
DV		 7675 struct intel_encoder *encoder;
7676 struct intel_connector *connector;
f6e5b160 7677
9a935856
DV		 7678 list_for_each_entry(connector, &dev->mode_config.connector_list,
7679 base.head) {
7680 connector->new_encoder =
7681 to_intel_encoder(connector->base.encoder);
7682 }
f6e5b160 7683
9a935856
DV		 7684 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7685 base.head) {
7686 encoder->new_crtc =
7687 to_intel_crtc(encoder->base.crtc);
7688 }
f6e5b160
CW		 7689}
7690
9a935856
DV		 7691/**
7692 * intel_modeset_commit_output_state
7693 *
7694 * This function copies the stage display pipe configuration to the real one.
7695 */
7696static void intel_modeset_commit_output_state(struct drm_device *dev)
7697{
7698 struct intel_encoder *encoder;
7699 struct intel_connector *connector;
f6e5b160 7700
9a935856
DV		 7701 list_for_each_entry(connector, &dev->mode_config.connector_list,
7702 base.head) {
7703 connector->base.encoder = &connector->new_encoder->base;
7704 }
f6e5b160 7705
9a935856
DV		 7706 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7707 base.head) {
7708 encoder->base.crtc = &encoder->new_crtc->base;
7709 }
7710}
7711
050f7aeb
DV		 7712static void
7713connected_sink_compute_bpp(struct intel_connector * connector,
7714 struct intel_crtc_config *pipe_config)
7715{
7716 int bpp = pipe_config->pipe_bpp;
7717
7718 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7719 connector->base.base.id,
7720 drm_get_connector_name(&connector->base));
7721
7722 /* Don't use an invalid EDID bpc value */
7723 if (connector->base.display_info.bpc &&
7724 connector->base.display_info.bpc * 3 < bpp) {
7725 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7726 bpp, connector->base.display_info.bpc*3);
7727 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7728 }
7729
7730 /* Clamp bpp to 8 on screens without EDID 1.4 */
7731 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7732 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7733 bpp);
7734 pipe_config->pipe_bpp = 24;
7735 }
7736}
7737
4e53c2e0 7738static int
050f7aeb
DV		 7739compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7740 struct drm_framebuffer *fb,
7741 struct intel_crtc_config *pipe_config)
4e53c2e0 7742{
050f7aeb
DV		 7743 struct drm_device *dev = crtc->base.dev;
7744 struct intel_connector *connector;
4e53c2e0
DV		 7745 int bpp;
7746
d42264b1
DV		 7747 switch (fb->pixel_format) {
7748 case DRM_FORMAT_C8:
4e53c2e0
DV		 7749 bpp = 8*3; /* since we go through a colormap */
7750 break;
d42264b1
DV		 7751 case DRM_FORMAT_XRGB1555:
7752 case DRM_FORMAT_ARGB1555:
7753 /* checked in intel_framebuffer_init already */
7754 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7755 return -EINVAL;
7756 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7757 bpp = 6*3; /* min is 18bpp */
7758 break;
d42264b1
DV		 7759 case DRM_FORMAT_XBGR8888:
7760 case DRM_FORMAT_ABGR8888:
7761 /* checked in intel_framebuffer_init already */
7762 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7763 return -EINVAL;
7764 case DRM_FORMAT_XRGB8888:
7765 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7766 bpp = 8*3;
7767 break;
d42264b1
DV		 7768 case DRM_FORMAT_XRGB2101010:
7769 case DRM_FORMAT_ARGB2101010:
7770 case DRM_FORMAT_XBGR2101010:
7771 case DRM_FORMAT_ABGR2101010:
7772 /* checked in intel_framebuffer_init already */
7773 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7774 return -EINVAL;
4e53c2e0
DV		 7775 bpp = 10*3;
7776 break;
baba133a 7777 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7778 default:
7779 DRM_DEBUG_KMS("unsupported depth\n");
7780 return -EINVAL;
7781 }
7782
4e53c2e0
DV		 7783 pipe_config->pipe_bpp = bpp;
7784
7785 /* Clamp display bpp to EDID value */
7786 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 7787 base.head) {
1b829e05
DV		 7788 if (!connector->new_encoder ||
7789 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 7790 continue;
7791
050f7aeb 7792 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 7793 }
7794
7795 return bpp;
7796}
7797
c0b03411
DV		 7798static void intel_dump_pipe_config(struct intel_crtc *crtc,
7799 struct intel_crtc_config *pipe_config,
7800 const char *context)
7801{
7802 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7803 context, pipe_name(crtc->pipe));
7804
7805 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7806 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7807 pipe_config->pipe_bpp, pipe_config->dither);
7808 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7809 pipe_config->has_pch_encoder,
7810 pipe_config->fdi_lanes,
7811 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7812 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7813 pipe_config->fdi_m_n.tu);
7814 DRM_DEBUG_KMS("requested mode:\n");
7815 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7816 DRM_DEBUG_KMS("adjusted mode:\n");
7817 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7818 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7819 pipe_config->gmch_pfit.control,
7820 pipe_config->gmch_pfit.pgm_ratios,
7821 pipe_config->gmch_pfit.lvds_border_bits);
7822 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7823 pipe_config->pch_pfit.pos,
7824 pipe_config->pch_pfit.size);
42db64ef 7825 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 7826}
7827
accfc0c5
DV		 7828static bool check_encoder_cloning(struct drm_crtc *crtc)
7829{
7830 int num_encoders = 0;
7831 bool uncloneable_encoders = false;
7832 struct intel_encoder *encoder;
7833
7834 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7835 base.head) {
7836 if (&encoder->new_crtc->base != crtc)
7837 continue;
7838
7839 num_encoders++;
7840 if (!encoder->cloneable)
7841 uncloneable_encoders = true;
7842 }
7843
7844 return !(num_encoders > 1 && uncloneable_encoders);
7845}
7846
b8cecdf5
DV		 7847static struct intel_crtc_config *
7848intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7849 struct drm_framebuffer *fb,
b8cecdf5 7850 struct drm_display_mode *mode)
ee7b9f93 7851{
7758a113 7852 struct drm_device *dev = crtc->dev;
7758a113
DV		 7853 struct drm_encoder_helper_funcs *encoder_funcs;
7854 struct intel_encoder *encoder;
b8cecdf5 7855 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7856 int plane_bpp, ret = -EINVAL;
7857 bool retry = true;
ee7b9f93 7858
accfc0c5
DV		 7859 if (!check_encoder_cloning(crtc)) {
7860 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7861 return ERR_PTR(-EINVAL);
7862 }
7863
b8cecdf5
DV		 7864 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7865 if (!pipe_config)
7758a113
DV		 7866 return ERR_PTR(-ENOMEM);
7867
b8cecdf5
DV		 7868 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7869 drm_mode_copy(&pipe_config->requested_mode, mode);
eccb140b 7870 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
c0d43d62 7871 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 7872
050f7aeb
DV		 7873 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7874 * plane pixel format and any sink constraints into account. Returns the
7875 * source plane bpp so that dithering can be selected on mismatches
7876 * after encoders and crtc also have had their say. */
7877 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7878 fb, pipe_config);
4e53c2e0
DV		 7879 if (plane_bpp < 0)
7880 goto fail;
7881
e29c22c0 7882encoder_retry:
ef1b460d 7883 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 7884 pipe_config->port_clock = 0;
ef1b460d 7885 pipe_config->pixel_multiplier = 1;
ff9a6750 7886
7758a113
DV		 7887 /* Pass our mode to the connectors and the CRTC to give them a chance to
7888 * adjust it according to limitations or connector properties, and also
7889 * a chance to reject the mode entirely.
47f1c6c9 7890 */
7758a113
DV		 7891 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7892 base.head) {
47f1c6c9 7893
7758a113
DV		 7894 if (&encoder->new_crtc->base != crtc)
7895 continue;
7ae89233
DV		 7896
7897 if (encoder->compute_config) {
7898 if (!(encoder->compute_config(encoder, pipe_config))) {
7899 DRM_DEBUG_KMS("Encoder config failure\n");
7900 goto fail;
7901 }
7902
7903 continue;
7904 }
7905
7758a113 7906 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7907 if (!(encoder_funcs->mode_fixup(&encoder->base,
7908 &pipe_config->requested_mode,
7909 &pipe_config->adjusted_mode))) {
7758a113
DV		 7910 DRM_DEBUG_KMS("Encoder fixup failed\n");
7911 goto fail;
7912 }
ee7b9f93 7913 }
47f1c6c9 7914
ff9a6750
DV		 7915 /* Set default port clock if not overwritten by the encoder. Needs to be
7916 * done afterwards in case the encoder adjusts the mode. */
7917 if (!pipe_config->port_clock)
7918 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7919
a43f6e0f 7920 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 7921 if (ret < 0) {
7758a113
DV		 7922 DRM_DEBUG_KMS("CRTC fixup failed\n");
7923 goto fail;
ee7b9f93 7924 }
e29c22c0
DV		 7925
7926 if (ret == RETRY) {
7927 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7928 ret = -EINVAL;
7929 goto fail;
7930 }
7931
7932 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7933 retry = false;
7934 goto encoder_retry;
7935 }
7936
4e53c2e0
DV		 7937 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7938 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7939 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7940
b8cecdf5 7941 return pipe_config;
7758a113 7942fail:
b8cecdf5 7943 kfree(pipe_config);
e29c22c0 7944 return ERR_PTR(ret);
ee7b9f93 7945}
47f1c6c9 7946
e2e1ed41
DV		 7947/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7948 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7949static void
7950intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7951 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7952{
7953 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7954 struct drm_device *dev = crtc->dev;
7955 struct intel_encoder *encoder;
7956 struct intel_connector *connector;
7957 struct drm_crtc *tmp_crtc;
79e53945 7958
e2e1ed41 7959 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7960
e2e1ed41
DV		 7961 /* Check which crtcs have changed outputs connected to them, these need
7962 * to be part of the prepare_pipes mask. We don't (yet) support global
7963 * modeset across multiple crtcs, so modeset_pipes will only have one
7964 * bit set at most. */
7965 list_for_each_entry(connector, &dev->mode_config.connector_list,
7966 base.head) {
7967 if (connector->base.encoder == &connector->new_encoder->base)
7968 continue;
79e53945 7969
e2e1ed41
DV		 7970 if (connector->base.encoder) {
7971 tmp_crtc = connector->base.encoder->crtc;
7972
7973 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7974 }
7975
7976 if (connector->new_encoder)
7977 *prepare_pipes |=
7978 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7979 }
7980
e2e1ed41
DV		 7981 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7982 base.head) {
7983 if (encoder->base.crtc == &encoder->new_crtc->base)
7984 continue;
7985
7986 if (encoder->base.crtc) {
7987 tmp_crtc = encoder->base.crtc;
7988
7989 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7990 }
7991
7992 if (encoder->new_crtc)
7993 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7994 }
7995
e2e1ed41
DV		 7996 /* Check for any pipes that will be fully disabled ... */
7997 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7998 base.head) {
7999 bool used = false;
22fd0fab 8000
e2e1ed41
DV		 8001 /* Don't try to disable disabled crtcs. */
8002 if (!intel_crtc->base.enabled)
8003 continue;
7e7d76c3 8004
e2e1ed41
DV		 8005 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8006 base.head) {
8007 if (encoder->new_crtc == intel_crtc)
8008 used = true;
8009 }
8010
8011 if (!used)
8012 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8013 }
8014
e2e1ed41
DV		 8015
8016 /* set_mode is also used to update properties on life display pipes. */
8017 intel_crtc = to_intel_crtc(crtc);
8018 if (crtc->enabled)
8019 *prepare_pipes |= 1 << intel_crtc->pipe;
8020
b6c5164d
DV		 8021 /*
8022 * For simplicity do a full modeset on any pipe where the output routing
8023 * changed. We could be more clever, but that would require us to be
8024 * more careful with calling the relevant encoder->mode_set functions.
8025 */
e2e1ed41
DV		 8026 if (*prepare_pipes)
8027 *modeset_pipes = *prepare_pipes;
8028
8029 /* ... and mask these out. */
8030 *modeset_pipes &= ~(*disable_pipes);
8031 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8032
8033 /*
8034 * HACK: We don't (yet) fully support global modesets. intel_set_config
8035 * obies this rule, but the modeset restore mode of
8036 * intel_modeset_setup_hw_state does not.
8037 */
8038 *modeset_pipes &= 1 << intel_crtc->pipe;
8039 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8040
8041 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8042 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8043}
79e53945 8044
ea9d758d 8045static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8046{
ea9d758d 8047 struct drm_encoder *encoder;
f6e5b160 8048 struct drm_device *dev = crtc->dev;
f6e5b160 8049
ea9d758d
DV		 8050 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8051 if (encoder->crtc == crtc)
8052 return true;
8053
8054 return false;
8055}
8056
8057static void
8058intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8059{
8060 struct intel_encoder *intel_encoder;
8061 struct intel_crtc *intel_crtc;
8062 struct drm_connector *connector;
8063
8064 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8065 base.head) {
8066 if (!intel_encoder->base.crtc)
8067 continue;
8068
8069 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8070
8071 if (prepare_pipes & (1 << intel_crtc->pipe))
8072 intel_encoder->connectors_active = false;
8073 }
8074
8075 intel_modeset_commit_output_state(dev);
8076
8077 /* Update computed state. */
8078 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8079 base.head) {
8080 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8081 }
8082
8083 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8084 if (!connector->encoder || !connector->encoder->crtc)
8085 continue;
8086
8087 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8088
8089 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8090 struct drm_property *dpms_property =
8091 dev->mode_config.dpms_property;
8092
ea9d758d 8093 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8094 drm_object_property_set_value(&connector->base,
68d34720
DV		 8095 dpms_property,
8096 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8097
8098 intel_encoder = to_intel_encoder(connector->encoder);
8099 intel_encoder->connectors_active = true;
8100 }
8101 }
8102
8103}
8104
f1f644dc
JB		 8105static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8106 struct intel_crtc_config *new)
8107{
8108 int clock1, clock2, diff;
8109
8110 clock1 = cur->adjusted_mode.clock;
8111 clock2 = new->adjusted_mode.clock;
8112
8113 if (clock1 == clock2)
8114 return true;
8115
8116 if (!clock1 || !clock2)
8117 return false;
8118
8119 diff = abs(clock1 - clock2);
8120
8121 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8122 return true;
8123
8124 return false;
8125}
8126
25c5b266
DV		 8127#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8128 list_for_each_entry((intel_crtc), \
8129 &(dev)->mode_config.crtc_list, \
8130 base.head) \
0973f18f 8131 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8132
0e8ffe1b 8133static bool
2fa2fe9a
DV		 8134intel_pipe_config_compare(struct drm_device *dev,
8135 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8136 struct intel_crtc_config *pipe_config)
8137{
66e985c0
DV		 8138#define PIPE_CONF_CHECK_X(name) \
8139 if (current_config->name != pipe_config->name) { \
8140 DRM_ERROR("mismatch in " #name " " \
8141 "(expected 0x%08x, found 0x%08x)\n", \
8142 current_config->name, \
8143 pipe_config->name); \
8144 return false; \
8145 }
8146
08a24034
DV		 8147#define PIPE_CONF_CHECK_I(name) \
8148 if (current_config->name != pipe_config->name) { \
8149 DRM_ERROR("mismatch in " #name " " \
8150 "(expected %i, found %i)\n", \
8151 current_config->name, \
8152 pipe_config->name); \
8153 return false; \
88adfff1
DV		 8154 }
8155
1bd1bd80
DV		 8156#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8157 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8158 DRM_ERROR("mismatch in " #name " " \
8159 "(expected %i, found %i)\n", \
8160 current_config->name & (mask), \
8161 pipe_config->name & (mask)); \
8162 return false; \
8163 }
8164
bb760063
DV		 8165#define PIPE_CONF_QUIRK(quirk) \
8166 ((current_config->quirks | pipe_config->quirks) & (quirk))
8167
eccb140b
DV		 8168 PIPE_CONF_CHECK_I(cpu_transcoder);
8169
08a24034
DV		 8170 PIPE_CONF_CHECK_I(has_pch_encoder);
8171 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8172 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8173 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8174 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8175 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8176 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8177
1bd1bd80
DV		 8178 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8179 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8180 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8181 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8182 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8183 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8184
8185 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8186 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8187 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8188 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8189 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8190 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8191
c93f54cf 8192 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8193
1bd1bd80
DV		 8194 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8195 DRM_MODE_FLAG_INTERLACE);
8196
bb760063
DV		 8197 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8198 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8199 DRM_MODE_FLAG_PHSYNC);
8200 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8201 DRM_MODE_FLAG_NHSYNC);
8202 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8203 DRM_MODE_FLAG_PVSYNC);
8204 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8205 DRM_MODE_FLAG_NVSYNC);
8206 }
045ac3b5 8207
1bd1bd80
DV		 8208 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8209 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8210
2fa2fe9a
DV		 8211 PIPE_CONF_CHECK_I(gmch_pfit.control);
8212 /* pfit ratios are autocomputed by the hw on gen4+ */
8213 if (INTEL_INFO(dev)->gen < 4)
8214 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8215 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8216 PIPE_CONF_CHECK_I(pch_pfit.pos);
8217 PIPE_CONF_CHECK_I(pch_pfit.size);
8218
42db64ef
PZ		 8219 PIPE_CONF_CHECK_I(ips_enabled);
8220
c0d43d62 8221 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8222 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8223 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8224 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8225 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8226
66e985c0 8227#undef PIPE_CONF_CHECK_X
08a24034 8228#undef PIPE_CONF_CHECK_I
1bd1bd80 8229#undef PIPE_CONF_CHECK_FLAGS
bb760063 8230#undef PIPE_CONF_QUIRK
88adfff1 8231
f1f644dc
JB		 8232 if (!IS_HASWELL(dev)) {
8233 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
8234 DRM_ERROR("mismatch in clock (expected %d, found %d\n",
8235 current_config->adjusted_mode.clock,
8236 pipe_config->adjusted_mode.clock);
8237 return false;
8238 }
8239 }
8240
0e8ffe1b
DV		 8241 return true;
8242}
8243
91d1b4bd
DV		 8244static void
8245check_connector_state(struct drm_device *dev)
8af6cf88 8246{
8af6cf88
DV		 8247 struct intel_connector *connector;
8248
8249 list_for_each_entry(connector, &dev->mode_config.connector_list,
8250 base.head) {
8251 /* This also checks the encoder/connector hw state with the
8252 * ->get_hw_state callbacks. */
8253 intel_connector_check_state(connector);
8254
8255 WARN(&connector->new_encoder->base != connector->base.encoder,
8256 "connector's staged encoder doesn't match current encoder\n");
8257 }
91d1b4bd
DV		 8258}
8259
8260static void
8261check_encoder_state(struct drm_device *dev)
8262{
8263 struct intel_encoder *encoder;
8264 struct intel_connector *connector;
8af6cf88
DV		 8265
8266 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8267 base.head) {
8268 bool enabled = false;
8269 bool active = false;
8270 enum pipe pipe, tracked_pipe;
8271
8272 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8273 encoder->base.base.id,
8274 drm_get_encoder_name(&encoder->base));
8275
8276 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8277 "encoder's stage crtc doesn't match current crtc\n");
8278 WARN(encoder->connectors_active && !encoder->base.crtc,
8279 "encoder's active_connectors set, but no crtc\n");
8280
8281 list_for_each_entry(connector, &dev->mode_config.connector_list,
8282 base.head) {
8283 if (connector->base.encoder != &encoder->base)
8284 continue;
8285 enabled = true;
8286 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8287 active = true;
8288 }
8289 WARN(!!encoder->base.crtc != enabled,
8290 "encoder's enabled state mismatch "
8291 "(expected %i, found %i)\n",
8292 !!encoder->base.crtc, enabled);
8293 WARN(active && !encoder->base.crtc,
8294 "active encoder with no crtc\n");
8295
8296 WARN(encoder->connectors_active != active,
8297 "encoder's computed active state doesn't match tracked active state "
8298 "(expected %i, found %i)\n", active, encoder->connectors_active);
8299
8300 active = encoder->get_hw_state(encoder, &pipe);
8301 WARN(active != encoder->connectors_active,
8302 "encoder's hw state doesn't match sw tracking "
8303 "(expected %i, found %i)\n",
8304 encoder->connectors_active, active);
8305
8306 if (!encoder->base.crtc)
8307 continue;
8308
8309 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8310 WARN(active && pipe != tracked_pipe,
8311 "active encoder's pipe doesn't match"
8312 "(expected %i, found %i)\n",
8313 tracked_pipe, pipe);
8314
8315 }
91d1b4bd
DV		 8316}
8317
8318static void
8319check_crtc_state(struct drm_device *dev)
8320{
8321 drm_i915_private_t *dev_priv = dev->dev_private;
8322 struct intel_crtc *crtc;
8323 struct intel_encoder *encoder;
8324 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8325
8326 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8327 base.head) {
8328 bool enabled = false;
8329 bool active = false;
8330
045ac3b5
JB		 8331 memset(&pipe_config, 0, sizeof(pipe_config));
8332
8af6cf88
DV		 8333 DRM_DEBUG_KMS("[CRTC:%d]\n",
8334 crtc->base.base.id);
8335
8336 WARN(crtc->active && !crtc->base.enabled,
8337 "active crtc, but not enabled in sw tracking\n");
8338
8339 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8340 base.head) {
8341 if (encoder->base.crtc != &crtc->base)
8342 continue;
8343 enabled = true;
8344 if (encoder->connectors_active)
8345 active = true;
8346 }
6c49f241 8347
8af6cf88
DV		 8348 WARN(active != crtc->active,
8349 "crtc's computed active state doesn't match tracked active state "
8350 "(expected %i, found %i)\n", active, crtc->active);
8351 WARN(enabled != crtc->base.enabled,
8352 "crtc's computed enabled state doesn't match tracked enabled state "
8353 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8354
0e8ffe1b
DV		 8355 active = dev_priv->display.get_pipe_config(crtc,
8356 &pipe_config);
d62cf62a
DV		 8357
8358 /* hw state is inconsistent with the pipe A quirk */
8359 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8360 active = crtc->active;
8361
6c49f241
DV		 8362 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8363 base.head) {
8364 if (encoder->base.crtc != &crtc->base)
8365 continue;
f1f644dc
JB		 8366 if (encoder->get_config &&
8367 dev_priv->display.get_clock) {
6c49f241 8368 encoder->get_config(encoder, &pipe_config);
f1f644dc
JB		 8369 dev_priv->display.get_clock(crtc,
8370 &pipe_config);
8371 }
6c49f241
DV		 8372 }
8373
0e8ffe1b
DV		 8374 WARN(crtc->active != active,
8375 "crtc active state doesn't match with hw state "
8376 "(expected %i, found %i)\n", crtc->active, active);
8377
c0b03411
DV		 8378 if (active &&
8379 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8380 WARN(1, "pipe state doesn't match!\n");
8381 intel_dump_pipe_config(crtc, &pipe_config,
8382 "[hw state]");
8383 intel_dump_pipe_config(crtc, &crtc->config,
8384 "[sw state]");
8385 }
8af6cf88
DV		 8386 }
8387}
8388
91d1b4bd
DV		 8389static void
8390check_shared_dpll_state(struct drm_device *dev)
8391{
8392 drm_i915_private_t *dev_priv = dev->dev_private;
8393 struct intel_crtc *crtc;
8394 struct intel_dpll_hw_state dpll_hw_state;
8395 int i;
5358901f
DV		 8396
8397 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8398 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8399 int enabled_crtcs = 0, active_crtcs = 0;
8400 bool active;
8401
8402 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8403
8404 DRM_DEBUG_KMS("%s\n", pll->name);
8405
8406 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8407
8408 WARN(pll->active > pll->refcount,
8409 "more active pll users than references: %i vs %i\n",
8410 pll->active, pll->refcount);
8411 WARN(pll->active && !pll->on,
8412 "pll in active use but not on in sw tracking\n");
8413 WARN(pll->on != active,
8414 "pll on state mismatch (expected %i, found %i)\n",
8415 pll->on, active);
8416
8417 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8418 base.head) {
8419 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8420 enabled_crtcs++;
8421 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8422 active_crtcs++;
8423 }
8424 WARN(pll->active != active_crtcs,
8425 "pll active crtcs mismatch (expected %i, found %i)\n",
8426 pll->active, active_crtcs);
8427 WARN(pll->refcount != enabled_crtcs,
8428 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8429 pll->refcount, enabled_crtcs);
66e985c0
DV		 8430
8431 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8432 sizeof(dpll_hw_state)),
8433 "pll hw state mismatch\n");
5358901f 8434 }
8af6cf88
DV		 8435}
8436
91d1b4bd
DV		 8437void
8438intel_modeset_check_state(struct drm_device *dev)
8439{
8440 check_connector_state(dev);
8441 check_encoder_state(dev);
8442 check_crtc_state(dev);
8443 check_shared_dpll_state(dev);
8444}
8445
f30da187
DV		 8446static int __intel_set_mode(struct drm_crtc *crtc,
8447 struct drm_display_mode *mode,
8448 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8449{
8450 struct drm_device *dev = crtc->dev;
dbf2b54e 8451 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8452 struct drm_display_mode *saved_mode, *saved_hwmode;
8453 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8454 struct intel_crtc *intel_crtc;
8455 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8456 int ret = 0;
a6778b3c 8457
3ac18232 8458 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8459 if (!saved_mode)
8460 return -ENOMEM;
3ac18232 8461 saved_hwmode = saved_mode + 1;
a6778b3c 8462
e2e1ed41 8463 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8464 &prepare_pipes, &disable_pipes);
8465
3ac18232
TG		 8466 *saved_hwmode = crtc->hwmode;
8467 *saved_mode = crtc->mode;
a6778b3c 8468
25c5b266
DV		 8469 /* Hack: Because we don't (yet) support global modeset on multiple
8470 * crtcs, we don't keep track of the new mode for more than one crtc.
8471 * Hence simply check whether any bit is set in modeset_pipes in all the
8472 * pieces of code that are not yet converted to deal with mutliple crtcs
8473 * changing their mode at the same time. */
25c5b266 8474 if (modeset_pipes) {
4e53c2e0 8475 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8476 if (IS_ERR(pipe_config)) {
8477 ret = PTR_ERR(pipe_config);
8478 pipe_config = NULL;
8479
3ac18232 8480 goto out;
25c5b266 8481 }
c0b03411
DV		 8482 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8483 "[modeset]");
25c5b266 8484 }
a6778b3c 8485
460da916
DV		 8486 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8487 intel_crtc_disable(&intel_crtc->base);
8488
ea9d758d
DV		 8489 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8490 if (intel_crtc->base.enabled)
8491 dev_priv->display.crtc_disable(&intel_crtc->base);
8492 }
a6778b3c 8493
6c4c86f5
DV		 8494 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8495 * to set it here already despite that we pass it down the callchain.
f6e5b160 8496 */
b8cecdf5 8497 if (modeset_pipes) {
25c5b266 8498 crtc->mode = *mode;
b8cecdf5
DV		 8499 /* mode_set/enable/disable functions rely on a correct pipe
8500 * config. */
8501 to_intel_crtc(crtc)->config = *pipe_config;
8502 }
7758a113 8503
ea9d758d
DV		 8504 /* Only after disabling all output pipelines that will be changed can we
8505 * update the the output configuration. */
8506 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8507
47fab737
DV		 8508 if (dev_priv->display.modeset_global_resources)
8509 dev_priv->display.modeset_global_resources(dev);
8510
a6778b3c
DV		 8511 /* Set up the DPLL and any encoders state that needs to adjust or depend
8512 * on the DPLL.
f6e5b160 8513 */
25c5b266 8514 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8515 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8516 x, y, fb);
8517 if (ret)
8518 goto done;
a6778b3c
DV		 8519 }
8520
8521 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8522 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8523 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8524
25c5b266
DV		 8525 if (modeset_pipes) {
8526 /* Store real post-adjustment hardware mode. */
b8cecdf5 8527 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8528
25c5b266
DV		 8529 /* Calculate and store various constants which
8530 * are later needed by vblank and swap-completion
8531 * timestamping. They are derived from true hwmode.
8532 */
8533 drm_calc_timestamping_constants(crtc);
8534 }
a6778b3c
DV		 8535
8536 /* FIXME: add subpixel order */
8537done:
c0c36b94 8538 if (ret && crtc->enabled) {
3ac18232
TG		 8539 crtc->hwmode = *saved_hwmode;
8540 crtc->mode = *saved_mode;
a6778b3c
DV		 8541 }
8542
3ac18232 8543out:
b8cecdf5 8544 kfree(pipe_config);
3ac18232 8545 kfree(saved_mode);
a6778b3c 8546 return ret;
f6e5b160
CW		 8547}
8548
f30da187
DV		 8549int intel_set_mode(struct drm_crtc *crtc,
8550 struct drm_display_mode *mode,
8551 int x, int y, struct drm_framebuffer *fb)
8552{
8553 int ret;
8554
8555 ret = __intel_set_mode(crtc, mode, x, y, fb);
8556
8557 if (ret == 0)
8558 intel_modeset_check_state(crtc->dev);
8559
8560 return ret;
8561}
8562
c0c36b94
CW		 8563void intel_crtc_restore_mode(struct drm_crtc *crtc)
8564{
8565 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8566}
8567
25c5b266
DV		 8568#undef for_each_intel_crtc_masked
8569
d9e55608
DV		 8570static void intel_set_config_free(struct intel_set_config *config)
8571{
8572 if (!config)
8573 return;
8574
1aa4b628
DV		 8575 kfree(config->save_connector_encoders);
8576 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8577 kfree(config);
8578}
8579
85f9eb71
DV		 8580static int intel_set_config_save_state(struct drm_device *dev,
8581 struct intel_set_config *config)
8582{
85f9eb71
DV		 8583 struct drm_encoder *encoder;
8584 struct drm_connector *connector;
8585 int count;
8586
1aa4b628
DV		 8587 config->save_encoder_crtcs =
8588 kcalloc(dev->mode_config.num_encoder,
8589 sizeof(struct drm_crtc *), GFP_KERNEL);
8590 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8591 return -ENOMEM;
8592
1aa4b628
DV		 8593 config->save_connector_encoders =
8594 kcalloc(dev->mode_config.num_connector,
8595 sizeof(struct drm_encoder *), GFP_KERNEL);
8596 if (!config->save_connector_encoders)
85f9eb71
DV		 8597 return -ENOMEM;
8598
8599 /* Copy data. Note that driver private data is not affected.
8600 * Should anything bad happen only the expected state is
8601 * restored, not the drivers personal bookkeeping.
8602 */
85f9eb71
DV		 8603 count = 0;
8604 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8605 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8606 }
8607
8608 count = 0;
8609 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8610 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8611 }
8612
8613 return 0;
8614}
8615
8616static void intel_set_config_restore_state(struct drm_device *dev,
8617 struct intel_set_config *config)
8618{
9a935856
DV		 8619 struct intel_encoder *encoder;
8620 struct intel_connector *connector;
85f9eb71
DV		 8621 int count;
8622
85f9eb71 8623 count = 0;
9a935856
DV		 8624 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8625 encoder->new_crtc =
8626 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8627 }
8628
8629 count = 0;
9a935856
DV		 8630 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8631 connector->new_encoder =
8632 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8633 }
8634}
8635
e3de42b6
ID		 8636static bool
8637is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
8638 int num_connectors)
8639{
8640 int i;
8641
8642 for (i = 0; i < num_connectors; i++)
8643 if (connectors[i].encoder &&
8644 connectors[i].encoder->crtc == crtc &&
8645 connectors[i].dpms != DRM_MODE_DPMS_ON)
8646 return true;
8647
8648 return false;
8649}
8650
5e2b584e
DV		 8651static void
8652intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8653 struct intel_set_config *config)
8654{
8655
8656 /* We should be able to check here if the fb has the same properties
8657 * and then just flip_or_move it */
e3de42b6
ID		 8658 if (set->connectors != NULL &&
8659 is_crtc_connector_off(set->crtc, *set->connectors,
8660 set->num_connectors)) {
8661 config->mode_changed = true;
8662 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 8663 /* If we have no fb then treat it as a full mode set */
8664 if (set->crtc->fb == NULL) {
8665 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8666 config->mode_changed = true;
8667 } else if (set->fb == NULL) {
8668 config->mode_changed = true;
72f4901e
DV		 8669 } else if (set->fb->pixel_format !=
8670 set->crtc->fb->pixel_format) {
5e2b584e 8671 config->mode_changed = true;
e3de42b6 8672 } else {
5e2b584e 8673 config->fb_changed = true;
e3de42b6 8674 }
5e2b584e
DV		 8675 }
8676
835c5873 8677 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8678 config->fb_changed = true;
8679
8680 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8681 DRM_DEBUG_KMS("modes are different, full mode set\n");
8682 drm_mode_debug_printmodeline(&set->crtc->mode);
8683 drm_mode_debug_printmodeline(set->mode);
8684 config->mode_changed = true;
8685 }
8686}
8687
2e431051 8688static int
9a935856
DV		 8689intel_modeset_stage_output_state(struct drm_device *dev,
8690 struct drm_mode_set *set,
8691 struct intel_set_config *config)
50f56119 8692{
85f9eb71 8693 struct drm_crtc *new_crtc;
9a935856
DV		 8694 struct intel_connector *connector;
8695 struct intel_encoder *encoder;
2e431051 8696 int count, ro;
50f56119 8697
9abdda74 8698 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8699 * of connectors. For paranoia, double-check this. */
8700 WARN_ON(!set->fb && (set->num_connectors != 0));
8701 WARN_ON(set->fb && (set->num_connectors == 0));
8702
50f56119 8703 count = 0;
9a935856
DV		 8704 list_for_each_entry(connector, &dev->mode_config.connector_list,
8705 base.head) {
8706 /* Otherwise traverse passed in connector list and get encoders
8707 * for them. */
50f56119 8708 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8709 if (set->connectors[ro] == &connector->base) {
8710 connector->new_encoder = connector->encoder;
50f56119
DV		 8711 break;
8712 }
8713 }
8714
9a935856
DV		 8715 /* If we disable the crtc, disable all its connectors. Also, if
8716 * the connector is on the changing crtc but not on the new
8717 * connector list, disable it. */
8718 if ((!set->fb || ro == set->num_connectors) &&
8719 connector->base.encoder &&
8720 connector->base.encoder->crtc == set->crtc) {
8721 connector->new_encoder = NULL;
8722
8723 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8724 connector->base.base.id,
8725 drm_get_connector_name(&connector->base));
8726 }
8727
8728
8729 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8730 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8731 config->mode_changed = true;
50f56119
DV		 8732 }
8733 }
9a935856 8734 /* connector->new_encoder is now updated for all connectors. */
50f56119 8735
9a935856 8736 /* Update crtc of enabled connectors. */
50f56119 8737 count = 0;
9a935856
DV		 8738 list_for_each_entry(connector, &dev->mode_config.connector_list,
8739 base.head) {
8740 if (!connector->new_encoder)
50f56119
DV		 8741 continue;
8742
9a935856 8743 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8744
8745 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8746 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8747 new_crtc = set->crtc;
8748 }
8749
8750 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8751 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8752 new_crtc)) {
5e2b584e 8753 return -EINVAL;
50f56119 8754 }
9a935856
DV		 8755 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8756
8757 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8758 connector->base.base.id,
8759 drm_get_connector_name(&connector->base),
8760 new_crtc->base.id);
8761 }
8762
8763 /* Check for any encoders that needs to be disabled. */
8764 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8765 base.head) {
8766 list_for_each_entry(connector,
8767 &dev->mode_config.connector_list,
8768 base.head) {
8769 if (connector->new_encoder == encoder) {
8770 WARN_ON(!connector->new_encoder->new_crtc);
8771
8772 goto next_encoder;
8773 }
8774 }
8775 encoder->new_crtc = NULL;
8776next_encoder:
8777 /* Only now check for crtc changes so we don't miss encoders
8778 * that will be disabled. */
8779 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8780 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8781 config->mode_changed = true;
50f56119
DV		 8782 }
8783 }
9a935856 8784 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8785
2e431051
DV		 8786 return 0;
8787}
8788
8789static int intel_crtc_set_config(struct drm_mode_set *set)
8790{
8791 struct drm_device *dev;
2e431051
DV		 8792 struct drm_mode_set save_set;
8793 struct intel_set_config *config;
8794 int ret;
2e431051 8795
8d3e375e
DV		 8796 BUG_ON(!set);
8797 BUG_ON(!set->crtc);
8798 BUG_ON(!set->crtc->helper_private);
2e431051 8799
7e53f3a4
DV		 8800 /* Enforce sane interface api - has been abused by the fb helper. */
8801 BUG_ON(!set->mode && set->fb);
8802 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8803
2e431051
DV		 8804 if (set->fb) {
8805 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8806 set->crtc->base.id, set->fb->base.id,
8807 (int)set->num_connectors, set->x, set->y);
8808 } else {
8809 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8810 }
8811
8812 dev = set->crtc->dev;
8813
8814 ret = -ENOMEM;
8815 config = kzalloc(sizeof(*config), GFP_KERNEL);
8816 if (!config)
8817 goto out_config;
8818
8819 ret = intel_set_config_save_state(dev, config);
8820 if (ret)
8821 goto out_config;
8822
8823 save_set.crtc = set->crtc;
8824 save_set.mode = &set->crtc->mode;
8825 save_set.x = set->crtc->x;
8826 save_set.y = set->crtc->y;
8827 save_set.fb = set->crtc->fb;
8828
8829 /* Compute whether we need a full modeset, only an fb base update or no
8830 * change at all. In the future we might also check whether only the
8831 * mode changed, e.g. for LVDS where we only change the panel fitter in
8832 * such cases. */
8833 intel_set_config_compute_mode_changes(set, config);
8834
9a935856 8835 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8836 if (ret)
8837 goto fail;
8838
5e2b584e 8839 if (config->mode_changed) {
c0c36b94
CW		 8840 ret = intel_set_mode(set->crtc, set->mode,
8841 set->x, set->y, set->fb);
5e2b584e 8842 } else if (config->fb_changed) {
4878cae2
VS		 8843 intel_crtc_wait_for_pending_flips(set->crtc);
8844
4f660f49 8845 ret = intel_pipe_set_base(set->crtc,
94352cf9 8846 set->x, set->y, set->fb);
50f56119
DV		 8847 }
8848
2d05eae1 8849 if (ret) {
bf67dfeb
DV		 8850 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8851 set->crtc->base.id, ret);
50f56119 8852fail:
2d05eae1 8853 intel_set_config_restore_state(dev, config);
50f56119 8854
2d05eae1
CW		 8855 /* Try to restore the config */
8856 if (config->mode_changed &&
8857 intel_set_mode(save_set.crtc, save_set.mode,
8858 save_set.x, save_set.y, save_set.fb))
8859 DRM_ERROR("failed to restore config after modeset failure\n");
8860 }
50f56119 8861
d9e55608
DV		 8862out_config:
8863 intel_set_config_free(config);
50f56119
DV		 8864 return ret;
8865}
f6e5b160
CW		 8866
8867static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8868 .cursor_set = intel_crtc_cursor_set,
8869 .cursor_move = intel_crtc_cursor_move,
8870 .gamma_set = intel_crtc_gamma_set,
50f56119 8871 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8872 .destroy = intel_crtc_destroy,
8873 .page_flip = intel_crtc_page_flip,
8874};
8875
79f689aa
PZ		 8876static void intel_cpu_pll_init(struct drm_device *dev)
8877{
affa9354 8878 if (HAS_DDI(dev))
79f689aa
PZ		 8879 intel_ddi_pll_init(dev);
8880}
8881
5358901f
DV		 8882static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8883 struct intel_shared_dpll *pll,
8884 struct intel_dpll_hw_state *hw_state)
ee7b9f93 8885{
5358901f 8886 uint32_t val;
ee7b9f93 8887
5358901f 8888 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 8889 hw_state->dpll = val;
8890 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8891 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 8892
8893 return val & DPLL_VCO_ENABLE;
8894}
8895
15bdd4cf
DV		 8896static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
8897 struct intel_shared_dpll *pll)
8898{
8899 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
8900 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
8901}
8902
e7b903d2
DV		 8903static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8904 struct intel_shared_dpll *pll)
8905{
e7b903d2
DV		 8906 /* PCH refclock must be enabled first */
8907 assert_pch_refclk_enabled(dev_priv);
8908
15bdd4cf
DV		 8909 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8910
8911 /* Wait for the clocks to stabilize. */
8912 POSTING_READ(PCH_DPLL(pll->id));
8913 udelay(150);
8914
8915 /* The pixel multiplier can only be updated once the
8916 * DPLL is enabled and the clocks are stable.
8917 *
8918 * So write it again.
8919 */
8920 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8921 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 8922 udelay(200);
8923}
8924
8925static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8926 struct intel_shared_dpll *pll)
8927{
8928 struct drm_device *dev = dev_priv->dev;
8929 struct intel_crtc *crtc;
e7b903d2
DV		 8930
8931 /* Make sure no transcoder isn't still depending on us. */
8932 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8933 if (intel_crtc_to_shared_dpll(crtc) == pll)
8934 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 8935 }
8936
15bdd4cf
DV		 8937 I915_WRITE(PCH_DPLL(pll->id), 0);
8938 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 8939 udelay(200);
8940}
8941
46edb027
DV		 8942static char *ibx_pch_dpll_names[] = {
8943 "PCH DPLL A",
8944 "PCH DPLL B",
8945};
8946
7c74ade1 8947static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 8948{
e7b903d2 8949 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 8950 int i;
8951
7c74ade1 8952 dev_priv->num_shared_dpll = 2;
ee7b9f93 8953
e72f9fbf 8954 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 8955 dev_priv->shared_dplls[i].id = i;
8956 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 8957 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 8958 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
8959 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 8960 dev_priv->shared_dplls[i].get_hw_state =
8961 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 8962 }
8963}
8964
7c74ade1
DV		 8965static void intel_shared_dpll_init(struct drm_device *dev)
8966{
e7b903d2 8967 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 8968
8969 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8970 ibx_pch_dpll_init(dev);
8971 else
8972 dev_priv->num_shared_dpll = 0;
8973
8974 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
8975 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
8976 dev_priv->num_shared_dpll);
8977}
8978
b358d0a6 8979static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8980{
22fd0fab 8981 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8982 struct intel_crtc *intel_crtc;
8983 int i;
8984
8985 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8986 if (intel_crtc == NULL)
8987 return;
8988
8989 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8990
8991 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8992 for (i = 0; i < 256; i++) {
8993 intel_crtc->lut_r[i] = i;
8994 intel_crtc->lut_g[i] = i;
8995 intel_crtc->lut_b[i] = i;
8996 }
8997
80824003
JB		 8998 /* Swap pipes & planes for FBC on pre-965 */
8999 intel_crtc->pipe = pipe;
9000 intel_crtc->plane = pipe;
e2e767ab 9001 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9002 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9003 intel_crtc->plane = !pipe;
80824003
JB		 9004 }
9005
22fd0fab
JB		 9006 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9007 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9008 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9009 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9010
79e53945 9011 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9012}
9013
08d7b3d1 9014int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9015 struct drm_file *file)
08d7b3d1 9016{
08d7b3d1 9017 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9018 struct drm_mode_object *drmmode_obj;
9019 struct intel_crtc *crtc;
08d7b3d1 9020
1cff8f6b
DV		 9021 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9022 return -ENODEV;
08d7b3d1 9023
c05422d5
DV		 9024 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9025 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9026
c05422d5 9027 if (!drmmode_obj) {
08d7b3d1
CW		 9028 DRM_ERROR("no such CRTC id\n");
9029 return -EINVAL;
9030 }
9031
c05422d5
DV		 9032 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9033 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9034
c05422d5 9035 return 0;
08d7b3d1
CW		 9036}
9037
66a9278e 9038static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9039{
66a9278e
DV		 9040 struct drm_device *dev = encoder->base.dev;
9041 struct intel_encoder *source_encoder;
79e53945 9042 int index_mask = 0;
79e53945
JB		 9043 int entry = 0;
9044
66a9278e
DV		 9045 list_for_each_entry(source_encoder,
9046 &dev->mode_config.encoder_list, base.head) {
9047
9048 if (encoder == source_encoder)
79e53945 9049 index_mask |= (1 << entry);
66a9278e
DV		 9050
9051 /* Intel hw has only one MUX where enocoders could be cloned. */
9052 if (encoder->cloneable && source_encoder->cloneable)
9053 index_mask |= (1 << entry);
9054
79e53945
JB		 9055 entry++;
9056 }
4ef69c7a 9057
79e53945
JB		 9058 return index_mask;
9059}
9060
4d302442
CW		 9061static bool has_edp_a(struct drm_device *dev)
9062{
9063 struct drm_i915_private *dev_priv = dev->dev_private;
9064
9065 if (!IS_MOBILE(dev))
9066 return false;
9067
9068 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9069 return false;
9070
9071 if (IS_GEN5(dev) &&
9072 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9073 return false;
9074
9075 return true;
9076}
9077
79e53945
JB		 9078static void intel_setup_outputs(struct drm_device *dev)
9079{
725e30ad 9080 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9081 struct intel_encoder *encoder;
cb0953d7 9082 bool dpd_is_edp = false;
79e53945 9083
c9093354 9084 intel_lvds_init(dev);
79e53945 9085
c40c0f5b 9086 if (!IS_ULT(dev))
79935fca 9087 intel_crt_init(dev);
cb0953d7 9088
affa9354 9089 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9090 int found;
9091
9092 /* Haswell uses DDI functions to detect digital outputs */
9093 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9094 /* DDI A only supports eDP */
9095 if (found)
9096 intel_ddi_init(dev, PORT_A);
9097
9098 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9099 * register */
9100 found = I915_READ(SFUSE_STRAP);
9101
9102 if (found & SFUSE_STRAP_DDIB_DETECTED)
9103 intel_ddi_init(dev, PORT_B);
9104 if (found & SFUSE_STRAP_DDIC_DETECTED)
9105 intel_ddi_init(dev, PORT_C);
9106 if (found & SFUSE_STRAP_DDID_DETECTED)
9107 intel_ddi_init(dev, PORT_D);
9108 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9109 int found;
270b3042
DV		 9110 dpd_is_edp = intel_dpd_is_edp(dev);
9111
9112 if (has_edp_a(dev))
9113 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9114
dc0fa718 9115 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9116 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9117 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9118 if (!found)
e2debe91 9119 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9120 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9121 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9122 }
9123
dc0fa718 9124 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9125 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9126
dc0fa718 9127 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9128 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9129
5eb08b69 9130 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9131 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9132
270b3042 9133 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9134 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9135 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9136 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 9137 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9138 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 9139
dc0fa718 9140 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9141 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9142 PORT_B);
67cfc203
VS		 9143 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9144 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9145 }
103a196f 9146 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9147 bool found = false;
7d57382e 9148
e2debe91 9149 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9150 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9151 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9152 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9153 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9154 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9155 }
27185ae1 9156
e7281eab 9157 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9158 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9159 }
13520b05
KH		 9160
9161 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9162
e2debe91 9163 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9164 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9165 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9166 }
27185ae1 9167
e2debe91 9168 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9169
b01f2c3a
JB		 9170 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9171 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9172 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9173 }
e7281eab 9174 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9175 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9176 }
27185ae1 9177
b01f2c3a 9178 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9179 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9180 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9181 } else if (IS_GEN2(dev))
79e53945
JB		 9182 intel_dvo_init(dev);
9183
103a196f 9184 if (SUPPORTS_TV(dev))
79e53945
JB		 9185 intel_tv_init(dev);
9186
4ef69c7a
CW		 9187 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9188 encoder->base.possible_crtcs = encoder->crtc_mask;
9189 encoder->base.possible_clones =
66a9278e 9190 intel_encoder_clones(encoder);
79e53945 9191 }
47356eb6 9192
dde86e2d 9193 intel_init_pch_refclk(dev);
270b3042
DV		 9194
9195 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9196}
9197
9198static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9199{
9200 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 9201
9202 drm_framebuffer_cleanup(fb);
05394f39 9203 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 9204
9205 kfree(intel_fb);
9206}
9207
9208static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9209 struct drm_file *file,
79e53945
JB		 9210 unsigned int *handle)
9211{
9212 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9213 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9214
05394f39 9215 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9216}
9217
9218static const struct drm_framebuffer_funcs intel_fb_funcs = {
9219 .destroy = intel_user_framebuffer_destroy,
9220 .create_handle = intel_user_framebuffer_create_handle,
9221};
9222
38651674
DA		 9223int intel_framebuffer_init(struct drm_device *dev,
9224 struct intel_framebuffer *intel_fb,
308e5bcb 9225 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9226 struct drm_i915_gem_object *obj)
79e53945 9227{
a35cdaa0 9228 int pitch_limit;
79e53945
JB		 9229 int ret;
9230
c16ed4be
CW		 9231 if (obj->tiling_mode == I915_TILING_Y) {
9232 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9233 return -EINVAL;
c16ed4be 9234 }
57cd6508 9235
c16ed4be
CW		 9236 if (mode_cmd->pitches[0] & 63) {
9237 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9238 mode_cmd->pitches[0]);
57cd6508 9239 return -EINVAL;
c16ed4be 9240 }
57cd6508 9241
a35cdaa0
CW		 9242 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9243 pitch_limit = 32*1024;
9244 } else if (INTEL_INFO(dev)->gen >= 4) {
9245 if (obj->tiling_mode)
9246 pitch_limit = 16*1024;
9247 else
9248 pitch_limit = 32*1024;
9249 } else if (INTEL_INFO(dev)->gen >= 3) {
9250 if (obj->tiling_mode)
9251 pitch_limit = 8*1024;
9252 else
9253 pitch_limit = 16*1024;
9254 } else
9255 /* XXX DSPC is limited to 4k tiled */
9256 pitch_limit = 8*1024;
9257
9258 if (mode_cmd->pitches[0] > pitch_limit) {
9259 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9260 obj->tiling_mode ? "tiled" : "linear",
9261 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9262 return -EINVAL;
c16ed4be 9263 }
5d7bd705
VS		 9264
9265 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9266 mode_cmd->pitches[0] != obj->stride) {
9267 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9268 mode_cmd->pitches[0], obj->stride);
5d7bd705 9269 return -EINVAL;
c16ed4be 9270 }
5d7bd705 9271
57779d06 9272 /* Reject formats not supported by any plane early. */
308e5bcb 9273 switch (mode_cmd->pixel_format) {
57779d06 9274 case DRM_FORMAT_C8:
04b3924d
VS		 9275 case DRM_FORMAT_RGB565:
9276 case DRM_FORMAT_XRGB8888:
9277 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9278 break;
9279 case DRM_FORMAT_XRGB1555:
9280 case DRM_FORMAT_ARGB1555:
c16ed4be 9281 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9282 DRM_DEBUG("unsupported pixel format: %s\n",
9283 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9284 return -EINVAL;
c16ed4be 9285 }
57779d06
VS		 9286 break;
9287 case DRM_FORMAT_XBGR8888:
9288 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9289 case DRM_FORMAT_XRGB2101010:
9290 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9291 case DRM_FORMAT_XBGR2101010:
9292 case DRM_FORMAT_ABGR2101010:
c16ed4be 9293 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9294 DRM_DEBUG("unsupported pixel format: %s\n",
9295 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9296 return -EINVAL;
c16ed4be 9297 }
b5626747 9298 break;
04b3924d
VS		 9299 case DRM_FORMAT_YUYV:
9300 case DRM_FORMAT_UYVY:
9301 case DRM_FORMAT_YVYU:
9302 case DRM_FORMAT_VYUY:
c16ed4be 9303 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9304 DRM_DEBUG("unsupported pixel format: %s\n",
9305 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9306 return -EINVAL;
c16ed4be 9307 }
57cd6508
CW		 9308 break;
9309 default:
4ee62c76
VS		 9310 DRM_DEBUG("unsupported pixel format: %s\n",
9311 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9312 return -EINVAL;
9313 }
9314
90f9a336
VS		 9315 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9316 if (mode_cmd->offsets[0] != 0)
9317 return -EINVAL;
9318
c7d73f6a
DV		 9319 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9320 intel_fb->obj = obj;
9321
79e53945
JB		 9322 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9323 if (ret) {
9324 DRM_ERROR("framebuffer init failed %d\n", ret);
9325 return ret;
9326 }
9327
79e53945
JB		 9328 return 0;
9329}
9330
79e53945
JB		 9331static struct drm_framebuffer *
9332intel_user_framebuffer_create(struct drm_device *dev,
9333 struct drm_file *filp,
308e5bcb 9334 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9335{
05394f39 9336 struct drm_i915_gem_object *obj;
79e53945 9337
308e5bcb
JB		 9338 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9339 mode_cmd->handles[0]));
c8725226 9340 if (&obj->base == NULL)
cce13ff7 9341 return ERR_PTR(-ENOENT);
79e53945 9342
d2dff872 9343 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9344}
9345
79e53945 9346static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9347 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9348 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9349};
9350
e70236a8
JB		 9351/* Set up chip specific display functions */
9352static void intel_init_display(struct drm_device *dev)
9353{
9354 struct drm_i915_private *dev_priv = dev->dev_private;
9355
ee9300bb
DV		 9356 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9357 dev_priv->display.find_dpll = g4x_find_best_dpll;
9358 else if (IS_VALLEYVIEW(dev))
9359 dev_priv->display.find_dpll = vlv_find_best_dpll;
9360 else if (IS_PINEVIEW(dev))
9361 dev_priv->display.find_dpll = pnv_find_best_dpll;
9362 else
9363 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9364
affa9354 9365 if (HAS_DDI(dev)) {
0e8ffe1b 9366 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9367 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9368 dev_priv->display.crtc_enable = haswell_crtc_enable;
9369 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9370 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9371 dev_priv->display.update_plane = ironlake_update_plane;
9372 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9373 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f1f644dc 9374 dev_priv->display.get_clock = ironlake_crtc_clock_get;
f564048e 9375 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9376 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9377 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9378 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9379 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9380 } else if (IS_VALLEYVIEW(dev)) {
9381 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9382 dev_priv->display.get_clock = i9xx_crtc_clock_get;
89b667f8
JB		 9383 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9384 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9385 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9386 dev_priv->display.off = i9xx_crtc_off;
9387 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9388 } else {
0e8ffe1b 9389 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9390 dev_priv->display.get_clock = i9xx_crtc_clock_get;
f564048e 9391 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9392 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9393 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9394 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9395 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9396 }
e70236a8 9397
e70236a8 9398 /* Returns the core display clock speed */
25eb05fc
JB		 9399 if (IS_VALLEYVIEW(dev))
9400 dev_priv->display.get_display_clock_speed =
9401 valleyview_get_display_clock_speed;
9402 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9403 dev_priv->display.get_display_clock_speed =
9404 i945_get_display_clock_speed;
9405 else if (IS_I915G(dev))
9406 dev_priv->display.get_display_clock_speed =
9407 i915_get_display_clock_speed;
f2b115e6 9408 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9409 dev_priv->display.get_display_clock_speed =
9410 i9xx_misc_get_display_clock_speed;
9411 else if (IS_I915GM(dev))
9412 dev_priv->display.get_display_clock_speed =
9413 i915gm_get_display_clock_speed;
9414 else if (IS_I865G(dev))
9415 dev_priv->display.get_display_clock_speed =
9416 i865_get_display_clock_speed;
f0f8a9ce 9417 else if (IS_I85X(dev))
e70236a8
JB		 9418 dev_priv->display.get_display_clock_speed =
9419 i855_get_display_clock_speed;
9420 else /* 852, 830 */
9421 dev_priv->display.get_display_clock_speed =
9422 i830_get_display_clock_speed;
9423
7f8a8569 9424 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9425 if (IS_GEN5(dev)) {
674cf967 9426 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9427 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9428 } else if (IS_GEN6(dev)) {
674cf967 9429 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9430 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9431 } else if (IS_IVYBRIDGE(dev)) {
9432 /* FIXME: detect B0+ stepping and use auto training */
9433 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9434 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9435 dev_priv->display.modeset_global_resources =
9436 ivb_modeset_global_resources;
c82e4d26
ED		 9437 } else if (IS_HASWELL(dev)) {
9438 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9439 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9440 dev_priv->display.modeset_global_resources =
9441 haswell_modeset_global_resources;
a0e63c22 9442 }
6067aaea 9443 } else if (IS_G4X(dev)) {
e0dac65e 9444 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9445 }
8c9f3aaf
JB		 9446
9447 /* Default just returns -ENODEV to indicate unsupported */
9448 dev_priv->display.queue_flip = intel_default_queue_flip;
9449
9450 switch (INTEL_INFO(dev)->gen) {
9451 case 2:
9452 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9453 break;
9454
9455 case 3:
9456 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9457 break;
9458
9459 case 4:
9460 case 5:
9461 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9462 break;
9463
9464 case 6:
9465 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9466 break;
7c9017e5
JB		 9467 case 7:
9468 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9469 break;
8c9f3aaf 9470 }
e70236a8
JB		 9471}
9472
b690e96c
JB		 9473/*
9474 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9475 * resume, or other times. This quirk makes sure that's the case for
9476 * affected systems.
9477 */
0206e353 9478static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9479{
9480 struct drm_i915_private *dev_priv = dev->dev_private;
9481
9482 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9483 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9484}
9485
435793df
KP		 9486/*
9487 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9488 */
9489static void quirk_ssc_force_disable(struct drm_device *dev)
9490{
9491 struct drm_i915_private *dev_priv = dev->dev_private;
9492 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9493 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9494}
9495
4dca20ef 9496/*
5a15ab5b
CE		 9497 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9498 * brightness value
4dca20ef
CE		 9499 */
9500static void quirk_invert_brightness(struct drm_device *dev)
9501{
9502 struct drm_i915_private *dev_priv = dev->dev_private;
9503 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9504 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9505}
9506
b690e96c
JB		 9507struct intel_quirk {
9508 int device;
9509 int subsystem_vendor;
9510 int subsystem_device;
9511 void (*hook)(struct drm_device *dev);
9512};
9513
5f85f176
EE		 9514/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9515struct intel_dmi_quirk {
9516 void (*hook)(struct drm_device *dev);
9517 const struct dmi_system_id (*dmi_id_list)[];
9518};
9519
9520static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9521{
9522 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9523 return 1;
9524}
9525
9526static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9527 {
9528 .dmi_id_list = &(const struct dmi_system_id[]) {
9529 {
9530 .callback = intel_dmi_reverse_brightness,
9531 .ident = "NCR Corporation",
9532 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9533 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9534 },
9535 },
9536 { } /* terminating entry */
9537 },
9538 .hook = quirk_invert_brightness,
9539 },
9540};
9541
c43b5634 9542static struct intel_quirk intel_quirks[] = {
b690e96c 9543 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9544 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9545
b690e96c
JB		 9546 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9547 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9548
b690e96c
JB		 9549 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9550 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9551
ccd0d36e 9552 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9553 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9554 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9555
9556 /* Lenovo U160 cannot use SSC on LVDS */
9557 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9558
9559 /* Sony Vaio Y cannot use SSC on LVDS */
9560 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9561
9562 /* Acer Aspire 5734Z must invert backlight brightness */
9563 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9564
9565 /* Acer/eMachines G725 */
9566 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9567
9568 /* Acer/eMachines e725 */
9569 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9570
9571 /* Acer/Packard Bell NCL20 */
9572 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9573
9574 /* Acer Aspire 4736Z */
9575 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9576};
9577
9578static void intel_init_quirks(struct drm_device *dev)
9579{
9580 struct pci_dev *d = dev->pdev;
9581 int i;
9582
9583 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9584 struct intel_quirk *q = &intel_quirks[i];
9585
9586 if (d->device == q->device &&
9587 (d->subsystem_vendor == q->subsystem_vendor ||
9588 q->subsystem_vendor == PCI_ANY_ID) &&
9589 (d->subsystem_device == q->subsystem_device ||
9590 q->subsystem_device == PCI_ANY_ID))
9591 q->hook(dev);
9592 }
5f85f176
EE		 9593 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9594 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9595 intel_dmi_quirks[i].hook(dev);
9596 }
b690e96c
JB		 9597}
9598
9cce37f4
JB		 9599/* Disable the VGA plane that we never use */
9600static void i915_disable_vga(struct drm_device *dev)
9601{
9602 struct drm_i915_private *dev_priv = dev->dev_private;
9603 u8 sr1;
766aa1c4 9604 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9605
9606 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9607 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9608 sr1 = inb(VGA_SR_DATA);
9609 outb(sr1 | 1<<5, VGA_SR_DATA);
9610 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9611 udelay(300);
9612
9613 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9614 POSTING_READ(vga_reg);
9615}
9616
f817586c
DV		 9617void intel_modeset_init_hw(struct drm_device *dev)
9618{
fa42e23c 9619 intel_init_power_well(dev);
0232e927 9620
a8f78b58
ED		 9621 intel_prepare_ddi(dev);
9622
f817586c
DV		 9623 intel_init_clock_gating(dev);
9624
79f5b2c7 9625 mutex_lock(&dev->struct_mutex);
8090c6b9 9626 intel_enable_gt_powersave(dev);
79f5b2c7 9627 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9628}
9629
7d708ee4
ID		 9630void intel_modeset_suspend_hw(struct drm_device *dev)
9631{
9632 intel_suspend_hw(dev);
9633}
9634
79e53945
JB		 9635void intel_modeset_init(struct drm_device *dev)
9636{
652c393a 9637 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9638 int i, j, ret;
79e53945
JB		 9639
9640 drm_mode_config_init(dev);
9641
9642 dev->mode_config.min_width = 0;
9643 dev->mode_config.min_height = 0;
9644
019d96cb
DA		 9645 dev->mode_config.preferred_depth = 24;
9646 dev->mode_config.prefer_shadow = 1;
9647
e6ecefaa 9648 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9649
b690e96c
JB		 9650 intel_init_quirks(dev);
9651
1fa61106
ED		 9652 intel_init_pm(dev);
9653
e3c74757
BW		 9654 if (INTEL_INFO(dev)->num_pipes == 0)
9655 return;
9656
e70236a8
JB		 9657 intel_init_display(dev);
9658
a6c45cf0
CW		 9659 if (IS_GEN2(dev)) {
9660 dev->mode_config.max_width = 2048;
9661 dev->mode_config.max_height = 2048;
9662 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9663 dev->mode_config.max_width = 4096;
9664 dev->mode_config.max_height = 4096;
79e53945 9665 } else {
a6c45cf0
CW		 9666 dev->mode_config.max_width = 8192;
9667 dev->mode_config.max_height = 8192;
79e53945 9668 }
5d4545ae 9669 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9670
28c97730 9671 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9672 INTEL_INFO(dev)->num_pipes,
9673 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9674
7eb552ae 9675 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9676 intel_crtc_init(dev, i);
7f1f3851
JB		 9677 for (j = 0; j < dev_priv->num_plane; j++) {
9678 ret = intel_plane_init(dev, i, j);
9679 if (ret)
06da8da2
VS		 9680 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9681 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9682 }
79e53945
JB		 9683 }
9684
79f689aa 9685 intel_cpu_pll_init(dev);
e72f9fbf 9686 intel_shared_dpll_init(dev);
ee7b9f93 9687
9cce37f4
JB		 9688 /* Just disable it once at startup */
9689 i915_disable_vga(dev);
79e53945 9690 intel_setup_outputs(dev);
11be49eb
CW		 9691
9692 /* Just in case the BIOS is doing something questionable. */
9693 intel_disable_fbc(dev);
2c7111db
CW		 9694}
9695
24929352
DV		 9696static void
9697intel_connector_break_all_links(struct intel_connector *connector)
9698{
9699 connector->base.dpms = DRM_MODE_DPMS_OFF;
9700 connector->base.encoder = NULL;
9701 connector->encoder->connectors_active = false;
9702 connector->encoder->base.crtc = NULL;
9703}
9704
7fad798e
DV		 9705static void intel_enable_pipe_a(struct drm_device *dev)
9706{
9707 struct intel_connector *connector;
9708 struct drm_connector *crt = NULL;
9709 struct intel_load_detect_pipe load_detect_temp;
9710
9711 /* We can't just switch on the pipe A, we need to set things up with a
9712 * proper mode and output configuration. As a gross hack, enable pipe A
9713 * by enabling the load detect pipe once. */
9714 list_for_each_entry(connector,
9715 &dev->mode_config.connector_list,
9716 base.head) {
9717 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9718 crt = &connector->base;
9719 break;
9720 }
9721 }
9722
9723 if (!crt)
9724 return;
9725
9726 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9727 intel_release_load_detect_pipe(crt, &load_detect_temp);
9728
652c393a 9729
7fad798e
DV		 9730}
9731
fa555837
DV		 9732static bool
9733intel_check_plane_mapping(struct intel_crtc *crtc)
9734{
7eb552ae
BW		 9735 struct drm_device *dev = crtc->base.dev;
9736 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9737 u32 reg, val;
9738
7eb552ae 9739 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9740 return true;
9741
9742 reg = DSPCNTR(!crtc->plane);
9743 val = I915_READ(reg);
9744
9745 if ((val & DISPLAY_PLANE_ENABLE) &&
9746 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9747 return false;
9748
9749 return true;
9750}
9751
24929352
DV		 9752static void intel_sanitize_crtc(struct intel_crtc *crtc)
9753{
9754 struct drm_device *dev = crtc->base.dev;
9755 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9756 u32 reg;
24929352 9757
24929352 9758 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9759 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9760 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9761
9762 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9763 * disable the crtc (and hence change the state) if it is wrong. Note
9764 * that gen4+ has a fixed plane -> pipe mapping. */
9765 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9766 struct intel_connector *connector;
9767 bool plane;
9768
24929352
DV		 9769 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9770 crtc->base.base.id);
9771
9772 /* Pipe has the wrong plane attached and the plane is active.
9773 * Temporarily change the plane mapping and disable everything
9774 * ... */
9775 plane = crtc->plane;
9776 crtc->plane = !plane;
9777 dev_priv->display.crtc_disable(&crtc->base);
9778 crtc->plane = plane;
9779
9780 /* ... and break all links. */
9781 list_for_each_entry(connector, &dev->mode_config.connector_list,
9782 base.head) {
9783 if (connector->encoder->base.crtc != &crtc->base)
9784 continue;
9785
9786 intel_connector_break_all_links(connector);
9787 }
9788
9789 WARN_ON(crtc->active);
9790 crtc->base.enabled = false;
9791 }
24929352 9792
7fad798e
DV		 9793 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9794 crtc->pipe == PIPE_A && !crtc->active) {
9795 /* BIOS forgot to enable pipe A, this mostly happens after
9796 * resume. Force-enable the pipe to fix this, the update_dpms
9797 * call below we restore the pipe to the right state, but leave
9798 * the required bits on. */
9799 intel_enable_pipe_a(dev);
9800 }
9801
24929352
DV		 9802 /* Adjust the state of the output pipe according to whether we
9803 * have active connectors/encoders. */
9804 intel_crtc_update_dpms(&crtc->base);
9805
9806 if (crtc->active != crtc->base.enabled) {
9807 struct intel_encoder *encoder;
9808
9809 /* This can happen either due to bugs in the get_hw_state
9810 * functions or because the pipe is force-enabled due to the
9811 * pipe A quirk. */
9812 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9813 crtc->base.base.id,
9814 crtc->base.enabled ? "enabled" : "disabled",
9815 crtc->active ? "enabled" : "disabled");
9816
9817 crtc->base.enabled = crtc->active;
9818
9819 /* Because we only establish the connector -> encoder ->
9820 * crtc links if something is active, this means the
9821 * crtc is now deactivated. Break the links. connector
9822 * -> encoder links are only establish when things are
9823 * actually up, hence no need to break them. */
9824 WARN_ON(crtc->active);
9825
9826 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9827 WARN_ON(encoder->connectors_active);
9828 encoder->base.crtc = NULL;
9829 }
9830 }
9831}
9832
9833static void intel_sanitize_encoder(struct intel_encoder *encoder)
9834{
9835 struct intel_connector *connector;
9836 struct drm_device *dev = encoder->base.dev;
9837
9838 /* We need to check both for a crtc link (meaning that the
9839 * encoder is active and trying to read from a pipe) and the
9840 * pipe itself being active. */
9841 bool has_active_crtc = encoder->base.crtc &&
9842 to_intel_crtc(encoder->base.crtc)->active;
9843
9844 if (encoder->connectors_active && !has_active_crtc) {
9845 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9846 encoder->base.base.id,
9847 drm_get_encoder_name(&encoder->base));
9848
9849 /* Connector is active, but has no active pipe. This is
9850 * fallout from our resume register restoring. Disable
9851 * the encoder manually again. */
9852 if (encoder->base.crtc) {
9853 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9854 encoder->base.base.id,
9855 drm_get_encoder_name(&encoder->base));
9856 encoder->disable(encoder);
9857 }
9858
9859 /* Inconsistent output/port/pipe state happens presumably due to
9860 * a bug in one of the get_hw_state functions. Or someplace else
9861 * in our code, like the register restore mess on resume. Clamp
9862 * things to off as a safer default. */
9863 list_for_each_entry(connector,
9864 &dev->mode_config.connector_list,
9865 base.head) {
9866 if (connector->encoder != encoder)
9867 continue;
9868
9869 intel_connector_break_all_links(connector);
9870 }
9871 }
9872 /* Enabled encoders without active connectors will be fixed in
9873 * the crtc fixup. */
9874}
9875
44cec740 9876void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9877{
9878 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9879 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9880
9881 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9882 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9883 i915_disable_vga(dev);
0fde901f
KM		 9884 }
9885}
9886
30e984df 9887static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 9888{
9889 struct drm_i915_private *dev_priv = dev->dev_private;
9890 enum pipe pipe;
24929352
DV		 9891 struct intel_crtc *crtc;
9892 struct intel_encoder *encoder;
9893 struct intel_connector *connector;
5358901f 9894 int i;
24929352 9895
0e8ffe1b
DV		 9896 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9897 base.head) {
88adfff1 9898 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 9899
0e8ffe1b
DV		 9900 crtc->active = dev_priv->display.get_pipe_config(crtc,
9901 &crtc->config);
24929352
DV		 9902
9903 crtc->base.enabled = crtc->active;
9904
9905 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9906 crtc->base.base.id,
9907 crtc->active ? "enabled" : "disabled");
9908 }
9909
5358901f 9910 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 9911 if (HAS_DDI(dev))
6441ab5f
PZ		 9912 intel_ddi_setup_hw_pll_state(dev);
9913
5358901f
DV		 9914 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9915 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9916
9917 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9918 pll->active = 0;
9919 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9920 base.head) {
9921 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9922 pll->active++;
9923 }
9924 pll->refcount = pll->active;
9925
9926 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9927 pll->name, pll->refcount);
9928 }
9929
24929352
DV		 9930 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9931 base.head) {
9932 pipe = 0;
9933
9934 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 9935 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9936 encoder->base.crtc = &crtc->base;
f1f644dc
JB		 9937 if (encoder->get_config &&
9938 dev_priv->display.get_clock) {
045ac3b5 9939 encoder->get_config(encoder, &crtc->config);
f1f644dc
JB		 9940 dev_priv->display.get_clock(crtc,
9941 &crtc->config);
9942 }
24929352
DV		 9943 } else {
9944 encoder->base.crtc = NULL;
9945 }
9946
9947 encoder->connectors_active = false;
9948 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9949 encoder->base.base.id,
9950 drm_get_encoder_name(&encoder->base),
9951 encoder->base.crtc ? "enabled" : "disabled",
9952 pipe);
9953 }
9954
9955 list_for_each_entry(connector, &dev->mode_config.connector_list,
9956 base.head) {
9957 if (connector->get_hw_state(connector)) {
9958 connector->base.dpms = DRM_MODE_DPMS_ON;
9959 connector->encoder->connectors_active = true;
9960 connector->base.encoder = &connector->encoder->base;
9961 } else {
9962 connector->base.dpms = DRM_MODE_DPMS_OFF;
9963 connector->base.encoder = NULL;
9964 }
9965 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9966 connector->base.base.id,
9967 drm_get_connector_name(&connector->base),
9968 connector->base.encoder ? "enabled" : "disabled");
9969 }
30e984df
DV		 9970}
9971
9972/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9973 * and i915 state tracking structures. */
9974void intel_modeset_setup_hw_state(struct drm_device *dev,
9975 bool force_restore)
9976{
9977 struct drm_i915_private *dev_priv = dev->dev_private;
9978 enum pipe pipe;
9979 struct drm_plane *plane;
9980 struct intel_crtc *crtc;
9981 struct intel_encoder *encoder;
9982
9983 intel_modeset_readout_hw_state(dev);
24929352 9984
babea61d
JB		 9985 /*
9986 * Now that we have the config, copy it to each CRTC struct
9987 * Note that this could go away if we move to using crtc_config
9988 * checking everywhere.
9989 */
9990 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9991 base.head) {
9992 if (crtc->active && i915_fastboot) {
9993 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
9994
9995 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
9996 crtc->base.base.id);
9997 drm_mode_debug_printmodeline(&crtc->base.mode);
9998 }
9999 }
10000
24929352
DV		 10001 /* HW state is read out, now we need to sanitize this mess. */
10002 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10003 base.head) {
10004 intel_sanitize_encoder(encoder);
10005 }
10006
10007 for_each_pipe(pipe) {
10008 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10009 intel_sanitize_crtc(crtc);
c0b03411 10010 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10011 }
9a935856 10012
45e2b5f6 10013 if (force_restore) {
f30da187
DV		 10014 /*
10015 * We need to use raw interfaces for restoring state to avoid
10016 * checking (bogus) intermediate states.
10017 */
45e2b5f6 10018 for_each_pipe(pipe) {
b5644d05
JB		 10019 struct drm_crtc *crtc =
10020 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10021
10022 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10023 crtc->fb);
45e2b5f6 10024 }
b5644d05
JB		 10025 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10026 intel_plane_restore(plane);
0fde901f
KM		 10027
10028 i915_redisable_vga(dev);
45e2b5f6
DV		 10029 } else {
10030 intel_modeset_update_staged_output_state(dev);
10031 }
8af6cf88
DV		 10032
10033 intel_modeset_check_state(dev);
2e938892
DV		 10034
10035 drm_mode_config_reset(dev);
2c7111db
CW		 10036}
10037
10038void intel_modeset_gem_init(struct drm_device *dev)
10039{
1833b134 10040 intel_modeset_init_hw(dev);
02e792fb
DV		 10041
10042 intel_setup_overlay(dev);
24929352 10043
45e2b5f6 10044 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10045}
10046
10047void intel_modeset_cleanup(struct drm_device *dev)
10048{
652c393a
JB		 10049 struct drm_i915_private *dev_priv = dev->dev_private;
10050 struct drm_crtc *crtc;
10051 struct intel_crtc *intel_crtc;
10052
fd0c0642
DV		 10053 /*
10054 * Interrupts and polling as the first thing to avoid creating havoc.
10055 * Too much stuff here (turning of rps, connectors, ...) would
10056 * experience fancy races otherwise.
10057 */
10058 drm_irq_uninstall(dev);
10059 cancel_work_sync(&dev_priv->hotplug_work);
10060 /*
10061 * Due to the hpd irq storm handling the hotplug work can re-arm the
10062 * poll handlers. Hence disable polling after hpd handling is shut down.
10063 */
f87ea761 10064 drm_kms_helper_poll_fini(dev);
fd0c0642 10065
652c393a
JB		 10066 mutex_lock(&dev->struct_mutex);
10067
723bfd70
JB		 10068 intel_unregister_dsm_handler();
10069
652c393a
JB		 10070 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10071 /* Skip inactive CRTCs */
10072 if (!crtc->fb)
10073 continue;
10074
10075 intel_crtc = to_intel_crtc(crtc);
3dec0095 10076 intel_increase_pllclock(crtc);
652c393a
JB		 10077 }
10078
973d04f9 10079 intel_disable_fbc(dev);
e70236a8 10080
8090c6b9 10081 intel_disable_gt_powersave(dev);
0cdab21f 10082
930ebb46
DV		 10083 ironlake_teardown_rc6(dev);
10084
69341a5e
KH		 10085 mutex_unlock(&dev->struct_mutex);
10086
1630fe75
CW		 10087 /* flush any delayed tasks or pending work */
10088 flush_scheduled_work();
10089
dc652f90
JN		 10090 /* destroy backlight, if any, before the connectors */
10091 intel_panel_destroy_backlight(dev);
10092
79e53945 10093 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10094
10095 intel_cleanup_overlay(dev);
79e53945
JB		 10096}
10097
f1c79df3
ZW		 10098/*
10099 * Return which encoder is currently attached for connector.
10100 */
df0e9248 10101struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10102{
df0e9248
CW		 10103 return &intel_attached_encoder(connector)->base;
10104}
f1c79df3 10105
df0e9248
CW		 10106void intel_connector_attach_encoder(struct intel_connector *connector,
10107 struct intel_encoder *encoder)
10108{
10109 connector->encoder = encoder;
10110 drm_mode_connector_attach_encoder(&connector->base,
10111 &encoder->base);
79e53945 10112}
28d52043
DA		 10113
10114/*
10115 * set vga decode state - true == enable VGA decode
10116 */
10117int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10118{
10119 struct drm_i915_private *dev_priv = dev->dev_private;
10120 u16 gmch_ctrl;
10121
10122 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10123 if (state)
10124 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10125 else
10126 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10127 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10128 return 0;
10129}
c4a1d9e4
CW		 10130
10131#ifdef CONFIG_DEBUG_FS
10132#include <linux/seq_file.h>
10133
10134struct intel_display_error_state {
ff57f1b0
PZ		 10135
10136 u32 power_well_driver;
10137
c4a1d9e4
CW		 10138 struct intel_cursor_error_state {
10139 u32 control;
10140 u32 position;
10141 u32 base;
10142 u32 size;
52331309 10143 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10144
10145 struct intel_pipe_error_state {
ff57f1b0 10146 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 10147 u32 conf;
10148 u32 source;
10149
10150 u32 htotal;
10151 u32 hblank;
10152 u32 hsync;
10153 u32 vtotal;
10154 u32 vblank;
10155 u32 vsync;
52331309 10156 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10157
10158 struct intel_plane_error_state {
10159 u32 control;
10160 u32 stride;
10161 u32 size;
10162 u32 pos;
10163 u32 addr;
10164 u32 surface;
10165 u32 tile_offset;
52331309 10166 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 10167};
10168
10169struct intel_display_error_state *
10170intel_display_capture_error_state(struct drm_device *dev)
10171{
0206e353 10172 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10173 struct intel_display_error_state *error;
702e7a56 10174 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 10175 int i;
10176
10177 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10178 if (error == NULL)
10179 return NULL;
10180
ff57f1b0
PZ		 10181 if (HAS_POWER_WELL(dev))
10182 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10183
52331309 10184 for_each_pipe(i) {
702e7a56 10185 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 10186 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 10187
a18c4c3d
PZ		 10188 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10189 error->cursor[i].control = I915_READ(CURCNTR(i));
10190 error->cursor[i].position = I915_READ(CURPOS(i));
10191 error->cursor[i].base = I915_READ(CURBASE(i));
10192 } else {
10193 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10194 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10195 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10196 }
c4a1d9e4
CW		 10197
10198 error->plane[i].control = I915_READ(DSPCNTR(i));
10199 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10200 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10201 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10202 error->plane[i].pos = I915_READ(DSPPOS(i));
10203 }
ca291363
PZ		 10204 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10205 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10206 if (INTEL_INFO(dev)->gen >= 4) {
10207 error->plane[i].surface = I915_READ(DSPSURF(i));
10208 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10209 }
10210
702e7a56 10211 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 10212 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 10213 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10214 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10215 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10216 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10217 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10218 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10219 }
10220
12d217c7
PZ		 10221 /* In the code above we read the registers without checking if the power
10222 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10223 * prevent the next I915_WRITE from detecting it and printing an error
10224 * message. */
10225 if (HAS_POWER_WELL(dev))
10226 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10227
c4a1d9e4
CW		 10228 return error;
10229}
10230
edc3d884
MK		 10231#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10232
c4a1d9e4 10233void
edc3d884 10234intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10235 struct drm_device *dev,
10236 struct intel_display_error_state *error)
10237{
10238 int i;
10239
edc3d884 10240 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10241 if (HAS_POWER_WELL(dev))
edc3d884 10242 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10243 error->power_well_driver);
52331309 10244 for_each_pipe(i) {
edc3d884
MK		 10245 err_printf(m, "Pipe [%d]:\n", i);
10246 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 10247 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 10248 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
10249 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10250 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
10251 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
10252 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
10253 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
10254 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
10255 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
10256
10257 err_printf(m, "Plane [%d]:\n", i);
10258 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10259 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10260 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10261 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10262 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10263 }
4b71a570 10264 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10265 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10266 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10267 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10268 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10269 }
10270
edc3d884
MK		 10271 err_printf(m, "Cursor [%d]:\n", i);
10272 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10273 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10274 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 10275 }
10276}
10277#endif
Linux kernel - Deliverables
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