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drm/i915: don't enable PM_VEBOX_CS_ERROR_INTERRUPT
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
f1f644dc
JB		 48static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
49 struct intel_crtc_config *pipe_config);
50static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
51 struct intel_crtc_config *pipe_config);
52
79e53945 53typedef struct {
0206e353 54 int min, max;
79e53945
JB		 55} intel_range_t;
56
57typedef struct {
0206e353
AJ		 58 int dot_limit;
59 int p2_slow, p2_fast;
79e53945
JB		 60} intel_p2_t;
61
62#define INTEL_P2_NUM 2
d4906093
ML		 63typedef struct intel_limit intel_limit_t;
64struct intel_limit {
0206e353
AJ		 65 intel_range_t dot, vco, n, m, m1, m2, p, p1;
66 intel_p2_t p2;
d4906093 67};
79e53945 68
2377b741
JB		 69/* FDI */
70#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
71
d2acd215
DV		 72int
73intel_pch_rawclk(struct drm_device *dev)
74{
75 struct drm_i915_private *dev_priv = dev->dev_private;
76
77 WARN_ON(!HAS_PCH_SPLIT(dev));
78
79 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
80}
81
021357ac
CW		 82static inline u32 /* units of 100MHz */
83intel_fdi_link_freq(struct drm_device *dev)
84{
8b99e68c
CW		 85 if (IS_GEN5(dev)) {
86 struct drm_i915_private *dev_priv = dev->dev_private;
87 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
88 } else
89 return 27;
021357ac
CW		 90}
91
5d536e28 92static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 93 .dot = { .min = 25000, .max = 350000 },
94 .vco = { .min = 930000, .max = 1400000 },
95 .n = { .min = 3, .max = 16 },
96 .m = { .min = 96, .max = 140 },
97 .m1 = { .min = 18, .max = 26 },
98 .m2 = { .min = 6, .max = 16 },
99 .p = { .min = 4, .max = 128 },
100 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 101 .p2 = { .dot_limit = 165000,
102 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 103};
104
5d536e28
DV		 105static const intel_limit_t intel_limits_i8xx_dvo = {
106 .dot = { .min = 25000, .max = 350000 },
107 .vco = { .min = 930000, .max = 1400000 },
108 .n = { .min = 3, .max = 16 },
109 .m = { .min = 96, .max = 140 },
110 .m1 = { .min = 18, .max = 26 },
111 .m2 = { .min = 6, .max = 16 },
112 .p = { .min = 4, .max = 128 },
113 .p1 = { .min = 2, .max = 33 },
114 .p2 = { .dot_limit = 165000,
115 .p2_slow = 4, .p2_fast = 4 },
116};
117
e4b36699 118static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 119 .dot = { .min = 25000, .max = 350000 },
120 .vco = { .min = 930000, .max = 1400000 },
121 .n = { .min = 3, .max = 16 },
122 .m = { .min = 96, .max = 140 },
123 .m1 = { .min = 18, .max = 26 },
124 .m2 = { .min = 6, .max = 16 },
125 .p = { .min = 4, .max = 128 },
126 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 127 .p2 = { .dot_limit = 165000,
128 .p2_slow = 14, .p2_fast = 7 },
e4b36699 129};
273e27ca 130
e4b36699 131static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 132 .dot = { .min = 20000, .max = 400000 },
133 .vco = { .min = 1400000, .max = 2800000 },
134 .n = { .min = 1, .max = 6 },
135 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 136 .m1 = { .min = 8, .max = 18 },
137 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 138 .p = { .min = 5, .max = 80 },
139 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 140 .p2 = { .dot_limit = 200000,
141 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 142};
143
144static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 149 .m1 = { .min = 8, .max = 18 },
150 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 151 .p = { .min = 7, .max = 98 },
152 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 153 .p2 = { .dot_limit = 112000,
154 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 155};
156
273e27ca 157
e4b36699 158static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 159 .dot = { .min = 25000, .max = 270000 },
160 .vco = { .min = 1750000, .max = 3500000},
161 .n = { .min = 1, .max = 4 },
162 .m = { .min = 104, .max = 138 },
163 .m1 = { .min = 17, .max = 23 },
164 .m2 = { .min = 5, .max = 11 },
165 .p = { .min = 10, .max = 30 },
166 .p1 = { .min = 1, .max = 3},
167 .p2 = { .dot_limit = 270000,
168 .p2_slow = 10,
169 .p2_fast = 10
044c7c41 170 },
e4b36699
KP		 171};
172
173static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 174 .dot = { .min = 22000, .max = 400000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 16, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 5, .max = 80 },
181 .p1 = { .min = 1, .max = 8},
182 .p2 = { .dot_limit = 165000,
183 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 184};
185
186static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 187 .dot = { .min = 20000, .max = 115000 },
188 .vco = { .min = 1750000, .max = 3500000 },
189 .n = { .min = 1, .max = 3 },
190 .m = { .min = 104, .max = 138 },
191 .m1 = { .min = 17, .max = 23 },
192 .m2 = { .min = 5, .max = 11 },
193 .p = { .min = 28, .max = 112 },
194 .p1 = { .min = 2, .max = 8 },
195 .p2 = { .dot_limit = 0,
196 .p2_slow = 14, .p2_fast = 14
044c7c41 197 },
e4b36699
KP		 198};
199
200static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 201 .dot = { .min = 80000, .max = 224000 },
202 .vco = { .min = 1750000, .max = 3500000 },
203 .n = { .min = 1, .max = 3 },
204 .m = { .min = 104, .max = 138 },
205 .m1 = { .min = 17, .max = 23 },
206 .m2 = { .min = 5, .max = 11 },
207 .p = { .min = 14, .max = 42 },
208 .p1 = { .min = 2, .max = 6 },
209 .p2 = { .dot_limit = 0,
210 .p2_slow = 7, .p2_fast = 7
044c7c41 211 },
e4b36699
KP		 212};
213
f2b115e6 214static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 215 .dot = { .min = 20000, .max = 400000},
216 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 217 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 218 .n = { .min = 3, .max = 6 },
219 .m = { .min = 2, .max = 256 },
273e27ca 220 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 221 .m1 = { .min = 0, .max = 0 },
222 .m2 = { .min = 0, .max = 254 },
223 .p = { .min = 5, .max = 80 },
224 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 225 .p2 = { .dot_limit = 200000,
226 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 227};
228
f2b115e6 229static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 230 .dot = { .min = 20000, .max = 400000 },
231 .vco = { .min = 1700000, .max = 3500000 },
232 .n = { .min = 3, .max = 6 },
233 .m = { .min = 2, .max = 256 },
234 .m1 = { .min = 0, .max = 0 },
235 .m2 = { .min = 0, .max = 254 },
236 .p = { .min = 7, .max = 112 },
237 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 238 .p2 = { .dot_limit = 112000,
239 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 240};
241
273e27ca
EA		 242/* Ironlake / Sandybridge
243 *
244 * We calculate clock using (register_value + 2) for N/M1/M2, so here
245 * the range value for them is (actual_value - 2).
246 */
b91ad0ec 247static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 248 .dot = { .min = 25000, .max = 350000 },
249 .vco = { .min = 1760000, .max = 3510000 },
250 .n = { .min = 1, .max = 5 },
251 .m = { .min = 79, .max = 127 },
252 .m1 = { .min = 12, .max = 22 },
253 .m2 = { .min = 5, .max = 9 },
254 .p = { .min = 5, .max = 80 },
255 .p1 = { .min = 1, .max = 8 },
256 .p2 = { .dot_limit = 225000,
257 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 258};
259
b91ad0ec 260static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 261 .dot = { .min = 25000, .max = 350000 },
262 .vco = { .min = 1760000, .max = 3510000 },
263 .n = { .min = 1, .max = 3 },
264 .m = { .min = 79, .max = 118 },
265 .m1 = { .min = 12, .max = 22 },
266 .m2 = { .min = 5, .max = 9 },
267 .p = { .min = 28, .max = 112 },
268 .p1 = { .min = 2, .max = 8 },
269 .p2 = { .dot_limit = 225000,
270 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 271};
272
273static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 274 .dot = { .min = 25000, .max = 350000 },
275 .vco = { .min = 1760000, .max = 3510000 },
276 .n = { .min = 1, .max = 3 },
277 .m = { .min = 79, .max = 127 },
278 .m1 = { .min = 12, .max = 22 },
279 .m2 = { .min = 5, .max = 9 },
280 .p = { .min = 14, .max = 56 },
281 .p1 = { .min = 2, .max = 8 },
282 .p2 = { .dot_limit = 225000,
283 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 284};
285
273e27ca 286/* LVDS 100mhz refclk limits. */
b91ad0ec 287static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 288 .dot = { .min = 25000, .max = 350000 },
289 .vco = { .min = 1760000, .max = 3510000 },
290 .n = { .min = 1, .max = 2 },
291 .m = { .min = 79, .max = 126 },
292 .m1 = { .min = 12, .max = 22 },
293 .m2 = { .min = 5, .max = 9 },
294 .p = { .min = 28, .max = 112 },
0206e353 295 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 296 .p2 = { .dot_limit = 225000,
297 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 298};
299
300static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 301 .dot = { .min = 25000, .max = 350000 },
302 .vco = { .min = 1760000, .max = 3510000 },
303 .n = { .min = 1, .max = 3 },
304 .m = { .min = 79, .max = 126 },
305 .m1 = { .min = 12, .max = 22 },
306 .m2 = { .min = 5, .max = 9 },
307 .p = { .min = 14, .max = 42 },
0206e353 308 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 309 .p2 = { .dot_limit = 225000,
310 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 311};
312
a0c4da24
JB		 313static const intel_limit_t intel_limits_vlv_dac = {
314 .dot = { .min = 25000, .max = 270000 },
315 .vco = { .min = 4000000, .max = 6000000 },
316 .n = { .min = 1, .max = 7 },
317 .m = { .min = 22, .max = 450 }, /* guess */
318 .m1 = { .min = 2, .max = 3 },
319 .m2 = { .min = 11, .max = 156 },
320 .p = { .min = 10, .max = 30 },
75e53986 321 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 322 .p2 = { .dot_limit = 270000,
323 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 324};
325
326static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 327 .dot = { .min = 25000, .max = 270000 },
328 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 329 .n = { .min = 1, .max = 7 },
330 .m = { .min = 60, .max = 300 }, /* guess */
331 .m1 = { .min = 2, .max = 3 },
332 .m2 = { .min = 11, .max = 156 },
333 .p = { .min = 10, .max = 30 },
334 .p1 = { .min = 2, .max = 3 },
335 .p2 = { .dot_limit = 270000,
336 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 337};
338
339static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 340 .dot = { .min = 25000, .max = 270000 },
341 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 342 .n = { .min = 1, .max = 7 },
74a4dd2e 343 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 344 .m1 = { .min = 2, .max = 3 },
345 .m2 = { .min = 11, .max = 156 },
346 .p = { .min = 10, .max = 30 },
75e53986 347 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 348 .p2 = { .dot_limit = 270000,
349 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 350};
351
1b894b59
CW		 352static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
353 int refclk)
2c07245f 354{
b91ad0ec 355 struct drm_device *dev = crtc->dev;
2c07245f 356 const intel_limit_t *limit;
b91ad0ec
ZW		 357
358 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 359 if (intel_is_dual_link_lvds(dev)) {
1b894b59 360 if (refclk == 100000)
b91ad0ec
ZW		 361 limit = &intel_limits_ironlake_dual_lvds_100m;
362 else
363 limit = &intel_limits_ironlake_dual_lvds;
364 } else {
1b894b59 365 if (refclk == 100000)
b91ad0ec
ZW		 366 limit = &intel_limits_ironlake_single_lvds_100m;
367 else
368 limit = &intel_limits_ironlake_single_lvds;
369 }
c6bb3538 370 } else
b91ad0ec 371 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 372
373 return limit;
374}
375
044c7c41
ML		 376static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
377{
378 struct drm_device *dev = crtc->dev;
044c7c41
ML		 379 const intel_limit_t *limit;
380
381 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 382 if (intel_is_dual_link_lvds(dev))
e4b36699 383 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 384 else
e4b36699 385 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 386 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
387 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 388 limit = &intel_limits_g4x_hdmi;
044c7c41 389 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 390 limit = &intel_limits_g4x_sdvo;
044c7c41 391 } else /* The option is for other outputs */
e4b36699 392 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 393
394 return limit;
395}
396
1b894b59 397static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 398{
399 struct drm_device *dev = crtc->dev;
400 const intel_limit_t *limit;
401
bad720ff 402 if (HAS_PCH_SPLIT(dev))
1b894b59 403 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 404 else if (IS_G4X(dev)) {
044c7c41 405 limit = intel_g4x_limit(crtc);
f2b115e6 406 } else if (IS_PINEVIEW(dev)) {
2177832f 407 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 408 limit = &intel_limits_pineview_lvds;
2177832f 409 else
f2b115e6 410 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 411 } else if (IS_VALLEYVIEW(dev)) {
412 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
413 limit = &intel_limits_vlv_dac;
414 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
415 limit = &intel_limits_vlv_hdmi;
416 else
417 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 418 } else if (!IS_GEN2(dev)) {
419 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
420 limit = &intel_limits_i9xx_lvds;
421 else
422 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 423 } else {
424 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 425 limit = &intel_limits_i8xx_lvds;
5d536e28 426 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 427 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 428 else
429 limit = &intel_limits_i8xx_dac;
79e53945
JB		 430 }
431 return limit;
432}
433
f2b115e6
AJ		 434/* m1 is reserved as 0 in Pineview, n is a ring counter */
435static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 436{
2177832f
SL		 437 clock->m = clock->m2 + 2;
438 clock->p = clock->p1 * clock->p2;
439 clock->vco = refclk * clock->m / clock->n;
440 clock->dot = clock->vco / clock->p;
441}
442
7429e9d4
DV		 443static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
444{
445 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
446}
447
ac58c3f0 448static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 449{
7429e9d4 450 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 451 clock->p = clock->p1 * clock->p2;
452 clock->vco = refclk * clock->m / (clock->n + 2);
453 clock->dot = clock->vco / clock->p;
454}
455
79e53945
JB		 456/**
457 * Returns whether any output on the specified pipe is of the specified type
458 */
4ef69c7a 459bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 460{
4ef69c7a 461 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 462 struct intel_encoder *encoder;
463
6c2b7c12
DV		 464 for_each_encoder_on_crtc(dev, crtc, encoder)
465 if (encoder->type == type)
4ef69c7a
CW		 466 return true;
467
468 return false;
79e53945
JB		 469}
470
7c04d1d9 471#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 472/**
473 * Returns whether the given set of divisors are valid for a given refclk with
474 * the given connectors.
475 */
476
1b894b59
CW		 477static bool intel_PLL_is_valid(struct drm_device *dev,
478 const intel_limit_t *limit,
479 const intel_clock_t *clock)
79e53945 480{
79e53945 481 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 482 INTELPllInvalid("p1 out of range\n");
79e53945 483 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 484 INTELPllInvalid("p out of range\n");
79e53945 485 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 486 INTELPllInvalid("m2 out of range\n");
79e53945 487 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 488 INTELPllInvalid("m1 out of range\n");
f2b115e6 489 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 490 INTELPllInvalid("m1 <= m2\n");
79e53945 491 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 492 INTELPllInvalid("m out of range\n");
79e53945 493 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 494 INTELPllInvalid("n out of range\n");
79e53945 495 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 496 INTELPllInvalid("vco out of range\n");
79e53945
JB		 497 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
498 * connector, etc., rather than just a single range.
499 */
500 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 501 INTELPllInvalid("dot out of range\n");
79e53945
JB		 502
503 return true;
504}
505
d4906093 506static bool
ee9300bb 507i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 508 int target, int refclk, intel_clock_t *match_clock,
509 intel_clock_t *best_clock)
79e53945
JB		 510{
511 struct drm_device *dev = crtc->dev;
79e53945 512 intel_clock_t clock;
79e53945
JB		 513 int err = target;
514
a210b028 515 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 516 /*
a210b028
DV		 517 * For LVDS just rely on its current settings for dual-channel.
518 * We haven't figured out how to reliably set up different
519 * single/dual channel state, if we even can.
79e53945 520 */
1974cad0 521 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 522 clock.p2 = limit->p2.p2_fast;
523 else
524 clock.p2 = limit->p2.p2_slow;
525 } else {
526 if (target < limit->p2.dot_limit)
527 clock.p2 = limit->p2.p2_slow;
528 else
529 clock.p2 = limit->p2.p2_fast;
530 }
531
0206e353 532 memset(best_clock, 0, sizeof(*best_clock));
79e53945 533
42158660
ZY		 534 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
535 clock.m1++) {
536 for (clock.m2 = limit->m2.min;
537 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 538 if (clock.m2 >= clock.m1)
42158660
ZY		 539 break;
540 for (clock.n = limit->n.min;
541 clock.n <= limit->n.max; clock.n++) {
542 for (clock.p1 = limit->p1.min;
543 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 544 int this_err;
545
ac58c3f0
DV		 546 i9xx_clock(refclk, &clock);
547 if (!intel_PLL_is_valid(dev, limit,
548 &clock))
549 continue;
550 if (match_clock &&
551 clock.p != match_clock->p)
552 continue;
553
554 this_err = abs(clock.dot - target);
555 if (this_err < err) {
556 *best_clock = clock;
557 err = this_err;
558 }
559 }
560 }
561 }
562 }
563
564 return (err != target);
565}
566
567static bool
ee9300bb
DV		 568pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
569 int target, int refclk, intel_clock_t *match_clock,
570 intel_clock_t *best_clock)
79e53945
JB		 571{
572 struct drm_device *dev = crtc->dev;
79e53945 573 intel_clock_t clock;
79e53945
JB		 574 int err = target;
575
a210b028 576 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 577 /*
a210b028
DV		 578 * For LVDS just rely on its current settings for dual-channel.
579 * We haven't figured out how to reliably set up different
580 * single/dual channel state, if we even can.
79e53945 581 */
1974cad0 582 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 583 clock.p2 = limit->p2.p2_fast;
584 else
585 clock.p2 = limit->p2.p2_slow;
586 } else {
587 if (target < limit->p2.dot_limit)
588 clock.p2 = limit->p2.p2_slow;
589 else
590 clock.p2 = limit->p2.p2_fast;
591 }
592
0206e353 593 memset(best_clock, 0, sizeof(*best_clock));
79e53945 594
42158660
ZY		 595 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
596 clock.m1++) {
597 for (clock.m2 = limit->m2.min;
598 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 599 for (clock.n = limit->n.min;
600 clock.n <= limit->n.max; clock.n++) {
601 for (clock.p1 = limit->p1.min;
602 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 603 int this_err;
604
ac58c3f0 605 pineview_clock(refclk, &clock);
1b894b59
CW		 606 if (!intel_PLL_is_valid(dev, limit,
607 &clock))
79e53945 608 continue;
cec2f356
SP		 609 if (match_clock &&
610 clock.p != match_clock->p)
611 continue;
79e53945
JB		 612
613 this_err = abs(clock.dot - target);
614 if (this_err < err) {
615 *best_clock = clock;
616 err = this_err;
617 }
618 }
619 }
620 }
621 }
622
623 return (err != target);
624}
625
d4906093 626static bool
ee9300bb
DV		 627g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
628 int target, int refclk, intel_clock_t *match_clock,
629 intel_clock_t *best_clock)
d4906093
ML		 630{
631 struct drm_device *dev = crtc->dev;
d4906093
ML		 632 intel_clock_t clock;
633 int max_n;
634 bool found;
6ba770dc
AJ		 635 /* approximately equals target * 0.00585 */
636 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 637 found = false;
638
639 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 640 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 641 clock.p2 = limit->p2.p2_fast;
642 else
643 clock.p2 = limit->p2.p2_slow;
644 } else {
645 if (target < limit->p2.dot_limit)
646 clock.p2 = limit->p2.p2_slow;
647 else
648 clock.p2 = limit->p2.p2_fast;
649 }
650
651 memset(best_clock, 0, sizeof(*best_clock));
652 max_n = limit->n.max;
f77f13e2 653 /* based on hardware requirement, prefer smaller n to precision */
d4906093 654 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 655 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 656 for (clock.m1 = limit->m1.max;
657 clock.m1 >= limit->m1.min; clock.m1--) {
658 for (clock.m2 = limit->m2.max;
659 clock.m2 >= limit->m2.min; clock.m2--) {
660 for (clock.p1 = limit->p1.max;
661 clock.p1 >= limit->p1.min; clock.p1--) {
662 int this_err;
663
ac58c3f0 664 i9xx_clock(refclk, &clock);
1b894b59
CW		 665 if (!intel_PLL_is_valid(dev, limit,
666 &clock))
d4906093 667 continue;
1b894b59
CW		 668
669 this_err = abs(clock.dot - target);
d4906093
ML		 670 if (this_err < err_most) {
671 *best_clock = clock;
672 err_most = this_err;
673 max_n = clock.n;
674 found = true;
675 }
676 }
677 }
678 }
679 }
2c07245f
ZW		 680 return found;
681}
682
a0c4da24 683static bool
ee9300bb
DV		 684vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
685 int target, int refclk, intel_clock_t *match_clock,
686 intel_clock_t *best_clock)
a0c4da24
JB		 687{
688 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
689 u32 m, n, fastclk;
690 u32 updrate, minupdate, fracbits, p;
691 unsigned long bestppm, ppm, absppm;
692 int dotclk, flag;
693
af447bd3 694 flag = 0;
a0c4da24
JB		 695 dotclk = target * 1000;
696 bestppm = 1000000;
697 ppm = absppm = 0;
698 fastclk = dotclk / (2*100);
699 updrate = 0;
700 minupdate = 19200;
701 fracbits = 1;
702 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
703 bestm1 = bestm2 = bestp1 = bestp2 = 0;
704
705 /* based on hardware requirement, prefer smaller n to precision */
706 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
707 updrate = refclk / n;
708 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
709 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
710 if (p2 > 10)
711 p2 = p2 - 1;
712 p = p1 * p2;
713 /* based on hardware requirement, prefer bigger m1,m2 values */
714 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
715 m2 = (((2*(fastclk * p * n / m1 )) +
716 refclk) / (2*refclk));
717 m = m1 * m2;
718 vco = updrate * m;
719 if (vco >= limit->vco.min && vco < limit->vco.max) {
720 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
721 absppm = (ppm > 0) ? ppm : (-ppm);
722 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
723 bestppm = 0;
724 flag = 1;
725 }
726 if (absppm < bestppm - 10) {
727 bestppm = absppm;
728 flag = 1;
729 }
730 if (flag) {
731 bestn = n;
732 bestm1 = m1;
733 bestm2 = m2;
734 bestp1 = p1;
735 bestp2 = p2;
736 flag = 0;
737 }
738 }
739 }
740 }
741 }
742 }
743 best_clock->n = bestn;
744 best_clock->m1 = bestm1;
745 best_clock->m2 = bestm2;
746 best_clock->p1 = bestp1;
747 best_clock->p2 = bestp2;
748
749 return true;
750}
a4fc5ed6 751
a5c961d1
PZ		 752enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
753 enum pipe pipe)
754{
755 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
757
3b117c8f 758 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 759}
760
a928d536
PZ		 761static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
762{
763 struct drm_i915_private *dev_priv = dev->dev_private;
764 u32 frame, frame_reg = PIPEFRAME(pipe);
765
766 frame = I915_READ(frame_reg);
767
768 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
769 DRM_DEBUG_KMS("vblank wait timed out\n");
770}
771
9d0498a2
JB		 772/**
773 * intel_wait_for_vblank - wait for vblank on a given pipe
774 * @dev: drm device
775 * @pipe: pipe to wait for
776 *
777 * Wait for vblank to occur on a given pipe. Needed for various bits of
778 * mode setting code.
779 */
780void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 781{
9d0498a2 782 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 783 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 784
a928d536
PZ		 785 if (INTEL_INFO(dev)->gen >= 5) {
786 ironlake_wait_for_vblank(dev, pipe);
787 return;
788 }
789
300387c0
CW		 790 /* Clear existing vblank status. Note this will clear any other
791 * sticky status fields as well.
792 *
793 * This races with i915_driver_irq_handler() with the result
794 * that either function could miss a vblank event. Here it is not
795 * fatal, as we will either wait upon the next vblank interrupt or
796 * timeout. Generally speaking intel_wait_for_vblank() is only
797 * called during modeset at which time the GPU should be idle and
798 * should *not* be performing page flips and thus not waiting on
799 * vblanks...
800 * Currently, the result of us stealing a vblank from the irq
801 * handler is that a single frame will be skipped during swapbuffers.
802 */
803 I915_WRITE(pipestat_reg,
804 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
805
9d0498a2 806 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 807 if (wait_for(I915_READ(pipestat_reg) &
808 PIPE_VBLANK_INTERRUPT_STATUS,
809 50))
9d0498a2
JB		 810 DRM_DEBUG_KMS("vblank wait timed out\n");
811}
812
ab7ad7f6
KP		 813/*
814 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 815 * @dev: drm device
816 * @pipe: pipe to wait for
817 *
818 * After disabling a pipe, we can't wait for vblank in the usual way,
819 * spinning on the vblank interrupt status bit, since we won't actually
820 * see an interrupt when the pipe is disabled.
821 *
ab7ad7f6
KP		 822 * On Gen4 and above:
823 * wait for the pipe register state bit to turn off
824 *
825 * Otherwise:
826 * wait for the display line value to settle (it usually
827 * ends up stopping at the start of the next frame).
58e10eb9 828 *
9d0498a2 829 */
58e10eb9 830void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 831{
832 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 833 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
834 pipe);
ab7ad7f6
KP		 835
836 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 837 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 838
839 /* Wait for the Pipe State to go off */
58e10eb9
CW		 840 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
841 100))
284637d9 842 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 843 } else {
837ba00f 844 u32 last_line, line_mask;
58e10eb9 845 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 846 unsigned long timeout = jiffies + msecs_to_jiffies(100);
847
837ba00f
PZ		 848 if (IS_GEN2(dev))
849 line_mask = DSL_LINEMASK_GEN2;
850 else
851 line_mask = DSL_LINEMASK_GEN3;
852
ab7ad7f6
KP		 853 /* Wait for the display line to settle */
854 do {
837ba00f 855 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 856 mdelay(5);
837ba00f 857 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 858 time_after(timeout, jiffies));
859 if (time_after(jiffies, timeout))
284637d9 860 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 861 }
79e53945
JB		 862}
863
b0ea7d37
DL		 864/*
865 * ibx_digital_port_connected - is the specified port connected?
866 * @dev_priv: i915 private structure
867 * @port: the port to test
868 *
869 * Returns true if @port is connected, false otherwise.
870 */
871bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
872 struct intel_digital_port *port)
873{
874 u32 bit;
875
c36346e3
DL		 876 if (HAS_PCH_IBX(dev_priv->dev)) {
877 switch(port->port) {
878 case PORT_B:
879 bit = SDE_PORTB_HOTPLUG;
880 break;
881 case PORT_C:
882 bit = SDE_PORTC_HOTPLUG;
883 break;
884 case PORT_D:
885 bit = SDE_PORTD_HOTPLUG;
886 break;
887 default:
888 return true;
889 }
890 } else {
891 switch(port->port) {
892 case PORT_B:
893 bit = SDE_PORTB_HOTPLUG_CPT;
894 break;
895 case PORT_C:
896 bit = SDE_PORTC_HOTPLUG_CPT;
897 break;
898 case PORT_D:
899 bit = SDE_PORTD_HOTPLUG_CPT;
900 break;
901 default:
902 return true;
903 }
b0ea7d37
DL		 904 }
905
906 return I915_READ(SDEISR) & bit;
907}
908
b24e7179
JB		 909static const char *state_string(bool enabled)
910{
911 return enabled ? "on" : "off";
912}
913
914/* Only for pre-ILK configs */
55607e8a
DV		 915void assert_pll(struct drm_i915_private *dev_priv,
916 enum pipe pipe, bool state)
b24e7179
JB		 917{
918 int reg;
919 u32 val;
920 bool cur_state;
921
922 reg = DPLL(pipe);
923 val = I915_READ(reg);
924 cur_state = !!(val & DPLL_VCO_ENABLE);
925 WARN(cur_state != state,
926 "PLL state assertion failure (expected %s, current %s)\n",
927 state_string(state), state_string(cur_state));
928}
b24e7179 929
55607e8a 930struct intel_shared_dpll *
e2b78267
DV		 931intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
932{
933 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
934
a43f6e0f 935 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 936 return NULL;
937
a43f6e0f 938 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 939}
940
040484af 941/* For ILK+ */
55607e8a
DV		 942void assert_shared_dpll(struct drm_i915_private *dev_priv,
943 struct intel_shared_dpll *pll,
944 bool state)
040484af 945{
040484af 946 bool cur_state;
5358901f 947 struct intel_dpll_hw_state hw_state;
040484af 948
9d82aa17
ED		 949 if (HAS_PCH_LPT(dev_priv->dev)) {
950 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
951 return;
952 }
953
92b27b08 954 if (WARN (!pll,
46edb027 955 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 956 return;
ee7b9f93 957
5358901f 958 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 959 WARN(cur_state != state,
5358901f
DV		 960 "%s assertion failure (expected %s, current %s)\n",
961 pll->name, state_string(state), state_string(cur_state));
040484af 962}
040484af
JB		 963
964static void assert_fdi_tx(struct drm_i915_private *dev_priv,
965 enum pipe pipe, bool state)
966{
967 int reg;
968 u32 val;
969 bool cur_state;
ad80a810
PZ		 970 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
971 pipe);
040484af 972
affa9354
PZ		 973 if (HAS_DDI(dev_priv->dev)) {
974 /* DDI does not have a specific FDI_TX register */
ad80a810 975 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 976 val = I915_READ(reg);
ad80a810 977 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 978 } else {
979 reg = FDI_TX_CTL(pipe);
980 val = I915_READ(reg);
981 cur_state = !!(val & FDI_TX_ENABLE);
982 }
040484af
JB		 983 WARN(cur_state != state,
984 "FDI TX state assertion failure (expected %s, current %s)\n",
985 state_string(state), state_string(cur_state));
986}
987#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
988#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
989
990static void assert_fdi_rx(struct drm_i915_private *dev_priv,
991 enum pipe pipe, bool state)
992{
993 int reg;
994 u32 val;
995 bool cur_state;
996
d63fa0dc
PZ		 997 reg = FDI_RX_CTL(pipe);
998 val = I915_READ(reg);
999 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1000 WARN(cur_state != state,
1001 "FDI RX state assertion failure (expected %s, current %s)\n",
1002 state_string(state), state_string(cur_state));
1003}
1004#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1005#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1006
1007static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1008 enum pipe pipe)
1009{
1010 int reg;
1011 u32 val;
1012
1013 /* ILK FDI PLL is always enabled */
1014 if (dev_priv->info->gen == 5)
1015 return;
1016
bf507ef7 1017 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1018 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1019 return;
1020
040484af
JB		 1021 reg = FDI_TX_CTL(pipe);
1022 val = I915_READ(reg);
1023 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1024}
1025
55607e8a
DV		 1026void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1027 enum pipe pipe, bool state)
040484af
JB		 1028{
1029 int reg;
1030 u32 val;
55607e8a 1031 bool cur_state;
040484af
JB		 1032
1033 reg = FDI_RX_CTL(pipe);
1034 val = I915_READ(reg);
55607e8a
DV		 1035 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1036 WARN(cur_state != state,
1037 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1038 state_string(state), state_string(cur_state));
040484af
JB		 1039}
1040
ea0760cf
JB		 1041static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1042 enum pipe pipe)
1043{
1044 int pp_reg, lvds_reg;
1045 u32 val;
1046 enum pipe panel_pipe = PIPE_A;
0de3b485 1047 bool locked = true;
ea0760cf
JB		 1048
1049 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1050 pp_reg = PCH_PP_CONTROL;
1051 lvds_reg = PCH_LVDS;
1052 } else {
1053 pp_reg = PP_CONTROL;
1054 lvds_reg = LVDS;
1055 }
1056
1057 val = I915_READ(pp_reg);
1058 if (!(val & PANEL_POWER_ON) ||
1059 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1060 locked = false;
1061
1062 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1063 panel_pipe = PIPE_B;
1064
1065 WARN(panel_pipe == pipe && locked,
1066 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1067 pipe_name(pipe));
ea0760cf
JB		 1068}
1069
b840d907
JB		 1070void assert_pipe(struct drm_i915_private *dev_priv,
1071 enum pipe pipe, bool state)
b24e7179
JB		 1072{
1073 int reg;
1074 u32 val;
63d7bbe9 1075 bool cur_state;
702e7a56
PZ		 1076 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1077 pipe);
b24e7179 1078
8e636784
DV		 1079 /* if we need the pipe A quirk it must be always on */
1080 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1081 state = true;
1082
b97186f0
PZ		 1083 if (!intel_display_power_enabled(dev_priv->dev,
1084 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1085 cur_state = false;
1086 } else {
1087 reg = PIPECONF(cpu_transcoder);
1088 val = I915_READ(reg);
1089 cur_state = !!(val & PIPECONF_ENABLE);
1090 }
1091
63d7bbe9
JB		 1092 WARN(cur_state != state,
1093 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1094 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1095}
1096
931872fc
CW		 1097static void assert_plane(struct drm_i915_private *dev_priv,
1098 enum plane plane, bool state)
b24e7179
JB		 1099{
1100 int reg;
1101 u32 val;
931872fc 1102 bool cur_state;
b24e7179
JB		 1103
1104 reg = DSPCNTR(plane);
1105 val = I915_READ(reg);
931872fc
CW		 1106 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1107 WARN(cur_state != state,
1108 "plane %c assertion failure (expected %s, current %s)\n",
1109 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1110}
1111
931872fc
CW		 1112#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1113#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1114
b24e7179
JB		 1115static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1116 enum pipe pipe)
1117{
653e1026 1118 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1119 int reg, i;
1120 u32 val;
1121 int cur_pipe;
1122
653e1026
VS		 1123 /* Primary planes are fixed to pipes on gen4+ */
1124 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1125 reg = DSPCNTR(pipe);
1126 val = I915_READ(reg);
1127 WARN((val & DISPLAY_PLANE_ENABLE),
1128 "plane %c assertion failure, should be disabled but not\n",
1129 plane_name(pipe));
19ec1358 1130 return;
28c05794 1131 }
19ec1358 1132
b24e7179 1133 /* Need to check both planes against the pipe */
653e1026 1134 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
b24e7179
JB		 1135 reg = DSPCNTR(i);
1136 val = I915_READ(reg);
1137 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1138 DISPPLANE_SEL_PIPE_SHIFT;
1139 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1140 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1141 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1142 }
1143}
1144
19332d7a
JB		 1145static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1146 enum pipe pipe)
1147{
20674eef 1148 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1149 int reg, i;
1150 u32 val;
1151
20674eef
VS		 1152 if (IS_VALLEYVIEW(dev)) {
1153 for (i = 0; i < dev_priv->num_plane; i++) {
1154 reg = SPCNTR(pipe, i);
1155 val = I915_READ(reg);
1156 WARN((val & SP_ENABLE),
1157 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1158 sprite_name(pipe, i), pipe_name(pipe));
1159 }
1160 } else if (INTEL_INFO(dev)->gen >= 7) {
1161 reg = SPRCTL(pipe);
19332d7a 1162 val = I915_READ(reg);
20674eef 1163 WARN((val & SPRITE_ENABLE),
06da8da2 1164 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1165 plane_name(pipe), pipe_name(pipe));
1166 } else if (INTEL_INFO(dev)->gen >= 5) {
1167 reg = DVSCNTR(pipe);
19332d7a 1168 val = I915_READ(reg);
20674eef 1169 WARN((val & DVS_ENABLE),
06da8da2 1170 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1171 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1172 }
1173}
1174
92f2584a
JB		 1175static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1176{
1177 u32 val;
1178 bool enabled;
1179
9d82aa17
ED		 1180 if (HAS_PCH_LPT(dev_priv->dev)) {
1181 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1182 return;
1183 }
1184
92f2584a
JB		 1185 val = I915_READ(PCH_DREF_CONTROL);
1186 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1187 DREF_SUPERSPREAD_SOURCE_MASK));
1188 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1189}
1190
ab9412ba
DV		 1191static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1192 enum pipe pipe)
92f2584a
JB		 1193{
1194 int reg;
1195 u32 val;
1196 bool enabled;
1197
ab9412ba 1198 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1199 val = I915_READ(reg);
1200 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1201 WARN(enabled,
1202 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1203 pipe_name(pipe));
92f2584a
JB		 1204}
1205
4e634389
KP		 1206static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1207 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1208{
1209 if ((val & DP_PORT_EN) == 0)
1210 return false;
1211
1212 if (HAS_PCH_CPT(dev_priv->dev)) {
1213 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1214 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1215 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1216 return false;
1217 } else {
1218 if ((val & DP_PIPE_MASK) != (pipe << 30))
1219 return false;
1220 }
1221 return true;
1222}
1223
1519b995
KP		 1224static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1225 enum pipe pipe, u32 val)
1226{
dc0fa718 1227 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1228 return false;
1229
1230 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1231 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1232 return false;
1233 } else {
dc0fa718 1234 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1235 return false;
1236 }
1237 return true;
1238}
1239
1240static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1241 enum pipe pipe, u32 val)
1242{
1243 if ((val & LVDS_PORT_EN) == 0)
1244 return false;
1245
1246 if (HAS_PCH_CPT(dev_priv->dev)) {
1247 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1248 return false;
1249 } else {
1250 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1251 return false;
1252 }
1253 return true;
1254}
1255
1256static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1257 enum pipe pipe, u32 val)
1258{
1259 if ((val & ADPA_DAC_ENABLE) == 0)
1260 return false;
1261 if (HAS_PCH_CPT(dev_priv->dev)) {
1262 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1263 return false;
1264 } else {
1265 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1266 return false;
1267 }
1268 return true;
1269}
1270
291906f1 1271static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1272 enum pipe pipe, int reg, u32 port_sel)
291906f1 1273{
47a05eca 1274 u32 val = I915_READ(reg);
4e634389 1275 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1276 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1277 reg, pipe_name(pipe));
de9a35ab 1278
75c5da27
DV		 1279 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1280 && (val & DP_PIPEB_SELECT),
de9a35ab 1281 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1282}
1283
1284static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1285 enum pipe pipe, int reg)
1286{
47a05eca 1287 u32 val = I915_READ(reg);
b70ad586 1288 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1289 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1290 reg, pipe_name(pipe));
de9a35ab 1291
dc0fa718 1292 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1293 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1294 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1295}
1296
1297static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1298 enum pipe pipe)
1299{
1300 int reg;
1301 u32 val;
291906f1 1302
f0575e92
KP		 1303 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1304 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1305 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1306
1307 reg = PCH_ADPA;
1308 val = I915_READ(reg);
b70ad586 1309 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1310 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1311 pipe_name(pipe));
291906f1
JB		 1312
1313 reg = PCH_LVDS;
1314 val = I915_READ(reg);
b70ad586 1315 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1316 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1317 pipe_name(pipe));
291906f1 1318
e2debe91
PZ		 1319 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1320 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1321 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1322}
1323
87442f73
DV		 1324static void vlv_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1325{
1326 int reg;
1327 u32 val;
1328
1329 assert_pipe_disabled(dev_priv, pipe);
1330
1331 /* No really, not for ILK+ */
1332 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1333
1334 /* PLL is protected by panel, make sure we can write it */
1335 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1336 assert_panel_unlocked(dev_priv, pipe);
1337
1338 reg = DPLL(pipe);
1339 val = I915_READ(reg);
1340 val |= DPLL_VCO_ENABLE;
1341
1342 /* We do this three times for luck */
1343 I915_WRITE(reg, val);
1344 POSTING_READ(reg);
1345 udelay(150); /* wait for warmup */
1346 I915_WRITE(reg, val);
1347 POSTING_READ(reg);
1348 udelay(150); /* wait for warmup */
1349 I915_WRITE(reg, val);
1350 POSTING_READ(reg);
1351 udelay(150); /* wait for warmup */
1352}
1353
66e3d5c0 1354static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1355{
66e3d5c0
DV		 1356 struct drm_device *dev = crtc->base.dev;
1357 struct drm_i915_private *dev_priv = dev->dev_private;
1358 int reg = DPLL(crtc->pipe);
1359 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1360
66e3d5c0 1361 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1362
63d7bbe9 1363 /* No really, not for ILK+ */
87442f73 1364 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1365
1366 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1367 if (IS_MOBILE(dev) && !IS_I830(dev))
1368 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1369
66e3d5c0
DV		 1370 I915_WRITE(reg, dpll);
1371
1372 /* Wait for the clocks to stabilize. */
1373 POSTING_READ(reg);
1374 udelay(150);
1375
1376 if (INTEL_INFO(dev)->gen >= 4) {
1377 I915_WRITE(DPLL_MD(crtc->pipe),
1378 crtc->config.dpll_hw_state.dpll_md);
1379 } else {
1380 /* The pixel multiplier can only be updated once the
1381 * DPLL is enabled and the clocks are stable.
1382 *
1383 * So write it again.
1384 */
1385 I915_WRITE(reg, dpll);
1386 }
63d7bbe9
JB		 1387
1388 /* We do this three times for luck */
66e3d5c0 1389 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1390 POSTING_READ(reg);
1391 udelay(150); /* wait for warmup */
66e3d5c0 1392 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1393 POSTING_READ(reg);
1394 udelay(150); /* wait for warmup */
66e3d5c0 1395 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1396 POSTING_READ(reg);
1397 udelay(150); /* wait for warmup */
1398}
1399
1400/**
1401 * intel_disable_pll - disable a PLL
1402 * @dev_priv: i915 private structure
1403 * @pipe: pipe PLL to disable
1404 *
1405 * Disable the PLL for @pipe, making sure the pipe is off first.
1406 *
1407 * Note! This is for pre-ILK only.
1408 */
1409static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1410{
1411 int reg;
1412 u32 val;
1413
1414 /* Don't disable pipe A or pipe A PLLs if needed */
1415 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1416 return;
1417
1418 /* Make sure the pipe isn't still relying on us */
1419 assert_pipe_disabled(dev_priv, pipe);
1420
1421 reg = DPLL(pipe);
1422 val = I915_READ(reg);
1423 val &= ~DPLL_VCO_ENABLE;
1424 I915_WRITE(reg, val);
1425 POSTING_READ(reg);
1426}
1427
89b667f8
JB		 1428void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1429{
1430 u32 port_mask;
1431
1432 if (!port)
1433 port_mask = DPLL_PORTB_READY_MASK;
1434 else
1435 port_mask = DPLL_PORTC_READY_MASK;
1436
1437 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1438 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1439 'B' + port, I915_READ(DPLL(0)));
1440}
1441
92f2584a 1442/**
e72f9fbf 1443 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1444 * @dev_priv: i915 private structure
1445 * @pipe: pipe PLL to enable
1446 *
1447 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1448 * drives the transcoder clock.
1449 */
e2b78267 1450static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1451{
e2b78267
DV		 1452 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1453 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1454
48da64a8 1455 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1456 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1457 if (WARN_ON(pll == NULL))
48da64a8
CW		 1458 return;
1459
1460 if (WARN_ON(pll->refcount == 0))
1461 return;
ee7b9f93 1462
46edb027
DV		 1463 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1464 pll->name, pll->active, pll->on,
e2b78267 1465 crtc->base.base.id);
92f2584a 1466
cdbd2316
DV		 1467 if (pll->active++) {
1468 WARN_ON(!pll->on);
e9d6944e 1469 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1470 return;
1471 }
f4a091c7 1472 WARN_ON(pll->on);
ee7b9f93 1473
46edb027 1474 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1475 pll->enable(dev_priv, pll);
ee7b9f93 1476 pll->on = true;
92f2584a
JB		 1477}
1478
e2b78267 1479static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1480{
e2b78267
DV		 1481 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1482 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1483
92f2584a
JB		 1484 /* PCH only available on ILK+ */
1485 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1486 if (WARN_ON(pll == NULL))
ee7b9f93 1487 return;
92f2584a 1488
48da64a8
CW		 1489 if (WARN_ON(pll->refcount == 0))
1490 return;
7a419866 1491
46edb027
DV		 1492 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1493 pll->name, pll->active, pll->on,
e2b78267 1494 crtc->base.base.id);
7a419866 1495
48da64a8 1496 if (WARN_ON(pll->active == 0)) {
e9d6944e 1497 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1498 return;
1499 }
1500
e9d6944e 1501 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1502 WARN_ON(!pll->on);
cdbd2316 1503 if (--pll->active)
7a419866 1504 return;
ee7b9f93 1505
46edb027 1506 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1507 pll->disable(dev_priv, pll);
ee7b9f93 1508 pll->on = false;
92f2584a
JB		 1509}
1510
b8a4f404
PZ		 1511static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1512 enum pipe pipe)
040484af 1513{
23670b32 1514 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1515 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1517 uint32_t reg, val, pipeconf_val;
040484af
JB		 1518
1519 /* PCH only available on ILK+ */
1520 BUG_ON(dev_priv->info->gen < 5);
1521
1522 /* Make sure PCH DPLL is enabled */
e72f9fbf 1523 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1524 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1525
1526 /* FDI must be feeding us bits for PCH ports */
1527 assert_fdi_tx_enabled(dev_priv, pipe);
1528 assert_fdi_rx_enabled(dev_priv, pipe);
1529
23670b32
DV		 1530 if (HAS_PCH_CPT(dev)) {
1531 /* Workaround: Set the timing override bit before enabling the
1532 * pch transcoder. */
1533 reg = TRANS_CHICKEN2(pipe);
1534 val = I915_READ(reg);
1535 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1536 I915_WRITE(reg, val);
59c859d6 1537 }
23670b32 1538
ab9412ba 1539 reg = PCH_TRANSCONF(pipe);
040484af 1540 val = I915_READ(reg);
5f7f726d 1541 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1542
1543 if (HAS_PCH_IBX(dev_priv->dev)) {
1544 /*
1545 * make the BPC in transcoder be consistent with
1546 * that in pipeconf reg.
1547 */
dfd07d72
DV		 1548 val &= ~PIPECONF_BPC_MASK;
1549 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1550 }
5f7f726d
PZ		 1551
1552 val &= ~TRANS_INTERLACE_MASK;
1553 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1554 if (HAS_PCH_IBX(dev_priv->dev) &&
1555 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1556 val |= TRANS_LEGACY_INTERLACED_ILK;
1557 else
1558 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1559 else
1560 val |= TRANS_PROGRESSIVE;
1561
040484af
JB		 1562 I915_WRITE(reg, val | TRANS_ENABLE);
1563 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1564 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1565}
1566
8fb033d7 1567static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1568 enum transcoder cpu_transcoder)
040484af 1569{
8fb033d7 1570 u32 val, pipeconf_val;
8fb033d7
PZ		 1571
1572 /* PCH only available on ILK+ */
1573 BUG_ON(dev_priv->info->gen < 5);
1574
8fb033d7 1575 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1576 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1577 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1578
223a6fdf
PZ		 1579 /* Workaround: set timing override bit. */
1580 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1581 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1582 I915_WRITE(_TRANSA_CHICKEN2, val);
1583
25f3ef11 1584 val = TRANS_ENABLE;
937bb610 1585 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1586
9a76b1c6
PZ		 1587 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1588 PIPECONF_INTERLACED_ILK)
a35f2679 1589 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1590 else
1591 val |= TRANS_PROGRESSIVE;
1592
ab9412ba
DV		 1593 I915_WRITE(LPT_TRANSCONF, val);
1594 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1595 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1596}
1597
b8a4f404
PZ		 1598static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1599 enum pipe pipe)
040484af 1600{
23670b32
DV		 1601 struct drm_device *dev = dev_priv->dev;
1602 uint32_t reg, val;
040484af
JB		 1603
1604 /* FDI relies on the transcoder */
1605 assert_fdi_tx_disabled(dev_priv, pipe);
1606 assert_fdi_rx_disabled(dev_priv, pipe);
1607
291906f1
JB		 1608 /* Ports must be off as well */
1609 assert_pch_ports_disabled(dev_priv, pipe);
1610
ab9412ba 1611 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1612 val = I915_READ(reg);
1613 val &= ~TRANS_ENABLE;
1614 I915_WRITE(reg, val);
1615 /* wait for PCH transcoder off, transcoder state */
1616 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1617 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1618
1619 if (!HAS_PCH_IBX(dev)) {
1620 /* Workaround: Clear the timing override chicken bit again. */
1621 reg = TRANS_CHICKEN2(pipe);
1622 val = I915_READ(reg);
1623 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1624 I915_WRITE(reg, val);
1625 }
040484af
JB		 1626}
1627
ab4d966c 1628static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1629{
8fb033d7
PZ		 1630 u32 val;
1631
ab9412ba 1632 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1633 val &= ~TRANS_ENABLE;
ab9412ba 1634 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1635 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1636 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1637 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1638
1639 /* Workaround: clear timing override bit. */
1640 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1641 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1642 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1643}
1644
b24e7179 1645/**
309cfea8 1646 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1647 * @dev_priv: i915 private structure
1648 * @pipe: pipe to enable
040484af 1649 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1650 *
1651 * Enable @pipe, making sure that various hardware specific requirements
1652 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1653 *
1654 * @pipe should be %PIPE_A or %PIPE_B.
1655 *
1656 * Will wait until the pipe is actually running (i.e. first vblank) before
1657 * returning.
1658 */
040484af
JB		 1659static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1660 bool pch_port)
b24e7179 1661{
702e7a56
PZ		 1662 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1663 pipe);
1a240d4d 1664 enum pipe pch_transcoder;
b24e7179
JB		 1665 int reg;
1666 u32 val;
1667
58c6eaa2
DV		 1668 assert_planes_disabled(dev_priv, pipe);
1669 assert_sprites_disabled(dev_priv, pipe);
1670
681e5811 1671 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1672 pch_transcoder = TRANSCODER_A;
1673 else
1674 pch_transcoder = pipe;
1675
b24e7179
JB		 1676 /*
1677 * A pipe without a PLL won't actually be able to drive bits from
1678 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1679 * need the check.
1680 */
1681 if (!HAS_PCH_SPLIT(dev_priv->dev))
1682 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1683 else {
1684 if (pch_port) {
1685 /* if driving the PCH, we need FDI enabled */
cc391bbb 1686 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1687 assert_fdi_tx_pll_enabled(dev_priv,
1688 (enum pipe) cpu_transcoder);
040484af
JB		 1689 }
1690 /* FIXME: assert CPU port conditions for SNB+ */
1691 }
b24e7179 1692
702e7a56 1693 reg = PIPECONF(cpu_transcoder);
b24e7179 1694 val = I915_READ(reg);
00d70b15
CW		 1695 if (val & PIPECONF_ENABLE)
1696 return;
1697
1698 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1699 intel_wait_for_vblank(dev_priv->dev, pipe);
1700}
1701
1702/**
309cfea8 1703 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1704 * @dev_priv: i915 private structure
1705 * @pipe: pipe to disable
1706 *
1707 * Disable @pipe, making sure that various hardware specific requirements
1708 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1709 *
1710 * @pipe should be %PIPE_A or %PIPE_B.
1711 *
1712 * Will wait until the pipe has shut down before returning.
1713 */
1714static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1715 enum pipe pipe)
1716{
702e7a56
PZ		 1717 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1718 pipe);
b24e7179
JB		 1719 int reg;
1720 u32 val;
1721
1722 /*
1723 * Make sure planes won't keep trying to pump pixels to us,
1724 * or we might hang the display.
1725 */
1726 assert_planes_disabled(dev_priv, pipe);
19332d7a 1727 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1728
1729 /* Don't disable pipe A or pipe A PLLs if needed */
1730 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1731 return;
1732
702e7a56 1733 reg = PIPECONF(cpu_transcoder);
b24e7179 1734 val = I915_READ(reg);
00d70b15
CW		 1735 if ((val & PIPECONF_ENABLE) == 0)
1736 return;
1737
1738 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1739 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1740}
1741
d74362c9
KP		 1742/*
1743 * Plane regs are double buffered, going from enabled->disabled needs a
1744 * trigger in order to latch. The display address reg provides this.
1745 */
6f1d69b0 1746void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1747 enum plane plane)
1748{
14f86147
DL		 1749 if (dev_priv->info->gen >= 4)
1750 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1751 else
1752 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1753}
1754
b24e7179
JB		 1755/**
1756 * intel_enable_plane - enable a display plane on a given pipe
1757 * @dev_priv: i915 private structure
1758 * @plane: plane to enable
1759 * @pipe: pipe being fed
1760 *
1761 * Enable @plane on @pipe, making sure that @pipe is running first.
1762 */
1763static void intel_enable_plane(struct drm_i915_private *dev_priv,
1764 enum plane plane, enum pipe pipe)
1765{
1766 int reg;
1767 u32 val;
1768
1769 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1770 assert_pipe_enabled(dev_priv, pipe);
1771
1772 reg = DSPCNTR(plane);
1773 val = I915_READ(reg);
00d70b15
CW		 1774 if (val & DISPLAY_PLANE_ENABLE)
1775 return;
1776
1777 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1778 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1779 intel_wait_for_vblank(dev_priv->dev, pipe);
1780}
1781
b24e7179
JB		 1782/**
1783 * intel_disable_plane - disable a display plane
1784 * @dev_priv: i915 private structure
1785 * @plane: plane to disable
1786 * @pipe: pipe consuming the data
1787 *
1788 * Disable @plane; should be an independent operation.
1789 */
1790static void intel_disable_plane(struct drm_i915_private *dev_priv,
1791 enum plane plane, enum pipe pipe)
1792{
1793 int reg;
1794 u32 val;
1795
1796 reg = DSPCNTR(plane);
1797 val = I915_READ(reg);
00d70b15
CW		 1798 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1799 return;
1800
1801 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1802 intel_flush_display_plane(dev_priv, plane);
1803 intel_wait_for_vblank(dev_priv->dev, pipe);
1804}
1805
693db184
CW		 1806static bool need_vtd_wa(struct drm_device *dev)
1807{
1808#ifdef CONFIG_INTEL_IOMMU
1809 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1810 return true;
1811#endif
1812 return false;
1813}
1814
127bd2ac 1815int
48b956c5 1816intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1817 struct drm_i915_gem_object *obj,
919926ae 1818 struct intel_ring_buffer *pipelined)
6b95a207 1819{
ce453d81 1820 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1821 u32 alignment;
1822 int ret;
1823
05394f39 1824 switch (obj->tiling_mode) {
6b95a207 1825 case I915_TILING_NONE:
534843da
CW		 1826 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1827 alignment = 128 * 1024;
a6c45cf0 1828 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1829 alignment = 4 * 1024;
1830 else
1831 alignment = 64 * 1024;
6b95a207
KH		 1832 break;
1833 case I915_TILING_X:
1834 /* pin() will align the object as required by fence */
1835 alignment = 0;
1836 break;
1837 case I915_TILING_Y:
8bb6e959
DV		 1838 /* Despite that we check this in framebuffer_init userspace can
1839 * screw us over and change the tiling after the fact. Only
1840 * pinned buffers can't change their tiling. */
1841 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1842 return -EINVAL;
1843 default:
1844 BUG();
1845 }
1846
693db184
CW		 1847 /* Note that the w/a also requires 64 PTE of padding following the
1848 * bo. We currently fill all unused PTE with the shadow page and so
1849 * we should always have valid PTE following the scanout preventing
1850 * the VT-d warning.
1851 */
1852 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1853 alignment = 256 * 1024;
1854
ce453d81 1855 dev_priv->mm.interruptible = false;
2da3b9b9 1856 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1857 if (ret)
ce453d81 1858 goto err_interruptible;
6b95a207
KH		 1859
1860 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1861 * fence, whereas 965+ only requires a fence if using
1862 * framebuffer compression. For simplicity, we always install
1863 * a fence as the cost is not that onerous.
1864 */
06d98131 1865 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1866 if (ret)
1867 goto err_unpin;
1690e1eb 1868
9a5a53b3 1869 i915_gem_object_pin_fence(obj);
6b95a207 1870
ce453d81 1871 dev_priv->mm.interruptible = true;
6b95a207 1872 return 0;
48b956c5
CW		 1873
1874err_unpin:
1875 i915_gem_object_unpin(obj);
ce453d81
CW		 1876err_interruptible:
1877 dev_priv->mm.interruptible = true;
48b956c5 1878 return ret;
6b95a207
KH		 1879}
1880
1690e1eb
CW		 1881void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1882{
1883 i915_gem_object_unpin_fence(obj);
1884 i915_gem_object_unpin(obj);
1885}
1886
c2c75131
DV		 1887/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1888 * is assumed to be a power-of-two. */
bc752862
CW		 1889unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1890 unsigned int tiling_mode,
1891 unsigned int cpp,
1892 unsigned int pitch)
c2c75131 1893{
bc752862
CW		 1894 if (tiling_mode != I915_TILING_NONE) {
1895 unsigned int tile_rows, tiles;
c2c75131 1896
bc752862
CW		 1897 tile_rows = *y / 8;
1898 *y %= 8;
c2c75131 1899
bc752862
CW		 1900 tiles = *x / (512/cpp);
1901 *x %= 512/cpp;
1902
1903 return tile_rows * pitch * 8 + tiles * 4096;
1904 } else {
1905 unsigned int offset;
1906
1907 offset = *y * pitch + *x * cpp;
1908 *y = 0;
1909 *x = (offset & 4095) / cpp;
1910 return offset & -4096;
1911 }
c2c75131
DV		 1912}
1913
17638cd6
JB		 1914static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1915 int x, int y)
81255565
JB		 1916{
1917 struct drm_device *dev = crtc->dev;
1918 struct drm_i915_private *dev_priv = dev->dev_private;
1919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1920 struct intel_framebuffer *intel_fb;
05394f39 1921 struct drm_i915_gem_object *obj;
81255565 1922 int plane = intel_crtc->plane;
e506a0c6 1923 unsigned long linear_offset;
81255565 1924 u32 dspcntr;
5eddb70b 1925 u32 reg;
81255565
JB		 1926
1927 switch (plane) {
1928 case 0:
1929 case 1:
1930 break;
1931 default:
84f44ce7 1932 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1933 return -EINVAL;
1934 }
1935
1936 intel_fb = to_intel_framebuffer(fb);
1937 obj = intel_fb->obj;
81255565 1938
5eddb70b
CW		 1939 reg = DSPCNTR(plane);
1940 dspcntr = I915_READ(reg);
81255565
JB		 1941 /* Mask out pixel format bits in case we change it */
1942 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1943 switch (fb->pixel_format) {
1944 case DRM_FORMAT_C8:
81255565
JB		 1945 dspcntr |= DISPPLANE_8BPP;
1946 break;
57779d06
VS		 1947 case DRM_FORMAT_XRGB1555:
1948 case DRM_FORMAT_ARGB1555:
1949 dspcntr |= DISPPLANE_BGRX555;
81255565 1950 break;
57779d06
VS		 1951 case DRM_FORMAT_RGB565:
1952 dspcntr |= DISPPLANE_BGRX565;
1953 break;
1954 case DRM_FORMAT_XRGB8888:
1955 case DRM_FORMAT_ARGB8888:
1956 dspcntr |= DISPPLANE_BGRX888;
1957 break;
1958 case DRM_FORMAT_XBGR8888:
1959 case DRM_FORMAT_ABGR8888:
1960 dspcntr |= DISPPLANE_RGBX888;
1961 break;
1962 case DRM_FORMAT_XRGB2101010:
1963 case DRM_FORMAT_ARGB2101010:
1964 dspcntr |= DISPPLANE_BGRX101010;
1965 break;
1966 case DRM_FORMAT_XBGR2101010:
1967 case DRM_FORMAT_ABGR2101010:
1968 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1969 break;
1970 default:
baba133a 1971 BUG();
81255565 1972 }
57779d06 1973
a6c45cf0 1974 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1975 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1976 dspcntr |= DISPPLANE_TILED;
1977 else
1978 dspcntr &= ~DISPPLANE_TILED;
1979 }
1980
de1aa629
VS		 1981 if (IS_G4X(dev))
1982 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1983
5eddb70b 1984 I915_WRITE(reg, dspcntr);
81255565 1985
e506a0c6 1986 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1987
c2c75131
DV		 1988 if (INTEL_INFO(dev)->gen >= 4) {
1989 intel_crtc->dspaddr_offset =
bc752862
CW		 1990 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1991 fb->bits_per_pixel / 8,
1992 fb->pitches[0]);
c2c75131
DV		 1993 linear_offset -= intel_crtc->dspaddr_offset;
1994 } else {
e506a0c6 1995 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 1996 }
e506a0c6 1997
f343c5f6
BW		 1998 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1999 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2000 fb->pitches[0]);
01f2c773 2001 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2002 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2003 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2004 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2005 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2006 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2007 } else
f343c5f6 2008 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2009 POSTING_READ(reg);
81255565 2010
17638cd6
JB		 2011 return 0;
2012}
2013
2014static int ironlake_update_plane(struct drm_crtc *crtc,
2015 struct drm_framebuffer *fb, int x, int y)
2016{
2017 struct drm_device *dev = crtc->dev;
2018 struct drm_i915_private *dev_priv = dev->dev_private;
2019 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2020 struct intel_framebuffer *intel_fb;
2021 struct drm_i915_gem_object *obj;
2022 int plane = intel_crtc->plane;
e506a0c6 2023 unsigned long linear_offset;
17638cd6
JB		 2024 u32 dspcntr;
2025 u32 reg;
2026
2027 switch (plane) {
2028 case 0:
2029 case 1:
27f8227b 2030 case 2:
17638cd6
JB		 2031 break;
2032 default:
84f44ce7 2033 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2034 return -EINVAL;
2035 }
2036
2037 intel_fb = to_intel_framebuffer(fb);
2038 obj = intel_fb->obj;
2039
2040 reg = DSPCNTR(plane);
2041 dspcntr = I915_READ(reg);
2042 /* Mask out pixel format bits in case we change it */
2043 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2044 switch (fb->pixel_format) {
2045 case DRM_FORMAT_C8:
17638cd6
JB		 2046 dspcntr |= DISPPLANE_8BPP;
2047 break;
57779d06
VS		 2048 case DRM_FORMAT_RGB565:
2049 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2050 break;
57779d06
VS		 2051 case DRM_FORMAT_XRGB8888:
2052 case DRM_FORMAT_ARGB8888:
2053 dspcntr |= DISPPLANE_BGRX888;
2054 break;
2055 case DRM_FORMAT_XBGR8888:
2056 case DRM_FORMAT_ABGR8888:
2057 dspcntr |= DISPPLANE_RGBX888;
2058 break;
2059 case DRM_FORMAT_XRGB2101010:
2060 case DRM_FORMAT_ARGB2101010:
2061 dspcntr |= DISPPLANE_BGRX101010;
2062 break;
2063 case DRM_FORMAT_XBGR2101010:
2064 case DRM_FORMAT_ABGR2101010:
2065 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2066 break;
2067 default:
baba133a 2068 BUG();
17638cd6
JB		 2069 }
2070
2071 if (obj->tiling_mode != I915_TILING_NONE)
2072 dspcntr |= DISPPLANE_TILED;
2073 else
2074 dspcntr &= ~DISPPLANE_TILED;
2075
2076 /* must disable */
2077 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2078
2079 I915_WRITE(reg, dspcntr);
2080
e506a0c6 2081 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2082 intel_crtc->dspaddr_offset =
bc752862
CW		 2083 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2084 fb->bits_per_pixel / 8,
2085 fb->pitches[0]);
c2c75131 2086 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2087
f343c5f6
BW		 2088 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2089 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2090 fb->pitches[0]);
01f2c773 2091 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2092 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2093 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2094 if (IS_HASWELL(dev)) {
2095 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2096 } else {
2097 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2098 I915_WRITE(DSPLINOFF(plane), linear_offset);
2099 }
17638cd6
JB		 2100 POSTING_READ(reg);
2101
2102 return 0;
2103}
2104
2105/* Assume fb object is pinned & idle & fenced and just update base pointers */
2106static int
2107intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2108 int x, int y, enum mode_set_atomic state)
2109{
2110 struct drm_device *dev = crtc->dev;
2111 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2112
6b8e6ed0
CW		 2113 if (dev_priv->display.disable_fbc)
2114 dev_priv->display.disable_fbc(dev);
3dec0095 2115 intel_increase_pllclock(crtc);
81255565 2116
6b8e6ed0 2117 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2118}
2119
96a02917
VS		 2120void intel_display_handle_reset(struct drm_device *dev)
2121{
2122 struct drm_i915_private *dev_priv = dev->dev_private;
2123 struct drm_crtc *crtc;
2124
2125 /*
2126 * Flips in the rings have been nuked by the reset,
2127 * so complete all pending flips so that user space
2128 * will get its events and not get stuck.
2129 *
2130 * Also update the base address of all primary
2131 * planes to the the last fb to make sure we're
2132 * showing the correct fb after a reset.
2133 *
2134 * Need to make two loops over the crtcs so that we
2135 * don't try to grab a crtc mutex before the
2136 * pending_flip_queue really got woken up.
2137 */
2138
2139 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2140 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2141 enum plane plane = intel_crtc->plane;
2142
2143 intel_prepare_page_flip(dev, plane);
2144 intel_finish_page_flip_plane(dev, plane);
2145 }
2146
2147 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2149
2150 mutex_lock(&crtc->mutex);
2151 if (intel_crtc->active)
2152 dev_priv->display.update_plane(crtc, crtc->fb,
2153 crtc->x, crtc->y);
2154 mutex_unlock(&crtc->mutex);
2155 }
2156}
2157
14667a4b
CW		 2158static int
2159intel_finish_fb(struct drm_framebuffer *old_fb)
2160{
2161 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2162 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2163 bool was_interruptible = dev_priv->mm.interruptible;
2164 int ret;
2165
14667a4b
CW		 2166 /* Big Hammer, we also need to ensure that any pending
2167 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2168 * current scanout is retired before unpinning the old
2169 * framebuffer.
2170 *
2171 * This should only fail upon a hung GPU, in which case we
2172 * can safely continue.
2173 */
2174 dev_priv->mm.interruptible = false;
2175 ret = i915_gem_object_finish_gpu(obj);
2176 dev_priv->mm.interruptible = was_interruptible;
2177
2178 return ret;
2179}
2180
198598d0
VS		 2181static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2182{
2183 struct drm_device *dev = crtc->dev;
2184 struct drm_i915_master_private *master_priv;
2185 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2186
2187 if (!dev->primary->master)
2188 return;
2189
2190 master_priv = dev->primary->master->driver_priv;
2191 if (!master_priv->sarea_priv)
2192 return;
2193
2194 switch (intel_crtc->pipe) {
2195 case 0:
2196 master_priv->sarea_priv->pipeA_x = x;
2197 master_priv->sarea_priv->pipeA_y = y;
2198 break;
2199 case 1:
2200 master_priv->sarea_priv->pipeB_x = x;
2201 master_priv->sarea_priv->pipeB_y = y;
2202 break;
2203 default:
2204 break;
2205 }
2206}
2207
5c3b82e2 2208static int
3c4fdcfb 2209intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2210 struct drm_framebuffer *fb)
79e53945
JB		 2211{
2212 struct drm_device *dev = crtc->dev;
6b8e6ed0 2213 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2214 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2215 struct drm_framebuffer *old_fb;
5c3b82e2 2216 int ret;
79e53945
JB		 2217
2218 /* no fb bound */
94352cf9 2219 if (!fb) {
a5071c2f 2220 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2221 return 0;
2222 }
2223
7eb552ae 2224 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2225 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2226 plane_name(intel_crtc->plane),
2227 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2228 return -EINVAL;
79e53945
JB		 2229 }
2230
5c3b82e2 2231 mutex_lock(&dev->struct_mutex);
265db958 2232 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2233 to_intel_framebuffer(fb)->obj,
919926ae 2234 NULL);
5c3b82e2
CW		 2235 if (ret != 0) {
2236 mutex_unlock(&dev->struct_mutex);
a5071c2f 2237 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2238 return ret;
2239 }
79e53945 2240
4d6a3e63
JB		 2241 /* Update pipe size and adjust fitter if needed */
2242 if (i915_fastboot) {
2243 I915_WRITE(PIPESRC(intel_crtc->pipe),
2244 ((crtc->mode.hdisplay - 1) << 16) |
2245 (crtc->mode.vdisplay - 1));
2246 if (!intel_crtc->config.pch_pfit.size &&
2247 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2248 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2249 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2250 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2251 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2252 }
2253 }
2254
94352cf9 2255 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2256 if (ret) {
94352cf9 2257 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2258 mutex_unlock(&dev->struct_mutex);
a5071c2f 2259 DRM_ERROR("failed to update base address\n");
4e6cfefc 2260 return ret;
79e53945 2261 }
3c4fdcfb 2262
94352cf9
DV		 2263 old_fb = crtc->fb;
2264 crtc->fb = fb;
6c4c86f5
DV		 2265 crtc->x = x;
2266 crtc->y = y;
94352cf9 2267
b7f1de28 2268 if (old_fb) {
d7697eea
DV		 2269 if (intel_crtc->active && old_fb != fb)
2270 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2271 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2272 }
652c393a 2273
6b8e6ed0 2274 intel_update_fbc(dev);
5c3b82e2 2275 mutex_unlock(&dev->struct_mutex);
79e53945 2276
198598d0 2277 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2278
2279 return 0;
79e53945
JB		 2280}
2281
5e84e1a4
ZW		 2282static void intel_fdi_normal_train(struct drm_crtc *crtc)
2283{
2284 struct drm_device *dev = crtc->dev;
2285 struct drm_i915_private *dev_priv = dev->dev_private;
2286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2287 int pipe = intel_crtc->pipe;
2288 u32 reg, temp;
2289
2290 /* enable normal train */
2291 reg = FDI_TX_CTL(pipe);
2292 temp = I915_READ(reg);
61e499bf 2293 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2294 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2295 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2296 } else {
2297 temp &= ~FDI_LINK_TRAIN_NONE;
2298 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2299 }
5e84e1a4
ZW		 2300 I915_WRITE(reg, temp);
2301
2302 reg = FDI_RX_CTL(pipe);
2303 temp = I915_READ(reg);
2304 if (HAS_PCH_CPT(dev)) {
2305 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2306 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2307 } else {
2308 temp &= ~FDI_LINK_TRAIN_NONE;
2309 temp |= FDI_LINK_TRAIN_NONE;
2310 }
2311 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2312
2313 /* wait one idle pattern time */
2314 POSTING_READ(reg);
2315 udelay(1000);
357555c0
JB		 2316
2317 /* IVB wants error correction enabled */
2318 if (IS_IVYBRIDGE(dev))
2319 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2320 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2321}
2322
1e833f40
DV		 2323static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2324{
2325 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2326}
2327
01a415fd
DV		 2328static void ivb_modeset_global_resources(struct drm_device *dev)
2329{
2330 struct drm_i915_private *dev_priv = dev->dev_private;
2331 struct intel_crtc *pipe_B_crtc =
2332 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2333 struct intel_crtc *pipe_C_crtc =
2334 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2335 uint32_t temp;
2336
1e833f40
DV		 2337 /*
2338 * When everything is off disable fdi C so that we could enable fdi B
2339 * with all lanes. Note that we don't care about enabled pipes without
2340 * an enabled pch encoder.
2341 */
2342 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2343 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2344 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2345 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2346
2347 temp = I915_READ(SOUTH_CHICKEN1);
2348 temp &= ~FDI_BC_BIFURCATION_SELECT;
2349 DRM_DEBUG_KMS("disabling fdi C rx\n");
2350 I915_WRITE(SOUTH_CHICKEN1, temp);
2351 }
2352}
2353
8db9d77b
ZW		 2354/* The FDI link training functions for ILK/Ibexpeak. */
2355static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2356{
2357 struct drm_device *dev = crtc->dev;
2358 struct drm_i915_private *dev_priv = dev->dev_private;
2359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2360 int pipe = intel_crtc->pipe;
0fc932b8 2361 int plane = intel_crtc->plane;
5eddb70b 2362 u32 reg, temp, tries;
8db9d77b 2363
0fc932b8
JB		 2364 /* FDI needs bits from pipe & plane first */
2365 assert_pipe_enabled(dev_priv, pipe);
2366 assert_plane_enabled(dev_priv, plane);
2367
e1a44743
AJ		 2368 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2369 for train result */
5eddb70b
CW		 2370 reg = FDI_RX_IMR(pipe);
2371 temp = I915_READ(reg);
e1a44743
AJ		 2372 temp &= ~FDI_RX_SYMBOL_LOCK;
2373 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2374 I915_WRITE(reg, temp);
2375 I915_READ(reg);
e1a44743
AJ		 2376 udelay(150);
2377
8db9d77b 2378 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2379 reg = FDI_TX_CTL(pipe);
2380 temp = I915_READ(reg);
627eb5a3
DV		 2381 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2382 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2383 temp &= ~FDI_LINK_TRAIN_NONE;
2384 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2385 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2386
5eddb70b
CW		 2387 reg = FDI_RX_CTL(pipe);
2388 temp = I915_READ(reg);
8db9d77b
ZW		 2389 temp &= ~FDI_LINK_TRAIN_NONE;
2390 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2391 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2392
2393 POSTING_READ(reg);
8db9d77b
ZW		 2394 udelay(150);
2395
5b2adf89 2396 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2397 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2398 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2399 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2400
5eddb70b 2401 reg = FDI_RX_IIR(pipe);
e1a44743 2402 for (tries = 0; tries < 5; tries++) {
5eddb70b 2403 temp = I915_READ(reg);
8db9d77b
ZW		 2404 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2405
2406 if ((temp & FDI_RX_BIT_LOCK)) {
2407 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2408 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2409 break;
2410 }
8db9d77b 2411 }
e1a44743 2412 if (tries == 5)
5eddb70b 2413 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2414
2415 /* Train 2 */
5eddb70b
CW		 2416 reg = FDI_TX_CTL(pipe);
2417 temp = I915_READ(reg);
8db9d77b
ZW		 2418 temp &= ~FDI_LINK_TRAIN_NONE;
2419 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2420 I915_WRITE(reg, temp);
8db9d77b 2421
5eddb70b
CW		 2422 reg = FDI_RX_CTL(pipe);
2423 temp = I915_READ(reg);
8db9d77b
ZW		 2424 temp &= ~FDI_LINK_TRAIN_NONE;
2425 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2426 I915_WRITE(reg, temp);
8db9d77b 2427
5eddb70b
CW		 2428 POSTING_READ(reg);
2429 udelay(150);
8db9d77b 2430
5eddb70b 2431 reg = FDI_RX_IIR(pipe);
e1a44743 2432 for (tries = 0; tries < 5; tries++) {
5eddb70b 2433 temp = I915_READ(reg);
8db9d77b
ZW		 2434 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2435
2436 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2437 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2438 DRM_DEBUG_KMS("FDI train 2 done.\n");
2439 break;
2440 }
8db9d77b 2441 }
e1a44743 2442 if (tries == 5)
5eddb70b 2443 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2444
2445 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2446
8db9d77b
ZW		 2447}
2448
0206e353 2449static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2450 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2451 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2452 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2453 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2454};
2455
2456/* The FDI link training functions for SNB/Cougarpoint. */
2457static void gen6_fdi_link_train(struct drm_crtc *crtc)
2458{
2459 struct drm_device *dev = crtc->dev;
2460 struct drm_i915_private *dev_priv = dev->dev_private;
2461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2462 int pipe = intel_crtc->pipe;
fa37d39e 2463 u32 reg, temp, i, retry;
8db9d77b 2464
e1a44743
AJ		 2465 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2466 for train result */
5eddb70b
CW		 2467 reg = FDI_RX_IMR(pipe);
2468 temp = I915_READ(reg);
e1a44743
AJ		 2469 temp &= ~FDI_RX_SYMBOL_LOCK;
2470 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2471 I915_WRITE(reg, temp);
2472
2473 POSTING_READ(reg);
e1a44743
AJ		 2474 udelay(150);
2475
8db9d77b 2476 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2477 reg = FDI_TX_CTL(pipe);
2478 temp = I915_READ(reg);
627eb5a3
DV		 2479 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2480 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2481 temp &= ~FDI_LINK_TRAIN_NONE;
2482 temp |= FDI_LINK_TRAIN_PATTERN_1;
2483 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2484 /* SNB-B */
2485 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2486 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2487
d74cf324
DV		 2488 I915_WRITE(FDI_RX_MISC(pipe),
2489 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2490
5eddb70b
CW		 2491 reg = FDI_RX_CTL(pipe);
2492 temp = I915_READ(reg);
8db9d77b
ZW		 2493 if (HAS_PCH_CPT(dev)) {
2494 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2495 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2496 } else {
2497 temp &= ~FDI_LINK_TRAIN_NONE;
2498 temp |= FDI_LINK_TRAIN_PATTERN_1;
2499 }
5eddb70b
CW		 2500 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2501
2502 POSTING_READ(reg);
8db9d77b
ZW		 2503 udelay(150);
2504
0206e353 2505 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2506 reg = FDI_TX_CTL(pipe);
2507 temp = I915_READ(reg);
8db9d77b
ZW		 2508 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2509 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2510 I915_WRITE(reg, temp);
2511
2512 POSTING_READ(reg);
8db9d77b
ZW		 2513 udelay(500);
2514
fa37d39e
SP		 2515 for (retry = 0; retry < 5; retry++) {
2516 reg = FDI_RX_IIR(pipe);
2517 temp = I915_READ(reg);
2518 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2519 if (temp & FDI_RX_BIT_LOCK) {
2520 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2521 DRM_DEBUG_KMS("FDI train 1 done.\n");
2522 break;
2523 }
2524 udelay(50);
8db9d77b 2525 }
fa37d39e
SP		 2526 if (retry < 5)
2527 break;
8db9d77b
ZW		 2528 }
2529 if (i == 4)
5eddb70b 2530 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2531
2532 /* Train 2 */
5eddb70b
CW		 2533 reg = FDI_TX_CTL(pipe);
2534 temp = I915_READ(reg);
8db9d77b
ZW		 2535 temp &= ~FDI_LINK_TRAIN_NONE;
2536 temp |= FDI_LINK_TRAIN_PATTERN_2;
2537 if (IS_GEN6(dev)) {
2538 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2539 /* SNB-B */
2540 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2541 }
5eddb70b 2542 I915_WRITE(reg, temp);
8db9d77b 2543
5eddb70b
CW		 2544 reg = FDI_RX_CTL(pipe);
2545 temp = I915_READ(reg);
8db9d77b
ZW		 2546 if (HAS_PCH_CPT(dev)) {
2547 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2548 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2549 } else {
2550 temp &= ~FDI_LINK_TRAIN_NONE;
2551 temp |= FDI_LINK_TRAIN_PATTERN_2;
2552 }
5eddb70b
CW		 2553 I915_WRITE(reg, temp);
2554
2555 POSTING_READ(reg);
8db9d77b
ZW		 2556 udelay(150);
2557
0206e353 2558 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2559 reg = FDI_TX_CTL(pipe);
2560 temp = I915_READ(reg);
8db9d77b
ZW		 2561 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2562 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2563 I915_WRITE(reg, temp);
2564
2565 POSTING_READ(reg);
8db9d77b
ZW		 2566 udelay(500);
2567
fa37d39e
SP		 2568 for (retry = 0; retry < 5; retry++) {
2569 reg = FDI_RX_IIR(pipe);
2570 temp = I915_READ(reg);
2571 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2572 if (temp & FDI_RX_SYMBOL_LOCK) {
2573 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2574 DRM_DEBUG_KMS("FDI train 2 done.\n");
2575 break;
2576 }
2577 udelay(50);
8db9d77b 2578 }
fa37d39e
SP		 2579 if (retry < 5)
2580 break;
8db9d77b
ZW		 2581 }
2582 if (i == 4)
5eddb70b 2583 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2584
2585 DRM_DEBUG_KMS("FDI train done.\n");
2586}
2587
357555c0
JB		 2588/* Manual link training for Ivy Bridge A0 parts */
2589static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2590{
2591 struct drm_device *dev = crtc->dev;
2592 struct drm_i915_private *dev_priv = dev->dev_private;
2593 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2594 int pipe = intel_crtc->pipe;
2595 u32 reg, temp, i;
2596
2597 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2598 for train result */
2599 reg = FDI_RX_IMR(pipe);
2600 temp = I915_READ(reg);
2601 temp &= ~FDI_RX_SYMBOL_LOCK;
2602 temp &= ~FDI_RX_BIT_LOCK;
2603 I915_WRITE(reg, temp);
2604
2605 POSTING_READ(reg);
2606 udelay(150);
2607
01a415fd
DV		 2608 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2609 I915_READ(FDI_RX_IIR(pipe)));
2610
357555c0
JB		 2611 /* enable CPU FDI TX and PCH FDI RX */
2612 reg = FDI_TX_CTL(pipe);
2613 temp = I915_READ(reg);
627eb5a3
DV		 2614 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2615 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2616 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2617 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2618 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2619 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2620 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2621 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2622
d74cf324
DV		 2623 I915_WRITE(FDI_RX_MISC(pipe),
2624 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2625
357555c0
JB		 2626 reg = FDI_RX_CTL(pipe);
2627 temp = I915_READ(reg);
2628 temp &= ~FDI_LINK_TRAIN_AUTO;
2629 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2630 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2631 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2632 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2633
2634 POSTING_READ(reg);
2635 udelay(150);
2636
0206e353 2637 for (i = 0; i < 4; i++) {
357555c0
JB		 2638 reg = FDI_TX_CTL(pipe);
2639 temp = I915_READ(reg);
2640 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2641 temp |= snb_b_fdi_train_param[i];
2642 I915_WRITE(reg, temp);
2643
2644 POSTING_READ(reg);
2645 udelay(500);
2646
2647 reg = FDI_RX_IIR(pipe);
2648 temp = I915_READ(reg);
2649 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2650
2651 if (temp & FDI_RX_BIT_LOCK ||
2652 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2653 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2654 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2655 break;
2656 }
2657 }
2658 if (i == 4)
2659 DRM_ERROR("FDI train 1 fail!\n");
2660
2661 /* Train 2 */
2662 reg = FDI_TX_CTL(pipe);
2663 temp = I915_READ(reg);
2664 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2665 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2666 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2667 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2668 I915_WRITE(reg, temp);
2669
2670 reg = FDI_RX_CTL(pipe);
2671 temp = I915_READ(reg);
2672 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2673 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2674 I915_WRITE(reg, temp);
2675
2676 POSTING_READ(reg);
2677 udelay(150);
2678
0206e353 2679 for (i = 0; i < 4; i++) {
357555c0
JB		 2680 reg = FDI_TX_CTL(pipe);
2681 temp = I915_READ(reg);
2682 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2683 temp |= snb_b_fdi_train_param[i];
2684 I915_WRITE(reg, temp);
2685
2686 POSTING_READ(reg);
2687 udelay(500);
2688
2689 reg = FDI_RX_IIR(pipe);
2690 temp = I915_READ(reg);
2691 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2692
2693 if (temp & FDI_RX_SYMBOL_LOCK) {
2694 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2695 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2696 break;
2697 }
2698 }
2699 if (i == 4)
2700 DRM_ERROR("FDI train 2 fail!\n");
2701
2702 DRM_DEBUG_KMS("FDI train done.\n");
2703}
2704
88cefb6c 2705static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2706{
88cefb6c 2707 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2708 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2709 int pipe = intel_crtc->pipe;
5eddb70b 2710 u32 reg, temp;
79e53945 2711
c64e311e 2712
c98e9dcf 2713 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2714 reg = FDI_RX_CTL(pipe);
2715 temp = I915_READ(reg);
627eb5a3
DV		 2716 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2717 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2718 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2719 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2720
2721 POSTING_READ(reg);
c98e9dcf
JB		 2722 udelay(200);
2723
2724 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2725 temp = I915_READ(reg);
2726 I915_WRITE(reg, temp | FDI_PCDCLK);
2727
2728 POSTING_READ(reg);
c98e9dcf
JB		 2729 udelay(200);
2730
20749730
PZ		 2731 /* Enable CPU FDI TX PLL, always on for Ironlake */
2732 reg = FDI_TX_CTL(pipe);
2733 temp = I915_READ(reg);
2734 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2735 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2736
20749730
PZ		 2737 POSTING_READ(reg);
2738 udelay(100);
6be4a607 2739 }
0e23b99d
JB		 2740}
2741
88cefb6c
DV		 2742static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2743{
2744 struct drm_device *dev = intel_crtc->base.dev;
2745 struct drm_i915_private *dev_priv = dev->dev_private;
2746 int pipe = intel_crtc->pipe;
2747 u32 reg, temp;
2748
2749 /* Switch from PCDclk to Rawclk */
2750 reg = FDI_RX_CTL(pipe);
2751 temp = I915_READ(reg);
2752 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2753
2754 /* Disable CPU FDI TX PLL */
2755 reg = FDI_TX_CTL(pipe);
2756 temp = I915_READ(reg);
2757 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2758
2759 POSTING_READ(reg);
2760 udelay(100);
2761
2762 reg = FDI_RX_CTL(pipe);
2763 temp = I915_READ(reg);
2764 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2765
2766 /* Wait for the clocks to turn off. */
2767 POSTING_READ(reg);
2768 udelay(100);
2769}
2770
0fc932b8
JB		 2771static void ironlake_fdi_disable(struct drm_crtc *crtc)
2772{
2773 struct drm_device *dev = crtc->dev;
2774 struct drm_i915_private *dev_priv = dev->dev_private;
2775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2776 int pipe = intel_crtc->pipe;
2777 u32 reg, temp;
2778
2779 /* disable CPU FDI tx and PCH FDI rx */
2780 reg = FDI_TX_CTL(pipe);
2781 temp = I915_READ(reg);
2782 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2783 POSTING_READ(reg);
2784
2785 reg = FDI_RX_CTL(pipe);
2786 temp = I915_READ(reg);
2787 temp &= ~(0x7 << 16);
dfd07d72 2788 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2789 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2790
2791 POSTING_READ(reg);
2792 udelay(100);
2793
2794 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2795 if (HAS_PCH_IBX(dev)) {
2796 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2797 }
0fc932b8
JB		 2798
2799 /* still set train pattern 1 */
2800 reg = FDI_TX_CTL(pipe);
2801 temp = I915_READ(reg);
2802 temp &= ~FDI_LINK_TRAIN_NONE;
2803 temp |= FDI_LINK_TRAIN_PATTERN_1;
2804 I915_WRITE(reg, temp);
2805
2806 reg = FDI_RX_CTL(pipe);
2807 temp = I915_READ(reg);
2808 if (HAS_PCH_CPT(dev)) {
2809 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2810 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2811 } else {
2812 temp &= ~FDI_LINK_TRAIN_NONE;
2813 temp |= FDI_LINK_TRAIN_PATTERN_1;
2814 }
2815 /* BPC in FDI rx is consistent with that in PIPECONF */
2816 temp &= ~(0x07 << 16);
dfd07d72 2817 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2818 I915_WRITE(reg, temp);
2819
2820 POSTING_READ(reg);
2821 udelay(100);
2822}
2823
5bb61643
CW		 2824static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2825{
2826 struct drm_device *dev = crtc->dev;
2827 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2828 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2829 unsigned long flags;
2830 bool pending;
2831
10d83730
VS		 2832 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2833 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2834 return false;
2835
2836 spin_lock_irqsave(&dev->event_lock, flags);
2837 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2838 spin_unlock_irqrestore(&dev->event_lock, flags);
2839
2840 return pending;
2841}
2842
e6c3a2a6
CW		 2843static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2844{
0f91128d 2845 struct drm_device *dev = crtc->dev;
5bb61643 2846 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2847
2848 if (crtc->fb == NULL)
2849 return;
2850
2c10d571
DV		 2851 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2852
5bb61643
CW		 2853 wait_event(dev_priv->pending_flip_queue,
2854 !intel_crtc_has_pending_flip(crtc));
2855
0f91128d
CW		 2856 mutex_lock(&dev->struct_mutex);
2857 intel_finish_fb(crtc->fb);
2858 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2859}
2860
e615efe4
ED		 2861/* Program iCLKIP clock to the desired frequency */
2862static void lpt_program_iclkip(struct drm_crtc *crtc)
2863{
2864 struct drm_device *dev = crtc->dev;
2865 struct drm_i915_private *dev_priv = dev->dev_private;
2866 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2867 u32 temp;
2868
09153000
DV		 2869 mutex_lock(&dev_priv->dpio_lock);
2870
e615efe4
ED		 2871 /* It is necessary to ungate the pixclk gate prior to programming
2872 * the divisors, and gate it back when it is done.
2873 */
2874 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2875
2876 /* Disable SSCCTL */
2877 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2878 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2879 SBI_SSCCTL_DISABLE,
2880 SBI_ICLK);
e615efe4
ED		 2881
2882 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2883 if (crtc->mode.clock == 20000) {
2884 auxdiv = 1;
2885 divsel = 0x41;
2886 phaseinc = 0x20;
2887 } else {
2888 /* The iCLK virtual clock root frequency is in MHz,
2889 * but the crtc->mode.clock in in KHz. To get the divisors,
2890 * it is necessary to divide one by another, so we
2891 * convert the virtual clock precision to KHz here for higher
2892 * precision.
2893 */
2894 u32 iclk_virtual_root_freq = 172800 * 1000;
2895 u32 iclk_pi_range = 64;
2896 u32 desired_divisor, msb_divisor_value, pi_value;
2897
2898 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2899 msb_divisor_value = desired_divisor / iclk_pi_range;
2900 pi_value = desired_divisor % iclk_pi_range;
2901
2902 auxdiv = 0;
2903 divsel = msb_divisor_value - 2;
2904 phaseinc = pi_value;
2905 }
2906
2907 /* This should not happen with any sane values */
2908 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2909 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2910 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2911 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2912
2913 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2914 crtc->mode.clock,
2915 auxdiv,
2916 divsel,
2917 phasedir,
2918 phaseinc);
2919
2920 /* Program SSCDIVINTPHASE6 */
988d6ee8 2921 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2922 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2923 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2924 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2925 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2926 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2927 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2928 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2929
2930 /* Program SSCAUXDIV */
988d6ee8 2931 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2932 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2933 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2934 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2935
2936 /* Enable modulator and associated divider */
988d6ee8 2937 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2938 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2939 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2940
2941 /* Wait for initialization time */
2942 udelay(24);
2943
2944 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2945
2946 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2947}
2948
275f01b2
DV		 2949static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2950 enum pipe pch_transcoder)
2951{
2952 struct drm_device *dev = crtc->base.dev;
2953 struct drm_i915_private *dev_priv = dev->dev_private;
2954 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2955
2956 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2957 I915_READ(HTOTAL(cpu_transcoder)));
2958 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2959 I915_READ(HBLANK(cpu_transcoder)));
2960 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2961 I915_READ(HSYNC(cpu_transcoder)));
2962
2963 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2964 I915_READ(VTOTAL(cpu_transcoder)));
2965 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2966 I915_READ(VBLANK(cpu_transcoder)));
2967 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2968 I915_READ(VSYNC(cpu_transcoder)));
2969 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2970 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2971}
2972
f67a559d
JB		 2973/*
2974 * Enable PCH resources required for PCH ports:
2975 * - PCH PLLs
2976 * - FDI training & RX/TX
2977 * - update transcoder timings
2978 * - DP transcoding bits
2979 * - transcoder
2980 */
2981static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2982{
2983 struct drm_device *dev = crtc->dev;
2984 struct drm_i915_private *dev_priv = dev->dev_private;
2985 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2986 int pipe = intel_crtc->pipe;
ee7b9f93 2987 u32 reg, temp;
2c07245f 2988
ab9412ba 2989 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2990
cd986abb
DV		 2991 /* Write the TU size bits before fdi link training, so that error
2992 * detection works. */
2993 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2994 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2995
c98e9dcf 2996 /* For PCH output, training FDI link */
674cf967 2997 dev_priv->display.fdi_link_train(crtc);
2c07245f 2998
572deb37
DV		 2999 /* XXX: pch pll's can be enabled any time before we enable the PCH
3000 * transcoder, and we actually should do this to not upset any PCH
3001 * transcoder that already use the clock when we share it.
3002 *
e72f9fbf
DV		 3003 * Note that enable_shared_dpll tries to do the right thing, but
3004 * get_shared_dpll unconditionally resets the pll - we need that to have
3005 * the right LVDS enable sequence. */
3006 ironlake_enable_shared_dpll(intel_crtc);
6f13b7b5 3007
303b81e0 3008 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3009 u32 sel;
4b645f14 3010
c98e9dcf 3011 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3012 temp |= TRANS_DPLL_ENABLE(pipe);
3013 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3014 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3015 temp |= sel;
3016 else
3017 temp &= ~sel;
c98e9dcf 3018 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3019 }
5eddb70b 3020
d9b6cb56
JB		 3021 /* set transcoder timing, panel must allow it */
3022 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3023 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3024
303b81e0 3025 intel_fdi_normal_train(crtc);
5e84e1a4 3026
c98e9dcf
JB		 3027 /* For PCH DP, enable TRANS_DP_CTL */
3028 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3029 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3030 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3031 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3032 reg = TRANS_DP_CTL(pipe);
3033 temp = I915_READ(reg);
3034 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3035 TRANS_DP_SYNC_MASK |
3036 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3037 temp |= (TRANS_DP_OUTPUT_ENABLE |
3038 TRANS_DP_ENH_FRAMING);
9325c9f0 3039 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3040
3041 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3042 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3043 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3044 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3045
3046 switch (intel_trans_dp_port_sel(crtc)) {
3047 case PCH_DP_B:
5eddb70b 3048 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3049 break;
3050 case PCH_DP_C:
5eddb70b 3051 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3052 break;
3053 case PCH_DP_D:
5eddb70b 3054 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3055 break;
3056 default:
e95d41e1 3057 BUG();
32f9d658 3058 }
2c07245f 3059
5eddb70b 3060 I915_WRITE(reg, temp);
6be4a607 3061 }
b52eb4dc 3062
b8a4f404 3063 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3064}
3065
1507e5bd
PZ		 3066static void lpt_pch_enable(struct drm_crtc *crtc)
3067{
3068 struct drm_device *dev = crtc->dev;
3069 struct drm_i915_private *dev_priv = dev->dev_private;
3070 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3071 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3072
ab9412ba 3073 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3074
8c52b5e8 3075 lpt_program_iclkip(crtc);
1507e5bd 3076
0540e488 3077 /* Set transcoder timing. */
275f01b2 3078 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3079
937bb610 3080 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3081}
3082
e2b78267 3083static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3084{
e2b78267 3085 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3086
3087 if (pll == NULL)
3088 return;
3089
3090 if (pll->refcount == 0) {
46edb027 3091 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3092 return;
3093 }
3094
f4a091c7
DV		 3095 if (--pll->refcount == 0) {
3096 WARN_ON(pll->on);
3097 WARN_ON(pll->active);
3098 }
3099
a43f6e0f 3100 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3101}
3102
b89a1d39 3103static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3104{
e2b78267
DV		 3105 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3106 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3107 enum intel_dpll_id i;
ee7b9f93 3108
ee7b9f93 3109 if (pll) {
46edb027
DV		 3110 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3111 crtc->base.base.id, pll->name);
e2b78267 3112 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3113 }
3114
98b6bd99
DV		 3115 if (HAS_PCH_IBX(dev_priv->dev)) {
3116 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3117 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3118 pll = &dev_priv->shared_dplls[i];
98b6bd99 3119
46edb027
DV		 3120 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3121 crtc->base.base.id, pll->name);
98b6bd99
DV		 3122
3123 goto found;
3124 }
3125
e72f9fbf
DV		 3126 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3127 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3128
3129 /* Only want to check enabled timings first */
3130 if (pll->refcount == 0)
3131 continue;
3132
b89a1d39
DV		 3133 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3134 sizeof(pll->hw_state)) == 0) {
46edb027 3135 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3136 crtc->base.base.id,
46edb027 3137 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3138
3139 goto found;
3140 }
3141 }
3142
3143 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3144 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3145 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3146 if (pll->refcount == 0) {
46edb027
DV		 3147 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3148 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3149 goto found;
3150 }
3151 }
3152
3153 return NULL;
3154
3155found:
a43f6e0f 3156 crtc->config.shared_dpll = i;
46edb027
DV		 3157 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3158 pipe_name(crtc->pipe));
ee7b9f93 3159
cdbd2316 3160 if (pll->active == 0) {
66e985c0
DV		 3161 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3162 sizeof(pll->hw_state));
3163
46edb027 3164 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3165 WARN_ON(pll->on);
e9d6944e 3166 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3167
15bdd4cf 3168 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3169 }
3170 pll->refcount++;
e04c7350 3171
ee7b9f93
JB		 3172 return pll;
3173}
3174
a1520318 3175static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3176{
3177 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3178 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3179 u32 temp;
3180
3181 temp = I915_READ(dslreg);
3182 udelay(500);
3183 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3184 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3185 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3186 }
3187}
3188
b074cec8
JB		 3189static void ironlake_pfit_enable(struct intel_crtc *crtc)
3190{
3191 struct drm_device *dev = crtc->base.dev;
3192 struct drm_i915_private *dev_priv = dev->dev_private;
3193 int pipe = crtc->pipe;
3194
0ef37f3f 3195 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3196 /* Force use of hard-coded filter coefficients
3197 * as some pre-programmed values are broken,
3198 * e.g. x201.
3199 */
3200 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3201 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3202 PF_PIPE_SEL_IVB(pipe));
3203 else
3204 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3205 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3206 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3207 }
3208}
3209
bb53d4ae
VS		 3210static void intel_enable_planes(struct drm_crtc *crtc)
3211{
3212 struct drm_device *dev = crtc->dev;
3213 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3214 struct intel_plane *intel_plane;
3215
3216 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3217 if (intel_plane->pipe == pipe)
3218 intel_plane_restore(&intel_plane->base);
3219}
3220
3221static void intel_disable_planes(struct drm_crtc *crtc)
3222{
3223 struct drm_device *dev = crtc->dev;
3224 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3225 struct intel_plane *intel_plane;
3226
3227 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3228 if (intel_plane->pipe == pipe)
3229 intel_plane_disable(&intel_plane->base);
3230}
3231
f67a559d
JB		 3232static void ironlake_crtc_enable(struct drm_crtc *crtc)
3233{
3234 struct drm_device *dev = crtc->dev;
3235 struct drm_i915_private *dev_priv = dev->dev_private;
3236 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3237 struct intel_encoder *encoder;
f67a559d
JB		 3238 int pipe = intel_crtc->pipe;
3239 int plane = intel_crtc->plane;
f67a559d 3240
08a48469
DV		 3241 WARN_ON(!crtc->enabled);
3242
f67a559d
JB		 3243 if (intel_crtc->active)
3244 return;
3245
3246 intel_crtc->active = true;
8664281b
PZ		 3247
3248 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3249 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3250
f67a559d
JB		 3251 intel_update_watermarks(dev);
3252
f6736a1a 3253 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3254 if (encoder->pre_enable)
3255 encoder->pre_enable(encoder);
f67a559d 3256
5bfe2ac0 3257 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3258 /* Note: FDI PLL enabling _must_ be done before we enable the
3259 * cpu pipes, hence this is separate from all the other fdi/pch
3260 * enabling. */
88cefb6c 3261 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3262 } else {
3263 assert_fdi_tx_disabled(dev_priv, pipe);
3264 assert_fdi_rx_disabled(dev_priv, pipe);
3265 }
f67a559d 3266
b074cec8 3267 ironlake_pfit_enable(intel_crtc);
f67a559d 3268
9c54c0dd
JB		 3269 /*
3270 * On ILK+ LUT must be loaded before the pipe is running but with
3271 * clocks enabled
3272 */
3273 intel_crtc_load_lut(crtc);
3274
5bfe2ac0
DV		 3275 intel_enable_pipe(dev_priv, pipe,
3276 intel_crtc->config.has_pch_encoder);
f67a559d 3277 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3278 intel_enable_planes(crtc);
5c38d48c 3279 intel_crtc_update_cursor(crtc, true);
f67a559d 3280
5bfe2ac0 3281 if (intel_crtc->config.has_pch_encoder)
f67a559d 3282 ironlake_pch_enable(crtc);
c98e9dcf 3283
d1ebd816 3284 mutex_lock(&dev->struct_mutex);
bed4a673 3285 intel_update_fbc(dev);
d1ebd816
BW		 3286 mutex_unlock(&dev->struct_mutex);
3287
fa5c73b1
DV		 3288 for_each_encoder_on_crtc(dev, crtc, encoder)
3289 encoder->enable(encoder);
61b77ddd
DV		 3290
3291 if (HAS_PCH_CPT(dev))
a1520318 3292 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3293
3294 /*
3295 * There seems to be a race in PCH platform hw (at least on some
3296 * outputs) where an enabled pipe still completes any pageflip right
3297 * away (as if the pipe is off) instead of waiting for vblank. As soon
3298 * as the first vblank happend, everything works as expected. Hence just
3299 * wait for one vblank before returning to avoid strange things
3300 * happening.
3301 */
3302 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3303}
3304
42db64ef
PZ		 3305/* IPS only exists on ULT machines and is tied to pipe A. */
3306static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3307{
f5adf94e 3308 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3309}
3310
3311static void hsw_enable_ips(struct intel_crtc *crtc)
3312{
3313 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3314
3315 if (!crtc->config.ips_enabled)
3316 return;
3317
3318 /* We can only enable IPS after we enable a plane and wait for a vblank.
3319 * We guarantee that the plane is enabled by calling intel_enable_ips
3320 * only after intel_enable_plane. And intel_enable_plane already waits
3321 * for a vblank, so all we need to do here is to enable the IPS bit. */
3322 assert_plane_enabled(dev_priv, crtc->plane);
3323 I915_WRITE(IPS_CTL, IPS_ENABLE);
3324}
3325
3326static void hsw_disable_ips(struct intel_crtc *crtc)
3327{
3328 struct drm_device *dev = crtc->base.dev;
3329 struct drm_i915_private *dev_priv = dev->dev_private;
3330
3331 if (!crtc->config.ips_enabled)
3332 return;
3333
3334 assert_plane_enabled(dev_priv, crtc->plane);
3335 I915_WRITE(IPS_CTL, 0);
3336
3337 /* We need to wait for a vblank before we can disable the plane. */
3338 intel_wait_for_vblank(dev, crtc->pipe);
3339}
3340
4f771f10
PZ		 3341static void haswell_crtc_enable(struct drm_crtc *crtc)
3342{
3343 struct drm_device *dev = crtc->dev;
3344 struct drm_i915_private *dev_priv = dev->dev_private;
3345 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3346 struct intel_encoder *encoder;
3347 int pipe = intel_crtc->pipe;
3348 int plane = intel_crtc->plane;
4f771f10
PZ		 3349
3350 WARN_ON(!crtc->enabled);
3351
3352 if (intel_crtc->active)
3353 return;
3354
3355 intel_crtc->active = true;
8664281b
PZ		 3356
3357 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3358 if (intel_crtc->config.has_pch_encoder)
3359 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3360
4f771f10
PZ		 3361 intel_update_watermarks(dev);
3362
5bfe2ac0 3363 if (intel_crtc->config.has_pch_encoder)
04945641 3364 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3365
3366 for_each_encoder_on_crtc(dev, crtc, encoder)
3367 if (encoder->pre_enable)
3368 encoder->pre_enable(encoder);
3369
1f544388 3370 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3371
b074cec8 3372 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3373
3374 /*
3375 * On ILK+ LUT must be loaded before the pipe is running but with
3376 * clocks enabled
3377 */
3378 intel_crtc_load_lut(crtc);
3379
1f544388 3380 intel_ddi_set_pipe_settings(crtc);
8228c251 3381 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3382
5bfe2ac0
DV		 3383 intel_enable_pipe(dev_priv, pipe,
3384 intel_crtc->config.has_pch_encoder);
4f771f10 3385 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3386 intel_enable_planes(crtc);
5c38d48c 3387 intel_crtc_update_cursor(crtc, true);
4f771f10 3388
42db64ef
PZ		 3389 hsw_enable_ips(intel_crtc);
3390
5bfe2ac0 3391 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3392 lpt_pch_enable(crtc);
4f771f10
PZ		 3393
3394 mutex_lock(&dev->struct_mutex);
3395 intel_update_fbc(dev);
3396 mutex_unlock(&dev->struct_mutex);
3397
4f771f10
PZ		 3398 for_each_encoder_on_crtc(dev, crtc, encoder)
3399 encoder->enable(encoder);
3400
4f771f10
PZ		 3401 /*
3402 * There seems to be a race in PCH platform hw (at least on some
3403 * outputs) where an enabled pipe still completes any pageflip right
3404 * away (as if the pipe is off) instead of waiting for vblank. As soon
3405 * as the first vblank happend, everything works as expected. Hence just
3406 * wait for one vblank before returning to avoid strange things
3407 * happening.
3408 */
3409 intel_wait_for_vblank(dev, intel_crtc->pipe);
3410}
3411
3f8dce3a
DV		 3412static void ironlake_pfit_disable(struct intel_crtc *crtc)
3413{
3414 struct drm_device *dev = crtc->base.dev;
3415 struct drm_i915_private *dev_priv = dev->dev_private;
3416 int pipe = crtc->pipe;
3417
3418 /* To avoid upsetting the power well on haswell only disable the pfit if
3419 * it's in use. The hw state code will make sure we get this right. */
3420 if (crtc->config.pch_pfit.size) {
3421 I915_WRITE(PF_CTL(pipe), 0);
3422 I915_WRITE(PF_WIN_POS(pipe), 0);
3423 I915_WRITE(PF_WIN_SZ(pipe), 0);
3424 }
3425}
3426
6be4a607
JB		 3427static void ironlake_crtc_disable(struct drm_crtc *crtc)
3428{
3429 struct drm_device *dev = crtc->dev;
3430 struct drm_i915_private *dev_priv = dev->dev_private;
3431 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3432 struct intel_encoder *encoder;
6be4a607
JB		 3433 int pipe = intel_crtc->pipe;
3434 int plane = intel_crtc->plane;
5eddb70b 3435 u32 reg, temp;
b52eb4dc 3436
ef9c3aee 3437
f7abfe8b
CW		 3438 if (!intel_crtc->active)
3439 return;
3440
ea9d758d
DV		 3441 for_each_encoder_on_crtc(dev, crtc, encoder)
3442 encoder->disable(encoder);
3443
e6c3a2a6 3444 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3445 drm_vblank_off(dev, pipe);
913d8d11 3446
5c3fe8b0 3447 if (dev_priv->fbc.plane == plane)
973d04f9 3448 intel_disable_fbc(dev);
2c07245f 3449
0d5b8c61 3450 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3451 intel_disable_planes(crtc);
0d5b8c61
VS		 3452 intel_disable_plane(dev_priv, plane, pipe);
3453
d925c59a
DV		 3454 if (intel_crtc->config.has_pch_encoder)
3455 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3456
b24e7179 3457 intel_disable_pipe(dev_priv, pipe);
32f9d658 3458
3f8dce3a 3459 ironlake_pfit_disable(intel_crtc);
2c07245f 3460
bf49ec8c
DV		 3461 for_each_encoder_on_crtc(dev, crtc, encoder)
3462 if (encoder->post_disable)
3463 encoder->post_disable(encoder);
2c07245f 3464
d925c59a
DV		 3465 if (intel_crtc->config.has_pch_encoder) {
3466 ironlake_fdi_disable(crtc);
913d8d11 3467
d925c59a
DV		 3468 ironlake_disable_pch_transcoder(dev_priv, pipe);
3469 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3470
d925c59a
DV		 3471 if (HAS_PCH_CPT(dev)) {
3472 /* disable TRANS_DP_CTL */
3473 reg = TRANS_DP_CTL(pipe);
3474 temp = I915_READ(reg);
3475 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3476 TRANS_DP_PORT_SEL_MASK);
3477 temp |= TRANS_DP_PORT_SEL_NONE;
3478 I915_WRITE(reg, temp);
3479
3480 /* disable DPLL_SEL */
3481 temp = I915_READ(PCH_DPLL_SEL);
11887397 3482 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3483 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3484 }
e3421a18 3485
d925c59a 3486 /* disable PCH DPLL */
e72f9fbf 3487 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3488
d925c59a
DV		 3489 ironlake_fdi_pll_disable(intel_crtc);
3490 }
6b383a7f 3491
f7abfe8b 3492 intel_crtc->active = false;
6b383a7f 3493 intel_update_watermarks(dev);
d1ebd816
BW		 3494
3495 mutex_lock(&dev->struct_mutex);
6b383a7f 3496 intel_update_fbc(dev);
d1ebd816 3497 mutex_unlock(&dev->struct_mutex);
6be4a607 3498}
1b3c7a47 3499
4f771f10 3500static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3501{
4f771f10
PZ		 3502 struct drm_device *dev = crtc->dev;
3503 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3504 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3505 struct intel_encoder *encoder;
3506 int pipe = intel_crtc->pipe;
3507 int plane = intel_crtc->plane;
3b117c8f 3508 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3509
4f771f10
PZ		 3510 if (!intel_crtc->active)
3511 return;
3512
3513 for_each_encoder_on_crtc(dev, crtc, encoder)
3514 encoder->disable(encoder);
3515
3516 intel_crtc_wait_for_pending_flips(crtc);
3517 drm_vblank_off(dev, pipe);
4f771f10 3518
891348b2 3519 /* FBC must be disabled before disabling the plane on HSW. */
5c3fe8b0 3520 if (dev_priv->fbc.plane == plane)
4f771f10
PZ		 3521 intel_disable_fbc(dev);
3522
42db64ef
PZ		 3523 hsw_disable_ips(intel_crtc);
3524
0d5b8c61 3525 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3526 intel_disable_planes(crtc);
891348b2
RV		 3527 intel_disable_plane(dev_priv, plane, pipe);
3528
8664281b
PZ		 3529 if (intel_crtc->config.has_pch_encoder)
3530 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3531 intel_disable_pipe(dev_priv, pipe);
3532
ad80a810 3533 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3534
3f8dce3a 3535 ironlake_pfit_disable(intel_crtc);
4f771f10 3536
1f544388 3537 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3538
3539 for_each_encoder_on_crtc(dev, crtc, encoder)
3540 if (encoder->post_disable)
3541 encoder->post_disable(encoder);
3542
88adfff1 3543 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3544 lpt_disable_pch_transcoder(dev_priv);
8664281b 3545 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3546 intel_ddi_fdi_disable(crtc);
83616634 3547 }
4f771f10
PZ		 3548
3549 intel_crtc->active = false;
3550 intel_update_watermarks(dev);
3551
3552 mutex_lock(&dev->struct_mutex);
3553 intel_update_fbc(dev);
3554 mutex_unlock(&dev->struct_mutex);
3555}
3556
ee7b9f93
JB		 3557static void ironlake_crtc_off(struct drm_crtc *crtc)
3558{
3559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3560 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3561}
3562
6441ab5f
PZ		 3563static void haswell_crtc_off(struct drm_crtc *crtc)
3564{
3565 intel_ddi_put_crtc_pll(crtc);
3566}
3567
02e792fb
DV		 3568static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3569{
02e792fb 3570 if (!enable && intel_crtc->overlay) {
23f09ce3 3571 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3572 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3573
23f09ce3 3574 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3575 dev_priv->mm.interruptible = false;
3576 (void) intel_overlay_switch_off(intel_crtc->overlay);
3577 dev_priv->mm.interruptible = true;
23f09ce3 3578 mutex_unlock(&dev->struct_mutex);
02e792fb 3579 }
02e792fb 3580
5dcdbcb0
CW		 3581 /* Let userspace switch the overlay on again. In most cases userspace
3582 * has to recompute where to put it anyway.
3583 */
02e792fb
DV		 3584}
3585
61bc95c1
EE		 3586/**
3587 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3588 * cursor plane briefly if not already running after enabling the display
3589 * plane.
3590 * This workaround avoids occasional blank screens when self refresh is
3591 * enabled.
3592 */
3593static void
3594g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3595{
3596 u32 cntl = I915_READ(CURCNTR(pipe));
3597
3598 if ((cntl & CURSOR_MODE) == 0) {
3599 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3600
3601 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3602 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3603 intel_wait_for_vblank(dev_priv->dev, pipe);
3604 I915_WRITE(CURCNTR(pipe), cntl);
3605 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3606 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3607 }
3608}
3609
2dd24552
JB		 3610static void i9xx_pfit_enable(struct intel_crtc *crtc)
3611{
3612 struct drm_device *dev = crtc->base.dev;
3613 struct drm_i915_private *dev_priv = dev->dev_private;
3614 struct intel_crtc_config *pipe_config = &crtc->config;
3615
328d8e82 3616 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3617 return;
3618
2dd24552 3619 /*
c0b03411
DV		 3620 * The panel fitter should only be adjusted whilst the pipe is disabled,
3621 * according to register description and PRM.
2dd24552 3622 */
c0b03411
DV		 3623 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3624 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3625
b074cec8
JB		 3626 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3627 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3628
3629 /* Border color in case we don't scale up to the full screen. Black by
3630 * default, change to something else for debugging. */
3631 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3632}
3633
89b667f8
JB		 3634static void valleyview_crtc_enable(struct drm_crtc *crtc)
3635{
3636 struct drm_device *dev = crtc->dev;
3637 struct drm_i915_private *dev_priv = dev->dev_private;
3638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3639 struct intel_encoder *encoder;
3640 int pipe = intel_crtc->pipe;
3641 int plane = intel_crtc->plane;
3642
3643 WARN_ON(!crtc->enabled);
3644
3645 if (intel_crtc->active)
3646 return;
3647
3648 intel_crtc->active = true;
3649 intel_update_watermarks(dev);
3650
3651 mutex_lock(&dev_priv->dpio_lock);
3652
3653 for_each_encoder_on_crtc(dev, crtc, encoder)
3654 if (encoder->pre_pll_enable)
3655 encoder->pre_pll_enable(encoder);
3656
87442f73 3657 vlv_enable_pll(dev_priv, pipe);
89b667f8
JB		 3658
3659 for_each_encoder_on_crtc(dev, crtc, encoder)
3660 if (encoder->pre_enable)
3661 encoder->pre_enable(encoder);
3662
3663 /* VLV wants encoder enabling _before_ the pipe is up. */
3664 for_each_encoder_on_crtc(dev, crtc, encoder)
3665 encoder->enable(encoder);
3666
2dd24552
JB		 3667 i9xx_pfit_enable(intel_crtc);
3668
63cbb074
VS		 3669 intel_crtc_load_lut(crtc);
3670
89b667f8
JB		 3671 intel_enable_pipe(dev_priv, pipe, false);
3672 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3673 intel_enable_planes(crtc);
5c38d48c 3674 intel_crtc_update_cursor(crtc, true);
89b667f8 3675
89b667f8
JB		 3676 intel_update_fbc(dev);
3677
89b667f8
JB		 3678 mutex_unlock(&dev_priv->dpio_lock);
3679}
3680
0b8765c6 3681static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3682{
3683 struct drm_device *dev = crtc->dev;
79e53945
JB		 3684 struct drm_i915_private *dev_priv = dev->dev_private;
3685 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3686 struct intel_encoder *encoder;
79e53945 3687 int pipe = intel_crtc->pipe;
80824003 3688 int plane = intel_crtc->plane;
79e53945 3689
08a48469
DV		 3690 WARN_ON(!crtc->enabled);
3691
f7abfe8b
CW		 3692 if (intel_crtc->active)
3693 return;
3694
3695 intel_crtc->active = true;
6b383a7f
CW		 3696 intel_update_watermarks(dev);
3697
9d6d9f19
MK		 3698 for_each_encoder_on_crtc(dev, crtc, encoder)
3699 if (encoder->pre_enable)
3700 encoder->pre_enable(encoder);
3701
f6736a1a
DV		 3702 i9xx_enable_pll(intel_crtc);
3703
2dd24552
JB		 3704 i9xx_pfit_enable(intel_crtc);
3705
63cbb074
VS		 3706 intel_crtc_load_lut(crtc);
3707
040484af 3708 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3709 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3710 intel_enable_planes(crtc);
22e407d7 3711 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3712 if (IS_G4X(dev))
3713 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3714 intel_crtc_update_cursor(crtc, true);
79e53945 3715
0b8765c6
JB		 3716 /* Give the overlay scaler a chance to enable if it's on this pipe */
3717 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3718
f440eb13 3719 intel_update_fbc(dev);
ef9c3aee 3720
fa5c73b1
DV		 3721 for_each_encoder_on_crtc(dev, crtc, encoder)
3722 encoder->enable(encoder);
0b8765c6 3723}
79e53945 3724
87476d63
DV		 3725static void i9xx_pfit_disable(struct intel_crtc *crtc)
3726{
3727 struct drm_device *dev = crtc->base.dev;
3728 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3729
328d8e82
DV		 3730 if (!crtc->config.gmch_pfit.control)
3731 return;
87476d63 3732
328d8e82 3733 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3734
328d8e82
DV		 3735 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3736 I915_READ(PFIT_CONTROL));
3737 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3738}
3739
0b8765c6
JB		 3740static void i9xx_crtc_disable(struct drm_crtc *crtc)
3741{
3742 struct drm_device *dev = crtc->dev;
3743 struct drm_i915_private *dev_priv = dev->dev_private;
3744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3745 struct intel_encoder *encoder;
0b8765c6
JB		 3746 int pipe = intel_crtc->pipe;
3747 int plane = intel_crtc->plane;
ef9c3aee 3748
f7abfe8b
CW		 3749 if (!intel_crtc->active)
3750 return;
3751
ea9d758d
DV		 3752 for_each_encoder_on_crtc(dev, crtc, encoder)
3753 encoder->disable(encoder);
3754
0b8765c6 3755 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3756 intel_crtc_wait_for_pending_flips(crtc);
3757 drm_vblank_off(dev, pipe);
0b8765c6 3758
5c3fe8b0 3759 if (dev_priv->fbc.plane == plane)
973d04f9 3760 intel_disable_fbc(dev);
79e53945 3761
0d5b8c61
VS		 3762 intel_crtc_dpms_overlay(intel_crtc, false);
3763 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3764 intel_disable_planes(crtc);
b24e7179 3765 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3766
b24e7179 3767 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3768
87476d63 3769 i9xx_pfit_disable(intel_crtc);
24a1f16d 3770
89b667f8
JB		 3771 for_each_encoder_on_crtc(dev, crtc, encoder)
3772 if (encoder->post_disable)
3773 encoder->post_disable(encoder);
3774
63d7bbe9 3775 intel_disable_pll(dev_priv, pipe);
0b8765c6 3776
f7abfe8b 3777 intel_crtc->active = false;
6b383a7f
CW		 3778 intel_update_fbc(dev);
3779 intel_update_watermarks(dev);
0b8765c6
JB		 3780}
3781
ee7b9f93
JB		 3782static void i9xx_crtc_off(struct drm_crtc *crtc)
3783{
3784}
3785
976f8a20
DV		 3786static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3787 bool enabled)
2c07245f
ZW		 3788{
3789 struct drm_device *dev = crtc->dev;
3790 struct drm_i915_master_private *master_priv;
3791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3792 int pipe = intel_crtc->pipe;
79e53945
JB		 3793
3794 if (!dev->primary->master)
3795 return;
3796
3797 master_priv = dev->primary->master->driver_priv;
3798 if (!master_priv->sarea_priv)
3799 return;
3800
79e53945
JB		 3801 switch (pipe) {
3802 case 0:
3803 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3804 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3805 break;
3806 case 1:
3807 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3808 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3809 break;
3810 default:
9db4a9c7 3811 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3812 break;
3813 }
79e53945
JB		 3814}
3815
976f8a20
DV		 3816/**
3817 * Sets the power management mode of the pipe and plane.
3818 */
3819void intel_crtc_update_dpms(struct drm_crtc *crtc)
3820{
3821 struct drm_device *dev = crtc->dev;
3822 struct drm_i915_private *dev_priv = dev->dev_private;
3823 struct intel_encoder *intel_encoder;
3824 bool enable = false;
3825
3826 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3827 enable |= intel_encoder->connectors_active;
3828
3829 if (enable)
3830 dev_priv->display.crtc_enable(crtc);
3831 else
3832 dev_priv->display.crtc_disable(crtc);
3833
3834 intel_crtc_update_sarea(crtc, enable);
3835}
3836
cdd59983
CW		 3837static void intel_crtc_disable(struct drm_crtc *crtc)
3838{
cdd59983 3839 struct drm_device *dev = crtc->dev;
976f8a20 3840 struct drm_connector *connector;
ee7b9f93 3841 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3842 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3843
976f8a20
DV		 3844 /* crtc should still be enabled when we disable it. */
3845 WARN_ON(!crtc->enabled);
3846
3847 dev_priv->display.crtc_disable(crtc);
c77bf565 3848 intel_crtc->eld_vld = false;
976f8a20 3849 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3850 dev_priv->display.off(crtc);
3851
931872fc
CW		 3852 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3853 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3854
3855 if (crtc->fb) {
3856 mutex_lock(&dev->struct_mutex);
1690e1eb 3857 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3858 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3859 crtc->fb = NULL;
3860 }
3861
3862 /* Update computed state. */
3863 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3864 if (!connector->encoder || !connector->encoder->crtc)
3865 continue;
3866
3867 if (connector->encoder->crtc != crtc)
3868 continue;
3869
3870 connector->dpms = DRM_MODE_DPMS_OFF;
3871 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3872 }
3873}
3874
a261b246 3875void intel_modeset_disable(struct drm_device *dev)
79e53945 3876{
a261b246
DV		 3877 struct drm_crtc *crtc;
3878
3879 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3880 if (crtc->enabled)
3881 intel_crtc_disable(crtc);
3882 }
79e53945
JB		 3883}
3884
ea5b213a 3885void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3886{
4ef69c7a 3887 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3888
ea5b213a
CW		 3889 drm_encoder_cleanup(encoder);
3890 kfree(intel_encoder);
7e7d76c3
JB		 3891}
3892
5ab432ef
DV		 3893/* Simple dpms helper for encodres with just one connector, no cloning and only
3894 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3895 * state of the entire output pipe. */
3896void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3897{
5ab432ef
DV		 3898 if (mode == DRM_MODE_DPMS_ON) {
3899 encoder->connectors_active = true;
3900
b2cabb0e 3901 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3902 } else {
3903 encoder->connectors_active = false;
3904
b2cabb0e 3905 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3906 }
79e53945
JB		 3907}
3908
0a91ca29
DV		 3909/* Cross check the actual hw state with our own modeset state tracking (and it's
3910 * internal consistency). */
b980514c 3911static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3912{
0a91ca29
DV		 3913 if (connector->get_hw_state(connector)) {
3914 struct intel_encoder *encoder = connector->encoder;
3915 struct drm_crtc *crtc;
3916 bool encoder_enabled;
3917 enum pipe pipe;
3918
3919 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3920 connector->base.base.id,
3921 drm_get_connector_name(&connector->base));
3922
3923 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3924 "wrong connector dpms state\n");
3925 WARN(connector->base.encoder != &encoder->base,
3926 "active connector not linked to encoder\n");
3927 WARN(!encoder->connectors_active,
3928 "encoder->connectors_active not set\n");
3929
3930 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3931 WARN(!encoder_enabled, "encoder not enabled\n");
3932 if (WARN_ON(!encoder->base.crtc))
3933 return;
3934
3935 crtc = encoder->base.crtc;
3936
3937 WARN(!crtc->enabled, "crtc not enabled\n");
3938 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3939 WARN(pipe != to_intel_crtc(crtc)->pipe,
3940 "encoder active on the wrong pipe\n");
3941 }
79e53945
JB		 3942}
3943
5ab432ef
DV		 3944/* Even simpler default implementation, if there's really no special case to
3945 * consider. */
3946void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3947{
5ab432ef 3948 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3949
5ab432ef
DV		 3950 /* All the simple cases only support two dpms states. */
3951 if (mode != DRM_MODE_DPMS_ON)
3952 mode = DRM_MODE_DPMS_OFF;
d4270e57 3953
5ab432ef
DV		 3954 if (mode == connector->dpms)
3955 return;
3956
3957 connector->dpms = mode;
3958
3959 /* Only need to change hw state when actually enabled */
3960 if (encoder->base.crtc)
3961 intel_encoder_dpms(encoder, mode);
3962 else
8af6cf88 3963 WARN_ON(encoder->connectors_active != false);
0a91ca29 3964
b980514c 3965 intel_modeset_check_state(connector->dev);
79e53945
JB		 3966}
3967
f0947c37
DV		 3968/* Simple connector->get_hw_state implementation for encoders that support only
3969 * one connector and no cloning and hence the encoder state determines the state
3970 * of the connector. */
3971bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3972{
24929352 3973 enum pipe pipe = 0;
f0947c37 3974 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3975
f0947c37 3976 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3977}
3978
1857e1da
DV		 3979static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3980 struct intel_crtc_config *pipe_config)
3981{
3982 struct drm_i915_private *dev_priv = dev->dev_private;
3983 struct intel_crtc *pipe_B_crtc =
3984 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3985
3986 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3987 pipe_name(pipe), pipe_config->fdi_lanes);
3988 if (pipe_config->fdi_lanes > 4) {
3989 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3990 pipe_name(pipe), pipe_config->fdi_lanes);
3991 return false;
3992 }
3993
3994 if (IS_HASWELL(dev)) {
3995 if (pipe_config->fdi_lanes > 2) {
3996 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3997 pipe_config->fdi_lanes);
3998 return false;
3999 } else {
4000 return true;
4001 }
4002 }
4003
4004 if (INTEL_INFO(dev)->num_pipes == 2)
4005 return true;
4006
4007 /* Ivybridge 3 pipe is really complicated */
4008 switch (pipe) {
4009 case PIPE_A:
4010 return true;
4011 case PIPE_B:
4012 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4013 pipe_config->fdi_lanes > 2) {
4014 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4015 pipe_name(pipe), pipe_config->fdi_lanes);
4016 return false;
4017 }
4018 return true;
4019 case PIPE_C:
1e833f40 4020 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4021 pipe_B_crtc->config.fdi_lanes <= 2) {
4022 if (pipe_config->fdi_lanes > 2) {
4023 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4024 pipe_name(pipe), pipe_config->fdi_lanes);
4025 return false;
4026 }
4027 } else {
4028 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4029 return false;
4030 }
4031 return true;
4032 default:
4033 BUG();
4034 }
4035}
4036
e29c22c0
DV		 4037#define RETRY 1
4038static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4039 struct intel_crtc_config *pipe_config)
877d48d5 4040{
1857e1da 4041 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4042 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4043 int lane, link_bw, fdi_dotclock;
e29c22c0 4044 bool setup_ok, needs_recompute = false;
877d48d5 4045
e29c22c0 4046retry:
877d48d5
DV		 4047 /* FDI is a binary signal running at ~2.7GHz, encoding
4048 * each output octet as 10 bits. The actual frequency
4049 * is stored as a divider into a 100MHz clock, and the
4050 * mode pixel clock is stored in units of 1KHz.
4051 * Hence the bw of each lane in terms of the mode signal
4052 * is:
4053 */
4054 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4055
ff9a6750 4056 fdi_dotclock = adjusted_mode->clock;
ef1b460d 4057 fdi_dotclock /= pipe_config->pixel_multiplier;
877d48d5 4058
2bd89a07 4059 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4060 pipe_config->pipe_bpp);
4061
4062 pipe_config->fdi_lanes = lane;
4063
2bd89a07 4064 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4065 link_bw, &pipe_config->fdi_m_n);
1857e1da 4066
e29c22c0
DV		 4067 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4068 intel_crtc->pipe, pipe_config);
4069 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4070 pipe_config->pipe_bpp -= 2*3;
4071 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4072 pipe_config->pipe_bpp);
4073 needs_recompute = true;
4074 pipe_config->bw_constrained = true;
4075
4076 goto retry;
4077 }
4078
4079 if (needs_recompute)
4080 return RETRY;
4081
4082 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4083}
4084
42db64ef
PZ		 4085static void hsw_compute_ips_config(struct intel_crtc *crtc,
4086 struct intel_crtc_config *pipe_config)
4087{
3c4ca58c
PZ		 4088 pipe_config->ips_enabled = i915_enable_ips &&
4089 hsw_crtc_supports_ips(crtc) &&
42db64ef
PZ		 4090 pipe_config->pipe_bpp == 24;
4091}
4092
a43f6e0f 4093static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4094 struct intel_crtc_config *pipe_config)
79e53945 4095{
a43f6e0f 4096 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4097 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4098
bad720ff 4099 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4100 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4101 if (pipe_config->requested_mode.clock * 3
4102 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4103 return -EINVAL;
2c07245f 4104 }
89749350 4105
f9bef081
DV		 4106 /* All interlaced capable intel hw wants timings in frames. Note though
4107 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4108 * timings, so we need to be careful not to clobber these.*/
7ae89233 4109 if (!pipe_config->timings_set)
f9bef081 4110 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4111
8693a824
DL		 4112 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4113 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4114 */
4115 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4116 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4117 return -EINVAL;
44f46b42 4118
bd080ee5 4119 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4120 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4121 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4122 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4123 * for lvds. */
4124 pipe_config->pipe_bpp = 8*3;
4125 }
4126
f5adf94e 4127 if (HAS_IPS(dev))
a43f6e0f
DV		 4128 hsw_compute_ips_config(crtc, pipe_config);
4129
4130 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4131 * clock survives for now. */
4132 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4133 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4134
877d48d5 4135 if (pipe_config->has_pch_encoder)
a43f6e0f 4136 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4137
e29c22c0 4138 return 0;
79e53945
JB		 4139}
4140
25eb05fc
JB		 4141static int valleyview_get_display_clock_speed(struct drm_device *dev)
4142{
4143 return 400000; /* FIXME */
4144}
4145
e70236a8
JB		 4146static int i945_get_display_clock_speed(struct drm_device *dev)
4147{
4148 return 400000;
4149}
79e53945 4150
e70236a8 4151static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4152{
e70236a8
JB		 4153 return 333000;
4154}
79e53945 4155
e70236a8
JB		 4156static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4157{
4158 return 200000;
4159}
79e53945 4160
e70236a8
JB		 4161static int i915gm_get_display_clock_speed(struct drm_device *dev)
4162{
4163 u16 gcfgc = 0;
79e53945 4164
e70236a8
JB		 4165 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4166
4167 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4168 return 133000;
4169 else {
4170 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4171 case GC_DISPLAY_CLOCK_333_MHZ:
4172 return 333000;
4173 default:
4174 case GC_DISPLAY_CLOCK_190_200_MHZ:
4175 return 190000;
79e53945 4176 }
e70236a8
JB		 4177 }
4178}
4179
4180static int i865_get_display_clock_speed(struct drm_device *dev)
4181{
4182 return 266000;
4183}
4184
4185static int i855_get_display_clock_speed(struct drm_device *dev)
4186{
4187 u16 hpllcc = 0;
4188 /* Assume that the hardware is in the high speed state. This
4189 * should be the default.
4190 */
4191 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4192 case GC_CLOCK_133_200:
4193 case GC_CLOCK_100_200:
4194 return 200000;
4195 case GC_CLOCK_166_250:
4196 return 250000;
4197 case GC_CLOCK_100_133:
79e53945 4198 return 133000;
e70236a8 4199 }
79e53945 4200
e70236a8
JB		 4201 /* Shouldn't happen */
4202 return 0;
4203}
79e53945 4204
e70236a8
JB		 4205static int i830_get_display_clock_speed(struct drm_device *dev)
4206{
4207 return 133000;
79e53945
JB		 4208}
4209
2c07245f 4210static void
a65851af 4211intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4212{
a65851af
VS		 4213 while (*num > DATA_LINK_M_N_MASK ||
4214 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4215 *num >>= 1;
4216 *den >>= 1;
4217 }
4218}
4219
a65851af
VS		 4220static void compute_m_n(unsigned int m, unsigned int n,
4221 uint32_t *ret_m, uint32_t *ret_n)
4222{
4223 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4224 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4225 intel_reduce_m_n_ratio(ret_m, ret_n);
4226}
4227
e69d0bc1
DV		 4228void
4229intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4230 int pixel_clock, int link_clock,
4231 struct intel_link_m_n *m_n)
2c07245f 4232{
e69d0bc1 4233 m_n->tu = 64;
a65851af
VS		 4234
4235 compute_m_n(bits_per_pixel * pixel_clock,
4236 link_clock * nlanes * 8,
4237 &m_n->gmch_m, &m_n->gmch_n);
4238
4239 compute_m_n(pixel_clock, link_clock,
4240 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4241}
4242
a7615030
CW		 4243static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4244{
72bbe58c
KP		 4245 if (i915_panel_use_ssc >= 0)
4246 return i915_panel_use_ssc != 0;
41aa3448 4247 return dev_priv->vbt.lvds_use_ssc
435793df 4248 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4249}
4250
a0c4da24
JB		 4251static int vlv_get_refclk(struct drm_crtc *crtc)
4252{
4253 struct drm_device *dev = crtc->dev;
4254 struct drm_i915_private *dev_priv = dev->dev_private;
4255 int refclk = 27000; /* for DP & HDMI */
4256
4257 return 100000; /* only one validated so far */
4258
4259 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4260 refclk = 96000;
4261 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4262 if (intel_panel_use_ssc(dev_priv))
4263 refclk = 100000;
4264 else
4265 refclk = 96000;
4266 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4267 refclk = 100000;
4268 }
4269
4270 return refclk;
4271}
4272
c65d77d8
JB		 4273static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4274{
4275 struct drm_device *dev = crtc->dev;
4276 struct drm_i915_private *dev_priv = dev->dev_private;
4277 int refclk;
4278
a0c4da24
JB		 4279 if (IS_VALLEYVIEW(dev)) {
4280 refclk = vlv_get_refclk(crtc);
4281 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4282 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4283 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4284 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4285 refclk / 1000);
4286 } else if (!IS_GEN2(dev)) {
4287 refclk = 96000;
4288 } else {
4289 refclk = 48000;
4290 }
4291
4292 return refclk;
4293}
4294
7429e9d4 4295static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4296{
7df00d7a 4297 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4298}
f47709a9 4299
7429e9d4
DV		 4300static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4301{
4302 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4303}
4304
f47709a9 4305static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4306 intel_clock_t *reduced_clock)
4307{
f47709a9 4308 struct drm_device *dev = crtc->base.dev;
a7516a05 4309 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4310 int pipe = crtc->pipe;
a7516a05
JB		 4311 u32 fp, fp2 = 0;
4312
4313 if (IS_PINEVIEW(dev)) {
7429e9d4 4314 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4315 if (reduced_clock)
7429e9d4 4316 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4317 } else {
7429e9d4 4318 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4319 if (reduced_clock)
7429e9d4 4320 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4321 }
4322
4323 I915_WRITE(FP0(pipe), fp);
8bcc2795 4324 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4325
f47709a9
DV		 4326 crtc->lowfreq_avail = false;
4327 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4328 reduced_clock && i915_powersave) {
4329 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4330 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4331 crtc->lowfreq_avail = true;
a7516a05
JB		 4332 } else {
4333 I915_WRITE(FP1(pipe), fp);
8bcc2795 4334 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4335 }
4336}
4337
89b667f8
JB		 4338static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4339{
4340 u32 reg_val;
4341
4342 /*
4343 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4344 * and set it to a reasonable value instead.
4345 */
ae99258f 4346 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4347 reg_val &= 0xffffff00;
4348 reg_val |= 0x00000030;
ae99258f 4349 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4350
ae99258f 4351 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4352 reg_val &= 0x8cffffff;
4353 reg_val = 0x8c000000;
ae99258f 4354 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4355
ae99258f 4356 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4357 reg_val &= 0xffffff00;
ae99258f 4358 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4359
ae99258f 4360 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4361 reg_val &= 0x00ffffff;
4362 reg_val |= 0xb0000000;
ae99258f 4363 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4364}
4365
b551842d
DV		 4366static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4367 struct intel_link_m_n *m_n)
4368{
4369 struct drm_device *dev = crtc->base.dev;
4370 struct drm_i915_private *dev_priv = dev->dev_private;
4371 int pipe = crtc->pipe;
4372
e3b95f1e
DV		 4373 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4374 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4375 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4376 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4377}
4378
4379static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4380 struct intel_link_m_n *m_n)
4381{
4382 struct drm_device *dev = crtc->base.dev;
4383 struct drm_i915_private *dev_priv = dev->dev_private;
4384 int pipe = crtc->pipe;
4385 enum transcoder transcoder = crtc->config.cpu_transcoder;
4386
4387 if (INTEL_INFO(dev)->gen >= 5) {
4388 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4389 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4390 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4391 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4392 } else {
e3b95f1e
DV		 4393 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4394 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4395 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4396 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4397 }
4398}
4399
03afc4a2
DV		 4400static void intel_dp_set_m_n(struct intel_crtc *crtc)
4401{
4402 if (crtc->config.has_pch_encoder)
4403 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4404 else
4405 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4406}
4407
f47709a9 4408static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4409{
f47709a9 4410 struct drm_device *dev = crtc->base.dev;
a0c4da24 4411 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8 4412 struct intel_encoder *encoder;
f47709a9 4413 int pipe = crtc->pipe;
89b667f8 4414 u32 dpll, mdiv;
a0c4da24 4415 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4416 bool is_hdmi;
198a037f 4417 u32 coreclk, reg_val, dpll_md;
a0c4da24 4418
09153000
DV		 4419 mutex_lock(&dev_priv->dpio_lock);
4420
89b667f8 4421 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4422
f47709a9
DV		 4423 bestn = crtc->config.dpll.n;
4424 bestm1 = crtc->config.dpll.m1;
4425 bestm2 = crtc->config.dpll.m2;
4426 bestp1 = crtc->config.dpll.p1;
4427 bestp2 = crtc->config.dpll.p2;
a0c4da24 4428
89b667f8
JB		 4429 /* See eDP HDMI DPIO driver vbios notes doc */
4430
4431 /* PLL B needs special handling */
4432 if (pipe)
4433 vlv_pllb_recal_opamp(dev_priv);
4434
4435 /* Set up Tx target for periodic Rcomp update */
ae99258f 4436 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4437
4438 /* Disable target IRef on PLL */
ae99258f 4439 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4440 reg_val &= 0x00ffffff;
ae99258f 4441 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4442
4443 /* Disable fast lock */
ae99258f 4444 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4445
4446 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4447 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4448 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4449 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4450 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4451
4452 /*
4453 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4454 * but we don't support that).
4455 * Note: don't use the DAC post divider as it seems unstable.
4456 */
4457 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4458 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4459
a0c4da24 4460 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4461 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4462
89b667f8 4463 /* Set HBR and RBR LPF coefficients */
ff9a6750 4464 if (crtc->config.port_clock == 162000 ||
99750bd4 4465 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4466 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
4abb2c39 4467 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
885b0120 4468 0x009f0003);
89b667f8 4469 else
4abb2c39 4470 vlv_dpio_write(dev_priv, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4471 0x00d0000f);
4472
4473 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4474 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4475 /* Use SSC source */
4476 if (!pipe)
ae99258f 4477 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4478 0x0df40000);
4479 else
ae99258f 4480 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4481 0x0df70000);
4482 } else { /* HDMI or VGA */
4483 /* Use bend source */
4484 if (!pipe)
ae99258f 4485 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4486 0x0df70000);
4487 else
ae99258f 4488 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4489 0x0df40000);
4490 }
a0c4da24 4491
ae99258f 4492 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4493 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4494 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4495 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4496 coreclk |= 0x01000000;
ae99258f 4497 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4498
ae99258f 4499 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4500
89b667f8
JB		 4501 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4502 if (encoder->pre_pll_enable)
4503 encoder->pre_pll_enable(encoder);
a0c4da24 4504
89b667f8
JB		 4505 /* Enable DPIO clock input */
4506 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4507 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4508 if (pipe)
4509 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24
JB		 4510
4511 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4512 crtc->config.dpll_hw_state.dpll = dpll;
4513
a0c4da24
JB		 4514 I915_WRITE(DPLL(pipe), dpll);
4515 POSTING_READ(DPLL(pipe));
2a8f64ca 4516 udelay(150);
a0c4da24 4517
a0c4da24
JB		 4518 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4519 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4520
ef1b460d
DV		 4521 dpll_md = (crtc->config.pixel_multiplier - 1)
4522 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4523 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4524
198a037f 4525 I915_WRITE(DPLL_MD(pipe), dpll_md);
2a8f64ca 4526 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4527
89b667f8
JB		 4528 if (crtc->config.has_dp_encoder)
4529 intel_dp_set_m_n(crtc);
09153000
DV		 4530
4531 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4532}
4533
f47709a9
DV		 4534static void i9xx_update_pll(struct intel_crtc *crtc,
4535 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4536 int num_connectors)
4537{
f47709a9 4538 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4539 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4540 u32 dpll;
4541 bool is_sdvo;
f47709a9 4542 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4543
f47709a9 4544 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4545
f47709a9
DV		 4546 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4547 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4548
4549 dpll = DPLL_VGA_MODE_DIS;
4550
f47709a9 4551 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4552 dpll |= DPLLB_MODE_LVDS;
4553 else
4554 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4555
ef1b460d 4556 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4557 dpll |= (crtc->config.pixel_multiplier - 1)
4558 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4559 }
198a037f
DV		 4560
4561 if (is_sdvo)
4a33e48d 4562 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4563
f47709a9 4564 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4565 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4566
4567 /* compute bitmask from p1 value */
4568 if (IS_PINEVIEW(dev))
4569 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4570 else {
4571 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4572 if (IS_G4X(dev) && reduced_clock)
4573 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4574 }
4575 switch (clock->p2) {
4576 case 5:
4577 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4578 break;
4579 case 7:
4580 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4581 break;
4582 case 10:
4583 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4584 break;
4585 case 14:
4586 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4587 break;
4588 }
4589 if (INTEL_INFO(dev)->gen >= 4)
4590 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4591
09ede541 4592 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4593 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4594 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4595 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4596 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4597 else
4598 dpll |= PLL_REF_INPUT_DREFCLK;
4599
4600 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4601 crtc->config.dpll_hw_state.dpll = dpll;
4602
eb1cbe48 4603 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4604 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4605 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4606 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4607 }
66e3d5c0
DV		 4608
4609 if (crtc->config.has_dp_encoder)
4610 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4611}
4612
f47709a9 4613static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4614 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4615 int num_connectors)
4616{
f47709a9 4617 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4618 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4619 u32 dpll;
f47709a9 4620 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4621
f47709a9 4622 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4623
eb1cbe48
DV		 4624 dpll = DPLL_VGA_MODE_DIS;
4625
f47709a9 4626 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4627 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4628 } else {
4629 if (clock->p1 == 2)
4630 dpll |= PLL_P1_DIVIDE_BY_TWO;
4631 else
4632 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4633 if (clock->p2 == 4)
4634 dpll |= PLL_P2_DIVIDE_BY_4;
4635 }
4636
4a33e48d
DV		 4637 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4638 dpll |= DPLL_DVO_2X_MODE;
4639
f47709a9 4640 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4641 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4642 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4643 else
4644 dpll |= PLL_REF_INPUT_DREFCLK;
4645
4646 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4647 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4648}
4649
8a654f3b 4650static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4651{
4652 struct drm_device *dev = intel_crtc->base.dev;
4653 struct drm_i915_private *dev_priv = dev->dev_private;
4654 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4655 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4656 struct drm_display_mode *adjusted_mode =
4657 &intel_crtc->config.adjusted_mode;
4658 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
4d8a62ea
DV		 4659 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4660
4661 /* We need to be careful not to changed the adjusted mode, for otherwise
4662 * the hw state checker will get angry at the mismatch. */
4663 crtc_vtotal = adjusted_mode->crtc_vtotal;
4664 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4665
4666 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4667 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4668 crtc_vtotal -= 1;
4669 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4670 vsyncshift = adjusted_mode->crtc_hsync_start
4671 - adjusted_mode->crtc_htotal / 2;
4672 } else {
4673 vsyncshift = 0;
4674 }
4675
4676 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4677 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4678
fe2b8f9d 4679 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4680 (adjusted_mode->crtc_hdisplay - 1) |
4681 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4682 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4683 (adjusted_mode->crtc_hblank_start - 1) |
4684 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4685 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4686 (adjusted_mode->crtc_hsync_start - 1) |
4687 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4688
fe2b8f9d 4689 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4690 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4691 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4692 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4693 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4694 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4695 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4696 (adjusted_mode->crtc_vsync_start - 1) |
4697 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4698
b5e508d4
PZ		 4699 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4700 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4701 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4702 * bits. */
4703 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4704 (pipe == PIPE_B || pipe == PIPE_C))
4705 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4706
b0e77b9c
PZ		 4707 /* pipesrc controls the size that is scaled from, which should
4708 * always be the user's requested size.
4709 */
4710 I915_WRITE(PIPESRC(pipe),
4711 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4712}
4713
1bd1bd80
DV		 4714static void intel_get_pipe_timings(struct intel_crtc *crtc,
4715 struct intel_crtc_config *pipe_config)
4716{
4717 struct drm_device *dev = crtc->base.dev;
4718 struct drm_i915_private *dev_priv = dev->dev_private;
4719 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4720 uint32_t tmp;
4721
4722 tmp = I915_READ(HTOTAL(cpu_transcoder));
4723 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4724 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4725 tmp = I915_READ(HBLANK(cpu_transcoder));
4726 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4727 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4728 tmp = I915_READ(HSYNC(cpu_transcoder));
4729 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4730 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4731
4732 tmp = I915_READ(VTOTAL(cpu_transcoder));
4733 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4734 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4735 tmp = I915_READ(VBLANK(cpu_transcoder));
4736 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4737 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4738 tmp = I915_READ(VSYNC(cpu_transcoder));
4739 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4740 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4741
4742 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4743 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4744 pipe_config->adjusted_mode.crtc_vtotal += 1;
4745 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4746 }
4747
4748 tmp = I915_READ(PIPESRC(crtc->pipe));
4749 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4750 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4751}
4752
babea61d
JB		 4753static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4754 struct intel_crtc_config *pipe_config)
4755{
4756 struct drm_crtc *crtc = &intel_crtc->base;
4757
4758 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4759 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4760 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4761 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4762
4763 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4764 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4765 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4766 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4767
4768 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4769
4770 crtc->mode.clock = pipe_config->adjusted_mode.clock;
4771 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4772}
4773
84b046f3
DV		 4774static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4775{
4776 struct drm_device *dev = intel_crtc->base.dev;
4777 struct drm_i915_private *dev_priv = dev->dev_private;
4778 uint32_t pipeconf;
4779
9f11a9e4 4780 pipeconf = 0;
84b046f3
DV		 4781
4782 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4783 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4784 * core speed.
4785 *
4786 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4787 * pipe == 0 check?
4788 */
4789 if (intel_crtc->config.requested_mode.clock >
4790 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4791 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3
DV		 4792 }
4793
ff9ce46e
DV		 4794 /* only g4x and later have fancy bpc/dither controls */
4795 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4796 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4797 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4798 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4799 PIPECONF_DITHER_TYPE_SP;
84b046f3 4800
ff9ce46e
DV		 4801 switch (intel_crtc->config.pipe_bpp) {
4802 case 18:
4803 pipeconf |= PIPECONF_6BPC;
4804 break;
4805 case 24:
4806 pipeconf |= PIPECONF_8BPC;
4807 break;
4808 case 30:
4809 pipeconf |= PIPECONF_10BPC;
4810 break;
4811 default:
4812 /* Case prevented by intel_choose_pipe_bpp_dither. */
4813 BUG();
84b046f3
DV		 4814 }
4815 }
4816
4817 if (HAS_PIPE_CXSR(dev)) {
4818 if (intel_crtc->lowfreq_avail) {
4819 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4820 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4821 } else {
4822 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 4823 }
4824 }
4825
84b046f3
DV		 4826 if (!IS_GEN2(dev) &&
4827 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4828 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4829 else
4830 pipeconf |= PIPECONF_PROGRESSIVE;
4831
9f11a9e4
DV		 4832 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
4833 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 4834
84b046f3
DV		 4835 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4836 POSTING_READ(PIPECONF(intel_crtc->pipe));
4837}
4838
f564048e 4839static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4840 int x, int y,
94352cf9 4841 struct drm_framebuffer *fb)
79e53945
JB		 4842{
4843 struct drm_device *dev = crtc->dev;
4844 struct drm_i915_private *dev_priv = dev->dev_private;
4845 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 4846 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4847 int pipe = intel_crtc->pipe;
80824003 4848 int plane = intel_crtc->plane;
c751ce4f 4849 int refclk, num_connectors = 0;
652c393a 4850 intel_clock_t clock, reduced_clock;
84b046f3 4851 u32 dspcntr;
a16af721
DV		 4852 bool ok, has_reduced_clock = false;
4853 bool is_lvds = false;
5eddb70b 4854 struct intel_encoder *encoder;
d4906093 4855 const intel_limit_t *limit;
5c3b82e2 4856 int ret;
79e53945 4857
6c2b7c12 4858 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4859 switch (encoder->type) {
79e53945
JB		 4860 case INTEL_OUTPUT_LVDS:
4861 is_lvds = true;
4862 break;
79e53945 4863 }
43565a06 4864
c751ce4f 4865 num_connectors++;
79e53945
JB		 4866 }
4867
c65d77d8 4868 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4869
d4906093
ML		 4870 /*
4871 * Returns a set of divisors for the desired target clock with the given
4872 * refclk, or FALSE. The returned values represent the clock equation:
4873 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4874 */
1b894b59 4875 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 4876 ok = dev_priv->display.find_dpll(limit, crtc,
4877 intel_crtc->config.port_clock,
ee9300bb
DV		 4878 refclk, NULL, &clock);
4879 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4880 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4881 return -EINVAL;
79e53945
JB		 4882 }
4883
cda4b7d3 4884 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4885 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4886
ddc9003c 4887 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4888 /*
4889 * Ensure we match the reduced clock's P to the target clock.
4890 * If the clocks don't match, we can't switch the display clock
4891 * by using the FP0/FP1. In such case we will disable the LVDS
4892 * downclock feature.
4893 */
ee9300bb
DV		 4894 has_reduced_clock =
4895 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4896 dev_priv->lvds_downclock,
ee9300bb 4897 refclk, &clock,
5eddb70b 4898 &reduced_clock);
7026d4ac 4899 }
f47709a9
DV		 4900 /* Compat-code for transition, will disappear. */
4901 if (!intel_crtc->config.clock_set) {
4902 intel_crtc->config.dpll.n = clock.n;
4903 intel_crtc->config.dpll.m1 = clock.m1;
4904 intel_crtc->config.dpll.m2 = clock.m2;
4905 intel_crtc->config.dpll.p1 = clock.p1;
4906 intel_crtc->config.dpll.p2 = clock.p2;
4907 }
7026d4ac 4908
eb1cbe48 4909 if (IS_GEN2(dev))
8a654f3b 4910 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 4911 has_reduced_clock ? &reduced_clock : NULL,
4912 num_connectors);
a0c4da24 4913 else if (IS_VALLEYVIEW(dev))
f47709a9 4914 vlv_update_pll(intel_crtc);
79e53945 4915 else
f47709a9 4916 i9xx_update_pll(intel_crtc,
eb1cbe48 4917 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4918 num_connectors);
79e53945 4919
79e53945
JB		 4920 /* Set up the display plane register */
4921 dspcntr = DISPPLANE_GAMMA_ENABLE;
4922
da6ecc5d
JB		 4923 if (!IS_VALLEYVIEW(dev)) {
4924 if (pipe == 0)
4925 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4926 else
4927 dspcntr |= DISPPLANE_SEL_PIPE_B;
4928 }
79e53945 4929
8a654f3b 4930 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 4931
4932 /* pipesrc and dspsize control the size that is scaled from,
4933 * which should always be the user's requested size.
79e53945 4934 */
929c77fb
EA		 4935 I915_WRITE(DSPSIZE(plane),
4936 ((mode->vdisplay - 1) << 16) |
4937 (mode->hdisplay - 1));
4938 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4939
84b046f3
DV		 4940 i9xx_set_pipeconf(intel_crtc);
4941
f564048e
EA		 4942 I915_WRITE(DSPCNTR(plane), dspcntr);
4943 POSTING_READ(DSPCNTR(plane));
4944
94352cf9 4945 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4946
4947 intel_update_watermarks(dev);
4948
f564048e
EA		 4949 return ret;
4950}
4951
2fa2fe9a
DV		 4952static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4953 struct intel_crtc_config *pipe_config)
4954{
4955 struct drm_device *dev = crtc->base.dev;
4956 struct drm_i915_private *dev_priv = dev->dev_private;
4957 uint32_t tmp;
4958
4959 tmp = I915_READ(PFIT_CONTROL);
4960
4961 if (INTEL_INFO(dev)->gen < 4) {
4962 if (crtc->pipe != PIPE_B)
4963 return;
4964
4965 /* gen2/3 store dither state in pfit control, needs to match */
4966 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4967 } else {
4968 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4969 return;
4970 }
4971
4972 if (!(tmp & PFIT_ENABLE))
4973 return;
4974
4975 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4976 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4977 if (INTEL_INFO(dev)->gen < 5)
4978 pipe_config->gmch_pfit.lvds_border_bits =
4979 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4980}
4981
0e8ffe1b
DV		 4982static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4983 struct intel_crtc_config *pipe_config)
4984{
4985 struct drm_device *dev = crtc->base.dev;
4986 struct drm_i915_private *dev_priv = dev->dev_private;
4987 uint32_t tmp;
4988
e143a21c 4989 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 4990 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 4991
0e8ffe1b
DV		 4992 tmp = I915_READ(PIPECONF(crtc->pipe));
4993 if (!(tmp & PIPECONF_ENABLE))
4994 return false;
4995
1bd1bd80
DV		 4996 intel_get_pipe_timings(crtc, pipe_config);
4997
2fa2fe9a
DV		 4998 i9xx_get_pfit_config(crtc, pipe_config);
4999
6c49f241
DV		 5000 if (INTEL_INFO(dev)->gen >= 4) {
5001 tmp = I915_READ(DPLL_MD(crtc->pipe));
5002 pipe_config->pixel_multiplier =
5003 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5004 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5005 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5006 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5007 tmp = I915_READ(DPLL(crtc->pipe));
5008 pipe_config->pixel_multiplier =
5009 ((tmp & SDVO_MULTIPLIER_MASK)
5010 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5011 } else {
5012 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5013 * port and will be fixed up in the encoder->get_config
5014 * function. */
5015 pipe_config->pixel_multiplier = 1;
5016 }
8bcc2795
DV		 5017 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5018 if (!IS_VALLEYVIEW(dev)) {
5019 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5020 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5021 } else {
5022 /* Mask out read-only status bits. */
5023 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5024 DPLL_PORTC_READY_MASK |
5025 DPLL_PORTB_READY_MASK);
8bcc2795 5026 }
6c49f241 5027
0e8ffe1b
DV		 5028 return true;
5029}
5030
dde86e2d 5031static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5032{
5033 struct drm_i915_private *dev_priv = dev->dev_private;
5034 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5035 struct intel_encoder *encoder;
74cfd7ac 5036 u32 val, final;
13d83a67 5037 bool has_lvds = false;
199e5d79 5038 bool has_cpu_edp = false;
199e5d79 5039 bool has_panel = false;
99eb6a01
KP		 5040 bool has_ck505 = false;
5041 bool can_ssc = false;
13d83a67
JB		 5042
5043 /* We need to take the global config into account */
199e5d79
KP		 5044 list_for_each_entry(encoder, &mode_config->encoder_list,
5045 base.head) {
5046 switch (encoder->type) {
5047 case INTEL_OUTPUT_LVDS:
5048 has_panel = true;
5049 has_lvds = true;
5050 break;
5051 case INTEL_OUTPUT_EDP:
5052 has_panel = true;
2de6905f 5053 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5054 has_cpu_edp = true;
5055 break;
13d83a67
JB		 5056 }
5057 }
5058
99eb6a01 5059 if (HAS_PCH_IBX(dev)) {
41aa3448 5060 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5061 can_ssc = has_ck505;
5062 } else {
5063 has_ck505 = false;
5064 can_ssc = true;
5065 }
5066
2de6905f
ID		 5067 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5068 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5069
5070 /* Ironlake: try to setup display ref clock before DPLL
5071 * enabling. This is only under driver's control after
5072 * PCH B stepping, previous chipset stepping should be
5073 * ignoring this setting.
5074 */
74cfd7ac
CW		 5075 val = I915_READ(PCH_DREF_CONTROL);
5076
5077 /* As we must carefully and slowly disable/enable each source in turn,
5078 * compute the final state we want first and check if we need to
5079 * make any changes at all.
5080 */
5081 final = val;
5082 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5083 if (has_ck505)
5084 final |= DREF_NONSPREAD_CK505_ENABLE;
5085 else
5086 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5087
5088 final &= ~DREF_SSC_SOURCE_MASK;
5089 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5090 final &= ~DREF_SSC1_ENABLE;
5091
5092 if (has_panel) {
5093 final |= DREF_SSC_SOURCE_ENABLE;
5094
5095 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5096 final |= DREF_SSC1_ENABLE;
5097
5098 if (has_cpu_edp) {
5099 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5100 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5101 else
5102 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5103 } else
5104 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5105 } else {
5106 final |= DREF_SSC_SOURCE_DISABLE;
5107 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5108 }
5109
5110 if (final == val)
5111 return;
5112
13d83a67 5113 /* Always enable nonspread source */
74cfd7ac 5114 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5115
99eb6a01 5116 if (has_ck505)
74cfd7ac 5117 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5118 else
74cfd7ac 5119 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5120
199e5d79 5121 if (has_panel) {
74cfd7ac
CW		 5122 val &= ~DREF_SSC_SOURCE_MASK;
5123 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5124
199e5d79 5125 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5126 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5127 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5128 val |= DREF_SSC1_ENABLE;
e77166b5 5129 } else
74cfd7ac 5130 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5131
5132 /* Get SSC going before enabling the outputs */
74cfd7ac 5133 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5134 POSTING_READ(PCH_DREF_CONTROL);
5135 udelay(200);
5136
74cfd7ac 5137 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5138
5139 /* Enable CPU source on CPU attached eDP */
199e5d79 5140 if (has_cpu_edp) {
99eb6a01 5141 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5142 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5143 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5144 }
13d83a67 5145 else
74cfd7ac 5146 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5147 } else
74cfd7ac 5148 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5149
74cfd7ac 5150 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5151 POSTING_READ(PCH_DREF_CONTROL);
5152 udelay(200);
5153 } else {
5154 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5155
74cfd7ac 5156 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5157
5158 /* Turn off CPU output */
74cfd7ac 5159 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5160
74cfd7ac 5161 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5162 POSTING_READ(PCH_DREF_CONTROL);
5163 udelay(200);
5164
5165 /* Turn off the SSC source */
74cfd7ac
CW		 5166 val &= ~DREF_SSC_SOURCE_MASK;
5167 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5168
5169 /* Turn off SSC1 */
74cfd7ac 5170 val &= ~DREF_SSC1_ENABLE;
199e5d79 5171
74cfd7ac 5172 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5173 POSTING_READ(PCH_DREF_CONTROL);
5174 udelay(200);
5175 }
74cfd7ac
CW		 5176
5177 BUG_ON(val != final);
13d83a67
JB		 5178}
5179
dde86e2d
PZ		 5180/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5181static void lpt_init_pch_refclk(struct drm_device *dev)
5182{
5183 struct drm_i915_private *dev_priv = dev->dev_private;
5184 struct drm_mode_config *mode_config = &dev->mode_config;
5185 struct intel_encoder *encoder;
5186 bool has_vga = false;
5187 bool is_sdv = false;
5188 u32 tmp;
5189
5190 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5191 switch (encoder->type) {
5192 case INTEL_OUTPUT_ANALOG:
5193 has_vga = true;
5194 break;
5195 }
5196 }
5197
5198 if (!has_vga)
5199 return;
5200
c00db246
DV		 5201 mutex_lock(&dev_priv->dpio_lock);
5202
dde86e2d
PZ		 5203 /* XXX: Rip out SDV support once Haswell ships for real. */
5204 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5205 is_sdv = true;
5206
5207 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5208 tmp &= ~SBI_SSCCTL_DISABLE;
5209 tmp |= SBI_SSCCTL_PATHALT;
5210 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5211
5212 udelay(24);
5213
5214 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5215 tmp &= ~SBI_SSCCTL_PATHALT;
5216 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5217
5218 if (!is_sdv) {
5219 tmp = I915_READ(SOUTH_CHICKEN2);
5220 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5221 I915_WRITE(SOUTH_CHICKEN2, tmp);
5222
5223 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5224 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5225 DRM_ERROR("FDI mPHY reset assert timeout\n");
5226
5227 tmp = I915_READ(SOUTH_CHICKEN2);
5228 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5229 I915_WRITE(SOUTH_CHICKEN2, tmp);
5230
5231 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5232 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5233 100))
5234 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5235 }
5236
5237 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5238 tmp &= ~(0xFF << 24);
5239 tmp |= (0x12 << 24);
5240 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5241
dde86e2d
PZ		 5242 if (is_sdv) {
5243 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5244 tmp |= 0x7FFF;
5245 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5246 }
5247
5248 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5249 tmp |= (1 << 11);
5250 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5251
5252 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5253 tmp |= (1 << 11);
5254 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5255
5256 if (is_sdv) {
5257 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5258 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5259 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5260
5261 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5262 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5263 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5264
5265 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5266 tmp |= (0x3F << 8);
5267 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5268
5269 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5270 tmp |= (0x3F << 8);
5271 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5272 }
5273
5274 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5275 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5276 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5277
5278 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5279 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5280 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5281
5282 if (!is_sdv) {
5283 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5284 tmp &= ~(7 << 13);
5285 tmp |= (5 << 13);
5286 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5287
5288 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5289 tmp &= ~(7 << 13);
5290 tmp |= (5 << 13);
5291 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5292 }
5293
5294 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5295 tmp &= ~0xFF;
5296 tmp |= 0x1C;
5297 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5298
5299 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5300 tmp &= ~0xFF;
5301 tmp |= 0x1C;
5302 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5303
5304 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5305 tmp &= ~(0xFF << 16);
5306 tmp |= (0x1C << 16);
5307 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5308
5309 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5310 tmp &= ~(0xFF << 16);
5311 tmp |= (0x1C << 16);
5312 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5313
5314 if (!is_sdv) {
5315 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5316 tmp |= (1 << 27);
5317 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5318
5319 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5320 tmp |= (1 << 27);
5321 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5322
5323 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5324 tmp &= ~(0xF << 28);
5325 tmp |= (4 << 28);
5326 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5327
5328 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5329 tmp &= ~(0xF << 28);
5330 tmp |= (4 << 28);
5331 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5332 }
5333
5334 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5335 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5336 tmp |= SBI_DBUFF0_ENABLE;
5337 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5338
5339 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5340}
5341
5342/*
5343 * Initialize reference clocks when the driver loads
5344 */
5345void intel_init_pch_refclk(struct drm_device *dev)
5346{
5347 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5348 ironlake_init_pch_refclk(dev);
5349 else if (HAS_PCH_LPT(dev))
5350 lpt_init_pch_refclk(dev);
5351}
5352
d9d444cb
JB		 5353static int ironlake_get_refclk(struct drm_crtc *crtc)
5354{
5355 struct drm_device *dev = crtc->dev;
5356 struct drm_i915_private *dev_priv = dev->dev_private;
5357 struct intel_encoder *encoder;
d9d444cb
JB		 5358 int num_connectors = 0;
5359 bool is_lvds = false;
5360
6c2b7c12 5361 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5362 switch (encoder->type) {
5363 case INTEL_OUTPUT_LVDS:
5364 is_lvds = true;
5365 break;
d9d444cb
JB		 5366 }
5367 num_connectors++;
5368 }
5369
5370 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5371 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5372 dev_priv->vbt.lvds_ssc_freq);
5373 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5374 }
5375
5376 return 120000;
5377}
5378
6ff93609 5379static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5380{
c8203565 5381 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5382 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5383 int pipe = intel_crtc->pipe;
c8203565
PZ		 5384 uint32_t val;
5385
78114071 5386 val = 0;
c8203565 5387
965e0c48 5388 switch (intel_crtc->config.pipe_bpp) {
c8203565 5389 case 18:
dfd07d72 5390 val |= PIPECONF_6BPC;
c8203565
PZ		 5391 break;
5392 case 24:
dfd07d72 5393 val |= PIPECONF_8BPC;
c8203565
PZ		 5394 break;
5395 case 30:
dfd07d72 5396 val |= PIPECONF_10BPC;
c8203565
PZ		 5397 break;
5398 case 36:
dfd07d72 5399 val |= PIPECONF_12BPC;
c8203565
PZ		 5400 break;
5401 default:
cc769b62
PZ		 5402 /* Case prevented by intel_choose_pipe_bpp_dither. */
5403 BUG();
c8203565
PZ		 5404 }
5405
d8b32247 5406 if (intel_crtc->config.dither)
c8203565
PZ		 5407 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5408
6ff93609 5409 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5410 val |= PIPECONF_INTERLACED_ILK;
5411 else
5412 val |= PIPECONF_PROGRESSIVE;
5413
50f3b016 5414 if (intel_crtc->config.limited_color_range)
3685a8f3 5415 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5416
c8203565
PZ		 5417 I915_WRITE(PIPECONF(pipe), val);
5418 POSTING_READ(PIPECONF(pipe));
5419}
5420
86d3efce
VS		 5421/*
5422 * Set up the pipe CSC unit.
5423 *
5424 * Currently only full range RGB to limited range RGB conversion
5425 * is supported, but eventually this should handle various
5426 * RGB<->YCbCr scenarios as well.
5427 */
50f3b016 5428static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5429{
5430 struct drm_device *dev = crtc->dev;
5431 struct drm_i915_private *dev_priv = dev->dev_private;
5432 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5433 int pipe = intel_crtc->pipe;
5434 uint16_t coeff = 0x7800; /* 1.0 */
5435
5436 /*
5437 * TODO: Check what kind of values actually come out of the pipe
5438 * with these coeff/postoff values and adjust to get the best
5439 * accuracy. Perhaps we even need to take the bpc value into
5440 * consideration.
5441 */
5442
50f3b016 5443 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5444 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5445
5446 /*
5447 * GY/GU and RY/RU should be the other way around according
5448 * to BSpec, but reality doesn't agree. Just set them up in
5449 * a way that results in the correct picture.
5450 */
5451 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5452 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5453
5454 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5455 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5456
5457 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5458 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5459
5460 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5461 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5462 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5463
5464 if (INTEL_INFO(dev)->gen > 6) {
5465 uint16_t postoff = 0;
5466
50f3b016 5467 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5468 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5469
5470 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5471 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5472 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5473
5474 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5475 } else {
5476 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5477
50f3b016 5478 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5479 mode |= CSC_BLACK_SCREEN_OFFSET;
5480
5481 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5482 }
5483}
5484
6ff93609 5485static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5486{
5487 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5489 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5490 uint32_t val;
5491
3eff4faa 5492 val = 0;
ee2b0b38 5493
d8b32247 5494 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5495 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5496
6ff93609 5497 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5498 val |= PIPECONF_INTERLACED_ILK;
5499 else
5500 val |= PIPECONF_PROGRESSIVE;
5501
702e7a56
PZ		 5502 I915_WRITE(PIPECONF(cpu_transcoder), val);
5503 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5504
5505 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5506 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5507}
5508
6591c6e4 5509static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5510 intel_clock_t *clock,
5511 bool *has_reduced_clock,
5512 intel_clock_t *reduced_clock)
5513{
5514 struct drm_device *dev = crtc->dev;
5515 struct drm_i915_private *dev_priv = dev->dev_private;
5516 struct intel_encoder *intel_encoder;
5517 int refclk;
d4906093 5518 const intel_limit_t *limit;
a16af721 5519 bool ret, is_lvds = false;
79e53945 5520
6591c6e4
PZ		 5521 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5522 switch (intel_encoder->type) {
79e53945
JB		 5523 case INTEL_OUTPUT_LVDS:
5524 is_lvds = true;
5525 break;
79e53945
JB		 5526 }
5527 }
5528
d9d444cb 5529 refclk = ironlake_get_refclk(crtc);
79e53945 5530
d4906093
ML		 5531 /*
5532 * Returns a set of divisors for the desired target clock with the given
5533 * refclk, or FALSE. The returned values represent the clock equation:
5534 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5535 */
1b894b59 5536 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5537 ret = dev_priv->display.find_dpll(limit, crtc,
5538 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5539 refclk, NULL, clock);
6591c6e4
PZ		 5540 if (!ret)
5541 return false;
cda4b7d3 5542
ddc9003c 5543 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5544 /*
5545 * Ensure we match the reduced clock's P to the target clock.
5546 * If the clocks don't match, we can't switch the display clock
5547 * by using the FP0/FP1. In such case we will disable the LVDS
5548 * downclock feature.
5549 */
ee9300bb
DV		 5550 *has_reduced_clock =
5551 dev_priv->display.find_dpll(limit, crtc,
5552 dev_priv->lvds_downclock,
5553 refclk, clock,
5554 reduced_clock);
652c393a 5555 }
61e9653f 5556
6591c6e4
PZ		 5557 return true;
5558}
5559
01a415fd
DV		 5560static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5561{
5562 struct drm_i915_private *dev_priv = dev->dev_private;
5563 uint32_t temp;
5564
5565 temp = I915_READ(SOUTH_CHICKEN1);
5566 if (temp & FDI_BC_BIFURCATION_SELECT)
5567 return;
5568
5569 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5570 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5571
5572 temp |= FDI_BC_BIFURCATION_SELECT;
5573 DRM_DEBUG_KMS("enabling fdi C rx\n");
5574 I915_WRITE(SOUTH_CHICKEN1, temp);
5575 POSTING_READ(SOUTH_CHICKEN1);
5576}
5577
ebfd86fd 5578static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5579{
5580 struct drm_device *dev = intel_crtc->base.dev;
5581 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5582
5583 switch (intel_crtc->pipe) {
5584 case PIPE_A:
ebfd86fd 5585 break;
01a415fd 5586 case PIPE_B:
ebfd86fd 5587 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5588 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5589 else
5590 cpt_enable_fdi_bc_bifurcation(dev);
5591
ebfd86fd 5592 break;
01a415fd 5593 case PIPE_C:
01a415fd
DV		 5594 cpt_enable_fdi_bc_bifurcation(dev);
5595
ebfd86fd 5596 break;
01a415fd
DV		 5597 default:
5598 BUG();
5599 }
5600}
5601
d4b1931c
PZ		 5602int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5603{
5604 /*
5605 * Account for spread spectrum to avoid
5606 * oversubscribing the link. Max center spread
5607 * is 2.5%; use 5% for safety's sake.
5608 */
5609 u32 bps = target_clock * bpp * 21 / 20;
5610 return bps / (link_bw * 8) + 1;
5611}
5612
7429e9d4 5613static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5614{
7429e9d4 5615 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5616}
5617
de13a2e3 5618static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5619 u32 *fp,
9a7c7890 5620 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5621{
de13a2e3 5622 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5623 struct drm_device *dev = crtc->dev;
5624 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5625 struct intel_encoder *intel_encoder;
5626 uint32_t dpll;
6cc5f341 5627 int factor, num_connectors = 0;
09ede541 5628 bool is_lvds = false, is_sdvo = false;
79e53945 5629
de13a2e3
PZ		 5630 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5631 switch (intel_encoder->type) {
79e53945
JB		 5632 case INTEL_OUTPUT_LVDS:
5633 is_lvds = true;
5634 break;
5635 case INTEL_OUTPUT_SDVO:
7d57382e 5636 case INTEL_OUTPUT_HDMI:
79e53945 5637 is_sdvo = true;
79e53945 5638 break;
79e53945 5639 }
43565a06 5640
c751ce4f 5641 num_connectors++;
79e53945 5642 }
79e53945 5643
c1858123 5644 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5645 factor = 21;
5646 if (is_lvds) {
5647 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5648 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5649 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5650 factor = 25;
09ede541 5651 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5652 factor = 20;
c1858123 5653
7429e9d4 5654 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5655 *fp |= FP_CB_TUNE;
2c07245f 5656
9a7c7890
DV		 5657 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5658 *fp2 |= FP_CB_TUNE;
5659
5eddb70b 5660 dpll = 0;
2c07245f 5661
a07d6787
EA		 5662 if (is_lvds)
5663 dpll |= DPLLB_MODE_LVDS;
5664 else
5665 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5666
ef1b460d
DV		 5667 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5668 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5669
5670 if (is_sdvo)
4a33e48d 5671 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5672 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5673 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5674
a07d6787 5675 /* compute bitmask from p1 value */
7429e9d4 5676 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5677 /* also FPA1 */
7429e9d4 5678 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5679
7429e9d4 5680 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5681 case 5:
5682 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5683 break;
5684 case 7:
5685 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5686 break;
5687 case 10:
5688 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5689 break;
5690 case 14:
5691 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5692 break;
79e53945
JB		 5693 }
5694
b4c09f3b 5695 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5696 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5697 else
5698 dpll |= PLL_REF_INPUT_DREFCLK;
5699
959e16d6 5700 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5701}
5702
5703static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5704 int x, int y,
5705 struct drm_framebuffer *fb)
5706{
5707 struct drm_device *dev = crtc->dev;
5708 struct drm_i915_private *dev_priv = dev->dev_private;
5709 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5710 int pipe = intel_crtc->pipe;
5711 int plane = intel_crtc->plane;
5712 int num_connectors = 0;
5713 intel_clock_t clock, reduced_clock;
cbbab5bd 5714 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5715 bool ok, has_reduced_clock = false;
8b47047b 5716 bool is_lvds = false;
de13a2e3 5717 struct intel_encoder *encoder;
e2b78267 5718 struct intel_shared_dpll *pll;
de13a2e3 5719 int ret;
de13a2e3
PZ		 5720
5721 for_each_encoder_on_crtc(dev, crtc, encoder) {
5722 switch (encoder->type) {
5723 case INTEL_OUTPUT_LVDS:
5724 is_lvds = true;
5725 break;
de13a2e3
PZ		 5726 }
5727
5728 num_connectors++;
a07d6787 5729 }
79e53945 5730
5dc5298b
PZ		 5731 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5732 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5733
ff9a6750 5734 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 5735 &has_reduced_clock, &reduced_clock);
ee9300bb 5736 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5737 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5738 return -EINVAL;
79e53945 5739 }
f47709a9
DV		 5740 /* Compat-code for transition, will disappear. */
5741 if (!intel_crtc->config.clock_set) {
5742 intel_crtc->config.dpll.n = clock.n;
5743 intel_crtc->config.dpll.m1 = clock.m1;
5744 intel_crtc->config.dpll.m2 = clock.m2;
5745 intel_crtc->config.dpll.p1 = clock.p1;
5746 intel_crtc->config.dpll.p2 = clock.p2;
5747 }
79e53945 5748
de13a2e3
PZ		 5749 /* Ensure that the cursor is valid for the new mode before changing... */
5750 intel_crtc_update_cursor(crtc, true);
5751
5dc5298b 5752 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5753 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 5754 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5755 if (has_reduced_clock)
7429e9d4 5756 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5757
7429e9d4 5758 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5759 &fp, &reduced_clock,
5760 has_reduced_clock ? &fp2 : NULL);
5761
959e16d6 5762 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 5763 intel_crtc->config.dpll_hw_state.fp0 = fp;
5764 if (has_reduced_clock)
5765 intel_crtc->config.dpll_hw_state.fp1 = fp2;
5766 else
5767 intel_crtc->config.dpll_hw_state.fp1 = fp;
5768
b89a1d39 5769 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 5770 if (pll == NULL) {
84f44ce7
VS		 5771 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5772 pipe_name(pipe));
4b645f14
JB		 5773 return -EINVAL;
5774 }
ee7b9f93 5775 } else
e72f9fbf 5776 intel_put_shared_dpll(intel_crtc);
79e53945 5777
03afc4a2
DV		 5778 if (intel_crtc->config.has_dp_encoder)
5779 intel_dp_set_m_n(intel_crtc);
79e53945 5780
bcd644e0
DV		 5781 if (is_lvds && has_reduced_clock && i915_powersave)
5782 intel_crtc->lowfreq_avail = true;
5783 else
5784 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 5785
5786 if (intel_crtc->config.has_pch_encoder) {
5787 pll = intel_crtc_to_shared_dpll(intel_crtc);
5788
652c393a
JB		 5789 }
5790
8a654f3b 5791 intel_set_pipe_timings(intel_crtc);
5eddb70b 5792
ca3a0ff8 5793 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5794 intel_cpu_transcoder_set_m_n(intel_crtc,
5795 &intel_crtc->config.fdi_m_n);
5796 }
2c07245f 5797
ebfd86fd
DV		 5798 if (IS_IVYBRIDGE(dev))
5799 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 5800
6ff93609 5801 ironlake_set_pipeconf(crtc);
79e53945 5802
a1f9e77e
PZ		 5803 /* Set up the display plane register */
5804 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5805 POSTING_READ(DSPCNTR(plane));
79e53945 5806
94352cf9 5807 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5808
5809 intel_update_watermarks(dev);
5810
1857e1da 5811 return ret;
79e53945
JB		 5812}
5813
72419203
DV		 5814static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5815 struct intel_crtc_config *pipe_config)
5816{
5817 struct drm_device *dev = crtc->base.dev;
5818 struct drm_i915_private *dev_priv = dev->dev_private;
5819 enum transcoder transcoder = pipe_config->cpu_transcoder;
5820
5821 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5822 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5823 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5824 & ~TU_SIZE_MASK;
5825 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5826 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5827 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5828}
5829
2fa2fe9a
DV		 5830static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5831 struct intel_crtc_config *pipe_config)
5832{
5833 struct drm_device *dev = crtc->base.dev;
5834 struct drm_i915_private *dev_priv = dev->dev_private;
5835 uint32_t tmp;
5836
5837 tmp = I915_READ(PF_CTL(crtc->pipe));
5838
5839 if (tmp & PF_ENABLE) {
5840 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5841 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 5842
5843 /* We currently do not free assignements of panel fitters on
5844 * ivb/hsw (since we don't use the higher upscaling modes which
5845 * differentiates them) so just WARN about this case for now. */
5846 if (IS_GEN7(dev)) {
5847 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
5848 PF_PIPE_SEL_IVB(crtc->pipe));
5849 }
2fa2fe9a 5850 }
79e53945
JB		 5851}
5852
0e8ffe1b
DV		 5853static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5854 struct intel_crtc_config *pipe_config)
5855{
5856 struct drm_device *dev = crtc->base.dev;
5857 struct drm_i915_private *dev_priv = dev->dev_private;
5858 uint32_t tmp;
5859
e143a21c 5860 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5861 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5862
0e8ffe1b
DV		 5863 tmp = I915_READ(PIPECONF(crtc->pipe));
5864 if (!(tmp & PIPECONF_ENABLE))
5865 return false;
5866
ab9412ba 5867 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 5868 struct intel_shared_dpll *pll;
5869
88adfff1
DV		 5870 pipe_config->has_pch_encoder = true;
5871
627eb5a3
DV		 5872 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5873 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5874 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5875
5876 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 5877
c0d43d62 5878 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 5879 pipe_config->shared_dpll =
5880 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 5881 } else {
5882 tmp = I915_READ(PCH_DPLL_SEL);
5883 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
5884 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
5885 else
5886 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
5887 }
66e985c0
DV		 5888
5889 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
5890
5891 WARN_ON(!pll->get_hw_state(dev_priv, pll,
5892 &pipe_config->dpll_hw_state));
c93f54cf
DV		 5893
5894 tmp = pipe_config->dpll_hw_state.dpll;
5895 pipe_config->pixel_multiplier =
5896 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
5897 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
6c49f241
DV		 5898 } else {
5899 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 5900 }
5901
1bd1bd80
DV		 5902 intel_get_pipe_timings(crtc, pipe_config);
5903
2fa2fe9a
DV		 5904 ironlake_get_pfit_config(crtc, pipe_config);
5905
0e8ffe1b
DV		 5906 return true;
5907}
5908
d6dd9eb1
DV		 5909static void haswell_modeset_global_resources(struct drm_device *dev)
5910{
d6dd9eb1
DV		 5911 bool enable = false;
5912 struct intel_crtc *crtc;
d6dd9eb1
DV		 5913
5914 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 5915 if (!crtc->base.enabled)
5916 continue;
d6dd9eb1 5917
e7a639c4
DV		 5918 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5919 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 5920 enable = true;
5921 }
5922
d6dd9eb1
DV		 5923 intel_set_power_well(dev, enable);
5924}
5925
09b4ddf9 5926static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5927 int x, int y,
5928 struct drm_framebuffer *fb)
5929{
5930 struct drm_device *dev = crtc->dev;
5931 struct drm_i915_private *dev_priv = dev->dev_private;
5932 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 5933 int plane = intel_crtc->plane;
09b4ddf9 5934 int ret;
09b4ddf9 5935
ff9a6750 5936 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 5937 return -EINVAL;
5938
09b4ddf9
PZ		 5939 /* Ensure that the cursor is valid for the new mode before changing... */
5940 intel_crtc_update_cursor(crtc, true);
5941
03afc4a2
DV		 5942 if (intel_crtc->config.has_dp_encoder)
5943 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5944
5945 intel_crtc->lowfreq_avail = false;
09b4ddf9 5946
8a654f3b 5947 intel_set_pipe_timings(intel_crtc);
09b4ddf9 5948
ca3a0ff8 5949 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5950 intel_cpu_transcoder_set_m_n(intel_crtc,
5951 &intel_crtc->config.fdi_m_n);
5952 }
09b4ddf9 5953
6ff93609 5954 haswell_set_pipeconf(crtc);
09b4ddf9 5955
50f3b016 5956 intel_set_pipe_csc(crtc);
86d3efce 5957
09b4ddf9 5958 /* Set up the display plane register */
86d3efce 5959 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5960 POSTING_READ(DSPCNTR(plane));
5961
5962 ret = intel_pipe_set_base(crtc, x, y, fb);
5963
5964 intel_update_watermarks(dev);
5965
1f803ee5 5966 return ret;
79e53945
JB		 5967}
5968
0e8ffe1b
DV		 5969static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5970 struct intel_crtc_config *pipe_config)
5971{
5972 struct drm_device *dev = crtc->base.dev;
5973 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 5974 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 5975 uint32_t tmp;
5976
e143a21c 5977 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 5978 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
5979
eccb140b
DV		 5980 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5981 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5982 enum pipe trans_edp_pipe;
5983 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5984 default:
5985 WARN(1, "unknown pipe linked to edp transcoder\n");
5986 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5987 case TRANS_DDI_EDP_INPUT_A_ON:
5988 trans_edp_pipe = PIPE_A;
5989 break;
5990 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5991 trans_edp_pipe = PIPE_B;
5992 break;
5993 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5994 trans_edp_pipe = PIPE_C;
5995 break;
5996 }
5997
5998 if (trans_edp_pipe == crtc->pipe)
5999 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6000 }
6001
b97186f0 6002 if (!intel_display_power_enabled(dev,
eccb140b 6003 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6004 return false;
6005
eccb140b 6006 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6007 if (!(tmp & PIPECONF_ENABLE))
6008 return false;
6009
88adfff1 6010 /*
f196e6be 6011 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6012 * DDI E. So just check whether this pipe is wired to DDI E and whether
6013 * the PCH transcoder is on.
6014 */
eccb140b 6015 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6016 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6017 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6018 pipe_config->has_pch_encoder = true;
6019
627eb5a3
DV		 6020 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6021 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6022 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6023
6024 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6025 }
6026
1bd1bd80
DV		 6027 intel_get_pipe_timings(crtc, pipe_config);
6028
2fa2fe9a
DV		 6029 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6030 if (intel_display_power_enabled(dev, pfit_domain))
6031 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6032
42db64ef
PZ		 6033 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6034 (I915_READ(IPS_CTL) & IPS_ENABLE);
6035
6c49f241
DV		 6036 pipe_config->pixel_multiplier = 1;
6037
0e8ffe1b
DV		 6038 return true;
6039}
6040
f564048e 6041static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6042 int x, int y,
94352cf9 6043 struct drm_framebuffer *fb)
f564048e
EA		 6044{
6045 struct drm_device *dev = crtc->dev;
6046 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6047 struct drm_encoder_helper_funcs *encoder_funcs;
6048 struct intel_encoder *encoder;
0b701d27 6049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6050 struct drm_display_mode *adjusted_mode =
6051 &intel_crtc->config.adjusted_mode;
6052 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6053 int pipe = intel_crtc->pipe;
f564048e
EA		 6054 int ret;
6055
0b701d27 6056 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6057
b8cecdf5
DV		 6058 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6059
79e53945 6060 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6061
9256aa19
DV		 6062 if (ret != 0)
6063 return ret;
6064
6065 for_each_encoder_on_crtc(dev, crtc, encoder) {
6066 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6067 encoder->base.base.id,
6068 drm_get_encoder_name(&encoder->base),
6069 mode->base.id, mode->name);
6cc5f341
DV		 6070 if (encoder->mode_set) {
6071 encoder->mode_set(encoder);
6072 } else {
6073 encoder_funcs = encoder->base.helper_private;
6074 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6075 }
9256aa19
DV		 6076 }
6077
6078 return 0;
79e53945
JB		 6079}
6080
3a9627f4
WF		 6081static bool intel_eld_uptodate(struct drm_connector *connector,
6082 int reg_eldv, uint32_t bits_eldv,
6083 int reg_elda, uint32_t bits_elda,
6084 int reg_edid)
6085{
6086 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6087 uint8_t *eld = connector->eld;
6088 uint32_t i;
6089
6090 i = I915_READ(reg_eldv);
6091 i &= bits_eldv;
6092
6093 if (!eld[0])
6094 return !i;
6095
6096 if (!i)
6097 return false;
6098
6099 i = I915_READ(reg_elda);
6100 i &= ~bits_elda;
6101 I915_WRITE(reg_elda, i);
6102
6103 for (i = 0; i < eld[2]; i++)
6104 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6105 return false;
6106
6107 return true;
6108}
6109
e0dac65e
WF		 6110static void g4x_write_eld(struct drm_connector *connector,
6111 struct drm_crtc *crtc)
6112{
6113 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6114 uint8_t *eld = connector->eld;
6115 uint32_t eldv;
6116 uint32_t len;
6117 uint32_t i;
6118
6119 i = I915_READ(G4X_AUD_VID_DID);
6120
6121 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6122 eldv = G4X_ELDV_DEVCL_DEVBLC;
6123 else
6124 eldv = G4X_ELDV_DEVCTG;
6125
3a9627f4
WF		 6126 if (intel_eld_uptodate(connector,
6127 G4X_AUD_CNTL_ST, eldv,
6128 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6129 G4X_HDMIW_HDMIEDID))
6130 return;
6131
e0dac65e
WF		 6132 i = I915_READ(G4X_AUD_CNTL_ST);
6133 i &= ~(eldv | G4X_ELD_ADDR);
6134 len = (i >> 9) & 0x1f; /* ELD buffer size */
6135 I915_WRITE(G4X_AUD_CNTL_ST, i);
6136
6137 if (!eld[0])
6138 return;
6139
6140 len = min_t(uint8_t, eld[2], len);
6141 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6142 for (i = 0; i < len; i++)
6143 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6144
6145 i = I915_READ(G4X_AUD_CNTL_ST);
6146 i |= eldv;
6147 I915_WRITE(G4X_AUD_CNTL_ST, i);
6148}
6149
83358c85
WX		 6150static void haswell_write_eld(struct drm_connector *connector,
6151 struct drm_crtc *crtc)
6152{
6153 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6154 uint8_t *eld = connector->eld;
6155 struct drm_device *dev = crtc->dev;
7b9f35a6 6156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6157 uint32_t eldv;
6158 uint32_t i;
6159 int len;
6160 int pipe = to_intel_crtc(crtc)->pipe;
6161 int tmp;
6162
6163 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6164 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6165 int aud_config = HSW_AUD_CFG(pipe);
6166 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6167
6168
6169 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6170
6171 /* Audio output enable */
6172 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6173 tmp = I915_READ(aud_cntrl_st2);
6174 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6175 I915_WRITE(aud_cntrl_st2, tmp);
6176
6177 /* Wait for 1 vertical blank */
6178 intel_wait_for_vblank(dev, pipe);
6179
6180 /* Set ELD valid state */
6181 tmp = I915_READ(aud_cntrl_st2);
6182 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6183 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6184 I915_WRITE(aud_cntrl_st2, tmp);
6185 tmp = I915_READ(aud_cntrl_st2);
6186 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6187
6188 /* Enable HDMI mode */
6189 tmp = I915_READ(aud_config);
6190 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6191 /* clear N_programing_enable and N_value_index */
6192 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6193 I915_WRITE(aud_config, tmp);
6194
6195 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6196
6197 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6198 intel_crtc->eld_vld = true;
83358c85
WX		 6199
6200 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6201 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6202 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6203 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6204 } else
6205 I915_WRITE(aud_config, 0);
6206
6207 if (intel_eld_uptodate(connector,
6208 aud_cntrl_st2, eldv,
6209 aud_cntl_st, IBX_ELD_ADDRESS,
6210 hdmiw_hdmiedid))
6211 return;
6212
6213 i = I915_READ(aud_cntrl_st2);
6214 i &= ~eldv;
6215 I915_WRITE(aud_cntrl_st2, i);
6216
6217 if (!eld[0])
6218 return;
6219
6220 i = I915_READ(aud_cntl_st);
6221 i &= ~IBX_ELD_ADDRESS;
6222 I915_WRITE(aud_cntl_st, i);
6223 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6224 DRM_DEBUG_DRIVER("port num:%d\n", i);
6225
6226 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6227 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6228 for (i = 0; i < len; i++)
6229 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6230
6231 i = I915_READ(aud_cntrl_st2);
6232 i |= eldv;
6233 I915_WRITE(aud_cntrl_st2, i);
6234
6235}
6236
e0dac65e
WF		 6237static void ironlake_write_eld(struct drm_connector *connector,
6238 struct drm_crtc *crtc)
6239{
6240 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6241 uint8_t *eld = connector->eld;
6242 uint32_t eldv;
6243 uint32_t i;
6244 int len;
6245 int hdmiw_hdmiedid;
b6daa025 6246 int aud_config;
e0dac65e
WF		 6247 int aud_cntl_st;
6248 int aud_cntrl_st2;
9b138a83 6249 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6250
b3f33cbf 6251 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6252 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6253 aud_config = IBX_AUD_CFG(pipe);
6254 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6255 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6256 } else {
9b138a83
WX		 6257 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6258 aud_config = CPT_AUD_CFG(pipe);
6259 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6260 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6261 }
6262
9b138a83 6263 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6264
6265 i = I915_READ(aud_cntl_st);
9b138a83 6266 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6267 if (!i) {
6268 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6269 /* operate blindly on all ports */
1202b4c6
WF		 6270 eldv = IBX_ELD_VALIDB;
6271 eldv |= IBX_ELD_VALIDB << 4;
6272 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6273 } else {
2582a850 6274 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6275 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6276 }
6277
3a9627f4
WF		 6278 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6279 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6280 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6281 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6282 } else
6283 I915_WRITE(aud_config, 0);
e0dac65e 6284
3a9627f4
WF		 6285 if (intel_eld_uptodate(connector,
6286 aud_cntrl_st2, eldv,
6287 aud_cntl_st, IBX_ELD_ADDRESS,
6288 hdmiw_hdmiedid))
6289 return;
6290
e0dac65e
WF		 6291 i = I915_READ(aud_cntrl_st2);
6292 i &= ~eldv;
6293 I915_WRITE(aud_cntrl_st2, i);
6294
6295 if (!eld[0])
6296 return;
6297
e0dac65e 6298 i = I915_READ(aud_cntl_st);
1202b4c6 6299 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6300 I915_WRITE(aud_cntl_st, i);
6301
6302 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6303 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6304 for (i = 0; i < len; i++)
6305 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6306
6307 i = I915_READ(aud_cntrl_st2);
6308 i |= eldv;
6309 I915_WRITE(aud_cntrl_st2, i);
6310}
6311
6312void intel_write_eld(struct drm_encoder *encoder,
6313 struct drm_display_mode *mode)
6314{
6315 struct drm_crtc *crtc = encoder->crtc;
6316 struct drm_connector *connector;
6317 struct drm_device *dev = encoder->dev;
6318 struct drm_i915_private *dev_priv = dev->dev_private;
6319
6320 connector = drm_select_eld(encoder, mode);
6321 if (!connector)
6322 return;
6323
6324 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6325 connector->base.id,
6326 drm_get_connector_name(connector),
6327 connector->encoder->base.id,
6328 drm_get_encoder_name(connector->encoder));
6329
6330 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6331
6332 if (dev_priv->display.write_eld)
6333 dev_priv->display.write_eld(connector, crtc);
6334}
6335
79e53945
JB		 6336/** Loads the palette/gamma unit for the CRTC with the prepared values */
6337void intel_crtc_load_lut(struct drm_crtc *crtc)
6338{
6339 struct drm_device *dev = crtc->dev;
6340 struct drm_i915_private *dev_priv = dev->dev_private;
6341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6342 enum pipe pipe = intel_crtc->pipe;
6343 int palreg = PALETTE(pipe);
79e53945 6344 int i;
42db64ef 6345 bool reenable_ips = false;
79e53945
JB		 6346
6347 /* The clocks have to be on to load the palette. */
aed3f09d 6348 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6349 return;
6350
14420bd0
VS		 6351 if (!HAS_PCH_SPLIT(dev_priv->dev))
6352 assert_pll_enabled(dev_priv, pipe);
6353
f2b115e6 6354 /* use legacy palette for Ironlake */
bad720ff 6355 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6356 palreg = LGC_PALETTE(pipe);
6357
6358 /* Workaround : Do not read or write the pipe palette/gamma data while
6359 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6360 */
6361 if (intel_crtc->config.ips_enabled &&
6362 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6363 GAMMA_MODE_MODE_SPLIT)) {
6364 hsw_disable_ips(intel_crtc);
6365 reenable_ips = true;
6366 }
2c07245f 6367
79e53945
JB		 6368 for (i = 0; i < 256; i++) {
6369 I915_WRITE(palreg + 4 * i,
6370 (intel_crtc->lut_r[i] << 16) |
6371 (intel_crtc->lut_g[i] << 8) |
6372 intel_crtc->lut_b[i]);
6373 }
42db64ef
PZ		 6374
6375 if (reenable_ips)
6376 hsw_enable_ips(intel_crtc);
79e53945
JB		 6377}
6378
560b85bb
CW		 6379static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6380{
6381 struct drm_device *dev = crtc->dev;
6382 struct drm_i915_private *dev_priv = dev->dev_private;
6383 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6384 bool visible = base != 0;
6385 u32 cntl;
6386
6387 if (intel_crtc->cursor_visible == visible)
6388 return;
6389
9db4a9c7 6390 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6391 if (visible) {
6392 /* On these chipsets we can only modify the base whilst
6393 * the cursor is disabled.
6394 */
9db4a9c7 6395 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6396
6397 cntl &= ~(CURSOR_FORMAT_MASK);
6398 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6399 cntl |= CURSOR_ENABLE |
6400 CURSOR_GAMMA_ENABLE |
6401 CURSOR_FORMAT_ARGB;
6402 } else
6403 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6404 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6405
6406 intel_crtc->cursor_visible = visible;
6407}
6408
6409static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6410{
6411 struct drm_device *dev = crtc->dev;
6412 struct drm_i915_private *dev_priv = dev->dev_private;
6413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6414 int pipe = intel_crtc->pipe;
6415 bool visible = base != 0;
6416
6417 if (intel_crtc->cursor_visible != visible) {
548f245b 6418 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6419 if (base) {
6420 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6421 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6422 cntl |= pipe << 28; /* Connect to correct pipe */
6423 } else {
6424 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6425 cntl |= CURSOR_MODE_DISABLE;
6426 }
9db4a9c7 6427 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6428
6429 intel_crtc->cursor_visible = visible;
6430 }
6431 /* and commit changes on next vblank */
9db4a9c7 6432 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6433}
6434
65a21cd6
JB		 6435static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6436{
6437 struct drm_device *dev = crtc->dev;
6438 struct drm_i915_private *dev_priv = dev->dev_private;
6439 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6440 int pipe = intel_crtc->pipe;
6441 bool visible = base != 0;
6442
6443 if (intel_crtc->cursor_visible != visible) {
6444 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6445 if (base) {
6446 cntl &= ~CURSOR_MODE;
6447 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6448 } else {
6449 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6450 cntl |= CURSOR_MODE_DISABLE;
6451 }
86d3efce
VS		 6452 if (IS_HASWELL(dev))
6453 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6454 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6455
6456 intel_crtc->cursor_visible = visible;
6457 }
6458 /* and commit changes on next vblank */
6459 I915_WRITE(CURBASE_IVB(pipe), base);
6460}
6461
cda4b7d3 6462/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6463static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6464 bool on)
cda4b7d3
CW		 6465{
6466 struct drm_device *dev = crtc->dev;
6467 struct drm_i915_private *dev_priv = dev->dev_private;
6468 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6469 int pipe = intel_crtc->pipe;
6470 int x = intel_crtc->cursor_x;
6471 int y = intel_crtc->cursor_y;
560b85bb 6472 u32 base, pos;
cda4b7d3
CW		 6473 bool visible;
6474
6475 pos = 0;
6476
6b383a7f 6477 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6478 base = intel_crtc->cursor_addr;
6479 if (x > (int) crtc->fb->width)
6480 base = 0;
6481
6482 if (y > (int) crtc->fb->height)
6483 base = 0;
6484 } else
6485 base = 0;
6486
6487 if (x < 0) {
6488 if (x + intel_crtc->cursor_width < 0)
6489 base = 0;
6490
6491 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6492 x = -x;
6493 }
6494 pos |= x << CURSOR_X_SHIFT;
6495
6496 if (y < 0) {
6497 if (y + intel_crtc->cursor_height < 0)
6498 base = 0;
6499
6500 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6501 y = -y;
6502 }
6503 pos |= y << CURSOR_Y_SHIFT;
6504
6505 visible = base != 0;
560b85bb 6506 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6507 return;
6508
0cd83aa9 6509 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6510 I915_WRITE(CURPOS_IVB(pipe), pos);
6511 ivb_update_cursor(crtc, base);
6512 } else {
6513 I915_WRITE(CURPOS(pipe), pos);
6514 if (IS_845G(dev) || IS_I865G(dev))
6515 i845_update_cursor(crtc, base);
6516 else
6517 i9xx_update_cursor(crtc, base);
6518 }
cda4b7d3
CW		 6519}
6520
79e53945 6521static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6522 struct drm_file *file,
79e53945
JB		 6523 uint32_t handle,
6524 uint32_t width, uint32_t height)
6525{
6526 struct drm_device *dev = crtc->dev;
6527 struct drm_i915_private *dev_priv = dev->dev_private;
6528 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6529 struct drm_i915_gem_object *obj;
cda4b7d3 6530 uint32_t addr;
3f8bc370 6531 int ret;
79e53945 6532
79e53945
JB		 6533 /* if we want to turn off the cursor ignore width and height */
6534 if (!handle) {
28c97730 6535 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6536 addr = 0;
05394f39 6537 obj = NULL;
5004417d 6538 mutex_lock(&dev->struct_mutex);
3f8bc370 6539 goto finish;
79e53945
JB		 6540 }
6541
6542 /* Currently we only support 64x64 cursors */
6543 if (width != 64 || height != 64) {
6544 DRM_ERROR("we currently only support 64x64 cursors\n");
6545 return -EINVAL;
6546 }
6547
05394f39 6548 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6549 if (&obj->base == NULL)
79e53945
JB		 6550 return -ENOENT;
6551
05394f39 6552 if (obj->base.size < width * height * 4) {
79e53945 6553 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6554 ret = -ENOMEM;
6555 goto fail;
79e53945
JB		 6556 }
6557
71acb5eb 6558 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6559 mutex_lock(&dev->struct_mutex);
b295d1b6 6560 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6561 unsigned alignment;
6562
d9e86c0e
CW		 6563 if (obj->tiling_mode) {
6564 DRM_ERROR("cursor cannot be tiled\n");
6565 ret = -EINVAL;
6566 goto fail_locked;
6567 }
6568
693db184
CW		 6569 /* Note that the w/a also requires 2 PTE of padding following
6570 * the bo. We currently fill all unused PTE with the shadow
6571 * page and so we should always have valid PTE following the
6572 * cursor preventing the VT-d warning.
6573 */
6574 alignment = 0;
6575 if (need_vtd_wa(dev))
6576 alignment = 64*1024;
6577
6578 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6579 if (ret) {
6580 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6581 goto fail_locked;
e7b526bb
CW		 6582 }
6583
d9e86c0e
CW		 6584 ret = i915_gem_object_put_fence(obj);
6585 if (ret) {
2da3b9b9 6586 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6587 goto fail_unpin;
6588 }
6589
f343c5f6 6590 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 6591 } else {
6eeefaf3 6592 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6593 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6594 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6595 align);
71acb5eb
DA		 6596 if (ret) {
6597 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6598 goto fail_locked;
71acb5eb 6599 }
05394f39 6600 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6601 }
6602
a6c45cf0 6603 if (IS_GEN2(dev))
14b60391
JB		 6604 I915_WRITE(CURSIZE, (height << 12) | width);
6605
3f8bc370 6606 finish:
3f8bc370 6607 if (intel_crtc->cursor_bo) {
b295d1b6 6608 if (dev_priv->info->cursor_needs_physical) {
05394f39 6609 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6610 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6611 } else
6612 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6613 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6614 }
80824003 6615
7f9872e0 6616 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6617
6618 intel_crtc->cursor_addr = addr;
05394f39 6619 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6620 intel_crtc->cursor_width = width;
6621 intel_crtc->cursor_height = height;
6622
40ccc72b 6623 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6624
79e53945 6625 return 0;
e7b526bb 6626fail_unpin:
05394f39 6627 i915_gem_object_unpin(obj);
7f9872e0 6628fail_locked:
34b8686e 6629 mutex_unlock(&dev->struct_mutex);
bc9025bd 6630fail:
05394f39 6631 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6632 return ret;
79e53945
JB		 6633}
6634
6635static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6636{
79e53945 6637 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6638
cda4b7d3
CW		 6639 intel_crtc->cursor_x = x;
6640 intel_crtc->cursor_y = y;
652c393a 6641
40ccc72b 6642 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6643
6644 return 0;
6645}
6646
6647/** Sets the color ramps on behalf of RandR */
6648void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6649 u16 blue, int regno)
6650{
6651 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6652
6653 intel_crtc->lut_r[regno] = red >> 8;
6654 intel_crtc->lut_g[regno] = green >> 8;
6655 intel_crtc->lut_b[regno] = blue >> 8;
6656}
6657
b8c00ac5
DA		 6658void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6659 u16 *blue, int regno)
6660{
6661 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6662
6663 *red = intel_crtc->lut_r[regno] << 8;
6664 *green = intel_crtc->lut_g[regno] << 8;
6665 *blue = intel_crtc->lut_b[regno] << 8;
6666}
6667
79e53945 6668static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6669 u16 *blue, uint32_t start, uint32_t size)
79e53945 6670{
7203425a 6671 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6672 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6673
7203425a 6674 for (i = start; i < end; i++) {
79e53945
JB		 6675 intel_crtc->lut_r[i] = red[i] >> 8;
6676 intel_crtc->lut_g[i] = green[i] >> 8;
6677 intel_crtc->lut_b[i] = blue[i] >> 8;
6678 }
6679
6680 intel_crtc_load_lut(crtc);
6681}
6682
79e53945
JB		 6683/* VESA 640x480x72Hz mode to set on the pipe */
6684static struct drm_display_mode load_detect_mode = {
6685 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6686 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6687};
6688
d2dff872
CW		 6689static struct drm_framebuffer *
6690intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6691 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6692 struct drm_i915_gem_object *obj)
6693{
6694 struct intel_framebuffer *intel_fb;
6695 int ret;
6696
6697 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6698 if (!intel_fb) {
6699 drm_gem_object_unreference_unlocked(&obj->base);
6700 return ERR_PTR(-ENOMEM);
6701 }
6702
6703 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6704 if (ret) {
6705 drm_gem_object_unreference_unlocked(&obj->base);
6706 kfree(intel_fb);
6707 return ERR_PTR(ret);
6708 }
6709
6710 return &intel_fb->base;
6711}
6712
6713static u32
6714intel_framebuffer_pitch_for_width(int width, int bpp)
6715{
6716 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6717 return ALIGN(pitch, 64);
6718}
6719
6720static u32
6721intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6722{
6723 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6724 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6725}
6726
6727static struct drm_framebuffer *
6728intel_framebuffer_create_for_mode(struct drm_device *dev,
6729 struct drm_display_mode *mode,
6730 int depth, int bpp)
6731{
6732 struct drm_i915_gem_object *obj;
0fed39bd 6733 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6734
6735 obj = i915_gem_alloc_object(dev,
6736 intel_framebuffer_size_for_mode(mode, bpp));
6737 if (obj == NULL)
6738 return ERR_PTR(-ENOMEM);
6739
6740 mode_cmd.width = mode->hdisplay;
6741 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6742 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6743 bpp);
5ca0c34a 6744 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6745
6746 return intel_framebuffer_create(dev, &mode_cmd, obj);
6747}
6748
6749static struct drm_framebuffer *
6750mode_fits_in_fbdev(struct drm_device *dev,
6751 struct drm_display_mode *mode)
6752{
6753 struct drm_i915_private *dev_priv = dev->dev_private;
6754 struct drm_i915_gem_object *obj;
6755 struct drm_framebuffer *fb;
6756
6757 if (dev_priv->fbdev == NULL)
6758 return NULL;
6759
6760 obj = dev_priv->fbdev->ifb.obj;
6761 if (obj == NULL)
6762 return NULL;
6763
6764 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6765 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6766 fb->bits_per_pixel))
d2dff872
CW		 6767 return NULL;
6768
01f2c773 6769 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6770 return NULL;
6771
6772 return fb;
6773}
6774
d2434ab7 6775bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6776 struct drm_display_mode *mode,
8261b191 6777 struct intel_load_detect_pipe *old)
79e53945
JB		 6778{
6779 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6780 struct intel_encoder *intel_encoder =
6781 intel_attached_encoder(connector);
79e53945 6782 struct drm_crtc *possible_crtc;
4ef69c7a 6783 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6784 struct drm_crtc *crtc = NULL;
6785 struct drm_device *dev = encoder->dev;
94352cf9 6786 struct drm_framebuffer *fb;
79e53945
JB		 6787 int i = -1;
6788
d2dff872
CW		 6789 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6790 connector->base.id, drm_get_connector_name(connector),
6791 encoder->base.id, drm_get_encoder_name(encoder));
6792
79e53945
JB		 6793 /*
6794 * Algorithm gets a little messy:
7a5e4805 6795 *
79e53945
JB		 6796 * - if the connector already has an assigned crtc, use it (but make
6797 * sure it's on first)
7a5e4805 6798 *
79e53945
JB		 6799 * - try to find the first unused crtc that can drive this connector,
6800 * and use that if we find one
79e53945
JB		 6801 */
6802
6803 /* See if we already have a CRTC for this connector */
6804 if (encoder->crtc) {
6805 crtc = encoder->crtc;
8261b191 6806
7b24056b
DV		 6807 mutex_lock(&crtc->mutex);
6808
24218aac 6809 old->dpms_mode = connector->dpms;
8261b191
CW		 6810 old->load_detect_temp = false;
6811
6812 /* Make sure the crtc and connector are running */
24218aac
DV		 6813 if (connector->dpms != DRM_MODE_DPMS_ON)
6814 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6815
7173188d 6816 return true;
79e53945
JB		 6817 }
6818
6819 /* Find an unused one (if possible) */
6820 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6821 i++;
6822 if (!(encoder->possible_crtcs & (1 << i)))
6823 continue;
6824 if (!possible_crtc->enabled) {
6825 crtc = possible_crtc;
6826 break;
6827 }
79e53945
JB		 6828 }
6829
6830 /*
6831 * If we didn't find an unused CRTC, don't use any.
6832 */
6833 if (!crtc) {
7173188d
CW		 6834 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6835 return false;
79e53945
JB		 6836 }
6837
7b24056b 6838 mutex_lock(&crtc->mutex);
fc303101
DV		 6839 intel_encoder->new_crtc = to_intel_crtc(crtc);
6840 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6841
6842 intel_crtc = to_intel_crtc(crtc);
24218aac 6843 old->dpms_mode = connector->dpms;
8261b191 6844 old->load_detect_temp = true;
d2dff872 6845 old->release_fb = NULL;
79e53945 6846
6492711d
CW		 6847 if (!mode)
6848 mode = &load_detect_mode;
79e53945 6849
d2dff872
CW		 6850 /* We need a framebuffer large enough to accommodate all accesses
6851 * that the plane may generate whilst we perform load detection.
6852 * We can not rely on the fbcon either being present (we get called
6853 * during its initialisation to detect all boot displays, or it may
6854 * not even exist) or that it is large enough to satisfy the
6855 * requested mode.
6856 */
94352cf9
DV		 6857 fb = mode_fits_in_fbdev(dev, mode);
6858 if (fb == NULL) {
d2dff872 6859 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6860 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6861 old->release_fb = fb;
d2dff872
CW		 6862 } else
6863 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6864 if (IS_ERR(fb)) {
d2dff872 6865 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6866 mutex_unlock(&crtc->mutex);
0e8b3d3e 6867 return false;
79e53945 6868 }
79e53945 6869
c0c36b94 6870 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6871 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6872 if (old->release_fb)
6873 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6874 mutex_unlock(&crtc->mutex);
0e8b3d3e 6875 return false;
79e53945 6876 }
7173188d 6877
79e53945 6878 /* let the connector get through one full cycle before testing */
9d0498a2 6879 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6880 return true;
79e53945
JB		 6881}
6882
d2434ab7 6883void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6884 struct intel_load_detect_pipe *old)
79e53945 6885{
d2434ab7
DV		 6886 struct intel_encoder *intel_encoder =
6887 intel_attached_encoder(connector);
4ef69c7a 6888 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6889 struct drm_crtc *crtc = encoder->crtc;
79e53945 6890
d2dff872
CW		 6891 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6892 connector->base.id, drm_get_connector_name(connector),
6893 encoder->base.id, drm_get_encoder_name(encoder));
6894
8261b191 6895 if (old->load_detect_temp) {
fc303101
DV		 6896 to_intel_connector(connector)->new_encoder = NULL;
6897 intel_encoder->new_crtc = NULL;
6898 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6899
36206361
DV		 6900 if (old->release_fb) {
6901 drm_framebuffer_unregister_private(old->release_fb);
6902 drm_framebuffer_unreference(old->release_fb);
6903 }
d2dff872 6904
67c96400 6905 mutex_unlock(&crtc->mutex);
0622a53c 6906 return;
79e53945
JB		 6907 }
6908
c751ce4f 6909 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6910 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6911 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6912
6913 mutex_unlock(&crtc->mutex);
79e53945
JB		 6914}
6915
6916/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 6917static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
6918 struct intel_crtc_config *pipe_config)
79e53945 6919{
f1f644dc 6920 struct drm_device *dev = crtc->base.dev;
79e53945 6921 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 6922 int pipe = pipe_config->cpu_transcoder;
548f245b 6923 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6924 u32 fp;
6925 intel_clock_t clock;
6926
6927 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6928 fp = I915_READ(FP0(pipe));
79e53945 6929 else
39adb7a5 6930 fp = I915_READ(FP1(pipe));
79e53945
JB		 6931
6932 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6933 if (IS_PINEVIEW(dev)) {
6934 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6935 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6936 } else {
6937 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6938 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6939 }
6940
a6c45cf0 6941 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6942 if (IS_PINEVIEW(dev))
6943 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6944 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6945 else
6946 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6947 DPLL_FPA01_P1_POST_DIV_SHIFT);
6948
6949 switch (dpll & DPLL_MODE_MASK) {
6950 case DPLLB_MODE_DAC_SERIAL:
6951 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6952 5 : 10;
6953 break;
6954 case DPLLB_MODE_LVDS:
6955 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6956 7 : 14;
6957 break;
6958 default:
28c97730 6959 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 6960 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc
JB		 6961 pipe_config->adjusted_mode.clock = 0;
6962 return;
79e53945
JB		 6963 }
6964
ac58c3f0
DV		 6965 if (IS_PINEVIEW(dev))
6966 pineview_clock(96000, &clock);
6967 else
6968 i9xx_clock(96000, &clock);
79e53945
JB		 6969 } else {
6970 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6971
6972 if (is_lvds) {
6973 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6974 DPLL_FPA01_P1_POST_DIV_SHIFT);
6975 clock.p2 = 14;
6976
6977 if ((dpll & PLL_REF_INPUT_MASK) ==
6978 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6979 /* XXX: might not be 66MHz */
ac58c3f0 6980 i9xx_clock(66000, &clock);
79e53945 6981 } else
ac58c3f0 6982 i9xx_clock(48000, &clock);
79e53945
JB		 6983 } else {
6984 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6985 clock.p1 = 2;
6986 else {
6987 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6988 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6989 }
6990 if (dpll & PLL_P2_DIVIDE_BY_4)
6991 clock.p2 = 4;
6992 else
6993 clock.p2 = 2;
6994
ac58c3f0 6995 i9xx_clock(48000, &clock);
79e53945
JB		 6996 }
6997 }
6998
f1f644dc
JB		 6999 pipe_config->adjusted_mode.clock = clock.dot *
7000 pipe_config->pixel_multiplier;
7001}
7002
7003static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
7004 struct intel_crtc_config *pipe_config)
7005{
7006 struct drm_device *dev = crtc->base.dev;
7007 struct drm_i915_private *dev_priv = dev->dev_private;
7008 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
7009 int link_freq, repeat;
7010 u64 clock;
7011 u32 link_m, link_n;
7012
7013 repeat = pipe_config->pixel_multiplier;
7014
7015 /*
7016 * The calculation for the data clock is:
7017 * pixel_clock = ((m/n)*(link_clock * nr_lanes * repeat))/bpp
7018 * But we want to avoid losing precison if possible, so:
7019 * pixel_clock = ((m * link_clock * nr_lanes * repeat)/(n*bpp))
7020 *
7021 * and the link clock is simpler:
7022 * link_clock = (m * link_clock * repeat) / n
7023 */
7024
7025 /*
7026 * We need to get the FDI or DP link clock here to derive
7027 * the M/N dividers.
7028 *
7029 * For FDI, we read it from the BIOS or use a fixed 2.7GHz.
7030 * For DP, it's either 1.62GHz or 2.7GHz.
7031 * We do our calculations in 10*MHz since we don't need much precison.
79e53945 7032 */
f1f644dc
JB		 7033 if (pipe_config->has_pch_encoder)
7034 link_freq = intel_fdi_link_freq(dev) * 10000;
7035 else
7036 link_freq = pipe_config->port_clock;
7037
7038 link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
7039 link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
7040
7041 if (!link_m || !link_n)
7042 return;
79e53945 7043
f1f644dc
JB		 7044 clock = ((u64)link_m * (u64)link_freq * (u64)repeat);
7045 do_div(clock, link_n);
7046
7047 pipe_config->adjusted_mode.clock = clock;
79e53945
JB		 7048}
7049
7050/** Returns the currently programmed mode of the given pipe. */
7051struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7052 struct drm_crtc *crtc)
7053{
548f245b 7054 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7055 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7056 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7057 struct drm_display_mode *mode;
f1f644dc 7058 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7059 int htot = I915_READ(HTOTAL(cpu_transcoder));
7060 int hsync = I915_READ(HSYNC(cpu_transcoder));
7061 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7062 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 7063
7064 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7065 if (!mode)
7066 return NULL;
7067
f1f644dc
JB		 7068 /*
7069 * Construct a pipe_config sufficient for getting the clock info
7070 * back out of crtc_clock_get.
7071 *
7072 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7073 * to use a real value here instead.
7074 */
e143a21c 7075 pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe;
f1f644dc
JB		 7076 pipe_config.pixel_multiplier = 1;
7077 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7078
7079 mode->clock = pipe_config.adjusted_mode.clock;
79e53945
JB		 7080 mode->hdisplay = (htot & 0xffff) + 1;
7081 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7082 mode->hsync_start = (hsync & 0xffff) + 1;
7083 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7084 mode->vdisplay = (vtot & 0xffff) + 1;
7085 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7086 mode->vsync_start = (vsync & 0xffff) + 1;
7087 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7088
7089 drm_mode_set_name(mode);
79e53945
JB		 7090
7091 return mode;
7092}
7093
3dec0095 7094static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7095{
7096 struct drm_device *dev = crtc->dev;
7097 drm_i915_private_t *dev_priv = dev->dev_private;
7098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7099 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7100 int dpll_reg = DPLL(pipe);
7101 int dpll;
652c393a 7102
bad720ff 7103 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7104 return;
7105
7106 if (!dev_priv->lvds_downclock_avail)
7107 return;
7108
dbdc6479 7109 dpll = I915_READ(dpll_reg);
652c393a 7110 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7111 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7112
8ac5a6d5 7113 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7114
7115 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7116 I915_WRITE(dpll_reg, dpll);
9d0498a2 7117 intel_wait_for_vblank(dev, pipe);
dbdc6479 7118
652c393a
JB		 7119 dpll = I915_READ(dpll_reg);
7120 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7121 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7122 }
652c393a
JB		 7123}
7124
7125static void intel_decrease_pllclock(struct drm_crtc *crtc)
7126{
7127 struct drm_device *dev = crtc->dev;
7128 drm_i915_private_t *dev_priv = dev->dev_private;
7129 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7130
bad720ff 7131 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7132 return;
7133
7134 if (!dev_priv->lvds_downclock_avail)
7135 return;
7136
7137 /*
7138 * Since this is called by a timer, we should never get here in
7139 * the manual case.
7140 */
7141 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7142 int pipe = intel_crtc->pipe;
7143 int dpll_reg = DPLL(pipe);
7144 int dpll;
f6e5b160 7145
44d98a61 7146 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7147
8ac5a6d5 7148 assert_panel_unlocked(dev_priv, pipe);
652c393a 7149
dc257cf1 7150 dpll = I915_READ(dpll_reg);
652c393a
JB		 7151 dpll |= DISPLAY_RATE_SELECT_FPA1;
7152 I915_WRITE(dpll_reg, dpll);
9d0498a2 7153 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7154 dpll = I915_READ(dpll_reg);
7155 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7156 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7157 }
7158
7159}
7160
f047e395
CW		 7161void intel_mark_busy(struct drm_device *dev)
7162{
f047e395
CW		 7163 i915_update_gfx_val(dev->dev_private);
7164}
7165
7166void intel_mark_idle(struct drm_device *dev)
652c393a 7167{
652c393a 7168 struct drm_crtc *crtc;
652c393a
JB		 7169
7170 if (!i915_powersave)
7171 return;
7172
652c393a 7173 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7174 if (!crtc->fb)
7175 continue;
7176
725a5b54 7177 intel_decrease_pllclock(crtc);
652c393a 7178 }
652c393a
JB		 7179}
7180
c65355bb
CW		 7181void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7182 struct intel_ring_buffer *ring)
652c393a 7183{
f047e395
CW		 7184 struct drm_device *dev = obj->base.dev;
7185 struct drm_crtc *crtc;
652c393a 7186
f047e395 7187 if (!i915_powersave)
acb87dfb
CW		 7188 return;
7189
652c393a
JB		 7190 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7191 if (!crtc->fb)
7192 continue;
7193
c65355bb
CW		 7194 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7195 continue;
7196
7197 intel_increase_pllclock(crtc);
7198 if (ring && intel_fbc_enabled(dev))
7199 ring->fbc_dirty = true;
652c393a
JB		 7200 }
7201}
7202
79e53945
JB		 7203static void intel_crtc_destroy(struct drm_crtc *crtc)
7204{
7205 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7206 struct drm_device *dev = crtc->dev;
7207 struct intel_unpin_work *work;
7208 unsigned long flags;
7209
7210 spin_lock_irqsave(&dev->event_lock, flags);
7211 work = intel_crtc->unpin_work;
7212 intel_crtc->unpin_work = NULL;
7213 spin_unlock_irqrestore(&dev->event_lock, flags);
7214
7215 if (work) {
7216 cancel_work_sync(&work->work);
7217 kfree(work);
7218 }
79e53945 7219
40ccc72b
MK		 7220 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7221
79e53945 7222 drm_crtc_cleanup(crtc);
67e77c5a 7223
79e53945
JB		 7224 kfree(intel_crtc);
7225}
7226
6b95a207
KH		 7227static void intel_unpin_work_fn(struct work_struct *__work)
7228{
7229 struct intel_unpin_work *work =
7230 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7231 struct drm_device *dev = work->crtc->dev;
6b95a207 7232
b4a98e57 7233 mutex_lock(&dev->struct_mutex);
1690e1eb 7234 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7235 drm_gem_object_unreference(&work->pending_flip_obj->base);
7236 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7237
b4a98e57
CW		 7238 intel_update_fbc(dev);
7239 mutex_unlock(&dev->struct_mutex);
7240
7241 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7242 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7243
6b95a207
KH		 7244 kfree(work);
7245}
7246
1afe3e9d 7247static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7248 struct drm_crtc *crtc)
6b95a207
KH		 7249{
7250 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7252 struct intel_unpin_work *work;
6b95a207
KH		 7253 unsigned long flags;
7254
7255 /* Ignore early vblank irqs */
7256 if (intel_crtc == NULL)
7257 return;
7258
7259 spin_lock_irqsave(&dev->event_lock, flags);
7260 work = intel_crtc->unpin_work;
e7d841ca
CW		 7261
7262 /* Ensure we don't miss a work->pending update ... */
7263 smp_rmb();
7264
7265 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7266 spin_unlock_irqrestore(&dev->event_lock, flags);
7267 return;
7268 }
7269
e7d841ca
CW		 7270 /* and that the unpin work is consistent wrt ->pending. */
7271 smp_rmb();
7272
6b95a207 7273 intel_crtc->unpin_work = NULL;
6b95a207 7274
45a066eb
RC		 7275 if (work->event)
7276 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7277
0af7e4df
MK		 7278 drm_vblank_put(dev, intel_crtc->pipe);
7279
6b95a207
KH		 7280 spin_unlock_irqrestore(&dev->event_lock, flags);
7281
2c10d571 7282 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7283
7284 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7285
7286 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7287}
7288
1afe3e9d
JB		 7289void intel_finish_page_flip(struct drm_device *dev, int pipe)
7290{
7291 drm_i915_private_t *dev_priv = dev->dev_private;
7292 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7293
49b14a5c 7294 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7295}
7296
7297void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7298{
7299 drm_i915_private_t *dev_priv = dev->dev_private;
7300 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7301
49b14a5c 7302 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7303}
7304
6b95a207
KH		 7305void intel_prepare_page_flip(struct drm_device *dev, int plane)
7306{
7307 drm_i915_private_t *dev_priv = dev->dev_private;
7308 struct intel_crtc *intel_crtc =
7309 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7310 unsigned long flags;
7311
e7d841ca
CW		 7312 /* NB: An MMIO update of the plane base pointer will also
7313 * generate a page-flip completion irq, i.e. every modeset
7314 * is also accompanied by a spurious intel_prepare_page_flip().
7315 */
6b95a207 7316 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7317 if (intel_crtc->unpin_work)
7318 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7319 spin_unlock_irqrestore(&dev->event_lock, flags);
7320}
7321
e7d841ca
CW		 7322inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7323{
7324 /* Ensure that the work item is consistent when activating it ... */
7325 smp_wmb();
7326 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7327 /* and that it is marked active as soon as the irq could fire. */
7328 smp_wmb();
7329}
7330
8c9f3aaf
JB		 7331static int intel_gen2_queue_flip(struct drm_device *dev,
7332 struct drm_crtc *crtc,
7333 struct drm_framebuffer *fb,
7334 struct drm_i915_gem_object *obj)
7335{
7336 struct drm_i915_private *dev_priv = dev->dev_private;
7337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7338 u32 flip_mask;
6d90c952 7339 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7340 int ret;
7341
6d90c952 7342 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7343 if (ret)
83d4092b 7344 goto err;
8c9f3aaf 7345
6d90c952 7346 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7347 if (ret)
83d4092b 7348 goto err_unpin;
8c9f3aaf
JB		 7349
7350 /* Can't queue multiple flips, so wait for the previous
7351 * one to finish before executing the next.
7352 */
7353 if (intel_crtc->plane)
7354 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7355 else
7356 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7357 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7358 intel_ring_emit(ring, MI_NOOP);
7359 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7360 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7361 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7362 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7363 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7364
7365 intel_mark_page_flip_active(intel_crtc);
6d90c952 7366 intel_ring_advance(ring);
83d4092b
CW		 7367 return 0;
7368
7369err_unpin:
7370 intel_unpin_fb_obj(obj);
7371err:
8c9f3aaf
JB		 7372 return ret;
7373}
7374
7375static int intel_gen3_queue_flip(struct drm_device *dev,
7376 struct drm_crtc *crtc,
7377 struct drm_framebuffer *fb,
7378 struct drm_i915_gem_object *obj)
7379{
7380 struct drm_i915_private *dev_priv = dev->dev_private;
7381 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7382 u32 flip_mask;
6d90c952 7383 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7384 int ret;
7385
6d90c952 7386 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7387 if (ret)
83d4092b 7388 goto err;
8c9f3aaf 7389
6d90c952 7390 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7391 if (ret)
83d4092b 7392 goto err_unpin;
8c9f3aaf
JB		 7393
7394 if (intel_crtc->plane)
7395 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7396 else
7397 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7398 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7399 intel_ring_emit(ring, MI_NOOP);
7400 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7401 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7402 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7403 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7404 intel_ring_emit(ring, MI_NOOP);
7405
e7d841ca 7406 intel_mark_page_flip_active(intel_crtc);
6d90c952 7407 intel_ring_advance(ring);
83d4092b
CW		 7408 return 0;
7409
7410err_unpin:
7411 intel_unpin_fb_obj(obj);
7412err:
8c9f3aaf
JB		 7413 return ret;
7414}
7415
7416static int intel_gen4_queue_flip(struct drm_device *dev,
7417 struct drm_crtc *crtc,
7418 struct drm_framebuffer *fb,
7419 struct drm_i915_gem_object *obj)
7420{
7421 struct drm_i915_private *dev_priv = dev->dev_private;
7422 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7423 uint32_t pf, pipesrc;
6d90c952 7424 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7425 int ret;
7426
6d90c952 7427 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7428 if (ret)
83d4092b 7429 goto err;
8c9f3aaf 7430
6d90c952 7431 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7432 if (ret)
83d4092b 7433 goto err_unpin;
8c9f3aaf
JB		 7434
7435 /* i965+ uses the linear or tiled offsets from the
7436 * Display Registers (which do not change across a page-flip)
7437 * so we need only reprogram the base address.
7438 */
6d90c952
DV		 7439 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7440 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7441 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 7442 intel_ring_emit(ring,
f343c5f6 7443 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 7444 obj->tiling_mode);
8c9f3aaf
JB		 7445
7446 /* XXX Enabling the panel-fitter across page-flip is so far
7447 * untested on non-native modes, so ignore it for now.
7448 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7449 */
7450 pf = 0;
7451 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7452 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7453
7454 intel_mark_page_flip_active(intel_crtc);
6d90c952 7455 intel_ring_advance(ring);
83d4092b
CW		 7456 return 0;
7457
7458err_unpin:
7459 intel_unpin_fb_obj(obj);
7460err:
8c9f3aaf
JB		 7461 return ret;
7462}
7463
7464static int intel_gen6_queue_flip(struct drm_device *dev,
7465 struct drm_crtc *crtc,
7466 struct drm_framebuffer *fb,
7467 struct drm_i915_gem_object *obj)
7468{
7469 struct drm_i915_private *dev_priv = dev->dev_private;
7470 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7471 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7472 uint32_t pf, pipesrc;
7473 int ret;
7474
6d90c952 7475 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7476 if (ret)
83d4092b 7477 goto err;
8c9f3aaf 7478
6d90c952 7479 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7480 if (ret)
83d4092b 7481 goto err_unpin;
8c9f3aaf 7482
6d90c952
DV		 7483 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7484 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7485 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 7486 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 7487
dc257cf1
DV		 7488 /* Contrary to the suggestions in the documentation,
7489 * "Enable Panel Fitter" does not seem to be required when page
7490 * flipping with a non-native mode, and worse causes a normal
7491 * modeset to fail.
7492 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7493 */
7494 pf = 0;
8c9f3aaf 7495 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7496 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7497
7498 intel_mark_page_flip_active(intel_crtc);
6d90c952 7499 intel_ring_advance(ring);
83d4092b
CW		 7500 return 0;
7501
7502err_unpin:
7503 intel_unpin_fb_obj(obj);
7504err:
8c9f3aaf
JB		 7505 return ret;
7506}
7507
7c9017e5
JB		 7508/*
7509 * On gen7 we currently use the blit ring because (in early silicon at least)
7510 * the render ring doesn't give us interrpts for page flip completion, which
7511 * means clients will hang after the first flip is queued. Fortunately the
7512 * blit ring generates interrupts properly, so use it instead.
7513 */
7514static int intel_gen7_queue_flip(struct drm_device *dev,
7515 struct drm_crtc *crtc,
7516 struct drm_framebuffer *fb,
7517 struct drm_i915_gem_object *obj)
7518{
7519 struct drm_i915_private *dev_priv = dev->dev_private;
7520 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7521 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7522 uint32_t plane_bit = 0;
7c9017e5
JB		 7523 int ret;
7524
7525 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7526 if (ret)
83d4092b 7527 goto err;
7c9017e5 7528
cb05d8de
DV		 7529 switch(intel_crtc->plane) {
7530 case PLANE_A:
7531 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7532 break;
7533 case PLANE_B:
7534 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7535 break;
7536 case PLANE_C:
7537 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7538 break;
7539 default:
7540 WARN_ONCE(1, "unknown plane in flip command\n");
7541 ret = -ENODEV;
ab3951eb 7542 goto err_unpin;
cb05d8de
DV		 7543 }
7544
7c9017e5
JB		 7545 ret = intel_ring_begin(ring, 4);
7546 if (ret)
83d4092b 7547 goto err_unpin;
7c9017e5 7548
cb05d8de 7549 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7550 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 7551 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 7552 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7553
7554 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7555 intel_ring_advance(ring);
83d4092b
CW		 7556 return 0;
7557
7558err_unpin:
7559 intel_unpin_fb_obj(obj);
7560err:
7c9017e5
JB		 7561 return ret;
7562}
7563
8c9f3aaf
JB		 7564static int intel_default_queue_flip(struct drm_device *dev,
7565 struct drm_crtc *crtc,
7566 struct drm_framebuffer *fb,
7567 struct drm_i915_gem_object *obj)
7568{
7569 return -ENODEV;
7570}
7571
6b95a207
KH		 7572static int intel_crtc_page_flip(struct drm_crtc *crtc,
7573 struct drm_framebuffer *fb,
7574 struct drm_pending_vblank_event *event)
7575{
7576 struct drm_device *dev = crtc->dev;
7577 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7578 struct drm_framebuffer *old_fb = crtc->fb;
7579 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7580 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7581 struct intel_unpin_work *work;
8c9f3aaf 7582 unsigned long flags;
52e68630 7583 int ret;
6b95a207 7584
e6a595d2
VS		 7585 /* Can't change pixel format via MI display flips. */
7586 if (fb->pixel_format != crtc->fb->pixel_format)
7587 return -EINVAL;
7588
7589 /*
7590 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7591 * Note that pitch changes could also affect these register.
7592 */
7593 if (INTEL_INFO(dev)->gen > 3 &&
7594 (fb->offsets[0] != crtc->fb->offsets[0] ||
7595 fb->pitches[0] != crtc->fb->pitches[0]))
7596 return -EINVAL;
7597
6b95a207
KH		 7598 work = kzalloc(sizeof *work, GFP_KERNEL);
7599 if (work == NULL)
7600 return -ENOMEM;
7601
6b95a207 7602 work->event = event;
b4a98e57 7603 work->crtc = crtc;
4a35f83b 7604 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7605 INIT_WORK(&work->work, intel_unpin_work_fn);
7606
7317c75e
JB		 7607 ret = drm_vblank_get(dev, intel_crtc->pipe);
7608 if (ret)
7609 goto free_work;
7610
6b95a207
KH		 7611 /* We borrow the event spin lock for protecting unpin_work */
7612 spin_lock_irqsave(&dev->event_lock, flags);
7613 if (intel_crtc->unpin_work) {
7614 spin_unlock_irqrestore(&dev->event_lock, flags);
7615 kfree(work);
7317c75e 7616 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7617
7618 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7619 return -EBUSY;
7620 }
7621 intel_crtc->unpin_work = work;
7622 spin_unlock_irqrestore(&dev->event_lock, flags);
7623
b4a98e57
CW		 7624 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7625 flush_workqueue(dev_priv->wq);
7626
79158103
CW		 7627 ret = i915_mutex_lock_interruptible(dev);
7628 if (ret)
7629 goto cleanup;
6b95a207 7630
75dfca80 7631 /* Reference the objects for the scheduled work. */
05394f39
CW		 7632 drm_gem_object_reference(&work->old_fb_obj->base);
7633 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7634
7635 crtc->fb = fb;
96b099fd 7636
e1f99ce6 7637 work->pending_flip_obj = obj;
e1f99ce6 7638
4e5359cd
SF		 7639 work->enable_stall_check = true;
7640
b4a98e57 7641 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7642 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7643
8c9f3aaf
JB		 7644 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7645 if (ret)
7646 goto cleanup_pending;
6b95a207 7647
7782de3b 7648 intel_disable_fbc(dev);
c65355bb 7649 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 7650 mutex_unlock(&dev->struct_mutex);
7651
e5510fac
JB		 7652 trace_i915_flip_request(intel_crtc->plane, obj);
7653
6b95a207 7654 return 0;
96b099fd 7655
8c9f3aaf 7656cleanup_pending:
b4a98e57 7657 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7658 crtc->fb = old_fb;
05394f39
CW		 7659 drm_gem_object_unreference(&work->old_fb_obj->base);
7660 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7661 mutex_unlock(&dev->struct_mutex);
7662
79158103 7663cleanup:
96b099fd
CW		 7664 spin_lock_irqsave(&dev->event_lock, flags);
7665 intel_crtc->unpin_work = NULL;
7666 spin_unlock_irqrestore(&dev->event_lock, flags);
7667
7317c75e
JB		 7668 drm_vblank_put(dev, intel_crtc->pipe);
7669free_work:
96b099fd
CW		 7670 kfree(work);
7671
7672 return ret;
6b95a207
KH		 7673}
7674
f6e5b160 7675static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7676 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7677 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7678};
7679
50f56119
DV		 7680static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7681 struct drm_crtc *crtc)
7682{
7683 struct drm_device *dev;
7684 struct drm_crtc *tmp;
7685 int crtc_mask = 1;
47f1c6c9 7686
50f56119 7687 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7688
50f56119 7689 dev = crtc->dev;
47f1c6c9 7690
50f56119
DV		 7691 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7692 if (tmp == crtc)
7693 break;
7694 crtc_mask <<= 1;
7695 }
47f1c6c9 7696
50f56119
DV		 7697 if (encoder->possible_crtcs & crtc_mask)
7698 return true;
7699 return false;
47f1c6c9 7700}
79e53945 7701
9a935856
DV		 7702/**
7703 * intel_modeset_update_staged_output_state
7704 *
7705 * Updates the staged output configuration state, e.g. after we've read out the
7706 * current hw state.
7707 */
7708static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7709{
9a935856
DV		 7710 struct intel_encoder *encoder;
7711 struct intel_connector *connector;
f6e5b160 7712
9a935856
DV		 7713 list_for_each_entry(connector, &dev->mode_config.connector_list,
7714 base.head) {
7715 connector->new_encoder =
7716 to_intel_encoder(connector->base.encoder);
7717 }
f6e5b160 7718
9a935856
DV		 7719 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7720 base.head) {
7721 encoder->new_crtc =
7722 to_intel_crtc(encoder->base.crtc);
7723 }
f6e5b160
CW		 7724}
7725
9a935856
DV		 7726/**
7727 * intel_modeset_commit_output_state
7728 *
7729 * This function copies the stage display pipe configuration to the real one.
7730 */
7731static void intel_modeset_commit_output_state(struct drm_device *dev)
7732{
7733 struct intel_encoder *encoder;
7734 struct intel_connector *connector;
f6e5b160 7735
9a935856
DV		 7736 list_for_each_entry(connector, &dev->mode_config.connector_list,
7737 base.head) {
7738 connector->base.encoder = &connector->new_encoder->base;
7739 }
f6e5b160 7740
9a935856
DV		 7741 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7742 base.head) {
7743 encoder->base.crtc = &encoder->new_crtc->base;
7744 }
7745}
7746
050f7aeb
DV		 7747static void
7748connected_sink_compute_bpp(struct intel_connector * connector,
7749 struct intel_crtc_config *pipe_config)
7750{
7751 int bpp = pipe_config->pipe_bpp;
7752
7753 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7754 connector->base.base.id,
7755 drm_get_connector_name(&connector->base));
7756
7757 /* Don't use an invalid EDID bpc value */
7758 if (connector->base.display_info.bpc &&
7759 connector->base.display_info.bpc * 3 < bpp) {
7760 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7761 bpp, connector->base.display_info.bpc*3);
7762 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7763 }
7764
7765 /* Clamp bpp to 8 on screens without EDID 1.4 */
7766 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7767 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7768 bpp);
7769 pipe_config->pipe_bpp = 24;
7770 }
7771}
7772
4e53c2e0 7773static int
050f7aeb
DV		 7774compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7775 struct drm_framebuffer *fb,
7776 struct intel_crtc_config *pipe_config)
4e53c2e0 7777{
050f7aeb
DV		 7778 struct drm_device *dev = crtc->base.dev;
7779 struct intel_connector *connector;
4e53c2e0
DV		 7780 int bpp;
7781
d42264b1
DV		 7782 switch (fb->pixel_format) {
7783 case DRM_FORMAT_C8:
4e53c2e0
DV		 7784 bpp = 8*3; /* since we go through a colormap */
7785 break;
d42264b1
DV		 7786 case DRM_FORMAT_XRGB1555:
7787 case DRM_FORMAT_ARGB1555:
7788 /* checked in intel_framebuffer_init already */
7789 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7790 return -EINVAL;
7791 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7792 bpp = 6*3; /* min is 18bpp */
7793 break;
d42264b1
DV		 7794 case DRM_FORMAT_XBGR8888:
7795 case DRM_FORMAT_ABGR8888:
7796 /* checked in intel_framebuffer_init already */
7797 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7798 return -EINVAL;
7799 case DRM_FORMAT_XRGB8888:
7800 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7801 bpp = 8*3;
7802 break;
d42264b1
DV		 7803 case DRM_FORMAT_XRGB2101010:
7804 case DRM_FORMAT_ARGB2101010:
7805 case DRM_FORMAT_XBGR2101010:
7806 case DRM_FORMAT_ABGR2101010:
7807 /* checked in intel_framebuffer_init already */
7808 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7809 return -EINVAL;
4e53c2e0
DV		 7810 bpp = 10*3;
7811 break;
baba133a 7812 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7813 default:
7814 DRM_DEBUG_KMS("unsupported depth\n");
7815 return -EINVAL;
7816 }
7817
4e53c2e0
DV		 7818 pipe_config->pipe_bpp = bpp;
7819
7820 /* Clamp display bpp to EDID value */
7821 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 7822 base.head) {
1b829e05
DV		 7823 if (!connector->new_encoder ||
7824 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 7825 continue;
7826
050f7aeb 7827 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 7828 }
7829
7830 return bpp;
7831}
7832
c0b03411
DV		 7833static void intel_dump_pipe_config(struct intel_crtc *crtc,
7834 struct intel_crtc_config *pipe_config,
7835 const char *context)
7836{
7837 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7838 context, pipe_name(crtc->pipe));
7839
7840 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7841 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7842 pipe_config->pipe_bpp, pipe_config->dither);
7843 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7844 pipe_config->has_pch_encoder,
7845 pipe_config->fdi_lanes,
7846 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7847 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7848 pipe_config->fdi_m_n.tu);
7849 DRM_DEBUG_KMS("requested mode:\n");
7850 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7851 DRM_DEBUG_KMS("adjusted mode:\n");
7852 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7853 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7854 pipe_config->gmch_pfit.control,
7855 pipe_config->gmch_pfit.pgm_ratios,
7856 pipe_config->gmch_pfit.lvds_border_bits);
7857 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7858 pipe_config->pch_pfit.pos,
7859 pipe_config->pch_pfit.size);
42db64ef 7860 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 7861}
7862
accfc0c5
DV		 7863static bool check_encoder_cloning(struct drm_crtc *crtc)
7864{
7865 int num_encoders = 0;
7866 bool uncloneable_encoders = false;
7867 struct intel_encoder *encoder;
7868
7869 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
7870 base.head) {
7871 if (&encoder->new_crtc->base != crtc)
7872 continue;
7873
7874 num_encoders++;
7875 if (!encoder->cloneable)
7876 uncloneable_encoders = true;
7877 }
7878
7879 return !(num_encoders > 1 && uncloneable_encoders);
7880}
7881
b8cecdf5
DV		 7882static struct intel_crtc_config *
7883intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7884 struct drm_framebuffer *fb,
b8cecdf5 7885 struct drm_display_mode *mode)
ee7b9f93 7886{
7758a113 7887 struct drm_device *dev = crtc->dev;
7758a113
DV		 7888 struct drm_encoder_helper_funcs *encoder_funcs;
7889 struct intel_encoder *encoder;
b8cecdf5 7890 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7891 int plane_bpp, ret = -EINVAL;
7892 bool retry = true;
ee7b9f93 7893
accfc0c5
DV		 7894 if (!check_encoder_cloning(crtc)) {
7895 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
7896 return ERR_PTR(-EINVAL);
7897 }
7898
b8cecdf5
DV		 7899 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7900 if (!pipe_config)
7758a113
DV		 7901 return ERR_PTR(-ENOMEM);
7902
b8cecdf5
DV		 7903 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7904 drm_mode_copy(&pipe_config->requested_mode, mode);
e143a21c
DV		 7905 pipe_config->cpu_transcoder =
7906 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 7907 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 7908
050f7aeb
DV		 7909 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7910 * plane pixel format and any sink constraints into account. Returns the
7911 * source plane bpp so that dithering can be selected on mismatches
7912 * after encoders and crtc also have had their say. */
7913 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7914 fb, pipe_config);
4e53c2e0
DV		 7915 if (plane_bpp < 0)
7916 goto fail;
7917
e29c22c0 7918encoder_retry:
ef1b460d 7919 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 7920 pipe_config->port_clock = 0;
ef1b460d 7921 pipe_config->pixel_multiplier = 1;
ff9a6750 7922
7758a113
DV		 7923 /* Pass our mode to the connectors and the CRTC to give them a chance to
7924 * adjust it according to limitations or connector properties, and also
7925 * a chance to reject the mode entirely.
47f1c6c9 7926 */
7758a113
DV		 7927 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7928 base.head) {
47f1c6c9 7929
7758a113
DV		 7930 if (&encoder->new_crtc->base != crtc)
7931 continue;
7ae89233
DV		 7932
7933 if (encoder->compute_config) {
7934 if (!(encoder->compute_config(encoder, pipe_config))) {
7935 DRM_DEBUG_KMS("Encoder config failure\n");
7936 goto fail;
7937 }
7938
7939 continue;
7940 }
7941
7758a113 7942 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7943 if (!(encoder_funcs->mode_fixup(&encoder->base,
7944 &pipe_config->requested_mode,
7945 &pipe_config->adjusted_mode))) {
7758a113
DV		 7946 DRM_DEBUG_KMS("Encoder fixup failed\n");
7947 goto fail;
7948 }
ee7b9f93 7949 }
47f1c6c9 7950
ff9a6750
DV		 7951 /* Set default port clock if not overwritten by the encoder. Needs to be
7952 * done afterwards in case the encoder adjusts the mode. */
7953 if (!pipe_config->port_clock)
7954 pipe_config->port_clock = pipe_config->adjusted_mode.clock;
7955
a43f6e0f 7956 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 7957 if (ret < 0) {
7758a113
DV		 7958 DRM_DEBUG_KMS("CRTC fixup failed\n");
7959 goto fail;
ee7b9f93 7960 }
e29c22c0
DV		 7961
7962 if (ret == RETRY) {
7963 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7964 ret = -EINVAL;
7965 goto fail;
7966 }
7967
7968 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7969 retry = false;
7970 goto encoder_retry;
7971 }
7972
4e53c2e0
DV		 7973 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7974 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7975 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7976
b8cecdf5 7977 return pipe_config;
7758a113 7978fail:
b8cecdf5 7979 kfree(pipe_config);
e29c22c0 7980 return ERR_PTR(ret);
ee7b9f93 7981}
47f1c6c9 7982
e2e1ed41
DV		 7983/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7984 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7985static void
7986intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7987 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7988{
7989 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7990 struct drm_device *dev = crtc->dev;
7991 struct intel_encoder *encoder;
7992 struct intel_connector *connector;
7993 struct drm_crtc *tmp_crtc;
79e53945 7994
e2e1ed41 7995 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7996
e2e1ed41
DV		 7997 /* Check which crtcs have changed outputs connected to them, these need
7998 * to be part of the prepare_pipes mask. We don't (yet) support global
7999 * modeset across multiple crtcs, so modeset_pipes will only have one
8000 * bit set at most. */
8001 list_for_each_entry(connector, &dev->mode_config.connector_list,
8002 base.head) {
8003 if (connector->base.encoder == &connector->new_encoder->base)
8004 continue;
79e53945 8005
e2e1ed41
DV		 8006 if (connector->base.encoder) {
8007 tmp_crtc = connector->base.encoder->crtc;
8008
8009 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8010 }
8011
8012 if (connector->new_encoder)
8013 *prepare_pipes |=
8014 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8015 }
8016
e2e1ed41
DV		 8017 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8018 base.head) {
8019 if (encoder->base.crtc == &encoder->new_crtc->base)
8020 continue;
8021
8022 if (encoder->base.crtc) {
8023 tmp_crtc = encoder->base.crtc;
8024
8025 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8026 }
8027
8028 if (encoder->new_crtc)
8029 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8030 }
8031
e2e1ed41
DV		 8032 /* Check for any pipes that will be fully disabled ... */
8033 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8034 base.head) {
8035 bool used = false;
22fd0fab 8036
e2e1ed41
DV		 8037 /* Don't try to disable disabled crtcs. */
8038 if (!intel_crtc->base.enabled)
8039 continue;
7e7d76c3 8040
e2e1ed41
DV		 8041 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8042 base.head) {
8043 if (encoder->new_crtc == intel_crtc)
8044 used = true;
8045 }
8046
8047 if (!used)
8048 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8049 }
8050
e2e1ed41
DV		 8051
8052 /* set_mode is also used to update properties on life display pipes. */
8053 intel_crtc = to_intel_crtc(crtc);
8054 if (crtc->enabled)
8055 *prepare_pipes |= 1 << intel_crtc->pipe;
8056
b6c5164d
DV		 8057 /*
8058 * For simplicity do a full modeset on any pipe where the output routing
8059 * changed. We could be more clever, but that would require us to be
8060 * more careful with calling the relevant encoder->mode_set functions.
8061 */
e2e1ed41
DV		 8062 if (*prepare_pipes)
8063 *modeset_pipes = *prepare_pipes;
8064
8065 /* ... and mask these out. */
8066 *modeset_pipes &= ~(*disable_pipes);
8067 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8068
8069 /*
8070 * HACK: We don't (yet) fully support global modesets. intel_set_config
8071 * obies this rule, but the modeset restore mode of
8072 * intel_modeset_setup_hw_state does not.
8073 */
8074 *modeset_pipes &= 1 << intel_crtc->pipe;
8075 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8076
8077 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8078 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8079}
79e53945 8080
ea9d758d 8081static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8082{
ea9d758d 8083 struct drm_encoder *encoder;
f6e5b160 8084 struct drm_device *dev = crtc->dev;
f6e5b160 8085
ea9d758d
DV		 8086 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8087 if (encoder->crtc == crtc)
8088 return true;
8089
8090 return false;
8091}
8092
8093static void
8094intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8095{
8096 struct intel_encoder *intel_encoder;
8097 struct intel_crtc *intel_crtc;
8098 struct drm_connector *connector;
8099
8100 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8101 base.head) {
8102 if (!intel_encoder->base.crtc)
8103 continue;
8104
8105 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8106
8107 if (prepare_pipes & (1 << intel_crtc->pipe))
8108 intel_encoder->connectors_active = false;
8109 }
8110
8111 intel_modeset_commit_output_state(dev);
8112
8113 /* Update computed state. */
8114 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8115 base.head) {
8116 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8117 }
8118
8119 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8120 if (!connector->encoder || !connector->encoder->crtc)
8121 continue;
8122
8123 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8124
8125 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8126 struct drm_property *dpms_property =
8127 dev->mode_config.dpms_property;
8128
ea9d758d 8129 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8130 drm_object_property_set_value(&connector->base,
68d34720
DV		 8131 dpms_property,
8132 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8133
8134 intel_encoder = to_intel_encoder(connector->encoder);
8135 intel_encoder->connectors_active = true;
8136 }
8137 }
8138
8139}
8140
f1f644dc
JB		 8141static bool intel_fuzzy_clock_check(struct intel_crtc_config *cur,
8142 struct intel_crtc_config *new)
8143{
8144 int clock1, clock2, diff;
8145
8146 clock1 = cur->adjusted_mode.clock;
8147 clock2 = new->adjusted_mode.clock;
8148
8149 if (clock1 == clock2)
8150 return true;
8151
8152 if (!clock1 || !clock2)
8153 return false;
8154
8155 diff = abs(clock1 - clock2);
8156
8157 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8158 return true;
8159
8160 return false;
8161}
8162
25c5b266
DV		 8163#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8164 list_for_each_entry((intel_crtc), \
8165 &(dev)->mode_config.crtc_list, \
8166 base.head) \
0973f18f 8167 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8168
0e8ffe1b 8169static bool
2fa2fe9a
DV		 8170intel_pipe_config_compare(struct drm_device *dev,
8171 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8172 struct intel_crtc_config *pipe_config)
8173{
66e985c0
DV		 8174#define PIPE_CONF_CHECK_X(name) \
8175 if (current_config->name != pipe_config->name) { \
8176 DRM_ERROR("mismatch in " #name " " \
8177 "(expected 0x%08x, found 0x%08x)\n", \
8178 current_config->name, \
8179 pipe_config->name); \
8180 return false; \
8181 }
8182
08a24034
DV		 8183#define PIPE_CONF_CHECK_I(name) \
8184 if (current_config->name != pipe_config->name) { \
8185 DRM_ERROR("mismatch in " #name " " \
8186 "(expected %i, found %i)\n", \
8187 current_config->name, \
8188 pipe_config->name); \
8189 return false; \
88adfff1
DV		 8190 }
8191
1bd1bd80
DV		 8192#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8193 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8194 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8195 "(expected %i, found %i)\n", \
8196 current_config->name & (mask), \
8197 pipe_config->name & (mask)); \
8198 return false; \
8199 }
8200
bb760063
DV		 8201#define PIPE_CONF_QUIRK(quirk) \
8202 ((current_config->quirks | pipe_config->quirks) & (quirk))
8203
eccb140b
DV		 8204 PIPE_CONF_CHECK_I(cpu_transcoder);
8205
08a24034
DV		 8206 PIPE_CONF_CHECK_I(has_pch_encoder);
8207 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8208 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8209 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8210 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8211 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8212 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8213
1bd1bd80
DV		 8214 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8215 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8216 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8217 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8218 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8219 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8220
8221 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8222 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8223 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8224 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8225 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8226 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8227
c93f54cf 8228 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8229
1bd1bd80
DV		 8230 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8231 DRM_MODE_FLAG_INTERLACE);
8232
bb760063
DV		 8233 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8234 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8235 DRM_MODE_FLAG_PHSYNC);
8236 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8237 DRM_MODE_FLAG_NHSYNC);
8238 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8239 DRM_MODE_FLAG_PVSYNC);
8240 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8241 DRM_MODE_FLAG_NVSYNC);
8242 }
045ac3b5 8243
1bd1bd80
DV		 8244 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8245 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8246
2fa2fe9a
DV		 8247 PIPE_CONF_CHECK_I(gmch_pfit.control);
8248 /* pfit ratios are autocomputed by the hw on gen4+ */
8249 if (INTEL_INFO(dev)->gen < 4)
8250 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8251 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8252 PIPE_CONF_CHECK_I(pch_pfit.pos);
8253 PIPE_CONF_CHECK_I(pch_pfit.size);
8254
42db64ef
PZ		 8255 PIPE_CONF_CHECK_I(ips_enabled);
8256
c0d43d62 8257 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8258 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8259 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8260 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8261 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8262
66e985c0 8263#undef PIPE_CONF_CHECK_X
08a24034 8264#undef PIPE_CONF_CHECK_I
1bd1bd80 8265#undef PIPE_CONF_CHECK_FLAGS
bb760063 8266#undef PIPE_CONF_QUIRK
88adfff1 8267
f1f644dc
JB		 8268 if (!IS_HASWELL(dev)) {
8269 if (!intel_fuzzy_clock_check(current_config, pipe_config)) {
6f02488e 8270 DRM_ERROR("mismatch in clock (expected %d, found %d)\n",
f1f644dc
JB		 8271 current_config->adjusted_mode.clock,
8272 pipe_config->adjusted_mode.clock);
8273 return false;
8274 }
8275 }
8276
0e8ffe1b
DV		 8277 return true;
8278}
8279
91d1b4bd
DV		 8280static void
8281check_connector_state(struct drm_device *dev)
8af6cf88 8282{
8af6cf88
DV		 8283 struct intel_connector *connector;
8284
8285 list_for_each_entry(connector, &dev->mode_config.connector_list,
8286 base.head) {
8287 /* This also checks the encoder/connector hw state with the
8288 * ->get_hw_state callbacks. */
8289 intel_connector_check_state(connector);
8290
8291 WARN(&connector->new_encoder->base != connector->base.encoder,
8292 "connector's staged encoder doesn't match current encoder\n");
8293 }
91d1b4bd
DV		 8294}
8295
8296static void
8297check_encoder_state(struct drm_device *dev)
8298{
8299 struct intel_encoder *encoder;
8300 struct intel_connector *connector;
8af6cf88
DV		 8301
8302 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8303 base.head) {
8304 bool enabled = false;
8305 bool active = false;
8306 enum pipe pipe, tracked_pipe;
8307
8308 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8309 encoder->base.base.id,
8310 drm_get_encoder_name(&encoder->base));
8311
8312 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8313 "encoder's stage crtc doesn't match current crtc\n");
8314 WARN(encoder->connectors_active && !encoder->base.crtc,
8315 "encoder's active_connectors set, but no crtc\n");
8316
8317 list_for_each_entry(connector, &dev->mode_config.connector_list,
8318 base.head) {
8319 if (connector->base.encoder != &encoder->base)
8320 continue;
8321 enabled = true;
8322 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8323 active = true;
8324 }
8325 WARN(!!encoder->base.crtc != enabled,
8326 "encoder's enabled state mismatch "
8327 "(expected %i, found %i)\n",
8328 !!encoder->base.crtc, enabled);
8329 WARN(active && !encoder->base.crtc,
8330 "active encoder with no crtc\n");
8331
8332 WARN(encoder->connectors_active != active,
8333 "encoder's computed active state doesn't match tracked active state "
8334 "(expected %i, found %i)\n", active, encoder->connectors_active);
8335
8336 active = encoder->get_hw_state(encoder, &pipe);
8337 WARN(active != encoder->connectors_active,
8338 "encoder's hw state doesn't match sw tracking "
8339 "(expected %i, found %i)\n",
8340 encoder->connectors_active, active);
8341
8342 if (!encoder->base.crtc)
8343 continue;
8344
8345 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8346 WARN(active && pipe != tracked_pipe,
8347 "active encoder's pipe doesn't match"
8348 "(expected %i, found %i)\n",
8349 tracked_pipe, pipe);
8350
8351 }
91d1b4bd
DV		 8352}
8353
8354static void
8355check_crtc_state(struct drm_device *dev)
8356{
8357 drm_i915_private_t *dev_priv = dev->dev_private;
8358 struct intel_crtc *crtc;
8359 struct intel_encoder *encoder;
8360 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8361
8362 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8363 base.head) {
8364 bool enabled = false;
8365 bool active = false;
8366
045ac3b5
JB		 8367 memset(&pipe_config, 0, sizeof(pipe_config));
8368
8af6cf88
DV		 8369 DRM_DEBUG_KMS("[CRTC:%d]\n",
8370 crtc->base.base.id);
8371
8372 WARN(crtc->active && !crtc->base.enabled,
8373 "active crtc, but not enabled in sw tracking\n");
8374
8375 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8376 base.head) {
8377 if (encoder->base.crtc != &crtc->base)
8378 continue;
8379 enabled = true;
8380 if (encoder->connectors_active)
8381 active = true;
8382 }
6c49f241 8383
8af6cf88
DV		 8384 WARN(active != crtc->active,
8385 "crtc's computed active state doesn't match tracked active state "
8386 "(expected %i, found %i)\n", active, crtc->active);
8387 WARN(enabled != crtc->base.enabled,
8388 "crtc's computed enabled state doesn't match tracked enabled state "
8389 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8390
0e8ffe1b
DV		 8391 active = dev_priv->display.get_pipe_config(crtc,
8392 &pipe_config);
d62cf62a
DV		 8393
8394 /* hw state is inconsistent with the pipe A quirk */
8395 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
8396 active = crtc->active;
8397
6c49f241
DV		 8398 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8399 base.head) {
8400 if (encoder->base.crtc != &crtc->base)
8401 continue;
510d5f2f 8402 if (encoder->get_config)
6c49f241
DV		 8403 encoder->get_config(encoder, &pipe_config);
8404 }
8405
510d5f2f
JB		 8406 if (dev_priv->display.get_clock)
8407 dev_priv->display.get_clock(crtc, &pipe_config);
8408
0e8ffe1b
DV		 8409 WARN(crtc->active != active,
8410 "crtc active state doesn't match with hw state "
8411 "(expected %i, found %i)\n", crtc->active, active);
8412
c0b03411
DV		 8413 if (active &&
8414 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8415 WARN(1, "pipe state doesn't match!\n");
8416 intel_dump_pipe_config(crtc, &pipe_config,
8417 "[hw state]");
8418 intel_dump_pipe_config(crtc, &crtc->config,
8419 "[sw state]");
8420 }
8af6cf88
DV		 8421 }
8422}
8423
91d1b4bd
DV		 8424static void
8425check_shared_dpll_state(struct drm_device *dev)
8426{
8427 drm_i915_private_t *dev_priv = dev->dev_private;
8428 struct intel_crtc *crtc;
8429 struct intel_dpll_hw_state dpll_hw_state;
8430 int i;
5358901f
DV		 8431
8432 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
8433 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
8434 int enabled_crtcs = 0, active_crtcs = 0;
8435 bool active;
8436
8437 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
8438
8439 DRM_DEBUG_KMS("%s\n", pll->name);
8440
8441 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
8442
8443 WARN(pll->active > pll->refcount,
8444 "more active pll users than references: %i vs %i\n",
8445 pll->active, pll->refcount);
8446 WARN(pll->active && !pll->on,
8447 "pll in active use but not on in sw tracking\n");
8448 WARN(pll->on != active,
8449 "pll on state mismatch (expected %i, found %i)\n",
8450 pll->on, active);
8451
8452 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8453 base.head) {
8454 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
8455 enabled_crtcs++;
8456 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
8457 active_crtcs++;
8458 }
8459 WARN(pll->active != active_crtcs,
8460 "pll active crtcs mismatch (expected %i, found %i)\n",
8461 pll->active, active_crtcs);
8462 WARN(pll->refcount != enabled_crtcs,
8463 "pll enabled crtcs mismatch (expected %i, found %i)\n",
8464 pll->refcount, enabled_crtcs);
66e985c0
DV		 8465
8466 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
8467 sizeof(dpll_hw_state)),
8468 "pll hw state mismatch\n");
5358901f 8469 }
8af6cf88
DV		 8470}
8471
91d1b4bd
DV		 8472void
8473intel_modeset_check_state(struct drm_device *dev)
8474{
8475 check_connector_state(dev);
8476 check_encoder_state(dev);
8477 check_crtc_state(dev);
8478 check_shared_dpll_state(dev);
8479}
8480
f30da187
DV		 8481static int __intel_set_mode(struct drm_crtc *crtc,
8482 struct drm_display_mode *mode,
8483 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8484{
8485 struct drm_device *dev = crtc->dev;
dbf2b54e 8486 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8487 struct drm_display_mode *saved_mode, *saved_hwmode;
8488 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8489 struct intel_crtc *intel_crtc;
8490 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8491 int ret = 0;
a6778b3c 8492
3ac18232 8493 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8494 if (!saved_mode)
8495 return -ENOMEM;
3ac18232 8496 saved_hwmode = saved_mode + 1;
a6778b3c 8497
e2e1ed41 8498 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8499 &prepare_pipes, &disable_pipes);
8500
3ac18232
TG		 8501 *saved_hwmode = crtc->hwmode;
8502 *saved_mode = crtc->mode;
a6778b3c 8503
25c5b266
DV		 8504 /* Hack: Because we don't (yet) support global modeset on multiple
8505 * crtcs, we don't keep track of the new mode for more than one crtc.
8506 * Hence simply check whether any bit is set in modeset_pipes in all the
8507 * pieces of code that are not yet converted to deal with mutliple crtcs
8508 * changing their mode at the same time. */
25c5b266 8509 if (modeset_pipes) {
4e53c2e0 8510 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8511 if (IS_ERR(pipe_config)) {
8512 ret = PTR_ERR(pipe_config);
8513 pipe_config = NULL;
8514
3ac18232 8515 goto out;
25c5b266 8516 }
c0b03411
DV		 8517 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8518 "[modeset]");
25c5b266 8519 }
a6778b3c 8520
460da916
DV		 8521 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8522 intel_crtc_disable(&intel_crtc->base);
8523
ea9d758d
DV		 8524 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8525 if (intel_crtc->base.enabled)
8526 dev_priv->display.crtc_disable(&intel_crtc->base);
8527 }
a6778b3c 8528
6c4c86f5
DV		 8529 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8530 * to set it here already despite that we pass it down the callchain.
f6e5b160 8531 */
b8cecdf5 8532 if (modeset_pipes) {
25c5b266 8533 crtc->mode = *mode;
b8cecdf5
DV		 8534 /* mode_set/enable/disable functions rely on a correct pipe
8535 * config. */
8536 to_intel_crtc(crtc)->config = *pipe_config;
8537 }
7758a113 8538
ea9d758d
DV		 8539 /* Only after disabling all output pipelines that will be changed can we
8540 * update the the output configuration. */
8541 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8542
47fab737
DV		 8543 if (dev_priv->display.modeset_global_resources)
8544 dev_priv->display.modeset_global_resources(dev);
8545
a6778b3c
DV		 8546 /* Set up the DPLL and any encoders state that needs to adjust or depend
8547 * on the DPLL.
f6e5b160 8548 */
25c5b266 8549 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8550 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8551 x, y, fb);
8552 if (ret)
8553 goto done;
a6778b3c
DV		 8554 }
8555
8556 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8557 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8558 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8559
25c5b266
DV		 8560 if (modeset_pipes) {
8561 /* Store real post-adjustment hardware mode. */
b8cecdf5 8562 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8563
25c5b266
DV		 8564 /* Calculate and store various constants which
8565 * are later needed by vblank and swap-completion
8566 * timestamping. They are derived from true hwmode.
8567 */
8568 drm_calc_timestamping_constants(crtc);
8569 }
a6778b3c
DV		 8570
8571 /* FIXME: add subpixel order */
8572done:
c0c36b94 8573 if (ret && crtc->enabled) {
3ac18232
TG		 8574 crtc->hwmode = *saved_hwmode;
8575 crtc->mode = *saved_mode;
a6778b3c
DV		 8576 }
8577
3ac18232 8578out:
b8cecdf5 8579 kfree(pipe_config);
3ac18232 8580 kfree(saved_mode);
a6778b3c 8581 return ret;
f6e5b160
CW		 8582}
8583
f30da187
DV		 8584int intel_set_mode(struct drm_crtc *crtc,
8585 struct drm_display_mode *mode,
8586 int x, int y, struct drm_framebuffer *fb)
8587{
8588 int ret;
8589
8590 ret = __intel_set_mode(crtc, mode, x, y, fb);
8591
8592 if (ret == 0)
8593 intel_modeset_check_state(crtc->dev);
8594
8595 return ret;
8596}
8597
c0c36b94
CW		 8598void intel_crtc_restore_mode(struct drm_crtc *crtc)
8599{
8600 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8601}
8602
25c5b266
DV		 8603#undef for_each_intel_crtc_masked
8604
d9e55608
DV		 8605static void intel_set_config_free(struct intel_set_config *config)
8606{
8607 if (!config)
8608 return;
8609
1aa4b628
DV		 8610 kfree(config->save_connector_encoders);
8611 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8612 kfree(config);
8613}
8614
85f9eb71
DV		 8615static int intel_set_config_save_state(struct drm_device *dev,
8616 struct intel_set_config *config)
8617{
85f9eb71
DV		 8618 struct drm_encoder *encoder;
8619 struct drm_connector *connector;
8620 int count;
8621
1aa4b628
DV		 8622 config->save_encoder_crtcs =
8623 kcalloc(dev->mode_config.num_encoder,
8624 sizeof(struct drm_crtc *), GFP_KERNEL);
8625 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8626 return -ENOMEM;
8627
1aa4b628
DV		 8628 config->save_connector_encoders =
8629 kcalloc(dev->mode_config.num_connector,
8630 sizeof(struct drm_encoder *), GFP_KERNEL);
8631 if (!config->save_connector_encoders)
85f9eb71
DV		 8632 return -ENOMEM;
8633
8634 /* Copy data. Note that driver private data is not affected.
8635 * Should anything bad happen only the expected state is
8636 * restored, not the drivers personal bookkeeping.
8637 */
85f9eb71
DV		 8638 count = 0;
8639 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8640 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8641 }
8642
8643 count = 0;
8644 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8645 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8646 }
8647
8648 return 0;
8649}
8650
8651static void intel_set_config_restore_state(struct drm_device *dev,
8652 struct intel_set_config *config)
8653{
9a935856
DV		 8654 struct intel_encoder *encoder;
8655 struct intel_connector *connector;
85f9eb71
DV		 8656 int count;
8657
85f9eb71 8658 count = 0;
9a935856
DV		 8659 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8660 encoder->new_crtc =
8661 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8662 }
8663
8664 count = 0;
9a935856
DV		 8665 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8666 connector->new_encoder =
8667 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8668 }
8669}
8670
e3de42b6
ID		 8671static bool
8672is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
8673 int num_connectors)
8674{
8675 int i;
8676
8677 for (i = 0; i < num_connectors; i++)
8678 if (connectors[i].encoder &&
8679 connectors[i].encoder->crtc == crtc &&
8680 connectors[i].dpms != DRM_MODE_DPMS_ON)
8681 return true;
8682
8683 return false;
8684}
8685
5e2b584e
DV		 8686static void
8687intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8688 struct intel_set_config *config)
8689{
8690
8691 /* We should be able to check here if the fb has the same properties
8692 * and then just flip_or_move it */
e3de42b6
ID		 8693 if (set->connectors != NULL &&
8694 is_crtc_connector_off(set->crtc, *set->connectors,
8695 set->num_connectors)) {
8696 config->mode_changed = true;
8697 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 8698 /* If we have no fb then treat it as a full mode set */
8699 if (set->crtc->fb == NULL) {
319d9827
JB		 8700 struct intel_crtc *intel_crtc =
8701 to_intel_crtc(set->crtc);
8702
8703 if (intel_crtc->active && i915_fastboot) {
8704 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
8705 config->fb_changed = true;
8706 } else {
8707 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
8708 config->mode_changed = true;
8709 }
5e2b584e
DV		 8710 } else if (set->fb == NULL) {
8711 config->mode_changed = true;
72f4901e
DV		 8712 } else if (set->fb->pixel_format !=
8713 set->crtc->fb->pixel_format) {
5e2b584e 8714 config->mode_changed = true;
e3de42b6 8715 } else {
5e2b584e 8716 config->fb_changed = true;
e3de42b6 8717 }
5e2b584e
DV		 8718 }
8719
835c5873 8720 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8721 config->fb_changed = true;
8722
8723 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8724 DRM_DEBUG_KMS("modes are different, full mode set\n");
8725 drm_mode_debug_printmodeline(&set->crtc->mode);
8726 drm_mode_debug_printmodeline(set->mode);
8727 config->mode_changed = true;
8728 }
8729}
8730
2e431051 8731static int
9a935856
DV		 8732intel_modeset_stage_output_state(struct drm_device *dev,
8733 struct drm_mode_set *set,
8734 struct intel_set_config *config)
50f56119 8735{
85f9eb71 8736 struct drm_crtc *new_crtc;
9a935856
DV		 8737 struct intel_connector *connector;
8738 struct intel_encoder *encoder;
2e431051 8739 int count, ro;
50f56119 8740
9abdda74 8741 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8742 * of connectors. For paranoia, double-check this. */
8743 WARN_ON(!set->fb && (set->num_connectors != 0));
8744 WARN_ON(set->fb && (set->num_connectors == 0));
8745
50f56119 8746 count = 0;
9a935856
DV		 8747 list_for_each_entry(connector, &dev->mode_config.connector_list,
8748 base.head) {
8749 /* Otherwise traverse passed in connector list and get encoders
8750 * for them. */
50f56119 8751 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8752 if (set->connectors[ro] == &connector->base) {
8753 connector->new_encoder = connector->encoder;
50f56119
DV		 8754 break;
8755 }
8756 }
8757
9a935856
DV		 8758 /* If we disable the crtc, disable all its connectors. Also, if
8759 * the connector is on the changing crtc but not on the new
8760 * connector list, disable it. */
8761 if ((!set->fb || ro == set->num_connectors) &&
8762 connector->base.encoder &&
8763 connector->base.encoder->crtc == set->crtc) {
8764 connector->new_encoder = NULL;
8765
8766 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8767 connector->base.base.id,
8768 drm_get_connector_name(&connector->base));
8769 }
8770
8771
8772 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8773 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8774 config->mode_changed = true;
50f56119
DV		 8775 }
8776 }
9a935856 8777 /* connector->new_encoder is now updated for all connectors. */
50f56119 8778
9a935856 8779 /* Update crtc of enabled connectors. */
50f56119 8780 count = 0;
9a935856
DV		 8781 list_for_each_entry(connector, &dev->mode_config.connector_list,
8782 base.head) {
8783 if (!connector->new_encoder)
50f56119
DV		 8784 continue;
8785
9a935856 8786 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8787
8788 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8789 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8790 new_crtc = set->crtc;
8791 }
8792
8793 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8794 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8795 new_crtc)) {
5e2b584e 8796 return -EINVAL;
50f56119 8797 }
9a935856
DV		 8798 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8799
8800 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8801 connector->base.base.id,
8802 drm_get_connector_name(&connector->base),
8803 new_crtc->base.id);
8804 }
8805
8806 /* Check for any encoders that needs to be disabled. */
8807 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8808 base.head) {
8809 list_for_each_entry(connector,
8810 &dev->mode_config.connector_list,
8811 base.head) {
8812 if (connector->new_encoder == encoder) {
8813 WARN_ON(!connector->new_encoder->new_crtc);
8814
8815 goto next_encoder;
8816 }
8817 }
8818 encoder->new_crtc = NULL;
8819next_encoder:
8820 /* Only now check for crtc changes so we don't miss encoders
8821 * that will be disabled. */
8822 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8823 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8824 config->mode_changed = true;
50f56119
DV		 8825 }
8826 }
9a935856 8827 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8828
2e431051
DV		 8829 return 0;
8830}
8831
8832static int intel_crtc_set_config(struct drm_mode_set *set)
8833{
8834 struct drm_device *dev;
2e431051
DV		 8835 struct drm_mode_set save_set;
8836 struct intel_set_config *config;
8837 int ret;
2e431051 8838
8d3e375e
DV		 8839 BUG_ON(!set);
8840 BUG_ON(!set->crtc);
8841 BUG_ON(!set->crtc->helper_private);
2e431051 8842
7e53f3a4
DV		 8843 /* Enforce sane interface api - has been abused by the fb helper. */
8844 BUG_ON(!set->mode && set->fb);
8845 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8846
2e431051
DV		 8847 if (set->fb) {
8848 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8849 set->crtc->base.id, set->fb->base.id,
8850 (int)set->num_connectors, set->x, set->y);
8851 } else {
8852 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8853 }
8854
8855 dev = set->crtc->dev;
8856
8857 ret = -ENOMEM;
8858 config = kzalloc(sizeof(*config), GFP_KERNEL);
8859 if (!config)
8860 goto out_config;
8861
8862 ret = intel_set_config_save_state(dev, config);
8863 if (ret)
8864 goto out_config;
8865
8866 save_set.crtc = set->crtc;
8867 save_set.mode = &set->crtc->mode;
8868 save_set.x = set->crtc->x;
8869 save_set.y = set->crtc->y;
8870 save_set.fb = set->crtc->fb;
8871
8872 /* Compute whether we need a full modeset, only an fb base update or no
8873 * change at all. In the future we might also check whether only the
8874 * mode changed, e.g. for LVDS where we only change the panel fitter in
8875 * such cases. */
8876 intel_set_config_compute_mode_changes(set, config);
8877
9a935856 8878 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8879 if (ret)
8880 goto fail;
8881
5e2b584e 8882 if (config->mode_changed) {
c0c36b94
CW		 8883 ret = intel_set_mode(set->crtc, set->mode,
8884 set->x, set->y, set->fb);
5e2b584e 8885 } else if (config->fb_changed) {
4878cae2
VS		 8886 intel_crtc_wait_for_pending_flips(set->crtc);
8887
4f660f49 8888 ret = intel_pipe_set_base(set->crtc,
94352cf9 8889 set->x, set->y, set->fb);
50f56119
DV		 8890 }
8891
2d05eae1 8892 if (ret) {
bf67dfeb
DV		 8893 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
8894 set->crtc->base.id, ret);
50f56119 8895fail:
2d05eae1 8896 intel_set_config_restore_state(dev, config);
50f56119 8897
2d05eae1
CW		 8898 /* Try to restore the config */
8899 if (config->mode_changed &&
8900 intel_set_mode(save_set.crtc, save_set.mode,
8901 save_set.x, save_set.y, save_set.fb))
8902 DRM_ERROR("failed to restore config after modeset failure\n");
8903 }
50f56119 8904
d9e55608
DV		 8905out_config:
8906 intel_set_config_free(config);
50f56119
DV		 8907 return ret;
8908}
f6e5b160
CW		 8909
8910static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8911 .cursor_set = intel_crtc_cursor_set,
8912 .cursor_move = intel_crtc_cursor_move,
8913 .gamma_set = intel_crtc_gamma_set,
50f56119 8914 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8915 .destroy = intel_crtc_destroy,
8916 .page_flip = intel_crtc_page_flip,
8917};
8918
79f689aa
PZ		 8919static void intel_cpu_pll_init(struct drm_device *dev)
8920{
affa9354 8921 if (HAS_DDI(dev))
79f689aa
PZ		 8922 intel_ddi_pll_init(dev);
8923}
8924
5358901f
DV		 8925static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
8926 struct intel_shared_dpll *pll,
8927 struct intel_dpll_hw_state *hw_state)
ee7b9f93 8928{
5358901f 8929 uint32_t val;
ee7b9f93 8930
5358901f 8931 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 8932 hw_state->dpll = val;
8933 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
8934 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 8935
8936 return val & DPLL_VCO_ENABLE;
8937}
8938
15bdd4cf
DV		 8939static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
8940 struct intel_shared_dpll *pll)
8941{
8942 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
8943 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
8944}
8945
e7b903d2
DV		 8946static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
8947 struct intel_shared_dpll *pll)
8948{
e7b903d2
DV		 8949 /* PCH refclock must be enabled first */
8950 assert_pch_refclk_enabled(dev_priv);
8951
15bdd4cf
DV		 8952 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8953
8954 /* Wait for the clocks to stabilize. */
8955 POSTING_READ(PCH_DPLL(pll->id));
8956 udelay(150);
8957
8958 /* The pixel multiplier can only be updated once the
8959 * DPLL is enabled and the clocks are stable.
8960 *
8961 * So write it again.
8962 */
8963 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
8964 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 8965 udelay(200);
8966}
8967
8968static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
8969 struct intel_shared_dpll *pll)
8970{
8971 struct drm_device *dev = dev_priv->dev;
8972 struct intel_crtc *crtc;
e7b903d2
DV		 8973
8974 /* Make sure no transcoder isn't still depending on us. */
8975 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
8976 if (intel_crtc_to_shared_dpll(crtc) == pll)
8977 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 8978 }
8979
15bdd4cf
DV		 8980 I915_WRITE(PCH_DPLL(pll->id), 0);
8981 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 8982 udelay(200);
8983}
8984
46edb027
DV		 8985static char *ibx_pch_dpll_names[] = {
8986 "PCH DPLL A",
8987 "PCH DPLL B",
8988};
8989
7c74ade1 8990static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 8991{
e7b903d2 8992 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 8993 int i;
8994
7c74ade1 8995 dev_priv->num_shared_dpll = 2;
ee7b9f93 8996
e72f9fbf 8997 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 8998 dev_priv->shared_dplls[i].id = i;
8999 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9000 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9001 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9002 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9003 dev_priv->shared_dplls[i].get_hw_state =
9004 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9005 }
9006}
9007
7c74ade1
DV		 9008static void intel_shared_dpll_init(struct drm_device *dev)
9009{
e7b903d2 9010 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9011
9012 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9013 ibx_pch_dpll_init(dev);
9014 else
9015 dev_priv->num_shared_dpll = 0;
9016
9017 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9018 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9019 dev_priv->num_shared_dpll);
9020}
9021
b358d0a6 9022static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9023{
22fd0fab 9024 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9025 struct intel_crtc *intel_crtc;
9026 int i;
9027
9028 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
9029 if (intel_crtc == NULL)
9030 return;
9031
9032 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9033
9034 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9035 for (i = 0; i < 256; i++) {
9036 intel_crtc->lut_r[i] = i;
9037 intel_crtc->lut_g[i] = i;
9038 intel_crtc->lut_b[i] = i;
9039 }
9040
80824003
JB		 9041 /* Swap pipes & planes for FBC on pre-965 */
9042 intel_crtc->pipe = pipe;
9043 intel_crtc->plane = pipe;
e2e767ab 9044 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9045 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9046 intel_crtc->plane = !pipe;
80824003
JB		 9047 }
9048
22fd0fab
JB		 9049 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9050 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9051 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9052 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9053
79e53945 9054 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9055}
9056
08d7b3d1 9057int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9058 struct drm_file *file)
08d7b3d1 9059{
08d7b3d1 9060 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9061 struct drm_mode_object *drmmode_obj;
9062 struct intel_crtc *crtc;
08d7b3d1 9063
1cff8f6b
DV		 9064 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9065 return -ENODEV;
08d7b3d1 9066
c05422d5
DV		 9067 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9068 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9069
c05422d5 9070 if (!drmmode_obj) {
08d7b3d1
CW		 9071 DRM_ERROR("no such CRTC id\n");
9072 return -EINVAL;
9073 }
9074
c05422d5
DV		 9075 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9076 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9077
c05422d5 9078 return 0;
08d7b3d1
CW		 9079}
9080
66a9278e 9081static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9082{
66a9278e
DV		 9083 struct drm_device *dev = encoder->base.dev;
9084 struct intel_encoder *source_encoder;
79e53945 9085 int index_mask = 0;
79e53945
JB		 9086 int entry = 0;
9087
66a9278e
DV		 9088 list_for_each_entry(source_encoder,
9089 &dev->mode_config.encoder_list, base.head) {
9090
9091 if (encoder == source_encoder)
79e53945 9092 index_mask |= (1 << entry);
66a9278e
DV		 9093
9094 /* Intel hw has only one MUX where enocoders could be cloned. */
9095 if (encoder->cloneable && source_encoder->cloneable)
9096 index_mask |= (1 << entry);
9097
79e53945
JB		 9098 entry++;
9099 }
4ef69c7a 9100
79e53945
JB		 9101 return index_mask;
9102}
9103
4d302442
CW		 9104static bool has_edp_a(struct drm_device *dev)
9105{
9106 struct drm_i915_private *dev_priv = dev->dev_private;
9107
9108 if (!IS_MOBILE(dev))
9109 return false;
9110
9111 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9112 return false;
9113
9114 if (IS_GEN5(dev) &&
9115 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9116 return false;
9117
9118 return true;
9119}
9120
79e53945
JB		 9121static void intel_setup_outputs(struct drm_device *dev)
9122{
725e30ad 9123 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9124 struct intel_encoder *encoder;
cb0953d7 9125 bool dpd_is_edp = false;
79e53945 9126
c9093354 9127 intel_lvds_init(dev);
79e53945 9128
c40c0f5b 9129 if (!IS_ULT(dev))
79935fca 9130 intel_crt_init(dev);
cb0953d7 9131
affa9354 9132 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9133 int found;
9134
9135 /* Haswell uses DDI functions to detect digital outputs */
9136 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9137 /* DDI A only supports eDP */
9138 if (found)
9139 intel_ddi_init(dev, PORT_A);
9140
9141 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9142 * register */
9143 found = I915_READ(SFUSE_STRAP);
9144
9145 if (found & SFUSE_STRAP_DDIB_DETECTED)
9146 intel_ddi_init(dev, PORT_B);
9147 if (found & SFUSE_STRAP_DDIC_DETECTED)
9148 intel_ddi_init(dev, PORT_C);
9149 if (found & SFUSE_STRAP_DDID_DETECTED)
9150 intel_ddi_init(dev, PORT_D);
9151 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9152 int found;
270b3042
DV		 9153 dpd_is_edp = intel_dpd_is_edp(dev);
9154
9155 if (has_edp_a(dev))
9156 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9157
dc0fa718 9158 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9159 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9160 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9161 if (!found)
e2debe91 9162 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9163 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9164 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9165 }
9166
dc0fa718 9167 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9168 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9169
dc0fa718 9170 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9171 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9172
5eb08b69 9173 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9174 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9175
270b3042 9176 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9177 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9178 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9179 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 9180 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9181 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 9182
dc0fa718 9183 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9184 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9185 PORT_B);
67cfc203
VS		 9186 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9187 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9188 }
103a196f 9189 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9190 bool found = false;
7d57382e 9191
e2debe91 9192 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9193 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9194 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9195 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9196 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9197 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9198 }
27185ae1 9199
e7281eab 9200 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9201 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9202 }
13520b05
KH		 9203
9204 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9205
e2debe91 9206 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9207 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9208 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9209 }
27185ae1 9210
e2debe91 9211 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9212
b01f2c3a
JB		 9213 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9214 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9215 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9216 }
e7281eab 9217 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9218 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9219 }
27185ae1 9220
b01f2c3a 9221 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9222 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9223 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9224 } else if (IS_GEN2(dev))
79e53945
JB		 9225 intel_dvo_init(dev);
9226
103a196f 9227 if (SUPPORTS_TV(dev))
79e53945
JB		 9228 intel_tv_init(dev);
9229
4ef69c7a
CW		 9230 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9231 encoder->base.possible_crtcs = encoder->crtc_mask;
9232 encoder->base.possible_clones =
66a9278e 9233 intel_encoder_clones(encoder);
79e53945 9234 }
47356eb6 9235
dde86e2d 9236 intel_init_pch_refclk(dev);
270b3042
DV		 9237
9238 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9239}
9240
9241static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9242{
9243 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 9244
9245 drm_framebuffer_cleanup(fb);
05394f39 9246 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 9247
9248 kfree(intel_fb);
9249}
9250
9251static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9252 struct drm_file *file,
79e53945
JB		 9253 unsigned int *handle)
9254{
9255 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9256 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9257
05394f39 9258 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9259}
9260
9261static const struct drm_framebuffer_funcs intel_fb_funcs = {
9262 .destroy = intel_user_framebuffer_destroy,
9263 .create_handle = intel_user_framebuffer_create_handle,
9264};
9265
38651674
DA		 9266int intel_framebuffer_init(struct drm_device *dev,
9267 struct intel_framebuffer *intel_fb,
308e5bcb 9268 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9269 struct drm_i915_gem_object *obj)
79e53945 9270{
a35cdaa0 9271 int pitch_limit;
79e53945
JB		 9272 int ret;
9273
c16ed4be
CW		 9274 if (obj->tiling_mode == I915_TILING_Y) {
9275 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9276 return -EINVAL;
c16ed4be 9277 }
57cd6508 9278
c16ed4be
CW		 9279 if (mode_cmd->pitches[0] & 63) {
9280 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9281 mode_cmd->pitches[0]);
57cd6508 9282 return -EINVAL;
c16ed4be 9283 }
57cd6508 9284
a35cdaa0
CW		 9285 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9286 pitch_limit = 32*1024;
9287 } else if (INTEL_INFO(dev)->gen >= 4) {
9288 if (obj->tiling_mode)
9289 pitch_limit = 16*1024;
9290 else
9291 pitch_limit = 32*1024;
9292 } else if (INTEL_INFO(dev)->gen >= 3) {
9293 if (obj->tiling_mode)
9294 pitch_limit = 8*1024;
9295 else
9296 pitch_limit = 16*1024;
9297 } else
9298 /* XXX DSPC is limited to 4k tiled */
9299 pitch_limit = 8*1024;
9300
9301 if (mode_cmd->pitches[0] > pitch_limit) {
9302 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
9303 obj->tiling_mode ? "tiled" : "linear",
9304 mode_cmd->pitches[0], pitch_limit);
5d7bd705 9305 return -EINVAL;
c16ed4be 9306 }
5d7bd705
VS		 9307
9308 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 9309 mode_cmd->pitches[0] != obj->stride) {
9310 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
9311 mode_cmd->pitches[0], obj->stride);
5d7bd705 9312 return -EINVAL;
c16ed4be 9313 }
5d7bd705 9314
57779d06 9315 /* Reject formats not supported by any plane early. */
308e5bcb 9316 switch (mode_cmd->pixel_format) {
57779d06 9317 case DRM_FORMAT_C8:
04b3924d
VS		 9318 case DRM_FORMAT_RGB565:
9319 case DRM_FORMAT_XRGB8888:
9320 case DRM_FORMAT_ARGB8888:
57779d06
VS		 9321 break;
9322 case DRM_FORMAT_XRGB1555:
9323 case DRM_FORMAT_ARGB1555:
c16ed4be 9324 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 9325 DRM_DEBUG("unsupported pixel format: %s\n",
9326 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9327 return -EINVAL;
c16ed4be 9328 }
57779d06
VS		 9329 break;
9330 case DRM_FORMAT_XBGR8888:
9331 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 9332 case DRM_FORMAT_XRGB2101010:
9333 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 9334 case DRM_FORMAT_XBGR2101010:
9335 case DRM_FORMAT_ABGR2101010:
c16ed4be 9336 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 9337 DRM_DEBUG("unsupported pixel format: %s\n",
9338 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9339 return -EINVAL;
c16ed4be 9340 }
b5626747 9341 break;
04b3924d
VS		 9342 case DRM_FORMAT_YUYV:
9343 case DRM_FORMAT_UYVY:
9344 case DRM_FORMAT_YVYU:
9345 case DRM_FORMAT_VYUY:
c16ed4be 9346 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 9347 DRM_DEBUG("unsupported pixel format: %s\n",
9348 drm_get_format_name(mode_cmd->pixel_format));
57779d06 9349 return -EINVAL;
c16ed4be 9350 }
57cd6508
CW		 9351 break;
9352 default:
4ee62c76
VS		 9353 DRM_DEBUG("unsupported pixel format: %s\n",
9354 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 9355 return -EINVAL;
9356 }
9357
90f9a336
VS		 9358 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
9359 if (mode_cmd->offsets[0] != 0)
9360 return -EINVAL;
9361
c7d73f6a
DV		 9362 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
9363 intel_fb->obj = obj;
9364
79e53945
JB		 9365 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
9366 if (ret) {
9367 DRM_ERROR("framebuffer init failed %d\n", ret);
9368 return ret;
9369 }
9370
79e53945
JB		 9371 return 0;
9372}
9373
79e53945
JB		 9374static struct drm_framebuffer *
9375intel_user_framebuffer_create(struct drm_device *dev,
9376 struct drm_file *filp,
308e5bcb 9377 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 9378{
05394f39 9379 struct drm_i915_gem_object *obj;
79e53945 9380
308e5bcb
JB		 9381 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9382 mode_cmd->handles[0]));
c8725226 9383 if (&obj->base == NULL)
cce13ff7 9384 return ERR_PTR(-ENOENT);
79e53945 9385
d2dff872 9386 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9387}
9388
79e53945 9389static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9390 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9391 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9392};
9393
e70236a8
JB		 9394/* Set up chip specific display functions */
9395static void intel_init_display(struct drm_device *dev)
9396{
9397 struct drm_i915_private *dev_priv = dev->dev_private;
9398
ee9300bb
DV		 9399 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9400 dev_priv->display.find_dpll = g4x_find_best_dpll;
9401 else if (IS_VALLEYVIEW(dev))
9402 dev_priv->display.find_dpll = vlv_find_best_dpll;
9403 else if (IS_PINEVIEW(dev))
9404 dev_priv->display.find_dpll = pnv_find_best_dpll;
9405 else
9406 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9407
affa9354 9408 if (HAS_DDI(dev)) {
0e8ffe1b 9409 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9410 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9411 dev_priv->display.crtc_enable = haswell_crtc_enable;
9412 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9413 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9414 dev_priv->display.update_plane = ironlake_update_plane;
9415 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9416 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f1f644dc 9417 dev_priv->display.get_clock = ironlake_crtc_clock_get;
f564048e 9418 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9419 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9420 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9421 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9422 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9423 } else if (IS_VALLEYVIEW(dev)) {
9424 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9425 dev_priv->display.get_clock = i9xx_crtc_clock_get;
89b667f8
JB		 9426 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9427 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9428 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9429 dev_priv->display.off = i9xx_crtc_off;
9430 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9431 } else {
0e8ffe1b 9432 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f1f644dc 9433 dev_priv->display.get_clock = i9xx_crtc_clock_get;
f564048e 9434 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9435 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9436 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9437 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9438 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9439 }
e70236a8 9440
e70236a8 9441 /* Returns the core display clock speed */
25eb05fc
JB		 9442 if (IS_VALLEYVIEW(dev))
9443 dev_priv->display.get_display_clock_speed =
9444 valleyview_get_display_clock_speed;
9445 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9446 dev_priv->display.get_display_clock_speed =
9447 i945_get_display_clock_speed;
9448 else if (IS_I915G(dev))
9449 dev_priv->display.get_display_clock_speed =
9450 i915_get_display_clock_speed;
f2b115e6 9451 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9452 dev_priv->display.get_display_clock_speed =
9453 i9xx_misc_get_display_clock_speed;
9454 else if (IS_I915GM(dev))
9455 dev_priv->display.get_display_clock_speed =
9456 i915gm_get_display_clock_speed;
9457 else if (IS_I865G(dev))
9458 dev_priv->display.get_display_clock_speed =
9459 i865_get_display_clock_speed;
f0f8a9ce 9460 else if (IS_I85X(dev))
e70236a8
JB		 9461 dev_priv->display.get_display_clock_speed =
9462 i855_get_display_clock_speed;
9463 else /* 852, 830 */
9464 dev_priv->display.get_display_clock_speed =
9465 i830_get_display_clock_speed;
9466
7f8a8569 9467 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9468 if (IS_GEN5(dev)) {
674cf967 9469 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9470 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9471 } else if (IS_GEN6(dev)) {
674cf967 9472 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9473 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9474 } else if (IS_IVYBRIDGE(dev)) {
9475 /* FIXME: detect B0+ stepping and use auto training */
9476 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9477 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9478 dev_priv->display.modeset_global_resources =
9479 ivb_modeset_global_resources;
c82e4d26
ED		 9480 } else if (IS_HASWELL(dev)) {
9481 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9482 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9483 dev_priv->display.modeset_global_resources =
9484 haswell_modeset_global_resources;
a0e63c22 9485 }
6067aaea 9486 } else if (IS_G4X(dev)) {
e0dac65e 9487 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9488 }
8c9f3aaf
JB		 9489
9490 /* Default just returns -ENODEV to indicate unsupported */
9491 dev_priv->display.queue_flip = intel_default_queue_flip;
9492
9493 switch (INTEL_INFO(dev)->gen) {
9494 case 2:
9495 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9496 break;
9497
9498 case 3:
9499 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9500 break;
9501
9502 case 4:
9503 case 5:
9504 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9505 break;
9506
9507 case 6:
9508 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9509 break;
7c9017e5
JB		 9510 case 7:
9511 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9512 break;
8c9f3aaf 9513 }
e70236a8
JB		 9514}
9515
b690e96c
JB		 9516/*
9517 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9518 * resume, or other times. This quirk makes sure that's the case for
9519 * affected systems.
9520 */
0206e353 9521static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9522{
9523 struct drm_i915_private *dev_priv = dev->dev_private;
9524
9525 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9526 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9527}
9528
435793df
KP		 9529/*
9530 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9531 */
9532static void quirk_ssc_force_disable(struct drm_device *dev)
9533{
9534 struct drm_i915_private *dev_priv = dev->dev_private;
9535 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9536 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9537}
9538
4dca20ef 9539/*
5a15ab5b
CE		 9540 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9541 * brightness value
4dca20ef
CE		 9542 */
9543static void quirk_invert_brightness(struct drm_device *dev)
9544{
9545 struct drm_i915_private *dev_priv = dev->dev_private;
9546 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9547 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9548}
9549
b690e96c
JB		 9550struct intel_quirk {
9551 int device;
9552 int subsystem_vendor;
9553 int subsystem_device;
9554 void (*hook)(struct drm_device *dev);
9555};
9556
5f85f176
EE		 9557/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9558struct intel_dmi_quirk {
9559 void (*hook)(struct drm_device *dev);
9560 const struct dmi_system_id (*dmi_id_list)[];
9561};
9562
9563static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9564{
9565 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9566 return 1;
9567}
9568
9569static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9570 {
9571 .dmi_id_list = &(const struct dmi_system_id[]) {
9572 {
9573 .callback = intel_dmi_reverse_brightness,
9574 .ident = "NCR Corporation",
9575 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9576 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9577 },
9578 },
9579 { } /* terminating entry */
9580 },
9581 .hook = quirk_invert_brightness,
9582 },
9583};
9584
c43b5634 9585static struct intel_quirk intel_quirks[] = {
b690e96c 9586 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9587 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9588
b690e96c
JB		 9589 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9590 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9591
b690e96c
JB		 9592 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9593 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9594
ccd0d36e 9595 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9596 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9597 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9598
9599 /* Lenovo U160 cannot use SSC on LVDS */
9600 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9601
9602 /* Sony Vaio Y cannot use SSC on LVDS */
9603 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9604
9605 /* Acer Aspire 5734Z must invert backlight brightness */
9606 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9607
9608 /* Acer/eMachines G725 */
9609 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9610
9611 /* Acer/eMachines e725 */
9612 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9613
9614 /* Acer/Packard Bell NCL20 */
9615 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9616
9617 /* Acer Aspire 4736Z */
9618 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9619};
9620
9621static void intel_init_quirks(struct drm_device *dev)
9622{
9623 struct pci_dev *d = dev->pdev;
9624 int i;
9625
9626 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9627 struct intel_quirk *q = &intel_quirks[i];
9628
9629 if (d->device == q->device &&
9630 (d->subsystem_vendor == q->subsystem_vendor ||
9631 q->subsystem_vendor == PCI_ANY_ID) &&
9632 (d->subsystem_device == q->subsystem_device ||
9633 q->subsystem_device == PCI_ANY_ID))
9634 q->hook(dev);
9635 }
5f85f176
EE		 9636 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9637 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9638 intel_dmi_quirks[i].hook(dev);
9639 }
b690e96c
JB		 9640}
9641
9cce37f4
JB		 9642/* Disable the VGA plane that we never use */
9643static void i915_disable_vga(struct drm_device *dev)
9644{
9645 struct drm_i915_private *dev_priv = dev->dev_private;
9646 u8 sr1;
766aa1c4 9647 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9648
9649 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9650 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9651 sr1 = inb(VGA_SR_DATA);
9652 outb(sr1 | 1<<5, VGA_SR_DATA);
9653 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9654 udelay(300);
9655
9656 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9657 POSTING_READ(vga_reg);
9658}
9659
f817586c
DV		 9660void intel_modeset_init_hw(struct drm_device *dev)
9661{
fa42e23c 9662 intel_init_power_well(dev);
0232e927 9663
a8f78b58
ED		 9664 intel_prepare_ddi(dev);
9665
f817586c
DV		 9666 intel_init_clock_gating(dev);
9667
79f5b2c7 9668 mutex_lock(&dev->struct_mutex);
8090c6b9 9669 intel_enable_gt_powersave(dev);
79f5b2c7 9670 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9671}
9672
7d708ee4
ID		 9673void intel_modeset_suspend_hw(struct drm_device *dev)
9674{
9675 intel_suspend_hw(dev);
9676}
9677
79e53945
JB		 9678void intel_modeset_init(struct drm_device *dev)
9679{
652c393a 9680 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9681 int i, j, ret;
79e53945
JB		 9682
9683 drm_mode_config_init(dev);
9684
9685 dev->mode_config.min_width = 0;
9686 dev->mode_config.min_height = 0;
9687
019d96cb
DA		 9688 dev->mode_config.preferred_depth = 24;
9689 dev->mode_config.prefer_shadow = 1;
9690
e6ecefaa 9691 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9692
b690e96c
JB		 9693 intel_init_quirks(dev);
9694
1fa61106
ED		 9695 intel_init_pm(dev);
9696
e3c74757
BW		 9697 if (INTEL_INFO(dev)->num_pipes == 0)
9698 return;
9699
e70236a8
JB		 9700 intel_init_display(dev);
9701
a6c45cf0
CW		 9702 if (IS_GEN2(dev)) {
9703 dev->mode_config.max_width = 2048;
9704 dev->mode_config.max_height = 2048;
9705 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9706 dev->mode_config.max_width = 4096;
9707 dev->mode_config.max_height = 4096;
79e53945 9708 } else {
a6c45cf0
CW		 9709 dev->mode_config.max_width = 8192;
9710 dev->mode_config.max_height = 8192;
79e53945 9711 }
5d4545ae 9712 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9713
28c97730 9714 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9715 INTEL_INFO(dev)->num_pipes,
9716 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9717
7eb552ae 9718 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9719 intel_crtc_init(dev, i);
7f1f3851
JB		 9720 for (j = 0; j < dev_priv->num_plane; j++) {
9721 ret = intel_plane_init(dev, i, j);
9722 if (ret)
06da8da2
VS		 9723 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9724 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9725 }
79e53945
JB		 9726 }
9727
79f689aa 9728 intel_cpu_pll_init(dev);
e72f9fbf 9729 intel_shared_dpll_init(dev);
ee7b9f93 9730
9cce37f4
JB		 9731 /* Just disable it once at startup */
9732 i915_disable_vga(dev);
79e53945 9733 intel_setup_outputs(dev);
11be49eb
CW		 9734
9735 /* Just in case the BIOS is doing something questionable. */
9736 intel_disable_fbc(dev);
2c7111db
CW		 9737}
9738
24929352
DV		 9739static void
9740intel_connector_break_all_links(struct intel_connector *connector)
9741{
9742 connector->base.dpms = DRM_MODE_DPMS_OFF;
9743 connector->base.encoder = NULL;
9744 connector->encoder->connectors_active = false;
9745 connector->encoder->base.crtc = NULL;
9746}
9747
7fad798e
DV		 9748static void intel_enable_pipe_a(struct drm_device *dev)
9749{
9750 struct intel_connector *connector;
9751 struct drm_connector *crt = NULL;
9752 struct intel_load_detect_pipe load_detect_temp;
9753
9754 /* We can't just switch on the pipe A, we need to set things up with a
9755 * proper mode and output configuration. As a gross hack, enable pipe A
9756 * by enabling the load detect pipe once. */
9757 list_for_each_entry(connector,
9758 &dev->mode_config.connector_list,
9759 base.head) {
9760 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9761 crt = &connector->base;
9762 break;
9763 }
9764 }
9765
9766 if (!crt)
9767 return;
9768
9769 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9770 intel_release_load_detect_pipe(crt, &load_detect_temp);
9771
652c393a 9772
7fad798e
DV		 9773}
9774
fa555837
DV		 9775static bool
9776intel_check_plane_mapping(struct intel_crtc *crtc)
9777{
7eb552ae
BW		 9778 struct drm_device *dev = crtc->base.dev;
9779 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9780 u32 reg, val;
9781
7eb552ae 9782 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9783 return true;
9784
9785 reg = DSPCNTR(!crtc->plane);
9786 val = I915_READ(reg);
9787
9788 if ((val & DISPLAY_PLANE_ENABLE) &&
9789 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9790 return false;
9791
9792 return true;
9793}
9794
24929352
DV		 9795static void intel_sanitize_crtc(struct intel_crtc *crtc)
9796{
9797 struct drm_device *dev = crtc->base.dev;
9798 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9799 u32 reg;
24929352 9800
24929352 9801 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9802 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9803 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9804
9805 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9806 * disable the crtc (and hence change the state) if it is wrong. Note
9807 * that gen4+ has a fixed plane -> pipe mapping. */
9808 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9809 struct intel_connector *connector;
9810 bool plane;
9811
24929352
DV		 9812 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9813 crtc->base.base.id);
9814
9815 /* Pipe has the wrong plane attached and the plane is active.
9816 * Temporarily change the plane mapping and disable everything
9817 * ... */
9818 plane = crtc->plane;
9819 crtc->plane = !plane;
9820 dev_priv->display.crtc_disable(&crtc->base);
9821 crtc->plane = plane;
9822
9823 /* ... and break all links. */
9824 list_for_each_entry(connector, &dev->mode_config.connector_list,
9825 base.head) {
9826 if (connector->encoder->base.crtc != &crtc->base)
9827 continue;
9828
9829 intel_connector_break_all_links(connector);
9830 }
9831
9832 WARN_ON(crtc->active);
9833 crtc->base.enabled = false;
9834 }
24929352 9835
7fad798e
DV		 9836 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9837 crtc->pipe == PIPE_A && !crtc->active) {
9838 /* BIOS forgot to enable pipe A, this mostly happens after
9839 * resume. Force-enable the pipe to fix this, the update_dpms
9840 * call below we restore the pipe to the right state, but leave
9841 * the required bits on. */
9842 intel_enable_pipe_a(dev);
9843 }
9844
24929352
DV		 9845 /* Adjust the state of the output pipe according to whether we
9846 * have active connectors/encoders. */
9847 intel_crtc_update_dpms(&crtc->base);
9848
9849 if (crtc->active != crtc->base.enabled) {
9850 struct intel_encoder *encoder;
9851
9852 /* This can happen either due to bugs in the get_hw_state
9853 * functions or because the pipe is force-enabled due to the
9854 * pipe A quirk. */
9855 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9856 crtc->base.base.id,
9857 crtc->base.enabled ? "enabled" : "disabled",
9858 crtc->active ? "enabled" : "disabled");
9859
9860 crtc->base.enabled = crtc->active;
9861
9862 /* Because we only establish the connector -> encoder ->
9863 * crtc links if something is active, this means the
9864 * crtc is now deactivated. Break the links. connector
9865 * -> encoder links are only establish when things are
9866 * actually up, hence no need to break them. */
9867 WARN_ON(crtc->active);
9868
9869 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9870 WARN_ON(encoder->connectors_active);
9871 encoder->base.crtc = NULL;
9872 }
9873 }
9874}
9875
9876static void intel_sanitize_encoder(struct intel_encoder *encoder)
9877{
9878 struct intel_connector *connector;
9879 struct drm_device *dev = encoder->base.dev;
9880
9881 /* We need to check both for a crtc link (meaning that the
9882 * encoder is active and trying to read from a pipe) and the
9883 * pipe itself being active. */
9884 bool has_active_crtc = encoder->base.crtc &&
9885 to_intel_crtc(encoder->base.crtc)->active;
9886
9887 if (encoder->connectors_active && !has_active_crtc) {
9888 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9889 encoder->base.base.id,
9890 drm_get_encoder_name(&encoder->base));
9891
9892 /* Connector is active, but has no active pipe. This is
9893 * fallout from our resume register restoring. Disable
9894 * the encoder manually again. */
9895 if (encoder->base.crtc) {
9896 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9897 encoder->base.base.id,
9898 drm_get_encoder_name(&encoder->base));
9899 encoder->disable(encoder);
9900 }
9901
9902 /* Inconsistent output/port/pipe state happens presumably due to
9903 * a bug in one of the get_hw_state functions. Or someplace else
9904 * in our code, like the register restore mess on resume. Clamp
9905 * things to off as a safer default. */
9906 list_for_each_entry(connector,
9907 &dev->mode_config.connector_list,
9908 base.head) {
9909 if (connector->encoder != encoder)
9910 continue;
9911
9912 intel_connector_break_all_links(connector);
9913 }
9914 }
9915 /* Enabled encoders without active connectors will be fixed in
9916 * the crtc fixup. */
9917}
9918
44cec740 9919void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9920{
9921 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9922 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9923
9924 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9925 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9926 i915_disable_vga(dev);
0fde901f
KM		 9927 }
9928}
9929
30e984df 9930static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 9931{
9932 struct drm_i915_private *dev_priv = dev->dev_private;
9933 enum pipe pipe;
24929352
DV		 9934 struct intel_crtc *crtc;
9935 struct intel_encoder *encoder;
9936 struct intel_connector *connector;
5358901f 9937 int i;
24929352 9938
0e8ffe1b
DV		 9939 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9940 base.head) {
88adfff1 9941 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 9942
0e8ffe1b
DV		 9943 crtc->active = dev_priv->display.get_pipe_config(crtc,
9944 &crtc->config);
24929352
DV		 9945
9946 crtc->base.enabled = crtc->active;
9947
9948 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9949 crtc->base.base.id,
9950 crtc->active ? "enabled" : "disabled");
9951 }
9952
5358901f 9953 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 9954 if (HAS_DDI(dev))
6441ab5f
PZ		 9955 intel_ddi_setup_hw_pll_state(dev);
9956
5358901f
DV		 9957 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9958 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9959
9960 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
9961 pll->active = 0;
9962 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9963 base.head) {
9964 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9965 pll->active++;
9966 }
9967 pll->refcount = pll->active;
9968
9969 DRM_DEBUG_KMS("%s hw state readout: refcount %i\n",
9970 pll->name, pll->refcount);
9971 }
9972
24929352
DV		 9973 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9974 base.head) {
9975 pipe = 0;
9976
9977 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 9978 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9979 encoder->base.crtc = &crtc->base;
510d5f2f 9980 if (encoder->get_config)
045ac3b5 9981 encoder->get_config(encoder, &crtc->config);
24929352
DV		 9982 } else {
9983 encoder->base.crtc = NULL;
9984 }
9985
9986 encoder->connectors_active = false;
9987 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9988 encoder->base.base.id,
9989 drm_get_encoder_name(&encoder->base),
9990 encoder->base.crtc ? "enabled" : "disabled",
9991 pipe);
9992 }
9993
510d5f2f
JB		 9994 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9995 base.head) {
9996 if (!crtc->active)
9997 continue;
9998 if (dev_priv->display.get_clock)
9999 dev_priv->display.get_clock(crtc,
10000 &crtc->config);
10001 }
10002
24929352
DV		 10003 list_for_each_entry(connector, &dev->mode_config.connector_list,
10004 base.head) {
10005 if (connector->get_hw_state(connector)) {
10006 connector->base.dpms = DRM_MODE_DPMS_ON;
10007 connector->encoder->connectors_active = true;
10008 connector->base.encoder = &connector->encoder->base;
10009 } else {
10010 connector->base.dpms = DRM_MODE_DPMS_OFF;
10011 connector->base.encoder = NULL;
10012 }
10013 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10014 connector->base.base.id,
10015 drm_get_connector_name(&connector->base),
10016 connector->base.encoder ? "enabled" : "disabled");
10017 }
30e984df
DV		 10018}
10019
10020/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10021 * and i915 state tracking structures. */
10022void intel_modeset_setup_hw_state(struct drm_device *dev,
10023 bool force_restore)
10024{
10025 struct drm_i915_private *dev_priv = dev->dev_private;
10026 enum pipe pipe;
10027 struct drm_plane *plane;
10028 struct intel_crtc *crtc;
10029 struct intel_encoder *encoder;
10030
10031 intel_modeset_readout_hw_state(dev);
24929352 10032
babea61d
JB		 10033 /*
10034 * Now that we have the config, copy it to each CRTC struct
10035 * Note that this could go away if we move to using crtc_config
10036 * checking everywhere.
10037 */
10038 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10039 base.head) {
10040 if (crtc->active && i915_fastboot) {
10041 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10042
10043 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10044 crtc->base.base.id);
10045 drm_mode_debug_printmodeline(&crtc->base.mode);
10046 }
10047 }
10048
24929352
DV		 10049 /* HW state is read out, now we need to sanitize this mess. */
10050 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10051 base.head) {
10052 intel_sanitize_encoder(encoder);
10053 }
10054
10055 for_each_pipe(pipe) {
10056 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10057 intel_sanitize_crtc(crtc);
c0b03411 10058 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10059 }
9a935856 10060
45e2b5f6 10061 if (force_restore) {
f30da187
DV		 10062 /*
10063 * We need to use raw interfaces for restoring state to avoid
10064 * checking (bogus) intermediate states.
10065 */
45e2b5f6 10066 for_each_pipe(pipe) {
b5644d05
JB		 10067 struct drm_crtc *crtc =
10068 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10069
10070 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10071 crtc->fb);
45e2b5f6 10072 }
b5644d05
JB		 10073 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
10074 intel_plane_restore(plane);
0fde901f
KM		 10075
10076 i915_redisable_vga(dev);
45e2b5f6
DV		 10077 } else {
10078 intel_modeset_update_staged_output_state(dev);
10079 }
8af6cf88
DV		 10080
10081 intel_modeset_check_state(dev);
2e938892
DV		 10082
10083 drm_mode_config_reset(dev);
2c7111db
CW		 10084}
10085
10086void intel_modeset_gem_init(struct drm_device *dev)
10087{
1833b134 10088 intel_modeset_init_hw(dev);
02e792fb
DV		 10089
10090 intel_setup_overlay(dev);
24929352 10091
45e2b5f6 10092 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10093}
10094
10095void intel_modeset_cleanup(struct drm_device *dev)
10096{
652c393a
JB		 10097 struct drm_i915_private *dev_priv = dev->dev_private;
10098 struct drm_crtc *crtc;
10099 struct intel_crtc *intel_crtc;
10100
fd0c0642
DV		 10101 /*
10102 * Interrupts and polling as the first thing to avoid creating havoc.
10103 * Too much stuff here (turning of rps, connectors, ...) would
10104 * experience fancy races otherwise.
10105 */
10106 drm_irq_uninstall(dev);
10107 cancel_work_sync(&dev_priv->hotplug_work);
10108 /*
10109 * Due to the hpd irq storm handling the hotplug work can re-arm the
10110 * poll handlers. Hence disable polling after hpd handling is shut down.
10111 */
f87ea761 10112 drm_kms_helper_poll_fini(dev);
fd0c0642 10113
652c393a
JB		 10114 mutex_lock(&dev->struct_mutex);
10115
723bfd70
JB		 10116 intel_unregister_dsm_handler();
10117
652c393a
JB		 10118 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10119 /* Skip inactive CRTCs */
10120 if (!crtc->fb)
10121 continue;
10122
10123 intel_crtc = to_intel_crtc(crtc);
3dec0095 10124 intel_increase_pllclock(crtc);
652c393a
JB		 10125 }
10126
973d04f9 10127 intel_disable_fbc(dev);
e70236a8 10128
8090c6b9 10129 intel_disable_gt_powersave(dev);
0cdab21f 10130
930ebb46
DV		 10131 ironlake_teardown_rc6(dev);
10132
69341a5e
KH		 10133 mutex_unlock(&dev->struct_mutex);
10134
1630fe75
CW		 10135 /* flush any delayed tasks or pending work */
10136 flush_scheduled_work();
10137
dc652f90
JN		 10138 /* destroy backlight, if any, before the connectors */
10139 intel_panel_destroy_backlight(dev);
10140
79e53945 10141 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10142
10143 intel_cleanup_overlay(dev);
79e53945
JB		 10144}
10145
f1c79df3
ZW		 10146/*
10147 * Return which encoder is currently attached for connector.
10148 */
df0e9248 10149struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10150{
df0e9248
CW		 10151 return &intel_attached_encoder(connector)->base;
10152}
f1c79df3 10153
df0e9248
CW		 10154void intel_connector_attach_encoder(struct intel_connector *connector,
10155 struct intel_encoder *encoder)
10156{
10157 connector->encoder = encoder;
10158 drm_mode_connector_attach_encoder(&connector->base,
10159 &encoder->base);
79e53945 10160}
28d52043
DA		 10161
10162/*
10163 * set vga decode state - true == enable VGA decode
10164 */
10165int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10166{
10167 struct drm_i915_private *dev_priv = dev->dev_private;
10168 u16 gmch_ctrl;
10169
10170 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10171 if (state)
10172 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10173 else
10174 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10175 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10176 return 0;
10177}
c4a1d9e4
CW		 10178
10179#ifdef CONFIG_DEBUG_FS
10180#include <linux/seq_file.h>
10181
10182struct intel_display_error_state {
ff57f1b0
PZ		 10183
10184 u32 power_well_driver;
10185
c4a1d9e4
CW		 10186 struct intel_cursor_error_state {
10187 u32 control;
10188 u32 position;
10189 u32 base;
10190 u32 size;
52331309 10191 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10192
10193 struct intel_pipe_error_state {
ff57f1b0 10194 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 10195 u32 conf;
10196 u32 source;
10197
10198 u32 htotal;
10199 u32 hblank;
10200 u32 hsync;
10201 u32 vtotal;
10202 u32 vblank;
10203 u32 vsync;
52331309 10204 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10205
10206 struct intel_plane_error_state {
10207 u32 control;
10208 u32 stride;
10209 u32 size;
10210 u32 pos;
10211 u32 addr;
10212 u32 surface;
10213 u32 tile_offset;
52331309 10214 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 10215};
10216
10217struct intel_display_error_state *
10218intel_display_capture_error_state(struct drm_device *dev)
10219{
0206e353 10220 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10221 struct intel_display_error_state *error;
702e7a56 10222 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 10223 int i;
10224
10225 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10226 if (error == NULL)
10227 return NULL;
10228
ff57f1b0
PZ		 10229 if (HAS_POWER_WELL(dev))
10230 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
10231
52331309 10232 for_each_pipe(i) {
702e7a56 10233 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 10234 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 10235
a18c4c3d
PZ		 10236 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
10237 error->cursor[i].control = I915_READ(CURCNTR(i));
10238 error->cursor[i].position = I915_READ(CURPOS(i));
10239 error->cursor[i].base = I915_READ(CURBASE(i));
10240 } else {
10241 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
10242 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
10243 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
10244 }
c4a1d9e4
CW		 10245
10246 error->plane[i].control = I915_READ(DSPCNTR(i));
10247 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 10248 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 10249 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 10250 error->plane[i].pos = I915_READ(DSPPOS(i));
10251 }
ca291363
PZ		 10252 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
10253 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 10254 if (INTEL_INFO(dev)->gen >= 4) {
10255 error->plane[i].surface = I915_READ(DSPSURF(i));
10256 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
10257 }
10258
702e7a56 10259 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 10260 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 10261 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
10262 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
10263 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
10264 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
10265 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
10266 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 10267 }
10268
12d217c7
PZ		 10269 /* In the code above we read the registers without checking if the power
10270 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
10271 * prevent the next I915_WRITE from detecting it and printing an error
10272 * message. */
10273 if (HAS_POWER_WELL(dev))
10274 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
10275
c4a1d9e4
CW		 10276 return error;
10277}
10278
edc3d884
MK		 10279#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
10280
c4a1d9e4 10281void
edc3d884 10282intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 10283 struct drm_device *dev,
10284 struct intel_display_error_state *error)
10285{
10286 int i;
10287
edc3d884 10288 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 10289 if (HAS_POWER_WELL(dev))
edc3d884 10290 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 10291 error->power_well_driver);
52331309 10292 for_each_pipe(i) {
edc3d884
MK		 10293 err_printf(m, "Pipe [%d]:\n", i);
10294 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 10295 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 10296 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
10297 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
10298 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
10299 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
10300 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
10301 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
10302 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
10303 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
10304
10305 err_printf(m, "Plane [%d]:\n", i);
10306 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
10307 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 10308 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 10309 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
10310 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 10311 }
4b71a570 10312 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 10313 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 10314 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 10315 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
10316 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 10317 }
10318
edc3d884
MK		 10319 err_printf(m, "Cursor [%d]:\n", i);
10320 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
10321 err_printf(m, " POS: %08x\n", error->cursor[i].position);
10322 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 10323 }
10324}
10325#endif
Linux kernel - Deliverables
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