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drm/i915: fold in IS_PNV checks from the split up find_dpll functions
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 47
79e53945 48typedef struct {
0206e353 49 int min, max;
79e53945
JB		 50} intel_range_t;
51
52typedef struct {
0206e353
AJ		 53 int dot_limit;
54 int p2_slow, p2_fast;
79e53945
JB		 55} intel_p2_t;
56
57#define INTEL_P2_NUM 2
d4906093
ML		 58typedef struct intel_limit intel_limit_t;
59struct intel_limit {
0206e353
AJ		 60 intel_range_t dot, vco, n, m, m1, m2, p, p1;
61 intel_p2_t p2;
d4906093 62};
79e53945 63
2377b741
JB		 64/* FDI */
65#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
66
d2acd215
DV		 67int
68intel_pch_rawclk(struct drm_device *dev)
69{
70 struct drm_i915_private *dev_priv = dev->dev_private;
71
72 WARN_ON(!HAS_PCH_SPLIT(dev));
73
74 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
75}
76
021357ac
CW		 77static inline u32 /* units of 100MHz */
78intel_fdi_link_freq(struct drm_device *dev)
79{
8b99e68c
CW		 80 if (IS_GEN5(dev)) {
81 struct drm_i915_private *dev_priv = dev->dev_private;
82 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
83 } else
84 return 27;
021357ac
CW		 85}
86
e4b36699 87static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 88 .dot = { .min = 25000, .max = 350000 },
89 .vco = { .min = 930000, .max = 1400000 },
90 .n = { .min = 3, .max = 16 },
91 .m = { .min = 96, .max = 140 },
92 .m1 = { .min = 18, .max = 26 },
93 .m2 = { .min = 6, .max = 16 },
94 .p = { .min = 4, .max = 128 },
95 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 96 .p2 = { .dot_limit = 165000,
97 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 98};
99
100static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 101 .dot = { .min = 25000, .max = 350000 },
102 .vco = { .min = 930000, .max = 1400000 },
103 .n = { .min = 3, .max = 16 },
104 .m = { .min = 96, .max = 140 },
105 .m1 = { .min = 18, .max = 26 },
106 .m2 = { .min = 6, .max = 16 },
107 .p = { .min = 4, .max = 128 },
108 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 109 .p2 = { .dot_limit = 165000,
110 .p2_slow = 14, .p2_fast = 7 },
e4b36699 111};
273e27ca 112
e4b36699 113static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 114 .dot = { .min = 20000, .max = 400000 },
115 .vco = { .min = 1400000, .max = 2800000 },
116 .n = { .min = 1, .max = 6 },
117 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 118 .m1 = { .min = 8, .max = 18 },
119 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 120 .p = { .min = 5, .max = 80 },
121 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 122 .p2 = { .dot_limit = 200000,
123 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 124};
125
126static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 127 .dot = { .min = 20000, .max = 400000 },
128 .vco = { .min = 1400000, .max = 2800000 },
129 .n = { .min = 1, .max = 6 },
130 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 131 .m1 = { .min = 8, .max = 18 },
132 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 133 .p = { .min = 7, .max = 98 },
134 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 135 .p2 = { .dot_limit = 112000,
136 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 137};
138
273e27ca 139
e4b36699 140static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 141 .dot = { .min = 25000, .max = 270000 },
142 .vco = { .min = 1750000, .max = 3500000},
143 .n = { .min = 1, .max = 4 },
144 .m = { .min = 104, .max = 138 },
145 .m1 = { .min = 17, .max = 23 },
146 .m2 = { .min = 5, .max = 11 },
147 .p = { .min = 10, .max = 30 },
148 .p1 = { .min = 1, .max = 3},
149 .p2 = { .dot_limit = 270000,
150 .p2_slow = 10,
151 .p2_fast = 10
044c7c41 152 },
e4b36699
KP		 153};
154
155static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 156 .dot = { .min = 22000, .max = 400000 },
157 .vco = { .min = 1750000, .max = 3500000},
158 .n = { .min = 1, .max = 4 },
159 .m = { .min = 104, .max = 138 },
160 .m1 = { .min = 16, .max = 23 },
161 .m2 = { .min = 5, .max = 11 },
162 .p = { .min = 5, .max = 80 },
163 .p1 = { .min = 1, .max = 8},
164 .p2 = { .dot_limit = 165000,
165 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 166};
167
168static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 169 .dot = { .min = 20000, .max = 115000 },
170 .vco = { .min = 1750000, .max = 3500000 },
171 .n = { .min = 1, .max = 3 },
172 .m = { .min = 104, .max = 138 },
173 .m1 = { .min = 17, .max = 23 },
174 .m2 = { .min = 5, .max = 11 },
175 .p = { .min = 28, .max = 112 },
176 .p1 = { .min = 2, .max = 8 },
177 .p2 = { .dot_limit = 0,
178 .p2_slow = 14, .p2_fast = 14
044c7c41 179 },
e4b36699
KP		 180};
181
182static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 183 .dot = { .min = 80000, .max = 224000 },
184 .vco = { .min = 1750000, .max = 3500000 },
185 .n = { .min = 1, .max = 3 },
186 .m = { .min = 104, .max = 138 },
187 .m1 = { .min = 17, .max = 23 },
188 .m2 = { .min = 5, .max = 11 },
189 .p = { .min = 14, .max = 42 },
190 .p1 = { .min = 2, .max = 6 },
191 .p2 = { .dot_limit = 0,
192 .p2_slow = 7, .p2_fast = 7
044c7c41 193 },
e4b36699
KP		 194};
195
f2b115e6 196static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 197 .dot = { .min = 20000, .max = 400000},
198 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 199 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 200 .n = { .min = 3, .max = 6 },
201 .m = { .min = 2, .max = 256 },
273e27ca 202 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 203 .m1 = { .min = 0, .max = 0 },
204 .m2 = { .min = 0, .max = 254 },
205 .p = { .min = 5, .max = 80 },
206 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 207 .p2 = { .dot_limit = 200000,
208 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 209};
210
f2b115e6 211static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 212 .dot = { .min = 20000, .max = 400000 },
213 .vco = { .min = 1700000, .max = 3500000 },
214 .n = { .min = 3, .max = 6 },
215 .m = { .min = 2, .max = 256 },
216 .m1 = { .min = 0, .max = 0 },
217 .m2 = { .min = 0, .max = 254 },
218 .p = { .min = 7, .max = 112 },
219 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 220 .p2 = { .dot_limit = 112000,
221 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 222};
223
273e27ca
EA		 224/* Ironlake / Sandybridge
225 *
226 * We calculate clock using (register_value + 2) for N/M1/M2, so here
227 * the range value for them is (actual_value - 2).
228 */
b91ad0ec 229static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 230 .dot = { .min = 25000, .max = 350000 },
231 .vco = { .min = 1760000, .max = 3510000 },
232 .n = { .min = 1, .max = 5 },
233 .m = { .min = 79, .max = 127 },
234 .m1 = { .min = 12, .max = 22 },
235 .m2 = { .min = 5, .max = 9 },
236 .p = { .min = 5, .max = 80 },
237 .p1 = { .min = 1, .max = 8 },
238 .p2 = { .dot_limit = 225000,
239 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 240};
241
b91ad0ec 242static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 243 .dot = { .min = 25000, .max = 350000 },
244 .vco = { .min = 1760000, .max = 3510000 },
245 .n = { .min = 1, .max = 3 },
246 .m = { .min = 79, .max = 118 },
247 .m1 = { .min = 12, .max = 22 },
248 .m2 = { .min = 5, .max = 9 },
249 .p = { .min = 28, .max = 112 },
250 .p1 = { .min = 2, .max = 8 },
251 .p2 = { .dot_limit = 225000,
252 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 253};
254
255static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 256 .dot = { .min = 25000, .max = 350000 },
257 .vco = { .min = 1760000, .max = 3510000 },
258 .n = { .min = 1, .max = 3 },
259 .m = { .min = 79, .max = 127 },
260 .m1 = { .min = 12, .max = 22 },
261 .m2 = { .min = 5, .max = 9 },
262 .p = { .min = 14, .max = 56 },
263 .p1 = { .min = 2, .max = 8 },
264 .p2 = { .dot_limit = 225000,
265 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 266};
267
273e27ca 268/* LVDS 100mhz refclk limits. */
b91ad0ec 269static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 270 .dot = { .min = 25000, .max = 350000 },
271 .vco = { .min = 1760000, .max = 3510000 },
272 .n = { .min = 1, .max = 2 },
273 .m = { .min = 79, .max = 126 },
274 .m1 = { .min = 12, .max = 22 },
275 .m2 = { .min = 5, .max = 9 },
276 .p = { .min = 28, .max = 112 },
0206e353 277 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 278 .p2 = { .dot_limit = 225000,
279 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 280};
281
282static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 3 },
286 .m = { .min = 79, .max = 126 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 14, .max = 42 },
0206e353 290 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 293};
294
a0c4da24
JB		 295static const intel_limit_t intel_limits_vlv_dac = {
296 .dot = { .min = 25000, .max = 270000 },
297 .vco = { .min = 4000000, .max = 6000000 },
298 .n = { .min = 1, .max = 7 },
299 .m = { .min = 22, .max = 450 }, /* guess */
300 .m1 = { .min = 2, .max = 3 },
301 .m2 = { .min = 11, .max = 156 },
302 .p = { .min = 10, .max = 30 },
75e53986 303 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 304 .p2 = { .dot_limit = 270000,
305 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 306};
307
308static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 309 .dot = { .min = 25000, .max = 270000 },
310 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 311 .n = { .min = 1, .max = 7 },
312 .m = { .min = 60, .max = 300 }, /* guess */
313 .m1 = { .min = 2, .max = 3 },
314 .m2 = { .min = 11, .max = 156 },
315 .p = { .min = 10, .max = 30 },
316 .p1 = { .min = 2, .max = 3 },
317 .p2 = { .dot_limit = 270000,
318 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 319};
320
321static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 322 .dot = { .min = 25000, .max = 270000 },
323 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 324 .n = { .min = 1, .max = 7 },
74a4dd2e 325 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 326 .m1 = { .min = 2, .max = 3 },
327 .m2 = { .min = 11, .max = 156 },
328 .p = { .min = 10, .max = 30 },
75e53986 329 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 330 .p2 = { .dot_limit = 270000,
331 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 332};
333
1b894b59
CW		 334static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
335 int refclk)
2c07245f 336{
b91ad0ec 337 struct drm_device *dev = crtc->dev;
2c07245f 338 const intel_limit_t *limit;
b91ad0ec
ZW		 339
340 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 341 if (intel_is_dual_link_lvds(dev)) {
1b894b59 342 if (refclk == 100000)
b91ad0ec
ZW		 343 limit = &intel_limits_ironlake_dual_lvds_100m;
344 else
345 limit = &intel_limits_ironlake_dual_lvds;
346 } else {
1b894b59 347 if (refclk == 100000)
b91ad0ec
ZW		 348 limit = &intel_limits_ironlake_single_lvds_100m;
349 else
350 limit = &intel_limits_ironlake_single_lvds;
351 }
c6bb3538 352 } else
b91ad0ec 353 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 354
355 return limit;
356}
357
044c7c41
ML		 358static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
359{
360 struct drm_device *dev = crtc->dev;
044c7c41
ML		 361 const intel_limit_t *limit;
362
363 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 364 if (intel_is_dual_link_lvds(dev))
e4b36699 365 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 366 else
e4b36699 367 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 368 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
369 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 370 limit = &intel_limits_g4x_hdmi;
044c7c41 371 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 372 limit = &intel_limits_g4x_sdvo;
044c7c41 373 } else /* The option is for other outputs */
e4b36699 374 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 375
376 return limit;
377}
378
1b894b59 379static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 380{
381 struct drm_device *dev = crtc->dev;
382 const intel_limit_t *limit;
383
bad720ff 384 if (HAS_PCH_SPLIT(dev))
1b894b59 385 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 386 else if (IS_G4X(dev)) {
044c7c41 387 limit = intel_g4x_limit(crtc);
f2b115e6 388 } else if (IS_PINEVIEW(dev)) {
2177832f 389 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 390 limit = &intel_limits_pineview_lvds;
2177832f 391 else
f2b115e6 392 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 393 } else if (IS_VALLEYVIEW(dev)) {
394 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
395 limit = &intel_limits_vlv_dac;
396 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
397 limit = &intel_limits_vlv_hdmi;
398 else
399 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 400 } else if (!IS_GEN2(dev)) {
401 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
402 limit = &intel_limits_i9xx_lvds;
403 else
404 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 405 } else {
406 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 407 limit = &intel_limits_i8xx_lvds;
79e53945 408 else
e4b36699 409 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 410 }
411 return limit;
412}
413
f2b115e6
AJ		 414/* m1 is reserved as 0 in Pineview, n is a ring counter */
415static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 416{
2177832f
SL		 417 clock->m = clock->m2 + 2;
418 clock->p = clock->p1 * clock->p2;
419 clock->vco = refclk * clock->m / clock->n;
420 clock->dot = clock->vco / clock->p;
421}
422
7429e9d4
DV		 423static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
424{
425 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
426}
427
ac58c3f0 428static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 429{
7429e9d4 430 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 431 clock->p = clock->p1 * clock->p2;
432 clock->vco = refclk * clock->m / (clock->n + 2);
433 clock->dot = clock->vco / clock->p;
434}
435
79e53945
JB		 436/**
437 * Returns whether any output on the specified pipe is of the specified type
438 */
4ef69c7a 439bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 440{
4ef69c7a 441 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 442 struct intel_encoder *encoder;
443
6c2b7c12
DV		 444 for_each_encoder_on_crtc(dev, crtc, encoder)
445 if (encoder->type == type)
4ef69c7a
CW		 446 return true;
447
448 return false;
79e53945
JB		 449}
450
7c04d1d9 451#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 452/**
453 * Returns whether the given set of divisors are valid for a given refclk with
454 * the given connectors.
455 */
456
1b894b59
CW		 457static bool intel_PLL_is_valid(struct drm_device *dev,
458 const intel_limit_t *limit,
459 const intel_clock_t *clock)
79e53945 460{
79e53945 461 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 462 INTELPllInvalid("p1 out of range\n");
79e53945 463 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 464 INTELPllInvalid("p out of range\n");
79e53945 465 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 466 INTELPllInvalid("m2 out of range\n");
79e53945 467 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 468 INTELPllInvalid("m1 out of range\n");
f2b115e6 469 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 470 INTELPllInvalid("m1 <= m2\n");
79e53945 471 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 472 INTELPllInvalid("m out of range\n");
79e53945 473 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 474 INTELPllInvalid("n out of range\n");
79e53945 475 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 476 INTELPllInvalid("vco out of range\n");
79e53945
JB		 477 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
478 * connector, etc., rather than just a single range.
479 */
480 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 481 INTELPllInvalid("dot out of range\n");
79e53945
JB		 482
483 return true;
484}
485
d4906093 486static bool
ee9300bb 487i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 488 int target, int refclk, intel_clock_t *match_clock,
489 intel_clock_t *best_clock)
ac58c3f0
DV		 490{
491 struct drm_device *dev = crtc->dev;
492 intel_clock_t clock;
493 int err = target;
494
495 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
496 /*
497 * For LVDS just rely on its current settings for dual-channel.
498 * We haven't figured out how to reliably set up different
499 * single/dual channel state, if we even can.
500 */
501 if (intel_is_dual_link_lvds(dev))
502 clock.p2 = limit->p2.p2_fast;
503 else
504 clock.p2 = limit->p2.p2_slow;
505 } else {
506 if (target < limit->p2.dot_limit)
507 clock.p2 = limit->p2.p2_slow;
508 else
509 clock.p2 = limit->p2.p2_fast;
510 }
511
512 memset(best_clock, 0, sizeof(*best_clock));
513
514 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
515 clock.m1++) {
516 for (clock.m2 = limit->m2.min;
517 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 518 if (clock.m2 >= clock.m1)
ac58c3f0
DV		 519 break;
520 for (clock.n = limit->n.min;
521 clock.n <= limit->n.max; clock.n++) {
522 for (clock.p1 = limit->p1.min;
523 clock.p1 <= limit->p1.max; clock.p1++) {
524 int this_err;
d4906093 525
ac58c3f0
DV		 526 i9xx_clock(refclk, &clock);
527 if (!intel_PLL_is_valid(dev, limit,
528 &clock))
529 continue;
530 if (match_clock &&
531 clock.p != match_clock->p)
532 continue;
533
534 this_err = abs(clock.dot - target);
535 if (this_err < err) {
536 *best_clock = clock;
537 err = this_err;
538 }
539 }
540 }
541 }
542 }
543
544 return (err != target);
545}
546
547static bool
ee9300bb
DV		 548pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
549 int target, int refclk, intel_clock_t *match_clock,
550 intel_clock_t *best_clock)
79e53945
JB		 551{
552 struct drm_device *dev = crtc->dev;
79e53945 553 intel_clock_t clock;
79e53945
JB		 554 int err = target;
555
a210b028 556 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 557 /*
a210b028
DV		 558 * For LVDS just rely on its current settings for dual-channel.
559 * We haven't figured out how to reliably set up different
560 * single/dual channel state, if we even can.
79e53945 561 */
1974cad0 562 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 563 clock.p2 = limit->p2.p2_fast;
564 else
565 clock.p2 = limit->p2.p2_slow;
566 } else {
567 if (target < limit->p2.dot_limit)
568 clock.p2 = limit->p2.p2_slow;
569 else
570 clock.p2 = limit->p2.p2_fast;
571 }
572
0206e353 573 memset(best_clock, 0, sizeof(*best_clock));
79e53945 574
42158660
ZY		 575 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
576 clock.m1++) {
577 for (clock.m2 = limit->m2.min;
578 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 579 for (clock.n = limit->n.min;
580 clock.n <= limit->n.max; clock.n++) {
581 for (clock.p1 = limit->p1.min;
582 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 583 int this_err;
584
ac58c3f0 585 pineview_clock(refclk, &clock);
1b894b59
CW		 586 if (!intel_PLL_is_valid(dev, limit,
587 &clock))
79e53945 588 continue;
cec2f356
SP		 589 if (match_clock &&
590 clock.p != match_clock->p)
591 continue;
79e53945
JB		 592
593 this_err = abs(clock.dot - target);
594 if (this_err < err) {
595 *best_clock = clock;
596 err = this_err;
597 }
598 }
599 }
600 }
601 }
602
603 return (err != target);
604}
605
d4906093 606static bool
ee9300bb
DV		 607g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
608 int target, int refclk, intel_clock_t *match_clock,
609 intel_clock_t *best_clock)
d4906093
ML		 610{
611 struct drm_device *dev = crtc->dev;
d4906093
ML		 612 intel_clock_t clock;
613 int max_n;
614 bool found;
6ba770dc
AJ		 615 /* approximately equals target * 0.00585 */
616 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 617 found = false;
618
619 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 620 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 621 clock.p2 = limit->p2.p2_fast;
622 else
623 clock.p2 = limit->p2.p2_slow;
624 } else {
625 if (target < limit->p2.dot_limit)
626 clock.p2 = limit->p2.p2_slow;
627 else
628 clock.p2 = limit->p2.p2_fast;
629 }
630
631 memset(best_clock, 0, sizeof(*best_clock));
632 max_n = limit->n.max;
f77f13e2 633 /* based on hardware requirement, prefer smaller n to precision */
d4906093 634 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 635 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 636 for (clock.m1 = limit->m1.max;
637 clock.m1 >= limit->m1.min; clock.m1--) {
638 for (clock.m2 = limit->m2.max;
639 clock.m2 >= limit->m2.min; clock.m2--) {
640 for (clock.p1 = limit->p1.max;
641 clock.p1 >= limit->p1.min; clock.p1--) {
642 int this_err;
643
ac58c3f0 644 i9xx_clock(refclk, &clock);
1b894b59
CW		 645 if (!intel_PLL_is_valid(dev, limit,
646 &clock))
d4906093 647 continue;
1b894b59
CW		 648
649 this_err = abs(clock.dot - target);
d4906093
ML		 650 if (this_err < err_most) {
651 *best_clock = clock;
652 err_most = this_err;
653 max_n = clock.n;
654 found = true;
655 }
656 }
657 }
658 }
659 }
2c07245f
ZW		 660 return found;
661}
662
a0c4da24 663static bool
ee9300bb
DV		 664vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
a0c4da24
JB		 667{
668 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
669 u32 m, n, fastclk;
670 u32 updrate, minupdate, fracbits, p;
671 unsigned long bestppm, ppm, absppm;
672 int dotclk, flag;
673
af447bd3 674 flag = 0;
a0c4da24
JB		 675 dotclk = target * 1000;
676 bestppm = 1000000;
677 ppm = absppm = 0;
678 fastclk = dotclk / (2*100);
679 updrate = 0;
680 minupdate = 19200;
681 fracbits = 1;
682 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
683 bestm1 = bestm2 = bestp1 = bestp2 = 0;
684
685 /* based on hardware requirement, prefer smaller n to precision */
686 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
687 updrate = refclk / n;
688 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
689 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
690 if (p2 > 10)
691 p2 = p2 - 1;
692 p = p1 * p2;
693 /* based on hardware requirement, prefer bigger m1,m2 values */
694 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
695 m2 = (((2*(fastclk * p * n / m1 )) +
696 refclk) / (2*refclk));
697 m = m1 * m2;
698 vco = updrate * m;
699 if (vco >= limit->vco.min && vco < limit->vco.max) {
700 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
701 absppm = (ppm > 0) ? ppm : (-ppm);
702 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
703 bestppm = 0;
704 flag = 1;
705 }
706 if (absppm < bestppm - 10) {
707 bestppm = absppm;
708 flag = 1;
709 }
710 if (flag) {
711 bestn = n;
712 bestm1 = m1;
713 bestm2 = m2;
714 bestp1 = p1;
715 bestp2 = p2;
716 flag = 0;
717 }
718 }
719 }
720 }
721 }
722 }
723 best_clock->n = bestn;
724 best_clock->m1 = bestm1;
725 best_clock->m2 = bestm2;
726 best_clock->p1 = bestp1;
727 best_clock->p2 = bestp2;
728
729 return true;
730}
a4fc5ed6 731
a5c961d1
PZ		 732enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
733 enum pipe pipe)
734{
735 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
736 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
737
3b117c8f 738 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 739}
740
a928d536
PZ		 741static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
742{
743 struct drm_i915_private *dev_priv = dev->dev_private;
744 u32 frame, frame_reg = PIPEFRAME(pipe);
745
746 frame = I915_READ(frame_reg);
747
748 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
749 DRM_DEBUG_KMS("vblank wait timed out\n");
750}
751
9d0498a2
JB		 752/**
753 * intel_wait_for_vblank - wait for vblank on a given pipe
754 * @dev: drm device
755 * @pipe: pipe to wait for
756 *
757 * Wait for vblank to occur on a given pipe. Needed for various bits of
758 * mode setting code.
759 */
760void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 761{
9d0498a2 762 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 763 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 764
a928d536
PZ		 765 if (INTEL_INFO(dev)->gen >= 5) {
766 ironlake_wait_for_vblank(dev, pipe);
767 return;
768 }
769
300387c0
CW		 770 /* Clear existing vblank status. Note this will clear any other
771 * sticky status fields as well.
772 *
773 * This races with i915_driver_irq_handler() with the result
774 * that either function could miss a vblank event. Here it is not
775 * fatal, as we will either wait upon the next vblank interrupt or
776 * timeout. Generally speaking intel_wait_for_vblank() is only
777 * called during modeset at which time the GPU should be idle and
778 * should *not* be performing page flips and thus not waiting on
779 * vblanks...
780 * Currently, the result of us stealing a vblank from the irq
781 * handler is that a single frame will be skipped during swapbuffers.
782 */
783 I915_WRITE(pipestat_reg,
784 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
785
9d0498a2 786 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 787 if (wait_for(I915_READ(pipestat_reg) &
788 PIPE_VBLANK_INTERRUPT_STATUS,
789 50))
9d0498a2
JB		 790 DRM_DEBUG_KMS("vblank wait timed out\n");
791}
792
ab7ad7f6
KP		 793/*
794 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 795 * @dev: drm device
796 * @pipe: pipe to wait for
797 *
798 * After disabling a pipe, we can't wait for vblank in the usual way,
799 * spinning on the vblank interrupt status bit, since we won't actually
800 * see an interrupt when the pipe is disabled.
801 *
ab7ad7f6
KP		 802 * On Gen4 and above:
803 * wait for the pipe register state bit to turn off
804 *
805 * Otherwise:
806 * wait for the display line value to settle (it usually
807 * ends up stopping at the start of the next frame).
58e10eb9 808 *
9d0498a2 809 */
58e10eb9 810void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 811{
812 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 813 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
814 pipe);
ab7ad7f6
KP		 815
816 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 817 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 818
819 /* Wait for the Pipe State to go off */
58e10eb9
CW		 820 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
821 100))
284637d9 822 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 823 } else {
837ba00f 824 u32 last_line, line_mask;
58e10eb9 825 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 826 unsigned long timeout = jiffies + msecs_to_jiffies(100);
827
837ba00f
PZ		 828 if (IS_GEN2(dev))
829 line_mask = DSL_LINEMASK_GEN2;
830 else
831 line_mask = DSL_LINEMASK_GEN3;
832
ab7ad7f6
KP		 833 /* Wait for the display line to settle */
834 do {
837ba00f 835 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 836 mdelay(5);
837ba00f 837 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 838 time_after(timeout, jiffies));
839 if (time_after(jiffies, timeout))
284637d9 840 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 841 }
79e53945
JB		 842}
843
b0ea7d37
DL		 844/*
845 * ibx_digital_port_connected - is the specified port connected?
846 * @dev_priv: i915 private structure
847 * @port: the port to test
848 *
849 * Returns true if @port is connected, false otherwise.
850 */
851bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
852 struct intel_digital_port *port)
853{
854 u32 bit;
855
c36346e3
DL		 856 if (HAS_PCH_IBX(dev_priv->dev)) {
857 switch(port->port) {
858 case PORT_B:
859 bit = SDE_PORTB_HOTPLUG;
860 break;
861 case PORT_C:
862 bit = SDE_PORTC_HOTPLUG;
863 break;
864 case PORT_D:
865 bit = SDE_PORTD_HOTPLUG;
866 break;
867 default:
868 return true;
869 }
870 } else {
871 switch(port->port) {
872 case PORT_B:
873 bit = SDE_PORTB_HOTPLUG_CPT;
874 break;
875 case PORT_C:
876 bit = SDE_PORTC_HOTPLUG_CPT;
877 break;
878 case PORT_D:
879 bit = SDE_PORTD_HOTPLUG_CPT;
880 break;
881 default:
882 return true;
883 }
b0ea7d37
DL		 884 }
885
886 return I915_READ(SDEISR) & bit;
887}
888
b24e7179
JB		 889static const char *state_string(bool enabled)
890{
891 return enabled ? "on" : "off";
892}
893
894/* Only for pre-ILK configs */
895static void assert_pll(struct drm_i915_private *dev_priv,
896 enum pipe pipe, bool state)
897{
898 int reg;
899 u32 val;
900 bool cur_state;
901
902 reg = DPLL(pipe);
903 val = I915_READ(reg);
904 cur_state = !!(val & DPLL_VCO_ENABLE);
905 WARN(cur_state != state,
906 "PLL state assertion failure (expected %s, current %s)\n",
907 state_string(state), state_string(cur_state));
908}
909#define assert_pll_enabled(d, p) assert_pll(d, p, true)
910#define assert_pll_disabled(d, p) assert_pll(d, p, false)
911
040484af
JB		 912/* For ILK+ */
913static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 914 struct intel_pch_pll *pll,
915 struct intel_crtc *crtc,
916 bool state)
040484af 917{
040484af
JB		 918 u32 val;
919 bool cur_state;
920
9d82aa17
ED		 921 if (HAS_PCH_LPT(dev_priv->dev)) {
922 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
923 return;
924 }
925
92b27b08
CW		 926 if (WARN (!pll,
927 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 928 return;
ee7b9f93 929
92b27b08
CW		 930 val = I915_READ(pll->pll_reg);
931 cur_state = !!(val & DPLL_VCO_ENABLE);
932 WARN(cur_state != state,
933 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
934 pll->pll_reg, state_string(state), state_string(cur_state), val);
935
936 /* Make sure the selected PLL is correctly attached to the transcoder */
937 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 938 u32 pch_dpll;
939
940 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 941 cur_state = pll->pll_reg == _PCH_DPLL_B;
942 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
4bb6f1f3
VS		 943 "PLL[%d] not attached to this transcoder %c: %08x\n",
944 cur_state, pipe_name(crtc->pipe), pch_dpll)) {
92b27b08
CW		 945 cur_state = !!(val >> (4*crtc->pipe + 3));
946 WARN(cur_state != state,
4bb6f1f3 947 "PLL[%d] not %s on this transcoder %c: %08x\n",
92b27b08
CW		 948 pll->pll_reg == _PCH_DPLL_B,
949 state_string(state),
4bb6f1f3 950 pipe_name(crtc->pipe),
92b27b08
CW		 951 val);
952 }
d3ccbe86 953 }
040484af 954}
92b27b08
CW		 955#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
956#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 957
958static void assert_fdi_tx(struct drm_i915_private *dev_priv,
959 enum pipe pipe, bool state)
960{
961 int reg;
962 u32 val;
963 bool cur_state;
ad80a810
PZ		 964 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
965 pipe);
040484af 966
affa9354
PZ		 967 if (HAS_DDI(dev_priv->dev)) {
968 /* DDI does not have a specific FDI_TX register */
ad80a810 969 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 970 val = I915_READ(reg);
ad80a810 971 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 972 } else {
973 reg = FDI_TX_CTL(pipe);
974 val = I915_READ(reg);
975 cur_state = !!(val & FDI_TX_ENABLE);
976 }
040484af
JB		 977 WARN(cur_state != state,
978 "FDI TX state assertion failure (expected %s, current %s)\n",
979 state_string(state), state_string(cur_state));
980}
981#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
982#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
983
984static void assert_fdi_rx(struct drm_i915_private *dev_priv,
985 enum pipe pipe, bool state)
986{
987 int reg;
988 u32 val;
989 bool cur_state;
990
d63fa0dc
PZ		 991 reg = FDI_RX_CTL(pipe);
992 val = I915_READ(reg);
993 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 994 WARN(cur_state != state,
995 "FDI RX state assertion failure (expected %s, current %s)\n",
996 state_string(state), state_string(cur_state));
997}
998#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
999#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1000
1001static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1002 enum pipe pipe)
1003{
1004 int reg;
1005 u32 val;
1006
1007 /* ILK FDI PLL is always enabled */
1008 if (dev_priv->info->gen == 5)
1009 return;
1010
bf507ef7 1011 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1012 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1013 return;
1014
040484af
JB		 1015 reg = FDI_TX_CTL(pipe);
1016 val = I915_READ(reg);
1017 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1018}
1019
1020static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1021 enum pipe pipe)
1022{
1023 int reg;
1024 u32 val;
1025
1026 reg = FDI_RX_CTL(pipe);
1027 val = I915_READ(reg);
1028 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1029}
1030
ea0760cf
JB		 1031static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1032 enum pipe pipe)
1033{
1034 int pp_reg, lvds_reg;
1035 u32 val;
1036 enum pipe panel_pipe = PIPE_A;
0de3b485 1037 bool locked = true;
ea0760cf
JB		 1038
1039 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1040 pp_reg = PCH_PP_CONTROL;
1041 lvds_reg = PCH_LVDS;
1042 } else {
1043 pp_reg = PP_CONTROL;
1044 lvds_reg = LVDS;
1045 }
1046
1047 val = I915_READ(pp_reg);
1048 if (!(val & PANEL_POWER_ON) ||
1049 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1050 locked = false;
1051
1052 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1053 panel_pipe = PIPE_B;
1054
1055 WARN(panel_pipe == pipe && locked,
1056 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1057 pipe_name(pipe));
ea0760cf
JB		 1058}
1059
b840d907
JB		 1060void assert_pipe(struct drm_i915_private *dev_priv,
1061 enum pipe pipe, bool state)
b24e7179
JB		 1062{
1063 int reg;
1064 u32 val;
63d7bbe9 1065 bool cur_state;
702e7a56
PZ		 1066 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1067 pipe);
b24e7179 1068
8e636784
DV		 1069 /* if we need the pipe A quirk it must be always on */
1070 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1071 state = true;
1072
b97186f0
PZ		 1073 if (!intel_display_power_enabled(dev_priv->dev,
1074 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1075 cur_state = false;
1076 } else {
1077 reg = PIPECONF(cpu_transcoder);
1078 val = I915_READ(reg);
1079 cur_state = !!(val & PIPECONF_ENABLE);
1080 }
1081
63d7bbe9
JB		 1082 WARN(cur_state != state,
1083 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1084 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1085}
1086
931872fc
CW		 1087static void assert_plane(struct drm_i915_private *dev_priv,
1088 enum plane plane, bool state)
b24e7179
JB		 1089{
1090 int reg;
1091 u32 val;
931872fc 1092 bool cur_state;
b24e7179
JB		 1093
1094 reg = DSPCNTR(plane);
1095 val = I915_READ(reg);
931872fc
CW		 1096 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1097 WARN(cur_state != state,
1098 "plane %c assertion failure (expected %s, current %s)\n",
1099 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1100}
1101
931872fc
CW		 1102#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1103#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1104
b24e7179
JB		 1105static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1106 enum pipe pipe)
1107{
1108 int reg, i;
1109 u32 val;
1110 int cur_pipe;
1111
19ec1358 1112 /* Planes are fixed to pipes on ILK+ */
da6ecc5d 1113 if (HAS_PCH_SPLIT(dev_priv->dev) || IS_VALLEYVIEW(dev_priv->dev)) {
28c05794
AJ		 1114 reg = DSPCNTR(pipe);
1115 val = I915_READ(reg);
1116 WARN((val & DISPLAY_PLANE_ENABLE),
1117 "plane %c assertion failure, should be disabled but not\n",
1118 plane_name(pipe));
19ec1358 1119 return;
28c05794 1120 }
19ec1358 1121
b24e7179
JB		 1122 /* Need to check both planes against the pipe */
1123 for (i = 0; i < 2; i++) {
1124 reg = DSPCNTR(i);
1125 val = I915_READ(reg);
1126 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1127 DISPPLANE_SEL_PIPE_SHIFT;
1128 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1129 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1130 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1131 }
1132}
1133
19332d7a
JB		 1134static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1135 enum pipe pipe)
1136{
1137 int reg, i;
1138 u32 val;
1139
1140 if (!IS_VALLEYVIEW(dev_priv->dev))
1141 return;
1142
1143 /* Need to check both planes against the pipe */
1144 for (i = 0; i < dev_priv->num_plane; i++) {
1145 reg = SPCNTR(pipe, i);
1146 val = I915_READ(reg);
1147 WARN((val & SP_ENABLE),
06da8da2
VS		 1148 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1149 sprite_name(pipe, i), pipe_name(pipe));
19332d7a
JB		 1150 }
1151}
1152
92f2584a
JB		 1153static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1154{
1155 u32 val;
1156 bool enabled;
1157
9d82aa17
ED		 1158 if (HAS_PCH_LPT(dev_priv->dev)) {
1159 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1160 return;
1161 }
1162
92f2584a
JB		 1163 val = I915_READ(PCH_DREF_CONTROL);
1164 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1165 DREF_SUPERSPREAD_SOURCE_MASK));
1166 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1167}
1168
ab9412ba
DV		 1169static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
92f2584a
JB		 1171{
1172 int reg;
1173 u32 val;
1174 bool enabled;
1175
ab9412ba 1176 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1177 val = I915_READ(reg);
1178 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1179 WARN(enabled,
1180 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1181 pipe_name(pipe));
92f2584a
JB		 1182}
1183
4e634389
KP		 1184static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1185 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1186{
1187 if ((val & DP_PORT_EN) == 0)
1188 return false;
1189
1190 if (HAS_PCH_CPT(dev_priv->dev)) {
1191 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1192 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1193 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1194 return false;
1195 } else {
1196 if ((val & DP_PIPE_MASK) != (pipe << 30))
1197 return false;
1198 }
1199 return true;
1200}
1201
1519b995
KP		 1202static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1203 enum pipe pipe, u32 val)
1204{
dc0fa718 1205 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1206 return false;
1207
1208 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1209 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1210 return false;
1211 } else {
dc0fa718 1212 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1213 return false;
1214 }
1215 return true;
1216}
1217
1218static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1219 enum pipe pipe, u32 val)
1220{
1221 if ((val & LVDS_PORT_EN) == 0)
1222 return false;
1223
1224 if (HAS_PCH_CPT(dev_priv->dev)) {
1225 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1226 return false;
1227 } else {
1228 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1229 return false;
1230 }
1231 return true;
1232}
1233
1234static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1235 enum pipe pipe, u32 val)
1236{
1237 if ((val & ADPA_DAC_ENABLE) == 0)
1238 return false;
1239 if (HAS_PCH_CPT(dev_priv->dev)) {
1240 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1241 return false;
1242 } else {
1243 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1244 return false;
1245 }
1246 return true;
1247}
1248
291906f1 1249static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1250 enum pipe pipe, int reg, u32 port_sel)
291906f1 1251{
47a05eca 1252 u32 val = I915_READ(reg);
4e634389 1253 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1254 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1255 reg, pipe_name(pipe));
de9a35ab 1256
75c5da27
DV		 1257 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1258 && (val & DP_PIPEB_SELECT),
de9a35ab 1259 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1260}
1261
1262static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1263 enum pipe pipe, int reg)
1264{
47a05eca 1265 u32 val = I915_READ(reg);
b70ad586 1266 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1267 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1268 reg, pipe_name(pipe));
de9a35ab 1269
dc0fa718 1270 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1271 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1272 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1273}
1274
1275static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1276 enum pipe pipe)
1277{
1278 int reg;
1279 u32 val;
291906f1 1280
f0575e92
KP		 1281 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1282 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1283 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1284
1285 reg = PCH_ADPA;
1286 val = I915_READ(reg);
b70ad586 1287 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1288 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1289 pipe_name(pipe));
291906f1
JB		 1290
1291 reg = PCH_LVDS;
1292 val = I915_READ(reg);
b70ad586 1293 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1294 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1295 pipe_name(pipe));
291906f1 1296
e2debe91
PZ		 1297 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1298 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1299 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1300}
1301
63d7bbe9
JB		 1302/**
1303 * intel_enable_pll - enable a PLL
1304 * @dev_priv: i915 private structure
1305 * @pipe: pipe PLL to enable
1306 *
1307 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1308 * make sure the PLL reg is writable first though, since the panel write
1309 * protect mechanism may be enabled.
1310 *
1311 * Note! This is for pre-ILK only.
7434a255
TR		 1312 *
1313 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1314 */
1315static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1316{
1317 int reg;
1318 u32 val;
1319
58c6eaa2
DV		 1320 assert_pipe_disabled(dev_priv, pipe);
1321
63d7bbe9 1322 /* No really, not for ILK+ */
a0c4da24 1323 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1324
1325 /* PLL is protected by panel, make sure we can write it */
1326 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1327 assert_panel_unlocked(dev_priv, pipe);
1328
1329 reg = DPLL(pipe);
1330 val = I915_READ(reg);
1331 val |= DPLL_VCO_ENABLE;
1332
1333 /* We do this three times for luck */
1334 I915_WRITE(reg, val);
1335 POSTING_READ(reg);
1336 udelay(150); /* wait for warmup */
1337 I915_WRITE(reg, val);
1338 POSTING_READ(reg);
1339 udelay(150); /* wait for warmup */
1340 I915_WRITE(reg, val);
1341 POSTING_READ(reg);
1342 udelay(150); /* wait for warmup */
1343}
1344
1345/**
1346 * intel_disable_pll - disable a PLL
1347 * @dev_priv: i915 private structure
1348 * @pipe: pipe PLL to disable
1349 *
1350 * Disable the PLL for @pipe, making sure the pipe is off first.
1351 *
1352 * Note! This is for pre-ILK only.
1353 */
1354static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1355{
1356 int reg;
1357 u32 val;
1358
1359 /* Don't disable pipe A or pipe A PLLs if needed */
1360 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1361 return;
1362
1363 /* Make sure the pipe isn't still relying on us */
1364 assert_pipe_disabled(dev_priv, pipe);
1365
1366 reg = DPLL(pipe);
1367 val = I915_READ(reg);
1368 val &= ~DPLL_VCO_ENABLE;
1369 I915_WRITE(reg, val);
1370 POSTING_READ(reg);
1371}
1372
89b667f8
JB		 1373void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1374{
1375 u32 port_mask;
1376
1377 if (!port)
1378 port_mask = DPLL_PORTB_READY_MASK;
1379 else
1380 port_mask = DPLL_PORTC_READY_MASK;
1381
1382 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1383 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1384 'B' + port, I915_READ(DPLL(0)));
1385}
1386
92f2584a 1387/**
b6b4e185 1388 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1389 * @dev_priv: i915 private structure
1390 * @pipe: pipe PLL to enable
1391 *
1392 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1393 * drives the transcoder clock.
1394 */
b6b4e185 1395static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1396{
ee7b9f93 1397 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1398 struct intel_pch_pll *pll;
92f2584a
JB		 1399 int reg;
1400 u32 val;
1401
48da64a8 1402 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1403 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1404 pll = intel_crtc->pch_pll;
1405 if (pll == NULL)
1406 return;
1407
1408 if (WARN_ON(pll->refcount == 0))
1409 return;
ee7b9f93
JB		 1410
1411 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1412 pll->pll_reg, pll->active, pll->on,
1413 intel_crtc->base.base.id);
92f2584a
JB		 1414
1415 /* PCH refclock must be enabled first */
1416 assert_pch_refclk_enabled(dev_priv);
1417
ee7b9f93 1418 if (pll->active++ && pll->on) {
92b27b08 1419 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1420 return;
1421 }
1422
1423 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1424
1425 reg = pll->pll_reg;
92f2584a
JB		 1426 val = I915_READ(reg);
1427 val |= DPLL_VCO_ENABLE;
1428 I915_WRITE(reg, val);
1429 POSTING_READ(reg);
1430 udelay(200);
ee7b9f93
JB		 1431
1432 pll->on = true;
92f2584a
JB		 1433}
1434
ee7b9f93 1435static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1436{
ee7b9f93
JB		 1437 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1438 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1439 int reg;
ee7b9f93 1440 u32 val;
4c609cb8 1441
92f2584a
JB		 1442 /* PCH only available on ILK+ */
1443 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1444 if (pll == NULL)
1445 return;
92f2584a 1446
48da64a8
CW		 1447 if (WARN_ON(pll->refcount == 0))
1448 return;
7a419866 1449
ee7b9f93
JB		 1450 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1451 pll->pll_reg, pll->active, pll->on,
1452 intel_crtc->base.base.id);
7a419866 1453
48da64a8 1454 if (WARN_ON(pll->active == 0)) {
92b27b08 1455 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1456 return;
1457 }
1458
ee7b9f93 1459 if (--pll->active) {
92b27b08 1460 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1461 return;
ee7b9f93
JB		 1462 }
1463
1464 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1465
1466 /* Make sure transcoder isn't still depending on us */
ab9412ba 1467 assert_pch_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1468
ee7b9f93 1469 reg = pll->pll_reg;
92f2584a
JB		 1470 val = I915_READ(reg);
1471 val &= ~DPLL_VCO_ENABLE;
1472 I915_WRITE(reg, val);
1473 POSTING_READ(reg);
1474 udelay(200);
ee7b9f93
JB		 1475
1476 pll->on = false;
92f2584a
JB		 1477}
1478
b8a4f404
PZ		 1479static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1480 enum pipe pipe)
040484af 1481{
23670b32 1482 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1483 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1484 uint32_t reg, val, pipeconf_val;
040484af
JB		 1485
1486 /* PCH only available on ILK+ */
1487 BUG_ON(dev_priv->info->gen < 5);
1488
1489 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1490 assert_pch_pll_enabled(dev_priv,
1491 to_intel_crtc(crtc)->pch_pll,
1492 to_intel_crtc(crtc));
040484af
JB		 1493
1494 /* FDI must be feeding us bits for PCH ports */
1495 assert_fdi_tx_enabled(dev_priv, pipe);
1496 assert_fdi_rx_enabled(dev_priv, pipe);
1497
23670b32
DV		 1498 if (HAS_PCH_CPT(dev)) {
1499 /* Workaround: Set the timing override bit before enabling the
1500 * pch transcoder. */
1501 reg = TRANS_CHICKEN2(pipe);
1502 val = I915_READ(reg);
1503 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1504 I915_WRITE(reg, val);
59c859d6 1505 }
23670b32 1506
ab9412ba 1507 reg = PCH_TRANSCONF(pipe);
040484af 1508 val = I915_READ(reg);
5f7f726d 1509 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1510
1511 if (HAS_PCH_IBX(dev_priv->dev)) {
1512 /*
1513 * make the BPC in transcoder be consistent with
1514 * that in pipeconf reg.
1515 */
dfd07d72
DV		 1516 val &= ~PIPECONF_BPC_MASK;
1517 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1518 }
5f7f726d
PZ		 1519
1520 val &= ~TRANS_INTERLACE_MASK;
1521 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1522 if (HAS_PCH_IBX(dev_priv->dev) &&
1523 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1524 val |= TRANS_LEGACY_INTERLACED_ILK;
1525 else
1526 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1527 else
1528 val |= TRANS_PROGRESSIVE;
1529
040484af
JB		 1530 I915_WRITE(reg, val | TRANS_ENABLE);
1531 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1532 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1533}
1534
8fb033d7 1535static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1536 enum transcoder cpu_transcoder)
040484af 1537{
8fb033d7 1538 u32 val, pipeconf_val;
8fb033d7
PZ		 1539
1540 /* PCH only available on ILK+ */
1541 BUG_ON(dev_priv->info->gen < 5);
1542
8fb033d7 1543 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1544 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1545 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1546
223a6fdf
PZ		 1547 /* Workaround: set timing override bit. */
1548 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1549 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1550 I915_WRITE(_TRANSA_CHICKEN2, val);
1551
25f3ef11 1552 val = TRANS_ENABLE;
937bb610 1553 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1554
9a76b1c6
PZ		 1555 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1556 PIPECONF_INTERLACED_ILK)
a35f2679 1557 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1558 else
1559 val |= TRANS_PROGRESSIVE;
1560
ab9412ba
DV		 1561 I915_WRITE(LPT_TRANSCONF, val);
1562 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1563 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1564}
1565
b8a4f404
PZ		 1566static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1567 enum pipe pipe)
040484af 1568{
23670b32
DV		 1569 struct drm_device *dev = dev_priv->dev;
1570 uint32_t reg, val;
040484af
JB		 1571
1572 /* FDI relies on the transcoder */
1573 assert_fdi_tx_disabled(dev_priv, pipe);
1574 assert_fdi_rx_disabled(dev_priv, pipe);
1575
291906f1
JB		 1576 /* Ports must be off as well */
1577 assert_pch_ports_disabled(dev_priv, pipe);
1578
ab9412ba 1579 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1580 val = I915_READ(reg);
1581 val &= ~TRANS_ENABLE;
1582 I915_WRITE(reg, val);
1583 /* wait for PCH transcoder off, transcoder state */
1584 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1585 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1586
1587 if (!HAS_PCH_IBX(dev)) {
1588 /* Workaround: Clear the timing override chicken bit again. */
1589 reg = TRANS_CHICKEN2(pipe);
1590 val = I915_READ(reg);
1591 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1592 I915_WRITE(reg, val);
1593 }
040484af
JB		 1594}
1595
ab4d966c 1596static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1597{
8fb033d7
PZ		 1598 u32 val;
1599
ab9412ba 1600 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1601 val &= ~TRANS_ENABLE;
ab9412ba 1602 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1603 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1604 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1605 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1606
1607 /* Workaround: clear timing override bit. */
1608 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1609 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1610 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1611}
1612
b24e7179 1613/**
309cfea8 1614 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1615 * @dev_priv: i915 private structure
1616 * @pipe: pipe to enable
040484af 1617 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1618 *
1619 * Enable @pipe, making sure that various hardware specific requirements
1620 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1621 *
1622 * @pipe should be %PIPE_A or %PIPE_B.
1623 *
1624 * Will wait until the pipe is actually running (i.e. first vblank) before
1625 * returning.
1626 */
040484af
JB		 1627static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1628 bool pch_port)
b24e7179 1629{
702e7a56
PZ		 1630 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1631 pipe);
1a240d4d 1632 enum pipe pch_transcoder;
b24e7179
JB		 1633 int reg;
1634 u32 val;
1635
58c6eaa2
DV		 1636 assert_planes_disabled(dev_priv, pipe);
1637 assert_sprites_disabled(dev_priv, pipe);
1638
681e5811 1639 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1640 pch_transcoder = TRANSCODER_A;
1641 else
1642 pch_transcoder = pipe;
1643
b24e7179
JB		 1644 /*
1645 * A pipe without a PLL won't actually be able to drive bits from
1646 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1647 * need the check.
1648 */
1649 if (!HAS_PCH_SPLIT(dev_priv->dev))
1650 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1651 else {
1652 if (pch_port) {
1653 /* if driving the PCH, we need FDI enabled */
cc391bbb 1654 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1655 assert_fdi_tx_pll_enabled(dev_priv,
1656 (enum pipe) cpu_transcoder);
040484af
JB		 1657 }
1658 /* FIXME: assert CPU port conditions for SNB+ */
1659 }
b24e7179 1660
702e7a56 1661 reg = PIPECONF(cpu_transcoder);
b24e7179 1662 val = I915_READ(reg);
00d70b15
CW		 1663 if (val & PIPECONF_ENABLE)
1664 return;
1665
1666 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1667 intel_wait_for_vblank(dev_priv->dev, pipe);
1668}
1669
1670/**
309cfea8 1671 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1672 * @dev_priv: i915 private structure
1673 * @pipe: pipe to disable
1674 *
1675 * Disable @pipe, making sure that various hardware specific requirements
1676 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1677 *
1678 * @pipe should be %PIPE_A or %PIPE_B.
1679 *
1680 * Will wait until the pipe has shut down before returning.
1681 */
1682static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1683 enum pipe pipe)
1684{
702e7a56
PZ		 1685 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1686 pipe);
b24e7179
JB		 1687 int reg;
1688 u32 val;
1689
1690 /*
1691 * Make sure planes won't keep trying to pump pixels to us,
1692 * or we might hang the display.
1693 */
1694 assert_planes_disabled(dev_priv, pipe);
19332d7a 1695 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1696
1697 /* Don't disable pipe A or pipe A PLLs if needed */
1698 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1699 return;
1700
702e7a56 1701 reg = PIPECONF(cpu_transcoder);
b24e7179 1702 val = I915_READ(reg);
00d70b15
CW		 1703 if ((val & PIPECONF_ENABLE) == 0)
1704 return;
1705
1706 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1707 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1708}
1709
d74362c9
KP		 1710/*
1711 * Plane regs are double buffered, going from enabled->disabled needs a
1712 * trigger in order to latch. The display address reg provides this.
1713 */
6f1d69b0 1714void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1715 enum plane plane)
1716{
14f86147
DL		 1717 if (dev_priv->info->gen >= 4)
1718 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1719 else
1720 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1721}
1722
b24e7179
JB		 1723/**
1724 * intel_enable_plane - enable a display plane on a given pipe
1725 * @dev_priv: i915 private structure
1726 * @plane: plane to enable
1727 * @pipe: pipe being fed
1728 *
1729 * Enable @plane on @pipe, making sure that @pipe is running first.
1730 */
1731static void intel_enable_plane(struct drm_i915_private *dev_priv,
1732 enum plane plane, enum pipe pipe)
1733{
1734 int reg;
1735 u32 val;
1736
1737 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1738 assert_pipe_enabled(dev_priv, pipe);
1739
1740 reg = DSPCNTR(plane);
1741 val = I915_READ(reg);
00d70b15
CW		 1742 if (val & DISPLAY_PLANE_ENABLE)
1743 return;
1744
1745 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1746 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1747 intel_wait_for_vblank(dev_priv->dev, pipe);
1748}
1749
b24e7179
JB		 1750/**
1751 * intel_disable_plane - disable a display plane
1752 * @dev_priv: i915 private structure
1753 * @plane: plane to disable
1754 * @pipe: pipe consuming the data
1755 *
1756 * Disable @plane; should be an independent operation.
1757 */
1758static void intel_disable_plane(struct drm_i915_private *dev_priv,
1759 enum plane plane, enum pipe pipe)
1760{
1761 int reg;
1762 u32 val;
1763
1764 reg = DSPCNTR(plane);
1765 val = I915_READ(reg);
00d70b15
CW		 1766 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1767 return;
1768
1769 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1770 intel_flush_display_plane(dev_priv, plane);
1771 intel_wait_for_vblank(dev_priv->dev, pipe);
1772}
1773
693db184
CW		 1774static bool need_vtd_wa(struct drm_device *dev)
1775{
1776#ifdef CONFIG_INTEL_IOMMU
1777 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1778 return true;
1779#endif
1780 return false;
1781}
1782
127bd2ac 1783int
48b956c5 1784intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1785 struct drm_i915_gem_object *obj,
919926ae 1786 struct intel_ring_buffer *pipelined)
6b95a207 1787{
ce453d81 1788 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1789 u32 alignment;
1790 int ret;
1791
05394f39 1792 switch (obj->tiling_mode) {
6b95a207 1793 case I915_TILING_NONE:
534843da
CW		 1794 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1795 alignment = 128 * 1024;
a6c45cf0 1796 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1797 alignment = 4 * 1024;
1798 else
1799 alignment = 64 * 1024;
6b95a207
KH		 1800 break;
1801 case I915_TILING_X:
1802 /* pin() will align the object as required by fence */
1803 alignment = 0;
1804 break;
1805 case I915_TILING_Y:
8bb6e959
DV		 1806 /* Despite that we check this in framebuffer_init userspace can
1807 * screw us over and change the tiling after the fact. Only
1808 * pinned buffers can't change their tiling. */
1809 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1810 return -EINVAL;
1811 default:
1812 BUG();
1813 }
1814
693db184
CW		 1815 /* Note that the w/a also requires 64 PTE of padding following the
1816 * bo. We currently fill all unused PTE with the shadow page and so
1817 * we should always have valid PTE following the scanout preventing
1818 * the VT-d warning.
1819 */
1820 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1821 alignment = 256 * 1024;
1822
ce453d81 1823 dev_priv->mm.interruptible = false;
2da3b9b9 1824 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1825 if (ret)
ce453d81 1826 goto err_interruptible;
6b95a207
KH		 1827
1828 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1829 * fence, whereas 965+ only requires a fence if using
1830 * framebuffer compression. For simplicity, we always install
1831 * a fence as the cost is not that onerous.
1832 */
06d98131 1833 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1834 if (ret)
1835 goto err_unpin;
1690e1eb 1836
9a5a53b3 1837 i915_gem_object_pin_fence(obj);
6b95a207 1838
ce453d81 1839 dev_priv->mm.interruptible = true;
6b95a207 1840 return 0;
48b956c5
CW		 1841
1842err_unpin:
1843 i915_gem_object_unpin(obj);
ce453d81
CW		 1844err_interruptible:
1845 dev_priv->mm.interruptible = true;
48b956c5 1846 return ret;
6b95a207
KH		 1847}
1848
1690e1eb
CW		 1849void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1850{
1851 i915_gem_object_unpin_fence(obj);
1852 i915_gem_object_unpin(obj);
1853}
1854
c2c75131
DV		 1855/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1856 * is assumed to be a power-of-two. */
bc752862
CW		 1857unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1858 unsigned int tiling_mode,
1859 unsigned int cpp,
1860 unsigned int pitch)
c2c75131 1861{
bc752862
CW		 1862 if (tiling_mode != I915_TILING_NONE) {
1863 unsigned int tile_rows, tiles;
c2c75131 1864
bc752862
CW		 1865 tile_rows = *y / 8;
1866 *y %= 8;
c2c75131 1867
bc752862
CW		 1868 tiles = *x / (512/cpp);
1869 *x %= 512/cpp;
1870
1871 return tile_rows * pitch * 8 + tiles * 4096;
1872 } else {
1873 unsigned int offset;
1874
1875 offset = *y * pitch + *x * cpp;
1876 *y = 0;
1877 *x = (offset & 4095) / cpp;
1878 return offset & -4096;
1879 }
c2c75131
DV		 1880}
1881
17638cd6
JB		 1882static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1883 int x, int y)
81255565
JB		 1884{
1885 struct drm_device *dev = crtc->dev;
1886 struct drm_i915_private *dev_priv = dev->dev_private;
1887 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1888 struct intel_framebuffer *intel_fb;
05394f39 1889 struct drm_i915_gem_object *obj;
81255565 1890 int plane = intel_crtc->plane;
e506a0c6 1891 unsigned long linear_offset;
81255565 1892 u32 dspcntr;
5eddb70b 1893 u32 reg;
81255565
JB		 1894
1895 switch (plane) {
1896 case 0:
1897 case 1:
1898 break;
1899 default:
84f44ce7 1900 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 1901 return -EINVAL;
1902 }
1903
1904 intel_fb = to_intel_framebuffer(fb);
1905 obj = intel_fb->obj;
81255565 1906
5eddb70b
CW		 1907 reg = DSPCNTR(plane);
1908 dspcntr = I915_READ(reg);
81255565
JB		 1909 /* Mask out pixel format bits in case we change it */
1910 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 1911 switch (fb->pixel_format) {
1912 case DRM_FORMAT_C8:
81255565
JB		 1913 dspcntr |= DISPPLANE_8BPP;
1914 break;
57779d06
VS		 1915 case DRM_FORMAT_XRGB1555:
1916 case DRM_FORMAT_ARGB1555:
1917 dspcntr |= DISPPLANE_BGRX555;
81255565 1918 break;
57779d06
VS		 1919 case DRM_FORMAT_RGB565:
1920 dspcntr |= DISPPLANE_BGRX565;
1921 break;
1922 case DRM_FORMAT_XRGB8888:
1923 case DRM_FORMAT_ARGB8888:
1924 dspcntr |= DISPPLANE_BGRX888;
1925 break;
1926 case DRM_FORMAT_XBGR8888:
1927 case DRM_FORMAT_ABGR8888:
1928 dspcntr |= DISPPLANE_RGBX888;
1929 break;
1930 case DRM_FORMAT_XRGB2101010:
1931 case DRM_FORMAT_ARGB2101010:
1932 dspcntr |= DISPPLANE_BGRX101010;
1933 break;
1934 case DRM_FORMAT_XBGR2101010:
1935 case DRM_FORMAT_ABGR2101010:
1936 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 1937 break;
1938 default:
baba133a 1939 BUG();
81255565 1940 }
57779d06 1941
a6c45cf0 1942 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 1943 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 1944 dspcntr |= DISPPLANE_TILED;
1945 else
1946 dspcntr &= ~DISPPLANE_TILED;
1947 }
1948
5eddb70b 1949 I915_WRITE(reg, dspcntr);
81255565 1950
e506a0c6 1951 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 1952
c2c75131
DV		 1953 if (INTEL_INFO(dev)->gen >= 4) {
1954 intel_crtc->dspaddr_offset =
bc752862
CW		 1955 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
1956 fb->bits_per_pixel / 8,
1957 fb->pitches[0]);
c2c75131
DV		 1958 linear_offset -= intel_crtc->dspaddr_offset;
1959 } else {
e506a0c6 1960 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 1961 }
e506a0c6
DV		 1962
1963 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
1964 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 1965 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 1966 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 1967 I915_MODIFY_DISPBASE(DSPSURF(plane),
1968 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 1969 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 1970 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 1971 } else
e506a0c6 1972 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 1973 POSTING_READ(reg);
81255565 1974
17638cd6
JB		 1975 return 0;
1976}
1977
1978static int ironlake_update_plane(struct drm_crtc *crtc,
1979 struct drm_framebuffer *fb, int x, int y)
1980{
1981 struct drm_device *dev = crtc->dev;
1982 struct drm_i915_private *dev_priv = dev->dev_private;
1983 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1984 struct intel_framebuffer *intel_fb;
1985 struct drm_i915_gem_object *obj;
1986 int plane = intel_crtc->plane;
e506a0c6 1987 unsigned long linear_offset;
17638cd6
JB		 1988 u32 dspcntr;
1989 u32 reg;
1990
1991 switch (plane) {
1992 case 0:
1993 case 1:
27f8227b 1994 case 2:
17638cd6
JB		 1995 break;
1996 default:
84f44ce7 1997 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 1998 return -EINVAL;
1999 }
2000
2001 intel_fb = to_intel_framebuffer(fb);
2002 obj = intel_fb->obj;
2003
2004 reg = DSPCNTR(plane);
2005 dspcntr = I915_READ(reg);
2006 /* Mask out pixel format bits in case we change it */
2007 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2008 switch (fb->pixel_format) {
2009 case DRM_FORMAT_C8:
17638cd6
JB		 2010 dspcntr |= DISPPLANE_8BPP;
2011 break;
57779d06
VS		 2012 case DRM_FORMAT_RGB565:
2013 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2014 break;
57779d06
VS		 2015 case DRM_FORMAT_XRGB8888:
2016 case DRM_FORMAT_ARGB8888:
2017 dspcntr |= DISPPLANE_BGRX888;
2018 break;
2019 case DRM_FORMAT_XBGR8888:
2020 case DRM_FORMAT_ABGR8888:
2021 dspcntr |= DISPPLANE_RGBX888;
2022 break;
2023 case DRM_FORMAT_XRGB2101010:
2024 case DRM_FORMAT_ARGB2101010:
2025 dspcntr |= DISPPLANE_BGRX101010;
2026 break;
2027 case DRM_FORMAT_XBGR2101010:
2028 case DRM_FORMAT_ABGR2101010:
2029 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2030 break;
2031 default:
baba133a 2032 BUG();
17638cd6
JB		 2033 }
2034
2035 if (obj->tiling_mode != I915_TILING_NONE)
2036 dspcntr |= DISPPLANE_TILED;
2037 else
2038 dspcntr &= ~DISPPLANE_TILED;
2039
2040 /* must disable */
2041 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2042
2043 I915_WRITE(reg, dspcntr);
2044
e506a0c6 2045 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2046 intel_crtc->dspaddr_offset =
bc752862
CW		 2047 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2048 fb->bits_per_pixel / 8,
2049 fb->pitches[0]);
c2c75131 2050 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2051
e506a0c6
DV		 2052 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2053 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2054 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2055 I915_MODIFY_DISPBASE(DSPSURF(plane),
2056 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2057 if (IS_HASWELL(dev)) {
2058 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2059 } else {
2060 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2061 I915_WRITE(DSPLINOFF(plane), linear_offset);
2062 }
17638cd6
JB		 2063 POSTING_READ(reg);
2064
2065 return 0;
2066}
2067
2068/* Assume fb object is pinned & idle & fenced and just update base pointers */
2069static int
2070intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2071 int x, int y, enum mode_set_atomic state)
2072{
2073 struct drm_device *dev = crtc->dev;
2074 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2075
6b8e6ed0
CW		 2076 if (dev_priv->display.disable_fbc)
2077 dev_priv->display.disable_fbc(dev);
3dec0095 2078 intel_increase_pllclock(crtc);
81255565 2079
6b8e6ed0 2080 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2081}
2082
96a02917
VS		 2083void intel_display_handle_reset(struct drm_device *dev)
2084{
2085 struct drm_i915_private *dev_priv = dev->dev_private;
2086 struct drm_crtc *crtc;
2087
2088 /*
2089 * Flips in the rings have been nuked by the reset,
2090 * so complete all pending flips so that user space
2091 * will get its events and not get stuck.
2092 *
2093 * Also update the base address of all primary
2094 * planes to the the last fb to make sure we're
2095 * showing the correct fb after a reset.
2096 *
2097 * Need to make two loops over the crtcs so that we
2098 * don't try to grab a crtc mutex before the
2099 * pending_flip_queue really got woken up.
2100 */
2101
2102 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2103 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2104 enum plane plane = intel_crtc->plane;
2105
2106 intel_prepare_page_flip(dev, plane);
2107 intel_finish_page_flip_plane(dev, plane);
2108 }
2109
2110 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2112
2113 mutex_lock(&crtc->mutex);
2114 if (intel_crtc->active)
2115 dev_priv->display.update_plane(crtc, crtc->fb,
2116 crtc->x, crtc->y);
2117 mutex_unlock(&crtc->mutex);
2118 }
2119}
2120
14667a4b
CW		 2121static int
2122intel_finish_fb(struct drm_framebuffer *old_fb)
2123{
2124 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2125 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2126 bool was_interruptible = dev_priv->mm.interruptible;
2127 int ret;
2128
14667a4b
CW		 2129 /* Big Hammer, we also need to ensure that any pending
2130 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2131 * current scanout is retired before unpinning the old
2132 * framebuffer.
2133 *
2134 * This should only fail upon a hung GPU, in which case we
2135 * can safely continue.
2136 */
2137 dev_priv->mm.interruptible = false;
2138 ret = i915_gem_object_finish_gpu(obj);
2139 dev_priv->mm.interruptible = was_interruptible;
2140
2141 return ret;
2142}
2143
198598d0
VS		 2144static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2145{
2146 struct drm_device *dev = crtc->dev;
2147 struct drm_i915_master_private *master_priv;
2148 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2149
2150 if (!dev->primary->master)
2151 return;
2152
2153 master_priv = dev->primary->master->driver_priv;
2154 if (!master_priv->sarea_priv)
2155 return;
2156
2157 switch (intel_crtc->pipe) {
2158 case 0:
2159 master_priv->sarea_priv->pipeA_x = x;
2160 master_priv->sarea_priv->pipeA_y = y;
2161 break;
2162 case 1:
2163 master_priv->sarea_priv->pipeB_x = x;
2164 master_priv->sarea_priv->pipeB_y = y;
2165 break;
2166 default:
2167 break;
2168 }
2169}
2170
5c3b82e2 2171static int
3c4fdcfb 2172intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2173 struct drm_framebuffer *fb)
79e53945
JB		 2174{
2175 struct drm_device *dev = crtc->dev;
6b8e6ed0 2176 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2177 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2178 struct drm_framebuffer *old_fb;
5c3b82e2 2179 int ret;
79e53945
JB		 2180
2181 /* no fb bound */
94352cf9 2182 if (!fb) {
a5071c2f 2183 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2184 return 0;
2185 }
2186
7eb552ae 2187 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2188 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2189 plane_name(intel_crtc->plane),
2190 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2191 return -EINVAL;
79e53945
JB		 2192 }
2193
5c3b82e2 2194 mutex_lock(&dev->struct_mutex);
265db958 2195 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2196 to_intel_framebuffer(fb)->obj,
919926ae 2197 NULL);
5c3b82e2
CW		 2198 if (ret != 0) {
2199 mutex_unlock(&dev->struct_mutex);
a5071c2f 2200 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2201 return ret;
2202 }
79e53945 2203
94352cf9 2204 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2205 if (ret) {
94352cf9 2206 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2207 mutex_unlock(&dev->struct_mutex);
a5071c2f 2208 DRM_ERROR("failed to update base address\n");
4e6cfefc 2209 return ret;
79e53945 2210 }
3c4fdcfb 2211
94352cf9
DV		 2212 old_fb = crtc->fb;
2213 crtc->fb = fb;
6c4c86f5
DV		 2214 crtc->x = x;
2215 crtc->y = y;
94352cf9 2216
b7f1de28 2217 if (old_fb) {
d7697eea
DV		 2218 if (intel_crtc->active && old_fb != fb)
2219 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2220 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2221 }
652c393a 2222
6b8e6ed0 2223 intel_update_fbc(dev);
5c3b82e2 2224 mutex_unlock(&dev->struct_mutex);
79e53945 2225
198598d0 2226 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2227
2228 return 0;
79e53945
JB		 2229}
2230
5e84e1a4
ZW		 2231static void intel_fdi_normal_train(struct drm_crtc *crtc)
2232{
2233 struct drm_device *dev = crtc->dev;
2234 struct drm_i915_private *dev_priv = dev->dev_private;
2235 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2236 int pipe = intel_crtc->pipe;
2237 u32 reg, temp;
2238
2239 /* enable normal train */
2240 reg = FDI_TX_CTL(pipe);
2241 temp = I915_READ(reg);
61e499bf 2242 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2243 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2244 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2245 } else {
2246 temp &= ~FDI_LINK_TRAIN_NONE;
2247 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2248 }
5e84e1a4
ZW		 2249 I915_WRITE(reg, temp);
2250
2251 reg = FDI_RX_CTL(pipe);
2252 temp = I915_READ(reg);
2253 if (HAS_PCH_CPT(dev)) {
2254 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2255 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2256 } else {
2257 temp &= ~FDI_LINK_TRAIN_NONE;
2258 temp |= FDI_LINK_TRAIN_NONE;
2259 }
2260 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2261
2262 /* wait one idle pattern time */
2263 POSTING_READ(reg);
2264 udelay(1000);
357555c0
JB		 2265
2266 /* IVB wants error correction enabled */
2267 if (IS_IVYBRIDGE(dev))
2268 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2269 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2270}
2271
1e833f40
DV		 2272static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2273{
2274 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2275}
2276
01a415fd
DV		 2277static void ivb_modeset_global_resources(struct drm_device *dev)
2278{
2279 struct drm_i915_private *dev_priv = dev->dev_private;
2280 struct intel_crtc *pipe_B_crtc =
2281 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2282 struct intel_crtc *pipe_C_crtc =
2283 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2284 uint32_t temp;
2285
1e833f40
DV		 2286 /*
2287 * When everything is off disable fdi C so that we could enable fdi B
2288 * with all lanes. Note that we don't care about enabled pipes without
2289 * an enabled pch encoder.
2290 */
2291 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2292 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2293 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2294 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2295
2296 temp = I915_READ(SOUTH_CHICKEN1);
2297 temp &= ~FDI_BC_BIFURCATION_SELECT;
2298 DRM_DEBUG_KMS("disabling fdi C rx\n");
2299 I915_WRITE(SOUTH_CHICKEN1, temp);
2300 }
2301}
2302
8db9d77b
ZW		 2303/* The FDI link training functions for ILK/Ibexpeak. */
2304static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2305{
2306 struct drm_device *dev = crtc->dev;
2307 struct drm_i915_private *dev_priv = dev->dev_private;
2308 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2309 int pipe = intel_crtc->pipe;
0fc932b8 2310 int plane = intel_crtc->plane;
5eddb70b 2311 u32 reg, temp, tries;
8db9d77b 2312
0fc932b8
JB		 2313 /* FDI needs bits from pipe & plane first */
2314 assert_pipe_enabled(dev_priv, pipe);
2315 assert_plane_enabled(dev_priv, plane);
2316
e1a44743
AJ		 2317 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2318 for train result */
5eddb70b
CW		 2319 reg = FDI_RX_IMR(pipe);
2320 temp = I915_READ(reg);
e1a44743
AJ		 2321 temp &= ~FDI_RX_SYMBOL_LOCK;
2322 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2323 I915_WRITE(reg, temp);
2324 I915_READ(reg);
e1a44743
AJ		 2325 udelay(150);
2326
8db9d77b 2327 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2328 reg = FDI_TX_CTL(pipe);
2329 temp = I915_READ(reg);
627eb5a3
DV		 2330 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2331 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2332 temp &= ~FDI_LINK_TRAIN_NONE;
2333 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2334 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2335
5eddb70b
CW		 2336 reg = FDI_RX_CTL(pipe);
2337 temp = I915_READ(reg);
8db9d77b
ZW		 2338 temp &= ~FDI_LINK_TRAIN_NONE;
2339 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2340 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2341
2342 POSTING_READ(reg);
8db9d77b
ZW		 2343 udelay(150);
2344
5b2adf89 2345 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2346 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2347 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2348 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2349
5eddb70b 2350 reg = FDI_RX_IIR(pipe);
e1a44743 2351 for (tries = 0; tries < 5; tries++) {
5eddb70b 2352 temp = I915_READ(reg);
8db9d77b
ZW		 2353 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2354
2355 if ((temp & FDI_RX_BIT_LOCK)) {
2356 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2357 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2358 break;
2359 }
8db9d77b 2360 }
e1a44743 2361 if (tries == 5)
5eddb70b 2362 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2363
2364 /* Train 2 */
5eddb70b
CW		 2365 reg = FDI_TX_CTL(pipe);
2366 temp = I915_READ(reg);
8db9d77b
ZW		 2367 temp &= ~FDI_LINK_TRAIN_NONE;
2368 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2369 I915_WRITE(reg, temp);
8db9d77b 2370
5eddb70b
CW		 2371 reg = FDI_RX_CTL(pipe);
2372 temp = I915_READ(reg);
8db9d77b
ZW		 2373 temp &= ~FDI_LINK_TRAIN_NONE;
2374 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2375 I915_WRITE(reg, temp);
8db9d77b 2376
5eddb70b
CW		 2377 POSTING_READ(reg);
2378 udelay(150);
8db9d77b 2379
5eddb70b 2380 reg = FDI_RX_IIR(pipe);
e1a44743 2381 for (tries = 0; tries < 5; tries++) {
5eddb70b 2382 temp = I915_READ(reg);
8db9d77b
ZW		 2383 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2384
2385 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2386 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2387 DRM_DEBUG_KMS("FDI train 2 done.\n");
2388 break;
2389 }
8db9d77b 2390 }
e1a44743 2391 if (tries == 5)
5eddb70b 2392 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2393
2394 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2395
8db9d77b
ZW		 2396}
2397
0206e353 2398static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2399 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2400 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2401 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2402 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2403};
2404
2405/* The FDI link training functions for SNB/Cougarpoint. */
2406static void gen6_fdi_link_train(struct drm_crtc *crtc)
2407{
2408 struct drm_device *dev = crtc->dev;
2409 struct drm_i915_private *dev_priv = dev->dev_private;
2410 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2411 int pipe = intel_crtc->pipe;
fa37d39e 2412 u32 reg, temp, i, retry;
8db9d77b 2413
e1a44743
AJ		 2414 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2415 for train result */
5eddb70b
CW		 2416 reg = FDI_RX_IMR(pipe);
2417 temp = I915_READ(reg);
e1a44743
AJ		 2418 temp &= ~FDI_RX_SYMBOL_LOCK;
2419 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2420 I915_WRITE(reg, temp);
2421
2422 POSTING_READ(reg);
e1a44743
AJ		 2423 udelay(150);
2424
8db9d77b 2425 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2426 reg = FDI_TX_CTL(pipe);
2427 temp = I915_READ(reg);
627eb5a3
DV		 2428 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2429 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2430 temp &= ~FDI_LINK_TRAIN_NONE;
2431 temp |= FDI_LINK_TRAIN_PATTERN_1;
2432 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2433 /* SNB-B */
2434 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2435 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2436
d74cf324
DV		 2437 I915_WRITE(FDI_RX_MISC(pipe),
2438 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2439
5eddb70b
CW		 2440 reg = FDI_RX_CTL(pipe);
2441 temp = I915_READ(reg);
8db9d77b
ZW		 2442 if (HAS_PCH_CPT(dev)) {
2443 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2444 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2445 } else {
2446 temp &= ~FDI_LINK_TRAIN_NONE;
2447 temp |= FDI_LINK_TRAIN_PATTERN_1;
2448 }
5eddb70b
CW		 2449 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2450
2451 POSTING_READ(reg);
8db9d77b
ZW		 2452 udelay(150);
2453
0206e353 2454 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2455 reg = FDI_TX_CTL(pipe);
2456 temp = I915_READ(reg);
8db9d77b
ZW		 2457 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2458 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2459 I915_WRITE(reg, temp);
2460
2461 POSTING_READ(reg);
8db9d77b
ZW		 2462 udelay(500);
2463
fa37d39e
SP		 2464 for (retry = 0; retry < 5; retry++) {
2465 reg = FDI_RX_IIR(pipe);
2466 temp = I915_READ(reg);
2467 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2468 if (temp & FDI_RX_BIT_LOCK) {
2469 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2470 DRM_DEBUG_KMS("FDI train 1 done.\n");
2471 break;
2472 }
2473 udelay(50);
8db9d77b 2474 }
fa37d39e
SP		 2475 if (retry < 5)
2476 break;
8db9d77b
ZW		 2477 }
2478 if (i == 4)
5eddb70b 2479 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2480
2481 /* Train 2 */
5eddb70b
CW		 2482 reg = FDI_TX_CTL(pipe);
2483 temp = I915_READ(reg);
8db9d77b
ZW		 2484 temp &= ~FDI_LINK_TRAIN_NONE;
2485 temp |= FDI_LINK_TRAIN_PATTERN_2;
2486 if (IS_GEN6(dev)) {
2487 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2488 /* SNB-B */
2489 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2490 }
5eddb70b 2491 I915_WRITE(reg, temp);
8db9d77b 2492
5eddb70b
CW		 2493 reg = FDI_RX_CTL(pipe);
2494 temp = I915_READ(reg);
8db9d77b
ZW		 2495 if (HAS_PCH_CPT(dev)) {
2496 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2497 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2498 } else {
2499 temp &= ~FDI_LINK_TRAIN_NONE;
2500 temp |= FDI_LINK_TRAIN_PATTERN_2;
2501 }
5eddb70b
CW		 2502 I915_WRITE(reg, temp);
2503
2504 POSTING_READ(reg);
8db9d77b
ZW		 2505 udelay(150);
2506
0206e353 2507 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2508 reg = FDI_TX_CTL(pipe);
2509 temp = I915_READ(reg);
8db9d77b
ZW		 2510 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2511 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2512 I915_WRITE(reg, temp);
2513
2514 POSTING_READ(reg);
8db9d77b
ZW		 2515 udelay(500);
2516
fa37d39e
SP		 2517 for (retry = 0; retry < 5; retry++) {
2518 reg = FDI_RX_IIR(pipe);
2519 temp = I915_READ(reg);
2520 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2521 if (temp & FDI_RX_SYMBOL_LOCK) {
2522 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2523 DRM_DEBUG_KMS("FDI train 2 done.\n");
2524 break;
2525 }
2526 udelay(50);
8db9d77b 2527 }
fa37d39e
SP		 2528 if (retry < 5)
2529 break;
8db9d77b
ZW		 2530 }
2531 if (i == 4)
5eddb70b 2532 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2533
2534 DRM_DEBUG_KMS("FDI train done.\n");
2535}
2536
357555c0
JB		 2537/* Manual link training for Ivy Bridge A0 parts */
2538static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2539{
2540 struct drm_device *dev = crtc->dev;
2541 struct drm_i915_private *dev_priv = dev->dev_private;
2542 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2543 int pipe = intel_crtc->pipe;
2544 u32 reg, temp, i;
2545
2546 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2547 for train result */
2548 reg = FDI_RX_IMR(pipe);
2549 temp = I915_READ(reg);
2550 temp &= ~FDI_RX_SYMBOL_LOCK;
2551 temp &= ~FDI_RX_BIT_LOCK;
2552 I915_WRITE(reg, temp);
2553
2554 POSTING_READ(reg);
2555 udelay(150);
2556
01a415fd
DV		 2557 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2558 I915_READ(FDI_RX_IIR(pipe)));
2559
357555c0
JB		 2560 /* enable CPU FDI TX and PCH FDI RX */
2561 reg = FDI_TX_CTL(pipe);
2562 temp = I915_READ(reg);
627eb5a3
DV		 2563 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2564 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
357555c0
JB		 2565 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2566 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2567 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2568 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2569 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2570 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2571
d74cf324
DV		 2572 I915_WRITE(FDI_RX_MISC(pipe),
2573 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2574
357555c0
JB		 2575 reg = FDI_RX_CTL(pipe);
2576 temp = I915_READ(reg);
2577 temp &= ~FDI_LINK_TRAIN_AUTO;
2578 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2579 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2580 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2581 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2582
2583 POSTING_READ(reg);
2584 udelay(150);
2585
0206e353 2586 for (i = 0; i < 4; i++) {
357555c0
JB		 2587 reg = FDI_TX_CTL(pipe);
2588 temp = I915_READ(reg);
2589 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2590 temp |= snb_b_fdi_train_param[i];
2591 I915_WRITE(reg, temp);
2592
2593 POSTING_READ(reg);
2594 udelay(500);
2595
2596 reg = FDI_RX_IIR(pipe);
2597 temp = I915_READ(reg);
2598 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2599
2600 if (temp & FDI_RX_BIT_LOCK ||
2601 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2602 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2603 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2604 break;
2605 }
2606 }
2607 if (i == 4)
2608 DRM_ERROR("FDI train 1 fail!\n");
2609
2610 /* Train 2 */
2611 reg = FDI_TX_CTL(pipe);
2612 temp = I915_READ(reg);
2613 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2614 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2615 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2616 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2617 I915_WRITE(reg, temp);
2618
2619 reg = FDI_RX_CTL(pipe);
2620 temp = I915_READ(reg);
2621 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2622 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2623 I915_WRITE(reg, temp);
2624
2625 POSTING_READ(reg);
2626 udelay(150);
2627
0206e353 2628 for (i = 0; i < 4; i++) {
357555c0
JB		 2629 reg = FDI_TX_CTL(pipe);
2630 temp = I915_READ(reg);
2631 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2632 temp |= snb_b_fdi_train_param[i];
2633 I915_WRITE(reg, temp);
2634
2635 POSTING_READ(reg);
2636 udelay(500);
2637
2638 reg = FDI_RX_IIR(pipe);
2639 temp = I915_READ(reg);
2640 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2641
2642 if (temp & FDI_RX_SYMBOL_LOCK) {
2643 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2644 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2645 break;
2646 }
2647 }
2648 if (i == 4)
2649 DRM_ERROR("FDI train 2 fail!\n");
2650
2651 DRM_DEBUG_KMS("FDI train done.\n");
2652}
2653
88cefb6c 2654static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2655{
88cefb6c 2656 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2657 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2658 int pipe = intel_crtc->pipe;
5eddb70b 2659 u32 reg, temp;
79e53945 2660
c64e311e 2661
c98e9dcf 2662 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2663 reg = FDI_RX_CTL(pipe);
2664 temp = I915_READ(reg);
627eb5a3
DV		 2665 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2666 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2667 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2668 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2669
2670 POSTING_READ(reg);
c98e9dcf
JB		 2671 udelay(200);
2672
2673 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2674 temp = I915_READ(reg);
2675 I915_WRITE(reg, temp | FDI_PCDCLK);
2676
2677 POSTING_READ(reg);
c98e9dcf
JB		 2678 udelay(200);
2679
20749730
PZ		 2680 /* Enable CPU FDI TX PLL, always on for Ironlake */
2681 reg = FDI_TX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2684 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2685
20749730
PZ		 2686 POSTING_READ(reg);
2687 udelay(100);
6be4a607 2688 }
0e23b99d
JB		 2689}
2690
88cefb6c
DV		 2691static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2692{
2693 struct drm_device *dev = intel_crtc->base.dev;
2694 struct drm_i915_private *dev_priv = dev->dev_private;
2695 int pipe = intel_crtc->pipe;
2696 u32 reg, temp;
2697
2698 /* Switch from PCDclk to Rawclk */
2699 reg = FDI_RX_CTL(pipe);
2700 temp = I915_READ(reg);
2701 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2702
2703 /* Disable CPU FDI TX PLL */
2704 reg = FDI_TX_CTL(pipe);
2705 temp = I915_READ(reg);
2706 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2707
2708 POSTING_READ(reg);
2709 udelay(100);
2710
2711 reg = FDI_RX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2714
2715 /* Wait for the clocks to turn off. */
2716 POSTING_READ(reg);
2717 udelay(100);
2718}
2719
0fc932b8
JB		 2720static void ironlake_fdi_disable(struct drm_crtc *crtc)
2721{
2722 struct drm_device *dev = crtc->dev;
2723 struct drm_i915_private *dev_priv = dev->dev_private;
2724 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2725 int pipe = intel_crtc->pipe;
2726 u32 reg, temp;
2727
2728 /* disable CPU FDI tx and PCH FDI rx */
2729 reg = FDI_TX_CTL(pipe);
2730 temp = I915_READ(reg);
2731 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2732 POSTING_READ(reg);
2733
2734 reg = FDI_RX_CTL(pipe);
2735 temp = I915_READ(reg);
2736 temp &= ~(0x7 << 16);
dfd07d72 2737 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2738 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2739
2740 POSTING_READ(reg);
2741 udelay(100);
2742
2743 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2744 if (HAS_PCH_IBX(dev)) {
2745 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2746 }
0fc932b8
JB		 2747
2748 /* still set train pattern 1 */
2749 reg = FDI_TX_CTL(pipe);
2750 temp = I915_READ(reg);
2751 temp &= ~FDI_LINK_TRAIN_NONE;
2752 temp |= FDI_LINK_TRAIN_PATTERN_1;
2753 I915_WRITE(reg, temp);
2754
2755 reg = FDI_RX_CTL(pipe);
2756 temp = I915_READ(reg);
2757 if (HAS_PCH_CPT(dev)) {
2758 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2759 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2760 } else {
2761 temp &= ~FDI_LINK_TRAIN_NONE;
2762 temp |= FDI_LINK_TRAIN_PATTERN_1;
2763 }
2764 /* BPC in FDI rx is consistent with that in PIPECONF */
2765 temp &= ~(0x07 << 16);
dfd07d72 2766 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2767 I915_WRITE(reg, temp);
2768
2769 POSTING_READ(reg);
2770 udelay(100);
2771}
2772
5bb61643
CW		 2773static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2774{
2775 struct drm_device *dev = crtc->dev;
2776 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2778 unsigned long flags;
2779 bool pending;
2780
10d83730
VS		 2781 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2782 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2783 return false;
2784
2785 spin_lock_irqsave(&dev->event_lock, flags);
2786 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2787 spin_unlock_irqrestore(&dev->event_lock, flags);
2788
2789 return pending;
2790}
2791
e6c3a2a6
CW		 2792static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2793{
0f91128d 2794 struct drm_device *dev = crtc->dev;
5bb61643 2795 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2796
2797 if (crtc->fb == NULL)
2798 return;
2799
2c10d571
DV		 2800 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2801
5bb61643
CW		 2802 wait_event(dev_priv->pending_flip_queue,
2803 !intel_crtc_has_pending_flip(crtc));
2804
0f91128d
CW		 2805 mutex_lock(&dev->struct_mutex);
2806 intel_finish_fb(crtc->fb);
2807 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2808}
2809
e615efe4
ED		 2810/* Program iCLKIP clock to the desired frequency */
2811static void lpt_program_iclkip(struct drm_crtc *crtc)
2812{
2813 struct drm_device *dev = crtc->dev;
2814 struct drm_i915_private *dev_priv = dev->dev_private;
2815 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2816 u32 temp;
2817
09153000
DV		 2818 mutex_lock(&dev_priv->dpio_lock);
2819
e615efe4
ED		 2820 /* It is necessary to ungate the pixclk gate prior to programming
2821 * the divisors, and gate it back when it is done.
2822 */
2823 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2824
2825 /* Disable SSCCTL */
2826 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2827 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2828 SBI_SSCCTL_DISABLE,
2829 SBI_ICLK);
e615efe4
ED		 2830
2831 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2832 if (crtc->mode.clock == 20000) {
2833 auxdiv = 1;
2834 divsel = 0x41;
2835 phaseinc = 0x20;
2836 } else {
2837 /* The iCLK virtual clock root frequency is in MHz,
2838 * but the crtc->mode.clock in in KHz. To get the divisors,
2839 * it is necessary to divide one by another, so we
2840 * convert the virtual clock precision to KHz here for higher
2841 * precision.
2842 */
2843 u32 iclk_virtual_root_freq = 172800 * 1000;
2844 u32 iclk_pi_range = 64;
2845 u32 desired_divisor, msb_divisor_value, pi_value;
2846
2847 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2848 msb_divisor_value = desired_divisor / iclk_pi_range;
2849 pi_value = desired_divisor % iclk_pi_range;
2850
2851 auxdiv = 0;
2852 divsel = msb_divisor_value - 2;
2853 phaseinc = pi_value;
2854 }
2855
2856 /* This should not happen with any sane values */
2857 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2858 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2859 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2860 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2861
2862 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2863 crtc->mode.clock,
2864 auxdiv,
2865 divsel,
2866 phasedir,
2867 phaseinc);
2868
2869 /* Program SSCDIVINTPHASE6 */
988d6ee8 2870 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2871 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2872 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2873 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2874 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2875 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2876 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 2877 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 2878
2879 /* Program SSCAUXDIV */
988d6ee8 2880 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 2881 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2882 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 2883 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 2884
2885 /* Enable modulator and associated divider */
988d6ee8 2886 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 2887 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 2888 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 2889
2890 /* Wait for initialization time */
2891 udelay(24);
2892
2893 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 2894
2895 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 2896}
2897
275f01b2
DV		 2898static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
2899 enum pipe pch_transcoder)
2900{
2901 struct drm_device *dev = crtc->base.dev;
2902 struct drm_i915_private *dev_priv = dev->dev_private;
2903 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
2904
2905 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
2906 I915_READ(HTOTAL(cpu_transcoder)));
2907 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
2908 I915_READ(HBLANK(cpu_transcoder)));
2909 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
2910 I915_READ(HSYNC(cpu_transcoder)));
2911
2912 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
2913 I915_READ(VTOTAL(cpu_transcoder)));
2914 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
2915 I915_READ(VBLANK(cpu_transcoder)));
2916 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
2917 I915_READ(VSYNC(cpu_transcoder)));
2918 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
2919 I915_READ(VSYNCSHIFT(cpu_transcoder)));
2920}
2921
f67a559d
JB		 2922/*
2923 * Enable PCH resources required for PCH ports:
2924 * - PCH PLLs
2925 * - FDI training & RX/TX
2926 * - update transcoder timings
2927 * - DP transcoding bits
2928 * - transcoder
2929 */
2930static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2931{
2932 struct drm_device *dev = crtc->dev;
2933 struct drm_i915_private *dev_priv = dev->dev_private;
2934 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2935 int pipe = intel_crtc->pipe;
ee7b9f93 2936 u32 reg, temp;
2c07245f 2937
ab9412ba 2938 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 2939
cd986abb
DV		 2940 /* Write the TU size bits before fdi link training, so that error
2941 * detection works. */
2942 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2943 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
2944
c98e9dcf 2945 /* For PCH output, training FDI link */
674cf967 2946 dev_priv->display.fdi_link_train(crtc);
2c07245f 2947
572deb37
DV		 2948 /* XXX: pch pll's can be enabled any time before we enable the PCH
2949 * transcoder, and we actually should do this to not upset any PCH
2950 * transcoder that already use the clock when we share it.
2951 *
2952 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
2953 * unconditionally resets the pll - we need that to have the right LVDS
2954 * enable sequence. */
b6b4e185 2955 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 2956
303b81e0 2957 if (HAS_PCH_CPT(dev)) {
ee7b9f93 2958 u32 sel;
4b645f14 2959
c98e9dcf 2960 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 2961 switch (pipe) {
2962 default:
2963 case 0:
2964 temp |= TRANSA_DPLL_ENABLE;
2965 sel = TRANSA_DPLLB_SEL;
2966 break;
2967 case 1:
2968 temp |= TRANSB_DPLL_ENABLE;
2969 sel = TRANSB_DPLLB_SEL;
2970 break;
2971 case 2:
2972 temp |= TRANSC_DPLL_ENABLE;
2973 sel = TRANSC_DPLLB_SEL;
2974 break;
d64311ab 2975 }
ee7b9f93
JB		 2976 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
2977 temp |= sel;
2978 else
2979 temp &= ~sel;
c98e9dcf 2980 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2981 }
5eddb70b 2982
d9b6cb56
JB		 2983 /* set transcoder timing, panel must allow it */
2984 assert_panel_unlocked(dev_priv, pipe);
275f01b2 2985 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 2986
303b81e0 2987 intel_fdi_normal_train(crtc);
5e84e1a4 2988
c98e9dcf
JB		 2989 /* For PCH DP, enable TRANS_DP_CTL */
2990 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2991 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2992 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 2993 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 2994 reg = TRANS_DP_CTL(pipe);
2995 temp = I915_READ(reg);
2996 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2997 TRANS_DP_SYNC_MASK |
2998 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2999 temp |= (TRANS_DP_OUTPUT_ENABLE |
3000 TRANS_DP_ENH_FRAMING);
9325c9f0 3001 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3002
3003 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3004 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3005 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3006 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3007
3008 switch (intel_trans_dp_port_sel(crtc)) {
3009 case PCH_DP_B:
5eddb70b 3010 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3011 break;
3012 case PCH_DP_C:
5eddb70b 3013 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3014 break;
3015 case PCH_DP_D:
5eddb70b 3016 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3017 break;
3018 default:
e95d41e1 3019 BUG();
32f9d658 3020 }
2c07245f 3021
5eddb70b 3022 I915_WRITE(reg, temp);
6be4a607 3023 }
b52eb4dc 3024
b8a4f404 3025 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3026}
3027
1507e5bd
PZ		 3028static void lpt_pch_enable(struct drm_crtc *crtc)
3029{
3030 struct drm_device *dev = crtc->dev;
3031 struct drm_i915_private *dev_priv = dev->dev_private;
3032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3033 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3034
ab9412ba 3035 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3036
8c52b5e8 3037 lpt_program_iclkip(crtc);
1507e5bd 3038
0540e488 3039 /* Set transcoder timing. */
275f01b2 3040 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3041
937bb610 3042 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3043}
3044
ee7b9f93
JB		 3045static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3046{
3047 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3048
3049 if (pll == NULL)
3050 return;
3051
3052 if (pll->refcount == 0) {
3053 WARN(1, "bad PCH PLL refcount\n");
3054 return;
3055 }
3056
3057 --pll->refcount;
3058 intel_crtc->pch_pll = NULL;
3059}
3060
3061static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3062{
3063 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3064 struct intel_pch_pll *pll;
3065 int i;
3066
3067 pll = intel_crtc->pch_pll;
3068 if (pll) {
3069 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3070 intel_crtc->base.base.id, pll->pll_reg);
3071 goto prepare;
3072 }
3073
98b6bd99
DV		 3074 if (HAS_PCH_IBX(dev_priv->dev)) {
3075 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3076 i = intel_crtc->pipe;
3077 pll = &dev_priv->pch_plls[i];
3078
3079 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3080 intel_crtc->base.base.id, pll->pll_reg);
3081
3082 goto found;
3083 }
3084
ee7b9f93
JB		 3085 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3086 pll = &dev_priv->pch_plls[i];
3087
3088 /* Only want to check enabled timings first */
3089 if (pll->refcount == 0)
3090 continue;
3091
3092 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3093 fp == I915_READ(pll->fp0_reg)) {
3094 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3095 intel_crtc->base.base.id,
3096 pll->pll_reg, pll->refcount, pll->active);
3097
3098 goto found;
3099 }
3100 }
3101
3102 /* Ok no matching timings, maybe there's a free one? */
3103 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3104 pll = &dev_priv->pch_plls[i];
3105 if (pll->refcount == 0) {
3106 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3107 intel_crtc->base.base.id, pll->pll_reg);
3108 goto found;
3109 }
3110 }
3111
3112 return NULL;
3113
3114found:
3115 intel_crtc->pch_pll = pll;
3116 pll->refcount++;
84f44ce7 3117 DRM_DEBUG_DRIVER("using pll %d for pipe %c\n", i, pipe_name(intel_crtc->pipe));
ee7b9f93
JB		 3118prepare: /* separate function? */
3119 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3120
e04c7350
CW		 3121 /* Wait for the clocks to stabilize before rewriting the regs */
3122 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3123 POSTING_READ(pll->pll_reg);
3124 udelay(150);
e04c7350
CW		 3125
3126 I915_WRITE(pll->fp0_reg, fp);
3127 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3128 pll->on = false;
3129 return pll;
3130}
3131
a1520318 3132static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3133{
3134 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3135 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3136 u32 temp;
3137
3138 temp = I915_READ(dslreg);
3139 udelay(500);
3140 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3141 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3142 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3143 }
3144}
3145
b074cec8
JB		 3146static void ironlake_pfit_enable(struct intel_crtc *crtc)
3147{
3148 struct drm_device *dev = crtc->base.dev;
3149 struct drm_i915_private *dev_priv = dev->dev_private;
3150 int pipe = crtc->pipe;
3151
0ef37f3f 3152 if (crtc->config.pch_pfit.size) {
b074cec8
JB		 3153 /* Force use of hard-coded filter coefficients
3154 * as some pre-programmed values are broken,
3155 * e.g. x201.
3156 */
3157 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3158 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3159 PF_PIPE_SEL_IVB(pipe));
3160 else
3161 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3162 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3163 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
3164 }
3165}
3166
f67a559d
JB		 3167static void ironlake_crtc_enable(struct drm_crtc *crtc)
3168{
3169 struct drm_device *dev = crtc->dev;
3170 struct drm_i915_private *dev_priv = dev->dev_private;
3171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3172 struct intel_encoder *encoder;
f67a559d
JB		 3173 int pipe = intel_crtc->pipe;
3174 int plane = intel_crtc->plane;
3175 u32 temp;
f67a559d 3176
08a48469
DV		 3177 WARN_ON(!crtc->enabled);
3178
f67a559d
JB		 3179 if (intel_crtc->active)
3180 return;
3181
3182 intel_crtc->active = true;
8664281b
PZ		 3183
3184 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3185 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3186
f67a559d
JB		 3187 intel_update_watermarks(dev);
3188
3189 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3190 temp = I915_READ(PCH_LVDS);
3191 if ((temp & LVDS_PORT_EN) == 0)
3192 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3193 }
3194
f67a559d 3195
5bfe2ac0 3196 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3197 /* Note: FDI PLL enabling _must_ be done before we enable the
3198 * cpu pipes, hence this is separate from all the other fdi/pch
3199 * enabling. */
88cefb6c 3200 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3201 } else {
3202 assert_fdi_tx_disabled(dev_priv, pipe);
3203 assert_fdi_rx_disabled(dev_priv, pipe);
3204 }
f67a559d 3205
bf49ec8c
DV		 3206 for_each_encoder_on_crtc(dev, crtc, encoder)
3207 if (encoder->pre_enable)
3208 encoder->pre_enable(encoder);
f67a559d
JB		 3209
3210 /* Enable panel fitting for LVDS */
b074cec8 3211 ironlake_pfit_enable(intel_crtc);
f67a559d 3212
9c54c0dd
JB		 3213 /*
3214 * On ILK+ LUT must be loaded before the pipe is running but with
3215 * clocks enabled
3216 */
3217 intel_crtc_load_lut(crtc);
3218
5bfe2ac0
DV		 3219 intel_enable_pipe(dev_priv, pipe,
3220 intel_crtc->config.has_pch_encoder);
f67a559d
JB		 3221 intel_enable_plane(dev_priv, plane, pipe);
3222
5bfe2ac0 3223 if (intel_crtc->config.has_pch_encoder)
f67a559d 3224 ironlake_pch_enable(crtc);
c98e9dcf 3225
d1ebd816 3226 mutex_lock(&dev->struct_mutex);
bed4a673 3227 intel_update_fbc(dev);
d1ebd816
BW		 3228 mutex_unlock(&dev->struct_mutex);
3229
6b383a7f 3230 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3231
fa5c73b1
DV		 3232 for_each_encoder_on_crtc(dev, crtc, encoder)
3233 encoder->enable(encoder);
61b77ddd
DV		 3234
3235 if (HAS_PCH_CPT(dev))
a1520318 3236 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3237
3238 /*
3239 * There seems to be a race in PCH platform hw (at least on some
3240 * outputs) where an enabled pipe still completes any pageflip right
3241 * away (as if the pipe is off) instead of waiting for vblank. As soon
3242 * as the first vblank happend, everything works as expected. Hence just
3243 * wait for one vblank before returning to avoid strange things
3244 * happening.
3245 */
3246 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3247}
3248
42db64ef
PZ		 3249/* IPS only exists on ULT machines and is tied to pipe A. */
3250static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3251{
3252 return IS_ULT(crtc->base.dev) && crtc->pipe == PIPE_A;
3253}
3254
3255static void hsw_enable_ips(struct intel_crtc *crtc)
3256{
3257 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3258
3259 if (!crtc->config.ips_enabled)
3260 return;
3261
3262 /* We can only enable IPS after we enable a plane and wait for a vblank.
3263 * We guarantee that the plane is enabled by calling intel_enable_ips
3264 * only after intel_enable_plane. And intel_enable_plane already waits
3265 * for a vblank, so all we need to do here is to enable the IPS bit. */
3266 assert_plane_enabled(dev_priv, crtc->plane);
3267 I915_WRITE(IPS_CTL, IPS_ENABLE);
3268}
3269
3270static void hsw_disable_ips(struct intel_crtc *crtc)
3271{
3272 struct drm_device *dev = crtc->base.dev;
3273 struct drm_i915_private *dev_priv = dev->dev_private;
3274
3275 if (!crtc->config.ips_enabled)
3276 return;
3277
3278 assert_plane_enabled(dev_priv, crtc->plane);
3279 I915_WRITE(IPS_CTL, 0);
3280
3281 /* We need to wait for a vblank before we can disable the plane. */
3282 intel_wait_for_vblank(dev, crtc->pipe);
3283}
3284
4f771f10
PZ		 3285static void haswell_crtc_enable(struct drm_crtc *crtc)
3286{
3287 struct drm_device *dev = crtc->dev;
3288 struct drm_i915_private *dev_priv = dev->dev_private;
3289 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3290 struct intel_encoder *encoder;
3291 int pipe = intel_crtc->pipe;
3292 int plane = intel_crtc->plane;
4f771f10
PZ		 3293
3294 WARN_ON(!crtc->enabled);
3295
3296 if (intel_crtc->active)
3297 return;
3298
3299 intel_crtc->active = true;
8664281b
PZ		 3300
3301 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3302 if (intel_crtc->config.has_pch_encoder)
3303 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3304
4f771f10
PZ		 3305 intel_update_watermarks(dev);
3306
5bfe2ac0 3307 if (intel_crtc->config.has_pch_encoder)
04945641 3308 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3309
3310 for_each_encoder_on_crtc(dev, crtc, encoder)
3311 if (encoder->pre_enable)
3312 encoder->pre_enable(encoder);
3313
1f544388 3314 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3315
1f544388 3316 /* Enable panel fitting for eDP */
b074cec8 3317 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3318
3319 /*
3320 * On ILK+ LUT must be loaded before the pipe is running but with
3321 * clocks enabled
3322 */
3323 intel_crtc_load_lut(crtc);
3324
1f544388 3325 intel_ddi_set_pipe_settings(crtc);
8228c251 3326 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3327
5bfe2ac0
DV		 3328 intel_enable_pipe(dev_priv, pipe,
3329 intel_crtc->config.has_pch_encoder);
4f771f10
PZ		 3330 intel_enable_plane(dev_priv, plane, pipe);
3331
42db64ef
PZ		 3332 hsw_enable_ips(intel_crtc);
3333
5bfe2ac0 3334 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3335 lpt_pch_enable(crtc);
4f771f10
PZ		 3336
3337 mutex_lock(&dev->struct_mutex);
3338 intel_update_fbc(dev);
3339 mutex_unlock(&dev->struct_mutex);
3340
3341 intel_crtc_update_cursor(crtc, true);
3342
3343 for_each_encoder_on_crtc(dev, crtc, encoder)
3344 encoder->enable(encoder);
3345
4f771f10
PZ		 3346 /*
3347 * There seems to be a race in PCH platform hw (at least on some
3348 * outputs) where an enabled pipe still completes any pageflip right
3349 * away (as if the pipe is off) instead of waiting for vblank. As soon
3350 * as the first vblank happend, everything works as expected. Hence just
3351 * wait for one vblank before returning to avoid strange things
3352 * happening.
3353 */
3354 intel_wait_for_vblank(dev, intel_crtc->pipe);
3355}
3356
3f8dce3a
DV		 3357static void ironlake_pfit_disable(struct intel_crtc *crtc)
3358{
3359 struct drm_device *dev = crtc->base.dev;
3360 struct drm_i915_private *dev_priv = dev->dev_private;
3361 int pipe = crtc->pipe;
3362
3363 /* To avoid upsetting the power well on haswell only disable the pfit if
3364 * it's in use. The hw state code will make sure we get this right. */
3365 if (crtc->config.pch_pfit.size) {
3366 I915_WRITE(PF_CTL(pipe), 0);
3367 I915_WRITE(PF_WIN_POS(pipe), 0);
3368 I915_WRITE(PF_WIN_SZ(pipe), 0);
3369 }
3370}
3371
6be4a607
JB		 3372static void ironlake_crtc_disable(struct drm_crtc *crtc)
3373{
3374 struct drm_device *dev = crtc->dev;
3375 struct drm_i915_private *dev_priv = dev->dev_private;
3376 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3377 struct intel_encoder *encoder;
6be4a607
JB		 3378 int pipe = intel_crtc->pipe;
3379 int plane = intel_crtc->plane;
5eddb70b 3380 u32 reg, temp;
b52eb4dc 3381
ef9c3aee 3382
f7abfe8b
CW		 3383 if (!intel_crtc->active)
3384 return;
3385
ea9d758d
DV		 3386 for_each_encoder_on_crtc(dev, crtc, encoder)
3387 encoder->disable(encoder);
3388
e6c3a2a6 3389 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3390 drm_vblank_off(dev, pipe);
6b383a7f 3391 intel_crtc_update_cursor(crtc, false);
5eddb70b 3392
b24e7179 3393 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3394
973d04f9
CW		 3395 if (dev_priv->cfb_plane == plane)
3396 intel_disable_fbc(dev);
2c07245f 3397
8664281b 3398 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
b24e7179 3399 intel_disable_pipe(dev_priv, pipe);
32f9d658 3400
3f8dce3a 3401 ironlake_pfit_disable(intel_crtc);
2c07245f 3402
bf49ec8c
DV		 3403 for_each_encoder_on_crtc(dev, crtc, encoder)
3404 if (encoder->post_disable)
3405 encoder->post_disable(encoder);
2c07245f 3406
0fc932b8 3407 ironlake_fdi_disable(crtc);
249c0e64 3408
b8a4f404 3409 ironlake_disable_pch_transcoder(dev_priv, pipe);
8664281b 3410 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
913d8d11 3411
6be4a607
JB		 3412 if (HAS_PCH_CPT(dev)) {
3413 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3414 reg = TRANS_DP_CTL(pipe);
3415 temp = I915_READ(reg);
3416 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3417 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3418 I915_WRITE(reg, temp);
6be4a607
JB		 3419
3420 /* disable DPLL_SEL */
3421 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3422 switch (pipe) {
3423 case 0:
d64311ab 3424 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3425 break;
3426 case 1:
6be4a607 3427 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3428 break;
3429 case 2:
4b645f14 3430 /* C shares PLL A or B */
d64311ab 3431 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3432 break;
3433 default:
3434 BUG(); /* wtf */
3435 }
6be4a607 3436 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3437 }
e3421a18 3438
6be4a607 3439 /* disable PCH DPLL */
ee7b9f93 3440 intel_disable_pch_pll(intel_crtc);
8db9d77b 3441
88cefb6c 3442 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3443
f7abfe8b 3444 intel_crtc->active = false;
6b383a7f 3445 intel_update_watermarks(dev);
d1ebd816
BW		 3446
3447 mutex_lock(&dev->struct_mutex);
6b383a7f 3448 intel_update_fbc(dev);
d1ebd816 3449 mutex_unlock(&dev->struct_mutex);
6be4a607 3450}
1b3c7a47 3451
4f771f10 3452static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3453{
4f771f10
PZ		 3454 struct drm_device *dev = crtc->dev;
3455 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3456 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3457 struct intel_encoder *encoder;
3458 int pipe = intel_crtc->pipe;
3459 int plane = intel_crtc->plane;
3b117c8f 3460 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3461
4f771f10
PZ		 3462 if (!intel_crtc->active)
3463 return;
3464
3465 for_each_encoder_on_crtc(dev, crtc, encoder)
3466 encoder->disable(encoder);
3467
3468 intel_crtc_wait_for_pending_flips(crtc);
3469 drm_vblank_off(dev, pipe);
3470 intel_crtc_update_cursor(crtc, false);
3471
891348b2 3472 /* FBC must be disabled before disabling the plane on HSW. */
4f771f10
PZ		 3473 if (dev_priv->cfb_plane == plane)
3474 intel_disable_fbc(dev);
3475
42db64ef
PZ		 3476 hsw_disable_ips(intel_crtc);
3477
891348b2
RV		 3478 intel_disable_plane(dev_priv, plane, pipe);
3479
8664281b
PZ		 3480 if (intel_crtc->config.has_pch_encoder)
3481 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3482 intel_disable_pipe(dev_priv, pipe);
3483
ad80a810 3484 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3485
3f8dce3a 3486 ironlake_pfit_disable(intel_crtc);
4f771f10 3487
1f544388 3488 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3489
3490 for_each_encoder_on_crtc(dev, crtc, encoder)
3491 if (encoder->post_disable)
3492 encoder->post_disable(encoder);
3493
88adfff1 3494 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3495 lpt_disable_pch_transcoder(dev_priv);
8664281b 3496 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3497 intel_ddi_fdi_disable(crtc);
83616634 3498 }
4f771f10
PZ		 3499
3500 intel_crtc->active = false;
3501 intel_update_watermarks(dev);
3502
3503 mutex_lock(&dev->struct_mutex);
3504 intel_update_fbc(dev);
3505 mutex_unlock(&dev->struct_mutex);
3506}
3507
ee7b9f93
JB		 3508static void ironlake_crtc_off(struct drm_crtc *crtc)
3509{
3510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3511 intel_put_pch_pll(intel_crtc);
3512}
3513
6441ab5f
PZ		 3514static void haswell_crtc_off(struct drm_crtc *crtc)
3515{
3516 intel_ddi_put_crtc_pll(crtc);
3517}
3518
02e792fb
DV		 3519static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3520{
02e792fb 3521 if (!enable && intel_crtc->overlay) {
23f09ce3 3522 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3523 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3524
23f09ce3 3525 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3526 dev_priv->mm.interruptible = false;
3527 (void) intel_overlay_switch_off(intel_crtc->overlay);
3528 dev_priv->mm.interruptible = true;
23f09ce3 3529 mutex_unlock(&dev->struct_mutex);
02e792fb 3530 }
02e792fb 3531
5dcdbcb0
CW		 3532 /* Let userspace switch the overlay on again. In most cases userspace
3533 * has to recompute where to put it anyway.
3534 */
02e792fb
DV		 3535}
3536
61bc95c1
EE		 3537/**
3538 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3539 * cursor plane briefly if not already running after enabling the display
3540 * plane.
3541 * This workaround avoids occasional blank screens when self refresh is
3542 * enabled.
3543 */
3544static void
3545g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3546{
3547 u32 cntl = I915_READ(CURCNTR(pipe));
3548
3549 if ((cntl & CURSOR_MODE) == 0) {
3550 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3551
3552 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3553 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3554 intel_wait_for_vblank(dev_priv->dev, pipe);
3555 I915_WRITE(CURCNTR(pipe), cntl);
3556 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3557 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3558 }
3559}
3560
2dd24552
JB		 3561static void i9xx_pfit_enable(struct intel_crtc *crtc)
3562{
3563 struct drm_device *dev = crtc->base.dev;
3564 struct drm_i915_private *dev_priv = dev->dev_private;
3565 struct intel_crtc_config *pipe_config = &crtc->config;
3566
328d8e82 3567 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3568 return;
3569
2dd24552 3570 /*
c0b03411
DV		 3571 * The panel fitter should only be adjusted whilst the pipe is disabled,
3572 * according to register description and PRM.
2dd24552 3573 */
c0b03411
DV		 3574 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3575 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3576
b074cec8
JB		 3577 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3578 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3579
3580 /* Border color in case we don't scale up to the full screen. Black by
3581 * default, change to something else for debugging. */
3582 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3583}
3584
89b667f8
JB		 3585static void valleyview_crtc_enable(struct drm_crtc *crtc)
3586{
3587 struct drm_device *dev = crtc->dev;
3588 struct drm_i915_private *dev_priv = dev->dev_private;
3589 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3590 struct intel_encoder *encoder;
3591 int pipe = intel_crtc->pipe;
3592 int plane = intel_crtc->plane;
3593
3594 WARN_ON(!crtc->enabled);
3595
3596 if (intel_crtc->active)
3597 return;
3598
3599 intel_crtc->active = true;
3600 intel_update_watermarks(dev);
3601
3602 mutex_lock(&dev_priv->dpio_lock);
3603
3604 for_each_encoder_on_crtc(dev, crtc, encoder)
3605 if (encoder->pre_pll_enable)
3606 encoder->pre_pll_enable(encoder);
3607
3608 intel_enable_pll(dev_priv, pipe);
3609
3610 for_each_encoder_on_crtc(dev, crtc, encoder)
3611 if (encoder->pre_enable)
3612 encoder->pre_enable(encoder);
3613
3614 /* VLV wants encoder enabling _before_ the pipe is up. */
3615 for_each_encoder_on_crtc(dev, crtc, encoder)
3616 encoder->enable(encoder);
3617
2dd24552
JB		 3618 /* Enable panel fitting for eDP */
3619 i9xx_pfit_enable(intel_crtc);
3620
89b667f8
JB		 3621 intel_enable_pipe(dev_priv, pipe, false);
3622 intel_enable_plane(dev_priv, plane, pipe);
3623
3624 intel_crtc_load_lut(crtc);
3625 intel_update_fbc(dev);
3626
3627 /* Give the overlay scaler a chance to enable if it's on this pipe */
3628 intel_crtc_dpms_overlay(intel_crtc, true);
3629 intel_crtc_update_cursor(crtc, true);
3630
3631 mutex_unlock(&dev_priv->dpio_lock);
3632}
3633
0b8765c6 3634static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3635{
3636 struct drm_device *dev = crtc->dev;
79e53945
JB		 3637 struct drm_i915_private *dev_priv = dev->dev_private;
3638 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3639 struct intel_encoder *encoder;
79e53945 3640 int pipe = intel_crtc->pipe;
80824003 3641 int plane = intel_crtc->plane;
79e53945 3642
08a48469
DV		 3643 WARN_ON(!crtc->enabled);
3644
f7abfe8b
CW		 3645 if (intel_crtc->active)
3646 return;
3647
3648 intel_crtc->active = true;
6b383a7f
CW		 3649 intel_update_watermarks(dev);
3650
63d7bbe9 3651 intel_enable_pll(dev_priv, pipe);
9d6d9f19
MK		 3652
3653 for_each_encoder_on_crtc(dev, crtc, encoder)
3654 if (encoder->pre_enable)
3655 encoder->pre_enable(encoder);
3656
2dd24552
JB		 3657 /* Enable panel fitting for LVDS */
3658 i9xx_pfit_enable(intel_crtc);
3659
040484af 3660 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3661 intel_enable_plane(dev_priv, plane, pipe);
61bc95c1
EE		 3662 if (IS_G4X(dev))
3663 g4x_fixup_plane(dev_priv, pipe);
79e53945 3664
0b8765c6 3665 intel_crtc_load_lut(crtc);
bed4a673 3666 intel_update_fbc(dev);
79e53945 3667
0b8765c6
JB		 3668 /* Give the overlay scaler a chance to enable if it's on this pipe */
3669 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3670 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3671
fa5c73b1
DV		 3672 for_each_encoder_on_crtc(dev, crtc, encoder)
3673 encoder->enable(encoder);
0b8765c6 3674}
79e53945 3675
87476d63
DV		 3676static void i9xx_pfit_disable(struct intel_crtc *crtc)
3677{
3678 struct drm_device *dev = crtc->base.dev;
3679 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3680
328d8e82
DV		 3681 if (!crtc->config.gmch_pfit.control)
3682 return;
87476d63 3683
328d8e82 3684 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3685
328d8e82
DV		 3686 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3687 I915_READ(PFIT_CONTROL));
3688 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3689}
3690
0b8765c6
JB		 3691static void i9xx_crtc_disable(struct drm_crtc *crtc)
3692{
3693 struct drm_device *dev = crtc->dev;
3694 struct drm_i915_private *dev_priv = dev->dev_private;
3695 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3696 struct intel_encoder *encoder;
0b8765c6
JB		 3697 int pipe = intel_crtc->pipe;
3698 int plane = intel_crtc->plane;
ef9c3aee 3699
f7abfe8b
CW		 3700 if (!intel_crtc->active)
3701 return;
3702
ea9d758d
DV		 3703 for_each_encoder_on_crtc(dev, crtc, encoder)
3704 encoder->disable(encoder);
3705
0b8765c6 3706 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3707 intel_crtc_wait_for_pending_flips(crtc);
3708 drm_vblank_off(dev, pipe);
0b8765c6 3709 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3710 intel_crtc_update_cursor(crtc, false);
0b8765c6 3711
973d04f9
CW		 3712 if (dev_priv->cfb_plane == plane)
3713 intel_disable_fbc(dev);
79e53945 3714
b24e7179 3715 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3716 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3717
87476d63 3718 i9xx_pfit_disable(intel_crtc);
24a1f16d 3719
89b667f8
JB		 3720 for_each_encoder_on_crtc(dev, crtc, encoder)
3721 if (encoder->post_disable)
3722 encoder->post_disable(encoder);
3723
63d7bbe9 3724 intel_disable_pll(dev_priv, pipe);
0b8765c6 3725
f7abfe8b 3726 intel_crtc->active = false;
6b383a7f
CW		 3727 intel_update_fbc(dev);
3728 intel_update_watermarks(dev);
0b8765c6
JB		 3729}
3730
ee7b9f93
JB		 3731static void i9xx_crtc_off(struct drm_crtc *crtc)
3732{
3733}
3734
976f8a20
DV		 3735static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3736 bool enabled)
2c07245f
ZW		 3737{
3738 struct drm_device *dev = crtc->dev;
3739 struct drm_i915_master_private *master_priv;
3740 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3741 int pipe = intel_crtc->pipe;
79e53945
JB		 3742
3743 if (!dev->primary->master)
3744 return;
3745
3746 master_priv = dev->primary->master->driver_priv;
3747 if (!master_priv->sarea_priv)
3748 return;
3749
79e53945
JB		 3750 switch (pipe) {
3751 case 0:
3752 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3753 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3754 break;
3755 case 1:
3756 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3757 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3758 break;
3759 default:
9db4a9c7 3760 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3761 break;
3762 }
79e53945
JB		 3763}
3764
976f8a20
DV		 3765/**
3766 * Sets the power management mode of the pipe and plane.
3767 */
3768void intel_crtc_update_dpms(struct drm_crtc *crtc)
3769{
3770 struct drm_device *dev = crtc->dev;
3771 struct drm_i915_private *dev_priv = dev->dev_private;
3772 struct intel_encoder *intel_encoder;
3773 bool enable = false;
3774
3775 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3776 enable |= intel_encoder->connectors_active;
3777
3778 if (enable)
3779 dev_priv->display.crtc_enable(crtc);
3780 else
3781 dev_priv->display.crtc_disable(crtc);
3782
3783 intel_crtc_update_sarea(crtc, enable);
3784}
3785
cdd59983
CW		 3786static void intel_crtc_disable(struct drm_crtc *crtc)
3787{
cdd59983 3788 struct drm_device *dev = crtc->dev;
976f8a20 3789 struct drm_connector *connector;
ee7b9f93 3790 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3791 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3792
976f8a20
DV		 3793 /* crtc should still be enabled when we disable it. */
3794 WARN_ON(!crtc->enabled);
3795
3796 dev_priv->display.crtc_disable(crtc);
c77bf565 3797 intel_crtc->eld_vld = false;
976f8a20 3798 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3799 dev_priv->display.off(crtc);
3800
931872fc
CW		 3801 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3802 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3803
3804 if (crtc->fb) {
3805 mutex_lock(&dev->struct_mutex);
1690e1eb 3806 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3807 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3808 crtc->fb = NULL;
3809 }
3810
3811 /* Update computed state. */
3812 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3813 if (!connector->encoder || !connector->encoder->crtc)
3814 continue;
3815
3816 if (connector->encoder->crtc != crtc)
3817 continue;
3818
3819 connector->dpms = DRM_MODE_DPMS_OFF;
3820 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3821 }
3822}
3823
a261b246 3824void intel_modeset_disable(struct drm_device *dev)
79e53945 3825{
a261b246
DV		 3826 struct drm_crtc *crtc;
3827
3828 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3829 if (crtc->enabled)
3830 intel_crtc_disable(crtc);
3831 }
79e53945
JB		 3832}
3833
ea5b213a 3834void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3835{
4ef69c7a 3836 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3837
ea5b213a
CW		 3838 drm_encoder_cleanup(encoder);
3839 kfree(intel_encoder);
7e7d76c3
JB		 3840}
3841
5ab432ef
DV		 3842/* Simple dpms helper for encodres with just one connector, no cloning and only
3843 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3844 * state of the entire output pipe. */
3845void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3846{
5ab432ef
DV		 3847 if (mode == DRM_MODE_DPMS_ON) {
3848 encoder->connectors_active = true;
3849
b2cabb0e 3850 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3851 } else {
3852 encoder->connectors_active = false;
3853
b2cabb0e 3854 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3855 }
79e53945
JB		 3856}
3857
0a91ca29
DV		 3858/* Cross check the actual hw state with our own modeset state tracking (and it's
3859 * internal consistency). */
b980514c 3860static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3861{
0a91ca29
DV		 3862 if (connector->get_hw_state(connector)) {
3863 struct intel_encoder *encoder = connector->encoder;
3864 struct drm_crtc *crtc;
3865 bool encoder_enabled;
3866 enum pipe pipe;
3867
3868 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3869 connector->base.base.id,
3870 drm_get_connector_name(&connector->base));
3871
3872 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3873 "wrong connector dpms state\n");
3874 WARN(connector->base.encoder != &encoder->base,
3875 "active connector not linked to encoder\n");
3876 WARN(!encoder->connectors_active,
3877 "encoder->connectors_active not set\n");
3878
3879 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3880 WARN(!encoder_enabled, "encoder not enabled\n");
3881 if (WARN_ON(!encoder->base.crtc))
3882 return;
3883
3884 crtc = encoder->base.crtc;
3885
3886 WARN(!crtc->enabled, "crtc not enabled\n");
3887 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3888 WARN(pipe != to_intel_crtc(crtc)->pipe,
3889 "encoder active on the wrong pipe\n");
3890 }
79e53945
JB		 3891}
3892
5ab432ef
DV		 3893/* Even simpler default implementation, if there's really no special case to
3894 * consider. */
3895void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3896{
5ab432ef 3897 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3898
5ab432ef
DV		 3899 /* All the simple cases only support two dpms states. */
3900 if (mode != DRM_MODE_DPMS_ON)
3901 mode = DRM_MODE_DPMS_OFF;
d4270e57 3902
5ab432ef
DV		 3903 if (mode == connector->dpms)
3904 return;
3905
3906 connector->dpms = mode;
3907
3908 /* Only need to change hw state when actually enabled */
3909 if (encoder->base.crtc)
3910 intel_encoder_dpms(encoder, mode);
3911 else
8af6cf88 3912 WARN_ON(encoder->connectors_active != false);
0a91ca29 3913
b980514c 3914 intel_modeset_check_state(connector->dev);
79e53945
JB		 3915}
3916
f0947c37
DV		 3917/* Simple connector->get_hw_state implementation for encoders that support only
3918 * one connector and no cloning and hence the encoder state determines the state
3919 * of the connector. */
3920bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3921{
24929352 3922 enum pipe pipe = 0;
f0947c37 3923 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3924
f0947c37 3925 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3926}
3927
1857e1da
DV		 3928static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
3929 struct intel_crtc_config *pipe_config)
3930{
3931 struct drm_i915_private *dev_priv = dev->dev_private;
3932 struct intel_crtc *pipe_B_crtc =
3933 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
3934
3935 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
3936 pipe_name(pipe), pipe_config->fdi_lanes);
3937 if (pipe_config->fdi_lanes > 4) {
3938 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
3939 pipe_name(pipe), pipe_config->fdi_lanes);
3940 return false;
3941 }
3942
3943 if (IS_HASWELL(dev)) {
3944 if (pipe_config->fdi_lanes > 2) {
3945 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
3946 pipe_config->fdi_lanes);
3947 return false;
3948 } else {
3949 return true;
3950 }
3951 }
3952
3953 if (INTEL_INFO(dev)->num_pipes == 2)
3954 return true;
3955
3956 /* Ivybridge 3 pipe is really complicated */
3957 switch (pipe) {
3958 case PIPE_A:
3959 return true;
3960 case PIPE_B:
3961 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
3962 pipe_config->fdi_lanes > 2) {
3963 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3964 pipe_name(pipe), pipe_config->fdi_lanes);
3965 return false;
3966 }
3967 return true;
3968 case PIPE_C:
1e833f40 3969 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 3970 pipe_B_crtc->config.fdi_lanes <= 2) {
3971 if (pipe_config->fdi_lanes > 2) {
3972 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
3973 pipe_name(pipe), pipe_config->fdi_lanes);
3974 return false;
3975 }
3976 } else {
3977 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
3978 return false;
3979 }
3980 return true;
3981 default:
3982 BUG();
3983 }
3984}
3985
e29c22c0
DV		 3986#define RETRY 1
3987static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
3988 struct intel_crtc_config *pipe_config)
877d48d5 3989{
1857e1da 3990 struct drm_device *dev = intel_crtc->base.dev;
877d48d5
DV		 3991 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
3992 int target_clock, lane, link_bw;
e29c22c0 3993 bool setup_ok, needs_recompute = false;
877d48d5 3994
e29c22c0 3995retry:
877d48d5
DV		 3996 /* FDI is a binary signal running at ~2.7GHz, encoding
3997 * each output octet as 10 bits. The actual frequency
3998 * is stored as a divider into a 100MHz clock, and the
3999 * mode pixel clock is stored in units of 1KHz.
4000 * Hence the bw of each lane in terms of the mode signal
4001 * is:
4002 */
4003 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4004
4005 if (pipe_config->pixel_target_clock)
4006 target_clock = pipe_config->pixel_target_clock;
4007 else
4008 target_clock = adjusted_mode->clock;
4009
4010 lane = ironlake_get_lanes_required(target_clock, link_bw,
4011 pipe_config->pipe_bpp);
4012
4013 pipe_config->fdi_lanes = lane;
4014
4015 if (pipe_config->pixel_multiplier > 1)
4016 link_bw *= pipe_config->pixel_multiplier;
4017 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, target_clock,
4018 link_bw, &pipe_config->fdi_m_n);
1857e1da 4019
e29c22c0
DV		 4020 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4021 intel_crtc->pipe, pipe_config);
4022 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4023 pipe_config->pipe_bpp -= 2*3;
4024 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4025 pipe_config->pipe_bpp);
4026 needs_recompute = true;
4027 pipe_config->bw_constrained = true;
4028
4029 goto retry;
4030 }
4031
4032 if (needs_recompute)
4033 return RETRY;
4034
4035 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4036}
4037
42db64ef
PZ		 4038static void hsw_compute_ips_config(struct intel_crtc *crtc,
4039 struct intel_crtc_config *pipe_config)
4040{
3c4ca58c
PZ		 4041 pipe_config->ips_enabled = i915_enable_ips &&
4042 hsw_crtc_supports_ips(crtc) &&
42db64ef
PZ		 4043 pipe_config->pipe_bpp == 24;
4044}
4045
e29c22c0
DV		 4046static int intel_crtc_compute_config(struct drm_crtc *crtc,
4047 struct intel_crtc_config *pipe_config)
79e53945 4048{
2c07245f 4049 struct drm_device *dev = crtc->dev;
b8cecdf5 4050 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
42db64ef 4051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
89749350 4052
bad720ff 4053 if (HAS_PCH_SPLIT(dev)) {
2c07245f 4054 /* FDI link clock is fixed at 2.7G */
b8cecdf5
DV		 4055 if (pipe_config->requested_mode.clock * 3
4056 > IRONLAKE_FDI_FREQ * 4)
e29c22c0 4057 return -EINVAL;
2c07245f 4058 }
89749350 4059
f9bef081
DV		 4060 /* All interlaced capable intel hw wants timings in frames. Note though
4061 * that intel_lvds_mode_fixup does some funny tricks with the crtc
4062 * timings, so we need to be careful not to clobber these.*/
7ae89233 4063 if (!pipe_config->timings_set)
f9bef081 4064 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 4065
8693a824
DL		 4066 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4067 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4068 */
4069 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4070 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4071 return -EINVAL;
44f46b42 4072
bd080ee5 4073 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4074 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4075 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4076 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4077 * for lvds. */
4078 pipe_config->pipe_bpp = 8*3;
4079 }
4080
42db64ef
PZ		 4081 if (IS_HASWELL(dev))
4082 hsw_compute_ips_config(intel_crtc, pipe_config);
4083
877d48d5 4084 if (pipe_config->has_pch_encoder)
42db64ef 4085 return ironlake_fdi_compute_config(intel_crtc, pipe_config);
877d48d5 4086
e29c22c0 4087 return 0;
79e53945
JB		 4088}
4089
25eb05fc
JB		 4090static int valleyview_get_display_clock_speed(struct drm_device *dev)
4091{
4092 return 400000; /* FIXME */
4093}
4094
e70236a8
JB		 4095static int i945_get_display_clock_speed(struct drm_device *dev)
4096{
4097 return 400000;
4098}
79e53945 4099
e70236a8 4100static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4101{
e70236a8
JB		 4102 return 333000;
4103}
79e53945 4104
e70236a8
JB		 4105static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4106{
4107 return 200000;
4108}
79e53945 4109
e70236a8
JB		 4110static int i915gm_get_display_clock_speed(struct drm_device *dev)
4111{
4112 u16 gcfgc = 0;
79e53945 4113
e70236a8
JB		 4114 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4115
4116 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4117 return 133000;
4118 else {
4119 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4120 case GC_DISPLAY_CLOCK_333_MHZ:
4121 return 333000;
4122 default:
4123 case GC_DISPLAY_CLOCK_190_200_MHZ:
4124 return 190000;
79e53945 4125 }
e70236a8
JB		 4126 }
4127}
4128
4129static int i865_get_display_clock_speed(struct drm_device *dev)
4130{
4131 return 266000;
4132}
4133
4134static int i855_get_display_clock_speed(struct drm_device *dev)
4135{
4136 u16 hpllcc = 0;
4137 /* Assume that the hardware is in the high speed state. This
4138 * should be the default.
4139 */
4140 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4141 case GC_CLOCK_133_200:
4142 case GC_CLOCK_100_200:
4143 return 200000;
4144 case GC_CLOCK_166_250:
4145 return 250000;
4146 case GC_CLOCK_100_133:
79e53945 4147 return 133000;
e70236a8 4148 }
79e53945 4149
e70236a8
JB		 4150 /* Shouldn't happen */
4151 return 0;
4152}
79e53945 4153
e70236a8
JB		 4154static int i830_get_display_clock_speed(struct drm_device *dev)
4155{
4156 return 133000;
79e53945
JB		 4157}
4158
2c07245f 4159static void
a65851af 4160intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4161{
a65851af
VS		 4162 while (*num > DATA_LINK_M_N_MASK ||
4163 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4164 *num >>= 1;
4165 *den >>= 1;
4166 }
4167}
4168
a65851af
VS		 4169static void compute_m_n(unsigned int m, unsigned int n,
4170 uint32_t *ret_m, uint32_t *ret_n)
4171{
4172 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4173 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4174 intel_reduce_m_n_ratio(ret_m, ret_n);
4175}
4176
e69d0bc1
DV		 4177void
4178intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4179 int pixel_clock, int link_clock,
4180 struct intel_link_m_n *m_n)
2c07245f 4181{
e69d0bc1 4182 m_n->tu = 64;
a65851af
VS		 4183
4184 compute_m_n(bits_per_pixel * pixel_clock,
4185 link_clock * nlanes * 8,
4186 &m_n->gmch_m, &m_n->gmch_n);
4187
4188 compute_m_n(pixel_clock, link_clock,
4189 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4190}
4191
a7615030
CW		 4192static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4193{
72bbe58c
KP		 4194 if (i915_panel_use_ssc >= 0)
4195 return i915_panel_use_ssc != 0;
41aa3448 4196 return dev_priv->vbt.lvds_use_ssc
435793df 4197 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4198}
4199
a0c4da24
JB		 4200static int vlv_get_refclk(struct drm_crtc *crtc)
4201{
4202 struct drm_device *dev = crtc->dev;
4203 struct drm_i915_private *dev_priv = dev->dev_private;
4204 int refclk = 27000; /* for DP & HDMI */
4205
4206 return 100000; /* only one validated so far */
4207
4208 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4209 refclk = 96000;
4210 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4211 if (intel_panel_use_ssc(dev_priv))
4212 refclk = 100000;
4213 else
4214 refclk = 96000;
4215 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4216 refclk = 100000;
4217 }
4218
4219 return refclk;
4220}
4221
c65d77d8
JB		 4222static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4223{
4224 struct drm_device *dev = crtc->dev;
4225 struct drm_i915_private *dev_priv = dev->dev_private;
4226 int refclk;
4227
a0c4da24
JB		 4228 if (IS_VALLEYVIEW(dev)) {
4229 refclk = vlv_get_refclk(crtc);
4230 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4231 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4232 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4233 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4234 refclk / 1000);
4235 } else if (!IS_GEN2(dev)) {
4236 refclk = 96000;
4237 } else {
4238 refclk = 48000;
4239 }
4240
4241 return refclk;
4242}
4243
7429e9d4
DV		 4244static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
4245{
4246 return (1 << dpll->n) << 16 | dpll->m1 << 8 | dpll->m2;
4247}
4248
4249static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4250{
4251 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
4252}
4253
f47709a9 4254static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4255 intel_clock_t *reduced_clock)
4256{
f47709a9 4257 struct drm_device *dev = crtc->base.dev;
a7516a05 4258 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4259 int pipe = crtc->pipe;
a7516a05
JB		 4260 u32 fp, fp2 = 0;
4261
4262 if (IS_PINEVIEW(dev)) {
7429e9d4 4263 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4264 if (reduced_clock)
7429e9d4 4265 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4266 } else {
7429e9d4 4267 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4268 if (reduced_clock)
7429e9d4 4269 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4270 }
4271
4272 I915_WRITE(FP0(pipe), fp);
4273
f47709a9
DV		 4274 crtc->lowfreq_avail = false;
4275 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4276 reduced_clock && i915_powersave) {
4277 I915_WRITE(FP1(pipe), fp2);
f47709a9 4278 crtc->lowfreq_avail = true;
a7516a05
JB		 4279 } else {
4280 I915_WRITE(FP1(pipe), fp);
4281 }
4282}
4283
89b667f8
JB		 4284static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv)
4285{
4286 u32 reg_val;
4287
4288 /*
4289 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4290 * and set it to a reasonable value instead.
4291 */
ae99258f 4292 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8
JB		 4293 reg_val &= 0xffffff00;
4294 reg_val |= 0x00000030;
ae99258f 4295 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4296
ae99258f 4297 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4298 reg_val &= 0x8cffffff;
4299 reg_val = 0x8c000000;
ae99258f 4300 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8 4301
ae99258f 4302 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF(1));
89b667f8 4303 reg_val &= 0xffffff00;
ae99258f 4304 vlv_dpio_write(dev_priv, DPIO_IREF(1), reg_val);
89b667f8 4305
ae99258f 4306 reg_val = vlv_dpio_read(dev_priv, DPIO_CALIBRATION);
89b667f8
JB		 4307 reg_val &= 0x00ffffff;
4308 reg_val |= 0xb0000000;
ae99258f 4309 vlv_dpio_write(dev_priv, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4310}
4311
b551842d
DV		 4312static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4313 struct intel_link_m_n *m_n)
4314{
4315 struct drm_device *dev = crtc->base.dev;
4316 struct drm_i915_private *dev_priv = dev->dev_private;
4317 int pipe = crtc->pipe;
4318
e3b95f1e
DV		 4319 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4320 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4321 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4322 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4323}
4324
4325static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4326 struct intel_link_m_n *m_n)
4327{
4328 struct drm_device *dev = crtc->base.dev;
4329 struct drm_i915_private *dev_priv = dev->dev_private;
4330 int pipe = crtc->pipe;
4331 enum transcoder transcoder = crtc->config.cpu_transcoder;
4332
4333 if (INTEL_INFO(dev)->gen >= 5) {
4334 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4335 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4336 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4337 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4338 } else {
e3b95f1e
DV		 4339 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4340 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4341 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4342 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4343 }
4344}
4345
03afc4a2
DV		 4346static void intel_dp_set_m_n(struct intel_crtc *crtc)
4347{
4348 if (crtc->config.has_pch_encoder)
4349 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4350 else
4351 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4352}
4353
f47709a9 4354static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4355{
f47709a9 4356 struct drm_device *dev = crtc->base.dev;
a0c4da24 4357 struct drm_i915_private *dev_priv = dev->dev_private;
89b667f8
JB		 4358 struct drm_display_mode *adjusted_mode =
4359 &crtc->config.adjusted_mode;
4360 struct intel_encoder *encoder;
f47709a9 4361 int pipe = crtc->pipe;
89b667f8 4362 u32 dpll, mdiv;
a0c4da24 4363 u32 bestn, bestm1, bestm2, bestp1, bestp2;
89b667f8 4364 bool is_hdmi;
198a037f 4365 u32 coreclk, reg_val, dpll_md;
a0c4da24 4366
09153000
DV		 4367 mutex_lock(&dev_priv->dpio_lock);
4368
89b667f8 4369 is_hdmi = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
a0c4da24 4370
f47709a9
DV		 4371 bestn = crtc->config.dpll.n;
4372 bestm1 = crtc->config.dpll.m1;
4373 bestm2 = crtc->config.dpll.m2;
4374 bestp1 = crtc->config.dpll.p1;
4375 bestp2 = crtc->config.dpll.p2;
a0c4da24 4376
89b667f8
JB		 4377 /* See eDP HDMI DPIO driver vbios notes doc */
4378
4379 /* PLL B needs special handling */
4380 if (pipe)
4381 vlv_pllb_recal_opamp(dev_priv);
4382
4383 /* Set up Tx target for periodic Rcomp update */
ae99258f 4384 vlv_dpio_write(dev_priv, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4385
4386 /* Disable target IRef on PLL */
ae99258f 4387 reg_val = vlv_dpio_read(dev_priv, DPIO_IREF_CTL(pipe));
89b667f8 4388 reg_val &= 0x00ffffff;
ae99258f 4389 vlv_dpio_write(dev_priv, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4390
4391 /* Disable fast lock */
ae99258f 4392 vlv_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4393
4394 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4395 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4396 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4397 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4398 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4399
4400 /*
4401 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4402 * but we don't support that).
4403 * Note: don't use the DAC post divider as it seems unstable.
4404 */
4405 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ae99258f 4406 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4407
89b667f8 4408 mdiv |= DPIO_ENABLE_CALIBRATION;
ae99258f 4409 vlv_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
a0c4da24 4410
89b667f8
JB		 4411 /* Set HBR and RBR LPF coefficients */
4412 if (adjusted_mode->clock == 162000 ||
4413 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
ae99258f 4414 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4415 0x005f0021);
4416 else
ae99258f 4417 vlv_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe),
89b667f8
JB		 4418 0x00d0000f);
4419
4420 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4421 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4422 /* Use SSC source */
4423 if (!pipe)
ae99258f 4424 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4425 0x0df40000);
4426 else
ae99258f 4427 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4428 0x0df70000);
4429 } else { /* HDMI or VGA */
4430 /* Use bend source */
4431 if (!pipe)
ae99258f 4432 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4433 0x0df70000);
4434 else
ae99258f 4435 vlv_dpio_write(dev_priv, DPIO_REFSFR(pipe),
89b667f8
JB		 4436 0x0df40000);
4437 }
a0c4da24 4438
ae99258f 4439 coreclk = vlv_dpio_read(dev_priv, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4440 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4441 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4442 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4443 coreclk |= 0x01000000;
ae99258f 4444 vlv_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4445
ae99258f 4446 vlv_dpio_write(dev_priv, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4447
89b667f8
JB		 4448 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
4449 if (encoder->pre_pll_enable)
4450 encoder->pre_pll_enable(encoder);
2a8f64ca 4451
89b667f8
JB		 4452 /* Enable DPIO clock input */
4453 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4454 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4455 if (pipe)
4456 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
2a8f64ca 4457
89b667f8 4458 dpll |= DPLL_VCO_ENABLE;
2a8f64ca 4459 I915_WRITE(DPLL(pipe), dpll);
2a8f64ca
VP		 4460 POSTING_READ(DPLL(pipe));
4461 udelay(150);
a0c4da24 4462
89b667f8
JB		 4463 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4464 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4465
198a037f
DV		 4466 dpll_md = 0;
4467 if (crtc->config.pixel_multiplier > 1) {
4468 dpll_md = (crtc->config.pixel_multiplier - 1)
4469 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
2a8f64ca 4470 }
198a037f
DV		 4471 I915_WRITE(DPLL_MD(pipe), dpll_md);
4472 POSTING_READ(DPLL_MD(pipe));
f47709a9 4473
89b667f8
JB		 4474 if (crtc->config.has_dp_encoder)
4475 intel_dp_set_m_n(crtc);
09153000
DV		 4476
4477 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4478}
4479
f47709a9
DV		 4480static void i9xx_update_pll(struct intel_crtc *crtc,
4481 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4482 int num_connectors)
4483{
f47709a9 4484 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4485 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4486 struct intel_encoder *encoder;
f47709a9 4487 int pipe = crtc->pipe;
eb1cbe48
DV		 4488 u32 dpll;
4489 bool is_sdvo;
f47709a9 4490 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4491
f47709a9 4492 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4493
f47709a9
DV		 4494 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4495 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4496
4497 dpll = DPLL_VGA_MODE_DIS;
4498
f47709a9 4499 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4500 dpll |= DPLLB_MODE_LVDS;
4501 else
4502 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4503
198a037f
DV		 4504 if ((crtc->config.pixel_multiplier > 1) &&
4505 (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))) {
4506 dpll |= (crtc->config.pixel_multiplier - 1)
4507 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4508 }
198a037f
DV		 4509
4510 if (is_sdvo)
4511 dpll |= DPLL_DVO_HIGH_SPEED;
4512
f47709a9 4513 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
eb1cbe48
DV		 4514 dpll |= DPLL_DVO_HIGH_SPEED;
4515
4516 /* compute bitmask from p1 value */
4517 if (IS_PINEVIEW(dev))
4518 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4519 else {
4520 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4521 if (IS_G4X(dev) && reduced_clock)
4522 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4523 }
4524 switch (clock->p2) {
4525 case 5:
4526 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4527 break;
4528 case 7:
4529 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4530 break;
4531 case 10:
4532 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4533 break;
4534 case 14:
4535 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4536 break;
4537 }
4538 if (INTEL_INFO(dev)->gen >= 4)
4539 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4540
09ede541 4541 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4542 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4543 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4544 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4545 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4546 else
4547 dpll |= PLL_REF_INPUT_DREFCLK;
4548
4549 dpll |= DPLL_VCO_ENABLE;
4550 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4551 POSTING_READ(DPLL(pipe));
4552 udelay(150);
4553
f47709a9 4554 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4555 if (encoder->pre_pll_enable)
4556 encoder->pre_pll_enable(encoder);
eb1cbe48 4557
f47709a9
DV		 4558 if (crtc->config.has_dp_encoder)
4559 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4560
4561 I915_WRITE(DPLL(pipe), dpll);
4562
4563 /* Wait for the clocks to stabilize. */
4564 POSTING_READ(DPLL(pipe));
4565 udelay(150);
4566
4567 if (INTEL_INFO(dev)->gen >= 4) {
198a037f
DV		 4568 u32 dpll_md = 0;
4569 if (crtc->config.pixel_multiplier > 1) {
4570 dpll_md = (crtc->config.pixel_multiplier - 1)
4571 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
eb1cbe48 4572 }
198a037f 4573 I915_WRITE(DPLL_MD(pipe), dpll_md);
eb1cbe48
DV		 4574 } else {
4575 /* The pixel multiplier can only be updated once the
4576 * DPLL is enabled and the clocks are stable.
4577 *
4578 * So write it again.
4579 */
4580 I915_WRITE(DPLL(pipe), dpll);
4581 }
4582}
4583
f47709a9 4584static void i8xx_update_pll(struct intel_crtc *crtc,
eb1cbe48 4585 struct drm_display_mode *adjusted_mode,
f47709a9 4586 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4587 int num_connectors)
4588{
f47709a9 4589 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4590 struct drm_i915_private *dev_priv = dev->dev_private;
dafd226c 4591 struct intel_encoder *encoder;
f47709a9 4592 int pipe = crtc->pipe;
eb1cbe48 4593 u32 dpll;
f47709a9 4594 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4595
f47709a9 4596 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4597
eb1cbe48
DV		 4598 dpll = DPLL_VGA_MODE_DIS;
4599
f47709a9 4600 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4601 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4602 } else {
4603 if (clock->p1 == 2)
4604 dpll |= PLL_P1_DIVIDE_BY_TWO;
4605 else
4606 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4607 if (clock->p2 == 4)
4608 dpll |= PLL_P2_DIVIDE_BY_4;
4609 }
4610
f47709a9 4611 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4612 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4613 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4614 else
4615 dpll |= PLL_REF_INPUT_DREFCLK;
4616
4617 dpll |= DPLL_VCO_ENABLE;
4618 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4619 POSTING_READ(DPLL(pipe));
4620 udelay(150);
4621
f47709a9 4622 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
dafd226c
DV		 4623 if (encoder->pre_pll_enable)
4624 encoder->pre_pll_enable(encoder);
eb1cbe48 4625
5b5896e4
DV		 4626 I915_WRITE(DPLL(pipe), dpll);
4627
4628 /* Wait for the clocks to stabilize. */
4629 POSTING_READ(DPLL(pipe));
4630 udelay(150);
4631
eb1cbe48
DV		 4632 /* The pixel multiplier can only be updated once the
4633 * DPLL is enabled and the clocks are stable.
4634 *
4635 * So write it again.
4636 */
4637 I915_WRITE(DPLL(pipe), dpll);
4638}
4639
b0e77b9c
PZ		 4640static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4641 struct drm_display_mode *mode,
4642 struct drm_display_mode *adjusted_mode)
4643{
4644 struct drm_device *dev = intel_crtc->base.dev;
4645 struct drm_i915_private *dev_priv = dev->dev_private;
4646 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4647 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
4d8a62ea
DV		 4648 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4649
4650 /* We need to be careful not to changed the adjusted mode, for otherwise
4651 * the hw state checker will get angry at the mismatch. */
4652 crtc_vtotal = adjusted_mode->crtc_vtotal;
4653 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4654
4655 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4656 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4657 crtc_vtotal -= 1;
4658 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4659 vsyncshift = adjusted_mode->crtc_hsync_start
4660 - adjusted_mode->crtc_htotal / 2;
4661 } else {
4662 vsyncshift = 0;
4663 }
4664
4665 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4666 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4667
fe2b8f9d 4668 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4669 (adjusted_mode->crtc_hdisplay - 1) |
4670 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4671 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4672 (adjusted_mode->crtc_hblank_start - 1) |
4673 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4674 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4675 (adjusted_mode->crtc_hsync_start - 1) |
4676 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4677
fe2b8f9d 4678 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4679 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4680 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4681 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4682 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4683 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4684 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4685 (adjusted_mode->crtc_vsync_start - 1) |
4686 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4687
b5e508d4
PZ		 4688 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4689 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4690 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4691 * bits. */
4692 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4693 (pipe == PIPE_B || pipe == PIPE_C))
4694 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4695
b0e77b9c
PZ		 4696 /* pipesrc controls the size that is scaled from, which should
4697 * always be the user's requested size.
4698 */
4699 I915_WRITE(PIPESRC(pipe),
4700 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4701}
4702
1bd1bd80
DV		 4703static void intel_get_pipe_timings(struct intel_crtc *crtc,
4704 struct intel_crtc_config *pipe_config)
4705{
4706 struct drm_device *dev = crtc->base.dev;
4707 struct drm_i915_private *dev_priv = dev->dev_private;
4708 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4709 uint32_t tmp;
4710
4711 tmp = I915_READ(HTOTAL(cpu_transcoder));
4712 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4713 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4714 tmp = I915_READ(HBLANK(cpu_transcoder));
4715 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4716 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4717 tmp = I915_READ(HSYNC(cpu_transcoder));
4718 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4719 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4720
4721 tmp = I915_READ(VTOTAL(cpu_transcoder));
4722 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4723 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4724 tmp = I915_READ(VBLANK(cpu_transcoder));
4725 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4726 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4727 tmp = I915_READ(VSYNC(cpu_transcoder));
4728 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4729 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4730
4731 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4732 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4733 pipe_config->adjusted_mode.crtc_vtotal += 1;
4734 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4735 }
4736
4737 tmp = I915_READ(PIPESRC(crtc->pipe));
4738 pipe_config->requested_mode.vdisplay = (tmp & 0xffff) + 1;
4739 pipe_config->requested_mode.hdisplay = ((tmp >> 16) & 0xffff) + 1;
4740}
4741
84b046f3
DV		 4742static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4743{
4744 struct drm_device *dev = intel_crtc->base.dev;
4745 struct drm_i915_private *dev_priv = dev->dev_private;
4746 uint32_t pipeconf;
4747
4748 pipeconf = I915_READ(PIPECONF(intel_crtc->pipe));
4749
4750 if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4751 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4752 * core speed.
4753 *
4754 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4755 * pipe == 0 check?
4756 */
4757 if (intel_crtc->config.requested_mode.clock >
4758 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4759 pipeconf |= PIPECONF_DOUBLE_WIDE;
4760 else
4761 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4762 }
4763
ff9ce46e
DV		 4764 /* only g4x and later have fancy bpc/dither controls */
4765 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
4766 pipeconf &= ~(PIPECONF_BPC_MASK |
4767 PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4768
4769 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4770 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
4771 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 4772 PIPECONF_DITHER_TYPE_SP;
84b046f3 4773
ff9ce46e
DV		 4774 switch (intel_crtc->config.pipe_bpp) {
4775 case 18:
4776 pipeconf |= PIPECONF_6BPC;
4777 break;
4778 case 24:
4779 pipeconf |= PIPECONF_8BPC;
4780 break;
4781 case 30:
4782 pipeconf |= PIPECONF_10BPC;
4783 break;
4784 default:
4785 /* Case prevented by intel_choose_pipe_bpp_dither. */
4786 BUG();
84b046f3
DV		 4787 }
4788 }
4789
4790 if (HAS_PIPE_CXSR(dev)) {
4791 if (intel_crtc->lowfreq_avail) {
4792 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4793 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4794 } else {
4795 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4796 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4797 }
4798 }
4799
4800 pipeconf &= ~PIPECONF_INTERLACE_MASK;
4801 if (!IS_GEN2(dev) &&
4802 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
4803 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4804 else
4805 pipeconf |= PIPECONF_PROGRESSIVE;
4806
9c8e09b7
VS		 4807 if (IS_VALLEYVIEW(dev)) {
4808 if (intel_crtc->config.limited_color_range)
4809 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
4810 else
4811 pipeconf &= ~PIPECONF_COLOR_RANGE_SELECT;
4812 }
4813
84b046f3
DV		 4814 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
4815 POSTING_READ(PIPECONF(intel_crtc->pipe));
4816}
4817
f564048e 4818static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 4819 int x, int y,
94352cf9 4820 struct drm_framebuffer *fb)
79e53945
JB		 4821{
4822 struct drm_device *dev = crtc->dev;
4823 struct drm_i915_private *dev_priv = dev->dev_private;
4824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 4825 struct drm_display_mode *adjusted_mode =
4826 &intel_crtc->config.adjusted_mode;
4827 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
79e53945 4828 int pipe = intel_crtc->pipe;
80824003 4829 int plane = intel_crtc->plane;
c751ce4f 4830 int refclk, num_connectors = 0;
652c393a 4831 intel_clock_t clock, reduced_clock;
84b046f3 4832 u32 dspcntr;
a16af721
DV		 4833 bool ok, has_reduced_clock = false;
4834 bool is_lvds = false;
5eddb70b 4835 struct intel_encoder *encoder;
d4906093 4836 const intel_limit_t *limit;
5c3b82e2 4837 int ret;
79e53945 4838
6c2b7c12 4839 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4840 switch (encoder->type) {
79e53945
JB		 4841 case INTEL_OUTPUT_LVDS:
4842 is_lvds = true;
4843 break;
79e53945 4844 }
43565a06 4845
c751ce4f 4846 num_connectors++;
79e53945
JB		 4847 }
4848
c65d77d8 4849 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4850
d4906093
ML		 4851 /*
4852 * Returns a set of divisors for the desired target clock with the given
4853 * refclk, or FALSE. The returned values represent the clock equation:
4854 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4855 */
1b894b59 4856 limit = intel_limit(crtc, refclk);
ee9300bb
DV		 4857 ok = dev_priv->display.find_dpll(limit, crtc, adjusted_mode->clock,
4858 refclk, NULL, &clock);
4859 if (!ok && !intel_crtc->config.clock_set) {
79e53945 4860 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4861 return -EINVAL;
79e53945
JB		 4862 }
4863
cda4b7d3 4864 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4865 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4866
ddc9003c 4867 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4868 /*
4869 * Ensure we match the reduced clock's P to the target clock.
4870 * If the clocks don't match, we can't switch the display clock
4871 * by using the FP0/FP1. In such case we will disable the LVDS
4872 * downclock feature.
4873 */
ee9300bb
DV		 4874 has_reduced_clock =
4875 dev_priv->display.find_dpll(limit, crtc,
5eddb70b 4876 dev_priv->lvds_downclock,
ee9300bb 4877 refclk, &clock,
5eddb70b 4878 &reduced_clock);
7026d4ac 4879 }
f47709a9
DV		 4880 /* Compat-code for transition, will disappear. */
4881 if (!intel_crtc->config.clock_set) {
4882 intel_crtc->config.dpll.n = clock.n;
4883 intel_crtc->config.dpll.m1 = clock.m1;
4884 intel_crtc->config.dpll.m2 = clock.m2;
4885 intel_crtc->config.dpll.p1 = clock.p1;
4886 intel_crtc->config.dpll.p2 = clock.p2;
4887 }
7026d4ac 4888
eb1cbe48 4889 if (IS_GEN2(dev))
f47709a9 4890 i8xx_update_pll(intel_crtc, adjusted_mode,
2a8f64ca
VP		 4891 has_reduced_clock ? &reduced_clock : NULL,
4892 num_connectors);
a0c4da24 4893 else if (IS_VALLEYVIEW(dev))
f47709a9 4894 vlv_update_pll(intel_crtc);
79e53945 4895 else
f47709a9 4896 i9xx_update_pll(intel_crtc,
eb1cbe48 4897 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 4898 num_connectors);
79e53945 4899
79e53945
JB		 4900 /* Set up the display plane register */
4901 dspcntr = DISPPLANE_GAMMA_ENABLE;
4902
da6ecc5d
JB		 4903 if (!IS_VALLEYVIEW(dev)) {
4904 if (pipe == 0)
4905 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4906 else
4907 dspcntr |= DISPPLANE_SEL_PIPE_B;
4908 }
79e53945 4909
b0e77b9c 4910 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4911
4912 /* pipesrc and dspsize control the size that is scaled from,
4913 * which should always be the user's requested size.
79e53945 4914 */
929c77fb
EA		 4915 I915_WRITE(DSPSIZE(plane),
4916 ((mode->vdisplay - 1) << 16) |
4917 (mode->hdisplay - 1));
4918 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4919
84b046f3
DV		 4920 i9xx_set_pipeconf(intel_crtc);
4921
f564048e
EA		 4922 I915_WRITE(DSPCNTR(plane), dspcntr);
4923 POSTING_READ(DSPCNTR(plane));
4924
94352cf9 4925 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4926
4927 intel_update_watermarks(dev);
4928
f564048e
EA		 4929 return ret;
4930}
4931
2fa2fe9a
DV		 4932static void i9xx_get_pfit_config(struct intel_crtc *crtc,
4933 struct intel_crtc_config *pipe_config)
4934{
4935 struct drm_device *dev = crtc->base.dev;
4936 struct drm_i915_private *dev_priv = dev->dev_private;
4937 uint32_t tmp;
4938
4939 tmp = I915_READ(PFIT_CONTROL);
4940
4941 if (INTEL_INFO(dev)->gen < 4) {
4942 if (crtc->pipe != PIPE_B)
4943 return;
4944
4945 /* gen2/3 store dither state in pfit control, needs to match */
4946 pipe_config->gmch_pfit.control = tmp & PANEL_8TO6_DITHER_ENABLE;
4947 } else {
4948 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
4949 return;
4950 }
4951
4952 if (!(tmp & PFIT_ENABLE))
4953 return;
4954
4955 pipe_config->gmch_pfit.control = I915_READ(PFIT_CONTROL);
4956 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
4957 if (INTEL_INFO(dev)->gen < 5)
4958 pipe_config->gmch_pfit.lvds_border_bits =
4959 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
4960}
4961
0e8ffe1b
DV		 4962static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
4963 struct intel_crtc_config *pipe_config)
4964{
4965 struct drm_device *dev = crtc->base.dev;
4966 struct drm_i915_private *dev_priv = dev->dev_private;
4967 uint32_t tmp;
4968
eccb140b
DV		 4969 pipe_config->cpu_transcoder = crtc->pipe;
4970
0e8ffe1b
DV		 4971 tmp = I915_READ(PIPECONF(crtc->pipe));
4972 if (!(tmp & PIPECONF_ENABLE))
4973 return false;
4974
1bd1bd80
DV		 4975 intel_get_pipe_timings(crtc, pipe_config);
4976
2fa2fe9a
DV		 4977 i9xx_get_pfit_config(crtc, pipe_config);
4978
0e8ffe1b
DV		 4979 return true;
4980}
4981
dde86e2d 4982static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4983{
4984 struct drm_i915_private *dev_priv = dev->dev_private;
4985 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4986 struct intel_encoder *encoder;
74cfd7ac 4987 u32 val, final;
13d83a67 4988 bool has_lvds = false;
199e5d79 4989 bool has_cpu_edp = false;
199e5d79 4990 bool has_panel = false;
99eb6a01
KP		 4991 bool has_ck505 = false;
4992 bool can_ssc = false;
13d83a67
JB		 4993
4994 /* We need to take the global config into account */
199e5d79
KP		 4995 list_for_each_entry(encoder, &mode_config->encoder_list,
4996 base.head) {
4997 switch (encoder->type) {
4998 case INTEL_OUTPUT_LVDS:
4999 has_panel = true;
5000 has_lvds = true;
5001 break;
5002 case INTEL_OUTPUT_EDP:
5003 has_panel = true;
2de6905f 5004 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5005 has_cpu_edp = true;
5006 break;
13d83a67
JB		 5007 }
5008 }
5009
99eb6a01 5010 if (HAS_PCH_IBX(dev)) {
41aa3448 5011 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5012 can_ssc = has_ck505;
5013 } else {
5014 has_ck505 = false;
5015 can_ssc = true;
5016 }
5017
2de6905f
ID		 5018 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5019 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5020
5021 /* Ironlake: try to setup display ref clock before DPLL
5022 * enabling. This is only under driver's control after
5023 * PCH B stepping, previous chipset stepping should be
5024 * ignoring this setting.
5025 */
74cfd7ac
CW		 5026 val = I915_READ(PCH_DREF_CONTROL);
5027
5028 /* As we must carefully and slowly disable/enable each source in turn,
5029 * compute the final state we want first and check if we need to
5030 * make any changes at all.
5031 */
5032 final = val;
5033 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5034 if (has_ck505)
5035 final |= DREF_NONSPREAD_CK505_ENABLE;
5036 else
5037 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5038
5039 final &= ~DREF_SSC_SOURCE_MASK;
5040 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5041 final &= ~DREF_SSC1_ENABLE;
5042
5043 if (has_panel) {
5044 final |= DREF_SSC_SOURCE_ENABLE;
5045
5046 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5047 final |= DREF_SSC1_ENABLE;
5048
5049 if (has_cpu_edp) {
5050 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5051 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5052 else
5053 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5054 } else
5055 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5056 } else {
5057 final |= DREF_SSC_SOURCE_DISABLE;
5058 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5059 }
5060
5061 if (final == val)
5062 return;
5063
13d83a67 5064 /* Always enable nonspread source */
74cfd7ac 5065 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5066
99eb6a01 5067 if (has_ck505)
74cfd7ac 5068 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5069 else
74cfd7ac 5070 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5071
199e5d79 5072 if (has_panel) {
74cfd7ac
CW		 5073 val &= ~DREF_SSC_SOURCE_MASK;
5074 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5075
199e5d79 5076 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5077 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5078 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5079 val |= DREF_SSC1_ENABLE;
e77166b5 5080 } else
74cfd7ac 5081 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5082
5083 /* Get SSC going before enabling the outputs */
74cfd7ac 5084 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5085 POSTING_READ(PCH_DREF_CONTROL);
5086 udelay(200);
5087
74cfd7ac 5088 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5089
5090 /* Enable CPU source on CPU attached eDP */
199e5d79 5091 if (has_cpu_edp) {
99eb6a01 5092 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5093 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5094 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5095 }
13d83a67 5096 else
74cfd7ac 5097 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5098 } else
74cfd7ac 5099 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5100
74cfd7ac 5101 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5102 POSTING_READ(PCH_DREF_CONTROL);
5103 udelay(200);
5104 } else {
5105 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5106
74cfd7ac 5107 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5108
5109 /* Turn off CPU output */
74cfd7ac 5110 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5111
74cfd7ac 5112 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5113 POSTING_READ(PCH_DREF_CONTROL);
5114 udelay(200);
5115
5116 /* Turn off the SSC source */
74cfd7ac
CW		 5117 val &= ~DREF_SSC_SOURCE_MASK;
5118 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5119
5120 /* Turn off SSC1 */
74cfd7ac 5121 val &= ~DREF_SSC1_ENABLE;
199e5d79 5122
74cfd7ac 5123 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5124 POSTING_READ(PCH_DREF_CONTROL);
5125 udelay(200);
5126 }
74cfd7ac
CW		 5127
5128 BUG_ON(val != final);
13d83a67
JB		 5129}
5130
dde86e2d
PZ		 5131/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
5132static void lpt_init_pch_refclk(struct drm_device *dev)
5133{
5134 struct drm_i915_private *dev_priv = dev->dev_private;
5135 struct drm_mode_config *mode_config = &dev->mode_config;
5136 struct intel_encoder *encoder;
5137 bool has_vga = false;
5138 bool is_sdv = false;
5139 u32 tmp;
5140
5141 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5142 switch (encoder->type) {
5143 case INTEL_OUTPUT_ANALOG:
5144 has_vga = true;
5145 break;
5146 }
5147 }
5148
5149 if (!has_vga)
5150 return;
5151
c00db246
DV		 5152 mutex_lock(&dev_priv->dpio_lock);
5153
dde86e2d
PZ		 5154 /* XXX: Rip out SDV support once Haswell ships for real. */
5155 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
5156 is_sdv = true;
5157
5158 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5159 tmp &= ~SBI_SSCCTL_DISABLE;
5160 tmp |= SBI_SSCCTL_PATHALT;
5161 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5162
5163 udelay(24);
5164
5165 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5166 tmp &= ~SBI_SSCCTL_PATHALT;
5167 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5168
5169 if (!is_sdv) {
5170 tmp = I915_READ(SOUTH_CHICKEN2);
5171 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5172 I915_WRITE(SOUTH_CHICKEN2, tmp);
5173
5174 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5175 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5176 DRM_ERROR("FDI mPHY reset assert timeout\n");
5177
5178 tmp = I915_READ(SOUTH_CHICKEN2);
5179 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5180 I915_WRITE(SOUTH_CHICKEN2, tmp);
5181
5182 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5183 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
5184 100))
5185 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
5186 }
5187
5188 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5189 tmp &= ~(0xFF << 24);
5190 tmp |= (0x12 << 24);
5191 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5192
dde86e2d
PZ		 5193 if (is_sdv) {
5194 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
5195 tmp |= 0x7FFF;
5196 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
5197 }
5198
5199 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5200 tmp |= (1 << 11);
5201 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5202
5203 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5204 tmp |= (1 << 11);
5205 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5206
5207 if (is_sdv) {
5208 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
5209 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5210 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
5211
5212 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
5213 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
5214 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
5215
5216 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
5217 tmp |= (0x3F << 8);
5218 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
5219
5220 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
5221 tmp |= (0x3F << 8);
5222 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
5223 }
5224
5225 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5226 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5227 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5228
5229 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5230 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5231 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5232
5233 if (!is_sdv) {
5234 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5235 tmp &= ~(7 << 13);
5236 tmp |= (5 << 13);
5237 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
5238
5239 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5240 tmp &= ~(7 << 13);
5241 tmp |= (5 << 13);
5242 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
5243 }
5244
5245 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5246 tmp &= ~0xFF;
5247 tmp |= 0x1C;
5248 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5249
5250 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5251 tmp &= ~0xFF;
5252 tmp |= 0x1C;
5253 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5254
5255 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5256 tmp &= ~(0xFF << 16);
5257 tmp |= (0x1C << 16);
5258 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5259
5260 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5261 tmp &= ~(0xFF << 16);
5262 tmp |= (0x1C << 16);
5263 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5264
5265 if (!is_sdv) {
5266 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5267 tmp |= (1 << 27);
5268 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5269
5270 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5271 tmp |= (1 << 27);
5272 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5273
5274 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5275 tmp &= ~(0xF << 28);
5276 tmp |= (4 << 28);
5277 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5278
5279 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5280 tmp &= ~(0xF << 28);
5281 tmp |= (4 << 28);
5282 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5283 }
5284
5285 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5286 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5287 tmp |= SBI_DBUFF0_ENABLE;
5288 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5289
5290 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5291}
5292
5293/*
5294 * Initialize reference clocks when the driver loads
5295 */
5296void intel_init_pch_refclk(struct drm_device *dev)
5297{
5298 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5299 ironlake_init_pch_refclk(dev);
5300 else if (HAS_PCH_LPT(dev))
5301 lpt_init_pch_refclk(dev);
5302}
5303
d9d444cb
JB		 5304static int ironlake_get_refclk(struct drm_crtc *crtc)
5305{
5306 struct drm_device *dev = crtc->dev;
5307 struct drm_i915_private *dev_priv = dev->dev_private;
5308 struct intel_encoder *encoder;
d9d444cb
JB		 5309 int num_connectors = 0;
5310 bool is_lvds = false;
5311
6c2b7c12 5312 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5313 switch (encoder->type) {
5314 case INTEL_OUTPUT_LVDS:
5315 is_lvds = true;
5316 break;
d9d444cb
JB		 5317 }
5318 num_connectors++;
5319 }
5320
5321 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5322 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5323 dev_priv->vbt.lvds_ssc_freq);
5324 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5325 }
5326
5327 return 120000;
5328}
5329
6ff93609 5330static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5331{
c8203565 5332 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5333 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5334 int pipe = intel_crtc->pipe;
c8203565
PZ		 5335 uint32_t val;
5336
5337 val = I915_READ(PIPECONF(pipe));
5338
dfd07d72 5339 val &= ~PIPECONF_BPC_MASK;
965e0c48 5340 switch (intel_crtc->config.pipe_bpp) {
c8203565 5341 case 18:
dfd07d72 5342 val |= PIPECONF_6BPC;
c8203565
PZ		 5343 break;
5344 case 24:
dfd07d72 5345 val |= PIPECONF_8BPC;
c8203565
PZ		 5346 break;
5347 case 30:
dfd07d72 5348 val |= PIPECONF_10BPC;
c8203565
PZ		 5349 break;
5350 case 36:
dfd07d72 5351 val |= PIPECONF_12BPC;
c8203565
PZ		 5352 break;
5353 default:
cc769b62
PZ		 5354 /* Case prevented by intel_choose_pipe_bpp_dither. */
5355 BUG();
c8203565
PZ		 5356 }
5357
5358 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5359 if (intel_crtc->config.dither)
c8203565
PZ		 5360 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5361
5362 val &= ~PIPECONF_INTERLACE_MASK;
6ff93609 5363 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5364 val |= PIPECONF_INTERLACED_ILK;
5365 else
5366 val |= PIPECONF_PROGRESSIVE;
5367
50f3b016 5368 if (intel_crtc->config.limited_color_range)
3685a8f3
VS		 5369 val |= PIPECONF_COLOR_RANGE_SELECT;
5370 else
5371 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5372
c8203565
PZ		 5373 I915_WRITE(PIPECONF(pipe), val);
5374 POSTING_READ(PIPECONF(pipe));
5375}
5376
86d3efce
VS		 5377/*
5378 * Set up the pipe CSC unit.
5379 *
5380 * Currently only full range RGB to limited range RGB conversion
5381 * is supported, but eventually this should handle various
5382 * RGB<->YCbCr scenarios as well.
5383 */
50f3b016 5384static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5385{
5386 struct drm_device *dev = crtc->dev;
5387 struct drm_i915_private *dev_priv = dev->dev_private;
5388 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5389 int pipe = intel_crtc->pipe;
5390 uint16_t coeff = 0x7800; /* 1.0 */
5391
5392 /*
5393 * TODO: Check what kind of values actually come out of the pipe
5394 * with these coeff/postoff values and adjust to get the best
5395 * accuracy. Perhaps we even need to take the bpc value into
5396 * consideration.
5397 */
5398
50f3b016 5399 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5400 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5401
5402 /*
5403 * GY/GU and RY/RU should be the other way around according
5404 * to BSpec, but reality doesn't agree. Just set them up in
5405 * a way that results in the correct picture.
5406 */
5407 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5408 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5409
5410 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5411 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5412
5413 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5414 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5415
5416 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5417 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5418 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5419
5420 if (INTEL_INFO(dev)->gen > 6) {
5421 uint16_t postoff = 0;
5422
50f3b016 5423 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5424 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5425
5426 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5427 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5428 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5429
5430 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5431 } else {
5432 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5433
50f3b016 5434 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5435 mode |= CSC_BLACK_SCREEN_OFFSET;
5436
5437 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5438 }
5439}
5440
6ff93609 5441static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5442{
5443 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5444 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5445 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5446 uint32_t val;
5447
702e7a56 5448 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5449
5450 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
d8b32247 5451 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5452 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5453
5454 val &= ~PIPECONF_INTERLACE_MASK_HSW;
6ff93609 5455 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5456 val |= PIPECONF_INTERLACED_ILK;
5457 else
5458 val |= PIPECONF_PROGRESSIVE;
5459
702e7a56
PZ		 5460 I915_WRITE(PIPECONF(cpu_transcoder), val);
5461 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5462}
5463
6591c6e4
PZ		 5464static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5465 struct drm_display_mode *adjusted_mode,
5466 intel_clock_t *clock,
5467 bool *has_reduced_clock,
5468 intel_clock_t *reduced_clock)
5469{
5470 struct drm_device *dev = crtc->dev;
5471 struct drm_i915_private *dev_priv = dev->dev_private;
5472 struct intel_encoder *intel_encoder;
5473 int refclk;
d4906093 5474 const intel_limit_t *limit;
a16af721 5475 bool ret, is_lvds = false;
79e53945 5476
6591c6e4
PZ		 5477 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5478 switch (intel_encoder->type) {
79e53945
JB		 5479 case INTEL_OUTPUT_LVDS:
5480 is_lvds = true;
5481 break;
79e53945
JB		 5482 }
5483 }
5484
d9d444cb 5485 refclk = ironlake_get_refclk(crtc);
79e53945 5486
d4906093
ML		 5487 /*
5488 * Returns a set of divisors for the desired target clock with the given
5489 * refclk, or FALSE. The returned values represent the clock equation:
5490 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5491 */
1b894b59 5492 limit = intel_limit(crtc, refclk);
ee9300bb
DV		 5493 ret = dev_priv->display.find_dpll(limit, crtc, adjusted_mode->clock,
5494 refclk, NULL, clock);
6591c6e4
PZ		 5495 if (!ret)
5496 return false;
cda4b7d3 5497
ddc9003c 5498 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5499 /*
5500 * Ensure we match the reduced clock's P to the target clock.
5501 * If the clocks don't match, we can't switch the display clock
5502 * by using the FP0/FP1. In such case we will disable the LVDS
5503 * downclock feature.
5504 */
ee9300bb
DV		 5505 *has_reduced_clock =
5506 dev_priv->display.find_dpll(limit, crtc,
5507 dev_priv->lvds_downclock,
5508 refclk, clock,
5509 reduced_clock);
652c393a 5510 }
61e9653f 5511
6591c6e4
PZ		 5512 return true;
5513}
5514
01a415fd
DV		 5515static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5516{
5517 struct drm_i915_private *dev_priv = dev->dev_private;
5518 uint32_t temp;
5519
5520 temp = I915_READ(SOUTH_CHICKEN1);
5521 if (temp & FDI_BC_BIFURCATION_SELECT)
5522 return;
5523
5524 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5525 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5526
5527 temp |= FDI_BC_BIFURCATION_SELECT;
5528 DRM_DEBUG_KMS("enabling fdi C rx\n");
5529 I915_WRITE(SOUTH_CHICKEN1, temp);
5530 POSTING_READ(SOUTH_CHICKEN1);
5531}
5532
ebfd86fd
DV		 5533static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
5534{
5535 struct drm_device *dev = intel_crtc->base.dev;
5536 struct drm_i915_private *dev_priv = dev->dev_private;
5537
5538 switch (intel_crtc->pipe) {
5539 case PIPE_A:
5540 break;
5541 case PIPE_B:
5542 if (intel_crtc->config.fdi_lanes > 2)
5543 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5544 else
5545 cpt_enable_fdi_bc_bifurcation(dev);
5546
5547 break;
5548 case PIPE_C:
01a415fd
DV		 5549 cpt_enable_fdi_bc_bifurcation(dev);
5550
ebfd86fd 5551 break;
01a415fd
DV		 5552 default:
5553 BUG();
5554 }
5555}
5556
d4b1931c
PZ		 5557int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5558{
5559 /*
5560 * Account for spread spectrum to avoid
5561 * oversubscribing the link. Max center spread
5562 * is 2.5%; use 5% for safety's sake.
5563 */
5564 u32 bps = target_clock * bpp * 21 / 20;
5565 return bps / (link_bw * 8) + 1;
5566}
5567
7429e9d4
DV		 5568static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
5569{
5570 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
5571}
5572
de13a2e3 5573static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5574 u32 *fp,
9a7c7890 5575 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5576{
de13a2e3 5577 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5578 struct drm_device *dev = crtc->dev;
5579 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5580 struct intel_encoder *intel_encoder;
5581 uint32_t dpll;
6cc5f341 5582 int factor, num_connectors = 0;
09ede541 5583 bool is_lvds = false, is_sdvo = false;
79e53945 5584
de13a2e3
PZ		 5585 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5586 switch (intel_encoder->type) {
79e53945
JB		 5587 case INTEL_OUTPUT_LVDS:
5588 is_lvds = true;
5589 break;
5590 case INTEL_OUTPUT_SDVO:
7d57382e 5591 case INTEL_OUTPUT_HDMI:
79e53945
JB		 5592 is_sdvo = true;
5593 break;
79e53945 5594 }
43565a06 5595
c751ce4f 5596 num_connectors++;
79e53945 5597 }
79e53945 5598
c1858123 5599 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5600 factor = 21;
5601 if (is_lvds) {
5602 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5603 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5604 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5605 factor = 25;
09ede541 5606 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5607 factor = 20;
c1858123 5608
7429e9d4 5609 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5610 *fp |= FP_CB_TUNE;
2c07245f 5611
9a7c7890
DV		 5612 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5613 *fp2 |= FP_CB_TUNE;
5614
5eddb70b 5615 dpll = 0;
2c07245f 5616
a07d6787
EA		 5617 if (is_lvds)
5618 dpll |= DPLLB_MODE_LVDS;
5619 else
5620 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f
DV		 5621
5622 if (intel_crtc->config.pixel_multiplier > 1) {
5623 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5624 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
a07d6787 5625 }
198a037f
DV		 5626
5627 if (is_sdvo)
5628 dpll |= DPLL_DVO_HIGH_SPEED;
9566e9af 5629 if (intel_crtc->config.has_dp_encoder)
a07d6787 5630 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5631
a07d6787 5632 /* compute bitmask from p1 value */
7429e9d4 5633 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5634 /* also FPA1 */
7429e9d4 5635 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5636
7429e9d4 5637 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5638 case 5:
5639 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5640 break;
5641 case 7:
5642 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5643 break;
5644 case 10:
5645 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5646 break;
5647 case 14:
5648 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5649 break;
79e53945
JB		 5650 }
5651
b4c09f3b 5652 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5653 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5654 else
5655 dpll |= PLL_REF_INPUT_DREFCLK;
5656
de13a2e3
PZ		 5657 return dpll;
5658}
5659
5660static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5661 int x, int y,
5662 struct drm_framebuffer *fb)
5663{
5664 struct drm_device *dev = crtc->dev;
5665 struct drm_i915_private *dev_priv = dev->dev_private;
5666 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5667 struct drm_display_mode *adjusted_mode =
5668 &intel_crtc->config.adjusted_mode;
5669 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
de13a2e3
PZ		 5670 int pipe = intel_crtc->pipe;
5671 int plane = intel_crtc->plane;
5672 int num_connectors = 0;
5673 intel_clock_t clock, reduced_clock;
cbbab5bd 5674 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5675 bool ok, has_reduced_clock = false;
8b47047b 5676 bool is_lvds = false;
de13a2e3 5677 struct intel_encoder *encoder;
de13a2e3 5678 int ret;
de13a2e3
PZ		 5679
5680 for_each_encoder_on_crtc(dev, crtc, encoder) {
5681 switch (encoder->type) {
5682 case INTEL_OUTPUT_LVDS:
5683 is_lvds = true;
5684 break;
de13a2e3
PZ		 5685 }
5686
5687 num_connectors++;
a07d6787 5688 }
79e53945 5689
5dc5298b
PZ		 5690 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5691 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5692
de13a2e3
PZ		 5693 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5694 &has_reduced_clock, &reduced_clock);
ee9300bb 5695 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 5696 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5697 return -EINVAL;
79e53945 5698 }
f47709a9
DV		 5699 /* Compat-code for transition, will disappear. */
5700 if (!intel_crtc->config.clock_set) {
5701 intel_crtc->config.dpll.n = clock.n;
5702 intel_crtc->config.dpll.m1 = clock.m1;
5703 intel_crtc->config.dpll.m2 = clock.m2;
5704 intel_crtc->config.dpll.p1 = clock.p1;
5705 intel_crtc->config.dpll.p2 = clock.p2;
5706 }
79e53945 5707
de13a2e3
PZ		 5708 /* Ensure that the cursor is valid for the new mode before changing... */
5709 intel_crtc_update_cursor(crtc, true);
5710
5dc5298b 5711 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 5712 if (intel_crtc->config.has_pch_encoder) {
ee7b9f93 5713 struct intel_pch_pll *pll;
4b645f14 5714
7429e9d4 5715 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 5716 if (has_reduced_clock)
7429e9d4 5717 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 5718
7429e9d4 5719 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 5720 &fp, &reduced_clock,
5721 has_reduced_clock ? &fp2 : NULL);
5722
ee7b9f93
JB		 5723 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5724 if (pll == NULL) {
84f44ce7
VS		 5725 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
5726 pipe_name(pipe));
4b645f14
JB		 5727 return -EINVAL;
5728 }
ee7b9f93
JB		 5729 } else
5730 intel_put_pch_pll(intel_crtc);
79e53945 5731
03afc4a2
DV		 5732 if (intel_crtc->config.has_dp_encoder)
5733 intel_dp_set_m_n(intel_crtc);
79e53945 5734
dafd226c
DV		 5735 for_each_encoder_on_crtc(dev, crtc, encoder)
5736 if (encoder->pre_pll_enable)
5737 encoder->pre_pll_enable(encoder);
79e53945 5738
ee7b9f93
JB		 5739 if (intel_crtc->pch_pll) {
5740 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5741
32f9d658 5742 /* Wait for the clocks to stabilize. */
ee7b9f93 5743 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5744 udelay(150);
5745
8febb297
EA		 5746 /* The pixel multiplier can only be updated once the
5747 * DPLL is enabled and the clocks are stable.
5748 *
5749 * So write it again.
5750 */
ee7b9f93 5751 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5752 }
79e53945 5753
5eddb70b 5754 intel_crtc->lowfreq_avail = false;
ee7b9f93 5755 if (intel_crtc->pch_pll) {
4b645f14 5756 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5757 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5758 intel_crtc->lowfreq_avail = true;
4b645f14 5759 } else {
ee7b9f93 5760 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5761 }
5762 }
5763
b0e77b9c 5764 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5765
ca3a0ff8 5766 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5767 intel_cpu_transcoder_set_m_n(intel_crtc,
5768 &intel_crtc->config.fdi_m_n);
5769 }
2c07245f 5770
ebfd86fd
DV		 5771 if (IS_IVYBRIDGE(dev))
5772 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
2c07245f 5773
6ff93609 5774 ironlake_set_pipeconf(crtc);
79e53945 5775
a1f9e77e
PZ		 5776 /* Set up the display plane register */
5777 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5778 POSTING_READ(DSPCNTR(plane));
79e53945 5779
94352cf9 5780 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5781
5782 intel_update_watermarks(dev);
5783
1857e1da 5784 return ret;
79e53945
JB		 5785}
5786
72419203
DV		 5787static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5788 struct intel_crtc_config *pipe_config)
5789{
5790 struct drm_device *dev = crtc->base.dev;
5791 struct drm_i915_private *dev_priv = dev->dev_private;
5792 enum transcoder transcoder = pipe_config->cpu_transcoder;
5793
5794 pipe_config->fdi_m_n.link_m = I915_READ(PIPE_LINK_M1(transcoder));
5795 pipe_config->fdi_m_n.link_n = I915_READ(PIPE_LINK_N1(transcoder));
5796 pipe_config->fdi_m_n.gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
5797 & ~TU_SIZE_MASK;
5798 pipe_config->fdi_m_n.gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
5799 pipe_config->fdi_m_n.tu = ((I915_READ(PIPE_DATA_M1(transcoder))
5800 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
5801}
5802
2fa2fe9a
DV		 5803static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5804 struct intel_crtc_config *pipe_config)
5805{
5806 struct drm_device *dev = crtc->base.dev;
5807 struct drm_i915_private *dev_priv = dev->dev_private;
5808 uint32_t tmp;
5809
5810 tmp = I915_READ(PF_CTL(crtc->pipe));
5811
5812 if (tmp & PF_ENABLE) {
5813 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
5814 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
5815 }
5816}
5817
0e8ffe1b
DV		 5818static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5819 struct intel_crtc_config *pipe_config)
5820{
5821 struct drm_device *dev = crtc->base.dev;
5822 struct drm_i915_private *dev_priv = dev->dev_private;
5823 uint32_t tmp;
5824
eccb140b
DV		 5825 pipe_config->cpu_transcoder = crtc->pipe;
5826
0e8ffe1b
DV		 5827 tmp = I915_READ(PIPECONF(crtc->pipe));
5828 if (!(tmp & PIPECONF_ENABLE))
5829 return false;
5830
ab9412ba 5831 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
88adfff1
DV		 5832 pipe_config->has_pch_encoder = true;
5833
627eb5a3
DV		 5834 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
5835 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5836 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5837
5838 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5839 }
5840
1bd1bd80
DV		 5841 intel_get_pipe_timings(crtc, pipe_config);
5842
2fa2fe9a
DV		 5843 ironlake_get_pfit_config(crtc, pipe_config);
5844
0e8ffe1b
DV		 5845 return true;
5846}
5847
d6dd9eb1
DV		 5848static void haswell_modeset_global_resources(struct drm_device *dev)
5849{
d6dd9eb1
DV		 5850 bool enable = false;
5851 struct intel_crtc *crtc;
d6dd9eb1
DV		 5852
5853 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 5854 if (!crtc->base.enabled)
5855 continue;
d6dd9eb1 5856
e7a639c4
DV		 5857 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.size ||
5858 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 5859 enable = true;
5860 }
5861
d6dd9eb1
DV		 5862 intel_set_power_well(dev, enable);
5863}
5864
09b4ddf9 5865static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 5866 int x, int y,
5867 struct drm_framebuffer *fb)
5868{
5869 struct drm_device *dev = crtc->dev;
5870 struct drm_i915_private *dev_priv = dev->dev_private;
5871 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 5872 struct drm_display_mode *adjusted_mode =
5873 &intel_crtc->config.adjusted_mode;
5874 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
09b4ddf9
PZ		 5875 int pipe = intel_crtc->pipe;
5876 int plane = intel_crtc->plane;
5877 int num_connectors = 0;
8b47047b 5878 bool is_cpu_edp = false;
09b4ddf9 5879 struct intel_encoder *encoder;
09b4ddf9 5880 int ret;
09b4ddf9
PZ		 5881
5882 for_each_encoder_on_crtc(dev, crtc, encoder) {
5883 switch (encoder->type) {
09b4ddf9 5884 case INTEL_OUTPUT_EDP:
d8e8b582 5885 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
09b4ddf9
PZ		 5886 is_cpu_edp = true;
5887 break;
5888 }
5889
5890 num_connectors++;
5891 }
5892
5dc5298b
PZ		 5893 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5894 num_connectors, pipe_name(pipe));
5895
6441ab5f
PZ		 5896 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5897 return -EINVAL;
5898
09b4ddf9
PZ		 5899 /* Ensure that the cursor is valid for the new mode before changing... */
5900 intel_crtc_update_cursor(crtc, true);
5901
03afc4a2
DV		 5902 if (intel_crtc->config.has_dp_encoder)
5903 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 5904
5905 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5906
5907 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5908
ca3a0ff8 5909 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 5910 intel_cpu_transcoder_set_m_n(intel_crtc,
5911 &intel_crtc->config.fdi_m_n);
5912 }
09b4ddf9 5913
6ff93609 5914 haswell_set_pipeconf(crtc);
09b4ddf9 5915
50f3b016 5916 intel_set_pipe_csc(crtc);
86d3efce 5917
09b4ddf9 5918 /* Set up the display plane register */
86d3efce 5919 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 5920 POSTING_READ(DSPCNTR(plane));
5921
5922 ret = intel_pipe_set_base(crtc, x, y, fb);
5923
5924 intel_update_watermarks(dev);
5925
1f803ee5 5926 return ret;
79e53945
JB		 5927}
5928
0e8ffe1b
DV		 5929static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5930 struct intel_crtc_config *pipe_config)
5931{
5932 struct drm_device *dev = crtc->base.dev;
5933 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 5934 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 5935 uint32_t tmp;
5936
eccb140b
DV		 5937 pipe_config->cpu_transcoder = crtc->pipe;
5938 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
5939 if (tmp & TRANS_DDI_FUNC_ENABLE) {
5940 enum pipe trans_edp_pipe;
5941 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
5942 default:
5943 WARN(1, "unknown pipe linked to edp transcoder\n");
5944 case TRANS_DDI_EDP_INPUT_A_ONOFF:
5945 case TRANS_DDI_EDP_INPUT_A_ON:
5946 trans_edp_pipe = PIPE_A;
5947 break;
5948 case TRANS_DDI_EDP_INPUT_B_ONOFF:
5949 trans_edp_pipe = PIPE_B;
5950 break;
5951 case TRANS_DDI_EDP_INPUT_C_ONOFF:
5952 trans_edp_pipe = PIPE_C;
5953 break;
5954 }
5955
5956 if (trans_edp_pipe == crtc->pipe)
5957 pipe_config->cpu_transcoder = TRANSCODER_EDP;
5958 }
5959
b97186f0 5960 if (!intel_display_power_enabled(dev,
eccb140b 5961 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 5962 return false;
5963
eccb140b 5964 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 5965 if (!(tmp & PIPECONF_ENABLE))
5966 return false;
5967
88adfff1 5968 /*
f196e6be 5969 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 5970 * DDI E. So just check whether this pipe is wired to DDI E and whether
5971 * the PCH transcoder is on.
5972 */
eccb140b 5973 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 5974 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 5975 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 5976 pipe_config->has_pch_encoder = true;
5977
627eb5a3
DV		 5978 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
5979 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
5980 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 5981
5982 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 5983 }
5984
1bd1bd80
DV		 5985 intel_get_pipe_timings(crtc, pipe_config);
5986
2fa2fe9a
DV		 5987 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
5988 if (intel_display_power_enabled(dev, pfit_domain))
5989 ironlake_get_pfit_config(crtc, pipe_config);
5990
42db64ef
PZ		 5991 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
5992 (I915_READ(IPS_CTL) & IPS_ENABLE);
5993
0e8ffe1b
DV		 5994 return true;
5995}
5996
f564048e 5997static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5998 int x, int y,
94352cf9 5999 struct drm_framebuffer *fb)
f564048e
EA		 6000{
6001 struct drm_device *dev = crtc->dev;
6002 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 6003 struct drm_encoder_helper_funcs *encoder_funcs;
6004 struct intel_encoder *encoder;
0b701d27 6005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5
DV		 6006 struct drm_display_mode *adjusted_mode =
6007 &intel_crtc->config.adjusted_mode;
6008 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6009 int pipe = intel_crtc->pipe;
f564048e
EA		 6010 int ret;
6011
0b701d27 6012 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6013
b8cecdf5
DV		 6014 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6015
79e53945 6016 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6017
9256aa19
DV		 6018 if (ret != 0)
6019 return ret;
6020
6021 for_each_encoder_on_crtc(dev, crtc, encoder) {
6022 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6023 encoder->base.base.id,
6024 drm_get_encoder_name(&encoder->base),
6025 mode->base.id, mode->name);
6cc5f341
DV		 6026 if (encoder->mode_set) {
6027 encoder->mode_set(encoder);
6028 } else {
6029 encoder_funcs = encoder->base.helper_private;
6030 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
6031 }
9256aa19
DV		 6032 }
6033
6034 return 0;
79e53945
JB		 6035}
6036
3a9627f4
WF		 6037static bool intel_eld_uptodate(struct drm_connector *connector,
6038 int reg_eldv, uint32_t bits_eldv,
6039 int reg_elda, uint32_t bits_elda,
6040 int reg_edid)
6041{
6042 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6043 uint8_t *eld = connector->eld;
6044 uint32_t i;
6045
6046 i = I915_READ(reg_eldv);
6047 i &= bits_eldv;
6048
6049 if (!eld[0])
6050 return !i;
6051
6052 if (!i)
6053 return false;
6054
6055 i = I915_READ(reg_elda);
6056 i &= ~bits_elda;
6057 I915_WRITE(reg_elda, i);
6058
6059 for (i = 0; i < eld[2]; i++)
6060 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6061 return false;
6062
6063 return true;
6064}
6065
e0dac65e
WF		 6066static void g4x_write_eld(struct drm_connector *connector,
6067 struct drm_crtc *crtc)
6068{
6069 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6070 uint8_t *eld = connector->eld;
6071 uint32_t eldv;
6072 uint32_t len;
6073 uint32_t i;
6074
6075 i = I915_READ(G4X_AUD_VID_DID);
6076
6077 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6078 eldv = G4X_ELDV_DEVCL_DEVBLC;
6079 else
6080 eldv = G4X_ELDV_DEVCTG;
6081
3a9627f4
WF		 6082 if (intel_eld_uptodate(connector,
6083 G4X_AUD_CNTL_ST, eldv,
6084 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6085 G4X_HDMIW_HDMIEDID))
6086 return;
6087
e0dac65e
WF		 6088 i = I915_READ(G4X_AUD_CNTL_ST);
6089 i &= ~(eldv | G4X_ELD_ADDR);
6090 len = (i >> 9) & 0x1f; /* ELD buffer size */
6091 I915_WRITE(G4X_AUD_CNTL_ST, i);
6092
6093 if (!eld[0])
6094 return;
6095
6096 len = min_t(uint8_t, eld[2], len);
6097 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6098 for (i = 0; i < len; i++)
6099 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6100
6101 i = I915_READ(G4X_AUD_CNTL_ST);
6102 i |= eldv;
6103 I915_WRITE(G4X_AUD_CNTL_ST, i);
6104}
6105
83358c85
WX		 6106static void haswell_write_eld(struct drm_connector *connector,
6107 struct drm_crtc *crtc)
6108{
6109 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6110 uint8_t *eld = connector->eld;
6111 struct drm_device *dev = crtc->dev;
7b9f35a6 6112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6113 uint32_t eldv;
6114 uint32_t i;
6115 int len;
6116 int pipe = to_intel_crtc(crtc)->pipe;
6117 int tmp;
6118
6119 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6120 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6121 int aud_config = HSW_AUD_CFG(pipe);
6122 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6123
6124
6125 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6126
6127 /* Audio output enable */
6128 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6129 tmp = I915_READ(aud_cntrl_st2);
6130 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6131 I915_WRITE(aud_cntrl_st2, tmp);
6132
6133 /* Wait for 1 vertical blank */
6134 intel_wait_for_vblank(dev, pipe);
6135
6136 /* Set ELD valid state */
6137 tmp = I915_READ(aud_cntrl_st2);
6138 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
6139 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6140 I915_WRITE(aud_cntrl_st2, tmp);
6141 tmp = I915_READ(aud_cntrl_st2);
6142 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
6143
6144 /* Enable HDMI mode */
6145 tmp = I915_READ(aud_config);
6146 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
6147 /* clear N_programing_enable and N_value_index */
6148 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6149 I915_WRITE(aud_config, tmp);
6150
6151 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6152
6153 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6154 intel_crtc->eld_vld = true;
83358c85
WX		 6155
6156 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6157 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6158 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6159 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6160 } else
6161 I915_WRITE(aud_config, 0);
6162
6163 if (intel_eld_uptodate(connector,
6164 aud_cntrl_st2, eldv,
6165 aud_cntl_st, IBX_ELD_ADDRESS,
6166 hdmiw_hdmiedid))
6167 return;
6168
6169 i = I915_READ(aud_cntrl_st2);
6170 i &= ~eldv;
6171 I915_WRITE(aud_cntrl_st2, i);
6172
6173 if (!eld[0])
6174 return;
6175
6176 i = I915_READ(aud_cntl_st);
6177 i &= ~IBX_ELD_ADDRESS;
6178 I915_WRITE(aud_cntl_st, i);
6179 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6180 DRM_DEBUG_DRIVER("port num:%d\n", i);
6181
6182 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6183 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6184 for (i = 0; i < len; i++)
6185 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6186
6187 i = I915_READ(aud_cntrl_st2);
6188 i |= eldv;
6189 I915_WRITE(aud_cntrl_st2, i);
6190
6191}
6192
e0dac65e
WF		 6193static void ironlake_write_eld(struct drm_connector *connector,
6194 struct drm_crtc *crtc)
6195{
6196 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6197 uint8_t *eld = connector->eld;
6198 uint32_t eldv;
6199 uint32_t i;
6200 int len;
6201 int hdmiw_hdmiedid;
b6daa025 6202 int aud_config;
e0dac65e
WF		 6203 int aud_cntl_st;
6204 int aud_cntrl_st2;
9b138a83 6205 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6206
b3f33cbf 6207 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6208 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6209 aud_config = IBX_AUD_CFG(pipe);
6210 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6211 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6212 } else {
9b138a83
WX		 6213 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6214 aud_config = CPT_AUD_CFG(pipe);
6215 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6216 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6217 }
6218
9b138a83 6219 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6220
6221 i = I915_READ(aud_cntl_st);
9b138a83 6222 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6223 if (!i) {
6224 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6225 /* operate blindly on all ports */
1202b4c6
WF		 6226 eldv = IBX_ELD_VALIDB;
6227 eldv |= IBX_ELD_VALIDB << 4;
6228 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6229 } else {
2582a850 6230 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6231 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6232 }
6233
3a9627f4
WF		 6234 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6235 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6236 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6237 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6238 } else
6239 I915_WRITE(aud_config, 0);
e0dac65e 6240
3a9627f4
WF		 6241 if (intel_eld_uptodate(connector,
6242 aud_cntrl_st2, eldv,
6243 aud_cntl_st, IBX_ELD_ADDRESS,
6244 hdmiw_hdmiedid))
6245 return;
6246
e0dac65e
WF		 6247 i = I915_READ(aud_cntrl_st2);
6248 i &= ~eldv;
6249 I915_WRITE(aud_cntrl_st2, i);
6250
6251 if (!eld[0])
6252 return;
6253
e0dac65e 6254 i = I915_READ(aud_cntl_st);
1202b4c6 6255 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6256 I915_WRITE(aud_cntl_st, i);
6257
6258 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6259 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6260 for (i = 0; i < len; i++)
6261 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6262
6263 i = I915_READ(aud_cntrl_st2);
6264 i |= eldv;
6265 I915_WRITE(aud_cntrl_st2, i);
6266}
6267
6268void intel_write_eld(struct drm_encoder *encoder,
6269 struct drm_display_mode *mode)
6270{
6271 struct drm_crtc *crtc = encoder->crtc;
6272 struct drm_connector *connector;
6273 struct drm_device *dev = encoder->dev;
6274 struct drm_i915_private *dev_priv = dev->dev_private;
6275
6276 connector = drm_select_eld(encoder, mode);
6277 if (!connector)
6278 return;
6279
6280 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6281 connector->base.id,
6282 drm_get_connector_name(connector),
6283 connector->encoder->base.id,
6284 drm_get_encoder_name(connector->encoder));
6285
6286 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6287
6288 if (dev_priv->display.write_eld)
6289 dev_priv->display.write_eld(connector, crtc);
6290}
6291
79e53945
JB		 6292/** Loads the palette/gamma unit for the CRTC with the prepared values */
6293void intel_crtc_load_lut(struct drm_crtc *crtc)
6294{
6295 struct drm_device *dev = crtc->dev;
6296 struct drm_i915_private *dev_priv = dev->dev_private;
6297 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
42db64ef
PZ		 6298 enum pipe pipe = intel_crtc->pipe;
6299 int palreg = PALETTE(pipe);
79e53945 6300 int i;
42db64ef 6301 bool reenable_ips = false;
79e53945
JB		 6302
6303 /* The clocks have to be on to load the palette. */
aed3f09d 6304 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6305 return;
6306
f2b115e6 6307 /* use legacy palette for Ironlake */
bad720ff 6308 if (HAS_PCH_SPLIT(dev))
42db64ef
PZ		 6309 palreg = LGC_PALETTE(pipe);
6310
6311 /* Workaround : Do not read or write the pipe palette/gamma data while
6312 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
6313 */
6314 if (intel_crtc->config.ips_enabled &&
6315 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
6316 GAMMA_MODE_MODE_SPLIT)) {
6317 hsw_disable_ips(intel_crtc);
6318 reenable_ips = true;
6319 }
2c07245f 6320
79e53945
JB		 6321 for (i = 0; i < 256; i++) {
6322 I915_WRITE(palreg + 4 * i,
6323 (intel_crtc->lut_r[i] << 16) |
6324 (intel_crtc->lut_g[i] << 8) |
6325 intel_crtc->lut_b[i]);
6326 }
42db64ef
PZ		 6327
6328 if (reenable_ips)
6329 hsw_enable_ips(intel_crtc);
79e53945
JB		 6330}
6331
560b85bb
CW		 6332static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6333{
6334 struct drm_device *dev = crtc->dev;
6335 struct drm_i915_private *dev_priv = dev->dev_private;
6336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6337 bool visible = base != 0;
6338 u32 cntl;
6339
6340 if (intel_crtc->cursor_visible == visible)
6341 return;
6342
9db4a9c7 6343 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6344 if (visible) {
6345 /* On these chipsets we can only modify the base whilst
6346 * the cursor is disabled.
6347 */
9db4a9c7 6348 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6349
6350 cntl &= ~(CURSOR_FORMAT_MASK);
6351 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6352 cntl |= CURSOR_ENABLE |
6353 CURSOR_GAMMA_ENABLE |
6354 CURSOR_FORMAT_ARGB;
6355 } else
6356 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6357 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6358
6359 intel_crtc->cursor_visible = visible;
6360}
6361
6362static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6363{
6364 struct drm_device *dev = crtc->dev;
6365 struct drm_i915_private *dev_priv = dev->dev_private;
6366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6367 int pipe = intel_crtc->pipe;
6368 bool visible = base != 0;
6369
6370 if (intel_crtc->cursor_visible != visible) {
548f245b 6371 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6372 if (base) {
6373 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6374 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6375 cntl |= pipe << 28; /* Connect to correct pipe */
6376 } else {
6377 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6378 cntl |= CURSOR_MODE_DISABLE;
6379 }
9db4a9c7 6380 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6381
6382 intel_crtc->cursor_visible = visible;
6383 }
6384 /* and commit changes on next vblank */
9db4a9c7 6385 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6386}
6387
65a21cd6
JB		 6388static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6389{
6390 struct drm_device *dev = crtc->dev;
6391 struct drm_i915_private *dev_priv = dev->dev_private;
6392 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6393 int pipe = intel_crtc->pipe;
6394 bool visible = base != 0;
6395
6396 if (intel_crtc->cursor_visible != visible) {
6397 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6398 if (base) {
6399 cntl &= ~CURSOR_MODE;
6400 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6401 } else {
6402 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6403 cntl |= CURSOR_MODE_DISABLE;
6404 }
86d3efce
VS		 6405 if (IS_HASWELL(dev))
6406 cntl |= CURSOR_PIPE_CSC_ENABLE;
65a21cd6
JB		 6407 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6408
6409 intel_crtc->cursor_visible = visible;
6410 }
6411 /* and commit changes on next vblank */
6412 I915_WRITE(CURBASE_IVB(pipe), base);
6413}
6414
cda4b7d3 6415/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6416static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6417 bool on)
cda4b7d3
CW		 6418{
6419 struct drm_device *dev = crtc->dev;
6420 struct drm_i915_private *dev_priv = dev->dev_private;
6421 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6422 int pipe = intel_crtc->pipe;
6423 int x = intel_crtc->cursor_x;
6424 int y = intel_crtc->cursor_y;
560b85bb 6425 u32 base, pos;
cda4b7d3
CW		 6426 bool visible;
6427
6428 pos = 0;
6429
6b383a7f 6430 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6431 base = intel_crtc->cursor_addr;
6432 if (x > (int) crtc->fb->width)
6433 base = 0;
6434
6435 if (y > (int) crtc->fb->height)
6436 base = 0;
6437 } else
6438 base = 0;
6439
6440 if (x < 0) {
6441 if (x + intel_crtc->cursor_width < 0)
6442 base = 0;
6443
6444 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6445 x = -x;
6446 }
6447 pos |= x << CURSOR_X_SHIFT;
6448
6449 if (y < 0) {
6450 if (y + intel_crtc->cursor_height < 0)
6451 base = 0;
6452
6453 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6454 y = -y;
6455 }
6456 pos |= y << CURSOR_Y_SHIFT;
6457
6458 visible = base != 0;
560b85bb 6459 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6460 return;
6461
0cd83aa9 6462 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6463 I915_WRITE(CURPOS_IVB(pipe), pos);
6464 ivb_update_cursor(crtc, base);
6465 } else {
6466 I915_WRITE(CURPOS(pipe), pos);
6467 if (IS_845G(dev) || IS_I865G(dev))
6468 i845_update_cursor(crtc, base);
6469 else
6470 i9xx_update_cursor(crtc, base);
6471 }
cda4b7d3
CW		 6472}
6473
79e53945 6474static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6475 struct drm_file *file,
79e53945
JB		 6476 uint32_t handle,
6477 uint32_t width, uint32_t height)
6478{
6479 struct drm_device *dev = crtc->dev;
6480 struct drm_i915_private *dev_priv = dev->dev_private;
6481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6482 struct drm_i915_gem_object *obj;
cda4b7d3 6483 uint32_t addr;
3f8bc370 6484 int ret;
79e53945 6485
79e53945
JB		 6486 /* if we want to turn off the cursor ignore width and height */
6487 if (!handle) {
28c97730 6488 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6489 addr = 0;
05394f39 6490 obj = NULL;
5004417d 6491 mutex_lock(&dev->struct_mutex);
3f8bc370 6492 goto finish;
79e53945
JB		 6493 }
6494
6495 /* Currently we only support 64x64 cursors */
6496 if (width != 64 || height != 64) {
6497 DRM_ERROR("we currently only support 64x64 cursors\n");
6498 return -EINVAL;
6499 }
6500
05394f39 6501 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6502 if (&obj->base == NULL)
79e53945
JB		 6503 return -ENOENT;
6504
05394f39 6505 if (obj->base.size < width * height * 4) {
79e53945 6506 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6507 ret = -ENOMEM;
6508 goto fail;
79e53945
JB		 6509 }
6510
71acb5eb 6511 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6512 mutex_lock(&dev->struct_mutex);
b295d1b6 6513 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 6514 unsigned alignment;
6515
d9e86c0e
CW		 6516 if (obj->tiling_mode) {
6517 DRM_ERROR("cursor cannot be tiled\n");
6518 ret = -EINVAL;
6519 goto fail_locked;
6520 }
6521
693db184
CW		 6522 /* Note that the w/a also requires 2 PTE of padding following
6523 * the bo. We currently fill all unused PTE with the shadow
6524 * page and so we should always have valid PTE following the
6525 * cursor preventing the VT-d warning.
6526 */
6527 alignment = 0;
6528 if (need_vtd_wa(dev))
6529 alignment = 64*1024;
6530
6531 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 6532 if (ret) {
6533 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6534 goto fail_locked;
e7b526bb
CW		 6535 }
6536
d9e86c0e
CW		 6537 ret = i915_gem_object_put_fence(obj);
6538 if (ret) {
2da3b9b9 6539 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6540 goto fail_unpin;
6541 }
6542
05394f39 6543 addr = obj->gtt_offset;
71acb5eb 6544 } else {
6eeefaf3 6545 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6546 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6547 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6548 align);
71acb5eb
DA		 6549 if (ret) {
6550 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6551 goto fail_locked;
71acb5eb 6552 }
05394f39 6553 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6554 }
6555
a6c45cf0 6556 if (IS_GEN2(dev))
14b60391
JB		 6557 I915_WRITE(CURSIZE, (height << 12) | width);
6558
3f8bc370 6559 finish:
3f8bc370 6560 if (intel_crtc->cursor_bo) {
b295d1b6 6561 if (dev_priv->info->cursor_needs_physical) {
05394f39 6562 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6563 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6564 } else
6565 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6566 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6567 }
80824003 6568
7f9872e0 6569 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6570
6571 intel_crtc->cursor_addr = addr;
05394f39 6572 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6573 intel_crtc->cursor_width = width;
6574 intel_crtc->cursor_height = height;
6575
40ccc72b 6576 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 6577
79e53945 6578 return 0;
e7b526bb 6579fail_unpin:
05394f39 6580 i915_gem_object_unpin(obj);
7f9872e0 6581fail_locked:
34b8686e 6582 mutex_unlock(&dev->struct_mutex);
bc9025bd 6583fail:
05394f39 6584 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6585 return ret;
79e53945
JB		 6586}
6587
6588static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6589{
79e53945 6590 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6591
cda4b7d3
CW		 6592 intel_crtc->cursor_x = x;
6593 intel_crtc->cursor_y = y;
652c393a 6594
40ccc72b 6595 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 6596
6597 return 0;
6598}
6599
6600/** Sets the color ramps on behalf of RandR */
6601void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6602 u16 blue, int regno)
6603{
6604 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6605
6606 intel_crtc->lut_r[regno] = red >> 8;
6607 intel_crtc->lut_g[regno] = green >> 8;
6608 intel_crtc->lut_b[regno] = blue >> 8;
6609}
6610
b8c00ac5
DA		 6611void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6612 u16 *blue, int regno)
6613{
6614 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6615
6616 *red = intel_crtc->lut_r[regno] << 8;
6617 *green = intel_crtc->lut_g[regno] << 8;
6618 *blue = intel_crtc->lut_b[regno] << 8;
6619}
6620
79e53945 6621static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6622 u16 *blue, uint32_t start, uint32_t size)
79e53945 6623{
7203425a 6624 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6626
7203425a 6627 for (i = start; i < end; i++) {
79e53945
JB		 6628 intel_crtc->lut_r[i] = red[i] >> 8;
6629 intel_crtc->lut_g[i] = green[i] >> 8;
6630 intel_crtc->lut_b[i] = blue[i] >> 8;
6631 }
6632
6633 intel_crtc_load_lut(crtc);
6634}
6635
79e53945
JB		 6636/* VESA 640x480x72Hz mode to set on the pipe */
6637static struct drm_display_mode load_detect_mode = {
6638 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6639 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6640};
6641
d2dff872
CW		 6642static struct drm_framebuffer *
6643intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6644 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6645 struct drm_i915_gem_object *obj)
6646{
6647 struct intel_framebuffer *intel_fb;
6648 int ret;
6649
6650 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6651 if (!intel_fb) {
6652 drm_gem_object_unreference_unlocked(&obj->base);
6653 return ERR_PTR(-ENOMEM);
6654 }
6655
6656 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6657 if (ret) {
6658 drm_gem_object_unreference_unlocked(&obj->base);
6659 kfree(intel_fb);
6660 return ERR_PTR(ret);
6661 }
6662
6663 return &intel_fb->base;
6664}
6665
6666static u32
6667intel_framebuffer_pitch_for_width(int width, int bpp)
6668{
6669 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6670 return ALIGN(pitch, 64);
6671}
6672
6673static u32
6674intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6675{
6676 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6677 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6678}
6679
6680static struct drm_framebuffer *
6681intel_framebuffer_create_for_mode(struct drm_device *dev,
6682 struct drm_display_mode *mode,
6683 int depth, int bpp)
6684{
6685 struct drm_i915_gem_object *obj;
0fed39bd 6686 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6687
6688 obj = i915_gem_alloc_object(dev,
6689 intel_framebuffer_size_for_mode(mode, bpp));
6690 if (obj == NULL)
6691 return ERR_PTR(-ENOMEM);
6692
6693 mode_cmd.width = mode->hdisplay;
6694 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6695 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6696 bpp);
5ca0c34a 6697 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6698
6699 return intel_framebuffer_create(dev, &mode_cmd, obj);
6700}
6701
6702static struct drm_framebuffer *
6703mode_fits_in_fbdev(struct drm_device *dev,
6704 struct drm_display_mode *mode)
6705{
6706 struct drm_i915_private *dev_priv = dev->dev_private;
6707 struct drm_i915_gem_object *obj;
6708 struct drm_framebuffer *fb;
6709
6710 if (dev_priv->fbdev == NULL)
6711 return NULL;
6712
6713 obj = dev_priv->fbdev->ifb.obj;
6714 if (obj == NULL)
6715 return NULL;
6716
6717 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6718 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6719 fb->bits_per_pixel))
d2dff872
CW		 6720 return NULL;
6721
01f2c773 6722 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6723 return NULL;
6724
6725 return fb;
6726}
6727
d2434ab7 6728bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6729 struct drm_display_mode *mode,
8261b191 6730 struct intel_load_detect_pipe *old)
79e53945
JB		 6731{
6732 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6733 struct intel_encoder *intel_encoder =
6734 intel_attached_encoder(connector);
79e53945 6735 struct drm_crtc *possible_crtc;
4ef69c7a 6736 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6737 struct drm_crtc *crtc = NULL;
6738 struct drm_device *dev = encoder->dev;
94352cf9 6739 struct drm_framebuffer *fb;
79e53945
JB		 6740 int i = -1;
6741
d2dff872
CW		 6742 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6743 connector->base.id, drm_get_connector_name(connector),
6744 encoder->base.id, drm_get_encoder_name(encoder));
6745
79e53945
JB		 6746 /*
6747 * Algorithm gets a little messy:
7a5e4805 6748 *
79e53945
JB		 6749 * - if the connector already has an assigned crtc, use it (but make
6750 * sure it's on first)
7a5e4805 6751 *
79e53945
JB		 6752 * - try to find the first unused crtc that can drive this connector,
6753 * and use that if we find one
79e53945
JB		 6754 */
6755
6756 /* See if we already have a CRTC for this connector */
6757 if (encoder->crtc) {
6758 crtc = encoder->crtc;
8261b191 6759
7b24056b
DV		 6760 mutex_lock(&crtc->mutex);
6761
24218aac 6762 old->dpms_mode = connector->dpms;
8261b191
CW		 6763 old->load_detect_temp = false;
6764
6765 /* Make sure the crtc and connector are running */
24218aac
DV		 6766 if (connector->dpms != DRM_MODE_DPMS_ON)
6767 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6768
7173188d 6769 return true;
79e53945
JB		 6770 }
6771
6772 /* Find an unused one (if possible) */
6773 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6774 i++;
6775 if (!(encoder->possible_crtcs & (1 << i)))
6776 continue;
6777 if (!possible_crtc->enabled) {
6778 crtc = possible_crtc;
6779 break;
6780 }
79e53945
JB		 6781 }
6782
6783 /*
6784 * If we didn't find an unused CRTC, don't use any.
6785 */
6786 if (!crtc) {
7173188d
CW		 6787 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6788 return false;
79e53945
JB		 6789 }
6790
7b24056b 6791 mutex_lock(&crtc->mutex);
fc303101
DV		 6792 intel_encoder->new_crtc = to_intel_crtc(crtc);
6793 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6794
6795 intel_crtc = to_intel_crtc(crtc);
24218aac 6796 old->dpms_mode = connector->dpms;
8261b191 6797 old->load_detect_temp = true;
d2dff872 6798 old->release_fb = NULL;
79e53945 6799
6492711d
CW		 6800 if (!mode)
6801 mode = &load_detect_mode;
79e53945 6802
d2dff872
CW		 6803 /* We need a framebuffer large enough to accommodate all accesses
6804 * that the plane may generate whilst we perform load detection.
6805 * We can not rely on the fbcon either being present (we get called
6806 * during its initialisation to detect all boot displays, or it may
6807 * not even exist) or that it is large enough to satisfy the
6808 * requested mode.
6809 */
94352cf9
DV		 6810 fb = mode_fits_in_fbdev(dev, mode);
6811 if (fb == NULL) {
d2dff872 6812 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6813 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6814 old->release_fb = fb;
d2dff872
CW		 6815 } else
6816 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6817 if (IS_ERR(fb)) {
d2dff872 6818 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 6819 mutex_unlock(&crtc->mutex);
0e8b3d3e 6820 return false;
79e53945 6821 }
79e53945 6822
c0c36b94 6823 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6824 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6825 if (old->release_fb)
6826 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 6827 mutex_unlock(&crtc->mutex);
0e8b3d3e 6828 return false;
79e53945 6829 }
7173188d 6830
79e53945 6831 /* let the connector get through one full cycle before testing */
9d0498a2 6832 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6833 return true;
79e53945
JB		 6834}
6835
d2434ab7 6836void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6837 struct intel_load_detect_pipe *old)
79e53945 6838{
d2434ab7
DV		 6839 struct intel_encoder *intel_encoder =
6840 intel_attached_encoder(connector);
4ef69c7a 6841 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 6842 struct drm_crtc *crtc = encoder->crtc;
79e53945 6843
d2dff872
CW		 6844 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6845 connector->base.id, drm_get_connector_name(connector),
6846 encoder->base.id, drm_get_encoder_name(encoder));
6847
8261b191 6848 if (old->load_detect_temp) {
fc303101
DV		 6849 to_intel_connector(connector)->new_encoder = NULL;
6850 intel_encoder->new_crtc = NULL;
6851 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 6852
36206361
DV		 6853 if (old->release_fb) {
6854 drm_framebuffer_unregister_private(old->release_fb);
6855 drm_framebuffer_unreference(old->release_fb);
6856 }
d2dff872 6857
67c96400 6858 mutex_unlock(&crtc->mutex);
0622a53c 6859 return;
79e53945
JB		 6860 }
6861
c751ce4f 6862 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6863 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6864 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 6865
6866 mutex_unlock(&crtc->mutex);
79e53945
JB		 6867}
6868
6869/* Returns the clock of the currently programmed mode of the given pipe. */
6870static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6871{
6872 struct drm_i915_private *dev_priv = dev->dev_private;
6873 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6874 int pipe = intel_crtc->pipe;
548f245b 6875 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6876 u32 fp;
6877 intel_clock_t clock;
6878
6879 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6880 fp = I915_READ(FP0(pipe));
79e53945 6881 else
39adb7a5 6882 fp = I915_READ(FP1(pipe));
79e53945
JB		 6883
6884 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6885 if (IS_PINEVIEW(dev)) {
6886 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6887 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6888 } else {
6889 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6890 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6891 }
6892
a6c45cf0 6893 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6894 if (IS_PINEVIEW(dev))
6895 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6896 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6897 else
6898 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6899 DPLL_FPA01_P1_POST_DIV_SHIFT);
6900
6901 switch (dpll & DPLL_MODE_MASK) {
6902 case DPLLB_MODE_DAC_SERIAL:
6903 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6904 5 : 10;
6905 break;
6906 case DPLLB_MODE_LVDS:
6907 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6908 7 : 14;
6909 break;
6910 default:
28c97730 6911 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6912 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6913 return 0;
6914 }
6915
ac58c3f0
DV		 6916 if (IS_PINEVIEW(dev))
6917 pineview_clock(96000, &clock);
6918 else
6919 i9xx_clock(96000, &clock);
79e53945
JB		 6920 } else {
6921 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6922
6923 if (is_lvds) {
6924 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6925 DPLL_FPA01_P1_POST_DIV_SHIFT);
6926 clock.p2 = 14;
6927
6928 if ((dpll & PLL_REF_INPUT_MASK) ==
6929 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6930 /* XXX: might not be 66MHz */
ac58c3f0 6931 i9xx_clock(66000, &clock);
79e53945 6932 } else
ac58c3f0 6933 i9xx_clock(48000, &clock);
79e53945
JB		 6934 } else {
6935 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6936 clock.p1 = 2;
6937 else {
6938 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6939 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6940 }
6941 if (dpll & PLL_P2_DIVIDE_BY_4)
6942 clock.p2 = 4;
6943 else
6944 clock.p2 = 2;
6945
ac58c3f0 6946 i9xx_clock(48000, &clock);
79e53945
JB		 6947 }
6948 }
6949
6950 /* XXX: It would be nice to validate the clocks, but we can't reuse
6951 * i830PllIsValid() because it relies on the xf86_config connector
6952 * configuration being accurate, which it isn't necessarily.
6953 */
6954
6955 return clock.dot;
6956}
6957
6958/** Returns the currently programmed mode of the given pipe. */
6959struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6960 struct drm_crtc *crtc)
6961{
548f245b 6962 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6963 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 6964 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 6965 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6966 int htot = I915_READ(HTOTAL(cpu_transcoder));
6967 int hsync = I915_READ(HSYNC(cpu_transcoder));
6968 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6969 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6970
6971 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6972 if (!mode)
6973 return NULL;
6974
6975 mode->clock = intel_crtc_clock_get(dev, crtc);
6976 mode->hdisplay = (htot & 0xffff) + 1;
6977 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6978 mode->hsync_start = (hsync & 0xffff) + 1;
6979 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6980 mode->vdisplay = (vtot & 0xffff) + 1;
6981 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6982 mode->vsync_start = (vsync & 0xffff) + 1;
6983 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6984
6985 drm_mode_set_name(mode);
79e53945
JB		 6986
6987 return mode;
6988}
6989
3dec0095 6990static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6991{
6992 struct drm_device *dev = crtc->dev;
6993 drm_i915_private_t *dev_priv = dev->dev_private;
6994 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6995 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6996 int dpll_reg = DPLL(pipe);
6997 int dpll;
652c393a 6998
bad720ff 6999 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7000 return;
7001
7002 if (!dev_priv->lvds_downclock_avail)
7003 return;
7004
dbdc6479 7005 dpll = I915_READ(dpll_reg);
652c393a 7006 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7007 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7008
8ac5a6d5 7009 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7010
7011 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7012 I915_WRITE(dpll_reg, dpll);
9d0498a2 7013 intel_wait_for_vblank(dev, pipe);
dbdc6479 7014
652c393a
JB		 7015 dpll = I915_READ(dpll_reg);
7016 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7017 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7018 }
652c393a
JB		 7019}
7020
7021static void intel_decrease_pllclock(struct drm_crtc *crtc)
7022{
7023 struct drm_device *dev = crtc->dev;
7024 drm_i915_private_t *dev_priv = dev->dev_private;
7025 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7026
bad720ff 7027 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7028 return;
7029
7030 if (!dev_priv->lvds_downclock_avail)
7031 return;
7032
7033 /*
7034 * Since this is called by a timer, we should never get here in
7035 * the manual case.
7036 */
7037 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7038 int pipe = intel_crtc->pipe;
7039 int dpll_reg = DPLL(pipe);
7040 int dpll;
f6e5b160 7041
44d98a61 7042 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7043
8ac5a6d5 7044 assert_panel_unlocked(dev_priv, pipe);
652c393a 7045
dc257cf1 7046 dpll = I915_READ(dpll_reg);
652c393a
JB		 7047 dpll |= DISPLAY_RATE_SELECT_FPA1;
7048 I915_WRITE(dpll_reg, dpll);
9d0498a2 7049 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7050 dpll = I915_READ(dpll_reg);
7051 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7052 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7053 }
7054
7055}
7056
f047e395
CW		 7057void intel_mark_busy(struct drm_device *dev)
7058{
f047e395
CW		 7059 i915_update_gfx_val(dev->dev_private);
7060}
7061
7062void intel_mark_idle(struct drm_device *dev)
652c393a 7063{
652c393a 7064 struct drm_crtc *crtc;
652c393a
JB		 7065
7066 if (!i915_powersave)
7067 return;
7068
652c393a 7069 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7070 if (!crtc->fb)
7071 continue;
7072
725a5b54 7073 intel_decrease_pllclock(crtc);
652c393a 7074 }
652c393a
JB		 7075}
7076
725a5b54 7077void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 7078{
f047e395
CW		 7079 struct drm_device *dev = obj->base.dev;
7080 struct drm_crtc *crtc;
652c393a 7081
f047e395 7082 if (!i915_powersave)
acb87dfb
CW		 7083 return;
7084
652c393a
JB		 7085 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7086 if (!crtc->fb)
7087 continue;
7088
f047e395 7089 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 7090 intel_increase_pllclock(crtc);
652c393a
JB		 7091 }
7092}
7093
79e53945
JB		 7094static void intel_crtc_destroy(struct drm_crtc *crtc)
7095{
7096 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7097 struct drm_device *dev = crtc->dev;
7098 struct intel_unpin_work *work;
7099 unsigned long flags;
7100
7101 spin_lock_irqsave(&dev->event_lock, flags);
7102 work = intel_crtc->unpin_work;
7103 intel_crtc->unpin_work = NULL;
7104 spin_unlock_irqrestore(&dev->event_lock, flags);
7105
7106 if (work) {
7107 cancel_work_sync(&work->work);
7108 kfree(work);
7109 }
79e53945 7110
40ccc72b
MK		 7111 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7112
79e53945 7113 drm_crtc_cleanup(crtc);
67e77c5a 7114
79e53945
JB		 7115 kfree(intel_crtc);
7116}
7117
6b95a207
KH		 7118static void intel_unpin_work_fn(struct work_struct *__work)
7119{
7120 struct intel_unpin_work *work =
7121 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7122 struct drm_device *dev = work->crtc->dev;
6b95a207 7123
b4a98e57 7124 mutex_lock(&dev->struct_mutex);
1690e1eb 7125 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7126 drm_gem_object_unreference(&work->pending_flip_obj->base);
7127 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7128
b4a98e57
CW		 7129 intel_update_fbc(dev);
7130 mutex_unlock(&dev->struct_mutex);
7131
7132 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7133 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7134
6b95a207
KH		 7135 kfree(work);
7136}
7137
1afe3e9d 7138static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7139 struct drm_crtc *crtc)
6b95a207
KH		 7140{
7141 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7142 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7143 struct intel_unpin_work *work;
6b95a207
KH		 7144 unsigned long flags;
7145
7146 /* Ignore early vblank irqs */
7147 if (intel_crtc == NULL)
7148 return;
7149
7150 spin_lock_irqsave(&dev->event_lock, flags);
7151 work = intel_crtc->unpin_work;
e7d841ca
CW		 7152
7153 /* Ensure we don't miss a work->pending update ... */
7154 smp_rmb();
7155
7156 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7157 spin_unlock_irqrestore(&dev->event_lock, flags);
7158 return;
7159 }
7160
e7d841ca
CW		 7161 /* and that the unpin work is consistent wrt ->pending. */
7162 smp_rmb();
7163
6b95a207 7164 intel_crtc->unpin_work = NULL;
6b95a207 7165
45a066eb
RC		 7166 if (work->event)
7167 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7168
0af7e4df
MK		 7169 drm_vblank_put(dev, intel_crtc->pipe);
7170
6b95a207
KH		 7171 spin_unlock_irqrestore(&dev->event_lock, flags);
7172
2c10d571 7173 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7174
7175 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7176
7177 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7178}
7179
1afe3e9d
JB		 7180void intel_finish_page_flip(struct drm_device *dev, int pipe)
7181{
7182 drm_i915_private_t *dev_priv = dev->dev_private;
7183 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7184
49b14a5c 7185 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7186}
7187
7188void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7189{
7190 drm_i915_private_t *dev_priv = dev->dev_private;
7191 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7192
49b14a5c 7193 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7194}
7195
6b95a207
KH		 7196void intel_prepare_page_flip(struct drm_device *dev, int plane)
7197{
7198 drm_i915_private_t *dev_priv = dev->dev_private;
7199 struct intel_crtc *intel_crtc =
7200 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7201 unsigned long flags;
7202
e7d841ca
CW		 7203 /* NB: An MMIO update of the plane base pointer will also
7204 * generate a page-flip completion irq, i.e. every modeset
7205 * is also accompanied by a spurious intel_prepare_page_flip().
7206 */
6b95a207 7207 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7208 if (intel_crtc->unpin_work)
7209 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7210 spin_unlock_irqrestore(&dev->event_lock, flags);
7211}
7212
e7d841ca
CW		 7213inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7214{
7215 /* Ensure that the work item is consistent when activating it ... */
7216 smp_wmb();
7217 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7218 /* and that it is marked active as soon as the irq could fire. */
7219 smp_wmb();
7220}
7221
8c9f3aaf
JB		 7222static int intel_gen2_queue_flip(struct drm_device *dev,
7223 struct drm_crtc *crtc,
7224 struct drm_framebuffer *fb,
7225 struct drm_i915_gem_object *obj)
7226{
7227 struct drm_i915_private *dev_priv = dev->dev_private;
7228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7229 u32 flip_mask;
6d90c952 7230 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7231 int ret;
7232
6d90c952 7233 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7234 if (ret)
83d4092b 7235 goto err;
8c9f3aaf 7236
6d90c952 7237 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7238 if (ret)
83d4092b 7239 goto err_unpin;
8c9f3aaf
JB		 7240
7241 /* Can't queue multiple flips, so wait for the previous
7242 * one to finish before executing the next.
7243 */
7244 if (intel_crtc->plane)
7245 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7246 else
7247 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7248 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7249 intel_ring_emit(ring, MI_NOOP);
7250 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7251 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7252 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7253 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 7254 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7255
7256 intel_mark_page_flip_active(intel_crtc);
6d90c952 7257 intel_ring_advance(ring);
83d4092b
CW		 7258 return 0;
7259
7260err_unpin:
7261 intel_unpin_fb_obj(obj);
7262err:
8c9f3aaf
JB		 7263 return ret;
7264}
7265
7266static int intel_gen3_queue_flip(struct drm_device *dev,
7267 struct drm_crtc *crtc,
7268 struct drm_framebuffer *fb,
7269 struct drm_i915_gem_object *obj)
7270{
7271 struct drm_i915_private *dev_priv = dev->dev_private;
7272 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7273 u32 flip_mask;
6d90c952 7274 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7275 int ret;
7276
6d90c952 7277 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7278 if (ret)
83d4092b 7279 goto err;
8c9f3aaf 7280
6d90c952 7281 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7282 if (ret)
83d4092b 7283 goto err_unpin;
8c9f3aaf
JB		 7284
7285 if (intel_crtc->plane)
7286 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7287 else
7288 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7289 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7290 intel_ring_emit(ring, MI_NOOP);
7291 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7292 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7293 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 7294 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 7295 intel_ring_emit(ring, MI_NOOP);
7296
e7d841ca 7297 intel_mark_page_flip_active(intel_crtc);
6d90c952 7298 intel_ring_advance(ring);
83d4092b
CW		 7299 return 0;
7300
7301err_unpin:
7302 intel_unpin_fb_obj(obj);
7303err:
8c9f3aaf
JB		 7304 return ret;
7305}
7306
7307static int intel_gen4_queue_flip(struct drm_device *dev,
7308 struct drm_crtc *crtc,
7309 struct drm_framebuffer *fb,
7310 struct drm_i915_gem_object *obj)
7311{
7312 struct drm_i915_private *dev_priv = dev->dev_private;
7313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7314 uint32_t pf, pipesrc;
6d90c952 7315 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7316 int ret;
7317
6d90c952 7318 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7319 if (ret)
83d4092b 7320 goto err;
8c9f3aaf 7321
6d90c952 7322 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7323 if (ret)
83d4092b 7324 goto err_unpin;
8c9f3aaf
JB		 7325
7326 /* i965+ uses the linear or tiled offsets from the
7327 * Display Registers (which do not change across a page-flip)
7328 * so we need only reprogram the base address.
7329 */
6d90c952
DV		 7330 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7331 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7332 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7333 intel_ring_emit(ring,
7334 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7335 obj->tiling_mode);
8c9f3aaf
JB		 7336
7337 /* XXX Enabling the panel-fitter across page-flip is so far
7338 * untested on non-native modes, so ignore it for now.
7339 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7340 */
7341 pf = 0;
7342 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7343 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7344
7345 intel_mark_page_flip_active(intel_crtc);
6d90c952 7346 intel_ring_advance(ring);
83d4092b
CW		 7347 return 0;
7348
7349err_unpin:
7350 intel_unpin_fb_obj(obj);
7351err:
8c9f3aaf
JB		 7352 return ret;
7353}
7354
7355static int intel_gen6_queue_flip(struct drm_device *dev,
7356 struct drm_crtc *crtc,
7357 struct drm_framebuffer *fb,
7358 struct drm_i915_gem_object *obj)
7359{
7360 struct drm_i915_private *dev_priv = dev->dev_private;
7361 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7362 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7363 uint32_t pf, pipesrc;
7364 int ret;
7365
6d90c952 7366 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7367 if (ret)
83d4092b 7368 goto err;
8c9f3aaf 7369
6d90c952 7370 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7371 if (ret)
83d4092b 7372 goto err_unpin;
8c9f3aaf 7373
6d90c952
DV		 7374 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7375 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7376 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7377 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7378
dc257cf1
DV		 7379 /* Contrary to the suggestions in the documentation,
7380 * "Enable Panel Fitter" does not seem to be required when page
7381 * flipping with a non-native mode, and worse causes a normal
7382 * modeset to fail.
7383 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7384 */
7385 pf = 0;
8c9f3aaf 7386 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7387 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7388
7389 intel_mark_page_flip_active(intel_crtc);
6d90c952 7390 intel_ring_advance(ring);
83d4092b
CW		 7391 return 0;
7392
7393err_unpin:
7394 intel_unpin_fb_obj(obj);
7395err:
8c9f3aaf
JB		 7396 return ret;
7397}
7398
7c9017e5
JB		 7399/*
7400 * On gen7 we currently use the blit ring because (in early silicon at least)
7401 * the render ring doesn't give us interrpts for page flip completion, which
7402 * means clients will hang after the first flip is queued. Fortunately the
7403 * blit ring generates interrupts properly, so use it instead.
7404 */
7405static int intel_gen7_queue_flip(struct drm_device *dev,
7406 struct drm_crtc *crtc,
7407 struct drm_framebuffer *fb,
7408 struct drm_i915_gem_object *obj)
7409{
7410 struct drm_i915_private *dev_priv = dev->dev_private;
7411 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7412 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7413 uint32_t plane_bit = 0;
7c9017e5
JB		 7414 int ret;
7415
7416 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7417 if (ret)
83d4092b 7418 goto err;
7c9017e5 7419
cb05d8de
DV		 7420 switch(intel_crtc->plane) {
7421 case PLANE_A:
7422 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7423 break;
7424 case PLANE_B:
7425 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7426 break;
7427 case PLANE_C:
7428 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7429 break;
7430 default:
7431 WARN_ONCE(1, "unknown plane in flip command\n");
7432 ret = -ENODEV;
ab3951eb 7433 goto err_unpin;
cb05d8de
DV		 7434 }
7435
7c9017e5
JB		 7436 ret = intel_ring_begin(ring, 4);
7437 if (ret)
83d4092b 7438 goto err_unpin;
7c9017e5 7439
cb05d8de 7440 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7441 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7442 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7443 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7444
7445 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7446 intel_ring_advance(ring);
83d4092b
CW		 7447 return 0;
7448
7449err_unpin:
7450 intel_unpin_fb_obj(obj);
7451err:
7c9017e5
JB		 7452 return ret;
7453}
7454
8c9f3aaf
JB		 7455static int intel_default_queue_flip(struct drm_device *dev,
7456 struct drm_crtc *crtc,
7457 struct drm_framebuffer *fb,
7458 struct drm_i915_gem_object *obj)
7459{
7460 return -ENODEV;
7461}
7462
6b95a207
KH		 7463static int intel_crtc_page_flip(struct drm_crtc *crtc,
7464 struct drm_framebuffer *fb,
7465 struct drm_pending_vblank_event *event)
7466{
7467 struct drm_device *dev = crtc->dev;
7468 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 7469 struct drm_framebuffer *old_fb = crtc->fb;
7470 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 7471 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7472 struct intel_unpin_work *work;
8c9f3aaf 7473 unsigned long flags;
52e68630 7474 int ret;
6b95a207 7475
e6a595d2
VS		 7476 /* Can't change pixel format via MI display flips. */
7477 if (fb->pixel_format != crtc->fb->pixel_format)
7478 return -EINVAL;
7479
7480 /*
7481 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7482 * Note that pitch changes could also affect these register.
7483 */
7484 if (INTEL_INFO(dev)->gen > 3 &&
7485 (fb->offsets[0] != crtc->fb->offsets[0] ||
7486 fb->pitches[0] != crtc->fb->pitches[0]))
7487 return -EINVAL;
7488
6b95a207
KH		 7489 work = kzalloc(sizeof *work, GFP_KERNEL);
7490 if (work == NULL)
7491 return -ENOMEM;
7492
6b95a207 7493 work->event = event;
b4a98e57 7494 work->crtc = crtc;
4a35f83b 7495 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 7496 INIT_WORK(&work->work, intel_unpin_work_fn);
7497
7317c75e
JB		 7498 ret = drm_vblank_get(dev, intel_crtc->pipe);
7499 if (ret)
7500 goto free_work;
7501
6b95a207
KH		 7502 /* We borrow the event spin lock for protecting unpin_work */
7503 spin_lock_irqsave(&dev->event_lock, flags);
7504 if (intel_crtc->unpin_work) {
7505 spin_unlock_irqrestore(&dev->event_lock, flags);
7506 kfree(work);
7317c75e 7507 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7508
7509 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7510 return -EBUSY;
7511 }
7512 intel_crtc->unpin_work = work;
7513 spin_unlock_irqrestore(&dev->event_lock, flags);
7514
b4a98e57
CW		 7515 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7516 flush_workqueue(dev_priv->wq);
7517
79158103
CW		 7518 ret = i915_mutex_lock_interruptible(dev);
7519 if (ret)
7520 goto cleanup;
6b95a207 7521
75dfca80 7522 /* Reference the objects for the scheduled work. */
05394f39
CW		 7523 drm_gem_object_reference(&work->old_fb_obj->base);
7524 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7525
7526 crtc->fb = fb;
96b099fd 7527
e1f99ce6 7528 work->pending_flip_obj = obj;
e1f99ce6 7529
4e5359cd
SF		 7530 work->enable_stall_check = true;
7531
b4a98e57 7532 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 7533 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 7534
8c9f3aaf
JB		 7535 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7536 if (ret)
7537 goto cleanup_pending;
6b95a207 7538
7782de3b 7539 intel_disable_fbc(dev);
f047e395 7540 intel_mark_fb_busy(obj);
6b95a207
KH		 7541 mutex_unlock(&dev->struct_mutex);
7542
e5510fac
JB		 7543 trace_i915_flip_request(intel_crtc->plane, obj);
7544
6b95a207 7545 return 0;
96b099fd 7546
8c9f3aaf 7547cleanup_pending:
b4a98e57 7548 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 7549 crtc->fb = old_fb;
05394f39
CW		 7550 drm_gem_object_unreference(&work->old_fb_obj->base);
7551 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7552 mutex_unlock(&dev->struct_mutex);
7553
79158103 7554cleanup:
96b099fd
CW		 7555 spin_lock_irqsave(&dev->event_lock, flags);
7556 intel_crtc->unpin_work = NULL;
7557 spin_unlock_irqrestore(&dev->event_lock, flags);
7558
7317c75e
JB		 7559 drm_vblank_put(dev, intel_crtc->pipe);
7560free_work:
96b099fd
CW		 7561 kfree(work);
7562
7563 return ret;
6b95a207
KH		 7564}
7565
f6e5b160 7566static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7567 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7568 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 7569};
7570
6ed0f796 7571bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7572{
6ed0f796
DV		 7573 struct intel_encoder *other_encoder;
7574 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7575
6ed0f796
DV		 7576 if (WARN_ON(!crtc))
7577 return false;
7578
7579 list_for_each_entry(other_encoder,
7580 &crtc->dev->mode_config.encoder_list,
7581 base.head) {
7582
7583 if (&other_encoder->new_crtc->base != crtc ||
7584 encoder == other_encoder)
7585 continue;
7586 else
7587 return true;
f47166d2
CW		 7588 }
7589
6ed0f796
DV		 7590 return false;
7591}
47f1c6c9 7592
50f56119
DV		 7593static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7594 struct drm_crtc *crtc)
7595{
7596 struct drm_device *dev;
7597 struct drm_crtc *tmp;
7598 int crtc_mask = 1;
47f1c6c9 7599
50f56119 7600 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7601
50f56119 7602 dev = crtc->dev;
47f1c6c9 7603
50f56119
DV		 7604 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7605 if (tmp == crtc)
7606 break;
7607 crtc_mask <<= 1;
7608 }
47f1c6c9 7609
50f56119
DV		 7610 if (encoder->possible_crtcs & crtc_mask)
7611 return true;
7612 return false;
47f1c6c9 7613}
79e53945 7614
9a935856
DV		 7615/**
7616 * intel_modeset_update_staged_output_state
7617 *
7618 * Updates the staged output configuration state, e.g. after we've read out the
7619 * current hw state.
7620 */
7621static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7622{
9a935856
DV		 7623 struct intel_encoder *encoder;
7624 struct intel_connector *connector;
f6e5b160 7625
9a935856
DV		 7626 list_for_each_entry(connector, &dev->mode_config.connector_list,
7627 base.head) {
7628 connector->new_encoder =
7629 to_intel_encoder(connector->base.encoder);
7630 }
f6e5b160 7631
9a935856
DV		 7632 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7633 base.head) {
7634 encoder->new_crtc =
7635 to_intel_crtc(encoder->base.crtc);
7636 }
f6e5b160
CW		 7637}
7638
9a935856
DV		 7639/**
7640 * intel_modeset_commit_output_state
7641 *
7642 * This function copies the stage display pipe configuration to the real one.
7643 */
7644static void intel_modeset_commit_output_state(struct drm_device *dev)
7645{
7646 struct intel_encoder *encoder;
7647 struct intel_connector *connector;
f6e5b160 7648
9a935856
DV		 7649 list_for_each_entry(connector, &dev->mode_config.connector_list,
7650 base.head) {
7651 connector->base.encoder = &connector->new_encoder->base;
7652 }
f6e5b160 7653
9a935856
DV		 7654 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7655 base.head) {
7656 encoder->base.crtc = &encoder->new_crtc->base;
7657 }
7658}
7659
050f7aeb
DV		 7660static void
7661connected_sink_compute_bpp(struct intel_connector * connector,
7662 struct intel_crtc_config *pipe_config)
7663{
7664 int bpp = pipe_config->pipe_bpp;
7665
7666 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
7667 connector->base.base.id,
7668 drm_get_connector_name(&connector->base));
7669
7670 /* Don't use an invalid EDID bpc value */
7671 if (connector->base.display_info.bpc &&
7672 connector->base.display_info.bpc * 3 < bpp) {
7673 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
7674 bpp, connector->base.display_info.bpc*3);
7675 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
7676 }
7677
7678 /* Clamp bpp to 8 on screens without EDID 1.4 */
7679 if (connector->base.display_info.bpc == 0 && bpp > 24) {
7680 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
7681 bpp);
7682 pipe_config->pipe_bpp = 24;
7683 }
7684}
7685
4e53c2e0 7686static int
050f7aeb
DV		 7687compute_baseline_pipe_bpp(struct intel_crtc *crtc,
7688 struct drm_framebuffer *fb,
7689 struct intel_crtc_config *pipe_config)
4e53c2e0 7690{
050f7aeb
DV		 7691 struct drm_device *dev = crtc->base.dev;
7692 struct intel_connector *connector;
4e53c2e0
DV		 7693 int bpp;
7694
d42264b1
DV		 7695 switch (fb->pixel_format) {
7696 case DRM_FORMAT_C8:
4e53c2e0
DV		 7697 bpp = 8*3; /* since we go through a colormap */
7698 break;
d42264b1
DV		 7699 case DRM_FORMAT_XRGB1555:
7700 case DRM_FORMAT_ARGB1555:
7701 /* checked in intel_framebuffer_init already */
7702 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
7703 return -EINVAL;
7704 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 7705 bpp = 6*3; /* min is 18bpp */
7706 break;
d42264b1
DV		 7707 case DRM_FORMAT_XBGR8888:
7708 case DRM_FORMAT_ABGR8888:
7709 /* checked in intel_framebuffer_init already */
7710 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
7711 return -EINVAL;
7712 case DRM_FORMAT_XRGB8888:
7713 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 7714 bpp = 8*3;
7715 break;
d42264b1
DV		 7716 case DRM_FORMAT_XRGB2101010:
7717 case DRM_FORMAT_ARGB2101010:
7718 case DRM_FORMAT_XBGR2101010:
7719 case DRM_FORMAT_ABGR2101010:
7720 /* checked in intel_framebuffer_init already */
7721 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 7722 return -EINVAL;
4e53c2e0
DV		 7723 bpp = 10*3;
7724 break;
baba133a 7725 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 7726 default:
7727 DRM_DEBUG_KMS("unsupported depth\n");
7728 return -EINVAL;
7729 }
7730
4e53c2e0
DV		 7731 pipe_config->pipe_bpp = bpp;
7732
7733 /* Clamp display bpp to EDID value */
7734 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 7735 base.head) {
1b829e05
DV		 7736 if (!connector->new_encoder ||
7737 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 7738 continue;
7739
050f7aeb 7740 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 7741 }
7742
7743 return bpp;
7744}
7745
c0b03411
DV		 7746static void intel_dump_pipe_config(struct intel_crtc *crtc,
7747 struct intel_crtc_config *pipe_config,
7748 const char *context)
7749{
7750 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
7751 context, pipe_name(crtc->pipe));
7752
7753 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
7754 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
7755 pipe_config->pipe_bpp, pipe_config->dither);
7756 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
7757 pipe_config->has_pch_encoder,
7758 pipe_config->fdi_lanes,
7759 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
7760 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
7761 pipe_config->fdi_m_n.tu);
7762 DRM_DEBUG_KMS("requested mode:\n");
7763 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
7764 DRM_DEBUG_KMS("adjusted mode:\n");
7765 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
7766 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
7767 pipe_config->gmch_pfit.control,
7768 pipe_config->gmch_pfit.pgm_ratios,
7769 pipe_config->gmch_pfit.lvds_border_bits);
7770 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x\n",
7771 pipe_config->pch_pfit.pos,
7772 pipe_config->pch_pfit.size);
42db64ef 7773 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
c0b03411
DV		 7774}
7775
b8cecdf5
DV		 7776static struct intel_crtc_config *
7777intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 7778 struct drm_framebuffer *fb,
b8cecdf5 7779 struct drm_display_mode *mode)
ee7b9f93 7780{
7758a113 7781 struct drm_device *dev = crtc->dev;
7758a113
DV		 7782 struct drm_encoder_helper_funcs *encoder_funcs;
7783 struct intel_encoder *encoder;
b8cecdf5 7784 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 7785 int plane_bpp, ret = -EINVAL;
7786 bool retry = true;
ee7b9f93 7787
b8cecdf5
DV		 7788 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
7789 if (!pipe_config)
7758a113
DV		 7790 return ERR_PTR(-ENOMEM);
7791
b8cecdf5
DV		 7792 drm_mode_copy(&pipe_config->adjusted_mode, mode);
7793 drm_mode_copy(&pipe_config->requested_mode, mode);
eccb140b 7794 pipe_config->cpu_transcoder = to_intel_crtc(crtc)->pipe;
b8cecdf5 7795
050f7aeb
DV		 7796 /* Compute a starting value for pipe_config->pipe_bpp taking the source
7797 * plane pixel format and any sink constraints into account. Returns the
7798 * source plane bpp so that dithering can be selected on mismatches
7799 * after encoders and crtc also have had their say. */
7800 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
7801 fb, pipe_config);
4e53c2e0
DV		 7802 if (plane_bpp < 0)
7803 goto fail;
7804
e29c22c0 7805encoder_retry:
7758a113
DV		 7806 /* Pass our mode to the connectors and the CRTC to give them a chance to
7807 * adjust it according to limitations or connector properties, and also
7808 * a chance to reject the mode entirely.
47f1c6c9 7809 */
7758a113
DV		 7810 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7811 base.head) {
47f1c6c9 7812
7758a113
DV		 7813 if (&encoder->new_crtc->base != crtc)
7814 continue;
7ae89233
DV		 7815
7816 if (encoder->compute_config) {
7817 if (!(encoder->compute_config(encoder, pipe_config))) {
7818 DRM_DEBUG_KMS("Encoder config failure\n");
7819 goto fail;
7820 }
7821
7822 continue;
7823 }
7824
7758a113 7825 encoder_funcs = encoder->base.helper_private;
b8cecdf5
DV		 7826 if (!(encoder_funcs->mode_fixup(&encoder->base,
7827 &pipe_config->requested_mode,
7828 &pipe_config->adjusted_mode))) {
7758a113
DV		 7829 DRM_DEBUG_KMS("Encoder fixup failed\n");
7830 goto fail;
7831 }
ee7b9f93 7832 }
47f1c6c9 7833
e29c22c0
DV		 7834 ret = intel_crtc_compute_config(crtc, pipe_config);
7835 if (ret < 0) {
7758a113
DV		 7836 DRM_DEBUG_KMS("CRTC fixup failed\n");
7837 goto fail;
ee7b9f93 7838 }
e29c22c0
DV		 7839
7840 if (ret == RETRY) {
7841 if (WARN(!retry, "loop in pipe configuration computation\n")) {
7842 ret = -EINVAL;
7843 goto fail;
7844 }
7845
7846 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
7847 retry = false;
7848 goto encoder_retry;
7849 }
7850
4e53c2e0
DV		 7851 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
7852 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
7853 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
7854
b8cecdf5 7855 return pipe_config;
7758a113 7856fail:
b8cecdf5 7857 kfree(pipe_config);
e29c22c0 7858 return ERR_PTR(ret);
ee7b9f93 7859}
47f1c6c9 7860
e2e1ed41
DV		 7861/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7862 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7863static void
7864intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7865 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7866{
7867 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7868 struct drm_device *dev = crtc->dev;
7869 struct intel_encoder *encoder;
7870 struct intel_connector *connector;
7871 struct drm_crtc *tmp_crtc;
79e53945 7872
e2e1ed41 7873 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7874
e2e1ed41
DV		 7875 /* Check which crtcs have changed outputs connected to them, these need
7876 * to be part of the prepare_pipes mask. We don't (yet) support global
7877 * modeset across multiple crtcs, so modeset_pipes will only have one
7878 * bit set at most. */
7879 list_for_each_entry(connector, &dev->mode_config.connector_list,
7880 base.head) {
7881 if (connector->base.encoder == &connector->new_encoder->base)
7882 continue;
79e53945 7883
e2e1ed41
DV		 7884 if (connector->base.encoder) {
7885 tmp_crtc = connector->base.encoder->crtc;
7886
7887 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7888 }
7889
7890 if (connector->new_encoder)
7891 *prepare_pipes |=
7892 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7893 }
7894
e2e1ed41
DV		 7895 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7896 base.head) {
7897 if (encoder->base.crtc == &encoder->new_crtc->base)
7898 continue;
7899
7900 if (encoder->base.crtc) {
7901 tmp_crtc = encoder->base.crtc;
7902
7903 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7904 }
7905
7906 if (encoder->new_crtc)
7907 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7908 }
7909
e2e1ed41
DV		 7910 /* Check for any pipes that will be fully disabled ... */
7911 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7912 base.head) {
7913 bool used = false;
22fd0fab 7914
e2e1ed41
DV		 7915 /* Don't try to disable disabled crtcs. */
7916 if (!intel_crtc->base.enabled)
7917 continue;
7e7d76c3 7918
e2e1ed41
DV		 7919 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7920 base.head) {
7921 if (encoder->new_crtc == intel_crtc)
7922 used = true;
7923 }
7924
7925 if (!used)
7926 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7927 }
7928
e2e1ed41
DV		 7929
7930 /* set_mode is also used to update properties on life display pipes. */
7931 intel_crtc = to_intel_crtc(crtc);
7932 if (crtc->enabled)
7933 *prepare_pipes |= 1 << intel_crtc->pipe;
7934
b6c5164d
DV		 7935 /*
7936 * For simplicity do a full modeset on any pipe where the output routing
7937 * changed. We could be more clever, but that would require us to be
7938 * more careful with calling the relevant encoder->mode_set functions.
7939 */
e2e1ed41
DV		 7940 if (*prepare_pipes)
7941 *modeset_pipes = *prepare_pipes;
7942
7943 /* ... and mask these out. */
7944 *modeset_pipes &= ~(*disable_pipes);
7945 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 7946
7947 /*
7948 * HACK: We don't (yet) fully support global modesets. intel_set_config
7949 * obies this rule, but the modeset restore mode of
7950 * intel_modeset_setup_hw_state does not.
7951 */
7952 *modeset_pipes &= 1 << intel_crtc->pipe;
7953 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 7954
7955 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7956 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 7957}
79e53945 7958
ea9d758d 7959static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7960{
ea9d758d 7961 struct drm_encoder *encoder;
f6e5b160 7962 struct drm_device *dev = crtc->dev;
f6e5b160 7963
ea9d758d
DV		 7964 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7965 if (encoder->crtc == crtc)
7966 return true;
7967
7968 return false;
7969}
7970
7971static void
7972intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7973{
7974 struct intel_encoder *intel_encoder;
7975 struct intel_crtc *intel_crtc;
7976 struct drm_connector *connector;
7977
7978 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7979 base.head) {
7980 if (!intel_encoder->base.crtc)
7981 continue;
7982
7983 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7984
7985 if (prepare_pipes & (1 << intel_crtc->pipe))
7986 intel_encoder->connectors_active = false;
7987 }
7988
7989 intel_modeset_commit_output_state(dev);
7990
7991 /* Update computed state. */
7992 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7993 base.head) {
7994 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7995 }
7996
7997 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7998 if (!connector->encoder || !connector->encoder->crtc)
7999 continue;
8000
8001 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8002
8003 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8004 struct drm_property *dpms_property =
8005 dev->mode_config.dpms_property;
8006
ea9d758d 8007 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8008 drm_object_property_set_value(&connector->base,
68d34720
DV		 8009 dpms_property,
8010 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8011
8012 intel_encoder = to_intel_encoder(connector->encoder);
8013 intel_encoder->connectors_active = true;
8014 }
8015 }
8016
8017}
8018
25c5b266
DV		 8019#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8020 list_for_each_entry((intel_crtc), \
8021 &(dev)->mode_config.crtc_list, \
8022 base.head) \
0973f18f 8023 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8024
0e8ffe1b 8025static bool
2fa2fe9a
DV		 8026intel_pipe_config_compare(struct drm_device *dev,
8027 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8028 struct intel_crtc_config *pipe_config)
8029{
08a24034
DV		 8030#define PIPE_CONF_CHECK_I(name) \
8031 if (current_config->name != pipe_config->name) { \
8032 DRM_ERROR("mismatch in " #name " " \
8033 "(expected %i, found %i)\n", \
8034 current_config->name, \
8035 pipe_config->name); \
8036 return false; \
88adfff1
DV		 8037 }
8038
1bd1bd80
DV		 8039#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8040 if ((current_config->name ^ pipe_config->name) & (mask)) { \
8041 DRM_ERROR("mismatch in " #name " " \
8042 "(expected %i, found %i)\n", \
8043 current_config->name & (mask), \
8044 pipe_config->name & (mask)); \
8045 return false; \
8046 }
8047
eccb140b
DV		 8048 PIPE_CONF_CHECK_I(cpu_transcoder);
8049
08a24034
DV		 8050 PIPE_CONF_CHECK_I(has_pch_encoder);
8051 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8052 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8053 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8054 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8055 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8056 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8057
1bd1bd80
DV		 8058 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8059 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8060 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8061 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8062 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8063 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8064
8065 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8066 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8067 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8068 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8069 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8070 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8071
8072 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8073 DRM_MODE_FLAG_INTERLACE);
8074
045ac3b5
JB		 8075 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8076 DRM_MODE_FLAG_PHSYNC);
8077 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8078 DRM_MODE_FLAG_NHSYNC);
8079 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8080 DRM_MODE_FLAG_PVSYNC);
8081 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8082 DRM_MODE_FLAG_NVSYNC);
8083
1bd1bd80
DV		 8084 PIPE_CONF_CHECK_I(requested_mode.hdisplay);
8085 PIPE_CONF_CHECK_I(requested_mode.vdisplay);
8086
2fa2fe9a
DV		 8087 PIPE_CONF_CHECK_I(gmch_pfit.control);
8088 /* pfit ratios are autocomputed by the hw on gen4+ */
8089 if (INTEL_INFO(dev)->gen < 4)
8090 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8091 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
8092 PIPE_CONF_CHECK_I(pch_pfit.pos);
8093 PIPE_CONF_CHECK_I(pch_pfit.size);
8094
42db64ef
PZ		 8095 PIPE_CONF_CHECK_I(ips_enabled);
8096
08a24034 8097#undef PIPE_CONF_CHECK_I
1bd1bd80 8098#undef PIPE_CONF_CHECK_FLAGS
627eb5a3 8099
0e8ffe1b
DV		 8100 return true;
8101}
8102
b980514c 8103void
8af6cf88
DV		 8104intel_modeset_check_state(struct drm_device *dev)
8105{
0e8ffe1b 8106 drm_i915_private_t *dev_priv = dev->dev_private;
8af6cf88
DV		 8107 struct intel_crtc *crtc;
8108 struct intel_encoder *encoder;
8109 struct intel_connector *connector;
0e8ffe1b 8110 struct intel_crtc_config pipe_config;
8af6cf88
DV		 8111
8112 list_for_each_entry(connector, &dev->mode_config.connector_list,
8113 base.head) {
8114 /* This also checks the encoder/connector hw state with the
8115 * ->get_hw_state callbacks. */
8116 intel_connector_check_state(connector);
8117
8118 WARN(&connector->new_encoder->base != connector->base.encoder,
8119 "connector's staged encoder doesn't match current encoder\n");
8120 }
8121
8122 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8123 base.head) {
8124 bool enabled = false;
8125 bool active = false;
8126 enum pipe pipe, tracked_pipe;
8127
8128 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8129 encoder->base.base.id,
8130 drm_get_encoder_name(&encoder->base));
8131
8132 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8133 "encoder's stage crtc doesn't match current crtc\n");
8134 WARN(encoder->connectors_active && !encoder->base.crtc,
8135 "encoder's active_connectors set, but no crtc\n");
8136
8137 list_for_each_entry(connector, &dev->mode_config.connector_list,
8138 base.head) {
8139 if (connector->base.encoder != &encoder->base)
8140 continue;
8141 enabled = true;
8142 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8143 active = true;
8144 }
8145 WARN(!!encoder->base.crtc != enabled,
8146 "encoder's enabled state mismatch "
8147 "(expected %i, found %i)\n",
8148 !!encoder->base.crtc, enabled);
8149 WARN(active && !encoder->base.crtc,
8150 "active encoder with no crtc\n");
8151
8152 WARN(encoder->connectors_active != active,
8153 "encoder's computed active state doesn't match tracked active state "
8154 "(expected %i, found %i)\n", active, encoder->connectors_active);
8155
8156 active = encoder->get_hw_state(encoder, &pipe);
8157 WARN(active != encoder->connectors_active,
8158 "encoder's hw state doesn't match sw tracking "
8159 "(expected %i, found %i)\n",
8160 encoder->connectors_active, active);
8161
8162 if (!encoder->base.crtc)
8163 continue;
8164
8165 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
8166 WARN(active && pipe != tracked_pipe,
8167 "active encoder's pipe doesn't match"
8168 "(expected %i, found %i)\n",
8169 tracked_pipe, pipe);
8170
8171 }
8172
8173 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
8174 base.head) {
8175 bool enabled = false;
8176 bool active = false;
8177
045ac3b5
JB		 8178 memset(&pipe_config, 0, sizeof(pipe_config));
8179
8af6cf88
DV		 8180 DRM_DEBUG_KMS("[CRTC:%d]\n",
8181 crtc->base.base.id);
8182
8183 WARN(crtc->active && !crtc->base.enabled,
8184 "active crtc, but not enabled in sw tracking\n");
8185
8186 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8187 base.head) {
8188 if (encoder->base.crtc != &crtc->base)
8189 continue;
8190 enabled = true;
8191 if (encoder->connectors_active)
8192 active = true;
045ac3b5
JB		 8193 if (encoder->get_config)
8194 encoder->get_config(encoder, &pipe_config);
8af6cf88
DV		 8195 }
8196 WARN(active != crtc->active,
8197 "crtc's computed active state doesn't match tracked active state "
8198 "(expected %i, found %i)\n", active, crtc->active);
8199 WARN(enabled != crtc->base.enabled,
8200 "crtc's computed enabled state doesn't match tracked enabled state "
8201 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
8202
0e8ffe1b
DV		 8203 active = dev_priv->display.get_pipe_config(crtc,
8204 &pipe_config);
8205 WARN(crtc->active != active,
8206 "crtc active state doesn't match with hw state "
8207 "(expected %i, found %i)\n", crtc->active, active);
8208
c0b03411
DV		 8209 if (active &&
8210 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
8211 WARN(1, "pipe state doesn't match!\n");
8212 intel_dump_pipe_config(crtc, &pipe_config,
8213 "[hw state]");
8214 intel_dump_pipe_config(crtc, &crtc->config,
8215 "[sw state]");
8216 }
8af6cf88
DV		 8217 }
8218}
8219
f30da187
DV		 8220static int __intel_set_mode(struct drm_crtc *crtc,
8221 struct drm_display_mode *mode,
8222 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 8223{
8224 struct drm_device *dev = crtc->dev;
dbf2b54e 8225 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 8226 struct drm_display_mode *saved_mode, *saved_hwmode;
8227 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 8228 struct intel_crtc *intel_crtc;
8229 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 8230 int ret = 0;
a6778b3c 8231
3ac18232 8232 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 8233 if (!saved_mode)
8234 return -ENOMEM;
3ac18232 8235 saved_hwmode = saved_mode + 1;
a6778b3c 8236
e2e1ed41 8237 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 8238 &prepare_pipes, &disable_pipes);
8239
3ac18232
TG		 8240 *saved_hwmode = crtc->hwmode;
8241 *saved_mode = crtc->mode;
a6778b3c 8242
25c5b266
DV		 8243 /* Hack: Because we don't (yet) support global modeset on multiple
8244 * crtcs, we don't keep track of the new mode for more than one crtc.
8245 * Hence simply check whether any bit is set in modeset_pipes in all the
8246 * pieces of code that are not yet converted to deal with mutliple crtcs
8247 * changing their mode at the same time. */
25c5b266 8248 if (modeset_pipes) {
4e53c2e0 8249 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 8250 if (IS_ERR(pipe_config)) {
8251 ret = PTR_ERR(pipe_config);
8252 pipe_config = NULL;
8253
3ac18232 8254 goto out;
25c5b266 8255 }
c0b03411
DV		 8256 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
8257 "[modeset]");
25c5b266 8258 }
a6778b3c 8259
460da916
DV		 8260 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
8261 intel_crtc_disable(&intel_crtc->base);
8262
ea9d758d
DV		 8263 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
8264 if (intel_crtc->base.enabled)
8265 dev_priv->display.crtc_disable(&intel_crtc->base);
8266 }
a6778b3c 8267
6c4c86f5
DV		 8268 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
8269 * to set it here already despite that we pass it down the callchain.
f6e5b160 8270 */
b8cecdf5 8271 if (modeset_pipes) {
25c5b266 8272 crtc->mode = *mode;
b8cecdf5
DV		 8273 /* mode_set/enable/disable functions rely on a correct pipe
8274 * config. */
8275 to_intel_crtc(crtc)->config = *pipe_config;
8276 }
7758a113 8277
ea9d758d
DV		 8278 /* Only after disabling all output pipelines that will be changed can we
8279 * update the the output configuration. */
8280 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 8281
47fab737
DV		 8282 if (dev_priv->display.modeset_global_resources)
8283 dev_priv->display.modeset_global_resources(dev);
8284
a6778b3c
DV		 8285 /* Set up the DPLL and any encoders state that needs to adjust or depend
8286 * on the DPLL.
f6e5b160 8287 */
25c5b266 8288 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 8289 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 8290 x, y, fb);
8291 if (ret)
8292 goto done;
a6778b3c
DV		 8293 }
8294
8295 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 8296 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
8297 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 8298
25c5b266
DV		 8299 if (modeset_pipes) {
8300 /* Store real post-adjustment hardware mode. */
b8cecdf5 8301 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 8302
25c5b266
DV		 8303 /* Calculate and store various constants which
8304 * are later needed by vblank and swap-completion
8305 * timestamping. They are derived from true hwmode.
8306 */
8307 drm_calc_timestamping_constants(crtc);
8308 }
a6778b3c
DV		 8309
8310 /* FIXME: add subpixel order */
8311done:
c0c36b94 8312 if (ret && crtc->enabled) {
3ac18232
TG		 8313 crtc->hwmode = *saved_hwmode;
8314 crtc->mode = *saved_mode;
a6778b3c
DV		 8315 }
8316
3ac18232 8317out:
b8cecdf5 8318 kfree(pipe_config);
3ac18232 8319 kfree(saved_mode);
a6778b3c 8320 return ret;
f6e5b160
CW		 8321}
8322
f30da187
DV		 8323int intel_set_mode(struct drm_crtc *crtc,
8324 struct drm_display_mode *mode,
8325 int x, int y, struct drm_framebuffer *fb)
8326{
8327 int ret;
8328
8329 ret = __intel_set_mode(crtc, mode, x, y, fb);
8330
8331 if (ret == 0)
8332 intel_modeset_check_state(crtc->dev);
8333
8334 return ret;
8335}
8336
c0c36b94
CW		 8337void intel_crtc_restore_mode(struct drm_crtc *crtc)
8338{
8339 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
8340}
8341
25c5b266
DV		 8342#undef for_each_intel_crtc_masked
8343
d9e55608
DV		 8344static void intel_set_config_free(struct intel_set_config *config)
8345{
8346 if (!config)
8347 return;
8348
1aa4b628
DV		 8349 kfree(config->save_connector_encoders);
8350 kfree(config->save_encoder_crtcs);
d9e55608
DV		 8351 kfree(config);
8352}
8353
85f9eb71
DV		 8354static int intel_set_config_save_state(struct drm_device *dev,
8355 struct intel_set_config *config)
8356{
85f9eb71
DV		 8357 struct drm_encoder *encoder;
8358 struct drm_connector *connector;
8359 int count;
8360
1aa4b628
DV		 8361 config->save_encoder_crtcs =
8362 kcalloc(dev->mode_config.num_encoder,
8363 sizeof(struct drm_crtc *), GFP_KERNEL);
8364 if (!config->save_encoder_crtcs)
85f9eb71
DV		 8365 return -ENOMEM;
8366
1aa4b628
DV		 8367 config->save_connector_encoders =
8368 kcalloc(dev->mode_config.num_connector,
8369 sizeof(struct drm_encoder *), GFP_KERNEL);
8370 if (!config->save_connector_encoders)
85f9eb71
DV		 8371 return -ENOMEM;
8372
8373 /* Copy data. Note that driver private data is not affected.
8374 * Should anything bad happen only the expected state is
8375 * restored, not the drivers personal bookkeeping.
8376 */
85f9eb71
DV		 8377 count = 0;
8378 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 8379 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 8380 }
8381
8382 count = 0;
8383 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 8384 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 8385 }
8386
8387 return 0;
8388}
8389
8390static void intel_set_config_restore_state(struct drm_device *dev,
8391 struct intel_set_config *config)
8392{
9a935856
DV		 8393 struct intel_encoder *encoder;
8394 struct intel_connector *connector;
85f9eb71
DV		 8395 int count;
8396
85f9eb71 8397 count = 0;
9a935856
DV		 8398 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8399 encoder->new_crtc =
8400 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 8401 }
8402
8403 count = 0;
9a935856
DV		 8404 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
8405 connector->new_encoder =
8406 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 8407 }
8408}
8409
5e2b584e
DV		 8410static void
8411intel_set_config_compute_mode_changes(struct drm_mode_set *set,
8412 struct intel_set_config *config)
8413{
8414
8415 /* We should be able to check here if the fb has the same properties
8416 * and then just flip_or_move it */
8417 if (set->crtc->fb != set->fb) {
8418 /* If we have no fb then treat it as a full mode set */
8419 if (set->crtc->fb == NULL) {
8420 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
8421 config->mode_changed = true;
8422 } else if (set->fb == NULL) {
8423 config->mode_changed = true;
72f4901e
DV		 8424 } else if (set->fb->pixel_format !=
8425 set->crtc->fb->pixel_format) {
5e2b584e
DV		 8426 config->mode_changed = true;
8427 } else
8428 config->fb_changed = true;
8429 }
8430
835c5873 8431 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 8432 config->fb_changed = true;
8433
8434 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
8435 DRM_DEBUG_KMS("modes are different, full mode set\n");
8436 drm_mode_debug_printmodeline(&set->crtc->mode);
8437 drm_mode_debug_printmodeline(set->mode);
8438 config->mode_changed = true;
8439 }
8440}
8441
2e431051 8442static int
9a935856
DV		 8443intel_modeset_stage_output_state(struct drm_device *dev,
8444 struct drm_mode_set *set,
8445 struct intel_set_config *config)
50f56119 8446{
85f9eb71 8447 struct drm_crtc *new_crtc;
9a935856
DV		 8448 struct intel_connector *connector;
8449 struct intel_encoder *encoder;
2e431051 8450 int count, ro;
50f56119 8451
9abdda74 8452 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 8453 * of connectors. For paranoia, double-check this. */
8454 WARN_ON(!set->fb && (set->num_connectors != 0));
8455 WARN_ON(set->fb && (set->num_connectors == 0));
8456
50f56119 8457 count = 0;
9a935856
DV		 8458 list_for_each_entry(connector, &dev->mode_config.connector_list,
8459 base.head) {
8460 /* Otherwise traverse passed in connector list and get encoders
8461 * for them. */
50f56119 8462 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 8463 if (set->connectors[ro] == &connector->base) {
8464 connector->new_encoder = connector->encoder;
50f56119
DV		 8465 break;
8466 }
8467 }
8468
9a935856
DV		 8469 /* If we disable the crtc, disable all its connectors. Also, if
8470 * the connector is on the changing crtc but not on the new
8471 * connector list, disable it. */
8472 if ((!set->fb || ro == set->num_connectors) &&
8473 connector->base.encoder &&
8474 connector->base.encoder->crtc == set->crtc) {
8475 connector->new_encoder = NULL;
8476
8477 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
8478 connector->base.base.id,
8479 drm_get_connector_name(&connector->base));
8480 }
8481
8482
8483 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 8484 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 8485 config->mode_changed = true;
50f56119
DV		 8486 }
8487 }
9a935856 8488 /* connector->new_encoder is now updated for all connectors. */
50f56119 8489
9a935856 8490 /* Update crtc of enabled connectors. */
50f56119 8491 count = 0;
9a935856
DV		 8492 list_for_each_entry(connector, &dev->mode_config.connector_list,
8493 base.head) {
8494 if (!connector->new_encoder)
50f56119
DV		 8495 continue;
8496
9a935856 8497 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 8498
8499 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 8500 if (set->connectors[ro] == &connector->base)
50f56119
DV		 8501 new_crtc = set->crtc;
8502 }
8503
8504 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 8505 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
8506 new_crtc)) {
5e2b584e 8507 return -EINVAL;
50f56119 8508 }
9a935856
DV		 8509 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
8510
8511 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
8512 connector->base.base.id,
8513 drm_get_connector_name(&connector->base),
8514 new_crtc->base.id);
8515 }
8516
8517 /* Check for any encoders that needs to be disabled. */
8518 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8519 base.head) {
8520 list_for_each_entry(connector,
8521 &dev->mode_config.connector_list,
8522 base.head) {
8523 if (connector->new_encoder == encoder) {
8524 WARN_ON(!connector->new_encoder->new_crtc);
8525
8526 goto next_encoder;
8527 }
8528 }
8529 encoder->new_crtc = NULL;
8530next_encoder:
8531 /* Only now check for crtc changes so we don't miss encoders
8532 * that will be disabled. */
8533 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 8534 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 8535 config->mode_changed = true;
50f56119
DV		 8536 }
8537 }
9a935856 8538 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 8539
2e431051
DV		 8540 return 0;
8541}
8542
8543static int intel_crtc_set_config(struct drm_mode_set *set)
8544{
8545 struct drm_device *dev;
2e431051
DV		 8546 struct drm_mode_set save_set;
8547 struct intel_set_config *config;
8548 int ret;
2e431051 8549
8d3e375e
DV		 8550 BUG_ON(!set);
8551 BUG_ON(!set->crtc);
8552 BUG_ON(!set->crtc->helper_private);
2e431051 8553
7e53f3a4
DV		 8554 /* Enforce sane interface api - has been abused by the fb helper. */
8555 BUG_ON(!set->mode && set->fb);
8556 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 8557
2e431051
DV		 8558 if (set->fb) {
8559 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
8560 set->crtc->base.id, set->fb->base.id,
8561 (int)set->num_connectors, set->x, set->y);
8562 } else {
8563 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 8564 }
8565
8566 dev = set->crtc->dev;
8567
8568 ret = -ENOMEM;
8569 config = kzalloc(sizeof(*config), GFP_KERNEL);
8570 if (!config)
8571 goto out_config;
8572
8573 ret = intel_set_config_save_state(dev, config);
8574 if (ret)
8575 goto out_config;
8576
8577 save_set.crtc = set->crtc;
8578 save_set.mode = &set->crtc->mode;
8579 save_set.x = set->crtc->x;
8580 save_set.y = set->crtc->y;
8581 save_set.fb = set->crtc->fb;
8582
8583 /* Compute whether we need a full modeset, only an fb base update or no
8584 * change at all. In the future we might also check whether only the
8585 * mode changed, e.g. for LVDS where we only change the panel fitter in
8586 * such cases. */
8587 intel_set_config_compute_mode_changes(set, config);
8588
9a935856 8589 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8590 if (ret)
8591 goto fail;
8592
5e2b584e 8593 if (config->mode_changed) {
c0c36b94
CW		 8594 ret = intel_set_mode(set->crtc, set->mode,
8595 set->x, set->y, set->fb);
8596 if (ret) {
8597 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8598 set->crtc->base.id, ret);
87f1faa6
DV		 8599 goto fail;
8600 }
5e2b584e 8601 } else if (config->fb_changed) {
4878cae2
VS		 8602 intel_crtc_wait_for_pending_flips(set->crtc);
8603
4f660f49 8604 ret = intel_pipe_set_base(set->crtc,
94352cf9 8605 set->x, set->y, set->fb);
50f56119
DV		 8606 }
8607
d9e55608
DV		 8608 intel_set_config_free(config);
8609
50f56119
DV		 8610 return 0;
8611
8612fail:
85f9eb71 8613 intel_set_config_restore_state(dev, config);
50f56119
DV		 8614
8615 /* Try to restore the config */
5e2b584e 8616 if (config->mode_changed &&
c0c36b94
CW		 8617 intel_set_mode(save_set.crtc, save_set.mode,
8618 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8619 DRM_ERROR("failed to restore config after modeset failure\n");
8620
d9e55608
DV		 8621out_config:
8622 intel_set_config_free(config);
50f56119
DV		 8623 return ret;
8624}
f6e5b160
CW		 8625
8626static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8627 .cursor_set = intel_crtc_cursor_set,
8628 .cursor_move = intel_crtc_cursor_move,
8629 .gamma_set = intel_crtc_gamma_set,
50f56119 8630 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8631 .destroy = intel_crtc_destroy,
8632 .page_flip = intel_crtc_page_flip,
8633};
8634
79f689aa
PZ		 8635static void intel_cpu_pll_init(struct drm_device *dev)
8636{
affa9354 8637 if (HAS_DDI(dev))
79f689aa
PZ		 8638 intel_ddi_pll_init(dev);
8639}
8640
ee7b9f93
JB		 8641static void intel_pch_pll_init(struct drm_device *dev)
8642{
8643 drm_i915_private_t *dev_priv = dev->dev_private;
8644 int i;
8645
8646 if (dev_priv->num_pch_pll == 0) {
8647 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8648 return;
8649 }
8650
8651 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8652 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8653 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8654 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8655 }
8656}
8657
b358d0a6 8658static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8659{
22fd0fab 8660 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8661 struct intel_crtc *intel_crtc;
8662 int i;
8663
8664 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8665 if (intel_crtc == NULL)
8666 return;
8667
8668 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8669
8670 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8671 for (i = 0; i < 256; i++) {
8672 intel_crtc->lut_r[i] = i;
8673 intel_crtc->lut_g[i] = i;
8674 intel_crtc->lut_b[i] = i;
8675 }
8676
80824003
JB		 8677 /* Swap pipes & planes for FBC on pre-965 */
8678 intel_crtc->pipe = pipe;
8679 intel_crtc->plane = pipe;
e2e767ab 8680 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8681 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8682 intel_crtc->plane = !pipe;
80824003
JB		 8683 }
8684
22fd0fab
JB		 8685 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8686 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8687 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8688 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8689
79e53945 8690 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8691}
8692
08d7b3d1 8693int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8694 struct drm_file *file)
08d7b3d1 8695{
08d7b3d1 8696 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8697 struct drm_mode_object *drmmode_obj;
8698 struct intel_crtc *crtc;
08d7b3d1 8699
1cff8f6b
DV		 8700 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8701 return -ENODEV;
08d7b3d1 8702
c05422d5
DV		 8703 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8704 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8705
c05422d5 8706 if (!drmmode_obj) {
08d7b3d1
CW		 8707 DRM_ERROR("no such CRTC id\n");
8708 return -EINVAL;
8709 }
8710
c05422d5
DV		 8711 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8712 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8713
c05422d5 8714 return 0;
08d7b3d1
CW		 8715}
8716
66a9278e 8717static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8718{
66a9278e
DV		 8719 struct drm_device *dev = encoder->base.dev;
8720 struct intel_encoder *source_encoder;
79e53945 8721 int index_mask = 0;
79e53945
JB		 8722 int entry = 0;
8723
66a9278e
DV		 8724 list_for_each_entry(source_encoder,
8725 &dev->mode_config.encoder_list, base.head) {
8726
8727 if (encoder == source_encoder)
79e53945 8728 index_mask |= (1 << entry);
66a9278e
DV		 8729
8730 /* Intel hw has only one MUX where enocoders could be cloned. */
8731 if (encoder->cloneable && source_encoder->cloneable)
8732 index_mask |= (1 << entry);
8733
79e53945
JB		 8734 entry++;
8735 }
4ef69c7a 8736
79e53945
JB		 8737 return index_mask;
8738}
8739
4d302442
CW		 8740static bool has_edp_a(struct drm_device *dev)
8741{
8742 struct drm_i915_private *dev_priv = dev->dev_private;
8743
8744 if (!IS_MOBILE(dev))
8745 return false;
8746
8747 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8748 return false;
8749
8750 if (IS_GEN5(dev) &&
8751 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8752 return false;
8753
8754 return true;
8755}
8756
79e53945
JB		 8757static void intel_setup_outputs(struct drm_device *dev)
8758{
725e30ad 8759 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8760 struct intel_encoder *encoder;
cb0953d7 8761 bool dpd_is_edp = false;
f3cfcba6 8762 bool has_lvds;
79e53945 8763
f3cfcba6 8764 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8765 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8766 /* disable the panel fitter on everything but LVDS */
8767 I915_WRITE(PFIT_CONTROL, 0);
8768 }
79e53945 8769
c40c0f5b 8770 if (!IS_ULT(dev))
79935fca 8771 intel_crt_init(dev);
cb0953d7 8772
affa9354 8773 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8774 int found;
8775
8776 /* Haswell uses DDI functions to detect digital outputs */
8777 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8778 /* DDI A only supports eDP */
8779 if (found)
8780 intel_ddi_init(dev, PORT_A);
8781
8782 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8783 * register */
8784 found = I915_READ(SFUSE_STRAP);
8785
8786 if (found & SFUSE_STRAP_DDIB_DETECTED)
8787 intel_ddi_init(dev, PORT_B);
8788 if (found & SFUSE_STRAP_DDIC_DETECTED)
8789 intel_ddi_init(dev, PORT_C);
8790 if (found & SFUSE_STRAP_DDID_DETECTED)
8791 intel_ddi_init(dev, PORT_D);
8792 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8793 int found;
270b3042
DV		 8794 dpd_is_edp = intel_dpd_is_edp(dev);
8795
8796 if (has_edp_a(dev))
8797 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8798
dc0fa718 8799 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 8800 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8801 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8802 if (!found)
e2debe91 8803 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 8804 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8805 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8806 }
8807
dc0fa718 8808 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 8809 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 8810
dc0fa718 8811 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 8812 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 8813
5eb08b69 8814 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8815 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8816
270b3042 8817 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8818 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8819 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8820 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8821 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8822 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8823
dc0fa718 8824 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 8825 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
8826 PORT_B);
67cfc203
VS		 8827 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8828 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 8829 }
103a196f 8830 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8831 bool found = false;
7d57382e 8832
e2debe91 8833 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8834 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 8835 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 8836 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8837 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 8838 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 8839 }
27185ae1 8840
e7281eab 8841 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8842 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 8843 }
13520b05
KH		 8844
8845 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8846
e2debe91 8847 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 8848 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 8849 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 8850 }
27185ae1 8851
e2debe91 8852 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 8853
b01f2c3a
JB		 8854 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8855 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 8856 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 8857 }
e7281eab 8858 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 8859 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 8860 }
27185ae1 8861
b01f2c3a 8862 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 8863 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 8864 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 8865 } else if (IS_GEN2(dev))
79e53945
JB		 8866 intel_dvo_init(dev);
8867
103a196f 8868 if (SUPPORTS_TV(dev))
79e53945
JB		 8869 intel_tv_init(dev);
8870
4ef69c7a
CW		 8871 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8872 encoder->base.possible_crtcs = encoder->crtc_mask;
8873 encoder->base.possible_clones =
66a9278e 8874 intel_encoder_clones(encoder);
79e53945 8875 }
47356eb6 8876
dde86e2d 8877 intel_init_pch_refclk(dev);
270b3042
DV		 8878
8879 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8880}
8881
8882static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8883{
8884 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8885
8886 drm_framebuffer_cleanup(fb);
05394f39 8887 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8888
8889 kfree(intel_fb);
8890}
8891
8892static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8893 struct drm_file *file,
79e53945
JB		 8894 unsigned int *handle)
8895{
8896 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8897 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8898
05394f39 8899 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8900}
8901
8902static const struct drm_framebuffer_funcs intel_fb_funcs = {
8903 .destroy = intel_user_framebuffer_destroy,
8904 .create_handle = intel_user_framebuffer_create_handle,
8905};
8906
38651674
DA		 8907int intel_framebuffer_init(struct drm_device *dev,
8908 struct intel_framebuffer *intel_fb,
308e5bcb 8909 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8910 struct drm_i915_gem_object *obj)
79e53945 8911{
79e53945
JB		 8912 int ret;
8913
c16ed4be
CW		 8914 if (obj->tiling_mode == I915_TILING_Y) {
8915 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 8916 return -EINVAL;
c16ed4be 8917 }
57cd6508 8918
c16ed4be
CW		 8919 if (mode_cmd->pitches[0] & 63) {
8920 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
8921 mode_cmd->pitches[0]);
57cd6508 8922 return -EINVAL;
c16ed4be 8923 }
57cd6508 8924
5d7bd705 8925 /* FIXME <= Gen4 stride limits are bit unclear */
c16ed4be
CW		 8926 if (mode_cmd->pitches[0] > 32768) {
8927 DRM_DEBUG("pitch (%d) must be at less than 32768\n",
8928 mode_cmd->pitches[0]);
5d7bd705 8929 return -EINVAL;
c16ed4be 8930 }
5d7bd705
VS		 8931
8932 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 8933 mode_cmd->pitches[0] != obj->stride) {
8934 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
8935 mode_cmd->pitches[0], obj->stride);
5d7bd705 8936 return -EINVAL;
c16ed4be 8937 }
5d7bd705 8938
57779d06 8939 /* Reject formats not supported by any plane early. */
308e5bcb 8940 switch (mode_cmd->pixel_format) {
57779d06 8941 case DRM_FORMAT_C8:
04b3924d
VS		 8942 case DRM_FORMAT_RGB565:
8943 case DRM_FORMAT_XRGB8888:
8944 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8945 break;
8946 case DRM_FORMAT_XRGB1555:
8947 case DRM_FORMAT_ARGB1555:
c16ed4be
CW		 8948 if (INTEL_INFO(dev)->gen > 3) {
8949 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8950 return -EINVAL;
c16ed4be 8951 }
57779d06
VS		 8952 break;
8953 case DRM_FORMAT_XBGR8888:
8954 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8955 case DRM_FORMAT_XRGB2101010:
8956 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8957 case DRM_FORMAT_XBGR2101010:
8958 case DRM_FORMAT_ABGR2101010:
c16ed4be
CW		 8959 if (INTEL_INFO(dev)->gen < 4) {
8960 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8961 return -EINVAL;
c16ed4be 8962 }
b5626747 8963 break;
04b3924d
VS		 8964 case DRM_FORMAT_YUYV:
8965 case DRM_FORMAT_UYVY:
8966 case DRM_FORMAT_YVYU:
8967 case DRM_FORMAT_VYUY:
c16ed4be
CW		 8968 if (INTEL_INFO(dev)->gen < 5) {
8969 DRM_DEBUG("invalid format: 0x%08x\n", mode_cmd->pixel_format);
57779d06 8970 return -EINVAL;
c16ed4be 8971 }
57cd6508
CW		 8972 break;
8973 default:
c16ed4be 8974 DRM_DEBUG("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8975 return -EINVAL;
8976 }
8977
90f9a336
VS		 8978 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8979 if (mode_cmd->offsets[0] != 0)
8980 return -EINVAL;
8981
c7d73f6a
DV		 8982 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8983 intel_fb->obj = obj;
8984
79e53945
JB		 8985 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8986 if (ret) {
8987 DRM_ERROR("framebuffer init failed %d\n", ret);
8988 return ret;
8989 }
8990
79e53945
JB		 8991 return 0;
8992}
8993
79e53945
JB		 8994static struct drm_framebuffer *
8995intel_user_framebuffer_create(struct drm_device *dev,
8996 struct drm_file *filp,
308e5bcb 8997 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8998{
05394f39 8999 struct drm_i915_gem_object *obj;
79e53945 9000
308e5bcb
JB		 9001 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
9002 mode_cmd->handles[0]));
c8725226 9003 if (&obj->base == NULL)
cce13ff7 9004 return ERR_PTR(-ENOENT);
79e53945 9005
d2dff872 9006 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 9007}
9008
79e53945 9009static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 9010 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 9011 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 9012};
9013
e70236a8
JB		 9014/* Set up chip specific display functions */
9015static void intel_init_display(struct drm_device *dev)
9016{
9017 struct drm_i915_private *dev_priv = dev->dev_private;
9018
ee9300bb
DV		 9019 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
9020 dev_priv->display.find_dpll = g4x_find_best_dpll;
9021 else if (IS_VALLEYVIEW(dev))
9022 dev_priv->display.find_dpll = vlv_find_best_dpll;
9023 else if (IS_PINEVIEW(dev))
9024 dev_priv->display.find_dpll = pnv_find_best_dpll;
9025 else
9026 dev_priv->display.find_dpll = i9xx_find_best_dpll;
9027
affa9354 9028 if (HAS_DDI(dev)) {
0e8ffe1b 9029 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 9030 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 9031 dev_priv->display.crtc_enable = haswell_crtc_enable;
9032 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 9033 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 9034 dev_priv->display.update_plane = ironlake_update_plane;
9035 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 9036 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 9037 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 9038 dev_priv->display.crtc_enable = ironlake_crtc_enable;
9039 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 9040 dev_priv->display.off = ironlake_crtc_off;
17638cd6 9041 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 9042 } else if (IS_VALLEYVIEW(dev)) {
9043 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
9044 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
9045 dev_priv->display.crtc_enable = valleyview_crtc_enable;
9046 dev_priv->display.crtc_disable = i9xx_crtc_disable;
9047 dev_priv->display.off = i9xx_crtc_off;
9048 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9049 } else {
0e8ffe1b 9050 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 9051 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 9052 dev_priv->display.crtc_enable = i9xx_crtc_enable;
9053 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 9054 dev_priv->display.off = i9xx_crtc_off;
17638cd6 9055 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 9056 }
e70236a8 9057
e70236a8 9058 /* Returns the core display clock speed */
25eb05fc
JB		 9059 if (IS_VALLEYVIEW(dev))
9060 dev_priv->display.get_display_clock_speed =
9061 valleyview_get_display_clock_speed;
9062 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 9063 dev_priv->display.get_display_clock_speed =
9064 i945_get_display_clock_speed;
9065 else if (IS_I915G(dev))
9066 dev_priv->display.get_display_clock_speed =
9067 i915_get_display_clock_speed;
f2b115e6 9068 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 9069 dev_priv->display.get_display_clock_speed =
9070 i9xx_misc_get_display_clock_speed;
9071 else if (IS_I915GM(dev))
9072 dev_priv->display.get_display_clock_speed =
9073 i915gm_get_display_clock_speed;
9074 else if (IS_I865G(dev))
9075 dev_priv->display.get_display_clock_speed =
9076 i865_get_display_clock_speed;
f0f8a9ce 9077 else if (IS_I85X(dev))
e70236a8
JB		 9078 dev_priv->display.get_display_clock_speed =
9079 i855_get_display_clock_speed;
9080 else /* 852, 830 */
9081 dev_priv->display.get_display_clock_speed =
9082 i830_get_display_clock_speed;
9083
7f8a8569 9084 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 9085 if (IS_GEN5(dev)) {
674cf967 9086 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 9087 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 9088 } else if (IS_GEN6(dev)) {
674cf967 9089 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 9090 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 9091 } else if (IS_IVYBRIDGE(dev)) {
9092 /* FIXME: detect B0+ stepping and use auto training */
9093 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 9094 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 9095 dev_priv->display.modeset_global_resources =
9096 ivb_modeset_global_resources;
c82e4d26
ED		 9097 } else if (IS_HASWELL(dev)) {
9098 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 9099 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 9100 dev_priv->display.modeset_global_resources =
9101 haswell_modeset_global_resources;
a0e63c22 9102 }
6067aaea 9103 } else if (IS_G4X(dev)) {
e0dac65e 9104 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 9105 }
8c9f3aaf
JB		 9106
9107 /* Default just returns -ENODEV to indicate unsupported */
9108 dev_priv->display.queue_flip = intel_default_queue_flip;
9109
9110 switch (INTEL_INFO(dev)->gen) {
9111 case 2:
9112 dev_priv->display.queue_flip = intel_gen2_queue_flip;
9113 break;
9114
9115 case 3:
9116 dev_priv->display.queue_flip = intel_gen3_queue_flip;
9117 break;
9118
9119 case 4:
9120 case 5:
9121 dev_priv->display.queue_flip = intel_gen4_queue_flip;
9122 break;
9123
9124 case 6:
9125 dev_priv->display.queue_flip = intel_gen6_queue_flip;
9126 break;
7c9017e5
JB		 9127 case 7:
9128 dev_priv->display.queue_flip = intel_gen7_queue_flip;
9129 break;
8c9f3aaf 9130 }
e70236a8
JB		 9131}
9132
b690e96c
JB		 9133/*
9134 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
9135 * resume, or other times. This quirk makes sure that's the case for
9136 * affected systems.
9137 */
0206e353 9138static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 9139{
9140 struct drm_i915_private *dev_priv = dev->dev_private;
9141
9142 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 9143 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 9144}
9145
435793df
KP		 9146/*
9147 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
9148 */
9149static void quirk_ssc_force_disable(struct drm_device *dev)
9150{
9151 struct drm_i915_private *dev_priv = dev->dev_private;
9152 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 9153 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 9154}
9155
4dca20ef 9156/*
5a15ab5b
CE		 9157 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
9158 * brightness value
4dca20ef
CE		 9159 */
9160static void quirk_invert_brightness(struct drm_device *dev)
9161{
9162 struct drm_i915_private *dev_priv = dev->dev_private;
9163 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 9164 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 9165}
9166
b690e96c
JB		 9167struct intel_quirk {
9168 int device;
9169 int subsystem_vendor;
9170 int subsystem_device;
9171 void (*hook)(struct drm_device *dev);
9172};
9173
5f85f176
EE		 9174/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
9175struct intel_dmi_quirk {
9176 void (*hook)(struct drm_device *dev);
9177 const struct dmi_system_id (*dmi_id_list)[];
9178};
9179
9180static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
9181{
9182 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
9183 return 1;
9184}
9185
9186static const struct intel_dmi_quirk intel_dmi_quirks[] = {
9187 {
9188 .dmi_id_list = &(const struct dmi_system_id[]) {
9189 {
9190 .callback = intel_dmi_reverse_brightness,
9191 .ident = "NCR Corporation",
9192 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
9193 DMI_MATCH(DMI_PRODUCT_NAME, ""),
9194 },
9195 },
9196 { } /* terminating entry */
9197 },
9198 .hook = quirk_invert_brightness,
9199 },
9200};
9201
c43b5634 9202static struct intel_quirk intel_quirks[] = {
b690e96c 9203 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 9204 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 9205
b690e96c
JB		 9206 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
9207 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
9208
b690e96c
JB		 9209 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
9210 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
9211
ccd0d36e 9212 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 9213 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 9214 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 9215
9216 /* Lenovo U160 cannot use SSC on LVDS */
9217 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 9218
9219 /* Sony Vaio Y cannot use SSC on LVDS */
9220 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 9221
9222 /* Acer Aspire 5734Z must invert backlight brightness */
9223 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 9224
9225 /* Acer/eMachines G725 */
9226 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 9227
9228 /* Acer/eMachines e725 */
9229 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 9230
9231 /* Acer/Packard Bell NCL20 */
9232 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
ac4199e0
DV		 9233
9234 /* Acer Aspire 4736Z */
9235 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
b690e96c
JB		 9236};
9237
9238static void intel_init_quirks(struct drm_device *dev)
9239{
9240 struct pci_dev *d = dev->pdev;
9241 int i;
9242
9243 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
9244 struct intel_quirk *q = &intel_quirks[i];
9245
9246 if (d->device == q->device &&
9247 (d->subsystem_vendor == q->subsystem_vendor ||
9248 q->subsystem_vendor == PCI_ANY_ID) &&
9249 (d->subsystem_device == q->subsystem_device ||
9250 q->subsystem_device == PCI_ANY_ID))
9251 q->hook(dev);
9252 }
5f85f176
EE		 9253 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
9254 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
9255 intel_dmi_quirks[i].hook(dev);
9256 }
b690e96c
JB		 9257}
9258
9cce37f4
JB		 9259/* Disable the VGA plane that we never use */
9260static void i915_disable_vga(struct drm_device *dev)
9261{
9262 struct drm_i915_private *dev_priv = dev->dev_private;
9263 u8 sr1;
766aa1c4 9264 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 9265
9266 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 9267 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 9268 sr1 = inb(VGA_SR_DATA);
9269 outb(sr1 | 1<<5, VGA_SR_DATA);
9270 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
9271 udelay(300);
9272
9273 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9274 POSTING_READ(vga_reg);
9275}
9276
f817586c
DV		 9277void intel_modeset_init_hw(struct drm_device *dev)
9278{
fa42e23c 9279 intel_init_power_well(dev);
0232e927 9280
a8f78b58
ED		 9281 intel_prepare_ddi(dev);
9282
f817586c
DV		 9283 intel_init_clock_gating(dev);
9284
79f5b2c7 9285 mutex_lock(&dev->struct_mutex);
8090c6b9 9286 intel_enable_gt_powersave(dev);
79f5b2c7 9287 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 9288}
9289
7d708ee4
ID		 9290void intel_modeset_suspend_hw(struct drm_device *dev)
9291{
9292 intel_suspend_hw(dev);
9293}
9294
79e53945
JB		 9295void intel_modeset_init(struct drm_device *dev)
9296{
652c393a 9297 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 9298 int i, j, ret;
79e53945
JB		 9299
9300 drm_mode_config_init(dev);
9301
9302 dev->mode_config.min_width = 0;
9303 dev->mode_config.min_height = 0;
9304
019d96cb
DA		 9305 dev->mode_config.preferred_depth = 24;
9306 dev->mode_config.prefer_shadow = 1;
9307
e6ecefaa 9308 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 9309
b690e96c
JB		 9310 intel_init_quirks(dev);
9311
1fa61106
ED		 9312 intel_init_pm(dev);
9313
e3c74757
BW		 9314 if (INTEL_INFO(dev)->num_pipes == 0)
9315 return;
9316
e70236a8
JB		 9317 intel_init_display(dev);
9318
a6c45cf0
CW		 9319 if (IS_GEN2(dev)) {
9320 dev->mode_config.max_width = 2048;
9321 dev->mode_config.max_height = 2048;
9322 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9323 dev->mode_config.max_width = 4096;
9324 dev->mode_config.max_height = 4096;
79e53945 9325 } else {
a6c45cf0
CW		 9326 dev->mode_config.max_width = 8192;
9327 dev->mode_config.max_height = 8192;
79e53945 9328 }
5d4545ae 9329 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 9330
28c97730 9331 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 9332 INTEL_INFO(dev)->num_pipes,
9333 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 9334
7eb552ae 9335 for (i = 0; i < INTEL_INFO(dev)->num_pipes; i++) {
79e53945 9336 intel_crtc_init(dev, i);
7f1f3851
JB		 9337 for (j = 0; j < dev_priv->num_plane; j++) {
9338 ret = intel_plane_init(dev, i, j);
9339 if (ret)
06da8da2
VS		 9340 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
9341 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 9342 }
79e53945
JB		 9343 }
9344
79f689aa 9345 intel_cpu_pll_init(dev);
ee7b9f93
JB		 9346 intel_pch_pll_init(dev);
9347
9cce37f4
JB		 9348 /* Just disable it once at startup */
9349 i915_disable_vga(dev);
79e53945 9350 intel_setup_outputs(dev);
11be49eb
CW		 9351
9352 /* Just in case the BIOS is doing something questionable. */
9353 intel_disable_fbc(dev);
2c7111db
CW		 9354}
9355
24929352
DV		 9356static void
9357intel_connector_break_all_links(struct intel_connector *connector)
9358{
9359 connector->base.dpms = DRM_MODE_DPMS_OFF;
9360 connector->base.encoder = NULL;
9361 connector->encoder->connectors_active = false;
9362 connector->encoder->base.crtc = NULL;
9363}
9364
7fad798e
DV		 9365static void intel_enable_pipe_a(struct drm_device *dev)
9366{
9367 struct intel_connector *connector;
9368 struct drm_connector *crt = NULL;
9369 struct intel_load_detect_pipe load_detect_temp;
9370
9371 /* We can't just switch on the pipe A, we need to set things up with a
9372 * proper mode and output configuration. As a gross hack, enable pipe A
9373 * by enabling the load detect pipe once. */
9374 list_for_each_entry(connector,
9375 &dev->mode_config.connector_list,
9376 base.head) {
9377 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
9378 crt = &connector->base;
9379 break;
9380 }
9381 }
9382
9383 if (!crt)
9384 return;
9385
9386 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
9387 intel_release_load_detect_pipe(crt, &load_detect_temp);
9388
652c393a 9389
7fad798e
DV		 9390}
9391
fa555837
DV		 9392static bool
9393intel_check_plane_mapping(struct intel_crtc *crtc)
9394{
7eb552ae
BW		 9395 struct drm_device *dev = crtc->base.dev;
9396 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 9397 u32 reg, val;
9398
7eb552ae 9399 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 9400 return true;
9401
9402 reg = DSPCNTR(!crtc->plane);
9403 val = I915_READ(reg);
9404
9405 if ((val & DISPLAY_PLANE_ENABLE) &&
9406 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
9407 return false;
9408
9409 return true;
9410}
9411
24929352
DV		 9412static void intel_sanitize_crtc(struct intel_crtc *crtc)
9413{
9414 struct drm_device *dev = crtc->base.dev;
9415 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 9416 u32 reg;
24929352 9417
24929352 9418 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 9419 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 9420 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
9421
9422 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 9423 * disable the crtc (and hence change the state) if it is wrong. Note
9424 * that gen4+ has a fixed plane -> pipe mapping. */
9425 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 9426 struct intel_connector *connector;
9427 bool plane;
9428
24929352
DV		 9429 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
9430 crtc->base.base.id);
9431
9432 /* Pipe has the wrong plane attached and the plane is active.
9433 * Temporarily change the plane mapping and disable everything
9434 * ... */
9435 plane = crtc->plane;
9436 crtc->plane = !plane;
9437 dev_priv->display.crtc_disable(&crtc->base);
9438 crtc->plane = plane;
9439
9440 /* ... and break all links. */
9441 list_for_each_entry(connector, &dev->mode_config.connector_list,
9442 base.head) {
9443 if (connector->encoder->base.crtc != &crtc->base)
9444 continue;
9445
9446 intel_connector_break_all_links(connector);
9447 }
9448
9449 WARN_ON(crtc->active);
9450 crtc->base.enabled = false;
9451 }
24929352 9452
7fad798e
DV		 9453 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
9454 crtc->pipe == PIPE_A && !crtc->active) {
9455 /* BIOS forgot to enable pipe A, this mostly happens after
9456 * resume. Force-enable the pipe to fix this, the update_dpms
9457 * call below we restore the pipe to the right state, but leave
9458 * the required bits on. */
9459 intel_enable_pipe_a(dev);
9460 }
9461
24929352
DV		 9462 /* Adjust the state of the output pipe according to whether we
9463 * have active connectors/encoders. */
9464 intel_crtc_update_dpms(&crtc->base);
9465
9466 if (crtc->active != crtc->base.enabled) {
9467 struct intel_encoder *encoder;
9468
9469 /* This can happen either due to bugs in the get_hw_state
9470 * functions or because the pipe is force-enabled due to the
9471 * pipe A quirk. */
9472 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
9473 crtc->base.base.id,
9474 crtc->base.enabled ? "enabled" : "disabled",
9475 crtc->active ? "enabled" : "disabled");
9476
9477 crtc->base.enabled = crtc->active;
9478
9479 /* Because we only establish the connector -> encoder ->
9480 * crtc links if something is active, this means the
9481 * crtc is now deactivated. Break the links. connector
9482 * -> encoder links are only establish when things are
9483 * actually up, hence no need to break them. */
9484 WARN_ON(crtc->active);
9485
9486 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
9487 WARN_ON(encoder->connectors_active);
9488 encoder->base.crtc = NULL;
9489 }
9490 }
9491}
9492
9493static void intel_sanitize_encoder(struct intel_encoder *encoder)
9494{
9495 struct intel_connector *connector;
9496 struct drm_device *dev = encoder->base.dev;
9497
9498 /* We need to check both for a crtc link (meaning that the
9499 * encoder is active and trying to read from a pipe) and the
9500 * pipe itself being active. */
9501 bool has_active_crtc = encoder->base.crtc &&
9502 to_intel_crtc(encoder->base.crtc)->active;
9503
9504 if (encoder->connectors_active && !has_active_crtc) {
9505 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
9506 encoder->base.base.id,
9507 drm_get_encoder_name(&encoder->base));
9508
9509 /* Connector is active, but has no active pipe. This is
9510 * fallout from our resume register restoring. Disable
9511 * the encoder manually again. */
9512 if (encoder->base.crtc) {
9513 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
9514 encoder->base.base.id,
9515 drm_get_encoder_name(&encoder->base));
9516 encoder->disable(encoder);
9517 }
9518
9519 /* Inconsistent output/port/pipe state happens presumably due to
9520 * a bug in one of the get_hw_state functions. Or someplace else
9521 * in our code, like the register restore mess on resume. Clamp
9522 * things to off as a safer default. */
9523 list_for_each_entry(connector,
9524 &dev->mode_config.connector_list,
9525 base.head) {
9526 if (connector->encoder != encoder)
9527 continue;
9528
9529 intel_connector_break_all_links(connector);
9530 }
9531 }
9532 /* Enabled encoders without active connectors will be fixed in
9533 * the crtc fixup. */
9534}
9535
44cec740 9536void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 9537{
9538 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 9539 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f
KM		 9540
9541 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
9542 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 9543 i915_disable_vga(dev);
0fde901f
KM		 9544 }
9545}
9546
24929352
DV		 9547/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
9548 * and i915 state tracking structures. */
45e2b5f6
DV		 9549void intel_modeset_setup_hw_state(struct drm_device *dev,
9550 bool force_restore)
24929352
DV		 9551{
9552 struct drm_i915_private *dev_priv = dev->dev_private;
9553 enum pipe pipe;
b5644d05 9554 struct drm_plane *plane;
24929352
DV		 9555 struct intel_crtc *crtc;
9556 struct intel_encoder *encoder;
9557 struct intel_connector *connector;
9558
0e8ffe1b
DV		 9559 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9560 base.head) {
88adfff1 9561 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 9562
0e8ffe1b
DV		 9563 crtc->active = dev_priv->display.get_pipe_config(crtc,
9564 &crtc->config);
24929352
DV		 9565
9566 crtc->base.enabled = crtc->active;
9567
9568 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9569 crtc->base.base.id,
9570 crtc->active ? "enabled" : "disabled");
9571 }
9572
affa9354 9573 if (HAS_DDI(dev))
6441ab5f
PZ		 9574 intel_ddi_setup_hw_pll_state(dev);
9575
24929352
DV		 9576 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9577 base.head) {
9578 pipe = 0;
9579
9580 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 9581 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9582 encoder->base.crtc = &crtc->base;
9583 if (encoder->get_config)
9584 encoder->get_config(encoder, &crtc->config);
24929352
DV		 9585 } else {
9586 encoder->base.crtc = NULL;
9587 }
9588
9589 encoder->connectors_active = false;
9590 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9591 encoder->base.base.id,
9592 drm_get_encoder_name(&encoder->base),
9593 encoder->base.crtc ? "enabled" : "disabled",
9594 pipe);
9595 }
9596
9597 list_for_each_entry(connector, &dev->mode_config.connector_list,
9598 base.head) {
9599 if (connector->get_hw_state(connector)) {
9600 connector->base.dpms = DRM_MODE_DPMS_ON;
9601 connector->encoder->connectors_active = true;
9602 connector->base.encoder = &connector->encoder->base;
9603 } else {
9604 connector->base.dpms = DRM_MODE_DPMS_OFF;
9605 connector->base.encoder = NULL;
9606 }
9607 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9608 connector->base.base.id,
9609 drm_get_connector_name(&connector->base),
9610 connector->base.encoder ? "enabled" : "disabled");
9611 }
9612
9613 /* HW state is read out, now we need to sanitize this mess. */
9614 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9615 base.head) {
9616 intel_sanitize_encoder(encoder);
9617 }
9618
9619 for_each_pipe(pipe) {
9620 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9621 intel_sanitize_crtc(crtc);
c0b03411 9622 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 9623 }
9a935856 9624
45e2b5f6 9625 if (force_restore) {
f30da187
DV		 9626 /*
9627 * We need to use raw interfaces for restoring state to avoid
9628 * checking (bogus) intermediate states.
9629 */
45e2b5f6 9630 for_each_pipe(pipe) {
b5644d05
JB		 9631 struct drm_crtc *crtc =
9632 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 9633
9634 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
9635 crtc->fb);
45e2b5f6 9636 }
b5644d05
JB		 9637 list_for_each_entry(plane, &dev->mode_config.plane_list, head)
9638 intel_plane_restore(plane);
0fde901f
KM		 9639
9640 i915_redisable_vga(dev);
45e2b5f6
DV		 9641 } else {
9642 intel_modeset_update_staged_output_state(dev);
9643 }
8af6cf88
DV		 9644
9645 intel_modeset_check_state(dev);
2e938892
DV		 9646
9647 drm_mode_config_reset(dev);
2c7111db
CW		 9648}
9649
9650void intel_modeset_gem_init(struct drm_device *dev)
9651{
1833b134 9652 intel_modeset_init_hw(dev);
02e792fb
DV		 9653
9654 intel_setup_overlay(dev);
24929352 9655
45e2b5f6 9656 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9657}
9658
9659void intel_modeset_cleanup(struct drm_device *dev)
9660{
652c393a
JB		 9661 struct drm_i915_private *dev_priv = dev->dev_private;
9662 struct drm_crtc *crtc;
9663 struct intel_crtc *intel_crtc;
9664
fd0c0642
DV		 9665 /*
9666 * Interrupts and polling as the first thing to avoid creating havoc.
9667 * Too much stuff here (turning of rps, connectors, ...) would
9668 * experience fancy races otherwise.
9669 */
9670 drm_irq_uninstall(dev);
9671 cancel_work_sync(&dev_priv->hotplug_work);
9672 /*
9673 * Due to the hpd irq storm handling the hotplug work can re-arm the
9674 * poll handlers. Hence disable polling after hpd handling is shut down.
9675 */
f87ea761 9676 drm_kms_helper_poll_fini(dev);
fd0c0642 9677
652c393a
JB		 9678 mutex_lock(&dev->struct_mutex);
9679
723bfd70
JB		 9680 intel_unregister_dsm_handler();
9681
652c393a
JB		 9682 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9683 /* Skip inactive CRTCs */
9684 if (!crtc->fb)
9685 continue;
9686
9687 intel_crtc = to_intel_crtc(crtc);
3dec0095 9688 intel_increase_pllclock(crtc);
652c393a
JB		 9689 }
9690
973d04f9 9691 intel_disable_fbc(dev);
e70236a8 9692
8090c6b9 9693 intel_disable_gt_powersave(dev);
0cdab21f 9694
930ebb46
DV		 9695 ironlake_teardown_rc6(dev);
9696
69341a5e
KH		 9697 mutex_unlock(&dev->struct_mutex);
9698
1630fe75
CW		 9699 /* flush any delayed tasks or pending work */
9700 flush_scheduled_work();
9701
dc652f90
JN		 9702 /* destroy backlight, if any, before the connectors */
9703 intel_panel_destroy_backlight(dev);
9704
79e53945 9705 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9706
9707 intel_cleanup_overlay(dev);
79e53945
JB		 9708}
9709
f1c79df3
ZW		 9710/*
9711 * Return which encoder is currently attached for connector.
9712 */
df0e9248 9713struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9714{
df0e9248
CW		 9715 return &intel_attached_encoder(connector)->base;
9716}
f1c79df3 9717
df0e9248
CW		 9718void intel_connector_attach_encoder(struct intel_connector *connector,
9719 struct intel_encoder *encoder)
9720{
9721 connector->encoder = encoder;
9722 drm_mode_connector_attach_encoder(&connector->base,
9723 &encoder->base);
79e53945 9724}
28d52043
DA		 9725
9726/*
9727 * set vga decode state - true == enable VGA decode
9728 */
9729int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9730{
9731 struct drm_i915_private *dev_priv = dev->dev_private;
9732 u16 gmch_ctrl;
9733
9734 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9735 if (state)
9736 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9737 else
9738 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9739 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9740 return 0;
9741}
c4a1d9e4
CW		 9742
9743#ifdef CONFIG_DEBUG_FS
9744#include <linux/seq_file.h>
9745
9746struct intel_display_error_state {
ff57f1b0
PZ		 9747
9748 u32 power_well_driver;
9749
c4a1d9e4
CW		 9750 struct intel_cursor_error_state {
9751 u32 control;
9752 u32 position;
9753 u32 base;
9754 u32 size;
52331309 9755 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9756
9757 struct intel_pipe_error_state {
ff57f1b0 9758 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9759 u32 conf;
9760 u32 source;
9761
9762 u32 htotal;
9763 u32 hblank;
9764 u32 hsync;
9765 u32 vtotal;
9766 u32 vblank;
9767 u32 vsync;
52331309 9768 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9769
9770 struct intel_plane_error_state {
9771 u32 control;
9772 u32 stride;
9773 u32 size;
9774 u32 pos;
9775 u32 addr;
9776 u32 surface;
9777 u32 tile_offset;
52331309 9778 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9779};
9780
9781struct intel_display_error_state *
9782intel_display_capture_error_state(struct drm_device *dev)
9783{
0206e353 9784 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9785 struct intel_display_error_state *error;
702e7a56 9786 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9787 int i;
9788
9789 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9790 if (error == NULL)
9791 return NULL;
9792
ff57f1b0
PZ		 9793 if (HAS_POWER_WELL(dev))
9794 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
9795
52331309 9796 for_each_pipe(i) {
702e7a56 9797 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
ff57f1b0 9798 error->pipe[i].cpu_transcoder = cpu_transcoder;
702e7a56 9799
a18c4c3d
PZ		 9800 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
9801 error->cursor[i].control = I915_READ(CURCNTR(i));
9802 error->cursor[i].position = I915_READ(CURPOS(i));
9803 error->cursor[i].base = I915_READ(CURBASE(i));
9804 } else {
9805 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
9806 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
9807 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
9808 }
c4a1d9e4
CW		 9809
9810 error->plane[i].control = I915_READ(DSPCNTR(i));
9811 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 9812 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 9813 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 9814 error->plane[i].pos = I915_READ(DSPPOS(i));
9815 }
ca291363
PZ		 9816 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
9817 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 9818 if (INTEL_INFO(dev)->gen >= 4) {
9819 error->plane[i].surface = I915_READ(DSPSURF(i));
9820 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9821 }
9822
702e7a56 9823 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9824 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9825 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9826 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9827 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9828 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9829 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9830 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9831 }
9832
12d217c7
PZ		 9833 /* In the code above we read the registers without checking if the power
9834 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
9835 * prevent the next I915_WRITE from detecting it and printing an error
9836 * message. */
9837 if (HAS_POWER_WELL(dev))
9838 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
9839
c4a1d9e4
CW		 9840 return error;
9841}
9842
edc3d884
MK		 9843#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
9844
c4a1d9e4 9845void
edc3d884 9846intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 9847 struct drm_device *dev,
9848 struct intel_display_error_state *error)
9849{
9850 int i;
9851
edc3d884 9852 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 9853 if (HAS_POWER_WELL(dev))
edc3d884 9854 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 9855 error->power_well_driver);
52331309 9856 for_each_pipe(i) {
edc3d884
MK		 9857 err_printf(m, "Pipe [%d]:\n", i);
9858 err_printf(m, " CPU transcoder: %c\n",
ff57f1b0 9859 transcoder_name(error->pipe[i].cpu_transcoder));
edc3d884
MK		 9860 err_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9861 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
9862 err_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9863 err_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9864 err_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9865 err_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9866 err_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9867 err_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9868
9869 err_printf(m, "Plane [%d]:\n", i);
9870 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
9871 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 9872 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 9873 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
9874 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 9875 }
4b71a570 9876 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 9877 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 9878 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 9879 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
9880 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 9881 }
9882
edc3d884
MK		 9883 err_printf(m, "Cursor [%d]:\n", i);
9884 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9885 err_printf(m, " POS: %08x\n", error->cursor[i].position);
9886 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4
CW		 9887 }
9888}
9889#endif
Linux kernel - Deliverables
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