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drm/i915: adjust framebuffer base address on gen4+
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
d4906093
ML		 87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
79e53945 91
a4fc5ed6
KP		 92static bool
93intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
5eb08b69 96static bool
f2b115e6 97intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
a4fc5ed6 100
a0c4da24
JB		 101static bool
102intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103 int target, int refclk, intel_clock_t *match_clock,
104 intel_clock_t *best_clock);
105
021357ac
CW		 106static inline u32 /* units of 100MHz */
107intel_fdi_link_freq(struct drm_device *dev)
108{
8b99e68c
CW		 109 if (IS_GEN5(dev)) {
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
112 } else
113 return 27;
021357ac
CW		 114}
115
e4b36699 116static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 117 .dot = { .min = 25000, .max = 350000 },
118 .vco = { .min = 930000, .max = 1400000 },
119 .n = { .min = 3, .max = 16 },
120 .m = { .min = 96, .max = 140 },
121 .m1 = { .min = 18, .max = 26 },
122 .m2 = { .min = 6, .max = 16 },
123 .p = { .min = 4, .max = 128 },
124 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 125 .p2 = { .dot_limit = 165000,
126 .p2_slow = 4, .p2_fast = 2 },
d4906093 127 .find_pll = intel_find_best_PLL,
e4b36699
KP		 128};
129
130static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 131 .dot = { .min = 25000, .max = 350000 },
132 .vco = { .min = 930000, .max = 1400000 },
133 .n = { .min = 3, .max = 16 },
134 .m = { .min = 96, .max = 140 },
135 .m1 = { .min = 18, .max = 26 },
136 .m2 = { .min = 6, .max = 16 },
137 .p = { .min = 4, .max = 128 },
138 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 139 .p2 = { .dot_limit = 165000,
140 .p2_slow = 14, .p2_fast = 7 },
d4906093 141 .find_pll = intel_find_best_PLL,
e4b36699 142};
273e27ca 143
e4b36699 144static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 10, .max = 22 },
150 .m2 = { .min = 5, .max = 9 },
151 .p = { .min = 5, .max = 80 },
152 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 153 .p2 = { .dot_limit = 200000,
154 .p2_slow = 10, .p2_fast = 5 },
d4906093 155 .find_pll = intel_find_best_PLL,
e4b36699
KP		 156};
157
158static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 10, .max = 22 },
164 .m2 = { .min = 5, .max = 9 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
d4906093 169 .find_pll = intel_find_best_PLL,
e4b36699
KP		 170};
171
273e27ca 172
e4b36699 173static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 174 .dot = { .min = 25000, .max = 270000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 10, .max = 30 },
181 .p1 = { .min = 1, .max = 3},
182 .p2 = { .dot_limit = 270000,
183 .p2_slow = 10,
184 .p2_fast = 10
044c7c41 185 },
d4906093 186 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 187};
188
189static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 190 .dot = { .min = 22000, .max = 400000 },
191 .vco = { .min = 1750000, .max = 3500000},
192 .n = { .min = 1, .max = 4 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 16, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8},
198 .p2 = { .dot_limit = 165000,
199 .p2_slow = 10, .p2_fast = 5 },
d4906093 200 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 201};
202
203static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 204 .dot = { .min = 20000, .max = 115000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 28, .max = 112 },
211 .p1 = { .min = 2, .max = 8 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 14, .p2_fast = 14
044c7c41 214 },
d4906093 215 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 216};
217
218static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 219 .dot = { .min = 80000, .max = 224000 },
220 .vco = { .min = 1750000, .max = 3500000 },
221 .n = { .min = 1, .max = 3 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 14, .max = 42 },
226 .p1 = { .min = 2, .max = 6 },
227 .p2 = { .dot_limit = 0,
228 .p2_slow = 7, .p2_fast = 7
044c7c41 229 },
d4906093 230 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 231};
232
233static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 234 .dot = { .min = 161670, .max = 227000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 2 },
237 .m = { .min = 97, .max = 108 },
238 .m1 = { .min = 0x10, .max = 0x12 },
239 .m2 = { .min = 0x05, .max = 0x06 },
240 .p = { .min = 10, .max = 20 },
241 .p1 = { .min = 1, .max = 2},
242 .p2 = { .dot_limit = 0,
273e27ca 243 .p2_slow = 10, .p2_fast = 10 },
0206e353 244 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 245};
246
f2b115e6 247static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 248 .dot = { .min = 20000, .max = 400000},
249 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 250 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 251 .n = { .min = 3, .max = 6 },
252 .m = { .min = 2, .max = 256 },
273e27ca 253 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 254 .m1 = { .min = 0, .max = 0 },
255 .m2 = { .min = 0, .max = 254 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 258 .p2 = { .dot_limit = 200000,
259 .p2_slow = 10, .p2_fast = 5 },
6115707b 260 .find_pll = intel_find_best_PLL,
e4b36699
KP		 261};
262
f2b115e6 263static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1700000, .max = 3500000 },
266 .n = { .min = 3, .max = 6 },
267 .m = { .min = 2, .max = 256 },
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 7, .max = 112 },
271 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 272 .p2 = { .dot_limit = 112000,
273 .p2_slow = 14, .p2_fast = 14 },
6115707b 274 .find_pll = intel_find_best_PLL,
e4b36699
KP		 275};
276
273e27ca
EA		 277/* Ironlake / Sandybridge
278 *
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
281 */
b91ad0ec 282static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 5 },
286 .m = { .min = 79, .max = 127 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 10, .p2_fast = 5 },
4547668a 293 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 294};
295
b91ad0ec 296static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 297 .dot = { .min = 25000, .max = 350000 },
298 .vco = { .min = 1760000, .max = 3510000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 79, .max = 118 },
301 .m1 = { .min = 12, .max = 22 },
302 .m2 = { .min = 5, .max = 9 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 225000,
306 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 307 .find_pll = intel_g4x_find_best_PLL,
308};
309
310static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 14, .max = 56 },
318 .p1 = { .min = 2, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 321 .find_pll = intel_g4x_find_best_PLL,
322};
323
273e27ca 324/* LVDS 100mhz refclk limits. */
b91ad0ec 325static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 2 },
329 .m = { .min = 79, .max = 126 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
0206e353 333 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 336 .find_pll = intel_g4x_find_best_PLL,
337};
338
339static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 126 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 42 },
0206e353 347 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 350 .find_pll = intel_g4x_find_best_PLL,
351};
352
353static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000},
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 81, .max = 90 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 10, .max = 20 },
361 .p1 = { .min = 1, .max = 2},
362 .p2 = { .dot_limit = 0,
273e27ca 363 .p2_slow = 10, .p2_fast = 10 },
0206e353 364 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 365};
366
a0c4da24
JB		 367static const intel_limit_t intel_limits_vlv_dac = {
368 .dot = { .min = 25000, .max = 270000 },
369 .vco = { .min = 4000000, .max = 6000000 },
370 .n = { .min = 1, .max = 7 },
371 .m = { .min = 22, .max = 450 }, /* guess */
372 .m1 = { .min = 2, .max = 3 },
373 .m2 = { .min = 11, .max = 156 },
374 .p = { .min = 10, .max = 30 },
375 .p1 = { .min = 2, .max = 3 },
376 .p2 = { .dot_limit = 270000,
377 .p2_slow = 2, .p2_fast = 20 },
378 .find_pll = intel_vlv_find_best_pll,
379};
380
381static const intel_limit_t intel_limits_vlv_hdmi = {
382 .dot = { .min = 20000, .max = 165000 },
383 .vco = { .min = 5994000, .max = 4000000 },
384 .n = { .min = 1, .max = 7 },
385 .m = { .min = 60, .max = 300 }, /* guess */
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p = { .min = 10, .max = 30 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .dot_limit = 270000,
391 .p2_slow = 2, .p2_fast = 20 },
392 .find_pll = intel_vlv_find_best_pll,
393};
394
395static const intel_limit_t intel_limits_vlv_dp = {
396 .dot = { .min = 162000, .max = 270000 },
397 .vco = { .min = 5994000, .max = 4000000 },
398 .n = { .min = 1, .max = 7 },
399 .m = { .min = 60, .max = 300 }, /* guess */
400 .m1 = { .min = 2, .max = 3 },
401 .m2 = { .min = 11, .max = 156 },
402 .p = { .min = 10, .max = 30 },
403 .p1 = { .min = 2, .max = 3 },
404 .p2 = { .dot_limit = 270000,
405 .p2_slow = 2, .p2_fast = 20 },
406 .find_pll = intel_vlv_find_best_pll,
407};
408
57f350b6
JB		 409u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
410{
411 unsigned long flags;
412 u32 val = 0;
413
414 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
417 goto out_unlock;
418 }
419
420 I915_WRITE(DPIO_REG, reg);
421 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
422 DPIO_BYTE);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
425 goto out_unlock;
426 }
427 val = I915_READ(DPIO_DATA);
428
429out_unlock:
430 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
431 return val;
432}
433
a0c4da24
JB		 434static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
435 u32 val)
436{
437 unsigned long flags;
438
439 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
442 goto out_unlock;
443 }
444
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
448 DPIO_BYTE);
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
451
452out_unlock:
453 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
454}
455
57f350b6
JB		 456static void vlv_init_dpio(struct drm_device *dev)
457{
458 struct drm_i915_private *dev_priv = dev->dev_private;
459
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
465}
466
618563e3
DV		 467static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
468{
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
470 return 1;
471}
472
473static const struct dmi_system_id intel_dual_link_lvds[] = {
474 {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
477 .matches = {
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
480 },
481 },
482 { } /* terminating entry */
483};
484
b0354385
TI		 485static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
486 unsigned int reg)
487{
488 unsigned int val;
489
121d527a
TI		 490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
493
618563e3
DV		 494 if (dmi_check_system(intel_dual_link_lvds))
495 return true;
496
b0354385
TI		 497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
499 else {
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
504 */
505 val = I915_READ(reg);
14d94a3d 506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
509 }
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
511}
512
1b894b59
CW		 513static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
514 int refclk)
2c07245f 515{
b91ad0ec
ZW		 516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 518 const intel_limit_t *limit;
b91ad0ec
ZW		 519
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 522 /* LVDS dual channel */
1b894b59 523 if (refclk == 100000)
b91ad0ec
ZW		 524 limit = &intel_limits_ironlake_dual_lvds_100m;
525 else
526 limit = &intel_limits_ironlake_dual_lvds;
527 } else {
1b894b59 528 if (refclk == 100000)
b91ad0ec
ZW		 529 limit = &intel_limits_ironlake_single_lvds_100m;
530 else
531 limit = &intel_limits_ironlake_single_lvds;
532 }
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 534 HAS_eDP)
535 limit = &intel_limits_ironlake_display_port;
2c07245f 536 else
b91ad0ec 537 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 538
539 return limit;
540}
541
044c7c41
ML		 542static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
543{
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
547
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 549 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 550 /* LVDS with dual channel */
e4b36699 551 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 552 else
553 /* LVDS with dual channel */
e4b36699 554 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 557 limit = &intel_limits_g4x_hdmi;
044c7c41 558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 559 limit = &intel_limits_g4x_sdvo;
0206e353 560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 561 limit = &intel_limits_g4x_display_port;
044c7c41 562 } else /* The option is for other outputs */
e4b36699 563 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 564
565 return limit;
566}
567
1b894b59 568static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 569{
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
572
bad720ff 573 if (HAS_PCH_SPLIT(dev))
1b894b59 574 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 575 else if (IS_G4X(dev)) {
044c7c41 576 limit = intel_g4x_limit(crtc);
f2b115e6 577 } else if (IS_PINEVIEW(dev)) {
2177832f 578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 579 limit = &intel_limits_pineview_lvds;
2177832f 580 else
f2b115e6 581 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
587 else
588 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
592 else
593 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 594 } else {
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 596 limit = &intel_limits_i8xx_lvds;
79e53945 597 else
e4b36699 598 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 599 }
600 return limit;
601}
602
f2b115e6
AJ		 603/* m1 is reserved as 0 in Pineview, n is a ring counter */
604static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 605{
2177832f
SL		 606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
610}
611
612static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
613{
f2b115e6
AJ		 614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
2177832f
SL		 616 return;
617 }
79e53945
JB		 618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
622}
623
79e53945
JB		 624/**
625 * Returns whether any output on the specified pipe is of the specified type
626 */
4ef69c7a 627bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 628{
4ef69c7a
CW		 629 struct drm_device *dev = crtc->dev;
630 struct drm_mode_config *mode_config = &dev->mode_config;
631 struct intel_encoder *encoder;
632
633 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
634 if (encoder->base.crtc == crtc && encoder->type == type)
635 return true;
636
637 return false;
79e53945
JB		 638}
639
7c04d1d9 640#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 641/**
642 * Returns whether the given set of divisors are valid for a given refclk with
643 * the given connectors.
644 */
645
1b894b59
CW		 646static bool intel_PLL_is_valid(struct drm_device *dev,
647 const intel_limit_t *limit,
648 const intel_clock_t *clock)
79e53945 649{
79e53945 650 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 651 INTELPllInvalid("p1 out of range\n");
79e53945 652 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 653 INTELPllInvalid("p out of range\n");
79e53945 654 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 655 INTELPllInvalid("m2 out of range\n");
79e53945 656 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 657 INTELPllInvalid("m1 out of range\n");
f2b115e6 658 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 659 INTELPllInvalid("m1 <= m2\n");
79e53945 660 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 661 INTELPllInvalid("m out of range\n");
79e53945 662 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 663 INTELPllInvalid("n out of range\n");
79e53945 664 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 665 INTELPllInvalid("vco out of range\n");
79e53945
JB		 666 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
667 * connector, etc., rather than just a single range.
668 */
669 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 670 INTELPllInvalid("dot out of range\n");
79e53945
JB		 671
672 return true;
673}
674
d4906093
ML		 675static bool
676intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 677 int target, int refclk, intel_clock_t *match_clock,
678 intel_clock_t *best_clock)
d4906093 679
79e53945
JB		 680{
681 struct drm_device *dev = crtc->dev;
682 struct drm_i915_private *dev_priv = dev->dev_private;
683 intel_clock_t clock;
79e53945
JB		 684 int err = target;
685
bc5e5718 686 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 687 (I915_READ(LVDS)) != 0) {
79e53945
JB		 688 /*
689 * For LVDS, if the panel is on, just rely on its current
690 * settings for dual-channel. We haven't figured out how to
691 * reliably set up different single/dual channel state, if we
692 * even can.
693 */
b0354385 694 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 695 clock.p2 = limit->p2.p2_fast;
696 else
697 clock.p2 = limit->p2.p2_slow;
698 } else {
699 if (target < limit->p2.dot_limit)
700 clock.p2 = limit->p2.p2_slow;
701 else
702 clock.p2 = limit->p2.p2_fast;
703 }
704
0206e353 705 memset(best_clock, 0, sizeof(*best_clock));
79e53945 706
42158660
ZY		 707 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
708 clock.m1++) {
709 for (clock.m2 = limit->m2.min;
710 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 711 /* m1 is always 0 in Pineview */
712 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 713 break;
714 for (clock.n = limit->n.min;
715 clock.n <= limit->n.max; clock.n++) {
716 for (clock.p1 = limit->p1.min;
717 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 718 int this_err;
719
2177832f 720 intel_clock(dev, refclk, &clock);
1b894b59
CW		 721 if (!intel_PLL_is_valid(dev, limit,
722 &clock))
79e53945 723 continue;
cec2f356
SP		 724 if (match_clock &&
725 clock.p != match_clock->p)
726 continue;
79e53945
JB		 727
728 this_err = abs(clock.dot - target);
729 if (this_err < err) {
730 *best_clock = clock;
731 err = this_err;
732 }
733 }
734 }
735 }
736 }
737
738 return (err != target);
739}
740
d4906093
ML		 741static bool
742intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 743 int target, int refclk, intel_clock_t *match_clock,
744 intel_clock_t *best_clock)
d4906093
ML		 745{
746 struct drm_device *dev = crtc->dev;
747 struct drm_i915_private *dev_priv = dev->dev_private;
748 intel_clock_t clock;
749 int max_n;
750 bool found;
6ba770dc
AJ		 751 /* approximately equals target * 0.00585 */
752 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 753 found = false;
754
755 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 756 int lvds_reg;
757
c619eed4 758 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 759 lvds_reg = PCH_LVDS;
760 else
761 lvds_reg = LVDS;
762 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 763 LVDS_CLKB_POWER_UP)
764 clock.p2 = limit->p2.p2_fast;
765 else
766 clock.p2 = limit->p2.p2_slow;
767 } else {
768 if (target < limit->p2.dot_limit)
769 clock.p2 = limit->p2.p2_slow;
770 else
771 clock.p2 = limit->p2.p2_fast;
772 }
773
774 memset(best_clock, 0, sizeof(*best_clock));
775 max_n = limit->n.max;
f77f13e2 776 /* based on hardware requirement, prefer smaller n to precision */
d4906093 777 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 778 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 779 for (clock.m1 = limit->m1.max;
780 clock.m1 >= limit->m1.min; clock.m1--) {
781 for (clock.m2 = limit->m2.max;
782 clock.m2 >= limit->m2.min; clock.m2--) {
783 for (clock.p1 = limit->p1.max;
784 clock.p1 >= limit->p1.min; clock.p1--) {
785 int this_err;
786
2177832f 787 intel_clock(dev, refclk, &clock);
1b894b59
CW		 788 if (!intel_PLL_is_valid(dev, limit,
789 &clock))
d4906093 790 continue;
cec2f356
SP		 791 if (match_clock &&
792 clock.p != match_clock->p)
793 continue;
1b894b59
CW		 794
795 this_err = abs(clock.dot - target);
d4906093
ML		 796 if (this_err < err_most) {
797 *best_clock = clock;
798 err_most = this_err;
799 max_n = clock.n;
800 found = true;
801 }
802 }
803 }
804 }
805 }
2c07245f
ZW		 806 return found;
807}
808
5eb08b69 809static bool
f2b115e6 810intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 811 int target, int refclk, intel_clock_t *match_clock,
812 intel_clock_t *best_clock)
5eb08b69
ZW		 813{
814 struct drm_device *dev = crtc->dev;
815 intel_clock_t clock;
4547668a 816
5eb08b69
ZW		 817 if (target < 200000) {
818 clock.n = 1;
819 clock.p1 = 2;
820 clock.p2 = 10;
821 clock.m1 = 12;
822 clock.m2 = 9;
823 } else {
824 clock.n = 2;
825 clock.p1 = 1;
826 clock.p2 = 10;
827 clock.m1 = 14;
828 clock.m2 = 8;
829 }
830 intel_clock(dev, refclk, &clock);
831 memcpy(best_clock, &clock, sizeof(intel_clock_t));
832 return true;
833}
834
a4fc5ed6
KP		 835/* DisplayPort has only two frequencies, 162MHz and 270MHz */
836static bool
837intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 838 int target, int refclk, intel_clock_t *match_clock,
839 intel_clock_t *best_clock)
a4fc5ed6 840{
5eddb70b
CW		 841 intel_clock_t clock;
842 if (target < 200000) {
843 clock.p1 = 2;
844 clock.p2 = 10;
845 clock.n = 2;
846 clock.m1 = 23;
847 clock.m2 = 8;
848 } else {
849 clock.p1 = 1;
850 clock.p2 = 10;
851 clock.n = 1;
852 clock.m1 = 14;
853 clock.m2 = 2;
854 }
855 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
856 clock.p = (clock.p1 * clock.p2);
857 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
858 clock.vco = 0;
859 memcpy(best_clock, &clock, sizeof(intel_clock_t));
860 return true;
a4fc5ed6 861}
a0c4da24
JB		 862static bool
863intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
864 int target, int refclk, intel_clock_t *match_clock,
865 intel_clock_t *best_clock)
866{
867 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
868 u32 m, n, fastclk;
869 u32 updrate, minupdate, fracbits, p;
870 unsigned long bestppm, ppm, absppm;
871 int dotclk, flag;
872
873 dotclk = target * 1000;
874 bestppm = 1000000;
875 ppm = absppm = 0;
876 fastclk = dotclk / (2*100);
877 updrate = 0;
878 minupdate = 19200;
879 fracbits = 1;
880 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881 bestm1 = bestm2 = bestp1 = bestp2 = 0;
882
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885 updrate = refclk / n;
886 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
888 if (p2 > 10)
889 p2 = p2 - 1;
890 p = p1 * p2;
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893 m2 = (((2*(fastclk * p * n / m1 )) +
894 refclk) / (2*refclk));
895 m = m1 * m2;
896 vco = updrate * m;
897 if (vco >= limit->vco.min && vco < limit->vco.max) {
898 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899 absppm = (ppm > 0) ? ppm : (-ppm);
900 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
901 bestppm = 0;
902 flag = 1;
903 }
904 if (absppm < bestppm - 10) {
905 bestppm = absppm;
906 flag = 1;
907 }
908 if (flag) {
909 bestn = n;
910 bestm1 = m1;
911 bestm2 = m2;
912 bestp1 = p1;
913 bestp2 = p2;
914 flag = 0;
915 }
916 }
917 }
918 }
919 }
920 }
921 best_clock->n = bestn;
922 best_clock->m1 = bestm1;
923 best_clock->m2 = bestm2;
924 best_clock->p1 = bestp1;
925 best_clock->p2 = bestp2;
926
927 return true;
928}
a4fc5ed6 929
a928d536
PZ		 930static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
931{
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 u32 frame, frame_reg = PIPEFRAME(pipe);
934
935 frame = I915_READ(frame_reg);
936
937 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
939}
940
9d0498a2
JB		 941/**
942 * intel_wait_for_vblank - wait for vblank on a given pipe
943 * @dev: drm device
944 * @pipe: pipe to wait for
945 *
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
947 * mode setting code.
948 */
949void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 950{
9d0498a2 951 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 952 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 953
a928d536
PZ		 954 if (INTEL_INFO(dev)->gen >= 5) {
955 ironlake_wait_for_vblank(dev, pipe);
956 return;
957 }
958
300387c0
CW		 959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
961 *
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
968 * vblanks...
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
971 */
972 I915_WRITE(pipestat_reg,
973 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
974
9d0498a2 975 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 976 if (wait_for(I915_READ(pipestat_reg) &
977 PIPE_VBLANK_INTERRUPT_STATUS,
978 50))
9d0498a2
JB		 979 DRM_DEBUG_KMS("vblank wait timed out\n");
980}
981
ab7ad7f6
KP		 982/*
983 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 984 * @dev: drm device
985 * @pipe: pipe to wait for
986 *
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
990 *
ab7ad7f6
KP		 991 * On Gen4 and above:
992 * wait for the pipe register state bit to turn off
993 *
994 * Otherwise:
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
58e10eb9 997 *
9d0498a2 998 */
58e10eb9 999void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1000{
1001 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 1002
1003 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 1004 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 1005
1006 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1007 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008 100))
ab7ad7f6
KP		 1009 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1010 } else {
837ba00f 1011 u32 last_line, line_mask;
58e10eb9 1012 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1013 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
837ba00f
PZ		 1015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
ab7ad7f6
KP		 1020 /* Wait for the display line to settle */
1021 do {
837ba00f 1022 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1023 mdelay(5);
837ba00f 1024 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1025 time_after(timeout, jiffies));
1026 if (time_after(jiffies, timeout))
1027 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1028 }
79e53945
JB		 1029}
1030
b24e7179
JB		 1031static const char *state_string(bool enabled)
1032{
1033 return enabled ? "on" : "off";
1034}
1035
1036/* Only for pre-ILK configs */
1037static void assert_pll(struct drm_i915_private *dev_priv,
1038 enum pipe pipe, bool state)
1039{
1040 int reg;
1041 u32 val;
1042 bool cur_state;
1043
1044 reg = DPLL(pipe);
1045 val = I915_READ(reg);
1046 cur_state = !!(val & DPLL_VCO_ENABLE);
1047 WARN(cur_state != state,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
1050}
1051#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
040484af
JB		 1054/* For ILK+ */
1055static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1056 struct intel_pch_pll *pll,
1057 struct intel_crtc *crtc,
1058 bool state)
040484af 1059{
040484af
JB		 1060 u32 val;
1061 bool cur_state;
1062
9d82aa17
ED		 1063 if (HAS_PCH_LPT(dev_priv->dev)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065 return;
1066 }
1067
92b27b08
CW		 1068 if (WARN (!pll,
1069 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1070 return;
ee7b9f93 1071
92b27b08
CW		 1072 val = I915_READ(pll->pll_reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 WARN(cur_state != state,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1080 u32 pch_dpll;
1081
1082 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1083 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state, crtc->pipe, pch_dpll)) {
1087 cur_state = !!(val >> (4*crtc->pipe + 3));
1088 WARN(cur_state != state,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll->pll_reg == _PCH_DPLL_B,
1091 state_string(state),
1092 crtc->pipe,
1093 val);
1094 }
d3ccbe86 1095 }
040484af 1096}
92b27b08
CW		 1097#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1099
1100static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1102{
1103 int reg;
1104 u32 val;
1105 bool cur_state;
1106
bf507ef7
ED		 1107 if (IS_HASWELL(dev_priv->dev)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg = DDI_FUNC_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112 } else {
1113 reg = FDI_TX_CTL(pipe);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & FDI_TX_ENABLE);
1116 }
040484af
JB		 1117 WARN(cur_state != state,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120}
1121#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, bool state)
1126{
1127 int reg;
1128 u32 val;
1129 bool cur_state;
1130
59c859d6
ED		 1131 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133 return;
1134 } else {
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1138 }
040484af
JB		 1139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1142}
1143#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147 enum pipe pipe)
1148{
1149 int reg;
1150 u32 val;
1151
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1154 return;
1155
bf507ef7
ED		 1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv->dev))
1158 return;
1159
040484af
JB		 1160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163}
1164
1165static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166 enum pipe pipe)
1167{
1168 int reg;
1169 u32 val;
1170
59c859d6
ED		 1171 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173 return;
1174 }
040484af
JB		 1175 reg = FDI_RX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178}
1179
ea0760cf
JB		 1180static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181 enum pipe pipe)
1182{
1183 int pp_reg, lvds_reg;
1184 u32 val;
1185 enum pipe panel_pipe = PIPE_A;
0de3b485 1186 bool locked = true;
ea0760cf
JB		 1187
1188 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189 pp_reg = PCH_PP_CONTROL;
1190 lvds_reg = PCH_LVDS;
1191 } else {
1192 pp_reg = PP_CONTROL;
1193 lvds_reg = LVDS;
1194 }
1195
1196 val = I915_READ(pp_reg);
1197 if (!(val & PANEL_POWER_ON) ||
1198 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199 locked = false;
1200
1201 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202 panel_pipe = PIPE_B;
1203
1204 WARN(panel_pipe == pipe && locked,
1205 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1206 pipe_name(pipe));
ea0760cf
JB		 1207}
1208
b840d907
JB		 1209void assert_pipe(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, bool state)
b24e7179
JB		 1211{
1212 int reg;
1213 u32 val;
63d7bbe9 1214 bool cur_state;
b24e7179 1215
8e636784
DV		 1216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218 state = true;
1219
b24e7179
JB		 1220 reg = PIPECONF(pipe);
1221 val = I915_READ(reg);
63d7bbe9
JB		 1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 WARN(cur_state != state,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1225 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1226}
1227
931872fc
CW		 1228static void assert_plane(struct drm_i915_private *dev_priv,
1229 enum plane plane, bool state)
b24e7179
JB		 1230{
1231 int reg;
1232 u32 val;
931872fc 1233 bool cur_state;
b24e7179
JB		 1234
1235 reg = DSPCNTR(plane);
1236 val = I915_READ(reg);
931872fc
CW		 1237 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238 WARN(cur_state != state,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1241}
1242
931872fc
CW		 1243#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
b24e7179
JB		 1246static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
1248{
1249 int reg, i;
1250 u32 val;
1251 int cur_pipe;
1252
19ec1358 1253 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1254 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255 reg = DSPCNTR(pipe);
1256 val = I915_READ(reg);
1257 WARN((val & DISPLAY_PLANE_ENABLE),
1258 "plane %c assertion failure, should be disabled but not\n",
1259 plane_name(pipe));
19ec1358 1260 return;
28c05794 1261 }
19ec1358 1262
b24e7179
JB		 1263 /* Need to check both planes against the pipe */
1264 for (i = 0; i < 2; i++) {
1265 reg = DSPCNTR(i);
1266 val = I915_READ(reg);
1267 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268 DISPPLANE_SEL_PIPE_SHIFT;
1269 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1272 }
1273}
1274
92f2584a
JB		 1275static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276{
1277 u32 val;
1278 bool enabled;
1279
9d82aa17
ED		 1280 if (HAS_PCH_LPT(dev_priv->dev)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282 return;
1283 }
1284
92f2584a
JB		 1285 val = I915_READ(PCH_DREF_CONTROL);
1286 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287 DREF_SUPERSPREAD_SOURCE_MASK));
1288 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289}
1290
1291static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293{
1294 int reg;
1295 u32 val;
1296 bool enabled;
1297
1298 reg = TRANSCONF(pipe);
1299 val = I915_READ(reg);
1300 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1301 WARN(enabled,
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303 pipe_name(pipe));
92f2584a
JB		 1304}
1305
4e634389
KP		 1306static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1308{
1309 if ((val & DP_PORT_EN) == 0)
1310 return false;
1311
1312 if (HAS_PCH_CPT(dev_priv->dev)) {
1313 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else {
1318 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319 return false;
1320 }
1321 return true;
1322}
1323
1519b995
KP		 1324static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, u32 val)
1326{
1327 if ((val & PORT_ENABLE) == 0)
1328 return false;
1329
1330 if (HAS_PCH_CPT(dev_priv->dev)) {
1331 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332 return false;
1333 } else {
1334 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335 return false;
1336 }
1337 return true;
1338}
1339
1340static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342{
1343 if ((val & LVDS_PORT_EN) == 0)
1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348 return false;
1349 } else {
1350 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351 return false;
1352 }
1353 return true;
1354}
1355
1356static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358{
1359 if ((val & ADPA_DAC_ENABLE) == 0)
1360 return false;
1361 if (HAS_PCH_CPT(dev_priv->dev)) {
1362 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363 return false;
1364 } else {
1365 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366 return false;
1367 }
1368 return true;
1369}
1370
291906f1 1371static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1372 enum pipe pipe, int reg, u32 port_sel)
291906f1 1373{
47a05eca 1374 u32 val = I915_READ(reg);
4e634389 1375 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1377 reg, pipe_name(pipe));
de9a35ab
DV		 1378
1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1380 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1381}
1382
1383static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1384 enum pipe pipe, int reg)
1385{
47a05eca 1386 u32 val = I915_READ(reg);
1519b995 1387 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
23c99e77 1388 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1389 reg, pipe_name(pipe));
de9a35ab
DV		 1390
1391 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1392 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1393}
1394
1395static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe)
1397{
1398 int reg;
1399 u32 val;
291906f1 1400
f0575e92
KP		 1401 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1402 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1403 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1404
1405 reg = PCH_ADPA;
1406 val = I915_READ(reg);
1519b995 1407 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1408 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1409 pipe_name(pipe));
291906f1
JB		 1410
1411 reg = PCH_LVDS;
1412 val = I915_READ(reg);
1519b995 1413 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1414 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1415 pipe_name(pipe));
291906f1
JB		 1416
1417 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1418 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1419 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1420}
1421
63d7bbe9
JB		 1422/**
1423 * intel_enable_pll - enable a PLL
1424 * @dev_priv: i915 private structure
1425 * @pipe: pipe PLL to enable
1426 *
1427 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1428 * make sure the PLL reg is writable first though, since the panel write
1429 * protect mechanism may be enabled.
1430 *
1431 * Note! This is for pre-ILK only.
1432 */
1433static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1434{
1435 int reg;
1436 u32 val;
1437
1438 /* No really, not for ILK+ */
a0c4da24 1439 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1440
1441 /* PLL is protected by panel, make sure we can write it */
1442 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1443 assert_panel_unlocked(dev_priv, pipe);
1444
1445 reg = DPLL(pipe);
1446 val = I915_READ(reg);
1447 val |= DPLL_VCO_ENABLE;
1448
1449 /* We do this three times for luck */
1450 I915_WRITE(reg, val);
1451 POSTING_READ(reg);
1452 udelay(150); /* wait for warmup */
1453 I915_WRITE(reg, val);
1454 POSTING_READ(reg);
1455 udelay(150); /* wait for warmup */
1456 I915_WRITE(reg, val);
1457 POSTING_READ(reg);
1458 udelay(150); /* wait for warmup */
1459}
1460
1461/**
1462 * intel_disable_pll - disable a PLL
1463 * @dev_priv: i915 private structure
1464 * @pipe: pipe PLL to disable
1465 *
1466 * Disable the PLL for @pipe, making sure the pipe is off first.
1467 *
1468 * Note! This is for pre-ILK only.
1469 */
1470static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1471{
1472 int reg;
1473 u32 val;
1474
1475 /* Don't disable pipe A or pipe A PLLs if needed */
1476 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1477 return;
1478
1479 /* Make sure the pipe isn't still relying on us */
1480 assert_pipe_disabled(dev_priv, pipe);
1481
1482 reg = DPLL(pipe);
1483 val = I915_READ(reg);
1484 val &= ~DPLL_VCO_ENABLE;
1485 I915_WRITE(reg, val);
1486 POSTING_READ(reg);
1487}
1488
a416edef
ED		 1489/* SBI access */
1490static void
1491intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1492{
1493 unsigned long flags;
1494
1495 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1496 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1497 100)) {
1498 DRM_ERROR("timeout waiting for SBI to become ready\n");
1499 goto out_unlock;
1500 }
1501
1502 I915_WRITE(SBI_ADDR,
1503 (reg << 16));
1504 I915_WRITE(SBI_DATA,
1505 value);
1506 I915_WRITE(SBI_CTL_STAT,
1507 SBI_BUSY |
1508 SBI_CTL_OP_CRWR);
1509
39fb50f6 1510 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1511 100)) {
1512 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1513 goto out_unlock;
1514 }
1515
1516out_unlock:
1517 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1518}
1519
1520static u32
1521intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1522{
1523 unsigned long flags;
39fb50f6 1524 u32 value = 0;
a416edef
ED		 1525
1526 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1527 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1528 100)) {
1529 DRM_ERROR("timeout waiting for SBI to become ready\n");
1530 goto out_unlock;
1531 }
1532
1533 I915_WRITE(SBI_ADDR,
1534 (reg << 16));
1535 I915_WRITE(SBI_CTL_STAT,
1536 SBI_BUSY |
1537 SBI_CTL_OP_CRRD);
1538
39fb50f6 1539 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1540 100)) {
1541 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1542 goto out_unlock;
1543 }
1544
1545 value = I915_READ(SBI_DATA);
1546
1547out_unlock:
1548 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1549 return value;
1550}
1551
92f2584a
JB		 1552/**
1553 * intel_enable_pch_pll - enable PCH PLL
1554 * @dev_priv: i915 private structure
1555 * @pipe: pipe PLL to enable
1556 *
1557 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1558 * drives the transcoder clock.
1559 */
ee7b9f93 1560static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1561{
ee7b9f93 1562 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1563 struct intel_pch_pll *pll;
92f2584a
JB		 1564 int reg;
1565 u32 val;
1566
48da64a8 1567 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1568 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1569 pll = intel_crtc->pch_pll;
1570 if (pll == NULL)
1571 return;
1572
1573 if (WARN_ON(pll->refcount == 0))
1574 return;
ee7b9f93
JB		 1575
1576 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1577 pll->pll_reg, pll->active, pll->on,
1578 intel_crtc->base.base.id);
92f2584a
JB		 1579
1580 /* PCH refclock must be enabled first */
1581 assert_pch_refclk_enabled(dev_priv);
1582
ee7b9f93 1583 if (pll->active++ && pll->on) {
92b27b08 1584 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1585 return;
1586 }
1587
1588 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1589
1590 reg = pll->pll_reg;
92f2584a
JB		 1591 val = I915_READ(reg);
1592 val |= DPLL_VCO_ENABLE;
1593 I915_WRITE(reg, val);
1594 POSTING_READ(reg);
1595 udelay(200);
ee7b9f93
JB		 1596
1597 pll->on = true;
92f2584a
JB		 1598}
1599
ee7b9f93 1600static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1601{
ee7b9f93
JB		 1602 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1603 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1604 int reg;
ee7b9f93 1605 u32 val;
4c609cb8 1606
92f2584a
JB		 1607 /* PCH only available on ILK+ */
1608 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1609 if (pll == NULL)
1610 return;
92f2584a 1611
48da64a8
CW		 1612 if (WARN_ON(pll->refcount == 0))
1613 return;
7a419866 1614
ee7b9f93
JB		 1615 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1616 pll->pll_reg, pll->active, pll->on,
1617 intel_crtc->base.base.id);
7a419866 1618
48da64a8 1619 if (WARN_ON(pll->active == 0)) {
92b27b08 1620 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1621 return;
1622 }
1623
ee7b9f93 1624 if (--pll->active) {
92b27b08 1625 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1626 return;
ee7b9f93
JB		 1627 }
1628
1629 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1630
1631 /* Make sure transcoder isn't still depending on us */
1632 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1633
ee7b9f93 1634 reg = pll->pll_reg;
92f2584a
JB		 1635 val = I915_READ(reg);
1636 val &= ~DPLL_VCO_ENABLE;
1637 I915_WRITE(reg, val);
1638 POSTING_READ(reg);
1639 udelay(200);
ee7b9f93
JB		 1640
1641 pll->on = false;
92f2584a
JB		 1642}
1643
040484af
JB		 1644static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1645 enum pipe pipe)
1646{
1647 int reg;
5f7f726d 1648 u32 val, pipeconf_val;
7c26e5c6 1649 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1650
1651 /* PCH only available on ILK+ */
1652 BUG_ON(dev_priv->info->gen < 5);
1653
1654 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1655 assert_pch_pll_enabled(dev_priv,
1656 to_intel_crtc(crtc)->pch_pll,
1657 to_intel_crtc(crtc));
040484af
JB		 1658
1659 /* FDI must be feeding us bits for PCH ports */
1660 assert_fdi_tx_enabled(dev_priv, pipe);
1661 assert_fdi_rx_enabled(dev_priv, pipe);
1662
59c859d6
ED		 1663 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1664 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1665 return;
1666 }
040484af
JB		 1667 reg = TRANSCONF(pipe);
1668 val = I915_READ(reg);
5f7f726d 1669 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1670
1671 if (HAS_PCH_IBX(dev_priv->dev)) {
1672 /*
1673 * make the BPC in transcoder be consistent with
1674 * that in pipeconf reg.
1675 */
1676 val &= ~PIPE_BPC_MASK;
5f7f726d 1677 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1678 }
5f7f726d
PZ		 1679
1680 val &= ~TRANS_INTERLACE_MASK;
1681 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1682 if (HAS_PCH_IBX(dev_priv->dev) &&
1683 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1684 val |= TRANS_LEGACY_INTERLACED_ILK;
1685 else
1686 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1687 else
1688 val |= TRANS_PROGRESSIVE;
1689
040484af
JB		 1690 I915_WRITE(reg, val | TRANS_ENABLE);
1691 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1692 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1693}
1694
1695static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1696 enum pipe pipe)
1697{
1698 int reg;
1699 u32 val;
1700
1701 /* FDI relies on the transcoder */
1702 assert_fdi_tx_disabled(dev_priv, pipe);
1703 assert_fdi_rx_disabled(dev_priv, pipe);
1704
291906f1
JB		 1705 /* Ports must be off as well */
1706 assert_pch_ports_disabled(dev_priv, pipe);
1707
040484af
JB		 1708 reg = TRANSCONF(pipe);
1709 val = I915_READ(reg);
1710 val &= ~TRANS_ENABLE;
1711 I915_WRITE(reg, val);
1712 /* wait for PCH transcoder off, transcoder state */
1713 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1714 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1715}
1716
b24e7179 1717/**
309cfea8 1718 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1719 * @dev_priv: i915 private structure
1720 * @pipe: pipe to enable
040484af 1721 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1722 *
1723 * Enable @pipe, making sure that various hardware specific requirements
1724 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1725 *
1726 * @pipe should be %PIPE_A or %PIPE_B.
1727 *
1728 * Will wait until the pipe is actually running (i.e. first vblank) before
1729 * returning.
1730 */
040484af
JB		 1731static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1732 bool pch_port)
b24e7179
JB		 1733{
1734 int reg;
1735 u32 val;
1736
1737 /*
1738 * A pipe without a PLL won't actually be able to drive bits from
1739 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1740 * need the check.
1741 */
1742 if (!HAS_PCH_SPLIT(dev_priv->dev))
1743 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1744 else {
1745 if (pch_port) {
1746 /* if driving the PCH, we need FDI enabled */
1747 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1748 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1749 }
1750 /* FIXME: assert CPU port conditions for SNB+ */
1751 }
b24e7179
JB		 1752
1753 reg = PIPECONF(pipe);
1754 val = I915_READ(reg);
00d70b15
CW		 1755 if (val & PIPECONF_ENABLE)
1756 return;
1757
1758 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1759 intel_wait_for_vblank(dev_priv->dev, pipe);
1760}
1761
1762/**
309cfea8 1763 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1764 * @dev_priv: i915 private structure
1765 * @pipe: pipe to disable
1766 *
1767 * Disable @pipe, making sure that various hardware specific requirements
1768 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1769 *
1770 * @pipe should be %PIPE_A or %PIPE_B.
1771 *
1772 * Will wait until the pipe has shut down before returning.
1773 */
1774static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1775 enum pipe pipe)
1776{
1777 int reg;
1778 u32 val;
1779
1780 /*
1781 * Make sure planes won't keep trying to pump pixels to us,
1782 * or we might hang the display.
1783 */
1784 assert_planes_disabled(dev_priv, pipe);
1785
1786 /* Don't disable pipe A or pipe A PLLs if needed */
1787 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1788 return;
1789
1790 reg = PIPECONF(pipe);
1791 val = I915_READ(reg);
00d70b15
CW		 1792 if ((val & PIPECONF_ENABLE) == 0)
1793 return;
1794
1795 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1796 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1797}
1798
d74362c9
KP		 1799/*
1800 * Plane regs are double buffered, going from enabled->disabled needs a
1801 * trigger in order to latch. The display address reg provides this.
1802 */
6f1d69b0 1803void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1804 enum plane plane)
1805{
1806 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1807 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1808}
1809
b24e7179
JB		 1810/**
1811 * intel_enable_plane - enable a display plane on a given pipe
1812 * @dev_priv: i915 private structure
1813 * @plane: plane to enable
1814 * @pipe: pipe being fed
1815 *
1816 * Enable @plane on @pipe, making sure that @pipe is running first.
1817 */
1818static void intel_enable_plane(struct drm_i915_private *dev_priv,
1819 enum plane plane, enum pipe pipe)
1820{
1821 int reg;
1822 u32 val;
1823
1824 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1825 assert_pipe_enabled(dev_priv, pipe);
1826
1827 reg = DSPCNTR(plane);
1828 val = I915_READ(reg);
00d70b15
CW		 1829 if (val & DISPLAY_PLANE_ENABLE)
1830 return;
1831
1832 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1833 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1834 intel_wait_for_vblank(dev_priv->dev, pipe);
1835}
1836
b24e7179
JB		 1837/**
1838 * intel_disable_plane - disable a display plane
1839 * @dev_priv: i915 private structure
1840 * @plane: plane to disable
1841 * @pipe: pipe consuming the data
1842 *
1843 * Disable @plane; should be an independent operation.
1844 */
1845static void intel_disable_plane(struct drm_i915_private *dev_priv,
1846 enum plane plane, enum pipe pipe)
1847{
1848 int reg;
1849 u32 val;
1850
1851 reg = DSPCNTR(plane);
1852 val = I915_READ(reg);
00d70b15
CW		 1853 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1854 return;
1855
1856 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1857 intel_flush_display_plane(dev_priv, plane);
1858 intel_wait_for_vblank(dev_priv->dev, pipe);
1859}
1860
47a05eca 1861static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1862 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1863{
1864 u32 val = I915_READ(reg);
4e634389 1865 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1866 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1867 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1868 }
47a05eca
JB		 1869}
1870
1871static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1872 enum pipe pipe, int reg)
1873{
1874 u32 val = I915_READ(reg);
1519b995 1875 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1876 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1877 reg, pipe);
47a05eca 1878 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1879 }
47a05eca
JB		 1880}
1881
1882/* Disable any ports connected to this transcoder */
1883static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1884 enum pipe pipe)
1885{
1886 u32 reg, val;
1887
1888 val = I915_READ(PCH_PP_CONTROL);
1889 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1890
f0575e92
KP		 1891 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1892 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1893 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1894
1895 reg = PCH_ADPA;
1896 val = I915_READ(reg);
1519b995 1897 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1898 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1899
1900 reg = PCH_LVDS;
1901 val = I915_READ(reg);
1519b995
KP		 1902 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1903 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1904 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1905 POSTING_READ(reg);
1906 udelay(100);
1907 }
1908
1909 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1910 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1911 disable_pch_hdmi(dev_priv, pipe, HDMID);
1912}
1913
127bd2ac 1914int
48b956c5 1915intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1916 struct drm_i915_gem_object *obj,
919926ae 1917 struct intel_ring_buffer *pipelined)
6b95a207 1918{
ce453d81 1919 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1920 u32 alignment;
1921 int ret;
1922
05394f39 1923 switch (obj->tiling_mode) {
6b95a207 1924 case I915_TILING_NONE:
534843da
CW		 1925 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1926 alignment = 128 * 1024;
a6c45cf0 1927 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1928 alignment = 4 * 1024;
1929 else
1930 alignment = 64 * 1024;
6b95a207
KH		 1931 break;
1932 case I915_TILING_X:
1933 /* pin() will align the object as required by fence */
1934 alignment = 0;
1935 break;
1936 case I915_TILING_Y:
1937 /* FIXME: Is this true? */
1938 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1939 return -EINVAL;
1940 default:
1941 BUG();
1942 }
1943
ce453d81 1944 dev_priv->mm.interruptible = false;
2da3b9b9 1945 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1946 if (ret)
ce453d81 1947 goto err_interruptible;
6b95a207
KH		 1948
1949 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1950 * fence, whereas 965+ only requires a fence if using
1951 * framebuffer compression. For simplicity, we always install
1952 * a fence as the cost is not that onerous.
1953 */
06d98131 1954 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1955 if (ret)
1956 goto err_unpin;
1690e1eb 1957
9a5a53b3 1958 i915_gem_object_pin_fence(obj);
6b95a207 1959
ce453d81 1960 dev_priv->mm.interruptible = true;
6b95a207 1961 return 0;
48b956c5
CW		 1962
1963err_unpin:
1964 i915_gem_object_unpin(obj);
ce453d81
CW		 1965err_interruptible:
1966 dev_priv->mm.interruptible = true;
48b956c5 1967 return ret;
6b95a207
KH		 1968}
1969
1690e1eb
CW		 1970void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1971{
1972 i915_gem_object_unpin_fence(obj);
1973 i915_gem_object_unpin(obj);
1974}
1975
c2c75131
DV		 1976/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1977 * is assumed to be a power-of-two. */
1978static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1979 unsigned int bpp,
1980 unsigned int pitch)
1981{
1982 int tile_rows, tiles;
1983
1984 tile_rows = *y / 8;
1985 *y %= 8;
1986 tiles = *x / (512/bpp);
1987 *x %= 512/bpp;
1988
1989 return tile_rows * pitch * 8 + tiles * 4096;
1990}
1991
17638cd6
JB		 1992static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1993 int x, int y)
81255565
JB		 1994{
1995 struct drm_device *dev = crtc->dev;
1996 struct drm_i915_private *dev_priv = dev->dev_private;
1997 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1998 struct intel_framebuffer *intel_fb;
05394f39 1999 struct drm_i915_gem_object *obj;
81255565 2000 int plane = intel_crtc->plane;
e506a0c6 2001 unsigned long linear_offset;
81255565 2002 u32 dspcntr;
5eddb70b 2003 u32 reg;
81255565
JB		 2004
2005 switch (plane) {
2006 case 0:
2007 case 1:
2008 break;
2009 default:
2010 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2011 return -EINVAL;
2012 }
2013
2014 intel_fb = to_intel_framebuffer(fb);
2015 obj = intel_fb->obj;
81255565 2016
5eddb70b
CW		 2017 reg = DSPCNTR(plane);
2018 dspcntr = I915_READ(reg);
81255565
JB		 2019 /* Mask out pixel format bits in case we change it */
2020 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2021 switch (fb->bits_per_pixel) {
2022 case 8:
2023 dspcntr |= DISPPLANE_8BPP;
2024 break;
2025 case 16:
2026 if (fb->depth == 15)
2027 dspcntr |= DISPPLANE_15_16BPP;
2028 else
2029 dspcntr |= DISPPLANE_16BPP;
2030 break;
2031 case 24:
2032 case 32:
2033 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2034 break;
2035 default:
17638cd6 2036 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2037 return -EINVAL;
2038 }
a6c45cf0 2039 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2040 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2041 dspcntr |= DISPPLANE_TILED;
2042 else
2043 dspcntr &= ~DISPPLANE_TILED;
2044 }
2045
5eddb70b 2046 I915_WRITE(reg, dspcntr);
81255565 2047
e506a0c6 2048 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2049
c2c75131
DV		 2050 if (INTEL_INFO(dev)->gen >= 4) {
2051 intel_crtc->dspaddr_offset =
2052 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2053 fb->bits_per_pixel / 8,
2054 fb->pitches[0]);
2055 linear_offset -= intel_crtc->dspaddr_offset;
2056 } else {
e506a0c6 2057 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2058 }
e506a0c6
DV		 2059
2060 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2061 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2062 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2063 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2064 I915_MODIFY_DISPBASE(DSPSURF(plane),
2065 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2066 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2067 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2068 } else
e506a0c6 2069 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2070 POSTING_READ(reg);
81255565 2071
17638cd6
JB		 2072 return 0;
2073}
2074
2075static int ironlake_update_plane(struct drm_crtc *crtc,
2076 struct drm_framebuffer *fb, int x, int y)
2077{
2078 struct drm_device *dev = crtc->dev;
2079 struct drm_i915_private *dev_priv = dev->dev_private;
2080 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2081 struct intel_framebuffer *intel_fb;
2082 struct drm_i915_gem_object *obj;
2083 int plane = intel_crtc->plane;
e506a0c6 2084 unsigned long linear_offset;
17638cd6
JB		 2085 u32 dspcntr;
2086 u32 reg;
2087
2088 switch (plane) {
2089 case 0:
2090 case 1:
27f8227b 2091 case 2:
17638cd6
JB		 2092 break;
2093 default:
2094 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2095 return -EINVAL;
2096 }
2097
2098 intel_fb = to_intel_framebuffer(fb);
2099 obj = intel_fb->obj;
2100
2101 reg = DSPCNTR(plane);
2102 dspcntr = I915_READ(reg);
2103 /* Mask out pixel format bits in case we change it */
2104 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2105 switch (fb->bits_per_pixel) {
2106 case 8:
2107 dspcntr |= DISPPLANE_8BPP;
2108 break;
2109 case 16:
2110 if (fb->depth != 16)
2111 return -EINVAL;
2112
2113 dspcntr |= DISPPLANE_16BPP;
2114 break;
2115 case 24:
2116 case 32:
2117 if (fb->depth == 24)
2118 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2119 else if (fb->depth == 30)
2120 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2121 else
2122 return -EINVAL;
2123 break;
2124 default:
2125 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2126 return -EINVAL;
2127 }
2128
2129 if (obj->tiling_mode != I915_TILING_NONE)
2130 dspcntr |= DISPPLANE_TILED;
2131 else
2132 dspcntr &= ~DISPPLANE_TILED;
2133
2134 /* must disable */
2135 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2136
2137 I915_WRITE(reg, dspcntr);
2138
e506a0c6 2139 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131
DV		 2140 intel_crtc->dspaddr_offset =
2141 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2142 fb->bits_per_pixel / 8,
2143 fb->pitches[0]);
2144 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2145
e506a0c6
DV		 2146 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2147 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2148 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2149 I915_MODIFY_DISPBASE(DSPSURF(plane),
2150 obj->gtt_offset + intel_crtc->dspaddr_offset);
17638cd6 2151 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2152 I915_WRITE(DSPLINOFF(plane), linear_offset);
17638cd6
JB		 2153 POSTING_READ(reg);
2154
2155 return 0;
2156}
2157
2158/* Assume fb object is pinned & idle & fenced and just update base pointers */
2159static int
2160intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2161 int x, int y, enum mode_set_atomic state)
2162{
2163 struct drm_device *dev = crtc->dev;
2164 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2165
6b8e6ed0
CW		 2166 if (dev_priv->display.disable_fbc)
2167 dev_priv->display.disable_fbc(dev);
3dec0095 2168 intel_increase_pllclock(crtc);
81255565 2169
6b8e6ed0 2170 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2171}
2172
14667a4b
CW		 2173static int
2174intel_finish_fb(struct drm_framebuffer *old_fb)
2175{
2176 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2177 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2178 bool was_interruptible = dev_priv->mm.interruptible;
2179 int ret;
2180
2181 wait_event(dev_priv->pending_flip_queue,
2182 atomic_read(&dev_priv->mm.wedged) ||
2183 atomic_read(&obj->pending_flip) == 0);
2184
2185 /* Big Hammer, we also need to ensure that any pending
2186 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2187 * current scanout is retired before unpinning the old
2188 * framebuffer.
2189 *
2190 * This should only fail upon a hung GPU, in which case we
2191 * can safely continue.
2192 */
2193 dev_priv->mm.interruptible = false;
2194 ret = i915_gem_object_finish_gpu(obj);
2195 dev_priv->mm.interruptible = was_interruptible;
2196
2197 return ret;
2198}
2199
5c3b82e2 2200static int
3c4fdcfb
KH		 2201intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2202 struct drm_framebuffer *old_fb)
79e53945
JB		 2203{
2204 struct drm_device *dev = crtc->dev;
6b8e6ed0 2205 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 2206 struct drm_i915_master_private *master_priv;
2207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2208 int ret;
79e53945
JB		 2209
2210 /* no fb bound */
2211 if (!crtc->fb) {
a5071c2f 2212 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2213 return 0;
2214 }
2215
5826eca5
ED		 2216 if(intel_crtc->plane > dev_priv->num_pipe) {
2217 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2218 intel_crtc->plane,
2219 dev_priv->num_pipe);
5c3b82e2 2220 return -EINVAL;
79e53945
JB		 2221 }
2222
5c3b82e2 2223 mutex_lock(&dev->struct_mutex);
265db958
CW		 2224 ret = intel_pin_and_fence_fb_obj(dev,
2225 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2226 NULL);
5c3b82e2
CW		 2227 if (ret != 0) {
2228 mutex_unlock(&dev->struct_mutex);
a5071c2f 2229 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2230 return ret;
2231 }
79e53945 2232
14667a4b
CW		 2233 if (old_fb)
2234 intel_finish_fb(old_fb);
265db958 2235
6b8e6ed0 2236 ret = dev_priv->display.update_plane(crtc, crtc->fb, x, y);
4e6cfefc 2237 if (ret) {
1690e1eb 2238 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2239 mutex_unlock(&dev->struct_mutex);
a5071c2f 2240 DRM_ERROR("failed to update base address\n");
4e6cfefc 2241 return ret;
79e53945 2242 }
3c4fdcfb 2243
b7f1de28
CW		 2244 if (old_fb) {
2245 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2246 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2247 }
652c393a 2248
6b8e6ed0 2249 intel_update_fbc(dev);
5c3b82e2 2250 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2251
2252 if (!dev->primary->master)
5c3b82e2 2253 return 0;
79e53945
JB		 2254
2255 master_priv = dev->primary->master->driver_priv;
2256 if (!master_priv->sarea_priv)
5c3b82e2 2257 return 0;
79e53945 2258
265db958 2259 if (intel_crtc->pipe) {
79e53945
JB		 2260 master_priv->sarea_priv->pipeB_x = x;
2261 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2262 } else {
2263 master_priv->sarea_priv->pipeA_x = x;
2264 master_priv->sarea_priv->pipeA_y = y;
79e53945 2265 }
5c3b82e2
CW		 2266
2267 return 0;
79e53945
JB		 2268}
2269
5eddb70b 2270static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2271{
2272 struct drm_device *dev = crtc->dev;
2273 struct drm_i915_private *dev_priv = dev->dev_private;
2274 u32 dpa_ctl;
2275
28c97730 2276 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2277 dpa_ctl = I915_READ(DP_A);
2278 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2279
2280 if (clock < 200000) {
2281 u32 temp;
2282 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2283 /* workaround for 160Mhz:
2284 1) program 0x4600c bits 15:0 = 0x8124
2285 2) program 0x46010 bit 0 = 1
2286 3) program 0x46034 bit 24 = 1
2287 4) program 0x64000 bit 14 = 1
2288 */
2289 temp = I915_READ(0x4600c);
2290 temp &= 0xffff0000;
2291 I915_WRITE(0x4600c, temp | 0x8124);
2292
2293 temp = I915_READ(0x46010);
2294 I915_WRITE(0x46010, temp | 1);
2295
2296 temp = I915_READ(0x46034);
2297 I915_WRITE(0x46034, temp | (1 << 24));
2298 } else {
2299 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2300 }
2301 I915_WRITE(DP_A, dpa_ctl);
2302
5eddb70b 2303 POSTING_READ(DP_A);
32f9d658
ZW		 2304 udelay(500);
2305}
2306
5e84e1a4
ZW		 2307static void intel_fdi_normal_train(struct drm_crtc *crtc)
2308{
2309 struct drm_device *dev = crtc->dev;
2310 struct drm_i915_private *dev_priv = dev->dev_private;
2311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2312 int pipe = intel_crtc->pipe;
2313 u32 reg, temp;
2314
2315 /* enable normal train */
2316 reg = FDI_TX_CTL(pipe);
2317 temp = I915_READ(reg);
61e499bf 2318 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2319 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2320 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2321 } else {
2322 temp &= ~FDI_LINK_TRAIN_NONE;
2323 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2324 }
5e84e1a4
ZW		 2325 I915_WRITE(reg, temp);
2326
2327 reg = FDI_RX_CTL(pipe);
2328 temp = I915_READ(reg);
2329 if (HAS_PCH_CPT(dev)) {
2330 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2331 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2332 } else {
2333 temp &= ~FDI_LINK_TRAIN_NONE;
2334 temp |= FDI_LINK_TRAIN_NONE;
2335 }
2336 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2337
2338 /* wait one idle pattern time */
2339 POSTING_READ(reg);
2340 udelay(1000);
357555c0
JB		 2341
2342 /* IVB wants error correction enabled */
2343 if (IS_IVYBRIDGE(dev))
2344 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2345 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2346}
2347
291427f5
JB		 2348static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2349{
2350 struct drm_i915_private *dev_priv = dev->dev_private;
2351 u32 flags = I915_READ(SOUTH_CHICKEN1);
2352
2353 flags |= FDI_PHASE_SYNC_OVR(pipe);
2354 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2355 flags |= FDI_PHASE_SYNC_EN(pipe);
2356 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2357 POSTING_READ(SOUTH_CHICKEN1);
2358}
2359
8db9d77b
ZW		 2360/* The FDI link training functions for ILK/Ibexpeak. */
2361static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2362{
2363 struct drm_device *dev = crtc->dev;
2364 struct drm_i915_private *dev_priv = dev->dev_private;
2365 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2366 int pipe = intel_crtc->pipe;
0fc932b8 2367 int plane = intel_crtc->plane;
5eddb70b 2368 u32 reg, temp, tries;
8db9d77b 2369
0fc932b8
JB		 2370 /* FDI needs bits from pipe & plane first */
2371 assert_pipe_enabled(dev_priv, pipe);
2372 assert_plane_enabled(dev_priv, plane);
2373
e1a44743
AJ		 2374 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2375 for train result */
5eddb70b
CW		 2376 reg = FDI_RX_IMR(pipe);
2377 temp = I915_READ(reg);
e1a44743
AJ		 2378 temp &= ~FDI_RX_SYMBOL_LOCK;
2379 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2380 I915_WRITE(reg, temp);
2381 I915_READ(reg);
e1a44743
AJ		 2382 udelay(150);
2383
8db9d77b 2384 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2385 reg = FDI_TX_CTL(pipe);
2386 temp = I915_READ(reg);
77ffb597
AJ		 2387 temp &= ~(7 << 19);
2388 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2389 temp &= ~FDI_LINK_TRAIN_NONE;
2390 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2391 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2392
5eddb70b
CW		 2393 reg = FDI_RX_CTL(pipe);
2394 temp = I915_READ(reg);
8db9d77b
ZW		 2395 temp &= ~FDI_LINK_TRAIN_NONE;
2396 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2397 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2398
2399 POSTING_READ(reg);
8db9d77b
ZW		 2400 udelay(150);
2401
5b2adf89 2402 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2403 if (HAS_PCH_IBX(dev)) {
2404 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2405 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2406 FDI_RX_PHASE_SYNC_POINTER_EN);
2407 }
5b2adf89 2408
5eddb70b 2409 reg = FDI_RX_IIR(pipe);
e1a44743 2410 for (tries = 0; tries < 5; tries++) {
5eddb70b 2411 temp = I915_READ(reg);
8db9d77b
ZW		 2412 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2413
2414 if ((temp & FDI_RX_BIT_LOCK)) {
2415 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2416 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2417 break;
2418 }
8db9d77b 2419 }
e1a44743 2420 if (tries == 5)
5eddb70b 2421 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2422
2423 /* Train 2 */
5eddb70b
CW		 2424 reg = FDI_TX_CTL(pipe);
2425 temp = I915_READ(reg);
8db9d77b
ZW		 2426 temp &= ~FDI_LINK_TRAIN_NONE;
2427 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2428 I915_WRITE(reg, temp);
8db9d77b 2429
5eddb70b
CW		 2430 reg = FDI_RX_CTL(pipe);
2431 temp = I915_READ(reg);
8db9d77b
ZW		 2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2434 I915_WRITE(reg, temp);
8db9d77b 2435
5eddb70b
CW		 2436 POSTING_READ(reg);
2437 udelay(150);
8db9d77b 2438
5eddb70b 2439 reg = FDI_RX_IIR(pipe);
e1a44743 2440 for (tries = 0; tries < 5; tries++) {
5eddb70b 2441 temp = I915_READ(reg);
8db9d77b
ZW		 2442 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2443
2444 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2445 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2446 DRM_DEBUG_KMS("FDI train 2 done.\n");
2447 break;
2448 }
8db9d77b 2449 }
e1a44743 2450 if (tries == 5)
5eddb70b 2451 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2452
2453 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2454
8db9d77b
ZW		 2455}
2456
0206e353 2457static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2458 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2459 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2460 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2461 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2462};
2463
2464/* The FDI link training functions for SNB/Cougarpoint. */
2465static void gen6_fdi_link_train(struct drm_crtc *crtc)
2466{
2467 struct drm_device *dev = crtc->dev;
2468 struct drm_i915_private *dev_priv = dev->dev_private;
2469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2470 int pipe = intel_crtc->pipe;
fa37d39e 2471 u32 reg, temp, i, retry;
8db9d77b 2472
e1a44743
AJ		 2473 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2474 for train result */
5eddb70b
CW		 2475 reg = FDI_RX_IMR(pipe);
2476 temp = I915_READ(reg);
e1a44743
AJ		 2477 temp &= ~FDI_RX_SYMBOL_LOCK;
2478 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2479 I915_WRITE(reg, temp);
2480
2481 POSTING_READ(reg);
e1a44743
AJ		 2482 udelay(150);
2483
8db9d77b 2484 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2485 reg = FDI_TX_CTL(pipe);
2486 temp = I915_READ(reg);
77ffb597
AJ		 2487 temp &= ~(7 << 19);
2488 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2489 temp &= ~FDI_LINK_TRAIN_NONE;
2490 temp |= FDI_LINK_TRAIN_PATTERN_1;
2491 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2492 /* SNB-B */
2493 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2494 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2495
5eddb70b
CW		 2496 reg = FDI_RX_CTL(pipe);
2497 temp = I915_READ(reg);
8db9d77b
ZW		 2498 if (HAS_PCH_CPT(dev)) {
2499 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2500 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2501 } else {
2502 temp &= ~FDI_LINK_TRAIN_NONE;
2503 temp |= FDI_LINK_TRAIN_PATTERN_1;
2504 }
5eddb70b
CW		 2505 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2506
2507 POSTING_READ(reg);
8db9d77b
ZW		 2508 udelay(150);
2509
291427f5
JB		 2510 if (HAS_PCH_CPT(dev))
2511 cpt_phase_pointer_enable(dev, pipe);
2512
0206e353 2513 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2514 reg = FDI_TX_CTL(pipe);
2515 temp = I915_READ(reg);
8db9d77b
ZW		 2516 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2517 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2518 I915_WRITE(reg, temp);
2519
2520 POSTING_READ(reg);
8db9d77b
ZW		 2521 udelay(500);
2522
fa37d39e
SP		 2523 for (retry = 0; retry < 5; retry++) {
2524 reg = FDI_RX_IIR(pipe);
2525 temp = I915_READ(reg);
2526 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2527 if (temp & FDI_RX_BIT_LOCK) {
2528 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2529 DRM_DEBUG_KMS("FDI train 1 done.\n");
2530 break;
2531 }
2532 udelay(50);
8db9d77b 2533 }
fa37d39e
SP		 2534 if (retry < 5)
2535 break;
8db9d77b
ZW		 2536 }
2537 if (i == 4)
5eddb70b 2538 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2539
2540 /* Train 2 */
5eddb70b
CW		 2541 reg = FDI_TX_CTL(pipe);
2542 temp = I915_READ(reg);
8db9d77b
ZW		 2543 temp &= ~FDI_LINK_TRAIN_NONE;
2544 temp |= FDI_LINK_TRAIN_PATTERN_2;
2545 if (IS_GEN6(dev)) {
2546 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2547 /* SNB-B */
2548 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2549 }
5eddb70b 2550 I915_WRITE(reg, temp);
8db9d77b 2551
5eddb70b
CW		 2552 reg = FDI_RX_CTL(pipe);
2553 temp = I915_READ(reg);
8db9d77b
ZW		 2554 if (HAS_PCH_CPT(dev)) {
2555 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2556 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2557 } else {
2558 temp &= ~FDI_LINK_TRAIN_NONE;
2559 temp |= FDI_LINK_TRAIN_PATTERN_2;
2560 }
5eddb70b
CW		 2561 I915_WRITE(reg, temp);
2562
2563 POSTING_READ(reg);
8db9d77b
ZW		 2564 udelay(150);
2565
0206e353 2566 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2567 reg = FDI_TX_CTL(pipe);
2568 temp = I915_READ(reg);
8db9d77b
ZW		 2569 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2570 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2571 I915_WRITE(reg, temp);
2572
2573 POSTING_READ(reg);
8db9d77b
ZW		 2574 udelay(500);
2575
fa37d39e
SP		 2576 for (retry = 0; retry < 5; retry++) {
2577 reg = FDI_RX_IIR(pipe);
2578 temp = I915_READ(reg);
2579 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2580 if (temp & FDI_RX_SYMBOL_LOCK) {
2581 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2582 DRM_DEBUG_KMS("FDI train 2 done.\n");
2583 break;
2584 }
2585 udelay(50);
8db9d77b 2586 }
fa37d39e
SP		 2587 if (retry < 5)
2588 break;
8db9d77b
ZW		 2589 }
2590 if (i == 4)
5eddb70b 2591 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2592
2593 DRM_DEBUG_KMS("FDI train done.\n");
2594}
2595
357555c0
JB		 2596/* Manual link training for Ivy Bridge A0 parts */
2597static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2598{
2599 struct drm_device *dev = crtc->dev;
2600 struct drm_i915_private *dev_priv = dev->dev_private;
2601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2602 int pipe = intel_crtc->pipe;
2603 u32 reg, temp, i;
2604
2605 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2606 for train result */
2607 reg = FDI_RX_IMR(pipe);
2608 temp = I915_READ(reg);
2609 temp &= ~FDI_RX_SYMBOL_LOCK;
2610 temp &= ~FDI_RX_BIT_LOCK;
2611 I915_WRITE(reg, temp);
2612
2613 POSTING_READ(reg);
2614 udelay(150);
2615
2616 /* enable CPU FDI TX and PCH FDI RX */
2617 reg = FDI_TX_CTL(pipe);
2618 temp = I915_READ(reg);
2619 temp &= ~(7 << 19);
2620 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2621 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2622 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2623 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2624 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2625 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2626 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2627
2628 reg = FDI_RX_CTL(pipe);
2629 temp = I915_READ(reg);
2630 temp &= ~FDI_LINK_TRAIN_AUTO;
2631 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2632 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2633 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2634 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2635
2636 POSTING_READ(reg);
2637 udelay(150);
2638
291427f5
JB		 2639 if (HAS_PCH_CPT(dev))
2640 cpt_phase_pointer_enable(dev, pipe);
2641
0206e353 2642 for (i = 0; i < 4; i++) {
357555c0
JB		 2643 reg = FDI_TX_CTL(pipe);
2644 temp = I915_READ(reg);
2645 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2646 temp |= snb_b_fdi_train_param[i];
2647 I915_WRITE(reg, temp);
2648
2649 POSTING_READ(reg);
2650 udelay(500);
2651
2652 reg = FDI_RX_IIR(pipe);
2653 temp = I915_READ(reg);
2654 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2655
2656 if (temp & FDI_RX_BIT_LOCK ||
2657 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2658 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2659 DRM_DEBUG_KMS("FDI train 1 done.\n");
2660 break;
2661 }
2662 }
2663 if (i == 4)
2664 DRM_ERROR("FDI train 1 fail!\n");
2665
2666 /* Train 2 */
2667 reg = FDI_TX_CTL(pipe);
2668 temp = I915_READ(reg);
2669 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2670 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2671 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2672 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2673 I915_WRITE(reg, temp);
2674
2675 reg = FDI_RX_CTL(pipe);
2676 temp = I915_READ(reg);
2677 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2678 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2679 I915_WRITE(reg, temp);
2680
2681 POSTING_READ(reg);
2682 udelay(150);
2683
0206e353 2684 for (i = 0; i < 4; i++) {
357555c0
JB		 2685 reg = FDI_TX_CTL(pipe);
2686 temp = I915_READ(reg);
2687 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2688 temp |= snb_b_fdi_train_param[i];
2689 I915_WRITE(reg, temp);
2690
2691 POSTING_READ(reg);
2692 udelay(500);
2693
2694 reg = FDI_RX_IIR(pipe);
2695 temp = I915_READ(reg);
2696 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2697
2698 if (temp & FDI_RX_SYMBOL_LOCK) {
2699 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2700 DRM_DEBUG_KMS("FDI train 2 done.\n");
2701 break;
2702 }
2703 }
2704 if (i == 4)
2705 DRM_ERROR("FDI train 2 fail!\n");
2706
2707 DRM_DEBUG_KMS("FDI train done.\n");
2708}
2709
2710static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2711{
2712 struct drm_device *dev = crtc->dev;
2713 struct drm_i915_private *dev_priv = dev->dev_private;
2714 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2715 int pipe = intel_crtc->pipe;
5eddb70b 2716 u32 reg, temp;
79e53945 2717
c64e311e 2718 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2719 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2720 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2721
c98e9dcf 2722 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2723 reg = FDI_RX_CTL(pipe);
2724 temp = I915_READ(reg);
2725 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2726 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2727 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2728 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2729
2730 POSTING_READ(reg);
c98e9dcf
JB		 2731 udelay(200);
2732
2733 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2734 temp = I915_READ(reg);
2735 I915_WRITE(reg, temp | FDI_PCDCLK);
2736
2737 POSTING_READ(reg);
c98e9dcf
JB		 2738 udelay(200);
2739
bf507ef7
ED		 2740 /* On Haswell, the PLL configuration for ports and pipes is handled
2741 * separately, as part of DDI setup */
2742 if (!IS_HASWELL(dev)) {
2743 /* Enable CPU FDI TX PLL, always on for Ironlake */
2744 reg = FDI_TX_CTL(pipe);
2745 temp = I915_READ(reg);
2746 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2747 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2748
bf507ef7
ED		 2749 POSTING_READ(reg);
2750 udelay(100);
2751 }
6be4a607 2752 }
0e23b99d
JB		 2753}
2754
291427f5
JB		 2755static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2756{
2757 struct drm_i915_private *dev_priv = dev->dev_private;
2758 u32 flags = I915_READ(SOUTH_CHICKEN1);
2759
2760 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2761 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2762 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2763 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2764 POSTING_READ(SOUTH_CHICKEN1);
2765}
0fc932b8
JB		 2766static void ironlake_fdi_disable(struct drm_crtc *crtc)
2767{
2768 struct drm_device *dev = crtc->dev;
2769 struct drm_i915_private *dev_priv = dev->dev_private;
2770 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2771 int pipe = intel_crtc->pipe;
2772 u32 reg, temp;
2773
2774 /* disable CPU FDI tx and PCH FDI rx */
2775 reg = FDI_TX_CTL(pipe);
2776 temp = I915_READ(reg);
2777 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2778 POSTING_READ(reg);
2779
2780 reg = FDI_RX_CTL(pipe);
2781 temp = I915_READ(reg);
2782 temp &= ~(0x7 << 16);
2783 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2784 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2785
2786 POSTING_READ(reg);
2787 udelay(100);
2788
2789 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2790 if (HAS_PCH_IBX(dev)) {
2791 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2792 I915_WRITE(FDI_RX_CHICKEN(pipe),
2793 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2794 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2795 } else if (HAS_PCH_CPT(dev)) {
2796 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2797 }
0fc932b8
JB		 2798
2799 /* still set train pattern 1 */
2800 reg = FDI_TX_CTL(pipe);
2801 temp = I915_READ(reg);
2802 temp &= ~FDI_LINK_TRAIN_NONE;
2803 temp |= FDI_LINK_TRAIN_PATTERN_1;
2804 I915_WRITE(reg, temp);
2805
2806 reg = FDI_RX_CTL(pipe);
2807 temp = I915_READ(reg);
2808 if (HAS_PCH_CPT(dev)) {
2809 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2810 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2811 } else {
2812 temp &= ~FDI_LINK_TRAIN_NONE;
2813 temp |= FDI_LINK_TRAIN_PATTERN_1;
2814 }
2815 /* BPC in FDI rx is consistent with that in PIPECONF */
2816 temp &= ~(0x07 << 16);
2817 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2818 I915_WRITE(reg, temp);
2819
2820 POSTING_READ(reg);
2821 udelay(100);
2822}
2823
e6c3a2a6
CW		 2824static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2825{
0f91128d 2826 struct drm_device *dev = crtc->dev;
e6c3a2a6
CW		 2827
2828 if (crtc->fb == NULL)
2829 return;
2830
0f91128d
CW		 2831 mutex_lock(&dev->struct_mutex);
2832 intel_finish_fb(crtc->fb);
2833 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2834}
2835
040484af
JB		 2836static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2837{
2838 struct drm_device *dev = crtc->dev;
2839 struct drm_mode_config *mode_config = &dev->mode_config;
2840 struct intel_encoder *encoder;
2841
2842 /*
2843 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2844 * must be driven by its own crtc; no sharing is possible.
2845 */
2846 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2847 if (encoder->base.crtc != crtc)
2848 continue;
2849
6ee8bab0
ED		 2850 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2851 * CPU handles all others */
2852 if (IS_HASWELL(dev)) {
2853 /* It is still unclear how this will work on PPT, so throw up a warning */
2854 WARN_ON(!HAS_PCH_LPT(dev));
2855
2856 if (encoder->type == DRM_MODE_ENCODER_DAC) {
2857 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2858 return true;
2859 } else {
2860 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
2861 encoder->type);
2862 return false;
2863 }
2864 }
2865
040484af
JB		 2866 switch (encoder->type) {
2867 case INTEL_OUTPUT_EDP:
2868 if (!intel_encoder_is_pch_edp(&encoder->base))
2869 return false;
2870 continue;
2871 }
2872 }
2873
2874 return true;
2875}
2876
e615efe4
ED		 2877/* Program iCLKIP clock to the desired frequency */
2878static void lpt_program_iclkip(struct drm_crtc *crtc)
2879{
2880 struct drm_device *dev = crtc->dev;
2881 struct drm_i915_private *dev_priv = dev->dev_private;
2882 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2883 u32 temp;
2884
2885 /* It is necessary to ungate the pixclk gate prior to programming
2886 * the divisors, and gate it back when it is done.
2887 */
2888 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2889
2890 /* Disable SSCCTL */
2891 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2892 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2893 SBI_SSCCTL_DISABLE);
2894
2895 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2896 if (crtc->mode.clock == 20000) {
2897 auxdiv = 1;
2898 divsel = 0x41;
2899 phaseinc = 0x20;
2900 } else {
2901 /* The iCLK virtual clock root frequency is in MHz,
2902 * but the crtc->mode.clock in in KHz. To get the divisors,
2903 * it is necessary to divide one by another, so we
2904 * convert the virtual clock precision to KHz here for higher
2905 * precision.
2906 */
2907 u32 iclk_virtual_root_freq = 172800 * 1000;
2908 u32 iclk_pi_range = 64;
2909 u32 desired_divisor, msb_divisor_value, pi_value;
2910
2911 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2912 msb_divisor_value = desired_divisor / iclk_pi_range;
2913 pi_value = desired_divisor % iclk_pi_range;
2914
2915 auxdiv = 0;
2916 divsel = msb_divisor_value - 2;
2917 phaseinc = pi_value;
2918 }
2919
2920 /* This should not happen with any sane values */
2921 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2922 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2923 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2924 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2925
2926 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2927 crtc->mode.clock,
2928 auxdiv,
2929 divsel,
2930 phasedir,
2931 phaseinc);
2932
2933 /* Program SSCDIVINTPHASE6 */
2934 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2935 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2936 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2937 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2938 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2939 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2940 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2941
2942 intel_sbi_write(dev_priv,
2943 SBI_SSCDIVINTPHASE6,
2944 temp);
2945
2946 /* Program SSCAUXDIV */
2947 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2948 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2949 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2950 intel_sbi_write(dev_priv,
2951 SBI_SSCAUXDIV6,
2952 temp);
2953
2954
2955 /* Enable modulator and associated divider */
2956 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2957 temp &= ~SBI_SSCCTL_DISABLE;
2958 intel_sbi_write(dev_priv,
2959 SBI_SSCCTL6,
2960 temp);
2961
2962 /* Wait for initialization time */
2963 udelay(24);
2964
2965 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2966}
2967
f67a559d
JB		 2968/*
2969 * Enable PCH resources required for PCH ports:
2970 * - PCH PLLs
2971 * - FDI training & RX/TX
2972 * - update transcoder timings
2973 * - DP transcoding bits
2974 * - transcoder
2975 */
2976static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2977{
2978 struct drm_device *dev = crtc->dev;
2979 struct drm_i915_private *dev_priv = dev->dev_private;
2980 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2981 int pipe = intel_crtc->pipe;
ee7b9f93 2982 u32 reg, temp;
2c07245f 2983
e7e164db
CW		 2984 assert_transcoder_disabled(dev_priv, pipe);
2985
c98e9dcf 2986 /* For PCH output, training FDI link */
674cf967 2987 dev_priv->display.fdi_link_train(crtc);
2c07245f 2988
6f13b7b5
CW		 2989 intel_enable_pch_pll(intel_crtc);
2990
e615efe4
ED		 2991 if (HAS_PCH_LPT(dev)) {
2992 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
2993 lpt_program_iclkip(crtc);
2994 } else if (HAS_PCH_CPT(dev)) {
ee7b9f93 2995 u32 sel;
4b645f14 2996
c98e9dcf 2997 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 2998 switch (pipe) {
2999 default:
3000 case 0:
3001 temp |= TRANSA_DPLL_ENABLE;
3002 sel = TRANSA_DPLLB_SEL;
3003 break;
3004 case 1:
3005 temp |= TRANSB_DPLL_ENABLE;
3006 sel = TRANSB_DPLLB_SEL;
3007 break;
3008 case 2:
3009 temp |= TRANSC_DPLL_ENABLE;
3010 sel = TRANSC_DPLLB_SEL;
3011 break;
d64311ab 3012 }
ee7b9f93
JB		 3013 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3014 temp |= sel;
3015 else
3016 temp &= ~sel;
c98e9dcf 3017 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3018 }
5eddb70b 3019
d9b6cb56
JB		 3020 /* set transcoder timing, panel must allow it */
3021 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3022 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3023 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3024 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3025
5eddb70b
CW		 3026 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3027 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3028 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3029 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3030
f57e1e3a
ED		 3031 if (!IS_HASWELL(dev))
3032 intel_fdi_normal_train(crtc);
5e84e1a4 3033
c98e9dcf
JB		 3034 /* For PCH DP, enable TRANS_DP_CTL */
3035 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3036 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3037 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3038 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3039 reg = TRANS_DP_CTL(pipe);
3040 temp = I915_READ(reg);
3041 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3042 TRANS_DP_SYNC_MASK |
3043 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3044 temp |= (TRANS_DP_OUTPUT_ENABLE |
3045 TRANS_DP_ENH_FRAMING);
9325c9f0 3046 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3047
3048 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3049 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3050 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3051 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3052
3053 switch (intel_trans_dp_port_sel(crtc)) {
3054 case PCH_DP_B:
5eddb70b 3055 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3056 break;
3057 case PCH_DP_C:
5eddb70b 3058 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3059 break;
3060 case PCH_DP_D:
5eddb70b 3061 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3062 break;
3063 default:
3064 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 3065 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 3066 break;
32f9d658 3067 }
2c07245f 3068
5eddb70b 3069 I915_WRITE(reg, temp);
6be4a607 3070 }
b52eb4dc 3071
040484af 3072 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3073}
3074
ee7b9f93
JB		 3075static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3076{
3077 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3078
3079 if (pll == NULL)
3080 return;
3081
3082 if (pll->refcount == 0) {
3083 WARN(1, "bad PCH PLL refcount\n");
3084 return;
3085 }
3086
3087 --pll->refcount;
3088 intel_crtc->pch_pll = NULL;
3089}
3090
3091static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3092{
3093 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3094 struct intel_pch_pll *pll;
3095 int i;
3096
3097 pll = intel_crtc->pch_pll;
3098 if (pll) {
3099 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3100 intel_crtc->base.base.id, pll->pll_reg);
3101 goto prepare;
3102 }
3103
98b6bd99
DV		 3104 if (HAS_PCH_IBX(dev_priv->dev)) {
3105 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3106 i = intel_crtc->pipe;
3107 pll = &dev_priv->pch_plls[i];
3108
3109 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3110 intel_crtc->base.base.id, pll->pll_reg);
3111
3112 goto found;
3113 }
3114
ee7b9f93
JB		 3115 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3116 pll = &dev_priv->pch_plls[i];
3117
3118 /* Only want to check enabled timings first */
3119 if (pll->refcount == 0)
3120 continue;
3121
3122 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3123 fp == I915_READ(pll->fp0_reg)) {
3124 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3125 intel_crtc->base.base.id,
3126 pll->pll_reg, pll->refcount, pll->active);
3127
3128 goto found;
3129 }
3130 }
3131
3132 /* Ok no matching timings, maybe there's a free one? */
3133 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3134 pll = &dev_priv->pch_plls[i];
3135 if (pll->refcount == 0) {
3136 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3137 intel_crtc->base.base.id, pll->pll_reg);
3138 goto found;
3139 }
3140 }
3141
3142 return NULL;
3143
3144found:
3145 intel_crtc->pch_pll = pll;
3146 pll->refcount++;
3147 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3148prepare: /* separate function? */
3149 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3150
e04c7350
CW		 3151 /* Wait for the clocks to stabilize before rewriting the regs */
3152 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3153 POSTING_READ(pll->pll_reg);
3154 udelay(150);
e04c7350
CW		 3155
3156 I915_WRITE(pll->fp0_reg, fp);
3157 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3158 pll->on = false;
3159 return pll;
3160}
3161
d4270e57
JB		 3162void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3163{
3164 struct drm_i915_private *dev_priv = dev->dev_private;
3165 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3166 u32 temp;
3167
3168 temp = I915_READ(dslreg);
3169 udelay(500);
3170 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3171 /* Without this, mode sets may fail silently on FDI */
3172 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3173 udelay(250);
3174 I915_WRITE(tc2reg, 0);
3175 if (wait_for(I915_READ(dslreg) != temp, 5))
3176 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3177 }
3178}
3179
f67a559d
JB		 3180static void ironlake_crtc_enable(struct drm_crtc *crtc)
3181{
3182 struct drm_device *dev = crtc->dev;
3183 struct drm_i915_private *dev_priv = dev->dev_private;
3184 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3185 int pipe = intel_crtc->pipe;
3186 int plane = intel_crtc->plane;
3187 u32 temp;
3188 bool is_pch_port;
3189
3190 if (intel_crtc->active)
3191 return;
3192
3193 intel_crtc->active = true;
3194 intel_update_watermarks(dev);
3195
3196 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3197 temp = I915_READ(PCH_LVDS);
3198 if ((temp & LVDS_PORT_EN) == 0)
3199 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3200 }
3201
3202 is_pch_port = intel_crtc_driving_pch(crtc);
3203
3204 if (is_pch_port)
357555c0 3205 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 3206 else
3207 ironlake_fdi_disable(crtc);
3208
3209 /* Enable panel fitting for LVDS */
3210 if (dev_priv->pch_pf_size &&
3211 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3212 /* Force use of hard-coded filter coefficients
3213 * as some pre-programmed values are broken,
3214 * e.g. x201.
3215 */
9db4a9c7
JB		 3216 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3217 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3218 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3219 }
3220
9c54c0dd
JB		 3221 /*
3222 * On ILK+ LUT must be loaded before the pipe is running but with
3223 * clocks enabled
3224 */
3225 intel_crtc_load_lut(crtc);
3226
f67a559d
JB		 3227 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3228 intel_enable_plane(dev_priv, plane, pipe);
3229
3230 if (is_pch_port)
3231 ironlake_pch_enable(crtc);
c98e9dcf 3232
d1ebd816 3233 mutex_lock(&dev->struct_mutex);
bed4a673 3234 intel_update_fbc(dev);
d1ebd816
BW		 3235 mutex_unlock(&dev->struct_mutex);
3236
6b383a7f 3237 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 3238}
3239
3240static void ironlake_crtc_disable(struct drm_crtc *crtc)
3241{
3242 struct drm_device *dev = crtc->dev;
3243 struct drm_i915_private *dev_priv = dev->dev_private;
3244 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3245 int pipe = intel_crtc->pipe;
3246 int plane = intel_crtc->plane;
5eddb70b 3247 u32 reg, temp;
b52eb4dc 3248
f7abfe8b
CW		 3249 if (!intel_crtc->active)
3250 return;
3251
e6c3a2a6 3252 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3253 drm_vblank_off(dev, pipe);
6b383a7f 3254 intel_crtc_update_cursor(crtc, false);
5eddb70b 3255
b24e7179 3256 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3257
973d04f9
CW		 3258 if (dev_priv->cfb_plane == plane)
3259 intel_disable_fbc(dev);
2c07245f 3260
b24e7179 3261 intel_disable_pipe(dev_priv, pipe);
32f9d658 3262
6be4a607 3263 /* Disable PF */
9db4a9c7
JB		 3264 I915_WRITE(PF_CTL(pipe), 0);
3265 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3266
0fc932b8 3267 ironlake_fdi_disable(crtc);
2c07245f 3268
47a05eca
JB		 3269 /* This is a horrible layering violation; we should be doing this in
3270 * the connector/encoder ->prepare instead, but we don't always have
3271 * enough information there about the config to know whether it will
3272 * actually be necessary or just cause undesired flicker.
3273 */
3274 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 3275
040484af 3276 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3277
6be4a607
JB		 3278 if (HAS_PCH_CPT(dev)) {
3279 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3280 reg = TRANS_DP_CTL(pipe);
3281 temp = I915_READ(reg);
3282 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3283 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3284 I915_WRITE(reg, temp);
6be4a607
JB		 3285
3286 /* disable DPLL_SEL */
3287 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3288 switch (pipe) {
3289 case 0:
d64311ab 3290 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3291 break;
3292 case 1:
6be4a607 3293 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3294 break;
3295 case 2:
4b645f14 3296 /* C shares PLL A or B */
d64311ab 3297 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3298 break;
3299 default:
3300 BUG(); /* wtf */
3301 }
6be4a607 3302 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3303 }
e3421a18 3304
6be4a607 3305 /* disable PCH DPLL */
ee7b9f93 3306 intel_disable_pch_pll(intel_crtc);
8db9d77b 3307
6be4a607 3308 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 3309 reg = FDI_RX_CTL(pipe);
3310 temp = I915_READ(reg);
3311 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 3312
6be4a607 3313 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 3314 reg = FDI_TX_CTL(pipe);
3315 temp = I915_READ(reg);
3316 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3317
3318 POSTING_READ(reg);
6be4a607 3319 udelay(100);
8db9d77b 3320
5eddb70b
CW		 3321 reg = FDI_RX_CTL(pipe);
3322 temp = I915_READ(reg);
3323 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 3324
6be4a607 3325 /* Wait for the clocks to turn off. */
5eddb70b 3326 POSTING_READ(reg);
6be4a607 3327 udelay(100);
6b383a7f 3328
f7abfe8b 3329 intel_crtc->active = false;
6b383a7f 3330 intel_update_watermarks(dev);
d1ebd816
BW		 3331
3332 mutex_lock(&dev->struct_mutex);
6b383a7f 3333 intel_update_fbc(dev);
d1ebd816 3334 mutex_unlock(&dev->struct_mutex);
6be4a607 3335}
1b3c7a47 3336
6be4a607
JB		 3337static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3338{
3339 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3340 int pipe = intel_crtc->pipe;
3341 int plane = intel_crtc->plane;
8db9d77b 3342
6be4a607
JB		 3343 /* XXX: When our outputs are all unaware of DPMS modes other than off
3344 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3345 */
3346 switch (mode) {
3347 case DRM_MODE_DPMS_ON:
3348 case DRM_MODE_DPMS_STANDBY:
3349 case DRM_MODE_DPMS_SUSPEND:
3350 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3351 ironlake_crtc_enable(crtc);
3352 break;
1b3c7a47 3353
6be4a607
JB		 3354 case DRM_MODE_DPMS_OFF:
3355 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3356 ironlake_crtc_disable(crtc);
2c07245f
ZW		 3357 break;
3358 }
3359}
3360
ee7b9f93
JB		 3361static void ironlake_crtc_off(struct drm_crtc *crtc)
3362{
3363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3364 intel_put_pch_pll(intel_crtc);
3365}
3366
02e792fb
DV		 3367static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3368{
02e792fb 3369 if (!enable && intel_crtc->overlay) {
23f09ce3 3370 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3371 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3372
23f09ce3 3373 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3374 dev_priv->mm.interruptible = false;
3375 (void) intel_overlay_switch_off(intel_crtc->overlay);
3376 dev_priv->mm.interruptible = true;
23f09ce3 3377 mutex_unlock(&dev->struct_mutex);
02e792fb 3378 }
02e792fb 3379
5dcdbcb0
CW		 3380 /* Let userspace switch the overlay on again. In most cases userspace
3381 * has to recompute where to put it anyway.
3382 */
02e792fb
DV		 3383}
3384
0b8765c6 3385static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3386{
3387 struct drm_device *dev = crtc->dev;
79e53945
JB		 3388 struct drm_i915_private *dev_priv = dev->dev_private;
3389 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3390 int pipe = intel_crtc->pipe;
80824003 3391 int plane = intel_crtc->plane;
79e53945 3392
f7abfe8b
CW		 3393 if (intel_crtc->active)
3394 return;
3395
3396 intel_crtc->active = true;
6b383a7f
CW		 3397 intel_update_watermarks(dev);
3398
63d7bbe9 3399 intel_enable_pll(dev_priv, pipe);
040484af 3400 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3401 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3402
0b8765c6 3403 intel_crtc_load_lut(crtc);
bed4a673 3404 intel_update_fbc(dev);
79e53945 3405
0b8765c6
JB		 3406 /* Give the overlay scaler a chance to enable if it's on this pipe */
3407 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3408 intel_crtc_update_cursor(crtc, true);
0b8765c6 3409}
79e53945 3410
0b8765c6
JB		 3411static void i9xx_crtc_disable(struct drm_crtc *crtc)
3412{
3413 struct drm_device *dev = crtc->dev;
3414 struct drm_i915_private *dev_priv = dev->dev_private;
3415 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3416 int pipe = intel_crtc->pipe;
3417 int plane = intel_crtc->plane;
b690e96c 3418
f7abfe8b
CW		 3419 if (!intel_crtc->active)
3420 return;
3421
0b8765c6 3422 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3423 intel_crtc_wait_for_pending_flips(crtc);
3424 drm_vblank_off(dev, pipe);
0b8765c6 3425 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3426 intel_crtc_update_cursor(crtc, false);
0b8765c6 3427
973d04f9
CW		 3428 if (dev_priv->cfb_plane == plane)
3429 intel_disable_fbc(dev);
79e53945 3430
b24e7179 3431 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3432 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3433 intel_disable_pll(dev_priv, pipe);
0b8765c6 3434
f7abfe8b 3435 intel_crtc->active = false;
6b383a7f
CW		 3436 intel_update_fbc(dev);
3437 intel_update_watermarks(dev);
0b8765c6
JB		 3438}
3439
3440static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3441{
3442 /* XXX: When our outputs are all unaware of DPMS modes other than off
3443 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3444 */
3445 switch (mode) {
3446 case DRM_MODE_DPMS_ON:
3447 case DRM_MODE_DPMS_STANDBY:
3448 case DRM_MODE_DPMS_SUSPEND:
3449 i9xx_crtc_enable(crtc);
3450 break;
3451 case DRM_MODE_DPMS_OFF:
3452 i9xx_crtc_disable(crtc);
79e53945
JB		 3453 break;
3454 }
2c07245f
ZW		 3455}
3456
ee7b9f93
JB		 3457static void i9xx_crtc_off(struct drm_crtc *crtc)
3458{
3459}
3460
2c07245f
ZW		 3461/**
3462 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3463 */
3464static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3465{
3466 struct drm_device *dev = crtc->dev;
e70236a8 3467 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3468 struct drm_i915_master_private *master_priv;
3469 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3470 int pipe = intel_crtc->pipe;
3471 bool enabled;
3472
032d2a0d
CW		 3473 if (intel_crtc->dpms_mode == mode)
3474 return;
3475
65655d4a 3476 intel_crtc->dpms_mode = mode;
debcaddc 3477
e70236a8 3478 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3479
3480 if (!dev->primary->master)
3481 return;
3482
3483 master_priv = dev->primary->master->driver_priv;
3484 if (!master_priv->sarea_priv)
3485 return;
3486
3487 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3488
3489 switch (pipe) {
3490 case 0:
3491 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3492 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3493 break;
3494 case 1:
3495 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3496 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3497 break;
3498 default:
9db4a9c7 3499 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3500 break;
3501 }
79e53945
JB		 3502}
3503
cdd59983
CW		 3504static void intel_crtc_disable(struct drm_crtc *crtc)
3505{
3506 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3507 struct drm_device *dev = crtc->dev;
ee7b9f93 3508 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983
CW		 3509
3510 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
ee7b9f93
JB		 3511 dev_priv->display.off(crtc);
3512
931872fc
CW		 3513 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3514 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3515
3516 if (crtc->fb) {
3517 mutex_lock(&dev->struct_mutex);
1690e1eb 3518 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983
CW		 3519 mutex_unlock(&dev->struct_mutex);
3520 }
3521}
3522
7e7d76c3
JB		 3523/* Prepare for a mode set.
3524 *
3525 * Note we could be a lot smarter here. We need to figure out which outputs
3526 * will be enabled, which disabled (in short, how the config will changes)
3527 * and perform the minimum necessary steps to accomplish that, e.g. updating
3528 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3529 * panel fitting is in the proper state, etc.
3530 */
3531static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3532{
7e7d76c3 3533 i9xx_crtc_disable(crtc);
79e53945
JB		 3534}
3535
7e7d76c3 3536static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3537{
7e7d76c3 3538 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3539}
3540
3541static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3542{
7e7d76c3 3543 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3544}
3545
3546static void ironlake_crtc_commit(struct drm_crtc *crtc)
3547{
7e7d76c3 3548 ironlake_crtc_enable(crtc);
79e53945
JB		 3549}
3550
0206e353 3551void intel_encoder_prepare(struct drm_encoder *encoder)
79e53945
JB		 3552{
3553 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3554 /* lvds has its own version of prepare see intel_lvds_prepare */
3555 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3556}
3557
0206e353 3558void intel_encoder_commit(struct drm_encoder *encoder)
79e53945
JB		 3559{
3560 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
d4270e57 3561 struct drm_device *dev = encoder->dev;
d47d7cb8 3562 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
d4270e57 3563
79e53945
JB		 3564 /* lvds has its own version of commit see intel_lvds_commit */
3565 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
d4270e57
JB		 3566
3567 if (HAS_PCH_CPT(dev))
3568 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
79e53945
JB		 3569}
3570
ea5b213a
CW		 3571void intel_encoder_destroy(struct drm_encoder *encoder)
3572{
4ef69c7a 3573 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3574
ea5b213a
CW		 3575 drm_encoder_cleanup(encoder);
3576 kfree(intel_encoder);
3577}
3578
79e53945
JB		 3579static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3580 struct drm_display_mode *mode,
3581 struct drm_display_mode *adjusted_mode)
3582{
2c07245f 3583 struct drm_device *dev = crtc->dev;
89749350 3584
bad720ff 3585 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3586 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3587 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3588 return false;
2c07245f 3589 }
89749350 3590
f9bef081
DV		 3591 /* All interlaced capable intel hw wants timings in frames. Note though
3592 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3593 * timings, so we need to be careful not to clobber these.*/
3594 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3595 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3596
79e53945
JB		 3597 return true;
3598}
3599
25eb05fc
JB		 3600static int valleyview_get_display_clock_speed(struct drm_device *dev)
3601{
3602 return 400000; /* FIXME */
3603}
3604
e70236a8
JB		 3605static int i945_get_display_clock_speed(struct drm_device *dev)
3606{
3607 return 400000;
3608}
79e53945 3609
e70236a8 3610static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3611{
e70236a8
JB		 3612 return 333000;
3613}
79e53945 3614
e70236a8
JB		 3615static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3616{
3617 return 200000;
3618}
79e53945 3619
e70236a8
JB		 3620static int i915gm_get_display_clock_speed(struct drm_device *dev)
3621{
3622 u16 gcfgc = 0;
79e53945 3623
e70236a8
JB		 3624 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3625
3626 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3627 return 133000;
3628 else {
3629 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3630 case GC_DISPLAY_CLOCK_333_MHZ:
3631 return 333000;
3632 default:
3633 case GC_DISPLAY_CLOCK_190_200_MHZ:
3634 return 190000;
79e53945 3635 }
e70236a8
JB		 3636 }
3637}
3638
3639static int i865_get_display_clock_speed(struct drm_device *dev)
3640{
3641 return 266000;
3642}
3643
3644static int i855_get_display_clock_speed(struct drm_device *dev)
3645{
3646 u16 hpllcc = 0;
3647 /* Assume that the hardware is in the high speed state. This
3648 * should be the default.
3649 */
3650 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3651 case GC_CLOCK_133_200:
3652 case GC_CLOCK_100_200:
3653 return 200000;
3654 case GC_CLOCK_166_250:
3655 return 250000;
3656 case GC_CLOCK_100_133:
79e53945 3657 return 133000;
e70236a8 3658 }
79e53945 3659
e70236a8
JB		 3660 /* Shouldn't happen */
3661 return 0;
3662}
79e53945 3663
e70236a8
JB		 3664static int i830_get_display_clock_speed(struct drm_device *dev)
3665{
3666 return 133000;
79e53945
JB		 3667}
3668
2c07245f
ZW		 3669struct fdi_m_n {
3670 u32 tu;
3671 u32 gmch_m;
3672 u32 gmch_n;
3673 u32 link_m;
3674 u32 link_n;
3675};
3676
3677static void
3678fdi_reduce_ratio(u32 *num, u32 *den)
3679{
3680 while (*num > 0xffffff || *den > 0xffffff) {
3681 *num >>= 1;
3682 *den >>= 1;
3683 }
3684}
3685
2c07245f 3686static void
f2b115e6
AJ		 3687ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3688 int link_clock, struct fdi_m_n *m_n)
2c07245f 3689{
2c07245f
ZW		 3690 m_n->tu = 64; /* default size */
3691
22ed1113
CW		 3692 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3693 m_n->gmch_m = bits_per_pixel * pixel_clock;
3694 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3695 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3696
22ed1113
CW		 3697 m_n->link_m = pixel_clock;
3698 m_n->link_n = link_clock;
2c07245f
ZW		 3699 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3700}
3701
a7615030
CW		 3702static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3703{
72bbe58c
KP		 3704 if (i915_panel_use_ssc >= 0)
3705 return i915_panel_use_ssc != 0;
3706 return dev_priv->lvds_use_ssc
435793df 3707 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3708}
3709
5a354204
JB		 3710/**
3711 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3712 * @crtc: CRTC structure
3b5c78a3 3713 * @mode: requested mode
5a354204
JB		 3714 *
3715 * A pipe may be connected to one or more outputs. Based on the depth of the
3716 * attached framebuffer, choose a good color depth to use on the pipe.
3717 *
3718 * If possible, match the pipe depth to the fb depth. In some cases, this
3719 * isn't ideal, because the connected output supports a lesser or restricted
3720 * set of depths. Resolve that here:
3721 * LVDS typically supports only 6bpc, so clamp down in that case
3722 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3723 * Displays may support a restricted set as well, check EDID and clamp as
3724 * appropriate.
3b5c78a3 3725 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 3726 *
3727 * RETURNS:
3728 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3729 * true if they don't match).
3730 */
3731static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3b5c78a3
AJ		 3732 unsigned int *pipe_bpp,
3733 struct drm_display_mode *mode)
5a354204
JB		 3734{
3735 struct drm_device *dev = crtc->dev;
3736 struct drm_i915_private *dev_priv = dev->dev_private;
3737 struct drm_encoder *encoder;
3738 struct drm_connector *connector;
3739 unsigned int display_bpc = UINT_MAX, bpc;
3740
3741 /* Walk the encoders & connectors on this crtc, get min bpc */
3742 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
3743 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3744
3745 if (encoder->crtc != crtc)
3746 continue;
3747
3748 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3749 unsigned int lvds_bpc;
3750
3751 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3752 LVDS_A3_POWER_UP)
3753 lvds_bpc = 8;
3754 else
3755 lvds_bpc = 6;
3756
3757 if (lvds_bpc < display_bpc) {
82820490 3758 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 3759 display_bpc = lvds_bpc;
3760 }
3761 continue;
3762 }
3763
3764 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
3765 /* Use VBT settings if we have an eDP panel */
3766 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
3767
3768 if (edp_bpc < display_bpc) {
82820490 3769 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5a354204
JB		 3770 display_bpc = edp_bpc;
3771 }
3772 continue;
3773 }
3774
3775 /* Not one of the known troublemakers, check the EDID */
3776 list_for_each_entry(connector, &dev->mode_config.connector_list,
3777 head) {
3778 if (connector->encoder != encoder)
3779 continue;
3780
62ac41a6
JB		 3781 /* Don't use an invalid EDID bpc value */
3782 if (connector->display_info.bpc &&
3783 connector->display_info.bpc < display_bpc) {
82820490 3784 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 3785 display_bpc = connector->display_info.bpc;
3786 }
3787 }
3788
3789 /*
3790 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3791 * through, clamp it down. (Note: >12bpc will be caught below.)
3792 */
3793 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3794 if (display_bpc > 8 && display_bpc < 12) {
82820490 3795 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 3796 display_bpc = 12;
3797 } else {
82820490 3798 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 3799 display_bpc = 8;
3800 }
3801 }
3802 }
3803
3b5c78a3
AJ		 3804 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3805 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3806 display_bpc = 6;
3807 }
3808
5a354204
JB		 3809 /*
3810 * We could just drive the pipe at the highest bpc all the time and
3811 * enable dithering as needed, but that costs bandwidth. So choose
3812 * the minimum value that expresses the full color range of the fb but
3813 * also stays within the max display bpc discovered above.
3814 */
3815
3816 switch (crtc->fb->depth) {
3817 case 8:
3818 bpc = 8; /* since we go through a colormap */
3819 break;
3820 case 15:
3821 case 16:
3822 bpc = 6; /* min is 18bpp */
3823 break;
3824 case 24:
578393cd 3825 bpc = 8;
5a354204
JB		 3826 break;
3827 case 30:
578393cd 3828 bpc = 10;
5a354204
JB		 3829 break;
3830 case 48:
578393cd 3831 bpc = 12;
5a354204
JB		 3832 break;
3833 default:
3834 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3835 bpc = min((unsigned int)8, display_bpc);
3836 break;
3837 }
3838
578393cd
KP		 3839 display_bpc = min(display_bpc, bpc);
3840
82820490
AJ		 3841 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3842 bpc, display_bpc);
5a354204 3843
578393cd 3844 *pipe_bpp = display_bpc * 3;
5a354204
JB		 3845
3846 return display_bpc != bpc;
3847}
3848
a0c4da24
JB		 3849static int vlv_get_refclk(struct drm_crtc *crtc)
3850{
3851 struct drm_device *dev = crtc->dev;
3852 struct drm_i915_private *dev_priv = dev->dev_private;
3853 int refclk = 27000; /* for DP & HDMI */
3854
3855 return 100000; /* only one validated so far */
3856
3857 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3858 refclk = 96000;
3859 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3860 if (intel_panel_use_ssc(dev_priv))
3861 refclk = 100000;
3862 else
3863 refclk = 96000;
3864 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3865 refclk = 100000;
3866 }
3867
3868 return refclk;
3869}
3870
c65d77d8
JB		 3871static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3872{
3873 struct drm_device *dev = crtc->dev;
3874 struct drm_i915_private *dev_priv = dev->dev_private;
3875 int refclk;
3876
a0c4da24
JB		 3877 if (IS_VALLEYVIEW(dev)) {
3878 refclk = vlv_get_refclk(crtc);
3879 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 3880 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3881 refclk = dev_priv->lvds_ssc_freq * 1000;
3882 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3883 refclk / 1000);
3884 } else if (!IS_GEN2(dev)) {
3885 refclk = 96000;
3886 } else {
3887 refclk = 48000;
3888 }
3889
3890 return refclk;
3891}
3892
3893static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3894 intel_clock_t *clock)
3895{
3896 /* SDVO TV has fixed PLL values depend on its clock range,
3897 this mirrors vbios setting. */
3898 if (adjusted_mode->clock >= 100000
3899 && adjusted_mode->clock < 140500) {
3900 clock->p1 = 2;
3901 clock->p2 = 10;
3902 clock->n = 3;
3903 clock->m1 = 16;
3904 clock->m2 = 8;
3905 } else if (adjusted_mode->clock >= 140500
3906 && adjusted_mode->clock <= 200000) {
3907 clock->p1 = 1;
3908 clock->p2 = 10;
3909 clock->n = 6;
3910 clock->m1 = 12;
3911 clock->m2 = 8;
3912 }
3913}
3914
a7516a05
JB		 3915static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3916 intel_clock_t *clock,
3917 intel_clock_t *reduced_clock)
3918{
3919 struct drm_device *dev = crtc->dev;
3920 struct drm_i915_private *dev_priv = dev->dev_private;
3921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3922 int pipe = intel_crtc->pipe;
3923 u32 fp, fp2 = 0;
3924
3925 if (IS_PINEVIEW(dev)) {
3926 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3927 if (reduced_clock)
3928 fp2 = (1 << reduced_clock->n) << 16 |
3929 reduced_clock->m1 << 8 | reduced_clock->m2;
3930 } else {
3931 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3932 if (reduced_clock)
3933 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3934 reduced_clock->m2;
3935 }
3936
3937 I915_WRITE(FP0(pipe), fp);
3938
3939 intel_crtc->lowfreq_avail = false;
3940 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3941 reduced_clock && i915_powersave) {
3942 I915_WRITE(FP1(pipe), fp2);
3943 intel_crtc->lowfreq_avail = true;
3944 } else {
3945 I915_WRITE(FP1(pipe), fp);
3946 }
3947}
3948
93e537a1
DV		 3949static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3950 struct drm_display_mode *adjusted_mode)
3951{
3952 struct drm_device *dev = crtc->dev;
3953 struct drm_i915_private *dev_priv = dev->dev_private;
3954 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3955 int pipe = intel_crtc->pipe;
284d5df5 3956 u32 temp;
93e537a1
DV		 3957
3958 temp = I915_READ(LVDS);
3959 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3960 if (pipe == 1) {
3961 temp |= LVDS_PIPEB_SELECT;
3962 } else {
3963 temp &= ~LVDS_PIPEB_SELECT;
3964 }
3965 /* set the corresponsding LVDS_BORDER bit */
3966 temp |= dev_priv->lvds_border_bits;
3967 /* Set the B0-B3 data pairs corresponding to whether we're going to
3968 * set the DPLLs for dual-channel mode or not.
3969 */
3970 if (clock->p2 == 7)
3971 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3972 else
3973 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3974
3975 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3976 * appropriately here, but we need to look more thoroughly into how
3977 * panels behave in the two modes.
3978 */
3979 /* set the dithering flag on LVDS as needed */
3980 if (INTEL_INFO(dev)->gen >= 4) {
3981 if (dev_priv->lvds_dither)
3982 temp |= LVDS_ENABLE_DITHER;
3983 else
3984 temp &= ~LVDS_ENABLE_DITHER;
3985 }
284d5df5 3986 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 3987 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 3988 temp |= LVDS_HSYNC_POLARITY;
93e537a1 3989 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 3990 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 3991 I915_WRITE(LVDS, temp);
3992}
3993
a0c4da24
JB		 3994static void vlv_update_pll(struct drm_crtc *crtc,
3995 struct drm_display_mode *mode,
3996 struct drm_display_mode *adjusted_mode,
3997 intel_clock_t *clock, intel_clock_t *reduced_clock,
3998 int refclk, int num_connectors)
3999{
4000 struct drm_device *dev = crtc->dev;
4001 struct drm_i915_private *dev_priv = dev->dev_private;
4002 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4003 int pipe = intel_crtc->pipe;
4004 u32 dpll, mdiv, pdiv;
4005 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4006 bool is_hdmi;
4007
4008 is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4009
4010 bestn = clock->n;
4011 bestm1 = clock->m1;
4012 bestm2 = clock->m2;
4013 bestp1 = clock->p1;
4014 bestp2 = clock->p2;
4015
4016 /* Enable DPIO clock input */
4017 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4018 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4019 I915_WRITE(DPLL(pipe), dpll);
4020 POSTING_READ(DPLL(pipe));
4021
4022 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4023 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4024 mdiv |= ((bestn << DPIO_N_SHIFT));
4025 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4026 mdiv |= (1 << DPIO_K_SHIFT);
4027 mdiv |= DPIO_ENABLE_CALIBRATION;
4028 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4029
4030 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4031
4032 pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4033 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4034 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4035 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4036
4037 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4038
4039 dpll |= DPLL_VCO_ENABLE;
4040 I915_WRITE(DPLL(pipe), dpll);
4041 POSTING_READ(DPLL(pipe));
4042 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4043 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4044
4045 if (is_hdmi) {
4046 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4047
4048 if (temp > 1)
4049 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4050 else
4051 temp = 0;
4052
4053 I915_WRITE(DPLL_MD(pipe), temp);
4054 POSTING_READ(DPLL_MD(pipe));
4055 }
4056
4057 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4058}
4059
eb1cbe48
DV		 4060static void i9xx_update_pll(struct drm_crtc *crtc,
4061 struct drm_display_mode *mode,
4062 struct drm_display_mode *adjusted_mode,
4063 intel_clock_t *clock, intel_clock_t *reduced_clock,
4064 int num_connectors)
4065{
4066 struct drm_device *dev = crtc->dev;
4067 struct drm_i915_private *dev_priv = dev->dev_private;
4068 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4069 int pipe = intel_crtc->pipe;
4070 u32 dpll;
4071 bool is_sdvo;
4072
4073 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4074 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4075
4076 dpll = DPLL_VGA_MODE_DIS;
4077
4078 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4079 dpll |= DPLLB_MODE_LVDS;
4080 else
4081 dpll |= DPLLB_MODE_DAC_SERIAL;
4082 if (is_sdvo) {
4083 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4084 if (pixel_multiplier > 1) {
4085 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4086 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4087 }
4088 dpll |= DPLL_DVO_HIGH_SPEED;
4089 }
4090 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4091 dpll |= DPLL_DVO_HIGH_SPEED;
4092
4093 /* compute bitmask from p1 value */
4094 if (IS_PINEVIEW(dev))
4095 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4096 else {
4097 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4098 if (IS_G4X(dev) && reduced_clock)
4099 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4100 }
4101 switch (clock->p2) {
4102 case 5:
4103 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4104 break;
4105 case 7:
4106 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4107 break;
4108 case 10:
4109 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4110 break;
4111 case 14:
4112 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4113 break;
4114 }
4115 if (INTEL_INFO(dev)->gen >= 4)
4116 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4117
4118 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4119 dpll |= PLL_REF_INPUT_TVCLKINBC;
4120 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4121 /* XXX: just matching BIOS for now */
4122 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4123 dpll |= 3;
4124 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4125 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4126 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4127 else
4128 dpll |= PLL_REF_INPUT_DREFCLK;
4129
4130 dpll |= DPLL_VCO_ENABLE;
4131 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4132 POSTING_READ(DPLL(pipe));
4133 udelay(150);
4134
4135 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4136 * This is an exception to the general rule that mode_set doesn't turn
4137 * things on.
4138 */
4139 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4140 intel_update_lvds(crtc, clock, adjusted_mode);
4141
4142 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4143 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4144
4145 I915_WRITE(DPLL(pipe), dpll);
4146
4147 /* Wait for the clocks to stabilize. */
4148 POSTING_READ(DPLL(pipe));
4149 udelay(150);
4150
4151 if (INTEL_INFO(dev)->gen >= 4) {
4152 u32 temp = 0;
4153 if (is_sdvo) {
4154 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4155 if (temp > 1)
4156 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4157 else
4158 temp = 0;
4159 }
4160 I915_WRITE(DPLL_MD(pipe), temp);
4161 } else {
4162 /* The pixel multiplier can only be updated once the
4163 * DPLL is enabled and the clocks are stable.
4164 *
4165 * So write it again.
4166 */
4167 I915_WRITE(DPLL(pipe), dpll);
4168 }
4169}
4170
4171static void i8xx_update_pll(struct drm_crtc *crtc,
4172 struct drm_display_mode *adjusted_mode,
4173 intel_clock_t *clock,
4174 int num_connectors)
4175{
4176 struct drm_device *dev = crtc->dev;
4177 struct drm_i915_private *dev_priv = dev->dev_private;
4178 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4179 int pipe = intel_crtc->pipe;
4180 u32 dpll;
4181
4182 dpll = DPLL_VGA_MODE_DIS;
4183
4184 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4185 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4186 } else {
4187 if (clock->p1 == 2)
4188 dpll |= PLL_P1_DIVIDE_BY_TWO;
4189 else
4190 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4191 if (clock->p2 == 4)
4192 dpll |= PLL_P2_DIVIDE_BY_4;
4193 }
4194
4195 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4196 /* XXX: just matching BIOS for now */
4197 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4198 dpll |= 3;
4199 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4200 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4201 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4202 else
4203 dpll |= PLL_REF_INPUT_DREFCLK;
4204
4205 dpll |= DPLL_VCO_ENABLE;
4206 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4207 POSTING_READ(DPLL(pipe));
4208 udelay(150);
4209
4210 I915_WRITE(DPLL(pipe), dpll);
4211
4212 /* Wait for the clocks to stabilize. */
4213 POSTING_READ(DPLL(pipe));
4214 udelay(150);
4215
4216 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4217 * This is an exception to the general rule that mode_set doesn't turn
4218 * things on.
4219 */
4220 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4221 intel_update_lvds(crtc, clock, adjusted_mode);
4222
4223 /* The pixel multiplier can only be updated once the
4224 * DPLL is enabled and the clocks are stable.
4225 *
4226 * So write it again.
4227 */
4228 I915_WRITE(DPLL(pipe), dpll);
4229}
4230
f564048e
EA		 4231static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4232 struct drm_display_mode *mode,
4233 struct drm_display_mode *adjusted_mode,
4234 int x, int y,
4235 struct drm_framebuffer *old_fb)
79e53945
JB		 4236{
4237 struct drm_device *dev = crtc->dev;
4238 struct drm_i915_private *dev_priv = dev->dev_private;
4239 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4240 int pipe = intel_crtc->pipe;
80824003 4241 int plane = intel_crtc->plane;
c751ce4f 4242 int refclk, num_connectors = 0;
652c393a 4243 intel_clock_t clock, reduced_clock;
eb1cbe48
DV		 4244 u32 dspcntr, pipeconf, vsyncshift;
4245 bool ok, has_reduced_clock = false, is_sdvo = false;
4246 bool is_lvds = false, is_tv = false, is_dp = false;
79e53945 4247 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 4248 struct intel_encoder *encoder;
d4906093 4249 const intel_limit_t *limit;
5c3b82e2 4250 int ret;
79e53945 4251
5eddb70b
CW		 4252 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4253 if (encoder->base.crtc != crtc)
79e53945
JB		 4254 continue;
4255
5eddb70b 4256 switch (encoder->type) {
79e53945
JB		 4257 case INTEL_OUTPUT_LVDS:
4258 is_lvds = true;
4259 break;
4260 case INTEL_OUTPUT_SDVO:
7d57382e 4261 case INTEL_OUTPUT_HDMI:
79e53945 4262 is_sdvo = true;
5eddb70b 4263 if (encoder->needs_tv_clock)
e2f0ba97 4264 is_tv = true;
79e53945 4265 break;
79e53945
JB		 4266 case INTEL_OUTPUT_TVOUT:
4267 is_tv = true;
4268 break;
a4fc5ed6
KP		 4269 case INTEL_OUTPUT_DISPLAYPORT:
4270 is_dp = true;
4271 break;
79e53945 4272 }
43565a06 4273
c751ce4f 4274 num_connectors++;
79e53945
JB		 4275 }
4276
c65d77d8 4277 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4278
d4906093
ML		 4279 /*
4280 * Returns a set of divisors for the desired target clock with the given
4281 * refclk, or FALSE. The returned values represent the clock equation:
4282 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4283 */
1b894b59 4284 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4285 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4286 &clock);
79e53945
JB		 4287 if (!ok) {
4288 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4289 return -EINVAL;
79e53945
JB		 4290 }
4291
cda4b7d3 4292 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4293 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4294
ddc9003c 4295 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4296 /*
4297 * Ensure we match the reduced clock's P to the target clock.
4298 * If the clocks don't match, we can't switch the display clock
4299 * by using the FP0/FP1. In such case we will disable the LVDS
4300 * downclock feature.
4301 */
ddc9003c 4302 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4303 dev_priv->lvds_downclock,
4304 refclk,
cec2f356 4305 &clock,
5eddb70b 4306 &reduced_clock);
7026d4ac
ZW		 4307 }
4308
c65d77d8
JB		 4309 if (is_sdvo && is_tv)
4310 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4311
a7516a05
JB		 4312 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4313 &reduced_clock : NULL);
79e53945 4314
eb1cbe48
DV		 4315 if (IS_GEN2(dev))
4316 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
a0c4da24
JB		 4317 else if (IS_VALLEYVIEW(dev))
4318 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4319 refclk, num_connectors);
79e53945 4320 else
eb1cbe48
DV		 4321 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4322 has_reduced_clock ? &reduced_clock : NULL,
4323 num_connectors);
79e53945
JB		 4324
4325 /* setup pipeconf */
5eddb70b 4326 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4327
4328 /* Set up the display plane register */
4329 dspcntr = DISPPLANE_GAMMA_ENABLE;
4330
929c77fb
EA		 4331 if (pipe == 0)
4332 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4333 else
4334 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4335
a6c45cf0 4336 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4337 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4338 * core speed.
4339 *
4340 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4341 * pipe == 0 check?
4342 */
e70236a8
JB		 4343 if (mode->clock >
4344 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4345 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4346 else
5eddb70b 4347 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4348 }
4349
3b5c78a3
AJ		 4350 /* default to 8bpc */
4351 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4352 if (is_dp) {
4353 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4354 pipeconf |= PIPECONF_BPP_6 |
4355 PIPECONF_DITHER_EN |
4356 PIPECONF_DITHER_TYPE_SP;
4357 }
4358 }
4359
28c97730 4360 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4361 drm_mode_debug_printmodeline(mode);
4362
a7516a05
JB		 4363 if (HAS_PIPE_CXSR(dev)) {
4364 if (intel_crtc->lowfreq_avail) {
28c97730 4365 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4366 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4367 } else {
28c97730 4368 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4369 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4370 }
4371 }
4372
617cf884 4373 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575
DV		 4374 if (!IS_GEN2(dev) &&
4375 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157
KH		 4376 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4377 /* the chip adds 2 halflines automatically */
734b4157 4378 adjusted_mode->crtc_vtotal -= 1;
734b4157 4379 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4380 vsyncshift = adjusted_mode->crtc_hsync_start
4381 - adjusted_mode->crtc_htotal/2;
4382 } else {
617cf884 4383 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4384 vsyncshift = 0;
4385 }
4386
4387 if (!IS_GEN3(dev))
4388 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
734b4157 4389
5eddb70b
CW		 4390 I915_WRITE(HTOTAL(pipe),
4391 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4392 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4393 I915_WRITE(HBLANK(pipe),
4394 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4395 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4396 I915_WRITE(HSYNC(pipe),
4397 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4398 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4399
4400 I915_WRITE(VTOTAL(pipe),
4401 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4402 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4403 I915_WRITE(VBLANK(pipe),
4404 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4405 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4406 I915_WRITE(VSYNC(pipe),
4407 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4408 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 4409
4410 /* pipesrc and dspsize control the size that is scaled from,
4411 * which should always be the user's requested size.
79e53945 4412 */
929c77fb
EA		 4413 I915_WRITE(DSPSIZE(plane),
4414 ((mode->vdisplay - 1) << 16) |
4415 (mode->hdisplay - 1));
4416 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 4417 I915_WRITE(PIPESRC(pipe),
4418 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4419
f564048e
EA		 4420 I915_WRITE(PIPECONF(pipe), pipeconf);
4421 POSTING_READ(PIPECONF(pipe));
929c77fb 4422 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4423
4424 intel_wait_for_vblank(dev, pipe);
4425
f564048e
EA		 4426 I915_WRITE(DSPCNTR(plane), dspcntr);
4427 POSTING_READ(DSPCNTR(plane));
4428
4429 ret = intel_pipe_set_base(crtc, x, y, old_fb);
4430
4431 intel_update_watermarks(dev);
4432
f564048e
EA		 4433 return ret;
4434}
4435
9fb526db
KP		 4436/*
4437 * Initialize reference clocks when the driver loads
4438 */
4439void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4440{
4441 struct drm_i915_private *dev_priv = dev->dev_private;
4442 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4443 struct intel_encoder *encoder;
13d83a67
JB		 4444 u32 temp;
4445 bool has_lvds = false;
199e5d79
KP		 4446 bool has_cpu_edp = false;
4447 bool has_pch_edp = false;
4448 bool has_panel = false;
99eb6a01
KP		 4449 bool has_ck505 = false;
4450 bool can_ssc = false;
13d83a67
JB		 4451
4452 /* We need to take the global config into account */
199e5d79
KP		 4453 list_for_each_entry(encoder, &mode_config->encoder_list,
4454 base.head) {
4455 switch (encoder->type) {
4456 case INTEL_OUTPUT_LVDS:
4457 has_panel = true;
4458 has_lvds = true;
4459 break;
4460 case INTEL_OUTPUT_EDP:
4461 has_panel = true;
4462 if (intel_encoder_is_pch_edp(&encoder->base))
4463 has_pch_edp = true;
4464 else
4465 has_cpu_edp = true;
4466 break;
13d83a67
JB		 4467 }
4468 }
4469
99eb6a01
KP		 4470 if (HAS_PCH_IBX(dev)) {
4471 has_ck505 = dev_priv->display_clock_mode;
4472 can_ssc = has_ck505;
4473 } else {
4474 has_ck505 = false;
4475 can_ssc = true;
4476 }
4477
4478 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4479 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4480 has_ck505);
13d83a67
JB		 4481
4482 /* Ironlake: try to setup display ref clock before DPLL
4483 * enabling. This is only under driver's control after
4484 * PCH B stepping, previous chipset stepping should be
4485 * ignoring this setting.
4486 */
4487 temp = I915_READ(PCH_DREF_CONTROL);
4488 /* Always enable nonspread source */
4489 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4490
99eb6a01
KP		 4491 if (has_ck505)
4492 temp |= DREF_NONSPREAD_CK505_ENABLE;
4493 else
4494 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4495
199e5d79
KP		 4496 if (has_panel) {
4497 temp &= ~DREF_SSC_SOURCE_MASK;
4498 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4499
199e5d79 4500 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4501 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4502 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4503 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4504 } else
4505 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4506
4507 /* Get SSC going before enabling the outputs */
4508 I915_WRITE(PCH_DREF_CONTROL, temp);
4509 POSTING_READ(PCH_DREF_CONTROL);
4510 udelay(200);
4511
13d83a67
JB		 4512 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4513
4514 /* Enable CPU source on CPU attached eDP */
199e5d79 4515 if (has_cpu_edp) {
99eb6a01 4516 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4517 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4518 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4519 }
13d83a67
JB		 4520 else
4521 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4522 } else
4523 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4524
4525 I915_WRITE(PCH_DREF_CONTROL, temp);
4526 POSTING_READ(PCH_DREF_CONTROL);
4527 udelay(200);
4528 } else {
4529 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4530
4531 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4532
4533 /* Turn off CPU output */
4534 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4535
4536 I915_WRITE(PCH_DREF_CONTROL, temp);
4537 POSTING_READ(PCH_DREF_CONTROL);
4538 udelay(200);
4539
4540 /* Turn off the SSC source */
4541 temp &= ~DREF_SSC_SOURCE_MASK;
4542 temp |= DREF_SSC_SOURCE_DISABLE;
4543
4544 /* Turn off SSC1 */
4545 temp &= ~ DREF_SSC1_ENABLE;
4546
13d83a67
JB		 4547 I915_WRITE(PCH_DREF_CONTROL, temp);
4548 POSTING_READ(PCH_DREF_CONTROL);
4549 udelay(200);
4550 }
4551}
4552
d9d444cb
JB		 4553static int ironlake_get_refclk(struct drm_crtc *crtc)
4554{
4555 struct drm_device *dev = crtc->dev;
4556 struct drm_i915_private *dev_priv = dev->dev_private;
4557 struct intel_encoder *encoder;
4558 struct drm_mode_config *mode_config = &dev->mode_config;
4559 struct intel_encoder *edp_encoder = NULL;
4560 int num_connectors = 0;
4561 bool is_lvds = false;
4562
4563 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4564 if (encoder->base.crtc != crtc)
4565 continue;
4566
4567 switch (encoder->type) {
4568 case INTEL_OUTPUT_LVDS:
4569 is_lvds = true;
4570 break;
4571 case INTEL_OUTPUT_EDP:
4572 edp_encoder = encoder;
4573 break;
4574 }
4575 num_connectors++;
4576 }
4577
4578 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4579 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4580 dev_priv->lvds_ssc_freq);
4581 return dev_priv->lvds_ssc_freq * 1000;
4582 }
4583
4584 return 120000;
4585}
4586
f564048e
EA		 4587static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4588 struct drm_display_mode *mode,
4589 struct drm_display_mode *adjusted_mode,
4590 int x, int y,
4591 struct drm_framebuffer *old_fb)
79e53945
JB		 4592{
4593 struct drm_device *dev = crtc->dev;
4594 struct drm_i915_private *dev_priv = dev->dev_private;
4595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4596 int pipe = intel_crtc->pipe;
80824003 4597 int plane = intel_crtc->plane;
c751ce4f 4598 int refclk, num_connectors = 0;
652c393a 4599 intel_clock_t clock, reduced_clock;
5eddb70b 4600 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4601 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4602 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 4603 struct drm_mode_config *mode_config = &dev->mode_config;
e3aef172 4604 struct intel_encoder *encoder, *edp_encoder = NULL;
d4906093 4605 const intel_limit_t *limit;
5c3b82e2 4606 int ret;
2c07245f 4607 struct fdi_m_n m_n = {0};
fae14981 4608 u32 temp;
5a354204
JB		 4609 int target_clock, pixel_multiplier, lane, link_bw, factor;
4610 unsigned int pipe_bpp;
4611 bool dither;
e3aef172 4612 bool is_cpu_edp = false, is_pch_edp = false;
79e53945 4613
5eddb70b
CW		 4614 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4615 if (encoder->base.crtc != crtc)
79e53945
JB		 4616 continue;
4617
5eddb70b 4618 switch (encoder->type) {
79e53945
JB		 4619 case INTEL_OUTPUT_LVDS:
4620 is_lvds = true;
4621 break;
4622 case INTEL_OUTPUT_SDVO:
7d57382e 4623 case INTEL_OUTPUT_HDMI:
79e53945 4624 is_sdvo = true;
5eddb70b 4625 if (encoder->needs_tv_clock)
e2f0ba97 4626 is_tv = true;
79e53945 4627 break;
79e53945
JB		 4628 case INTEL_OUTPUT_TVOUT:
4629 is_tv = true;
4630 break;
4631 case INTEL_OUTPUT_ANALOG:
4632 is_crt = true;
4633 break;
a4fc5ed6
KP		 4634 case INTEL_OUTPUT_DISPLAYPORT:
4635 is_dp = true;
4636 break;
32f9d658 4637 case INTEL_OUTPUT_EDP:
e3aef172
JB		 4638 is_dp = true;
4639 if (intel_encoder_is_pch_edp(&encoder->base))
4640 is_pch_edp = true;
4641 else
4642 is_cpu_edp = true;
4643 edp_encoder = encoder;
32f9d658 4644 break;
79e53945 4645 }
43565a06 4646
c751ce4f 4647 num_connectors++;
79e53945
JB		 4648 }
4649
d9d444cb 4650 refclk = ironlake_get_refclk(crtc);
79e53945 4651
d4906093
ML		 4652 /*
4653 * Returns a set of divisors for the desired target clock with the given
4654 * refclk, or FALSE. The returned values represent the clock equation:
4655 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4656 */
1b894b59 4657 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4658 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4659 &clock);
79e53945
JB		 4660 if (!ok) {
4661 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4662 return -EINVAL;
79e53945
JB		 4663 }
4664
cda4b7d3 4665 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4666 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4667
ddc9003c 4668 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4669 /*
4670 * Ensure we match the reduced clock's P to the target clock.
4671 * If the clocks don't match, we can't switch the display clock
4672 * by using the FP0/FP1. In such case we will disable the LVDS
4673 * downclock feature.
4674 */
ddc9003c 4675 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4676 dev_priv->lvds_downclock,
4677 refclk,
cec2f356 4678 &clock,
5eddb70b 4679 &reduced_clock);
652c393a 4680 }
61e9653f
DV		 4681
4682 if (is_sdvo && is_tv)
4683 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4684
7026d4ac 4685
2c07245f 4686 /* FDI link */
8febb297
EA		 4687 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4688 lane = 0;
4689 /* CPU eDP doesn't require FDI link, so just set DP M/N
4690 according to current link config */
e3aef172 4691 if (is_cpu_edp) {
e3aef172 4692 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 4693 } else {
8febb297
EA		 4694 /* FDI is a binary signal running at ~2.7GHz, encoding
4695 * each output octet as 10 bits. The actual frequency
4696 * is stored as a divider into a 100MHz clock, and the
4697 * mode pixel clock is stored in units of 1KHz.
4698 * Hence the bw of each lane in terms of the mode signal
4699 * is:
4700 */
4701 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4702 }
58a27471 4703
94bf2ced
DV		 4704 /* [e]DP over FDI requires target mode clock instead of link clock. */
4705 if (edp_encoder)
4706 target_clock = intel_edp_target_clock(edp_encoder, mode);
4707 else if (is_dp)
4708 target_clock = mode->clock;
4709 else
4710 target_clock = adjusted_mode->clock;
4711
8febb297
EA		 4712 /* determine panel color depth */
4713 temp = I915_READ(PIPECONF(pipe));
4714 temp &= ~PIPE_BPC_MASK;
3b5c78a3 4715 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5a354204
JB		 4716 switch (pipe_bpp) {
4717 case 18:
4718 temp |= PIPE_6BPC;
8febb297 4719 break;
5a354204
JB		 4720 case 24:
4721 temp |= PIPE_8BPC;
8febb297 4722 break;
5a354204
JB		 4723 case 30:
4724 temp |= PIPE_10BPC;
8febb297 4725 break;
5a354204
JB		 4726 case 36:
4727 temp |= PIPE_12BPC;
8febb297
EA		 4728 break;
4729 default:
62ac41a6
JB		 4730 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4731 pipe_bpp);
5a354204
JB		 4732 temp |= PIPE_8BPC;
4733 pipe_bpp = 24;
4734 break;
8febb297 4735 }
77ffb597 4736
5a354204
JB		 4737 intel_crtc->bpp = pipe_bpp;
4738 I915_WRITE(PIPECONF(pipe), temp);
4739
8febb297
EA		 4740 if (!lane) {
4741 /*
4742 * Account for spread spectrum to avoid
4743 * oversubscribing the link. Max center spread
4744 * is 2.5%; use 5% for safety's sake.
4745 */
5a354204 4746 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 4747 lane = bps / (link_bw * 8) + 1;
5eb08b69 4748 }
2c07245f 4749
8febb297
EA		 4750 intel_crtc->fdi_lanes = lane;
4751
4752 if (pixel_multiplier > 1)
4753 link_bw *= pixel_multiplier;
5a354204
JB		 4754 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4755 &m_n);
8febb297 4756
a07d6787
EA		 4757 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4758 if (has_reduced_clock)
4759 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4760 reduced_clock.m2;
79e53945 4761
c1858123 4762 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4763 factor = 21;
4764 if (is_lvds) {
4765 if ((intel_panel_use_ssc(dev_priv) &&
4766 dev_priv->lvds_ssc_freq == 100) ||
4767 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4768 factor = 25;
4769 } else if (is_sdvo && is_tv)
4770 factor = 20;
c1858123 4771
cb0e0931 4772 if (clock.m < factor * clock.n)
8febb297 4773 fp |= FP_CB_TUNE;
2c07245f 4774
5eddb70b 4775 dpll = 0;
2c07245f 4776
a07d6787
EA		 4777 if (is_lvds)
4778 dpll |= DPLLB_MODE_LVDS;
4779 else
4780 dpll |= DPLLB_MODE_DAC_SERIAL;
4781 if (is_sdvo) {
4782 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4783 if (pixel_multiplier > 1) {
4784 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4785 }
a07d6787
EA		 4786 dpll |= DPLL_DVO_HIGH_SPEED;
4787 }
e3aef172 4788 if (is_dp && !is_cpu_edp)
a07d6787 4789 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4790
a07d6787
EA		 4791 /* compute bitmask from p1 value */
4792 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4793 /* also FPA1 */
4794 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4795
4796 switch (clock.p2) {
4797 case 5:
4798 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4799 break;
4800 case 7:
4801 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4802 break;
4803 case 10:
4804 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4805 break;
4806 case 14:
4807 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4808 break;
79e53945
JB		 4809 }
4810
43565a06
KH		 4811 if (is_sdvo && is_tv)
4812 dpll |= PLL_REF_INPUT_TVCLKINBC;
4813 else if (is_tv)
79e53945 4814 /* XXX: just matching BIOS for now */
43565a06 4815 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4816 dpll |= 3;
a7615030 4817 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4818 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4819 else
4820 dpll |= PLL_REF_INPUT_DREFCLK;
4821
4822 /* setup pipeconf */
5eddb70b 4823 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4824
4825 /* Set up the display plane register */
4826 dspcntr = DISPPLANE_GAMMA_ENABLE;
4827
f7cb34d4 4828 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 4829 drm_mode_debug_printmodeline(mode);
4830
9d82aa17
ED		 4831 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4832 * pre-Haswell/LPT generation */
4833 if (HAS_PCH_LPT(dev)) {
4834 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4835 pipe);
4836 } else if (!is_cpu_edp) {
ee7b9f93 4837 struct intel_pch_pll *pll;
4b645f14 4838
ee7b9f93
JB		 4839 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4840 if (pll == NULL) {
4841 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4842 pipe);
4b645f14
JB		 4843 return -EINVAL;
4844 }
ee7b9f93
JB		 4845 } else
4846 intel_put_pch_pll(intel_crtc);
79e53945
JB		 4847
4848 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4849 * This is an exception to the general rule that mode_set doesn't turn
4850 * things on.
4851 */
4852 if (is_lvds) {
fae14981 4853 temp = I915_READ(PCH_LVDS);
5eddb70b 4854 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 4855 if (HAS_PCH_CPT(dev)) {
4856 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 4857 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 4858 } else {
4859 if (pipe == 1)
4860 temp |= LVDS_PIPEB_SELECT;
4861 else
4862 temp &= ~LVDS_PIPEB_SELECT;
4863 }
4b645f14 4864
a3e17eb8 4865 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4866 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4867 /* Set the B0-B3 data pairs corresponding to whether we're going to
4868 * set the DPLLs for dual-channel mode or not.
4869 */
4870 if (clock.p2 == 7)
5eddb70b 4871 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4872 else
5eddb70b 4873 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4874
4875 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4876 * appropriately here, but we need to look more thoroughly into how
4877 * panels behave in the two modes.
4878 */
284d5df5 4879 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 4880 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4881 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 4882 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4883 temp |= LVDS_VSYNC_POLARITY;
fae14981 4884 I915_WRITE(PCH_LVDS, temp);
79e53945 4885 }
434ed097 4886
8febb297
EA		 4887 pipeconf &= ~PIPECONF_DITHER_EN;
4888 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 4889 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 4890 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 4891 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 4892 }
e3aef172 4893 if (is_dp && !is_cpu_edp) {
a4fc5ed6 4894 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 4895 } else {
8db9d77b 4896 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 4897 I915_WRITE(TRANSDATA_M1(pipe), 0);
4898 I915_WRITE(TRANSDATA_N1(pipe), 0);
4899 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4900 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 4901 }
79e53945 4902
ee7b9f93
JB		 4903 if (intel_crtc->pch_pll) {
4904 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 4905
32f9d658 4906 /* Wait for the clocks to stabilize. */
ee7b9f93 4907 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 4908 udelay(150);
4909
8febb297
EA		 4910 /* The pixel multiplier can only be updated once the
4911 * DPLL is enabled and the clocks are stable.
4912 *
4913 * So write it again.
4914 */
ee7b9f93 4915 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 4916 }
79e53945 4917
5eddb70b 4918 intel_crtc->lowfreq_avail = false;
ee7b9f93 4919 if (intel_crtc->pch_pll) {
4b645f14 4920 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 4921 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 4922 intel_crtc->lowfreq_avail = true;
4b645f14 4923 } else {
ee7b9f93 4924 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 4925 }
4926 }
4927
617cf884 4928 pipeconf &= ~PIPECONF_INTERLACE_MASK;
734b4157 4929 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5def474e 4930 pipeconf |= PIPECONF_INTERLACED_ILK;
734b4157 4931 /* the chip adds 2 halflines automatically */
734b4157 4932 adjusted_mode->crtc_vtotal -= 1;
734b4157 4933 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4934 I915_WRITE(VSYNCSHIFT(pipe),
4935 adjusted_mode->crtc_hsync_start
4936 - adjusted_mode->crtc_htotal/2);
4937 } else {
617cf884 4938 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4939 I915_WRITE(VSYNCSHIFT(pipe), 0);
4940 }
734b4157 4941
5eddb70b
CW		 4942 I915_WRITE(HTOTAL(pipe),
4943 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4944 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4945 I915_WRITE(HBLANK(pipe),
4946 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4947 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4948 I915_WRITE(HSYNC(pipe),
4949 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4950 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4951
4952 I915_WRITE(VTOTAL(pipe),
4953 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4954 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4955 I915_WRITE(VBLANK(pipe),
4956 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4957 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4958 I915_WRITE(VSYNC(pipe),
4959 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4960 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 4961
8febb297
EA		 4962 /* pipesrc controls the size that is scaled from, which should
4963 * always be the user's requested size.
79e53945 4964 */
5eddb70b
CW		 4965 I915_WRITE(PIPESRC(pipe),
4966 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4967
8febb297
EA		 4968 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4969 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4970 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4971 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 4972
e3aef172 4973 if (is_cpu_edp)
8febb297 4974 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 4975
5eddb70b
CW		 4976 I915_WRITE(PIPECONF(pipe), pipeconf);
4977 POSTING_READ(PIPECONF(pipe));
79e53945 4978
9d0498a2 4979 intel_wait_for_vblank(dev, pipe);
79e53945 4980
5eddb70b 4981 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 4982 POSTING_READ(DSPCNTR(plane));
79e53945 4983
5c3b82e2 4984 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 4985
4986 intel_update_watermarks(dev);
4987
1f8eeabf
ED		 4988 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
4989
1f803ee5 4990 return ret;
79e53945
JB		 4991}
4992
f564048e
EA		 4993static int intel_crtc_mode_set(struct drm_crtc *crtc,
4994 struct drm_display_mode *mode,
4995 struct drm_display_mode *adjusted_mode,
4996 int x, int y,
4997 struct drm_framebuffer *old_fb)
4998{
4999 struct drm_device *dev = crtc->dev;
5000 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5001 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5002 int pipe = intel_crtc->pipe;
f564048e
EA		 5003 int ret;
5004
0b701d27 5005 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5006
f564048e
EA		 5007 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5008 x, y, old_fb);
79e53945 5009 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5010
d8e70a25
JB		 5011 if (ret)
5012 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
5013 else
5014 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
120eced9 5015
1f803ee5 5016 return ret;
79e53945
JB		 5017}
5018
3a9627f4
WF		 5019static bool intel_eld_uptodate(struct drm_connector *connector,
5020 int reg_eldv, uint32_t bits_eldv,
5021 int reg_elda, uint32_t bits_elda,
5022 int reg_edid)
5023{
5024 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5025 uint8_t *eld = connector->eld;
5026 uint32_t i;
5027
5028 i = I915_READ(reg_eldv);
5029 i &= bits_eldv;
5030
5031 if (!eld[0])
5032 return !i;
5033
5034 if (!i)
5035 return false;
5036
5037 i = I915_READ(reg_elda);
5038 i &= ~bits_elda;
5039 I915_WRITE(reg_elda, i);
5040
5041 for (i = 0; i < eld[2]; i++)
5042 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5043 return false;
5044
5045 return true;
5046}
5047
e0dac65e
WF		 5048static void g4x_write_eld(struct drm_connector *connector,
5049 struct drm_crtc *crtc)
5050{
5051 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5052 uint8_t *eld = connector->eld;
5053 uint32_t eldv;
5054 uint32_t len;
5055 uint32_t i;
5056
5057 i = I915_READ(G4X_AUD_VID_DID);
5058
5059 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5060 eldv = G4X_ELDV_DEVCL_DEVBLC;
5061 else
5062 eldv = G4X_ELDV_DEVCTG;
5063
3a9627f4
WF		 5064 if (intel_eld_uptodate(connector,
5065 G4X_AUD_CNTL_ST, eldv,
5066 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5067 G4X_HDMIW_HDMIEDID))
5068 return;
5069
e0dac65e
WF		 5070 i = I915_READ(G4X_AUD_CNTL_ST);
5071 i &= ~(eldv | G4X_ELD_ADDR);
5072 len = (i >> 9) & 0x1f; /* ELD buffer size */
5073 I915_WRITE(G4X_AUD_CNTL_ST, i);
5074
5075 if (!eld[0])
5076 return;
5077
5078 len = min_t(uint8_t, eld[2], len);
5079 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5080 for (i = 0; i < len; i++)
5081 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5082
5083 i = I915_READ(G4X_AUD_CNTL_ST);
5084 i |= eldv;
5085 I915_WRITE(G4X_AUD_CNTL_ST, i);
5086}
5087
5088static void ironlake_write_eld(struct drm_connector *connector,
5089 struct drm_crtc *crtc)
5090{
5091 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5092 uint8_t *eld = connector->eld;
5093 uint32_t eldv;
5094 uint32_t i;
5095 int len;
5096 int hdmiw_hdmiedid;
b6daa025 5097 int aud_config;
e0dac65e
WF		 5098 int aud_cntl_st;
5099 int aud_cntrl_st2;
5100
b3f33cbf 5101 if (HAS_PCH_IBX(connector->dev)) {
1202b4c6 5102 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
b6daa025 5103 aud_config = IBX_AUD_CONFIG_A;
1202b4c6
WF		 5104 aud_cntl_st = IBX_AUD_CNTL_ST_A;
5105 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5106 } else {
1202b4c6 5107 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
b6daa025 5108 aud_config = CPT_AUD_CONFIG_A;
1202b4c6
WF		 5109 aud_cntl_st = CPT_AUD_CNTL_ST_A;
5110 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5111 }
5112
5113 i = to_intel_crtc(crtc)->pipe;
5114 hdmiw_hdmiedid += i * 0x100;
5115 aud_cntl_st += i * 0x100;
b6daa025 5116 aud_config += i * 0x100;
e0dac65e
WF		 5117
5118 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
5119
5120 i = I915_READ(aud_cntl_st);
5121 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
5122 if (!i) {
5123 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5124 /* operate blindly on all ports */
1202b4c6
WF		 5125 eldv = IBX_ELD_VALIDB;
5126 eldv |= IBX_ELD_VALIDB << 4;
5127 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5128 } else {
5129 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5130 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5131 }
5132
3a9627f4
WF		 5133 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5134 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5135 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5136 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5137 } else
5138 I915_WRITE(aud_config, 0);
e0dac65e 5139
3a9627f4
WF		 5140 if (intel_eld_uptodate(connector,
5141 aud_cntrl_st2, eldv,
5142 aud_cntl_st, IBX_ELD_ADDRESS,
5143 hdmiw_hdmiedid))
5144 return;
5145
e0dac65e
WF		 5146 i = I915_READ(aud_cntrl_st2);
5147 i &= ~eldv;
5148 I915_WRITE(aud_cntrl_st2, i);
5149
5150 if (!eld[0])
5151 return;
5152
e0dac65e 5153 i = I915_READ(aud_cntl_st);
1202b4c6 5154 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 5155 I915_WRITE(aud_cntl_st, i);
5156
5157 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5158 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5159 for (i = 0; i < len; i++)
5160 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5161
5162 i = I915_READ(aud_cntrl_st2);
5163 i |= eldv;
5164 I915_WRITE(aud_cntrl_st2, i);
5165}
5166
5167void intel_write_eld(struct drm_encoder *encoder,
5168 struct drm_display_mode *mode)
5169{
5170 struct drm_crtc *crtc = encoder->crtc;
5171 struct drm_connector *connector;
5172 struct drm_device *dev = encoder->dev;
5173 struct drm_i915_private *dev_priv = dev->dev_private;
5174
5175 connector = drm_select_eld(encoder, mode);
5176 if (!connector)
5177 return;
5178
5179 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5180 connector->base.id,
5181 drm_get_connector_name(connector),
5182 connector->encoder->base.id,
5183 drm_get_encoder_name(connector->encoder));
5184
5185 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5186
5187 if (dev_priv->display.write_eld)
5188 dev_priv->display.write_eld(connector, crtc);
5189}
5190
79e53945
JB		 5191/** Loads the palette/gamma unit for the CRTC with the prepared values */
5192void intel_crtc_load_lut(struct drm_crtc *crtc)
5193{
5194 struct drm_device *dev = crtc->dev;
5195 struct drm_i915_private *dev_priv = dev->dev_private;
5196 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5197 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5198 int i;
5199
5200 /* The clocks have to be on to load the palette. */
aed3f09d 5201 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 5202 return;
5203
f2b115e6 5204 /* use legacy palette for Ironlake */
bad720ff 5205 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5206 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5207
79e53945
JB		 5208 for (i = 0; i < 256; i++) {
5209 I915_WRITE(palreg + 4 * i,
5210 (intel_crtc->lut_r[i] << 16) |
5211 (intel_crtc->lut_g[i] << 8) |
5212 intel_crtc->lut_b[i]);
5213 }
5214}
5215
560b85bb
CW		 5216static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5217{
5218 struct drm_device *dev = crtc->dev;
5219 struct drm_i915_private *dev_priv = dev->dev_private;
5220 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5221 bool visible = base != 0;
5222 u32 cntl;
5223
5224 if (intel_crtc->cursor_visible == visible)
5225 return;
5226
9db4a9c7 5227 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5228 if (visible) {
5229 /* On these chipsets we can only modify the base whilst
5230 * the cursor is disabled.
5231 */
9db4a9c7 5232 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5233
5234 cntl &= ~(CURSOR_FORMAT_MASK);
5235 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5236 cntl |= CURSOR_ENABLE |
5237 CURSOR_GAMMA_ENABLE |
5238 CURSOR_FORMAT_ARGB;
5239 } else
5240 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5241 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5242
5243 intel_crtc->cursor_visible = visible;
5244}
5245
5246static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5247{
5248 struct drm_device *dev = crtc->dev;
5249 struct drm_i915_private *dev_priv = dev->dev_private;
5250 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5251 int pipe = intel_crtc->pipe;
5252 bool visible = base != 0;
5253
5254 if (intel_crtc->cursor_visible != visible) {
548f245b 5255 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5256 if (base) {
5257 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5258 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5259 cntl |= pipe << 28; /* Connect to correct pipe */
5260 } else {
5261 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5262 cntl |= CURSOR_MODE_DISABLE;
5263 }
9db4a9c7 5264 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5265
5266 intel_crtc->cursor_visible = visible;
5267 }
5268 /* and commit changes on next vblank */
9db4a9c7 5269 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5270}
5271
65a21cd6
JB		 5272static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5273{
5274 struct drm_device *dev = crtc->dev;
5275 struct drm_i915_private *dev_priv = dev->dev_private;
5276 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5277 int pipe = intel_crtc->pipe;
5278 bool visible = base != 0;
5279
5280 if (intel_crtc->cursor_visible != visible) {
5281 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5282 if (base) {
5283 cntl &= ~CURSOR_MODE;
5284 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5285 } else {
5286 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5287 cntl |= CURSOR_MODE_DISABLE;
5288 }
5289 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5290
5291 intel_crtc->cursor_visible = visible;
5292 }
5293 /* and commit changes on next vblank */
5294 I915_WRITE(CURBASE_IVB(pipe), base);
5295}
5296
cda4b7d3 5297/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5298static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5299 bool on)
cda4b7d3
CW		 5300{
5301 struct drm_device *dev = crtc->dev;
5302 struct drm_i915_private *dev_priv = dev->dev_private;
5303 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5304 int pipe = intel_crtc->pipe;
5305 int x = intel_crtc->cursor_x;
5306 int y = intel_crtc->cursor_y;
560b85bb 5307 u32 base, pos;
cda4b7d3
CW		 5308 bool visible;
5309
5310 pos = 0;
5311
6b383a7f 5312 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5313 base = intel_crtc->cursor_addr;
5314 if (x > (int) crtc->fb->width)
5315 base = 0;
5316
5317 if (y > (int) crtc->fb->height)
5318 base = 0;
5319 } else
5320 base = 0;
5321
5322 if (x < 0) {
5323 if (x + intel_crtc->cursor_width < 0)
5324 base = 0;
5325
5326 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5327 x = -x;
5328 }
5329 pos |= x << CURSOR_X_SHIFT;
5330
5331 if (y < 0) {
5332 if (y + intel_crtc->cursor_height < 0)
5333 base = 0;
5334
5335 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5336 y = -y;
5337 }
5338 pos |= y << CURSOR_Y_SHIFT;
5339
5340 visible = base != 0;
560b85bb 5341 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5342 return;
5343
0cd83aa9 5344 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 5345 I915_WRITE(CURPOS_IVB(pipe), pos);
5346 ivb_update_cursor(crtc, base);
5347 } else {
5348 I915_WRITE(CURPOS(pipe), pos);
5349 if (IS_845G(dev) || IS_I865G(dev))
5350 i845_update_cursor(crtc, base);
5351 else
5352 i9xx_update_cursor(crtc, base);
5353 }
cda4b7d3
CW		 5354}
5355
79e53945 5356static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5357 struct drm_file *file,
79e53945
JB		 5358 uint32_t handle,
5359 uint32_t width, uint32_t height)
5360{
5361 struct drm_device *dev = crtc->dev;
5362 struct drm_i915_private *dev_priv = dev->dev_private;
5363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5364 struct drm_i915_gem_object *obj;
cda4b7d3 5365 uint32_t addr;
3f8bc370 5366 int ret;
79e53945 5367
28c97730 5368 DRM_DEBUG_KMS("\n");
79e53945
JB		 5369
5370 /* if we want to turn off the cursor ignore width and height */
5371 if (!handle) {
28c97730 5372 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5373 addr = 0;
05394f39 5374 obj = NULL;
5004417d 5375 mutex_lock(&dev->struct_mutex);
3f8bc370 5376 goto finish;
79e53945
JB		 5377 }
5378
5379 /* Currently we only support 64x64 cursors */
5380 if (width != 64 || height != 64) {
5381 DRM_ERROR("we currently only support 64x64 cursors\n");
5382 return -EINVAL;
5383 }
5384
05394f39 5385 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5386 if (&obj->base == NULL)
79e53945
JB		 5387 return -ENOENT;
5388
05394f39 5389 if (obj->base.size < width * height * 4) {
79e53945 5390 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5391 ret = -ENOMEM;
5392 goto fail;
79e53945
JB		 5393 }
5394
71acb5eb 5395 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5396 mutex_lock(&dev->struct_mutex);
b295d1b6 5397 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5398 if (obj->tiling_mode) {
5399 DRM_ERROR("cursor cannot be tiled\n");
5400 ret = -EINVAL;
5401 goto fail_locked;
5402 }
5403
2da3b9b9 5404 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 5405 if (ret) {
5406 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 5407 goto fail_locked;
e7b526bb
CW		 5408 }
5409
d9e86c0e
CW		 5410 ret = i915_gem_object_put_fence(obj);
5411 if (ret) {
2da3b9b9 5412 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 5413 goto fail_unpin;
5414 }
5415
05394f39 5416 addr = obj->gtt_offset;
71acb5eb 5417 } else {
6eeefaf3 5418 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5419 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5420 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5421 align);
71acb5eb
DA		 5422 if (ret) {
5423 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5424 goto fail_locked;
71acb5eb 5425 }
05394f39 5426 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5427 }
5428
a6c45cf0 5429 if (IS_GEN2(dev))
14b60391
JB		 5430 I915_WRITE(CURSIZE, (height << 12) | width);
5431
3f8bc370 5432 finish:
3f8bc370 5433 if (intel_crtc->cursor_bo) {
b295d1b6 5434 if (dev_priv->info->cursor_needs_physical) {
05394f39 5435 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5436 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5437 } else
5438 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5439 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5440 }
80824003 5441
7f9872e0 5442 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5443
5444 intel_crtc->cursor_addr = addr;
05394f39 5445 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5446 intel_crtc->cursor_width = width;
5447 intel_crtc->cursor_height = height;
5448
6b383a7f 5449 intel_crtc_update_cursor(crtc, true);
3f8bc370 5450
79e53945 5451 return 0;
e7b526bb 5452fail_unpin:
05394f39 5453 i915_gem_object_unpin(obj);
7f9872e0 5454fail_locked:
34b8686e 5455 mutex_unlock(&dev->struct_mutex);
bc9025bd 5456fail:
05394f39 5457 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5458 return ret;
79e53945
JB		 5459}
5460
5461static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5462{
79e53945 5463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5464
cda4b7d3
CW		 5465 intel_crtc->cursor_x = x;
5466 intel_crtc->cursor_y = y;
652c393a 5467
6b383a7f 5468 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5469
5470 return 0;
5471}
5472
5473/** Sets the color ramps on behalf of RandR */
5474void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5475 u16 blue, int regno)
5476{
5477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5478
5479 intel_crtc->lut_r[regno] = red >> 8;
5480 intel_crtc->lut_g[regno] = green >> 8;
5481 intel_crtc->lut_b[regno] = blue >> 8;
5482}
5483
b8c00ac5
DA		 5484void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5485 u16 *blue, int regno)
5486{
5487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5488
5489 *red = intel_crtc->lut_r[regno] << 8;
5490 *green = intel_crtc->lut_g[regno] << 8;
5491 *blue = intel_crtc->lut_b[regno] << 8;
5492}
5493
79e53945 5494static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5495 u16 *blue, uint32_t start, uint32_t size)
79e53945 5496{
7203425a 5497 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5498 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5499
7203425a 5500 for (i = start; i < end; i++) {
79e53945
JB		 5501 intel_crtc->lut_r[i] = red[i] >> 8;
5502 intel_crtc->lut_g[i] = green[i] >> 8;
5503 intel_crtc->lut_b[i] = blue[i] >> 8;
5504 }
5505
5506 intel_crtc_load_lut(crtc);
5507}
5508
5509/**
5510 * Get a pipe with a simple mode set on it for doing load-based monitor
5511 * detection.
5512 *
5513 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5514 * its requirements. The pipe will be connected to no other encoders.
79e53945 5515 *
c751ce4f 5516 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5517 * configured for it. In the future, it could choose to temporarily disable
5518 * some outputs to free up a pipe for its use.
5519 *
5520 * \return crtc, or NULL if no pipes are available.
5521 */
5522
5523/* VESA 640x480x72Hz mode to set on the pipe */
5524static struct drm_display_mode load_detect_mode = {
5525 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5526 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5527};
5528
d2dff872
CW		 5529static struct drm_framebuffer *
5530intel_framebuffer_create(struct drm_device *dev,
308e5bcb 5531 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 5532 struct drm_i915_gem_object *obj)
5533{
5534 struct intel_framebuffer *intel_fb;
5535 int ret;
5536
5537 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5538 if (!intel_fb) {
5539 drm_gem_object_unreference_unlocked(&obj->base);
5540 return ERR_PTR(-ENOMEM);
5541 }
5542
5543 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5544 if (ret) {
5545 drm_gem_object_unreference_unlocked(&obj->base);
5546 kfree(intel_fb);
5547 return ERR_PTR(ret);
5548 }
5549
5550 return &intel_fb->base;
5551}
5552
5553static u32
5554intel_framebuffer_pitch_for_width(int width, int bpp)
5555{
5556 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5557 return ALIGN(pitch, 64);
5558}
5559
5560static u32
5561intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5562{
5563 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5564 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5565}
5566
5567static struct drm_framebuffer *
5568intel_framebuffer_create_for_mode(struct drm_device *dev,
5569 struct drm_display_mode *mode,
5570 int depth, int bpp)
5571{
5572 struct drm_i915_gem_object *obj;
308e5bcb 5573 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 5574
5575 obj = i915_gem_alloc_object(dev,
5576 intel_framebuffer_size_for_mode(mode, bpp));
5577 if (obj == NULL)
5578 return ERR_PTR(-ENOMEM);
5579
5580 mode_cmd.width = mode->hdisplay;
5581 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 5582 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5583 bpp);
5ca0c34a 5584 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 5585
5586 return intel_framebuffer_create(dev, &mode_cmd, obj);
5587}
5588
5589static struct drm_framebuffer *
5590mode_fits_in_fbdev(struct drm_device *dev,
5591 struct drm_display_mode *mode)
5592{
5593 struct drm_i915_private *dev_priv = dev->dev_private;
5594 struct drm_i915_gem_object *obj;
5595 struct drm_framebuffer *fb;
5596
5597 if (dev_priv->fbdev == NULL)
5598 return NULL;
5599
5600 obj = dev_priv->fbdev->ifb.obj;
5601 if (obj == NULL)
5602 return NULL;
5603
5604 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 5605 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5606 fb->bits_per_pixel))
d2dff872
CW		 5607 return NULL;
5608
01f2c773 5609 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 5610 return NULL;
5611
5612 return fb;
5613}
5614
7173188d
CW		 5615bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
5616 struct drm_connector *connector,
5617 struct drm_display_mode *mode,
8261b191 5618 struct intel_load_detect_pipe *old)
79e53945
JB		 5619{
5620 struct intel_crtc *intel_crtc;
5621 struct drm_crtc *possible_crtc;
4ef69c7a 5622 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5623 struct drm_crtc *crtc = NULL;
5624 struct drm_device *dev = encoder->dev;
d2dff872 5625 struct drm_framebuffer *old_fb;
79e53945
JB		 5626 int i = -1;
5627
d2dff872
CW		 5628 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5629 connector->base.id, drm_get_connector_name(connector),
5630 encoder->base.id, drm_get_encoder_name(encoder));
5631
79e53945
JB		 5632 /*
5633 * Algorithm gets a little messy:
7a5e4805 5634 *
79e53945
JB		 5635 * - if the connector already has an assigned crtc, use it (but make
5636 * sure it's on first)
7a5e4805 5637 *
79e53945
JB		 5638 * - try to find the first unused crtc that can drive this connector,
5639 * and use that if we find one
79e53945
JB		 5640 */
5641
5642 /* See if we already have a CRTC for this connector */
5643 if (encoder->crtc) {
5644 crtc = encoder->crtc;
8261b191 5645
79e53945 5646 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5647 old->dpms_mode = intel_crtc->dpms_mode;
5648 old->load_detect_temp = false;
5649
5650 /* Make sure the crtc and connector are running */
79e53945 5651 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 5652 struct drm_encoder_helper_funcs *encoder_funcs;
5653 struct drm_crtc_helper_funcs *crtc_funcs;
5654
79e53945
JB		 5655 crtc_funcs = crtc->helper_private;
5656 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 5657
5658 encoder_funcs = encoder->helper_private;
79e53945
JB		 5659 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
5660 }
8261b191 5661
7173188d 5662 return true;
79e53945
JB		 5663 }
5664
5665 /* Find an unused one (if possible) */
5666 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5667 i++;
5668 if (!(encoder->possible_crtcs & (1 << i)))
5669 continue;
5670 if (!possible_crtc->enabled) {
5671 crtc = possible_crtc;
5672 break;
5673 }
79e53945
JB		 5674 }
5675
5676 /*
5677 * If we didn't find an unused CRTC, don't use any.
5678 */
5679 if (!crtc) {
7173188d
CW		 5680 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5681 return false;
79e53945
JB		 5682 }
5683
5684 encoder->crtc = crtc;
c1c43977 5685 connector->encoder = encoder;
79e53945
JB		 5686
5687 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 5688 old->dpms_mode = intel_crtc->dpms_mode;
5689 old->load_detect_temp = true;
d2dff872 5690 old->release_fb = NULL;
79e53945 5691
6492711d
CW		 5692 if (!mode)
5693 mode = &load_detect_mode;
79e53945 5694
d2dff872
CW		 5695 old_fb = crtc->fb;
5696
5697 /* We need a framebuffer large enough to accommodate all accesses
5698 * that the plane may generate whilst we perform load detection.
5699 * We can not rely on the fbcon either being present (we get called
5700 * during its initialisation to detect all boot displays, or it may
5701 * not even exist) or that it is large enough to satisfy the
5702 * requested mode.
5703 */
5704 crtc->fb = mode_fits_in_fbdev(dev, mode);
5705 if (crtc->fb == NULL) {
5706 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
5707 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5708 old->release_fb = crtc->fb;
5709 } else
5710 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
5711 if (IS_ERR(crtc->fb)) {
5712 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
5713 crtc->fb = old_fb;
5714 return false;
79e53945 5715 }
79e53945 5716
d2dff872 5717 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 5718 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5719 if (old->release_fb)
5720 old->release_fb->funcs->destroy(old->release_fb);
5721 crtc->fb = old_fb;
6492711d 5722 return false;
79e53945 5723 }
7173188d 5724
79e53945 5725 /* let the connector get through one full cycle before testing */
9d0498a2 5726 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5727
7173188d 5728 return true;
79e53945
JB		 5729}
5730
c1c43977 5731void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 5732 struct drm_connector *connector,
5733 struct intel_load_detect_pipe *old)
79e53945 5734{
4ef69c7a 5735 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5736 struct drm_device *dev = encoder->dev;
5737 struct drm_crtc *crtc = encoder->crtc;
5738 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
5739 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
5740
d2dff872
CW		 5741 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5742 connector->base.id, drm_get_connector_name(connector),
5743 encoder->base.id, drm_get_encoder_name(encoder));
5744
8261b191 5745 if (old->load_detect_temp) {
c1c43977 5746 connector->encoder = NULL;
79e53945 5747 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 5748
5749 if (old->release_fb)
5750 old->release_fb->funcs->destroy(old->release_fb);
5751
0622a53c 5752 return;
79e53945
JB		 5753 }
5754
c751ce4f 5755 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 5756 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
5757 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 5758 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 5759 }
5760}
5761
5762/* Returns the clock of the currently programmed mode of the given pipe. */
5763static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5764{
5765 struct drm_i915_private *dev_priv = dev->dev_private;
5766 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5767 int pipe = intel_crtc->pipe;
548f245b 5768 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5769 u32 fp;
5770 intel_clock_t clock;
5771
5772 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5773 fp = I915_READ(FP0(pipe));
79e53945 5774 else
39adb7a5 5775 fp = I915_READ(FP1(pipe));
79e53945
JB		 5776
5777 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5778 if (IS_PINEVIEW(dev)) {
5779 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5780 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5781 } else {
5782 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5783 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5784 }
5785
a6c45cf0 5786 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5787 if (IS_PINEVIEW(dev))
5788 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5789 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5790 else
5791 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5792 DPLL_FPA01_P1_POST_DIV_SHIFT);
5793
5794 switch (dpll & DPLL_MODE_MASK) {
5795 case DPLLB_MODE_DAC_SERIAL:
5796 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5797 5 : 10;
5798 break;
5799 case DPLLB_MODE_LVDS:
5800 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5801 7 : 14;
5802 break;
5803 default:
28c97730 5804 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5805 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5806 return 0;
5807 }
5808
5809 /* XXX: Handle the 100Mhz refclk */
2177832f 5810 intel_clock(dev, 96000, &clock);
79e53945
JB		 5811 } else {
5812 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5813
5814 if (is_lvds) {
5815 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5816 DPLL_FPA01_P1_POST_DIV_SHIFT);
5817 clock.p2 = 14;
5818
5819 if ((dpll & PLL_REF_INPUT_MASK) ==
5820 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5821 /* XXX: might not be 66MHz */
2177832f 5822 intel_clock(dev, 66000, &clock);
79e53945 5823 } else
2177832f 5824 intel_clock(dev, 48000, &clock);
79e53945
JB		 5825 } else {
5826 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5827 clock.p1 = 2;
5828 else {
5829 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5830 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5831 }
5832 if (dpll & PLL_P2_DIVIDE_BY_4)
5833 clock.p2 = 4;
5834 else
5835 clock.p2 = 2;
5836
2177832f 5837 intel_clock(dev, 48000, &clock);
79e53945
JB		 5838 }
5839 }
5840
5841 /* XXX: It would be nice to validate the clocks, but we can't reuse
5842 * i830PllIsValid() because it relies on the xf86_config connector
5843 * configuration being accurate, which it isn't necessarily.
5844 */
5845
5846 return clock.dot;
5847}
5848
5849/** Returns the currently programmed mode of the given pipe. */
5850struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5851 struct drm_crtc *crtc)
5852{
548f245b 5853 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5854 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5855 int pipe = intel_crtc->pipe;
5856 struct drm_display_mode *mode;
548f245b
JB		 5857 int htot = I915_READ(HTOTAL(pipe));
5858 int hsync = I915_READ(HSYNC(pipe));
5859 int vtot = I915_READ(VTOTAL(pipe));
5860 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5861
5862 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5863 if (!mode)
5864 return NULL;
5865
5866 mode->clock = intel_crtc_clock_get(dev, crtc);
5867 mode->hdisplay = (htot & 0xffff) + 1;
5868 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5869 mode->hsync_start = (hsync & 0xffff) + 1;
5870 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5871 mode->vdisplay = (vtot & 0xffff) + 1;
5872 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5873 mode->vsync_start = (vsync & 0xffff) + 1;
5874 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5875
5876 drm_mode_set_name(mode);
79e53945
JB		 5877
5878 return mode;
5879}
5880
652c393a
JB		 5881#define GPU_IDLE_TIMEOUT 500 /* ms */
5882
5883/* When this timer fires, we've been idle for awhile */
5884static void intel_gpu_idle_timer(unsigned long arg)
5885{
5886 struct drm_device *dev = (struct drm_device *)arg;
5887 drm_i915_private_t *dev_priv = dev->dev_private;
5888
ff7ea4c0
CW		 5889 if (!list_empty(&dev_priv->mm.active_list)) {
5890 /* Still processing requests, so just re-arm the timer. */
5891 mod_timer(&dev_priv->idle_timer, jiffies +
5892 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
5893 return;
5894 }
652c393a 5895
ff7ea4c0 5896 dev_priv->busy = false;
01dfba93 5897 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5898}
5899
652c393a
JB		 5900#define CRTC_IDLE_TIMEOUT 1000 /* ms */
5901
5902static void intel_crtc_idle_timer(unsigned long arg)
5903{
5904 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
5905 struct drm_crtc *crtc = &intel_crtc->base;
5906 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 5907 struct intel_framebuffer *intel_fb;
652c393a 5908
ff7ea4c0
CW		 5909 intel_fb = to_intel_framebuffer(crtc->fb);
5910 if (intel_fb && intel_fb->obj->active) {
5911 /* The framebuffer is still being accessed by the GPU. */
5912 mod_timer(&intel_crtc->idle_timer, jiffies +
5913 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
5914 return;
5915 }
652c393a 5916
ff7ea4c0 5917 intel_crtc->busy = false;
01dfba93 5918 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 5919}
5920
3dec0095 5921static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 5922{
5923 struct drm_device *dev = crtc->dev;
5924 drm_i915_private_t *dev_priv = dev->dev_private;
5925 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5926 int pipe = intel_crtc->pipe;
dbdc6479
JB		 5927 int dpll_reg = DPLL(pipe);
5928 int dpll;
652c393a 5929
bad720ff 5930 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5931 return;
5932
5933 if (!dev_priv->lvds_downclock_avail)
5934 return;
5935
dbdc6479 5936 dpll = I915_READ(dpll_reg);
652c393a 5937 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 5938 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 5939
8ac5a6d5 5940 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 5941
5942 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5943 I915_WRITE(dpll_reg, dpll);
9d0498a2 5944 intel_wait_for_vblank(dev, pipe);
dbdc6479 5945
652c393a
JB		 5946 dpll = I915_READ(dpll_reg);
5947 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 5948 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 5949 }
5950
5951 /* Schedule downclock */
3dec0095
DV		 5952 mod_timer(&intel_crtc->idle_timer, jiffies +
5953 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 5954}
5955
5956static void intel_decrease_pllclock(struct drm_crtc *crtc)
5957{
5958 struct drm_device *dev = crtc->dev;
5959 drm_i915_private_t *dev_priv = dev->dev_private;
5960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 5961
bad720ff 5962 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5963 return;
5964
5965 if (!dev_priv->lvds_downclock_avail)
5966 return;
5967
5968 /*
5969 * Since this is called by a timer, we should never get here in
5970 * the manual case.
5971 */
5972 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 5973 int pipe = intel_crtc->pipe;
5974 int dpll_reg = DPLL(pipe);
5975 int dpll;
f6e5b160 5976
44d98a61 5977 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 5978
8ac5a6d5 5979 assert_panel_unlocked(dev_priv, pipe);
652c393a 5980
dc257cf1 5981 dpll = I915_READ(dpll_reg);
652c393a
JB		 5982 dpll |= DISPLAY_RATE_SELECT_FPA1;
5983 I915_WRITE(dpll_reg, dpll);
9d0498a2 5984 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 5985 dpll = I915_READ(dpll_reg);
5986 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 5987 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 5988 }
5989
5990}
5991
5992/**
5993 * intel_idle_update - adjust clocks for idleness
5994 * @work: work struct
5995 *
5996 * Either the GPU or display (or both) went idle. Check the busy status
5997 * here and adjust the CRTC and GPU clocks as necessary.
5998 */
5999static void intel_idle_update(struct work_struct *work)
6000{
6001 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6002 idle_work);
6003 struct drm_device *dev = dev_priv->dev;
6004 struct drm_crtc *crtc;
6005 struct intel_crtc *intel_crtc;
6006
6007 if (!i915_powersave)
6008 return;
6009
6010 mutex_lock(&dev->struct_mutex);
6011
7648fa99
JB		 6012 i915_update_gfx_val(dev_priv);
6013
652c393a
JB		 6014 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6015 /* Skip inactive CRTCs */
6016 if (!crtc->fb)
6017 continue;
6018
6019 intel_crtc = to_intel_crtc(crtc);
6020 if (!intel_crtc->busy)
6021 intel_decrease_pllclock(crtc);
6022 }
6023
45ac22c8 6024
652c393a
JB		 6025 mutex_unlock(&dev->struct_mutex);
6026}
6027
6028/**
6029 * intel_mark_busy - mark the GPU and possibly the display busy
6030 * @dev: drm device
6031 * @obj: object we're operating on
6032 *
6033 * Callers can use this function to indicate that the GPU is busy processing
6034 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
6035 * buffer), we'll also mark the display as busy, so we know to increase its
6036 * clock frequency.
6037 */
05394f39 6038void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 6039{
6040 drm_i915_private_t *dev_priv = dev->dev_private;
6041 struct drm_crtc *crtc = NULL;
6042 struct intel_framebuffer *intel_fb;
6043 struct intel_crtc *intel_crtc;
6044
5e17ee74
ZW		 6045 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6046 return;
6047
9104183d
CW		 6048 if (!dev_priv->busy) {
6049 intel_sanitize_pm(dev);
28cf798f 6050 dev_priv->busy = true;
9104183d 6051 } else
28cf798f
CW		 6052 mod_timer(&dev_priv->idle_timer, jiffies +
6053 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a 6054
acb87dfb
CW		 6055 if (obj == NULL)
6056 return;
6057
652c393a
JB		 6058 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6059 if (!crtc->fb)
6060 continue;
6061
6062 intel_crtc = to_intel_crtc(crtc);
6063 intel_fb = to_intel_framebuffer(crtc->fb);
6064 if (intel_fb->obj == obj) {
6065 if (!intel_crtc->busy) {
6066 /* Non-busy -> busy, upclock */
3dec0095 6067 intel_increase_pllclock(crtc);
652c393a
JB		 6068 intel_crtc->busy = true;
6069 } else {
6070 /* Busy -> busy, put off timer */
6071 mod_timer(&intel_crtc->idle_timer, jiffies +
6072 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6073 }
6074 }
6075 }
6076}
6077
79e53945
JB		 6078static void intel_crtc_destroy(struct drm_crtc *crtc)
6079{
6080 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6081 struct drm_device *dev = crtc->dev;
6082 struct intel_unpin_work *work;
6083 unsigned long flags;
6084
6085 spin_lock_irqsave(&dev->event_lock, flags);
6086 work = intel_crtc->unpin_work;
6087 intel_crtc->unpin_work = NULL;
6088 spin_unlock_irqrestore(&dev->event_lock, flags);
6089
6090 if (work) {
6091 cancel_work_sync(&work->work);
6092 kfree(work);
6093 }
79e53945
JB		 6094
6095 drm_crtc_cleanup(crtc);
67e77c5a 6096
79e53945
JB		 6097 kfree(intel_crtc);
6098}
6099
6b95a207
KH		 6100static void intel_unpin_work_fn(struct work_struct *__work)
6101{
6102 struct intel_unpin_work *work =
6103 container_of(__work, struct intel_unpin_work, work);
6104
6105 mutex_lock(&work->dev->struct_mutex);
1690e1eb 6106 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6107 drm_gem_object_unreference(&work->pending_flip_obj->base);
6108 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6109
7782de3b 6110 intel_update_fbc(work->dev);
6b95a207
KH		 6111 mutex_unlock(&work->dev->struct_mutex);
6112 kfree(work);
6113}
6114
1afe3e9d 6115static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6116 struct drm_crtc *crtc)
6b95a207
KH		 6117{
6118 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6119 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6120 struct intel_unpin_work *work;
05394f39 6121 struct drm_i915_gem_object *obj;
6b95a207 6122 struct drm_pending_vblank_event *e;
49b14a5c 6123 struct timeval tnow, tvbl;
6b95a207
KH		 6124 unsigned long flags;
6125
6126 /* Ignore early vblank irqs */
6127 if (intel_crtc == NULL)
6128 return;
6129
49b14a5c
MK		 6130 do_gettimeofday(&tnow);
6131
6b95a207
KH		 6132 spin_lock_irqsave(&dev->event_lock, flags);
6133 work = intel_crtc->unpin_work;
6134 if (work == NULL || !work->pending) {
6135 spin_unlock_irqrestore(&dev->event_lock, flags);
6136 return;
6137 }
6138
6139 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6140
6141 if (work->event) {
6142 e = work->event;
49b14a5c 6143 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6144
6145 /* Called before vblank count and timestamps have
6146 * been updated for the vblank interval of flip
6147 * completion? Need to increment vblank count and
6148 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6149 * to account for this. We assume this happened if we
6150 * get called over 0.9 frame durations after the last
6151 * timestamped vblank.
6152 *
6153 * This calculation can not be used with vrefresh rates
6154 * below 5Hz (10Hz to be on the safe side) without
6155 * promoting to 64 integers.
0af7e4df 6156 */
49b14a5c
MK		 6157 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6158 9 * crtc->framedur_ns) {
0af7e4df 6159 e->event.sequence++;
49b14a5c
MK		 6160 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6161 crtc->framedur_ns);
0af7e4df
MK		 6162 }
6163
49b14a5c
MK		 6164 e->event.tv_sec = tvbl.tv_sec;
6165 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6166
6b95a207
KH		 6167 list_add_tail(&e->base.link,
6168 &e->base.file_priv->event_list);
6169 wake_up_interruptible(&e->base.file_priv->event_wait);
6170 }
6171
0af7e4df
MK		 6172 drm_vblank_put(dev, intel_crtc->pipe);
6173
6b95a207
KH		 6174 spin_unlock_irqrestore(&dev->event_lock, flags);
6175
05394f39 6176 obj = work->old_fb_obj;
d9e86c0e 6177
e59f2bac 6178 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6179 &obj->pending_flip.counter);
6180 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6181 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6182
6b95a207 6183 schedule_work(&work->work);
e5510fac
JB		 6184
6185 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6186}
6187
1afe3e9d
JB		 6188void intel_finish_page_flip(struct drm_device *dev, int pipe)
6189{
6190 drm_i915_private_t *dev_priv = dev->dev_private;
6191 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6192
49b14a5c 6193 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6194}
6195
6196void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6197{
6198 drm_i915_private_t *dev_priv = dev->dev_private;
6199 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6200
49b14a5c 6201 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6202}
6203
6b95a207
KH		 6204void intel_prepare_page_flip(struct drm_device *dev, int plane)
6205{
6206 drm_i915_private_t *dev_priv = dev->dev_private;
6207 struct intel_crtc *intel_crtc =
6208 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6209 unsigned long flags;
6210
6211 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6212 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6213 if ((++intel_crtc->unpin_work->pending) > 1)
6214 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6215 } else {
6216 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6217 }
6b95a207
KH		 6218 spin_unlock_irqrestore(&dev->event_lock, flags);
6219}
6220
8c9f3aaf
JB		 6221static int intel_gen2_queue_flip(struct drm_device *dev,
6222 struct drm_crtc *crtc,
6223 struct drm_framebuffer *fb,
6224 struct drm_i915_gem_object *obj)
6225{
6226 struct drm_i915_private *dev_priv = dev->dev_private;
6227 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6228 u32 flip_mask;
6d90c952 6229 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6230 int ret;
6231
6d90c952 6232 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6233 if (ret)
83d4092b 6234 goto err;
8c9f3aaf 6235
6d90c952 6236 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6237 if (ret)
83d4092b 6238 goto err_unpin;
8c9f3aaf
JB		 6239
6240 /* Can't queue multiple flips, so wait for the previous
6241 * one to finish before executing the next.
6242 */
6243 if (intel_crtc->plane)
6244 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6245 else
6246 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6247 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6248 intel_ring_emit(ring, MI_NOOP);
6249 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6250 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6251 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6252 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6253 intel_ring_emit(ring, 0); /* aux display base address, unused */
6254 intel_ring_advance(ring);
83d4092b
CW		 6255 return 0;
6256
6257err_unpin:
6258 intel_unpin_fb_obj(obj);
6259err:
8c9f3aaf
JB		 6260 return ret;
6261}
6262
6263static int intel_gen3_queue_flip(struct drm_device *dev,
6264 struct drm_crtc *crtc,
6265 struct drm_framebuffer *fb,
6266 struct drm_i915_gem_object *obj)
6267{
6268 struct drm_i915_private *dev_priv = dev->dev_private;
6269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6270 u32 flip_mask;
6d90c952 6271 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6272 int ret;
6273
6d90c952 6274 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6275 if (ret)
83d4092b 6276 goto err;
8c9f3aaf 6277
6d90c952 6278 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6279 if (ret)
83d4092b 6280 goto err_unpin;
8c9f3aaf
JB		 6281
6282 if (intel_crtc->plane)
6283 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6284 else
6285 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6286 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6287 intel_ring_emit(ring, MI_NOOP);
6288 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6289 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6290 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6291 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6292 intel_ring_emit(ring, MI_NOOP);
6293
6294 intel_ring_advance(ring);
83d4092b
CW		 6295 return 0;
6296
6297err_unpin:
6298 intel_unpin_fb_obj(obj);
6299err:
8c9f3aaf
JB		 6300 return ret;
6301}
6302
6303static int intel_gen4_queue_flip(struct drm_device *dev,
6304 struct drm_crtc *crtc,
6305 struct drm_framebuffer *fb,
6306 struct drm_i915_gem_object *obj)
6307{
6308 struct drm_i915_private *dev_priv = dev->dev_private;
6309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6310 uint32_t pf, pipesrc;
6d90c952 6311 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6312 int ret;
6313
6d90c952 6314 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6315 if (ret)
83d4092b 6316 goto err;
8c9f3aaf 6317
6d90c952 6318 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6319 if (ret)
83d4092b 6320 goto err_unpin;
8c9f3aaf
JB		 6321
6322 /* i965+ uses the linear or tiled offsets from the
6323 * Display Registers (which do not change across a page-flip)
6324 * so we need only reprogram the base address.
6325 */
6d90c952
DV		 6326 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6327 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6328 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 6329 intel_ring_emit(ring,
6330 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6331 obj->tiling_mode);
8c9f3aaf
JB		 6332
6333 /* XXX Enabling the panel-fitter across page-flip is so far
6334 * untested on non-native modes, so ignore it for now.
6335 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6336 */
6337 pf = 0;
6338 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6339 intel_ring_emit(ring, pf | pipesrc);
6340 intel_ring_advance(ring);
83d4092b
CW		 6341 return 0;
6342
6343err_unpin:
6344 intel_unpin_fb_obj(obj);
6345err:
8c9f3aaf
JB		 6346 return ret;
6347}
6348
6349static int intel_gen6_queue_flip(struct drm_device *dev,
6350 struct drm_crtc *crtc,
6351 struct drm_framebuffer *fb,
6352 struct drm_i915_gem_object *obj)
6353{
6354 struct drm_i915_private *dev_priv = dev->dev_private;
6355 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 6356 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6357 uint32_t pf, pipesrc;
6358 int ret;
6359
6d90c952 6360 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6361 if (ret)
83d4092b 6362 goto err;
8c9f3aaf 6363
6d90c952 6364 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6365 if (ret)
83d4092b 6366 goto err_unpin;
8c9f3aaf 6367
6d90c952
DV		 6368 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6369 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6370 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 6371 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 6372
dc257cf1
DV		 6373 /* Contrary to the suggestions in the documentation,
6374 * "Enable Panel Fitter" does not seem to be required when page
6375 * flipping with a non-native mode, and worse causes a normal
6376 * modeset to fail.
6377 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6378 */
6379 pf = 0;
8c9f3aaf 6380 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6381 intel_ring_emit(ring, pf | pipesrc);
6382 intel_ring_advance(ring);
83d4092b
CW		 6383 return 0;
6384
6385err_unpin:
6386 intel_unpin_fb_obj(obj);
6387err:
8c9f3aaf
JB		 6388 return ret;
6389}
6390
7c9017e5
JB		 6391/*
6392 * On gen7 we currently use the blit ring because (in early silicon at least)
6393 * the render ring doesn't give us interrpts for page flip completion, which
6394 * means clients will hang after the first flip is queued. Fortunately the
6395 * blit ring generates interrupts properly, so use it instead.
6396 */
6397static int intel_gen7_queue_flip(struct drm_device *dev,
6398 struct drm_crtc *crtc,
6399 struct drm_framebuffer *fb,
6400 struct drm_i915_gem_object *obj)
6401{
6402 struct drm_i915_private *dev_priv = dev->dev_private;
6403 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6404 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 6405 uint32_t plane_bit = 0;
7c9017e5
JB		 6406 int ret;
6407
6408 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6409 if (ret)
83d4092b 6410 goto err;
7c9017e5 6411
cb05d8de
DV		 6412 switch(intel_crtc->plane) {
6413 case PLANE_A:
6414 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6415 break;
6416 case PLANE_B:
6417 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6418 break;
6419 case PLANE_C:
6420 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6421 break;
6422 default:
6423 WARN_ONCE(1, "unknown plane in flip command\n");
6424 ret = -ENODEV;
6425 goto err;
6426 }
6427
7c9017e5
JB		 6428 ret = intel_ring_begin(ring, 4);
6429 if (ret)
83d4092b 6430 goto err_unpin;
7c9017e5 6431
cb05d8de 6432 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 6433 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 6434 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 6435 intel_ring_emit(ring, (MI_NOOP));
6436 intel_ring_advance(ring);
83d4092b
CW		 6437 return 0;
6438
6439err_unpin:
6440 intel_unpin_fb_obj(obj);
6441err:
7c9017e5
JB		 6442 return ret;
6443}
6444
8c9f3aaf
JB		 6445static int intel_default_queue_flip(struct drm_device *dev,
6446 struct drm_crtc *crtc,
6447 struct drm_framebuffer *fb,
6448 struct drm_i915_gem_object *obj)
6449{
6450 return -ENODEV;
6451}
6452
6b95a207
KH		 6453static int intel_crtc_page_flip(struct drm_crtc *crtc,
6454 struct drm_framebuffer *fb,
6455 struct drm_pending_vblank_event *event)
6456{
6457 struct drm_device *dev = crtc->dev;
6458 struct drm_i915_private *dev_priv = dev->dev_private;
6459 struct intel_framebuffer *intel_fb;
05394f39 6460 struct drm_i915_gem_object *obj;
6b95a207
KH		 6461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6462 struct intel_unpin_work *work;
8c9f3aaf 6463 unsigned long flags;
52e68630 6464 int ret;
6b95a207 6465
e6a595d2
VS		 6466 /* Can't change pixel format via MI display flips. */
6467 if (fb->pixel_format != crtc->fb->pixel_format)
6468 return -EINVAL;
6469
6470 /*
6471 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6472 * Note that pitch changes could also affect these register.
6473 */
6474 if (INTEL_INFO(dev)->gen > 3 &&
6475 (fb->offsets[0] != crtc->fb->offsets[0] ||
6476 fb->pitches[0] != crtc->fb->pitches[0]))
6477 return -EINVAL;
6478
6b95a207
KH		 6479 work = kzalloc(sizeof *work, GFP_KERNEL);
6480 if (work == NULL)
6481 return -ENOMEM;
6482
6b95a207
KH		 6483 work->event = event;
6484 work->dev = crtc->dev;
6485 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6486 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6487 INIT_WORK(&work->work, intel_unpin_work_fn);
6488
7317c75e
JB		 6489 ret = drm_vblank_get(dev, intel_crtc->pipe);
6490 if (ret)
6491 goto free_work;
6492
6b95a207
KH		 6493 /* We borrow the event spin lock for protecting unpin_work */
6494 spin_lock_irqsave(&dev->event_lock, flags);
6495 if (intel_crtc->unpin_work) {
6496 spin_unlock_irqrestore(&dev->event_lock, flags);
6497 kfree(work);
7317c75e 6498 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 6499
6500 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6501 return -EBUSY;
6502 }
6503 intel_crtc->unpin_work = work;
6504 spin_unlock_irqrestore(&dev->event_lock, flags);
6505
6506 intel_fb = to_intel_framebuffer(fb);
6507 obj = intel_fb->obj;
6508
468f0b44 6509 mutex_lock(&dev->struct_mutex);
6b95a207 6510
75dfca80 6511 /* Reference the objects for the scheduled work. */
05394f39
CW		 6512 drm_gem_object_reference(&work->old_fb_obj->base);
6513 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6514
6515 crtc->fb = fb;
96b099fd 6516
e1f99ce6 6517 work->pending_flip_obj = obj;
e1f99ce6 6518
4e5359cd
SF		 6519 work->enable_stall_check = true;
6520
e1f99ce6
CW		 6521 /* Block clients from rendering to the new back buffer until
6522 * the flip occurs and the object is no longer visible.
6523 */
05394f39 6524 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6525
8c9f3aaf
JB		 6526 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6527 if (ret)
6528 goto cleanup_pending;
6b95a207 6529
7782de3b 6530 intel_disable_fbc(dev);
acb87dfb 6531 intel_mark_busy(dev, obj);
6b95a207
KH		 6532 mutex_unlock(&dev->struct_mutex);
6533
e5510fac
JB		 6534 trace_i915_flip_request(intel_crtc->plane, obj);
6535
6b95a207 6536 return 0;
96b099fd 6537
8c9f3aaf
JB		 6538cleanup_pending:
6539 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 6540 drm_gem_object_unreference(&work->old_fb_obj->base);
6541 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6542 mutex_unlock(&dev->struct_mutex);
6543
6544 spin_lock_irqsave(&dev->event_lock, flags);
6545 intel_crtc->unpin_work = NULL;
6546 spin_unlock_irqrestore(&dev->event_lock, flags);
6547
7317c75e
JB		 6548 drm_vblank_put(dev, intel_crtc->pipe);
6549free_work:
96b099fd
CW		 6550 kfree(work);
6551
6552 return ret;
6b95a207
KH		 6553}
6554
47f1c6c9
CW		 6555static void intel_sanitize_modesetting(struct drm_device *dev,
6556 int pipe, int plane)
6557{
6558 struct drm_i915_private *dev_priv = dev->dev_private;
6559 u32 reg, val;
a9dcf84b 6560 int i;
47f1c6c9 6561
f47166d2 6562 /* Clear any frame start delays used for debugging left by the BIOS */
a9dcf84b
DV		 6563 for_each_pipe(i) {
6564 reg = PIPECONF(i);
f47166d2
CW		 6565 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
6566 }
6567
47f1c6c9
CW		 6568 if (HAS_PCH_SPLIT(dev))
6569 return;
6570
6571 /* Who knows what state these registers were left in by the BIOS or
6572 * grub?
6573 *
6574 * If we leave the registers in a conflicting state (e.g. with the
6575 * display plane reading from the other pipe than the one we intend
6576 * to use) then when we attempt to teardown the active mode, we will
6577 * not disable the pipes and planes in the correct order -- leaving
6578 * a plane reading from a disabled pipe and possibly leading to
6579 * undefined behaviour.
6580 */
6581
6582 reg = DSPCNTR(plane);
6583 val = I915_READ(reg);
6584
6585 if ((val & DISPLAY_PLANE_ENABLE) == 0)
6586 return;
6587 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
6588 return;
6589
6590 /* This display plane is active and attached to the other CPU pipe. */
6591 pipe = !pipe;
6592
6593 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 6594 intel_disable_plane(dev_priv, plane, pipe);
6595 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 6596}
79e53945 6597
f6e5b160
CW		 6598static void intel_crtc_reset(struct drm_crtc *crtc)
6599{
6600 struct drm_device *dev = crtc->dev;
6601 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6602
6603 /* Reset flags back to the 'unknown' status so that they
6604 * will be correctly set on the initial modeset.
6605 */
6606 intel_crtc->dpms_mode = -1;
6607
6608 /* We need to fix up any BIOS configuration that conflicts with
6609 * our expectations.
6610 */
6611 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
6612}
6613
6614static struct drm_crtc_helper_funcs intel_helper_funcs = {
6615 .dpms = intel_crtc_dpms,
6616 .mode_fixup = intel_crtc_mode_fixup,
6617 .mode_set = intel_crtc_mode_set,
6618 .mode_set_base = intel_pipe_set_base,
6619 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6620 .load_lut = intel_crtc_load_lut,
6621 .disable = intel_crtc_disable,
6622};
6623
6624static const struct drm_crtc_funcs intel_crtc_funcs = {
6625 .reset = intel_crtc_reset,
6626 .cursor_set = intel_crtc_cursor_set,
6627 .cursor_move = intel_crtc_cursor_move,
6628 .gamma_set = intel_crtc_gamma_set,
6629 .set_config = drm_crtc_helper_set_config,
6630 .destroy = intel_crtc_destroy,
6631 .page_flip = intel_crtc_page_flip,
6632};
6633
ee7b9f93
JB		 6634static void intel_pch_pll_init(struct drm_device *dev)
6635{
6636 drm_i915_private_t *dev_priv = dev->dev_private;
6637 int i;
6638
6639 if (dev_priv->num_pch_pll == 0) {
6640 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
6641 return;
6642 }
6643
6644 for (i = 0; i < dev_priv->num_pch_pll; i++) {
6645 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
6646 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
6647 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
6648 }
6649}
6650
b358d0a6 6651static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 6652{
22fd0fab 6653 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 6654 struct intel_crtc *intel_crtc;
6655 int i;
6656
6657 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
6658 if (intel_crtc == NULL)
6659 return;
6660
6661 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
6662
6663 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 6664 for (i = 0; i < 256; i++) {
6665 intel_crtc->lut_r[i] = i;
6666 intel_crtc->lut_g[i] = i;
6667 intel_crtc->lut_b[i] = i;
6668 }
6669
80824003
JB		 6670 /* Swap pipes & planes for FBC on pre-965 */
6671 intel_crtc->pipe = pipe;
6672 intel_crtc->plane = pipe;
e2e767ab 6673 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 6674 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 6675 intel_crtc->plane = !pipe;
80824003
JB		 6676 }
6677
22fd0fab
JB		 6678 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
6679 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
6680 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
6681 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
6682
5d1d0cc8 6683 intel_crtc_reset(&intel_crtc->base);
04dbff52 6684 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 6685 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 6686
6687 if (HAS_PCH_SPLIT(dev)) {
6688 intel_helper_funcs.prepare = ironlake_crtc_prepare;
6689 intel_helper_funcs.commit = ironlake_crtc_commit;
6690 } else {
6691 intel_helper_funcs.prepare = i9xx_crtc_prepare;
6692 intel_helper_funcs.commit = i9xx_crtc_commit;
6693 }
6694
79e53945
JB		 6695 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
6696
652c393a
JB		 6697 intel_crtc->busy = false;
6698
6699 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
6700 (unsigned long)intel_crtc);
79e53945
JB		 6701}
6702
08d7b3d1 6703int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 6704 struct drm_file *file)
08d7b3d1 6705{
08d7b3d1 6706 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 6707 struct drm_mode_object *drmmode_obj;
6708 struct intel_crtc *crtc;
08d7b3d1 6709
1cff8f6b
DV		 6710 if (!drm_core_check_feature(dev, DRIVER_MODESET))
6711 return -ENODEV;
08d7b3d1 6712
c05422d5
DV		 6713 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
6714 DRM_MODE_OBJECT_CRTC);
08d7b3d1 6715
c05422d5 6716 if (!drmmode_obj) {
08d7b3d1
CW		 6717 DRM_ERROR("no such CRTC id\n");
6718 return -EINVAL;
6719 }
6720
c05422d5
DV		 6721 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
6722 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 6723
c05422d5 6724 return 0;
08d7b3d1
CW		 6725}
6726
c5e4df33 6727static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 6728{
4ef69c7a 6729 struct intel_encoder *encoder;
79e53945 6730 int index_mask = 0;
79e53945
JB		 6731 int entry = 0;
6732
4ef69c7a
CW		 6733 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6734 if (type_mask & encoder->clone_mask)
79e53945
JB		 6735 index_mask |= (1 << entry);
6736 entry++;
6737 }
4ef69c7a 6738
79e53945
JB		 6739 return index_mask;
6740}
6741
4d302442
CW		 6742static bool has_edp_a(struct drm_device *dev)
6743{
6744 struct drm_i915_private *dev_priv = dev->dev_private;
6745
6746 if (!IS_MOBILE(dev))
6747 return false;
6748
6749 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
6750 return false;
6751
6752 if (IS_GEN5(dev) &&
6753 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
6754 return false;
6755
6756 return true;
6757}
6758
79e53945
JB		 6759static void intel_setup_outputs(struct drm_device *dev)
6760{
725e30ad 6761 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 6762 struct intel_encoder *encoder;
cb0953d7 6763 bool dpd_is_edp = false;
f3cfcba6 6764 bool has_lvds;
79e53945 6765
f3cfcba6 6766 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 6767 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
6768 /* disable the panel fitter on everything but LVDS */
6769 I915_WRITE(PFIT_CONTROL, 0);
6770 }
79e53945 6771
bad720ff 6772 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 6773 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 6774
4d302442 6775 if (has_edp_a(dev))
32f9d658
ZW		 6776 intel_dp_init(dev, DP_A);
6777
cb0953d7
AJ		 6778 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
6779 intel_dp_init(dev, PCH_DP_D);
6780 }
6781
6782 intel_crt_init(dev);
6783
0e72a5b5
ED		 6784 if (IS_HASWELL(dev)) {
6785 int found;
6786
6787 /* Haswell uses DDI functions to detect digital outputs */
6788 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
6789 /* DDI A only supports eDP */
6790 if (found)
6791 intel_ddi_init(dev, PORT_A);
6792
6793 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
6794 * register */
6795 found = I915_READ(SFUSE_STRAP);
6796
6797 if (found & SFUSE_STRAP_DDIB_DETECTED)
6798 intel_ddi_init(dev, PORT_B);
6799 if (found & SFUSE_STRAP_DDIC_DETECTED)
6800 intel_ddi_init(dev, PORT_C);
6801 if (found & SFUSE_STRAP_DDID_DETECTED)
6802 intel_ddi_init(dev, PORT_D);
6803 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7
AJ		 6804 int found;
6805
30ad48b7 6806 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 6807 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 6808 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7
ZW		 6809 if (!found)
6810 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 6811 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
6812 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 6813 }
6814
6815 if (I915_READ(HDMIC) & PORT_DETECTED)
6816 intel_hdmi_init(dev, HDMIC);
6817
b708a1d5 6818 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
30ad48b7
ZW		 6819 intel_hdmi_init(dev, HDMID);
6820
5eb08b69
ZW		 6821 if (I915_READ(PCH_DP_C) & DP_DETECTED)
6822 intel_dp_init(dev, PCH_DP_C);
6823
cb0953d7 6824 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69 6825 intel_dp_init(dev, PCH_DP_D);
4a87d65d
JB		 6826 } else if (IS_VALLEYVIEW(dev)) {
6827 int found;
6828
6829 if (I915_READ(SDVOB) & PORT_DETECTED) {
6830 /* SDVOB multiplex with HDMIB */
6831 found = intel_sdvo_init(dev, SDVOB, true);
6832 if (!found)
6833 intel_hdmi_init(dev, SDVOB);
6834 if (!found && (I915_READ(DP_B) & DP_DETECTED))
6835 intel_dp_init(dev, DP_B);
6836 }
6837
6838 if (I915_READ(SDVOC) & PORT_DETECTED)
6839 intel_hdmi_init(dev, SDVOC);
5eb08b69 6840
4a87d65d
JB		 6841 /* Shares lanes with HDMI on SDVOC */
6842 if (I915_READ(DP_C) & DP_DETECTED)
6843 intel_dp_init(dev, DP_C);
103a196f 6844 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 6845 bool found = false;
7d57382e 6846
725e30ad 6847 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 6848 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 6849 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 6850 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
6851 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 6852 intel_hdmi_init(dev, SDVOB);
b01f2c3a 6853 }
27185ae1 6854
b01f2c3a
JB		 6855 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
6856 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 6857 intel_dp_init(dev, DP_B);
b01f2c3a 6858 }
725e30ad 6859 }
13520b05
KH		 6860
6861 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 6862
b01f2c3a
JB		 6863 if (I915_READ(SDVOB) & SDVO_DETECTED) {
6864 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 6865 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 6866 }
27185ae1
ML		 6867
6868 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
6869
b01f2c3a
JB		 6870 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
6871 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 6872 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 6873 }
6874 if (SUPPORTS_INTEGRATED_DP(dev)) {
6875 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 6876 intel_dp_init(dev, DP_C);
b01f2c3a 6877 }
725e30ad 6878 }
27185ae1 6879
b01f2c3a
JB		 6880 if (SUPPORTS_INTEGRATED_DP(dev) &&
6881 (I915_READ(DP_D) & DP_DETECTED)) {
6882 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 6883 intel_dp_init(dev, DP_D);
b01f2c3a 6884 }
bad720ff 6885 } else if (IS_GEN2(dev))
79e53945
JB		 6886 intel_dvo_init(dev);
6887
103a196f 6888 if (SUPPORTS_TV(dev))
79e53945
JB		 6889 intel_tv_init(dev);
6890
4ef69c7a
CW		 6891 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6892 encoder->base.possible_crtcs = encoder->crtc_mask;
6893 encoder->base.possible_clones =
6894 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 6895 }
47356eb6 6896
2c7111db
CW		 6897 /* disable all the possible outputs/crtcs before entering KMS mode */
6898 drm_helper_disable_unused_functions(dev);
9fb526db 6899
40579abe 6900 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 6901 ironlake_init_pch_refclk(dev);
79e53945
JB		 6902}
6903
6904static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
6905{
6906 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 6907
6908 drm_framebuffer_cleanup(fb);
05394f39 6909 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 6910
6911 kfree(intel_fb);
6912}
6913
6914static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 6915 struct drm_file *file,
79e53945
JB		 6916 unsigned int *handle)
6917{
6918 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 6919 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 6920
05394f39 6921 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 6922}
6923
6924static const struct drm_framebuffer_funcs intel_fb_funcs = {
6925 .destroy = intel_user_framebuffer_destroy,
6926 .create_handle = intel_user_framebuffer_create_handle,
6927};
6928
38651674
DA		 6929int intel_framebuffer_init(struct drm_device *dev,
6930 struct intel_framebuffer *intel_fb,
308e5bcb 6931 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 6932 struct drm_i915_gem_object *obj)
79e53945 6933{
79e53945
JB		 6934 int ret;
6935
05394f39 6936 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 6937 return -EINVAL;
6938
308e5bcb 6939 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 6940 return -EINVAL;
6941
308e5bcb 6942 switch (mode_cmd->pixel_format) {
04b3924d
VS		 6943 case DRM_FORMAT_RGB332:
6944 case DRM_FORMAT_RGB565:
6945 case DRM_FORMAT_XRGB8888:
b250da79 6946 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 6947 case DRM_FORMAT_ARGB8888:
6948 case DRM_FORMAT_XRGB2101010:
6949 case DRM_FORMAT_ARGB2101010:
308e5bcb 6950 /* RGB formats are common across chipsets */
b5626747 6951 break;
04b3924d
VS		 6952 case DRM_FORMAT_YUYV:
6953 case DRM_FORMAT_UYVY:
6954 case DRM_FORMAT_YVYU:
6955 case DRM_FORMAT_VYUY:
57cd6508
CW		 6956 break;
6957 default:
aca25848
ED		 6958 DRM_DEBUG_KMS("unsupported pixel format %u\n",
6959 mode_cmd->pixel_format);
57cd6508
CW		 6960 return -EINVAL;
6961 }
6962
79e53945
JB		 6963 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
6964 if (ret) {
6965 DRM_ERROR("framebuffer init failed %d\n", ret);
6966 return ret;
6967 }
6968
6969 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 6970 intel_fb->obj = obj;
79e53945
JB		 6971 return 0;
6972}
6973
79e53945
JB		 6974static struct drm_framebuffer *
6975intel_user_framebuffer_create(struct drm_device *dev,
6976 struct drm_file *filp,
308e5bcb 6977 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 6978{
05394f39 6979 struct drm_i915_gem_object *obj;
79e53945 6980
308e5bcb
JB		 6981 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
6982 mode_cmd->handles[0]));
c8725226 6983 if (&obj->base == NULL)
cce13ff7 6984 return ERR_PTR(-ENOENT);
79e53945 6985
d2dff872 6986 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 6987}
6988
79e53945 6989static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 6990 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 6991 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 6992};
6993
e70236a8
JB		 6994/* Set up chip specific display functions */
6995static void intel_init_display(struct drm_device *dev)
6996{
6997 struct drm_i915_private *dev_priv = dev->dev_private;
6998
6999 /* We always want a DPMS function */
f564048e 7000 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 7001 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 7002 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
ee7b9f93 7003 dev_priv->display.off = ironlake_crtc_off;
17638cd6 7004 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 7005 } else {
e70236a8 7006 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 7007 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
ee7b9f93 7008 dev_priv->display.off = i9xx_crtc_off;
17638cd6 7009 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 7010 }
e70236a8 7011
e70236a8 7012 /* Returns the core display clock speed */
25eb05fc
JB		 7013 if (IS_VALLEYVIEW(dev))
7014 dev_priv->display.get_display_clock_speed =
7015 valleyview_get_display_clock_speed;
7016 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 7017 dev_priv->display.get_display_clock_speed =
7018 i945_get_display_clock_speed;
7019 else if (IS_I915G(dev))
7020 dev_priv->display.get_display_clock_speed =
7021 i915_get_display_clock_speed;
f2b115e6 7022 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 7023 dev_priv->display.get_display_clock_speed =
7024 i9xx_misc_get_display_clock_speed;
7025 else if (IS_I915GM(dev))
7026 dev_priv->display.get_display_clock_speed =
7027 i915gm_get_display_clock_speed;
7028 else if (IS_I865G(dev))
7029 dev_priv->display.get_display_clock_speed =
7030 i865_get_display_clock_speed;
f0f8a9ce 7031 else if (IS_I85X(dev))
e70236a8
JB		 7032 dev_priv->display.get_display_clock_speed =
7033 i855_get_display_clock_speed;
7034 else /* 852, 830 */
7035 dev_priv->display.get_display_clock_speed =
7036 i830_get_display_clock_speed;
7037
7f8a8569 7038 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 7039 if (IS_GEN5(dev)) {
674cf967 7040 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 7041 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 7042 } else if (IS_GEN6(dev)) {
674cf967 7043 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 7044 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 7045 } else if (IS_IVYBRIDGE(dev)) {
7046 /* FIXME: detect B0+ stepping and use auto training */
7047 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 7048 dev_priv->display.write_eld = ironlake_write_eld;
c82e4d26
ED		 7049 } else if (IS_HASWELL(dev)) {
7050 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
4abb3c8c 7051 dev_priv->display.write_eld = ironlake_write_eld;
7f8a8569
ZW		 7052 } else
7053 dev_priv->display.update_wm = NULL;
6067aaea 7054 } else if (IS_G4X(dev)) {
e0dac65e 7055 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 7056 }
8c9f3aaf
JB		 7057
7058 /* Default just returns -ENODEV to indicate unsupported */
7059 dev_priv->display.queue_flip = intel_default_queue_flip;
7060
7061 switch (INTEL_INFO(dev)->gen) {
7062 case 2:
7063 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7064 break;
7065
7066 case 3:
7067 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7068 break;
7069
7070 case 4:
7071 case 5:
7072 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7073 break;
7074
7075 case 6:
7076 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7077 break;
7c9017e5
JB		 7078 case 7:
7079 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7080 break;
8c9f3aaf 7081 }
e70236a8
JB		 7082}
7083
b690e96c
JB		 7084/*
7085 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7086 * resume, or other times. This quirk makes sure that's the case for
7087 * affected systems.
7088 */
0206e353 7089static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 7090{
7091 struct drm_i915_private *dev_priv = dev->dev_private;
7092
7093 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 7094 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 7095}
7096
435793df
KP		 7097/*
7098 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7099 */
7100static void quirk_ssc_force_disable(struct drm_device *dev)
7101{
7102 struct drm_i915_private *dev_priv = dev->dev_private;
7103 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 7104 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 7105}
7106
4dca20ef 7107/*
5a15ab5b
CE		 7108 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7109 * brightness value
4dca20ef
CE		 7110 */
7111static void quirk_invert_brightness(struct drm_device *dev)
7112{
7113 struct drm_i915_private *dev_priv = dev->dev_private;
7114 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 7115 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 7116}
7117
b690e96c
JB		 7118struct intel_quirk {
7119 int device;
7120 int subsystem_vendor;
7121 int subsystem_device;
7122 void (*hook)(struct drm_device *dev);
7123};
7124
c43b5634 7125static struct intel_quirk intel_quirks[] = {
b690e96c 7126 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 7127 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c
JB		 7128
7129 /* Thinkpad R31 needs pipe A force quirk */
7130 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
7131 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7132 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7133
7134 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
7135 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
7136 /* ThinkPad X40 needs pipe A force quirk */
7137
7138 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7139 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7140
7141 /* 855 & before need to leave pipe A & dpll A up */
7142 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7143 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 7144
7145 /* Lenovo U160 cannot use SSC on LVDS */
7146 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 7147
7148 /* Sony Vaio Y cannot use SSC on LVDS */
7149 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 7150
7151 /* Acer Aspire 5734Z must invert backlight brightness */
7152 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 7153};
7154
7155static void intel_init_quirks(struct drm_device *dev)
7156{
7157 struct pci_dev *d = dev->pdev;
7158 int i;
7159
7160 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7161 struct intel_quirk *q = &intel_quirks[i];
7162
7163 if (d->device == q->device &&
7164 (d->subsystem_vendor == q->subsystem_vendor ||
7165 q->subsystem_vendor == PCI_ANY_ID) &&
7166 (d->subsystem_device == q->subsystem_device ||
7167 q->subsystem_device == PCI_ANY_ID))
7168 q->hook(dev);
7169 }
7170}
7171
9cce37f4
JB		 7172/* Disable the VGA plane that we never use */
7173static void i915_disable_vga(struct drm_device *dev)
7174{
7175 struct drm_i915_private *dev_priv = dev->dev_private;
7176 u8 sr1;
7177 u32 vga_reg;
7178
7179 if (HAS_PCH_SPLIT(dev))
7180 vga_reg = CPU_VGACNTRL;
7181 else
7182 vga_reg = VGACNTRL;
7183
7184 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 7185 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 7186 sr1 = inb(VGA_SR_DATA);
7187 outb(sr1 | 1<<5, VGA_SR_DATA);
7188 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7189 udelay(300);
7190
7191 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7192 POSTING_READ(vga_reg);
7193}
7194
f82cfb6b
JB		 7195static void ivb_pch_pwm_override(struct drm_device *dev)
7196{
7197 struct drm_i915_private *dev_priv = dev->dev_private;
7198
7199 /*
7200 * IVB has CPU eDP backlight regs too, set things up to let the
7201 * PCH regs control the backlight
7202 */
7cf41601 7203 I915_WRITE(BLC_PWM_CPU_CTL2, BLM_PWM_ENABLE);
f82cfb6b 7204 I915_WRITE(BLC_PWM_CPU_CTL, 0);
7cf41601 7205 I915_WRITE(BLC_PWM_PCH_CTL1, BLM_PCH_PWM_ENABLE | BLM_PCH_OVERRIDE_ENABLE);
f82cfb6b
JB		 7206}
7207
f817586c
DV		 7208void intel_modeset_init_hw(struct drm_device *dev)
7209{
a8f78b58
ED		 7210 intel_prepare_ddi(dev);
7211
f817586c
DV		 7212 intel_init_clock_gating(dev);
7213
79f5b2c7 7214 mutex_lock(&dev->struct_mutex);
8090c6b9 7215 intel_enable_gt_powersave(dev);
79f5b2c7 7216 mutex_unlock(&dev->struct_mutex);
f82cfb6b
JB		 7217
7218 if (IS_IVYBRIDGE(dev))
7219 ivb_pch_pwm_override(dev);
f817586c
DV		 7220}
7221
79e53945
JB		 7222void intel_modeset_init(struct drm_device *dev)
7223{
652c393a 7224 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 7225 int i, ret;
79e53945
JB		 7226
7227 drm_mode_config_init(dev);
7228
7229 dev->mode_config.min_width = 0;
7230 dev->mode_config.min_height = 0;
7231
019d96cb
DA		 7232 dev->mode_config.preferred_depth = 24;
7233 dev->mode_config.prefer_shadow = 1;
7234
e6ecefaa 7235 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 7236
b690e96c
JB		 7237 intel_init_quirks(dev);
7238
1fa61106
ED		 7239 intel_init_pm(dev);
7240
e70236a8
JB		 7241 intel_init_display(dev);
7242
a6c45cf0
CW		 7243 if (IS_GEN2(dev)) {
7244 dev->mode_config.max_width = 2048;
7245 dev->mode_config.max_height = 2048;
7246 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 7247 dev->mode_config.max_width = 4096;
7248 dev->mode_config.max_height = 4096;
79e53945 7249 } else {
a6c45cf0
CW		 7250 dev->mode_config.max_width = 8192;
7251 dev->mode_config.max_height = 8192;
79e53945 7252 }
dd2757f8 7253 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 7254
28c97730 7255 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 7256 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 7257
a3524f1b 7258 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 7259 intel_crtc_init(dev, i);
00c2064b
JB		 7260 ret = intel_plane_init(dev, i);
7261 if (ret)
7262 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 7263 }
7264
ee7b9f93
JB		 7265 intel_pch_pll_init(dev);
7266
9cce37f4
JB		 7267 /* Just disable it once at startup */
7268 i915_disable_vga(dev);
79e53945 7269 intel_setup_outputs(dev);
652c393a 7270
652c393a
JB		 7271 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
7272 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
7273 (unsigned long)dev);
2c7111db
CW		 7274}
7275
7276void intel_modeset_gem_init(struct drm_device *dev)
7277{
1833b134 7278 intel_modeset_init_hw(dev);
02e792fb
DV		 7279
7280 intel_setup_overlay(dev);
79e53945
JB		 7281}
7282
7283void intel_modeset_cleanup(struct drm_device *dev)
7284{
652c393a
JB		 7285 struct drm_i915_private *dev_priv = dev->dev_private;
7286 struct drm_crtc *crtc;
7287 struct intel_crtc *intel_crtc;
7288
f87ea761 7289 drm_kms_helper_poll_fini(dev);
652c393a
JB		 7290 mutex_lock(&dev->struct_mutex);
7291
723bfd70
JB		 7292 intel_unregister_dsm_handler();
7293
7294
652c393a
JB		 7295 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7296 /* Skip inactive CRTCs */
7297 if (!crtc->fb)
7298 continue;
7299
7300 intel_crtc = to_intel_crtc(crtc);
3dec0095 7301 intel_increase_pllclock(crtc);
652c393a
JB		 7302 }
7303
973d04f9 7304 intel_disable_fbc(dev);
e70236a8 7305
8090c6b9 7306 intel_disable_gt_powersave(dev);
0cdab21f 7307
930ebb46
DV		 7308 ironlake_teardown_rc6(dev);
7309
57f350b6
JB		 7310 if (IS_VALLEYVIEW(dev))
7311 vlv_init_dpio(dev);
7312
69341a5e
KH		 7313 mutex_unlock(&dev->struct_mutex);
7314
6c0d9350
DV		 7315 /* Disable the irq before mode object teardown, for the irq might
7316 * enqueue unpin/hotplug work. */
7317 drm_irq_uninstall(dev);
7318 cancel_work_sync(&dev_priv->hotplug_work);
6fdd4d98 7319 cancel_work_sync(&dev_priv->rps_work);
6c0d9350 7320
1630fe75
CW		 7321 /* flush any delayed tasks or pending work */
7322 flush_scheduled_work();
7323
3dec0095
DV		 7324 /* Shut off idle work before the crtcs get freed. */
7325 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7326 intel_crtc = to_intel_crtc(crtc);
7327 del_timer_sync(&intel_crtc->idle_timer);
7328 }
7329 del_timer_sync(&dev_priv->idle_timer);
7330 cancel_work_sync(&dev_priv->idle_work);
7331
79e53945
JB		 7332 drm_mode_config_cleanup(dev);
7333}
7334
f1c79df3
ZW		 7335/*
7336 * Return which encoder is currently attached for connector.
7337 */
df0e9248 7338struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 7339{
df0e9248
CW		 7340 return &intel_attached_encoder(connector)->base;
7341}
f1c79df3 7342
df0e9248
CW		 7343void intel_connector_attach_encoder(struct intel_connector *connector,
7344 struct intel_encoder *encoder)
7345{
7346 connector->encoder = encoder;
7347 drm_mode_connector_attach_encoder(&connector->base,
7348 &encoder->base);
79e53945 7349}
28d52043
DA		 7350
7351/*
7352 * set vga decode state - true == enable VGA decode
7353 */
7354int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
7355{
7356 struct drm_i915_private *dev_priv = dev->dev_private;
7357 u16 gmch_ctrl;
7358
7359 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
7360 if (state)
7361 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
7362 else
7363 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
7364 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
7365 return 0;
7366}
c4a1d9e4
CW		 7367
7368#ifdef CONFIG_DEBUG_FS
7369#include <linux/seq_file.h>
7370
7371struct intel_display_error_state {
7372 struct intel_cursor_error_state {
7373 u32 control;
7374 u32 position;
7375 u32 base;
7376 u32 size;
7377 } cursor[2];
7378
7379 struct intel_pipe_error_state {
7380 u32 conf;
7381 u32 source;
7382
7383 u32 htotal;
7384 u32 hblank;
7385 u32 hsync;
7386 u32 vtotal;
7387 u32 vblank;
7388 u32 vsync;
7389 } pipe[2];
7390
7391 struct intel_plane_error_state {
7392 u32 control;
7393 u32 stride;
7394 u32 size;
7395 u32 pos;
7396 u32 addr;
7397 u32 surface;
7398 u32 tile_offset;
7399 } plane[2];
7400};
7401
7402struct intel_display_error_state *
7403intel_display_capture_error_state(struct drm_device *dev)
7404{
0206e353 7405 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 7406 struct intel_display_error_state *error;
7407 int i;
7408
7409 error = kmalloc(sizeof(*error), GFP_ATOMIC);
7410 if (error == NULL)
7411 return NULL;
7412
7413 for (i = 0; i < 2; i++) {
7414 error->cursor[i].control = I915_READ(CURCNTR(i));
7415 error->cursor[i].position = I915_READ(CURPOS(i));
7416 error->cursor[i].base = I915_READ(CURBASE(i));
7417
7418 error->plane[i].control = I915_READ(DSPCNTR(i));
7419 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
7420 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 7421 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 7422 error->plane[i].addr = I915_READ(DSPADDR(i));
7423 if (INTEL_INFO(dev)->gen >= 4) {
7424 error->plane[i].surface = I915_READ(DSPSURF(i));
7425 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
7426 }
7427
7428 error->pipe[i].conf = I915_READ(PIPECONF(i));
7429 error->pipe[i].source = I915_READ(PIPESRC(i));
7430 error->pipe[i].htotal = I915_READ(HTOTAL(i));
7431 error->pipe[i].hblank = I915_READ(HBLANK(i));
7432 error->pipe[i].hsync = I915_READ(HSYNC(i));
7433 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
7434 error->pipe[i].vblank = I915_READ(VBLANK(i));
7435 error->pipe[i].vsync = I915_READ(VSYNC(i));
7436 }
7437
7438 return error;
7439}
7440
7441void
7442intel_display_print_error_state(struct seq_file *m,
7443 struct drm_device *dev,
7444 struct intel_display_error_state *error)
7445{
7446 int i;
7447
7448 for (i = 0; i < 2; i++) {
7449 seq_printf(m, "Pipe [%d]:\n", i);
7450 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
7451 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
7452 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
7453 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
7454 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
7455 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
7456 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
7457 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
7458
7459 seq_printf(m, "Plane [%d]:\n", i);
7460 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
7461 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
7462 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
7463 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
7464 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
7465 if (INTEL_INFO(dev)->gen >= 4) {
7466 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
7467 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
7468 }
7469
7470 seq_printf(m, "Cursor [%d]:\n", i);
7471 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
7472 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
7473 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
7474 }
7475}
7476#endif
Linux kernel - Deliverables
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