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drm/i915: Removing the drrs capability enum initialization
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
319c1d42 40#include <drm/drm_atomic.h>
c196e1d6 41#include <drm/drm_atomic_helper.h>
760285e7
DH		 42#include <drm/drm_dp_helper.h>
43#include <drm/drm_crtc_helper.h>
465c120c
MR		 44#include <drm/drm_plane_helper.h>
45#include <drm/drm_rect.h>
c0f372b3 46#include <linux/dma_remapping.h>
79e53945 47
465c120c
MR		 48/* Primary plane formats supported by all gen */
49#define COMMON_PRIMARY_FORMATS \
50 DRM_FORMAT_C8, \
51 DRM_FORMAT_RGB565, \
52 DRM_FORMAT_XRGB8888, \
53 DRM_FORMAT_ARGB8888
54
55/* Primary plane formats for gen <= 3 */
56static const uint32_t intel_primary_formats_gen2[] = {
57 COMMON_PRIMARY_FORMATS,
58 DRM_FORMAT_XRGB1555,
59 DRM_FORMAT_ARGB1555,
60};
61
62/* Primary plane formats for gen >= 4 */
63static const uint32_t intel_primary_formats_gen4[] = {
64 COMMON_PRIMARY_FORMATS, \
65 DRM_FORMAT_XBGR8888,
66 DRM_FORMAT_ABGR8888,
67 DRM_FORMAT_XRGB2101010,
68 DRM_FORMAT_ARGB2101010,
69 DRM_FORMAT_XBGR2101010,
70 DRM_FORMAT_ABGR2101010,
71};
72
3d7d6510
MR		 73/* Cursor formats */
74static const uint32_t intel_cursor_formats[] = {
75 DRM_FORMAT_ARGB8888,
76};
77
6b383a7f 78static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 79
f1f644dc 80static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 81 struct intel_crtc_state *pipe_config);
18442d08 82static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 83 struct intel_crtc_state *pipe_config);
f1f644dc 84
e7457a9a
DL		 85static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
86 int x, int y, struct drm_framebuffer *old_fb);
eb1bfe80
JB		 87static int intel_framebuffer_init(struct drm_device *dev,
88 struct intel_framebuffer *ifb,
89 struct drm_mode_fb_cmd2 *mode_cmd,
90 struct drm_i915_gem_object *obj);
5b18e57c
DV		 91static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc);
92static void intel_set_pipe_timings(struct intel_crtc *intel_crtc);
29407aab 93static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 94 struct intel_link_m_n *m_n,
95 struct intel_link_m_n *m2_n2);
29407aab 96static void ironlake_set_pipeconf(struct drm_crtc *crtc);
229fca97
DV		 97static void haswell_set_pipeconf(struct drm_crtc *crtc);
98static void intel_set_pipe_csc(struct drm_crtc *crtc);
d288f65f 99static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 100 const struct intel_crtc_state *pipe_config);
d288f65f 101static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 102 const struct intel_crtc_state *pipe_config);
ea2c67bb
MR		 103static void intel_begin_crtc_commit(struct drm_crtc *crtc);
104static void intel_finish_crtc_commit(struct drm_crtc *crtc);
e7457a9a 105
0e32b39c
DA		 106static struct intel_encoder *intel_find_encoder(struct intel_connector *connector, int pipe)
107{
108 if (!connector->mst_port)
109 return connector->encoder;
110 else
111 return &connector->mst_port->mst_encoders[pipe]->base;
112}
113
79e53945 114typedef struct {
0206e353 115 int min, max;
79e53945
JB		 116} intel_range_t;
117
118typedef struct {
0206e353
AJ		 119 int dot_limit;
120 int p2_slow, p2_fast;
79e53945
JB		 121} intel_p2_t;
122
d4906093
ML		 123typedef struct intel_limit intel_limit_t;
124struct intel_limit {
0206e353
AJ		 125 intel_range_t dot, vco, n, m, m1, m2, p, p1;
126 intel_p2_t p2;
d4906093 127};
79e53945 128
d2acd215
DV		 129int
130intel_pch_rawclk(struct drm_device *dev)
131{
132 struct drm_i915_private *dev_priv = dev->dev_private;
133
134 WARN_ON(!HAS_PCH_SPLIT(dev));
135
136 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
137}
138
021357ac
CW		 139static inline u32 /* units of 100MHz */
140intel_fdi_link_freq(struct drm_device *dev)
141{
8b99e68c
CW		 142 if (IS_GEN5(dev)) {
143 struct drm_i915_private *dev_priv = dev->dev_private;
144 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
145 } else
146 return 27;
021357ac
CW		 147}
148
5d536e28 149static const intel_limit_t intel_limits_i8xx_dac = {
0206e353 150 .dot = { .min = 25000, .max = 350000 },
9c333719 151 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 152 .n = { .min = 2, .max = 16 },
0206e353
AJ		 153 .m = { .min = 96, .max = 140 },
154 .m1 = { .min = 18, .max = 26 },
155 .m2 = { .min = 6, .max = 16 },
156 .p = { .min = 4, .max = 128 },
157 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 158 .p2 = { .dot_limit = 165000,
159 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 160};
161
5d536e28
DV		 162static const intel_limit_t intel_limits_i8xx_dvo = {
163 .dot = { .min = 25000, .max = 350000 },
9c333719 164 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 165 .n = { .min = 2, .max = 16 },
5d536e28
DV		 166 .m = { .min = 96, .max = 140 },
167 .m1 = { .min = 18, .max = 26 },
168 .m2 = { .min = 6, .max = 16 },
169 .p = { .min = 4, .max = 128 },
170 .p1 = { .min = 2, .max = 33 },
171 .p2 = { .dot_limit = 165000,
172 .p2_slow = 4, .p2_fast = 4 },
173};
174
e4b36699 175static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353 176 .dot = { .min = 25000, .max = 350000 },
9c333719 177 .vco = { .min = 908000, .max = 1512000 },
91dbe5fb 178 .n = { .min = 2, .max = 16 },
0206e353
AJ		 179 .m = { .min = 96, .max = 140 },
180 .m1 = { .min = 18, .max = 26 },
181 .m2 = { .min = 6, .max = 16 },
182 .p = { .min = 4, .max = 128 },
183 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 184 .p2 = { .dot_limit = 165000,
185 .p2_slow = 14, .p2_fast = 7 },
e4b36699 186};
273e27ca 187
e4b36699 188static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 189 .dot = { .min = 20000, .max = 400000 },
190 .vco = { .min = 1400000, .max = 2800000 },
191 .n = { .min = 1, .max = 6 },
192 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 193 .m1 = { .min = 8, .max = 18 },
194 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 195 .p = { .min = 5, .max = 80 },
196 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 197 .p2 = { .dot_limit = 200000,
198 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 199};
200
201static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 202 .dot = { .min = 20000, .max = 400000 },
203 .vco = { .min = 1400000, .max = 2800000 },
204 .n = { .min = 1, .max = 6 },
205 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 206 .m1 = { .min = 8, .max = 18 },
207 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 208 .p = { .min = 7, .max = 98 },
209 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 210 .p2 = { .dot_limit = 112000,
211 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 212};
213
273e27ca 214
e4b36699 215static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 216 .dot = { .min = 25000, .max = 270000 },
217 .vco = { .min = 1750000, .max = 3500000},
218 .n = { .min = 1, .max = 4 },
219 .m = { .min = 104, .max = 138 },
220 .m1 = { .min = 17, .max = 23 },
221 .m2 = { .min = 5, .max = 11 },
222 .p = { .min = 10, .max = 30 },
223 .p1 = { .min = 1, .max = 3},
224 .p2 = { .dot_limit = 270000,
225 .p2_slow = 10,
226 .p2_fast = 10
044c7c41 227 },
e4b36699
KP		 228};
229
230static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 231 .dot = { .min = 22000, .max = 400000 },
232 .vco = { .min = 1750000, .max = 3500000},
233 .n = { .min = 1, .max = 4 },
234 .m = { .min = 104, .max = 138 },
235 .m1 = { .min = 16, .max = 23 },
236 .m2 = { .min = 5, .max = 11 },
237 .p = { .min = 5, .max = 80 },
238 .p1 = { .min = 1, .max = 8},
239 .p2 = { .dot_limit = 165000,
240 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 241};
242
243static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 244 .dot = { .min = 20000, .max = 115000 },
245 .vco = { .min = 1750000, .max = 3500000 },
246 .n = { .min = 1, .max = 3 },
247 .m = { .min = 104, .max = 138 },
248 .m1 = { .min = 17, .max = 23 },
249 .m2 = { .min = 5, .max = 11 },
250 .p = { .min = 28, .max = 112 },
251 .p1 = { .min = 2, .max = 8 },
252 .p2 = { .dot_limit = 0,
253 .p2_slow = 14, .p2_fast = 14
044c7c41 254 },
e4b36699
KP		 255};
256
257static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 258 .dot = { .min = 80000, .max = 224000 },
259 .vco = { .min = 1750000, .max = 3500000 },
260 .n = { .min = 1, .max = 3 },
261 .m = { .min = 104, .max = 138 },
262 .m1 = { .min = 17, .max = 23 },
263 .m2 = { .min = 5, .max = 11 },
264 .p = { .min = 14, .max = 42 },
265 .p1 = { .min = 2, .max = 6 },
266 .p2 = { .dot_limit = 0,
267 .p2_slow = 7, .p2_fast = 7
044c7c41 268 },
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000},
273 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 274 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 275 .n = { .min = 3, .max = 6 },
276 .m = { .min = 2, .max = 256 },
273e27ca 277 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 278 .m1 = { .min = 0, .max = 0 },
279 .m2 = { .min = 0, .max = 254 },
280 .p = { .min = 5, .max = 80 },
281 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 282 .p2 = { .dot_limit = 200000,
283 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 284};
285
f2b115e6 286static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 287 .dot = { .min = 20000, .max = 400000 },
288 .vco = { .min = 1700000, .max = 3500000 },
289 .n = { .min = 3, .max = 6 },
290 .m = { .min = 2, .max = 256 },
291 .m1 = { .min = 0, .max = 0 },
292 .m2 = { .min = 0, .max = 254 },
293 .p = { .min = 7, .max = 112 },
294 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 295 .p2 = { .dot_limit = 112000,
296 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 297};
298
273e27ca
EA		 299/* Ironlake / Sandybridge
300 *
301 * We calculate clock using (register_value + 2) for N/M1/M2, so here
302 * the range value for them is (actual_value - 2).
303 */
b91ad0ec 304static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 5 },
308 .m = { .min = 79, .max = 127 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 5, .max = 80 },
312 .p1 = { .min = 1, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 315};
316
b91ad0ec 317static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 318 .dot = { .min = 25000, .max = 350000 },
319 .vco = { .min = 1760000, .max = 3510000 },
320 .n = { .min = 1, .max = 3 },
321 .m = { .min = 79, .max = 118 },
322 .m1 = { .min = 12, .max = 22 },
323 .m2 = { .min = 5, .max = 9 },
324 .p = { .min = 28, .max = 112 },
325 .p1 = { .min = 2, .max = 8 },
326 .p2 = { .dot_limit = 225000,
327 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 328};
329
330static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 331 .dot = { .min = 25000, .max = 350000 },
332 .vco = { .min = 1760000, .max = 3510000 },
333 .n = { .min = 1, .max = 3 },
334 .m = { .min = 79, .max = 127 },
335 .m1 = { .min = 12, .max = 22 },
336 .m2 = { .min = 5, .max = 9 },
337 .p = { .min = 14, .max = 56 },
338 .p1 = { .min = 2, .max = 8 },
339 .p2 = { .dot_limit = 225000,
340 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 341};
342
273e27ca 343/* LVDS 100mhz refclk limits. */
b91ad0ec 344static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 345 .dot = { .min = 25000, .max = 350000 },
346 .vco = { .min = 1760000, .max = 3510000 },
347 .n = { .min = 1, .max = 2 },
348 .m = { .min = 79, .max = 126 },
349 .m1 = { .min = 12, .max = 22 },
350 .m2 = { .min = 5, .max = 9 },
351 .p = { .min = 28, .max = 112 },
0206e353 352 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 353 .p2 = { .dot_limit = 225000,
354 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 355};
356
357static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 358 .dot = { .min = 25000, .max = 350000 },
359 .vco = { .min = 1760000, .max = 3510000 },
360 .n = { .min = 1, .max = 3 },
361 .m = { .min = 79, .max = 126 },
362 .m1 = { .min = 12, .max = 22 },
363 .m2 = { .min = 5, .max = 9 },
364 .p = { .min = 14, .max = 42 },
0206e353 365 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 366 .p2 = { .dot_limit = 225000,
367 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 368};
369
dc730512 370static const intel_limit_t intel_limits_vlv = {
f01b7962
VS		 371 /*
372 * These are the data rate limits (measured in fast clocks)
373 * since those are the strictest limits we have. The fast
374 * clock and actual rate limits are more relaxed, so checking
375 * them would make no difference.
376 */
377 .dot = { .min = 25000 * 5, .max = 270000 * 5 },
75e53986 378 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 379 .n = { .min = 1, .max = 7 },
a0c4da24
JB		 380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
b99ab663 382 .p1 = { .min = 2, .max = 3 },
5fdc9c49 383 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */
a0c4da24
JB		 384};
385
ef9348c8
CML		 386static const intel_limit_t intel_limits_chv = {
387 /*
388 * These are the data rate limits (measured in fast clocks)
389 * since those are the strictest limits we have. The fast
390 * clock and actual rate limits are more relaxed, so checking
391 * them would make no difference.
392 */
393 .dot = { .min = 25000 * 5, .max = 540000 * 5},
17fe1021 394 .vco = { .min = 4800000, .max = 6480000 },
ef9348c8
CML		 395 .n = { .min = 1, .max = 1 },
396 .m1 = { .min = 2, .max = 2 },
397 .m2 = { .min = 24 << 22, .max = 175 << 22 },
398 .p1 = { .min = 2, .max = 4 },
399 .p2 = { .p2_slow = 1, .p2_fast = 14 },
400};
401
6b4bf1c4
VS		 402static void vlv_clock(int refclk, intel_clock_t *clock)
403{
404 clock->m = clock->m1 * clock->m2;
405 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 406 if (WARN_ON(clock->n == 0 || clock->p == 0))
407 return;
fb03ac01
VS		 408 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
409 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
6b4bf1c4
VS		 410}
411
e0638cdf
PZ		 412/**
413 * Returns whether any output on the specified pipe is of the specified type
414 */
4093561b 415bool intel_pipe_has_type(struct intel_crtc *crtc, enum intel_output_type type)
e0638cdf 416{
409ee761 417 struct drm_device *dev = crtc->base.dev;
e0638cdf
PZ		 418 struct intel_encoder *encoder;
419
409ee761 420 for_each_encoder_on_crtc(dev, &crtc->base, encoder)
e0638cdf
PZ		 421 if (encoder->type == type)
422 return true;
423
424 return false;
425}
426
d0737e1d
ACO		 427/**
428 * Returns whether any output on the specified pipe will have the specified
429 * type after a staged modeset is complete, i.e., the same as
430 * intel_pipe_has_type() but looking at encoder->new_crtc instead of
431 * encoder->crtc.
432 */
433static bool intel_pipe_will_have_type(struct intel_crtc *crtc, int type)
434{
435 struct drm_device *dev = crtc->base.dev;
436 struct intel_encoder *encoder;
437
438 for_each_intel_encoder(dev, encoder)
439 if (encoder->new_crtc == crtc && encoder->type == type)
440 return true;
441
442 return false;
443}
444
409ee761 445static const intel_limit_t *intel_ironlake_limit(struct intel_crtc *crtc,
1b894b59 446 int refclk)
2c07245f 447{
409ee761 448 struct drm_device *dev = crtc->base.dev;
2c07245f 449 const intel_limit_t *limit;
b91ad0ec 450
d0737e1d 451 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 452 if (intel_is_dual_link_lvds(dev)) {
1b894b59 453 if (refclk == 100000)
b91ad0ec
ZW		 454 limit = &intel_limits_ironlake_dual_lvds_100m;
455 else
456 limit = &intel_limits_ironlake_dual_lvds;
457 } else {
1b894b59 458 if (refclk == 100000)
b91ad0ec
ZW		 459 limit = &intel_limits_ironlake_single_lvds_100m;
460 else
461 limit = &intel_limits_ironlake_single_lvds;
462 }
c6bb3538 463 } else
b91ad0ec 464 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 465
466 return limit;
467}
468
409ee761 469static const intel_limit_t *intel_g4x_limit(struct intel_crtc *crtc)
044c7c41 470{
409ee761 471 struct drm_device *dev = crtc->base.dev;
044c7c41
ML		 472 const intel_limit_t *limit;
473
d0737e1d 474 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 475 if (intel_is_dual_link_lvds(dev))
e4b36699 476 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 477 else
e4b36699 478 limit = &intel_limits_g4x_single_channel_lvds;
d0737e1d
ACO		 479 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI) ||
480 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 481 limit = &intel_limits_g4x_hdmi;
d0737e1d 482 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 483 limit = &intel_limits_g4x_sdvo;
044c7c41 484 } else /* The option is for other outputs */
e4b36699 485 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 486
487 return limit;
488}
489
409ee761 490static const intel_limit_t *intel_limit(struct intel_crtc *crtc, int refclk)
79e53945 491{
409ee761 492 struct drm_device *dev = crtc->base.dev;
79e53945
JB		 493 const intel_limit_t *limit;
494
bad720ff 495 if (HAS_PCH_SPLIT(dev))
1b894b59 496 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 497 else if (IS_G4X(dev)) {
044c7c41 498 limit = intel_g4x_limit(crtc);
f2b115e6 499 } else if (IS_PINEVIEW(dev)) {
d0737e1d 500 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 501 limit = &intel_limits_pineview_lvds;
2177832f 502 else
f2b115e6 503 limit = &intel_limits_pineview_sdvo;
ef9348c8
CML		 504 } else if (IS_CHERRYVIEW(dev)) {
505 limit = &intel_limits_chv;
a0c4da24 506 } else if (IS_VALLEYVIEW(dev)) {
dc730512 507 limit = &intel_limits_vlv;
a6c45cf0 508 } else if (!IS_GEN2(dev)) {
d0737e1d 509 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
a6c45cf0
CW		 510 limit = &intel_limits_i9xx_lvds;
511 else
512 limit = &intel_limits_i9xx_sdvo;
79e53945 513 } else {
d0737e1d 514 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 515 limit = &intel_limits_i8xx_lvds;
d0737e1d 516 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 517 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 518 else
519 limit = &intel_limits_i8xx_dac;
79e53945
JB		 520 }
521 return limit;
522}
523
f2b115e6
AJ		 524/* m1 is reserved as 0 in Pineview, n is a ring counter */
525static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 526{
2177832f
SL		 527 clock->m = clock->m2 + 2;
528 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 529 if (WARN_ON(clock->n == 0 || clock->p == 0))
530 return;
fb03ac01
VS		 531 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n);
532 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
2177832f
SL		 533}
534
7429e9d4
DV		 535static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
536{
537 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
538}
539
ac58c3f0 540static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 541{
7429e9d4 542 clock->m = i9xx_dpll_compute_m(clock);
79e53945 543 clock->p = clock->p1 * clock->p2;
ed5ca77e
VS		 544 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0))
545 return;
fb03ac01
VS		 546 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2);
547 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
79e53945
JB		 548}
549
ef9348c8
CML		 550static void chv_clock(int refclk, intel_clock_t *clock)
551{
552 clock->m = clock->m1 * clock->m2;
553 clock->p = clock->p1 * clock->p2;
554 if (WARN_ON(clock->n == 0 || clock->p == 0))
555 return;
556 clock->vco = DIV_ROUND_CLOSEST_ULL((uint64_t)refclk * clock->m,
557 clock->n << 22);
558 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p);
559}
560
7c04d1d9 561#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 562/**
563 * Returns whether the given set of divisors are valid for a given refclk with
564 * the given connectors.
565 */
566
1b894b59
CW		 567static bool intel_PLL_is_valid(struct drm_device *dev,
568 const intel_limit_t *limit,
569 const intel_clock_t *clock)
79e53945 570{
f01b7962
VS		 571 if (clock->n < limit->n.min || limit->n.max < clock->n)
572 INTELPllInvalid("n out of range\n");
79e53945 573 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 574 INTELPllInvalid("p1 out of range\n");
79e53945 575 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 576 INTELPllInvalid("m2 out of range\n");
79e53945 577 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 578 INTELPllInvalid("m1 out of range\n");
f01b7962
VS		 579
580 if (!IS_PINEVIEW(dev) && !IS_VALLEYVIEW(dev))
581 if (clock->m1 <= clock->m2)
582 INTELPllInvalid("m1 <= m2\n");
583
584 if (!IS_VALLEYVIEW(dev)) {
585 if (clock->p < limit->p.min || limit->p.max < clock->p)
586 INTELPllInvalid("p out of range\n");
587 if (clock->m < limit->m.min || limit->m.max < clock->m)
588 INTELPllInvalid("m out of range\n");
589 }
590
79e53945 591 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 592 INTELPllInvalid("vco out of range\n");
79e53945
JB		 593 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
594 * connector, etc., rather than just a single range.
595 */
596 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 597 INTELPllInvalid("dot out of range\n");
79e53945
JB		 598
599 return true;
600}
601
d4906093 602static bool
a919ff14 603i9xx_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
cec2f356
SP		 604 int target, int refclk, intel_clock_t *match_clock,
605 intel_clock_t *best_clock)
79e53945 606{
a919ff14 607 struct drm_device *dev = crtc->base.dev;
79e53945 608 intel_clock_t clock;
79e53945
JB		 609 int err = target;
610
d0737e1d 611 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 612 /*
a210b028
DV		 613 * For LVDS just rely on its current settings for dual-channel.
614 * We haven't figured out how to reliably set up different
615 * single/dual channel state, if we even can.
79e53945 616 */
1974cad0 617 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 618 clock.p2 = limit->p2.p2_fast;
619 else
620 clock.p2 = limit->p2.p2_slow;
621 } else {
622 if (target < limit->p2.dot_limit)
623 clock.p2 = limit->p2.p2_slow;
624 else
625 clock.p2 = limit->p2.p2_fast;
626 }
627
0206e353 628 memset(best_clock, 0, sizeof(*best_clock));
79e53945 629
42158660
ZY		 630 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
631 clock.m1++) {
632 for (clock.m2 = limit->m2.min;
633 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 634 if (clock.m2 >= clock.m1)
42158660
ZY		 635 break;
636 for (clock.n = limit->n.min;
637 clock.n <= limit->n.max; clock.n++) {
638 for (clock.p1 = limit->p1.min;
639 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 640 int this_err;
641
ac58c3f0
DV		 642 i9xx_clock(refclk, &clock);
643 if (!intel_PLL_is_valid(dev, limit,
644 &clock))
645 continue;
646 if (match_clock &&
647 clock.p != match_clock->p)
648 continue;
649
650 this_err = abs(clock.dot - target);
651 if (this_err < err) {
652 *best_clock = clock;
653 err = this_err;
654 }
655 }
656 }
657 }
658 }
659
660 return (err != target);
661}
662
663static bool
a919ff14 664pnv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
ee9300bb
DV		 665 int target, int refclk, intel_clock_t *match_clock,
666 intel_clock_t *best_clock)
79e53945 667{
a919ff14 668 struct drm_device *dev = crtc->base.dev;
79e53945 669 intel_clock_t clock;
79e53945
JB		 670 int err = target;
671
d0737e1d 672 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 673 /*
a210b028
DV		 674 * For LVDS just rely on its current settings for dual-channel.
675 * We haven't figured out how to reliably set up different
676 * single/dual channel state, if we even can.
79e53945 677 */
1974cad0 678 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 679 clock.p2 = limit->p2.p2_fast;
680 else
681 clock.p2 = limit->p2.p2_slow;
682 } else {
683 if (target < limit->p2.dot_limit)
684 clock.p2 = limit->p2.p2_slow;
685 else
686 clock.p2 = limit->p2.p2_fast;
687 }
688
0206e353 689 memset(best_clock, 0, sizeof(*best_clock));
79e53945 690
42158660
ZY		 691 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
692 clock.m1++) {
693 for (clock.m2 = limit->m2.min;
694 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 695 for (clock.n = limit->n.min;
696 clock.n <= limit->n.max; clock.n++) {
697 for (clock.p1 = limit->p1.min;
698 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 699 int this_err;
700
ac58c3f0 701 pineview_clock(refclk, &clock);
1b894b59
CW		 702 if (!intel_PLL_is_valid(dev, limit,
703 &clock))
79e53945 704 continue;
cec2f356
SP		 705 if (match_clock &&
706 clock.p != match_clock->p)
707 continue;
79e53945
JB		 708
709 this_err = abs(clock.dot - target);
710 if (this_err < err) {
711 *best_clock = clock;
712 err = this_err;
713 }
714 }
715 }
716 }
717 }
718
719 return (err != target);
720}
721
d4906093 722static bool
a919ff14 723g4x_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
ee9300bb
DV		 724 int target, int refclk, intel_clock_t *match_clock,
725 intel_clock_t *best_clock)
d4906093 726{
a919ff14 727 struct drm_device *dev = crtc->base.dev;
d4906093
ML		 728 intel_clock_t clock;
729 int max_n;
730 bool found;
6ba770dc
AJ		 731 /* approximately equals target * 0.00585 */
732 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 733 found = false;
734
d0737e1d 735 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 736 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 737 clock.p2 = limit->p2.p2_fast;
738 else
739 clock.p2 = limit->p2.p2_slow;
740 } else {
741 if (target < limit->p2.dot_limit)
742 clock.p2 = limit->p2.p2_slow;
743 else
744 clock.p2 = limit->p2.p2_fast;
745 }
746
747 memset(best_clock, 0, sizeof(*best_clock));
748 max_n = limit->n.max;
f77f13e2 749 /* based on hardware requirement, prefer smaller n to precision */
d4906093 750 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 751 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 752 for (clock.m1 = limit->m1.max;
753 clock.m1 >= limit->m1.min; clock.m1--) {
754 for (clock.m2 = limit->m2.max;
755 clock.m2 >= limit->m2.min; clock.m2--) {
756 for (clock.p1 = limit->p1.max;
757 clock.p1 >= limit->p1.min; clock.p1--) {
758 int this_err;
759
ac58c3f0 760 i9xx_clock(refclk, &clock);
1b894b59
CW		 761 if (!intel_PLL_is_valid(dev, limit,
762 &clock))
d4906093 763 continue;
1b894b59
CW		 764
765 this_err = abs(clock.dot - target);
d4906093
ML		 766 if (this_err < err_most) {
767 *best_clock = clock;
768 err_most = this_err;
769 max_n = clock.n;
770 found = true;
771 }
772 }
773 }
774 }
775 }
2c07245f
ZW		 776 return found;
777}
778
d5dd62bd
ID		 779/*
780 * Check if the calculated PLL configuration is more optimal compared to the
781 * best configuration and error found so far. Return the calculated error.
782 */
783static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq,
784 const intel_clock_t *calculated_clock,
785 const intel_clock_t *best_clock,
786 unsigned int best_error_ppm,
787 unsigned int *error_ppm)
788{
9ca3ba01
ID		 789 /*
790 * For CHV ignore the error and consider only the P value.
791 * Prefer a bigger P value based on HW requirements.
792 */
793 if (IS_CHERRYVIEW(dev)) {
794 *error_ppm = 0;
795
796 return calculated_clock->p > best_clock->p;
797 }
798
24be4e46
ID		 799 if (WARN_ON_ONCE(!target_freq))
800 return false;
801
d5dd62bd
ID		 802 *error_ppm = div_u64(1000000ULL *
803 abs(target_freq - calculated_clock->dot),
804 target_freq);
805 /*
806 * Prefer a better P value over a better (smaller) error if the error
807 * is small. Ensure this preference for future configurations too by
808 * setting the error to 0.
809 */
810 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) {
811 *error_ppm = 0;
812
813 return true;
814 }
815
816 return *error_ppm + 10 < best_error_ppm;
817}
818
a0c4da24 819static bool
a919ff14 820vlv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
ee9300bb
DV		 821 int target, int refclk, intel_clock_t *match_clock,
822 intel_clock_t *best_clock)
a0c4da24 823{
a919ff14 824 struct drm_device *dev = crtc->base.dev;
6b4bf1c4 825 intel_clock_t clock;
69e4f900 826 unsigned int bestppm = 1000000;
27e639bf
VS		 827 /* min update 19.2 MHz */
828 int max_n = min(limit->n.max, refclk / 19200);
49e497ef 829 bool found = false;
a0c4da24 830
6b4bf1c4
VS		 831 target *= 5; /* fast clock */
832
833 memset(best_clock, 0, sizeof(*best_clock));
a0c4da24
JB		 834
835 /* based on hardware requirement, prefer smaller n to precision */
27e639bf 836 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
811bbf05 837 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
889059d8 838 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow;
c1a9ae43 839 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
6b4bf1c4 840 clock.p = clock.p1 * clock.p2;
a0c4da24 841 /* based on hardware requirement, prefer bigger m1,m2 values */
6b4bf1c4 842 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
d5dd62bd 843 unsigned int ppm;
69e4f900 844
6b4bf1c4
VS		 845 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n,
846 refclk * clock.m1);
847
848 vlv_clock(refclk, &clock);
43b0ac53 849
f01b7962
VS		 850 if (!intel_PLL_is_valid(dev, limit,
851 &clock))
43b0ac53
VS		 852 continue;
853
d5dd62bd
ID		 854 if (!vlv_PLL_is_optimal(dev, target,
855 &clock,
856 best_clock,
857 bestppm, &ppm))
858 continue;
6b4bf1c4 859
d5dd62bd
ID		 860 *best_clock = clock;
861 bestppm = ppm;
862 found = true;
a0c4da24
JB		 863 }
864 }
865 }
866 }
a0c4da24 867
49e497ef 868 return found;
a0c4da24 869}
a4fc5ed6 870
ef9348c8 871static bool
a919ff14 872chv_find_best_dpll(const intel_limit_t *limit, struct intel_crtc *crtc,
ef9348c8
CML		 873 int target, int refclk, intel_clock_t *match_clock,
874 intel_clock_t *best_clock)
875{
a919ff14 876 struct drm_device *dev = crtc->base.dev;
9ca3ba01 877 unsigned int best_error_ppm;
ef9348c8
CML		 878 intel_clock_t clock;
879 uint64_t m2;
880 int found = false;
881
882 memset(best_clock, 0, sizeof(*best_clock));
9ca3ba01 883 best_error_ppm = 1000000;
ef9348c8
CML		 884
885 /*
886 * Based on hardware doc, the n always set to 1, and m1 always
887 * set to 2. If requires to support 200Mhz refclk, we need to
888 * revisit this because n may not 1 anymore.
889 */
890 clock.n = 1, clock.m1 = 2;
891 target *= 5; /* fast clock */
892
893 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) {
894 for (clock.p2 = limit->p2.p2_fast;
895 clock.p2 >= limit->p2.p2_slow;
896 clock.p2 -= clock.p2 > 10 ? 2 : 1) {
9ca3ba01 897 unsigned int error_ppm;
ef9348c8
CML		 898
899 clock.p = clock.p1 * clock.p2;
900
901 m2 = DIV_ROUND_CLOSEST_ULL(((uint64_t)target * clock.p *
902 clock.n) << 22, refclk * clock.m1);
903
904 if (m2 > INT_MAX/clock.m1)
905 continue;
906
907 clock.m2 = m2;
908
909 chv_clock(refclk, &clock);
910
911 if (!intel_PLL_is_valid(dev, limit, &clock))
912 continue;
913
9ca3ba01
ID		 914 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock,
915 best_error_ppm, &error_ppm))
916 continue;
917
918 *best_clock = clock;
919 best_error_ppm = error_ppm;
920 found = true;
ef9348c8
CML		 921 }
922 }
923
924 return found;
925}
926
20ddf665
VS		 927bool intel_crtc_active(struct drm_crtc *crtc)
928{
929 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
930
931 /* Be paranoid as we can arrive here with only partial
932 * state retrieved from the hardware during setup.
933 *
241bfc38 934 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 935 * as Haswell has gained clock readout/fastboot support.
936 *
66e514c1 937 * We can ditch the crtc->primary->fb check as soon as we can
20ddf665 938 * properly reconstruct framebuffers.
c3d1f436
MR		 939 *
940 * FIXME: The intel_crtc->active here should be switched to
941 * crtc->state->active once we have proper CRTC states wired up
942 * for atomic.
20ddf665 943 */
c3d1f436 944 return intel_crtc->active && crtc->primary->state->fb &&
6e3c9717 945 intel_crtc->config->base.adjusted_mode.crtc_clock;
20ddf665
VS		 946}
947
a5c961d1
PZ		 948enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
949 enum pipe pipe)
950{
951 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
952 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
953
6e3c9717 954 return intel_crtc->config->cpu_transcoder;
a5c961d1
PZ		 955}
956
fbf49ea2
VS		 957static bool pipe_dsl_stopped(struct drm_device *dev, enum pipe pipe)
958{
959 struct drm_i915_private *dev_priv = dev->dev_private;
960 u32 reg = PIPEDSL(pipe);
961 u32 line1, line2;
962 u32 line_mask;
963
964 if (IS_GEN2(dev))
965 line_mask = DSL_LINEMASK_GEN2;
966 else
967 line_mask = DSL_LINEMASK_GEN3;
968
969 line1 = I915_READ(reg) & line_mask;
970 mdelay(5);
971 line2 = I915_READ(reg) & line_mask;
972
973 return line1 == line2;
974}
975
ab7ad7f6
KP		 976/*
977 * intel_wait_for_pipe_off - wait for pipe to turn off
575f7ab7 978 * @crtc: crtc whose pipe to wait for
9d0498a2
JB		 979 *
980 * After disabling a pipe, we can't wait for vblank in the usual way,
981 * spinning on the vblank interrupt status bit, since we won't actually
982 * see an interrupt when the pipe is disabled.
983 *
ab7ad7f6
KP		 984 * On Gen4 and above:
985 * wait for the pipe register state bit to turn off
986 *
987 * Otherwise:
988 * wait for the display line value to settle (it usually
989 * ends up stopping at the start of the next frame).
58e10eb9 990 *
9d0498a2 991 */
575f7ab7 992static void intel_wait_for_pipe_off(struct intel_crtc *crtc)
9d0498a2 993{
575f7ab7 994 struct drm_device *dev = crtc->base.dev;
9d0498a2 995 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 996 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 997 enum pipe pipe = crtc->pipe;
ab7ad7f6
KP		 998
999 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 1000 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 1001
1002 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1003 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1004 100))
284637d9 1005 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1006 } else {
ab7ad7f6 1007 /* Wait for the display line to settle */
fbf49ea2 1008 if (wait_for(pipe_dsl_stopped(dev, pipe), 100))
284637d9 1009 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 1010 }
79e53945
JB		 1011}
1012
b0ea7d37
DL		 1013/*
1014 * ibx_digital_port_connected - is the specified port connected?
1015 * @dev_priv: i915 private structure
1016 * @port: the port to test
1017 *
1018 * Returns true if @port is connected, false otherwise.
1019 */
1020bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
1021 struct intel_digital_port *port)
1022{
1023 u32 bit;
1024
c36346e3 1025 if (HAS_PCH_IBX(dev_priv->dev)) {
eba905b2 1026 switch (port->port) {
c36346e3
DL		 1027 case PORT_B:
1028 bit = SDE_PORTB_HOTPLUG;
1029 break;
1030 case PORT_C:
1031 bit = SDE_PORTC_HOTPLUG;
1032 break;
1033 case PORT_D:
1034 bit = SDE_PORTD_HOTPLUG;
1035 break;
1036 default:
1037 return true;
1038 }
1039 } else {
eba905b2 1040 switch (port->port) {
c36346e3
DL		 1041 case PORT_B:
1042 bit = SDE_PORTB_HOTPLUG_CPT;
1043 break;
1044 case PORT_C:
1045 bit = SDE_PORTC_HOTPLUG_CPT;
1046 break;
1047 case PORT_D:
1048 bit = SDE_PORTD_HOTPLUG_CPT;
1049 break;
1050 default:
1051 return true;
1052 }
b0ea7d37
DL		 1053 }
1054
1055 return I915_READ(SDEISR) & bit;
1056}
1057
b24e7179
JB		 1058static const char *state_string(bool enabled)
1059{
1060 return enabled ? "on" : "off";
1061}
1062
1063/* Only for pre-ILK configs */
55607e8a
DV		 1064void assert_pll(struct drm_i915_private *dev_priv,
1065 enum pipe pipe, bool state)
b24e7179
JB		 1066{
1067 int reg;
1068 u32 val;
1069 bool cur_state;
1070
1071 reg = DPLL(pipe);
1072 val = I915_READ(reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
e2c719b7 1074 I915_STATE_WARN(cur_state != state,
b24e7179
JB		 1075 "PLL state assertion failure (expected %s, current %s)\n",
1076 state_string(state), state_string(cur_state));
1077}
b24e7179 1078
23538ef1
JN		 1079/* XXX: the dsi pll is shared between MIPI DSI ports */
1080static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
1081{
1082 u32 val;
1083 bool cur_state;
1084
1085 mutex_lock(&dev_priv->dpio_lock);
1086 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
1087 mutex_unlock(&dev_priv->dpio_lock);
1088
1089 cur_state = val & DSI_PLL_VCO_EN;
e2c719b7 1090 I915_STATE_WARN(cur_state != state,
23538ef1
JN		 1091 "DSI PLL state assertion failure (expected %s, current %s)\n",
1092 state_string(state), state_string(cur_state));
1093}
1094#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
1095#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
1096
55607e8a 1097struct intel_shared_dpll *
e2b78267
DV		 1098intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
1099{
1100 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1101
6e3c9717 1102 if (crtc->config->shared_dpll < 0)
e2b78267
DV		 1103 return NULL;
1104
6e3c9717 1105 return &dev_priv->shared_dplls[crtc->config->shared_dpll];
e2b78267
DV		 1106}
1107
040484af 1108/* For ILK+ */
55607e8a
DV		 1109void assert_shared_dpll(struct drm_i915_private *dev_priv,
1110 struct intel_shared_dpll *pll,
1111 bool state)
040484af 1112{
040484af 1113 bool cur_state;
5358901f 1114 struct intel_dpll_hw_state hw_state;
040484af 1115
92b27b08 1116 if (WARN (!pll,
46edb027 1117 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 1118 return;
ee7b9f93 1119
5358901f 1120 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
e2c719b7 1121 I915_STATE_WARN(cur_state != state,
5358901f
DV		 1122 "%s assertion failure (expected %s, current %s)\n",
1123 pll->name, state_string(state), state_string(cur_state));
040484af 1124}
040484af
JB		 1125
1126static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1127 enum pipe pipe, bool state)
1128{
1129 int reg;
1130 u32 val;
1131 bool cur_state;
ad80a810
PZ		 1132 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1133 pipe);
040484af 1134
affa9354
PZ		 1135 if (HAS_DDI(dev_priv->dev)) {
1136 /* DDI does not have a specific FDI_TX register */
ad80a810 1137 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1138 val = I915_READ(reg);
ad80a810 1139 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1140 } else {
1141 reg = FDI_TX_CTL(pipe);
1142 val = I915_READ(reg);
1143 cur_state = !!(val & FDI_TX_ENABLE);
1144 }
e2c719b7 1145 I915_STATE_WARN(cur_state != state,
040484af
JB		 1146 "FDI TX state assertion failure (expected %s, current %s)\n",
1147 state_string(state), state_string(cur_state));
1148}
1149#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1150#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1151
1152static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1153 enum pipe pipe, bool state)
1154{
1155 int reg;
1156 u32 val;
1157 bool cur_state;
1158
d63fa0dc
PZ		 1159 reg = FDI_RX_CTL(pipe);
1160 val = I915_READ(reg);
1161 cur_state = !!(val & FDI_RX_ENABLE);
e2c719b7 1162 I915_STATE_WARN(cur_state != state,
040484af
JB		 1163 "FDI RX state assertion failure (expected %s, current %s)\n",
1164 state_string(state), state_string(cur_state));
1165}
1166#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1167#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1168
1169static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1170 enum pipe pipe)
1171{
1172 int reg;
1173 u32 val;
1174
1175 /* ILK FDI PLL is always enabled */
3d13ef2e 1176 if (INTEL_INFO(dev_priv->dev)->gen == 5)
040484af
JB		 1177 return;
1178
bf507ef7 1179 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1180 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1181 return;
1182
040484af
JB		 1183 reg = FDI_TX_CTL(pipe);
1184 val = I915_READ(reg);
e2c719b7 1185 I915_STATE_WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
040484af
JB		 1186}
1187
55607e8a
DV		 1188void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1189 enum pipe pipe, bool state)
040484af
JB		 1190{
1191 int reg;
1192 u32 val;
55607e8a 1193 bool cur_state;
040484af
JB		 1194
1195 reg = FDI_RX_CTL(pipe);
1196 val = I915_READ(reg);
55607e8a 1197 cur_state = !!(val & FDI_RX_PLL_ENABLE);
e2c719b7 1198 I915_STATE_WARN(cur_state != state,
55607e8a
DV		 1199 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1200 state_string(state), state_string(cur_state));
040484af
JB		 1201}
1202
b680c37a
DV		 1203void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1204 enum pipe pipe)
ea0760cf 1205{
bedd4dba
JN		 1206 struct drm_device *dev = dev_priv->dev;
1207 int pp_reg;
ea0760cf
JB		 1208 u32 val;
1209 enum pipe panel_pipe = PIPE_A;
0de3b485 1210 bool locked = true;
ea0760cf 1211
bedd4dba
JN		 1212 if (WARN_ON(HAS_DDI(dev)))
1213 return;
1214
1215 if (HAS_PCH_SPLIT(dev)) {
1216 u32 port_sel;
1217
ea0760cf 1218 pp_reg = PCH_PP_CONTROL;
bedd4dba
JN		 1219 port_sel = I915_READ(PCH_PP_ON_DELAYS) & PANEL_PORT_SELECT_MASK;
1220
1221 if (port_sel == PANEL_PORT_SELECT_LVDS &&
1222 I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT)
1223 panel_pipe = PIPE_B;
1224 /* XXX: else fix for eDP */
1225 } else if (IS_VALLEYVIEW(dev)) {
1226 /* presumably write lock depends on pipe, not port select */
1227 pp_reg = VLV_PIPE_PP_CONTROL(pipe);
1228 panel_pipe = pipe;
ea0760cf
JB		 1229 } else {
1230 pp_reg = PP_CONTROL;
bedd4dba
JN		 1231 if (I915_READ(LVDS) & LVDS_PIPEB_SELECT)
1232 panel_pipe = PIPE_B;
ea0760cf
JB		 1233 }
1234
1235 val = I915_READ(pp_reg);
1236 if (!(val & PANEL_POWER_ON) ||
ec49ba2d 1237 ((val & PANEL_UNLOCK_MASK) == PANEL_UNLOCK_REGS))
ea0760cf
JB		 1238 locked = false;
1239
e2c719b7 1240 I915_STATE_WARN(panel_pipe == pipe && locked,
ea0760cf 1241 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1242 pipe_name(pipe));
ea0760cf
JB		 1243}
1244
93ce0ba6
JN		 1245static void assert_cursor(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, bool state)
1247{
1248 struct drm_device *dev = dev_priv->dev;
1249 bool cur_state;
1250
d9d82081 1251 if (IS_845G(dev) || IS_I865G(dev))
93ce0ba6 1252 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
d9d82081 1253 else
5efb3e28 1254 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
93ce0ba6 1255
e2c719b7 1256 I915_STATE_WARN(cur_state != state,
93ce0ba6
JN		 1257 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1258 pipe_name(pipe), state_string(state), state_string(cur_state));
1259}
1260#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1261#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1262
b840d907
JB		 1263void assert_pipe(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, bool state)
b24e7179
JB		 1265{
1266 int reg;
1267 u32 val;
63d7bbe9 1268 bool cur_state;
702e7a56
PZ		 1269 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1270 pipe);
b24e7179 1271
b6b5d049
VS		 1272 /* if we need the pipe quirk it must be always on */
1273 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1274 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
8e636784
DV		 1275 state = true;
1276
f458ebbc 1277 if (!intel_display_power_is_enabled(dev_priv,
b97186f0 1278 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1279 cur_state = false;
1280 } else {
1281 reg = PIPECONF(cpu_transcoder);
1282 val = I915_READ(reg);
1283 cur_state = !!(val & PIPECONF_ENABLE);
1284 }
1285
e2c719b7 1286 I915_STATE_WARN(cur_state != state,
63d7bbe9 1287 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1288 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1289}
1290
931872fc
CW		 1291static void assert_plane(struct drm_i915_private *dev_priv,
1292 enum plane plane, bool state)
b24e7179
JB		 1293{
1294 int reg;
1295 u32 val;
931872fc 1296 bool cur_state;
b24e7179
JB		 1297
1298 reg = DSPCNTR(plane);
1299 val = I915_READ(reg);
931872fc 1300 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
e2c719b7 1301 I915_STATE_WARN(cur_state != state,
931872fc
CW		 1302 "plane %c assertion failure (expected %s, current %s)\n",
1303 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1304}
1305
931872fc
CW		 1306#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1307#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1308
b24e7179
JB		 1309static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1310 enum pipe pipe)
1311{
653e1026 1312 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1313 int reg, i;
1314 u32 val;
1315 int cur_pipe;
1316
653e1026
VS		 1317 /* Primary planes are fixed to pipes on gen4+ */
1318 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1319 reg = DSPCNTR(pipe);
1320 val = I915_READ(reg);
e2c719b7 1321 I915_STATE_WARN(val & DISPLAY_PLANE_ENABLE,
28c05794
AJ		 1322 "plane %c assertion failure, should be disabled but not\n",
1323 plane_name(pipe));
19ec1358 1324 return;
28c05794 1325 }
19ec1358 1326
b24e7179 1327 /* Need to check both planes against the pipe */
055e393f 1328 for_each_pipe(dev_priv, i) {
b24e7179
JB		 1329 reg = DSPCNTR(i);
1330 val = I915_READ(reg);
1331 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1332 DISPPLANE_SEL_PIPE_SHIFT;
e2c719b7 1333 I915_STATE_WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1334 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1335 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1336 }
1337}
1338
19332d7a
JB		 1339static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1340 enum pipe pipe)
1341{
20674eef 1342 struct drm_device *dev = dev_priv->dev;
1fe47785 1343 int reg, sprite;
19332d7a
JB		 1344 u32 val;
1345
7feb8b88 1346 if (INTEL_INFO(dev)->gen >= 9) {
3bdcfc0c 1347 for_each_sprite(dev_priv, pipe, sprite) {
7feb8b88 1348 val = I915_READ(PLANE_CTL(pipe, sprite));
e2c719b7 1349 I915_STATE_WARN(val & PLANE_CTL_ENABLE,
7feb8b88
DL		 1350 "plane %d assertion failure, should be off on pipe %c but is still active\n",
1351 sprite, pipe_name(pipe));
1352 }
1353 } else if (IS_VALLEYVIEW(dev)) {
3bdcfc0c 1354 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 1355 reg = SPCNTR(pipe, sprite);
20674eef 1356 val = I915_READ(reg);
e2c719b7 1357 I915_STATE_WARN(val & SP_ENABLE,
20674eef 1358 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1fe47785 1359 sprite_name(pipe, sprite), pipe_name(pipe));
20674eef
VS		 1360 }
1361 } else if (INTEL_INFO(dev)->gen >= 7) {
1362 reg = SPRCTL(pipe);
19332d7a 1363 val = I915_READ(reg);
e2c719b7 1364 I915_STATE_WARN(val & SPRITE_ENABLE,
06da8da2 1365 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1366 plane_name(pipe), pipe_name(pipe));
1367 } else if (INTEL_INFO(dev)->gen >= 5) {
1368 reg = DVSCNTR(pipe);
19332d7a 1369 val = I915_READ(reg);
e2c719b7 1370 I915_STATE_WARN(val & DVS_ENABLE,
06da8da2 1371 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1372 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1373 }
1374}
1375
08c71e5e
VS		 1376static void assert_vblank_disabled(struct drm_crtc *crtc)
1377{
e2c719b7 1378 if (I915_STATE_WARN_ON(drm_crtc_vblank_get(crtc) == 0))
08c71e5e
VS		 1379 drm_crtc_vblank_put(crtc);
1380}
1381
89eff4be 1382static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
92f2584a
JB		 1383{
1384 u32 val;
1385 bool enabled;
1386
e2c719b7 1387 I915_STATE_WARN_ON(!(HAS_PCH_IBX(dev_priv->dev) || HAS_PCH_CPT(dev_priv->dev)));
9d82aa17 1388
92f2584a
JB		 1389 val = I915_READ(PCH_DREF_CONTROL);
1390 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1391 DREF_SUPERSPREAD_SOURCE_MASK));
e2c719b7 1392 I915_STATE_WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
92f2584a
JB		 1393}
1394
ab9412ba
DV		 1395static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe)
92f2584a
JB		 1397{
1398 int reg;
1399 u32 val;
1400 bool enabled;
1401
ab9412ba 1402 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1403 val = I915_READ(reg);
1404 enabled = !!(val & TRANS_ENABLE);
e2c719b7 1405 I915_STATE_WARN(enabled,
9db4a9c7
JB		 1406 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1407 pipe_name(pipe));
92f2584a
JB		 1408}
1409
4e634389
KP		 1410static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1411 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1412{
1413 if ((val & DP_PORT_EN) == 0)
1414 return false;
1415
1416 if (HAS_PCH_CPT(dev_priv->dev)) {
1417 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1418 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1419 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1420 return false;
44f37d1f
CML		 1421 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1422 if ((val & DP_PIPE_MASK_CHV) != DP_PIPE_SELECT_CHV(pipe))
1423 return false;
f0575e92
KP		 1424 } else {
1425 if ((val & DP_PIPE_MASK) != (pipe << 30))
1426 return false;
1427 }
1428 return true;
1429}
1430
1519b995
KP		 1431static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1432 enum pipe pipe, u32 val)
1433{
dc0fa718 1434 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1435 return false;
1436
1437 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1438 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995 1439 return false;
44f37d1f
CML		 1440 } else if (IS_CHERRYVIEW(dev_priv->dev)) {
1441 if ((val & SDVO_PIPE_SEL_MASK_CHV) != SDVO_PIPE_SEL_CHV(pipe))
1442 return false;
1519b995 1443 } else {
dc0fa718 1444 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1445 return false;
1446 }
1447 return true;
1448}
1449
1450static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1451 enum pipe pipe, u32 val)
1452{
1453 if ((val & LVDS_PORT_EN) == 0)
1454 return false;
1455
1456 if (HAS_PCH_CPT(dev_priv->dev)) {
1457 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1458 return false;
1459 } else {
1460 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1461 return false;
1462 }
1463 return true;
1464}
1465
1466static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1467 enum pipe pipe, u32 val)
1468{
1469 if ((val & ADPA_DAC_ENABLE) == 0)
1470 return false;
1471 if (HAS_PCH_CPT(dev_priv->dev)) {
1472 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1473 return false;
1474 } else {
1475 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1476 return false;
1477 }
1478 return true;
1479}
1480
291906f1 1481static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1482 enum pipe pipe, int reg, u32 port_sel)
291906f1 1483{
47a05eca 1484 u32 val = I915_READ(reg);
e2c719b7 1485 I915_STATE_WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1486 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1487 reg, pipe_name(pipe));
de9a35ab 1488
e2c719b7 1489 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
75c5da27 1490 && (val & DP_PIPEB_SELECT),
de9a35ab 1491 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1492}
1493
1494static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1495 enum pipe pipe, int reg)
1496{
47a05eca 1497 u32 val = I915_READ(reg);
e2c719b7 1498 I915_STATE_WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1499 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1500 reg, pipe_name(pipe));
de9a35ab 1501
e2c719b7 1502 I915_STATE_WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1503 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1504 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1505}
1506
1507static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1508 enum pipe pipe)
1509{
1510 int reg;
1511 u32 val;
291906f1 1512
f0575e92
KP		 1513 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1514 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1515 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1516
1517 reg = PCH_ADPA;
1518 val = I915_READ(reg);
e2c719b7 1519 I915_STATE_WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1520 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1521 pipe_name(pipe));
291906f1
JB		 1522
1523 reg = PCH_LVDS;
1524 val = I915_READ(reg);
e2c719b7 1525 I915_STATE_WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1526 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1527 pipe_name(pipe));
291906f1 1528
e2debe91
PZ		 1529 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1530 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1531 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1532}
1533
40e9cf64
JB		 1534static void intel_init_dpio(struct drm_device *dev)
1535{
1536 struct drm_i915_private *dev_priv = dev->dev_private;
1537
1538 if (!IS_VALLEYVIEW(dev))
1539 return;
1540
a09caddd
CML		 1541 /*
1542 * IOSF_PORT_DPIO is used for VLV x2 PHY (DP/HDMI B and C),
1543 * CHV x1 PHY (DP/HDMI D)
1544 * IOSF_PORT_DPIO_2 is used for CHV x2 PHY (DP/HDMI B and C)
1545 */
1546 if (IS_CHERRYVIEW(dev)) {
1547 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO_2;
1548 DPIO_PHY_IOSF_PORT(DPIO_PHY1) = IOSF_PORT_DPIO;
1549 } else {
1550 DPIO_PHY_IOSF_PORT(DPIO_PHY0) = IOSF_PORT_DPIO;
1551 }
5382f5f3
JB		 1552}
1553
d288f65f 1554static void vlv_enable_pll(struct intel_crtc *crtc,
5cec258b 1555 const struct intel_crtc_state *pipe_config)
87442f73 1556{
426115cf
DV		 1557 struct drm_device *dev = crtc->base.dev;
1558 struct drm_i915_private *dev_priv = dev->dev_private;
1559 int reg = DPLL(crtc->pipe);
d288f65f 1560 u32 dpll = pipe_config->dpll_hw_state.dpll;
87442f73 1561
426115cf 1562 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1563
1564 /* No really, not for ILK+ */
1565 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1566
1567 /* PLL is protected by panel, make sure we can write it */
6a9e7363 1568 if (IS_MOBILE(dev_priv->dev))
426115cf 1569 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1570
426115cf
DV		 1571 I915_WRITE(reg, dpll);
1572 POSTING_READ(reg);
1573 udelay(150);
1574
1575 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1576 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1577
d288f65f 1578 I915_WRITE(DPLL_MD(crtc->pipe), pipe_config->dpll_hw_state.dpll_md);
426115cf 1579 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1580
1581 /* We do this three times for luck */
426115cf 1582 I915_WRITE(reg, dpll);
87442f73
DV		 1583 POSTING_READ(reg);
1584 udelay(150); /* wait for warmup */
426115cf 1585 I915_WRITE(reg, dpll);
87442f73
DV		 1586 POSTING_READ(reg);
1587 udelay(150); /* wait for warmup */
426115cf 1588 I915_WRITE(reg, dpll);
87442f73
DV		 1589 POSTING_READ(reg);
1590 udelay(150); /* wait for warmup */
1591}
1592
d288f65f 1593static void chv_enable_pll(struct intel_crtc *crtc,
5cec258b 1594 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 1595{
1596 struct drm_device *dev = crtc->base.dev;
1597 struct drm_i915_private *dev_priv = dev->dev_private;
1598 int pipe = crtc->pipe;
1599 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9d556c99
CML		 1600 u32 tmp;
1601
1602 assert_pipe_disabled(dev_priv, crtc->pipe);
1603
1604 BUG_ON(!IS_CHERRYVIEW(dev_priv->dev));
1605
1606 mutex_lock(&dev_priv->dpio_lock);
1607
1608 /* Enable back the 10bit clock to display controller */
1609 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1610 tmp |= DPIO_DCLKP_EN;
1611 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
1612
1613 /*
1614 * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
1615 */
1616 udelay(1);
1617
1618 /* Enable PLL */
d288f65f 1619 I915_WRITE(DPLL(pipe), pipe_config->dpll_hw_state.dpll);
9d556c99
CML		 1620
1621 /* Check PLL is locked */
a11b0703 1622 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
9d556c99
CML		 1623 DRM_ERROR("PLL %d failed to lock\n", pipe);
1624
a11b0703 1625 /* not sure when this should be written */
d288f65f 1626 I915_WRITE(DPLL_MD(pipe), pipe_config->dpll_hw_state.dpll_md);
a11b0703
VS		 1627 POSTING_READ(DPLL_MD(pipe));
1628
9d556c99
CML		 1629 mutex_unlock(&dev_priv->dpio_lock);
1630}
1631
1c4e0274
VS		 1632static int intel_num_dvo_pipes(struct drm_device *dev)
1633{
1634 struct intel_crtc *crtc;
1635 int count = 0;
1636
1637 for_each_intel_crtc(dev, crtc)
1638 count += crtc->active &&
409ee761 1639 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO);
1c4e0274
VS		 1640
1641 return count;
1642}
1643
66e3d5c0 1644static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1645{
66e3d5c0
DV		 1646 struct drm_device *dev = crtc->base.dev;
1647 struct drm_i915_private *dev_priv = dev->dev_private;
1648 int reg = DPLL(crtc->pipe);
6e3c9717 1649 u32 dpll = crtc->config->dpll_hw_state.dpll;
63d7bbe9 1650
66e3d5c0 1651 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1652
63d7bbe9 1653 /* No really, not for ILK+ */
3d13ef2e 1654 BUG_ON(INTEL_INFO(dev)->gen >= 5);
63d7bbe9
JB		 1655
1656 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1657 if (IS_MOBILE(dev) && !IS_I830(dev))
1658 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1659
1c4e0274
VS		 1660 /* Enable DVO 2x clock on both PLLs if necessary */
1661 if (IS_I830(dev) && intel_num_dvo_pipes(dev) > 0) {
1662 /*
1663 * It appears to be important that we don't enable this
1664 * for the current pipe before otherwise configuring the
1665 * PLL. No idea how this should be handled if multiple
1666 * DVO outputs are enabled simultaneosly.
1667 */
1668 dpll |= DPLL_DVO_2X_MODE;
1669 I915_WRITE(DPLL(!crtc->pipe),
1670 I915_READ(DPLL(!crtc->pipe)) | DPLL_DVO_2X_MODE);
1671 }
66e3d5c0
DV		 1672
1673 /* Wait for the clocks to stabilize. */
1674 POSTING_READ(reg);
1675 udelay(150);
1676
1677 if (INTEL_INFO(dev)->gen >= 4) {
1678 I915_WRITE(DPLL_MD(crtc->pipe),
6e3c9717 1679 crtc->config->dpll_hw_state.dpll_md);
66e3d5c0
DV		 1680 } else {
1681 /* The pixel multiplier can only be updated once the
1682 * DPLL is enabled and the clocks are stable.
1683 *
1684 * So write it again.
1685 */
1686 I915_WRITE(reg, dpll);
1687 }
63d7bbe9
JB		 1688
1689 /* We do this three times for luck */
66e3d5c0 1690 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1691 POSTING_READ(reg);
1692 udelay(150); /* wait for warmup */
66e3d5c0 1693 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1694 POSTING_READ(reg);
1695 udelay(150); /* wait for warmup */
66e3d5c0 1696 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1697 POSTING_READ(reg);
1698 udelay(150); /* wait for warmup */
1699}
1700
1701/**
50b44a44 1702 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1703 * @dev_priv: i915 private structure
1704 * @pipe: pipe PLL to disable
1705 *
1706 * Disable the PLL for @pipe, making sure the pipe is off first.
1707 *
1708 * Note! This is for pre-ILK only.
1709 */
1c4e0274 1710static void i9xx_disable_pll(struct intel_crtc *crtc)
63d7bbe9 1711{
1c4e0274
VS		 1712 struct drm_device *dev = crtc->base.dev;
1713 struct drm_i915_private *dev_priv = dev->dev_private;
1714 enum pipe pipe = crtc->pipe;
1715
1716 /* Disable DVO 2x clock on both PLLs if necessary */
1717 if (IS_I830(dev) &&
409ee761 1718 intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO) &&
1c4e0274
VS		 1719 intel_num_dvo_pipes(dev) == 1) {
1720 I915_WRITE(DPLL(PIPE_B),
1721 I915_READ(DPLL(PIPE_B)) & ~DPLL_DVO_2X_MODE);
1722 I915_WRITE(DPLL(PIPE_A),
1723 I915_READ(DPLL(PIPE_A)) & ~DPLL_DVO_2X_MODE);
1724 }
1725
b6b5d049
VS		 1726 /* Don't disable pipe or pipe PLLs if needed */
1727 if ((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
1728 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
63d7bbe9
JB		 1729 return;
1730
1731 /* Make sure the pipe isn't still relying on us */
1732 assert_pipe_disabled(dev_priv, pipe);
1733
50b44a44
DV		 1734 I915_WRITE(DPLL(pipe), 0);
1735 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1736}
1737
f6071166
JB		 1738static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1739{
1740 u32 val = 0;
1741
1742 /* Make sure the pipe isn't still relying on us */
1743 assert_pipe_disabled(dev_priv, pipe);
1744
e5cbfbfb
ID		 1745 /*
1746 * Leave integrated clock source and reference clock enabled for pipe B.
1747 * The latter is needed for VGA hotplug / manual detection.
1748 */
f6071166 1749 if (pipe == PIPE_B)
e5cbfbfb 1750 val = DPLL_INTEGRATED_CRI_CLK_VLV | DPLL_REFA_CLK_ENABLE_VLV;
f6071166
JB		 1751 I915_WRITE(DPLL(pipe), val);
1752 POSTING_READ(DPLL(pipe));
076ed3b2
CML		 1753
1754}
1755
1756static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1757{
d752048d 1758 enum dpio_channel port = vlv_pipe_to_channel(pipe);
076ed3b2
CML		 1759 u32 val;
1760
a11b0703
VS		 1761 /* Make sure the pipe isn't still relying on us */
1762 assert_pipe_disabled(dev_priv, pipe);
076ed3b2 1763
a11b0703 1764 /* Set PLL en = 0 */
d17ec4ce 1765 val = DPLL_SSC_REF_CLOCK_CHV | DPLL_REFA_CLK_ENABLE_VLV;
a11b0703
VS		 1766 if (pipe != PIPE_A)
1767 val |= DPLL_INTEGRATED_CRI_CLK_VLV;
1768 I915_WRITE(DPLL(pipe), val);
1769 POSTING_READ(DPLL(pipe));
d752048d
VS		 1770
1771 mutex_lock(&dev_priv->dpio_lock);
1772
1773 /* Disable 10bit clock to display controller */
1774 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
1775 val &= ~DPIO_DCLKP_EN;
1776 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
1777
61407f6d
VS		 1778 /* disable left/right clock distribution */
1779 if (pipe != PIPE_B) {
1780 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1781 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1782 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1783 } else {
1784 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1785 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1786 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1787 }
1788
d752048d 1789 mutex_unlock(&dev_priv->dpio_lock);
f6071166
JB		 1790}
1791
e4607fcf
CML		 1792void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
1793 struct intel_digital_port *dport)
89b667f8
JB		 1794{
1795 u32 port_mask;
00fc31b7 1796 int dpll_reg;
89b667f8 1797
e4607fcf
CML		 1798 switch (dport->port) {
1799 case PORT_B:
89b667f8 1800 port_mask = DPLL_PORTB_READY_MASK;
00fc31b7 1801 dpll_reg = DPLL(0);
e4607fcf
CML		 1802 break;
1803 case PORT_C:
89b667f8 1804 port_mask = DPLL_PORTC_READY_MASK;
00fc31b7
CML		 1805 dpll_reg = DPLL(0);
1806 break;
1807 case PORT_D:
1808 port_mask = DPLL_PORTD_READY_MASK;
1809 dpll_reg = DPIO_PHY_STATUS;
e4607fcf
CML		 1810 break;
1811 default:
1812 BUG();
1813 }
89b667f8 1814
00fc31b7 1815 if (wait_for((I915_READ(dpll_reg) & port_mask) == 0, 1000))
89b667f8 1816 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
00fc31b7 1817 port_name(dport->port), I915_READ(dpll_reg));
89b667f8
JB		 1818}
1819
b14b1055
DV		 1820static void intel_prepare_shared_dpll(struct intel_crtc *crtc)
1821{
1822 struct drm_device *dev = crtc->base.dev;
1823 struct drm_i915_private *dev_priv = dev->dev_private;
1824 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
1825
be19f0ff
CW		 1826 if (WARN_ON(pll == NULL))
1827 return;
1828
3e369b76 1829 WARN_ON(!pll->config.crtc_mask);
b14b1055
DV		 1830 if (pll->active == 0) {
1831 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
1832 WARN_ON(pll->on);
1833 assert_shared_dpll_disabled(dev_priv, pll);
1834
1835 pll->mode_set(dev_priv, pll);
1836 }
1837}
1838
92f2584a 1839/**
85b3894f 1840 * intel_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1841 * @dev_priv: i915 private structure
1842 * @pipe: pipe PLL to enable
1843 *
1844 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1845 * drives the transcoder clock.
1846 */
85b3894f 1847static void intel_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1848{
3d13ef2e
DL		 1849 struct drm_device *dev = crtc->base.dev;
1850 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1851 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1852
87a875bb 1853 if (WARN_ON(pll == NULL))
48da64a8
CW		 1854 return;
1855
3e369b76 1856 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1857 return;
ee7b9f93 1858
74dd6928 1859 DRM_DEBUG_KMS("enable %s (active %d, on? %d) for crtc %d\n",
46edb027 1860 pll->name, pll->active, pll->on,
e2b78267 1861 crtc->base.base.id);
92f2584a 1862
cdbd2316
DV		 1863 if (pll->active++) {
1864 WARN_ON(!pll->on);
e9d6944e 1865 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1866 return;
1867 }
f4a091c7 1868 WARN_ON(pll->on);
ee7b9f93 1869
bd2bb1b9
PZ		 1870 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
1871
46edb027 1872 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1873 pll->enable(dev_priv, pll);
ee7b9f93 1874 pll->on = true;
92f2584a
JB		 1875}
1876
f6daaec2 1877static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1878{
3d13ef2e
DL		 1879 struct drm_device *dev = crtc->base.dev;
1880 struct drm_i915_private *dev_priv = dev->dev_private;
e2b78267 1881 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1882
92f2584a 1883 /* PCH only available on ILK+ */
3d13ef2e 1884 BUG_ON(INTEL_INFO(dev)->gen < 5);
87a875bb 1885 if (WARN_ON(pll == NULL))
ee7b9f93 1886 return;
92f2584a 1887
3e369b76 1888 if (WARN_ON(pll->config.crtc_mask == 0))
48da64a8 1889 return;
7a419866 1890
46edb027
DV		 1891 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1892 pll->name, pll->active, pll->on,
e2b78267 1893 crtc->base.base.id);
7a419866 1894
48da64a8 1895 if (WARN_ON(pll->active == 0)) {
e9d6944e 1896 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1897 return;
1898 }
1899
e9d6944e 1900 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1901 WARN_ON(!pll->on);
cdbd2316 1902 if (--pll->active)
7a419866 1903 return;
ee7b9f93 1904
46edb027 1905 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1906 pll->disable(dev_priv, pll);
ee7b9f93 1907 pll->on = false;
bd2bb1b9
PZ		 1908
1909 intel_display_power_put(dev_priv, POWER_DOMAIN_PLLS);
92f2584a
JB		 1910}
1911
b8a4f404
PZ		 1912static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1913 enum pipe pipe)
040484af 1914{
23670b32 1915 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1916 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1917 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1918 uint32_t reg, val, pipeconf_val;
040484af
JB		 1919
1920 /* PCH only available on ILK+ */
55522f37 1921 BUG_ON(!HAS_PCH_SPLIT(dev));
040484af
JB		 1922
1923 /* Make sure PCH DPLL is enabled */
e72f9fbf 1924 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1925 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1926
1927 /* FDI must be feeding us bits for PCH ports */
1928 assert_fdi_tx_enabled(dev_priv, pipe);
1929 assert_fdi_rx_enabled(dev_priv, pipe);
1930
23670b32
DV		 1931 if (HAS_PCH_CPT(dev)) {
1932 /* Workaround: Set the timing override bit before enabling the
1933 * pch transcoder. */
1934 reg = TRANS_CHICKEN2(pipe);
1935 val = I915_READ(reg);
1936 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1937 I915_WRITE(reg, val);
59c859d6 1938 }
23670b32 1939
ab9412ba 1940 reg = PCH_TRANSCONF(pipe);
040484af 1941 val = I915_READ(reg);
5f7f726d 1942 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1943
1944 if (HAS_PCH_IBX(dev_priv->dev)) {
1945 /*
1946 * make the BPC in transcoder be consistent with
1947 * that in pipeconf reg.
1948 */
dfd07d72
DV		 1949 val &= ~PIPECONF_BPC_MASK;
1950 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1951 }
5f7f726d
PZ		 1952
1953 val &= ~TRANS_INTERLACE_MASK;
1954 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6 1955 if (HAS_PCH_IBX(dev_priv->dev) &&
409ee761 1956 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
7c26e5c6
PZ		 1957 val |= TRANS_LEGACY_INTERLACED_ILK;
1958 else
1959 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1960 else
1961 val |= TRANS_PROGRESSIVE;
1962
040484af
JB		 1963 I915_WRITE(reg, val | TRANS_ENABLE);
1964 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1965 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1966}
1967
8fb033d7 1968static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1969 enum transcoder cpu_transcoder)
040484af 1970{
8fb033d7 1971 u32 val, pipeconf_val;
8fb033d7
PZ		 1972
1973 /* PCH only available on ILK+ */
55522f37 1974 BUG_ON(!HAS_PCH_SPLIT(dev_priv->dev));
8fb033d7 1975
8fb033d7 1976 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1977 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1978 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1979
223a6fdf
PZ		 1980 /* Workaround: set timing override bit. */
1981 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1982 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1983 I915_WRITE(_TRANSA_CHICKEN2, val);
1984
25f3ef11 1985 val = TRANS_ENABLE;
937bb610 1986 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1987
9a76b1c6
PZ		 1988 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1989 PIPECONF_INTERLACED_ILK)
a35f2679 1990 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1991 else
1992 val |= TRANS_PROGRESSIVE;
1993
ab9412ba
DV		 1994 I915_WRITE(LPT_TRANSCONF, val);
1995 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1996 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1997}
1998
b8a4f404
PZ		 1999static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
2000 enum pipe pipe)
040484af 2001{
23670b32
DV		 2002 struct drm_device *dev = dev_priv->dev;
2003 uint32_t reg, val;
040484af
JB		 2004
2005 /* FDI relies on the transcoder */
2006 assert_fdi_tx_disabled(dev_priv, pipe);
2007 assert_fdi_rx_disabled(dev_priv, pipe);
2008
291906f1
JB		 2009 /* Ports must be off as well */
2010 assert_pch_ports_disabled(dev_priv, pipe);
2011
ab9412ba 2012 reg = PCH_TRANSCONF(pipe);
040484af
JB		 2013 val = I915_READ(reg);
2014 val &= ~TRANS_ENABLE;
2015 I915_WRITE(reg, val);
2016 /* wait for PCH transcoder off, transcoder state */
2017 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 2018 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 2019
2020 if (!HAS_PCH_IBX(dev)) {
2021 /* Workaround: Clear the timing override chicken bit again. */
2022 reg = TRANS_CHICKEN2(pipe);
2023 val = I915_READ(reg);
2024 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
2025 I915_WRITE(reg, val);
2026 }
040484af
JB		 2027}
2028
ab4d966c 2029static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 2030{
8fb033d7
PZ		 2031 u32 val;
2032
ab9412ba 2033 val = I915_READ(LPT_TRANSCONF);
8fb033d7 2034 val &= ~TRANS_ENABLE;
ab9412ba 2035 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 2036 /* wait for PCH transcoder off, transcoder state */
ab9412ba 2037 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 2038 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 2039
2040 /* Workaround: clear timing override bit. */
2041 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 2042 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 2043 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 2044}
2045
b24e7179 2046/**
309cfea8 2047 * intel_enable_pipe - enable a pipe, asserting requirements
0372264a 2048 * @crtc: crtc responsible for the pipe
b24e7179 2049 *
0372264a 2050 * Enable @crtc's pipe, making sure that various hardware specific requirements
b24e7179 2051 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
b24e7179 2052 */
e1fdc473 2053static void intel_enable_pipe(struct intel_crtc *crtc)
b24e7179 2054{
0372264a
PZ		 2055 struct drm_device *dev = crtc->base.dev;
2056 struct drm_i915_private *dev_priv = dev->dev_private;
2057 enum pipe pipe = crtc->pipe;
702e7a56
PZ		 2058 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
2059 pipe);
1a240d4d 2060 enum pipe pch_transcoder;
b24e7179
JB		 2061 int reg;
2062 u32 val;
2063
58c6eaa2 2064 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2065 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 2066 assert_sprites_disabled(dev_priv, pipe);
2067
681e5811 2068 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 2069 pch_transcoder = TRANSCODER_A;
2070 else
2071 pch_transcoder = pipe;
2072
b24e7179
JB		 2073 /*
2074 * A pipe without a PLL won't actually be able to drive bits from
2075 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
2076 * need the check.
2077 */
2078 if (!HAS_PCH_SPLIT(dev_priv->dev))
409ee761 2079 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
23538ef1
JN		 2080 assert_dsi_pll_enabled(dev_priv);
2081 else
2082 assert_pll_enabled(dev_priv, pipe);
040484af 2083 else {
6e3c9717 2084 if (crtc->config->has_pch_encoder) {
040484af 2085 /* if driving the PCH, we need FDI enabled */
cc391bbb 2086 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 2087 assert_fdi_tx_pll_enabled(dev_priv,
2088 (enum pipe) cpu_transcoder);
040484af
JB		 2089 }
2090 /* FIXME: assert CPU port conditions for SNB+ */
2091 }
b24e7179 2092
702e7a56 2093 reg = PIPECONF(cpu_transcoder);
b24e7179 2094 val = I915_READ(reg);
7ad25d48 2095 if (val & PIPECONF_ENABLE) {
b6b5d049
VS		 2096 WARN_ON(!((pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
2097 (pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE)));
00d70b15 2098 return;
7ad25d48 2099 }
00d70b15
CW		 2100
2101 I915_WRITE(reg, val | PIPECONF_ENABLE);
851855d8 2102 POSTING_READ(reg);
b24e7179
JB		 2103}
2104
2105/**
309cfea8 2106 * intel_disable_pipe - disable a pipe, asserting requirements
575f7ab7 2107 * @crtc: crtc whose pipes is to be disabled
b24e7179 2108 *
575f7ab7
VS		 2109 * Disable the pipe of @crtc, making sure that various hardware
2110 * specific requirements are met, if applicable, e.g. plane
2111 * disabled, panel fitter off, etc.
b24e7179
JB		 2112 *
2113 * Will wait until the pipe has shut down before returning.
2114 */
575f7ab7 2115static void intel_disable_pipe(struct intel_crtc *crtc)
b24e7179 2116{
575f7ab7 2117 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
6e3c9717 2118 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
575f7ab7 2119 enum pipe pipe = crtc->pipe;
b24e7179
JB		 2120 int reg;
2121 u32 val;
2122
2123 /*
2124 * Make sure planes won't keep trying to pump pixels to us,
2125 * or we might hang the display.
2126 */
2127 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 2128 assert_cursor_disabled(dev_priv, pipe);
19332d7a 2129 assert_sprites_disabled(dev_priv, pipe);
b24e7179 2130
702e7a56 2131 reg = PIPECONF(cpu_transcoder);
b24e7179 2132 val = I915_READ(reg);
00d70b15
CW		 2133 if ((val & PIPECONF_ENABLE) == 0)
2134 return;
2135
67adc644
VS		 2136 /*
2137 * Double wide has implications for planes
2138 * so best keep it disabled when not needed.
2139 */
6e3c9717 2140 if (crtc->config->double_wide)
67adc644
VS		 2141 val &= ~PIPECONF_DOUBLE_WIDE;
2142
2143 /* Don't disable pipe or pipe PLLs if needed */
b6b5d049
VS		 2144 if (!(pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) &&
2145 !(pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
67adc644
VS		 2146 val &= ~PIPECONF_ENABLE;
2147
2148 I915_WRITE(reg, val);
2149 if ((val & PIPECONF_ENABLE) == 0)
2150 intel_wait_for_pipe_off(crtc);
b24e7179
JB		 2151}
2152
d74362c9
KP		 2153/*
2154 * Plane regs are double buffered, going from enabled->disabled needs a
2155 * trigger in order to latch. The display address reg provides this.
2156 */
1dba99f4
VS		 2157void intel_flush_primary_plane(struct drm_i915_private *dev_priv,
2158 enum plane plane)
d74362c9 2159{
3d13ef2e
DL		 2160 struct drm_device *dev = dev_priv->dev;
2161 u32 reg = INTEL_INFO(dev)->gen >= 4 ? DSPSURF(plane) : DSPADDR(plane);
1dba99f4
VS		 2162
2163 I915_WRITE(reg, I915_READ(reg));
2164 POSTING_READ(reg);
d74362c9
KP		 2165}
2166
b24e7179 2167/**
262ca2b0 2168 * intel_enable_primary_hw_plane - enable the primary plane on a given pipe
fdd508a6
VS		 2169 * @plane: plane to be enabled
2170 * @crtc: crtc for the plane
b24e7179 2171 *
fdd508a6 2172 * Enable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2173 */
fdd508a6
VS		 2174static void intel_enable_primary_hw_plane(struct drm_plane *plane,
2175 struct drm_crtc *crtc)
b24e7179 2176{
fdd508a6
VS		 2177 struct drm_device *dev = plane->dev;
2178 struct drm_i915_private *dev_priv = dev->dev_private;
2179 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b24e7179
JB		 2180
2181 /* If the pipe isn't enabled, we can't pump pixels and may hang */
fdd508a6 2182 assert_pipe_enabled(dev_priv, intel_crtc->pipe);
b24e7179 2183
98ec7739
VS		 2184 if (intel_crtc->primary_enabled)
2185 return;
0037f71c 2186
4c445e0e 2187 intel_crtc->primary_enabled = true;
939c2fe8 2188
fdd508a6
VS		 2189 dev_priv->display.update_primary_plane(crtc, plane->fb,
2190 crtc->x, crtc->y);
33c3b0d1
VS		 2191
2192 /*
2193 * BDW signals flip done immediately if the plane
2194 * is disabled, even if the plane enable is already
2195 * armed to occur at the next vblank :(
2196 */
2197 if (IS_BROADWELL(dev))
2198 intel_wait_for_vblank(dev, intel_crtc->pipe);
b24e7179
JB		 2199}
2200
b24e7179 2201/**
262ca2b0 2202 * intel_disable_primary_hw_plane - disable the primary hardware plane
fdd508a6
VS		 2203 * @plane: plane to be disabled
2204 * @crtc: crtc for the plane
b24e7179 2205 *
fdd508a6 2206 * Disable @plane on @crtc, making sure that the pipe is running first.
b24e7179 2207 */
fdd508a6
VS		 2208static void intel_disable_primary_hw_plane(struct drm_plane *plane,
2209 struct drm_crtc *crtc)
b24e7179 2210{
fdd508a6
VS		 2211 struct drm_device *dev = plane->dev;
2212 struct drm_i915_private *dev_priv = dev->dev_private;
2213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2214
32b7eeec
MR		 2215 if (WARN_ON(!intel_crtc->active))
2216 return;
b24e7179 2217
98ec7739
VS		 2218 if (!intel_crtc->primary_enabled)
2219 return;
0037f71c 2220
4c445e0e 2221 intel_crtc->primary_enabled = false;
939c2fe8 2222
fdd508a6
VS		 2223 dev_priv->display.update_primary_plane(crtc, plane->fb,
2224 crtc->x, crtc->y);
b24e7179
JB		 2225}
2226
693db184
CW		 2227static bool need_vtd_wa(struct drm_device *dev)
2228{
2229#ifdef CONFIG_INTEL_IOMMU
2230 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
2231 return true;
2232#endif
2233 return false;
2234}
2235
50470bb0 2236unsigned int
6761dd31
TU		 2237intel_tile_height(struct drm_device *dev, uint32_t pixel_format,
2238 uint64_t fb_format_modifier)
a57ce0b2 2239{
6761dd31
TU		 2240 unsigned int tile_height;
2241 uint32_t pixel_bytes;
a57ce0b2 2242
b5d0e9bf
DL		 2243 switch (fb_format_modifier) {
2244 case DRM_FORMAT_MOD_NONE:
2245 tile_height = 1;
2246 break;
2247 case I915_FORMAT_MOD_X_TILED:
2248 tile_height = IS_GEN2(dev) ? 16 : 8;
2249 break;
2250 case I915_FORMAT_MOD_Y_TILED:
2251 tile_height = 32;
2252 break;
2253 case I915_FORMAT_MOD_Yf_TILED:
6761dd31
TU		 2254 pixel_bytes = drm_format_plane_cpp(pixel_format, 0);
2255 switch (pixel_bytes) {
b5d0e9bf 2256 default:
6761dd31 2257 case 1:
b5d0e9bf
DL		 2258 tile_height = 64;
2259 break;
6761dd31
TU		 2260 case 2:
2261 case 4:
b5d0e9bf
DL		 2262 tile_height = 32;
2263 break;
6761dd31 2264 case 8:
b5d0e9bf
DL		 2265 tile_height = 16;
2266 break;
6761dd31 2267 case 16:
b5d0e9bf
DL		 2268 WARN_ONCE(1,
2269 "128-bit pixels are not supported for display!");
2270 tile_height = 16;
2271 break;
2272 }
2273 break;
2274 default:
2275 MISSING_CASE(fb_format_modifier);
2276 tile_height = 1;
2277 break;
2278 }
091df6cb 2279
6761dd31
TU		 2280 return tile_height;
2281}
2282
2283unsigned int
2284intel_fb_align_height(struct drm_device *dev, unsigned int height,
2285 uint32_t pixel_format, uint64_t fb_format_modifier)
2286{
2287 return ALIGN(height, intel_tile_height(dev, pixel_format,
2288 fb_format_modifier));
a57ce0b2
JB		 2289}
2290
f64b98cd
TU		 2291static int
2292intel_fill_fb_ggtt_view(struct i915_ggtt_view *view, struct drm_framebuffer *fb,
2293 const struct drm_plane_state *plane_state)
2294{
50470bb0
TU		 2295 struct intel_rotation_info *info = &view->rotation_info;
2296 static const struct i915_ggtt_view rotated_view =
2297 { .type = I915_GGTT_VIEW_ROTATED };
2298
f64b98cd
TU		 2299 *view = i915_ggtt_view_normal;
2300
50470bb0
TU		 2301 if (!plane_state)
2302 return 0;
2303
121920fa 2304 if (!intel_rotation_90_or_270(plane_state->rotation))
50470bb0
TU		 2305 return 0;
2306
2307 *view = rotated_view;
2308
2309 info->height = fb->height;
2310 info->pixel_format = fb->pixel_format;
2311 info->pitch = fb->pitches[0];
2312 info->fb_modifier = fb->modifier[0];
2313
2314 if (!(info->fb_modifier == I915_FORMAT_MOD_Y_TILED ||
2315 info->fb_modifier == I915_FORMAT_MOD_Yf_TILED)) {
2316 DRM_DEBUG_KMS(
2317 "Y or Yf tiling is needed for 90/270 rotation!\n");
2318 return -EINVAL;
2319 }
2320
f64b98cd
TU		 2321 return 0;
2322}
2323
127bd2ac 2324int
850c4cdc
TU		 2325intel_pin_and_fence_fb_obj(struct drm_plane *plane,
2326 struct drm_framebuffer *fb,
82bc3b2d 2327 const struct drm_plane_state *plane_state,
a4872ba6 2328 struct intel_engine_cs *pipelined)
6b95a207 2329{
850c4cdc 2330 struct drm_device *dev = fb->dev;
ce453d81 2331 struct drm_i915_private *dev_priv = dev->dev_private;
850c4cdc 2332 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd 2333 struct i915_ggtt_view view;
6b95a207
KH		 2334 u32 alignment;
2335 int ret;
2336
ebcdd39e
MR		 2337 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2338
7b911adc
TU		 2339 switch (fb->modifier[0]) {
2340 case DRM_FORMAT_MOD_NONE:
1fada4cc
DL		 2341 if (INTEL_INFO(dev)->gen >= 9)
2342 alignment = 256 * 1024;
2343 else if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
534843da 2344 alignment = 128 * 1024;
a6c45cf0 2345 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 2346 alignment = 4 * 1024;
2347 else
2348 alignment = 64 * 1024;
6b95a207 2349 break;
7b911adc 2350 case I915_FORMAT_MOD_X_TILED:
1fada4cc
DL		 2351 if (INTEL_INFO(dev)->gen >= 9)
2352 alignment = 256 * 1024;
2353 else {
2354 /* pin() will align the object as required by fence */
2355 alignment = 0;
2356 }
6b95a207 2357 break;
7b911adc 2358 case I915_FORMAT_MOD_Y_TILED:
1327b9a1
DL		 2359 case I915_FORMAT_MOD_Yf_TILED:
2360 if (WARN_ONCE(INTEL_INFO(dev)->gen < 9,
2361 "Y tiling bo slipped through, driver bug!\n"))
2362 return -EINVAL;
2363 alignment = 1 * 1024 * 1024;
2364 break;
6b95a207 2365 default:
7b911adc
TU		 2366 MISSING_CASE(fb->modifier[0]);
2367 return -EINVAL;
6b95a207
KH		 2368 }
2369
f64b98cd
TU		 2370 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2371 if (ret)
2372 return ret;
2373
693db184
CW		 2374 /* Note that the w/a also requires 64 PTE of padding following the
2375 * bo. We currently fill all unused PTE with the shadow page and so
2376 * we should always have valid PTE following the scanout preventing
2377 * the VT-d warning.
2378 */
2379 if (need_vtd_wa(dev) && alignment < 256 * 1024)
2380 alignment = 256 * 1024;
2381
d6dd6843
PZ		 2382 /*
2383 * Global gtt pte registers are special registers which actually forward
2384 * writes to a chunk of system memory. Which means that there is no risk
2385 * that the register values disappear as soon as we call
2386 * intel_runtime_pm_put(), so it is correct to wrap only the
2387 * pin/unpin/fence and not more.
2388 */
2389 intel_runtime_pm_get(dev_priv);
2390
ce453d81 2391 dev_priv->mm.interruptible = false;
e6617330 2392 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined,
f64b98cd 2393 &view);
48b956c5 2394 if (ret)
ce453d81 2395 goto err_interruptible;
6b95a207
KH		 2396
2397 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2398 * fence, whereas 965+ only requires a fence if using
2399 * framebuffer compression. For simplicity, we always install
2400 * a fence as the cost is not that onerous.
2401 */
06d98131 2402 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 2403 if (ret)
2404 goto err_unpin;
1690e1eb 2405
9a5a53b3 2406 i915_gem_object_pin_fence(obj);
6b95a207 2407
ce453d81 2408 dev_priv->mm.interruptible = true;
d6dd6843 2409 intel_runtime_pm_put(dev_priv);
6b95a207 2410 return 0;
48b956c5
CW		 2411
2412err_unpin:
f64b98cd 2413 i915_gem_object_unpin_from_display_plane(obj, &view);
ce453d81
CW		 2414err_interruptible:
2415 dev_priv->mm.interruptible = true;
d6dd6843 2416 intel_runtime_pm_put(dev_priv);
48b956c5 2417 return ret;
6b95a207
KH		 2418}
2419
82bc3b2d
TU		 2420static void intel_unpin_fb_obj(struct drm_framebuffer *fb,
2421 const struct drm_plane_state *plane_state)
1690e1eb 2422{
82bc3b2d 2423 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
f64b98cd
TU		 2424 struct i915_ggtt_view view;
2425 int ret;
82bc3b2d 2426
ebcdd39e
MR		 2427 WARN_ON(!mutex_is_locked(&obj->base.dev->struct_mutex));
2428
f64b98cd
TU		 2429 ret = intel_fill_fb_ggtt_view(&view, fb, plane_state);
2430 WARN_ONCE(ret, "Couldn't get view from plane state!");
2431
1690e1eb 2432 i915_gem_object_unpin_fence(obj);
f64b98cd 2433 i915_gem_object_unpin_from_display_plane(obj, &view);
1690e1eb
CW		 2434}
2435
c2c75131
DV		 2436/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2437 * is assumed to be a power-of-two. */
bc752862
CW		 2438unsigned long intel_gen4_compute_page_offset(int *x, int *y,
2439 unsigned int tiling_mode,
2440 unsigned int cpp,
2441 unsigned int pitch)
c2c75131 2442{
bc752862
CW		 2443 if (tiling_mode != I915_TILING_NONE) {
2444 unsigned int tile_rows, tiles;
c2c75131 2445
bc752862
CW		 2446 tile_rows = *y / 8;
2447 *y %= 8;
c2c75131 2448
bc752862
CW		 2449 tiles = *x / (512/cpp);
2450 *x %= 512/cpp;
2451
2452 return tile_rows * pitch * 8 + tiles * 4096;
2453 } else {
2454 unsigned int offset;
2455
2456 offset = *y * pitch + *x * cpp;
2457 *y = 0;
2458 *x = (offset & 4095) / cpp;
2459 return offset & -4096;
2460 }
c2c75131
DV		 2461}
2462
b35d63fa 2463static int i9xx_format_to_fourcc(int format)
46f297fb
JB		 2464{
2465 switch (format) {
2466 case DISPPLANE_8BPP:
2467 return DRM_FORMAT_C8;
2468 case DISPPLANE_BGRX555:
2469 return DRM_FORMAT_XRGB1555;
2470 case DISPPLANE_BGRX565:
2471 return DRM_FORMAT_RGB565;
2472 default:
2473 case DISPPLANE_BGRX888:
2474 return DRM_FORMAT_XRGB8888;
2475 case DISPPLANE_RGBX888:
2476 return DRM_FORMAT_XBGR8888;
2477 case DISPPLANE_BGRX101010:
2478 return DRM_FORMAT_XRGB2101010;
2479 case DISPPLANE_RGBX101010:
2480 return DRM_FORMAT_XBGR2101010;
2481 }
2482}
2483
bc8d7dff
DL		 2484static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
2485{
2486 switch (format) {
2487 case PLANE_CTL_FORMAT_RGB_565:
2488 return DRM_FORMAT_RGB565;
2489 default:
2490 case PLANE_CTL_FORMAT_XRGB_8888:
2491 if (rgb_order) {
2492 if (alpha)
2493 return DRM_FORMAT_ABGR8888;
2494 else
2495 return DRM_FORMAT_XBGR8888;
2496 } else {
2497 if (alpha)
2498 return DRM_FORMAT_ARGB8888;
2499 else
2500 return DRM_FORMAT_XRGB8888;
2501 }
2502 case PLANE_CTL_FORMAT_XRGB_2101010:
2503 if (rgb_order)
2504 return DRM_FORMAT_XBGR2101010;
2505 else
2506 return DRM_FORMAT_XRGB2101010;
2507 }
2508}
2509
5724dbd1
DL		 2510static bool
2511intel_alloc_plane_obj(struct intel_crtc *crtc,
2512 struct intel_initial_plane_config *plane_config)
46f297fb
JB		 2513{
2514 struct drm_device *dev = crtc->base.dev;
2515 struct drm_i915_gem_object *obj = NULL;
2516 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
2d14030b 2517 struct drm_framebuffer *fb = &plane_config->fb->base;
f37b5c2b
DV		 2518 u32 base_aligned = round_down(plane_config->base, PAGE_SIZE);
2519 u32 size_aligned = round_up(plane_config->base + plane_config->size,
2520 PAGE_SIZE);
2521
2522 size_aligned -= base_aligned;
46f297fb 2523
ff2652ea
CW		 2524 if (plane_config->size == 0)
2525 return false;
2526
f37b5c2b
DV		 2527 obj = i915_gem_object_create_stolen_for_preallocated(dev,
2528 base_aligned,
2529 base_aligned,
2530 size_aligned);
46f297fb 2531 if (!obj)
484b41dd 2532 return false;
46f297fb 2533
49af449b
DL		 2534 obj->tiling_mode = plane_config->tiling;
2535 if (obj->tiling_mode == I915_TILING_X)
6bf129df 2536 obj->stride = fb->pitches[0];
46f297fb 2537
6bf129df
DL		 2538 mode_cmd.pixel_format = fb->pixel_format;
2539 mode_cmd.width = fb->width;
2540 mode_cmd.height = fb->height;
2541 mode_cmd.pitches[0] = fb->pitches[0];
18c5247e
DV		 2542 mode_cmd.modifier[0] = fb->modifier[0];
2543 mode_cmd.flags = DRM_MODE_FB_MODIFIERS;
46f297fb
JB		 2544
2545 mutex_lock(&dev->struct_mutex);
2546
6bf129df 2547 if (intel_framebuffer_init(dev, to_intel_framebuffer(fb),
484b41dd 2548 &mode_cmd, obj)) {
46f297fb
JB		 2549 DRM_DEBUG_KMS("intel fb init failed\n");
2550 goto out_unref_obj;
2551 }
2552
a071fa00 2553 obj->frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(crtc->pipe);
46f297fb 2554 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2555
2556 DRM_DEBUG_KMS("plane fb obj %p\n", obj);
2557 return true;
46f297fb
JB		 2558
2559out_unref_obj:
2560 drm_gem_object_unreference(&obj->base);
2561 mutex_unlock(&dev->struct_mutex);
484b41dd
JB		 2562 return false;
2563}
2564
afd65eb4
MR		 2565/* Update plane->state->fb to match plane->fb after driver-internal updates */
2566static void
2567update_state_fb(struct drm_plane *plane)
2568{
2569 if (plane->fb == plane->state->fb)
2570 return;
2571
2572 if (plane->state->fb)
2573 drm_framebuffer_unreference(plane->state->fb);
2574 plane->state->fb = plane->fb;
2575 if (plane->state->fb)
2576 drm_framebuffer_reference(plane->state->fb);
2577}
2578
5724dbd1
DL		 2579static void
2580intel_find_plane_obj(struct intel_crtc *intel_crtc,
2581 struct intel_initial_plane_config *plane_config)
484b41dd
JB		 2582{
2583 struct drm_device *dev = intel_crtc->base.dev;
d9ceb816 2584 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd
JB		 2585 struct drm_crtc *c;
2586 struct intel_crtc *i;
2ff8fde1 2587 struct drm_i915_gem_object *obj;
484b41dd 2588
2d14030b 2589 if (!plane_config->fb)
484b41dd
JB		 2590 return;
2591
f55548b5 2592 if (intel_alloc_plane_obj(intel_crtc, plane_config)) {
fb9981aa
DL		 2593 struct drm_plane *primary = intel_crtc->base.primary;
2594
2595 primary->fb = &plane_config->fb->base;
2596 primary->state->crtc = &intel_crtc->base;
2597 update_state_fb(primary);
2598
484b41dd 2599 return;
f55548b5 2600 }
484b41dd 2601
2d14030b 2602 kfree(plane_config->fb);
484b41dd
JB		 2603
2604 /*
2605 * Failed to alloc the obj, check to see if we should share
2606 * an fb with another CRTC instead
2607 */
70e1e0ec 2608 for_each_crtc(dev, c) {
484b41dd
JB		 2609 i = to_intel_crtc(c);
2610
2611 if (c == &intel_crtc->base)
2612 continue;
2613
2ff8fde1
MR		 2614 if (!i->active)
2615 continue;
2616
2617 obj = intel_fb_obj(c->primary->fb);
2618 if (obj == NULL)
484b41dd
JB		 2619 continue;
2620
2ff8fde1 2621 if (i915_gem_obj_ggtt_offset(obj) == plane_config->base) {
fb9981aa
DL		 2622 struct drm_plane *primary = intel_crtc->base.primary;
2623
d9ceb816
JB		 2624 if (obj->tiling_mode != I915_TILING_NONE)
2625 dev_priv->preserve_bios_swizzle = true;
2626
66e514c1 2627 drm_framebuffer_reference(c->primary->fb);
fb9981aa
DL		 2628 primary->fb = c->primary->fb;
2629 primary->state->crtc = &intel_crtc->base;
5ba76c41 2630 update_state_fb(intel_crtc->base.primary);
2ff8fde1 2631 obj->frontbuffer_bits |= INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
484b41dd
JB		 2632 break;
2633 }
2634 }
46f297fb
JB		 2635}
2636
29b9bde6
DV		 2637static void i9xx_update_primary_plane(struct drm_crtc *crtc,
2638 struct drm_framebuffer *fb,
2639 int x, int y)
81255565
JB		 2640{
2641 struct drm_device *dev = crtc->dev;
2642 struct drm_i915_private *dev_priv = dev->dev_private;
2643 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c9ba6fad 2644 struct drm_i915_gem_object *obj;
81255565 2645 int plane = intel_crtc->plane;
e506a0c6 2646 unsigned long linear_offset;
81255565 2647 u32 dspcntr;
f45651ba 2648 u32 reg = DSPCNTR(plane);
48404c1e 2649 int pixel_size;
f45651ba 2650
fdd508a6
VS		 2651 if (!intel_crtc->primary_enabled) {
2652 I915_WRITE(reg, 0);
2653 if (INTEL_INFO(dev)->gen >= 4)
2654 I915_WRITE(DSPSURF(plane), 0);
2655 else
2656 I915_WRITE(DSPADDR(plane), 0);
2657 POSTING_READ(reg);
2658 return;
2659 }
2660
c9ba6fad
VS		 2661 obj = intel_fb_obj(fb);
2662 if (WARN_ON(obj == NULL))
2663 return;
2664
2665 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2666
f45651ba
VS		 2667 dspcntr = DISPPLANE_GAMMA_ENABLE;
2668
fdd508a6 2669 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2670
2671 if (INTEL_INFO(dev)->gen < 4) {
2672 if (intel_crtc->pipe == PIPE_B)
2673 dspcntr |= DISPPLANE_SEL_PIPE_B;
2674
2675 /* pipesrc and dspsize control the size that is scaled from,
2676 * which should always be the user's requested size.
2677 */
2678 I915_WRITE(DSPSIZE(plane),
6e3c9717
ACO		 2679 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2680 (intel_crtc->config->pipe_src_w - 1));
f45651ba 2681 I915_WRITE(DSPPOS(plane), 0);
c14b0485
VS		 2682 } else if (IS_CHERRYVIEW(dev) && plane == PLANE_B) {
2683 I915_WRITE(PRIMSIZE(plane),
6e3c9717
ACO		 2684 ((intel_crtc->config->pipe_src_h - 1) << 16) |
2685 (intel_crtc->config->pipe_src_w - 1));
c14b0485
VS		 2686 I915_WRITE(PRIMPOS(plane), 0);
2687 I915_WRITE(PRIMCNSTALPHA(plane), 0);
f45651ba 2688 }
81255565 2689
57779d06
VS		 2690 switch (fb->pixel_format) {
2691 case DRM_FORMAT_C8:
81255565
JB		 2692 dspcntr |= DISPPLANE_8BPP;
2693 break;
57779d06
VS		 2694 case DRM_FORMAT_XRGB1555:
2695 case DRM_FORMAT_ARGB1555:
2696 dspcntr |= DISPPLANE_BGRX555;
81255565 2697 break;
57779d06
VS		 2698 case DRM_FORMAT_RGB565:
2699 dspcntr |= DISPPLANE_BGRX565;
2700 break;
2701 case DRM_FORMAT_XRGB8888:
2702 case DRM_FORMAT_ARGB8888:
2703 dspcntr |= DISPPLANE_BGRX888;
2704 break;
2705 case DRM_FORMAT_XBGR8888:
2706 case DRM_FORMAT_ABGR8888:
2707 dspcntr |= DISPPLANE_RGBX888;
2708 break;
2709 case DRM_FORMAT_XRGB2101010:
2710 case DRM_FORMAT_ARGB2101010:
2711 dspcntr |= DISPPLANE_BGRX101010;
2712 break;
2713 case DRM_FORMAT_XBGR2101010:
2714 case DRM_FORMAT_ABGR2101010:
2715 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2716 break;
2717 default:
baba133a 2718 BUG();
81255565 2719 }
57779d06 2720
f45651ba
VS		 2721 if (INTEL_INFO(dev)->gen >= 4 &&
2722 obj->tiling_mode != I915_TILING_NONE)
2723 dspcntr |= DISPPLANE_TILED;
81255565 2724
de1aa629
VS		 2725 if (IS_G4X(dev))
2726 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2727
b9897127 2728 linear_offset = y * fb->pitches[0] + x * pixel_size;
81255565 2729
c2c75131
DV		 2730 if (INTEL_INFO(dev)->gen >= 4) {
2731 intel_crtc->dspaddr_offset =
bc752862 2732 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2733 pixel_size,
bc752862 2734 fb->pitches[0]);
c2c75131
DV		 2735 linear_offset -= intel_crtc->dspaddr_offset;
2736 } else {
e506a0c6 2737 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2738 }
e506a0c6 2739
8e7d688b 2740 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2741 dspcntr |= DISPPLANE_ROTATE_180;
2742
6e3c9717
ACO		 2743 x += (intel_crtc->config->pipe_src_w - 1);
2744 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2745
2746 /* Finding the last pixel of the last line of the display
2747 data and adding to linear_offset*/
2748 linear_offset +=
6e3c9717
ACO		 2749 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2750 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2751 }
2752
2753 I915_WRITE(reg, dspcntr);
2754
01f2c773 2755 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2756 if (INTEL_INFO(dev)->gen >= 4) {
85ba7b7d
DV		 2757 I915_WRITE(DSPSURF(plane),
2758 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2759 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2760 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2761 } else
f343c5f6 2762 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2763 POSTING_READ(reg);
17638cd6
JB		 2764}
2765
29b9bde6
DV		 2766static void ironlake_update_primary_plane(struct drm_crtc *crtc,
2767 struct drm_framebuffer *fb,
2768 int x, int y)
17638cd6
JB		 2769{
2770 struct drm_device *dev = crtc->dev;
2771 struct drm_i915_private *dev_priv = dev->dev_private;
2772 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
c9ba6fad 2773 struct drm_i915_gem_object *obj;
17638cd6 2774 int plane = intel_crtc->plane;
e506a0c6 2775 unsigned long linear_offset;
17638cd6 2776 u32 dspcntr;
f45651ba 2777 u32 reg = DSPCNTR(plane);
48404c1e 2778 int pixel_size;
f45651ba 2779
fdd508a6
VS		 2780 if (!intel_crtc->primary_enabled) {
2781 I915_WRITE(reg, 0);
2782 I915_WRITE(DSPSURF(plane), 0);
2783 POSTING_READ(reg);
2784 return;
2785 }
2786
c9ba6fad
VS		 2787 obj = intel_fb_obj(fb);
2788 if (WARN_ON(obj == NULL))
2789 return;
2790
2791 pixel_size = drm_format_plane_cpp(fb->pixel_format, 0);
2792
f45651ba
VS		 2793 dspcntr = DISPPLANE_GAMMA_ENABLE;
2794
fdd508a6 2795 dspcntr |= DISPLAY_PLANE_ENABLE;
f45651ba
VS		 2796
2797 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2798 dspcntr |= DISPPLANE_PIPE_CSC_ENABLE;
17638cd6 2799
57779d06
VS		 2800 switch (fb->pixel_format) {
2801 case DRM_FORMAT_C8:
17638cd6
JB		 2802 dspcntr |= DISPPLANE_8BPP;
2803 break;
57779d06
VS		 2804 case DRM_FORMAT_RGB565:
2805 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2806 break;
57779d06
VS		 2807 case DRM_FORMAT_XRGB8888:
2808 case DRM_FORMAT_ARGB8888:
2809 dspcntr |= DISPPLANE_BGRX888;
2810 break;
2811 case DRM_FORMAT_XBGR8888:
2812 case DRM_FORMAT_ABGR8888:
2813 dspcntr |= DISPPLANE_RGBX888;
2814 break;
2815 case DRM_FORMAT_XRGB2101010:
2816 case DRM_FORMAT_ARGB2101010:
2817 dspcntr |= DISPPLANE_BGRX101010;
2818 break;
2819 case DRM_FORMAT_XBGR2101010:
2820 case DRM_FORMAT_ABGR2101010:
2821 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2822 break;
2823 default:
baba133a 2824 BUG();
17638cd6
JB		 2825 }
2826
2827 if (obj->tiling_mode != I915_TILING_NONE)
2828 dspcntr |= DISPPLANE_TILED;
17638cd6 2829
f45651ba 2830 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev))
1f5d76db 2831 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6 2832
b9897127 2833 linear_offset = y * fb->pitches[0] + x * pixel_size;
c2c75131 2834 intel_crtc->dspaddr_offset =
bc752862 2835 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
b9897127 2836 pixel_size,
bc752862 2837 fb->pitches[0]);
c2c75131 2838 linear_offset -= intel_crtc->dspaddr_offset;
8e7d688b 2839 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180)) {
48404c1e
SJ		 2840 dspcntr |= DISPPLANE_ROTATE_180;
2841
2842 if (!IS_HASWELL(dev) && !IS_BROADWELL(dev)) {
6e3c9717
ACO		 2843 x += (intel_crtc->config->pipe_src_w - 1);
2844 y += (intel_crtc->config->pipe_src_h - 1);
48404c1e
SJ		 2845
2846 /* Finding the last pixel of the last line of the display
2847 data and adding to linear_offset*/
2848 linear_offset +=
6e3c9717
ACO		 2849 (intel_crtc->config->pipe_src_h - 1) * fb->pitches[0] +
2850 (intel_crtc->config->pipe_src_w - 1) * pixel_size;
48404c1e
SJ		 2851 }
2852 }
2853
2854 I915_WRITE(reg, dspcntr);
17638cd6 2855
01f2c773 2856 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
85ba7b7d
DV		 2857 I915_WRITE(DSPSURF(plane),
2858 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
b3dc685e 2859 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
bc1c91eb
DL		 2860 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2861 } else {
2862 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2863 I915_WRITE(DSPLINOFF(plane), linear_offset);
2864 }
17638cd6 2865 POSTING_READ(reg);
17638cd6
JB		 2866}
2867
b321803d
DL		 2868u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
2869 uint32_t pixel_format)
2870{
2871 u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
2872
2873 /*
2874 * The stride is either expressed as a multiple of 64 bytes
2875 * chunks for linear buffers or in number of tiles for tiled
2876 * buffers.
2877 */
2878 switch (fb_modifier) {
2879 case DRM_FORMAT_MOD_NONE:
2880 return 64;
2881 case I915_FORMAT_MOD_X_TILED:
2882 if (INTEL_INFO(dev)->gen == 2)
2883 return 128;
2884 return 512;
2885 case I915_FORMAT_MOD_Y_TILED:
2886 /* No need to check for old gens and Y tiling since this is
2887 * about the display engine and those will be blocked before
2888 * we get here.
2889 */
2890 return 128;
2891 case I915_FORMAT_MOD_Yf_TILED:
2892 if (bits_per_pixel == 8)
2893 return 64;
2894 else
2895 return 128;
2896 default:
2897 MISSING_CASE(fb_modifier);
2898 return 64;
2899 }
2900}
2901
121920fa
TU		 2902unsigned long intel_plane_obj_offset(struct intel_plane *intel_plane,
2903 struct drm_i915_gem_object *obj)
2904{
2905 enum i915_ggtt_view_type view = I915_GGTT_VIEW_NORMAL;
2906
2907 if (intel_rotation_90_or_270(intel_plane->base.state->rotation))
2908 view = I915_GGTT_VIEW_ROTATED;
2909
2910 return i915_gem_obj_ggtt_offset_view(obj, view);
2911}
2912
70d21f0e
DL		 2913static void skylake_update_primary_plane(struct drm_crtc *crtc,
2914 struct drm_framebuffer *fb,
2915 int x, int y)
2916{
2917 struct drm_device *dev = crtc->dev;
2918 struct drm_i915_private *dev_priv = dev->dev_private;
2919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
70d21f0e
DL		 2920 struct drm_i915_gem_object *obj;
2921 int pipe = intel_crtc->pipe;
b321803d 2922 u32 plane_ctl, stride_div;
121920fa 2923 unsigned long surf_addr;
70d21f0e
DL		 2924
2925 if (!intel_crtc->primary_enabled) {
2926 I915_WRITE(PLANE_CTL(pipe, 0), 0);
2927 I915_WRITE(PLANE_SURF(pipe, 0), 0);
2928 POSTING_READ(PLANE_CTL(pipe, 0));
2929 return;
2930 }
2931
2932 plane_ctl = PLANE_CTL_ENABLE |
2933 PLANE_CTL_PIPE_GAMMA_ENABLE |
2934 PLANE_CTL_PIPE_CSC_ENABLE;
2935
2936 switch (fb->pixel_format) {
2937 case DRM_FORMAT_RGB565:
2938 plane_ctl |= PLANE_CTL_FORMAT_RGB_565;
2939 break;
2940 case DRM_FORMAT_XRGB8888:
2941 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2942 break;
f75fb42a
JN		 2943 case DRM_FORMAT_ARGB8888:
2944 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2945 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2946 break;
70d21f0e
DL		 2947 case DRM_FORMAT_XBGR8888:
2948 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2949 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2950 break;
f75fb42a
JN		 2951 case DRM_FORMAT_ABGR8888:
2952 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2953 plane_ctl |= PLANE_CTL_FORMAT_XRGB_8888;
2954 plane_ctl |= PLANE_CTL_ALPHA_SW_PREMULTIPLY;
2955 break;
70d21f0e
DL		 2956 case DRM_FORMAT_XRGB2101010:
2957 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2958 break;
2959 case DRM_FORMAT_XBGR2101010:
2960 plane_ctl |= PLANE_CTL_ORDER_RGBX;
2961 plane_ctl |= PLANE_CTL_FORMAT_XRGB_2101010;
2962 break;
2963 default:
2964 BUG();
2965 }
2966
30af77c4
DV		 2967 switch (fb->modifier[0]) {
2968 case DRM_FORMAT_MOD_NONE:
70d21f0e 2969 break;
30af77c4 2970 case I915_FORMAT_MOD_X_TILED:
70d21f0e 2971 plane_ctl |= PLANE_CTL_TILED_X;
b321803d
DL		 2972 break;
2973 case I915_FORMAT_MOD_Y_TILED:
2974 plane_ctl |= PLANE_CTL_TILED_Y;
2975 break;
2976 case I915_FORMAT_MOD_Yf_TILED:
2977 plane_ctl |= PLANE_CTL_TILED_YF;
70d21f0e
DL		 2978 break;
2979 default:
b321803d 2980 MISSING_CASE(fb->modifier[0]);
70d21f0e
DL		 2981 }
2982
2983 plane_ctl |= PLANE_CTL_PLANE_GAMMA_DISABLE;
8e7d688b 2984 if (crtc->primary->state->rotation == BIT(DRM_ROTATE_180))
1447dde0 2985 plane_ctl |= PLANE_CTL_ROTATE_180;
70d21f0e 2986
b321803d
DL		 2987 obj = intel_fb_obj(fb);
2988 stride_div = intel_fb_stride_alignment(dev, fb->modifier[0],
2989 fb->pixel_format);
121920fa 2990 surf_addr = intel_plane_obj_offset(to_intel_plane(crtc->primary), obj);
b321803d 2991
70d21f0e 2992 I915_WRITE(PLANE_CTL(pipe, 0), plane_ctl);
70d21f0e
DL		 2993 I915_WRITE(PLANE_POS(pipe, 0), 0);
2994 I915_WRITE(PLANE_OFFSET(pipe, 0), (y << 16) | x);
2995 I915_WRITE(PLANE_SIZE(pipe, 0),
6e3c9717
ACO		 2996 (intel_crtc->config->pipe_src_h - 1) << 16 |
2997 (intel_crtc->config->pipe_src_w - 1));
b321803d 2998 I915_WRITE(PLANE_STRIDE(pipe, 0), fb->pitches[0] / stride_div);
121920fa 2999 I915_WRITE(PLANE_SURF(pipe, 0), surf_addr);
70d21f0e
DL		 3000
3001 POSTING_READ(PLANE_SURF(pipe, 0));
3002}
3003
17638cd6
JB		 3004/* Assume fb object is pinned & idle & fenced and just update base pointers */
3005static int
3006intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
3007 int x, int y, enum mode_set_atomic state)
3008{
3009 struct drm_device *dev = crtc->dev;
3010 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 3011
6b8e6ed0
CW		 3012 if (dev_priv->display.disable_fbc)
3013 dev_priv->display.disable_fbc(dev);
81255565 3014
29b9bde6
DV		 3015 dev_priv->display.update_primary_plane(crtc, fb, x, y);
3016
3017 return 0;
81255565
JB		 3018}
3019
7514747d 3020static void intel_complete_page_flips(struct drm_device *dev)
96a02917 3021{
96a02917
VS		 3022 struct drm_crtc *crtc;
3023
70e1e0ec 3024 for_each_crtc(dev, crtc) {
96a02917
VS		 3025 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3026 enum plane plane = intel_crtc->plane;
3027
3028 intel_prepare_page_flip(dev, plane);
3029 intel_finish_page_flip_plane(dev, plane);
3030 }
7514747d
VS		 3031}
3032
3033static void intel_update_primary_planes(struct drm_device *dev)
3034{
3035 struct drm_i915_private *dev_priv = dev->dev_private;
3036 struct drm_crtc *crtc;
96a02917 3037
70e1e0ec 3038 for_each_crtc(dev, crtc) {
96a02917
VS		 3039 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3040
51fd371b 3041 drm_modeset_lock(&crtc->mutex, NULL);
947fdaad
CW		 3042 /*
3043 * FIXME: Once we have proper support for primary planes (and
3044 * disabling them without disabling the entire crtc) allow again
66e514c1 3045 * a NULL crtc->primary->fb.
947fdaad 3046 */
f4510a27 3047 if (intel_crtc->active && crtc->primary->fb)
262ca2b0 3048 dev_priv->display.update_primary_plane(crtc,
66e514c1 3049 crtc->primary->fb,
262ca2b0
MR		 3050 crtc->x,
3051 crtc->y);
51fd371b 3052 drm_modeset_unlock(&crtc->mutex);
96a02917
VS		 3053 }
3054}
3055
7514747d
VS		 3056void intel_prepare_reset(struct drm_device *dev)
3057{
f98ce92f
VS		 3058 struct drm_i915_private *dev_priv = to_i915(dev);
3059 struct intel_crtc *crtc;
3060
7514747d
VS		 3061 /* no reset support for gen2 */
3062 if (IS_GEN2(dev))
3063 return;
3064
3065 /* reset doesn't touch the display */
3066 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
3067 return;
3068
3069 drm_modeset_lock_all(dev);
f98ce92f
VS		 3070
3071 /*
3072 * Disabling the crtcs gracefully seems nicer. Also the
3073 * g33 docs say we should at least disable all the planes.
3074 */
3075 for_each_intel_crtc(dev, crtc) {
3076 if (crtc->active)
3077 dev_priv->display.crtc_disable(&crtc->base);
3078 }
7514747d
VS		 3079}
3080
3081void intel_finish_reset(struct drm_device *dev)
3082{
3083 struct drm_i915_private *dev_priv = to_i915(dev);
3084
3085 /*
3086 * Flips in the rings will be nuked by the reset,
3087 * so complete all pending flips so that user space
3088 * will get its events and not get stuck.
3089 */
3090 intel_complete_page_flips(dev);
3091
3092 /* no reset support for gen2 */
3093 if (IS_GEN2(dev))
3094 return;
3095
3096 /* reset doesn't touch the display */
3097 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev)) {
3098 /*
3099 * Flips in the rings have been nuked by the reset,
3100 * so update the base address of all primary
3101 * planes to the the last fb to make sure we're
3102 * showing the correct fb after a reset.
3103 */
3104 intel_update_primary_planes(dev);
3105 return;
3106 }
3107
3108 /*
3109 * The display has been reset as well,
3110 * so need a full re-initialization.
3111 */
3112 intel_runtime_pm_disable_interrupts(dev_priv);
3113 intel_runtime_pm_enable_interrupts(dev_priv);
3114
3115 intel_modeset_init_hw(dev);
3116
3117 spin_lock_irq(&dev_priv->irq_lock);
3118 if (dev_priv->display.hpd_irq_setup)
3119 dev_priv->display.hpd_irq_setup(dev);
3120 spin_unlock_irq(&dev_priv->irq_lock);
3121
3122 intel_modeset_setup_hw_state(dev, true);
3123
3124 intel_hpd_init(dev_priv);
3125
3126 drm_modeset_unlock_all(dev);
3127}
3128
14667a4b
CW		 3129static int
3130intel_finish_fb(struct drm_framebuffer *old_fb)
3131{
2ff8fde1 3132 struct drm_i915_gem_object *obj = intel_fb_obj(old_fb);
14667a4b
CW		 3133 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3134 bool was_interruptible = dev_priv->mm.interruptible;
3135 int ret;
3136
14667a4b
CW		 3137 /* Big Hammer, we also need to ensure that any pending
3138 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
3139 * current scanout is retired before unpinning the old
3140 * framebuffer.
3141 *
3142 * This should only fail upon a hung GPU, in which case we
3143 * can safely continue.
3144 */
3145 dev_priv->mm.interruptible = false;
3146 ret = i915_gem_object_finish_gpu(obj);
3147 dev_priv->mm.interruptible = was_interruptible;
3148
3149 return ret;
3150}
3151
7d5e3799
CW		 3152static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
3153{
3154 struct drm_device *dev = crtc->dev;
3155 struct drm_i915_private *dev_priv = dev->dev_private;
3156 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7d5e3799
CW		 3157 bool pending;
3158
3159 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
3160 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
3161 return false;
3162
5e2d7afc 3163 spin_lock_irq(&dev->event_lock);
7d5e3799 3164 pending = to_intel_crtc(crtc)->unpin_work != NULL;
5e2d7afc 3165 spin_unlock_irq(&dev->event_lock);
7d5e3799
CW		 3166
3167 return pending;
3168}
3169
e30e8f75
GP		 3170static void intel_update_pipe_size(struct intel_crtc *crtc)
3171{
3172 struct drm_device *dev = crtc->base.dev;
3173 struct drm_i915_private *dev_priv = dev->dev_private;
3174 const struct drm_display_mode *adjusted_mode;
3175
3176 if (!i915.fastboot)
3177 return;
3178
3179 /*
3180 * Update pipe size and adjust fitter if needed: the reason for this is
3181 * that in compute_mode_changes we check the native mode (not the pfit
3182 * mode) to see if we can flip rather than do a full mode set. In the
3183 * fastboot case, we'll flip, but if we don't update the pipesrc and
3184 * pfit state, we'll end up with a big fb scanned out into the wrong
3185 * sized surface.
3186 *
3187 * To fix this properly, we need to hoist the checks up into
3188 * compute_mode_changes (or above), check the actual pfit state and
3189 * whether the platform allows pfit disable with pipe active, and only
3190 * then update the pipesrc and pfit state, even on the flip path.
3191 */
3192
6e3c9717 3193 adjusted_mode = &crtc->config->base.adjusted_mode;
e30e8f75
GP		 3194
3195 I915_WRITE(PIPESRC(crtc->pipe),
3196 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
3197 (adjusted_mode->crtc_vdisplay - 1));
6e3c9717 3198 if (!crtc->config->pch_pfit.enabled &&
409ee761
ACO		 3199 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3200 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
e30e8f75
GP		 3201 I915_WRITE(PF_CTL(crtc->pipe), 0);
3202 I915_WRITE(PF_WIN_POS(crtc->pipe), 0);
3203 I915_WRITE(PF_WIN_SZ(crtc->pipe), 0);
3204 }
6e3c9717
ACO		 3205 crtc->config->pipe_src_w = adjusted_mode->crtc_hdisplay;
3206 crtc->config->pipe_src_h = adjusted_mode->crtc_vdisplay;
e30e8f75
GP		 3207}
3208
5e84e1a4
ZW		 3209static void intel_fdi_normal_train(struct drm_crtc *crtc)
3210{
3211 struct drm_device *dev = crtc->dev;
3212 struct drm_i915_private *dev_priv = dev->dev_private;
3213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3214 int pipe = intel_crtc->pipe;
3215 u32 reg, temp;
3216
3217 /* enable normal train */
3218 reg = FDI_TX_CTL(pipe);
3219 temp = I915_READ(reg);
61e499bf 3220 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 3221 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3222 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 3223 } else {
3224 temp &= ~FDI_LINK_TRAIN_NONE;
3225 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 3226 }
5e84e1a4
ZW		 3227 I915_WRITE(reg, temp);
3228
3229 reg = FDI_RX_CTL(pipe);
3230 temp = I915_READ(reg);
3231 if (HAS_PCH_CPT(dev)) {
3232 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3233 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
3234 } else {
3235 temp &= ~FDI_LINK_TRAIN_NONE;
3236 temp |= FDI_LINK_TRAIN_NONE;
3237 }
3238 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
3239
3240 /* wait one idle pattern time */
3241 POSTING_READ(reg);
3242 udelay(1000);
357555c0
JB		 3243
3244 /* IVB wants error correction enabled */
3245 if (IS_IVYBRIDGE(dev))
3246 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
3247 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 3248}
3249
8db9d77b
ZW		 3250/* The FDI link training functions for ILK/Ibexpeak. */
3251static void ironlake_fdi_link_train(struct drm_crtc *crtc)
3252{
3253 struct drm_device *dev = crtc->dev;
3254 struct drm_i915_private *dev_priv = dev->dev_private;
3255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3256 int pipe = intel_crtc->pipe;
5eddb70b 3257 u32 reg, temp, tries;
8db9d77b 3258
1c8562f6 3259 /* FDI needs bits from pipe first */
0fc932b8 3260 assert_pipe_enabled(dev_priv, pipe);
0fc932b8 3261
e1a44743
AJ		 3262 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3263 for train result */
5eddb70b
CW		 3264 reg = FDI_RX_IMR(pipe);
3265 temp = I915_READ(reg);
e1a44743
AJ		 3266 temp &= ~FDI_RX_SYMBOL_LOCK;
3267 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3268 I915_WRITE(reg, temp);
3269 I915_READ(reg);
e1a44743
AJ		 3270 udelay(150);
3271
8db9d77b 3272 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3273 reg = FDI_TX_CTL(pipe);
3274 temp = I915_READ(reg);
627eb5a3 3275 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3276 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3277 temp &= ~FDI_LINK_TRAIN_NONE;
3278 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 3279 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3280
5eddb70b
CW		 3281 reg = FDI_RX_CTL(pipe);
3282 temp = I915_READ(reg);
8db9d77b
ZW		 3283 temp &= ~FDI_LINK_TRAIN_NONE;
3284 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 3285 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3286
3287 POSTING_READ(reg);
8db9d77b
ZW		 3288 udelay(150);
3289
5b2adf89 3290 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 3291 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
3292 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
3293 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 3294
5eddb70b 3295 reg = FDI_RX_IIR(pipe);
e1a44743 3296 for (tries = 0; tries < 5; tries++) {
5eddb70b 3297 temp = I915_READ(reg);
8db9d77b
ZW		 3298 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3299
3300 if ((temp & FDI_RX_BIT_LOCK)) {
3301 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 3302 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 3303 break;
3304 }
8db9d77b 3305 }
e1a44743 3306 if (tries == 5)
5eddb70b 3307 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3308
3309 /* Train 2 */
5eddb70b
CW		 3310 reg = FDI_TX_CTL(pipe);
3311 temp = I915_READ(reg);
8db9d77b
ZW		 3312 temp &= ~FDI_LINK_TRAIN_NONE;
3313 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3314 I915_WRITE(reg, temp);
8db9d77b 3315
5eddb70b
CW		 3316 reg = FDI_RX_CTL(pipe);
3317 temp = I915_READ(reg);
8db9d77b
ZW		 3318 temp &= ~FDI_LINK_TRAIN_NONE;
3319 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 3320 I915_WRITE(reg, temp);
8db9d77b 3321
5eddb70b
CW		 3322 POSTING_READ(reg);
3323 udelay(150);
8db9d77b 3324
5eddb70b 3325 reg = FDI_RX_IIR(pipe);
e1a44743 3326 for (tries = 0; tries < 5; tries++) {
5eddb70b 3327 temp = I915_READ(reg);
8db9d77b
ZW		 3328 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3329
3330 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 3331 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 3332 DRM_DEBUG_KMS("FDI train 2 done.\n");
3333 break;
3334 }
8db9d77b 3335 }
e1a44743 3336 if (tries == 5)
5eddb70b 3337 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3338
3339 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 3340
8db9d77b
ZW		 3341}
3342
0206e353 3343static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 3344 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
3345 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
3346 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
3347 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
3348};
3349
3350/* The FDI link training functions for SNB/Cougarpoint. */
3351static void gen6_fdi_link_train(struct drm_crtc *crtc)
3352{
3353 struct drm_device *dev = crtc->dev;
3354 struct drm_i915_private *dev_priv = dev->dev_private;
3355 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3356 int pipe = intel_crtc->pipe;
fa37d39e 3357 u32 reg, temp, i, retry;
8db9d77b 3358
e1a44743
AJ		 3359 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3360 for train result */
5eddb70b
CW		 3361 reg = FDI_RX_IMR(pipe);
3362 temp = I915_READ(reg);
e1a44743
AJ		 3363 temp &= ~FDI_RX_SYMBOL_LOCK;
3364 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 3365 I915_WRITE(reg, temp);
3366
3367 POSTING_READ(reg);
e1a44743
AJ		 3368 udelay(150);
3369
8db9d77b 3370 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 3371 reg = FDI_TX_CTL(pipe);
3372 temp = I915_READ(reg);
627eb5a3 3373 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3374 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
8db9d77b
ZW		 3375 temp &= ~FDI_LINK_TRAIN_NONE;
3376 temp |= FDI_LINK_TRAIN_PATTERN_1;
3377 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3378 /* SNB-B */
3379 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 3380 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 3381
d74cf324
DV		 3382 I915_WRITE(FDI_RX_MISC(pipe),
3383 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
3384
5eddb70b
CW		 3385 reg = FDI_RX_CTL(pipe);
3386 temp = I915_READ(reg);
8db9d77b
ZW		 3387 if (HAS_PCH_CPT(dev)) {
3388 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3389 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3390 } else {
3391 temp &= ~FDI_LINK_TRAIN_NONE;
3392 temp |= FDI_LINK_TRAIN_PATTERN_1;
3393 }
5eddb70b
CW		 3394 I915_WRITE(reg, temp | FDI_RX_ENABLE);
3395
3396 POSTING_READ(reg);
8db9d77b
ZW		 3397 udelay(150);
3398
0206e353 3399 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3400 reg = FDI_TX_CTL(pipe);
3401 temp = I915_READ(reg);
8db9d77b
ZW		 3402 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3403 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3404 I915_WRITE(reg, temp);
3405
3406 POSTING_READ(reg);
8db9d77b
ZW		 3407 udelay(500);
3408
fa37d39e
SP		 3409 for (retry = 0; retry < 5; retry++) {
3410 reg = FDI_RX_IIR(pipe);
3411 temp = I915_READ(reg);
3412 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3413 if (temp & FDI_RX_BIT_LOCK) {
3414 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3415 DRM_DEBUG_KMS("FDI train 1 done.\n");
3416 break;
3417 }
3418 udelay(50);
8db9d77b 3419 }
fa37d39e
SP		 3420 if (retry < 5)
3421 break;
8db9d77b
ZW		 3422 }
3423 if (i == 4)
5eddb70b 3424 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 3425
3426 /* Train 2 */
5eddb70b
CW		 3427 reg = FDI_TX_CTL(pipe);
3428 temp = I915_READ(reg);
8db9d77b
ZW		 3429 temp &= ~FDI_LINK_TRAIN_NONE;
3430 temp |= FDI_LINK_TRAIN_PATTERN_2;
3431 if (IS_GEN6(dev)) {
3432 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3433 /* SNB-B */
3434 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
3435 }
5eddb70b 3436 I915_WRITE(reg, temp);
8db9d77b 3437
5eddb70b
CW		 3438 reg = FDI_RX_CTL(pipe);
3439 temp = I915_READ(reg);
8db9d77b
ZW		 3440 if (HAS_PCH_CPT(dev)) {
3441 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3442 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
3443 } else {
3444 temp &= ~FDI_LINK_TRAIN_NONE;
3445 temp |= FDI_LINK_TRAIN_PATTERN_2;
3446 }
5eddb70b
CW		 3447 I915_WRITE(reg, temp);
3448
3449 POSTING_READ(reg);
8db9d77b
ZW		 3450 udelay(150);
3451
0206e353 3452 for (i = 0; i < 4; i++) {
5eddb70b
CW		 3453 reg = FDI_TX_CTL(pipe);
3454 temp = I915_READ(reg);
8db9d77b
ZW		 3455 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
3456 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 3457 I915_WRITE(reg, temp);
3458
3459 POSTING_READ(reg);
8db9d77b
ZW		 3460 udelay(500);
3461
fa37d39e
SP		 3462 for (retry = 0; retry < 5; retry++) {
3463 reg = FDI_RX_IIR(pipe);
3464 temp = I915_READ(reg);
3465 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
3466 if (temp & FDI_RX_SYMBOL_LOCK) {
3467 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3468 DRM_DEBUG_KMS("FDI train 2 done.\n");
3469 break;
3470 }
3471 udelay(50);
8db9d77b 3472 }
fa37d39e
SP		 3473 if (retry < 5)
3474 break;
8db9d77b
ZW		 3475 }
3476 if (i == 4)
5eddb70b 3477 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 3478
3479 DRM_DEBUG_KMS("FDI train done.\n");
3480}
3481
357555c0
JB		 3482/* Manual link training for Ivy Bridge A0 parts */
3483static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
3484{
3485 struct drm_device *dev = crtc->dev;
3486 struct drm_i915_private *dev_priv = dev->dev_private;
3487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3488 int pipe = intel_crtc->pipe;
139ccd3f 3489 u32 reg, temp, i, j;
357555c0
JB		 3490
3491 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
3492 for train result */
3493 reg = FDI_RX_IMR(pipe);
3494 temp = I915_READ(reg);
3495 temp &= ~FDI_RX_SYMBOL_LOCK;
3496 temp &= ~FDI_RX_BIT_LOCK;
3497 I915_WRITE(reg, temp);
3498
3499 POSTING_READ(reg);
3500 udelay(150);
3501
01a415fd
DV		 3502 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
3503 I915_READ(FDI_RX_IIR(pipe)));
3504
139ccd3f
JB		 3505 /* Try each vswing and preemphasis setting twice before moving on */
3506 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
3507 /* disable first in case we need to retry */
3508 reg = FDI_TX_CTL(pipe);
3509 temp = I915_READ(reg);
3510 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
3511 temp &= ~FDI_TX_ENABLE;
3512 I915_WRITE(reg, temp);
357555c0 3513
139ccd3f
JB		 3514 reg = FDI_RX_CTL(pipe);
3515 temp = I915_READ(reg);
3516 temp &= ~FDI_LINK_TRAIN_AUTO;
3517 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3518 temp &= ~FDI_RX_ENABLE;
3519 I915_WRITE(reg, temp);
357555c0 3520
139ccd3f 3521 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 3522 reg = FDI_TX_CTL(pipe);
3523 temp = I915_READ(reg);
139ccd3f 3524 temp &= ~FDI_DP_PORT_WIDTH_MASK;
6e3c9717 3525 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
139ccd3f 3526 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 3527 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 3528 temp |= snb_b_fdi_train_param[j/2];
3529 temp |= FDI_COMPOSITE_SYNC;
3530 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 3531
139ccd3f
JB		 3532 I915_WRITE(FDI_RX_MISC(pipe),
3533 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 3534
139ccd3f 3535 reg = FDI_RX_CTL(pipe);
357555c0 3536 temp = I915_READ(reg);
139ccd3f
JB		 3537 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3538 temp |= FDI_COMPOSITE_SYNC;
3539 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 3540
139ccd3f
JB		 3541 POSTING_READ(reg);
3542 udelay(1); /* should be 0.5us */
357555c0 3543
139ccd3f
JB		 3544 for (i = 0; i < 4; i++) {
3545 reg = FDI_RX_IIR(pipe);
3546 temp = I915_READ(reg);
3547 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3548
139ccd3f
JB		 3549 if (temp & FDI_RX_BIT_LOCK ||
3550 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
3551 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
3552 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
3553 i);
3554 break;
3555 }
3556 udelay(1); /* should be 0.5us */
3557 }
3558 if (i == 4) {
3559 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
3560 continue;
3561 }
357555c0 3562
139ccd3f 3563 /* Train 2 */
357555c0
JB		 3564 reg = FDI_TX_CTL(pipe);
3565 temp = I915_READ(reg);
139ccd3f
JB		 3566 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
3567 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
3568 I915_WRITE(reg, temp);
3569
3570 reg = FDI_RX_CTL(pipe);
3571 temp = I915_READ(reg);
3572 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3573 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 3574 I915_WRITE(reg, temp);
3575
3576 POSTING_READ(reg);
139ccd3f 3577 udelay(2); /* should be 1.5us */
357555c0 3578
139ccd3f
JB		 3579 for (i = 0; i < 4; i++) {
3580 reg = FDI_RX_IIR(pipe);
3581 temp = I915_READ(reg);
3582 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 3583
139ccd3f
JB		 3584 if (temp & FDI_RX_SYMBOL_LOCK ||
3585 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
3586 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
3587 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
3588 i);
3589 goto train_done;
3590 }
3591 udelay(2); /* should be 1.5us */
357555c0 3592 }
139ccd3f
JB		 3593 if (i == 4)
3594 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 3595 }
357555c0 3596
139ccd3f 3597train_done:
357555c0
JB		 3598 DRM_DEBUG_KMS("FDI train done.\n");
3599}
3600
88cefb6c 3601static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 3602{
88cefb6c 3603 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 3604 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 3605 int pipe = intel_crtc->pipe;
5eddb70b 3606 u32 reg, temp;
79e53945 3607
c64e311e 3608
c98e9dcf 3609 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 3610 reg = FDI_RX_CTL(pipe);
3611 temp = I915_READ(reg);
627eb5a3 3612 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
6e3c9717 3613 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config->fdi_lanes);
dfd07d72 3614 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 3615 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
3616
3617 POSTING_READ(reg);
c98e9dcf
JB		 3618 udelay(200);
3619
3620 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 3621 temp = I915_READ(reg);
3622 I915_WRITE(reg, temp | FDI_PCDCLK);
3623
3624 POSTING_READ(reg);
c98e9dcf
JB		 3625 udelay(200);
3626
20749730
PZ		 3627 /* Enable CPU FDI TX PLL, always on for Ironlake */
3628 reg = FDI_TX_CTL(pipe);
3629 temp = I915_READ(reg);
3630 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
3631 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 3632
20749730
PZ		 3633 POSTING_READ(reg);
3634 udelay(100);
6be4a607 3635 }
0e23b99d
JB		 3636}
3637
88cefb6c
DV		 3638static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
3639{
3640 struct drm_device *dev = intel_crtc->base.dev;
3641 struct drm_i915_private *dev_priv = dev->dev_private;
3642 int pipe = intel_crtc->pipe;
3643 u32 reg, temp;
3644
3645 /* Switch from PCDclk to Rawclk */
3646 reg = FDI_RX_CTL(pipe);
3647 temp = I915_READ(reg);
3648 I915_WRITE(reg, temp & ~FDI_PCDCLK);
3649
3650 /* Disable CPU FDI TX PLL */
3651 reg = FDI_TX_CTL(pipe);
3652 temp = I915_READ(reg);
3653 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3654
3655 POSTING_READ(reg);
3656 udelay(100);
3657
3658 reg = FDI_RX_CTL(pipe);
3659 temp = I915_READ(reg);
3660 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
3661
3662 /* Wait for the clocks to turn off. */
3663 POSTING_READ(reg);
3664 udelay(100);
3665}
3666
0fc932b8
JB		 3667static void ironlake_fdi_disable(struct drm_crtc *crtc)
3668{
3669 struct drm_device *dev = crtc->dev;
3670 struct drm_i915_private *dev_priv = dev->dev_private;
3671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3672 int pipe = intel_crtc->pipe;
3673 u32 reg, temp;
3674
3675 /* disable CPU FDI tx and PCH FDI rx */
3676 reg = FDI_TX_CTL(pipe);
3677 temp = I915_READ(reg);
3678 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
3679 POSTING_READ(reg);
3680
3681 reg = FDI_RX_CTL(pipe);
3682 temp = I915_READ(reg);
3683 temp &= ~(0x7 << 16);
dfd07d72 3684 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3685 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
3686
3687 POSTING_READ(reg);
3688 udelay(100);
3689
3690 /* Ironlake workaround, disable clock pointer after downing FDI */
eba905b2 3691 if (HAS_PCH_IBX(dev))
6f06ce18 3692 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 3693
3694 /* still set train pattern 1 */
3695 reg = FDI_TX_CTL(pipe);
3696 temp = I915_READ(reg);
3697 temp &= ~FDI_LINK_TRAIN_NONE;
3698 temp |= FDI_LINK_TRAIN_PATTERN_1;
3699 I915_WRITE(reg, temp);
3700
3701 reg = FDI_RX_CTL(pipe);
3702 temp = I915_READ(reg);
3703 if (HAS_PCH_CPT(dev)) {
3704 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
3705 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
3706 } else {
3707 temp &= ~FDI_LINK_TRAIN_NONE;
3708 temp |= FDI_LINK_TRAIN_PATTERN_1;
3709 }
3710 /* BPC in FDI rx is consistent with that in PIPECONF */
3711 temp &= ~(0x07 << 16);
dfd07d72 3712 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 3713 I915_WRITE(reg, temp);
3714
3715 POSTING_READ(reg);
3716 udelay(100);
3717}
3718
5dce5b93
CW		 3719bool intel_has_pending_fb_unpin(struct drm_device *dev)
3720{
3721 struct intel_crtc *crtc;
3722
3723 /* Note that we don't need to be called with mode_config.lock here
3724 * as our list of CRTC objects is static for the lifetime of the
3725 * device and so cannot disappear as we iterate. Similarly, we can
3726 * happily treat the predicates as racy, atomic checks as userspace
3727 * cannot claim and pin a new fb without at least acquring the
3728 * struct_mutex and so serialising with us.
3729 */
d3fcc808 3730 for_each_intel_crtc(dev, crtc) {
5dce5b93
CW		 3731 if (atomic_read(&crtc->unpin_work_count) == 0)
3732 continue;
3733
3734 if (crtc->unpin_work)
3735 intel_wait_for_vblank(dev, crtc->pipe);
3736
3737 return true;
3738 }
3739
3740 return false;
3741}
3742
d6bbafa1
CW		 3743static void page_flip_completed(struct intel_crtc *intel_crtc)
3744{
3745 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
3746 struct intel_unpin_work *work = intel_crtc->unpin_work;
3747
3748 /* ensure that the unpin work is consistent wrt ->pending. */
3749 smp_rmb();
3750 intel_crtc->unpin_work = NULL;
3751
3752 if (work->event)
3753 drm_send_vblank_event(intel_crtc->base.dev,
3754 intel_crtc->pipe,
3755 work->event);
3756
3757 drm_crtc_vblank_put(&intel_crtc->base);
3758
3759 wake_up_all(&dev_priv->pending_flip_queue);
3760 queue_work(dev_priv->wq, &work->work);
3761
3762 trace_i915_flip_complete(intel_crtc->plane,
3763 work->pending_flip_obj);
3764}
3765
46a55d30 3766void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
e6c3a2a6 3767{
0f91128d 3768 struct drm_device *dev = crtc->dev;
5bb61643 3769 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6 3770
2c10d571 3771 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
9c787942
CW		 3772 if (WARN_ON(wait_event_timeout(dev_priv->pending_flip_queue,
3773 !intel_crtc_has_pending_flip(crtc),
3774 60*HZ) == 0)) {
3775 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2c10d571 3776
5e2d7afc 3777 spin_lock_irq(&dev->event_lock);
9c787942
CW		 3778 if (intel_crtc->unpin_work) {
3779 WARN_ONCE(1, "Removing stuck page flip\n");
3780 page_flip_completed(intel_crtc);
3781 }
5e2d7afc 3782 spin_unlock_irq(&dev->event_lock);
9c787942 3783 }
5bb61643 3784
975d568a
CW		 3785 if (crtc->primary->fb) {
3786 mutex_lock(&dev->struct_mutex);
3787 intel_finish_fb(crtc->primary->fb);
3788 mutex_unlock(&dev->struct_mutex);
3789 }
e6c3a2a6
CW		 3790}
3791
e615efe4
ED		 3792/* Program iCLKIP clock to the desired frequency */
3793static void lpt_program_iclkip(struct drm_crtc *crtc)
3794{
3795 struct drm_device *dev = crtc->dev;
3796 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3797 int clock = to_intel_crtc(crtc)->config->base.adjusted_mode.crtc_clock;
e615efe4
ED		 3798 u32 divsel, phaseinc, auxdiv, phasedir = 0;
3799 u32 temp;
3800
09153000
DV		 3801 mutex_lock(&dev_priv->dpio_lock);
3802
e615efe4
ED		 3803 /* It is necessary to ungate the pixclk gate prior to programming
3804 * the divisors, and gate it back when it is done.
3805 */
3806 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
3807
3808 /* Disable SSCCTL */
3809 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 3810 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
3811 SBI_SSCCTL_DISABLE,
3812 SBI_ICLK);
e615efe4
ED		 3813
3814 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 3815 if (clock == 20000) {
e615efe4
ED		 3816 auxdiv = 1;
3817 divsel = 0x41;
3818 phaseinc = 0x20;
3819 } else {
3820 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 3821 * but the adjusted_mode->crtc_clock in in KHz. To get the
3822 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 3823 * convert the virtual clock precision to KHz here for higher
3824 * precision.
3825 */
3826 u32 iclk_virtual_root_freq = 172800 * 1000;
3827 u32 iclk_pi_range = 64;
3828 u32 desired_divisor, msb_divisor_value, pi_value;
3829
12d7ceed 3830 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3831 msb_divisor_value = desired_divisor / iclk_pi_range;
3832 pi_value = desired_divisor % iclk_pi_range;
3833
3834 auxdiv = 0;
3835 divsel = msb_divisor_value - 2;
3836 phaseinc = pi_value;
3837 }
3838
3839 /* This should not happen with any sane values */
3840 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3841 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3842 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3843 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3844
3845 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3846 clock,
e615efe4
ED		 3847 auxdiv,
3848 divsel,
3849 phasedir,
3850 phaseinc);
3851
3852 /* Program SSCDIVINTPHASE6 */
988d6ee8 3853 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3854 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3855 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3856 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3857 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3858 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3859 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3860 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3861
3862 /* Program SSCAUXDIV */
988d6ee8 3863 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3864 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3865 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3866 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3867
3868 /* Enable modulator and associated divider */
988d6ee8 3869 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3870 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3871 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3872
3873 /* Wait for initialization time */
3874 udelay(24);
3875
3876 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3877
3878 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3879}
3880
275f01b2
DV		 3881static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3882 enum pipe pch_transcoder)
3883{
3884 struct drm_device *dev = crtc->base.dev;
3885 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 3886 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder;
275f01b2
DV		 3887
3888 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3889 I915_READ(HTOTAL(cpu_transcoder)));
3890 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3891 I915_READ(HBLANK(cpu_transcoder)));
3892 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3893 I915_READ(HSYNC(cpu_transcoder)));
3894
3895 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3896 I915_READ(VTOTAL(cpu_transcoder)));
3897 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3898 I915_READ(VBLANK(cpu_transcoder)));
3899 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3900 I915_READ(VSYNC(cpu_transcoder)));
3901 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3902 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3903}
3904
003632d9 3905static void cpt_set_fdi_bc_bifurcation(struct drm_device *dev, bool enable)
1fbc0d78
DV		 3906{
3907 struct drm_i915_private *dev_priv = dev->dev_private;
3908 uint32_t temp;
3909
3910 temp = I915_READ(SOUTH_CHICKEN1);
003632d9 3911 if (!!(temp & FDI_BC_BIFURCATION_SELECT) == enable)
1fbc0d78
DV		 3912 return;
3913
3914 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
3915 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
3916
003632d9
ACO		 3917 temp &= ~FDI_BC_BIFURCATION_SELECT;
3918 if (enable)
3919 temp |= FDI_BC_BIFURCATION_SELECT;
3920
3921 DRM_DEBUG_KMS("%sabling fdi C rx\n", enable ? "en" : "dis");
1fbc0d78
DV		 3922 I915_WRITE(SOUTH_CHICKEN1, temp);
3923 POSTING_READ(SOUTH_CHICKEN1);
3924}
3925
3926static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
3927{
3928 struct drm_device *dev = intel_crtc->base.dev;
1fbc0d78
DV		 3929
3930 switch (intel_crtc->pipe) {
3931 case PIPE_A:
3932 break;
3933 case PIPE_B:
6e3c9717 3934 if (intel_crtc->config->fdi_lanes > 2)
003632d9 3935 cpt_set_fdi_bc_bifurcation(dev, false);
1fbc0d78 3936 else
003632d9 3937 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 3938
3939 break;
3940 case PIPE_C:
003632d9 3941 cpt_set_fdi_bc_bifurcation(dev, true);
1fbc0d78
DV		 3942
3943 break;
3944 default:
3945 BUG();
3946 }
3947}
3948
f67a559d
JB		 3949/*
3950 * Enable PCH resources required for PCH ports:
3951 * - PCH PLLs
3952 * - FDI training & RX/TX
3953 * - update transcoder timings
3954 * - DP transcoding bits
3955 * - transcoder
3956 */
3957static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3958{
3959 struct drm_device *dev = crtc->dev;
3960 struct drm_i915_private *dev_priv = dev->dev_private;
3961 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3962 int pipe = intel_crtc->pipe;
ee7b9f93 3963 u32 reg, temp;
2c07245f 3964
ab9412ba 3965 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3966
1fbc0d78
DV		 3967 if (IS_IVYBRIDGE(dev))
3968 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
3969
cd986abb
DV		 3970 /* Write the TU size bits before fdi link training, so that error
3971 * detection works. */
3972 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3973 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3974
c98e9dcf 3975 /* For PCH output, training FDI link */
674cf967 3976 dev_priv->display.fdi_link_train(crtc);
2c07245f 3977
3ad8a208
DV		 3978 /* We need to program the right clock selection before writing the pixel
3979 * mutliplier into the DPLL. */
303b81e0 3980 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3981 u32 sel;
4b645f14 3982
c98e9dcf 3983 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3984 temp |= TRANS_DPLL_ENABLE(pipe);
3985 sel = TRANS_DPLLB_SEL(pipe);
6e3c9717 3986 if (intel_crtc->config->shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3987 temp |= sel;
3988 else
3989 temp &= ~sel;
c98e9dcf 3990 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3991 }
5eddb70b 3992
3ad8a208
DV		 3993 /* XXX: pch pll's can be enabled any time before we enable the PCH
3994 * transcoder, and we actually should do this to not upset any PCH
3995 * transcoder that already use the clock when we share it.
3996 *
3997 * Note that enable_shared_dpll tries to do the right thing, but
3998 * get_shared_dpll unconditionally resets the pll - we need that to have
3999 * the right LVDS enable sequence. */
85b3894f 4000 intel_enable_shared_dpll(intel_crtc);
3ad8a208 4001
d9b6cb56
JB		 4002 /* set transcoder timing, panel must allow it */
4003 assert_panel_unlocked(dev_priv, pipe);
275f01b2 4004 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 4005
303b81e0 4006 intel_fdi_normal_train(crtc);
5e84e1a4 4007
c98e9dcf 4008 /* For PCH DP, enable TRANS_DP_CTL */
6e3c9717 4009 if (HAS_PCH_CPT(dev) && intel_crtc->config->has_dp_encoder) {
dfd07d72 4010 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 4011 reg = TRANS_DP_CTL(pipe);
4012 temp = I915_READ(reg);
4013 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 4014 TRANS_DP_SYNC_MASK |
4015 TRANS_DP_BPC_MASK);
5eddb70b
CW		 4016 temp |= (TRANS_DP_OUTPUT_ENABLE |
4017 TRANS_DP_ENH_FRAMING);
9325c9f0 4018 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 4019
4020 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 4021 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 4022 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 4023 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 4024
4025 switch (intel_trans_dp_port_sel(crtc)) {
4026 case PCH_DP_B:
5eddb70b 4027 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 4028 break;
4029 case PCH_DP_C:
5eddb70b 4030 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 4031 break;
4032 case PCH_DP_D:
5eddb70b 4033 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 4034 break;
4035 default:
e95d41e1 4036 BUG();
32f9d658 4037 }
2c07245f 4038
5eddb70b 4039 I915_WRITE(reg, temp);
6be4a607 4040 }
b52eb4dc 4041
b8a4f404 4042 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 4043}
4044
1507e5bd
PZ		 4045static void lpt_pch_enable(struct drm_crtc *crtc)
4046{
4047 struct drm_device *dev = crtc->dev;
4048 struct drm_i915_private *dev_priv = dev->dev_private;
4049 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 4050 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
1507e5bd 4051
ab9412ba 4052 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 4053
8c52b5e8 4054 lpt_program_iclkip(crtc);
1507e5bd 4055
0540e488 4056 /* Set transcoder timing. */
275f01b2 4057 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 4058
937bb610 4059 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 4060}
4061
716c2e55 4062void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 4063{
e2b78267 4064 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 4065
4066 if (pll == NULL)
4067 return;
4068
3e369b76 4069 if (!(pll->config.crtc_mask & (1 << crtc->pipe))) {
1e6f2ddc 4070 WARN(1, "bad %s crtc mask\n", pll->name);
ee7b9f93
JB		 4071 return;
4072 }
4073
3e369b76
ACO		 4074 pll->config.crtc_mask &= ~(1 << crtc->pipe);
4075 if (pll->config.crtc_mask == 0) {
f4a091c7
DV		 4076 WARN_ON(pll->on);
4077 WARN_ON(pll->active);
4078 }
4079
6e3c9717 4080 crtc->config->shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 4081}
4082
190f68c5
ACO		 4083struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc,
4084 struct intel_crtc_state *crtc_state)
ee7b9f93 4085{
e2b78267 4086 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8bd31e67 4087 struct intel_shared_dpll *pll;
e2b78267 4088 enum intel_dpll_id i;
ee7b9f93 4089
98b6bd99
DV		 4090 if (HAS_PCH_IBX(dev_priv->dev)) {
4091 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 4092 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 4093 pll = &dev_priv->shared_dplls[i];
98b6bd99 4094
46edb027
DV		 4095 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
4096 crtc->base.base.id, pll->name);
98b6bd99 4097
8bd31e67 4098 WARN_ON(pll->new_config->crtc_mask);
f2a69f44 4099
98b6bd99
DV		 4100 goto found;
4101 }
4102
e72f9fbf
DV		 4103 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4104 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 4105
4106 /* Only want to check enabled timings first */
8bd31e67 4107 if (pll->new_config->crtc_mask == 0)
ee7b9f93
JB		 4108 continue;
4109
190f68c5 4110 if (memcmp(&crtc_state->dpll_hw_state,
8bd31e67
ACO		 4111 &pll->new_config->hw_state,
4112 sizeof(pll->new_config->hw_state)) == 0) {
4113 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (crtc mask 0x%08x, ative %d)\n",
1e6f2ddc 4114 crtc->base.base.id, pll->name,
8bd31e67
ACO		 4115 pll->new_config->crtc_mask,
4116 pll->active);
ee7b9f93
JB		 4117 goto found;
4118 }
4119 }
4120
4121 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 4122 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4123 pll = &dev_priv->shared_dplls[i];
8bd31e67 4124 if (pll->new_config->crtc_mask == 0) {
46edb027
DV		 4125 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
4126 crtc->base.base.id, pll->name);
ee7b9f93
JB		 4127 goto found;
4128 }
4129 }
4130
4131 return NULL;
4132
4133found:
8bd31e67 4134 if (pll->new_config->crtc_mask == 0)
190f68c5 4135 pll->new_config->hw_state = crtc_state->dpll_hw_state;
f2a69f44 4136
190f68c5 4137 crtc_state->shared_dpll = i;
46edb027
DV		 4138 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
4139 pipe_name(crtc->pipe));
ee7b9f93 4140
8bd31e67 4141 pll->new_config->crtc_mask |= 1 << crtc->pipe;
e04c7350 4142
ee7b9f93
JB		 4143 return pll;
4144}
4145
8bd31e67
ACO		 4146/**
4147 * intel_shared_dpll_start_config - start a new PLL staged config
4148 * @dev_priv: DRM device
4149 * @clear_pipes: mask of pipes that will have their PLLs freed
4150 *
4151 * Starts a new PLL staged config, copying the current config but
4152 * releasing the references of pipes specified in clear_pipes.
4153 */
4154static int intel_shared_dpll_start_config(struct drm_i915_private *dev_priv,
4155 unsigned clear_pipes)
4156{
4157 struct intel_shared_dpll *pll;
4158 enum intel_dpll_id i;
4159
4160 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4161 pll = &dev_priv->shared_dplls[i];
4162
4163 pll->new_config = kmemdup(&pll->config, sizeof pll->config,
4164 GFP_KERNEL);
4165 if (!pll->new_config)
4166 goto cleanup;
4167
4168 pll->new_config->crtc_mask &= ~clear_pipes;
4169 }
4170
4171 return 0;
4172
4173cleanup:
4174 while (--i >= 0) {
4175 pll = &dev_priv->shared_dplls[i];
f354d733 4176 kfree(pll->new_config);
8bd31e67
ACO		 4177 pll->new_config = NULL;
4178 }
4179
4180 return -ENOMEM;
4181}
4182
4183static void intel_shared_dpll_commit(struct drm_i915_private *dev_priv)
4184{
4185 struct intel_shared_dpll *pll;
4186 enum intel_dpll_id i;
4187
4188 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4189 pll = &dev_priv->shared_dplls[i];
4190
4191 WARN_ON(pll->new_config == &pll->config);
4192
4193 pll->config = *pll->new_config;
4194 kfree(pll->new_config);
4195 pll->new_config = NULL;
4196 }
4197}
4198
4199static void intel_shared_dpll_abort_config(struct drm_i915_private *dev_priv)
4200{
4201 struct intel_shared_dpll *pll;
4202 enum intel_dpll_id i;
4203
4204 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
4205 pll = &dev_priv->shared_dplls[i];
4206
4207 WARN_ON(pll->new_config == &pll->config);
4208
4209 kfree(pll->new_config);
4210 pll->new_config = NULL;
4211 }
4212}
4213
a1520318 4214static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 4215{
4216 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 4217 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 4218 u32 temp;
4219
4220 temp = I915_READ(dslreg);
4221 udelay(500);
4222 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 4223 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 4224 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 4225 }
4226}
4227
bd2e244f
JB		 4228static void skylake_pfit_enable(struct intel_crtc *crtc)
4229{
4230 struct drm_device *dev = crtc->base.dev;
4231 struct drm_i915_private *dev_priv = dev->dev_private;
4232 int pipe = crtc->pipe;
4233
6e3c9717 4234 if (crtc->config->pch_pfit.enabled) {
bd2e244f 4235 I915_WRITE(PS_CTL(pipe), PS_ENABLE);
6e3c9717
ACO		 4236 I915_WRITE(PS_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4237 I915_WRITE(PS_WIN_SZ(pipe), crtc->config->pch_pfit.size);
bd2e244f
JB		 4238 }
4239}
4240
b074cec8
JB		 4241static void ironlake_pfit_enable(struct intel_crtc *crtc)
4242{
4243 struct drm_device *dev = crtc->base.dev;
4244 struct drm_i915_private *dev_priv = dev->dev_private;
4245 int pipe = crtc->pipe;
4246
6e3c9717 4247 if (crtc->config->pch_pfit.enabled) {
b074cec8
JB		 4248 /* Force use of hard-coded filter coefficients
4249 * as some pre-programmed values are broken,
4250 * e.g. x201.
4251 */
4252 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4253 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
4254 PF_PIPE_SEL_IVB(pipe));
4255 else
4256 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
6e3c9717
ACO		 4257 I915_WRITE(PF_WIN_POS(pipe), crtc->config->pch_pfit.pos);
4258 I915_WRITE(PF_WIN_SZ(pipe), crtc->config->pch_pfit.size);
d4270e57
JB		 4259 }
4260}
4261
4a3b8769 4262static void intel_enable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4263{
4264 struct drm_device *dev = crtc->dev;
4265 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4266 struct drm_plane *plane;
bb53d4ae
VS		 4267 struct intel_plane *intel_plane;
4268
af2b653b
MR		 4269 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4270 intel_plane = to_intel_plane(plane);
bb53d4ae
VS		 4271 if (intel_plane->pipe == pipe)
4272 intel_plane_restore(&intel_plane->base);
af2b653b 4273 }
bb53d4ae
VS		 4274}
4275
0d703d4e
MR		 4276/*
4277 * Disable a plane internally without actually modifying the plane's state.
4278 * This will allow us to easily restore the plane later by just reprogramming
4279 * its state.
4280 */
4281static void disable_plane_internal(struct drm_plane *plane)
4282{
4283 struct intel_plane *intel_plane = to_intel_plane(plane);
4284 struct drm_plane_state *state =
4285 plane->funcs->atomic_duplicate_state(plane);
4286 struct intel_plane_state *intel_state = to_intel_plane_state(state);
4287
4288 intel_state->visible = false;
4289 intel_plane->commit_plane(plane, intel_state);
4290
4291 intel_plane_destroy_state(plane, state);
4292}
4293
4a3b8769 4294static void intel_disable_sprite_planes(struct drm_crtc *crtc)
bb53d4ae
VS		 4295{
4296 struct drm_device *dev = crtc->dev;
4297 enum pipe pipe = to_intel_crtc(crtc)->pipe;
af2b653b 4298 struct drm_plane *plane;
bb53d4ae
VS		 4299 struct intel_plane *intel_plane;
4300
af2b653b
MR		 4301 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
4302 intel_plane = to_intel_plane(plane);
0d703d4e
MR		 4303 if (plane->fb && intel_plane->pipe == pipe)
4304 disable_plane_internal(plane);
af2b653b 4305 }
bb53d4ae
VS		 4306}
4307
20bc8673 4308void hsw_enable_ips(struct intel_crtc *crtc)
d77e4531 4309{
cea165c3
VS		 4310 struct drm_device *dev = crtc->base.dev;
4311 struct drm_i915_private *dev_priv = dev->dev_private;
d77e4531 4312
6e3c9717 4313 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4314 return;
4315
cea165c3
VS		 4316 /* We can only enable IPS after we enable a plane and wait for a vblank */
4317 intel_wait_for_vblank(dev, crtc->pipe);
4318
d77e4531 4319 assert_plane_enabled(dev_priv, crtc->plane);
cea165c3 4320 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4321 mutex_lock(&dev_priv->rps.hw_lock);
4322 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0xc0000000));
4323 mutex_unlock(&dev_priv->rps.hw_lock);
4324 /* Quoting Art Runyan: "its not safe to expect any particular
4325 * value in IPS_CTL bit 31 after enabling IPS through the
e59150dc
JB		 4326 * mailbox." Moreover, the mailbox may return a bogus state,
4327 * so we need to just enable it and continue on.
2a114cc1
BW		 4328 */
4329 } else {
4330 I915_WRITE(IPS_CTL, IPS_ENABLE);
4331 /* The bit only becomes 1 in the next vblank, so this wait here
4332 * is essentially intel_wait_for_vblank. If we don't have this
4333 * and don't wait for vblanks until the end of crtc_enable, then
4334 * the HW state readout code will complain that the expected
4335 * IPS_CTL value is not the one we read. */
4336 if (wait_for(I915_READ_NOTRACE(IPS_CTL) & IPS_ENABLE, 50))
4337 DRM_ERROR("Timed out waiting for IPS enable\n");
4338 }
d77e4531
PZ		 4339}
4340
20bc8673 4341void hsw_disable_ips(struct intel_crtc *crtc)
d77e4531
PZ		 4342{
4343 struct drm_device *dev = crtc->base.dev;
4344 struct drm_i915_private *dev_priv = dev->dev_private;
4345
6e3c9717 4346 if (!crtc->config->ips_enabled)
d77e4531
PZ		 4347 return;
4348
4349 assert_plane_enabled(dev_priv, crtc->plane);
23d0b130 4350 if (IS_BROADWELL(dev)) {
2a114cc1
BW		 4351 mutex_lock(&dev_priv->rps.hw_lock);
4352 WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
4353 mutex_unlock(&dev_priv->rps.hw_lock);
23d0b130
BW		 4354 /* wait for pcode to finish disabling IPS, which may take up to 42ms */
4355 if (wait_for((I915_READ(IPS_CTL) & IPS_ENABLE) == 0, 42))
4356 DRM_ERROR("Timed out waiting for IPS disable\n");
e59150dc 4357 } else {
2a114cc1 4358 I915_WRITE(IPS_CTL, 0);
e59150dc
JB		 4359 POSTING_READ(IPS_CTL);
4360 }
d77e4531
PZ		 4361
4362 /* We need to wait for a vblank before we can disable the plane. */
4363 intel_wait_for_vblank(dev, crtc->pipe);
4364}
4365
4366/** Loads the palette/gamma unit for the CRTC with the prepared values */
4367static void intel_crtc_load_lut(struct drm_crtc *crtc)
4368{
4369 struct drm_device *dev = crtc->dev;
4370 struct drm_i915_private *dev_priv = dev->dev_private;
4371 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4372 enum pipe pipe = intel_crtc->pipe;
4373 int palreg = PALETTE(pipe);
4374 int i;
4375 bool reenable_ips = false;
4376
4377 /* The clocks have to be on to load the palette. */
83d65738 4378 if (!crtc->state->enable || !intel_crtc->active)
d77e4531
PZ		 4379 return;
4380
4381 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
409ee761 4382 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI))
d77e4531
PZ		 4383 assert_dsi_pll_enabled(dev_priv);
4384 else
4385 assert_pll_enabled(dev_priv, pipe);
4386 }
4387
4388 /* use legacy palette for Ironlake */
7a1db49a 4389 if (!HAS_GMCH_DISPLAY(dev))
d77e4531
PZ		 4390 palreg = LGC_PALETTE(pipe);
4391
4392 /* Workaround : Do not read or write the pipe palette/gamma data while
4393 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
4394 */
6e3c9717 4395 if (IS_HASWELL(dev) && intel_crtc->config->ips_enabled &&
d77e4531
PZ		 4396 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
4397 GAMMA_MODE_MODE_SPLIT)) {
4398 hsw_disable_ips(intel_crtc);
4399 reenable_ips = true;
4400 }
4401
4402 for (i = 0; i < 256; i++) {
4403 I915_WRITE(palreg + 4 * i,
4404 (intel_crtc->lut_r[i] << 16) |
4405 (intel_crtc->lut_g[i] << 8) |
4406 intel_crtc->lut_b[i]);
4407 }
4408
4409 if (reenable_ips)
4410 hsw_enable_ips(intel_crtc);
4411}
4412
d3eedb1a
VS		 4413static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
4414{
4415 if (!enable && intel_crtc->overlay) {
4416 struct drm_device *dev = intel_crtc->base.dev;
4417 struct drm_i915_private *dev_priv = dev->dev_private;
4418
4419 mutex_lock(&dev->struct_mutex);
4420 dev_priv->mm.interruptible = false;
4421 (void) intel_overlay_switch_off(intel_crtc->overlay);
4422 dev_priv->mm.interruptible = true;
4423 mutex_unlock(&dev->struct_mutex);
4424 }
4425
4426 /* Let userspace switch the overlay on again. In most cases userspace
4427 * has to recompute where to put it anyway.
4428 */
4429}
4430
d3eedb1a 4431static void intel_crtc_enable_planes(struct drm_crtc *crtc)
a5c4d7bc
VS		 4432{
4433 struct drm_device *dev = crtc->dev;
a5c4d7bc
VS		 4434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4435 int pipe = intel_crtc->pipe;
a5c4d7bc 4436
fdd508a6 4437 intel_enable_primary_hw_plane(crtc->primary, crtc);
4a3b8769 4438 intel_enable_sprite_planes(crtc);
a5c4d7bc 4439 intel_crtc_update_cursor(crtc, true);
d3eedb1a 4440 intel_crtc_dpms_overlay(intel_crtc, true);
a5c4d7bc
VS		 4441
4442 hsw_enable_ips(intel_crtc);
4443
4444 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4445 intel_fbc_update(dev);
a5c4d7bc 4446 mutex_unlock(&dev->struct_mutex);
f99d7069
DV		 4447
4448 /*
4449 * FIXME: Once we grow proper nuclear flip support out of this we need
4450 * to compute the mask of flip planes precisely. For the time being
4451 * consider this a flip from a NULL plane.
4452 */
4453 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4454}
4455
d3eedb1a 4456static void intel_crtc_disable_planes(struct drm_crtc *crtc)
a5c4d7bc
VS		 4457{
4458 struct drm_device *dev = crtc->dev;
4459 struct drm_i915_private *dev_priv = dev->dev_private;
4460 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4461 int pipe = intel_crtc->pipe;
a5c4d7bc
VS		 4462
4463 intel_crtc_wait_for_pending_flips(crtc);
a5c4d7bc 4464
e35fef21 4465 if (dev_priv->fbc.crtc == intel_crtc)
7ff0ebcc 4466 intel_fbc_disable(dev);
a5c4d7bc
VS		 4467
4468 hsw_disable_ips(intel_crtc);
4469
d3eedb1a 4470 intel_crtc_dpms_overlay(intel_crtc, false);
a5c4d7bc 4471 intel_crtc_update_cursor(crtc, false);
4a3b8769 4472 intel_disable_sprite_planes(crtc);
fdd508a6 4473 intel_disable_primary_hw_plane(crtc->primary, crtc);
f98551ae 4474
f99d7069
DV		 4475 /*
4476 * FIXME: Once we grow proper nuclear flip support out of this we need
4477 * to compute the mask of flip planes precisely. For the time being
4478 * consider this a flip to a NULL plane.
4479 */
4480 intel_frontbuffer_flip(dev, INTEL_FRONTBUFFER_ALL_MASK(pipe));
a5c4d7bc
VS		 4481}
4482
f67a559d
JB		 4483static void ironlake_crtc_enable(struct drm_crtc *crtc)
4484{
4485 struct drm_device *dev = crtc->dev;
4486 struct drm_i915_private *dev_priv = dev->dev_private;
4487 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4488 struct intel_encoder *encoder;
f67a559d 4489 int pipe = intel_crtc->pipe;
f67a559d 4490
83d65738 4491 WARN_ON(!crtc->state->enable);
08a48469 4492
f67a559d
JB		 4493 if (intel_crtc->active)
4494 return;
4495
6e3c9717 4496 if (intel_crtc->config->has_pch_encoder)
b14b1055
DV		 4497 intel_prepare_shared_dpll(intel_crtc);
4498
6e3c9717 4499 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4500 intel_dp_set_m_n(intel_crtc, M1_N1);
29407aab
DV		 4501
4502 intel_set_pipe_timings(intel_crtc);
4503
6e3c9717 4504 if (intel_crtc->config->has_pch_encoder) {
29407aab 4505 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4506 &intel_crtc->config->fdi_m_n, NULL);
29407aab
DV		 4507 }
4508
4509 ironlake_set_pipeconf(crtc);
4510
f67a559d 4511 intel_crtc->active = true;
8664281b 4512
a72e4c9f
DV		 4513 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4514 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
8664281b 4515
f6736a1a 4516 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 4517 if (encoder->pre_enable)
4518 encoder->pre_enable(encoder);
f67a559d 4519
6e3c9717 4520 if (intel_crtc->config->has_pch_encoder) {
fff367c7
DV		 4521 /* Note: FDI PLL enabling _must_ be done before we enable the
4522 * cpu pipes, hence this is separate from all the other fdi/pch
4523 * enabling. */
88cefb6c 4524 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 4525 } else {
4526 assert_fdi_tx_disabled(dev_priv, pipe);
4527 assert_fdi_rx_disabled(dev_priv, pipe);
4528 }
f67a559d 4529
b074cec8 4530 ironlake_pfit_enable(intel_crtc);
f67a559d 4531
9c54c0dd
JB		 4532 /*
4533 * On ILK+ LUT must be loaded before the pipe is running but with
4534 * clocks enabled
4535 */
4536 intel_crtc_load_lut(crtc);
4537
f37fcc2a 4538 intel_update_watermarks(crtc);
e1fdc473 4539 intel_enable_pipe(intel_crtc);
f67a559d 4540
6e3c9717 4541 if (intel_crtc->config->has_pch_encoder)
f67a559d 4542 ironlake_pch_enable(crtc);
c98e9dcf 4543
f9b61ff6
DV		 4544 assert_vblank_disabled(crtc);
4545 drm_crtc_vblank_on(crtc);
4546
fa5c73b1
DV		 4547 for_each_encoder_on_crtc(dev, crtc, encoder)
4548 encoder->enable(encoder);
61b77ddd
DV		 4549
4550 if (HAS_PCH_CPT(dev))
a1520318 4551 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100 4552
d3eedb1a 4553 intel_crtc_enable_planes(crtc);
6be4a607
JB		 4554}
4555
42db64ef
PZ		 4556/* IPS only exists on ULT machines and is tied to pipe A. */
4557static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
4558{
f5adf94e 4559 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 4560}
4561
e4916946
PZ		 4562/*
4563 * This implements the workaround described in the "notes" section of the mode
4564 * set sequence documentation. When going from no pipes or single pipe to
4565 * multiple pipes, and planes are enabled after the pipe, we need to wait at
4566 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
4567 */
4568static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
4569{
4570 struct drm_device *dev = crtc->base.dev;
4571 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
4572
4573 /* We want to get the other_active_crtc only if there's only 1 other
4574 * active crtc. */
d3fcc808 4575 for_each_intel_crtc(dev, crtc_it) {
e4916946
PZ		 4576 if (!crtc_it->active || crtc_it == crtc)
4577 continue;
4578
4579 if (other_active_crtc)
4580 return;
4581
4582 other_active_crtc = crtc_it;
4583 }
4584 if (!other_active_crtc)
4585 return;
4586
4587 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4588 intel_wait_for_vblank(dev, other_active_crtc->pipe);
4589}
4590
4f771f10
PZ		 4591static void haswell_crtc_enable(struct drm_crtc *crtc)
4592{
4593 struct drm_device *dev = crtc->dev;
4594 struct drm_i915_private *dev_priv = dev->dev_private;
4595 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4596 struct intel_encoder *encoder;
4597 int pipe = intel_crtc->pipe;
4f771f10 4598
83d65738 4599 WARN_ON(!crtc->state->enable);
4f771f10
PZ		 4600
4601 if (intel_crtc->active)
4602 return;
4603
df8ad70c
DV		 4604 if (intel_crtc_to_shared_dpll(intel_crtc))
4605 intel_enable_shared_dpll(intel_crtc);
4606
6e3c9717 4607 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 4608 intel_dp_set_m_n(intel_crtc, M1_N1);
229fca97
DV		 4609
4610 intel_set_pipe_timings(intel_crtc);
4611
6e3c9717
ACO		 4612 if (intel_crtc->config->cpu_transcoder != TRANSCODER_EDP) {
4613 I915_WRITE(PIPE_MULT(intel_crtc->config->cpu_transcoder),
4614 intel_crtc->config->pixel_multiplier - 1);
ebb69c95
CT		 4615 }
4616
6e3c9717 4617 if (intel_crtc->config->has_pch_encoder) {
229fca97 4618 intel_cpu_transcoder_set_m_n(intel_crtc,
6e3c9717 4619 &intel_crtc->config->fdi_m_n, NULL);
229fca97
DV		 4620 }
4621
4622 haswell_set_pipeconf(crtc);
4623
4624 intel_set_pipe_csc(crtc);
4625
4f771f10 4626 intel_crtc->active = true;
8664281b 4627
a72e4c9f 4628 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4f771f10
PZ		 4629 for_each_encoder_on_crtc(dev, crtc, encoder)
4630 if (encoder->pre_enable)
4631 encoder->pre_enable(encoder);
4632
6e3c9717 4633 if (intel_crtc->config->has_pch_encoder) {
a72e4c9f
DV		 4634 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4635 true);
4fe9467d
ID		 4636 dev_priv->display.fdi_link_train(crtc);
4637 }
4638
1f544388 4639 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 4640
bd2e244f
JB		 4641 if (IS_SKYLAKE(dev))
4642 skylake_pfit_enable(intel_crtc);
4643 else
4644 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 4645
4646 /*
4647 * On ILK+ LUT must be loaded before the pipe is running but with
4648 * clocks enabled
4649 */
4650 intel_crtc_load_lut(crtc);
4651
1f544388 4652 intel_ddi_set_pipe_settings(crtc);
8228c251 4653 intel_ddi_enable_transcoder_func(crtc);
4f771f10 4654
f37fcc2a 4655 intel_update_watermarks(crtc);
e1fdc473 4656 intel_enable_pipe(intel_crtc);
42db64ef 4657
6e3c9717 4658 if (intel_crtc->config->has_pch_encoder)
1507e5bd 4659 lpt_pch_enable(crtc);
4f771f10 4660
6e3c9717 4661 if (intel_crtc->config->dp_encoder_is_mst)
0e32b39c
DA		 4662 intel_ddi_set_vc_payload_alloc(crtc, true);
4663
f9b61ff6
DV		 4664 assert_vblank_disabled(crtc);
4665 drm_crtc_vblank_on(crtc);
4666
8807e55b 4667 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 4668 encoder->enable(encoder);
8807e55b
JN		 4669 intel_opregion_notify_encoder(encoder, true);
4670 }
4f771f10 4671
e4916946
PZ		 4672 /* If we change the relative order between pipe/planes enabling, we need
4673 * to change the workaround. */
4674 haswell_mode_set_planes_workaround(intel_crtc);
d3eedb1a 4675 intel_crtc_enable_planes(crtc);
4f771f10
PZ		 4676}
4677
bd2e244f
JB		 4678static void skylake_pfit_disable(struct intel_crtc *crtc)
4679{
4680 struct drm_device *dev = crtc->base.dev;
4681 struct drm_i915_private *dev_priv = dev->dev_private;
4682 int pipe = crtc->pipe;
4683
4684 /* To avoid upsetting the power well on haswell only disable the pfit if
4685 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4686 if (crtc->config->pch_pfit.enabled) {
bd2e244f
JB		 4687 I915_WRITE(PS_CTL(pipe), 0);
4688 I915_WRITE(PS_WIN_POS(pipe), 0);
4689 I915_WRITE(PS_WIN_SZ(pipe), 0);
4690 }
4691}
4692
3f8dce3a
DV		 4693static void ironlake_pfit_disable(struct intel_crtc *crtc)
4694{
4695 struct drm_device *dev = crtc->base.dev;
4696 struct drm_i915_private *dev_priv = dev->dev_private;
4697 int pipe = crtc->pipe;
4698
4699 /* To avoid upsetting the power well on haswell only disable the pfit if
4700 * it's in use. The hw state code will make sure we get this right. */
6e3c9717 4701 if (crtc->config->pch_pfit.enabled) {
3f8dce3a
DV		 4702 I915_WRITE(PF_CTL(pipe), 0);
4703 I915_WRITE(PF_WIN_POS(pipe), 0);
4704 I915_WRITE(PF_WIN_SZ(pipe), 0);
4705 }
4706}
4707
6be4a607
JB		 4708static void ironlake_crtc_disable(struct drm_crtc *crtc)
4709{
4710 struct drm_device *dev = crtc->dev;
4711 struct drm_i915_private *dev_priv = dev->dev_private;
4712 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 4713 struct intel_encoder *encoder;
6be4a607 4714 int pipe = intel_crtc->pipe;
5eddb70b 4715 u32 reg, temp;
b52eb4dc 4716
f7abfe8b
CW		 4717 if (!intel_crtc->active)
4718 return;
4719
d3eedb1a 4720 intel_crtc_disable_planes(crtc);
a5c4d7bc 4721
ea9d758d
DV		 4722 for_each_encoder_on_crtc(dev, crtc, encoder)
4723 encoder->disable(encoder);
4724
f9b61ff6
DV		 4725 drm_crtc_vblank_off(crtc);
4726 assert_vblank_disabled(crtc);
4727
6e3c9717 4728 if (intel_crtc->config->has_pch_encoder)
a72e4c9f 4729 intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
d925c59a 4730
575f7ab7 4731 intel_disable_pipe(intel_crtc);
32f9d658 4732
3f8dce3a 4733 ironlake_pfit_disable(intel_crtc);
2c07245f 4734
bf49ec8c
DV		 4735 for_each_encoder_on_crtc(dev, crtc, encoder)
4736 if (encoder->post_disable)
4737 encoder->post_disable(encoder);
2c07245f 4738
6e3c9717 4739 if (intel_crtc->config->has_pch_encoder) {
d925c59a 4740 ironlake_fdi_disable(crtc);
913d8d11 4741
d925c59a 4742 ironlake_disable_pch_transcoder(dev_priv, pipe);
6be4a607 4743
d925c59a
DV		 4744 if (HAS_PCH_CPT(dev)) {
4745 /* disable TRANS_DP_CTL */
4746 reg = TRANS_DP_CTL(pipe);
4747 temp = I915_READ(reg);
4748 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
4749 TRANS_DP_PORT_SEL_MASK);
4750 temp |= TRANS_DP_PORT_SEL_NONE;
4751 I915_WRITE(reg, temp);
4752
4753 /* disable DPLL_SEL */
4754 temp = I915_READ(PCH_DPLL_SEL);
11887397 4755 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 4756 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 4757 }
e3421a18 4758
d925c59a 4759 /* disable PCH DPLL */
e72f9fbf 4760 intel_disable_shared_dpll(intel_crtc);
8db9d77b 4761
d925c59a
DV		 4762 ironlake_fdi_pll_disable(intel_crtc);
4763 }
6b383a7f 4764
f7abfe8b 4765 intel_crtc->active = false;
46ba614c 4766 intel_update_watermarks(crtc);
d1ebd816
BW		 4767
4768 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4769 intel_fbc_update(dev);
d1ebd816 4770 mutex_unlock(&dev->struct_mutex);
6be4a607 4771}
1b3c7a47 4772
4f771f10 4773static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 4774{
4f771f10
PZ		 4775 struct drm_device *dev = crtc->dev;
4776 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 4777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10 4778 struct intel_encoder *encoder;
6e3c9717 4779 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee7b9f93 4780
4f771f10
PZ		 4781 if (!intel_crtc->active)
4782 return;
4783
d3eedb1a 4784 intel_crtc_disable_planes(crtc);
dda9a66a 4785
8807e55b
JN		 4786 for_each_encoder_on_crtc(dev, crtc, encoder) {
4787 intel_opregion_notify_encoder(encoder, false);
4f771f10 4788 encoder->disable(encoder);
8807e55b 4789 }
4f771f10 4790
f9b61ff6
DV		 4791 drm_crtc_vblank_off(crtc);
4792 assert_vblank_disabled(crtc);
4793
6e3c9717 4794 if (intel_crtc->config->has_pch_encoder)
a72e4c9f
DV		 4795 intel_set_pch_fifo_underrun_reporting(dev_priv, TRANSCODER_A,
4796 false);
575f7ab7 4797 intel_disable_pipe(intel_crtc);
4f771f10 4798
6e3c9717 4799 if (intel_crtc->config->dp_encoder_is_mst)
a4bf214f
VS		 4800 intel_ddi_set_vc_payload_alloc(crtc, false);
4801
ad80a810 4802 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 4803
bd2e244f
JB		 4804 if (IS_SKYLAKE(dev))
4805 skylake_pfit_disable(intel_crtc);
4806 else
4807 ironlake_pfit_disable(intel_crtc);
4f771f10 4808
1f544388 4809 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10 4810
6e3c9717 4811 if (intel_crtc->config->has_pch_encoder) {
ab4d966c 4812 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 4813 intel_ddi_fdi_disable(crtc);
83616634 4814 }
4f771f10 4815
97b040aa
ID		 4816 for_each_encoder_on_crtc(dev, crtc, encoder)
4817 if (encoder->post_disable)
4818 encoder->post_disable(encoder);
4819
4f771f10 4820 intel_crtc->active = false;
46ba614c 4821 intel_update_watermarks(crtc);
4f771f10
PZ		 4822
4823 mutex_lock(&dev->struct_mutex);
7ff0ebcc 4824 intel_fbc_update(dev);
4f771f10 4825 mutex_unlock(&dev->struct_mutex);
df8ad70c
DV		 4826
4827 if (intel_crtc_to_shared_dpll(intel_crtc))
4828 intel_disable_shared_dpll(intel_crtc);
4f771f10
PZ		 4829}
4830
ee7b9f93
JB		 4831static void ironlake_crtc_off(struct drm_crtc *crtc)
4832{
4833 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 4834 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 4835}
4836
6441ab5f 4837
2dd24552
JB		 4838static void i9xx_pfit_enable(struct intel_crtc *crtc)
4839{
4840 struct drm_device *dev = crtc->base.dev;
4841 struct drm_i915_private *dev_priv = dev->dev_private;
6e3c9717 4842 struct intel_crtc_state *pipe_config = crtc->config;
2dd24552 4843
681a8504 4844 if (!pipe_config->gmch_pfit.control)
2dd24552
JB		 4845 return;
4846
2dd24552 4847 /*
c0b03411
DV		 4848 * The panel fitter should only be adjusted whilst the pipe is disabled,
4849 * according to register description and PRM.
2dd24552 4850 */
c0b03411
DV		 4851 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
4852 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 4853
b074cec8
JB		 4854 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
4855 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 4856
4857 /* Border color in case we don't scale up to the full screen. Black by
4858 * default, change to something else for debugging. */
4859 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 4860}
4861
d05410f9
DA		 4862static enum intel_display_power_domain port_to_power_domain(enum port port)
4863{
4864 switch (port) {
4865 case PORT_A:
4866 return POWER_DOMAIN_PORT_DDI_A_4_LANES;
4867 case PORT_B:
4868 return POWER_DOMAIN_PORT_DDI_B_4_LANES;
4869 case PORT_C:
4870 return POWER_DOMAIN_PORT_DDI_C_4_LANES;
4871 case PORT_D:
4872 return POWER_DOMAIN_PORT_DDI_D_4_LANES;
4873 default:
4874 WARN_ON_ONCE(1);
4875 return POWER_DOMAIN_PORT_OTHER;
4876 }
4877}
4878
77d22dca
ID		 4879#define for_each_power_domain(domain, mask) \
4880 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
4881 if ((1 << (domain)) & (mask))
4882
319be8ae
ID		 4883enum intel_display_power_domain
4884intel_display_port_power_domain(struct intel_encoder *intel_encoder)
4885{
4886 struct drm_device *dev = intel_encoder->base.dev;
4887 struct intel_digital_port *intel_dig_port;
4888
4889 switch (intel_encoder->type) {
4890 case INTEL_OUTPUT_UNKNOWN:
4891 /* Only DDI platforms should ever use this output type */
4892 WARN_ON_ONCE(!HAS_DDI(dev));
4893 case INTEL_OUTPUT_DISPLAYPORT:
4894 case INTEL_OUTPUT_HDMI:
4895 case INTEL_OUTPUT_EDP:
4896 intel_dig_port = enc_to_dig_port(&intel_encoder->base);
d05410f9 4897 return port_to_power_domain(intel_dig_port->port);
0e32b39c
DA		 4898 case INTEL_OUTPUT_DP_MST:
4899 intel_dig_port = enc_to_mst(&intel_encoder->base)->primary;
4900 return port_to_power_domain(intel_dig_port->port);
319be8ae
ID		 4901 case INTEL_OUTPUT_ANALOG:
4902 return POWER_DOMAIN_PORT_CRT;
4903 case INTEL_OUTPUT_DSI:
4904 return POWER_DOMAIN_PORT_DSI;
4905 default:
4906 return POWER_DOMAIN_PORT_OTHER;
4907 }
4908}
4909
4910static unsigned long get_crtc_power_domains(struct drm_crtc *crtc)
77d22dca 4911{
319be8ae
ID		 4912 struct drm_device *dev = crtc->dev;
4913 struct intel_encoder *intel_encoder;
4914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4915 enum pipe pipe = intel_crtc->pipe;
77d22dca
ID		 4916 unsigned long mask;
4917 enum transcoder transcoder;
4918
4919 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe);
4920
4921 mask = BIT(POWER_DOMAIN_PIPE(pipe));
4922 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder));
6e3c9717
ACO		 4923 if (intel_crtc->config->pch_pfit.enabled ||
4924 intel_crtc->config->pch_pfit.force_thru)
77d22dca
ID		 4925 mask |= BIT(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
4926
319be8ae
ID		 4927 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4928 mask |= BIT(intel_display_port_power_domain(intel_encoder));
4929
77d22dca
ID		 4930 return mask;
4931}
4932
77d22dca
ID		 4933static void modeset_update_crtc_power_domains(struct drm_device *dev)
4934{
4935 struct drm_i915_private *dev_priv = dev->dev_private;
4936 unsigned long pipe_domains[I915_MAX_PIPES] = { 0, };
4937 struct intel_crtc *crtc;
4938
4939 /*
4940 * First get all needed power domains, then put all unneeded, to avoid
4941 * any unnecessary toggling of the power wells.
4942 */
d3fcc808 4943 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 4944 enum intel_display_power_domain domain;
4945
83d65738 4946 if (!crtc->base.state->enable)
77d22dca
ID		 4947 continue;
4948
319be8ae 4949 pipe_domains[crtc->pipe] = get_crtc_power_domains(&crtc->base);
77d22dca
ID		 4950
4951 for_each_power_domain(domain, pipe_domains[crtc->pipe])
4952 intel_display_power_get(dev_priv, domain);
4953 }
4954
50f6e502
VS		 4955 if (dev_priv->display.modeset_global_resources)
4956 dev_priv->display.modeset_global_resources(dev);
4957
d3fcc808 4958 for_each_intel_crtc(dev, crtc) {
77d22dca
ID		 4959 enum intel_display_power_domain domain;
4960
4961 for_each_power_domain(domain, crtc->enabled_power_domains)
4962 intel_display_power_put(dev_priv, domain);
4963
4964 crtc->enabled_power_domains = pipe_domains[crtc->pipe];
4965 }
4966
4967 intel_display_set_init_power(dev_priv, false);
4968}
4969
dfcab17e 4970/* returns HPLL frequency in kHz */
f8bf63fd 4971static int valleyview_get_vco(struct drm_i915_private *dev_priv)
30a970c6 4972{
586f49dc 4973 int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
30a970c6 4974
586f49dc
JB		 4975 /* Obtain SKU information */
4976 mutex_lock(&dev_priv->dpio_lock);
4977 hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
4978 CCK_FUSE_HPLL_FREQ_MASK;
4979 mutex_unlock(&dev_priv->dpio_lock);
30a970c6 4980
dfcab17e 4981 return vco_freq[hpll_freq] * 1000;
30a970c6
JB		 4982}
4983
f8bf63fd
VS		 4984static void vlv_update_cdclk(struct drm_device *dev)
4985{
4986 struct drm_i915_private *dev_priv = dev->dev_private;
4987
4988 dev_priv->vlv_cdclk_freq = dev_priv->display.get_display_clock_speed(dev);
43dc52c3 4989 DRM_DEBUG_DRIVER("Current CD clock rate: %d kHz\n",
f8bf63fd
VS		 4990 dev_priv->vlv_cdclk_freq);
4991
4992 /*
4993 * Program the gmbus_freq based on the cdclk frequency.
4994 * BSpec erroneously claims we should aim for 4MHz, but
4995 * in fact 1MHz is the correct frequency.
4996 */
6be1e3d3 4997 I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->vlv_cdclk_freq, 1000));
f8bf63fd
VS		 4998}
4999
30a970c6
JB		 5000/* Adjust CDclk dividers to allow high res or save power if possible */
5001static void valleyview_set_cdclk(struct drm_device *dev, int cdclk)
5002{
5003 struct drm_i915_private *dev_priv = dev->dev_private;
5004 u32 val, cmd;
5005
d197b7d3 5006 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
d60c4473 5007
dfcab17e 5008 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
30a970c6 5009 cmd = 2;
dfcab17e 5010 else if (cdclk == 266667)
30a970c6
JB		 5011 cmd = 1;
5012 else
5013 cmd = 0;
5014
5015 mutex_lock(&dev_priv->rps.hw_lock);
5016 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5017 val &= ~DSPFREQGUAR_MASK;
5018 val |= (cmd << DSPFREQGUAR_SHIFT);
5019 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5020 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5021 DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
5022 50)) {
5023 DRM_ERROR("timed out waiting for CDclk change\n");
5024 }
5025 mutex_unlock(&dev_priv->rps.hw_lock);
5026
dfcab17e 5027 if (cdclk == 400000) {
6bcda4f0 5028 u32 divider;
30a970c6 5029
6bcda4f0 5030 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
30a970c6
JB		 5031
5032 mutex_lock(&dev_priv->dpio_lock);
5033 /* adjust cdclk divider */
5034 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
9cf33db5 5035 val &= ~DISPLAY_FREQUENCY_VALUES;
30a970c6
JB		 5036 val |= divider;
5037 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
a877e801
VS		 5038
5039 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
5040 DISPLAY_FREQUENCY_STATUS) == (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5041 50))
5042 DRM_ERROR("timed out waiting for CDclk change\n");
30a970c6
JB		 5043 mutex_unlock(&dev_priv->dpio_lock);
5044 }
5045
5046 mutex_lock(&dev_priv->dpio_lock);
5047 /* adjust self-refresh exit latency value */
5048 val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
5049 val &= ~0x7f;
5050
5051 /*
5052 * For high bandwidth configs, we set a higher latency in the bunit
5053 * so that the core display fetch happens in time to avoid underruns.
5054 */
dfcab17e 5055 if (cdclk == 400000)
30a970c6
JB		 5056 val |= 4500 / 250; /* 4.5 usec */
5057 else
5058 val |= 3000 / 250; /* 3.0 usec */
5059 vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
5060 mutex_unlock(&dev_priv->dpio_lock);
5061
f8bf63fd 5062 vlv_update_cdclk(dev);
30a970c6
JB		 5063}
5064
383c5a6a
VS		 5065static void cherryview_set_cdclk(struct drm_device *dev, int cdclk)
5066{
5067 struct drm_i915_private *dev_priv = dev->dev_private;
5068 u32 val, cmd;
5069
5070 WARN_ON(dev_priv->display.get_display_clock_speed(dev) != dev_priv->vlv_cdclk_freq);
5071
5072 switch (cdclk) {
383c5a6a
VS		 5073 case 333333:
5074 case 320000:
383c5a6a 5075 case 266667:
383c5a6a 5076 case 200000:
383c5a6a
VS		 5077 break;
5078 default:
5f77eeb0 5079 MISSING_CASE(cdclk);
383c5a6a
VS		 5080 return;
5081 }
5082
9d0d3fda
VS		 5083 /*
5084 * Specs are full of misinformation, but testing on actual
5085 * hardware has shown that we just need to write the desired
5086 * CCK divider into the Punit register.
5087 */
5088 cmd = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
5089
383c5a6a
VS		 5090 mutex_lock(&dev_priv->rps.hw_lock);
5091 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
5092 val &= ~DSPFREQGUAR_MASK_CHV;
5093 val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
5094 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
5095 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) &
5096 DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
5097 50)) {
5098 DRM_ERROR("timed out waiting for CDclk change\n");
5099 }
5100 mutex_unlock(&dev_priv->rps.hw_lock);
5101
5102 vlv_update_cdclk(dev);
5103}
5104
30a970c6
JB		 5105static int valleyview_calc_cdclk(struct drm_i915_private *dev_priv,
5106 int max_pixclk)
5107{
6bcda4f0 5108 int freq_320 = (dev_priv->hpll_freq << 1) % 320000 != 0 ? 333333 : 320000;
6cca3195 5109 int limit = IS_CHERRYVIEW(dev_priv) ? 95 : 90;
29dc7ef3 5110
30a970c6
JB		 5111 /*
5112 * Really only a few cases to deal with, as only 4 CDclks are supported:
5113 * 200MHz
5114 * 267MHz
29dc7ef3 5115 * 320/333MHz (depends on HPLL freq)
6cca3195
VS		 5116 * 400MHz (VLV only)
5117 * So we check to see whether we're above 90% (VLV) or 95% (CHV)
5118 * of the lower bin and adjust if needed.
e37c67a1
VS		 5119 *
5120 * We seem to get an unstable or solid color picture at 200MHz.
5121 * Not sure what's wrong. For now use 200MHz only when all pipes
5122 * are off.
30a970c6 5123 */
6cca3195
VS		 5124 if (!IS_CHERRYVIEW(dev_priv) &&
5125 max_pixclk > freq_320*limit/100)
dfcab17e 5126 return 400000;
6cca3195 5127 else if (max_pixclk > 266667*limit/100)
29dc7ef3 5128 return freq_320;
e37c67a1 5129 else if (max_pixclk > 0)
dfcab17e 5130 return 266667;
e37c67a1
VS		 5131 else
5132 return 200000;
30a970c6
JB		 5133}
5134
2f2d7aa1
VS		 5135/* compute the max pixel clock for new configuration */
5136static int intel_mode_max_pixclk(struct drm_i915_private *dev_priv)
30a970c6
JB		 5137{
5138 struct drm_device *dev = dev_priv->dev;
5139 struct intel_crtc *intel_crtc;
5140 int max_pixclk = 0;
5141
d3fcc808 5142 for_each_intel_crtc(dev, intel_crtc) {
2f2d7aa1 5143 if (intel_crtc->new_enabled)
30a970c6 5144 max_pixclk = max(max_pixclk,
2d112de7 5145 intel_crtc->new_config->base.adjusted_mode.crtc_clock);
30a970c6
JB		 5146 }
5147
5148 return max_pixclk;
5149}
5150
5151static void valleyview_modeset_global_pipes(struct drm_device *dev,
2f2d7aa1 5152 unsigned *prepare_pipes)
30a970c6
JB		 5153{
5154 struct drm_i915_private *dev_priv = dev->dev_private;
5155 struct intel_crtc *intel_crtc;
2f2d7aa1 5156 int max_pixclk = intel_mode_max_pixclk(dev_priv);
30a970c6 5157
d60c4473
ID		 5158 if (valleyview_calc_cdclk(dev_priv, max_pixclk) ==
5159 dev_priv->vlv_cdclk_freq)
30a970c6
JB		 5160 return;
5161
2f2d7aa1 5162 /* disable/enable all currently active pipes while we change cdclk */
d3fcc808 5163 for_each_intel_crtc(dev, intel_crtc)
83d65738 5164 if (intel_crtc->base.state->enable)
30a970c6
JB		 5165 *prepare_pipes |= (1 << intel_crtc->pipe);
5166}
5167
1e69cd74
VS		 5168static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
5169{
5170 unsigned int credits, default_credits;
5171
5172 if (IS_CHERRYVIEW(dev_priv))
5173 default_credits = PFI_CREDIT(12);
5174 else
5175 default_credits = PFI_CREDIT(8);
5176
5177 if (DIV_ROUND_CLOSEST(dev_priv->vlv_cdclk_freq, 1000) >= dev_priv->rps.cz_freq) {
5178 /* CHV suggested value is 31 or 63 */
5179 if (IS_CHERRYVIEW(dev_priv))
5180 credits = PFI_CREDIT_31;
5181 else
5182 credits = PFI_CREDIT(15);
5183 } else {
5184 credits = default_credits;
5185 }
5186
5187 /*
5188 * WA - write default credits before re-programming
5189 * FIXME: should we also set the resend bit here?
5190 */
5191 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5192 default_credits);
5193
5194 I915_WRITE(GCI_CONTROL, VGA_FAST_MODE_DISABLE |
5195 credits | PFI_CREDIT_RESEND);
5196
5197 /*
5198 * FIXME is this guaranteed to clear
5199 * immediately or should we poll for it?
5200 */
5201 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND);
5202}
5203
30a970c6
JB		 5204static void valleyview_modeset_global_resources(struct drm_device *dev)
5205{
5206 struct drm_i915_private *dev_priv = dev->dev_private;
2f2d7aa1 5207 int max_pixclk = intel_mode_max_pixclk(dev_priv);
30a970c6
JB		 5208 int req_cdclk = valleyview_calc_cdclk(dev_priv, max_pixclk);
5209
383c5a6a 5210 if (req_cdclk != dev_priv->vlv_cdclk_freq) {
738c05c0
ID		 5211 /*
5212 * FIXME: We can end up here with all power domains off, yet
5213 * with a CDCLK frequency other than the minimum. To account
5214 * for this take the PIPE-A power domain, which covers the HW
5215 * blocks needed for the following programming. This can be
5216 * removed once it's guaranteed that we get here either with
5217 * the minimum CDCLK set, or the required power domains
5218 * enabled.
5219 */
5220 intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
5221
383c5a6a
VS		 5222 if (IS_CHERRYVIEW(dev))
5223 cherryview_set_cdclk(dev, req_cdclk);
5224 else
5225 valleyview_set_cdclk(dev, req_cdclk);
738c05c0 5226
1e69cd74
VS		 5227 vlv_program_pfi_credits(dev_priv);
5228
738c05c0 5229 intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
383c5a6a 5230 }
30a970c6
JB		 5231}
5232
89b667f8
JB		 5233static void valleyview_crtc_enable(struct drm_crtc *crtc)
5234{
5235 struct drm_device *dev = crtc->dev;
a72e4c9f 5236 struct drm_i915_private *dev_priv = to_i915(dev);
89b667f8
JB		 5237 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5238 struct intel_encoder *encoder;
5239 int pipe = intel_crtc->pipe;
23538ef1 5240 bool is_dsi;
89b667f8 5241
83d65738 5242 WARN_ON(!crtc->state->enable);
89b667f8
JB		 5243
5244 if (intel_crtc->active)
5245 return;
5246
409ee761 5247 is_dsi = intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI);
8525a235 5248
1ae0d137
VS		 5249 if (!is_dsi) {
5250 if (IS_CHERRYVIEW(dev))
6e3c9717 5251 chv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5252 else
6e3c9717 5253 vlv_prepare_pll(intel_crtc, intel_crtc->config);
1ae0d137 5254 }
5b18e57c 5255
6e3c9717 5256 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5257 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5258
5259 intel_set_pipe_timings(intel_crtc);
5260
c14b0485
VS		 5261 if (IS_CHERRYVIEW(dev) && pipe == PIPE_B) {
5262 struct drm_i915_private *dev_priv = dev->dev_private;
5263
5264 I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
5265 I915_WRITE(CHV_CANVAS(pipe), 0);
5266 }
5267
5b18e57c
DV		 5268 i9xx_set_pipeconf(intel_crtc);
5269
89b667f8 5270 intel_crtc->active = true;
89b667f8 5271
a72e4c9f 5272 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5273
89b667f8
JB		 5274 for_each_encoder_on_crtc(dev, crtc, encoder)
5275 if (encoder->pre_pll_enable)
5276 encoder->pre_pll_enable(encoder);
5277
9d556c99
CML		 5278 if (!is_dsi) {
5279 if (IS_CHERRYVIEW(dev))
6e3c9717 5280 chv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5281 else
6e3c9717 5282 vlv_enable_pll(intel_crtc, intel_crtc->config);
9d556c99 5283 }
89b667f8
JB		 5284
5285 for_each_encoder_on_crtc(dev, crtc, encoder)
5286 if (encoder->pre_enable)
5287 encoder->pre_enable(encoder);
5288
2dd24552
JB		 5289 i9xx_pfit_enable(intel_crtc);
5290
63cbb074
VS		 5291 intel_crtc_load_lut(crtc);
5292
f37fcc2a 5293 intel_update_watermarks(crtc);
e1fdc473 5294 intel_enable_pipe(intel_crtc);
be6a6f8e 5295
4b3a9526
VS		 5296 assert_vblank_disabled(crtc);
5297 drm_crtc_vblank_on(crtc);
5298
f9b61ff6
DV		 5299 for_each_encoder_on_crtc(dev, crtc, encoder)
5300 encoder->enable(encoder);
5301
9ab0460b 5302 intel_crtc_enable_planes(crtc);
d40d9187 5303
56b80e1f 5304 /* Underruns don't raise interrupts, so check manually. */
a72e4c9f 5305 i9xx_check_fifo_underruns(dev_priv);
89b667f8
JB		 5306}
5307
f13c2ef3
DV		 5308static void i9xx_set_pll_dividers(struct intel_crtc *crtc)
5309{
5310 struct drm_device *dev = crtc->base.dev;
5311 struct drm_i915_private *dev_priv = dev->dev_private;
5312
6e3c9717
ACO		 5313 I915_WRITE(FP0(crtc->pipe), crtc->config->dpll_hw_state.fp0);
5314 I915_WRITE(FP1(crtc->pipe), crtc->config->dpll_hw_state.fp1);
f13c2ef3
DV		 5315}
5316
0b8765c6 5317static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 5318{
5319 struct drm_device *dev = crtc->dev;
a72e4c9f 5320 struct drm_i915_private *dev_priv = to_i915(dev);
79e53945 5321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5322 struct intel_encoder *encoder;
79e53945 5323 int pipe = intel_crtc->pipe;
79e53945 5324
83d65738 5325 WARN_ON(!crtc->state->enable);
08a48469 5326
f7abfe8b
CW		 5327 if (intel_crtc->active)
5328 return;
5329
f13c2ef3
DV		 5330 i9xx_set_pll_dividers(intel_crtc);
5331
6e3c9717 5332 if (intel_crtc->config->has_dp_encoder)
fe3cd48d 5333 intel_dp_set_m_n(intel_crtc, M1_N1);
5b18e57c
DV		 5334
5335 intel_set_pipe_timings(intel_crtc);
5336
5b18e57c
DV		 5337 i9xx_set_pipeconf(intel_crtc);
5338
f7abfe8b 5339 intel_crtc->active = true;
6b383a7f 5340
4a3436e8 5341 if (!IS_GEN2(dev))
a72e4c9f 5342 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5343
9d6d9f19
MK		 5344 for_each_encoder_on_crtc(dev, crtc, encoder)
5345 if (encoder->pre_enable)
5346 encoder->pre_enable(encoder);
5347
f6736a1a
DV		 5348 i9xx_enable_pll(intel_crtc);
5349
2dd24552
JB		 5350 i9xx_pfit_enable(intel_crtc);
5351
63cbb074
VS		 5352 intel_crtc_load_lut(crtc);
5353
f37fcc2a 5354 intel_update_watermarks(crtc);
e1fdc473 5355 intel_enable_pipe(intel_crtc);
be6a6f8e 5356
4b3a9526
VS		 5357 assert_vblank_disabled(crtc);
5358 drm_crtc_vblank_on(crtc);
5359
f9b61ff6
DV		 5360 for_each_encoder_on_crtc(dev, crtc, encoder)
5361 encoder->enable(encoder);
5362
9ab0460b 5363 intel_crtc_enable_planes(crtc);
d40d9187 5364
4a3436e8
VS		 5365 /*
5366 * Gen2 reports pipe underruns whenever all planes are disabled.
5367 * So don't enable underrun reporting before at least some planes
5368 * are enabled.
5369 * FIXME: Need to fix the logic to work when we turn off all planes
5370 * but leave the pipe running.
5371 */
5372 if (IS_GEN2(dev))
a72e4c9f 5373 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
4a3436e8 5374
56b80e1f 5375 /* Underruns don't raise interrupts, so check manually. */
a72e4c9f 5376 i9xx_check_fifo_underruns(dev_priv);
0b8765c6 5377}
79e53945 5378
87476d63
DV		 5379static void i9xx_pfit_disable(struct intel_crtc *crtc)
5380{
5381 struct drm_device *dev = crtc->base.dev;
5382 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 5383
6e3c9717 5384 if (!crtc->config->gmch_pfit.control)
328d8e82 5385 return;
87476d63 5386
328d8e82 5387 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 5388
328d8e82
DV		 5389 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
5390 I915_READ(PFIT_CONTROL));
5391 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 5392}
5393
0b8765c6
JB		 5394static void i9xx_crtc_disable(struct drm_crtc *crtc)
5395{
5396 struct drm_device *dev = crtc->dev;
5397 struct drm_i915_private *dev_priv = dev->dev_private;
5398 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 5399 struct intel_encoder *encoder;
0b8765c6 5400 int pipe = intel_crtc->pipe;
ef9c3aee 5401
f7abfe8b
CW		 5402 if (!intel_crtc->active)
5403 return;
5404
4a3436e8
VS		 5405 /*
5406 * Gen2 reports pipe underruns whenever all planes are disabled.
5407 * So diasble underrun reporting before all the planes get disabled.
5408 * FIXME: Need to fix the logic to work when we turn off all planes
5409 * but leave the pipe running.
5410 */
5411 if (IS_GEN2(dev))
a72e4c9f 5412 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 5413
564ed191
ID		 5414 /*
5415 * Vblank time updates from the shadow to live plane control register
5416 * are blocked if the memory self-refresh mode is active at that
5417 * moment. So to make sure the plane gets truly disabled, disable
5418 * first the self-refresh mode. The self-refresh enable bit in turn
5419 * will be checked/applied by the HW only at the next frame start
5420 * event which is after the vblank start event, so we need to have a
5421 * wait-for-vblank between disabling the plane and the pipe.
5422 */
5423 intel_set_memory_cxsr(dev_priv, false);
9ab0460b
VS		 5424 intel_crtc_disable_planes(crtc);
5425
6304cd91
VS		 5426 /*
5427 * On gen2 planes are double buffered but the pipe isn't, so we must
5428 * wait for planes to fully turn off before disabling the pipe.
564ed191
ID		 5429 * We also need to wait on all gmch platforms because of the
5430 * self-refresh mode constraint explained above.
6304cd91 5431 */
564ed191 5432 intel_wait_for_vblank(dev, pipe);
6304cd91 5433
4b3a9526
VS		 5434 for_each_encoder_on_crtc(dev, crtc, encoder)
5435 encoder->disable(encoder);
5436
f9b61ff6
DV		 5437 drm_crtc_vblank_off(crtc);
5438 assert_vblank_disabled(crtc);
5439
575f7ab7 5440 intel_disable_pipe(intel_crtc);
24a1f16d 5441
87476d63 5442 i9xx_pfit_disable(intel_crtc);
24a1f16d 5443
89b667f8
JB		 5444 for_each_encoder_on_crtc(dev, crtc, encoder)
5445 if (encoder->post_disable)
5446 encoder->post_disable(encoder);
5447
409ee761 5448 if (!intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_DSI)) {
076ed3b2
CML		 5449 if (IS_CHERRYVIEW(dev))
5450 chv_disable_pll(dev_priv, pipe);
5451 else if (IS_VALLEYVIEW(dev))
5452 vlv_disable_pll(dev_priv, pipe);
5453 else
1c4e0274 5454 i9xx_disable_pll(intel_crtc);
076ed3b2 5455 }
0b8765c6 5456
4a3436e8 5457 if (!IS_GEN2(dev))
a72e4c9f 5458 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
4a3436e8 5459
f7abfe8b 5460 intel_crtc->active = false;
46ba614c 5461 intel_update_watermarks(crtc);
f37fcc2a 5462
efa9624e 5463 mutex_lock(&dev->struct_mutex);
7ff0ebcc 5464 intel_fbc_update(dev);
efa9624e 5465 mutex_unlock(&dev->struct_mutex);
0b8765c6
JB		 5466}
5467
ee7b9f93
JB		 5468static void i9xx_crtc_off(struct drm_crtc *crtc)
5469{
5470}
5471
b04c5bd6
BF		 5472/* Master function to enable/disable CRTC and corresponding power wells */
5473void intel_crtc_control(struct drm_crtc *crtc, bool enable)
976f8a20
DV		 5474{
5475 struct drm_device *dev = crtc->dev;
5476 struct drm_i915_private *dev_priv = dev->dev_private;
0e572fe7 5477 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
0e572fe7
DV		 5478 enum intel_display_power_domain domain;
5479 unsigned long domains;
976f8a20 5480
0e572fe7
DV		 5481 if (enable) {
5482 if (!intel_crtc->active) {
e1e9fb84
DV		 5483 domains = get_crtc_power_domains(crtc);
5484 for_each_power_domain(domain, domains)
5485 intel_display_power_get(dev_priv, domain);
5486 intel_crtc->enabled_power_domains = domains;
0e572fe7
DV		 5487
5488 dev_priv->display.crtc_enable(crtc);
5489 }
5490 } else {
5491 if (intel_crtc->active) {
5492 dev_priv->display.crtc_disable(crtc);
5493
e1e9fb84
DV		 5494 domains = intel_crtc->enabled_power_domains;
5495 for_each_power_domain(domain, domains)
5496 intel_display_power_put(dev_priv, domain);
5497 intel_crtc->enabled_power_domains = 0;
0e572fe7
DV		 5498 }
5499 }
b04c5bd6
BF		 5500}
5501
5502/**
5503 * Sets the power management mode of the pipe and plane.
5504 */
5505void intel_crtc_update_dpms(struct drm_crtc *crtc)
5506{
5507 struct drm_device *dev = crtc->dev;
5508 struct intel_encoder *intel_encoder;
5509 bool enable = false;
5510
5511 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
5512 enable |= intel_encoder->connectors_active;
5513
5514 intel_crtc_control(crtc, enable);
976f8a20
DV		 5515}
5516
cdd59983
CW		 5517static void intel_crtc_disable(struct drm_crtc *crtc)
5518{
cdd59983 5519 struct drm_device *dev = crtc->dev;
976f8a20 5520 struct drm_connector *connector;
ee7b9f93 5521 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 5522
976f8a20 5523 /* crtc should still be enabled when we disable it. */
83d65738 5524 WARN_ON(!crtc->state->enable);
976f8a20
DV		 5525
5526 dev_priv->display.crtc_disable(crtc);
ee7b9f93
JB		 5527 dev_priv->display.off(crtc);
5528
455a6808 5529 crtc->primary->funcs->disable_plane(crtc->primary);
976f8a20
DV		 5530
5531 /* Update computed state. */
5532 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
5533 if (!connector->encoder || !connector->encoder->crtc)
5534 continue;
5535
5536 if (connector->encoder->crtc != crtc)
5537 continue;
5538
5539 connector->dpms = DRM_MODE_DPMS_OFF;
5540 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 5541 }
5542}
5543
ea5b213a 5544void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 5545{
4ef69c7a 5546 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 5547
ea5b213a
CW		 5548 drm_encoder_cleanup(encoder);
5549 kfree(intel_encoder);
7e7d76c3
JB		 5550}
5551
9237329d 5552/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 5553 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
5554 * state of the entire output pipe. */
9237329d 5555static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 5556{
5ab432ef
DV		 5557 if (mode == DRM_MODE_DPMS_ON) {
5558 encoder->connectors_active = true;
5559
b2cabb0e 5560 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 5561 } else {
5562 encoder->connectors_active = false;
5563
b2cabb0e 5564 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 5565 }
79e53945
JB		 5566}
5567
0a91ca29
DV		 5568/* Cross check the actual hw state with our own modeset state tracking (and it's
5569 * internal consistency). */
b980514c 5570static void intel_connector_check_state(struct intel_connector *connector)
79e53945 5571{
0a91ca29
DV		 5572 if (connector->get_hw_state(connector)) {
5573 struct intel_encoder *encoder = connector->encoder;
5574 struct drm_crtc *crtc;
5575 bool encoder_enabled;
5576 enum pipe pipe;
5577
5578 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
5579 connector->base.base.id,
c23cc417 5580 connector->base.name);
0a91ca29 5581
0e32b39c
DA		 5582 /* there is no real hw state for MST connectors */
5583 if (connector->mst_port)
5584 return;
5585
e2c719b7 5586 I915_STATE_WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
0a91ca29 5587 "wrong connector dpms state\n");
e2c719b7 5588 I915_STATE_WARN(connector->base.encoder != &encoder->base,
0a91ca29 5589 "active connector not linked to encoder\n");
0a91ca29 5590
36cd7444 5591 if (encoder) {
e2c719b7 5592 I915_STATE_WARN(!encoder->connectors_active,
36cd7444
DA		 5593 "encoder->connectors_active not set\n");
5594
5595 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
e2c719b7
RC		 5596 I915_STATE_WARN(!encoder_enabled, "encoder not enabled\n");
5597 if (I915_STATE_WARN_ON(!encoder->base.crtc))
36cd7444 5598 return;
0a91ca29 5599
36cd7444 5600 crtc = encoder->base.crtc;
0a91ca29 5601
83d65738
MR		 5602 I915_STATE_WARN(!crtc->state->enable,
5603 "crtc not enabled\n");
e2c719b7
RC		 5604 I915_STATE_WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
5605 I915_STATE_WARN(pipe != to_intel_crtc(crtc)->pipe,
36cd7444
DA		 5606 "encoder active on the wrong pipe\n");
5607 }
0a91ca29 5608 }
79e53945
JB		 5609}
5610
5ab432ef
DV		 5611/* Even simpler default implementation, if there's really no special case to
5612 * consider. */
5613void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 5614{
5ab432ef
DV		 5615 /* All the simple cases only support two dpms states. */
5616 if (mode != DRM_MODE_DPMS_ON)
5617 mode = DRM_MODE_DPMS_OFF;
d4270e57 5618
5ab432ef
DV		 5619 if (mode == connector->dpms)
5620 return;
5621
5622 connector->dpms = mode;
5623
5624 /* Only need to change hw state when actually enabled */
c9976dcf
CW		 5625 if (connector->encoder)
5626 intel_encoder_dpms(to_intel_encoder(connector->encoder), mode);
0a91ca29 5627
b980514c 5628 intel_modeset_check_state(connector->dev);
79e53945
JB		 5629}
5630
f0947c37
DV		 5631/* Simple connector->get_hw_state implementation for encoders that support only
5632 * one connector and no cloning and hence the encoder state determines the state
5633 * of the connector. */
5634bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 5635{
24929352 5636 enum pipe pipe = 0;
f0947c37 5637 struct intel_encoder *encoder = connector->encoder;
ea5b213a 5638
f0947c37 5639 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 5640}
5641
d272ddfa
VS		 5642static int pipe_required_fdi_lanes(struct drm_device *dev, enum pipe pipe)
5643{
5644 struct intel_crtc *crtc =
5645 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5646
5647 if (crtc->base.state->enable &&
5648 crtc->config->has_pch_encoder)
5649 return crtc->config->fdi_lanes;
5650
5651 return 0;
5652}
5653
1857e1da 5654static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
5cec258b 5655 struct intel_crtc_state *pipe_config)
1857e1da 5656{
1857e1da
DV		 5657 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
5658 pipe_name(pipe), pipe_config->fdi_lanes);
5659 if (pipe_config->fdi_lanes > 4) {
5660 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
5661 pipe_name(pipe), pipe_config->fdi_lanes);
5662 return false;
5663 }
5664
bafb6553 5665 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
1857e1da
DV		 5666 if (pipe_config->fdi_lanes > 2) {
5667 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
5668 pipe_config->fdi_lanes);
5669 return false;
5670 } else {
5671 return true;
5672 }
5673 }
5674
5675 if (INTEL_INFO(dev)->num_pipes == 2)
5676 return true;
5677
5678 /* Ivybridge 3 pipe is really complicated */
5679 switch (pipe) {
5680 case PIPE_A:
5681 return true;
5682 case PIPE_B:
d272ddfa
VS		 5683 if (pipe_config->fdi_lanes > 2 &&
5684 pipe_required_fdi_lanes(dev, PIPE_C) > 0) {
1857e1da
DV		 5685 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
5686 pipe_name(pipe), pipe_config->fdi_lanes);
5687 return false;
5688 }
5689 return true;
5690 case PIPE_C:
251cc67c
VS		 5691 if (pipe_config->fdi_lanes > 2) {
5692 DRM_DEBUG_KMS("only 2 lanes on pipe %c: required %i lanes\n",
5693 pipe_name(pipe), pipe_config->fdi_lanes);
5694 return false;
5695 }
d272ddfa 5696 if (pipe_required_fdi_lanes(dev, PIPE_B) > 2) {
1857e1da
DV		 5697 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5698 return false;
5699 }
5700 return true;
5701 default:
5702 BUG();
5703 }
5704}
5705
e29c22c0
DV		 5706#define RETRY 1
5707static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
5cec258b 5708 struct intel_crtc_state *pipe_config)
877d48d5 5709{
1857e1da 5710 struct drm_device *dev = intel_crtc->base.dev;
2d112de7 5711 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
ff9a6750 5712 int lane, link_bw, fdi_dotclock;
e29c22c0 5713 bool setup_ok, needs_recompute = false;
877d48d5 5714
e29c22c0 5715retry:
877d48d5
DV		 5716 /* FDI is a binary signal running at ~2.7GHz, encoding
5717 * each output octet as 10 bits. The actual frequency
5718 * is stored as a divider into a 100MHz clock, and the
5719 * mode pixel clock is stored in units of 1KHz.
5720 * Hence the bw of each lane in terms of the mode signal
5721 * is:
5722 */
5723 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5724
241bfc38 5725 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 5726
2bd89a07 5727 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 5728 pipe_config->pipe_bpp);
5729
5730 pipe_config->fdi_lanes = lane;
5731
2bd89a07 5732 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 5733 link_bw, &pipe_config->fdi_m_n);
1857e1da 5734
e29c22c0
DV		 5735 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
5736 intel_crtc->pipe, pipe_config);
5737 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
5738 pipe_config->pipe_bpp -= 2*3;
5739 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
5740 pipe_config->pipe_bpp);
5741 needs_recompute = true;
5742 pipe_config->bw_constrained = true;
5743
5744 goto retry;
5745 }
5746
5747 if (needs_recompute)
5748 return RETRY;
5749
5750 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 5751}
5752
42db64ef 5753static void hsw_compute_ips_config(struct intel_crtc *crtc,
5cec258b 5754 struct intel_crtc_state *pipe_config)
42db64ef 5755{
d330a953 5756 pipe_config->ips_enabled = i915.enable_ips &&
3c4ca58c 5757 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 5758 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 5759}
5760
a43f6e0f 5761static int intel_crtc_compute_config(struct intel_crtc *crtc,
5cec258b 5762 struct intel_crtc_state *pipe_config)
79e53945 5763{
a43f6e0f 5764 struct drm_device *dev = crtc->base.dev;
8bd31e67 5765 struct drm_i915_private *dev_priv = dev->dev_private;
2d112de7 5766 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
89749350 5767
ad3a4479 5768 /* FIXME should check pixel clock limits on all platforms */
cf532bb2 5769 if (INTEL_INFO(dev)->gen < 4) {
cf532bb2
VS		 5770 int clock_limit =
5771 dev_priv->display.get_display_clock_speed(dev);
5772
5773 /*
5774 * Enable pixel doubling when the dot clock
5775 * is > 90% of the (display) core speed.
5776 *
b397c96b
VS		 5777 * GDG double wide on either pipe,
5778 * otherwise pipe A only.
cf532bb2 5779 */
b397c96b 5780 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 5781 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 5782 clock_limit *= 2;
cf532bb2 5783 pipe_config->double_wide = true;
ad3a4479
VS		 5784 }
5785
241bfc38 5786 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 5787 return -EINVAL;
2c07245f 5788 }
89749350 5789
1d1d0e27
VS		 5790 /*
5791 * Pipe horizontal size must be even in:
5792 * - DVO ganged mode
5793 * - LVDS dual channel mode
5794 * - Double wide pipe
5795 */
b4f2bf4c 5796 if ((intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
1d1d0e27
VS		 5797 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
5798 pipe_config->pipe_src_w &= ~1;
5799
8693a824
DL		 5800 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
5801 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 5802 */
5803 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
5804 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 5805 return -EINVAL;
44f46b42 5806
bd080ee5 5807 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 5808 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 5809 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 5810 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
5811 * for lvds. */
5812 pipe_config->pipe_bpp = 8*3;
5813 }
5814
f5adf94e 5815 if (HAS_IPS(dev))
a43f6e0f
DV		 5816 hsw_compute_ips_config(crtc, pipe_config);
5817
877d48d5 5818 if (pipe_config->has_pch_encoder)
a43f6e0f 5819 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 5820
e29c22c0 5821 return 0;
79e53945
JB		 5822}
5823
25eb05fc
JB		 5824static int valleyview_get_display_clock_speed(struct drm_device *dev)
5825{
d197b7d3 5826 struct drm_i915_private *dev_priv = dev->dev_private;
d197b7d3
VS		 5827 u32 val;
5828 int divider;
5829
6bcda4f0
VS		 5830 if (dev_priv->hpll_freq == 0)
5831 dev_priv->hpll_freq = valleyview_get_vco(dev_priv);
5832
d197b7d3
VS		 5833 mutex_lock(&dev_priv->dpio_lock);
5834 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
5835 mutex_unlock(&dev_priv->dpio_lock);
5836
5837 divider = val & DISPLAY_FREQUENCY_VALUES;
5838
7d007f40
VS		 5839 WARN((val & DISPLAY_FREQUENCY_STATUS) !=
5840 (divider << DISPLAY_FREQUENCY_STATUS_SHIFT),
5841 "cdclk change in progress\n");
5842
6bcda4f0 5843 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, divider + 1);
25eb05fc
JB		 5844}
5845
e70236a8
JB		 5846static int i945_get_display_clock_speed(struct drm_device *dev)
5847{
5848 return 400000;
5849}
79e53945 5850
e70236a8 5851static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 5852{
e70236a8
JB		 5853 return 333000;
5854}
79e53945 5855
e70236a8
JB		 5856static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
5857{
5858 return 200000;
5859}
79e53945 5860
257a7ffc
DV		 5861static int pnv_get_display_clock_speed(struct drm_device *dev)
5862{
5863 u16 gcfgc = 0;
5864
5865 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5866
5867 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5868 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
5869 return 267000;
5870 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
5871 return 333000;
5872 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
5873 return 444000;
5874 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
5875 return 200000;
5876 default:
5877 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
5878 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
5879 return 133000;
5880 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
5881 return 167000;
5882 }
5883}
5884
e70236a8
JB		 5885static int i915gm_get_display_clock_speed(struct drm_device *dev)
5886{
5887 u16 gcfgc = 0;
79e53945 5888
e70236a8
JB		 5889 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
5890
5891 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
5892 return 133000;
5893 else {
5894 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
5895 case GC_DISPLAY_CLOCK_333_MHZ:
5896 return 333000;
5897 default:
5898 case GC_DISPLAY_CLOCK_190_200_MHZ:
5899 return 190000;
79e53945 5900 }
e70236a8
JB		 5901 }
5902}
5903
5904static int i865_get_display_clock_speed(struct drm_device *dev)
5905{
5906 return 266000;
5907}
5908
5909static int i855_get_display_clock_speed(struct drm_device *dev)
5910{
5911 u16 hpllcc = 0;
5912 /* Assume that the hardware is in the high speed state. This
5913 * should be the default.
5914 */
5915 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
5916 case GC_CLOCK_133_200:
5917 case GC_CLOCK_100_200:
5918 return 200000;
5919 case GC_CLOCK_166_250:
5920 return 250000;
5921 case GC_CLOCK_100_133:
79e53945 5922 return 133000;
e70236a8 5923 }
79e53945 5924
e70236a8
JB		 5925 /* Shouldn't happen */
5926 return 0;
5927}
79e53945 5928
e70236a8
JB		 5929static int i830_get_display_clock_speed(struct drm_device *dev)
5930{
5931 return 133000;
79e53945
JB		 5932}
5933
2c07245f 5934static void
a65851af 5935intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 5936{
a65851af
VS		 5937 while (*num > DATA_LINK_M_N_MASK ||
5938 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 5939 *num >>= 1;
5940 *den >>= 1;
5941 }
5942}
5943
a65851af
VS		 5944static void compute_m_n(unsigned int m, unsigned int n,
5945 uint32_t *ret_m, uint32_t *ret_n)
5946{
5947 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
5948 *ret_m = div_u64((uint64_t) m * *ret_n, n);
5949 intel_reduce_m_n_ratio(ret_m, ret_n);
5950}
5951
e69d0bc1
DV		 5952void
5953intel_link_compute_m_n(int bits_per_pixel, int nlanes,
5954 int pixel_clock, int link_clock,
5955 struct intel_link_m_n *m_n)
2c07245f 5956{
e69d0bc1 5957 m_n->tu = 64;
a65851af
VS		 5958
5959 compute_m_n(bits_per_pixel * pixel_clock,
5960 link_clock * nlanes * 8,
5961 &m_n->gmch_m, &m_n->gmch_n);
5962
5963 compute_m_n(pixel_clock, link_clock,
5964 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 5965}
5966
a7615030
CW		 5967static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
5968{
d330a953
JN		 5969 if (i915.panel_use_ssc >= 0)
5970 return i915.panel_use_ssc != 0;
41aa3448 5971 return dev_priv->vbt.lvds_use_ssc
435793df 5972 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 5973}
5974
409ee761 5975static int i9xx_get_refclk(struct intel_crtc *crtc, int num_connectors)
c65d77d8 5976{
409ee761 5977 struct drm_device *dev = crtc->base.dev;
c65d77d8
JB		 5978 struct drm_i915_private *dev_priv = dev->dev_private;
5979 int refclk;
5980
a0c4da24 5981 if (IS_VALLEYVIEW(dev)) {
9a0ea498 5982 refclk = 100000;
d0737e1d 5983 } else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 5984 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b
VS		 5985 refclk = dev_priv->vbt.lvds_ssc_freq;
5986 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n", refclk);
c65d77d8
JB		 5987 } else if (!IS_GEN2(dev)) {
5988 refclk = 96000;
5989 } else {
5990 refclk = 48000;
5991 }
5992
5993 return refclk;
5994}
5995
7429e9d4 5996static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 5997{
7df00d7a 5998 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 5999}
f47709a9 6000
7429e9d4
DV		 6001static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
6002{
6003 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 6004}
6005
f47709a9 6006static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
190f68c5 6007 struct intel_crtc_state *crtc_state,
a7516a05
JB		 6008 intel_clock_t *reduced_clock)
6009{
f47709a9 6010 struct drm_device *dev = crtc->base.dev;
a7516a05
JB		 6011 u32 fp, fp2 = 0;
6012
6013 if (IS_PINEVIEW(dev)) {
190f68c5 6014 fp = pnv_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6015 if (reduced_clock)
7429e9d4 6016 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 6017 } else {
190f68c5 6018 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
a7516a05 6019 if (reduced_clock)
7429e9d4 6020 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 6021 }
6022
190f68c5 6023 crtc_state->dpll_hw_state.fp0 = fp;
a7516a05 6024
f47709a9 6025 crtc->lowfreq_avail = false;
e1f234bd 6026 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
d330a953 6027 reduced_clock && i915.powersave) {
190f68c5 6028 crtc_state->dpll_hw_state.fp1 = fp2;
f47709a9 6029 crtc->lowfreq_avail = true;
a7516a05 6030 } else {
190f68c5 6031 crtc_state->dpll_hw_state.fp1 = fp;
a7516a05
JB		 6032 }
6033}
6034
5e69f97f
CML		 6035static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
6036 pipe)
89b667f8
JB		 6037{
6038 u32 reg_val;
6039
6040 /*
6041 * PLLB opamp always calibrates to max value of 0x3f, force enable it
6042 * and set it to a reasonable value instead.
6043 */
ab3c759a 6044 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8
JB		 6045 reg_val &= 0xffffff00;
6046 reg_val |= 0x00000030;
ab3c759a 6047 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6048
ab3c759a 6049 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6050 reg_val &= 0x8cffffff;
6051 reg_val = 0x8c000000;
ab3c759a 6052 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8 6053
ab3c759a 6054 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1));
89b667f8 6055 reg_val &= 0xffffff00;
ab3c759a 6056 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val);
89b667f8 6057
ab3c759a 6058 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13);
89b667f8
JB		 6059 reg_val &= 0x00ffffff;
6060 reg_val |= 0xb0000000;
ab3c759a 6061 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val);
89b667f8
JB		 6062}
6063
b551842d
DV		 6064static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
6065 struct intel_link_m_n *m_n)
6066{
6067 struct drm_device *dev = crtc->base.dev;
6068 struct drm_i915_private *dev_priv = dev->dev_private;
6069 int pipe = crtc->pipe;
6070
e3b95f1e
DV		 6071 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6072 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
6073 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
6074 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 6075}
6076
6077static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
f769cd24
VK		 6078 struct intel_link_m_n *m_n,
6079 struct intel_link_m_n *m2_n2)
b551842d
DV		 6080{
6081 struct drm_device *dev = crtc->base.dev;
6082 struct drm_i915_private *dev_priv = dev->dev_private;
6083 int pipe = crtc->pipe;
6e3c9717 6084 enum transcoder transcoder = crtc->config->cpu_transcoder;
b551842d
DV		 6085
6086 if (INTEL_INFO(dev)->gen >= 5) {
6087 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
6088 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
6089 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
6090 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
f769cd24
VK		 6091 /* M2_N2 registers to be set only for gen < 8 (M2_N2 available
6092 * for gen < 8) and if DRRS is supported (to make sure the
6093 * registers are not unnecessarily accessed).
6094 */
44395bfe 6095 if (m2_n2 && (IS_CHERRYVIEW(dev) || INTEL_INFO(dev)->gen < 8) &&
6e3c9717 6096 crtc->config->has_drrs) {
f769cd24
VK		 6097 I915_WRITE(PIPE_DATA_M2(transcoder),
6098 TU_SIZE(m2_n2->tu) | m2_n2->gmch_m);
6099 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n);
6100 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m);
6101 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n);
6102 }
b551842d 6103 } else {
e3b95f1e
DV		 6104 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
6105 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
6106 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
6107 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 6108 }
6109}
6110
fe3cd48d 6111void intel_dp_set_m_n(struct intel_crtc *crtc, enum link_m_n_set m_n)
03afc4a2 6112{
fe3cd48d
R		 6113 struct intel_link_m_n *dp_m_n, *dp_m2_n2 = NULL;
6114
6115 if (m_n == M1_N1) {
6116 dp_m_n = &crtc->config->dp_m_n;
6117 dp_m2_n2 = &crtc->config->dp_m2_n2;
6118 } else if (m_n == M2_N2) {
6119
6120 /*
6121 * M2_N2 registers are not supported. Hence m2_n2 divider value
6122 * needs to be programmed into M1_N1.
6123 */
6124 dp_m_n = &crtc->config->dp_m2_n2;
6125 } else {
6126 DRM_ERROR("Unsupported divider value\n");
6127 return;
6128 }
6129
6e3c9717
ACO		 6130 if (crtc->config->has_pch_encoder)
6131 intel_pch_transcoder_set_m_n(crtc, &crtc->config->dp_m_n);
03afc4a2 6132 else
fe3cd48d 6133 intel_cpu_transcoder_set_m_n(crtc, dp_m_n, dp_m2_n2);
03afc4a2
DV		 6134}
6135
d288f65f 6136static void vlv_update_pll(struct intel_crtc *crtc,
5cec258b 6137 struct intel_crtc_state *pipe_config)
bdd4b6a6
DV		 6138{
6139 u32 dpll, dpll_md;
6140
6141 /*
6142 * Enable DPIO clock input. We should never disable the reference
6143 * clock for pipe B, since VGA hotplug / manual detection depends
6144 * on it.
6145 */
6146 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
6147 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
6148 /* We should never disable this, set it here for state tracking */
6149 if (crtc->pipe == PIPE_B)
6150 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
6151 dpll |= DPLL_VCO_ENABLE;
d288f65f 6152 pipe_config->dpll_hw_state.dpll = dpll;
bdd4b6a6 6153
d288f65f 6154 dpll_md = (pipe_config->pixel_multiplier - 1)
bdd4b6a6 6155 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
d288f65f 6156 pipe_config->dpll_hw_state.dpll_md = dpll_md;
bdd4b6a6
DV		 6157}
6158
d288f65f 6159static void vlv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6160 const struct intel_crtc_state *pipe_config)
a0c4da24 6161{
f47709a9 6162 struct drm_device *dev = crtc->base.dev;
a0c4da24 6163 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 6164 int pipe = crtc->pipe;
bdd4b6a6 6165 u32 mdiv;
a0c4da24 6166 u32 bestn, bestm1, bestm2, bestp1, bestp2;
bdd4b6a6 6167 u32 coreclk, reg_val;
a0c4da24 6168
09153000
DV		 6169 mutex_lock(&dev_priv->dpio_lock);
6170
d288f65f
VS		 6171 bestn = pipe_config->dpll.n;
6172 bestm1 = pipe_config->dpll.m1;
6173 bestm2 = pipe_config->dpll.m2;
6174 bestp1 = pipe_config->dpll.p1;
6175 bestp2 = pipe_config->dpll.p2;
a0c4da24 6176
89b667f8
JB		 6177 /* See eDP HDMI DPIO driver vbios notes doc */
6178
6179 /* PLL B needs special handling */
bdd4b6a6 6180 if (pipe == PIPE_B)
5e69f97f 6181 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 6182
6183 /* Set up Tx target for periodic Rcomp update */
ab3c759a 6184 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f);
89b667f8
JB		 6185
6186 /* Disable target IRef on PLL */
ab3c759a 6187 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe));
89b667f8 6188 reg_val &= 0x00ffffff;
ab3c759a 6189 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val);
89b667f8
JB		 6190
6191 /* Disable fast lock */
ab3c759a 6192 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610);
89b667f8
JB		 6193
6194 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 6195 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
6196 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
6197 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 6198 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 6199
6200 /*
6201 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
6202 * but we don't support that).
6203 * Note: don't use the DAC post divider as it seems unstable.
6204 */
6205 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
ab3c759a 6206 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6207
a0c4da24 6208 mdiv |= DPIO_ENABLE_CALIBRATION;
ab3c759a 6209 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv);
a0c4da24 6210
89b667f8 6211 /* Set HBR and RBR LPF coefficients */
d288f65f 6212 if (pipe_config->port_clock == 162000 ||
409ee761
ACO		 6213 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG) ||
6214 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
ab3c759a 6215 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
885b0120 6216 0x009f0003);
89b667f8 6217 else
ab3c759a 6218 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe),
89b667f8
JB		 6219 0x00d0000f);
6220
681a8504 6221 if (pipe_config->has_dp_encoder) {
89b667f8 6222 /* Use SSC source */
bdd4b6a6 6223 if (pipe == PIPE_A)
ab3c759a 6224 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6225 0x0df40000);
6226 else
ab3c759a 6227 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6228 0x0df70000);
6229 } else { /* HDMI or VGA */
6230 /* Use bend source */
bdd4b6a6 6231 if (pipe == PIPE_A)
ab3c759a 6232 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6233 0x0df70000);
6234 else
ab3c759a 6235 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe),
89b667f8
JB		 6236 0x0df40000);
6237 }
a0c4da24 6238
ab3c759a 6239 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe));
89b667f8 6240 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
409ee761
ACO		 6241 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
6242 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
89b667f8 6243 coreclk |= 0x01000000;
ab3c759a 6244 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
a0c4da24 6245
ab3c759a 6246 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
09153000 6247 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 6248}
6249
d288f65f 6250static void chv_update_pll(struct intel_crtc *crtc,
5cec258b 6251 struct intel_crtc_state *pipe_config)
1ae0d137 6252{
d288f65f 6253 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLOCK_CHV |
1ae0d137
VS		 6254 DPLL_REFA_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS |
6255 DPLL_VCO_ENABLE;
6256 if (crtc->pipe != PIPE_A)
d288f65f 6257 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
1ae0d137 6258
d288f65f
VS		 6259 pipe_config->dpll_hw_state.dpll_md =
6260 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
1ae0d137
VS		 6261}
6262
d288f65f 6263static void chv_prepare_pll(struct intel_crtc *crtc,
5cec258b 6264 const struct intel_crtc_state *pipe_config)
9d556c99
CML		 6265{
6266 struct drm_device *dev = crtc->base.dev;
6267 struct drm_i915_private *dev_priv = dev->dev_private;
6268 int pipe = crtc->pipe;
6269 int dpll_reg = DPLL(crtc->pipe);
6270 enum dpio_channel port = vlv_pipe_to_channel(pipe);
9cbe40c1 6271 u32 loopfilter, tribuf_calcntr;
9d556c99 6272 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac;
a945ce7e 6273 u32 dpio_val;
9cbe40c1 6274 int vco;
9d556c99 6275
d288f65f
VS		 6276 bestn = pipe_config->dpll.n;
6277 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff;
6278 bestm1 = pipe_config->dpll.m1;
6279 bestm2 = pipe_config->dpll.m2 >> 22;
6280 bestp1 = pipe_config->dpll.p1;
6281 bestp2 = pipe_config->dpll.p2;
9cbe40c1 6282 vco = pipe_config->dpll.vco;
a945ce7e 6283 dpio_val = 0;
9cbe40c1 6284 loopfilter = 0;
9d556c99
CML		 6285
6286 /*
6287 * Enable Refclk and SSC
6288 */
a11b0703 6289 I915_WRITE(dpll_reg,
d288f65f 6290 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE);
a11b0703
VS		 6291
6292 mutex_lock(&dev_priv->dpio_lock);
9d556c99 6293
9d556c99
CML		 6294 /* p1 and p2 divider */
6295 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
6296 5 << DPIO_CHV_S1_DIV_SHIFT |
6297 bestp1 << DPIO_CHV_P1_DIV_SHIFT |
6298 bestp2 << DPIO_CHV_P2_DIV_SHIFT |
6299 1 << DPIO_CHV_K_DIV_SHIFT);
6300
6301 /* Feedback post-divider - m2 */
6302 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2);
6303
6304 /* Feedback refclk divider - n and m1 */
6305 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port),
6306 DPIO_CHV_M1_DIV_BY_2 |
6307 1 << DPIO_CHV_N_DIV_SHIFT);
6308
6309 /* M2 fraction division */
a945ce7e
VP		 6310 if (bestm2_frac)
6311 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac);
9d556c99
CML		 6312
6313 /* M2 fraction division enable */
a945ce7e
VP		 6314 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
6315 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN);
6316 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT);
6317 if (bestm2_frac)
6318 dpio_val |= DPIO_CHV_FRAC_DIV_EN;
6319 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val);
9d556c99 6320
de3a0fde
VP		 6321 /* Program digital lock detect threshold */
6322 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port));
6323 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK |
6324 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE);
6325 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT);
6326 if (!bestm2_frac)
6327 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE;
6328 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val);
6329
9d556c99 6330 /* Loop filter */
9cbe40c1
VP		 6331 if (vco == 5400000) {
6332 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT);
6333 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT);
6334 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT);
6335 tribuf_calcntr = 0x9;
6336 } else if (vco <= 6200000) {
6337 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT);
6338 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT);
6339 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6340 tribuf_calcntr = 0x9;
6341 } else if (vco <= 6480000) {
6342 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6343 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6344 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6345 tribuf_calcntr = 0x8;
6346 } else {
6347 /* Not supported. Apply the same limits as in the max case */
6348 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT);
6349 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT);
6350 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT);
6351 tribuf_calcntr = 0;
6352 }
9d556c99
CML		 6353 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter);
6354
968040b2 6355 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port));
9cbe40c1
VP		 6356 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK;
6357 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT);
6358 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val);
6359
9d556c99
CML		 6360 /* AFC Recal */
6361 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port),
6362 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
6363 DPIO_AFC_RECAL);
6364
6365 mutex_unlock(&dev_priv->dpio_lock);
6366}
6367
d288f65f
VS		 6368/**
6369 * vlv_force_pll_on - forcibly enable just the PLL
6370 * @dev_priv: i915 private structure
6371 * @pipe: pipe PLL to enable
6372 * @dpll: PLL configuration
6373 *
6374 * Enable the PLL for @pipe using the supplied @dpll config. To be used
6375 * in cases where we need the PLL enabled even when @pipe is not going to
6376 * be enabled.
6377 */
6378void vlv_force_pll_on(struct drm_device *dev, enum pipe pipe,
6379 const struct dpll *dpll)
6380{
6381 struct intel_crtc *crtc =
6382 to_intel_crtc(intel_get_crtc_for_pipe(dev, pipe));
5cec258b 6383 struct intel_crtc_state pipe_config = {
d288f65f
VS		 6384 .pixel_multiplier = 1,
6385 .dpll = *dpll,
6386 };
6387
6388 if (IS_CHERRYVIEW(dev)) {
6389 chv_update_pll(crtc, &pipe_config);
6390 chv_prepare_pll(crtc, &pipe_config);
6391 chv_enable_pll(crtc, &pipe_config);
6392 } else {
6393 vlv_update_pll(crtc, &pipe_config);
6394 vlv_prepare_pll(crtc, &pipe_config);
6395 vlv_enable_pll(crtc, &pipe_config);
6396 }
6397}
6398
6399/**
6400 * vlv_force_pll_off - forcibly disable just the PLL
6401 * @dev_priv: i915 private structure
6402 * @pipe: pipe PLL to disable
6403 *
6404 * Disable the PLL for @pipe. To be used in cases where we need
6405 * the PLL enabled even when @pipe is not going to be enabled.
6406 */
6407void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe)
6408{
6409 if (IS_CHERRYVIEW(dev))
6410 chv_disable_pll(to_i915(dev), pipe);
6411 else
6412 vlv_disable_pll(to_i915(dev), pipe);
6413}
6414
f47709a9 6415static void i9xx_update_pll(struct intel_crtc *crtc,
190f68c5 6416 struct intel_crtc_state *crtc_state,
f47709a9 6417 intel_clock_t *reduced_clock,
eb1cbe48
DV		 6418 int num_connectors)
6419{
f47709a9 6420 struct drm_device *dev = crtc->base.dev;
eb1cbe48 6421 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 6422 u32 dpll;
6423 bool is_sdvo;
190f68c5 6424 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 6425
190f68c5 6426 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 6427
d0737e1d
ACO		 6428 is_sdvo = intel_pipe_will_have_type(crtc, INTEL_OUTPUT_SDVO) ||
6429 intel_pipe_will_have_type(crtc, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 6430
6431 dpll = DPLL_VGA_MODE_DIS;
6432
d0737e1d 6433 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 6434 dpll |= DPLLB_MODE_LVDS;
6435 else
6436 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 6437
ef1b460d 6438 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
190f68c5 6439 dpll |= (crtc_state->pixel_multiplier - 1)
198a037f 6440 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 6441 }
198a037f
DV		 6442
6443 if (is_sdvo)
4a33e48d 6444 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 6445
190f68c5 6446 if (crtc_state->has_dp_encoder)
4a33e48d 6447 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 6448
6449 /* compute bitmask from p1 value */
6450 if (IS_PINEVIEW(dev))
6451 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
6452 else {
6453 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6454 if (IS_G4X(dev) && reduced_clock)
6455 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
6456 }
6457 switch (clock->p2) {
6458 case 5:
6459 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
6460 break;
6461 case 7:
6462 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
6463 break;
6464 case 10:
6465 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
6466 break;
6467 case 14:
6468 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
6469 break;
6470 }
6471 if (INTEL_INFO(dev)->gen >= 4)
6472 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
6473
190f68c5 6474 if (crtc_state->sdvo_tv_clock)
eb1cbe48 6475 dpll |= PLL_REF_INPUT_TVCLKINBC;
d0737e1d 6476 else if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 6477 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6478 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6479 else
6480 dpll |= PLL_REF_INPUT_DREFCLK;
6481
6482 dpll |= DPLL_VCO_ENABLE;
190f68c5 6483 crtc_state->dpll_hw_state.dpll = dpll;
8bcc2795 6484
eb1cbe48 6485 if (INTEL_INFO(dev)->gen >= 4) {
190f68c5 6486 u32 dpll_md = (crtc_state->pixel_multiplier - 1)
ef1b460d 6487 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
190f68c5 6488 crtc_state->dpll_hw_state.dpll_md = dpll_md;
eb1cbe48
DV		 6489 }
6490}
6491
f47709a9 6492static void i8xx_update_pll(struct intel_crtc *crtc,
190f68c5 6493 struct intel_crtc_state *crtc_state,
f47709a9 6494 intel_clock_t *reduced_clock,
eb1cbe48
DV		 6495 int num_connectors)
6496{
f47709a9 6497 struct drm_device *dev = crtc->base.dev;
eb1cbe48 6498 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 6499 u32 dpll;
190f68c5 6500 struct dpll *clock = &crtc_state->dpll;
eb1cbe48 6501
190f68c5 6502 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock);
2a8f64ca 6503
eb1cbe48
DV		 6504 dpll = DPLL_VGA_MODE_DIS;
6505
d0737e1d 6506 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 6507 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6508 } else {
6509 if (clock->p1 == 2)
6510 dpll |= PLL_P1_DIVIDE_BY_TWO;
6511 else
6512 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
6513 if (clock->p2 == 4)
6514 dpll |= PLL_P2_DIVIDE_BY_4;
6515 }
6516
d0737e1d 6517 if (!IS_I830(dev) && intel_pipe_will_have_type(crtc, INTEL_OUTPUT_DVO))
4a33e48d
DV		 6518 dpll |= DPLL_DVO_2X_MODE;
6519
d0737e1d 6520 if (intel_pipe_will_have_type(crtc, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 6521 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
6522 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
6523 else
6524 dpll |= PLL_REF_INPUT_DREFCLK;
6525
6526 dpll |= DPLL_VCO_ENABLE;
190f68c5 6527 crtc_state->dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 6528}
6529
8a654f3b 6530static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 6531{
6532 struct drm_device *dev = intel_crtc->base.dev;
6533 struct drm_i915_private *dev_priv = dev->dev_private;
6534 enum pipe pipe = intel_crtc->pipe;
6e3c9717 6535 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
8a654f3b 6536 struct drm_display_mode *adjusted_mode =
6e3c9717 6537 &intel_crtc->config->base.adjusted_mode;
1caea6e9
VS		 6538 uint32_t crtc_vtotal, crtc_vblank_end;
6539 int vsyncshift = 0;
4d8a62ea
DV		 6540
6541 /* We need to be careful not to changed the adjusted mode, for otherwise
6542 * the hw state checker will get angry at the mismatch. */
6543 crtc_vtotal = adjusted_mode->crtc_vtotal;
6544 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c 6545
609aeaca 6546 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
b0e77b9c 6547 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 6548 crtc_vtotal -= 1;
6549 crtc_vblank_end -= 1;
609aeaca 6550
409ee761 6551 if (intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
609aeaca
VS		 6552 vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
6553 else
6554 vsyncshift = adjusted_mode->crtc_hsync_start -
6555 adjusted_mode->crtc_htotal / 2;
1caea6e9
VS		 6556 if (vsyncshift < 0)
6557 vsyncshift += adjusted_mode->crtc_htotal;
b0e77b9c
PZ		 6558 }
6559
6560 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 6561 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 6562
fe2b8f9d 6563 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 6564 (adjusted_mode->crtc_hdisplay - 1) |
6565 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 6566 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 6567 (adjusted_mode->crtc_hblank_start - 1) |
6568 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 6569 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 6570 (adjusted_mode->crtc_hsync_start - 1) |
6571 ((adjusted_mode->crtc_hsync_end - 1) << 16));
6572
fe2b8f9d 6573 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 6574 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 6575 ((crtc_vtotal - 1) << 16));
fe2b8f9d 6576 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 6577 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 6578 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 6579 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 6580 (adjusted_mode->crtc_vsync_start - 1) |
6581 ((adjusted_mode->crtc_vsync_end - 1) << 16));
6582
b5e508d4
PZ		 6583 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
6584 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
6585 * documented on the DDI_FUNC_CTL register description, EDP Input Select
6586 * bits. */
6587 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
6588 (pipe == PIPE_B || pipe == PIPE_C))
6589 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
6590
b0e77b9c
PZ		 6591 /* pipesrc controls the size that is scaled from, which should
6592 * always be the user's requested size.
6593 */
6594 I915_WRITE(PIPESRC(pipe),
6e3c9717
ACO		 6595 ((intel_crtc->config->pipe_src_w - 1) << 16) |
6596 (intel_crtc->config->pipe_src_h - 1));
b0e77b9c
PZ		 6597}
6598
1bd1bd80 6599static void intel_get_pipe_timings(struct intel_crtc *crtc,
5cec258b 6600 struct intel_crtc_state *pipe_config)
1bd1bd80
DV		 6601{
6602 struct drm_device *dev = crtc->base.dev;
6603 struct drm_i915_private *dev_priv = dev->dev_private;
6604 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
6605 uint32_t tmp;
6606
6607 tmp = I915_READ(HTOTAL(cpu_transcoder));
2d112de7
ACO		 6608 pipe_config->base.adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
6609 pipe_config->base.adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6610 tmp = I915_READ(HBLANK(cpu_transcoder));
2d112de7
ACO		 6611 pipe_config->base.adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
6612 pipe_config->base.adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6613 tmp = I915_READ(HSYNC(cpu_transcoder));
2d112de7
ACO		 6614 pipe_config->base.adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
6615 pipe_config->base.adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 6616
6617 tmp = I915_READ(VTOTAL(cpu_transcoder));
2d112de7
ACO		 6618 pipe_config->base.adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
6619 pipe_config->base.adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6620 tmp = I915_READ(VBLANK(cpu_transcoder));
2d112de7
ACO		 6621 pipe_config->base.adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
6622 pipe_config->base.adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80 6623 tmp = I915_READ(VSYNC(cpu_transcoder));
2d112de7
ACO		 6624 pipe_config->base.adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
6625 pipe_config->base.adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
1bd1bd80
DV		 6626
6627 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
2d112de7
ACO		 6628 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
6629 pipe_config->base.adjusted_mode.crtc_vtotal += 1;
6630 pipe_config->base.adjusted_mode.crtc_vblank_end += 1;
1bd1bd80
DV		 6631 }
6632
6633 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 6634 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
6635 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
6636
2d112de7
ACO		 6637 pipe_config->base.mode.vdisplay = pipe_config->pipe_src_h;
6638 pipe_config->base.mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 6639}
6640
f6a83288 6641void intel_mode_from_pipe_config(struct drm_display_mode *mode,
5cec258b 6642 struct intel_crtc_state *pipe_config)
babea61d 6643{
2d112de7
ACO		 6644 mode->hdisplay = pipe_config->base.adjusted_mode.crtc_hdisplay;
6645 mode->htotal = pipe_config->base.adjusted_mode.crtc_htotal;
6646 mode->hsync_start = pipe_config->base.adjusted_mode.crtc_hsync_start;
6647 mode->hsync_end = pipe_config->base.adjusted_mode.crtc_hsync_end;
babea61d 6648
2d112de7
ACO		 6649 mode->vdisplay = pipe_config->base.adjusted_mode.crtc_vdisplay;
6650 mode->vtotal = pipe_config->base.adjusted_mode.crtc_vtotal;
6651 mode->vsync_start = pipe_config->base.adjusted_mode.crtc_vsync_start;
6652 mode->vsync_end = pipe_config->base.adjusted_mode.crtc_vsync_end;
babea61d 6653
2d112de7 6654 mode->flags = pipe_config->base.adjusted_mode.flags;
babea61d 6655
2d112de7
ACO		 6656 mode->clock = pipe_config->base.adjusted_mode.crtc_clock;
6657 mode->flags |= pipe_config->base.adjusted_mode.flags;
babea61d
JB		 6658}
6659
84b046f3
DV		 6660static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
6661{
6662 struct drm_device *dev = intel_crtc->base.dev;
6663 struct drm_i915_private *dev_priv = dev->dev_private;
6664 uint32_t pipeconf;
6665
9f11a9e4 6666 pipeconf = 0;
84b046f3 6667
b6b5d049
VS		 6668 if ((intel_crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
6669 (intel_crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
6670 pipeconf |= I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE;
67c72a12 6671
6e3c9717 6672 if (intel_crtc->config->double_wide)
cf532bb2 6673 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 6674
ff9ce46e
DV		 6675 /* only g4x and later have fancy bpc/dither controls */
6676 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e 6677 /* Bspec claims that we can't use dithering for 30bpp pipes. */
6e3c9717 6678 if (intel_crtc->config->dither && intel_crtc->config->pipe_bpp != 30)
ff9ce46e 6679 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 6680 PIPECONF_DITHER_TYPE_SP;
84b046f3 6681
6e3c9717 6682 switch (intel_crtc->config->pipe_bpp) {
ff9ce46e
DV		 6683 case 18:
6684 pipeconf |= PIPECONF_6BPC;
6685 break;
6686 case 24:
6687 pipeconf |= PIPECONF_8BPC;
6688 break;
6689 case 30:
6690 pipeconf |= PIPECONF_10BPC;
6691 break;
6692 default:
6693 /* Case prevented by intel_choose_pipe_bpp_dither. */
6694 BUG();
84b046f3
DV		 6695 }
6696 }
6697
6698 if (HAS_PIPE_CXSR(dev)) {
6699 if (intel_crtc->lowfreq_avail) {
6700 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
6701 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
6702 } else {
6703 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 6704 }
6705 }
6706
6e3c9717 6707 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
efc2cfff 6708 if (INTEL_INFO(dev)->gen < 4 ||
409ee761 6709 intel_pipe_has_type(intel_crtc, INTEL_OUTPUT_SDVO))
efc2cfff
VS		 6710 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
6711 else
6712 pipeconf |= PIPECONF_INTERLACE_W_SYNC_SHIFT;
6713 } else
84b046f3
DV		 6714 pipeconf |= PIPECONF_PROGRESSIVE;
6715
6e3c9717 6716 if (IS_VALLEYVIEW(dev) && intel_crtc->config->limited_color_range)
9f11a9e4 6717 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 6718
84b046f3
DV		 6719 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
6720 POSTING_READ(PIPECONF(intel_crtc->pipe));
6721}
6722
190f68c5
ACO		 6723static int i9xx_crtc_compute_clock(struct intel_crtc *crtc,
6724 struct intel_crtc_state *crtc_state)
79e53945 6725{
c7653199 6726 struct drm_device *dev = crtc->base.dev;
79e53945 6727 struct drm_i915_private *dev_priv = dev->dev_private;
c751ce4f 6728 int refclk, num_connectors = 0;
652c393a 6729 intel_clock_t clock, reduced_clock;
a16af721 6730 bool ok, has_reduced_clock = false;
e9fd1c02 6731 bool is_lvds = false, is_dsi = false;
5eddb70b 6732 struct intel_encoder *encoder;
d4906093 6733 const intel_limit_t *limit;
79e53945 6734
d0737e1d
ACO		 6735 for_each_intel_encoder(dev, encoder) {
6736 if (encoder->new_crtc != crtc)
6737 continue;
6738
5eddb70b 6739 switch (encoder->type) {
79e53945
JB		 6740 case INTEL_OUTPUT_LVDS:
6741 is_lvds = true;
6742 break;
e9fd1c02
JN		 6743 case INTEL_OUTPUT_DSI:
6744 is_dsi = true;
6745 break;
6847d71b
PZ		 6746 default:
6747 break;
79e53945 6748 }
43565a06 6749
c751ce4f 6750 num_connectors++;
79e53945
JB		 6751 }
6752
f2335330 6753 if (is_dsi)
5b18e57c 6754 return 0;
f2335330 6755
190f68c5 6756 if (!crtc_state->clock_set) {
409ee761 6757 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 6758
e9fd1c02
JN		 6759 /*
6760 * Returns a set of divisors for the desired target clock with
6761 * the given refclk, or FALSE. The returned values represent
6762 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
6763 * 2) / p1 / p2.
6764 */
409ee761 6765 limit = intel_limit(crtc, refclk);
c7653199 6766 ok = dev_priv->display.find_dpll(limit, crtc,
190f68c5 6767 crtc_state->port_clock,
e9fd1c02 6768 refclk, NULL, &clock);
f2335330 6769 if (!ok) {
e9fd1c02
JN		 6770 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6771 return -EINVAL;
6772 }
79e53945 6773
f2335330
JN		 6774 if (is_lvds && dev_priv->lvds_downclock_avail) {
6775 /*
6776 * Ensure we match the reduced clock's P to the target
6777 * clock. If the clocks don't match, we can't switch
6778 * the display clock by using the FP0/FP1. In such case
6779 * we will disable the LVDS downclock feature.
6780 */
6781 has_reduced_clock =
c7653199 6782 dev_priv->display.find_dpll(limit, crtc,
f2335330
JN		 6783 dev_priv->lvds_downclock,
6784 refclk, &clock,
6785 &reduced_clock);
6786 }
6787 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 6788 crtc_state->dpll.n = clock.n;
6789 crtc_state->dpll.m1 = clock.m1;
6790 crtc_state->dpll.m2 = clock.m2;
6791 crtc_state->dpll.p1 = clock.p1;
6792 crtc_state->dpll.p2 = clock.p2;
f47709a9 6793 }
7026d4ac 6794
e9fd1c02 6795 if (IS_GEN2(dev)) {
190f68c5 6796 i8xx_update_pll(crtc, crtc_state,
2a8f64ca
VP		 6797 has_reduced_clock ? &reduced_clock : NULL,
6798 num_connectors);
9d556c99 6799 } else if (IS_CHERRYVIEW(dev)) {
190f68c5 6800 chv_update_pll(crtc, crtc_state);
e9fd1c02 6801 } else if (IS_VALLEYVIEW(dev)) {
190f68c5 6802 vlv_update_pll(crtc, crtc_state);
e9fd1c02 6803 } else {
190f68c5 6804 i9xx_update_pll(crtc, crtc_state,
eb1cbe48 6805 has_reduced_clock ? &reduced_clock : NULL,
eba905b2 6806 num_connectors);
e9fd1c02 6807 }
79e53945 6808
c8f7a0db 6809 return 0;
f564048e
EA		 6810}
6811
2fa2fe9a 6812static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5cec258b 6813 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 6814{
6815 struct drm_device *dev = crtc->base.dev;
6816 struct drm_i915_private *dev_priv = dev->dev_private;
6817 uint32_t tmp;
6818
dc9e7dec
VS		 6819 if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev)))
6820 return;
6821
2fa2fe9a 6822 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 6823 if (!(tmp & PFIT_ENABLE))
6824 return;
2fa2fe9a 6825
06922821 6826 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 6827 if (INTEL_INFO(dev)->gen < 4) {
6828 if (crtc->pipe != PIPE_B)
6829 return;
2fa2fe9a
DV		 6830 } else {
6831 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
6832 return;
6833 }
6834
06922821 6835 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 6836 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
6837 if (INTEL_INFO(dev)->gen < 5)
6838 pipe_config->gmch_pfit.lvds_border_bits =
6839 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
6840}
6841
acbec814 6842static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 6843 struct intel_crtc_state *pipe_config)
acbec814
JB		 6844{
6845 struct drm_device *dev = crtc->base.dev;
6846 struct drm_i915_private *dev_priv = dev->dev_private;
6847 int pipe = pipe_config->cpu_transcoder;
6848 intel_clock_t clock;
6849 u32 mdiv;
662c6ecb 6850 int refclk = 100000;
acbec814 6851
f573de5a
SK		 6852 /* In case of MIPI DPLL will not even be used */
6853 if (!(pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE))
6854 return;
6855
acbec814 6856 mutex_lock(&dev_priv->dpio_lock);
ab3c759a 6857 mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
acbec814
JB		 6858 mutex_unlock(&dev_priv->dpio_lock);
6859
6860 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
6861 clock.m2 = mdiv & DPIO_M2DIV_MASK;
6862 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
6863 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
6864 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
6865
f646628b 6866 vlv_clock(refclk, &clock);
acbec814 6867
f646628b
VS		 6868 /* clock.dot is the fast clock */
6869 pipe_config->port_clock = clock.dot / 5;
acbec814
JB		 6870}
6871
5724dbd1
DL		 6872static void
6873i9xx_get_initial_plane_config(struct intel_crtc *crtc,
6874 struct intel_initial_plane_config *plane_config)
1ad292b5
JB		 6875{
6876 struct drm_device *dev = crtc->base.dev;
6877 struct drm_i915_private *dev_priv = dev->dev_private;
6878 u32 val, base, offset;
6879 int pipe = crtc->pipe, plane = crtc->plane;
6880 int fourcc, pixel_format;
6761dd31 6881 unsigned int aligned_height;
b113d5ee 6882 struct drm_framebuffer *fb;
1b842c89 6883 struct intel_framebuffer *intel_fb;
1ad292b5 6884
42a7b088
DL		 6885 val = I915_READ(DSPCNTR(plane));
6886 if (!(val & DISPLAY_PLANE_ENABLE))
6887 return;
6888
d9806c9f 6889 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 6890 if (!intel_fb) {
1ad292b5
JB		 6891 DRM_DEBUG_KMS("failed to alloc fb\n");
6892 return;
6893 }
6894
1b842c89
DL		 6895 fb = &intel_fb->base;
6896
18c5247e
DV		 6897 if (INTEL_INFO(dev)->gen >= 4) {
6898 if (val & DISPPLANE_TILED) {
49af449b 6899 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 6900 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
6901 }
6902 }
1ad292b5
JB		 6903
6904 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 6905 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 6906 fb->pixel_format = fourcc;
6907 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
1ad292b5
JB		 6908
6909 if (INTEL_INFO(dev)->gen >= 4) {
49af449b 6910 if (plane_config->tiling)
1ad292b5
JB		 6911 offset = I915_READ(DSPTILEOFF(plane));
6912 else
6913 offset = I915_READ(DSPLINOFF(plane));
6914 base = I915_READ(DSPSURF(plane)) & 0xfffff000;
6915 } else {
6916 base = I915_READ(DSPADDR(plane));
6917 }
6918 plane_config->base = base;
6919
6920 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 6921 fb->width = ((val >> 16) & 0xfff) + 1;
6922 fb->height = ((val >> 0) & 0xfff) + 1;
1ad292b5
JB		 6923
6924 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 6925 fb->pitches[0] = val & 0xffffffc0;
1ad292b5 6926
b113d5ee 6927 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 6928 fb->pixel_format,
6929 fb->modifier[0]);
1ad292b5 6930
f37b5c2b 6931 plane_config->size = fb->pitches[0] * aligned_height;
1ad292b5 6932
2844a921
DL		 6933 DRM_DEBUG_KMS("pipe/plane %c/%d with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
6934 pipe_name(pipe), plane, fb->width, fb->height,
6935 fb->bits_per_pixel, base, fb->pitches[0],
6936 plane_config->size);
1ad292b5 6937
2d14030b 6938 plane_config->fb = intel_fb;
1ad292b5
JB		 6939}
6940
70b23a98 6941static void chv_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 6942 struct intel_crtc_state *pipe_config)
70b23a98
VS		 6943{
6944 struct drm_device *dev = crtc->base.dev;
6945 struct drm_i915_private *dev_priv = dev->dev_private;
6946 int pipe = pipe_config->cpu_transcoder;
6947 enum dpio_channel port = vlv_pipe_to_channel(pipe);
6948 intel_clock_t clock;
6949 u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2;
6950 int refclk = 100000;
6951
6952 mutex_lock(&dev_priv->dpio_lock);
6953 cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
6954 pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
6955 pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
6956 pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
6957 mutex_unlock(&dev_priv->dpio_lock);
6958
6959 clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
6960 clock.m2 = ((pll_dw0 & 0xff) << 22) | (pll_dw2 & 0x3fffff);
6961 clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
6962 clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
6963 clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
6964
6965 chv_clock(refclk, &clock);
6966
6967 /* clock.dot is the fast clock */
6968 pipe_config->port_clock = clock.dot / 5;
6969}
6970
0e8ffe1b 6971static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5cec258b 6972 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 6973{
6974 struct drm_device *dev = crtc->base.dev;
6975 struct drm_i915_private *dev_priv = dev->dev_private;
6976 uint32_t tmp;
6977
f458ebbc
DV		 6978 if (!intel_display_power_is_enabled(dev_priv,
6979 POWER_DOMAIN_PIPE(crtc->pipe)))
b5482bd0
ID		 6980 return false;
6981
e143a21c 6982 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 6983 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 6984
0e8ffe1b
DV		 6985 tmp = I915_READ(PIPECONF(crtc->pipe));
6986 if (!(tmp & PIPECONF_ENABLE))
6987 return false;
6988
42571aef
VS		 6989 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
6990 switch (tmp & PIPECONF_BPC_MASK) {
6991 case PIPECONF_6BPC:
6992 pipe_config->pipe_bpp = 18;
6993 break;
6994 case PIPECONF_8BPC:
6995 pipe_config->pipe_bpp = 24;
6996 break;
6997 case PIPECONF_10BPC:
6998 pipe_config->pipe_bpp = 30;
6999 break;
7000 default:
7001 break;
7002 }
7003 }
7004
b5a9fa09
DV		 7005 if (IS_VALLEYVIEW(dev) && (tmp & PIPECONF_COLOR_RANGE_SELECT))
7006 pipe_config->limited_color_range = true;
7007
282740f7
VS		 7008 if (INTEL_INFO(dev)->gen < 4)
7009 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
7010
1bd1bd80
DV		 7011 intel_get_pipe_timings(crtc, pipe_config);
7012
2fa2fe9a
DV		 7013 i9xx_get_pfit_config(crtc, pipe_config);
7014
6c49f241
DV		 7015 if (INTEL_INFO(dev)->gen >= 4) {
7016 tmp = I915_READ(DPLL_MD(crtc->pipe));
7017 pipe_config->pixel_multiplier =
7018 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
7019 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 7020 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 7021 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
7022 tmp = I915_READ(DPLL(crtc->pipe));
7023 pipe_config->pixel_multiplier =
7024 ((tmp & SDVO_MULTIPLIER_MASK)
7025 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
7026 } else {
7027 /* Note that on i915G/GM the pixel multiplier is in the sdvo
7028 * port and will be fixed up in the encoder->get_config
7029 * function. */
7030 pipe_config->pixel_multiplier = 1;
7031 }
8bcc2795
DV		 7032 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
7033 if (!IS_VALLEYVIEW(dev)) {
1c4e0274
VS		 7034 /*
7035 * DPLL_DVO_2X_MODE must be enabled for both DPLLs
7036 * on 830. Filter it out here so that we don't
7037 * report errors due to that.
7038 */
7039 if (IS_I830(dev))
7040 pipe_config->dpll_hw_state.dpll &= ~DPLL_DVO_2X_MODE;
7041
8bcc2795
DV		 7042 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
7043 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 7044 } else {
7045 /* Mask out read-only status bits. */
7046 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
7047 DPLL_PORTC_READY_MASK |
7048 DPLL_PORTB_READY_MASK);
8bcc2795 7049 }
6c49f241 7050
70b23a98
VS		 7051 if (IS_CHERRYVIEW(dev))
7052 chv_crtc_clock_get(crtc, pipe_config);
7053 else if (IS_VALLEYVIEW(dev))
acbec814
JB		 7054 vlv_crtc_clock_get(crtc, pipe_config);
7055 else
7056 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 7057
0e8ffe1b
DV		 7058 return true;
7059}
7060
dde86e2d 7061static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 7062{
7063 struct drm_i915_private *dev_priv = dev->dev_private;
13d83a67 7064 struct intel_encoder *encoder;
74cfd7ac 7065 u32 val, final;
13d83a67 7066 bool has_lvds = false;
199e5d79 7067 bool has_cpu_edp = false;
199e5d79 7068 bool has_panel = false;
99eb6a01
KP		 7069 bool has_ck505 = false;
7070 bool can_ssc = false;
13d83a67
JB		 7071
7072 /* We need to take the global config into account */
b2784e15 7073 for_each_intel_encoder(dev, encoder) {
199e5d79
KP		 7074 switch (encoder->type) {
7075 case INTEL_OUTPUT_LVDS:
7076 has_panel = true;
7077 has_lvds = true;
7078 break;
7079 case INTEL_OUTPUT_EDP:
7080 has_panel = true;
2de6905f 7081 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 7082 has_cpu_edp = true;
7083 break;
6847d71b
PZ		 7084 default:
7085 break;
13d83a67
JB		 7086 }
7087 }
7088
99eb6a01 7089 if (HAS_PCH_IBX(dev)) {
41aa3448 7090 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 7091 can_ssc = has_ck505;
7092 } else {
7093 has_ck505 = false;
7094 can_ssc = true;
7095 }
7096
2de6905f
ID		 7097 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
7098 has_panel, has_lvds, has_ck505);
13d83a67
JB		 7099
7100 /* Ironlake: try to setup display ref clock before DPLL
7101 * enabling. This is only under driver's control after
7102 * PCH B stepping, previous chipset stepping should be
7103 * ignoring this setting.
7104 */
74cfd7ac
CW		 7105 val = I915_READ(PCH_DREF_CONTROL);
7106
7107 /* As we must carefully and slowly disable/enable each source in turn,
7108 * compute the final state we want first and check if we need to
7109 * make any changes at all.
7110 */
7111 final = val;
7112 final &= ~DREF_NONSPREAD_SOURCE_MASK;
7113 if (has_ck505)
7114 final |= DREF_NONSPREAD_CK505_ENABLE;
7115 else
7116 final |= DREF_NONSPREAD_SOURCE_ENABLE;
7117
7118 final &= ~DREF_SSC_SOURCE_MASK;
7119 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
7120 final &= ~DREF_SSC1_ENABLE;
7121
7122 if (has_panel) {
7123 final |= DREF_SSC_SOURCE_ENABLE;
7124
7125 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7126 final |= DREF_SSC1_ENABLE;
7127
7128 if (has_cpu_edp) {
7129 if (intel_panel_use_ssc(dev_priv) && can_ssc)
7130 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
7131 else
7132 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
7133 } else
7134 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7135 } else {
7136 final |= DREF_SSC_SOURCE_DISABLE;
7137 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
7138 }
7139
7140 if (final == val)
7141 return;
7142
13d83a67 7143 /* Always enable nonspread source */
74cfd7ac 7144 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 7145
99eb6a01 7146 if (has_ck505)
74cfd7ac 7147 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 7148 else
74cfd7ac 7149 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 7150
199e5d79 7151 if (has_panel) {
74cfd7ac
CW		 7152 val &= ~DREF_SSC_SOURCE_MASK;
7153 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 7154
199e5d79 7155 /* SSC must be turned on before enabling the CPU output */
99eb6a01 7156 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7157 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 7158 val |= DREF_SSC1_ENABLE;
e77166b5 7159 } else
74cfd7ac 7160 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 7161
7162 /* Get SSC going before enabling the outputs */
74cfd7ac 7163 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7164 POSTING_READ(PCH_DREF_CONTROL);
7165 udelay(200);
7166
74cfd7ac 7167 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 7168
7169 /* Enable CPU source on CPU attached eDP */
199e5d79 7170 if (has_cpu_edp) {
99eb6a01 7171 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 7172 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 7173 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
eba905b2 7174 } else
74cfd7ac 7175 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 7176 } else
74cfd7ac 7177 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7178
74cfd7ac 7179 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7180 POSTING_READ(PCH_DREF_CONTROL);
7181 udelay(200);
7182 } else {
7183 DRM_DEBUG_KMS("Disabling SSC entirely\n");
7184
74cfd7ac 7185 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 7186
7187 /* Turn off CPU output */
74cfd7ac 7188 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 7189
74cfd7ac 7190 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 7191 POSTING_READ(PCH_DREF_CONTROL);
7192 udelay(200);
7193
7194 /* Turn off the SSC source */
74cfd7ac
CW		 7195 val &= ~DREF_SSC_SOURCE_MASK;
7196 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 7197
7198 /* Turn off SSC1 */
74cfd7ac 7199 val &= ~DREF_SSC1_ENABLE;
199e5d79 7200
74cfd7ac 7201 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 7202 POSTING_READ(PCH_DREF_CONTROL);
7203 udelay(200);
7204 }
74cfd7ac
CW		 7205
7206 BUG_ON(val != final);
13d83a67
JB		 7207}
7208
f31f2d55 7209static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 7210{
f31f2d55 7211 uint32_t tmp;
dde86e2d 7212
0ff066a9
PZ		 7213 tmp = I915_READ(SOUTH_CHICKEN2);
7214 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
7215 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7216
0ff066a9
PZ		 7217 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
7218 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
7219 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 7220
0ff066a9
PZ		 7221 tmp = I915_READ(SOUTH_CHICKEN2);
7222 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
7223 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 7224
0ff066a9
PZ		 7225 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
7226 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
7227 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 7228}
7229
7230/* WaMPhyProgramming:hsw */
7231static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
7232{
7233 uint32_t tmp;
dde86e2d
PZ		 7234
7235 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
7236 tmp &= ~(0xFF << 24);
7237 tmp |= (0x12 << 24);
7238 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
7239
dde86e2d
PZ		 7240 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
7241 tmp |= (1 << 11);
7242 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
7243
7244 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
7245 tmp |= (1 << 11);
7246 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
7247
dde86e2d
PZ		 7248 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
7249 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7250 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
7251
7252 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
7253 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
7254 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
7255
0ff066a9
PZ		 7256 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
7257 tmp &= ~(7 << 13);
7258 tmp |= (5 << 13);
7259 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 7260
0ff066a9
PZ		 7261 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
7262 tmp &= ~(7 << 13);
7263 tmp |= (5 << 13);
7264 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 7265
7266 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
7267 tmp &= ~0xFF;
7268 tmp |= 0x1C;
7269 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
7270
7271 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
7272 tmp &= ~0xFF;
7273 tmp |= 0x1C;
7274 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
7275
7276 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
7277 tmp &= ~(0xFF << 16);
7278 tmp |= (0x1C << 16);
7279 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
7280
7281 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
7282 tmp &= ~(0xFF << 16);
7283 tmp |= (0x1C << 16);
7284 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
7285
0ff066a9
PZ		 7286 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
7287 tmp |= (1 << 27);
7288 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 7289
0ff066a9
PZ		 7290 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
7291 tmp |= (1 << 27);
7292 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 7293
0ff066a9
PZ		 7294 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
7295 tmp &= ~(0xF << 28);
7296 tmp |= (4 << 28);
7297 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 7298
0ff066a9
PZ		 7299 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
7300 tmp &= ~(0xF << 28);
7301 tmp |= (4 << 28);
7302 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 7303}
7304
2fa86a1f
PZ		 7305/* Implements 3 different sequences from BSpec chapter "Display iCLK
7306 * Programming" based on the parameters passed:
7307 * - Sequence to enable CLKOUT_DP
7308 * - Sequence to enable CLKOUT_DP without spread
7309 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
7310 */
7311static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
7312 bool with_fdi)
f31f2d55
PZ		 7313{
7314 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 7315 uint32_t reg, tmp;
7316
7317 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
7318 with_spread = true;
7319 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
7320 with_fdi, "LP PCH doesn't have FDI\n"))
7321 with_fdi = false;
f31f2d55
PZ		 7322
7323 mutex_lock(&dev_priv->dpio_lock);
7324
7325 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7326 tmp &= ~SBI_SSCCTL_DISABLE;
7327 tmp |= SBI_SSCCTL_PATHALT;
7328 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7329
7330 udelay(24);
7331
2fa86a1f
PZ		 7332 if (with_spread) {
7333 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7334 tmp &= ~SBI_SSCCTL_PATHALT;
7335 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 7336
2fa86a1f
PZ		 7337 if (with_fdi) {
7338 lpt_reset_fdi_mphy(dev_priv);
7339 lpt_program_fdi_mphy(dev_priv);
7340 }
7341 }
dde86e2d 7342
2fa86a1f
PZ		 7343 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7344 SBI_GEN0 : SBI_DBUFF0;
7345 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7346 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7347 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 7348
7349 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 7350}
7351
47701c3b
PZ		 7352/* Sequence to disable CLKOUT_DP */
7353static void lpt_disable_clkout_dp(struct drm_device *dev)
7354{
7355 struct drm_i915_private *dev_priv = dev->dev_private;
7356 uint32_t reg, tmp;
7357
7358 mutex_lock(&dev_priv->dpio_lock);
7359
7360 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
7361 SBI_GEN0 : SBI_DBUFF0;
7362 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
7363 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
7364 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
7365
7366 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
7367 if (!(tmp & SBI_SSCCTL_DISABLE)) {
7368 if (!(tmp & SBI_SSCCTL_PATHALT)) {
7369 tmp |= SBI_SSCCTL_PATHALT;
7370 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7371 udelay(32);
7372 }
7373 tmp |= SBI_SSCCTL_DISABLE;
7374 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
7375 }
7376
7377 mutex_unlock(&dev_priv->dpio_lock);
7378}
7379
bf8fa3d3
PZ		 7380static void lpt_init_pch_refclk(struct drm_device *dev)
7381{
bf8fa3d3
PZ		 7382 struct intel_encoder *encoder;
7383 bool has_vga = false;
7384
b2784e15 7385 for_each_intel_encoder(dev, encoder) {
bf8fa3d3
PZ		 7386 switch (encoder->type) {
7387 case INTEL_OUTPUT_ANALOG:
7388 has_vga = true;
7389 break;
6847d71b
PZ		 7390 default:
7391 break;
bf8fa3d3
PZ		 7392 }
7393 }
7394
47701c3b
PZ		 7395 if (has_vga)
7396 lpt_enable_clkout_dp(dev, true, true);
7397 else
7398 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 7399}
7400
dde86e2d
PZ		 7401/*
7402 * Initialize reference clocks when the driver loads
7403 */
7404void intel_init_pch_refclk(struct drm_device *dev)
7405{
7406 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7407 ironlake_init_pch_refclk(dev);
7408 else if (HAS_PCH_LPT(dev))
7409 lpt_init_pch_refclk(dev);
7410}
7411
d9d444cb
JB		 7412static int ironlake_get_refclk(struct drm_crtc *crtc)
7413{
7414 struct drm_device *dev = crtc->dev;
7415 struct drm_i915_private *dev_priv = dev->dev_private;
7416 struct intel_encoder *encoder;
d9d444cb
JB		 7417 int num_connectors = 0;
7418 bool is_lvds = false;
7419
d0737e1d
ACO		 7420 for_each_intel_encoder(dev, encoder) {
7421 if (encoder->new_crtc != to_intel_crtc(crtc))
7422 continue;
7423
d9d444cb
JB		 7424 switch (encoder->type) {
7425 case INTEL_OUTPUT_LVDS:
7426 is_lvds = true;
7427 break;
6847d71b
PZ		 7428 default:
7429 break;
d9d444cb
JB		 7430 }
7431 num_connectors++;
7432 }
7433
7434 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
e91e941b 7435 DRM_DEBUG_KMS("using SSC reference clock of %d kHz\n",
41aa3448 7436 dev_priv->vbt.lvds_ssc_freq);
e91e941b 7437 return dev_priv->vbt.lvds_ssc_freq;
d9d444cb
JB		 7438 }
7439
7440 return 120000;
7441}
7442
6ff93609 7443static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 7444{
c8203565 7445 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 7446 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7447 int pipe = intel_crtc->pipe;
c8203565
PZ		 7448 uint32_t val;
7449
78114071 7450 val = 0;
c8203565 7451
6e3c9717 7452 switch (intel_crtc->config->pipe_bpp) {
c8203565 7453 case 18:
dfd07d72 7454 val |= PIPECONF_6BPC;
c8203565
PZ		 7455 break;
7456 case 24:
dfd07d72 7457 val |= PIPECONF_8BPC;
c8203565
PZ		 7458 break;
7459 case 30:
dfd07d72 7460 val |= PIPECONF_10BPC;
c8203565
PZ		 7461 break;
7462 case 36:
dfd07d72 7463 val |= PIPECONF_12BPC;
c8203565
PZ		 7464 break;
7465 default:
cc769b62
PZ		 7466 /* Case prevented by intel_choose_pipe_bpp_dither. */
7467 BUG();
c8203565
PZ		 7468 }
7469
6e3c9717 7470 if (intel_crtc->config->dither)
c8203565
PZ		 7471 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7472
6e3c9717 7473 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 7474 val |= PIPECONF_INTERLACED_ILK;
7475 else
7476 val |= PIPECONF_PROGRESSIVE;
7477
6e3c9717 7478 if (intel_crtc->config->limited_color_range)
3685a8f3 7479 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 7480
c8203565
PZ		 7481 I915_WRITE(PIPECONF(pipe), val);
7482 POSTING_READ(PIPECONF(pipe));
7483}
7484
86d3efce
VS		 7485/*
7486 * Set up the pipe CSC unit.
7487 *
7488 * Currently only full range RGB to limited range RGB conversion
7489 * is supported, but eventually this should handle various
7490 * RGB<->YCbCr scenarios as well.
7491 */
50f3b016 7492static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 7493{
7494 struct drm_device *dev = crtc->dev;
7495 struct drm_i915_private *dev_priv = dev->dev_private;
7496 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7497 int pipe = intel_crtc->pipe;
7498 uint16_t coeff = 0x7800; /* 1.0 */
7499
7500 /*
7501 * TODO: Check what kind of values actually come out of the pipe
7502 * with these coeff/postoff values and adjust to get the best
7503 * accuracy. Perhaps we even need to take the bpc value into
7504 * consideration.
7505 */
7506
6e3c9717 7507 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 7508 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
7509
7510 /*
7511 * GY/GU and RY/RU should be the other way around according
7512 * to BSpec, but reality doesn't agree. Just set them up in
7513 * a way that results in the correct picture.
7514 */
7515 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
7516 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
7517
7518 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
7519 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
7520
7521 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
7522 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
7523
7524 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
7525 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
7526 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
7527
7528 if (INTEL_INFO(dev)->gen > 6) {
7529 uint16_t postoff = 0;
7530
6e3c9717 7531 if (intel_crtc->config->limited_color_range)
32cf0cb0 7532 postoff = (16 * (1 << 12) / 255) & 0x1fff;
86d3efce
VS		 7533
7534 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
7535 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
7536 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
7537
7538 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
7539 } else {
7540 uint32_t mode = CSC_MODE_YUV_TO_RGB;
7541
6e3c9717 7542 if (intel_crtc->config->limited_color_range)
86d3efce
VS		 7543 mode |= CSC_BLACK_SCREEN_OFFSET;
7544
7545 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
7546 }
7547}
7548
6ff93609 7549static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38 7550{
756f85cf
PZ		 7551 struct drm_device *dev = crtc->dev;
7552 struct drm_i915_private *dev_priv = dev->dev_private;
ee2b0b38 7553 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
756f85cf 7554 enum pipe pipe = intel_crtc->pipe;
6e3c9717 7555 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
ee2b0b38
PZ		 7556 uint32_t val;
7557
3eff4faa 7558 val = 0;
ee2b0b38 7559
6e3c9717 7560 if (IS_HASWELL(dev) && intel_crtc->config->dither)
ee2b0b38
PZ		 7561 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
7562
6e3c9717 7563 if (intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 7564 val |= PIPECONF_INTERLACED_ILK;
7565 else
7566 val |= PIPECONF_PROGRESSIVE;
7567
702e7a56
PZ		 7568 I915_WRITE(PIPECONF(cpu_transcoder), val);
7569 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 7570
7571 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
7572 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
756f85cf 7573
3cdf122c 7574 if (IS_BROADWELL(dev) || INTEL_INFO(dev)->gen >= 9) {
756f85cf
PZ		 7575 val = 0;
7576
6e3c9717 7577 switch (intel_crtc->config->pipe_bpp) {
756f85cf
PZ		 7578 case 18:
7579 val |= PIPEMISC_DITHER_6_BPC;
7580 break;
7581 case 24:
7582 val |= PIPEMISC_DITHER_8_BPC;
7583 break;
7584 case 30:
7585 val |= PIPEMISC_DITHER_10_BPC;
7586 break;
7587 case 36:
7588 val |= PIPEMISC_DITHER_12_BPC;
7589 break;
7590 default:
7591 /* Case prevented by pipe_config_set_bpp. */
7592 BUG();
7593 }
7594
6e3c9717 7595 if (intel_crtc->config->dither)
756f85cf
PZ		 7596 val |= PIPEMISC_DITHER_ENABLE | PIPEMISC_DITHER_TYPE_SP;
7597
7598 I915_WRITE(PIPEMISC(pipe), val);
7599 }
ee2b0b38
PZ		 7600}
7601
6591c6e4 7602static bool ironlake_compute_clocks(struct drm_crtc *crtc,
190f68c5 7603 struct intel_crtc_state *crtc_state,
6591c6e4
PZ		 7604 intel_clock_t *clock,
7605 bool *has_reduced_clock,
7606 intel_clock_t *reduced_clock)
7607{
7608 struct drm_device *dev = crtc->dev;
7609 struct drm_i915_private *dev_priv = dev->dev_private;
a919ff14 7610 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6591c6e4 7611 int refclk;
d4906093 7612 const intel_limit_t *limit;
a16af721 7613 bool ret, is_lvds = false;
79e53945 7614
d0737e1d 7615 is_lvds = intel_pipe_will_have_type(intel_crtc, INTEL_OUTPUT_LVDS);
79e53945 7616
d9d444cb 7617 refclk = ironlake_get_refclk(crtc);
79e53945 7618
d4906093
ML		 7619 /*
7620 * Returns a set of divisors for the desired target clock with the given
7621 * refclk, or FALSE. The returned values represent the clock equation:
7622 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
7623 */
409ee761 7624 limit = intel_limit(intel_crtc, refclk);
a919ff14 7625 ret = dev_priv->display.find_dpll(limit, intel_crtc,
190f68c5 7626 crtc_state->port_clock,
ee9300bb 7627 refclk, NULL, clock);
6591c6e4
PZ		 7628 if (!ret)
7629 return false;
cda4b7d3 7630
ddc9003c 7631 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 7632 /*
7633 * Ensure we match the reduced clock's P to the target clock.
7634 * If the clocks don't match, we can't switch the display clock
7635 * by using the FP0/FP1. In such case we will disable the LVDS
7636 * downclock feature.
7637 */
ee9300bb 7638 *has_reduced_clock =
a919ff14 7639 dev_priv->display.find_dpll(limit, intel_crtc,
ee9300bb
DV		 7640 dev_priv->lvds_downclock,
7641 refclk, clock,
7642 reduced_clock);
652c393a 7643 }
61e9653f 7644
6591c6e4
PZ		 7645 return true;
7646}
7647
d4b1931c
PZ		 7648int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
7649{
7650 /*
7651 * Account for spread spectrum to avoid
7652 * oversubscribing the link. Max center spread
7653 * is 2.5%; use 5% for safety's sake.
7654 */
7655 u32 bps = target_clock * bpp * 21 / 20;
619d4d04 7656 return DIV_ROUND_UP(bps, link_bw * 8);
d4b1931c
PZ		 7657}
7658
7429e9d4 7659static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 7660{
7429e9d4 7661 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 7662}
7663
de13a2e3 7664static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
190f68c5 7665 struct intel_crtc_state *crtc_state,
7429e9d4 7666 u32 *fp,
9a7c7890 7667 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 7668{
de13a2e3 7669 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 7670 struct drm_device *dev = crtc->dev;
7671 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 7672 struct intel_encoder *intel_encoder;
7673 uint32_t dpll;
6cc5f341 7674 int factor, num_connectors = 0;
09ede541 7675 bool is_lvds = false, is_sdvo = false;
79e53945 7676
d0737e1d
ACO		 7677 for_each_intel_encoder(dev, intel_encoder) {
7678 if (intel_encoder->new_crtc != to_intel_crtc(crtc))
7679 continue;
7680
de13a2e3 7681 switch (intel_encoder->type) {
79e53945
JB		 7682 case INTEL_OUTPUT_LVDS:
7683 is_lvds = true;
7684 break;
7685 case INTEL_OUTPUT_SDVO:
7d57382e 7686 case INTEL_OUTPUT_HDMI:
79e53945 7687 is_sdvo = true;
79e53945 7688 break;
6847d71b
PZ		 7689 default:
7690 break;
79e53945 7691 }
43565a06 7692
c751ce4f 7693 num_connectors++;
79e53945 7694 }
79e53945 7695
c1858123 7696 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 7697 factor = 21;
7698 if (is_lvds) {
7699 if ((intel_panel_use_ssc(dev_priv) &&
e91e941b 7700 dev_priv->vbt.lvds_ssc_freq == 100000) ||
f0b44056 7701 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 7702 factor = 25;
190f68c5 7703 } else if (crtc_state->sdvo_tv_clock)
8febb297 7704 factor = 20;
c1858123 7705
190f68c5 7706 if (ironlake_needs_fb_cb_tune(&crtc_state->dpll, factor))
7d0ac5b7 7707 *fp |= FP_CB_TUNE;
2c07245f 7708
9a7c7890
DV		 7709 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
7710 *fp2 |= FP_CB_TUNE;
7711
5eddb70b 7712 dpll = 0;
2c07245f 7713
a07d6787
EA		 7714 if (is_lvds)
7715 dpll |= DPLLB_MODE_LVDS;
7716 else
7717 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 7718
190f68c5 7719 dpll |= (crtc_state->pixel_multiplier - 1)
ef1b460d 7720 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 7721
7722 if (is_sdvo)
4a33e48d 7723 dpll |= DPLL_SDVO_HIGH_SPEED;
190f68c5 7724 if (crtc_state->has_dp_encoder)
4a33e48d 7725 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 7726
a07d6787 7727 /* compute bitmask from p1 value */
190f68c5 7728 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 7729 /* also FPA1 */
190f68c5 7730 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 7731
190f68c5 7732 switch (crtc_state->dpll.p2) {
a07d6787
EA		 7733 case 5:
7734 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
7735 break;
7736 case 7:
7737 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
7738 break;
7739 case 10:
7740 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
7741 break;
7742 case 14:
7743 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
7744 break;
79e53945
JB		 7745 }
7746
b4c09f3b 7747 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 7748 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 7749 else
7750 dpll |= PLL_REF_INPUT_DREFCLK;
7751
959e16d6 7752 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 7753}
7754
190f68c5
ACO		 7755static int ironlake_crtc_compute_clock(struct intel_crtc *crtc,
7756 struct intel_crtc_state *crtc_state)
de13a2e3 7757{
c7653199 7758 struct drm_device *dev = crtc->base.dev;
de13a2e3 7759 intel_clock_t clock, reduced_clock;
cbbab5bd 7760 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 7761 bool ok, has_reduced_clock = false;
8b47047b 7762 bool is_lvds = false;
e2b78267 7763 struct intel_shared_dpll *pll;
de13a2e3 7764
409ee761 7765 is_lvds = intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS);
79e53945 7766
5dc5298b
PZ		 7767 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
7768 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 7769
190f68c5 7770 ok = ironlake_compute_clocks(&crtc->base, crtc_state, &clock,
de13a2e3 7771 &has_reduced_clock, &reduced_clock);
190f68c5 7772 if (!ok && !crtc_state->clock_set) {
de13a2e3
PZ		 7773 DRM_ERROR("Couldn't find PLL settings for mode!\n");
7774 return -EINVAL;
79e53945 7775 }
f47709a9 7776 /* Compat-code for transition, will disappear. */
190f68c5
ACO		 7777 if (!crtc_state->clock_set) {
7778 crtc_state->dpll.n = clock.n;
7779 crtc_state->dpll.m1 = clock.m1;
7780 crtc_state->dpll.m2 = clock.m2;
7781 crtc_state->dpll.p1 = clock.p1;
7782 crtc_state->dpll.p2 = clock.p2;
f47709a9 7783 }
79e53945 7784
5dc5298b 7785 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
190f68c5
ACO		 7786 if (crtc_state->has_pch_encoder) {
7787 fp = i9xx_dpll_compute_fp(&crtc_state->dpll);
cbbab5bd 7788 if (has_reduced_clock)
7429e9d4 7789 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 7790
190f68c5 7791 dpll = ironlake_compute_dpll(crtc, crtc_state,
cbbab5bd
DV		 7792 &fp, &reduced_clock,
7793 has_reduced_clock ? &fp2 : NULL);
7794
190f68c5
ACO		 7795 crtc_state->dpll_hw_state.dpll = dpll;
7796 crtc_state->dpll_hw_state.fp0 = fp;
66e985c0 7797 if (has_reduced_clock)
190f68c5 7798 crtc_state->dpll_hw_state.fp1 = fp2;
66e985c0 7799 else
190f68c5 7800 crtc_state->dpll_hw_state.fp1 = fp;
66e985c0 7801
190f68c5 7802 pll = intel_get_shared_dpll(crtc, crtc_state);
ee7b9f93 7803 if (pll == NULL) {
84f44ce7 7804 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
c7653199 7805 pipe_name(crtc->pipe));
4b645f14
JB		 7806 return -EINVAL;
7807 }
3fb37703 7808 }
79e53945 7809
d330a953 7810 if (is_lvds && has_reduced_clock && i915.powersave)
c7653199 7811 crtc->lowfreq_avail = true;
bcd644e0 7812 else
c7653199 7813 crtc->lowfreq_avail = false;
e2b78267 7814
c8f7a0db 7815 return 0;
79e53945
JB		 7816}
7817
eb14cb74
VS		 7818static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
7819 struct intel_link_m_n *m_n)
7820{
7821 struct drm_device *dev = crtc->base.dev;
7822 struct drm_i915_private *dev_priv = dev->dev_private;
7823 enum pipe pipe = crtc->pipe;
7824
7825 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
7826 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
7827 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
7828 & ~TU_SIZE_MASK;
7829 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
7830 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
7831 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7832}
7833
7834static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
7835 enum transcoder transcoder,
b95af8be
VK		 7836 struct intel_link_m_n *m_n,
7837 struct intel_link_m_n *m2_n2)
72419203
DV		 7838{
7839 struct drm_device *dev = crtc->base.dev;
7840 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 7841 enum pipe pipe = crtc->pipe;
72419203 7842
eb14cb74
VS		 7843 if (INTEL_INFO(dev)->gen >= 5) {
7844 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
7845 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
7846 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
7847 & ~TU_SIZE_MASK;
7848 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
7849 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
7850 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
b95af8be
VK		 7851 /* Read M2_N2 registers only for gen < 8 (M2_N2 available for
7852 * gen < 8) and if DRRS is supported (to make sure the
7853 * registers are not unnecessarily read).
7854 */
7855 if (m2_n2 && INTEL_INFO(dev)->gen < 8 &&
6e3c9717 7856 crtc->config->has_drrs) {
b95af8be
VK		 7857 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder));
7858 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder));
7859 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder))
7860 & ~TU_SIZE_MASK;
7861 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder));
7862 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder))
7863 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7864 }
eb14cb74
VS		 7865 } else {
7866 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
7867 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
7868 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
7869 & ~TU_SIZE_MASK;
7870 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
7871 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
7872 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
7873 }
7874}
7875
7876void intel_dp_get_m_n(struct intel_crtc *crtc,
5cec258b 7877 struct intel_crtc_state *pipe_config)
eb14cb74 7878{
681a8504 7879 if (pipe_config->has_pch_encoder)
eb14cb74
VS		 7880 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
7881 else
7882 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be
VK		 7883 &pipe_config->dp_m_n,
7884 &pipe_config->dp_m2_n2);
eb14cb74 7885}
72419203 7886
eb14cb74 7887static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
5cec258b 7888 struct intel_crtc_state *pipe_config)
eb14cb74
VS		 7889{
7890 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
b95af8be 7891 &pipe_config->fdi_m_n, NULL);
72419203
DV		 7892}
7893
bd2e244f 7894static void skylake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7895 struct intel_crtc_state *pipe_config)
bd2e244f
JB		 7896{
7897 struct drm_device *dev = crtc->base.dev;
7898 struct drm_i915_private *dev_priv = dev->dev_private;
7899 uint32_t tmp;
7900
7901 tmp = I915_READ(PS_CTL(crtc->pipe));
7902
7903 if (tmp & PS_ENABLE) {
7904 pipe_config->pch_pfit.enabled = true;
7905 pipe_config->pch_pfit.pos = I915_READ(PS_WIN_POS(crtc->pipe));
7906 pipe_config->pch_pfit.size = I915_READ(PS_WIN_SZ(crtc->pipe));
7907 }
7908}
7909
5724dbd1
DL		 7910static void
7911skylake_get_initial_plane_config(struct intel_crtc *crtc,
7912 struct intel_initial_plane_config *plane_config)
bc8d7dff
DL		 7913{
7914 struct drm_device *dev = crtc->base.dev;
7915 struct drm_i915_private *dev_priv = dev->dev_private;
40f46283 7916 u32 val, base, offset, stride_mult, tiling;
bc8d7dff
DL		 7917 int pipe = crtc->pipe;
7918 int fourcc, pixel_format;
6761dd31 7919 unsigned int aligned_height;
bc8d7dff 7920 struct drm_framebuffer *fb;
1b842c89 7921 struct intel_framebuffer *intel_fb;
bc8d7dff 7922
d9806c9f 7923 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 7924 if (!intel_fb) {
bc8d7dff
DL		 7925 DRM_DEBUG_KMS("failed to alloc fb\n");
7926 return;
7927 }
7928
1b842c89
DL		 7929 fb = &intel_fb->base;
7930
bc8d7dff 7931 val = I915_READ(PLANE_CTL(pipe, 0));
42a7b088
DL		 7932 if (!(val & PLANE_CTL_ENABLE))
7933 goto error;
7934
bc8d7dff
DL		 7935 pixel_format = val & PLANE_CTL_FORMAT_MASK;
7936 fourcc = skl_format_to_fourcc(pixel_format,
7937 val & PLANE_CTL_ORDER_RGBX,
7938 val & PLANE_CTL_ALPHA_MASK);
7939 fb->pixel_format = fourcc;
7940 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
7941
40f46283
DL		 7942 tiling = val & PLANE_CTL_TILED_MASK;
7943 switch (tiling) {
7944 case PLANE_CTL_TILED_LINEAR:
7945 fb->modifier[0] = DRM_FORMAT_MOD_NONE;
7946 break;
7947 case PLANE_CTL_TILED_X:
7948 plane_config->tiling = I915_TILING_X;
7949 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
7950 break;
7951 case PLANE_CTL_TILED_Y:
7952 fb->modifier[0] = I915_FORMAT_MOD_Y_TILED;
7953 break;
7954 case PLANE_CTL_TILED_YF:
7955 fb->modifier[0] = I915_FORMAT_MOD_Yf_TILED;
7956 break;
7957 default:
7958 MISSING_CASE(tiling);
7959 goto error;
7960 }
7961
bc8d7dff
DL		 7962 base = I915_READ(PLANE_SURF(pipe, 0)) & 0xfffff000;
7963 plane_config->base = base;
7964
7965 offset = I915_READ(PLANE_OFFSET(pipe, 0));
7966
7967 val = I915_READ(PLANE_SIZE(pipe, 0));
7968 fb->height = ((val >> 16) & 0xfff) + 1;
7969 fb->width = ((val >> 0) & 0x1fff) + 1;
7970
7971 val = I915_READ(PLANE_STRIDE(pipe, 0));
40f46283
DL		 7972 stride_mult = intel_fb_stride_alignment(dev, fb->modifier[0],
7973 fb->pixel_format);
bc8d7dff
DL		 7974 fb->pitches[0] = (val & 0x3ff) * stride_mult;
7975
7976 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 7977 fb->pixel_format,
7978 fb->modifier[0]);
bc8d7dff 7979
f37b5c2b 7980 plane_config->size = fb->pitches[0] * aligned_height;
bc8d7dff
DL		 7981
7982 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
7983 pipe_name(pipe), fb->width, fb->height,
7984 fb->bits_per_pixel, base, fb->pitches[0],
7985 plane_config->size);
7986
2d14030b 7987 plane_config->fb = intel_fb;
bc8d7dff
DL		 7988 return;
7989
7990error:
7991 kfree(fb);
7992}
7993
2fa2fe9a 7994static void ironlake_get_pfit_config(struct intel_crtc *crtc,
5cec258b 7995 struct intel_crtc_state *pipe_config)
2fa2fe9a
DV		 7996{
7997 struct drm_device *dev = crtc->base.dev;
7998 struct drm_i915_private *dev_priv = dev->dev_private;
7999 uint32_t tmp;
8000
8001 tmp = I915_READ(PF_CTL(crtc->pipe));
8002
8003 if (tmp & PF_ENABLE) {
fd4daa9c 8004 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 8005 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
8006 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 8007
8008 /* We currently do not free assignements of panel fitters on
8009 * ivb/hsw (since we don't use the higher upscaling modes which
8010 * differentiates them) so just WARN about this case for now. */
8011 if (IS_GEN7(dev)) {
8012 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
8013 PF_PIPE_SEL_IVB(crtc->pipe));
8014 }
2fa2fe9a 8015 }
79e53945
JB		 8016}
8017
5724dbd1
DL		 8018static void
8019ironlake_get_initial_plane_config(struct intel_crtc *crtc,
8020 struct intel_initial_plane_config *plane_config)
4c6baa59
JB		 8021{
8022 struct drm_device *dev = crtc->base.dev;
8023 struct drm_i915_private *dev_priv = dev->dev_private;
8024 u32 val, base, offset;
aeee5a49 8025 int pipe = crtc->pipe;
4c6baa59 8026 int fourcc, pixel_format;
6761dd31 8027 unsigned int aligned_height;
b113d5ee 8028 struct drm_framebuffer *fb;
1b842c89 8029 struct intel_framebuffer *intel_fb;
4c6baa59 8030
42a7b088
DL		 8031 val = I915_READ(DSPCNTR(pipe));
8032 if (!(val & DISPLAY_PLANE_ENABLE))
8033 return;
8034
d9806c9f 8035 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
1b842c89 8036 if (!intel_fb) {
4c6baa59
JB		 8037 DRM_DEBUG_KMS("failed to alloc fb\n");
8038 return;
8039 }
8040
1b842c89
DL		 8041 fb = &intel_fb->base;
8042
18c5247e
DV		 8043 if (INTEL_INFO(dev)->gen >= 4) {
8044 if (val & DISPPLANE_TILED) {
49af449b 8045 plane_config->tiling = I915_TILING_X;
18c5247e
DV		 8046 fb->modifier[0] = I915_FORMAT_MOD_X_TILED;
8047 }
8048 }
4c6baa59
JB		 8049
8050 pixel_format = val & DISPPLANE_PIXFORMAT_MASK;
b35d63fa 8051 fourcc = i9xx_format_to_fourcc(pixel_format);
b113d5ee
DL		 8052 fb->pixel_format = fourcc;
8053 fb->bits_per_pixel = drm_format_plane_cpp(fourcc, 0) * 8;
4c6baa59 8054
aeee5a49 8055 base = I915_READ(DSPSURF(pipe)) & 0xfffff000;
4c6baa59 8056 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
aeee5a49 8057 offset = I915_READ(DSPOFFSET(pipe));
4c6baa59 8058 } else {
49af449b 8059 if (plane_config->tiling)
aeee5a49 8060 offset = I915_READ(DSPTILEOFF(pipe));
4c6baa59 8061 else
aeee5a49 8062 offset = I915_READ(DSPLINOFF(pipe));
4c6baa59
JB		 8063 }
8064 plane_config->base = base;
8065
8066 val = I915_READ(PIPESRC(pipe));
b113d5ee
DL		 8067 fb->width = ((val >> 16) & 0xfff) + 1;
8068 fb->height = ((val >> 0) & 0xfff) + 1;
4c6baa59
JB		 8069
8070 val = I915_READ(DSPSTRIDE(pipe));
b113d5ee 8071 fb->pitches[0] = val & 0xffffffc0;
4c6baa59 8072
b113d5ee 8073 aligned_height = intel_fb_align_height(dev, fb->height,
091df6cb
DV		 8074 fb->pixel_format,
8075 fb->modifier[0]);
4c6baa59 8076
f37b5c2b 8077 plane_config->size = fb->pitches[0] * aligned_height;
4c6baa59 8078
2844a921
DL		 8079 DRM_DEBUG_KMS("pipe %c with fb: size=%dx%d@%d, offset=%x, pitch %d, size 0x%x\n",
8080 pipe_name(pipe), fb->width, fb->height,
8081 fb->bits_per_pixel, base, fb->pitches[0],
8082 plane_config->size);
b113d5ee 8083
2d14030b 8084 plane_config->fb = intel_fb;
4c6baa59
JB		 8085}
8086
0e8ffe1b 8087static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8088 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8089{
8090 struct drm_device *dev = crtc->base.dev;
8091 struct drm_i915_private *dev_priv = dev->dev_private;
8092 uint32_t tmp;
8093
f458ebbc
DV		 8094 if (!intel_display_power_is_enabled(dev_priv,
8095 POWER_DOMAIN_PIPE(crtc->pipe)))
930e8c9e
PZ		 8096 return false;
8097
e143a21c 8098 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 8099 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 8100
0e8ffe1b
DV		 8101 tmp = I915_READ(PIPECONF(crtc->pipe));
8102 if (!(tmp & PIPECONF_ENABLE))
8103 return false;
8104
42571aef
VS		 8105 switch (tmp & PIPECONF_BPC_MASK) {
8106 case PIPECONF_6BPC:
8107 pipe_config->pipe_bpp = 18;
8108 break;
8109 case PIPECONF_8BPC:
8110 pipe_config->pipe_bpp = 24;
8111 break;
8112 case PIPECONF_10BPC:
8113 pipe_config->pipe_bpp = 30;
8114 break;
8115 case PIPECONF_12BPC:
8116 pipe_config->pipe_bpp = 36;
8117 break;
8118 default:
8119 break;
8120 }
8121
b5a9fa09
DV		 8122 if (tmp & PIPECONF_COLOR_RANGE_SELECT)
8123 pipe_config->limited_color_range = true;
8124
ab9412ba 8125 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 8126 struct intel_shared_dpll *pll;
8127
88adfff1
DV		 8128 pipe_config->has_pch_encoder = true;
8129
627eb5a3
DV		 8130 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
8131 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8132 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 8133
8134 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 8135
c0d43d62 8136 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 8137 pipe_config->shared_dpll =
8138 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 8139 } else {
8140 tmp = I915_READ(PCH_DPLL_SEL);
8141 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
8142 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
8143 else
8144 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
8145 }
66e985c0
DV		 8146
8147 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8148
8149 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8150 &pipe_config->dpll_hw_state));
c93f54cf
DV		 8151
8152 tmp = pipe_config->dpll_hw_state.dpll;
8153 pipe_config->pixel_multiplier =
8154 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
8155 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 8156
8157 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 8158 } else {
8159 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 8160 }
8161
1bd1bd80
DV		 8162 intel_get_pipe_timings(crtc, pipe_config);
8163
2fa2fe9a
DV		 8164 ironlake_get_pfit_config(crtc, pipe_config);
8165
0e8ffe1b
DV		 8166 return true;
8167}
8168
be256dc7
PZ		 8169static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
8170{
8171 struct drm_device *dev = dev_priv->dev;
be256dc7 8172 struct intel_crtc *crtc;
be256dc7 8173
d3fcc808 8174 for_each_intel_crtc(dev, crtc)
e2c719b7 8175 I915_STATE_WARN(crtc->active, "CRTC for pipe %c enabled\n",
be256dc7
PZ		 8176 pipe_name(crtc->pipe));
8177
e2c719b7
RC		 8178 I915_STATE_WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
8179 I915_STATE_WARN(I915_READ(SPLL_CTL) & SPLL_PLL_ENABLE, "SPLL enabled\n");
8180 I915_STATE_WARN(I915_READ(WRPLL_CTL1) & WRPLL_PLL_ENABLE, "WRPLL1 enabled\n");
8181 I915_STATE_WARN(I915_READ(WRPLL_CTL2) & WRPLL_PLL_ENABLE, "WRPLL2 enabled\n");
8182 I915_STATE_WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
8183 I915_STATE_WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
be256dc7 8184 "CPU PWM1 enabled\n");
c5107b87 8185 if (IS_HASWELL(dev))
e2c719b7 8186 I915_STATE_WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
c5107b87 8187 "CPU PWM2 enabled\n");
e2c719b7 8188 I915_STATE_WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
be256dc7 8189 "PCH PWM1 enabled\n");
e2c719b7 8190 I915_STATE_WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
be256dc7 8191 "Utility pin enabled\n");
e2c719b7 8192 I915_STATE_WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
be256dc7 8193
9926ada1
PZ		 8194 /*
8195 * In theory we can still leave IRQs enabled, as long as only the HPD
8196 * interrupts remain enabled. We used to check for that, but since it's
8197 * gen-specific and since we only disable LCPLL after we fully disable
8198 * the interrupts, the check below should be enough.
8199 */
e2c719b7 8200 I915_STATE_WARN(intel_irqs_enabled(dev_priv), "IRQs enabled\n");
be256dc7
PZ		 8201}
8202
9ccd5aeb
PZ		 8203static uint32_t hsw_read_dcomp(struct drm_i915_private *dev_priv)
8204{
8205 struct drm_device *dev = dev_priv->dev;
8206
8207 if (IS_HASWELL(dev))
8208 return I915_READ(D_COMP_HSW);
8209 else
8210 return I915_READ(D_COMP_BDW);
8211}
8212
3c4c9b81
PZ		 8213static void hsw_write_dcomp(struct drm_i915_private *dev_priv, uint32_t val)
8214{
8215 struct drm_device *dev = dev_priv->dev;
8216
8217 if (IS_HASWELL(dev)) {
8218 mutex_lock(&dev_priv->rps.hw_lock);
8219 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
8220 val))
f475dadf 8221 DRM_ERROR("Failed to write to D_COMP\n");
3c4c9b81
PZ		 8222 mutex_unlock(&dev_priv->rps.hw_lock);
8223 } else {
9ccd5aeb
PZ		 8224 I915_WRITE(D_COMP_BDW, val);
8225 POSTING_READ(D_COMP_BDW);
3c4c9b81 8226 }
be256dc7
PZ		 8227}
8228
8229/*
8230 * This function implements pieces of two sequences from BSpec:
8231 * - Sequence for display software to disable LCPLL
8232 * - Sequence for display software to allow package C8+
8233 * The steps implemented here are just the steps that actually touch the LCPLL
8234 * register. Callers should take care of disabling all the display engine
8235 * functions, doing the mode unset, fixing interrupts, etc.
8236 */
6ff58d53
PZ		 8237static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
8238 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 8239{
8240 uint32_t val;
8241
8242 assert_can_disable_lcpll(dev_priv);
8243
8244 val = I915_READ(LCPLL_CTL);
8245
8246 if (switch_to_fclk) {
8247 val |= LCPLL_CD_SOURCE_FCLK;
8248 I915_WRITE(LCPLL_CTL, val);
8249
8250 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
8251 LCPLL_CD_SOURCE_FCLK_DONE, 1))
8252 DRM_ERROR("Switching to FCLK failed\n");
8253
8254 val = I915_READ(LCPLL_CTL);
8255 }
8256
8257 val |= LCPLL_PLL_DISABLE;
8258 I915_WRITE(LCPLL_CTL, val);
8259 POSTING_READ(LCPLL_CTL);
8260
8261 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
8262 DRM_ERROR("LCPLL still locked\n");
8263
9ccd5aeb 8264 val = hsw_read_dcomp(dev_priv);
be256dc7 8265 val |= D_COMP_COMP_DISABLE;
3c4c9b81 8266 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 8267 ndelay(100);
8268
9ccd5aeb
PZ		 8269 if (wait_for((hsw_read_dcomp(dev_priv) & D_COMP_RCOMP_IN_PROGRESS) == 0,
8270 1))
be256dc7
PZ		 8271 DRM_ERROR("D_COMP RCOMP still in progress\n");
8272
8273 if (allow_power_down) {
8274 val = I915_READ(LCPLL_CTL);
8275 val |= LCPLL_POWER_DOWN_ALLOW;
8276 I915_WRITE(LCPLL_CTL, val);
8277 POSTING_READ(LCPLL_CTL);
8278 }
8279}
8280
8281/*
8282 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
8283 * source.
8284 */
6ff58d53 8285static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 8286{
8287 uint32_t val;
8288
8289 val = I915_READ(LCPLL_CTL);
8290
8291 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
8292 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
8293 return;
8294
a8a8bd54
PZ		 8295 /*
8296 * Make sure we're not on PC8 state before disabling PC8, otherwise
8297 * we'll hang the machine. To prevent PC8 state, just enable force_wake.
a8a8bd54 8298 */
59bad947 8299 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
215733fa 8300
be256dc7
PZ		 8301 if (val & LCPLL_POWER_DOWN_ALLOW) {
8302 val &= ~LCPLL_POWER_DOWN_ALLOW;
8303 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 8304 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 8305 }
8306
9ccd5aeb 8307 val = hsw_read_dcomp(dev_priv);
be256dc7
PZ		 8308 val |= D_COMP_COMP_FORCE;
8309 val &= ~D_COMP_COMP_DISABLE;
3c4c9b81 8310 hsw_write_dcomp(dev_priv, val);
be256dc7
PZ		 8311
8312 val = I915_READ(LCPLL_CTL);
8313 val &= ~LCPLL_PLL_DISABLE;
8314 I915_WRITE(LCPLL_CTL, val);
8315
8316 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
8317 DRM_ERROR("LCPLL not locked yet\n");
8318
8319 if (val & LCPLL_CD_SOURCE_FCLK) {
8320 val = I915_READ(LCPLL_CTL);
8321 val &= ~LCPLL_CD_SOURCE_FCLK;
8322 I915_WRITE(LCPLL_CTL, val);
8323
8324 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
8325 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
8326 DRM_ERROR("Switching back to LCPLL failed\n");
8327 }
215733fa 8328
59bad947 8329 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
be256dc7
PZ		 8330}
8331
765dab67
PZ		 8332/*
8333 * Package states C8 and deeper are really deep PC states that can only be
8334 * reached when all the devices on the system allow it, so even if the graphics
8335 * device allows PC8+, it doesn't mean the system will actually get to these
8336 * states. Our driver only allows PC8+ when going into runtime PM.
8337 *
8338 * The requirements for PC8+ are that all the outputs are disabled, the power
8339 * well is disabled and most interrupts are disabled, and these are also
8340 * requirements for runtime PM. When these conditions are met, we manually do
8341 * the other conditions: disable the interrupts, clocks and switch LCPLL refclk
8342 * to Fclk. If we're in PC8+ and we get an non-hotplug interrupt, we can hard
8343 * hang the machine.
8344 *
8345 * When we really reach PC8 or deeper states (not just when we allow it) we lose
8346 * the state of some registers, so when we come back from PC8+ we need to
8347 * restore this state. We don't get into PC8+ if we're not in RC6, so we don't
8348 * need to take care of the registers kept by RC6. Notice that this happens even
8349 * if we don't put the device in PCI D3 state (which is what currently happens
8350 * because of the runtime PM support).
8351 *
8352 * For more, read "Display Sequences for Package C8" on the hardware
8353 * documentation.
8354 */
a14cb6fc 8355void hsw_enable_pc8(struct drm_i915_private *dev_priv)
c67a470b 8356{
c67a470b
PZ		 8357 struct drm_device *dev = dev_priv->dev;
8358 uint32_t val;
8359
c67a470b
PZ		 8360 DRM_DEBUG_KMS("Enabling package C8+\n");
8361
c67a470b
PZ		 8362 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8363 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8364 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
8365 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8366 }
8367
8368 lpt_disable_clkout_dp(dev);
c67a470b
PZ		 8369 hsw_disable_lcpll(dev_priv, true, true);
8370}
8371
a14cb6fc 8372void hsw_disable_pc8(struct drm_i915_private *dev_priv)
c67a470b
PZ		 8373{
8374 struct drm_device *dev = dev_priv->dev;
8375 uint32_t val;
8376
c67a470b
PZ		 8377 DRM_DEBUG_KMS("Disabling package C8+\n");
8378
8379 hsw_restore_lcpll(dev_priv);
c67a470b
PZ		 8380 lpt_init_pch_refclk(dev);
8381
8382 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
8383 val = I915_READ(SOUTH_DSPCLK_GATE_D);
8384 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
8385 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
8386 }
8387
8388 intel_prepare_ddi(dev);
c67a470b
PZ		 8389}
8390
190f68c5
ACO		 8391static int haswell_crtc_compute_clock(struct intel_crtc *crtc,
8392 struct intel_crtc_state *crtc_state)
09b4ddf9 8393{
190f68c5 8394 if (!intel_ddi_pll_select(crtc, crtc_state))
6441ab5f 8395 return -EINVAL;
716c2e55 8396
c7653199 8397 crtc->lowfreq_avail = false;
644cef34 8398
c8f7a0db 8399 return 0;
79e53945
JB		 8400}
8401
96b7dfb7
S		 8402static void skylake_get_ddi_pll(struct drm_i915_private *dev_priv,
8403 enum port port,
5cec258b 8404 struct intel_crtc_state *pipe_config)
96b7dfb7 8405{
3148ade7 8406 u32 temp, dpll_ctl1;
96b7dfb7
S		 8407
8408 temp = I915_READ(DPLL_CTRL2) & DPLL_CTRL2_DDI_CLK_SEL_MASK(port);
8409 pipe_config->ddi_pll_sel = temp >> (port * 3 + 1);
8410
8411 switch (pipe_config->ddi_pll_sel) {
3148ade7
DL		 8412 case SKL_DPLL0:
8413 /*
8414 * On SKL the eDP DPLL (DPLL0 as we don't use SSC) is not part
8415 * of the shared DPLL framework and thus needs to be read out
8416 * separately
8417 */
8418 dpll_ctl1 = I915_READ(DPLL_CTRL1);
8419 pipe_config->dpll_hw_state.ctrl1 = dpll_ctl1 & 0x3f;
8420 break;
96b7dfb7
S		 8421 case SKL_DPLL1:
8422 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL1;
8423 break;
8424 case SKL_DPLL2:
8425 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL2;
8426 break;
8427 case SKL_DPLL3:
8428 pipe_config->shared_dpll = DPLL_ID_SKL_DPLL3;
8429 break;
96b7dfb7
S		 8430 }
8431}
8432
7d2c8175
DL		 8433static void haswell_get_ddi_pll(struct drm_i915_private *dev_priv,
8434 enum port port,
5cec258b 8435 struct intel_crtc_state *pipe_config)
7d2c8175
DL		 8436{
8437 pipe_config->ddi_pll_sel = I915_READ(PORT_CLK_SEL(port));
8438
8439 switch (pipe_config->ddi_pll_sel) {
8440 case PORT_CLK_SEL_WRPLL1:
8441 pipe_config->shared_dpll = DPLL_ID_WRPLL1;
8442 break;
8443 case PORT_CLK_SEL_WRPLL2:
8444 pipe_config->shared_dpll = DPLL_ID_WRPLL2;
8445 break;
8446 }
8447}
8448
26804afd 8449static void haswell_get_ddi_port_state(struct intel_crtc *crtc,
5cec258b 8450 struct intel_crtc_state *pipe_config)
26804afd
DV		 8451{
8452 struct drm_device *dev = crtc->base.dev;
8453 struct drm_i915_private *dev_priv = dev->dev_private;
d452c5b6 8454 struct intel_shared_dpll *pll;
26804afd
DV		 8455 enum port port;
8456 uint32_t tmp;
8457
8458 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
8459
8460 port = (tmp & TRANS_DDI_PORT_MASK) >> TRANS_DDI_PORT_SHIFT;
8461
96b7dfb7
S		 8462 if (IS_SKYLAKE(dev))
8463 skylake_get_ddi_pll(dev_priv, port, pipe_config);
8464 else
8465 haswell_get_ddi_pll(dev_priv, port, pipe_config);
9cd86933 8466
d452c5b6
DV		 8467 if (pipe_config->shared_dpll >= 0) {
8468 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
8469
8470 WARN_ON(!pll->get_hw_state(dev_priv, pll,
8471 &pipe_config->dpll_hw_state));
8472 }
8473
26804afd
DV		 8474 /*
8475 * Haswell has only FDI/PCH transcoder A. It is which is connected to
8476 * DDI E. So just check whether this pipe is wired to DDI E and whether
8477 * the PCH transcoder is on.
8478 */
ca370455
DL		 8479 if (INTEL_INFO(dev)->gen < 9 &&
8480 (port == PORT_E) && I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
26804afd
DV		 8481 pipe_config->has_pch_encoder = true;
8482
8483 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
8484 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
8485 FDI_DP_PORT_WIDTH_SHIFT) + 1;
8486
8487 ironlake_get_fdi_m_n_config(crtc, pipe_config);
8488 }
8489}
8490
0e8ffe1b 8491static bool haswell_get_pipe_config(struct intel_crtc *crtc,
5cec258b 8492 struct intel_crtc_state *pipe_config)
0e8ffe1b
DV		 8493{
8494 struct drm_device *dev = crtc->base.dev;
8495 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 8496 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 8497 uint32_t tmp;
8498
f458ebbc 8499 if (!intel_display_power_is_enabled(dev_priv,
b5482bd0
ID		 8500 POWER_DOMAIN_PIPE(crtc->pipe)))
8501 return false;
8502
e143a21c 8503 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 8504 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
8505
eccb140b
DV		 8506 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8507 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8508 enum pipe trans_edp_pipe;
8509 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8510 default:
8511 WARN(1, "unknown pipe linked to edp transcoder\n");
8512 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8513 case TRANS_DDI_EDP_INPUT_A_ON:
8514 trans_edp_pipe = PIPE_A;
8515 break;
8516 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8517 trans_edp_pipe = PIPE_B;
8518 break;
8519 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8520 trans_edp_pipe = PIPE_C;
8521 break;
8522 }
8523
8524 if (trans_edp_pipe == crtc->pipe)
8525 pipe_config->cpu_transcoder = TRANSCODER_EDP;
8526 }
8527
f458ebbc 8528 if (!intel_display_power_is_enabled(dev_priv,
eccb140b 8529 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 8530 return false;
8531
eccb140b 8532 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 8533 if (!(tmp & PIPECONF_ENABLE))
8534 return false;
8535
26804afd 8536 haswell_get_ddi_port_state(crtc, pipe_config);
627eb5a3 8537
1bd1bd80
DV		 8538 intel_get_pipe_timings(crtc, pipe_config);
8539
2fa2fe9a 8540 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
bd2e244f
JB		 8541 if (intel_display_power_is_enabled(dev_priv, pfit_domain)) {
8542 if (IS_SKYLAKE(dev))
8543 skylake_get_pfit_config(crtc, pipe_config);
8544 else
8545 ironlake_get_pfit_config(crtc, pipe_config);
8546 }
88adfff1 8547
e59150dc
JB		 8548 if (IS_HASWELL(dev))
8549 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
8550 (I915_READ(IPS_CTL) & IPS_ENABLE);
42db64ef 8551
ebb69c95
CT		 8552 if (pipe_config->cpu_transcoder != TRANSCODER_EDP) {
8553 pipe_config->pixel_multiplier =
8554 I915_READ(PIPE_MULT(pipe_config->cpu_transcoder)) + 1;
8555 } else {
8556 pipe_config->pixel_multiplier = 1;
8557 }
6c49f241 8558
0e8ffe1b
DV		 8559 return true;
8560}
8561
560b85bb
CW		 8562static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
8563{
8564 struct drm_device *dev = crtc->dev;
8565 struct drm_i915_private *dev_priv = dev->dev_private;
8566 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dc41c154 8567 uint32_t cntl = 0, size = 0;
560b85bb 8568
dc41c154 8569 if (base) {
3dd512fb
MR		 8570 unsigned int width = intel_crtc->base.cursor->state->crtc_w;
8571 unsigned int height = intel_crtc->base.cursor->state->crtc_h;
dc41c154
VS		 8572 unsigned int stride = roundup_pow_of_two(width) * 4;
8573
8574 switch (stride) {
8575 default:
8576 WARN_ONCE(1, "Invalid cursor width/stride, width=%u, stride=%u\n",
8577 width, stride);
8578 stride = 256;
8579 /* fallthrough */
8580 case 256:
8581 case 512:
8582 case 1024:
8583 case 2048:
8584 break;
4b0e333e
CW		 8585 }
8586
dc41c154
VS		 8587 cntl |= CURSOR_ENABLE |
8588 CURSOR_GAMMA_ENABLE |
8589 CURSOR_FORMAT_ARGB |
8590 CURSOR_STRIDE(stride);
8591
8592 size = (height << 12) | width;
4b0e333e 8593 }
560b85bb 8594
dc41c154
VS		 8595 if (intel_crtc->cursor_cntl != 0 &&
8596 (intel_crtc->cursor_base != base ||
8597 intel_crtc->cursor_size != size ||
8598 intel_crtc->cursor_cntl != cntl)) {
8599 /* On these chipsets we can only modify the base/size/stride
8600 * whilst the cursor is disabled.
8601 */
8602 I915_WRITE(_CURACNTR, 0);
4b0e333e 8603 POSTING_READ(_CURACNTR);
dc41c154 8604 intel_crtc->cursor_cntl = 0;
4b0e333e 8605 }
560b85bb 8606
99d1f387 8607 if (intel_crtc->cursor_base != base) {
9db4a9c7 8608 I915_WRITE(_CURABASE, base);
99d1f387
VS		 8609 intel_crtc->cursor_base = base;
8610 }
4726e0b0 8611
dc41c154
VS		 8612 if (intel_crtc->cursor_size != size) {
8613 I915_WRITE(CURSIZE, size);
8614 intel_crtc->cursor_size = size;
4b0e333e 8615 }
560b85bb 8616
4b0e333e 8617 if (intel_crtc->cursor_cntl != cntl) {
4b0e333e
CW		 8618 I915_WRITE(_CURACNTR, cntl);
8619 POSTING_READ(_CURACNTR);
4b0e333e 8620 intel_crtc->cursor_cntl = cntl;
560b85bb 8621 }
560b85bb
CW		 8622}
8623
560b85bb 8624static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
65a21cd6
JB		 8625{
8626 struct drm_device *dev = crtc->dev;
8627 struct drm_i915_private *dev_priv = dev->dev_private;
8628 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8629 int pipe = intel_crtc->pipe;
4b0e333e
CW		 8630 uint32_t cntl;
8631
8632 cntl = 0;
8633 if (base) {
8634 cntl = MCURSOR_GAMMA_ENABLE;
3dd512fb 8635 switch (intel_crtc->base.cursor->state->crtc_w) {
4726e0b0
SK		 8636 case 64:
8637 cntl |= CURSOR_MODE_64_ARGB_AX;
8638 break;
8639 case 128:
8640 cntl |= CURSOR_MODE_128_ARGB_AX;
8641 break;
8642 case 256:
8643 cntl |= CURSOR_MODE_256_ARGB_AX;
8644 break;
8645 default:
3dd512fb 8646 MISSING_CASE(intel_crtc->base.cursor->state->crtc_w);
4726e0b0 8647 return;
65a21cd6 8648 }
4b0e333e 8649 cntl |= pipe << 28; /* Connect to correct pipe */
47bf17a7
VS		 8650
8651 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
8652 cntl |= CURSOR_PIPE_CSC_ENABLE;
4b0e333e 8653 }
65a21cd6 8654
8e7d688b 8655 if (crtc->cursor->state->rotation == BIT(DRM_ROTATE_180))
4398ad45
VS		 8656 cntl |= CURSOR_ROTATE_180;
8657
4b0e333e
CW		 8658 if (intel_crtc->cursor_cntl != cntl) {
8659 I915_WRITE(CURCNTR(pipe), cntl);
8660 POSTING_READ(CURCNTR(pipe));
8661 intel_crtc->cursor_cntl = cntl;
65a21cd6 8662 }
4b0e333e 8663
65a21cd6 8664 /* and commit changes on next vblank */
5efb3e28
VS		 8665 I915_WRITE(CURBASE(pipe), base);
8666 POSTING_READ(CURBASE(pipe));
99d1f387
VS		 8667
8668 intel_crtc->cursor_base = base;
65a21cd6
JB		 8669}
8670
cda4b7d3 8671/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 8672static void intel_crtc_update_cursor(struct drm_crtc *crtc,
8673 bool on)
cda4b7d3
CW		 8674{
8675 struct drm_device *dev = crtc->dev;
8676 struct drm_i915_private *dev_priv = dev->dev_private;
8677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8678 int pipe = intel_crtc->pipe;
3d7d6510
MR		 8679 int x = crtc->cursor_x;
8680 int y = crtc->cursor_y;
d6e4db15 8681 u32 base = 0, pos = 0;
cda4b7d3 8682
d6e4db15 8683 if (on)
cda4b7d3 8684 base = intel_crtc->cursor_addr;
cda4b7d3 8685
6e3c9717 8686 if (x >= intel_crtc->config->pipe_src_w)
d6e4db15
VS		 8687 base = 0;
8688
6e3c9717 8689 if (y >= intel_crtc->config->pipe_src_h)
cda4b7d3
CW		 8690 base = 0;
8691
8692 if (x < 0) {
3dd512fb 8693 if (x + intel_crtc->base.cursor->state->crtc_w <= 0)
cda4b7d3
CW		 8694 base = 0;
8695
8696 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
8697 x = -x;
8698 }
8699 pos |= x << CURSOR_X_SHIFT;
8700
8701 if (y < 0) {
3dd512fb 8702 if (y + intel_crtc->base.cursor->state->crtc_h <= 0)
cda4b7d3
CW		 8703 base = 0;
8704
8705 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
8706 y = -y;
8707 }
8708 pos |= y << CURSOR_Y_SHIFT;
8709
4b0e333e 8710 if (base == 0 && intel_crtc->cursor_base == 0)
cda4b7d3
CW		 8711 return;
8712
5efb3e28
VS		 8713 I915_WRITE(CURPOS(pipe), pos);
8714
4398ad45
VS		 8715 /* ILK+ do this automagically */
8716 if (HAS_GMCH_DISPLAY(dev) &&
8e7d688b 8717 crtc->cursor->state->rotation == BIT(DRM_ROTATE_180)) {
3dd512fb
MR		 8718 base += (intel_crtc->base.cursor->state->crtc_h *
8719 intel_crtc->base.cursor->state->crtc_w - 1) * 4;
4398ad45
VS		 8720 }
8721
8ac54669 8722 if (IS_845G(dev) || IS_I865G(dev))
5efb3e28
VS		 8723 i845_update_cursor(crtc, base);
8724 else
8725 i9xx_update_cursor(crtc, base);
cda4b7d3
CW		 8726}
8727
dc41c154
VS		 8728static bool cursor_size_ok(struct drm_device *dev,
8729 uint32_t width, uint32_t height)
8730{
8731 if (width == 0 || height == 0)
8732 return false;
8733
8734 /*
8735 * 845g/865g are special in that they are only limited by
8736 * the width of their cursors, the height is arbitrary up to
8737 * the precision of the register. Everything else requires
8738 * square cursors, limited to a few power-of-two sizes.
8739 */
8740 if (IS_845G(dev) || IS_I865G(dev)) {
8741 if ((width & 63) != 0)
8742 return false;
8743
8744 if (width > (IS_845G(dev) ? 64 : 512))
8745 return false;
8746
8747 if (height > 1023)
8748 return false;
8749 } else {
8750 switch (width | height) {
8751 case 256:
8752 case 128:
8753 if (IS_GEN2(dev))
8754 return false;
8755 case 64:
8756 break;
8757 default:
8758 return false;
8759 }
8760 }
8761
8762 return true;
8763}
8764
79e53945 8765static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 8766 u16 *blue, uint32_t start, uint32_t size)
79e53945 8767{
7203425a 8768 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 8769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 8770
7203425a 8771 for (i = start; i < end; i++) {
79e53945
JB		 8772 intel_crtc->lut_r[i] = red[i] >> 8;
8773 intel_crtc->lut_g[i] = green[i] >> 8;
8774 intel_crtc->lut_b[i] = blue[i] >> 8;
8775 }
8776
8777 intel_crtc_load_lut(crtc);
8778}
8779
79e53945
JB		 8780/* VESA 640x480x72Hz mode to set on the pipe */
8781static struct drm_display_mode load_detect_mode = {
8782 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
8783 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
8784};
8785
a8bb6818
DV		 8786struct drm_framebuffer *
8787__intel_framebuffer_create(struct drm_device *dev,
8788 struct drm_mode_fb_cmd2 *mode_cmd,
8789 struct drm_i915_gem_object *obj)
d2dff872
CW		 8790{
8791 struct intel_framebuffer *intel_fb;
8792 int ret;
8793
8794 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
8795 if (!intel_fb) {
6ccb81f2 8796 drm_gem_object_unreference(&obj->base);
d2dff872
CW		 8797 return ERR_PTR(-ENOMEM);
8798 }
8799
8800 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
dd4916c5
DV		 8801 if (ret)
8802 goto err;
d2dff872
CW		 8803
8804 return &intel_fb->base;
dd4916c5 8805err:
6ccb81f2 8806 drm_gem_object_unreference(&obj->base);
dd4916c5
DV		 8807 kfree(intel_fb);
8808
8809 return ERR_PTR(ret);
d2dff872
CW		 8810}
8811
b5ea642a 8812static struct drm_framebuffer *
a8bb6818
DV		 8813intel_framebuffer_create(struct drm_device *dev,
8814 struct drm_mode_fb_cmd2 *mode_cmd,
8815 struct drm_i915_gem_object *obj)
8816{
8817 struct drm_framebuffer *fb;
8818 int ret;
8819
8820 ret = i915_mutex_lock_interruptible(dev);
8821 if (ret)
8822 return ERR_PTR(ret);
8823 fb = __intel_framebuffer_create(dev, mode_cmd, obj);
8824 mutex_unlock(&dev->struct_mutex);
8825
8826 return fb;
8827}
8828
d2dff872
CW		 8829static u32
8830intel_framebuffer_pitch_for_width(int width, int bpp)
8831{
8832 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
8833 return ALIGN(pitch, 64);
8834}
8835
8836static u32
8837intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
8838{
8839 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
1267a26b 8840 return PAGE_ALIGN(pitch * mode->vdisplay);
d2dff872
CW		 8841}
8842
8843static struct drm_framebuffer *
8844intel_framebuffer_create_for_mode(struct drm_device *dev,
8845 struct drm_display_mode *mode,
8846 int depth, int bpp)
8847{
8848 struct drm_i915_gem_object *obj;
0fed39bd 8849 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 8850
8851 obj = i915_gem_alloc_object(dev,
8852 intel_framebuffer_size_for_mode(mode, bpp));
8853 if (obj == NULL)
8854 return ERR_PTR(-ENOMEM);
8855
8856 mode_cmd.width = mode->hdisplay;
8857 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 8858 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
8859 bpp);
5ca0c34a 8860 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 8861
8862 return intel_framebuffer_create(dev, &mode_cmd, obj);
8863}
8864
8865static struct drm_framebuffer *
8866mode_fits_in_fbdev(struct drm_device *dev,
8867 struct drm_display_mode *mode)
8868{
4520f53a 8869#ifdef CONFIG_DRM_I915_FBDEV
d2dff872
CW		 8870 struct drm_i915_private *dev_priv = dev->dev_private;
8871 struct drm_i915_gem_object *obj;
8872 struct drm_framebuffer *fb;
8873
4c0e5528 8874 if (!dev_priv->fbdev)
d2dff872
CW		 8875 return NULL;
8876
4c0e5528 8877 if (!dev_priv->fbdev->fb)
d2dff872
CW		 8878 return NULL;
8879
4c0e5528
DV		 8880 obj = dev_priv->fbdev->fb->obj;
8881 BUG_ON(!obj);
8882
8bcd4553 8883 fb = &dev_priv->fbdev->fb->base;
01f2c773
VS		 8884 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
8885 fb->bits_per_pixel))
d2dff872
CW		 8886 return NULL;
8887
01f2c773 8888 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 8889 return NULL;
8890
8891 return fb;
4520f53a
DV		 8892#else
8893 return NULL;
8894#endif
d2dff872
CW		 8895}
8896
d2434ab7 8897bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 8898 struct drm_display_mode *mode,
51fd371b
RC		 8899 struct intel_load_detect_pipe *old,
8900 struct drm_modeset_acquire_ctx *ctx)
79e53945
JB		 8901{
8902 struct intel_crtc *intel_crtc;
d2434ab7
DV		 8903 struct intel_encoder *intel_encoder =
8904 intel_attached_encoder(connector);
79e53945 8905 struct drm_crtc *possible_crtc;
4ef69c7a 8906 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 8907 struct drm_crtc *crtc = NULL;
8908 struct drm_device *dev = encoder->dev;
94352cf9 8909 struct drm_framebuffer *fb;
51fd371b
RC		 8910 struct drm_mode_config *config = &dev->mode_config;
8911 int ret, i = -1;
79e53945 8912
d2dff872 8913 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 8914 connector->base.id, connector->name,
8e329a03 8915 encoder->base.id, encoder->name);
d2dff872 8916
51fd371b
RC		 8917retry:
8918 ret = drm_modeset_lock(&config->connection_mutex, ctx);
8919 if (ret)
8920 goto fail_unlock;
6e9f798d 8921
79e53945
JB		 8922 /*
8923 * Algorithm gets a little messy:
7a5e4805 8924 *
79e53945
JB		 8925 * - if the connector already has an assigned crtc, use it (but make
8926 * sure it's on first)
7a5e4805 8927 *
79e53945
JB		 8928 * - try to find the first unused crtc that can drive this connector,
8929 * and use that if we find one
79e53945
JB		 8930 */
8931
8932 /* See if we already have a CRTC for this connector */
8933 if (encoder->crtc) {
8934 crtc = encoder->crtc;
8261b191 8935
51fd371b 8936 ret = drm_modeset_lock(&crtc->mutex, ctx);
4d02e2de
DV		 8937 if (ret)
8938 goto fail_unlock;
8939 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
51fd371b
RC		 8940 if (ret)
8941 goto fail_unlock;
7b24056b 8942
24218aac 8943 old->dpms_mode = connector->dpms;
8261b191
CW		 8944 old->load_detect_temp = false;
8945
8946 /* Make sure the crtc and connector are running */
24218aac
DV		 8947 if (connector->dpms != DRM_MODE_DPMS_ON)
8948 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 8949
7173188d 8950 return true;
79e53945
JB		 8951 }
8952
8953 /* Find an unused one (if possible) */
70e1e0ec 8954 for_each_crtc(dev, possible_crtc) {
79e53945
JB		 8955 i++;
8956 if (!(encoder->possible_crtcs & (1 << i)))
8957 continue;
83d65738 8958 if (possible_crtc->state->enable)
a459249c
VS		 8959 continue;
8960 /* This can occur when applying the pipe A quirk on resume. */
8961 if (to_intel_crtc(possible_crtc)->new_enabled)
8962 continue;
8963
8964 crtc = possible_crtc;
8965 break;
79e53945
JB		 8966 }
8967
8968 /*
8969 * If we didn't find an unused CRTC, don't use any.
8970 */
8971 if (!crtc) {
7173188d 8972 DRM_DEBUG_KMS("no pipe available for load-detect\n");
51fd371b 8973 goto fail_unlock;
79e53945
JB		 8974 }
8975
51fd371b
RC		 8976 ret = drm_modeset_lock(&crtc->mutex, ctx);
8977 if (ret)
4d02e2de
DV		 8978 goto fail_unlock;
8979 ret = drm_modeset_lock(&crtc->primary->mutex, ctx);
8980 if (ret)
51fd371b 8981 goto fail_unlock;
fc303101
DV		 8982 intel_encoder->new_crtc = to_intel_crtc(crtc);
8983 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 8984
8985 intel_crtc = to_intel_crtc(crtc);
412b61d8 8986 intel_crtc->new_enabled = true;
6e3c9717 8987 intel_crtc->new_config = intel_crtc->config;
24218aac 8988 old->dpms_mode = connector->dpms;
8261b191 8989 old->load_detect_temp = true;
d2dff872 8990 old->release_fb = NULL;
79e53945 8991
6492711d
CW		 8992 if (!mode)
8993 mode = &load_detect_mode;
79e53945 8994
d2dff872
CW		 8995 /* We need a framebuffer large enough to accommodate all accesses
8996 * that the plane may generate whilst we perform load detection.
8997 * We can not rely on the fbcon either being present (we get called
8998 * during its initialisation to detect all boot displays, or it may
8999 * not even exist) or that it is large enough to satisfy the
9000 * requested mode.
9001 */
94352cf9
DV		 9002 fb = mode_fits_in_fbdev(dev, mode);
9003 if (fb == NULL) {
d2dff872 9004 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 9005 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
9006 old->release_fb = fb;
d2dff872
CW		 9007 } else
9008 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 9009 if (IS_ERR(fb)) {
d2dff872 9010 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
412b61d8 9011 goto fail;
79e53945 9012 }
79e53945 9013
c0c36b94 9014 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 9015 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 9016 if (old->release_fb)
9017 old->release_fb->funcs->destroy(old->release_fb);
412b61d8 9018 goto fail;
79e53945 9019 }
9128b040 9020 crtc->primary->crtc = crtc;
7173188d 9021
79e53945 9022 /* let the connector get through one full cycle before testing */
9d0498a2 9023 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 9024 return true;
412b61d8
VS		 9025
9026 fail:
83d65738 9027 intel_crtc->new_enabled = crtc->state->enable;
412b61d8 9028 if (intel_crtc->new_enabled)
6e3c9717 9029 intel_crtc->new_config = intel_crtc->config;
412b61d8
VS		 9030 else
9031 intel_crtc->new_config = NULL;
51fd371b
RC		 9032fail_unlock:
9033 if (ret == -EDEADLK) {
9034 drm_modeset_backoff(ctx);
9035 goto retry;
9036 }
9037
412b61d8 9038 return false;
79e53945
JB		 9039}
9040
d2434ab7 9041void intel_release_load_detect_pipe(struct drm_connector *connector,
208bf9fd 9042 struct intel_load_detect_pipe *old)
79e53945 9043{
d2434ab7
DV		 9044 struct intel_encoder *intel_encoder =
9045 intel_attached_encoder(connector);
4ef69c7a 9046 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 9047 struct drm_crtc *crtc = encoder->crtc;
412b61d8 9048 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 9049
d2dff872 9050 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
c23cc417 9051 connector->base.id, connector->name,
8e329a03 9052 encoder->base.id, encoder->name);
d2dff872 9053
8261b191 9054 if (old->load_detect_temp) {
fc303101
DV		 9055 to_intel_connector(connector)->new_encoder = NULL;
9056 intel_encoder->new_crtc = NULL;
412b61d8
VS		 9057 intel_crtc->new_enabled = false;
9058 intel_crtc->new_config = NULL;
fc303101 9059 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 9060
36206361
DV		 9061 if (old->release_fb) {
9062 drm_framebuffer_unregister_private(old->release_fb);
9063 drm_framebuffer_unreference(old->release_fb);
9064 }
d2dff872 9065
0622a53c 9066 return;
79e53945
JB		 9067 }
9068
c751ce4f 9069 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 9070 if (old->dpms_mode != DRM_MODE_DPMS_ON)
9071 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 9072}
9073
da4a1efa 9074static int i9xx_pll_refclk(struct drm_device *dev,
5cec258b 9075 const struct intel_crtc_state *pipe_config)
da4a1efa
VS		 9076{
9077 struct drm_i915_private *dev_priv = dev->dev_private;
9078 u32 dpll = pipe_config->dpll_hw_state.dpll;
9079
9080 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
e91e941b 9081 return dev_priv->vbt.lvds_ssc_freq;
da4a1efa
VS		 9082 else if (HAS_PCH_SPLIT(dev))
9083 return 120000;
9084 else if (!IS_GEN2(dev))
9085 return 96000;
9086 else
9087 return 48000;
9088}
9089
79e53945 9090/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc 9091static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
5cec258b 9092 struct intel_crtc_state *pipe_config)
79e53945 9093{
f1f644dc 9094 struct drm_device *dev = crtc->base.dev;
79e53945 9095 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 9096 int pipe = pipe_config->cpu_transcoder;
293623f7 9097 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 9098 u32 fp;
9099 intel_clock_t clock;
da4a1efa 9100 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 9101
9102 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 9103 fp = pipe_config->dpll_hw_state.fp0;
79e53945 9104 else
293623f7 9105 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 9106
9107 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 9108 if (IS_PINEVIEW(dev)) {
9109 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
9110 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 9111 } else {
9112 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
9113 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
9114 }
9115
a6c45cf0 9116 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 9117 if (IS_PINEVIEW(dev))
9118 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
9119 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 9120 else
9121 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 9122 DPLL_FPA01_P1_POST_DIV_SHIFT);
9123
9124 switch (dpll & DPLL_MODE_MASK) {
9125 case DPLLB_MODE_DAC_SERIAL:
9126 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
9127 5 : 10;
9128 break;
9129 case DPLLB_MODE_LVDS:
9130 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
9131 7 : 14;
9132 break;
9133 default:
28c97730 9134 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 9135 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 9136 return;
79e53945
JB		 9137 }
9138
ac58c3f0 9139 if (IS_PINEVIEW(dev))
da4a1efa 9140 pineview_clock(refclk, &clock);
ac58c3f0 9141 else
da4a1efa 9142 i9xx_clock(refclk, &clock);
79e53945 9143 } else {
0fb58223 9144 u32 lvds = IS_I830(dev) ? 0 : I915_READ(LVDS);
b1c560d1 9145 bool is_lvds = (pipe == 1) && (lvds & LVDS_PORT_EN);
79e53945
JB		 9146
9147 if (is_lvds) {
9148 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
9149 DPLL_FPA01_P1_POST_DIV_SHIFT);
b1c560d1
VS		 9150
9151 if (lvds & LVDS_CLKB_POWER_UP)
9152 clock.p2 = 7;
9153 else
9154 clock.p2 = 14;
79e53945
JB		 9155 } else {
9156 if (dpll & PLL_P1_DIVIDE_BY_TWO)
9157 clock.p1 = 2;
9158 else {
9159 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
9160 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
9161 }
9162 if (dpll & PLL_P2_DIVIDE_BY_4)
9163 clock.p2 = 4;
9164 else
9165 clock.p2 = 2;
79e53945 9166 }
da4a1efa
VS		 9167
9168 i9xx_clock(refclk, &clock);
79e53945
JB		 9169 }
9170
18442d08
VS		 9171 /*
9172 * This value includes pixel_multiplier. We will use
241bfc38 9173 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 9174 * encoder's get_config() function.
9175 */
9176 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 9177}
9178
6878da05
VS		 9179int intel_dotclock_calculate(int link_freq,
9180 const struct intel_link_m_n *m_n)
f1f644dc 9181{
f1f644dc
JB		 9182 /*
9183 * The calculation for the data clock is:
1041a02f 9184 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 9185 * But we want to avoid losing precison if possible, so:
1041a02f 9186 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 9187 *
9188 * and the link clock is simpler:
1041a02f 9189 * link_clock = (m * link_clock) / n
f1f644dc
JB		 9190 */
9191
6878da05
VS		 9192 if (!m_n->link_n)
9193 return 0;
f1f644dc 9194
6878da05
VS		 9195 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
9196}
f1f644dc 9197
18442d08 9198static void ironlake_pch_clock_get(struct intel_crtc *crtc,
5cec258b 9199 struct intel_crtc_state *pipe_config)
6878da05
VS		 9200{
9201 struct drm_device *dev = crtc->base.dev;
79e53945 9202
18442d08
VS		 9203 /* read out port_clock from the DPLL */
9204 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 9205
f1f644dc 9206 /*
18442d08 9207 * This value does not include pixel_multiplier.
241bfc38 9208 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 9209 * agree once we know their relationship in the encoder's
9210 * get_config() function.
79e53945 9211 */
2d112de7 9212 pipe_config->base.adjusted_mode.crtc_clock =
18442d08
VS		 9213 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
9214 &pipe_config->fdi_m_n);
79e53945
JB		 9215}
9216
9217/** Returns the currently programmed mode of the given pipe. */
9218struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
9219 struct drm_crtc *crtc)
9220{
548f245b 9221 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 9222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 9223 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder;
79e53945 9224 struct drm_display_mode *mode;
5cec258b 9225 struct intel_crtc_state pipe_config;
fe2b8f9d
PZ		 9226 int htot = I915_READ(HTOTAL(cpu_transcoder));
9227 int hsync = I915_READ(HSYNC(cpu_transcoder));
9228 int vtot = I915_READ(VTOTAL(cpu_transcoder));
9229 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 9230 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 9231
9232 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
9233 if (!mode)
9234 return NULL;
9235
f1f644dc
JB		 9236 /*
9237 * Construct a pipe_config sufficient for getting the clock info
9238 * back out of crtc_clock_get.
9239 *
9240 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
9241 * to use a real value here instead.
9242 */
293623f7 9243 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 9244 pipe_config.pixel_multiplier = 1;
293623f7
VS		 9245 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
9246 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
9247 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 9248 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
9249
773ae034 9250 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 9251 mode->hdisplay = (htot & 0xffff) + 1;
9252 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
9253 mode->hsync_start = (hsync & 0xffff) + 1;
9254 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
9255 mode->vdisplay = (vtot & 0xffff) + 1;
9256 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
9257 mode->vsync_start = (vsync & 0xffff) + 1;
9258 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
9259
9260 drm_mode_set_name(mode);
79e53945
JB		 9261
9262 return mode;
9263}
9264
652c393a
JB		 9265static void intel_decrease_pllclock(struct drm_crtc *crtc)
9266{
9267 struct drm_device *dev = crtc->dev;
fbee40df 9268 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 9269 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 9270
baff296c 9271 if (!HAS_GMCH_DISPLAY(dev))
652c393a
JB		 9272 return;
9273
9274 if (!dev_priv->lvds_downclock_avail)
9275 return;
9276
9277 /*
9278 * Since this is called by a timer, we should never get here in
9279 * the manual case.
9280 */
9281 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 9282 int pipe = intel_crtc->pipe;
9283 int dpll_reg = DPLL(pipe);
9284 int dpll;
f6e5b160 9285
44d98a61 9286 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 9287
8ac5a6d5 9288 assert_panel_unlocked(dev_priv, pipe);
652c393a 9289
dc257cf1 9290 dpll = I915_READ(dpll_reg);
652c393a
JB		 9291 dpll |= DISPLAY_RATE_SELECT_FPA1;
9292 I915_WRITE(dpll_reg, dpll);
9d0498a2 9293 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 9294 dpll = I915_READ(dpll_reg);
9295 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 9296 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 9297 }
9298
9299}
9300
f047e395
CW		 9301void intel_mark_busy(struct drm_device *dev)
9302{
c67a470b
PZ		 9303 struct drm_i915_private *dev_priv = dev->dev_private;
9304
f62a0076
CW		 9305 if (dev_priv->mm.busy)
9306 return;
9307
43694d69 9308 intel_runtime_pm_get(dev_priv);
c67a470b 9309 i915_update_gfx_val(dev_priv);
43cf3bf0
CW		 9310 if (INTEL_INFO(dev)->gen >= 6)
9311 gen6_rps_busy(dev_priv);
f62a0076 9312 dev_priv->mm.busy = true;
f047e395
CW		 9313}
9314
9315void intel_mark_idle(struct drm_device *dev)
652c393a 9316{
c67a470b 9317 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 9318 struct drm_crtc *crtc;
652c393a 9319
f62a0076
CW		 9320 if (!dev_priv->mm.busy)
9321 return;
9322
9323 dev_priv->mm.busy = false;
9324
d330a953 9325 if (!i915.powersave)
bb4cdd53 9326 goto out;
652c393a 9327
70e1e0ec 9328 for_each_crtc(dev, crtc) {
f4510a27 9329 if (!crtc->primary->fb)
652c393a
JB		 9330 continue;
9331
725a5b54 9332 intel_decrease_pllclock(crtc);
652c393a 9333 }
b29c19b6 9334
3d13ef2e 9335 if (INTEL_INFO(dev)->gen >= 6)
b29c19b6 9336 gen6_rps_idle(dev->dev_private);
bb4cdd53
PZ		 9337
9338out:
43694d69 9339 intel_runtime_pm_put(dev_priv);
652c393a
JB		 9340}
9341
f5de6e07
ACO		 9342static void intel_crtc_set_state(struct intel_crtc *crtc,
9343 struct intel_crtc_state *crtc_state)
9344{
9345 kfree(crtc->config);
9346 crtc->config = crtc_state;
16f3f658 9347 crtc->base.state = &crtc_state->base;
f5de6e07
ACO		 9348}
9349
79e53945
JB		 9350static void intel_crtc_destroy(struct drm_crtc *crtc)
9351{
9352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 9353 struct drm_device *dev = crtc->dev;
9354 struct intel_unpin_work *work;
67e77c5a 9355
5e2d7afc 9356 spin_lock_irq(&dev->event_lock);
67e77c5a
DV		 9357 work = intel_crtc->unpin_work;
9358 intel_crtc->unpin_work = NULL;
5e2d7afc 9359 spin_unlock_irq(&dev->event_lock);
67e77c5a
DV		 9360
9361 if (work) {
9362 cancel_work_sync(&work->work);
9363 kfree(work);
9364 }
79e53945 9365
f5de6e07 9366 intel_crtc_set_state(intel_crtc, NULL);
79e53945 9367 drm_crtc_cleanup(crtc);
67e77c5a 9368
79e53945
JB		 9369 kfree(intel_crtc);
9370}
9371
6b95a207
KH		 9372static void intel_unpin_work_fn(struct work_struct *__work)
9373{
9374 struct intel_unpin_work *work =
9375 container_of(__work, struct intel_unpin_work, work);
b4a98e57 9376 struct drm_device *dev = work->crtc->dev;
f99d7069 9377 enum pipe pipe = to_intel_crtc(work->crtc)->pipe;
6b95a207 9378
b4a98e57 9379 mutex_lock(&dev->struct_mutex);
82bc3b2d 9380 intel_unpin_fb_obj(work->old_fb, work->crtc->primary->state);
05394f39 9381 drm_gem_object_unreference(&work->pending_flip_obj->base);
d9e86c0e 9382
7ff0ebcc 9383 intel_fbc_update(dev);
f06cc1b9
JH		 9384
9385 if (work->flip_queued_req)
146d84f0 9386 i915_gem_request_assign(&work->flip_queued_req, NULL);
b4a98e57
CW		 9387 mutex_unlock(&dev->struct_mutex);
9388
f99d7069 9389 intel_frontbuffer_flip_complete(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
89ed88ba 9390 drm_framebuffer_unreference(work->old_fb);
f99d7069 9391
b4a98e57
CW		 9392 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
9393 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
9394
6b95a207
KH		 9395 kfree(work);
9396}
9397
1afe3e9d 9398static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 9399 struct drm_crtc *crtc)
6b95a207 9400{
6b95a207
KH		 9401 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9402 struct intel_unpin_work *work;
6b95a207
KH		 9403 unsigned long flags;
9404
9405 /* Ignore early vblank irqs */
9406 if (intel_crtc == NULL)
9407 return;
9408
f326038a
DV		 9409 /*
9410 * This is called both by irq handlers and the reset code (to complete
9411 * lost pageflips) so needs the full irqsave spinlocks.
9412 */
6b95a207
KH		 9413 spin_lock_irqsave(&dev->event_lock, flags);
9414 work = intel_crtc->unpin_work;
e7d841ca
CW		 9415
9416 /* Ensure we don't miss a work->pending update ... */
9417 smp_rmb();
9418
9419 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 9420 spin_unlock_irqrestore(&dev->event_lock, flags);
9421 return;
9422 }
9423
d6bbafa1 9424 page_flip_completed(intel_crtc);
0af7e4df 9425
6b95a207 9426 spin_unlock_irqrestore(&dev->event_lock, flags);
6b95a207
KH		 9427}
9428
1afe3e9d
JB		 9429void intel_finish_page_flip(struct drm_device *dev, int pipe)
9430{
fbee40df 9431 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 9432 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9433
49b14a5c 9434 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 9435}
9436
9437void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
9438{
fbee40df 9439 struct drm_i915_private *dev_priv = dev->dev_private;
1afe3e9d
JB		 9440 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
9441
49b14a5c 9442 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 9443}
9444
75f7f3ec
VS		 9445/* Is 'a' after or equal to 'b'? */
9446static bool g4x_flip_count_after_eq(u32 a, u32 b)
9447{
9448 return !((a - b) & 0x80000000);
9449}
9450
9451static bool page_flip_finished(struct intel_crtc *crtc)
9452{
9453 struct drm_device *dev = crtc->base.dev;
9454 struct drm_i915_private *dev_priv = dev->dev_private;
9455
bdfa7542
VS		 9456 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
9457 crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
9458 return true;
9459
75f7f3ec
VS		 9460 /*
9461 * The relevant registers doen't exist on pre-ctg.
9462 * As the flip done interrupt doesn't trigger for mmio
9463 * flips on gmch platforms, a flip count check isn't
9464 * really needed there. But since ctg has the registers,
9465 * include it in the check anyway.
9466 */
9467 if (INTEL_INFO(dev)->gen < 5 && !IS_G4X(dev))
9468 return true;
9469
9470 /*
9471 * A DSPSURFLIVE check isn't enough in case the mmio and CS flips
9472 * used the same base address. In that case the mmio flip might
9473 * have completed, but the CS hasn't even executed the flip yet.
9474 *
9475 * A flip count check isn't enough as the CS might have updated
9476 * the base address just after start of vblank, but before we
9477 * managed to process the interrupt. This means we'd complete the
9478 * CS flip too soon.
9479 *
9480 * Combining both checks should get us a good enough result. It may
9481 * still happen that the CS flip has been executed, but has not
9482 * yet actually completed. But in case the base address is the same
9483 * anyway, we don't really care.
9484 */
9485 return (I915_READ(DSPSURFLIVE(crtc->plane)) & ~0xfff) ==
9486 crtc->unpin_work->gtt_offset &&
9487 g4x_flip_count_after_eq(I915_READ(PIPE_FLIPCOUNT_GM45(crtc->pipe)),
9488 crtc->unpin_work->flip_count);
9489}
9490
6b95a207
KH		 9491void intel_prepare_page_flip(struct drm_device *dev, int plane)
9492{
fbee40df 9493 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 9494 struct intel_crtc *intel_crtc =
9495 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
9496 unsigned long flags;
9497
f326038a
DV		 9498
9499 /*
9500 * This is called both by irq handlers and the reset code (to complete
9501 * lost pageflips) so needs the full irqsave spinlocks.
9502 *
9503 * NB: An MMIO update of the plane base pointer will also
e7d841ca
CW		 9504 * generate a page-flip completion irq, i.e. every modeset
9505 * is also accompanied by a spurious intel_prepare_page_flip().
9506 */
6b95a207 9507 spin_lock_irqsave(&dev->event_lock, flags);
75f7f3ec 9508 if (intel_crtc->unpin_work && page_flip_finished(intel_crtc))
e7d841ca 9509 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 9510 spin_unlock_irqrestore(&dev->event_lock, flags);
9511}
9512
eba905b2 9513static inline void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
e7d841ca
CW		 9514{
9515 /* Ensure that the work item is consistent when activating it ... */
9516 smp_wmb();
9517 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
9518 /* and that it is marked active as soon as the irq could fire. */
9519 smp_wmb();
9520}
9521
8c9f3aaf
JB		 9522static int intel_gen2_queue_flip(struct drm_device *dev,
9523 struct drm_crtc *crtc,
9524 struct drm_framebuffer *fb,
ed8d1975 9525 struct drm_i915_gem_object *obj,
a4872ba6 9526 struct intel_engine_cs *ring,
ed8d1975 9527 uint32_t flags)
8c9f3aaf 9528{
8c9f3aaf 9529 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 9530 u32 flip_mask;
9531 int ret;
9532
6d90c952 9533 ret = intel_ring_begin(ring, 6);
8c9f3aaf 9534 if (ret)
4fa62c89 9535 return ret;
8c9f3aaf
JB		 9536
9537 /* Can't queue multiple flips, so wait for the previous
9538 * one to finish before executing the next.
9539 */
9540 if (intel_crtc->plane)
9541 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9542 else
9543 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 9544 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9545 intel_ring_emit(ring, MI_NOOP);
9546 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9547 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9548 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 9549 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952 9550 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 9551
9552 intel_mark_page_flip_active(intel_crtc);
09246732 9553 __intel_ring_advance(ring);
83d4092b 9554 return 0;
8c9f3aaf
JB		 9555}
9556
9557static int intel_gen3_queue_flip(struct drm_device *dev,
9558 struct drm_crtc *crtc,
9559 struct drm_framebuffer *fb,
ed8d1975 9560 struct drm_i915_gem_object *obj,
a4872ba6 9561 struct intel_engine_cs *ring,
ed8d1975 9562 uint32_t flags)
8c9f3aaf 9563{
8c9f3aaf 9564 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf
JB		 9565 u32 flip_mask;
9566 int ret;
9567
6d90c952 9568 ret = intel_ring_begin(ring, 6);
8c9f3aaf 9569 if (ret)
4fa62c89 9570 return ret;
8c9f3aaf
JB		 9571
9572 if (intel_crtc->plane)
9573 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
9574 else
9575 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 9576 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
9577 intel_ring_emit(ring, MI_NOOP);
9578 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
9579 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9580 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 9581 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
6d90c952
DV		 9582 intel_ring_emit(ring, MI_NOOP);
9583
e7d841ca 9584 intel_mark_page_flip_active(intel_crtc);
09246732 9585 __intel_ring_advance(ring);
83d4092b 9586 return 0;
8c9f3aaf
JB		 9587}
9588
9589static int intel_gen4_queue_flip(struct drm_device *dev,
9590 struct drm_crtc *crtc,
9591 struct drm_framebuffer *fb,
ed8d1975 9592 struct drm_i915_gem_object *obj,
a4872ba6 9593 struct intel_engine_cs *ring,
ed8d1975 9594 uint32_t flags)
8c9f3aaf
JB		 9595{
9596 struct drm_i915_private *dev_priv = dev->dev_private;
9597 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9598 uint32_t pf, pipesrc;
9599 int ret;
9600
6d90c952 9601 ret = intel_ring_begin(ring, 4);
8c9f3aaf 9602 if (ret)
4fa62c89 9603 return ret;
8c9f3aaf
JB		 9604
9605 /* i965+ uses the linear or tiled offsets from the
9606 * Display Registers (which do not change across a page-flip)
9607 * so we need only reprogram the base address.
9608 */
6d90c952
DV		 9609 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9610 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9611 intel_ring_emit(ring, fb->pitches[0]);
75f7f3ec 9612 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset |
c2c75131 9613 obj->tiling_mode);
8c9f3aaf
JB		 9614
9615 /* XXX Enabling the panel-fitter across page-flip is so far
9616 * untested on non-native modes, so ignore it for now.
9617 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
9618 */
9619 pf = 0;
9620 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 9621 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 9622
9623 intel_mark_page_flip_active(intel_crtc);
09246732 9624 __intel_ring_advance(ring);
83d4092b 9625 return 0;
8c9f3aaf
JB		 9626}
9627
9628static int intel_gen6_queue_flip(struct drm_device *dev,
9629 struct drm_crtc *crtc,
9630 struct drm_framebuffer *fb,
ed8d1975 9631 struct drm_i915_gem_object *obj,
a4872ba6 9632 struct intel_engine_cs *ring,
ed8d1975 9633 uint32_t flags)
8c9f3aaf
JB		 9634{
9635 struct drm_i915_private *dev_priv = dev->dev_private;
9636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9637 uint32_t pf, pipesrc;
9638 int ret;
9639
6d90c952 9640 ret = intel_ring_begin(ring, 4);
8c9f3aaf 9641 if (ret)
4fa62c89 9642 return ret;
8c9f3aaf 9643
6d90c952
DV		 9644 intel_ring_emit(ring, MI_DISPLAY_FLIP |
9645 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
9646 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
75f7f3ec 9647 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
8c9f3aaf 9648
dc257cf1
DV		 9649 /* Contrary to the suggestions in the documentation,
9650 * "Enable Panel Fitter" does not seem to be required when page
9651 * flipping with a non-native mode, and worse causes a normal
9652 * modeset to fail.
9653 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
9654 */
9655 pf = 0;
8c9f3aaf 9656 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 9657 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 9658
9659 intel_mark_page_flip_active(intel_crtc);
09246732 9660 __intel_ring_advance(ring);
83d4092b 9661 return 0;
8c9f3aaf
JB		 9662}
9663
7c9017e5
JB		 9664static int intel_gen7_queue_flip(struct drm_device *dev,
9665 struct drm_crtc *crtc,
9666 struct drm_framebuffer *fb,
ed8d1975 9667 struct drm_i915_gem_object *obj,
a4872ba6 9668 struct intel_engine_cs *ring,
ed8d1975 9669 uint32_t flags)
7c9017e5 9670{
7c9017e5 9671 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cb05d8de 9672 uint32_t plane_bit = 0;
ffe74d75
CW		 9673 int len, ret;
9674
eba905b2 9675 switch (intel_crtc->plane) {
cb05d8de
DV		 9676 case PLANE_A:
9677 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
9678 break;
9679 case PLANE_B:
9680 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
9681 break;
9682 case PLANE_C:
9683 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
9684 break;
9685 default:
9686 WARN_ONCE(1, "unknown plane in flip command\n");
4fa62c89 9687 return -ENODEV;
cb05d8de
DV		 9688 }
9689
ffe74d75 9690 len = 4;
f476828a 9691 if (ring->id == RCS) {
ffe74d75 9692 len += 6;
f476828a
DL		 9693 /*
9694 * On Gen 8, SRM is now taking an extra dword to accommodate
9695 * 48bits addresses, and we need a NOOP for the batch size to
9696 * stay even.
9697 */
9698 if (IS_GEN8(dev))
9699 len += 2;
9700 }
ffe74d75 9701
f66fab8e
VS		 9702 /*
9703 * BSpec MI_DISPLAY_FLIP for IVB:
9704 * "The full packet must be contained within the same cache line."
9705 *
9706 * Currently the LRI+SRM+MI_DISPLAY_FLIP all fit within the same
9707 * cacheline, if we ever start emitting more commands before
9708 * the MI_DISPLAY_FLIP we may need to first emit everything else,
9709 * then do the cacheline alignment, and finally emit the
9710 * MI_DISPLAY_FLIP.
9711 */
9712 ret = intel_ring_cacheline_align(ring);
9713 if (ret)
4fa62c89 9714 return ret;
f66fab8e 9715
ffe74d75 9716 ret = intel_ring_begin(ring, len);
7c9017e5 9717 if (ret)
4fa62c89 9718 return ret;
7c9017e5 9719
ffe74d75
CW		 9720 /* Unmask the flip-done completion message. Note that the bspec says that
9721 * we should do this for both the BCS and RCS, and that we must not unmask
9722 * more than one flip event at any time (or ensure that one flip message
9723 * can be sent by waiting for flip-done prior to queueing new flips).
9724 * Experimentation says that BCS works despite DERRMR masking all
9725 * flip-done completion events and that unmasking all planes at once
9726 * for the RCS also doesn't appear to drop events. Setting the DERRMR
9727 * to zero does lead to lockups within MI_DISPLAY_FLIP.
9728 */
9729 if (ring->id == RCS) {
9730 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
9731 intel_ring_emit(ring, DERRMR);
9732 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
9733 DERRMR_PIPEB_PRI_FLIP_DONE |
9734 DERRMR_PIPEC_PRI_FLIP_DONE));
f476828a
DL		 9735 if (IS_GEN8(dev))
9736 intel_ring_emit(ring, MI_STORE_REGISTER_MEM_GEN8(1) |
9737 MI_SRM_LRM_GLOBAL_GTT);
9738 else
9739 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1) |
9740 MI_SRM_LRM_GLOBAL_GTT);
ffe74d75
CW		 9741 intel_ring_emit(ring, DERRMR);
9742 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
f476828a
DL		 9743 if (IS_GEN8(dev)) {
9744 intel_ring_emit(ring, 0);
9745 intel_ring_emit(ring, MI_NOOP);
9746 }
ffe74d75
CW		 9747 }
9748
cb05d8de 9749 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 9750 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
75f7f3ec 9751 intel_ring_emit(ring, intel_crtc->unpin_work->gtt_offset);
7c9017e5 9752 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 9753
9754 intel_mark_page_flip_active(intel_crtc);
09246732 9755 __intel_ring_advance(ring);
83d4092b 9756 return 0;
7c9017e5
JB		 9757}
9758
84c33a64
SG		 9759static bool use_mmio_flip(struct intel_engine_cs *ring,
9760 struct drm_i915_gem_object *obj)
9761{
9762 /*
9763 * This is not being used for older platforms, because
9764 * non-availability of flip done interrupt forces us to use
9765 * CS flips. Older platforms derive flip done using some clever
9766 * tricks involving the flip_pending status bits and vblank irqs.
9767 * So using MMIO flips there would disrupt this mechanism.
9768 */
9769
8e09bf83
CW		 9770 if (ring == NULL)
9771 return true;
9772
84c33a64
SG		 9773 if (INTEL_INFO(ring->dev)->gen < 5)
9774 return false;
9775
9776 if (i915.use_mmio_flip < 0)
9777 return false;
9778 else if (i915.use_mmio_flip > 0)
9779 return true;
14bf993e
OM		 9780 else if (i915.enable_execlists)
9781 return true;
84c33a64 9782 else
41c52415 9783 return ring != i915_gem_request_get_ring(obj->last_read_req);
84c33a64
SG		 9784}
9785
ff944564
DL		 9786static void skl_do_mmio_flip(struct intel_crtc *intel_crtc)
9787{
9788 struct drm_device *dev = intel_crtc->base.dev;
9789 struct drm_i915_private *dev_priv = dev->dev_private;
9790 struct drm_framebuffer *fb = intel_crtc->base.primary->fb;
9791 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
9792 struct drm_i915_gem_object *obj = intel_fb->obj;
9793 const enum pipe pipe = intel_crtc->pipe;
9794 u32 ctl, stride;
9795
9796 ctl = I915_READ(PLANE_CTL(pipe, 0));
9797 ctl &= ~PLANE_CTL_TILED_MASK;
9798 if (obj->tiling_mode == I915_TILING_X)
9799 ctl |= PLANE_CTL_TILED_X;
9800
9801 /*
9802 * The stride is either expressed as a multiple of 64 bytes chunks for
9803 * linear buffers or in number of tiles for tiled buffers.
9804 */
9805 stride = fb->pitches[0] >> 6;
9806 if (obj->tiling_mode == I915_TILING_X)
9807 stride = fb->pitches[0] >> 9; /* X tiles are 512 bytes wide */
9808
9809 /*
9810 * Both PLANE_CTL and PLANE_STRIDE are not updated on vblank but on
9811 * PLANE_SURF updates, the update is then guaranteed to be atomic.
9812 */
9813 I915_WRITE(PLANE_CTL(pipe, 0), ctl);
9814 I915_WRITE(PLANE_STRIDE(pipe, 0), stride);
9815
9816 I915_WRITE(PLANE_SURF(pipe, 0), intel_crtc->unpin_work->gtt_offset);
9817 POSTING_READ(PLANE_SURF(pipe, 0));
9818}
9819
9820static void ilk_do_mmio_flip(struct intel_crtc *intel_crtc)
84c33a64
SG		 9821{
9822 struct drm_device *dev = intel_crtc->base.dev;
9823 struct drm_i915_private *dev_priv = dev->dev_private;
9824 struct intel_framebuffer *intel_fb =
9825 to_intel_framebuffer(intel_crtc->base.primary->fb);
9826 struct drm_i915_gem_object *obj = intel_fb->obj;
9827 u32 dspcntr;
9828 u32 reg;
9829
84c33a64
SG		 9830 reg = DSPCNTR(intel_crtc->plane);
9831 dspcntr = I915_READ(reg);
9832
c5d97472
DL		 9833 if (obj->tiling_mode != I915_TILING_NONE)
9834 dspcntr |= DISPPLANE_TILED;
9835 else
9836 dspcntr &= ~DISPPLANE_TILED;
9837
84c33a64
SG		 9838 I915_WRITE(reg, dspcntr);
9839
9840 I915_WRITE(DSPSURF(intel_crtc->plane),
9841 intel_crtc->unpin_work->gtt_offset);
9842 POSTING_READ(DSPSURF(intel_crtc->plane));
84c33a64 9843
ff944564
DL		 9844}
9845
9846/*
9847 * XXX: This is the temporary way to update the plane registers until we get
9848 * around to using the usual plane update functions for MMIO flips
9849 */
9850static void intel_do_mmio_flip(struct intel_crtc *intel_crtc)
9851{
9852 struct drm_device *dev = intel_crtc->base.dev;
9853 bool atomic_update;
9854 u32 start_vbl_count;
9855
9856 intel_mark_page_flip_active(intel_crtc);
9857
9858 atomic_update = intel_pipe_update_start(intel_crtc, &start_vbl_count);
9859
9860 if (INTEL_INFO(dev)->gen >= 9)
9861 skl_do_mmio_flip(intel_crtc);
9862 else
9863 /* use_mmio_flip() retricts MMIO flips to ilk+ */
9864 ilk_do_mmio_flip(intel_crtc);
9865
9362c7c5
ACO		 9866 if (atomic_update)
9867 intel_pipe_update_end(intel_crtc, start_vbl_count);
84c33a64
SG		 9868}
9869
9362c7c5 9870static void intel_mmio_flip_work_func(struct work_struct *work)
84c33a64 9871{
cc8c4cc2 9872 struct intel_crtc *crtc =
9362c7c5 9873 container_of(work, struct intel_crtc, mmio_flip.work);
cc8c4cc2 9874 struct intel_mmio_flip *mmio_flip;
84c33a64 9875
cc8c4cc2
JH		 9876 mmio_flip = &crtc->mmio_flip;
9877 if (mmio_flip->req)
9c654818
JH		 9878 WARN_ON(__i915_wait_request(mmio_flip->req,
9879 crtc->reset_counter,
9880 false, NULL, NULL) != 0);
84c33a64 9881
cc8c4cc2
JH		 9882 intel_do_mmio_flip(crtc);
9883 if (mmio_flip->req) {
9884 mutex_lock(&crtc->base.dev->struct_mutex);
146d84f0 9885 i915_gem_request_assign(&mmio_flip->req, NULL);
cc8c4cc2
JH		 9886 mutex_unlock(&crtc->base.dev->struct_mutex);
9887 }
84c33a64
SG		 9888}
9889
9890static int intel_queue_mmio_flip(struct drm_device *dev,
9891 struct drm_crtc *crtc,
9892 struct drm_framebuffer *fb,
9893 struct drm_i915_gem_object *obj,
9894 struct intel_engine_cs *ring,
9895 uint32_t flags)
9896{
84c33a64 9897 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
84c33a64 9898
cc8c4cc2
JH		 9899 i915_gem_request_assign(&intel_crtc->mmio_flip.req,
9900 obj->last_write_req);
536f5b5e
ACO		 9901
9902 schedule_work(&intel_crtc->mmio_flip.work);
84c33a64 9903
84c33a64
SG		 9904 return 0;
9905}
9906
8c9f3aaf
JB		 9907static int intel_default_queue_flip(struct drm_device *dev,
9908 struct drm_crtc *crtc,
9909 struct drm_framebuffer *fb,
ed8d1975 9910 struct drm_i915_gem_object *obj,
a4872ba6 9911 struct intel_engine_cs *ring,
ed8d1975 9912 uint32_t flags)
8c9f3aaf
JB		 9913{
9914 return -ENODEV;
9915}
9916
d6bbafa1
CW		 9917static bool __intel_pageflip_stall_check(struct drm_device *dev,
9918 struct drm_crtc *crtc)
9919{
9920 struct drm_i915_private *dev_priv = dev->dev_private;
9921 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9922 struct intel_unpin_work *work = intel_crtc->unpin_work;
9923 u32 addr;
9924
9925 if (atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE)
9926 return true;
9927
9928 if (!work->enable_stall_check)
9929 return false;
9930
9931 if (work->flip_ready_vblank == 0) {
3a8a946e
DV		 9932 if (work->flip_queued_req &&
9933 !i915_gem_request_completed(work->flip_queued_req, true))
d6bbafa1
CW		 9934 return false;
9935
1e3feefd 9936 work->flip_ready_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1
CW		 9937 }
9938
1e3feefd 9939 if (drm_crtc_vblank_count(crtc) - work->flip_ready_vblank < 3)
d6bbafa1
CW		 9940 return false;
9941
9942 /* Potential stall - if we see that the flip has happened,
9943 * assume a missed interrupt. */
9944 if (INTEL_INFO(dev)->gen >= 4)
9945 addr = I915_HI_DISPBASE(I915_READ(DSPSURF(intel_crtc->plane)));
9946 else
9947 addr = I915_READ(DSPADDR(intel_crtc->plane));
9948
9949 /* There is a potential issue here with a false positive after a flip
9950 * to the same address. We could address this by checking for a
9951 * non-incrementing frame counter.
9952 */
9953 return addr == work->gtt_offset;
9954}
9955
9956void intel_check_page_flip(struct drm_device *dev, int pipe)
9957{
9958 struct drm_i915_private *dev_priv = dev->dev_private;
9959 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
9960 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
f326038a 9961
6c51d46f 9962 WARN_ON(!in_interrupt());
d6bbafa1
CW		 9963
9964 if (crtc == NULL)
9965 return;
9966
f326038a 9967 spin_lock(&dev->event_lock);
d6bbafa1
CW		 9968 if (intel_crtc->unpin_work && __intel_pageflip_stall_check(dev, crtc)) {
9969 WARN_ONCE(1, "Kicking stuck page flip: queued at %d, now %d\n",
1e3feefd
DV		 9970 intel_crtc->unpin_work->flip_queued_vblank,
9971 drm_vblank_count(dev, pipe));
d6bbafa1
CW		 9972 page_flip_completed(intel_crtc);
9973 }
f326038a 9974 spin_unlock(&dev->event_lock);
d6bbafa1
CW		 9975}
9976
6b95a207
KH		 9977static int intel_crtc_page_flip(struct drm_crtc *crtc,
9978 struct drm_framebuffer *fb,
ed8d1975
KP		 9979 struct drm_pending_vblank_event *event,
9980 uint32_t page_flip_flags)
6b95a207
KH		 9981{
9982 struct drm_device *dev = crtc->dev;
9983 struct drm_i915_private *dev_priv = dev->dev_private;
f4510a27 9984 struct drm_framebuffer *old_fb = crtc->primary->fb;
2ff8fde1 9985 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
6b95a207 9986 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
455a6808 9987 struct drm_plane *primary = crtc->primary;
a071fa00 9988 enum pipe pipe = intel_crtc->pipe;
6b95a207 9989 struct intel_unpin_work *work;
a4872ba6 9990 struct intel_engine_cs *ring;
52e68630 9991 int ret;
6b95a207 9992
2ff8fde1
MR		 9993 /*
9994 * drm_mode_page_flip_ioctl() should already catch this, but double
9995 * check to be safe. In the future we may enable pageflipping from
9996 * a disabled primary plane.
9997 */
9998 if (WARN_ON(intel_fb_obj(old_fb) == NULL))
9999 return -EBUSY;
10000
e6a595d2 10001 /* Can't change pixel format via MI display flips. */
f4510a27 10002 if (fb->pixel_format != crtc->primary->fb->pixel_format)
e6a595d2
VS		 10003 return -EINVAL;
10004
10005 /*
10006 * TILEOFF/LINOFF registers can't be changed via MI display flips.
10007 * Note that pitch changes could also affect these register.
10008 */
10009 if (INTEL_INFO(dev)->gen > 3 &&
f4510a27
MR		 10010 (fb->offsets[0] != crtc->primary->fb->offsets[0] ||
10011 fb->pitches[0] != crtc->primary->fb->pitches[0]))
e6a595d2
VS		 10012 return -EINVAL;
10013
f900db47
CW		 10014 if (i915_terminally_wedged(&dev_priv->gpu_error))
10015 goto out_hang;
10016
b14c5679 10017 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 10018 if (work == NULL)
10019 return -ENOMEM;
10020
6b95a207 10021 work->event = event;
b4a98e57 10022 work->crtc = crtc;
ab8d6675 10023 work->old_fb = old_fb;
6b95a207
KH		 10024 INIT_WORK(&work->work, intel_unpin_work_fn);
10025
87b6b101 10026 ret = drm_crtc_vblank_get(crtc);
7317c75e
JB		 10027 if (ret)
10028 goto free_work;
10029
6b95a207 10030 /* We borrow the event spin lock for protecting unpin_work */
5e2d7afc 10031 spin_lock_irq(&dev->event_lock);
6b95a207 10032 if (intel_crtc->unpin_work) {
d6bbafa1
CW		 10033 /* Before declaring the flip queue wedged, check if
10034 * the hardware completed the operation behind our backs.
10035 */
10036 if (__intel_pageflip_stall_check(dev, crtc)) {
10037 DRM_DEBUG_DRIVER("flip queue: previous flip completed, continuing\n");
10038 page_flip_completed(intel_crtc);
10039 } else {
10040 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5e2d7afc 10041 spin_unlock_irq(&dev->event_lock);
468f0b44 10042
d6bbafa1
CW		 10043 drm_crtc_vblank_put(crtc);
10044 kfree(work);
10045 return -EBUSY;
10046 }
6b95a207
KH		 10047 }
10048 intel_crtc->unpin_work = work;
5e2d7afc 10049 spin_unlock_irq(&dev->event_lock);
6b95a207 10050
b4a98e57
CW		 10051 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
10052 flush_workqueue(dev_priv->wq);
10053
75dfca80 10054 /* Reference the objects for the scheduled work. */
ab8d6675 10055 drm_framebuffer_reference(work->old_fb);
05394f39 10056 drm_gem_object_reference(&obj->base);
6b95a207 10057
f4510a27 10058 crtc->primary->fb = fb;
afd65eb4 10059 update_state_fb(crtc->primary);
1ed1f968 10060
e1f99ce6 10061 work->pending_flip_obj = obj;
e1f99ce6 10062
89ed88ba
CW		 10063 ret = i915_mutex_lock_interruptible(dev);
10064 if (ret)
10065 goto cleanup;
10066
b4a98e57 10067 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 10068 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 10069
75f7f3ec 10070 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
a071fa00 10071 work->flip_count = I915_READ(PIPE_FLIPCOUNT_GM45(pipe)) + 1;
75f7f3ec 10072
4fa62c89
VS		 10073 if (IS_VALLEYVIEW(dev)) {
10074 ring = &dev_priv->ring[BCS];
ab8d6675 10075 if (obj->tiling_mode != intel_fb_obj(work->old_fb)->tiling_mode)
8e09bf83
CW		 10076 /* vlv: DISPLAY_FLIP fails to change tiling */
10077 ring = NULL;
48bf5b2d 10078 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
2a92d5bc 10079 ring = &dev_priv->ring[BCS];
4fa62c89 10080 } else if (INTEL_INFO(dev)->gen >= 7) {
41c52415 10081 ring = i915_gem_request_get_ring(obj->last_read_req);
4fa62c89
VS		 10082 if (ring == NULL || ring->id != RCS)
10083 ring = &dev_priv->ring[BCS];
10084 } else {
10085 ring = &dev_priv->ring[RCS];
10086 }
10087
82bc3b2d
TU		 10088 ret = intel_pin_and_fence_fb_obj(crtc->primary, fb,
10089 crtc->primary->state, ring);
8c9f3aaf
JB		 10090 if (ret)
10091 goto cleanup_pending;
6b95a207 10092
121920fa
TU		 10093 work->gtt_offset = intel_plane_obj_offset(to_intel_plane(primary), obj)
10094 + intel_crtc->dspaddr_offset;
4fa62c89 10095
d6bbafa1 10096 if (use_mmio_flip(ring, obj)) {
84c33a64
SG		 10097 ret = intel_queue_mmio_flip(dev, crtc, fb, obj, ring,
10098 page_flip_flags);
d6bbafa1
CW		 10099 if (ret)
10100 goto cleanup_unpin;
10101
f06cc1b9
JH		 10102 i915_gem_request_assign(&work->flip_queued_req,
10103 obj->last_write_req);
d6bbafa1 10104 } else {
84c33a64 10105 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, ring,
d6bbafa1
CW		 10106 page_flip_flags);
10107 if (ret)
10108 goto cleanup_unpin;
10109
f06cc1b9
JH		 10110 i915_gem_request_assign(&work->flip_queued_req,
10111 intel_ring_get_request(ring));
d6bbafa1
CW		 10112 }
10113
1e3feefd 10114 work->flip_queued_vblank = drm_crtc_vblank_count(crtc);
d6bbafa1 10115 work->enable_stall_check = true;
4fa62c89 10116
ab8d6675 10117 i915_gem_track_fb(intel_fb_obj(work->old_fb), obj,
a071fa00
DV		 10118 INTEL_FRONTBUFFER_PRIMARY(pipe));
10119
7ff0ebcc 10120 intel_fbc_disable(dev);
f99d7069 10121 intel_frontbuffer_flip_prepare(dev, INTEL_FRONTBUFFER_PRIMARY(pipe));
6b95a207
KH		 10122 mutex_unlock(&dev->struct_mutex);
10123
e5510fac
JB		 10124 trace_i915_flip_request(intel_crtc->plane, obj);
10125
6b95a207 10126 return 0;
96b099fd 10127
4fa62c89 10128cleanup_unpin:
82bc3b2d 10129 intel_unpin_fb_obj(fb, crtc->primary->state);
8c9f3aaf 10130cleanup_pending:
b4a98e57 10131 atomic_dec(&intel_crtc->unpin_work_count);
89ed88ba
CW		 10132 mutex_unlock(&dev->struct_mutex);
10133cleanup:
f4510a27 10134 crtc->primary->fb = old_fb;
afd65eb4 10135 update_state_fb(crtc->primary);
89ed88ba
CW		 10136
10137 drm_gem_object_unreference_unlocked(&obj->base);
ab8d6675 10138 drm_framebuffer_unreference(work->old_fb);
96b099fd 10139
5e2d7afc 10140 spin_lock_irq(&dev->event_lock);
96b099fd 10141 intel_crtc->unpin_work = NULL;
5e2d7afc 10142 spin_unlock_irq(&dev->event_lock);
96b099fd 10143
87b6b101 10144 drm_crtc_vblank_put(crtc);
7317c75e 10145free_work:
96b099fd
CW		 10146 kfree(work);
10147
f900db47
CW		 10148 if (ret == -EIO) {
10149out_hang:
53a366b9 10150 ret = intel_plane_restore(primary);
f0d3dad3 10151 if (ret == 0 && event) {
5e2d7afc 10152 spin_lock_irq(&dev->event_lock);
a071fa00 10153 drm_send_vblank_event(dev, pipe, event);
5e2d7afc 10154 spin_unlock_irq(&dev->event_lock);
f0d3dad3 10155 }
f900db47 10156 }
96b099fd 10157 return ret;
6b95a207
KH		 10158}
10159
f6e5b160 10160static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 10161 .mode_set_base_atomic = intel_pipe_set_base_atomic,
10162 .load_lut = intel_crtc_load_lut,
ea2c67bb
MR		 10163 .atomic_begin = intel_begin_crtc_commit,
10164 .atomic_flush = intel_finish_crtc_commit,
f6e5b160
CW		 10165};
10166
9a935856
DV		 10167/**
10168 * intel_modeset_update_staged_output_state
10169 *
10170 * Updates the staged output configuration state, e.g. after we've read out the
10171 * current hw state.
10172 */
10173static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 10174{
7668851f 10175 struct intel_crtc *crtc;
9a935856
DV		 10176 struct intel_encoder *encoder;
10177 struct intel_connector *connector;
f6e5b160 10178
3a3371ff 10179 for_each_intel_connector(dev, connector) {
9a935856
DV		 10180 connector->new_encoder =
10181 to_intel_encoder(connector->base.encoder);
10182 }
f6e5b160 10183
b2784e15 10184 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 10185 encoder->new_crtc =
10186 to_intel_crtc(encoder->base.crtc);
10187 }
7668851f 10188
d3fcc808 10189 for_each_intel_crtc(dev, crtc) {
83d65738 10190 crtc->new_enabled = crtc->base.state->enable;
7bd0a8e7
VS		 10191
10192 if (crtc->new_enabled)
6e3c9717 10193 crtc->new_config = crtc->config;
7bd0a8e7
VS		 10194 else
10195 crtc->new_config = NULL;
7668851f 10196 }
f6e5b160
CW		 10197}
10198
9a935856
DV		 10199/**
10200 * intel_modeset_commit_output_state
10201 *
10202 * This function copies the stage display pipe configuration to the real one.
10203 */
10204static void intel_modeset_commit_output_state(struct drm_device *dev)
10205{
7668851f 10206 struct intel_crtc *crtc;
9a935856
DV		 10207 struct intel_encoder *encoder;
10208 struct intel_connector *connector;
f6e5b160 10209
3a3371ff 10210 for_each_intel_connector(dev, connector) {
9a935856
DV		 10211 connector->base.encoder = &connector->new_encoder->base;
10212 }
f6e5b160 10213
b2784e15 10214 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 10215 encoder->base.crtc = &encoder->new_crtc->base;
10216 }
7668851f 10217
d3fcc808 10218 for_each_intel_crtc(dev, crtc) {
83d65738 10219 crtc->base.state->enable = crtc->new_enabled;
7668851f
VS		 10220 crtc->base.enabled = crtc->new_enabled;
10221 }
9a935856
DV		 10222}
10223
050f7aeb 10224static void
eba905b2 10225connected_sink_compute_bpp(struct intel_connector *connector,
5cec258b 10226 struct intel_crtc_state *pipe_config)
050f7aeb
DV		 10227{
10228 int bpp = pipe_config->pipe_bpp;
10229
10230 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
10231 connector->base.base.id,
c23cc417 10232 connector->base.name);
050f7aeb
DV		 10233
10234 /* Don't use an invalid EDID bpc value */
10235 if (connector->base.display_info.bpc &&
10236 connector->base.display_info.bpc * 3 < bpp) {
10237 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
10238 bpp, connector->base.display_info.bpc*3);
10239 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
10240 }
10241
10242 /* Clamp bpp to 8 on screens without EDID 1.4 */
10243 if (connector->base.display_info.bpc == 0 && bpp > 24) {
10244 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
10245 bpp);
10246 pipe_config->pipe_bpp = 24;
10247 }
10248}
10249
4e53c2e0 10250static int
050f7aeb
DV		 10251compute_baseline_pipe_bpp(struct intel_crtc *crtc,
10252 struct drm_framebuffer *fb,
5cec258b 10253 struct intel_crtc_state *pipe_config)
4e53c2e0 10254{
050f7aeb
DV		 10255 struct drm_device *dev = crtc->base.dev;
10256 struct intel_connector *connector;
4e53c2e0
DV		 10257 int bpp;
10258
d42264b1
DV		 10259 switch (fb->pixel_format) {
10260 case DRM_FORMAT_C8:
4e53c2e0
DV		 10261 bpp = 8*3; /* since we go through a colormap */
10262 break;
d42264b1
DV		 10263 case DRM_FORMAT_XRGB1555:
10264 case DRM_FORMAT_ARGB1555:
10265 /* checked in intel_framebuffer_init already */
10266 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
10267 return -EINVAL;
10268 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 10269 bpp = 6*3; /* min is 18bpp */
10270 break;
d42264b1
DV		 10271 case DRM_FORMAT_XBGR8888:
10272 case DRM_FORMAT_ABGR8888:
10273 /* checked in intel_framebuffer_init already */
10274 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
10275 return -EINVAL;
10276 case DRM_FORMAT_XRGB8888:
10277 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 10278 bpp = 8*3;
10279 break;
d42264b1
DV		 10280 case DRM_FORMAT_XRGB2101010:
10281 case DRM_FORMAT_ARGB2101010:
10282 case DRM_FORMAT_XBGR2101010:
10283 case DRM_FORMAT_ABGR2101010:
10284 /* checked in intel_framebuffer_init already */
10285 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 10286 return -EINVAL;
4e53c2e0
DV		 10287 bpp = 10*3;
10288 break;
baba133a 10289 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 10290 default:
10291 DRM_DEBUG_KMS("unsupported depth\n");
10292 return -EINVAL;
10293 }
10294
4e53c2e0
DV		 10295 pipe_config->pipe_bpp = bpp;
10296
10297 /* Clamp display bpp to EDID value */
3a3371ff 10298 for_each_intel_connector(dev, connector) {
1b829e05
DV		 10299 if (!connector->new_encoder ||
10300 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 10301 continue;
10302
050f7aeb 10303 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 10304 }
10305
10306 return bpp;
10307}
10308
644db711
DV		 10309static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
10310{
10311 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
10312 "type: 0x%x flags: 0x%x\n",
1342830c 10313 mode->crtc_clock,
644db711
DV		 10314 mode->crtc_hdisplay, mode->crtc_hsync_start,
10315 mode->crtc_hsync_end, mode->crtc_htotal,
10316 mode->crtc_vdisplay, mode->crtc_vsync_start,
10317 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
10318}
10319
c0b03411 10320static void intel_dump_pipe_config(struct intel_crtc *crtc,
5cec258b 10321 struct intel_crtc_state *pipe_config,
c0b03411
DV		 10322 const char *context)
10323{
10324 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
10325 context, pipe_name(crtc->pipe));
10326
10327 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
10328 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
10329 pipe_config->pipe_bpp, pipe_config->dither);
10330 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10331 pipe_config->has_pch_encoder,
10332 pipe_config->fdi_lanes,
10333 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
10334 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
10335 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 10336 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
10337 pipe_config->has_dp_encoder,
10338 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
10339 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
10340 pipe_config->dp_m_n.tu);
b95af8be
VK		 10341
10342 DRM_DEBUG_KMS("dp: %i, gmch_m2: %u, gmch_n2: %u, link_m2: %u, link_n2: %u, tu2: %u\n",
10343 pipe_config->has_dp_encoder,
10344 pipe_config->dp_m2_n2.gmch_m,
10345 pipe_config->dp_m2_n2.gmch_n,
10346 pipe_config->dp_m2_n2.link_m,
10347 pipe_config->dp_m2_n2.link_n,
10348 pipe_config->dp_m2_n2.tu);
10349
55072d19
DV		 10350 DRM_DEBUG_KMS("audio: %i, infoframes: %i\n",
10351 pipe_config->has_audio,
10352 pipe_config->has_infoframe);
10353
c0b03411 10354 DRM_DEBUG_KMS("requested mode:\n");
2d112de7 10355 drm_mode_debug_printmodeline(&pipe_config->base.mode);
c0b03411 10356 DRM_DEBUG_KMS("adjusted mode:\n");
2d112de7
ACO		 10357 drm_mode_debug_printmodeline(&pipe_config->base.adjusted_mode);
10358 intel_dump_crtc_timings(&pipe_config->base.adjusted_mode);
d71b8d4a 10359 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 10360 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
10361 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 10362 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
10363 pipe_config->gmch_pfit.control,
10364 pipe_config->gmch_pfit.pgm_ratios,
10365 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 10366 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 10367 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 10368 pipe_config->pch_pfit.size,
10369 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 10370 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 10371 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
c0b03411
DV		 10372}
10373
bc079e8b
VS		 10374static bool encoders_cloneable(const struct intel_encoder *a,
10375 const struct intel_encoder *b)
accfc0c5 10376{
bc079e8b
VS		 10377 /* masks could be asymmetric, so check both ways */
10378 return a == b || (a->cloneable & (1 << b->type) &&
10379 b->cloneable & (1 << a->type));
10380}
10381
10382static bool check_single_encoder_cloning(struct intel_crtc *crtc,
10383 struct intel_encoder *encoder)
10384{
10385 struct drm_device *dev = crtc->base.dev;
10386 struct intel_encoder *source_encoder;
10387
b2784e15 10388 for_each_intel_encoder(dev, source_encoder) {
bc079e8b
VS		 10389 if (source_encoder->new_crtc != crtc)
10390 continue;
10391
10392 if (!encoders_cloneable(encoder, source_encoder))
10393 return false;
10394 }
10395
10396 return true;
10397}
10398
10399static bool check_encoder_cloning(struct intel_crtc *crtc)
10400{
10401 struct drm_device *dev = crtc->base.dev;
accfc0c5
DV		 10402 struct intel_encoder *encoder;
10403
b2784e15 10404 for_each_intel_encoder(dev, encoder) {
bc079e8b 10405 if (encoder->new_crtc != crtc)
accfc0c5
DV		 10406 continue;
10407
bc079e8b
VS		 10408 if (!check_single_encoder_cloning(crtc, encoder))
10409 return false;
accfc0c5
DV		 10410 }
10411
bc079e8b 10412 return true;
accfc0c5
DV		 10413}
10414
00f0b378
VS		 10415static bool check_digital_port_conflicts(struct drm_device *dev)
10416{
10417 struct intel_connector *connector;
10418 unsigned int used_ports = 0;
10419
10420 /*
10421 * Walk the connector list instead of the encoder
10422 * list to detect the problem on ddi platforms
10423 * where there's just one encoder per digital port.
10424 */
3a3371ff 10425 for_each_intel_connector(dev, connector) {
00f0b378
VS		 10426 struct intel_encoder *encoder = connector->new_encoder;
10427
10428 if (!encoder)
10429 continue;
10430
10431 WARN_ON(!encoder->new_crtc);
10432
10433 switch (encoder->type) {
10434 unsigned int port_mask;
10435 case INTEL_OUTPUT_UNKNOWN:
10436 if (WARN_ON(!HAS_DDI(dev)))
10437 break;
10438 case INTEL_OUTPUT_DISPLAYPORT:
10439 case INTEL_OUTPUT_HDMI:
10440 case INTEL_OUTPUT_EDP:
10441 port_mask = 1 << enc_to_dig_port(&encoder->base)->port;
10442
10443 /* the same port mustn't appear more than once */
10444 if (used_ports & port_mask)
10445 return false;
10446
10447 used_ports |= port_mask;
10448 default:
10449 break;
10450 }
10451 }
10452
10453 return true;
10454}
10455
5cec258b 10456static struct intel_crtc_state *
b8cecdf5 10457intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 10458 struct drm_framebuffer *fb,
b8cecdf5 10459 struct drm_display_mode *mode)
ee7b9f93 10460{
7758a113 10461 struct drm_device *dev = crtc->dev;
7758a113 10462 struct intel_encoder *encoder;
5cec258b 10463 struct intel_crtc_state *pipe_config;
e29c22c0
DV		 10464 int plane_bpp, ret = -EINVAL;
10465 bool retry = true;
ee7b9f93 10466
bc079e8b 10467 if (!check_encoder_cloning(to_intel_crtc(crtc))) {
accfc0c5
DV		 10468 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
10469 return ERR_PTR(-EINVAL);
10470 }
10471
00f0b378
VS		 10472 if (!check_digital_port_conflicts(dev)) {
10473 DRM_DEBUG_KMS("rejecting conflicting digital port configuration\n");
10474 return ERR_PTR(-EINVAL);
10475 }
10476
b8cecdf5
DV		 10477 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
10478 if (!pipe_config)
7758a113
DV		 10479 return ERR_PTR(-ENOMEM);
10480
07878248 10481 pipe_config->base.crtc = crtc;
2d112de7
ACO		 10482 drm_mode_copy(&pipe_config->base.adjusted_mode, mode);
10483 drm_mode_copy(&pipe_config->base.mode, mode);
37327abd 10484
e143a21c
DV		 10485 pipe_config->cpu_transcoder =
10486 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 10487 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 10488
2960bc9c
ID		 10489 /*
10490 * Sanitize sync polarity flags based on requested ones. If neither
10491 * positive or negative polarity is requested, treat this as meaning
10492 * negative polarity.
10493 */
2d112de7 10494 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 10495 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
2d112de7 10496 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
2960bc9c 10497
2d112de7 10498 if (!(pipe_config->base.adjusted_mode.flags &
2960bc9c 10499 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
2d112de7 10500 pipe_config->base.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
2960bc9c 10501
050f7aeb
DV		 10502 /* Compute a starting value for pipe_config->pipe_bpp taking the source
10503 * plane pixel format and any sink constraints into account. Returns the
10504 * source plane bpp so that dithering can be selected on mismatches
10505 * after encoders and crtc also have had their say. */
10506 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
10507 fb, pipe_config);
4e53c2e0
DV		 10508 if (plane_bpp < 0)
10509 goto fail;
10510
e41a56be
VS		 10511 /*
10512 * Determine the real pipe dimensions. Note that stereo modes can
10513 * increase the actual pipe size due to the frame doubling and
10514 * insertion of additional space for blanks between the frame. This
10515 * is stored in the crtc timings. We use the requested mode to do this
10516 * computation to clearly distinguish it from the adjusted mode, which
10517 * can be changed by the connectors in the below retry loop.
10518 */
2d112de7 10519 drm_crtc_get_hv_timing(&pipe_config->base.mode,
ecb7e16b
GP		 10520 &pipe_config->pipe_src_w,
10521 &pipe_config->pipe_src_h);
e41a56be 10522
e29c22c0 10523encoder_retry:
ef1b460d 10524 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 10525 pipe_config->port_clock = 0;
ef1b460d 10526 pipe_config->pixel_multiplier = 1;
ff9a6750 10527
135c81b8 10528 /* Fill in default crtc timings, allow encoders to overwrite them. */
2d112de7
ACO		 10529 drm_mode_set_crtcinfo(&pipe_config->base.adjusted_mode,
10530 CRTC_STEREO_DOUBLE);
135c81b8 10531
7758a113
DV		 10532 /* Pass our mode to the connectors and the CRTC to give them a chance to
10533 * adjust it according to limitations or connector properties, and also
10534 * a chance to reject the mode entirely.
47f1c6c9 10535 */
b2784e15 10536 for_each_intel_encoder(dev, encoder) {
47f1c6c9 10537
7758a113
DV		 10538 if (&encoder->new_crtc->base != crtc)
10539 continue;
7ae89233 10540
efea6e8e
DV		 10541 if (!(encoder->compute_config(encoder, pipe_config))) {
10542 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 10543 goto fail;
10544 }
ee7b9f93 10545 }
47f1c6c9 10546
ff9a6750
DV		 10547 /* Set default port clock if not overwritten by the encoder. Needs to be
10548 * done afterwards in case the encoder adjusts the mode. */
10549 if (!pipe_config->port_clock)
2d112de7 10550 pipe_config->port_clock = pipe_config->base.adjusted_mode.crtc_clock
241bfc38 10551 * pipe_config->pixel_multiplier;
ff9a6750 10552
a43f6e0f 10553 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 10554 if (ret < 0) {
7758a113
DV		 10555 DRM_DEBUG_KMS("CRTC fixup failed\n");
10556 goto fail;
ee7b9f93 10557 }
e29c22c0
DV		 10558
10559 if (ret == RETRY) {
10560 if (WARN(!retry, "loop in pipe configuration computation\n")) {
10561 ret = -EINVAL;
10562 goto fail;
10563 }
10564
10565 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
10566 retry = false;
10567 goto encoder_retry;
10568 }
10569
4e53c2e0
DV		 10570 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
10571 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
10572 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
10573
b8cecdf5 10574 return pipe_config;
7758a113 10575fail:
b8cecdf5 10576 kfree(pipe_config);
e29c22c0 10577 return ERR_PTR(ret);
ee7b9f93 10578}
47f1c6c9 10579
e2e1ed41
DV		 10580/* Computes which crtcs are affected and sets the relevant bits in the mask. For
10581 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
10582static void
10583intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
10584 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 10585{
10586 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 10587 struct drm_device *dev = crtc->dev;
10588 struct intel_encoder *encoder;
10589 struct intel_connector *connector;
10590 struct drm_crtc *tmp_crtc;
79e53945 10591
e2e1ed41 10592 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 10593
e2e1ed41
DV		 10594 /* Check which crtcs have changed outputs connected to them, these need
10595 * to be part of the prepare_pipes mask. We don't (yet) support global
10596 * modeset across multiple crtcs, so modeset_pipes will only have one
10597 * bit set at most. */
3a3371ff 10598 for_each_intel_connector(dev, connector) {
e2e1ed41
DV		 10599 if (connector->base.encoder == &connector->new_encoder->base)
10600 continue;
79e53945 10601
e2e1ed41
DV		 10602 if (connector->base.encoder) {
10603 tmp_crtc = connector->base.encoder->crtc;
10604
10605 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10606 }
10607
10608 if (connector->new_encoder)
10609 *prepare_pipes |=
10610 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 10611 }
10612
b2784e15 10613 for_each_intel_encoder(dev, encoder) {
e2e1ed41
DV		 10614 if (encoder->base.crtc == &encoder->new_crtc->base)
10615 continue;
10616
10617 if (encoder->base.crtc) {
10618 tmp_crtc = encoder->base.crtc;
10619
10620 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
10621 }
10622
10623 if (encoder->new_crtc)
10624 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 10625 }
10626
7668851f 10627 /* Check for pipes that will be enabled/disabled ... */
d3fcc808 10628 for_each_intel_crtc(dev, intel_crtc) {
83d65738 10629 if (intel_crtc->base.state->enable == intel_crtc->new_enabled)
e2e1ed41 10630 continue;
7e7d76c3 10631
7668851f 10632 if (!intel_crtc->new_enabled)
e2e1ed41 10633 *disable_pipes |= 1 << intel_crtc->pipe;
7668851f
VS		 10634 else
10635 *prepare_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 10636 }
10637
e2e1ed41
DV		 10638
10639 /* set_mode is also used to update properties on life display pipes. */
10640 intel_crtc = to_intel_crtc(crtc);
7668851f 10641 if (intel_crtc->new_enabled)
e2e1ed41
DV		 10642 *prepare_pipes |= 1 << intel_crtc->pipe;
10643
b6c5164d
DV		 10644 /*
10645 * For simplicity do a full modeset on any pipe where the output routing
10646 * changed. We could be more clever, but that would require us to be
10647 * more careful with calling the relevant encoder->mode_set functions.
10648 */
e2e1ed41
DV		 10649 if (*prepare_pipes)
10650 *modeset_pipes = *prepare_pipes;
10651
10652 /* ... and mask these out. */
10653 *modeset_pipes &= ~(*disable_pipes);
10654 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 10655
10656 /*
10657 * HACK: We don't (yet) fully support global modesets. intel_set_config
10658 * obies this rule, but the modeset restore mode of
10659 * intel_modeset_setup_hw_state does not.
10660 */
10661 *modeset_pipes &= 1 << intel_crtc->pipe;
10662 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 10663
10664 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
10665 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 10666}
79e53945 10667
ea9d758d 10668static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 10669{
ea9d758d 10670 struct drm_encoder *encoder;
f6e5b160 10671 struct drm_device *dev = crtc->dev;
f6e5b160 10672
ea9d758d
DV		 10673 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
10674 if (encoder->crtc == crtc)
10675 return true;
10676
10677 return false;
10678}
10679
10680static void
10681intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
10682{
ba41c0de 10683 struct drm_i915_private *dev_priv = dev->dev_private;
ea9d758d
DV		 10684 struct intel_encoder *intel_encoder;
10685 struct intel_crtc *intel_crtc;
10686 struct drm_connector *connector;
10687
ba41c0de
DV		 10688 intel_shared_dpll_commit(dev_priv);
10689
b2784e15 10690 for_each_intel_encoder(dev, intel_encoder) {
ea9d758d
DV		 10691 if (!intel_encoder->base.crtc)
10692 continue;
10693
10694 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
10695
10696 if (prepare_pipes & (1 << intel_crtc->pipe))
10697 intel_encoder->connectors_active = false;
10698 }
10699
10700 intel_modeset_commit_output_state(dev);
10701
7668851f 10702 /* Double check state. */
d3fcc808 10703 for_each_intel_crtc(dev, intel_crtc) {
83d65738 10704 WARN_ON(intel_crtc->base.state->enable != intel_crtc_in_use(&intel_crtc->base));
7bd0a8e7 10705 WARN_ON(intel_crtc->new_config &&
6e3c9717 10706 intel_crtc->new_config != intel_crtc->config);
83d65738 10707 WARN_ON(intel_crtc->base.state->enable != !!intel_crtc->new_config);
ea9d758d
DV		 10708 }
10709
10710 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
10711 if (!connector->encoder || !connector->encoder->crtc)
10712 continue;
10713
10714 intel_crtc = to_intel_crtc(connector->encoder->crtc);
10715
10716 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 10717 struct drm_property *dpms_property =
10718 dev->mode_config.dpms_property;
10719
ea9d758d 10720 connector->dpms = DRM_MODE_DPMS_ON;
662595df 10721 drm_object_property_set_value(&connector->base,
68d34720
DV		 10722 dpms_property,
10723 DRM_MODE_DPMS_ON);
ea9d758d
DV		 10724
10725 intel_encoder = to_intel_encoder(connector->encoder);
10726 intel_encoder->connectors_active = true;
10727 }
10728 }
10729
10730}
10731
3bd26263 10732static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 10733{
3bd26263 10734 int diff;
f1f644dc
JB		 10735
10736 if (clock1 == clock2)
10737 return true;
10738
10739 if (!clock1 || !clock2)
10740 return false;
10741
10742 diff = abs(clock1 - clock2);
10743
10744 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
10745 return true;
10746
10747 return false;
10748}
10749
25c5b266
DV		 10750#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
10751 list_for_each_entry((intel_crtc), \
10752 &(dev)->mode_config.crtc_list, \
10753 base.head) \
0973f18f 10754 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 10755
0e8ffe1b 10756static bool
2fa2fe9a 10757intel_pipe_config_compare(struct drm_device *dev,
5cec258b
ACO		 10758 struct intel_crtc_state *current_config,
10759 struct intel_crtc_state *pipe_config)
0e8ffe1b 10760{
66e985c0
DV		 10761#define PIPE_CONF_CHECK_X(name) \
10762 if (current_config->name != pipe_config->name) { \
10763 DRM_ERROR("mismatch in " #name " " \
10764 "(expected 0x%08x, found 0x%08x)\n", \
10765 current_config->name, \
10766 pipe_config->name); \
10767 return false; \
10768 }
10769
08a24034
DV		 10770#define PIPE_CONF_CHECK_I(name) \
10771 if (current_config->name != pipe_config->name) { \
10772 DRM_ERROR("mismatch in " #name " " \
10773 "(expected %i, found %i)\n", \
10774 current_config->name, \
10775 pipe_config->name); \
10776 return false; \
88adfff1
DV		 10777 }
10778
b95af8be
VK		 10779/* This is required for BDW+ where there is only one set of registers for
10780 * switching between high and low RR.
10781 * This macro can be used whenever a comparison has to be made between one
10782 * hw state and multiple sw state variables.
10783 */
10784#define PIPE_CONF_CHECK_I_ALT(name, alt_name) \
10785 if ((current_config->name != pipe_config->name) && \
10786 (current_config->alt_name != pipe_config->name)) { \
10787 DRM_ERROR("mismatch in " #name " " \
10788 "(expected %i or %i, found %i)\n", \
10789 current_config->name, \
10790 current_config->alt_name, \
10791 pipe_config->name); \
10792 return false; \
10793 }
10794
1bd1bd80
DV		 10795#define PIPE_CONF_CHECK_FLAGS(name, mask) \
10796 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 10797 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 10798 "(expected %i, found %i)\n", \
10799 current_config->name & (mask), \
10800 pipe_config->name & (mask)); \
10801 return false; \
10802 }
10803
5e550656
VS		 10804#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
10805 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
10806 DRM_ERROR("mismatch in " #name " " \
10807 "(expected %i, found %i)\n", \
10808 current_config->name, \
10809 pipe_config->name); \
10810 return false; \
10811 }
10812
bb760063
DV		 10813#define PIPE_CONF_QUIRK(quirk) \
10814 ((current_config->quirks | pipe_config->quirks) & (quirk))
10815
eccb140b
DV		 10816 PIPE_CONF_CHECK_I(cpu_transcoder);
10817
08a24034
DV		 10818 PIPE_CONF_CHECK_I(has_pch_encoder);
10819 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 10820 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
10821 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
10822 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
10823 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
10824 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 10825
eb14cb74 10826 PIPE_CONF_CHECK_I(has_dp_encoder);
b95af8be
VK		 10827
10828 if (INTEL_INFO(dev)->gen < 8) {
10829 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
10830 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
10831 PIPE_CONF_CHECK_I(dp_m_n.link_m);
10832 PIPE_CONF_CHECK_I(dp_m_n.link_n);
10833 PIPE_CONF_CHECK_I(dp_m_n.tu);
10834
10835 if (current_config->has_drrs) {
10836 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_m);
10837 PIPE_CONF_CHECK_I(dp_m2_n2.gmch_n);
10838 PIPE_CONF_CHECK_I(dp_m2_n2.link_m);
10839 PIPE_CONF_CHECK_I(dp_m2_n2.link_n);
10840 PIPE_CONF_CHECK_I(dp_m2_n2.tu);
10841 }
10842 } else {
10843 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_m, dp_m2_n2.gmch_m);
10844 PIPE_CONF_CHECK_I_ALT(dp_m_n.gmch_n, dp_m2_n2.gmch_n);
10845 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_m, dp_m2_n2.link_m);
10846 PIPE_CONF_CHECK_I_ALT(dp_m_n.link_n, dp_m2_n2.link_n);
10847 PIPE_CONF_CHECK_I_ALT(dp_m_n.tu, dp_m2_n2.tu);
10848 }
eb14cb74 10849
2d112de7
ACO		 10850 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hdisplay);
10851 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_htotal);
10852 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_start);
10853 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hblank_end);
10854 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_start);
10855 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_hsync_end);
1bd1bd80 10856
2d112de7
ACO		 10857 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vdisplay);
10858 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vtotal);
10859 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_start);
10860 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vblank_end);
10861 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_start);
10862 PIPE_CONF_CHECK_I(base.adjusted_mode.crtc_vsync_end);
1bd1bd80 10863
c93f54cf 10864 PIPE_CONF_CHECK_I(pixel_multiplier);
6897b4b5 10865 PIPE_CONF_CHECK_I(has_hdmi_sink);
b5a9fa09
DV		 10866 if ((INTEL_INFO(dev)->gen < 8 && !IS_HASWELL(dev)) ||
10867 IS_VALLEYVIEW(dev))
10868 PIPE_CONF_CHECK_I(limited_color_range);
e43823ec 10869 PIPE_CONF_CHECK_I(has_infoframe);
6c49f241 10870
9ed109a7
DV		 10871 PIPE_CONF_CHECK_I(has_audio);
10872
2d112de7 10873 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
1bd1bd80
DV		 10874 DRM_MODE_FLAG_INTERLACE);
10875
bb760063 10876 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
2d112de7 10877 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 10878 DRM_MODE_FLAG_PHSYNC);
2d112de7 10879 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 10880 DRM_MODE_FLAG_NHSYNC);
2d112de7 10881 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063 10882 DRM_MODE_FLAG_PVSYNC);
2d112de7 10883 PIPE_CONF_CHECK_FLAGS(base.adjusted_mode.flags,
bb760063
DV		 10884 DRM_MODE_FLAG_NVSYNC);
10885 }
045ac3b5 10886
37327abd
VS		 10887 PIPE_CONF_CHECK_I(pipe_src_w);
10888 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 10889
9953599b
DV		 10890 /*
10891 * FIXME: BIOS likes to set up a cloned config with lvds+external
10892 * screen. Since we don't yet re-compute the pipe config when moving
10893 * just the lvds port away to another pipe the sw tracking won't match.
10894 *
10895 * Proper atomic modesets with recomputed global state will fix this.
10896 * Until then just don't check gmch state for inherited modes.
10897 */
10898 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_INHERITED_MODE)) {
10899 PIPE_CONF_CHECK_I(gmch_pfit.control);
10900 /* pfit ratios are autocomputed by the hw on gen4+ */
10901 if (INTEL_INFO(dev)->gen < 4)
10902 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
10903 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
10904 }
10905
fd4daa9c
CW		 10906 PIPE_CONF_CHECK_I(pch_pfit.enabled);
10907 if (current_config->pch_pfit.enabled) {
10908 PIPE_CONF_CHECK_I(pch_pfit.pos);
10909 PIPE_CONF_CHECK_I(pch_pfit.size);
10910 }
2fa2fe9a 10911
e59150dc
JB		 10912 /* BDW+ don't expose a synchronous way to read the state */
10913 if (IS_HASWELL(dev))
10914 PIPE_CONF_CHECK_I(ips_enabled);
42db64ef 10915
282740f7
VS		 10916 PIPE_CONF_CHECK_I(double_wide);
10917
26804afd
DV		 10918 PIPE_CONF_CHECK_X(ddi_pll_sel);
10919
c0d43d62 10920 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 10921 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 10922 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 10923 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
10924 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
d452c5b6 10925 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
3f4cd19f
DL		 10926 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
10927 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
10928 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
c0d43d62 10929
42571aef
VS		 10930 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
10931 PIPE_CONF_CHECK_I(pipe_bpp);
10932
2d112de7 10933 PIPE_CONF_CHECK_CLOCK_FUZZY(base.adjusted_mode.crtc_clock);
a9a7e98a 10934 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
5e550656 10935
66e985c0 10936#undef PIPE_CONF_CHECK_X
08a24034 10937#undef PIPE_CONF_CHECK_I
b95af8be 10938#undef PIPE_CONF_CHECK_I_ALT
1bd1bd80 10939#undef PIPE_CONF_CHECK_FLAGS
5e550656 10940#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 10941#undef PIPE_CONF_QUIRK
88adfff1 10942
0e8ffe1b
DV		 10943 return true;
10944}
10945
08db6652
DL		 10946static void check_wm_state(struct drm_device *dev)
10947{
10948 struct drm_i915_private *dev_priv = dev->dev_private;
10949 struct skl_ddb_allocation hw_ddb, *sw_ddb;
10950 struct intel_crtc *intel_crtc;
10951 int plane;
10952
10953 if (INTEL_INFO(dev)->gen < 9)
10954 return;
10955
10956 skl_ddb_get_hw_state(dev_priv, &hw_ddb);
10957 sw_ddb = &dev_priv->wm.skl_hw.ddb;
10958
10959 for_each_intel_crtc(dev, intel_crtc) {
10960 struct skl_ddb_entry *hw_entry, *sw_entry;
10961 const enum pipe pipe = intel_crtc->pipe;
10962
10963 if (!intel_crtc->active)
10964 continue;
10965
10966 /* planes */
dd740780 10967 for_each_plane(dev_priv, pipe, plane) {
08db6652
DL		 10968 hw_entry = &hw_ddb.plane[pipe][plane];
10969 sw_entry = &sw_ddb->plane[pipe][plane];
10970
10971 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10972 continue;
10973
10974 DRM_ERROR("mismatch in DDB state pipe %c plane %d "
10975 "(expected (%u,%u), found (%u,%u))\n",
10976 pipe_name(pipe), plane + 1,
10977 sw_entry->start, sw_entry->end,
10978 hw_entry->start, hw_entry->end);
10979 }
10980
10981 /* cursor */
10982 hw_entry = &hw_ddb.cursor[pipe];
10983 sw_entry = &sw_ddb->cursor[pipe];
10984
10985 if (skl_ddb_entry_equal(hw_entry, sw_entry))
10986 continue;
10987
10988 DRM_ERROR("mismatch in DDB state pipe %c cursor "
10989 "(expected (%u,%u), found (%u,%u))\n",
10990 pipe_name(pipe),
10991 sw_entry->start, sw_entry->end,
10992 hw_entry->start, hw_entry->end);
10993 }
10994}
10995
91d1b4bd
DV		 10996static void
10997check_connector_state(struct drm_device *dev)
8af6cf88 10998{
8af6cf88
DV		 10999 struct intel_connector *connector;
11000
3a3371ff 11001 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11002 /* This also checks the encoder/connector hw state with the
11003 * ->get_hw_state callbacks. */
11004 intel_connector_check_state(connector);
11005
e2c719b7 11006 I915_STATE_WARN(&connector->new_encoder->base != connector->base.encoder,
8af6cf88
DV		 11007 "connector's staged encoder doesn't match current encoder\n");
11008 }
91d1b4bd
DV		 11009}
11010
11011static void
11012check_encoder_state(struct drm_device *dev)
11013{
11014 struct intel_encoder *encoder;
11015 struct intel_connector *connector;
8af6cf88 11016
b2784e15 11017 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 11018 bool enabled = false;
11019 bool active = false;
11020 enum pipe pipe, tracked_pipe;
11021
11022 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
11023 encoder->base.base.id,
8e329a03 11024 encoder->base.name);
8af6cf88 11025
e2c719b7 11026 I915_STATE_WARN(&encoder->new_crtc->base != encoder->base.crtc,
8af6cf88 11027 "encoder's stage crtc doesn't match current crtc\n");
e2c719b7 11028 I915_STATE_WARN(encoder->connectors_active && !encoder->base.crtc,
8af6cf88
DV		 11029 "encoder's active_connectors set, but no crtc\n");
11030
3a3371ff 11031 for_each_intel_connector(dev, connector) {
8af6cf88
DV		 11032 if (connector->base.encoder != &encoder->base)
11033 continue;
11034 enabled = true;
11035 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
11036 active = true;
11037 }
0e32b39c
DA		 11038 /*
11039 * for MST connectors if we unplug the connector is gone
11040 * away but the encoder is still connected to a crtc
11041 * until a modeset happens in response to the hotplug.
11042 */
11043 if (!enabled && encoder->base.encoder_type == DRM_MODE_ENCODER_DPMST)
11044 continue;
11045
e2c719b7 11046 I915_STATE_WARN(!!encoder->base.crtc != enabled,
8af6cf88
DV		 11047 "encoder's enabled state mismatch "
11048 "(expected %i, found %i)\n",
11049 !!encoder->base.crtc, enabled);
e2c719b7 11050 I915_STATE_WARN(active && !encoder->base.crtc,
8af6cf88
DV		 11051 "active encoder with no crtc\n");
11052
e2c719b7 11053 I915_STATE_WARN(encoder->connectors_active != active,
8af6cf88
DV		 11054 "encoder's computed active state doesn't match tracked active state "
11055 "(expected %i, found %i)\n", active, encoder->connectors_active);
11056
11057 active = encoder->get_hw_state(encoder, &pipe);
e2c719b7 11058 I915_STATE_WARN(active != encoder->connectors_active,
8af6cf88
DV		 11059 "encoder's hw state doesn't match sw tracking "
11060 "(expected %i, found %i)\n",
11061 encoder->connectors_active, active);
11062
11063 if (!encoder->base.crtc)
11064 continue;
11065
11066 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
e2c719b7 11067 I915_STATE_WARN(active && pipe != tracked_pipe,
8af6cf88
DV		 11068 "active encoder's pipe doesn't match"
11069 "(expected %i, found %i)\n",
11070 tracked_pipe, pipe);
11071
11072 }
91d1b4bd
DV		 11073}
11074
11075static void
11076check_crtc_state(struct drm_device *dev)
11077{
fbee40df 11078 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 11079 struct intel_crtc *crtc;
11080 struct intel_encoder *encoder;
5cec258b 11081 struct intel_crtc_state pipe_config;
8af6cf88 11082
d3fcc808 11083 for_each_intel_crtc(dev, crtc) {
8af6cf88
DV		 11084 bool enabled = false;
11085 bool active = false;
11086
045ac3b5
JB		 11087 memset(&pipe_config, 0, sizeof(pipe_config));
11088
8af6cf88
DV		 11089 DRM_DEBUG_KMS("[CRTC:%d]\n",
11090 crtc->base.base.id);
11091
83d65738 11092 I915_STATE_WARN(crtc->active && !crtc->base.state->enable,
8af6cf88
DV		 11093 "active crtc, but not enabled in sw tracking\n");
11094
b2784e15 11095 for_each_intel_encoder(dev, encoder) {
8af6cf88
DV		 11096 if (encoder->base.crtc != &crtc->base)
11097 continue;
11098 enabled = true;
11099 if (encoder->connectors_active)
11100 active = true;
11101 }
6c49f241 11102
e2c719b7 11103 I915_STATE_WARN(active != crtc->active,
8af6cf88
DV		 11104 "crtc's computed active state doesn't match tracked active state "
11105 "(expected %i, found %i)\n", active, crtc->active);
83d65738 11106 I915_STATE_WARN(enabled != crtc->base.state->enable,
8af6cf88 11107 "crtc's computed enabled state doesn't match tracked enabled state "
83d65738
MR		 11108 "(expected %i, found %i)\n", enabled,
11109 crtc->base.state->enable);
8af6cf88 11110
0e8ffe1b
DV		 11111 active = dev_priv->display.get_pipe_config(crtc,
11112 &pipe_config);
d62cf62a 11113
b6b5d049
VS		 11114 /* hw state is inconsistent with the pipe quirk */
11115 if ((crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) ||
11116 (crtc->pipe == PIPE_B && dev_priv->quirks & QUIRK_PIPEB_FORCE))
d62cf62a
DV		 11117 active = crtc->active;
11118
b2784e15 11119 for_each_intel_encoder(dev, encoder) {
3eaba51c 11120 enum pipe pipe;
6c49f241
DV		 11121 if (encoder->base.crtc != &crtc->base)
11122 continue;
1d37b689 11123 if (encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 11124 encoder->get_config(encoder, &pipe_config);
11125 }
11126
e2c719b7 11127 I915_STATE_WARN(crtc->active != active,
0e8ffe1b
DV		 11128 "crtc active state doesn't match with hw state "
11129 "(expected %i, found %i)\n", crtc->active, active);
11130
c0b03411 11131 if (active &&
6e3c9717 11132 !intel_pipe_config_compare(dev, crtc->config, &pipe_config)) {
e2c719b7 11133 I915_STATE_WARN(1, "pipe state doesn't match!\n");
c0b03411
DV		 11134 intel_dump_pipe_config(crtc, &pipe_config,
11135 "[hw state]");
6e3c9717 11136 intel_dump_pipe_config(crtc, crtc->config,
c0b03411
DV		 11137 "[sw state]");
11138 }
8af6cf88
DV		 11139 }
11140}
11141
91d1b4bd
DV		 11142static void
11143check_shared_dpll_state(struct drm_device *dev)
11144{
fbee40df 11145 struct drm_i915_private *dev_priv = dev->dev_private;
91d1b4bd
DV		 11146 struct intel_crtc *crtc;
11147 struct intel_dpll_hw_state dpll_hw_state;
11148 int i;
5358901f
DV		 11149
11150 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
11151 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
11152 int enabled_crtcs = 0, active_crtcs = 0;
11153 bool active;
11154
11155 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
11156
11157 DRM_DEBUG_KMS("%s\n", pll->name);
11158
11159 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
11160
e2c719b7 11161 I915_STATE_WARN(pll->active > hweight32(pll->config.crtc_mask),
5358901f 11162 "more active pll users than references: %i vs %i\n",
3e369b76 11163 pll->active, hweight32(pll->config.crtc_mask));
e2c719b7 11164 I915_STATE_WARN(pll->active && !pll->on,
5358901f 11165 "pll in active use but not on in sw tracking\n");
e2c719b7 11166 I915_STATE_WARN(pll->on && !pll->active,
35c95375 11167 "pll in on but not on in use in sw tracking\n");
e2c719b7 11168 I915_STATE_WARN(pll->on != active,
5358901f
DV		 11169 "pll on state mismatch (expected %i, found %i)\n",
11170 pll->on, active);
11171
d3fcc808 11172 for_each_intel_crtc(dev, crtc) {
83d65738 11173 if (crtc->base.state->enable && intel_crtc_to_shared_dpll(crtc) == pll)
5358901f
DV		 11174 enabled_crtcs++;
11175 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
11176 active_crtcs++;
11177 }
e2c719b7 11178 I915_STATE_WARN(pll->active != active_crtcs,
5358901f
DV		 11179 "pll active crtcs mismatch (expected %i, found %i)\n",
11180 pll->active, active_crtcs);
e2c719b7 11181 I915_STATE_WARN(hweight32(pll->config.crtc_mask) != enabled_crtcs,
5358901f 11182 "pll enabled crtcs mismatch (expected %i, found %i)\n",
3e369b76 11183 hweight32(pll->config.crtc_mask), enabled_crtcs);
66e985c0 11184
e2c719b7 11185 I915_STATE_WARN(pll->on && memcmp(&pll->config.hw_state, &dpll_hw_state,
66e985c0
DV		 11186 sizeof(dpll_hw_state)),
11187 "pll hw state mismatch\n");
5358901f 11188 }
8af6cf88
DV		 11189}
11190
91d1b4bd
DV		 11191void
11192intel_modeset_check_state(struct drm_device *dev)
11193{
08db6652 11194 check_wm_state(dev);
91d1b4bd
DV		 11195 check_connector_state(dev);
11196 check_encoder_state(dev);
11197 check_crtc_state(dev);
11198 check_shared_dpll_state(dev);
11199}
11200
5cec258b 11201void ironlake_check_encoder_dotclock(const struct intel_crtc_state *pipe_config,
18442d08
VS		 11202 int dotclock)
11203{
11204 /*
11205 * FDI already provided one idea for the dotclock.
11206 * Yell if the encoder disagrees.
11207 */
2d112de7 11208 WARN(!intel_fuzzy_clock_check(pipe_config->base.adjusted_mode.crtc_clock, dotclock),
18442d08 11209 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
2d112de7 11210 pipe_config->base.adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 11211}
11212
80715b2f
VS		 11213static void update_scanline_offset(struct intel_crtc *crtc)
11214{
11215 struct drm_device *dev = crtc->base.dev;
11216
11217 /*
11218 * The scanline counter increments at the leading edge of hsync.
11219 *
11220 * On most platforms it starts counting from vtotal-1 on the
11221 * first active line. That means the scanline counter value is
11222 * always one less than what we would expect. Ie. just after
11223 * start of vblank, which also occurs at start of hsync (on the
11224 * last active line), the scanline counter will read vblank_start-1.
11225 *
11226 * On gen2 the scanline counter starts counting from 1 instead
11227 * of vtotal-1, so we have to subtract one (or rather add vtotal-1
11228 * to keep the value positive), instead of adding one.
11229 *
11230 * On HSW+ the behaviour of the scanline counter depends on the output
11231 * type. For DP ports it behaves like most other platforms, but on HDMI
11232 * there's an extra 1 line difference. So we need to add two instead of
11233 * one to the value.
11234 */
11235 if (IS_GEN2(dev)) {
6e3c9717 11236 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
80715b2f
VS		 11237 int vtotal;
11238
11239 vtotal = mode->crtc_vtotal;
11240 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
11241 vtotal /= 2;
11242
11243 crtc->scanline_offset = vtotal - 1;
11244 } else if (HAS_DDI(dev) &&
409ee761 11245 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI)) {
80715b2f
VS		 11246 crtc->scanline_offset = 2;
11247 } else
11248 crtc->scanline_offset = 1;
11249}
11250
5cec258b 11251static struct intel_crtc_state *
7f27126e
JB		 11252intel_modeset_compute_config(struct drm_crtc *crtc,
11253 struct drm_display_mode *mode,
11254 struct drm_framebuffer *fb,
11255 unsigned *modeset_pipes,
11256 unsigned *prepare_pipes,
11257 unsigned *disable_pipes)
11258{
5cec258b 11259 struct intel_crtc_state *pipe_config = NULL;
7f27126e
JB		 11260
11261 intel_modeset_affected_pipes(crtc, modeset_pipes,
11262 prepare_pipes, disable_pipes);
11263
11264 if ((*modeset_pipes) == 0)
11265 goto out;
11266
11267 /*
11268 * Note this needs changes when we start tracking multiple modes
11269 * and crtcs. At that point we'll need to compute the whole config
11270 * (i.e. one pipe_config for each crtc) rather than just the one
11271 * for this crtc.
11272 */
11273 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
11274 if (IS_ERR(pipe_config)) {
11275 goto out;
11276 }
11277 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
11278 "[modeset]");
7f27126e
JB		 11279
11280out:
11281 return pipe_config;
11282}
11283
ed6739ef
ACO		 11284static int __intel_set_mode_setup_plls(struct drm_device *dev,
11285 unsigned modeset_pipes,
11286 unsigned disable_pipes)
11287{
11288 struct drm_i915_private *dev_priv = to_i915(dev);
11289 unsigned clear_pipes = modeset_pipes | disable_pipes;
11290 struct intel_crtc *intel_crtc;
11291 int ret = 0;
11292
11293 if (!dev_priv->display.crtc_compute_clock)
11294 return 0;
11295
11296 ret = intel_shared_dpll_start_config(dev_priv, clear_pipes);
11297 if (ret)
11298 goto done;
11299
11300 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
11301 struct intel_crtc_state *state = intel_crtc->new_config;
11302 ret = dev_priv->display.crtc_compute_clock(intel_crtc,
11303 state);
11304 if (ret) {
11305 intel_shared_dpll_abort_config(dev_priv);
11306 goto done;
11307 }
11308 }
11309
11310done:
11311 return ret;
11312}
11313
f30da187
DV		 11314static int __intel_set_mode(struct drm_crtc *crtc,
11315 struct drm_display_mode *mode,
7f27126e 11316 int x, int y, struct drm_framebuffer *fb,
5cec258b 11317 struct intel_crtc_state *pipe_config,
7f27126e
JB		 11318 unsigned modeset_pipes,
11319 unsigned prepare_pipes,
11320 unsigned disable_pipes)
a6778b3c
DV		 11321{
11322 struct drm_device *dev = crtc->dev;
fbee40df 11323 struct drm_i915_private *dev_priv = dev->dev_private;
4b4b9238 11324 struct drm_display_mode *saved_mode;
25c5b266 11325 struct intel_crtc *intel_crtc;
c0c36b94 11326 int ret = 0;
a6778b3c 11327
4b4b9238 11328 saved_mode = kmalloc(sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 11329 if (!saved_mode)
11330 return -ENOMEM;
a6778b3c 11331
3ac18232 11332 *saved_mode = crtc->mode;
a6778b3c 11333
b9950a13
VS		 11334 if (modeset_pipes)
11335 to_intel_crtc(crtc)->new_config = pipe_config;
11336
30a970c6
JB		 11337 /*
11338 * See if the config requires any additional preparation, e.g.
11339 * to adjust global state with pipes off. We need to do this
11340 * here so we can get the modeset_pipe updated config for the new
11341 * mode set on this crtc. For other crtcs we need to use the
11342 * adjusted_mode bits in the crtc directly.
11343 */
c164f833 11344 if (IS_VALLEYVIEW(dev)) {
2f2d7aa1 11345 valleyview_modeset_global_pipes(dev, &prepare_pipes);
30a970c6 11346
c164f833
VS		 11347 /* may have added more to prepare_pipes than we should */
11348 prepare_pipes &= ~disable_pipes;
11349 }
11350
ed6739ef
ACO		 11351 ret = __intel_set_mode_setup_plls(dev, modeset_pipes, disable_pipes);
11352 if (ret)
11353 goto done;
8bd31e67 11354
460da916
DV		 11355 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
11356 intel_crtc_disable(&intel_crtc->base);
11357
ea9d758d 11358 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
83d65738 11359 if (intel_crtc->base.state->enable)
ea9d758d
DV		 11360 dev_priv->display.crtc_disable(&intel_crtc->base);
11361 }
a6778b3c 11362
6c4c86f5
DV		 11363 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
11364 * to set it here already despite that we pass it down the callchain.
7f27126e
JB		 11365 *
11366 * Note we'll need to fix this up when we start tracking multiple
11367 * pipes; here we assume a single modeset_pipe and only track the
11368 * single crtc and mode.
f6e5b160 11369 */
b8cecdf5 11370 if (modeset_pipes) {
25c5b266 11371 crtc->mode = *mode;
b8cecdf5
DV		 11372 /* mode_set/enable/disable functions rely on a correct pipe
11373 * config. */
f5de6e07 11374 intel_crtc_set_state(to_intel_crtc(crtc), pipe_config);
c326c0a9
VS		 11375
11376 /*
11377 * Calculate and store various constants which
11378 * are later needed by vblank and swap-completion
11379 * timestamping. They are derived from true hwmode.
11380 */
11381 drm_calc_timestamping_constants(crtc,
2d112de7 11382 &pipe_config->base.adjusted_mode);
b8cecdf5 11383 }
7758a113 11384
ea9d758d
DV		 11385 /* Only after disabling all output pipelines that will be changed can we
11386 * update the the output configuration. */
11387 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 11388
50f6e502 11389 modeset_update_crtc_power_domains(dev);
47fab737 11390
a6778b3c
DV		 11391 /* Set up the DPLL and any encoders state that needs to adjust or depend
11392 * on the DPLL.
f6e5b160 11393 */
25c5b266 11394 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
455a6808
GP		 11395 struct drm_plane *primary = intel_crtc->base.primary;
11396 int vdisplay, hdisplay;
4c10794f 11397
455a6808
GP		 11398 drm_crtc_get_hv_timing(mode, &hdisplay, &vdisplay);
11399 ret = primary->funcs->update_plane(primary, &intel_crtc->base,
11400 fb, 0, 0,
11401 hdisplay, vdisplay,
11402 x << 16, y << 16,
11403 hdisplay << 16, vdisplay << 16);
a6778b3c
DV		 11404 }
11405
11406 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
80715b2f
VS		 11407 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
11408 update_scanline_offset(intel_crtc);
11409
25c5b266 11410 dev_priv->display.crtc_enable(&intel_crtc->base);
80715b2f 11411 }
a6778b3c 11412
a6778b3c
DV		 11413 /* FIXME: add subpixel order */
11414done:
83d65738 11415 if (ret && crtc->state->enable)
3ac18232 11416 crtc->mode = *saved_mode;
a6778b3c 11417
3ac18232 11418 kfree(saved_mode);
a6778b3c 11419 return ret;
f6e5b160
CW		 11420}
11421
7f27126e
JB		 11422static int intel_set_mode_pipes(struct drm_crtc *crtc,
11423 struct drm_display_mode *mode,
11424 int x, int y, struct drm_framebuffer *fb,
5cec258b 11425 struct intel_crtc_state *pipe_config,
7f27126e
JB		 11426 unsigned modeset_pipes,
11427 unsigned prepare_pipes,
11428 unsigned disable_pipes)
f30da187
DV		 11429{
11430 int ret;
11431
7f27126e
JB		 11432 ret = __intel_set_mode(crtc, mode, x, y, fb, pipe_config, modeset_pipes,
11433 prepare_pipes, disable_pipes);
f30da187
DV		 11434
11435 if (ret == 0)
11436 intel_modeset_check_state(crtc->dev);
11437
11438 return ret;
11439}
11440
7f27126e
JB		 11441static int intel_set_mode(struct drm_crtc *crtc,
11442 struct drm_display_mode *mode,
11443 int x, int y, struct drm_framebuffer *fb)
11444{
5cec258b 11445 struct intel_crtc_state *pipe_config;
7f27126e
JB		 11446 unsigned modeset_pipes, prepare_pipes, disable_pipes;
11447
11448 pipe_config = intel_modeset_compute_config(crtc, mode, fb,
11449 &modeset_pipes,
11450 &prepare_pipes,
11451 &disable_pipes);
11452
11453 if (IS_ERR(pipe_config))
11454 return PTR_ERR(pipe_config);
11455
11456 return intel_set_mode_pipes(crtc, mode, x, y, fb, pipe_config,
11457 modeset_pipes, prepare_pipes,
11458 disable_pipes);
11459}
11460
c0c36b94
CW		 11461void intel_crtc_restore_mode(struct drm_crtc *crtc)
11462{
f4510a27 11463 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->primary->fb);
c0c36b94
CW		 11464}
11465
25c5b266
DV		 11466#undef for_each_intel_crtc_masked
11467
d9e55608
DV		 11468static void intel_set_config_free(struct intel_set_config *config)
11469{
11470 if (!config)
11471 return;
11472
1aa4b628
DV		 11473 kfree(config->save_connector_encoders);
11474 kfree(config->save_encoder_crtcs);
7668851f 11475 kfree(config->save_crtc_enabled);
d9e55608
DV		 11476 kfree(config);
11477}
11478
85f9eb71
DV		 11479static int intel_set_config_save_state(struct drm_device *dev,
11480 struct intel_set_config *config)
11481{
7668851f 11482 struct drm_crtc *crtc;
85f9eb71
DV		 11483 struct drm_encoder *encoder;
11484 struct drm_connector *connector;
11485 int count;
11486
7668851f
VS		 11487 config->save_crtc_enabled =
11488 kcalloc(dev->mode_config.num_crtc,
11489 sizeof(bool), GFP_KERNEL);
11490 if (!config->save_crtc_enabled)
11491 return -ENOMEM;
11492
1aa4b628
DV		 11493 config->save_encoder_crtcs =
11494 kcalloc(dev->mode_config.num_encoder,
11495 sizeof(struct drm_crtc *), GFP_KERNEL);
11496 if (!config->save_encoder_crtcs)
85f9eb71
DV		 11497 return -ENOMEM;
11498
1aa4b628
DV		 11499 config->save_connector_encoders =
11500 kcalloc(dev->mode_config.num_connector,
11501 sizeof(struct drm_encoder *), GFP_KERNEL);
11502 if (!config->save_connector_encoders)
85f9eb71
DV		 11503 return -ENOMEM;
11504
11505 /* Copy data. Note that driver private data is not affected.
11506 * Should anything bad happen only the expected state is
11507 * restored, not the drivers personal bookkeeping.
11508 */
7668851f 11509 count = 0;
70e1e0ec 11510 for_each_crtc(dev, crtc) {
83d65738 11511 config->save_crtc_enabled[count++] = crtc->state->enable;
7668851f
VS		 11512 }
11513
85f9eb71
DV		 11514 count = 0;
11515 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 11516 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 11517 }
11518
11519 count = 0;
11520 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 11521 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 11522 }
11523
11524 return 0;
11525}
11526
11527static void intel_set_config_restore_state(struct drm_device *dev,
11528 struct intel_set_config *config)
11529{
7668851f 11530 struct intel_crtc *crtc;
9a935856
DV		 11531 struct intel_encoder *encoder;
11532 struct intel_connector *connector;
85f9eb71
DV		 11533 int count;
11534
7668851f 11535 count = 0;
d3fcc808 11536 for_each_intel_crtc(dev, crtc) {
7668851f 11537 crtc->new_enabled = config->save_crtc_enabled[count++];
7bd0a8e7
VS		 11538
11539 if (crtc->new_enabled)
6e3c9717 11540 crtc->new_config = crtc->config;
7bd0a8e7
VS		 11541 else
11542 crtc->new_config = NULL;
7668851f
VS		 11543 }
11544
85f9eb71 11545 count = 0;
b2784e15 11546 for_each_intel_encoder(dev, encoder) {
9a935856
DV		 11547 encoder->new_crtc =
11548 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 11549 }
11550
11551 count = 0;
3a3371ff 11552 for_each_intel_connector(dev, connector) {
9a935856
DV		 11553 connector->new_encoder =
11554 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 11555 }
11556}
11557
e3de42b6 11558static bool
2e57f47d 11559is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 11560{
11561 int i;
11562
2e57f47d
CW		 11563 if (set->num_connectors == 0)
11564 return false;
11565
11566 if (WARN_ON(set->connectors == NULL))
11567 return false;
11568
11569 for (i = 0; i < set->num_connectors; i++)
11570 if (set->connectors[i]->encoder &&
11571 set->connectors[i]->encoder->crtc == set->crtc &&
11572 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 11573 return true;
11574
11575 return false;
11576}
11577
5e2b584e
DV		 11578static void
11579intel_set_config_compute_mode_changes(struct drm_mode_set *set,
11580 struct intel_set_config *config)
11581{
11582
11583 /* We should be able to check here if the fb has the same properties
11584 * and then just flip_or_move it */
2e57f47d
CW		 11585 if (is_crtc_connector_off(set)) {
11586 config->mode_changed = true;
f4510a27 11587 } else if (set->crtc->primary->fb != set->fb) {
3b150f08
MR		 11588 /*
11589 * If we have no fb, we can only flip as long as the crtc is
11590 * active, otherwise we need a full mode set. The crtc may
11591 * be active if we've only disabled the primary plane, or
11592 * in fastboot situations.
11593 */
f4510a27 11594 if (set->crtc->primary->fb == NULL) {
319d9827
JB		 11595 struct intel_crtc *intel_crtc =
11596 to_intel_crtc(set->crtc);
11597
3b150f08 11598 if (intel_crtc->active) {
319d9827
JB		 11599 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
11600 config->fb_changed = true;
11601 } else {
11602 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
11603 config->mode_changed = true;
11604 }
5e2b584e
DV		 11605 } else if (set->fb == NULL) {
11606 config->mode_changed = true;
72f4901e 11607 } else if (set->fb->pixel_format !=
f4510a27 11608 set->crtc->primary->fb->pixel_format) {
5e2b584e 11609 config->mode_changed = true;
e3de42b6 11610 } else {
5e2b584e 11611 config->fb_changed = true;
e3de42b6 11612 }
5e2b584e
DV		 11613 }
11614
835c5873 11615 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 11616 config->fb_changed = true;
11617
11618 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
11619 DRM_DEBUG_KMS("modes are different, full mode set\n");
11620 drm_mode_debug_printmodeline(&set->crtc->mode);
11621 drm_mode_debug_printmodeline(set->mode);
11622 config->mode_changed = true;
11623 }
a1d95703
CW		 11624
11625 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
11626 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 11627}
11628
2e431051 11629static int
9a935856
DV		 11630intel_modeset_stage_output_state(struct drm_device *dev,
11631 struct drm_mode_set *set,
11632 struct intel_set_config *config)
50f56119 11633{
9a935856
DV		 11634 struct intel_connector *connector;
11635 struct intel_encoder *encoder;
7668851f 11636 struct intel_crtc *crtc;
f3f08572 11637 int ro;
50f56119 11638
9abdda74 11639 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 11640 * of connectors. For paranoia, double-check this. */
11641 WARN_ON(!set->fb && (set->num_connectors != 0));
11642 WARN_ON(set->fb && (set->num_connectors == 0));
11643
3a3371ff 11644 for_each_intel_connector(dev, connector) {
9a935856
DV		 11645 /* Otherwise traverse passed in connector list and get encoders
11646 * for them. */
50f56119 11647 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 11648 if (set->connectors[ro] == &connector->base) {
0e32b39c 11649 connector->new_encoder = intel_find_encoder(connector, to_intel_crtc(set->crtc)->pipe);
50f56119
DV		 11650 break;
11651 }
11652 }
11653
9a935856
DV		 11654 /* If we disable the crtc, disable all its connectors. Also, if
11655 * the connector is on the changing crtc but not on the new
11656 * connector list, disable it. */
11657 if ((!set->fb || ro == set->num_connectors) &&
11658 connector->base.encoder &&
11659 connector->base.encoder->crtc == set->crtc) {
11660 connector->new_encoder = NULL;
11661
11662 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
11663 connector->base.base.id,
c23cc417 11664 connector->base.name);
9a935856
DV		 11665 }
11666
11667
11668 if (&connector->new_encoder->base != connector->base.encoder) {
10634189
ACO		 11669 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] encoder changed, full mode switch\n",
11670 connector->base.base.id,
11671 connector->base.name);
5e2b584e 11672 config->mode_changed = true;
50f56119
DV		 11673 }
11674 }
9a935856 11675 /* connector->new_encoder is now updated for all connectors. */
50f56119 11676
9a935856 11677 /* Update crtc of enabled connectors. */
3a3371ff 11678 for_each_intel_connector(dev, connector) {
7668851f
VS		 11679 struct drm_crtc *new_crtc;
11680
9a935856 11681 if (!connector->new_encoder)
50f56119
DV		 11682 continue;
11683
9a935856 11684 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 11685
11686 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 11687 if (set->connectors[ro] == &connector->base)
50f56119
DV		 11688 new_crtc = set->crtc;
11689 }
11690
11691 /* Make sure the new CRTC will work with the encoder */
14509916
TR		 11692 if (!drm_encoder_crtc_ok(&connector->new_encoder->base,
11693 new_crtc)) {
5e2b584e 11694 return -EINVAL;
50f56119 11695 }
0e32b39c 11696 connector->new_encoder->new_crtc = to_intel_crtc(new_crtc);
9a935856
DV		 11697
11698 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
11699 connector->base.base.id,
c23cc417 11700 connector->base.name,
9a935856
DV		 11701 new_crtc->base.id);
11702 }
11703
11704 /* Check for any encoders that needs to be disabled. */
b2784e15 11705 for_each_intel_encoder(dev, encoder) {
5a65f358 11706 int num_connectors = 0;
3a3371ff 11707 for_each_intel_connector(dev, connector) {
9a935856
DV		 11708 if (connector->new_encoder == encoder) {
11709 WARN_ON(!connector->new_encoder->new_crtc);
5a65f358 11710 num_connectors++;
9a935856
DV		 11711 }
11712 }
5a65f358
PZ		 11713
11714 if (num_connectors == 0)
11715 encoder->new_crtc = NULL;
11716 else if (num_connectors > 1)
11717 return -EINVAL;
11718
9a935856
DV		 11719 /* Only now check for crtc changes so we don't miss encoders
11720 * that will be disabled. */
11721 if (&encoder->new_crtc->base != encoder->base.crtc) {
10634189
ACO		 11722 DRM_DEBUG_KMS("[ENCODER:%d:%s] crtc changed, full mode switch\n",
11723 encoder->base.base.id,
11724 encoder->base.name);
5e2b584e 11725 config->mode_changed = true;
50f56119
DV		 11726 }
11727 }
9a935856 11728 /* Now we've also updated encoder->new_crtc for all encoders. */
3a3371ff 11729 for_each_intel_connector(dev, connector) {
0e32b39c
DA		 11730 if (connector->new_encoder)
11731 if (connector->new_encoder != connector->encoder)
11732 connector->encoder = connector->new_encoder;
11733 }
d3fcc808 11734 for_each_intel_crtc(dev, crtc) {
7668851f
VS		 11735 crtc->new_enabled = false;
11736
b2784e15 11737 for_each_intel_encoder(dev, encoder) {
7668851f
VS		 11738 if (encoder->new_crtc == crtc) {
11739 crtc->new_enabled = true;
11740 break;
11741 }
11742 }
11743
83d65738 11744 if (crtc->new_enabled != crtc->base.state->enable) {
10634189
ACO		 11745 DRM_DEBUG_KMS("[CRTC:%d] %sabled, full mode switch\n",
11746 crtc->base.base.id,
7668851f
VS		 11747 crtc->new_enabled ? "en" : "dis");
11748 config->mode_changed = true;
11749 }
7bd0a8e7
VS		 11750
11751 if (crtc->new_enabled)
6e3c9717 11752 crtc->new_config = crtc->config;
7bd0a8e7
VS		 11753 else
11754 crtc->new_config = NULL;
7668851f
VS		 11755 }
11756
2e431051
DV		 11757 return 0;
11758}
11759
7d00a1f5
VS		 11760static void disable_crtc_nofb(struct intel_crtc *crtc)
11761{
11762 struct drm_device *dev = crtc->base.dev;
11763 struct intel_encoder *encoder;
11764 struct intel_connector *connector;
11765
11766 DRM_DEBUG_KMS("Trying to restore without FB -> disabling pipe %c\n",
11767 pipe_name(crtc->pipe));
11768
3a3371ff 11769 for_each_intel_connector(dev, connector) {
7d00a1f5
VS		 11770 if (connector->new_encoder &&
11771 connector->new_encoder->new_crtc == crtc)
11772 connector->new_encoder = NULL;
11773 }
11774
b2784e15 11775 for_each_intel_encoder(dev, encoder) {
7d00a1f5
VS		 11776 if (encoder->new_crtc == crtc)
11777 encoder->new_crtc = NULL;
11778 }
11779
11780 crtc->new_enabled = false;
7bd0a8e7 11781 crtc->new_config = NULL;
7d00a1f5
VS		 11782}
11783
2e431051
DV		 11784static int intel_crtc_set_config(struct drm_mode_set *set)
11785{
11786 struct drm_device *dev;
2e431051
DV		 11787 struct drm_mode_set save_set;
11788 struct intel_set_config *config;
5cec258b 11789 struct intel_crtc_state *pipe_config;
50f52756 11790 unsigned modeset_pipes, prepare_pipes, disable_pipes;
2e431051 11791 int ret;
2e431051 11792
8d3e375e
DV		 11793 BUG_ON(!set);
11794 BUG_ON(!set->crtc);
11795 BUG_ON(!set->crtc->helper_private);
2e431051 11796
7e53f3a4
DV		 11797 /* Enforce sane interface api - has been abused by the fb helper. */
11798 BUG_ON(!set->mode && set->fb);
11799 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 11800
2e431051
DV		 11801 if (set->fb) {
11802 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
11803 set->crtc->base.id, set->fb->base.id,
11804 (int)set->num_connectors, set->x, set->y);
11805 } else {
11806 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 11807 }
11808
11809 dev = set->crtc->dev;
11810
11811 ret = -ENOMEM;
11812 config = kzalloc(sizeof(*config), GFP_KERNEL);
11813 if (!config)
11814 goto out_config;
11815
11816 ret = intel_set_config_save_state(dev, config);
11817 if (ret)
11818 goto out_config;
11819
11820 save_set.crtc = set->crtc;
11821 save_set.mode = &set->crtc->mode;
11822 save_set.x = set->crtc->x;
11823 save_set.y = set->crtc->y;
f4510a27 11824 save_set.fb = set->crtc->primary->fb;
2e431051
DV		 11825
11826 /* Compute whether we need a full modeset, only an fb base update or no
11827 * change at all. In the future we might also check whether only the
11828 * mode changed, e.g. for LVDS where we only change the panel fitter in
11829 * such cases. */
11830 intel_set_config_compute_mode_changes(set, config);
11831
9a935856 11832 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 11833 if (ret)
11834 goto fail;
11835
50f52756
JB		 11836 pipe_config = intel_modeset_compute_config(set->crtc, set->mode,
11837 set->fb,
11838 &modeset_pipes,
11839 &prepare_pipes,
11840 &disable_pipes);
20664591 11841 if (IS_ERR(pipe_config)) {
6ac0483b 11842 ret = PTR_ERR(pipe_config);
50f52756 11843 goto fail;
20664591 11844 } else if (pipe_config) {
b9950a13 11845 if (pipe_config->has_audio !=
6e3c9717 11846 to_intel_crtc(set->crtc)->config->has_audio)
20664591
JB		 11847 config->mode_changed = true;
11848
af15d2ce
JB		 11849 /*
11850 * Note we have an issue here with infoframes: current code
11851 * only updates them on the full mode set path per hw
11852 * requirements. So here we should be checking for any
11853 * required changes and forcing a mode set.
11854 */
20664591 11855 }
50f52756
JB		 11856
11857 /* set_mode will free it in the mode_changed case */
11858 if (!config->mode_changed)
11859 kfree(pipe_config);
11860
1f9954d0
JB		 11861 intel_update_pipe_size(to_intel_crtc(set->crtc));
11862
5e2b584e 11863 if (config->mode_changed) {
50f52756
JB		 11864 ret = intel_set_mode_pipes(set->crtc, set->mode,
11865 set->x, set->y, set->fb, pipe_config,
11866 modeset_pipes, prepare_pipes,
11867 disable_pipes);
5e2b584e 11868 } else if (config->fb_changed) {
3b150f08 11869 struct intel_crtc *intel_crtc = to_intel_crtc(set->crtc);
455a6808
GP		 11870 struct drm_plane *primary = set->crtc->primary;
11871 int vdisplay, hdisplay;
3b150f08 11872
455a6808
GP		 11873 drm_crtc_get_hv_timing(set->mode, &hdisplay, &vdisplay);
11874 ret = primary->funcs->update_plane(primary, set->crtc, set->fb,
11875 0, 0, hdisplay, vdisplay,
11876 set->x << 16, set->y << 16,
11877 hdisplay << 16, vdisplay << 16);
3b150f08
MR		 11878
11879 /*
11880 * We need to make sure the primary plane is re-enabled if it
11881 * has previously been turned off.
11882 */
11883 if (!intel_crtc->primary_enabled && ret == 0) {
11884 WARN_ON(!intel_crtc->active);
fdd508a6 11885 intel_enable_primary_hw_plane(set->crtc->primary, set->crtc);
3b150f08
MR		 11886 }
11887
7ca51a3a
JB		 11888 /*
11889 * In the fastboot case this may be our only check of the
11890 * state after boot. It would be better to only do it on
11891 * the first update, but we don't have a nice way of doing that
11892 * (and really, set_config isn't used much for high freq page
11893 * flipping, so increasing its cost here shouldn't be a big
11894 * deal).
11895 */
d330a953 11896 if (i915.fastboot && ret == 0)
7ca51a3a 11897 intel_modeset_check_state(set->crtc->dev);
50f56119
DV		 11898 }
11899
2d05eae1 11900 if (ret) {
bf67dfeb
DV		 11901 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
11902 set->crtc->base.id, ret);
50f56119 11903fail:
2d05eae1 11904 intel_set_config_restore_state(dev, config);
50f56119 11905
7d00a1f5
VS		 11906 /*
11907 * HACK: if the pipe was on, but we didn't have a framebuffer,
11908 * force the pipe off to avoid oopsing in the modeset code
11909 * due to fb==NULL. This should only happen during boot since
11910 * we don't yet reconstruct the FB from the hardware state.
11911 */
11912 if (to_intel_crtc(save_set.crtc)->new_enabled && !save_set.fb)
11913 disable_crtc_nofb(to_intel_crtc(save_set.crtc));
11914
2d05eae1
CW		 11915 /* Try to restore the config */
11916 if (config->mode_changed &&
11917 intel_set_mode(save_set.crtc, save_set.mode,
11918 save_set.x, save_set.y, save_set.fb))
11919 DRM_ERROR("failed to restore config after modeset failure\n");
11920 }
50f56119 11921
d9e55608
DV		 11922out_config:
11923 intel_set_config_free(config);
50f56119
DV		 11924 return ret;
11925}
f6e5b160
CW		 11926
11927static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160 11928 .gamma_set = intel_crtc_gamma_set,
50f56119 11929 .set_config = intel_crtc_set_config,
f6e5b160
CW		 11930 .destroy = intel_crtc_destroy,
11931 .page_flip = intel_crtc_page_flip,
1356837e
MR		 11932 .atomic_duplicate_state = intel_crtc_duplicate_state,
11933 .atomic_destroy_state = intel_crtc_destroy_state,
f6e5b160
CW		 11934};
11935
5358901f
DV		 11936static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
11937 struct intel_shared_dpll *pll,
11938 struct intel_dpll_hw_state *hw_state)
ee7b9f93 11939{
5358901f 11940 uint32_t val;
ee7b9f93 11941
f458ebbc 11942 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PLLS))
bd2bb1b9
PZ		 11943 return false;
11944
5358901f 11945 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 11946 hw_state->dpll = val;
11947 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
11948 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 11949
11950 return val & DPLL_VCO_ENABLE;
11951}
11952
15bdd4cf
DV		 11953static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
11954 struct intel_shared_dpll *pll)
11955{
3e369b76
ACO		 11956 I915_WRITE(PCH_FP0(pll->id), pll->config.hw_state.fp0);
11957 I915_WRITE(PCH_FP1(pll->id), pll->config.hw_state.fp1);
15bdd4cf
DV		 11958}
11959
e7b903d2
DV		 11960static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
11961 struct intel_shared_dpll *pll)
11962{
e7b903d2 11963 /* PCH refclock must be enabled first */
89eff4be 11964 ibx_assert_pch_refclk_enabled(dev_priv);
e7b903d2 11965
3e369b76 11966 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf
DV		 11967
11968 /* Wait for the clocks to stabilize. */
11969 POSTING_READ(PCH_DPLL(pll->id));
11970 udelay(150);
11971
11972 /* The pixel multiplier can only be updated once the
11973 * DPLL is enabled and the clocks are stable.
11974 *
11975 * So write it again.
11976 */
3e369b76 11977 I915_WRITE(PCH_DPLL(pll->id), pll->config.hw_state.dpll);
15bdd4cf 11978 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 11979 udelay(200);
11980}
11981
11982static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
11983 struct intel_shared_dpll *pll)
11984{
11985 struct drm_device *dev = dev_priv->dev;
11986 struct intel_crtc *crtc;
e7b903d2
DV		 11987
11988 /* Make sure no transcoder isn't still depending on us. */
d3fcc808 11989 for_each_intel_crtc(dev, crtc) {
e7b903d2
DV		 11990 if (intel_crtc_to_shared_dpll(crtc) == pll)
11991 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 11992 }
11993
15bdd4cf
DV		 11994 I915_WRITE(PCH_DPLL(pll->id), 0);
11995 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 11996 udelay(200);
11997}
11998
46edb027
DV		 11999static char *ibx_pch_dpll_names[] = {
12000 "PCH DPLL A",
12001 "PCH DPLL B",
12002};
12003
7c74ade1 12004static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 12005{
e7b903d2 12006 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 12007 int i;
12008
7c74ade1 12009 dev_priv->num_shared_dpll = 2;
ee7b9f93 12010
e72f9fbf 12011 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 12012 dev_priv->shared_dplls[i].id = i;
12013 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 12014 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 12015 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
12016 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 12017 dev_priv->shared_dplls[i].get_hw_state =
12018 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 12019 }
12020}
12021
7c74ade1
DV		 12022static void intel_shared_dpll_init(struct drm_device *dev)
12023{
e7b903d2 12024 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1 12025
9cd86933
DV		 12026 if (HAS_DDI(dev))
12027 intel_ddi_pll_init(dev);
12028 else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
7c74ade1
DV		 12029 ibx_pch_dpll_init(dev);
12030 else
12031 dev_priv->num_shared_dpll = 0;
12032
12033 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
7c74ade1
DV		 12034}
12035
1fc0a8f7
TU		 12036/**
12037 * intel_wm_need_update - Check whether watermarks need updating
12038 * @plane: drm plane
12039 * @state: new plane state
12040 *
12041 * Check current plane state versus the new one to determine whether
12042 * watermarks need to be recalculated.
12043 *
12044 * Returns true or false.
12045 */
12046bool intel_wm_need_update(struct drm_plane *plane,
12047 struct drm_plane_state *state)
12048{
12049 /* Update watermarks on tiling changes. */
12050 if (!plane->state->fb || !state->fb ||
12051 plane->state->fb->modifier[0] != state->fb->modifier[0] ||
12052 plane->state->rotation != state->rotation)
12053 return true;
12054
12055 return false;
12056}
12057
6beb8c23
MR		 12058/**
12059 * intel_prepare_plane_fb - Prepare fb for usage on plane
12060 * @plane: drm plane to prepare for
12061 * @fb: framebuffer to prepare for presentation
12062 *
12063 * Prepares a framebuffer for usage on a display plane. Generally this
12064 * involves pinning the underlying object and updating the frontbuffer tracking
12065 * bits. Some older platforms need special physical address handling for
12066 * cursor planes.
12067 *
12068 * Returns 0 on success, negative error code on failure.
12069 */
12070int
12071intel_prepare_plane_fb(struct drm_plane *plane,
d136dfee
TU		 12072 struct drm_framebuffer *fb,
12073 const struct drm_plane_state *new_state)
465c120c
MR		 12074{
12075 struct drm_device *dev = plane->dev;
6beb8c23
MR		 12076 struct intel_plane *intel_plane = to_intel_plane(plane);
12077 enum pipe pipe = intel_plane->pipe;
12078 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12079 struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb);
12080 unsigned frontbuffer_bits = 0;
12081 int ret = 0;
465c120c 12082
ea2c67bb 12083 if (!obj)
465c120c
MR		 12084 return 0;
12085
6beb8c23
MR		 12086 switch (plane->type) {
12087 case DRM_PLANE_TYPE_PRIMARY:
12088 frontbuffer_bits = INTEL_FRONTBUFFER_PRIMARY(pipe);
12089 break;
12090 case DRM_PLANE_TYPE_CURSOR:
12091 frontbuffer_bits = INTEL_FRONTBUFFER_CURSOR(pipe);
12092 break;
12093 case DRM_PLANE_TYPE_OVERLAY:
12094 frontbuffer_bits = INTEL_FRONTBUFFER_SPRITE(pipe);
12095 break;
12096 }
465c120c 12097
6beb8c23 12098 mutex_lock(&dev->struct_mutex);
465c120c 12099
6beb8c23
MR		 12100 if (plane->type == DRM_PLANE_TYPE_CURSOR &&
12101 INTEL_INFO(dev)->cursor_needs_physical) {
12102 int align = IS_I830(dev) ? 16 * 1024 : 256;
12103 ret = i915_gem_object_attach_phys(obj, align);
12104 if (ret)
12105 DRM_DEBUG_KMS("failed to attach phys object\n");
12106 } else {
82bc3b2d 12107 ret = intel_pin_and_fence_fb_obj(plane, fb, new_state, NULL);
6beb8c23 12108 }
465c120c 12109
6beb8c23
MR		 12110 if (ret == 0)
12111 i915_gem_track_fb(old_obj, obj, frontbuffer_bits);
fdd508a6 12112
4c34574f 12113 mutex_unlock(&dev->struct_mutex);
465c120c 12114
6beb8c23
MR		 12115 return ret;
12116}
12117
38f3ce3a
MR		 12118/**
12119 * intel_cleanup_plane_fb - Cleans up an fb after plane use
12120 * @plane: drm plane to clean up for
12121 * @fb: old framebuffer that was on plane
12122 *
12123 * Cleans up a framebuffer that has just been removed from a plane.
12124 */
12125void
12126intel_cleanup_plane_fb(struct drm_plane *plane,
d136dfee
TU		 12127 struct drm_framebuffer *fb,
12128 const struct drm_plane_state *old_state)
38f3ce3a
MR		 12129{
12130 struct drm_device *dev = plane->dev;
12131 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
12132
12133 if (WARN_ON(!obj))
12134 return;
12135
12136 if (plane->type != DRM_PLANE_TYPE_CURSOR ||
12137 !INTEL_INFO(dev)->cursor_needs_physical) {
12138 mutex_lock(&dev->struct_mutex);
82bc3b2d 12139 intel_unpin_fb_obj(fb, old_state);
38f3ce3a
MR		 12140 mutex_unlock(&dev->struct_mutex);
12141 }
465c120c
MR		 12142}
12143
12144static int
3c692a41
GP		 12145intel_check_primary_plane(struct drm_plane *plane,
12146 struct intel_plane_state *state)
12147{
32b7eeec
MR		 12148 struct drm_device *dev = plane->dev;
12149 struct drm_i915_private *dev_priv = dev->dev_private;
2b875c22 12150 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 12151 struct intel_crtc *intel_crtc;
2b875c22 12152 struct drm_framebuffer *fb = state->base.fb;
3c692a41
GP		 12153 struct drm_rect *dest = &state->dst;
12154 struct drm_rect *src = &state->src;
12155 const struct drm_rect *clip = &state->clip;
465c120c
MR		 12156 int ret;
12157
ea2c67bb
MR		 12158 crtc = crtc ? crtc : plane->crtc;
12159 intel_crtc = to_intel_crtc(crtc);
12160
c59cb179
MR		 12161 ret = drm_plane_helper_check_update(plane, crtc, fb,
12162 src, dest, clip,
12163 DRM_PLANE_HELPER_NO_SCALING,
12164 DRM_PLANE_HELPER_NO_SCALING,
12165 false, true, &state->visible);
12166 if (ret)
12167 return ret;
465c120c 12168
32b7eeec
MR		 12169 if (intel_crtc->active) {
12170 intel_crtc->atomic.wait_for_flips = true;
12171
12172 /*
12173 * FBC does not work on some platforms for rotated
12174 * planes, so disable it when rotation is not 0 and
12175 * update it when rotation is set back to 0.
12176 *
12177 * FIXME: This is redundant with the fbc update done in
12178 * the primary plane enable function except that that
12179 * one is done too late. We eventually need to unify
12180 * this.
12181 */
12182 if (intel_crtc->primary_enabled &&
12183 INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) &&
e35fef21 12184 dev_priv->fbc.crtc == intel_crtc &&
8e7d688b 12185 state->base.rotation != BIT(DRM_ROTATE_0)) {
32b7eeec
MR		 12186 intel_crtc->atomic.disable_fbc = true;
12187 }
12188
12189 if (state->visible) {
12190 /*
12191 * BDW signals flip done immediately if the plane
12192 * is disabled, even if the plane enable is already
12193 * armed to occur at the next vblank :(
12194 */
12195 if (IS_BROADWELL(dev) && !intel_crtc->primary_enabled)
12196 intel_crtc->atomic.wait_vblank = true;
12197 }
12198
12199 intel_crtc->atomic.fb_bits |=
12200 INTEL_FRONTBUFFER_PRIMARY(intel_crtc->pipe);
12201
12202 intel_crtc->atomic.update_fbc = true;
0fda6568 12203
1fc0a8f7 12204 if (intel_wm_need_update(plane, &state->base))
0fda6568 12205 intel_crtc->atomic.update_wm = true;
ccc759dc
GP		 12206 }
12207
14af293f
GP		 12208 return 0;
12209}
12210
12211static void
12212intel_commit_primary_plane(struct drm_plane *plane,
12213 struct intel_plane_state *state)
12214{
2b875c22
MR		 12215 struct drm_crtc *crtc = state->base.crtc;
12216 struct drm_framebuffer *fb = state->base.fb;
12217 struct drm_device *dev = plane->dev;
14af293f 12218 struct drm_i915_private *dev_priv = dev->dev_private;
ea2c67bb 12219 struct intel_crtc *intel_crtc;
14af293f
GP		 12220 struct drm_rect *src = &state->src;
12221
ea2c67bb
MR		 12222 crtc = crtc ? crtc : plane->crtc;
12223 intel_crtc = to_intel_crtc(crtc);
cf4c7c12
MR		 12224
12225 plane->fb = fb;
9dc806fc
MR		 12226 crtc->x = src->x1 >> 16;
12227 crtc->y = src->y1 >> 16;
ccc759dc 12228
ccc759dc 12229 if (intel_crtc->active) {
ccc759dc 12230 if (state->visible) {
ccc759dc
GP		 12231 /* FIXME: kill this fastboot hack */
12232 intel_update_pipe_size(intel_crtc);
465c120c 12233
ccc759dc 12234 intel_crtc->primary_enabled = true;
465c120c 12235
ccc759dc
GP		 12236 dev_priv->display.update_primary_plane(crtc, plane->fb,
12237 crtc->x, crtc->y);
ccc759dc
GP		 12238 } else {
12239 /*
12240 * If clipping results in a non-visible primary plane,
12241 * we'll disable the primary plane. Note that this is
12242 * a bit different than what happens if userspace
12243 * explicitly disables the plane by passing fb=0
12244 * because plane->fb still gets set and pinned.
12245 */
12246 intel_disable_primary_hw_plane(plane, crtc);
48404c1e 12247 }
ccc759dc 12248 }
465c120c
MR		 12249}
12250
32b7eeec 12251static void intel_begin_crtc_commit(struct drm_crtc *crtc)
3c692a41 12252{
32b7eeec 12253 struct drm_device *dev = crtc->dev;
140fd38d 12254 struct drm_i915_private *dev_priv = dev->dev_private;
3c692a41 12255 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ea2c67bb
MR		 12256 struct intel_plane *intel_plane;
12257 struct drm_plane *p;
12258 unsigned fb_bits = 0;
12259
12260 /* Track fb's for any planes being disabled */
12261 list_for_each_entry(p, &dev->mode_config.plane_list, head) {
12262 intel_plane = to_intel_plane(p);
12263
12264 if (intel_crtc->atomic.disabled_planes &
12265 (1 << drm_plane_index(p))) {
12266 switch (p->type) {
12267 case DRM_PLANE_TYPE_PRIMARY:
12268 fb_bits = INTEL_FRONTBUFFER_PRIMARY(intel_plane->pipe);
12269 break;
12270 case DRM_PLANE_TYPE_CURSOR:
12271 fb_bits = INTEL_FRONTBUFFER_CURSOR(intel_plane->pipe);
12272 break;
12273 case DRM_PLANE_TYPE_OVERLAY:
12274 fb_bits = INTEL_FRONTBUFFER_SPRITE(intel_plane->pipe);
12275 break;
12276 }
3c692a41 12277
ea2c67bb
MR		 12278 mutex_lock(&dev->struct_mutex);
12279 i915_gem_track_fb(intel_fb_obj(p->fb), NULL, fb_bits);
12280 mutex_unlock(&dev->struct_mutex);
12281 }
12282 }
3c692a41 12283
32b7eeec
MR		 12284 if (intel_crtc->atomic.wait_for_flips)
12285 intel_crtc_wait_for_pending_flips(crtc);
3c692a41 12286
32b7eeec
MR		 12287 if (intel_crtc->atomic.disable_fbc)
12288 intel_fbc_disable(dev);
3c692a41 12289
32b7eeec
MR		 12290 if (intel_crtc->atomic.pre_disable_primary)
12291 intel_pre_disable_primary(crtc);
3c692a41 12292
32b7eeec
MR		 12293 if (intel_crtc->atomic.update_wm)
12294 intel_update_watermarks(crtc);
3c692a41 12295
32b7eeec 12296 intel_runtime_pm_get(dev_priv);
3c692a41 12297
c34c9ee4
MR		 12298 /* Perform vblank evasion around commit operation */
12299 if (intel_crtc->active)
12300 intel_crtc->atomic.evade =
12301 intel_pipe_update_start(intel_crtc,
12302 &intel_crtc->atomic.start_vbl_count);
32b7eeec
MR		 12303}
12304
12305static void intel_finish_crtc_commit(struct drm_crtc *crtc)
12306{
12307 struct drm_device *dev = crtc->dev;
12308 struct drm_i915_private *dev_priv = dev->dev_private;
12309 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
12310 struct drm_plane *p;
12311
c34c9ee4
MR		 12312 if (intel_crtc->atomic.evade)
12313 intel_pipe_update_end(intel_crtc,
12314 intel_crtc->atomic.start_vbl_count);
3c692a41 12315
140fd38d 12316 intel_runtime_pm_put(dev_priv);
3c692a41 12317
32b7eeec
MR		 12318 if (intel_crtc->atomic.wait_vblank)
12319 intel_wait_for_vblank(dev, intel_crtc->pipe);
12320
12321 intel_frontbuffer_flip(dev, intel_crtc->atomic.fb_bits);
12322
12323 if (intel_crtc->atomic.update_fbc) {
ccc759dc 12324 mutex_lock(&dev->struct_mutex);
7ff0ebcc 12325 intel_fbc_update(dev);
ccc759dc 12326 mutex_unlock(&dev->struct_mutex);
38f3ce3a 12327 }
3c692a41 12328
32b7eeec
MR		 12329 if (intel_crtc->atomic.post_enable_primary)
12330 intel_post_enable_primary(crtc);
3c692a41 12331
32b7eeec
MR		 12332 drm_for_each_legacy_plane(p, &dev->mode_config.plane_list)
12333 if (intel_crtc->atomic.update_sprite_watermarks & drm_plane_index(p))
12334 intel_update_sprite_watermarks(p, crtc, 0, 0, 0,
12335 false, false);
12336
12337 memset(&intel_crtc->atomic, 0, sizeof(intel_crtc->atomic));
3c692a41
GP		 12338}
12339
cf4c7c12 12340/**
4a3b8769
MR		 12341 * intel_plane_destroy - destroy a plane
12342 * @plane: plane to destroy
cf4c7c12 12343 *
4a3b8769
MR		 12344 * Common destruction function for all types of planes (primary, cursor,
12345 * sprite).
cf4c7c12 12346 */
4a3b8769 12347void intel_plane_destroy(struct drm_plane *plane)
465c120c
MR		 12348{
12349 struct intel_plane *intel_plane = to_intel_plane(plane);
12350 drm_plane_cleanup(plane);
12351 kfree(intel_plane);
12352}
12353
65a3fea0 12354const struct drm_plane_funcs intel_plane_funcs = {
ff42e093
DV		 12355 .update_plane = drm_plane_helper_update,
12356 .disable_plane = drm_plane_helper_disable,
3d7d6510 12357 .destroy = intel_plane_destroy,
c196e1d6 12358 .set_property = drm_atomic_helper_plane_set_property,
a98b3431
MR		 12359 .atomic_get_property = intel_plane_atomic_get_property,
12360 .atomic_set_property = intel_plane_atomic_set_property,
ea2c67bb
MR		 12361 .atomic_duplicate_state = intel_plane_duplicate_state,
12362 .atomic_destroy_state = intel_plane_destroy_state,
12363
465c120c
MR		 12364};
12365
12366static struct drm_plane *intel_primary_plane_create(struct drm_device *dev,
12367 int pipe)
12368{
12369 struct intel_plane *primary;
8e7d688b 12370 struct intel_plane_state *state;
465c120c
MR		 12371 const uint32_t *intel_primary_formats;
12372 int num_formats;
12373
12374 primary = kzalloc(sizeof(*primary), GFP_KERNEL);
12375 if (primary == NULL)
12376 return NULL;
12377
8e7d688b
MR		 12378 state = intel_create_plane_state(&primary->base);
12379 if (!state) {
ea2c67bb
MR		 12380 kfree(primary);
12381 return NULL;
12382 }
8e7d688b 12383 primary->base.state = &state->base;
ea2c67bb 12384
465c120c
MR		 12385 primary->can_scale = false;
12386 primary->max_downscale = 1;
12387 primary->pipe = pipe;
12388 primary->plane = pipe;
c59cb179
MR		 12389 primary->check_plane = intel_check_primary_plane;
12390 primary->commit_plane = intel_commit_primary_plane;
465c120c
MR		 12391 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4)
12392 primary->plane = !pipe;
12393
12394 if (INTEL_INFO(dev)->gen <= 3) {
12395 intel_primary_formats = intel_primary_formats_gen2;
12396 num_formats = ARRAY_SIZE(intel_primary_formats_gen2);
12397 } else {
12398 intel_primary_formats = intel_primary_formats_gen4;
12399 num_formats = ARRAY_SIZE(intel_primary_formats_gen4);
12400 }
12401
12402 drm_universal_plane_init(dev, &primary->base, 0,
65a3fea0 12403 &intel_plane_funcs,
465c120c
MR		 12404 intel_primary_formats, num_formats,
12405 DRM_PLANE_TYPE_PRIMARY);
48404c1e
SJ		 12406
12407 if (INTEL_INFO(dev)->gen >= 4) {
12408 if (!dev->mode_config.rotation_property)
12409 dev->mode_config.rotation_property =
12410 drm_mode_create_rotation_property(dev,
12411 BIT(DRM_ROTATE_0) |
12412 BIT(DRM_ROTATE_180));
12413 if (dev->mode_config.rotation_property)
12414 drm_object_attach_property(&primary->base.base,
12415 dev->mode_config.rotation_property,
8e7d688b 12416 state->base.rotation);
48404c1e
SJ		 12417 }
12418
ea2c67bb
MR		 12419 drm_plane_helper_add(&primary->base, &intel_plane_helper_funcs);
12420
465c120c
MR		 12421 return &primary->base;
12422}
12423
3d7d6510 12424static int
852e787c
GP		 12425intel_check_cursor_plane(struct drm_plane *plane,
12426 struct intel_plane_state *state)
3d7d6510 12427{
2b875c22 12428 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb 12429 struct drm_device *dev = plane->dev;
2b875c22 12430 struct drm_framebuffer *fb = state->base.fb;
852e787c
GP		 12431 struct drm_rect *dest = &state->dst;
12432 struct drm_rect *src = &state->src;
12433 const struct drm_rect *clip = &state->clip;
757f9a3e 12434 struct drm_i915_gem_object *obj = intel_fb_obj(fb);
ea2c67bb 12435 struct intel_crtc *intel_crtc;
757f9a3e
GP		 12436 unsigned stride;
12437 int ret;
3d7d6510 12438
ea2c67bb
MR		 12439 crtc = crtc ? crtc : plane->crtc;
12440 intel_crtc = to_intel_crtc(crtc);
12441
757f9a3e 12442 ret = drm_plane_helper_check_update(plane, crtc, fb,
852e787c 12443 src, dest, clip,
3d7d6510
MR		 12444 DRM_PLANE_HELPER_NO_SCALING,
12445 DRM_PLANE_HELPER_NO_SCALING,
852e787c 12446 true, true, &state->visible);
757f9a3e
GP		 12447 if (ret)
12448 return ret;
12449
12450
12451 /* if we want to turn off the cursor ignore width and height */
12452 if (!obj)
32b7eeec 12453 goto finish;
757f9a3e 12454
757f9a3e 12455 /* Check for which cursor types we support */
ea2c67bb
MR		 12456 if (!cursor_size_ok(dev, state->base.crtc_w, state->base.crtc_h)) {
12457 DRM_DEBUG("Cursor dimension %dx%d not supported\n",
12458 state->base.crtc_w, state->base.crtc_h);
757f9a3e
GP		 12459 return -EINVAL;
12460 }
12461
ea2c67bb
MR		 12462 stride = roundup_pow_of_two(state->base.crtc_w) * 4;
12463 if (obj->base.size < stride * state->base.crtc_h) {
757f9a3e
GP		 12464 DRM_DEBUG_KMS("buffer is too small\n");
12465 return -ENOMEM;
12466 }
12467
3a656b54 12468 if (fb->modifier[0] != DRM_FORMAT_MOD_NONE) {
757f9a3e
GP		 12469 DRM_DEBUG_KMS("cursor cannot be tiled\n");
12470 ret = -EINVAL;
12471 }
757f9a3e 12472
32b7eeec
MR		 12473finish:
12474 if (intel_crtc->active) {
3749f463 12475 if (plane->state->crtc_w != state->base.crtc_w)
32b7eeec
MR		 12476 intel_crtc->atomic.update_wm = true;
12477
12478 intel_crtc->atomic.fb_bits |=
12479 INTEL_FRONTBUFFER_CURSOR(intel_crtc->pipe);
12480 }
12481
757f9a3e 12482 return ret;
852e787c 12483}
3d7d6510 12484
f4a2cf29 12485static void
852e787c
GP		 12486intel_commit_cursor_plane(struct drm_plane *plane,
12487 struct intel_plane_state *state)
12488{
2b875c22 12489 struct drm_crtc *crtc = state->base.crtc;
ea2c67bb
MR		 12490 struct drm_device *dev = plane->dev;
12491 struct intel_crtc *intel_crtc;
2b875c22 12492 struct drm_i915_gem_object *obj = intel_fb_obj(state->base.fb);
a912f12f 12493 uint32_t addr;
852e787c 12494
ea2c67bb
MR		 12495 crtc = crtc ? crtc : plane->crtc;
12496 intel_crtc = to_intel_crtc(crtc);
12497
2b875c22 12498 plane->fb = state->base.fb;
ea2c67bb
MR		 12499 crtc->cursor_x = state->base.crtc_x;
12500 crtc->cursor_y = state->base.crtc_y;
12501
a912f12f
GP		 12502 if (intel_crtc->cursor_bo == obj)
12503 goto update;
4ed91096 12504
f4a2cf29 12505 if (!obj)
a912f12f 12506 addr = 0;
f4a2cf29 12507 else if (!INTEL_INFO(dev)->cursor_needs_physical)
a912f12f 12508 addr = i915_gem_obj_ggtt_offset(obj);
f4a2cf29 12509 else
a912f12f 12510 addr = obj->phys_handle->busaddr;
852e787c 12511
a912f12f
GP		 12512 intel_crtc->cursor_addr = addr;
12513 intel_crtc->cursor_bo = obj;
12514update:
852e787c 12515
32b7eeec 12516 if (intel_crtc->active)
a912f12f 12517 intel_crtc_update_cursor(crtc, state->visible);
852e787c
GP		 12518}
12519
3d7d6510
MR		 12520static struct drm_plane *intel_cursor_plane_create(struct drm_device *dev,
12521 int pipe)
12522{
12523 struct intel_plane *cursor;
8e7d688b 12524 struct intel_plane_state *state;
3d7d6510
MR		 12525
12526 cursor = kzalloc(sizeof(*cursor), GFP_KERNEL);
12527 if (cursor == NULL)
12528 return NULL;
12529
8e7d688b
MR		 12530 state = intel_create_plane_state(&cursor->base);
12531 if (!state) {
ea2c67bb
MR		 12532 kfree(cursor);
12533 return NULL;
12534 }
8e7d688b 12535 cursor->base.state = &state->base;
ea2c67bb 12536
3d7d6510
MR		 12537 cursor->can_scale = false;
12538 cursor->max_downscale = 1;
12539 cursor->pipe = pipe;
12540 cursor->plane = pipe;
c59cb179
MR		 12541 cursor->check_plane = intel_check_cursor_plane;
12542 cursor->commit_plane = intel_commit_cursor_plane;
3d7d6510
MR		 12543
12544 drm_universal_plane_init(dev, &cursor->base, 0,
65a3fea0 12545 &intel_plane_funcs,
3d7d6510
MR		 12546 intel_cursor_formats,
12547 ARRAY_SIZE(intel_cursor_formats),
12548 DRM_PLANE_TYPE_CURSOR);
4398ad45
VS		 12549
12550 if (INTEL_INFO(dev)->gen >= 4) {
12551 if (!dev->mode_config.rotation_property)
12552 dev->mode_config.rotation_property =
12553 drm_mode_create_rotation_property(dev,
12554 BIT(DRM_ROTATE_0) |
12555 BIT(DRM_ROTATE_180));
12556 if (dev->mode_config.rotation_property)
12557 drm_object_attach_property(&cursor->base.base,
12558 dev->mode_config.rotation_property,
8e7d688b 12559 state->base.rotation);
4398ad45
VS		 12560 }
12561
ea2c67bb
MR		 12562 drm_plane_helper_add(&cursor->base, &intel_plane_helper_funcs);
12563
3d7d6510
MR		 12564 return &cursor->base;
12565}
12566
b358d0a6 12567static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 12568{
fbee40df 12569 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 12570 struct intel_crtc *intel_crtc;
f5de6e07 12571 struct intel_crtc_state *crtc_state = NULL;
3d7d6510
MR		 12572 struct drm_plane *primary = NULL;
12573 struct drm_plane *cursor = NULL;
465c120c 12574 int i, ret;
79e53945 12575
955382f3 12576 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 12577 if (intel_crtc == NULL)
12578 return;
12579
f5de6e07
ACO		 12580 crtc_state = kzalloc(sizeof(*crtc_state), GFP_KERNEL);
12581 if (!crtc_state)
12582 goto fail;
12583 intel_crtc_set_state(intel_crtc, crtc_state);
07878248 12584 crtc_state->base.crtc = &intel_crtc->base;
f5de6e07 12585
465c120c 12586 primary = intel_primary_plane_create(dev, pipe);
3d7d6510
MR		 12587 if (!primary)
12588 goto fail;
12589
12590 cursor = intel_cursor_plane_create(dev, pipe);
12591 if (!cursor)
12592 goto fail;
12593
465c120c 12594 ret = drm_crtc_init_with_planes(dev, &intel_crtc->base, primary,
3d7d6510
MR		 12595 cursor, &intel_crtc_funcs);
12596 if (ret)
12597 goto fail;
79e53945
JB		 12598
12599 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 12600 for (i = 0; i < 256; i++) {
12601 intel_crtc->lut_r[i] = i;
12602 intel_crtc->lut_g[i] = i;
12603 intel_crtc->lut_b[i] = i;
12604 }
12605
1f1c2e24
VS		 12606 /*
12607 * On gen2/3 only plane A can do fbc, but the panel fitter and lvds port
8c0f92e1 12608 * is hooked to pipe B. Hence we want plane A feeding pipe B.
1f1c2e24 12609 */
80824003
JB		 12610 intel_crtc->pipe = pipe;
12611 intel_crtc->plane = pipe;
3a77c4c4 12612 if (HAS_FBC(dev) && INTEL_INFO(dev)->gen < 4) {
28c97730 12613 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 12614 intel_crtc->plane = !pipe;
80824003
JB		 12615 }
12616
4b0e333e
CW		 12617 intel_crtc->cursor_base = ~0;
12618 intel_crtc->cursor_cntl = ~0;
dc41c154 12619 intel_crtc->cursor_size = ~0;
8d7849db 12620
22fd0fab
JB		 12621 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
12622 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
12623 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
12624 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
12625
9362c7c5
ACO		 12626 INIT_WORK(&intel_crtc->mmio_flip.work, intel_mmio_flip_work_func);
12627
79e53945 12628 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
87b6b101
DV		 12629
12630 WARN_ON(drm_crtc_index(&intel_crtc->base) != intel_crtc->pipe);
3d7d6510
MR		 12631 return;
12632
12633fail:
12634 if (primary)
12635 drm_plane_cleanup(primary);
12636 if (cursor)
12637 drm_plane_cleanup(cursor);
f5de6e07 12638 kfree(crtc_state);
3d7d6510 12639 kfree(intel_crtc);
79e53945
JB		 12640}
12641
752aa88a
JB		 12642enum pipe intel_get_pipe_from_connector(struct intel_connector *connector)
12643{
12644 struct drm_encoder *encoder = connector->base.encoder;
6e9f798d 12645 struct drm_device *dev = connector->base.dev;
752aa88a 12646
51fd371b 12647 WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
752aa88a 12648
d3babd3f 12649 if (!encoder || WARN_ON(!encoder->crtc))
752aa88a
JB		 12650 return INVALID_PIPE;
12651
12652 return to_intel_crtc(encoder->crtc)->pipe;
12653}
12654
08d7b3d1 12655int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 12656 struct drm_file *file)
08d7b3d1 12657{
08d7b3d1 12658 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7707e653 12659 struct drm_crtc *drmmode_crtc;
c05422d5 12660 struct intel_crtc *crtc;
08d7b3d1 12661
7707e653 12662 drmmode_crtc = drm_crtc_find(dev, pipe_from_crtc_id->crtc_id);
08d7b3d1 12663
7707e653 12664 if (!drmmode_crtc) {
08d7b3d1 12665 DRM_ERROR("no such CRTC id\n");
3f2c2057 12666 return -ENOENT;
08d7b3d1
CW		 12667 }
12668
7707e653 12669 crtc = to_intel_crtc(drmmode_crtc);
c05422d5 12670 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 12671
c05422d5 12672 return 0;
08d7b3d1
CW		 12673}
12674
66a9278e 12675static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 12676{
66a9278e
DV		 12677 struct drm_device *dev = encoder->base.dev;
12678 struct intel_encoder *source_encoder;
79e53945 12679 int index_mask = 0;
79e53945
JB		 12680 int entry = 0;
12681
b2784e15 12682 for_each_intel_encoder(dev, source_encoder) {
bc079e8b 12683 if (encoders_cloneable(encoder, source_encoder))
66a9278e
DV		 12684 index_mask |= (1 << entry);
12685
79e53945
JB		 12686 entry++;
12687 }
4ef69c7a 12688
79e53945
JB		 12689 return index_mask;
12690}
12691
4d302442
CW		 12692static bool has_edp_a(struct drm_device *dev)
12693{
12694 struct drm_i915_private *dev_priv = dev->dev_private;
12695
12696 if (!IS_MOBILE(dev))
12697 return false;
12698
12699 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
12700 return false;
12701
e3589908 12702 if (IS_GEN5(dev) && (I915_READ(FUSE_STRAP) & ILK_eDP_A_DISABLE))
4d302442
CW		 12703 return false;
12704
12705 return true;
12706}
12707
84b4e042
JB		 12708static bool intel_crt_present(struct drm_device *dev)
12709{
12710 struct drm_i915_private *dev_priv = dev->dev_private;
12711
884497ed
DL		 12712 if (INTEL_INFO(dev)->gen >= 9)
12713 return false;
12714
cf404ce4 12715 if (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
84b4e042
JB		 12716 return false;
12717
12718 if (IS_CHERRYVIEW(dev))
12719 return false;
12720
12721 if (IS_VALLEYVIEW(dev) && !dev_priv->vbt.int_crt_support)
12722 return false;
12723
12724 return true;
12725}
12726
79e53945
JB		 12727static void intel_setup_outputs(struct drm_device *dev)
12728{
725e30ad 12729 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 12730 struct intel_encoder *encoder;
c6f95f27 12731 struct drm_connector *connector;
cb0953d7 12732 bool dpd_is_edp = false;
79e53945 12733
c9093354 12734 intel_lvds_init(dev);
79e53945 12735
84b4e042 12736 if (intel_crt_present(dev))
79935fca 12737 intel_crt_init(dev);
cb0953d7 12738
affa9354 12739 if (HAS_DDI(dev)) {
0e72a5b5
ED		 12740 int found;
12741
de31facd
JB		 12742 /*
12743 * Haswell uses DDI functions to detect digital outputs.
12744 * On SKL pre-D0 the strap isn't connected, so we assume
12745 * it's there.
12746 */
0e72a5b5 12747 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
de31facd
JB		 12748 /* WaIgnoreDDIAStrap: skl */
12749 if (found ||
12750 (IS_SKYLAKE(dev) && INTEL_REVID(dev) < SKL_REVID_D0))
0e72a5b5
ED		 12751 intel_ddi_init(dev, PORT_A);
12752
12753 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
12754 * register */
12755 found = I915_READ(SFUSE_STRAP);
12756
12757 if (found & SFUSE_STRAP_DDIB_DETECTED)
12758 intel_ddi_init(dev, PORT_B);
12759 if (found & SFUSE_STRAP_DDIC_DETECTED)
12760 intel_ddi_init(dev, PORT_C);
12761 if (found & SFUSE_STRAP_DDID_DETECTED)
12762 intel_ddi_init(dev, PORT_D);
12763 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 12764 int found;
5d8a7752 12765 dpd_is_edp = intel_dp_is_edp(dev, PORT_D);
270b3042
DV		 12766
12767 if (has_edp_a(dev))
12768 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 12769
dc0fa718 12770 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 12771 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 12772 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 12773 if (!found)
e2debe91 12774 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 12775 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 12776 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 12777 }
12778
dc0fa718 12779 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 12780 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 12781
dc0fa718 12782 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 12783 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 12784
5eb08b69 12785 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 12786 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 12787
270b3042 12788 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 12789 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 12790 } else if (IS_VALLEYVIEW(dev)) {
e17ac6db
VS		 12791 /*
12792 * The DP_DETECTED bit is the latched state of the DDC
12793 * SDA pin at boot. However since eDP doesn't require DDC
12794 * (no way to plug in a DP->HDMI dongle) the DDC pins for
12795 * eDP ports may have been muxed to an alternate function.
12796 * Thus we can't rely on the DP_DETECTED bit alone to detect
12797 * eDP ports. Consult the VBT as well as DP_DETECTED to
12798 * detect eDP ports.
12799 */
d2182a66
VS		 12800 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED &&
12801 !intel_dp_is_edp(dev, PORT_B))
585a94b8
AB		 12802 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
12803 PORT_B);
e17ac6db
VS		 12804 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED ||
12805 intel_dp_is_edp(dev, PORT_B))
12806 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
585a94b8 12807
d2182a66
VS		 12808 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED &&
12809 !intel_dp_is_edp(dev, PORT_C))
6f6005a5
JB		 12810 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
12811 PORT_C);
e17ac6db
VS		 12812 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED ||
12813 intel_dp_is_edp(dev, PORT_C))
12814 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 12815
9418c1f1 12816 if (IS_CHERRYVIEW(dev)) {
e17ac6db 12817 if (I915_READ(VLV_DISPLAY_BASE + CHV_HDMID) & SDVO_DETECTED)
9418c1f1
VS		 12818 intel_hdmi_init(dev, VLV_DISPLAY_BASE + CHV_HDMID,
12819 PORT_D);
e17ac6db
VS		 12820 /* eDP not supported on port D, so don't check VBT */
12821 if (I915_READ(VLV_DISPLAY_BASE + DP_D) & DP_DETECTED)
12822 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_D, PORT_D);
9418c1f1
VS		 12823 }
12824
3cfca973 12825 intel_dsi_init(dev);
103a196f 12826 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 12827 bool found = false;
7d57382e 12828
e2debe91 12829 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 12830 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 12831 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 12832 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
12833 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 12834 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 12835 }
27185ae1 12836
e7281eab 12837 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 12838 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 12839 }
13520b05
KH		 12840
12841 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 12842
e2debe91 12843 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 12844 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 12845 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 12846 }
27185ae1 12847
e2debe91 12848 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 12849
b01f2c3a
JB		 12850 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
12851 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 12852 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 12853 }
e7281eab 12854 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 12855 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 12856 }
27185ae1 12857
b01f2c3a 12858 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 12859 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 12860 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 12861 } else if (IS_GEN2(dev))
79e53945
JB		 12862 intel_dvo_init(dev);
12863
103a196f 12864 if (SUPPORTS_TV(dev))
79e53945
JB		 12865 intel_tv_init(dev);
12866
c6f95f27
MR		 12867 /*
12868 * FIXME: We don't have full atomic support yet, but we want to be
12869 * able to enable/test plane updates via the atomic interface in the
12870 * meantime. However as soon as we flip DRIVER_ATOMIC on, the DRM core
12871 * will take some atomic codepaths to lookup properties during
12872 * drmModeGetConnector() that unconditionally dereference
12873 * connector->state.
12874 *
12875 * We create a dummy connector state here for each connector to ensure
12876 * the DRM core doesn't try to dereference a NULL connector->state.
12877 * The actual connector properties will never be updated or contain
12878 * useful information, but since we're doing this specifically for
12879 * testing/debug of the plane operations (and only when a specific
12880 * kernel module option is given), that shouldn't really matter.
12881 *
12882 * Once atomic support for crtc's + connectors lands, this loop should
12883 * be removed since we'll be setting up real connector state, which
12884 * will contain Intel-specific properties.
12885 */
12886 if (drm_core_check_feature(dev, DRIVER_ATOMIC)) {
12887 list_for_each_entry(connector,
12888 &dev->mode_config.connector_list,
12889 head) {
12890 if (!WARN_ON(connector->state)) {
12891 connector->state =
12892 kzalloc(sizeof(*connector->state),
12893 GFP_KERNEL);
12894 }
12895 }
12896 }
12897
0bc12bcb 12898 intel_psr_init(dev);
7c8f8a70 12899
b2784e15 12900 for_each_intel_encoder(dev, encoder) {
4ef69c7a
CW		 12901 encoder->base.possible_crtcs = encoder->crtc_mask;
12902 encoder->base.possible_clones =
66a9278e 12903 intel_encoder_clones(encoder);
79e53945 12904 }
47356eb6 12905
dde86e2d 12906 intel_init_pch_refclk(dev);
270b3042
DV		 12907
12908 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 12909}
12910
12911static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
12912{
60a5ca01 12913 struct drm_device *dev = fb->dev;
79e53945 12914 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 12915
ef2d633e 12916 drm_framebuffer_cleanup(fb);
60a5ca01 12917 mutex_lock(&dev->struct_mutex);
ef2d633e 12918 WARN_ON(!intel_fb->obj->framebuffer_references--);
60a5ca01
VS		 12919 drm_gem_object_unreference(&intel_fb->obj->base);
12920 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 12921 kfree(intel_fb);
12922}
12923
12924static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 12925 struct drm_file *file,
79e53945
JB		 12926 unsigned int *handle)
12927{
12928 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 12929 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 12930
05394f39 12931 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 12932}
12933
12934static const struct drm_framebuffer_funcs intel_fb_funcs = {
12935 .destroy = intel_user_framebuffer_destroy,
12936 .create_handle = intel_user_framebuffer_create_handle,
12937};
12938
b321803d
DL		 12939static
12940u32 intel_fb_pitch_limit(struct drm_device *dev, uint64_t fb_modifier,
12941 uint32_t pixel_format)
12942{
12943 u32 gen = INTEL_INFO(dev)->gen;
12944
12945 if (gen >= 9) {
12946 /* "The stride in bytes must not exceed the of the size of 8K
12947 * pixels and 32K bytes."
12948 */
12949 return min(8192*drm_format_plane_cpp(pixel_format, 0), 32768);
12950 } else if (gen >= 5 && !IS_VALLEYVIEW(dev)) {
12951 return 32*1024;
12952 } else if (gen >= 4) {
12953 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12954 return 16*1024;
12955 else
12956 return 32*1024;
12957 } else if (gen >= 3) {
12958 if (fb_modifier == I915_FORMAT_MOD_X_TILED)
12959 return 8*1024;
12960 else
12961 return 16*1024;
12962 } else {
12963 /* XXX DSPC is limited to 4k tiled */
12964 return 8*1024;
12965 }
12966}
12967
b5ea642a
DV		 12968static int intel_framebuffer_init(struct drm_device *dev,
12969 struct intel_framebuffer *intel_fb,
12970 struct drm_mode_fb_cmd2 *mode_cmd,
12971 struct drm_i915_gem_object *obj)
79e53945 12972{
6761dd31 12973 unsigned int aligned_height;
79e53945 12974 int ret;
b321803d 12975 u32 pitch_limit, stride_alignment;
79e53945 12976
dd4916c5
DV		 12977 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
12978
2a80eada
DV		 12979 if (mode_cmd->flags & DRM_MODE_FB_MODIFIERS) {
12980 /* Enforce that fb modifier and tiling mode match, but only for
12981 * X-tiled. This is needed for FBC. */
12982 if (!!(obj->tiling_mode == I915_TILING_X) !=
12983 !!(mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED)) {
12984 DRM_DEBUG("tiling_mode doesn't match fb modifier\n");
12985 return -EINVAL;
12986 }
12987 } else {
12988 if (obj->tiling_mode == I915_TILING_X)
12989 mode_cmd->modifier[0] = I915_FORMAT_MOD_X_TILED;
12990 else if (obj->tiling_mode == I915_TILING_Y) {
12991 DRM_DEBUG("No Y tiling for legacy addfb\n");
12992 return -EINVAL;
12993 }
12994 }
12995
9a8f0a12
TU		 12996 /* Passed in modifier sanity checking. */
12997 switch (mode_cmd->modifier[0]) {
12998 case I915_FORMAT_MOD_Y_TILED:
12999 case I915_FORMAT_MOD_Yf_TILED:
13000 if (INTEL_INFO(dev)->gen < 9) {
13001 DRM_DEBUG("Unsupported tiling 0x%llx!\n",
13002 mode_cmd->modifier[0]);
13003 return -EINVAL;
13004 }
13005 case DRM_FORMAT_MOD_NONE:
13006 case I915_FORMAT_MOD_X_TILED:
13007 break;
13008 default:
13009 DRM_ERROR("Unsupported fb modifier 0x%llx!\n",
13010 mode_cmd->modifier[0]);
57cd6508 13011 return -EINVAL;
c16ed4be 13012 }
57cd6508 13013
b321803d
DL		 13014 stride_alignment = intel_fb_stride_alignment(dev, mode_cmd->modifier[0],
13015 mode_cmd->pixel_format);
13016 if (mode_cmd->pitches[0] & (stride_alignment - 1)) {
13017 DRM_DEBUG("pitch (%d) must be at least %u byte aligned\n",
13018 mode_cmd->pitches[0], stride_alignment);
57cd6508 13019 return -EINVAL;
c16ed4be 13020 }
57cd6508 13021
b321803d
DL		 13022 pitch_limit = intel_fb_pitch_limit(dev, mode_cmd->modifier[0],
13023 mode_cmd->pixel_format);
a35cdaa0 13024 if (mode_cmd->pitches[0] > pitch_limit) {
b321803d
DL		 13025 DRM_DEBUG("%s pitch (%u) must be at less than %d\n",
13026 mode_cmd->modifier[0] != DRM_FORMAT_MOD_NONE ?
2a80eada 13027 "tiled" : "linear",
a35cdaa0 13028 mode_cmd->pitches[0], pitch_limit);
5d7bd705 13029 return -EINVAL;
c16ed4be 13030 }
5d7bd705 13031
2a80eada 13032 if (mode_cmd->modifier[0] == I915_FORMAT_MOD_X_TILED &&
c16ed4be
CW		 13033 mode_cmd->pitches[0] != obj->stride) {
13034 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
13035 mode_cmd->pitches[0], obj->stride);
5d7bd705 13036 return -EINVAL;
c16ed4be 13037 }
5d7bd705 13038
57779d06 13039 /* Reject formats not supported by any plane early. */
308e5bcb 13040 switch (mode_cmd->pixel_format) {
57779d06 13041 case DRM_FORMAT_C8:
04b3924d
VS		 13042 case DRM_FORMAT_RGB565:
13043 case DRM_FORMAT_XRGB8888:
13044 case DRM_FORMAT_ARGB8888:
57779d06
VS		 13045 break;
13046 case DRM_FORMAT_XRGB1555:
13047 case DRM_FORMAT_ARGB1555:
c16ed4be 13048 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 13049 DRM_DEBUG("unsupported pixel format: %s\n",
13050 drm_get_format_name(mode_cmd->pixel_format));
57779d06 13051 return -EINVAL;
c16ed4be 13052 }
57779d06
VS		 13053 break;
13054 case DRM_FORMAT_XBGR8888:
13055 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 13056 case DRM_FORMAT_XRGB2101010:
13057 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 13058 case DRM_FORMAT_XBGR2101010:
13059 case DRM_FORMAT_ABGR2101010:
c16ed4be 13060 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 13061 DRM_DEBUG("unsupported pixel format: %s\n",
13062 drm_get_format_name(mode_cmd->pixel_format));
57779d06 13063 return -EINVAL;
c16ed4be 13064 }
b5626747 13065 break;
04b3924d
VS		 13066 case DRM_FORMAT_YUYV:
13067 case DRM_FORMAT_UYVY:
13068 case DRM_FORMAT_YVYU:
13069 case DRM_FORMAT_VYUY:
c16ed4be 13070 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 13071 DRM_DEBUG("unsupported pixel format: %s\n",
13072 drm_get_format_name(mode_cmd->pixel_format));
57779d06 13073 return -EINVAL;
c16ed4be 13074 }
57cd6508
CW		 13075 break;
13076 default:
4ee62c76
VS		 13077 DRM_DEBUG("unsupported pixel format: %s\n",
13078 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 13079 return -EINVAL;
13080 }
13081
90f9a336
VS		 13082 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
13083 if (mode_cmd->offsets[0] != 0)
13084 return -EINVAL;
13085
ec2c981e 13086 aligned_height = intel_fb_align_height(dev, mode_cmd->height,
091df6cb
DV		 13087 mode_cmd->pixel_format,
13088 mode_cmd->modifier[0]);
53155c0a
DV		 13089 /* FIXME drm helper for size checks (especially planar formats)? */
13090 if (obj->base.size < aligned_height * mode_cmd->pitches[0])
13091 return -EINVAL;
13092
c7d73f6a
DV		 13093 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
13094 intel_fb->obj = obj;
80075d49 13095 intel_fb->obj->framebuffer_references++;
c7d73f6a 13096
79e53945
JB		 13097 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
13098 if (ret) {
13099 DRM_ERROR("framebuffer init failed %d\n", ret);
13100 return ret;
13101 }
13102
79e53945
JB		 13103 return 0;
13104}
13105
79e53945
JB		 13106static struct drm_framebuffer *
13107intel_user_framebuffer_create(struct drm_device *dev,
13108 struct drm_file *filp,
308e5bcb 13109 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 13110{
05394f39 13111 struct drm_i915_gem_object *obj;
79e53945 13112
308e5bcb
JB		 13113 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
13114 mode_cmd->handles[0]));
c8725226 13115 if (&obj->base == NULL)
cce13ff7 13116 return ERR_PTR(-ENOENT);
79e53945 13117
d2dff872 13118 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 13119}
13120
4520f53a 13121#ifndef CONFIG_DRM_I915_FBDEV
0632fef6 13122static inline void intel_fbdev_output_poll_changed(struct drm_device *dev)
4520f53a
DV		 13123{
13124}
13125#endif
13126
79e53945 13127static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 13128 .fb_create = intel_user_framebuffer_create,
0632fef6 13129 .output_poll_changed = intel_fbdev_output_poll_changed,
5ee67f1c
MR		 13130 .atomic_check = intel_atomic_check,
13131 .atomic_commit = intel_atomic_commit,
79e53945
JB		 13132};
13133
e70236a8
JB		 13134/* Set up chip specific display functions */
13135static void intel_init_display(struct drm_device *dev)
13136{
13137 struct drm_i915_private *dev_priv = dev->dev_private;
13138
ee9300bb
DV		 13139 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
13140 dev_priv->display.find_dpll = g4x_find_best_dpll;
ef9348c8
CML		 13141 else if (IS_CHERRYVIEW(dev))
13142 dev_priv->display.find_dpll = chv_find_best_dpll;
ee9300bb
DV		 13143 else if (IS_VALLEYVIEW(dev))
13144 dev_priv->display.find_dpll = vlv_find_best_dpll;
13145 else if (IS_PINEVIEW(dev))
13146 dev_priv->display.find_dpll = pnv_find_best_dpll;
13147 else
13148 dev_priv->display.find_dpll = i9xx_find_best_dpll;
13149
bc8d7dff
DL		 13150 if (INTEL_INFO(dev)->gen >= 9) {
13151 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 13152 dev_priv->display.get_initial_plane_config =
13153 skylake_get_initial_plane_config;
bc8d7dff
DL		 13154 dev_priv->display.crtc_compute_clock =
13155 haswell_crtc_compute_clock;
13156 dev_priv->display.crtc_enable = haswell_crtc_enable;
13157 dev_priv->display.crtc_disable = haswell_crtc_disable;
13158 dev_priv->display.off = ironlake_crtc_off;
13159 dev_priv->display.update_primary_plane =
13160 skylake_update_primary_plane;
13161 } else if (HAS_DDI(dev)) {
0e8ffe1b 13162 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
5724dbd1
DL		 13163 dev_priv->display.get_initial_plane_config =
13164 ironlake_get_initial_plane_config;
797d0259
ACO		 13165 dev_priv->display.crtc_compute_clock =
13166 haswell_crtc_compute_clock;
4f771f10
PZ		 13167 dev_priv->display.crtc_enable = haswell_crtc_enable;
13168 dev_priv->display.crtc_disable = haswell_crtc_disable;
df8ad70c 13169 dev_priv->display.off = ironlake_crtc_off;
bc8d7dff
DL		 13170 dev_priv->display.update_primary_plane =
13171 ironlake_update_primary_plane;
09b4ddf9 13172 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 13173 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
5724dbd1
DL		 13174 dev_priv->display.get_initial_plane_config =
13175 ironlake_get_initial_plane_config;
3fb37703
ACO		 13176 dev_priv->display.crtc_compute_clock =
13177 ironlake_crtc_compute_clock;
76e5a89c
DV		 13178 dev_priv->display.crtc_enable = ironlake_crtc_enable;
13179 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 13180 dev_priv->display.off = ironlake_crtc_off;
262ca2b0
MR		 13181 dev_priv->display.update_primary_plane =
13182 ironlake_update_primary_plane;
89b667f8
JB		 13183 } else if (IS_VALLEYVIEW(dev)) {
13184 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 13185 dev_priv->display.get_initial_plane_config =
13186 i9xx_get_initial_plane_config;
d6dfee7a 13187 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
89b667f8
JB		 13188 dev_priv->display.crtc_enable = valleyview_crtc_enable;
13189 dev_priv->display.crtc_disable = i9xx_crtc_disable;
13190 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 13191 dev_priv->display.update_primary_plane =
13192 i9xx_update_primary_plane;
f564048e 13193 } else {
0e8ffe1b 13194 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
5724dbd1
DL		 13195 dev_priv->display.get_initial_plane_config =
13196 i9xx_get_initial_plane_config;
d6dfee7a 13197 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock;
76e5a89c
DV		 13198 dev_priv->display.crtc_enable = i9xx_crtc_enable;
13199 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 13200 dev_priv->display.off = i9xx_crtc_off;
262ca2b0
MR		 13201 dev_priv->display.update_primary_plane =
13202 i9xx_update_primary_plane;
f564048e 13203 }
e70236a8 13204
e70236a8 13205 /* Returns the core display clock speed */
25eb05fc
JB		 13206 if (IS_VALLEYVIEW(dev))
13207 dev_priv->display.get_display_clock_speed =
13208 valleyview_get_display_clock_speed;
13209 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 13210 dev_priv->display.get_display_clock_speed =
13211 i945_get_display_clock_speed;
13212 else if (IS_I915G(dev))
13213 dev_priv->display.get_display_clock_speed =
13214 i915_get_display_clock_speed;
257a7ffc 13215 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 13216 dev_priv->display.get_display_clock_speed =
13217 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 13218 else if (IS_PINEVIEW(dev))
13219 dev_priv->display.get_display_clock_speed =
13220 pnv_get_display_clock_speed;
e70236a8
JB		 13221 else if (IS_I915GM(dev))
13222 dev_priv->display.get_display_clock_speed =
13223 i915gm_get_display_clock_speed;
13224 else if (IS_I865G(dev))
13225 dev_priv->display.get_display_clock_speed =
13226 i865_get_display_clock_speed;
f0f8a9ce 13227 else if (IS_I85X(dev))
e70236a8
JB		 13228 dev_priv->display.get_display_clock_speed =
13229 i855_get_display_clock_speed;
13230 else /* 852, 830 */
13231 dev_priv->display.get_display_clock_speed =
13232 i830_get_display_clock_speed;
13233
7c10a2b5 13234 if (IS_GEN5(dev)) {
3bb11b53 13235 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
3bb11b53
SJ		 13236 } else if (IS_GEN6(dev)) {
13237 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
3bb11b53
SJ		 13238 } else if (IS_IVYBRIDGE(dev)) {
13239 /* FIXME: detect B0+ stepping and use auto training */
13240 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
059b2fe9 13241 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3bb11b53 13242 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
30a970c6
JB		 13243 } else if (IS_VALLEYVIEW(dev)) {
13244 dev_priv->display.modeset_global_resources =
13245 valleyview_modeset_global_resources;
e70236a8 13246 }
8c9f3aaf 13247
8c9f3aaf
JB		 13248 switch (INTEL_INFO(dev)->gen) {
13249 case 2:
13250 dev_priv->display.queue_flip = intel_gen2_queue_flip;
13251 break;
13252
13253 case 3:
13254 dev_priv->display.queue_flip = intel_gen3_queue_flip;
13255 break;
13256
13257 case 4:
13258 case 5:
13259 dev_priv->display.queue_flip = intel_gen4_queue_flip;
13260 break;
13261
13262 case 6:
13263 dev_priv->display.queue_flip = intel_gen6_queue_flip;
13264 break;
7c9017e5 13265 case 7:
4e0bbc31 13266 case 8: /* FIXME(BDW): Check that the gen8 RCS flip works. */
7c9017e5
JB		 13267 dev_priv->display.queue_flip = intel_gen7_queue_flip;
13268 break;
830c81db 13269 case 9:
ba343e02
TU		 13270 /* Drop through - unsupported since execlist only. */
13271 default:
13272 /* Default just returns -ENODEV to indicate unsupported */
13273 dev_priv->display.queue_flip = intel_default_queue_flip;
8c9f3aaf 13274 }
7bd688cd
JN		 13275
13276 intel_panel_init_backlight_funcs(dev);
e39b999a
VS		 13277
13278 mutex_init(&dev_priv->pps_mutex);
e70236a8
JB		 13279}
13280
b690e96c
JB		 13281/*
13282 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
13283 * resume, or other times. This quirk makes sure that's the case for
13284 * affected systems.
13285 */
0206e353 13286static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 13287{
13288 struct drm_i915_private *dev_priv = dev->dev_private;
13289
13290 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 13291 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 13292}
13293
b6b5d049
VS		 13294static void quirk_pipeb_force(struct drm_device *dev)
13295{
13296 struct drm_i915_private *dev_priv = dev->dev_private;
13297
13298 dev_priv->quirks |= QUIRK_PIPEB_FORCE;
13299 DRM_INFO("applying pipe b force quirk\n");
13300}
13301
435793df
KP		 13302/*
13303 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
13304 */
13305static void quirk_ssc_force_disable(struct drm_device *dev)
13306{
13307 struct drm_i915_private *dev_priv = dev->dev_private;
13308 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 13309 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 13310}
13311
4dca20ef 13312/*
5a15ab5b
CE		 13313 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
13314 * brightness value
4dca20ef
CE		 13315 */
13316static void quirk_invert_brightness(struct drm_device *dev)
13317{
13318 struct drm_i915_private *dev_priv = dev->dev_private;
13319 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 13320 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 13321}
13322
9c72cc6f
SD		 13323/* Some VBT's incorrectly indicate no backlight is present */
13324static void quirk_backlight_present(struct drm_device *dev)
13325{
13326 struct drm_i915_private *dev_priv = dev->dev_private;
13327 dev_priv->quirks |= QUIRK_BACKLIGHT_PRESENT;
13328 DRM_INFO("applying backlight present quirk\n");
13329}
13330
b690e96c
JB		 13331struct intel_quirk {
13332 int device;
13333 int subsystem_vendor;
13334 int subsystem_device;
13335 void (*hook)(struct drm_device *dev);
13336};
13337
5f85f176
EE		 13338/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
13339struct intel_dmi_quirk {
13340 void (*hook)(struct drm_device *dev);
13341 const struct dmi_system_id (*dmi_id_list)[];
13342};
13343
13344static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
13345{
13346 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
13347 return 1;
13348}
13349
13350static const struct intel_dmi_quirk intel_dmi_quirks[] = {
13351 {
13352 .dmi_id_list = &(const struct dmi_system_id[]) {
13353 {
13354 .callback = intel_dmi_reverse_brightness,
13355 .ident = "NCR Corporation",
13356 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
13357 DMI_MATCH(DMI_PRODUCT_NAME, ""),
13358 },
13359 },
13360 { } /* terminating entry */
13361 },
13362 .hook = quirk_invert_brightness,
13363 },
13364};
13365
c43b5634 13366static struct intel_quirk intel_quirks[] = {
b690e96c 13367 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 13368 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 13369
b690e96c
JB		 13370 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
13371 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
13372
b690e96c
JB		 13373 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
13374 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
13375
5f080c0f
VS		 13376 /* 830 needs to leave pipe A & dpll A up */
13377 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
13378
b6b5d049
VS		 13379 /* 830 needs to leave pipe B & dpll B up */
13380 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipeb_force },
13381
435793df
KP		 13382 /* Lenovo U160 cannot use SSC on LVDS */
13383 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 13384
13385 /* Sony Vaio Y cannot use SSC on LVDS */
13386 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 13387
be505f64
AH		 13388 /* Acer Aspire 5734Z must invert backlight brightness */
13389 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
13390
13391 /* Acer/eMachines G725 */
13392 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
13393
13394 /* Acer/eMachines e725 */
13395 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
13396
13397 /* Acer/Packard Bell NCL20 */
13398 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
13399
13400 /* Acer Aspire 4736Z */
13401 { 0x2a42, 0x1025, 0x0260, quirk_invert_brightness },
0f540c3a
JN		 13402
13403 /* Acer Aspire 5336 */
13404 { 0x2a42, 0x1025, 0x048a, quirk_invert_brightness },
2e93a1aa
SD		 13405
13406 /* Acer C720 and C720P Chromebooks (Celeron 2955U) have backlights */
13407 { 0x0a06, 0x1025, 0x0a11, quirk_backlight_present },
d4967d8c 13408
dfb3d47b
SD		 13409 /* Acer C720 Chromebook (Core i3 4005U) */
13410 { 0x0a16, 0x1025, 0x0a11, quirk_backlight_present },
13411
b2a9601c 13412 /* Apple Macbook 2,1 (Core 2 T7400) */
13413 { 0x27a2, 0x8086, 0x7270, quirk_backlight_present },
13414
d4967d8c
SD		 13415 /* Toshiba CB35 Chromebook (Celeron 2955U) */
13416 { 0x0a06, 0x1179, 0x0a88, quirk_backlight_present },
724cb06f
SD		 13417
13418 /* HP Chromebook 14 (Celeron 2955U) */
13419 { 0x0a06, 0x103c, 0x21ed, quirk_backlight_present },
cf6f0af9
JN		 13420
13421 /* Dell Chromebook 11 */
13422 { 0x0a06, 0x1028, 0x0a35, quirk_backlight_present },
b690e96c
JB		 13423};
13424
13425static void intel_init_quirks(struct drm_device *dev)
13426{
13427 struct pci_dev *d = dev->pdev;
13428 int i;
13429
13430 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
13431 struct intel_quirk *q = &intel_quirks[i];
13432
13433 if (d->device == q->device &&
13434 (d->subsystem_vendor == q->subsystem_vendor ||
13435 q->subsystem_vendor == PCI_ANY_ID) &&
13436 (d->subsystem_device == q->subsystem_device ||
13437 q->subsystem_device == PCI_ANY_ID))
13438 q->hook(dev);
13439 }
5f85f176
EE		 13440 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
13441 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
13442 intel_dmi_quirks[i].hook(dev);
13443 }
b690e96c
JB		 13444}
13445
9cce37f4
JB		 13446/* Disable the VGA plane that we never use */
13447static void i915_disable_vga(struct drm_device *dev)
13448{
13449 struct drm_i915_private *dev_priv = dev->dev_private;
13450 u8 sr1;
766aa1c4 13451 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4 13452
2b37c616 13453 /* WaEnableVGAAccessThroughIOPort:ctg,elk,ilk,snb,ivb,vlv,hsw */
9cce37f4 13454 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 13455 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 13456 sr1 = inb(VGA_SR_DATA);
13457 outb(sr1 | 1<<5, VGA_SR_DATA);
13458 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
13459 udelay(300);
13460
01f5a626 13461 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
9cce37f4
JB		 13462 POSTING_READ(vga_reg);
13463}
13464
f817586c
DV		 13465void intel_modeset_init_hw(struct drm_device *dev)
13466{
a8f78b58
ED		 13467 intel_prepare_ddi(dev);
13468
f8bf63fd
VS		 13469 if (IS_VALLEYVIEW(dev))
13470 vlv_update_cdclk(dev);
13471
f817586c
DV		 13472 intel_init_clock_gating(dev);
13473
8090c6b9 13474 intel_enable_gt_powersave(dev);
f817586c
DV		 13475}
13476
79e53945
JB		 13477void intel_modeset_init(struct drm_device *dev)
13478{
652c393a 13479 struct drm_i915_private *dev_priv = dev->dev_private;
1fe47785 13480 int sprite, ret;
8cc87b75 13481 enum pipe pipe;
46f297fb 13482 struct intel_crtc *crtc;
79e53945
JB		 13483
13484 drm_mode_config_init(dev);
13485
13486 dev->mode_config.min_width = 0;
13487 dev->mode_config.min_height = 0;
13488
019d96cb
DA		 13489 dev->mode_config.preferred_depth = 24;
13490 dev->mode_config.prefer_shadow = 1;
13491
25bab385
TU		 13492 dev->mode_config.allow_fb_modifiers = true;
13493
e6ecefaa 13494 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 13495
b690e96c
JB		 13496 intel_init_quirks(dev);
13497
1fa61106
ED		 13498 intel_init_pm(dev);
13499
e3c74757
BW		 13500 if (INTEL_INFO(dev)->num_pipes == 0)
13501 return;
13502
e70236a8 13503 intel_init_display(dev);
7c10a2b5 13504 intel_init_audio(dev);
e70236a8 13505
a6c45cf0
CW		 13506 if (IS_GEN2(dev)) {
13507 dev->mode_config.max_width = 2048;
13508 dev->mode_config.max_height = 2048;
13509 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 13510 dev->mode_config.max_width = 4096;
13511 dev->mode_config.max_height = 4096;
79e53945 13512 } else {
a6c45cf0
CW		 13513 dev->mode_config.max_width = 8192;
13514 dev->mode_config.max_height = 8192;
79e53945 13515 }
068be561 13516
dc41c154
VS		 13517 if (IS_845G(dev) || IS_I865G(dev)) {
13518 dev->mode_config.cursor_width = IS_845G(dev) ? 64 : 512;
13519 dev->mode_config.cursor_height = 1023;
13520 } else if (IS_GEN2(dev)) {
068be561
DL		 13521 dev->mode_config.cursor_width = GEN2_CURSOR_WIDTH;
13522 dev->mode_config.cursor_height = GEN2_CURSOR_HEIGHT;
13523 } else {
13524 dev->mode_config.cursor_width = MAX_CURSOR_WIDTH;
13525 dev->mode_config.cursor_height = MAX_CURSOR_HEIGHT;
13526 }
13527
5d4545ae 13528 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 13529
28c97730 13530 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 13531 INTEL_INFO(dev)->num_pipes,
13532 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 13533
055e393f 13534 for_each_pipe(dev_priv, pipe) {
8cc87b75 13535 intel_crtc_init(dev, pipe);
3bdcfc0c 13536 for_each_sprite(dev_priv, pipe, sprite) {
1fe47785 13537 ret = intel_plane_init(dev, pipe, sprite);
7f1f3851 13538 if (ret)
06da8da2 13539 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
1fe47785 13540 pipe_name(pipe), sprite_name(pipe, sprite), ret);
7f1f3851 13541 }
79e53945
JB		 13542 }
13543
f42bb70d
JB		 13544 intel_init_dpio(dev);
13545
e72f9fbf 13546 intel_shared_dpll_init(dev);
ee7b9f93 13547
9cce37f4
JB		 13548 /* Just disable it once at startup */
13549 i915_disable_vga(dev);
79e53945 13550 intel_setup_outputs(dev);
11be49eb
CW		 13551
13552 /* Just in case the BIOS is doing something questionable. */
7ff0ebcc 13553 intel_fbc_disable(dev);
fa9fa083 13554
6e9f798d 13555 drm_modeset_lock_all(dev);
fa9fa083 13556 intel_modeset_setup_hw_state(dev, false);
6e9f798d 13557 drm_modeset_unlock_all(dev);
46f297fb 13558
d3fcc808 13559 for_each_intel_crtc(dev, crtc) {
46f297fb
JB		 13560 if (!crtc->active)
13561 continue;
13562
46f297fb 13563 /*
46f297fb
JB		 13564 * Note that reserving the BIOS fb up front prevents us
13565 * from stuffing other stolen allocations like the ring
13566 * on top. This prevents some ugliness at boot time, and
13567 * can even allow for smooth boot transitions if the BIOS
13568 * fb is large enough for the active pipe configuration.
13569 */
5724dbd1
DL		 13570 if (dev_priv->display.get_initial_plane_config) {
13571 dev_priv->display.get_initial_plane_config(crtc,
46f297fb
JB		 13572 &crtc->plane_config);
13573 /*
13574 * If the fb is shared between multiple heads, we'll
13575 * just get the first one.
13576 */
484b41dd 13577 intel_find_plane_obj(crtc, &crtc->plane_config);
46f297fb 13578 }
46f297fb 13579 }
2c7111db
CW		 13580}
13581
7fad798e
DV		 13582static void intel_enable_pipe_a(struct drm_device *dev)
13583{
13584 struct intel_connector *connector;
13585 struct drm_connector *crt = NULL;
13586 struct intel_load_detect_pipe load_detect_temp;
208bf9fd 13587 struct drm_modeset_acquire_ctx *ctx = dev->mode_config.acquire_ctx;
7fad798e
DV		 13588
13589 /* We can't just switch on the pipe A, we need to set things up with a
13590 * proper mode and output configuration. As a gross hack, enable pipe A
13591 * by enabling the load detect pipe once. */
3a3371ff 13592 for_each_intel_connector(dev, connector) {
7fad798e
DV		 13593 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
13594 crt = &connector->base;
13595 break;
13596 }
13597 }
13598
13599 if (!crt)
13600 return;
13601
208bf9fd
VS		 13602 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp, ctx))
13603 intel_release_load_detect_pipe(crt, &load_detect_temp);
7fad798e
DV		 13604}
13605
fa555837
DV		 13606static bool
13607intel_check_plane_mapping(struct intel_crtc *crtc)
13608{
7eb552ae
BW		 13609 struct drm_device *dev = crtc->base.dev;
13610 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 13611 u32 reg, val;
13612
7eb552ae 13613 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 13614 return true;
13615
13616 reg = DSPCNTR(!crtc->plane);
13617 val = I915_READ(reg);
13618
13619 if ((val & DISPLAY_PLANE_ENABLE) &&
13620 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
13621 return false;
13622
13623 return true;
13624}
13625
24929352
DV		 13626static void intel_sanitize_crtc(struct intel_crtc *crtc)
13627{
13628 struct drm_device *dev = crtc->base.dev;
13629 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 13630 u32 reg;
24929352 13631
24929352 13632 /* Clear any frame start delays used for debugging left by the BIOS */
6e3c9717 13633 reg = PIPECONF(crtc->config->cpu_transcoder);
24929352
DV		 13634 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
13635
d3eaf884 13636 /* restore vblank interrupts to correct state */
9625604c 13637 drm_crtc_vblank_reset(&crtc->base);
d297e103
VS		 13638 if (crtc->active) {
13639 update_scanline_offset(crtc);
9625604c
DV		 13640 drm_crtc_vblank_on(&crtc->base);
13641 }
d3eaf884 13642
24929352 13643 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 13644 * disable the crtc (and hence change the state) if it is wrong. Note
13645 * that gen4+ has a fixed plane -> pipe mapping. */
13646 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 13647 struct intel_connector *connector;
13648 bool plane;
13649
24929352
DV		 13650 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
13651 crtc->base.base.id);
13652
13653 /* Pipe has the wrong plane attached and the plane is active.
13654 * Temporarily change the plane mapping and disable everything
13655 * ... */
13656 plane = crtc->plane;
13657 crtc->plane = !plane;
9c8958bc 13658 crtc->primary_enabled = true;
24929352
DV		 13659 dev_priv->display.crtc_disable(&crtc->base);
13660 crtc->plane = plane;
13661
13662 /* ... and break all links. */
3a3371ff 13663 for_each_intel_connector(dev, connector) {
24929352
DV		 13664 if (connector->encoder->base.crtc != &crtc->base)
13665 continue;
13666
7f1950fb
EE		 13667 connector->base.dpms = DRM_MODE_DPMS_OFF;
13668 connector->base.encoder = NULL;
24929352 13669 }
7f1950fb
EE		 13670 /* multiple connectors may have the same encoder:
13671 * handle them and break crtc link separately */
3a3371ff 13672 for_each_intel_connector(dev, connector)
7f1950fb
EE		 13673 if (connector->encoder->base.crtc == &crtc->base) {
13674 connector->encoder->base.crtc = NULL;
13675 connector->encoder->connectors_active = false;
13676 }
24929352
DV		 13677
13678 WARN_ON(crtc->active);
83d65738 13679 crtc->base.state->enable = false;
24929352
DV		 13680 crtc->base.enabled = false;
13681 }
24929352 13682
7fad798e
DV		 13683 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
13684 crtc->pipe == PIPE_A && !crtc->active) {
13685 /* BIOS forgot to enable pipe A, this mostly happens after
13686 * resume. Force-enable the pipe to fix this, the update_dpms
13687 * call below we restore the pipe to the right state, but leave
13688 * the required bits on. */
13689 intel_enable_pipe_a(dev);
13690 }
13691
24929352
DV		 13692 /* Adjust the state of the output pipe according to whether we
13693 * have active connectors/encoders. */
13694 intel_crtc_update_dpms(&crtc->base);
13695
83d65738 13696 if (crtc->active != crtc->base.state->enable) {
24929352
DV		 13697 struct intel_encoder *encoder;
13698
13699 /* This can happen either due to bugs in the get_hw_state
13700 * functions or because the pipe is force-enabled due to the
13701 * pipe A quirk. */
13702 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
13703 crtc->base.base.id,
83d65738 13704 crtc->base.state->enable ? "enabled" : "disabled",
24929352
DV		 13705 crtc->active ? "enabled" : "disabled");
13706
83d65738 13707 crtc->base.state->enable = crtc->active;
24929352
DV		 13708 crtc->base.enabled = crtc->active;
13709
13710 /* Because we only establish the connector -> encoder ->
13711 * crtc links if something is active, this means the
13712 * crtc is now deactivated. Break the links. connector
13713 * -> encoder links are only establish when things are
13714 * actually up, hence no need to break them. */
13715 WARN_ON(crtc->active);
13716
13717 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
13718 WARN_ON(encoder->connectors_active);
13719 encoder->base.crtc = NULL;
13720 }
13721 }
c5ab3bc0 13722
a3ed6aad 13723 if (crtc->active || HAS_GMCH_DISPLAY(dev)) {
4cc31489
DV		 13724 /*
13725 * We start out with underrun reporting disabled to avoid races.
13726 * For correct bookkeeping mark this on active crtcs.
13727 *
c5ab3bc0
DV		 13728 * Also on gmch platforms we dont have any hardware bits to
13729 * disable the underrun reporting. Which means we need to start
13730 * out with underrun reporting disabled also on inactive pipes,
13731 * since otherwise we'll complain about the garbage we read when
13732 * e.g. coming up after runtime pm.
13733 *
4cc31489
DV		 13734 * No protection against concurrent access is required - at
13735 * worst a fifo underrun happens which also sets this to false.
13736 */
13737 crtc->cpu_fifo_underrun_disabled = true;
13738 crtc->pch_fifo_underrun_disabled = true;
13739 }
24929352
DV		 13740}
13741
13742static void intel_sanitize_encoder(struct intel_encoder *encoder)
13743{
13744 struct intel_connector *connector;
13745 struct drm_device *dev = encoder->base.dev;
13746
13747 /* We need to check both for a crtc link (meaning that the
13748 * encoder is active and trying to read from a pipe) and the
13749 * pipe itself being active. */
13750 bool has_active_crtc = encoder->base.crtc &&
13751 to_intel_crtc(encoder->base.crtc)->active;
13752
13753 if (encoder->connectors_active && !has_active_crtc) {
13754 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
13755 encoder->base.base.id,
8e329a03 13756 encoder->base.name);
24929352
DV		 13757
13758 /* Connector is active, but has no active pipe. This is
13759 * fallout from our resume register restoring. Disable
13760 * the encoder manually again. */
13761 if (encoder->base.crtc) {
13762 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
13763 encoder->base.base.id,
8e329a03 13764 encoder->base.name);
24929352 13765 encoder->disable(encoder);
a62d1497
VS		 13766 if (encoder->post_disable)
13767 encoder->post_disable(encoder);
24929352 13768 }
7f1950fb
EE		 13769 encoder->base.crtc = NULL;
13770 encoder->connectors_active = false;
24929352
DV		 13771
13772 /* Inconsistent output/port/pipe state happens presumably due to
13773 * a bug in one of the get_hw_state functions. Or someplace else
13774 * in our code, like the register restore mess on resume. Clamp
13775 * things to off as a safer default. */
3a3371ff 13776 for_each_intel_connector(dev, connector) {
24929352
DV		 13777 if (connector->encoder != encoder)
13778 continue;
7f1950fb
EE		 13779 connector->base.dpms = DRM_MODE_DPMS_OFF;
13780 connector->base.encoder = NULL;
24929352
DV		 13781 }
13782 }
13783 /* Enabled encoders without active connectors will be fixed in
13784 * the crtc fixup. */
13785}
13786
04098753 13787void i915_redisable_vga_power_on(struct drm_device *dev)
0fde901f
KM		 13788{
13789 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 13790 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 13791
04098753
ID		 13792 if (!(I915_READ(vga_reg) & VGA_DISP_DISABLE)) {
13793 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
13794 i915_disable_vga(dev);
13795 }
13796}
13797
13798void i915_redisable_vga(struct drm_device *dev)
13799{
13800 struct drm_i915_private *dev_priv = dev->dev_private;
13801
8dc8a27c
PZ		 13802 /* This function can be called both from intel_modeset_setup_hw_state or
13803 * at a very early point in our resume sequence, where the power well
13804 * structures are not yet restored. Since this function is at a very
13805 * paranoid "someone might have enabled VGA while we were not looking"
13806 * level, just check if the power well is enabled instead of trying to
13807 * follow the "don't touch the power well if we don't need it" policy
13808 * the rest of the driver uses. */
f458ebbc 13809 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_VGA))
8dc8a27c
PZ		 13810 return;
13811
04098753 13812 i915_redisable_vga_power_on(dev);
0fde901f
KM		 13813}
13814
98ec7739
VS		 13815static bool primary_get_hw_state(struct intel_crtc *crtc)
13816{
13817 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
13818
13819 if (!crtc->active)
13820 return false;
13821
13822 return I915_READ(DSPCNTR(crtc->plane)) & DISPLAY_PLANE_ENABLE;
13823}
13824
30e984df 13825static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 13826{
13827 struct drm_i915_private *dev_priv = dev->dev_private;
13828 enum pipe pipe;
24929352
DV		 13829 struct intel_crtc *crtc;
13830 struct intel_encoder *encoder;
13831 struct intel_connector *connector;
5358901f 13832 int i;
24929352 13833
d3fcc808 13834 for_each_intel_crtc(dev, crtc) {
6e3c9717 13835 memset(crtc->config, 0, sizeof(*crtc->config));
3b117c8f 13836
6e3c9717 13837 crtc->config->quirks |= PIPE_CONFIG_QUIRK_INHERITED_MODE;
9953599b 13838
0e8ffe1b 13839 crtc->active = dev_priv->display.get_pipe_config(crtc,
6e3c9717 13840 crtc->config);
24929352 13841
83d65738 13842 crtc->base.state->enable = crtc->active;
24929352 13843 crtc->base.enabled = crtc->active;
98ec7739 13844 crtc->primary_enabled = primary_get_hw_state(crtc);
24929352
DV		 13845
13846 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
13847 crtc->base.base.id,
13848 crtc->active ? "enabled" : "disabled");
13849 }
13850
5358901f
DV		 13851 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13852 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13853
3e369b76
ACO		 13854 pll->on = pll->get_hw_state(dev_priv, pll,
13855 &pll->config.hw_state);
5358901f 13856 pll->active = 0;
3e369b76 13857 pll->config.crtc_mask = 0;
d3fcc808 13858 for_each_intel_crtc(dev, crtc) {
1e6f2ddc 13859 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll) {
5358901f 13860 pll->active++;
3e369b76 13861 pll->config.crtc_mask |= 1 << crtc->pipe;
1e6f2ddc 13862 }
5358901f 13863 }
5358901f 13864
1e6f2ddc 13865 DRM_DEBUG_KMS("%s hw state readout: crtc_mask 0x%08x, on %i\n",
3e369b76 13866 pll->name, pll->config.crtc_mask, pll->on);
bd2bb1b9 13867
3e369b76 13868 if (pll->config.crtc_mask)
bd2bb1b9 13869 intel_display_power_get(dev_priv, POWER_DOMAIN_PLLS);
5358901f
DV		 13870 }
13871
b2784e15 13872 for_each_intel_encoder(dev, encoder) {
24929352
DV		 13873 pipe = 0;
13874
13875 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 13876 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13877 encoder->base.crtc = &crtc->base;
6e3c9717 13878 encoder->get_config(encoder, crtc->config);
24929352
DV		 13879 } else {
13880 encoder->base.crtc = NULL;
13881 }
13882
13883 encoder->connectors_active = false;
6f2bcceb 13884 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
24929352 13885 encoder->base.base.id,
8e329a03 13886 encoder->base.name,
24929352 13887 encoder->base.crtc ? "enabled" : "disabled",
6f2bcceb 13888 pipe_name(pipe));
24929352
DV		 13889 }
13890
3a3371ff 13891 for_each_intel_connector(dev, connector) {
24929352
DV		 13892 if (connector->get_hw_state(connector)) {
13893 connector->base.dpms = DRM_MODE_DPMS_ON;
13894 connector->encoder->connectors_active = true;
13895 connector->base.encoder = &connector->encoder->base;
13896 } else {
13897 connector->base.dpms = DRM_MODE_DPMS_OFF;
13898 connector->base.encoder = NULL;
13899 }
13900 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
13901 connector->base.base.id,
c23cc417 13902 connector->base.name,
24929352
DV		 13903 connector->base.encoder ? "enabled" : "disabled");
13904 }
30e984df
DV		 13905}
13906
13907/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
13908 * and i915 state tracking structures. */
13909void intel_modeset_setup_hw_state(struct drm_device *dev,
13910 bool force_restore)
13911{
13912 struct drm_i915_private *dev_priv = dev->dev_private;
13913 enum pipe pipe;
30e984df
DV		 13914 struct intel_crtc *crtc;
13915 struct intel_encoder *encoder;
35c95375 13916 int i;
30e984df
DV		 13917
13918 intel_modeset_readout_hw_state(dev);
24929352 13919
babea61d
JB		 13920 /*
13921 * Now that we have the config, copy it to each CRTC struct
13922 * Note that this could go away if we move to using crtc_config
13923 * checking everywhere.
13924 */
d3fcc808 13925 for_each_intel_crtc(dev, crtc) {
d330a953 13926 if (crtc->active && i915.fastboot) {
6e3c9717
ACO		 13927 intel_mode_from_pipe_config(&crtc->base.mode,
13928 crtc->config);
babea61d
JB		 13929 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
13930 crtc->base.base.id);
13931 drm_mode_debug_printmodeline(&crtc->base.mode);
13932 }
13933 }
13934
24929352 13935 /* HW state is read out, now we need to sanitize this mess. */
b2784e15 13936 for_each_intel_encoder(dev, encoder) {
24929352
DV		 13937 intel_sanitize_encoder(encoder);
13938 }
13939
055e393f 13940 for_each_pipe(dev_priv, pipe) {
24929352
DV		 13941 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
13942 intel_sanitize_crtc(crtc);
6e3c9717
ACO		 13943 intel_dump_pipe_config(crtc, crtc->config,
13944 "[setup_hw_state]");
24929352 13945 }
9a935856 13946
35c95375
DV		 13947 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
13948 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
13949
13950 if (!pll->on || pll->active)
13951 continue;
13952
13953 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
13954
13955 pll->disable(dev_priv, pll);
13956 pll->on = false;
13957 }
13958
3078999f
PB		 13959 if (IS_GEN9(dev))
13960 skl_wm_get_hw_state(dev);
13961 else if (HAS_PCH_SPLIT(dev))
243e6a44
VS		 13962 ilk_wm_get_hw_state(dev);
13963
45e2b5f6 13964 if (force_restore) {
7d0bc1ea
VS		 13965 i915_redisable_vga(dev);
13966
f30da187
DV		 13967 /*
13968 * We need to use raw interfaces for restoring state to avoid
13969 * checking (bogus) intermediate states.
13970 */
055e393f 13971 for_each_pipe(dev_priv, pipe) {
b5644d05
JB		 13972 struct drm_crtc *crtc =
13973 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187 13974
7f27126e
JB		 13975 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
13976 crtc->primary->fb);
45e2b5f6
DV		 13977 }
13978 } else {
13979 intel_modeset_update_staged_output_state(dev);
13980 }
8af6cf88
DV		 13981
13982 intel_modeset_check_state(dev);
2c7111db
CW		 13983}
13984
13985void intel_modeset_gem_init(struct drm_device *dev)
13986{
92122789 13987 struct drm_i915_private *dev_priv = dev->dev_private;
484b41dd 13988 struct drm_crtc *c;
2ff8fde1 13989 struct drm_i915_gem_object *obj;
484b41dd 13990
ae48434c
ID		 13991 mutex_lock(&dev->struct_mutex);
13992 intel_init_gt_powersave(dev);
13993 mutex_unlock(&dev->struct_mutex);
13994
92122789
JB		 13995 /*
13996 * There may be no VBT; and if the BIOS enabled SSC we can
13997 * just keep using it to avoid unnecessary flicker. Whereas if the
13998 * BIOS isn't using it, don't assume it will work even if the VBT
13999 * indicates as much.
14000 */
14001 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
14002 dev_priv->vbt.lvds_use_ssc = !!(I915_READ(PCH_DREF_CONTROL) &
14003 DREF_SSC1_ENABLE);
14004
1833b134 14005 intel_modeset_init_hw(dev);
02e792fb
DV		 14006
14007 intel_setup_overlay(dev);
484b41dd
JB		 14008
14009 /*
14010 * Make sure any fbs we allocated at startup are properly
14011 * pinned & fenced. When we do the allocation it's too early
14012 * for this.
14013 */
14014 mutex_lock(&dev->struct_mutex);
70e1e0ec 14015 for_each_crtc(dev, c) {
2ff8fde1
MR		 14016 obj = intel_fb_obj(c->primary->fb);
14017 if (obj == NULL)
484b41dd
JB		 14018 continue;
14019
850c4cdc
TU		 14020 if (intel_pin_and_fence_fb_obj(c->primary,
14021 c->primary->fb,
82bc3b2d 14022 c->primary->state,
850c4cdc 14023 NULL)) {
484b41dd
JB		 14024 DRM_ERROR("failed to pin boot fb on pipe %d\n",
14025 to_intel_crtc(c)->pipe);
66e514c1
DA		 14026 drm_framebuffer_unreference(c->primary->fb);
14027 c->primary->fb = NULL;
afd65eb4 14028 update_state_fb(c->primary);
484b41dd
JB		 14029 }
14030 }
14031 mutex_unlock(&dev->struct_mutex);
0962c3c9
VS		 14032
14033 intel_backlight_register(dev);
79e53945
JB		 14034}
14035
4932e2c3
ID		 14036void intel_connector_unregister(struct intel_connector *intel_connector)
14037{
14038 struct drm_connector *connector = &intel_connector->base;
14039
14040 intel_panel_destroy_backlight(connector);
34ea3d38 14041 drm_connector_unregister(connector);
4932e2c3
ID		 14042}
14043
79e53945
JB		 14044void intel_modeset_cleanup(struct drm_device *dev)
14045{
652c393a 14046 struct drm_i915_private *dev_priv = dev->dev_private;
d9255d57 14047 struct drm_connector *connector;
652c393a 14048
2eb5252e
ID		 14049 intel_disable_gt_powersave(dev);
14050
0962c3c9
VS		 14051 intel_backlight_unregister(dev);
14052
fd0c0642
DV		 14053 /*
14054 * Interrupts and polling as the first thing to avoid creating havoc.
2eb5252e 14055 * Too much stuff here (turning of connectors, ...) would
fd0c0642
DV		 14056 * experience fancy races otherwise.
14057 */
2aeb7d3a 14058 intel_irq_uninstall(dev_priv);
eb21b92b 14059
fd0c0642
DV		 14060 /*
14061 * Due to the hpd irq storm handling the hotplug work can re-arm the
14062 * poll handlers. Hence disable polling after hpd handling is shut down.
14063 */
f87ea761 14064 drm_kms_helper_poll_fini(dev);
fd0c0642 14065
652c393a
JB		 14066 mutex_lock(&dev->struct_mutex);
14067
723bfd70
JB		 14068 intel_unregister_dsm_handler();
14069
7ff0ebcc 14070 intel_fbc_disable(dev);
e70236a8 14071
69341a5e
KH		 14072 mutex_unlock(&dev->struct_mutex);
14073
1630fe75
CW		 14074 /* flush any delayed tasks or pending work */
14075 flush_scheduled_work();
14076
db31af1d
JN		 14077 /* destroy the backlight and sysfs files before encoders/connectors */
14078 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4932e2c3
ID		 14079 struct intel_connector *intel_connector;
14080
14081 intel_connector = to_intel_connector(connector);
14082 intel_connector->unregister(intel_connector);
db31af1d 14083 }
d9255d57 14084
79e53945 14085 drm_mode_config_cleanup(dev);
4d7bb011
DV		 14086
14087 intel_cleanup_overlay(dev);
ae48434c
ID		 14088
14089 mutex_lock(&dev->struct_mutex);
14090 intel_cleanup_gt_powersave(dev);
14091 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 14092}
14093
f1c79df3
ZW		 14094/*
14095 * Return which encoder is currently attached for connector.
14096 */
df0e9248 14097struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 14098{
df0e9248
CW		 14099 return &intel_attached_encoder(connector)->base;
14100}
f1c79df3 14101
df0e9248
CW		 14102void intel_connector_attach_encoder(struct intel_connector *connector,
14103 struct intel_encoder *encoder)
14104{
14105 connector->encoder = encoder;
14106 drm_mode_connector_attach_encoder(&connector->base,
14107 &encoder->base);
79e53945 14108}
28d52043
DA		 14109
14110/*
14111 * set vga decode state - true == enable VGA decode
14112 */
14113int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
14114{
14115 struct drm_i915_private *dev_priv = dev->dev_private;
a885b3cc 14116 unsigned reg = INTEL_INFO(dev)->gen >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
28d52043
DA		 14117 u16 gmch_ctrl;
14118
75fa041d
CW		 14119 if (pci_read_config_word(dev_priv->bridge_dev, reg, &gmch_ctrl)) {
14120 DRM_ERROR("failed to read control word\n");
14121 return -EIO;
14122 }
14123
c0cc8a55
CW		 14124 if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !state)
14125 return 0;
14126
28d52043
DA		 14127 if (state)
14128 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
14129 else
14130 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
75fa041d
CW		 14131
14132 if (pci_write_config_word(dev_priv->bridge_dev, reg, gmch_ctrl)) {
14133 DRM_ERROR("failed to write control word\n");
14134 return -EIO;
14135 }
14136
28d52043
DA		 14137 return 0;
14138}
c4a1d9e4 14139
c4a1d9e4 14140struct intel_display_error_state {
ff57f1b0
PZ		 14141
14142 u32 power_well_driver;
14143
63b66e5b
CW		 14144 int num_transcoders;
14145
c4a1d9e4
CW		 14146 struct intel_cursor_error_state {
14147 u32 control;
14148 u32 position;
14149 u32 base;
14150 u32 size;
52331309 14151 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 14152
14153 struct intel_pipe_error_state {
ddf9c536 14154 bool power_domain_on;
c4a1d9e4 14155 u32 source;
f301b1e1 14156 u32 stat;
52331309 14157 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 14158
14159 struct intel_plane_error_state {
14160 u32 control;
14161 u32 stride;
14162 u32 size;
14163 u32 pos;
14164 u32 addr;
14165 u32 surface;
14166 u32 tile_offset;
52331309 14167 } plane[I915_MAX_PIPES];
63b66e5b
CW		 14168
14169 struct intel_transcoder_error_state {
ddf9c536 14170 bool power_domain_on;
63b66e5b
CW		 14171 enum transcoder cpu_transcoder;
14172
14173 u32 conf;
14174
14175 u32 htotal;
14176 u32 hblank;
14177 u32 hsync;
14178 u32 vtotal;
14179 u32 vblank;
14180 u32 vsync;
14181 } transcoder[4];
c4a1d9e4
CW		 14182};
14183
14184struct intel_display_error_state *
14185intel_display_capture_error_state(struct drm_device *dev)
14186{
fbee40df 14187 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4 14188 struct intel_display_error_state *error;
63b66e5b
CW		 14189 int transcoders[] = {
14190 TRANSCODER_A,
14191 TRANSCODER_B,
14192 TRANSCODER_C,
14193 TRANSCODER_EDP,
14194 };
c4a1d9e4
CW		 14195 int i;
14196
63b66e5b
CW		 14197 if (INTEL_INFO(dev)->num_pipes == 0)
14198 return NULL;
14199
9d1cb914 14200 error = kzalloc(sizeof(*error), GFP_ATOMIC);
c4a1d9e4
CW		 14201 if (error == NULL)
14202 return NULL;
14203
190be112 14204 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ff57f1b0
PZ		 14205 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
14206
055e393f 14207 for_each_pipe(dev_priv, i) {
ddf9c536 14208 error->pipe[i].power_domain_on =
f458ebbc
DV		 14209 __intel_display_power_is_enabled(dev_priv,
14210 POWER_DOMAIN_PIPE(i));
ddf9c536 14211 if (!error->pipe[i].power_domain_on)
9d1cb914
PZ		 14212 continue;
14213
5efb3e28
VS		 14214 error->cursor[i].control = I915_READ(CURCNTR(i));
14215 error->cursor[i].position = I915_READ(CURPOS(i));
14216 error->cursor[i].base = I915_READ(CURBASE(i));
c4a1d9e4
CW		 14217
14218 error->plane[i].control = I915_READ(DSPCNTR(i));
14219 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 14220 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 14221 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 14222 error->plane[i].pos = I915_READ(DSPPOS(i));
14223 }
ca291363
PZ		 14224 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
14225 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 14226 if (INTEL_INFO(dev)->gen >= 4) {
14227 error->plane[i].surface = I915_READ(DSPSURF(i));
14228 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
14229 }
14230
c4a1d9e4 14231 error->pipe[i].source = I915_READ(PIPESRC(i));
f301b1e1 14232
3abfce77 14233 if (HAS_GMCH_DISPLAY(dev))
f301b1e1 14234 error->pipe[i].stat = I915_READ(PIPESTAT(i));
63b66e5b
CW		 14235 }
14236
14237 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
14238 if (HAS_DDI(dev_priv->dev))
14239 error->num_transcoders++; /* Account for eDP. */
14240
14241 for (i = 0; i < error->num_transcoders; i++) {
14242 enum transcoder cpu_transcoder = transcoders[i];
14243
ddf9c536 14244 error->transcoder[i].power_domain_on =
f458ebbc 14245 __intel_display_power_is_enabled(dev_priv,
38cc1daf 14246 POWER_DOMAIN_TRANSCODER(cpu_transcoder));
ddf9c536 14247 if (!error->transcoder[i].power_domain_on)
9d1cb914
PZ		 14248 continue;
14249
63b66e5b
CW		 14250 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14251
14252 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14253 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14254 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14255 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14256 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14257 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14258 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 14259 }
14260
14261 return error;
14262}
14263
edc3d884
MK		 14264#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
14265
c4a1d9e4 14266void
edc3d884 14267intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 14268 struct drm_device *dev,
14269 struct intel_display_error_state *error)
14270{
055e393f 14271 struct drm_i915_private *dev_priv = dev->dev_private;
c4a1d9e4
CW		 14272 int i;
14273
63b66e5b
CW		 14274 if (!error)
14275 return;
14276
edc3d884 14277 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
190be112 14278 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
edc3d884 14279 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 14280 error->power_well_driver);
055e393f 14281 for_each_pipe(dev_priv, i) {
edc3d884 14282 err_printf(m, "Pipe [%d]:\n", i);
ddf9c536
ID		 14283 err_printf(m, " Power: %s\n",
14284 error->pipe[i].power_domain_on ? "on" : "off");
edc3d884 14285 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
f301b1e1 14286 err_printf(m, " STAT: %08x\n", error->pipe[i].stat);
edc3d884
MK		 14287
14288 err_printf(m, "Plane [%d]:\n", i);
14289 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
14290 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 14291 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 14292 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
14293 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 14294 }
4b71a570 14295 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 14296 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 14297 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 14298 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
14299 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 14300 }
14301
edc3d884
MK		 14302 err_printf(m, "Cursor [%d]:\n", i);
14303 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
14304 err_printf(m, " POS: %08x\n", error->cursor[i].position);
14305 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 14306 }
63b66e5b
CW		 14307
14308 for (i = 0; i < error->num_transcoders; i++) {
1cf84bb6 14309 err_printf(m, "CPU transcoder: %c\n",
63b66e5b 14310 transcoder_name(error->transcoder[i].cpu_transcoder));
ddf9c536
ID		 14311 err_printf(m, " Power: %s\n",
14312 error->transcoder[i].power_domain_on ? "on" : "off");
63b66e5b
CW		 14313 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14314 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14315 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14316 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14317 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14318 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14319 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
14320 }
c4a1d9e4 14321}
e2fcdaa9
VS		 14322
14323void intel_modeset_preclose(struct drm_device *dev, struct drm_file *file)
14324{
14325 struct intel_crtc *crtc;
14326
14327 for_each_intel_crtc(dev, crtc) {
14328 struct intel_unpin_work *work;
e2fcdaa9 14329
5e2d7afc 14330 spin_lock_irq(&dev->event_lock);
e2fcdaa9
VS		 14331
14332 work = crtc->unpin_work;
14333
14334 if (work && work->event &&
14335 work->event->base.file_priv == file) {
14336 kfree(work->event);
14337 work->event = NULL;
14338 }
14339
5e2d7afc 14340 spin_unlock_irq(&dev->event_lock);
e2fcdaa9
VS		 14341 }
14342}
Linux kernel - Deliverables
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