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drm/i915: Don't underflow bestppm
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
3dec0095 44static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 45static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945 46
f1f644dc
JB		 47static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
48 struct intel_crtc_config *pipe_config);
18442d08
VS		 49static void ironlake_pch_clock_get(struct intel_crtc *crtc,
50 struct intel_crtc_config *pipe_config);
f1f644dc 51
e7457a9a
DL		 52static int intel_set_mode(struct drm_crtc *crtc, struct drm_display_mode *mode,
53 int x, int y, struct drm_framebuffer *old_fb);
54
55
79e53945 56typedef struct {
0206e353 57 int min, max;
79e53945
JB		 58} intel_range_t;
59
60typedef struct {
0206e353
AJ		 61 int dot_limit;
62 int p2_slow, p2_fast;
79e53945
JB		 63} intel_p2_t;
64
d4906093
ML		 65typedef struct intel_limit intel_limit_t;
66struct intel_limit {
0206e353
AJ		 67 intel_range_t dot, vco, n, m, m1, m2, p, p1;
68 intel_p2_t p2;
d4906093 69};
79e53945 70
d2acd215
DV		 71int
72intel_pch_rawclk(struct drm_device *dev)
73{
74 struct drm_i915_private *dev_priv = dev->dev_private;
75
76 WARN_ON(!HAS_PCH_SPLIT(dev));
77
78 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
79}
80
021357ac
CW		 81static inline u32 /* units of 100MHz */
82intel_fdi_link_freq(struct drm_device *dev)
83{
8b99e68c
CW		 84 if (IS_GEN5(dev)) {
85 struct drm_i915_private *dev_priv = dev->dev_private;
86 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
87 } else
88 return 27;
021357ac
CW		 89}
90
5d536e28 91static const intel_limit_t intel_limits_i8xx_dac = {
0206e353
AJ		 92 .dot = { .min = 25000, .max = 350000 },
93 .vco = { .min = 930000, .max = 1400000 },
94 .n = { .min = 3, .max = 16 },
95 .m = { .min = 96, .max = 140 },
96 .m1 = { .min = 18, .max = 26 },
97 .m2 = { .min = 6, .max = 16 },
98 .p = { .min = 4, .max = 128 },
99 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 100 .p2 = { .dot_limit = 165000,
101 .p2_slow = 4, .p2_fast = 2 },
e4b36699
KP		 102};
103
5d536e28
DV		 104static const intel_limit_t intel_limits_i8xx_dvo = {
105 .dot = { .min = 25000, .max = 350000 },
106 .vco = { .min = 930000, .max = 1400000 },
107 .n = { .min = 3, .max = 16 },
108 .m = { .min = 96, .max = 140 },
109 .m1 = { .min = 18, .max = 26 },
110 .m2 = { .min = 6, .max = 16 },
111 .p = { .min = 4, .max = 128 },
112 .p1 = { .min = 2, .max = 33 },
113 .p2 = { .dot_limit = 165000,
114 .p2_slow = 4, .p2_fast = 4 },
115};
116
e4b36699 117static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 118 .dot = { .min = 25000, .max = 350000 },
119 .vco = { .min = 930000, .max = 1400000 },
120 .n = { .min = 3, .max = 16 },
121 .m = { .min = 96, .max = 140 },
122 .m1 = { .min = 18, .max = 26 },
123 .m2 = { .min = 6, .max = 16 },
124 .p = { .min = 4, .max = 128 },
125 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 126 .p2 = { .dot_limit = 165000,
127 .p2_slow = 14, .p2_fast = 7 },
e4b36699 128};
273e27ca 129
e4b36699 130static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 131 .dot = { .min = 20000, .max = 400000 },
132 .vco = { .min = 1400000, .max = 2800000 },
133 .n = { .min = 1, .max = 6 },
134 .m = { .min = 70, .max = 120 },
4f7dfb67
PJ		 135 .m1 = { .min = 8, .max = 18 },
136 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 137 .p = { .min = 5, .max = 80 },
138 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 139 .p2 = { .dot_limit = 200000,
140 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 141};
142
143static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 144 .dot = { .min = 20000, .max = 400000 },
145 .vco = { .min = 1400000, .max = 2800000 },
146 .n = { .min = 1, .max = 6 },
147 .m = { .min = 70, .max = 120 },
53a7d2d1
PJ		 148 .m1 = { .min = 8, .max = 18 },
149 .m2 = { .min = 3, .max = 7 },
0206e353
AJ		 150 .p = { .min = 7, .max = 98 },
151 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 152 .p2 = { .dot_limit = 112000,
153 .p2_slow = 14, .p2_fast = 7 },
e4b36699
KP		 154};
155
273e27ca 156
e4b36699 157static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 158 .dot = { .min = 25000, .max = 270000 },
159 .vco = { .min = 1750000, .max = 3500000},
160 .n = { .min = 1, .max = 4 },
161 .m = { .min = 104, .max = 138 },
162 .m1 = { .min = 17, .max = 23 },
163 .m2 = { .min = 5, .max = 11 },
164 .p = { .min = 10, .max = 30 },
165 .p1 = { .min = 1, .max = 3},
166 .p2 = { .dot_limit = 270000,
167 .p2_slow = 10,
168 .p2_fast = 10
044c7c41 169 },
e4b36699
KP		 170};
171
172static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 173 .dot = { .min = 22000, .max = 400000 },
174 .vco = { .min = 1750000, .max = 3500000},
175 .n = { .min = 1, .max = 4 },
176 .m = { .min = 104, .max = 138 },
177 .m1 = { .min = 16, .max = 23 },
178 .m2 = { .min = 5, .max = 11 },
179 .p = { .min = 5, .max = 80 },
180 .p1 = { .min = 1, .max = 8},
181 .p2 = { .dot_limit = 165000,
182 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 183};
184
185static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 186 .dot = { .min = 20000, .max = 115000 },
187 .vco = { .min = 1750000, .max = 3500000 },
188 .n = { .min = 1, .max = 3 },
189 .m = { .min = 104, .max = 138 },
190 .m1 = { .min = 17, .max = 23 },
191 .m2 = { .min = 5, .max = 11 },
192 .p = { .min = 28, .max = 112 },
193 .p1 = { .min = 2, .max = 8 },
194 .p2 = { .dot_limit = 0,
195 .p2_slow = 14, .p2_fast = 14
044c7c41 196 },
e4b36699
KP		 197};
198
199static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 200 .dot = { .min = 80000, .max = 224000 },
201 .vco = { .min = 1750000, .max = 3500000 },
202 .n = { .min = 1, .max = 3 },
203 .m = { .min = 104, .max = 138 },
204 .m1 = { .min = 17, .max = 23 },
205 .m2 = { .min = 5, .max = 11 },
206 .p = { .min = 14, .max = 42 },
207 .p1 = { .min = 2, .max = 6 },
208 .p2 = { .dot_limit = 0,
209 .p2_slow = 7, .p2_fast = 7
044c7c41 210 },
e4b36699
KP		 211};
212
f2b115e6 213static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 214 .dot = { .min = 20000, .max = 400000},
215 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 216 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 217 .n = { .min = 3, .max = 6 },
218 .m = { .min = 2, .max = 256 },
273e27ca 219 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 220 .m1 = { .min = 0, .max = 0 },
221 .m2 = { .min = 0, .max = 254 },
222 .p = { .min = 5, .max = 80 },
223 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 224 .p2 = { .dot_limit = 200000,
225 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 226};
227
f2b115e6 228static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 229 .dot = { .min = 20000, .max = 400000 },
230 .vco = { .min = 1700000, .max = 3500000 },
231 .n = { .min = 3, .max = 6 },
232 .m = { .min = 2, .max = 256 },
233 .m1 = { .min = 0, .max = 0 },
234 .m2 = { .min = 0, .max = 254 },
235 .p = { .min = 7, .max = 112 },
236 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 237 .p2 = { .dot_limit = 112000,
238 .p2_slow = 14, .p2_fast = 14 },
e4b36699
KP		 239};
240
273e27ca
EA		 241/* Ironlake / Sandybridge
242 *
243 * We calculate clock using (register_value + 2) for N/M1/M2, so here
244 * the range value for them is (actual_value - 2).
245 */
b91ad0ec 246static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 247 .dot = { .min = 25000, .max = 350000 },
248 .vco = { .min = 1760000, .max = 3510000 },
249 .n = { .min = 1, .max = 5 },
250 .m = { .min = 79, .max = 127 },
251 .m1 = { .min = 12, .max = 22 },
252 .m2 = { .min = 5, .max = 9 },
253 .p = { .min = 5, .max = 80 },
254 .p1 = { .min = 1, .max = 8 },
255 .p2 = { .dot_limit = 225000,
256 .p2_slow = 10, .p2_fast = 5 },
e4b36699
KP		 257};
258
b91ad0ec 259static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 260 .dot = { .min = 25000, .max = 350000 },
261 .vco = { .min = 1760000, .max = 3510000 },
262 .n = { .min = 1, .max = 3 },
263 .m = { .min = 79, .max = 118 },
264 .m1 = { .min = 12, .max = 22 },
265 .m2 = { .min = 5, .max = 9 },
266 .p = { .min = 28, .max = 112 },
267 .p1 = { .min = 2, .max = 8 },
268 .p2 = { .dot_limit = 225000,
269 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 270};
271
272static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 273 .dot = { .min = 25000, .max = 350000 },
274 .vco = { .min = 1760000, .max = 3510000 },
275 .n = { .min = 1, .max = 3 },
276 .m = { .min = 79, .max = 127 },
277 .m1 = { .min = 12, .max = 22 },
278 .m2 = { .min = 5, .max = 9 },
279 .p = { .min = 14, .max = 56 },
280 .p1 = { .min = 2, .max = 8 },
281 .p2 = { .dot_limit = 225000,
282 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 283};
284
273e27ca 285/* LVDS 100mhz refclk limits. */
b91ad0ec 286static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 287 .dot = { .min = 25000, .max = 350000 },
288 .vco = { .min = 1760000, .max = 3510000 },
289 .n = { .min = 1, .max = 2 },
290 .m = { .min = 79, .max = 126 },
291 .m1 = { .min = 12, .max = 22 },
292 .m2 = { .min = 5, .max = 9 },
293 .p = { .min = 28, .max = 112 },
0206e353 294 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 295 .p2 = { .dot_limit = 225000,
296 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 297};
298
299static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 300 .dot = { .min = 25000, .max = 350000 },
301 .vco = { .min = 1760000, .max = 3510000 },
302 .n = { .min = 1, .max = 3 },
303 .m = { .min = 79, .max = 126 },
304 .m1 = { .min = 12, .max = 22 },
305 .m2 = { .min = 5, .max = 9 },
306 .p = { .min = 14, .max = 42 },
0206e353 307 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 308 .p2 = { .dot_limit = 225000,
309 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 310};
311
a0c4da24
JB		 312static const intel_limit_t intel_limits_vlv_dac = {
313 .dot = { .min = 25000, .max = 270000 },
314 .vco = { .min = 4000000, .max = 6000000 },
315 .n = { .min = 1, .max = 7 },
316 .m = { .min = 22, .max = 450 }, /* guess */
317 .m1 = { .min = 2, .max = 3 },
318 .m2 = { .min = 11, .max = 156 },
319 .p = { .min = 10, .max = 30 },
75e53986 320 .p1 = { .min = 1, .max = 3 },
a0c4da24
JB		 321 .p2 = { .dot_limit = 270000,
322 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 323};
324
325static const intel_limit_t intel_limits_vlv_hdmi = {
75e53986
DV		 326 .dot = { .min = 25000, .max = 270000 },
327 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24
JB		 328 .n = { .min = 1, .max = 7 },
329 .m = { .min = 60, .max = 300 }, /* guess */
330 .m1 = { .min = 2, .max = 3 },
331 .m2 = { .min = 11, .max = 156 },
332 .p = { .min = 10, .max = 30 },
333 .p1 = { .min = 2, .max = 3 },
334 .p2 = { .dot_limit = 270000,
335 .p2_slow = 2, .p2_fast = 20 },
a0c4da24
JB		 336};
337
e0638cdf
PZ		 338/**
339 * Returns whether any output on the specified pipe is of the specified type
340 */
341static bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
342{
343 struct drm_device *dev = crtc->dev;
344 struct intel_encoder *encoder;
345
346 for_each_encoder_on_crtc(dev, crtc, encoder)
347 if (encoder->type == type)
348 return true;
349
350 return false;
351}
352
1b894b59
CW		 353static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
354 int refclk)
2c07245f 355{
b91ad0ec 356 struct drm_device *dev = crtc->dev;
2c07245f 357 const intel_limit_t *limit;
b91ad0ec
ZW		 358
359 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 360 if (intel_is_dual_link_lvds(dev)) {
1b894b59 361 if (refclk == 100000)
b91ad0ec
ZW		 362 limit = &intel_limits_ironlake_dual_lvds_100m;
363 else
364 limit = &intel_limits_ironlake_dual_lvds;
365 } else {
1b894b59 366 if (refclk == 100000)
b91ad0ec
ZW		 367 limit = &intel_limits_ironlake_single_lvds_100m;
368 else
369 limit = &intel_limits_ironlake_single_lvds;
370 }
c6bb3538 371 } else
b91ad0ec 372 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 373
374 return limit;
375}
376
044c7c41
ML		 377static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
378{
379 struct drm_device *dev = crtc->dev;
044c7c41
ML		 380 const intel_limit_t *limit;
381
382 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 383 if (intel_is_dual_link_lvds(dev))
e4b36699 384 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41 385 else
e4b36699 386 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 387 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
388 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 389 limit = &intel_limits_g4x_hdmi;
044c7c41 390 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 391 limit = &intel_limits_g4x_sdvo;
044c7c41 392 } else /* The option is for other outputs */
e4b36699 393 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 394
395 return limit;
396}
397
1b894b59 398static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 399{
400 struct drm_device *dev = crtc->dev;
401 const intel_limit_t *limit;
402
bad720ff 403 if (HAS_PCH_SPLIT(dev))
1b894b59 404 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 405 else if (IS_G4X(dev)) {
044c7c41 406 limit = intel_g4x_limit(crtc);
f2b115e6 407 } else if (IS_PINEVIEW(dev)) {
2177832f 408 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 409 limit = &intel_limits_pineview_lvds;
2177832f 410 else
f2b115e6 411 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 412 } else if (IS_VALLEYVIEW(dev)) {
413 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
414 limit = &intel_limits_vlv_dac;
a0c4da24 415 else
65ce4bf5 416 limit = &intel_limits_vlv_hdmi;
a6c45cf0
CW		 417 } else if (!IS_GEN2(dev)) {
418 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
419 limit = &intel_limits_i9xx_lvds;
420 else
421 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 422 } else {
423 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 424 limit = &intel_limits_i8xx_lvds;
5d536e28 425 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DVO))
e4b36699 426 limit = &intel_limits_i8xx_dvo;
5d536e28
DV		 427 else
428 limit = &intel_limits_i8xx_dac;
79e53945
JB		 429 }
430 return limit;
431}
432
f2b115e6
AJ		 433/* m1 is reserved as 0 in Pineview, n is a ring counter */
434static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 435{
2177832f
SL		 436 clock->m = clock->m2 + 2;
437 clock->p = clock->p1 * clock->p2;
438 clock->vco = refclk * clock->m / clock->n;
439 clock->dot = clock->vco / clock->p;
440}
441
7429e9d4
DV		 442static uint32_t i9xx_dpll_compute_m(struct dpll *dpll)
443{
444 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2);
445}
446
ac58c3f0 447static void i9xx_clock(int refclk, intel_clock_t *clock)
2177832f 448{
7429e9d4 449 clock->m = i9xx_dpll_compute_m(clock);
79e53945
JB		 450 clock->p = clock->p1 * clock->p2;
451 clock->vco = refclk * clock->m / (clock->n + 2);
452 clock->dot = clock->vco / clock->p;
453}
454
7c04d1d9 455#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 456/**
457 * Returns whether the given set of divisors are valid for a given refclk with
458 * the given connectors.
459 */
460
1b894b59
CW		 461static bool intel_PLL_is_valid(struct drm_device *dev,
462 const intel_limit_t *limit,
463 const intel_clock_t *clock)
79e53945 464{
79e53945 465 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 466 INTELPllInvalid("p1 out of range\n");
79e53945 467 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 468 INTELPllInvalid("p out of range\n");
79e53945 469 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 470 INTELPllInvalid("m2 out of range\n");
79e53945 471 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 472 INTELPllInvalid("m1 out of range\n");
f2b115e6 473 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 474 INTELPllInvalid("m1 <= m2\n");
79e53945 475 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 476 INTELPllInvalid("m out of range\n");
79e53945 477 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 478 INTELPllInvalid("n out of range\n");
79e53945 479 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 480 INTELPllInvalid("vco out of range\n");
79e53945
JB		 481 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
482 * connector, etc., rather than just a single range.
483 */
484 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 485 INTELPllInvalid("dot out of range\n");
79e53945
JB		 486
487 return true;
488}
489
d4906093 490static bool
ee9300bb 491i9xx_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 492 int target, int refclk, intel_clock_t *match_clock,
493 intel_clock_t *best_clock)
79e53945
JB		 494{
495 struct drm_device *dev = crtc->dev;
79e53945 496 intel_clock_t clock;
79e53945
JB		 497 int err = target;
498
a210b028 499 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 500 /*
a210b028
DV		 501 * For LVDS just rely on its current settings for dual-channel.
502 * We haven't figured out how to reliably set up different
503 * single/dual channel state, if we even can.
79e53945 504 */
1974cad0 505 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 506 clock.p2 = limit->p2.p2_fast;
507 else
508 clock.p2 = limit->p2.p2_slow;
509 } else {
510 if (target < limit->p2.dot_limit)
511 clock.p2 = limit->p2.p2_slow;
512 else
513 clock.p2 = limit->p2.p2_fast;
514 }
515
0206e353 516 memset(best_clock, 0, sizeof(*best_clock));
79e53945 517
42158660
ZY		 518 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
519 clock.m1++) {
520 for (clock.m2 = limit->m2.min;
521 clock.m2 <= limit->m2.max; clock.m2++) {
c0efc387 522 if (clock.m2 >= clock.m1)
42158660
ZY		 523 break;
524 for (clock.n = limit->n.min;
525 clock.n <= limit->n.max; clock.n++) {
526 for (clock.p1 = limit->p1.min;
527 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 528 int this_err;
529
ac58c3f0
DV		 530 i9xx_clock(refclk, &clock);
531 if (!intel_PLL_is_valid(dev, limit,
532 &clock))
533 continue;
534 if (match_clock &&
535 clock.p != match_clock->p)
536 continue;
537
538 this_err = abs(clock.dot - target);
539 if (this_err < err) {
540 *best_clock = clock;
541 err = this_err;
542 }
543 }
544 }
545 }
546 }
547
548 return (err != target);
549}
550
551static bool
ee9300bb
DV		 552pnv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
553 int target, int refclk, intel_clock_t *match_clock,
554 intel_clock_t *best_clock)
79e53945
JB		 555{
556 struct drm_device *dev = crtc->dev;
79e53945 557 intel_clock_t clock;
79e53945
JB		 558 int err = target;
559
a210b028 560 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 561 /*
a210b028
DV		 562 * For LVDS just rely on its current settings for dual-channel.
563 * We haven't figured out how to reliably set up different
564 * single/dual channel state, if we even can.
79e53945 565 */
1974cad0 566 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 567 clock.p2 = limit->p2.p2_fast;
568 else
569 clock.p2 = limit->p2.p2_slow;
570 } else {
571 if (target < limit->p2.dot_limit)
572 clock.p2 = limit->p2.p2_slow;
573 else
574 clock.p2 = limit->p2.p2_fast;
575 }
576
0206e353 577 memset(best_clock, 0, sizeof(*best_clock));
79e53945 578
42158660
ZY		 579 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
580 clock.m1++) {
581 for (clock.m2 = limit->m2.min;
582 clock.m2 <= limit->m2.max; clock.m2++) {
42158660
ZY		 583 for (clock.n = limit->n.min;
584 clock.n <= limit->n.max; clock.n++) {
585 for (clock.p1 = limit->p1.min;
586 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 587 int this_err;
588
ac58c3f0 589 pineview_clock(refclk, &clock);
1b894b59
CW		 590 if (!intel_PLL_is_valid(dev, limit,
591 &clock))
79e53945 592 continue;
cec2f356
SP		 593 if (match_clock &&
594 clock.p != match_clock->p)
595 continue;
79e53945
JB		 596
597 this_err = abs(clock.dot - target);
598 if (this_err < err) {
599 *best_clock = clock;
600 err = this_err;
601 }
602 }
603 }
604 }
605 }
606
607 return (err != target);
608}
609
d4906093 610static bool
ee9300bb
DV		 611g4x_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
612 int target, int refclk, intel_clock_t *match_clock,
613 intel_clock_t *best_clock)
d4906093
ML		 614{
615 struct drm_device *dev = crtc->dev;
d4906093
ML		 616 intel_clock_t clock;
617 int max_n;
618 bool found;
6ba770dc
AJ		 619 /* approximately equals target * 0.00585 */
620 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 621 found = false;
622
623 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 624 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 625 clock.p2 = limit->p2.p2_fast;
626 else
627 clock.p2 = limit->p2.p2_slow;
628 } else {
629 if (target < limit->p2.dot_limit)
630 clock.p2 = limit->p2.p2_slow;
631 else
632 clock.p2 = limit->p2.p2_fast;
633 }
634
635 memset(best_clock, 0, sizeof(*best_clock));
636 max_n = limit->n.max;
f77f13e2 637 /* based on hardware requirement, prefer smaller n to precision */
d4906093 638 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 639 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 640 for (clock.m1 = limit->m1.max;
641 clock.m1 >= limit->m1.min; clock.m1--) {
642 for (clock.m2 = limit->m2.max;
643 clock.m2 >= limit->m2.min; clock.m2--) {
644 for (clock.p1 = limit->p1.max;
645 clock.p1 >= limit->p1.min; clock.p1--) {
646 int this_err;
647
ac58c3f0 648 i9xx_clock(refclk, &clock);
1b894b59
CW		 649 if (!intel_PLL_is_valid(dev, limit,
650 &clock))
d4906093 651 continue;
1b894b59
CW		 652
653 this_err = abs(clock.dot - target);
d4906093
ML		 654 if (this_err < err_most) {
655 *best_clock = clock;
656 err_most = this_err;
657 max_n = clock.n;
658 found = true;
659 }
660 }
661 }
662 }
663 }
2c07245f
ZW		 664 return found;
665}
666
a0c4da24 667static bool
ee9300bb
DV		 668vlv_find_best_dpll(const intel_limit_t *limit, struct drm_crtc *crtc,
669 int target, int refclk, intel_clock_t *match_clock,
670 intel_clock_t *best_clock)
a0c4da24
JB		 671{
672 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
673 u32 m, n, fastclk;
f3f08572 674 u32 updrate, minupdate, p;
69e4f900 675 unsigned int bestppm = 1000000;
a0c4da24
JB		 676 int dotclk, flag;
677
af447bd3 678 flag = 0;
a0c4da24 679 dotclk = target * 1000;
a0c4da24
JB		 680 fastclk = dotclk / (2*100);
681 updrate = 0;
682 minupdate = 19200;
a0c4da24
JB		 683 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
684 bestm1 = bestm2 = bestp1 = bestp2 = 0;
685
686 /* based on hardware requirement, prefer smaller n to precision */
687 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
688 updrate = refclk / n;
689 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
690 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
691 if (p2 > 10)
692 p2 = p2 - 1;
693 p = p1 * p2;
694 /* based on hardware requirement, prefer bigger m1,m2 values */
695 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
69e4f900
VS		 696 unsigned int ppm, diff;
697
5de56df5 698 m2 = DIV_ROUND_CLOSEST(fastclk * p * n, refclk * m1);
a0c4da24
JB		 699 m = m1 * m2;
700 vco = updrate * m;
43b0ac53
VS		 701
702 if (vco < limit->vco.min || vco >= limit->vco.max)
703 continue;
704
69e4f900
VS		 705 diff = abs(vco / p - fastclk);
706 ppm = div_u64(1000000ULL * diff, fastclk);
707 if (ppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
43b0ac53
VS		 708 bestppm = 0;
709 flag = 1;
710 }
c686122c 711 if (bestppm >= 10 && ppm < bestppm - 10) {
69e4f900 712 bestppm = ppm;
43b0ac53
VS		 713 flag = 1;
714 }
715 if (flag) {
716 bestn = n;
717 bestm1 = m1;
718 bestm2 = m2;
719 bestp1 = p1;
720 bestp2 = p2;
721 flag = 0;
a0c4da24
JB		 722 }
723 }
724 }
725 }
726 }
727 best_clock->n = bestn;
728 best_clock->m1 = bestm1;
729 best_clock->m2 = bestm2;
730 best_clock->p1 = bestp1;
731 best_clock->p2 = bestp2;
732
733 return true;
734}
a4fc5ed6 735
20ddf665
VS		 736bool intel_crtc_active(struct drm_crtc *crtc)
737{
738 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
739
740 /* Be paranoid as we can arrive here with only partial
741 * state retrieved from the hardware during setup.
742 *
241bfc38 743 * We can ditch the adjusted_mode.crtc_clock check as soon
20ddf665
VS		 744 * as Haswell has gained clock readout/fastboot support.
745 *
746 * We can ditch the crtc->fb check as soon as we can
747 * properly reconstruct framebuffers.
748 */
749 return intel_crtc->active && crtc->fb &&
241bfc38 750 intel_crtc->config.adjusted_mode.crtc_clock;
20ddf665
VS		 751}
752
a5c961d1
PZ		 753enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
754 enum pipe pipe)
755{
756 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
757 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
758
3b117c8f 759 return intel_crtc->config.cpu_transcoder;
a5c961d1
PZ		 760}
761
a928d536
PZ		 762static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
763{
764 struct drm_i915_private *dev_priv = dev->dev_private;
765 u32 frame, frame_reg = PIPEFRAME(pipe);
766
767 frame = I915_READ(frame_reg);
768
769 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
770 DRM_DEBUG_KMS("vblank wait timed out\n");
771}
772
9d0498a2
JB		 773/**
774 * intel_wait_for_vblank - wait for vblank on a given pipe
775 * @dev: drm device
776 * @pipe: pipe to wait for
777 *
778 * Wait for vblank to occur on a given pipe. Needed for various bits of
779 * mode setting code.
780 */
781void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 782{
9d0498a2 783 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 784 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 785
a928d536
PZ		 786 if (INTEL_INFO(dev)->gen >= 5) {
787 ironlake_wait_for_vblank(dev, pipe);
788 return;
789 }
790
300387c0
CW		 791 /* Clear existing vblank status. Note this will clear any other
792 * sticky status fields as well.
793 *
794 * This races with i915_driver_irq_handler() with the result
795 * that either function could miss a vblank event. Here it is not
796 * fatal, as we will either wait upon the next vblank interrupt or
797 * timeout. Generally speaking intel_wait_for_vblank() is only
798 * called during modeset at which time the GPU should be idle and
799 * should *not* be performing page flips and thus not waiting on
800 * vblanks...
801 * Currently, the result of us stealing a vblank from the irq
802 * handler is that a single frame will be skipped during swapbuffers.
803 */
804 I915_WRITE(pipestat_reg,
805 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
806
9d0498a2 807 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 808 if (wait_for(I915_READ(pipestat_reg) &
809 PIPE_VBLANK_INTERRUPT_STATUS,
810 50))
9d0498a2
JB		 811 DRM_DEBUG_KMS("vblank wait timed out\n");
812}
813
ab7ad7f6
KP		 814/*
815 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 816 * @dev: drm device
817 * @pipe: pipe to wait for
818 *
819 * After disabling a pipe, we can't wait for vblank in the usual way,
820 * spinning on the vblank interrupt status bit, since we won't actually
821 * see an interrupt when the pipe is disabled.
822 *
ab7ad7f6
KP		 823 * On Gen4 and above:
824 * wait for the pipe register state bit to turn off
825 *
826 * Otherwise:
827 * wait for the display line value to settle (it usually
828 * ends up stopping at the start of the next frame).
58e10eb9 829 *
9d0498a2 830 */
58e10eb9 831void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 832{
833 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 834 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
835 pipe);
ab7ad7f6
KP		 836
837 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 838 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 839
840 /* Wait for the Pipe State to go off */
58e10eb9
CW		 841 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
842 100))
284637d9 843 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 844 } else {
837ba00f 845 u32 last_line, line_mask;
58e10eb9 846 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 847 unsigned long timeout = jiffies + msecs_to_jiffies(100);
848
837ba00f
PZ		 849 if (IS_GEN2(dev))
850 line_mask = DSL_LINEMASK_GEN2;
851 else
852 line_mask = DSL_LINEMASK_GEN3;
853
ab7ad7f6
KP		 854 /* Wait for the display line to settle */
855 do {
837ba00f 856 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 857 mdelay(5);
837ba00f 858 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 859 time_after(timeout, jiffies));
860 if (time_after(jiffies, timeout))
284637d9 861 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 862 }
79e53945
JB		 863}
864
b0ea7d37
DL		 865/*
866 * ibx_digital_port_connected - is the specified port connected?
867 * @dev_priv: i915 private structure
868 * @port: the port to test
869 *
870 * Returns true if @port is connected, false otherwise.
871 */
872bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
873 struct intel_digital_port *port)
874{
875 u32 bit;
876
c36346e3
DL		 877 if (HAS_PCH_IBX(dev_priv->dev)) {
878 switch(port->port) {
879 case PORT_B:
880 bit = SDE_PORTB_HOTPLUG;
881 break;
882 case PORT_C:
883 bit = SDE_PORTC_HOTPLUG;
884 break;
885 case PORT_D:
886 bit = SDE_PORTD_HOTPLUG;
887 break;
888 default:
889 return true;
890 }
891 } else {
892 switch(port->port) {
893 case PORT_B:
894 bit = SDE_PORTB_HOTPLUG_CPT;
895 break;
896 case PORT_C:
897 bit = SDE_PORTC_HOTPLUG_CPT;
898 break;
899 case PORT_D:
900 bit = SDE_PORTD_HOTPLUG_CPT;
901 break;
902 default:
903 return true;
904 }
b0ea7d37
DL		 905 }
906
907 return I915_READ(SDEISR) & bit;
908}
909
b24e7179
JB		 910static const char *state_string(bool enabled)
911{
912 return enabled ? "on" : "off";
913}
914
915/* Only for pre-ILK configs */
55607e8a
DV		 916void assert_pll(struct drm_i915_private *dev_priv,
917 enum pipe pipe, bool state)
b24e7179
JB		 918{
919 int reg;
920 u32 val;
921 bool cur_state;
922
923 reg = DPLL(pipe);
924 val = I915_READ(reg);
925 cur_state = !!(val & DPLL_VCO_ENABLE);
926 WARN(cur_state != state,
927 "PLL state assertion failure (expected %s, current %s)\n",
928 state_string(state), state_string(cur_state));
929}
b24e7179 930
23538ef1
JN		 931/* XXX: the dsi pll is shared between MIPI DSI ports */
932static void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
933{
934 u32 val;
935 bool cur_state;
936
937 mutex_lock(&dev_priv->dpio_lock);
938 val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
939 mutex_unlock(&dev_priv->dpio_lock);
940
941 cur_state = val & DSI_PLL_VCO_EN;
942 WARN(cur_state != state,
943 "DSI PLL state assertion failure (expected %s, current %s)\n",
944 state_string(state), state_string(cur_state));
945}
946#define assert_dsi_pll_enabled(d) assert_dsi_pll(d, true)
947#define assert_dsi_pll_disabled(d) assert_dsi_pll(d, false)
948
55607e8a 949struct intel_shared_dpll *
e2b78267
DV		 950intel_crtc_to_shared_dpll(struct intel_crtc *crtc)
951{
952 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
953
a43f6e0f 954 if (crtc->config.shared_dpll < 0)
e2b78267
DV		 955 return NULL;
956
a43f6e0f 957 return &dev_priv->shared_dplls[crtc->config.shared_dpll];
e2b78267
DV		 958}
959
040484af 960/* For ILK+ */
55607e8a
DV		 961void assert_shared_dpll(struct drm_i915_private *dev_priv,
962 struct intel_shared_dpll *pll,
963 bool state)
040484af 964{
040484af 965 bool cur_state;
5358901f 966 struct intel_dpll_hw_state hw_state;
040484af 967
9d82aa17
ED		 968 if (HAS_PCH_LPT(dev_priv->dev)) {
969 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
970 return;
971 }
972
92b27b08 973 if (WARN (!pll,
46edb027 974 "asserting DPLL %s with no DPLL\n", state_string(state)))
ee7b9f93 975 return;
ee7b9f93 976
5358901f 977 cur_state = pll->get_hw_state(dev_priv, pll, &hw_state);
92b27b08 978 WARN(cur_state != state,
5358901f
DV		 979 "%s assertion failure (expected %s, current %s)\n",
980 pll->name, state_string(state), state_string(cur_state));
040484af 981}
040484af
JB		 982
983static void assert_fdi_tx(struct drm_i915_private *dev_priv,
984 enum pipe pipe, bool state)
985{
986 int reg;
987 u32 val;
988 bool cur_state;
ad80a810
PZ		 989 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
990 pipe);
040484af 991
affa9354
PZ		 992 if (HAS_DDI(dev_priv->dev)) {
993 /* DDI does not have a specific FDI_TX register */
ad80a810 994 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 995 val = I915_READ(reg);
ad80a810 996 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 997 } else {
998 reg = FDI_TX_CTL(pipe);
999 val = I915_READ(reg);
1000 cur_state = !!(val & FDI_TX_ENABLE);
1001 }
040484af
JB		 1002 WARN(cur_state != state,
1003 "FDI TX state assertion failure (expected %s, current %s)\n",
1004 state_string(state), state_string(cur_state));
1005}
1006#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1007#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1008
1009static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1010 enum pipe pipe, bool state)
1011{
1012 int reg;
1013 u32 val;
1014 bool cur_state;
1015
d63fa0dc
PZ		 1016 reg = FDI_RX_CTL(pipe);
1017 val = I915_READ(reg);
1018 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1019 WARN(cur_state != state,
1020 "FDI RX state assertion failure (expected %s, current %s)\n",
1021 state_string(state), state_string(cur_state));
1022}
1023#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1024#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1025
1026static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1027 enum pipe pipe)
1028{
1029 int reg;
1030 u32 val;
1031
1032 /* ILK FDI PLL is always enabled */
1033 if (dev_priv->info->gen == 5)
1034 return;
1035
bf507ef7 1036 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1037 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1038 return;
1039
040484af
JB		 1040 reg = FDI_TX_CTL(pipe);
1041 val = I915_READ(reg);
1042 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1043}
1044
55607e8a
DV		 1045void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, bool state)
040484af
JB		 1047{
1048 int reg;
1049 u32 val;
55607e8a 1050 bool cur_state;
040484af
JB		 1051
1052 reg = FDI_RX_CTL(pipe);
1053 val = I915_READ(reg);
55607e8a
DV		 1054 cur_state = !!(val & FDI_RX_PLL_ENABLE);
1055 WARN(cur_state != state,
1056 "FDI RX PLL assertion failure (expected %s, current %s)\n",
1057 state_string(state), state_string(cur_state));
040484af
JB		 1058}
1059
ea0760cf
JB		 1060static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1061 enum pipe pipe)
1062{
1063 int pp_reg, lvds_reg;
1064 u32 val;
1065 enum pipe panel_pipe = PIPE_A;
0de3b485 1066 bool locked = true;
ea0760cf
JB		 1067
1068 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1069 pp_reg = PCH_PP_CONTROL;
1070 lvds_reg = PCH_LVDS;
1071 } else {
1072 pp_reg = PP_CONTROL;
1073 lvds_reg = LVDS;
1074 }
1075
1076 val = I915_READ(pp_reg);
1077 if (!(val & PANEL_POWER_ON) ||
1078 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1079 locked = false;
1080
1081 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1082 panel_pipe = PIPE_B;
1083
1084 WARN(panel_pipe == pipe && locked,
1085 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1086 pipe_name(pipe));
ea0760cf
JB		 1087}
1088
93ce0ba6
JN		 1089static void assert_cursor(struct drm_i915_private *dev_priv,
1090 enum pipe pipe, bool state)
1091{
1092 struct drm_device *dev = dev_priv->dev;
1093 bool cur_state;
1094
1095 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1096 cur_state = I915_READ(CURCNTR_IVB(pipe)) & CURSOR_MODE;
1097 else if (IS_845G(dev) || IS_I865G(dev))
1098 cur_state = I915_READ(_CURACNTR) & CURSOR_ENABLE;
1099 else
1100 cur_state = I915_READ(CURCNTR(pipe)) & CURSOR_MODE;
1101
1102 WARN(cur_state != state,
1103 "cursor on pipe %c assertion failure (expected %s, current %s)\n",
1104 pipe_name(pipe), state_string(state), state_string(cur_state));
1105}
1106#define assert_cursor_enabled(d, p) assert_cursor(d, p, true)
1107#define assert_cursor_disabled(d, p) assert_cursor(d, p, false)
1108
b840d907
JB		 1109void assert_pipe(struct drm_i915_private *dev_priv,
1110 enum pipe pipe, bool state)
b24e7179
JB		 1111{
1112 int reg;
1113 u32 val;
63d7bbe9 1114 bool cur_state;
702e7a56
PZ		 1115 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1116 pipe);
b24e7179 1117
8e636784
DV		 1118 /* if we need the pipe A quirk it must be always on */
1119 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1120 state = true;
1121
b97186f0
PZ		 1122 if (!intel_display_power_enabled(dev_priv->dev,
1123 POWER_DOMAIN_TRANSCODER(cpu_transcoder))) {
69310161
PZ		 1124 cur_state = false;
1125 } else {
1126 reg = PIPECONF(cpu_transcoder);
1127 val = I915_READ(reg);
1128 cur_state = !!(val & PIPECONF_ENABLE);
1129 }
1130
63d7bbe9
JB		 1131 WARN(cur_state != state,
1132 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1133 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1134}
1135
931872fc
CW		 1136static void assert_plane(struct drm_i915_private *dev_priv,
1137 enum plane plane, bool state)
b24e7179
JB		 1138{
1139 int reg;
1140 u32 val;
931872fc 1141 bool cur_state;
b24e7179
JB		 1142
1143 reg = DSPCNTR(plane);
1144 val = I915_READ(reg);
931872fc
CW		 1145 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1146 WARN(cur_state != state,
1147 "plane %c assertion failure (expected %s, current %s)\n",
1148 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1149}
1150
931872fc
CW		 1151#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1152#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1153
b24e7179
JB		 1154static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1155 enum pipe pipe)
1156{
653e1026 1157 struct drm_device *dev = dev_priv->dev;
b24e7179
JB		 1158 int reg, i;
1159 u32 val;
1160 int cur_pipe;
1161
653e1026
VS		 1162 /* Primary planes are fixed to pipes on gen4+ */
1163 if (INTEL_INFO(dev)->gen >= 4) {
28c05794
AJ		 1164 reg = DSPCNTR(pipe);
1165 val = I915_READ(reg);
1166 WARN((val & DISPLAY_PLANE_ENABLE),
1167 "plane %c assertion failure, should be disabled but not\n",
1168 plane_name(pipe));
19ec1358 1169 return;
28c05794 1170 }
19ec1358 1171
b24e7179 1172 /* Need to check both planes against the pipe */
08e2a7de 1173 for_each_pipe(i) {
b24e7179
JB		 1174 reg = DSPCNTR(i);
1175 val = I915_READ(reg);
1176 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1177 DISPPLANE_SEL_PIPE_SHIFT;
1178 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1179 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1180 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1181 }
1182}
1183
19332d7a
JB		 1184static void assert_sprites_disabled(struct drm_i915_private *dev_priv,
1185 enum pipe pipe)
1186{
20674eef 1187 struct drm_device *dev = dev_priv->dev;
19332d7a
JB		 1188 int reg, i;
1189 u32 val;
1190
20674eef
VS		 1191 if (IS_VALLEYVIEW(dev)) {
1192 for (i = 0; i < dev_priv->num_plane; i++) {
1193 reg = SPCNTR(pipe, i);
1194 val = I915_READ(reg);
1195 WARN((val & SP_ENABLE),
1196 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
1197 sprite_name(pipe, i), pipe_name(pipe));
1198 }
1199 } else if (INTEL_INFO(dev)->gen >= 7) {
1200 reg = SPRCTL(pipe);
19332d7a 1201 val = I915_READ(reg);
20674eef 1202 WARN((val & SPRITE_ENABLE),
06da8da2 1203 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef
VS		 1204 plane_name(pipe), pipe_name(pipe));
1205 } else if (INTEL_INFO(dev)->gen >= 5) {
1206 reg = DVSCNTR(pipe);
19332d7a 1207 val = I915_READ(reg);
20674eef 1208 WARN((val & DVS_ENABLE),
06da8da2 1209 "sprite %c assertion failure, should be off on pipe %c but is still active\n",
20674eef 1210 plane_name(pipe), pipe_name(pipe));
19332d7a
JB		 1211 }
1212}
1213
92f2584a
JB		 1214static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1215{
1216 u32 val;
1217 bool enabled;
1218
9d82aa17
ED		 1219 if (HAS_PCH_LPT(dev_priv->dev)) {
1220 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1221 return;
1222 }
1223
92f2584a
JB		 1224 val = I915_READ(PCH_DREF_CONTROL);
1225 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1226 DREF_SUPERSPREAD_SOURCE_MASK));
1227 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1228}
1229
ab9412ba
DV		 1230static void assert_pch_transcoder_disabled(struct drm_i915_private *dev_priv,
1231 enum pipe pipe)
92f2584a
JB		 1232{
1233 int reg;
1234 u32 val;
1235 bool enabled;
1236
ab9412ba 1237 reg = PCH_TRANSCONF(pipe);
92f2584a
JB		 1238 val = I915_READ(reg);
1239 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1240 WARN(enabled,
1241 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1242 pipe_name(pipe));
92f2584a
JB		 1243}
1244
4e634389
KP		 1245static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1246 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1247{
1248 if ((val & DP_PORT_EN) == 0)
1249 return false;
1250
1251 if (HAS_PCH_CPT(dev_priv->dev)) {
1252 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1253 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1254 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1255 return false;
1256 } else {
1257 if ((val & DP_PIPE_MASK) != (pipe << 30))
1258 return false;
1259 }
1260 return true;
1261}
1262
1519b995
KP		 1263static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1264 enum pipe pipe, u32 val)
1265{
dc0fa718 1266 if ((val & SDVO_ENABLE) == 0)
1519b995
KP		 1267 return false;
1268
1269 if (HAS_PCH_CPT(dev_priv->dev)) {
dc0fa718 1270 if ((val & SDVO_PIPE_SEL_MASK_CPT) != SDVO_PIPE_SEL_CPT(pipe))
1519b995
KP		 1271 return false;
1272 } else {
dc0fa718 1273 if ((val & SDVO_PIPE_SEL_MASK) != SDVO_PIPE_SEL(pipe))
1519b995
KP		 1274 return false;
1275 }
1276 return true;
1277}
1278
1279static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1280 enum pipe pipe, u32 val)
1281{
1282 if ((val & LVDS_PORT_EN) == 0)
1283 return false;
1284
1285 if (HAS_PCH_CPT(dev_priv->dev)) {
1286 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1287 return false;
1288 } else {
1289 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1290 return false;
1291 }
1292 return true;
1293}
1294
1295static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1296 enum pipe pipe, u32 val)
1297{
1298 if ((val & ADPA_DAC_ENABLE) == 0)
1299 return false;
1300 if (HAS_PCH_CPT(dev_priv->dev)) {
1301 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1302 return false;
1303 } else {
1304 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1305 return false;
1306 }
1307 return true;
1308}
1309
291906f1 1310static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1311 enum pipe pipe, int reg, u32 port_sel)
291906f1 1312{
47a05eca 1313 u32 val = I915_READ(reg);
4e634389 1314 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1315 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1316 reg, pipe_name(pipe));
de9a35ab 1317
75c5da27
DV		 1318 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1319 && (val & DP_PIPEB_SELECT),
de9a35ab 1320 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1321}
1322
1323static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1324 enum pipe pipe, int reg)
1325{
47a05eca 1326 u32 val = I915_READ(reg);
b70ad586 1327 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1328 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1329 reg, pipe_name(pipe));
de9a35ab 1330
dc0fa718 1331 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_ENABLE) == 0
75c5da27 1332 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1333 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1334}
1335
1336static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1337 enum pipe pipe)
1338{
1339 int reg;
1340 u32 val;
291906f1 1341
f0575e92
KP		 1342 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1343 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1344 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1345
1346 reg = PCH_ADPA;
1347 val = I915_READ(reg);
b70ad586 1348 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1349 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1350 pipe_name(pipe));
291906f1
JB		 1351
1352 reg = PCH_LVDS;
1353 val = I915_READ(reg);
b70ad586 1354 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1355 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1356 pipe_name(pipe));
291906f1 1357
e2debe91
PZ		 1358 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIB);
1359 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMIC);
1360 assert_pch_hdmi_disabled(dev_priv, pipe, PCH_HDMID);
291906f1
JB		 1361}
1362
40e9cf64
JB		 1363static void intel_init_dpio(struct drm_device *dev)
1364{
1365 struct drm_i915_private *dev_priv = dev->dev_private;
1366
1367 if (!IS_VALLEYVIEW(dev))
1368 return;
1369
1370 /*
1371 * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1372 * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
1373 * a. GUnit 0x2110 bit[0] set to 1 (def 0)
1374 * b. The other bits such as sfr settings / modesel may all be set
1375 * to 0.
1376 *
1377 * This should only be done on init and resume from S3 with both
1378 * PLLs disabled, or we risk losing DPIO and PLL synchronization.
1379 */
1380 I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1381}
1382
426115cf 1383static void vlv_enable_pll(struct intel_crtc *crtc)
87442f73 1384{
426115cf
DV		 1385 struct drm_device *dev = crtc->base.dev;
1386 struct drm_i915_private *dev_priv = dev->dev_private;
1387 int reg = DPLL(crtc->pipe);
1388 u32 dpll = crtc->config.dpll_hw_state.dpll;
87442f73 1389
426115cf 1390 assert_pipe_disabled(dev_priv, crtc->pipe);
87442f73
DV		 1391
1392 /* No really, not for ILK+ */
1393 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev));
1394
1395 /* PLL is protected by panel, make sure we can write it */
1396 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
426115cf 1397 assert_panel_unlocked(dev_priv, crtc->pipe);
87442f73 1398
426115cf
DV		 1399 I915_WRITE(reg, dpll);
1400 POSTING_READ(reg);
1401 udelay(150);
1402
1403 if (wait_for(((I915_READ(reg) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
1404 DRM_ERROR("DPLL %d failed to lock\n", crtc->pipe);
1405
1406 I915_WRITE(DPLL_MD(crtc->pipe), crtc->config.dpll_hw_state.dpll_md);
1407 POSTING_READ(DPLL_MD(crtc->pipe));
87442f73
DV		 1408
1409 /* We do this three times for luck */
426115cf 1410 I915_WRITE(reg, dpll);
87442f73
DV		 1411 POSTING_READ(reg);
1412 udelay(150); /* wait for warmup */
426115cf 1413 I915_WRITE(reg, dpll);
87442f73
DV		 1414 POSTING_READ(reg);
1415 udelay(150); /* wait for warmup */
426115cf 1416 I915_WRITE(reg, dpll);
87442f73
DV		 1417 POSTING_READ(reg);
1418 udelay(150); /* wait for warmup */
1419}
1420
66e3d5c0 1421static void i9xx_enable_pll(struct intel_crtc *crtc)
63d7bbe9 1422{
66e3d5c0
DV		 1423 struct drm_device *dev = crtc->base.dev;
1424 struct drm_i915_private *dev_priv = dev->dev_private;
1425 int reg = DPLL(crtc->pipe);
1426 u32 dpll = crtc->config.dpll_hw_state.dpll;
63d7bbe9 1427
66e3d5c0 1428 assert_pipe_disabled(dev_priv, crtc->pipe);
58c6eaa2 1429
63d7bbe9 1430 /* No really, not for ILK+ */
87442f73 1431 BUG_ON(dev_priv->info->gen >= 5);
63d7bbe9
JB		 1432
1433 /* PLL is protected by panel, make sure we can write it */
66e3d5c0
DV		 1434 if (IS_MOBILE(dev) && !IS_I830(dev))
1435 assert_panel_unlocked(dev_priv, crtc->pipe);
63d7bbe9 1436
66e3d5c0
DV		 1437 I915_WRITE(reg, dpll);
1438
1439 /* Wait for the clocks to stabilize. */
1440 POSTING_READ(reg);
1441 udelay(150);
1442
1443 if (INTEL_INFO(dev)->gen >= 4) {
1444 I915_WRITE(DPLL_MD(crtc->pipe),
1445 crtc->config.dpll_hw_state.dpll_md);
1446 } else {
1447 /* The pixel multiplier can only be updated once the
1448 * DPLL is enabled and the clocks are stable.
1449 *
1450 * So write it again.
1451 */
1452 I915_WRITE(reg, dpll);
1453 }
63d7bbe9
JB		 1454
1455 /* We do this three times for luck */
66e3d5c0 1456 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1457 POSTING_READ(reg);
1458 udelay(150); /* wait for warmup */
66e3d5c0 1459 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1460 POSTING_READ(reg);
1461 udelay(150); /* wait for warmup */
66e3d5c0 1462 I915_WRITE(reg, dpll);
63d7bbe9
JB		 1463 POSTING_READ(reg);
1464 udelay(150); /* wait for warmup */
1465}
1466
1467/**
50b44a44 1468 * i9xx_disable_pll - disable a PLL
63d7bbe9
JB		 1469 * @dev_priv: i915 private structure
1470 * @pipe: pipe PLL to disable
1471 *
1472 * Disable the PLL for @pipe, making sure the pipe is off first.
1473 *
1474 * Note! This is for pre-ILK only.
1475 */
50b44a44 1476static void i9xx_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9 1477{
63d7bbe9
JB		 1478 /* Don't disable pipe A or pipe A PLLs if needed */
1479 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1480 return;
1481
1482 /* Make sure the pipe isn't still relying on us */
1483 assert_pipe_disabled(dev_priv, pipe);
1484
50b44a44
DV		 1485 I915_WRITE(DPLL(pipe), 0);
1486 POSTING_READ(DPLL(pipe));
63d7bbe9
JB		 1487}
1488
f6071166
JB		 1489static void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1490{
1491 u32 val = 0;
1492
1493 /* Make sure the pipe isn't still relying on us */
1494 assert_pipe_disabled(dev_priv, pipe);
1495
1496 /* Leave integrated clock source enabled */
1497 if (pipe == PIPE_B)
1498 val = DPLL_INTEGRATED_CRI_CLK_VLV;
1499 I915_WRITE(DPLL(pipe), val);
1500 POSTING_READ(DPLL(pipe));
1501}
1502
89b667f8
JB		 1503void vlv_wait_port_ready(struct drm_i915_private *dev_priv, int port)
1504{
1505 u32 port_mask;
1506
1507 if (!port)
1508 port_mask = DPLL_PORTB_READY_MASK;
1509 else
1510 port_mask = DPLL_PORTC_READY_MASK;
1511
1512 if (wait_for((I915_READ(DPLL(0)) & port_mask) == 0, 1000))
1513 WARN(1, "timed out waiting for port %c ready: 0x%08x\n",
1514 'B' + port, I915_READ(DPLL(0)));
1515}
1516
92f2584a 1517/**
e72f9fbf 1518 * ironlake_enable_shared_dpll - enable PCH PLL
92f2584a
JB		 1519 * @dev_priv: i915 private structure
1520 * @pipe: pipe PLL to enable
1521 *
1522 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1523 * drives the transcoder clock.
1524 */
e2b78267 1525static void ironlake_enable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1526{
e2b78267
DV		 1527 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1528 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
92f2584a 1529
48da64a8 1530 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1531 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1532 if (WARN_ON(pll == NULL))
48da64a8
CW		 1533 return;
1534
1535 if (WARN_ON(pll->refcount == 0))
1536 return;
ee7b9f93 1537
46edb027
DV		 1538 DRM_DEBUG_KMS("enable %s (active %d, on? %d)for crtc %d\n",
1539 pll->name, pll->active, pll->on,
e2b78267 1540 crtc->base.base.id);
92f2584a 1541
cdbd2316
DV		 1542 if (pll->active++) {
1543 WARN_ON(!pll->on);
e9d6944e 1544 assert_shared_dpll_enabled(dev_priv, pll);
ee7b9f93
JB		 1545 return;
1546 }
f4a091c7 1547 WARN_ON(pll->on);
ee7b9f93 1548
46edb027 1549 DRM_DEBUG_KMS("enabling %s\n", pll->name);
e7b903d2 1550 pll->enable(dev_priv, pll);
ee7b9f93 1551 pll->on = true;
92f2584a
JB		 1552}
1553
e2b78267 1554static void intel_disable_shared_dpll(struct intel_crtc *crtc)
92f2584a 1555{
e2b78267
DV		 1556 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
1557 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
4c609cb8 1558
92f2584a
JB		 1559 /* PCH only available on ILK+ */
1560 BUG_ON(dev_priv->info->gen < 5);
87a875bb 1561 if (WARN_ON(pll == NULL))
ee7b9f93 1562 return;
92f2584a 1563
48da64a8
CW		 1564 if (WARN_ON(pll->refcount == 0))
1565 return;
7a419866 1566
46edb027
DV		 1567 DRM_DEBUG_KMS("disable %s (active %d, on? %d) for crtc %d\n",
1568 pll->name, pll->active, pll->on,
e2b78267 1569 crtc->base.base.id);
7a419866 1570
48da64a8 1571 if (WARN_ON(pll->active == 0)) {
e9d6944e 1572 assert_shared_dpll_disabled(dev_priv, pll);
48da64a8
CW		 1573 return;
1574 }
1575
e9d6944e 1576 assert_shared_dpll_enabled(dev_priv, pll);
f4a091c7 1577 WARN_ON(!pll->on);
cdbd2316 1578 if (--pll->active)
7a419866 1579 return;
ee7b9f93 1580
46edb027 1581 DRM_DEBUG_KMS("disabling %s\n", pll->name);
e7b903d2 1582 pll->disable(dev_priv, pll);
ee7b9f93 1583 pll->on = false;
92f2584a
JB		 1584}
1585
b8a4f404
PZ		 1586static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1587 enum pipe pipe)
040484af 1588{
23670b32 1589 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1590 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
e2b78267 1591 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
23670b32 1592 uint32_t reg, val, pipeconf_val;
040484af
JB		 1593
1594 /* PCH only available on ILK+ */
1595 BUG_ON(dev_priv->info->gen < 5);
1596
1597 /* Make sure PCH DPLL is enabled */
e72f9fbf 1598 assert_shared_dpll_enabled(dev_priv,
e9d6944e 1599 intel_crtc_to_shared_dpll(intel_crtc));
040484af
JB		 1600
1601 /* FDI must be feeding us bits for PCH ports */
1602 assert_fdi_tx_enabled(dev_priv, pipe);
1603 assert_fdi_rx_enabled(dev_priv, pipe);
1604
23670b32
DV		 1605 if (HAS_PCH_CPT(dev)) {
1606 /* Workaround: Set the timing override bit before enabling the
1607 * pch transcoder. */
1608 reg = TRANS_CHICKEN2(pipe);
1609 val = I915_READ(reg);
1610 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1611 I915_WRITE(reg, val);
59c859d6 1612 }
23670b32 1613
ab9412ba 1614 reg = PCH_TRANSCONF(pipe);
040484af 1615 val = I915_READ(reg);
5f7f726d 1616 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1617
1618 if (HAS_PCH_IBX(dev_priv->dev)) {
1619 /*
1620 * make the BPC in transcoder be consistent with
1621 * that in pipeconf reg.
1622 */
dfd07d72
DV		 1623 val &= ~PIPECONF_BPC_MASK;
1624 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1625 }
5f7f726d
PZ		 1626
1627 val &= ~TRANS_INTERLACE_MASK;
1628 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1629 if (HAS_PCH_IBX(dev_priv->dev) &&
1630 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1631 val |= TRANS_LEGACY_INTERLACED_ILK;
1632 else
1633 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1634 else
1635 val |= TRANS_PROGRESSIVE;
1636
040484af
JB		 1637 I915_WRITE(reg, val | TRANS_ENABLE);
1638 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
4bb6f1f3 1639 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe));
040484af
JB		 1640}
1641
8fb033d7 1642static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1643 enum transcoder cpu_transcoder)
040484af 1644{
8fb033d7 1645 u32 val, pipeconf_val;
8fb033d7
PZ		 1646
1647 /* PCH only available on ILK+ */
1648 BUG_ON(dev_priv->info->gen < 5);
1649
8fb033d7 1650 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1651 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1652 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1653
223a6fdf
PZ		 1654 /* Workaround: set timing override bit. */
1655 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1656 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1657 I915_WRITE(_TRANSA_CHICKEN2, val);
1658
25f3ef11 1659 val = TRANS_ENABLE;
937bb610 1660 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1661
9a76b1c6
PZ		 1662 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1663 PIPECONF_INTERLACED_ILK)
a35f2679 1664 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1665 else
1666 val |= TRANS_PROGRESSIVE;
1667
ab9412ba
DV		 1668 I915_WRITE(LPT_TRANSCONF, val);
1669 if (wait_for(I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE, 100))
937bb610 1670 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1671}
1672
b8a4f404
PZ		 1673static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1674 enum pipe pipe)
040484af 1675{
23670b32
DV		 1676 struct drm_device *dev = dev_priv->dev;
1677 uint32_t reg, val;
040484af
JB		 1678
1679 /* FDI relies on the transcoder */
1680 assert_fdi_tx_disabled(dev_priv, pipe);
1681 assert_fdi_rx_disabled(dev_priv, pipe);
1682
291906f1
JB		 1683 /* Ports must be off as well */
1684 assert_pch_ports_disabled(dev_priv, pipe);
1685
ab9412ba 1686 reg = PCH_TRANSCONF(pipe);
040484af
JB		 1687 val = I915_READ(reg);
1688 val &= ~TRANS_ENABLE;
1689 I915_WRITE(reg, val);
1690 /* wait for PCH transcoder off, transcoder state */
1691 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4bb6f1f3 1692 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
23670b32
DV		 1693
1694 if (!HAS_PCH_IBX(dev)) {
1695 /* Workaround: Clear the timing override chicken bit again. */
1696 reg = TRANS_CHICKEN2(pipe);
1697 val = I915_READ(reg);
1698 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1699 I915_WRITE(reg, val);
1700 }
040484af
JB		 1701}
1702
ab4d966c 1703static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1704{
8fb033d7
PZ		 1705 u32 val;
1706
ab9412ba 1707 val = I915_READ(LPT_TRANSCONF);
8fb033d7 1708 val &= ~TRANS_ENABLE;
ab9412ba 1709 I915_WRITE(LPT_TRANSCONF, val);
8fb033d7 1710 /* wait for PCH transcoder off, transcoder state */
ab9412ba 1711 if (wait_for((I915_READ(LPT_TRANSCONF) & TRANS_STATE_ENABLE) == 0, 50))
8a52fd9f 1712 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1713
1714 /* Workaround: clear timing override bit. */
1715 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1716 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1717 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1718}
1719
b24e7179 1720/**
309cfea8 1721 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1722 * @dev_priv: i915 private structure
1723 * @pipe: pipe to enable
040484af 1724 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1725 *
1726 * Enable @pipe, making sure that various hardware specific requirements
1727 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1728 *
1729 * @pipe should be %PIPE_A or %PIPE_B.
1730 *
1731 * Will wait until the pipe is actually running (i.e. first vblank) before
1732 * returning.
1733 */
040484af 1734static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
23538ef1 1735 bool pch_port, bool dsi)
b24e7179 1736{
702e7a56
PZ		 1737 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1738 pipe);
1a240d4d 1739 enum pipe pch_transcoder;
b24e7179
JB		 1740 int reg;
1741 u32 val;
1742
58c6eaa2 1743 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1744 assert_cursor_disabled(dev_priv, pipe);
58c6eaa2
DV		 1745 assert_sprites_disabled(dev_priv, pipe);
1746
681e5811 1747 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1748 pch_transcoder = TRANSCODER_A;
1749 else
1750 pch_transcoder = pipe;
1751
b24e7179
JB		 1752 /*
1753 * A pipe without a PLL won't actually be able to drive bits from
1754 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1755 * need the check.
1756 */
1757 if (!HAS_PCH_SPLIT(dev_priv->dev))
23538ef1
JN		 1758 if (dsi)
1759 assert_dsi_pll_enabled(dev_priv);
1760 else
1761 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1762 else {
1763 if (pch_port) {
1764 /* if driving the PCH, we need FDI enabled */
cc391bbb 1765 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1766 assert_fdi_tx_pll_enabled(dev_priv,
1767 (enum pipe) cpu_transcoder);
040484af
JB		 1768 }
1769 /* FIXME: assert CPU port conditions for SNB+ */
1770 }
b24e7179 1771
702e7a56 1772 reg = PIPECONF(cpu_transcoder);
b24e7179 1773 val = I915_READ(reg);
00d70b15
CW		 1774 if (val & PIPECONF_ENABLE)
1775 return;
1776
1777 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1778 intel_wait_for_vblank(dev_priv->dev, pipe);
1779}
1780
1781/**
309cfea8 1782 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1783 * @dev_priv: i915 private structure
1784 * @pipe: pipe to disable
1785 *
1786 * Disable @pipe, making sure that various hardware specific requirements
1787 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1788 *
1789 * @pipe should be %PIPE_A or %PIPE_B.
1790 *
1791 * Will wait until the pipe has shut down before returning.
1792 */
1793static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1794 enum pipe pipe)
1795{
702e7a56
PZ		 1796 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1797 pipe);
b24e7179
JB		 1798 int reg;
1799 u32 val;
1800
1801 /*
1802 * Make sure planes won't keep trying to pump pixels to us,
1803 * or we might hang the display.
1804 */
1805 assert_planes_disabled(dev_priv, pipe);
93ce0ba6 1806 assert_cursor_disabled(dev_priv, pipe);
19332d7a 1807 assert_sprites_disabled(dev_priv, pipe);
b24e7179
JB		 1808
1809 /* Don't disable pipe A or pipe A PLLs if needed */
1810 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1811 return;
1812
702e7a56 1813 reg = PIPECONF(cpu_transcoder);
b24e7179 1814 val = I915_READ(reg);
00d70b15
CW		 1815 if ((val & PIPECONF_ENABLE) == 0)
1816 return;
1817
1818 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1819 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1820}
1821
d74362c9
KP		 1822/*
1823 * Plane regs are double buffered, going from enabled->disabled needs a
1824 * trigger in order to latch. The display address reg provides this.
1825 */
6f1d69b0 1826void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1827 enum plane plane)
1828{
14f86147
DL		 1829 if (dev_priv->info->gen >= 4)
1830 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1831 else
1832 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1833}
1834
b24e7179
JB		 1835/**
1836 * intel_enable_plane - enable a display plane on a given pipe
1837 * @dev_priv: i915 private structure
1838 * @plane: plane to enable
1839 * @pipe: pipe being fed
1840 *
1841 * Enable @plane on @pipe, making sure that @pipe is running first.
1842 */
1843static void intel_enable_plane(struct drm_i915_private *dev_priv,
1844 enum plane plane, enum pipe pipe)
1845{
1846 int reg;
1847 u32 val;
1848
1849 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1850 assert_pipe_enabled(dev_priv, pipe);
1851
1852 reg = DSPCNTR(plane);
1853 val = I915_READ(reg);
00d70b15
CW		 1854 if (val & DISPLAY_PLANE_ENABLE)
1855 return;
1856
1857 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1858 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1859 intel_wait_for_vblank(dev_priv->dev, pipe);
1860}
1861
b24e7179
JB		 1862/**
1863 * intel_disable_plane - disable a display plane
1864 * @dev_priv: i915 private structure
1865 * @plane: plane to disable
1866 * @pipe: pipe consuming the data
1867 *
1868 * Disable @plane; should be an independent operation.
1869 */
1870static void intel_disable_plane(struct drm_i915_private *dev_priv,
1871 enum plane plane, enum pipe pipe)
1872{
1873 int reg;
1874 u32 val;
1875
1876 reg = DSPCNTR(plane);
1877 val = I915_READ(reg);
00d70b15
CW		 1878 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1879 return;
1880
1881 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1882 intel_flush_display_plane(dev_priv, plane);
1883 intel_wait_for_vblank(dev_priv->dev, pipe);
1884}
1885
693db184
CW		 1886static bool need_vtd_wa(struct drm_device *dev)
1887{
1888#ifdef CONFIG_INTEL_IOMMU
1889 if (INTEL_INFO(dev)->gen >= 6 && intel_iommu_gfx_mapped)
1890 return true;
1891#endif
1892 return false;
1893}
1894
127bd2ac 1895int
48b956c5 1896intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1897 struct drm_i915_gem_object *obj,
919926ae 1898 struct intel_ring_buffer *pipelined)
6b95a207 1899{
ce453d81 1900 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1901 u32 alignment;
1902 int ret;
1903
05394f39 1904 switch (obj->tiling_mode) {
6b95a207 1905 case I915_TILING_NONE:
534843da
CW		 1906 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1907 alignment = 128 * 1024;
a6c45cf0 1908 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1909 alignment = 4 * 1024;
1910 else
1911 alignment = 64 * 1024;
6b95a207
KH		 1912 break;
1913 case I915_TILING_X:
1914 /* pin() will align the object as required by fence */
1915 alignment = 0;
1916 break;
1917 case I915_TILING_Y:
8bb6e959
DV		 1918 /* Despite that we check this in framebuffer_init userspace can
1919 * screw us over and change the tiling after the fact. Only
1920 * pinned buffers can't change their tiling. */
1921 DRM_DEBUG_DRIVER("Y tiled not allowed for scan out buffers\n");
6b95a207
KH		 1922 return -EINVAL;
1923 default:
1924 BUG();
1925 }
1926
693db184
CW		 1927 /* Note that the w/a also requires 64 PTE of padding following the
1928 * bo. We currently fill all unused PTE with the shadow page and so
1929 * we should always have valid PTE following the scanout preventing
1930 * the VT-d warning.
1931 */
1932 if (need_vtd_wa(dev) && alignment < 256 * 1024)
1933 alignment = 256 * 1024;
1934
ce453d81 1935 dev_priv->mm.interruptible = false;
2da3b9b9 1936 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1937 if (ret)
ce453d81 1938 goto err_interruptible;
6b95a207
KH		 1939
1940 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1941 * fence, whereas 965+ only requires a fence if using
1942 * framebuffer compression. For simplicity, we always install
1943 * a fence as the cost is not that onerous.
1944 */
06d98131 1945 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1946 if (ret)
1947 goto err_unpin;
1690e1eb 1948
9a5a53b3 1949 i915_gem_object_pin_fence(obj);
6b95a207 1950
ce453d81 1951 dev_priv->mm.interruptible = true;
6b95a207 1952 return 0;
48b956c5
CW		 1953
1954err_unpin:
cc98b413 1955 i915_gem_object_unpin_from_display_plane(obj);
ce453d81
CW		 1956err_interruptible:
1957 dev_priv->mm.interruptible = true;
48b956c5 1958 return ret;
6b95a207
KH		 1959}
1960
1690e1eb
CW		 1961void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1962{
1963 i915_gem_object_unpin_fence(obj);
cc98b413 1964 i915_gem_object_unpin_from_display_plane(obj);
1690e1eb
CW		 1965}
1966
c2c75131
DV		 1967/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1968 * is assumed to be a power-of-two. */
bc752862
CW		 1969unsigned long intel_gen4_compute_page_offset(int *x, int *y,
1970 unsigned int tiling_mode,
1971 unsigned int cpp,
1972 unsigned int pitch)
c2c75131 1973{
bc752862
CW		 1974 if (tiling_mode != I915_TILING_NONE) {
1975 unsigned int tile_rows, tiles;
c2c75131 1976
bc752862
CW		 1977 tile_rows = *y / 8;
1978 *y %= 8;
c2c75131 1979
bc752862
CW		 1980 tiles = *x / (512/cpp);
1981 *x %= 512/cpp;
1982
1983 return tile_rows * pitch * 8 + tiles * 4096;
1984 } else {
1985 unsigned int offset;
1986
1987 offset = *y * pitch + *x * cpp;
1988 *y = 0;
1989 *x = (offset & 4095) / cpp;
1990 return offset & -4096;
1991 }
c2c75131
DV		 1992}
1993
17638cd6
JB		 1994static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1995 int x, int y)
81255565
JB		 1996{
1997 struct drm_device *dev = crtc->dev;
1998 struct drm_i915_private *dev_priv = dev->dev_private;
1999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2000 struct intel_framebuffer *intel_fb;
05394f39 2001 struct drm_i915_gem_object *obj;
81255565 2002 int plane = intel_crtc->plane;
e506a0c6 2003 unsigned long linear_offset;
81255565 2004 u32 dspcntr;
5eddb70b 2005 u32 reg;
81255565
JB		 2006
2007 switch (plane) {
2008 case 0:
2009 case 1:
2010 break;
2011 default:
84f44ce7 2012 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
81255565
JB		 2013 return -EINVAL;
2014 }
2015
2016 intel_fb = to_intel_framebuffer(fb);
2017 obj = intel_fb->obj;
81255565 2018
5eddb70b
CW		 2019 reg = DSPCNTR(plane);
2020 dspcntr = I915_READ(reg);
81255565
JB		 2021 /* Mask out pixel format bits in case we change it */
2022 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2023 switch (fb->pixel_format) {
2024 case DRM_FORMAT_C8:
81255565
JB		 2025 dspcntr |= DISPPLANE_8BPP;
2026 break;
57779d06
VS		 2027 case DRM_FORMAT_XRGB1555:
2028 case DRM_FORMAT_ARGB1555:
2029 dspcntr |= DISPPLANE_BGRX555;
81255565 2030 break;
57779d06
VS		 2031 case DRM_FORMAT_RGB565:
2032 dspcntr |= DISPPLANE_BGRX565;
2033 break;
2034 case DRM_FORMAT_XRGB8888:
2035 case DRM_FORMAT_ARGB8888:
2036 dspcntr |= DISPPLANE_BGRX888;
2037 break;
2038 case DRM_FORMAT_XBGR8888:
2039 case DRM_FORMAT_ABGR8888:
2040 dspcntr |= DISPPLANE_RGBX888;
2041 break;
2042 case DRM_FORMAT_XRGB2101010:
2043 case DRM_FORMAT_ARGB2101010:
2044 dspcntr |= DISPPLANE_BGRX101010;
2045 break;
2046 case DRM_FORMAT_XBGR2101010:
2047 case DRM_FORMAT_ABGR2101010:
2048 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2049 break;
2050 default:
baba133a 2051 BUG();
81255565 2052 }
57779d06 2053
a6c45cf0 2054 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2055 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2056 dspcntr |= DISPPLANE_TILED;
2057 else
2058 dspcntr &= ~DISPPLANE_TILED;
2059 }
2060
de1aa629
VS		 2061 if (IS_G4X(dev))
2062 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2063
5eddb70b 2064 I915_WRITE(reg, dspcntr);
81255565 2065
e506a0c6 2066 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2067
c2c75131
DV		 2068 if (INTEL_INFO(dev)->gen >= 4) {
2069 intel_crtc->dspaddr_offset =
bc752862
CW		 2070 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2071 fb->bits_per_pixel / 8,
2072 fb->pitches[0]);
c2c75131
DV		 2073 linear_offset -= intel_crtc->dspaddr_offset;
2074 } else {
e506a0c6 2075 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2076 }
e506a0c6 2077
f343c5f6
BW		 2078 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2079 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2080 fb->pitches[0]);
01f2c773 2081 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2082 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131 2083 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2084 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
5eddb70b 2085 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2086 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2087 } else
f343c5f6 2088 I915_WRITE(DSPADDR(plane), i915_gem_obj_ggtt_offset(obj) + linear_offset);
5eddb70b 2089 POSTING_READ(reg);
81255565 2090
17638cd6
JB		 2091 return 0;
2092}
2093
2094static int ironlake_update_plane(struct drm_crtc *crtc,
2095 struct drm_framebuffer *fb, int x, int y)
2096{
2097 struct drm_device *dev = crtc->dev;
2098 struct drm_i915_private *dev_priv = dev->dev_private;
2099 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2100 struct intel_framebuffer *intel_fb;
2101 struct drm_i915_gem_object *obj;
2102 int plane = intel_crtc->plane;
e506a0c6 2103 unsigned long linear_offset;
17638cd6
JB		 2104 u32 dspcntr;
2105 u32 reg;
2106
2107 switch (plane) {
2108 case 0:
2109 case 1:
27f8227b 2110 case 2:
17638cd6
JB		 2111 break;
2112 default:
84f44ce7 2113 DRM_ERROR("Can't update plane %c in SAREA\n", plane_name(plane));
17638cd6
JB		 2114 return -EINVAL;
2115 }
2116
2117 intel_fb = to_intel_framebuffer(fb);
2118 obj = intel_fb->obj;
2119
2120 reg = DSPCNTR(plane);
2121 dspcntr = I915_READ(reg);
2122 /* Mask out pixel format bits in case we change it */
2123 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2124 switch (fb->pixel_format) {
2125 case DRM_FORMAT_C8:
17638cd6
JB		 2126 dspcntr |= DISPPLANE_8BPP;
2127 break;
57779d06
VS		 2128 case DRM_FORMAT_RGB565:
2129 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2130 break;
57779d06
VS		 2131 case DRM_FORMAT_XRGB8888:
2132 case DRM_FORMAT_ARGB8888:
2133 dspcntr |= DISPPLANE_BGRX888;
2134 break;
2135 case DRM_FORMAT_XBGR8888:
2136 case DRM_FORMAT_ABGR8888:
2137 dspcntr |= DISPPLANE_RGBX888;
2138 break;
2139 case DRM_FORMAT_XRGB2101010:
2140 case DRM_FORMAT_ARGB2101010:
2141 dspcntr |= DISPPLANE_BGRX101010;
2142 break;
2143 case DRM_FORMAT_XBGR2101010:
2144 case DRM_FORMAT_ABGR2101010:
2145 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2146 break;
2147 default:
baba133a 2148 BUG();
17638cd6
JB		 2149 }
2150
2151 if (obj->tiling_mode != I915_TILING_NONE)
2152 dspcntr |= DISPPLANE_TILED;
2153 else
2154 dspcntr &= ~DISPPLANE_TILED;
2155
1f5d76db
PZ		 2156 if (IS_HASWELL(dev))
2157 dspcntr &= ~DISPPLANE_TRICKLE_FEED_DISABLE;
2158 else
2159 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
17638cd6
JB		 2160
2161 I915_WRITE(reg, dspcntr);
2162
e506a0c6 2163 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2164 intel_crtc->dspaddr_offset =
bc752862
CW		 2165 intel_gen4_compute_page_offset(&x, &y, obj->tiling_mode,
2166 fb->bits_per_pixel / 8,
2167 fb->pitches[0]);
c2c75131 2168 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2169
f343c5f6
BW		 2170 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
2171 i915_gem_obj_ggtt_offset(obj), linear_offset, x, y,
2172 fb->pitches[0]);
01f2c773 2173 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131 2174 I915_MODIFY_DISPBASE(DSPSURF(plane),
f343c5f6 2175 i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2176 if (IS_HASWELL(dev)) {
2177 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2178 } else {
2179 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2180 I915_WRITE(DSPLINOFF(plane), linear_offset);
2181 }
17638cd6
JB		 2182 POSTING_READ(reg);
2183
2184 return 0;
2185}
2186
2187/* Assume fb object is pinned & idle & fenced and just update base pointers */
2188static int
2189intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2190 int x, int y, enum mode_set_atomic state)
2191{
2192 struct drm_device *dev = crtc->dev;
2193 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2194
6b8e6ed0
CW		 2195 if (dev_priv->display.disable_fbc)
2196 dev_priv->display.disable_fbc(dev);
3dec0095 2197 intel_increase_pllclock(crtc);
81255565 2198
6b8e6ed0 2199 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2200}
2201
96a02917
VS		 2202void intel_display_handle_reset(struct drm_device *dev)
2203{
2204 struct drm_i915_private *dev_priv = dev->dev_private;
2205 struct drm_crtc *crtc;
2206
2207 /*
2208 * Flips in the rings have been nuked by the reset,
2209 * so complete all pending flips so that user space
2210 * will get its events and not get stuck.
2211 *
2212 * Also update the base address of all primary
2213 * planes to the the last fb to make sure we're
2214 * showing the correct fb after a reset.
2215 *
2216 * Need to make two loops over the crtcs so that we
2217 * don't try to grab a crtc mutex before the
2218 * pending_flip_queue really got woken up.
2219 */
2220
2221 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2222 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2223 enum plane plane = intel_crtc->plane;
2224
2225 intel_prepare_page_flip(dev, plane);
2226 intel_finish_page_flip_plane(dev, plane);
2227 }
2228
2229 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2230 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2231
2232 mutex_lock(&crtc->mutex);
2233 if (intel_crtc->active)
2234 dev_priv->display.update_plane(crtc, crtc->fb,
2235 crtc->x, crtc->y);
2236 mutex_unlock(&crtc->mutex);
2237 }
2238}
2239
14667a4b
CW		 2240static int
2241intel_finish_fb(struct drm_framebuffer *old_fb)
2242{
2243 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2244 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2245 bool was_interruptible = dev_priv->mm.interruptible;
2246 int ret;
2247
14667a4b
CW		 2248 /* Big Hammer, we also need to ensure that any pending
2249 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2250 * current scanout is retired before unpinning the old
2251 * framebuffer.
2252 *
2253 * This should only fail upon a hung GPU, in which case we
2254 * can safely continue.
2255 */
2256 dev_priv->mm.interruptible = false;
2257 ret = i915_gem_object_finish_gpu(obj);
2258 dev_priv->mm.interruptible = was_interruptible;
2259
2260 return ret;
2261}
2262
198598d0
VS		 2263static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2264{
2265 struct drm_device *dev = crtc->dev;
2266 struct drm_i915_master_private *master_priv;
2267 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2268
2269 if (!dev->primary->master)
2270 return;
2271
2272 master_priv = dev->primary->master->driver_priv;
2273 if (!master_priv->sarea_priv)
2274 return;
2275
2276 switch (intel_crtc->pipe) {
2277 case 0:
2278 master_priv->sarea_priv->pipeA_x = x;
2279 master_priv->sarea_priv->pipeA_y = y;
2280 break;
2281 case 1:
2282 master_priv->sarea_priv->pipeB_x = x;
2283 master_priv->sarea_priv->pipeB_y = y;
2284 break;
2285 default:
2286 break;
2287 }
2288}
2289
5c3b82e2 2290static int
3c4fdcfb 2291intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2292 struct drm_framebuffer *fb)
79e53945
JB		 2293{
2294 struct drm_device *dev = crtc->dev;
6b8e6ed0 2295 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2296 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2297 struct drm_framebuffer *old_fb;
5c3b82e2 2298 int ret;
79e53945
JB		 2299
2300 /* no fb bound */
94352cf9 2301 if (!fb) {
a5071c2f 2302 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2303 return 0;
2304 }
2305
7eb552ae 2306 if (intel_crtc->plane > INTEL_INFO(dev)->num_pipes) {
84f44ce7
VS		 2307 DRM_ERROR("no plane for crtc: plane %c, num_pipes %d\n",
2308 plane_name(intel_crtc->plane),
2309 INTEL_INFO(dev)->num_pipes);
5c3b82e2 2310 return -EINVAL;
79e53945
JB		 2311 }
2312
5c3b82e2 2313 mutex_lock(&dev->struct_mutex);
265db958 2314 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2315 to_intel_framebuffer(fb)->obj,
919926ae 2316 NULL);
5c3b82e2
CW		 2317 if (ret != 0) {
2318 mutex_unlock(&dev->struct_mutex);
a5071c2f 2319 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2320 return ret;
2321 }
79e53945 2322
bb2043de
DL		 2323 /*
2324 * Update pipe size and adjust fitter if needed: the reason for this is
2325 * that in compute_mode_changes we check the native mode (not the pfit
2326 * mode) to see if we can flip rather than do a full mode set. In the
2327 * fastboot case, we'll flip, but if we don't update the pipesrc and
2328 * pfit state, we'll end up with a big fb scanned out into the wrong
2329 * sized surface.
2330 *
2331 * To fix this properly, we need to hoist the checks up into
2332 * compute_mode_changes (or above), check the actual pfit state and
2333 * whether the platform allows pfit disable with pipe active, and only
2334 * then update the pipesrc and pfit state, even on the flip path.
2335 */
4d6a3e63 2336 if (i915_fastboot) {
d7bf63f2
DL		 2337 const struct drm_display_mode *adjusted_mode =
2338 &intel_crtc->config.adjusted_mode;
2339
4d6a3e63 2340 I915_WRITE(PIPESRC(intel_crtc->pipe),
d7bf63f2
DL		 2341 ((adjusted_mode->crtc_hdisplay - 1) << 16) |
2342 (adjusted_mode->crtc_vdisplay - 1));
fd4daa9c 2343 if (!intel_crtc->config.pch_pfit.enabled &&
4d6a3e63
JB		 2344 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
2345 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
2346 I915_WRITE(PF_CTL(intel_crtc->pipe), 0);
2347 I915_WRITE(PF_WIN_POS(intel_crtc->pipe), 0);
2348 I915_WRITE(PF_WIN_SZ(intel_crtc->pipe), 0);
2349 }
2350 }
2351
94352cf9 2352 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2353 if (ret) {
94352cf9 2354 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2355 mutex_unlock(&dev->struct_mutex);
a5071c2f 2356 DRM_ERROR("failed to update base address\n");
4e6cfefc 2357 return ret;
79e53945 2358 }
3c4fdcfb 2359
94352cf9
DV		 2360 old_fb = crtc->fb;
2361 crtc->fb = fb;
6c4c86f5
DV		 2362 crtc->x = x;
2363 crtc->y = y;
94352cf9 2364
b7f1de28 2365 if (old_fb) {
d7697eea
DV		 2366 if (intel_crtc->active && old_fb != fb)
2367 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2368 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2369 }
652c393a 2370
6b8e6ed0 2371 intel_update_fbc(dev);
4906557e 2372 intel_edp_psr_update(dev);
5c3b82e2 2373 mutex_unlock(&dev->struct_mutex);
79e53945 2374
198598d0 2375 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2376
2377 return 0;
79e53945
JB		 2378}
2379
5e84e1a4
ZW		 2380static void intel_fdi_normal_train(struct drm_crtc *crtc)
2381{
2382 struct drm_device *dev = crtc->dev;
2383 struct drm_i915_private *dev_priv = dev->dev_private;
2384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2385 int pipe = intel_crtc->pipe;
2386 u32 reg, temp;
2387
2388 /* enable normal train */
2389 reg = FDI_TX_CTL(pipe);
2390 temp = I915_READ(reg);
61e499bf 2391 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2392 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2393 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2394 } else {
2395 temp &= ~FDI_LINK_TRAIN_NONE;
2396 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2397 }
5e84e1a4
ZW		 2398 I915_WRITE(reg, temp);
2399
2400 reg = FDI_RX_CTL(pipe);
2401 temp = I915_READ(reg);
2402 if (HAS_PCH_CPT(dev)) {
2403 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2404 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2405 } else {
2406 temp &= ~FDI_LINK_TRAIN_NONE;
2407 temp |= FDI_LINK_TRAIN_NONE;
2408 }
2409 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2410
2411 /* wait one idle pattern time */
2412 POSTING_READ(reg);
2413 udelay(1000);
357555c0
JB		 2414
2415 /* IVB wants error correction enabled */
2416 if (IS_IVYBRIDGE(dev))
2417 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2418 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2419}
2420
1e833f40
DV		 2421static bool pipe_has_enabled_pch(struct intel_crtc *intel_crtc)
2422{
2423 return intel_crtc->base.enabled && intel_crtc->config.has_pch_encoder;
2424}
2425
01a415fd
DV		 2426static void ivb_modeset_global_resources(struct drm_device *dev)
2427{
2428 struct drm_i915_private *dev_priv = dev->dev_private;
2429 struct intel_crtc *pipe_B_crtc =
2430 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2431 struct intel_crtc *pipe_C_crtc =
2432 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2433 uint32_t temp;
2434
1e833f40
DV		 2435 /*
2436 * When everything is off disable fdi C so that we could enable fdi B
2437 * with all lanes. Note that we don't care about enabled pipes without
2438 * an enabled pch encoder.
2439 */
2440 if (!pipe_has_enabled_pch(pipe_B_crtc) &&
2441 !pipe_has_enabled_pch(pipe_C_crtc)) {
01a415fd
DV		 2442 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2443 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2444
2445 temp = I915_READ(SOUTH_CHICKEN1);
2446 temp &= ~FDI_BC_BIFURCATION_SELECT;
2447 DRM_DEBUG_KMS("disabling fdi C rx\n");
2448 I915_WRITE(SOUTH_CHICKEN1, temp);
2449 }
2450}
2451
8db9d77b
ZW		 2452/* The FDI link training functions for ILK/Ibexpeak. */
2453static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2454{
2455 struct drm_device *dev = crtc->dev;
2456 struct drm_i915_private *dev_priv = dev->dev_private;
2457 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2458 int pipe = intel_crtc->pipe;
0fc932b8 2459 int plane = intel_crtc->plane;
5eddb70b 2460 u32 reg, temp, tries;
8db9d77b 2461
0fc932b8
JB		 2462 /* FDI needs bits from pipe & plane first */
2463 assert_pipe_enabled(dev_priv, pipe);
2464 assert_plane_enabled(dev_priv, plane);
2465
e1a44743
AJ		 2466 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2467 for train result */
5eddb70b
CW		 2468 reg = FDI_RX_IMR(pipe);
2469 temp = I915_READ(reg);
e1a44743
AJ		 2470 temp &= ~FDI_RX_SYMBOL_LOCK;
2471 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2472 I915_WRITE(reg, temp);
2473 I915_READ(reg);
e1a44743
AJ		 2474 udelay(150);
2475
8db9d77b 2476 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2477 reg = FDI_TX_CTL(pipe);
2478 temp = I915_READ(reg);
627eb5a3
DV		 2479 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2480 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2481 temp &= ~FDI_LINK_TRAIN_NONE;
2482 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2483 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2484
5eddb70b
CW		 2485 reg = FDI_RX_CTL(pipe);
2486 temp = I915_READ(reg);
8db9d77b
ZW		 2487 temp &= ~FDI_LINK_TRAIN_NONE;
2488 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2489 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2490
2491 POSTING_READ(reg);
8db9d77b
ZW		 2492 udelay(150);
2493
5b2adf89 2494 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2495 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2496 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2497 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2498
5eddb70b 2499 reg = FDI_RX_IIR(pipe);
e1a44743 2500 for (tries = 0; tries < 5; tries++) {
5eddb70b 2501 temp = I915_READ(reg);
8db9d77b
ZW		 2502 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2503
2504 if ((temp & FDI_RX_BIT_LOCK)) {
2505 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2506 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2507 break;
2508 }
8db9d77b 2509 }
e1a44743 2510 if (tries == 5)
5eddb70b 2511 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2512
2513 /* Train 2 */
5eddb70b
CW		 2514 reg = FDI_TX_CTL(pipe);
2515 temp = I915_READ(reg);
8db9d77b
ZW		 2516 temp &= ~FDI_LINK_TRAIN_NONE;
2517 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2518 I915_WRITE(reg, temp);
8db9d77b 2519
5eddb70b
CW		 2520 reg = FDI_RX_CTL(pipe);
2521 temp = I915_READ(reg);
8db9d77b
ZW		 2522 temp &= ~FDI_LINK_TRAIN_NONE;
2523 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2524 I915_WRITE(reg, temp);
8db9d77b 2525
5eddb70b
CW		 2526 POSTING_READ(reg);
2527 udelay(150);
8db9d77b 2528
5eddb70b 2529 reg = FDI_RX_IIR(pipe);
e1a44743 2530 for (tries = 0; tries < 5; tries++) {
5eddb70b 2531 temp = I915_READ(reg);
8db9d77b
ZW		 2532 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2533
2534 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2535 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2536 DRM_DEBUG_KMS("FDI train 2 done.\n");
2537 break;
2538 }
8db9d77b 2539 }
e1a44743 2540 if (tries == 5)
5eddb70b 2541 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2542
2543 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2544
8db9d77b
ZW		 2545}
2546
0206e353 2547static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2548 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2549 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2550 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2551 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2552};
2553
2554/* The FDI link training functions for SNB/Cougarpoint. */
2555static void gen6_fdi_link_train(struct drm_crtc *crtc)
2556{
2557 struct drm_device *dev = crtc->dev;
2558 struct drm_i915_private *dev_priv = dev->dev_private;
2559 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2560 int pipe = intel_crtc->pipe;
fa37d39e 2561 u32 reg, temp, i, retry;
8db9d77b 2562
e1a44743
AJ		 2563 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2564 for train result */
5eddb70b
CW		 2565 reg = FDI_RX_IMR(pipe);
2566 temp = I915_READ(reg);
e1a44743
AJ		 2567 temp &= ~FDI_RX_SYMBOL_LOCK;
2568 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2569 I915_WRITE(reg, temp);
2570
2571 POSTING_READ(reg);
e1a44743
AJ		 2572 udelay(150);
2573
8db9d77b 2574 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2575 reg = FDI_TX_CTL(pipe);
2576 temp = I915_READ(reg);
627eb5a3
DV		 2577 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2578 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
8db9d77b
ZW		 2579 temp &= ~FDI_LINK_TRAIN_NONE;
2580 temp |= FDI_LINK_TRAIN_PATTERN_1;
2581 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2582 /* SNB-B */
2583 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2584 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2585
d74cf324
DV		 2586 I915_WRITE(FDI_RX_MISC(pipe),
2587 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2588
5eddb70b
CW		 2589 reg = FDI_RX_CTL(pipe);
2590 temp = I915_READ(reg);
8db9d77b
ZW		 2591 if (HAS_PCH_CPT(dev)) {
2592 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2593 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2594 } else {
2595 temp &= ~FDI_LINK_TRAIN_NONE;
2596 temp |= FDI_LINK_TRAIN_PATTERN_1;
2597 }
5eddb70b
CW		 2598 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2599
2600 POSTING_READ(reg);
8db9d77b
ZW		 2601 udelay(150);
2602
0206e353 2603 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2604 reg = FDI_TX_CTL(pipe);
2605 temp = I915_READ(reg);
8db9d77b
ZW		 2606 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2607 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2608 I915_WRITE(reg, temp);
2609
2610 POSTING_READ(reg);
8db9d77b
ZW		 2611 udelay(500);
2612
fa37d39e
SP		 2613 for (retry = 0; retry < 5; retry++) {
2614 reg = FDI_RX_IIR(pipe);
2615 temp = I915_READ(reg);
2616 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2617 if (temp & FDI_RX_BIT_LOCK) {
2618 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2619 DRM_DEBUG_KMS("FDI train 1 done.\n");
2620 break;
2621 }
2622 udelay(50);
8db9d77b 2623 }
fa37d39e
SP		 2624 if (retry < 5)
2625 break;
8db9d77b
ZW		 2626 }
2627 if (i == 4)
5eddb70b 2628 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2629
2630 /* Train 2 */
5eddb70b
CW		 2631 reg = FDI_TX_CTL(pipe);
2632 temp = I915_READ(reg);
8db9d77b
ZW		 2633 temp &= ~FDI_LINK_TRAIN_NONE;
2634 temp |= FDI_LINK_TRAIN_PATTERN_2;
2635 if (IS_GEN6(dev)) {
2636 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2637 /* SNB-B */
2638 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2639 }
5eddb70b 2640 I915_WRITE(reg, temp);
8db9d77b 2641
5eddb70b
CW		 2642 reg = FDI_RX_CTL(pipe);
2643 temp = I915_READ(reg);
8db9d77b
ZW		 2644 if (HAS_PCH_CPT(dev)) {
2645 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2646 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2647 } else {
2648 temp &= ~FDI_LINK_TRAIN_NONE;
2649 temp |= FDI_LINK_TRAIN_PATTERN_2;
2650 }
5eddb70b
CW		 2651 I915_WRITE(reg, temp);
2652
2653 POSTING_READ(reg);
8db9d77b
ZW		 2654 udelay(150);
2655
0206e353 2656 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2657 reg = FDI_TX_CTL(pipe);
2658 temp = I915_READ(reg);
8db9d77b
ZW		 2659 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2660 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2661 I915_WRITE(reg, temp);
2662
2663 POSTING_READ(reg);
8db9d77b
ZW		 2664 udelay(500);
2665
fa37d39e
SP		 2666 for (retry = 0; retry < 5; retry++) {
2667 reg = FDI_RX_IIR(pipe);
2668 temp = I915_READ(reg);
2669 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2670 if (temp & FDI_RX_SYMBOL_LOCK) {
2671 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2672 DRM_DEBUG_KMS("FDI train 2 done.\n");
2673 break;
2674 }
2675 udelay(50);
8db9d77b 2676 }
fa37d39e
SP		 2677 if (retry < 5)
2678 break;
8db9d77b
ZW		 2679 }
2680 if (i == 4)
5eddb70b 2681 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2682
2683 DRM_DEBUG_KMS("FDI train done.\n");
2684}
2685
357555c0
JB		 2686/* Manual link training for Ivy Bridge A0 parts */
2687static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2688{
2689 struct drm_device *dev = crtc->dev;
2690 struct drm_i915_private *dev_priv = dev->dev_private;
2691 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2692 int pipe = intel_crtc->pipe;
139ccd3f 2693 u32 reg, temp, i, j;
357555c0
JB		 2694
2695 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2696 for train result */
2697 reg = FDI_RX_IMR(pipe);
2698 temp = I915_READ(reg);
2699 temp &= ~FDI_RX_SYMBOL_LOCK;
2700 temp &= ~FDI_RX_BIT_LOCK;
2701 I915_WRITE(reg, temp);
2702
2703 POSTING_READ(reg);
2704 udelay(150);
2705
01a415fd
DV		 2706 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2707 I915_READ(FDI_RX_IIR(pipe)));
2708
139ccd3f
JB		 2709 /* Try each vswing and preemphasis setting twice before moving on */
2710 for (j = 0; j < ARRAY_SIZE(snb_b_fdi_train_param) * 2; j++) {
2711 /* disable first in case we need to retry */
2712 reg = FDI_TX_CTL(pipe);
2713 temp = I915_READ(reg);
2714 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2715 temp &= ~FDI_TX_ENABLE;
2716 I915_WRITE(reg, temp);
357555c0 2717
139ccd3f
JB		 2718 reg = FDI_RX_CTL(pipe);
2719 temp = I915_READ(reg);
2720 temp &= ~FDI_LINK_TRAIN_AUTO;
2721 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2722 temp &= ~FDI_RX_ENABLE;
2723 I915_WRITE(reg, temp);
357555c0 2724
139ccd3f 2725 /* enable CPU FDI TX and PCH FDI RX */
357555c0
JB		 2726 reg = FDI_TX_CTL(pipe);
2727 temp = I915_READ(reg);
139ccd3f
JB		 2728 temp &= ~FDI_DP_PORT_WIDTH_MASK;
2729 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
2730 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
357555c0 2731 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
139ccd3f
JB		 2732 temp |= snb_b_fdi_train_param[j/2];
2733 temp |= FDI_COMPOSITE_SYNC;
2734 I915_WRITE(reg, temp | FDI_TX_ENABLE);
357555c0 2735
139ccd3f
JB		 2736 I915_WRITE(FDI_RX_MISC(pipe),
2737 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
357555c0 2738
139ccd3f 2739 reg = FDI_RX_CTL(pipe);
357555c0 2740 temp = I915_READ(reg);
139ccd3f
JB		 2741 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2742 temp |= FDI_COMPOSITE_SYNC;
2743 I915_WRITE(reg, temp | FDI_RX_ENABLE);
357555c0 2744
139ccd3f
JB		 2745 POSTING_READ(reg);
2746 udelay(1); /* should be 0.5us */
357555c0 2747
139ccd3f
JB		 2748 for (i = 0; i < 4; i++) {
2749 reg = FDI_RX_IIR(pipe);
2750 temp = I915_READ(reg);
2751 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2752
139ccd3f
JB		 2753 if (temp & FDI_RX_BIT_LOCK ||
2754 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2755 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2756 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n",
2757 i);
2758 break;
2759 }
2760 udelay(1); /* should be 0.5us */
2761 }
2762 if (i == 4) {
2763 DRM_DEBUG_KMS("FDI train 1 fail on vswing %d\n", j / 2);
2764 continue;
2765 }
357555c0 2766
139ccd3f 2767 /* Train 2 */
357555c0
JB		 2768 reg = FDI_TX_CTL(pipe);
2769 temp = I915_READ(reg);
139ccd3f
JB		 2770 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2771 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2772 I915_WRITE(reg, temp);
2773
2774 reg = FDI_RX_CTL(pipe);
2775 temp = I915_READ(reg);
2776 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2777 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
357555c0
JB		 2778 I915_WRITE(reg, temp);
2779
2780 POSTING_READ(reg);
139ccd3f 2781 udelay(2); /* should be 1.5us */
357555c0 2782
139ccd3f
JB		 2783 for (i = 0; i < 4; i++) {
2784 reg = FDI_RX_IIR(pipe);
2785 temp = I915_READ(reg);
2786 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
357555c0 2787
139ccd3f
JB		 2788 if (temp & FDI_RX_SYMBOL_LOCK ||
2789 (I915_READ(reg) & FDI_RX_SYMBOL_LOCK)) {
2790 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2791 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n",
2792 i);
2793 goto train_done;
2794 }
2795 udelay(2); /* should be 1.5us */
357555c0 2796 }
139ccd3f
JB		 2797 if (i == 4)
2798 DRM_DEBUG_KMS("FDI train 2 fail on vswing %d\n", j / 2);
357555c0 2799 }
357555c0 2800
139ccd3f 2801train_done:
357555c0
JB		 2802 DRM_DEBUG_KMS("FDI train done.\n");
2803}
2804
88cefb6c 2805static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2806{
88cefb6c 2807 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2808 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2809 int pipe = intel_crtc->pipe;
5eddb70b 2810 u32 reg, temp;
79e53945 2811
c64e311e 2812
c98e9dcf 2813 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2814 reg = FDI_RX_CTL(pipe);
2815 temp = I915_READ(reg);
627eb5a3
DV		 2816 temp &= ~(FDI_DP_PORT_WIDTH_MASK | (0x7 << 16));
2817 temp |= FDI_DP_PORT_WIDTH(intel_crtc->config.fdi_lanes);
dfd07d72 2818 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2819 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2820
2821 POSTING_READ(reg);
c98e9dcf
JB		 2822 udelay(200);
2823
2824 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2825 temp = I915_READ(reg);
2826 I915_WRITE(reg, temp | FDI_PCDCLK);
2827
2828 POSTING_READ(reg);
c98e9dcf
JB		 2829 udelay(200);
2830
20749730
PZ		 2831 /* Enable CPU FDI TX PLL, always on for Ironlake */
2832 reg = FDI_TX_CTL(pipe);
2833 temp = I915_READ(reg);
2834 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2835 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2836
20749730
PZ		 2837 POSTING_READ(reg);
2838 udelay(100);
6be4a607 2839 }
0e23b99d
JB		 2840}
2841
88cefb6c
DV		 2842static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2843{
2844 struct drm_device *dev = intel_crtc->base.dev;
2845 struct drm_i915_private *dev_priv = dev->dev_private;
2846 int pipe = intel_crtc->pipe;
2847 u32 reg, temp;
2848
2849 /* Switch from PCDclk to Rawclk */
2850 reg = FDI_RX_CTL(pipe);
2851 temp = I915_READ(reg);
2852 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2853
2854 /* Disable CPU FDI TX PLL */
2855 reg = FDI_TX_CTL(pipe);
2856 temp = I915_READ(reg);
2857 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2858
2859 POSTING_READ(reg);
2860 udelay(100);
2861
2862 reg = FDI_RX_CTL(pipe);
2863 temp = I915_READ(reg);
2864 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2865
2866 /* Wait for the clocks to turn off. */
2867 POSTING_READ(reg);
2868 udelay(100);
2869}
2870
0fc932b8
JB		 2871static void ironlake_fdi_disable(struct drm_crtc *crtc)
2872{
2873 struct drm_device *dev = crtc->dev;
2874 struct drm_i915_private *dev_priv = dev->dev_private;
2875 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2876 int pipe = intel_crtc->pipe;
2877 u32 reg, temp;
2878
2879 /* disable CPU FDI tx and PCH FDI rx */
2880 reg = FDI_TX_CTL(pipe);
2881 temp = I915_READ(reg);
2882 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2883 POSTING_READ(reg);
2884
2885 reg = FDI_RX_CTL(pipe);
2886 temp = I915_READ(reg);
2887 temp &= ~(0x7 << 16);
dfd07d72 2888 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2889 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2890
2891 POSTING_READ(reg);
2892 udelay(100);
2893
2894 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2895 if (HAS_PCH_IBX(dev)) {
2896 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2897 }
0fc932b8
JB		 2898
2899 /* still set train pattern 1 */
2900 reg = FDI_TX_CTL(pipe);
2901 temp = I915_READ(reg);
2902 temp &= ~FDI_LINK_TRAIN_NONE;
2903 temp |= FDI_LINK_TRAIN_PATTERN_1;
2904 I915_WRITE(reg, temp);
2905
2906 reg = FDI_RX_CTL(pipe);
2907 temp = I915_READ(reg);
2908 if (HAS_PCH_CPT(dev)) {
2909 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2910 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2911 } else {
2912 temp &= ~FDI_LINK_TRAIN_NONE;
2913 temp |= FDI_LINK_TRAIN_PATTERN_1;
2914 }
2915 /* BPC in FDI rx is consistent with that in PIPECONF */
2916 temp &= ~(0x07 << 16);
dfd07d72 2917 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2918 I915_WRITE(reg, temp);
2919
2920 POSTING_READ(reg);
2921 udelay(100);
2922}
2923
5bb61643
CW		 2924static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2925{
2926 struct drm_device *dev = crtc->dev;
2927 struct drm_i915_private *dev_priv = dev->dev_private;
10d83730 2928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5bb61643
CW		 2929 unsigned long flags;
2930 bool pending;
2931
10d83730
VS		 2932 if (i915_reset_in_progress(&dev_priv->gpu_error) ||
2933 intel_crtc->reset_counter != atomic_read(&dev_priv->gpu_error.reset_counter))
5bb61643
CW		 2934 return false;
2935
2936 spin_lock_irqsave(&dev->event_lock, flags);
2937 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2938 spin_unlock_irqrestore(&dev->event_lock, flags);
2939
2940 return pending;
2941}
2942
e6c3a2a6
CW		 2943static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2944{
0f91128d 2945 struct drm_device *dev = crtc->dev;
5bb61643 2946 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2947
2948 if (crtc->fb == NULL)
2949 return;
2950
2c10d571
DV		 2951 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2952
5bb61643
CW		 2953 wait_event(dev_priv->pending_flip_queue,
2954 !intel_crtc_has_pending_flip(crtc));
2955
0f91128d
CW		 2956 mutex_lock(&dev->struct_mutex);
2957 intel_finish_fb(crtc->fb);
2958 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2959}
2960
e615efe4
ED		 2961/* Program iCLKIP clock to the desired frequency */
2962static void lpt_program_iclkip(struct drm_crtc *crtc)
2963{
2964 struct drm_device *dev = crtc->dev;
2965 struct drm_i915_private *dev_priv = dev->dev_private;
241bfc38 2966 int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
e615efe4
ED		 2967 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2968 u32 temp;
2969
09153000
DV		 2970 mutex_lock(&dev_priv->dpio_lock);
2971
e615efe4
ED		 2972 /* It is necessary to ungate the pixclk gate prior to programming
2973 * the divisors, and gate it back when it is done.
2974 */
2975 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2976
2977 /* Disable SSCCTL */
2978 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2979 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2980 SBI_SSCCTL_DISABLE,
2981 SBI_ICLK);
e615efe4
ED		 2982
2983 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
12d7ceed 2984 if (clock == 20000) {
e615efe4
ED		 2985 auxdiv = 1;
2986 divsel = 0x41;
2987 phaseinc = 0x20;
2988 } else {
2989 /* The iCLK virtual clock root frequency is in MHz,
241bfc38
DL		 2990 * but the adjusted_mode->crtc_clock in in KHz. To get the
2991 * divisors, it is necessary to divide one by another, so we
e615efe4
ED		 2992 * convert the virtual clock precision to KHz here for higher
2993 * precision.
2994 */
2995 u32 iclk_virtual_root_freq = 172800 * 1000;
2996 u32 iclk_pi_range = 64;
2997 u32 desired_divisor, msb_divisor_value, pi_value;
2998
12d7ceed 2999 desired_divisor = (iclk_virtual_root_freq / clock);
e615efe4
ED		 3000 msb_divisor_value = desired_divisor / iclk_pi_range;
3001 pi_value = desired_divisor % iclk_pi_range;
3002
3003 auxdiv = 0;
3004 divsel = msb_divisor_value - 2;
3005 phaseinc = pi_value;
3006 }
3007
3008 /* This should not happen with any sane values */
3009 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3010 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3011 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3012 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3013
3014 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
12d7ceed 3015 clock,
e615efe4
ED		 3016 auxdiv,
3017 divsel,
3018 phasedir,
3019 phaseinc);
3020
3021 /* Program SSCDIVINTPHASE6 */
988d6ee8 3022 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 3023 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3024 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3025 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3026 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3027 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3028 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3029 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3030
3031 /* Program SSCAUXDIV */
988d6ee8 3032 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3033 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3034 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3035 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3036
3037 /* Enable modulator and associated divider */
988d6ee8 3038 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3039 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3040 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3041
3042 /* Wait for initialization time */
3043 udelay(24);
3044
3045 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3046
3047 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3048}
3049
275f01b2
DV		 3050static void ironlake_pch_transcoder_set_timings(struct intel_crtc *crtc,
3051 enum pipe pch_transcoder)
3052{
3053 struct drm_device *dev = crtc->base.dev;
3054 struct drm_i915_private *dev_priv = dev->dev_private;
3055 enum transcoder cpu_transcoder = crtc->config.cpu_transcoder;
3056
3057 I915_WRITE(PCH_TRANS_HTOTAL(pch_transcoder),
3058 I915_READ(HTOTAL(cpu_transcoder)));
3059 I915_WRITE(PCH_TRANS_HBLANK(pch_transcoder),
3060 I915_READ(HBLANK(cpu_transcoder)));
3061 I915_WRITE(PCH_TRANS_HSYNC(pch_transcoder),
3062 I915_READ(HSYNC(cpu_transcoder)));
3063
3064 I915_WRITE(PCH_TRANS_VTOTAL(pch_transcoder),
3065 I915_READ(VTOTAL(cpu_transcoder)));
3066 I915_WRITE(PCH_TRANS_VBLANK(pch_transcoder),
3067 I915_READ(VBLANK(cpu_transcoder)));
3068 I915_WRITE(PCH_TRANS_VSYNC(pch_transcoder),
3069 I915_READ(VSYNC(cpu_transcoder)));
3070 I915_WRITE(PCH_TRANS_VSYNCSHIFT(pch_transcoder),
3071 I915_READ(VSYNCSHIFT(cpu_transcoder)));
3072}
3073
f67a559d
JB		 3074/*
3075 * Enable PCH resources required for PCH ports:
3076 * - PCH PLLs
3077 * - FDI training & RX/TX
3078 * - update transcoder timings
3079 * - DP transcoding bits
3080 * - transcoder
3081 */
3082static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3083{
3084 struct drm_device *dev = crtc->dev;
3085 struct drm_i915_private *dev_priv = dev->dev_private;
3086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3087 int pipe = intel_crtc->pipe;
ee7b9f93 3088 u32 reg, temp;
2c07245f 3089
ab9412ba 3090 assert_pch_transcoder_disabled(dev_priv, pipe);
e7e164db 3091
cd986abb
DV		 3092 /* Write the TU size bits before fdi link training, so that error
3093 * detection works. */
3094 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3095 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3096
c98e9dcf 3097 /* For PCH output, training FDI link */
674cf967 3098 dev_priv->display.fdi_link_train(crtc);
2c07245f 3099
3ad8a208
DV		 3100 /* We need to program the right clock selection before writing the pixel
3101 * mutliplier into the DPLL. */
303b81e0 3102 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3103 u32 sel;
4b645f14 3104
c98e9dcf 3105 temp = I915_READ(PCH_DPLL_SEL);
11887397
DV		 3106 temp |= TRANS_DPLL_ENABLE(pipe);
3107 sel = TRANS_DPLLB_SEL(pipe);
a43f6e0f 3108 if (intel_crtc->config.shared_dpll == DPLL_ID_PCH_PLL_B)
ee7b9f93
JB		 3109 temp |= sel;
3110 else
3111 temp &= ~sel;
c98e9dcf 3112 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3113 }
5eddb70b 3114
3ad8a208
DV		 3115 /* XXX: pch pll's can be enabled any time before we enable the PCH
3116 * transcoder, and we actually should do this to not upset any PCH
3117 * transcoder that already use the clock when we share it.
3118 *
3119 * Note that enable_shared_dpll tries to do the right thing, but
3120 * get_shared_dpll unconditionally resets the pll - we need that to have
3121 * the right LVDS enable sequence. */
3122 ironlake_enable_shared_dpll(intel_crtc);
3123
d9b6cb56
JB		 3124 /* set transcoder timing, panel must allow it */
3125 assert_panel_unlocked(dev_priv, pipe);
275f01b2 3126 ironlake_pch_transcoder_set_timings(intel_crtc, pipe);
8db9d77b 3127
303b81e0 3128 intel_fdi_normal_train(crtc);
5e84e1a4 3129
c98e9dcf
JB		 3130 /* For PCH DP, enable TRANS_DP_CTL */
3131 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3132 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3133 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3134 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3135 reg = TRANS_DP_CTL(pipe);
3136 temp = I915_READ(reg);
3137 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3138 TRANS_DP_SYNC_MASK |
3139 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3140 temp |= (TRANS_DP_OUTPUT_ENABLE |
3141 TRANS_DP_ENH_FRAMING);
9325c9f0 3142 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3143
3144 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3145 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3146 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3147 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3148
3149 switch (intel_trans_dp_port_sel(crtc)) {
3150 case PCH_DP_B:
5eddb70b 3151 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3152 break;
3153 case PCH_DP_C:
5eddb70b 3154 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3155 break;
3156 case PCH_DP_D:
5eddb70b 3157 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3158 break;
3159 default:
e95d41e1 3160 BUG();
32f9d658 3161 }
2c07245f 3162
5eddb70b 3163 I915_WRITE(reg, temp);
6be4a607 3164 }
b52eb4dc 3165
b8a4f404 3166 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3167}
3168
1507e5bd
PZ		 3169static void lpt_pch_enable(struct drm_crtc *crtc)
3170{
3171 struct drm_device *dev = crtc->dev;
3172 struct drm_i915_private *dev_priv = dev->dev_private;
3173 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 3174 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
1507e5bd 3175
ab9412ba 3176 assert_pch_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3177
8c52b5e8 3178 lpt_program_iclkip(crtc);
1507e5bd 3179
0540e488 3180 /* Set transcoder timing. */
275f01b2 3181 ironlake_pch_transcoder_set_timings(intel_crtc, PIPE_A);
1507e5bd 3182
937bb610 3183 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3184}
3185
e2b78267 3186static void intel_put_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3187{
e2b78267 3188 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
ee7b9f93
JB		 3189
3190 if (pll == NULL)
3191 return;
3192
3193 if (pll->refcount == 0) {
46edb027 3194 WARN(1, "bad %s refcount\n", pll->name);
ee7b9f93
JB		 3195 return;
3196 }
3197
f4a091c7
DV		 3198 if (--pll->refcount == 0) {
3199 WARN_ON(pll->on);
3200 WARN_ON(pll->active);
3201 }
3202
a43f6e0f 3203 crtc->config.shared_dpll = DPLL_ID_PRIVATE;
ee7b9f93
JB		 3204}
3205
b89a1d39 3206static struct intel_shared_dpll *intel_get_shared_dpll(struct intel_crtc *crtc)
ee7b9f93 3207{
e2b78267
DV		 3208 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3209 struct intel_shared_dpll *pll = intel_crtc_to_shared_dpll(crtc);
3210 enum intel_dpll_id i;
ee7b9f93 3211
ee7b9f93 3212 if (pll) {
46edb027
DV		 3213 DRM_DEBUG_KMS("CRTC:%d dropping existing %s\n",
3214 crtc->base.base.id, pll->name);
e2b78267 3215 intel_put_shared_dpll(crtc);
ee7b9f93
JB		 3216 }
3217
98b6bd99
DV		 3218 if (HAS_PCH_IBX(dev_priv->dev)) {
3219 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
d94ab068 3220 i = (enum intel_dpll_id) crtc->pipe;
e72f9fbf 3221 pll = &dev_priv->shared_dplls[i];
98b6bd99 3222
46edb027
DV		 3223 DRM_DEBUG_KMS("CRTC:%d using pre-allocated %s\n",
3224 crtc->base.base.id, pll->name);
98b6bd99
DV		 3225
3226 goto found;
3227 }
3228
e72f9fbf
DV		 3229 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3230 pll = &dev_priv->shared_dplls[i];
ee7b9f93
JB		 3231
3232 /* Only want to check enabled timings first */
3233 if (pll->refcount == 0)
3234 continue;
3235
b89a1d39
DV		 3236 if (memcmp(&crtc->config.dpll_hw_state, &pll->hw_state,
3237 sizeof(pll->hw_state)) == 0) {
46edb027 3238 DRM_DEBUG_KMS("CRTC:%d sharing existing %s (refcount %d, ative %d)\n",
e2b78267 3239 crtc->base.base.id,
46edb027 3240 pll->name, pll->refcount, pll->active);
ee7b9f93
JB		 3241
3242 goto found;
3243 }
3244 }
3245
3246 /* Ok no matching timings, maybe there's a free one? */
e72f9fbf
DV		 3247 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
3248 pll = &dev_priv->shared_dplls[i];
ee7b9f93 3249 if (pll->refcount == 0) {
46edb027
DV		 3250 DRM_DEBUG_KMS("CRTC:%d allocated %s\n",
3251 crtc->base.base.id, pll->name);
ee7b9f93
JB		 3252 goto found;
3253 }
3254 }
3255
3256 return NULL;
3257
3258found:
a43f6e0f 3259 crtc->config.shared_dpll = i;
46edb027
DV		 3260 DRM_DEBUG_DRIVER("using %s for pipe %c\n", pll->name,
3261 pipe_name(crtc->pipe));
ee7b9f93 3262
cdbd2316 3263 if (pll->active == 0) {
66e985c0
DV		 3264 memcpy(&pll->hw_state, &crtc->config.dpll_hw_state,
3265 sizeof(pll->hw_state));
3266
46edb027 3267 DRM_DEBUG_DRIVER("setting up %s\n", pll->name);
cdbd2316 3268 WARN_ON(pll->on);
e9d6944e 3269 assert_shared_dpll_disabled(dev_priv, pll);
ee7b9f93 3270
15bdd4cf 3271 pll->mode_set(dev_priv, pll);
cdbd2316
DV		 3272 }
3273 pll->refcount++;
e04c7350 3274
ee7b9f93
JB		 3275 return pll;
3276}
3277
a1520318 3278static void cpt_verify_modeset(struct drm_device *dev, int pipe)
d4270e57
JB		 3279{
3280 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3281 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3282 u32 temp;
3283
3284 temp = I915_READ(dslreg);
3285 udelay(500);
3286 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57 3287 if (wait_for(I915_READ(dslreg) != temp, 5))
84f44ce7 3288 DRM_ERROR("mode set failed: pipe %c stuck\n", pipe_name(pipe));
d4270e57
JB		 3289 }
3290}
3291
b074cec8
JB		 3292static void ironlake_pfit_enable(struct intel_crtc *crtc)
3293{
3294 struct drm_device *dev = crtc->base.dev;
3295 struct drm_i915_private *dev_priv = dev->dev_private;
3296 int pipe = crtc->pipe;
3297
fd4daa9c 3298 if (crtc->config.pch_pfit.enabled) {
b074cec8
JB		 3299 /* Force use of hard-coded filter coefficients
3300 * as some pre-programmed values are broken,
3301 * e.g. x201.
3302 */
3303 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
3304 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3305 PF_PIPE_SEL_IVB(pipe));
3306 else
3307 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3308 I915_WRITE(PF_WIN_POS(pipe), crtc->config.pch_pfit.pos);
3309 I915_WRITE(PF_WIN_SZ(pipe), crtc->config.pch_pfit.size);
d4270e57
JB		 3310 }
3311}
3312
bb53d4ae
VS		 3313static void intel_enable_planes(struct drm_crtc *crtc)
3314{
3315 struct drm_device *dev = crtc->dev;
3316 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3317 struct intel_plane *intel_plane;
3318
3319 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3320 if (intel_plane->pipe == pipe)
3321 intel_plane_restore(&intel_plane->base);
3322}
3323
3324static void intel_disable_planes(struct drm_crtc *crtc)
3325{
3326 struct drm_device *dev = crtc->dev;
3327 enum pipe pipe = to_intel_crtc(crtc)->pipe;
3328 struct intel_plane *intel_plane;
3329
3330 list_for_each_entry(intel_plane, &dev->mode_config.plane_list, base.head)
3331 if (intel_plane->pipe == pipe)
3332 intel_plane_disable(&intel_plane->base);
3333}
3334
d77e4531
PZ		 3335static void hsw_enable_ips(struct intel_crtc *crtc)
3336{
3337 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
3338
3339 if (!crtc->config.ips_enabled)
3340 return;
3341
3342 /* We can only enable IPS after we enable a plane and wait for a vblank.
3343 * We guarantee that the plane is enabled by calling intel_enable_ips
3344 * only after intel_enable_plane. And intel_enable_plane already waits
3345 * for a vblank, so all we need to do here is to enable the IPS bit. */
3346 assert_plane_enabled(dev_priv, crtc->plane);
3347 I915_WRITE(IPS_CTL, IPS_ENABLE);
3348}
3349
3350static void hsw_disable_ips(struct intel_crtc *crtc)
3351{
3352 struct drm_device *dev = crtc->base.dev;
3353 struct drm_i915_private *dev_priv = dev->dev_private;
3354
3355 if (!crtc->config.ips_enabled)
3356 return;
3357
3358 assert_plane_enabled(dev_priv, crtc->plane);
3359 I915_WRITE(IPS_CTL, 0);
3360 POSTING_READ(IPS_CTL);
3361
3362 /* We need to wait for a vblank before we can disable the plane. */
3363 intel_wait_for_vblank(dev, crtc->pipe);
3364}
3365
3366/** Loads the palette/gamma unit for the CRTC with the prepared values */
3367static void intel_crtc_load_lut(struct drm_crtc *crtc)
3368{
3369 struct drm_device *dev = crtc->dev;
3370 struct drm_i915_private *dev_priv = dev->dev_private;
3371 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3372 enum pipe pipe = intel_crtc->pipe;
3373 int palreg = PALETTE(pipe);
3374 int i;
3375 bool reenable_ips = false;
3376
3377 /* The clocks have to be on to load the palette. */
3378 if (!crtc->enabled || !intel_crtc->active)
3379 return;
3380
3381 if (!HAS_PCH_SPLIT(dev_priv->dev)) {
3382 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3383 assert_dsi_pll_enabled(dev_priv);
3384 else
3385 assert_pll_enabled(dev_priv, pipe);
3386 }
3387
3388 /* use legacy palette for Ironlake */
3389 if (HAS_PCH_SPLIT(dev))
3390 palreg = LGC_PALETTE(pipe);
3391
3392 /* Workaround : Do not read or write the pipe palette/gamma data while
3393 * GAMMA_MODE is configured for split gamma and IPS_CTL has IPS enabled.
3394 */
3395 if (intel_crtc->config.ips_enabled &&
3396 ((I915_READ(GAMMA_MODE(pipe)) & GAMMA_MODE_MODE_MASK) ==
3397 GAMMA_MODE_MODE_SPLIT)) {
3398 hsw_disable_ips(intel_crtc);
3399 reenable_ips = true;
3400 }
3401
3402 for (i = 0; i < 256; i++) {
3403 I915_WRITE(palreg + 4 * i,
3404 (intel_crtc->lut_r[i] << 16) |
3405 (intel_crtc->lut_g[i] << 8) |
3406 intel_crtc->lut_b[i]);
3407 }
3408
3409 if (reenable_ips)
3410 hsw_enable_ips(intel_crtc);
3411}
3412
f67a559d
JB		 3413static void ironlake_crtc_enable(struct drm_crtc *crtc)
3414{
3415 struct drm_device *dev = crtc->dev;
3416 struct drm_i915_private *dev_priv = dev->dev_private;
3417 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3418 struct intel_encoder *encoder;
f67a559d
JB		 3419 int pipe = intel_crtc->pipe;
3420 int plane = intel_crtc->plane;
f67a559d 3421
08a48469
DV		 3422 WARN_ON(!crtc->enabled);
3423
f67a559d
JB		 3424 if (intel_crtc->active)
3425 return;
3426
3427 intel_crtc->active = true;
8664281b
PZ		 3428
3429 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3430 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
3431
f6736a1a 3432 for_each_encoder_on_crtc(dev, crtc, encoder)
952735ee
DV		 3433 if (encoder->pre_enable)
3434 encoder->pre_enable(encoder);
f67a559d 3435
5bfe2ac0 3436 if (intel_crtc->config.has_pch_encoder) {
fff367c7
DV		 3437 /* Note: FDI PLL enabling _must_ be done before we enable the
3438 * cpu pipes, hence this is separate from all the other fdi/pch
3439 * enabling. */
88cefb6c 3440 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3441 } else {
3442 assert_fdi_tx_disabled(dev_priv, pipe);
3443 assert_fdi_rx_disabled(dev_priv, pipe);
3444 }
f67a559d 3445
b074cec8 3446 ironlake_pfit_enable(intel_crtc);
f67a559d 3447
9c54c0dd
JB		 3448 /*
3449 * On ILK+ LUT must be loaded before the pipe is running but with
3450 * clocks enabled
3451 */
3452 intel_crtc_load_lut(crtc);
3453
f37fcc2a 3454 intel_update_watermarks(crtc);
5bfe2ac0 3455 intel_enable_pipe(dev_priv, pipe,
23538ef1 3456 intel_crtc->config.has_pch_encoder, false);
f67a559d 3457 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3458 intel_enable_planes(crtc);
5c38d48c 3459 intel_crtc_update_cursor(crtc, true);
f67a559d 3460
5bfe2ac0 3461 if (intel_crtc->config.has_pch_encoder)
f67a559d 3462 ironlake_pch_enable(crtc);
c98e9dcf 3463
d1ebd816 3464 mutex_lock(&dev->struct_mutex);
bed4a673 3465 intel_update_fbc(dev);
d1ebd816
BW		 3466 mutex_unlock(&dev->struct_mutex);
3467
fa5c73b1
DV		 3468 for_each_encoder_on_crtc(dev, crtc, encoder)
3469 encoder->enable(encoder);
61b77ddd
DV		 3470
3471 if (HAS_PCH_CPT(dev))
a1520318 3472 cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3473
3474 /*
3475 * There seems to be a race in PCH platform hw (at least on some
3476 * outputs) where an enabled pipe still completes any pageflip right
3477 * away (as if the pipe is off) instead of waiting for vblank. As soon
3478 * as the first vblank happend, everything works as expected. Hence just
3479 * wait for one vblank before returning to avoid strange things
3480 * happening.
3481 */
3482 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3483}
3484
42db64ef
PZ		 3485/* IPS only exists on ULT machines and is tied to pipe A. */
3486static bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
3487{
f5adf94e 3488 return HAS_IPS(crtc->base.dev) && crtc->pipe == PIPE_A;
42db64ef
PZ		 3489}
3490
dda9a66a
VS		 3491static void haswell_crtc_enable_planes(struct drm_crtc *crtc)
3492{
3493 struct drm_device *dev = crtc->dev;
3494 struct drm_i915_private *dev_priv = dev->dev_private;
3495 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3496 int pipe = intel_crtc->pipe;
3497 int plane = intel_crtc->plane;
3498
3499 intel_enable_plane(dev_priv, plane, pipe);
3500 intel_enable_planes(crtc);
3501 intel_crtc_update_cursor(crtc, true);
3502
3503 hsw_enable_ips(intel_crtc);
3504
3505 mutex_lock(&dev->struct_mutex);
3506 intel_update_fbc(dev);
3507 mutex_unlock(&dev->struct_mutex);
3508}
3509
3510static void haswell_crtc_disable_planes(struct drm_crtc *crtc)
3511{
3512 struct drm_device *dev = crtc->dev;
3513 struct drm_i915_private *dev_priv = dev->dev_private;
3514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3515 int pipe = intel_crtc->pipe;
3516 int plane = intel_crtc->plane;
3517
3518 intel_crtc_wait_for_pending_flips(crtc);
3519 drm_vblank_off(dev, pipe);
3520
3521 /* FBC must be disabled before disabling the plane on HSW. */
3522 if (dev_priv->fbc.plane == plane)
3523 intel_disable_fbc(dev);
3524
3525 hsw_disable_ips(intel_crtc);
3526
3527 intel_crtc_update_cursor(crtc, false);
3528 intel_disable_planes(crtc);
3529 intel_disable_plane(dev_priv, plane, pipe);
3530}
3531
e4916946
PZ		 3532/*
3533 * This implements the workaround described in the "notes" section of the mode
3534 * set sequence documentation. When going from no pipes or single pipe to
3535 * multiple pipes, and planes are enabled after the pipe, we need to wait at
3536 * least 2 vblanks on the first pipe before enabling planes on the second pipe.
3537 */
3538static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc)
3539{
3540 struct drm_device *dev = crtc->base.dev;
3541 struct intel_crtc *crtc_it, *other_active_crtc = NULL;
3542
3543 /* We want to get the other_active_crtc only if there's only 1 other
3544 * active crtc. */
3545 list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) {
3546 if (!crtc_it->active || crtc_it == crtc)
3547 continue;
3548
3549 if (other_active_crtc)
3550 return;
3551
3552 other_active_crtc = crtc_it;
3553 }
3554 if (!other_active_crtc)
3555 return;
3556
3557 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3558 intel_wait_for_vblank(dev, other_active_crtc->pipe);
3559}
3560
4f771f10
PZ		 3561static void haswell_crtc_enable(struct drm_crtc *crtc)
3562{
3563 struct drm_device *dev = crtc->dev;
3564 struct drm_i915_private *dev_priv = dev->dev_private;
3565 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3566 struct intel_encoder *encoder;
3567 int pipe = intel_crtc->pipe;
4f771f10
PZ		 3568
3569 WARN_ON(!crtc->enabled);
3570
3571 if (intel_crtc->active)
3572 return;
3573
3574 intel_crtc->active = true;
8664281b
PZ		 3575
3576 intel_set_cpu_fifo_underrun_reporting(dev, pipe, true);
3577 if (intel_crtc->config.has_pch_encoder)
3578 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
3579
5bfe2ac0 3580 if (intel_crtc->config.has_pch_encoder)
04945641 3581 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3582
3583 for_each_encoder_on_crtc(dev, crtc, encoder)
3584 if (encoder->pre_enable)
3585 encoder->pre_enable(encoder);
3586
1f544388 3587 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3588
b074cec8 3589 ironlake_pfit_enable(intel_crtc);
4f771f10
PZ		 3590
3591 /*
3592 * On ILK+ LUT must be loaded before the pipe is running but with
3593 * clocks enabled
3594 */
3595 intel_crtc_load_lut(crtc);
3596
1f544388 3597 intel_ddi_set_pipe_settings(crtc);
8228c251 3598 intel_ddi_enable_transcoder_func(crtc);
4f771f10 3599
f37fcc2a 3600 intel_update_watermarks(crtc);
5bfe2ac0 3601 intel_enable_pipe(dev_priv, pipe,
23538ef1 3602 intel_crtc->config.has_pch_encoder, false);
42db64ef 3603
5bfe2ac0 3604 if (intel_crtc->config.has_pch_encoder)
1507e5bd 3605 lpt_pch_enable(crtc);
4f771f10 3606
8807e55b 3607 for_each_encoder_on_crtc(dev, crtc, encoder) {
4f771f10 3608 encoder->enable(encoder);
8807e55b
JN		 3609 intel_opregion_notify_encoder(encoder, true);
3610 }
4f771f10 3611
e4916946
PZ		 3612 /* If we change the relative order between pipe/planes enabling, we need
3613 * to change the workaround. */
3614 haswell_mode_set_planes_workaround(intel_crtc);
dda9a66a
VS		 3615 haswell_crtc_enable_planes(crtc);
3616
4f771f10
PZ		 3617 /*
3618 * There seems to be a race in PCH platform hw (at least on some
3619 * outputs) where an enabled pipe still completes any pageflip right
3620 * away (as if the pipe is off) instead of waiting for vblank. As soon
3621 * as the first vblank happend, everything works as expected. Hence just
3622 * wait for one vblank before returning to avoid strange things
3623 * happening.
3624 */
3625 intel_wait_for_vblank(dev, intel_crtc->pipe);
3626}
3627
3f8dce3a
DV		 3628static void ironlake_pfit_disable(struct intel_crtc *crtc)
3629{
3630 struct drm_device *dev = crtc->base.dev;
3631 struct drm_i915_private *dev_priv = dev->dev_private;
3632 int pipe = crtc->pipe;
3633
3634 /* To avoid upsetting the power well on haswell only disable the pfit if
3635 * it's in use. The hw state code will make sure we get this right. */
fd4daa9c 3636 if (crtc->config.pch_pfit.enabled) {
3f8dce3a
DV		 3637 I915_WRITE(PF_CTL(pipe), 0);
3638 I915_WRITE(PF_WIN_POS(pipe), 0);
3639 I915_WRITE(PF_WIN_SZ(pipe), 0);
3640 }
3641}
3642
6be4a607
JB		 3643static void ironlake_crtc_disable(struct drm_crtc *crtc)
3644{
3645 struct drm_device *dev = crtc->dev;
3646 struct drm_i915_private *dev_priv = dev->dev_private;
3647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3648 struct intel_encoder *encoder;
6be4a607
JB		 3649 int pipe = intel_crtc->pipe;
3650 int plane = intel_crtc->plane;
5eddb70b 3651 u32 reg, temp;
b52eb4dc 3652
ef9c3aee 3653
f7abfe8b
CW		 3654 if (!intel_crtc->active)
3655 return;
3656
ea9d758d
DV		 3657 for_each_encoder_on_crtc(dev, crtc, encoder)
3658 encoder->disable(encoder);
3659
e6c3a2a6 3660 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3661 drm_vblank_off(dev, pipe);
913d8d11 3662
5c3fe8b0 3663 if (dev_priv->fbc.plane == plane)
973d04f9 3664 intel_disable_fbc(dev);
2c07245f 3665
0d5b8c61 3666 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3667 intel_disable_planes(crtc);
0d5b8c61
VS		 3668 intel_disable_plane(dev_priv, plane, pipe);
3669
d925c59a
DV		 3670 if (intel_crtc->config.has_pch_encoder)
3671 intel_set_pch_fifo_underrun_reporting(dev, pipe, false);
3672
b24e7179 3673 intel_disable_pipe(dev_priv, pipe);
32f9d658 3674
3f8dce3a 3675 ironlake_pfit_disable(intel_crtc);
2c07245f 3676
bf49ec8c
DV		 3677 for_each_encoder_on_crtc(dev, crtc, encoder)
3678 if (encoder->post_disable)
3679 encoder->post_disable(encoder);
2c07245f 3680
d925c59a
DV		 3681 if (intel_crtc->config.has_pch_encoder) {
3682 ironlake_fdi_disable(crtc);
913d8d11 3683
d925c59a
DV		 3684 ironlake_disable_pch_transcoder(dev_priv, pipe);
3685 intel_set_pch_fifo_underrun_reporting(dev, pipe, true);
6be4a607 3686
d925c59a
DV		 3687 if (HAS_PCH_CPT(dev)) {
3688 /* disable TRANS_DP_CTL */
3689 reg = TRANS_DP_CTL(pipe);
3690 temp = I915_READ(reg);
3691 temp &= ~(TRANS_DP_OUTPUT_ENABLE |
3692 TRANS_DP_PORT_SEL_MASK);
3693 temp |= TRANS_DP_PORT_SEL_NONE;
3694 I915_WRITE(reg, temp);
3695
3696 /* disable DPLL_SEL */
3697 temp = I915_READ(PCH_DPLL_SEL);
11887397 3698 temp &= ~(TRANS_DPLL_ENABLE(pipe) | TRANS_DPLLB_SEL(pipe));
d925c59a 3699 I915_WRITE(PCH_DPLL_SEL, temp);
9db4a9c7 3700 }
e3421a18 3701
d925c59a 3702 /* disable PCH DPLL */
e72f9fbf 3703 intel_disable_shared_dpll(intel_crtc);
8db9d77b 3704
d925c59a
DV		 3705 ironlake_fdi_pll_disable(intel_crtc);
3706 }
6b383a7f 3707
f7abfe8b 3708 intel_crtc->active = false;
46ba614c 3709 intel_update_watermarks(crtc);
d1ebd816
BW		 3710
3711 mutex_lock(&dev->struct_mutex);
6b383a7f 3712 intel_update_fbc(dev);
d1ebd816 3713 mutex_unlock(&dev->struct_mutex);
6be4a607 3714}
1b3c7a47 3715
4f771f10 3716static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3717{
4f771f10
PZ		 3718 struct drm_device *dev = crtc->dev;
3719 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3720 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3721 struct intel_encoder *encoder;
3722 int pipe = intel_crtc->pipe;
3b117c8f 3723 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee7b9f93 3724
4f771f10
PZ		 3725 if (!intel_crtc->active)
3726 return;
3727
dda9a66a
VS		 3728 haswell_crtc_disable_planes(crtc);
3729
8807e55b
JN		 3730 for_each_encoder_on_crtc(dev, crtc, encoder) {
3731 intel_opregion_notify_encoder(encoder, false);
4f771f10 3732 encoder->disable(encoder);
8807e55b 3733 }
4f771f10 3734
8664281b
PZ		 3735 if (intel_crtc->config.has_pch_encoder)
3736 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, false);
4f771f10
PZ		 3737 intel_disable_pipe(dev_priv, pipe);
3738
ad80a810 3739 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10 3740
3f8dce3a 3741 ironlake_pfit_disable(intel_crtc);
4f771f10 3742
1f544388 3743 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3744
3745 for_each_encoder_on_crtc(dev, crtc, encoder)
3746 if (encoder->post_disable)
3747 encoder->post_disable(encoder);
3748
88adfff1 3749 if (intel_crtc->config.has_pch_encoder) {
ab4d966c 3750 lpt_disable_pch_transcoder(dev_priv);
8664281b 3751 intel_set_pch_fifo_underrun_reporting(dev, TRANSCODER_A, true);
1ad960f2 3752 intel_ddi_fdi_disable(crtc);
83616634 3753 }
4f771f10
PZ		 3754
3755 intel_crtc->active = false;
46ba614c 3756 intel_update_watermarks(crtc);
4f771f10
PZ		 3757
3758 mutex_lock(&dev->struct_mutex);
3759 intel_update_fbc(dev);
3760 mutex_unlock(&dev->struct_mutex);
3761}
3762
ee7b9f93
JB		 3763static void ironlake_crtc_off(struct drm_crtc *crtc)
3764{
3765 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
e72f9fbf 3766 intel_put_shared_dpll(intel_crtc);
ee7b9f93
JB		 3767}
3768
6441ab5f
PZ		 3769static void haswell_crtc_off(struct drm_crtc *crtc)
3770{
3771 intel_ddi_put_crtc_pll(crtc);
3772}
3773
02e792fb
DV		 3774static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3775{
02e792fb 3776 if (!enable && intel_crtc->overlay) {
23f09ce3 3777 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3778 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3779
23f09ce3 3780 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3781 dev_priv->mm.interruptible = false;
3782 (void) intel_overlay_switch_off(intel_crtc->overlay);
3783 dev_priv->mm.interruptible = true;
23f09ce3 3784 mutex_unlock(&dev->struct_mutex);
02e792fb 3785 }
02e792fb 3786
5dcdbcb0
CW		 3787 /* Let userspace switch the overlay on again. In most cases userspace
3788 * has to recompute where to put it anyway.
3789 */
02e792fb
DV		 3790}
3791
61bc95c1
EE		 3792/**
3793 * i9xx_fixup_plane - ugly workaround for G45 to fire up the hardware
3794 * cursor plane briefly if not already running after enabling the display
3795 * plane.
3796 * This workaround avoids occasional blank screens when self refresh is
3797 * enabled.
3798 */
3799static void
3800g4x_fixup_plane(struct drm_i915_private *dev_priv, enum pipe pipe)
3801{
3802 u32 cntl = I915_READ(CURCNTR(pipe));
3803
3804 if ((cntl & CURSOR_MODE) == 0) {
3805 u32 fw_bcl_self = I915_READ(FW_BLC_SELF);
3806
3807 I915_WRITE(FW_BLC_SELF, fw_bcl_self & ~FW_BLC_SELF_EN);
3808 I915_WRITE(CURCNTR(pipe), CURSOR_MODE_64_ARGB_AX);
3809 intel_wait_for_vblank(dev_priv->dev, pipe);
3810 I915_WRITE(CURCNTR(pipe), cntl);
3811 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3812 I915_WRITE(FW_BLC_SELF, fw_bcl_self);
3813 }
3814}
3815
2dd24552
JB		 3816static void i9xx_pfit_enable(struct intel_crtc *crtc)
3817{
3818 struct drm_device *dev = crtc->base.dev;
3819 struct drm_i915_private *dev_priv = dev->dev_private;
3820 struct intel_crtc_config *pipe_config = &crtc->config;
3821
328d8e82 3822 if (!crtc->config.gmch_pfit.control)
2dd24552
JB		 3823 return;
3824
2dd24552 3825 /*
c0b03411
DV		 3826 * The panel fitter should only be adjusted whilst the pipe is disabled,
3827 * according to register description and PRM.
2dd24552 3828 */
c0b03411
DV		 3829 WARN_ON(I915_READ(PFIT_CONTROL) & PFIT_ENABLE);
3830 assert_pipe_disabled(dev_priv, crtc->pipe);
2dd24552 3831
b074cec8
JB		 3832 I915_WRITE(PFIT_PGM_RATIOS, pipe_config->gmch_pfit.pgm_ratios);
3833 I915_WRITE(PFIT_CONTROL, pipe_config->gmch_pfit.control);
5a80c45c
DV		 3834
3835 /* Border color in case we don't scale up to the full screen. Black by
3836 * default, change to something else for debugging. */
3837 I915_WRITE(BCLRPAT(crtc->pipe), 0);
2dd24552
JB		 3838}
3839
89b667f8
JB		 3840static void valleyview_crtc_enable(struct drm_crtc *crtc)
3841{
3842 struct drm_device *dev = crtc->dev;
3843 struct drm_i915_private *dev_priv = dev->dev_private;
3844 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3845 struct intel_encoder *encoder;
3846 int pipe = intel_crtc->pipe;
3847 int plane = intel_crtc->plane;
23538ef1 3848 bool is_dsi;
89b667f8
JB		 3849
3850 WARN_ON(!crtc->enabled);
3851
3852 if (intel_crtc->active)
3853 return;
3854
3855 intel_crtc->active = true;
89b667f8 3856
89b667f8
JB		 3857 for_each_encoder_on_crtc(dev, crtc, encoder)
3858 if (encoder->pre_pll_enable)
3859 encoder->pre_pll_enable(encoder);
3860
23538ef1
JN		 3861 is_dsi = intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI);
3862
e9fd1c02
JN		 3863 if (!is_dsi)
3864 vlv_enable_pll(intel_crtc);
89b667f8
JB		 3865
3866 for_each_encoder_on_crtc(dev, crtc, encoder)
3867 if (encoder->pre_enable)
3868 encoder->pre_enable(encoder);
3869
2dd24552
JB		 3870 i9xx_pfit_enable(intel_crtc);
3871
63cbb074
VS		 3872 intel_crtc_load_lut(crtc);
3873
f37fcc2a 3874 intel_update_watermarks(crtc);
23538ef1 3875 intel_enable_pipe(dev_priv, pipe, false, is_dsi);
89b667f8 3876 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3877 intel_enable_planes(crtc);
5c38d48c 3878 intel_crtc_update_cursor(crtc, true);
89b667f8 3879
89b667f8 3880 intel_update_fbc(dev);
5004945f
JN		 3881
3882 for_each_encoder_on_crtc(dev, crtc, encoder)
3883 encoder->enable(encoder);
89b667f8
JB		 3884}
3885
0b8765c6 3886static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3887{
3888 struct drm_device *dev = crtc->dev;
79e53945
JB		 3889 struct drm_i915_private *dev_priv = dev->dev_private;
3890 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3891 struct intel_encoder *encoder;
79e53945 3892 int pipe = intel_crtc->pipe;
80824003 3893 int plane = intel_crtc->plane;
79e53945 3894
08a48469
DV		 3895 WARN_ON(!crtc->enabled);
3896
f7abfe8b
CW		 3897 if (intel_crtc->active)
3898 return;
3899
3900 intel_crtc->active = true;
6b383a7f 3901
9d6d9f19
MK		 3902 for_each_encoder_on_crtc(dev, crtc, encoder)
3903 if (encoder->pre_enable)
3904 encoder->pre_enable(encoder);
3905
f6736a1a
DV		 3906 i9xx_enable_pll(intel_crtc);
3907
2dd24552
JB		 3908 i9xx_pfit_enable(intel_crtc);
3909
63cbb074
VS		 3910 intel_crtc_load_lut(crtc);
3911
f37fcc2a 3912 intel_update_watermarks(crtc);
23538ef1 3913 intel_enable_pipe(dev_priv, pipe, false, false);
b24e7179 3914 intel_enable_plane(dev_priv, plane, pipe);
bb53d4ae 3915 intel_enable_planes(crtc);
22e407d7 3916 /* The fixup needs to happen before cursor is enabled */
61bc95c1
EE		 3917 if (IS_G4X(dev))
3918 g4x_fixup_plane(dev_priv, pipe);
22e407d7 3919 intel_crtc_update_cursor(crtc, true);
79e53945 3920
0b8765c6
JB		 3921 /* Give the overlay scaler a chance to enable if it's on this pipe */
3922 intel_crtc_dpms_overlay(intel_crtc, true);
ef9c3aee 3923
f440eb13 3924 intel_update_fbc(dev);
ef9c3aee 3925
fa5c73b1
DV		 3926 for_each_encoder_on_crtc(dev, crtc, encoder)
3927 encoder->enable(encoder);
0b8765c6 3928}
79e53945 3929
87476d63
DV		 3930static void i9xx_pfit_disable(struct intel_crtc *crtc)
3931{
3932 struct drm_device *dev = crtc->base.dev;
3933 struct drm_i915_private *dev_priv = dev->dev_private;
87476d63 3934
328d8e82
DV		 3935 if (!crtc->config.gmch_pfit.control)
3936 return;
87476d63 3937
328d8e82 3938 assert_pipe_disabled(dev_priv, crtc->pipe);
87476d63 3939
328d8e82
DV		 3940 DRM_DEBUG_DRIVER("disabling pfit, current: 0x%08x\n",
3941 I915_READ(PFIT_CONTROL));
3942 I915_WRITE(PFIT_CONTROL, 0);
87476d63
DV		 3943}
3944
0b8765c6
JB		 3945static void i9xx_crtc_disable(struct drm_crtc *crtc)
3946{
3947 struct drm_device *dev = crtc->dev;
3948 struct drm_i915_private *dev_priv = dev->dev_private;
3949 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3950 struct intel_encoder *encoder;
0b8765c6
JB		 3951 int pipe = intel_crtc->pipe;
3952 int plane = intel_crtc->plane;
ef9c3aee 3953
f7abfe8b
CW		 3954 if (!intel_crtc->active)
3955 return;
3956
ea9d758d
DV		 3957 for_each_encoder_on_crtc(dev, crtc, encoder)
3958 encoder->disable(encoder);
3959
0b8765c6 3960 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3961 intel_crtc_wait_for_pending_flips(crtc);
3962 drm_vblank_off(dev, pipe);
0b8765c6 3963
5c3fe8b0 3964 if (dev_priv->fbc.plane == plane)
973d04f9 3965 intel_disable_fbc(dev);
79e53945 3966
0d5b8c61
VS		 3967 intel_crtc_dpms_overlay(intel_crtc, false);
3968 intel_crtc_update_cursor(crtc, false);
bb53d4ae 3969 intel_disable_planes(crtc);
b24e7179 3970 intel_disable_plane(dev_priv, plane, pipe);
0d5b8c61 3971
b24e7179 3972 intel_disable_pipe(dev_priv, pipe);
24a1f16d 3973
87476d63 3974 i9xx_pfit_disable(intel_crtc);
24a1f16d 3975
89b667f8
JB		 3976 for_each_encoder_on_crtc(dev, crtc, encoder)
3977 if (encoder->post_disable)
3978 encoder->post_disable(encoder);
3979
f6071166
JB		 3980 if (IS_VALLEYVIEW(dev) && !intel_pipe_has_type(crtc, INTEL_OUTPUT_DSI))
3981 vlv_disable_pll(dev_priv, pipe);
3982 else if (!IS_VALLEYVIEW(dev))
e9fd1c02 3983 i9xx_disable_pll(dev_priv, pipe);
0b8765c6 3984
f7abfe8b 3985 intel_crtc->active = false;
46ba614c 3986 intel_update_watermarks(crtc);
f37fcc2a 3987
6b383a7f 3988 intel_update_fbc(dev);
0b8765c6
JB		 3989}
3990
ee7b9f93
JB		 3991static void i9xx_crtc_off(struct drm_crtc *crtc)
3992{
3993}
3994
976f8a20
DV		 3995static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3996 bool enabled)
2c07245f
ZW		 3997{
3998 struct drm_device *dev = crtc->dev;
3999 struct drm_i915_master_private *master_priv;
4000 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4001 int pipe = intel_crtc->pipe;
79e53945
JB		 4002
4003 if (!dev->primary->master)
4004 return;
4005
4006 master_priv = dev->primary->master->driver_priv;
4007 if (!master_priv->sarea_priv)
4008 return;
4009
79e53945
JB		 4010 switch (pipe) {
4011 case 0:
4012 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
4013 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
4014 break;
4015 case 1:
4016 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
4017 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
4018 break;
4019 default:
9db4a9c7 4020 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 4021 break;
4022 }
79e53945
JB		 4023}
4024
976f8a20
DV		 4025/**
4026 * Sets the power management mode of the pipe and plane.
4027 */
4028void intel_crtc_update_dpms(struct drm_crtc *crtc)
4029{
4030 struct drm_device *dev = crtc->dev;
4031 struct drm_i915_private *dev_priv = dev->dev_private;
4032 struct intel_encoder *intel_encoder;
4033 bool enable = false;
4034
4035 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
4036 enable |= intel_encoder->connectors_active;
4037
4038 if (enable)
4039 dev_priv->display.crtc_enable(crtc);
4040 else
4041 dev_priv->display.crtc_disable(crtc);
4042
4043 intel_crtc_update_sarea(crtc, enable);
4044}
4045
cdd59983
CW		 4046static void intel_crtc_disable(struct drm_crtc *crtc)
4047{
cdd59983 4048 struct drm_device *dev = crtc->dev;
976f8a20 4049 struct drm_connector *connector;
ee7b9f93 4050 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 4051 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 4052
976f8a20
DV		 4053 /* crtc should still be enabled when we disable it. */
4054 WARN_ON(!crtc->enabled);
4055
4056 dev_priv->display.crtc_disable(crtc);
c77bf565 4057 intel_crtc->eld_vld = false;
976f8a20 4058 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 4059 dev_priv->display.off(crtc);
4060
931872fc 4061 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
93ce0ba6 4062 assert_cursor_disabled(dev_priv, to_intel_crtc(crtc)->pipe);
931872fc 4063 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 4064
4065 if (crtc->fb) {
4066 mutex_lock(&dev->struct_mutex);
1690e1eb 4067 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 4068 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 4069 crtc->fb = NULL;
4070 }
4071
4072 /* Update computed state. */
4073 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4074 if (!connector->encoder || !connector->encoder->crtc)
4075 continue;
4076
4077 if (connector->encoder->crtc != crtc)
4078 continue;
4079
4080 connector->dpms = DRM_MODE_DPMS_OFF;
4081 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 4082 }
4083}
4084
ea5b213a 4085void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 4086{
4ef69c7a 4087 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 4088
ea5b213a
CW		 4089 drm_encoder_cleanup(encoder);
4090 kfree(intel_encoder);
7e7d76c3
JB		 4091}
4092
9237329d 4093/* Simple dpms helper for encoders with just one connector, no cloning and only
5ab432ef
DV		 4094 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
4095 * state of the entire output pipe. */
9237329d 4096static void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 4097{
5ab432ef
DV		 4098 if (mode == DRM_MODE_DPMS_ON) {
4099 encoder->connectors_active = true;
4100
b2cabb0e 4101 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 4102 } else {
4103 encoder->connectors_active = false;
4104
b2cabb0e 4105 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 4106 }
79e53945
JB		 4107}
4108
0a91ca29
DV		 4109/* Cross check the actual hw state with our own modeset state tracking (and it's
4110 * internal consistency). */
b980514c 4111static void intel_connector_check_state(struct intel_connector *connector)
79e53945 4112{
0a91ca29
DV		 4113 if (connector->get_hw_state(connector)) {
4114 struct intel_encoder *encoder = connector->encoder;
4115 struct drm_crtc *crtc;
4116 bool encoder_enabled;
4117 enum pipe pipe;
4118
4119 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4120 connector->base.base.id,
4121 drm_get_connector_name(&connector->base));
4122
4123 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
4124 "wrong connector dpms state\n");
4125 WARN(connector->base.encoder != &encoder->base,
4126 "active connector not linked to encoder\n");
4127 WARN(!encoder->connectors_active,
4128 "encoder->connectors_active not set\n");
4129
4130 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
4131 WARN(!encoder_enabled, "encoder not enabled\n");
4132 if (WARN_ON(!encoder->base.crtc))
4133 return;
4134
4135 crtc = encoder->base.crtc;
4136
4137 WARN(!crtc->enabled, "crtc not enabled\n");
4138 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
4139 WARN(pipe != to_intel_crtc(crtc)->pipe,
4140 "encoder active on the wrong pipe\n");
4141 }
79e53945
JB		 4142}
4143
5ab432ef
DV		 4144/* Even simpler default implementation, if there's really no special case to
4145 * consider. */
4146void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 4147{
5ab432ef 4148 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 4149
5ab432ef
DV		 4150 /* All the simple cases only support two dpms states. */
4151 if (mode != DRM_MODE_DPMS_ON)
4152 mode = DRM_MODE_DPMS_OFF;
d4270e57 4153
5ab432ef
DV		 4154 if (mode == connector->dpms)
4155 return;
4156
4157 connector->dpms = mode;
4158
4159 /* Only need to change hw state when actually enabled */
4160 if (encoder->base.crtc)
4161 intel_encoder_dpms(encoder, mode);
4162 else
8af6cf88 4163 WARN_ON(encoder->connectors_active != false);
0a91ca29 4164
b980514c 4165 intel_modeset_check_state(connector->dev);
79e53945
JB		 4166}
4167
f0947c37
DV		 4168/* Simple connector->get_hw_state implementation for encoders that support only
4169 * one connector and no cloning and hence the encoder state determines the state
4170 * of the connector. */
4171bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 4172{
24929352 4173 enum pipe pipe = 0;
f0947c37 4174 struct intel_encoder *encoder = connector->encoder;
ea5b213a 4175
f0947c37 4176 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 4177}
4178
1857e1da
DV		 4179static bool ironlake_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
4180 struct intel_crtc_config *pipe_config)
4181{
4182 struct drm_i915_private *dev_priv = dev->dev_private;
4183 struct intel_crtc *pipe_B_crtc =
4184 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
4185
4186 DRM_DEBUG_KMS("checking fdi config on pipe %c, lanes %i\n",
4187 pipe_name(pipe), pipe_config->fdi_lanes);
4188 if (pipe_config->fdi_lanes > 4) {
4189 DRM_DEBUG_KMS("invalid fdi lane config on pipe %c: %i lanes\n",
4190 pipe_name(pipe), pipe_config->fdi_lanes);
4191 return false;
4192 }
4193
4194 if (IS_HASWELL(dev)) {
4195 if (pipe_config->fdi_lanes > 2) {
4196 DRM_DEBUG_KMS("only 2 lanes on haswell, required: %i lanes\n",
4197 pipe_config->fdi_lanes);
4198 return false;
4199 } else {
4200 return true;
4201 }
4202 }
4203
4204 if (INTEL_INFO(dev)->num_pipes == 2)
4205 return true;
4206
4207 /* Ivybridge 3 pipe is really complicated */
4208 switch (pipe) {
4209 case PIPE_A:
4210 return true;
4211 case PIPE_B:
4212 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
4213 pipe_config->fdi_lanes > 2) {
4214 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4215 pipe_name(pipe), pipe_config->fdi_lanes);
4216 return false;
4217 }
4218 return true;
4219 case PIPE_C:
1e833f40 4220 if (!pipe_has_enabled_pch(pipe_B_crtc) ||
1857e1da
DV		 4221 pipe_B_crtc->config.fdi_lanes <= 2) {
4222 if (pipe_config->fdi_lanes > 2) {
4223 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %c: %i lanes\n",
4224 pipe_name(pipe), pipe_config->fdi_lanes);
4225 return false;
4226 }
4227 } else {
4228 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
4229 return false;
4230 }
4231 return true;
4232 default:
4233 BUG();
4234 }
4235}
4236
e29c22c0
DV		 4237#define RETRY 1
4238static int ironlake_fdi_compute_config(struct intel_crtc *intel_crtc,
4239 struct intel_crtc_config *pipe_config)
877d48d5 4240{
1857e1da 4241 struct drm_device *dev = intel_crtc->base.dev;
877d48d5 4242 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
ff9a6750 4243 int lane, link_bw, fdi_dotclock;
e29c22c0 4244 bool setup_ok, needs_recompute = false;
877d48d5 4245
e29c22c0 4246retry:
877d48d5
DV		 4247 /* FDI is a binary signal running at ~2.7GHz, encoding
4248 * each output octet as 10 bits. The actual frequency
4249 * is stored as a divider into a 100MHz clock, and the
4250 * mode pixel clock is stored in units of 1KHz.
4251 * Hence the bw of each lane in terms of the mode signal
4252 * is:
4253 */
4254 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4255
241bfc38 4256 fdi_dotclock = adjusted_mode->crtc_clock;
877d48d5 4257
2bd89a07 4258 lane = ironlake_get_lanes_required(fdi_dotclock, link_bw,
877d48d5
DV		 4259 pipe_config->pipe_bpp);
4260
4261 pipe_config->fdi_lanes = lane;
4262
2bd89a07 4263 intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
877d48d5 4264 link_bw, &pipe_config->fdi_m_n);
1857e1da 4265
e29c22c0
DV		 4266 setup_ok = ironlake_check_fdi_lanes(intel_crtc->base.dev,
4267 intel_crtc->pipe, pipe_config);
4268 if (!setup_ok && pipe_config->pipe_bpp > 6*3) {
4269 pipe_config->pipe_bpp -= 2*3;
4270 DRM_DEBUG_KMS("fdi link bw constraint, reducing pipe bpp to %i\n",
4271 pipe_config->pipe_bpp);
4272 needs_recompute = true;
4273 pipe_config->bw_constrained = true;
4274
4275 goto retry;
4276 }
4277
4278 if (needs_recompute)
4279 return RETRY;
4280
4281 return setup_ok ? 0 : -EINVAL;
877d48d5
DV		 4282}
4283
42db64ef
PZ		 4284static void hsw_compute_ips_config(struct intel_crtc *crtc,
4285 struct intel_crtc_config *pipe_config)
4286{
3c4ca58c
PZ		 4287 pipe_config->ips_enabled = i915_enable_ips &&
4288 hsw_crtc_supports_ips(crtc) &&
b6dfdc9b 4289 pipe_config->pipe_bpp <= 24;
42db64ef
PZ		 4290}
4291
a43f6e0f 4292static int intel_crtc_compute_config(struct intel_crtc *crtc,
e29c22c0 4293 struct intel_crtc_config *pipe_config)
79e53945 4294{
a43f6e0f 4295 struct drm_device *dev = crtc->base.dev;
b8cecdf5 4296 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
89749350 4297
ad3a4479 4298 /* FIXME should check pixel clock limits on all platforms */
cf532bb2
VS		 4299 if (INTEL_INFO(dev)->gen < 4) {
4300 struct drm_i915_private *dev_priv = dev->dev_private;
4301 int clock_limit =
4302 dev_priv->display.get_display_clock_speed(dev);
4303
4304 /*
4305 * Enable pixel doubling when the dot clock
4306 * is > 90% of the (display) core speed.
4307 *
b397c96b
VS		 4308 * GDG double wide on either pipe,
4309 * otherwise pipe A only.
cf532bb2 4310 */
b397c96b 4311 if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
241bfc38 4312 adjusted_mode->crtc_clock > clock_limit * 9 / 10) {
ad3a4479 4313 clock_limit *= 2;
cf532bb2 4314 pipe_config->double_wide = true;
ad3a4479
VS		 4315 }
4316
241bfc38 4317 if (adjusted_mode->crtc_clock > clock_limit * 9 / 10)
e29c22c0 4318 return -EINVAL;
2c07245f 4319 }
89749350 4320
1d1d0e27
VS		 4321 /*
4322 * Pipe horizontal size must be even in:
4323 * - DVO ganged mode
4324 * - LVDS dual channel mode
4325 * - Double wide pipe
4326 */
4327 if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
4328 intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
4329 pipe_config->pipe_src_w &= ~1;
4330
8693a824
DL		 4331 /* Cantiga+ cannot handle modes with a hsync front porch of 0.
4332 * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
44f46b42
CW		 4333 */
4334 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
4335 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
e29c22c0 4336 return -EINVAL;
44f46b42 4337
bd080ee5 4338 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) && pipe_config->pipe_bpp > 10*3) {
5d2d38dd 4339 pipe_config->pipe_bpp = 10*3; /* 12bpc is gen5+ */
bd080ee5 4340 } else if (INTEL_INFO(dev)->gen <= 4 && pipe_config->pipe_bpp > 8*3) {
5d2d38dd
DV		 4341 /* only a 8bpc pipe, with 6bpc dither through the panel fitter
4342 * for lvds. */
4343 pipe_config->pipe_bpp = 8*3;
4344 }
4345
f5adf94e 4346 if (HAS_IPS(dev))
a43f6e0f
DV		 4347 hsw_compute_ips_config(crtc, pipe_config);
4348
4349 /* XXX: PCH clock sharing is done in ->mode_set, so make sure the old
4350 * clock survives for now. */
4351 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
4352 pipe_config->shared_dpll = crtc->config.shared_dpll;
42db64ef 4353
877d48d5 4354 if (pipe_config->has_pch_encoder)
a43f6e0f 4355 return ironlake_fdi_compute_config(crtc, pipe_config);
877d48d5 4356
e29c22c0 4357 return 0;
79e53945
JB		 4358}
4359
25eb05fc
JB		 4360static int valleyview_get_display_clock_speed(struct drm_device *dev)
4361{
4362 return 400000; /* FIXME */
4363}
4364
e70236a8
JB		 4365static int i945_get_display_clock_speed(struct drm_device *dev)
4366{
4367 return 400000;
4368}
79e53945 4369
e70236a8 4370static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 4371{
e70236a8
JB		 4372 return 333000;
4373}
79e53945 4374
e70236a8
JB		 4375static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
4376{
4377 return 200000;
4378}
79e53945 4379
257a7ffc
DV		 4380static int pnv_get_display_clock_speed(struct drm_device *dev)
4381{
4382 u16 gcfgc = 0;
4383
4384 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4385
4386 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4387 case GC_DISPLAY_CLOCK_267_MHZ_PNV:
4388 return 267000;
4389 case GC_DISPLAY_CLOCK_333_MHZ_PNV:
4390 return 333000;
4391 case GC_DISPLAY_CLOCK_444_MHZ_PNV:
4392 return 444000;
4393 case GC_DISPLAY_CLOCK_200_MHZ_PNV:
4394 return 200000;
4395 default:
4396 DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc);
4397 case GC_DISPLAY_CLOCK_133_MHZ_PNV:
4398 return 133000;
4399 case GC_DISPLAY_CLOCK_167_MHZ_PNV:
4400 return 167000;
4401 }
4402}
4403
e70236a8
JB		 4404static int i915gm_get_display_clock_speed(struct drm_device *dev)
4405{
4406 u16 gcfgc = 0;
79e53945 4407
e70236a8
JB		 4408 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
4409
4410 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
4411 return 133000;
4412 else {
4413 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
4414 case GC_DISPLAY_CLOCK_333_MHZ:
4415 return 333000;
4416 default:
4417 case GC_DISPLAY_CLOCK_190_200_MHZ:
4418 return 190000;
79e53945 4419 }
e70236a8
JB		 4420 }
4421}
4422
4423static int i865_get_display_clock_speed(struct drm_device *dev)
4424{
4425 return 266000;
4426}
4427
4428static int i855_get_display_clock_speed(struct drm_device *dev)
4429{
4430 u16 hpllcc = 0;
4431 /* Assume that the hardware is in the high speed state. This
4432 * should be the default.
4433 */
4434 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
4435 case GC_CLOCK_133_200:
4436 case GC_CLOCK_100_200:
4437 return 200000;
4438 case GC_CLOCK_166_250:
4439 return 250000;
4440 case GC_CLOCK_100_133:
79e53945 4441 return 133000;
e70236a8 4442 }
79e53945 4443
e70236a8
JB		 4444 /* Shouldn't happen */
4445 return 0;
4446}
79e53945 4447
e70236a8
JB		 4448static int i830_get_display_clock_speed(struct drm_device *dev)
4449{
4450 return 133000;
79e53945
JB		 4451}
4452
2c07245f 4453static void
a65851af 4454intel_reduce_m_n_ratio(uint32_t *num, uint32_t *den)
2c07245f 4455{
a65851af
VS		 4456 while (*num > DATA_LINK_M_N_MASK ||
4457 *den > DATA_LINK_M_N_MASK) {
2c07245f
ZW		 4458 *num >>= 1;
4459 *den >>= 1;
4460 }
4461}
4462
a65851af
VS		 4463static void compute_m_n(unsigned int m, unsigned int n,
4464 uint32_t *ret_m, uint32_t *ret_n)
4465{
4466 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
4467 *ret_m = div_u64((uint64_t) m * *ret_n, n);
4468 intel_reduce_m_n_ratio(ret_m, ret_n);
4469}
4470
e69d0bc1
DV		 4471void
4472intel_link_compute_m_n(int bits_per_pixel, int nlanes,
4473 int pixel_clock, int link_clock,
4474 struct intel_link_m_n *m_n)
2c07245f 4475{
e69d0bc1 4476 m_n->tu = 64;
a65851af
VS		 4477
4478 compute_m_n(bits_per_pixel * pixel_clock,
4479 link_clock * nlanes * 8,
4480 &m_n->gmch_m, &m_n->gmch_n);
4481
4482 compute_m_n(pixel_clock, link_clock,
4483 &m_n->link_m, &m_n->link_n);
2c07245f
ZW		 4484}
4485
a7615030
CW		 4486static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4487{
72bbe58c
KP		 4488 if (i915_panel_use_ssc >= 0)
4489 return i915_panel_use_ssc != 0;
41aa3448 4490 return dev_priv->vbt.lvds_use_ssc
435793df 4491 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4492}
4493
c65d77d8
JB		 4494static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4495{
4496 struct drm_device *dev = crtc->dev;
4497 struct drm_i915_private *dev_priv = dev->dev_private;
4498 int refclk;
4499
a0c4da24 4500 if (IS_VALLEYVIEW(dev)) {
9a0ea498 4501 refclk = 100000;
a0c4da24 4502 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8 4503 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
41aa3448 4504 refclk = dev_priv->vbt.lvds_ssc_freq * 1000;
c65d77d8
JB		 4505 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4506 refclk / 1000);
4507 } else if (!IS_GEN2(dev)) {
4508 refclk = 96000;
4509 } else {
4510 refclk = 48000;
4511 }
4512
4513 return refclk;
4514}
4515
7429e9d4 4516static uint32_t pnv_dpll_compute_fp(struct dpll *dpll)
c65d77d8 4517{
7df00d7a 4518 return (1 << dpll->n) << 16 | dpll->m2;
7429e9d4 4519}
f47709a9 4520
7429e9d4
DV		 4521static uint32_t i9xx_dpll_compute_fp(struct dpll *dpll)
4522{
4523 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2;
c65d77d8
JB		 4524}
4525
f47709a9 4526static void i9xx_update_pll_dividers(struct intel_crtc *crtc,
a7516a05
JB		 4527 intel_clock_t *reduced_clock)
4528{
f47709a9 4529 struct drm_device *dev = crtc->base.dev;
a7516a05 4530 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4531 int pipe = crtc->pipe;
a7516a05
JB		 4532 u32 fp, fp2 = 0;
4533
4534 if (IS_PINEVIEW(dev)) {
7429e9d4 4535 fp = pnv_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4536 if (reduced_clock)
7429e9d4 4537 fp2 = pnv_dpll_compute_fp(reduced_clock);
a7516a05 4538 } else {
7429e9d4 4539 fp = i9xx_dpll_compute_fp(&crtc->config.dpll);
a7516a05 4540 if (reduced_clock)
7429e9d4 4541 fp2 = i9xx_dpll_compute_fp(reduced_clock);
a7516a05
JB		 4542 }
4543
4544 I915_WRITE(FP0(pipe), fp);
8bcc2795 4545 crtc->config.dpll_hw_state.fp0 = fp;
a7516a05 4546
f47709a9
DV		 4547 crtc->lowfreq_avail = false;
4548 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
a7516a05
JB		 4549 reduced_clock && i915_powersave) {
4550 I915_WRITE(FP1(pipe), fp2);
8bcc2795 4551 crtc->config.dpll_hw_state.fp1 = fp2;
f47709a9 4552 crtc->lowfreq_avail = true;
a7516a05
JB		 4553 } else {
4554 I915_WRITE(FP1(pipe), fp);
8bcc2795 4555 crtc->config.dpll_hw_state.fp1 = fp;
a7516a05
JB		 4556 }
4557}
4558
5e69f97f
CML		 4559static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, enum pipe
4560 pipe)
89b667f8
JB		 4561{
4562 u32 reg_val;
4563
4564 /*
4565 * PLLB opamp always calibrates to max value of 0x3f, force enable it
4566 * and set it to a reasonable value instead.
4567 */
5e69f97f 4568 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8
JB		 4569 reg_val &= 0xffffff00;
4570 reg_val |= 0x00000030;
5e69f97f 4571 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4572
5e69f97f 4573 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4574 reg_val &= 0x8cffffff;
4575 reg_val = 0x8c000000;
5e69f97f 4576 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8 4577
5e69f97f 4578 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF(1));
89b667f8 4579 reg_val &= 0xffffff00;
5e69f97f 4580 vlv_dpio_write(dev_priv, pipe, DPIO_IREF(1), reg_val);
89b667f8 4581
5e69f97f 4582 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_CALIBRATION);
89b667f8
JB		 4583 reg_val &= 0x00ffffff;
4584 reg_val |= 0xb0000000;
5e69f97f 4585 vlv_dpio_write(dev_priv, pipe, DPIO_CALIBRATION, reg_val);
89b667f8
JB		 4586}
4587
b551842d
DV		 4588static void intel_pch_transcoder_set_m_n(struct intel_crtc *crtc,
4589 struct intel_link_m_n *m_n)
4590{
4591 struct drm_device *dev = crtc->base.dev;
4592 struct drm_i915_private *dev_priv = dev->dev_private;
4593 int pipe = crtc->pipe;
4594
e3b95f1e
DV		 4595 I915_WRITE(PCH_TRANS_DATA_M1(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4596 I915_WRITE(PCH_TRANS_DATA_N1(pipe), m_n->gmch_n);
4597 I915_WRITE(PCH_TRANS_LINK_M1(pipe), m_n->link_m);
4598 I915_WRITE(PCH_TRANS_LINK_N1(pipe), m_n->link_n);
b551842d
DV		 4599}
4600
4601static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc,
4602 struct intel_link_m_n *m_n)
4603{
4604 struct drm_device *dev = crtc->base.dev;
4605 struct drm_i915_private *dev_priv = dev->dev_private;
4606 int pipe = crtc->pipe;
4607 enum transcoder transcoder = crtc->config.cpu_transcoder;
4608
4609 if (INTEL_INFO(dev)->gen >= 5) {
4610 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m);
4611 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n);
4612 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m);
4613 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n);
4614 } else {
e3b95f1e
DV		 4615 I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | m_n->gmch_m);
4616 I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n);
4617 I915_WRITE(PIPE_LINK_M_G4X(pipe), m_n->link_m);
4618 I915_WRITE(PIPE_LINK_N_G4X(pipe), m_n->link_n);
b551842d
DV		 4619 }
4620}
4621
03afc4a2
DV		 4622static void intel_dp_set_m_n(struct intel_crtc *crtc)
4623{
4624 if (crtc->config.has_pch_encoder)
4625 intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4626 else
4627 intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n);
4628}
4629
f47709a9 4630static void vlv_update_pll(struct intel_crtc *crtc)
a0c4da24 4631{
f47709a9 4632 struct drm_device *dev = crtc->base.dev;
a0c4da24 4633 struct drm_i915_private *dev_priv = dev->dev_private;
f47709a9 4634 int pipe = crtc->pipe;
89b667f8 4635 u32 dpll, mdiv;
a0c4da24 4636 u32 bestn, bestm1, bestm2, bestp1, bestp2;
198a037f 4637 u32 coreclk, reg_val, dpll_md;
a0c4da24 4638
09153000
DV		 4639 mutex_lock(&dev_priv->dpio_lock);
4640
f47709a9
DV		 4641 bestn = crtc->config.dpll.n;
4642 bestm1 = crtc->config.dpll.m1;
4643 bestm2 = crtc->config.dpll.m2;
4644 bestp1 = crtc->config.dpll.p1;
4645 bestp2 = crtc->config.dpll.p2;
a0c4da24 4646
89b667f8
JB		 4647 /* See eDP HDMI DPIO driver vbios notes doc */
4648
4649 /* PLL B needs special handling */
4650 if (pipe)
5e69f97f 4651 vlv_pllb_recal_opamp(dev_priv, pipe);
89b667f8
JB		 4652
4653 /* Set up Tx target for periodic Rcomp update */
5e69f97f 4654 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_BCAST, 0x0100000f);
89b667f8
JB		 4655
4656 /* Disable target IRef on PLL */
5e69f97f 4657 reg_val = vlv_dpio_read(dev_priv, pipe, DPIO_IREF_CTL(pipe));
89b667f8 4658 reg_val &= 0x00ffffff;
5e69f97f 4659 vlv_dpio_write(dev_priv, pipe, DPIO_IREF_CTL(pipe), reg_val);
89b667f8
JB		 4660
4661 /* Disable fast lock */
5e69f97f 4662 vlv_dpio_write(dev_priv, pipe, DPIO_FASTCLK_DISABLE, 0x610);
89b667f8
JB		 4663
4664 /* Set idtafcrecal before PLL is enabled */
a0c4da24
JB		 4665 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4666 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4667 mdiv |= ((bestn << DPIO_N_SHIFT));
a0c4da24 4668 mdiv |= (1 << DPIO_K_SHIFT);
7df5080b
JB		 4669
4670 /*
4671 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS,
4672 * but we don't support that).
4673 * Note: don't use the DAC post divider as it seems unstable.
4674 */
4675 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT);
5e69f97f 4676 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4677
a0c4da24 4678 mdiv |= DPIO_ENABLE_CALIBRATION;
5e69f97f 4679 vlv_dpio_write(dev_priv, pipe, DPIO_DIV(pipe), mdiv);
a0c4da24 4680
89b667f8 4681 /* Set HBR and RBR LPF coefficients */
ff9a6750 4682 if (crtc->config.port_clock == 162000 ||
99750bd4 4683 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_ANALOG) ||
89b667f8 4684 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI))
5e69f97f 4685 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
885b0120 4686 0x009f0003);
89b667f8 4687 else
5e69f97f 4688 vlv_dpio_write(dev_priv, pipe, DPIO_LPF_COEFF(pipe),
89b667f8
JB		 4689 0x00d0000f);
4690
4691 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP) ||
4692 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT)) {
4693 /* Use SSC source */
4694 if (!pipe)
5e69f97f 4695 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4696 0x0df40000);
4697 else
5e69f97f 4698 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4699 0x0df70000);
4700 } else { /* HDMI or VGA */
4701 /* Use bend source */
4702 if (!pipe)
5e69f97f 4703 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4704 0x0df70000);
4705 else
5e69f97f 4706 vlv_dpio_write(dev_priv, pipe, DPIO_REFSFR(pipe),
89b667f8
JB		 4707 0x0df40000);
4708 }
a0c4da24 4709
5e69f97f 4710 coreclk = vlv_dpio_read(dev_priv, pipe, DPIO_CORE_CLK(pipe));
89b667f8
JB		 4711 coreclk = (coreclk & 0x0000ff00) | 0x01c00000;
4712 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT) ||
4713 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_EDP))
4714 coreclk |= 0x01000000;
5e69f97f 4715 vlv_dpio_write(dev_priv, pipe, DPIO_CORE_CLK(pipe), coreclk);
a0c4da24 4716
5e69f97f 4717 vlv_dpio_write(dev_priv, pipe, DPIO_PLL_CML(pipe), 0x87871000);
a0c4da24 4718
89b667f8
JB		 4719 /* Enable DPIO clock input */
4720 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4721 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
f6071166
JB		 4722 /* We should never disable this, set it here for state tracking */
4723 if (pipe == PIPE_B)
89b667f8 4724 dpll |= DPLL_INTEGRATED_CRI_CLK_VLV;
a0c4da24 4725 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4726 crtc->config.dpll_hw_state.dpll = dpll;
4727
ef1b460d
DV		 4728 dpll_md = (crtc->config.pixel_multiplier - 1)
4729 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795
DV		 4730 crtc->config.dpll_hw_state.dpll_md = dpll_md;
4731
89b667f8
JB		 4732 if (crtc->config.has_dp_encoder)
4733 intel_dp_set_m_n(crtc);
09153000
DV		 4734
4735 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4736}
4737
f47709a9
DV		 4738static void i9xx_update_pll(struct intel_crtc *crtc,
4739 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4740 int num_connectors)
4741{
f47709a9 4742 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4743 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48
DV		 4744 u32 dpll;
4745 bool is_sdvo;
f47709a9 4746 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4747
f47709a9 4748 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4749
f47709a9
DV		 4750 is_sdvo = intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_SDVO) ||
4751 intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_HDMI);
eb1cbe48
DV		 4752
4753 dpll = DPLL_VGA_MODE_DIS;
4754
f47709a9 4755 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS))
eb1cbe48
DV		 4756 dpll |= DPLLB_MODE_LVDS;
4757 else
4758 dpll |= DPLLB_MODE_DAC_SERIAL;
6cc5f341 4759
ef1b460d 4760 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
198a037f
DV		 4761 dpll |= (crtc->config.pixel_multiplier - 1)
4762 << SDVO_MULTIPLIER_SHIFT_HIRES;
eb1cbe48 4763 }
198a037f
DV		 4764
4765 if (is_sdvo)
4a33e48d 4766 dpll |= DPLL_SDVO_HIGH_SPEED;
198a037f 4767
f47709a9 4768 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DISPLAYPORT))
4a33e48d 4769 dpll |= DPLL_SDVO_HIGH_SPEED;
eb1cbe48
DV		 4770
4771 /* compute bitmask from p1 value */
4772 if (IS_PINEVIEW(dev))
4773 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4774 else {
4775 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4776 if (IS_G4X(dev) && reduced_clock)
4777 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4778 }
4779 switch (clock->p2) {
4780 case 5:
4781 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4782 break;
4783 case 7:
4784 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4785 break;
4786 case 10:
4787 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4788 break;
4789 case 14:
4790 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4791 break;
4792 }
4793 if (INTEL_INFO(dev)->gen >= 4)
4794 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4795
09ede541 4796 if (crtc->config.sdvo_tv_clock)
eb1cbe48 4797 dpll |= PLL_REF_INPUT_TVCLKINBC;
f47709a9 4798 else if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4799 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4800 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4801 else
4802 dpll |= PLL_REF_INPUT_DREFCLK;
4803
4804 dpll |= DPLL_VCO_ENABLE;
8bcc2795
DV		 4805 crtc->config.dpll_hw_state.dpll = dpll;
4806
eb1cbe48 4807 if (INTEL_INFO(dev)->gen >= 4) {
ef1b460d
DV		 4808 u32 dpll_md = (crtc->config.pixel_multiplier - 1)
4809 << DPLL_MD_UDI_MULTIPLIER_SHIFT;
8bcc2795 4810 crtc->config.dpll_hw_state.dpll_md = dpll_md;
eb1cbe48 4811 }
66e3d5c0
DV		 4812
4813 if (crtc->config.has_dp_encoder)
4814 intel_dp_set_m_n(crtc);
eb1cbe48
DV		 4815}
4816
f47709a9 4817static void i8xx_update_pll(struct intel_crtc *crtc,
f47709a9 4818 intel_clock_t *reduced_clock,
eb1cbe48
DV		 4819 int num_connectors)
4820{
f47709a9 4821 struct drm_device *dev = crtc->base.dev;
eb1cbe48 4822 struct drm_i915_private *dev_priv = dev->dev_private;
eb1cbe48 4823 u32 dpll;
f47709a9 4824 struct dpll *clock = &crtc->config.dpll;
eb1cbe48 4825
f47709a9 4826 i9xx_update_pll_dividers(crtc, reduced_clock);
2a8f64ca 4827
eb1cbe48
DV		 4828 dpll = DPLL_VGA_MODE_DIS;
4829
f47709a9 4830 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS)) {
eb1cbe48
DV		 4831 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4832 } else {
4833 if (clock->p1 == 2)
4834 dpll |= PLL_P1_DIVIDE_BY_TWO;
4835 else
4836 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4837 if (clock->p2 == 4)
4838 dpll |= PLL_P2_DIVIDE_BY_4;
4839 }
4840
4a33e48d
DV		 4841 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_DVO))
4842 dpll |= DPLL_DVO_2X_MODE;
4843
f47709a9 4844 if (intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
eb1cbe48
DV		 4845 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4846 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4847 else
4848 dpll |= PLL_REF_INPUT_DREFCLK;
4849
4850 dpll |= DPLL_VCO_ENABLE;
8bcc2795 4851 crtc->config.dpll_hw_state.dpll = dpll;
eb1cbe48
DV		 4852}
4853
8a654f3b 4854static void intel_set_pipe_timings(struct intel_crtc *intel_crtc)
b0e77b9c
PZ		 4855{
4856 struct drm_device *dev = intel_crtc->base.dev;
4857 struct drm_i915_private *dev_priv = dev->dev_private;
4858 enum pipe pipe = intel_crtc->pipe;
3b117c8f 4859 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
8a654f3b
DV		 4860 struct drm_display_mode *adjusted_mode =
4861 &intel_crtc->config.adjusted_mode;
4d8a62ea
DV		 4862 uint32_t vsyncshift, crtc_vtotal, crtc_vblank_end;
4863
4864 /* We need to be careful not to changed the adjusted mode, for otherwise
4865 * the hw state checker will get angry at the mismatch. */
4866 crtc_vtotal = adjusted_mode->crtc_vtotal;
4867 crtc_vblank_end = adjusted_mode->crtc_vblank_end;
b0e77b9c
PZ		 4868
4869 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4870 /* the chip adds 2 halflines automatically */
4d8a62ea
DV		 4871 crtc_vtotal -= 1;
4872 crtc_vblank_end -= 1;
b0e77b9c
PZ		 4873 vsyncshift = adjusted_mode->crtc_hsync_start
4874 - adjusted_mode->crtc_htotal / 2;
4875 } else {
4876 vsyncshift = 0;
4877 }
4878
4879 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4880 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4881
fe2b8f9d 4882 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4883 (adjusted_mode->crtc_hdisplay - 1) |
4884 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4885 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4886 (adjusted_mode->crtc_hblank_start - 1) |
4887 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4888 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4889 (adjusted_mode->crtc_hsync_start - 1) |
4890 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4891
fe2b8f9d 4892 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c 4893 (adjusted_mode->crtc_vdisplay - 1) |
4d8a62ea 4894 ((crtc_vtotal - 1) << 16));
fe2b8f9d 4895 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c 4896 (adjusted_mode->crtc_vblank_start - 1) |
4d8a62ea 4897 ((crtc_vblank_end - 1) << 16));
fe2b8f9d 4898 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4899 (adjusted_mode->crtc_vsync_start - 1) |
4900 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4901
b5e508d4
PZ		 4902 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4903 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4904 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4905 * bits. */
4906 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4907 (pipe == PIPE_B || pipe == PIPE_C))
4908 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4909
b0e77b9c
PZ		 4910 /* pipesrc controls the size that is scaled from, which should
4911 * always be the user's requested size.
4912 */
4913 I915_WRITE(PIPESRC(pipe),
37327abd
VS		 4914 ((intel_crtc->config.pipe_src_w - 1) << 16) |
4915 (intel_crtc->config.pipe_src_h - 1));
b0e77b9c
PZ		 4916}
4917
1bd1bd80
DV		 4918static void intel_get_pipe_timings(struct intel_crtc *crtc,
4919 struct intel_crtc_config *pipe_config)
4920{
4921 struct drm_device *dev = crtc->base.dev;
4922 struct drm_i915_private *dev_priv = dev->dev_private;
4923 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
4924 uint32_t tmp;
4925
4926 tmp = I915_READ(HTOTAL(cpu_transcoder));
4927 pipe_config->adjusted_mode.crtc_hdisplay = (tmp & 0xffff) + 1;
4928 pipe_config->adjusted_mode.crtc_htotal = ((tmp >> 16) & 0xffff) + 1;
4929 tmp = I915_READ(HBLANK(cpu_transcoder));
4930 pipe_config->adjusted_mode.crtc_hblank_start = (tmp & 0xffff) + 1;
4931 pipe_config->adjusted_mode.crtc_hblank_end = ((tmp >> 16) & 0xffff) + 1;
4932 tmp = I915_READ(HSYNC(cpu_transcoder));
4933 pipe_config->adjusted_mode.crtc_hsync_start = (tmp & 0xffff) + 1;
4934 pipe_config->adjusted_mode.crtc_hsync_end = ((tmp >> 16) & 0xffff) + 1;
4935
4936 tmp = I915_READ(VTOTAL(cpu_transcoder));
4937 pipe_config->adjusted_mode.crtc_vdisplay = (tmp & 0xffff) + 1;
4938 pipe_config->adjusted_mode.crtc_vtotal = ((tmp >> 16) & 0xffff) + 1;
4939 tmp = I915_READ(VBLANK(cpu_transcoder));
4940 pipe_config->adjusted_mode.crtc_vblank_start = (tmp & 0xffff) + 1;
4941 pipe_config->adjusted_mode.crtc_vblank_end = ((tmp >> 16) & 0xffff) + 1;
4942 tmp = I915_READ(VSYNC(cpu_transcoder));
4943 pipe_config->adjusted_mode.crtc_vsync_start = (tmp & 0xffff) + 1;
4944 pipe_config->adjusted_mode.crtc_vsync_end = ((tmp >> 16) & 0xffff) + 1;
4945
4946 if (I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_INTERLACE_MASK) {
4947 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_INTERLACE;
4948 pipe_config->adjusted_mode.crtc_vtotal += 1;
4949 pipe_config->adjusted_mode.crtc_vblank_end += 1;
4950 }
4951
4952 tmp = I915_READ(PIPESRC(crtc->pipe));
37327abd
VS		 4953 pipe_config->pipe_src_h = (tmp & 0xffff) + 1;
4954 pipe_config->pipe_src_w = ((tmp >> 16) & 0xffff) + 1;
4955
4956 pipe_config->requested_mode.vdisplay = pipe_config->pipe_src_h;
4957 pipe_config->requested_mode.hdisplay = pipe_config->pipe_src_w;
1bd1bd80
DV		 4958}
4959
babea61d
JB		 4960static void intel_crtc_mode_from_pipe_config(struct intel_crtc *intel_crtc,
4961 struct intel_crtc_config *pipe_config)
4962{
4963 struct drm_crtc *crtc = &intel_crtc->base;
4964
4965 crtc->mode.hdisplay = pipe_config->adjusted_mode.crtc_hdisplay;
4966 crtc->mode.htotal = pipe_config->adjusted_mode.crtc_htotal;
4967 crtc->mode.hsync_start = pipe_config->adjusted_mode.crtc_hsync_start;
4968 crtc->mode.hsync_end = pipe_config->adjusted_mode.crtc_hsync_end;
4969
4970 crtc->mode.vdisplay = pipe_config->adjusted_mode.crtc_vdisplay;
4971 crtc->mode.vtotal = pipe_config->adjusted_mode.crtc_vtotal;
4972 crtc->mode.vsync_start = pipe_config->adjusted_mode.crtc_vsync_start;
4973 crtc->mode.vsync_end = pipe_config->adjusted_mode.crtc_vsync_end;
4974
4975 crtc->mode.flags = pipe_config->adjusted_mode.flags;
4976
241bfc38 4977 crtc->mode.clock = pipe_config->adjusted_mode.crtc_clock;
babea61d
JB		 4978 crtc->mode.flags |= pipe_config->adjusted_mode.flags;
4979}
4980
84b046f3
DV		 4981static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
4982{
4983 struct drm_device *dev = intel_crtc->base.dev;
4984 struct drm_i915_private *dev_priv = dev->dev_private;
4985 uint32_t pipeconf;
4986
9f11a9e4 4987 pipeconf = 0;
84b046f3 4988
67c72a12
DV		 4989 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
4990 I915_READ(PIPECONF(intel_crtc->pipe)) & PIPECONF_ENABLE)
4991 pipeconf |= PIPECONF_ENABLE;
4992
cf532bb2
VS		 4993 if (intel_crtc->config.double_wide)
4994 pipeconf |= PIPECONF_DOUBLE_WIDE;
84b046f3 4995
ff9ce46e
DV		 4996 /* only g4x and later have fancy bpc/dither controls */
4997 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
ff9ce46e
DV		 4998 /* Bspec claims that we can't use dithering for 30bpp pipes. */
4999 if (intel_crtc->config.dither && intel_crtc->config.pipe_bpp != 30)
5000 pipeconf |= PIPECONF_DITHER_EN |
84b046f3 5001 PIPECONF_DITHER_TYPE_SP;
84b046f3 5002
ff9ce46e
DV		 5003 switch (intel_crtc->config.pipe_bpp) {
5004 case 18:
5005 pipeconf |= PIPECONF_6BPC;
5006 break;
5007 case 24:
5008 pipeconf |= PIPECONF_8BPC;
5009 break;
5010 case 30:
5011 pipeconf |= PIPECONF_10BPC;
5012 break;
5013 default:
5014 /* Case prevented by intel_choose_pipe_bpp_dither. */
5015 BUG();
84b046f3
DV		 5016 }
5017 }
5018
5019 if (HAS_PIPE_CXSR(dev)) {
5020 if (intel_crtc->lowfreq_avail) {
5021 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5022 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5023 } else {
5024 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
84b046f3
DV		 5025 }
5026 }
5027
84b046f3
DV		 5028 if (!IS_GEN2(dev) &&
5029 intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
5030 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5031 else
5032 pipeconf |= PIPECONF_PROGRESSIVE;
5033
9f11a9e4
DV		 5034 if (IS_VALLEYVIEW(dev) && intel_crtc->config.limited_color_range)
5035 pipeconf |= PIPECONF_COLOR_RANGE_SELECT;
9c8e09b7 5036
84b046f3
DV		 5037 I915_WRITE(PIPECONF(intel_crtc->pipe), pipeconf);
5038 POSTING_READ(PIPECONF(intel_crtc->pipe));
5039}
5040
f564048e 5041static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
f564048e 5042 int x, int y,
94352cf9 5043 struct drm_framebuffer *fb)
79e53945
JB		 5044{
5045 struct drm_device *dev = crtc->dev;
5046 struct drm_i915_private *dev_priv = dev->dev_private;
5047 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5048 int pipe = intel_crtc->pipe;
80824003 5049 int plane = intel_crtc->plane;
c751ce4f 5050 int refclk, num_connectors = 0;
652c393a 5051 intel_clock_t clock, reduced_clock;
84b046f3 5052 u32 dspcntr;
a16af721 5053 bool ok, has_reduced_clock = false;
e9fd1c02 5054 bool is_lvds = false, is_dsi = false;
5eddb70b 5055 struct intel_encoder *encoder;
d4906093 5056 const intel_limit_t *limit;
5c3b82e2 5057 int ret;
79e53945 5058
6c2b7c12 5059 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 5060 switch (encoder->type) {
79e53945
JB		 5061 case INTEL_OUTPUT_LVDS:
5062 is_lvds = true;
5063 break;
e9fd1c02
JN		 5064 case INTEL_OUTPUT_DSI:
5065 is_dsi = true;
5066 break;
79e53945 5067 }
43565a06 5068
c751ce4f 5069 num_connectors++;
79e53945
JB		 5070 }
5071
f2335330
JN		 5072 if (is_dsi)
5073 goto skip_dpll;
5074
5075 if (!intel_crtc->config.clock_set) {
5076 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 5077
e9fd1c02
JN		 5078 /*
5079 * Returns a set of divisors for the desired target clock with
5080 * the given refclk, or FALSE. The returned values represent
5081 * the clock equation: reflck * (5 * (m1 + 2) + (m2 + 2)) / (n +
5082 * 2) / p1 / p2.
5083 */
5084 limit = intel_limit(crtc, refclk);
5085 ok = dev_priv->display.find_dpll(limit, crtc,
5086 intel_crtc->config.port_clock,
5087 refclk, NULL, &clock);
f2335330 5088 if (!ok) {
e9fd1c02
JN		 5089 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5090 return -EINVAL;
5091 }
79e53945 5092
f2335330
JN		 5093 if (is_lvds && dev_priv->lvds_downclock_avail) {
5094 /*
5095 * Ensure we match the reduced clock's P to the target
5096 * clock. If the clocks don't match, we can't switch
5097 * the display clock by using the FP0/FP1. In such case
5098 * we will disable the LVDS downclock feature.
5099 */
5100 has_reduced_clock =
5101 dev_priv->display.find_dpll(limit, crtc,
5102 dev_priv->lvds_downclock,
5103 refclk, &clock,
5104 &reduced_clock);
5105 }
5106 /* Compat-code for transition, will disappear. */
f47709a9
DV		 5107 intel_crtc->config.dpll.n = clock.n;
5108 intel_crtc->config.dpll.m1 = clock.m1;
5109 intel_crtc->config.dpll.m2 = clock.m2;
5110 intel_crtc->config.dpll.p1 = clock.p1;
5111 intel_crtc->config.dpll.p2 = clock.p2;
5112 }
7026d4ac 5113
e9fd1c02 5114 if (IS_GEN2(dev)) {
8a654f3b 5115 i8xx_update_pll(intel_crtc,
2a8f64ca
VP		 5116 has_reduced_clock ? &reduced_clock : NULL,
5117 num_connectors);
e9fd1c02 5118 } else if (IS_VALLEYVIEW(dev)) {
f2335330 5119 vlv_update_pll(intel_crtc);
e9fd1c02 5120 } else {
f47709a9 5121 i9xx_update_pll(intel_crtc,
eb1cbe48 5122 has_reduced_clock ? &reduced_clock : NULL,
89b667f8 5123 num_connectors);
e9fd1c02 5124 }
79e53945 5125
f2335330 5126skip_dpll:
79e53945
JB		 5127 /* Set up the display plane register */
5128 dspcntr = DISPPLANE_GAMMA_ENABLE;
5129
da6ecc5d
JB		 5130 if (!IS_VALLEYVIEW(dev)) {
5131 if (pipe == 0)
5132 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5133 else
5134 dspcntr |= DISPPLANE_SEL_PIPE_B;
5135 }
79e53945 5136
8a654f3b 5137 intel_set_pipe_timings(intel_crtc);
5eddb70b
CW		 5138
5139 /* pipesrc and dspsize control the size that is scaled from,
5140 * which should always be the user's requested size.
79e53945 5141 */
929c77fb 5142 I915_WRITE(DSPSIZE(plane),
37327abd
VS		 5143 ((intel_crtc->config.pipe_src_h - 1) << 16) |
5144 (intel_crtc->config.pipe_src_w - 1));
929c77fb 5145 I915_WRITE(DSPPOS(plane), 0);
2c07245f 5146
84b046f3
DV		 5147 i9xx_set_pipeconf(intel_crtc);
5148
f564048e
EA		 5149 I915_WRITE(DSPCNTR(plane), dspcntr);
5150 POSTING_READ(DSPCNTR(plane));
5151
94352cf9 5152 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e 5153
f564048e
EA		 5154 return ret;
5155}
5156
2fa2fe9a
DV		 5157static void i9xx_get_pfit_config(struct intel_crtc *crtc,
5158 struct intel_crtc_config *pipe_config)
5159{
5160 struct drm_device *dev = crtc->base.dev;
5161 struct drm_i915_private *dev_priv = dev->dev_private;
5162 uint32_t tmp;
5163
5164 tmp = I915_READ(PFIT_CONTROL);
06922821
DV		 5165 if (!(tmp & PFIT_ENABLE))
5166 return;
2fa2fe9a 5167
06922821 5168 /* Check whether the pfit is attached to our pipe. */
2fa2fe9a
DV		 5169 if (INTEL_INFO(dev)->gen < 4) {
5170 if (crtc->pipe != PIPE_B)
5171 return;
2fa2fe9a
DV		 5172 } else {
5173 if ((tmp & PFIT_PIPE_MASK) != (crtc->pipe << PFIT_PIPE_SHIFT))
5174 return;
5175 }
5176
06922821 5177 pipe_config->gmch_pfit.control = tmp;
2fa2fe9a
DV		 5178 pipe_config->gmch_pfit.pgm_ratios = I915_READ(PFIT_PGM_RATIOS);
5179 if (INTEL_INFO(dev)->gen < 5)
5180 pipe_config->gmch_pfit.lvds_border_bits =
5181 I915_READ(LVDS) & LVDS_BORDER_ENABLE;
5182}
5183
acbec814
JB		 5184static void vlv_crtc_clock_get(struct intel_crtc *crtc,
5185 struct intel_crtc_config *pipe_config)
5186{
5187 struct drm_device *dev = crtc->base.dev;
5188 struct drm_i915_private *dev_priv = dev->dev_private;
5189 int pipe = pipe_config->cpu_transcoder;
5190 intel_clock_t clock;
5191 u32 mdiv;
662c6ecb 5192 int refclk = 100000;
acbec814
JB		 5193
5194 mutex_lock(&dev_priv->dpio_lock);
5195 mdiv = vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe));
5196 mutex_unlock(&dev_priv->dpio_lock);
5197
5198 clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
5199 clock.m2 = mdiv & DPIO_M2DIV_MASK;
5200 clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
5201 clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
5202 clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
5203
662c6ecb
CW		 5204 clock.vco = refclk * clock.m1 * clock.m2 / clock.n;
5205 clock.dot = 2 * clock.vco / (clock.p1 * clock.p2);
acbec814
JB		 5206
5207 pipe_config->port_clock = clock.dot / 10;
5208}
5209
0e8ffe1b
DV		 5210static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
5211 struct intel_crtc_config *pipe_config)
5212{
5213 struct drm_device *dev = crtc->base.dev;
5214 struct drm_i915_private *dev_priv = dev->dev_private;
5215 uint32_t tmp;
5216
e143a21c 5217 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 5218 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 5219
0e8ffe1b
DV		 5220 tmp = I915_READ(PIPECONF(crtc->pipe));
5221 if (!(tmp & PIPECONF_ENABLE))
5222 return false;
5223
42571aef
VS		 5224 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
5225 switch (tmp & PIPECONF_BPC_MASK) {
5226 case PIPECONF_6BPC:
5227 pipe_config->pipe_bpp = 18;
5228 break;
5229 case PIPECONF_8BPC:
5230 pipe_config->pipe_bpp = 24;
5231 break;
5232 case PIPECONF_10BPC:
5233 pipe_config->pipe_bpp = 30;
5234 break;
5235 default:
5236 break;
5237 }
5238 }
5239
282740f7
VS		 5240 if (INTEL_INFO(dev)->gen < 4)
5241 pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
5242
1bd1bd80
DV		 5243 intel_get_pipe_timings(crtc, pipe_config);
5244
2fa2fe9a
DV		 5245 i9xx_get_pfit_config(crtc, pipe_config);
5246
6c49f241
DV		 5247 if (INTEL_INFO(dev)->gen >= 4) {
5248 tmp = I915_READ(DPLL_MD(crtc->pipe));
5249 pipe_config->pixel_multiplier =
5250 ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
5251 >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
8bcc2795 5252 pipe_config->dpll_hw_state.dpll_md = tmp;
6c49f241
DV		 5253 } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
5254 tmp = I915_READ(DPLL(crtc->pipe));
5255 pipe_config->pixel_multiplier =
5256 ((tmp & SDVO_MULTIPLIER_MASK)
5257 >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
5258 } else {
5259 /* Note that on i915G/GM the pixel multiplier is in the sdvo
5260 * port and will be fixed up in the encoder->get_config
5261 * function. */
5262 pipe_config->pixel_multiplier = 1;
5263 }
8bcc2795
DV		 5264 pipe_config->dpll_hw_state.dpll = I915_READ(DPLL(crtc->pipe));
5265 if (!IS_VALLEYVIEW(dev)) {
5266 pipe_config->dpll_hw_state.fp0 = I915_READ(FP0(crtc->pipe));
5267 pipe_config->dpll_hw_state.fp1 = I915_READ(FP1(crtc->pipe));
165e901c
VS		 5268 } else {
5269 /* Mask out read-only status bits. */
5270 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
5271 DPLL_PORTC_READY_MASK |
5272 DPLL_PORTB_READY_MASK);
8bcc2795 5273 }
6c49f241 5274
acbec814
JB		 5275 if (IS_VALLEYVIEW(dev))
5276 vlv_crtc_clock_get(crtc, pipe_config);
5277 else
5278 i9xx_crtc_clock_get(crtc, pipe_config);
18442d08 5279
0e8ffe1b
DV		 5280 return true;
5281}
5282
dde86e2d 5283static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5284{
5285 struct drm_i915_private *dev_priv = dev->dev_private;
5286 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5287 struct intel_encoder *encoder;
74cfd7ac 5288 u32 val, final;
13d83a67 5289 bool has_lvds = false;
199e5d79 5290 bool has_cpu_edp = false;
199e5d79 5291 bool has_panel = false;
99eb6a01
KP		 5292 bool has_ck505 = false;
5293 bool can_ssc = false;
13d83a67
JB		 5294
5295 /* We need to take the global config into account */
199e5d79
KP		 5296 list_for_each_entry(encoder, &mode_config->encoder_list,
5297 base.head) {
5298 switch (encoder->type) {
5299 case INTEL_OUTPUT_LVDS:
5300 has_panel = true;
5301 has_lvds = true;
5302 break;
5303 case INTEL_OUTPUT_EDP:
5304 has_panel = true;
2de6905f 5305 if (enc_to_dig_port(&encoder->base)->port == PORT_A)
199e5d79
KP		 5306 has_cpu_edp = true;
5307 break;
13d83a67
JB		 5308 }
5309 }
5310
99eb6a01 5311 if (HAS_PCH_IBX(dev)) {
41aa3448 5312 has_ck505 = dev_priv->vbt.display_clock_mode;
99eb6a01
KP		 5313 can_ssc = has_ck505;
5314 } else {
5315 has_ck505 = false;
5316 can_ssc = true;
5317 }
5318
2de6905f
ID		 5319 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_ck505 %d\n",
5320 has_panel, has_lvds, has_ck505);
13d83a67
JB		 5321
5322 /* Ironlake: try to setup display ref clock before DPLL
5323 * enabling. This is only under driver's control after
5324 * PCH B stepping, previous chipset stepping should be
5325 * ignoring this setting.
5326 */
74cfd7ac
CW		 5327 val = I915_READ(PCH_DREF_CONTROL);
5328
5329 /* As we must carefully and slowly disable/enable each source in turn,
5330 * compute the final state we want first and check if we need to
5331 * make any changes at all.
5332 */
5333 final = val;
5334 final &= ~DREF_NONSPREAD_SOURCE_MASK;
5335 if (has_ck505)
5336 final |= DREF_NONSPREAD_CK505_ENABLE;
5337 else
5338 final |= DREF_NONSPREAD_SOURCE_ENABLE;
5339
5340 final &= ~DREF_SSC_SOURCE_MASK;
5341 final &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5342 final &= ~DREF_SSC1_ENABLE;
5343
5344 if (has_panel) {
5345 final |= DREF_SSC_SOURCE_ENABLE;
5346
5347 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5348 final |= DREF_SSC1_ENABLE;
5349
5350 if (has_cpu_edp) {
5351 if (intel_panel_use_ssc(dev_priv) && can_ssc)
5352 final |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
5353 else
5354 final |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
5355 } else
5356 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5357 } else {
5358 final |= DREF_SSC_SOURCE_DISABLE;
5359 final |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5360 }
5361
5362 if (final == val)
5363 return;
5364
13d83a67 5365 /* Always enable nonspread source */
74cfd7ac 5366 val &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5367
99eb6a01 5368 if (has_ck505)
74cfd7ac 5369 val |= DREF_NONSPREAD_CK505_ENABLE;
99eb6a01 5370 else
74cfd7ac 5371 val |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5372
199e5d79 5373 if (has_panel) {
74cfd7ac
CW		 5374 val &= ~DREF_SSC_SOURCE_MASK;
5375 val |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5376
199e5d79 5377 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5378 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5379 DRM_DEBUG_KMS("Using SSC on panel\n");
74cfd7ac 5380 val |= DREF_SSC1_ENABLE;
e77166b5 5381 } else
74cfd7ac 5382 val &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 5383
5384 /* Get SSC going before enabling the outputs */
74cfd7ac 5385 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5386 POSTING_READ(PCH_DREF_CONTROL);
5387 udelay(200);
5388
74cfd7ac 5389 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
13d83a67
JB		 5390
5391 /* Enable CPU source on CPU attached eDP */
199e5d79 5392 if (has_cpu_edp) {
99eb6a01 5393 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5394 DRM_DEBUG_KMS("Using SSC on eDP\n");
74cfd7ac 5395 val |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5396 }
13d83a67 5397 else
74cfd7ac 5398 val |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79 5399 } else
74cfd7ac 5400 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5401
74cfd7ac 5402 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5403 POSTING_READ(PCH_DREF_CONTROL);
5404 udelay(200);
5405 } else {
5406 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5407
74cfd7ac 5408 val &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
199e5d79
KP		 5409
5410 /* Turn off CPU output */
74cfd7ac 5411 val |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
199e5d79 5412
74cfd7ac 5413 I915_WRITE(PCH_DREF_CONTROL, val);
199e5d79
KP		 5414 POSTING_READ(PCH_DREF_CONTROL);
5415 udelay(200);
5416
5417 /* Turn off the SSC source */
74cfd7ac
CW		 5418 val &= ~DREF_SSC_SOURCE_MASK;
5419 val |= DREF_SSC_SOURCE_DISABLE;
199e5d79
KP		 5420
5421 /* Turn off SSC1 */
74cfd7ac 5422 val &= ~DREF_SSC1_ENABLE;
199e5d79 5423
74cfd7ac 5424 I915_WRITE(PCH_DREF_CONTROL, val);
13d83a67
JB		 5425 POSTING_READ(PCH_DREF_CONTROL);
5426 udelay(200);
5427 }
74cfd7ac
CW		 5428
5429 BUG_ON(val != final);
13d83a67
JB		 5430}
5431
f31f2d55 5432static void lpt_reset_fdi_mphy(struct drm_i915_private *dev_priv)
dde86e2d 5433{
f31f2d55 5434 uint32_t tmp;
dde86e2d 5435
0ff066a9
PZ		 5436 tmp = I915_READ(SOUTH_CHICKEN2);
5437 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
5438 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5439
0ff066a9
PZ		 5440 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
5441 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
5442 DRM_ERROR("FDI mPHY reset assert timeout\n");
dde86e2d 5443
0ff066a9
PZ		 5444 tmp = I915_READ(SOUTH_CHICKEN2);
5445 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
5446 I915_WRITE(SOUTH_CHICKEN2, tmp);
dde86e2d 5447
0ff066a9
PZ		 5448 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
5449 FDI_MPHY_IOSFSB_RESET_STATUS) == 0, 100))
5450 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
f31f2d55
PZ		 5451}
5452
5453/* WaMPhyProgramming:hsw */
5454static void lpt_program_fdi_mphy(struct drm_i915_private *dev_priv)
5455{
5456 uint32_t tmp;
dde86e2d
PZ		 5457
5458 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
5459 tmp &= ~(0xFF << 24);
5460 tmp |= (0x12 << 24);
5461 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
5462
dde86e2d
PZ		 5463 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
5464 tmp |= (1 << 11);
5465 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
5466
5467 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
5468 tmp |= (1 << 11);
5469 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
5470
dde86e2d
PZ		 5471 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
5472 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5473 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
5474
5475 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
5476 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
5477 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
5478
0ff066a9
PZ		 5479 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
5480 tmp &= ~(7 << 13);
5481 tmp |= (5 << 13);
5482 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
dde86e2d 5483
0ff066a9
PZ		 5484 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
5485 tmp &= ~(7 << 13);
5486 tmp |= (5 << 13);
5487 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
dde86e2d
PZ		 5488
5489 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
5490 tmp &= ~0xFF;
5491 tmp |= 0x1C;
5492 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
5493
5494 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
5495 tmp &= ~0xFF;
5496 tmp |= 0x1C;
5497 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
5498
5499 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
5500 tmp &= ~(0xFF << 16);
5501 tmp |= (0x1C << 16);
5502 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
5503
5504 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
5505 tmp &= ~(0xFF << 16);
5506 tmp |= (0x1C << 16);
5507 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5508
0ff066a9
PZ		 5509 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5510 tmp |= (1 << 27);
5511 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
dde86e2d 5512
0ff066a9
PZ		 5513 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5514 tmp |= (1 << 27);
5515 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
dde86e2d 5516
0ff066a9
PZ		 5517 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5518 tmp &= ~(0xF << 28);
5519 tmp |= (4 << 28);
5520 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
dde86e2d 5521
0ff066a9
PZ		 5522 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5523 tmp &= ~(0xF << 28);
5524 tmp |= (4 << 28);
5525 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
f31f2d55
PZ		 5526}
5527
2fa86a1f
PZ		 5528/* Implements 3 different sequences from BSpec chapter "Display iCLK
5529 * Programming" based on the parameters passed:
5530 * - Sequence to enable CLKOUT_DP
5531 * - Sequence to enable CLKOUT_DP without spread
5532 * - Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O
5533 */
5534static void lpt_enable_clkout_dp(struct drm_device *dev, bool with_spread,
5535 bool with_fdi)
f31f2d55
PZ		 5536{
5537 struct drm_i915_private *dev_priv = dev->dev_private;
2fa86a1f
PZ		 5538 uint32_t reg, tmp;
5539
5540 if (WARN(with_fdi && !with_spread, "FDI requires downspread\n"))
5541 with_spread = true;
5542 if (WARN(dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE &&
5543 with_fdi, "LP PCH doesn't have FDI\n"))
5544 with_fdi = false;
f31f2d55
PZ		 5545
5546 mutex_lock(&dev_priv->dpio_lock);
5547
5548 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5549 tmp &= ~SBI_SSCCTL_DISABLE;
5550 tmp |= SBI_SSCCTL_PATHALT;
5551 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5552
5553 udelay(24);
5554
2fa86a1f
PZ		 5555 if (with_spread) {
5556 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5557 tmp &= ~SBI_SSCCTL_PATHALT;
5558 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
f31f2d55 5559
2fa86a1f
PZ		 5560 if (with_fdi) {
5561 lpt_reset_fdi_mphy(dev_priv);
5562 lpt_program_fdi_mphy(dev_priv);
5563 }
5564 }
dde86e2d 5565
2fa86a1f
PZ		 5566 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5567 SBI_GEN0 : SBI_DBUFF0;
5568 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5569 tmp |= SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5570 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
c00db246
DV		 5571
5572 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5573}
5574
47701c3b
PZ		 5575/* Sequence to disable CLKOUT_DP */
5576static void lpt_disable_clkout_dp(struct drm_device *dev)
5577{
5578 struct drm_i915_private *dev_priv = dev->dev_private;
5579 uint32_t reg, tmp;
5580
5581 mutex_lock(&dev_priv->dpio_lock);
5582
5583 reg = (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) ?
5584 SBI_GEN0 : SBI_DBUFF0;
5585 tmp = intel_sbi_read(dev_priv, reg, SBI_ICLK);
5586 tmp &= ~SBI_GEN0_CFG_BUFFENABLE_DISABLE;
5587 intel_sbi_write(dev_priv, reg, tmp, SBI_ICLK);
5588
5589 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
5590 if (!(tmp & SBI_SSCCTL_DISABLE)) {
5591 if (!(tmp & SBI_SSCCTL_PATHALT)) {
5592 tmp |= SBI_SSCCTL_PATHALT;
5593 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5594 udelay(32);
5595 }
5596 tmp |= SBI_SSCCTL_DISABLE;
5597 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
5598 }
5599
5600 mutex_unlock(&dev_priv->dpio_lock);
5601}
5602
bf8fa3d3
PZ		 5603static void lpt_init_pch_refclk(struct drm_device *dev)
5604{
5605 struct drm_mode_config *mode_config = &dev->mode_config;
5606 struct intel_encoder *encoder;
5607 bool has_vga = false;
5608
5609 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5610 switch (encoder->type) {
5611 case INTEL_OUTPUT_ANALOG:
5612 has_vga = true;
5613 break;
5614 }
5615 }
5616
47701c3b
PZ		 5617 if (has_vga)
5618 lpt_enable_clkout_dp(dev, true, true);
5619 else
5620 lpt_disable_clkout_dp(dev);
bf8fa3d3
PZ		 5621}
5622
dde86e2d
PZ		 5623/*
5624 * Initialize reference clocks when the driver loads
5625 */
5626void intel_init_pch_refclk(struct drm_device *dev)
5627{
5628 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5629 ironlake_init_pch_refclk(dev);
5630 else if (HAS_PCH_LPT(dev))
5631 lpt_init_pch_refclk(dev);
5632}
5633
d9d444cb
JB		 5634static int ironlake_get_refclk(struct drm_crtc *crtc)
5635{
5636 struct drm_device *dev = crtc->dev;
5637 struct drm_i915_private *dev_priv = dev->dev_private;
5638 struct intel_encoder *encoder;
d9d444cb
JB		 5639 int num_connectors = 0;
5640 bool is_lvds = false;
5641
6c2b7c12 5642 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5643 switch (encoder->type) {
5644 case INTEL_OUTPUT_LVDS:
5645 is_lvds = true;
5646 break;
d9d444cb
JB		 5647 }
5648 num_connectors++;
5649 }
5650
5651 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5652 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
41aa3448
RV		 5653 dev_priv->vbt.lvds_ssc_freq);
5654 return dev_priv->vbt.lvds_ssc_freq * 1000;
d9d444cb
JB		 5655 }
5656
5657 return 120000;
5658}
5659
6ff93609 5660static void ironlake_set_pipeconf(struct drm_crtc *crtc)
79e53945 5661{
c8203565 5662 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5663 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5664 int pipe = intel_crtc->pipe;
c8203565
PZ		 5665 uint32_t val;
5666
78114071 5667 val = 0;
c8203565 5668
965e0c48 5669 switch (intel_crtc->config.pipe_bpp) {
c8203565 5670 case 18:
dfd07d72 5671 val |= PIPECONF_6BPC;
c8203565
PZ		 5672 break;
5673 case 24:
dfd07d72 5674 val |= PIPECONF_8BPC;
c8203565
PZ		 5675 break;
5676 case 30:
dfd07d72 5677 val |= PIPECONF_10BPC;
c8203565
PZ		 5678 break;
5679 case 36:
dfd07d72 5680 val |= PIPECONF_12BPC;
c8203565
PZ		 5681 break;
5682 default:
cc769b62
PZ		 5683 /* Case prevented by intel_choose_pipe_bpp_dither. */
5684 BUG();
c8203565
PZ		 5685 }
5686
d8b32247 5687 if (intel_crtc->config.dither)
c8203565
PZ		 5688 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5689
6ff93609 5690 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
c8203565
PZ		 5691 val |= PIPECONF_INTERLACED_ILK;
5692 else
5693 val |= PIPECONF_PROGRESSIVE;
5694
50f3b016 5695 if (intel_crtc->config.limited_color_range)
3685a8f3 5696 val |= PIPECONF_COLOR_RANGE_SELECT;
3685a8f3 5697
c8203565
PZ		 5698 I915_WRITE(PIPECONF(pipe), val);
5699 POSTING_READ(PIPECONF(pipe));
5700}
5701
86d3efce
VS		 5702/*
5703 * Set up the pipe CSC unit.
5704 *
5705 * Currently only full range RGB to limited range RGB conversion
5706 * is supported, but eventually this should handle various
5707 * RGB<->YCbCr scenarios as well.
5708 */
50f3b016 5709static void intel_set_pipe_csc(struct drm_crtc *crtc)
86d3efce
VS		 5710{
5711 struct drm_device *dev = crtc->dev;
5712 struct drm_i915_private *dev_priv = dev->dev_private;
5713 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5714 int pipe = intel_crtc->pipe;
5715 uint16_t coeff = 0x7800; /* 1.0 */
5716
5717 /*
5718 * TODO: Check what kind of values actually come out of the pipe
5719 * with these coeff/postoff values and adjust to get the best
5720 * accuracy. Perhaps we even need to take the bpc value into
5721 * consideration.
5722 */
5723
50f3b016 5724 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5725 coeff = ((235 - 16) * (1 << 12) / 255) & 0xff8; /* 0.xxx... */
5726
5727 /*
5728 * GY/GU and RY/RU should be the other way around according
5729 * to BSpec, but reality doesn't agree. Just set them up in
5730 * a way that results in the correct picture.
5731 */
5732 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff << 16);
5733 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), 0);
5734
5735 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff);
5736 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), 0);
5737
5738 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), 0);
5739 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff << 16);
5740
5741 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), 0);
5742 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), 0);
5743 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), 0);
5744
5745 if (INTEL_INFO(dev)->gen > 6) {
5746 uint16_t postoff = 0;
5747
50f3b016 5748 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5749 postoff = (16 * (1 << 13) / 255) & 0x1fff;
5750
5751 I915_WRITE(PIPE_CSC_POSTOFF_HI(pipe), postoff);
5752 I915_WRITE(PIPE_CSC_POSTOFF_ME(pipe), postoff);
5753 I915_WRITE(PIPE_CSC_POSTOFF_LO(pipe), postoff);
5754
5755 I915_WRITE(PIPE_CSC_MODE(pipe), 0);
5756 } else {
5757 uint32_t mode = CSC_MODE_YUV_TO_RGB;
5758
50f3b016 5759 if (intel_crtc->config.limited_color_range)
86d3efce
VS		 5760 mode |= CSC_BLACK_SCREEN_OFFSET;
5761
5762 I915_WRITE(PIPE_CSC_MODE(pipe), mode);
5763 }
5764}
5765
6ff93609 5766static void haswell_set_pipeconf(struct drm_crtc *crtc)
ee2b0b38
PZ		 5767{
5768 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5769 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 5770 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
ee2b0b38
PZ		 5771 uint32_t val;
5772
3eff4faa 5773 val = 0;
ee2b0b38 5774
d8b32247 5775 if (intel_crtc->config.dither)
ee2b0b38
PZ		 5776 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5777
6ff93609 5778 if (intel_crtc->config.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
ee2b0b38
PZ		 5779 val |= PIPECONF_INTERLACED_ILK;
5780 else
5781 val |= PIPECONF_PROGRESSIVE;
5782
702e7a56
PZ		 5783 I915_WRITE(PIPECONF(cpu_transcoder), val);
5784 POSTING_READ(PIPECONF(cpu_transcoder));
3eff4faa
DV		 5785
5786 I915_WRITE(GAMMA_MODE(intel_crtc->pipe), GAMMA_MODE_MODE_8BIT);
5787 POSTING_READ(GAMMA_MODE(intel_crtc->pipe));
ee2b0b38
PZ		 5788}
5789
6591c6e4 5790static bool ironlake_compute_clocks(struct drm_crtc *crtc,
6591c6e4
PZ		 5791 intel_clock_t *clock,
5792 bool *has_reduced_clock,
5793 intel_clock_t *reduced_clock)
5794{
5795 struct drm_device *dev = crtc->dev;
5796 struct drm_i915_private *dev_priv = dev->dev_private;
5797 struct intel_encoder *intel_encoder;
5798 int refclk;
d4906093 5799 const intel_limit_t *limit;
a16af721 5800 bool ret, is_lvds = false;
79e53945 5801
6591c6e4
PZ		 5802 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5803 switch (intel_encoder->type) {
79e53945
JB		 5804 case INTEL_OUTPUT_LVDS:
5805 is_lvds = true;
5806 break;
79e53945
JB		 5807 }
5808 }
5809
d9d444cb 5810 refclk = ironlake_get_refclk(crtc);
79e53945 5811
d4906093
ML		 5812 /*
5813 * Returns a set of divisors for the desired target clock with the given
5814 * refclk, or FALSE. The returned values represent the clock equation:
5815 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5816 */
1b894b59 5817 limit = intel_limit(crtc, refclk);
ff9a6750
DV		 5818 ret = dev_priv->display.find_dpll(limit, crtc,
5819 to_intel_crtc(crtc)->config.port_clock,
ee9300bb 5820 refclk, NULL, clock);
6591c6e4
PZ		 5821 if (!ret)
5822 return false;
cda4b7d3 5823
ddc9003c 5824 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5825 /*
5826 * Ensure we match the reduced clock's P to the target clock.
5827 * If the clocks don't match, we can't switch the display clock
5828 * by using the FP0/FP1. In such case we will disable the LVDS
5829 * downclock feature.
5830 */
ee9300bb
DV		 5831 *has_reduced_clock =
5832 dev_priv->display.find_dpll(limit, crtc,
5833 dev_priv->lvds_downclock,
5834 refclk, clock,
5835 reduced_clock);
652c393a 5836 }
61e9653f 5837
6591c6e4
PZ		 5838 return true;
5839}
5840
01a415fd
DV		 5841static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5842{
5843 struct drm_i915_private *dev_priv = dev->dev_private;
5844 uint32_t temp;
5845
5846 temp = I915_READ(SOUTH_CHICKEN1);
5847 if (temp & FDI_BC_BIFURCATION_SELECT)
5848 return;
5849
5850 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5851 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5852
5853 temp |= FDI_BC_BIFURCATION_SELECT;
5854 DRM_DEBUG_KMS("enabling fdi C rx\n");
5855 I915_WRITE(SOUTH_CHICKEN1, temp);
5856 POSTING_READ(SOUTH_CHICKEN1);
5857}
5858
ebfd86fd 5859static void ivybridge_update_fdi_bc_bifurcation(struct intel_crtc *intel_crtc)
01a415fd
DV		 5860{
5861 struct drm_device *dev = intel_crtc->base.dev;
5862 struct drm_i915_private *dev_priv = dev->dev_private;
01a415fd
DV		 5863
5864 switch (intel_crtc->pipe) {
5865 case PIPE_A:
ebfd86fd 5866 break;
01a415fd 5867 case PIPE_B:
ebfd86fd 5868 if (intel_crtc->config.fdi_lanes > 2)
01a415fd
DV		 5869 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5870 else
5871 cpt_enable_fdi_bc_bifurcation(dev);
5872
ebfd86fd 5873 break;
01a415fd 5874 case PIPE_C:
01a415fd
DV		 5875 cpt_enable_fdi_bc_bifurcation(dev);
5876
ebfd86fd 5877 break;
01a415fd
DV		 5878 default:
5879 BUG();
5880 }
5881}
5882
d4b1931c
PZ		 5883int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5884{
5885 /*
5886 * Account for spread spectrum to avoid
5887 * oversubscribing the link. Max center spread
5888 * is 2.5%; use 5% for safety's sake.
5889 */
5890 u32 bps = target_clock * bpp * 21 / 20;
5891 return bps / (link_bw * 8) + 1;
5892}
5893
7429e9d4 5894static bool ironlake_needs_fb_cb_tune(struct dpll *dpll, int factor)
6cf86a5e 5895{
7429e9d4 5896 return i9xx_dpll_compute_m(dpll) < factor * dpll->n;
f48d8f23
PZ		 5897}
5898
de13a2e3 5899static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
7429e9d4 5900 u32 *fp,
9a7c7890 5901 intel_clock_t *reduced_clock, u32 *fp2)
79e53945 5902{
de13a2e3 5903 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5904 struct drm_device *dev = crtc->dev;
5905 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5906 struct intel_encoder *intel_encoder;
5907 uint32_t dpll;
6cc5f341 5908 int factor, num_connectors = 0;
09ede541 5909 bool is_lvds = false, is_sdvo = false;
79e53945 5910
de13a2e3
PZ		 5911 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5912 switch (intel_encoder->type) {
79e53945
JB		 5913 case INTEL_OUTPUT_LVDS:
5914 is_lvds = true;
5915 break;
5916 case INTEL_OUTPUT_SDVO:
7d57382e 5917 case INTEL_OUTPUT_HDMI:
79e53945 5918 is_sdvo = true;
79e53945 5919 break;
79e53945 5920 }
43565a06 5921
c751ce4f 5922 num_connectors++;
79e53945 5923 }
79e53945 5924
c1858123 5925 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5926 factor = 21;
5927 if (is_lvds) {
5928 if ((intel_panel_use_ssc(dev_priv) &&
41aa3448 5929 dev_priv->vbt.lvds_ssc_freq == 100) ||
f0b44056 5930 (HAS_PCH_IBX(dev) && intel_is_dual_link_lvds(dev)))
8febb297 5931 factor = 25;
09ede541 5932 } else if (intel_crtc->config.sdvo_tv_clock)
8febb297 5933 factor = 20;
c1858123 5934
7429e9d4 5935 if (ironlake_needs_fb_cb_tune(&intel_crtc->config.dpll, factor))
7d0ac5b7 5936 *fp |= FP_CB_TUNE;
2c07245f 5937
9a7c7890
DV		 5938 if (fp2 && (reduced_clock->m < factor * reduced_clock->n))
5939 *fp2 |= FP_CB_TUNE;
5940
5eddb70b 5941 dpll = 0;
2c07245f 5942
a07d6787
EA		 5943 if (is_lvds)
5944 dpll |= DPLLB_MODE_LVDS;
5945 else
5946 dpll |= DPLLB_MODE_DAC_SERIAL;
198a037f 5947
ef1b460d
DV		 5948 dpll |= (intel_crtc->config.pixel_multiplier - 1)
5949 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
198a037f
DV		 5950
5951 if (is_sdvo)
4a33e48d 5952 dpll |= DPLL_SDVO_HIGH_SPEED;
9566e9af 5953 if (intel_crtc->config.has_dp_encoder)
4a33e48d 5954 dpll |= DPLL_SDVO_HIGH_SPEED;
79e53945 5955
a07d6787 5956 /* compute bitmask from p1 value */
7429e9d4 5957 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5958 /* also FPA1 */
7429e9d4 5959 dpll |= (1 << (intel_crtc->config.dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5960
7429e9d4 5961 switch (intel_crtc->config.dpll.p2) {
a07d6787
EA		 5962 case 5:
5963 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5964 break;
5965 case 7:
5966 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5967 break;
5968 case 10:
5969 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5970 break;
5971 case 14:
5972 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5973 break;
79e53945
JB		 5974 }
5975
b4c09f3b 5976 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5977 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5978 else
5979 dpll |= PLL_REF_INPUT_DREFCLK;
5980
959e16d6 5981 return dpll | DPLL_VCO_ENABLE;
de13a2e3
PZ		 5982}
5983
5984static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
de13a2e3
PZ		 5985 int x, int y,
5986 struct drm_framebuffer *fb)
5987{
5988 struct drm_device *dev = crtc->dev;
5989 struct drm_i915_private *dev_priv = dev->dev_private;
5990 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5991 int pipe = intel_crtc->pipe;
5992 int plane = intel_crtc->plane;
5993 int num_connectors = 0;
5994 intel_clock_t clock, reduced_clock;
cbbab5bd 5995 u32 dpll = 0, fp = 0, fp2 = 0;
e2f12b07 5996 bool ok, has_reduced_clock = false;
8b47047b 5997 bool is_lvds = false;
de13a2e3 5998 struct intel_encoder *encoder;
e2b78267 5999 struct intel_shared_dpll *pll;
de13a2e3 6000 int ret;
de13a2e3
PZ		 6001
6002 for_each_encoder_on_crtc(dev, crtc, encoder) {
6003 switch (encoder->type) {
6004 case INTEL_OUTPUT_LVDS:
6005 is_lvds = true;
6006 break;
de13a2e3
PZ		 6007 }
6008
6009 num_connectors++;
a07d6787 6010 }
79e53945 6011
5dc5298b
PZ		 6012 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
6013 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 6014
ff9a6750 6015 ok = ironlake_compute_clocks(crtc, &clock,
de13a2e3 6016 &has_reduced_clock, &reduced_clock);
ee9300bb 6017 if (!ok && !intel_crtc->config.clock_set) {
de13a2e3
PZ		 6018 DRM_ERROR("Couldn't find PLL settings for mode!\n");
6019 return -EINVAL;
79e53945 6020 }
f47709a9
DV		 6021 /* Compat-code for transition, will disappear. */
6022 if (!intel_crtc->config.clock_set) {
6023 intel_crtc->config.dpll.n = clock.n;
6024 intel_crtc->config.dpll.m1 = clock.m1;
6025 intel_crtc->config.dpll.m2 = clock.m2;
6026 intel_crtc->config.dpll.p1 = clock.p1;
6027 intel_crtc->config.dpll.p2 = clock.p2;
6028 }
79e53945 6029
5dc5298b 6030 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
8b47047b 6031 if (intel_crtc->config.has_pch_encoder) {
7429e9d4 6032 fp = i9xx_dpll_compute_fp(&intel_crtc->config.dpll);
cbbab5bd 6033 if (has_reduced_clock)
7429e9d4 6034 fp2 = i9xx_dpll_compute_fp(&reduced_clock);
cbbab5bd 6035
7429e9d4 6036 dpll = ironlake_compute_dpll(intel_crtc,
cbbab5bd
DV		 6037 &fp, &reduced_clock,
6038 has_reduced_clock ? &fp2 : NULL);
6039
959e16d6 6040 intel_crtc->config.dpll_hw_state.dpll = dpll;
66e985c0
DV		 6041 intel_crtc->config.dpll_hw_state.fp0 = fp;
6042 if (has_reduced_clock)
6043 intel_crtc->config.dpll_hw_state.fp1 = fp2;
6044 else
6045 intel_crtc->config.dpll_hw_state.fp1 = fp;
6046
b89a1d39 6047 pll = intel_get_shared_dpll(intel_crtc);
ee7b9f93 6048 if (pll == NULL) {
84f44ce7
VS		 6049 DRM_DEBUG_DRIVER("failed to find PLL for pipe %c\n",
6050 pipe_name(pipe));
4b645f14
JB		 6051 return -EINVAL;
6052 }
ee7b9f93 6053 } else
e72f9fbf 6054 intel_put_shared_dpll(intel_crtc);
79e53945 6055
03afc4a2
DV		 6056 if (intel_crtc->config.has_dp_encoder)
6057 intel_dp_set_m_n(intel_crtc);
79e53945 6058
bcd644e0
DV		 6059 if (is_lvds && has_reduced_clock && i915_powersave)
6060 intel_crtc->lowfreq_avail = true;
6061 else
6062 intel_crtc->lowfreq_avail = false;
e2b78267
DV		 6063
6064 if (intel_crtc->config.has_pch_encoder) {
6065 pll = intel_crtc_to_shared_dpll(intel_crtc);
6066
652c393a
JB		 6067 }
6068
8a654f3b 6069 intel_set_pipe_timings(intel_crtc);
5eddb70b 6070
ca3a0ff8 6071 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6072 intel_cpu_transcoder_set_m_n(intel_crtc,
6073 &intel_crtc->config.fdi_m_n);
6074 }
2c07245f 6075
ebfd86fd
DV		 6076 if (IS_IVYBRIDGE(dev))
6077 ivybridge_update_fdi_bc_bifurcation(intel_crtc);
79e53945 6078
6ff93609 6079 ironlake_set_pipeconf(crtc);
79e53945 6080
a1f9e77e
PZ		 6081 /* Set up the display plane register */
6082 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 6083 POSTING_READ(DSPCNTR(plane));
79e53945 6084
94352cf9 6085 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd 6086
1857e1da 6087 return ret;
79e53945
JB		 6088}
6089
eb14cb74
VS		 6090static void intel_pch_transcoder_get_m_n(struct intel_crtc *crtc,
6091 struct intel_link_m_n *m_n)
6092{
6093 struct drm_device *dev = crtc->base.dev;
6094 struct drm_i915_private *dev_priv = dev->dev_private;
6095 enum pipe pipe = crtc->pipe;
6096
6097 m_n->link_m = I915_READ(PCH_TRANS_LINK_M1(pipe));
6098 m_n->link_n = I915_READ(PCH_TRANS_LINK_N1(pipe));
6099 m_n->gmch_m = I915_READ(PCH_TRANS_DATA_M1(pipe))
6100 & ~TU_SIZE_MASK;
6101 m_n->gmch_n = I915_READ(PCH_TRANS_DATA_N1(pipe));
6102 m_n->tu = ((I915_READ(PCH_TRANS_DATA_M1(pipe))
6103 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6104}
6105
6106static void intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc,
6107 enum transcoder transcoder,
6108 struct intel_link_m_n *m_n)
72419203
DV		 6109{
6110 struct drm_device *dev = crtc->base.dev;
6111 struct drm_i915_private *dev_priv = dev->dev_private;
eb14cb74 6112 enum pipe pipe = crtc->pipe;
72419203 6113
eb14cb74
VS		 6114 if (INTEL_INFO(dev)->gen >= 5) {
6115 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder));
6116 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder));
6117 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder))
6118 & ~TU_SIZE_MASK;
6119 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder));
6120 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder))
6121 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6122 } else {
6123 m_n->link_m = I915_READ(PIPE_LINK_M_G4X(pipe));
6124 m_n->link_n = I915_READ(PIPE_LINK_N_G4X(pipe));
6125 m_n->gmch_m = I915_READ(PIPE_DATA_M_G4X(pipe))
6126 & ~TU_SIZE_MASK;
6127 m_n->gmch_n = I915_READ(PIPE_DATA_N_G4X(pipe));
6128 m_n->tu = ((I915_READ(PIPE_DATA_M_G4X(pipe))
6129 & TU_SIZE_MASK) >> TU_SIZE_SHIFT) + 1;
6130 }
6131}
6132
6133void intel_dp_get_m_n(struct intel_crtc *crtc,
6134 struct intel_crtc_config *pipe_config)
6135{
6136 if (crtc->config.has_pch_encoder)
6137 intel_pch_transcoder_get_m_n(crtc, &pipe_config->dp_m_n);
6138 else
6139 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6140 &pipe_config->dp_m_n);
6141}
72419203 6142
eb14cb74
VS		 6143static void ironlake_get_fdi_m_n_config(struct intel_crtc *crtc,
6144 struct intel_crtc_config *pipe_config)
6145{
6146 intel_cpu_transcoder_get_m_n(crtc, pipe_config->cpu_transcoder,
6147 &pipe_config->fdi_m_n);
72419203
DV		 6148}
6149
2fa2fe9a
DV		 6150static void ironlake_get_pfit_config(struct intel_crtc *crtc,
6151 struct intel_crtc_config *pipe_config)
6152{
6153 struct drm_device *dev = crtc->base.dev;
6154 struct drm_i915_private *dev_priv = dev->dev_private;
6155 uint32_t tmp;
6156
6157 tmp = I915_READ(PF_CTL(crtc->pipe));
6158
6159 if (tmp & PF_ENABLE) {
fd4daa9c 6160 pipe_config->pch_pfit.enabled = true;
2fa2fe9a
DV		 6161 pipe_config->pch_pfit.pos = I915_READ(PF_WIN_POS(crtc->pipe));
6162 pipe_config->pch_pfit.size = I915_READ(PF_WIN_SZ(crtc->pipe));
cb8b2a30
DV		 6163
6164 /* We currently do not free assignements of panel fitters on
6165 * ivb/hsw (since we don't use the higher upscaling modes which
6166 * differentiates them) so just WARN about this case for now. */
6167 if (IS_GEN7(dev)) {
6168 WARN_ON((tmp & PF_PIPE_SEL_MASK_IVB) !=
6169 PF_PIPE_SEL_IVB(crtc->pipe));
6170 }
2fa2fe9a 6171 }
79e53945
JB		 6172}
6173
0e8ffe1b
DV		 6174static bool ironlake_get_pipe_config(struct intel_crtc *crtc,
6175 struct intel_crtc_config *pipe_config)
6176{
6177 struct drm_device *dev = crtc->base.dev;
6178 struct drm_i915_private *dev_priv = dev->dev_private;
6179 uint32_t tmp;
6180
e143a21c 6181 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62 6182 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
eccb140b 6183
0e8ffe1b
DV		 6184 tmp = I915_READ(PIPECONF(crtc->pipe));
6185 if (!(tmp & PIPECONF_ENABLE))
6186 return false;
6187
42571aef
VS		 6188 switch (tmp & PIPECONF_BPC_MASK) {
6189 case PIPECONF_6BPC:
6190 pipe_config->pipe_bpp = 18;
6191 break;
6192 case PIPECONF_8BPC:
6193 pipe_config->pipe_bpp = 24;
6194 break;
6195 case PIPECONF_10BPC:
6196 pipe_config->pipe_bpp = 30;
6197 break;
6198 case PIPECONF_12BPC:
6199 pipe_config->pipe_bpp = 36;
6200 break;
6201 default:
6202 break;
6203 }
6204
ab9412ba 6205 if (I915_READ(PCH_TRANSCONF(crtc->pipe)) & TRANS_ENABLE) {
66e985c0
DV		 6206 struct intel_shared_dpll *pll;
6207
88adfff1
DV		 6208 pipe_config->has_pch_encoder = true;
6209
627eb5a3
DV		 6210 tmp = I915_READ(FDI_RX_CTL(crtc->pipe));
6211 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6212 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6213
6214 ironlake_get_fdi_m_n_config(crtc, pipe_config);
6c49f241 6215
c0d43d62 6216 if (HAS_PCH_IBX(dev_priv->dev)) {
d94ab068
DV		 6217 pipe_config->shared_dpll =
6218 (enum intel_dpll_id) crtc->pipe;
c0d43d62
DV		 6219 } else {
6220 tmp = I915_READ(PCH_DPLL_SEL);
6221 if (tmp & TRANS_DPLLB_SEL(crtc->pipe))
6222 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_B;
6223 else
6224 pipe_config->shared_dpll = DPLL_ID_PCH_PLL_A;
6225 }
66e985c0
DV		 6226
6227 pll = &dev_priv->shared_dplls[pipe_config->shared_dpll];
6228
6229 WARN_ON(!pll->get_hw_state(dev_priv, pll,
6230 &pipe_config->dpll_hw_state));
c93f54cf
DV		 6231
6232 tmp = pipe_config->dpll_hw_state.dpll;
6233 pipe_config->pixel_multiplier =
6234 ((tmp & PLL_REF_SDVO_HDMI_MULTIPLIER_MASK)
6235 >> PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT) + 1;
18442d08
VS		 6236
6237 ironlake_pch_clock_get(crtc, pipe_config);
6c49f241
DV		 6238 } else {
6239 pipe_config->pixel_multiplier = 1;
627eb5a3
DV		 6240 }
6241
1bd1bd80
DV		 6242 intel_get_pipe_timings(crtc, pipe_config);
6243
2fa2fe9a
DV		 6244 ironlake_get_pfit_config(crtc, pipe_config);
6245
0e8ffe1b
DV		 6246 return true;
6247}
6248
be256dc7
PZ		 6249static void assert_can_disable_lcpll(struct drm_i915_private *dev_priv)
6250{
6251 struct drm_device *dev = dev_priv->dev;
6252 struct intel_ddi_plls *plls = &dev_priv->ddi_plls;
6253 struct intel_crtc *crtc;
6254 unsigned long irqflags;
bd633a7c 6255 uint32_t val;
be256dc7
PZ		 6256
6257 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6258 WARN(crtc->base.enabled, "CRTC for pipe %c enabled\n",
6259 pipe_name(crtc->pipe));
6260
6261 WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on\n");
6262 WARN(plls->spll_refcount, "SPLL enabled\n");
6263 WARN(plls->wrpll1_refcount, "WRPLL1 enabled\n");
6264 WARN(plls->wrpll2_refcount, "WRPLL2 enabled\n");
6265 WARN(I915_READ(PCH_PP_STATUS) & PP_ON, "Panel power on\n");
6266 WARN(I915_READ(BLC_PWM_CPU_CTL2) & BLM_PWM_ENABLE,
6267 "CPU PWM1 enabled\n");
6268 WARN(I915_READ(HSW_BLC_PWM2_CTL) & BLM_PWM_ENABLE,
6269 "CPU PWM2 enabled\n");
6270 WARN(I915_READ(BLC_PWM_PCH_CTL1) & BLM_PCH_PWM_ENABLE,
6271 "PCH PWM1 enabled\n");
6272 WARN(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
6273 "Utility pin enabled\n");
6274 WARN(I915_READ(PCH_GTC_CTL) & PCH_GTC_ENABLE, "PCH GTC enabled\n");
6275
6276 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
6277 val = I915_READ(DEIMR);
6278 WARN((val & ~DE_PCH_EVENT_IVB) != val,
6279 "Unexpected DEIMR bits enabled: 0x%x\n", val);
6280 val = I915_READ(SDEIMR);
bd633a7c 6281 WARN((val | SDE_HOTPLUG_MASK_CPT) != 0xffffffff,
be256dc7
PZ		 6282 "Unexpected SDEIMR bits enabled: 0x%x\n", val);
6283 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
6284}
6285
6286/*
6287 * This function implements pieces of two sequences from BSpec:
6288 * - Sequence for display software to disable LCPLL
6289 * - Sequence for display software to allow package C8+
6290 * The steps implemented here are just the steps that actually touch the LCPLL
6291 * register. Callers should take care of disabling all the display engine
6292 * functions, doing the mode unset, fixing interrupts, etc.
6293 */
6ff58d53
PZ		 6294static void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
6295 bool switch_to_fclk, bool allow_power_down)
be256dc7
PZ		 6296{
6297 uint32_t val;
6298
6299 assert_can_disable_lcpll(dev_priv);
6300
6301 val = I915_READ(LCPLL_CTL);
6302
6303 if (switch_to_fclk) {
6304 val |= LCPLL_CD_SOURCE_FCLK;
6305 I915_WRITE(LCPLL_CTL, val);
6306
6307 if (wait_for_atomic_us(I915_READ(LCPLL_CTL) &
6308 LCPLL_CD_SOURCE_FCLK_DONE, 1))
6309 DRM_ERROR("Switching to FCLK failed\n");
6310
6311 val = I915_READ(LCPLL_CTL);
6312 }
6313
6314 val |= LCPLL_PLL_DISABLE;
6315 I915_WRITE(LCPLL_CTL, val);
6316 POSTING_READ(LCPLL_CTL);
6317
6318 if (wait_for((I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK) == 0, 1))
6319 DRM_ERROR("LCPLL still locked\n");
6320
6321 val = I915_READ(D_COMP);
6322 val |= D_COMP_COMP_DISABLE;
515b2392
PZ		 6323 mutex_lock(&dev_priv->rps.hw_lock);
6324 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6325 DRM_ERROR("Failed to disable D_COMP\n");
6326 mutex_unlock(&dev_priv->rps.hw_lock);
be256dc7
PZ		 6327 POSTING_READ(D_COMP);
6328 ndelay(100);
6329
6330 if (wait_for((I915_READ(D_COMP) & D_COMP_RCOMP_IN_PROGRESS) == 0, 1))
6331 DRM_ERROR("D_COMP RCOMP still in progress\n");
6332
6333 if (allow_power_down) {
6334 val = I915_READ(LCPLL_CTL);
6335 val |= LCPLL_POWER_DOWN_ALLOW;
6336 I915_WRITE(LCPLL_CTL, val);
6337 POSTING_READ(LCPLL_CTL);
6338 }
6339}
6340
6341/*
6342 * Fully restores LCPLL, disallowing power down and switching back to LCPLL
6343 * source.
6344 */
6ff58d53 6345static void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
be256dc7
PZ		 6346{
6347 uint32_t val;
6348
6349 val = I915_READ(LCPLL_CTL);
6350
6351 if ((val & (LCPLL_PLL_LOCK | LCPLL_PLL_DISABLE | LCPLL_CD_SOURCE_FCLK |
6352 LCPLL_POWER_DOWN_ALLOW)) == LCPLL_PLL_LOCK)
6353 return;
6354
215733fa
PZ		 6355 /* Make sure we're not on PC8 state before disabling PC8, otherwise
6356 * we'll hang the machine! */
6357 dev_priv->uncore.funcs.force_wake_get(dev_priv);
6358
be256dc7
PZ		 6359 if (val & LCPLL_POWER_DOWN_ALLOW) {
6360 val &= ~LCPLL_POWER_DOWN_ALLOW;
6361 I915_WRITE(LCPLL_CTL, val);
35d8f2eb 6362 POSTING_READ(LCPLL_CTL);
be256dc7
PZ		 6363 }
6364
6365 val = I915_READ(D_COMP);
6366 val |= D_COMP_COMP_FORCE;
6367 val &= ~D_COMP_COMP_DISABLE;
515b2392
PZ		 6368 mutex_lock(&dev_priv->rps.hw_lock);
6369 if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
6370 DRM_ERROR("Failed to enable D_COMP\n");
6371 mutex_unlock(&dev_priv->rps.hw_lock);
35d8f2eb 6372 POSTING_READ(D_COMP);
be256dc7
PZ		 6373
6374 val = I915_READ(LCPLL_CTL);
6375 val &= ~LCPLL_PLL_DISABLE;
6376 I915_WRITE(LCPLL_CTL, val);
6377
6378 if (wait_for(I915_READ(LCPLL_CTL) & LCPLL_PLL_LOCK, 5))
6379 DRM_ERROR("LCPLL not locked yet\n");
6380
6381 if (val & LCPLL_CD_SOURCE_FCLK) {
6382 val = I915_READ(LCPLL_CTL);
6383 val &= ~LCPLL_CD_SOURCE_FCLK;
6384 I915_WRITE(LCPLL_CTL, val);
6385
6386 if (wait_for_atomic_us((I915_READ(LCPLL_CTL) &
6387 LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
6388 DRM_ERROR("Switching back to LCPLL failed\n");
6389 }
215733fa
PZ		 6390
6391 dev_priv->uncore.funcs.force_wake_put(dev_priv);
be256dc7
PZ		 6392}
6393
c67a470b
PZ		 6394void hsw_enable_pc8_work(struct work_struct *__work)
6395{
6396 struct drm_i915_private *dev_priv =
6397 container_of(to_delayed_work(__work), struct drm_i915_private,
6398 pc8.enable_work);
6399 struct drm_device *dev = dev_priv->dev;
6400 uint32_t val;
6401
6402 if (dev_priv->pc8.enabled)
6403 return;
6404
6405 DRM_DEBUG_KMS("Enabling package C8+\n");
6406
6407 dev_priv->pc8.enabled = true;
6408
6409 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6410 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6411 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6412 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6413 }
6414
6415 lpt_disable_clkout_dp(dev);
6416 hsw_pc8_disable_interrupts(dev);
6417 hsw_disable_lcpll(dev_priv, true, true);
6418}
6419
6420static void __hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6421{
6422 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6423 WARN(dev_priv->pc8.disable_count < 1,
6424 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6425
6426 dev_priv->pc8.disable_count--;
6427 if (dev_priv->pc8.disable_count != 0)
6428 return;
6429
6430 schedule_delayed_work(&dev_priv->pc8.enable_work,
90058745 6431 msecs_to_jiffies(i915_pc8_timeout));
c67a470b
PZ		 6432}
6433
6434static void __hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6435{
6436 struct drm_device *dev = dev_priv->dev;
6437 uint32_t val;
6438
6439 WARN_ON(!mutex_is_locked(&dev_priv->pc8.lock));
6440 WARN(dev_priv->pc8.disable_count < 0,
6441 "pc8.disable_count: %d\n", dev_priv->pc8.disable_count);
6442
6443 dev_priv->pc8.disable_count++;
6444 if (dev_priv->pc8.disable_count != 1)
6445 return;
6446
6447 cancel_delayed_work_sync(&dev_priv->pc8.enable_work);
6448 if (!dev_priv->pc8.enabled)
6449 return;
6450
6451 DRM_DEBUG_KMS("Disabling package C8+\n");
6452
6453 hsw_restore_lcpll(dev_priv);
6454 hsw_pc8_restore_interrupts(dev);
6455 lpt_init_pch_refclk(dev);
6456
6457 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6458 val = I915_READ(SOUTH_DSPCLK_GATE_D);
6459 val |= PCH_LP_PARTITION_LEVEL_DISABLE;
6460 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6461 }
6462
6463 intel_prepare_ddi(dev);
6464 i915_gem_init_swizzling(dev);
6465 mutex_lock(&dev_priv->rps.hw_lock);
6466 gen6_update_ring_freq(dev);
6467 mutex_unlock(&dev_priv->rps.hw_lock);
6468 dev_priv->pc8.enabled = false;
6469}
6470
6471void hsw_enable_package_c8(struct drm_i915_private *dev_priv)
6472{
6473 mutex_lock(&dev_priv->pc8.lock);
6474 __hsw_enable_package_c8(dev_priv);
6475 mutex_unlock(&dev_priv->pc8.lock);
6476}
6477
6478void hsw_disable_package_c8(struct drm_i915_private *dev_priv)
6479{
6480 mutex_lock(&dev_priv->pc8.lock);
6481 __hsw_disable_package_c8(dev_priv);
6482 mutex_unlock(&dev_priv->pc8.lock);
6483}
6484
6485static bool hsw_can_enable_package_c8(struct drm_i915_private *dev_priv)
6486{
6487 struct drm_device *dev = dev_priv->dev;
6488 struct intel_crtc *crtc;
6489 uint32_t val;
6490
6491 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head)
6492 if (crtc->base.enabled)
6493 return false;
6494
6495 /* This case is still possible since we have the i915.disable_power_well
6496 * parameter and also the KVMr or something else might be requesting the
6497 * power well. */
6498 val = I915_READ(HSW_PWR_WELL_DRIVER);
6499 if (val != 0) {
6500 DRM_DEBUG_KMS("Not enabling PC8: power well on\n");
6501 return false;
6502 }
6503
6504 return true;
6505}
6506
6507/* Since we're called from modeset_global_resources there's no way to
6508 * symmetrically increase and decrease the refcount, so we use
6509 * dev_priv->pc8.requirements_met to track whether we already have the refcount
6510 * or not.
6511 */
6512static void hsw_update_package_c8(struct drm_device *dev)
6513{
6514 struct drm_i915_private *dev_priv = dev->dev_private;
6515 bool allow;
6516
6517 if (!i915_enable_pc8)
6518 return;
6519
6520 mutex_lock(&dev_priv->pc8.lock);
6521
6522 allow = hsw_can_enable_package_c8(dev_priv);
6523
6524 if (allow == dev_priv->pc8.requirements_met)
6525 goto done;
6526
6527 dev_priv->pc8.requirements_met = allow;
6528
6529 if (allow)
6530 __hsw_enable_package_c8(dev_priv);
6531 else
6532 __hsw_disable_package_c8(dev_priv);
6533
6534done:
6535 mutex_unlock(&dev_priv->pc8.lock);
6536}
6537
6538static void hsw_package_c8_gpu_idle(struct drm_i915_private *dev_priv)
6539{
6540 if (!dev_priv->pc8.gpu_idle) {
6541 dev_priv->pc8.gpu_idle = true;
6542 hsw_enable_package_c8(dev_priv);
6543 }
6544}
6545
6546static void hsw_package_c8_gpu_busy(struct drm_i915_private *dev_priv)
6547{
6548 if (dev_priv->pc8.gpu_idle) {
6549 dev_priv->pc8.gpu_idle = false;
6550 hsw_disable_package_c8(dev_priv);
6551 }
be256dc7
PZ		 6552}
6553
d6dd9eb1
DV		 6554static void haswell_modeset_global_resources(struct drm_device *dev)
6555{
d6dd9eb1
DV		 6556 bool enable = false;
6557 struct intel_crtc *crtc;
d6dd9eb1
DV		 6558
6559 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
e7a639c4
DV		 6560 if (!crtc->base.enabled)
6561 continue;
d6dd9eb1 6562
fd4daa9c 6563 if (crtc->pipe != PIPE_A || crtc->config.pch_pfit.enabled ||
e7a639c4 6564 crtc->config.cpu_transcoder != TRANSCODER_EDP)
d6dd9eb1
DV		 6565 enable = true;
6566 }
6567
d6dd9eb1 6568 intel_set_power_well(dev, enable);
c67a470b
PZ		 6569
6570 hsw_update_package_c8(dev);
d6dd9eb1
DV		 6571}
6572
09b4ddf9 6573static int haswell_crtc_mode_set(struct drm_crtc *crtc,
09b4ddf9
PZ		 6574 int x, int y,
6575 struct drm_framebuffer *fb)
6576{
6577 struct drm_device *dev = crtc->dev;
6578 struct drm_i915_private *dev_priv = dev->dev_private;
6579 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
09b4ddf9 6580 int plane = intel_crtc->plane;
09b4ddf9 6581 int ret;
09b4ddf9 6582
ff9a6750 6583 if (!intel_ddi_pll_mode_set(crtc))
6441ab5f
PZ		 6584 return -EINVAL;
6585
03afc4a2
DV		 6586 if (intel_crtc->config.has_dp_encoder)
6587 intel_dp_set_m_n(intel_crtc);
09b4ddf9
PZ		 6588
6589 intel_crtc->lowfreq_avail = false;
09b4ddf9 6590
8a654f3b 6591 intel_set_pipe_timings(intel_crtc);
09b4ddf9 6592
ca3a0ff8 6593 if (intel_crtc->config.has_pch_encoder) {
ca3a0ff8
DV		 6594 intel_cpu_transcoder_set_m_n(intel_crtc,
6595 &intel_crtc->config.fdi_m_n);
6596 }
09b4ddf9 6597
6ff93609 6598 haswell_set_pipeconf(crtc);
09b4ddf9 6599
50f3b016 6600 intel_set_pipe_csc(crtc);
86d3efce 6601
09b4ddf9 6602 /* Set up the display plane register */
86d3efce 6603 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE | DISPPLANE_PIPE_CSC_ENABLE);
09b4ddf9
PZ		 6604 POSTING_READ(DSPCNTR(plane));
6605
6606 ret = intel_pipe_set_base(crtc, x, y, fb);
6607
1f803ee5 6608 return ret;
79e53945
JB		 6609}
6610
0e8ffe1b
DV		 6611static bool haswell_get_pipe_config(struct intel_crtc *crtc,
6612 struct intel_crtc_config *pipe_config)
6613{
6614 struct drm_device *dev = crtc->base.dev;
6615 struct drm_i915_private *dev_priv = dev->dev_private;
2fa2fe9a 6616 enum intel_display_power_domain pfit_domain;
0e8ffe1b
DV		 6617 uint32_t tmp;
6618
e143a21c 6619 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
c0d43d62
DV		 6620 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
6621
eccb140b
DV		 6622 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
6623 if (tmp & TRANS_DDI_FUNC_ENABLE) {
6624 enum pipe trans_edp_pipe;
6625 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
6626 default:
6627 WARN(1, "unknown pipe linked to edp transcoder\n");
6628 case TRANS_DDI_EDP_INPUT_A_ONOFF:
6629 case TRANS_DDI_EDP_INPUT_A_ON:
6630 trans_edp_pipe = PIPE_A;
6631 break;
6632 case TRANS_DDI_EDP_INPUT_B_ONOFF:
6633 trans_edp_pipe = PIPE_B;
6634 break;
6635 case TRANS_DDI_EDP_INPUT_C_ONOFF:
6636 trans_edp_pipe = PIPE_C;
6637 break;
6638 }
6639
6640 if (trans_edp_pipe == crtc->pipe)
6641 pipe_config->cpu_transcoder = TRANSCODER_EDP;
6642 }
6643
b97186f0 6644 if (!intel_display_power_enabled(dev,
eccb140b 6645 POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
2bfce950
PZ		 6646 return false;
6647
eccb140b 6648 tmp = I915_READ(PIPECONF(pipe_config->cpu_transcoder));
0e8ffe1b
DV		 6649 if (!(tmp & PIPECONF_ENABLE))
6650 return false;
6651
88adfff1 6652 /*
f196e6be 6653 * Haswell has only FDI/PCH transcoder A. It is which is connected to
88adfff1
DV		 6654 * DDI E. So just check whether this pipe is wired to DDI E and whether
6655 * the PCH transcoder is on.
6656 */
eccb140b 6657 tmp = I915_READ(TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
88adfff1 6658 if ((tmp & TRANS_DDI_PORT_MASK) == TRANS_DDI_SELECT_PORT(PORT_E) &&
ab9412ba 6659 I915_READ(LPT_TRANSCONF) & TRANS_ENABLE) {
88adfff1
DV		 6660 pipe_config->has_pch_encoder = true;
6661
627eb5a3
DV		 6662 tmp = I915_READ(FDI_RX_CTL(PIPE_A));
6663 pipe_config->fdi_lanes = ((FDI_DP_PORT_WIDTH_MASK & tmp) >>
6664 FDI_DP_PORT_WIDTH_SHIFT) + 1;
72419203
DV		 6665
6666 ironlake_get_fdi_m_n_config(crtc, pipe_config);
627eb5a3
DV		 6667 }
6668
1bd1bd80
DV		 6669 intel_get_pipe_timings(crtc, pipe_config);
6670
2fa2fe9a
DV		 6671 pfit_domain = POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe);
6672 if (intel_display_power_enabled(dev, pfit_domain))
6673 ironlake_get_pfit_config(crtc, pipe_config);
88adfff1 6674
42db64ef
PZ		 6675 pipe_config->ips_enabled = hsw_crtc_supports_ips(crtc) &&
6676 (I915_READ(IPS_CTL) & IPS_ENABLE);
6677
6c49f241
DV		 6678 pipe_config->pixel_multiplier = 1;
6679
0e8ffe1b
DV		 6680 return true;
6681}
6682
f564048e 6683static int intel_crtc_mode_set(struct drm_crtc *crtc,
f564048e 6684 int x, int y,
94352cf9 6685 struct drm_framebuffer *fb)
f564048e
EA		 6686{
6687 struct drm_device *dev = crtc->dev;
6688 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19 6689 struct intel_encoder *encoder;
0b701d27 6690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b8cecdf5 6691 struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
0b701d27 6692 int pipe = intel_crtc->pipe;
f564048e
EA		 6693 int ret;
6694
0b701d27 6695 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 6696
b8cecdf5
DV		 6697 ret = dev_priv->display.crtc_mode_set(crtc, x, y, fb);
6698
79e53945 6699 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 6700
9256aa19
DV		 6701 if (ret != 0)
6702 return ret;
6703
6704 for_each_encoder_on_crtc(dev, crtc, encoder) {
6705 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6706 encoder->base.base.id,
6707 drm_get_encoder_name(&encoder->base),
6708 mode->base.id, mode->name);
36f2d1f1 6709 encoder->mode_set(encoder);
9256aa19
DV		 6710 }
6711
6712 return 0;
79e53945
JB		 6713}
6714
3a9627f4
WF		 6715static bool intel_eld_uptodate(struct drm_connector *connector,
6716 int reg_eldv, uint32_t bits_eldv,
6717 int reg_elda, uint32_t bits_elda,
6718 int reg_edid)
6719{
6720 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6721 uint8_t *eld = connector->eld;
6722 uint32_t i;
6723
6724 i = I915_READ(reg_eldv);
6725 i &= bits_eldv;
6726
6727 if (!eld[0])
6728 return !i;
6729
6730 if (!i)
6731 return false;
6732
6733 i = I915_READ(reg_elda);
6734 i &= ~bits_elda;
6735 I915_WRITE(reg_elda, i);
6736
6737 for (i = 0; i < eld[2]; i++)
6738 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6739 return false;
6740
6741 return true;
6742}
6743
e0dac65e
WF		 6744static void g4x_write_eld(struct drm_connector *connector,
6745 struct drm_crtc *crtc)
6746{
6747 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6748 uint8_t *eld = connector->eld;
6749 uint32_t eldv;
6750 uint32_t len;
6751 uint32_t i;
6752
6753 i = I915_READ(G4X_AUD_VID_DID);
6754
6755 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6756 eldv = G4X_ELDV_DEVCL_DEVBLC;
6757 else
6758 eldv = G4X_ELDV_DEVCTG;
6759
3a9627f4
WF		 6760 if (intel_eld_uptodate(connector,
6761 G4X_AUD_CNTL_ST, eldv,
6762 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6763 G4X_HDMIW_HDMIEDID))
6764 return;
6765
e0dac65e
WF		 6766 i = I915_READ(G4X_AUD_CNTL_ST);
6767 i &= ~(eldv | G4X_ELD_ADDR);
6768 len = (i >> 9) & 0x1f; /* ELD buffer size */
6769 I915_WRITE(G4X_AUD_CNTL_ST, i);
6770
6771 if (!eld[0])
6772 return;
6773
6774 len = min_t(uint8_t, eld[2], len);
6775 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6776 for (i = 0; i < len; i++)
6777 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6778
6779 i = I915_READ(G4X_AUD_CNTL_ST);
6780 i |= eldv;
6781 I915_WRITE(G4X_AUD_CNTL_ST, i);
6782}
6783
83358c85
WX		 6784static void haswell_write_eld(struct drm_connector *connector,
6785 struct drm_crtc *crtc)
6786{
6787 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6788 uint8_t *eld = connector->eld;
6789 struct drm_device *dev = crtc->dev;
7b9f35a6 6790 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 6791 uint32_t eldv;
6792 uint32_t i;
6793 int len;
6794 int pipe = to_intel_crtc(crtc)->pipe;
6795 int tmp;
6796
6797 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
6798 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
6799 int aud_config = HSW_AUD_CFG(pipe);
6800 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
6801
6802
6803 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
6804
6805 /* Audio output enable */
6806 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
6807 tmp = I915_READ(aud_cntrl_st2);
6808 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
6809 I915_WRITE(aud_cntrl_st2, tmp);
6810
6811 /* Wait for 1 vertical blank */
6812 intel_wait_for_vblank(dev, pipe);
6813
6814 /* Set ELD valid state */
6815 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6816 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%08x\n", tmp);
83358c85
WX		 6817 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
6818 I915_WRITE(aud_cntrl_st2, tmp);
6819 tmp = I915_READ(aud_cntrl_st2);
7e7cb34f 6820 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%08x\n", tmp);
83358c85
WX		 6821
6822 /* Enable HDMI mode */
6823 tmp = I915_READ(aud_config);
7e7cb34f 6824 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%08x\n", tmp);
83358c85
WX		 6825 /* clear N_programing_enable and N_value_index */
6826 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
6827 I915_WRITE(aud_config, tmp);
6828
6829 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
6830
6831 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 6832 intel_crtc->eld_vld = true;
83358c85
WX		 6833
6834 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6835 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6836 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
6837 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6838 } else
6839 I915_WRITE(aud_config, 0);
6840
6841 if (intel_eld_uptodate(connector,
6842 aud_cntrl_st2, eldv,
6843 aud_cntl_st, IBX_ELD_ADDRESS,
6844 hdmiw_hdmiedid))
6845 return;
6846
6847 i = I915_READ(aud_cntrl_st2);
6848 i &= ~eldv;
6849 I915_WRITE(aud_cntrl_st2, i);
6850
6851 if (!eld[0])
6852 return;
6853
6854 i = I915_READ(aud_cntl_st);
6855 i &= ~IBX_ELD_ADDRESS;
6856 I915_WRITE(aud_cntl_st, i);
6857 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
6858 DRM_DEBUG_DRIVER("port num:%d\n", i);
6859
6860 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6861 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6862 for (i = 0; i < len; i++)
6863 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6864
6865 i = I915_READ(aud_cntrl_st2);
6866 i |= eldv;
6867 I915_WRITE(aud_cntrl_st2, i);
6868
6869}
6870
e0dac65e
WF		 6871static void ironlake_write_eld(struct drm_connector *connector,
6872 struct drm_crtc *crtc)
6873{
6874 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6875 uint8_t *eld = connector->eld;
6876 uint32_t eldv;
6877 uint32_t i;
6878 int len;
6879 int hdmiw_hdmiedid;
b6daa025 6880 int aud_config;
e0dac65e
WF		 6881 int aud_cntl_st;
6882 int aud_cntrl_st2;
9b138a83 6883 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 6884
b3f33cbf 6885 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 6886 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
6887 aud_config = IBX_AUD_CFG(pipe);
6888 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 6889 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6890 } else {
9b138a83
WX		 6891 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
6892 aud_config = CPT_AUD_CFG(pipe);
6893 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 6894 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6895 }
6896
9b138a83 6897 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 6898
6899 i = I915_READ(aud_cntl_st);
9b138a83 6900 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 6901 if (!i) {
6902 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6903 /* operate blindly on all ports */
1202b4c6
WF		 6904 eldv = IBX_ELD_VALIDB;
6905 eldv |= IBX_ELD_VALIDB << 4;
6906 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e 6907 } else {
2582a850 6908 DRM_DEBUG_DRIVER("ELD on port %c\n", port_name(i));
1202b4c6 6909 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6910 }
6911
3a9627f4
WF		 6912 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6913 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6914 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 6915 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
6916 } else
6917 I915_WRITE(aud_config, 0);
e0dac65e 6918
3a9627f4
WF		 6919 if (intel_eld_uptodate(connector,
6920 aud_cntrl_st2, eldv,
6921 aud_cntl_st, IBX_ELD_ADDRESS,
6922 hdmiw_hdmiedid))
6923 return;
6924
e0dac65e
WF		 6925 i = I915_READ(aud_cntrl_st2);
6926 i &= ~eldv;
6927 I915_WRITE(aud_cntrl_st2, i);
6928
6929 if (!eld[0])
6930 return;
6931
e0dac65e 6932 i = I915_READ(aud_cntl_st);
1202b4c6 6933 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6934 I915_WRITE(aud_cntl_st, i);
6935
6936 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6937 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6938 for (i = 0; i < len; i++)
6939 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6940
6941 i = I915_READ(aud_cntrl_st2);
6942 i |= eldv;
6943 I915_WRITE(aud_cntrl_st2, i);
6944}
6945
6946void intel_write_eld(struct drm_encoder *encoder,
6947 struct drm_display_mode *mode)
6948{
6949 struct drm_crtc *crtc = encoder->crtc;
6950 struct drm_connector *connector;
6951 struct drm_device *dev = encoder->dev;
6952 struct drm_i915_private *dev_priv = dev->dev_private;
6953
6954 connector = drm_select_eld(encoder, mode);
6955 if (!connector)
6956 return;
6957
6958 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6959 connector->base.id,
6960 drm_get_connector_name(connector),
6961 connector->encoder->base.id,
6962 drm_get_encoder_name(connector->encoder));
6963
6964 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6965
6966 if (dev_priv->display.write_eld)
6967 dev_priv->display.write_eld(connector, crtc);
6968}
6969
560b85bb
CW		 6970static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6971{
6972 struct drm_device *dev = crtc->dev;
6973 struct drm_i915_private *dev_priv = dev->dev_private;
6974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6975 bool visible = base != 0;
6976 u32 cntl;
6977
6978 if (intel_crtc->cursor_visible == visible)
6979 return;
6980
9db4a9c7 6981 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6982 if (visible) {
6983 /* On these chipsets we can only modify the base whilst
6984 * the cursor is disabled.
6985 */
9db4a9c7 6986 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6987
6988 cntl &= ~(CURSOR_FORMAT_MASK);
6989 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6990 cntl |= CURSOR_ENABLE |
6991 CURSOR_GAMMA_ENABLE |
6992 CURSOR_FORMAT_ARGB;
6993 } else
6994 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6995 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6996
6997 intel_crtc->cursor_visible = visible;
6998}
6999
7000static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
7001{
7002 struct drm_device *dev = crtc->dev;
7003 struct drm_i915_private *dev_priv = dev->dev_private;
7004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7005 int pipe = intel_crtc->pipe;
7006 bool visible = base != 0;
7007
7008 if (intel_crtc->cursor_visible != visible) {
548f245b 7009 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 7010 if (base) {
7011 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
7012 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7013 cntl |= pipe << 28; /* Connect to correct pipe */
7014 } else {
7015 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7016 cntl |= CURSOR_MODE_DISABLE;
7017 }
9db4a9c7 7018 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 7019
7020 intel_crtc->cursor_visible = visible;
7021 }
7022 /* and commit changes on next vblank */
9db4a9c7 7023 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 7024}
7025
65a21cd6
JB		 7026static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
7027{
7028 struct drm_device *dev = crtc->dev;
7029 struct drm_i915_private *dev_priv = dev->dev_private;
7030 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7031 int pipe = intel_crtc->pipe;
7032 bool visible = base != 0;
7033
7034 if (intel_crtc->cursor_visible != visible) {
7035 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
7036 if (base) {
7037 cntl &= ~CURSOR_MODE;
7038 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
7039 } else {
7040 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
7041 cntl |= CURSOR_MODE_DISABLE;
7042 }
1f5d76db 7043 if (IS_HASWELL(dev)) {
86d3efce 7044 cntl |= CURSOR_PIPE_CSC_ENABLE;
1f5d76db
PZ		 7045 cntl &= ~CURSOR_TRICKLE_FEED_DISABLE;
7046 }
65a21cd6
JB		 7047 I915_WRITE(CURCNTR_IVB(pipe), cntl);
7048
7049 intel_crtc->cursor_visible = visible;
7050 }
7051 /* and commit changes on next vblank */
7052 I915_WRITE(CURBASE_IVB(pipe), base);
7053}
7054
cda4b7d3 7055/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 7056static void intel_crtc_update_cursor(struct drm_crtc *crtc,
7057 bool on)
cda4b7d3
CW		 7058{
7059 struct drm_device *dev = crtc->dev;
7060 struct drm_i915_private *dev_priv = dev->dev_private;
7061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7062 int pipe = intel_crtc->pipe;
7063 int x = intel_crtc->cursor_x;
7064 int y = intel_crtc->cursor_y;
d6e4db15 7065 u32 base = 0, pos = 0;
cda4b7d3
CW		 7066 bool visible;
7067
d6e4db15 7068 if (on)
cda4b7d3 7069 base = intel_crtc->cursor_addr;
cda4b7d3 7070
d6e4db15
VS		 7071 if (x >= intel_crtc->config.pipe_src_w)
7072 base = 0;
7073
7074 if (y >= intel_crtc->config.pipe_src_h)
cda4b7d3
CW		 7075 base = 0;
7076
7077 if (x < 0) {
efc9064e 7078 if (x + intel_crtc->cursor_width <= 0)
cda4b7d3
CW		 7079 base = 0;
7080
7081 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
7082 x = -x;
7083 }
7084 pos |= x << CURSOR_X_SHIFT;
7085
7086 if (y < 0) {
efc9064e 7087 if (y + intel_crtc->cursor_height <= 0)
cda4b7d3
CW		 7088 base = 0;
7089
7090 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
7091 y = -y;
7092 }
7093 pos |= y << CURSOR_Y_SHIFT;
7094
7095 visible = base != 0;
560b85bb 7096 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 7097 return;
7098
0cd83aa9 7099 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 7100 I915_WRITE(CURPOS_IVB(pipe), pos);
7101 ivb_update_cursor(crtc, base);
7102 } else {
7103 I915_WRITE(CURPOS(pipe), pos);
7104 if (IS_845G(dev) || IS_I865G(dev))
7105 i845_update_cursor(crtc, base);
7106 else
7107 i9xx_update_cursor(crtc, base);
7108 }
cda4b7d3
CW		 7109}
7110
79e53945 7111static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 7112 struct drm_file *file,
79e53945
JB		 7113 uint32_t handle,
7114 uint32_t width, uint32_t height)
7115{
7116 struct drm_device *dev = crtc->dev;
7117 struct drm_i915_private *dev_priv = dev->dev_private;
7118 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 7119 struct drm_i915_gem_object *obj;
cda4b7d3 7120 uint32_t addr;
3f8bc370 7121 int ret;
79e53945 7122
79e53945
JB		 7123 /* if we want to turn off the cursor ignore width and height */
7124 if (!handle) {
28c97730 7125 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 7126 addr = 0;
05394f39 7127 obj = NULL;
5004417d 7128 mutex_lock(&dev->struct_mutex);
3f8bc370 7129 goto finish;
79e53945
JB		 7130 }
7131
7132 /* Currently we only support 64x64 cursors */
7133 if (width != 64 || height != 64) {
7134 DRM_ERROR("we currently only support 64x64 cursors\n");
7135 return -EINVAL;
7136 }
7137
05394f39 7138 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 7139 if (&obj->base == NULL)
79e53945
JB		 7140 return -ENOENT;
7141
05394f39 7142 if (obj->base.size < width * height * 4) {
79e53945 7143 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 7144 ret = -ENOMEM;
7145 goto fail;
79e53945
JB		 7146 }
7147
71acb5eb 7148 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 7149 mutex_lock(&dev->struct_mutex);
b295d1b6 7150 if (!dev_priv->info->cursor_needs_physical) {
693db184
CW		 7151 unsigned alignment;
7152
d9e86c0e
CW		 7153 if (obj->tiling_mode) {
7154 DRM_ERROR("cursor cannot be tiled\n");
7155 ret = -EINVAL;
7156 goto fail_locked;
7157 }
7158
693db184
CW		 7159 /* Note that the w/a also requires 2 PTE of padding following
7160 * the bo. We currently fill all unused PTE with the shadow
7161 * page and so we should always have valid PTE following the
7162 * cursor preventing the VT-d warning.
7163 */
7164 alignment = 0;
7165 if (need_vtd_wa(dev))
7166 alignment = 64*1024;
7167
7168 ret = i915_gem_object_pin_to_display_plane(obj, alignment, NULL);
e7b526bb
CW		 7169 if (ret) {
7170 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 7171 goto fail_locked;
e7b526bb
CW		 7172 }
7173
d9e86c0e
CW		 7174 ret = i915_gem_object_put_fence(obj);
7175 if (ret) {
2da3b9b9 7176 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 7177 goto fail_unpin;
7178 }
7179
f343c5f6 7180 addr = i915_gem_obj_ggtt_offset(obj);
71acb5eb 7181 } else {
6eeefaf3 7182 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 7183 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 7184 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
7185 align);
71acb5eb
DA		 7186 if (ret) {
7187 DRM_ERROR("failed to attach phys object\n");
7f9872e0 7188 goto fail_locked;
71acb5eb 7189 }
05394f39 7190 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 7191 }
7192
a6c45cf0 7193 if (IS_GEN2(dev))
14b60391
JB		 7194 I915_WRITE(CURSIZE, (height << 12) | width);
7195
3f8bc370 7196 finish:
3f8bc370 7197 if (intel_crtc->cursor_bo) {
b295d1b6 7198 if (dev_priv->info->cursor_needs_physical) {
05394f39 7199 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 7200 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
7201 } else
cc98b413 7202 i915_gem_object_unpin_from_display_plane(intel_crtc->cursor_bo);
05394f39 7203 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 7204 }
80824003 7205
7f9872e0 7206 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 7207
7208 intel_crtc->cursor_addr = addr;
05394f39 7209 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 7210 intel_crtc->cursor_width = width;
7211 intel_crtc->cursor_height = height;
7212
f2f5f771
VS		 7213 if (intel_crtc->active)
7214 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
3f8bc370 7215
79e53945 7216 return 0;
e7b526bb 7217fail_unpin:
cc98b413 7218 i915_gem_object_unpin_from_display_plane(obj);
7f9872e0 7219fail_locked:
34b8686e 7220 mutex_unlock(&dev->struct_mutex);
bc9025bd 7221fail:
05394f39 7222 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 7223 return ret;
79e53945
JB		 7224}
7225
7226static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
7227{
79e53945 7228 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7229
cda4b7d3
CW		 7230 intel_crtc->cursor_x = x;
7231 intel_crtc->cursor_y = y;
652c393a 7232
f2f5f771
VS		 7233 if (intel_crtc->active)
7234 intel_crtc_update_cursor(crtc, intel_crtc->cursor_bo != NULL);
79e53945
JB		 7235
7236 return 0;
b8c00ac5
DA		 7237}
7238
79e53945 7239static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 7240 u16 *blue, uint32_t start, uint32_t size)
79e53945 7241{
7203425a 7242 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 7243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 7244
7203425a 7245 for (i = start; i < end; i++) {
79e53945
JB		 7246 intel_crtc->lut_r[i] = red[i] >> 8;
7247 intel_crtc->lut_g[i] = green[i] >> 8;
7248 intel_crtc->lut_b[i] = blue[i] >> 8;
7249 }
7250
7251 intel_crtc_load_lut(crtc);
7252}
7253
79e53945
JB		 7254/* VESA 640x480x72Hz mode to set on the pipe */
7255static struct drm_display_mode load_detect_mode = {
7256 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
7257 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
7258};
7259
d2dff872
CW		 7260static struct drm_framebuffer *
7261intel_framebuffer_create(struct drm_device *dev,
308e5bcb 7262 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 7263 struct drm_i915_gem_object *obj)
7264{
7265 struct intel_framebuffer *intel_fb;
7266 int ret;
7267
7268 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
7269 if (!intel_fb) {
7270 drm_gem_object_unreference_unlocked(&obj->base);
7271 return ERR_PTR(-ENOMEM);
7272 }
7273
7274 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
7275 if (ret) {
7276 drm_gem_object_unreference_unlocked(&obj->base);
7277 kfree(intel_fb);
7278 return ERR_PTR(ret);
7279 }
7280
7281 return &intel_fb->base;
7282}
7283
7284static u32
7285intel_framebuffer_pitch_for_width(int width, int bpp)
7286{
7287 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
7288 return ALIGN(pitch, 64);
7289}
7290
7291static u32
7292intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
7293{
7294 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
7295 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
7296}
7297
7298static struct drm_framebuffer *
7299intel_framebuffer_create_for_mode(struct drm_device *dev,
7300 struct drm_display_mode *mode,
7301 int depth, int bpp)
7302{
7303 struct drm_i915_gem_object *obj;
0fed39bd 7304 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 7305
7306 obj = i915_gem_alloc_object(dev,
7307 intel_framebuffer_size_for_mode(mode, bpp));
7308 if (obj == NULL)
7309 return ERR_PTR(-ENOMEM);
7310
7311 mode_cmd.width = mode->hdisplay;
7312 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 7313 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
7314 bpp);
5ca0c34a 7315 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 7316
7317 return intel_framebuffer_create(dev, &mode_cmd, obj);
7318}
7319
7320static struct drm_framebuffer *
7321mode_fits_in_fbdev(struct drm_device *dev,
7322 struct drm_display_mode *mode)
7323{
7324 struct drm_i915_private *dev_priv = dev->dev_private;
7325 struct drm_i915_gem_object *obj;
7326 struct drm_framebuffer *fb;
7327
7328 if (dev_priv->fbdev == NULL)
7329 return NULL;
7330
7331 obj = dev_priv->fbdev->ifb.obj;
7332 if (obj == NULL)
7333 return NULL;
7334
7335 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 7336 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
7337 fb->bits_per_pixel))
d2dff872
CW		 7338 return NULL;
7339
01f2c773 7340 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 7341 return NULL;
7342
7343 return fb;
7344}
7345
d2434ab7 7346bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 7347 struct drm_display_mode *mode,
8261b191 7348 struct intel_load_detect_pipe *old)
79e53945
JB		 7349{
7350 struct intel_crtc *intel_crtc;
d2434ab7
DV		 7351 struct intel_encoder *intel_encoder =
7352 intel_attached_encoder(connector);
79e53945 7353 struct drm_crtc *possible_crtc;
4ef69c7a 7354 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 7355 struct drm_crtc *crtc = NULL;
7356 struct drm_device *dev = encoder->dev;
94352cf9 7357 struct drm_framebuffer *fb;
79e53945
JB		 7358 int i = -1;
7359
d2dff872
CW		 7360 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7361 connector->base.id, drm_get_connector_name(connector),
7362 encoder->base.id, drm_get_encoder_name(encoder));
7363
79e53945
JB		 7364 /*
7365 * Algorithm gets a little messy:
7a5e4805 7366 *
79e53945
JB		 7367 * - if the connector already has an assigned crtc, use it (but make
7368 * sure it's on first)
7a5e4805 7369 *
79e53945
JB		 7370 * - try to find the first unused crtc that can drive this connector,
7371 * and use that if we find one
79e53945
JB		 7372 */
7373
7374 /* See if we already have a CRTC for this connector */
7375 if (encoder->crtc) {
7376 crtc = encoder->crtc;
8261b191 7377
7b24056b
DV		 7378 mutex_lock(&crtc->mutex);
7379
24218aac 7380 old->dpms_mode = connector->dpms;
8261b191
CW		 7381 old->load_detect_temp = false;
7382
7383 /* Make sure the crtc and connector are running */
24218aac
DV		 7384 if (connector->dpms != DRM_MODE_DPMS_ON)
7385 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 7386
7173188d 7387 return true;
79e53945
JB		 7388 }
7389
7390 /* Find an unused one (if possible) */
7391 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
7392 i++;
7393 if (!(encoder->possible_crtcs & (1 << i)))
7394 continue;
7395 if (!possible_crtc->enabled) {
7396 crtc = possible_crtc;
7397 break;
7398 }
79e53945
JB		 7399 }
7400
7401 /*
7402 * If we didn't find an unused CRTC, don't use any.
7403 */
7404 if (!crtc) {
7173188d
CW		 7405 DRM_DEBUG_KMS("no pipe available for load-detect\n");
7406 return false;
79e53945
JB		 7407 }
7408
7b24056b 7409 mutex_lock(&crtc->mutex);
fc303101
DV		 7410 intel_encoder->new_crtc = to_intel_crtc(crtc);
7411 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 7412
7413 intel_crtc = to_intel_crtc(crtc);
24218aac 7414 old->dpms_mode = connector->dpms;
8261b191 7415 old->load_detect_temp = true;
d2dff872 7416 old->release_fb = NULL;
79e53945 7417
6492711d
CW		 7418 if (!mode)
7419 mode = &load_detect_mode;
79e53945 7420
d2dff872
CW		 7421 /* We need a framebuffer large enough to accommodate all accesses
7422 * that the plane may generate whilst we perform load detection.
7423 * We can not rely on the fbcon either being present (we get called
7424 * during its initialisation to detect all boot displays, or it may
7425 * not even exist) or that it is large enough to satisfy the
7426 * requested mode.
7427 */
94352cf9
DV		 7428 fb = mode_fits_in_fbdev(dev, mode);
7429 if (fb == NULL) {
d2dff872 7430 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 7431 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
7432 old->release_fb = fb;
d2dff872
CW		 7433 } else
7434 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 7435 if (IS_ERR(fb)) {
d2dff872 7436 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
7b24056b 7437 mutex_unlock(&crtc->mutex);
0e8b3d3e 7438 return false;
79e53945 7439 }
79e53945 7440
c0c36b94 7441 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 7442 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 7443 if (old->release_fb)
7444 old->release_fb->funcs->destroy(old->release_fb);
7b24056b 7445 mutex_unlock(&crtc->mutex);
0e8b3d3e 7446 return false;
79e53945 7447 }
7173188d 7448
79e53945 7449 /* let the connector get through one full cycle before testing */
9d0498a2 7450 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 7451 return true;
79e53945
JB		 7452}
7453
d2434ab7 7454void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 7455 struct intel_load_detect_pipe *old)
79e53945 7456{
d2434ab7
DV		 7457 struct intel_encoder *intel_encoder =
7458 intel_attached_encoder(connector);
4ef69c7a 7459 struct drm_encoder *encoder = &intel_encoder->base;
7b24056b 7460 struct drm_crtc *crtc = encoder->crtc;
79e53945 7461
d2dff872
CW		 7462 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
7463 connector->base.id, drm_get_connector_name(connector),
7464 encoder->base.id, drm_get_encoder_name(encoder));
7465
8261b191 7466 if (old->load_detect_temp) {
fc303101
DV		 7467 to_intel_connector(connector)->new_encoder = NULL;
7468 intel_encoder->new_crtc = NULL;
7469 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872 7470
36206361
DV		 7471 if (old->release_fb) {
7472 drm_framebuffer_unregister_private(old->release_fb);
7473 drm_framebuffer_unreference(old->release_fb);
7474 }
d2dff872 7475
67c96400 7476 mutex_unlock(&crtc->mutex);
0622a53c 7477 return;
79e53945
JB		 7478 }
7479
c751ce4f 7480 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 7481 if (old->dpms_mode != DRM_MODE_DPMS_ON)
7482 connector->funcs->dpms(connector, old->dpms_mode);
7b24056b
DV		 7483
7484 mutex_unlock(&crtc->mutex);
79e53945
JB		 7485}
7486
da4a1efa
VS		 7487static int i9xx_pll_refclk(struct drm_device *dev,
7488 const struct intel_crtc_config *pipe_config)
7489{
7490 struct drm_i915_private *dev_priv = dev->dev_private;
7491 u32 dpll = pipe_config->dpll_hw_state.dpll;
7492
7493 if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
7494 return dev_priv->vbt.lvds_ssc_freq * 1000;
7495 else if (HAS_PCH_SPLIT(dev))
7496 return 120000;
7497 else if (!IS_GEN2(dev))
7498 return 96000;
7499 else
7500 return 48000;
7501}
7502
79e53945 7503/* Returns the clock of the currently programmed mode of the given pipe. */
f1f644dc
JB		 7504static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
7505 struct intel_crtc_config *pipe_config)
79e53945 7506{
f1f644dc 7507 struct drm_device *dev = crtc->base.dev;
79e53945 7508 struct drm_i915_private *dev_priv = dev->dev_private;
f1f644dc 7509 int pipe = pipe_config->cpu_transcoder;
293623f7 7510 u32 dpll = pipe_config->dpll_hw_state.dpll;
79e53945
JB		 7511 u32 fp;
7512 intel_clock_t clock;
da4a1efa 7513 int refclk = i9xx_pll_refclk(dev, pipe_config);
79e53945
JB		 7514
7515 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
293623f7 7516 fp = pipe_config->dpll_hw_state.fp0;
79e53945 7517 else
293623f7 7518 fp = pipe_config->dpll_hw_state.fp1;
79e53945
JB		 7519
7520 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 7521 if (IS_PINEVIEW(dev)) {
7522 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
7523 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 7524 } else {
7525 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
7526 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
7527 }
7528
a6c45cf0 7529 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 7530 if (IS_PINEVIEW(dev))
7531 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
7532 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 7533 else
7534 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 7535 DPLL_FPA01_P1_POST_DIV_SHIFT);
7536
7537 switch (dpll & DPLL_MODE_MASK) {
7538 case DPLLB_MODE_DAC_SERIAL:
7539 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
7540 5 : 10;
7541 break;
7542 case DPLLB_MODE_LVDS:
7543 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
7544 7 : 14;
7545 break;
7546 default:
28c97730 7547 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945 7548 "mode\n", (int)(dpll & DPLL_MODE_MASK));
f1f644dc 7549 return;
79e53945
JB		 7550 }
7551
ac58c3f0 7552 if (IS_PINEVIEW(dev))
da4a1efa 7553 pineview_clock(refclk, &clock);
ac58c3f0 7554 else
da4a1efa 7555 i9xx_clock(refclk, &clock);
79e53945
JB		 7556 } else {
7557 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
7558
7559 if (is_lvds) {
7560 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
7561 DPLL_FPA01_P1_POST_DIV_SHIFT);
7562 clock.p2 = 14;
79e53945
JB		 7563 } else {
7564 if (dpll & PLL_P1_DIVIDE_BY_TWO)
7565 clock.p1 = 2;
7566 else {
7567 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
7568 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
7569 }
7570 if (dpll & PLL_P2_DIVIDE_BY_4)
7571 clock.p2 = 4;
7572 else
7573 clock.p2 = 2;
79e53945 7574 }
da4a1efa
VS		 7575
7576 i9xx_clock(refclk, &clock);
79e53945
JB		 7577 }
7578
18442d08
VS		 7579 /*
7580 * This value includes pixel_multiplier. We will use
241bfc38 7581 * port_clock to compute adjusted_mode.crtc_clock in the
18442d08
VS		 7582 * encoder's get_config() function.
7583 */
7584 pipe_config->port_clock = clock.dot;
f1f644dc
JB		 7585}
7586
6878da05
VS		 7587int intel_dotclock_calculate(int link_freq,
7588 const struct intel_link_m_n *m_n)
f1f644dc 7589{
f1f644dc
JB		 7590 /*
7591 * The calculation for the data clock is:
1041a02f 7592 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
f1f644dc 7593 * But we want to avoid losing precison if possible, so:
1041a02f 7594 * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
f1f644dc
JB		 7595 *
7596 * and the link clock is simpler:
1041a02f 7597 * link_clock = (m * link_clock) / n
f1f644dc
JB		 7598 */
7599
6878da05
VS		 7600 if (!m_n->link_n)
7601 return 0;
f1f644dc 7602
6878da05
VS		 7603 return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
7604}
f1f644dc 7605
18442d08
VS		 7606static void ironlake_pch_clock_get(struct intel_crtc *crtc,
7607 struct intel_crtc_config *pipe_config)
6878da05
VS		 7608{
7609 struct drm_device *dev = crtc->base.dev;
79e53945 7610
18442d08
VS		 7611 /* read out port_clock from the DPLL */
7612 i9xx_crtc_clock_get(crtc, pipe_config);
f1f644dc 7613
f1f644dc 7614 /*
18442d08 7615 * This value does not include pixel_multiplier.
241bfc38 7616 * We will check that port_clock and adjusted_mode.crtc_clock
18442d08
VS		 7617 * agree once we know their relationship in the encoder's
7618 * get_config() function.
79e53945 7619 */
241bfc38 7620 pipe_config->adjusted_mode.crtc_clock =
18442d08
VS		 7621 intel_dotclock_calculate(intel_fdi_link_freq(dev) * 10000,
7622 &pipe_config->fdi_m_n);
79e53945
JB		 7623}
7624
7625/** Returns the currently programmed mode of the given pipe. */
7626struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
7627 struct drm_crtc *crtc)
7628{
548f245b 7629 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 7630 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3b117c8f 7631 enum transcoder cpu_transcoder = intel_crtc->config.cpu_transcoder;
79e53945 7632 struct drm_display_mode *mode;
f1f644dc 7633 struct intel_crtc_config pipe_config;
fe2b8f9d
PZ		 7634 int htot = I915_READ(HTOTAL(cpu_transcoder));
7635 int hsync = I915_READ(HSYNC(cpu_transcoder));
7636 int vtot = I915_READ(VTOTAL(cpu_transcoder));
7637 int vsync = I915_READ(VSYNC(cpu_transcoder));
293623f7 7638 enum pipe pipe = intel_crtc->pipe;
79e53945
JB		 7639
7640 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
7641 if (!mode)
7642 return NULL;
7643
f1f644dc
JB		 7644 /*
7645 * Construct a pipe_config sufficient for getting the clock info
7646 * back out of crtc_clock_get.
7647 *
7648 * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
7649 * to use a real value here instead.
7650 */
293623f7 7651 pipe_config.cpu_transcoder = (enum transcoder) pipe;
f1f644dc 7652 pipe_config.pixel_multiplier = 1;
293623f7
VS		 7653 pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
7654 pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
7655 pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
f1f644dc
JB		 7656 i9xx_crtc_clock_get(intel_crtc, &pipe_config);
7657
773ae034 7658 mode->clock = pipe_config.port_clock / pipe_config.pixel_multiplier;
79e53945
JB		 7659 mode->hdisplay = (htot & 0xffff) + 1;
7660 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
7661 mode->hsync_start = (hsync & 0xffff) + 1;
7662 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
7663 mode->vdisplay = (vtot & 0xffff) + 1;
7664 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
7665 mode->vsync_start = (vsync & 0xffff) + 1;
7666 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
7667
7668 drm_mode_set_name(mode);
79e53945
JB		 7669
7670 return mode;
7671}
7672
3dec0095 7673static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 7674{
7675 struct drm_device *dev = crtc->dev;
7676 drm_i915_private_t *dev_priv = dev->dev_private;
7677 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7678 int pipe = intel_crtc->pipe;
dbdc6479
JB		 7679 int dpll_reg = DPLL(pipe);
7680 int dpll;
652c393a 7681
bad720ff 7682 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7683 return;
7684
7685 if (!dev_priv->lvds_downclock_avail)
7686 return;
7687
dbdc6479 7688 dpll = I915_READ(dpll_reg);
652c393a 7689 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 7690 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 7691
8ac5a6d5 7692 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 7693
7694 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
7695 I915_WRITE(dpll_reg, dpll);
9d0498a2 7696 intel_wait_for_vblank(dev, pipe);
dbdc6479 7697
652c393a
JB		 7698 dpll = I915_READ(dpll_reg);
7699 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 7700 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 7701 }
652c393a
JB		 7702}
7703
7704static void intel_decrease_pllclock(struct drm_crtc *crtc)
7705{
7706 struct drm_device *dev = crtc->dev;
7707 drm_i915_private_t *dev_priv = dev->dev_private;
7708 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 7709
bad720ff 7710 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 7711 return;
7712
7713 if (!dev_priv->lvds_downclock_avail)
7714 return;
7715
7716 /*
7717 * Since this is called by a timer, we should never get here in
7718 * the manual case.
7719 */
7720 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 7721 int pipe = intel_crtc->pipe;
7722 int dpll_reg = DPLL(pipe);
7723 int dpll;
f6e5b160 7724
44d98a61 7725 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 7726
8ac5a6d5 7727 assert_panel_unlocked(dev_priv, pipe);
652c393a 7728
dc257cf1 7729 dpll = I915_READ(dpll_reg);
652c393a
JB		 7730 dpll |= DISPLAY_RATE_SELECT_FPA1;
7731 I915_WRITE(dpll_reg, dpll);
9d0498a2 7732 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 7733 dpll = I915_READ(dpll_reg);
7734 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 7735 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 7736 }
7737
7738}
7739
f047e395
CW		 7740void intel_mark_busy(struct drm_device *dev)
7741{
c67a470b
PZ		 7742 struct drm_i915_private *dev_priv = dev->dev_private;
7743
7744 hsw_package_c8_gpu_busy(dev_priv);
7745 i915_update_gfx_val(dev_priv);
f047e395
CW		 7746}
7747
7748void intel_mark_idle(struct drm_device *dev)
652c393a 7749{
c67a470b 7750 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 7751 struct drm_crtc *crtc;
652c393a 7752
c67a470b
PZ		 7753 hsw_package_c8_gpu_idle(dev_priv);
7754
652c393a
JB		 7755 if (!i915_powersave)
7756 return;
7757
652c393a 7758 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 7759 if (!crtc->fb)
7760 continue;
7761
725a5b54 7762 intel_decrease_pllclock(crtc);
652c393a 7763 }
b29c19b6
CW		 7764
7765 if (dev_priv->info->gen >= 6)
7766 gen6_rps_idle(dev->dev_private);
652c393a
JB		 7767}
7768
c65355bb
CW		 7769void intel_mark_fb_busy(struct drm_i915_gem_object *obj,
7770 struct intel_ring_buffer *ring)
652c393a 7771{
f047e395
CW		 7772 struct drm_device *dev = obj->base.dev;
7773 struct drm_crtc *crtc;
652c393a 7774
f047e395 7775 if (!i915_powersave)
acb87dfb
CW		 7776 return;
7777
652c393a
JB		 7778 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7779 if (!crtc->fb)
7780 continue;
7781
c65355bb
CW		 7782 if (to_intel_framebuffer(crtc->fb)->obj != obj)
7783 continue;
7784
7785 intel_increase_pllclock(crtc);
7786 if (ring && intel_fbc_enabled(dev))
7787 ring->fbc_dirty = true;
652c393a
JB		 7788 }
7789}
7790
79e53945
JB		 7791static void intel_crtc_destroy(struct drm_crtc *crtc)
7792{
7793 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7794 struct drm_device *dev = crtc->dev;
7795 struct intel_unpin_work *work;
7796 unsigned long flags;
7797
7798 spin_lock_irqsave(&dev->event_lock, flags);
7799 work = intel_crtc->unpin_work;
7800 intel_crtc->unpin_work = NULL;
7801 spin_unlock_irqrestore(&dev->event_lock, flags);
7802
7803 if (work) {
7804 cancel_work_sync(&work->work);
7805 kfree(work);
7806 }
79e53945 7807
40ccc72b
MK		 7808 intel_crtc_cursor_set(crtc, NULL, 0, 0, 0);
7809
79e53945 7810 drm_crtc_cleanup(crtc);
67e77c5a 7811
79e53945
JB		 7812 kfree(intel_crtc);
7813}
7814
6b95a207
KH		 7815static void intel_unpin_work_fn(struct work_struct *__work)
7816{
7817 struct intel_unpin_work *work =
7818 container_of(__work, struct intel_unpin_work, work);
b4a98e57 7819 struct drm_device *dev = work->crtc->dev;
6b95a207 7820
b4a98e57 7821 mutex_lock(&dev->struct_mutex);
1690e1eb 7822 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 7823 drm_gem_object_unreference(&work->pending_flip_obj->base);
7824 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7825
b4a98e57
CW		 7826 intel_update_fbc(dev);
7827 mutex_unlock(&dev->struct_mutex);
7828
7829 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
7830 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
7831
6b95a207
KH		 7832 kfree(work);
7833}
7834
1afe3e9d 7835static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7836 struct drm_crtc *crtc)
6b95a207
KH		 7837{
7838 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7840 struct intel_unpin_work *work;
6b95a207
KH		 7841 unsigned long flags;
7842
7843 /* Ignore early vblank irqs */
7844 if (intel_crtc == NULL)
7845 return;
7846
7847 spin_lock_irqsave(&dev->event_lock, flags);
7848 work = intel_crtc->unpin_work;
e7d841ca
CW		 7849
7850 /* Ensure we don't miss a work->pending update ... */
7851 smp_rmb();
7852
7853 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 7854 spin_unlock_irqrestore(&dev->event_lock, flags);
7855 return;
7856 }
7857
e7d841ca
CW		 7858 /* and that the unpin work is consistent wrt ->pending. */
7859 smp_rmb();
7860
6b95a207 7861 intel_crtc->unpin_work = NULL;
6b95a207 7862
45a066eb
RC		 7863 if (work->event)
7864 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 7865
0af7e4df
MK		 7866 drm_vblank_put(dev, intel_crtc->pipe);
7867
6b95a207
KH		 7868 spin_unlock_irqrestore(&dev->event_lock, flags);
7869
2c10d571 7870 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 7871
7872 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 7873
7874 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7875}
7876
1afe3e9d
JB		 7877void intel_finish_page_flip(struct drm_device *dev, int pipe)
7878{
7879 drm_i915_private_t *dev_priv = dev->dev_private;
7880 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7881
49b14a5c 7882 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7883}
7884
7885void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7886{
7887 drm_i915_private_t *dev_priv = dev->dev_private;
7888 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7889
49b14a5c 7890 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7891}
7892
6b95a207
KH		 7893void intel_prepare_page_flip(struct drm_device *dev, int plane)
7894{
7895 drm_i915_private_t *dev_priv = dev->dev_private;
7896 struct intel_crtc *intel_crtc =
7897 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7898 unsigned long flags;
7899
e7d841ca
CW		 7900 /* NB: An MMIO update of the plane base pointer will also
7901 * generate a page-flip completion irq, i.e. every modeset
7902 * is also accompanied by a spurious intel_prepare_page_flip().
7903 */
6b95a207 7904 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 7905 if (intel_crtc->unpin_work)
7906 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 7907 spin_unlock_irqrestore(&dev->event_lock, flags);
7908}
7909
e7d841ca
CW		 7910inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
7911{
7912 /* Ensure that the work item is consistent when activating it ... */
7913 smp_wmb();
7914 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
7915 /* and that it is marked active as soon as the irq could fire. */
7916 smp_wmb();
7917}
7918
8c9f3aaf
JB		 7919static int intel_gen2_queue_flip(struct drm_device *dev,
7920 struct drm_crtc *crtc,
7921 struct drm_framebuffer *fb,
ed8d1975
KP		 7922 struct drm_i915_gem_object *obj,
7923 uint32_t flags)
8c9f3aaf
JB		 7924{
7925 struct drm_i915_private *dev_priv = dev->dev_private;
7926 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7927 u32 flip_mask;
6d90c952 7928 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7929 int ret;
7930
6d90c952 7931 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7932 if (ret)
83d4092b 7933 goto err;
8c9f3aaf 7934
6d90c952 7935 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7936 if (ret)
83d4092b 7937 goto err_unpin;
8c9f3aaf
JB		 7938
7939 /* Can't queue multiple flips, so wait for the previous
7940 * one to finish before executing the next.
7941 */
7942 if (intel_crtc->plane)
7943 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7944 else
7945 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7946 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7947 intel_ring_emit(ring, MI_NOOP);
7948 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7949 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7950 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7951 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952 7952 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 7953
7954 intel_mark_page_flip_active(intel_crtc);
09246732 7955 __intel_ring_advance(ring);
83d4092b
CW		 7956 return 0;
7957
7958err_unpin:
7959 intel_unpin_fb_obj(obj);
7960err:
8c9f3aaf
JB		 7961 return ret;
7962}
7963
7964static int intel_gen3_queue_flip(struct drm_device *dev,
7965 struct drm_crtc *crtc,
7966 struct drm_framebuffer *fb,
ed8d1975
KP		 7967 struct drm_i915_gem_object *obj,
7968 uint32_t flags)
8c9f3aaf
JB		 7969{
7970 struct drm_i915_private *dev_priv = dev->dev_private;
7971 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 7972 u32 flip_mask;
6d90c952 7973 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7974 int ret;
7975
6d90c952 7976 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7977 if (ret)
83d4092b 7978 goto err;
8c9f3aaf 7979
6d90c952 7980 ret = intel_ring_begin(ring, 6);
8c9f3aaf 7981 if (ret)
83d4092b 7982 goto err_unpin;
8c9f3aaf
JB		 7983
7984 if (intel_crtc->plane)
7985 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7986 else
7987 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 7988 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
7989 intel_ring_emit(ring, MI_NOOP);
7990 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
7991 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7992 intel_ring_emit(ring, fb->pitches[0]);
f343c5f6 7993 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
6d90c952
DV		 7994 intel_ring_emit(ring, MI_NOOP);
7995
e7d841ca 7996 intel_mark_page_flip_active(intel_crtc);
09246732 7997 __intel_ring_advance(ring);
83d4092b
CW		 7998 return 0;
7999
8000err_unpin:
8001 intel_unpin_fb_obj(obj);
8002err:
8c9f3aaf
JB		 8003 return ret;
8004}
8005
8006static int intel_gen4_queue_flip(struct drm_device *dev,
8007 struct drm_crtc *crtc,
8008 struct drm_framebuffer *fb,
ed8d1975
KP		 8009 struct drm_i915_gem_object *obj,
8010 uint32_t flags)
8c9f3aaf
JB		 8011{
8012 struct drm_i915_private *dev_priv = dev->dev_private;
8013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8014 uint32_t pf, pipesrc;
6d90c952 8015 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8016 int ret;
8017
6d90c952 8018 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8019 if (ret)
83d4092b 8020 goto err;
8c9f3aaf 8021
6d90c952 8022 ret = intel_ring_begin(ring, 4);
8c9f3aaf 8023 if (ret)
83d4092b 8024 goto err_unpin;
8c9f3aaf
JB		 8025
8026 /* i965+ uses the linear or tiled offsets from the
8027 * Display Registers (which do not change across a page-flip)
8028 * so we need only reprogram the base address.
8029 */
6d90c952
DV		 8030 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8031 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8032 intel_ring_emit(ring, fb->pitches[0]);
c2c75131 8033 intel_ring_emit(ring,
f343c5f6 8034 (i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset) |
c2c75131 8035 obj->tiling_mode);
8c9f3aaf
JB		 8036
8037 /* XXX Enabling the panel-fitter across page-flip is so far
8038 * untested on non-native modes, so ignore it for now.
8039 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
8040 */
8041 pf = 0;
8042 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 8043 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 8044
8045 intel_mark_page_flip_active(intel_crtc);
09246732 8046 __intel_ring_advance(ring);
83d4092b
CW		 8047 return 0;
8048
8049err_unpin:
8050 intel_unpin_fb_obj(obj);
8051err:
8c9f3aaf
JB		 8052 return ret;
8053}
8054
8055static int intel_gen6_queue_flip(struct drm_device *dev,
8056 struct drm_crtc *crtc,
8057 struct drm_framebuffer *fb,
ed8d1975
KP		 8058 struct drm_i915_gem_object *obj,
8059 uint32_t flags)
8c9f3aaf
JB		 8060{
8061 struct drm_i915_private *dev_priv = dev->dev_private;
8062 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 8063 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 8064 uint32_t pf, pipesrc;
8065 int ret;
8066
6d90c952 8067 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 8068 if (ret)
83d4092b 8069 goto err;
8c9f3aaf 8070
6d90c952 8071 ret = intel_ring_begin(ring, 4);
8c9f3aaf 8072 if (ret)
83d4092b 8073 goto err_unpin;
8c9f3aaf 8074
6d90c952
DV		 8075 intel_ring_emit(ring, MI_DISPLAY_FLIP |
8076 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
8077 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
f343c5f6 8078 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
8c9f3aaf 8079
dc257cf1
DV		 8080 /* Contrary to the suggestions in the documentation,
8081 * "Enable Panel Fitter" does not seem to be required when page
8082 * flipping with a non-native mode, and worse causes a normal
8083 * modeset to fail.
8084 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
8085 */
8086 pf = 0;
8c9f3aaf 8087 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 8088 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 8089
8090 intel_mark_page_flip_active(intel_crtc);
09246732 8091 __intel_ring_advance(ring);
83d4092b
CW		 8092 return 0;
8093
8094err_unpin:
8095 intel_unpin_fb_obj(obj);
8096err:
8c9f3aaf
JB		 8097 return ret;
8098}
8099
7c9017e5
JB		 8100static int intel_gen7_queue_flip(struct drm_device *dev,
8101 struct drm_crtc *crtc,
8102 struct drm_framebuffer *fb,
ed8d1975
KP		 8103 struct drm_i915_gem_object *obj,
8104 uint32_t flags)
7c9017e5
JB		 8105{
8106 struct drm_i915_private *dev_priv = dev->dev_private;
8107 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ffe74d75 8108 struct intel_ring_buffer *ring;
cb05d8de 8109 uint32_t plane_bit = 0;
ffe74d75
CW		 8110 int len, ret;
8111
8112 ring = obj->ring;
1c5fd085 8113 if (IS_VALLEYVIEW(dev) || ring == NULL || ring->id != RCS)
ffe74d75 8114 ring = &dev_priv->ring[BCS];
7c9017e5
JB		 8115
8116 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8117 if (ret)
83d4092b 8118 goto err;
7c9017e5 8119
cb05d8de
DV		 8120 switch(intel_crtc->plane) {
8121 case PLANE_A:
8122 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
8123 break;
8124 case PLANE_B:
8125 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
8126 break;
8127 case PLANE_C:
8128 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
8129 break;
8130 default:
8131 WARN_ONCE(1, "unknown plane in flip command\n");
8132 ret = -ENODEV;
ab3951eb 8133 goto err_unpin;
cb05d8de
DV		 8134 }
8135
ffe74d75
CW		 8136 len = 4;
8137 if (ring->id == RCS)
8138 len += 6;
8139
8140 ret = intel_ring_begin(ring, len);
7c9017e5 8141 if (ret)
83d4092b 8142 goto err_unpin;
7c9017e5 8143
ffe74d75
CW		 8144 /* Unmask the flip-done completion message. Note that the bspec says that
8145 * we should do this for both the BCS and RCS, and that we must not unmask
8146 * more than one flip event at any time (or ensure that one flip message
8147 * can be sent by waiting for flip-done prior to queueing new flips).
8148 * Experimentation says that BCS works despite DERRMR masking all
8149 * flip-done completion events and that unmasking all planes at once
8150 * for the RCS also doesn't appear to drop events. Setting the DERRMR
8151 * to zero does lead to lockups within MI_DISPLAY_FLIP.
8152 */
8153 if (ring->id == RCS) {
8154 intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
8155 intel_ring_emit(ring, DERRMR);
8156 intel_ring_emit(ring, ~(DERRMR_PIPEA_PRI_FLIP_DONE |
8157 DERRMR_PIPEB_PRI_FLIP_DONE |
8158 DERRMR_PIPEC_PRI_FLIP_DONE));
8159 intel_ring_emit(ring, MI_STORE_REGISTER_MEM(1));
8160 intel_ring_emit(ring, DERRMR);
8161 intel_ring_emit(ring, ring->scratch.gtt_offset + 256);
8162 }
8163
cb05d8de 8164 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 8165 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
f343c5f6 8166 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(obj) + intel_crtc->dspaddr_offset);
7c9017e5 8167 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 8168
8169 intel_mark_page_flip_active(intel_crtc);
09246732 8170 __intel_ring_advance(ring);
83d4092b
CW		 8171 return 0;
8172
8173err_unpin:
8174 intel_unpin_fb_obj(obj);
8175err:
7c9017e5
JB		 8176 return ret;
8177}
8178
8c9f3aaf
JB		 8179static int intel_default_queue_flip(struct drm_device *dev,
8180 struct drm_crtc *crtc,
8181 struct drm_framebuffer *fb,
ed8d1975
KP		 8182 struct drm_i915_gem_object *obj,
8183 uint32_t flags)
8c9f3aaf
JB		 8184{
8185 return -ENODEV;
8186}
8187
6b95a207
KH		 8188static int intel_crtc_page_flip(struct drm_crtc *crtc,
8189 struct drm_framebuffer *fb,
ed8d1975
KP		 8190 struct drm_pending_vblank_event *event,
8191 uint32_t page_flip_flags)
6b95a207
KH		 8192{
8193 struct drm_device *dev = crtc->dev;
8194 struct drm_i915_private *dev_priv = dev->dev_private;
4a35f83b
VS		 8195 struct drm_framebuffer *old_fb = crtc->fb;
8196 struct drm_i915_gem_object *obj = to_intel_framebuffer(fb)->obj;
6b95a207
KH		 8197 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8198 struct intel_unpin_work *work;
8c9f3aaf 8199 unsigned long flags;
52e68630 8200 int ret;
6b95a207 8201
e6a595d2
VS		 8202 /* Can't change pixel format via MI display flips. */
8203 if (fb->pixel_format != crtc->fb->pixel_format)
8204 return -EINVAL;
8205
8206 /*
8207 * TILEOFF/LINOFF registers can't be changed via MI display flips.
8208 * Note that pitch changes could also affect these register.
8209 */
8210 if (INTEL_INFO(dev)->gen > 3 &&
8211 (fb->offsets[0] != crtc->fb->offsets[0] ||
8212 fb->pitches[0] != crtc->fb->pitches[0]))
8213 return -EINVAL;
8214
b14c5679 8215 work = kzalloc(sizeof(*work), GFP_KERNEL);
6b95a207
KH		 8216 if (work == NULL)
8217 return -ENOMEM;
8218
6b95a207 8219 work->event = event;
b4a98e57 8220 work->crtc = crtc;
4a35f83b 8221 work->old_fb_obj = to_intel_framebuffer(old_fb)->obj;
6b95a207
KH		 8222 INIT_WORK(&work->work, intel_unpin_work_fn);
8223
7317c75e
JB		 8224 ret = drm_vblank_get(dev, intel_crtc->pipe);
8225 if (ret)
8226 goto free_work;
8227
6b95a207
KH		 8228 /* We borrow the event spin lock for protecting unpin_work */
8229 spin_lock_irqsave(&dev->event_lock, flags);
8230 if (intel_crtc->unpin_work) {
8231 spin_unlock_irqrestore(&dev->event_lock, flags);
8232 kfree(work);
7317c75e 8233 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 8234
8235 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 8236 return -EBUSY;
8237 }
8238 intel_crtc->unpin_work = work;
8239 spin_unlock_irqrestore(&dev->event_lock, flags);
8240
b4a98e57
CW		 8241 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
8242 flush_workqueue(dev_priv->wq);
8243
79158103
CW		 8244 ret = i915_mutex_lock_interruptible(dev);
8245 if (ret)
8246 goto cleanup;
6b95a207 8247
75dfca80 8248 /* Reference the objects for the scheduled work. */
05394f39
CW		 8249 drm_gem_object_reference(&work->old_fb_obj->base);
8250 drm_gem_object_reference(&obj->base);
6b95a207
KH		 8251
8252 crtc->fb = fb;
96b099fd 8253
e1f99ce6 8254 work->pending_flip_obj = obj;
e1f99ce6 8255
4e5359cd
SF		 8256 work->enable_stall_check = true;
8257
b4a98e57 8258 atomic_inc(&intel_crtc->unpin_work_count);
10d83730 8259 intel_crtc->reset_counter = atomic_read(&dev_priv->gpu_error.reset_counter);
e1f99ce6 8260
ed8d1975 8261 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj, page_flip_flags);
8c9f3aaf
JB		 8262 if (ret)
8263 goto cleanup_pending;
6b95a207 8264
7782de3b 8265 intel_disable_fbc(dev);
c65355bb 8266 intel_mark_fb_busy(obj, NULL);
6b95a207
KH		 8267 mutex_unlock(&dev->struct_mutex);
8268
e5510fac
JB		 8269 trace_i915_flip_request(intel_crtc->plane, obj);
8270
6b95a207 8271 return 0;
96b099fd 8272
8c9f3aaf 8273cleanup_pending:
b4a98e57 8274 atomic_dec(&intel_crtc->unpin_work_count);
4a35f83b 8275 crtc->fb = old_fb;
05394f39
CW		 8276 drm_gem_object_unreference(&work->old_fb_obj->base);
8277 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 8278 mutex_unlock(&dev->struct_mutex);
8279
79158103 8280cleanup:
96b099fd
CW		 8281 spin_lock_irqsave(&dev->event_lock, flags);
8282 intel_crtc->unpin_work = NULL;
8283 spin_unlock_irqrestore(&dev->event_lock, flags);
8284
7317c75e
JB		 8285 drm_vblank_put(dev, intel_crtc->pipe);
8286free_work:
96b099fd
CW		 8287 kfree(work);
8288
8289 return ret;
6b95a207
KH		 8290}
8291
f6e5b160 8292static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 8293 .mode_set_base_atomic = intel_pipe_set_base_atomic,
8294 .load_lut = intel_crtc_load_lut,
f6e5b160
CW		 8295};
8296
50f56119
DV		 8297static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
8298 struct drm_crtc *crtc)
8299{
8300 struct drm_device *dev;
8301 struct drm_crtc *tmp;
8302 int crtc_mask = 1;
47f1c6c9 8303
50f56119 8304 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 8305
50f56119 8306 dev = crtc->dev;
47f1c6c9 8307
50f56119
DV		 8308 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
8309 if (tmp == crtc)
8310 break;
8311 crtc_mask <<= 1;
8312 }
47f1c6c9 8313
50f56119
DV		 8314 if (encoder->possible_crtcs & crtc_mask)
8315 return true;
8316 return false;
47f1c6c9 8317}
79e53945 8318
9a935856
DV		 8319/**
8320 * intel_modeset_update_staged_output_state
8321 *
8322 * Updates the staged output configuration state, e.g. after we've read out the
8323 * current hw state.
8324 */
8325static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 8326{
9a935856
DV		 8327 struct intel_encoder *encoder;
8328 struct intel_connector *connector;
f6e5b160 8329
9a935856
DV		 8330 list_for_each_entry(connector, &dev->mode_config.connector_list,
8331 base.head) {
8332 connector->new_encoder =
8333 to_intel_encoder(connector->base.encoder);
8334 }
f6e5b160 8335
9a935856
DV		 8336 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8337 base.head) {
8338 encoder->new_crtc =
8339 to_intel_crtc(encoder->base.crtc);
8340 }
f6e5b160
CW		 8341}
8342
9a935856
DV		 8343/**
8344 * intel_modeset_commit_output_state
8345 *
8346 * This function copies the stage display pipe configuration to the real one.
8347 */
8348static void intel_modeset_commit_output_state(struct drm_device *dev)
8349{
8350 struct intel_encoder *encoder;
8351 struct intel_connector *connector;
f6e5b160 8352
9a935856
DV		 8353 list_for_each_entry(connector, &dev->mode_config.connector_list,
8354 base.head) {
8355 connector->base.encoder = &connector->new_encoder->base;
8356 }
f6e5b160 8357
9a935856
DV		 8358 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8359 base.head) {
8360 encoder->base.crtc = &encoder->new_crtc->base;
8361 }
8362}
8363
050f7aeb
DV		 8364static void
8365connected_sink_compute_bpp(struct intel_connector * connector,
8366 struct intel_crtc_config *pipe_config)
8367{
8368 int bpp = pipe_config->pipe_bpp;
8369
8370 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] checking for sink bpp constrains\n",
8371 connector->base.base.id,
8372 drm_get_connector_name(&connector->base));
8373
8374 /* Don't use an invalid EDID bpc value */
8375 if (connector->base.display_info.bpc &&
8376 connector->base.display_info.bpc * 3 < bpp) {
8377 DRM_DEBUG_KMS("clamping display bpp (was %d) to EDID reported max of %d\n",
8378 bpp, connector->base.display_info.bpc*3);
8379 pipe_config->pipe_bpp = connector->base.display_info.bpc*3;
8380 }
8381
8382 /* Clamp bpp to 8 on screens without EDID 1.4 */
8383 if (connector->base.display_info.bpc == 0 && bpp > 24) {
8384 DRM_DEBUG_KMS("clamping display bpp (was %d) to default limit of 24\n",
8385 bpp);
8386 pipe_config->pipe_bpp = 24;
8387 }
8388}
8389
4e53c2e0 8390static int
050f7aeb
DV		 8391compute_baseline_pipe_bpp(struct intel_crtc *crtc,
8392 struct drm_framebuffer *fb,
8393 struct intel_crtc_config *pipe_config)
4e53c2e0 8394{
050f7aeb
DV		 8395 struct drm_device *dev = crtc->base.dev;
8396 struct intel_connector *connector;
4e53c2e0
DV		 8397 int bpp;
8398
d42264b1
DV		 8399 switch (fb->pixel_format) {
8400 case DRM_FORMAT_C8:
4e53c2e0
DV		 8401 bpp = 8*3; /* since we go through a colormap */
8402 break;
d42264b1
DV		 8403 case DRM_FORMAT_XRGB1555:
8404 case DRM_FORMAT_ARGB1555:
8405 /* checked in intel_framebuffer_init already */
8406 if (WARN_ON(INTEL_INFO(dev)->gen > 3))
8407 return -EINVAL;
8408 case DRM_FORMAT_RGB565:
4e53c2e0
DV		 8409 bpp = 6*3; /* min is 18bpp */
8410 break;
d42264b1
DV		 8411 case DRM_FORMAT_XBGR8888:
8412 case DRM_FORMAT_ABGR8888:
8413 /* checked in intel_framebuffer_init already */
8414 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
8415 return -EINVAL;
8416 case DRM_FORMAT_XRGB8888:
8417 case DRM_FORMAT_ARGB8888:
4e53c2e0
DV		 8418 bpp = 8*3;
8419 break;
d42264b1
DV		 8420 case DRM_FORMAT_XRGB2101010:
8421 case DRM_FORMAT_ARGB2101010:
8422 case DRM_FORMAT_XBGR2101010:
8423 case DRM_FORMAT_ABGR2101010:
8424 /* checked in intel_framebuffer_init already */
8425 if (WARN_ON(INTEL_INFO(dev)->gen < 4))
baba133a 8426 return -EINVAL;
4e53c2e0
DV		 8427 bpp = 10*3;
8428 break;
baba133a 8429 /* TODO: gen4+ supports 16 bpc floating point, too. */
4e53c2e0
DV		 8430 default:
8431 DRM_DEBUG_KMS("unsupported depth\n");
8432 return -EINVAL;
8433 }
8434
4e53c2e0
DV		 8435 pipe_config->pipe_bpp = bpp;
8436
8437 /* Clamp display bpp to EDID value */
8438 list_for_each_entry(connector, &dev->mode_config.connector_list,
050f7aeb 8439 base.head) {
1b829e05
DV		 8440 if (!connector->new_encoder ||
8441 connector->new_encoder->new_crtc != crtc)
4e53c2e0
DV		 8442 continue;
8443
050f7aeb 8444 connected_sink_compute_bpp(connector, pipe_config);
4e53c2e0
DV		 8445 }
8446
8447 return bpp;
8448}
8449
644db711
DV		 8450static void intel_dump_crtc_timings(const struct drm_display_mode *mode)
8451{
8452 DRM_DEBUG_KMS("crtc timings: %d %d %d %d %d %d %d %d %d, "
8453 "type: 0x%x flags: 0x%x\n",
1342830c 8454 mode->crtc_clock,
644db711
DV		 8455 mode->crtc_hdisplay, mode->crtc_hsync_start,
8456 mode->crtc_hsync_end, mode->crtc_htotal,
8457 mode->crtc_vdisplay, mode->crtc_vsync_start,
8458 mode->crtc_vsync_end, mode->crtc_vtotal, mode->type, mode->flags);
8459}
8460
c0b03411
DV		 8461static void intel_dump_pipe_config(struct intel_crtc *crtc,
8462 struct intel_crtc_config *pipe_config,
8463 const char *context)
8464{
8465 DRM_DEBUG_KMS("[CRTC:%d]%s config for pipe %c\n", crtc->base.base.id,
8466 context, pipe_name(crtc->pipe));
8467
8468 DRM_DEBUG_KMS("cpu_transcoder: %c\n", transcoder_name(pipe_config->cpu_transcoder));
8469 DRM_DEBUG_KMS("pipe bpp: %i, dithering: %i\n",
8470 pipe_config->pipe_bpp, pipe_config->dither);
8471 DRM_DEBUG_KMS("fdi/pch: %i, lanes: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8472 pipe_config->has_pch_encoder,
8473 pipe_config->fdi_lanes,
8474 pipe_config->fdi_m_n.gmch_m, pipe_config->fdi_m_n.gmch_n,
8475 pipe_config->fdi_m_n.link_m, pipe_config->fdi_m_n.link_n,
8476 pipe_config->fdi_m_n.tu);
eb14cb74
VS		 8477 DRM_DEBUG_KMS("dp: %i, gmch_m: %u, gmch_n: %u, link_m: %u, link_n: %u, tu: %u\n",
8478 pipe_config->has_dp_encoder,
8479 pipe_config->dp_m_n.gmch_m, pipe_config->dp_m_n.gmch_n,
8480 pipe_config->dp_m_n.link_m, pipe_config->dp_m_n.link_n,
8481 pipe_config->dp_m_n.tu);
c0b03411
DV		 8482 DRM_DEBUG_KMS("requested mode:\n");
8483 drm_mode_debug_printmodeline(&pipe_config->requested_mode);
8484 DRM_DEBUG_KMS("adjusted mode:\n");
8485 drm_mode_debug_printmodeline(&pipe_config->adjusted_mode);
644db711 8486 intel_dump_crtc_timings(&pipe_config->adjusted_mode);
d71b8d4a 8487 DRM_DEBUG_KMS("port clock: %d\n", pipe_config->port_clock);
37327abd
VS		 8488 DRM_DEBUG_KMS("pipe src size: %dx%d\n",
8489 pipe_config->pipe_src_w, pipe_config->pipe_src_h);
c0b03411
DV		 8490 DRM_DEBUG_KMS("gmch pfit: control: 0x%08x, ratios: 0x%08x, lvds border: 0x%08x\n",
8491 pipe_config->gmch_pfit.control,
8492 pipe_config->gmch_pfit.pgm_ratios,
8493 pipe_config->gmch_pfit.lvds_border_bits);
fd4daa9c 8494 DRM_DEBUG_KMS("pch pfit: pos: 0x%08x, size: 0x%08x, %s\n",
c0b03411 8495 pipe_config->pch_pfit.pos,
fd4daa9c
CW		 8496 pipe_config->pch_pfit.size,
8497 pipe_config->pch_pfit.enabled ? "enabled" : "disabled");
42db64ef 8498 DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
cf532bb2 8499 DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
c0b03411
DV		 8500}
8501
accfc0c5
DV		 8502static bool check_encoder_cloning(struct drm_crtc *crtc)
8503{
8504 int num_encoders = 0;
8505 bool uncloneable_encoders = false;
8506 struct intel_encoder *encoder;
8507
8508 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list,
8509 base.head) {
8510 if (&encoder->new_crtc->base != crtc)
8511 continue;
8512
8513 num_encoders++;
8514 if (!encoder->cloneable)
8515 uncloneable_encoders = true;
8516 }
8517
8518 return !(num_encoders > 1 && uncloneable_encoders);
8519}
8520
b8cecdf5
DV		 8521static struct intel_crtc_config *
8522intel_modeset_pipe_config(struct drm_crtc *crtc,
4e53c2e0 8523 struct drm_framebuffer *fb,
b8cecdf5 8524 struct drm_display_mode *mode)
ee7b9f93 8525{
7758a113 8526 struct drm_device *dev = crtc->dev;
7758a113 8527 struct intel_encoder *encoder;
b8cecdf5 8528 struct intel_crtc_config *pipe_config;
e29c22c0
DV		 8529 int plane_bpp, ret = -EINVAL;
8530 bool retry = true;
ee7b9f93 8531
accfc0c5
DV		 8532 if (!check_encoder_cloning(crtc)) {
8533 DRM_DEBUG_KMS("rejecting invalid cloning configuration\n");
8534 return ERR_PTR(-EINVAL);
8535 }
8536
b8cecdf5
DV		 8537 pipe_config = kzalloc(sizeof(*pipe_config), GFP_KERNEL);
8538 if (!pipe_config)
7758a113
DV		 8539 return ERR_PTR(-ENOMEM);
8540
b8cecdf5
DV		 8541 drm_mode_copy(&pipe_config->adjusted_mode, mode);
8542 drm_mode_copy(&pipe_config->requested_mode, mode);
37327abd 8543
e143a21c
DV		 8544 pipe_config->cpu_transcoder =
8545 (enum transcoder) to_intel_crtc(crtc)->pipe;
c0d43d62 8546 pipe_config->shared_dpll = DPLL_ID_PRIVATE;
b8cecdf5 8547
2960bc9c
ID		 8548 /*
8549 * Sanitize sync polarity flags based on requested ones. If neither
8550 * positive or negative polarity is requested, treat this as meaning
8551 * negative polarity.
8552 */
8553 if (!(pipe_config->adjusted_mode.flags &
8554 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
8555 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
8556
8557 if (!(pipe_config->adjusted_mode.flags &
8558 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
8559 pipe_config->adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
8560
050f7aeb
DV		 8561 /* Compute a starting value for pipe_config->pipe_bpp taking the source
8562 * plane pixel format and any sink constraints into account. Returns the
8563 * source plane bpp so that dithering can be selected on mismatches
8564 * after encoders and crtc also have had their say. */
8565 plane_bpp = compute_baseline_pipe_bpp(to_intel_crtc(crtc),
8566 fb, pipe_config);
4e53c2e0
DV		 8567 if (plane_bpp < 0)
8568 goto fail;
8569
e41a56be
VS		 8570 /*
8571 * Determine the real pipe dimensions. Note that stereo modes can
8572 * increase the actual pipe size due to the frame doubling and
8573 * insertion of additional space for blanks between the frame. This
8574 * is stored in the crtc timings. We use the requested mode to do this
8575 * computation to clearly distinguish it from the adjusted mode, which
8576 * can be changed by the connectors in the below retry loop.
8577 */
8578 drm_mode_set_crtcinfo(&pipe_config->requested_mode, CRTC_STEREO_DOUBLE);
8579 pipe_config->pipe_src_w = pipe_config->requested_mode.crtc_hdisplay;
8580 pipe_config->pipe_src_h = pipe_config->requested_mode.crtc_vdisplay;
8581
e29c22c0 8582encoder_retry:
ef1b460d 8583 /* Ensure the port clock defaults are reset when retrying. */
ff9a6750 8584 pipe_config->port_clock = 0;
ef1b460d 8585 pipe_config->pixel_multiplier = 1;
ff9a6750 8586
135c81b8 8587 /* Fill in default crtc timings, allow encoders to overwrite them. */
6ce70f5e 8588 drm_mode_set_crtcinfo(&pipe_config->adjusted_mode, CRTC_STEREO_DOUBLE);
135c81b8 8589
7758a113
DV		 8590 /* Pass our mode to the connectors and the CRTC to give them a chance to
8591 * adjust it according to limitations or connector properties, and also
8592 * a chance to reject the mode entirely.
47f1c6c9 8593 */
7758a113
DV		 8594 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8595 base.head) {
47f1c6c9 8596
7758a113
DV		 8597 if (&encoder->new_crtc->base != crtc)
8598 continue;
7ae89233 8599
efea6e8e
DV		 8600 if (!(encoder->compute_config(encoder, pipe_config))) {
8601 DRM_DEBUG_KMS("Encoder config failure\n");
7758a113
DV		 8602 goto fail;
8603 }
ee7b9f93 8604 }
47f1c6c9 8605
ff9a6750
DV		 8606 /* Set default port clock if not overwritten by the encoder. Needs to be
8607 * done afterwards in case the encoder adjusts the mode. */
8608 if (!pipe_config->port_clock)
241bfc38
DL		 8609 pipe_config->port_clock = pipe_config->adjusted_mode.crtc_clock
8610 * pipe_config->pixel_multiplier;
ff9a6750 8611
a43f6e0f 8612 ret = intel_crtc_compute_config(to_intel_crtc(crtc), pipe_config);
e29c22c0 8613 if (ret < 0) {
7758a113
DV		 8614 DRM_DEBUG_KMS("CRTC fixup failed\n");
8615 goto fail;
ee7b9f93 8616 }
e29c22c0
DV		 8617
8618 if (ret == RETRY) {
8619 if (WARN(!retry, "loop in pipe configuration computation\n")) {
8620 ret = -EINVAL;
8621 goto fail;
8622 }
8623
8624 DRM_DEBUG_KMS("CRTC bw constrained, retrying\n");
8625 retry = false;
8626 goto encoder_retry;
8627 }
8628
4e53c2e0
DV		 8629 pipe_config->dither = pipe_config->pipe_bpp != plane_bpp;
8630 DRM_DEBUG_KMS("plane bpp: %i, pipe bpp: %i, dithering: %i\n",
8631 plane_bpp, pipe_config->pipe_bpp, pipe_config->dither);
8632
b8cecdf5 8633 return pipe_config;
7758a113 8634fail:
b8cecdf5 8635 kfree(pipe_config);
e29c22c0 8636 return ERR_PTR(ret);
ee7b9f93 8637}
47f1c6c9 8638
e2e1ed41
DV		 8639/* Computes which crtcs are affected and sets the relevant bits in the mask. For
8640 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
8641static void
8642intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
8643 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 8644{
8645 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 8646 struct drm_device *dev = crtc->dev;
8647 struct intel_encoder *encoder;
8648 struct intel_connector *connector;
8649 struct drm_crtc *tmp_crtc;
79e53945 8650
e2e1ed41 8651 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 8652
e2e1ed41
DV		 8653 /* Check which crtcs have changed outputs connected to them, these need
8654 * to be part of the prepare_pipes mask. We don't (yet) support global
8655 * modeset across multiple crtcs, so modeset_pipes will only have one
8656 * bit set at most. */
8657 list_for_each_entry(connector, &dev->mode_config.connector_list,
8658 base.head) {
8659 if (connector->base.encoder == &connector->new_encoder->base)
8660 continue;
79e53945 8661
e2e1ed41
DV		 8662 if (connector->base.encoder) {
8663 tmp_crtc = connector->base.encoder->crtc;
8664
8665 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8666 }
8667
8668 if (connector->new_encoder)
8669 *prepare_pipes |=
8670 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 8671 }
8672
e2e1ed41
DV		 8673 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8674 base.head) {
8675 if (encoder->base.crtc == &encoder->new_crtc->base)
8676 continue;
8677
8678 if (encoder->base.crtc) {
8679 tmp_crtc = encoder->base.crtc;
8680
8681 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
8682 }
8683
8684 if (encoder->new_crtc)
8685 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 8686 }
8687
e2e1ed41
DV		 8688 /* Check for any pipes that will be fully disabled ... */
8689 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8690 base.head) {
8691 bool used = false;
22fd0fab 8692
e2e1ed41
DV		 8693 /* Don't try to disable disabled crtcs. */
8694 if (!intel_crtc->base.enabled)
8695 continue;
7e7d76c3 8696
e2e1ed41
DV		 8697 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8698 base.head) {
8699 if (encoder->new_crtc == intel_crtc)
8700 used = true;
8701 }
8702
8703 if (!used)
8704 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 8705 }
8706
e2e1ed41
DV		 8707
8708 /* set_mode is also used to update properties on life display pipes. */
8709 intel_crtc = to_intel_crtc(crtc);
8710 if (crtc->enabled)
8711 *prepare_pipes |= 1 << intel_crtc->pipe;
8712
b6c5164d
DV		 8713 /*
8714 * For simplicity do a full modeset on any pipe where the output routing
8715 * changed. We could be more clever, but that would require us to be
8716 * more careful with calling the relevant encoder->mode_set functions.
8717 */
e2e1ed41
DV		 8718 if (*prepare_pipes)
8719 *modeset_pipes = *prepare_pipes;
8720
8721 /* ... and mask these out. */
8722 *modeset_pipes &= ~(*disable_pipes);
8723 *prepare_pipes &= ~(*disable_pipes);
b6c5164d
DV		 8724
8725 /*
8726 * HACK: We don't (yet) fully support global modesets. intel_set_config
8727 * obies this rule, but the modeset restore mode of
8728 * intel_modeset_setup_hw_state does not.
8729 */
8730 *modeset_pipes &= 1 << intel_crtc->pipe;
8731 *prepare_pipes &= 1 << intel_crtc->pipe;
e3641d3f
DV		 8732
8733 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
8734 *modeset_pipes, *prepare_pipes, *disable_pipes);
47f1c6c9 8735}
79e53945 8736
ea9d758d 8737static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 8738{
ea9d758d 8739 struct drm_encoder *encoder;
f6e5b160 8740 struct drm_device *dev = crtc->dev;
f6e5b160 8741
ea9d758d
DV		 8742 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
8743 if (encoder->crtc == crtc)
8744 return true;
8745
8746 return false;
8747}
8748
8749static void
8750intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
8751{
8752 struct intel_encoder *intel_encoder;
8753 struct intel_crtc *intel_crtc;
8754 struct drm_connector *connector;
8755
8756 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
8757 base.head) {
8758 if (!intel_encoder->base.crtc)
8759 continue;
8760
8761 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
8762
8763 if (prepare_pipes & (1 << intel_crtc->pipe))
8764 intel_encoder->connectors_active = false;
8765 }
8766
8767 intel_modeset_commit_output_state(dev);
8768
8769 /* Update computed state. */
8770 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
8771 base.head) {
8772 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
8773 }
8774
8775 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
8776 if (!connector->encoder || !connector->encoder->crtc)
8777 continue;
8778
8779 intel_crtc = to_intel_crtc(connector->encoder->crtc);
8780
8781 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 8782 struct drm_property *dpms_property =
8783 dev->mode_config.dpms_property;
8784
ea9d758d 8785 connector->dpms = DRM_MODE_DPMS_ON;
662595df 8786 drm_object_property_set_value(&connector->base,
68d34720
DV		 8787 dpms_property,
8788 DRM_MODE_DPMS_ON);
ea9d758d
DV		 8789
8790 intel_encoder = to_intel_encoder(connector->encoder);
8791 intel_encoder->connectors_active = true;
8792 }
8793 }
8794
8795}
8796
3bd26263 8797static bool intel_fuzzy_clock_check(int clock1, int clock2)
f1f644dc 8798{
3bd26263 8799 int diff;
f1f644dc
JB		 8800
8801 if (clock1 == clock2)
8802 return true;
8803
8804 if (!clock1 || !clock2)
8805 return false;
8806
8807 diff = abs(clock1 - clock2);
8808
8809 if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
8810 return true;
8811
8812 return false;
8813}
8814
25c5b266
DV		 8815#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
8816 list_for_each_entry((intel_crtc), \
8817 &(dev)->mode_config.crtc_list, \
8818 base.head) \
0973f18f 8819 if (mask & (1 <<(intel_crtc)->pipe))
25c5b266 8820
0e8ffe1b 8821static bool
2fa2fe9a
DV		 8822intel_pipe_config_compare(struct drm_device *dev,
8823 struct intel_crtc_config *current_config,
0e8ffe1b
DV		 8824 struct intel_crtc_config *pipe_config)
8825{
66e985c0
DV		 8826#define PIPE_CONF_CHECK_X(name) \
8827 if (current_config->name != pipe_config->name) { \
8828 DRM_ERROR("mismatch in " #name " " \
8829 "(expected 0x%08x, found 0x%08x)\n", \
8830 current_config->name, \
8831 pipe_config->name); \
8832 return false; \
8833 }
8834
08a24034
DV		 8835#define PIPE_CONF_CHECK_I(name) \
8836 if (current_config->name != pipe_config->name) { \
8837 DRM_ERROR("mismatch in " #name " " \
8838 "(expected %i, found %i)\n", \
8839 current_config->name, \
8840 pipe_config->name); \
8841 return false; \
88adfff1
DV		 8842 }
8843
1bd1bd80
DV		 8844#define PIPE_CONF_CHECK_FLAGS(name, mask) \
8845 if ((current_config->name ^ pipe_config->name) & (mask)) { \
6f02488e 8846 DRM_ERROR("mismatch in " #name "(" #mask ") " \
1bd1bd80
DV		 8847 "(expected %i, found %i)\n", \
8848 current_config->name & (mask), \
8849 pipe_config->name & (mask)); \
8850 return false; \
8851 }
8852
5e550656
VS		 8853#define PIPE_CONF_CHECK_CLOCK_FUZZY(name) \
8854 if (!intel_fuzzy_clock_check(current_config->name, pipe_config->name)) { \
8855 DRM_ERROR("mismatch in " #name " " \
8856 "(expected %i, found %i)\n", \
8857 current_config->name, \
8858 pipe_config->name); \
8859 return false; \
8860 }
8861
bb760063
DV		 8862#define PIPE_CONF_QUIRK(quirk) \
8863 ((current_config->quirks | pipe_config->quirks) & (quirk))
8864
eccb140b
DV		 8865 PIPE_CONF_CHECK_I(cpu_transcoder);
8866
08a24034
DV		 8867 PIPE_CONF_CHECK_I(has_pch_encoder);
8868 PIPE_CONF_CHECK_I(fdi_lanes);
72419203
DV		 8869 PIPE_CONF_CHECK_I(fdi_m_n.gmch_m);
8870 PIPE_CONF_CHECK_I(fdi_m_n.gmch_n);
8871 PIPE_CONF_CHECK_I(fdi_m_n.link_m);
8872 PIPE_CONF_CHECK_I(fdi_m_n.link_n);
8873 PIPE_CONF_CHECK_I(fdi_m_n.tu);
08a24034 8874
eb14cb74
VS		 8875 PIPE_CONF_CHECK_I(has_dp_encoder);
8876 PIPE_CONF_CHECK_I(dp_m_n.gmch_m);
8877 PIPE_CONF_CHECK_I(dp_m_n.gmch_n);
8878 PIPE_CONF_CHECK_I(dp_m_n.link_m);
8879 PIPE_CONF_CHECK_I(dp_m_n.link_n);
8880 PIPE_CONF_CHECK_I(dp_m_n.tu);
8881
1bd1bd80
DV		 8882 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hdisplay);
8883 PIPE_CONF_CHECK_I(adjusted_mode.crtc_htotal);
8884 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_start);
8885 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hblank_end);
8886 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_start);
8887 PIPE_CONF_CHECK_I(adjusted_mode.crtc_hsync_end);
8888
8889 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vdisplay);
8890 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vtotal);
8891 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_start);
8892 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vblank_end);
8893 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_start);
8894 PIPE_CONF_CHECK_I(adjusted_mode.crtc_vsync_end);
8895
c93f54cf 8896 PIPE_CONF_CHECK_I(pixel_multiplier);
6c49f241 8897
1bd1bd80
DV		 8898 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8899 DRM_MODE_FLAG_INTERLACE);
8900
bb760063
DV		 8901 if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
8902 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8903 DRM_MODE_FLAG_PHSYNC);
8904 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8905 DRM_MODE_FLAG_NHSYNC);
8906 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8907 DRM_MODE_FLAG_PVSYNC);
8908 PIPE_CONF_CHECK_FLAGS(adjusted_mode.flags,
8909 DRM_MODE_FLAG_NVSYNC);
8910 }
045ac3b5 8911
37327abd
VS		 8912 PIPE_CONF_CHECK_I(pipe_src_w);
8913 PIPE_CONF_CHECK_I(pipe_src_h);
1bd1bd80 8914
2fa2fe9a
DV		 8915 PIPE_CONF_CHECK_I(gmch_pfit.control);
8916 /* pfit ratios are autocomputed by the hw on gen4+ */
8917 if (INTEL_INFO(dev)->gen < 4)
8918 PIPE_CONF_CHECK_I(gmch_pfit.pgm_ratios);
8919 PIPE_CONF_CHECK_I(gmch_pfit.lvds_border_bits);
fd4daa9c
CW		 8920 PIPE_CONF_CHECK_I(pch_pfit.enabled);
8921 if (current_config->pch_pfit.enabled) {
8922 PIPE_CONF_CHECK_I(pch_pfit.pos);
8923 PIPE_CONF_CHECK_I(pch_pfit.size);
8924 }
2fa2fe9a 8925
42db64ef
PZ		 8926 PIPE_CONF_CHECK_I(ips_enabled);
8927
282740f7
VS		 8928 PIPE_CONF_CHECK_I(double_wide);
8929
c0d43d62 8930 PIPE_CONF_CHECK_I(shared_dpll);
66e985c0 8931 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
8bcc2795 8932 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
66e985c0
DV		 8933 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
8934 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
c0d43d62 8935
42571aef
VS		 8936 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5)
8937 PIPE_CONF_CHECK_I(pipe_bpp);
8938
d71b8d4a 8939 if (!IS_HASWELL(dev)) {
241bfc38 8940 PIPE_CONF_CHECK_CLOCK_FUZZY(adjusted_mode.crtc_clock);
d71b8d4a
VS		 8941 PIPE_CONF_CHECK_CLOCK_FUZZY(port_clock);
8942 }
5e550656 8943
66e985c0 8944#undef PIPE_CONF_CHECK_X
08a24034 8945#undef PIPE_CONF_CHECK_I
1bd1bd80 8946#undef PIPE_CONF_CHECK_FLAGS
5e550656 8947#undef PIPE_CONF_CHECK_CLOCK_FUZZY
bb760063 8948#undef PIPE_CONF_QUIRK
88adfff1 8949
0e8ffe1b
DV		 8950 return true;
8951}
8952
91d1b4bd
DV		 8953static void
8954check_connector_state(struct drm_device *dev)
8af6cf88 8955{
8af6cf88
DV		 8956 struct intel_connector *connector;
8957
8958 list_for_each_entry(connector, &dev->mode_config.connector_list,
8959 base.head) {
8960 /* This also checks the encoder/connector hw state with the
8961 * ->get_hw_state callbacks. */
8962 intel_connector_check_state(connector);
8963
8964 WARN(&connector->new_encoder->base != connector->base.encoder,
8965 "connector's staged encoder doesn't match current encoder\n");
8966 }
91d1b4bd
DV		 8967}
8968
8969static void
8970check_encoder_state(struct drm_device *dev)
8971{
8972 struct intel_encoder *encoder;
8973 struct intel_connector *connector;
8af6cf88
DV		 8974
8975 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8976 base.head) {
8977 bool enabled = false;
8978 bool active = false;
8979 enum pipe pipe, tracked_pipe;
8980
8981 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
8982 encoder->base.base.id,
8983 drm_get_encoder_name(&encoder->base));
8984
8985 WARN(&encoder->new_crtc->base != encoder->base.crtc,
8986 "encoder's stage crtc doesn't match current crtc\n");
8987 WARN(encoder->connectors_active && !encoder->base.crtc,
8988 "encoder's active_connectors set, but no crtc\n");
8989
8990 list_for_each_entry(connector, &dev->mode_config.connector_list,
8991 base.head) {
8992 if (connector->base.encoder != &encoder->base)
8993 continue;
8994 enabled = true;
8995 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
8996 active = true;
8997 }
8998 WARN(!!encoder->base.crtc != enabled,
8999 "encoder's enabled state mismatch "
9000 "(expected %i, found %i)\n",
9001 !!encoder->base.crtc, enabled);
9002 WARN(active && !encoder->base.crtc,
9003 "active encoder with no crtc\n");
9004
9005 WARN(encoder->connectors_active != active,
9006 "encoder's computed active state doesn't match tracked active state "
9007 "(expected %i, found %i)\n", active, encoder->connectors_active);
9008
9009 active = encoder->get_hw_state(encoder, &pipe);
9010 WARN(active != encoder->connectors_active,
9011 "encoder's hw state doesn't match sw tracking "
9012 "(expected %i, found %i)\n",
9013 encoder->connectors_active, active);
9014
9015 if (!encoder->base.crtc)
9016 continue;
9017
9018 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
9019 WARN(active && pipe != tracked_pipe,
9020 "active encoder's pipe doesn't match"
9021 "(expected %i, found %i)\n",
9022 tracked_pipe, pipe);
9023
9024 }
91d1b4bd
DV		 9025}
9026
9027static void
9028check_crtc_state(struct drm_device *dev)
9029{
9030 drm_i915_private_t *dev_priv = dev->dev_private;
9031 struct intel_crtc *crtc;
9032 struct intel_encoder *encoder;
9033 struct intel_crtc_config pipe_config;
8af6cf88
DV		 9034
9035 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9036 base.head) {
9037 bool enabled = false;
9038 bool active = false;
9039
045ac3b5
JB		 9040 memset(&pipe_config, 0, sizeof(pipe_config));
9041
8af6cf88
DV		 9042 DRM_DEBUG_KMS("[CRTC:%d]\n",
9043 crtc->base.base.id);
9044
9045 WARN(crtc->active && !crtc->base.enabled,
9046 "active crtc, but not enabled in sw tracking\n");
9047
9048 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9049 base.head) {
9050 if (encoder->base.crtc != &crtc->base)
9051 continue;
9052 enabled = true;
9053 if (encoder->connectors_active)
9054 active = true;
9055 }
6c49f241 9056
8af6cf88
DV		 9057 WARN(active != crtc->active,
9058 "crtc's computed active state doesn't match tracked active state "
9059 "(expected %i, found %i)\n", active, crtc->active);
9060 WARN(enabled != crtc->base.enabled,
9061 "crtc's computed enabled state doesn't match tracked enabled state "
9062 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
9063
0e8ffe1b
DV		 9064 active = dev_priv->display.get_pipe_config(crtc,
9065 &pipe_config);
d62cf62a
DV		 9066
9067 /* hw state is inconsistent with the pipe A quirk */
9068 if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
9069 active = crtc->active;
9070
6c49f241
DV		 9071 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9072 base.head) {
3eaba51c 9073 enum pipe pipe;
6c49f241
DV		 9074 if (encoder->base.crtc != &crtc->base)
9075 continue;
3eaba51c
VS		 9076 if (encoder->get_config &&
9077 encoder->get_hw_state(encoder, &pipe))
6c49f241
DV		 9078 encoder->get_config(encoder, &pipe_config);
9079 }
9080
0e8ffe1b
DV		 9081 WARN(crtc->active != active,
9082 "crtc active state doesn't match with hw state "
9083 "(expected %i, found %i)\n", crtc->active, active);
9084
c0b03411
DV		 9085 if (active &&
9086 !intel_pipe_config_compare(dev, &crtc->config, &pipe_config)) {
9087 WARN(1, "pipe state doesn't match!\n");
9088 intel_dump_pipe_config(crtc, &pipe_config,
9089 "[hw state]");
9090 intel_dump_pipe_config(crtc, &crtc->config,
9091 "[sw state]");
9092 }
8af6cf88
DV		 9093 }
9094}
9095
91d1b4bd
DV		 9096static void
9097check_shared_dpll_state(struct drm_device *dev)
9098{
9099 drm_i915_private_t *dev_priv = dev->dev_private;
9100 struct intel_crtc *crtc;
9101 struct intel_dpll_hw_state dpll_hw_state;
9102 int i;
5358901f
DV		 9103
9104 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
9105 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
9106 int enabled_crtcs = 0, active_crtcs = 0;
9107 bool active;
9108
9109 memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
9110
9111 DRM_DEBUG_KMS("%s\n", pll->name);
9112
9113 active = pll->get_hw_state(dev_priv, pll, &dpll_hw_state);
9114
9115 WARN(pll->active > pll->refcount,
9116 "more active pll users than references: %i vs %i\n",
9117 pll->active, pll->refcount);
9118 WARN(pll->active && !pll->on,
9119 "pll in active use but not on in sw tracking\n");
35c95375
DV		 9120 WARN(pll->on && !pll->active,
9121 "pll in on but not on in use in sw tracking\n");
5358901f
DV		 9122 WARN(pll->on != active,
9123 "pll on state mismatch (expected %i, found %i)\n",
9124 pll->on, active);
9125
9126 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
9127 base.head) {
9128 if (crtc->base.enabled && intel_crtc_to_shared_dpll(crtc) == pll)
9129 enabled_crtcs++;
9130 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
9131 active_crtcs++;
9132 }
9133 WARN(pll->active != active_crtcs,
9134 "pll active crtcs mismatch (expected %i, found %i)\n",
9135 pll->active, active_crtcs);
9136 WARN(pll->refcount != enabled_crtcs,
9137 "pll enabled crtcs mismatch (expected %i, found %i)\n",
9138 pll->refcount, enabled_crtcs);
66e985c0
DV		 9139
9140 WARN(pll->on && memcmp(&pll->hw_state, &dpll_hw_state,
9141 sizeof(dpll_hw_state)),
9142 "pll hw state mismatch\n");
5358901f 9143 }
8af6cf88
DV		 9144}
9145
91d1b4bd
DV		 9146void
9147intel_modeset_check_state(struct drm_device *dev)
9148{
9149 check_connector_state(dev);
9150 check_encoder_state(dev);
9151 check_crtc_state(dev);
9152 check_shared_dpll_state(dev);
9153}
9154
18442d08
VS		 9155void ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config,
9156 int dotclock)
9157{
9158 /*
9159 * FDI already provided one idea for the dotclock.
9160 * Yell if the encoder disagrees.
9161 */
241bfc38 9162 WARN(!intel_fuzzy_clock_check(pipe_config->adjusted_mode.crtc_clock, dotclock),
18442d08 9163 "FDI dotclock and encoder dotclock mismatch, fdi: %i, encoder: %i\n",
241bfc38 9164 pipe_config->adjusted_mode.crtc_clock, dotclock);
18442d08
VS		 9165}
9166
f30da187
DV		 9167static int __intel_set_mode(struct drm_crtc *crtc,
9168 struct drm_display_mode *mode,
9169 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 9170{
9171 struct drm_device *dev = crtc->dev;
dbf2b54e 9172 drm_i915_private_t *dev_priv = dev->dev_private;
b8cecdf5
DV		 9173 struct drm_display_mode *saved_mode, *saved_hwmode;
9174 struct intel_crtc_config *pipe_config = NULL;
25c5b266
DV		 9175 struct intel_crtc *intel_crtc;
9176 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 9177 int ret = 0;
a6778b3c 9178
a1e22653 9179 saved_mode = kcalloc(2, sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 9180 if (!saved_mode)
9181 return -ENOMEM;
3ac18232 9182 saved_hwmode = saved_mode + 1;
a6778b3c 9183
e2e1ed41 9184 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 9185 &prepare_pipes, &disable_pipes);
9186
3ac18232
TG		 9187 *saved_hwmode = crtc->hwmode;
9188 *saved_mode = crtc->mode;
a6778b3c 9189
25c5b266
DV		 9190 /* Hack: Because we don't (yet) support global modeset on multiple
9191 * crtcs, we don't keep track of the new mode for more than one crtc.
9192 * Hence simply check whether any bit is set in modeset_pipes in all the
9193 * pieces of code that are not yet converted to deal with mutliple crtcs
9194 * changing their mode at the same time. */
25c5b266 9195 if (modeset_pipes) {
4e53c2e0 9196 pipe_config = intel_modeset_pipe_config(crtc, fb, mode);
b8cecdf5
DV		 9197 if (IS_ERR(pipe_config)) {
9198 ret = PTR_ERR(pipe_config);
9199 pipe_config = NULL;
9200
3ac18232 9201 goto out;
25c5b266 9202 }
c0b03411
DV		 9203 intel_dump_pipe_config(to_intel_crtc(crtc), pipe_config,
9204 "[modeset]");
25c5b266 9205 }
a6778b3c 9206
460da916
DV		 9207 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
9208 intel_crtc_disable(&intel_crtc->base);
9209
ea9d758d
DV		 9210 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
9211 if (intel_crtc->base.enabled)
9212 dev_priv->display.crtc_disable(&intel_crtc->base);
9213 }
a6778b3c 9214
6c4c86f5
DV		 9215 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
9216 * to set it here already despite that we pass it down the callchain.
f6e5b160 9217 */
b8cecdf5 9218 if (modeset_pipes) {
25c5b266 9219 crtc->mode = *mode;
b8cecdf5
DV		 9220 /* mode_set/enable/disable functions rely on a correct pipe
9221 * config. */
9222 to_intel_crtc(crtc)->config = *pipe_config;
9223 }
7758a113 9224
ea9d758d
DV		 9225 /* Only after disabling all output pipelines that will be changed can we
9226 * update the the output configuration. */
9227 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 9228
47fab737
DV		 9229 if (dev_priv->display.modeset_global_resources)
9230 dev_priv->display.modeset_global_resources(dev);
9231
a6778b3c
DV		 9232 /* Set up the DPLL and any encoders state that needs to adjust or depend
9233 * on the DPLL.
f6e5b160 9234 */
25c5b266 9235 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94 9236 ret = intel_crtc_mode_set(&intel_crtc->base,
c0c36b94
CW		 9237 x, y, fb);
9238 if (ret)
9239 goto done;
a6778b3c
DV		 9240 }
9241
9242 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 9243 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
9244 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 9245
25c5b266
DV		 9246 if (modeset_pipes) {
9247 /* Store real post-adjustment hardware mode. */
b8cecdf5 9248 crtc->hwmode = pipe_config->adjusted_mode;
a6778b3c 9249
25c5b266
DV		 9250 /* Calculate and store various constants which
9251 * are later needed by vblank and swap-completion
9252 * timestamping. They are derived from true hwmode.
9253 */
9254 drm_calc_timestamping_constants(crtc);
9255 }
a6778b3c
DV		 9256
9257 /* FIXME: add subpixel order */
9258done:
c0c36b94 9259 if (ret && crtc->enabled) {
3ac18232
TG		 9260 crtc->hwmode = *saved_hwmode;
9261 crtc->mode = *saved_mode;
a6778b3c
DV		 9262 }
9263
3ac18232 9264out:
b8cecdf5 9265 kfree(pipe_config);
3ac18232 9266 kfree(saved_mode);
a6778b3c 9267 return ret;
f6e5b160
CW		 9268}
9269
e7457a9a
DL		 9270static int intel_set_mode(struct drm_crtc *crtc,
9271 struct drm_display_mode *mode,
9272 int x, int y, struct drm_framebuffer *fb)
f30da187
DV		 9273{
9274 int ret;
9275
9276 ret = __intel_set_mode(crtc, mode, x, y, fb);
9277
9278 if (ret == 0)
9279 intel_modeset_check_state(crtc->dev);
9280
9281 return ret;
9282}
9283
c0c36b94
CW		 9284void intel_crtc_restore_mode(struct drm_crtc *crtc)
9285{
9286 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
9287}
9288
25c5b266
DV		 9289#undef for_each_intel_crtc_masked
9290
d9e55608
DV		 9291static void intel_set_config_free(struct intel_set_config *config)
9292{
9293 if (!config)
9294 return;
9295
1aa4b628
DV		 9296 kfree(config->save_connector_encoders);
9297 kfree(config->save_encoder_crtcs);
d9e55608
DV		 9298 kfree(config);
9299}
9300
85f9eb71
DV		 9301static int intel_set_config_save_state(struct drm_device *dev,
9302 struct intel_set_config *config)
9303{
85f9eb71
DV		 9304 struct drm_encoder *encoder;
9305 struct drm_connector *connector;
9306 int count;
9307
1aa4b628
DV		 9308 config->save_encoder_crtcs =
9309 kcalloc(dev->mode_config.num_encoder,
9310 sizeof(struct drm_crtc *), GFP_KERNEL);
9311 if (!config->save_encoder_crtcs)
85f9eb71
DV		 9312 return -ENOMEM;
9313
1aa4b628
DV		 9314 config->save_connector_encoders =
9315 kcalloc(dev->mode_config.num_connector,
9316 sizeof(struct drm_encoder *), GFP_KERNEL);
9317 if (!config->save_connector_encoders)
85f9eb71
DV		 9318 return -ENOMEM;
9319
9320 /* Copy data. Note that driver private data is not affected.
9321 * Should anything bad happen only the expected state is
9322 * restored, not the drivers personal bookkeeping.
9323 */
85f9eb71
DV		 9324 count = 0;
9325 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 9326 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 9327 }
9328
9329 count = 0;
9330 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 9331 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 9332 }
9333
9334 return 0;
9335}
9336
9337static void intel_set_config_restore_state(struct drm_device *dev,
9338 struct intel_set_config *config)
9339{
9a935856
DV		 9340 struct intel_encoder *encoder;
9341 struct intel_connector *connector;
85f9eb71
DV		 9342 int count;
9343
85f9eb71 9344 count = 0;
9a935856
DV		 9345 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9346 encoder->new_crtc =
9347 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 9348 }
9349
9350 count = 0;
9a935856
DV		 9351 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
9352 connector->new_encoder =
9353 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 9354 }
9355}
9356
e3de42b6 9357static bool
2e57f47d 9358is_crtc_connector_off(struct drm_mode_set *set)
e3de42b6
ID		 9359{
9360 int i;
9361
2e57f47d
CW		 9362 if (set->num_connectors == 0)
9363 return false;
9364
9365 if (WARN_ON(set->connectors == NULL))
9366 return false;
9367
9368 for (i = 0; i < set->num_connectors; i++)
9369 if (set->connectors[i]->encoder &&
9370 set->connectors[i]->encoder->crtc == set->crtc &&
9371 set->connectors[i]->dpms != DRM_MODE_DPMS_ON)
e3de42b6
ID		 9372 return true;
9373
9374 return false;
9375}
9376
5e2b584e
DV		 9377static void
9378intel_set_config_compute_mode_changes(struct drm_mode_set *set,
9379 struct intel_set_config *config)
9380{
9381
9382 /* We should be able to check here if the fb has the same properties
9383 * and then just flip_or_move it */
2e57f47d
CW		 9384 if (is_crtc_connector_off(set)) {
9385 config->mode_changed = true;
e3de42b6 9386 } else if (set->crtc->fb != set->fb) {
5e2b584e
DV		 9387 /* If we have no fb then treat it as a full mode set */
9388 if (set->crtc->fb == NULL) {
319d9827
JB		 9389 struct intel_crtc *intel_crtc =
9390 to_intel_crtc(set->crtc);
9391
9392 if (intel_crtc->active && i915_fastboot) {
9393 DRM_DEBUG_KMS("crtc has no fb, will flip\n");
9394 config->fb_changed = true;
9395 } else {
9396 DRM_DEBUG_KMS("inactive crtc, full mode set\n");
9397 config->mode_changed = true;
9398 }
5e2b584e
DV		 9399 } else if (set->fb == NULL) {
9400 config->mode_changed = true;
72f4901e
DV		 9401 } else if (set->fb->pixel_format !=
9402 set->crtc->fb->pixel_format) {
5e2b584e 9403 config->mode_changed = true;
e3de42b6 9404 } else {
5e2b584e 9405 config->fb_changed = true;
e3de42b6 9406 }
5e2b584e
DV		 9407 }
9408
835c5873 9409 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 9410 config->fb_changed = true;
9411
9412 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
9413 DRM_DEBUG_KMS("modes are different, full mode set\n");
9414 drm_mode_debug_printmodeline(&set->crtc->mode);
9415 drm_mode_debug_printmodeline(set->mode);
9416 config->mode_changed = true;
9417 }
a1d95703
CW		 9418
9419 DRM_DEBUG_KMS("computed changes for [CRTC:%d], mode_changed=%d, fb_changed=%d\n",
9420 set->crtc->base.id, config->mode_changed, config->fb_changed);
5e2b584e
DV		 9421}
9422
2e431051 9423static int
9a935856
DV		 9424intel_modeset_stage_output_state(struct drm_device *dev,
9425 struct drm_mode_set *set,
9426 struct intel_set_config *config)
50f56119 9427{
85f9eb71 9428 struct drm_crtc *new_crtc;
9a935856
DV		 9429 struct intel_connector *connector;
9430 struct intel_encoder *encoder;
f3f08572 9431 int ro;
50f56119 9432
9abdda74 9433 /* The upper layers ensure that we either disable a crtc or have a list
9a935856
DV		 9434 * of connectors. For paranoia, double-check this. */
9435 WARN_ON(!set->fb && (set->num_connectors != 0));
9436 WARN_ON(set->fb && (set->num_connectors == 0));
9437
9a935856
DV		 9438 list_for_each_entry(connector, &dev->mode_config.connector_list,
9439 base.head) {
9440 /* Otherwise traverse passed in connector list and get encoders
9441 * for them. */
50f56119 9442 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 9443 if (set->connectors[ro] == &connector->base) {
9444 connector->new_encoder = connector->encoder;
50f56119
DV		 9445 break;
9446 }
9447 }
9448
9a935856
DV		 9449 /* If we disable the crtc, disable all its connectors. Also, if
9450 * the connector is on the changing crtc but not on the new
9451 * connector list, disable it. */
9452 if ((!set->fb || ro == set->num_connectors) &&
9453 connector->base.encoder &&
9454 connector->base.encoder->crtc == set->crtc) {
9455 connector->new_encoder = NULL;
9456
9457 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
9458 connector->base.base.id,
9459 drm_get_connector_name(&connector->base));
9460 }
9461
9462
9463 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 9464 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 9465 config->mode_changed = true;
50f56119
DV		 9466 }
9467 }
9a935856 9468 /* connector->new_encoder is now updated for all connectors. */
50f56119 9469
9a935856 9470 /* Update crtc of enabled connectors. */
9a935856
DV		 9471 list_for_each_entry(connector, &dev->mode_config.connector_list,
9472 base.head) {
9473 if (!connector->new_encoder)
50f56119
DV		 9474 continue;
9475
9a935856 9476 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 9477
9478 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 9479 if (set->connectors[ro] == &connector->base)
50f56119
DV		 9480 new_crtc = set->crtc;
9481 }
9482
9483 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 9484 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
9485 new_crtc)) {
5e2b584e 9486 return -EINVAL;
50f56119 9487 }
9a935856
DV		 9488 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
9489
9490 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
9491 connector->base.base.id,
9492 drm_get_connector_name(&connector->base),
9493 new_crtc->base.id);
9494 }
9495
9496 /* Check for any encoders that needs to be disabled. */
9497 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9498 base.head) {
9499 list_for_each_entry(connector,
9500 &dev->mode_config.connector_list,
9501 base.head) {
9502 if (connector->new_encoder == encoder) {
9503 WARN_ON(!connector->new_encoder->new_crtc);
9504
9505 goto next_encoder;
9506 }
9507 }
9508 encoder->new_crtc = NULL;
9509next_encoder:
9510 /* Only now check for crtc changes so we don't miss encoders
9511 * that will be disabled. */
9512 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 9513 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 9514 config->mode_changed = true;
50f56119
DV		 9515 }
9516 }
9a935856 9517 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 9518
2e431051
DV		 9519 return 0;
9520}
9521
9522static int intel_crtc_set_config(struct drm_mode_set *set)
9523{
9524 struct drm_device *dev;
2e431051
DV		 9525 struct drm_mode_set save_set;
9526 struct intel_set_config *config;
9527 int ret;
2e431051 9528
8d3e375e
DV		 9529 BUG_ON(!set);
9530 BUG_ON(!set->crtc);
9531 BUG_ON(!set->crtc->helper_private);
2e431051 9532
7e53f3a4
DV		 9533 /* Enforce sane interface api - has been abused by the fb helper. */
9534 BUG_ON(!set->mode && set->fb);
9535 BUG_ON(set->fb && set->num_connectors == 0);
431e50f7 9536
2e431051
DV		 9537 if (set->fb) {
9538 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
9539 set->crtc->base.id, set->fb->base.id,
9540 (int)set->num_connectors, set->x, set->y);
9541 } else {
9542 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 9543 }
9544
9545 dev = set->crtc->dev;
9546
9547 ret = -ENOMEM;
9548 config = kzalloc(sizeof(*config), GFP_KERNEL);
9549 if (!config)
9550 goto out_config;
9551
9552 ret = intel_set_config_save_state(dev, config);
9553 if (ret)
9554 goto out_config;
9555
9556 save_set.crtc = set->crtc;
9557 save_set.mode = &set->crtc->mode;
9558 save_set.x = set->crtc->x;
9559 save_set.y = set->crtc->y;
9560 save_set.fb = set->crtc->fb;
9561
9562 /* Compute whether we need a full modeset, only an fb base update or no
9563 * change at all. In the future we might also check whether only the
9564 * mode changed, e.g. for LVDS where we only change the panel fitter in
9565 * such cases. */
9566 intel_set_config_compute_mode_changes(set, config);
9567
9a935856 9568 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 9569 if (ret)
9570 goto fail;
9571
5e2b584e 9572 if (config->mode_changed) {
c0c36b94
CW		 9573 ret = intel_set_mode(set->crtc, set->mode,
9574 set->x, set->y, set->fb);
5e2b584e 9575 } else if (config->fb_changed) {
4878cae2
VS		 9576 intel_crtc_wait_for_pending_flips(set->crtc);
9577
4f660f49 9578 ret = intel_pipe_set_base(set->crtc,
94352cf9 9579 set->x, set->y, set->fb);
50f56119
DV		 9580 }
9581
2d05eae1 9582 if (ret) {
bf67dfeb
DV		 9583 DRM_DEBUG_KMS("failed to set mode on [CRTC:%d], err = %d\n",
9584 set->crtc->base.id, ret);
50f56119 9585fail:
2d05eae1 9586 intel_set_config_restore_state(dev, config);
50f56119 9587
2d05eae1
CW		 9588 /* Try to restore the config */
9589 if (config->mode_changed &&
9590 intel_set_mode(save_set.crtc, save_set.mode,
9591 save_set.x, save_set.y, save_set.fb))
9592 DRM_ERROR("failed to restore config after modeset failure\n");
9593 }
50f56119 9594
d9e55608
DV		 9595out_config:
9596 intel_set_config_free(config);
50f56119
DV		 9597 return ret;
9598}
f6e5b160
CW		 9599
9600static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 9601 .cursor_set = intel_crtc_cursor_set,
9602 .cursor_move = intel_crtc_cursor_move,
9603 .gamma_set = intel_crtc_gamma_set,
50f56119 9604 .set_config = intel_crtc_set_config,
f6e5b160
CW		 9605 .destroy = intel_crtc_destroy,
9606 .page_flip = intel_crtc_page_flip,
9607};
9608
79f689aa
PZ		 9609static void intel_cpu_pll_init(struct drm_device *dev)
9610{
affa9354 9611 if (HAS_DDI(dev))
79f689aa
PZ		 9612 intel_ddi_pll_init(dev);
9613}
9614
5358901f
DV		 9615static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
9616 struct intel_shared_dpll *pll,
9617 struct intel_dpll_hw_state *hw_state)
ee7b9f93 9618{
5358901f 9619 uint32_t val;
ee7b9f93 9620
5358901f 9621 val = I915_READ(PCH_DPLL(pll->id));
66e985c0
DV		 9622 hw_state->dpll = val;
9623 hw_state->fp0 = I915_READ(PCH_FP0(pll->id));
9624 hw_state->fp1 = I915_READ(PCH_FP1(pll->id));
5358901f
DV		 9625
9626 return val & DPLL_VCO_ENABLE;
9627}
9628
15bdd4cf
DV		 9629static void ibx_pch_dpll_mode_set(struct drm_i915_private *dev_priv,
9630 struct intel_shared_dpll *pll)
9631{
9632 I915_WRITE(PCH_FP0(pll->id), pll->hw_state.fp0);
9633 I915_WRITE(PCH_FP1(pll->id), pll->hw_state.fp1);
9634}
9635
e7b903d2
DV		 9636static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
9637 struct intel_shared_dpll *pll)
9638{
e7b903d2
DV		 9639 /* PCH refclock must be enabled first */
9640 assert_pch_refclk_enabled(dev_priv);
9641
15bdd4cf
DV		 9642 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9643
9644 /* Wait for the clocks to stabilize. */
9645 POSTING_READ(PCH_DPLL(pll->id));
9646 udelay(150);
9647
9648 /* The pixel multiplier can only be updated once the
9649 * DPLL is enabled and the clocks are stable.
9650 *
9651 * So write it again.
9652 */
9653 I915_WRITE(PCH_DPLL(pll->id), pll->hw_state.dpll);
9654 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9655 udelay(200);
9656}
9657
9658static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
9659 struct intel_shared_dpll *pll)
9660{
9661 struct drm_device *dev = dev_priv->dev;
9662 struct intel_crtc *crtc;
e7b903d2
DV		 9663
9664 /* Make sure no transcoder isn't still depending on us. */
9665 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
9666 if (intel_crtc_to_shared_dpll(crtc) == pll)
9667 assert_pch_transcoder_disabled(dev_priv, crtc->pipe);
ee7b9f93
JB		 9668 }
9669
15bdd4cf
DV		 9670 I915_WRITE(PCH_DPLL(pll->id), 0);
9671 POSTING_READ(PCH_DPLL(pll->id));
e7b903d2
DV		 9672 udelay(200);
9673}
9674
46edb027
DV		 9675static char *ibx_pch_dpll_names[] = {
9676 "PCH DPLL A",
9677 "PCH DPLL B",
9678};
9679
7c74ade1 9680static void ibx_pch_dpll_init(struct drm_device *dev)
ee7b9f93 9681{
e7b903d2 9682 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93
JB		 9683 int i;
9684
7c74ade1 9685 dev_priv->num_shared_dpll = 2;
ee7b9f93 9686
e72f9fbf 9687 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
46edb027
DV		 9688 dev_priv->shared_dplls[i].id = i;
9689 dev_priv->shared_dplls[i].name = ibx_pch_dpll_names[i];
15bdd4cf 9690 dev_priv->shared_dplls[i].mode_set = ibx_pch_dpll_mode_set;
e7b903d2
DV		 9691 dev_priv->shared_dplls[i].enable = ibx_pch_dpll_enable;
9692 dev_priv->shared_dplls[i].disable = ibx_pch_dpll_disable;
5358901f
DV		 9693 dev_priv->shared_dplls[i].get_hw_state =
9694 ibx_pch_dpll_get_hw_state;
ee7b9f93
JB		 9695 }
9696}
9697
7c74ade1
DV		 9698static void intel_shared_dpll_init(struct drm_device *dev)
9699{
e7b903d2 9700 struct drm_i915_private *dev_priv = dev->dev_private;
7c74ade1
DV		 9701
9702 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9703 ibx_pch_dpll_init(dev);
9704 else
9705 dev_priv->num_shared_dpll = 0;
9706
9707 BUG_ON(dev_priv->num_shared_dpll > I915_NUM_PLLS);
9708 DRM_DEBUG_KMS("%i shared PLLs initialized\n",
9709 dev_priv->num_shared_dpll);
9710}
9711
b358d0a6 9712static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 9713{
22fd0fab 9714 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 9715 struct intel_crtc *intel_crtc;
9716 int i;
9717
955382f3 9718 intel_crtc = kzalloc(sizeof(*intel_crtc), GFP_KERNEL);
79e53945
JB		 9719 if (intel_crtc == NULL)
9720 return;
9721
9722 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
9723
9724 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 9725 for (i = 0; i < 256; i++) {
9726 intel_crtc->lut_r[i] = i;
9727 intel_crtc->lut_g[i] = i;
9728 intel_crtc->lut_b[i] = i;
9729 }
9730
80824003
JB		 9731 /* Swap pipes & planes for FBC on pre-965 */
9732 intel_crtc->pipe = pipe;
9733 intel_crtc->plane = pipe;
e2e767ab 9734 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 9735 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 9736 intel_crtc->plane = !pipe;
80824003
JB		 9737 }
9738
22fd0fab
JB		 9739 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
9740 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
9741 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
9742 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
9743
79e53945 9744 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 9745}
9746
08d7b3d1 9747int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 9748 struct drm_file *file)
08d7b3d1 9749{
08d7b3d1 9750 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 9751 struct drm_mode_object *drmmode_obj;
9752 struct intel_crtc *crtc;
08d7b3d1 9753
1cff8f6b
DV		 9754 if (!drm_core_check_feature(dev, DRIVER_MODESET))
9755 return -ENODEV;
08d7b3d1 9756
c05422d5
DV		 9757 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
9758 DRM_MODE_OBJECT_CRTC);
08d7b3d1 9759
c05422d5 9760 if (!drmmode_obj) {
08d7b3d1
CW		 9761 DRM_ERROR("no such CRTC id\n");
9762 return -EINVAL;
9763 }
9764
c05422d5
DV		 9765 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
9766 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 9767
c05422d5 9768 return 0;
08d7b3d1
CW		 9769}
9770
66a9278e 9771static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 9772{
66a9278e
DV		 9773 struct drm_device *dev = encoder->base.dev;
9774 struct intel_encoder *source_encoder;
79e53945 9775 int index_mask = 0;
79e53945
JB		 9776 int entry = 0;
9777
66a9278e
DV		 9778 list_for_each_entry(source_encoder,
9779 &dev->mode_config.encoder_list, base.head) {
9780
9781 if (encoder == source_encoder)
79e53945 9782 index_mask |= (1 << entry);
66a9278e
DV		 9783
9784 /* Intel hw has only one MUX where enocoders could be cloned. */
9785 if (encoder->cloneable && source_encoder->cloneable)
9786 index_mask |= (1 << entry);
9787
79e53945
JB		 9788 entry++;
9789 }
4ef69c7a 9790
79e53945
JB		 9791 return index_mask;
9792}
9793
4d302442
CW		 9794static bool has_edp_a(struct drm_device *dev)
9795{
9796 struct drm_i915_private *dev_priv = dev->dev_private;
9797
9798 if (!IS_MOBILE(dev))
9799 return false;
9800
9801 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
9802 return false;
9803
9804 if (IS_GEN5(dev) &&
9805 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
9806 return false;
9807
9808 return true;
9809}
9810
79e53945
JB		 9811static void intel_setup_outputs(struct drm_device *dev)
9812{
725e30ad 9813 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 9814 struct intel_encoder *encoder;
cb0953d7 9815 bool dpd_is_edp = false;
79e53945 9816
c9093354 9817 intel_lvds_init(dev);
79e53945 9818
c40c0f5b 9819 if (!IS_ULT(dev))
79935fca 9820 intel_crt_init(dev);
cb0953d7 9821
affa9354 9822 if (HAS_DDI(dev)) {
0e72a5b5
ED		 9823 int found;
9824
9825 /* Haswell uses DDI functions to detect digital outputs */
9826 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
9827 /* DDI A only supports eDP */
9828 if (found)
9829 intel_ddi_init(dev, PORT_A);
9830
9831 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
9832 * register */
9833 found = I915_READ(SFUSE_STRAP);
9834
9835 if (found & SFUSE_STRAP_DDIB_DETECTED)
9836 intel_ddi_init(dev, PORT_B);
9837 if (found & SFUSE_STRAP_DDIC_DETECTED)
9838 intel_ddi_init(dev, PORT_C);
9839 if (found & SFUSE_STRAP_DDID_DETECTED)
9840 intel_ddi_init(dev, PORT_D);
9841 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 9842 int found;
270b3042
DV		 9843 dpd_is_edp = intel_dpd_is_edp(dev);
9844
9845 if (has_edp_a(dev))
9846 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 9847
dc0fa718 9848 if (I915_READ(PCH_HDMIB) & SDVO_DETECTED) {
461ed3ca 9849 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 9850 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 9851 if (!found)
e2debe91 9852 intel_hdmi_init(dev, PCH_HDMIB, PORT_B);
5eb08b69 9853 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 9854 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 9855 }
9856
dc0fa718 9857 if (I915_READ(PCH_HDMIC) & SDVO_DETECTED)
e2debe91 9858 intel_hdmi_init(dev, PCH_HDMIC, PORT_C);
30ad48b7 9859
dc0fa718 9860 if (!dpd_is_edp && I915_READ(PCH_HDMID) & SDVO_DETECTED)
e2debe91 9861 intel_hdmi_init(dev, PCH_HDMID, PORT_D);
30ad48b7 9862
5eb08b69 9863 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 9864 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 9865
270b3042 9866 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 9867 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 9868 } else if (IS_VALLEYVIEW(dev)) {
19c03924 9869 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
6f6005a5
JB		 9870 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIC) & SDVO_DETECTED) {
9871 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIC,
9872 PORT_C);
9873 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
9874 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C,
9875 PORT_C);
9876 }
19c03924 9877
dc0fa718 9878 if (I915_READ(VLV_DISPLAY_BASE + GEN4_HDMIB) & SDVO_DETECTED) {
e2debe91
PZ		 9879 intel_hdmi_init(dev, VLV_DISPLAY_BASE + GEN4_HDMIB,
9880 PORT_B);
67cfc203
VS		 9881 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
9882 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d 9883 }
3cfca973
JN		 9884
9885 intel_dsi_init(dev);
103a196f 9886 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 9887 bool found = false;
7d57382e 9888
e2debe91 9889 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9890 DRM_DEBUG_KMS("probing SDVOB\n");
e2debe91 9891 found = intel_sdvo_init(dev, GEN3_SDVOB, true);
b01f2c3a
JB		 9892 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
9893 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
e2debe91 9894 intel_hdmi_init(dev, GEN4_HDMIB, PORT_B);
b01f2c3a 9895 }
27185ae1 9896
e7281eab 9897 if (!found && SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9898 intel_dp_init(dev, DP_B, PORT_B);
725e30ad 9899 }
13520b05
KH		 9900
9901 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 9902
e2debe91 9903 if (I915_READ(GEN3_SDVOB) & SDVO_DETECTED) {
b01f2c3a 9904 DRM_DEBUG_KMS("probing SDVOC\n");
e2debe91 9905 found = intel_sdvo_init(dev, GEN3_SDVOC, false);
b01f2c3a 9906 }
27185ae1 9907
e2debe91 9908 if (!found && (I915_READ(GEN3_SDVOC) & SDVO_DETECTED)) {
27185ae1 9909
b01f2c3a
JB		 9910 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
9911 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
e2debe91 9912 intel_hdmi_init(dev, GEN4_HDMIC, PORT_C);
b01f2c3a 9913 }
e7281eab 9914 if (SUPPORTS_INTEGRATED_DP(dev))
ab9d7c30 9915 intel_dp_init(dev, DP_C, PORT_C);
725e30ad 9916 }
27185ae1 9917
b01f2c3a 9918 if (SUPPORTS_INTEGRATED_DP(dev) &&
e7281eab 9919 (I915_READ(DP_D) & DP_DETECTED))
ab9d7c30 9920 intel_dp_init(dev, DP_D, PORT_D);
bad720ff 9921 } else if (IS_GEN2(dev))
79e53945
JB		 9922 intel_dvo_init(dev);
9923
103a196f 9924 if (SUPPORTS_TV(dev))
79e53945
JB		 9925 intel_tv_init(dev);
9926
4ef69c7a
CW		 9927 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
9928 encoder->base.possible_crtcs = encoder->crtc_mask;
9929 encoder->base.possible_clones =
66a9278e 9930 intel_encoder_clones(encoder);
79e53945 9931 }
47356eb6 9932
dde86e2d 9933 intel_init_pch_refclk(dev);
270b3042
DV		 9934
9935 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 9936}
9937
ddfe1567
CW		 9938void intel_framebuffer_fini(struct intel_framebuffer *fb)
9939{
9940 drm_framebuffer_cleanup(&fb->base);
9941 drm_gem_object_unreference_unlocked(&fb->obj->base);
9942}
9943
79e53945
JB		 9944static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
9945{
9946 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945 9947
ddfe1567 9948 intel_framebuffer_fini(intel_fb);
79e53945
JB		 9949 kfree(intel_fb);
9950}
9951
9952static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 9953 struct drm_file *file,
79e53945
JB		 9954 unsigned int *handle)
9955{
9956 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 9957 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 9958
05394f39 9959 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 9960}
9961
9962static const struct drm_framebuffer_funcs intel_fb_funcs = {
9963 .destroy = intel_user_framebuffer_destroy,
9964 .create_handle = intel_user_framebuffer_create_handle,
9965};
9966
38651674
DA		 9967int intel_framebuffer_init(struct drm_device *dev,
9968 struct intel_framebuffer *intel_fb,
308e5bcb 9969 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 9970 struct drm_i915_gem_object *obj)
79e53945 9971{
a35cdaa0 9972 int pitch_limit;
79e53945
JB		 9973 int ret;
9974
c16ed4be
CW		 9975 if (obj->tiling_mode == I915_TILING_Y) {
9976 DRM_DEBUG("hardware does not support tiling Y\n");
57cd6508 9977 return -EINVAL;
c16ed4be 9978 }
57cd6508 9979
c16ed4be
CW		 9980 if (mode_cmd->pitches[0] & 63) {
9981 DRM_DEBUG("pitch (%d) must be at least 64 byte aligned\n",
9982 mode_cmd->pitches[0]);
57cd6508 9983 return -EINVAL;
c16ed4be 9984 }
57cd6508 9985
a35cdaa0
CW		 9986 if (INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev)) {
9987 pitch_limit = 32*1024;
9988 } else if (INTEL_INFO(dev)->gen >= 4) {
9989 if (obj->tiling_mode)
9990 pitch_limit = 16*1024;
9991 else
9992 pitch_limit = 32*1024;
9993 } else if (INTEL_INFO(dev)->gen >= 3) {
9994 if (obj->tiling_mode)
9995 pitch_limit = 8*1024;
9996 else
9997 pitch_limit = 16*1024;
9998 } else
9999 /* XXX DSPC is limited to 4k tiled */
10000 pitch_limit = 8*1024;
10001
10002 if (mode_cmd->pitches[0] > pitch_limit) {
10003 DRM_DEBUG("%s pitch (%d) must be at less than %d\n",
10004 obj->tiling_mode ? "tiled" : "linear",
10005 mode_cmd->pitches[0], pitch_limit);
5d7bd705 10006 return -EINVAL;
c16ed4be 10007 }
5d7bd705
VS		 10008
10009 if (obj->tiling_mode != I915_TILING_NONE &&
c16ed4be
CW		 10010 mode_cmd->pitches[0] != obj->stride) {
10011 DRM_DEBUG("pitch (%d) must match tiling stride (%d)\n",
10012 mode_cmd->pitches[0], obj->stride);
5d7bd705 10013 return -EINVAL;
c16ed4be 10014 }
5d7bd705 10015
57779d06 10016 /* Reject formats not supported by any plane early. */
308e5bcb 10017 switch (mode_cmd->pixel_format) {
57779d06 10018 case DRM_FORMAT_C8:
04b3924d
VS		 10019 case DRM_FORMAT_RGB565:
10020 case DRM_FORMAT_XRGB8888:
10021 case DRM_FORMAT_ARGB8888:
57779d06
VS		 10022 break;
10023 case DRM_FORMAT_XRGB1555:
10024 case DRM_FORMAT_ARGB1555:
c16ed4be 10025 if (INTEL_INFO(dev)->gen > 3) {
4ee62c76
VS		 10026 DRM_DEBUG("unsupported pixel format: %s\n",
10027 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10028 return -EINVAL;
c16ed4be 10029 }
57779d06
VS		 10030 break;
10031 case DRM_FORMAT_XBGR8888:
10032 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 10033 case DRM_FORMAT_XRGB2101010:
10034 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 10035 case DRM_FORMAT_XBGR2101010:
10036 case DRM_FORMAT_ABGR2101010:
c16ed4be 10037 if (INTEL_INFO(dev)->gen < 4) {
4ee62c76
VS		 10038 DRM_DEBUG("unsupported pixel format: %s\n",
10039 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10040 return -EINVAL;
c16ed4be 10041 }
b5626747 10042 break;
04b3924d
VS		 10043 case DRM_FORMAT_YUYV:
10044 case DRM_FORMAT_UYVY:
10045 case DRM_FORMAT_YVYU:
10046 case DRM_FORMAT_VYUY:
c16ed4be 10047 if (INTEL_INFO(dev)->gen < 5) {
4ee62c76
VS		 10048 DRM_DEBUG("unsupported pixel format: %s\n",
10049 drm_get_format_name(mode_cmd->pixel_format));
57779d06 10050 return -EINVAL;
c16ed4be 10051 }
57cd6508
CW		 10052 break;
10053 default:
4ee62c76
VS		 10054 DRM_DEBUG("unsupported pixel format: %s\n",
10055 drm_get_format_name(mode_cmd->pixel_format));
57cd6508
CW		 10056 return -EINVAL;
10057 }
10058
90f9a336
VS		 10059 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
10060 if (mode_cmd->offsets[0] != 0)
10061 return -EINVAL;
10062
c7d73f6a
DV		 10063 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
10064 intel_fb->obj = obj;
10065
79e53945
JB		 10066 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
10067 if (ret) {
10068 DRM_ERROR("framebuffer init failed %d\n", ret);
10069 return ret;
10070 }
10071
79e53945
JB		 10072 return 0;
10073}
10074
79e53945
JB		 10075static struct drm_framebuffer *
10076intel_user_framebuffer_create(struct drm_device *dev,
10077 struct drm_file *filp,
308e5bcb 10078 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 10079{
05394f39 10080 struct drm_i915_gem_object *obj;
79e53945 10081
308e5bcb
JB		 10082 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
10083 mode_cmd->handles[0]));
c8725226 10084 if (&obj->base == NULL)
cce13ff7 10085 return ERR_PTR(-ENOENT);
79e53945 10086
d2dff872 10087 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 10088}
10089
79e53945 10090static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 10091 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 10092 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 10093};
10094
e70236a8
JB		 10095/* Set up chip specific display functions */
10096static void intel_init_display(struct drm_device *dev)
10097{
10098 struct drm_i915_private *dev_priv = dev->dev_private;
10099
ee9300bb
DV		 10100 if (HAS_PCH_SPLIT(dev) || IS_G4X(dev))
10101 dev_priv->display.find_dpll = g4x_find_best_dpll;
10102 else if (IS_VALLEYVIEW(dev))
10103 dev_priv->display.find_dpll = vlv_find_best_dpll;
10104 else if (IS_PINEVIEW(dev))
10105 dev_priv->display.find_dpll = pnv_find_best_dpll;
10106 else
10107 dev_priv->display.find_dpll = i9xx_find_best_dpll;
10108
affa9354 10109 if (HAS_DDI(dev)) {
0e8ffe1b 10110 dev_priv->display.get_pipe_config = haswell_get_pipe_config;
09b4ddf9 10111 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 10112 dev_priv->display.crtc_enable = haswell_crtc_enable;
10113 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 10114 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 10115 dev_priv->display.update_plane = ironlake_update_plane;
10116 } else if (HAS_PCH_SPLIT(dev)) {
0e8ffe1b 10117 dev_priv->display.get_pipe_config = ironlake_get_pipe_config;
f564048e 10118 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 10119 dev_priv->display.crtc_enable = ironlake_crtc_enable;
10120 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 10121 dev_priv->display.off = ironlake_crtc_off;
17638cd6 10122 dev_priv->display.update_plane = ironlake_update_plane;
89b667f8
JB		 10123 } else if (IS_VALLEYVIEW(dev)) {
10124 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
10125 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
10126 dev_priv->display.crtc_enable = valleyview_crtc_enable;
10127 dev_priv->display.crtc_disable = i9xx_crtc_disable;
10128 dev_priv->display.off = i9xx_crtc_off;
10129 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10130 } else {
0e8ffe1b 10131 dev_priv->display.get_pipe_config = i9xx_get_pipe_config;
f564048e 10132 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 10133 dev_priv->display.crtc_enable = i9xx_crtc_enable;
10134 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 10135 dev_priv->display.off = i9xx_crtc_off;
17638cd6 10136 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 10137 }
e70236a8 10138
e70236a8 10139 /* Returns the core display clock speed */
25eb05fc
JB		 10140 if (IS_VALLEYVIEW(dev))
10141 dev_priv->display.get_display_clock_speed =
10142 valleyview_get_display_clock_speed;
10143 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 10144 dev_priv->display.get_display_clock_speed =
10145 i945_get_display_clock_speed;
10146 else if (IS_I915G(dev))
10147 dev_priv->display.get_display_clock_speed =
10148 i915_get_display_clock_speed;
257a7ffc 10149 else if (IS_I945GM(dev) || IS_845G(dev))
e70236a8
JB		 10150 dev_priv->display.get_display_clock_speed =
10151 i9xx_misc_get_display_clock_speed;
257a7ffc
DV		 10152 else if (IS_PINEVIEW(dev))
10153 dev_priv->display.get_display_clock_speed =
10154 pnv_get_display_clock_speed;
e70236a8
JB		 10155 else if (IS_I915GM(dev))
10156 dev_priv->display.get_display_clock_speed =
10157 i915gm_get_display_clock_speed;
10158 else if (IS_I865G(dev))
10159 dev_priv->display.get_display_clock_speed =
10160 i865_get_display_clock_speed;
f0f8a9ce 10161 else if (IS_I85X(dev))
e70236a8
JB		 10162 dev_priv->display.get_display_clock_speed =
10163 i855_get_display_clock_speed;
10164 else /* 852, 830 */
10165 dev_priv->display.get_display_clock_speed =
10166 i830_get_display_clock_speed;
10167
7f8a8569 10168 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 10169 if (IS_GEN5(dev)) {
674cf967 10170 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 10171 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 10172 } else if (IS_GEN6(dev)) {
674cf967 10173 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 10174 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 10175 } else if (IS_IVYBRIDGE(dev)) {
10176 /* FIXME: detect B0+ stepping and use auto training */
10177 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 10178 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 10179 dev_priv->display.modeset_global_resources =
10180 ivb_modeset_global_resources;
c82e4d26
ED		 10181 } else if (IS_HASWELL(dev)) {
10182 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 10183 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 10184 dev_priv->display.modeset_global_resources =
10185 haswell_modeset_global_resources;
a0e63c22 10186 }
6067aaea 10187 } else if (IS_G4X(dev)) {
e0dac65e 10188 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 10189 }
8c9f3aaf
JB		 10190
10191 /* Default just returns -ENODEV to indicate unsupported */
10192 dev_priv->display.queue_flip = intel_default_queue_flip;
10193
10194 switch (INTEL_INFO(dev)->gen) {
10195 case 2:
10196 dev_priv->display.queue_flip = intel_gen2_queue_flip;
10197 break;
10198
10199 case 3:
10200 dev_priv->display.queue_flip = intel_gen3_queue_flip;
10201 break;
10202
10203 case 4:
10204 case 5:
10205 dev_priv->display.queue_flip = intel_gen4_queue_flip;
10206 break;
10207
10208 case 6:
10209 dev_priv->display.queue_flip = intel_gen6_queue_flip;
10210 break;
7c9017e5
JB		 10211 case 7:
10212 dev_priv->display.queue_flip = intel_gen7_queue_flip;
10213 break;
8c9f3aaf 10214 }
e70236a8
JB		 10215}
10216
b690e96c
JB		 10217/*
10218 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
10219 * resume, or other times. This quirk makes sure that's the case for
10220 * affected systems.
10221 */
0206e353 10222static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 10223{
10224 struct drm_i915_private *dev_priv = dev->dev_private;
10225
10226 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 10227 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 10228}
10229
435793df
KP		 10230/*
10231 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
10232 */
10233static void quirk_ssc_force_disable(struct drm_device *dev)
10234{
10235 struct drm_i915_private *dev_priv = dev->dev_private;
10236 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 10237 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 10238}
10239
4dca20ef 10240/*
5a15ab5b
CE		 10241 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
10242 * brightness value
4dca20ef
CE		 10243 */
10244static void quirk_invert_brightness(struct drm_device *dev)
10245{
10246 struct drm_i915_private *dev_priv = dev->dev_private;
10247 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 10248 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 10249}
10250
e85843be
KM		 10251/*
10252 * Some machines (Dell XPS13) suffer broken backlight controls if
10253 * BLM_PCH_PWM_ENABLE is set.
10254 */
10255static void quirk_no_pcm_pwm_enable(struct drm_device *dev)
10256{
10257 struct drm_i915_private *dev_priv = dev->dev_private;
10258 dev_priv->quirks |= QUIRK_NO_PCH_PWM_ENABLE;
10259 DRM_INFO("applying no-PCH_PWM_ENABLE quirk\n");
10260}
10261
b690e96c
JB		 10262struct intel_quirk {
10263 int device;
10264 int subsystem_vendor;
10265 int subsystem_device;
10266 void (*hook)(struct drm_device *dev);
10267};
10268
5f85f176
EE		 10269/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
10270struct intel_dmi_quirk {
10271 void (*hook)(struct drm_device *dev);
10272 const struct dmi_system_id (*dmi_id_list)[];
10273};
10274
10275static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
10276{
10277 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
10278 return 1;
10279}
10280
10281static const struct intel_dmi_quirk intel_dmi_quirks[] = {
10282 {
10283 .dmi_id_list = &(const struct dmi_system_id[]) {
10284 {
10285 .callback = intel_dmi_reverse_brightness,
10286 .ident = "NCR Corporation",
10287 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
10288 DMI_MATCH(DMI_PRODUCT_NAME, ""),
10289 },
10290 },
10291 { } /* terminating entry */
10292 },
10293 .hook = quirk_invert_brightness,
10294 },
10295};
10296
c43b5634 10297static struct intel_quirk intel_quirks[] = {
b690e96c 10298 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 10299 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 10300
b690e96c
JB		 10301 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
10302 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
10303
b690e96c
JB		 10304 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
10305 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
10306
ccd0d36e 10307 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 10308 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 10309 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 10310
10311 /* Lenovo U160 cannot use SSC on LVDS */
10312 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 10313
10314 /* Sony Vaio Y cannot use SSC on LVDS */
10315 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b 10316
ee1452d7
JN		 10317 /*
10318 * All GM45 Acer (and its brands eMachines and Packard Bell) laptops
10319 * seem to use inverted backlight PWM.
10320 */
10321 { 0x2a42, 0x1025, PCI_ANY_ID, quirk_invert_brightness },
e85843be
KM		 10322
10323 /* Dell XPS13 HD Sandy Bridge */
10324 { 0x0116, 0x1028, 0x052e, quirk_no_pcm_pwm_enable },
10325 /* Dell XPS13 HD and XPS13 FHD Ivy Bridge */
10326 { 0x0166, 0x1028, 0x058b, quirk_no_pcm_pwm_enable },
b690e96c
JB		 10327};
10328
10329static void intel_init_quirks(struct drm_device *dev)
10330{
10331 struct pci_dev *d = dev->pdev;
10332 int i;
10333
10334 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
10335 struct intel_quirk *q = &intel_quirks[i];
10336
10337 if (d->device == q->device &&
10338 (d->subsystem_vendor == q->subsystem_vendor ||
10339 q->subsystem_vendor == PCI_ANY_ID) &&
10340 (d->subsystem_device == q->subsystem_device ||
10341 q->subsystem_device == PCI_ANY_ID))
10342 q->hook(dev);
10343 }
5f85f176
EE		 10344 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
10345 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
10346 intel_dmi_quirks[i].hook(dev);
10347 }
b690e96c
JB		 10348}
10349
9cce37f4
JB		 10350/* Disable the VGA plane that we never use */
10351static void i915_disable_vga(struct drm_device *dev)
10352{
10353 struct drm_i915_private *dev_priv = dev->dev_private;
10354 u8 sr1;
766aa1c4 10355 u32 vga_reg = i915_vgacntrl_reg(dev);
9cce37f4
JB		 10356
10357 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 10358 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 10359 sr1 = inb(VGA_SR_DATA);
10360 outb(sr1 | 1<<5, VGA_SR_DATA);
10361 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10362 udelay(300);
10363
10364 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
10365 POSTING_READ(vga_reg);
10366}
10367
6e1b4fda 10368static void i915_enable_vga_mem(struct drm_device *dev)
81b5c7bc
AW		 10369{
10370 /* Enable VGA memory on Intel HD */
10371 if (HAS_PCH_SPLIT(dev)) {
10372 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10373 outb(inb(VGA_MSR_READ) | VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10374 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10375 VGA_RSRC_LEGACY_MEM |
10376 VGA_RSRC_NORMAL_IO |
10377 VGA_RSRC_NORMAL_MEM);
10378 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10379 }
10380}
10381
6e1b4fda
VS		 10382void i915_disable_vga_mem(struct drm_device *dev)
10383{
10384 /* Disable VGA memory on Intel HD */
10385 if (HAS_PCH_SPLIT(dev)) {
10386 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
10387 outb(inb(VGA_MSR_READ) & ~VGA_MSR_MEM_EN, VGA_MSR_WRITE);
10388 vga_set_legacy_decoding(dev->pdev, VGA_RSRC_LEGACY_IO |
10389 VGA_RSRC_NORMAL_IO |
10390 VGA_RSRC_NORMAL_MEM);
10391 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
10392 }
10393}
10394
f817586c
DV		 10395void intel_modeset_init_hw(struct drm_device *dev)
10396{
f6071166
JB		 10397 struct drm_i915_private *dev_priv = dev->dev_private;
10398
a8f78b58
ED		 10399 intel_prepare_ddi(dev);
10400
f817586c
DV		 10401 intel_init_clock_gating(dev);
10402
f6071166
JB		 10403 /* Enable the CRI clock source so we can get at the display */
10404 if (IS_VALLEYVIEW(dev))
10405 I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) |
10406 DPLL_INTEGRATED_CRI_CLK_VLV);
10407
40e9cf64
JB		 10408 intel_init_dpio(dev);
10409
79f5b2c7 10410 mutex_lock(&dev->struct_mutex);
8090c6b9 10411 intel_enable_gt_powersave(dev);
79f5b2c7 10412 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 10413}
10414
7d708ee4
ID		 10415void intel_modeset_suspend_hw(struct drm_device *dev)
10416{
10417 intel_suspend_hw(dev);
10418}
10419
79e53945
JB		 10420void intel_modeset_init(struct drm_device *dev)
10421{
652c393a 10422 struct drm_i915_private *dev_priv = dev->dev_private;
7f1f3851 10423 int i, j, ret;
79e53945
JB		 10424
10425 drm_mode_config_init(dev);
10426
10427 dev->mode_config.min_width = 0;
10428 dev->mode_config.min_height = 0;
10429
019d96cb
DA		 10430 dev->mode_config.preferred_depth = 24;
10431 dev->mode_config.prefer_shadow = 1;
10432
e6ecefaa 10433 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 10434
b690e96c
JB		 10435 intel_init_quirks(dev);
10436
1fa61106
ED		 10437 intel_init_pm(dev);
10438
e3c74757
BW		 10439 if (INTEL_INFO(dev)->num_pipes == 0)
10440 return;
10441
e70236a8
JB		 10442 intel_init_display(dev);
10443
a6c45cf0
CW		 10444 if (IS_GEN2(dev)) {
10445 dev->mode_config.max_width = 2048;
10446 dev->mode_config.max_height = 2048;
10447 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 10448 dev->mode_config.max_width = 4096;
10449 dev->mode_config.max_height = 4096;
79e53945 10450 } else {
a6c45cf0
CW		 10451 dev->mode_config.max_width = 8192;
10452 dev->mode_config.max_height = 8192;
79e53945 10453 }
5d4545ae 10454 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 10455
28c97730 10456 DRM_DEBUG_KMS("%d display pipe%s available.\n",
7eb552ae
BW		 10457 INTEL_INFO(dev)->num_pipes,
10458 INTEL_INFO(dev)->num_pipes > 1 ? "s" : "");
79e53945 10459
08e2a7de 10460 for_each_pipe(i) {
79e53945 10461 intel_crtc_init(dev, i);
7f1f3851
JB		 10462 for (j = 0; j < dev_priv->num_plane; j++) {
10463 ret = intel_plane_init(dev, i, j);
10464 if (ret)
06da8da2
VS		 10465 DRM_DEBUG_KMS("pipe %c sprite %c init failed: %d\n",
10466 pipe_name(i), sprite_name(i, j), ret);
7f1f3851 10467 }
79e53945
JB		 10468 }
10469
79f689aa 10470 intel_cpu_pll_init(dev);
e72f9fbf 10471 intel_shared_dpll_init(dev);
ee7b9f93 10472
9cce37f4
JB		 10473 /* Just disable it once at startup */
10474 i915_disable_vga(dev);
79e53945 10475 intel_setup_outputs(dev);
11be49eb
CW		 10476
10477 /* Just in case the BIOS is doing something questionable. */
10478 intel_disable_fbc(dev);
2c7111db
CW		 10479}
10480
24929352
DV		 10481static void
10482intel_connector_break_all_links(struct intel_connector *connector)
10483{
10484 connector->base.dpms = DRM_MODE_DPMS_OFF;
10485 connector->base.encoder = NULL;
10486 connector->encoder->connectors_active = false;
10487 connector->encoder->base.crtc = NULL;
10488}
10489
7fad798e
DV		 10490static void intel_enable_pipe_a(struct drm_device *dev)
10491{
10492 struct intel_connector *connector;
10493 struct drm_connector *crt = NULL;
10494 struct intel_load_detect_pipe load_detect_temp;
10495
10496 /* We can't just switch on the pipe A, we need to set things up with a
10497 * proper mode and output configuration. As a gross hack, enable pipe A
10498 * by enabling the load detect pipe once. */
10499 list_for_each_entry(connector,
10500 &dev->mode_config.connector_list,
10501 base.head) {
10502 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
10503 crt = &connector->base;
10504 break;
10505 }
10506 }
10507
10508 if (!crt)
10509 return;
10510
10511 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
10512 intel_release_load_detect_pipe(crt, &load_detect_temp);
10513
652c393a 10514
7fad798e
DV		 10515}
10516
fa555837
DV		 10517static bool
10518intel_check_plane_mapping(struct intel_crtc *crtc)
10519{
7eb552ae
BW		 10520 struct drm_device *dev = crtc->base.dev;
10521 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837
DV		 10522 u32 reg, val;
10523
7eb552ae 10524 if (INTEL_INFO(dev)->num_pipes == 1)
fa555837
DV		 10525 return true;
10526
10527 reg = DSPCNTR(!crtc->plane);
10528 val = I915_READ(reg);
10529
10530 if ((val & DISPLAY_PLANE_ENABLE) &&
10531 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
10532 return false;
10533
10534 return true;
10535}
10536
24929352
DV		 10537static void intel_sanitize_crtc(struct intel_crtc *crtc)
10538{
10539 struct drm_device *dev = crtc->base.dev;
10540 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 10541 u32 reg;
24929352 10542
24929352 10543 /* Clear any frame start delays used for debugging left by the BIOS */
3b117c8f 10544 reg = PIPECONF(crtc->config.cpu_transcoder);
24929352
DV		 10545 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
10546
10547 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 10548 * disable the crtc (and hence change the state) if it is wrong. Note
10549 * that gen4+ has a fixed plane -> pipe mapping. */
10550 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 10551 struct intel_connector *connector;
10552 bool plane;
10553
24929352
DV		 10554 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
10555 crtc->base.base.id);
10556
10557 /* Pipe has the wrong plane attached and the plane is active.
10558 * Temporarily change the plane mapping and disable everything
10559 * ... */
10560 plane = crtc->plane;
10561 crtc->plane = !plane;
10562 dev_priv->display.crtc_disable(&crtc->base);
10563 crtc->plane = plane;
10564
10565 /* ... and break all links. */
10566 list_for_each_entry(connector, &dev->mode_config.connector_list,
10567 base.head) {
10568 if (connector->encoder->base.crtc != &crtc->base)
10569 continue;
10570
10571 intel_connector_break_all_links(connector);
10572 }
10573
10574 WARN_ON(crtc->active);
10575 crtc->base.enabled = false;
10576 }
24929352 10577
7fad798e
DV		 10578 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
10579 crtc->pipe == PIPE_A && !crtc->active) {
10580 /* BIOS forgot to enable pipe A, this mostly happens after
10581 * resume. Force-enable the pipe to fix this, the update_dpms
10582 * call below we restore the pipe to the right state, but leave
10583 * the required bits on. */
10584 intel_enable_pipe_a(dev);
10585 }
10586
24929352
DV		 10587 /* Adjust the state of the output pipe according to whether we
10588 * have active connectors/encoders. */
10589 intel_crtc_update_dpms(&crtc->base);
10590
10591 if (crtc->active != crtc->base.enabled) {
10592 struct intel_encoder *encoder;
10593
10594 /* This can happen either due to bugs in the get_hw_state
10595 * functions or because the pipe is force-enabled due to the
10596 * pipe A quirk. */
10597 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
10598 crtc->base.base.id,
10599 crtc->base.enabled ? "enabled" : "disabled",
10600 crtc->active ? "enabled" : "disabled");
10601
10602 crtc->base.enabled = crtc->active;
10603
10604 /* Because we only establish the connector -> encoder ->
10605 * crtc links if something is active, this means the
10606 * crtc is now deactivated. Break the links. connector
10607 * -> encoder links are only establish when things are
10608 * actually up, hence no need to break them. */
10609 WARN_ON(crtc->active);
10610
10611 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
10612 WARN_ON(encoder->connectors_active);
10613 encoder->base.crtc = NULL;
10614 }
10615 }
10616}
10617
10618static void intel_sanitize_encoder(struct intel_encoder *encoder)
10619{
10620 struct intel_connector *connector;
10621 struct drm_device *dev = encoder->base.dev;
10622
10623 /* We need to check both for a crtc link (meaning that the
10624 * encoder is active and trying to read from a pipe) and the
10625 * pipe itself being active. */
10626 bool has_active_crtc = encoder->base.crtc &&
10627 to_intel_crtc(encoder->base.crtc)->active;
10628
10629 if (encoder->connectors_active && !has_active_crtc) {
10630 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
10631 encoder->base.base.id,
10632 drm_get_encoder_name(&encoder->base));
10633
10634 /* Connector is active, but has no active pipe. This is
10635 * fallout from our resume register restoring. Disable
10636 * the encoder manually again. */
10637 if (encoder->base.crtc) {
10638 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
10639 encoder->base.base.id,
10640 drm_get_encoder_name(&encoder->base));
10641 encoder->disable(encoder);
10642 }
10643
10644 /* Inconsistent output/port/pipe state happens presumably due to
10645 * a bug in one of the get_hw_state functions. Or someplace else
10646 * in our code, like the register restore mess on resume. Clamp
10647 * things to off as a safer default. */
10648 list_for_each_entry(connector,
10649 &dev->mode_config.connector_list,
10650 base.head) {
10651 if (connector->encoder != encoder)
10652 continue;
10653
10654 intel_connector_break_all_links(connector);
10655 }
10656 }
10657 /* Enabled encoders without active connectors will be fixed in
10658 * the crtc fixup. */
10659}
10660
44cec740 10661void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 10662{
10663 struct drm_i915_private *dev_priv = dev->dev_private;
766aa1c4 10664 u32 vga_reg = i915_vgacntrl_reg(dev);
0fde901f 10665
8dc8a27c
PZ		 10666 /* This function can be called both from intel_modeset_setup_hw_state or
10667 * at a very early point in our resume sequence, where the power well
10668 * structures are not yet restored. Since this function is at a very
10669 * paranoid "someone might have enabled VGA while we were not looking"
10670 * level, just check if the power well is enabled instead of trying to
10671 * follow the "don't touch the power well if we don't need it" policy
10672 * the rest of the driver uses. */
10673 if (HAS_POWER_WELL(dev) &&
6aedd1f5 10674 (I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_STATE_ENABLED) == 0)
8dc8a27c
PZ		 10675 return;
10676
0fde901f
KM		 10677 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
10678 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
209d5211 10679 i915_disable_vga(dev);
6e1b4fda 10680 i915_disable_vga_mem(dev);
0fde901f
KM		 10681 }
10682}
10683
30e984df 10684static void intel_modeset_readout_hw_state(struct drm_device *dev)
24929352
DV		 10685{
10686 struct drm_i915_private *dev_priv = dev->dev_private;
10687 enum pipe pipe;
24929352
DV		 10688 struct intel_crtc *crtc;
10689 struct intel_encoder *encoder;
10690 struct intel_connector *connector;
5358901f 10691 int i;
24929352 10692
0e8ffe1b
DV		 10693 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10694 base.head) {
88adfff1 10695 memset(&crtc->config, 0, sizeof(crtc->config));
3b117c8f 10696
0e8ffe1b
DV		 10697 crtc->active = dev_priv->display.get_pipe_config(crtc,
10698 &crtc->config);
24929352
DV		 10699
10700 crtc->base.enabled = crtc->active;
10701
10702 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
10703 crtc->base.base.id,
10704 crtc->active ? "enabled" : "disabled");
10705 }
10706
5358901f 10707 /* FIXME: Smash this into the new shared dpll infrastructure. */
affa9354 10708 if (HAS_DDI(dev))
6441ab5f
PZ		 10709 intel_ddi_setup_hw_pll_state(dev);
10710
5358901f
DV		 10711 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10712 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10713
10714 pll->on = pll->get_hw_state(dev_priv, pll, &pll->hw_state);
10715 pll->active = 0;
10716 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10717 base.head) {
10718 if (crtc->active && intel_crtc_to_shared_dpll(crtc) == pll)
10719 pll->active++;
10720 }
10721 pll->refcount = pll->active;
10722
35c95375
DV		 10723 DRM_DEBUG_KMS("%s hw state readout: refcount %i, on %i\n",
10724 pll->name, pll->refcount, pll->on);
5358901f
DV		 10725 }
10726
24929352
DV		 10727 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10728 base.head) {
10729 pipe = 0;
10730
10731 if (encoder->get_hw_state(encoder, &pipe)) {
045ac3b5
JB		 10732 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10733 encoder->base.crtc = &crtc->base;
510d5f2f 10734 if (encoder->get_config)
045ac3b5 10735 encoder->get_config(encoder, &crtc->config);
24929352
DV		 10736 } else {
10737 encoder->base.crtc = NULL;
10738 }
10739
10740 encoder->connectors_active = false;
10741 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
10742 encoder->base.base.id,
10743 drm_get_encoder_name(&encoder->base),
10744 encoder->base.crtc ? "enabled" : "disabled",
10745 pipe);
10746 }
10747
10748 list_for_each_entry(connector, &dev->mode_config.connector_list,
10749 base.head) {
10750 if (connector->get_hw_state(connector)) {
10751 connector->base.dpms = DRM_MODE_DPMS_ON;
10752 connector->encoder->connectors_active = true;
10753 connector->base.encoder = &connector->encoder->base;
10754 } else {
10755 connector->base.dpms = DRM_MODE_DPMS_OFF;
10756 connector->base.encoder = NULL;
10757 }
10758 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
10759 connector->base.base.id,
10760 drm_get_connector_name(&connector->base),
10761 connector->base.encoder ? "enabled" : "disabled");
10762 }
30e984df
DV		 10763}
10764
10765/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
10766 * and i915 state tracking structures. */
10767void intel_modeset_setup_hw_state(struct drm_device *dev,
10768 bool force_restore)
10769{
10770 struct drm_i915_private *dev_priv = dev->dev_private;
10771 enum pipe pipe;
30e984df
DV		 10772 struct intel_crtc *crtc;
10773 struct intel_encoder *encoder;
35c95375 10774 int i;
30e984df
DV		 10775
10776 intel_modeset_readout_hw_state(dev);
24929352 10777
babea61d
JB		 10778 /*
10779 * Now that we have the config, copy it to each CRTC struct
10780 * Note that this could go away if we move to using crtc_config
10781 * checking everywhere.
10782 */
10783 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
10784 base.head) {
10785 if (crtc->active && i915_fastboot) {
10786 intel_crtc_mode_from_pipe_config(crtc, &crtc->config);
10787
10788 DRM_DEBUG_KMS("[CRTC:%d] found active mode: ",
10789 crtc->base.base.id);
10790 drm_mode_debug_printmodeline(&crtc->base.mode);
10791 }
10792 }
10793
24929352
DV		 10794 /* HW state is read out, now we need to sanitize this mess. */
10795 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
10796 base.head) {
10797 intel_sanitize_encoder(encoder);
10798 }
10799
10800 for_each_pipe(pipe) {
10801 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
10802 intel_sanitize_crtc(crtc);
c0b03411 10803 intel_dump_pipe_config(crtc, &crtc->config, "[setup_hw_state]");
24929352 10804 }
9a935856 10805
35c95375
DV		 10806 for (i = 0; i < dev_priv->num_shared_dpll; i++) {
10807 struct intel_shared_dpll *pll = &dev_priv->shared_dplls[i];
10808
10809 if (!pll->on || pll->active)
10810 continue;
10811
10812 DRM_DEBUG_KMS("%s enabled but not in use, disabling\n", pll->name);
10813
10814 pll->disable(dev_priv, pll);
10815 pll->on = false;
10816 }
10817
45e2b5f6 10818 if (force_restore) {
7d0bc1ea
VS		 10819 i915_redisable_vga(dev);
10820
f30da187
DV		 10821 /*
10822 * We need to use raw interfaces for restoring state to avoid
10823 * checking (bogus) intermediate states.
10824 */
45e2b5f6 10825 for_each_pipe(pipe) {
b5644d05
JB		 10826 struct drm_crtc *crtc =
10827 dev_priv->pipe_to_crtc_mapping[pipe];
f30da187
DV		 10828
10829 __intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y,
10830 crtc->fb);
45e2b5f6
DV		 10831 }
10832 } else {
10833 intel_modeset_update_staged_output_state(dev);
10834 }
8af6cf88
DV		 10835
10836 intel_modeset_check_state(dev);
2e938892
DV		 10837
10838 drm_mode_config_reset(dev);
2c7111db
CW		 10839}
10840
10841void intel_modeset_gem_init(struct drm_device *dev)
10842{
1833b134 10843 intel_modeset_init_hw(dev);
02e792fb
DV		 10844
10845 intel_setup_overlay(dev);
24929352 10846
45e2b5f6 10847 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 10848}
10849
10850void intel_modeset_cleanup(struct drm_device *dev)
10851{
652c393a
JB		 10852 struct drm_i915_private *dev_priv = dev->dev_private;
10853 struct drm_crtc *crtc;
d9255d57 10854 struct drm_connector *connector;
652c393a 10855
fd0c0642
DV		 10856 /*
10857 * Interrupts and polling as the first thing to avoid creating havoc.
10858 * Too much stuff here (turning of rps, connectors, ...) would
10859 * experience fancy races otherwise.
10860 */
10861 drm_irq_uninstall(dev);
10862 cancel_work_sync(&dev_priv->hotplug_work);
10863 /*
10864 * Due to the hpd irq storm handling the hotplug work can re-arm the
10865 * poll handlers. Hence disable polling after hpd handling is shut down.
10866 */
f87ea761 10867 drm_kms_helper_poll_fini(dev);
fd0c0642 10868
652c393a
JB		 10869 mutex_lock(&dev->struct_mutex);
10870
723bfd70
JB		 10871 intel_unregister_dsm_handler();
10872
652c393a
JB		 10873 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
10874 /* Skip inactive CRTCs */
10875 if (!crtc->fb)
10876 continue;
10877
3dec0095 10878 intel_increase_pllclock(crtc);
652c393a
JB		 10879 }
10880
973d04f9 10881 intel_disable_fbc(dev);
e70236a8 10882
6e1b4fda 10883 i915_enable_vga_mem(dev);
81b5c7bc 10884
8090c6b9 10885 intel_disable_gt_powersave(dev);
0cdab21f 10886
930ebb46
DV		 10887 ironlake_teardown_rc6(dev);
10888
69341a5e
KH		 10889 mutex_unlock(&dev->struct_mutex);
10890
1630fe75
CW		 10891 /* flush any delayed tasks or pending work */
10892 flush_scheduled_work();
10893
dc652f90
JN		 10894 /* destroy backlight, if any, before the connectors */
10895 intel_panel_destroy_backlight(dev);
10896
d9255d57
PZ		 10897 /* destroy the sysfs files before encoders/connectors */
10898 list_for_each_entry(connector, &dev->mode_config.connector_list, head)
10899 drm_sysfs_connector_remove(connector);
10900
79e53945 10901 drm_mode_config_cleanup(dev);
4d7bb011
DV		 10902
10903 intel_cleanup_overlay(dev);
79e53945
JB		 10904}
10905
f1c79df3
ZW		 10906/*
10907 * Return which encoder is currently attached for connector.
10908 */
df0e9248 10909struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 10910{
df0e9248
CW		 10911 return &intel_attached_encoder(connector)->base;
10912}
f1c79df3 10913
df0e9248
CW		 10914void intel_connector_attach_encoder(struct intel_connector *connector,
10915 struct intel_encoder *encoder)
10916{
10917 connector->encoder = encoder;
10918 drm_mode_connector_attach_encoder(&connector->base,
10919 &encoder->base);
79e53945 10920}
28d52043
DA		 10921
10922/*
10923 * set vga decode state - true == enable VGA decode
10924 */
10925int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
10926{
10927 struct drm_i915_private *dev_priv = dev->dev_private;
10928 u16 gmch_ctrl;
10929
10930 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
10931 if (state)
10932 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
10933 else
10934 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
10935 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
10936 return 0;
10937}
c4a1d9e4 10938
c4a1d9e4 10939struct intel_display_error_state {
ff57f1b0
PZ		 10940
10941 u32 power_well_driver;
10942
63b66e5b
CW		 10943 int num_transcoders;
10944
c4a1d9e4
CW		 10945 struct intel_cursor_error_state {
10946 u32 control;
10947 u32 position;
10948 u32 base;
10949 u32 size;
52331309 10950 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 10951
10952 struct intel_pipe_error_state {
c4a1d9e4 10953 u32 source;
52331309 10954 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 10955
10956 struct intel_plane_error_state {
10957 u32 control;
10958 u32 stride;
10959 u32 size;
10960 u32 pos;
10961 u32 addr;
10962 u32 surface;
10963 u32 tile_offset;
52331309 10964 } plane[I915_MAX_PIPES];
63b66e5b
CW		 10965
10966 struct intel_transcoder_error_state {
10967 enum transcoder cpu_transcoder;
10968
10969 u32 conf;
10970
10971 u32 htotal;
10972 u32 hblank;
10973 u32 hsync;
10974 u32 vtotal;
10975 u32 vblank;
10976 u32 vsync;
10977 } transcoder[4];
c4a1d9e4
CW		 10978};
10979
10980struct intel_display_error_state *
10981intel_display_capture_error_state(struct drm_device *dev)
10982{
0206e353 10983 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 10984 struct intel_display_error_state *error;
63b66e5b
CW		 10985 int transcoders[] = {
10986 TRANSCODER_A,
10987 TRANSCODER_B,
10988 TRANSCODER_C,
10989 TRANSCODER_EDP,
10990 };
c4a1d9e4
CW		 10991 int i;
10992
63b66e5b
CW		 10993 if (INTEL_INFO(dev)->num_pipes == 0)
10994 return NULL;
10995
c4a1d9e4
CW		 10996 error = kmalloc(sizeof(*error), GFP_ATOMIC);
10997 if (error == NULL)
10998 return NULL;
10999
ff57f1b0
PZ		 11000 if (HAS_POWER_WELL(dev))
11001 error->power_well_driver = I915_READ(HSW_PWR_WELL_DRIVER);
11002
52331309 11003 for_each_pipe(i) {
a18c4c3d
PZ		 11004 if (INTEL_INFO(dev)->gen <= 6 || IS_VALLEYVIEW(dev)) {
11005 error->cursor[i].control = I915_READ(CURCNTR(i));
11006 error->cursor[i].position = I915_READ(CURPOS(i));
11007 error->cursor[i].base = I915_READ(CURBASE(i));
11008 } else {
11009 error->cursor[i].control = I915_READ(CURCNTR_IVB(i));
11010 error->cursor[i].position = I915_READ(CURPOS_IVB(i));
11011 error->cursor[i].base = I915_READ(CURBASE_IVB(i));
11012 }
c4a1d9e4
CW		 11013
11014 error->plane[i].control = I915_READ(DSPCNTR(i));
11015 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
80ca378b 11016 if (INTEL_INFO(dev)->gen <= 3) {
51889b35 11017 error->plane[i].size = I915_READ(DSPSIZE(i));
80ca378b
PZ		 11018 error->plane[i].pos = I915_READ(DSPPOS(i));
11019 }
ca291363
PZ		 11020 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
11021 error->plane[i].addr = I915_READ(DSPADDR(i));
c4a1d9e4
CW		 11022 if (INTEL_INFO(dev)->gen >= 4) {
11023 error->plane[i].surface = I915_READ(DSPSURF(i));
11024 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
11025 }
11026
c4a1d9e4 11027 error->pipe[i].source = I915_READ(PIPESRC(i));
63b66e5b
CW		 11028 }
11029
11030 error->num_transcoders = INTEL_INFO(dev)->num_pipes;
11031 if (HAS_DDI(dev_priv->dev))
11032 error->num_transcoders++; /* Account for eDP. */
11033
11034 for (i = 0; i < error->num_transcoders; i++) {
11035 enum transcoder cpu_transcoder = transcoders[i];
11036
11037 error->transcoder[i].cpu_transcoder = cpu_transcoder;
11038
11039 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
11040 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
11041 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
11042 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
11043 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
11044 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
11045 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 11046 }
11047
12d217c7
PZ		 11048 /* In the code above we read the registers without checking if the power
11049 * well was on, so here we have to clear the FPGA_DBG_RM_NOCLAIM bit to
11050 * prevent the next I915_WRITE from detecting it and printing an error
11051 * message. */
907b28c5 11052 intel_uncore_clear_errors(dev);
12d217c7 11053
c4a1d9e4
CW		 11054 return error;
11055}
11056
edc3d884
MK		 11057#define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
11058
c4a1d9e4 11059void
edc3d884 11060intel_display_print_error_state(struct drm_i915_error_state_buf *m,
c4a1d9e4
CW		 11061 struct drm_device *dev,
11062 struct intel_display_error_state *error)
11063{
11064 int i;
11065
63b66e5b
CW		 11066 if (!error)
11067 return;
11068
edc3d884 11069 err_printf(m, "Num Pipes: %d\n", INTEL_INFO(dev)->num_pipes);
ff57f1b0 11070 if (HAS_POWER_WELL(dev))
edc3d884 11071 err_printf(m, "PWR_WELL_CTL2: %08x\n",
ff57f1b0 11072 error->power_well_driver);
52331309 11073 for_each_pipe(i) {
edc3d884 11074 err_printf(m, "Pipe [%d]:\n", i);
edc3d884 11075 err_printf(m, " SRC: %08x\n", error->pipe[i].source);
edc3d884
MK		 11076
11077 err_printf(m, "Plane [%d]:\n", i);
11078 err_printf(m, " CNTR: %08x\n", error->plane[i].control);
11079 err_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
80ca378b 11080 if (INTEL_INFO(dev)->gen <= 3) {
edc3d884
MK		 11081 err_printf(m, " SIZE: %08x\n", error->plane[i].size);
11082 err_printf(m, " POS: %08x\n", error->plane[i].pos);
80ca378b 11083 }
4b71a570 11084 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
edc3d884 11085 err_printf(m, " ADDR: %08x\n", error->plane[i].addr);
c4a1d9e4 11086 if (INTEL_INFO(dev)->gen >= 4) {
edc3d884
MK		 11087 err_printf(m, " SURF: %08x\n", error->plane[i].surface);
11088 err_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
c4a1d9e4
CW		 11089 }
11090
edc3d884
MK		 11091 err_printf(m, "Cursor [%d]:\n", i);
11092 err_printf(m, " CNTR: %08x\n", error->cursor[i].control);
11093 err_printf(m, " POS: %08x\n", error->cursor[i].position);
11094 err_printf(m, " BASE: %08x\n", error->cursor[i].base);
c4a1d9e4 11095 }
63b66e5b
CW		 11096
11097 for (i = 0; i < error->num_transcoders; i++) {
11098 err_printf(m, " CPU transcoder: %c\n",
11099 transcoder_name(error->transcoder[i].cpu_transcoder));
11100 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
11101 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
11102 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
11103 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
11104 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
11105 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
11106 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
11107 }
c4a1d9e4 11108}
Linux kernel - Deliverables
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