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drm/i915: gen6_gmch_remove can be static
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
760285e7 35#include <drm/drmP.h>
79e53945 36#include "intel_drv.h"
760285e7 37#include <drm/i915_drm.h>
79e53945 38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
760285e7
DH		 40#include <drm/drm_dp_helper.h>
41#include <drm/drm_crtc_helper.h>
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
0206e353 44bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 45static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 46static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 47
48typedef struct {
0206e353
AJ		 49 /* given values */
50 int n;
51 int m1, m2;
52 int p1, p2;
53 /* derived values */
54 int dot;
55 int vco;
56 int m;
57 int p;
79e53945
JB		 58} intel_clock_t;
59
60typedef struct {
0206e353 61 int min, max;
79e53945
JB		 62} intel_range_t;
63
64typedef struct {
0206e353
AJ		 65 int dot_limit;
66 int p2_slow, p2_fast;
79e53945
JB		 67} intel_p2_t;
68
69#define INTEL_P2_NUM 2
d4906093
ML		 70typedef struct intel_limit intel_limit_t;
71struct intel_limit {
0206e353
AJ		 72 intel_range_t dot, vco, n, m, m1, m2, p, p1;
73 intel_p2_t p2;
74 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 75 int, int, intel_clock_t *, intel_clock_t *);
d4906093 76};
79e53945 77
2377b741
JB		 78/* FDI */
79#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
80
d2acd215
DV		 81int
82intel_pch_rawclk(struct drm_device *dev)
83{
84 struct drm_i915_private *dev_priv = dev->dev_private;
85
86 WARN_ON(!HAS_PCH_SPLIT(dev));
87
88 return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
89}
90
d4906093
ML		 91static bool
92intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 93 int target, int refclk, intel_clock_t *match_clock,
94 intel_clock_t *best_clock);
d4906093
ML		 95static bool
96intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 97 int target, int refclk, intel_clock_t *match_clock,
98 intel_clock_t *best_clock);
79e53945 99
a4fc5ed6
KP		 100static bool
101intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 102 int target, int refclk, intel_clock_t *match_clock,
103 intel_clock_t *best_clock);
5eb08b69 104static bool
f2b115e6 105intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 106 int target, int refclk, intel_clock_t *match_clock,
107 intel_clock_t *best_clock);
a4fc5ed6 108
a0c4da24
JB		 109static bool
110intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
111 int target, int refclk, intel_clock_t *match_clock,
112 intel_clock_t *best_clock);
113
021357ac
CW		 114static inline u32 /* units of 100MHz */
115intel_fdi_link_freq(struct drm_device *dev)
116{
8b99e68c
CW		 117 if (IS_GEN5(dev)) {
118 struct drm_i915_private *dev_priv = dev->dev_private;
119 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
120 } else
121 return 27;
021357ac
CW		 122}
123
e4b36699 124static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 125 .dot = { .min = 25000, .max = 350000 },
126 .vco = { .min = 930000, .max = 1400000 },
127 .n = { .min = 3, .max = 16 },
128 .m = { .min = 96, .max = 140 },
129 .m1 = { .min = 18, .max = 26 },
130 .m2 = { .min = 6, .max = 16 },
131 .p = { .min = 4, .max = 128 },
132 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 133 .p2 = { .dot_limit = 165000,
134 .p2_slow = 4, .p2_fast = 2 },
d4906093 135 .find_pll = intel_find_best_PLL,
e4b36699
KP		 136};
137
138static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 139 .dot = { .min = 25000, .max = 350000 },
140 .vco = { .min = 930000, .max = 1400000 },
141 .n = { .min = 3, .max = 16 },
142 .m = { .min = 96, .max = 140 },
143 .m1 = { .min = 18, .max = 26 },
144 .m2 = { .min = 6, .max = 16 },
145 .p = { .min = 4, .max = 128 },
146 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 147 .p2 = { .dot_limit = 165000,
148 .p2_slow = 14, .p2_fast = 7 },
d4906093 149 .find_pll = intel_find_best_PLL,
e4b36699 150};
273e27ca 151
e4b36699 152static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 153 .dot = { .min = 20000, .max = 400000 },
154 .vco = { .min = 1400000, .max = 2800000 },
155 .n = { .min = 1, .max = 6 },
156 .m = { .min = 70, .max = 120 },
157 .m1 = { .min = 10, .max = 22 },
158 .m2 = { .min = 5, .max = 9 },
159 .p = { .min = 5, .max = 80 },
160 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 161 .p2 = { .dot_limit = 200000,
162 .p2_slow = 10, .p2_fast = 5 },
d4906093 163 .find_pll = intel_find_best_PLL,
e4b36699
KP		 164};
165
166static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 167 .dot = { .min = 20000, .max = 400000 },
168 .vco = { .min = 1400000, .max = 2800000 },
169 .n = { .min = 1, .max = 6 },
170 .m = { .min = 70, .max = 120 },
171 .m1 = { .min = 10, .max = 22 },
172 .m2 = { .min = 5, .max = 9 },
173 .p = { .min = 7, .max = 98 },
174 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 175 .p2 = { .dot_limit = 112000,
176 .p2_slow = 14, .p2_fast = 7 },
d4906093 177 .find_pll = intel_find_best_PLL,
e4b36699
KP		 178};
179
273e27ca 180
e4b36699 181static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 182 .dot = { .min = 25000, .max = 270000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 17, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 10, .max = 30 },
189 .p1 = { .min = 1, .max = 3},
190 .p2 = { .dot_limit = 270000,
191 .p2_slow = 10,
192 .p2_fast = 10
044c7c41 193 },
d4906093 194 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 195};
196
197static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 198 .dot = { .min = 22000, .max = 400000 },
199 .vco = { .min = 1750000, .max = 3500000},
200 .n = { .min = 1, .max = 4 },
201 .m = { .min = 104, .max = 138 },
202 .m1 = { .min = 16, .max = 23 },
203 .m2 = { .min = 5, .max = 11 },
204 .p = { .min = 5, .max = 80 },
205 .p1 = { .min = 1, .max = 8},
206 .p2 = { .dot_limit = 165000,
207 .p2_slow = 10, .p2_fast = 5 },
d4906093 208 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 209};
210
211static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 212 .dot = { .min = 20000, .max = 115000 },
213 .vco = { .min = 1750000, .max = 3500000 },
214 .n = { .min = 1, .max = 3 },
215 .m = { .min = 104, .max = 138 },
216 .m1 = { .min = 17, .max = 23 },
217 .m2 = { .min = 5, .max = 11 },
218 .p = { .min = 28, .max = 112 },
219 .p1 = { .min = 2, .max = 8 },
220 .p2 = { .dot_limit = 0,
221 .p2_slow = 14, .p2_fast = 14
044c7c41 222 },
d4906093 223 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 224};
225
226static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 227 .dot = { .min = 80000, .max = 224000 },
228 .vco = { .min = 1750000, .max = 3500000 },
229 .n = { .min = 1, .max = 3 },
230 .m = { .min = 104, .max = 138 },
231 .m1 = { .min = 17, .max = 23 },
232 .m2 = { .min = 5, .max = 11 },
233 .p = { .min = 14, .max = 42 },
234 .p1 = { .min = 2, .max = 6 },
235 .p2 = { .dot_limit = 0,
236 .p2_slow = 7, .p2_fast = 7
044c7c41 237 },
d4906093 238 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 239};
240
241static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 242 .dot = { .min = 161670, .max = 227000 },
243 .vco = { .min = 1750000, .max = 3500000},
244 .n = { .min = 1, .max = 2 },
245 .m = { .min = 97, .max = 108 },
246 .m1 = { .min = 0x10, .max = 0x12 },
247 .m2 = { .min = 0x05, .max = 0x06 },
248 .p = { .min = 10, .max = 20 },
249 .p1 = { .min = 1, .max = 2},
250 .p2 = { .dot_limit = 0,
273e27ca 251 .p2_slow = 10, .p2_fast = 10 },
0206e353 252 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 253};
254
f2b115e6 255static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 256 .dot = { .min = 20000, .max = 400000},
257 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 258 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 259 .n = { .min = 3, .max = 6 },
260 .m = { .min = 2, .max = 256 },
273e27ca 261 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 262 .m1 = { .min = 0, .max = 0 },
263 .m2 = { .min = 0, .max = 254 },
264 .p = { .min = 5, .max = 80 },
265 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 266 .p2 = { .dot_limit = 200000,
267 .p2_slow = 10, .p2_fast = 5 },
6115707b 268 .find_pll = intel_find_best_PLL,
e4b36699
KP		 269};
270
f2b115e6 271static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 272 .dot = { .min = 20000, .max = 400000 },
273 .vco = { .min = 1700000, .max = 3500000 },
274 .n = { .min = 3, .max = 6 },
275 .m = { .min = 2, .max = 256 },
276 .m1 = { .min = 0, .max = 0 },
277 .m2 = { .min = 0, .max = 254 },
278 .p = { .min = 7, .max = 112 },
279 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 280 .p2 = { .dot_limit = 112000,
281 .p2_slow = 14, .p2_fast = 14 },
6115707b 282 .find_pll = intel_find_best_PLL,
e4b36699
KP		 283};
284
273e27ca
EA		 285/* Ironlake / Sandybridge
286 *
287 * We calculate clock using (register_value + 2) for N/M1/M2, so here
288 * the range value for them is (actual_value - 2).
289 */
b91ad0ec 290static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 291 .dot = { .min = 25000, .max = 350000 },
292 .vco = { .min = 1760000, .max = 3510000 },
293 .n = { .min = 1, .max = 5 },
294 .m = { .min = 79, .max = 127 },
295 .m1 = { .min = 12, .max = 22 },
296 .m2 = { .min = 5, .max = 9 },
297 .p = { .min = 5, .max = 80 },
298 .p1 = { .min = 1, .max = 8 },
299 .p2 = { .dot_limit = 225000,
300 .p2_slow = 10, .p2_fast = 5 },
4547668a 301 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 302};
303
b91ad0ec 304static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 305 .dot = { .min = 25000, .max = 350000 },
306 .vco = { .min = 1760000, .max = 3510000 },
307 .n = { .min = 1, .max = 3 },
308 .m = { .min = 79, .max = 118 },
309 .m1 = { .min = 12, .max = 22 },
310 .m2 = { .min = 5, .max = 9 },
311 .p = { .min = 28, .max = 112 },
312 .p1 = { .min = 2, .max = 8 },
313 .p2 = { .dot_limit = 225000,
314 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 315 .find_pll = intel_g4x_find_best_PLL,
316};
317
318static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 319 .dot = { .min = 25000, .max = 350000 },
320 .vco = { .min = 1760000, .max = 3510000 },
321 .n = { .min = 1, .max = 3 },
322 .m = { .min = 79, .max = 127 },
323 .m1 = { .min = 12, .max = 22 },
324 .m2 = { .min = 5, .max = 9 },
325 .p = { .min = 14, .max = 56 },
326 .p1 = { .min = 2, .max = 8 },
327 .p2 = { .dot_limit = 225000,
328 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 329 .find_pll = intel_g4x_find_best_PLL,
330};
331
273e27ca 332/* LVDS 100mhz refclk limits. */
b91ad0ec 333static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 334 .dot = { .min = 25000, .max = 350000 },
335 .vco = { .min = 1760000, .max = 3510000 },
336 .n = { .min = 1, .max = 2 },
337 .m = { .min = 79, .max = 126 },
338 .m1 = { .min = 12, .max = 22 },
339 .m2 = { .min = 5, .max = 9 },
340 .p = { .min = 28, .max = 112 },
0206e353 341 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 342 .p2 = { .dot_limit = 225000,
343 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 344 .find_pll = intel_g4x_find_best_PLL,
345};
346
347static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 348 .dot = { .min = 25000, .max = 350000 },
349 .vco = { .min = 1760000, .max = 3510000 },
350 .n = { .min = 1, .max = 3 },
351 .m = { .min = 79, .max = 126 },
352 .m1 = { .min = 12, .max = 22 },
353 .m2 = { .min = 5, .max = 9 },
354 .p = { .min = 14, .max = 42 },
0206e353 355 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 356 .p2 = { .dot_limit = 225000,
357 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 358 .find_pll = intel_g4x_find_best_PLL,
359};
360
361static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 362 .dot = { .min = 25000, .max = 350000 },
363 .vco = { .min = 1760000, .max = 3510000},
364 .n = { .min = 1, .max = 2 },
365 .m = { .min = 81, .max = 90 },
366 .m1 = { .min = 12, .max = 22 },
367 .m2 = { .min = 5, .max = 9 },
368 .p = { .min = 10, .max = 20 },
369 .p1 = { .min = 1, .max = 2},
370 .p2 = { .dot_limit = 0,
273e27ca 371 .p2_slow = 10, .p2_fast = 10 },
0206e353 372 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 373};
374
a0c4da24
JB		 375static const intel_limit_t intel_limits_vlv_dac = {
376 .dot = { .min = 25000, .max = 270000 },
377 .vco = { .min = 4000000, .max = 6000000 },
378 .n = { .min = 1, .max = 7 },
379 .m = { .min = 22, .max = 450 }, /* guess */
380 .m1 = { .min = 2, .max = 3 },
381 .m2 = { .min = 11, .max = 156 },
382 .p = { .min = 10, .max = 30 },
383 .p1 = { .min = 2, .max = 3 },
384 .p2 = { .dot_limit = 270000,
385 .p2_slow = 2, .p2_fast = 20 },
386 .find_pll = intel_vlv_find_best_pll,
387};
388
389static const intel_limit_t intel_limits_vlv_hdmi = {
390 .dot = { .min = 20000, .max = 165000 },
17dc9257 391 .vco = { .min = 4000000, .max = 5994000},
a0c4da24
JB		 392 .n = { .min = 1, .max = 7 },
393 .m = { .min = 60, .max = 300 }, /* guess */
394 .m1 = { .min = 2, .max = 3 },
395 .m2 = { .min = 11, .max = 156 },
396 .p = { .min = 10, .max = 30 },
397 .p1 = { .min = 2, .max = 3 },
398 .p2 = { .dot_limit = 270000,
399 .p2_slow = 2, .p2_fast = 20 },
400 .find_pll = intel_vlv_find_best_pll,
401};
402
403static const intel_limit_t intel_limits_vlv_dp = {
74a4dd2e
VP		 404 .dot = { .min = 25000, .max = 270000 },
405 .vco = { .min = 4000000, .max = 6000000 },
a0c4da24 406 .n = { .min = 1, .max = 7 },
74a4dd2e 407 .m = { .min = 22, .max = 450 },
a0c4da24
JB		 408 .m1 = { .min = 2, .max = 3 },
409 .m2 = { .min = 11, .max = 156 },
410 .p = { .min = 10, .max = 30 },
411 .p1 = { .min = 2, .max = 3 },
412 .p2 = { .dot_limit = 270000,
413 .p2_slow = 2, .p2_fast = 20 },
414 .find_pll = intel_vlv_find_best_pll,
415};
416
57f350b6
JB		 417u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
418{
09153000 419 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
57f350b6 420
57f350b6
JB		 421 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
422 DRM_ERROR("DPIO idle wait timed out\n");
09153000 423 return 0;
57f350b6
JB		 424 }
425
426 I915_WRITE(DPIO_REG, reg);
427 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
428 DPIO_BYTE);
429 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
430 DRM_ERROR("DPIO read wait timed out\n");
09153000 431 return 0;
57f350b6 432 }
57f350b6 433
09153000 434 return I915_READ(DPIO_DATA);
57f350b6
JB		 435}
436
a0c4da24
JB		 437static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
438 u32 val)
439{
09153000 440 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a0c4da24 441
a0c4da24
JB		 442 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
443 DRM_ERROR("DPIO idle wait timed out\n");
09153000 444 return;
a0c4da24
JB		 445 }
446
447 I915_WRITE(DPIO_DATA, val);
448 I915_WRITE(DPIO_REG, reg);
449 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
450 DPIO_BYTE);
451 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
452 DRM_ERROR("DPIO write wait timed out\n");
a0c4da24
JB		 453}
454
57f350b6
JB		 455static void vlv_init_dpio(struct drm_device *dev)
456{
457 struct drm_i915_private *dev_priv = dev->dev_private;
458
459 /* Reset the DPIO config */
460 I915_WRITE(DPIO_CTL, 0);
461 POSTING_READ(DPIO_CTL);
462 I915_WRITE(DPIO_CTL, 1);
463 POSTING_READ(DPIO_CTL);
464}
465
1b894b59
CW		 466static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
467 int refclk)
2c07245f 468{
b91ad0ec 469 struct drm_device *dev = crtc->dev;
2c07245f 470 const intel_limit_t *limit;
b91ad0ec
ZW		 471
472 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 473 if (intel_is_dual_link_lvds(dev)) {
b91ad0ec 474 /* LVDS dual channel */
1b894b59 475 if (refclk == 100000)
b91ad0ec
ZW		 476 limit = &intel_limits_ironlake_dual_lvds_100m;
477 else
478 limit = &intel_limits_ironlake_dual_lvds;
479 } else {
1b894b59 480 if (refclk == 100000)
b91ad0ec
ZW		 481 limit = &intel_limits_ironlake_single_lvds_100m;
482 else
483 limit = &intel_limits_ironlake_single_lvds;
484 }
485 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
547dc041 486 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
4547668a 487 limit = &intel_limits_ironlake_display_port;
2c07245f 488 else
b91ad0ec 489 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 490
491 return limit;
492}
493
044c7c41
ML		 494static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
495{
496 struct drm_device *dev = crtc->dev;
044c7c41
ML		 497 const intel_limit_t *limit;
498
499 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1974cad0 500 if (intel_is_dual_link_lvds(dev))
044c7c41 501 /* LVDS with dual channel */
e4b36699 502 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 503 else
504 /* LVDS with dual channel */
e4b36699 505 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 506 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
507 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 508 limit = &intel_limits_g4x_hdmi;
044c7c41 509 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 510 limit = &intel_limits_g4x_sdvo;
0206e353 511 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 512 limit = &intel_limits_g4x_display_port;
044c7c41 513 } else /* The option is for other outputs */
e4b36699 514 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 515
516 return limit;
517}
518
1b894b59 519static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 520{
521 struct drm_device *dev = crtc->dev;
522 const intel_limit_t *limit;
523
bad720ff 524 if (HAS_PCH_SPLIT(dev))
1b894b59 525 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 526 else if (IS_G4X(dev)) {
044c7c41 527 limit = intel_g4x_limit(crtc);
f2b115e6 528 } else if (IS_PINEVIEW(dev)) {
2177832f 529 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 530 limit = &intel_limits_pineview_lvds;
2177832f 531 else
f2b115e6 532 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 533 } else if (IS_VALLEYVIEW(dev)) {
534 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
535 limit = &intel_limits_vlv_dac;
536 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
537 limit = &intel_limits_vlv_hdmi;
538 else
539 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 540 } else if (!IS_GEN2(dev)) {
541 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
542 limit = &intel_limits_i9xx_lvds;
543 else
544 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 545 } else {
546 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 547 limit = &intel_limits_i8xx_lvds;
79e53945 548 else
e4b36699 549 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 550 }
551 return limit;
552}
553
f2b115e6
AJ		 554/* m1 is reserved as 0 in Pineview, n is a ring counter */
555static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 556{
2177832f
SL		 557 clock->m = clock->m2 + 2;
558 clock->p = clock->p1 * clock->p2;
559 clock->vco = refclk * clock->m / clock->n;
560 clock->dot = clock->vco / clock->p;
561}
562
563static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
564{
f2b115e6
AJ		 565 if (IS_PINEVIEW(dev)) {
566 pineview_clock(refclk, clock);
2177832f
SL		 567 return;
568 }
79e53945
JB		 569 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
570 clock->p = clock->p1 * clock->p2;
571 clock->vco = refclk * clock->m / (clock->n + 2);
572 clock->dot = clock->vco / clock->p;
573}
574
79e53945
JB		 575/**
576 * Returns whether any output on the specified pipe is of the specified type
577 */
4ef69c7a 578bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 579{
4ef69c7a 580 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 581 struct intel_encoder *encoder;
582
6c2b7c12
DV		 583 for_each_encoder_on_crtc(dev, crtc, encoder)
584 if (encoder->type == type)
4ef69c7a
CW		 585 return true;
586
587 return false;
79e53945
JB		 588}
589
7c04d1d9 590#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 591/**
592 * Returns whether the given set of divisors are valid for a given refclk with
593 * the given connectors.
594 */
595
1b894b59
CW		 596static bool intel_PLL_is_valid(struct drm_device *dev,
597 const intel_limit_t *limit,
598 const intel_clock_t *clock)
79e53945 599{
79e53945 600 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 601 INTELPllInvalid("p1 out of range\n");
79e53945 602 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 603 INTELPllInvalid("p out of range\n");
79e53945 604 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 605 INTELPllInvalid("m2 out of range\n");
79e53945 606 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 607 INTELPllInvalid("m1 out of range\n");
f2b115e6 608 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 609 INTELPllInvalid("m1 <= m2\n");
79e53945 610 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 611 INTELPllInvalid("m out of range\n");
79e53945 612 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 613 INTELPllInvalid("n out of range\n");
79e53945 614 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 615 INTELPllInvalid("vco out of range\n");
79e53945
JB		 616 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
617 * connector, etc., rather than just a single range.
618 */
619 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 620 INTELPllInvalid("dot out of range\n");
79e53945
JB		 621
622 return true;
623}
624
d4906093
ML		 625static bool
626intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 627 int target, int refclk, intel_clock_t *match_clock,
628 intel_clock_t *best_clock)
d4906093 629
79e53945
JB		 630{
631 struct drm_device *dev = crtc->dev;
79e53945 632 intel_clock_t clock;
79e53945
JB		 633 int err = target;
634
a210b028 635 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
79e53945 636 /*
a210b028
DV		 637 * For LVDS just rely on its current settings for dual-channel.
638 * We haven't figured out how to reliably set up different
639 * single/dual channel state, if we even can.
79e53945 640 */
1974cad0 641 if (intel_is_dual_link_lvds(dev))
79e53945
JB		 642 clock.p2 = limit->p2.p2_fast;
643 else
644 clock.p2 = limit->p2.p2_slow;
645 } else {
646 if (target < limit->p2.dot_limit)
647 clock.p2 = limit->p2.p2_slow;
648 else
649 clock.p2 = limit->p2.p2_fast;
650 }
651
0206e353 652 memset(best_clock, 0, sizeof(*best_clock));
79e53945 653
42158660
ZY		 654 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
655 clock.m1++) {
656 for (clock.m2 = limit->m2.min;
657 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 658 /* m1 is always 0 in Pineview */
659 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 660 break;
661 for (clock.n = limit->n.min;
662 clock.n <= limit->n.max; clock.n++) {
663 for (clock.p1 = limit->p1.min;
664 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 665 int this_err;
666
2177832f 667 intel_clock(dev, refclk, &clock);
1b894b59
CW		 668 if (!intel_PLL_is_valid(dev, limit,
669 &clock))
79e53945 670 continue;
cec2f356
SP		 671 if (match_clock &&
672 clock.p != match_clock->p)
673 continue;
79e53945
JB		 674
675 this_err = abs(clock.dot - target);
676 if (this_err < err) {
677 *best_clock = clock;
678 err = this_err;
679 }
680 }
681 }
682 }
683 }
684
685 return (err != target);
686}
687
d4906093
ML		 688static bool
689intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 690 int target, int refclk, intel_clock_t *match_clock,
691 intel_clock_t *best_clock)
d4906093
ML		 692{
693 struct drm_device *dev = crtc->dev;
d4906093
ML		 694 intel_clock_t clock;
695 int max_n;
696 bool found;
6ba770dc
AJ		 697 /* approximately equals target * 0.00585 */
698 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 699 found = false;
700
701 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 702 int lvds_reg;
703
c619eed4 704 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 705 lvds_reg = PCH_LVDS;
706 else
707 lvds_reg = LVDS;
1974cad0 708 if (intel_is_dual_link_lvds(dev))
d4906093
ML		 709 clock.p2 = limit->p2.p2_fast;
710 else
711 clock.p2 = limit->p2.p2_slow;
712 } else {
713 if (target < limit->p2.dot_limit)
714 clock.p2 = limit->p2.p2_slow;
715 else
716 clock.p2 = limit->p2.p2_fast;
717 }
718
719 memset(best_clock, 0, sizeof(*best_clock));
720 max_n = limit->n.max;
f77f13e2 721 /* based on hardware requirement, prefer smaller n to precision */
d4906093 722 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 723 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 724 for (clock.m1 = limit->m1.max;
725 clock.m1 >= limit->m1.min; clock.m1--) {
726 for (clock.m2 = limit->m2.max;
727 clock.m2 >= limit->m2.min; clock.m2--) {
728 for (clock.p1 = limit->p1.max;
729 clock.p1 >= limit->p1.min; clock.p1--) {
730 int this_err;
731
2177832f 732 intel_clock(dev, refclk, &clock);
1b894b59
CW		 733 if (!intel_PLL_is_valid(dev, limit,
734 &clock))
d4906093 735 continue;
cec2f356
SP		 736 if (match_clock &&
737 clock.p != match_clock->p)
738 continue;
1b894b59
CW		 739
740 this_err = abs(clock.dot - target);
d4906093
ML		 741 if (this_err < err_most) {
742 *best_clock = clock;
743 err_most = this_err;
744 max_n = clock.n;
745 found = true;
746 }
747 }
748 }
749 }
750 }
2c07245f
ZW		 751 return found;
752}
753
5eb08b69 754static bool
f2b115e6 755intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 756 int target, int refclk, intel_clock_t *match_clock,
757 intel_clock_t *best_clock)
5eb08b69
ZW		 758{
759 struct drm_device *dev = crtc->dev;
760 intel_clock_t clock;
4547668a 761
5eb08b69
ZW		 762 if (target < 200000) {
763 clock.n = 1;
764 clock.p1 = 2;
765 clock.p2 = 10;
766 clock.m1 = 12;
767 clock.m2 = 9;
768 } else {
769 clock.n = 2;
770 clock.p1 = 1;
771 clock.p2 = 10;
772 clock.m1 = 14;
773 clock.m2 = 8;
774 }
775 intel_clock(dev, refclk, &clock);
776 memcpy(best_clock, &clock, sizeof(intel_clock_t));
777 return true;
778}
779
a4fc5ed6
KP		 780/* DisplayPort has only two frequencies, 162MHz and 270MHz */
781static bool
782intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 783 int target, int refclk, intel_clock_t *match_clock,
784 intel_clock_t *best_clock)
a4fc5ed6 785{
5eddb70b
CW		 786 intel_clock_t clock;
787 if (target < 200000) {
788 clock.p1 = 2;
789 clock.p2 = 10;
790 clock.n = 2;
791 clock.m1 = 23;
792 clock.m2 = 8;
793 } else {
794 clock.p1 = 1;
795 clock.p2 = 10;
796 clock.n = 1;
797 clock.m1 = 14;
798 clock.m2 = 2;
799 }
800 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
801 clock.p = (clock.p1 * clock.p2);
802 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
803 clock.vco = 0;
804 memcpy(best_clock, &clock, sizeof(intel_clock_t));
805 return true;
a4fc5ed6 806}
a0c4da24
JB		 807static bool
808intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
809 int target, int refclk, intel_clock_t *match_clock,
810 intel_clock_t *best_clock)
811{
812 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
813 u32 m, n, fastclk;
814 u32 updrate, minupdate, fracbits, p;
815 unsigned long bestppm, ppm, absppm;
816 int dotclk, flag;
817
af447bd3 818 flag = 0;
a0c4da24
JB		 819 dotclk = target * 1000;
820 bestppm = 1000000;
821 ppm = absppm = 0;
822 fastclk = dotclk / (2*100);
823 updrate = 0;
824 minupdate = 19200;
825 fracbits = 1;
826 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
827 bestm1 = bestm2 = bestp1 = bestp2 = 0;
828
829 /* based on hardware requirement, prefer smaller n to precision */
830 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
831 updrate = refclk / n;
832 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
833 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
834 if (p2 > 10)
835 p2 = p2 - 1;
836 p = p1 * p2;
837 /* based on hardware requirement, prefer bigger m1,m2 values */
838 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
839 m2 = (((2*(fastclk * p * n / m1 )) +
840 refclk) / (2*refclk));
841 m = m1 * m2;
842 vco = updrate * m;
843 if (vco >= limit->vco.min && vco < limit->vco.max) {
844 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
845 absppm = (ppm > 0) ? ppm : (-ppm);
846 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
847 bestppm = 0;
848 flag = 1;
849 }
850 if (absppm < bestppm - 10) {
851 bestppm = absppm;
852 flag = 1;
853 }
854 if (flag) {
855 bestn = n;
856 bestm1 = m1;
857 bestm2 = m2;
858 bestp1 = p1;
859 bestp2 = p2;
860 flag = 0;
861 }
862 }
863 }
864 }
865 }
866 }
867 best_clock->n = bestn;
868 best_clock->m1 = bestm1;
869 best_clock->m2 = bestm2;
870 best_clock->p1 = bestp1;
871 best_clock->p2 = bestp2;
872
873 return true;
874}
a4fc5ed6 875
a5c961d1
PZ		 876enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
877 enum pipe pipe)
878{
879 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
880 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
881
882 return intel_crtc->cpu_transcoder;
883}
884
a928d536
PZ		 885static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
886{
887 struct drm_i915_private *dev_priv = dev->dev_private;
888 u32 frame, frame_reg = PIPEFRAME(pipe);
889
890 frame = I915_READ(frame_reg);
891
892 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
893 DRM_DEBUG_KMS("vblank wait timed out\n");
894}
895
9d0498a2
JB		 896/**
897 * intel_wait_for_vblank - wait for vblank on a given pipe
898 * @dev: drm device
899 * @pipe: pipe to wait for
900 *
901 * Wait for vblank to occur on a given pipe. Needed for various bits of
902 * mode setting code.
903 */
904void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 905{
9d0498a2 906 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 907 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 908
a928d536
PZ		 909 if (INTEL_INFO(dev)->gen >= 5) {
910 ironlake_wait_for_vblank(dev, pipe);
911 return;
912 }
913
300387c0
CW		 914 /* Clear existing vblank status. Note this will clear any other
915 * sticky status fields as well.
916 *
917 * This races with i915_driver_irq_handler() with the result
918 * that either function could miss a vblank event. Here it is not
919 * fatal, as we will either wait upon the next vblank interrupt or
920 * timeout. Generally speaking intel_wait_for_vblank() is only
921 * called during modeset at which time the GPU should be idle and
922 * should *not* be performing page flips and thus not waiting on
923 * vblanks...
924 * Currently, the result of us stealing a vblank from the irq
925 * handler is that a single frame will be skipped during swapbuffers.
926 */
927 I915_WRITE(pipestat_reg,
928 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
929
9d0498a2 930 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 931 if (wait_for(I915_READ(pipestat_reg) &
932 PIPE_VBLANK_INTERRUPT_STATUS,
933 50))
9d0498a2
JB		 934 DRM_DEBUG_KMS("vblank wait timed out\n");
935}
936
ab7ad7f6
KP		 937/*
938 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 939 * @dev: drm device
940 * @pipe: pipe to wait for
941 *
942 * After disabling a pipe, we can't wait for vblank in the usual way,
943 * spinning on the vblank interrupt status bit, since we won't actually
944 * see an interrupt when the pipe is disabled.
945 *
ab7ad7f6
KP		 946 * On Gen4 and above:
947 * wait for the pipe register state bit to turn off
948 *
949 * Otherwise:
950 * wait for the display line value to settle (it usually
951 * ends up stopping at the start of the next frame).
58e10eb9 952 *
9d0498a2 953 */
58e10eb9 954void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 955{
956 struct drm_i915_private *dev_priv = dev->dev_private;
702e7a56
PZ		 957 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
958 pipe);
ab7ad7f6
KP		 959
960 if (INTEL_INFO(dev)->gen >= 4) {
702e7a56 961 int reg = PIPECONF(cpu_transcoder);
ab7ad7f6
KP		 962
963 /* Wait for the Pipe State to go off */
58e10eb9
CW		 964 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
965 100))
284637d9 966 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 967 } else {
837ba00f 968 u32 last_line, line_mask;
58e10eb9 969 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 970 unsigned long timeout = jiffies + msecs_to_jiffies(100);
971
837ba00f
PZ		 972 if (IS_GEN2(dev))
973 line_mask = DSL_LINEMASK_GEN2;
974 else
975 line_mask = DSL_LINEMASK_GEN3;
976
ab7ad7f6
KP		 977 /* Wait for the display line to settle */
978 do {
837ba00f 979 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 980 mdelay(5);
837ba00f 981 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 982 time_after(timeout, jiffies));
983 if (time_after(jiffies, timeout))
284637d9 984 WARN(1, "pipe_off wait timed out\n");
ab7ad7f6 985 }
79e53945
JB		 986}
987
b0ea7d37
DL		 988/*
989 * ibx_digital_port_connected - is the specified port connected?
990 * @dev_priv: i915 private structure
991 * @port: the port to test
992 *
993 * Returns true if @port is connected, false otherwise.
994 */
995bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
996 struct intel_digital_port *port)
997{
998 u32 bit;
999
c36346e3
DL		 1000 if (HAS_PCH_IBX(dev_priv->dev)) {
1001 switch(port->port) {
1002 case PORT_B:
1003 bit = SDE_PORTB_HOTPLUG;
1004 break;
1005 case PORT_C:
1006 bit = SDE_PORTC_HOTPLUG;
1007 break;
1008 case PORT_D:
1009 bit = SDE_PORTD_HOTPLUG;
1010 break;
1011 default:
1012 return true;
1013 }
1014 } else {
1015 switch(port->port) {
1016 case PORT_B:
1017 bit = SDE_PORTB_HOTPLUG_CPT;
1018 break;
1019 case PORT_C:
1020 bit = SDE_PORTC_HOTPLUG_CPT;
1021 break;
1022 case PORT_D:
1023 bit = SDE_PORTD_HOTPLUG_CPT;
1024 break;
1025 default:
1026 return true;
1027 }
b0ea7d37
DL		 1028 }
1029
1030 return I915_READ(SDEISR) & bit;
1031}
1032
b24e7179
JB		 1033static const char *state_string(bool enabled)
1034{
1035 return enabled ? "on" : "off";
1036}
1037
1038/* Only for pre-ILK configs */
1039static void assert_pll(struct drm_i915_private *dev_priv,
1040 enum pipe pipe, bool state)
1041{
1042 int reg;
1043 u32 val;
1044 bool cur_state;
1045
1046 reg = DPLL(pipe);
1047 val = I915_READ(reg);
1048 cur_state = !!(val & DPLL_VCO_ENABLE);
1049 WARN(cur_state != state,
1050 "PLL state assertion failure (expected %s, current %s)\n",
1051 state_string(state), state_string(cur_state));
1052}
1053#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1054#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1055
040484af
JB		 1056/* For ILK+ */
1057static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1058 struct intel_pch_pll *pll,
1059 struct intel_crtc *crtc,
1060 bool state)
040484af 1061{
040484af
JB		 1062 u32 val;
1063 bool cur_state;
1064
9d82aa17
ED		 1065 if (HAS_PCH_LPT(dev_priv->dev)) {
1066 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1067 return;
1068 }
1069
92b27b08
CW		 1070 if (WARN (!pll,
1071 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1072 return;
ee7b9f93 1073
92b27b08
CW		 1074 val = I915_READ(pll->pll_reg);
1075 cur_state = !!(val & DPLL_VCO_ENABLE);
1076 WARN(cur_state != state,
1077 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1078 pll->pll_reg, state_string(state), state_string(cur_state), val);
1079
1080 /* Make sure the selected PLL is correctly attached to the transcoder */
1081 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1082 u32 pch_dpll;
1083
1084 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1085 cur_state = pll->pll_reg == _PCH_DPLL_B;
1086 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1087 "PLL[%d] not attached to this transcoder %d: %08x\n",
1088 cur_state, crtc->pipe, pch_dpll)) {
1089 cur_state = !!(val >> (4*crtc->pipe + 3));
1090 WARN(cur_state != state,
1091 "PLL[%d] not %s on this transcoder %d: %08x\n",
1092 pll->pll_reg == _PCH_DPLL_B,
1093 state_string(state),
1094 crtc->pipe,
1095 val);
1096 }
d3ccbe86 1097 }
040484af 1098}
92b27b08
CW		 1099#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1100#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1101
1102static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1103 enum pipe pipe, bool state)
1104{
1105 int reg;
1106 u32 val;
1107 bool cur_state;
ad80a810
PZ		 1108 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1109 pipe);
040484af 1110
affa9354
PZ		 1111 if (HAS_DDI(dev_priv->dev)) {
1112 /* DDI does not have a specific FDI_TX register */
ad80a810 1113 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
bf507ef7 1114 val = I915_READ(reg);
ad80a810 1115 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
bf507ef7
ED		 1116 } else {
1117 reg = FDI_TX_CTL(pipe);
1118 val = I915_READ(reg);
1119 cur_state = !!(val & FDI_TX_ENABLE);
1120 }
040484af
JB		 1121 WARN(cur_state != state,
1122 "FDI TX state assertion failure (expected %s, current %s)\n",
1123 state_string(state), state_string(cur_state));
1124}
1125#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1126#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1127
1128static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1129 enum pipe pipe, bool state)
1130{
1131 int reg;
1132 u32 val;
1133 bool cur_state;
1134
d63fa0dc
PZ		 1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
040484af
JB		 1138 WARN(cur_state != state,
1139 "FDI RX state assertion failure (expected %s, current %s)\n",
1140 state_string(state), state_string(cur_state));
1141}
1142#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1143#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1144
1145static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1146 enum pipe pipe)
1147{
1148 int reg;
1149 u32 val;
1150
1151 /* ILK FDI PLL is always enabled */
1152 if (dev_priv->info->gen == 5)
1153 return;
1154
bf507ef7 1155 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
affa9354 1156 if (HAS_DDI(dev_priv->dev))
bf507ef7
ED		 1157 return;
1158
040484af
JB		 1159 reg = FDI_TX_CTL(pipe);
1160 val = I915_READ(reg);
1161 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1162}
1163
1164static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1165 enum pipe pipe)
1166{
1167 int reg;
1168 u32 val;
1169
1170 reg = FDI_RX_CTL(pipe);
1171 val = I915_READ(reg);
1172 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1173}
1174
ea0760cf
JB		 1175static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1176 enum pipe pipe)
1177{
1178 int pp_reg, lvds_reg;
1179 u32 val;
1180 enum pipe panel_pipe = PIPE_A;
0de3b485 1181 bool locked = true;
ea0760cf
JB		 1182
1183 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1184 pp_reg = PCH_PP_CONTROL;
1185 lvds_reg = PCH_LVDS;
1186 } else {
1187 pp_reg = PP_CONTROL;
1188 lvds_reg = LVDS;
1189 }
1190
1191 val = I915_READ(pp_reg);
1192 if (!(val & PANEL_POWER_ON) ||
1193 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1194 locked = false;
1195
1196 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1197 panel_pipe = PIPE_B;
1198
1199 WARN(panel_pipe == pipe && locked,
1200 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1201 pipe_name(pipe));
ea0760cf
JB		 1202}
1203
b840d907
JB		 1204void assert_pipe(struct drm_i915_private *dev_priv,
1205 enum pipe pipe, bool state)
b24e7179
JB		 1206{
1207 int reg;
1208 u32 val;
63d7bbe9 1209 bool cur_state;
702e7a56
PZ		 1210 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1211 pipe);
b24e7179 1212
8e636784
DV		 1213 /* if we need the pipe A quirk it must be always on */
1214 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1215 state = true;
1216
69310161
PZ		 1217 if (IS_HASWELL(dev_priv->dev) && cpu_transcoder != TRANSCODER_EDP &&
1218 !(I915_READ(HSW_PWR_WELL_DRIVER) & HSW_PWR_WELL_ENABLE)) {
1219 cur_state = false;
1220 } else {
1221 reg = PIPECONF(cpu_transcoder);
1222 val = I915_READ(reg);
1223 cur_state = !!(val & PIPECONF_ENABLE);
1224 }
1225
63d7bbe9
JB		 1226 WARN(cur_state != state,
1227 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1228 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1229}
1230
931872fc
CW		 1231static void assert_plane(struct drm_i915_private *dev_priv,
1232 enum plane plane, bool state)
b24e7179
JB		 1233{
1234 int reg;
1235 u32 val;
931872fc 1236 bool cur_state;
b24e7179
JB		 1237
1238 reg = DSPCNTR(plane);
1239 val = I915_READ(reg);
931872fc
CW		 1240 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1241 WARN(cur_state != state,
1242 "plane %c assertion failure (expected %s, current %s)\n",
1243 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1244}
1245
931872fc
CW		 1246#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1247#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1248
b24e7179
JB		 1249static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1250 enum pipe pipe)
1251{
1252 int reg, i;
1253 u32 val;
1254 int cur_pipe;
1255
19ec1358 1256 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1257 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1258 reg = DSPCNTR(pipe);
1259 val = I915_READ(reg);
1260 WARN((val & DISPLAY_PLANE_ENABLE),
1261 "plane %c assertion failure, should be disabled but not\n",
1262 plane_name(pipe));
19ec1358 1263 return;
28c05794 1264 }
19ec1358 1265
b24e7179
JB		 1266 /* Need to check both planes against the pipe */
1267 for (i = 0; i < 2; i++) {
1268 reg = DSPCNTR(i);
1269 val = I915_READ(reg);
1270 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1271 DISPPLANE_SEL_PIPE_SHIFT;
1272 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1273 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1274 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1275 }
1276}
1277
92f2584a
JB		 1278static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1279{
1280 u32 val;
1281 bool enabled;
1282
9d82aa17
ED		 1283 if (HAS_PCH_LPT(dev_priv->dev)) {
1284 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1285 return;
1286 }
1287
92f2584a
JB		 1288 val = I915_READ(PCH_DREF_CONTROL);
1289 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1290 DREF_SUPERSPREAD_SOURCE_MASK));
1291 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1292}
1293
1294static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1295 enum pipe pipe)
1296{
1297 int reg;
1298 u32 val;
1299 bool enabled;
1300
1301 reg = TRANSCONF(pipe);
1302 val = I915_READ(reg);
1303 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1304 WARN(enabled,
1305 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1306 pipe_name(pipe));
92f2584a
JB		 1307}
1308
4e634389
KP		 1309static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1310 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1311{
1312 if ((val & DP_PORT_EN) == 0)
1313 return false;
1314
1315 if (HAS_PCH_CPT(dev_priv->dev)) {
1316 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1317 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1318 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1319 return false;
1320 } else {
1321 if ((val & DP_PIPE_MASK) != (pipe << 30))
1322 return false;
1323 }
1324 return true;
1325}
1326
1519b995
KP		 1327static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1328 enum pipe pipe, u32 val)
1329{
1330 if ((val & PORT_ENABLE) == 0)
1331 return false;
1332
1333 if (HAS_PCH_CPT(dev_priv->dev)) {
1334 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1335 return false;
1336 } else {
1337 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1338 return false;
1339 }
1340 return true;
1341}
1342
1343static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1344 enum pipe pipe, u32 val)
1345{
1346 if ((val & LVDS_PORT_EN) == 0)
1347 return false;
1348
1349 if (HAS_PCH_CPT(dev_priv->dev)) {
1350 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1351 return false;
1352 } else {
1353 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1354 return false;
1355 }
1356 return true;
1357}
1358
1359static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1360 enum pipe pipe, u32 val)
1361{
1362 if ((val & ADPA_DAC_ENABLE) == 0)
1363 return false;
1364 if (HAS_PCH_CPT(dev_priv->dev)) {
1365 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1366 return false;
1367 } else {
1368 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1369 return false;
1370 }
1371 return true;
1372}
1373
291906f1 1374static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1375 enum pipe pipe, int reg, u32 port_sel)
291906f1 1376{
47a05eca 1377 u32 val = I915_READ(reg);
4e634389 1378 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1379 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1380 reg, pipe_name(pipe));
de9a35ab 1381
75c5da27
DV		 1382 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1383 && (val & DP_PIPEB_SELECT),
de9a35ab 1384 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1385}
1386
1387static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1388 enum pipe pipe, int reg)
1389{
47a05eca 1390 u32 val = I915_READ(reg);
b70ad586 1391 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1392 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1393 reg, pipe_name(pipe));
de9a35ab 1394
75c5da27
DV		 1395 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1396 && (val & SDVO_PIPE_B_SELECT),
de9a35ab 1397 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1398}
1399
1400static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1401 enum pipe pipe)
1402{
1403 int reg;
1404 u32 val;
291906f1 1405
f0575e92
KP		 1406 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1407 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1408 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1409
1410 reg = PCH_ADPA;
1411 val = I915_READ(reg);
b70ad586 1412 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1413 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1414 pipe_name(pipe));
291906f1
JB		 1415
1416 reg = PCH_LVDS;
1417 val = I915_READ(reg);
b70ad586 1418 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1419 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1420 pipe_name(pipe));
291906f1
JB		 1421
1422 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1423 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1424 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1425}
1426
63d7bbe9
JB		 1427/**
1428 * intel_enable_pll - enable a PLL
1429 * @dev_priv: i915 private structure
1430 * @pipe: pipe PLL to enable
1431 *
1432 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1433 * make sure the PLL reg is writable first though, since the panel write
1434 * protect mechanism may be enabled.
1435 *
1436 * Note! This is for pre-ILK only.
7434a255
TR		 1437 *
1438 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9
JB		 1439 */
1440static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1441{
1442 int reg;
1443 u32 val;
1444
1445 /* No really, not for ILK+ */
a0c4da24 1446 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1447
1448 /* PLL is protected by panel, make sure we can write it */
1449 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1450 assert_panel_unlocked(dev_priv, pipe);
1451
1452 reg = DPLL(pipe);
1453 val = I915_READ(reg);
1454 val |= DPLL_VCO_ENABLE;
1455
1456 /* We do this three times for luck */
1457 I915_WRITE(reg, val);
1458 POSTING_READ(reg);
1459 udelay(150); /* wait for warmup */
1460 I915_WRITE(reg, val);
1461 POSTING_READ(reg);
1462 udelay(150); /* wait for warmup */
1463 I915_WRITE(reg, val);
1464 POSTING_READ(reg);
1465 udelay(150); /* wait for warmup */
1466}
1467
1468/**
1469 * intel_disable_pll - disable a PLL
1470 * @dev_priv: i915 private structure
1471 * @pipe: pipe PLL to disable
1472 *
1473 * Disable the PLL for @pipe, making sure the pipe is off first.
1474 *
1475 * Note! This is for pre-ILK only.
1476 */
1477static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1478{
1479 int reg;
1480 u32 val;
1481
1482 /* Don't disable pipe A or pipe A PLLs if needed */
1483 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1484 return;
1485
1486 /* Make sure the pipe isn't still relying on us */
1487 assert_pipe_disabled(dev_priv, pipe);
1488
1489 reg = DPLL(pipe);
1490 val = I915_READ(reg);
1491 val &= ~DPLL_VCO_ENABLE;
1492 I915_WRITE(reg, val);
1493 POSTING_READ(reg);
1494}
1495
a416edef
ED		 1496/* SBI access */
1497static void
988d6ee8
PZ		 1498intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
1499 enum intel_sbi_destination destination)
a416edef 1500{
988d6ee8 1501 u32 tmp;
a416edef 1502
09153000 1503 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1504
39fb50f6 1505 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1506 100)) {
1507 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1508 return;
a416edef
ED		 1509 }
1510
988d6ee8
PZ		 1511 I915_WRITE(SBI_ADDR, (reg << 16));
1512 I915_WRITE(SBI_DATA, value);
1513
1514 if (destination == SBI_ICLK)
1515 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
1516 else
1517 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
1518 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
a416edef 1519
39fb50f6 1520 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1521 100)) {
1522 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
09153000 1523 return;
a416edef 1524 }
a416edef
ED		 1525}
1526
1527static u32
988d6ee8
PZ		 1528intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
1529 enum intel_sbi_destination destination)
a416edef 1530{
39fb50f6 1531 u32 value = 0;
09153000 1532 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
a416edef 1533
39fb50f6 1534 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1535 100)) {
1536 DRM_ERROR("timeout waiting for SBI to become ready\n");
09153000 1537 return 0;
a416edef
ED		 1538 }
1539
988d6ee8
PZ		 1540 I915_WRITE(SBI_ADDR, (reg << 16));
1541
1542 if (destination == SBI_ICLK)
1543 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
1544 else
1545 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
1546 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
a416edef 1547
39fb50f6 1548 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1549 100)) {
1550 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
09153000 1551 return 0;
a416edef
ED		 1552 }
1553
09153000 1554 return I915_READ(SBI_DATA);
a416edef
ED		 1555}
1556
92f2584a 1557/**
b6b4e185 1558 * ironlake_enable_pch_pll - enable PCH PLL
92f2584a
JB		 1559 * @dev_priv: i915 private structure
1560 * @pipe: pipe PLL to enable
1561 *
1562 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1563 * drives the transcoder clock.
1564 */
b6b4e185 1565static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1566{
ee7b9f93 1567 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1568 struct intel_pch_pll *pll;
92f2584a
JB		 1569 int reg;
1570 u32 val;
1571
48da64a8 1572 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1573 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1574 pll = intel_crtc->pch_pll;
1575 if (pll == NULL)
1576 return;
1577
1578 if (WARN_ON(pll->refcount == 0))
1579 return;
ee7b9f93
JB		 1580
1581 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1582 pll->pll_reg, pll->active, pll->on,
1583 intel_crtc->base.base.id);
92f2584a
JB		 1584
1585 /* PCH refclock must be enabled first */
1586 assert_pch_refclk_enabled(dev_priv);
1587
ee7b9f93 1588 if (pll->active++ && pll->on) {
92b27b08 1589 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1590 return;
1591 }
1592
1593 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1594
1595 reg = pll->pll_reg;
92f2584a
JB		 1596 val = I915_READ(reg);
1597 val |= DPLL_VCO_ENABLE;
1598 I915_WRITE(reg, val);
1599 POSTING_READ(reg);
1600 udelay(200);
ee7b9f93
JB		 1601
1602 pll->on = true;
92f2584a
JB		 1603}
1604
ee7b9f93 1605static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1606{
ee7b9f93
JB		 1607 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1608 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1609 int reg;
ee7b9f93 1610 u32 val;
4c609cb8 1611
92f2584a
JB		 1612 /* PCH only available on ILK+ */
1613 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1614 if (pll == NULL)
1615 return;
92f2584a 1616
48da64a8
CW		 1617 if (WARN_ON(pll->refcount == 0))
1618 return;
7a419866 1619
ee7b9f93
JB		 1620 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1621 pll->pll_reg, pll->active, pll->on,
1622 intel_crtc->base.base.id);
7a419866 1623
48da64a8 1624 if (WARN_ON(pll->active == 0)) {
92b27b08 1625 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1626 return;
1627 }
1628
ee7b9f93 1629 if (--pll->active) {
92b27b08 1630 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1631 return;
ee7b9f93
JB		 1632 }
1633
1634 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1635
1636 /* Make sure transcoder isn't still depending on us */
1637 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1638
ee7b9f93 1639 reg = pll->pll_reg;
92f2584a
JB		 1640 val = I915_READ(reg);
1641 val &= ~DPLL_VCO_ENABLE;
1642 I915_WRITE(reg, val);
1643 POSTING_READ(reg);
1644 udelay(200);
ee7b9f93
JB		 1645
1646 pll->on = false;
92f2584a
JB		 1647}
1648
b8a4f404
PZ		 1649static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1650 enum pipe pipe)
040484af 1651{
23670b32 1652 struct drm_device *dev = dev_priv->dev;
7c26e5c6 1653 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
23670b32 1654 uint32_t reg, val, pipeconf_val;
040484af
JB		 1655
1656 /* PCH only available on ILK+ */
1657 BUG_ON(dev_priv->info->gen < 5);
1658
1659 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1660 assert_pch_pll_enabled(dev_priv,
1661 to_intel_crtc(crtc)->pch_pll,
1662 to_intel_crtc(crtc));
040484af
JB		 1663
1664 /* FDI must be feeding us bits for PCH ports */
1665 assert_fdi_tx_enabled(dev_priv, pipe);
1666 assert_fdi_rx_enabled(dev_priv, pipe);
1667
23670b32
DV		 1668 if (HAS_PCH_CPT(dev)) {
1669 /* Workaround: Set the timing override bit before enabling the
1670 * pch transcoder. */
1671 reg = TRANS_CHICKEN2(pipe);
1672 val = I915_READ(reg);
1673 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1674 I915_WRITE(reg, val);
59c859d6 1675 }
23670b32 1676
040484af
JB		 1677 reg = TRANSCONF(pipe);
1678 val = I915_READ(reg);
5f7f726d 1679 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1680
1681 if (HAS_PCH_IBX(dev_priv->dev)) {
1682 /*
1683 * make the BPC in transcoder be consistent with
1684 * that in pipeconf reg.
1685 */
dfd07d72
DV		 1686 val &= ~PIPECONF_BPC_MASK;
1687 val |= pipeconf_val & PIPECONF_BPC_MASK;
e9bcff5c 1688 }
5f7f726d
PZ		 1689
1690 val &= ~TRANS_INTERLACE_MASK;
1691 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1692 if (HAS_PCH_IBX(dev_priv->dev) &&
1693 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1694 val |= TRANS_LEGACY_INTERLACED_ILK;
1695 else
1696 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1697 else
1698 val |= TRANS_PROGRESSIVE;
1699
040484af
JB		 1700 I915_WRITE(reg, val | TRANS_ENABLE);
1701 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1702 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1703}
1704
8fb033d7 1705static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
937bb610 1706 enum transcoder cpu_transcoder)
040484af 1707{
8fb033d7 1708 u32 val, pipeconf_val;
8fb033d7
PZ		 1709
1710 /* PCH only available on ILK+ */
1711 BUG_ON(dev_priv->info->gen < 5);
1712
8fb033d7 1713 /* FDI must be feeding us bits for PCH ports */
1a240d4d 1714 assert_fdi_tx_enabled(dev_priv, (enum pipe) cpu_transcoder);
937bb610 1715 assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
8fb033d7 1716
223a6fdf
PZ		 1717 /* Workaround: set timing override bit. */
1718 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1719 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf
PZ		 1720 I915_WRITE(_TRANSA_CHICKEN2, val);
1721
25f3ef11 1722 val = TRANS_ENABLE;
937bb610 1723 pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
8fb033d7 1724
9a76b1c6
PZ		 1725 if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1726 PIPECONF_INTERLACED_ILK)
a35f2679 1727 val |= TRANS_INTERLACED;
8fb033d7
PZ		 1728 else
1729 val |= TRANS_PROGRESSIVE;
1730
25f3ef11 1731 I915_WRITE(TRANSCONF(TRANSCODER_A), val);
937bb610
PZ		 1732 if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1733 DRM_ERROR("Failed to enable PCH transcoder\n");
8fb033d7
PZ		 1734}
1735
b8a4f404
PZ		 1736static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1737 enum pipe pipe)
040484af 1738{
23670b32
DV		 1739 struct drm_device *dev = dev_priv->dev;
1740 uint32_t reg, val;
040484af
JB		 1741
1742 /* FDI relies on the transcoder */
1743 assert_fdi_tx_disabled(dev_priv, pipe);
1744 assert_fdi_rx_disabled(dev_priv, pipe);
1745
291906f1
JB		 1746 /* Ports must be off as well */
1747 assert_pch_ports_disabled(dev_priv, pipe);
1748
040484af
JB		 1749 reg = TRANSCONF(pipe);
1750 val = I915_READ(reg);
1751 val &= ~TRANS_ENABLE;
1752 I915_WRITE(reg, val);
1753 /* wait for PCH transcoder off, transcoder state */
1754 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1755 DRM_ERROR("failed to disable transcoder %d\n", pipe);
23670b32
DV		 1756
1757 if (!HAS_PCH_IBX(dev)) {
1758 /* Workaround: Clear the timing override chicken bit again. */
1759 reg = TRANS_CHICKEN2(pipe);
1760 val = I915_READ(reg);
1761 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1762 I915_WRITE(reg, val);
1763 }
040484af
JB		 1764}
1765
ab4d966c 1766static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
8fb033d7 1767{
8fb033d7
PZ		 1768 u32 val;
1769
8a52fd9f 1770 val = I915_READ(_TRANSACONF);
8fb033d7 1771 val &= ~TRANS_ENABLE;
8a52fd9f 1772 I915_WRITE(_TRANSACONF, val);
8fb033d7 1773 /* wait for PCH transcoder off, transcoder state */
8a52fd9f
PZ		 1774 if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1775 DRM_ERROR("Failed to disable PCH transcoder\n");
223a6fdf
PZ		 1776
1777 /* Workaround: clear timing override bit. */
1778 val = I915_READ(_TRANSA_CHICKEN2);
23670b32 1779 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
223a6fdf 1780 I915_WRITE(_TRANSA_CHICKEN2, val);
040484af
JB		 1781}
1782
b24e7179 1783/**
309cfea8 1784 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1785 * @dev_priv: i915 private structure
1786 * @pipe: pipe to enable
040484af 1787 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1788 *
1789 * Enable @pipe, making sure that various hardware specific requirements
1790 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1791 *
1792 * @pipe should be %PIPE_A or %PIPE_B.
1793 *
1794 * Will wait until the pipe is actually running (i.e. first vblank) before
1795 * returning.
1796 */
040484af
JB		 1797static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1798 bool pch_port)
b24e7179 1799{
702e7a56
PZ		 1800 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1801 pipe);
1a240d4d 1802 enum pipe pch_transcoder;
b24e7179
JB		 1803 int reg;
1804 u32 val;
1805
681e5811 1806 if (HAS_PCH_LPT(dev_priv->dev))
cc391bbb
PZ		 1807 pch_transcoder = TRANSCODER_A;
1808 else
1809 pch_transcoder = pipe;
1810
b24e7179
JB		 1811 /*
1812 * A pipe without a PLL won't actually be able to drive bits from
1813 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1814 * need the check.
1815 */
1816 if (!HAS_PCH_SPLIT(dev_priv->dev))
1817 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1818 else {
1819 if (pch_port) {
1820 /* if driving the PCH, we need FDI enabled */
cc391bbb 1821 assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1a240d4d
DV		 1822 assert_fdi_tx_pll_enabled(dev_priv,
1823 (enum pipe) cpu_transcoder);
040484af
JB		 1824 }
1825 /* FIXME: assert CPU port conditions for SNB+ */
1826 }
b24e7179 1827
702e7a56 1828 reg = PIPECONF(cpu_transcoder);
b24e7179 1829 val = I915_READ(reg);
00d70b15
CW		 1830 if (val & PIPECONF_ENABLE)
1831 return;
1832
1833 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1834 intel_wait_for_vblank(dev_priv->dev, pipe);
1835}
1836
1837/**
309cfea8 1838 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1839 * @dev_priv: i915 private structure
1840 * @pipe: pipe to disable
1841 *
1842 * Disable @pipe, making sure that various hardware specific requirements
1843 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1844 *
1845 * @pipe should be %PIPE_A or %PIPE_B.
1846 *
1847 * Will wait until the pipe has shut down before returning.
1848 */
1849static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1850 enum pipe pipe)
1851{
702e7a56
PZ		 1852 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1853 pipe);
b24e7179
JB		 1854 int reg;
1855 u32 val;
1856
1857 /*
1858 * Make sure planes won't keep trying to pump pixels to us,
1859 * or we might hang the display.
1860 */
1861 assert_planes_disabled(dev_priv, pipe);
1862
1863 /* Don't disable pipe A or pipe A PLLs if needed */
1864 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1865 return;
1866
702e7a56 1867 reg = PIPECONF(cpu_transcoder);
b24e7179 1868 val = I915_READ(reg);
00d70b15
CW		 1869 if ((val & PIPECONF_ENABLE) == 0)
1870 return;
1871
1872 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1873 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1874}
1875
d74362c9
KP		 1876/*
1877 * Plane regs are double buffered, going from enabled->disabled needs a
1878 * trigger in order to latch. The display address reg provides this.
1879 */
6f1d69b0 1880void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1881 enum plane plane)
1882{
14f86147
DL		 1883 if (dev_priv->info->gen >= 4)
1884 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1885 else
1886 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
d74362c9
KP		 1887}
1888
b24e7179
JB		 1889/**
1890 * intel_enable_plane - enable a display plane on a given pipe
1891 * @dev_priv: i915 private structure
1892 * @plane: plane to enable
1893 * @pipe: pipe being fed
1894 *
1895 * Enable @plane on @pipe, making sure that @pipe is running first.
1896 */
1897static void intel_enable_plane(struct drm_i915_private *dev_priv,
1898 enum plane plane, enum pipe pipe)
1899{
1900 int reg;
1901 u32 val;
1902
1903 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1904 assert_pipe_enabled(dev_priv, pipe);
1905
1906 reg = DSPCNTR(plane);
1907 val = I915_READ(reg);
00d70b15
CW		 1908 if (val & DISPLAY_PLANE_ENABLE)
1909 return;
1910
1911 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1912 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1913 intel_wait_for_vblank(dev_priv->dev, pipe);
1914}
1915
b24e7179
JB		 1916/**
1917 * intel_disable_plane - disable a display plane
1918 * @dev_priv: i915 private structure
1919 * @plane: plane to disable
1920 * @pipe: pipe consuming the data
1921 *
1922 * Disable @plane; should be an independent operation.
1923 */
1924static void intel_disable_plane(struct drm_i915_private *dev_priv,
1925 enum plane plane, enum pipe pipe)
1926{
1927 int reg;
1928 u32 val;
1929
1930 reg = DSPCNTR(plane);
1931 val = I915_READ(reg);
00d70b15
CW		 1932 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1933 return;
1934
1935 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1936 intel_flush_display_plane(dev_priv, plane);
1937 intel_wait_for_vblank(dev_priv->dev, pipe);
1938}
1939
127bd2ac 1940int
48b956c5 1941intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1942 struct drm_i915_gem_object *obj,
919926ae 1943 struct intel_ring_buffer *pipelined)
6b95a207 1944{
ce453d81 1945 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1946 u32 alignment;
1947 int ret;
1948
05394f39 1949 switch (obj->tiling_mode) {
6b95a207 1950 case I915_TILING_NONE:
534843da
CW		 1951 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1952 alignment = 128 * 1024;
a6c45cf0 1953 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1954 alignment = 4 * 1024;
1955 else
1956 alignment = 64 * 1024;
6b95a207
KH		 1957 break;
1958 case I915_TILING_X:
1959 /* pin() will align the object as required by fence */
1960 alignment = 0;
1961 break;
1962 case I915_TILING_Y:
1963 /* FIXME: Is this true? */
1964 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1965 return -EINVAL;
1966 default:
1967 BUG();
1968 }
1969
ce453d81 1970 dev_priv->mm.interruptible = false;
2da3b9b9 1971 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1972 if (ret)
ce453d81 1973 goto err_interruptible;
6b95a207
KH		 1974
1975 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1976 * fence, whereas 965+ only requires a fence if using
1977 * framebuffer compression. For simplicity, we always install
1978 * a fence as the cost is not that onerous.
1979 */
06d98131 1980 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1981 if (ret)
1982 goto err_unpin;
1690e1eb 1983
9a5a53b3 1984 i915_gem_object_pin_fence(obj);
6b95a207 1985
ce453d81 1986 dev_priv->mm.interruptible = true;
6b95a207 1987 return 0;
48b956c5
CW		 1988
1989err_unpin:
1990 i915_gem_object_unpin(obj);
ce453d81
CW		 1991err_interruptible:
1992 dev_priv->mm.interruptible = true;
48b956c5 1993 return ret;
6b95a207
KH		 1994}
1995
1690e1eb
CW		 1996void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1997{
1998 i915_gem_object_unpin_fence(obj);
1999 i915_gem_object_unpin(obj);
2000}
2001
c2c75131
DV		 2002/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
2003 * is assumed to be a power-of-two. */
5a35e99e
DL		 2004unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
2005 unsigned int bpp,
2006 unsigned int pitch)
c2c75131
DV		 2007{
2008 int tile_rows, tiles;
2009
2010 tile_rows = *y / 8;
2011 *y %= 8;
2012 tiles = *x / (512/bpp);
2013 *x %= 512/bpp;
2014
2015 return tile_rows * pitch * 8 + tiles * 4096;
2016}
2017
17638cd6
JB		 2018static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2019 int x, int y)
81255565
JB		 2020{
2021 struct drm_device *dev = crtc->dev;
2022 struct drm_i915_private *dev_priv = dev->dev_private;
2023 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2024 struct intel_framebuffer *intel_fb;
05394f39 2025 struct drm_i915_gem_object *obj;
81255565 2026 int plane = intel_crtc->plane;
e506a0c6 2027 unsigned long linear_offset;
81255565 2028 u32 dspcntr;
5eddb70b 2029 u32 reg;
81255565
JB		 2030
2031 switch (plane) {
2032 case 0:
2033 case 1:
2034 break;
2035 default:
2036 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2037 return -EINVAL;
2038 }
2039
2040 intel_fb = to_intel_framebuffer(fb);
2041 obj = intel_fb->obj;
81255565 2042
5eddb70b
CW		 2043 reg = DSPCNTR(plane);
2044 dspcntr = I915_READ(reg);
81255565
JB		 2045 /* Mask out pixel format bits in case we change it */
2046 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2047 switch (fb->pixel_format) {
2048 case DRM_FORMAT_C8:
81255565
JB		 2049 dspcntr |= DISPPLANE_8BPP;
2050 break;
57779d06
VS		 2051 case DRM_FORMAT_XRGB1555:
2052 case DRM_FORMAT_ARGB1555:
2053 dspcntr |= DISPPLANE_BGRX555;
81255565 2054 break;
57779d06
VS		 2055 case DRM_FORMAT_RGB565:
2056 dspcntr |= DISPPLANE_BGRX565;
2057 break;
2058 case DRM_FORMAT_XRGB8888:
2059 case DRM_FORMAT_ARGB8888:
2060 dspcntr |= DISPPLANE_BGRX888;
2061 break;
2062 case DRM_FORMAT_XBGR8888:
2063 case DRM_FORMAT_ABGR8888:
2064 dspcntr |= DISPPLANE_RGBX888;
2065 break;
2066 case DRM_FORMAT_XRGB2101010:
2067 case DRM_FORMAT_ARGB2101010:
2068 dspcntr |= DISPPLANE_BGRX101010;
2069 break;
2070 case DRM_FORMAT_XBGR2101010:
2071 case DRM_FORMAT_ABGR2101010:
2072 dspcntr |= DISPPLANE_RGBX101010;
81255565
JB		 2073 break;
2074 default:
57779d06 2075 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
81255565
JB		 2076 return -EINVAL;
2077 }
57779d06 2078
a6c45cf0 2079 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2080 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2081 dspcntr |= DISPPLANE_TILED;
2082 else
2083 dspcntr &= ~DISPPLANE_TILED;
2084 }
2085
5eddb70b 2086 I915_WRITE(reg, dspcntr);
81255565 2087
e506a0c6 2088 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2089
c2c75131
DV		 2090 if (INTEL_INFO(dev)->gen >= 4) {
2091 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2092 intel_gen4_compute_offset_xtiled(&x, &y,
2093 fb->bits_per_pixel / 8,
2094 fb->pitches[0]);
c2c75131
DV		 2095 linear_offset -= intel_crtc->dspaddr_offset;
2096 } else {
e506a0c6 2097 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2098 }
e506a0c6
DV		 2099
2100 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2101 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2102 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2103 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2104 I915_MODIFY_DISPBASE(DSPSURF(plane),
2105 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2106 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2107 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2108 } else
e506a0c6 2109 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2110 POSTING_READ(reg);
81255565 2111
17638cd6
JB		 2112 return 0;
2113}
2114
2115static int ironlake_update_plane(struct drm_crtc *crtc,
2116 struct drm_framebuffer *fb, int x, int y)
2117{
2118 struct drm_device *dev = crtc->dev;
2119 struct drm_i915_private *dev_priv = dev->dev_private;
2120 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2121 struct intel_framebuffer *intel_fb;
2122 struct drm_i915_gem_object *obj;
2123 int plane = intel_crtc->plane;
e506a0c6 2124 unsigned long linear_offset;
17638cd6
JB		 2125 u32 dspcntr;
2126 u32 reg;
2127
2128 switch (plane) {
2129 case 0:
2130 case 1:
27f8227b 2131 case 2:
17638cd6
JB		 2132 break;
2133 default:
2134 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2135 return -EINVAL;
2136 }
2137
2138 intel_fb = to_intel_framebuffer(fb);
2139 obj = intel_fb->obj;
2140
2141 reg = DSPCNTR(plane);
2142 dspcntr = I915_READ(reg);
2143 /* Mask out pixel format bits in case we change it */
2144 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
57779d06
VS		 2145 switch (fb->pixel_format) {
2146 case DRM_FORMAT_C8:
17638cd6
JB		 2147 dspcntr |= DISPPLANE_8BPP;
2148 break;
57779d06
VS		 2149 case DRM_FORMAT_RGB565:
2150 dspcntr |= DISPPLANE_BGRX565;
17638cd6 2151 break;
57779d06
VS		 2152 case DRM_FORMAT_XRGB8888:
2153 case DRM_FORMAT_ARGB8888:
2154 dspcntr |= DISPPLANE_BGRX888;
2155 break;
2156 case DRM_FORMAT_XBGR8888:
2157 case DRM_FORMAT_ABGR8888:
2158 dspcntr |= DISPPLANE_RGBX888;
2159 break;
2160 case DRM_FORMAT_XRGB2101010:
2161 case DRM_FORMAT_ARGB2101010:
2162 dspcntr |= DISPPLANE_BGRX101010;
2163 break;
2164 case DRM_FORMAT_XBGR2101010:
2165 case DRM_FORMAT_ABGR2101010:
2166 dspcntr |= DISPPLANE_RGBX101010;
17638cd6
JB		 2167 break;
2168 default:
57779d06 2169 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
17638cd6
JB		 2170 return -EINVAL;
2171 }
2172
2173 if (obj->tiling_mode != I915_TILING_NONE)
2174 dspcntr |= DISPPLANE_TILED;
2175 else
2176 dspcntr &= ~DISPPLANE_TILED;
2177
2178 /* must disable */
2179 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2180
2181 I915_WRITE(reg, dspcntr);
2182
e506a0c6 2183 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131 2184 intel_crtc->dspaddr_offset =
5a35e99e
DL		 2185 intel_gen4_compute_offset_xtiled(&x, &y,
2186 fb->bits_per_pixel / 8,
2187 fb->pitches[0]);
c2c75131 2188 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2189
e506a0c6
DV		 2190 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2191 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2192 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2193 I915_MODIFY_DISPBASE(DSPSURF(plane),
2194 obj->gtt_offset + intel_crtc->dspaddr_offset);
bc1c91eb
DL		 2195 if (IS_HASWELL(dev)) {
2196 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2197 } else {
2198 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2199 I915_WRITE(DSPLINOFF(plane), linear_offset);
2200 }
17638cd6
JB		 2201 POSTING_READ(reg);
2202
2203 return 0;
2204}
2205
2206/* Assume fb object is pinned & idle & fenced and just update base pointers */
2207static int
2208intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2209 int x, int y, enum mode_set_atomic state)
2210{
2211 struct drm_device *dev = crtc->dev;
2212 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2213
6b8e6ed0
CW		 2214 if (dev_priv->display.disable_fbc)
2215 dev_priv->display.disable_fbc(dev);
3dec0095 2216 intel_increase_pllclock(crtc);
81255565 2217
6b8e6ed0 2218 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2219}
2220
14667a4b
CW		 2221static int
2222intel_finish_fb(struct drm_framebuffer *old_fb)
2223{
2224 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2225 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2226 bool was_interruptible = dev_priv->mm.interruptible;
2227 int ret;
2228
2c10d571
DV		 2229 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2230
14667a4b 2231 wait_event(dev_priv->pending_flip_queue,
1f83fee0 2232 i915_reset_in_progress(&dev_priv->gpu_error) ||
14667a4b
CW		 2233 atomic_read(&obj->pending_flip) == 0);
2234
2235 /* Big Hammer, we also need to ensure that any pending
2236 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2237 * current scanout is retired before unpinning the old
2238 * framebuffer.
2239 *
2240 * This should only fail upon a hung GPU, in which case we
2241 * can safely continue.
2242 */
2243 dev_priv->mm.interruptible = false;
2244 ret = i915_gem_object_finish_gpu(obj);
2245 dev_priv->mm.interruptible = was_interruptible;
2246
2247 return ret;
2248}
2249
198598d0
VS		 2250static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2251{
2252 struct drm_device *dev = crtc->dev;
2253 struct drm_i915_master_private *master_priv;
2254 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2255
2256 if (!dev->primary->master)
2257 return;
2258
2259 master_priv = dev->primary->master->driver_priv;
2260 if (!master_priv->sarea_priv)
2261 return;
2262
2263 switch (intel_crtc->pipe) {
2264 case 0:
2265 master_priv->sarea_priv->pipeA_x = x;
2266 master_priv->sarea_priv->pipeA_y = y;
2267 break;
2268 case 1:
2269 master_priv->sarea_priv->pipeB_x = x;
2270 master_priv->sarea_priv->pipeB_y = y;
2271 break;
2272 default:
2273 break;
2274 }
2275}
2276
5c3b82e2 2277static int
3c4fdcfb 2278intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2279 struct drm_framebuffer *fb)
79e53945
JB		 2280{
2281 struct drm_device *dev = crtc->dev;
6b8e6ed0 2282 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 2283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2284 struct drm_framebuffer *old_fb;
5c3b82e2 2285 int ret;
79e53945
JB		 2286
2287 /* no fb bound */
94352cf9 2288 if (!fb) {
a5071c2f 2289 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2290 return 0;
2291 }
2292
5826eca5
ED		 2293 if(intel_crtc->plane > dev_priv->num_pipe) {
2294 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2295 intel_crtc->plane,
2296 dev_priv->num_pipe);
5c3b82e2 2297 return -EINVAL;
79e53945
JB		 2298 }
2299
5c3b82e2 2300 mutex_lock(&dev->struct_mutex);
265db958 2301 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2302 to_intel_framebuffer(fb)->obj,
919926ae 2303 NULL);
5c3b82e2
CW		 2304 if (ret != 0) {
2305 mutex_unlock(&dev->struct_mutex);
a5071c2f 2306 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2307 return ret;
2308 }
79e53945 2309
94352cf9
DV		 2310 if (crtc->fb)
2311 intel_finish_fb(crtc->fb);
265db958 2312
94352cf9 2313 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2314 if (ret) {
94352cf9 2315 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2316 mutex_unlock(&dev->struct_mutex);
a5071c2f 2317 DRM_ERROR("failed to update base address\n");
4e6cfefc 2318 return ret;
79e53945 2319 }
3c4fdcfb 2320
94352cf9
DV		 2321 old_fb = crtc->fb;
2322 crtc->fb = fb;
6c4c86f5
DV		 2323 crtc->x = x;
2324 crtc->y = y;
94352cf9 2325
b7f1de28
CW		 2326 if (old_fb) {
2327 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2328 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2329 }
652c393a 2330
6b8e6ed0 2331 intel_update_fbc(dev);
5c3b82e2 2332 mutex_unlock(&dev->struct_mutex);
79e53945 2333
198598d0 2334 intel_crtc_update_sarea_pos(crtc, x, y);
5c3b82e2
CW		 2335
2336 return 0;
79e53945
JB		 2337}
2338
5e84e1a4
ZW		 2339static void intel_fdi_normal_train(struct drm_crtc *crtc)
2340{
2341 struct drm_device *dev = crtc->dev;
2342 struct drm_i915_private *dev_priv = dev->dev_private;
2343 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2344 int pipe = intel_crtc->pipe;
2345 u32 reg, temp;
2346
2347 /* enable normal train */
2348 reg = FDI_TX_CTL(pipe);
2349 temp = I915_READ(reg);
61e499bf 2350 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2351 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2352 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2353 } else {
2354 temp &= ~FDI_LINK_TRAIN_NONE;
2355 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2356 }
5e84e1a4
ZW		 2357 I915_WRITE(reg, temp);
2358
2359 reg = FDI_RX_CTL(pipe);
2360 temp = I915_READ(reg);
2361 if (HAS_PCH_CPT(dev)) {
2362 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2363 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2364 } else {
2365 temp &= ~FDI_LINK_TRAIN_NONE;
2366 temp |= FDI_LINK_TRAIN_NONE;
2367 }
2368 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2369
2370 /* wait one idle pattern time */
2371 POSTING_READ(reg);
2372 udelay(1000);
357555c0
JB		 2373
2374 /* IVB wants error correction enabled */
2375 if (IS_IVYBRIDGE(dev))
2376 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2377 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2378}
2379
01a415fd
DV		 2380static void ivb_modeset_global_resources(struct drm_device *dev)
2381{
2382 struct drm_i915_private *dev_priv = dev->dev_private;
2383 struct intel_crtc *pipe_B_crtc =
2384 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2385 struct intel_crtc *pipe_C_crtc =
2386 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2387 uint32_t temp;
2388
2389 /* When everything is off disable fdi C so that we could enable fdi B
2390 * with all lanes. XXX: This misses the case where a pipe is not using
2391 * any pch resources and so doesn't need any fdi lanes. */
2392 if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2393 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2394 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2395
2396 temp = I915_READ(SOUTH_CHICKEN1);
2397 temp &= ~FDI_BC_BIFURCATION_SELECT;
2398 DRM_DEBUG_KMS("disabling fdi C rx\n");
2399 I915_WRITE(SOUTH_CHICKEN1, temp);
2400 }
2401}
2402
8db9d77b
ZW		 2403/* The FDI link training functions for ILK/Ibexpeak. */
2404static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2405{
2406 struct drm_device *dev = crtc->dev;
2407 struct drm_i915_private *dev_priv = dev->dev_private;
2408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2409 int pipe = intel_crtc->pipe;
0fc932b8 2410 int plane = intel_crtc->plane;
5eddb70b 2411 u32 reg, temp, tries;
8db9d77b 2412
0fc932b8
JB		 2413 /* FDI needs bits from pipe & plane first */
2414 assert_pipe_enabled(dev_priv, pipe);
2415 assert_plane_enabled(dev_priv, plane);
2416
e1a44743
AJ		 2417 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2418 for train result */
5eddb70b
CW		 2419 reg = FDI_RX_IMR(pipe);
2420 temp = I915_READ(reg);
e1a44743
AJ		 2421 temp &= ~FDI_RX_SYMBOL_LOCK;
2422 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2423 I915_WRITE(reg, temp);
2424 I915_READ(reg);
e1a44743
AJ		 2425 udelay(150);
2426
8db9d77b 2427 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2428 reg = FDI_TX_CTL(pipe);
2429 temp = I915_READ(reg);
77ffb597
AJ		 2430 temp &= ~(7 << 19);
2431 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2434 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2435
5eddb70b
CW		 2436 reg = FDI_RX_CTL(pipe);
2437 temp = I915_READ(reg);
8db9d77b
ZW		 2438 temp &= ~FDI_LINK_TRAIN_NONE;
2439 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2440 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2441
2442 POSTING_READ(reg);
8db9d77b
ZW		 2443 udelay(150);
2444
5b2adf89 2445 /* Ironlake workaround, enable clock pointer after FDI enable*/
8f5718a6
DV		 2446 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2447 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2448 FDI_RX_PHASE_SYNC_POINTER_EN);
5b2adf89 2449
5eddb70b 2450 reg = FDI_RX_IIR(pipe);
e1a44743 2451 for (tries = 0; tries < 5; tries++) {
5eddb70b 2452 temp = I915_READ(reg);
8db9d77b
ZW		 2453 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2454
2455 if ((temp & FDI_RX_BIT_LOCK)) {
2456 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2457 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2458 break;
2459 }
8db9d77b 2460 }
e1a44743 2461 if (tries == 5)
5eddb70b 2462 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2463
2464 /* Train 2 */
5eddb70b
CW		 2465 reg = FDI_TX_CTL(pipe);
2466 temp = I915_READ(reg);
8db9d77b
ZW		 2467 temp &= ~FDI_LINK_TRAIN_NONE;
2468 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2469 I915_WRITE(reg, temp);
8db9d77b 2470
5eddb70b
CW		 2471 reg = FDI_RX_CTL(pipe);
2472 temp = I915_READ(reg);
8db9d77b
ZW		 2473 temp &= ~FDI_LINK_TRAIN_NONE;
2474 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2475 I915_WRITE(reg, temp);
8db9d77b 2476
5eddb70b
CW		 2477 POSTING_READ(reg);
2478 udelay(150);
8db9d77b 2479
5eddb70b 2480 reg = FDI_RX_IIR(pipe);
e1a44743 2481 for (tries = 0; tries < 5; tries++) {
5eddb70b 2482 temp = I915_READ(reg);
8db9d77b
ZW		 2483 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2484
2485 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2486 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2487 DRM_DEBUG_KMS("FDI train 2 done.\n");
2488 break;
2489 }
8db9d77b 2490 }
e1a44743 2491 if (tries == 5)
5eddb70b 2492 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2493
2494 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2495
8db9d77b
ZW		 2496}
2497
0206e353 2498static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2499 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2500 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2501 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2502 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2503};
2504
2505/* The FDI link training functions for SNB/Cougarpoint. */
2506static void gen6_fdi_link_train(struct drm_crtc *crtc)
2507{
2508 struct drm_device *dev = crtc->dev;
2509 struct drm_i915_private *dev_priv = dev->dev_private;
2510 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2511 int pipe = intel_crtc->pipe;
fa37d39e 2512 u32 reg, temp, i, retry;
8db9d77b 2513
e1a44743
AJ		 2514 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2515 for train result */
5eddb70b
CW		 2516 reg = FDI_RX_IMR(pipe);
2517 temp = I915_READ(reg);
e1a44743
AJ		 2518 temp &= ~FDI_RX_SYMBOL_LOCK;
2519 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2520 I915_WRITE(reg, temp);
2521
2522 POSTING_READ(reg);
e1a44743
AJ		 2523 udelay(150);
2524
8db9d77b 2525 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2526 reg = FDI_TX_CTL(pipe);
2527 temp = I915_READ(reg);
77ffb597
AJ		 2528 temp &= ~(7 << 19);
2529 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2530 temp &= ~FDI_LINK_TRAIN_NONE;
2531 temp |= FDI_LINK_TRAIN_PATTERN_1;
2532 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2533 /* SNB-B */
2534 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2535 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2536
d74cf324
DV		 2537 I915_WRITE(FDI_RX_MISC(pipe),
2538 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2539
5eddb70b
CW		 2540 reg = FDI_RX_CTL(pipe);
2541 temp = I915_READ(reg);
8db9d77b
ZW		 2542 if (HAS_PCH_CPT(dev)) {
2543 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2544 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2545 } else {
2546 temp &= ~FDI_LINK_TRAIN_NONE;
2547 temp |= FDI_LINK_TRAIN_PATTERN_1;
2548 }
5eddb70b
CW		 2549 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2550
2551 POSTING_READ(reg);
8db9d77b
ZW		 2552 udelay(150);
2553
0206e353 2554 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2555 reg = FDI_TX_CTL(pipe);
2556 temp = I915_READ(reg);
8db9d77b
ZW		 2557 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2558 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2559 I915_WRITE(reg, temp);
2560
2561 POSTING_READ(reg);
8db9d77b
ZW		 2562 udelay(500);
2563
fa37d39e
SP		 2564 for (retry = 0; retry < 5; retry++) {
2565 reg = FDI_RX_IIR(pipe);
2566 temp = I915_READ(reg);
2567 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2568 if (temp & FDI_RX_BIT_LOCK) {
2569 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2570 DRM_DEBUG_KMS("FDI train 1 done.\n");
2571 break;
2572 }
2573 udelay(50);
8db9d77b 2574 }
fa37d39e
SP		 2575 if (retry < 5)
2576 break;
8db9d77b
ZW		 2577 }
2578 if (i == 4)
5eddb70b 2579 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2580
2581 /* Train 2 */
5eddb70b
CW		 2582 reg = FDI_TX_CTL(pipe);
2583 temp = I915_READ(reg);
8db9d77b
ZW		 2584 temp &= ~FDI_LINK_TRAIN_NONE;
2585 temp |= FDI_LINK_TRAIN_PATTERN_2;
2586 if (IS_GEN6(dev)) {
2587 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2588 /* SNB-B */
2589 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2590 }
5eddb70b 2591 I915_WRITE(reg, temp);
8db9d77b 2592
5eddb70b
CW		 2593 reg = FDI_RX_CTL(pipe);
2594 temp = I915_READ(reg);
8db9d77b
ZW		 2595 if (HAS_PCH_CPT(dev)) {
2596 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2597 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2598 } else {
2599 temp &= ~FDI_LINK_TRAIN_NONE;
2600 temp |= FDI_LINK_TRAIN_PATTERN_2;
2601 }
5eddb70b
CW		 2602 I915_WRITE(reg, temp);
2603
2604 POSTING_READ(reg);
8db9d77b
ZW		 2605 udelay(150);
2606
0206e353 2607 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2608 reg = FDI_TX_CTL(pipe);
2609 temp = I915_READ(reg);
8db9d77b
ZW		 2610 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2611 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2612 I915_WRITE(reg, temp);
2613
2614 POSTING_READ(reg);
8db9d77b
ZW		 2615 udelay(500);
2616
fa37d39e
SP		 2617 for (retry = 0; retry < 5; retry++) {
2618 reg = FDI_RX_IIR(pipe);
2619 temp = I915_READ(reg);
2620 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2621 if (temp & FDI_RX_SYMBOL_LOCK) {
2622 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2623 DRM_DEBUG_KMS("FDI train 2 done.\n");
2624 break;
2625 }
2626 udelay(50);
8db9d77b 2627 }
fa37d39e
SP		 2628 if (retry < 5)
2629 break;
8db9d77b
ZW		 2630 }
2631 if (i == 4)
5eddb70b 2632 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2633
2634 DRM_DEBUG_KMS("FDI train done.\n");
2635}
2636
357555c0
JB		 2637/* Manual link training for Ivy Bridge A0 parts */
2638static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2639{
2640 struct drm_device *dev = crtc->dev;
2641 struct drm_i915_private *dev_priv = dev->dev_private;
2642 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2643 int pipe = intel_crtc->pipe;
2644 u32 reg, temp, i;
2645
2646 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2647 for train result */
2648 reg = FDI_RX_IMR(pipe);
2649 temp = I915_READ(reg);
2650 temp &= ~FDI_RX_SYMBOL_LOCK;
2651 temp &= ~FDI_RX_BIT_LOCK;
2652 I915_WRITE(reg, temp);
2653
2654 POSTING_READ(reg);
2655 udelay(150);
2656
01a415fd
DV		 2657 DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2658 I915_READ(FDI_RX_IIR(pipe)));
2659
357555c0
JB		 2660 /* enable CPU FDI TX and PCH FDI RX */
2661 reg = FDI_TX_CTL(pipe);
2662 temp = I915_READ(reg);
2663 temp &= ~(7 << 19);
2664 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2665 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2666 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2667 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2668 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2669 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2670 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2671
d74cf324
DV		 2672 I915_WRITE(FDI_RX_MISC(pipe),
2673 FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2674
357555c0
JB		 2675 reg = FDI_RX_CTL(pipe);
2676 temp = I915_READ(reg);
2677 temp &= ~FDI_LINK_TRAIN_AUTO;
2678 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2679 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2680 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2681 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2682
2683 POSTING_READ(reg);
2684 udelay(150);
2685
0206e353 2686 for (i = 0; i < 4; i++) {
357555c0
JB		 2687 reg = FDI_TX_CTL(pipe);
2688 temp = I915_READ(reg);
2689 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2690 temp |= snb_b_fdi_train_param[i];
2691 I915_WRITE(reg, temp);
2692
2693 POSTING_READ(reg);
2694 udelay(500);
2695
2696 reg = FDI_RX_IIR(pipe);
2697 temp = I915_READ(reg);
2698 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2699
2700 if (temp & FDI_RX_BIT_LOCK ||
2701 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2702 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
01a415fd 2703 DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
357555c0
JB		 2704 break;
2705 }
2706 }
2707 if (i == 4)
2708 DRM_ERROR("FDI train 1 fail!\n");
2709
2710 /* Train 2 */
2711 reg = FDI_TX_CTL(pipe);
2712 temp = I915_READ(reg);
2713 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2714 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2715 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2716 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2717 I915_WRITE(reg, temp);
2718
2719 reg = FDI_RX_CTL(pipe);
2720 temp = I915_READ(reg);
2721 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2722 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2723 I915_WRITE(reg, temp);
2724
2725 POSTING_READ(reg);
2726 udelay(150);
2727
0206e353 2728 for (i = 0; i < 4; i++) {
357555c0
JB		 2729 reg = FDI_TX_CTL(pipe);
2730 temp = I915_READ(reg);
2731 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2732 temp |= snb_b_fdi_train_param[i];
2733 I915_WRITE(reg, temp);
2734
2735 POSTING_READ(reg);
2736 udelay(500);
2737
2738 reg = FDI_RX_IIR(pipe);
2739 temp = I915_READ(reg);
2740 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2741
2742 if (temp & FDI_RX_SYMBOL_LOCK) {
2743 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
01a415fd 2744 DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
357555c0
JB		 2745 break;
2746 }
2747 }
2748 if (i == 4)
2749 DRM_ERROR("FDI train 2 fail!\n");
2750
2751 DRM_DEBUG_KMS("FDI train done.\n");
2752}
2753
88cefb6c 2754static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2755{
88cefb6c 2756 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2757 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2758 int pipe = intel_crtc->pipe;
5eddb70b 2759 u32 reg, temp;
79e53945 2760
c64e311e 2761
c98e9dcf 2762 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2763 reg = FDI_RX_CTL(pipe);
2764 temp = I915_READ(reg);
2765 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2766 temp |= (intel_crtc->fdi_lanes - 1) << 19;
dfd07d72 2767 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
5eddb70b
CW		 2768 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2769
2770 POSTING_READ(reg);
c98e9dcf
JB		 2771 udelay(200);
2772
2773 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2774 temp = I915_READ(reg);
2775 I915_WRITE(reg, temp | FDI_PCDCLK);
2776
2777 POSTING_READ(reg);
c98e9dcf
JB		 2778 udelay(200);
2779
20749730
PZ		 2780 /* Enable CPU FDI TX PLL, always on for Ironlake */
2781 reg = FDI_TX_CTL(pipe);
2782 temp = I915_READ(reg);
2783 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2784 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2785
20749730
PZ		 2786 POSTING_READ(reg);
2787 udelay(100);
6be4a607 2788 }
0e23b99d
JB		 2789}
2790
88cefb6c
DV		 2791static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2792{
2793 struct drm_device *dev = intel_crtc->base.dev;
2794 struct drm_i915_private *dev_priv = dev->dev_private;
2795 int pipe = intel_crtc->pipe;
2796 u32 reg, temp;
2797
2798 /* Switch from PCDclk to Rawclk */
2799 reg = FDI_RX_CTL(pipe);
2800 temp = I915_READ(reg);
2801 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2802
2803 /* Disable CPU FDI TX PLL */
2804 reg = FDI_TX_CTL(pipe);
2805 temp = I915_READ(reg);
2806 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2807
2808 POSTING_READ(reg);
2809 udelay(100);
2810
2811 reg = FDI_RX_CTL(pipe);
2812 temp = I915_READ(reg);
2813 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2814
2815 /* Wait for the clocks to turn off. */
2816 POSTING_READ(reg);
2817 udelay(100);
2818}
2819
0fc932b8
JB		 2820static void ironlake_fdi_disable(struct drm_crtc *crtc)
2821{
2822 struct drm_device *dev = crtc->dev;
2823 struct drm_i915_private *dev_priv = dev->dev_private;
2824 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2825 int pipe = intel_crtc->pipe;
2826 u32 reg, temp;
2827
2828 /* disable CPU FDI tx and PCH FDI rx */
2829 reg = FDI_TX_CTL(pipe);
2830 temp = I915_READ(reg);
2831 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2832 POSTING_READ(reg);
2833
2834 reg = FDI_RX_CTL(pipe);
2835 temp = I915_READ(reg);
2836 temp &= ~(0x7 << 16);
dfd07d72 2837 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2838 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2839
2840 POSTING_READ(reg);
2841 udelay(100);
2842
2843 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2844 if (HAS_PCH_IBX(dev)) {
2845 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
6f06ce18 2846 }
0fc932b8
JB		 2847
2848 /* still set train pattern 1 */
2849 reg = FDI_TX_CTL(pipe);
2850 temp = I915_READ(reg);
2851 temp &= ~FDI_LINK_TRAIN_NONE;
2852 temp |= FDI_LINK_TRAIN_PATTERN_1;
2853 I915_WRITE(reg, temp);
2854
2855 reg = FDI_RX_CTL(pipe);
2856 temp = I915_READ(reg);
2857 if (HAS_PCH_CPT(dev)) {
2858 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2859 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2860 } else {
2861 temp &= ~FDI_LINK_TRAIN_NONE;
2862 temp |= FDI_LINK_TRAIN_PATTERN_1;
2863 }
2864 /* BPC in FDI rx is consistent with that in PIPECONF */
2865 temp &= ~(0x07 << 16);
dfd07d72 2866 temp |= (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) << 11;
0fc932b8
JB		 2867 I915_WRITE(reg, temp);
2868
2869 POSTING_READ(reg);
2870 udelay(100);
2871}
2872
5bb61643
CW		 2873static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2874{
2875 struct drm_device *dev = crtc->dev;
2876 struct drm_i915_private *dev_priv = dev->dev_private;
2877 unsigned long flags;
2878 bool pending;
2879
1f83fee0 2880 if (i915_reset_in_progress(&dev_priv->gpu_error))
5bb61643
CW		 2881 return false;
2882
2883 spin_lock_irqsave(&dev->event_lock, flags);
2884 pending = to_intel_crtc(crtc)->unpin_work != NULL;
2885 spin_unlock_irqrestore(&dev->event_lock, flags);
2886
2887 return pending;
2888}
2889
e6c3a2a6
CW		 2890static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2891{
0f91128d 2892 struct drm_device *dev = crtc->dev;
5bb61643 2893 struct drm_i915_private *dev_priv = dev->dev_private;
e6c3a2a6
CW		 2894
2895 if (crtc->fb == NULL)
2896 return;
2897
2c10d571
DV		 2898 WARN_ON(waitqueue_active(&dev_priv->pending_flip_queue));
2899
5bb61643
CW		 2900 wait_event(dev_priv->pending_flip_queue,
2901 !intel_crtc_has_pending_flip(crtc));
2902
0f91128d
CW		 2903 mutex_lock(&dev->struct_mutex);
2904 intel_finish_fb(crtc->fb);
2905 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2906}
2907
fc316cbe 2908static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
040484af
JB		 2909{
2910 struct drm_device *dev = crtc->dev;
228d3e36 2911 struct intel_encoder *intel_encoder;
040484af
JB		 2912
2913 /*
2914 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2915 * must be driven by its own crtc; no sharing is possible.
2916 */
228d3e36 2917 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
228d3e36 2918 switch (intel_encoder->type) {
040484af 2919 case INTEL_OUTPUT_EDP:
228d3e36 2920 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2921 return false;
2922 continue;
2923 }
2924 }
2925
2926 return true;
2927}
2928
fc316cbe
PZ		 2929static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2930{
2931 return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2932}
2933
e615efe4
ED		 2934/* Program iCLKIP clock to the desired frequency */
2935static void lpt_program_iclkip(struct drm_crtc *crtc)
2936{
2937 struct drm_device *dev = crtc->dev;
2938 struct drm_i915_private *dev_priv = dev->dev_private;
2939 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2940 u32 temp;
2941
09153000
DV		 2942 mutex_lock(&dev_priv->dpio_lock);
2943
e615efe4
ED		 2944 /* It is necessary to ungate the pixclk gate prior to programming
2945 * the divisors, and gate it back when it is done.
2946 */
2947 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2948
2949 /* Disable SSCCTL */
2950 intel_sbi_write(dev_priv, SBI_SSCCTL6,
988d6ee8
PZ		 2951 intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK) |
2952 SBI_SSCCTL_DISABLE,
2953 SBI_ICLK);
e615efe4
ED		 2954
2955 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2956 if (crtc->mode.clock == 20000) {
2957 auxdiv = 1;
2958 divsel = 0x41;
2959 phaseinc = 0x20;
2960 } else {
2961 /* The iCLK virtual clock root frequency is in MHz,
2962 * but the crtc->mode.clock in in KHz. To get the divisors,
2963 * it is necessary to divide one by another, so we
2964 * convert the virtual clock precision to KHz here for higher
2965 * precision.
2966 */
2967 u32 iclk_virtual_root_freq = 172800 * 1000;
2968 u32 iclk_pi_range = 64;
2969 u32 desired_divisor, msb_divisor_value, pi_value;
2970
2971 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2972 msb_divisor_value = desired_divisor / iclk_pi_range;
2973 pi_value = desired_divisor % iclk_pi_range;
2974
2975 auxdiv = 0;
2976 divsel = msb_divisor_value - 2;
2977 phaseinc = pi_value;
2978 }
2979
2980 /* This should not happen with any sane values */
2981 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2982 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2983 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2984 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2985
2986 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2987 crtc->mode.clock,
2988 auxdiv,
2989 divsel,
2990 phasedir,
2991 phaseinc);
2992
2993 /* Program SSCDIVINTPHASE6 */
988d6ee8 2994 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, SBI_ICLK);
e615efe4
ED		 2995 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2996 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2997 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2998 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2999 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3000 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
988d6ee8 3001 intel_sbi_write(dev_priv, SBI_SSCDIVINTPHASE6, temp, SBI_ICLK);
e615efe4
ED		 3002
3003 /* Program SSCAUXDIV */
988d6ee8 3004 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK);
e615efe4
ED		 3005 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3006 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
988d6ee8 3007 intel_sbi_write(dev_priv, SBI_SSCAUXDIV6, temp, SBI_ICLK);
e615efe4
ED		 3008
3009 /* Enable modulator and associated divider */
988d6ee8 3010 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK);
e615efe4 3011 temp &= ~SBI_SSCCTL_DISABLE;
988d6ee8 3012 intel_sbi_write(dev_priv, SBI_SSCCTL6, temp, SBI_ICLK);
e615efe4
ED		 3013
3014 /* Wait for initialization time */
3015 udelay(24);
3016
3017 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
09153000
DV		 3018
3019 mutex_unlock(&dev_priv->dpio_lock);
e615efe4
ED		 3020}
3021
f67a559d
JB		 3022/*
3023 * Enable PCH resources required for PCH ports:
3024 * - PCH PLLs
3025 * - FDI training & RX/TX
3026 * - update transcoder timings
3027 * - DP transcoding bits
3028 * - transcoder
3029 */
3030static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3031{
3032 struct drm_device *dev = crtc->dev;
3033 struct drm_i915_private *dev_priv = dev->dev_private;
3034 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3035 int pipe = intel_crtc->pipe;
ee7b9f93 3036 u32 reg, temp;
2c07245f 3037
e7e164db
CW		 3038 assert_transcoder_disabled(dev_priv, pipe);
3039
cd986abb
DV		 3040 /* Write the TU size bits before fdi link training, so that error
3041 * detection works. */
3042 I915_WRITE(FDI_RX_TUSIZE1(pipe),
3043 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3044
c98e9dcf 3045 /* For PCH output, training FDI link */
674cf967 3046 dev_priv->display.fdi_link_train(crtc);
2c07245f 3047
572deb37
DV		 3048 /* XXX: pch pll's can be enabled any time before we enable the PCH
3049 * transcoder, and we actually should do this to not upset any PCH
3050 * transcoder that already use the clock when we share it.
3051 *
3052 * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3053 * unconditionally resets the pll - we need that to have the right LVDS
3054 * enable sequence. */
b6b4e185 3055 ironlake_enable_pch_pll(intel_crtc);
6f13b7b5 3056
303b81e0 3057 if (HAS_PCH_CPT(dev)) {
ee7b9f93 3058 u32 sel;
4b645f14 3059
c98e9dcf 3060 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3061 switch (pipe) {
3062 default:
3063 case 0:
3064 temp |= TRANSA_DPLL_ENABLE;
3065 sel = TRANSA_DPLLB_SEL;
3066 break;
3067 case 1:
3068 temp |= TRANSB_DPLL_ENABLE;
3069 sel = TRANSB_DPLLB_SEL;
3070 break;
3071 case 2:
3072 temp |= TRANSC_DPLL_ENABLE;
3073 sel = TRANSC_DPLLB_SEL;
3074 break;
d64311ab 3075 }
ee7b9f93
JB		 3076 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3077 temp |= sel;
3078 else
3079 temp &= ~sel;
c98e9dcf 3080 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3081 }
5eddb70b 3082
d9b6cb56
JB		 3083 /* set transcoder timing, panel must allow it */
3084 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3085 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3086 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3087 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3088
5eddb70b
CW		 3089 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3090 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3091 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3092 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3093
303b81e0 3094 intel_fdi_normal_train(crtc);
5e84e1a4 3095
c98e9dcf
JB		 3096 /* For PCH DP, enable TRANS_DP_CTL */
3097 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3098 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3099 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
dfd07d72 3100 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPECONF_BPC_MASK) >> 5;
5eddb70b
CW		 3101 reg = TRANS_DP_CTL(pipe);
3102 temp = I915_READ(reg);
3103 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3104 TRANS_DP_SYNC_MASK |
3105 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3106 temp |= (TRANS_DP_OUTPUT_ENABLE |
3107 TRANS_DP_ENH_FRAMING);
9325c9f0 3108 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3109
3110 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3111 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3112 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3113 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3114
3115 switch (intel_trans_dp_port_sel(crtc)) {
3116 case PCH_DP_B:
5eddb70b 3117 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3118 break;
3119 case PCH_DP_C:
5eddb70b 3120 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3121 break;
3122 case PCH_DP_D:
5eddb70b 3123 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3124 break;
3125 default:
e95d41e1 3126 BUG();
32f9d658 3127 }
2c07245f 3128
5eddb70b 3129 I915_WRITE(reg, temp);
6be4a607 3130 }
b52eb4dc 3131
b8a4f404 3132 ironlake_enable_pch_transcoder(dev_priv, pipe);
f67a559d
JB		 3133}
3134
1507e5bd
PZ		 3135static void lpt_pch_enable(struct drm_crtc *crtc)
3136{
3137 struct drm_device *dev = crtc->dev;
3138 struct drm_i915_private *dev_priv = dev->dev_private;
3139 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
daed2dbb 3140 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
1507e5bd 3141
daed2dbb 3142 assert_transcoder_disabled(dev_priv, TRANSCODER_A);
1507e5bd 3143
8c52b5e8 3144 lpt_program_iclkip(crtc);
1507e5bd 3145
0540e488 3146 /* Set transcoder timing. */
daed2dbb
PZ		 3147 I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3148 I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3149 I915_WRITE(_TRANS_HSYNC_A, I915_READ(HSYNC(cpu_transcoder)));
1507e5bd 3150
daed2dbb
PZ		 3151 I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3152 I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3153 I915_WRITE(_TRANS_VSYNC_A, I915_READ(VSYNC(cpu_transcoder)));
3154 I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
1507e5bd 3155
937bb610 3156 lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
f67a559d
JB		 3157}
3158
ee7b9f93
JB		 3159static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3160{
3161 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3162
3163 if (pll == NULL)
3164 return;
3165
3166 if (pll->refcount == 0) {
3167 WARN(1, "bad PCH PLL refcount\n");
3168 return;
3169 }
3170
3171 --pll->refcount;
3172 intel_crtc->pch_pll = NULL;
3173}
3174
3175static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3176{
3177 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3178 struct intel_pch_pll *pll;
3179 int i;
3180
3181 pll = intel_crtc->pch_pll;
3182 if (pll) {
3183 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3184 intel_crtc->base.base.id, pll->pll_reg);
3185 goto prepare;
3186 }
3187
98b6bd99
DV		 3188 if (HAS_PCH_IBX(dev_priv->dev)) {
3189 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3190 i = intel_crtc->pipe;
3191 pll = &dev_priv->pch_plls[i];
3192
3193 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3194 intel_crtc->base.base.id, pll->pll_reg);
3195
3196 goto found;
3197 }
3198
ee7b9f93
JB		 3199 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3200 pll = &dev_priv->pch_plls[i];
3201
3202 /* Only want to check enabled timings first */
3203 if (pll->refcount == 0)
3204 continue;
3205
3206 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3207 fp == I915_READ(pll->fp0_reg)) {
3208 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3209 intel_crtc->base.base.id,
3210 pll->pll_reg, pll->refcount, pll->active);
3211
3212 goto found;
3213 }
3214 }
3215
3216 /* Ok no matching timings, maybe there's a free one? */
3217 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3218 pll = &dev_priv->pch_plls[i];
3219 if (pll->refcount == 0) {
3220 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3221 intel_crtc->base.base.id, pll->pll_reg);
3222 goto found;
3223 }
3224 }
3225
3226 return NULL;
3227
3228found:
3229 intel_crtc->pch_pll = pll;
3230 pll->refcount++;
3231 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3232prepare: /* separate function? */
3233 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3234
e04c7350
CW		 3235 /* Wait for the clocks to stabilize before rewriting the regs */
3236 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3237 POSTING_READ(pll->pll_reg);
3238 udelay(150);
e04c7350
CW		 3239
3240 I915_WRITE(pll->fp0_reg, fp);
3241 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3242 pll->on = false;
3243 return pll;
3244}
3245
d4270e57
JB		 3246void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3247{
3248 struct drm_i915_private *dev_priv = dev->dev_private;
23670b32 3249 int dslreg = PIPEDSL(pipe);
d4270e57
JB		 3250 u32 temp;
3251
3252 temp = I915_READ(dslreg);
3253 udelay(500);
3254 if (wait_for(I915_READ(dslreg) != temp, 5)) {
d4270e57
JB		 3255 if (wait_for(I915_READ(dslreg) != temp, 5))
3256 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3257 }
3258}
3259
f67a559d
JB		 3260static void ironlake_crtc_enable(struct drm_crtc *crtc)
3261{
3262 struct drm_device *dev = crtc->dev;
3263 struct drm_i915_private *dev_priv = dev->dev_private;
3264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3265 struct intel_encoder *encoder;
f67a559d
JB		 3266 int pipe = intel_crtc->pipe;
3267 int plane = intel_crtc->plane;
3268 u32 temp;
3269 bool is_pch_port;
3270
08a48469
DV		 3271 WARN_ON(!crtc->enabled);
3272
f67a559d
JB		 3273 if (intel_crtc->active)
3274 return;
3275
3276 intel_crtc->active = true;
3277 intel_update_watermarks(dev);
3278
3279 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3280 temp = I915_READ(PCH_LVDS);
3281 if ((temp & LVDS_PORT_EN) == 0)
3282 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3283 }
3284
fc316cbe 3285 is_pch_port = ironlake_crtc_driving_pch(crtc);
f67a559d 3286
46b6f814 3287 if (is_pch_port) {
fff367c7
DV		 3288 /* Note: FDI PLL enabling _must_ be done before we enable the
3289 * cpu pipes, hence this is separate from all the other fdi/pch
3290 * enabling. */
88cefb6c 3291 ironlake_fdi_pll_enable(intel_crtc);
46b6f814
DV		 3292 } else {
3293 assert_fdi_tx_disabled(dev_priv, pipe);
3294 assert_fdi_rx_disabled(dev_priv, pipe);
3295 }
f67a559d 3296
bf49ec8c
DV		 3297 for_each_encoder_on_crtc(dev, crtc, encoder)
3298 if (encoder->pre_enable)
3299 encoder->pre_enable(encoder);
f67a559d
JB		 3300
3301 /* Enable panel fitting for LVDS */
3302 if (dev_priv->pch_pf_size &&
547dc041
JN		 3303 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3304 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
f67a559d
JB		 3305 /* Force use of hard-coded filter coefficients
3306 * as some pre-programmed values are broken,
3307 * e.g. x201.
3308 */
13888d78
PZ		 3309 if (IS_IVYBRIDGE(dev))
3310 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3311 PF_PIPE_SEL_IVB(pipe));
3312 else
3313 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
9db4a9c7
JB		 3314 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3315 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3316 }
3317
9c54c0dd
JB		 3318 /*
3319 * On ILK+ LUT must be loaded before the pipe is running but with
3320 * clocks enabled
3321 */
3322 intel_crtc_load_lut(crtc);
3323
f67a559d
JB		 3324 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3325 intel_enable_plane(dev_priv, plane, pipe);
3326
3327 if (is_pch_port)
3328 ironlake_pch_enable(crtc);
c98e9dcf 3329
d1ebd816 3330 mutex_lock(&dev->struct_mutex);
bed4a673 3331 intel_update_fbc(dev);
d1ebd816
BW		 3332 mutex_unlock(&dev->struct_mutex);
3333
6b383a7f 3334 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3335
fa5c73b1
DV		 3336 for_each_encoder_on_crtc(dev, crtc, encoder)
3337 encoder->enable(encoder);
61b77ddd
DV		 3338
3339 if (HAS_PCH_CPT(dev))
3340 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6ce94100
DV		 3341
3342 /*
3343 * There seems to be a race in PCH platform hw (at least on some
3344 * outputs) where an enabled pipe still completes any pageflip right
3345 * away (as if the pipe is off) instead of waiting for vblank. As soon
3346 * as the first vblank happend, everything works as expected. Hence just
3347 * wait for one vblank before returning to avoid strange things
3348 * happening.
3349 */
3350 intel_wait_for_vblank(dev, intel_crtc->pipe);
6be4a607
JB		 3351}
3352
4f771f10
PZ		 3353static void haswell_crtc_enable(struct drm_crtc *crtc)
3354{
3355 struct drm_device *dev = crtc->dev;
3356 struct drm_i915_private *dev_priv = dev->dev_private;
3357 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3358 struct intel_encoder *encoder;
3359 int pipe = intel_crtc->pipe;
3360 int plane = intel_crtc->plane;
4f771f10
PZ		 3361 bool is_pch_port;
3362
3363 WARN_ON(!crtc->enabled);
3364
3365 if (intel_crtc->active)
3366 return;
3367
3368 intel_crtc->active = true;
3369 intel_update_watermarks(dev);
3370
fc316cbe 3371 is_pch_port = haswell_crtc_driving_pch(crtc);
4f771f10 3372
83616634 3373 if (is_pch_port)
04945641 3374 dev_priv->display.fdi_link_train(crtc);
4f771f10
PZ		 3375
3376 for_each_encoder_on_crtc(dev, crtc, encoder)
3377 if (encoder->pre_enable)
3378 encoder->pre_enable(encoder);
3379
1f544388 3380 intel_ddi_enable_pipe_clock(intel_crtc);
4f771f10 3381
1f544388 3382 /* Enable panel fitting for eDP */
547dc041
JN		 3383 if (dev_priv->pch_pf_size &&
3384 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4f771f10
PZ		 3385 /* Force use of hard-coded filter coefficients
3386 * as some pre-programmed values are broken,
3387 * e.g. x201.
3388 */
54075a7d
PZ		 3389 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3390 PF_PIPE_SEL_IVB(pipe));
4f771f10
PZ		 3391 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3392 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3393 }
3394
3395 /*
3396 * On ILK+ LUT must be loaded before the pipe is running but with
3397 * clocks enabled
3398 */
3399 intel_crtc_load_lut(crtc);
3400
1f544388
PZ		 3401 intel_ddi_set_pipe_settings(crtc);
3402 intel_ddi_enable_pipe_func(crtc);
4f771f10
PZ		 3403
3404 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3405 intel_enable_plane(dev_priv, plane, pipe);
3406
3407 if (is_pch_port)
1507e5bd 3408 lpt_pch_enable(crtc);
4f771f10
PZ		 3409
3410 mutex_lock(&dev->struct_mutex);
3411 intel_update_fbc(dev);
3412 mutex_unlock(&dev->struct_mutex);
3413
3414 intel_crtc_update_cursor(crtc, true);
3415
3416 for_each_encoder_on_crtc(dev, crtc, encoder)
3417 encoder->enable(encoder);
3418
4f771f10
PZ		 3419 /*
3420 * There seems to be a race in PCH platform hw (at least on some
3421 * outputs) where an enabled pipe still completes any pageflip right
3422 * away (as if the pipe is off) instead of waiting for vblank. As soon
3423 * as the first vblank happend, everything works as expected. Hence just
3424 * wait for one vblank before returning to avoid strange things
3425 * happening.
3426 */
3427 intel_wait_for_vblank(dev, intel_crtc->pipe);
3428}
3429
6be4a607
JB		 3430static void ironlake_crtc_disable(struct drm_crtc *crtc)
3431{
3432 struct drm_device *dev = crtc->dev;
3433 struct drm_i915_private *dev_priv = dev->dev_private;
3434 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3435 struct intel_encoder *encoder;
6be4a607
JB		 3436 int pipe = intel_crtc->pipe;
3437 int plane = intel_crtc->plane;
5eddb70b 3438 u32 reg, temp;
b52eb4dc 3439
ef9c3aee 3440
f7abfe8b
CW		 3441 if (!intel_crtc->active)
3442 return;
3443
ea9d758d
DV		 3444 for_each_encoder_on_crtc(dev, crtc, encoder)
3445 encoder->disable(encoder);
3446
e6c3a2a6 3447 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3448 drm_vblank_off(dev, pipe);
6b383a7f 3449 intel_crtc_update_cursor(crtc, false);
5eddb70b 3450
b24e7179 3451 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3452
973d04f9
CW		 3453 if (dev_priv->cfb_plane == plane)
3454 intel_disable_fbc(dev);
2c07245f 3455
b24e7179 3456 intel_disable_pipe(dev_priv, pipe);
32f9d658 3457
6be4a607 3458 /* Disable PF */
9db4a9c7
JB		 3459 I915_WRITE(PF_CTL(pipe), 0);
3460 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3461
bf49ec8c
DV		 3462 for_each_encoder_on_crtc(dev, crtc, encoder)
3463 if (encoder->post_disable)
3464 encoder->post_disable(encoder);
2c07245f 3465
0fc932b8 3466 ironlake_fdi_disable(crtc);
249c0e64 3467
b8a4f404 3468 ironlake_disable_pch_transcoder(dev_priv, pipe);
913d8d11 3469
6be4a607
JB		 3470 if (HAS_PCH_CPT(dev)) {
3471 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3472 reg = TRANS_DP_CTL(pipe);
3473 temp = I915_READ(reg);
3474 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3475 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3476 I915_WRITE(reg, temp);
6be4a607
JB		 3477
3478 /* disable DPLL_SEL */
3479 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3480 switch (pipe) {
3481 case 0:
d64311ab 3482 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3483 break;
3484 case 1:
6be4a607 3485 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3486 break;
3487 case 2:
4b645f14 3488 /* C shares PLL A or B */
d64311ab 3489 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3490 break;
3491 default:
3492 BUG(); /* wtf */
3493 }
6be4a607 3494 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3495 }
e3421a18 3496
6be4a607 3497 /* disable PCH DPLL */
ee7b9f93 3498 intel_disable_pch_pll(intel_crtc);
8db9d77b 3499
88cefb6c 3500 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3501
f7abfe8b 3502 intel_crtc->active = false;
6b383a7f 3503 intel_update_watermarks(dev);
d1ebd816
BW		 3504
3505 mutex_lock(&dev->struct_mutex);
6b383a7f 3506 intel_update_fbc(dev);
d1ebd816 3507 mutex_unlock(&dev->struct_mutex);
6be4a607 3508}
1b3c7a47 3509
4f771f10 3510static void haswell_crtc_disable(struct drm_crtc *crtc)
ee7b9f93 3511{
4f771f10
PZ		 3512 struct drm_device *dev = crtc->dev;
3513 struct drm_i915_private *dev_priv = dev->dev_private;
ee7b9f93 3514 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4f771f10
PZ		 3515 struct intel_encoder *encoder;
3516 int pipe = intel_crtc->pipe;
3517 int plane = intel_crtc->plane;
ad80a810 3518 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
83616634 3519 bool is_pch_port;
ee7b9f93 3520
4f771f10
PZ		 3521 if (!intel_crtc->active)
3522 return;
3523
83616634
PZ		 3524 is_pch_port = haswell_crtc_driving_pch(crtc);
3525
4f771f10
PZ		 3526 for_each_encoder_on_crtc(dev, crtc, encoder)
3527 encoder->disable(encoder);
3528
3529 intel_crtc_wait_for_pending_flips(crtc);
3530 drm_vblank_off(dev, pipe);
3531 intel_crtc_update_cursor(crtc, false);
3532
3533 intel_disable_plane(dev_priv, plane, pipe);
3534
3535 if (dev_priv->cfb_plane == plane)
3536 intel_disable_fbc(dev);
3537
3538 intel_disable_pipe(dev_priv, pipe);
3539
ad80a810 3540 intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
4f771f10
PZ		 3541
3542 /* Disable PF */
3543 I915_WRITE(PF_CTL(pipe), 0);
3544 I915_WRITE(PF_WIN_SZ(pipe), 0);
3545
1f544388 3546 intel_ddi_disable_pipe_clock(intel_crtc);
4f771f10
PZ		 3547
3548 for_each_encoder_on_crtc(dev, crtc, encoder)
3549 if (encoder->post_disable)
3550 encoder->post_disable(encoder);
3551
83616634 3552 if (is_pch_port) {
ab4d966c 3553 lpt_disable_pch_transcoder(dev_priv);
1ad960f2 3554 intel_ddi_fdi_disable(crtc);
83616634 3555 }
4f771f10
PZ		 3556
3557 intel_crtc->active = false;
3558 intel_update_watermarks(dev);
3559
3560 mutex_lock(&dev->struct_mutex);
3561 intel_update_fbc(dev);
3562 mutex_unlock(&dev->struct_mutex);
3563}
3564
ee7b9f93
JB		 3565static void ironlake_crtc_off(struct drm_crtc *crtc)
3566{
3567 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3568 intel_put_pch_pll(intel_crtc);
3569}
3570
6441ab5f
PZ		 3571static void haswell_crtc_off(struct drm_crtc *crtc)
3572{
a5c961d1
PZ		 3573 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3574
3575 /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3576 * start using it. */
1a240d4d 3577 intel_crtc->cpu_transcoder = (enum transcoder) intel_crtc->pipe;
a5c961d1 3578
6441ab5f
PZ		 3579 intel_ddi_put_crtc_pll(crtc);
3580}
3581
02e792fb
DV		 3582static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3583{
02e792fb 3584 if (!enable && intel_crtc->overlay) {
23f09ce3 3585 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3586 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3587
23f09ce3 3588 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3589 dev_priv->mm.interruptible = false;
3590 (void) intel_overlay_switch_off(intel_crtc->overlay);
3591 dev_priv->mm.interruptible = true;
23f09ce3 3592 mutex_unlock(&dev->struct_mutex);
02e792fb 3593 }
02e792fb 3594
5dcdbcb0
CW		 3595 /* Let userspace switch the overlay on again. In most cases userspace
3596 * has to recompute where to put it anyway.
3597 */
02e792fb
DV		 3598}
3599
0b8765c6 3600static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3601{
3602 struct drm_device *dev = crtc->dev;
79e53945
JB		 3603 struct drm_i915_private *dev_priv = dev->dev_private;
3604 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3605 struct intel_encoder *encoder;
79e53945 3606 int pipe = intel_crtc->pipe;
80824003 3607 int plane = intel_crtc->plane;
79e53945 3608
08a48469
DV		 3609 WARN_ON(!crtc->enabled);
3610
f7abfe8b
CW		 3611 if (intel_crtc->active)
3612 return;
3613
3614 intel_crtc->active = true;
6b383a7f
CW		 3615 intel_update_watermarks(dev);
3616
63d7bbe9 3617 intel_enable_pll(dev_priv, pipe);
040484af 3618 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3619 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3620
0b8765c6 3621 intel_crtc_load_lut(crtc);
bed4a673 3622 intel_update_fbc(dev);
79e53945 3623
0b8765c6
JB		 3624 /* Give the overlay scaler a chance to enable if it's on this pipe */
3625 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3626 intel_crtc_update_cursor(crtc, true);
ef9c3aee 3627
fa5c73b1
DV		 3628 for_each_encoder_on_crtc(dev, crtc, encoder)
3629 encoder->enable(encoder);
0b8765c6 3630}
79e53945 3631
0b8765c6
JB		 3632static void i9xx_crtc_disable(struct drm_crtc *crtc)
3633{
3634 struct drm_device *dev = crtc->dev;
3635 struct drm_i915_private *dev_priv = dev->dev_private;
3636 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3637 struct intel_encoder *encoder;
0b8765c6
JB		 3638 int pipe = intel_crtc->pipe;
3639 int plane = intel_crtc->plane;
b690e96c 3640
ef9c3aee 3641
f7abfe8b
CW		 3642 if (!intel_crtc->active)
3643 return;
3644
ea9d758d
DV		 3645 for_each_encoder_on_crtc(dev, crtc, encoder)
3646 encoder->disable(encoder);
3647
0b8765c6 3648 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3649 intel_crtc_wait_for_pending_flips(crtc);
3650 drm_vblank_off(dev, pipe);
0b8765c6 3651 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3652 intel_crtc_update_cursor(crtc, false);
0b8765c6 3653
973d04f9
CW		 3654 if (dev_priv->cfb_plane == plane)
3655 intel_disable_fbc(dev);
79e53945 3656
b24e7179 3657 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3658 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3659 intel_disable_pll(dev_priv, pipe);
0b8765c6 3660
f7abfe8b 3661 intel_crtc->active = false;
6b383a7f
CW		 3662 intel_update_fbc(dev);
3663 intel_update_watermarks(dev);
0b8765c6
JB		 3664}
3665
ee7b9f93
JB		 3666static void i9xx_crtc_off(struct drm_crtc *crtc)
3667{
3668}
3669
976f8a20
DV		 3670static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3671 bool enabled)
2c07245f
ZW		 3672{
3673 struct drm_device *dev = crtc->dev;
3674 struct drm_i915_master_private *master_priv;
3675 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3676 int pipe = intel_crtc->pipe;
79e53945
JB		 3677
3678 if (!dev->primary->master)
3679 return;
3680
3681 master_priv = dev->primary->master->driver_priv;
3682 if (!master_priv->sarea_priv)
3683 return;
3684
79e53945
JB		 3685 switch (pipe) {
3686 case 0:
3687 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3688 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3689 break;
3690 case 1:
3691 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3692 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3693 break;
3694 default:
9db4a9c7 3695 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3696 break;
3697 }
79e53945
JB		 3698}
3699
976f8a20
DV		 3700/**
3701 * Sets the power management mode of the pipe and plane.
3702 */
3703void intel_crtc_update_dpms(struct drm_crtc *crtc)
3704{
3705 struct drm_device *dev = crtc->dev;
3706 struct drm_i915_private *dev_priv = dev->dev_private;
3707 struct intel_encoder *intel_encoder;
3708 bool enable = false;
3709
3710 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3711 enable |= intel_encoder->connectors_active;
3712
3713 if (enable)
3714 dev_priv->display.crtc_enable(crtc);
3715 else
3716 dev_priv->display.crtc_disable(crtc);
3717
3718 intel_crtc_update_sarea(crtc, enable);
3719}
3720
3721static void intel_crtc_noop(struct drm_crtc *crtc)
3722{
3723}
3724
cdd59983
CW		 3725static void intel_crtc_disable(struct drm_crtc *crtc)
3726{
cdd59983 3727 struct drm_device *dev = crtc->dev;
976f8a20 3728 struct drm_connector *connector;
ee7b9f93 3729 struct drm_i915_private *dev_priv = dev->dev_private;
7b9f35a6 3730 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
cdd59983 3731
976f8a20
DV		 3732 /* crtc should still be enabled when we disable it. */
3733 WARN_ON(!crtc->enabled);
3734
7b9f35a6 3735 intel_crtc->eld_vld = false;
976f8a20
DV		 3736 dev_priv->display.crtc_disable(crtc);
3737 intel_crtc_update_sarea(crtc, false);
ee7b9f93
JB		 3738 dev_priv->display.off(crtc);
3739
931872fc
CW		 3740 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3741 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3742
3743 if (crtc->fb) {
3744 mutex_lock(&dev->struct_mutex);
1690e1eb 3745 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983 3746 mutex_unlock(&dev->struct_mutex);
976f8a20
DV		 3747 crtc->fb = NULL;
3748 }
3749
3750 /* Update computed state. */
3751 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3752 if (!connector->encoder || !connector->encoder->crtc)
3753 continue;
3754
3755 if (connector->encoder->crtc != crtc)
3756 continue;
3757
3758 connector->dpms = DRM_MODE_DPMS_OFF;
3759 to_intel_encoder(connector->encoder)->connectors_active = false;
cdd59983
CW		 3760 }
3761}
3762
a261b246 3763void intel_modeset_disable(struct drm_device *dev)
79e53945 3764{
a261b246
DV		 3765 struct drm_crtc *crtc;
3766
3767 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3768 if (crtc->enabled)
3769 intel_crtc_disable(crtc);
3770 }
79e53945
JB		 3771}
3772
1f703855 3773void intel_encoder_noop(struct drm_encoder *encoder)
79e53945 3774{
7e7d76c3
JB		 3775}
3776
ea5b213a 3777void intel_encoder_destroy(struct drm_encoder *encoder)
7e7d76c3 3778{
4ef69c7a 3779 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3780
ea5b213a
CW		 3781 drm_encoder_cleanup(encoder);
3782 kfree(intel_encoder);
7e7d76c3
JB		 3783}
3784
5ab432ef
DV		 3785/* Simple dpms helper for encodres with just one connector, no cloning and only
3786 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3787 * state of the entire output pipe. */
3788void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
7e7d76c3 3789{
5ab432ef
DV		 3790 if (mode == DRM_MODE_DPMS_ON) {
3791 encoder->connectors_active = true;
3792
b2cabb0e 3793 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3794 } else {
3795 encoder->connectors_active = false;
3796
b2cabb0e 3797 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef 3798 }
79e53945
JB		 3799}
3800
0a91ca29
DV		 3801/* Cross check the actual hw state with our own modeset state tracking (and it's
3802 * internal consistency). */
b980514c 3803static void intel_connector_check_state(struct intel_connector *connector)
79e53945 3804{
0a91ca29
DV		 3805 if (connector->get_hw_state(connector)) {
3806 struct intel_encoder *encoder = connector->encoder;
3807 struct drm_crtc *crtc;
3808 bool encoder_enabled;
3809 enum pipe pipe;
3810
3811 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3812 connector->base.base.id,
3813 drm_get_connector_name(&connector->base));
3814
3815 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3816 "wrong connector dpms state\n");
3817 WARN(connector->base.encoder != &encoder->base,
3818 "active connector not linked to encoder\n");
3819 WARN(!encoder->connectors_active,
3820 "encoder->connectors_active not set\n");
3821
3822 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3823 WARN(!encoder_enabled, "encoder not enabled\n");
3824 if (WARN_ON(!encoder->base.crtc))
3825 return;
3826
3827 crtc = encoder->base.crtc;
3828
3829 WARN(!crtc->enabled, "crtc not enabled\n");
3830 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3831 WARN(pipe != to_intel_crtc(crtc)->pipe,
3832 "encoder active on the wrong pipe\n");
3833 }
79e53945
JB		 3834}
3835
5ab432ef
DV		 3836/* Even simpler default implementation, if there's really no special case to
3837 * consider. */
3838void intel_connector_dpms(struct drm_connector *connector, int mode)
79e53945 3839{
5ab432ef 3840 struct intel_encoder *encoder = intel_attached_encoder(connector);
d4270e57 3841
5ab432ef
DV		 3842 /* All the simple cases only support two dpms states. */
3843 if (mode != DRM_MODE_DPMS_ON)
3844 mode = DRM_MODE_DPMS_OFF;
d4270e57 3845
5ab432ef
DV		 3846 if (mode == connector->dpms)
3847 return;
3848
3849 connector->dpms = mode;
3850
3851 /* Only need to change hw state when actually enabled */
3852 if (encoder->base.crtc)
3853 intel_encoder_dpms(encoder, mode);
3854 else
8af6cf88 3855 WARN_ON(encoder->connectors_active != false);
0a91ca29 3856
b980514c 3857 intel_modeset_check_state(connector->dev);
79e53945
JB		 3858}
3859
f0947c37
DV		 3860/* Simple connector->get_hw_state implementation for encoders that support only
3861 * one connector and no cloning and hence the encoder state determines the state
3862 * of the connector. */
3863bool intel_connector_get_hw_state(struct intel_connector *connector)
ea5b213a 3864{
24929352 3865 enum pipe pipe = 0;
f0947c37 3866 struct intel_encoder *encoder = connector->encoder;
ea5b213a 3867
f0947c37 3868 return encoder->get_hw_state(encoder, &pipe);
ea5b213a
CW		 3869}
3870
79e53945 3871static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3872 const struct drm_display_mode *mode,
79e53945
JB		 3873 struct drm_display_mode *adjusted_mode)
3874{
2c07245f 3875 struct drm_device *dev = crtc->dev;
89749350 3876
bad720ff 3877 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3878 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3879 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3880 return false;
2c07245f 3881 }
89749350 3882
f9bef081
DV		 3883 /* All interlaced capable intel hw wants timings in frames. Note though
3884 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3885 * timings, so we need to be careful not to clobber these.*/
3886 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3887 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3888
44f46b42
CW		 3889 /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3890 * with a hsync front porch of 0.
3891 */
3892 if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3893 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3894 return false;
3895
79e53945
JB		 3896 return true;
3897}
3898
25eb05fc
JB		 3899static int valleyview_get_display_clock_speed(struct drm_device *dev)
3900{
3901 return 400000; /* FIXME */
3902}
3903
e70236a8
JB		 3904static int i945_get_display_clock_speed(struct drm_device *dev)
3905{
3906 return 400000;
3907}
79e53945 3908
e70236a8 3909static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3910{
e70236a8
JB		 3911 return 333000;
3912}
79e53945 3913
e70236a8
JB		 3914static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3915{
3916 return 200000;
3917}
79e53945 3918
e70236a8
JB		 3919static int i915gm_get_display_clock_speed(struct drm_device *dev)
3920{
3921 u16 gcfgc = 0;
79e53945 3922
e70236a8
JB		 3923 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3924
3925 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3926 return 133000;
3927 else {
3928 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3929 case GC_DISPLAY_CLOCK_333_MHZ:
3930 return 333000;
3931 default:
3932 case GC_DISPLAY_CLOCK_190_200_MHZ:
3933 return 190000;
79e53945 3934 }
e70236a8
JB		 3935 }
3936}
3937
3938static int i865_get_display_clock_speed(struct drm_device *dev)
3939{
3940 return 266000;
3941}
3942
3943static int i855_get_display_clock_speed(struct drm_device *dev)
3944{
3945 u16 hpllcc = 0;
3946 /* Assume that the hardware is in the high speed state. This
3947 * should be the default.
3948 */
3949 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3950 case GC_CLOCK_133_200:
3951 case GC_CLOCK_100_200:
3952 return 200000;
3953 case GC_CLOCK_166_250:
3954 return 250000;
3955 case GC_CLOCK_100_133:
79e53945 3956 return 133000;
e70236a8 3957 }
79e53945 3958
e70236a8
JB		 3959 /* Shouldn't happen */
3960 return 0;
3961}
79e53945 3962
e70236a8
JB		 3963static int i830_get_display_clock_speed(struct drm_device *dev)
3964{
3965 return 133000;
79e53945
JB		 3966}
3967
2c07245f 3968static void
e69d0bc1 3969intel_reduce_ratio(uint32_t *num, uint32_t *den)
2c07245f
ZW		 3970{
3971 while (*num > 0xffffff || *den > 0xffffff) {
3972 *num >>= 1;
3973 *den >>= 1;
3974 }
3975}
3976
e69d0bc1
DV		 3977void
3978intel_link_compute_m_n(int bits_per_pixel, int nlanes,
3979 int pixel_clock, int link_clock,
3980 struct intel_link_m_n *m_n)
2c07245f 3981{
e69d0bc1 3982 m_n->tu = 64;
22ed1113
CW		 3983 m_n->gmch_m = bits_per_pixel * pixel_clock;
3984 m_n->gmch_n = link_clock * nlanes * 8;
e69d0bc1 3985 intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
22ed1113
CW		 3986 m_n->link_m = pixel_clock;
3987 m_n->link_n = link_clock;
e69d0bc1 3988 intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
2c07245f
ZW		 3989}
3990
a7615030
CW		 3991static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3992{
72bbe58c
KP		 3993 if (i915_panel_use_ssc >= 0)
3994 return i915_panel_use_ssc != 0;
3995 return dev_priv->lvds_use_ssc
435793df 3996 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3997}
3998
5a354204
JB		 3999/**
4000 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4001 * @crtc: CRTC structure
3b5c78a3 4002 * @mode: requested mode
5a354204
JB		 4003 *
4004 * A pipe may be connected to one or more outputs. Based on the depth of the
4005 * attached framebuffer, choose a good color depth to use on the pipe.
4006 *
4007 * If possible, match the pipe depth to the fb depth. In some cases, this
4008 * isn't ideal, because the connected output supports a lesser or restricted
4009 * set of depths. Resolve that here:
4010 * LVDS typically supports only 6bpc, so clamp down in that case
4011 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4012 * Displays may support a restricted set as well, check EDID and clamp as
4013 * appropriate.
3b5c78a3 4014 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4015 *
4016 * RETURNS:
4017 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4018 * true if they don't match).
4019 */
4020static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 4021 struct drm_framebuffer *fb,
3b5c78a3
AJ		 4022 unsigned int *pipe_bpp,
4023 struct drm_display_mode *mode)
5a354204
JB		 4024{
4025 struct drm_device *dev = crtc->dev;
4026 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 4027 struct drm_connector *connector;
6c2b7c12 4028 struct intel_encoder *intel_encoder;
5a354204
JB		 4029 unsigned int display_bpc = UINT_MAX, bpc;
4030
4031 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 4032 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 4033
4034 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4035 unsigned int lvds_bpc;
4036
4037 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4038 LVDS_A3_POWER_UP)
4039 lvds_bpc = 8;
4040 else
4041 lvds_bpc = 6;
4042
4043 if (lvds_bpc < display_bpc) {
82820490 4044 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4045 display_bpc = lvds_bpc;
4046 }
4047 continue;
4048 }
4049
5a354204
JB		 4050 /* Not one of the known troublemakers, check the EDID */
4051 list_for_each_entry(connector, &dev->mode_config.connector_list,
4052 head) {
6c2b7c12 4053 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 4054 continue;
4055
62ac41a6
JB		 4056 /* Don't use an invalid EDID bpc value */
4057 if (connector->display_info.bpc &&
4058 connector->display_info.bpc < display_bpc) {
82820490 4059 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4060 display_bpc = connector->display_info.bpc;
4061 }
4062 }
4063
2f4f649a
JN		 4064 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4065 /* Use VBT settings if we have an eDP panel */
4066 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4067
9a30a61f 4068 if (edp_bpc && edp_bpc < display_bpc) {
2f4f649a
JN		 4069 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
4070 display_bpc = edp_bpc;
4071 }
4072 continue;
4073 }
4074
5a354204
JB		 4075 /*
4076 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4077 * through, clamp it down. (Note: >12bpc will be caught below.)
4078 */
4079 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4080 if (display_bpc > 8 && display_bpc < 12) {
82820490 4081 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4082 display_bpc = 12;
4083 } else {
82820490 4084 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4085 display_bpc = 8;
4086 }
4087 }
4088 }
4089
3b5c78a3
AJ		 4090 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4091 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4092 display_bpc = 6;
4093 }
4094
5a354204
JB		 4095 /*
4096 * We could just drive the pipe at the highest bpc all the time and
4097 * enable dithering as needed, but that costs bandwidth. So choose
4098 * the minimum value that expresses the full color range of the fb but
4099 * also stays within the max display bpc discovered above.
4100 */
4101
94352cf9 4102 switch (fb->depth) {
5a354204
JB		 4103 case 8:
4104 bpc = 8; /* since we go through a colormap */
4105 break;
4106 case 15:
4107 case 16:
4108 bpc = 6; /* min is 18bpp */
4109 break;
4110 case 24:
578393cd 4111 bpc = 8;
5a354204
JB		 4112 break;
4113 case 30:
578393cd 4114 bpc = 10;
5a354204
JB		 4115 break;
4116 case 48:
578393cd 4117 bpc = 12;
5a354204
JB		 4118 break;
4119 default:
4120 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4121 bpc = min((unsigned int)8, display_bpc);
4122 break;
4123 }
4124
578393cd
KP		 4125 display_bpc = min(display_bpc, bpc);
4126
82820490
AJ		 4127 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4128 bpc, display_bpc);
5a354204 4129
578393cd 4130 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4131
4132 return display_bpc != bpc;
4133}
4134
a0c4da24
JB		 4135static int vlv_get_refclk(struct drm_crtc *crtc)
4136{
4137 struct drm_device *dev = crtc->dev;
4138 struct drm_i915_private *dev_priv = dev->dev_private;
4139 int refclk = 27000; /* for DP & HDMI */
4140
4141 return 100000; /* only one validated so far */
4142
4143 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4144 refclk = 96000;
4145 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4146 if (intel_panel_use_ssc(dev_priv))
4147 refclk = 100000;
4148 else
4149 refclk = 96000;
4150 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4151 refclk = 100000;
4152 }
4153
4154 return refclk;
4155}
4156
c65d77d8
JB		 4157static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4158{
4159 struct drm_device *dev = crtc->dev;
4160 struct drm_i915_private *dev_priv = dev->dev_private;
4161 int refclk;
4162
a0c4da24
JB		 4163 if (IS_VALLEYVIEW(dev)) {
4164 refclk = vlv_get_refclk(crtc);
4165 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 4166 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4167 refclk = dev_priv->lvds_ssc_freq * 1000;
4168 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4169 refclk / 1000);
4170 } else if (!IS_GEN2(dev)) {
4171 refclk = 96000;
4172 } else {
4173 refclk = 48000;
4174 }
4175
4176 return refclk;
4177}
4178
4179static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4180 intel_clock_t *clock)
4181{
4182 /* SDVO TV has fixed PLL values depend on its clock range,
4183 this mirrors vbios setting. */
4184 if (adjusted_mode->clock >= 100000
4185 && adjusted_mode->clock < 140500) {
4186 clock->p1 = 2;
4187 clock->p2 = 10;
4188 clock->n = 3;
4189 clock->m1 = 16;
4190 clock->m2 = 8;
4191 } else if (adjusted_mode->clock >= 140500
4192 && adjusted_mode->clock <= 200000) {
4193 clock->p1 = 1;
4194 clock->p2 = 10;
4195 clock->n = 6;
4196 clock->m1 = 12;
4197 clock->m2 = 8;
4198 }
4199}
4200
a7516a05
JB		 4201static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4202 intel_clock_t *clock,
4203 intel_clock_t *reduced_clock)
4204{
4205 struct drm_device *dev = crtc->dev;
4206 struct drm_i915_private *dev_priv = dev->dev_private;
4207 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4208 int pipe = intel_crtc->pipe;
4209 u32 fp, fp2 = 0;
4210
4211 if (IS_PINEVIEW(dev)) {
4212 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4213 if (reduced_clock)
4214 fp2 = (1 << reduced_clock->n) << 16 |
4215 reduced_clock->m1 << 8 | reduced_clock->m2;
4216 } else {
4217 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4218 if (reduced_clock)
4219 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4220 reduced_clock->m2;
4221 }
4222
4223 I915_WRITE(FP0(pipe), fp);
4224
4225 intel_crtc->lowfreq_avail = false;
4226 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4227 reduced_clock && i915_powersave) {
4228 I915_WRITE(FP1(pipe), fp2);
4229 intel_crtc->lowfreq_avail = true;
4230 } else {
4231 I915_WRITE(FP1(pipe), fp);
4232 }
4233}
4234
a0c4da24
JB		 4235static void vlv_update_pll(struct drm_crtc *crtc,
4236 struct drm_display_mode *mode,
4237 struct drm_display_mode *adjusted_mode,
4238 intel_clock_t *clock, intel_clock_t *reduced_clock,
2a8f64ca 4239 int num_connectors)
a0c4da24
JB		 4240{
4241 struct drm_device *dev = crtc->dev;
4242 struct drm_i915_private *dev_priv = dev->dev_private;
4243 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4244 int pipe = intel_crtc->pipe;
4245 u32 dpll, mdiv, pdiv;
4246 u32 bestn, bestm1, bestm2, bestp1, bestp2;
2a8f64ca
VP		 4247 bool is_sdvo;
4248 u32 temp;
a0c4da24 4249
09153000
DV		 4250 mutex_lock(&dev_priv->dpio_lock);
4251
2a8f64ca
VP		 4252 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4253 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
a0c4da24 4254
2a8f64ca
VP		 4255 dpll = DPLL_VGA_MODE_DIS;
4256 dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4257 dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4258 dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4259
4260 I915_WRITE(DPLL(pipe), dpll);
4261 POSTING_READ(DPLL(pipe));
a0c4da24
JB		 4262
4263 bestn = clock->n;
4264 bestm1 = clock->m1;
4265 bestm2 = clock->m2;
4266 bestp1 = clock->p1;
4267 bestp2 = clock->p2;
4268
2a8f64ca
VP		 4269 /*
4270 * In Valleyview PLL and program lane counter registers are exposed
4271 * through DPIO interface
4272 */
a0c4da24
JB		 4273 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4274 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4275 mdiv |= ((bestn << DPIO_N_SHIFT));
4276 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4277 mdiv |= (1 << DPIO_K_SHIFT);
4278 mdiv |= DPIO_ENABLE_CALIBRATION;
4279 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4280
4281 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4282
2a8f64ca 4283 pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
a0c4da24 4284 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
2a8f64ca
VP		 4285 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4286 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
a0c4da24
JB		 4287 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4288
2a8f64ca 4289 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
a0c4da24
JB		 4290
4291 dpll |= DPLL_VCO_ENABLE;
4292 I915_WRITE(DPLL(pipe), dpll);
4293 POSTING_READ(DPLL(pipe));
4294 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4295 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4296
2a8f64ca
VP		 4297 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4298
4299 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4300 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4301
4302 I915_WRITE(DPLL(pipe), dpll);
4303
4304 /* Wait for the clocks to stabilize. */
4305 POSTING_READ(DPLL(pipe));
4306 udelay(150);
a0c4da24 4307
2a8f64ca
VP		 4308 temp = 0;
4309 if (is_sdvo) {
4310 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
a0c4da24
JB		 4311 if (temp > 1)
4312 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4313 else
4314 temp = 0;
a0c4da24 4315 }
2a8f64ca
VP		 4316 I915_WRITE(DPLL_MD(pipe), temp);
4317 POSTING_READ(DPLL_MD(pipe));
a0c4da24 4318
2a8f64ca
VP		 4319 /* Now program lane control registers */
4320 if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4321 || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4322 {
4323 temp = 0x1000C4;
4324 if(pipe == 1)
4325 temp |= (1 << 21);
4326 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4327 }
4328 if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4329 {
4330 temp = 0x1000C4;
4331 if(pipe == 1)
4332 temp |= (1 << 21);
4333 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4334 }
09153000
DV		 4335
4336 mutex_unlock(&dev_priv->dpio_lock);
a0c4da24
JB		 4337}
4338
eb1cbe48
DV		 4339static void i9xx_update_pll(struct drm_crtc *crtc,
4340 struct drm_display_mode *mode,
4341 struct drm_display_mode *adjusted_mode,
4342 intel_clock_t *clock, intel_clock_t *reduced_clock,
4343 int num_connectors)
4344{
4345 struct drm_device *dev = crtc->dev;
4346 struct drm_i915_private *dev_priv = dev->dev_private;
4347 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4348 struct intel_encoder *encoder;
eb1cbe48
DV		 4349 int pipe = intel_crtc->pipe;
4350 u32 dpll;
4351 bool is_sdvo;
4352
2a8f64ca
VP		 4353 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4354
eb1cbe48
DV		 4355 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4356 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4357
4358 dpll = DPLL_VGA_MODE_DIS;
4359
4360 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4361 dpll |= DPLLB_MODE_LVDS;
4362 else
4363 dpll |= DPLLB_MODE_DAC_SERIAL;
4364 if (is_sdvo) {
4365 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4366 if (pixel_multiplier > 1) {
4367 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4368 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4369 }
4370 dpll |= DPLL_DVO_HIGH_SPEED;
4371 }
4372 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4373 dpll |= DPLL_DVO_HIGH_SPEED;
4374
4375 /* compute bitmask from p1 value */
4376 if (IS_PINEVIEW(dev))
4377 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4378 else {
4379 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4380 if (IS_G4X(dev) && reduced_clock)
4381 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4382 }
4383 switch (clock->p2) {
4384 case 5:
4385 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4386 break;
4387 case 7:
4388 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4389 break;
4390 case 10:
4391 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4392 break;
4393 case 14:
4394 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4395 break;
4396 }
4397 if (INTEL_INFO(dev)->gen >= 4)
4398 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4399
4400 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4401 dpll |= PLL_REF_INPUT_TVCLKINBC;
4402 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4403 /* XXX: just matching BIOS for now */
4404 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4405 dpll |= 3;
4406 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4407 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4408 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4409 else
4410 dpll |= PLL_REF_INPUT_DREFCLK;
4411
4412 dpll |= DPLL_VCO_ENABLE;
4413 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4414 POSTING_READ(DPLL(pipe));
4415 udelay(150);
4416
dafd226c
DV		 4417 for_each_encoder_on_crtc(dev, crtc, encoder)
4418 if (encoder->pre_pll_enable)
4419 encoder->pre_pll_enable(encoder);
eb1cbe48
DV		 4420
4421 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4422 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4423
4424 I915_WRITE(DPLL(pipe), dpll);
4425
4426 /* Wait for the clocks to stabilize. */
4427 POSTING_READ(DPLL(pipe));
4428 udelay(150);
4429
4430 if (INTEL_INFO(dev)->gen >= 4) {
4431 u32 temp = 0;
4432 if (is_sdvo) {
4433 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4434 if (temp > 1)
4435 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4436 else
4437 temp = 0;
4438 }
4439 I915_WRITE(DPLL_MD(pipe), temp);
4440 } else {
4441 /* The pixel multiplier can only be updated once the
4442 * DPLL is enabled and the clocks are stable.
4443 *
4444 * So write it again.
4445 */
4446 I915_WRITE(DPLL(pipe), dpll);
4447 }
4448}
4449
4450static void i8xx_update_pll(struct drm_crtc *crtc,
4451 struct drm_display_mode *adjusted_mode,
2a8f64ca 4452 intel_clock_t *clock, intel_clock_t *reduced_clock,
eb1cbe48
DV		 4453 int num_connectors)
4454{
4455 struct drm_device *dev = crtc->dev;
4456 struct drm_i915_private *dev_priv = dev->dev_private;
4457 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
dafd226c 4458 struct intel_encoder *encoder;
eb1cbe48
DV		 4459 int pipe = intel_crtc->pipe;
4460 u32 dpll;
4461
2a8f64ca
VP		 4462 i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4463
eb1cbe48
DV		 4464 dpll = DPLL_VGA_MODE_DIS;
4465
4466 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4467 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4468 } else {
4469 if (clock->p1 == 2)
4470 dpll |= PLL_P1_DIVIDE_BY_TWO;
4471 else
4472 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4473 if (clock->p2 == 4)
4474 dpll |= PLL_P2_DIVIDE_BY_4;
4475 }
4476
4477 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4478 /* XXX: just matching BIOS for now */
4479 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4480 dpll |= 3;
4481 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4482 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4483 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4484 else
4485 dpll |= PLL_REF_INPUT_DREFCLK;
4486
4487 dpll |= DPLL_VCO_ENABLE;
4488 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4489 POSTING_READ(DPLL(pipe));
4490 udelay(150);
4491
dafd226c
DV		 4492 for_each_encoder_on_crtc(dev, crtc, encoder)
4493 if (encoder->pre_pll_enable)
4494 encoder->pre_pll_enable(encoder);
eb1cbe48 4495
5b5896e4
DV		 4496 I915_WRITE(DPLL(pipe), dpll);
4497
4498 /* Wait for the clocks to stabilize. */
4499 POSTING_READ(DPLL(pipe));
4500 udelay(150);
4501
eb1cbe48
DV		 4502 /* The pixel multiplier can only be updated once the
4503 * DPLL is enabled and the clocks are stable.
4504 *
4505 * So write it again.
4506 */
4507 I915_WRITE(DPLL(pipe), dpll);
4508}
4509
b0e77b9c
PZ		 4510static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4511 struct drm_display_mode *mode,
4512 struct drm_display_mode *adjusted_mode)
4513{
4514 struct drm_device *dev = intel_crtc->base.dev;
4515 struct drm_i915_private *dev_priv = dev->dev_private;
4516 enum pipe pipe = intel_crtc->pipe;
fe2b8f9d 4517 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
b0e77b9c
PZ		 4518 uint32_t vsyncshift;
4519
4520 if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4521 /* the chip adds 2 halflines automatically */
4522 adjusted_mode->crtc_vtotal -= 1;
4523 adjusted_mode->crtc_vblank_end -= 1;
4524 vsyncshift = adjusted_mode->crtc_hsync_start
4525 - adjusted_mode->crtc_htotal / 2;
4526 } else {
4527 vsyncshift = 0;
4528 }
4529
4530 if (INTEL_INFO(dev)->gen > 3)
fe2b8f9d 4531 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
b0e77b9c 4532
fe2b8f9d 4533 I915_WRITE(HTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4534 (adjusted_mode->crtc_hdisplay - 1) |
4535 ((adjusted_mode->crtc_htotal - 1) << 16));
fe2b8f9d 4536 I915_WRITE(HBLANK(cpu_transcoder),
b0e77b9c
PZ		 4537 (adjusted_mode->crtc_hblank_start - 1) |
4538 ((adjusted_mode->crtc_hblank_end - 1) << 16));
fe2b8f9d 4539 I915_WRITE(HSYNC(cpu_transcoder),
b0e77b9c
PZ		 4540 (adjusted_mode->crtc_hsync_start - 1) |
4541 ((adjusted_mode->crtc_hsync_end - 1) << 16));
4542
fe2b8f9d 4543 I915_WRITE(VTOTAL(cpu_transcoder),
b0e77b9c
PZ		 4544 (adjusted_mode->crtc_vdisplay - 1) |
4545 ((adjusted_mode->crtc_vtotal - 1) << 16));
fe2b8f9d 4546 I915_WRITE(VBLANK(cpu_transcoder),
b0e77b9c
PZ		 4547 (adjusted_mode->crtc_vblank_start - 1) |
4548 ((adjusted_mode->crtc_vblank_end - 1) << 16));
fe2b8f9d 4549 I915_WRITE(VSYNC(cpu_transcoder),
b0e77b9c
PZ		 4550 (adjusted_mode->crtc_vsync_start - 1) |
4551 ((adjusted_mode->crtc_vsync_end - 1) << 16));
4552
b5e508d4
PZ		 4553 /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4554 * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4555 * documented on the DDI_FUNC_CTL register description, EDP Input Select
4556 * bits. */
4557 if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4558 (pipe == PIPE_B || pipe == PIPE_C))
4559 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4560
b0e77b9c
PZ		 4561 /* pipesrc controls the size that is scaled from, which should
4562 * always be the user's requested size.
4563 */
4564 I915_WRITE(PIPESRC(pipe),
4565 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4566}
4567
f564048e
EA		 4568static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4569 struct drm_display_mode *mode,
4570 struct drm_display_mode *adjusted_mode,
4571 int x, int y,
94352cf9 4572 struct drm_framebuffer *fb)
79e53945
JB		 4573{
4574 struct drm_device *dev = crtc->dev;
4575 struct drm_i915_private *dev_priv = dev->dev_private;
4576 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4577 int pipe = intel_crtc->pipe;
80824003 4578 int plane = intel_crtc->plane;
c751ce4f 4579 int refclk, num_connectors = 0;
652c393a 4580 intel_clock_t clock, reduced_clock;
b0e77b9c 4581 u32 dspcntr, pipeconf;
eb1cbe48
DV		 4582 bool ok, has_reduced_clock = false, is_sdvo = false;
4583 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4584 struct intel_encoder *encoder;
d4906093 4585 const intel_limit_t *limit;
5c3b82e2 4586 int ret;
79e53945 4587
6c2b7c12 4588 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4589 switch (encoder->type) {
79e53945
JB		 4590 case INTEL_OUTPUT_LVDS:
4591 is_lvds = true;
4592 break;
4593 case INTEL_OUTPUT_SDVO:
7d57382e 4594 case INTEL_OUTPUT_HDMI:
79e53945 4595 is_sdvo = true;
5eddb70b 4596 if (encoder->needs_tv_clock)
e2f0ba97 4597 is_tv = true;
79e53945 4598 break;
79e53945
JB		 4599 case INTEL_OUTPUT_TVOUT:
4600 is_tv = true;
4601 break;
a4fc5ed6
KP		 4602 case INTEL_OUTPUT_DISPLAYPORT:
4603 is_dp = true;
4604 break;
79e53945 4605 }
43565a06 4606
c751ce4f 4607 num_connectors++;
79e53945
JB		 4608 }
4609
c65d77d8 4610 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4611
d4906093
ML		 4612 /*
4613 * Returns a set of divisors for the desired target clock with the given
4614 * refclk, or FALSE. The returned values represent the clock equation:
4615 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4616 */
1b894b59 4617 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4618 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4619 &clock);
79e53945
JB		 4620 if (!ok) {
4621 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4622 return -EINVAL;
79e53945
JB		 4623 }
4624
cda4b7d3 4625 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4626 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4627
ddc9003c 4628 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4629 /*
4630 * Ensure we match the reduced clock's P to the target clock.
4631 * If the clocks don't match, we can't switch the display clock
4632 * by using the FP0/FP1. In such case we will disable the LVDS
4633 * downclock feature.
4634 */
ddc9003c 4635 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4636 dev_priv->lvds_downclock,
4637 refclk,
cec2f356 4638 &clock,
5eddb70b 4639 &reduced_clock);
7026d4ac
ZW		 4640 }
4641
c65d77d8
JB		 4642 if (is_sdvo && is_tv)
4643 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4644
eb1cbe48 4645 if (IS_GEN2(dev))
2a8f64ca
VP		 4646 i8xx_update_pll(crtc, adjusted_mode, &clock,
4647 has_reduced_clock ? &reduced_clock : NULL,
4648 num_connectors);
a0c4da24 4649 else if (IS_VALLEYVIEW(dev))
2a8f64ca
VP		 4650 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4651 has_reduced_clock ? &reduced_clock : NULL,
4652 num_connectors);
79e53945 4653 else
eb1cbe48
DV		 4654 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4655 has_reduced_clock ? &reduced_clock : NULL,
4656 num_connectors);
79e53945
JB		 4657
4658 /* setup pipeconf */
5eddb70b 4659 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4660
4661 /* Set up the display plane register */
4662 dspcntr = DISPPLANE_GAMMA_ENABLE;
4663
929c77fb
EA		 4664 if (pipe == 0)
4665 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4666 else
4667 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4668
a6c45cf0 4669 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4670 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4671 * core speed.
4672 *
4673 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4674 * pipe == 0 check?
4675 */
e70236a8
JB		 4676 if (mode->clock >
4677 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4678 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4679 else
5eddb70b 4680 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4681 }
4682
3b5c78a3 4683 /* default to 8bpc */
dfd07d72 4684 pipeconf &= ~(PIPECONF_BPC_MASK | PIPECONF_DITHER_EN);
3b5c78a3 4685 if (is_dp) {
0c96c65b 4686 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
dfd07d72 4687 pipeconf |= PIPECONF_6BPC |
3b5c78a3
AJ		 4688 PIPECONF_DITHER_EN |
4689 PIPECONF_DITHER_TYPE_SP;
4690 }
4691 }
4692
19c03924
GB		 4693 if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4694 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
dfd07d72 4695 pipeconf |= PIPECONF_6BPC |
19c03924
GB		 4696 PIPECONF_ENABLE |
4697 I965_PIPECONF_ACTIVE;
4698 }
4699 }
4700
28c97730 4701 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4702 drm_mode_debug_printmodeline(mode);
4703
a7516a05
JB		 4704 if (HAS_PIPE_CXSR(dev)) {
4705 if (intel_crtc->lowfreq_avail) {
28c97730 4706 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4707 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4708 } else {
28c97730 4709 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4710 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4711 }
4712 }
4713
617cf884 4714 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575 4715 if (!IS_GEN2(dev) &&
b0e77b9c 4716 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
734b4157 4717 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
b0e77b9c 4718 else
617cf884 4719 pipeconf |= PIPECONF_PROGRESSIVE;
734b4157 4720
b0e77b9c 4721 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b
CW		 4722
4723 /* pipesrc and dspsize control the size that is scaled from,
4724 * which should always be the user's requested size.
79e53945 4725 */
929c77fb
EA		 4726 I915_WRITE(DSPSIZE(plane),
4727 ((mode->vdisplay - 1) << 16) |
4728 (mode->hdisplay - 1));
4729 I915_WRITE(DSPPOS(plane), 0);
2c07245f 4730
f564048e
EA		 4731 I915_WRITE(PIPECONF(pipe), pipeconf);
4732 POSTING_READ(PIPECONF(pipe));
929c77fb 4733 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4734
4735 intel_wait_for_vblank(dev, pipe);
4736
f564048e
EA		 4737 I915_WRITE(DSPCNTR(plane), dspcntr);
4738 POSTING_READ(DSPCNTR(plane));
4739
94352cf9 4740 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4741
4742 intel_update_watermarks(dev);
4743
f564048e
EA		 4744 return ret;
4745}
4746
dde86e2d 4747static void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4748{
4749 struct drm_i915_private *dev_priv = dev->dev_private;
4750 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4751 struct intel_encoder *encoder;
13d83a67
JB		 4752 u32 temp;
4753 bool has_lvds = false;
199e5d79
KP		 4754 bool has_cpu_edp = false;
4755 bool has_pch_edp = false;
4756 bool has_panel = false;
99eb6a01
KP		 4757 bool has_ck505 = false;
4758 bool can_ssc = false;
13d83a67
JB		 4759
4760 /* We need to take the global config into account */
199e5d79
KP		 4761 list_for_each_entry(encoder, &mode_config->encoder_list,
4762 base.head) {
4763 switch (encoder->type) {
4764 case INTEL_OUTPUT_LVDS:
4765 has_panel = true;
4766 has_lvds = true;
4767 break;
4768 case INTEL_OUTPUT_EDP:
4769 has_panel = true;
4770 if (intel_encoder_is_pch_edp(&encoder->base))
4771 has_pch_edp = true;
4772 else
4773 has_cpu_edp = true;
4774 break;
13d83a67
JB		 4775 }
4776 }
4777
99eb6a01
KP		 4778 if (HAS_PCH_IBX(dev)) {
4779 has_ck505 = dev_priv->display_clock_mode;
4780 can_ssc = has_ck505;
4781 } else {
4782 has_ck505 = false;
4783 can_ssc = true;
4784 }
4785
4786 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4787 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4788 has_ck505);
13d83a67
JB		 4789
4790 /* Ironlake: try to setup display ref clock before DPLL
4791 * enabling. This is only under driver's control after
4792 * PCH B stepping, previous chipset stepping should be
4793 * ignoring this setting.
4794 */
4795 temp = I915_READ(PCH_DREF_CONTROL);
4796 /* Always enable nonspread source */
4797 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4798
99eb6a01
KP		 4799 if (has_ck505)
4800 temp |= DREF_NONSPREAD_CK505_ENABLE;
4801 else
4802 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4803
199e5d79
KP		 4804 if (has_panel) {
4805 temp &= ~DREF_SSC_SOURCE_MASK;
4806 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4807
199e5d79 4808 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4809 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4810 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4811 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4812 } else
4813 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4814
4815 /* Get SSC going before enabling the outputs */
4816 I915_WRITE(PCH_DREF_CONTROL, temp);
4817 POSTING_READ(PCH_DREF_CONTROL);
4818 udelay(200);
4819
13d83a67
JB		 4820 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4821
4822 /* Enable CPU source on CPU attached eDP */
199e5d79 4823 if (has_cpu_edp) {
99eb6a01 4824 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4825 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4826 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4827 }
13d83a67
JB		 4828 else
4829 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4830 } else
4831 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4832
4833 I915_WRITE(PCH_DREF_CONTROL, temp);
4834 POSTING_READ(PCH_DREF_CONTROL);
4835 udelay(200);
4836 } else {
4837 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4838
4839 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4840
4841 /* Turn off CPU output */
4842 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4843
4844 I915_WRITE(PCH_DREF_CONTROL, temp);
4845 POSTING_READ(PCH_DREF_CONTROL);
4846 udelay(200);
4847
4848 /* Turn off the SSC source */
4849 temp &= ~DREF_SSC_SOURCE_MASK;
4850 temp |= DREF_SSC_SOURCE_DISABLE;
4851
4852 /* Turn off SSC1 */
4853 temp &= ~ DREF_SSC1_ENABLE;
4854
13d83a67
JB		 4855 I915_WRITE(PCH_DREF_CONTROL, temp);
4856 POSTING_READ(PCH_DREF_CONTROL);
4857 udelay(200);
4858 }
4859}
4860
dde86e2d
PZ		 4861/* Sequence to enable CLKOUT_DP for FDI usage and configure PCH FDI I/O. */
4862static void lpt_init_pch_refclk(struct drm_device *dev)
4863{
4864 struct drm_i915_private *dev_priv = dev->dev_private;
4865 struct drm_mode_config *mode_config = &dev->mode_config;
4866 struct intel_encoder *encoder;
4867 bool has_vga = false;
4868 bool is_sdv = false;
4869 u32 tmp;
4870
4871 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4872 switch (encoder->type) {
4873 case INTEL_OUTPUT_ANALOG:
4874 has_vga = true;
4875 break;
4876 }
4877 }
4878
4879 if (!has_vga)
4880 return;
4881
c00db246
DV		 4882 mutex_lock(&dev_priv->dpio_lock);
4883
dde86e2d
PZ		 4884 /* XXX: Rip out SDV support once Haswell ships for real. */
4885 if (IS_HASWELL(dev) && (dev->pci_device & 0xFF00) == 0x0C00)
4886 is_sdv = true;
4887
4888 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4889 tmp &= ~SBI_SSCCTL_DISABLE;
4890 tmp |= SBI_SSCCTL_PATHALT;
4891 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4892
4893 udelay(24);
4894
4895 tmp = intel_sbi_read(dev_priv, SBI_SSCCTL, SBI_ICLK);
4896 tmp &= ~SBI_SSCCTL_PATHALT;
4897 intel_sbi_write(dev_priv, SBI_SSCCTL, tmp, SBI_ICLK);
4898
4899 if (!is_sdv) {
4900 tmp = I915_READ(SOUTH_CHICKEN2);
4901 tmp |= FDI_MPHY_IOSFSB_RESET_CTL;
4902 I915_WRITE(SOUTH_CHICKEN2, tmp);
4903
4904 if (wait_for_atomic_us(I915_READ(SOUTH_CHICKEN2) &
4905 FDI_MPHY_IOSFSB_RESET_STATUS, 100))
4906 DRM_ERROR("FDI mPHY reset assert timeout\n");
4907
4908 tmp = I915_READ(SOUTH_CHICKEN2);
4909 tmp &= ~FDI_MPHY_IOSFSB_RESET_CTL;
4910 I915_WRITE(SOUTH_CHICKEN2, tmp);
4911
4912 if (wait_for_atomic_us((I915_READ(SOUTH_CHICKEN2) &
4913 FDI_MPHY_IOSFSB_RESET_STATUS) == 0,
4914 100))
4915 DRM_ERROR("FDI mPHY reset de-assert timeout\n");
4916 }
4917
4918 tmp = intel_sbi_read(dev_priv, 0x8008, SBI_MPHY);
4919 tmp &= ~(0xFF << 24);
4920 tmp |= (0x12 << 24);
4921 intel_sbi_write(dev_priv, 0x8008, tmp, SBI_MPHY);
4922
4923 if (!is_sdv) {
4924 tmp = intel_sbi_read(dev_priv, 0x808C, SBI_MPHY);
4925 tmp &= ~(0x3 << 6);
4926 tmp |= (1 << 6) | (1 << 0);
4927 intel_sbi_write(dev_priv, 0x808C, tmp, SBI_MPHY);
4928 }
4929
4930 if (is_sdv) {
4931 tmp = intel_sbi_read(dev_priv, 0x800C, SBI_MPHY);
4932 tmp |= 0x7FFF;
4933 intel_sbi_write(dev_priv, 0x800C, tmp, SBI_MPHY);
4934 }
4935
4936 tmp = intel_sbi_read(dev_priv, 0x2008, SBI_MPHY);
4937 tmp |= (1 << 11);
4938 intel_sbi_write(dev_priv, 0x2008, tmp, SBI_MPHY);
4939
4940 tmp = intel_sbi_read(dev_priv, 0x2108, SBI_MPHY);
4941 tmp |= (1 << 11);
4942 intel_sbi_write(dev_priv, 0x2108, tmp, SBI_MPHY);
4943
4944 if (is_sdv) {
4945 tmp = intel_sbi_read(dev_priv, 0x2038, SBI_MPHY);
4946 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4947 intel_sbi_write(dev_priv, 0x2038, tmp, SBI_MPHY);
4948
4949 tmp = intel_sbi_read(dev_priv, 0x2138, SBI_MPHY);
4950 tmp |= (0x3F << 24) | (0xF << 20) | (0xF << 16);
4951 intel_sbi_write(dev_priv, 0x2138, tmp, SBI_MPHY);
4952
4953 tmp = intel_sbi_read(dev_priv, 0x203C, SBI_MPHY);
4954 tmp |= (0x3F << 8);
4955 intel_sbi_write(dev_priv, 0x203C, tmp, SBI_MPHY);
4956
4957 tmp = intel_sbi_read(dev_priv, 0x213C, SBI_MPHY);
4958 tmp |= (0x3F << 8);
4959 intel_sbi_write(dev_priv, 0x213C, tmp, SBI_MPHY);
4960 }
4961
4962 tmp = intel_sbi_read(dev_priv, 0x206C, SBI_MPHY);
4963 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4964 intel_sbi_write(dev_priv, 0x206C, tmp, SBI_MPHY);
4965
4966 tmp = intel_sbi_read(dev_priv, 0x216C, SBI_MPHY);
4967 tmp |= (1 << 24) | (1 << 21) | (1 << 18);
4968 intel_sbi_write(dev_priv, 0x216C, tmp, SBI_MPHY);
4969
4970 if (!is_sdv) {
4971 tmp = intel_sbi_read(dev_priv, 0x2080, SBI_MPHY);
4972 tmp &= ~(7 << 13);
4973 tmp |= (5 << 13);
4974 intel_sbi_write(dev_priv, 0x2080, tmp, SBI_MPHY);
4975
4976 tmp = intel_sbi_read(dev_priv, 0x2180, SBI_MPHY);
4977 tmp &= ~(7 << 13);
4978 tmp |= (5 << 13);
4979 intel_sbi_write(dev_priv, 0x2180, tmp, SBI_MPHY);
4980 }
4981
4982 tmp = intel_sbi_read(dev_priv, 0x208C, SBI_MPHY);
4983 tmp &= ~0xFF;
4984 tmp |= 0x1C;
4985 intel_sbi_write(dev_priv, 0x208C, tmp, SBI_MPHY);
4986
4987 tmp = intel_sbi_read(dev_priv, 0x218C, SBI_MPHY);
4988 tmp &= ~0xFF;
4989 tmp |= 0x1C;
4990 intel_sbi_write(dev_priv, 0x218C, tmp, SBI_MPHY);
4991
4992 tmp = intel_sbi_read(dev_priv, 0x2098, SBI_MPHY);
4993 tmp &= ~(0xFF << 16);
4994 tmp |= (0x1C << 16);
4995 intel_sbi_write(dev_priv, 0x2098, tmp, SBI_MPHY);
4996
4997 tmp = intel_sbi_read(dev_priv, 0x2198, SBI_MPHY);
4998 tmp &= ~(0xFF << 16);
4999 tmp |= (0x1C << 16);
5000 intel_sbi_write(dev_priv, 0x2198, tmp, SBI_MPHY);
5001
5002 if (!is_sdv) {
5003 tmp = intel_sbi_read(dev_priv, 0x20C4, SBI_MPHY);
5004 tmp |= (1 << 27);
5005 intel_sbi_write(dev_priv, 0x20C4, tmp, SBI_MPHY);
5006
5007 tmp = intel_sbi_read(dev_priv, 0x21C4, SBI_MPHY);
5008 tmp |= (1 << 27);
5009 intel_sbi_write(dev_priv, 0x21C4, tmp, SBI_MPHY);
5010
5011 tmp = intel_sbi_read(dev_priv, 0x20EC, SBI_MPHY);
5012 tmp &= ~(0xF << 28);
5013 tmp |= (4 << 28);
5014 intel_sbi_write(dev_priv, 0x20EC, tmp, SBI_MPHY);
5015
5016 tmp = intel_sbi_read(dev_priv, 0x21EC, SBI_MPHY);
5017 tmp &= ~(0xF << 28);
5018 tmp |= (4 << 28);
5019 intel_sbi_write(dev_priv, 0x21EC, tmp, SBI_MPHY);
5020 }
5021
5022 /* ULT uses SBI_GEN0, but ULT doesn't have VGA, so we don't care. */
5023 tmp = intel_sbi_read(dev_priv, SBI_DBUFF0, SBI_ICLK);
5024 tmp |= SBI_DBUFF0_ENABLE;
5025 intel_sbi_write(dev_priv, SBI_DBUFF0, tmp, SBI_ICLK);
c00db246
DV		 5026
5027 mutex_unlock(&dev_priv->dpio_lock);
dde86e2d
PZ		 5028}
5029
5030/*
5031 * Initialize reference clocks when the driver loads
5032 */
5033void intel_init_pch_refclk(struct drm_device *dev)
5034{
5035 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5036 ironlake_init_pch_refclk(dev);
5037 else if (HAS_PCH_LPT(dev))
5038 lpt_init_pch_refclk(dev);
5039}
5040
d9d444cb
JB		 5041static int ironlake_get_refclk(struct drm_crtc *crtc)
5042{
5043 struct drm_device *dev = crtc->dev;
5044 struct drm_i915_private *dev_priv = dev->dev_private;
5045 struct intel_encoder *encoder;
d9d444cb
JB		 5046 struct intel_encoder *edp_encoder = NULL;
5047 int num_connectors = 0;
5048 bool is_lvds = false;
5049
6c2b7c12 5050 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 5051 switch (encoder->type) {
5052 case INTEL_OUTPUT_LVDS:
5053 is_lvds = true;
5054 break;
5055 case INTEL_OUTPUT_EDP:
5056 edp_encoder = encoder;
5057 break;
5058 }
5059 num_connectors++;
5060 }
5061
5062 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5063 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5064 dev_priv->lvds_ssc_freq);
5065 return dev_priv->lvds_ssc_freq * 1000;
5066 }
5067
5068 return 120000;
5069}
5070
c8203565 5071static void ironlake_set_pipeconf(struct drm_crtc *crtc,
f564048e 5072 struct drm_display_mode *adjusted_mode,
c8203565 5073 bool dither)
79e53945 5074{
c8203565 5075 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
79e53945
JB		 5076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5077 int pipe = intel_crtc->pipe;
c8203565
PZ		 5078 uint32_t val;
5079
5080 val = I915_READ(PIPECONF(pipe));
5081
dfd07d72 5082 val &= ~PIPECONF_BPC_MASK;
c8203565
PZ		 5083 switch (intel_crtc->bpp) {
5084 case 18:
dfd07d72 5085 val |= PIPECONF_6BPC;
c8203565
PZ		 5086 break;
5087 case 24:
dfd07d72 5088 val |= PIPECONF_8BPC;
c8203565
PZ		 5089 break;
5090 case 30:
dfd07d72 5091 val |= PIPECONF_10BPC;
c8203565
PZ		 5092 break;
5093 case 36:
dfd07d72 5094 val |= PIPECONF_12BPC;
c8203565
PZ		 5095 break;
5096 default:
cc769b62
PZ		 5097 /* Case prevented by intel_choose_pipe_bpp_dither. */
5098 BUG();
c8203565
PZ		 5099 }
5100
5101 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5102 if (dither)
5103 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5104
5105 val &= ~PIPECONF_INTERLACE_MASK;
5106 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5107 val |= PIPECONF_INTERLACED_ILK;
5108 else
5109 val |= PIPECONF_PROGRESSIVE;
5110
3685a8f3
VS		 5111 if (adjusted_mode->private_flags & INTEL_MODE_LIMITED_COLOR_RANGE)
5112 val |= PIPECONF_COLOR_RANGE_SELECT;
5113 else
5114 val &= ~PIPECONF_COLOR_RANGE_SELECT;
5115
c8203565
PZ		 5116 I915_WRITE(PIPECONF(pipe), val);
5117 POSTING_READ(PIPECONF(pipe));
5118}
5119
ee2b0b38
PZ		 5120static void haswell_set_pipeconf(struct drm_crtc *crtc,
5121 struct drm_display_mode *adjusted_mode,
5122 bool dither)
5123{
5124 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
5125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
702e7a56 5126 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
ee2b0b38
PZ		 5127 uint32_t val;
5128
702e7a56 5129 val = I915_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5130
5131 val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
5132 if (dither)
5133 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
5134
5135 val &= ~PIPECONF_INTERLACE_MASK_HSW;
5136 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
5137 val |= PIPECONF_INTERLACED_ILK;
5138 else
5139 val |= PIPECONF_PROGRESSIVE;
5140
702e7a56
PZ		 5141 I915_WRITE(PIPECONF(cpu_transcoder), val);
5142 POSTING_READ(PIPECONF(cpu_transcoder));
ee2b0b38
PZ		 5143}
5144
6591c6e4
PZ		 5145static bool ironlake_compute_clocks(struct drm_crtc *crtc,
5146 struct drm_display_mode *adjusted_mode,
5147 intel_clock_t *clock,
5148 bool *has_reduced_clock,
5149 intel_clock_t *reduced_clock)
5150{
5151 struct drm_device *dev = crtc->dev;
5152 struct drm_i915_private *dev_priv = dev->dev_private;
5153 struct intel_encoder *intel_encoder;
5154 int refclk;
d4906093 5155 const intel_limit_t *limit;
6591c6e4 5156 bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
79e53945 5157
6591c6e4
PZ		 5158 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5159 switch (intel_encoder->type) {
79e53945
JB		 5160 case INTEL_OUTPUT_LVDS:
5161 is_lvds = true;
5162 break;
5163 case INTEL_OUTPUT_SDVO:
7d57382e 5164 case INTEL_OUTPUT_HDMI:
79e53945 5165 is_sdvo = true;
6591c6e4 5166 if (intel_encoder->needs_tv_clock)
e2f0ba97 5167 is_tv = true;
79e53945 5168 break;
79e53945
JB		 5169 case INTEL_OUTPUT_TVOUT:
5170 is_tv = true;
5171 break;
79e53945
JB		 5172 }
5173 }
5174
d9d444cb 5175 refclk = ironlake_get_refclk(crtc);
79e53945 5176
d4906093
ML		 5177 /*
5178 * Returns a set of divisors for the desired target clock with the given
5179 * refclk, or FALSE. The returned values represent the clock equation:
5180 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5181 */
1b894b59 5182 limit = intel_limit(crtc, refclk);
6591c6e4
PZ		 5183 ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5184 clock);
5185 if (!ret)
5186 return false;
cda4b7d3 5187
ddc9003c 5188 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 5189 /*
5190 * Ensure we match the reduced clock's P to the target clock.
5191 * If the clocks don't match, we can't switch the display clock
5192 * by using the FP0/FP1. In such case we will disable the LVDS
5193 * downclock feature.
5194 */
6591c6e4
PZ		 5195 *has_reduced_clock = limit->find_pll(limit, crtc,
5196 dev_priv->lvds_downclock,
5197 refclk,
5198 clock,
5199 reduced_clock);
652c393a 5200 }
61e9653f
DV		 5201
5202 if (is_sdvo && is_tv)
6591c6e4
PZ		 5203 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5204
5205 return true;
5206}
5207
01a415fd
DV		 5208static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5209{
5210 struct drm_i915_private *dev_priv = dev->dev_private;
5211 uint32_t temp;
5212
5213 temp = I915_READ(SOUTH_CHICKEN1);
5214 if (temp & FDI_BC_BIFURCATION_SELECT)
5215 return;
5216
5217 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5218 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5219
5220 temp |= FDI_BC_BIFURCATION_SELECT;
5221 DRM_DEBUG_KMS("enabling fdi C rx\n");
5222 I915_WRITE(SOUTH_CHICKEN1, temp);
5223 POSTING_READ(SOUTH_CHICKEN1);
5224}
5225
5226static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5227{
5228 struct drm_device *dev = intel_crtc->base.dev;
5229 struct drm_i915_private *dev_priv = dev->dev_private;
5230 struct intel_crtc *pipe_B_crtc =
5231 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5232
5233 DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5234 intel_crtc->pipe, intel_crtc->fdi_lanes);
5235 if (intel_crtc->fdi_lanes > 4) {
5236 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5237 intel_crtc->pipe, intel_crtc->fdi_lanes);
5238 /* Clamp lanes to avoid programming the hw with bogus values. */
5239 intel_crtc->fdi_lanes = 4;
5240
5241 return false;
5242 }
5243
5244 if (dev_priv->num_pipe == 2)
5245 return true;
5246
5247 switch (intel_crtc->pipe) {
5248 case PIPE_A:
5249 return true;
5250 case PIPE_B:
5251 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5252 intel_crtc->fdi_lanes > 2) {
5253 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5254 intel_crtc->pipe, intel_crtc->fdi_lanes);
5255 /* Clamp lanes to avoid programming the hw with bogus values. */
5256 intel_crtc->fdi_lanes = 2;
5257
5258 return false;
5259 }
5260
5261 if (intel_crtc->fdi_lanes > 2)
5262 WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5263 else
5264 cpt_enable_fdi_bc_bifurcation(dev);
5265
5266 return true;
5267 case PIPE_C:
5268 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5269 if (intel_crtc->fdi_lanes > 2) {
5270 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5271 intel_crtc->pipe, intel_crtc->fdi_lanes);
5272 /* Clamp lanes to avoid programming the hw with bogus values. */
5273 intel_crtc->fdi_lanes = 2;
5274
5275 return false;
5276 }
5277 } else {
5278 DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5279 return false;
5280 }
5281
5282 cpt_enable_fdi_bc_bifurcation(dev);
5283
5284 return true;
5285 default:
5286 BUG();
5287 }
5288}
5289
d4b1931c
PZ		 5290int ironlake_get_lanes_required(int target_clock, int link_bw, int bpp)
5291{
5292 /*
5293 * Account for spread spectrum to avoid
5294 * oversubscribing the link. Max center spread
5295 * is 2.5%; use 5% for safety's sake.
5296 */
5297 u32 bps = target_clock * bpp * 21 / 20;
5298 return bps / (link_bw * 8) + 1;
5299}
5300
f48d8f23
PZ		 5301static void ironlake_set_m_n(struct drm_crtc *crtc,
5302 struct drm_display_mode *mode,
5303 struct drm_display_mode *adjusted_mode)
79e53945
JB		 5304{
5305 struct drm_device *dev = crtc->dev;
5306 struct drm_i915_private *dev_priv = dev->dev_private;
5307 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
afe2fcf5 5308 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
f48d8f23 5309 struct intel_encoder *intel_encoder, *edp_encoder = NULL;
e69d0bc1 5310 struct intel_link_m_n m_n = {0};
f48d8f23
PZ		 5311 int target_clock, pixel_multiplier, lane, link_bw;
5312 bool is_dp = false, is_cpu_edp = false;
79e53945 5313
f48d8f23
PZ		 5314 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5315 switch (intel_encoder->type) {
a4fc5ed6
KP		 5316 case INTEL_OUTPUT_DISPLAYPORT:
5317 is_dp = true;
5318 break;
32f9d658 5319 case INTEL_OUTPUT_EDP:
e3aef172 5320 is_dp = true;
f48d8f23 5321 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5322 is_cpu_edp = true;
f48d8f23 5323 edp_encoder = intel_encoder;
32f9d658 5324 break;
79e53945 5325 }
79e53945 5326 }
61e9653f 5327
2c07245f 5328 /* FDI link */
8febb297
EA		 5329 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5330 lane = 0;
5331 /* CPU eDP doesn't require FDI link, so just set DP M/N
5332 according to current link config */
e3aef172 5333 if (is_cpu_edp) {
e3aef172 5334 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 5335 } else {
8febb297
EA		 5336 /* FDI is a binary signal running at ~2.7GHz, encoding
5337 * each output octet as 10 bits. The actual frequency
5338 * is stored as a divider into a 100MHz clock, and the
5339 * mode pixel clock is stored in units of 1KHz.
5340 * Hence the bw of each lane in terms of the mode signal
5341 * is:
5342 */
5343 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5344 }
58a27471 5345
94bf2ced
DV		 5346 /* [e]DP over FDI requires target mode clock instead of link clock. */
5347 if (edp_encoder)
5348 target_clock = intel_edp_target_clock(edp_encoder, mode);
5349 else if (is_dp)
5350 target_clock = mode->clock;
5351 else
5352 target_clock = adjusted_mode->clock;
5353
d4b1931c
PZ		 5354 if (!lane)
5355 lane = ironlake_get_lanes_required(target_clock, link_bw,
5356 intel_crtc->bpp);
2c07245f 5357
8febb297
EA		 5358 intel_crtc->fdi_lanes = lane;
5359
5360 if (pixel_multiplier > 1)
5361 link_bw *= pixel_multiplier;
e69d0bc1 5362 intel_link_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw, &m_n);
8febb297 5363
afe2fcf5
PZ		 5364 I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5365 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5366 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5367 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
f48d8f23
PZ		 5368}
5369
de13a2e3
PZ		 5370static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5371 struct drm_display_mode *adjusted_mode,
5372 intel_clock_t *clock, u32 fp)
79e53945 5373{
de13a2e3 5374 struct drm_crtc *crtc = &intel_crtc->base;
79e53945
JB		 5375 struct drm_device *dev = crtc->dev;
5376 struct drm_i915_private *dev_priv = dev->dev_private;
de13a2e3
PZ		 5377 struct intel_encoder *intel_encoder;
5378 uint32_t dpll;
5379 int factor, pixel_multiplier, num_connectors = 0;
5380 bool is_lvds = false, is_sdvo = false, is_tv = false;
5381 bool is_dp = false, is_cpu_edp = false;
79e53945 5382
de13a2e3
PZ		 5383 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5384 switch (intel_encoder->type) {
79e53945
JB		 5385 case INTEL_OUTPUT_LVDS:
5386 is_lvds = true;
5387 break;
5388 case INTEL_OUTPUT_SDVO:
7d57382e 5389 case INTEL_OUTPUT_HDMI:
79e53945 5390 is_sdvo = true;
de13a2e3 5391 if (intel_encoder->needs_tv_clock)
e2f0ba97 5392 is_tv = true;
79e53945 5393 break;
79e53945
JB		 5394 case INTEL_OUTPUT_TVOUT:
5395 is_tv = true;
5396 break;
a4fc5ed6
KP		 5397 case INTEL_OUTPUT_DISPLAYPORT:
5398 is_dp = true;
5399 break;
32f9d658 5400 case INTEL_OUTPUT_EDP:
e3aef172 5401 is_dp = true;
de13a2e3 5402 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
e3aef172 5403 is_cpu_edp = true;
32f9d658 5404 break;
79e53945 5405 }
43565a06 5406
c751ce4f 5407 num_connectors++;
79e53945 5408 }
79e53945 5409
c1858123 5410 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5411 factor = 21;
5412 if (is_lvds) {
5413 if ((intel_panel_use_ssc(dev_priv) &&
5414 dev_priv->lvds_ssc_freq == 100) ||
1974cad0 5415 intel_is_dual_link_lvds(dev))
8febb297
EA		 5416 factor = 25;
5417 } else if (is_sdvo && is_tv)
5418 factor = 20;
c1858123 5419
de13a2e3 5420 if (clock->m < factor * clock->n)
8febb297 5421 fp |= FP_CB_TUNE;
2c07245f 5422
5eddb70b 5423 dpll = 0;
2c07245f 5424
a07d6787
EA		 5425 if (is_lvds)
5426 dpll |= DPLLB_MODE_LVDS;
5427 else
5428 dpll |= DPLLB_MODE_DAC_SERIAL;
5429 if (is_sdvo) {
de13a2e3 5430 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
a07d6787
EA		 5431 if (pixel_multiplier > 1) {
5432 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5433 }
a07d6787
EA		 5434 dpll |= DPLL_DVO_HIGH_SPEED;
5435 }
e3aef172 5436 if (is_dp && !is_cpu_edp)
a07d6787 5437 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5438
a07d6787 5439 /* compute bitmask from p1 value */
de13a2e3 5440 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
a07d6787 5441 /* also FPA1 */
de13a2e3 5442 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
a07d6787 5443
de13a2e3 5444 switch (clock->p2) {
a07d6787
EA		 5445 case 5:
5446 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5447 break;
5448 case 7:
5449 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5450 break;
5451 case 10:
5452 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5453 break;
5454 case 14:
5455 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5456 break;
79e53945
JB		 5457 }
5458
43565a06
KH		 5459 if (is_sdvo && is_tv)
5460 dpll |= PLL_REF_INPUT_TVCLKINBC;
5461 else if (is_tv)
79e53945 5462 /* XXX: just matching BIOS for now */
43565a06 5463 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5464 dpll |= 3;
a7615030 5465 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5466 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5467 else
5468 dpll |= PLL_REF_INPUT_DREFCLK;
5469
de13a2e3
PZ		 5470 return dpll;
5471}
5472
5473static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5474 struct drm_display_mode *mode,
5475 struct drm_display_mode *adjusted_mode,
5476 int x, int y,
5477 struct drm_framebuffer *fb)
5478{
5479 struct drm_device *dev = crtc->dev;
5480 struct drm_i915_private *dev_priv = dev->dev_private;
5481 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5482 int pipe = intel_crtc->pipe;
5483 int plane = intel_crtc->plane;
5484 int num_connectors = 0;
5485 intel_clock_t clock, reduced_clock;
5486 u32 dpll, fp = 0, fp2 = 0;
e2f12b07
PZ		 5487 bool ok, has_reduced_clock = false;
5488 bool is_lvds = false, is_dp = false, is_cpu_edp = false;
de13a2e3 5489 struct intel_encoder *encoder;
de13a2e3 5490 int ret;
01a415fd 5491 bool dither, fdi_config_ok;
de13a2e3
PZ		 5492
5493 for_each_encoder_on_crtc(dev, crtc, encoder) {
5494 switch (encoder->type) {
5495 case INTEL_OUTPUT_LVDS:
5496 is_lvds = true;
5497 break;
de13a2e3
PZ		 5498 case INTEL_OUTPUT_DISPLAYPORT:
5499 is_dp = true;
5500 break;
5501 case INTEL_OUTPUT_EDP:
5502 is_dp = true;
e2f12b07 5503 if (!intel_encoder_is_pch_edp(&encoder->base))
de13a2e3
PZ		 5504 is_cpu_edp = true;
5505 break;
5506 }
5507
5508 num_connectors++;
a07d6787 5509 }
79e53945 5510
5dc5298b
PZ		 5511 WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5512 "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
a07d6787 5513
de13a2e3
PZ		 5514 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5515 &has_reduced_clock, &reduced_clock);
5516 if (!ok) {
5517 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5518 return -EINVAL;
79e53945
JB		 5519 }
5520
de13a2e3
PZ		 5521 /* Ensure that the cursor is valid for the new mode before changing... */
5522 intel_crtc_update_cursor(crtc, true);
5523
5524 /* determine panel color depth */
c8241969
JN		 5525 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5526 adjusted_mode);
de13a2e3
PZ		 5527 if (is_lvds && dev_priv->lvds_dither)
5528 dither = true;
5529
5530 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5531 if (has_reduced_clock)
5532 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5533 reduced_clock.m2;
5534
5535 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
79e53945 5536
f7cb34d4 5537 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5538 drm_mode_debug_printmodeline(mode);
5539
5dc5298b
PZ		 5540 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5541 if (!is_cpu_edp) {
ee7b9f93 5542 struct intel_pch_pll *pll;
4b645f14 5543
ee7b9f93
JB		 5544 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5545 if (pll == NULL) {
5546 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5547 pipe);
4b645f14
JB		 5548 return -EINVAL;
5549 }
ee7b9f93
JB		 5550 } else
5551 intel_put_pch_pll(intel_crtc);
79e53945 5552
2f0c2ad1 5553 if (is_dp && !is_cpu_edp)
a4fc5ed6 5554 intel_dp_set_m_n(crtc, mode, adjusted_mode);
79e53945 5555
dafd226c
DV		 5556 for_each_encoder_on_crtc(dev, crtc, encoder)
5557 if (encoder->pre_pll_enable)
5558 encoder->pre_pll_enable(encoder);
79e53945 5559
ee7b9f93
JB		 5560 if (intel_crtc->pch_pll) {
5561 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 5562
32f9d658 5563 /* Wait for the clocks to stabilize. */
ee7b9f93 5564 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 5565 udelay(150);
5566
8febb297
EA		 5567 /* The pixel multiplier can only be updated once the
5568 * DPLL is enabled and the clocks are stable.
5569 *
5570 * So write it again.
5571 */
ee7b9f93 5572 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 5573 }
79e53945 5574
5eddb70b 5575 intel_crtc->lowfreq_avail = false;
ee7b9f93 5576 if (intel_crtc->pch_pll) {
4b645f14 5577 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 5578 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 5579 intel_crtc->lowfreq_avail = true;
4b645f14 5580 } else {
ee7b9f93 5581 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 5582 }
5583 }
5584
b0e77b9c 5585 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5eddb70b 5586
01a415fd
DV		 5587 /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5588 * ironlake_check_fdi_lanes. */
f48d8f23 5589 ironlake_set_m_n(crtc, mode, adjusted_mode);
2c07245f 5590
01a415fd 5591 fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
2c07245f 5592
c8203565 5593 ironlake_set_pipeconf(crtc, adjusted_mode, dither);
79e53945 5594
9d0498a2 5595 intel_wait_for_vblank(dev, pipe);
79e53945 5596
a1f9e77e
PZ		 5597 /* Set up the display plane register */
5598 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
b24e7179 5599 POSTING_READ(DSPCNTR(plane));
79e53945 5600
94352cf9 5601 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5602
5603 intel_update_watermarks(dev);
5604
1f8eeabf
ED		 5605 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5606
01a415fd 5607 return fdi_config_ok ? ret : -EINVAL;
79e53945
JB		 5608}
5609
d6dd9eb1
DV		 5610static void haswell_modeset_global_resources(struct drm_device *dev)
5611{
5612 struct drm_i915_private *dev_priv = dev->dev_private;
5613 bool enable = false;
5614 struct intel_crtc *crtc;
5615 struct intel_encoder *encoder;
5616
5617 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
5618 if (crtc->pipe != PIPE_A && crtc->base.enabled)
5619 enable = true;
5620 /* XXX: Should check for edp transcoder here, but thanks to init
5621 * sequence that's not yet available. Just in case desktop eDP
5622 * on PORT D is possible on haswell, too. */
5623 }
5624
5625 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
5626 base.head) {
5627 if (encoder->type != INTEL_OUTPUT_EDP &&
5628 encoder->connectors_active)
5629 enable = true;
5630 }
5631
5632 /* Even the eDP panel fitter is outside the always-on well. */
5633 if (dev_priv->pch_pf_size)
5634 enable = true;
5635
5636 intel_set_power_well(dev, enable);
5637}
5638
09b4ddf9
PZ		 5639static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5640 struct drm_display_mode *mode,
5641 struct drm_display_mode *adjusted_mode,
5642 int x, int y,
5643 struct drm_framebuffer *fb)
5644{
5645 struct drm_device *dev = crtc->dev;
5646 struct drm_i915_private *dev_priv = dev->dev_private;
5647 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5648 int pipe = intel_crtc->pipe;
5649 int plane = intel_crtc->plane;
5650 int num_connectors = 0;
ed7ef439 5651 bool is_dp = false, is_cpu_edp = false;
09b4ddf9 5652 struct intel_encoder *encoder;
09b4ddf9
PZ		 5653 int ret;
5654 bool dither;
5655
5656 for_each_encoder_on_crtc(dev, crtc, encoder) {
5657 switch (encoder->type) {
09b4ddf9
PZ		 5658 case INTEL_OUTPUT_DISPLAYPORT:
5659 is_dp = true;
5660 break;
5661 case INTEL_OUTPUT_EDP:
5662 is_dp = true;
5663 if (!intel_encoder_is_pch_edp(&encoder->base))
5664 is_cpu_edp = true;
5665 break;
5666 }
5667
5668 num_connectors++;
5669 }
5670
5dc5298b
PZ		 5671 /* We are not sure yet this won't happen. */
5672 WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5673 INTEL_PCH_TYPE(dev));
5674
5675 WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5676 num_connectors, pipe_name(pipe));
5677
702e7a56 5678 WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
1ce42920
PZ		 5679 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5680
5681 WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5682
6441ab5f
PZ		 5683 if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5684 return -EINVAL;
5685
09b4ddf9
PZ		 5686 /* Ensure that the cursor is valid for the new mode before changing... */
5687 intel_crtc_update_cursor(crtc, true);
5688
5689 /* determine panel color depth */
c8241969
JN		 5690 dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5691 adjusted_mode);
09b4ddf9 5692
09b4ddf9
PZ		 5693 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5694 drm_mode_debug_printmodeline(mode);
5695
ed7ef439 5696 if (is_dp && !is_cpu_edp)
09b4ddf9 5697 intel_dp_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9
PZ		 5698
5699 intel_crtc->lowfreq_avail = false;
09b4ddf9
PZ		 5700
5701 intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5702
1eb8dfec
PZ		 5703 if (!is_dp || is_cpu_edp)
5704 ironlake_set_m_n(crtc, mode, adjusted_mode);
09b4ddf9 5705
ee2b0b38 5706 haswell_set_pipeconf(crtc, adjusted_mode, dither);
09b4ddf9 5707
09b4ddf9
PZ		 5708 /* Set up the display plane register */
5709 I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5710 POSTING_READ(DSPCNTR(plane));
5711
5712 ret = intel_pipe_set_base(crtc, x, y, fb);
5713
5714 intel_update_watermarks(dev);
5715
5716 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5717
1f803ee5 5718 return ret;
79e53945
JB		 5719}
5720
f564048e
EA		 5721static int intel_crtc_mode_set(struct drm_crtc *crtc,
5722 struct drm_display_mode *mode,
5723 struct drm_display_mode *adjusted_mode,
5724 int x, int y,
94352cf9 5725 struct drm_framebuffer *fb)
f564048e
EA		 5726{
5727 struct drm_device *dev = crtc->dev;
5728 struct drm_i915_private *dev_priv = dev->dev_private;
9256aa19
DV		 5729 struct drm_encoder_helper_funcs *encoder_funcs;
5730 struct intel_encoder *encoder;
0b701d27
EA		 5731 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5732 int pipe = intel_crtc->pipe;
f564048e
EA		 5733 int ret;
5734
cc464b2a
PZ		 5735 if (IS_HASWELL(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
5736 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5737 else
5738 intel_crtc->cpu_transcoder = pipe;
5739
0b701d27 5740 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5741
f564048e 5742 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5743 x, y, fb);
79e53945 5744 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5745
9256aa19
DV		 5746 if (ret != 0)
5747 return ret;
5748
5749 for_each_encoder_on_crtc(dev, crtc, encoder) {
5750 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5751 encoder->base.base.id,
5752 drm_get_encoder_name(&encoder->base),
5753 mode->base.id, mode->name);
5754 encoder_funcs = encoder->base.helper_private;
5755 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5756 }
5757
5758 return 0;
79e53945
JB		 5759}
5760
3a9627f4
WF		 5761static bool intel_eld_uptodate(struct drm_connector *connector,
5762 int reg_eldv, uint32_t bits_eldv,
5763 int reg_elda, uint32_t bits_elda,
5764 int reg_edid)
5765{
5766 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5767 uint8_t *eld = connector->eld;
5768 uint32_t i;
5769
5770 i = I915_READ(reg_eldv);
5771 i &= bits_eldv;
5772
5773 if (!eld[0])
5774 return !i;
5775
5776 if (!i)
5777 return false;
5778
5779 i = I915_READ(reg_elda);
5780 i &= ~bits_elda;
5781 I915_WRITE(reg_elda, i);
5782
5783 for (i = 0; i < eld[2]; i++)
5784 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5785 return false;
5786
5787 return true;
5788}
5789
e0dac65e
WF		 5790static void g4x_write_eld(struct drm_connector *connector,
5791 struct drm_crtc *crtc)
5792{
5793 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5794 uint8_t *eld = connector->eld;
5795 uint32_t eldv;
5796 uint32_t len;
5797 uint32_t i;
5798
5799 i = I915_READ(G4X_AUD_VID_DID);
5800
5801 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5802 eldv = G4X_ELDV_DEVCL_DEVBLC;
5803 else
5804 eldv = G4X_ELDV_DEVCTG;
5805
3a9627f4
WF		 5806 if (intel_eld_uptodate(connector,
5807 G4X_AUD_CNTL_ST, eldv,
5808 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5809 G4X_HDMIW_HDMIEDID))
5810 return;
5811
e0dac65e
WF		 5812 i = I915_READ(G4X_AUD_CNTL_ST);
5813 i &= ~(eldv | G4X_ELD_ADDR);
5814 len = (i >> 9) & 0x1f; /* ELD buffer size */
5815 I915_WRITE(G4X_AUD_CNTL_ST, i);
5816
5817 if (!eld[0])
5818 return;
5819
5820 len = min_t(uint8_t, eld[2], len);
5821 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5822 for (i = 0; i < len; i++)
5823 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5824
5825 i = I915_READ(G4X_AUD_CNTL_ST);
5826 i |= eldv;
5827 I915_WRITE(G4X_AUD_CNTL_ST, i);
5828}
5829
83358c85
WX		 5830static void haswell_write_eld(struct drm_connector *connector,
5831 struct drm_crtc *crtc)
5832{
5833 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5834 uint8_t *eld = connector->eld;
5835 struct drm_device *dev = crtc->dev;
7b9f35a6 5836 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
83358c85
WX		 5837 uint32_t eldv;
5838 uint32_t i;
5839 int len;
5840 int pipe = to_intel_crtc(crtc)->pipe;
5841 int tmp;
5842
5843 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5844 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5845 int aud_config = HSW_AUD_CFG(pipe);
5846 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5847
5848
5849 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5850
5851 /* Audio output enable */
5852 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5853 tmp = I915_READ(aud_cntrl_st2);
5854 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5855 I915_WRITE(aud_cntrl_st2, tmp);
5856
5857 /* Wait for 1 vertical blank */
5858 intel_wait_for_vblank(dev, pipe);
5859
5860 /* Set ELD valid state */
5861 tmp = I915_READ(aud_cntrl_st2);
5862 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5863 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5864 I915_WRITE(aud_cntrl_st2, tmp);
5865 tmp = I915_READ(aud_cntrl_st2);
5866 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5867
5868 /* Enable HDMI mode */
5869 tmp = I915_READ(aud_config);
5870 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5871 /* clear N_programing_enable and N_value_index */
5872 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5873 I915_WRITE(aud_config, tmp);
5874
5875 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5876
5877 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
7b9f35a6 5878 intel_crtc->eld_vld = true;
83358c85
WX		 5879
5880 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5881 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5882 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5883 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5884 } else
5885 I915_WRITE(aud_config, 0);
5886
5887 if (intel_eld_uptodate(connector,
5888 aud_cntrl_st2, eldv,
5889 aud_cntl_st, IBX_ELD_ADDRESS,
5890 hdmiw_hdmiedid))
5891 return;
5892
5893 i = I915_READ(aud_cntrl_st2);
5894 i &= ~eldv;
5895 I915_WRITE(aud_cntrl_st2, i);
5896
5897 if (!eld[0])
5898 return;
5899
5900 i = I915_READ(aud_cntl_st);
5901 i &= ~IBX_ELD_ADDRESS;
5902 I915_WRITE(aud_cntl_st, i);
5903 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5904 DRM_DEBUG_DRIVER("port num:%d\n", i);
5905
5906 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5907 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5908 for (i = 0; i < len; i++)
5909 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5910
5911 i = I915_READ(aud_cntrl_st2);
5912 i |= eldv;
5913 I915_WRITE(aud_cntrl_st2, i);
5914
5915}
5916
e0dac65e
WF		 5917static void ironlake_write_eld(struct drm_connector *connector,
5918 struct drm_crtc *crtc)
5919{
5920 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5921 uint8_t *eld = connector->eld;
5922 uint32_t eldv;
5923 uint32_t i;
5924 int len;
5925 int hdmiw_hdmiedid;
b6daa025 5926 int aud_config;
e0dac65e
WF		 5927 int aud_cntl_st;
5928 int aud_cntrl_st2;
9b138a83 5929 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5930
b3f33cbf 5931 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5932 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5933 aud_config = IBX_AUD_CFG(pipe);
5934 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5935 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5936 } else {
9b138a83
WX		 5937 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5938 aud_config = CPT_AUD_CFG(pipe);
5939 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5940 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5941 }
5942
9b138a83 5943 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5944
5945 i = I915_READ(aud_cntl_st);
9b138a83 5946 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5947 if (!i) {
5948 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5949 /* operate blindly on all ports */
1202b4c6
WF		 5950 eldv = IBX_ELD_VALIDB;
5951 eldv |= IBX_ELD_VALIDB << 4;
5952 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5953 } else {
5954 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5955 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5956 }
5957
3a9627f4
WF		 5958 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5959 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5960 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5961 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5962 } else
5963 I915_WRITE(aud_config, 0);
e0dac65e 5964
3a9627f4
WF		 5965 if (intel_eld_uptodate(connector,
5966 aud_cntrl_st2, eldv,
5967 aud_cntl_st, IBX_ELD_ADDRESS,
5968 hdmiw_hdmiedid))
5969 return;
5970
e0dac65e
WF		 5971 i = I915_READ(aud_cntrl_st2);
5972 i &= ~eldv;
5973 I915_WRITE(aud_cntrl_st2, i);
5974
5975 if (!eld[0])
5976 return;
5977
e0dac65e 5978 i = I915_READ(aud_cntl_st);
1202b4c6 5979 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 5980 I915_WRITE(aud_cntl_st, i);
5981
5982 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5983 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5984 for (i = 0; i < len; i++)
5985 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5986
5987 i = I915_READ(aud_cntrl_st2);
5988 i |= eldv;
5989 I915_WRITE(aud_cntrl_st2, i);
5990}
5991
5992void intel_write_eld(struct drm_encoder *encoder,
5993 struct drm_display_mode *mode)
5994{
5995 struct drm_crtc *crtc = encoder->crtc;
5996 struct drm_connector *connector;
5997 struct drm_device *dev = encoder->dev;
5998 struct drm_i915_private *dev_priv = dev->dev_private;
5999
6000 connector = drm_select_eld(encoder, mode);
6001 if (!connector)
6002 return;
6003
6004 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6005 connector->base.id,
6006 drm_get_connector_name(connector),
6007 connector->encoder->base.id,
6008 drm_get_encoder_name(connector->encoder));
6009
6010 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6011
6012 if (dev_priv->display.write_eld)
6013 dev_priv->display.write_eld(connector, crtc);
6014}
6015
79e53945
JB		 6016/** Loads the palette/gamma unit for the CRTC with the prepared values */
6017void intel_crtc_load_lut(struct drm_crtc *crtc)
6018{
6019 struct drm_device *dev = crtc->dev;
6020 struct drm_i915_private *dev_priv = dev->dev_private;
6021 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6022 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6023 int i;
6024
6025 /* The clocks have to be on to load the palette. */
aed3f09d 6026 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 6027 return;
6028
f2b115e6 6029 /* use legacy palette for Ironlake */
bad720ff 6030 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6031 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6032
79e53945
JB		 6033 for (i = 0; i < 256; i++) {
6034 I915_WRITE(palreg + 4 * i,
6035 (intel_crtc->lut_r[i] << 16) |
6036 (intel_crtc->lut_g[i] << 8) |
6037 intel_crtc->lut_b[i]);
6038 }
6039}
6040
560b85bb
CW		 6041static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6042{
6043 struct drm_device *dev = crtc->dev;
6044 struct drm_i915_private *dev_priv = dev->dev_private;
6045 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6046 bool visible = base != 0;
6047 u32 cntl;
6048
6049 if (intel_crtc->cursor_visible == visible)
6050 return;
6051
9db4a9c7 6052 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6053 if (visible) {
6054 /* On these chipsets we can only modify the base whilst
6055 * the cursor is disabled.
6056 */
9db4a9c7 6057 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6058
6059 cntl &= ~(CURSOR_FORMAT_MASK);
6060 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6061 cntl |= CURSOR_ENABLE |
6062 CURSOR_GAMMA_ENABLE |
6063 CURSOR_FORMAT_ARGB;
6064 } else
6065 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6066 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6067
6068 intel_crtc->cursor_visible = visible;
6069}
6070
6071static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6072{
6073 struct drm_device *dev = crtc->dev;
6074 struct drm_i915_private *dev_priv = dev->dev_private;
6075 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6076 int pipe = intel_crtc->pipe;
6077 bool visible = base != 0;
6078
6079 if (intel_crtc->cursor_visible != visible) {
548f245b 6080 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6081 if (base) {
6082 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6083 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6084 cntl |= pipe << 28; /* Connect to correct pipe */
6085 } else {
6086 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6087 cntl |= CURSOR_MODE_DISABLE;
6088 }
9db4a9c7 6089 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6090
6091 intel_crtc->cursor_visible = visible;
6092 }
6093 /* and commit changes on next vblank */
9db4a9c7 6094 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6095}
6096
65a21cd6
JB		 6097static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6098{
6099 struct drm_device *dev = crtc->dev;
6100 struct drm_i915_private *dev_priv = dev->dev_private;
6101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6102 int pipe = intel_crtc->pipe;
6103 bool visible = base != 0;
6104
6105 if (intel_crtc->cursor_visible != visible) {
6106 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6107 if (base) {
6108 cntl &= ~CURSOR_MODE;
6109 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6110 } else {
6111 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6112 cntl |= CURSOR_MODE_DISABLE;
6113 }
6114 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6115
6116 intel_crtc->cursor_visible = visible;
6117 }
6118 /* and commit changes on next vblank */
6119 I915_WRITE(CURBASE_IVB(pipe), base);
6120}
6121
cda4b7d3 6122/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6123static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6124 bool on)
cda4b7d3
CW		 6125{
6126 struct drm_device *dev = crtc->dev;
6127 struct drm_i915_private *dev_priv = dev->dev_private;
6128 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6129 int pipe = intel_crtc->pipe;
6130 int x = intel_crtc->cursor_x;
6131 int y = intel_crtc->cursor_y;
560b85bb 6132 u32 base, pos;
cda4b7d3
CW		 6133 bool visible;
6134
6135 pos = 0;
6136
6b383a7f 6137 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6138 base = intel_crtc->cursor_addr;
6139 if (x > (int) crtc->fb->width)
6140 base = 0;
6141
6142 if (y > (int) crtc->fb->height)
6143 base = 0;
6144 } else
6145 base = 0;
6146
6147 if (x < 0) {
6148 if (x + intel_crtc->cursor_width < 0)
6149 base = 0;
6150
6151 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6152 x = -x;
6153 }
6154 pos |= x << CURSOR_X_SHIFT;
6155
6156 if (y < 0) {
6157 if (y + intel_crtc->cursor_height < 0)
6158 base = 0;
6159
6160 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6161 y = -y;
6162 }
6163 pos |= y << CURSOR_Y_SHIFT;
6164
6165 visible = base != 0;
560b85bb 6166 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6167 return;
6168
0cd83aa9 6169 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 6170 I915_WRITE(CURPOS_IVB(pipe), pos);
6171 ivb_update_cursor(crtc, base);
6172 } else {
6173 I915_WRITE(CURPOS(pipe), pos);
6174 if (IS_845G(dev) || IS_I865G(dev))
6175 i845_update_cursor(crtc, base);
6176 else
6177 i9xx_update_cursor(crtc, base);
6178 }
cda4b7d3
CW		 6179}
6180
79e53945 6181static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6182 struct drm_file *file,
79e53945
JB		 6183 uint32_t handle,
6184 uint32_t width, uint32_t height)
6185{
6186 struct drm_device *dev = crtc->dev;
6187 struct drm_i915_private *dev_priv = dev->dev_private;
6188 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6189 struct drm_i915_gem_object *obj;
cda4b7d3 6190 uint32_t addr;
3f8bc370 6191 int ret;
79e53945 6192
79e53945
JB		 6193 /* if we want to turn off the cursor ignore width and height */
6194 if (!handle) {
28c97730 6195 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6196 addr = 0;
05394f39 6197 obj = NULL;
5004417d 6198 mutex_lock(&dev->struct_mutex);
3f8bc370 6199 goto finish;
79e53945
JB		 6200 }
6201
6202 /* Currently we only support 64x64 cursors */
6203 if (width != 64 || height != 64) {
6204 DRM_ERROR("we currently only support 64x64 cursors\n");
6205 return -EINVAL;
6206 }
6207
05394f39 6208 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6209 if (&obj->base == NULL)
79e53945
JB		 6210 return -ENOENT;
6211
05394f39 6212 if (obj->base.size < width * height * 4) {
79e53945 6213 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6214 ret = -ENOMEM;
6215 goto fail;
79e53945
JB		 6216 }
6217
71acb5eb 6218 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6219 mutex_lock(&dev->struct_mutex);
b295d1b6 6220 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6221 if (obj->tiling_mode) {
6222 DRM_ERROR("cursor cannot be tiled\n");
6223 ret = -EINVAL;
6224 goto fail_locked;
6225 }
6226
2da3b9b9 6227 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6228 if (ret) {
6229 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6230 goto fail_locked;
e7b526bb
CW		 6231 }
6232
d9e86c0e
CW		 6233 ret = i915_gem_object_put_fence(obj);
6234 if (ret) {
2da3b9b9 6235 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6236 goto fail_unpin;
6237 }
6238
05394f39 6239 addr = obj->gtt_offset;
71acb5eb 6240 } else {
6eeefaf3 6241 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6242 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6243 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6244 align);
71acb5eb
DA		 6245 if (ret) {
6246 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6247 goto fail_locked;
71acb5eb 6248 }
05394f39 6249 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6250 }
6251
a6c45cf0 6252 if (IS_GEN2(dev))
14b60391
JB		 6253 I915_WRITE(CURSIZE, (height << 12) | width);
6254
3f8bc370 6255 finish:
3f8bc370 6256 if (intel_crtc->cursor_bo) {
b295d1b6 6257 if (dev_priv->info->cursor_needs_physical) {
05394f39 6258 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6259 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6260 } else
6261 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6262 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6263 }
80824003 6264
7f9872e0 6265 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6266
6267 intel_crtc->cursor_addr = addr;
05394f39 6268 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6269 intel_crtc->cursor_width = width;
6270 intel_crtc->cursor_height = height;
6271
6b383a7f 6272 intel_crtc_update_cursor(crtc, true);
3f8bc370 6273
79e53945 6274 return 0;
e7b526bb 6275fail_unpin:
05394f39 6276 i915_gem_object_unpin(obj);
7f9872e0 6277fail_locked:
34b8686e 6278 mutex_unlock(&dev->struct_mutex);
bc9025bd 6279fail:
05394f39 6280 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6281 return ret;
79e53945
JB		 6282}
6283
6284static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6285{
79e53945 6286 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6287
cda4b7d3
CW		 6288 intel_crtc->cursor_x = x;
6289 intel_crtc->cursor_y = y;
652c393a 6290
6b383a7f 6291 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6292
6293 return 0;
6294}
6295
6296/** Sets the color ramps on behalf of RandR */
6297void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6298 u16 blue, int regno)
6299{
6300 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6301
6302 intel_crtc->lut_r[regno] = red >> 8;
6303 intel_crtc->lut_g[regno] = green >> 8;
6304 intel_crtc->lut_b[regno] = blue >> 8;
6305}
6306
b8c00ac5
DA		 6307void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6308 u16 *blue, int regno)
6309{
6310 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6311
6312 *red = intel_crtc->lut_r[regno] << 8;
6313 *green = intel_crtc->lut_g[regno] << 8;
6314 *blue = intel_crtc->lut_b[regno] << 8;
6315}
6316
79e53945 6317static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6318 u16 *blue, uint32_t start, uint32_t size)
79e53945 6319{
7203425a 6320 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6321 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6322
7203425a 6323 for (i = start; i < end; i++) {
79e53945
JB		 6324 intel_crtc->lut_r[i] = red[i] >> 8;
6325 intel_crtc->lut_g[i] = green[i] >> 8;
6326 intel_crtc->lut_b[i] = blue[i] >> 8;
6327 }
6328
6329 intel_crtc_load_lut(crtc);
6330}
6331
6332/**
6333 * Get a pipe with a simple mode set on it for doing load-based monitor
6334 * detection.
6335 *
6336 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6337 * its requirements. The pipe will be connected to no other encoders.
79e53945 6338 *
c751ce4f 6339 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6340 * configured for it. In the future, it could choose to temporarily disable
6341 * some outputs to free up a pipe for its use.
6342 *
6343 * \return crtc, or NULL if no pipes are available.
6344 */
6345
6346/* VESA 640x480x72Hz mode to set on the pipe */
6347static struct drm_display_mode load_detect_mode = {
6348 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6349 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6350};
6351
d2dff872
CW		 6352static struct drm_framebuffer *
6353intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6354 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6355 struct drm_i915_gem_object *obj)
6356{
6357 struct intel_framebuffer *intel_fb;
6358 int ret;
6359
6360 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6361 if (!intel_fb) {
6362 drm_gem_object_unreference_unlocked(&obj->base);
6363 return ERR_PTR(-ENOMEM);
6364 }
6365
6366 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6367 if (ret) {
6368 drm_gem_object_unreference_unlocked(&obj->base);
6369 kfree(intel_fb);
6370 return ERR_PTR(ret);
6371 }
6372
6373 return &intel_fb->base;
6374}
6375
6376static u32
6377intel_framebuffer_pitch_for_width(int width, int bpp)
6378{
6379 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6380 return ALIGN(pitch, 64);
6381}
6382
6383static u32
6384intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6385{
6386 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6387 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6388}
6389
6390static struct drm_framebuffer *
6391intel_framebuffer_create_for_mode(struct drm_device *dev,
6392 struct drm_display_mode *mode,
6393 int depth, int bpp)
6394{
6395 struct drm_i915_gem_object *obj;
0fed39bd 6396 struct drm_mode_fb_cmd2 mode_cmd = { 0 };
d2dff872
CW		 6397
6398 obj = i915_gem_alloc_object(dev,
6399 intel_framebuffer_size_for_mode(mode, bpp));
6400 if (obj == NULL)
6401 return ERR_PTR(-ENOMEM);
6402
6403 mode_cmd.width = mode->hdisplay;
6404 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6405 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6406 bpp);
5ca0c34a 6407 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 6408
6409 return intel_framebuffer_create(dev, &mode_cmd, obj);
6410}
6411
6412static struct drm_framebuffer *
6413mode_fits_in_fbdev(struct drm_device *dev,
6414 struct drm_display_mode *mode)
6415{
6416 struct drm_i915_private *dev_priv = dev->dev_private;
6417 struct drm_i915_gem_object *obj;
6418 struct drm_framebuffer *fb;
6419
6420 if (dev_priv->fbdev == NULL)
6421 return NULL;
6422
6423 obj = dev_priv->fbdev->ifb.obj;
6424 if (obj == NULL)
6425 return NULL;
6426
6427 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6428 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6429 fb->bits_per_pixel))
d2dff872
CW		 6430 return NULL;
6431
01f2c773 6432 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6433 return NULL;
6434
6435 return fb;
6436}
6437
d2434ab7 6438bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 6439 struct drm_display_mode *mode,
8261b191 6440 struct intel_load_detect_pipe *old)
79e53945
JB		 6441{
6442 struct intel_crtc *intel_crtc;
d2434ab7
DV		 6443 struct intel_encoder *intel_encoder =
6444 intel_attached_encoder(connector);
79e53945 6445 struct drm_crtc *possible_crtc;
4ef69c7a 6446 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6447 struct drm_crtc *crtc = NULL;
6448 struct drm_device *dev = encoder->dev;
94352cf9 6449 struct drm_framebuffer *fb;
79e53945
JB		 6450 int i = -1;
6451
d2dff872
CW		 6452 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6453 connector->base.id, drm_get_connector_name(connector),
6454 encoder->base.id, drm_get_encoder_name(encoder));
6455
79e53945
JB		 6456 /*
6457 * Algorithm gets a little messy:
7a5e4805 6458 *
79e53945
JB		 6459 * - if the connector already has an assigned crtc, use it (but make
6460 * sure it's on first)
7a5e4805 6461 *
79e53945
JB		 6462 * - try to find the first unused crtc that can drive this connector,
6463 * and use that if we find one
79e53945
JB		 6464 */
6465
6466 /* See if we already have a CRTC for this connector */
6467 if (encoder->crtc) {
6468 crtc = encoder->crtc;
8261b191 6469
24218aac 6470 old->dpms_mode = connector->dpms;
8261b191
CW		 6471 old->load_detect_temp = false;
6472
6473 /* Make sure the crtc and connector are running */
24218aac
DV		 6474 if (connector->dpms != DRM_MODE_DPMS_ON)
6475 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 6476
7173188d 6477 return true;
79e53945
JB		 6478 }
6479
6480 /* Find an unused one (if possible) */
6481 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6482 i++;
6483 if (!(encoder->possible_crtcs & (1 << i)))
6484 continue;
6485 if (!possible_crtc->enabled) {
6486 crtc = possible_crtc;
6487 break;
6488 }
79e53945
JB		 6489 }
6490
6491 /*
6492 * If we didn't find an unused CRTC, don't use any.
6493 */
6494 if (!crtc) {
7173188d
CW		 6495 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6496 return false;
79e53945
JB		 6497 }
6498
fc303101
DV		 6499 intel_encoder->new_crtc = to_intel_crtc(crtc);
6500 to_intel_connector(connector)->new_encoder = intel_encoder;
79e53945
JB		 6501
6502 intel_crtc = to_intel_crtc(crtc);
24218aac 6503 old->dpms_mode = connector->dpms;
8261b191 6504 old->load_detect_temp = true;
d2dff872 6505 old->release_fb = NULL;
79e53945 6506
6492711d
CW		 6507 if (!mode)
6508 mode = &load_detect_mode;
79e53945 6509
d2dff872
CW		 6510 /* We need a framebuffer large enough to accommodate all accesses
6511 * that the plane may generate whilst we perform load detection.
6512 * We can not rely on the fbcon either being present (we get called
6513 * during its initialisation to detect all boot displays, or it may
6514 * not even exist) or that it is large enough to satisfy the
6515 * requested mode.
6516 */
94352cf9
DV		 6517 fb = mode_fits_in_fbdev(dev, mode);
6518 if (fb == NULL) {
d2dff872 6519 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 6520 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6521 old->release_fb = fb;
d2dff872
CW		 6522 } else
6523 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 6524 if (IS_ERR(fb)) {
d2dff872 6525 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
0e8b3d3e 6526 return false;
79e53945 6527 }
79e53945 6528
c0c36b94 6529 if (intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 6530 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6531 if (old->release_fb)
6532 old->release_fb->funcs->destroy(old->release_fb);
0e8b3d3e 6533 return false;
79e53945 6534 }
7173188d 6535
79e53945 6536 /* let the connector get through one full cycle before testing */
9d0498a2 6537 intel_wait_for_vblank(dev, intel_crtc->pipe);
7173188d 6538 return true;
79e53945
JB		 6539}
6540
d2434ab7 6541void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 6542 struct intel_load_detect_pipe *old)
79e53945 6543{
d2434ab7
DV		 6544 struct intel_encoder *intel_encoder =
6545 intel_attached_encoder(connector);
4ef69c7a 6546 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 6547
d2dff872
CW		 6548 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6549 connector->base.id, drm_get_connector_name(connector),
6550 encoder->base.id, drm_get_encoder_name(encoder));
6551
8261b191 6552 if (old->load_detect_temp) {
fc303101
DV		 6553 struct drm_crtc *crtc = encoder->crtc;
6554
6555 to_intel_connector(connector)->new_encoder = NULL;
6556 intel_encoder->new_crtc = NULL;
6557 intel_set_mode(crtc, NULL, 0, 0, NULL);
d2dff872
CW		 6558
6559 if (old->release_fb)
6560 old->release_fb->funcs->destroy(old->release_fb);
6561
0622a53c 6562 return;
79e53945
JB		 6563 }
6564
c751ce4f 6565 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 6566 if (old->dpms_mode != DRM_MODE_DPMS_ON)
6567 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 6568}
6569
6570/* Returns the clock of the currently programmed mode of the given pipe. */
6571static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6572{
6573 struct drm_i915_private *dev_priv = dev->dev_private;
6574 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6575 int pipe = intel_crtc->pipe;
548f245b 6576 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6577 u32 fp;
6578 intel_clock_t clock;
6579
6580 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6581 fp = I915_READ(FP0(pipe));
79e53945 6582 else
39adb7a5 6583 fp = I915_READ(FP1(pipe));
79e53945
JB		 6584
6585 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6586 if (IS_PINEVIEW(dev)) {
6587 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6588 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6589 } else {
6590 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6591 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6592 }
6593
a6c45cf0 6594 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6595 if (IS_PINEVIEW(dev))
6596 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6597 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6598 else
6599 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6600 DPLL_FPA01_P1_POST_DIV_SHIFT);
6601
6602 switch (dpll & DPLL_MODE_MASK) {
6603 case DPLLB_MODE_DAC_SERIAL:
6604 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6605 5 : 10;
6606 break;
6607 case DPLLB_MODE_LVDS:
6608 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6609 7 : 14;
6610 break;
6611 default:
28c97730 6612 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6613 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6614 return 0;
6615 }
6616
6617 /* XXX: Handle the 100Mhz refclk */
2177832f 6618 intel_clock(dev, 96000, &clock);
79e53945
JB		 6619 } else {
6620 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6621
6622 if (is_lvds) {
6623 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6624 DPLL_FPA01_P1_POST_DIV_SHIFT);
6625 clock.p2 = 14;
6626
6627 if ((dpll & PLL_REF_INPUT_MASK) ==
6628 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6629 /* XXX: might not be 66MHz */
2177832f 6630 intel_clock(dev, 66000, &clock);
79e53945 6631 } else
2177832f 6632 intel_clock(dev, 48000, &clock);
79e53945
JB		 6633 } else {
6634 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6635 clock.p1 = 2;
6636 else {
6637 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6638 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6639 }
6640 if (dpll & PLL_P2_DIVIDE_BY_4)
6641 clock.p2 = 4;
6642 else
6643 clock.p2 = 2;
6644
2177832f 6645 intel_clock(dev, 48000, &clock);
79e53945
JB		 6646 }
6647 }
6648
6649 /* XXX: It would be nice to validate the clocks, but we can't reuse
6650 * i830PllIsValid() because it relies on the xf86_config connector
6651 * configuration being accurate, which it isn't necessarily.
6652 */
6653
6654 return clock.dot;
6655}
6656
6657/** Returns the currently programmed mode of the given pipe. */
6658struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6659 struct drm_crtc *crtc)
6660{
548f245b 6661 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 6662 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fe2b8f9d 6663 enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
79e53945 6664 struct drm_display_mode *mode;
fe2b8f9d
PZ		 6665 int htot = I915_READ(HTOTAL(cpu_transcoder));
6666 int hsync = I915_READ(HSYNC(cpu_transcoder));
6667 int vtot = I915_READ(VTOTAL(cpu_transcoder));
6668 int vsync = I915_READ(VSYNC(cpu_transcoder));
79e53945
JB		 6669
6670 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6671 if (!mode)
6672 return NULL;
6673
6674 mode->clock = intel_crtc_clock_get(dev, crtc);
6675 mode->hdisplay = (htot & 0xffff) + 1;
6676 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6677 mode->hsync_start = (hsync & 0xffff) + 1;
6678 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6679 mode->vdisplay = (vtot & 0xffff) + 1;
6680 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6681 mode->vsync_start = (vsync & 0xffff) + 1;
6682 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6683
6684 drm_mode_set_name(mode);
79e53945
JB		 6685
6686 return mode;
6687}
6688
3dec0095 6689static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6690{
6691 struct drm_device *dev = crtc->dev;
6692 drm_i915_private_t *dev_priv = dev->dev_private;
6693 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6694 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6695 int dpll_reg = DPLL(pipe);
6696 int dpll;
652c393a 6697
bad720ff 6698 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6699 return;
6700
6701 if (!dev_priv->lvds_downclock_avail)
6702 return;
6703
dbdc6479 6704 dpll = I915_READ(dpll_reg);
652c393a 6705 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6706 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 6707
8ac5a6d5 6708 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 6709
6710 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6711 I915_WRITE(dpll_reg, dpll);
9d0498a2 6712 intel_wait_for_vblank(dev, pipe);
dbdc6479 6713
652c393a
JB		 6714 dpll = I915_READ(dpll_reg);
6715 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6716 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 6717 }
652c393a
JB		 6718}
6719
6720static void intel_decrease_pllclock(struct drm_crtc *crtc)
6721{
6722 struct drm_device *dev = crtc->dev;
6723 drm_i915_private_t *dev_priv = dev->dev_private;
6724 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6725
bad720ff 6726 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6727 return;
6728
6729 if (!dev_priv->lvds_downclock_avail)
6730 return;
6731
6732 /*
6733 * Since this is called by a timer, we should never get here in
6734 * the manual case.
6735 */
6736 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6737 int pipe = intel_crtc->pipe;
6738 int dpll_reg = DPLL(pipe);
6739 int dpll;
f6e5b160 6740
44d98a61 6741 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6742
8ac5a6d5 6743 assert_panel_unlocked(dev_priv, pipe);
652c393a 6744
dc257cf1 6745 dpll = I915_READ(dpll_reg);
652c393a
JB		 6746 dpll |= DISPLAY_RATE_SELECT_FPA1;
6747 I915_WRITE(dpll_reg, dpll);
9d0498a2 6748 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6749 dpll = I915_READ(dpll_reg);
6750 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6751 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6752 }
6753
6754}
6755
f047e395
CW		 6756void intel_mark_busy(struct drm_device *dev)
6757{
f047e395
CW		 6758 i915_update_gfx_val(dev->dev_private);
6759}
6760
6761void intel_mark_idle(struct drm_device *dev)
652c393a 6762{
652c393a 6763 struct drm_crtc *crtc;
652c393a
JB		 6764
6765 if (!i915_powersave)
6766 return;
6767
652c393a 6768 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6769 if (!crtc->fb)
6770 continue;
6771
725a5b54 6772 intel_decrease_pllclock(crtc);
652c393a 6773 }
652c393a
JB		 6774}
6775
725a5b54 6776void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
652c393a 6777{
f047e395
CW		 6778 struct drm_device *dev = obj->base.dev;
6779 struct drm_crtc *crtc;
652c393a 6780
f047e395 6781 if (!i915_powersave)
acb87dfb
CW		 6782 return;
6783
652c393a
JB		 6784 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6785 if (!crtc->fb)
6786 continue;
6787
f047e395 6788 if (to_intel_framebuffer(crtc->fb)->obj == obj)
725a5b54 6789 intel_increase_pllclock(crtc);
652c393a
JB		 6790 }
6791}
6792
79e53945
JB		 6793static void intel_crtc_destroy(struct drm_crtc *crtc)
6794{
6795 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6796 struct drm_device *dev = crtc->dev;
6797 struct intel_unpin_work *work;
6798 unsigned long flags;
6799
6800 spin_lock_irqsave(&dev->event_lock, flags);
6801 work = intel_crtc->unpin_work;
6802 intel_crtc->unpin_work = NULL;
6803 spin_unlock_irqrestore(&dev->event_lock, flags);
6804
6805 if (work) {
6806 cancel_work_sync(&work->work);
6807 kfree(work);
6808 }
79e53945
JB		 6809
6810 drm_crtc_cleanup(crtc);
67e77c5a 6811
79e53945
JB		 6812 kfree(intel_crtc);
6813}
6814
6b95a207
KH		 6815static void intel_unpin_work_fn(struct work_struct *__work)
6816{
6817 struct intel_unpin_work *work =
6818 container_of(__work, struct intel_unpin_work, work);
b4a98e57 6819 struct drm_device *dev = work->crtc->dev;
6b95a207 6820
b4a98e57 6821 mutex_lock(&dev->struct_mutex);
1690e1eb 6822 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6823 drm_gem_object_unreference(&work->pending_flip_obj->base);
6824 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6825
b4a98e57
CW		 6826 intel_update_fbc(dev);
6827 mutex_unlock(&dev->struct_mutex);
6828
6829 BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6830 atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6831
6b95a207
KH		 6832 kfree(work);
6833}
6834
1afe3e9d 6835static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6836 struct drm_crtc *crtc)
6b95a207
KH		 6837{
6838 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6839 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6840 struct intel_unpin_work *work;
05394f39 6841 struct drm_i915_gem_object *obj;
6b95a207
KH		 6842 unsigned long flags;
6843
6844 /* Ignore early vblank irqs */
6845 if (intel_crtc == NULL)
6846 return;
6847
6848 spin_lock_irqsave(&dev->event_lock, flags);
6849 work = intel_crtc->unpin_work;
e7d841ca
CW		 6850
6851 /* Ensure we don't miss a work->pending update ... */
6852 smp_rmb();
6853
6854 if (work == NULL || atomic_read(&work->pending) < INTEL_FLIP_COMPLETE) {
6b95a207
KH		 6855 spin_unlock_irqrestore(&dev->event_lock, flags);
6856 return;
6857 }
6858
e7d841ca
CW		 6859 /* and that the unpin work is consistent wrt ->pending. */
6860 smp_rmb();
6861
6b95a207 6862 intel_crtc->unpin_work = NULL;
6b95a207 6863
45a066eb
RC		 6864 if (work->event)
6865 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6b95a207 6866
0af7e4df
MK		 6867 drm_vblank_put(dev, intel_crtc->pipe);
6868
6b95a207
KH		 6869 spin_unlock_irqrestore(&dev->event_lock, flags);
6870
05394f39 6871 obj = work->old_fb_obj;
d9e86c0e 6872
2c10d571 6873 wake_up_all(&dev_priv->pending_flip_queue);
b4a98e57
CW		 6874
6875 queue_work(dev_priv->wq, &work->work);
e5510fac
JB		 6876
6877 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6878}
6879
1afe3e9d
JB		 6880void intel_finish_page_flip(struct drm_device *dev, int pipe)
6881{
6882 drm_i915_private_t *dev_priv = dev->dev_private;
6883 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6884
49b14a5c 6885 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6886}
6887
6888void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6889{
6890 drm_i915_private_t *dev_priv = dev->dev_private;
6891 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6892
49b14a5c 6893 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6894}
6895
6b95a207
KH		 6896void intel_prepare_page_flip(struct drm_device *dev, int plane)
6897{
6898 drm_i915_private_t *dev_priv = dev->dev_private;
6899 struct intel_crtc *intel_crtc =
6900 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6901 unsigned long flags;
6902
e7d841ca
CW		 6903 /* NB: An MMIO update of the plane base pointer will also
6904 * generate a page-flip completion irq, i.e. every modeset
6905 * is also accompanied by a spurious intel_prepare_page_flip().
6906 */
6b95a207 6907 spin_lock_irqsave(&dev->event_lock, flags);
e7d841ca
CW		 6908 if (intel_crtc->unpin_work)
6909 atomic_inc_not_zero(&intel_crtc->unpin_work->pending);
6b95a207
KH		 6910 spin_unlock_irqrestore(&dev->event_lock, flags);
6911}
6912
e7d841ca
CW		 6913inline static void intel_mark_page_flip_active(struct intel_crtc *intel_crtc)
6914{
6915 /* Ensure that the work item is consistent when activating it ... */
6916 smp_wmb();
6917 atomic_set(&intel_crtc->unpin_work->pending, INTEL_FLIP_PENDING);
6918 /* and that it is marked active as soon as the irq could fire. */
6919 smp_wmb();
6920}
6921
8c9f3aaf
JB		 6922static int intel_gen2_queue_flip(struct drm_device *dev,
6923 struct drm_crtc *crtc,
6924 struct drm_framebuffer *fb,
6925 struct drm_i915_gem_object *obj)
6926{
6927 struct drm_i915_private *dev_priv = dev->dev_private;
6928 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6929 u32 flip_mask;
6d90c952 6930 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6931 int ret;
6932
6d90c952 6933 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6934 if (ret)
83d4092b 6935 goto err;
8c9f3aaf 6936
6d90c952 6937 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6938 if (ret)
83d4092b 6939 goto err_unpin;
8c9f3aaf
JB		 6940
6941 /* Can't queue multiple flips, so wait for the previous
6942 * one to finish before executing the next.
6943 */
6944 if (intel_crtc->plane)
6945 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6946 else
6947 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6948 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6949 intel_ring_emit(ring, MI_NOOP);
6950 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6951 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6952 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6953 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952 6954 intel_ring_emit(ring, 0); /* aux display base address, unused */
e7d841ca
CW		 6955
6956 intel_mark_page_flip_active(intel_crtc);
6d90c952 6957 intel_ring_advance(ring);
83d4092b
CW		 6958 return 0;
6959
6960err_unpin:
6961 intel_unpin_fb_obj(obj);
6962err:
8c9f3aaf
JB		 6963 return ret;
6964}
6965
6966static int intel_gen3_queue_flip(struct drm_device *dev,
6967 struct drm_crtc *crtc,
6968 struct drm_framebuffer *fb,
6969 struct drm_i915_gem_object *obj)
6970{
6971 struct drm_i915_private *dev_priv = dev->dev_private;
6972 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6973 u32 flip_mask;
6d90c952 6974 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6975 int ret;
6976
6d90c952 6977 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6978 if (ret)
83d4092b 6979 goto err;
8c9f3aaf 6980
6d90c952 6981 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6982 if (ret)
83d4092b 6983 goto err_unpin;
8c9f3aaf
JB		 6984
6985 if (intel_crtc->plane)
6986 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6987 else
6988 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6989 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6990 intel_ring_emit(ring, MI_NOOP);
6991 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6992 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6993 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6994 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6995 intel_ring_emit(ring, MI_NOOP);
6996
e7d841ca 6997 intel_mark_page_flip_active(intel_crtc);
6d90c952 6998 intel_ring_advance(ring);
83d4092b
CW		 6999 return 0;
7000
7001err_unpin:
7002 intel_unpin_fb_obj(obj);
7003err:
8c9f3aaf
JB		 7004 return ret;
7005}
7006
7007static int intel_gen4_queue_flip(struct drm_device *dev,
7008 struct drm_crtc *crtc,
7009 struct drm_framebuffer *fb,
7010 struct drm_i915_gem_object *obj)
7011{
7012 struct drm_i915_private *dev_priv = dev->dev_private;
7013 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7014 uint32_t pf, pipesrc;
6d90c952 7015 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7016 int ret;
7017
6d90c952 7018 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7019 if (ret)
83d4092b 7020 goto err;
8c9f3aaf 7021
6d90c952 7022 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7023 if (ret)
83d4092b 7024 goto err_unpin;
8c9f3aaf
JB		 7025
7026 /* i965+ uses the linear or tiled offsets from the
7027 * Display Registers (which do not change across a page-flip)
7028 * so we need only reprogram the base address.
7029 */
6d90c952
DV		 7030 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7031 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7032 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 7033 intel_ring_emit(ring,
7034 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
7035 obj->tiling_mode);
8c9f3aaf
JB		 7036
7037 /* XXX Enabling the panel-fitter across page-flip is so far
7038 * untested on non-native modes, so ignore it for now.
7039 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7040 */
7041 pf = 0;
7042 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7043 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7044
7045 intel_mark_page_flip_active(intel_crtc);
6d90c952 7046 intel_ring_advance(ring);
83d4092b
CW		 7047 return 0;
7048
7049err_unpin:
7050 intel_unpin_fb_obj(obj);
7051err:
8c9f3aaf
JB		 7052 return ret;
7053}
7054
7055static int intel_gen6_queue_flip(struct drm_device *dev,
7056 struct drm_crtc *crtc,
7057 struct drm_framebuffer *fb,
7058 struct drm_i915_gem_object *obj)
7059{
7060 struct drm_i915_private *dev_priv = dev->dev_private;
7061 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 7062 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 7063 uint32_t pf, pipesrc;
7064 int ret;
7065
6d90c952 7066 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 7067 if (ret)
83d4092b 7068 goto err;
8c9f3aaf 7069
6d90c952 7070 ret = intel_ring_begin(ring, 4);
8c9f3aaf 7071 if (ret)
83d4092b 7072 goto err_unpin;
8c9f3aaf 7073
6d90c952
DV		 7074 intel_ring_emit(ring, MI_DISPLAY_FLIP |
7075 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
7076 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 7077 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 7078
dc257cf1
DV		 7079 /* Contrary to the suggestions in the documentation,
7080 * "Enable Panel Fitter" does not seem to be required when page
7081 * flipping with a non-native mode, and worse causes a normal
7082 * modeset to fail.
7083 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7084 */
7085 pf = 0;
8c9f3aaf 7086 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952 7087 intel_ring_emit(ring, pf | pipesrc);
e7d841ca
CW		 7088
7089 intel_mark_page_flip_active(intel_crtc);
6d90c952 7090 intel_ring_advance(ring);
83d4092b
CW		 7091 return 0;
7092
7093err_unpin:
7094 intel_unpin_fb_obj(obj);
7095err:
8c9f3aaf
JB		 7096 return ret;
7097}
7098
7c9017e5
JB		 7099/*
7100 * On gen7 we currently use the blit ring because (in early silicon at least)
7101 * the render ring doesn't give us interrpts for page flip completion, which
7102 * means clients will hang after the first flip is queued. Fortunately the
7103 * blit ring generates interrupts properly, so use it instead.
7104 */
7105static int intel_gen7_queue_flip(struct drm_device *dev,
7106 struct drm_crtc *crtc,
7107 struct drm_framebuffer *fb,
7108 struct drm_i915_gem_object *obj)
7109{
7110 struct drm_i915_private *dev_priv = dev->dev_private;
7111 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7112 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 7113 uint32_t plane_bit = 0;
7c9017e5
JB		 7114 int ret;
7115
7116 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7117 if (ret)
83d4092b 7118 goto err;
7c9017e5 7119
cb05d8de
DV		 7120 switch(intel_crtc->plane) {
7121 case PLANE_A:
7122 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7123 break;
7124 case PLANE_B:
7125 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7126 break;
7127 case PLANE_C:
7128 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7129 break;
7130 default:
7131 WARN_ONCE(1, "unknown plane in flip command\n");
7132 ret = -ENODEV;
ab3951eb 7133 goto err_unpin;
cb05d8de
DV		 7134 }
7135
7c9017e5
JB		 7136 ret = intel_ring_begin(ring, 4);
7137 if (ret)
83d4092b 7138 goto err_unpin;
7c9017e5 7139
cb05d8de 7140 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 7141 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 7142 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5 7143 intel_ring_emit(ring, (MI_NOOP));
e7d841ca
CW		 7144
7145 intel_mark_page_flip_active(intel_crtc);
7c9017e5 7146 intel_ring_advance(ring);
83d4092b
CW		 7147 return 0;
7148
7149err_unpin:
7150 intel_unpin_fb_obj(obj);
7151err:
7c9017e5
JB		 7152 return ret;
7153}
7154
8c9f3aaf
JB		 7155static int intel_default_queue_flip(struct drm_device *dev,
7156 struct drm_crtc *crtc,
7157 struct drm_framebuffer *fb,
7158 struct drm_i915_gem_object *obj)
7159{
7160 return -ENODEV;
7161}
7162
6b95a207
KH		 7163static int intel_crtc_page_flip(struct drm_crtc *crtc,
7164 struct drm_framebuffer *fb,
7165 struct drm_pending_vblank_event *event)
7166{
7167 struct drm_device *dev = crtc->dev;
7168 struct drm_i915_private *dev_priv = dev->dev_private;
7169 struct intel_framebuffer *intel_fb;
05394f39 7170 struct drm_i915_gem_object *obj;
6b95a207
KH		 7171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7172 struct intel_unpin_work *work;
8c9f3aaf 7173 unsigned long flags;
52e68630 7174 int ret;
6b95a207 7175
e6a595d2
VS		 7176 /* Can't change pixel format via MI display flips. */
7177 if (fb->pixel_format != crtc->fb->pixel_format)
7178 return -EINVAL;
7179
7180 /*
7181 * TILEOFF/LINOFF registers can't be changed via MI display flips.
7182 * Note that pitch changes could also affect these register.
7183 */
7184 if (INTEL_INFO(dev)->gen > 3 &&
7185 (fb->offsets[0] != crtc->fb->offsets[0] ||
7186 fb->pitches[0] != crtc->fb->pitches[0]))
7187 return -EINVAL;
7188
6b95a207
KH		 7189 work = kzalloc(sizeof *work, GFP_KERNEL);
7190 if (work == NULL)
7191 return -ENOMEM;
7192
6b95a207 7193 work->event = event;
b4a98e57 7194 work->crtc = crtc;
6b95a207 7195 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7196 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7197 INIT_WORK(&work->work, intel_unpin_work_fn);
7198
7317c75e
JB		 7199 ret = drm_vblank_get(dev, intel_crtc->pipe);
7200 if (ret)
7201 goto free_work;
7202
6b95a207
KH		 7203 /* We borrow the event spin lock for protecting unpin_work */
7204 spin_lock_irqsave(&dev->event_lock, flags);
7205 if (intel_crtc->unpin_work) {
7206 spin_unlock_irqrestore(&dev->event_lock, flags);
7207 kfree(work);
7317c75e 7208 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7209
7210 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7211 return -EBUSY;
7212 }
7213 intel_crtc->unpin_work = work;
7214 spin_unlock_irqrestore(&dev->event_lock, flags);
7215
7216 intel_fb = to_intel_framebuffer(fb);
7217 obj = intel_fb->obj;
7218
b4a98e57
CW		 7219 if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7220 flush_workqueue(dev_priv->wq);
7221
79158103
CW		 7222 ret = i915_mutex_lock_interruptible(dev);
7223 if (ret)
7224 goto cleanup;
6b95a207 7225
75dfca80 7226 /* Reference the objects for the scheduled work. */
05394f39
CW		 7227 drm_gem_object_reference(&work->old_fb_obj->base);
7228 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7229
7230 crtc->fb = fb;
96b099fd 7231
e1f99ce6 7232 work->pending_flip_obj = obj;
e1f99ce6 7233
4e5359cd
SF		 7234 work->enable_stall_check = true;
7235
b4a98e57 7236 atomic_inc(&intel_crtc->unpin_work_count);
e1f99ce6 7237
8c9f3aaf
JB		 7238 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7239 if (ret)
7240 goto cleanup_pending;
6b95a207 7241
7782de3b 7242 intel_disable_fbc(dev);
f047e395 7243 intel_mark_fb_busy(obj);
6b95a207
KH		 7244 mutex_unlock(&dev->struct_mutex);
7245
e5510fac
JB		 7246 trace_i915_flip_request(intel_crtc->plane, obj);
7247
6b95a207 7248 return 0;
96b099fd 7249
8c9f3aaf 7250cleanup_pending:
b4a98e57 7251 atomic_dec(&intel_crtc->unpin_work_count);
05394f39
CW		 7252 drm_gem_object_unreference(&work->old_fb_obj->base);
7253 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7254 mutex_unlock(&dev->struct_mutex);
7255
79158103 7256cleanup:
96b099fd
CW		 7257 spin_lock_irqsave(&dev->event_lock, flags);
7258 intel_crtc->unpin_work = NULL;
7259 spin_unlock_irqrestore(&dev->event_lock, flags);
7260
7317c75e
JB		 7261 drm_vblank_put(dev, intel_crtc->pipe);
7262free_work:
96b099fd
CW		 7263 kfree(work);
7264
7265 return ret;
6b95a207
KH		 7266}
7267
f6e5b160 7268static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 7269 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7270 .load_lut = intel_crtc_load_lut,
976f8a20 7271 .disable = intel_crtc_noop,
f6e5b160
CW		 7272};
7273
6ed0f796 7274bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
47f1c6c9 7275{
6ed0f796
DV		 7276 struct intel_encoder *other_encoder;
7277 struct drm_crtc *crtc = &encoder->new_crtc->base;
47f1c6c9 7278
6ed0f796
DV		 7279 if (WARN_ON(!crtc))
7280 return false;
7281
7282 list_for_each_entry(other_encoder,
7283 &crtc->dev->mode_config.encoder_list,
7284 base.head) {
7285
7286 if (&other_encoder->new_crtc->base != crtc ||
7287 encoder == other_encoder)
7288 continue;
7289 else
7290 return true;
f47166d2
CW		 7291 }
7292
6ed0f796
DV		 7293 return false;
7294}
47f1c6c9 7295
50f56119
DV		 7296static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7297 struct drm_crtc *crtc)
7298{
7299 struct drm_device *dev;
7300 struct drm_crtc *tmp;
7301 int crtc_mask = 1;
47f1c6c9 7302
50f56119 7303 WARN(!crtc, "checking null crtc?\n");
47f1c6c9 7304
50f56119 7305 dev = crtc->dev;
47f1c6c9 7306
50f56119
DV		 7307 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7308 if (tmp == crtc)
7309 break;
7310 crtc_mask <<= 1;
7311 }
47f1c6c9 7312
50f56119
DV		 7313 if (encoder->possible_crtcs & crtc_mask)
7314 return true;
7315 return false;
47f1c6c9 7316}
79e53945 7317
9a935856
DV		 7318/**
7319 * intel_modeset_update_staged_output_state
7320 *
7321 * Updates the staged output configuration state, e.g. after we've read out the
7322 * current hw state.
7323 */
7324static void intel_modeset_update_staged_output_state(struct drm_device *dev)
f6e5b160 7325{
9a935856
DV		 7326 struct intel_encoder *encoder;
7327 struct intel_connector *connector;
f6e5b160 7328
9a935856
DV		 7329 list_for_each_entry(connector, &dev->mode_config.connector_list,
7330 base.head) {
7331 connector->new_encoder =
7332 to_intel_encoder(connector->base.encoder);
7333 }
f6e5b160 7334
9a935856
DV		 7335 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7336 base.head) {
7337 encoder->new_crtc =
7338 to_intel_crtc(encoder->base.crtc);
7339 }
f6e5b160
CW		 7340}
7341
9a935856
DV		 7342/**
7343 * intel_modeset_commit_output_state
7344 *
7345 * This function copies the stage display pipe configuration to the real one.
7346 */
7347static void intel_modeset_commit_output_state(struct drm_device *dev)
7348{
7349 struct intel_encoder *encoder;
7350 struct intel_connector *connector;
f6e5b160 7351
9a935856
DV		 7352 list_for_each_entry(connector, &dev->mode_config.connector_list,
7353 base.head) {
7354 connector->base.encoder = &connector->new_encoder->base;
7355 }
f6e5b160 7356
9a935856
DV		 7357 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7358 base.head) {
7359 encoder->base.crtc = &encoder->new_crtc->base;
7360 }
7361}
7362
7758a113
DV		 7363static struct drm_display_mode *
7364intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7365 struct drm_display_mode *mode)
ee7b9f93 7366{
7758a113
DV		 7367 struct drm_device *dev = crtc->dev;
7368 struct drm_display_mode *adjusted_mode;
7369 struct drm_encoder_helper_funcs *encoder_funcs;
7370 struct intel_encoder *encoder;
ee7b9f93 7371
7758a113
DV		 7372 adjusted_mode = drm_mode_duplicate(dev, mode);
7373 if (!adjusted_mode)
7374 return ERR_PTR(-ENOMEM);
7375
7376 /* Pass our mode to the connectors and the CRTC to give them a chance to
7377 * adjust it according to limitations or connector properties, and also
7378 * a chance to reject the mode entirely.
47f1c6c9 7379 */
7758a113
DV		 7380 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7381 base.head) {
47f1c6c9 7382
7758a113
DV		 7383 if (&encoder->new_crtc->base != crtc)
7384 continue;
7385 encoder_funcs = encoder->base.helper_private;
7386 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7387 adjusted_mode))) {
7388 DRM_DEBUG_KMS("Encoder fixup failed\n");
7389 goto fail;
7390 }
ee7b9f93 7391 }
47f1c6c9 7392
7758a113
DV		 7393 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7394 DRM_DEBUG_KMS("CRTC fixup failed\n");
7395 goto fail;
ee7b9f93 7396 }
7758a113 7397 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
47f1c6c9 7398
7758a113
DV		 7399 return adjusted_mode;
7400fail:
7401 drm_mode_destroy(dev, adjusted_mode);
7402 return ERR_PTR(-EINVAL);
ee7b9f93 7403}
47f1c6c9 7404
e2e1ed41
DV		 7405/* Computes which crtcs are affected and sets the relevant bits in the mask. For
7406 * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7407static void
7408intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7409 unsigned *prepare_pipes, unsigned *disable_pipes)
79e53945
JB		 7410{
7411 struct intel_crtc *intel_crtc;
e2e1ed41
DV		 7412 struct drm_device *dev = crtc->dev;
7413 struct intel_encoder *encoder;
7414 struct intel_connector *connector;
7415 struct drm_crtc *tmp_crtc;
79e53945 7416
e2e1ed41 7417 *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
79e53945 7418
e2e1ed41
DV		 7419 /* Check which crtcs have changed outputs connected to them, these need
7420 * to be part of the prepare_pipes mask. We don't (yet) support global
7421 * modeset across multiple crtcs, so modeset_pipes will only have one
7422 * bit set at most. */
7423 list_for_each_entry(connector, &dev->mode_config.connector_list,
7424 base.head) {
7425 if (connector->base.encoder == &connector->new_encoder->base)
7426 continue;
79e53945 7427
e2e1ed41
DV		 7428 if (connector->base.encoder) {
7429 tmp_crtc = connector->base.encoder->crtc;
7430
7431 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7432 }
7433
7434 if (connector->new_encoder)
7435 *prepare_pipes |=
7436 1 << connector->new_encoder->new_crtc->pipe;
79e53945
JB		 7437 }
7438
e2e1ed41
DV		 7439 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7440 base.head) {
7441 if (encoder->base.crtc == &encoder->new_crtc->base)
7442 continue;
7443
7444 if (encoder->base.crtc) {
7445 tmp_crtc = encoder->base.crtc;
7446
7447 *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7448 }
7449
7450 if (encoder->new_crtc)
7451 *prepare_pipes |= 1 << encoder->new_crtc->pipe;
80824003
JB		 7452 }
7453
e2e1ed41
DV		 7454 /* Check for any pipes that will be fully disabled ... */
7455 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7456 base.head) {
7457 bool used = false;
22fd0fab 7458
e2e1ed41
DV		 7459 /* Don't try to disable disabled crtcs. */
7460 if (!intel_crtc->base.enabled)
7461 continue;
7e7d76c3 7462
e2e1ed41
DV		 7463 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7464 base.head) {
7465 if (encoder->new_crtc == intel_crtc)
7466 used = true;
7467 }
7468
7469 if (!used)
7470 *disable_pipes |= 1 << intel_crtc->pipe;
7e7d76c3
JB		 7471 }
7472
e2e1ed41
DV		 7473
7474 /* set_mode is also used to update properties on life display pipes. */
7475 intel_crtc = to_intel_crtc(crtc);
7476 if (crtc->enabled)
7477 *prepare_pipes |= 1 << intel_crtc->pipe;
7478
7479 /* We only support modeset on one single crtc, hence we need to do that
7480 * only for the passed in crtc iff we change anything else than just
7481 * disable crtcs.
7482 *
7483 * This is actually not true, to be fully compatible with the old crtc
7484 * helper we automatically disable _any_ output (i.e. doesn't need to be
7485 * connected to the crtc we're modesetting on) if it's disconnected.
7486 * Which is a rather nutty api (since changed the output configuration
7487 * without userspace's explicit request can lead to confusion), but
7488 * alas. Hence we currently need to modeset on all pipes we prepare. */
7489 if (*prepare_pipes)
7490 *modeset_pipes = *prepare_pipes;
7491
7492 /* ... and mask these out. */
7493 *modeset_pipes &= ~(*disable_pipes);
7494 *prepare_pipes &= ~(*disable_pipes);
47f1c6c9 7495}
79e53945 7496
ea9d758d 7497static bool intel_crtc_in_use(struct drm_crtc *crtc)
f6e5b160 7498{
ea9d758d 7499 struct drm_encoder *encoder;
f6e5b160 7500 struct drm_device *dev = crtc->dev;
f6e5b160 7501
ea9d758d
DV		 7502 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7503 if (encoder->crtc == crtc)
7504 return true;
7505
7506 return false;
7507}
7508
7509static void
7510intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7511{
7512 struct intel_encoder *intel_encoder;
7513 struct intel_crtc *intel_crtc;
7514 struct drm_connector *connector;
7515
7516 list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7517 base.head) {
7518 if (!intel_encoder->base.crtc)
7519 continue;
7520
7521 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7522
7523 if (prepare_pipes & (1 << intel_crtc->pipe))
7524 intel_encoder->connectors_active = false;
7525 }
7526
7527 intel_modeset_commit_output_state(dev);
7528
7529 /* Update computed state. */
7530 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7531 base.head) {
7532 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7533 }
7534
7535 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7536 if (!connector->encoder || !connector->encoder->crtc)
7537 continue;
7538
7539 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7540
7541 if (prepare_pipes & (1 << intel_crtc->pipe)) {
68d34720
DV		 7542 struct drm_property *dpms_property =
7543 dev->mode_config.dpms_property;
7544
ea9d758d 7545 connector->dpms = DRM_MODE_DPMS_ON;
662595df 7546 drm_object_property_set_value(&connector->base,
68d34720
DV		 7547 dpms_property,
7548 DRM_MODE_DPMS_ON);
ea9d758d
DV		 7549
7550 intel_encoder = to_intel_encoder(connector->encoder);
7551 intel_encoder->connectors_active = true;
7552 }
7553 }
7554
7555}
7556
25c5b266
DV		 7557#define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7558 list_for_each_entry((intel_crtc), \
7559 &(dev)->mode_config.crtc_list, \
7560 base.head) \
7561 if (mask & (1 <<(intel_crtc)->pipe)) \
7562
b980514c 7563void
8af6cf88
DV		 7564intel_modeset_check_state(struct drm_device *dev)
7565{
7566 struct intel_crtc *crtc;
7567 struct intel_encoder *encoder;
7568 struct intel_connector *connector;
7569
7570 list_for_each_entry(connector, &dev->mode_config.connector_list,
7571 base.head) {
7572 /* This also checks the encoder/connector hw state with the
7573 * ->get_hw_state callbacks. */
7574 intel_connector_check_state(connector);
7575
7576 WARN(&connector->new_encoder->base != connector->base.encoder,
7577 "connector's staged encoder doesn't match current encoder\n");
7578 }
7579
7580 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7581 base.head) {
7582 bool enabled = false;
7583 bool active = false;
7584 enum pipe pipe, tracked_pipe;
7585
7586 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7587 encoder->base.base.id,
7588 drm_get_encoder_name(&encoder->base));
7589
7590 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7591 "encoder's stage crtc doesn't match current crtc\n");
7592 WARN(encoder->connectors_active && !encoder->base.crtc,
7593 "encoder's active_connectors set, but no crtc\n");
7594
7595 list_for_each_entry(connector, &dev->mode_config.connector_list,
7596 base.head) {
7597 if (connector->base.encoder != &encoder->base)
7598 continue;
7599 enabled = true;
7600 if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7601 active = true;
7602 }
7603 WARN(!!encoder->base.crtc != enabled,
7604 "encoder's enabled state mismatch "
7605 "(expected %i, found %i)\n",
7606 !!encoder->base.crtc, enabled);
7607 WARN(active && !encoder->base.crtc,
7608 "active encoder with no crtc\n");
7609
7610 WARN(encoder->connectors_active != active,
7611 "encoder's computed active state doesn't match tracked active state "
7612 "(expected %i, found %i)\n", active, encoder->connectors_active);
7613
7614 active = encoder->get_hw_state(encoder, &pipe);
7615 WARN(active != encoder->connectors_active,
7616 "encoder's hw state doesn't match sw tracking "
7617 "(expected %i, found %i)\n",
7618 encoder->connectors_active, active);
7619
7620 if (!encoder->base.crtc)
7621 continue;
7622
7623 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7624 WARN(active && pipe != tracked_pipe,
7625 "active encoder's pipe doesn't match"
7626 "(expected %i, found %i)\n",
7627 tracked_pipe, pipe);
7628
7629 }
7630
7631 list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7632 base.head) {
7633 bool enabled = false;
7634 bool active = false;
7635
7636 DRM_DEBUG_KMS("[CRTC:%d]\n",
7637 crtc->base.base.id);
7638
7639 WARN(crtc->active && !crtc->base.enabled,
7640 "active crtc, but not enabled in sw tracking\n");
7641
7642 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7643 base.head) {
7644 if (encoder->base.crtc != &crtc->base)
7645 continue;
7646 enabled = true;
7647 if (encoder->connectors_active)
7648 active = true;
7649 }
7650 WARN(active != crtc->active,
7651 "crtc's computed active state doesn't match tracked active state "
7652 "(expected %i, found %i)\n", active, crtc->active);
7653 WARN(enabled != crtc->base.enabled,
7654 "crtc's computed enabled state doesn't match tracked enabled state "
7655 "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7656
7657 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7658 }
7659}
7660
c0c36b94
CW		 7661int intel_set_mode(struct drm_crtc *crtc,
7662 struct drm_display_mode *mode,
7663 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 7664{
7665 struct drm_device *dev = crtc->dev;
dbf2b54e 7666 drm_i915_private_t *dev_priv = dev->dev_private;
3ac18232 7667 struct drm_display_mode *adjusted_mode, *saved_mode, *saved_hwmode;
25c5b266
DV		 7668 struct intel_crtc *intel_crtc;
7669 unsigned disable_pipes, prepare_pipes, modeset_pipes;
c0c36b94 7670 int ret = 0;
a6778b3c 7671
3ac18232 7672 saved_mode = kmalloc(2 * sizeof(*saved_mode), GFP_KERNEL);
c0c36b94
CW		 7673 if (!saved_mode)
7674 return -ENOMEM;
3ac18232 7675 saved_hwmode = saved_mode + 1;
a6778b3c 7676
e2e1ed41 7677 intel_modeset_affected_pipes(crtc, &modeset_pipes,
25c5b266
DV		 7678 &prepare_pipes, &disable_pipes);
7679
7680 DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7681 modeset_pipes, prepare_pipes, disable_pipes);
e2e1ed41 7682
976f8a20
DV		 7683 for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7684 intel_crtc_disable(&intel_crtc->base);
87f1faa6 7685
3ac18232
TG		 7686 *saved_hwmode = crtc->hwmode;
7687 *saved_mode = crtc->mode;
a6778b3c 7688
25c5b266
DV		 7689 /* Hack: Because we don't (yet) support global modeset on multiple
7690 * crtcs, we don't keep track of the new mode for more than one crtc.
7691 * Hence simply check whether any bit is set in modeset_pipes in all the
7692 * pieces of code that are not yet converted to deal with mutliple crtcs
7693 * changing their mode at the same time. */
7694 adjusted_mode = NULL;
7695 if (modeset_pipes) {
7696 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7697 if (IS_ERR(adjusted_mode)) {
c0c36b94 7698 ret = PTR_ERR(adjusted_mode);
3ac18232 7699 goto out;
25c5b266 7700 }
25c5b266 7701 }
a6778b3c 7702
ea9d758d
DV		 7703 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7704 if (intel_crtc->base.enabled)
7705 dev_priv->display.crtc_disable(&intel_crtc->base);
7706 }
a6778b3c 7707
6c4c86f5
DV		 7708 /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7709 * to set it here already despite that we pass it down the callchain.
f6e5b160 7710 */
6c4c86f5 7711 if (modeset_pipes)
25c5b266 7712 crtc->mode = *mode;
7758a113 7713
ea9d758d
DV		 7714 /* Only after disabling all output pipelines that will be changed can we
7715 * update the the output configuration. */
7716 intel_modeset_update_state(dev, prepare_pipes);
f6e5b160 7717
47fab737
DV		 7718 if (dev_priv->display.modeset_global_resources)
7719 dev_priv->display.modeset_global_resources(dev);
7720
a6778b3c
DV		 7721 /* Set up the DPLL and any encoders state that needs to adjust or depend
7722 * on the DPLL.
f6e5b160 7723 */
25c5b266 7724 for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
c0c36b94
CW		 7725 ret = intel_crtc_mode_set(&intel_crtc->base,
7726 mode, adjusted_mode,
7727 x, y, fb);
7728 if (ret)
7729 goto done;
a6778b3c
DV		 7730 }
7731
7732 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
25c5b266
DV		 7733 for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7734 dev_priv->display.crtc_enable(&intel_crtc->base);
a6778b3c 7735
25c5b266
DV		 7736 if (modeset_pipes) {
7737 /* Store real post-adjustment hardware mode. */
7738 crtc->hwmode = *adjusted_mode;
a6778b3c 7739
25c5b266
DV		 7740 /* Calculate and store various constants which
7741 * are later needed by vblank and swap-completion
7742 * timestamping. They are derived from true hwmode.
7743 */
7744 drm_calc_timestamping_constants(crtc);
7745 }
a6778b3c
DV		 7746
7747 /* FIXME: add subpixel order */
7748done:
7749 drm_mode_destroy(dev, adjusted_mode);
c0c36b94 7750 if (ret && crtc->enabled) {
3ac18232
TG		 7751 crtc->hwmode = *saved_hwmode;
7752 crtc->mode = *saved_mode;
8af6cf88
DV		 7753 } else {
7754 intel_modeset_check_state(dev);
a6778b3c
DV		 7755 }
7756
3ac18232
TG		 7757out:
7758 kfree(saved_mode);
a6778b3c 7759 return ret;
f6e5b160
CW		 7760}
7761
c0c36b94
CW		 7762void intel_crtc_restore_mode(struct drm_crtc *crtc)
7763{
7764 intel_set_mode(crtc, &crtc->mode, crtc->x, crtc->y, crtc->fb);
7765}
7766
25c5b266
DV		 7767#undef for_each_intel_crtc_masked
7768
d9e55608
DV		 7769static void intel_set_config_free(struct intel_set_config *config)
7770{
7771 if (!config)
7772 return;
7773
1aa4b628
DV		 7774 kfree(config->save_connector_encoders);
7775 kfree(config->save_encoder_crtcs);
d9e55608
DV		 7776 kfree(config);
7777}
7778
85f9eb71
DV		 7779static int intel_set_config_save_state(struct drm_device *dev,
7780 struct intel_set_config *config)
7781{
85f9eb71
DV		 7782 struct drm_encoder *encoder;
7783 struct drm_connector *connector;
7784 int count;
7785
1aa4b628
DV		 7786 config->save_encoder_crtcs =
7787 kcalloc(dev->mode_config.num_encoder,
7788 sizeof(struct drm_crtc *), GFP_KERNEL);
7789 if (!config->save_encoder_crtcs)
85f9eb71
DV		 7790 return -ENOMEM;
7791
1aa4b628
DV		 7792 config->save_connector_encoders =
7793 kcalloc(dev->mode_config.num_connector,
7794 sizeof(struct drm_encoder *), GFP_KERNEL);
7795 if (!config->save_connector_encoders)
85f9eb71
DV		 7796 return -ENOMEM;
7797
7798 /* Copy data. Note that driver private data is not affected.
7799 * Should anything bad happen only the expected state is
7800 * restored, not the drivers personal bookkeeping.
7801 */
85f9eb71
DV		 7802 count = 0;
7803 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 7804 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 7805 }
7806
7807 count = 0;
7808 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 7809 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 7810 }
7811
7812 return 0;
7813}
7814
7815static void intel_set_config_restore_state(struct drm_device *dev,
7816 struct intel_set_config *config)
7817{
9a935856
DV		 7818 struct intel_encoder *encoder;
7819 struct intel_connector *connector;
85f9eb71
DV		 7820 int count;
7821
85f9eb71 7822 count = 0;
9a935856
DV		 7823 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7824 encoder->new_crtc =
7825 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 7826 }
7827
7828 count = 0;
9a935856
DV		 7829 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7830 connector->new_encoder =
7831 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 7832 }
7833}
7834
5e2b584e
DV		 7835static void
7836intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7837 struct intel_set_config *config)
7838{
7839
7840 /* We should be able to check here if the fb has the same properties
7841 * and then just flip_or_move it */
7842 if (set->crtc->fb != set->fb) {
7843 /* If we have no fb then treat it as a full mode set */
7844 if (set->crtc->fb == NULL) {
7845 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7846 config->mode_changed = true;
7847 } else if (set->fb == NULL) {
7848 config->mode_changed = true;
7849 } else if (set->fb->depth != set->crtc->fb->depth) {
7850 config->mode_changed = true;
7851 } else if (set->fb->bits_per_pixel !=
7852 set->crtc->fb->bits_per_pixel) {
7853 config->mode_changed = true;
7854 } else
7855 config->fb_changed = true;
7856 }
7857
835c5873 7858 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 7859 config->fb_changed = true;
7860
7861 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7862 DRM_DEBUG_KMS("modes are different, full mode set\n");
7863 drm_mode_debug_printmodeline(&set->crtc->mode);
7864 drm_mode_debug_printmodeline(set->mode);
7865 config->mode_changed = true;
7866 }
7867}
7868
2e431051 7869static int
9a935856
DV		 7870intel_modeset_stage_output_state(struct drm_device *dev,
7871 struct drm_mode_set *set,
7872 struct intel_set_config *config)
50f56119 7873{
85f9eb71 7874 struct drm_crtc *new_crtc;
9a935856
DV		 7875 struct intel_connector *connector;
7876 struct intel_encoder *encoder;
2e431051 7877 int count, ro;
50f56119 7878
9a935856
DV		 7879 /* The upper layers ensure that we either disabl a crtc or have a list
7880 * of connectors. For paranoia, double-check this. */
7881 WARN_ON(!set->fb && (set->num_connectors != 0));
7882 WARN_ON(set->fb && (set->num_connectors == 0));
7883
50f56119 7884 count = 0;
9a935856
DV		 7885 list_for_each_entry(connector, &dev->mode_config.connector_list,
7886 base.head) {
7887 /* Otherwise traverse passed in connector list and get encoders
7888 * for them. */
50f56119 7889 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 7890 if (set->connectors[ro] == &connector->base) {
7891 connector->new_encoder = connector->encoder;
50f56119
DV		 7892 break;
7893 }
7894 }
7895
9a935856
DV		 7896 /* If we disable the crtc, disable all its connectors. Also, if
7897 * the connector is on the changing crtc but not on the new
7898 * connector list, disable it. */
7899 if ((!set->fb || ro == set->num_connectors) &&
7900 connector->base.encoder &&
7901 connector->base.encoder->crtc == set->crtc) {
7902 connector->new_encoder = NULL;
7903
7904 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7905 connector->base.base.id,
7906 drm_get_connector_name(&connector->base));
7907 }
7908
7909
7910 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 7911 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 7912 config->mode_changed = true;
50f56119
DV		 7913 }
7914 }
9a935856 7915 /* connector->new_encoder is now updated for all connectors. */
50f56119 7916
9a935856 7917 /* Update crtc of enabled connectors. */
50f56119 7918 count = 0;
9a935856
DV		 7919 list_for_each_entry(connector, &dev->mode_config.connector_list,
7920 base.head) {
7921 if (!connector->new_encoder)
50f56119
DV		 7922 continue;
7923
9a935856 7924 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 7925
7926 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 7927 if (set->connectors[ro] == &connector->base)
50f56119
DV		 7928 new_crtc = set->crtc;
7929 }
7930
7931 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 7932 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7933 new_crtc)) {
5e2b584e 7934 return -EINVAL;
50f56119 7935 }
9a935856
DV		 7936 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7937
7938 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7939 connector->base.base.id,
7940 drm_get_connector_name(&connector->base),
7941 new_crtc->base.id);
7942 }
7943
7944 /* Check for any encoders that needs to be disabled. */
7945 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7946 base.head) {
7947 list_for_each_entry(connector,
7948 &dev->mode_config.connector_list,
7949 base.head) {
7950 if (connector->new_encoder == encoder) {
7951 WARN_ON(!connector->new_encoder->new_crtc);
7952
7953 goto next_encoder;
7954 }
7955 }
7956 encoder->new_crtc = NULL;
7957next_encoder:
7958 /* Only now check for crtc changes so we don't miss encoders
7959 * that will be disabled. */
7960 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 7961 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 7962 config->mode_changed = true;
50f56119
DV		 7963 }
7964 }
9a935856 7965 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 7966
2e431051
DV		 7967 return 0;
7968}
7969
7970static int intel_crtc_set_config(struct drm_mode_set *set)
7971{
7972 struct drm_device *dev;
2e431051
DV		 7973 struct drm_mode_set save_set;
7974 struct intel_set_config *config;
7975 int ret;
2e431051 7976
8d3e375e
DV		 7977 BUG_ON(!set);
7978 BUG_ON(!set->crtc);
7979 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 7980
7981 if (!set->mode)
7982 set->fb = NULL;
7983
431e50f7
DV		 7984 /* The fb helper likes to play gross jokes with ->mode_set_config.
7985 * Unfortunately the crtc helper doesn't do much at all for this case,
7986 * so we have to cope with this madness until the fb helper is fixed up. */
7987 if (set->fb && set->num_connectors == 0)
7988 return 0;
7989
2e431051
DV		 7990 if (set->fb) {
7991 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7992 set->crtc->base.id, set->fb->base.id,
7993 (int)set->num_connectors, set->x, set->y);
7994 } else {
7995 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 7996 }
7997
7998 dev = set->crtc->dev;
7999
8000 ret = -ENOMEM;
8001 config = kzalloc(sizeof(*config), GFP_KERNEL);
8002 if (!config)
8003 goto out_config;
8004
8005 ret = intel_set_config_save_state(dev, config);
8006 if (ret)
8007 goto out_config;
8008
8009 save_set.crtc = set->crtc;
8010 save_set.mode = &set->crtc->mode;
8011 save_set.x = set->crtc->x;
8012 save_set.y = set->crtc->y;
8013 save_set.fb = set->crtc->fb;
8014
8015 /* Compute whether we need a full modeset, only an fb base update or no
8016 * change at all. In the future we might also check whether only the
8017 * mode changed, e.g. for LVDS where we only change the panel fitter in
8018 * such cases. */
8019 intel_set_config_compute_mode_changes(set, config);
8020
9a935856 8021 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 8022 if (ret)
8023 goto fail;
8024
5e2b584e 8025 if (config->mode_changed) {
87f1faa6 8026 if (set->mode) {
50f56119
DV		 8027 DRM_DEBUG_KMS("attempting to set mode from"
8028 " userspace\n");
8029 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 8030 }
8031
c0c36b94
CW		 8032 ret = intel_set_mode(set->crtc, set->mode,
8033 set->x, set->y, set->fb);
8034 if (ret) {
8035 DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
8036 set->crtc->base.id, ret);
87f1faa6
DV		 8037 goto fail;
8038 }
5e2b584e 8039 } else if (config->fb_changed) {
4f660f49 8040 ret = intel_pipe_set_base(set->crtc,
94352cf9 8041 set->x, set->y, set->fb);
50f56119
DV		 8042 }
8043
d9e55608
DV		 8044 intel_set_config_free(config);
8045
50f56119
DV		 8046 return 0;
8047
8048fail:
85f9eb71 8049 intel_set_config_restore_state(dev, config);
50f56119
DV		 8050
8051 /* Try to restore the config */
5e2b584e 8052 if (config->mode_changed &&
c0c36b94
CW		 8053 intel_set_mode(save_set.crtc, save_set.mode,
8054 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 8055 DRM_ERROR("failed to restore config after modeset failure\n");
8056
d9e55608
DV		 8057out_config:
8058 intel_set_config_free(config);
50f56119
DV		 8059 return ret;
8060}
f6e5b160
CW		 8061
8062static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 8063 .cursor_set = intel_crtc_cursor_set,
8064 .cursor_move = intel_crtc_cursor_move,
8065 .gamma_set = intel_crtc_gamma_set,
50f56119 8066 .set_config = intel_crtc_set_config,
f6e5b160
CW		 8067 .destroy = intel_crtc_destroy,
8068 .page_flip = intel_crtc_page_flip,
8069};
8070
79f689aa
PZ		 8071static void intel_cpu_pll_init(struct drm_device *dev)
8072{
affa9354 8073 if (HAS_DDI(dev))
79f689aa
PZ		 8074 intel_ddi_pll_init(dev);
8075}
8076
ee7b9f93
JB		 8077static void intel_pch_pll_init(struct drm_device *dev)
8078{
8079 drm_i915_private_t *dev_priv = dev->dev_private;
8080 int i;
8081
8082 if (dev_priv->num_pch_pll == 0) {
8083 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
8084 return;
8085 }
8086
8087 for (i = 0; i < dev_priv->num_pch_pll; i++) {
8088 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
8089 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8090 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8091 }
8092}
8093
b358d0a6 8094static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 8095{
22fd0fab 8096 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 8097 struct intel_crtc *intel_crtc;
8098 int i;
8099
8100 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8101 if (intel_crtc == NULL)
8102 return;
8103
8104 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8105
8106 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 8107 for (i = 0; i < 256; i++) {
8108 intel_crtc->lut_r[i] = i;
8109 intel_crtc->lut_g[i] = i;
8110 intel_crtc->lut_b[i] = i;
8111 }
8112
80824003
JB		 8113 /* Swap pipes & planes for FBC on pre-965 */
8114 intel_crtc->pipe = pipe;
8115 intel_crtc->plane = pipe;
a5c961d1 8116 intel_crtc->cpu_transcoder = pipe;
e2e767ab 8117 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 8118 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 8119 intel_crtc->plane = !pipe;
80824003
JB		 8120 }
8121
22fd0fab
JB		 8122 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8123 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8124 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8125 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8126
5a354204 8127 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 8128
79e53945 8129 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 8130}
8131
08d7b3d1 8132int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 8133 struct drm_file *file)
08d7b3d1 8134{
08d7b3d1 8135 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 8136 struct drm_mode_object *drmmode_obj;
8137 struct intel_crtc *crtc;
08d7b3d1 8138
1cff8f6b
DV		 8139 if (!drm_core_check_feature(dev, DRIVER_MODESET))
8140 return -ENODEV;
08d7b3d1 8141
c05422d5
DV		 8142 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8143 DRM_MODE_OBJECT_CRTC);
08d7b3d1 8144
c05422d5 8145 if (!drmmode_obj) {
08d7b3d1
CW		 8146 DRM_ERROR("no such CRTC id\n");
8147 return -EINVAL;
8148 }
8149
c05422d5
DV		 8150 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8151 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 8152
c05422d5 8153 return 0;
08d7b3d1
CW		 8154}
8155
66a9278e 8156static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 8157{
66a9278e
DV		 8158 struct drm_device *dev = encoder->base.dev;
8159 struct intel_encoder *source_encoder;
79e53945 8160 int index_mask = 0;
79e53945
JB		 8161 int entry = 0;
8162
66a9278e
DV		 8163 list_for_each_entry(source_encoder,
8164 &dev->mode_config.encoder_list, base.head) {
8165
8166 if (encoder == source_encoder)
79e53945 8167 index_mask |= (1 << entry);
66a9278e
DV		 8168
8169 /* Intel hw has only one MUX where enocoders could be cloned. */
8170 if (encoder->cloneable && source_encoder->cloneable)
8171 index_mask |= (1 << entry);
8172
79e53945
JB		 8173 entry++;
8174 }
4ef69c7a 8175
79e53945
JB		 8176 return index_mask;
8177}
8178
4d302442
CW		 8179static bool has_edp_a(struct drm_device *dev)
8180{
8181 struct drm_i915_private *dev_priv = dev->dev_private;
8182
8183 if (!IS_MOBILE(dev))
8184 return false;
8185
8186 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8187 return false;
8188
8189 if (IS_GEN5(dev) &&
8190 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8191 return false;
8192
8193 return true;
8194}
8195
79e53945
JB		 8196static void intel_setup_outputs(struct drm_device *dev)
8197{
725e30ad 8198 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 8199 struct intel_encoder *encoder;
cb0953d7 8200 bool dpd_is_edp = false;
f3cfcba6 8201 bool has_lvds;
79e53945 8202
f3cfcba6 8203 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 8204 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8205 /* disable the panel fitter on everything but LVDS */
8206 I915_WRITE(PFIT_CONTROL, 0);
8207 }
79e53945 8208
affa9354 8209 if (!(HAS_DDI(dev) && (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
79935fca 8210 intel_crt_init(dev);
cb0953d7 8211
affa9354 8212 if (HAS_DDI(dev)) {
0e72a5b5
ED		 8213 int found;
8214
8215 /* Haswell uses DDI functions to detect digital outputs */
8216 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8217 /* DDI A only supports eDP */
8218 if (found)
8219 intel_ddi_init(dev, PORT_A);
8220
8221 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8222 * register */
8223 found = I915_READ(SFUSE_STRAP);
8224
8225 if (found & SFUSE_STRAP_DDIB_DETECTED)
8226 intel_ddi_init(dev, PORT_B);
8227 if (found & SFUSE_STRAP_DDIC_DETECTED)
8228 intel_ddi_init(dev, PORT_C);
8229 if (found & SFUSE_STRAP_DDID_DETECTED)
8230 intel_ddi_init(dev, PORT_D);
8231 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7 8232 int found;
270b3042
DV		 8233 dpd_is_edp = intel_dpd_is_edp(dev);
8234
8235 if (has_edp_a(dev))
8236 intel_dp_init(dev, DP_A, PORT_A);
cb0953d7 8237
30ad48b7 8238 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 8239 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 8240 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 8241 if (!found)
08d644ad 8242 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 8243 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 8244 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 8245 }
8246
8247 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 8248 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 8249
b708a1d5 8250 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 8251 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 8252
5eb08b69 8253 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 8254 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 8255
270b3042 8256 if (I915_READ(PCH_DP_D) & DP_DETECTED)
ab9d7c30 8257 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d 8258 } else if (IS_VALLEYVIEW(dev)) {
19c03924 8259 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
67cfc203
VS		 8260 if (I915_READ(VLV_DISPLAY_BASE + DP_C) & DP_DETECTED)
8261 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_C, PORT_C);
19c03924 8262
67cfc203
VS		 8263 if (I915_READ(VLV_DISPLAY_BASE + SDVOB) & PORT_DETECTED) {
8264 intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOB, PORT_B);
8265 if (I915_READ(VLV_DISPLAY_BASE + DP_B) & DP_DETECTED)
8266 intel_dp_init(dev, VLV_DISPLAY_BASE + DP_B, PORT_B);
4a87d65d
JB		 8267 }
8268
67cfc203
VS		 8269 if (I915_READ(VLV_DISPLAY_BASE + SDVOC) & PORT_DETECTED)
8270 intel_hdmi_init(dev, VLV_DISPLAY_BASE + SDVOC, PORT_C);
5eb08b69 8271
103a196f 8272 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 8273 bool found = false;
7d57382e 8274
725e30ad 8275 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 8276 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 8277 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 8278 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8279 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 8280 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 8281 }
27185ae1 8282
b01f2c3a
JB		 8283 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8284 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 8285 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 8286 }
725e30ad 8287 }
13520b05
KH		 8288
8289 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 8290
b01f2c3a
JB		 8291 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8292 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 8293 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 8294 }
27185ae1
ML		 8295
8296 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8297
b01f2c3a
JB		 8298 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8299 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 8300 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 8301 }
8302 if (SUPPORTS_INTEGRATED_DP(dev)) {
8303 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 8304 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 8305 }
725e30ad 8306 }
27185ae1 8307
b01f2c3a
JB		 8308 if (SUPPORTS_INTEGRATED_DP(dev) &&
8309 (I915_READ(DP_D) & DP_DETECTED)) {
8310 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 8311 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 8312 }
bad720ff 8313 } else if (IS_GEN2(dev))
79e53945
JB		 8314 intel_dvo_init(dev);
8315
103a196f 8316 if (SUPPORTS_TV(dev))
79e53945
JB		 8317 intel_tv_init(dev);
8318
4ef69c7a
CW		 8319 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8320 encoder->base.possible_crtcs = encoder->crtc_mask;
8321 encoder->base.possible_clones =
66a9278e 8322 intel_encoder_clones(encoder);
79e53945 8323 }
47356eb6 8324
dde86e2d 8325 intel_init_pch_refclk(dev);
270b3042
DV		 8326
8327 drm_helper_move_panel_connectors_to_head(dev);
79e53945
JB		 8328}
8329
8330static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8331{
8332 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 8333
8334 drm_framebuffer_cleanup(fb);
05394f39 8335 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 8336
8337 kfree(intel_fb);
8338}
8339
8340static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 8341 struct drm_file *file,
79e53945
JB		 8342 unsigned int *handle)
8343{
8344 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 8345 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 8346
05394f39 8347 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 8348}
8349
8350static const struct drm_framebuffer_funcs intel_fb_funcs = {
8351 .destroy = intel_user_framebuffer_destroy,
8352 .create_handle = intel_user_framebuffer_create_handle,
8353};
8354
38651674
DA		 8355int intel_framebuffer_init(struct drm_device *dev,
8356 struct intel_framebuffer *intel_fb,
308e5bcb 8357 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 8358 struct drm_i915_gem_object *obj)
79e53945 8359{
79e53945
JB		 8360 int ret;
8361
05394f39 8362 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 8363 return -EINVAL;
8364
308e5bcb 8365 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 8366 return -EINVAL;
8367
5d7bd705
VS		 8368 /* FIXME <= Gen4 stride limits are bit unclear */
8369 if (mode_cmd->pitches[0] > 32768)
8370 return -EINVAL;
8371
8372 if (obj->tiling_mode != I915_TILING_NONE &&
8373 mode_cmd->pitches[0] != obj->stride)
8374 return -EINVAL;
8375
57779d06 8376 /* Reject formats not supported by any plane early. */
308e5bcb 8377 switch (mode_cmd->pixel_format) {
57779d06 8378 case DRM_FORMAT_C8:
04b3924d
VS		 8379 case DRM_FORMAT_RGB565:
8380 case DRM_FORMAT_XRGB8888:
8381 case DRM_FORMAT_ARGB8888:
57779d06
VS		 8382 break;
8383 case DRM_FORMAT_XRGB1555:
8384 case DRM_FORMAT_ARGB1555:
8385 if (INTEL_INFO(dev)->gen > 3)
8386 return -EINVAL;
8387 break;
8388 case DRM_FORMAT_XBGR8888:
8389 case DRM_FORMAT_ABGR8888:
04b3924d
VS		 8390 case DRM_FORMAT_XRGB2101010:
8391 case DRM_FORMAT_ARGB2101010:
57779d06
VS		 8392 case DRM_FORMAT_XBGR2101010:
8393 case DRM_FORMAT_ABGR2101010:
8394 if (INTEL_INFO(dev)->gen < 4)
8395 return -EINVAL;
b5626747 8396 break;
04b3924d
VS		 8397 case DRM_FORMAT_YUYV:
8398 case DRM_FORMAT_UYVY:
8399 case DRM_FORMAT_YVYU:
8400 case DRM_FORMAT_VYUY:
57779d06
VS		 8401 if (INTEL_INFO(dev)->gen < 6)
8402 return -EINVAL;
57cd6508
CW		 8403 break;
8404 default:
57779d06 8405 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
57cd6508
CW		 8406 return -EINVAL;
8407 }
8408
90f9a336
VS		 8409 /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8410 if (mode_cmd->offsets[0] != 0)
8411 return -EINVAL;
8412
79e53945
JB		 8413 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8414 if (ret) {
8415 DRM_ERROR("framebuffer init failed %d\n", ret);
8416 return ret;
8417 }
8418
8419 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 8420 intel_fb->obj = obj;
79e53945
JB		 8421 return 0;
8422}
8423
79e53945
JB		 8424static struct drm_framebuffer *
8425intel_user_framebuffer_create(struct drm_device *dev,
8426 struct drm_file *filp,
308e5bcb 8427 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 8428{
05394f39 8429 struct drm_i915_gem_object *obj;
79e53945 8430
308e5bcb
JB		 8431 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8432 mode_cmd->handles[0]));
c8725226 8433 if (&obj->base == NULL)
cce13ff7 8434 return ERR_PTR(-ENOENT);
79e53945 8435
d2dff872 8436 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 8437}
8438
79e53945 8439static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 8440 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 8441 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 8442};
8443
e70236a8
JB		 8444/* Set up chip specific display functions */
8445static void intel_init_display(struct drm_device *dev)
8446{
8447 struct drm_i915_private *dev_priv = dev->dev_private;
8448
8449 /* We always want a DPMS function */
affa9354 8450 if (HAS_DDI(dev)) {
09b4ddf9 8451 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
4f771f10
PZ		 8452 dev_priv->display.crtc_enable = haswell_crtc_enable;
8453 dev_priv->display.crtc_disable = haswell_crtc_disable;
6441ab5f 8454 dev_priv->display.off = haswell_crtc_off;
09b4ddf9
PZ		 8455 dev_priv->display.update_plane = ironlake_update_plane;
8456 } else if (HAS_PCH_SPLIT(dev)) {
f564048e 8457 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 8458 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8459 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 8460 dev_priv->display.off = ironlake_crtc_off;
17638cd6 8461 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8462 } else {
f564048e 8463 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 8464 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8465 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 8466 dev_priv->display.off = i9xx_crtc_off;
17638cd6 8467 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8468 }
e70236a8 8469
e70236a8 8470 /* Returns the core display clock speed */
25eb05fc
JB		 8471 if (IS_VALLEYVIEW(dev))
8472 dev_priv->display.get_display_clock_speed =
8473 valleyview_get_display_clock_speed;
8474 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8475 dev_priv->display.get_display_clock_speed =
8476 i945_get_display_clock_speed;
8477 else if (IS_I915G(dev))
8478 dev_priv->display.get_display_clock_speed =
8479 i915_get_display_clock_speed;
f2b115e6 8480 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8481 dev_priv->display.get_display_clock_speed =
8482 i9xx_misc_get_display_clock_speed;
8483 else if (IS_I915GM(dev))
8484 dev_priv->display.get_display_clock_speed =
8485 i915gm_get_display_clock_speed;
8486 else if (IS_I865G(dev))
8487 dev_priv->display.get_display_clock_speed =
8488 i865_get_display_clock_speed;
f0f8a9ce 8489 else if (IS_I85X(dev))
e70236a8
JB		 8490 dev_priv->display.get_display_clock_speed =
8491 i855_get_display_clock_speed;
8492 else /* 852, 830 */
8493 dev_priv->display.get_display_clock_speed =
8494 i830_get_display_clock_speed;
8495
7f8a8569 8496 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 8497 if (IS_GEN5(dev)) {
674cf967 8498 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 8499 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 8500 } else if (IS_GEN6(dev)) {
674cf967 8501 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 8502 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8503 } else if (IS_IVYBRIDGE(dev)) {
8504 /* FIXME: detect B0+ stepping and use auto training */
8505 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 8506 dev_priv->display.write_eld = ironlake_write_eld;
01a415fd
DV		 8507 dev_priv->display.modeset_global_resources =
8508 ivb_modeset_global_resources;
c82e4d26
ED		 8509 } else if (IS_HASWELL(dev)) {
8510 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 8511 dev_priv->display.write_eld = haswell_write_eld;
d6dd9eb1
DV		 8512 dev_priv->display.modeset_global_resources =
8513 haswell_modeset_global_resources;
a0e63c22 8514 }
6067aaea 8515 } else if (IS_G4X(dev)) {
e0dac65e 8516 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8517 }
8c9f3aaf
JB		 8518
8519 /* Default just returns -ENODEV to indicate unsupported */
8520 dev_priv->display.queue_flip = intel_default_queue_flip;
8521
8522 switch (INTEL_INFO(dev)->gen) {
8523 case 2:
8524 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8525 break;
8526
8527 case 3:
8528 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8529 break;
8530
8531 case 4:
8532 case 5:
8533 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8534 break;
8535
8536 case 6:
8537 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8538 break;
7c9017e5
JB		 8539 case 7:
8540 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8541 break;
8c9f3aaf 8542 }
e70236a8
JB		 8543}
8544
b690e96c
JB		 8545/*
8546 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8547 * resume, or other times. This quirk makes sure that's the case for
8548 * affected systems.
8549 */
0206e353 8550static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8551{
8552 struct drm_i915_private *dev_priv = dev->dev_private;
8553
8554 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 8555 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 8556}
8557
435793df
KP		 8558/*
8559 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8560 */
8561static void quirk_ssc_force_disable(struct drm_device *dev)
8562{
8563 struct drm_i915_private *dev_priv = dev->dev_private;
8564 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 8565 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 8566}
8567
4dca20ef 8568/*
5a15ab5b
CE		 8569 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8570 * brightness value
4dca20ef
CE		 8571 */
8572static void quirk_invert_brightness(struct drm_device *dev)
8573{
8574 struct drm_i915_private *dev_priv = dev->dev_private;
8575 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 8576 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 8577}
8578
b690e96c
JB		 8579struct intel_quirk {
8580 int device;
8581 int subsystem_vendor;
8582 int subsystem_device;
8583 void (*hook)(struct drm_device *dev);
8584};
8585
5f85f176
EE		 8586/* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8587struct intel_dmi_quirk {
8588 void (*hook)(struct drm_device *dev);
8589 const struct dmi_system_id (*dmi_id_list)[];
8590};
8591
8592static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8593{
8594 DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8595 return 1;
8596}
8597
8598static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8599 {
8600 .dmi_id_list = &(const struct dmi_system_id[]) {
8601 {
8602 .callback = intel_dmi_reverse_brightness,
8603 .ident = "NCR Corporation",
8604 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8605 DMI_MATCH(DMI_PRODUCT_NAME, ""),
8606 },
8607 },
8608 { } /* terminating entry */
8609 },
8610 .hook = quirk_invert_brightness,
8611 },
8612};
8613
c43b5634 8614static struct intel_quirk intel_quirks[] = {
b690e96c 8615 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8616 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 8617
b690e96c
JB		 8618 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8619 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8620
b690e96c
JB		 8621 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8622 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8623
ccd0d36e 8624 /* 830/845 need to leave pipe A & dpll A up */
b690e96c 8625 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 8626 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8627
8628 /* Lenovo U160 cannot use SSC on LVDS */
8629 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8630
8631 /* Sony Vaio Y cannot use SSC on LVDS */
8632 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 8633
8634 /* Acer Aspire 5734Z must invert backlight brightness */
8635 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
1ffff603
JN		 8636
8637 /* Acer/eMachines G725 */
8638 { 0x2a42, 0x1025, 0x0210, quirk_invert_brightness },
01e3a8fe
JN		 8639
8640 /* Acer/eMachines e725 */
8641 { 0x2a42, 0x1025, 0x0212, quirk_invert_brightness },
5559ecad
JN		 8642
8643 /* Acer/Packard Bell NCL20 */
8644 { 0x2a42, 0x1025, 0x034b, quirk_invert_brightness },
b690e96c
JB		 8645};
8646
8647static void intel_init_quirks(struct drm_device *dev)
8648{
8649 struct pci_dev *d = dev->pdev;
8650 int i;
8651
8652 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8653 struct intel_quirk *q = &intel_quirks[i];
8654
8655 if (d->device == q->device &&
8656 (d->subsystem_vendor == q->subsystem_vendor ||
8657 q->subsystem_vendor == PCI_ANY_ID) &&
8658 (d->subsystem_device == q->subsystem_device ||
8659 q->subsystem_device == PCI_ANY_ID))
8660 q->hook(dev);
8661 }
5f85f176
EE		 8662 for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8663 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8664 intel_dmi_quirks[i].hook(dev);
8665 }
b690e96c
JB		 8666}
8667
9cce37f4
JB		 8668/* Disable the VGA plane that we never use */
8669static void i915_disable_vga(struct drm_device *dev)
8670{
8671 struct drm_i915_private *dev_priv = dev->dev_private;
8672 u8 sr1;
8673 u32 vga_reg;
8674
8675 if (HAS_PCH_SPLIT(dev))
8676 vga_reg = CPU_VGACNTRL;
8677 else
8678 vga_reg = VGACNTRL;
8679
8680 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 8681 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 8682 sr1 = inb(VGA_SR_DATA);
8683 outb(sr1 | 1<<5, VGA_SR_DATA);
8684 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8685 udelay(300);
8686
8687 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8688 POSTING_READ(vga_reg);
8689}
8690
f817586c
DV		 8691void intel_modeset_init_hw(struct drm_device *dev)
8692{
fa42e23c 8693 intel_init_power_well(dev);
0232e927 8694
a8f78b58
ED		 8695 intel_prepare_ddi(dev);
8696
f817586c
DV		 8697 intel_init_clock_gating(dev);
8698
79f5b2c7 8699 mutex_lock(&dev->struct_mutex);
8090c6b9 8700 intel_enable_gt_powersave(dev);
79f5b2c7 8701 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 8702}
8703
79e53945
JB		 8704void intel_modeset_init(struct drm_device *dev)
8705{
652c393a 8706 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 8707 int i, ret;
79e53945
JB		 8708
8709 drm_mode_config_init(dev);
8710
8711 dev->mode_config.min_width = 0;
8712 dev->mode_config.min_height = 0;
8713
019d96cb
DA		 8714 dev->mode_config.preferred_depth = 24;
8715 dev->mode_config.prefer_shadow = 1;
8716
e6ecefaa 8717 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 8718
b690e96c
JB		 8719 intel_init_quirks(dev);
8720
1fa61106
ED		 8721 intel_init_pm(dev);
8722
e70236a8
JB		 8723 intel_init_display(dev);
8724
a6c45cf0
CW		 8725 if (IS_GEN2(dev)) {
8726 dev->mode_config.max_width = 2048;
8727 dev->mode_config.max_height = 2048;
8728 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 8729 dev->mode_config.max_width = 4096;
8730 dev->mode_config.max_height = 4096;
79e53945 8731 } else {
a6c45cf0
CW		 8732 dev->mode_config.max_width = 8192;
8733 dev->mode_config.max_height = 8192;
79e53945 8734 }
5d4545ae 8735 dev->mode_config.fb_base = dev_priv->gtt.mappable_base;
79e53945 8736
28c97730 8737 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 8738 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 8739
a3524f1b 8740 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 8741 intel_crtc_init(dev, i);
00c2064b
JB		 8742 ret = intel_plane_init(dev, i);
8743 if (ret)
8744 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 8745 }
8746
79f689aa 8747 intel_cpu_pll_init(dev);
ee7b9f93
JB		 8748 intel_pch_pll_init(dev);
8749
9cce37f4
JB		 8750 /* Just disable it once at startup */
8751 i915_disable_vga(dev);
79e53945 8752 intel_setup_outputs(dev);
11be49eb
CW		 8753
8754 /* Just in case the BIOS is doing something questionable. */
8755 intel_disable_fbc(dev);
2c7111db
CW		 8756}
8757
24929352
DV		 8758static void
8759intel_connector_break_all_links(struct intel_connector *connector)
8760{
8761 connector->base.dpms = DRM_MODE_DPMS_OFF;
8762 connector->base.encoder = NULL;
8763 connector->encoder->connectors_active = false;
8764 connector->encoder->base.crtc = NULL;
8765}
8766
7fad798e
DV		 8767static void intel_enable_pipe_a(struct drm_device *dev)
8768{
8769 struct intel_connector *connector;
8770 struct drm_connector *crt = NULL;
8771 struct intel_load_detect_pipe load_detect_temp;
8772
8773 /* We can't just switch on the pipe A, we need to set things up with a
8774 * proper mode and output configuration. As a gross hack, enable pipe A
8775 * by enabling the load detect pipe once. */
8776 list_for_each_entry(connector,
8777 &dev->mode_config.connector_list,
8778 base.head) {
8779 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8780 crt = &connector->base;
8781 break;
8782 }
8783 }
8784
8785 if (!crt)
8786 return;
8787
8788 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8789 intel_release_load_detect_pipe(crt, &load_detect_temp);
8790
652c393a 8791
7fad798e
DV		 8792}
8793
fa555837
DV		 8794static bool
8795intel_check_plane_mapping(struct intel_crtc *crtc)
8796{
8797 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8798 u32 reg, val;
8799
8800 if (dev_priv->num_pipe == 1)
8801 return true;
8802
8803 reg = DSPCNTR(!crtc->plane);
8804 val = I915_READ(reg);
8805
8806 if ((val & DISPLAY_PLANE_ENABLE) &&
8807 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8808 return false;
8809
8810 return true;
8811}
8812
24929352
DV		 8813static void intel_sanitize_crtc(struct intel_crtc *crtc)
8814{
8815 struct drm_device *dev = crtc->base.dev;
8816 struct drm_i915_private *dev_priv = dev->dev_private;
fa555837 8817 u32 reg;
24929352 8818
24929352 8819 /* Clear any frame start delays used for debugging left by the BIOS */
702e7a56 8820 reg = PIPECONF(crtc->cpu_transcoder);
24929352
DV		 8821 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8822
8823 /* We need to sanitize the plane -> pipe mapping first because this will
fa555837
DV		 8824 * disable the crtc (and hence change the state) if it is wrong. Note
8825 * that gen4+ has a fixed plane -> pipe mapping. */
8826 if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
24929352
DV		 8827 struct intel_connector *connector;
8828 bool plane;
8829
24929352
DV		 8830 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8831 crtc->base.base.id);
8832
8833 /* Pipe has the wrong plane attached and the plane is active.
8834 * Temporarily change the plane mapping and disable everything
8835 * ... */
8836 plane = crtc->plane;
8837 crtc->plane = !plane;
8838 dev_priv->display.crtc_disable(&crtc->base);
8839 crtc->plane = plane;
8840
8841 /* ... and break all links. */
8842 list_for_each_entry(connector, &dev->mode_config.connector_list,
8843 base.head) {
8844 if (connector->encoder->base.crtc != &crtc->base)
8845 continue;
8846
8847 intel_connector_break_all_links(connector);
8848 }
8849
8850 WARN_ON(crtc->active);
8851 crtc->base.enabled = false;
8852 }
24929352 8853
7fad798e
DV		 8854 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8855 crtc->pipe == PIPE_A && !crtc->active) {
8856 /* BIOS forgot to enable pipe A, this mostly happens after
8857 * resume. Force-enable the pipe to fix this, the update_dpms
8858 * call below we restore the pipe to the right state, but leave
8859 * the required bits on. */
8860 intel_enable_pipe_a(dev);
8861 }
8862
24929352
DV		 8863 /* Adjust the state of the output pipe according to whether we
8864 * have active connectors/encoders. */
8865 intel_crtc_update_dpms(&crtc->base);
8866
8867 if (crtc->active != crtc->base.enabled) {
8868 struct intel_encoder *encoder;
8869
8870 /* This can happen either due to bugs in the get_hw_state
8871 * functions or because the pipe is force-enabled due to the
8872 * pipe A quirk. */
8873 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8874 crtc->base.base.id,
8875 crtc->base.enabled ? "enabled" : "disabled",
8876 crtc->active ? "enabled" : "disabled");
8877
8878 crtc->base.enabled = crtc->active;
8879
8880 /* Because we only establish the connector -> encoder ->
8881 * crtc links if something is active, this means the
8882 * crtc is now deactivated. Break the links. connector
8883 * -> encoder links are only establish when things are
8884 * actually up, hence no need to break them. */
8885 WARN_ON(crtc->active);
8886
8887 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8888 WARN_ON(encoder->connectors_active);
8889 encoder->base.crtc = NULL;
8890 }
8891 }
8892}
8893
8894static void intel_sanitize_encoder(struct intel_encoder *encoder)
8895{
8896 struct intel_connector *connector;
8897 struct drm_device *dev = encoder->base.dev;
8898
8899 /* We need to check both for a crtc link (meaning that the
8900 * encoder is active and trying to read from a pipe) and the
8901 * pipe itself being active. */
8902 bool has_active_crtc = encoder->base.crtc &&
8903 to_intel_crtc(encoder->base.crtc)->active;
8904
8905 if (encoder->connectors_active && !has_active_crtc) {
8906 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8907 encoder->base.base.id,
8908 drm_get_encoder_name(&encoder->base));
8909
8910 /* Connector is active, but has no active pipe. This is
8911 * fallout from our resume register restoring. Disable
8912 * the encoder manually again. */
8913 if (encoder->base.crtc) {
8914 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8915 encoder->base.base.id,
8916 drm_get_encoder_name(&encoder->base));
8917 encoder->disable(encoder);
8918 }
8919
8920 /* Inconsistent output/port/pipe state happens presumably due to
8921 * a bug in one of the get_hw_state functions. Or someplace else
8922 * in our code, like the register restore mess on resume. Clamp
8923 * things to off as a safer default. */
8924 list_for_each_entry(connector,
8925 &dev->mode_config.connector_list,
8926 base.head) {
8927 if (connector->encoder != encoder)
8928 continue;
8929
8930 intel_connector_break_all_links(connector);
8931 }
8932 }
8933 /* Enabled encoders without active connectors will be fixed in
8934 * the crtc fixup. */
8935}
8936
44cec740 8937void i915_redisable_vga(struct drm_device *dev)
0fde901f
KM		 8938{
8939 struct drm_i915_private *dev_priv = dev->dev_private;
8940 u32 vga_reg;
8941
8942 if (HAS_PCH_SPLIT(dev))
8943 vga_reg = CPU_VGACNTRL;
8944 else
8945 vga_reg = VGACNTRL;
8946
8947 if (I915_READ(vga_reg) != VGA_DISP_DISABLE) {
8948 DRM_DEBUG_KMS("Something enabled VGA plane, disabling it\n");
8949 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8950 POSTING_READ(vga_reg);
8951 }
8952}
8953
24929352
DV		 8954/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8955 * and i915 state tracking structures. */
45e2b5f6
DV		 8956void intel_modeset_setup_hw_state(struct drm_device *dev,
8957 bool force_restore)
24929352
DV		 8958{
8959 struct drm_i915_private *dev_priv = dev->dev_private;
8960 enum pipe pipe;
8961 u32 tmp;
8962 struct intel_crtc *crtc;
8963 struct intel_encoder *encoder;
8964 struct intel_connector *connector;
8965
affa9354 8966 if (HAS_DDI(dev)) {
e28d54cb
PZ		 8967 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8968
8969 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8970 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8971 case TRANS_DDI_EDP_INPUT_A_ON:
8972 case TRANS_DDI_EDP_INPUT_A_ONOFF:
8973 pipe = PIPE_A;
8974 break;
8975 case TRANS_DDI_EDP_INPUT_B_ONOFF:
8976 pipe = PIPE_B;
8977 break;
8978 case TRANS_DDI_EDP_INPUT_C_ONOFF:
8979 pipe = PIPE_C;
8980 break;
8981 }
8982
8983 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8984 crtc->cpu_transcoder = TRANSCODER_EDP;
8985
8986 DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8987 pipe_name(pipe));
8988 }
8989 }
8990
24929352
DV		 8991 for_each_pipe(pipe) {
8992 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8993
702e7a56 8994 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
24929352
DV		 8995 if (tmp & PIPECONF_ENABLE)
8996 crtc->active = true;
8997 else
8998 crtc->active = false;
8999
9000 crtc->base.enabled = crtc->active;
9001
9002 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
9003 crtc->base.base.id,
9004 crtc->active ? "enabled" : "disabled");
9005 }
9006
affa9354 9007 if (HAS_DDI(dev))
6441ab5f
PZ		 9008 intel_ddi_setup_hw_pll_state(dev);
9009
24929352
DV		 9010 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9011 base.head) {
9012 pipe = 0;
9013
9014 if (encoder->get_hw_state(encoder, &pipe)) {
9015 encoder->base.crtc =
9016 dev_priv->pipe_to_crtc_mapping[pipe];
9017 } else {
9018 encoder->base.crtc = NULL;
9019 }
9020
9021 encoder->connectors_active = false;
9022 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
9023 encoder->base.base.id,
9024 drm_get_encoder_name(&encoder->base),
9025 encoder->base.crtc ? "enabled" : "disabled",
9026 pipe);
9027 }
9028
9029 list_for_each_entry(connector, &dev->mode_config.connector_list,
9030 base.head) {
9031 if (connector->get_hw_state(connector)) {
9032 connector->base.dpms = DRM_MODE_DPMS_ON;
9033 connector->encoder->connectors_active = true;
9034 connector->base.encoder = &connector->encoder->base;
9035 } else {
9036 connector->base.dpms = DRM_MODE_DPMS_OFF;
9037 connector->base.encoder = NULL;
9038 }
9039 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
9040 connector->base.base.id,
9041 drm_get_connector_name(&connector->base),
9042 connector->base.encoder ? "enabled" : "disabled");
9043 }
9044
9045 /* HW state is read out, now we need to sanitize this mess. */
9046 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
9047 base.head) {
9048 intel_sanitize_encoder(encoder);
9049 }
9050
9051 for_each_pipe(pipe) {
9052 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
9053 intel_sanitize_crtc(crtc);
9054 }
9a935856 9055
45e2b5f6
DV		 9056 if (force_restore) {
9057 for_each_pipe(pipe) {
c0c36b94 9058 intel_crtc_restore_mode(dev_priv->pipe_to_crtc_mapping[pipe]);
45e2b5f6 9059 }
0fde901f
KM		 9060
9061 i915_redisable_vga(dev);
45e2b5f6
DV		 9062 } else {
9063 intel_modeset_update_staged_output_state(dev);
9064 }
8af6cf88
DV		 9065
9066 intel_modeset_check_state(dev);
2e938892
DV		 9067
9068 drm_mode_config_reset(dev);
2c7111db
CW		 9069}
9070
9071void intel_modeset_gem_init(struct drm_device *dev)
9072{
1833b134 9073 intel_modeset_init_hw(dev);
02e792fb
DV		 9074
9075 intel_setup_overlay(dev);
24929352 9076
45e2b5f6 9077 intel_modeset_setup_hw_state(dev, false);
79e53945
JB		 9078}
9079
9080void intel_modeset_cleanup(struct drm_device *dev)
9081{
652c393a
JB		 9082 struct drm_i915_private *dev_priv = dev->dev_private;
9083 struct drm_crtc *crtc;
9084 struct intel_crtc *intel_crtc;
9085
f87ea761 9086 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9087 mutex_lock(&dev->struct_mutex);
9088
723bfd70
JB		 9089 intel_unregister_dsm_handler();
9090
9091
652c393a
JB		 9092 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9093 /* Skip inactive CRTCs */
9094 if (!crtc->fb)
9095 continue;
9096
9097 intel_crtc = to_intel_crtc(crtc);
3dec0095 9098 intel_increase_pllclock(crtc);
652c393a
JB		 9099 }
9100
973d04f9 9101 intel_disable_fbc(dev);
e70236a8 9102
8090c6b9 9103 intel_disable_gt_powersave(dev);
0cdab21f 9104
930ebb46
DV		 9105 ironlake_teardown_rc6(dev);
9106
57f350b6
JB		 9107 if (IS_VALLEYVIEW(dev))
9108 vlv_init_dpio(dev);
9109
69341a5e
KH		 9110 mutex_unlock(&dev->struct_mutex);
9111
6c0d9350
DV		 9112 /* Disable the irq before mode object teardown, for the irq might
9113 * enqueue unpin/hotplug work. */
9114 drm_irq_uninstall(dev);
9115 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 9116 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 9117
1630fe75
CW		 9118 /* flush any delayed tasks or pending work */
9119 flush_scheduled_work();
9120
79e53945 9121 drm_mode_config_cleanup(dev);
4d7bb011
DV		 9122
9123 intel_cleanup_overlay(dev);
79e53945
JB		 9124}
9125
f1c79df3
ZW		 9126/*
9127 * Return which encoder is currently attached for connector.
9128 */
df0e9248 9129struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9130{
df0e9248
CW		 9131 return &intel_attached_encoder(connector)->base;
9132}
f1c79df3 9133
df0e9248
CW		 9134void intel_connector_attach_encoder(struct intel_connector *connector,
9135 struct intel_encoder *encoder)
9136{
9137 connector->encoder = encoder;
9138 drm_mode_connector_attach_encoder(&connector->base,
9139 &encoder->base);
79e53945 9140}
28d52043
DA		 9141
9142/*
9143 * set vga decode state - true == enable VGA decode
9144 */
9145int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9146{
9147 struct drm_i915_private *dev_priv = dev->dev_private;
9148 u16 gmch_ctrl;
9149
9150 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9151 if (state)
9152 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9153 else
9154 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9155 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9156 return 0;
9157}
c4a1d9e4
CW		 9158
9159#ifdef CONFIG_DEBUG_FS
9160#include <linux/seq_file.h>
9161
9162struct intel_display_error_state {
9163 struct intel_cursor_error_state {
9164 u32 control;
9165 u32 position;
9166 u32 base;
9167 u32 size;
52331309 9168 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 9169
9170 struct intel_pipe_error_state {
9171 u32 conf;
9172 u32 source;
9173
9174 u32 htotal;
9175 u32 hblank;
9176 u32 hsync;
9177 u32 vtotal;
9178 u32 vblank;
9179 u32 vsync;
52331309 9180 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 9181
9182 struct intel_plane_error_state {
9183 u32 control;
9184 u32 stride;
9185 u32 size;
9186 u32 pos;
9187 u32 addr;
9188 u32 surface;
9189 u32 tile_offset;
52331309 9190 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 9191};
9192
9193struct intel_display_error_state *
9194intel_display_capture_error_state(struct drm_device *dev)
9195{
0206e353 9196 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4 9197 struct intel_display_error_state *error;
702e7a56 9198 enum transcoder cpu_transcoder;
c4a1d9e4
CW		 9199 int i;
9200
9201 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9202 if (error == NULL)
9203 return NULL;
9204
52331309 9205 for_each_pipe(i) {
702e7a56
PZ		 9206 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9207
c4a1d9e4
CW		 9208 error->cursor[i].control = I915_READ(CURCNTR(i));
9209 error->cursor[i].position = I915_READ(CURPOS(i));
9210 error->cursor[i].base = I915_READ(CURBASE(i));
9211
9212 error->plane[i].control = I915_READ(DSPCNTR(i));
9213 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9214 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9215 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9216 error->plane[i].addr = I915_READ(DSPADDR(i));
9217 if (INTEL_INFO(dev)->gen >= 4) {
9218 error->plane[i].surface = I915_READ(DSPSURF(i));
9219 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9220 }
9221
702e7a56 9222 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
c4a1d9e4 9223 error->pipe[i].source = I915_READ(PIPESRC(i));
fe2b8f9d
PZ		 9224 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9225 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9226 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9227 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9228 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9229 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
c4a1d9e4
CW		 9230 }
9231
9232 return error;
9233}
9234
9235void
9236intel_display_print_error_state(struct seq_file *m,
9237 struct drm_device *dev,
9238 struct intel_display_error_state *error)
9239{
52331309 9240 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9241 int i;
9242
52331309
DL		 9243 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9244 for_each_pipe(i) {
c4a1d9e4
CW		 9245 seq_printf(m, "Pipe [%d]:\n", i);
9246 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9247 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9248 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9249 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9250 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9251 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9252 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9253 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9254
9255 seq_printf(m, "Plane [%d]:\n", i);
9256 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9257 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9258 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9259 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9260 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9261 if (INTEL_INFO(dev)->gen >= 4) {
9262 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9263 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9264 }
9265
9266 seq_printf(m, "Cursor [%d]:\n", i);
9267 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9268 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9269 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9270 }
9271}
9272#endif
Linux kernel - Deliverables
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