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drm/i915: use staged outuput config in lvds->mode_fixup
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
618563e3 27#include <linux/dmi.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
3dec0095 47static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 48static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 49
50typedef struct {
0206e353
AJ		 51 /* given values */
52 int n;
53 int m1, m2;
54 int p1, p2;
55 /* derived values */
56 int dot;
57 int vco;
58 int m;
59 int p;
79e53945
JB		 60} intel_clock_t;
61
62typedef struct {
0206e353 63 int min, max;
79e53945
JB		 64} intel_range_t;
65
66typedef struct {
0206e353
AJ		 67 int dot_limit;
68 int p2_slow, p2_fast;
79e53945
JB		 69} intel_p2_t;
70
71#define INTEL_P2_NUM 2
d4906093
ML		 72typedef struct intel_limit intel_limit_t;
73struct intel_limit {
0206e353
AJ		 74 intel_range_t dot, vco, n, m, m1, m2, p, p1;
75 intel_p2_t p2;
76 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
cec2f356 77 int, int, intel_clock_t *, intel_clock_t *);
d4906093 78};
79e53945 79
2377b741
JB		 80/* FDI */
81#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
82
d4906093
ML		 83static bool
84intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 85 int target, int refclk, intel_clock_t *match_clock,
86 intel_clock_t *best_clock);
d4906093
ML		 87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 89 int target, int refclk, intel_clock_t *match_clock,
90 intel_clock_t *best_clock);
79e53945 91
a4fc5ed6
KP		 92static bool
93intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 94 int target, int refclk, intel_clock_t *match_clock,
95 intel_clock_t *best_clock);
5eb08b69 96static bool
f2b115e6 97intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
cec2f356
SP		 98 int target, int refclk, intel_clock_t *match_clock,
99 intel_clock_t *best_clock);
a4fc5ed6 100
a0c4da24
JB		 101static bool
102intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
103 int target, int refclk, intel_clock_t *match_clock,
104 intel_clock_t *best_clock);
105
021357ac
CW		 106static inline u32 /* units of 100MHz */
107intel_fdi_link_freq(struct drm_device *dev)
108{
8b99e68c
CW		 109 if (IS_GEN5(dev)) {
110 struct drm_i915_private *dev_priv = dev->dev_private;
111 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
112 } else
113 return 27;
021357ac
CW		 114}
115
e4b36699 116static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 117 .dot = { .min = 25000, .max = 350000 },
118 .vco = { .min = 930000, .max = 1400000 },
119 .n = { .min = 3, .max = 16 },
120 .m = { .min = 96, .max = 140 },
121 .m1 = { .min = 18, .max = 26 },
122 .m2 = { .min = 6, .max = 16 },
123 .p = { .min = 4, .max = 128 },
124 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 125 .p2 = { .dot_limit = 165000,
126 .p2_slow = 4, .p2_fast = 2 },
d4906093 127 .find_pll = intel_find_best_PLL,
e4b36699
KP		 128};
129
130static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 131 .dot = { .min = 25000, .max = 350000 },
132 .vco = { .min = 930000, .max = 1400000 },
133 .n = { .min = 3, .max = 16 },
134 .m = { .min = 96, .max = 140 },
135 .m1 = { .min = 18, .max = 26 },
136 .m2 = { .min = 6, .max = 16 },
137 .p = { .min = 4, .max = 128 },
138 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 139 .p2 = { .dot_limit = 165000,
140 .p2_slow = 14, .p2_fast = 7 },
d4906093 141 .find_pll = intel_find_best_PLL,
e4b36699 142};
273e27ca 143
e4b36699 144static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 145 .dot = { .min = 20000, .max = 400000 },
146 .vco = { .min = 1400000, .max = 2800000 },
147 .n = { .min = 1, .max = 6 },
148 .m = { .min = 70, .max = 120 },
149 .m1 = { .min = 10, .max = 22 },
150 .m2 = { .min = 5, .max = 9 },
151 .p = { .min = 5, .max = 80 },
152 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 153 .p2 = { .dot_limit = 200000,
154 .p2_slow = 10, .p2_fast = 5 },
d4906093 155 .find_pll = intel_find_best_PLL,
e4b36699
KP		 156};
157
158static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 159 .dot = { .min = 20000, .max = 400000 },
160 .vco = { .min = 1400000, .max = 2800000 },
161 .n = { .min = 1, .max = 6 },
162 .m = { .min = 70, .max = 120 },
163 .m1 = { .min = 10, .max = 22 },
164 .m2 = { .min = 5, .max = 9 },
165 .p = { .min = 7, .max = 98 },
166 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 167 .p2 = { .dot_limit = 112000,
168 .p2_slow = 14, .p2_fast = 7 },
d4906093 169 .find_pll = intel_find_best_PLL,
e4b36699
KP		 170};
171
273e27ca 172
e4b36699 173static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 174 .dot = { .min = 25000, .max = 270000 },
175 .vco = { .min = 1750000, .max = 3500000},
176 .n = { .min = 1, .max = 4 },
177 .m = { .min = 104, .max = 138 },
178 .m1 = { .min = 17, .max = 23 },
179 .m2 = { .min = 5, .max = 11 },
180 .p = { .min = 10, .max = 30 },
181 .p1 = { .min = 1, .max = 3},
182 .p2 = { .dot_limit = 270000,
183 .p2_slow = 10,
184 .p2_fast = 10
044c7c41 185 },
d4906093 186 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 187};
188
189static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 190 .dot = { .min = 22000, .max = 400000 },
191 .vco = { .min = 1750000, .max = 3500000},
192 .n = { .min = 1, .max = 4 },
193 .m = { .min = 104, .max = 138 },
194 .m1 = { .min = 16, .max = 23 },
195 .m2 = { .min = 5, .max = 11 },
196 .p = { .min = 5, .max = 80 },
197 .p1 = { .min = 1, .max = 8},
198 .p2 = { .dot_limit = 165000,
199 .p2_slow = 10, .p2_fast = 5 },
d4906093 200 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 201};
202
203static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 204 .dot = { .min = 20000, .max = 115000 },
205 .vco = { .min = 1750000, .max = 3500000 },
206 .n = { .min = 1, .max = 3 },
207 .m = { .min = 104, .max = 138 },
208 .m1 = { .min = 17, .max = 23 },
209 .m2 = { .min = 5, .max = 11 },
210 .p = { .min = 28, .max = 112 },
211 .p1 = { .min = 2, .max = 8 },
212 .p2 = { .dot_limit = 0,
213 .p2_slow = 14, .p2_fast = 14
044c7c41 214 },
d4906093 215 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 216};
217
218static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 219 .dot = { .min = 80000, .max = 224000 },
220 .vco = { .min = 1750000, .max = 3500000 },
221 .n = { .min = 1, .max = 3 },
222 .m = { .min = 104, .max = 138 },
223 .m1 = { .min = 17, .max = 23 },
224 .m2 = { .min = 5, .max = 11 },
225 .p = { .min = 14, .max = 42 },
226 .p1 = { .min = 2, .max = 6 },
227 .p2 = { .dot_limit = 0,
228 .p2_slow = 7, .p2_fast = 7
044c7c41 229 },
d4906093 230 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 231};
232
233static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 234 .dot = { .min = 161670, .max = 227000 },
235 .vco = { .min = 1750000, .max = 3500000},
236 .n = { .min = 1, .max = 2 },
237 .m = { .min = 97, .max = 108 },
238 .m1 = { .min = 0x10, .max = 0x12 },
239 .m2 = { .min = 0x05, .max = 0x06 },
240 .p = { .min = 10, .max = 20 },
241 .p1 = { .min = 1, .max = 2},
242 .p2 = { .dot_limit = 0,
273e27ca 243 .p2_slow = 10, .p2_fast = 10 },
0206e353 244 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 245};
246
f2b115e6 247static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 248 .dot = { .min = 20000, .max = 400000},
249 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 250 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 251 .n = { .min = 3, .max = 6 },
252 .m = { .min = 2, .max = 256 },
273e27ca 253 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 254 .m1 = { .min = 0, .max = 0 },
255 .m2 = { .min = 0, .max = 254 },
256 .p = { .min = 5, .max = 80 },
257 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 258 .p2 = { .dot_limit = 200000,
259 .p2_slow = 10, .p2_fast = 5 },
6115707b 260 .find_pll = intel_find_best_PLL,
e4b36699
KP		 261};
262
f2b115e6 263static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 264 .dot = { .min = 20000, .max = 400000 },
265 .vco = { .min = 1700000, .max = 3500000 },
266 .n = { .min = 3, .max = 6 },
267 .m = { .min = 2, .max = 256 },
268 .m1 = { .min = 0, .max = 0 },
269 .m2 = { .min = 0, .max = 254 },
270 .p = { .min = 7, .max = 112 },
271 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 272 .p2 = { .dot_limit = 112000,
273 .p2_slow = 14, .p2_fast = 14 },
6115707b 274 .find_pll = intel_find_best_PLL,
e4b36699
KP		 275};
276
273e27ca
EA		 277/* Ironlake / Sandybridge
278 *
279 * We calculate clock using (register_value + 2) for N/M1/M2, so here
280 * the range value for them is (actual_value - 2).
281 */
b91ad0ec 282static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 283 .dot = { .min = 25000, .max = 350000 },
284 .vco = { .min = 1760000, .max = 3510000 },
285 .n = { .min = 1, .max = 5 },
286 .m = { .min = 79, .max = 127 },
287 .m1 = { .min = 12, .max = 22 },
288 .m2 = { .min = 5, .max = 9 },
289 .p = { .min = 5, .max = 80 },
290 .p1 = { .min = 1, .max = 8 },
291 .p2 = { .dot_limit = 225000,
292 .p2_slow = 10, .p2_fast = 5 },
4547668a 293 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 294};
295
b91ad0ec 296static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 297 .dot = { .min = 25000, .max = 350000 },
298 .vco = { .min = 1760000, .max = 3510000 },
299 .n = { .min = 1, .max = 3 },
300 .m = { .min = 79, .max = 118 },
301 .m1 = { .min = 12, .max = 22 },
302 .m2 = { .min = 5, .max = 9 },
303 .p = { .min = 28, .max = 112 },
304 .p1 = { .min = 2, .max = 8 },
305 .p2 = { .dot_limit = 225000,
306 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 307 .find_pll = intel_g4x_find_best_PLL,
308};
309
310static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 311 .dot = { .min = 25000, .max = 350000 },
312 .vco = { .min = 1760000, .max = 3510000 },
313 .n = { .min = 1, .max = 3 },
314 .m = { .min = 79, .max = 127 },
315 .m1 = { .min = 12, .max = 22 },
316 .m2 = { .min = 5, .max = 9 },
317 .p = { .min = 14, .max = 56 },
318 .p1 = { .min = 2, .max = 8 },
319 .p2 = { .dot_limit = 225000,
320 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 321 .find_pll = intel_g4x_find_best_PLL,
322};
323
273e27ca 324/* LVDS 100mhz refclk limits. */
b91ad0ec 325static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 326 .dot = { .min = 25000, .max = 350000 },
327 .vco = { .min = 1760000, .max = 3510000 },
328 .n = { .min = 1, .max = 2 },
329 .m = { .min = 79, .max = 126 },
330 .m1 = { .min = 12, .max = 22 },
331 .m2 = { .min = 5, .max = 9 },
332 .p = { .min = 28, .max = 112 },
0206e353 333 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 334 .p2 = { .dot_limit = 225000,
335 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 336 .find_pll = intel_g4x_find_best_PLL,
337};
338
339static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 340 .dot = { .min = 25000, .max = 350000 },
341 .vco = { .min = 1760000, .max = 3510000 },
342 .n = { .min = 1, .max = 3 },
343 .m = { .min = 79, .max = 126 },
344 .m1 = { .min = 12, .max = 22 },
345 .m2 = { .min = 5, .max = 9 },
346 .p = { .min = 14, .max = 42 },
0206e353 347 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 348 .p2 = { .dot_limit = 225000,
349 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 350 .find_pll = intel_g4x_find_best_PLL,
351};
352
353static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 354 .dot = { .min = 25000, .max = 350000 },
355 .vco = { .min = 1760000, .max = 3510000},
356 .n = { .min = 1, .max = 2 },
357 .m = { .min = 81, .max = 90 },
358 .m1 = { .min = 12, .max = 22 },
359 .m2 = { .min = 5, .max = 9 },
360 .p = { .min = 10, .max = 20 },
361 .p1 = { .min = 1, .max = 2},
362 .p2 = { .dot_limit = 0,
273e27ca 363 .p2_slow = 10, .p2_fast = 10 },
0206e353 364 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 365};
366
a0c4da24
JB		 367static const intel_limit_t intel_limits_vlv_dac = {
368 .dot = { .min = 25000, .max = 270000 },
369 .vco = { .min = 4000000, .max = 6000000 },
370 .n = { .min = 1, .max = 7 },
371 .m = { .min = 22, .max = 450 }, /* guess */
372 .m1 = { .min = 2, .max = 3 },
373 .m2 = { .min = 11, .max = 156 },
374 .p = { .min = 10, .max = 30 },
375 .p1 = { .min = 2, .max = 3 },
376 .p2 = { .dot_limit = 270000,
377 .p2_slow = 2, .p2_fast = 20 },
378 .find_pll = intel_vlv_find_best_pll,
379};
380
381static const intel_limit_t intel_limits_vlv_hdmi = {
382 .dot = { .min = 20000, .max = 165000 },
383 .vco = { .min = 5994000, .max = 4000000 },
384 .n = { .min = 1, .max = 7 },
385 .m = { .min = 60, .max = 300 }, /* guess */
386 .m1 = { .min = 2, .max = 3 },
387 .m2 = { .min = 11, .max = 156 },
388 .p = { .min = 10, .max = 30 },
389 .p1 = { .min = 2, .max = 3 },
390 .p2 = { .dot_limit = 270000,
391 .p2_slow = 2, .p2_fast = 20 },
392 .find_pll = intel_vlv_find_best_pll,
393};
394
395static const intel_limit_t intel_limits_vlv_dp = {
396 .dot = { .min = 162000, .max = 270000 },
397 .vco = { .min = 5994000, .max = 4000000 },
398 .n = { .min = 1, .max = 7 },
399 .m = { .min = 60, .max = 300 }, /* guess */
400 .m1 = { .min = 2, .max = 3 },
401 .m2 = { .min = 11, .max = 156 },
402 .p = { .min = 10, .max = 30 },
403 .p1 = { .min = 2, .max = 3 },
404 .p2 = { .dot_limit = 270000,
405 .p2_slow = 2, .p2_fast = 20 },
406 .find_pll = intel_vlv_find_best_pll,
407};
408
57f350b6
JB		 409u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
410{
411 unsigned long flags;
412 u32 val = 0;
413
414 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
415 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
416 DRM_ERROR("DPIO idle wait timed out\n");
417 goto out_unlock;
418 }
419
420 I915_WRITE(DPIO_REG, reg);
421 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
422 DPIO_BYTE);
423 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
424 DRM_ERROR("DPIO read wait timed out\n");
425 goto out_unlock;
426 }
427 val = I915_READ(DPIO_DATA);
428
429out_unlock:
430 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
431 return val;
432}
433
a0c4da24
JB		 434static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
435 u32 val)
436{
437 unsigned long flags;
438
439 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
440 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
441 DRM_ERROR("DPIO idle wait timed out\n");
442 goto out_unlock;
443 }
444
445 I915_WRITE(DPIO_DATA, val);
446 I915_WRITE(DPIO_REG, reg);
447 I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
448 DPIO_BYTE);
449 if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
450 DRM_ERROR("DPIO write wait timed out\n");
451
452out_unlock:
453 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
454}
455
57f350b6
JB		 456static void vlv_init_dpio(struct drm_device *dev)
457{
458 struct drm_i915_private *dev_priv = dev->dev_private;
459
460 /* Reset the DPIO config */
461 I915_WRITE(DPIO_CTL, 0);
462 POSTING_READ(DPIO_CTL);
463 I915_WRITE(DPIO_CTL, 1);
464 POSTING_READ(DPIO_CTL);
465}
466
618563e3
DV		 467static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
468{
469 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
470 return 1;
471}
472
473static const struct dmi_system_id intel_dual_link_lvds[] = {
474 {
475 .callback = intel_dual_link_lvds_callback,
476 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
477 .matches = {
478 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
479 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
480 },
481 },
482 { } /* terminating entry */
483};
484
b0354385
TI		 485static bool is_dual_link_lvds(struct drm_i915_private *dev_priv,
486 unsigned int reg)
487{
488 unsigned int val;
489
121d527a
TI		 490 /* use the module option value if specified */
491 if (i915_lvds_channel_mode > 0)
492 return i915_lvds_channel_mode == 2;
493
618563e3
DV		 494 if (dmi_check_system(intel_dual_link_lvds))
495 return true;
496
b0354385
TI		 497 if (dev_priv->lvds_val)
498 val = dev_priv->lvds_val;
499 else {
500 /* BIOS should set the proper LVDS register value at boot, but
501 * in reality, it doesn't set the value when the lid is closed;
502 * we need to check "the value to be set" in VBT when LVDS
503 * register is uninitialized.
504 */
505 val = I915_READ(reg);
14d94a3d 506 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
b0354385
TI		 507 val = dev_priv->bios_lvds_val;
508 dev_priv->lvds_val = val;
509 }
510 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
511}
512
1b894b59
CW		 513static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
514 int refclk)
2c07245f 515{
b91ad0ec
ZW		 516 struct drm_device *dev = crtc->dev;
517 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 518 const intel_limit_t *limit;
b91ad0ec
ZW		 519
520 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 521 if (is_dual_link_lvds(dev_priv, PCH_LVDS)) {
b91ad0ec 522 /* LVDS dual channel */
1b894b59 523 if (refclk == 100000)
b91ad0ec
ZW		 524 limit = &intel_limits_ironlake_dual_lvds_100m;
525 else
526 limit = &intel_limits_ironlake_dual_lvds;
527 } else {
1b894b59 528 if (refclk == 100000)
b91ad0ec
ZW		 529 limit = &intel_limits_ironlake_single_lvds_100m;
530 else
531 limit = &intel_limits_ironlake_single_lvds;
532 }
533 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 534 HAS_eDP)
535 limit = &intel_limits_ironlake_display_port;
2c07245f 536 else
b91ad0ec 537 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 538
539 return limit;
540}
541
044c7c41
ML		 542static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
543{
544 struct drm_device *dev = crtc->dev;
545 struct drm_i915_private *dev_priv = dev->dev_private;
546 const intel_limit_t *limit;
547
548 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b0354385 549 if (is_dual_link_lvds(dev_priv, LVDS))
044c7c41 550 /* LVDS with dual channel */
e4b36699 551 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 552 else
553 /* LVDS with dual channel */
e4b36699 554 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 555 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
556 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 557 limit = &intel_limits_g4x_hdmi;
044c7c41 558 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 559 limit = &intel_limits_g4x_sdvo;
0206e353 560 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 561 limit = &intel_limits_g4x_display_port;
044c7c41 562 } else /* The option is for other outputs */
e4b36699 563 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 564
565 return limit;
566}
567
1b894b59 568static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 569{
570 struct drm_device *dev = crtc->dev;
571 const intel_limit_t *limit;
572
bad720ff 573 if (HAS_PCH_SPLIT(dev))
1b894b59 574 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 575 else if (IS_G4X(dev)) {
044c7c41 576 limit = intel_g4x_limit(crtc);
f2b115e6 577 } else if (IS_PINEVIEW(dev)) {
2177832f 578 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 579 limit = &intel_limits_pineview_lvds;
2177832f 580 else
f2b115e6 581 limit = &intel_limits_pineview_sdvo;
a0c4da24
JB		 582 } else if (IS_VALLEYVIEW(dev)) {
583 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
584 limit = &intel_limits_vlv_dac;
585 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
586 limit = &intel_limits_vlv_hdmi;
587 else
588 limit = &intel_limits_vlv_dp;
a6c45cf0
CW		 589 } else if (!IS_GEN2(dev)) {
590 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
591 limit = &intel_limits_i9xx_lvds;
592 else
593 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 594 } else {
595 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 596 limit = &intel_limits_i8xx_lvds;
79e53945 597 else
e4b36699 598 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 599 }
600 return limit;
601}
602
f2b115e6
AJ		 603/* m1 is reserved as 0 in Pineview, n is a ring counter */
604static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 605{
2177832f
SL		 606 clock->m = clock->m2 + 2;
607 clock->p = clock->p1 * clock->p2;
608 clock->vco = refclk * clock->m / clock->n;
609 clock->dot = clock->vco / clock->p;
610}
611
612static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
613{
f2b115e6
AJ		 614 if (IS_PINEVIEW(dev)) {
615 pineview_clock(refclk, clock);
2177832f
SL		 616 return;
617 }
79e53945
JB		 618 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
619 clock->p = clock->p1 * clock->p2;
620 clock->vco = refclk * clock->m / (clock->n + 2);
621 clock->dot = clock->vco / clock->p;
622}
623
79e53945
JB		 624/**
625 * Returns whether any output on the specified pipe is of the specified type
626 */
4ef69c7a 627bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 628{
4ef69c7a 629 struct drm_device *dev = crtc->dev;
4ef69c7a
CW		 630 struct intel_encoder *encoder;
631
6c2b7c12
DV		 632 for_each_encoder_on_crtc(dev, crtc, encoder)
633 if (encoder->type == type)
4ef69c7a
CW		 634 return true;
635
636 return false;
79e53945
JB		 637}
638
7c04d1d9 639#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 640/**
641 * Returns whether the given set of divisors are valid for a given refclk with
642 * the given connectors.
643 */
644
1b894b59
CW		 645static bool intel_PLL_is_valid(struct drm_device *dev,
646 const intel_limit_t *limit,
647 const intel_clock_t *clock)
79e53945 648{
79e53945 649 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 650 INTELPllInvalid("p1 out of range\n");
79e53945 651 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 652 INTELPllInvalid("p out of range\n");
79e53945 653 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 654 INTELPllInvalid("m2 out of range\n");
79e53945 655 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 656 INTELPllInvalid("m1 out of range\n");
f2b115e6 657 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 658 INTELPllInvalid("m1 <= m2\n");
79e53945 659 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 660 INTELPllInvalid("m out of range\n");
79e53945 661 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 662 INTELPllInvalid("n out of range\n");
79e53945 663 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 664 INTELPllInvalid("vco out of range\n");
79e53945
JB		 665 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
666 * connector, etc., rather than just a single range.
667 */
668 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 669 INTELPllInvalid("dot out of range\n");
79e53945
JB		 670
671 return true;
672}
673
d4906093
ML		 674static bool
675intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 676 int target, int refclk, intel_clock_t *match_clock,
677 intel_clock_t *best_clock)
d4906093 678
79e53945
JB		 679{
680 struct drm_device *dev = crtc->dev;
681 struct drm_i915_private *dev_priv = dev->dev_private;
682 intel_clock_t clock;
79e53945
JB		 683 int err = target;
684
bc5e5718 685 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 686 (I915_READ(LVDS)) != 0) {
79e53945
JB		 687 /*
688 * For LVDS, if the panel is on, just rely on its current
689 * settings for dual-channel. We haven't figured out how to
690 * reliably set up different single/dual channel state, if we
691 * even can.
692 */
b0354385 693 if (is_dual_link_lvds(dev_priv, LVDS))
79e53945
JB		 694 clock.p2 = limit->p2.p2_fast;
695 else
696 clock.p2 = limit->p2.p2_slow;
697 } else {
698 if (target < limit->p2.dot_limit)
699 clock.p2 = limit->p2.p2_slow;
700 else
701 clock.p2 = limit->p2.p2_fast;
702 }
703
0206e353 704 memset(best_clock, 0, sizeof(*best_clock));
79e53945 705
42158660
ZY		 706 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
707 clock.m1++) {
708 for (clock.m2 = limit->m2.min;
709 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 710 /* m1 is always 0 in Pineview */
711 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 712 break;
713 for (clock.n = limit->n.min;
714 clock.n <= limit->n.max; clock.n++) {
715 for (clock.p1 = limit->p1.min;
716 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 717 int this_err;
718
2177832f 719 intel_clock(dev, refclk, &clock);
1b894b59
CW		 720 if (!intel_PLL_is_valid(dev, limit,
721 &clock))
79e53945 722 continue;
cec2f356
SP		 723 if (match_clock &&
724 clock.p != match_clock->p)
725 continue;
79e53945
JB		 726
727 this_err = abs(clock.dot - target);
728 if (this_err < err) {
729 *best_clock = clock;
730 err = this_err;
731 }
732 }
733 }
734 }
735 }
736
737 return (err != target);
738}
739
d4906093
ML		 740static bool
741intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 742 int target, int refclk, intel_clock_t *match_clock,
743 intel_clock_t *best_clock)
d4906093
ML		 744{
745 struct drm_device *dev = crtc->dev;
746 struct drm_i915_private *dev_priv = dev->dev_private;
747 intel_clock_t clock;
748 int max_n;
749 bool found;
6ba770dc
AJ		 750 /* approximately equals target * 0.00585 */
751 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 752 found = false;
753
754 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 755 int lvds_reg;
756
c619eed4 757 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 758 lvds_reg = PCH_LVDS;
759 else
760 lvds_reg = LVDS;
761 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 762 LVDS_CLKB_POWER_UP)
763 clock.p2 = limit->p2.p2_fast;
764 else
765 clock.p2 = limit->p2.p2_slow;
766 } else {
767 if (target < limit->p2.dot_limit)
768 clock.p2 = limit->p2.p2_slow;
769 else
770 clock.p2 = limit->p2.p2_fast;
771 }
772
773 memset(best_clock, 0, sizeof(*best_clock));
774 max_n = limit->n.max;
f77f13e2 775 /* based on hardware requirement, prefer smaller n to precision */
d4906093 776 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 777 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 778 for (clock.m1 = limit->m1.max;
779 clock.m1 >= limit->m1.min; clock.m1--) {
780 for (clock.m2 = limit->m2.max;
781 clock.m2 >= limit->m2.min; clock.m2--) {
782 for (clock.p1 = limit->p1.max;
783 clock.p1 >= limit->p1.min; clock.p1--) {
784 int this_err;
785
2177832f 786 intel_clock(dev, refclk, &clock);
1b894b59
CW		 787 if (!intel_PLL_is_valid(dev, limit,
788 &clock))
d4906093 789 continue;
cec2f356
SP		 790 if (match_clock &&
791 clock.p != match_clock->p)
792 continue;
1b894b59
CW		 793
794 this_err = abs(clock.dot - target);
d4906093
ML		 795 if (this_err < err_most) {
796 *best_clock = clock;
797 err_most = this_err;
798 max_n = clock.n;
799 found = true;
800 }
801 }
802 }
803 }
804 }
2c07245f
ZW		 805 return found;
806}
807
5eb08b69 808static bool
f2b115e6 809intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 810 int target, int refclk, intel_clock_t *match_clock,
811 intel_clock_t *best_clock)
5eb08b69
ZW		 812{
813 struct drm_device *dev = crtc->dev;
814 intel_clock_t clock;
4547668a 815
5eb08b69
ZW		 816 if (target < 200000) {
817 clock.n = 1;
818 clock.p1 = 2;
819 clock.p2 = 10;
820 clock.m1 = 12;
821 clock.m2 = 9;
822 } else {
823 clock.n = 2;
824 clock.p1 = 1;
825 clock.p2 = 10;
826 clock.m1 = 14;
827 clock.m2 = 8;
828 }
829 intel_clock(dev, refclk, &clock);
830 memcpy(best_clock, &clock, sizeof(intel_clock_t));
831 return true;
832}
833
a4fc5ed6
KP		 834/* DisplayPort has only two frequencies, 162MHz and 270MHz */
835static bool
836intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
cec2f356
SP		 837 int target, int refclk, intel_clock_t *match_clock,
838 intel_clock_t *best_clock)
a4fc5ed6 839{
5eddb70b
CW		 840 intel_clock_t clock;
841 if (target < 200000) {
842 clock.p1 = 2;
843 clock.p2 = 10;
844 clock.n = 2;
845 clock.m1 = 23;
846 clock.m2 = 8;
847 } else {
848 clock.p1 = 1;
849 clock.p2 = 10;
850 clock.n = 1;
851 clock.m1 = 14;
852 clock.m2 = 2;
853 }
854 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
855 clock.p = (clock.p1 * clock.p2);
856 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
857 clock.vco = 0;
858 memcpy(best_clock, &clock, sizeof(intel_clock_t));
859 return true;
a4fc5ed6 860}
a0c4da24
JB		 861static bool
862intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
863 int target, int refclk, intel_clock_t *match_clock,
864 intel_clock_t *best_clock)
865{
866 u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
867 u32 m, n, fastclk;
868 u32 updrate, minupdate, fracbits, p;
869 unsigned long bestppm, ppm, absppm;
870 int dotclk, flag;
871
af447bd3 872 flag = 0;
a0c4da24
JB		 873 dotclk = target * 1000;
874 bestppm = 1000000;
875 ppm = absppm = 0;
876 fastclk = dotclk / (2*100);
877 updrate = 0;
878 minupdate = 19200;
879 fracbits = 1;
880 n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
881 bestm1 = bestm2 = bestp1 = bestp2 = 0;
882
883 /* based on hardware requirement, prefer smaller n to precision */
884 for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
885 updrate = refclk / n;
886 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
887 for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
888 if (p2 > 10)
889 p2 = p2 - 1;
890 p = p1 * p2;
891 /* based on hardware requirement, prefer bigger m1,m2 values */
892 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
893 m2 = (((2*(fastclk * p * n / m1 )) +
894 refclk) / (2*refclk));
895 m = m1 * m2;
896 vco = updrate * m;
897 if (vco >= limit->vco.min && vco < limit->vco.max) {
898 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
899 absppm = (ppm > 0) ? ppm : (-ppm);
900 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
901 bestppm = 0;
902 flag = 1;
903 }
904 if (absppm < bestppm - 10) {
905 bestppm = absppm;
906 flag = 1;
907 }
908 if (flag) {
909 bestn = n;
910 bestm1 = m1;
911 bestm2 = m2;
912 bestp1 = p1;
913 bestp2 = p2;
914 flag = 0;
915 }
916 }
917 }
918 }
919 }
920 }
921 best_clock->n = bestn;
922 best_clock->m1 = bestm1;
923 best_clock->m2 = bestm2;
924 best_clock->p1 = bestp1;
925 best_clock->p2 = bestp2;
926
927 return true;
928}
a4fc5ed6 929
a928d536
PZ		 930static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
931{
932 struct drm_i915_private *dev_priv = dev->dev_private;
933 u32 frame, frame_reg = PIPEFRAME(pipe);
934
935 frame = I915_READ(frame_reg);
936
937 if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
938 DRM_DEBUG_KMS("vblank wait timed out\n");
939}
940
9d0498a2
JB		 941/**
942 * intel_wait_for_vblank - wait for vblank on a given pipe
943 * @dev: drm device
944 * @pipe: pipe to wait for
945 *
946 * Wait for vblank to occur on a given pipe. Needed for various bits of
947 * mode setting code.
948 */
949void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 950{
9d0498a2 951 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 952 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 953
a928d536
PZ		 954 if (INTEL_INFO(dev)->gen >= 5) {
955 ironlake_wait_for_vblank(dev, pipe);
956 return;
957 }
958
300387c0
CW		 959 /* Clear existing vblank status. Note this will clear any other
960 * sticky status fields as well.
961 *
962 * This races with i915_driver_irq_handler() with the result
963 * that either function could miss a vblank event. Here it is not
964 * fatal, as we will either wait upon the next vblank interrupt or
965 * timeout. Generally speaking intel_wait_for_vblank() is only
966 * called during modeset at which time the GPU should be idle and
967 * should *not* be performing page flips and thus not waiting on
968 * vblanks...
969 * Currently, the result of us stealing a vblank from the irq
970 * handler is that a single frame will be skipped during swapbuffers.
971 */
972 I915_WRITE(pipestat_reg,
973 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
974
9d0498a2 975 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 976 if (wait_for(I915_READ(pipestat_reg) &
977 PIPE_VBLANK_INTERRUPT_STATUS,
978 50))
9d0498a2
JB		 979 DRM_DEBUG_KMS("vblank wait timed out\n");
980}
981
ab7ad7f6
KP		 982/*
983 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 984 * @dev: drm device
985 * @pipe: pipe to wait for
986 *
987 * After disabling a pipe, we can't wait for vblank in the usual way,
988 * spinning on the vblank interrupt status bit, since we won't actually
989 * see an interrupt when the pipe is disabled.
990 *
ab7ad7f6
KP		 991 * On Gen4 and above:
992 * wait for the pipe register state bit to turn off
993 *
994 * Otherwise:
995 * wait for the display line value to settle (it usually
996 * ends up stopping at the start of the next frame).
58e10eb9 997 *
9d0498a2 998 */
58e10eb9 999void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 1000{
1001 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 1002
1003 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 1004 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 1005
1006 /* Wait for the Pipe State to go off */
58e10eb9
CW		 1007 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
1008 100))
ab7ad7f6
KP		 1009 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1010 } else {
837ba00f 1011 u32 last_line, line_mask;
58e10eb9 1012 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 1013 unsigned long timeout = jiffies + msecs_to_jiffies(100);
1014
837ba00f
PZ		 1015 if (IS_GEN2(dev))
1016 line_mask = DSL_LINEMASK_GEN2;
1017 else
1018 line_mask = DSL_LINEMASK_GEN3;
1019
ab7ad7f6
KP		 1020 /* Wait for the display line to settle */
1021 do {
837ba00f 1022 last_line = I915_READ(reg) & line_mask;
ab7ad7f6 1023 mdelay(5);
837ba00f 1024 } while (((I915_READ(reg) & line_mask) != last_line) &&
ab7ad7f6
KP		 1025 time_after(timeout, jiffies));
1026 if (time_after(jiffies, timeout))
1027 DRM_DEBUG_KMS("pipe_off wait timed out\n");
1028 }
79e53945
JB		 1029}
1030
b24e7179
JB		 1031static const char *state_string(bool enabled)
1032{
1033 return enabled ? "on" : "off";
1034}
1035
1036/* Only for pre-ILK configs */
1037static void assert_pll(struct drm_i915_private *dev_priv,
1038 enum pipe pipe, bool state)
1039{
1040 int reg;
1041 u32 val;
1042 bool cur_state;
1043
1044 reg = DPLL(pipe);
1045 val = I915_READ(reg);
1046 cur_state = !!(val & DPLL_VCO_ENABLE);
1047 WARN(cur_state != state,
1048 "PLL state assertion failure (expected %s, current %s)\n",
1049 state_string(state), state_string(cur_state));
1050}
1051#define assert_pll_enabled(d, p) assert_pll(d, p, true)
1052#define assert_pll_disabled(d, p) assert_pll(d, p, false)
1053
040484af
JB		 1054/* For ILK+ */
1055static void assert_pch_pll(struct drm_i915_private *dev_priv,
92b27b08
CW		 1056 struct intel_pch_pll *pll,
1057 struct intel_crtc *crtc,
1058 bool state)
040484af 1059{
040484af
JB		 1060 u32 val;
1061 bool cur_state;
1062
9d82aa17
ED		 1063 if (HAS_PCH_LPT(dev_priv->dev)) {
1064 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1065 return;
1066 }
1067
92b27b08
CW		 1068 if (WARN (!pll,
1069 "asserting PCH PLL %s with no PLL\n", state_string(state)))
ee7b9f93 1070 return;
ee7b9f93 1071
92b27b08
CW		 1072 val = I915_READ(pll->pll_reg);
1073 cur_state = !!(val & DPLL_VCO_ENABLE);
1074 WARN(cur_state != state,
1075 "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1076 pll->pll_reg, state_string(state), state_string(cur_state), val);
1077
1078 /* Make sure the selected PLL is correctly attached to the transcoder */
1079 if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
d3ccbe86
JB		 1080 u32 pch_dpll;
1081
1082 pch_dpll = I915_READ(PCH_DPLL_SEL);
92b27b08
CW		 1083 cur_state = pll->pll_reg == _PCH_DPLL_B;
1084 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1085 "PLL[%d] not attached to this transcoder %d: %08x\n",
1086 cur_state, crtc->pipe, pch_dpll)) {
1087 cur_state = !!(val >> (4*crtc->pipe + 3));
1088 WARN(cur_state != state,
1089 "PLL[%d] not %s on this transcoder %d: %08x\n",
1090 pll->pll_reg == _PCH_DPLL_B,
1091 state_string(state),
1092 crtc->pipe,
1093 val);
1094 }
d3ccbe86 1095 }
040484af 1096}
92b27b08
CW		 1097#define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1098#define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
040484af
JB		 1099
1100static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1101 enum pipe pipe, bool state)
1102{
1103 int reg;
1104 u32 val;
1105 bool cur_state;
1106
bf507ef7
ED		 1107 if (IS_HASWELL(dev_priv->dev)) {
1108 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1109 reg = DDI_FUNC_CTL(pipe);
1110 val = I915_READ(reg);
1111 cur_state = !!(val & PIPE_DDI_FUNC_ENABLE);
1112 } else {
1113 reg = FDI_TX_CTL(pipe);
1114 val = I915_READ(reg);
1115 cur_state = !!(val & FDI_TX_ENABLE);
1116 }
040484af
JB		 1117 WARN(cur_state != state,
1118 "FDI TX state assertion failure (expected %s, current %s)\n",
1119 state_string(state), state_string(cur_state));
1120}
1121#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1122#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1123
1124static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1125 enum pipe pipe, bool state)
1126{
1127 int reg;
1128 u32 val;
1129 bool cur_state;
1130
59c859d6
ED		 1131 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1132 DRM_ERROR("Attempting to enable FDI_RX on Haswell pipe > 0\n");
1133 return;
1134 } else {
1135 reg = FDI_RX_CTL(pipe);
1136 val = I915_READ(reg);
1137 cur_state = !!(val & FDI_RX_ENABLE);
1138 }
040484af
JB		 1139 WARN(cur_state != state,
1140 "FDI RX state assertion failure (expected %s, current %s)\n",
1141 state_string(state), state_string(cur_state));
1142}
1143#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1144#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1145
1146static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1147 enum pipe pipe)
1148{
1149 int reg;
1150 u32 val;
1151
1152 /* ILK FDI PLL is always enabled */
1153 if (dev_priv->info->gen == 5)
1154 return;
1155
bf507ef7
ED		 1156 /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1157 if (IS_HASWELL(dev_priv->dev))
1158 return;
1159
040484af
JB		 1160 reg = FDI_TX_CTL(pipe);
1161 val = I915_READ(reg);
1162 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1163}
1164
1165static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1166 enum pipe pipe)
1167{
1168 int reg;
1169 u32 val;
1170
59c859d6
ED		 1171 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1172 DRM_ERROR("Attempting to enable FDI on Haswell with pipe > 0\n");
1173 return;
1174 }
040484af
JB		 1175 reg = FDI_RX_CTL(pipe);
1176 val = I915_READ(reg);
1177 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1178}
1179
ea0760cf
JB		 1180static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1181 enum pipe pipe)
1182{
1183 int pp_reg, lvds_reg;
1184 u32 val;
1185 enum pipe panel_pipe = PIPE_A;
0de3b485 1186 bool locked = true;
ea0760cf
JB		 1187
1188 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1189 pp_reg = PCH_PP_CONTROL;
1190 lvds_reg = PCH_LVDS;
1191 } else {
1192 pp_reg = PP_CONTROL;
1193 lvds_reg = LVDS;
1194 }
1195
1196 val = I915_READ(pp_reg);
1197 if (!(val & PANEL_POWER_ON) ||
1198 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1199 locked = false;
1200
1201 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1202 panel_pipe = PIPE_B;
1203
1204 WARN(panel_pipe == pipe && locked,
1205 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 1206 pipe_name(pipe));
ea0760cf
JB		 1207}
1208
b840d907
JB		 1209void assert_pipe(struct drm_i915_private *dev_priv,
1210 enum pipe pipe, bool state)
b24e7179
JB		 1211{
1212 int reg;
1213 u32 val;
63d7bbe9 1214 bool cur_state;
b24e7179 1215
8e636784
DV		 1216 /* if we need the pipe A quirk it must be always on */
1217 if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1218 state = true;
1219
b24e7179
JB		 1220 reg = PIPECONF(pipe);
1221 val = I915_READ(reg);
63d7bbe9
JB		 1222 cur_state = !!(val & PIPECONF_ENABLE);
1223 WARN(cur_state != state,
1224 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 1225 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 1226}
1227
931872fc
CW		 1228static void assert_plane(struct drm_i915_private *dev_priv,
1229 enum plane plane, bool state)
b24e7179
JB		 1230{
1231 int reg;
1232 u32 val;
931872fc 1233 bool cur_state;
b24e7179
JB		 1234
1235 reg = DSPCNTR(plane);
1236 val = I915_READ(reg);
931872fc
CW		 1237 cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1238 WARN(cur_state != state,
1239 "plane %c assertion failure (expected %s, current %s)\n",
1240 plane_name(plane), state_string(state), state_string(cur_state));
b24e7179
JB		 1241}
1242
931872fc
CW		 1243#define assert_plane_enabled(d, p) assert_plane(d, p, true)
1244#define assert_plane_disabled(d, p) assert_plane(d, p, false)
1245
b24e7179
JB		 1246static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1247 enum pipe pipe)
1248{
1249 int reg, i;
1250 u32 val;
1251 int cur_pipe;
1252
19ec1358 1253 /* Planes are fixed to pipes on ILK+ */
28c05794
AJ		 1254 if (HAS_PCH_SPLIT(dev_priv->dev)) {
1255 reg = DSPCNTR(pipe);
1256 val = I915_READ(reg);
1257 WARN((val & DISPLAY_PLANE_ENABLE),
1258 "plane %c assertion failure, should be disabled but not\n",
1259 plane_name(pipe));
19ec1358 1260 return;
28c05794 1261 }
19ec1358 1262
b24e7179
JB		 1263 /* Need to check both planes against the pipe */
1264 for (i = 0; i < 2; i++) {
1265 reg = DSPCNTR(i);
1266 val = I915_READ(reg);
1267 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1268 DISPPLANE_SEL_PIPE_SHIFT;
1269 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 1270 "plane %c assertion failure, should be off on pipe %c but is still active\n",
1271 plane_name(i), pipe_name(pipe));
b24e7179
JB		 1272 }
1273}
1274
92f2584a
JB		 1275static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1276{
1277 u32 val;
1278 bool enabled;
1279
9d82aa17
ED		 1280 if (HAS_PCH_LPT(dev_priv->dev)) {
1281 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1282 return;
1283 }
1284
92f2584a
JB		 1285 val = I915_READ(PCH_DREF_CONTROL);
1286 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1287 DREF_SUPERSPREAD_SOURCE_MASK));
1288 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1289}
1290
1291static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1292 enum pipe pipe)
1293{
1294 int reg;
1295 u32 val;
1296 bool enabled;
1297
1298 reg = TRANSCONF(pipe);
1299 val = I915_READ(reg);
1300 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 1301 WARN(enabled,
1302 "transcoder assertion failed, should be off on pipe %c but is still active\n",
1303 pipe_name(pipe));
92f2584a
JB		 1304}
1305
4e634389
KP		 1306static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1307 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 1308{
1309 if ((val & DP_PORT_EN) == 0)
1310 return false;
1311
1312 if (HAS_PCH_CPT(dev_priv->dev)) {
1313 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1314 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1315 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1316 return false;
1317 } else {
1318 if ((val & DP_PIPE_MASK) != (pipe << 30))
1319 return false;
1320 }
1321 return true;
1322}
1323
1519b995
KP		 1324static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1325 enum pipe pipe, u32 val)
1326{
1327 if ((val & PORT_ENABLE) == 0)
1328 return false;
1329
1330 if (HAS_PCH_CPT(dev_priv->dev)) {
1331 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1332 return false;
1333 } else {
1334 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1335 return false;
1336 }
1337 return true;
1338}
1339
1340static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1341 enum pipe pipe, u32 val)
1342{
1343 if ((val & LVDS_PORT_EN) == 0)
1344 return false;
1345
1346 if (HAS_PCH_CPT(dev_priv->dev)) {
1347 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1348 return false;
1349 } else {
1350 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1351 return false;
1352 }
1353 return true;
1354}
1355
1356static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1357 enum pipe pipe, u32 val)
1358{
1359 if ((val & ADPA_DAC_ENABLE) == 0)
1360 return false;
1361 if (HAS_PCH_CPT(dev_priv->dev)) {
1362 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1363 return false;
1364 } else {
1365 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1366 return false;
1367 }
1368 return true;
1369}
1370
291906f1 1371static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1372 enum pipe pipe, int reg, u32 port_sel)
291906f1 1373{
47a05eca 1374 u32 val = I915_READ(reg);
4e634389 1375 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1376 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1377 reg, pipe_name(pipe));
de9a35ab
DV		 1378
1379 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1380 "IBX PCH dp port still using transcoder B\n");
291906f1
JB		 1381}
1382
1383static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1384 enum pipe pipe, int reg)
1385{
47a05eca 1386 u32 val = I915_READ(reg);
e9a851ed 1387 WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
23c99e77 1388 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1389 reg, pipe_name(pipe));
de9a35ab
DV		 1390
1391 WARN(HAS_PCH_IBX(dev_priv->dev) && (val & SDVO_PIPE_B_SELECT),
1392 "IBX PCH hdmi port still using transcoder B\n");
291906f1
JB		 1393}
1394
1395static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1396 enum pipe pipe)
1397{
1398 int reg;
1399 u32 val;
291906f1 1400
f0575e92
KP		 1401 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1402 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1403 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1404
1405 reg = PCH_ADPA;
1406 val = I915_READ(reg);
e9a851ed 1407 WARN(adpa_pipe_enabled(dev_priv, pipe, val),
291906f1 1408 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1409 pipe_name(pipe));
291906f1
JB		 1410
1411 reg = PCH_LVDS;
1412 val = I915_READ(reg);
e9a851ed 1413 WARN(lvds_pipe_enabled(dev_priv, pipe, val),
291906f1 1414 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1415 pipe_name(pipe));
291906f1
JB		 1416
1417 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1418 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1419 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1420}
1421
63d7bbe9
JB		 1422/**
1423 * intel_enable_pll - enable a PLL
1424 * @dev_priv: i915 private structure
1425 * @pipe: pipe PLL to enable
1426 *
1427 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1428 * make sure the PLL reg is writable first though, since the panel write
1429 * protect mechanism may be enabled.
1430 *
1431 * Note! This is for pre-ILK only.
7434a255
TR		 1432 *
1433 * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
63d7bbe9 1434 */
a37b9b34 1435static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
63d7bbe9
JB		 1436{
1437 int reg;
1438 u32 val;
1439
1440 /* No really, not for ILK+ */
a0c4da24 1441 BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
63d7bbe9
JB		 1442
1443 /* PLL is protected by panel, make sure we can write it */
1444 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1445 assert_panel_unlocked(dev_priv, pipe);
1446
1447 reg = DPLL(pipe);
1448 val = I915_READ(reg);
1449 val |= DPLL_VCO_ENABLE;
1450
1451 /* We do this three times for luck */
1452 I915_WRITE(reg, val);
1453 POSTING_READ(reg);
1454 udelay(150); /* wait for warmup */
1455 I915_WRITE(reg, val);
1456 POSTING_READ(reg);
1457 udelay(150); /* wait for warmup */
1458 I915_WRITE(reg, val);
1459 POSTING_READ(reg);
1460 udelay(150); /* wait for warmup */
1461}
1462
1463/**
1464 * intel_disable_pll - disable a PLL
1465 * @dev_priv: i915 private structure
1466 * @pipe: pipe PLL to disable
1467 *
1468 * Disable the PLL for @pipe, making sure the pipe is off first.
1469 *
1470 * Note! This is for pre-ILK only.
1471 */
1472static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1473{
1474 int reg;
1475 u32 val;
1476
1477 /* Don't disable pipe A or pipe A PLLs if needed */
1478 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1479 return;
1480
1481 /* Make sure the pipe isn't still relying on us */
1482 assert_pipe_disabled(dev_priv, pipe);
1483
1484 reg = DPLL(pipe);
1485 val = I915_READ(reg);
1486 val &= ~DPLL_VCO_ENABLE;
1487 I915_WRITE(reg, val);
1488 POSTING_READ(reg);
1489}
1490
a416edef
ED		 1491/* SBI access */
1492static void
1493intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1494{
1495 unsigned long flags;
1496
1497 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1498 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1499 100)) {
1500 DRM_ERROR("timeout waiting for SBI to become ready\n");
1501 goto out_unlock;
1502 }
1503
1504 I915_WRITE(SBI_ADDR,
1505 (reg << 16));
1506 I915_WRITE(SBI_DATA,
1507 value);
1508 I915_WRITE(SBI_CTL_STAT,
1509 SBI_BUSY |
1510 SBI_CTL_OP_CRWR);
1511
39fb50f6 1512 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1513 100)) {
1514 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1515 goto out_unlock;
1516 }
1517
1518out_unlock:
1519 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1520}
1521
1522static u32
1523intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1524{
1525 unsigned long flags;
39fb50f6 1526 u32 value = 0;
a416edef
ED		 1527
1528 spin_lock_irqsave(&dev_priv->dpio_lock, flags);
39fb50f6 1529 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
a416edef
ED		 1530 100)) {
1531 DRM_ERROR("timeout waiting for SBI to become ready\n");
1532 goto out_unlock;
1533 }
1534
1535 I915_WRITE(SBI_ADDR,
1536 (reg << 16));
1537 I915_WRITE(SBI_CTL_STAT,
1538 SBI_BUSY |
1539 SBI_CTL_OP_CRRD);
1540
39fb50f6 1541 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
a416edef
ED		 1542 100)) {
1543 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1544 goto out_unlock;
1545 }
1546
1547 value = I915_READ(SBI_DATA);
1548
1549out_unlock:
1550 spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1551 return value;
1552}
1553
92f2584a
JB		 1554/**
1555 * intel_enable_pch_pll - enable PCH PLL
1556 * @dev_priv: i915 private structure
1557 * @pipe: pipe PLL to enable
1558 *
1559 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1560 * drives the transcoder clock.
1561 */
ee7b9f93 1562static void intel_enable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1563{
ee7b9f93 1564 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
48da64a8 1565 struct intel_pch_pll *pll;
92f2584a
JB		 1566 int reg;
1567 u32 val;
1568
48da64a8 1569 /* PCH PLLs only available on ILK, SNB and IVB */
92f2584a 1570 BUG_ON(dev_priv->info->gen < 5);
48da64a8
CW		 1571 pll = intel_crtc->pch_pll;
1572 if (pll == NULL)
1573 return;
1574
1575 if (WARN_ON(pll->refcount == 0))
1576 return;
ee7b9f93
JB		 1577
1578 DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1579 pll->pll_reg, pll->active, pll->on,
1580 intel_crtc->base.base.id);
92f2584a
JB		 1581
1582 /* PCH refclock must be enabled first */
1583 assert_pch_refclk_enabled(dev_priv);
1584
ee7b9f93 1585 if (pll->active++ && pll->on) {
92b27b08 1586 assert_pch_pll_enabled(dev_priv, pll, NULL);
ee7b9f93
JB		 1587 return;
1588 }
1589
1590 DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1591
1592 reg = pll->pll_reg;
92f2584a
JB		 1593 val = I915_READ(reg);
1594 val |= DPLL_VCO_ENABLE;
1595 I915_WRITE(reg, val);
1596 POSTING_READ(reg);
1597 udelay(200);
ee7b9f93
JB		 1598
1599 pll->on = true;
92f2584a
JB		 1600}
1601
ee7b9f93 1602static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
92f2584a 1603{
ee7b9f93
JB		 1604 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1605 struct intel_pch_pll *pll = intel_crtc->pch_pll;
92f2584a 1606 int reg;
ee7b9f93 1607 u32 val;
4c609cb8 1608
92f2584a
JB		 1609 /* PCH only available on ILK+ */
1610 BUG_ON(dev_priv->info->gen < 5);
ee7b9f93
JB		 1611 if (pll == NULL)
1612 return;
92f2584a 1613
48da64a8
CW		 1614 if (WARN_ON(pll->refcount == 0))
1615 return;
7a419866 1616
ee7b9f93
JB		 1617 DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1618 pll->pll_reg, pll->active, pll->on,
1619 intel_crtc->base.base.id);
7a419866 1620
48da64a8 1621 if (WARN_ON(pll->active == 0)) {
92b27b08 1622 assert_pch_pll_disabled(dev_priv, pll, NULL);
48da64a8
CW		 1623 return;
1624 }
1625
ee7b9f93 1626 if (--pll->active) {
92b27b08 1627 assert_pch_pll_enabled(dev_priv, pll, NULL);
7a419866 1628 return;
ee7b9f93
JB		 1629 }
1630
1631 DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1632
1633 /* Make sure transcoder isn't still depending on us */
1634 assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
7a419866 1635
ee7b9f93 1636 reg = pll->pll_reg;
92f2584a
JB		 1637 val = I915_READ(reg);
1638 val &= ~DPLL_VCO_ENABLE;
1639 I915_WRITE(reg, val);
1640 POSTING_READ(reg);
1641 udelay(200);
ee7b9f93
JB		 1642
1643 pll->on = false;
92f2584a
JB		 1644}
1645
040484af
JB		 1646static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1647 enum pipe pipe)
1648{
1649 int reg;
5f7f726d 1650 u32 val, pipeconf_val;
7c26e5c6 1651 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
040484af
JB		 1652
1653 /* PCH only available on ILK+ */
1654 BUG_ON(dev_priv->info->gen < 5);
1655
1656 /* Make sure PCH DPLL is enabled */
92b27b08
CW		 1657 assert_pch_pll_enabled(dev_priv,
1658 to_intel_crtc(crtc)->pch_pll,
1659 to_intel_crtc(crtc));
040484af
JB		 1660
1661 /* FDI must be feeding us bits for PCH ports */
1662 assert_fdi_tx_enabled(dev_priv, pipe);
1663 assert_fdi_rx_enabled(dev_priv, pipe);
1664
59c859d6
ED		 1665 if (IS_HASWELL(dev_priv->dev) && pipe > 0) {
1666 DRM_ERROR("Attempting to enable transcoder on Haswell with pipe > 0\n");
1667 return;
1668 }
040484af
JB		 1669 reg = TRANSCONF(pipe);
1670 val = I915_READ(reg);
5f7f726d 1671 pipeconf_val = I915_READ(PIPECONF(pipe));
e9bcff5c
JB		 1672
1673 if (HAS_PCH_IBX(dev_priv->dev)) {
1674 /*
1675 * make the BPC in transcoder be consistent with
1676 * that in pipeconf reg.
1677 */
1678 val &= ~PIPE_BPC_MASK;
5f7f726d 1679 val |= pipeconf_val & PIPE_BPC_MASK;
e9bcff5c 1680 }
5f7f726d
PZ		 1681
1682 val &= ~TRANS_INTERLACE_MASK;
1683 if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
7c26e5c6
PZ		 1684 if (HAS_PCH_IBX(dev_priv->dev) &&
1685 intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1686 val |= TRANS_LEGACY_INTERLACED_ILK;
1687 else
1688 val |= TRANS_INTERLACED;
5f7f726d
PZ		 1689 else
1690 val |= TRANS_PROGRESSIVE;
1691
040484af
JB		 1692 I915_WRITE(reg, val | TRANS_ENABLE);
1693 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1694 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1695}
1696
1697static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1698 enum pipe pipe)
1699{
1700 int reg;
1701 u32 val;
1702
1703 /* FDI relies on the transcoder */
1704 assert_fdi_tx_disabled(dev_priv, pipe);
1705 assert_fdi_rx_disabled(dev_priv, pipe);
1706
291906f1
JB		 1707 /* Ports must be off as well */
1708 assert_pch_ports_disabled(dev_priv, pipe);
1709
040484af
JB		 1710 reg = TRANSCONF(pipe);
1711 val = I915_READ(reg);
1712 val &= ~TRANS_ENABLE;
1713 I915_WRITE(reg, val);
1714 /* wait for PCH transcoder off, transcoder state */
1715 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1716 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1717}
1718
b24e7179 1719/**
309cfea8 1720 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1721 * @dev_priv: i915 private structure
1722 * @pipe: pipe to enable
040484af 1723 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1724 *
1725 * Enable @pipe, making sure that various hardware specific requirements
1726 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1727 *
1728 * @pipe should be %PIPE_A or %PIPE_B.
1729 *
1730 * Will wait until the pipe is actually running (i.e. first vblank) before
1731 * returning.
1732 */
040484af
JB		 1733static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1734 bool pch_port)
b24e7179
JB		 1735{
1736 int reg;
1737 u32 val;
1738
1739 /*
1740 * A pipe without a PLL won't actually be able to drive bits from
1741 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1742 * need the check.
1743 */
1744 if (!HAS_PCH_SPLIT(dev_priv->dev))
1745 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1746 else {
1747 if (pch_port) {
1748 /* if driving the PCH, we need FDI enabled */
1749 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1750 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1751 }
1752 /* FIXME: assert CPU port conditions for SNB+ */
1753 }
b24e7179
JB		 1754
1755 reg = PIPECONF(pipe);
1756 val = I915_READ(reg);
00d70b15
CW		 1757 if (val & PIPECONF_ENABLE)
1758 return;
1759
1760 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1761 intel_wait_for_vblank(dev_priv->dev, pipe);
1762}
1763
1764/**
309cfea8 1765 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1766 * @dev_priv: i915 private structure
1767 * @pipe: pipe to disable
1768 *
1769 * Disable @pipe, making sure that various hardware specific requirements
1770 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1771 *
1772 * @pipe should be %PIPE_A or %PIPE_B.
1773 *
1774 * Will wait until the pipe has shut down before returning.
1775 */
1776static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1777 enum pipe pipe)
1778{
1779 int reg;
1780 u32 val;
1781
1782 /*
1783 * Make sure planes won't keep trying to pump pixels to us,
1784 * or we might hang the display.
1785 */
1786 assert_planes_disabled(dev_priv, pipe);
1787
1788 /* Don't disable pipe A or pipe A PLLs if needed */
1789 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1790 return;
1791
1792 reg = PIPECONF(pipe);
1793 val = I915_READ(reg);
00d70b15
CW		 1794 if ((val & PIPECONF_ENABLE) == 0)
1795 return;
1796
1797 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1798 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1799}
1800
d74362c9
KP		 1801/*
1802 * Plane regs are double buffered, going from enabled->disabled needs a
1803 * trigger in order to latch. The display address reg provides this.
1804 */
6f1d69b0 1805void intel_flush_display_plane(struct drm_i915_private *dev_priv,
d74362c9
KP		 1806 enum plane plane)
1807{
1808 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1809 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1810}
1811
b24e7179
JB		 1812/**
1813 * intel_enable_plane - enable a display plane on a given pipe
1814 * @dev_priv: i915 private structure
1815 * @plane: plane to enable
1816 * @pipe: pipe being fed
1817 *
1818 * Enable @plane on @pipe, making sure that @pipe is running first.
1819 */
1820static void intel_enable_plane(struct drm_i915_private *dev_priv,
1821 enum plane plane, enum pipe pipe)
1822{
1823 int reg;
1824 u32 val;
1825
1826 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1827 assert_pipe_enabled(dev_priv, pipe);
1828
1829 reg = DSPCNTR(plane);
1830 val = I915_READ(reg);
00d70b15
CW		 1831 if (val & DISPLAY_PLANE_ENABLE)
1832 return;
1833
1834 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1835 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1836 intel_wait_for_vblank(dev_priv->dev, pipe);
1837}
1838
b24e7179
JB		 1839/**
1840 * intel_disable_plane - disable a display plane
1841 * @dev_priv: i915 private structure
1842 * @plane: plane to disable
1843 * @pipe: pipe consuming the data
1844 *
1845 * Disable @plane; should be an independent operation.
1846 */
1847static void intel_disable_plane(struct drm_i915_private *dev_priv,
1848 enum plane plane, enum pipe pipe)
1849{
1850 int reg;
1851 u32 val;
1852
1853 reg = DSPCNTR(plane);
1854 val = I915_READ(reg);
00d70b15
CW		 1855 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1856 return;
1857
1858 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1859 intel_flush_display_plane(dev_priv, plane);
1860 intel_wait_for_vblank(dev_priv->dev, pipe);
1861}
1862
47a05eca 1863static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1864 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1865{
1866 u32 val = I915_READ(reg);
4e634389 1867 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1868 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1869 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1870 }
47a05eca
JB		 1871}
1872
1873static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1874 enum pipe pipe, int reg)
1875{
1876 u32 val = I915_READ(reg);
e9a851ed 1877 if (hdmi_pipe_enabled(dev_priv, pipe, val)) {
f0575e92
KP		 1878 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1879 reg, pipe);
47a05eca 1880 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1881 }
47a05eca
JB		 1882}
1883
1884/* Disable any ports connected to this transcoder */
1885static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1886 enum pipe pipe)
1887{
1888 u32 reg, val;
1889
1890 val = I915_READ(PCH_PP_CONTROL);
1891 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1892
f0575e92
KP		 1893 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1894 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1895 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1896
1897 reg = PCH_ADPA;
1898 val = I915_READ(reg);
e9a851ed 1899 if (adpa_pipe_enabled(dev_priv, pipe, val))
47a05eca
JB		 1900 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1901
1902 reg = PCH_LVDS;
1903 val = I915_READ(reg);
e9a851ed 1904 if (lvds_pipe_enabled(dev_priv, pipe, val)) {
1519b995 1905 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1906 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1907 POSTING_READ(reg);
1908 udelay(100);
1909 }
1910
1911 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1912 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1913 disable_pch_hdmi(dev_priv, pipe, HDMID);
1914}
1915
127bd2ac 1916int
48b956c5 1917intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1918 struct drm_i915_gem_object *obj,
919926ae 1919 struct intel_ring_buffer *pipelined)
6b95a207 1920{
ce453d81 1921 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1922 u32 alignment;
1923 int ret;
1924
05394f39 1925 switch (obj->tiling_mode) {
6b95a207 1926 case I915_TILING_NONE:
534843da
CW		 1927 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1928 alignment = 128 * 1024;
a6c45cf0 1929 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1930 alignment = 4 * 1024;
1931 else
1932 alignment = 64 * 1024;
6b95a207
KH		 1933 break;
1934 case I915_TILING_X:
1935 /* pin() will align the object as required by fence */
1936 alignment = 0;
1937 break;
1938 case I915_TILING_Y:
1939 /* FIXME: Is this true? */
1940 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1941 return -EINVAL;
1942 default:
1943 BUG();
1944 }
1945
ce453d81 1946 dev_priv->mm.interruptible = false;
2da3b9b9 1947 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 1948 if (ret)
ce453d81 1949 goto err_interruptible;
6b95a207
KH		 1950
1951 /* Install a fence for tiled scan-out. Pre-i965 always needs a
1952 * fence, whereas 965+ only requires a fence if using
1953 * framebuffer compression. For simplicity, we always install
1954 * a fence as the cost is not that onerous.
1955 */
06d98131 1956 ret = i915_gem_object_get_fence(obj);
9a5a53b3
CW		 1957 if (ret)
1958 goto err_unpin;
1690e1eb 1959
9a5a53b3 1960 i915_gem_object_pin_fence(obj);
6b95a207 1961
ce453d81 1962 dev_priv->mm.interruptible = true;
6b95a207 1963 return 0;
48b956c5
CW		 1964
1965err_unpin:
1966 i915_gem_object_unpin(obj);
ce453d81
CW		 1967err_interruptible:
1968 dev_priv->mm.interruptible = true;
48b956c5 1969 return ret;
6b95a207
KH		 1970}
1971
1690e1eb
CW		 1972void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1973{
1974 i915_gem_object_unpin_fence(obj);
1975 i915_gem_object_unpin(obj);
1976}
1977
c2c75131
DV		 1978/* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1979 * is assumed to be a power-of-two. */
1980static unsigned long gen4_compute_dspaddr_offset_xtiled(int *x, int *y,
1981 unsigned int bpp,
1982 unsigned int pitch)
1983{
1984 int tile_rows, tiles;
1985
1986 tile_rows = *y / 8;
1987 *y %= 8;
1988 tiles = *x / (512/bpp);
1989 *x %= 512/bpp;
1990
1991 return tile_rows * pitch * 8 + tiles * 4096;
1992}
1993
17638cd6
JB		 1994static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1995 int x, int y)
81255565
JB		 1996{
1997 struct drm_device *dev = crtc->dev;
1998 struct drm_i915_private *dev_priv = dev->dev_private;
1999 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2000 struct intel_framebuffer *intel_fb;
05394f39 2001 struct drm_i915_gem_object *obj;
81255565 2002 int plane = intel_crtc->plane;
e506a0c6 2003 unsigned long linear_offset;
81255565 2004 u32 dspcntr;
5eddb70b 2005 u32 reg;
81255565
JB		 2006
2007 switch (plane) {
2008 case 0:
2009 case 1:
2010 break;
2011 default:
2012 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2013 return -EINVAL;
2014 }
2015
2016 intel_fb = to_intel_framebuffer(fb);
2017 obj = intel_fb->obj;
81255565 2018
5eddb70b
CW		 2019 reg = DSPCNTR(plane);
2020 dspcntr = I915_READ(reg);
81255565
JB		 2021 /* Mask out pixel format bits in case we change it */
2022 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2023 switch (fb->bits_per_pixel) {
2024 case 8:
2025 dspcntr |= DISPPLANE_8BPP;
2026 break;
2027 case 16:
2028 if (fb->depth == 15)
2029 dspcntr |= DISPPLANE_15_16BPP;
2030 else
2031 dspcntr |= DISPPLANE_16BPP;
2032 break;
2033 case 24:
2034 case 32:
2035 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2036 break;
2037 default:
17638cd6 2038 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2039 return -EINVAL;
2040 }
a6c45cf0 2041 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2042 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2043 dspcntr |= DISPPLANE_TILED;
2044 else
2045 dspcntr &= ~DISPPLANE_TILED;
2046 }
2047
5eddb70b 2048 I915_WRITE(reg, dspcntr);
81255565 2049
e506a0c6 2050 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2051
c2c75131
DV		 2052 if (INTEL_INFO(dev)->gen >= 4) {
2053 intel_crtc->dspaddr_offset =
2054 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2055 fb->bits_per_pixel / 8,
2056 fb->pitches[0]);
2057 linear_offset -= intel_crtc->dspaddr_offset;
2058 } else {
e506a0c6 2059 intel_crtc->dspaddr_offset = linear_offset;
c2c75131 2060 }
e506a0c6
DV		 2061
2062 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2063 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2064 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2065 if (INTEL_INFO(dev)->gen >= 4) {
c2c75131
DV		 2066 I915_MODIFY_DISPBASE(DSPSURF(plane),
2067 obj->gtt_offset + intel_crtc->dspaddr_offset);
5eddb70b 2068 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2069 I915_WRITE(DSPLINOFF(plane), linear_offset);
5eddb70b 2070 } else
e506a0c6 2071 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
5eddb70b 2072 POSTING_READ(reg);
81255565 2073
17638cd6
JB		 2074 return 0;
2075}
2076
2077static int ironlake_update_plane(struct drm_crtc *crtc,
2078 struct drm_framebuffer *fb, int x, int y)
2079{
2080 struct drm_device *dev = crtc->dev;
2081 struct drm_i915_private *dev_priv = dev->dev_private;
2082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2083 struct intel_framebuffer *intel_fb;
2084 struct drm_i915_gem_object *obj;
2085 int plane = intel_crtc->plane;
e506a0c6 2086 unsigned long linear_offset;
17638cd6
JB		 2087 u32 dspcntr;
2088 u32 reg;
2089
2090 switch (plane) {
2091 case 0:
2092 case 1:
27f8227b 2093 case 2:
17638cd6
JB		 2094 break;
2095 default:
2096 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2097 return -EINVAL;
2098 }
2099
2100 intel_fb = to_intel_framebuffer(fb);
2101 obj = intel_fb->obj;
2102
2103 reg = DSPCNTR(plane);
2104 dspcntr = I915_READ(reg);
2105 /* Mask out pixel format bits in case we change it */
2106 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2107 switch (fb->bits_per_pixel) {
2108 case 8:
2109 dspcntr |= DISPPLANE_8BPP;
2110 break;
2111 case 16:
2112 if (fb->depth != 16)
2113 return -EINVAL;
2114
2115 dspcntr |= DISPPLANE_16BPP;
2116 break;
2117 case 24:
2118 case 32:
2119 if (fb->depth == 24)
2120 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2121 else if (fb->depth == 30)
2122 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2123 else
2124 return -EINVAL;
2125 break;
2126 default:
2127 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2128 return -EINVAL;
2129 }
2130
2131 if (obj->tiling_mode != I915_TILING_NONE)
2132 dspcntr |= DISPPLANE_TILED;
2133 else
2134 dspcntr &= ~DISPPLANE_TILED;
2135
2136 /* must disable */
2137 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2138
2139 I915_WRITE(reg, dspcntr);
2140
e506a0c6 2141 linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
c2c75131
DV		 2142 intel_crtc->dspaddr_offset =
2143 gen4_compute_dspaddr_offset_xtiled(&x, &y,
2144 fb->bits_per_pixel / 8,
2145 fb->pitches[0]);
2146 linear_offset -= intel_crtc->dspaddr_offset;
17638cd6 2147
e506a0c6
DV		 2148 DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2149 obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
01f2c773 2150 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
c2c75131
DV		 2151 I915_MODIFY_DISPBASE(DSPSURF(plane),
2152 obj->gtt_offset + intel_crtc->dspaddr_offset);
17638cd6 2153 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
e506a0c6 2154 I915_WRITE(DSPLINOFF(plane), linear_offset);
17638cd6
JB		 2155 POSTING_READ(reg);
2156
2157 return 0;
2158}
2159
2160/* Assume fb object is pinned & idle & fenced and just update base pointers */
2161static int
2162intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2163 int x, int y, enum mode_set_atomic state)
2164{
2165 struct drm_device *dev = crtc->dev;
2166 struct drm_i915_private *dev_priv = dev->dev_private;
17638cd6 2167
6b8e6ed0
CW		 2168 if (dev_priv->display.disable_fbc)
2169 dev_priv->display.disable_fbc(dev);
3dec0095 2170 intel_increase_pllclock(crtc);
81255565 2171
6b8e6ed0 2172 return dev_priv->display.update_plane(crtc, fb, x, y);
81255565
JB		 2173}
2174
14667a4b
CW		 2175static int
2176intel_finish_fb(struct drm_framebuffer *old_fb)
2177{
2178 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2179 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2180 bool was_interruptible = dev_priv->mm.interruptible;
2181 int ret;
2182
2183 wait_event(dev_priv->pending_flip_queue,
2184 atomic_read(&dev_priv->mm.wedged) ||
2185 atomic_read(&obj->pending_flip) == 0);
2186
2187 /* Big Hammer, we also need to ensure that any pending
2188 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2189 * current scanout is retired before unpinning the old
2190 * framebuffer.
2191 *
2192 * This should only fail upon a hung GPU, in which case we
2193 * can safely continue.
2194 */
2195 dev_priv->mm.interruptible = false;
2196 ret = i915_gem_object_finish_gpu(obj);
2197 dev_priv->mm.interruptible = was_interruptible;
2198
2199 return ret;
2200}
2201
5c3b82e2 2202static int
3c4fdcfb 2203intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
94352cf9 2204 struct drm_framebuffer *fb)
79e53945
JB		 2205{
2206 struct drm_device *dev = crtc->dev;
6b8e6ed0 2207 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 2208 struct drm_i915_master_private *master_priv;
2209 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
94352cf9 2210 struct drm_framebuffer *old_fb;
5c3b82e2 2211 int ret;
79e53945
JB		 2212
2213 /* no fb bound */
94352cf9 2214 if (!fb) {
a5071c2f 2215 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2216 return 0;
2217 }
2218
5826eca5
ED		 2219 if(intel_crtc->plane > dev_priv->num_pipe) {
2220 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2221 intel_crtc->plane,
2222 dev_priv->num_pipe);
5c3b82e2 2223 return -EINVAL;
79e53945
JB		 2224 }
2225
5c3b82e2 2226 mutex_lock(&dev->struct_mutex);
265db958 2227 ret = intel_pin_and_fence_fb_obj(dev,
94352cf9 2228 to_intel_framebuffer(fb)->obj,
919926ae 2229 NULL);
5c3b82e2
CW		 2230 if (ret != 0) {
2231 mutex_unlock(&dev->struct_mutex);
a5071c2f 2232 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2233 return ret;
2234 }
79e53945 2235
94352cf9
DV		 2236 if (crtc->fb)
2237 intel_finish_fb(crtc->fb);
265db958 2238
94352cf9 2239 ret = dev_priv->display.update_plane(crtc, fb, x, y);
4e6cfefc 2240 if (ret) {
94352cf9 2241 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
5c3b82e2 2242 mutex_unlock(&dev->struct_mutex);
a5071c2f 2243 DRM_ERROR("failed to update base address\n");
4e6cfefc 2244 return ret;
79e53945 2245 }
3c4fdcfb 2246
94352cf9
DV		 2247 old_fb = crtc->fb;
2248 crtc->fb = fb;
2249
b7f1de28
CW		 2250 if (old_fb) {
2251 intel_wait_for_vblank(dev, intel_crtc->pipe);
1690e1eb 2252 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2253 }
652c393a 2254
6b8e6ed0 2255 intel_update_fbc(dev);
5c3b82e2 2256 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2257
2258 if (!dev->primary->master)
5c3b82e2 2259 return 0;
79e53945
JB		 2260
2261 master_priv = dev->primary->master->driver_priv;
2262 if (!master_priv->sarea_priv)
5c3b82e2 2263 return 0;
79e53945 2264
265db958 2265 if (intel_crtc->pipe) {
79e53945
JB		 2266 master_priv->sarea_priv->pipeB_x = x;
2267 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2268 } else {
2269 master_priv->sarea_priv->pipeA_x = x;
2270 master_priv->sarea_priv->pipeA_y = y;
79e53945 2271 }
5c3b82e2
CW		 2272
2273 return 0;
79e53945
JB		 2274}
2275
5eddb70b 2276static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2277{
2278 struct drm_device *dev = crtc->dev;
2279 struct drm_i915_private *dev_priv = dev->dev_private;
2280 u32 dpa_ctl;
2281
28c97730 2282 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2283 dpa_ctl = I915_READ(DP_A);
2284 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2285
2286 if (clock < 200000) {
2287 u32 temp;
2288 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2289 /* workaround for 160Mhz:
2290 1) program 0x4600c bits 15:0 = 0x8124
2291 2) program 0x46010 bit 0 = 1
2292 3) program 0x46034 bit 24 = 1
2293 4) program 0x64000 bit 14 = 1
2294 */
2295 temp = I915_READ(0x4600c);
2296 temp &= 0xffff0000;
2297 I915_WRITE(0x4600c, temp | 0x8124);
2298
2299 temp = I915_READ(0x46010);
2300 I915_WRITE(0x46010, temp | 1);
2301
2302 temp = I915_READ(0x46034);
2303 I915_WRITE(0x46034, temp | (1 << 24));
2304 } else {
2305 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2306 }
2307 I915_WRITE(DP_A, dpa_ctl);
2308
5eddb70b 2309 POSTING_READ(DP_A);
32f9d658
ZW		 2310 udelay(500);
2311}
2312
5e84e1a4
ZW		 2313static void intel_fdi_normal_train(struct drm_crtc *crtc)
2314{
2315 struct drm_device *dev = crtc->dev;
2316 struct drm_i915_private *dev_priv = dev->dev_private;
2317 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2318 int pipe = intel_crtc->pipe;
2319 u32 reg, temp;
2320
2321 /* enable normal train */
2322 reg = FDI_TX_CTL(pipe);
2323 temp = I915_READ(reg);
61e499bf 2324 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2325 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2326 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2327 } else {
2328 temp &= ~FDI_LINK_TRAIN_NONE;
2329 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2330 }
5e84e1a4
ZW		 2331 I915_WRITE(reg, temp);
2332
2333 reg = FDI_RX_CTL(pipe);
2334 temp = I915_READ(reg);
2335 if (HAS_PCH_CPT(dev)) {
2336 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2337 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2338 } else {
2339 temp &= ~FDI_LINK_TRAIN_NONE;
2340 temp |= FDI_LINK_TRAIN_NONE;
2341 }
2342 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2343
2344 /* wait one idle pattern time */
2345 POSTING_READ(reg);
2346 udelay(1000);
357555c0
JB		 2347
2348 /* IVB wants error correction enabled */
2349 if (IS_IVYBRIDGE(dev))
2350 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2351 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2352}
2353
291427f5
JB		 2354static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2355{
2356 struct drm_i915_private *dev_priv = dev->dev_private;
2357 u32 flags = I915_READ(SOUTH_CHICKEN1);
2358
2359 flags |= FDI_PHASE_SYNC_OVR(pipe);
2360 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2361 flags |= FDI_PHASE_SYNC_EN(pipe);
2362 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2363 POSTING_READ(SOUTH_CHICKEN1);
2364}
2365
8db9d77b
ZW		 2366/* The FDI link training functions for ILK/Ibexpeak. */
2367static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2368{
2369 struct drm_device *dev = crtc->dev;
2370 struct drm_i915_private *dev_priv = dev->dev_private;
2371 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2372 int pipe = intel_crtc->pipe;
0fc932b8 2373 int plane = intel_crtc->plane;
5eddb70b 2374 u32 reg, temp, tries;
8db9d77b 2375
0fc932b8
JB		 2376 /* FDI needs bits from pipe & plane first */
2377 assert_pipe_enabled(dev_priv, pipe);
2378 assert_plane_enabled(dev_priv, plane);
2379
e1a44743
AJ		 2380 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2381 for train result */
5eddb70b
CW		 2382 reg = FDI_RX_IMR(pipe);
2383 temp = I915_READ(reg);
e1a44743
AJ		 2384 temp &= ~FDI_RX_SYMBOL_LOCK;
2385 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2386 I915_WRITE(reg, temp);
2387 I915_READ(reg);
e1a44743
AJ		 2388 udelay(150);
2389
8db9d77b 2390 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2391 reg = FDI_TX_CTL(pipe);
2392 temp = I915_READ(reg);
77ffb597
AJ		 2393 temp &= ~(7 << 19);
2394 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2395 temp &= ~FDI_LINK_TRAIN_NONE;
2396 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2397 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2398
5eddb70b
CW		 2399 reg = FDI_RX_CTL(pipe);
2400 temp = I915_READ(reg);
8db9d77b
ZW		 2401 temp &= ~FDI_LINK_TRAIN_NONE;
2402 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2403 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2404
2405 POSTING_READ(reg);
8db9d77b
ZW		 2406 udelay(150);
2407
5b2adf89 2408 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2409 if (HAS_PCH_IBX(dev)) {
2410 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2411 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2412 FDI_RX_PHASE_SYNC_POINTER_EN);
2413 }
5b2adf89 2414
5eddb70b 2415 reg = FDI_RX_IIR(pipe);
e1a44743 2416 for (tries = 0; tries < 5; tries++) {
5eddb70b 2417 temp = I915_READ(reg);
8db9d77b
ZW		 2418 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2419
2420 if ((temp & FDI_RX_BIT_LOCK)) {
2421 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2422 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2423 break;
2424 }
8db9d77b 2425 }
e1a44743 2426 if (tries == 5)
5eddb70b 2427 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2428
2429 /* Train 2 */
5eddb70b
CW		 2430 reg = FDI_TX_CTL(pipe);
2431 temp = I915_READ(reg);
8db9d77b
ZW		 2432 temp &= ~FDI_LINK_TRAIN_NONE;
2433 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2434 I915_WRITE(reg, temp);
8db9d77b 2435
5eddb70b
CW		 2436 reg = FDI_RX_CTL(pipe);
2437 temp = I915_READ(reg);
8db9d77b
ZW		 2438 temp &= ~FDI_LINK_TRAIN_NONE;
2439 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2440 I915_WRITE(reg, temp);
8db9d77b 2441
5eddb70b
CW		 2442 POSTING_READ(reg);
2443 udelay(150);
8db9d77b 2444
5eddb70b 2445 reg = FDI_RX_IIR(pipe);
e1a44743 2446 for (tries = 0; tries < 5; tries++) {
5eddb70b 2447 temp = I915_READ(reg);
8db9d77b
ZW		 2448 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2449
2450 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2451 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2452 DRM_DEBUG_KMS("FDI train 2 done.\n");
2453 break;
2454 }
8db9d77b 2455 }
e1a44743 2456 if (tries == 5)
5eddb70b 2457 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2458
2459 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2460
8db9d77b
ZW		 2461}
2462
0206e353 2463static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2464 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2465 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2466 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2467 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2468};
2469
2470/* The FDI link training functions for SNB/Cougarpoint. */
2471static void gen6_fdi_link_train(struct drm_crtc *crtc)
2472{
2473 struct drm_device *dev = crtc->dev;
2474 struct drm_i915_private *dev_priv = dev->dev_private;
2475 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2476 int pipe = intel_crtc->pipe;
fa37d39e 2477 u32 reg, temp, i, retry;
8db9d77b 2478
e1a44743
AJ		 2479 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2480 for train result */
5eddb70b
CW		 2481 reg = FDI_RX_IMR(pipe);
2482 temp = I915_READ(reg);
e1a44743
AJ		 2483 temp &= ~FDI_RX_SYMBOL_LOCK;
2484 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2485 I915_WRITE(reg, temp);
2486
2487 POSTING_READ(reg);
e1a44743
AJ		 2488 udelay(150);
2489
8db9d77b 2490 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2491 reg = FDI_TX_CTL(pipe);
2492 temp = I915_READ(reg);
77ffb597
AJ		 2493 temp &= ~(7 << 19);
2494 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2495 temp &= ~FDI_LINK_TRAIN_NONE;
2496 temp |= FDI_LINK_TRAIN_PATTERN_1;
2497 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2498 /* SNB-B */
2499 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2500 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2501
5eddb70b
CW		 2502 reg = FDI_RX_CTL(pipe);
2503 temp = I915_READ(reg);
8db9d77b
ZW		 2504 if (HAS_PCH_CPT(dev)) {
2505 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2506 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2507 } else {
2508 temp &= ~FDI_LINK_TRAIN_NONE;
2509 temp |= FDI_LINK_TRAIN_PATTERN_1;
2510 }
5eddb70b
CW		 2511 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2512
2513 POSTING_READ(reg);
8db9d77b
ZW		 2514 udelay(150);
2515
291427f5
JB		 2516 if (HAS_PCH_CPT(dev))
2517 cpt_phase_pointer_enable(dev, pipe);
2518
0206e353 2519 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2520 reg = FDI_TX_CTL(pipe);
2521 temp = I915_READ(reg);
8db9d77b
ZW		 2522 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2523 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2524 I915_WRITE(reg, temp);
2525
2526 POSTING_READ(reg);
8db9d77b
ZW		 2527 udelay(500);
2528
fa37d39e
SP		 2529 for (retry = 0; retry < 5; retry++) {
2530 reg = FDI_RX_IIR(pipe);
2531 temp = I915_READ(reg);
2532 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2533 if (temp & FDI_RX_BIT_LOCK) {
2534 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2535 DRM_DEBUG_KMS("FDI train 1 done.\n");
2536 break;
2537 }
2538 udelay(50);
8db9d77b 2539 }
fa37d39e
SP		 2540 if (retry < 5)
2541 break;
8db9d77b
ZW		 2542 }
2543 if (i == 4)
5eddb70b 2544 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2545
2546 /* Train 2 */
5eddb70b
CW		 2547 reg = FDI_TX_CTL(pipe);
2548 temp = I915_READ(reg);
8db9d77b
ZW		 2549 temp &= ~FDI_LINK_TRAIN_NONE;
2550 temp |= FDI_LINK_TRAIN_PATTERN_2;
2551 if (IS_GEN6(dev)) {
2552 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2553 /* SNB-B */
2554 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2555 }
5eddb70b 2556 I915_WRITE(reg, temp);
8db9d77b 2557
5eddb70b
CW		 2558 reg = FDI_RX_CTL(pipe);
2559 temp = I915_READ(reg);
8db9d77b
ZW		 2560 if (HAS_PCH_CPT(dev)) {
2561 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2562 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2563 } else {
2564 temp &= ~FDI_LINK_TRAIN_NONE;
2565 temp |= FDI_LINK_TRAIN_PATTERN_2;
2566 }
5eddb70b
CW		 2567 I915_WRITE(reg, temp);
2568
2569 POSTING_READ(reg);
8db9d77b
ZW		 2570 udelay(150);
2571
0206e353 2572 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2573 reg = FDI_TX_CTL(pipe);
2574 temp = I915_READ(reg);
8db9d77b
ZW		 2575 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2576 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2577 I915_WRITE(reg, temp);
2578
2579 POSTING_READ(reg);
8db9d77b
ZW		 2580 udelay(500);
2581
fa37d39e
SP		 2582 for (retry = 0; retry < 5; retry++) {
2583 reg = FDI_RX_IIR(pipe);
2584 temp = I915_READ(reg);
2585 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2586 if (temp & FDI_RX_SYMBOL_LOCK) {
2587 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2588 DRM_DEBUG_KMS("FDI train 2 done.\n");
2589 break;
2590 }
2591 udelay(50);
8db9d77b 2592 }
fa37d39e
SP		 2593 if (retry < 5)
2594 break;
8db9d77b
ZW		 2595 }
2596 if (i == 4)
5eddb70b 2597 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2598
2599 DRM_DEBUG_KMS("FDI train done.\n");
2600}
2601
357555c0
JB		 2602/* Manual link training for Ivy Bridge A0 parts */
2603static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2604{
2605 struct drm_device *dev = crtc->dev;
2606 struct drm_i915_private *dev_priv = dev->dev_private;
2607 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2608 int pipe = intel_crtc->pipe;
2609 u32 reg, temp, i;
2610
2611 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2612 for train result */
2613 reg = FDI_RX_IMR(pipe);
2614 temp = I915_READ(reg);
2615 temp &= ~FDI_RX_SYMBOL_LOCK;
2616 temp &= ~FDI_RX_BIT_LOCK;
2617 I915_WRITE(reg, temp);
2618
2619 POSTING_READ(reg);
2620 udelay(150);
2621
2622 /* enable CPU FDI TX and PCH FDI RX */
2623 reg = FDI_TX_CTL(pipe);
2624 temp = I915_READ(reg);
2625 temp &= ~(7 << 19);
2626 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2627 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2628 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2629 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2630 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2631 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2632 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2633
2634 reg = FDI_RX_CTL(pipe);
2635 temp = I915_READ(reg);
2636 temp &= ~FDI_LINK_TRAIN_AUTO;
2637 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2638 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2639 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2640 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2641
2642 POSTING_READ(reg);
2643 udelay(150);
2644
291427f5
JB		 2645 if (HAS_PCH_CPT(dev))
2646 cpt_phase_pointer_enable(dev, pipe);
2647
0206e353 2648 for (i = 0; i < 4; i++) {
357555c0
JB		 2649 reg = FDI_TX_CTL(pipe);
2650 temp = I915_READ(reg);
2651 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2652 temp |= snb_b_fdi_train_param[i];
2653 I915_WRITE(reg, temp);
2654
2655 POSTING_READ(reg);
2656 udelay(500);
2657
2658 reg = FDI_RX_IIR(pipe);
2659 temp = I915_READ(reg);
2660 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2661
2662 if (temp & FDI_RX_BIT_LOCK ||
2663 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2664 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2665 DRM_DEBUG_KMS("FDI train 1 done.\n");
2666 break;
2667 }
2668 }
2669 if (i == 4)
2670 DRM_ERROR("FDI train 1 fail!\n");
2671
2672 /* Train 2 */
2673 reg = FDI_TX_CTL(pipe);
2674 temp = I915_READ(reg);
2675 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2676 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2677 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2678 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2679 I915_WRITE(reg, temp);
2680
2681 reg = FDI_RX_CTL(pipe);
2682 temp = I915_READ(reg);
2683 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2684 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2685 I915_WRITE(reg, temp);
2686
2687 POSTING_READ(reg);
2688 udelay(150);
2689
0206e353 2690 for (i = 0; i < 4; i++) {
357555c0
JB		 2691 reg = FDI_TX_CTL(pipe);
2692 temp = I915_READ(reg);
2693 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2694 temp |= snb_b_fdi_train_param[i];
2695 I915_WRITE(reg, temp);
2696
2697 POSTING_READ(reg);
2698 udelay(500);
2699
2700 reg = FDI_RX_IIR(pipe);
2701 temp = I915_READ(reg);
2702 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2703
2704 if (temp & FDI_RX_SYMBOL_LOCK) {
2705 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2706 DRM_DEBUG_KMS("FDI train 2 done.\n");
2707 break;
2708 }
2709 }
2710 if (i == 4)
2711 DRM_ERROR("FDI train 2 fail!\n");
2712
2713 DRM_DEBUG_KMS("FDI train done.\n");
2714}
2715
88cefb6c 2716static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2c07245f 2717{
88cefb6c 2718 struct drm_device *dev = intel_crtc->base.dev;
2c07245f 2719 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 2720 int pipe = intel_crtc->pipe;
5eddb70b 2721 u32 reg, temp;
79e53945 2722
c64e311e 2723 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2724 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2725 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2726
c98e9dcf 2727 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2728 reg = FDI_RX_CTL(pipe);
2729 temp = I915_READ(reg);
2730 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2731 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2732 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2733 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2734
2735 POSTING_READ(reg);
c98e9dcf
JB		 2736 udelay(200);
2737
2738 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2739 temp = I915_READ(reg);
2740 I915_WRITE(reg, temp | FDI_PCDCLK);
2741
2742 POSTING_READ(reg);
c98e9dcf
JB		 2743 udelay(200);
2744
bf507ef7
ED		 2745 /* On Haswell, the PLL configuration for ports and pipes is handled
2746 * separately, as part of DDI setup */
2747 if (!IS_HASWELL(dev)) {
2748 /* Enable CPU FDI TX PLL, always on for Ironlake */
2749 reg = FDI_TX_CTL(pipe);
2750 temp = I915_READ(reg);
2751 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2752 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
5eddb70b 2753
bf507ef7
ED		 2754 POSTING_READ(reg);
2755 udelay(100);
2756 }
6be4a607 2757 }
0e23b99d
JB		 2758}
2759
88cefb6c
DV		 2760static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2761{
2762 struct drm_device *dev = intel_crtc->base.dev;
2763 struct drm_i915_private *dev_priv = dev->dev_private;
2764 int pipe = intel_crtc->pipe;
2765 u32 reg, temp;
2766
2767 /* Switch from PCDclk to Rawclk */
2768 reg = FDI_RX_CTL(pipe);
2769 temp = I915_READ(reg);
2770 I915_WRITE(reg, temp & ~FDI_PCDCLK);
2771
2772 /* Disable CPU FDI TX PLL */
2773 reg = FDI_TX_CTL(pipe);
2774 temp = I915_READ(reg);
2775 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2776
2777 POSTING_READ(reg);
2778 udelay(100);
2779
2780 reg = FDI_RX_CTL(pipe);
2781 temp = I915_READ(reg);
2782 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2783
2784 /* Wait for the clocks to turn off. */
2785 POSTING_READ(reg);
2786 udelay(100);
2787}
2788
291427f5
JB		 2789static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2790{
2791 struct drm_i915_private *dev_priv = dev->dev_private;
2792 u32 flags = I915_READ(SOUTH_CHICKEN1);
2793
2794 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2795 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2796 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2797 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2798 POSTING_READ(SOUTH_CHICKEN1);
2799}
0fc932b8
JB		 2800static void ironlake_fdi_disable(struct drm_crtc *crtc)
2801{
2802 struct drm_device *dev = crtc->dev;
2803 struct drm_i915_private *dev_priv = dev->dev_private;
2804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2805 int pipe = intel_crtc->pipe;
2806 u32 reg, temp;
2807
2808 /* disable CPU FDI tx and PCH FDI rx */
2809 reg = FDI_TX_CTL(pipe);
2810 temp = I915_READ(reg);
2811 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2812 POSTING_READ(reg);
2813
2814 reg = FDI_RX_CTL(pipe);
2815 temp = I915_READ(reg);
2816 temp &= ~(0x7 << 16);
2817 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2818 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2819
2820 POSTING_READ(reg);
2821 udelay(100);
2822
2823 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2824 if (HAS_PCH_IBX(dev)) {
2825 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2826 I915_WRITE(FDI_RX_CHICKEN(pipe),
2827 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2828 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2829 } else if (HAS_PCH_CPT(dev)) {
2830 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2831 }
0fc932b8
JB		 2832
2833 /* still set train pattern 1 */
2834 reg = FDI_TX_CTL(pipe);
2835 temp = I915_READ(reg);
2836 temp &= ~FDI_LINK_TRAIN_NONE;
2837 temp |= FDI_LINK_TRAIN_PATTERN_1;
2838 I915_WRITE(reg, temp);
2839
2840 reg = FDI_RX_CTL(pipe);
2841 temp = I915_READ(reg);
2842 if (HAS_PCH_CPT(dev)) {
2843 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2844 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2845 } else {
2846 temp &= ~FDI_LINK_TRAIN_NONE;
2847 temp |= FDI_LINK_TRAIN_PATTERN_1;
2848 }
2849 /* BPC in FDI rx is consistent with that in PIPECONF */
2850 temp &= ~(0x07 << 16);
2851 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2852 I915_WRITE(reg, temp);
2853
2854 POSTING_READ(reg);
2855 udelay(100);
2856}
2857
e6c3a2a6
CW		 2858static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2859{
0f91128d 2860 struct drm_device *dev = crtc->dev;
e6c3a2a6
CW		 2861
2862 if (crtc->fb == NULL)
2863 return;
2864
0f91128d
CW		 2865 mutex_lock(&dev->struct_mutex);
2866 intel_finish_fb(crtc->fb);
2867 mutex_unlock(&dev->struct_mutex);
e6c3a2a6
CW		 2868}
2869
040484af
JB		 2870static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2871{
2872 struct drm_device *dev = crtc->dev;
228d3e36 2873 struct intel_encoder *intel_encoder;
040484af
JB		 2874
2875 /*
2876 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2877 * must be driven by its own crtc; no sharing is possible.
2878 */
228d3e36 2879 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
040484af 2880
6ee8bab0
ED		 2881 /* On Haswell, LPT PCH handles the VGA connection via FDI, and Haswell
2882 * CPU handles all others */
2883 if (IS_HASWELL(dev)) {
2884 /* It is still unclear how this will work on PPT, so throw up a warning */
2885 WARN_ON(!HAS_PCH_LPT(dev));
2886
228d3e36 2887 if (intel_encoder->type == INTEL_OUTPUT_ANALOG) {
6ee8bab0
ED		 2888 DRM_DEBUG_KMS("Haswell detected DAC encoder, assuming is PCH\n");
2889 return true;
2890 } else {
2891 DRM_DEBUG_KMS("Haswell detected encoder %d, assuming is CPU\n",
228d3e36 2892 intel_encoder->type);
6ee8bab0
ED		 2893 return false;
2894 }
2895 }
2896
228d3e36 2897 switch (intel_encoder->type) {
040484af 2898 case INTEL_OUTPUT_EDP:
228d3e36 2899 if (!intel_encoder_is_pch_edp(&intel_encoder->base))
040484af
JB		 2900 return false;
2901 continue;
2902 }
2903 }
2904
2905 return true;
2906}
2907
e615efe4
ED		 2908/* Program iCLKIP clock to the desired frequency */
2909static void lpt_program_iclkip(struct drm_crtc *crtc)
2910{
2911 struct drm_device *dev = crtc->dev;
2912 struct drm_i915_private *dev_priv = dev->dev_private;
2913 u32 divsel, phaseinc, auxdiv, phasedir = 0;
2914 u32 temp;
2915
2916 /* It is necessary to ungate the pixclk gate prior to programming
2917 * the divisors, and gate it back when it is done.
2918 */
2919 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2920
2921 /* Disable SSCCTL */
2922 intel_sbi_write(dev_priv, SBI_SSCCTL6,
2923 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2924 SBI_SSCCTL_DISABLE);
2925
2926 /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2927 if (crtc->mode.clock == 20000) {
2928 auxdiv = 1;
2929 divsel = 0x41;
2930 phaseinc = 0x20;
2931 } else {
2932 /* The iCLK virtual clock root frequency is in MHz,
2933 * but the crtc->mode.clock in in KHz. To get the divisors,
2934 * it is necessary to divide one by another, so we
2935 * convert the virtual clock precision to KHz here for higher
2936 * precision.
2937 */
2938 u32 iclk_virtual_root_freq = 172800 * 1000;
2939 u32 iclk_pi_range = 64;
2940 u32 desired_divisor, msb_divisor_value, pi_value;
2941
2942 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2943 msb_divisor_value = desired_divisor / iclk_pi_range;
2944 pi_value = desired_divisor % iclk_pi_range;
2945
2946 auxdiv = 0;
2947 divsel = msb_divisor_value - 2;
2948 phaseinc = pi_value;
2949 }
2950
2951 /* This should not happen with any sane values */
2952 WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
2953 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
2954 WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
2955 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
2956
2957 DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
2958 crtc->mode.clock,
2959 auxdiv,
2960 divsel,
2961 phasedir,
2962 phaseinc);
2963
2964 /* Program SSCDIVINTPHASE6 */
2965 temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
2966 temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
2967 temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
2968 temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
2969 temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
2970 temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
2971 temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
2972
2973 intel_sbi_write(dev_priv,
2974 SBI_SSCDIVINTPHASE6,
2975 temp);
2976
2977 /* Program SSCAUXDIV */
2978 temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
2979 temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
2980 temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
2981 intel_sbi_write(dev_priv,
2982 SBI_SSCAUXDIV6,
2983 temp);
2984
2985
2986 /* Enable modulator and associated divider */
2987 temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
2988 temp &= ~SBI_SSCCTL_DISABLE;
2989 intel_sbi_write(dev_priv,
2990 SBI_SSCCTL6,
2991 temp);
2992
2993 /* Wait for initialization time */
2994 udelay(24);
2995
2996 I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
2997}
2998
f67a559d
JB		 2999/*
3000 * Enable PCH resources required for PCH ports:
3001 * - PCH PLLs
3002 * - FDI training & RX/TX
3003 * - update transcoder timings
3004 * - DP transcoding bits
3005 * - transcoder
3006 */
3007static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 3008{
3009 struct drm_device *dev = crtc->dev;
3010 struct drm_i915_private *dev_priv = dev->dev_private;
3011 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3012 int pipe = intel_crtc->pipe;
ee7b9f93 3013 u32 reg, temp;
2c07245f 3014
e7e164db
CW		 3015 assert_transcoder_disabled(dev_priv, pipe);
3016
c98e9dcf 3017 /* For PCH output, training FDI link */
674cf967 3018 dev_priv->display.fdi_link_train(crtc);
2c07245f 3019
6f13b7b5
CW		 3020 intel_enable_pch_pll(intel_crtc);
3021
e615efe4
ED		 3022 if (HAS_PCH_LPT(dev)) {
3023 DRM_DEBUG_KMS("LPT detected: programming iCLKIP\n");
3024 lpt_program_iclkip(crtc);
3025 } else if (HAS_PCH_CPT(dev)) {
ee7b9f93 3026 u32 sel;
4b645f14 3027
c98e9dcf 3028 temp = I915_READ(PCH_DPLL_SEL);
ee7b9f93
JB		 3029 switch (pipe) {
3030 default:
3031 case 0:
3032 temp |= TRANSA_DPLL_ENABLE;
3033 sel = TRANSA_DPLLB_SEL;
3034 break;
3035 case 1:
3036 temp |= TRANSB_DPLL_ENABLE;
3037 sel = TRANSB_DPLLB_SEL;
3038 break;
3039 case 2:
3040 temp |= TRANSC_DPLL_ENABLE;
3041 sel = TRANSC_DPLLB_SEL;
3042 break;
d64311ab 3043 }
ee7b9f93
JB		 3044 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3045 temp |= sel;
3046 else
3047 temp &= ~sel;
c98e9dcf 3048 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 3049 }
5eddb70b 3050
d9b6cb56
JB		 3051 /* set transcoder timing, panel must allow it */
3052 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 3053 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3054 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3055 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 3056
5eddb70b
CW		 3057 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3058 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3059 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
0529a0d9 3060 I915_WRITE(TRANS_VSYNCSHIFT(pipe), I915_READ(VSYNCSHIFT(pipe)));
8db9d77b 3061
f57e1e3a
ED		 3062 if (!IS_HASWELL(dev))
3063 intel_fdi_normal_train(crtc);
5e84e1a4 3064
c98e9dcf
JB		 3065 /* For PCH DP, enable TRANS_DP_CTL */
3066 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 3067 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3068 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 3069 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 3070 reg = TRANS_DP_CTL(pipe);
3071 temp = I915_READ(reg);
3072 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 3073 TRANS_DP_SYNC_MASK |
3074 TRANS_DP_BPC_MASK);
5eddb70b
CW		 3075 temp |= (TRANS_DP_OUTPUT_ENABLE |
3076 TRANS_DP_ENH_FRAMING);
9325c9f0 3077 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 3078
3079 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 3080 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 3081 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 3082 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 3083
3084 switch (intel_trans_dp_port_sel(crtc)) {
3085 case PCH_DP_B:
5eddb70b 3086 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 3087 break;
3088 case PCH_DP_C:
5eddb70b 3089 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 3090 break;
3091 case PCH_DP_D:
5eddb70b 3092 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 3093 break;
3094 default:
3095 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 3096 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 3097 break;
32f9d658 3098 }
2c07245f 3099
5eddb70b 3100 I915_WRITE(reg, temp);
6be4a607 3101 }
b52eb4dc 3102
040484af 3103 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 3104}
3105
ee7b9f93
JB		 3106static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3107{
3108 struct intel_pch_pll *pll = intel_crtc->pch_pll;
3109
3110 if (pll == NULL)
3111 return;
3112
3113 if (pll->refcount == 0) {
3114 WARN(1, "bad PCH PLL refcount\n");
3115 return;
3116 }
3117
3118 --pll->refcount;
3119 intel_crtc->pch_pll = NULL;
3120}
3121
3122static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3123{
3124 struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3125 struct intel_pch_pll *pll;
3126 int i;
3127
3128 pll = intel_crtc->pch_pll;
3129 if (pll) {
3130 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3131 intel_crtc->base.base.id, pll->pll_reg);
3132 goto prepare;
3133 }
3134
98b6bd99
DV		 3135 if (HAS_PCH_IBX(dev_priv->dev)) {
3136 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3137 i = intel_crtc->pipe;
3138 pll = &dev_priv->pch_plls[i];
3139
3140 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3141 intel_crtc->base.base.id, pll->pll_reg);
3142
3143 goto found;
3144 }
3145
ee7b9f93
JB		 3146 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3147 pll = &dev_priv->pch_plls[i];
3148
3149 /* Only want to check enabled timings first */
3150 if (pll->refcount == 0)
3151 continue;
3152
3153 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3154 fp == I915_READ(pll->fp0_reg)) {
3155 DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3156 intel_crtc->base.base.id,
3157 pll->pll_reg, pll->refcount, pll->active);
3158
3159 goto found;
3160 }
3161 }
3162
3163 /* Ok no matching timings, maybe there's a free one? */
3164 for (i = 0; i < dev_priv->num_pch_pll; i++) {
3165 pll = &dev_priv->pch_plls[i];
3166 if (pll->refcount == 0) {
3167 DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3168 intel_crtc->base.base.id, pll->pll_reg);
3169 goto found;
3170 }
3171 }
3172
3173 return NULL;
3174
3175found:
3176 intel_crtc->pch_pll = pll;
3177 pll->refcount++;
3178 DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3179prepare: /* separate function? */
3180 DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
ee7b9f93 3181
e04c7350
CW		 3182 /* Wait for the clocks to stabilize before rewriting the regs */
3183 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3184 POSTING_READ(pll->pll_reg);
3185 udelay(150);
e04c7350
CW		 3186
3187 I915_WRITE(pll->fp0_reg, fp);
3188 I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
ee7b9f93
JB		 3189 pll->on = false;
3190 return pll;
3191}
3192
d4270e57
JB		 3193void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3194{
3195 struct drm_i915_private *dev_priv = dev->dev_private;
3196 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
3197 u32 temp;
3198
3199 temp = I915_READ(dslreg);
3200 udelay(500);
3201 if (wait_for(I915_READ(dslreg) != temp, 5)) {
3202 /* Without this, mode sets may fail silently on FDI */
3203 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
3204 udelay(250);
3205 I915_WRITE(tc2reg, 0);
3206 if (wait_for(I915_READ(dslreg) != temp, 5))
3207 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3208 }
3209}
3210
f67a559d
JB		 3211static void ironlake_crtc_enable(struct drm_crtc *crtc)
3212{
3213 struct drm_device *dev = crtc->dev;
3214 struct drm_i915_private *dev_priv = dev->dev_private;
3215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3216 struct intel_encoder *encoder;
f67a559d
JB		 3217 int pipe = intel_crtc->pipe;
3218 int plane = intel_crtc->plane;
3219 u32 temp;
3220 bool is_pch_port;
3221
08a48469
DV		 3222 WARN_ON(!crtc->enabled);
3223
ef9c3aee
DV		 3224 /* XXX: For compatability with the crtc helper code, call the encoder's
3225 * enable function unconditionally for now. */
f67a559d 3226 if (intel_crtc->active)
ef9c3aee 3227 goto encoders;
f67a559d
JB		 3228
3229 intel_crtc->active = true;
3230 intel_update_watermarks(dev);
3231
3232 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3233 temp = I915_READ(PCH_LVDS);
3234 if ((temp & LVDS_PORT_EN) == 0)
3235 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3236 }
3237
3238 is_pch_port = intel_crtc_driving_pch(crtc);
3239
3240 if (is_pch_port)
88cefb6c 3241 ironlake_fdi_pll_enable(intel_crtc);
f67a559d
JB		 3242 else
3243 ironlake_fdi_disable(crtc);
3244
3245 /* Enable panel fitting for LVDS */
3246 if (dev_priv->pch_pf_size &&
3247 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3248 /* Force use of hard-coded filter coefficients
3249 * as some pre-programmed values are broken,
3250 * e.g. x201.
3251 */
9db4a9c7
JB		 3252 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3253 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3254 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3255 }
3256
9c54c0dd
JB		 3257 /*
3258 * On ILK+ LUT must be loaded before the pipe is running but with
3259 * clocks enabled
3260 */
3261 intel_crtc_load_lut(crtc);
3262
f67a559d
JB		 3263 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3264 intel_enable_plane(dev_priv, plane, pipe);
3265
3266 if (is_pch_port)
3267 ironlake_pch_enable(crtc);
c98e9dcf 3268
d1ebd816 3269 mutex_lock(&dev->struct_mutex);
bed4a673 3270 intel_update_fbc(dev);
d1ebd816
BW		 3271 mutex_unlock(&dev->struct_mutex);
3272
6b383a7f 3273 intel_crtc_update_cursor(crtc, true);
ef9c3aee
DV		 3274
3275encoders:
fa5c73b1
DV		 3276 for_each_encoder_on_crtc(dev, crtc, encoder)
3277 encoder->enable(encoder);
61b77ddd
DV		 3278
3279 if (HAS_PCH_CPT(dev))
3280 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
6be4a607
JB		 3281}
3282
3283static void ironlake_crtc_disable(struct drm_crtc *crtc)
3284{
3285 struct drm_device *dev = crtc->dev;
3286 struct drm_i915_private *dev_priv = dev->dev_private;
3287 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3288 struct intel_encoder *encoder;
6be4a607
JB		 3289 int pipe = intel_crtc->pipe;
3290 int plane = intel_crtc->plane;
5eddb70b 3291 u32 reg, temp;
b52eb4dc 3292
ef9c3aee
DV		 3293 /* XXX: For compatability with the crtc helper code, call the encoder's
3294 * disable function unconditionally for now. */
fa5c73b1
DV		 3295 for_each_encoder_on_crtc(dev, crtc, encoder)
3296 encoder->disable(encoder);
ef9c3aee 3297
f7abfe8b
CW		 3298 if (!intel_crtc->active)
3299 return;
3300
e6c3a2a6 3301 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3302 drm_vblank_off(dev, pipe);
6b383a7f 3303 intel_crtc_update_cursor(crtc, false);
5eddb70b 3304
b24e7179 3305 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3306
973d04f9
CW		 3307 if (dev_priv->cfb_plane == plane)
3308 intel_disable_fbc(dev);
2c07245f 3309
b24e7179 3310 intel_disable_pipe(dev_priv, pipe);
32f9d658 3311
6be4a607 3312 /* Disable PF */
9db4a9c7
JB		 3313 I915_WRITE(PF_CTL(pipe), 0);
3314 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3315
0fc932b8 3316 ironlake_fdi_disable(crtc);
2c07245f 3317
47a05eca
JB		 3318 /* This is a horrible layering violation; we should be doing this in
3319 * the connector/encoder ->prepare instead, but we don't always have
3320 * enough information there about the config to know whether it will
3321 * actually be necessary or just cause undesired flicker.
3322 */
3323 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 3324
040484af 3325 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3326
6be4a607
JB		 3327 if (HAS_PCH_CPT(dev)) {
3328 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3329 reg = TRANS_DP_CTL(pipe);
3330 temp = I915_READ(reg);
3331 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3332 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3333 I915_WRITE(reg, temp);
6be4a607
JB		 3334
3335 /* disable DPLL_SEL */
3336 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3337 switch (pipe) {
3338 case 0:
d64311ab 3339 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3340 break;
3341 case 1:
6be4a607 3342 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3343 break;
3344 case 2:
4b645f14 3345 /* C shares PLL A or B */
d64311ab 3346 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3347 break;
3348 default:
3349 BUG(); /* wtf */
3350 }
6be4a607 3351 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3352 }
e3421a18 3353
6be4a607 3354 /* disable PCH DPLL */
ee7b9f93 3355 intel_disable_pch_pll(intel_crtc);
8db9d77b 3356
88cefb6c 3357 ironlake_fdi_pll_disable(intel_crtc);
6b383a7f 3358
f7abfe8b 3359 intel_crtc->active = false;
6b383a7f 3360 intel_update_watermarks(dev);
d1ebd816
BW		 3361
3362 mutex_lock(&dev->struct_mutex);
6b383a7f 3363 intel_update_fbc(dev);
d1ebd816 3364 mutex_unlock(&dev->struct_mutex);
6be4a607 3365}
1b3c7a47 3366
ee7b9f93
JB		 3367static void ironlake_crtc_off(struct drm_crtc *crtc)
3368{
3369 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3370 intel_put_pch_pll(intel_crtc);
3371}
3372
02e792fb
DV		 3373static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3374{
02e792fb 3375 if (!enable && intel_crtc->overlay) {
23f09ce3 3376 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3377 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3378
23f09ce3 3379 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3380 dev_priv->mm.interruptible = false;
3381 (void) intel_overlay_switch_off(intel_crtc->overlay);
3382 dev_priv->mm.interruptible = true;
23f09ce3 3383 mutex_unlock(&dev->struct_mutex);
02e792fb 3384 }
02e792fb 3385
5dcdbcb0
CW		 3386 /* Let userspace switch the overlay on again. In most cases userspace
3387 * has to recompute where to put it anyway.
3388 */
02e792fb
DV		 3389}
3390
0b8765c6 3391static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3392{
3393 struct drm_device *dev = crtc->dev;
79e53945
JB		 3394 struct drm_i915_private *dev_priv = dev->dev_private;
3395 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3396 struct intel_encoder *encoder;
79e53945 3397 int pipe = intel_crtc->pipe;
80824003 3398 int plane = intel_crtc->plane;
79e53945 3399
08a48469
DV		 3400 WARN_ON(!crtc->enabled);
3401
ef9c3aee
DV		 3402 /* XXX: For compatability with the crtc helper code, call the encoder's
3403 * enable function unconditionally for now. */
f7abfe8b 3404 if (intel_crtc->active)
ef9c3aee 3405 goto encoders;
f7abfe8b
CW		 3406
3407 intel_crtc->active = true;
6b383a7f
CW		 3408 intel_update_watermarks(dev);
3409
63d7bbe9 3410 intel_enable_pll(dev_priv, pipe);
040484af 3411 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3412 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3413
0b8765c6 3414 intel_crtc_load_lut(crtc);
bed4a673 3415 intel_update_fbc(dev);
79e53945 3416
0b8765c6
JB		 3417 /* Give the overlay scaler a chance to enable if it's on this pipe */
3418 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3419 intel_crtc_update_cursor(crtc, true);
ef9c3aee
DV		 3420
3421encoders:
fa5c73b1
DV		 3422 for_each_encoder_on_crtc(dev, crtc, encoder)
3423 encoder->enable(encoder);
0b8765c6 3424}
79e53945 3425
0b8765c6
JB		 3426static void i9xx_crtc_disable(struct drm_crtc *crtc)
3427{
3428 struct drm_device *dev = crtc->dev;
3429 struct drm_i915_private *dev_priv = dev->dev_private;
3430 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
ef9c3aee 3431 struct intel_encoder *encoder;
0b8765c6
JB		 3432 int pipe = intel_crtc->pipe;
3433 int plane = intel_crtc->plane;
b690e96c 3434
ef9c3aee
DV		 3435 /* XXX: For compatability with the crtc helper code, call the encoder's
3436 * disable function unconditionally for now. */
fa5c73b1
DV		 3437 for_each_encoder_on_crtc(dev, crtc, encoder)
3438 encoder->disable(encoder);
ef9c3aee 3439
f7abfe8b
CW		 3440 if (!intel_crtc->active)
3441 return;
3442
0b8765c6 3443 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3444 intel_crtc_wait_for_pending_flips(crtc);
3445 drm_vblank_off(dev, pipe);
0b8765c6 3446 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3447 intel_crtc_update_cursor(crtc, false);
0b8765c6 3448
973d04f9
CW		 3449 if (dev_priv->cfb_plane == plane)
3450 intel_disable_fbc(dev);
79e53945 3451
b24e7179 3452 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3453 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3454 intel_disable_pll(dev_priv, pipe);
0b8765c6 3455
f7abfe8b 3456 intel_crtc->active = false;
6b383a7f
CW		 3457 intel_update_fbc(dev);
3458 intel_update_watermarks(dev);
0b8765c6
JB		 3459}
3460
ee7b9f93
JB		 3461static void i9xx_crtc_off(struct drm_crtc *crtc)
3462{
3463}
3464
2c07245f
ZW		 3465/**
3466 * Sets the power management mode of the pipe and plane.
2c07245f 3467 */
b2cabb0e 3468void intel_crtc_update_dpms(struct drm_crtc *crtc)
2c07245f
ZW		 3469{
3470 struct drm_device *dev = crtc->dev;
e70236a8 3471 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3472 struct drm_i915_master_private *master_priv;
3473 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
b2cabb0e 3474 struct intel_encoder *intel_encoder;
2c07245f 3475 int pipe = intel_crtc->pipe;
b2cabb0e 3476 bool enabled, enable = false;
b2cabb0e
DV		 3477
3478 for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3479 enable |= intel_encoder->connectors_active;
3480
b2cabb0e 3481 if (enable)
76e5a89c 3482 dev_priv->display.crtc_enable(crtc);
b2cabb0e 3483 else
76e5a89c 3484 dev_priv->display.crtc_disable(crtc);
79e53945
JB		 3485
3486 if (!dev->primary->master)
3487 return;
3488
3489 master_priv = dev->primary->master->driver_priv;
3490 if (!master_priv->sarea_priv)
3491 return;
3492
b2cabb0e 3493 enabled = crtc->enabled && enable;
79e53945
JB		 3494
3495 switch (pipe) {
3496 case 0:
3497 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3498 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3499 break;
3500 case 1:
3501 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3502 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3503 break;
3504 default:
9db4a9c7 3505 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3506 break;
3507 }
79e53945
JB		 3508}
3509
cdd59983
CW		 3510static void intel_crtc_disable(struct drm_crtc *crtc)
3511{
cdd59983 3512 struct drm_device *dev = crtc->dev;
ee7b9f93 3513 struct drm_i915_private *dev_priv = dev->dev_private;
cdd59983 3514
b2cabb0e
DV		 3515 /* crtc->disable is only called when we have no encoders, hence this
3516 * will disable the pipe. */
3517 intel_crtc_update_dpms(crtc);
ee7b9f93
JB		 3518 dev_priv->display.off(crtc);
3519
931872fc
CW		 3520 assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3521 assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
cdd59983
CW		 3522
3523 if (crtc->fb) {
3524 mutex_lock(&dev->struct_mutex);
1690e1eb 3525 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
cdd59983
CW		 3526 mutex_unlock(&dev->struct_mutex);
3527 }
3528}
3529
5ab432ef
DV		 3530void intel_encoder_disable(struct drm_encoder *encoder)
3531{
3532 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3533
3534 intel_encoder->disable(intel_encoder);
3535}
3536
ea5b213a
CW		 3537void intel_encoder_destroy(struct drm_encoder *encoder)
3538{
4ef69c7a 3539 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3540
ea5b213a
CW		 3541 drm_encoder_cleanup(encoder);
3542 kfree(intel_encoder);
3543}
3544
5ab432ef
DV		 3545/* Simple dpms helper for encodres with just one connector, no cloning and only
3546 * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3547 * state of the entire output pipe. */
3548void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3549{
3550 if (mode == DRM_MODE_DPMS_ON) {
3551 encoder->connectors_active = true;
3552
b2cabb0e 3553 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3554 } else {
3555 encoder->connectors_active = false;
3556
b2cabb0e 3557 intel_crtc_update_dpms(encoder->base.crtc);
5ab432ef
DV		 3558 }
3559}
3560
0a91ca29
DV		 3561/* Cross check the actual hw state with our own modeset state tracking (and it's
3562 * internal consistency). */
3563void intel_connector_check_state(struct intel_connector *connector)
3564{
3565 if (connector->get_hw_state(connector)) {
3566 struct intel_encoder *encoder = connector->encoder;
3567 struct drm_crtc *crtc;
3568 bool encoder_enabled;
3569 enum pipe pipe;
3570
3571 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3572 connector->base.base.id,
3573 drm_get_connector_name(&connector->base));
3574
3575 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3576 "wrong connector dpms state\n");
3577 WARN(connector->base.encoder != &encoder->base,
3578 "active connector not linked to encoder\n");
3579 WARN(!encoder->connectors_active,
3580 "encoder->connectors_active not set\n");
3581
3582 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3583 WARN(!encoder_enabled, "encoder not enabled\n");
3584 if (WARN_ON(!encoder->base.crtc))
3585 return;
3586
3587 crtc = encoder->base.crtc;
3588
3589 WARN(!crtc->enabled, "crtc not enabled\n");
3590 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3591 WARN(pipe != to_intel_crtc(crtc)->pipe,
3592 "encoder active on the wrong pipe\n");
3593 }
3594}
3595
5ab432ef
DV		 3596/* Even simpler default implementation, if there's really no special case to
3597 * consider. */
3598void intel_connector_dpms(struct drm_connector *connector, int mode)
3599{
3600 struct intel_encoder *encoder = intel_attached_encoder(connector);
3601
3602 /* All the simple cases only support two dpms states. */
3603 if (mode != DRM_MODE_DPMS_ON)
3604 mode = DRM_MODE_DPMS_OFF;
3605
3606 if (mode == connector->dpms)
3607 return;
3608
3609 connector->dpms = mode;
3610
3611 /* Only need to change hw state when actually enabled */
3612 if (encoder->base.crtc)
3613 intel_encoder_dpms(encoder, mode);
3614 else
3615 encoder->connectors_active = false;
0a91ca29
DV		 3616
3617 intel_connector_check_state(to_intel_connector(connector));
5ab432ef
DV		 3618}
3619
f0947c37
DV		 3620/* Simple connector->get_hw_state implementation for encoders that support only
3621 * one connector and no cloning and hence the encoder state determines the state
3622 * of the connector. */
3623bool intel_connector_get_hw_state(struct intel_connector *connector)
3624{
24929352 3625 enum pipe pipe = 0;
f0947c37
DV		 3626 struct intel_encoder *encoder = connector->encoder;
3627
3628 return encoder->get_hw_state(encoder, &pipe);
3629}
3630
79e53945 3631static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
35313cde 3632 const struct drm_display_mode *mode,
79e53945
JB		 3633 struct drm_display_mode *adjusted_mode)
3634{
2c07245f 3635 struct drm_device *dev = crtc->dev;
89749350 3636
bad720ff 3637 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3638 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3639 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3640 return false;
2c07245f 3641 }
89749350 3642
f9bef081
DV		 3643 /* All interlaced capable intel hw wants timings in frames. Note though
3644 * that intel_lvds_mode_fixup does some funny tricks with the crtc
3645 * timings, so we need to be careful not to clobber these.*/
3646 if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3647 drm_mode_set_crtcinfo(adjusted_mode, 0);
89749350 3648
79e53945
JB		 3649 return true;
3650}
3651
25eb05fc
JB		 3652static int valleyview_get_display_clock_speed(struct drm_device *dev)
3653{
3654 return 400000; /* FIXME */
3655}
3656
e70236a8
JB		 3657static int i945_get_display_clock_speed(struct drm_device *dev)
3658{
3659 return 400000;
3660}
79e53945 3661
e70236a8 3662static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3663{
e70236a8
JB		 3664 return 333000;
3665}
79e53945 3666
e70236a8
JB		 3667static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3668{
3669 return 200000;
3670}
79e53945 3671
e70236a8
JB		 3672static int i915gm_get_display_clock_speed(struct drm_device *dev)
3673{
3674 u16 gcfgc = 0;
79e53945 3675
e70236a8
JB		 3676 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3677
3678 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3679 return 133000;
3680 else {
3681 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3682 case GC_DISPLAY_CLOCK_333_MHZ:
3683 return 333000;
3684 default:
3685 case GC_DISPLAY_CLOCK_190_200_MHZ:
3686 return 190000;
79e53945 3687 }
e70236a8
JB		 3688 }
3689}
3690
3691static int i865_get_display_clock_speed(struct drm_device *dev)
3692{
3693 return 266000;
3694}
3695
3696static int i855_get_display_clock_speed(struct drm_device *dev)
3697{
3698 u16 hpllcc = 0;
3699 /* Assume that the hardware is in the high speed state. This
3700 * should be the default.
3701 */
3702 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3703 case GC_CLOCK_133_200:
3704 case GC_CLOCK_100_200:
3705 return 200000;
3706 case GC_CLOCK_166_250:
3707 return 250000;
3708 case GC_CLOCK_100_133:
79e53945 3709 return 133000;
e70236a8 3710 }
79e53945 3711
e70236a8
JB		 3712 /* Shouldn't happen */
3713 return 0;
3714}
79e53945 3715
e70236a8
JB		 3716static int i830_get_display_clock_speed(struct drm_device *dev)
3717{
3718 return 133000;
79e53945
JB		 3719}
3720
2c07245f
ZW		 3721struct fdi_m_n {
3722 u32 tu;
3723 u32 gmch_m;
3724 u32 gmch_n;
3725 u32 link_m;
3726 u32 link_n;
3727};
3728
3729static void
3730fdi_reduce_ratio(u32 *num, u32 *den)
3731{
3732 while (*num > 0xffffff || *den > 0xffffff) {
3733 *num >>= 1;
3734 *den >>= 1;
3735 }
3736}
3737
2c07245f 3738static void
f2b115e6
AJ		 3739ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3740 int link_clock, struct fdi_m_n *m_n)
2c07245f 3741{
2c07245f
ZW		 3742 m_n->tu = 64; /* default size */
3743
22ed1113
CW		 3744 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3745 m_n->gmch_m = bits_per_pixel * pixel_clock;
3746 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3747 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3748
22ed1113
CW		 3749 m_n->link_m = pixel_clock;
3750 m_n->link_n = link_clock;
2c07245f
ZW		 3751 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3752}
3753
a7615030
CW		 3754static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
3755{
72bbe58c
KP		 3756 if (i915_panel_use_ssc >= 0)
3757 return i915_panel_use_ssc != 0;
3758 return dev_priv->lvds_use_ssc
435793df 3759 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 3760}
3761
5a354204
JB		 3762/**
3763 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
3764 * @crtc: CRTC structure
3b5c78a3 3765 * @mode: requested mode
5a354204
JB		 3766 *
3767 * A pipe may be connected to one or more outputs. Based on the depth of the
3768 * attached framebuffer, choose a good color depth to use on the pipe.
3769 *
3770 * If possible, match the pipe depth to the fb depth. In some cases, this
3771 * isn't ideal, because the connected output supports a lesser or restricted
3772 * set of depths. Resolve that here:
3773 * LVDS typically supports only 6bpc, so clamp down in that case
3774 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
3775 * Displays may support a restricted set as well, check EDID and clamp as
3776 * appropriate.
3b5c78a3 3777 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 3778 *
3779 * RETURNS:
3780 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
3781 * true if they don't match).
3782 */
3783static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
94352cf9 3784 struct drm_framebuffer *fb,
3b5c78a3
AJ		 3785 unsigned int *pipe_bpp,
3786 struct drm_display_mode *mode)
5a354204
JB		 3787{
3788 struct drm_device *dev = crtc->dev;
3789 struct drm_i915_private *dev_priv = dev->dev_private;
5a354204 3790 struct drm_connector *connector;
6c2b7c12 3791 struct intel_encoder *intel_encoder;
5a354204
JB		 3792 unsigned int display_bpc = UINT_MAX, bpc;
3793
3794 /* Walk the encoders & connectors on this crtc, get min bpc */
6c2b7c12 3795 for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5a354204
JB		 3796
3797 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
3798 unsigned int lvds_bpc;
3799
3800 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
3801 LVDS_A3_POWER_UP)
3802 lvds_bpc = 8;
3803 else
3804 lvds_bpc = 6;
3805
3806 if (lvds_bpc < display_bpc) {
82820490 3807 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 3808 display_bpc = lvds_bpc;
3809 }
3810 continue;
3811 }
3812
5a354204
JB		 3813 /* Not one of the known troublemakers, check the EDID */
3814 list_for_each_entry(connector, &dev->mode_config.connector_list,
3815 head) {
6c2b7c12 3816 if (connector->encoder != &intel_encoder->base)
5a354204
JB		 3817 continue;
3818
62ac41a6
JB		 3819 /* Don't use an invalid EDID bpc value */
3820 if (connector->display_info.bpc &&
3821 connector->display_info.bpc < display_bpc) {
82820490 3822 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 3823 display_bpc = connector->display_info.bpc;
3824 }
3825 }
3826
3827 /*
3828 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
3829 * through, clamp it down. (Note: >12bpc will be caught below.)
3830 */
3831 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
3832 if (display_bpc > 8 && display_bpc < 12) {
82820490 3833 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 3834 display_bpc = 12;
3835 } else {
82820490 3836 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 3837 display_bpc = 8;
3838 }
3839 }
3840 }
3841
3b5c78a3
AJ		 3842 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
3843 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
3844 display_bpc = 6;
3845 }
3846
5a354204
JB		 3847 /*
3848 * We could just drive the pipe at the highest bpc all the time and
3849 * enable dithering as needed, but that costs bandwidth. So choose
3850 * the minimum value that expresses the full color range of the fb but
3851 * also stays within the max display bpc discovered above.
3852 */
3853
94352cf9 3854 switch (fb->depth) {
5a354204
JB		 3855 case 8:
3856 bpc = 8; /* since we go through a colormap */
3857 break;
3858 case 15:
3859 case 16:
3860 bpc = 6; /* min is 18bpp */
3861 break;
3862 case 24:
578393cd 3863 bpc = 8;
5a354204
JB		 3864 break;
3865 case 30:
578393cd 3866 bpc = 10;
5a354204
JB		 3867 break;
3868 case 48:
578393cd 3869 bpc = 12;
5a354204
JB		 3870 break;
3871 default:
3872 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
3873 bpc = min((unsigned int)8, display_bpc);
3874 break;
3875 }
3876
578393cd
KP		 3877 display_bpc = min(display_bpc, bpc);
3878
82820490
AJ		 3879 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
3880 bpc, display_bpc);
5a354204 3881
578393cd 3882 *pipe_bpp = display_bpc * 3;
5a354204
JB		 3883
3884 return display_bpc != bpc;
3885}
3886
a0c4da24
JB		 3887static int vlv_get_refclk(struct drm_crtc *crtc)
3888{
3889 struct drm_device *dev = crtc->dev;
3890 struct drm_i915_private *dev_priv = dev->dev_private;
3891 int refclk = 27000; /* for DP & HDMI */
3892
3893 return 100000; /* only one validated so far */
3894
3895 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
3896 refclk = 96000;
3897 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3898 if (intel_panel_use_ssc(dev_priv))
3899 refclk = 100000;
3900 else
3901 refclk = 96000;
3902 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3903 refclk = 100000;
3904 }
3905
3906 return refclk;
3907}
3908
c65d77d8
JB		 3909static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
3910{
3911 struct drm_device *dev = crtc->dev;
3912 struct drm_i915_private *dev_priv = dev->dev_private;
3913 int refclk;
3914
a0c4da24
JB		 3915 if (IS_VALLEYVIEW(dev)) {
3916 refclk = vlv_get_refclk(crtc);
3917 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
c65d77d8
JB		 3918 intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
3919 refclk = dev_priv->lvds_ssc_freq * 1000;
3920 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3921 refclk / 1000);
3922 } else if (!IS_GEN2(dev)) {
3923 refclk = 96000;
3924 } else {
3925 refclk = 48000;
3926 }
3927
3928 return refclk;
3929}
3930
3931static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
3932 intel_clock_t *clock)
3933{
3934 /* SDVO TV has fixed PLL values depend on its clock range,
3935 this mirrors vbios setting. */
3936 if (adjusted_mode->clock >= 100000
3937 && adjusted_mode->clock < 140500) {
3938 clock->p1 = 2;
3939 clock->p2 = 10;
3940 clock->n = 3;
3941 clock->m1 = 16;
3942 clock->m2 = 8;
3943 } else if (adjusted_mode->clock >= 140500
3944 && adjusted_mode->clock <= 200000) {
3945 clock->p1 = 1;
3946 clock->p2 = 10;
3947 clock->n = 6;
3948 clock->m1 = 12;
3949 clock->m2 = 8;
3950 }
3951}
3952
a7516a05
JB		 3953static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
3954 intel_clock_t *clock,
3955 intel_clock_t *reduced_clock)
3956{
3957 struct drm_device *dev = crtc->dev;
3958 struct drm_i915_private *dev_priv = dev->dev_private;
3959 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3960 int pipe = intel_crtc->pipe;
3961 u32 fp, fp2 = 0;
3962
3963 if (IS_PINEVIEW(dev)) {
3964 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
3965 if (reduced_clock)
3966 fp2 = (1 << reduced_clock->n) << 16 |
3967 reduced_clock->m1 << 8 | reduced_clock->m2;
3968 } else {
3969 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
3970 if (reduced_clock)
3971 fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
3972 reduced_clock->m2;
3973 }
3974
3975 I915_WRITE(FP0(pipe), fp);
3976
3977 intel_crtc->lowfreq_avail = false;
3978 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
3979 reduced_clock && i915_powersave) {
3980 I915_WRITE(FP1(pipe), fp2);
3981 intel_crtc->lowfreq_avail = true;
3982 } else {
3983 I915_WRITE(FP1(pipe), fp);
3984 }
3985}
3986
93e537a1
DV		 3987static void intel_update_lvds(struct drm_crtc *crtc, intel_clock_t *clock,
3988 struct drm_display_mode *adjusted_mode)
3989{
3990 struct drm_device *dev = crtc->dev;
3991 struct drm_i915_private *dev_priv = dev->dev_private;
3992 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3993 int pipe = intel_crtc->pipe;
284d5df5 3994 u32 temp;
93e537a1
DV		 3995
3996 temp = I915_READ(LVDS);
3997 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3998 if (pipe == 1) {
3999 temp |= LVDS_PIPEB_SELECT;
4000 } else {
4001 temp &= ~LVDS_PIPEB_SELECT;
4002 }
4003 /* set the corresponsding LVDS_BORDER bit */
4004 temp |= dev_priv->lvds_border_bits;
4005 /* Set the B0-B3 data pairs corresponding to whether we're going to
4006 * set the DPLLs for dual-channel mode or not.
4007 */
4008 if (clock->p2 == 7)
4009 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
4010 else
4011 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
4012
4013 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4014 * appropriately here, but we need to look more thoroughly into how
4015 * panels behave in the two modes.
4016 */
4017 /* set the dithering flag on LVDS as needed */
4018 if (INTEL_INFO(dev)->gen >= 4) {
4019 if (dev_priv->lvds_dither)
4020 temp |= LVDS_ENABLE_DITHER;
4021 else
4022 temp &= ~LVDS_ENABLE_DITHER;
4023 }
284d5df5 4024 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
93e537a1 4025 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4026 temp |= LVDS_HSYNC_POLARITY;
93e537a1 4027 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4028 temp |= LVDS_VSYNC_POLARITY;
93e537a1
DV		 4029 I915_WRITE(LVDS, temp);
4030}
4031
a0c4da24
JB		 4032static void vlv_update_pll(struct drm_crtc *crtc,
4033 struct drm_display_mode *mode,
4034 struct drm_display_mode *adjusted_mode,
4035 intel_clock_t *clock, intel_clock_t *reduced_clock,
4036 int refclk, int num_connectors)
4037{
4038 struct drm_device *dev = crtc->dev;
4039 struct drm_i915_private *dev_priv = dev->dev_private;
4040 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4041 int pipe = intel_crtc->pipe;
4042 u32 dpll, mdiv, pdiv;
4043 u32 bestn, bestm1, bestm2, bestp1, bestp2;
4044 bool is_hdmi;
4045
4046 is_hdmi = intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4047
4048 bestn = clock->n;
4049 bestm1 = clock->m1;
4050 bestm2 = clock->m2;
4051 bestp1 = clock->p1;
4052 bestp2 = clock->p2;
4053
4054 /* Enable DPIO clock input */
4055 dpll = DPLL_EXT_BUFFER_ENABLE_VLV | DPLL_REFA_CLK_ENABLE_VLV |
4056 DPLL_VGA_MODE_DIS | DPLL_INTEGRATED_CLOCK_VLV;
4057 I915_WRITE(DPLL(pipe), dpll);
4058 POSTING_READ(DPLL(pipe));
4059
4060 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4061 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4062 mdiv |= ((bestn << DPIO_N_SHIFT));
4063 mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4064 mdiv |= (1 << DPIO_K_SHIFT);
4065 mdiv |= DPIO_ENABLE_CALIBRATION;
4066 intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4067
4068 intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4069
4070 pdiv = DPIO_REFSEL_OVERRIDE | (5 << DPIO_PLL_MODESEL_SHIFT) |
4071 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4072 (8 << DPIO_DRIVER_CTL_SHIFT) | (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4073 intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4074
4075 intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x009f0051);
4076
4077 dpll |= DPLL_VCO_ENABLE;
4078 I915_WRITE(DPLL(pipe), dpll);
4079 POSTING_READ(DPLL(pipe));
4080 if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4081 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4082
4083 if (is_hdmi) {
4084 u32 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4085
4086 if (temp > 1)
4087 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4088 else
4089 temp = 0;
4090
4091 I915_WRITE(DPLL_MD(pipe), temp);
4092 POSTING_READ(DPLL_MD(pipe));
4093 }
4094
4095 intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x641); /* ??? */
4096}
4097
eb1cbe48
DV		 4098static void i9xx_update_pll(struct drm_crtc *crtc,
4099 struct drm_display_mode *mode,
4100 struct drm_display_mode *adjusted_mode,
4101 intel_clock_t *clock, intel_clock_t *reduced_clock,
4102 int num_connectors)
4103{
4104 struct drm_device *dev = crtc->dev;
4105 struct drm_i915_private *dev_priv = dev->dev_private;
4106 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4107 int pipe = intel_crtc->pipe;
4108 u32 dpll;
4109 bool is_sdvo;
4110
4111 is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4112 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4113
4114 dpll = DPLL_VGA_MODE_DIS;
4115
4116 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4117 dpll |= DPLLB_MODE_LVDS;
4118 else
4119 dpll |= DPLLB_MODE_DAC_SERIAL;
4120 if (is_sdvo) {
4121 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4122 if (pixel_multiplier > 1) {
4123 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4124 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4125 }
4126 dpll |= DPLL_DVO_HIGH_SPEED;
4127 }
4128 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4129 dpll |= DPLL_DVO_HIGH_SPEED;
4130
4131 /* compute bitmask from p1 value */
4132 if (IS_PINEVIEW(dev))
4133 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4134 else {
4135 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4136 if (IS_G4X(dev) && reduced_clock)
4137 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4138 }
4139 switch (clock->p2) {
4140 case 5:
4141 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4142 break;
4143 case 7:
4144 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4145 break;
4146 case 10:
4147 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4148 break;
4149 case 14:
4150 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4151 break;
4152 }
4153 if (INTEL_INFO(dev)->gen >= 4)
4154 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4155
4156 if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4157 dpll |= PLL_REF_INPUT_TVCLKINBC;
4158 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4159 /* XXX: just matching BIOS for now */
4160 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4161 dpll |= 3;
4162 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4163 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4164 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4165 else
4166 dpll |= PLL_REF_INPUT_DREFCLK;
4167
4168 dpll |= DPLL_VCO_ENABLE;
4169 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4170 POSTING_READ(DPLL(pipe));
4171 udelay(150);
4172
4173 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4174 * This is an exception to the general rule that mode_set doesn't turn
4175 * things on.
4176 */
4177 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4178 intel_update_lvds(crtc, clock, adjusted_mode);
4179
4180 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4181 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4182
4183 I915_WRITE(DPLL(pipe), dpll);
4184
4185 /* Wait for the clocks to stabilize. */
4186 POSTING_READ(DPLL(pipe));
4187 udelay(150);
4188
4189 if (INTEL_INFO(dev)->gen >= 4) {
4190 u32 temp = 0;
4191 if (is_sdvo) {
4192 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4193 if (temp > 1)
4194 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4195 else
4196 temp = 0;
4197 }
4198 I915_WRITE(DPLL_MD(pipe), temp);
4199 } else {
4200 /* The pixel multiplier can only be updated once the
4201 * DPLL is enabled and the clocks are stable.
4202 *
4203 * So write it again.
4204 */
4205 I915_WRITE(DPLL(pipe), dpll);
4206 }
4207}
4208
4209static void i8xx_update_pll(struct drm_crtc *crtc,
4210 struct drm_display_mode *adjusted_mode,
4211 intel_clock_t *clock,
4212 int num_connectors)
4213{
4214 struct drm_device *dev = crtc->dev;
4215 struct drm_i915_private *dev_priv = dev->dev_private;
4216 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4217 int pipe = intel_crtc->pipe;
4218 u32 dpll;
4219
4220 dpll = DPLL_VGA_MODE_DIS;
4221
4222 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4223 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4224 } else {
4225 if (clock->p1 == 2)
4226 dpll |= PLL_P1_DIVIDE_BY_TWO;
4227 else
4228 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4229 if (clock->p2 == 4)
4230 dpll |= PLL_P2_DIVIDE_BY_4;
4231 }
4232
4233 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4234 /* XXX: just matching BIOS for now */
4235 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
4236 dpll |= 3;
4237 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4238 intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4239 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4240 else
4241 dpll |= PLL_REF_INPUT_DREFCLK;
4242
4243 dpll |= DPLL_VCO_ENABLE;
4244 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4245 POSTING_READ(DPLL(pipe));
4246 udelay(150);
4247
4248 I915_WRITE(DPLL(pipe), dpll);
4249
4250 /* Wait for the clocks to stabilize. */
4251 POSTING_READ(DPLL(pipe));
4252 udelay(150);
4253
4254 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4255 * This is an exception to the general rule that mode_set doesn't turn
4256 * things on.
4257 */
4258 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4259 intel_update_lvds(crtc, clock, adjusted_mode);
4260
4261 /* The pixel multiplier can only be updated once the
4262 * DPLL is enabled and the clocks are stable.
4263 *
4264 * So write it again.
4265 */
4266 I915_WRITE(DPLL(pipe), dpll);
4267}
4268
f564048e
EA		 4269static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4270 struct drm_display_mode *mode,
4271 struct drm_display_mode *adjusted_mode,
4272 int x, int y,
94352cf9 4273 struct drm_framebuffer *fb)
79e53945
JB		 4274{
4275 struct drm_device *dev = crtc->dev;
4276 struct drm_i915_private *dev_priv = dev->dev_private;
4277 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4278 int pipe = intel_crtc->pipe;
80824003 4279 int plane = intel_crtc->plane;
c751ce4f 4280 int refclk, num_connectors = 0;
652c393a 4281 intel_clock_t clock, reduced_clock;
eb1cbe48
DV		 4282 u32 dspcntr, pipeconf, vsyncshift;
4283 bool ok, has_reduced_clock = false, is_sdvo = false;
4284 bool is_lvds = false, is_tv = false, is_dp = false;
5eddb70b 4285 struct intel_encoder *encoder;
d4906093 4286 const intel_limit_t *limit;
5c3b82e2 4287 int ret;
79e53945 4288
6c2b7c12 4289 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4290 switch (encoder->type) {
79e53945
JB		 4291 case INTEL_OUTPUT_LVDS:
4292 is_lvds = true;
4293 break;
4294 case INTEL_OUTPUT_SDVO:
7d57382e 4295 case INTEL_OUTPUT_HDMI:
79e53945 4296 is_sdvo = true;
5eddb70b 4297 if (encoder->needs_tv_clock)
e2f0ba97 4298 is_tv = true;
79e53945 4299 break;
79e53945
JB		 4300 case INTEL_OUTPUT_TVOUT:
4301 is_tv = true;
4302 break;
a4fc5ed6
KP		 4303 case INTEL_OUTPUT_DISPLAYPORT:
4304 is_dp = true;
4305 break;
79e53945 4306 }
43565a06 4307
c751ce4f 4308 num_connectors++;
79e53945
JB		 4309 }
4310
c65d77d8 4311 refclk = i9xx_get_refclk(crtc, num_connectors);
79e53945 4312
d4906093
ML		 4313 /*
4314 * Returns a set of divisors for the desired target clock with the given
4315 * refclk, or FALSE. The returned values represent the clock equation:
4316 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4317 */
1b894b59 4318 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4319 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4320 &clock);
79e53945
JB		 4321 if (!ok) {
4322 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4323 return -EINVAL;
79e53945
JB		 4324 }
4325
cda4b7d3 4326 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4327 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4328
ddc9003c 4329 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4330 /*
4331 * Ensure we match the reduced clock's P to the target clock.
4332 * If the clocks don't match, we can't switch the display clock
4333 * by using the FP0/FP1. In such case we will disable the LVDS
4334 * downclock feature.
4335 */
ddc9003c 4336 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4337 dev_priv->lvds_downclock,
4338 refclk,
cec2f356 4339 &clock,
5eddb70b 4340 &reduced_clock);
7026d4ac
ZW		 4341 }
4342
c65d77d8
JB		 4343 if (is_sdvo && is_tv)
4344 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
7026d4ac 4345
a7516a05
JB		 4346 i9xx_update_pll_dividers(crtc, &clock, has_reduced_clock ?
4347 &reduced_clock : NULL);
79e53945 4348
eb1cbe48
DV		 4349 if (IS_GEN2(dev))
4350 i8xx_update_pll(crtc, adjusted_mode, &clock, num_connectors);
a0c4da24
JB		 4351 else if (IS_VALLEYVIEW(dev))
4352 vlv_update_pll(crtc, mode,adjusted_mode, &clock, NULL,
4353 refclk, num_connectors);
79e53945 4354 else
eb1cbe48
DV		 4355 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4356 has_reduced_clock ? &reduced_clock : NULL,
4357 num_connectors);
79e53945
JB		 4358
4359 /* setup pipeconf */
5eddb70b 4360 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4361
4362 /* Set up the display plane register */
4363 dspcntr = DISPPLANE_GAMMA_ENABLE;
4364
929c77fb
EA		 4365 if (pipe == 0)
4366 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4367 else
4368 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 4369
a6c45cf0 4370 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 4371 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4372 * core speed.
4373 *
4374 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4375 * pipe == 0 check?
4376 */
e70236a8
JB		 4377 if (mode->clock >
4378 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 4379 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 4380 else
5eddb70b 4381 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 4382 }
4383
3b5c78a3
AJ		 4384 /* default to 8bpc */
4385 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4386 if (is_dp) {
4387 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4388 pipeconf |= PIPECONF_BPP_6 |
4389 PIPECONF_DITHER_EN |
4390 PIPECONF_DITHER_TYPE_SP;
4391 }
4392 }
4393
28c97730 4394 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 4395 drm_mode_debug_printmodeline(mode);
4396
a7516a05
JB		 4397 if (HAS_PIPE_CXSR(dev)) {
4398 if (intel_crtc->lowfreq_avail) {
28c97730 4399 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a 4400 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
a7516a05 4401 } else {
28c97730 4402 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 4403 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4404 }
4405 }
4406
617cf884 4407 pipeconf &= ~PIPECONF_INTERLACE_MASK;
dbb02575
DV		 4408 if (!IS_GEN2(dev) &&
4409 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
734b4157
KH		 4410 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4411 /* the chip adds 2 halflines automatically */
734b4157 4412 adjusted_mode->crtc_vtotal -= 1;
734b4157 4413 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4414 vsyncshift = adjusted_mode->crtc_hsync_start
4415 - adjusted_mode->crtc_htotal/2;
4416 } else {
617cf884 4417 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4418 vsyncshift = 0;
4419 }
4420
4421 if (!IS_GEN3(dev))
4422 I915_WRITE(VSYNCSHIFT(pipe), vsyncshift);
734b4157 4423
5eddb70b
CW		 4424 I915_WRITE(HTOTAL(pipe),
4425 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4426 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4427 I915_WRITE(HBLANK(pipe),
4428 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4429 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4430 I915_WRITE(HSYNC(pipe),
4431 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4432 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4433
4434 I915_WRITE(VTOTAL(pipe),
4435 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4436 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4437 I915_WRITE(VBLANK(pipe),
4438 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4439 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4440 I915_WRITE(VSYNC(pipe),
4441 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4442 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 4443
4444 /* pipesrc and dspsize control the size that is scaled from,
4445 * which should always be the user's requested size.
79e53945 4446 */
929c77fb
EA		 4447 I915_WRITE(DSPSIZE(plane),
4448 ((mode->vdisplay - 1) << 16) |
4449 (mode->hdisplay - 1));
4450 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 4451 I915_WRITE(PIPESRC(pipe),
4452 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4453
f564048e
EA		 4454 I915_WRITE(PIPECONF(pipe), pipeconf);
4455 POSTING_READ(PIPECONF(pipe));
929c77fb 4456 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 4457
4458 intel_wait_for_vblank(dev, pipe);
4459
f564048e
EA		 4460 I915_WRITE(DSPCNTR(plane), dspcntr);
4461 POSTING_READ(DSPCNTR(plane));
4462
94352cf9 4463 ret = intel_pipe_set_base(crtc, x, y, fb);
f564048e
EA		 4464
4465 intel_update_watermarks(dev);
4466
f564048e
EA		 4467 return ret;
4468}
4469
9fb526db
KP		 4470/*
4471 * Initialize reference clocks when the driver loads
4472 */
4473void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 4474{
4475 struct drm_i915_private *dev_priv = dev->dev_private;
4476 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 4477 struct intel_encoder *encoder;
13d83a67
JB		 4478 u32 temp;
4479 bool has_lvds = false;
199e5d79
KP		 4480 bool has_cpu_edp = false;
4481 bool has_pch_edp = false;
4482 bool has_panel = false;
99eb6a01
KP		 4483 bool has_ck505 = false;
4484 bool can_ssc = false;
13d83a67
JB		 4485
4486 /* We need to take the global config into account */
199e5d79
KP		 4487 list_for_each_entry(encoder, &mode_config->encoder_list,
4488 base.head) {
4489 switch (encoder->type) {
4490 case INTEL_OUTPUT_LVDS:
4491 has_panel = true;
4492 has_lvds = true;
4493 break;
4494 case INTEL_OUTPUT_EDP:
4495 has_panel = true;
4496 if (intel_encoder_is_pch_edp(&encoder->base))
4497 has_pch_edp = true;
4498 else
4499 has_cpu_edp = true;
4500 break;
13d83a67
JB		 4501 }
4502 }
4503
99eb6a01
KP		 4504 if (HAS_PCH_IBX(dev)) {
4505 has_ck505 = dev_priv->display_clock_mode;
4506 can_ssc = has_ck505;
4507 } else {
4508 has_ck505 = false;
4509 can_ssc = true;
4510 }
4511
4512 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4513 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4514 has_ck505);
13d83a67
JB		 4515
4516 /* Ironlake: try to setup display ref clock before DPLL
4517 * enabling. This is only under driver's control after
4518 * PCH B stepping, previous chipset stepping should be
4519 * ignoring this setting.
4520 */
4521 temp = I915_READ(PCH_DREF_CONTROL);
4522 /* Always enable nonspread source */
4523 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 4524
99eb6a01
KP		 4525 if (has_ck505)
4526 temp |= DREF_NONSPREAD_CK505_ENABLE;
4527 else
4528 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 4529
199e5d79
KP		 4530 if (has_panel) {
4531 temp &= ~DREF_SSC_SOURCE_MASK;
4532 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 4533
199e5d79 4534 /* SSC must be turned on before enabling the CPU output */
99eb6a01 4535 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4536 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 4537 temp |= DREF_SSC1_ENABLE;
e77166b5
DV		 4538 } else
4539 temp &= ~DREF_SSC1_ENABLE;
199e5d79
KP		 4540
4541 /* Get SSC going before enabling the outputs */
4542 I915_WRITE(PCH_DREF_CONTROL, temp);
4543 POSTING_READ(PCH_DREF_CONTROL);
4544 udelay(200);
4545
13d83a67
JB		 4546 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4547
4548 /* Enable CPU source on CPU attached eDP */
199e5d79 4549 if (has_cpu_edp) {
99eb6a01 4550 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 4551 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 4552 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 4553 }
13d83a67
JB		 4554 else
4555 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 4556 } else
4557 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4558
4559 I915_WRITE(PCH_DREF_CONTROL, temp);
4560 POSTING_READ(PCH_DREF_CONTROL);
4561 udelay(200);
4562 } else {
4563 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4564
4565 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4566
4567 /* Turn off CPU output */
4568 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4569
4570 I915_WRITE(PCH_DREF_CONTROL, temp);
4571 POSTING_READ(PCH_DREF_CONTROL);
4572 udelay(200);
4573
4574 /* Turn off the SSC source */
4575 temp &= ~DREF_SSC_SOURCE_MASK;
4576 temp |= DREF_SSC_SOURCE_DISABLE;
4577
4578 /* Turn off SSC1 */
4579 temp &= ~ DREF_SSC1_ENABLE;
4580
13d83a67
JB		 4581 I915_WRITE(PCH_DREF_CONTROL, temp);
4582 POSTING_READ(PCH_DREF_CONTROL);
4583 udelay(200);
4584 }
4585}
4586
d9d444cb
JB		 4587static int ironlake_get_refclk(struct drm_crtc *crtc)
4588{
4589 struct drm_device *dev = crtc->dev;
4590 struct drm_i915_private *dev_priv = dev->dev_private;
4591 struct intel_encoder *encoder;
d9d444cb
JB		 4592 struct intel_encoder *edp_encoder = NULL;
4593 int num_connectors = 0;
4594 bool is_lvds = false;
4595
6c2b7c12 4596 for_each_encoder_on_crtc(dev, crtc, encoder) {
d9d444cb
JB		 4597 switch (encoder->type) {
4598 case INTEL_OUTPUT_LVDS:
4599 is_lvds = true;
4600 break;
4601 case INTEL_OUTPUT_EDP:
4602 edp_encoder = encoder;
4603 break;
4604 }
4605 num_connectors++;
4606 }
4607
4608 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4609 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4610 dev_priv->lvds_ssc_freq);
4611 return dev_priv->lvds_ssc_freq * 1000;
4612 }
4613
4614 return 120000;
4615}
4616
f564048e
EA		 4617static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
4618 struct drm_display_mode *mode,
4619 struct drm_display_mode *adjusted_mode,
4620 int x, int y,
94352cf9 4621 struct drm_framebuffer *fb)
79e53945
JB		 4622{
4623 struct drm_device *dev = crtc->dev;
4624 struct drm_i915_private *dev_priv = dev->dev_private;
4625 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4626 int pipe = intel_crtc->pipe;
80824003 4627 int plane = intel_crtc->plane;
c751ce4f 4628 int refclk, num_connectors = 0;
652c393a 4629 intel_clock_t clock, reduced_clock;
5eddb70b 4630 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 4631 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 4632 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
e3aef172 4633 struct intel_encoder *encoder, *edp_encoder = NULL;
d4906093 4634 const intel_limit_t *limit;
5c3b82e2 4635 int ret;
2c07245f 4636 struct fdi_m_n m_n = {0};
fae14981 4637 u32 temp;
5a354204
JB		 4638 int target_clock, pixel_multiplier, lane, link_bw, factor;
4639 unsigned int pipe_bpp;
4640 bool dither;
e3aef172 4641 bool is_cpu_edp = false, is_pch_edp = false;
79e53945 4642
6c2b7c12 4643 for_each_encoder_on_crtc(dev, crtc, encoder) {
5eddb70b 4644 switch (encoder->type) {
79e53945
JB		 4645 case INTEL_OUTPUT_LVDS:
4646 is_lvds = true;
4647 break;
4648 case INTEL_OUTPUT_SDVO:
7d57382e 4649 case INTEL_OUTPUT_HDMI:
79e53945 4650 is_sdvo = true;
5eddb70b 4651 if (encoder->needs_tv_clock)
e2f0ba97 4652 is_tv = true;
79e53945 4653 break;
79e53945
JB		 4654 case INTEL_OUTPUT_TVOUT:
4655 is_tv = true;
4656 break;
4657 case INTEL_OUTPUT_ANALOG:
4658 is_crt = true;
4659 break;
a4fc5ed6
KP		 4660 case INTEL_OUTPUT_DISPLAYPORT:
4661 is_dp = true;
4662 break;
32f9d658 4663 case INTEL_OUTPUT_EDP:
e3aef172
JB		 4664 is_dp = true;
4665 if (intel_encoder_is_pch_edp(&encoder->base))
4666 is_pch_edp = true;
4667 else
4668 is_cpu_edp = true;
4669 edp_encoder = encoder;
32f9d658 4670 break;
79e53945 4671 }
43565a06 4672
c751ce4f 4673 num_connectors++;
79e53945
JB		 4674 }
4675
d9d444cb 4676 refclk = ironlake_get_refclk(crtc);
79e53945 4677
d4906093
ML		 4678 /*
4679 * Returns a set of divisors for the desired target clock with the given
4680 * refclk, or FALSE. The returned values represent the clock equation:
4681 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4682 */
1b894b59 4683 limit = intel_limit(crtc, refclk);
cec2f356
SP		 4684 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4685 &clock);
79e53945
JB		 4686 if (!ok) {
4687 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 4688 return -EINVAL;
79e53945
JB		 4689 }
4690
cda4b7d3 4691 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 4692 intel_crtc_update_cursor(crtc, true);
cda4b7d3 4693
ddc9003c 4694 if (is_lvds && dev_priv->lvds_downclock_avail) {
cec2f356
SP		 4695 /*
4696 * Ensure we match the reduced clock's P to the target clock.
4697 * If the clocks don't match, we can't switch the display clock
4698 * by using the FP0/FP1. In such case we will disable the LVDS
4699 * downclock feature.
4700 */
ddc9003c 4701 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 4702 dev_priv->lvds_downclock,
4703 refclk,
cec2f356 4704 &clock,
5eddb70b 4705 &reduced_clock);
652c393a 4706 }
61e9653f
DV		 4707
4708 if (is_sdvo && is_tv)
4709 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4710
7026d4ac 4711
2c07245f 4712 /* FDI link */
8febb297
EA		 4713 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4714 lane = 0;
4715 /* CPU eDP doesn't require FDI link, so just set DP M/N
4716 according to current link config */
e3aef172 4717 if (is_cpu_edp) {
e3aef172 4718 intel_edp_link_config(edp_encoder, &lane, &link_bw);
8febb297 4719 } else {
8febb297
EA		 4720 /* FDI is a binary signal running at ~2.7GHz, encoding
4721 * each output octet as 10 bits. The actual frequency
4722 * is stored as a divider into a 100MHz clock, and the
4723 * mode pixel clock is stored in units of 1KHz.
4724 * Hence the bw of each lane in terms of the mode signal
4725 * is:
4726 */
4727 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
4728 }
58a27471 4729
94bf2ced
DV		 4730 /* [e]DP over FDI requires target mode clock instead of link clock. */
4731 if (edp_encoder)
4732 target_clock = intel_edp_target_clock(edp_encoder, mode);
4733 else if (is_dp)
4734 target_clock = mode->clock;
4735 else
4736 target_clock = adjusted_mode->clock;
4737
8febb297
EA		 4738 /* determine panel color depth */
4739 temp = I915_READ(PIPECONF(pipe));
4740 temp &= ~PIPE_BPC_MASK;
94352cf9 4741 dither = intel_choose_pipe_bpp_dither(crtc, fb, &pipe_bpp, mode);
5a354204
JB		 4742 switch (pipe_bpp) {
4743 case 18:
4744 temp |= PIPE_6BPC;
8febb297 4745 break;
5a354204
JB		 4746 case 24:
4747 temp |= PIPE_8BPC;
8febb297 4748 break;
5a354204
JB		 4749 case 30:
4750 temp |= PIPE_10BPC;
8febb297 4751 break;
5a354204
JB		 4752 case 36:
4753 temp |= PIPE_12BPC;
8febb297
EA		 4754 break;
4755 default:
62ac41a6
JB		 4756 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
4757 pipe_bpp);
5a354204
JB		 4758 temp |= PIPE_8BPC;
4759 pipe_bpp = 24;
4760 break;
8febb297 4761 }
77ffb597 4762
5a354204
JB		 4763 intel_crtc->bpp = pipe_bpp;
4764 I915_WRITE(PIPECONF(pipe), temp);
4765
8febb297
EA		 4766 if (!lane) {
4767 /*
4768 * Account for spread spectrum to avoid
4769 * oversubscribing the link. Max center spread
4770 * is 2.5%; use 5% for safety's sake.
4771 */
5a354204 4772 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 4773 lane = bps / (link_bw * 8) + 1;
5eb08b69 4774 }
2c07245f 4775
8febb297
EA		 4776 intel_crtc->fdi_lanes = lane;
4777
4778 if (pixel_multiplier > 1)
4779 link_bw *= pixel_multiplier;
5a354204
JB		 4780 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
4781 &m_n);
8febb297 4782
a07d6787
EA		 4783 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
4784 if (has_reduced_clock)
4785 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
4786 reduced_clock.m2;
79e53945 4787
c1858123 4788 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 4789 factor = 21;
4790 if (is_lvds) {
4791 if ((intel_panel_use_ssc(dev_priv) &&
4792 dev_priv->lvds_ssc_freq == 100) ||
4793 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
4794 factor = 25;
4795 } else if (is_sdvo && is_tv)
4796 factor = 20;
c1858123 4797
cb0e0931 4798 if (clock.m < factor * clock.n)
8febb297 4799 fp |= FP_CB_TUNE;
2c07245f 4800
5eddb70b 4801 dpll = 0;
2c07245f 4802
a07d6787
EA		 4803 if (is_lvds)
4804 dpll |= DPLLB_MODE_LVDS;
4805 else
4806 dpll |= DPLLB_MODE_DAC_SERIAL;
4807 if (is_sdvo) {
4808 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4809 if (pixel_multiplier > 1) {
4810 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 4811 }
a07d6787
EA		 4812 dpll |= DPLL_DVO_HIGH_SPEED;
4813 }
e3aef172 4814 if (is_dp && !is_cpu_edp)
a07d6787 4815 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 4816
a07d6787
EA		 4817 /* compute bitmask from p1 value */
4818 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4819 /* also FPA1 */
4820 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4821
4822 switch (clock.p2) {
4823 case 5:
4824 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4825 break;
4826 case 7:
4827 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4828 break;
4829 case 10:
4830 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4831 break;
4832 case 14:
4833 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4834 break;
79e53945
JB		 4835 }
4836
43565a06
KH		 4837 if (is_sdvo && is_tv)
4838 dpll |= PLL_REF_INPUT_TVCLKINBC;
4839 else if (is_tv)
79e53945 4840 /* XXX: just matching BIOS for now */
43565a06 4841 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 4842 dpll |= 3;
a7615030 4843 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 4844 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 4845 else
4846 dpll |= PLL_REF_INPUT_DREFCLK;
4847
4848 /* setup pipeconf */
5eddb70b 4849 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 4850
4851 /* Set up the display plane register */
4852 dspcntr = DISPPLANE_GAMMA_ENABLE;
4853
f7cb34d4 4854 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 4855 drm_mode_debug_printmodeline(mode);
4856
9d82aa17
ED		 4857 /* CPU eDP is the only output that doesn't need a PCH PLL of its own on
4858 * pre-Haswell/LPT generation */
4859 if (HAS_PCH_LPT(dev)) {
4860 DRM_DEBUG_KMS("LPT detected: no PLL for pipe %d necessary\n",
4861 pipe);
4862 } else if (!is_cpu_edp) {
ee7b9f93 4863 struct intel_pch_pll *pll;
4b645f14 4864
ee7b9f93
JB		 4865 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
4866 if (pll == NULL) {
4867 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
4868 pipe);
4b645f14
JB		 4869 return -EINVAL;
4870 }
ee7b9f93
JB		 4871 } else
4872 intel_put_pch_pll(intel_crtc);
79e53945
JB		 4873
4874 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
4875 * This is an exception to the general rule that mode_set doesn't turn
4876 * things on.
4877 */
4878 if (is_lvds) {
fae14981 4879 temp = I915_READ(PCH_LVDS);
5eddb70b 4880 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 4881 if (HAS_PCH_CPT(dev)) {
4882 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 4883 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 4884 } else {
4885 if (pipe == 1)
4886 temp |= LVDS_PIPEB_SELECT;
4887 else
4888 temp &= ~LVDS_PIPEB_SELECT;
4889 }
4b645f14 4890
a3e17eb8 4891 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 4892 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 4893 /* Set the B0-B3 data pairs corresponding to whether we're going to
4894 * set the DPLLs for dual-channel mode or not.
4895 */
4896 if (clock.p2 == 7)
5eddb70b 4897 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 4898 else
5eddb70b 4899 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 4900
4901 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
4902 * appropriately here, but we need to look more thoroughly into how
4903 * panels behave in the two modes.
4904 */
284d5df5 4905 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
aa9b500d 4906 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
284d5df5 4907 temp |= LVDS_HSYNC_POLARITY;
aa9b500d 4908 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
284d5df5 4909 temp |= LVDS_VSYNC_POLARITY;
fae14981 4910 I915_WRITE(PCH_LVDS, temp);
79e53945 4911 }
434ed097 4912
8febb297
EA		 4913 pipeconf &= ~PIPECONF_DITHER_EN;
4914 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 4915 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 4916 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 4917 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 4918 }
e3aef172 4919 if (is_dp && !is_cpu_edp) {
a4fc5ed6 4920 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 4921 } else {
8db9d77b 4922 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 4923 I915_WRITE(TRANSDATA_M1(pipe), 0);
4924 I915_WRITE(TRANSDATA_N1(pipe), 0);
4925 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
4926 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 4927 }
79e53945 4928
ee7b9f93
JB		 4929 if (intel_crtc->pch_pll) {
4930 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5eddb70b 4931
32f9d658 4932 /* Wait for the clocks to stabilize. */
ee7b9f93 4933 POSTING_READ(intel_crtc->pch_pll->pll_reg);
32f9d658
ZW		 4934 udelay(150);
4935
8febb297
EA		 4936 /* The pixel multiplier can only be updated once the
4937 * DPLL is enabled and the clocks are stable.
4938 *
4939 * So write it again.
4940 */
ee7b9f93 4941 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
79e53945 4942 }
79e53945 4943
5eddb70b 4944 intel_crtc->lowfreq_avail = false;
ee7b9f93 4945 if (intel_crtc->pch_pll) {
4b645f14 4946 if (is_lvds && has_reduced_clock && i915_powersave) {
ee7b9f93 4947 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
4b645f14 4948 intel_crtc->lowfreq_avail = true;
4b645f14 4949 } else {
ee7b9f93 4950 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
652c393a
JB		 4951 }
4952 }
4953
617cf884 4954 pipeconf &= ~PIPECONF_INTERLACE_MASK;
734b4157 4955 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5def474e 4956 pipeconf |= PIPECONF_INTERLACED_ILK;
734b4157 4957 /* the chip adds 2 halflines automatically */
734b4157 4958 adjusted_mode->crtc_vtotal -= 1;
734b4157 4959 adjusted_mode->crtc_vblank_end -= 1;
0529a0d9
DV		 4960 I915_WRITE(VSYNCSHIFT(pipe),
4961 adjusted_mode->crtc_hsync_start
4962 - adjusted_mode->crtc_htotal/2);
4963 } else {
617cf884 4964 pipeconf |= PIPECONF_PROGRESSIVE;
0529a0d9
DV		 4965 I915_WRITE(VSYNCSHIFT(pipe), 0);
4966 }
734b4157 4967
5eddb70b
CW		 4968 I915_WRITE(HTOTAL(pipe),
4969 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 4970 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 4971 I915_WRITE(HBLANK(pipe),
4972 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 4973 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 4974 I915_WRITE(HSYNC(pipe),
4975 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 4976 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 4977
4978 I915_WRITE(VTOTAL(pipe),
4979 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 4980 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 4981 I915_WRITE(VBLANK(pipe),
4982 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 4983 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 4984 I915_WRITE(VSYNC(pipe),
4985 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 4986 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 4987
8febb297
EA		 4988 /* pipesrc controls the size that is scaled from, which should
4989 * always be the user's requested size.
79e53945 4990 */
5eddb70b
CW		 4991 I915_WRITE(PIPESRC(pipe),
4992 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 4993
8febb297
EA		 4994 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4995 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4996 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4997 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 4998
e3aef172 4999 if (is_cpu_edp)
8febb297 5000 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f 5001
5eddb70b
CW		 5002 I915_WRITE(PIPECONF(pipe), pipeconf);
5003 POSTING_READ(PIPECONF(pipe));
79e53945 5004
9d0498a2 5005 intel_wait_for_vblank(dev, pipe);
79e53945 5006
5eddb70b 5007 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 5008 POSTING_READ(DSPCNTR(plane));
79e53945 5009
94352cf9 5010 ret = intel_pipe_set_base(crtc, x, y, fb);
7662c8bd
SL		 5011
5012 intel_update_watermarks(dev);
5013
1f8eeabf
ED		 5014 intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5015
1f803ee5 5016 return ret;
79e53945
JB		 5017}
5018
f564048e
EA		 5019static int intel_crtc_mode_set(struct drm_crtc *crtc,
5020 struct drm_display_mode *mode,
5021 struct drm_display_mode *adjusted_mode,
5022 int x, int y,
94352cf9 5023 struct drm_framebuffer *fb)
f564048e
EA		 5024{
5025 struct drm_device *dev = crtc->dev;
5026 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5027 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5028 int pipe = intel_crtc->pipe;
f564048e
EA		 5029 int ret;
5030
0b701d27 5031 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5032
f564048e 5033 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
94352cf9 5034 x, y, fb);
79e53945 5035 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5036
1f803ee5 5037 return ret;
79e53945
JB		 5038}
5039
3a9627f4
WF		 5040static bool intel_eld_uptodate(struct drm_connector *connector,
5041 int reg_eldv, uint32_t bits_eldv,
5042 int reg_elda, uint32_t bits_elda,
5043 int reg_edid)
5044{
5045 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5046 uint8_t *eld = connector->eld;
5047 uint32_t i;
5048
5049 i = I915_READ(reg_eldv);
5050 i &= bits_eldv;
5051
5052 if (!eld[0])
5053 return !i;
5054
5055 if (!i)
5056 return false;
5057
5058 i = I915_READ(reg_elda);
5059 i &= ~bits_elda;
5060 I915_WRITE(reg_elda, i);
5061
5062 for (i = 0; i < eld[2]; i++)
5063 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5064 return false;
5065
5066 return true;
5067}
5068
e0dac65e
WF		 5069static void g4x_write_eld(struct drm_connector *connector,
5070 struct drm_crtc *crtc)
5071{
5072 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5073 uint8_t *eld = connector->eld;
5074 uint32_t eldv;
5075 uint32_t len;
5076 uint32_t i;
5077
5078 i = I915_READ(G4X_AUD_VID_DID);
5079
5080 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5081 eldv = G4X_ELDV_DEVCL_DEVBLC;
5082 else
5083 eldv = G4X_ELDV_DEVCTG;
5084
3a9627f4
WF		 5085 if (intel_eld_uptodate(connector,
5086 G4X_AUD_CNTL_ST, eldv,
5087 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5088 G4X_HDMIW_HDMIEDID))
5089 return;
5090
e0dac65e
WF		 5091 i = I915_READ(G4X_AUD_CNTL_ST);
5092 i &= ~(eldv | G4X_ELD_ADDR);
5093 len = (i >> 9) & 0x1f; /* ELD buffer size */
5094 I915_WRITE(G4X_AUD_CNTL_ST, i);
5095
5096 if (!eld[0])
5097 return;
5098
5099 len = min_t(uint8_t, eld[2], len);
5100 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5101 for (i = 0; i < len; i++)
5102 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5103
5104 i = I915_READ(G4X_AUD_CNTL_ST);
5105 i |= eldv;
5106 I915_WRITE(G4X_AUD_CNTL_ST, i);
5107}
5108
83358c85
WX		 5109static void haswell_write_eld(struct drm_connector *connector,
5110 struct drm_crtc *crtc)
5111{
5112 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5113 uint8_t *eld = connector->eld;
5114 struct drm_device *dev = crtc->dev;
5115 uint32_t eldv;
5116 uint32_t i;
5117 int len;
5118 int pipe = to_intel_crtc(crtc)->pipe;
5119 int tmp;
5120
5121 int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5122 int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5123 int aud_config = HSW_AUD_CFG(pipe);
5124 int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5125
5126
5127 DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5128
5129 /* Audio output enable */
5130 DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5131 tmp = I915_READ(aud_cntrl_st2);
5132 tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5133 I915_WRITE(aud_cntrl_st2, tmp);
5134
5135 /* Wait for 1 vertical blank */
5136 intel_wait_for_vblank(dev, pipe);
5137
5138 /* Set ELD valid state */
5139 tmp = I915_READ(aud_cntrl_st2);
5140 DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5141 tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5142 I915_WRITE(aud_cntrl_st2, tmp);
5143 tmp = I915_READ(aud_cntrl_st2);
5144 DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5145
5146 /* Enable HDMI mode */
5147 tmp = I915_READ(aud_config);
5148 DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5149 /* clear N_programing_enable and N_value_index */
5150 tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5151 I915_WRITE(aud_config, tmp);
5152
5153 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5154
5155 eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5156
5157 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5158 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5159 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
5160 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5161 } else
5162 I915_WRITE(aud_config, 0);
5163
5164 if (intel_eld_uptodate(connector,
5165 aud_cntrl_st2, eldv,
5166 aud_cntl_st, IBX_ELD_ADDRESS,
5167 hdmiw_hdmiedid))
5168 return;
5169
5170 i = I915_READ(aud_cntrl_st2);
5171 i &= ~eldv;
5172 I915_WRITE(aud_cntrl_st2, i);
5173
5174 if (!eld[0])
5175 return;
5176
5177 i = I915_READ(aud_cntl_st);
5178 i &= ~IBX_ELD_ADDRESS;
5179 I915_WRITE(aud_cntl_st, i);
5180 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
5181 DRM_DEBUG_DRIVER("port num:%d\n", i);
5182
5183 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5184 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5185 for (i = 0; i < len; i++)
5186 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5187
5188 i = I915_READ(aud_cntrl_st2);
5189 i |= eldv;
5190 I915_WRITE(aud_cntrl_st2, i);
5191
5192}
5193
e0dac65e
WF		 5194static void ironlake_write_eld(struct drm_connector *connector,
5195 struct drm_crtc *crtc)
5196{
5197 struct drm_i915_private *dev_priv = connector->dev->dev_private;
5198 uint8_t *eld = connector->eld;
5199 uint32_t eldv;
5200 uint32_t i;
5201 int len;
5202 int hdmiw_hdmiedid;
b6daa025 5203 int aud_config;
e0dac65e
WF		 5204 int aud_cntl_st;
5205 int aud_cntrl_st2;
9b138a83 5206 int pipe = to_intel_crtc(crtc)->pipe;
e0dac65e 5207
b3f33cbf 5208 if (HAS_PCH_IBX(connector->dev)) {
9b138a83
WX		 5209 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5210 aud_config = IBX_AUD_CFG(pipe);
5211 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
1202b4c6 5212 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 5213 } else {
9b138a83
WX		 5214 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5215 aud_config = CPT_AUD_CFG(pipe);
5216 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
1202b4c6 5217 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 5218 }
5219
9b138a83 5220 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
e0dac65e
WF		 5221
5222 i = I915_READ(aud_cntl_st);
9b138a83 5223 i = (i >> 29) & DIP_PORT_SEL_MASK; /* DIP_Port_Select, 0x1 = PortB */
e0dac65e
WF		 5224 if (!i) {
5225 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5226 /* operate blindly on all ports */
1202b4c6
WF		 5227 eldv = IBX_ELD_VALIDB;
5228 eldv |= IBX_ELD_VALIDB << 4;
5229 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 5230 } else {
5231 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 5232 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 5233 }
5234
3a9627f4
WF		 5235 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5236 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5237 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
b6daa025
WF		 5238 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5239 } else
5240 I915_WRITE(aud_config, 0);
e0dac65e 5241
3a9627f4
WF		 5242 if (intel_eld_uptodate(connector,
5243 aud_cntrl_st2, eldv,
5244 aud_cntl_st, IBX_ELD_ADDRESS,
5245 hdmiw_hdmiedid))
5246 return;
5247
e0dac65e
WF		 5248 i = I915_READ(aud_cntrl_st2);
5249 i &= ~eldv;
5250 I915_WRITE(aud_cntrl_st2, i);
5251
5252 if (!eld[0])
5253 return;
5254
e0dac65e 5255 i = I915_READ(aud_cntl_st);
1202b4c6 5256 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 5257 I915_WRITE(aud_cntl_st, i);
5258
5259 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
5260 DRM_DEBUG_DRIVER("ELD size %d\n", len);
5261 for (i = 0; i < len; i++)
5262 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5263
5264 i = I915_READ(aud_cntrl_st2);
5265 i |= eldv;
5266 I915_WRITE(aud_cntrl_st2, i);
5267}
5268
5269void intel_write_eld(struct drm_encoder *encoder,
5270 struct drm_display_mode *mode)
5271{
5272 struct drm_crtc *crtc = encoder->crtc;
5273 struct drm_connector *connector;
5274 struct drm_device *dev = encoder->dev;
5275 struct drm_i915_private *dev_priv = dev->dev_private;
5276
5277 connector = drm_select_eld(encoder, mode);
5278 if (!connector)
5279 return;
5280
5281 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5282 connector->base.id,
5283 drm_get_connector_name(connector),
5284 connector->encoder->base.id,
5285 drm_get_encoder_name(connector->encoder));
5286
5287 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5288
5289 if (dev_priv->display.write_eld)
5290 dev_priv->display.write_eld(connector, crtc);
5291}
5292
79e53945
JB		 5293/** Loads the palette/gamma unit for the CRTC with the prepared values */
5294void intel_crtc_load_lut(struct drm_crtc *crtc)
5295{
5296 struct drm_device *dev = crtc->dev;
5297 struct drm_i915_private *dev_priv = dev->dev_private;
5298 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 5299 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 5300 int i;
5301
5302 /* The clocks have to be on to load the palette. */
aed3f09d 5303 if (!crtc->enabled || !intel_crtc->active)
79e53945
JB		 5304 return;
5305
f2b115e6 5306 /* use legacy palette for Ironlake */
bad720ff 5307 if (HAS_PCH_SPLIT(dev))
9db4a9c7 5308 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 5309
79e53945
JB		 5310 for (i = 0; i < 256; i++) {
5311 I915_WRITE(palreg + 4 * i,
5312 (intel_crtc->lut_r[i] << 16) |
5313 (intel_crtc->lut_g[i] << 8) |
5314 intel_crtc->lut_b[i]);
5315 }
5316}
5317
560b85bb
CW		 5318static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5319{
5320 struct drm_device *dev = crtc->dev;
5321 struct drm_i915_private *dev_priv = dev->dev_private;
5322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5323 bool visible = base != 0;
5324 u32 cntl;
5325
5326 if (intel_crtc->cursor_visible == visible)
5327 return;
5328
9db4a9c7 5329 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 5330 if (visible) {
5331 /* On these chipsets we can only modify the base whilst
5332 * the cursor is disabled.
5333 */
9db4a9c7 5334 I915_WRITE(_CURABASE, base);
560b85bb
CW		 5335
5336 cntl &= ~(CURSOR_FORMAT_MASK);
5337 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5338 cntl |= CURSOR_ENABLE |
5339 CURSOR_GAMMA_ENABLE |
5340 CURSOR_FORMAT_ARGB;
5341 } else
5342 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 5343 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 5344
5345 intel_crtc->cursor_visible = visible;
5346}
5347
5348static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
5349{
5350 struct drm_device *dev = crtc->dev;
5351 struct drm_i915_private *dev_priv = dev->dev_private;
5352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5353 int pipe = intel_crtc->pipe;
5354 bool visible = base != 0;
5355
5356 if (intel_crtc->cursor_visible != visible) {
548f245b 5357 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 5358 if (base) {
5359 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
5360 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5361 cntl |= pipe << 28; /* Connect to correct pipe */
5362 } else {
5363 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5364 cntl |= CURSOR_MODE_DISABLE;
5365 }
9db4a9c7 5366 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 5367
5368 intel_crtc->cursor_visible = visible;
5369 }
5370 /* and commit changes on next vblank */
9db4a9c7 5371 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 5372}
5373
65a21cd6
JB		 5374static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
5375{
5376 struct drm_device *dev = crtc->dev;
5377 struct drm_i915_private *dev_priv = dev->dev_private;
5378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5379 int pipe = intel_crtc->pipe;
5380 bool visible = base != 0;
5381
5382 if (intel_crtc->cursor_visible != visible) {
5383 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
5384 if (base) {
5385 cntl &= ~CURSOR_MODE;
5386 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
5387 } else {
5388 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
5389 cntl |= CURSOR_MODE_DISABLE;
5390 }
5391 I915_WRITE(CURCNTR_IVB(pipe), cntl);
5392
5393 intel_crtc->cursor_visible = visible;
5394 }
5395 /* and commit changes on next vblank */
5396 I915_WRITE(CURBASE_IVB(pipe), base);
5397}
5398
cda4b7d3 5399/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 5400static void intel_crtc_update_cursor(struct drm_crtc *crtc,
5401 bool on)
cda4b7d3
CW		 5402{
5403 struct drm_device *dev = crtc->dev;
5404 struct drm_i915_private *dev_priv = dev->dev_private;
5405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5406 int pipe = intel_crtc->pipe;
5407 int x = intel_crtc->cursor_x;
5408 int y = intel_crtc->cursor_y;
560b85bb 5409 u32 base, pos;
cda4b7d3
CW		 5410 bool visible;
5411
5412 pos = 0;
5413
6b383a7f 5414 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 5415 base = intel_crtc->cursor_addr;
5416 if (x > (int) crtc->fb->width)
5417 base = 0;
5418
5419 if (y > (int) crtc->fb->height)
5420 base = 0;
5421 } else
5422 base = 0;
5423
5424 if (x < 0) {
5425 if (x + intel_crtc->cursor_width < 0)
5426 base = 0;
5427
5428 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
5429 x = -x;
5430 }
5431 pos |= x << CURSOR_X_SHIFT;
5432
5433 if (y < 0) {
5434 if (y + intel_crtc->cursor_height < 0)
5435 base = 0;
5436
5437 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
5438 y = -y;
5439 }
5440 pos |= y << CURSOR_Y_SHIFT;
5441
5442 visible = base != 0;
560b85bb 5443 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 5444 return;
5445
0cd83aa9 5446 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
65a21cd6
JB		 5447 I915_WRITE(CURPOS_IVB(pipe), pos);
5448 ivb_update_cursor(crtc, base);
5449 } else {
5450 I915_WRITE(CURPOS(pipe), pos);
5451 if (IS_845G(dev) || IS_I865G(dev))
5452 i845_update_cursor(crtc, base);
5453 else
5454 i9xx_update_cursor(crtc, base);
5455 }
cda4b7d3
CW		 5456}
5457
79e53945 5458static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 5459 struct drm_file *file,
79e53945
JB		 5460 uint32_t handle,
5461 uint32_t width, uint32_t height)
5462{
5463 struct drm_device *dev = crtc->dev;
5464 struct drm_i915_private *dev_priv = dev->dev_private;
5465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 5466 struct drm_i915_gem_object *obj;
cda4b7d3 5467 uint32_t addr;
3f8bc370 5468 int ret;
79e53945 5469
79e53945
JB		 5470 /* if we want to turn off the cursor ignore width and height */
5471 if (!handle) {
28c97730 5472 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 5473 addr = 0;
05394f39 5474 obj = NULL;
5004417d 5475 mutex_lock(&dev->struct_mutex);
3f8bc370 5476 goto finish;
79e53945
JB		 5477 }
5478
5479 /* Currently we only support 64x64 cursors */
5480 if (width != 64 || height != 64) {
5481 DRM_ERROR("we currently only support 64x64 cursors\n");
5482 return -EINVAL;
5483 }
5484
05394f39 5485 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 5486 if (&obj->base == NULL)
79e53945
JB		 5487 return -ENOENT;
5488
05394f39 5489 if (obj->base.size < width * height * 4) {
79e53945 5490 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 5491 ret = -ENOMEM;
5492 goto fail;
79e53945
JB		 5493 }
5494
71acb5eb 5495 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 5496 mutex_lock(&dev->struct_mutex);
b295d1b6 5497 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 5498 if (obj->tiling_mode) {
5499 DRM_ERROR("cursor cannot be tiled\n");
5500 ret = -EINVAL;
5501 goto fail_locked;
5502 }
5503
2da3b9b9 5504 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 5505 if (ret) {
5506 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 5507 goto fail_locked;
e7b526bb
CW		 5508 }
5509
d9e86c0e
CW		 5510 ret = i915_gem_object_put_fence(obj);
5511 if (ret) {
2da3b9b9 5512 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 5513 goto fail_unpin;
5514 }
5515
05394f39 5516 addr = obj->gtt_offset;
71acb5eb 5517 } else {
6eeefaf3 5518 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 5519 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 5520 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
5521 align);
71acb5eb
DA		 5522 if (ret) {
5523 DRM_ERROR("failed to attach phys object\n");
7f9872e0 5524 goto fail_locked;
71acb5eb 5525 }
05394f39 5526 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 5527 }
5528
a6c45cf0 5529 if (IS_GEN2(dev))
14b60391
JB		 5530 I915_WRITE(CURSIZE, (height << 12) | width);
5531
3f8bc370 5532 finish:
3f8bc370 5533 if (intel_crtc->cursor_bo) {
b295d1b6 5534 if (dev_priv->info->cursor_needs_physical) {
05394f39 5535 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 5536 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
5537 } else
5538 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 5539 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 5540 }
80824003 5541
7f9872e0 5542 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 5543
5544 intel_crtc->cursor_addr = addr;
05394f39 5545 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 5546 intel_crtc->cursor_width = width;
5547 intel_crtc->cursor_height = height;
5548
6b383a7f 5549 intel_crtc_update_cursor(crtc, true);
3f8bc370 5550
79e53945 5551 return 0;
e7b526bb 5552fail_unpin:
05394f39 5553 i915_gem_object_unpin(obj);
7f9872e0 5554fail_locked:
34b8686e 5555 mutex_unlock(&dev->struct_mutex);
bc9025bd 5556fail:
05394f39 5557 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 5558 return ret;
79e53945
JB		 5559}
5560
5561static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
5562{
79e53945 5563 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5564
cda4b7d3
CW		 5565 intel_crtc->cursor_x = x;
5566 intel_crtc->cursor_y = y;
652c393a 5567
6b383a7f 5568 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 5569
5570 return 0;
5571}
5572
5573/** Sets the color ramps on behalf of RandR */
5574void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
5575 u16 blue, int regno)
5576{
5577 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5578
5579 intel_crtc->lut_r[regno] = red >> 8;
5580 intel_crtc->lut_g[regno] = green >> 8;
5581 intel_crtc->lut_b[regno] = blue >> 8;
5582}
5583
b8c00ac5
DA		 5584void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
5585 u16 *blue, int regno)
5586{
5587 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5588
5589 *red = intel_crtc->lut_r[regno] << 8;
5590 *green = intel_crtc->lut_g[regno] << 8;
5591 *blue = intel_crtc->lut_b[regno] << 8;
5592}
5593
79e53945 5594static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 5595 u16 *blue, uint32_t start, uint32_t size)
79e53945 5596{
7203425a 5597 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 5598 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 5599
7203425a 5600 for (i = start; i < end; i++) {
79e53945
JB		 5601 intel_crtc->lut_r[i] = red[i] >> 8;
5602 intel_crtc->lut_g[i] = green[i] >> 8;
5603 intel_crtc->lut_b[i] = blue[i] >> 8;
5604 }
5605
5606 intel_crtc_load_lut(crtc);
5607}
5608
5609/**
5610 * Get a pipe with a simple mode set on it for doing load-based monitor
5611 * detection.
5612 *
5613 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 5614 * its requirements. The pipe will be connected to no other encoders.
79e53945 5615 *
c751ce4f 5616 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 5617 * configured for it. In the future, it could choose to temporarily disable
5618 * some outputs to free up a pipe for its use.
5619 *
5620 * \return crtc, or NULL if no pipes are available.
5621 */
5622
5623/* VESA 640x480x72Hz mode to set on the pipe */
5624static struct drm_display_mode load_detect_mode = {
5625 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
5626 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
5627};
5628
d2dff872
CW		 5629static struct drm_framebuffer *
5630intel_framebuffer_create(struct drm_device *dev,
308e5bcb 5631 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 5632 struct drm_i915_gem_object *obj)
5633{
5634 struct intel_framebuffer *intel_fb;
5635 int ret;
5636
5637 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5638 if (!intel_fb) {
5639 drm_gem_object_unreference_unlocked(&obj->base);
5640 return ERR_PTR(-ENOMEM);
5641 }
5642
5643 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
5644 if (ret) {
5645 drm_gem_object_unreference_unlocked(&obj->base);
5646 kfree(intel_fb);
5647 return ERR_PTR(ret);
5648 }
5649
5650 return &intel_fb->base;
5651}
5652
5653static u32
5654intel_framebuffer_pitch_for_width(int width, int bpp)
5655{
5656 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
5657 return ALIGN(pitch, 64);
5658}
5659
5660static u32
5661intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
5662{
5663 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
5664 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
5665}
5666
5667static struct drm_framebuffer *
5668intel_framebuffer_create_for_mode(struct drm_device *dev,
5669 struct drm_display_mode *mode,
5670 int depth, int bpp)
5671{
5672 struct drm_i915_gem_object *obj;
308e5bcb 5673 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 5674
5675 obj = i915_gem_alloc_object(dev,
5676 intel_framebuffer_size_for_mode(mode, bpp));
5677 if (obj == NULL)
5678 return ERR_PTR(-ENOMEM);
5679
5680 mode_cmd.width = mode->hdisplay;
5681 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 5682 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
5683 bpp);
5ca0c34a 5684 mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
d2dff872
CW		 5685
5686 return intel_framebuffer_create(dev, &mode_cmd, obj);
5687}
5688
5689static struct drm_framebuffer *
5690mode_fits_in_fbdev(struct drm_device *dev,
5691 struct drm_display_mode *mode)
5692{
5693 struct drm_i915_private *dev_priv = dev->dev_private;
5694 struct drm_i915_gem_object *obj;
5695 struct drm_framebuffer *fb;
5696
5697 if (dev_priv->fbdev == NULL)
5698 return NULL;
5699
5700 obj = dev_priv->fbdev->ifb.obj;
5701 if (obj == NULL)
5702 return NULL;
5703
5704 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 5705 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
5706 fb->bits_per_pixel))
d2dff872
CW		 5707 return NULL;
5708
01f2c773 5709 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 5710 return NULL;
5711
5712 return fb;
5713}
5714
d2434ab7 5715bool intel_get_load_detect_pipe(struct drm_connector *connector,
7173188d 5716 struct drm_display_mode *mode,
8261b191 5717 struct intel_load_detect_pipe *old)
79e53945
JB		 5718{
5719 struct intel_crtc *intel_crtc;
d2434ab7
DV		 5720 struct intel_encoder *intel_encoder =
5721 intel_attached_encoder(connector);
79e53945 5722 struct drm_crtc *possible_crtc;
4ef69c7a 5723 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 5724 struct drm_crtc *crtc = NULL;
5725 struct drm_device *dev = encoder->dev;
94352cf9 5726 struct drm_framebuffer *fb;
79e53945
JB		 5727 int i = -1;
5728
d2dff872
CW		 5729 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5730 connector->base.id, drm_get_connector_name(connector),
5731 encoder->base.id, drm_get_encoder_name(encoder));
5732
79e53945
JB		 5733 /*
5734 * Algorithm gets a little messy:
7a5e4805 5735 *
79e53945
JB		 5736 * - if the connector already has an assigned crtc, use it (but make
5737 * sure it's on first)
7a5e4805 5738 *
79e53945
JB		 5739 * - try to find the first unused crtc that can drive this connector,
5740 * and use that if we find one
79e53945
JB		 5741 */
5742
5743 /* See if we already have a CRTC for this connector */
5744 if (encoder->crtc) {
5745 crtc = encoder->crtc;
8261b191 5746
24218aac 5747 old->dpms_mode = connector->dpms;
8261b191
CW		 5748 old->load_detect_temp = false;
5749
5750 /* Make sure the crtc and connector are running */
24218aac
DV		 5751 if (connector->dpms != DRM_MODE_DPMS_ON)
5752 connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
8261b191 5753
7173188d 5754 return true;
79e53945
JB		 5755 }
5756
5757 /* Find an unused one (if possible) */
5758 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
5759 i++;
5760 if (!(encoder->possible_crtcs & (1 << i)))
5761 continue;
5762 if (!possible_crtc->enabled) {
5763 crtc = possible_crtc;
5764 break;
5765 }
79e53945
JB		 5766 }
5767
5768 /*
5769 * If we didn't find an unused CRTC, don't use any.
5770 */
5771 if (!crtc) {
7173188d
CW		 5772 DRM_DEBUG_KMS("no pipe available for load-detect\n");
5773 return false;
79e53945
JB		 5774 }
5775
5776 encoder->crtc = crtc;
c1c43977 5777 connector->encoder = encoder;
79e53945
JB		 5778
5779 intel_crtc = to_intel_crtc(crtc);
24218aac 5780 old->dpms_mode = connector->dpms;
8261b191 5781 old->load_detect_temp = true;
d2dff872 5782 old->release_fb = NULL;
79e53945 5783
6492711d
CW		 5784 if (!mode)
5785 mode = &load_detect_mode;
79e53945 5786
d2dff872
CW		 5787 /* We need a framebuffer large enough to accommodate all accesses
5788 * that the plane may generate whilst we perform load detection.
5789 * We can not rely on the fbcon either being present (we get called
5790 * during its initialisation to detect all boot displays, or it may
5791 * not even exist) or that it is large enough to satisfy the
5792 * requested mode.
5793 */
94352cf9
DV		 5794 fb = mode_fits_in_fbdev(dev, mode);
5795 if (fb == NULL) {
d2dff872 5796 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
94352cf9
DV		 5797 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
5798 old->release_fb = fb;
d2dff872
CW		 5799 } else
5800 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
94352cf9 5801 if (IS_ERR(fb)) {
d2dff872 5802 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
24218aac 5803 goto fail;
79e53945 5804 }
79e53945 5805
94352cf9 5806 if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6492711d 5807 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 5808 if (old->release_fb)
5809 old->release_fb->funcs->destroy(old->release_fb);
24218aac 5810 goto fail;
79e53945 5811 }
7173188d 5812
79e53945 5813 /* let the connector get through one full cycle before testing */
9d0498a2 5814 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 5815
7173188d 5816 return true;
24218aac
DV		 5817fail:
5818 connector->encoder = NULL;
5819 encoder->crtc = NULL;
24218aac 5820 return false;
79e53945
JB		 5821}
5822
d2434ab7 5823void intel_release_load_detect_pipe(struct drm_connector *connector,
8261b191 5824 struct intel_load_detect_pipe *old)
79e53945 5825{
d2434ab7
DV		 5826 struct intel_encoder *intel_encoder =
5827 intel_attached_encoder(connector);
4ef69c7a 5828 struct drm_encoder *encoder = &intel_encoder->base;
79e53945 5829 struct drm_device *dev = encoder->dev;
79e53945 5830
d2dff872
CW		 5831 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5832 connector->base.id, drm_get_connector_name(connector),
5833 encoder->base.id, drm_get_encoder_name(encoder));
5834
8261b191 5835 if (old->load_detect_temp) {
c1c43977 5836 connector->encoder = NULL;
24218aac 5837 encoder->crtc = NULL;
79e53945 5838 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 5839
5840 if (old->release_fb)
5841 old->release_fb->funcs->destroy(old->release_fb);
5842
0622a53c 5843 return;
79e53945
JB		 5844 }
5845
c751ce4f 5846 /* Switch crtc and encoder back off if necessary */
24218aac
DV		 5847 if (old->dpms_mode != DRM_MODE_DPMS_ON)
5848 connector->funcs->dpms(connector, old->dpms_mode);
79e53945
JB		 5849}
5850
5851/* Returns the clock of the currently programmed mode of the given pipe. */
5852static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
5853{
5854 struct drm_i915_private *dev_priv = dev->dev_private;
5855 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5856 int pipe = intel_crtc->pipe;
548f245b 5857 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 5858 u32 fp;
5859 intel_clock_t clock;
5860
5861 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 5862 fp = I915_READ(FP0(pipe));
79e53945 5863 else
39adb7a5 5864 fp = I915_READ(FP1(pipe));
79e53945
JB		 5865
5866 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 5867 if (IS_PINEVIEW(dev)) {
5868 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
5869 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 5870 } else {
5871 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
5872 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
5873 }
5874
a6c45cf0 5875 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 5876 if (IS_PINEVIEW(dev))
5877 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
5878 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 5879 else
5880 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 5881 DPLL_FPA01_P1_POST_DIV_SHIFT);
5882
5883 switch (dpll & DPLL_MODE_MASK) {
5884 case DPLLB_MODE_DAC_SERIAL:
5885 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
5886 5 : 10;
5887 break;
5888 case DPLLB_MODE_LVDS:
5889 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
5890 7 : 14;
5891 break;
5892 default:
28c97730 5893 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 5894 "mode\n", (int)(dpll & DPLL_MODE_MASK));
5895 return 0;
5896 }
5897
5898 /* XXX: Handle the 100Mhz refclk */
2177832f 5899 intel_clock(dev, 96000, &clock);
79e53945
JB		 5900 } else {
5901 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
5902
5903 if (is_lvds) {
5904 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
5905 DPLL_FPA01_P1_POST_DIV_SHIFT);
5906 clock.p2 = 14;
5907
5908 if ((dpll & PLL_REF_INPUT_MASK) ==
5909 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
5910 /* XXX: might not be 66MHz */
2177832f 5911 intel_clock(dev, 66000, &clock);
79e53945 5912 } else
2177832f 5913 intel_clock(dev, 48000, &clock);
79e53945
JB		 5914 } else {
5915 if (dpll & PLL_P1_DIVIDE_BY_TWO)
5916 clock.p1 = 2;
5917 else {
5918 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
5919 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
5920 }
5921 if (dpll & PLL_P2_DIVIDE_BY_4)
5922 clock.p2 = 4;
5923 else
5924 clock.p2 = 2;
5925
2177832f 5926 intel_clock(dev, 48000, &clock);
79e53945
JB		 5927 }
5928 }
5929
5930 /* XXX: It would be nice to validate the clocks, but we can't reuse
5931 * i830PllIsValid() because it relies on the xf86_config connector
5932 * configuration being accurate, which it isn't necessarily.
5933 */
5934
5935 return clock.dot;
5936}
5937
5938/** Returns the currently programmed mode of the given pipe. */
5939struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
5940 struct drm_crtc *crtc)
5941{
548f245b 5942 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 5943 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5944 int pipe = intel_crtc->pipe;
5945 struct drm_display_mode *mode;
548f245b
JB		 5946 int htot = I915_READ(HTOTAL(pipe));
5947 int hsync = I915_READ(HSYNC(pipe));
5948 int vtot = I915_READ(VTOTAL(pipe));
5949 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 5950
5951 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
5952 if (!mode)
5953 return NULL;
5954
5955 mode->clock = intel_crtc_clock_get(dev, crtc);
5956 mode->hdisplay = (htot & 0xffff) + 1;
5957 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
5958 mode->hsync_start = (hsync & 0xffff) + 1;
5959 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
5960 mode->vdisplay = (vtot & 0xffff) + 1;
5961 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
5962 mode->vsync_start = (vsync & 0xffff) + 1;
5963 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
5964
5965 drm_mode_set_name(mode);
79e53945
JB		 5966
5967 return mode;
5968}
5969
3dec0095 5970static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 5971{
5972 struct drm_device *dev = crtc->dev;
5973 drm_i915_private_t *dev_priv = dev->dev_private;
5974 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5975 int pipe = intel_crtc->pipe;
dbdc6479
JB		 5976 int dpll_reg = DPLL(pipe);
5977 int dpll;
652c393a 5978
bad720ff 5979 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 5980 return;
5981
5982 if (!dev_priv->lvds_downclock_avail)
5983 return;
5984
dbdc6479 5985 dpll = I915_READ(dpll_reg);
652c393a 5986 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 5987 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a 5988
8ac5a6d5 5989 assert_panel_unlocked(dev_priv, pipe);
652c393a
JB		 5990
5991 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
5992 I915_WRITE(dpll_reg, dpll);
9d0498a2 5993 intel_wait_for_vblank(dev, pipe);
dbdc6479 5994
652c393a
JB		 5995 dpll = I915_READ(dpll_reg);
5996 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 5997 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a 5998 }
652c393a
JB		 5999}
6000
6001static void intel_decrease_pllclock(struct drm_crtc *crtc)
6002{
6003 struct drm_device *dev = crtc->dev;
6004 drm_i915_private_t *dev_priv = dev->dev_private;
6005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
652c393a 6006
bad720ff 6007 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6008 return;
6009
6010 if (!dev_priv->lvds_downclock_avail)
6011 return;
6012
6013 /*
6014 * Since this is called by a timer, we should never get here in
6015 * the manual case.
6016 */
6017 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
dc257cf1
DV		 6018 int pipe = intel_crtc->pipe;
6019 int dpll_reg = DPLL(pipe);
6020 int dpll;
f6e5b160 6021
44d98a61 6022 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a 6023
8ac5a6d5 6024 assert_panel_unlocked(dev_priv, pipe);
652c393a 6025
dc257cf1 6026 dpll = I915_READ(dpll_reg);
652c393a
JB		 6027 dpll |= DISPLAY_RATE_SELECT_FPA1;
6028 I915_WRITE(dpll_reg, dpll);
9d0498a2 6029 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6030 dpll = I915_READ(dpll_reg);
6031 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6032 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6033 }
6034
6035}
6036
f047e395
CW		 6037void intel_mark_busy(struct drm_device *dev)
6038{
f047e395
CW		 6039 i915_update_gfx_val(dev->dev_private);
6040}
6041
6042void intel_mark_idle(struct drm_device *dev)
652c393a 6043{
f047e395
CW		 6044}
6045
6046void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6047{
6048 struct drm_device *dev = obj->base.dev;
652c393a 6049 struct drm_crtc *crtc;
652c393a
JB		 6050
6051 if (!i915_powersave)
6052 return;
6053
652c393a 6054 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
652c393a
JB		 6055 if (!crtc->fb)
6056 continue;
6057
f047e395
CW		 6058 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6059 intel_increase_pllclock(crtc);
652c393a 6060 }
652c393a
JB		 6061}
6062
f047e395 6063void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
652c393a 6064{
f047e395
CW		 6065 struct drm_device *dev = obj->base.dev;
6066 struct drm_crtc *crtc;
652c393a 6067
f047e395 6068 if (!i915_powersave)
acb87dfb
CW		 6069 return;
6070
652c393a
JB		 6071 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6072 if (!crtc->fb)
6073 continue;
6074
f047e395
CW		 6075 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6076 intel_decrease_pllclock(crtc);
652c393a
JB		 6077 }
6078}
6079
79e53945
JB		 6080static void intel_crtc_destroy(struct drm_crtc *crtc)
6081{
6082 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 6083 struct drm_device *dev = crtc->dev;
6084 struct intel_unpin_work *work;
6085 unsigned long flags;
6086
6087 spin_lock_irqsave(&dev->event_lock, flags);
6088 work = intel_crtc->unpin_work;
6089 intel_crtc->unpin_work = NULL;
6090 spin_unlock_irqrestore(&dev->event_lock, flags);
6091
6092 if (work) {
6093 cancel_work_sync(&work->work);
6094 kfree(work);
6095 }
79e53945
JB		 6096
6097 drm_crtc_cleanup(crtc);
67e77c5a 6098
79e53945
JB		 6099 kfree(intel_crtc);
6100}
6101
6b95a207
KH		 6102static void intel_unpin_work_fn(struct work_struct *__work)
6103{
6104 struct intel_unpin_work *work =
6105 container_of(__work, struct intel_unpin_work, work);
6106
6107 mutex_lock(&work->dev->struct_mutex);
1690e1eb 6108 intel_unpin_fb_obj(work->old_fb_obj);
05394f39
CW		 6109 drm_gem_object_unreference(&work->pending_flip_obj->base);
6110 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 6111
7782de3b 6112 intel_update_fbc(work->dev);
6b95a207
KH		 6113 mutex_unlock(&work->dev->struct_mutex);
6114 kfree(work);
6115}
6116
1afe3e9d 6117static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 6118 struct drm_crtc *crtc)
6b95a207
KH		 6119{
6120 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 6121 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6122 struct intel_unpin_work *work;
05394f39 6123 struct drm_i915_gem_object *obj;
6b95a207 6124 struct drm_pending_vblank_event *e;
49b14a5c 6125 struct timeval tnow, tvbl;
6b95a207
KH		 6126 unsigned long flags;
6127
6128 /* Ignore early vblank irqs */
6129 if (intel_crtc == NULL)
6130 return;
6131
49b14a5c
MK		 6132 do_gettimeofday(&tnow);
6133
6b95a207
KH		 6134 spin_lock_irqsave(&dev->event_lock, flags);
6135 work = intel_crtc->unpin_work;
6136 if (work == NULL || !work->pending) {
6137 spin_unlock_irqrestore(&dev->event_lock, flags);
6138 return;
6139 }
6140
6141 intel_crtc->unpin_work = NULL;
6b95a207
KH		 6142
6143 if (work->event) {
6144 e = work->event;
49b14a5c 6145 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 6146
6147 /* Called before vblank count and timestamps have
6148 * been updated for the vblank interval of flip
6149 * completion? Need to increment vblank count and
6150 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 6151 * to account for this. We assume this happened if we
6152 * get called over 0.9 frame durations after the last
6153 * timestamped vblank.
6154 *
6155 * This calculation can not be used with vrefresh rates
6156 * below 5Hz (10Hz to be on the safe side) without
6157 * promoting to 64 integers.
0af7e4df 6158 */
49b14a5c
MK		 6159 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
6160 9 * crtc->framedur_ns) {
0af7e4df 6161 e->event.sequence++;
49b14a5c
MK		 6162 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
6163 crtc->framedur_ns);
0af7e4df
MK		 6164 }
6165
49b14a5c
MK		 6166 e->event.tv_sec = tvbl.tv_sec;
6167 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 6168
6b95a207
KH		 6169 list_add_tail(&e->base.link,
6170 &e->base.file_priv->event_list);
6171 wake_up_interruptible(&e->base.file_priv->event_wait);
6172 }
6173
0af7e4df
MK		 6174 drm_vblank_put(dev, intel_crtc->pipe);
6175
6b95a207
KH		 6176 spin_unlock_irqrestore(&dev->event_lock, flags);
6177
05394f39 6178 obj = work->old_fb_obj;
d9e86c0e 6179
e59f2bac 6180 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 6181 &obj->pending_flip.counter);
6182 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 6183 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 6184
6b95a207 6185 schedule_work(&work->work);
e5510fac
JB		 6186
6187 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 6188}
6189
1afe3e9d
JB		 6190void intel_finish_page_flip(struct drm_device *dev, int pipe)
6191{
6192 drm_i915_private_t *dev_priv = dev->dev_private;
6193 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6194
49b14a5c 6195 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6196}
6197
6198void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6199{
6200 drm_i915_private_t *dev_priv = dev->dev_private;
6201 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6202
49b14a5c 6203 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 6204}
6205
6b95a207
KH		 6206void intel_prepare_page_flip(struct drm_device *dev, int plane)
6207{
6208 drm_i915_private_t *dev_priv = dev->dev_private;
6209 struct intel_crtc *intel_crtc =
6210 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6211 unsigned long flags;
6212
6213 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 6214 if (intel_crtc->unpin_work) {
4e5359cd
SF		 6215 if ((++intel_crtc->unpin_work->pending) > 1)
6216 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 6217 } else {
6218 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6219 }
6b95a207
KH		 6220 spin_unlock_irqrestore(&dev->event_lock, flags);
6221}
6222
8c9f3aaf
JB		 6223static int intel_gen2_queue_flip(struct drm_device *dev,
6224 struct drm_crtc *crtc,
6225 struct drm_framebuffer *fb,
6226 struct drm_i915_gem_object *obj)
6227{
6228 struct drm_i915_private *dev_priv = dev->dev_private;
6229 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6230 u32 flip_mask;
6d90c952 6231 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6232 int ret;
6233
6d90c952 6234 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6235 if (ret)
83d4092b 6236 goto err;
8c9f3aaf 6237
6d90c952 6238 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6239 if (ret)
83d4092b 6240 goto err_unpin;
8c9f3aaf
JB		 6241
6242 /* Can't queue multiple flips, so wait for the previous
6243 * one to finish before executing the next.
6244 */
6245 if (intel_crtc->plane)
6246 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6247 else
6248 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6249 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6250 intel_ring_emit(ring, MI_NOOP);
6251 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6252 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6253 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6254 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6255 intel_ring_emit(ring, 0); /* aux display base address, unused */
6256 intel_ring_advance(ring);
83d4092b
CW		 6257 return 0;
6258
6259err_unpin:
6260 intel_unpin_fb_obj(obj);
6261err:
8c9f3aaf
JB		 6262 return ret;
6263}
6264
6265static int intel_gen3_queue_flip(struct drm_device *dev,
6266 struct drm_crtc *crtc,
6267 struct drm_framebuffer *fb,
6268 struct drm_i915_gem_object *obj)
6269{
6270 struct drm_i915_private *dev_priv = dev->dev_private;
6271 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
8c9f3aaf 6272 u32 flip_mask;
6d90c952 6273 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6274 int ret;
6275
6d90c952 6276 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6277 if (ret)
83d4092b 6278 goto err;
8c9f3aaf 6279
6d90c952 6280 ret = intel_ring_begin(ring, 6);
8c9f3aaf 6281 if (ret)
83d4092b 6282 goto err_unpin;
8c9f3aaf
JB		 6283
6284 if (intel_crtc->plane)
6285 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6286 else
6287 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6d90c952
DV		 6288 intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6289 intel_ring_emit(ring, MI_NOOP);
6290 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6291 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6292 intel_ring_emit(ring, fb->pitches[0]);
e506a0c6 6293 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6d90c952
DV		 6294 intel_ring_emit(ring, MI_NOOP);
6295
6296 intel_ring_advance(ring);
83d4092b
CW		 6297 return 0;
6298
6299err_unpin:
6300 intel_unpin_fb_obj(obj);
6301err:
8c9f3aaf
JB		 6302 return ret;
6303}
6304
6305static int intel_gen4_queue_flip(struct drm_device *dev,
6306 struct drm_crtc *crtc,
6307 struct drm_framebuffer *fb,
6308 struct drm_i915_gem_object *obj)
6309{
6310 struct drm_i915_private *dev_priv = dev->dev_private;
6311 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6312 uint32_t pf, pipesrc;
6d90c952 6313 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6314 int ret;
6315
6d90c952 6316 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6317 if (ret)
83d4092b 6318 goto err;
8c9f3aaf 6319
6d90c952 6320 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6321 if (ret)
83d4092b 6322 goto err_unpin;
8c9f3aaf
JB		 6323
6324 /* i965+ uses the linear or tiled offsets from the
6325 * Display Registers (which do not change across a page-flip)
6326 * so we need only reprogram the base address.
6327 */
6d90c952
DV		 6328 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6329 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6330 intel_ring_emit(ring, fb->pitches[0]);
c2c75131
DV		 6331 intel_ring_emit(ring,
6332 (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6333 obj->tiling_mode);
8c9f3aaf
JB		 6334
6335 /* XXX Enabling the panel-fitter across page-flip is so far
6336 * untested on non-native modes, so ignore it for now.
6337 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6338 */
6339 pf = 0;
6340 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6341 intel_ring_emit(ring, pf | pipesrc);
6342 intel_ring_advance(ring);
83d4092b
CW		 6343 return 0;
6344
6345err_unpin:
6346 intel_unpin_fb_obj(obj);
6347err:
8c9f3aaf
JB		 6348 return ret;
6349}
6350
6351static int intel_gen6_queue_flip(struct drm_device *dev,
6352 struct drm_crtc *crtc,
6353 struct drm_framebuffer *fb,
6354 struct drm_i915_gem_object *obj)
6355{
6356 struct drm_i915_private *dev_priv = dev->dev_private;
6357 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6d90c952 6358 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
8c9f3aaf
JB		 6359 uint32_t pf, pipesrc;
6360 int ret;
6361
6d90c952 6362 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
8c9f3aaf 6363 if (ret)
83d4092b 6364 goto err;
8c9f3aaf 6365
6d90c952 6366 ret = intel_ring_begin(ring, 4);
8c9f3aaf 6367 if (ret)
83d4092b 6368 goto err_unpin;
8c9f3aaf 6369
6d90c952
DV		 6370 intel_ring_emit(ring, MI_DISPLAY_FLIP |
6371 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6372 intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
c2c75131 6373 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
8c9f3aaf 6374
dc257cf1
DV		 6375 /* Contrary to the suggestions in the documentation,
6376 * "Enable Panel Fitter" does not seem to be required when page
6377 * flipping with a non-native mode, and worse causes a normal
6378 * modeset to fail.
6379 * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
6380 */
6381 pf = 0;
8c9f3aaf 6382 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6d90c952
DV		 6383 intel_ring_emit(ring, pf | pipesrc);
6384 intel_ring_advance(ring);
83d4092b
CW		 6385 return 0;
6386
6387err_unpin:
6388 intel_unpin_fb_obj(obj);
6389err:
8c9f3aaf
JB		 6390 return ret;
6391}
6392
7c9017e5
JB		 6393/*
6394 * On gen7 we currently use the blit ring because (in early silicon at least)
6395 * the render ring doesn't give us interrpts for page flip completion, which
6396 * means clients will hang after the first flip is queued. Fortunately the
6397 * blit ring generates interrupts properly, so use it instead.
6398 */
6399static int intel_gen7_queue_flip(struct drm_device *dev,
6400 struct drm_crtc *crtc,
6401 struct drm_framebuffer *fb,
6402 struct drm_i915_gem_object *obj)
6403{
6404 struct drm_i915_private *dev_priv = dev->dev_private;
6405 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6406 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
cb05d8de 6407 uint32_t plane_bit = 0;
7c9017e5
JB		 6408 int ret;
6409
6410 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6411 if (ret)
83d4092b 6412 goto err;
7c9017e5 6413
cb05d8de
DV		 6414 switch(intel_crtc->plane) {
6415 case PLANE_A:
6416 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
6417 break;
6418 case PLANE_B:
6419 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
6420 break;
6421 case PLANE_C:
6422 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
6423 break;
6424 default:
6425 WARN_ONCE(1, "unknown plane in flip command\n");
6426 ret = -ENODEV;
ab3951eb 6427 goto err_unpin;
cb05d8de
DV		 6428 }
6429
7c9017e5
JB		 6430 ret = intel_ring_begin(ring, 4);
6431 if (ret)
83d4092b 6432 goto err_unpin;
7c9017e5 6433
cb05d8de 6434 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
01f2c773 6435 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
c2c75131 6436 intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7c9017e5
JB		 6437 intel_ring_emit(ring, (MI_NOOP));
6438 intel_ring_advance(ring);
83d4092b
CW		 6439 return 0;
6440
6441err_unpin:
6442 intel_unpin_fb_obj(obj);
6443err:
7c9017e5
JB		 6444 return ret;
6445}
6446
8c9f3aaf
JB		 6447static int intel_default_queue_flip(struct drm_device *dev,
6448 struct drm_crtc *crtc,
6449 struct drm_framebuffer *fb,
6450 struct drm_i915_gem_object *obj)
6451{
6452 return -ENODEV;
6453}
6454
6b95a207
KH		 6455static int intel_crtc_page_flip(struct drm_crtc *crtc,
6456 struct drm_framebuffer *fb,
6457 struct drm_pending_vblank_event *event)
6458{
6459 struct drm_device *dev = crtc->dev;
6460 struct drm_i915_private *dev_priv = dev->dev_private;
6461 struct intel_framebuffer *intel_fb;
05394f39 6462 struct drm_i915_gem_object *obj;
6b95a207
KH		 6463 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6464 struct intel_unpin_work *work;
8c9f3aaf 6465 unsigned long flags;
52e68630 6466 int ret;
6b95a207 6467
e6a595d2
VS		 6468 /* Can't change pixel format via MI display flips. */
6469 if (fb->pixel_format != crtc->fb->pixel_format)
6470 return -EINVAL;
6471
6472 /*
6473 * TILEOFF/LINOFF registers can't be changed via MI display flips.
6474 * Note that pitch changes could also affect these register.
6475 */
6476 if (INTEL_INFO(dev)->gen > 3 &&
6477 (fb->offsets[0] != crtc->fb->offsets[0] ||
6478 fb->pitches[0] != crtc->fb->pitches[0]))
6479 return -EINVAL;
6480
6b95a207
KH		 6481 work = kzalloc(sizeof *work, GFP_KERNEL);
6482 if (work == NULL)
6483 return -ENOMEM;
6484
6b95a207
KH		 6485 work->event = event;
6486 work->dev = crtc->dev;
6487 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 6488 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 6489 INIT_WORK(&work->work, intel_unpin_work_fn);
6490
7317c75e
JB		 6491 ret = drm_vblank_get(dev, intel_crtc->pipe);
6492 if (ret)
6493 goto free_work;
6494
6b95a207
KH		 6495 /* We borrow the event spin lock for protecting unpin_work */
6496 spin_lock_irqsave(&dev->event_lock, flags);
6497 if (intel_crtc->unpin_work) {
6498 spin_unlock_irqrestore(&dev->event_lock, flags);
6499 kfree(work);
7317c75e 6500 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 6501
6502 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 6503 return -EBUSY;
6504 }
6505 intel_crtc->unpin_work = work;
6506 spin_unlock_irqrestore(&dev->event_lock, flags);
6507
6508 intel_fb = to_intel_framebuffer(fb);
6509 obj = intel_fb->obj;
6510
79158103
CW		 6511 ret = i915_mutex_lock_interruptible(dev);
6512 if (ret)
6513 goto cleanup;
6b95a207 6514
75dfca80 6515 /* Reference the objects for the scheduled work. */
05394f39
CW		 6516 drm_gem_object_reference(&work->old_fb_obj->base);
6517 drm_gem_object_reference(&obj->base);
6b95a207
KH		 6518
6519 crtc->fb = fb;
96b099fd 6520
e1f99ce6 6521 work->pending_flip_obj = obj;
e1f99ce6 6522
4e5359cd
SF		 6523 work->enable_stall_check = true;
6524
e1f99ce6
CW		 6525 /* Block clients from rendering to the new back buffer until
6526 * the flip occurs and the object is no longer visible.
6527 */
05394f39 6528 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 6529
8c9f3aaf
JB		 6530 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
6531 if (ret)
6532 goto cleanup_pending;
6b95a207 6533
7782de3b 6534 intel_disable_fbc(dev);
f047e395 6535 intel_mark_fb_busy(obj);
6b95a207
KH		 6536 mutex_unlock(&dev->struct_mutex);
6537
e5510fac
JB		 6538 trace_i915_flip_request(intel_crtc->plane, obj);
6539
6b95a207 6540 return 0;
96b099fd 6541
8c9f3aaf
JB		 6542cleanup_pending:
6543 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 6544 drm_gem_object_unreference(&work->old_fb_obj->base);
6545 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 6546 mutex_unlock(&dev->struct_mutex);
6547
79158103 6548cleanup:
96b099fd
CW		 6549 spin_lock_irqsave(&dev->event_lock, flags);
6550 intel_crtc->unpin_work = NULL;
6551 spin_unlock_irqrestore(&dev->event_lock, flags);
6552
7317c75e
JB		 6553 drm_vblank_put(dev, intel_crtc->pipe);
6554free_work:
96b099fd
CW		 6555 kfree(work);
6556
6557 return ret;
6b95a207
KH		 6558}
6559
f6e5b160 6560static struct drm_crtc_helper_funcs intel_helper_funcs = {
f6e5b160
CW		 6561 .mode_set_base_atomic = intel_pipe_set_base_atomic,
6562 .load_lut = intel_crtc_load_lut,
6563 .disable = intel_crtc_disable,
6564};
6565
6ed0f796
DV		 6566bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
6567{
6568 struct intel_encoder *other_encoder;
6569 struct drm_crtc *crtc = &encoder->new_crtc->base;
6570
6571 if (WARN_ON(!crtc))
6572 return false;
6573
6574 list_for_each_entry(other_encoder,
6575 &crtc->dev->mode_config.encoder_list,
6576 base.head) {
6577
6578 if (&other_encoder->new_crtc->base != crtc ||
6579 encoder == other_encoder)
6580 continue;
6581 else
6582 return true;
6583 }
6584
6585 return false;
6586}
6587
50f56119
DV		 6588static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
6589 struct drm_crtc *crtc)
6590{
6591 struct drm_device *dev;
6592 struct drm_crtc *tmp;
6593 int crtc_mask = 1;
6594
6595 WARN(!crtc, "checking null crtc?\n");
6596
6597 dev = crtc->dev;
6598
6599 list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
6600 if (tmp == crtc)
6601 break;
6602 crtc_mask <<= 1;
6603 }
6604
6605 if (encoder->possible_crtcs & crtc_mask)
6606 return true;
6607 return false;
6608}
6609
a6778b3c
DV		 6610static void
6611intel_crtc_prepare_encoders(struct drm_device *dev)
6612{
821112aa 6613 struct intel_encoder *encoder;
a6778b3c 6614
821112aa 6615 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
a6778b3c 6616 /* Disable unused encoders */
821112aa
DV		 6617 if (encoder->base.crtc == NULL)
6618 encoder->disable(encoder);
a6778b3c
DV		 6619 }
6620}
6621
9a935856
DV		 6622/**
6623 * intel_modeset_update_staged_output_state
6624 *
6625 * Updates the staged output configuration state, e.g. after we've read out the
6626 * current hw state.
6627 */
6628static void intel_modeset_update_staged_output_state(struct drm_device *dev)
6629{
6630 struct intel_encoder *encoder;
6631 struct intel_connector *connector;
6632
6633 list_for_each_entry(connector, &dev->mode_config.connector_list,
6634 base.head) {
6635 connector->new_encoder =
6636 to_intel_encoder(connector->base.encoder);
6637 }
6638
6639 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6640 base.head) {
6641 encoder->new_crtc =
6642 to_intel_crtc(encoder->base.crtc);
6643 }
6644}
6645
6646/**
6647 * intel_modeset_commit_output_state
6648 *
6649 * This function copies the stage display pipe configuration to the real one.
6650 */
6651static void intel_modeset_commit_output_state(struct drm_device *dev)
6652{
6653 struct intel_encoder *encoder;
6654 struct intel_connector *connector;
6655
6656 list_for_each_entry(connector, &dev->mode_config.connector_list,
6657 base.head) {
6658 connector->base.encoder = &connector->new_encoder->base;
6659 }
6660
6661 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6662 base.head) {
6663 encoder->base.crtc = &encoder->new_crtc->base;
6664 }
6665}
6666
7758a113
DV		 6667static struct drm_display_mode *
6668intel_modeset_adjusted_mode(struct drm_crtc *crtc,
6669 struct drm_display_mode *mode)
6670{
6671 struct drm_device *dev = crtc->dev;
6672 struct drm_display_mode *adjusted_mode;
6673 struct drm_encoder_helper_funcs *encoder_funcs;
6674 struct intel_encoder *encoder;
6675
6676 adjusted_mode = drm_mode_duplicate(dev, mode);
6677 if (!adjusted_mode)
6678 return ERR_PTR(-ENOMEM);
6679
6680 /* Pass our mode to the connectors and the CRTC to give them a chance to
6681 * adjust it according to limitations or connector properties, and also
6682 * a chance to reject the mode entirely.
6683 */
6684 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6685 base.head) {
6686
6687 if (&encoder->new_crtc->base != crtc)
6688 continue;
6689 encoder_funcs = encoder->base.helper_private;
6690 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
6691 adjusted_mode))) {
6692 DRM_DEBUG_KMS("Encoder fixup failed\n");
6693 goto fail;
6694 }
6695 }
6696
6697 if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
6698 DRM_DEBUG_KMS("CRTC fixup failed\n");
6699 goto fail;
6700 }
6701 DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
6702
6703 return adjusted_mode;
6704fail:
6705 drm_mode_destroy(dev, adjusted_mode);
6706 return ERR_PTR(-EINVAL);
6707}
6708
a6778b3c
DV		 6709bool intel_set_mode(struct drm_crtc *crtc,
6710 struct drm_display_mode *mode,
94352cf9 6711 int x, int y, struct drm_framebuffer *fb)
a6778b3c
DV		 6712{
6713 struct drm_device *dev = crtc->dev;
dbf2b54e 6714 drm_i915_private_t *dev_priv = dev->dev_private;
a6778b3c 6715 struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
a6778b3c 6716 struct drm_encoder_helper_funcs *encoder_funcs;
a6778b3c
DV		 6717 struct drm_encoder *encoder;
6718 bool ret = true;
6719
87f1faa6
DV		 6720 intel_modeset_commit_output_state(dev);
6721
a6778b3c 6722 crtc->enabled = drm_helper_crtc_in_use(crtc);
87f1faa6
DV		 6723 if (!crtc->enabled) {
6724 drm_helper_disable_unused_functions(dev);
a6778b3c 6725 return true;
87f1faa6 6726 }
a6778b3c 6727
a6778b3c
DV		 6728
6729 saved_hwmode = crtc->hwmode;
6730 saved_mode = crtc->mode;
a6778b3c 6731
7758a113
DV		 6732 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
6733 if (IS_ERR(adjusted_mode)) {
6734 return false;
a6778b3c 6735 }
a6778b3c 6736
a6778b3c
DV		 6737 intel_crtc_prepare_encoders(dev);
6738
dbf2b54e 6739 dev_priv->display.crtc_disable(crtc);
a6778b3c 6740
7758a113
DV		 6741 crtc->mode = *mode;
6742
a6778b3c
DV		 6743 /* Set up the DPLL and any encoders state that needs to adjust or depend
6744 * on the DPLL.
6745 */
94352cf9 6746 ret = !intel_crtc_mode_set(crtc, mode, adjusted_mode, x, y, fb);
a6778b3c
DV		 6747 if (!ret)
6748 goto done;
6749
6750 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
6751
6752 if (encoder->crtc != crtc)
6753 continue;
6754
6755 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
6756 encoder->base.id, drm_get_encoder_name(encoder),
6757 mode->base.id, mode->name);
6758 encoder_funcs = encoder->helper_private;
6759 encoder_funcs->mode_set(encoder, mode, adjusted_mode);
6760 }
6761
94352cf9
DV		 6762 crtc->x = x;
6763 crtc->y = y;
6764
a6778b3c 6765 /* Now enable the clocks, plane, pipe, and connectors that we set up. */
dbf2b54e 6766 dev_priv->display.crtc_enable(crtc);
a6778b3c 6767
a6778b3c
DV		 6768 /* Store real post-adjustment hardware mode. */
6769 crtc->hwmode = *adjusted_mode;
6770
6771 /* Calculate and store various constants which
6772 * are later needed by vblank and swap-completion
6773 * timestamping. They are derived from true hwmode.
6774 */
6775 drm_calc_timestamping_constants(crtc);
6776
6777 /* FIXME: add subpixel order */
6778done:
6779 drm_mode_destroy(dev, adjusted_mode);
6780 if (!ret) {
6781 crtc->hwmode = saved_hwmode;
6782 crtc->mode = saved_mode;
a6778b3c
DV		 6783 }
6784
6785 return ret;
6786}
6787
d9e55608
DV		 6788static void intel_set_config_free(struct intel_set_config *config)
6789{
6790 if (!config)
6791 return;
6792
1aa4b628
DV		 6793 kfree(config->save_connector_encoders);
6794 kfree(config->save_encoder_crtcs);
d9e55608
DV		 6795 kfree(config);
6796}
6797
85f9eb71
DV		 6798static int intel_set_config_save_state(struct drm_device *dev,
6799 struct intel_set_config *config)
6800{
85f9eb71
DV		 6801 struct drm_encoder *encoder;
6802 struct drm_connector *connector;
6803 int count;
6804
1aa4b628
DV		 6805 config->save_encoder_crtcs =
6806 kcalloc(dev->mode_config.num_encoder,
6807 sizeof(struct drm_crtc *), GFP_KERNEL);
6808 if (!config->save_encoder_crtcs)
85f9eb71
DV		 6809 return -ENOMEM;
6810
1aa4b628
DV		 6811 config->save_connector_encoders =
6812 kcalloc(dev->mode_config.num_connector,
6813 sizeof(struct drm_encoder *), GFP_KERNEL);
6814 if (!config->save_connector_encoders)
85f9eb71
DV		 6815 return -ENOMEM;
6816
6817 /* Copy data. Note that driver private data is not affected.
6818 * Should anything bad happen only the expected state is
6819 * restored, not the drivers personal bookkeeping.
6820 */
85f9eb71
DV		 6821 count = 0;
6822 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1aa4b628 6823 config->save_encoder_crtcs[count++] = encoder->crtc;
85f9eb71
DV		 6824 }
6825
6826 count = 0;
6827 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1aa4b628 6828 config->save_connector_encoders[count++] = connector->encoder;
85f9eb71
DV		 6829 }
6830
6831 return 0;
6832}
6833
6834static void intel_set_config_restore_state(struct drm_device *dev,
6835 struct intel_set_config *config)
6836{
9a935856
DV		 6837 struct intel_encoder *encoder;
6838 struct intel_connector *connector;
85f9eb71
DV		 6839 int count;
6840
85f9eb71 6841 count = 0;
9a935856
DV		 6842 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
6843 encoder->new_crtc =
6844 to_intel_crtc(config->save_encoder_crtcs[count++]);
85f9eb71
DV		 6845 }
6846
6847 count = 0;
9a935856
DV		 6848 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
6849 connector->new_encoder =
6850 to_intel_encoder(config->save_connector_encoders[count++]);
85f9eb71
DV		 6851 }
6852}
6853
5e2b584e
DV		 6854static void
6855intel_set_config_compute_mode_changes(struct drm_mode_set *set,
6856 struct intel_set_config *config)
6857{
6858
6859 /* We should be able to check here if the fb has the same properties
6860 * and then just flip_or_move it */
6861 if (set->crtc->fb != set->fb) {
6862 /* If we have no fb then treat it as a full mode set */
6863 if (set->crtc->fb == NULL) {
6864 DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
6865 config->mode_changed = true;
6866 } else if (set->fb == NULL) {
6867 config->mode_changed = true;
6868 } else if (set->fb->depth != set->crtc->fb->depth) {
6869 config->mode_changed = true;
6870 } else if (set->fb->bits_per_pixel !=
6871 set->crtc->fb->bits_per_pixel) {
6872 config->mode_changed = true;
6873 } else
6874 config->fb_changed = true;
6875 }
6876
835c5873 6877 if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
5e2b584e
DV		 6878 config->fb_changed = true;
6879
6880 if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
6881 DRM_DEBUG_KMS("modes are different, full mode set\n");
6882 drm_mode_debug_printmodeline(&set->crtc->mode);
6883 drm_mode_debug_printmodeline(set->mode);
6884 config->mode_changed = true;
6885 }
6886}
6887
2e431051 6888static int
9a935856
DV		 6889intel_modeset_stage_output_state(struct drm_device *dev,
6890 struct drm_mode_set *set,
6891 struct intel_set_config *config)
50f56119 6892{
85f9eb71 6893 struct drm_crtc *new_crtc;
9a935856
DV		 6894 struct intel_connector *connector;
6895 struct intel_encoder *encoder;
2e431051 6896 int count, ro;
50f56119 6897
9a935856
DV		 6898 /* The upper layers ensure that we either disabl a crtc or have a list
6899 * of connectors. For paranoia, double-check this. */
6900 WARN_ON(!set->fb && (set->num_connectors != 0));
6901 WARN_ON(set->fb && (set->num_connectors == 0));
6902
50f56119 6903 count = 0;
9a935856
DV		 6904 list_for_each_entry(connector, &dev->mode_config.connector_list,
6905 base.head) {
6906 /* Otherwise traverse passed in connector list and get encoders
6907 * for them. */
50f56119 6908 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856
DV		 6909 if (set->connectors[ro] == &connector->base) {
6910 connector->new_encoder = connector->encoder;
50f56119
DV		 6911 break;
6912 }
6913 }
6914
9a935856
DV		 6915 /* If we disable the crtc, disable all its connectors. Also, if
6916 * the connector is on the changing crtc but not on the new
6917 * connector list, disable it. */
6918 if ((!set->fb || ro == set->num_connectors) &&
6919 connector->base.encoder &&
6920 connector->base.encoder->crtc == set->crtc) {
6921 connector->new_encoder = NULL;
6922
6923 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
6924 connector->base.base.id,
6925 drm_get_connector_name(&connector->base));
6926 }
6927
6928
6929 if (&connector->new_encoder->base != connector->base.encoder) {
50f56119 6930 DRM_DEBUG_KMS("encoder changed, full mode switch\n");
5e2b584e 6931 config->mode_changed = true;
50f56119 6932 }
9a935856
DV		 6933
6934 /* Disable all disconnected encoders. */
6935 if (connector->base.status == connector_status_disconnected)
6936 connector->new_encoder = NULL;
50f56119 6937 }
9a935856 6938 /* connector->new_encoder is now updated for all connectors. */
50f56119 6939
9a935856 6940 /* Update crtc of enabled connectors. */
50f56119 6941 count = 0;
9a935856
DV		 6942 list_for_each_entry(connector, &dev->mode_config.connector_list,
6943 base.head) {
6944 if (!connector->new_encoder)
50f56119
DV		 6945 continue;
6946
9a935856 6947 new_crtc = connector->new_encoder->base.crtc;
50f56119
DV		 6948
6949 for (ro = 0; ro < set->num_connectors; ro++) {
9a935856 6950 if (set->connectors[ro] == &connector->base)
50f56119
DV		 6951 new_crtc = set->crtc;
6952 }
6953
6954 /* Make sure the new CRTC will work with the encoder */
9a935856
DV		 6955 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
6956 new_crtc)) {
5e2b584e 6957 return -EINVAL;
50f56119 6958 }
9a935856
DV		 6959 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
6960
6961 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
6962 connector->base.base.id,
6963 drm_get_connector_name(&connector->base),
6964 new_crtc->base.id);
6965 }
6966
6967 /* Check for any encoders that needs to be disabled. */
6968 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
6969 base.head) {
6970 list_for_each_entry(connector,
6971 &dev->mode_config.connector_list,
6972 base.head) {
6973 if (connector->new_encoder == encoder) {
6974 WARN_ON(!connector->new_encoder->new_crtc);
6975
6976 goto next_encoder;
6977 }
6978 }
6979 encoder->new_crtc = NULL;
6980next_encoder:
6981 /* Only now check for crtc changes so we don't miss encoders
6982 * that will be disabled. */
6983 if (&encoder->new_crtc->base != encoder->base.crtc) {
50f56119 6984 DRM_DEBUG_KMS("crtc changed, full mode switch\n");
5e2b584e 6985 config->mode_changed = true;
50f56119
DV		 6986 }
6987 }
9a935856 6988 /* Now we've also updated encoder->new_crtc for all encoders. */
50f56119 6989
2e431051
DV		 6990 return 0;
6991}
6992
6993static int intel_crtc_set_config(struct drm_mode_set *set)
6994{
6995 struct drm_device *dev;
2e431051
DV		 6996 struct drm_mode_set save_set;
6997 struct intel_set_config *config;
6998 int ret;
6999 int i;
7000
8d3e375e
DV		 7001 BUG_ON(!set);
7002 BUG_ON(!set->crtc);
7003 BUG_ON(!set->crtc->helper_private);
2e431051
DV		 7004
7005 if (!set->mode)
7006 set->fb = NULL;
7007
431e50f7
DV		 7008 /* The fb helper likes to play gross jokes with ->mode_set_config.
7009 * Unfortunately the crtc helper doesn't do much at all for this case,
7010 * so we have to cope with this madness until the fb helper is fixed up. */
7011 if (set->fb && set->num_connectors == 0)
7012 return 0;
7013
2e431051
DV		 7014 if (set->fb) {
7015 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7016 set->crtc->base.id, set->fb->base.id,
7017 (int)set->num_connectors, set->x, set->y);
7018 } else {
7019 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
2e431051
DV		 7020 }
7021
7022 dev = set->crtc->dev;
7023
7024 ret = -ENOMEM;
7025 config = kzalloc(sizeof(*config), GFP_KERNEL);
7026 if (!config)
7027 goto out_config;
7028
7029 ret = intel_set_config_save_state(dev, config);
7030 if (ret)
7031 goto out_config;
7032
7033 save_set.crtc = set->crtc;
7034 save_set.mode = &set->crtc->mode;
7035 save_set.x = set->crtc->x;
7036 save_set.y = set->crtc->y;
7037 save_set.fb = set->crtc->fb;
7038
7039 /* Compute whether we need a full modeset, only an fb base update or no
7040 * change at all. In the future we might also check whether only the
7041 * mode changed, e.g. for LVDS where we only change the panel fitter in
7042 * such cases. */
7043 intel_set_config_compute_mode_changes(set, config);
7044
9a935856 7045 ret = intel_modeset_stage_output_state(dev, set, config);
2e431051
DV		 7046 if (ret)
7047 goto fail;
7048
5e2b584e 7049 if (config->mode_changed) {
87f1faa6 7050 if (set->mode) {
50f56119
DV		 7051 DRM_DEBUG_KMS("attempting to set mode from"
7052 " userspace\n");
7053 drm_mode_debug_printmodeline(set->mode);
87f1faa6
DV		 7054 }
7055
7056 if (!intel_set_mode(set->crtc, set->mode,
7057 set->x, set->y, set->fb)) {
7058 DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7059 set->crtc->base.id);
7060 ret = -EINVAL;
7061 goto fail;
7062 }
7063
7064 if (set->crtc->enabled) {
50f56119
DV		 7065 DRM_DEBUG_KMS("Setting connector DPMS state to on\n");
7066 for (i = 0; i < set->num_connectors; i++) {
7067 DRM_DEBUG_KMS("\t[CONNECTOR:%d:%s] set DPMS on\n", set->connectors[i]->base.id,
7068 drm_get_connector_name(set->connectors[i]));
7069 set->connectors[i]->funcs->dpms(set->connectors[i], DRM_MODE_DPMS_ON);
7070 }
7071 }
5e2b584e 7072 } else if (config->fb_changed) {
4f660f49 7073 ret = intel_pipe_set_base(set->crtc,
94352cf9 7074 set->x, set->y, set->fb);
50f56119
DV		 7075 }
7076
d9e55608
DV		 7077 intel_set_config_free(config);
7078
50f56119
DV		 7079 return 0;
7080
7081fail:
85f9eb71 7082 intel_set_config_restore_state(dev, config);
50f56119
DV		 7083
7084 /* Try to restore the config */
5e2b584e 7085 if (config->mode_changed &&
a6778b3c
DV		 7086 !intel_set_mode(save_set.crtc, save_set.mode,
7087 save_set.x, save_set.y, save_set.fb))
50f56119
DV		 7088 DRM_ERROR("failed to restore config after modeset failure\n");
7089
d9e55608
DV		 7090out_config:
7091 intel_set_config_free(config);
50f56119
DV		 7092 return ret;
7093}
7094
f6e5b160 7095static const struct drm_crtc_funcs intel_crtc_funcs = {
f6e5b160
CW		 7096 .cursor_set = intel_crtc_cursor_set,
7097 .cursor_move = intel_crtc_cursor_move,
7098 .gamma_set = intel_crtc_gamma_set,
50f56119 7099 .set_config = intel_crtc_set_config,
f6e5b160
CW		 7100 .destroy = intel_crtc_destroy,
7101 .page_flip = intel_crtc_page_flip,
7102};
7103
ee7b9f93
JB		 7104static void intel_pch_pll_init(struct drm_device *dev)
7105{
7106 drm_i915_private_t *dev_priv = dev->dev_private;
7107 int i;
7108
7109 if (dev_priv->num_pch_pll == 0) {
7110 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7111 return;
7112 }
7113
7114 for (i = 0; i < dev_priv->num_pch_pll; i++) {
7115 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7116 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
7117 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
7118 }
7119}
7120
b358d0a6 7121static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 7122{
22fd0fab 7123 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 7124 struct intel_crtc *intel_crtc;
7125 int i;
7126
7127 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7128 if (intel_crtc == NULL)
7129 return;
7130
7131 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7132
7133 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7134 for (i = 0; i < 256; i++) {
7135 intel_crtc->lut_r[i] = i;
7136 intel_crtc->lut_g[i] = i;
7137 intel_crtc->lut_b[i] = i;
7138 }
7139
80824003
JB		 7140 /* Swap pipes & planes for FBC on pre-965 */
7141 intel_crtc->pipe = pipe;
7142 intel_crtc->plane = pipe;
e2e767ab 7143 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7144 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7145 intel_crtc->plane = !pipe;
80824003
JB		 7146 }
7147
22fd0fab
JB		 7148 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7149 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7150 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7151 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7152
5a354204 7153 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3 7154
79e53945 7155 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
79e53945
JB		 7156}
7157
08d7b3d1 7158int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7159 struct drm_file *file)
08d7b3d1 7160{
08d7b3d1 7161 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 7162 struct drm_mode_object *drmmode_obj;
7163 struct intel_crtc *crtc;
08d7b3d1 7164
1cff8f6b
DV		 7165 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7166 return -ENODEV;
08d7b3d1 7167
c05422d5
DV		 7168 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7169 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7170
c05422d5 7171 if (!drmmode_obj) {
08d7b3d1
CW		 7172 DRM_ERROR("no such CRTC id\n");
7173 return -EINVAL;
7174 }
7175
c05422d5
DV		 7176 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7177 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7178
c05422d5 7179 return 0;
08d7b3d1
CW		 7180}
7181
66a9278e 7182static int intel_encoder_clones(struct intel_encoder *encoder)
79e53945 7183{
66a9278e
DV		 7184 struct drm_device *dev = encoder->base.dev;
7185 struct intel_encoder *source_encoder;
79e53945 7186 int index_mask = 0;
79e53945
JB		 7187 int entry = 0;
7188
66a9278e
DV		 7189 list_for_each_entry(source_encoder,
7190 &dev->mode_config.encoder_list, base.head) {
7191
7192 if (encoder == source_encoder)
79e53945 7193 index_mask |= (1 << entry);
66a9278e
DV		 7194
7195 /* Intel hw has only one MUX where enocoders could be cloned. */
7196 if (encoder->cloneable && source_encoder->cloneable)
7197 index_mask |= (1 << entry);
7198
79e53945
JB		 7199 entry++;
7200 }
4ef69c7a 7201
79e53945
JB		 7202 return index_mask;
7203}
7204
4d302442
CW		 7205static bool has_edp_a(struct drm_device *dev)
7206{
7207 struct drm_i915_private *dev_priv = dev->dev_private;
7208
7209 if (!IS_MOBILE(dev))
7210 return false;
7211
7212 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7213 return false;
7214
7215 if (IS_GEN5(dev) &&
7216 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7217 return false;
7218
7219 return true;
7220}
7221
79e53945
JB		 7222static void intel_setup_outputs(struct drm_device *dev)
7223{
725e30ad 7224 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 7225 struct intel_encoder *encoder;
cb0953d7 7226 bool dpd_is_edp = false;
f3cfcba6 7227 bool has_lvds;
79e53945 7228
f3cfcba6 7229 has_lvds = intel_lvds_init(dev);
c5d1b51d
CW		 7230 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7231 /* disable the panel fitter on everything but LVDS */
7232 I915_WRITE(PFIT_CONTROL, 0);
7233 }
79e53945 7234
bad720ff 7235 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 7236 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 7237
4d302442 7238 if (has_edp_a(dev))
ab9d7c30 7239 intel_dp_init(dev, DP_A, PORT_A);
32f9d658 7240
cb0953d7 7241 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 7242 intel_dp_init(dev, PCH_DP_D, PORT_D);
cb0953d7
AJ		 7243 }
7244
7245 intel_crt_init(dev);
7246
0e72a5b5
ED		 7247 if (IS_HASWELL(dev)) {
7248 int found;
7249
7250 /* Haswell uses DDI functions to detect digital outputs */
7251 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
7252 /* DDI A only supports eDP */
7253 if (found)
7254 intel_ddi_init(dev, PORT_A);
7255
7256 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
7257 * register */
7258 found = I915_READ(SFUSE_STRAP);
7259
7260 if (found & SFUSE_STRAP_DDIB_DETECTED)
7261 intel_ddi_init(dev, PORT_B);
7262 if (found & SFUSE_STRAP_DDIC_DETECTED)
7263 intel_ddi_init(dev, PORT_C);
7264 if (found & SFUSE_STRAP_DDID_DETECTED)
7265 intel_ddi_init(dev, PORT_D);
7266 } else if (HAS_PCH_SPLIT(dev)) {
cb0953d7
AJ		 7267 int found;
7268
30ad48b7 7269 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca 7270 /* PCH SDVOB multiplex with HDMIB */
eef4eacb 7271 found = intel_sdvo_init(dev, PCH_SDVOB, true);
30ad48b7 7272 if (!found)
08d644ad 7273 intel_hdmi_init(dev, HDMIB, PORT_B);
5eb08b69 7274 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
ab9d7c30 7275 intel_dp_init(dev, PCH_DP_B, PORT_B);
30ad48b7
ZW		 7276 }
7277
7278 if (I915_READ(HDMIC) & PORT_DETECTED)
08d644ad 7279 intel_hdmi_init(dev, HDMIC, PORT_C);
30ad48b7 7280
b708a1d5 7281 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
08d644ad 7282 intel_hdmi_init(dev, HDMID, PORT_D);
30ad48b7 7283
5eb08b69 7284 if (I915_READ(PCH_DP_C) & DP_DETECTED)
ab9d7c30 7285 intel_dp_init(dev, PCH_DP_C, PORT_C);
5eb08b69 7286
cb0953d7 7287 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
ab9d7c30 7288 intel_dp_init(dev, PCH_DP_D, PORT_D);
4a87d65d
JB		 7289 } else if (IS_VALLEYVIEW(dev)) {
7290 int found;
7291
7292 if (I915_READ(SDVOB) & PORT_DETECTED) {
7293 /* SDVOB multiplex with HDMIB */
7294 found = intel_sdvo_init(dev, SDVOB, true);
7295 if (!found)
08d644ad 7296 intel_hdmi_init(dev, SDVOB, PORT_B);
4a87d65d 7297 if (!found && (I915_READ(DP_B) & DP_DETECTED))
ab9d7c30 7298 intel_dp_init(dev, DP_B, PORT_B);
4a87d65d
JB		 7299 }
7300
7301 if (I915_READ(SDVOC) & PORT_DETECTED)
08d644ad 7302 intel_hdmi_init(dev, SDVOC, PORT_C);
5eb08b69 7303
4a87d65d
JB		 7304 /* Shares lanes with HDMI on SDVOC */
7305 if (I915_READ(DP_C) & DP_DETECTED)
ab9d7c30 7306 intel_dp_init(dev, DP_C, PORT_C);
103a196f 7307 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 7308 bool found = false;
7d57382e 7309
725e30ad 7310 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 7311 DRM_DEBUG_KMS("probing SDVOB\n");
eef4eacb 7312 found = intel_sdvo_init(dev, SDVOB, true);
b01f2c3a
JB		 7313 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7314 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
08d644ad 7315 intel_hdmi_init(dev, SDVOB, PORT_B);
b01f2c3a 7316 }
27185ae1 7317
b01f2c3a
JB		 7318 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7319 DRM_DEBUG_KMS("probing DP_B\n");
ab9d7c30 7320 intel_dp_init(dev, DP_B, PORT_B);
b01f2c3a 7321 }
725e30ad 7322 }
13520b05
KH		 7323
7324 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 7325
b01f2c3a
JB		 7326 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7327 DRM_DEBUG_KMS("probing SDVOC\n");
eef4eacb 7328 found = intel_sdvo_init(dev, SDVOC, false);
b01f2c3a 7329 }
27185ae1
ML		 7330
7331 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7332
b01f2c3a
JB		 7333 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7334 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
08d644ad 7335 intel_hdmi_init(dev, SDVOC, PORT_C);
b01f2c3a
JB		 7336 }
7337 if (SUPPORTS_INTEGRATED_DP(dev)) {
7338 DRM_DEBUG_KMS("probing DP_C\n");
ab9d7c30 7339 intel_dp_init(dev, DP_C, PORT_C);
b01f2c3a 7340 }
725e30ad 7341 }
27185ae1 7342
b01f2c3a
JB		 7343 if (SUPPORTS_INTEGRATED_DP(dev) &&
7344 (I915_READ(DP_D) & DP_DETECTED)) {
7345 DRM_DEBUG_KMS("probing DP_D\n");
ab9d7c30 7346 intel_dp_init(dev, DP_D, PORT_D);
b01f2c3a 7347 }
bad720ff 7348 } else if (IS_GEN2(dev))
79e53945
JB		 7349 intel_dvo_init(dev);
7350
103a196f 7351 if (SUPPORTS_TV(dev))
79e53945
JB		 7352 intel_tv_init(dev);
7353
4ef69c7a
CW		 7354 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7355 encoder->base.possible_crtcs = encoder->crtc_mask;
7356 encoder->base.possible_clones =
66a9278e 7357 intel_encoder_clones(encoder);
79e53945 7358 }
47356eb6 7359
40579abe 7360 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
9fb526db 7361 ironlake_init_pch_refclk(dev);
79e53945
JB		 7362}
7363
7364static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7365{
7366 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 7367
7368 drm_framebuffer_cleanup(fb);
05394f39 7369 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 7370
7371 kfree(intel_fb);
7372}
7373
7374static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 7375 struct drm_file *file,
79e53945
JB		 7376 unsigned int *handle)
7377{
7378 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 7379 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 7380
05394f39 7381 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 7382}
7383
7384static const struct drm_framebuffer_funcs intel_fb_funcs = {
7385 .destroy = intel_user_framebuffer_destroy,
7386 .create_handle = intel_user_framebuffer_create_handle,
7387};
7388
38651674
DA		 7389int intel_framebuffer_init(struct drm_device *dev,
7390 struct intel_framebuffer *intel_fb,
308e5bcb 7391 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 7392 struct drm_i915_gem_object *obj)
79e53945 7393{
79e53945
JB		 7394 int ret;
7395
05394f39 7396 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 7397 return -EINVAL;
7398
308e5bcb 7399 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 7400 return -EINVAL;
7401
308e5bcb 7402 switch (mode_cmd->pixel_format) {
04b3924d
VS		 7403 case DRM_FORMAT_RGB332:
7404 case DRM_FORMAT_RGB565:
7405 case DRM_FORMAT_XRGB8888:
b250da79 7406 case DRM_FORMAT_XBGR8888:
04b3924d
VS		 7407 case DRM_FORMAT_ARGB8888:
7408 case DRM_FORMAT_XRGB2101010:
7409 case DRM_FORMAT_ARGB2101010:
308e5bcb 7410 /* RGB formats are common across chipsets */
b5626747 7411 break;
04b3924d
VS		 7412 case DRM_FORMAT_YUYV:
7413 case DRM_FORMAT_UYVY:
7414 case DRM_FORMAT_YVYU:
7415 case DRM_FORMAT_VYUY:
57cd6508
CW		 7416 break;
7417 default:
aca25848
ED		 7418 DRM_DEBUG_KMS("unsupported pixel format %u\n",
7419 mode_cmd->pixel_format);
57cd6508
CW		 7420 return -EINVAL;
7421 }
7422
79e53945
JB		 7423 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7424 if (ret) {
7425 DRM_ERROR("framebuffer init failed %d\n", ret);
7426 return ret;
7427 }
7428
7429 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 7430 intel_fb->obj = obj;
79e53945
JB		 7431 return 0;
7432}
7433
79e53945
JB		 7434static struct drm_framebuffer *
7435intel_user_framebuffer_create(struct drm_device *dev,
7436 struct drm_file *filp,
308e5bcb 7437 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 7438{
05394f39 7439 struct drm_i915_gem_object *obj;
79e53945 7440
308e5bcb
JB		 7441 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7442 mode_cmd->handles[0]));
c8725226 7443 if (&obj->base == NULL)
cce13ff7 7444 return ERR_PTR(-ENOENT);
79e53945 7445
d2dff872 7446 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 7447}
7448
79e53945 7449static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 7450 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 7451 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 7452};
7453
e70236a8
JB		 7454/* Set up chip specific display functions */
7455static void intel_init_display(struct drm_device *dev)
7456{
7457 struct drm_i915_private *dev_priv = dev->dev_private;
7458
7459 /* We always want a DPMS function */
f564048e 7460 if (HAS_PCH_SPLIT(dev)) {
f564048e 7461 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
76e5a89c
DV		 7462 dev_priv->display.crtc_enable = ironlake_crtc_enable;
7463 dev_priv->display.crtc_disable = ironlake_crtc_disable;
ee7b9f93 7464 dev_priv->display.off = ironlake_crtc_off;
17638cd6 7465 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 7466 } else {
f564048e 7467 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
76e5a89c
DV		 7468 dev_priv->display.crtc_enable = i9xx_crtc_enable;
7469 dev_priv->display.crtc_disable = i9xx_crtc_disable;
ee7b9f93 7470 dev_priv->display.off = i9xx_crtc_off;
17638cd6 7471 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 7472 }
e70236a8 7473
e70236a8 7474 /* Returns the core display clock speed */
25eb05fc
JB		 7475 if (IS_VALLEYVIEW(dev))
7476 dev_priv->display.get_display_clock_speed =
7477 valleyview_get_display_clock_speed;
7478 else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 7479 dev_priv->display.get_display_clock_speed =
7480 i945_get_display_clock_speed;
7481 else if (IS_I915G(dev))
7482 dev_priv->display.get_display_clock_speed =
7483 i915_get_display_clock_speed;
f2b115e6 7484 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 7485 dev_priv->display.get_display_clock_speed =
7486 i9xx_misc_get_display_clock_speed;
7487 else if (IS_I915GM(dev))
7488 dev_priv->display.get_display_clock_speed =
7489 i915gm_get_display_clock_speed;
7490 else if (IS_I865G(dev))
7491 dev_priv->display.get_display_clock_speed =
7492 i865_get_display_clock_speed;
f0f8a9ce 7493 else if (IS_I85X(dev))
e70236a8
JB		 7494 dev_priv->display.get_display_clock_speed =
7495 i855_get_display_clock_speed;
7496 else /* 852, 830 */
7497 dev_priv->display.get_display_clock_speed =
7498 i830_get_display_clock_speed;
7499
7f8a8569 7500 if (HAS_PCH_SPLIT(dev)) {
f00a3ddf 7501 if (IS_GEN5(dev)) {
674cf967 7502 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
e0dac65e 7503 dev_priv->display.write_eld = ironlake_write_eld;
1398261a 7504 } else if (IS_GEN6(dev)) {
674cf967 7505 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
e0dac65e 7506 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 7507 } else if (IS_IVYBRIDGE(dev)) {
7508 /* FIXME: detect B0+ stepping and use auto training */
7509 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
e0dac65e 7510 dev_priv->display.write_eld = ironlake_write_eld;
c82e4d26
ED		 7511 } else if (IS_HASWELL(dev)) {
7512 dev_priv->display.fdi_link_train = hsw_fdi_link_train;
83358c85 7513 dev_priv->display.write_eld = haswell_write_eld;
7f8a8569
ZW		 7514 } else
7515 dev_priv->display.update_wm = NULL;
6067aaea 7516 } else if (IS_G4X(dev)) {
e0dac65e 7517 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 7518 }
8c9f3aaf
JB		 7519
7520 /* Default just returns -ENODEV to indicate unsupported */
7521 dev_priv->display.queue_flip = intel_default_queue_flip;
7522
7523 switch (INTEL_INFO(dev)->gen) {
7524 case 2:
7525 dev_priv->display.queue_flip = intel_gen2_queue_flip;
7526 break;
7527
7528 case 3:
7529 dev_priv->display.queue_flip = intel_gen3_queue_flip;
7530 break;
7531
7532 case 4:
7533 case 5:
7534 dev_priv->display.queue_flip = intel_gen4_queue_flip;
7535 break;
7536
7537 case 6:
7538 dev_priv->display.queue_flip = intel_gen6_queue_flip;
7539 break;
7c9017e5
JB		 7540 case 7:
7541 dev_priv->display.queue_flip = intel_gen7_queue_flip;
7542 break;
8c9f3aaf 7543 }
e70236a8
JB		 7544}
7545
b690e96c
JB		 7546/*
7547 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
7548 * resume, or other times. This quirk makes sure that's the case for
7549 * affected systems.
7550 */
0206e353 7551static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 7552{
7553 struct drm_i915_private *dev_priv = dev->dev_private;
7554
7555 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
bc0daf48 7556 DRM_INFO("applying pipe a force quirk\n");
b690e96c
JB		 7557}
7558
435793df
KP		 7559/*
7560 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
7561 */
7562static void quirk_ssc_force_disable(struct drm_device *dev)
7563{
7564 struct drm_i915_private *dev_priv = dev->dev_private;
7565 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
bc0daf48 7566 DRM_INFO("applying lvds SSC disable quirk\n");
435793df
KP		 7567}
7568
4dca20ef 7569/*
5a15ab5b
CE		 7570 * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
7571 * brightness value
4dca20ef
CE		 7572 */
7573static void quirk_invert_brightness(struct drm_device *dev)
7574{
7575 struct drm_i915_private *dev_priv = dev->dev_private;
7576 dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
bc0daf48 7577 DRM_INFO("applying inverted panel brightness quirk\n");
435793df
KP		 7578}
7579
b690e96c
JB		 7580struct intel_quirk {
7581 int device;
7582 int subsystem_vendor;
7583 int subsystem_device;
7584 void (*hook)(struct drm_device *dev);
7585};
7586
c43b5634 7587static struct intel_quirk intel_quirks[] = {
b690e96c 7588 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 7589 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c 7590
b690e96c
JB		 7591 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
7592 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
7593
b690e96c
JB		 7594 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
7595 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
7596
7597 /* 855 & before need to leave pipe A & dpll A up */
7598 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
7599 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
dcdaed6e 7600 { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 7601
7602 /* Lenovo U160 cannot use SSC on LVDS */
7603 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 7604
7605 /* Sony Vaio Y cannot use SSC on LVDS */
7606 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
5a15ab5b
CE		 7607
7608 /* Acer Aspire 5734Z must invert backlight brightness */
7609 { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
b690e96c
JB		 7610};
7611
7612static void intel_init_quirks(struct drm_device *dev)
7613{
7614 struct pci_dev *d = dev->pdev;
7615 int i;
7616
7617 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
7618 struct intel_quirk *q = &intel_quirks[i];
7619
7620 if (d->device == q->device &&
7621 (d->subsystem_vendor == q->subsystem_vendor ||
7622 q->subsystem_vendor == PCI_ANY_ID) &&
7623 (d->subsystem_device == q->subsystem_device ||
7624 q->subsystem_device == PCI_ANY_ID))
7625 q->hook(dev);
7626 }
7627}
7628
9cce37f4
JB		 7629/* Disable the VGA plane that we never use */
7630static void i915_disable_vga(struct drm_device *dev)
7631{
7632 struct drm_i915_private *dev_priv = dev->dev_private;
7633 u8 sr1;
7634 u32 vga_reg;
7635
7636 if (HAS_PCH_SPLIT(dev))
7637 vga_reg = CPU_VGACNTRL;
7638 else
7639 vga_reg = VGACNTRL;
7640
7641 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
3fdcf431 7642 outb(SR01, VGA_SR_INDEX);
9cce37f4
JB		 7643 sr1 = inb(VGA_SR_DATA);
7644 outb(sr1 | 1<<5, VGA_SR_DATA);
7645 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
7646 udelay(300);
7647
7648 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
7649 POSTING_READ(vga_reg);
7650}
7651
f817586c
DV		 7652void intel_modeset_init_hw(struct drm_device *dev)
7653{
0232e927
ED		 7654 /* We attempt to init the necessary power wells early in the initialization
7655 * time, so the subsystems that expect power to be enabled can work.
7656 */
7657 intel_init_power_wells(dev);
7658
a8f78b58
ED		 7659 intel_prepare_ddi(dev);
7660
f817586c
DV		 7661 intel_init_clock_gating(dev);
7662
79f5b2c7 7663 mutex_lock(&dev->struct_mutex);
8090c6b9 7664 intel_enable_gt_powersave(dev);
79f5b2c7 7665 mutex_unlock(&dev->struct_mutex);
f817586c
DV		 7666}
7667
79e53945
JB		 7668void intel_modeset_init(struct drm_device *dev)
7669{
652c393a 7670 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 7671 int i, ret;
79e53945
JB		 7672
7673 drm_mode_config_init(dev);
7674
7675 dev->mode_config.min_width = 0;
7676 dev->mode_config.min_height = 0;
7677
019d96cb
DA		 7678 dev->mode_config.preferred_depth = 24;
7679 dev->mode_config.prefer_shadow = 1;
7680
e6ecefaa 7681 dev->mode_config.funcs = &intel_mode_funcs;
79e53945 7682
b690e96c
JB		 7683 intel_init_quirks(dev);
7684
1fa61106
ED		 7685 intel_init_pm(dev);
7686
e70236a8
JB		 7687 intel_init_display(dev);
7688
a6c45cf0
CW		 7689 if (IS_GEN2(dev)) {
7690 dev->mode_config.max_width = 2048;
7691 dev->mode_config.max_height = 2048;
7692 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 7693 dev->mode_config.max_width = 4096;
7694 dev->mode_config.max_height = 4096;
79e53945 7695 } else {
a6c45cf0
CW		 7696 dev->mode_config.max_width = 8192;
7697 dev->mode_config.max_height = 8192;
79e53945 7698 }
dd2757f8 7699 dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
79e53945 7700
28c97730 7701 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 7702 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 7703
a3524f1b 7704 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 7705 intel_crtc_init(dev, i);
00c2064b
JB		 7706 ret = intel_plane_init(dev, i);
7707 if (ret)
7708 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 7709 }
7710
ee7b9f93
JB		 7711 intel_pch_pll_init(dev);
7712
9cce37f4
JB		 7713 /* Just disable it once at startup */
7714 i915_disable_vga(dev);
79e53945 7715 intel_setup_outputs(dev);
2c7111db
CW		 7716}
7717
24929352
DV		 7718static void
7719intel_connector_break_all_links(struct intel_connector *connector)
7720{
7721 connector->base.dpms = DRM_MODE_DPMS_OFF;
7722 connector->base.encoder = NULL;
7723 connector->encoder->connectors_active = false;
7724 connector->encoder->base.crtc = NULL;
7725}
7726
7fad798e
DV		 7727static void intel_enable_pipe_a(struct drm_device *dev)
7728{
7729 struct intel_connector *connector;
7730 struct drm_connector *crt = NULL;
7731 struct intel_load_detect_pipe load_detect_temp;
7732
7733 /* We can't just switch on the pipe A, we need to set things up with a
7734 * proper mode and output configuration. As a gross hack, enable pipe A
7735 * by enabling the load detect pipe once. */
7736 list_for_each_entry(connector,
7737 &dev->mode_config.connector_list,
7738 base.head) {
7739 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
7740 crt = &connector->base;
7741 break;
7742 }
7743 }
7744
7745 if (!crt)
7746 return;
7747
7748 if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
7749 intel_release_load_detect_pipe(crt, &load_detect_temp);
7750
7751
7752}
7753
24929352
DV		 7754static void intel_sanitize_crtc(struct intel_crtc *crtc)
7755{
7756 struct drm_device *dev = crtc->base.dev;
7757 struct drm_i915_private *dev_priv = dev->dev_private;
7758 u32 reg, val;
7759
24929352
DV		 7760 /* Clear any frame start delays used for debugging left by the BIOS */
7761 reg = PIPECONF(crtc->pipe);
7762 I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
7763
7764 /* We need to sanitize the plane -> pipe mapping first because this will
7765 * disable the crtc (and hence change the state) if it is wrong. */
7766 if (!HAS_PCH_SPLIT(dev)) {
7767 struct intel_connector *connector;
7768 bool plane;
7769
7770 reg = DSPCNTR(crtc->plane);
7771 val = I915_READ(reg);
7772
7773 if ((val & DISPLAY_PLANE_ENABLE) == 0 &&
7774 (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
7775 goto ok;
7776
7777 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
7778 crtc->base.base.id);
7779
7780 /* Pipe has the wrong plane attached and the plane is active.
7781 * Temporarily change the plane mapping and disable everything
7782 * ... */
7783 plane = crtc->plane;
7784 crtc->plane = !plane;
7785 dev_priv->display.crtc_disable(&crtc->base);
7786 crtc->plane = plane;
7787
7788 /* ... and break all links. */
7789 list_for_each_entry(connector, &dev->mode_config.connector_list,
7790 base.head) {
7791 if (connector->encoder->base.crtc != &crtc->base)
7792 continue;
7793
7794 intel_connector_break_all_links(connector);
7795 }
7796
7797 WARN_ON(crtc->active);
7798 crtc->base.enabled = false;
7799 }
7800ok:
7801
7fad798e
DV		 7802 if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
7803 crtc->pipe == PIPE_A && !crtc->active) {
7804 /* BIOS forgot to enable pipe A, this mostly happens after
7805 * resume. Force-enable the pipe to fix this, the update_dpms
7806 * call below we restore the pipe to the right state, but leave
7807 * the required bits on. */
7808 intel_enable_pipe_a(dev);
7809 }
7810
24929352
DV		 7811 /* Adjust the state of the output pipe according to whether we
7812 * have active connectors/encoders. */
7813 intel_crtc_update_dpms(&crtc->base);
7814
7815 if (crtc->active != crtc->base.enabled) {
7816 struct intel_encoder *encoder;
7817
7818 /* This can happen either due to bugs in the get_hw_state
7819 * functions or because the pipe is force-enabled due to the
7820 * pipe A quirk. */
7821 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
7822 crtc->base.base.id,
7823 crtc->base.enabled ? "enabled" : "disabled",
7824 crtc->active ? "enabled" : "disabled");
7825
7826 crtc->base.enabled = crtc->active;
7827
7828 /* Because we only establish the connector -> encoder ->
7829 * crtc links if something is active, this means the
7830 * crtc is now deactivated. Break the links. connector
7831 * -> encoder links are only establish when things are
7832 * actually up, hence no need to break them. */
7833 WARN_ON(crtc->active);
7834
7835 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
7836 WARN_ON(encoder->connectors_active);
7837 encoder->base.crtc = NULL;
7838 }
7839 }
7840}
7841
7842static void intel_sanitize_encoder(struct intel_encoder *encoder)
7843{
7844 struct intel_connector *connector;
7845 struct drm_device *dev = encoder->base.dev;
7846
7847 /* We need to check both for a crtc link (meaning that the
7848 * encoder is active and trying to read from a pipe) and the
7849 * pipe itself being active. */
7850 bool has_active_crtc = encoder->base.crtc &&
7851 to_intel_crtc(encoder->base.crtc)->active;
7852
7853 if (encoder->connectors_active && !has_active_crtc) {
7854 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
7855 encoder->base.base.id,
7856 drm_get_encoder_name(&encoder->base));
7857
7858 /* Connector is active, but has no active pipe. This is
7859 * fallout from our resume register restoring. Disable
7860 * the encoder manually again. */
7861 if (encoder->base.crtc) {
7862 DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
7863 encoder->base.base.id,
7864 drm_get_encoder_name(&encoder->base));
7865 encoder->disable(encoder);
7866 }
7867
7868 /* Inconsistent output/port/pipe state happens presumably due to
7869 * a bug in one of the get_hw_state functions. Or someplace else
7870 * in our code, like the register restore mess on resume. Clamp
7871 * things to off as a safer default. */
7872 list_for_each_entry(connector,
7873 &dev->mode_config.connector_list,
7874 base.head) {
7875 if (connector->encoder != encoder)
7876 continue;
7877
7878 intel_connector_break_all_links(connector);
7879 }
7880 }
7881 /* Enabled encoders without active connectors will be fixed in
7882 * the crtc fixup. */
7883}
7884
7885/* Scan out the current hw modeset state, sanitizes it and maps it into the drm
7886 * and i915 state tracking structures. */
7887void intel_modeset_setup_hw_state(struct drm_device *dev)
7888{
7889 struct drm_i915_private *dev_priv = dev->dev_private;
7890 enum pipe pipe;
7891 u32 tmp;
7892 struct intel_crtc *crtc;
7893 struct intel_encoder *encoder;
7894 struct intel_connector *connector;
7895
7896 for_each_pipe(pipe) {
7897 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
7898
7899 tmp = I915_READ(PIPECONF(pipe));
7900 if (tmp & PIPECONF_ENABLE)
7901 crtc->active = true;
7902 else
7903 crtc->active = false;
7904
7905 crtc->base.enabled = crtc->active;
7906
7907 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
7908 crtc->base.base.id,
7909 crtc->active ? "enabled" : "disabled");
7910 }
7911
7912 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7913 base.head) {
7914 pipe = 0;
7915
7916 if (encoder->get_hw_state(encoder, &pipe)) {
7917 encoder->base.crtc =
7918 dev_priv->pipe_to_crtc_mapping[pipe];
7919 } else {
7920 encoder->base.crtc = NULL;
7921 }
7922
7923 encoder->connectors_active = false;
7924 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
7925 encoder->base.base.id,
7926 drm_get_encoder_name(&encoder->base),
7927 encoder->base.crtc ? "enabled" : "disabled",
7928 pipe);
7929 }
7930
7931 list_for_each_entry(connector, &dev->mode_config.connector_list,
7932 base.head) {
7933 if (connector->get_hw_state(connector)) {
7934 connector->base.dpms = DRM_MODE_DPMS_ON;
7935 connector->encoder->connectors_active = true;
7936 connector->base.encoder = &connector->encoder->base;
7937 } else {
7938 connector->base.dpms = DRM_MODE_DPMS_OFF;
7939 connector->base.encoder = NULL;
7940 }
7941 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
7942 connector->base.base.id,
7943 drm_get_connector_name(&connector->base),
7944 connector->base.encoder ? "enabled" : "disabled");
7945 }
7946
7947 /* HW state is read out, now we need to sanitize this mess. */
7948 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7949 base.head) {
7950 intel_sanitize_encoder(encoder);
7951 }
7952
7953 for_each_pipe(pipe) {
7954 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
7955 intel_sanitize_crtc(crtc);
7956 }
9a935856
DV		 7957
7958 intel_modeset_update_staged_output_state(dev);
24929352
DV		 7959}
7960
2c7111db
CW		 7961void intel_modeset_gem_init(struct drm_device *dev)
7962{
1833b134 7963 intel_modeset_init_hw(dev);
02e792fb
DV		 7964
7965 intel_setup_overlay(dev);
24929352
DV		 7966
7967 intel_modeset_setup_hw_state(dev);
79e53945
JB		 7968}
7969
7970void intel_modeset_cleanup(struct drm_device *dev)
7971{
652c393a
JB		 7972 struct drm_i915_private *dev_priv = dev->dev_private;
7973 struct drm_crtc *crtc;
7974 struct intel_crtc *intel_crtc;
7975
f87ea761 7976 drm_kms_helper_poll_fini(dev);
652c393a
JB		 7977 mutex_lock(&dev->struct_mutex);
7978
723bfd70
JB		 7979 intel_unregister_dsm_handler();
7980
7981
652c393a
JB		 7982 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7983 /* Skip inactive CRTCs */
7984 if (!crtc->fb)
7985 continue;
7986
7987 intel_crtc = to_intel_crtc(crtc);
3dec0095 7988 intel_increase_pllclock(crtc);
652c393a
JB		 7989 }
7990
973d04f9 7991 intel_disable_fbc(dev);
e70236a8 7992
8090c6b9 7993 intel_disable_gt_powersave(dev);
0cdab21f 7994
930ebb46
DV		 7995 ironlake_teardown_rc6(dev);
7996
57f350b6
JB		 7997 if (IS_VALLEYVIEW(dev))
7998 vlv_init_dpio(dev);
7999
69341a5e
KH		 8000 mutex_unlock(&dev->struct_mutex);
8001
6c0d9350
DV		 8002 /* Disable the irq before mode object teardown, for the irq might
8003 * enqueue unpin/hotplug work. */
8004 drm_irq_uninstall(dev);
8005 cancel_work_sync(&dev_priv->hotplug_work);
c6a828d3 8006 cancel_work_sync(&dev_priv->rps.work);
6c0d9350 8007
1630fe75
CW		 8008 /* flush any delayed tasks or pending work */
8009 flush_scheduled_work();
8010
79e53945
JB		 8011 drm_mode_config_cleanup(dev);
8012}
8013
f1c79df3
ZW		 8014/*
8015 * Return which encoder is currently attached for connector.
8016 */
df0e9248 8017struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 8018{
df0e9248
CW		 8019 return &intel_attached_encoder(connector)->base;
8020}
f1c79df3 8021
df0e9248
CW		 8022void intel_connector_attach_encoder(struct intel_connector *connector,
8023 struct intel_encoder *encoder)
8024{
8025 connector->encoder = encoder;
8026 drm_mode_connector_attach_encoder(&connector->base,
8027 &encoder->base);
79e53945 8028}
28d52043
DA		 8029
8030/*
8031 * set vga decode state - true == enable VGA decode
8032 */
8033int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
8034{
8035 struct drm_i915_private *dev_priv = dev->dev_private;
8036 u16 gmch_ctrl;
8037
8038 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
8039 if (state)
8040 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
8041 else
8042 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
8043 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
8044 return 0;
8045}
c4a1d9e4
CW		 8046
8047#ifdef CONFIG_DEBUG_FS
8048#include <linux/seq_file.h>
8049
8050struct intel_display_error_state {
8051 struct intel_cursor_error_state {
8052 u32 control;
8053 u32 position;
8054 u32 base;
8055 u32 size;
52331309 8056 } cursor[I915_MAX_PIPES];
c4a1d9e4
CW		 8057
8058 struct intel_pipe_error_state {
8059 u32 conf;
8060 u32 source;
8061
8062 u32 htotal;
8063 u32 hblank;
8064 u32 hsync;
8065 u32 vtotal;
8066 u32 vblank;
8067 u32 vsync;
52331309 8068 } pipe[I915_MAX_PIPES];
c4a1d9e4
CW		 8069
8070 struct intel_plane_error_state {
8071 u32 control;
8072 u32 stride;
8073 u32 size;
8074 u32 pos;
8075 u32 addr;
8076 u32 surface;
8077 u32 tile_offset;
52331309 8078 } plane[I915_MAX_PIPES];
c4a1d9e4
CW		 8079};
8080
8081struct intel_display_error_state *
8082intel_display_capture_error_state(struct drm_device *dev)
8083{
0206e353 8084 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 8085 struct intel_display_error_state *error;
8086 int i;
8087
8088 error = kmalloc(sizeof(*error), GFP_ATOMIC);
8089 if (error == NULL)
8090 return NULL;
8091
52331309 8092 for_each_pipe(i) {
c4a1d9e4
CW		 8093 error->cursor[i].control = I915_READ(CURCNTR(i));
8094 error->cursor[i].position = I915_READ(CURPOS(i));
8095 error->cursor[i].base = I915_READ(CURBASE(i));
8096
8097 error->plane[i].control = I915_READ(DSPCNTR(i));
8098 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
8099 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 8100 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 8101 error->plane[i].addr = I915_READ(DSPADDR(i));
8102 if (INTEL_INFO(dev)->gen >= 4) {
8103 error->plane[i].surface = I915_READ(DSPSURF(i));
8104 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
8105 }
8106
8107 error->pipe[i].conf = I915_READ(PIPECONF(i));
8108 error->pipe[i].source = I915_READ(PIPESRC(i));
8109 error->pipe[i].htotal = I915_READ(HTOTAL(i));
8110 error->pipe[i].hblank = I915_READ(HBLANK(i));
8111 error->pipe[i].hsync = I915_READ(HSYNC(i));
8112 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
8113 error->pipe[i].vblank = I915_READ(VBLANK(i));
8114 error->pipe[i].vsync = I915_READ(VSYNC(i));
8115 }
8116
8117 return error;
8118}
8119
8120void
8121intel_display_print_error_state(struct seq_file *m,
8122 struct drm_device *dev,
8123 struct intel_display_error_state *error)
8124{
52331309 8125 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 8126 int i;
8127
52331309
DL		 8128 seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
8129 for_each_pipe(i) {
c4a1d9e4
CW		 8130 seq_printf(m, "Pipe [%d]:\n", i);
8131 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
8132 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
8133 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
8134 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
8135 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
8136 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
8137 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
8138 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
8139
8140 seq_printf(m, "Plane [%d]:\n", i);
8141 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
8142 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
8143 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
8144 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
8145 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
8146 if (INTEL_INFO(dev)->gen >= 4) {
8147 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
8148 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
8149 }
8150
8151 seq_printf(m, "Cursor [%d]:\n", i);
8152 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
8153 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
8154 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
8155 }
8156}
8157#endif
Linux kernel - Deliverables
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