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drm/i915: no lvds quirk for AOpen MP45
[deliverable/linux.git] / drivers / gpu / drm / i915 / intel_display.c
CommitLineData
79e53945
JB		 1/*
2 * Copyright © 2006-2007 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 */
26
23b2f8bb 27#include <linux/cpufreq.h>
c1c7af60
JB		 28#include <linux/module.h>
29#include <linux/input.h>
79e53945 30#include <linux/i2c.h>
7662c8bd 31#include <linux/kernel.h>
5a0e3ad6 32#include <linux/slab.h>
9cce37f4 33#include <linux/vgaarb.h>
e0dac65e 34#include <drm/drm_edid.h>
79e53945
JB		 35#include "drmP.h"
36#include "intel_drv.h"
37#include "i915_drm.h"
38#include "i915_drv.h"
e5510fac 39#include "i915_trace.h"
ab2c0672 40#include "drm_dp_helper.h"
79e53945 41#include "drm_crtc_helper.h"
c0f372b3 42#include <linux/dma_remapping.h>
79e53945 43
32f9d658
ZW		 44#define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
45
0206e353 46bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
7662c8bd 47static void intel_update_watermarks(struct drm_device *dev);
3dec0095 48static void intel_increase_pllclock(struct drm_crtc *crtc);
6b383a7f 49static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
79e53945
JB		 50
51typedef struct {
0206e353
AJ		 52 /* given values */
53 int n;
54 int m1, m2;
55 int p1, p2;
56 /* derived values */
57 int dot;
58 int vco;
59 int m;
60 int p;
79e53945
JB		 61} intel_clock_t;
62
63typedef struct {
0206e353 64 int min, max;
79e53945
JB		 65} intel_range_t;
66
67typedef struct {
0206e353
AJ		 68 int dot_limit;
69 int p2_slow, p2_fast;
79e53945
JB		 70} intel_p2_t;
71
72#define INTEL_P2_NUM 2
d4906093
ML		 73typedef struct intel_limit intel_limit_t;
74struct intel_limit {
0206e353
AJ		 75 intel_range_t dot, vco, n, m, m1, m2, p, p1;
76 intel_p2_t p2;
77 bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
78 int, int, intel_clock_t *);
d4906093 79};
79e53945 80
2377b741
JB		 81/* FDI */
82#define IRONLAKE_FDI_FREQ 2700000 /* in kHz for mode->clock */
83
d4906093
ML		 84static bool
85intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
86 int target, int refclk, intel_clock_t *best_clock);
87static bool
88intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
89 int target, int refclk, intel_clock_t *best_clock);
79e53945 90
a4fc5ed6
KP		 91static bool
92intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
93 int target, int refclk, intel_clock_t *best_clock);
5eb08b69 94static bool
f2b115e6
AJ		 95intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
96 int target, int refclk, intel_clock_t *best_clock);
a4fc5ed6 97
021357ac
CW		 98static inline u32 /* units of 100MHz */
99intel_fdi_link_freq(struct drm_device *dev)
100{
8b99e68c
CW		 101 if (IS_GEN5(dev)) {
102 struct drm_i915_private *dev_priv = dev->dev_private;
103 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
104 } else
105 return 27;
021357ac
CW		 106}
107
e4b36699 108static const intel_limit_t intel_limits_i8xx_dvo = {
0206e353
AJ		 109 .dot = { .min = 25000, .max = 350000 },
110 .vco = { .min = 930000, .max = 1400000 },
111 .n = { .min = 3, .max = 16 },
112 .m = { .min = 96, .max = 140 },
113 .m1 = { .min = 18, .max = 26 },
114 .m2 = { .min = 6, .max = 16 },
115 .p = { .min = 4, .max = 128 },
116 .p1 = { .min = 2, .max = 33 },
273e27ca
EA		 117 .p2 = { .dot_limit = 165000,
118 .p2_slow = 4, .p2_fast = 2 },
d4906093 119 .find_pll = intel_find_best_PLL,
e4b36699
KP		 120};
121
122static const intel_limit_t intel_limits_i8xx_lvds = {
0206e353
AJ		 123 .dot = { .min = 25000, .max = 350000 },
124 .vco = { .min = 930000, .max = 1400000 },
125 .n = { .min = 3, .max = 16 },
126 .m = { .min = 96, .max = 140 },
127 .m1 = { .min = 18, .max = 26 },
128 .m2 = { .min = 6, .max = 16 },
129 .p = { .min = 4, .max = 128 },
130 .p1 = { .min = 1, .max = 6 },
273e27ca
EA		 131 .p2 = { .dot_limit = 165000,
132 .p2_slow = 14, .p2_fast = 7 },
d4906093 133 .find_pll = intel_find_best_PLL,
e4b36699 134};
273e27ca 135
e4b36699 136static const intel_limit_t intel_limits_i9xx_sdvo = {
0206e353
AJ		 137 .dot = { .min = 20000, .max = 400000 },
138 .vco = { .min = 1400000, .max = 2800000 },
139 .n = { .min = 1, .max = 6 },
140 .m = { .min = 70, .max = 120 },
141 .m1 = { .min = 10, .max = 22 },
142 .m2 = { .min = 5, .max = 9 },
143 .p = { .min = 5, .max = 80 },
144 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 145 .p2 = { .dot_limit = 200000,
146 .p2_slow = 10, .p2_fast = 5 },
d4906093 147 .find_pll = intel_find_best_PLL,
e4b36699
KP		 148};
149
150static const intel_limit_t intel_limits_i9xx_lvds = {
0206e353
AJ		 151 .dot = { .min = 20000, .max = 400000 },
152 .vco = { .min = 1400000, .max = 2800000 },
153 .n = { .min = 1, .max = 6 },
154 .m = { .min = 70, .max = 120 },
155 .m1 = { .min = 10, .max = 22 },
156 .m2 = { .min = 5, .max = 9 },
157 .p = { .min = 7, .max = 98 },
158 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 159 .p2 = { .dot_limit = 112000,
160 .p2_slow = 14, .p2_fast = 7 },
d4906093 161 .find_pll = intel_find_best_PLL,
e4b36699
KP		 162};
163
273e27ca 164
e4b36699 165static const intel_limit_t intel_limits_g4x_sdvo = {
273e27ca
EA		 166 .dot = { .min = 25000, .max = 270000 },
167 .vco = { .min = 1750000, .max = 3500000},
168 .n = { .min = 1, .max = 4 },
169 .m = { .min = 104, .max = 138 },
170 .m1 = { .min = 17, .max = 23 },
171 .m2 = { .min = 5, .max = 11 },
172 .p = { .min = 10, .max = 30 },
173 .p1 = { .min = 1, .max = 3},
174 .p2 = { .dot_limit = 270000,
175 .p2_slow = 10,
176 .p2_fast = 10
044c7c41 177 },
d4906093 178 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 179};
180
181static const intel_limit_t intel_limits_g4x_hdmi = {
273e27ca
EA		 182 .dot = { .min = 22000, .max = 400000 },
183 .vco = { .min = 1750000, .max = 3500000},
184 .n = { .min = 1, .max = 4 },
185 .m = { .min = 104, .max = 138 },
186 .m1 = { .min = 16, .max = 23 },
187 .m2 = { .min = 5, .max = 11 },
188 .p = { .min = 5, .max = 80 },
189 .p1 = { .min = 1, .max = 8},
190 .p2 = { .dot_limit = 165000,
191 .p2_slow = 10, .p2_fast = 5 },
d4906093 192 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 193};
194
195static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
273e27ca
EA		 196 .dot = { .min = 20000, .max = 115000 },
197 .vco = { .min = 1750000, .max = 3500000 },
198 .n = { .min = 1, .max = 3 },
199 .m = { .min = 104, .max = 138 },
200 .m1 = { .min = 17, .max = 23 },
201 .m2 = { .min = 5, .max = 11 },
202 .p = { .min = 28, .max = 112 },
203 .p1 = { .min = 2, .max = 8 },
204 .p2 = { .dot_limit = 0,
205 .p2_slow = 14, .p2_fast = 14
044c7c41 206 },
d4906093 207 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 208};
209
210static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
273e27ca
EA		 211 .dot = { .min = 80000, .max = 224000 },
212 .vco = { .min = 1750000, .max = 3500000 },
213 .n = { .min = 1, .max = 3 },
214 .m = { .min = 104, .max = 138 },
215 .m1 = { .min = 17, .max = 23 },
216 .m2 = { .min = 5, .max = 11 },
217 .p = { .min = 14, .max = 42 },
218 .p1 = { .min = 2, .max = 6 },
219 .p2 = { .dot_limit = 0,
220 .p2_slow = 7, .p2_fast = 7
044c7c41 221 },
d4906093 222 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 223};
224
225static const intel_limit_t intel_limits_g4x_display_port = {
0206e353
AJ		 226 .dot = { .min = 161670, .max = 227000 },
227 .vco = { .min = 1750000, .max = 3500000},
228 .n = { .min = 1, .max = 2 },
229 .m = { .min = 97, .max = 108 },
230 .m1 = { .min = 0x10, .max = 0x12 },
231 .m2 = { .min = 0x05, .max = 0x06 },
232 .p = { .min = 10, .max = 20 },
233 .p1 = { .min = 1, .max = 2},
234 .p2 = { .dot_limit = 0,
273e27ca 235 .p2_slow = 10, .p2_fast = 10 },
0206e353 236 .find_pll = intel_find_pll_g4x_dp,
e4b36699
KP		 237};
238
f2b115e6 239static const intel_limit_t intel_limits_pineview_sdvo = {
0206e353
AJ		 240 .dot = { .min = 20000, .max = 400000},
241 .vco = { .min = 1700000, .max = 3500000 },
273e27ca 242 /* Pineview's Ncounter is a ring counter */
0206e353
AJ		 243 .n = { .min = 3, .max = 6 },
244 .m = { .min = 2, .max = 256 },
273e27ca 245 /* Pineview only has one combined m divider, which we treat as m2. */
0206e353
AJ		 246 .m1 = { .min = 0, .max = 0 },
247 .m2 = { .min = 0, .max = 254 },
248 .p = { .min = 5, .max = 80 },
249 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 250 .p2 = { .dot_limit = 200000,
251 .p2_slow = 10, .p2_fast = 5 },
6115707b 252 .find_pll = intel_find_best_PLL,
e4b36699
KP		 253};
254
f2b115e6 255static const intel_limit_t intel_limits_pineview_lvds = {
0206e353
AJ		 256 .dot = { .min = 20000, .max = 400000 },
257 .vco = { .min = 1700000, .max = 3500000 },
258 .n = { .min = 3, .max = 6 },
259 .m = { .min = 2, .max = 256 },
260 .m1 = { .min = 0, .max = 0 },
261 .m2 = { .min = 0, .max = 254 },
262 .p = { .min = 7, .max = 112 },
263 .p1 = { .min = 1, .max = 8 },
273e27ca
EA		 264 .p2 = { .dot_limit = 112000,
265 .p2_slow = 14, .p2_fast = 14 },
6115707b 266 .find_pll = intel_find_best_PLL,
e4b36699
KP		 267};
268
273e27ca
EA		 269/* Ironlake / Sandybridge
270 *
271 * We calculate clock using (register_value + 2) for N/M1/M2, so here
272 * the range value for them is (actual_value - 2).
273 */
b91ad0ec 274static const intel_limit_t intel_limits_ironlake_dac = {
273e27ca
EA		 275 .dot = { .min = 25000, .max = 350000 },
276 .vco = { .min = 1760000, .max = 3510000 },
277 .n = { .min = 1, .max = 5 },
278 .m = { .min = 79, .max = 127 },
279 .m1 = { .min = 12, .max = 22 },
280 .m2 = { .min = 5, .max = 9 },
281 .p = { .min = 5, .max = 80 },
282 .p1 = { .min = 1, .max = 8 },
283 .p2 = { .dot_limit = 225000,
284 .p2_slow = 10, .p2_fast = 5 },
4547668a 285 .find_pll = intel_g4x_find_best_PLL,
e4b36699
KP		 286};
287
b91ad0ec 288static const intel_limit_t intel_limits_ironlake_single_lvds = {
273e27ca
EA		 289 .dot = { .min = 25000, .max = 350000 },
290 .vco = { .min = 1760000, .max = 3510000 },
291 .n = { .min = 1, .max = 3 },
292 .m = { .min = 79, .max = 118 },
293 .m1 = { .min = 12, .max = 22 },
294 .m2 = { .min = 5, .max = 9 },
295 .p = { .min = 28, .max = 112 },
296 .p1 = { .min = 2, .max = 8 },
297 .p2 = { .dot_limit = 225000,
298 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 299 .find_pll = intel_g4x_find_best_PLL,
300};
301
302static const intel_limit_t intel_limits_ironlake_dual_lvds = {
273e27ca
EA		 303 .dot = { .min = 25000, .max = 350000 },
304 .vco = { .min = 1760000, .max = 3510000 },
305 .n = { .min = 1, .max = 3 },
306 .m = { .min = 79, .max = 127 },
307 .m1 = { .min = 12, .max = 22 },
308 .m2 = { .min = 5, .max = 9 },
309 .p = { .min = 14, .max = 56 },
310 .p1 = { .min = 2, .max = 8 },
311 .p2 = { .dot_limit = 225000,
312 .p2_slow = 7, .p2_fast = 7 },
b91ad0ec
ZW		 313 .find_pll = intel_g4x_find_best_PLL,
314};
315
273e27ca 316/* LVDS 100mhz refclk limits. */
b91ad0ec 317static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
273e27ca
EA		 318 .dot = { .min = 25000, .max = 350000 },
319 .vco = { .min = 1760000, .max = 3510000 },
320 .n = { .min = 1, .max = 2 },
321 .m = { .min = 79, .max = 126 },
322 .m1 = { .min = 12, .max = 22 },
323 .m2 = { .min = 5, .max = 9 },
324 .p = { .min = 28, .max = 112 },
0206e353 325 .p1 = { .min = 2, .max = 8 },
273e27ca
EA		 326 .p2 = { .dot_limit = 225000,
327 .p2_slow = 14, .p2_fast = 14 },
b91ad0ec
ZW		 328 .find_pll = intel_g4x_find_best_PLL,
329};
330
331static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
273e27ca
EA		 332 .dot = { .min = 25000, .max = 350000 },
333 .vco = { .min = 1760000, .max = 3510000 },
334 .n = { .min = 1, .max = 3 },
335 .m = { .min = 79, .max = 126 },
336 .m1 = { .min = 12, .max = 22 },
337 .m2 = { .min = 5, .max = 9 },
338 .p = { .min = 14, .max = 42 },
0206e353 339 .p1 = { .min = 2, .max = 6 },
273e27ca
EA		 340 .p2 = { .dot_limit = 225000,
341 .p2_slow = 7, .p2_fast = 7 },
4547668a
ZY		 342 .find_pll = intel_g4x_find_best_PLL,
343};
344
345static const intel_limit_t intel_limits_ironlake_display_port = {
0206e353
AJ		 346 .dot = { .min = 25000, .max = 350000 },
347 .vco = { .min = 1760000, .max = 3510000},
348 .n = { .min = 1, .max = 2 },
349 .m = { .min = 81, .max = 90 },
350 .m1 = { .min = 12, .max = 22 },
351 .m2 = { .min = 5, .max = 9 },
352 .p = { .min = 10, .max = 20 },
353 .p1 = { .min = 1, .max = 2},
354 .p2 = { .dot_limit = 0,
273e27ca 355 .p2_slow = 10, .p2_fast = 10 },
0206e353 356 .find_pll = intel_find_pll_ironlake_dp,
79e53945
JB		 357};
358
1b894b59
CW		 359static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
360 int refclk)
2c07245f 361{
b91ad0ec
ZW		 362 struct drm_device *dev = crtc->dev;
363 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f 364 const intel_limit_t *limit;
b91ad0ec
ZW		 365
366 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
b91ad0ec
ZW		 367 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
368 LVDS_CLKB_POWER_UP) {
369 /* LVDS dual channel */
1b894b59 370 if (refclk == 100000)
b91ad0ec
ZW		 371 limit = &intel_limits_ironlake_dual_lvds_100m;
372 else
373 limit = &intel_limits_ironlake_dual_lvds;
374 } else {
1b894b59 375 if (refclk == 100000)
b91ad0ec
ZW		 376 limit = &intel_limits_ironlake_single_lvds_100m;
377 else
378 limit = &intel_limits_ironlake_single_lvds;
379 }
380 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
4547668a
ZY		 381 HAS_eDP)
382 limit = &intel_limits_ironlake_display_port;
2c07245f 383 else
b91ad0ec 384 limit = &intel_limits_ironlake_dac;
2c07245f
ZW		 385
386 return limit;
387}
388
044c7c41
ML		 389static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
390{
391 struct drm_device *dev = crtc->dev;
392 struct drm_i915_private *dev_priv = dev->dev_private;
393 const intel_limit_t *limit;
394
395 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
396 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
397 LVDS_CLKB_POWER_UP)
398 /* LVDS with dual channel */
e4b36699 399 limit = &intel_limits_g4x_dual_channel_lvds;
044c7c41
ML		 400 else
401 /* LVDS with dual channel */
e4b36699 402 limit = &intel_limits_g4x_single_channel_lvds;
044c7c41
ML		 403 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
404 intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
e4b36699 405 limit = &intel_limits_g4x_hdmi;
044c7c41 406 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
e4b36699 407 limit = &intel_limits_g4x_sdvo;
0206e353 408 } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
e4b36699 409 limit = &intel_limits_g4x_display_port;
044c7c41 410 } else /* The option is for other outputs */
e4b36699 411 limit = &intel_limits_i9xx_sdvo;
044c7c41
ML		 412
413 return limit;
414}
415
1b894b59 416static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
79e53945
JB		 417{
418 struct drm_device *dev = crtc->dev;
419 const intel_limit_t *limit;
420
bad720ff 421 if (HAS_PCH_SPLIT(dev))
1b894b59 422 limit = intel_ironlake_limit(crtc, refclk);
2c07245f 423 else if (IS_G4X(dev)) {
044c7c41 424 limit = intel_g4x_limit(crtc);
f2b115e6 425 } else if (IS_PINEVIEW(dev)) {
2177832f 426 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
f2b115e6 427 limit = &intel_limits_pineview_lvds;
2177832f 428 else
f2b115e6 429 limit = &intel_limits_pineview_sdvo;
a6c45cf0
CW		 430 } else if (!IS_GEN2(dev)) {
431 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
432 limit = &intel_limits_i9xx_lvds;
433 else
434 limit = &intel_limits_i9xx_sdvo;
79e53945
JB		 435 } else {
436 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
e4b36699 437 limit = &intel_limits_i8xx_lvds;
79e53945 438 else
e4b36699 439 limit = &intel_limits_i8xx_dvo;
79e53945
JB		 440 }
441 return limit;
442}
443
f2b115e6
AJ		 444/* m1 is reserved as 0 in Pineview, n is a ring counter */
445static void pineview_clock(int refclk, intel_clock_t *clock)
79e53945 446{
2177832f
SL		 447 clock->m = clock->m2 + 2;
448 clock->p = clock->p1 * clock->p2;
449 clock->vco = refclk * clock->m / clock->n;
450 clock->dot = clock->vco / clock->p;
451}
452
453static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
454{
f2b115e6
AJ		 455 if (IS_PINEVIEW(dev)) {
456 pineview_clock(refclk, clock);
2177832f
SL		 457 return;
458 }
79e53945
JB		 459 clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
460 clock->p = clock->p1 * clock->p2;
461 clock->vco = refclk * clock->m / (clock->n + 2);
462 clock->dot = clock->vco / clock->p;
463}
464
79e53945
JB		 465/**
466 * Returns whether any output on the specified pipe is of the specified type
467 */
4ef69c7a 468bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
79e53945 469{
4ef69c7a
CW		 470 struct drm_device *dev = crtc->dev;
471 struct drm_mode_config *mode_config = &dev->mode_config;
472 struct intel_encoder *encoder;
473
474 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
475 if (encoder->base.crtc == crtc && encoder->type == type)
476 return true;
477
478 return false;
79e53945
JB		 479}
480
7c04d1d9 481#define INTELPllInvalid(s) do { /* DRM_DEBUG(s); */ return false; } while (0)
79e53945
JB		 482/**
483 * Returns whether the given set of divisors are valid for a given refclk with
484 * the given connectors.
485 */
486
1b894b59
CW		 487static bool intel_PLL_is_valid(struct drm_device *dev,
488 const intel_limit_t *limit,
489 const intel_clock_t *clock)
79e53945 490{
79e53945 491 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
0206e353 492 INTELPllInvalid("p1 out of range\n");
79e53945 493 if (clock->p < limit->p.min || limit->p.max < clock->p)
0206e353 494 INTELPllInvalid("p out of range\n");
79e53945 495 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
0206e353 496 INTELPllInvalid("m2 out of range\n");
79e53945 497 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
0206e353 498 INTELPllInvalid("m1 out of range\n");
f2b115e6 499 if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
0206e353 500 INTELPllInvalid("m1 <= m2\n");
79e53945 501 if (clock->m < limit->m.min || limit->m.max < clock->m)
0206e353 502 INTELPllInvalid("m out of range\n");
79e53945 503 if (clock->n < limit->n.min || limit->n.max < clock->n)
0206e353 504 INTELPllInvalid("n out of range\n");
79e53945 505 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
0206e353 506 INTELPllInvalid("vco out of range\n");
79e53945
JB		 507 /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
508 * connector, etc., rather than just a single range.
509 */
510 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
0206e353 511 INTELPllInvalid("dot out of range\n");
79e53945
JB		 512
513 return true;
514}
515
d4906093
ML		 516static bool
517intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
518 int target, int refclk, intel_clock_t *best_clock)
519
79e53945
JB		 520{
521 struct drm_device *dev = crtc->dev;
522 struct drm_i915_private *dev_priv = dev->dev_private;
523 intel_clock_t clock;
79e53945
JB		 524 int err = target;
525
bc5e5718 526 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
832cc28d 527 (I915_READ(LVDS)) != 0) {
79e53945
JB		 528 /*
529 * For LVDS, if the panel is on, just rely on its current
530 * settings for dual-channel. We haven't figured out how to
531 * reliably set up different single/dual channel state, if we
532 * even can.
533 */
534 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
535 LVDS_CLKB_POWER_UP)
536 clock.p2 = limit->p2.p2_fast;
537 else
538 clock.p2 = limit->p2.p2_slow;
539 } else {
540 if (target < limit->p2.dot_limit)
541 clock.p2 = limit->p2.p2_slow;
542 else
543 clock.p2 = limit->p2.p2_fast;
544 }
545
0206e353 546 memset(best_clock, 0, sizeof(*best_clock));
79e53945 547
42158660
ZY		 548 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
549 clock.m1++) {
550 for (clock.m2 = limit->m2.min;
551 clock.m2 <= limit->m2.max; clock.m2++) {
f2b115e6
AJ		 552 /* m1 is always 0 in Pineview */
553 if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
42158660
ZY		 554 break;
555 for (clock.n = limit->n.min;
556 clock.n <= limit->n.max; clock.n++) {
557 for (clock.p1 = limit->p1.min;
558 clock.p1 <= limit->p1.max; clock.p1++) {
79e53945
JB		 559 int this_err;
560
2177832f 561 intel_clock(dev, refclk, &clock);
1b894b59
CW		 562 if (!intel_PLL_is_valid(dev, limit,
563 &clock))
79e53945
JB		 564 continue;
565
566 this_err = abs(clock.dot - target);
567 if (this_err < err) {
568 *best_clock = clock;
569 err = this_err;
570 }
571 }
572 }
573 }
574 }
575
576 return (err != target);
577}
578
d4906093
ML		 579static bool
580intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
581 int target, int refclk, intel_clock_t *best_clock)
582{
583 struct drm_device *dev = crtc->dev;
584 struct drm_i915_private *dev_priv = dev->dev_private;
585 intel_clock_t clock;
586 int max_n;
587 bool found;
6ba770dc
AJ		 588 /* approximately equals target * 0.00585 */
589 int err_most = (target >> 8) + (target >> 9);
d4906093
ML		 590 found = false;
591
592 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4547668a
ZY		 593 int lvds_reg;
594
c619eed4 595 if (HAS_PCH_SPLIT(dev))
4547668a
ZY		 596 lvds_reg = PCH_LVDS;
597 else
598 lvds_reg = LVDS;
599 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
d4906093
ML		 600 LVDS_CLKB_POWER_UP)
601 clock.p2 = limit->p2.p2_fast;
602 else
603 clock.p2 = limit->p2.p2_slow;
604 } else {
605 if (target < limit->p2.dot_limit)
606 clock.p2 = limit->p2.p2_slow;
607 else
608 clock.p2 = limit->p2.p2_fast;
609 }
610
611 memset(best_clock, 0, sizeof(*best_clock));
612 max_n = limit->n.max;
f77f13e2 613 /* based on hardware requirement, prefer smaller n to precision */
d4906093 614 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
f77f13e2 615 /* based on hardware requirement, prefere larger m1,m2 */
d4906093
ML		 616 for (clock.m1 = limit->m1.max;
617 clock.m1 >= limit->m1.min; clock.m1--) {
618 for (clock.m2 = limit->m2.max;
619 clock.m2 >= limit->m2.min; clock.m2--) {
620 for (clock.p1 = limit->p1.max;
621 clock.p1 >= limit->p1.min; clock.p1--) {
622 int this_err;
623
2177832f 624 intel_clock(dev, refclk, &clock);
1b894b59
CW		 625 if (!intel_PLL_is_valid(dev, limit,
626 &clock))
d4906093 627 continue;
1b894b59
CW		 628
629 this_err = abs(clock.dot - target);
d4906093
ML		 630 if (this_err < err_most) {
631 *best_clock = clock;
632 err_most = this_err;
633 max_n = clock.n;
634 found = true;
635 }
636 }
637 }
638 }
639 }
2c07245f
ZW		 640 return found;
641}
642
5eb08b69 643static bool
f2b115e6
AJ		 644intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
645 int target, int refclk, intel_clock_t *best_clock)
5eb08b69
ZW		 646{
647 struct drm_device *dev = crtc->dev;
648 intel_clock_t clock;
4547668a 649
5eb08b69
ZW		 650 if (target < 200000) {
651 clock.n = 1;
652 clock.p1 = 2;
653 clock.p2 = 10;
654 clock.m1 = 12;
655 clock.m2 = 9;
656 } else {
657 clock.n = 2;
658 clock.p1 = 1;
659 clock.p2 = 10;
660 clock.m1 = 14;
661 clock.m2 = 8;
662 }
663 intel_clock(dev, refclk, &clock);
664 memcpy(best_clock, &clock, sizeof(intel_clock_t));
665 return true;
666}
667
a4fc5ed6
KP		 668/* DisplayPort has only two frequencies, 162MHz and 270MHz */
669static bool
670intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
671 int target, int refclk, intel_clock_t *best_clock)
672{
5eddb70b
CW		 673 intel_clock_t clock;
674 if (target < 200000) {
675 clock.p1 = 2;
676 clock.p2 = 10;
677 clock.n = 2;
678 clock.m1 = 23;
679 clock.m2 = 8;
680 } else {
681 clock.p1 = 1;
682 clock.p2 = 10;
683 clock.n = 1;
684 clock.m1 = 14;
685 clock.m2 = 2;
686 }
687 clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
688 clock.p = (clock.p1 * clock.p2);
689 clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
690 clock.vco = 0;
691 memcpy(best_clock, &clock, sizeof(intel_clock_t));
692 return true;
a4fc5ed6
KP		 693}
694
9d0498a2
JB		 695/**
696 * intel_wait_for_vblank - wait for vblank on a given pipe
697 * @dev: drm device
698 * @pipe: pipe to wait for
699 *
700 * Wait for vblank to occur on a given pipe. Needed for various bits of
701 * mode setting code.
702 */
703void intel_wait_for_vblank(struct drm_device *dev, int pipe)
79e53945 704{
9d0498a2 705 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 706 int pipestat_reg = PIPESTAT(pipe);
9d0498a2 707
300387c0
CW		 708 /* Clear existing vblank status. Note this will clear any other
709 * sticky status fields as well.
710 *
711 * This races with i915_driver_irq_handler() with the result
712 * that either function could miss a vblank event. Here it is not
713 * fatal, as we will either wait upon the next vblank interrupt or
714 * timeout. Generally speaking intel_wait_for_vblank() is only
715 * called during modeset at which time the GPU should be idle and
716 * should *not* be performing page flips and thus not waiting on
717 * vblanks...
718 * Currently, the result of us stealing a vblank from the irq
719 * handler is that a single frame will be skipped during swapbuffers.
720 */
721 I915_WRITE(pipestat_reg,
722 I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
723
9d0498a2 724 /* Wait for vblank interrupt bit to set */
481b6af3
CW		 725 if (wait_for(I915_READ(pipestat_reg) &
726 PIPE_VBLANK_INTERRUPT_STATUS,
727 50))
9d0498a2
JB		 728 DRM_DEBUG_KMS("vblank wait timed out\n");
729}
730
ab7ad7f6
KP		 731/*
732 * intel_wait_for_pipe_off - wait for pipe to turn off
9d0498a2
JB		 733 * @dev: drm device
734 * @pipe: pipe to wait for
735 *
736 * After disabling a pipe, we can't wait for vblank in the usual way,
737 * spinning on the vblank interrupt status bit, since we won't actually
738 * see an interrupt when the pipe is disabled.
739 *
ab7ad7f6
KP		 740 * On Gen4 and above:
741 * wait for the pipe register state bit to turn off
742 *
743 * Otherwise:
744 * wait for the display line value to settle (it usually
745 * ends up stopping at the start of the next frame).
58e10eb9 746 *
9d0498a2 747 */
58e10eb9 748void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
9d0498a2
JB		 749{
750 struct drm_i915_private *dev_priv = dev->dev_private;
ab7ad7f6
KP		 751
752 if (INTEL_INFO(dev)->gen >= 4) {
58e10eb9 753 int reg = PIPECONF(pipe);
ab7ad7f6
KP		 754
755 /* Wait for the Pipe State to go off */
58e10eb9
CW		 756 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
757 100))
ab7ad7f6
KP		 758 DRM_DEBUG_KMS("pipe_off wait timed out\n");
759 } else {
760 u32 last_line;
58e10eb9 761 int reg = PIPEDSL(pipe);
ab7ad7f6
KP		 762 unsigned long timeout = jiffies + msecs_to_jiffies(100);
763
764 /* Wait for the display line to settle */
765 do {
58e10eb9 766 last_line = I915_READ(reg) & DSL_LINEMASK;
ab7ad7f6 767 mdelay(5);
58e10eb9 768 } while (((I915_READ(reg) & DSL_LINEMASK) != last_line) &&
ab7ad7f6
KP		 769 time_after(timeout, jiffies));
770 if (time_after(jiffies, timeout))
771 DRM_DEBUG_KMS("pipe_off wait timed out\n");
772 }
79e53945
JB		 773}
774
b24e7179
JB		 775static const char *state_string(bool enabled)
776{
777 return enabled ? "on" : "off";
778}
779
780/* Only for pre-ILK configs */
781static void assert_pll(struct drm_i915_private *dev_priv,
782 enum pipe pipe, bool state)
783{
784 int reg;
785 u32 val;
786 bool cur_state;
787
788 reg = DPLL(pipe);
789 val = I915_READ(reg);
790 cur_state = !!(val & DPLL_VCO_ENABLE);
791 WARN(cur_state != state,
792 "PLL state assertion failure (expected %s, current %s)\n",
793 state_string(state), state_string(cur_state));
794}
795#define assert_pll_enabled(d, p) assert_pll(d, p, true)
796#define assert_pll_disabled(d, p) assert_pll(d, p, false)
797
040484af
JB		 798/* For ILK+ */
799static void assert_pch_pll(struct drm_i915_private *dev_priv,
800 enum pipe pipe, bool state)
801{
802 int reg;
803 u32 val;
804 bool cur_state;
805
d3ccbe86
JB		 806 if (HAS_PCH_CPT(dev_priv->dev)) {
807 u32 pch_dpll;
808
809 pch_dpll = I915_READ(PCH_DPLL_SEL);
810
811 /* Make sure the selected PLL is enabled to the transcoder */
812 WARN(!((pch_dpll >> (4 * pipe)) & 8),
813 "transcoder %d PLL not enabled\n", pipe);
814
815 /* Convert the transcoder pipe number to a pll pipe number */
816 pipe = (pch_dpll >> (4 * pipe)) & 1;
817 }
818
040484af
JB		 819 reg = PCH_DPLL(pipe);
820 val = I915_READ(reg);
821 cur_state = !!(val & DPLL_VCO_ENABLE);
822 WARN(cur_state != state,
823 "PCH PLL state assertion failure (expected %s, current %s)\n",
824 state_string(state), state_string(cur_state));
825}
826#define assert_pch_pll_enabled(d, p) assert_pch_pll(d, p, true)
827#define assert_pch_pll_disabled(d, p) assert_pch_pll(d, p, false)
828
829static void assert_fdi_tx(struct drm_i915_private *dev_priv,
830 enum pipe pipe, bool state)
831{
832 int reg;
833 u32 val;
834 bool cur_state;
835
836 reg = FDI_TX_CTL(pipe);
837 val = I915_READ(reg);
838 cur_state = !!(val & FDI_TX_ENABLE);
839 WARN(cur_state != state,
840 "FDI TX state assertion failure (expected %s, current %s)\n",
841 state_string(state), state_string(cur_state));
842}
843#define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
844#define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
845
846static void assert_fdi_rx(struct drm_i915_private *dev_priv,
847 enum pipe pipe, bool state)
848{
849 int reg;
850 u32 val;
851 bool cur_state;
852
853 reg = FDI_RX_CTL(pipe);
854 val = I915_READ(reg);
855 cur_state = !!(val & FDI_RX_ENABLE);
856 WARN(cur_state != state,
857 "FDI RX state assertion failure (expected %s, current %s)\n",
858 state_string(state), state_string(cur_state));
859}
860#define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
861#define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
862
863static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
864 enum pipe pipe)
865{
866 int reg;
867 u32 val;
868
869 /* ILK FDI PLL is always enabled */
870 if (dev_priv->info->gen == 5)
871 return;
872
873 reg = FDI_TX_CTL(pipe);
874 val = I915_READ(reg);
875 WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
876}
877
878static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
879 enum pipe pipe)
880{
881 int reg;
882 u32 val;
883
884 reg = FDI_RX_CTL(pipe);
885 val = I915_READ(reg);
886 WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
887}
888
ea0760cf
JB		 889static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
890 enum pipe pipe)
891{
892 int pp_reg, lvds_reg;
893 u32 val;
894 enum pipe panel_pipe = PIPE_A;
0de3b485 895 bool locked = true;
ea0760cf
JB		 896
897 if (HAS_PCH_SPLIT(dev_priv->dev)) {
898 pp_reg = PCH_PP_CONTROL;
899 lvds_reg = PCH_LVDS;
900 } else {
901 pp_reg = PP_CONTROL;
902 lvds_reg = LVDS;
903 }
904
905 val = I915_READ(pp_reg);
906 if (!(val & PANEL_POWER_ON) ||
907 ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
908 locked = false;
909
910 if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
911 panel_pipe = PIPE_B;
912
913 WARN(panel_pipe == pipe && locked,
914 "panel assertion failure, pipe %c regs locked\n",
9db4a9c7 915 pipe_name(pipe));
ea0760cf
JB		 916}
917
b840d907
JB		 918void assert_pipe(struct drm_i915_private *dev_priv,
919 enum pipe pipe, bool state)
b24e7179
JB		 920{
921 int reg;
922 u32 val;
63d7bbe9 923 bool cur_state;
b24e7179
JB		 924
925 reg = PIPECONF(pipe);
926 val = I915_READ(reg);
63d7bbe9
JB		 927 cur_state = !!(val & PIPECONF_ENABLE);
928 WARN(cur_state != state,
929 "pipe %c assertion failure (expected %s, current %s)\n",
9db4a9c7 930 pipe_name(pipe), state_string(state), state_string(cur_state));
b24e7179
JB		 931}
932
933static void assert_plane_enabled(struct drm_i915_private *dev_priv,
934 enum plane plane)
935{
936 int reg;
937 u32 val;
938
939 reg = DSPCNTR(plane);
940 val = I915_READ(reg);
941 WARN(!(val & DISPLAY_PLANE_ENABLE),
942 "plane %c assertion failure, should be active but is disabled\n",
9db4a9c7 943 plane_name(plane));
b24e7179
JB		 944}
945
946static void assert_planes_disabled(struct drm_i915_private *dev_priv,
947 enum pipe pipe)
948{
949 int reg, i;
950 u32 val;
951 int cur_pipe;
952
19ec1358
JB		 953 /* Planes are fixed to pipes on ILK+ */
954 if (HAS_PCH_SPLIT(dev_priv->dev))
955 return;
956
b24e7179
JB		 957 /* Need to check both planes against the pipe */
958 for (i = 0; i < 2; i++) {
959 reg = DSPCNTR(i);
960 val = I915_READ(reg);
961 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
962 DISPPLANE_SEL_PIPE_SHIFT;
963 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
9db4a9c7
JB		 964 "plane %c assertion failure, should be off on pipe %c but is still active\n",
965 plane_name(i), pipe_name(pipe));
b24e7179
JB		 966 }
967}
968
92f2584a
JB		 969static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
970{
971 u32 val;
972 bool enabled;
973
974 val = I915_READ(PCH_DREF_CONTROL);
975 enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
976 DREF_SUPERSPREAD_SOURCE_MASK));
977 WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
978}
979
980static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
981 enum pipe pipe)
982{
983 int reg;
984 u32 val;
985 bool enabled;
986
987 reg = TRANSCONF(pipe);
988 val = I915_READ(reg);
989 enabled = !!(val & TRANS_ENABLE);
9db4a9c7
JB		 990 WARN(enabled,
991 "transcoder assertion failed, should be off on pipe %c but is still active\n",
992 pipe_name(pipe));
92f2584a
JB		 993}
994
4e634389
KP		 995static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
996 enum pipe pipe, u32 port_sel, u32 val)
f0575e92
KP		 997{
998 if ((val & DP_PORT_EN) == 0)
999 return false;
1000
1001 if (HAS_PCH_CPT(dev_priv->dev)) {
1002 u32 trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1003 u32 trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1004 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1005 return false;
1006 } else {
1007 if ((val & DP_PIPE_MASK) != (pipe << 30))
1008 return false;
1009 }
1010 return true;
1011}
1012
1519b995
KP		 1013static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1014 enum pipe pipe, u32 val)
1015{
1016 if ((val & PORT_ENABLE) == 0)
1017 return false;
1018
1019 if (HAS_PCH_CPT(dev_priv->dev)) {
1020 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1021 return false;
1022 } else {
1023 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1024 return false;
1025 }
1026 return true;
1027}
1028
1029static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1030 enum pipe pipe, u32 val)
1031{
1032 if ((val & LVDS_PORT_EN) == 0)
1033 return false;
1034
1035 if (HAS_PCH_CPT(dev_priv->dev)) {
1036 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1037 return false;
1038 } else {
1039 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1040 return false;
1041 }
1042 return true;
1043}
1044
1045static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1046 enum pipe pipe, u32 val)
1047{
1048 if ((val & ADPA_DAC_ENABLE) == 0)
1049 return false;
1050 if (HAS_PCH_CPT(dev_priv->dev)) {
1051 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1052 return false;
1053 } else {
1054 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1055 return false;
1056 }
1057 return true;
1058}
1059
291906f1 1060static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
f0575e92 1061 enum pipe pipe, int reg, u32 port_sel)
291906f1 1062{
47a05eca 1063 u32 val = I915_READ(reg);
4e634389 1064 WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
291906f1 1065 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1066 reg, pipe_name(pipe));
291906f1
JB		 1067}
1068
1069static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1070 enum pipe pipe, int reg)
1071{
47a05eca 1072 u32 val = I915_READ(reg);
1519b995 1073 WARN(hdmi_pipe_enabled(dev_priv, val, pipe),
291906f1 1074 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
9db4a9c7 1075 reg, pipe_name(pipe));
291906f1
JB		 1076}
1077
1078static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1079 enum pipe pipe)
1080{
1081 int reg;
1082 u32 val;
291906f1 1083
f0575e92
KP		 1084 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1085 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1086 assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
291906f1
JB		 1087
1088 reg = PCH_ADPA;
1089 val = I915_READ(reg);
1519b995 1090 WARN(adpa_pipe_enabled(dev_priv, val, pipe),
291906f1 1091 "PCH VGA enabled on transcoder %c, should be disabled\n",
9db4a9c7 1092 pipe_name(pipe));
291906f1
JB		 1093
1094 reg = PCH_LVDS;
1095 val = I915_READ(reg);
1519b995 1096 WARN(lvds_pipe_enabled(dev_priv, val, pipe),
291906f1 1097 "PCH LVDS enabled on transcoder %c, should be disabled\n",
9db4a9c7 1098 pipe_name(pipe));
291906f1
JB		 1099
1100 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1101 assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1102 assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1103}
1104
63d7bbe9
JB		 1105/**
1106 * intel_enable_pll - enable a PLL
1107 * @dev_priv: i915 private structure
1108 * @pipe: pipe PLL to enable
1109 *
1110 * Enable @pipe's PLL so we can start pumping pixels from a plane. Check to
1111 * make sure the PLL reg is writable first though, since the panel write
1112 * protect mechanism may be enabled.
1113 *
1114 * Note! This is for pre-ILK only.
1115 */
1116static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1117{
1118 int reg;
1119 u32 val;
1120
1121 /* No really, not for ILK+ */
1122 BUG_ON(dev_priv->info->gen >= 5);
1123
1124 /* PLL is protected by panel, make sure we can write it */
1125 if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1126 assert_panel_unlocked(dev_priv, pipe);
1127
1128 reg = DPLL(pipe);
1129 val = I915_READ(reg);
1130 val |= DPLL_VCO_ENABLE;
1131
1132 /* We do this three times for luck */
1133 I915_WRITE(reg, val);
1134 POSTING_READ(reg);
1135 udelay(150); /* wait for warmup */
1136 I915_WRITE(reg, val);
1137 POSTING_READ(reg);
1138 udelay(150); /* wait for warmup */
1139 I915_WRITE(reg, val);
1140 POSTING_READ(reg);
1141 udelay(150); /* wait for warmup */
1142}
1143
1144/**
1145 * intel_disable_pll - disable a PLL
1146 * @dev_priv: i915 private structure
1147 * @pipe: pipe PLL to disable
1148 *
1149 * Disable the PLL for @pipe, making sure the pipe is off first.
1150 *
1151 * Note! This is for pre-ILK only.
1152 */
1153static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1154{
1155 int reg;
1156 u32 val;
1157
1158 /* Don't disable pipe A or pipe A PLLs if needed */
1159 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1160 return;
1161
1162 /* Make sure the pipe isn't still relying on us */
1163 assert_pipe_disabled(dev_priv, pipe);
1164
1165 reg = DPLL(pipe);
1166 val = I915_READ(reg);
1167 val &= ~DPLL_VCO_ENABLE;
1168 I915_WRITE(reg, val);
1169 POSTING_READ(reg);
1170}
1171
92f2584a
JB		 1172/**
1173 * intel_enable_pch_pll - enable PCH PLL
1174 * @dev_priv: i915 private structure
1175 * @pipe: pipe PLL to enable
1176 *
1177 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1178 * drives the transcoder clock.
1179 */
1180static void intel_enable_pch_pll(struct drm_i915_private *dev_priv,
1181 enum pipe pipe)
1182{
1183 int reg;
1184 u32 val;
1185
4c609cb8
JB		 1186 if (pipe > 1)
1187 return;
1188
92f2584a
JB		 1189 /* PCH only available on ILK+ */
1190 BUG_ON(dev_priv->info->gen < 5);
1191
1192 /* PCH refclock must be enabled first */
1193 assert_pch_refclk_enabled(dev_priv);
1194
1195 reg = PCH_DPLL(pipe);
1196 val = I915_READ(reg);
1197 val |= DPLL_VCO_ENABLE;
1198 I915_WRITE(reg, val);
1199 POSTING_READ(reg);
1200 udelay(200);
1201}
1202
1203static void intel_disable_pch_pll(struct drm_i915_private *dev_priv,
1204 enum pipe pipe)
1205{
1206 int reg;
7a419866
JB		 1207 u32 val, pll_mask = TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL,
1208 pll_sel = TRANSC_DPLL_ENABLE;
92f2584a 1209
4c609cb8
JB		 1210 if (pipe > 1)
1211 return;
1212
92f2584a
JB		 1213 /* PCH only available on ILK+ */
1214 BUG_ON(dev_priv->info->gen < 5);
1215
1216 /* Make sure transcoder isn't still depending on us */
1217 assert_transcoder_disabled(dev_priv, pipe);
1218
7a419866
JB		 1219 if (pipe == 0)
1220 pll_sel |= TRANSC_DPLLA_SEL;
1221 else if (pipe == 1)
1222 pll_sel |= TRANSC_DPLLB_SEL;
1223
1224
1225 if ((I915_READ(PCH_DPLL_SEL) & pll_mask) == pll_sel)
1226 return;
1227
92f2584a
JB		 1228 reg = PCH_DPLL(pipe);
1229 val = I915_READ(reg);
1230 val &= ~DPLL_VCO_ENABLE;
1231 I915_WRITE(reg, val);
1232 POSTING_READ(reg);
1233 udelay(200);
1234}
1235
040484af
JB		 1236static void intel_enable_transcoder(struct drm_i915_private *dev_priv,
1237 enum pipe pipe)
1238{
1239 int reg;
1240 u32 val;
1241
1242 /* PCH only available on ILK+ */
1243 BUG_ON(dev_priv->info->gen < 5);
1244
1245 /* Make sure PCH DPLL is enabled */
1246 assert_pch_pll_enabled(dev_priv, pipe);
1247
1248 /* FDI must be feeding us bits for PCH ports */
1249 assert_fdi_tx_enabled(dev_priv, pipe);
1250 assert_fdi_rx_enabled(dev_priv, pipe);
1251
1252 reg = TRANSCONF(pipe);
1253 val = I915_READ(reg);
e9bcff5c
JB		 1254
1255 if (HAS_PCH_IBX(dev_priv->dev)) {
1256 /*
1257 * make the BPC in transcoder be consistent with
1258 * that in pipeconf reg.
1259 */
1260 val &= ~PIPE_BPC_MASK;
1261 val |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
1262 }
040484af
JB		 1263 I915_WRITE(reg, val | TRANS_ENABLE);
1264 if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1265 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1266}
1267
1268static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
1269 enum pipe pipe)
1270{
1271 int reg;
1272 u32 val;
1273
1274 /* FDI relies on the transcoder */
1275 assert_fdi_tx_disabled(dev_priv, pipe);
1276 assert_fdi_rx_disabled(dev_priv, pipe);
1277
291906f1
JB		 1278 /* Ports must be off as well */
1279 assert_pch_ports_disabled(dev_priv, pipe);
1280
040484af
JB		 1281 reg = TRANSCONF(pipe);
1282 val = I915_READ(reg);
1283 val &= ~TRANS_ENABLE;
1284 I915_WRITE(reg, val);
1285 /* wait for PCH transcoder off, transcoder state */
1286 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
4c9c18c2 1287 DRM_ERROR("failed to disable transcoder %d\n", pipe);
040484af
JB		 1288}
1289
b24e7179 1290/**
309cfea8 1291 * intel_enable_pipe - enable a pipe, asserting requirements
b24e7179
JB		 1292 * @dev_priv: i915 private structure
1293 * @pipe: pipe to enable
040484af 1294 * @pch_port: on ILK+, is this pipe driving a PCH port or not
b24e7179
JB		 1295 *
1296 * Enable @pipe, making sure that various hardware specific requirements
1297 * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1298 *
1299 * @pipe should be %PIPE_A or %PIPE_B.
1300 *
1301 * Will wait until the pipe is actually running (i.e. first vblank) before
1302 * returning.
1303 */
040484af
JB		 1304static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1305 bool pch_port)
b24e7179
JB		 1306{
1307 int reg;
1308 u32 val;
1309
1310 /*
1311 * A pipe without a PLL won't actually be able to drive bits from
1312 * a plane. On ILK+ the pipe PLLs are integrated, so we don't
1313 * need the check.
1314 */
1315 if (!HAS_PCH_SPLIT(dev_priv->dev))
1316 assert_pll_enabled(dev_priv, pipe);
040484af
JB		 1317 else {
1318 if (pch_port) {
1319 /* if driving the PCH, we need FDI enabled */
1320 assert_fdi_rx_pll_enabled(dev_priv, pipe);
1321 assert_fdi_tx_pll_enabled(dev_priv, pipe);
1322 }
1323 /* FIXME: assert CPU port conditions for SNB+ */
1324 }
b24e7179
JB		 1325
1326 reg = PIPECONF(pipe);
1327 val = I915_READ(reg);
00d70b15
CW		 1328 if (val & PIPECONF_ENABLE)
1329 return;
1330
1331 I915_WRITE(reg, val | PIPECONF_ENABLE);
b24e7179
JB		 1332 intel_wait_for_vblank(dev_priv->dev, pipe);
1333}
1334
1335/**
309cfea8 1336 * intel_disable_pipe - disable a pipe, asserting requirements
b24e7179
JB		 1337 * @dev_priv: i915 private structure
1338 * @pipe: pipe to disable
1339 *
1340 * Disable @pipe, making sure that various hardware specific requirements
1341 * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1342 *
1343 * @pipe should be %PIPE_A or %PIPE_B.
1344 *
1345 * Will wait until the pipe has shut down before returning.
1346 */
1347static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1348 enum pipe pipe)
1349{
1350 int reg;
1351 u32 val;
1352
1353 /*
1354 * Make sure planes won't keep trying to pump pixels to us,
1355 * or we might hang the display.
1356 */
1357 assert_planes_disabled(dev_priv, pipe);
1358
1359 /* Don't disable pipe A or pipe A PLLs if needed */
1360 if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1361 return;
1362
1363 reg = PIPECONF(pipe);
1364 val = I915_READ(reg);
00d70b15
CW		 1365 if ((val & PIPECONF_ENABLE) == 0)
1366 return;
1367
1368 I915_WRITE(reg, val & ~PIPECONF_ENABLE);
b24e7179
JB		 1369 intel_wait_for_pipe_off(dev_priv->dev, pipe);
1370}
1371
d74362c9
KP		 1372/*
1373 * Plane regs are double buffered, going from enabled->disabled needs a
1374 * trigger in order to latch. The display address reg provides this.
1375 */
1376static void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1377 enum plane plane)
1378{
1379 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1380 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1381}
1382
b24e7179
JB		 1383/**
1384 * intel_enable_plane - enable a display plane on a given pipe
1385 * @dev_priv: i915 private structure
1386 * @plane: plane to enable
1387 * @pipe: pipe being fed
1388 *
1389 * Enable @plane on @pipe, making sure that @pipe is running first.
1390 */
1391static void intel_enable_plane(struct drm_i915_private *dev_priv,
1392 enum plane plane, enum pipe pipe)
1393{
1394 int reg;
1395 u32 val;
1396
1397 /* If the pipe isn't enabled, we can't pump pixels and may hang */
1398 assert_pipe_enabled(dev_priv, pipe);
1399
1400 reg = DSPCNTR(plane);
1401 val = I915_READ(reg);
00d70b15
CW		 1402 if (val & DISPLAY_PLANE_ENABLE)
1403 return;
1404
1405 I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
d74362c9 1406 intel_flush_display_plane(dev_priv, plane);
b24e7179
JB		 1407 intel_wait_for_vblank(dev_priv->dev, pipe);
1408}
1409
b24e7179
JB		 1410/**
1411 * intel_disable_plane - disable a display plane
1412 * @dev_priv: i915 private structure
1413 * @plane: plane to disable
1414 * @pipe: pipe consuming the data
1415 *
1416 * Disable @plane; should be an independent operation.
1417 */
1418static void intel_disable_plane(struct drm_i915_private *dev_priv,
1419 enum plane plane, enum pipe pipe)
1420{
1421 int reg;
1422 u32 val;
1423
1424 reg = DSPCNTR(plane);
1425 val = I915_READ(reg);
00d70b15
CW		 1426 if ((val & DISPLAY_PLANE_ENABLE) == 0)
1427 return;
1428
1429 I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
b24e7179
JB		 1430 intel_flush_display_plane(dev_priv, plane);
1431 intel_wait_for_vblank(dev_priv->dev, pipe);
1432}
1433
47a05eca 1434static void disable_pch_dp(struct drm_i915_private *dev_priv,
f0575e92 1435 enum pipe pipe, int reg, u32 port_sel)
47a05eca
JB		 1436{
1437 u32 val = I915_READ(reg);
4e634389 1438 if (dp_pipe_enabled(dev_priv, pipe, port_sel, val)) {
f0575e92 1439 DRM_DEBUG_KMS("Disabling pch dp %x on pipe %d\n", reg, pipe);
47a05eca 1440 I915_WRITE(reg, val & ~DP_PORT_EN);
f0575e92 1441 }
47a05eca
JB		 1442}
1443
1444static void disable_pch_hdmi(struct drm_i915_private *dev_priv,
1445 enum pipe pipe, int reg)
1446{
1447 u32 val = I915_READ(reg);
1519b995 1448 if (hdmi_pipe_enabled(dev_priv, val, pipe)) {
f0575e92
KP		 1449 DRM_DEBUG_KMS("Disabling pch HDMI %x on pipe %d\n",
1450 reg, pipe);
47a05eca 1451 I915_WRITE(reg, val & ~PORT_ENABLE);
f0575e92 1452 }
47a05eca
JB		 1453}
1454
1455/* Disable any ports connected to this transcoder */
1456static void intel_disable_pch_ports(struct drm_i915_private *dev_priv,
1457 enum pipe pipe)
1458{
1459 u32 reg, val;
1460
1461 val = I915_READ(PCH_PP_CONTROL);
1462 I915_WRITE(PCH_PP_CONTROL, val | PANEL_UNLOCK_REGS);
1463
f0575e92
KP		 1464 disable_pch_dp(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1465 disable_pch_dp(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1466 disable_pch_dp(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
47a05eca
JB		 1467
1468 reg = PCH_ADPA;
1469 val = I915_READ(reg);
1519b995 1470 if (adpa_pipe_enabled(dev_priv, val, pipe))
47a05eca
JB		 1471 I915_WRITE(reg, val & ~ADPA_DAC_ENABLE);
1472
1473 reg = PCH_LVDS;
1474 val = I915_READ(reg);
1519b995
KP		 1475 if (lvds_pipe_enabled(dev_priv, val, pipe)) {
1476 DRM_DEBUG_KMS("disable lvds on pipe %d val 0x%08x\n", pipe, val);
47a05eca
JB		 1477 I915_WRITE(reg, val & ~LVDS_PORT_EN);
1478 POSTING_READ(reg);
1479 udelay(100);
1480 }
1481
1482 disable_pch_hdmi(dev_priv, pipe, HDMIB);
1483 disable_pch_hdmi(dev_priv, pipe, HDMIC);
1484 disable_pch_hdmi(dev_priv, pipe, HDMID);
1485}
1486
43a9539f
CW		 1487static void i8xx_disable_fbc(struct drm_device *dev)
1488{
1489 struct drm_i915_private *dev_priv = dev->dev_private;
1490 u32 fbc_ctl;
1491
1492 /* Disable compression */
1493 fbc_ctl = I915_READ(FBC_CONTROL);
1494 if ((fbc_ctl & FBC_CTL_EN) == 0)
1495 return;
1496
1497 fbc_ctl &= ~FBC_CTL_EN;
1498 I915_WRITE(FBC_CONTROL, fbc_ctl);
1499
1500 /* Wait for compressing bit to clear */
1501 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1502 DRM_DEBUG_KMS("FBC idle timed out\n");
1503 return;
1504 }
1505
1506 DRM_DEBUG_KMS("disabled FBC\n");
1507}
1508
80824003
JB		 1509static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1510{
1511 struct drm_device *dev = crtc->dev;
1512 struct drm_i915_private *dev_priv = dev->dev_private;
1513 struct drm_framebuffer *fb = crtc->fb;
1514 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1515 struct drm_i915_gem_object *obj = intel_fb->obj;
80824003 1516 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
016b9b61 1517 int cfb_pitch;
80824003
JB		 1518 int plane, i;
1519 u32 fbc_ctl, fbc_ctl2;
1520
016b9b61 1521 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
01f2c773
VS		 1522 if (fb->pitches[0] < cfb_pitch)
1523 cfb_pitch = fb->pitches[0];
80824003
JB		 1524
1525 /* FBC_CTL wants 64B units */
016b9b61
CW		 1526 cfb_pitch = (cfb_pitch / 64) - 1;
1527 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
80824003
JB		 1528
1529 /* Clear old tags */
1530 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1531 I915_WRITE(FBC_TAG + (i * 4), 0);
1532
1533 /* Set it up... */
de568510
CW		 1534 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
1535 fbc_ctl2 |= plane;
80824003
JB		 1536 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1537 I915_WRITE(FBC_FENCE_OFF, crtc->y);
1538
1539 /* enable it... */
1540 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
ee25df2b 1541 if (IS_I945GM(dev))
49677901 1542 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
016b9b61 1543 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
80824003 1544 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
016b9b61 1545 fbc_ctl |= obj->fence_reg;
80824003
JB		 1546 I915_WRITE(FBC_CONTROL, fbc_ctl);
1547
016b9b61
CW		 1548 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
1549 cfb_pitch, crtc->y, intel_crtc->plane);
80824003
JB		 1550}
1551
ee5382ae 1552static bool i8xx_fbc_enabled(struct drm_device *dev)
80824003 1553{
80824003
JB		 1554 struct drm_i915_private *dev_priv = dev->dev_private;
1555
1556 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1557}
1558
74dff282
JB		 1559static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1560{
1561 struct drm_device *dev = crtc->dev;
1562 struct drm_i915_private *dev_priv = dev->dev_private;
1563 struct drm_framebuffer *fb = crtc->fb;
1564 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1565 struct drm_i915_gem_object *obj = intel_fb->obj;
74dff282 1566 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1567 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
74dff282
JB		 1568 unsigned long stall_watermark = 200;
1569 u32 dpfc_ctl;
1570
74dff282 1571 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
016b9b61 1572 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
de568510 1573 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
74dff282 1574
74dff282
JB		 1575 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1576 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1577 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1578 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1579
1580 /* enable it... */
1581 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1582
28c97730 1583 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
74dff282
JB		 1584}
1585
43a9539f 1586static void g4x_disable_fbc(struct drm_device *dev)
74dff282
JB		 1587{
1588 struct drm_i915_private *dev_priv = dev->dev_private;
1589 u32 dpfc_ctl;
1590
1591 /* Disable compression */
1592 dpfc_ctl = I915_READ(DPFC_CONTROL);
bed4a673
CW		 1593 if (dpfc_ctl & DPFC_CTL_EN) {
1594 dpfc_ctl &= ~DPFC_CTL_EN;
1595 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
74dff282 1596
bed4a673
CW		 1597 DRM_DEBUG_KMS("disabled FBC\n");
1598 }
74dff282
JB		 1599}
1600
ee5382ae 1601static bool g4x_fbc_enabled(struct drm_device *dev)
74dff282 1602{
74dff282
JB		 1603 struct drm_i915_private *dev_priv = dev->dev_private;
1604
1605 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1606}
1607
4efe0708
JB		 1608static void sandybridge_blit_fbc_update(struct drm_device *dev)
1609{
1610 struct drm_i915_private *dev_priv = dev->dev_private;
1611 u32 blt_ecoskpd;
1612
1613 /* Make sure blitter notifies FBC of writes */
fcca7926 1614 gen6_gt_force_wake_get(dev_priv);
4efe0708
JB		 1615 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
1616 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
1617 GEN6_BLITTER_LOCK_SHIFT;
1618 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1619 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
1620 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1621 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
1622 GEN6_BLITTER_LOCK_SHIFT);
1623 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
1624 POSTING_READ(GEN6_BLITTER_ECOSKPD);
fcca7926 1625 gen6_gt_force_wake_put(dev_priv);
4efe0708
JB		 1626}
1627
b52eb4dc
ZY		 1628static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1629{
1630 struct drm_device *dev = crtc->dev;
1631 struct drm_i915_private *dev_priv = dev->dev_private;
1632 struct drm_framebuffer *fb = crtc->fb;
1633 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 1634 struct drm_i915_gem_object *obj = intel_fb->obj;
b52eb4dc 1635 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5eddb70b 1636 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
b52eb4dc
ZY		 1637 unsigned long stall_watermark = 200;
1638 u32 dpfc_ctl;
1639
bed4a673 1640 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
b52eb4dc
ZY		 1641 dpfc_ctl &= DPFC_RESERVED;
1642 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
9ce9d069
CW		 1643 /* Set persistent mode for front-buffer rendering, ala X. */
1644 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
016b9b61 1645 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
de568510 1646 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
b52eb4dc 1647
b52eb4dc
ZY		 1648 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1649 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1650 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1651 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
05394f39 1652 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
b52eb4dc 1653 /* enable it... */
bed4a673 1654 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
b52eb4dc 1655
9c04f015
YL		 1656 if (IS_GEN6(dev)) {
1657 I915_WRITE(SNB_DPFC_CTL_SA,
016b9b61 1658 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
9c04f015 1659 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
4efe0708 1660 sandybridge_blit_fbc_update(dev);
9c04f015
YL		 1661 }
1662
b52eb4dc
ZY		 1663 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1664}
1665
43a9539f 1666static void ironlake_disable_fbc(struct drm_device *dev)
b52eb4dc
ZY		 1667{
1668 struct drm_i915_private *dev_priv = dev->dev_private;
1669 u32 dpfc_ctl;
1670
1671 /* Disable compression */
1672 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
bed4a673
CW		 1673 if (dpfc_ctl & DPFC_CTL_EN) {
1674 dpfc_ctl &= ~DPFC_CTL_EN;
1675 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
b52eb4dc 1676
bed4a673
CW		 1677 DRM_DEBUG_KMS("disabled FBC\n");
1678 }
b52eb4dc
ZY		 1679}
1680
1681static bool ironlake_fbc_enabled(struct drm_device *dev)
1682{
1683 struct drm_i915_private *dev_priv = dev->dev_private;
1684
1685 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1686}
1687
ee5382ae
AJ		 1688bool intel_fbc_enabled(struct drm_device *dev)
1689{
1690 struct drm_i915_private *dev_priv = dev->dev_private;
1691
1692 if (!dev_priv->display.fbc_enabled)
1693 return false;
1694
1695 return dev_priv->display.fbc_enabled(dev);
1696}
1697
1630fe75
CW		 1698static void intel_fbc_work_fn(struct work_struct *__work)
1699{
1700 struct intel_fbc_work *work =
1701 container_of(to_delayed_work(__work),
1702 struct intel_fbc_work, work);
1703 struct drm_device *dev = work->crtc->dev;
1704 struct drm_i915_private *dev_priv = dev->dev_private;
1705
1706 mutex_lock(&dev->struct_mutex);
1707 if (work == dev_priv->fbc_work) {
1708 /* Double check that we haven't switched fb without cancelling
1709 * the prior work.
1710 */
016b9b61 1711 if (work->crtc->fb == work->fb) {
1630fe75
CW		 1712 dev_priv->display.enable_fbc(work->crtc,
1713 work->interval);
1714
016b9b61
CW		 1715 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
1716 dev_priv->cfb_fb = work->crtc->fb->base.id;
1717 dev_priv->cfb_y = work->crtc->y;
1718 }
1719
1630fe75
CW		 1720 dev_priv->fbc_work = NULL;
1721 }
1722 mutex_unlock(&dev->struct_mutex);
1723
1724 kfree(work);
1725}
1726
1727static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
1728{
1729 if (dev_priv->fbc_work == NULL)
1730 return;
1731
1732 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
1733
1734 /* Synchronisation is provided by struct_mutex and checking of
1735 * dev_priv->fbc_work, so we can perform the cancellation
1736 * entirely asynchronously.
1737 */
1738 if (cancel_delayed_work(&dev_priv->fbc_work->work))
1739 /* tasklet was killed before being run, clean up */
1740 kfree(dev_priv->fbc_work);
1741
1742 /* Mark the work as no longer wanted so that if it does
1743 * wake-up (because the work was already running and waiting
1744 * for our mutex), it will discover that is no longer
1745 * necessary to run.
1746 */
1747 dev_priv->fbc_work = NULL;
1748}
1749
43a9539f 1750static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
ee5382ae 1751{
1630fe75
CW		 1752 struct intel_fbc_work *work;
1753 struct drm_device *dev = crtc->dev;
1754 struct drm_i915_private *dev_priv = dev->dev_private;
ee5382ae
AJ		 1755
1756 if (!dev_priv->display.enable_fbc)
1757 return;
1758
1630fe75
CW		 1759 intel_cancel_fbc_work(dev_priv);
1760
1761 work = kzalloc(sizeof *work, GFP_KERNEL);
1762 if (work == NULL) {
1763 dev_priv->display.enable_fbc(crtc, interval);
1764 return;
1765 }
1766
1767 work->crtc = crtc;
1768 work->fb = crtc->fb;
1769 work->interval = interval;
1770 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
1771
1772 dev_priv->fbc_work = work;
1773
1774 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
1775
1776 /* Delay the actual enabling to let pageflipping cease and the
016b9b61
CW		 1777 * display to settle before starting the compression. Note that
1778 * this delay also serves a second purpose: it allows for a
1779 * vblank to pass after disabling the FBC before we attempt
1780 * to modify the control registers.
1630fe75
CW		 1781 *
1782 * A more complicated solution would involve tracking vblanks
1783 * following the termination of the page-flipping sequence
1784 * and indeed performing the enable as a co-routine and not
1785 * waiting synchronously upon the vblank.
1786 */
1787 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
ee5382ae
AJ		 1788}
1789
1790void intel_disable_fbc(struct drm_device *dev)
1791{
1792 struct drm_i915_private *dev_priv = dev->dev_private;
1793
1630fe75
CW		 1794 intel_cancel_fbc_work(dev_priv);
1795
ee5382ae
AJ		 1796 if (!dev_priv->display.disable_fbc)
1797 return;
1798
1799 dev_priv->display.disable_fbc(dev);
016b9b61 1800 dev_priv->cfb_plane = -1;
ee5382ae
AJ		 1801}
1802
80824003
JB		 1803/**
1804 * intel_update_fbc - enable/disable FBC as needed
bed4a673 1805 * @dev: the drm_device
80824003
JB		 1806 *
1807 * Set up the framebuffer compression hardware at mode set time. We
1808 * enable it if possible:
1809 * - plane A only (on pre-965)
1810 * - no pixel mulitply/line duplication
1811 * - no alpha buffer discard
1812 * - no dual wide
1813 * - framebuffer <= 2048 in width, 1536 in height
1814 *
1815 * We can't assume that any compression will take place (worst case),
1816 * so the compressed buffer has to be the same size as the uncompressed
1817 * one. It also must reside (along with the line length buffer) in
1818 * stolen memory.
1819 *
1820 * We need to enable/disable FBC on a global basis.
1821 */
bed4a673 1822static void intel_update_fbc(struct drm_device *dev)
80824003 1823{
80824003 1824 struct drm_i915_private *dev_priv = dev->dev_private;
bed4a673
CW		 1825 struct drm_crtc *crtc = NULL, *tmp_crtc;
1826 struct intel_crtc *intel_crtc;
1827 struct drm_framebuffer *fb;
80824003 1828 struct intel_framebuffer *intel_fb;
05394f39 1829 struct drm_i915_gem_object *obj;
cd0de039 1830 int enable_fbc;
9c928d16
JB		 1831
1832 DRM_DEBUG_KMS("\n");
80824003
JB		 1833
1834 if (!i915_powersave)
1835 return;
1836
ee5382ae 1837 if (!I915_HAS_FBC(dev))
e70236a8
JB		 1838 return;
1839
80824003
JB		 1840 /*
1841 * If FBC is already on, we just have to verify that we can
1842 * keep it that way...
1843 * Need to disable if:
9c928d16 1844 * - more than one pipe is active
80824003
JB		 1845 * - changing FBC params (stride, fence, mode)
1846 * - new fb is too large to fit in compressed buffer
1847 * - going to an unsupported config (interlace, pixel multiply, etc.)
1848 */
9c928d16 1849 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
d210246a 1850 if (tmp_crtc->enabled && tmp_crtc->fb) {
bed4a673
CW		 1851 if (crtc) {
1852 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1853 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1854 goto out_disable;
1855 }
1856 crtc = tmp_crtc;
1857 }
9c928d16 1858 }
bed4a673
CW		 1859
1860 if (!crtc || crtc->fb == NULL) {
1861 DRM_DEBUG_KMS("no output, disabling\n");
1862 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
9c928d16
JB		 1863 goto out_disable;
1864 }
bed4a673
CW		 1865
1866 intel_crtc = to_intel_crtc(crtc);
1867 fb = crtc->fb;
1868 intel_fb = to_intel_framebuffer(fb);
05394f39 1869 obj = intel_fb->obj;
bed4a673 1870
cd0de039
KP		 1871 enable_fbc = i915_enable_fbc;
1872 if (enable_fbc < 0) {
1873 DRM_DEBUG_KMS("fbc set to per-chip default\n");
1874 enable_fbc = 1;
d56d8b28 1875 if (INTEL_INFO(dev)->gen <= 6)
cd0de039
KP		 1876 enable_fbc = 0;
1877 }
1878 if (!enable_fbc) {
1879 DRM_DEBUG_KMS("fbc disabled per module param\n");
c1a9f047
JB		 1880 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
1881 goto out_disable;
1882 }
05394f39 1883 if (intel_fb->obj->base.size > dev_priv->cfb_size) {
28c97730 1884 DRM_DEBUG_KMS("framebuffer too large, disabling "
5eddb70b 1885 "compression\n");
b5e50c3f 1886 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
80824003
JB		 1887 goto out_disable;
1888 }
bed4a673
CW		 1889 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1890 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
28c97730 1891 DRM_DEBUG_KMS("mode incompatible with compression, "
5eddb70b 1892 "disabling\n");
b5e50c3f 1893 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
80824003
JB		 1894 goto out_disable;
1895 }
bed4a673
CW		 1896 if ((crtc->mode.hdisplay > 2048) ||
1897 (crtc->mode.vdisplay > 1536)) {
28c97730 1898 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
b5e50c3f 1899 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
80824003
JB		 1900 goto out_disable;
1901 }
bed4a673 1902 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
28c97730 1903 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
b5e50c3f 1904 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
80824003
JB		 1905 goto out_disable;
1906 }
de568510
CW		 1907
1908 /* The use of a CPU fence is mandatory in order to detect writes
1909 * by the CPU to the scanout and trigger updates to the FBC.
1910 */
1911 if (obj->tiling_mode != I915_TILING_X ||
1912 obj->fence_reg == I915_FENCE_REG_NONE) {
1913 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
b5e50c3f 1914 dev_priv->no_fbc_reason = FBC_NOT_TILED;
80824003
JB		 1915 goto out_disable;
1916 }
1917
c924b934
JW		 1918 /* If the kernel debugger is active, always disable compression */
1919 if (in_dbg_master())
1920 goto out_disable;
1921
016b9b61
CW		 1922 /* If the scanout has not changed, don't modify the FBC settings.
1923 * Note that we make the fundamental assumption that the fb->obj
1924 * cannot be unpinned (and have its GTT offset and fence revoked)
1925 * without first being decoupled from the scanout and FBC disabled.
1926 */
1927 if (dev_priv->cfb_plane == intel_crtc->plane &&
1928 dev_priv->cfb_fb == fb->base.id &&
1929 dev_priv->cfb_y == crtc->y)
1930 return;
1931
1932 if (intel_fbc_enabled(dev)) {
1933 /* We update FBC along two paths, after changing fb/crtc
1934 * configuration (modeswitching) and after page-flipping
1935 * finishes. For the latter, we know that not only did
1936 * we disable the FBC at the start of the page-flip
1937 * sequence, but also more than one vblank has passed.
1938 *
1939 * For the former case of modeswitching, it is possible
1940 * to switch between two FBC valid configurations
1941 * instantaneously so we do need to disable the FBC
1942 * before we can modify its control registers. We also
1943 * have to wait for the next vblank for that to take
1944 * effect. However, since we delay enabling FBC we can
1945 * assume that a vblank has passed since disabling and
1946 * that we can safely alter the registers in the deferred
1947 * callback.
1948 *
1949 * In the scenario that we go from a valid to invalid
1950 * and then back to valid FBC configuration we have
1951 * no strict enforcement that a vblank occurred since
1952 * disabling the FBC. However, along all current pipe
1953 * disabling paths we do need to wait for a vblank at
1954 * some point. And we wait before enabling FBC anyway.
1955 */
1956 DRM_DEBUG_KMS("disabling active FBC for update\n");
1957 intel_disable_fbc(dev);
1958 }
1959
bed4a673 1960 intel_enable_fbc(crtc, 500);
80824003
JB		 1961 return;
1962
1963out_disable:
80824003 1964 /* Multiple disables should be harmless */
a939406f
CW		 1965 if (intel_fbc_enabled(dev)) {
1966 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
ee5382ae 1967 intel_disable_fbc(dev);
a939406f 1968 }
80824003
JB		 1969}
1970
127bd2ac 1971int
48b956c5 1972intel_pin_and_fence_fb_obj(struct drm_device *dev,
05394f39 1973 struct drm_i915_gem_object *obj,
919926ae 1974 struct intel_ring_buffer *pipelined)
6b95a207 1975{
ce453d81 1976 struct drm_i915_private *dev_priv = dev->dev_private;
6b95a207
KH		 1977 u32 alignment;
1978 int ret;
1979
05394f39 1980 switch (obj->tiling_mode) {
6b95a207 1981 case I915_TILING_NONE:
534843da
CW		 1982 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1983 alignment = 128 * 1024;
a6c45cf0 1984 else if (INTEL_INFO(dev)->gen >= 4)
534843da
CW		 1985 alignment = 4 * 1024;
1986 else
1987 alignment = 64 * 1024;
6b95a207
KH		 1988 break;
1989 case I915_TILING_X:
1990 /* pin() will align the object as required by fence */
1991 alignment = 0;
1992 break;
1993 case I915_TILING_Y:
1994 /* FIXME: Is this true? */
1995 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1996 return -EINVAL;
1997 default:
1998 BUG();
1999 }
2000
ce453d81 2001 dev_priv->mm.interruptible = false;
2da3b9b9 2002 ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
48b956c5 2003 if (ret)
ce453d81 2004 goto err_interruptible;
6b95a207
KH		 2005
2006 /* Install a fence for tiled scan-out. Pre-i965 always needs a
2007 * fence, whereas 965+ only requires a fence if using
2008 * framebuffer compression. For simplicity, we always install
2009 * a fence as the cost is not that onerous.
2010 */
05394f39 2011 if (obj->tiling_mode != I915_TILING_NONE) {
ce453d81 2012 ret = i915_gem_object_get_fence(obj, pipelined);
48b956c5
CW		 2013 if (ret)
2014 goto err_unpin;
6b95a207
KH		 2015 }
2016
ce453d81 2017 dev_priv->mm.interruptible = true;
6b95a207 2018 return 0;
48b956c5
CW		 2019
2020err_unpin:
2021 i915_gem_object_unpin(obj);
ce453d81
CW		 2022err_interruptible:
2023 dev_priv->mm.interruptible = true;
48b956c5 2024 return ret;
6b95a207
KH		 2025}
2026
17638cd6
JB		 2027static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2028 int x, int y)
81255565
JB		 2029{
2030 struct drm_device *dev = crtc->dev;
2031 struct drm_i915_private *dev_priv = dev->dev_private;
2032 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2033 struct intel_framebuffer *intel_fb;
05394f39 2034 struct drm_i915_gem_object *obj;
81255565
JB		 2035 int plane = intel_crtc->plane;
2036 unsigned long Start, Offset;
81255565 2037 u32 dspcntr;
5eddb70b 2038 u32 reg;
81255565
JB		 2039
2040 switch (plane) {
2041 case 0:
2042 case 1:
2043 break;
2044 default:
2045 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2046 return -EINVAL;
2047 }
2048
2049 intel_fb = to_intel_framebuffer(fb);
2050 obj = intel_fb->obj;
81255565 2051
5eddb70b
CW		 2052 reg = DSPCNTR(plane);
2053 dspcntr = I915_READ(reg);
81255565
JB		 2054 /* Mask out pixel format bits in case we change it */
2055 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2056 switch (fb->bits_per_pixel) {
2057 case 8:
2058 dspcntr |= DISPPLANE_8BPP;
2059 break;
2060 case 16:
2061 if (fb->depth == 15)
2062 dspcntr |= DISPPLANE_15_16BPP;
2063 else
2064 dspcntr |= DISPPLANE_16BPP;
2065 break;
2066 case 24:
2067 case 32:
2068 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2069 break;
2070 default:
17638cd6 2071 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
81255565
JB		 2072 return -EINVAL;
2073 }
a6c45cf0 2074 if (INTEL_INFO(dev)->gen >= 4) {
05394f39 2075 if (obj->tiling_mode != I915_TILING_NONE)
81255565
JB		 2076 dspcntr |= DISPPLANE_TILED;
2077 else
2078 dspcntr &= ~DISPPLANE_TILED;
2079 }
2080
5eddb70b 2081 I915_WRITE(reg, dspcntr);
81255565 2082
05394f39 2083 Start = obj->gtt_offset;
01f2c773 2084 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
81255565 2085
4e6cfefc 2086 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 2087 Start, Offset, x, y, fb->pitches[0]);
2088 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
a6c45cf0 2089 if (INTEL_INFO(dev)->gen >= 4) {
5eddb70b
CW		 2090 I915_WRITE(DSPSURF(plane), Start);
2091 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2092 I915_WRITE(DSPADDR(plane), Offset);
2093 } else
2094 I915_WRITE(DSPADDR(plane), Start + Offset);
2095 POSTING_READ(reg);
81255565 2096
17638cd6
JB		 2097 return 0;
2098}
2099
2100static int ironlake_update_plane(struct drm_crtc *crtc,
2101 struct drm_framebuffer *fb, int x, int y)
2102{
2103 struct drm_device *dev = crtc->dev;
2104 struct drm_i915_private *dev_priv = dev->dev_private;
2105 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2106 struct intel_framebuffer *intel_fb;
2107 struct drm_i915_gem_object *obj;
2108 int plane = intel_crtc->plane;
2109 unsigned long Start, Offset;
2110 u32 dspcntr;
2111 u32 reg;
2112
2113 switch (plane) {
2114 case 0:
2115 case 1:
27f8227b 2116 case 2:
17638cd6
JB		 2117 break;
2118 default:
2119 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2120 return -EINVAL;
2121 }
2122
2123 intel_fb = to_intel_framebuffer(fb);
2124 obj = intel_fb->obj;
2125
2126 reg = DSPCNTR(plane);
2127 dspcntr = I915_READ(reg);
2128 /* Mask out pixel format bits in case we change it */
2129 dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2130 switch (fb->bits_per_pixel) {
2131 case 8:
2132 dspcntr |= DISPPLANE_8BPP;
2133 break;
2134 case 16:
2135 if (fb->depth != 16)
2136 return -EINVAL;
2137
2138 dspcntr |= DISPPLANE_16BPP;
2139 break;
2140 case 24:
2141 case 32:
2142 if (fb->depth == 24)
2143 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
2144 else if (fb->depth == 30)
2145 dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
2146 else
2147 return -EINVAL;
2148 break;
2149 default:
2150 DRM_ERROR("Unknown color depth %d\n", fb->bits_per_pixel);
2151 return -EINVAL;
2152 }
2153
2154 if (obj->tiling_mode != I915_TILING_NONE)
2155 dspcntr |= DISPPLANE_TILED;
2156 else
2157 dspcntr &= ~DISPPLANE_TILED;
2158
2159 /* must disable */
2160 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2161
2162 I915_WRITE(reg, dspcntr);
2163
2164 Start = obj->gtt_offset;
01f2c773 2165 Offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
17638cd6
JB		 2166
2167 DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
01f2c773
VS		 2168 Start, Offset, x, y, fb->pitches[0]);
2169 I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
17638cd6
JB		 2170 I915_WRITE(DSPSURF(plane), Start);
2171 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2172 I915_WRITE(DSPADDR(plane), Offset);
2173 POSTING_READ(reg);
2174
2175 return 0;
2176}
2177
2178/* Assume fb object is pinned & idle & fenced and just update base pointers */
2179static int
2180intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2181 int x, int y, enum mode_set_atomic state)
2182{
2183 struct drm_device *dev = crtc->dev;
2184 struct drm_i915_private *dev_priv = dev->dev_private;
2185 int ret;
2186
2187 ret = dev_priv->display.update_plane(crtc, fb, x, y);
2188 if (ret)
2189 return ret;
2190
bed4a673 2191 intel_update_fbc(dev);
3dec0095 2192 intel_increase_pllclock(crtc);
81255565
JB		 2193
2194 return 0;
2195}
2196
5c3b82e2 2197static int
3c4fdcfb
KH		 2198intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2199 struct drm_framebuffer *old_fb)
79e53945
JB		 2200{
2201 struct drm_device *dev = crtc->dev;
79e53945
JB		 2202 struct drm_i915_master_private *master_priv;
2203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5c3b82e2 2204 int ret;
79e53945
JB		 2205
2206 /* no fb bound */
2207 if (!crtc->fb) {
a5071c2f 2208 DRM_ERROR("No FB bound\n");
5c3b82e2
CW		 2209 return 0;
2210 }
2211
265db958 2212 switch (intel_crtc->plane) {
5c3b82e2
CW		 2213 case 0:
2214 case 1:
2215 break;
27f8227b
JB		 2216 case 2:
2217 if (IS_IVYBRIDGE(dev))
2218 break;
2219 /* fall through otherwise */
5c3b82e2 2220 default:
a5071c2f 2221 DRM_ERROR("no plane for crtc\n");
5c3b82e2 2222 return -EINVAL;
79e53945
JB		 2223 }
2224
5c3b82e2 2225 mutex_lock(&dev->struct_mutex);
265db958
CW		 2226 ret = intel_pin_and_fence_fb_obj(dev,
2227 to_intel_framebuffer(crtc->fb)->obj,
919926ae 2228 NULL);
5c3b82e2
CW		 2229 if (ret != 0) {
2230 mutex_unlock(&dev->struct_mutex);
a5071c2f 2231 DRM_ERROR("pin & fence failed\n");
5c3b82e2
CW		 2232 return ret;
2233 }
79e53945 2234
265db958 2235 if (old_fb) {
e6c3a2a6 2236 struct drm_i915_private *dev_priv = dev->dev_private;
05394f39 2237 struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
265db958 2238
e6c3a2a6 2239 wait_event(dev_priv->pending_flip_queue,
01eec727 2240 atomic_read(&dev_priv->mm.wedged) ||
05394f39 2241 atomic_read(&obj->pending_flip) == 0);
85345517
CW		 2242
2243 /* Big Hammer, we also need to ensure that any pending
2244 * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2245 * current scanout is retired before unpinning the old
2246 * framebuffer.
01eec727
CW		 2247 *
2248 * This should only fail upon a hung GPU, in which case we
2249 * can safely continue.
85345517 2250 */
a8198eea 2251 ret = i915_gem_object_finish_gpu(obj);
01eec727 2252 (void) ret;
265db958
CW		 2253 }
2254
21c74a8e
JW		 2255 ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y,
2256 LEAVE_ATOMIC_MODE_SET);
4e6cfefc 2257 if (ret) {
265db958 2258 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
5c3b82e2 2259 mutex_unlock(&dev->struct_mutex);
a5071c2f 2260 DRM_ERROR("failed to update base address\n");
4e6cfefc 2261 return ret;
79e53945 2262 }
3c4fdcfb 2263
b7f1de28
CW		 2264 if (old_fb) {
2265 intel_wait_for_vblank(dev, intel_crtc->pipe);
265db958 2266 i915_gem_object_unpin(to_intel_framebuffer(old_fb)->obj);
b7f1de28 2267 }
652c393a 2268
5c3b82e2 2269 mutex_unlock(&dev->struct_mutex);
79e53945
JB		 2270
2271 if (!dev->primary->master)
5c3b82e2 2272 return 0;
79e53945
JB		 2273
2274 master_priv = dev->primary->master->driver_priv;
2275 if (!master_priv->sarea_priv)
5c3b82e2 2276 return 0;
79e53945 2277
265db958 2278 if (intel_crtc->pipe) {
79e53945
JB		 2279 master_priv->sarea_priv->pipeB_x = x;
2280 master_priv->sarea_priv->pipeB_y = y;
5c3b82e2
CW		 2281 } else {
2282 master_priv->sarea_priv->pipeA_x = x;
2283 master_priv->sarea_priv->pipeA_y = y;
79e53945 2284 }
5c3b82e2
CW		 2285
2286 return 0;
79e53945
JB		 2287}
2288
5eddb70b 2289static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
32f9d658
ZW		 2290{
2291 struct drm_device *dev = crtc->dev;
2292 struct drm_i915_private *dev_priv = dev->dev_private;
2293 u32 dpa_ctl;
2294
28c97730 2295 DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
32f9d658
ZW		 2296 dpa_ctl = I915_READ(DP_A);
2297 dpa_ctl &= ~DP_PLL_FREQ_MASK;
2298
2299 if (clock < 200000) {
2300 u32 temp;
2301 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2302 /* workaround for 160Mhz:
2303 1) program 0x4600c bits 15:0 = 0x8124
2304 2) program 0x46010 bit 0 = 1
2305 3) program 0x46034 bit 24 = 1
2306 4) program 0x64000 bit 14 = 1
2307 */
2308 temp = I915_READ(0x4600c);
2309 temp &= 0xffff0000;
2310 I915_WRITE(0x4600c, temp | 0x8124);
2311
2312 temp = I915_READ(0x46010);
2313 I915_WRITE(0x46010, temp | 1);
2314
2315 temp = I915_READ(0x46034);
2316 I915_WRITE(0x46034, temp | (1 << 24));
2317 } else {
2318 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2319 }
2320 I915_WRITE(DP_A, dpa_ctl);
2321
5eddb70b 2322 POSTING_READ(DP_A);
32f9d658
ZW		 2323 udelay(500);
2324}
2325
5e84e1a4
ZW		 2326static void intel_fdi_normal_train(struct drm_crtc *crtc)
2327{
2328 struct drm_device *dev = crtc->dev;
2329 struct drm_i915_private *dev_priv = dev->dev_private;
2330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2331 int pipe = intel_crtc->pipe;
2332 u32 reg, temp;
2333
2334 /* enable normal train */
2335 reg = FDI_TX_CTL(pipe);
2336 temp = I915_READ(reg);
61e499bf 2337 if (IS_IVYBRIDGE(dev)) {
357555c0
JB		 2338 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2339 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
61e499bf
KP		 2340 } else {
2341 temp &= ~FDI_LINK_TRAIN_NONE;
2342 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
357555c0 2343 }
5e84e1a4
ZW		 2344 I915_WRITE(reg, temp);
2345
2346 reg = FDI_RX_CTL(pipe);
2347 temp = I915_READ(reg);
2348 if (HAS_PCH_CPT(dev)) {
2349 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2350 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2351 } else {
2352 temp &= ~FDI_LINK_TRAIN_NONE;
2353 temp |= FDI_LINK_TRAIN_NONE;
2354 }
2355 I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2356
2357 /* wait one idle pattern time */
2358 POSTING_READ(reg);
2359 udelay(1000);
357555c0
JB		 2360
2361 /* IVB wants error correction enabled */
2362 if (IS_IVYBRIDGE(dev))
2363 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2364 FDI_FE_ERRC_ENABLE);
5e84e1a4
ZW		 2365}
2366
291427f5
JB		 2367static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2368{
2369 struct drm_i915_private *dev_priv = dev->dev_private;
2370 u32 flags = I915_READ(SOUTH_CHICKEN1);
2371
2372 flags |= FDI_PHASE_SYNC_OVR(pipe);
2373 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2374 flags |= FDI_PHASE_SYNC_EN(pipe);
2375 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2376 POSTING_READ(SOUTH_CHICKEN1);
2377}
2378
8db9d77b
ZW		 2379/* The FDI link training functions for ILK/Ibexpeak. */
2380static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2381{
2382 struct drm_device *dev = crtc->dev;
2383 struct drm_i915_private *dev_priv = dev->dev_private;
2384 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2385 int pipe = intel_crtc->pipe;
0fc932b8 2386 int plane = intel_crtc->plane;
5eddb70b 2387 u32 reg, temp, tries;
8db9d77b 2388
0fc932b8
JB		 2389 /* FDI needs bits from pipe & plane first */
2390 assert_pipe_enabled(dev_priv, pipe);
2391 assert_plane_enabled(dev_priv, plane);
2392
e1a44743
AJ		 2393 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2394 for train result */
5eddb70b
CW		 2395 reg = FDI_RX_IMR(pipe);
2396 temp = I915_READ(reg);
e1a44743
AJ		 2397 temp &= ~FDI_RX_SYMBOL_LOCK;
2398 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2399 I915_WRITE(reg, temp);
2400 I915_READ(reg);
e1a44743
AJ		 2401 udelay(150);
2402
8db9d77b 2403 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2404 reg = FDI_TX_CTL(pipe);
2405 temp = I915_READ(reg);
77ffb597
AJ		 2406 temp &= ~(7 << 19);
2407 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2408 temp &= ~FDI_LINK_TRAIN_NONE;
2409 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b 2410 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2411
5eddb70b
CW		 2412 reg = FDI_RX_CTL(pipe);
2413 temp = I915_READ(reg);
8db9d77b
ZW		 2414 temp &= ~FDI_LINK_TRAIN_NONE;
2415 temp |= FDI_LINK_TRAIN_PATTERN_1;
5eddb70b
CW		 2416 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2417
2418 POSTING_READ(reg);
8db9d77b
ZW		 2419 udelay(150);
2420
5b2adf89 2421 /* Ironlake workaround, enable clock pointer after FDI enable*/
6f06ce18
JB		 2422 if (HAS_PCH_IBX(dev)) {
2423 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2424 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2425 FDI_RX_PHASE_SYNC_POINTER_EN);
2426 }
5b2adf89 2427
5eddb70b 2428 reg = FDI_RX_IIR(pipe);
e1a44743 2429 for (tries = 0; tries < 5; tries++) {
5eddb70b 2430 temp = I915_READ(reg);
8db9d77b
ZW		 2431 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2432
2433 if ((temp & FDI_RX_BIT_LOCK)) {
2434 DRM_DEBUG_KMS("FDI train 1 done.\n");
5eddb70b 2435 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2436 break;
2437 }
8db9d77b 2438 }
e1a44743 2439 if (tries == 5)
5eddb70b 2440 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2441
2442 /* Train 2 */
5eddb70b
CW		 2443 reg = FDI_TX_CTL(pipe);
2444 temp = I915_READ(reg);
8db9d77b
ZW		 2445 temp &= ~FDI_LINK_TRAIN_NONE;
2446 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2447 I915_WRITE(reg, temp);
8db9d77b 2448
5eddb70b
CW		 2449 reg = FDI_RX_CTL(pipe);
2450 temp = I915_READ(reg);
8db9d77b
ZW		 2451 temp &= ~FDI_LINK_TRAIN_NONE;
2452 temp |= FDI_LINK_TRAIN_PATTERN_2;
5eddb70b 2453 I915_WRITE(reg, temp);
8db9d77b 2454
5eddb70b
CW		 2455 POSTING_READ(reg);
2456 udelay(150);
8db9d77b 2457
5eddb70b 2458 reg = FDI_RX_IIR(pipe);
e1a44743 2459 for (tries = 0; tries < 5; tries++) {
5eddb70b 2460 temp = I915_READ(reg);
8db9d77b
ZW		 2461 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2462
2463 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2464 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2465 DRM_DEBUG_KMS("FDI train 2 done.\n");
2466 break;
2467 }
8db9d77b 2468 }
e1a44743 2469 if (tries == 5)
5eddb70b 2470 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2471
2472 DRM_DEBUG_KMS("FDI train done\n");
5c5313c8 2473
8db9d77b
ZW		 2474}
2475
0206e353 2476static const int snb_b_fdi_train_param[] = {
8db9d77b
ZW		 2477 FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2478 FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2479 FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2480 FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2481};
2482
2483/* The FDI link training functions for SNB/Cougarpoint. */
2484static void gen6_fdi_link_train(struct drm_crtc *crtc)
2485{
2486 struct drm_device *dev = crtc->dev;
2487 struct drm_i915_private *dev_priv = dev->dev_private;
2488 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2489 int pipe = intel_crtc->pipe;
5eddb70b 2490 u32 reg, temp, i;
8db9d77b 2491
e1a44743
AJ		 2492 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2493 for train result */
5eddb70b
CW		 2494 reg = FDI_RX_IMR(pipe);
2495 temp = I915_READ(reg);
e1a44743
AJ		 2496 temp &= ~FDI_RX_SYMBOL_LOCK;
2497 temp &= ~FDI_RX_BIT_LOCK;
5eddb70b
CW		 2498 I915_WRITE(reg, temp);
2499
2500 POSTING_READ(reg);
e1a44743
AJ		 2501 udelay(150);
2502
8db9d77b 2503 /* enable CPU FDI TX and PCH FDI RX */
5eddb70b
CW		 2504 reg = FDI_TX_CTL(pipe);
2505 temp = I915_READ(reg);
77ffb597
AJ		 2506 temp &= ~(7 << 19);
2507 temp |= (intel_crtc->fdi_lanes - 1) << 19;
8db9d77b
ZW		 2508 temp &= ~FDI_LINK_TRAIN_NONE;
2509 temp |= FDI_LINK_TRAIN_PATTERN_1;
2510 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2511 /* SNB-B */
2512 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
5eddb70b 2513 I915_WRITE(reg, temp | FDI_TX_ENABLE);
8db9d77b 2514
5eddb70b
CW		 2515 reg = FDI_RX_CTL(pipe);
2516 temp = I915_READ(reg);
8db9d77b
ZW		 2517 if (HAS_PCH_CPT(dev)) {
2518 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2519 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2520 } else {
2521 temp &= ~FDI_LINK_TRAIN_NONE;
2522 temp |= FDI_LINK_TRAIN_PATTERN_1;
2523 }
5eddb70b
CW		 2524 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2525
2526 POSTING_READ(reg);
8db9d77b
ZW		 2527 udelay(150);
2528
291427f5
JB		 2529 if (HAS_PCH_CPT(dev))
2530 cpt_phase_pointer_enable(dev, pipe);
2531
0206e353 2532 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2533 reg = FDI_TX_CTL(pipe);
2534 temp = I915_READ(reg);
8db9d77b
ZW		 2535 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2536 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2537 I915_WRITE(reg, temp);
2538
2539 POSTING_READ(reg);
8db9d77b
ZW		 2540 udelay(500);
2541
5eddb70b
CW		 2542 reg = FDI_RX_IIR(pipe);
2543 temp = I915_READ(reg);
8db9d77b
ZW		 2544 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2545
2546 if (temp & FDI_RX_BIT_LOCK) {
5eddb70b 2547 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
8db9d77b
ZW		 2548 DRM_DEBUG_KMS("FDI train 1 done.\n");
2549 break;
2550 }
2551 }
2552 if (i == 4)
5eddb70b 2553 DRM_ERROR("FDI train 1 fail!\n");
8db9d77b
ZW		 2554
2555 /* Train 2 */
5eddb70b
CW		 2556 reg = FDI_TX_CTL(pipe);
2557 temp = I915_READ(reg);
8db9d77b
ZW		 2558 temp &= ~FDI_LINK_TRAIN_NONE;
2559 temp |= FDI_LINK_TRAIN_PATTERN_2;
2560 if (IS_GEN6(dev)) {
2561 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2562 /* SNB-B */
2563 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2564 }
5eddb70b 2565 I915_WRITE(reg, temp);
8db9d77b 2566
5eddb70b
CW		 2567 reg = FDI_RX_CTL(pipe);
2568 temp = I915_READ(reg);
8db9d77b
ZW		 2569 if (HAS_PCH_CPT(dev)) {
2570 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2571 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2572 } else {
2573 temp &= ~FDI_LINK_TRAIN_NONE;
2574 temp |= FDI_LINK_TRAIN_PATTERN_2;
2575 }
5eddb70b
CW		 2576 I915_WRITE(reg, temp);
2577
2578 POSTING_READ(reg);
8db9d77b
ZW		 2579 udelay(150);
2580
0206e353 2581 for (i = 0; i < 4; i++) {
5eddb70b
CW		 2582 reg = FDI_TX_CTL(pipe);
2583 temp = I915_READ(reg);
8db9d77b
ZW		 2584 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2585 temp |= snb_b_fdi_train_param[i];
5eddb70b
CW		 2586 I915_WRITE(reg, temp);
2587
2588 POSTING_READ(reg);
8db9d77b
ZW		 2589 udelay(500);
2590
5eddb70b
CW		 2591 reg = FDI_RX_IIR(pipe);
2592 temp = I915_READ(reg);
8db9d77b
ZW		 2593 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2594
2595 if (temp & FDI_RX_SYMBOL_LOCK) {
5eddb70b 2596 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
8db9d77b
ZW		 2597 DRM_DEBUG_KMS("FDI train 2 done.\n");
2598 break;
2599 }
2600 }
2601 if (i == 4)
5eddb70b 2602 DRM_ERROR("FDI train 2 fail!\n");
8db9d77b
ZW		 2603
2604 DRM_DEBUG_KMS("FDI train done.\n");
2605}
2606
357555c0
JB		 2607/* Manual link training for Ivy Bridge A0 parts */
2608static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2609{
2610 struct drm_device *dev = crtc->dev;
2611 struct drm_i915_private *dev_priv = dev->dev_private;
2612 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2613 int pipe = intel_crtc->pipe;
2614 u32 reg, temp, i;
2615
2616 /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2617 for train result */
2618 reg = FDI_RX_IMR(pipe);
2619 temp = I915_READ(reg);
2620 temp &= ~FDI_RX_SYMBOL_LOCK;
2621 temp &= ~FDI_RX_BIT_LOCK;
2622 I915_WRITE(reg, temp);
2623
2624 POSTING_READ(reg);
2625 udelay(150);
2626
2627 /* enable CPU FDI TX and PCH FDI RX */
2628 reg = FDI_TX_CTL(pipe);
2629 temp = I915_READ(reg);
2630 temp &= ~(7 << 19);
2631 temp |= (intel_crtc->fdi_lanes - 1) << 19;
2632 temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2633 temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2634 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2635 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
c4f9c4c2 2636 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2637 I915_WRITE(reg, temp | FDI_TX_ENABLE);
2638
2639 reg = FDI_RX_CTL(pipe);
2640 temp = I915_READ(reg);
2641 temp &= ~FDI_LINK_TRAIN_AUTO;
2642 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2643 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
c4f9c4c2 2644 temp |= FDI_COMPOSITE_SYNC;
357555c0
JB		 2645 I915_WRITE(reg, temp | FDI_RX_ENABLE);
2646
2647 POSTING_READ(reg);
2648 udelay(150);
2649
291427f5
JB		 2650 if (HAS_PCH_CPT(dev))
2651 cpt_phase_pointer_enable(dev, pipe);
2652
0206e353 2653 for (i = 0; i < 4; i++) {
357555c0
JB		 2654 reg = FDI_TX_CTL(pipe);
2655 temp = I915_READ(reg);
2656 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2657 temp |= snb_b_fdi_train_param[i];
2658 I915_WRITE(reg, temp);
2659
2660 POSTING_READ(reg);
2661 udelay(500);
2662
2663 reg = FDI_RX_IIR(pipe);
2664 temp = I915_READ(reg);
2665 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2666
2667 if (temp & FDI_RX_BIT_LOCK ||
2668 (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2669 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2670 DRM_DEBUG_KMS("FDI train 1 done.\n");
2671 break;
2672 }
2673 }
2674 if (i == 4)
2675 DRM_ERROR("FDI train 1 fail!\n");
2676
2677 /* Train 2 */
2678 reg = FDI_TX_CTL(pipe);
2679 temp = I915_READ(reg);
2680 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2681 temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2682 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2683 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2684 I915_WRITE(reg, temp);
2685
2686 reg = FDI_RX_CTL(pipe);
2687 temp = I915_READ(reg);
2688 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2689 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2690 I915_WRITE(reg, temp);
2691
2692 POSTING_READ(reg);
2693 udelay(150);
2694
0206e353 2695 for (i = 0; i < 4; i++) {
357555c0
JB		 2696 reg = FDI_TX_CTL(pipe);
2697 temp = I915_READ(reg);
2698 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2699 temp |= snb_b_fdi_train_param[i];
2700 I915_WRITE(reg, temp);
2701
2702 POSTING_READ(reg);
2703 udelay(500);
2704
2705 reg = FDI_RX_IIR(pipe);
2706 temp = I915_READ(reg);
2707 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2708
2709 if (temp & FDI_RX_SYMBOL_LOCK) {
2710 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2711 DRM_DEBUG_KMS("FDI train 2 done.\n");
2712 break;
2713 }
2714 }
2715 if (i == 4)
2716 DRM_ERROR("FDI train 2 fail!\n");
2717
2718 DRM_DEBUG_KMS("FDI train done.\n");
2719}
2720
2721static void ironlake_fdi_pll_enable(struct drm_crtc *crtc)
2c07245f
ZW		 2722{
2723 struct drm_device *dev = crtc->dev;
2724 struct drm_i915_private *dev_priv = dev->dev_private;
2725 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2726 int pipe = intel_crtc->pipe;
5eddb70b 2727 u32 reg, temp;
79e53945 2728
c64e311e 2729 /* Write the TU size bits so error detection works */
5eddb70b
CW		 2730 I915_WRITE(FDI_RX_TUSIZE1(pipe),
2731 I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
c64e311e 2732
c98e9dcf 2733 /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
5eddb70b
CW		 2734 reg = FDI_RX_CTL(pipe);
2735 temp = I915_READ(reg);
2736 temp &= ~((0x7 << 19) | (0x7 << 16));
c98e9dcf 2737 temp |= (intel_crtc->fdi_lanes - 1) << 19;
5eddb70b
CW		 2738 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2739 I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2740
2741 POSTING_READ(reg);
c98e9dcf
JB		 2742 udelay(200);
2743
2744 /* Switch from Rawclk to PCDclk */
5eddb70b
CW		 2745 temp = I915_READ(reg);
2746 I915_WRITE(reg, temp | FDI_PCDCLK);
2747
2748 POSTING_READ(reg);
c98e9dcf
JB		 2749 udelay(200);
2750
2751 /* Enable CPU FDI TX PLL, always on for Ironlake */
5eddb70b
CW		 2752 reg = FDI_TX_CTL(pipe);
2753 temp = I915_READ(reg);
c98e9dcf 2754 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
5eddb70b
CW		 2755 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2756
2757 POSTING_READ(reg);
c98e9dcf 2758 udelay(100);
6be4a607 2759 }
0e23b99d
JB		 2760}
2761
291427f5
JB		 2762static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2763{
2764 struct drm_i915_private *dev_priv = dev->dev_private;
2765 u32 flags = I915_READ(SOUTH_CHICKEN1);
2766
2767 flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2768 I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2769 flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2770 I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2771 POSTING_READ(SOUTH_CHICKEN1);
2772}
0fc932b8
JB		 2773static void ironlake_fdi_disable(struct drm_crtc *crtc)
2774{
2775 struct drm_device *dev = crtc->dev;
2776 struct drm_i915_private *dev_priv = dev->dev_private;
2777 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2778 int pipe = intel_crtc->pipe;
2779 u32 reg, temp;
2780
2781 /* disable CPU FDI tx and PCH FDI rx */
2782 reg = FDI_TX_CTL(pipe);
2783 temp = I915_READ(reg);
2784 I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2785 POSTING_READ(reg);
2786
2787 reg = FDI_RX_CTL(pipe);
2788 temp = I915_READ(reg);
2789 temp &= ~(0x7 << 16);
2790 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2791 I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2792
2793 POSTING_READ(reg);
2794 udelay(100);
2795
2796 /* Ironlake workaround, disable clock pointer after downing FDI */
6f06ce18
JB		 2797 if (HAS_PCH_IBX(dev)) {
2798 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
0fc932b8
JB		 2799 I915_WRITE(FDI_RX_CHICKEN(pipe),
2800 I915_READ(FDI_RX_CHICKEN(pipe) &
6f06ce18 2801 ~FDI_RX_PHASE_SYNC_POINTER_EN));
291427f5
JB		 2802 } else if (HAS_PCH_CPT(dev)) {
2803 cpt_phase_pointer_disable(dev, pipe);
6f06ce18 2804 }
0fc932b8
JB		 2805
2806 /* still set train pattern 1 */
2807 reg = FDI_TX_CTL(pipe);
2808 temp = I915_READ(reg);
2809 temp &= ~FDI_LINK_TRAIN_NONE;
2810 temp |= FDI_LINK_TRAIN_PATTERN_1;
2811 I915_WRITE(reg, temp);
2812
2813 reg = FDI_RX_CTL(pipe);
2814 temp = I915_READ(reg);
2815 if (HAS_PCH_CPT(dev)) {
2816 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2817 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2818 } else {
2819 temp &= ~FDI_LINK_TRAIN_NONE;
2820 temp |= FDI_LINK_TRAIN_PATTERN_1;
2821 }
2822 /* BPC in FDI rx is consistent with that in PIPECONF */
2823 temp &= ~(0x07 << 16);
2824 temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2825 I915_WRITE(reg, temp);
2826
2827 POSTING_READ(reg);
2828 udelay(100);
2829}
2830
6b383a7f
CW		 2831/*
2832 * When we disable a pipe, we need to clear any pending scanline wait events
2833 * to avoid hanging the ring, which we assume we are waiting on.
2834 */
2835static void intel_clear_scanline_wait(struct drm_device *dev)
2836{
2837 struct drm_i915_private *dev_priv = dev->dev_private;
8168bd48 2838 struct intel_ring_buffer *ring;
6b383a7f
CW		 2839 u32 tmp;
2840
2841 if (IS_GEN2(dev))
2842 /* Can't break the hang on i8xx */
2843 return;
2844
1ec14ad3 2845 ring = LP_RING(dev_priv);
8168bd48
CW		 2846 tmp = I915_READ_CTL(ring);
2847 if (tmp & RING_WAIT)
2848 I915_WRITE_CTL(ring, tmp);
6b383a7f
CW		 2849}
2850
e6c3a2a6
CW		 2851static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2852{
05394f39 2853 struct drm_i915_gem_object *obj;
e6c3a2a6
CW		 2854 struct drm_i915_private *dev_priv;
2855
2856 if (crtc->fb == NULL)
2857 return;
2858
05394f39 2859 obj = to_intel_framebuffer(crtc->fb)->obj;
e6c3a2a6
CW		 2860 dev_priv = crtc->dev->dev_private;
2861 wait_event(dev_priv->pending_flip_queue,
05394f39 2862 atomic_read(&obj->pending_flip) == 0);
e6c3a2a6
CW		 2863}
2864
040484af
JB		 2865static bool intel_crtc_driving_pch(struct drm_crtc *crtc)
2866{
2867 struct drm_device *dev = crtc->dev;
2868 struct drm_mode_config *mode_config = &dev->mode_config;
2869 struct intel_encoder *encoder;
2870
2871 /*
2872 * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2873 * must be driven by its own crtc; no sharing is possible.
2874 */
2875 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
2876 if (encoder->base.crtc != crtc)
2877 continue;
2878
2879 switch (encoder->type) {
2880 case INTEL_OUTPUT_EDP:
2881 if (!intel_encoder_is_pch_edp(&encoder->base))
2882 return false;
2883 continue;
2884 }
2885 }
2886
2887 return true;
2888}
2889
f67a559d
JB		 2890/*
2891 * Enable PCH resources required for PCH ports:
2892 * - PCH PLLs
2893 * - FDI training & RX/TX
2894 * - update transcoder timings
2895 * - DP transcoding bits
2896 * - transcoder
2897 */
2898static void ironlake_pch_enable(struct drm_crtc *crtc)
0e23b99d
JB		 2899{
2900 struct drm_device *dev = crtc->dev;
2901 struct drm_i915_private *dev_priv = dev->dev_private;
2902 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2903 int pipe = intel_crtc->pipe;
4b645f14 2904 u32 reg, temp, transc_sel;
2c07245f 2905
c98e9dcf 2906 /* For PCH output, training FDI link */
674cf967 2907 dev_priv->display.fdi_link_train(crtc);
2c07245f 2908
92f2584a 2909 intel_enable_pch_pll(dev_priv, pipe);
8db9d77b 2910
c98e9dcf 2911 if (HAS_PCH_CPT(dev)) {
4b645f14
JB		 2912 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL :
2913 TRANSC_DPLLB_SEL;
2914
c98e9dcf
JB		 2915 /* Be sure PCH DPLL SEL is set */
2916 temp = I915_READ(PCH_DPLL_SEL);
d64311ab
JB		 2917 if (pipe == 0) {
2918 temp &= ~(TRANSA_DPLLB_SEL);
c98e9dcf 2919 temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
d64311ab
JB		 2920 } else if (pipe == 1) {
2921 temp &= ~(TRANSB_DPLLB_SEL);
c98e9dcf 2922 temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
d64311ab
JB		 2923 } else if (pipe == 2) {
2924 temp &= ~(TRANSC_DPLLB_SEL);
4b645f14 2925 temp |= (TRANSC_DPLL_ENABLE | transc_sel);
d64311ab 2926 }
c98e9dcf 2927 I915_WRITE(PCH_DPLL_SEL, temp);
c98e9dcf 2928 }
5eddb70b 2929
d9b6cb56
JB		 2930 /* set transcoder timing, panel must allow it */
2931 assert_panel_unlocked(dev_priv, pipe);
5eddb70b
CW		 2932 I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2933 I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2934 I915_WRITE(TRANS_HSYNC(pipe), I915_READ(HSYNC(pipe)));
8db9d77b 2935
5eddb70b
CW		 2936 I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2937 I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2938 I915_WRITE(TRANS_VSYNC(pipe), I915_READ(VSYNC(pipe)));
8db9d77b 2939
5e84e1a4
ZW		 2940 intel_fdi_normal_train(crtc);
2941
c98e9dcf
JB		 2942 /* For PCH DP, enable TRANS_DP_CTL */
2943 if (HAS_PCH_CPT(dev) &&
417e822d
KP		 2944 (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
2945 intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
9325c9f0 2946 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
5eddb70b
CW		 2947 reg = TRANS_DP_CTL(pipe);
2948 temp = I915_READ(reg);
2949 temp &= ~(TRANS_DP_PORT_SEL_MASK |
220cad3c
EA		 2950 TRANS_DP_SYNC_MASK |
2951 TRANS_DP_BPC_MASK);
5eddb70b
CW		 2952 temp |= (TRANS_DP_OUTPUT_ENABLE |
2953 TRANS_DP_ENH_FRAMING);
9325c9f0 2954 temp |= bpc << 9; /* same format but at 11:9 */
c98e9dcf
JB		 2955
2956 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
5eddb70b 2957 temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
c98e9dcf 2958 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
5eddb70b 2959 temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
c98e9dcf
JB		 2960
2961 switch (intel_trans_dp_port_sel(crtc)) {
2962 case PCH_DP_B:
5eddb70b 2963 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf
JB		 2964 break;
2965 case PCH_DP_C:
5eddb70b 2966 temp |= TRANS_DP_PORT_SEL_C;
c98e9dcf
JB		 2967 break;
2968 case PCH_DP_D:
5eddb70b 2969 temp |= TRANS_DP_PORT_SEL_D;
c98e9dcf
JB		 2970 break;
2971 default:
2972 DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
5eddb70b 2973 temp |= TRANS_DP_PORT_SEL_B;
c98e9dcf 2974 break;
32f9d658 2975 }
2c07245f 2976
5eddb70b 2977 I915_WRITE(reg, temp);
6be4a607 2978 }
b52eb4dc 2979
040484af 2980 intel_enable_transcoder(dev_priv, pipe);
f67a559d
JB		 2981}
2982
d4270e57
JB		 2983void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
2984{
2985 struct drm_i915_private *dev_priv = dev->dev_private;
2986 int dslreg = PIPEDSL(pipe), tc2reg = TRANS_CHICKEN2(pipe);
2987 u32 temp;
2988
2989 temp = I915_READ(dslreg);
2990 udelay(500);
2991 if (wait_for(I915_READ(dslreg) != temp, 5)) {
2992 /* Without this, mode sets may fail silently on FDI */
2993 I915_WRITE(tc2reg, TRANS_AUTOTRAIN_GEN_STALL_DIS);
2994 udelay(250);
2995 I915_WRITE(tc2reg, 0);
2996 if (wait_for(I915_READ(dslreg) != temp, 5))
2997 DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
2998 }
2999}
3000
f67a559d
JB		 3001static void ironlake_crtc_enable(struct drm_crtc *crtc)
3002{
3003 struct drm_device *dev = crtc->dev;
3004 struct drm_i915_private *dev_priv = dev->dev_private;
3005 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3006 int pipe = intel_crtc->pipe;
3007 int plane = intel_crtc->plane;
3008 u32 temp;
3009 bool is_pch_port;
3010
3011 if (intel_crtc->active)
3012 return;
3013
3014 intel_crtc->active = true;
3015 intel_update_watermarks(dev);
3016
3017 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3018 temp = I915_READ(PCH_LVDS);
3019 if ((temp & LVDS_PORT_EN) == 0)
3020 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3021 }
3022
3023 is_pch_port = intel_crtc_driving_pch(crtc);
3024
3025 if (is_pch_port)
357555c0 3026 ironlake_fdi_pll_enable(crtc);
f67a559d
JB		 3027 else
3028 ironlake_fdi_disable(crtc);
3029
3030 /* Enable panel fitting for LVDS */
3031 if (dev_priv->pch_pf_size &&
3032 (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) || HAS_eDP)) {
3033 /* Force use of hard-coded filter coefficients
3034 * as some pre-programmed values are broken,
3035 * e.g. x201.
3036 */
9db4a9c7
JB		 3037 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3038 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3039 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
f67a559d
JB		 3040 }
3041
9c54c0dd
JB		 3042 /*
3043 * On ILK+ LUT must be loaded before the pipe is running but with
3044 * clocks enabled
3045 */
3046 intel_crtc_load_lut(crtc);
3047
f67a559d
JB		 3048 intel_enable_pipe(dev_priv, pipe, is_pch_port);
3049 intel_enable_plane(dev_priv, plane, pipe);
3050
3051 if (is_pch_port)
3052 ironlake_pch_enable(crtc);
c98e9dcf 3053
d1ebd816 3054 mutex_lock(&dev->struct_mutex);
bed4a673 3055 intel_update_fbc(dev);
d1ebd816
BW		 3056 mutex_unlock(&dev->struct_mutex);
3057
6b383a7f 3058 intel_crtc_update_cursor(crtc, true);
6be4a607
JB		 3059}
3060
3061static void ironlake_crtc_disable(struct drm_crtc *crtc)
3062{
3063 struct drm_device *dev = crtc->dev;
3064 struct drm_i915_private *dev_priv = dev->dev_private;
3065 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3066 int pipe = intel_crtc->pipe;
3067 int plane = intel_crtc->plane;
5eddb70b 3068 u32 reg, temp;
b52eb4dc 3069
f7abfe8b
CW		 3070 if (!intel_crtc->active)
3071 return;
3072
e6c3a2a6 3073 intel_crtc_wait_for_pending_flips(crtc);
6be4a607 3074 drm_vblank_off(dev, pipe);
6b383a7f 3075 intel_crtc_update_cursor(crtc, false);
5eddb70b 3076
b24e7179 3077 intel_disable_plane(dev_priv, plane, pipe);
913d8d11 3078
973d04f9
CW		 3079 if (dev_priv->cfb_plane == plane)
3080 intel_disable_fbc(dev);
2c07245f 3081
b24e7179 3082 intel_disable_pipe(dev_priv, pipe);
32f9d658 3083
6be4a607 3084 /* Disable PF */
9db4a9c7
JB		 3085 I915_WRITE(PF_CTL(pipe), 0);
3086 I915_WRITE(PF_WIN_SZ(pipe), 0);
2c07245f 3087
0fc932b8 3088 ironlake_fdi_disable(crtc);
2c07245f 3089
47a05eca
JB		 3090 /* This is a horrible layering violation; we should be doing this in
3091 * the connector/encoder ->prepare instead, but we don't always have
3092 * enough information there about the config to know whether it will
3093 * actually be necessary or just cause undesired flicker.
3094 */
3095 intel_disable_pch_ports(dev_priv, pipe);
249c0e64 3096
040484af 3097 intel_disable_transcoder(dev_priv, pipe);
913d8d11 3098
6be4a607
JB		 3099 if (HAS_PCH_CPT(dev)) {
3100 /* disable TRANS_DP_CTL */
5eddb70b
CW		 3101 reg = TRANS_DP_CTL(pipe);
3102 temp = I915_READ(reg);
3103 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
cb3543c6 3104 temp |= TRANS_DP_PORT_SEL_NONE;
5eddb70b 3105 I915_WRITE(reg, temp);
6be4a607
JB		 3106
3107 /* disable DPLL_SEL */
3108 temp = I915_READ(PCH_DPLL_SEL);
9db4a9c7
JB		 3109 switch (pipe) {
3110 case 0:
d64311ab 3111 temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
9db4a9c7
JB		 3112 break;
3113 case 1:
6be4a607 3114 temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
9db4a9c7
JB		 3115 break;
3116 case 2:
4b645f14 3117 /* C shares PLL A or B */
d64311ab 3118 temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
9db4a9c7
JB		 3119 break;
3120 default:
3121 BUG(); /* wtf */
3122 }
6be4a607 3123 I915_WRITE(PCH_DPLL_SEL, temp);
6be4a607 3124 }
e3421a18 3125
6be4a607 3126 /* disable PCH DPLL */
4b645f14
JB		 3127 if (!intel_crtc->no_pll)
3128 intel_disable_pch_pll(dev_priv, pipe);
8db9d77b 3129
6be4a607 3130 /* Switch from PCDclk to Rawclk */
5eddb70b
CW		 3131 reg = FDI_RX_CTL(pipe);
3132 temp = I915_READ(reg);
3133 I915_WRITE(reg, temp & ~FDI_PCDCLK);
8db9d77b 3134
6be4a607 3135 /* Disable CPU FDI TX PLL */
5eddb70b
CW		 3136 reg = FDI_TX_CTL(pipe);
3137 temp = I915_READ(reg);
3138 I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
3139
3140 POSTING_READ(reg);
6be4a607 3141 udelay(100);
8db9d77b 3142
5eddb70b
CW		 3143 reg = FDI_RX_CTL(pipe);
3144 temp = I915_READ(reg);
3145 I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2c07245f 3146
6be4a607 3147 /* Wait for the clocks to turn off. */
5eddb70b 3148 POSTING_READ(reg);
6be4a607 3149 udelay(100);
6b383a7f 3150
f7abfe8b 3151 intel_crtc->active = false;
6b383a7f 3152 intel_update_watermarks(dev);
d1ebd816
BW		 3153
3154 mutex_lock(&dev->struct_mutex);
6b383a7f
CW		 3155 intel_update_fbc(dev);
3156 intel_clear_scanline_wait(dev);
d1ebd816 3157 mutex_unlock(&dev->struct_mutex);
6be4a607 3158}
1b3c7a47 3159
6be4a607
JB		 3160static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
3161{
3162 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3163 int pipe = intel_crtc->pipe;
3164 int plane = intel_crtc->plane;
8db9d77b 3165
6be4a607
JB		 3166 /* XXX: When our outputs are all unaware of DPMS modes other than off
3167 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3168 */
3169 switch (mode) {
3170 case DRM_MODE_DPMS_ON:
3171 case DRM_MODE_DPMS_STANDBY:
3172 case DRM_MODE_DPMS_SUSPEND:
3173 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
3174 ironlake_crtc_enable(crtc);
3175 break;
1b3c7a47 3176
6be4a607
JB		 3177 case DRM_MODE_DPMS_OFF:
3178 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
3179 ironlake_crtc_disable(crtc);
2c07245f
ZW		 3180 break;
3181 }
3182}
3183
02e792fb
DV		 3184static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3185{
02e792fb 3186 if (!enable && intel_crtc->overlay) {
23f09ce3 3187 struct drm_device *dev = intel_crtc->base.dev;
ce453d81 3188 struct drm_i915_private *dev_priv = dev->dev_private;
03f77ea5 3189
23f09ce3 3190 mutex_lock(&dev->struct_mutex);
ce453d81
CW		 3191 dev_priv->mm.interruptible = false;
3192 (void) intel_overlay_switch_off(intel_crtc->overlay);
3193 dev_priv->mm.interruptible = true;
23f09ce3 3194 mutex_unlock(&dev->struct_mutex);
02e792fb 3195 }
02e792fb 3196
5dcdbcb0
CW		 3197 /* Let userspace switch the overlay on again. In most cases userspace
3198 * has to recompute where to put it anyway.
3199 */
02e792fb
DV		 3200}
3201
0b8765c6 3202static void i9xx_crtc_enable(struct drm_crtc *crtc)
79e53945
JB		 3203{
3204 struct drm_device *dev = crtc->dev;
79e53945
JB		 3205 struct drm_i915_private *dev_priv = dev->dev_private;
3206 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3207 int pipe = intel_crtc->pipe;
80824003 3208 int plane = intel_crtc->plane;
79e53945 3209
f7abfe8b
CW		 3210 if (intel_crtc->active)
3211 return;
3212
3213 intel_crtc->active = true;
6b383a7f
CW		 3214 intel_update_watermarks(dev);
3215
63d7bbe9 3216 intel_enable_pll(dev_priv, pipe);
040484af 3217 intel_enable_pipe(dev_priv, pipe, false);
b24e7179 3218 intel_enable_plane(dev_priv, plane, pipe);
79e53945 3219
0b8765c6 3220 intel_crtc_load_lut(crtc);
bed4a673 3221 intel_update_fbc(dev);
79e53945 3222
0b8765c6
JB		 3223 /* Give the overlay scaler a chance to enable if it's on this pipe */
3224 intel_crtc_dpms_overlay(intel_crtc, true);
6b383a7f 3225 intel_crtc_update_cursor(crtc, true);
0b8765c6 3226}
79e53945 3227
0b8765c6
JB		 3228static void i9xx_crtc_disable(struct drm_crtc *crtc)
3229{
3230 struct drm_device *dev = crtc->dev;
3231 struct drm_i915_private *dev_priv = dev->dev_private;
3232 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3233 int pipe = intel_crtc->pipe;
3234 int plane = intel_crtc->plane;
b690e96c 3235
f7abfe8b
CW		 3236 if (!intel_crtc->active)
3237 return;
3238
0b8765c6 3239 /* Give the overlay scaler a chance to disable if it's on this pipe */
e6c3a2a6
CW		 3240 intel_crtc_wait_for_pending_flips(crtc);
3241 drm_vblank_off(dev, pipe);
0b8765c6 3242 intel_crtc_dpms_overlay(intel_crtc, false);
6b383a7f 3243 intel_crtc_update_cursor(crtc, false);
0b8765c6 3244
973d04f9
CW		 3245 if (dev_priv->cfb_plane == plane)
3246 intel_disable_fbc(dev);
79e53945 3247
b24e7179 3248 intel_disable_plane(dev_priv, plane, pipe);
b24e7179 3249 intel_disable_pipe(dev_priv, pipe);
63d7bbe9 3250 intel_disable_pll(dev_priv, pipe);
0b8765c6 3251
f7abfe8b 3252 intel_crtc->active = false;
6b383a7f
CW		 3253 intel_update_fbc(dev);
3254 intel_update_watermarks(dev);
3255 intel_clear_scanline_wait(dev);
0b8765c6
JB		 3256}
3257
3258static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
3259{
3260 /* XXX: When our outputs are all unaware of DPMS modes other than off
3261 * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
3262 */
3263 switch (mode) {
3264 case DRM_MODE_DPMS_ON:
3265 case DRM_MODE_DPMS_STANDBY:
3266 case DRM_MODE_DPMS_SUSPEND:
3267 i9xx_crtc_enable(crtc);
3268 break;
3269 case DRM_MODE_DPMS_OFF:
3270 i9xx_crtc_disable(crtc);
79e53945
JB		 3271 break;
3272 }
2c07245f
ZW		 3273}
3274
3275/**
3276 * Sets the power management mode of the pipe and plane.
2c07245f
ZW		 3277 */
3278static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
3279{
3280 struct drm_device *dev = crtc->dev;
e70236a8 3281 struct drm_i915_private *dev_priv = dev->dev_private;
2c07245f
ZW		 3282 struct drm_i915_master_private *master_priv;
3283 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3284 int pipe = intel_crtc->pipe;
3285 bool enabled;
3286
032d2a0d
CW		 3287 if (intel_crtc->dpms_mode == mode)
3288 return;
3289
65655d4a 3290 intel_crtc->dpms_mode = mode;
debcaddc 3291
e70236a8 3292 dev_priv->display.dpms(crtc, mode);
79e53945
JB		 3293
3294 if (!dev->primary->master)
3295 return;
3296
3297 master_priv = dev->primary->master->driver_priv;
3298 if (!master_priv->sarea_priv)
3299 return;
3300
3301 enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
3302
3303 switch (pipe) {
3304 case 0:
3305 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3306 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3307 break;
3308 case 1:
3309 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3310 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3311 break;
3312 default:
9db4a9c7 3313 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
79e53945
JB		 3314 break;
3315 }
79e53945
JB		 3316}
3317
cdd59983
CW		 3318static void intel_crtc_disable(struct drm_crtc *crtc)
3319{
3320 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3321 struct drm_device *dev = crtc->dev;
3322
3323 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
3324
3325 if (crtc->fb) {
3326 mutex_lock(&dev->struct_mutex);
3327 i915_gem_object_unpin(to_intel_framebuffer(crtc->fb)->obj);
3328 mutex_unlock(&dev->struct_mutex);
3329 }
3330}
3331
7e7d76c3
JB		 3332/* Prepare for a mode set.
3333 *
3334 * Note we could be a lot smarter here. We need to figure out which outputs
3335 * will be enabled, which disabled (in short, how the config will changes)
3336 * and perform the minimum necessary steps to accomplish that, e.g. updating
3337 * watermarks, FBC configuration, making sure PLLs are programmed correctly,
3338 * panel fitting is in the proper state, etc.
3339 */
3340static void i9xx_crtc_prepare(struct drm_crtc *crtc)
79e53945 3341{
7e7d76c3 3342 i9xx_crtc_disable(crtc);
79e53945
JB		 3343}
3344
7e7d76c3 3345static void i9xx_crtc_commit(struct drm_crtc *crtc)
79e53945 3346{
7e7d76c3 3347 i9xx_crtc_enable(crtc);
7e7d76c3
JB		 3348}
3349
3350static void ironlake_crtc_prepare(struct drm_crtc *crtc)
3351{
7e7d76c3 3352 ironlake_crtc_disable(crtc);
7e7d76c3
JB		 3353}
3354
3355static void ironlake_crtc_commit(struct drm_crtc *crtc)
3356{
7e7d76c3 3357 ironlake_crtc_enable(crtc);
79e53945
JB		 3358}
3359
0206e353 3360void intel_encoder_prepare(struct drm_encoder *encoder)
79e53945
JB		 3361{
3362 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3363 /* lvds has its own version of prepare see intel_lvds_prepare */
3364 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
3365}
3366
0206e353 3367void intel_encoder_commit(struct drm_encoder *encoder)
79e53945
JB		 3368{
3369 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
d4270e57
JB		 3370 struct drm_device *dev = encoder->dev;
3371 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3372 struct intel_crtc *intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
3373
79e53945
JB		 3374 /* lvds has its own version of commit see intel_lvds_commit */
3375 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
d4270e57
JB		 3376
3377 if (HAS_PCH_CPT(dev))
3378 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
79e53945
JB		 3379}
3380
ea5b213a
CW		 3381void intel_encoder_destroy(struct drm_encoder *encoder)
3382{
4ef69c7a 3383 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
ea5b213a 3384
ea5b213a
CW		 3385 drm_encoder_cleanup(encoder);
3386 kfree(intel_encoder);
3387}
3388
79e53945
JB		 3389static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3390 struct drm_display_mode *mode,
3391 struct drm_display_mode *adjusted_mode)
3392{
2c07245f 3393 struct drm_device *dev = crtc->dev;
89749350 3394
bad720ff 3395 if (HAS_PCH_SPLIT(dev)) {
2c07245f 3396 /* FDI link clock is fixed at 2.7G */
2377b741
JB		 3397 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3398 return false;
2c07245f 3399 }
89749350
CW		 3400
3401 /* XXX some encoders set the crtcinfo, others don't.
3402 * Obviously we need some form of conflict resolution here...
3403 */
3404 if (adjusted_mode->crtc_htotal == 0)
3405 drm_mode_set_crtcinfo(adjusted_mode, 0);
3406
79e53945
JB		 3407 return true;
3408}
3409
e70236a8
JB		 3410static int i945_get_display_clock_speed(struct drm_device *dev)
3411{
3412 return 400000;
3413}
79e53945 3414
e70236a8 3415static int i915_get_display_clock_speed(struct drm_device *dev)
79e53945 3416{
e70236a8
JB		 3417 return 333000;
3418}
79e53945 3419
e70236a8
JB		 3420static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3421{
3422 return 200000;
3423}
79e53945 3424
e70236a8
JB		 3425static int i915gm_get_display_clock_speed(struct drm_device *dev)
3426{
3427 u16 gcfgc = 0;
79e53945 3428
e70236a8
JB		 3429 pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3430
3431 if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3432 return 133000;
3433 else {
3434 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3435 case GC_DISPLAY_CLOCK_333_MHZ:
3436 return 333000;
3437 default:
3438 case GC_DISPLAY_CLOCK_190_200_MHZ:
3439 return 190000;
79e53945 3440 }
e70236a8
JB		 3441 }
3442}
3443
3444static int i865_get_display_clock_speed(struct drm_device *dev)
3445{
3446 return 266000;
3447}
3448
3449static int i855_get_display_clock_speed(struct drm_device *dev)
3450{
3451 u16 hpllcc = 0;
3452 /* Assume that the hardware is in the high speed state. This
3453 * should be the default.
3454 */
3455 switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3456 case GC_CLOCK_133_200:
3457 case GC_CLOCK_100_200:
3458 return 200000;
3459 case GC_CLOCK_166_250:
3460 return 250000;
3461 case GC_CLOCK_100_133:
79e53945 3462 return 133000;
e70236a8 3463 }
79e53945 3464
e70236a8
JB		 3465 /* Shouldn't happen */
3466 return 0;
3467}
79e53945 3468
e70236a8
JB		 3469static int i830_get_display_clock_speed(struct drm_device *dev)
3470{
3471 return 133000;
79e53945
JB		 3472}
3473
2c07245f
ZW		 3474struct fdi_m_n {
3475 u32 tu;
3476 u32 gmch_m;
3477 u32 gmch_n;
3478 u32 link_m;
3479 u32 link_n;
3480};
3481
3482static void
3483fdi_reduce_ratio(u32 *num, u32 *den)
3484{
3485 while (*num > 0xffffff || *den > 0xffffff) {
3486 *num >>= 1;
3487 *den >>= 1;
3488 }
3489}
3490
2c07245f 3491static void
f2b115e6
AJ		 3492ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
3493 int link_clock, struct fdi_m_n *m_n)
2c07245f 3494{
2c07245f
ZW		 3495 m_n->tu = 64; /* default size */
3496
22ed1113
CW		 3497 /* BUG_ON(pixel_clock > INT_MAX / 36); */
3498 m_n->gmch_m = bits_per_pixel * pixel_clock;
3499 m_n->gmch_n = link_clock * nlanes * 8;
2c07245f
ZW		 3500 fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
3501
22ed1113
CW		 3502 m_n->link_m = pixel_clock;
3503 m_n->link_n = link_clock;
2c07245f
ZW		 3504 fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
3505}
3506
3507
7662c8bd
SL		 3508struct intel_watermark_params {
3509 unsigned long fifo_size;
3510 unsigned long max_wm;
3511 unsigned long default_wm;
3512 unsigned long guard_size;
3513 unsigned long cacheline_size;
3514};
3515
f2b115e6 3516/* Pineview has different values for various configs */
d210246a 3517static const struct intel_watermark_params pineview_display_wm = {
f2b115e6
AJ		 3518 PINEVIEW_DISPLAY_FIFO,
3519 PINEVIEW_MAX_WM,
3520 PINEVIEW_DFT_WM,
3521 PINEVIEW_GUARD_WM,
3522 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3523};
d210246a 3524static const struct intel_watermark_params pineview_display_hplloff_wm = {
f2b115e6
AJ		 3525 PINEVIEW_DISPLAY_FIFO,
3526 PINEVIEW_MAX_WM,
3527 PINEVIEW_DFT_HPLLOFF_WM,
3528 PINEVIEW_GUARD_WM,
3529 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3530};
d210246a 3531static const struct intel_watermark_params pineview_cursor_wm = {
f2b115e6
AJ		 3532 PINEVIEW_CURSOR_FIFO,
3533 PINEVIEW_CURSOR_MAX_WM,
3534 PINEVIEW_CURSOR_DFT_WM,
3535 PINEVIEW_CURSOR_GUARD_WM,
3536 PINEVIEW_FIFO_LINE_SIZE,
7662c8bd 3537};
d210246a 3538static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
f2b115e6
AJ		 3539 PINEVIEW_CURSOR_FIFO,
3540 PINEVIEW_CURSOR_MAX_WM,
3541 PINEVIEW_CURSOR_DFT_WM,
3542 PINEVIEW_CURSOR_GUARD_WM,
3543 PINEVIEW_FIFO_LINE_SIZE
7662c8bd 3544};
d210246a 3545static const struct intel_watermark_params g4x_wm_info = {
0e442c60
JB		 3546 G4X_FIFO_SIZE,
3547 G4X_MAX_WM,
3548 G4X_MAX_WM,
3549 2,
3550 G4X_FIFO_LINE_SIZE,
3551};
d210246a 3552static const struct intel_watermark_params g4x_cursor_wm_info = {
4fe5e611
ZY		 3553 I965_CURSOR_FIFO,
3554 I965_CURSOR_MAX_WM,
3555 I965_CURSOR_DFT_WM,
3556 2,
3557 G4X_FIFO_LINE_SIZE,
3558};
d210246a 3559static const struct intel_watermark_params i965_cursor_wm_info = {
4fe5e611
ZY		 3560 I965_CURSOR_FIFO,
3561 I965_CURSOR_MAX_WM,
3562 I965_CURSOR_DFT_WM,
3563 2,
3564 I915_FIFO_LINE_SIZE,
3565};
d210246a 3566static const struct intel_watermark_params i945_wm_info = {
dff33cfc 3567 I945_FIFO_SIZE,
7662c8bd
SL		 3568 I915_MAX_WM,
3569 1,
dff33cfc
JB		 3570 2,
3571 I915_FIFO_LINE_SIZE
7662c8bd 3572};
d210246a 3573static const struct intel_watermark_params i915_wm_info = {
dff33cfc 3574 I915_FIFO_SIZE,
7662c8bd
SL		 3575 I915_MAX_WM,
3576 1,
dff33cfc 3577 2,
7662c8bd
SL		 3578 I915_FIFO_LINE_SIZE
3579};
d210246a 3580static const struct intel_watermark_params i855_wm_info = {
7662c8bd
SL		 3581 I855GM_FIFO_SIZE,
3582 I915_MAX_WM,
3583 1,
dff33cfc 3584 2,
7662c8bd
SL		 3585 I830_FIFO_LINE_SIZE
3586};
d210246a 3587static const struct intel_watermark_params i830_wm_info = {
7662c8bd
SL		 3588 I830_FIFO_SIZE,
3589 I915_MAX_WM,
3590 1,
dff33cfc 3591 2,
7662c8bd
SL		 3592 I830_FIFO_LINE_SIZE
3593};
3594
d210246a 3595static const struct intel_watermark_params ironlake_display_wm_info = {
7f8a8569
ZW		 3596 ILK_DISPLAY_FIFO,
3597 ILK_DISPLAY_MAXWM,
3598 ILK_DISPLAY_DFTWM,
3599 2,
3600 ILK_FIFO_LINE_SIZE
3601};
d210246a 3602static const struct intel_watermark_params ironlake_cursor_wm_info = {
c936f44d
ZY		 3603 ILK_CURSOR_FIFO,
3604 ILK_CURSOR_MAXWM,
3605 ILK_CURSOR_DFTWM,
3606 2,
3607 ILK_FIFO_LINE_SIZE
3608};
d210246a 3609static const struct intel_watermark_params ironlake_display_srwm_info = {
7f8a8569
ZW		 3610 ILK_DISPLAY_SR_FIFO,
3611 ILK_DISPLAY_MAX_SRWM,
3612 ILK_DISPLAY_DFT_SRWM,
3613 2,
3614 ILK_FIFO_LINE_SIZE
3615};
d210246a 3616static const struct intel_watermark_params ironlake_cursor_srwm_info = {
7f8a8569
ZW		 3617 ILK_CURSOR_SR_FIFO,
3618 ILK_CURSOR_MAX_SRWM,
3619 ILK_CURSOR_DFT_SRWM,
3620 2,
3621 ILK_FIFO_LINE_SIZE
3622};
3623
d210246a 3624static const struct intel_watermark_params sandybridge_display_wm_info = {
1398261a
YL		 3625 SNB_DISPLAY_FIFO,
3626 SNB_DISPLAY_MAXWM,
3627 SNB_DISPLAY_DFTWM,
3628 2,
3629 SNB_FIFO_LINE_SIZE
3630};
d210246a 3631static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1398261a
YL		 3632 SNB_CURSOR_FIFO,
3633 SNB_CURSOR_MAXWM,
3634 SNB_CURSOR_DFTWM,
3635 2,
3636 SNB_FIFO_LINE_SIZE
3637};
d210246a 3638static const struct intel_watermark_params sandybridge_display_srwm_info = {
1398261a
YL		 3639 SNB_DISPLAY_SR_FIFO,
3640 SNB_DISPLAY_MAX_SRWM,
3641 SNB_DISPLAY_DFT_SRWM,
3642 2,
3643 SNB_FIFO_LINE_SIZE
3644};
d210246a 3645static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1398261a
YL		 3646 SNB_CURSOR_SR_FIFO,
3647 SNB_CURSOR_MAX_SRWM,
3648 SNB_CURSOR_DFT_SRWM,
3649 2,
3650 SNB_FIFO_LINE_SIZE
3651};
3652
3653
dff33cfc
JB		 3654/**
3655 * intel_calculate_wm - calculate watermark level
3656 * @clock_in_khz: pixel clock
3657 * @wm: chip FIFO params
3658 * @pixel_size: display pixel size
3659 * @latency_ns: memory latency for the platform
3660 *
3661 * Calculate the watermark level (the level at which the display plane will
3662 * start fetching from memory again). Each chip has a different display
3663 * FIFO size and allocation, so the caller needs to figure that out and pass
3664 * in the correct intel_watermark_params structure.
3665 *
3666 * As the pixel clock runs, the FIFO will be drained at a rate that depends
3667 * on the pixel size. When it reaches the watermark level, it'll start
3668 * fetching FIFO line sized based chunks from memory until the FIFO fills
3669 * past the watermark point. If the FIFO drains completely, a FIFO underrun
3670 * will occur, and a display engine hang could result.
3671 */
7662c8bd 3672static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
d210246a
CW		 3673 const struct intel_watermark_params *wm,
3674 int fifo_size,
7662c8bd
SL		 3675 int pixel_size,
3676 unsigned long latency_ns)
3677{
390c4dd4 3678 long entries_required, wm_size;
dff33cfc 3679
d660467c
JB		 3680 /*
3681 * Note: we need to make sure we don't overflow for various clock &
3682 * latency values.
3683 * clocks go from a few thousand to several hundred thousand.
3684 * latency is usually a few thousand
3685 */
3686 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
3687 1000;
8de9b311 3688 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
7662c8bd 3689
bbb0aef5 3690 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
dff33cfc 3691
d210246a 3692 wm_size = fifo_size - (entries_required + wm->guard_size);
dff33cfc 3693
bbb0aef5 3694 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
7662c8bd 3695
390c4dd4
JB		 3696 /* Don't promote wm_size to unsigned... */
3697 if (wm_size > (long)wm->max_wm)
7662c8bd 3698 wm_size = wm->max_wm;
c3add4b6 3699 if (wm_size <= 0)
7662c8bd
SL		 3700 wm_size = wm->default_wm;
3701 return wm_size;
3702}
3703
3704struct cxsr_latency {
3705 int is_desktop;
95534263 3706 int is_ddr3;
7662c8bd
SL		 3707 unsigned long fsb_freq;
3708 unsigned long mem_freq;
3709 unsigned long display_sr;
3710 unsigned long display_hpll_disable;
3711 unsigned long cursor_sr;
3712 unsigned long cursor_hpll_disable;
3713};
3714
403c89ff 3715static const struct cxsr_latency cxsr_latency_table[] = {
95534263
LP		 3716 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
3717 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
3718 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
3719 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
3720 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
3721
3722 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
3723 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
3724 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
3725 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
3726 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
3727
3728 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
3729 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
3730 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
3731 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
3732 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
3733
3734 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
3735 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
3736 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
3737 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
3738 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
3739
3740 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
3741 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
3742 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
3743 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
3744 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
3745
3746 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
3747 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
3748 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
3749 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
3750 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
7662c8bd
SL		 3751};
3752
403c89ff
CW		 3753static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
3754 int is_ddr3,
3755 int fsb,
3756 int mem)
7662c8bd 3757{
403c89ff 3758 const struct cxsr_latency *latency;
7662c8bd 3759 int i;
7662c8bd
SL		 3760
3761 if (fsb == 0 || mem == 0)
3762 return NULL;
3763
3764 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
3765 latency = &cxsr_latency_table[i];
3766 if (is_desktop == latency->is_desktop &&
95534263 3767 is_ddr3 == latency->is_ddr3 &&
decbbcda
JSR		 3768 fsb == latency->fsb_freq && mem == latency->mem_freq)
3769 return latency;
7662c8bd 3770 }
decbbcda 3771
28c97730 3772 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
decbbcda
JSR		 3773
3774 return NULL;
7662c8bd
SL		 3775}
3776
f2b115e6 3777static void pineview_disable_cxsr(struct drm_device *dev)
7662c8bd
SL		 3778{
3779 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd
SL		 3780
3781 /* deactivate cxsr */
3e33d94d 3782 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
7662c8bd
SL		 3783}
3784
bcc24fb4
JB		 3785/*
3786 * Latency for FIFO fetches is dependent on several factors:
3787 * - memory configuration (speed, channels)
3788 * - chipset
3789 * - current MCH state
3790 * It can be fairly high in some situations, so here we assume a fairly
3791 * pessimal value. It's a tradeoff between extra memory fetches (if we
3792 * set this value too high, the FIFO will fetch frequently to stay full)
3793 * and power consumption (set it too low to save power and we might see
3794 * FIFO underruns and display "flicker").
3795 *
3796 * A value of 5us seems to be a good balance; safe for very low end
3797 * platforms but not overly aggressive on lower latency configs.
3798 */
69e302a9 3799static const int latency_ns = 5000;
7662c8bd 3800
e70236a8 3801static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
dff33cfc
JB		 3802{
3803 struct drm_i915_private *dev_priv = dev->dev_private;
3804 uint32_t dsparb = I915_READ(DSPARB);
3805 int size;
3806
8de9b311
CW		 3807 size = dsparb & 0x7f;
3808 if (plane)
3809 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
dff33cfc 3810
28c97730 3811 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3812 plane ? "B" : "A", size);
dff33cfc
JB		 3813
3814 return size;
3815}
7662c8bd 3816
e70236a8
JB		 3817static int i85x_get_fifo_size(struct drm_device *dev, int plane)
3818{
3819 struct drm_i915_private *dev_priv = dev->dev_private;
3820 uint32_t dsparb = I915_READ(DSPARB);
3821 int size;
3822
8de9b311
CW		 3823 size = dsparb & 0x1ff;
3824 if (plane)
3825 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
e70236a8 3826 size >>= 1; /* Convert to cachelines */
dff33cfc 3827
28c97730 3828 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3829 plane ? "B" : "A", size);
dff33cfc
JB		 3830
3831 return size;
3832}
7662c8bd 3833
e70236a8
JB		 3834static int i845_get_fifo_size(struct drm_device *dev, int plane)
3835{
3836 struct drm_i915_private *dev_priv = dev->dev_private;
3837 uint32_t dsparb = I915_READ(DSPARB);
3838 int size;
3839
3840 size = dsparb & 0x7f;
3841 size >>= 2; /* Convert to cachelines */
3842
28c97730 3843 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b
CW		 3844 plane ? "B" : "A",
3845 size);
e70236a8
JB		 3846
3847 return size;
3848}
3849
3850static int i830_get_fifo_size(struct drm_device *dev, int plane)
3851{
3852 struct drm_i915_private *dev_priv = dev->dev_private;
3853 uint32_t dsparb = I915_READ(DSPARB);
3854 int size;
3855
3856 size = dsparb & 0x7f;
3857 size >>= 1; /* Convert to cachelines */
3858
28c97730 3859 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
5eddb70b 3860 plane ? "B" : "A", size);
e70236a8
JB		 3861
3862 return size;
3863}
3864
d210246a
CW		 3865static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
3866{
3867 struct drm_crtc *crtc, *enabled = NULL;
3868
3869 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3870 if (crtc->enabled && crtc->fb) {
3871 if (enabled)
3872 return NULL;
3873 enabled = crtc;
3874 }
3875 }
3876
3877 return enabled;
3878}
3879
3880static void pineview_update_wm(struct drm_device *dev)
d4294342
ZY		 3881{
3882 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 3883 struct drm_crtc *crtc;
403c89ff 3884 const struct cxsr_latency *latency;
d4294342
ZY		 3885 u32 reg;
3886 unsigned long wm;
d4294342 3887
403c89ff 3888 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
95534263 3889 dev_priv->fsb_freq, dev_priv->mem_freq);
d4294342
ZY		 3890 if (!latency) {
3891 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3892 pineview_disable_cxsr(dev);
3893 return;
3894 }
3895
d210246a
CW		 3896 crtc = single_enabled_crtc(dev);
3897 if (crtc) {
3898 int clock = crtc->mode.clock;
3899 int pixel_size = crtc->fb->bits_per_pixel / 8;
d4294342
ZY		 3900
3901 /* Display SR */
d210246a
CW		 3902 wm = intel_calculate_wm(clock, &pineview_display_wm,
3903 pineview_display_wm.fifo_size,
d4294342
ZY		 3904 pixel_size, latency->display_sr);
3905 reg = I915_READ(DSPFW1);
3906 reg &= ~DSPFW_SR_MASK;
3907 reg |= wm << DSPFW_SR_SHIFT;
3908 I915_WRITE(DSPFW1, reg);
3909 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3910
3911 /* cursor SR */
d210246a
CW		 3912 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
3913 pineview_display_wm.fifo_size,
d4294342
ZY		 3914 pixel_size, latency->cursor_sr);
3915 reg = I915_READ(DSPFW3);
3916 reg &= ~DSPFW_CURSOR_SR_MASK;
3917 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3918 I915_WRITE(DSPFW3, reg);
3919
3920 /* Display HPLL off SR */
d210246a
CW		 3921 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
3922 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3923 pixel_size, latency->display_hpll_disable);
3924 reg = I915_READ(DSPFW3);
3925 reg &= ~DSPFW_HPLL_SR_MASK;
3926 reg |= wm & DSPFW_HPLL_SR_MASK;
3927 I915_WRITE(DSPFW3, reg);
3928
3929 /* cursor HPLL off SR */
d210246a
CW		 3930 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
3931 pineview_display_hplloff_wm.fifo_size,
d4294342
ZY		 3932 pixel_size, latency->cursor_hpll_disable);
3933 reg = I915_READ(DSPFW3);
3934 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3935 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3936 I915_WRITE(DSPFW3, reg);
3937 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3938
3939 /* activate cxsr */
3e33d94d
CW		 3940 I915_WRITE(DSPFW3,
3941 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
d4294342
ZY		 3942 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3943 } else {
3944 pineview_disable_cxsr(dev);
3945 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3946 }
3947}
3948
417ae147
CW		 3949static bool g4x_compute_wm0(struct drm_device *dev,
3950 int plane,
3951 const struct intel_watermark_params *display,
3952 int display_latency_ns,
3953 const struct intel_watermark_params *cursor,
3954 int cursor_latency_ns,
3955 int *plane_wm,
3956 int *cursor_wm)
3957{
3958 struct drm_crtc *crtc;
3959 int htotal, hdisplay, clock, pixel_size;
3960 int line_time_us, line_count;
3961 int entries, tlb_miss;
3962
3963 crtc = intel_get_crtc_for_plane(dev, plane);
5c72d064
CW		 3964 if (crtc->fb == NULL || !crtc->enabled) {
3965 *cursor_wm = cursor->guard_size;
3966 *plane_wm = display->guard_size;
417ae147 3967 return false;
5c72d064 3968 }
417ae147
CW		 3969
3970 htotal = crtc->mode.htotal;
3971 hdisplay = crtc->mode.hdisplay;
3972 clock = crtc->mode.clock;
3973 pixel_size = crtc->fb->bits_per_pixel / 8;
3974
3975 /* Use the small buffer method to calculate plane watermark */
3976 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
3977 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
3978 if (tlb_miss > 0)
3979 entries += tlb_miss;
3980 entries = DIV_ROUND_UP(entries, display->cacheline_size);
3981 *plane_wm = entries + display->guard_size;
3982 if (*plane_wm > (int)display->max_wm)
3983 *plane_wm = display->max_wm;
3984
3985 /* Use the large buffer method to calculate cursor watermark */
3986 line_time_us = ((htotal * 1000) / clock);
3987 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3988 entries = line_count * 64 * pixel_size;
3989 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
3990 if (tlb_miss > 0)
3991 entries += tlb_miss;
3992 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
3993 *cursor_wm = entries + cursor->guard_size;
3994 if (*cursor_wm > (int)cursor->max_wm)
3995 *cursor_wm = (int)cursor->max_wm;
3996
3997 return true;
3998}
3999
4000/*
4001 * Check the wm result.
4002 *
4003 * If any calculated watermark values is larger than the maximum value that
4004 * can be programmed into the associated watermark register, that watermark
4005 * must be disabled.
4006 */
4007static bool g4x_check_srwm(struct drm_device *dev,
4008 int display_wm, int cursor_wm,
4009 const struct intel_watermark_params *display,
4010 const struct intel_watermark_params *cursor)
652c393a 4011{
417ae147
CW		 4012 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
4013 display_wm, cursor_wm);
652c393a 4014
417ae147 4015 if (display_wm > display->max_wm) {
bbb0aef5 4016 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 4017 display_wm, display->max_wm);
4018 return false;
4019 }
0e442c60 4020
417ae147 4021 if (cursor_wm > cursor->max_wm) {
bbb0aef5 4022 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
417ae147
CW		 4023 cursor_wm, cursor->max_wm);
4024 return false;
4025 }
0e442c60 4026
417ae147
CW		 4027 if (!(display_wm || cursor_wm)) {
4028 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
4029 return false;
4030 }
0e442c60 4031
417ae147
CW		 4032 return true;
4033}
0e442c60 4034
417ae147 4035static bool g4x_compute_srwm(struct drm_device *dev,
d210246a
CW		 4036 int plane,
4037 int latency_ns,
417ae147
CW		 4038 const struct intel_watermark_params *display,
4039 const struct intel_watermark_params *cursor,
4040 int *display_wm, int *cursor_wm)
4041{
d210246a
CW		 4042 struct drm_crtc *crtc;
4043 int hdisplay, htotal, pixel_size, clock;
417ae147
CW		 4044 unsigned long line_time_us;
4045 int line_count, line_size;
4046 int small, large;
4047 int entries;
0e442c60 4048
417ae147
CW		 4049 if (!latency_ns) {
4050 *display_wm = *cursor_wm = 0;
4051 return false;
4052 }
0e442c60 4053
d210246a
CW		 4054 crtc = intel_get_crtc_for_plane(dev, plane);
4055 hdisplay = crtc->mode.hdisplay;
4056 htotal = crtc->mode.htotal;
4057 clock = crtc->mode.clock;
4058 pixel_size = crtc->fb->bits_per_pixel / 8;
4059
417ae147
CW		 4060 line_time_us = (htotal * 1000) / clock;
4061 line_count = (latency_ns / line_time_us + 1000) / 1000;
4062 line_size = hdisplay * pixel_size;
0e442c60 4063
417ae147
CW		 4064 /* Use the minimum of the small and large buffer method for primary */
4065 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4066 large = line_count * line_size;
0e442c60 4067
417ae147
CW		 4068 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4069 *display_wm = entries + display->guard_size;
4fe5e611 4070
417ae147
CW		 4071 /* calculate the self-refresh watermark for display cursor */
4072 entries = line_count * pixel_size * 64;
4073 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4074 *cursor_wm = entries + cursor->guard_size;
4fe5e611 4075
417ae147
CW		 4076 return g4x_check_srwm(dev,
4077 *display_wm, *cursor_wm,
4078 display, cursor);
4079}
4fe5e611 4080
7ccb4a53 4081#define single_plane_enabled(mask) is_power_of_2(mask)
d210246a
CW		 4082
4083static void g4x_update_wm(struct drm_device *dev)
417ae147
CW		 4084{
4085 static const int sr_latency_ns = 12000;
4086 struct drm_i915_private *dev_priv = dev->dev_private;
4087 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
d210246a
CW		 4088 int plane_sr, cursor_sr;
4089 unsigned int enabled = 0;
417ae147
CW		 4090
4091 if (g4x_compute_wm0(dev, 0,
4092 &g4x_wm_info, latency_ns,
4093 &g4x_cursor_wm_info, latency_ns,
4094 &planea_wm, &cursora_wm))
d210246a 4095 enabled |= 1;
417ae147
CW		 4096
4097 if (g4x_compute_wm0(dev, 1,
4098 &g4x_wm_info, latency_ns,
4099 &g4x_cursor_wm_info, latency_ns,
4100 &planeb_wm, &cursorb_wm))
d210246a 4101 enabled |= 2;
417ae147
CW		 4102
4103 plane_sr = cursor_sr = 0;
d210246a
CW		 4104 if (single_plane_enabled(enabled) &&
4105 g4x_compute_srwm(dev, ffs(enabled) - 1,
4106 sr_latency_ns,
417ae147
CW		 4107 &g4x_wm_info,
4108 &g4x_cursor_wm_info,
4109 &plane_sr, &cursor_sr))
0e442c60 4110 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
417ae147
CW		 4111 else
4112 I915_WRITE(FW_BLC_SELF,
4113 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
0e442c60 4114
308977ac
CW		 4115 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
4116 planea_wm, cursora_wm,
4117 planeb_wm, cursorb_wm,
4118 plane_sr, cursor_sr);
0e442c60 4119
417ae147
CW		 4120 I915_WRITE(DSPFW1,
4121 (plane_sr << DSPFW_SR_SHIFT) |
0e442c60 4122 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
417ae147
CW		 4123 (planeb_wm << DSPFW_PLANEB_SHIFT) |
4124 planea_wm);
4125 I915_WRITE(DSPFW2,
4126 (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
0e442c60
JB		 4127 (cursora_wm << DSPFW_CURSORA_SHIFT));
4128 /* HPLL off in SR has some issues on G4x... disable it */
417ae147
CW		 4129 I915_WRITE(DSPFW3,
4130 (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
0e442c60 4131 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
652c393a
JB		 4132}
4133
d210246a 4134static void i965_update_wm(struct drm_device *dev)
7662c8bd
SL		 4135{
4136 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4137 struct drm_crtc *crtc;
4138 int srwm = 1;
4fe5e611 4139 int cursor_sr = 16;
1dc7546d
JB		 4140
4141 /* Calc sr entries for one plane configs */
d210246a
CW		 4142 crtc = single_enabled_crtc(dev);
4143 if (crtc) {
1dc7546d 4144 /* self-refresh has much higher latency */
69e302a9 4145 static const int sr_latency_ns = 12000;
d210246a
CW		 4146 int clock = crtc->mode.clock;
4147 int htotal = crtc->mode.htotal;
4148 int hdisplay = crtc->mode.hdisplay;
4149 int pixel_size = crtc->fb->bits_per_pixel / 8;
4150 unsigned long line_time_us;
4151 int entries;
1dc7546d 4152
d210246a 4153 line_time_us = ((htotal * 1000) / clock);
1dc7546d
JB		 4154
4155 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4156 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4157 pixel_size * hdisplay;
4158 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
d210246a 4159 srwm = I965_FIFO_SIZE - entries;
1dc7546d
JB		 4160 if (srwm < 0)
4161 srwm = 1;
1b07e04e 4162 srwm &= 0x1ff;
308977ac
CW		 4163 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
4164 entries, srwm);
4fe5e611 4165
d210246a 4166 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
5eddb70b 4167 pixel_size * 64;
d210246a 4168 entries = DIV_ROUND_UP(entries,
8de9b311 4169 i965_cursor_wm_info.cacheline_size);
4fe5e611 4170 cursor_sr = i965_cursor_wm_info.fifo_size -
d210246a 4171 (entries + i965_cursor_wm_info.guard_size);
4fe5e611
ZY		 4172
4173 if (cursor_sr > i965_cursor_wm_info.max_wm)
4174 cursor_sr = i965_cursor_wm_info.max_wm;
4175
4176 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
4177 "cursor %d\n", srwm, cursor_sr);
4178
a6c45cf0 4179 if (IS_CRESTLINE(dev))
adcdbc66 4180 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
33c5fd12
DJ		 4181 } else {
4182 /* Turn off self refresh if both pipes are enabled */
a6c45cf0 4183 if (IS_CRESTLINE(dev))
adcdbc66
JB		 4184 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
4185 & ~FW_BLC_SELF_EN);
1dc7546d 4186 }
7662c8bd 4187
1dc7546d
JB		 4188 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
4189 srwm);
7662c8bd
SL		 4190
4191 /* 965 has limitations... */
417ae147
CW		 4192 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
4193 (8 << 16) | (8 << 8) | (8 << 0));
7662c8bd 4194 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
4fe5e611
ZY		 4195 /* update cursor SR watermark */
4196 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
7662c8bd
SL		 4197}
4198
d210246a 4199static void i9xx_update_wm(struct drm_device *dev)
7662c8bd
SL		 4200{
4201 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a 4202 const struct intel_watermark_params *wm_info;
dff33cfc
JB		 4203 uint32_t fwater_lo;
4204 uint32_t fwater_hi;
d210246a
CW		 4205 int cwm, srwm = 1;
4206 int fifo_size;
dff33cfc 4207 int planea_wm, planeb_wm;
d210246a 4208 struct drm_crtc *crtc, *enabled = NULL;
7662c8bd 4209
72557b4f 4210 if (IS_I945GM(dev))
d210246a 4211 wm_info = &i945_wm_info;
a6c45cf0 4212 else if (!IS_GEN2(dev))
d210246a 4213 wm_info = &i915_wm_info;
7662c8bd 4214 else
d210246a
CW		 4215 wm_info = &i855_wm_info;
4216
4217 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
4218 crtc = intel_get_crtc_for_plane(dev, 0);
4219 if (crtc->enabled && crtc->fb) {
4220 planea_wm = intel_calculate_wm(crtc->mode.clock,
4221 wm_info, fifo_size,
4222 crtc->fb->bits_per_pixel / 8,
4223 latency_ns);
4224 enabled = crtc;
4225 } else
4226 planea_wm = fifo_size - wm_info->guard_size;
4227
4228 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
4229 crtc = intel_get_crtc_for_plane(dev, 1);
4230 if (crtc->enabled && crtc->fb) {
4231 planeb_wm = intel_calculate_wm(crtc->mode.clock,
4232 wm_info, fifo_size,
4233 crtc->fb->bits_per_pixel / 8,
4234 latency_ns);
4235 if (enabled == NULL)
4236 enabled = crtc;
4237 else
4238 enabled = NULL;
4239 } else
4240 planeb_wm = fifo_size - wm_info->guard_size;
7662c8bd 4241
28c97730 4242 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
7662c8bd
SL		 4243
4244 /*
4245 * Overlay gets an aggressive default since video jitter is bad.
4246 */
4247 cwm = 2;
4248
18b2190c
AL		 4249 /* Play safe and disable self-refresh before adjusting watermarks. */
4250 if (IS_I945G(dev) || IS_I945GM(dev))
4251 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
4252 else if (IS_I915GM(dev))
4253 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
4254
dff33cfc 4255 /* Calc sr entries for one plane configs */
d210246a 4256 if (HAS_FW_BLC(dev) && enabled) {
dff33cfc 4257 /* self-refresh has much higher latency */
69e302a9 4258 static const int sr_latency_ns = 6000;
d210246a
CW		 4259 int clock = enabled->mode.clock;
4260 int htotal = enabled->mode.htotal;
4261 int hdisplay = enabled->mode.hdisplay;
4262 int pixel_size = enabled->fb->bits_per_pixel / 8;
4263 unsigned long line_time_us;
4264 int entries;
dff33cfc 4265
d210246a 4266 line_time_us = (htotal * 1000) / clock;
dff33cfc
JB		 4267
4268 /* Use ns/us then divide to preserve precision */
d210246a
CW		 4269 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
4270 pixel_size * hdisplay;
4271 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
4272 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
4273 srwm = wm_info->fifo_size - entries;
dff33cfc
JB		 4274 if (srwm < 0)
4275 srwm = 1;
ee980b80
LP		 4276
4277 if (IS_I945G(dev) || IS_I945GM(dev))
18b2190c
AL		 4278 I915_WRITE(FW_BLC_SELF,
4279 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
4280 else if (IS_I915GM(dev))
ee980b80 4281 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
7662c8bd
SL		 4282 }
4283
28c97730 4284 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
5eddb70b 4285 planea_wm, planeb_wm, cwm, srwm);
7662c8bd 4286
dff33cfc
JB		 4287 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
4288 fwater_hi = (cwm & 0x1f);
4289
4290 /* Set request length to 8 cachelines per fetch */
4291 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
4292 fwater_hi = fwater_hi | (1 << 8);
7662c8bd
SL		 4293
4294 I915_WRITE(FW_BLC, fwater_lo);
4295 I915_WRITE(FW_BLC2, fwater_hi);
18b2190c 4296
d210246a
CW		 4297 if (HAS_FW_BLC(dev)) {
4298 if (enabled) {
4299 if (IS_I945G(dev) || IS_I945GM(dev))
4300 I915_WRITE(FW_BLC_SELF,
4301 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4302 else if (IS_I915GM(dev))
4303 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
4304 DRM_DEBUG_KMS("memory self refresh enabled\n");
4305 } else
4306 DRM_DEBUG_KMS("memory self refresh disabled\n");
4307 }
7662c8bd
SL		 4308}
4309
d210246a 4310static void i830_update_wm(struct drm_device *dev)
7662c8bd
SL		 4311{
4312 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4313 struct drm_crtc *crtc;
4314 uint32_t fwater_lo;
dff33cfc 4315 int planea_wm;
7662c8bd 4316
d210246a
CW		 4317 crtc = single_enabled_crtc(dev);
4318 if (crtc == NULL)
4319 return;
7662c8bd 4320
d210246a
CW		 4321 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
4322 dev_priv->display.get_fifo_size(dev, 0),
4323 crtc->fb->bits_per_pixel / 8,
4324 latency_ns);
4325 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
f3601326
JB		 4326 fwater_lo |= (3<<8) | planea_wm;
4327
28c97730 4328 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
7662c8bd
SL		 4329
4330 I915_WRITE(FW_BLC, fwater_lo);
4331}
4332
7f8a8569 4333#define ILK_LP0_PLANE_LATENCY 700
c936f44d 4334#define ILK_LP0_CURSOR_LATENCY 1300
7f8a8569 4335
1398261a
YL		 4336/*
4337 * Check the wm result.
4338 *
4339 * If any calculated watermark values is larger than the maximum value that
4340 * can be programmed into the associated watermark register, that watermark
4341 * must be disabled.
1398261a 4342 */
b79d4990
JB		 4343static bool ironlake_check_srwm(struct drm_device *dev, int level,
4344 int fbc_wm, int display_wm, int cursor_wm,
4345 const struct intel_watermark_params *display,
4346 const struct intel_watermark_params *cursor)
1398261a
YL		 4347{
4348 struct drm_i915_private *dev_priv = dev->dev_private;
4349
4350 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
4351 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
4352
4353 if (fbc_wm > SNB_FBC_MAX_SRWM) {
4354 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4355 fbc_wm, SNB_FBC_MAX_SRWM, level);
1398261a
YL		 4356
4357 /* fbc has it's own way to disable FBC WM */
4358 I915_WRITE(DISP_ARB_CTL,
4359 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
4360 return false;
4361 }
4362
b79d4990 4363 if (display_wm > display->max_wm) {
1398261a 4364 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4365 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1398261a
YL		 4366 return false;
4367 }
4368
b79d4990 4369 if (cursor_wm > cursor->max_wm) {
1398261a 4370 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
b79d4990 4371 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1398261a
YL		 4372 return false;
4373 }
4374
4375 if (!(fbc_wm || display_wm || cursor_wm)) {
4376 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
4377 return false;
4378 }
4379
4380 return true;
4381}
4382
4383/*
4384 * Compute watermark values of WM[1-3],
4385 */
d210246a
CW		 4386static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
4387 int latency_ns,
b79d4990
JB		 4388 const struct intel_watermark_params *display,
4389 const struct intel_watermark_params *cursor,
4390 int *fbc_wm, int *display_wm, int *cursor_wm)
1398261a 4391{
d210246a 4392 struct drm_crtc *crtc;
1398261a 4393 unsigned long line_time_us;
d210246a 4394 int hdisplay, htotal, pixel_size, clock;
b79d4990 4395 int line_count, line_size;
1398261a
YL		 4396 int small, large;
4397 int entries;
1398261a
YL		 4398
4399 if (!latency_ns) {
4400 *fbc_wm = *display_wm = *cursor_wm = 0;
4401 return false;
4402 }
4403
d210246a
CW		 4404 crtc = intel_get_crtc_for_plane(dev, plane);
4405 hdisplay = crtc->mode.hdisplay;
4406 htotal = crtc->mode.htotal;
4407 clock = crtc->mode.clock;
4408 pixel_size = crtc->fb->bits_per_pixel / 8;
4409
1398261a
YL		 4410 line_time_us = (htotal * 1000) / clock;
4411 line_count = (latency_ns / line_time_us + 1000) / 1000;
4412 line_size = hdisplay * pixel_size;
4413
4414 /* Use the minimum of the small and large buffer method for primary */
4415 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4416 large = line_count * line_size;
4417
b79d4990
JB		 4418 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4419 *display_wm = entries + display->guard_size;
1398261a
YL		 4420
4421 /*
b79d4990 4422 * Spec says:
1398261a
YL		 4423 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
4424 */
4425 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
4426
4427 /* calculate the self-refresh watermark for display cursor */
4428 entries = line_count * pixel_size * 64;
b79d4990
JB		 4429 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
4430 *cursor_wm = entries + cursor->guard_size;
1398261a 4431
b79d4990
JB		 4432 return ironlake_check_srwm(dev, level,
4433 *fbc_wm, *display_wm, *cursor_wm,
4434 display, cursor);
4435}
4436
d210246a 4437static void ironlake_update_wm(struct drm_device *dev)
b79d4990
JB		 4438{
4439 struct drm_i915_private *dev_priv = dev->dev_private;
d210246a
CW		 4440 int fbc_wm, plane_wm, cursor_wm;
4441 unsigned int enabled;
b79d4990
JB		 4442
4443 enabled = 0;
9f405100
CW		 4444 if (g4x_compute_wm0(dev, 0,
4445 &ironlake_display_wm_info,
4446 ILK_LP0_PLANE_LATENCY,
4447 &ironlake_cursor_wm_info,
4448 ILK_LP0_CURSOR_LATENCY,
4449 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4450 I915_WRITE(WM0_PIPEA_ILK,
4451 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4452 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4453 " plane %d, " "cursor: %d\n",
4454 plane_wm, cursor_wm);
d210246a 4455 enabled |= 1;
b79d4990
JB		 4456 }
4457
9f405100
CW		 4458 if (g4x_compute_wm0(dev, 1,
4459 &ironlake_display_wm_info,
4460 ILK_LP0_PLANE_LATENCY,
4461 &ironlake_cursor_wm_info,
4462 ILK_LP0_CURSOR_LATENCY,
4463 &plane_wm, &cursor_wm)) {
b79d4990
JB		 4464 I915_WRITE(WM0_PIPEB_ILK,
4465 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4466 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4467 " plane %d, cursor: %d\n",
4468 plane_wm, cursor_wm);
d210246a 4469 enabled |= 2;
b79d4990
JB		 4470 }
4471
4472 /*
4473 * Calculate and update the self-refresh watermark only when one
4474 * display plane is used.
4475 */
4476 I915_WRITE(WM3_LP_ILK, 0);
4477 I915_WRITE(WM2_LP_ILK, 0);
4478 I915_WRITE(WM1_LP_ILK, 0);
4479
d210246a 4480 if (!single_plane_enabled(enabled))
b79d4990 4481 return;
d210246a 4482 enabled = ffs(enabled) - 1;
b79d4990
JB		 4483
4484 /* WM1 */
d210246a
CW		 4485 if (!ironlake_compute_srwm(dev, 1, enabled,
4486 ILK_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4487 &ironlake_display_srwm_info,
4488 &ironlake_cursor_srwm_info,
4489 &fbc_wm, &plane_wm, &cursor_wm))
4490 return;
4491
4492 I915_WRITE(WM1_LP_ILK,
4493 WM1_LP_SR_EN |
4494 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4495 (fbc_wm << WM1_LP_FBC_SHIFT) |
4496 (plane_wm << WM1_LP_SR_SHIFT) |
4497 cursor_wm);
4498
4499 /* WM2 */
d210246a
CW		 4500 if (!ironlake_compute_srwm(dev, 2, enabled,
4501 ILK_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4502 &ironlake_display_srwm_info,
4503 &ironlake_cursor_srwm_info,
4504 &fbc_wm, &plane_wm, &cursor_wm))
4505 return;
4506
4507 I915_WRITE(WM2_LP_ILK,
4508 WM2_LP_EN |
4509 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4510 (fbc_wm << WM1_LP_FBC_SHIFT) |
4511 (plane_wm << WM1_LP_SR_SHIFT) |
4512 cursor_wm);
4513
4514 /*
4515 * WM3 is unsupported on ILK, probably because we don't have latency
4516 * data for that power state
4517 */
1398261a
YL		 4518}
4519
b840d907 4520void sandybridge_update_wm(struct drm_device *dev)
1398261a
YL		 4521{
4522 struct drm_i915_private *dev_priv = dev->dev_private;
a0fa62d3 4523 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
d210246a
CW		 4524 int fbc_wm, plane_wm, cursor_wm;
4525 unsigned int enabled;
1398261a
YL		 4526
4527 enabled = 0;
9f405100
CW		 4528 if (g4x_compute_wm0(dev, 0,
4529 &sandybridge_display_wm_info, latency,
4530 &sandybridge_cursor_wm_info, latency,
4531 &plane_wm, &cursor_wm)) {
1398261a
YL		 4532 I915_WRITE(WM0_PIPEA_ILK,
4533 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4534 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
4535 " plane %d, " "cursor: %d\n",
4536 plane_wm, cursor_wm);
d210246a 4537 enabled |= 1;
1398261a
YL		 4538 }
4539
9f405100
CW		 4540 if (g4x_compute_wm0(dev, 1,
4541 &sandybridge_display_wm_info, latency,
4542 &sandybridge_cursor_wm_info, latency,
4543 &plane_wm, &cursor_wm)) {
1398261a
YL		 4544 I915_WRITE(WM0_PIPEB_ILK,
4545 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4546 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
4547 " plane %d, cursor: %d\n",
4548 plane_wm, cursor_wm);
d210246a 4549 enabled |= 2;
1398261a
YL		 4550 }
4551
d6c892df
JB		 4552 /* IVB has 3 pipes */
4553 if (IS_IVYBRIDGE(dev) &&
4554 g4x_compute_wm0(dev, 2,
4555 &sandybridge_display_wm_info, latency,
4556 &sandybridge_cursor_wm_info, latency,
4557 &plane_wm, &cursor_wm)) {
4558 I915_WRITE(WM0_PIPEC_IVB,
4559 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
4560 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
4561 " plane %d, cursor: %d\n",
4562 plane_wm, cursor_wm);
4563 enabled |= 3;
4564 }
4565
1398261a
YL		 4566 /*
4567 * Calculate and update the self-refresh watermark only when one
4568 * display plane is used.
4569 *
4570 * SNB support 3 levels of watermark.
4571 *
4572 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
4573 * and disabled in the descending order
4574 *
4575 */
4576 I915_WRITE(WM3_LP_ILK, 0);
4577 I915_WRITE(WM2_LP_ILK, 0);
4578 I915_WRITE(WM1_LP_ILK, 0);
4579
b840d907
JB		 4580 if (!single_plane_enabled(enabled) ||
4581 dev_priv->sprite_scaling_enabled)
1398261a 4582 return;
d210246a 4583 enabled = ffs(enabled) - 1;
1398261a
YL		 4584
4585 /* WM1 */
d210246a
CW		 4586 if (!ironlake_compute_srwm(dev, 1, enabled,
4587 SNB_READ_WM1_LATENCY() * 500,
b79d4990
JB		 4588 &sandybridge_display_srwm_info,
4589 &sandybridge_cursor_srwm_info,
4590 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4591 return;
4592
4593 I915_WRITE(WM1_LP_ILK,
4594 WM1_LP_SR_EN |
4595 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4596 (fbc_wm << WM1_LP_FBC_SHIFT) |
4597 (plane_wm << WM1_LP_SR_SHIFT) |
4598 cursor_wm);
4599
4600 /* WM2 */
d210246a
CW		 4601 if (!ironlake_compute_srwm(dev, 2, enabled,
4602 SNB_READ_WM2_LATENCY() * 500,
b79d4990
JB		 4603 &sandybridge_display_srwm_info,
4604 &sandybridge_cursor_srwm_info,
4605 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4606 return;
4607
4608 I915_WRITE(WM2_LP_ILK,
4609 WM2_LP_EN |
4610 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4611 (fbc_wm << WM1_LP_FBC_SHIFT) |
4612 (plane_wm << WM1_LP_SR_SHIFT) |
4613 cursor_wm);
4614
4615 /* WM3 */
d210246a
CW		 4616 if (!ironlake_compute_srwm(dev, 3, enabled,
4617 SNB_READ_WM3_LATENCY() * 500,
b79d4990
JB		 4618 &sandybridge_display_srwm_info,
4619 &sandybridge_cursor_srwm_info,
4620 &fbc_wm, &plane_wm, &cursor_wm))
1398261a
YL		 4621 return;
4622
4623 I915_WRITE(WM3_LP_ILK,
4624 WM3_LP_EN |
4625 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
4626 (fbc_wm << WM1_LP_FBC_SHIFT) |
4627 (plane_wm << WM1_LP_SR_SHIFT) |
4628 cursor_wm);
4629}
4630
b840d907
JB		 4631static bool
4632sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
4633 uint32_t sprite_width, int pixel_size,
4634 const struct intel_watermark_params *display,
4635 int display_latency_ns, int *sprite_wm)
4636{
4637 struct drm_crtc *crtc;
4638 int clock;
4639 int entries, tlb_miss;
4640
4641 crtc = intel_get_crtc_for_plane(dev, plane);
4642 if (crtc->fb == NULL || !crtc->enabled) {
4643 *sprite_wm = display->guard_size;
4644 return false;
4645 }
4646
4647 clock = crtc->mode.clock;
4648
4649 /* Use the small buffer method to calculate the sprite watermark */
4650 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
4651 tlb_miss = display->fifo_size*display->cacheline_size -
4652 sprite_width * 8;
4653 if (tlb_miss > 0)
4654 entries += tlb_miss;
4655 entries = DIV_ROUND_UP(entries, display->cacheline_size);
4656 *sprite_wm = entries + display->guard_size;
4657 if (*sprite_wm > (int)display->max_wm)
4658 *sprite_wm = display->max_wm;
4659
4660 return true;
4661}
4662
4663static bool
4664sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
4665 uint32_t sprite_width, int pixel_size,
4666 const struct intel_watermark_params *display,
4667 int latency_ns, int *sprite_wm)
4668{
4669 struct drm_crtc *crtc;
4670 unsigned long line_time_us;
4671 int clock;
4672 int line_count, line_size;
4673 int small, large;
4674 int entries;
4675
4676 if (!latency_ns) {
4677 *sprite_wm = 0;
4678 return false;
4679 }
4680
4681 crtc = intel_get_crtc_for_plane(dev, plane);
4682 clock = crtc->mode.clock;
4683
4684 line_time_us = (sprite_width * 1000) / clock;
4685 line_count = (latency_ns / line_time_us + 1000) / 1000;
4686 line_size = sprite_width * pixel_size;
4687
4688 /* Use the minimum of the small and large buffer method for primary */
4689 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
4690 large = line_count * line_size;
4691
4692 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
4693 *sprite_wm = entries + display->guard_size;
4694
4695 return *sprite_wm > 0x3ff ? false : true;
4696}
4697
4698static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4699 uint32_t sprite_width, int pixel_size)
4700{
4701 struct drm_i915_private *dev_priv = dev->dev_private;
4702 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
4703 int sprite_wm, reg;
4704 int ret;
4705
4706 switch (pipe) {
4707 case 0:
4708 reg = WM0_PIPEA_ILK;
4709 break;
4710 case 1:
4711 reg = WM0_PIPEB_ILK;
4712 break;
4713 case 2:
4714 reg = WM0_PIPEC_IVB;
4715 break;
4716 default:
4717 return; /* bad pipe */
4718 }
4719
4720 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
4721 &sandybridge_display_wm_info,
4722 latency, &sprite_wm);
4723 if (!ret) {
4724 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
4725 pipe);
4726 return;
4727 }
4728
4729 I915_WRITE(reg, I915_READ(reg) | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
4730 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
4731
4732
4733 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4734 pixel_size,
4735 &sandybridge_display_srwm_info,
4736 SNB_READ_WM1_LATENCY() * 500,
4737 &sprite_wm);
4738 if (!ret) {
4739 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
4740 pipe);
4741 return;
4742 }
4743 I915_WRITE(WM1S_LP_ILK, sprite_wm);
4744
4745 /* Only IVB has two more LP watermarks for sprite */
4746 if (!IS_IVYBRIDGE(dev))
4747 return;
4748
4749 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4750 pixel_size,
4751 &sandybridge_display_srwm_info,
4752 SNB_READ_WM2_LATENCY() * 500,
4753 &sprite_wm);
4754 if (!ret) {
4755 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
4756 pipe);
4757 return;
4758 }
4759 I915_WRITE(WM2S_LP_IVB, sprite_wm);
4760
4761 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
4762 pixel_size,
4763 &sandybridge_display_srwm_info,
4764 SNB_READ_WM3_LATENCY() * 500,
4765 &sprite_wm);
4766 if (!ret) {
4767 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
4768 pipe);
4769 return;
4770 }
4771 I915_WRITE(WM3S_LP_IVB, sprite_wm);
4772}
4773
7662c8bd
SL		 4774/**
4775 * intel_update_watermarks - update FIFO watermark values based on current modes
4776 *
4777 * Calculate watermark values for the various WM regs based on current mode
4778 * and plane configuration.
4779 *
4780 * There are several cases to deal with here:
4781 * - normal (i.e. non-self-refresh)
4782 * - self-refresh (SR) mode
4783 * - lines are large relative to FIFO size (buffer can hold up to 2)
4784 * - lines are small relative to FIFO size (buffer can hold more than 2
4785 * lines), so need to account for TLB latency
4786 *
4787 * The normal calculation is:
4788 * watermark = dotclock * bytes per pixel * latency
4789 * where latency is platform & configuration dependent (we assume pessimal
4790 * values here).
4791 *
4792 * The SR calculation is:
4793 * watermark = (trunc(latency/line time)+1) * surface width *
4794 * bytes per pixel
4795 * where
4796 * line time = htotal / dotclock
fa143215 4797 * surface width = hdisplay for normal plane and 64 for cursor
7662c8bd
SL		 4798 * and latency is assumed to be high, as above.
4799 *
4800 * The final value programmed to the register should always be rounded up,
4801 * and include an extra 2 entries to account for clock crossings.
4802 *
4803 * We don't use the sprite, so we can ignore that. And on Crestline we have
4804 * to set the non-SR watermarks to 8.
5eddb70b 4805 */
7662c8bd
SL		 4806static void intel_update_watermarks(struct drm_device *dev)
4807{
e70236a8 4808 struct drm_i915_private *dev_priv = dev->dev_private;
7662c8bd 4809
d210246a
CW		 4810 if (dev_priv->display.update_wm)
4811 dev_priv->display.update_wm(dev);
7662c8bd
SL		 4812}
4813
b840d907
JB		 4814void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4815 uint32_t sprite_width, int pixel_size)
4816{
4817 struct drm_i915_private *dev_priv = dev->dev_private;
4818
4819 if (dev_priv->display.update_sprite_wm)
4820 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4821 pixel_size);
4822}
4823
a7615030
CW		 4824static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4825{
72bbe58c
KP		 4826 if (i915_panel_use_ssc >= 0)
4827 return i915_panel_use_ssc != 0;
4828 return dev_priv->lvds_use_ssc
435793df 4829 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
a7615030
CW		 4830}
4831
5a354204
JB		 4832/**
4833 * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4834 * @crtc: CRTC structure
3b5c78a3 4835 * @mode: requested mode
5a354204
JB		 4836 *
4837 * A pipe may be connected to one or more outputs. Based on the depth of the
4838 * attached framebuffer, choose a good color depth to use on the pipe.
4839 *
4840 * If possible, match the pipe depth to the fb depth. In some cases, this
4841 * isn't ideal, because the connected output supports a lesser or restricted
4842 * set of depths. Resolve that here:
4843 * LVDS typically supports only 6bpc, so clamp down in that case
4844 * HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4845 * Displays may support a restricted set as well, check EDID and clamp as
4846 * appropriate.
3b5c78a3 4847 * DP may want to dither down to 6bpc to fit larger modes
5a354204
JB		 4848 *
4849 * RETURNS:
4850 * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4851 * true if they don't match).
4852 */
4853static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
3b5c78a3
AJ		 4854 unsigned int *pipe_bpp,
4855 struct drm_display_mode *mode)
5a354204
JB		 4856{
4857 struct drm_device *dev = crtc->dev;
4858 struct drm_i915_private *dev_priv = dev->dev_private;
4859 struct drm_encoder *encoder;
4860 struct drm_connector *connector;
4861 unsigned int display_bpc = UINT_MAX, bpc;
4862
4863 /* Walk the encoders & connectors on this crtc, get min bpc */
4864 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
4865 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
4866
4867 if (encoder->crtc != crtc)
4868 continue;
4869
4870 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4871 unsigned int lvds_bpc;
4872
4873 if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4874 LVDS_A3_POWER_UP)
4875 lvds_bpc = 8;
4876 else
4877 lvds_bpc = 6;
4878
4879 if (lvds_bpc < display_bpc) {
82820490 4880 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
5a354204
JB		 4881 display_bpc = lvds_bpc;
4882 }
4883 continue;
4884 }
4885
4886 if (intel_encoder->type == INTEL_OUTPUT_EDP) {
4887 /* Use VBT settings if we have an eDP panel */
4888 unsigned int edp_bpc = dev_priv->edp.bpp / 3;
4889
4890 if (edp_bpc < display_bpc) {
82820490 4891 DRM_DEBUG_KMS("clamping display bpc (was %d) to eDP (%d)\n", display_bpc, edp_bpc);
5a354204
JB		 4892 display_bpc = edp_bpc;
4893 }
4894 continue;
4895 }
4896
4897 /* Not one of the known troublemakers, check the EDID */
4898 list_for_each_entry(connector, &dev->mode_config.connector_list,
4899 head) {
4900 if (connector->encoder != encoder)
4901 continue;
4902
62ac41a6
JB		 4903 /* Don't use an invalid EDID bpc value */
4904 if (connector->display_info.bpc &&
4905 connector->display_info.bpc < display_bpc) {
82820490 4906 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
5a354204
JB		 4907 display_bpc = connector->display_info.bpc;
4908 }
4909 }
4910
4911 /*
4912 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4913 * through, clamp it down. (Note: >12bpc will be caught below.)
4914 */
4915 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4916 if (display_bpc > 8 && display_bpc < 12) {
82820490 4917 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
5a354204
JB		 4918 display_bpc = 12;
4919 } else {
82820490 4920 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
5a354204
JB		 4921 display_bpc = 8;
4922 }
4923 }
4924 }
4925
3b5c78a3
AJ		 4926 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4927 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4928 display_bpc = 6;
4929 }
4930
5a354204
JB		 4931 /*
4932 * We could just drive the pipe at the highest bpc all the time and
4933 * enable dithering as needed, but that costs bandwidth. So choose
4934 * the minimum value that expresses the full color range of the fb but
4935 * also stays within the max display bpc discovered above.
4936 */
4937
4938 switch (crtc->fb->depth) {
4939 case 8:
4940 bpc = 8; /* since we go through a colormap */
4941 break;
4942 case 15:
4943 case 16:
4944 bpc = 6; /* min is 18bpp */
4945 break;
4946 case 24:
578393cd 4947 bpc = 8;
5a354204
JB		 4948 break;
4949 case 30:
578393cd 4950 bpc = 10;
5a354204
JB		 4951 break;
4952 case 48:
578393cd 4953 bpc = 12;
5a354204
JB		 4954 break;
4955 default:
4956 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4957 bpc = min((unsigned int)8, display_bpc);
4958 break;
4959 }
4960
578393cd
KP		 4961 display_bpc = min(display_bpc, bpc);
4962
82820490
AJ		 4963 DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4964 bpc, display_bpc);
5a354204 4965
578393cd 4966 *pipe_bpp = display_bpc * 3;
5a354204
JB		 4967
4968 return display_bpc != bpc;
4969}
4970
f564048e
EA		 4971static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4972 struct drm_display_mode *mode,
4973 struct drm_display_mode *adjusted_mode,
4974 int x, int y,
4975 struct drm_framebuffer *old_fb)
79e53945
JB		 4976{
4977 struct drm_device *dev = crtc->dev;
4978 struct drm_i915_private *dev_priv = dev->dev_private;
4979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4980 int pipe = intel_crtc->pipe;
80824003 4981 int plane = intel_crtc->plane;
c751ce4f 4982 int refclk, num_connectors = 0;
652c393a 4983 intel_clock_t clock, reduced_clock;
5eddb70b 4984 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
652c393a 4985 bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
a4fc5ed6 4986 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
79e53945 4987 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 4988 struct intel_encoder *encoder;
d4906093 4989 const intel_limit_t *limit;
5c3b82e2 4990 int ret;
fae14981 4991 u32 temp;
aa9b500d 4992 u32 lvds_sync = 0;
79e53945 4993
5eddb70b
CW		 4994 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
4995 if (encoder->base.crtc != crtc)
79e53945
JB		 4996 continue;
4997
5eddb70b 4998 switch (encoder->type) {
79e53945
JB		 4999 case INTEL_OUTPUT_LVDS:
5000 is_lvds = true;
5001 break;
5002 case INTEL_OUTPUT_SDVO:
7d57382e 5003 case INTEL_OUTPUT_HDMI:
79e53945 5004 is_sdvo = true;
5eddb70b 5005 if (encoder->needs_tv_clock)
e2f0ba97 5006 is_tv = true;
79e53945
JB		 5007 break;
5008 case INTEL_OUTPUT_DVO:
5009 is_dvo = true;
5010 break;
5011 case INTEL_OUTPUT_TVOUT:
5012 is_tv = true;
5013 break;
5014 case INTEL_OUTPUT_ANALOG:
5015 is_crt = true;
5016 break;
a4fc5ed6
KP		 5017 case INTEL_OUTPUT_DISPLAYPORT:
5018 is_dp = true;
5019 break;
79e53945 5020 }
43565a06 5021
c751ce4f 5022 num_connectors++;
79e53945
JB		 5023 }
5024
a7615030 5025 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
43565a06 5026 refclk = dev_priv->lvds_ssc_freq * 1000;
28c97730 5027 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5eddb70b 5028 refclk / 1000);
a6c45cf0 5029 } else if (!IS_GEN2(dev)) {
79e53945
JB		 5030 refclk = 96000;
5031 } else {
5032 refclk = 48000;
5033 }
5034
d4906093
ML		 5035 /*
5036 * Returns a set of divisors for the desired target clock with the given
5037 * refclk, or FALSE. The returned values represent the clock equation:
5038 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5039 */
1b894b59 5040 limit = intel_limit(crtc, refclk);
d4906093 5041 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 5042 if (!ok) {
5043 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 5044 return -EINVAL;
79e53945
JB		 5045 }
5046
cda4b7d3 5047 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 5048 intel_crtc_update_cursor(crtc, true);
cda4b7d3 5049
ddc9003c
ZY		 5050 if (is_lvds && dev_priv->lvds_downclock_avail) {
5051 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 5052 dev_priv->lvds_downclock,
5053 refclk,
5054 &reduced_clock);
18f9ed12
ZY		 5055 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5056 /*
5057 * If the different P is found, it means that we can't
5058 * switch the display clock by using the FP0/FP1.
5059 * In such case we will disable the LVDS downclock
5060 * feature.
5061 */
5062 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 5063 "LVDS clock/downclock\n");
18f9ed12
ZY		 5064 has_reduced_clock = 0;
5065 }
652c393a 5066 }
7026d4ac
ZW		 5067 /* SDVO TV has fixed PLL values depend on its clock range,
5068 this mirrors vbios setting. */
5069 if (is_sdvo && is_tv) {
5070 if (adjusted_mode->clock >= 100000
5eddb70b 5071 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 5072 clock.p1 = 2;
5073 clock.p2 = 10;
5074 clock.n = 3;
5075 clock.m1 = 16;
5076 clock.m2 = 8;
5077 } else if (adjusted_mode->clock >= 140500
5eddb70b 5078 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 5079 clock.p1 = 1;
5080 clock.p2 = 10;
5081 clock.n = 6;
5082 clock.m1 = 12;
5083 clock.m2 = 8;
5084 }
5085 }
5086
f2b115e6 5087 if (IS_PINEVIEW(dev)) {
2177832f 5088 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 5089 if (has_reduced_clock)
5090 fp2 = (1 << reduced_clock.n) << 16 |
5091 reduced_clock.m1 << 8 | reduced_clock.m2;
5092 } else {
2177832f 5093 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
652c393a
JB		 5094 if (has_reduced_clock)
5095 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5096 reduced_clock.m2;
5097 }
79e53945 5098
929c77fb 5099 dpll = DPLL_VGA_MODE_DIS;
2c07245f 5100
a6c45cf0 5101 if (!IS_GEN2(dev)) {
79e53945
JB		 5102 if (is_lvds)
5103 dpll |= DPLLB_MODE_LVDS;
5104 else
5105 dpll |= DPLLB_MODE_DAC_SERIAL;
5106 if (is_sdvo) {
6c9547ff
CW		 5107 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5108 if (pixel_multiplier > 1) {
5109 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
5110 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
6c9547ff 5111 }
79e53945 5112 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5113 }
929c77fb 5114 if (is_dp)
a4fc5ed6 5115 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945
JB		 5116
5117 /* compute bitmask from p1 value */
f2b115e6
AJ		 5118 if (IS_PINEVIEW(dev))
5119 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
2c07245f 5120 else {
2177832f 5121 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
652c393a
JB		 5122 if (IS_G4X(dev) && has_reduced_clock)
5123 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
2c07245f 5124 }
79e53945
JB		 5125 switch (clock.p2) {
5126 case 5:
5127 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5128 break;
5129 case 7:
5130 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5131 break;
5132 case 10:
5133 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5134 break;
5135 case 14:
5136 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5137 break;
5138 }
929c77fb 5139 if (INTEL_INFO(dev)->gen >= 4)
79e53945
JB		 5140 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
5141 } else {
5142 if (is_lvds) {
5143 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5144 } else {
5145 if (clock.p1 == 2)
5146 dpll |= PLL_P1_DIVIDE_BY_TWO;
5147 else
5148 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5149 if (clock.p2 == 4)
5150 dpll |= PLL_P2_DIVIDE_BY_4;
5151 }
5152 }
5153
43565a06
KH		 5154 if (is_sdvo && is_tv)
5155 dpll |= PLL_REF_INPUT_TVCLKINBC;
5156 else if (is_tv)
79e53945 5157 /* XXX: just matching BIOS for now */
43565a06 5158 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5159 dpll |= 3;
a7615030 5160 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5161 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5162 else
5163 dpll |= PLL_REF_INPUT_DREFCLK;
5164
5165 /* setup pipeconf */
5eddb70b 5166 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5167
5168 /* Set up the display plane register */
5169 dspcntr = DISPPLANE_GAMMA_ENABLE;
5170
f2b115e6 5171 /* Ironlake's plane is forced to pipe, bit 24 is to
2c07245f 5172 enable color space conversion */
929c77fb
EA		 5173 if (pipe == 0)
5174 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
5175 else
5176 dspcntr |= DISPPLANE_SEL_PIPE_B;
79e53945 5177
a6c45cf0 5178 if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
79e53945
JB		 5179 /* Enable pixel doubling when the dot clock is > 90% of the (display)
5180 * core speed.
5181 *
5182 * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
5183 * pipe == 0 check?
5184 */
e70236a8
JB		 5185 if (mode->clock >
5186 dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
5eddb70b 5187 pipeconf |= PIPECONF_DOUBLE_WIDE;
79e53945 5188 else
5eddb70b 5189 pipeconf &= ~PIPECONF_DOUBLE_WIDE;
79e53945
JB		 5190 }
5191
3b5c78a3
AJ		 5192 /* default to 8bpc */
5193 pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
5194 if (is_dp) {
5195 if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
5196 pipeconf |= PIPECONF_BPP_6 |
5197 PIPECONF_DITHER_EN |
5198 PIPECONF_DITHER_TYPE_SP;
5199 }
5200 }
5201
929c77fb 5202 dpll |= DPLL_VCO_ENABLE;
8d86dc6a 5203
28c97730 5204 DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
79e53945
JB		 5205 drm_mode_debug_printmodeline(mode);
5206
fae14981
EA		 5207 I915_WRITE(FP0(pipe), fp);
5208 I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5eddb70b 5209
fae14981 5210 POSTING_READ(DPLL(pipe));
c713bb08 5211 udelay(150);
8db9d77b 5212
79e53945
JB		 5213 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5214 * This is an exception to the general rule that mode_set doesn't turn
5215 * things on.
5216 */
5217 if (is_lvds) {
fae14981 5218 temp = I915_READ(LVDS);
5eddb70b 5219 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
b3b095b3 5220 if (pipe == 1) {
929c77fb 5221 temp |= LVDS_PIPEB_SELECT;
b3b095b3 5222 } else {
929c77fb 5223 temp &= ~LVDS_PIPEB_SELECT;
b3b095b3 5224 }
a3e17eb8 5225 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5226 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5227 /* Set the B0-B3 data pairs corresponding to whether we're going to
5228 * set the DPLLs for dual-channel mode or not.
5229 */
5230 if (clock.p2 == 7)
5eddb70b 5231 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5232 else
5eddb70b 5233 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5234
5235 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5236 * appropriately here, but we need to look more thoroughly into how
5237 * panels behave in the two modes.
5238 */
929c77fb
EA		 5239 /* set the dithering flag on LVDS as needed */
5240 if (INTEL_INFO(dev)->gen >= 4) {
434ed097 5241 if (dev_priv->lvds_dither)
5eddb70b 5242 temp |= LVDS_ENABLE_DITHER;
434ed097 5243 else
5eddb70b 5244 temp &= ~LVDS_ENABLE_DITHER;
898822ce 5245 }
aa9b500d
BF		 5246 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5247 lvds_sync |= LVDS_HSYNC_POLARITY;
5248 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5249 lvds_sync |= LVDS_VSYNC_POLARITY;
5250 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5251 != lvds_sync) {
5252 char flags[2] = "-+";
5253 DRM_INFO("Changing LVDS panel from "
5254 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5255 flags[!(temp & LVDS_HSYNC_POLARITY)],
5256 flags[!(temp & LVDS_VSYNC_POLARITY)],
5257 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5258 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5259 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5260 temp |= lvds_sync;
5261 }
fae14981 5262 I915_WRITE(LVDS, temp);
79e53945 5263 }
434ed097 5264
929c77fb 5265 if (is_dp) {
a4fc5ed6 5266 intel_dp_set_m_n(crtc, mode, adjusted_mode);
434ed097
JB		 5267 }
5268
fae14981 5269 I915_WRITE(DPLL(pipe), dpll);
5eddb70b 5270
c713bb08 5271 /* Wait for the clocks to stabilize. */
fae14981 5272 POSTING_READ(DPLL(pipe));
c713bb08 5273 udelay(150);
32f9d658 5274
c713bb08
EA		 5275 if (INTEL_INFO(dev)->gen >= 4) {
5276 temp = 0;
5277 if (is_sdvo) {
5278 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
5279 if (temp > 1)
5280 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
5281 else
5282 temp = 0;
32f9d658 5283 }
c713bb08
EA		 5284 I915_WRITE(DPLL_MD(pipe), temp);
5285 } else {
5286 /* The pixel multiplier can only be updated once the
5287 * DPLL is enabled and the clocks are stable.
5288 *
5289 * So write it again.
5290 */
fae14981 5291 I915_WRITE(DPLL(pipe), dpll);
79e53945 5292 }
79e53945 5293
5eddb70b 5294 intel_crtc->lowfreq_avail = false;
652c393a 5295 if (is_lvds && has_reduced_clock && i915_powersave) {
fae14981 5296 I915_WRITE(FP1(pipe), fp2);
652c393a
JB		 5297 intel_crtc->lowfreq_avail = true;
5298 if (HAS_PIPE_CXSR(dev)) {
28c97730 5299 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
652c393a
JB		 5300 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5301 }
5302 } else {
fae14981 5303 I915_WRITE(FP1(pipe), fp);
652c393a 5304 if (HAS_PIPE_CXSR(dev)) {
28c97730 5305 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
652c393a
JB		 5306 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5307 }
5308 }
5309
734b4157
KH		 5310 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5311 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5312 /* the chip adds 2 halflines automatically */
5313 adjusted_mode->crtc_vdisplay -= 1;
5314 adjusted_mode->crtc_vtotal -= 1;
5315 adjusted_mode->crtc_vblank_start -= 1;
5316 adjusted_mode->crtc_vblank_end -= 1;
5317 adjusted_mode->crtc_vsync_end -= 1;
5318 adjusted_mode->crtc_vsync_start -= 1;
5319 } else
59df7b17 5320 pipeconf &= ~PIPECONF_INTERLACE_MASK; /* progressive */
734b4157 5321
5eddb70b
CW		 5322 I915_WRITE(HTOTAL(pipe),
5323 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5324 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5325 I915_WRITE(HBLANK(pipe),
5326 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5327 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5328 I915_WRITE(HSYNC(pipe),
5329 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5330 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5331
5332 I915_WRITE(VTOTAL(pipe),
5333 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5334 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5335 I915_WRITE(VBLANK(pipe),
5336 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5337 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5338 I915_WRITE(VSYNC(pipe),
5339 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5340 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b
CW		 5341
5342 /* pipesrc and dspsize control the size that is scaled from,
5343 * which should always be the user's requested size.
79e53945 5344 */
929c77fb
EA		 5345 I915_WRITE(DSPSIZE(plane),
5346 ((mode->vdisplay - 1) << 16) |
5347 (mode->hdisplay - 1));
5348 I915_WRITE(DSPPOS(plane), 0);
5eddb70b
CW		 5349 I915_WRITE(PIPESRC(pipe),
5350 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5351
f564048e
EA		 5352 I915_WRITE(PIPECONF(pipe), pipeconf);
5353 POSTING_READ(PIPECONF(pipe));
929c77fb 5354 intel_enable_pipe(dev_priv, pipe, false);
f564048e
EA		 5355
5356 intel_wait_for_vblank(dev, pipe);
5357
f564048e
EA		 5358 I915_WRITE(DSPCNTR(plane), dspcntr);
5359 POSTING_READ(DSPCNTR(plane));
284d9529 5360 intel_enable_plane(dev_priv, plane, pipe);
f564048e
EA		 5361
5362 ret = intel_pipe_set_base(crtc, x, y, old_fb);
5363
5364 intel_update_watermarks(dev);
5365
f564048e
EA		 5366 return ret;
5367}
5368
9fb526db
KP		 5369/*
5370 * Initialize reference clocks when the driver loads
5371 */
5372void ironlake_init_pch_refclk(struct drm_device *dev)
13d83a67
JB		 5373{
5374 struct drm_i915_private *dev_priv = dev->dev_private;
5375 struct drm_mode_config *mode_config = &dev->mode_config;
13d83a67 5376 struct intel_encoder *encoder;
13d83a67
JB		 5377 u32 temp;
5378 bool has_lvds = false;
199e5d79
KP		 5379 bool has_cpu_edp = false;
5380 bool has_pch_edp = false;
5381 bool has_panel = false;
99eb6a01
KP		 5382 bool has_ck505 = false;
5383 bool can_ssc = false;
13d83a67
JB		 5384
5385 /* We need to take the global config into account */
199e5d79
KP		 5386 list_for_each_entry(encoder, &mode_config->encoder_list,
5387 base.head) {
5388 switch (encoder->type) {
5389 case INTEL_OUTPUT_LVDS:
5390 has_panel = true;
5391 has_lvds = true;
5392 break;
5393 case INTEL_OUTPUT_EDP:
5394 has_panel = true;
5395 if (intel_encoder_is_pch_edp(&encoder->base))
5396 has_pch_edp = true;
5397 else
5398 has_cpu_edp = true;
5399 break;
13d83a67
JB		 5400 }
5401 }
5402
99eb6a01
KP		 5403 if (HAS_PCH_IBX(dev)) {
5404 has_ck505 = dev_priv->display_clock_mode;
5405 can_ssc = has_ck505;
5406 } else {
5407 has_ck505 = false;
5408 can_ssc = true;
5409 }
5410
5411 DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
5412 has_panel, has_lvds, has_pch_edp, has_cpu_edp,
5413 has_ck505);
13d83a67
JB		 5414
5415 /* Ironlake: try to setup display ref clock before DPLL
5416 * enabling. This is only under driver's control after
5417 * PCH B stepping, previous chipset stepping should be
5418 * ignoring this setting.
5419 */
5420 temp = I915_READ(PCH_DREF_CONTROL);
5421 /* Always enable nonspread source */
5422 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
13d83a67 5423
99eb6a01
KP		 5424 if (has_ck505)
5425 temp |= DREF_NONSPREAD_CK505_ENABLE;
5426 else
5427 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
13d83a67 5428
199e5d79
KP		 5429 if (has_panel) {
5430 temp &= ~DREF_SSC_SOURCE_MASK;
5431 temp |= DREF_SSC_SOURCE_ENABLE;
13d83a67 5432
199e5d79 5433 /* SSC must be turned on before enabling the CPU output */
99eb6a01 5434 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5435 DRM_DEBUG_KMS("Using SSC on panel\n");
13d83a67 5436 temp |= DREF_SSC1_ENABLE;
13d83a67 5437 }
199e5d79
KP		 5438
5439 /* Get SSC going before enabling the outputs */
5440 I915_WRITE(PCH_DREF_CONTROL, temp);
5441 POSTING_READ(PCH_DREF_CONTROL);
5442 udelay(200);
5443
13d83a67
JB		 5444 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5445
5446 /* Enable CPU source on CPU attached eDP */
199e5d79 5447 if (has_cpu_edp) {
99eb6a01 5448 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
199e5d79 5449 DRM_DEBUG_KMS("Using SSC on eDP\n");
13d83a67 5450 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
199e5d79 5451 }
13d83a67
JB		 5452 else
5453 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
199e5d79
KP		 5454 } else
5455 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5456
5457 I915_WRITE(PCH_DREF_CONTROL, temp);
5458 POSTING_READ(PCH_DREF_CONTROL);
5459 udelay(200);
5460 } else {
5461 DRM_DEBUG_KMS("Disabling SSC entirely\n");
5462
5463 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
5464
5465 /* Turn off CPU output */
5466 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
5467
5468 I915_WRITE(PCH_DREF_CONTROL, temp);
5469 POSTING_READ(PCH_DREF_CONTROL);
5470 udelay(200);
5471
5472 /* Turn off the SSC source */
5473 temp &= ~DREF_SSC_SOURCE_MASK;
5474 temp |= DREF_SSC_SOURCE_DISABLE;
5475
5476 /* Turn off SSC1 */
5477 temp &= ~ DREF_SSC1_ENABLE;
5478
13d83a67
JB		 5479 I915_WRITE(PCH_DREF_CONTROL, temp);
5480 POSTING_READ(PCH_DREF_CONTROL);
5481 udelay(200);
5482 }
5483}
5484
d9d444cb
JB		 5485static int ironlake_get_refclk(struct drm_crtc *crtc)
5486{
5487 struct drm_device *dev = crtc->dev;
5488 struct drm_i915_private *dev_priv = dev->dev_private;
5489 struct intel_encoder *encoder;
5490 struct drm_mode_config *mode_config = &dev->mode_config;
5491 struct intel_encoder *edp_encoder = NULL;
5492 int num_connectors = 0;
5493 bool is_lvds = false;
5494
5495 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5496 if (encoder->base.crtc != crtc)
5497 continue;
5498
5499 switch (encoder->type) {
5500 case INTEL_OUTPUT_LVDS:
5501 is_lvds = true;
5502 break;
5503 case INTEL_OUTPUT_EDP:
5504 edp_encoder = encoder;
5505 break;
5506 }
5507 num_connectors++;
5508 }
5509
5510 if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
5511 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
5512 dev_priv->lvds_ssc_freq);
5513 return dev_priv->lvds_ssc_freq * 1000;
5514 }
5515
5516 return 120000;
5517}
5518
f564048e
EA		 5519static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5520 struct drm_display_mode *mode,
5521 struct drm_display_mode *adjusted_mode,
5522 int x, int y,
5523 struct drm_framebuffer *old_fb)
79e53945
JB		 5524{
5525 struct drm_device *dev = crtc->dev;
5526 struct drm_i915_private *dev_priv = dev->dev_private;
5527 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5528 int pipe = intel_crtc->pipe;
80824003 5529 int plane = intel_crtc->plane;
c751ce4f 5530 int refclk, num_connectors = 0;
652c393a 5531 intel_clock_t clock, reduced_clock;
5eddb70b 5532 u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
a07d6787 5533 bool ok, has_reduced_clock = false, is_sdvo = false;
a4fc5ed6 5534 bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
8e647a27 5535 struct intel_encoder *has_edp_encoder = NULL;
79e53945 5536 struct drm_mode_config *mode_config = &dev->mode_config;
5eddb70b 5537 struct intel_encoder *encoder;
d4906093 5538 const intel_limit_t *limit;
5c3b82e2 5539 int ret;
2c07245f 5540 struct fdi_m_n m_n = {0};
fae14981 5541 u32 temp;
aa9b500d 5542 u32 lvds_sync = 0;
5a354204
JB		 5543 int target_clock, pixel_multiplier, lane, link_bw, factor;
5544 unsigned int pipe_bpp;
5545 bool dither;
79e53945 5546
5eddb70b
CW		 5547 list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
5548 if (encoder->base.crtc != crtc)
79e53945
JB		 5549 continue;
5550
5eddb70b 5551 switch (encoder->type) {
79e53945
JB		 5552 case INTEL_OUTPUT_LVDS:
5553 is_lvds = true;
5554 break;
5555 case INTEL_OUTPUT_SDVO:
7d57382e 5556 case INTEL_OUTPUT_HDMI:
79e53945 5557 is_sdvo = true;
5eddb70b 5558 if (encoder->needs_tv_clock)
e2f0ba97 5559 is_tv = true;
79e53945 5560 break;
79e53945
JB		 5561 case INTEL_OUTPUT_TVOUT:
5562 is_tv = true;
5563 break;
5564 case INTEL_OUTPUT_ANALOG:
5565 is_crt = true;
5566 break;
a4fc5ed6
KP		 5567 case INTEL_OUTPUT_DISPLAYPORT:
5568 is_dp = true;
5569 break;
32f9d658 5570 case INTEL_OUTPUT_EDP:
5eddb70b 5571 has_edp_encoder = encoder;
32f9d658 5572 break;
79e53945 5573 }
43565a06 5574
c751ce4f 5575 num_connectors++;
79e53945
JB		 5576 }
5577
d9d444cb 5578 refclk = ironlake_get_refclk(crtc);
79e53945 5579
d4906093
ML		 5580 /*
5581 * Returns a set of divisors for the desired target clock with the given
5582 * refclk, or FALSE. The returned values represent the clock equation:
5583 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5584 */
1b894b59 5585 limit = intel_limit(crtc, refclk);
d4906093 5586 ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
79e53945
JB		 5587 if (!ok) {
5588 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5c3b82e2 5589 return -EINVAL;
79e53945
JB		 5590 }
5591
cda4b7d3 5592 /* Ensure that the cursor is valid for the new mode before changing... */
6b383a7f 5593 intel_crtc_update_cursor(crtc, true);
cda4b7d3 5594
ddc9003c
ZY		 5595 if (is_lvds && dev_priv->lvds_downclock_avail) {
5596 has_reduced_clock = limit->find_pll(limit, crtc,
5eddb70b
CW		 5597 dev_priv->lvds_downclock,
5598 refclk,
5599 &reduced_clock);
18f9ed12
ZY		 5600 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
5601 /*
5602 * If the different P is found, it means that we can't
5603 * switch the display clock by using the FP0/FP1.
5604 * In such case we will disable the LVDS downclock
5605 * feature.
5606 */
5607 DRM_DEBUG_KMS("Different P is found for "
5eddb70b 5608 "LVDS clock/downclock\n");
18f9ed12
ZY		 5609 has_reduced_clock = 0;
5610 }
652c393a 5611 }
7026d4ac
ZW		 5612 /* SDVO TV has fixed PLL values depend on its clock range,
5613 this mirrors vbios setting. */
5614 if (is_sdvo && is_tv) {
5615 if (adjusted_mode->clock >= 100000
5eddb70b 5616 && adjusted_mode->clock < 140500) {
7026d4ac
ZW		 5617 clock.p1 = 2;
5618 clock.p2 = 10;
5619 clock.n = 3;
5620 clock.m1 = 16;
5621 clock.m2 = 8;
5622 } else if (adjusted_mode->clock >= 140500
5eddb70b 5623 && adjusted_mode->clock <= 200000) {
7026d4ac
ZW		 5624 clock.p1 = 1;
5625 clock.p2 = 10;
5626 clock.n = 6;
5627 clock.m1 = 12;
5628 clock.m2 = 8;
5629 }
5630 }
5631
2c07245f 5632 /* FDI link */
8febb297
EA		 5633 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5634 lane = 0;
5635 /* CPU eDP doesn't require FDI link, so just set DP M/N
5636 according to current link config */
5637 if (has_edp_encoder &&
5638 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5639 target_clock = mode->clock;
5640 intel_edp_link_config(has_edp_encoder,
5641 &lane, &link_bw);
5642 } else {
5643 /* [e]DP over FDI requires target mode clock
5644 instead of link clock */
5645 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5eb08b69 5646 target_clock = mode->clock;
8febb297
EA		 5647 else
5648 target_clock = adjusted_mode->clock;
5649
5650 /* FDI is a binary signal running at ~2.7GHz, encoding
5651 * each output octet as 10 bits. The actual frequency
5652 * is stored as a divider into a 100MHz clock, and the
5653 * mode pixel clock is stored in units of 1KHz.
5654 * Hence the bw of each lane in terms of the mode signal
5655 * is:
5656 */
5657 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5658 }
58a27471 5659
8febb297
EA		 5660 /* determine panel color depth */
5661 temp = I915_READ(PIPECONF(pipe));
5662 temp &= ~PIPE_BPC_MASK;
3b5c78a3 5663 dither = intel_choose_pipe_bpp_dither(crtc, &pipe_bpp, mode);
5a354204
JB		 5664 switch (pipe_bpp) {
5665 case 18:
5666 temp |= PIPE_6BPC;
8febb297 5667 break;
5a354204
JB		 5668 case 24:
5669 temp |= PIPE_8BPC;
8febb297 5670 break;
5a354204
JB		 5671 case 30:
5672 temp |= PIPE_10BPC;
8febb297 5673 break;
5a354204
JB		 5674 case 36:
5675 temp |= PIPE_12BPC;
8febb297
EA		 5676 break;
5677 default:
62ac41a6
JB		 5678 WARN(1, "intel_choose_pipe_bpp returned invalid value %d\n",
5679 pipe_bpp);
5a354204
JB		 5680 temp |= PIPE_8BPC;
5681 pipe_bpp = 24;
5682 break;
8febb297 5683 }
77ffb597 5684
5a354204
JB		 5685 intel_crtc->bpp = pipe_bpp;
5686 I915_WRITE(PIPECONF(pipe), temp);
5687
8febb297
EA		 5688 if (!lane) {
5689 /*
5690 * Account for spread spectrum to avoid
5691 * oversubscribing the link. Max center spread
5692 * is 2.5%; use 5% for safety's sake.
5693 */
5a354204 5694 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
8febb297 5695 lane = bps / (link_bw * 8) + 1;
5eb08b69 5696 }
2c07245f 5697
8febb297
EA		 5698 intel_crtc->fdi_lanes = lane;
5699
5700 if (pixel_multiplier > 1)
5701 link_bw *= pixel_multiplier;
5a354204
JB		 5702 ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5703 &m_n);
8febb297 5704
a07d6787
EA		 5705 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5706 if (has_reduced_clock)
5707 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5708 reduced_clock.m2;
79e53945 5709
c1858123 5710 /* Enable autotuning of the PLL clock (if permissible) */
8febb297
EA		 5711 factor = 21;
5712 if (is_lvds) {
5713 if ((intel_panel_use_ssc(dev_priv) &&
5714 dev_priv->lvds_ssc_freq == 100) ||
5715 (I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP)
5716 factor = 25;
5717 } else if (is_sdvo && is_tv)
5718 factor = 20;
c1858123 5719
cb0e0931 5720 if (clock.m < factor * clock.n)
8febb297 5721 fp |= FP_CB_TUNE;
2c07245f 5722
5eddb70b 5723 dpll = 0;
2c07245f 5724
a07d6787
EA		 5725 if (is_lvds)
5726 dpll |= DPLLB_MODE_LVDS;
5727 else
5728 dpll |= DPLLB_MODE_DAC_SERIAL;
5729 if (is_sdvo) {
5730 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5731 if (pixel_multiplier > 1) {
5732 dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
79e53945 5733 }
a07d6787
EA		 5734 dpll |= DPLL_DVO_HIGH_SPEED;
5735 }
5736 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base))
5737 dpll |= DPLL_DVO_HIGH_SPEED;
79e53945 5738
a07d6787
EA		 5739 /* compute bitmask from p1 value */
5740 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5741 /* also FPA1 */
5742 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5743
5744 switch (clock.p2) {
5745 case 5:
5746 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5747 break;
5748 case 7:
5749 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5750 break;
5751 case 10:
5752 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5753 break;
5754 case 14:
5755 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5756 break;
79e53945
JB		 5757 }
5758
43565a06
KH		 5759 if (is_sdvo && is_tv)
5760 dpll |= PLL_REF_INPUT_TVCLKINBC;
5761 else if (is_tv)
79e53945 5762 /* XXX: just matching BIOS for now */
43565a06 5763 /* dpll |= PLL_REF_INPUT_TVCLKINBC; */
79e53945 5764 dpll |= 3;
a7615030 5765 else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
43565a06 5766 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
79e53945
JB		 5767 else
5768 dpll |= PLL_REF_INPUT_DREFCLK;
5769
5770 /* setup pipeconf */
5eddb70b 5771 pipeconf = I915_READ(PIPECONF(pipe));
79e53945
JB		 5772
5773 /* Set up the display plane register */
5774 dspcntr = DISPPLANE_GAMMA_ENABLE;
5775
f7cb34d4 5776 DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
79e53945
JB		 5777 drm_mode_debug_printmodeline(mode);
5778
5c5313c8 5779 /* PCH eDP needs FDI, but CPU eDP does not */
4b645f14
JB		 5780 if (!intel_crtc->no_pll) {
5781 if (!has_edp_encoder ||
5782 intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5783 I915_WRITE(PCH_FP0(pipe), fp);
5784 I915_WRITE(PCH_DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
5785
5786 POSTING_READ(PCH_DPLL(pipe));
5787 udelay(150);
5788 }
5789 } else {
5790 if (dpll == (I915_READ(PCH_DPLL(0)) & 0x7fffffff) &&
5791 fp == I915_READ(PCH_FP0(0))) {
5792 intel_crtc->use_pll_a = true;
5793 DRM_DEBUG_KMS("using pipe a dpll\n");
5794 } else if (dpll == (I915_READ(PCH_DPLL(1)) & 0x7fffffff) &&
5795 fp == I915_READ(PCH_FP0(1))) {
5796 intel_crtc->use_pll_a = false;
5797 DRM_DEBUG_KMS("using pipe b dpll\n");
5798 } else {
5799 DRM_DEBUG_KMS("no matching PLL configuration for pipe 2\n");
5800 return -EINVAL;
5801 }
79e53945
JB		 5802 }
5803
5804 /* The LVDS pin pair needs to be on before the DPLLs are enabled.
5805 * This is an exception to the general rule that mode_set doesn't turn
5806 * things on.
5807 */
5808 if (is_lvds) {
fae14981 5809 temp = I915_READ(PCH_LVDS);
5eddb70b 5810 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
7885d205
JB		 5811 if (HAS_PCH_CPT(dev)) {
5812 temp &= ~PORT_TRANS_SEL_MASK;
4b645f14 5813 temp |= PORT_TRANS_SEL_CPT(pipe);
7885d205
JB		 5814 } else {
5815 if (pipe == 1)
5816 temp |= LVDS_PIPEB_SELECT;
5817 else
5818 temp &= ~LVDS_PIPEB_SELECT;
5819 }
4b645f14 5820
a3e17eb8 5821 /* set the corresponsding LVDS_BORDER bit */
5eddb70b 5822 temp |= dev_priv->lvds_border_bits;
79e53945
JB		 5823 /* Set the B0-B3 data pairs corresponding to whether we're going to
5824 * set the DPLLs for dual-channel mode or not.
5825 */
5826 if (clock.p2 == 7)
5eddb70b 5827 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
79e53945 5828 else
5eddb70b 5829 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
79e53945
JB		 5830
5831 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
5832 * appropriately here, but we need to look more thoroughly into how
5833 * panels behave in the two modes.
5834 */
aa9b500d
BF		 5835 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5836 lvds_sync |= LVDS_HSYNC_POLARITY;
5837 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5838 lvds_sync |= LVDS_VSYNC_POLARITY;
5839 if ((temp & (LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY))
5840 != lvds_sync) {
5841 char flags[2] = "-+";
5842 DRM_INFO("Changing LVDS panel from "
5843 "(%chsync, %cvsync) to (%chsync, %cvsync)\n",
5844 flags[!(temp & LVDS_HSYNC_POLARITY)],
5845 flags[!(temp & LVDS_VSYNC_POLARITY)],
5846 flags[!(lvds_sync & LVDS_HSYNC_POLARITY)],
5847 flags[!(lvds_sync & LVDS_VSYNC_POLARITY)]);
5848 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5849 temp |= lvds_sync;
5850 }
fae14981 5851 I915_WRITE(PCH_LVDS, temp);
79e53945 5852 }
434ed097 5853
8febb297
EA		 5854 pipeconf &= ~PIPECONF_DITHER_EN;
5855 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
5a354204 5856 if ((is_lvds && dev_priv->lvds_dither) || dither) {
8febb297 5857 pipeconf |= PIPECONF_DITHER_EN;
f74974c7 5858 pipeconf |= PIPECONF_DITHER_TYPE_SP;
434ed097 5859 }
5c5313c8 5860 if (is_dp || intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
a4fc5ed6 5861 intel_dp_set_m_n(crtc, mode, adjusted_mode);
8febb297 5862 } else {
8db9d77b 5863 /* For non-DP output, clear any trans DP clock recovery setting.*/
9db4a9c7
JB		 5864 I915_WRITE(TRANSDATA_M1(pipe), 0);
5865 I915_WRITE(TRANSDATA_N1(pipe), 0);
5866 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5867 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
8db9d77b 5868 }
79e53945 5869
4b645f14
JB		 5870 if (!intel_crtc->no_pll &&
5871 (!has_edp_encoder ||
5872 intel_encoder_is_pch_edp(&has_edp_encoder->base))) {
fae14981 5873 I915_WRITE(PCH_DPLL(pipe), dpll);
5eddb70b 5874
32f9d658 5875 /* Wait for the clocks to stabilize. */
fae14981 5876 POSTING_READ(PCH_DPLL(pipe));
32f9d658
ZW		 5877 udelay(150);
5878
8febb297
EA		 5879 /* The pixel multiplier can only be updated once the
5880 * DPLL is enabled and the clocks are stable.
5881 *
5882 * So write it again.
5883 */
fae14981 5884 I915_WRITE(PCH_DPLL(pipe), dpll);
79e53945 5885 }
79e53945 5886
5eddb70b 5887 intel_crtc->lowfreq_avail = false;
4b645f14
JB		 5888 if (!intel_crtc->no_pll) {
5889 if (is_lvds && has_reduced_clock && i915_powersave) {
5890 I915_WRITE(PCH_FP1(pipe), fp2);
5891 intel_crtc->lowfreq_avail = true;
5892 if (HAS_PIPE_CXSR(dev)) {
5893 DRM_DEBUG_KMS("enabling CxSR downclocking\n");
5894 pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
5895 }
5896 } else {
5897 I915_WRITE(PCH_FP1(pipe), fp);
5898 if (HAS_PIPE_CXSR(dev)) {
5899 DRM_DEBUG_KMS("disabling CxSR downclocking\n");
5900 pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
5901 }
652c393a
JB		 5902 }
5903 }
5904
734b4157
KH		 5905 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
5906 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
5907 /* the chip adds 2 halflines automatically */
5908 adjusted_mode->crtc_vdisplay -= 1;
5909 adjusted_mode->crtc_vtotal -= 1;
5910 adjusted_mode->crtc_vblank_start -= 1;
5911 adjusted_mode->crtc_vblank_end -= 1;
5912 adjusted_mode->crtc_vsync_end -= 1;
5913 adjusted_mode->crtc_vsync_start -= 1;
5914 } else
a4ea4308 5915 pipeconf &= ~PIPECONF_INTERLACE_MASK; /* progressive */
734b4157 5916
5eddb70b
CW		 5917 I915_WRITE(HTOTAL(pipe),
5918 (adjusted_mode->crtc_hdisplay - 1) |
79e53945 5919 ((adjusted_mode->crtc_htotal - 1) << 16));
5eddb70b
CW		 5920 I915_WRITE(HBLANK(pipe),
5921 (adjusted_mode->crtc_hblank_start - 1) |
79e53945 5922 ((adjusted_mode->crtc_hblank_end - 1) << 16));
5eddb70b
CW		 5923 I915_WRITE(HSYNC(pipe),
5924 (adjusted_mode->crtc_hsync_start - 1) |
79e53945 5925 ((adjusted_mode->crtc_hsync_end - 1) << 16));
5eddb70b
CW		 5926
5927 I915_WRITE(VTOTAL(pipe),
5928 (adjusted_mode->crtc_vdisplay - 1) |
79e53945 5929 ((adjusted_mode->crtc_vtotal - 1) << 16));
5eddb70b
CW		 5930 I915_WRITE(VBLANK(pipe),
5931 (adjusted_mode->crtc_vblank_start - 1) |
79e53945 5932 ((adjusted_mode->crtc_vblank_end - 1) << 16));
5eddb70b
CW		 5933 I915_WRITE(VSYNC(pipe),
5934 (adjusted_mode->crtc_vsync_start - 1) |
79e53945 5935 ((adjusted_mode->crtc_vsync_end - 1) << 16));
5eddb70b 5936
8febb297
EA		 5937 /* pipesrc controls the size that is scaled from, which should
5938 * always be the user's requested size.
79e53945 5939 */
5eddb70b
CW		 5940 I915_WRITE(PIPESRC(pipe),
5941 ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
2c07245f 5942
8febb297
EA		 5943 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
5944 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
5945 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
5946 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
2c07245f 5947
8febb297
EA		 5948 if (has_edp_encoder &&
5949 !intel_encoder_is_pch_edp(&has_edp_encoder->base)) {
5950 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
2c07245f
ZW		 5951 }
5952
5eddb70b
CW		 5953 I915_WRITE(PIPECONF(pipe), pipeconf);
5954 POSTING_READ(PIPECONF(pipe));
79e53945 5955
9d0498a2 5956 intel_wait_for_vblank(dev, pipe);
79e53945 5957
f00a3ddf 5958 if (IS_GEN5(dev)) {
553bd149
ZW		 5959 /* enable address swizzle for tiling buffer */
5960 temp = I915_READ(DISP_ARB_CTL);
5961 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
5962 }
5963
5eddb70b 5964 I915_WRITE(DSPCNTR(plane), dspcntr);
b24e7179 5965 POSTING_READ(DSPCNTR(plane));
79e53945 5966
5c3b82e2 5967 ret = intel_pipe_set_base(crtc, x, y, old_fb);
7662c8bd
SL		 5968
5969 intel_update_watermarks(dev);
5970
1f803ee5 5971 return ret;
79e53945
JB		 5972}
5973
f564048e
EA		 5974static int intel_crtc_mode_set(struct drm_crtc *crtc,
5975 struct drm_display_mode *mode,
5976 struct drm_display_mode *adjusted_mode,
5977 int x, int y,
5978 struct drm_framebuffer *old_fb)
5979{
5980 struct drm_device *dev = crtc->dev;
5981 struct drm_i915_private *dev_priv = dev->dev_private;
0b701d27
EA		 5982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5983 int pipe = intel_crtc->pipe;
f564048e
EA		 5984 int ret;
5985
0b701d27 5986 drm_vblank_pre_modeset(dev, pipe);
7662c8bd 5987
f564048e
EA		 5988 ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5989 x, y, old_fb);
79e53945 5990 drm_vblank_post_modeset(dev, pipe);
5c3b82e2 5991
d8e70a25
JB		 5992 if (ret)
5993 intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
5994 else
5995 intel_crtc->dpms_mode = DRM_MODE_DPMS_ON;
120eced9 5996
1f803ee5 5997 return ret;
79e53945
JB		 5998}
5999
3a9627f4
WF		 6000static bool intel_eld_uptodate(struct drm_connector *connector,
6001 int reg_eldv, uint32_t bits_eldv,
6002 int reg_elda, uint32_t bits_elda,
6003 int reg_edid)
6004{
6005 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6006 uint8_t *eld = connector->eld;
6007 uint32_t i;
6008
6009 i = I915_READ(reg_eldv);
6010 i &= bits_eldv;
6011
6012 if (!eld[0])
6013 return !i;
6014
6015 if (!i)
6016 return false;
6017
6018 i = I915_READ(reg_elda);
6019 i &= ~bits_elda;
6020 I915_WRITE(reg_elda, i);
6021
6022 for (i = 0; i < eld[2]; i++)
6023 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
6024 return false;
6025
6026 return true;
6027}
6028
e0dac65e
WF		 6029static void g4x_write_eld(struct drm_connector *connector,
6030 struct drm_crtc *crtc)
6031{
6032 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6033 uint8_t *eld = connector->eld;
6034 uint32_t eldv;
6035 uint32_t len;
6036 uint32_t i;
6037
6038 i = I915_READ(G4X_AUD_VID_DID);
6039
6040 if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
6041 eldv = G4X_ELDV_DEVCL_DEVBLC;
6042 else
6043 eldv = G4X_ELDV_DEVCTG;
6044
3a9627f4
WF		 6045 if (intel_eld_uptodate(connector,
6046 G4X_AUD_CNTL_ST, eldv,
6047 G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
6048 G4X_HDMIW_HDMIEDID))
6049 return;
6050
e0dac65e
WF		 6051 i = I915_READ(G4X_AUD_CNTL_ST);
6052 i &= ~(eldv | G4X_ELD_ADDR);
6053 len = (i >> 9) & 0x1f; /* ELD buffer size */
6054 I915_WRITE(G4X_AUD_CNTL_ST, i);
6055
6056 if (!eld[0])
6057 return;
6058
6059 len = min_t(uint8_t, eld[2], len);
6060 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6061 for (i = 0; i < len; i++)
6062 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
6063
6064 i = I915_READ(G4X_AUD_CNTL_ST);
6065 i |= eldv;
6066 I915_WRITE(G4X_AUD_CNTL_ST, i);
6067}
6068
6069static void ironlake_write_eld(struct drm_connector *connector,
6070 struct drm_crtc *crtc)
6071{
6072 struct drm_i915_private *dev_priv = connector->dev->dev_private;
6073 uint8_t *eld = connector->eld;
6074 uint32_t eldv;
6075 uint32_t i;
6076 int len;
6077 int hdmiw_hdmiedid;
6078 int aud_cntl_st;
6079 int aud_cntrl_st2;
6080
b3f33cbf 6081 if (HAS_PCH_IBX(connector->dev)) {
1202b4c6
WF		 6082 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID_A;
6083 aud_cntl_st = IBX_AUD_CNTL_ST_A;
6084 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
e0dac65e 6085 } else {
1202b4c6
WF		 6086 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID_A;
6087 aud_cntl_st = CPT_AUD_CNTL_ST_A;
6088 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
e0dac65e
WF		 6089 }
6090
6091 i = to_intel_crtc(crtc)->pipe;
6092 hdmiw_hdmiedid += i * 0x100;
6093 aud_cntl_st += i * 0x100;
6094
6095 DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(i));
6096
6097 i = I915_READ(aud_cntl_st);
6098 i = (i >> 29) & 0x3; /* DIP_Port_Select, 0x1 = PortB */
6099 if (!i) {
6100 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
6101 /* operate blindly on all ports */
1202b4c6
WF		 6102 eldv = IBX_ELD_VALIDB;
6103 eldv |= IBX_ELD_VALIDB << 4;
6104 eldv |= IBX_ELD_VALIDB << 8;
e0dac65e
WF		 6105 } else {
6106 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
1202b4c6 6107 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
e0dac65e
WF		 6108 }
6109
3a9627f4
WF		 6110 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
6111 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
6112 eld[5] |= (1 << 2); /* Conn_Type, 0x1 = DisplayPort */
e0dac65e
WF		 6113 }
6114
3a9627f4
WF		 6115 if (intel_eld_uptodate(connector,
6116 aud_cntrl_st2, eldv,
6117 aud_cntl_st, IBX_ELD_ADDRESS,
6118 hdmiw_hdmiedid))
6119 return;
6120
e0dac65e
WF		 6121 i = I915_READ(aud_cntrl_st2);
6122 i &= ~eldv;
6123 I915_WRITE(aud_cntrl_st2, i);
6124
6125 if (!eld[0])
6126 return;
6127
e0dac65e 6128 i = I915_READ(aud_cntl_st);
1202b4c6 6129 i &= ~IBX_ELD_ADDRESS;
e0dac65e
WF		 6130 I915_WRITE(aud_cntl_st, i);
6131
6132 len = min_t(uint8_t, eld[2], 21); /* 84 bytes of hw ELD buffer */
6133 DRM_DEBUG_DRIVER("ELD size %d\n", len);
6134 for (i = 0; i < len; i++)
6135 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
6136
6137 i = I915_READ(aud_cntrl_st2);
6138 i |= eldv;
6139 I915_WRITE(aud_cntrl_st2, i);
6140}
6141
6142void intel_write_eld(struct drm_encoder *encoder,
6143 struct drm_display_mode *mode)
6144{
6145 struct drm_crtc *crtc = encoder->crtc;
6146 struct drm_connector *connector;
6147 struct drm_device *dev = encoder->dev;
6148 struct drm_i915_private *dev_priv = dev->dev_private;
6149
6150 connector = drm_select_eld(encoder, mode);
6151 if (!connector)
6152 return;
6153
6154 DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6155 connector->base.id,
6156 drm_get_connector_name(connector),
6157 connector->encoder->base.id,
6158 drm_get_encoder_name(connector->encoder));
6159
6160 connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
6161
6162 if (dev_priv->display.write_eld)
6163 dev_priv->display.write_eld(connector, crtc);
6164}
6165
79e53945
JB		 6166/** Loads the palette/gamma unit for the CRTC with the prepared values */
6167void intel_crtc_load_lut(struct drm_crtc *crtc)
6168{
6169 struct drm_device *dev = crtc->dev;
6170 struct drm_i915_private *dev_priv = dev->dev_private;
6171 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
9db4a9c7 6172 int palreg = PALETTE(intel_crtc->pipe);
79e53945
JB		 6173 int i;
6174
6175 /* The clocks have to be on to load the palette. */
6176 if (!crtc->enabled)
6177 return;
6178
f2b115e6 6179 /* use legacy palette for Ironlake */
bad720ff 6180 if (HAS_PCH_SPLIT(dev))
9db4a9c7 6181 palreg = LGC_PALETTE(intel_crtc->pipe);
2c07245f 6182
79e53945
JB		 6183 for (i = 0; i < 256; i++) {
6184 I915_WRITE(palreg + 4 * i,
6185 (intel_crtc->lut_r[i] << 16) |
6186 (intel_crtc->lut_g[i] << 8) |
6187 intel_crtc->lut_b[i]);
6188 }
6189}
6190
560b85bb
CW		 6191static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
6192{
6193 struct drm_device *dev = crtc->dev;
6194 struct drm_i915_private *dev_priv = dev->dev_private;
6195 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6196 bool visible = base != 0;
6197 u32 cntl;
6198
6199 if (intel_crtc->cursor_visible == visible)
6200 return;
6201
9db4a9c7 6202 cntl = I915_READ(_CURACNTR);
560b85bb
CW		 6203 if (visible) {
6204 /* On these chipsets we can only modify the base whilst
6205 * the cursor is disabled.
6206 */
9db4a9c7 6207 I915_WRITE(_CURABASE, base);
560b85bb
CW		 6208
6209 cntl &= ~(CURSOR_FORMAT_MASK);
6210 /* XXX width must be 64, stride 256 => 0x00 << 28 */
6211 cntl |= CURSOR_ENABLE |
6212 CURSOR_GAMMA_ENABLE |
6213 CURSOR_FORMAT_ARGB;
6214 } else
6215 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
9db4a9c7 6216 I915_WRITE(_CURACNTR, cntl);
560b85bb
CW		 6217
6218 intel_crtc->cursor_visible = visible;
6219}
6220
6221static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6222{
6223 struct drm_device *dev = crtc->dev;
6224 struct drm_i915_private *dev_priv = dev->dev_private;
6225 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6226 int pipe = intel_crtc->pipe;
6227 bool visible = base != 0;
6228
6229 if (intel_crtc->cursor_visible != visible) {
548f245b 6230 uint32_t cntl = I915_READ(CURCNTR(pipe));
560b85bb
CW		 6231 if (base) {
6232 cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6233 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6234 cntl |= pipe << 28; /* Connect to correct pipe */
6235 } else {
6236 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6237 cntl |= CURSOR_MODE_DISABLE;
6238 }
9db4a9c7 6239 I915_WRITE(CURCNTR(pipe), cntl);
560b85bb
CW		 6240
6241 intel_crtc->cursor_visible = visible;
6242 }
6243 /* and commit changes on next vblank */
9db4a9c7 6244 I915_WRITE(CURBASE(pipe), base);
560b85bb
CW		 6245}
6246
65a21cd6
JB		 6247static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6248{
6249 struct drm_device *dev = crtc->dev;
6250 struct drm_i915_private *dev_priv = dev->dev_private;
6251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6252 int pipe = intel_crtc->pipe;
6253 bool visible = base != 0;
6254
6255 if (intel_crtc->cursor_visible != visible) {
6256 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6257 if (base) {
6258 cntl &= ~CURSOR_MODE;
6259 cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6260 } else {
6261 cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6262 cntl |= CURSOR_MODE_DISABLE;
6263 }
6264 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6265
6266 intel_crtc->cursor_visible = visible;
6267 }
6268 /* and commit changes on next vblank */
6269 I915_WRITE(CURBASE_IVB(pipe), base);
6270}
6271
cda4b7d3 6272/* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6b383a7f
CW		 6273static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6274 bool on)
cda4b7d3
CW		 6275{
6276 struct drm_device *dev = crtc->dev;
6277 struct drm_i915_private *dev_priv = dev->dev_private;
6278 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6279 int pipe = intel_crtc->pipe;
6280 int x = intel_crtc->cursor_x;
6281 int y = intel_crtc->cursor_y;
560b85bb 6282 u32 base, pos;
cda4b7d3
CW		 6283 bool visible;
6284
6285 pos = 0;
6286
6b383a7f 6287 if (on && crtc->enabled && crtc->fb) {
cda4b7d3
CW		 6288 base = intel_crtc->cursor_addr;
6289 if (x > (int) crtc->fb->width)
6290 base = 0;
6291
6292 if (y > (int) crtc->fb->height)
6293 base = 0;
6294 } else
6295 base = 0;
6296
6297 if (x < 0) {
6298 if (x + intel_crtc->cursor_width < 0)
6299 base = 0;
6300
6301 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6302 x = -x;
6303 }
6304 pos |= x << CURSOR_X_SHIFT;
6305
6306 if (y < 0) {
6307 if (y + intel_crtc->cursor_height < 0)
6308 base = 0;
6309
6310 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6311 y = -y;
6312 }
6313 pos |= y << CURSOR_Y_SHIFT;
6314
6315 visible = base != 0;
560b85bb 6316 if (!visible && !intel_crtc->cursor_visible)
cda4b7d3
CW		 6317 return;
6318
65a21cd6
JB		 6319 if (IS_IVYBRIDGE(dev)) {
6320 I915_WRITE(CURPOS_IVB(pipe), pos);
6321 ivb_update_cursor(crtc, base);
6322 } else {
6323 I915_WRITE(CURPOS(pipe), pos);
6324 if (IS_845G(dev) || IS_I865G(dev))
6325 i845_update_cursor(crtc, base);
6326 else
6327 i9xx_update_cursor(crtc, base);
6328 }
cda4b7d3
CW		 6329
6330 if (visible)
6331 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
6332}
6333
79e53945 6334static int intel_crtc_cursor_set(struct drm_crtc *crtc,
05394f39 6335 struct drm_file *file,
79e53945
JB		 6336 uint32_t handle,
6337 uint32_t width, uint32_t height)
6338{
6339 struct drm_device *dev = crtc->dev;
6340 struct drm_i915_private *dev_priv = dev->dev_private;
6341 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
05394f39 6342 struct drm_i915_gem_object *obj;
cda4b7d3 6343 uint32_t addr;
3f8bc370 6344 int ret;
79e53945 6345
28c97730 6346 DRM_DEBUG_KMS("\n");
79e53945
JB		 6347
6348 /* if we want to turn off the cursor ignore width and height */
6349 if (!handle) {
28c97730 6350 DRM_DEBUG_KMS("cursor off\n");
3f8bc370 6351 addr = 0;
05394f39 6352 obj = NULL;
5004417d 6353 mutex_lock(&dev->struct_mutex);
3f8bc370 6354 goto finish;
79e53945
JB		 6355 }
6356
6357 /* Currently we only support 64x64 cursors */
6358 if (width != 64 || height != 64) {
6359 DRM_ERROR("we currently only support 64x64 cursors\n");
6360 return -EINVAL;
6361 }
6362
05394f39 6363 obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
c8725226 6364 if (&obj->base == NULL)
79e53945
JB		 6365 return -ENOENT;
6366
05394f39 6367 if (obj->base.size < width * height * 4) {
79e53945 6368 DRM_ERROR("buffer is to small\n");
34b8686e
DA		 6369 ret = -ENOMEM;
6370 goto fail;
79e53945
JB		 6371 }
6372
71acb5eb 6373 /* we only need to pin inside GTT if cursor is non-phy */
7f9872e0 6374 mutex_lock(&dev->struct_mutex);
b295d1b6 6375 if (!dev_priv->info->cursor_needs_physical) {
d9e86c0e
CW		 6376 if (obj->tiling_mode) {
6377 DRM_ERROR("cursor cannot be tiled\n");
6378 ret = -EINVAL;
6379 goto fail_locked;
6380 }
6381
2da3b9b9 6382 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
e7b526bb
CW		 6383 if (ret) {
6384 DRM_ERROR("failed to move cursor bo into the GTT\n");
2da3b9b9 6385 goto fail_locked;
e7b526bb
CW		 6386 }
6387
d9e86c0e
CW		 6388 ret = i915_gem_object_put_fence(obj);
6389 if (ret) {
2da3b9b9 6390 DRM_ERROR("failed to release fence for cursor");
d9e86c0e
CW		 6391 goto fail_unpin;
6392 }
6393
05394f39 6394 addr = obj->gtt_offset;
71acb5eb 6395 } else {
6eeefaf3 6396 int align = IS_I830(dev) ? 16 * 1024 : 256;
05394f39 6397 ret = i915_gem_attach_phys_object(dev, obj,
6eeefaf3
CW		 6398 (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6399 align);
71acb5eb
DA		 6400 if (ret) {
6401 DRM_ERROR("failed to attach phys object\n");
7f9872e0 6402 goto fail_locked;
71acb5eb 6403 }
05394f39 6404 addr = obj->phys_obj->handle->busaddr;
3f8bc370
KH		 6405 }
6406
a6c45cf0 6407 if (IS_GEN2(dev))
14b60391
JB		 6408 I915_WRITE(CURSIZE, (height << 12) | width);
6409
3f8bc370 6410 finish:
3f8bc370 6411 if (intel_crtc->cursor_bo) {
b295d1b6 6412 if (dev_priv->info->cursor_needs_physical) {
05394f39 6413 if (intel_crtc->cursor_bo != obj)
71acb5eb
DA		 6414 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6415 } else
6416 i915_gem_object_unpin(intel_crtc->cursor_bo);
05394f39 6417 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
3f8bc370 6418 }
80824003 6419
7f9872e0 6420 mutex_unlock(&dev->struct_mutex);
3f8bc370
KH		 6421
6422 intel_crtc->cursor_addr = addr;
05394f39 6423 intel_crtc->cursor_bo = obj;
cda4b7d3
CW		 6424 intel_crtc->cursor_width = width;
6425 intel_crtc->cursor_height = height;
6426
6b383a7f 6427 intel_crtc_update_cursor(crtc, true);
3f8bc370 6428
79e53945 6429 return 0;
e7b526bb 6430fail_unpin:
05394f39 6431 i915_gem_object_unpin(obj);
7f9872e0 6432fail_locked:
34b8686e 6433 mutex_unlock(&dev->struct_mutex);
bc9025bd 6434fail:
05394f39 6435 drm_gem_object_unreference_unlocked(&obj->base);
34b8686e 6436 return ret;
79e53945
JB		 6437}
6438
6439static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6440{
79e53945 6441 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6442
cda4b7d3
CW		 6443 intel_crtc->cursor_x = x;
6444 intel_crtc->cursor_y = y;
652c393a 6445
6b383a7f 6446 intel_crtc_update_cursor(crtc, true);
79e53945
JB		 6447
6448 return 0;
6449}
6450
6451/** Sets the color ramps on behalf of RandR */
6452void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6453 u16 blue, int regno)
6454{
6455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6456
6457 intel_crtc->lut_r[regno] = red >> 8;
6458 intel_crtc->lut_g[regno] = green >> 8;
6459 intel_crtc->lut_b[regno] = blue >> 8;
6460}
6461
b8c00ac5
DA		 6462void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6463 u16 *blue, int regno)
6464{
6465 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6466
6467 *red = intel_crtc->lut_r[regno] << 8;
6468 *green = intel_crtc->lut_g[regno] << 8;
6469 *blue = intel_crtc->lut_b[regno] << 8;
6470}
6471
79e53945 6472static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
7203425a 6473 u16 *blue, uint32_t start, uint32_t size)
79e53945 6474{
7203425a 6475 int end = (start + size > 256) ? 256 : start + size, i;
79e53945 6476 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
79e53945 6477
7203425a 6478 for (i = start; i < end; i++) {
79e53945
JB		 6479 intel_crtc->lut_r[i] = red[i] >> 8;
6480 intel_crtc->lut_g[i] = green[i] >> 8;
6481 intel_crtc->lut_b[i] = blue[i] >> 8;
6482 }
6483
6484 intel_crtc_load_lut(crtc);
6485}
6486
6487/**
6488 * Get a pipe with a simple mode set on it for doing load-based monitor
6489 * detection.
6490 *
6491 * It will be up to the load-detect code to adjust the pipe as appropriate for
c751ce4f 6492 * its requirements. The pipe will be connected to no other encoders.
79e53945 6493 *
c751ce4f 6494 * Currently this code will only succeed if there is a pipe with no encoders
79e53945
JB		 6495 * configured for it. In the future, it could choose to temporarily disable
6496 * some outputs to free up a pipe for its use.
6497 *
6498 * \return crtc, or NULL if no pipes are available.
6499 */
6500
6501/* VESA 640x480x72Hz mode to set on the pipe */
6502static struct drm_display_mode load_detect_mode = {
6503 DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6504 704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6505};
6506
d2dff872
CW		 6507static struct drm_framebuffer *
6508intel_framebuffer_create(struct drm_device *dev,
308e5bcb 6509 struct drm_mode_fb_cmd2 *mode_cmd,
d2dff872
CW		 6510 struct drm_i915_gem_object *obj)
6511{
6512 struct intel_framebuffer *intel_fb;
6513 int ret;
6514
6515 intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6516 if (!intel_fb) {
6517 drm_gem_object_unreference_unlocked(&obj->base);
6518 return ERR_PTR(-ENOMEM);
6519 }
6520
6521 ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6522 if (ret) {
6523 drm_gem_object_unreference_unlocked(&obj->base);
6524 kfree(intel_fb);
6525 return ERR_PTR(ret);
6526 }
6527
6528 return &intel_fb->base;
6529}
6530
6531static u32
6532intel_framebuffer_pitch_for_width(int width, int bpp)
6533{
6534 u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6535 return ALIGN(pitch, 64);
6536}
6537
6538static u32
6539intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6540{
6541 u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6542 return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6543}
6544
6545static struct drm_framebuffer *
6546intel_framebuffer_create_for_mode(struct drm_device *dev,
6547 struct drm_display_mode *mode,
6548 int depth, int bpp)
6549{
6550 struct drm_i915_gem_object *obj;
308e5bcb 6551 struct drm_mode_fb_cmd2 mode_cmd;
d2dff872
CW		 6552
6553 obj = i915_gem_alloc_object(dev,
6554 intel_framebuffer_size_for_mode(mode, bpp));
6555 if (obj == NULL)
6556 return ERR_PTR(-ENOMEM);
6557
6558 mode_cmd.width = mode->hdisplay;
6559 mode_cmd.height = mode->vdisplay;
308e5bcb
JB		 6560 mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6561 bpp);
6562 mode_cmd.pixel_format = 0;
d2dff872
CW		 6563
6564 return intel_framebuffer_create(dev, &mode_cmd, obj);
6565}
6566
6567static struct drm_framebuffer *
6568mode_fits_in_fbdev(struct drm_device *dev,
6569 struct drm_display_mode *mode)
6570{
6571 struct drm_i915_private *dev_priv = dev->dev_private;
6572 struct drm_i915_gem_object *obj;
6573 struct drm_framebuffer *fb;
6574
6575 if (dev_priv->fbdev == NULL)
6576 return NULL;
6577
6578 obj = dev_priv->fbdev->ifb.obj;
6579 if (obj == NULL)
6580 return NULL;
6581
6582 fb = &dev_priv->fbdev->ifb.base;
01f2c773
VS		 6583 if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6584 fb->bits_per_pixel))
d2dff872
CW		 6585 return NULL;
6586
01f2c773 6587 if (obj->base.size < mode->vdisplay * fb->pitches[0])
d2dff872
CW		 6588 return NULL;
6589
6590 return fb;
6591}
6592
7173188d
CW		 6593bool intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
6594 struct drm_connector *connector,
6595 struct drm_display_mode *mode,
8261b191 6596 struct intel_load_detect_pipe *old)
79e53945
JB		 6597{
6598 struct intel_crtc *intel_crtc;
6599 struct drm_crtc *possible_crtc;
4ef69c7a 6600 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6601 struct drm_crtc *crtc = NULL;
6602 struct drm_device *dev = encoder->dev;
d2dff872 6603 struct drm_framebuffer *old_fb;
79e53945
JB		 6604 int i = -1;
6605
d2dff872
CW		 6606 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6607 connector->base.id, drm_get_connector_name(connector),
6608 encoder->base.id, drm_get_encoder_name(encoder));
6609
79e53945
JB		 6610 /*
6611 * Algorithm gets a little messy:
7a5e4805 6612 *
79e53945
JB		 6613 * - if the connector already has an assigned crtc, use it (but make
6614 * sure it's on first)
7a5e4805 6615 *
79e53945
JB		 6616 * - try to find the first unused crtc that can drive this connector,
6617 * and use that if we find one
79e53945
JB		 6618 */
6619
6620 /* See if we already have a CRTC for this connector */
6621 if (encoder->crtc) {
6622 crtc = encoder->crtc;
8261b191 6623
79e53945 6624 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6625 old->dpms_mode = intel_crtc->dpms_mode;
6626 old->load_detect_temp = false;
6627
6628 /* Make sure the crtc and connector are running */
79e53945 6629 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
6492711d
CW		 6630 struct drm_encoder_helper_funcs *encoder_funcs;
6631 struct drm_crtc_helper_funcs *crtc_funcs;
6632
79e53945
JB		 6633 crtc_funcs = crtc->helper_private;
6634 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
6492711d
CW		 6635
6636 encoder_funcs = encoder->helper_private;
79e53945
JB		 6637 encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
6638 }
8261b191 6639
7173188d 6640 return true;
79e53945
JB		 6641 }
6642
6643 /* Find an unused one (if possible) */
6644 list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6645 i++;
6646 if (!(encoder->possible_crtcs & (1 << i)))
6647 continue;
6648 if (!possible_crtc->enabled) {
6649 crtc = possible_crtc;
6650 break;
6651 }
79e53945
JB		 6652 }
6653
6654 /*
6655 * If we didn't find an unused CRTC, don't use any.
6656 */
6657 if (!crtc) {
7173188d
CW		 6658 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6659 return false;
79e53945
JB		 6660 }
6661
6662 encoder->crtc = crtc;
c1c43977 6663 connector->encoder = encoder;
79e53945
JB		 6664
6665 intel_crtc = to_intel_crtc(crtc);
8261b191
CW		 6666 old->dpms_mode = intel_crtc->dpms_mode;
6667 old->load_detect_temp = true;
d2dff872 6668 old->release_fb = NULL;
79e53945 6669
6492711d
CW		 6670 if (!mode)
6671 mode = &load_detect_mode;
79e53945 6672
d2dff872
CW		 6673 old_fb = crtc->fb;
6674
6675 /* We need a framebuffer large enough to accommodate all accesses
6676 * that the plane may generate whilst we perform load detection.
6677 * We can not rely on the fbcon either being present (we get called
6678 * during its initialisation to detect all boot displays, or it may
6679 * not even exist) or that it is large enough to satisfy the
6680 * requested mode.
6681 */
6682 crtc->fb = mode_fits_in_fbdev(dev, mode);
6683 if (crtc->fb == NULL) {
6684 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6685 crtc->fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6686 old->release_fb = crtc->fb;
6687 } else
6688 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6689 if (IS_ERR(crtc->fb)) {
6690 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6691 crtc->fb = old_fb;
6692 return false;
79e53945 6693 }
79e53945 6694
d2dff872 6695 if (!drm_crtc_helper_set_mode(crtc, mode, 0, 0, old_fb)) {
6492711d 6696 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
d2dff872
CW		 6697 if (old->release_fb)
6698 old->release_fb->funcs->destroy(old->release_fb);
6699 crtc->fb = old_fb;
6492711d 6700 return false;
79e53945 6701 }
7173188d 6702
79e53945 6703 /* let the connector get through one full cycle before testing */
9d0498a2 6704 intel_wait_for_vblank(dev, intel_crtc->pipe);
79e53945 6705
7173188d 6706 return true;
79e53945
JB		 6707}
6708
c1c43977 6709void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
8261b191
CW		 6710 struct drm_connector *connector,
6711 struct intel_load_detect_pipe *old)
79e53945 6712{
4ef69c7a 6713 struct drm_encoder *encoder = &intel_encoder->base;
79e53945
JB		 6714 struct drm_device *dev = encoder->dev;
6715 struct drm_crtc *crtc = encoder->crtc;
6716 struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
6717 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
6718
d2dff872
CW		 6719 DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6720 connector->base.id, drm_get_connector_name(connector),
6721 encoder->base.id, drm_get_encoder_name(encoder));
6722
8261b191 6723 if (old->load_detect_temp) {
c1c43977 6724 connector->encoder = NULL;
79e53945 6725 drm_helper_disable_unused_functions(dev);
d2dff872
CW		 6726
6727 if (old->release_fb)
6728 old->release_fb->funcs->destroy(old->release_fb);
6729
0622a53c 6730 return;
79e53945
JB		 6731 }
6732
c751ce4f 6733 /* Switch crtc and encoder back off if necessary */
0622a53c
CW		 6734 if (old->dpms_mode != DRM_MODE_DPMS_ON) {
6735 encoder_funcs->dpms(encoder, old->dpms_mode);
8261b191 6736 crtc_funcs->dpms(crtc, old->dpms_mode);
79e53945
JB		 6737 }
6738}
6739
6740/* Returns the clock of the currently programmed mode of the given pipe. */
6741static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6742{
6743 struct drm_i915_private *dev_priv = dev->dev_private;
6744 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6745 int pipe = intel_crtc->pipe;
548f245b 6746 u32 dpll = I915_READ(DPLL(pipe));
79e53945
JB		 6747 u32 fp;
6748 intel_clock_t clock;
6749
6750 if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
39adb7a5 6751 fp = I915_READ(FP0(pipe));
79e53945 6752 else
39adb7a5 6753 fp = I915_READ(FP1(pipe));
79e53945
JB		 6754
6755 clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
f2b115e6
AJ		 6756 if (IS_PINEVIEW(dev)) {
6757 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6758 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
2177832f
SL		 6759 } else {
6760 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6761 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6762 }
6763
a6c45cf0 6764 if (!IS_GEN2(dev)) {
f2b115e6
AJ		 6765 if (IS_PINEVIEW(dev))
6766 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6767 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
2177832f
SL		 6768 else
6769 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
79e53945
JB		 6770 DPLL_FPA01_P1_POST_DIV_SHIFT);
6771
6772 switch (dpll & DPLL_MODE_MASK) {
6773 case DPLLB_MODE_DAC_SERIAL:
6774 clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6775 5 : 10;
6776 break;
6777 case DPLLB_MODE_LVDS:
6778 clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6779 7 : 14;
6780 break;
6781 default:
28c97730 6782 DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
79e53945
JB		 6783 "mode\n", (int)(dpll & DPLL_MODE_MASK));
6784 return 0;
6785 }
6786
6787 /* XXX: Handle the 100Mhz refclk */
2177832f 6788 intel_clock(dev, 96000, &clock);
79e53945
JB		 6789 } else {
6790 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6791
6792 if (is_lvds) {
6793 clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6794 DPLL_FPA01_P1_POST_DIV_SHIFT);
6795 clock.p2 = 14;
6796
6797 if ((dpll & PLL_REF_INPUT_MASK) ==
6798 PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6799 /* XXX: might not be 66MHz */
2177832f 6800 intel_clock(dev, 66000, &clock);
79e53945 6801 } else
2177832f 6802 intel_clock(dev, 48000, &clock);
79e53945
JB		 6803 } else {
6804 if (dpll & PLL_P1_DIVIDE_BY_TWO)
6805 clock.p1 = 2;
6806 else {
6807 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6808 DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6809 }
6810 if (dpll & PLL_P2_DIVIDE_BY_4)
6811 clock.p2 = 4;
6812 else
6813 clock.p2 = 2;
6814
2177832f 6815 intel_clock(dev, 48000, &clock);
79e53945
JB		 6816 }
6817 }
6818
6819 /* XXX: It would be nice to validate the clocks, but we can't reuse
6820 * i830PllIsValid() because it relies on the xf86_config connector
6821 * configuration being accurate, which it isn't necessarily.
6822 */
6823
6824 return clock.dot;
6825}
6826
6827/** Returns the currently programmed mode of the given pipe. */
6828struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6829 struct drm_crtc *crtc)
6830{
548f245b 6831 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB		 6832 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6833 int pipe = intel_crtc->pipe;
6834 struct drm_display_mode *mode;
548f245b
JB		 6835 int htot = I915_READ(HTOTAL(pipe));
6836 int hsync = I915_READ(HSYNC(pipe));
6837 int vtot = I915_READ(VTOTAL(pipe));
6838 int vsync = I915_READ(VSYNC(pipe));
79e53945
JB		 6839
6840 mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6841 if (!mode)
6842 return NULL;
6843
6844 mode->clock = intel_crtc_clock_get(dev, crtc);
6845 mode->hdisplay = (htot & 0xffff) + 1;
6846 mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6847 mode->hsync_start = (hsync & 0xffff) + 1;
6848 mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6849 mode->vdisplay = (vtot & 0xffff) + 1;
6850 mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6851 mode->vsync_start = (vsync & 0xffff) + 1;
6852 mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6853
6854 drm_mode_set_name(mode);
6855 drm_mode_set_crtcinfo(mode, 0);
6856
6857 return mode;
6858}
6859
652c393a
JB		 6860#define GPU_IDLE_TIMEOUT 500 /* ms */
6861
6862/* When this timer fires, we've been idle for awhile */
6863static void intel_gpu_idle_timer(unsigned long arg)
6864{
6865 struct drm_device *dev = (struct drm_device *)arg;
6866 drm_i915_private_t *dev_priv = dev->dev_private;
6867
ff7ea4c0
CW		 6868 if (!list_empty(&dev_priv->mm.active_list)) {
6869 /* Still processing requests, so just re-arm the timer. */
6870 mod_timer(&dev_priv->idle_timer, jiffies +
6871 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
6872 return;
6873 }
652c393a 6874
ff7ea4c0 6875 dev_priv->busy = false;
01dfba93 6876 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6877}
6878
652c393a
JB		 6879#define CRTC_IDLE_TIMEOUT 1000 /* ms */
6880
6881static void intel_crtc_idle_timer(unsigned long arg)
6882{
6883 struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
6884 struct drm_crtc *crtc = &intel_crtc->base;
6885 drm_i915_private_t *dev_priv = crtc->dev->dev_private;
ff7ea4c0 6886 struct intel_framebuffer *intel_fb;
652c393a 6887
ff7ea4c0
CW		 6888 intel_fb = to_intel_framebuffer(crtc->fb);
6889 if (intel_fb && intel_fb->obj->active) {
6890 /* The framebuffer is still being accessed by the GPU. */
6891 mod_timer(&intel_crtc->idle_timer, jiffies +
6892 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
6893 return;
6894 }
652c393a 6895
ff7ea4c0 6896 intel_crtc->busy = false;
01dfba93 6897 queue_work(dev_priv->wq, &dev_priv->idle_work);
652c393a
JB		 6898}
6899
3dec0095 6900static void intel_increase_pllclock(struct drm_crtc *crtc)
652c393a
JB		 6901{
6902 struct drm_device *dev = crtc->dev;
6903 drm_i915_private_t *dev_priv = dev->dev_private;
6904 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6905 int pipe = intel_crtc->pipe;
dbdc6479
JB		 6906 int dpll_reg = DPLL(pipe);
6907 int dpll;
652c393a 6908
bad720ff 6909 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6910 return;
6911
6912 if (!dev_priv->lvds_downclock_avail)
6913 return;
6914
dbdc6479 6915 dpll = I915_READ(dpll_reg);
652c393a 6916 if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
44d98a61 6917 DRM_DEBUG_DRIVER("upclocking LVDS\n");
652c393a
JB		 6918
6919 /* Unlock panel regs */
dbdc6479
JB		 6920 I915_WRITE(PP_CONTROL,
6921 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
652c393a
JB		 6922
6923 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6924 I915_WRITE(dpll_reg, dpll);
9d0498a2 6925 intel_wait_for_vblank(dev, pipe);
dbdc6479 6926
652c393a
JB		 6927 dpll = I915_READ(dpll_reg);
6928 if (dpll & DISPLAY_RATE_SELECT_FPA1)
44d98a61 6929 DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
652c393a
JB		 6930
6931 /* ...and lock them again */
6932 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6933 }
6934
6935 /* Schedule downclock */
3dec0095
DV		 6936 mod_timer(&intel_crtc->idle_timer, jiffies +
6937 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
652c393a
JB		 6938}
6939
6940static void intel_decrease_pllclock(struct drm_crtc *crtc)
6941{
6942 struct drm_device *dev = crtc->dev;
6943 drm_i915_private_t *dev_priv = dev->dev_private;
6944 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6945 int pipe = intel_crtc->pipe;
9db4a9c7 6946 int dpll_reg = DPLL(pipe);
652c393a
JB		 6947 int dpll = I915_READ(dpll_reg);
6948
bad720ff 6949 if (HAS_PCH_SPLIT(dev))
652c393a
JB		 6950 return;
6951
6952 if (!dev_priv->lvds_downclock_avail)
6953 return;
6954
6955 /*
6956 * Since this is called by a timer, we should never get here in
6957 * the manual case.
6958 */
6959 if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
44d98a61 6960 DRM_DEBUG_DRIVER("downclocking LVDS\n");
652c393a
JB		 6961
6962 /* Unlock panel regs */
4a655f04
JB		 6963 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
6964 PANEL_UNLOCK_REGS);
652c393a
JB		 6965
6966 dpll |= DISPLAY_RATE_SELECT_FPA1;
6967 I915_WRITE(dpll_reg, dpll);
9d0498a2 6968 intel_wait_for_vblank(dev, pipe);
652c393a
JB		 6969 dpll = I915_READ(dpll_reg);
6970 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
44d98a61 6971 DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
652c393a
JB		 6972
6973 /* ...and lock them again */
6974 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
6975 }
6976
6977}
6978
6979/**
6980 * intel_idle_update - adjust clocks for idleness
6981 * @work: work struct
6982 *
6983 * Either the GPU or display (or both) went idle. Check the busy status
6984 * here and adjust the CRTC and GPU clocks as necessary.
6985 */
6986static void intel_idle_update(struct work_struct *work)
6987{
6988 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
6989 idle_work);
6990 struct drm_device *dev = dev_priv->dev;
6991 struct drm_crtc *crtc;
6992 struct intel_crtc *intel_crtc;
6993
6994 if (!i915_powersave)
6995 return;
6996
6997 mutex_lock(&dev->struct_mutex);
6998
7648fa99
JB		 6999 i915_update_gfx_val(dev_priv);
7000
652c393a
JB		 7001 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7002 /* Skip inactive CRTCs */
7003 if (!crtc->fb)
7004 continue;
7005
7006 intel_crtc = to_intel_crtc(crtc);
7007 if (!intel_crtc->busy)
7008 intel_decrease_pllclock(crtc);
7009 }
7010
45ac22c8 7011
652c393a
JB		 7012 mutex_unlock(&dev->struct_mutex);
7013}
7014
7015/**
7016 * intel_mark_busy - mark the GPU and possibly the display busy
7017 * @dev: drm device
7018 * @obj: object we're operating on
7019 *
7020 * Callers can use this function to indicate that the GPU is busy processing
7021 * commands. If @obj matches one of the CRTC objects (i.e. it's a scanout
7022 * buffer), we'll also mark the display as busy, so we know to increase its
7023 * clock frequency.
7024 */
05394f39 7025void intel_mark_busy(struct drm_device *dev, struct drm_i915_gem_object *obj)
652c393a
JB		 7026{
7027 drm_i915_private_t *dev_priv = dev->dev_private;
7028 struct drm_crtc *crtc = NULL;
7029 struct intel_framebuffer *intel_fb;
7030 struct intel_crtc *intel_crtc;
7031
5e17ee74
ZW		 7032 if (!drm_core_check_feature(dev, DRIVER_MODESET))
7033 return;
7034
18b2190c 7035 if (!dev_priv->busy)
28cf798f 7036 dev_priv->busy = true;
18b2190c 7037 else
28cf798f
CW		 7038 mod_timer(&dev_priv->idle_timer, jiffies +
7039 msecs_to_jiffies(GPU_IDLE_TIMEOUT));
652c393a
JB		 7040
7041 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
7042 if (!crtc->fb)
7043 continue;
7044
7045 intel_crtc = to_intel_crtc(crtc);
7046 intel_fb = to_intel_framebuffer(crtc->fb);
7047 if (intel_fb->obj == obj) {
7048 if (!intel_crtc->busy) {
7049 /* Non-busy -> busy, upclock */
3dec0095 7050 intel_increase_pllclock(crtc);
652c393a
JB		 7051 intel_crtc->busy = true;
7052 } else {
7053 /* Busy -> busy, put off timer */
7054 mod_timer(&intel_crtc->idle_timer, jiffies +
7055 msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
7056 }
7057 }
7058 }
7059}
7060
79e53945
JB		 7061static void intel_crtc_destroy(struct drm_crtc *crtc)
7062{
7063 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
67e77c5a
DV		 7064 struct drm_device *dev = crtc->dev;
7065 struct intel_unpin_work *work;
7066 unsigned long flags;
7067
7068 spin_lock_irqsave(&dev->event_lock, flags);
7069 work = intel_crtc->unpin_work;
7070 intel_crtc->unpin_work = NULL;
7071 spin_unlock_irqrestore(&dev->event_lock, flags);
7072
7073 if (work) {
7074 cancel_work_sync(&work->work);
7075 kfree(work);
7076 }
79e53945
JB		 7077
7078 drm_crtc_cleanup(crtc);
67e77c5a 7079
79e53945
JB		 7080 kfree(intel_crtc);
7081}
7082
6b95a207
KH		 7083static void intel_unpin_work_fn(struct work_struct *__work)
7084{
7085 struct intel_unpin_work *work =
7086 container_of(__work, struct intel_unpin_work, work);
7087
7088 mutex_lock(&work->dev->struct_mutex);
b1b87f6b 7089 i915_gem_object_unpin(work->old_fb_obj);
05394f39
CW		 7090 drm_gem_object_unreference(&work->pending_flip_obj->base);
7091 drm_gem_object_unreference(&work->old_fb_obj->base);
d9e86c0e 7092
7782de3b 7093 intel_update_fbc(work->dev);
6b95a207
KH		 7094 mutex_unlock(&work->dev->struct_mutex);
7095 kfree(work);
7096}
7097
1afe3e9d 7098static void do_intel_finish_page_flip(struct drm_device *dev,
49b14a5c 7099 struct drm_crtc *crtc)
6b95a207
KH		 7100{
7101 drm_i915_private_t *dev_priv = dev->dev_private;
6b95a207
KH		 7102 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7103 struct intel_unpin_work *work;
05394f39 7104 struct drm_i915_gem_object *obj;
6b95a207 7105 struct drm_pending_vblank_event *e;
49b14a5c 7106 struct timeval tnow, tvbl;
6b95a207
KH		 7107 unsigned long flags;
7108
7109 /* Ignore early vblank irqs */
7110 if (intel_crtc == NULL)
7111 return;
7112
49b14a5c
MK		 7113 do_gettimeofday(&tnow);
7114
6b95a207
KH		 7115 spin_lock_irqsave(&dev->event_lock, flags);
7116 work = intel_crtc->unpin_work;
7117 if (work == NULL || !work->pending) {
7118 spin_unlock_irqrestore(&dev->event_lock, flags);
7119 return;
7120 }
7121
7122 intel_crtc->unpin_work = NULL;
6b95a207
KH		 7123
7124 if (work->event) {
7125 e = work->event;
49b14a5c 7126 e->event.sequence = drm_vblank_count_and_time(dev, intel_crtc->pipe, &tvbl);
0af7e4df
MK		 7127
7128 /* Called before vblank count and timestamps have
7129 * been updated for the vblank interval of flip
7130 * completion? Need to increment vblank count and
7131 * add one videorefresh duration to returned timestamp
49b14a5c
MK		 7132 * to account for this. We assume this happened if we
7133 * get called over 0.9 frame durations after the last
7134 * timestamped vblank.
7135 *
7136 * This calculation can not be used with vrefresh rates
7137 * below 5Hz (10Hz to be on the safe side) without
7138 * promoting to 64 integers.
0af7e4df 7139 */
49b14a5c
MK		 7140 if (10 * (timeval_to_ns(&tnow) - timeval_to_ns(&tvbl)) >
7141 9 * crtc->framedur_ns) {
0af7e4df 7142 e->event.sequence++;
49b14a5c
MK		 7143 tvbl = ns_to_timeval(timeval_to_ns(&tvbl) +
7144 crtc->framedur_ns);
0af7e4df
MK		 7145 }
7146
49b14a5c
MK		 7147 e->event.tv_sec = tvbl.tv_sec;
7148 e->event.tv_usec = tvbl.tv_usec;
0af7e4df 7149
6b95a207
KH		 7150 list_add_tail(&e->base.link,
7151 &e->base.file_priv->event_list);
7152 wake_up_interruptible(&e->base.file_priv->event_wait);
7153 }
7154
0af7e4df
MK		 7155 drm_vblank_put(dev, intel_crtc->pipe);
7156
6b95a207
KH		 7157 spin_unlock_irqrestore(&dev->event_lock, flags);
7158
05394f39 7159 obj = work->old_fb_obj;
d9e86c0e 7160
e59f2bac 7161 atomic_clear_mask(1 << intel_crtc->plane,
05394f39
CW		 7162 &obj->pending_flip.counter);
7163 if (atomic_read(&obj->pending_flip) == 0)
f787a5f5 7164 wake_up(&dev_priv->pending_flip_queue);
d9e86c0e 7165
6b95a207 7166 schedule_work(&work->work);
e5510fac
JB		 7167
7168 trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6b95a207
KH		 7169}
7170
1afe3e9d
JB		 7171void intel_finish_page_flip(struct drm_device *dev, int pipe)
7172{
7173 drm_i915_private_t *dev_priv = dev->dev_private;
7174 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
7175
49b14a5c 7176 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7177}
7178
7179void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
7180{
7181 drm_i915_private_t *dev_priv = dev->dev_private;
7182 struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
7183
49b14a5c 7184 do_intel_finish_page_flip(dev, crtc);
1afe3e9d
JB		 7185}
7186
6b95a207
KH		 7187void intel_prepare_page_flip(struct drm_device *dev, int plane)
7188{
7189 drm_i915_private_t *dev_priv = dev->dev_private;
7190 struct intel_crtc *intel_crtc =
7191 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
7192 unsigned long flags;
7193
7194 spin_lock_irqsave(&dev->event_lock, flags);
de3f440f 7195 if (intel_crtc->unpin_work) {
4e5359cd
SF		 7196 if ((++intel_crtc->unpin_work->pending) > 1)
7197 DRM_ERROR("Prepared flip multiple times\n");
de3f440f
JB		 7198 } else {
7199 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
7200 }
6b95a207
KH		 7201 spin_unlock_irqrestore(&dev->event_lock, flags);
7202}
7203
8c9f3aaf
JB		 7204static int intel_gen2_queue_flip(struct drm_device *dev,
7205 struct drm_crtc *crtc,
7206 struct drm_framebuffer *fb,
7207 struct drm_i915_gem_object *obj)
7208{
7209 struct drm_i915_private *dev_priv = dev->dev_private;
7210 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7211 unsigned long offset;
7212 u32 flip_mask;
7213 int ret;
7214
7215 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7216 if (ret)
7217 goto out;
7218
7219 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 7220 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf
JB		 7221
7222 ret = BEGIN_LP_RING(6);
7223 if (ret)
7224 goto out;
7225
7226 /* Can't queue multiple flips, so wait for the previous
7227 * one to finish before executing the next.
7228 */
7229 if (intel_crtc->plane)
7230 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7231 else
7232 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7233 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7234 OUT_RING(MI_NOOP);
7235 OUT_RING(MI_DISPLAY_FLIP |
7236 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7237 OUT_RING(fb->pitches[0]);
8c9f3aaf
JB		 7238 OUT_RING(obj->gtt_offset + offset);
7239 OUT_RING(MI_NOOP);
7240 ADVANCE_LP_RING();
7241out:
7242 return ret;
7243}
7244
7245static int intel_gen3_queue_flip(struct drm_device *dev,
7246 struct drm_crtc *crtc,
7247 struct drm_framebuffer *fb,
7248 struct drm_i915_gem_object *obj)
7249{
7250 struct drm_i915_private *dev_priv = dev->dev_private;
7251 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7252 unsigned long offset;
7253 u32 flip_mask;
7254 int ret;
7255
7256 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7257 if (ret)
7258 goto out;
7259
7260 /* Offset into the new buffer for cases of shared fbs between CRTCs */
01f2c773 7261 offset = crtc->y * fb->pitches[0] + crtc->x * fb->bits_per_pixel/8;
8c9f3aaf
JB		 7262
7263 ret = BEGIN_LP_RING(6);
7264 if (ret)
7265 goto out;
7266
7267 if (intel_crtc->plane)
7268 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
7269 else
7270 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
7271 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
7272 OUT_RING(MI_NOOP);
7273 OUT_RING(MI_DISPLAY_FLIP_I915 |
7274 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7275 OUT_RING(fb->pitches[0]);
8c9f3aaf
JB		 7276 OUT_RING(obj->gtt_offset + offset);
7277 OUT_RING(MI_NOOP);
7278
7279 ADVANCE_LP_RING();
7280out:
7281 return ret;
7282}
7283
7284static int intel_gen4_queue_flip(struct drm_device *dev,
7285 struct drm_crtc *crtc,
7286 struct drm_framebuffer *fb,
7287 struct drm_i915_gem_object *obj)
7288{
7289 struct drm_i915_private *dev_priv = dev->dev_private;
7290 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7291 uint32_t pf, pipesrc;
7292 int ret;
7293
7294 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7295 if (ret)
7296 goto out;
7297
7298 ret = BEGIN_LP_RING(4);
7299 if (ret)
7300 goto out;
7301
7302 /* i965+ uses the linear or tiled offsets from the
7303 * Display Registers (which do not change across a page-flip)
7304 * so we need only reprogram the base address.
7305 */
7306 OUT_RING(MI_DISPLAY_FLIP |
7307 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7308 OUT_RING(fb->pitches[0]);
8c9f3aaf
JB		 7309 OUT_RING(obj->gtt_offset | obj->tiling_mode);
7310
7311 /* XXX Enabling the panel-fitter across page-flip is so far
7312 * untested on non-native modes, so ignore it for now.
7313 * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
7314 */
7315 pf = 0;
7316 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7317 OUT_RING(pf | pipesrc);
7318 ADVANCE_LP_RING();
7319out:
7320 return ret;
7321}
7322
7323static int intel_gen6_queue_flip(struct drm_device *dev,
7324 struct drm_crtc *crtc,
7325 struct drm_framebuffer *fb,
7326 struct drm_i915_gem_object *obj)
7327{
7328 struct drm_i915_private *dev_priv = dev->dev_private;
7329 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7330 uint32_t pf, pipesrc;
7331 int ret;
7332
7333 ret = intel_pin_and_fence_fb_obj(dev, obj, LP_RING(dev_priv));
7334 if (ret)
7335 goto out;
7336
7337 ret = BEGIN_LP_RING(4);
7338 if (ret)
7339 goto out;
7340
7341 OUT_RING(MI_DISPLAY_FLIP |
7342 MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
01f2c773 7343 OUT_RING(fb->pitches[0] | obj->tiling_mode);
8c9f3aaf
JB		 7344 OUT_RING(obj->gtt_offset);
7345
7346 pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7347 pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7348 OUT_RING(pf | pipesrc);
7349 ADVANCE_LP_RING();
7350out:
7351 return ret;
7352}
7353
7c9017e5
JB		 7354/*
7355 * On gen7 we currently use the blit ring because (in early silicon at least)
7356 * the render ring doesn't give us interrpts for page flip completion, which
7357 * means clients will hang after the first flip is queued. Fortunately the
7358 * blit ring generates interrupts properly, so use it instead.
7359 */
7360static int intel_gen7_queue_flip(struct drm_device *dev,
7361 struct drm_crtc *crtc,
7362 struct drm_framebuffer *fb,
7363 struct drm_i915_gem_object *obj)
7364{
7365 struct drm_i915_private *dev_priv = dev->dev_private;
7366 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7367 struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7368 int ret;
7369
7370 ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7371 if (ret)
7372 goto out;
7373
7374 ret = intel_ring_begin(ring, 4);
7375 if (ret)
7376 goto out;
7377
7378 intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | (intel_crtc->plane << 19));
01f2c773 7379 intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7c9017e5
JB		 7380 intel_ring_emit(ring, (obj->gtt_offset));
7381 intel_ring_emit(ring, (MI_NOOP));
7382 intel_ring_advance(ring);
7383out:
7384 return ret;
7385}
7386
8c9f3aaf
JB		 7387static int intel_default_queue_flip(struct drm_device *dev,
7388 struct drm_crtc *crtc,
7389 struct drm_framebuffer *fb,
7390 struct drm_i915_gem_object *obj)
7391{
7392 return -ENODEV;
7393}
7394
6b95a207
KH		 7395static int intel_crtc_page_flip(struct drm_crtc *crtc,
7396 struct drm_framebuffer *fb,
7397 struct drm_pending_vblank_event *event)
7398{
7399 struct drm_device *dev = crtc->dev;
7400 struct drm_i915_private *dev_priv = dev->dev_private;
7401 struct intel_framebuffer *intel_fb;
05394f39 7402 struct drm_i915_gem_object *obj;
6b95a207
KH		 7403 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7404 struct intel_unpin_work *work;
8c9f3aaf 7405 unsigned long flags;
52e68630 7406 int ret;
6b95a207
KH		 7407
7408 work = kzalloc(sizeof *work, GFP_KERNEL);
7409 if (work == NULL)
7410 return -ENOMEM;
7411
6b95a207
KH		 7412 work->event = event;
7413 work->dev = crtc->dev;
7414 intel_fb = to_intel_framebuffer(crtc->fb);
b1b87f6b 7415 work->old_fb_obj = intel_fb->obj;
6b95a207
KH		 7416 INIT_WORK(&work->work, intel_unpin_work_fn);
7417
7317c75e
JB		 7418 ret = drm_vblank_get(dev, intel_crtc->pipe);
7419 if (ret)
7420 goto free_work;
7421
6b95a207
KH		 7422 /* We borrow the event spin lock for protecting unpin_work */
7423 spin_lock_irqsave(&dev->event_lock, flags);
7424 if (intel_crtc->unpin_work) {
7425 spin_unlock_irqrestore(&dev->event_lock, flags);
7426 kfree(work);
7317c75e 7427 drm_vblank_put(dev, intel_crtc->pipe);
468f0b44
CW		 7428
7429 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
6b95a207
KH		 7430 return -EBUSY;
7431 }
7432 intel_crtc->unpin_work = work;
7433 spin_unlock_irqrestore(&dev->event_lock, flags);
7434
7435 intel_fb = to_intel_framebuffer(fb);
7436 obj = intel_fb->obj;
7437
468f0b44 7438 mutex_lock(&dev->struct_mutex);
6b95a207 7439
75dfca80 7440 /* Reference the objects for the scheduled work. */
05394f39
CW		 7441 drm_gem_object_reference(&work->old_fb_obj->base);
7442 drm_gem_object_reference(&obj->base);
6b95a207
KH		 7443
7444 crtc->fb = fb;
96b099fd 7445
e1f99ce6 7446 work->pending_flip_obj = obj;
e1f99ce6 7447
4e5359cd
SF		 7448 work->enable_stall_check = true;
7449
e1f99ce6
CW		 7450 /* Block clients from rendering to the new back buffer until
7451 * the flip occurs and the object is no longer visible.
7452 */
05394f39 7453 atomic_add(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
e1f99ce6 7454
8c9f3aaf
JB		 7455 ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7456 if (ret)
7457 goto cleanup_pending;
6b95a207 7458
7782de3b 7459 intel_disable_fbc(dev);
6b95a207
KH		 7460 mutex_unlock(&dev->struct_mutex);
7461
e5510fac
JB		 7462 trace_i915_flip_request(intel_crtc->plane, obj);
7463
6b95a207 7464 return 0;
96b099fd 7465
8c9f3aaf
JB		 7466cleanup_pending:
7467 atomic_sub(1 << intel_crtc->plane, &work->old_fb_obj->pending_flip);
05394f39
CW		 7468 drm_gem_object_unreference(&work->old_fb_obj->base);
7469 drm_gem_object_unreference(&obj->base);
96b099fd
CW		 7470 mutex_unlock(&dev->struct_mutex);
7471
7472 spin_lock_irqsave(&dev->event_lock, flags);
7473 intel_crtc->unpin_work = NULL;
7474 spin_unlock_irqrestore(&dev->event_lock, flags);
7475
7317c75e
JB		 7476 drm_vblank_put(dev, intel_crtc->pipe);
7477free_work:
96b099fd
CW		 7478 kfree(work);
7479
7480 return ret;
6b95a207
KH		 7481}
7482
47f1c6c9
CW		 7483static void intel_sanitize_modesetting(struct drm_device *dev,
7484 int pipe, int plane)
7485{
7486 struct drm_i915_private *dev_priv = dev->dev_private;
7487 u32 reg, val;
7488
7489 if (HAS_PCH_SPLIT(dev))
7490 return;
7491
7492 /* Who knows what state these registers were left in by the BIOS or
7493 * grub?
7494 *
7495 * If we leave the registers in a conflicting state (e.g. with the
7496 * display plane reading from the other pipe than the one we intend
7497 * to use) then when we attempt to teardown the active mode, we will
7498 * not disable the pipes and planes in the correct order -- leaving
7499 * a plane reading from a disabled pipe and possibly leading to
7500 * undefined behaviour.
7501 */
7502
7503 reg = DSPCNTR(plane);
7504 val = I915_READ(reg);
7505
7506 if ((val & DISPLAY_PLANE_ENABLE) == 0)
7507 return;
7508 if (!!(val & DISPPLANE_SEL_PIPE_MASK) == pipe)
7509 return;
7510
7511 /* This display plane is active and attached to the other CPU pipe. */
7512 pipe = !pipe;
7513
7514 /* Disable the plane and wait for it to stop reading from the pipe. */
b24e7179
JB		 7515 intel_disable_plane(dev_priv, plane, pipe);
7516 intel_disable_pipe(dev_priv, pipe);
47f1c6c9 7517}
79e53945 7518
f6e5b160
CW		 7519static void intel_crtc_reset(struct drm_crtc *crtc)
7520{
7521 struct drm_device *dev = crtc->dev;
7522 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7523
7524 /* Reset flags back to the 'unknown' status so that they
7525 * will be correctly set on the initial modeset.
7526 */
7527 intel_crtc->dpms_mode = -1;
7528
7529 /* We need to fix up any BIOS configuration that conflicts with
7530 * our expectations.
7531 */
7532 intel_sanitize_modesetting(dev, intel_crtc->pipe, intel_crtc->plane);
7533}
7534
7535static struct drm_crtc_helper_funcs intel_helper_funcs = {
7536 .dpms = intel_crtc_dpms,
7537 .mode_fixup = intel_crtc_mode_fixup,
7538 .mode_set = intel_crtc_mode_set,
7539 .mode_set_base = intel_pipe_set_base,
7540 .mode_set_base_atomic = intel_pipe_set_base_atomic,
7541 .load_lut = intel_crtc_load_lut,
7542 .disable = intel_crtc_disable,
7543};
7544
7545static const struct drm_crtc_funcs intel_crtc_funcs = {
7546 .reset = intel_crtc_reset,
7547 .cursor_set = intel_crtc_cursor_set,
7548 .cursor_move = intel_crtc_cursor_move,
7549 .gamma_set = intel_crtc_gamma_set,
7550 .set_config = drm_crtc_helper_set_config,
7551 .destroy = intel_crtc_destroy,
7552 .page_flip = intel_crtc_page_flip,
7553};
7554
b358d0a6 7555static void intel_crtc_init(struct drm_device *dev, int pipe)
79e53945 7556{
22fd0fab 7557 drm_i915_private_t *dev_priv = dev->dev_private;
79e53945
JB		 7558 struct intel_crtc *intel_crtc;
7559 int i;
7560
7561 intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
7562 if (intel_crtc == NULL)
7563 return;
7564
7565 drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
7566
7567 drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
79e53945
JB		 7568 for (i = 0; i < 256; i++) {
7569 intel_crtc->lut_r[i] = i;
7570 intel_crtc->lut_g[i] = i;
7571 intel_crtc->lut_b[i] = i;
7572 }
7573
80824003
JB		 7574 /* Swap pipes & planes for FBC on pre-965 */
7575 intel_crtc->pipe = pipe;
7576 intel_crtc->plane = pipe;
e2e767ab 7577 if (IS_MOBILE(dev) && IS_GEN3(dev)) {
28c97730 7578 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
e2e767ab 7579 intel_crtc->plane = !pipe;
80824003
JB		 7580 }
7581
22fd0fab
JB		 7582 BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
7583 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
7584 dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
7585 dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
7586
5d1d0cc8 7587 intel_crtc_reset(&intel_crtc->base);
04dbff52 7588 intel_crtc->active = true; /* force the pipe off on setup_init_config */
5a354204 7589 intel_crtc->bpp = 24; /* default for pre-Ironlake */
7e7d76c3
JB		 7590
7591 if (HAS_PCH_SPLIT(dev)) {
4b645f14
JB		 7592 if (pipe == 2 && IS_IVYBRIDGE(dev))
7593 intel_crtc->no_pll = true;
7e7d76c3
JB		 7594 intel_helper_funcs.prepare = ironlake_crtc_prepare;
7595 intel_helper_funcs.commit = ironlake_crtc_commit;
7596 } else {
7597 intel_helper_funcs.prepare = i9xx_crtc_prepare;
7598 intel_helper_funcs.commit = i9xx_crtc_commit;
7599 }
7600
79e53945
JB		 7601 drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
7602
652c393a
JB		 7603 intel_crtc->busy = false;
7604
7605 setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
7606 (unsigned long)intel_crtc);
79e53945
JB		 7607}
7608
08d7b3d1 7609int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
05394f39 7610 struct drm_file *file)
08d7b3d1
CW		 7611{
7612 drm_i915_private_t *dev_priv = dev->dev_private;
7613 struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
c05422d5
DV		 7614 struct drm_mode_object *drmmode_obj;
7615 struct intel_crtc *crtc;
08d7b3d1
CW		 7616
7617 if (!dev_priv) {
7618 DRM_ERROR("called with no initialization\n");
7619 return -EINVAL;
7620 }
7621
c05422d5
DV		 7622 drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
7623 DRM_MODE_OBJECT_CRTC);
08d7b3d1 7624
c05422d5 7625 if (!drmmode_obj) {
08d7b3d1
CW		 7626 DRM_ERROR("no such CRTC id\n");
7627 return -EINVAL;
7628 }
7629
c05422d5
DV		 7630 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
7631 pipe_from_crtc_id->pipe = crtc->pipe;
08d7b3d1 7632
c05422d5 7633 return 0;
08d7b3d1
CW		 7634}
7635
c5e4df33 7636static int intel_encoder_clones(struct drm_device *dev, int type_mask)
79e53945 7637{
4ef69c7a 7638 struct intel_encoder *encoder;
79e53945 7639 int index_mask = 0;
79e53945
JB		 7640 int entry = 0;
7641
4ef69c7a
CW		 7642 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7643 if (type_mask & encoder->clone_mask)
79e53945
JB		 7644 index_mask |= (1 << entry);
7645 entry++;
7646 }
4ef69c7a 7647
79e53945
JB		 7648 return index_mask;
7649}
7650
4d302442
CW		 7651static bool has_edp_a(struct drm_device *dev)
7652{
7653 struct drm_i915_private *dev_priv = dev->dev_private;
7654
7655 if (!IS_MOBILE(dev))
7656 return false;
7657
7658 if ((I915_READ(DP_A) & DP_DETECTED) == 0)
7659 return false;
7660
7661 if (IS_GEN5(dev) &&
7662 (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
7663 return false;
7664
7665 return true;
7666}
7667
79e53945
JB		 7668static void intel_setup_outputs(struct drm_device *dev)
7669{
725e30ad 7670 struct drm_i915_private *dev_priv = dev->dev_private;
4ef69c7a 7671 struct intel_encoder *encoder;
cb0953d7 7672 bool dpd_is_edp = false;
c5d1b51d 7673 bool has_lvds = false;
79e53945 7674
541998a1 7675 if (IS_MOBILE(dev) && !IS_I830(dev))
c5d1b51d
CW		 7676 has_lvds = intel_lvds_init(dev);
7677 if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
7678 /* disable the panel fitter on everything but LVDS */
7679 I915_WRITE(PFIT_CONTROL, 0);
7680 }
79e53945 7681
bad720ff 7682 if (HAS_PCH_SPLIT(dev)) {
cb0953d7 7683 dpd_is_edp = intel_dpd_is_edp(dev);
30ad48b7 7684
4d302442 7685 if (has_edp_a(dev))
32f9d658
ZW		 7686 intel_dp_init(dev, DP_A);
7687
cb0953d7
AJ		 7688 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
7689 intel_dp_init(dev, PCH_DP_D);
7690 }
7691
7692 intel_crt_init(dev);
7693
7694 if (HAS_PCH_SPLIT(dev)) {
7695 int found;
7696
30ad48b7 7697 if (I915_READ(HDMIB) & PORT_DETECTED) {
461ed3ca
ZY		 7698 /* PCH SDVOB multiplex with HDMIB */
7699 found = intel_sdvo_init(dev, PCH_SDVOB);
30ad48b7
ZW		 7700 if (!found)
7701 intel_hdmi_init(dev, HDMIB);
5eb08b69
ZW		 7702 if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
7703 intel_dp_init(dev, PCH_DP_B);
30ad48b7
ZW		 7704 }
7705
7706 if (I915_READ(HDMIC) & PORT_DETECTED)
7707 intel_hdmi_init(dev, HDMIC);
7708
7709 if (I915_READ(HDMID) & PORT_DETECTED)
7710 intel_hdmi_init(dev, HDMID);
7711
5eb08b69
ZW		 7712 if (I915_READ(PCH_DP_C) & DP_DETECTED)
7713 intel_dp_init(dev, PCH_DP_C);
7714
cb0953d7 7715 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5eb08b69
ZW		 7716 intel_dp_init(dev, PCH_DP_D);
7717
103a196f 7718 } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
27185ae1 7719 bool found = false;
7d57382e 7720
725e30ad 7721 if (I915_READ(SDVOB) & SDVO_DETECTED) {
b01f2c3a 7722 DRM_DEBUG_KMS("probing SDVOB\n");
725e30ad 7723 found = intel_sdvo_init(dev, SDVOB);
b01f2c3a
JB		 7724 if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
7725 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
725e30ad 7726 intel_hdmi_init(dev, SDVOB);
b01f2c3a 7727 }
27185ae1 7728
b01f2c3a
JB		 7729 if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
7730 DRM_DEBUG_KMS("probing DP_B\n");
a4fc5ed6 7731 intel_dp_init(dev, DP_B);
b01f2c3a 7732 }
725e30ad 7733 }
13520b05
KH		 7734
7735 /* Before G4X SDVOC doesn't have its own detect register */
13520b05 7736
b01f2c3a
JB		 7737 if (I915_READ(SDVOB) & SDVO_DETECTED) {
7738 DRM_DEBUG_KMS("probing SDVOC\n");
725e30ad 7739 found = intel_sdvo_init(dev, SDVOC);
b01f2c3a 7740 }
27185ae1
ML		 7741
7742 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
7743
b01f2c3a
JB		 7744 if (SUPPORTS_INTEGRATED_HDMI(dev)) {
7745 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
725e30ad 7746 intel_hdmi_init(dev, SDVOC);
b01f2c3a
JB		 7747 }
7748 if (SUPPORTS_INTEGRATED_DP(dev)) {
7749 DRM_DEBUG_KMS("probing DP_C\n");
a4fc5ed6 7750 intel_dp_init(dev, DP_C);
b01f2c3a 7751 }
725e30ad 7752 }
27185ae1 7753
b01f2c3a
JB		 7754 if (SUPPORTS_INTEGRATED_DP(dev) &&
7755 (I915_READ(DP_D) & DP_DETECTED)) {
7756 DRM_DEBUG_KMS("probing DP_D\n");
a4fc5ed6 7757 intel_dp_init(dev, DP_D);
b01f2c3a 7758 }
bad720ff 7759 } else if (IS_GEN2(dev))
79e53945
JB		 7760 intel_dvo_init(dev);
7761
103a196f 7762 if (SUPPORTS_TV(dev))
79e53945
JB		 7763 intel_tv_init(dev);
7764
4ef69c7a
CW		 7765 list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7766 encoder->base.possible_crtcs = encoder->crtc_mask;
7767 encoder->base.possible_clones =
7768 intel_encoder_clones(dev, encoder->clone_mask);
79e53945 7769 }
47356eb6 7770
2c7111db
CW		 7771 /* disable all the possible outputs/crtcs before entering KMS mode */
7772 drm_helper_disable_unused_functions(dev);
9fb526db
KP		 7773
7774 if (HAS_PCH_SPLIT(dev))
7775 ironlake_init_pch_refclk(dev);
79e53945
JB		 7776}
7777
7778static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
7779{
7780 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
79e53945
JB		 7781
7782 drm_framebuffer_cleanup(fb);
05394f39 7783 drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
79e53945
JB		 7784
7785 kfree(intel_fb);
7786}
7787
7788static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
05394f39 7789 struct drm_file *file,
79e53945
JB		 7790 unsigned int *handle)
7791{
7792 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
05394f39 7793 struct drm_i915_gem_object *obj = intel_fb->obj;
79e53945 7794
05394f39 7795 return drm_gem_handle_create(file, &obj->base, handle);
79e53945
JB		 7796}
7797
7798static const struct drm_framebuffer_funcs intel_fb_funcs = {
7799 .destroy = intel_user_framebuffer_destroy,
7800 .create_handle = intel_user_framebuffer_create_handle,
7801};
7802
38651674
DA		 7803int intel_framebuffer_init(struct drm_device *dev,
7804 struct intel_framebuffer *intel_fb,
308e5bcb 7805 struct drm_mode_fb_cmd2 *mode_cmd,
05394f39 7806 struct drm_i915_gem_object *obj)
79e53945 7807{
79e53945
JB		 7808 int ret;
7809
05394f39 7810 if (obj->tiling_mode == I915_TILING_Y)
57cd6508
CW		 7811 return -EINVAL;
7812
308e5bcb 7813 if (mode_cmd->pitches[0] & 63)
57cd6508
CW		 7814 return -EINVAL;
7815
308e5bcb 7816 switch (mode_cmd->pixel_format) {
04b3924d
VS		 7817 case DRM_FORMAT_RGB332:
7818 case DRM_FORMAT_RGB565:
7819 case DRM_FORMAT_XRGB8888:
7820 case DRM_FORMAT_ARGB8888:
7821 case DRM_FORMAT_XRGB2101010:
7822 case DRM_FORMAT_ARGB2101010:
308e5bcb 7823 /* RGB formats are common across chipsets */
b5626747 7824 break;
04b3924d
VS		 7825 case DRM_FORMAT_YUYV:
7826 case DRM_FORMAT_UYVY:
7827 case DRM_FORMAT_YVYU:
7828 case DRM_FORMAT_VYUY:
57cd6508
CW		 7829 break;
7830 default:
308e5bcb 7831 DRM_ERROR("unsupported pixel format\n");
57cd6508
CW		 7832 return -EINVAL;
7833 }
7834
79e53945
JB		 7835 ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
7836 if (ret) {
7837 DRM_ERROR("framebuffer init failed %d\n", ret);
7838 return ret;
7839 }
7840
7841 drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
79e53945 7842 intel_fb->obj = obj;
79e53945
JB		 7843 return 0;
7844}
7845
79e53945
JB		 7846static struct drm_framebuffer *
7847intel_user_framebuffer_create(struct drm_device *dev,
7848 struct drm_file *filp,
308e5bcb 7849 struct drm_mode_fb_cmd2 *mode_cmd)
79e53945 7850{
05394f39 7851 struct drm_i915_gem_object *obj;
79e53945 7852
308e5bcb
JB		 7853 obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
7854 mode_cmd->handles[0]));
c8725226 7855 if (&obj->base == NULL)
cce13ff7 7856 return ERR_PTR(-ENOENT);
79e53945 7857
d2dff872 7858 return intel_framebuffer_create(dev, mode_cmd, obj);
79e53945
JB		 7859}
7860
79e53945 7861static const struct drm_mode_config_funcs intel_mode_funcs = {
79e53945 7862 .fb_create = intel_user_framebuffer_create,
eb1f8e4f 7863 .output_poll_changed = intel_fb_output_poll_changed,
79e53945
JB		 7864};
7865
05394f39 7866static struct drm_i915_gem_object *
aa40d6bb 7867intel_alloc_context_page(struct drm_device *dev)
9ea8d059 7868{
05394f39 7869 struct drm_i915_gem_object *ctx;
9ea8d059
CW		 7870 int ret;
7871
2c34b850
BW		 7872 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
7873
aa40d6bb
ZN		 7874 ctx = i915_gem_alloc_object(dev, 4096);
7875 if (!ctx) {
9ea8d059
CW		 7876 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
7877 return NULL;
7878 }
7879
75e9e915 7880 ret = i915_gem_object_pin(ctx, 4096, true);
9ea8d059
CW		 7881 if (ret) {
7882 DRM_ERROR("failed to pin power context: %d\n", ret);
7883 goto err_unref;
7884 }
7885
aa40d6bb 7886 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
9ea8d059
CW		 7887 if (ret) {
7888 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
7889 goto err_unpin;
7890 }
9ea8d059 7891
aa40d6bb 7892 return ctx;
9ea8d059
CW		 7893
7894err_unpin:
aa40d6bb 7895 i915_gem_object_unpin(ctx);
9ea8d059 7896err_unref:
05394f39 7897 drm_gem_object_unreference(&ctx->base);
9ea8d059
CW		 7898 mutex_unlock(&dev->struct_mutex);
7899 return NULL;
7900}
7901
7648fa99
JB		 7902bool ironlake_set_drps(struct drm_device *dev, u8 val)
7903{
7904 struct drm_i915_private *dev_priv = dev->dev_private;
7905 u16 rgvswctl;
7906
7907 rgvswctl = I915_READ16(MEMSWCTL);
7908 if (rgvswctl & MEMCTL_CMD_STS) {
7909 DRM_DEBUG("gpu busy, RCS change rejected\n");
7910 return false; /* still busy with another command */
7911 }
7912
7913 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
7914 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
7915 I915_WRITE16(MEMSWCTL, rgvswctl);
7916 POSTING_READ16(MEMSWCTL);
7917
7918 rgvswctl |= MEMCTL_CMD_STS;
7919 I915_WRITE16(MEMSWCTL, rgvswctl);
7920
7921 return true;
7922}
7923
f97108d1
JB		 7924void ironlake_enable_drps(struct drm_device *dev)
7925{
7926 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7927 u32 rgvmodectl = I915_READ(MEMMODECTL);
f97108d1 7928 u8 fmax, fmin, fstart, vstart;
f97108d1 7929
ea056c14
JB		 7930 /* Enable temp reporting */
7931 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
7932 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
7933
f97108d1
JB		 7934 /* 100ms RC evaluation intervals */
7935 I915_WRITE(RCUPEI, 100000);
7936 I915_WRITE(RCDNEI, 100000);
7937
7938 /* Set max/min thresholds to 90ms and 80ms respectively */
7939 I915_WRITE(RCBMAXAVG, 90000);
7940 I915_WRITE(RCBMINAVG, 80000);
7941
7942 I915_WRITE(MEMIHYST, 1);
7943
7944 /* Set up min, max, and cur for interrupt handling */
7945 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
7946 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
7947 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
7948 MEMMODE_FSTART_SHIFT;
7648fa99 7949
f97108d1
JB		 7950 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
7951 PXVFREQ_PX_SHIFT;
7952
80dbf4b7 7953 dev_priv->fmax = fmax; /* IPS callback will increase this */
7648fa99
JB		 7954 dev_priv->fstart = fstart;
7955
80dbf4b7 7956 dev_priv->max_delay = fstart;
f97108d1
JB		 7957 dev_priv->min_delay = fmin;
7958 dev_priv->cur_delay = fstart;
7959
80dbf4b7
JB		 7960 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
7961 fmax, fmin, fstart);
7648fa99 7962
f97108d1
JB		 7963 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
7964
7965 /*
7966 * Interrupts will be enabled in ironlake_irq_postinstall
7967 */
7968
7969 I915_WRITE(VIDSTART, vstart);
7970 POSTING_READ(VIDSTART);
7971
7972 rgvmodectl |= MEMMODE_SWMODE_EN;
7973 I915_WRITE(MEMMODECTL, rgvmodectl);
7974
481b6af3 7975 if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
913d8d11 7976 DRM_ERROR("stuck trying to change perf mode\n");
f97108d1
JB		 7977 msleep(1);
7978
7648fa99 7979 ironlake_set_drps(dev, fstart);
f97108d1 7980
7648fa99
JB		 7981 dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
7982 I915_READ(0x112e0);
7983 dev_priv->last_time1 = jiffies_to_msecs(jiffies);
7984 dev_priv->last_count2 = I915_READ(0x112f4);
7985 getrawmonotonic(&dev_priv->last_time2);
f97108d1
JB		 7986}
7987
7988void ironlake_disable_drps(struct drm_device *dev)
7989{
7990 struct drm_i915_private *dev_priv = dev->dev_private;
7648fa99 7991 u16 rgvswctl = I915_READ16(MEMSWCTL);
f97108d1
JB		 7992
7993 /* Ack interrupts, disable EFC interrupt */
7994 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
7995 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
7996 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
7997 I915_WRITE(DEIIR, DE_PCU_EVENT);
7998 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
7999
8000 /* Go back to the starting frequency */
7648fa99 8001 ironlake_set_drps(dev, dev_priv->fstart);
f97108d1
JB		 8002 msleep(1);
8003 rgvswctl |= MEMCTL_CMD_STS;
8004 I915_WRITE(MEMSWCTL, rgvswctl);
8005 msleep(1);
8006
8007}
8008
3b8d8d91
JB		 8009void gen6_set_rps(struct drm_device *dev, u8 val)
8010{
8011 struct drm_i915_private *dev_priv = dev->dev_private;
8012 u32 swreq;
8013
8014 swreq = (val & 0x3ff) << 25;
8015 I915_WRITE(GEN6_RPNSWREQ, swreq);
8016}
8017
8018void gen6_disable_rps(struct drm_device *dev)
8019{
8020 struct drm_i915_private *dev_priv = dev->dev_private;
8021
8022 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
8023 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
8024 I915_WRITE(GEN6_PMIER, 0);
6fdd4d98
DV		 8025 /* Complete PM interrupt masking here doesn't race with the rps work
8026 * item again unmasking PM interrupts because that is using a different
8027 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
8028 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
4912d041
BW		 8029
8030 spin_lock_irq(&dev_priv->rps_lock);
8031 dev_priv->pm_iir = 0;
8032 spin_unlock_irq(&dev_priv->rps_lock);
8033
3b8d8d91
JB		 8034 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
8035}
8036
7648fa99
JB		 8037static unsigned long intel_pxfreq(u32 vidfreq)
8038{
8039 unsigned long freq;
8040 int div = (vidfreq & 0x3f0000) >> 16;
8041 int post = (vidfreq & 0x3000) >> 12;
8042 int pre = (vidfreq & 0x7);
8043
8044 if (!pre)
8045 return 0;
8046
8047 freq = ((div * 133333) / ((1<<post) * pre));
8048
8049 return freq;
8050}
8051
8052void intel_init_emon(struct drm_device *dev)
8053{
8054 struct drm_i915_private *dev_priv = dev->dev_private;
8055 u32 lcfuse;
8056 u8 pxw[16];
8057 int i;
8058
8059 /* Disable to program */
8060 I915_WRITE(ECR, 0);
8061 POSTING_READ(ECR);
8062
8063 /* Program energy weights for various events */
8064 I915_WRITE(SDEW, 0x15040d00);
8065 I915_WRITE(CSIEW0, 0x007f0000);
8066 I915_WRITE(CSIEW1, 0x1e220004);
8067 I915_WRITE(CSIEW2, 0x04000004);
8068
8069 for (i = 0; i < 5; i++)
8070 I915_WRITE(PEW + (i * 4), 0);
8071 for (i = 0; i < 3; i++)
8072 I915_WRITE(DEW + (i * 4), 0);
8073
8074 /* Program P-state weights to account for frequency power adjustment */
8075 for (i = 0; i < 16; i++) {
8076 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
8077 unsigned long freq = intel_pxfreq(pxvidfreq);
8078 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
8079 PXVFREQ_PX_SHIFT;
8080 unsigned long val;
8081
8082 val = vid * vid;
8083 val *= (freq / 1000);
8084 val *= 255;
8085 val /= (127*127*900);
8086 if (val > 0xff)
8087 DRM_ERROR("bad pxval: %ld\n", val);
8088 pxw[i] = val;
8089 }
8090 /* Render standby states get 0 weight */
8091 pxw[14] = 0;
8092 pxw[15] = 0;
8093
8094 for (i = 0; i < 4; i++) {
8095 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
8096 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
8097 I915_WRITE(PXW + (i * 4), val);
8098 }
8099
8100 /* Adjust magic regs to magic values (more experimental results) */
8101 I915_WRITE(OGW0, 0);
8102 I915_WRITE(OGW1, 0);
8103 I915_WRITE(EG0, 0x00007f00);
8104 I915_WRITE(EG1, 0x0000000e);
8105 I915_WRITE(EG2, 0x000e0000);
8106 I915_WRITE(EG3, 0x68000300);
8107 I915_WRITE(EG4, 0x42000000);
8108 I915_WRITE(EG5, 0x00140031);
8109 I915_WRITE(EG6, 0);
8110 I915_WRITE(EG7, 0);
8111
8112 for (i = 0; i < 8; i++)
8113 I915_WRITE(PXWL + (i * 4), 0);
8114
8115 /* Enable PMON + select events */
8116 I915_WRITE(ECR, 0x80000019);
8117
8118 lcfuse = I915_READ(LCFUSE02);
8119
8120 dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
8121}
8122
c0f372b3
KP		 8123static bool intel_enable_rc6(struct drm_device *dev)
8124{
8125 /*
8126 * Respect the kernel parameter if it is set
8127 */
8128 if (i915_enable_rc6 >= 0)
8129 return i915_enable_rc6;
8130
8131 /*
8132 * Disable RC6 on Ironlake
8133 */
8134 if (INTEL_INFO(dev)->gen == 5)
8135 return 0;
8136
8137 /*
371de6e4 8138 * Disable rc6 on Sandybridge
c0f372b3
KP		 8139 */
8140 if (INTEL_INFO(dev)->gen == 6) {
371de6e4
KP		 8141 DRM_DEBUG_DRIVER("Sandybridge: RC6 disabled\n");
8142 return 0;
c0f372b3
KP		 8143 }
8144 DRM_DEBUG_DRIVER("RC6 enabled\n");
8145 return 1;
8146}
8147
3b8d8d91 8148void gen6_enable_rps(struct drm_i915_private *dev_priv)
8fd26859 8149{
a6044e23
JB		 8150 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
8151 u32 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
7df8721b 8152 u32 pcu_mbox, rc6_mask = 0;
a6044e23 8153 int cur_freq, min_freq, max_freq;
8fd26859
CW		 8154 int i;
8155
8156 /* Here begins a magic sequence of register writes to enable
8157 * auto-downclocking.
8158 *
8159 * Perhaps there might be some value in exposing these to
8160 * userspace...
8161 */
8162 I915_WRITE(GEN6_RC_STATE, 0);
d1ebd816 8163 mutex_lock(&dev_priv->dev->struct_mutex);
fcca7926 8164 gen6_gt_force_wake_get(dev_priv);
8fd26859 8165
3b8d8d91 8166 /* disable the counters and set deterministic thresholds */
8fd26859
CW		 8167 I915_WRITE(GEN6_RC_CONTROL, 0);
8168
8169 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
8170 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
8171 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
8172 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
8173 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
8174
8175 for (i = 0; i < I915_NUM_RINGS; i++)
8176 I915_WRITE(RING_MAX_IDLE(dev_priv->ring[i].mmio_base), 10);
8177
8178 I915_WRITE(GEN6_RC_SLEEP, 0);
8179 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
8180 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
8181 I915_WRITE(GEN6_RC6p_THRESHOLD, 100000);
8182 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
8183
c0f372b3 8184 if (intel_enable_rc6(dev_priv->dev))
7df8721b
JB		 8185 rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
8186 GEN6_RC_CTL_RC6_ENABLE;
8187
8fd26859 8188 I915_WRITE(GEN6_RC_CONTROL,
7df8721b 8189 rc6_mask |
9c3d2f7f 8190 GEN6_RC_CTL_EI_MODE(1) |
8fd26859
CW		 8191 GEN6_RC_CTL_HW_ENABLE);
8192
3b8d8d91 8193 I915_WRITE(GEN6_RPNSWREQ,
8fd26859
CW		 8194 GEN6_FREQUENCY(10) |
8195 GEN6_OFFSET(0) |
8196 GEN6_AGGRESSIVE_TURBO);
8197 I915_WRITE(GEN6_RC_VIDEO_FREQ,
8198 GEN6_FREQUENCY(12));
8199
8200 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
8201 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
8202 18 << 24 |
8203 6 << 16);
ccab5c82
JB		 8204 I915_WRITE(GEN6_RP_UP_THRESHOLD, 10000);
8205 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 1000000);
8fd26859 8206 I915_WRITE(GEN6_RP_UP_EI, 100000);
ccab5c82 8207 I915_WRITE(GEN6_RP_DOWN_EI, 5000000);
8fd26859
CW		 8208 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
8209 I915_WRITE(GEN6_RP_CONTROL,
8210 GEN6_RP_MEDIA_TURBO |
6ed55ee7 8211 GEN6_RP_MEDIA_HW_MODE |
8fd26859
CW		 8212 GEN6_RP_MEDIA_IS_GFX |
8213 GEN6_RP_ENABLE |
ccab5c82
JB		 8214 GEN6_RP_UP_BUSY_AVG |
8215 GEN6_RP_DOWN_IDLE_CONT);
8fd26859
CW		 8216
8217 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8218 500))
8219 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8220
8221 I915_WRITE(GEN6_PCODE_DATA, 0);
8222 I915_WRITE(GEN6_PCODE_MAILBOX,
8223 GEN6_PCODE_READY |
8224 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8225 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8226 500))
8227 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8228
a6044e23
JB		 8229 min_freq = (rp_state_cap & 0xff0000) >> 16;
8230 max_freq = rp_state_cap & 0xff;
8231 cur_freq = (gt_perf_status & 0xff00) >> 8;
8232
8233 /* Check for overclock support */
8234 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8235 500))
8236 DRM_ERROR("timeout waiting for pcode mailbox to become idle\n");
8237 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_READ_OC_PARAMS);
8238 pcu_mbox = I915_READ(GEN6_PCODE_DATA);
8239 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
8240 500))
8241 DRM_ERROR("timeout waiting for pcode mailbox to finish\n");
8242 if (pcu_mbox & (1<<31)) { /* OC supported */
8243 max_freq = pcu_mbox & 0xff;
e281fcaa 8244 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max to %dMHz\n", pcu_mbox * 50);
a6044e23
JB		 8245 }
8246
8247 /* In units of 100MHz */
8248 dev_priv->max_delay = max_freq;
8249 dev_priv->min_delay = min_freq;
8250 dev_priv->cur_delay = cur_freq;
8251
8fd26859
CW		 8252 /* requires MSI enabled */
8253 I915_WRITE(GEN6_PMIER,
8254 GEN6_PM_MBOX_EVENT |
8255 GEN6_PM_THERMAL_EVENT |
8256 GEN6_PM_RP_DOWN_TIMEOUT |
8257 GEN6_PM_RP_UP_THRESHOLD |
8258 GEN6_PM_RP_DOWN_THRESHOLD |
8259 GEN6_PM_RP_UP_EI_EXPIRED |
8260 GEN6_PM_RP_DOWN_EI_EXPIRED);
4912d041
BW		 8261 spin_lock_irq(&dev_priv->rps_lock);
8262 WARN_ON(dev_priv->pm_iir != 0);
3b8d8d91 8263 I915_WRITE(GEN6_PMIMR, 0);
4912d041 8264 spin_unlock_irq(&dev_priv->rps_lock);
3b8d8d91
JB		 8265 /* enable all PM interrupts */
8266 I915_WRITE(GEN6_PMINTRMSK, 0);
8fd26859 8267
fcca7926 8268 gen6_gt_force_wake_put(dev_priv);
d1ebd816 8269 mutex_unlock(&dev_priv->dev->struct_mutex);
8fd26859
CW		 8270}
8271
23b2f8bb
JB		 8272void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
8273{
8274 int min_freq = 15;
8275 int gpu_freq, ia_freq, max_ia_freq;
8276 int scaling_factor = 180;
8277
8278 max_ia_freq = cpufreq_quick_get_max(0);
8279 /*
8280 * Default to measured freq if none found, PCU will ensure we don't go
8281 * over
8282 */
8283 if (!max_ia_freq)
8284 max_ia_freq = tsc_khz;
8285
8286 /* Convert from kHz to MHz */
8287 max_ia_freq /= 1000;
8288
8289 mutex_lock(&dev_priv->dev->struct_mutex);
8290
8291 /*
8292 * For each potential GPU frequency, load a ring frequency we'd like
8293 * to use for memory access. We do this by specifying the IA frequency
8294 * the PCU should use as a reference to determine the ring frequency.
8295 */
8296 for (gpu_freq = dev_priv->max_delay; gpu_freq >= dev_priv->min_delay;
8297 gpu_freq--) {
8298 int diff = dev_priv->max_delay - gpu_freq;
8299
8300 /*
8301 * For GPU frequencies less than 750MHz, just use the lowest
8302 * ring freq.
8303 */
8304 if (gpu_freq < min_freq)
8305 ia_freq = 800;
8306 else
8307 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
8308 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
8309
8310 I915_WRITE(GEN6_PCODE_DATA,
8311 (ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT) |
8312 gpu_freq);
8313 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY |
8314 GEN6_PCODE_WRITE_MIN_FREQ_TABLE);
8315 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) &
8316 GEN6_PCODE_READY) == 0, 10)) {
8317 DRM_ERROR("pcode write of freq table timed out\n");
8318 continue;
8319 }
8320 }
8321
8322 mutex_unlock(&dev_priv->dev->struct_mutex);
8323}
8324
6067aaea
JB		 8325static void ironlake_init_clock_gating(struct drm_device *dev)
8326{
8327 struct drm_i915_private *dev_priv = dev->dev_private;
8328 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8329
8330 /* Required for FBC */
8331 dspclk_gate |= DPFCUNIT_CLOCK_GATE_DISABLE |
8332 DPFCRUNIT_CLOCK_GATE_DISABLE |
8333 DPFDUNIT_CLOCK_GATE_DISABLE;
8334 /* Required for CxSR */
8335 dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
8336
8337 I915_WRITE(PCH_3DCGDIS0,
8338 MARIUNIT_CLOCK_GATE_DISABLE |
8339 SVSMUNIT_CLOCK_GATE_DISABLE);
8340 I915_WRITE(PCH_3DCGDIS1,
8341 VFMUNIT_CLOCK_GATE_DISABLE);
8342
8343 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
8344
6067aaea
JB		 8345 /*
8346 * According to the spec the following bits should be set in
8347 * order to enable memory self-refresh
8348 * The bit 22/21 of 0x42004
8349 * The bit 5 of 0x42020
8350 * The bit 15 of 0x45000
8351 */
8352 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8353 (I915_READ(ILK_DISPLAY_CHICKEN2) |
8354 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
8355 I915_WRITE(ILK_DSPCLK_GATE,
8356 (I915_READ(ILK_DSPCLK_GATE) |
8357 ILK_DPARB_CLK_GATE));
8358 I915_WRITE(DISP_ARB_CTL,
8359 (I915_READ(DISP_ARB_CTL) |
8360 DISP_FBC_WM_DIS));
8361 I915_WRITE(WM3_LP_ILK, 0);
8362 I915_WRITE(WM2_LP_ILK, 0);
8363 I915_WRITE(WM1_LP_ILK, 0);
8364
8365 /*
8366 * Based on the document from hardware guys the following bits
8367 * should be set unconditionally in order to enable FBC.
8368 * The bit 22 of 0x42000
8369 * The bit 22 of 0x42004
8370 * The bit 7,8,9 of 0x42020.
8371 */
8372 if (IS_IRONLAKE_M(dev)) {
8373 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8374 I915_READ(ILK_DISPLAY_CHICKEN1) |
8375 ILK_FBCQ_DIS);
8376 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8377 I915_READ(ILK_DISPLAY_CHICKEN2) |
8378 ILK_DPARB_GATE);
8379 I915_WRITE(ILK_DSPCLK_GATE,
8380 I915_READ(ILK_DSPCLK_GATE) |
8381 ILK_DPFC_DIS1 |
8382 ILK_DPFC_DIS2 |
8383 ILK_CLK_FBC);
8384 }
8385
8386 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8387 I915_READ(ILK_DISPLAY_CHICKEN2) |
8388 ILK_ELPIN_409_SELECT);
8389 I915_WRITE(_3D_CHICKEN2,
8390 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
8391 _3D_CHICKEN2_WM_READ_PIPELINED);
8fd26859
CW		 8392}
8393
6067aaea 8394static void gen6_init_clock_gating(struct drm_device *dev)
652c393a
JB		 8395{
8396 struct drm_i915_private *dev_priv = dev->dev_private;
9db4a9c7 8397 int pipe;
6067aaea
JB		 8398 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
8399
8400 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
652c393a 8401
6067aaea
JB		 8402 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8403 I915_READ(ILK_DISPLAY_CHICKEN2) |
8404 ILK_ELPIN_409_SELECT);
8956c8bb 8405
6067aaea
JB		 8406 I915_WRITE(WM3_LP_ILK, 0);
8407 I915_WRITE(WM2_LP_ILK, 0);
8408 I915_WRITE(WM1_LP_ILK, 0);
652c393a 8409
406478dc
EA		 8410 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
8411 * gating disable must be set. Failure to set it results in
8412 * flickering pixels due to Z write ordering failures after
8413 * some amount of runtime in the Mesa "fire" demo, and Unigine
8414 * Sanctuary and Tropics, and apparently anything else with
8415 * alpha test or pixel discard.
9ca1d10d
EA		 8416 *
8417 * According to the spec, bit 11 (RCCUNIT) must also be set,
8418 * but we didn't debug actual testcases to find it out.
406478dc 8419 */
9ca1d10d
EA		 8420 I915_WRITE(GEN6_UCGCTL2,
8421 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
8422 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
406478dc 8423
652c393a 8424 /*
6067aaea
JB		 8425 * According to the spec the following bits should be
8426 * set in order to enable memory self-refresh and fbc:
8427 * The bit21 and bit22 of 0x42000
8428 * The bit21 and bit22 of 0x42004
8429 * The bit5 and bit7 of 0x42020
8430 * The bit14 of 0x70180
8431 * The bit14 of 0x71180
652c393a 8432 */
6067aaea
JB		 8433 I915_WRITE(ILK_DISPLAY_CHICKEN1,
8434 I915_READ(ILK_DISPLAY_CHICKEN1) |
8435 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
8436 I915_WRITE(ILK_DISPLAY_CHICKEN2,
8437 I915_READ(ILK_DISPLAY_CHICKEN2) |
8438 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
8439 I915_WRITE(ILK_DSPCLK_GATE,
8440 I915_READ(ILK_DSPCLK_GATE) |
8441 ILK_DPARB_CLK_GATE |
8442 ILK_DPFD_CLK_GATE);
8956c8bb 8443
d74362c9 8444 for_each_pipe(pipe) {
6067aaea
JB		 8445 I915_WRITE(DSPCNTR(pipe),
8446 I915_READ(DSPCNTR(pipe)) |
8447 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 8448 intel_flush_display_plane(dev_priv, pipe);
8449 }
6067aaea 8450}
8956c8bb 8451
28963a3e
JB		 8452static void ivybridge_init_clock_gating(struct drm_device *dev)
8453{
8454 struct drm_i915_private *dev_priv = dev->dev_private;
8455 int pipe;
8456 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
7f8a8569 8457
28963a3e 8458 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
382b0936 8459
28963a3e
JB		 8460 I915_WRITE(WM3_LP_ILK, 0);
8461 I915_WRITE(WM2_LP_ILK, 0);
8462 I915_WRITE(WM1_LP_ILK, 0);
de6e2eaf 8463
28963a3e 8464 I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
67e92af0 8465
116ac8d2
EA		 8466 I915_WRITE(IVB_CHICKEN3,
8467 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
8468 CHICKEN3_DGMG_DONE_FIX_DISABLE);
8469
d74362c9 8470 for_each_pipe(pipe) {
28963a3e
JB		 8471 I915_WRITE(DSPCNTR(pipe),
8472 I915_READ(DSPCNTR(pipe)) |
8473 DISPPLANE_TRICKLE_FEED_DISABLE);
d74362c9
KP		 8474 intel_flush_display_plane(dev_priv, pipe);
8475 }
28963a3e
JB		 8476}
8477
6067aaea
JB		 8478static void g4x_init_clock_gating(struct drm_device *dev)
8479{
8480 struct drm_i915_private *dev_priv = dev->dev_private;
8481 uint32_t dspclk_gate;
8fd26859 8482
6067aaea
JB		 8483 I915_WRITE(RENCLK_GATE_D1, 0);
8484 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
8485 GS_UNIT_CLOCK_GATE_DISABLE |
8486 CL_UNIT_CLOCK_GATE_DISABLE);
8487 I915_WRITE(RAMCLK_GATE_D, 0);
8488 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
8489 OVRUNIT_CLOCK_GATE_DISABLE |
8490 OVCUNIT_CLOCK_GATE_DISABLE;
8491 if (IS_GM45(dev))
8492 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
8493 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
8494}
1398261a 8495
6067aaea
JB		 8496static void crestline_init_clock_gating(struct drm_device *dev)
8497{
8498 struct drm_i915_private *dev_priv = dev->dev_private;
652c393a 8499
6067aaea
JB		 8500 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
8501 I915_WRITE(RENCLK_GATE_D2, 0);
8502 I915_WRITE(DSPCLK_GATE_D, 0);
8503 I915_WRITE(RAMCLK_GATE_D, 0);
8504 I915_WRITE16(DEUC, 0);
8505}
652c393a 8506
6067aaea
JB		 8507static void broadwater_init_clock_gating(struct drm_device *dev)
8508{
8509 struct drm_i915_private *dev_priv = dev->dev_private;
8510
8511 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
8512 I965_RCC_CLOCK_GATE_DISABLE |
8513 I965_RCPB_CLOCK_GATE_DISABLE |
8514 I965_ISC_CLOCK_GATE_DISABLE |
8515 I965_FBC_CLOCK_GATE_DISABLE);
8516 I915_WRITE(RENCLK_GATE_D2, 0);
8517}
8518
8519static void gen3_init_clock_gating(struct drm_device *dev)
8520{
8521 struct drm_i915_private *dev_priv = dev->dev_private;
8522 u32 dstate = I915_READ(D_STATE);
8523
8524 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
8525 DSTATE_DOT_CLOCK_GATING;
8526 I915_WRITE(D_STATE, dstate);
8527}
8528
8529static void i85x_init_clock_gating(struct drm_device *dev)
8530{
8531 struct drm_i915_private *dev_priv = dev->dev_private;
8532
8533 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
8534}
8535
8536static void i830_init_clock_gating(struct drm_device *dev)
8537{
8538 struct drm_i915_private *dev_priv = dev->dev_private;
8539
8540 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
652c393a
JB		 8541}
8542
645c62a5
JB		 8543static void ibx_init_clock_gating(struct drm_device *dev)
8544{
8545 struct drm_i915_private *dev_priv = dev->dev_private;
8546
8547 /*
8548 * On Ibex Peak and Cougar Point, we need to disable clock
8549 * gating for the panel power sequencer or it will fail to
8550 * start up when no ports are active.
8551 */
8552 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8553}
8554
8555static void cpt_init_clock_gating(struct drm_device *dev)
8556{
8557 struct drm_i915_private *dev_priv = dev->dev_private;
3bcf603f 8558 int pipe;
645c62a5
JB		 8559
8560 /*
8561 * On Ibex Peak and Cougar Point, we need to disable clock
8562 * gating for the panel power sequencer or it will fail to
8563 * start up when no ports are active.
8564 */
8565 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
8566 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
8567 DPLS_EDP_PPS_FIX_DIS);
3bcf603f
JB		 8568 /* Without this, mode sets may fail silently on FDI */
8569 for_each_pipe(pipe)
8570 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_AUTOTRAIN_GEN_STALL_DIS);
652c393a
JB		 8571}
8572
ac668088 8573static void ironlake_teardown_rc6(struct drm_device *dev)
0cdab21f
CW		 8574{
8575 struct drm_i915_private *dev_priv = dev->dev_private;
8576
8577 if (dev_priv->renderctx) {
ac668088
CW		 8578 i915_gem_object_unpin(dev_priv->renderctx);
8579 drm_gem_object_unreference(&dev_priv->renderctx->base);
0cdab21f
CW		 8580 dev_priv->renderctx = NULL;
8581 }
8582
8583 if (dev_priv->pwrctx) {
ac668088
CW		 8584 i915_gem_object_unpin(dev_priv->pwrctx);
8585 drm_gem_object_unreference(&dev_priv->pwrctx->base);
8586 dev_priv->pwrctx = NULL;
8587 }
8588}
8589
8590static void ironlake_disable_rc6(struct drm_device *dev)
8591{
8592 struct drm_i915_private *dev_priv = dev->dev_private;
8593
8594 if (I915_READ(PWRCTXA)) {
8595 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
8596 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
8597 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
8598 50);
0cdab21f
CW		 8599
8600 I915_WRITE(PWRCTXA, 0);
8601 POSTING_READ(PWRCTXA);
8602
ac668088
CW		 8603 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
8604 POSTING_READ(RSTDBYCTL);
0cdab21f 8605 }
ac668088 8606
99507307 8607 ironlake_teardown_rc6(dev);
0cdab21f
CW		 8608}
8609
ac668088 8610static int ironlake_setup_rc6(struct drm_device *dev)
d5bb081b
JB		 8611{
8612 struct drm_i915_private *dev_priv = dev->dev_private;
8613
ac668088
CW		 8614 if (dev_priv->renderctx == NULL)
8615 dev_priv->renderctx = intel_alloc_context_page(dev);
8616 if (!dev_priv->renderctx)
8617 return -ENOMEM;
8618
8619 if (dev_priv->pwrctx == NULL)
8620 dev_priv->pwrctx = intel_alloc_context_page(dev);
8621 if (!dev_priv->pwrctx) {
8622 ironlake_teardown_rc6(dev);
8623 return -ENOMEM;
8624 }
8625
8626 return 0;
d5bb081b
JB		 8627}
8628
8629void ironlake_enable_rc6(struct drm_device *dev)
8630{
8631 struct drm_i915_private *dev_priv = dev->dev_private;
8632 int ret;
8633
ac668088
CW		 8634 /* rc6 disabled by default due to repeated reports of hanging during
8635 * boot and resume.
8636 */
c0f372b3 8637 if (!intel_enable_rc6(dev))
ac668088
CW		 8638 return;
8639
2c34b850 8640 mutex_lock(&dev->struct_mutex);
ac668088 8641 ret = ironlake_setup_rc6(dev);
2c34b850
BW		 8642 if (ret) {
8643 mutex_unlock(&dev->struct_mutex);
ac668088 8644 return;
2c34b850 8645 }
ac668088 8646
d5bb081b
JB		 8647 /*
8648 * GPU can automatically power down the render unit if given a page
8649 * to save state.
8650 */
8651 ret = BEGIN_LP_RING(6);
8652 if (ret) {
ac668088 8653 ironlake_teardown_rc6(dev);
2c34b850 8654 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8655 return;
8656 }
ac668088 8657
d5bb081b
JB		 8658 OUT_RING(MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
8659 OUT_RING(MI_SET_CONTEXT);
8660 OUT_RING(dev_priv->renderctx->gtt_offset |
8661 MI_MM_SPACE_GTT |
8662 MI_SAVE_EXT_STATE_EN |
8663 MI_RESTORE_EXT_STATE_EN |
8664 MI_RESTORE_INHIBIT);
8665 OUT_RING(MI_SUSPEND_FLUSH);
8666 OUT_RING(MI_NOOP);
8667 OUT_RING(MI_FLUSH);
8668 ADVANCE_LP_RING();
8669
4a246cfc
BW		 8670 /*
8671 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
8672 * does an implicit flush, combined with MI_FLUSH above, it should be
8673 * safe to assume that renderctx is valid
8674 */
8675 ret = intel_wait_ring_idle(LP_RING(dev_priv));
8676 if (ret) {
8677 DRM_ERROR("failed to enable ironlake power power savings\n");
8678 ironlake_teardown_rc6(dev);
8679 mutex_unlock(&dev->struct_mutex);
8680 return;
8681 }
8682
d5bb081b
JB		 8683 I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN);
8684 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2c34b850 8685 mutex_unlock(&dev->struct_mutex);
d5bb081b
JB		 8686}
8687
645c62a5
JB		 8688void intel_init_clock_gating(struct drm_device *dev)
8689{
8690 struct drm_i915_private *dev_priv = dev->dev_private;
8691
8692 dev_priv->display.init_clock_gating(dev);
8693
8694 if (dev_priv->display.init_pch_clock_gating)
8695 dev_priv->display.init_pch_clock_gating(dev);
8696}
ac668088 8697
e70236a8
JB		 8698/* Set up chip specific display functions */
8699static void intel_init_display(struct drm_device *dev)
8700{
8701 struct drm_i915_private *dev_priv = dev->dev_private;
8702
8703 /* We always want a DPMS function */
f564048e 8704 if (HAS_PCH_SPLIT(dev)) {
f2b115e6 8705 dev_priv->display.dpms = ironlake_crtc_dpms;
f564048e 8706 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
17638cd6 8707 dev_priv->display.update_plane = ironlake_update_plane;
f564048e 8708 } else {
e70236a8 8709 dev_priv->display.dpms = i9xx_crtc_dpms;
f564048e 8710 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
17638cd6 8711 dev_priv->display.update_plane = i9xx_update_plane;
f564048e 8712 }
e70236a8 8713
ee5382ae 8714 if (I915_HAS_FBC(dev)) {
9c04f015 8715 if (HAS_PCH_SPLIT(dev)) {
b52eb4dc
ZY		 8716 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
8717 dev_priv->display.enable_fbc = ironlake_enable_fbc;
8718 dev_priv->display.disable_fbc = ironlake_disable_fbc;
8719 } else if (IS_GM45(dev)) {
74dff282
JB		 8720 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
8721 dev_priv->display.enable_fbc = g4x_enable_fbc;
8722 dev_priv->display.disable_fbc = g4x_disable_fbc;
a6c45cf0 8723 } else if (IS_CRESTLINE(dev)) {
e70236a8
JB		 8724 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
8725 dev_priv->display.enable_fbc = i8xx_enable_fbc;
8726 dev_priv->display.disable_fbc = i8xx_disable_fbc;
8727 }
74dff282 8728 /* 855GM needs testing */
e70236a8
JB		 8729 }
8730
8731 /* Returns the core display clock speed */
0206e353 8732 if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
e70236a8
JB		 8733 dev_priv->display.get_display_clock_speed =
8734 i945_get_display_clock_speed;
8735 else if (IS_I915G(dev))
8736 dev_priv->display.get_display_clock_speed =
8737 i915_get_display_clock_speed;
f2b115e6 8738 else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
e70236a8
JB		 8739 dev_priv->display.get_display_clock_speed =
8740 i9xx_misc_get_display_clock_speed;
8741 else if (IS_I915GM(dev))
8742 dev_priv->display.get_display_clock_speed =
8743 i915gm_get_display_clock_speed;
8744 else if (IS_I865G(dev))
8745 dev_priv->display.get_display_clock_speed =
8746 i865_get_display_clock_speed;
f0f8a9ce 8747 else if (IS_I85X(dev))
e70236a8
JB		 8748 dev_priv->display.get_display_clock_speed =
8749 i855_get_display_clock_speed;
8750 else /* 852, 830 */
8751 dev_priv->display.get_display_clock_speed =
8752 i830_get_display_clock_speed;
8753
8754 /* For FIFO watermark updates */
7f8a8569 8755 if (HAS_PCH_SPLIT(dev)) {
8d715f00
KP		 8756 dev_priv->display.force_wake_get = __gen6_gt_force_wake_get;
8757 dev_priv->display.force_wake_put = __gen6_gt_force_wake_put;
8758
8759 /* IVB configs may use multi-threaded forcewake */
8760 if (IS_IVYBRIDGE(dev)) {
8761 u32 ecobus;
8762
c7dffff7
KP		 8763 /* A small trick here - if the bios hasn't configured MT forcewake,
8764 * and if the device is in RC6, then force_wake_mt_get will not wake
8765 * the device and the ECOBUS read will return zero. Which will be
8766 * (correctly) interpreted by the test below as MT forcewake being
8767 * disabled.
8768 */
8d715f00
KP		 8769 mutex_lock(&dev->struct_mutex);
8770 __gen6_gt_force_wake_mt_get(dev_priv);
c7dffff7 8771 ecobus = I915_READ_NOTRACE(ECOBUS);
8d715f00
KP		 8772 __gen6_gt_force_wake_mt_put(dev_priv);
8773 mutex_unlock(&dev->struct_mutex);
8774
8775 if (ecobus & FORCEWAKE_MT_ENABLE) {
8776 DRM_DEBUG_KMS("Using MT version of forcewake\n");
8777 dev_priv->display.force_wake_get =
8778 __gen6_gt_force_wake_mt_get;
8779 dev_priv->display.force_wake_put =
8780 __gen6_gt_force_wake_mt_put;
8781 }
8782 }
8783
645c62a5
JB		 8784 if (HAS_PCH_IBX(dev))
8785 dev_priv->display.init_pch_clock_gating = ibx_init_clock_gating;
8786 else if (HAS_PCH_CPT(dev))
8787 dev_priv->display.init_pch_clock_gating = cpt_init_clock_gating;
8788
f00a3ddf 8789 if (IS_GEN5(dev)) {
7f8a8569
ZW		 8790 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
8791 dev_priv->display.update_wm = ironlake_update_wm;
8792 else {
8793 DRM_DEBUG_KMS("Failed to get proper latency. "
8794 "Disable CxSR\n");
8795 dev_priv->display.update_wm = NULL;
1398261a 8796 }
674cf967 8797 dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
6067aaea 8798 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
e0dac65e 8799 dev_priv->display.write_eld = ironlake_write_eld;
1398261a
YL		 8800 } else if (IS_GEN6(dev)) {
8801 if (SNB_READ_WM0_LATENCY()) {
8802 dev_priv->display.update_wm = sandybridge_update_wm;
b840d907 8803 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
1398261a
YL		 8804 } else {
8805 DRM_DEBUG_KMS("Failed to read display plane latency. "
8806 "Disable CxSR\n");
8807 dev_priv->display.update_wm = NULL;
7f8a8569 8808 }
674cf967 8809 dev_priv->display.fdi_link_train = gen6_fdi_link_train;
6067aaea 8810 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
e0dac65e 8811 dev_priv->display.write_eld = ironlake_write_eld;
357555c0
JB		 8812 } else if (IS_IVYBRIDGE(dev)) {
8813 /* FIXME: detect B0+ stepping and use auto training */
8814 dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
fe100d4d
JB		 8815 if (SNB_READ_WM0_LATENCY()) {
8816 dev_priv->display.update_wm = sandybridge_update_wm;
b840d907 8817 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
fe100d4d
JB		 8818 } else {
8819 DRM_DEBUG_KMS("Failed to read display plane latency. "
8820 "Disable CxSR\n");
8821 dev_priv->display.update_wm = NULL;
8822 }
28963a3e 8823 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
e0dac65e 8824 dev_priv->display.write_eld = ironlake_write_eld;
7f8a8569
ZW		 8825 } else
8826 dev_priv->display.update_wm = NULL;
8827 } else if (IS_PINEVIEW(dev)) {
d4294342 8828 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
95534263 8829 dev_priv->is_ddr3,
d4294342
ZY		 8830 dev_priv->fsb_freq,
8831 dev_priv->mem_freq)) {
8832 DRM_INFO("failed to find known CxSR latency "
95534263 8833 "(found ddr%s fsb freq %d, mem freq %d), "
d4294342 8834 "disabling CxSR\n",
0206e353 8835 (dev_priv->is_ddr3 == 1) ? "3" : "2",
d4294342
ZY		 8836 dev_priv->fsb_freq, dev_priv->mem_freq);
8837 /* Disable CxSR and never update its watermark again */
8838 pineview_disable_cxsr(dev);
8839 dev_priv->display.update_wm = NULL;
8840 } else
8841 dev_priv->display.update_wm = pineview_update_wm;
95e0ee92 8842 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6067aaea 8843 } else if (IS_G4X(dev)) {
e0dac65e 8844 dev_priv->display.write_eld = g4x_write_eld;
e70236a8 8845 dev_priv->display.update_wm = g4x_update_wm;
6067aaea
JB		 8846 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
8847 } else if (IS_GEN4(dev)) {
e70236a8 8848 dev_priv->display.update_wm = i965_update_wm;
6067aaea
JB		 8849 if (IS_CRESTLINE(dev))
8850 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
8851 else if (IS_BROADWATER(dev))
8852 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
8853 } else if (IS_GEN3(dev)) {
e70236a8
JB		 8854 dev_priv->display.update_wm = i9xx_update_wm;
8855 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6067aaea
JB		 8856 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
8857 } else if (IS_I865G(dev)) {
8858 dev_priv->display.update_wm = i830_update_wm;
8859 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
8860 dev_priv->display.get_fifo_size = i830_get_fifo_size;
8f4695ed
AJ		 8861 } else if (IS_I85X(dev)) {
8862 dev_priv->display.update_wm = i9xx_update_wm;
8863 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
6067aaea 8864 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
e70236a8 8865 } else {
8f4695ed 8866 dev_priv->display.update_wm = i830_update_wm;
6067aaea 8867 dev_priv->display.init_clock_gating = i830_init_clock_gating;
8f4695ed 8868 if (IS_845G(dev))
e70236a8
JB		 8869 dev_priv->display.get_fifo_size = i845_get_fifo_size;
8870 else
8871 dev_priv->display.get_fifo_size = i830_get_fifo_size;
e70236a8 8872 }
8c9f3aaf
JB		 8873
8874 /* Default just returns -ENODEV to indicate unsupported */
8875 dev_priv->display.queue_flip = intel_default_queue_flip;
8876
8877 switch (INTEL_INFO(dev)->gen) {
8878 case 2:
8879 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8880 break;
8881
8882 case 3:
8883 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8884 break;
8885
8886 case 4:
8887 case 5:
8888 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8889 break;
8890
8891 case 6:
8892 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8893 break;
7c9017e5
JB		 8894 case 7:
8895 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8896 break;
8c9f3aaf 8897 }
e70236a8
JB		 8898}
8899
b690e96c
JB		 8900/*
8901 * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8902 * resume, or other times. This quirk makes sure that's the case for
8903 * affected systems.
8904 */
0206e353 8905static void quirk_pipea_force(struct drm_device *dev)
b690e96c
JB		 8906{
8907 struct drm_i915_private *dev_priv = dev->dev_private;
8908
8909 dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8910 DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
8911}
8912
435793df
KP		 8913/*
8914 * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8915 */
8916static void quirk_ssc_force_disable(struct drm_device *dev)
8917{
8918 struct drm_i915_private *dev_priv = dev->dev_private;
8919 dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8920}
8921
b690e96c
JB		 8922struct intel_quirk {
8923 int device;
8924 int subsystem_vendor;
8925 int subsystem_device;
8926 void (*hook)(struct drm_device *dev);
8927};
8928
8929struct intel_quirk intel_quirks[] = {
8930 /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
8931 { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
8932 /* HP Mini needs pipe A force quirk (LP: #322104) */
0206e353 8933 { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
b690e96c
JB		 8934
8935 /* Thinkpad R31 needs pipe A force quirk */
8936 { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
8937 /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8938 { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8939
8940 /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
8941 { 0x3577, 0x1014, 0x0513, quirk_pipea_force },
8942 /* ThinkPad X40 needs pipe A force quirk */
8943
8944 /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8945 { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8946
8947 /* 855 & before need to leave pipe A & dpll A up */
8948 { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8949 { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
435793df
KP		 8950
8951 /* Lenovo U160 cannot use SSC on LVDS */
8952 { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
070d329a
MAS		 8953
8954 /* Sony Vaio Y cannot use SSC on LVDS */
8955 { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
b690e96c
JB		 8956};
8957
8958static void intel_init_quirks(struct drm_device *dev)
8959{
8960 struct pci_dev *d = dev->pdev;
8961 int i;
8962
8963 for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8964 struct intel_quirk *q = &intel_quirks[i];
8965
8966 if (d->device == q->device &&
8967 (d->subsystem_vendor == q->subsystem_vendor ||
8968 q->subsystem_vendor == PCI_ANY_ID) &&
8969 (d->subsystem_device == q->subsystem_device ||
8970 q->subsystem_device == PCI_ANY_ID))
8971 q->hook(dev);
8972 }
8973}
8974
9cce37f4
JB		 8975/* Disable the VGA plane that we never use */
8976static void i915_disable_vga(struct drm_device *dev)
8977{
8978 struct drm_i915_private *dev_priv = dev->dev_private;
8979 u8 sr1;
8980 u32 vga_reg;
8981
8982 if (HAS_PCH_SPLIT(dev))
8983 vga_reg = CPU_VGACNTRL;
8984 else
8985 vga_reg = VGACNTRL;
8986
8987 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8988 outb(1, VGA_SR_INDEX);
8989 sr1 = inb(VGA_SR_DATA);
8990 outb(sr1 | 1<<5, VGA_SR_DATA);
8991 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8992 udelay(300);
8993
8994 I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8995 POSTING_READ(vga_reg);
8996}
8997
79e53945
JB		 8998void intel_modeset_init(struct drm_device *dev)
8999{
652c393a 9000 struct drm_i915_private *dev_priv = dev->dev_private;
b840d907 9001 int i, ret;
79e53945
JB		 9002
9003 drm_mode_config_init(dev);
9004
9005 dev->mode_config.min_width = 0;
9006 dev->mode_config.min_height = 0;
9007
9008 dev->mode_config.funcs = (void *)&intel_mode_funcs;
9009
b690e96c
JB		 9010 intel_init_quirks(dev);
9011
e70236a8
JB		 9012 intel_init_display(dev);
9013
a6c45cf0
CW		 9014 if (IS_GEN2(dev)) {
9015 dev->mode_config.max_width = 2048;
9016 dev->mode_config.max_height = 2048;
9017 } else if (IS_GEN3(dev)) {
5e4d6fa7
KP		 9018 dev->mode_config.max_width = 4096;
9019 dev->mode_config.max_height = 4096;
79e53945 9020 } else {
a6c45cf0
CW		 9021 dev->mode_config.max_width = 8192;
9022 dev->mode_config.max_height = 8192;
79e53945 9023 }
35c3047a 9024 dev->mode_config.fb_base = dev->agp->base;
79e53945 9025
28c97730 9026 DRM_DEBUG_KMS("%d display pipe%s available.\n",
a3524f1b 9027 dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
79e53945 9028
a3524f1b 9029 for (i = 0; i < dev_priv->num_pipe; i++) {
79e53945 9030 intel_crtc_init(dev, i);
00c2064b
JB		 9031 ret = intel_plane_init(dev, i);
9032 if (ret)
9033 DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
79e53945
JB		 9034 }
9035
9cce37f4
JB		 9036 /* Just disable it once at startup */
9037 i915_disable_vga(dev);
79e53945 9038 intel_setup_outputs(dev);
652c393a 9039
645c62a5 9040 intel_init_clock_gating(dev);
9cce37f4 9041
7648fa99 9042 if (IS_IRONLAKE_M(dev)) {
f97108d1 9043 ironlake_enable_drps(dev);
7648fa99
JB		 9044 intel_init_emon(dev);
9045 }
f97108d1 9046
1c70c0ce 9047 if (IS_GEN6(dev) || IS_GEN7(dev)) {
3b8d8d91 9048 gen6_enable_rps(dev_priv);
23b2f8bb
JB		 9049 gen6_update_ring_freq(dev_priv);
9050 }
3b8d8d91 9051
652c393a
JB		 9052 INIT_WORK(&dev_priv->idle_work, intel_idle_update);
9053 setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
9054 (unsigned long)dev);
2c7111db
CW		 9055}
9056
9057void intel_modeset_gem_init(struct drm_device *dev)
9058{
9059 if (IS_IRONLAKE_M(dev))
9060 ironlake_enable_rc6(dev);
02e792fb
DV		 9061
9062 intel_setup_overlay(dev);
79e53945
JB		 9063}
9064
9065void intel_modeset_cleanup(struct drm_device *dev)
9066{
652c393a
JB		 9067 struct drm_i915_private *dev_priv = dev->dev_private;
9068 struct drm_crtc *crtc;
9069 struct intel_crtc *intel_crtc;
9070
f87ea761 9071 drm_kms_helper_poll_fini(dev);
652c393a
JB		 9072 mutex_lock(&dev->struct_mutex);
9073
723bfd70
JB		 9074 intel_unregister_dsm_handler();
9075
9076
652c393a
JB		 9077 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9078 /* Skip inactive CRTCs */
9079 if (!crtc->fb)
9080 continue;
9081
9082 intel_crtc = to_intel_crtc(crtc);
3dec0095 9083 intel_increase_pllclock(crtc);
652c393a
JB		 9084 }
9085
973d04f9 9086 intel_disable_fbc(dev);
e70236a8 9087
f97108d1
JB		 9088 if (IS_IRONLAKE_M(dev))
9089 ironlake_disable_drps(dev);
1c70c0ce 9090 if (IS_GEN6(dev) || IS_GEN7(dev))
3b8d8d91 9091 gen6_disable_rps(dev);
f97108d1 9092
d5bb081b
JB		 9093 if (IS_IRONLAKE_M(dev))
9094 ironlake_disable_rc6(dev);
0cdab21f 9095
69341a5e
KH		 9096 mutex_unlock(&dev->struct_mutex);
9097
6c0d9350
DV		 9098 /* Disable the irq before mode object teardown, for the irq might
9099 * enqueue unpin/hotplug work. */
9100 drm_irq_uninstall(dev);
9101 cancel_work_sync(&dev_priv->hotplug_work);
6fdd4d98 9102 cancel_work_sync(&dev_priv->rps_work);
6c0d9350 9103
1630fe75
CW		 9104 /* flush any delayed tasks or pending work */
9105 flush_scheduled_work();
9106
3dec0095
DV		 9107 /* Shut off idle work before the crtcs get freed. */
9108 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
9109 intel_crtc = to_intel_crtc(crtc);
9110 del_timer_sync(&intel_crtc->idle_timer);
9111 }
9112 del_timer_sync(&dev_priv->idle_timer);
9113 cancel_work_sync(&dev_priv->idle_work);
9114
79e53945
JB		 9115 drm_mode_config_cleanup(dev);
9116}
9117
f1c79df3
ZW		 9118/*
9119 * Return which encoder is currently attached for connector.
9120 */
df0e9248 9121struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
79e53945 9122{
df0e9248
CW		 9123 return &intel_attached_encoder(connector)->base;
9124}
f1c79df3 9125
df0e9248
CW		 9126void intel_connector_attach_encoder(struct intel_connector *connector,
9127 struct intel_encoder *encoder)
9128{
9129 connector->encoder = encoder;
9130 drm_mode_connector_attach_encoder(&connector->base,
9131 &encoder->base);
79e53945 9132}
28d52043
DA		 9133
9134/*
9135 * set vga decode state - true == enable VGA decode
9136 */
9137int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9138{
9139 struct drm_i915_private *dev_priv = dev->dev_private;
9140 u16 gmch_ctrl;
9141
9142 pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9143 if (state)
9144 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9145 else
9146 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9147 pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9148 return 0;
9149}
c4a1d9e4
CW		 9150
9151#ifdef CONFIG_DEBUG_FS
9152#include <linux/seq_file.h>
9153
9154struct intel_display_error_state {
9155 struct intel_cursor_error_state {
9156 u32 control;
9157 u32 position;
9158 u32 base;
9159 u32 size;
9160 } cursor[2];
9161
9162 struct intel_pipe_error_state {
9163 u32 conf;
9164 u32 source;
9165
9166 u32 htotal;
9167 u32 hblank;
9168 u32 hsync;
9169 u32 vtotal;
9170 u32 vblank;
9171 u32 vsync;
9172 } pipe[2];
9173
9174 struct intel_plane_error_state {
9175 u32 control;
9176 u32 stride;
9177 u32 size;
9178 u32 pos;
9179 u32 addr;
9180 u32 surface;
9181 u32 tile_offset;
9182 } plane[2];
9183};
9184
9185struct intel_display_error_state *
9186intel_display_capture_error_state(struct drm_device *dev)
9187{
0206e353 9188 drm_i915_private_t *dev_priv = dev->dev_private;
c4a1d9e4
CW		 9189 struct intel_display_error_state *error;
9190 int i;
9191
9192 error = kmalloc(sizeof(*error), GFP_ATOMIC);
9193 if (error == NULL)
9194 return NULL;
9195
9196 for (i = 0; i < 2; i++) {
9197 error->cursor[i].control = I915_READ(CURCNTR(i));
9198 error->cursor[i].position = I915_READ(CURPOS(i));
9199 error->cursor[i].base = I915_READ(CURBASE(i));
9200
9201 error->plane[i].control = I915_READ(DSPCNTR(i));
9202 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9203 error->plane[i].size = I915_READ(DSPSIZE(i));
0206e353 9204 error->plane[i].pos = I915_READ(DSPPOS(i));
c4a1d9e4
CW		 9205 error->plane[i].addr = I915_READ(DSPADDR(i));
9206 if (INTEL_INFO(dev)->gen >= 4) {
9207 error->plane[i].surface = I915_READ(DSPSURF(i));
9208 error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9209 }
9210
9211 error->pipe[i].conf = I915_READ(PIPECONF(i));
9212 error->pipe[i].source = I915_READ(PIPESRC(i));
9213 error->pipe[i].htotal = I915_READ(HTOTAL(i));
9214 error->pipe[i].hblank = I915_READ(HBLANK(i));
9215 error->pipe[i].hsync = I915_READ(HSYNC(i));
9216 error->pipe[i].vtotal = I915_READ(VTOTAL(i));
9217 error->pipe[i].vblank = I915_READ(VBLANK(i));
9218 error->pipe[i].vsync = I915_READ(VSYNC(i));
9219 }
9220
9221 return error;
9222}
9223
9224void
9225intel_display_print_error_state(struct seq_file *m,
9226 struct drm_device *dev,
9227 struct intel_display_error_state *error)
9228{
9229 int i;
9230
9231 for (i = 0; i < 2; i++) {
9232 seq_printf(m, "Pipe [%d]:\n", i);
9233 seq_printf(m, " CONF: %08x\n", error->pipe[i].conf);
9234 seq_printf(m, " SRC: %08x\n", error->pipe[i].source);
9235 seq_printf(m, " HTOTAL: %08x\n", error->pipe[i].htotal);
9236 seq_printf(m, " HBLANK: %08x\n", error->pipe[i].hblank);
9237 seq_printf(m, " HSYNC: %08x\n", error->pipe[i].hsync);
9238 seq_printf(m, " VTOTAL: %08x\n", error->pipe[i].vtotal);
9239 seq_printf(m, " VBLANK: %08x\n", error->pipe[i].vblank);
9240 seq_printf(m, " VSYNC: %08x\n", error->pipe[i].vsync);
9241
9242 seq_printf(m, "Plane [%d]:\n", i);
9243 seq_printf(m, " CNTR: %08x\n", error->plane[i].control);
9244 seq_printf(m, " STRIDE: %08x\n", error->plane[i].stride);
9245 seq_printf(m, " SIZE: %08x\n", error->plane[i].size);
9246 seq_printf(m, " POS: %08x\n", error->plane[i].pos);
9247 seq_printf(m, " ADDR: %08x\n", error->plane[i].addr);
9248 if (INTEL_INFO(dev)->gen >= 4) {
9249 seq_printf(m, " SURF: %08x\n", error->plane[i].surface);
9250 seq_printf(m, " TILEOFF: %08x\n", error->plane[i].tile_offset);
9251 }
9252
9253 seq_printf(m, "Cursor [%d]:\n", i);
9254 seq_printf(m, " CNTR: %08x\n", error->cursor[i].control);
9255 seq_printf(m, " POS: %08x\n", error->cursor[i].position);
9256 seq_printf(m, " BASE: %08x\n", error->cursor[i].base);
9257 }
9258}
9259#endif
Linux kernel - Deliverables
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